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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRTN_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DLRTN_BEHAVIORAL_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dlrtn (
Q ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_ms__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRTN_BEHAVIORAL_V |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 15:44:08 09/12/2015
// Design Name: 4:3 Encoder
// Module Name: C:/Users/adam/Documents/GitHub/Digital Systems/hw1problem1/encoder43TB.v
// Project Name: hw1problem1
////////////////////////////////////////////////////////////////////////////////
module encoder43TB;
reg A, B, C, D;
wire [2:0] Ygates, Yexpression, Ytable;
encoder43gates Encoder43Gates(A, B, C, D, Ygates[2], Ygates[1], Ygates[0]);
encoder43expression Encoder43Expression(A, B, C, D, Yexpression[2], Yexpression[1], Yexpression[0]);
encoder43table Encoder43Table(A, B, C, D, Ytable[2], Ytable[1], Ytable[0]);
initial fork
#0 A = 0;
#0 B = 0;
#0 C = 0;
#0 D = 0;
#1 A = 0;
#1 B = 0;
#1 C = 1;
#1 D = 0;
#2 A = 0;
#2 B = 0;
#2 C = 0;
#2 D = 1;
#3 A = 0;
#3 B = 0;
#3 C = 1;
#3 D = 1;
#4 A = 0;
#4 B = 1;
#4 C = 0;
#4 D = 0;
#5 A = 0;
#5 B = 1;
#5 C = 1;
#5 D = 0;
#6 A = 0;
#6 B = 1;
#6 C = 0;
#6 D = 1;
#7 A = 0;
#7 B = 1;
#7 C = 1;
#7 D = 1;
#8 A = 1;
#8 B = 0;
#8 C = 0;
#8 D = 0;
#9 A = 1;
#9 B = 0;
#9 C = 1;
#9 D = 0;
#10 A = 1;
#10 B = 0;
#10 C = 0;
#10 D = 1;
#11 A = 1;
#11 B = 0;
#11 C = 1;
#11 D = 1;
#12 A = 1;
#12 B = 1;
#12 C = 0;
#12 D = 0;
#13 A = 1;
#13 B = 1;
#13 C = 1;
#13 D = 0;
#14 A = 1;
#14 B = 1;
#14 C = 0;
#14 D = 1;
#15 A = 1;
#15 B = 1;
#15 C = 1;
#15 D = 1;
#16 $stop;
join
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Sep 18 13:00:14 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// c:/Projects/srio_test/srio_test/srio_test.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0_stub.v
// Design : fifo_generator_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
module fifo_generator_0(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
empty, rd_data_count, wr_data_count, prog_full, prog_empty)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[63:0],wr_en,rd_en,dout[63:0],full,empty,rd_data_count[8:0],wr_data_count[9:0],prog_full,prog_empty" */;
input rst;
input wr_clk;
input rd_clk;
input [63:0]din;
input wr_en;
input rd_en;
output [63:0]dout;
output full;
output empty;
output [8:0]rd_data_count;
output [9:0]wr_data_count;
output prog_full;
output prog_empty;
endmodule
|
// file: clk_wiz_v1_8.v
//
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1 32.024 0.000 50.0 271.037 265.971
// CLK_OUT2 16.012 0.000 50.0 322.832 265.971
// CLK_OUT3 8.006 0.000 50.0 365.304 265.971
// CLK_OUT4 64.048 0.000 50.0 224.987 265.971
//
//----------------------------------------------------------------------------
// Input Clock Input Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// primary 50.000 0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_wiz_v1_8,clk_wiz_v1_8,{component_name=clk_wiz_v1_8,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=4,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module clk_wiz_v1_8
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
output CLK_OUT4
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the PLL primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire locked_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkout4_unused;
wire clkout5_unused;
PLL_BASE
#(.BANDWIDTH ("OPTIMIZED"),
.CLK_FEEDBACK ("CLKFBOUT"),
.COMPENSATION ("SYSTEM_SYNCHRONOUS"),
.DIVCLK_DIVIDE (2),
.CLKFBOUT_MULT (41),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (32),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (64),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DIVIDE (128),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DIVIDE (16),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKIN_PERIOD (20.0),
.REF_JITTER (0.010))
pll_base_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKOUT0 (clkout0),
.CLKOUT1 (clkout1),
.CLKOUT2 (clkout2),
.CLKOUT3 (clkout3),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.LOCKED (locked_unused),
.RST (1'b0),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN (clkin1));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkout1));
BUFG clkout3_buf
(.O (CLK_OUT3),
.I (clkout2));
BUFG clkout4_buf
(.O (CLK_OUT4),
.I (clkout3));
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2019 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(* Evgeny Makarov, INRIA, 2007 *)
(************************************************************************)
(** This file defined the strong (course-of-value, well-founded) recursion
and proves its properties *)
Require Export NSub.
Ltac f_equiv' := repeat (repeat f_equiv; try intros ? ? ?; auto).
Module NStrongRecProp (Import N : NAxiomsRecSig').
Include NSubProp N.
Section StrongRecursion.
Variable A : Type.
Variable Aeq : relation A.
Variable Aeq_equiv : Equivalence Aeq.
(** [strong_rec] allows defining a recursive function [phi] given by
an equation [phi(n) = F(phi)(n)] where recursive calls to [phi]
in [F] are made on strictly lower numbers than [n].
For [strong_rec a F n]:
- Parameter [a:A] is a default value used internally, it has no
effect on the final result.
- Parameter [F:(N->A)->N->A] is the step function:
[F f n] should return [phi(n)] when [f] is a function
that coincide with [phi] for numbers strictly less than [n].
*)
Definition strong_rec (a : A) (f : (N.t -> A) -> N.t -> A) (n : N.t) : A :=
recursion (fun _ => a) (fun _ => f) (S n) n.
(** For convenience, we use in proofs an intermediate definition
between [recursion] and [strong_rec]. *)
Definition strong_rec0 (a : A) (f : (N.t -> A) -> N.t -> A) : N.t -> N.t -> A :=
recursion (fun _ => a) (fun _ => f).
Lemma strong_rec_alt : forall a f n,
strong_rec a f n = strong_rec0 a f (S n) n.
Proof.
reflexivity.
Qed.
Instance strong_rec0_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> N.eq ==> Aeq)
strong_rec0.
Proof.
unfold strong_rec0; f_equiv'.
Qed.
Instance strong_rec_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> Aeq) strong_rec.
Proof.
intros a a' Eaa' f f' Eff' n n' Enn'.
rewrite !strong_rec_alt; f_equiv'.
Qed.
Section FixPoint.
Variable f : (N.t -> A) -> N.t -> A.
Variable f_wd : Proper ((N.eq==>Aeq)==>N.eq==>Aeq) f.
Lemma strong_rec0_0 : forall a m,
(strong_rec0 a f 0 m) = a.
Proof.
intros. unfold strong_rec0. rewrite recursion_0; auto.
Qed.
Lemma strong_rec0_succ : forall a n m,
Aeq (strong_rec0 a f (S n) m) (f (strong_rec0 a f n) m).
Proof.
intros. unfold strong_rec0.
f_equiv.
rewrite recursion_succ; f_equiv'.
Qed.
Lemma strong_rec_0 : forall a,
Aeq (strong_rec a f 0) (f (fun _ => a) 0).
Proof.
intros. rewrite strong_rec_alt, strong_rec0_succ; f_equiv'.
rewrite strong_rec0_0. reflexivity.
Qed.
(* We need an assumption saying that for every n, the step function (f h n)
calls h only on the segment [0 ... n - 1]. This means that if h1 and h2
coincide on values < n, then (f h1 n) coincides with (f h2 n) *)
Hypothesis step_good :
forall (n : N.t) (h1 h2 : N.t -> A),
(forall m : N.t, m < n -> Aeq (h1 m) (h2 m)) -> Aeq (f h1 n) (f h2 n).
Lemma strong_rec0_more_steps : forall a k n m, m < n ->
Aeq (strong_rec0 a f n m) (strong_rec0 a f (n+k) m).
Proof.
intros a k n. pattern n.
apply induction; clear n.
intros n n' Hn; setoid_rewrite Hn; auto with *.
intros m Hm. destruct (nlt_0_r _ Hm).
intros n IH m Hm.
rewrite lt_succ_r in Hm.
rewrite add_succ_l.
rewrite 2 strong_rec0_succ.
apply step_good.
intros m' Hm'.
apply IH.
apply lt_le_trans with m; auto.
Qed.
Lemma strong_rec0_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec0 a f (S n) n) (f (fun n => strong_rec0 a f (S n) n) n).
Proof.
intros.
rewrite strong_rec0_succ.
apply step_good.
intros m Hm.
symmetry.
setoid_replace n with (S m + (n - S m)).
apply strong_rec0_more_steps.
apply lt_succ_diag_r.
rewrite add_comm.
symmetry.
apply sub_add.
rewrite le_succ_l; auto.
Qed.
Theorem strong_rec_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec a f n) (f (strong_rec a f) n).
Proof.
intros.
transitivity (f (fun n => strong_rec0 a f (S n) n) n).
rewrite strong_rec_alt.
apply strong_rec0_fixpoint.
f_equiv.
intros x x' Hx; rewrite strong_rec_alt, Hx; auto with *.
Qed.
(** NB: without the [step_good] hypothesis, we have proved that
[strong_rec a f 0] is [f (fun _ => a) 0]. Now we can prove
that the first argument of [f] is arbitrary in this case...
*)
Theorem strong_rec_0_any : forall (a : A)(any : N.t->A),
Aeq (strong_rec a f 0) (f any 0).
Proof.
intros.
rewrite strong_rec_fixpoint.
apply step_good.
intros m Hm. destruct (nlt_0_r _ Hm).
Qed.
(** ... and that first argument of [strong_rec] is always arbitrary. *)
Lemma strong_rec_any_fst_arg : forall a a' n,
Aeq (strong_rec a f n) (strong_rec a' f n).
Proof.
intros a a' n.
generalize (le_refl n).
set (k:=n) at -2. clearbody k. revert k. pattern n.
apply induction; clear n.
(* compat *)
intros n n' Hn. setoid_rewrite Hn; auto with *.
(* 0 *)
intros k Hk. rewrite le_0_r in Hk.
rewrite Hk, strong_rec_0. symmetry. apply strong_rec_0_any.
(* S *)
intros n IH k Hk.
rewrite 2 strong_rec_fixpoint.
apply step_good.
intros m Hm.
apply IH.
rewrite succ_le_mono.
apply le_trans with k; auto.
rewrite le_succ_l; auto.
Qed.
End FixPoint.
End StrongRecursion.
Arguments strong_rec [A] a f n.
End NStrongRecProp.
|
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
assign tx = rx; // TODO(#658): Remove this work-around
wire [8:0] addr;
wire [17:0] ram_out;
wire ram_in;
RAM_SHIFTER #(
.IO_WIDTH(16),
.ADDR_WIDTH(9),
.PHASE_SHIFT(3)
) shifter (
.clk(clk),
.in(sw),
.out(led),
.addr(addr),
.ram_out(| ram_out),
.ram_in(ram_in)
);
RAMB18E1 #(
.RAM_MODE("TDP"), // True dual-port mode (2x2 in/out ports)
.READ_WIDTH_A(18),
.WRITE_WIDTH_B(18),
.WRITE_MODE_B("WRITE_FIRST") // transparent write
) ram (
// read from A
.CLKARDCLK(clk), // shared clock
.ENARDEN(1'b1), // enable read
.REGCEAREGCE(1'b0), // disable clock to the output register (not using it)
.RSTRAMARSTRAM(1'b0), // don't reset output latch
.RSTREGARSTREG(1'b0), // don't reset output register
.ADDRARDADDR({~sw[0], addr, 4'b0}), // use upper 10 bits, lower 4 are zero
.WEA(4'h0), // disable writing from this half
.DIADI(16'h0000), // no input
.DIPADIP(2'h0), // no input
.DOADO(ram_out[15:0]), // 16 bit output
.DOPADOP(ram_out[17:16]), // 2 more output bits
// write to B
.CLKBWRCLK(clk), // shared clock
.ENBWREN(1'b1), // enable write
.REGCEB(1'b0), // disable clock to the output register (no output)
.RSTRAMB(1'b0), // don't reset the output latch
.RSTREGB(1'b0), // don't reset the output register
.ADDRBWRADDR({sw[0], addr, 4'b0}), // use upper 10 bits, lower 4 are zero
.DIBDI({16{ram_in}}), // 16 bit input
.DIPBDIP({2{ram_in}}), // 2 more input bits
.WEBWE(8'h03) // enable writing all 2 bytes-wide (16 bits)
);
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module controls 16x2 character LCD on the Altera DE2 Board. *
* *
******************************************************************************/
module nios_system_character_lcd_0 (
// Inputs
clk,
reset,
address,
chipselect,
read,
write,
writedata,
// Bidirectionals
LCD_DATA,
// Outputs
LCD_ON,
LCD_BLON,
LCD_EN,
LCD_RS,
LCD_RW,
readdata,
waitrequest
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CURSOR_ON = 1'b1;
parameter BLINKING_ON = 1'b0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input address;
input chipselect;
input read;
input write;
input [ 7: 0] writedata;
// Bidirectionals
inout [ 7: 0] LCD_DATA; // LCD Data bus 8 bits
// Outputs
output LCD_ON; // LCD Power ON/OFF
output LCD_BLON; // LCD Back Light ON/OFF
output LCD_EN; // LCD Enable
output LCD_RS; // LCD 0-Command/1-Data Select
output LCD_RW; // LCD 1-Read/0-Write Select
output [ 7: 0] readdata;
output waitrequest;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam LCD_STATE_0_IDLE = 3'h0,
LCD_STATE_1_INITIALIZE = 3'h1,
LCD_STATE_2_START_CHECK_BUSY = 3'h2,
LCD_STATE_3_CHECK_BUSY = 3'h3,
LCD_STATE_4_BEGIN_TRANSFER = 3'h4,
LCD_STATE_5_TRANSFER = 3'h5,
LCD_STATE_6_COMPLETE = 3'h6;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire transfer_complete;
wire done_initialization;
wire init_send_command;
wire [ 8: 0] init_command;
wire send_data;
wire [ 7: 0] data_received;
// Internal Registers
reg initialize_lcd_display;
reg [ 7: 0] data_to_send;
reg rs;
reg rw;
// State Machine Registers
reg [ 2: 0] ns_lcd_controller;
reg [ 2: 0] s_lcd_controller;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
s_lcd_controller <= LCD_STATE_0_IDLE;
else
s_lcd_controller <= ns_lcd_controller;
end
always @(*)
begin
// Defaults
ns_lcd_controller = LCD_STATE_0_IDLE;
case (s_lcd_controller)
LCD_STATE_0_IDLE:
begin
if (initialize_lcd_display)
ns_lcd_controller = LCD_STATE_1_INITIALIZE;
else if (chipselect)
ns_lcd_controller = LCD_STATE_2_START_CHECK_BUSY;
else
ns_lcd_controller = LCD_STATE_0_IDLE;
end
LCD_STATE_1_INITIALIZE:
begin
if (done_initialization)
ns_lcd_controller = LCD_STATE_6_COMPLETE;
else
ns_lcd_controller = LCD_STATE_1_INITIALIZE;
end
LCD_STATE_2_START_CHECK_BUSY:
begin
if (transfer_complete == 1'b0)
ns_lcd_controller = LCD_STATE_3_CHECK_BUSY;
else
ns_lcd_controller = LCD_STATE_2_START_CHECK_BUSY;
end
LCD_STATE_3_CHECK_BUSY:
begin
if ((transfer_complete) && (data_received[7]))
ns_lcd_controller = LCD_STATE_2_START_CHECK_BUSY;
else if ((transfer_complete) && (data_received[7] == 1'b0))
ns_lcd_controller = LCD_STATE_4_BEGIN_TRANSFER;
else
ns_lcd_controller = LCD_STATE_3_CHECK_BUSY;
end
LCD_STATE_4_BEGIN_TRANSFER:
begin
if (transfer_complete == 1'b0)
ns_lcd_controller = LCD_STATE_5_TRANSFER;
else
ns_lcd_controller = LCD_STATE_4_BEGIN_TRANSFER;
end
LCD_STATE_5_TRANSFER:
begin
if (transfer_complete)
ns_lcd_controller = LCD_STATE_6_COMPLETE;
else
ns_lcd_controller = LCD_STATE_5_TRANSFER;
end
LCD_STATE_6_COMPLETE:
begin
ns_lcd_controller = LCD_STATE_0_IDLE;
end
default:
begin
ns_lcd_controller = LCD_STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
initialize_lcd_display <= 1'b1;
else if (done_initialization)
initialize_lcd_display <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
data_to_send <= 8'h00;
else if (s_lcd_controller == LCD_STATE_1_INITIALIZE)
data_to_send <= init_command[7:0];
else if (s_lcd_controller == LCD_STATE_4_BEGIN_TRANSFER)
data_to_send <= writedata[7:0];
end
always @(posedge clk)
begin
if (reset)
rs <= 1'b0;
else if (s_lcd_controller == LCD_STATE_1_INITIALIZE)
rs <= init_command[8];
else if (s_lcd_controller == LCD_STATE_2_START_CHECK_BUSY)
rs <= 1'b0;
else if (s_lcd_controller == LCD_STATE_4_BEGIN_TRANSFER)
rs <= address;
end
always @(posedge clk)
begin
if (reset)
rw <= 1'b0;
else if (s_lcd_controller == LCD_STATE_1_INITIALIZE)
rw <= 1'b0;
else if (s_lcd_controller == LCD_STATE_2_START_CHECK_BUSY)
rw <= 1'b1;
else if (s_lcd_controller == LCD_STATE_4_BEGIN_TRANSFER)
rw <= ~write;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign readdata = data_received;
assign waitrequest = chipselect & (s_lcd_controller != LCD_STATE_6_COMPLETE);
// Internal Assignments
assign send_data =
(s_lcd_controller == LCD_STATE_1_INITIALIZE) ? init_send_command :
(s_lcd_controller == LCD_STATE_3_CHECK_BUSY) ? 1'b1 :
(s_lcd_controller == LCD_STATE_5_TRANSFER) ? 1'b1 : 1'b0;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_character_lcd_communication Char_LCD_Comm (
// Inputs
.clk (clk),
.reset (reset),
.data_in (data_to_send),
.enable (send_data),
.rs (rs),
.rw (rw),
.display_on (1'b1),
.back_light_on (1'b1),
// Bidirectionals
.LCD_DATA (LCD_DATA),
// Outputs
.LCD_ON (LCD_ON),
.LCD_BLON (LCD_BLON),
.LCD_EN (LCD_EN),
.LCD_RS (LCD_RS),
.LCD_RW (LCD_RW),
.data_out (data_received),
.transfer_complete (transfer_complete)
);
altera_up_character_lcd_initialization Char_LCD_Init (
// Inputs
.clk (clk),
.reset (reset),
.initialize_LCD_display (initialize_lcd_display),
.command_was_sent (transfer_complete),
// Bidirectionals
// Outputs
.done_initialization (done_initialization),
.send_command (init_send_command),
.the_command (init_command)
);
defparam
Char_LCD_Init.CURSOR_ON = CURSOR_ON,
Char_LCD_Init.BLINKING_ON = BLINKING_ON;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / D Flip-Flop with Clock Enable and Asynchronous Clear
// /___/ /\ Filename : FDCE.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 08/24/10 - Initial version.
// 10/20/10 - remove unused pin line from table.
// 11/01/11 - Disable timing check when set reset active (CR632017)
// 12/08/11 - add MSGON and XON attributes (CR636891)
// 01/16/12 - 640813 - add MSGON and XON functionality
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module FDCE #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
parameter MSGON = "TRUE",
parameter XON = "TRUE",
`endif
parameter [0:0] INIT = 1'b0,
parameter [0:0] IS_CLR_INVERTED = 1'b0,
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D_INVERTED = 1'b0
)(
output Q,
input C,
input CE,
input CLR,
input D
);
reg [0:0] IS_CLR_INVERTED_REG = IS_CLR_INVERTED;
reg [0:0] IS_C_INVERTED_REG = IS_C_INVERTED;
reg [0:0] IS_D_INVERTED_REG = IS_D_INVERTED;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING
wire D_dly, C_dly, CE_dly;
wire CLR_dly;
`endif
wire CLR_in;
`ifdef XIL_TIMING
assign CLR_in = (CLR_dly ^ IS_CLR_INVERTED_REG) && (CLR !== 1'bz);
`else
assign CLR_in = (CLR ^ IS_CLR_INVERTED_REG) && (CLR !== 1'bz);
`endif
// begin behavioral model
reg Q_out;
assign #100 Q = Q_out;
always @(glblGSR or CLR_in)
if (glblGSR)
assign Q_out = INIT;
else if (CLR_in === 1'b1)
assign Q_out = 1'b0;
else if (CLR_in === 1'bx)
assign Q_out = 1'bx;
else
deassign Q_out;
`ifdef XIL_TIMING
generate
if (IS_C_INVERTED == 1'b0) begin : generate_block1
always @(posedge C_dly or posedge CLR_in)
if (CLR_in || (CLR === 1'bx && Q_out == 1'b0))
Q_out <= 1'b0;
else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG))))
Q_out <= D_dly ^ IS_D_INVERTED_REG;
end else begin : generate_block1
always @(negedge C_dly or posedge CLR_in)
if (CLR_in || (CLR === 1'bx && Q_out == 1'b0))
Q_out <= 1'b0;
else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG))))
Q_out <= D_dly ^ IS_D_INVERTED_REG;
end
endgenerate
`else
generate
if (IS_C_INVERTED == 1'b0) begin : generate_block1
always @(posedge C or posedge CLR_in)
if (CLR_in || (CLR === 1'bx && Q_out == 1'b0))
Q_out <= 1'b0;
else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG))))
Q_out <= D ^ IS_D_INVERTED_REG;
end else begin : generate_block1
always @(negedge C or posedge CLR_in)
if (CLR_in || (CLR === 1'bx && Q_out == 1'b0))
Q_out <= 1'b0;
else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG))))
Q_out <= D ^ IS_D_INVERTED_REG;
end
endgenerate
`endif
`ifdef XIL_TIMING
reg notifier;
wire notifier1;
`endif
`ifdef XIL_TIMING
wire ngsr, in_out;
wire nrst;
wire in_clk_enable, in_clk_enable_p, in_clk_enable_n;
wire ce_clk_enable, ce_clk_enable_p, ce_clk_enable_n;
reg init_enable = 1'b1;
wire rst_clk_enable, rst_clk_enable_p, rst_clk_enable_n;
`endif
`ifdef XIL_TIMING
not (ngsr, glblGSR);
xor (in_out, D_dly, IS_D_INVERTED_REG, Q_out);
not (nrst, (CLR_dly ^ IS_CLR_INVERTED_REG) && (CLR !== 1'bz));
and (in_clk_enable, ngsr, nrst, CE || (CE === 1'bz));
and (ce_clk_enable, ngsr, nrst, in_out);
and (rst_clk_enable, ngsr, CE || (CE === 1'bz), D ^ IS_D_INVERTED_REG);
always @(negedge nrst) init_enable = (MSGON =="TRUE") && ~glblGSR && (Q_out ^ INIT);
assign notifier1 = (XON == "FALSE") ? 1'bx : notifier;
assign ce_clk_enable_n = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b1);
assign in_clk_enable_n = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b1);
assign rst_clk_enable_n = (MSGON =="TRUE") && rst_clk_enable && (IS_C_INVERTED == 1'b1);
assign ce_clk_enable_p = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b0);
assign in_clk_enable_p = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b0);
assign rst_clk_enable_p = (MSGON =="TRUE") && rst_clk_enable && (IS_C_INVERTED == 1'b0);
`endif
// end behavioral model
`ifdef XIL_TIMING
specify
(C => Q) = (100:100:100, 100:100:100);
(negedge CLR => (Q +: 0)) = (0:0:0, 0:0:0);
(posedge CLR => (Q +: 0)) = (0:0:0, 0:0:0);
(CLR => Q) = (0:0:0, 0:0:0);
$period (negedge C &&& CE, 0:0:0, notifier);
$period (posedge C &&& CE, 0:0:0, notifier);
$recrem (negedge CLR, negedge C, 0:0:0, 0:0:0, notifier,rst_clk_enable_n,rst_clk_enable_n,CLR_dly, C_dly);
$recrem (negedge CLR, posedge C, 0:0:0, 0:0:0, notifier,rst_clk_enable_p,rst_clk_enable_p,CLR_dly, C_dly);
$recrem (posedge CLR, negedge C, 0:0:0, 0:0:0, notifier,rst_clk_enable_n,rst_clk_enable_n,CLR_dly, C_dly);
$recrem (posedge CLR, posedge C, 0:0:0, 0:0:0, notifier,rst_clk_enable_p,rst_clk_enable_p,CLR_dly, C_dly);
$setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly);
$setuphold (negedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly);
$setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly);
$setuphold (negedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly);
$setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly);
$setuphold (posedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly);
$setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly);
$setuphold (posedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly);
$width (negedge C &&& CE, 0:0:0, 0, notifier);
$width (negedge CLR &&& init_enable, 0:0:0, 0, notifier);
$width (posedge C &&& CE, 0:0:0, 0, notifier);
$width (posedge CLR &&& init_enable, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:07:56 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n544, n545, n546,
n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, n557,
n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, n568,
n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579,
n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590,
n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601,
n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612,
n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, n623,
n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634,
n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645,
n646, n647, n648, n649, n650, n651, n652, n653, n654, n655, n656,
n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667,
n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678,
n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689,
n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700,
n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722,
n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733,
n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744,
n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, n755,
n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766,
n767, n768, n769, n770, n771, n772, n773, n774, n775, n776, n777,
n778, n779, n780, n781, n782, n783, n784, n785, n786, n787, n788,
n789, n790, n791, n792, n793, n794, n795, n796, n797, n798, n799,
n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810,
n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821,
n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832,
n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843,
n844, n845, n846, n847, n848, n850, n851, n852, n853, n854, n855,
n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, n866,
n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, n877,
n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888,
n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899,
n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910,
n911, n912, n913, n914, n915, n916, n917, n918, n919, n920, n921,
n922, n923, n924, n925, n926, n927, n928, n929, n930, n931, n932,
n933, n934, n935, n936, n937, n938, n939, n940, n941, n942, n943,
n944, n945, n946, n947, n948, n949, n950, n951, n952,
DP_OP_15J10_123_2691_n8, DP_OP_15J10_123_2691_n7,
DP_OP_15J10_123_2691_n6, DP_OP_15J10_123_2691_n5,
DP_OP_15J10_123_2691_n4, intadd_4_B_9_, intadd_4_B_8_, intadd_4_B_7_,
intadd_4_B_6_, intadd_4_B_5_, intadd_4_B_4_, intadd_4_B_3_,
intadd_4_B_2_, intadd_4_B_1_, intadd_4_B_0_, intadd_4_CI,
intadd_4_SUM_9_, intadd_4_SUM_8_, intadd_4_SUM_7_, intadd_4_SUM_6_,
intadd_4_SUM_5_, intadd_4_SUM_4_, intadd_4_SUM_3_, intadd_4_SUM_2_,
intadd_4_SUM_1_, intadd_4_SUM_0_, intadd_4_n10, intadd_4_n9,
intadd_4_n8, intadd_4_n7, intadd_4_n6, intadd_4_n5, intadd_4_n4,
intadd_4_n3, intadd_4_n2, intadd_4_n1, n953, n954, n955, n956, n957,
n958, n959, n960, n961, n962, n963, n964, n965, n966, n967, n968,
n969, n970, n971, n972, n973, n974, n975, n976, n977, n978, n979,
n980, n981, n982, n983, n984, n985, n986, n987, n988, n989, n990,
n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001,
n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011,
n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021,
n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031,
n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041,
n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051,
n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061,
n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071,
n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081,
n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091,
n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101,
n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111,
n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121,
n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131,
n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141,
n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151,
n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1161, n1162,
n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172,
n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182,
n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192,
n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202,
n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212,
n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222,
n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232,
n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242,
n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252,
n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262,
n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272,
n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282,
n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292,
n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302,
n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312,
n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322,
n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332,
n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343,
n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353,
n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363,
n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373,
n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383,
n1384, n1385, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394,
n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404,
n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414,
n1415, n1416, n1417, n1419, n1420, n1421, n1422, n1423, n1424, n1425,
n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435,
n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445,
n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455,
n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465,
n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475,
n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1514, n1515, n1516,
n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526,
n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536,
n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546,
n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556,
n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566,
n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576,
n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586,
n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596,
n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606,
n1607, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617,
n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627,
n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637,
n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647,
n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657,
n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667,
n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677,
n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687,
n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697,
n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707,
n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717,
n1718, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728,
n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738,
n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748,
n1749, n1751, n1752, n1753;
wire [1:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:1] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:1] Raw_mant_NRM_SWR;
wire [25:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n947), .CK(clk), .RN(n1722), .QN(
n963) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n911), .CK(clk), .RN(n1723), .Q(
intAS) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n910), .CK(clk), .RN(n1726), .Q(
left_right_SHT2) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1735),
.Q(ready) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n846), .CK(clk), .RN(n1727),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n845), .CK(clk), .RN(n1728),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n844), .CK(clk), .RN(n1724),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n843), .CK(clk), .RN(n1741),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n842), .CK(clk), .RN(n1735), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n841), .CK(clk), .RN(n1731), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n840), .CK(clk), .RN(n1734), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n839), .CK(clk), .RN(n1733), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n838), .CK(clk), .RN(n973), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n837), .CK(clk), .RN(n1747), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n836), .CK(clk), .RN(n1736), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n835), .CK(clk), .RN(n1748), .Q(
final_result_ieee[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n834), .CK(clk), .RN(n1727), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n833), .CK(clk), .RN(n1725), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n832), .CK(clk), .RN(n1725), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n831), .CK(clk), .RN(n1735), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n830), .CK(clk), .RN(n1724), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n829), .CK(clk), .RN(n1729), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n828), .CK(clk), .RN(n1727), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n827), .CK(clk), .RN(n1725), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n826), .CK(clk), .RN(n1015), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n825), .CK(clk), .RN(n1723), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n824), .CK(clk), .RN(n1726), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n823), .CK(clk), .RN(n1727), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n822), .CK(clk), .RN(n1721), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n821), .CK(clk), .RN(n1722), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n820), .CK(clk), .RN(n1730), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n819), .CK(clk), .RN(n1723), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n818), .CK(clk), .RN(n1743), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n817), .CK(clk), .RN(n1726), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n816), .CK(clk), .RN(n1721), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n815), .CK(clk), .RN(n1722), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n814), .CK(clk), .RN(n1730), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n813), .CK(clk), .RN(n1733), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n812), .CK(clk), .RN(n1734), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n807), .CK(clk), .RN(n1731), .QN(n964)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n806), .CK(clk), .RN(n1732), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n805), .CK(clk), .RN(n1748), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n804), .CK(clk), .RN(n1736), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n803), .CK(clk), .RN(n1747), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n802), .CK(clk), .RN(n1731), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n801), .CK(clk), .RN(n1732), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n800), .CK(clk), .RN(n1748), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n799), .CK(clk), .RN(n1736), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n797), .CK(clk), .RN(n1747), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n796), .CK(clk), .RN(n1732), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n794), .CK(clk), .RN(n1748), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n793), .CK(clk), .RN(n1736), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n791), .CK(clk), .RN(n1747), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n790), .CK(clk), .RN(n973), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n788), .CK(clk), .RN(n1728), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n787), .CK(clk), .RN(n973), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n785), .CK(clk), .RN(n973), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n784), .CK(clk), .RN(n1013), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n782), .CK(clk), .RN(n1743), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n781), .CK(clk), .RN(n1742), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n779), .CK(clk), .RN(n1722), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n778), .CK(clk), .RN(n1743), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n776), .CK(clk), .RN(n1742), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n775), .CK(clk), .RN(n1742), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n773), .CK(clk), .RN(n1726), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n772), .CK(clk), .RN(n1729), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n770), .CK(clk), .RN(n1742), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n769), .CK(clk), .RN(n1741), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n767), .CK(clk), .RN(n1742), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n766), .CK(clk), .RN(n1728), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n764), .CK(clk), .RN(n1734), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n763), .CK(clk), .RN(n1731), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n761), .CK(clk), .RN(n1732), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n760), .CK(clk), .RN(n1748), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n758), .CK(clk), .RN(n1736), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n757), .CK(clk), .RN(n1747), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n755), .CK(clk), .RN(n973), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n754), .CK(clk), .RN(n1733), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n752), .CK(clk), .RN(n1732), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n751), .CK(clk), .RN(n1747), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n749), .CK(clk), .RN(n1736), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n748), .CK(clk), .RN(n1731), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n746), .CK(clk), .RN(n973), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n745), .CK(clk), .RN(n1733), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n743), .CK(clk), .RN(n1734), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n742), .CK(clk), .RN(n1748), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n740), .CK(clk), .RN(n1748), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n739), .CK(clk), .RN(n1737), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n737), .CK(clk), .RN(n1734), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n736), .CK(clk), .RN(n1734), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n734), .CK(clk), .RN(n1013), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n733), .CK(clk), .RN(n1726), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n731), .CK(clk), .RN(n1742), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n1729), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n729), .CK(clk), .RN(n1746), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n728), .CK(clk), .RN(n1726), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n726), .CK(clk), .RN(n1748), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n725), .CK(clk), .RN(n1742), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n724), .CK(clk), .RN(n1748), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n723), .CK(clk), .RN(n1723), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n721), .CK(clk), .RN(n1737), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n720), .CK(clk), .RN(n1740), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n719), .CK(clk), .RN(n1014), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n718), .CK(clk), .RN(n1731), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n716), .CK(clk), .RN(n1013), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n715), .CK(clk), .RN(n1740), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n714), .CK(clk), .RN(n1735), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n713), .CK(clk), .RN(n1728), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n711), .CK(clk), .RN(n1735), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n710), .CK(clk), .RN(n1728), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n709), .CK(clk), .RN(n1735), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n708), .CK(clk), .RN(n1728), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n706), .CK(clk), .RN(n1735), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n705), .CK(clk), .RN(n1728), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n704), .CK(clk), .RN(n1735), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n703), .CK(clk), .RN(n1728), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n701), .CK(clk), .RN(n1735), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n700), .CK(clk), .RN(n1728), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n699), .CK(clk), .RN(n1748), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n698), .CK(clk), .RN(n1736), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n696), .CK(clk), .RN(n1731), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n695), .CK(clk), .RN(n1747), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n694), .CK(clk), .RN(n1732), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n693), .CK(clk), .RN(n1748), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n691), .CK(clk), .RN(n1736), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n690), .CK(clk), .RN(n1747), .QN(
n965) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n689), .CK(clk), .RN(n973), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n687), .CK(clk), .RN(n1733), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n685), .CK(clk), .RN(n1737), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n683), .CK(clk), .RN(n1746), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n682), .CK(clk), .RN(n1737), .QN(
n971) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n681), .CK(clk), .RN(n1746), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n680), .CK(clk), .RN(n1737), .QN(
n972) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n679), .CK(clk), .RN(n1746), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n677), .CK(clk), .RN(n1746), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n675), .CK(clk), .RN(n1737), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n673), .CK(clk), .RN(n1738), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n672), .CK(clk), .RN(n1741), .QN(
n966) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n671), .CK(clk), .RN(n1738), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n669), .CK(clk), .RN(n1738), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n668), .CK(clk), .RN(n1738),
.QN(n967) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n667), .CK(clk), .RN(n1738), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n665), .CK(clk), .RN(n1738), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n664), .CK(clk), .RN(n1738),
.QN(n968) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n663), .CK(clk), .RN(n1738), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n661), .CK(clk), .RN(n1739), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n660), .CK(clk), .RN(n1739),
.QN(n969) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n659), .CK(clk), .RN(n1739), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n657), .CK(clk), .RN(n1739), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n655), .CK(clk), .RN(n1739), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n653), .CK(clk), .RN(n1739), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n652), .CK(clk), .RN(n1739),
.QN(n970) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n651), .CK(clk), .RN(n1739), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n649), .CK(clk), .RN(n1740), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n647), .CK(clk), .RN(n1740), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n640), .CK(clk), .RN(n1740), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n639), .CK(clk), .RN(n1731), .Q(
overflow_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n638), .CK(clk), .RN(n1740), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n637), .CK(clk), .RN(n1740), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n636), .CK(clk), .RN(n1729), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n635), .CK(clk), .RN(n1741), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n634), .CK(clk), .RN(n1729), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n633), .CK(clk), .RN(n1741), .Q(
zero_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n632), .CK(clk), .RN(n1729), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n631), .CK(clk), .RN(n1741), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n629), .CK(clk), .RN(n1729), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n628), .CK(clk), .RN(n1741), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n627), .CK(clk), .RN(n1729), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n626), .CK(clk), .RN(n1741), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n625), .CK(clk), .RN(n1729), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n624), .CK(clk), .RN(n1732), .Q(
final_result_ieee[31]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n609), .CK(clk), .RN(n1743), .Q(
DmP_mant_SFG_SWR[1]), .QN(n1003) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n606), .CK(clk), .RN(n1743), .Q(
DmP_mant_SFG_SWR[8]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n603), .CK(clk), .RN(n1743), .Q(
DmP_mant_SFG_SWR[0]), .QN(n1004) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n602), .CK(clk), .RN(n1743), .QN(
n960) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n1747), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n583), .CK(clk), .RN(n1744), .Q(
final_result_ieee[10]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n580), .CK(clk), .RN(n1745), .Q(
DmP_mant_SFG_SWR[11]), .QN(n1008) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n578), .CK(clk), .RN(n1745), .Q(
DmP_mant_SFG_SWR[10]), .QN(n991) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n577), .CK(clk), .RN(n1745), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n576), .CK(clk), .RN(n1745), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n574), .CK(clk), .RN(n1745), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n573), .CK(clk), .RN(n1745), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n572), .CK(clk), .RN(n1745), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n571), .CK(clk), .RN(n1745), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n570), .CK(clk), .RN(n1737), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n569), .CK(clk), .RN(n1746), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n568), .CK(clk), .RN(n1737), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n567), .CK(clk), .RN(n1746), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n566), .CK(clk), .RN(n1737), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n565), .CK(clk), .RN(n1746), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n564), .CK(clk), .RN(n1737), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n563), .CK(clk), .RN(n1746), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n562), .CK(clk), .RN(n1737), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n561), .CK(clk), .RN(n1746), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n560), .CK(clk), .RN(n1737), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n559), .CK(clk), .RN(n1746), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n558), .CK(clk), .RN(n1734), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n557), .CK(clk), .RN(n1731), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n556), .CK(clk), .RN(n1732), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n555), .CK(clk), .RN(n1748), .Q(
final_result_ieee[22]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n549), .CK(clk), .RN(n1747), .Q(
DmP_mant_SFG_SWR[20]), .QN(n997) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n548), .CK(clk), .RN(n973), .Q(
DmP_mant_SFG_SWR[21]), .QN(n998) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n545), .CK(clk), .RN(n1733), .Q(
DmP_mant_SFG_SWR[24]), .QN(n1000) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n544), .CK(clk), .RN(n1734), .Q(
DmP_mant_SFG_SWR[25]), .QN(n1001) );
CMPR32X2TS intadd_4_U11 ( .A(n1670), .B(intadd_4_B_0_), .C(intadd_4_CI),
.CO(intadd_4_n10), .S(intadd_4_SUM_0_) );
CMPR32X2TS intadd_4_U10 ( .A(n1669), .B(intadd_4_B_1_), .C(intadd_4_n10),
.CO(intadd_4_n9), .S(intadd_4_SUM_1_) );
CMPR32X2TS intadd_4_U9 ( .A(n1676), .B(intadd_4_B_2_), .C(intadd_4_n9), .CO(
intadd_4_n8), .S(intadd_4_SUM_2_) );
CMPR32X2TS intadd_4_U8 ( .A(n1699), .B(intadd_4_B_3_), .C(intadd_4_n8), .CO(
intadd_4_n7), .S(intadd_4_SUM_3_) );
CMPR32X2TS intadd_4_U7 ( .A(n1698), .B(intadd_4_B_4_), .C(intadd_4_n7), .CO(
intadd_4_n6), .S(intadd_4_SUM_4_) );
CMPR32X2TS intadd_4_U6 ( .A(n1705), .B(intadd_4_B_5_), .C(intadd_4_n6), .CO(
intadd_4_n5), .S(intadd_4_SUM_5_) );
CMPR32X2TS intadd_4_U5 ( .A(n1704), .B(intadd_4_B_6_), .C(intadd_4_n5), .CO(
intadd_4_n4), .S(intadd_4_SUM_6_) );
CMPR32X2TS intadd_4_U4 ( .A(n1714), .B(intadd_4_B_7_), .C(intadd_4_n4), .CO(
intadd_4_n3), .S(intadd_4_SUM_7_) );
CMPR32X2TS intadd_4_U3 ( .A(n1713), .B(intadd_4_B_8_), .C(intadd_4_n3), .CO(
intadd_4_n2), .S(intadd_4_SUM_8_) );
CMPR32X2TS intadd_4_U2 ( .A(n1717), .B(intadd_4_B_9_), .C(intadd_4_n2), .CO(
intadd_4_n1), .S(intadd_4_SUM_9_) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n919), .CK(clk), .RN(n1723),
.Q(intDX_EWSW[24]), .QN(n1710) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n864), .CK(clk), .RN(n1735), .Q(
Data_array_SWR[12]), .QN(n1709) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n599), .CK(clk), .RN(n1743), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1702) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n891), .CK(clk), .RN(n1728),
.Q(intDY_EWSW[18]), .QN(n1695) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n915), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[28]), .QN(n1694) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n886), .CK(clk), .RN(n1015),
.Q(intDY_EWSW[23]), .QN(n1693) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n889), .CK(clk), .RN(n1724),
.Q(intDY_EWSW[20]), .QN(n1690) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n895), .CK(clk), .RN(n1015),
.Q(intDY_EWSW[14]), .QN(n1688) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n897), .CK(clk), .RN(n1728),
.Q(intDY_EWSW[12]), .QN(n1687) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n901), .CK(clk), .RN(n1727), .Q(
intDY_EWSW[8]), .QN(n1684) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n908), .CK(clk), .RN(n1723), .Q(
intDY_EWSW[1]), .QN(n1683) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n888), .CK(clk), .RN(n1725),
.Q(intDY_EWSW[21]), .QN(n1682) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n896), .CK(clk), .RN(n1724),
.Q(intDY_EWSW[13]), .QN(n1681) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n892), .CK(clk), .RN(n1727),
.Q(intDY_EWSW[17]), .QN(n1679) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n906), .CK(clk), .RN(n1729), .Q(
intDY_EWSW[3]), .QN(n1678) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n937), .CK(clk), .RN(n1722), .Q(
intDX_EWSW[6]), .QN(n1663) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n927), .CK(clk), .RN(n1722),
.Q(intDX_EWSW[16]), .QN(n1662) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n938), .CK(clk), .RN(n1726), .Q(
intDX_EWSW[5]), .QN(n1658) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n848), .CK(clk), .RN(n1730), .Q(
shift_value_SHT2_EWR[4]), .QN(n1655) );
DFFRX1TS inst_ShiftRegister_Q_reg_4_ ( .D(n948), .CK(clk), .RN(n1726), .QN(
n1718) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n917), .CK(clk), .RN(n1746),
.Q(intDX_EWSW[26]), .QN(n1652) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n918), .CK(clk), .RN(n1730),
.Q(intDX_EWSW[25]), .QN(n1651) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n866), .CK(clk), .RN(n1727), .Q(
Data_array_SWR[14]), .QN(n1650) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n875), .CK(clk), .RN(n1727), .Q(
Data_array_SWR[23]), .QN(n1646) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n887), .CK(clk), .RN(n1725),
.Q(intDY_EWSW[22]), .QN(n1643) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1730), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1640) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n936), .CK(clk), .RN(n1730), .Q(
intDX_EWSW[7]), .QN(n1637) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n939), .CK(clk), .RN(n1723), .Q(
intDX_EWSW[4]), .QN(n1636) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n575), .CK(clk), .RN(n1735), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1634) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n611), .CK(clk), .RN(n1743), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1633) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n622), .CK(clk), .RN(n1739), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1631) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n874), .CK(clk), .RN(n1722), .Q(
Data_array_SWR[22]), .QN(n1630) );
DFFRX2TS inst_ShiftRegister_Q_reg_2_ ( .D(n946), .CK(clk), .RN(n1730), .QN(
n1749) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n883), .CK(clk), .RN(n1015),
.Q(intDY_EWSW[26]), .QN(n1753) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n894), .CK(clk), .RN(n1741),
.Q(intDY_EWSW[15]), .QN(n1752) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n898), .CK(clk), .RN(n1725),
.Q(intDY_EWSW[11]), .QN(n1751) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n692), .CK(clk), .RN(n1742), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1703) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n697), .CK(clk), .RN(n1735), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1697) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n1014), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1675) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n727), .CK(clk), .RN(n1732), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1659) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n600), .CK(clk), .RN(n1743), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1657) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n596), .CK(clk), .RN(n1743), .Q(
Raw_mant_NRM_SWR[4]), .QN(n1635) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n579), .CK(clk), .RN(n1745), .Q(
Raw_mant_NRM_SWR[12]), .QN(n1653) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n594), .CK(clk), .RN(n1015), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1660) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n587), .CK(clk), .RN(n1744), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1661) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n585), .CK(clk), .RN(n1744), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1656) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n589), .CK(clk), .RN(n1744), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1654) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n621), .CK(clk), .RN(n1015), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1628) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n951), .CK(clk), .RN(
n1723), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1674) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n617), .CK(clk), .RN(n1736), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1626) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n808), .CK(clk), .RN(n1733), .Q(
DMP_EXP_EWSW[26]), .QN(n1711) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n809), .CK(clk), .RN(n1734), .Q(
DMP_EXP_EWSW[25]), .QN(n1701) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n810), .CK(clk), .RN(n1736), .Q(
DMP_EXP_EWSW[24]), .QN(n1649) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n642), .CK(clk), .RN(n1740), .Q(
DmP_EXP_EWSW[26]), .QN(n1708) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n643), .CK(clk), .RN(n1740), .Q(
DmP_EXP_EWSW[25]), .QN(n1712) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n644), .CK(clk), .RN(n1740), .Q(
DmP_EXP_EWSW[24]), .QN(n1648) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n616), .CK(clk), .RN(n1742), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1625) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n879), .CK(clk), .RN(n1721),
.Q(intDY_EWSW[30]), .QN(n1639) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n890), .CK(clk), .RN(n1728),
.Q(intDY_EWSW[19]), .QN(n1645) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n882), .CK(clk), .RN(n1722),
.Q(intDY_EWSW[27]), .QN(n1691) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n885), .CK(clk), .RN(n1724),
.Q(intDY_EWSW[24]), .QN(n1629) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n893), .CK(clk), .RN(n1725),
.Q(intDY_EWSW[16]), .QN(n1689) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n900), .CK(clk), .RN(n1725), .Q(
intDY_EWSW[9]), .QN(n1680) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n903), .CK(clk), .RN(n1741), .Q(
intDY_EWSW[6]), .QN(n1672) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n905), .CK(clk), .RN(n1727), .Q(
intDY_EWSW[4]), .QN(n1686) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n904), .CK(clk), .RN(n1728), .Q(
intDY_EWSW[5]), .QN(n1641) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n909), .CK(clk), .RN(n1723), .Q(
intDY_EWSW[0]), .QN(n1642) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n907), .CK(clk), .RN(n1721), .Q(
intDY_EWSW[2]), .QN(n1685) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n913), .CK(clk), .RN(n1722),
.Q(intDX_EWSW[30]), .QN(n1644) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n914), .CK(clk), .RN(n1730),
.Q(intDX_EWSW[29]), .QN(n1692) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n902), .CK(clk), .RN(n1724), .Q(
intDY_EWSW[7]), .QN(n1673) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n613), .CK(clk), .RN(n1732), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1627) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n880), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[29]), .QN(n1666) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n862), .CK(clk), .RN(n1741), .Q(
Data_array_SWR[10]), .QN(n1706) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n872), .CK(clk), .RN(n1015), .Q(
Data_array_SWR[20]), .QN(n1715) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n870), .CK(clk), .RN(n1722), .Q(
Data_array_SWR[18]), .QN(n1700) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n867), .CK(clk), .RN(n1725), .Q(
Data_array_SWR[15]), .QN(n1647) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n863), .CK(clk), .RN(n1727), .Q(
Data_array_SWR[11]), .QN(n1707) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n871), .CK(clk), .RN(n1727), .Q(
Data_array_SWR[19]), .QN(n1696) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n940), .CK(clk), .RN(n1722), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n920), .CK(clk), .RN(n1730),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n928), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n922), .CK(clk), .RN(n1722),
.Q(intDX_EWSW[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n930), .CK(clk), .RN(n1748),
.Q(intDX_EWSW[13]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n876), .CK(clk), .RN(n1747), .Q(
Data_array_SWR[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n618), .CK(clk), .RN(n1746), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n926), .CK(clk), .RN(n1730),
.Q(intDX_EWSW[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n877), .CK(clk), .RN(n1735), .Q(
Data_array_SWR[25]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n932), .CK(clk), .RN(n1730),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n934), .CK(clk), .RN(n1723), .Q(
intDX_EWSW[9]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n935), .CK(clk), .RN(n1726), .Q(
intDX_EWSW[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n916), .CK(clk), .RN(n1721),
.Q(intDX_EWSW[27]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n591), .CK(clk), .RN(n1744), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n865), .CK(clk), .RN(n1724), .Q(
Data_array_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n581), .CK(clk), .RN(n1745), .Q(
Raw_mant_NRM_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n619), .CK(clk), .RN(n1742), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n623), .CK(clk), .RN(n1014), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n605), .CK(clk), .RN(n1743), .Q(
Raw_mant_NRM_SWR[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n943), .CK(clk), .RN(n1726), .Q(
intDX_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n925), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[18]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n608), .CK(clk), .RN(n1743), .Q(
Raw_mant_NRM_SWR[1]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n952), .CK(clk), .RN(
n1723), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n860), .CK(clk), .RN(n1724), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n868), .CK(clk), .RN(n1725), .Q(
Data_array_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n620), .CK(clk), .RN(n1015), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n856), .CK(clk), .RN(n1729), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n857), .CK(clk), .RN(n1735), .Q(
Data_array_SWR[5]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n615), .CK(clk), .RN(n1741), .Q(
Raw_mant_NRM_SWR[23]), .QN(n957) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n858), .CK(clk), .RN(n1724), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n859), .CK(clk), .RN(n1725), .Q(
Data_array_SWR[7]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_2_ ( .D(n792), .CK(clk), .RN(n1747), .Q(
DMP_SFG[2]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n762), .CK(clk), .RN(n1734), .Q(
DMP_SFG[12]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n912), .CK(clk), .RN(n1740),
.Q(intDX_EWSW[31]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n850), .CK(clk), .RN(n1726), .Q(
shift_value_SHT2_EWR[3]), .QN(n1665) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n614), .CK(clk), .RN(n1730), .Q(
Raw_mant_NRM_SWR[24]), .QN(n1011) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n774), .CK(clk), .RN(n1733), .Q(
DMP_SFG[8]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n795), .CK(clk), .RN(n1731), .Q(
DMP_SFG[1]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n646), .CK(clk), .RN(n1740), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n656), .CK(clk), .RN(n1739), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n658), .CK(clk), .RN(n1739), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n676), .CK(clk), .RN(n1737), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n684), .CK(clk), .RN(n1746), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n654), .CK(clk), .RN(n1739), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n666), .CK(clk), .RN(n1738), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n670), .CK(clk), .RN(n1738), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n674), .CK(clk), .RN(n1737), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n899), .CK(clk), .RN(n1725),
.Q(intDY_EWSW[10]), .QN(n959) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n650), .CK(clk), .RN(n1739), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n662), .CK(clk), .RN(n1738), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n648), .CK(clk), .RN(n1740), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n678), .CK(clk), .RN(n1746), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n686), .CK(clk), .RN(n973), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n688), .CK(clk), .RN(n1733), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n777), .CK(clk), .RN(n1747), .Q(
DMP_SFG[7]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n765), .CK(clk), .RN(n1732), .Q(
DMP_SFG[11]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n786), .CK(clk), .RN(n1722), .Q(
DMP_SFG[4]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n789), .CK(clk), .RN(n1723), .Q(
DMP_SFG[3]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n582), .CK(clk), .RN(n1745), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n584), .CK(clk), .RN(n1744), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n597), .CK(clk), .RN(n1743), .Q(
DmP_mant_SFG_SWR[3]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n601), .CK(clk), .RN(n1743), .Q(
DmP_mant_SFG_SWR[2]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n768), .CK(clk), .RN(n1735), .Q(
DMP_SFG[10]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n780), .CK(clk), .RN(n1014), .Q(
DMP_SFG[6]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n798), .CK(clk), .RN(n973), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n771), .CK(clk), .RN(n1015), .Q(
DMP_SFG[9]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n546), .CK(clk), .RN(n1736), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n547), .CK(clk), .RN(n1748), .Q(
DmP_mant_SFG_SWR[22]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n847), .CK(clk), .RN(n1735),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n783), .CK(clk), .RN(n1736), .Q(
DMP_SFG[5]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n884), .CK(clk), .RN(n1729),
.Q(intDY_EWSW[25]), .QN(n1720) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n811), .CK(clk), .RN(n1747), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n1742), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n712), .CK(clk), .RN(n1013), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n717), .CK(clk), .RN(n1721), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n1743), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n854), .CK(clk), .RN(n1724), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n855), .CK(clk), .RN(n1725), .Q(
Data_array_SWR[3]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n878), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[31]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n931), .CK(clk), .RN(n1730),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n923), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n929), .CK(clk), .RN(n1721),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n921), .CK(clk), .RN(n1723),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n942), .CK(clk), .RN(n1721), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n941), .CK(clk), .RN(n1721), .Q(
intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n933), .CK(clk), .RN(n1723),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n881), .CK(clk), .RN(n1723),
.Q(intDY_EWSW[28]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n924), .CK(clk), .RN(n1722),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n861), .CK(clk), .RN(n1741), .Q(
Data_array_SWR[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n869), .CK(clk), .RN(n1015), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n873), .CK(clk), .RN(n1725), .Q(
Data_array_SWR[21]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n851), .CK(clk), .RN(n1721), .Q(
shift_value_SHT2_EWR[2]), .QN(n1664) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n735), .CK(clk), .RN(n1013), .Q(
DMP_SFG[21]), .QN(n1713) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n586), .CK(clk), .RN(n1744), .Q(
DmP_mant_SFG_SWR[9]), .QN(n1009) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n590), .CK(clk), .RN(n1744), .Q(
DmP_mant_SFG_SWR[5]), .QN(n1007) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n595), .CK(clk), .RN(n1744), .Q(
DmP_mant_SFG_SWR[6]), .QN(n1005) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n588), .CK(clk), .RN(n1744), .Q(
DmP_mant_SFG_SWR[7]), .QN(n1010) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n645), .CK(clk), .RN(n1740), .Q(
DmP_EXP_EWSW[23]), .QN(n999) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n852), .CK(clk), .RN(n1726), .Q(
Data_array_SWR[0]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n853), .CK(clk), .RN(n1741), .Q(
Data_array_SWR[1]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n641), .CK(clk), .RN(n1740), .Q(
DmP_EXP_EWSW[27]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n554), .CK(clk), .RN(n1736), .Q(
DmP_mant_SFG_SWR[15]), .QN(n992) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n553), .CK(clk), .RN(n1747), .Q(
DmP_mant_SFG_SWR[16]), .QN(n993) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n552), .CK(clk), .RN(n1732), .Q(
DmP_mant_SFG_SWR[17]), .QN(n994) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n551), .CK(clk), .RN(n1748), .Q(
DmP_mant_SFG_SWR[18]), .QN(n995) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n550), .CK(clk), .RN(n1736), .Q(
DmP_mant_SFG_SWR[19]), .QN(n996) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n741), .CK(clk), .RN(n1732), .Q(
DMP_SFG[19]), .QN(n1704) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n738), .CK(clk), .RN(n1740), .Q(
DMP_SFG[20]), .QN(n1714) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n747), .CK(clk), .RN(n1731), .Q(
DMP_SFG[17]), .QN(n1698) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n753), .CK(clk), .RN(n973), .Q(
DMP_SFG[15]), .QN(n1676) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n756), .CK(clk), .RN(n1732), .Q(
DMP_SFG[14]), .QN(n1669) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n759), .CK(clk), .RN(n1748), .Q(
DMP_SFG[13]), .QN(n1670) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n732), .CK(clk), .RN(n1737), .Q(
DMP_SFG[22]), .QN(n1717) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n744), .CK(clk), .RN(n1733), .Q(
DMP_SFG[18]), .QN(n1705) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n750), .CK(clk), .RN(n1734), .Q(
DMP_SFG[16]), .QN(n1699) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n604), .CK(clk), .RN(n1739), .Q(
LZD_output_NRM2_EW[1]), .QN(n1667) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n610), .CK(clk), .RN(n1742), .Q(
LZD_output_NRM2_EW[4]), .QN(n1677) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n598), .CK(clk), .RN(n1015), .Q(
LZD_output_NRM2_EW[3]), .QN(n1671) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n607), .CK(clk), .RN(n1733), .Q(
LZD_output_NRM2_EW[2]), .QN(n1668) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n612), .CK(clk), .RN(n1013), .Q(
DmP_mant_SFG_SWR[14]), .QN(n1002) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n592), .CK(clk), .RN(n1744), .Q(
DmP_mant_SFG_SWR[4]), .QN(n1006) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n949), .CK(clk), .RN(n1739), .Q(
n1632), .QN(n1716) );
ADDFX1TS DP_OP_15J10_123_2691_U7 ( .A(n1668), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J10_123_2691_n7), .CO(DP_OP_15J10_123_2691_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J10_123_2691_U6 ( .A(n1671), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J10_123_2691_n6), .CO(DP_OP_15J10_123_2691_n5), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J10_123_2691_U5 ( .A(n1677), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J10_123_2691_n5), .CO(DP_OP_15J10_123_2691_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX4TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n630), .CK(clk), .RN(n1729), .Q(n1012), .QN(n1638) );
CMPR32X2TS DP_OP_15J10_123_2691_U8 ( .A(n1667), .B(DMP_exp_NRM2_EW[1]), .C(
DP_OP_15J10_123_2691_n8), .CO(DP_OP_15J10_123_2691_n7), .S(
exp_rslt_NRM2_EW1[1]) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n945), .CK(clk), .RN(n1730), .Q(
Shift_reg_FLAGS_7[1]), .QN(n953) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n950), .CK(clk), .RN(n1721), .Q(
Shift_reg_FLAGS_7_6), .QN(n956) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n944), .CK(clk), .RN(n1741), .Q(
Shift_reg_FLAGS_7[0]) );
NAND2X4TS U964 ( .A(n976), .B(n1602), .Y(n1411) );
NOR2X6TS U965 ( .A(n1105), .B(n1200), .Y(n1111) );
CMPR32X2TS U966 ( .A(DMP_SFG[1]), .B(n1039), .C(n1471), .CO(n1484), .S(n1016) );
AOI222X4TS U967 ( .A0(Data_array_SWR[21]), .A1(n1481), .B0(
Data_array_SWR[17]), .B1(n1480), .C0(Data_array_SWR[25]), .C1(n1455),
.Y(n1445) );
OAI21XLTS U968 ( .A0(Raw_mant_NRM_SWR[7]), .A1(Raw_mant_NRM_SWR[6]), .B0(
n1207), .Y(n1208) );
OAI21XLTS U969 ( .A0(n1369), .A1(n987), .B0(n1306), .Y(n868) );
INVX3TS U970 ( .A(n1309), .Y(n1377) );
INVX3TS U971 ( .A(n1303), .Y(n1280) );
CLKINVX6TS U972 ( .A(n1379), .Y(n1238) );
AND2X2TS U973 ( .A(n1239), .B(n1387), .Y(n1240) );
OAI211X2TS U974 ( .A0(n1660), .A1(n1227), .B0(n1226), .C0(n1225), .Y(n1243)
);
AOI31X1TS U975 ( .A0(n1224), .A1(Raw_mant_NRM_SWR[8]), .A2(n1661), .B0(n1335), .Y(n1225) );
AND2X4TS U976 ( .A(Shift_reg_FLAGS_7_6), .B(n1105), .Y(n1151) );
AO21X1TS U977 ( .A0(n1219), .A1(Raw_mant_NRM_SWR[18]), .B0(n1327), .Y(n1228)
);
INVX4TS U978 ( .A(n1352), .Y(n954) );
NOR2X6TS U979 ( .A(shift_value_SHT2_EWR[4]), .B(n1464), .Y(n1430) );
CLKINVX3TS U980 ( .A(n1550), .Y(n1429) );
AND2X4TS U981 ( .A(beg_OP), .B(n1347), .Y(n1351) );
INVX3TS U982 ( .A(n1387), .Y(n955) );
CLKINVX3TS U983 ( .A(n1549), .Y(n1438) );
NOR2BX4TS U984 ( .AN(Shift_amount_SHT1_EWR[0]), .B(Shift_reg_FLAGS_7[1]),
.Y(n1296) );
NAND2BXLTS U985 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n1054) );
NAND2BXLTS U986 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1088) );
NAND2BXLTS U987 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n1042) );
NAND2BXLTS U988 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n1067) );
NAND2BXLTS U989 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n1063) );
NAND2BXLTS U990 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1082) );
CLKAND2X2TS U991 ( .A(n1321), .B(n1322), .Y(n1320) );
OAI211XLTS U992 ( .A0(n1045), .A1(n1100), .B0(n1044), .C0(n1043), .Y(n1050)
);
NAND3XLTS U993 ( .A(n1753), .B(n1042), .C(intDX_EWSW[26]), .Y(n1044) );
NAND3BXLTS U994 ( .AN(n1086), .B(n1084), .C(n1083), .Y(n1103) );
AO22XLTS U995 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n1514), .B0(n1638), .B1(n1006),
.Y(n961) );
AOI31XLTS U996 ( .A0(n1653), .A1(Raw_mant_NRM_SWR[11]), .A2(n1229), .B0(
n1228), .Y(n1236) );
NAND2BXLTS U997 ( .AN(n1227), .B(Raw_mant_NRM_SWR[5]), .Y(n1332) );
AOI222X4TS U998 ( .A0(Data_array_SWR[21]), .A1(n1429), .B0(
Data_array_SWR[17]), .B1(n1430), .C0(Data_array_SWR[25]), .C1(n1438),
.Y(n1527) );
NAND2BXLTS U999 ( .AN(n1338), .B(n1032), .Y(n1034) );
AOI222X1TS U1000 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n1380), .B0(n989), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1370), .C1(DmP_mant_SHT1_SW[8]), .Y(n1275)
);
AOI222X1TS U1001 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1380), .B0(n989), .B1(
DmP_mant_SHT1_SW[3]), .C0(n1370), .C1(n977), .Y(n1288) );
AOI222X1TS U1002 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1380), .B0(n989), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1370), .C1(DmP_mant_SHT1_SW[3]), .Y(n1292)
);
AOI222X1TS U1003 ( .A0(DMP_SFG[12]), .A1(n974), .B0(DMP_SFG[12]), .B1(n1316),
.C0(n974), .C1(n1316), .Y(intadd_4_B_0_) );
AOI222X1TS U1004 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1380), .B0(
DmP_mant_SHT1_SW[20]), .B1(n1370), .C0(n989), .C1(n978), .Y(n1276) );
AOI222X1TS U1005 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n1380), .B0(n989), .B1(
n982), .C0(n1370), .C1(DmP_mant_SHT1_SW[10]), .Y(n1284) );
AOI222X1TS U1006 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1380), .B0(n989), .B1(
n981), .C0(n1370), .C1(DmP_mant_SHT1_SW[12]), .Y(n1281) );
AOI222X1TS U1007 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1358), .B0(n989), .B1(
n980), .C0(n1370), .C1(DmP_mant_SHT1_SW[14]), .Y(n1268) );
AOI222X1TS U1008 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1380), .B0(n989), .B1(n979), .C0(n1370), .C1(DmP_mant_SHT1_SW[16]), .Y(n1265) );
OAI21XLTS U1009 ( .A0(n1633), .A1(n1372), .B0(n1307), .Y(n1308) );
AOI31X1TS U1010 ( .A0(n975), .A1(DMP_SFG[2]), .A2(n1473), .B0(n1483), .Y(
n1493) );
OAI21XLTS U1011 ( .A0(n1330), .A1(n1329), .B0(n1328), .Y(n1336) );
AO22XLTS U1012 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1358), .B0(n990), .B1(n1360),
.Y(n1359) );
OAI21XLTS U1013 ( .A0(n1702), .A1(n1362), .B0(n1361), .Y(n1363) );
OAI21XLTS U1014 ( .A0(n1661), .A1(n1362), .B0(n1301), .Y(n1302) );
OAI21XLTS U1015 ( .A0(n1656), .A1(n1372), .B0(n1367), .Y(n1368) );
OAI21XLTS U1016 ( .A0(n1653), .A1(n1372), .B0(n1371), .Y(n1373) );
AOI222X1TS U1017 ( .A0(n1575), .A1(n1620), .B0(Data_array_SWR[9]), .B1(n1593), .C0(n1574), .C1(n1591), .Y(n1605) );
AOI222X1TS U1018 ( .A0(n1575), .A1(n1597), .B0(n1621), .B1(Data_array_SWR[9]), .C0(n1574), .C1(n1512), .Y(n1573) );
CLKINVX3TS U1019 ( .A(n1411), .Y(n1613) );
BUFX4TS U1020 ( .A(n1718), .Y(n1413) );
AOI2BB2XLTS U1021 ( .B0(Raw_mant_NRM_SWR[3]), .B1(n1377), .A0N(n1293), .A1N(
n1238), .Y(n1261) );
AOI2BB2XLTS U1022 ( .B0(Raw_mant_NRM_SWR[7]), .B1(n1377), .A0N(n1279), .A1N(
n1238), .Y(n1263) );
OAI211XLTS U1023 ( .A0(n1275), .A1(n987), .B0(n1274), .C0(n1273), .Y(n861)
);
AOI2BB2XLTS U1024 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1377), .A0N(n1284),
.A1N(n1238), .Y(n1273) );
AO22XLTS U1025 ( .A0(n1348), .A1(Data_X[19]), .B0(n954), .B1(intDX_EWSW[19]),
.Y(n924) );
AO22XLTS U1026 ( .A0(n1351), .A1(Data_Y[28]), .B0(n1355), .B1(intDY_EWSW[28]), .Y(n881) );
AO22XLTS U1027 ( .A0(n1354), .A1(Data_X[10]), .B0(n954), .B1(intDX_EWSW[10]),
.Y(n933) );
AO22XLTS U1028 ( .A0(n1356), .A1(Data_Y[31]), .B0(n954), .B1(intDY_EWSW[31]),
.Y(n878) );
AO22XLTS U1029 ( .A0(n1613), .A1(DMP_SHT2_EWSW[5]), .B0(n1611), .B1(
DMP_SFG[5]), .Y(n783) );
AO22XLTS U1030 ( .A0(n1616), .A1(DMP_SHT2_EWSW[9]), .B0(n1611), .B1(
DMP_SFG[9]), .Y(n771) );
AO22XLTS U1031 ( .A0(n1528), .A1(DMP_SHT2_EWSW[0]), .B0(n1611), .B1(
DMP_SFG[0]), .Y(n798) );
AO22XLTS U1032 ( .A0(n1528), .A1(DMP_SHT2_EWSW[6]), .B0(n1611), .B1(
DMP_SFG[6]), .Y(n780) );
AO22XLTS U1033 ( .A0(n1528), .A1(DMP_SHT2_EWSW[10]), .B0(n1611), .B1(
DMP_SFG[10]), .Y(n768) );
AO22XLTS U1034 ( .A0(n1613), .A1(n1589), .B0(n1611), .B1(DmP_mant_SFG_SWR[2]), .Y(n601) );
AO22XLTS U1035 ( .A0(n1616), .A1(n1588), .B0(n1611), .B1(DmP_mant_SFG_SWR[3]), .Y(n597) );
AO22XLTS U1036 ( .A0(n1528), .A1(n1524), .B0(n1611), .B1(
DmP_mant_SFG_SWR[12]), .Y(n584) );
AO22XLTS U1037 ( .A0(n1616), .A1(n1572), .B0(n1617), .B1(
DmP_mant_SFG_SWR[13]), .Y(n582) );
AO22XLTS U1038 ( .A0(n1613), .A1(DMP_SHT2_EWSW[3]), .B0(n1411), .B1(
DMP_SFG[3]), .Y(n789) );
AO22XLTS U1039 ( .A0(n1616), .A1(DMP_SHT2_EWSW[4]), .B0(n1411), .B1(
DMP_SFG[4]), .Y(n786) );
AO22XLTS U1040 ( .A0(n1528), .A1(DMP_SHT2_EWSW[11]), .B0(n1611), .B1(
DMP_SFG[11]), .Y(n765) );
AO22XLTS U1041 ( .A0(n1632), .A1(DmP_EXP_EWSW[1]), .B0(n1416), .B1(
DmP_mant_SHT1_SW[1]), .Y(n688) );
AO22XLTS U1042 ( .A0(n1632), .A1(DmP_EXP_EWSW[2]), .B0(n1416), .B1(
DmP_mant_SHT1_SW[2]), .Y(n686) );
AO22XLTS U1043 ( .A0(n1632), .A1(DmP_EXP_EWSW[6]), .B0(n1416), .B1(
DmP_mant_SHT1_SW[6]), .Y(n678) );
AO22XLTS U1044 ( .A0(n1423), .A1(DmP_EXP_EWSW[14]), .B0(n1414), .B1(
DmP_mant_SHT1_SW[14]), .Y(n662) );
AO22XLTS U1045 ( .A0(n1423), .A1(DmP_EXP_EWSW[20]), .B0(n1416), .B1(
DmP_mant_SHT1_SW[20]), .Y(n650) );
AO22XLTS U1046 ( .A0(n1632), .A1(DmP_EXP_EWSW[8]), .B0(n1416), .B1(
DmP_mant_SHT1_SW[8]), .Y(n674) );
AO22XLTS U1047 ( .A0(n1423), .A1(DmP_EXP_EWSW[10]), .B0(n1416), .B1(
DmP_mant_SHT1_SW[10]), .Y(n670) );
AO22XLTS U1048 ( .A0(n1423), .A1(DmP_EXP_EWSW[12]), .B0(n1416), .B1(
DmP_mant_SHT1_SW[12]), .Y(n666) );
AO22XLTS U1049 ( .A0(n1423), .A1(DmP_EXP_EWSW[18]), .B0(n1416), .B1(
DmP_mant_SHT1_SW[18]), .Y(n654) );
AO22XLTS U1050 ( .A0(n1632), .A1(DmP_EXP_EWSW[3]), .B0(n1416), .B1(
DmP_mant_SHT1_SW[3]), .Y(n684) );
AO22XLTS U1051 ( .A0(n1632), .A1(DmP_EXP_EWSW[7]), .B0(n1416), .B1(
DmP_mant_SHT1_SW[7]), .Y(n676) );
AO22XLTS U1052 ( .A0(n1423), .A1(DmP_EXP_EWSW[22]), .B0(n1416), .B1(
DmP_mant_SHT1_SW[22]), .Y(n646) );
AO22XLTS U1053 ( .A0(n1616), .A1(DMP_SHT2_EWSW[1]), .B0(n1411), .B1(
DMP_SFG[1]), .Y(n795) );
AO22XLTS U1054 ( .A0(n1616), .A1(DMP_SHT2_EWSW[8]), .B0(n1611), .B1(
DMP_SFG[8]), .Y(n774) );
AO22XLTS U1055 ( .A0(n1348), .A1(Data_X[31]), .B0(n1353), .B1(intDX_EWSW[31]), .Y(n912) );
AO22XLTS U1056 ( .A0(n1528), .A1(DMP_SHT2_EWSW[12]), .B0(n1617), .B1(
DMP_SFG[12]), .Y(n762) );
AO22XLTS U1057 ( .A0(n1528), .A1(DMP_SHT2_EWSW[2]), .B0(n1411), .B1(
DMP_SFG[2]), .Y(n792) );
OAI211XLTS U1058 ( .A0(n1275), .A1(n1238), .B0(n1249), .C0(n1248), .Y(n859)
);
OAI211XLTS U1059 ( .A0(n1310), .A1(n1238), .B0(n1257), .C0(n1256), .Y(n858)
);
OAI211XLTS U1060 ( .A0(n1288), .A1(n987), .B0(n1287), .C0(n1286), .Y(n857)
);
OAI211XLTS U1061 ( .A0(n1292), .A1(n987), .B0(n1291), .C0(n1290), .Y(n856)
);
AO22XLTS U1062 ( .A0(n1352), .A1(Data_X[18]), .B0(n1355), .B1(intDX_EWSW[18]), .Y(n925) );
AO22XLTS U1063 ( .A0(n1356), .A1(Data_X[0]), .B0(n1355), .B1(intDX_EWSW[0]),
.Y(n943) );
NAND2BXLTS U1064 ( .AN(n1532), .B(n1531), .Y(n1533) );
AOI2BB2XLTS U1065 ( .B0(Raw_mant_NRM_SWR[11]), .B1(n1377), .A0N(n1268),
.A1N(n1238), .Y(n1259) );
OAI211XLTS U1066 ( .A0(n1279), .A1(n987), .B0(n1278), .C0(n1277), .Y(n871)
);
AOI2BB2XLTS U1067 ( .B0(Raw_mant_NRM_SWR[5]), .B1(n1377), .A0N(n1276), .A1N(
n1238), .Y(n1277) );
OAI211XLTS U1068 ( .A0(n1284), .A1(n987), .B0(n1283), .C0(n1282), .Y(n863)
);
AOI2BB2XLTS U1069 ( .B0(Raw_mant_NRM_SWR[13]), .B1(n1377), .A0N(n1281),
.A1N(n1238), .Y(n1282) );
OAI211XLTS U1070 ( .A0(n1268), .A1(n987), .B0(n1267), .C0(n1266), .Y(n867)
);
AOI2BB2XLTS U1071 ( .B0(Raw_mant_NRM_SWR[9]), .B1(n1377), .A0N(n1265), .A1N(
n1238), .Y(n1266) );
OAI21XLTS U1072 ( .A0(n1365), .A1(n1238), .B0(n1300), .Y(n870) );
AO22XLTS U1073 ( .A0(n1345), .A1(n1569), .B0(n1346), .B1(n976), .Y(n946) );
OAI21XLTS U1074 ( .A0(n1357), .A1(n1238), .B0(n1295), .Y(n875) );
OAI21XLTS U1075 ( .A0(n1387), .A1(n1655), .B0(n1215), .Y(n848) );
AO22XLTS U1076 ( .A0(n1423), .A1(DmP_EXP_EWSW[15]), .B0(n1414), .B1(n979),
.Y(n660) );
AO22XLTS U1077 ( .A0(n1423), .A1(DmP_EXP_EWSW[13]), .B0(n1416), .B1(n980),
.Y(n664) );
AO22XLTS U1078 ( .A0(n1423), .A1(DmP_EXP_EWSW[11]), .B0(n1416), .B1(n981),
.Y(n668) );
AO22XLTS U1079 ( .A0(n1423), .A1(DmP_EXP_EWSW[9]), .B0(n1416), .B1(n982),
.Y(n672) );
AO22XLTS U1080 ( .A0(n1632), .A1(DmP_EXP_EWSW[5]), .B0(n1416), .B1(n983),
.Y(n680) );
AO22XLTS U1081 ( .A0(n1632), .A1(DmP_EXP_EWSW[4]), .B0(n1416), .B1(n977),
.Y(n682) );
AO22XLTS U1082 ( .A0(n1632), .A1(DmP_EXP_EWSW[0]), .B0(n1424), .B1(n984),
.Y(n690) );
AO22XLTS U1083 ( .A0(n1346), .A1(busy), .B0(n1345), .B1(n976), .Y(n947) );
OA22X1TS U1084 ( .A0(n1459), .A1(DmP_mant_SFG_SWR[14]), .B0(n1002), .B1(
n1012), .Y(n958) );
BUFX3TS U1085 ( .A(n955), .Y(n1385) );
OR2X1TS U1086 ( .A(Shift_reg_FLAGS_7[1]), .B(Shift_amount_SHT1_EWR[0]), .Y(
n962) );
AOI211XLTS U1087 ( .A0(intDY_EWSW[16]), .A1(n1662), .B0(n1091), .C0(n1121),
.Y(n1083) );
OAI211XLTS U1088 ( .A0(n1272), .A1(n987), .B0(n1271), .C0(n1270), .Y(n853)
);
NOR2BX2TS U1089 ( .AN(n1330), .B(n1329), .Y(n1219) );
AOI222X1TS U1090 ( .A0(n1594), .A1(n1597), .B0(n1621), .B1(Data_array_SWR[8]), .C0(n1592), .C1(n1512), .Y(n1590) );
CLKINVX3TS U1091 ( .A(n1596), .Y(n1621) );
AOI222X1TS U1092 ( .A0(n1594), .A1(n1620), .B0(Data_array_SWR[8]), .B1(n1593), .C0(n1592), .C1(n1591), .Y(n1606) );
CLKINVX3TS U1093 ( .A(n1553), .Y(n1593) );
BUFX4TS U1094 ( .A(n1742), .Y(n1729) );
BUFX4TS U1095 ( .A(n1742), .Y(n1741) );
BUFX4TS U1096 ( .A(n1742), .Y(n1739) );
BUFX4TS U1097 ( .A(n1746), .Y(n1740) );
NOR2X4TS U1098 ( .A(shift_value_SHT2_EWR[4]), .B(n1620), .Y(n1591) );
NOR2X4TS U1099 ( .A(shift_value_SHT2_EWR[4]), .B(n1597), .Y(n1512) );
BUFX4TS U1100 ( .A(n1736), .Y(n1728) );
BUFX4TS U1101 ( .A(n1723), .Y(n1735) );
BUFX3TS U1102 ( .A(n1736), .Y(n1015) );
BUFX3TS U1103 ( .A(n1716), .Y(n1415) );
NOR4BBX2TS U1104 ( .AN(n1237), .BN(n1236), .C(n1235), .D(n1234), .Y(n1258)
);
BUFX3TS U1105 ( .A(n1014), .Y(n973) );
BUFX4TS U1106 ( .A(n1014), .Y(n1736) );
BUFX4TS U1107 ( .A(n1014), .Y(n1747) );
BUFX4TS U1108 ( .A(n1014), .Y(n1748) );
BUFX4TS U1109 ( .A(n1014), .Y(n1732) );
BUFX3TS U1110 ( .A(n1741), .Y(n1014) );
BUFX4TS U1111 ( .A(n1747), .Y(n1743) );
BUFX4TS U1112 ( .A(n1729), .Y(n1746) );
BUFX4TS U1113 ( .A(n1728), .Y(n1737) );
BUFX4TS U1114 ( .A(n1728), .Y(n1722) );
BUFX4TS U1115 ( .A(n1013), .Y(n1742) );
NOR2X2TS U1116 ( .A(shift_value_SHT2_EWR[2]), .B(n1665), .Y(n1455) );
OAI22X2TS U1117 ( .A0(n1630), .A1(n1464), .B0(n1700), .B1(n1463), .Y(n1577)
);
OAI22X2TS U1118 ( .A0(n1646), .A1(n1464), .B0(n1696), .B1(n1463), .Y(n1586)
);
BUFX4TS U1119 ( .A(n1724), .Y(n1723) );
BUFX4TS U1120 ( .A(n1729), .Y(n1726) );
BUFX4TS U1121 ( .A(n1725), .Y(n1730) );
INVX2TS U1122 ( .A(n958), .Y(n974) );
XNOR2X2TS U1123 ( .A(DMP_exp_NRM2_EW[7]), .B(n1023), .Y(n1033) );
INVX2TS U1124 ( .A(n961), .Y(n975) );
XNOR2X2TS U1125 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J10_123_2691_n4), .Y(
n1035) );
NOR2X4TS U1126 ( .A(n1463), .B(shift_value_SHT2_EWR[4]), .Y(n1467) );
BUFX4TS U1127 ( .A(n1106), .Y(n1408) );
INVX2TS U1128 ( .A(n963), .Y(n976) );
INVX2TS U1129 ( .A(n971), .Y(n977) );
INVX2TS U1130 ( .A(n970), .Y(n978) );
INVX2TS U1131 ( .A(n969), .Y(n979) );
INVX2TS U1132 ( .A(n968), .Y(n980) );
INVX2TS U1133 ( .A(n967), .Y(n981) );
INVX2TS U1134 ( .A(n966), .Y(n982) );
INVX2TS U1135 ( .A(n972), .Y(n983) );
INVX2TS U1136 ( .A(n965), .Y(n984) );
INVX2TS U1137 ( .A(n964), .Y(n985) );
NOR2X2TS U1138 ( .A(n1258), .B(n953), .Y(n1337) );
AOI211X1TS U1139 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n953), .B0(n1370), .C0(
n1359), .Y(n1364) );
BUFX4TS U1140 ( .A(n1411), .Y(n1611) );
CLKINVX6TS U1141 ( .A(n1620), .Y(n1597) );
BUFX6TS U1142 ( .A(left_right_SHT2), .Y(n1620) );
BUFX4TS U1143 ( .A(n1200), .Y(n1344) );
INVX2TS U1144 ( .A(n1240), .Y(n986) );
INVX4TS U1145 ( .A(n1240), .Y(n987) );
BUFX4TS U1146 ( .A(n1411), .Y(n1617) );
INVX2TS U1147 ( .A(n962), .Y(n988) );
INVX4TS U1148 ( .A(n962), .Y(n989) );
CLKINVX6TS U1149 ( .A(n1411), .Y(n1528) );
CLKINVX6TS U1150 ( .A(n1411), .Y(n1616) );
INVX2TS U1151 ( .A(n960), .Y(n990) );
OAI211XLTS U1152 ( .A0(n1276), .A1(n986), .B0(n1262), .C0(n1261), .Y(n873)
);
OAI211XLTS U1153 ( .A0(n1265), .A1(n986), .B0(n1264), .C0(n1263), .Y(n869)
);
AOI32X1TS U1154 ( .A0(n1695), .A1(n1088), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1645), .Y(n1089) );
AOI221X1TS U1155 ( .A0(n1695), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1645), .C0(n1121), .Y(n1126) );
AOI221X1TS U1156 ( .A0(n1691), .A1(intDX_EWSW[27]), .B0(intDY_EWSW[28]),
.B1(n1694), .C0(n1114), .Y(n1118) );
AOI221X1TS U1157 ( .A0(n959), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]), .B1(
n1751), .C0(n1129), .Y(n1134) );
AOI221X1TS U1158 ( .A0(n1685), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1678), .C0(n1137), .Y(n1142) );
AOI221X1TS U1159 ( .A0(n1683), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[17]), .B1(
n1679), .C0(n1120), .Y(n1127) );
AOI221X1TS U1160 ( .A0(n1643), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1693), .C0(n1123), .Y(n1124) );
AOI221X1TS U1161 ( .A0(n1688), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1752), .C0(n1131), .Y(n1132) );
OAI211X2TS U1162 ( .A0(intDX_EWSW[20]), .A1(n1690), .B0(n1096), .C0(n1082),
.Y(n1091) );
AOI221X1TS U1163 ( .A0(n1690), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1682), .C0(n1122), .Y(n1125) );
OAI211X2TS U1164 ( .A0(intDX_EWSW[12]), .A1(n1687), .B0(n1077), .C0(n1063),
.Y(n1079) );
AOI221X1TS U1165 ( .A0(n1687), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1681), .C0(n1130), .Y(n1133) );
OAI211XLTS U1166 ( .A0(n1288), .A1(n1238), .B0(n1245), .C0(n1244), .Y(n855)
);
OAI211XLTS U1167 ( .A0(n1292), .A1(n1238), .B0(n1253), .C0(n1252), .Y(n854)
);
OAI31XLTS U1168 ( .A0(n1410), .A1(n1150), .A2(n1419), .B0(n1149), .Y(n801)
);
NOR2X2TS U1169 ( .A(n999), .B(DMP_EXP_EWSW[23]), .Y(n1394) );
BUFX4TS U1170 ( .A(n1729), .Y(n1725) );
XNOR2X2TS U1171 ( .A(DMP_exp_NRM2_EW[6]), .B(n1020), .Y(n1338) );
XNOR2X2TS U1172 ( .A(DMP_exp_NRM2_EW[0]), .B(n1317), .Y(n1036) );
CLKINVX6TS U1173 ( .A(n1459), .Y(n1514) );
NOR2X2TS U1174 ( .A(n1470), .B(DMP_SFG[3]), .Y(n1482) );
NOR2X2TS U1175 ( .A(n1446), .B(DMP_SFG[4]), .Y(n1494) );
NOR2X2TS U1176 ( .A(n1315), .B(DMP_SFG[11]), .Y(n1532) );
NOR2X2TS U1177 ( .A(n1504), .B(DMP_SFG[7]), .Y(n1559) );
AOI222X1TS U1178 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1358), .B0(n988), .B1(
DmP_mant_SHT1_SW[6]), .C0(n1370), .C1(DmP_mant_SHT1_SW[7]), .Y(n1310)
);
AOI222X1TS U1179 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1358), .B0(n989), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1370), .C1(DmP_mant_SHT1_SW[18]), .Y(n1279) );
AOI222X4TS U1180 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n1380), .B0(n989), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1370), .C1(DmP_mant_SHT1_SW[17]), .Y(n1304) );
AOI222X1TS U1181 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1358), .B0(n989), .B1(
DmP_mant_SHT1_SW[21]), .C0(n1370), .C1(DmP_mant_SHT1_SW[22]), .Y(n1293) );
OAI211XLTS U1182 ( .A0(n975), .A1(DMP_SFG[2]), .B0(n1471), .C0(DMP_SFG[1]),
.Y(n1474) );
NOR2X4TS U1183 ( .A(n1523), .B(n1522), .Y(n1600) );
OAI2BB1X2TS U1184 ( .A0N(n1026), .A1N(n1025), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1522) );
INVX4TS U1185 ( .A(n1351), .Y(n1353) );
NAND3X2TS U1186 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.C(n1655), .Y(n1549) );
CLKINVX6TS U1187 ( .A(n1151), .Y(n1417) );
NAND2X4TS U1188 ( .A(n953), .B(n1413), .Y(n1387) );
CLKINVX6TS U1189 ( .A(n1413), .Y(n1426) );
XOR2XLTS U1190 ( .A(DMP_SFG[12]), .B(n974), .Y(n1436) );
AOI222X1TS U1191 ( .A0(n1578), .A1(n1597), .B0(n1621), .B1(Data_array_SWR[7]), .C0(n1577), .C1(n1512), .Y(n1576) );
AOI222X1TS U1192 ( .A0(n1578), .A1(n1620), .B0(Data_array_SWR[7]), .B1(n1593), .C0(n1577), .C1(n1591), .Y(n1607) );
AOI222X1TS U1193 ( .A0(n1587), .A1(n1597), .B0(n1621), .B1(Data_array_SWR[6]), .C0(n1586), .C1(n1512), .Y(n1585) );
AOI222X1TS U1194 ( .A0(n1587), .A1(n1620), .B0(Data_array_SWR[6]), .B1(n1593), .C0(n1586), .C1(n1591), .Y(n1609) );
AOI222X1TS U1195 ( .A0(n1581), .A1(n1597), .B0(n1621), .B1(Data_array_SWR[5]), .C0(n1580), .C1(n1512), .Y(n1579) );
AOI222X1TS U1196 ( .A0(n1581), .A1(n1620), .B0(Data_array_SWR[5]), .B1(n1593), .C0(n1580), .C1(n1591), .Y(n1610) );
AOI222X1TS U1197 ( .A0(n1584), .A1(n1597), .B0(n1621), .B1(Data_array_SWR[4]), .C0(n1583), .C1(n1512), .Y(n1582) );
AOI222X1TS U1198 ( .A0(n1584), .A1(n1620), .B0(Data_array_SWR[4]), .B1(n1593), .C0(n1583), .C1(n1591), .Y(n1612) );
INVX3TS U1199 ( .A(n1420), .Y(n1602) );
AOI222X4TS U1200 ( .A0(Data_array_SWR[20]), .A1(n1429), .B0(
Data_array_SWR[24]), .B1(n1438), .C0(Data_array_SWR[16]), .C1(n1430),
.Y(n1526) );
AOI222X4TS U1201 ( .A0(Data_array_SWR[20]), .A1(n1481), .B0(
Data_array_SWR[24]), .B1(n1455), .C0(Data_array_SWR[16]), .C1(n1480),
.Y(n1511) );
NOR2X2TS U1202 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1674), .Y(n1343) );
OAI21X2TS U1203 ( .A0(intDX_EWSW[18]), .A1(n1695), .B0(n1088), .Y(n1121) );
AOI32X1TS U1204 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1231), .A2(n1230), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1231), .Y(n1232) );
NOR3X1TS U1205 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1330) );
NOR2X2TS U1206 ( .A(Raw_mant_NRM_SWR[13]), .B(n1206), .Y(n1229) );
OAI211XLTS U1207 ( .A0(n1281), .A1(n986), .B0(n1260), .C0(n1259), .Y(n865)
);
AOI221X1TS U1208 ( .A0(n1684), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1672), .C0(n1139), .Y(n1140) );
NOR2XLTS U1209 ( .A(n1751), .B(intDX_EWSW[11]), .Y(n1065) );
OAI21XLTS U1210 ( .A0(intDX_EWSW[15]), .A1(n1752), .B0(intDX_EWSW[14]), .Y(
n1073) );
NOR2XLTS U1211 ( .A(n1086), .B(intDY_EWSW[16]), .Y(n1087) );
OAI21XLTS U1212 ( .A0(intDX_EWSW[21]), .A1(n1682), .B0(intDX_EWSW[20]), .Y(
n1085) );
NOR2XLTS U1213 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1230) );
OAI21XLTS U1214 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1657), .B0(n1635), .Y(n1220) );
AOI31XLTS U1215 ( .A0(n1219), .A1(Raw_mant_NRM_SWR[16]), .A2(n1628), .B0(
n1217), .Y(n1226) );
OAI21XLTS U1216 ( .A0(n1635), .A1(n1372), .B0(n1297), .Y(n1298) );
OAI21XLTS U1217 ( .A0(n1482), .A1(n1474), .B0(n1493), .Y(n1475) );
NOR2XLTS U1218 ( .A(n1483), .B(n1482), .Y(n1486) );
OAI21XLTS U1219 ( .A0(DmP_EXP_EWSW[25]), .A1(n1701), .B0(n1398), .Y(n1395)
);
INVX2TS U1220 ( .A(rst), .Y(n1013) );
AOI31XLTS U1221 ( .A0(n1426), .A1(Shift_amount_SHT1_EWR[4]), .A2(n953), .B0(
n1319), .Y(n1215) );
OAI21XLTS U1222 ( .A0(n1343), .A1(n1040), .B0(n1340), .Y(n951) );
OAI21XLTS U1223 ( .A0(n1752), .A1(n1205), .B0(n1204), .Y(n819) );
OAI21XLTS U1224 ( .A0(n1683), .A1(n1205), .B0(n1164), .Y(n833) );
OAI21XLTS U1225 ( .A0(n1375), .A1(n1238), .B0(n1312), .Y(n860) );
INVX4TS U1226 ( .A(n1413), .Y(busy) );
BUFX3TS U1227 ( .A(n1014), .Y(n1734) );
BUFX3TS U1228 ( .A(n1742), .Y(n1738) );
BUFX3TS U1229 ( .A(n1014), .Y(n1733) );
BUFX3TS U1230 ( .A(n1732), .Y(n1745) );
BUFX3TS U1231 ( .A(n1736), .Y(n1727) );
BUFX3TS U1232 ( .A(n1725), .Y(n1721) );
BUFX3TS U1233 ( .A(n1732), .Y(n1744) );
BUFX3TS U1234 ( .A(n1014), .Y(n1731) );
BUFX3TS U1235 ( .A(n1739), .Y(n1724) );
AO22XLTS U1236 ( .A0(Shift_reg_FLAGS_7[1]), .A1(ZERO_FLAG_NRM), .B0(n953),
.B1(ZERO_FLAG_SHT1SHT2), .Y(n634) );
AO22XLTS U1237 ( .A0(Shift_reg_FLAGS_7[1]), .A1(SIGN_FLAG_NRM), .B0(n953),
.B1(SIGN_FLAG_SHT1SHT2), .Y(n625) );
BUFX4TS U1238 ( .A(n1749), .Y(n1567) );
BUFX3TS U1239 ( .A(n1567), .Y(n1546) );
INVX4TS U1240 ( .A(n1546), .Y(n1487) );
AOI2BB2X1TS U1241 ( .B0(DmP_mant_SFG_SWR[2]), .B1(n1012), .A0N(n1012), .A1N(
DmP_mant_SFG_SWR[2]), .Y(n1037) );
CLKAND2X2TS U1242 ( .A(n1037), .B(DMP_SFG[0]), .Y(n1039) );
AOI2BB2X1TS U1243 ( .B0(DmP_mant_SFG_SWR[3]), .B1(n1012), .A0N(n1012), .A1N(
DmP_mant_SFG_SWR[3]), .Y(n1471) );
AO22XLTS U1244 ( .A0(n1567), .A1(Raw_mant_NRM_SWR[3]), .B0(n1487), .B1(n1016), .Y(n599) );
BUFX3TS U1245 ( .A(n1638), .Y(n1459) );
AO22XLTS U1246 ( .A0(n1567), .A1(Raw_mant_NRM_SWR[4]), .B0(n1487), .B1(n1017), .Y(n596) );
INVX2TS U1247 ( .A(DP_OP_15J10_123_2691_n4), .Y(n1018) );
NAND2X1TS U1248 ( .A(n1675), .B(n1018), .Y(n1020) );
INVX2TS U1249 ( .A(n1020), .Y(n1019) );
NAND2X1TS U1250 ( .A(n1697), .B(n1019), .Y(n1023) );
INVX1TS U1251 ( .A(LZD_output_NRM2_EW[0]), .Y(n1317) );
AND4X1TS U1252 ( .A(exp_rslt_NRM2_EW1[3]), .B(n1036), .C(
exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n1021) );
AND4X1TS U1253 ( .A(n1338), .B(n1035), .C(exp_rslt_NRM2_EW1[4]), .D(n1021),
.Y(n1022) );
CLKAND2X2TS U1254 ( .A(n1033), .B(n1022), .Y(n1026) );
INVX2TS U1255 ( .A(n1023), .Y(n1024) );
CLKAND2X2TS U1256 ( .A(n1703), .B(n1024), .Y(n1025) );
INVX2TS U1257 ( .A(n1522), .Y(n1027) );
CLKBUFX2TS U1258 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1420) );
AO22XLTS U1259 ( .A0(n1027), .A1(n1033), .B0(n1602), .B1(
final_result_ieee[30]), .Y(n835) );
NOR2XLTS U1260 ( .A(n1036), .B(exp_rslt_NRM2_EW1[1]), .Y(n1030) );
INVX2TS U1261 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n1029) );
INVX2TS U1262 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n1028) );
NAND4BXLTS U1263 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n1030), .C(n1029), .D(n1028), .Y(n1031) );
NOR2XLTS U1264 ( .A(n1031), .B(n1035), .Y(n1032) );
OR2X1TS U1265 ( .A(n1034), .B(n1033), .Y(n1313) );
NAND2X2TS U1266 ( .A(n1313), .B(n1420), .Y(n1339) );
OA22X1TS U1267 ( .A0(n1339), .A1(n1035), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[28]), .Y(n837) );
OA22X1TS U1268 ( .A0(n1339), .A1(exp_rslt_NRM2_EW1[1]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[24]), .Y(n841) );
OA22X1TS U1269 ( .A0(n1339), .A1(exp_rslt_NRM2_EW1[3]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[26]), .Y(n839) );
OA22X1TS U1270 ( .A0(n1339), .A1(n1036), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[23]), .Y(n842) );
OA22X1TS U1271 ( .A0(n1339), .A1(exp_rslt_NRM2_EW1[4]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[27]), .Y(n838) );
OA22X1TS U1272 ( .A0(n1339), .A1(exp_rslt_NRM2_EW1[2]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[25]), .Y(n840) );
OAI21XLTS U1273 ( .A0(n1426), .A1(n1597), .B0(n953), .Y(n910) );
NOR2XLTS U1274 ( .A(n1037), .B(DMP_SFG[0]), .Y(n1038) );
INVX4TS U1275 ( .A(n1546), .Y(n1569) );
OAI32X1TS U1276 ( .A0(n1546), .A1(n1039), .A2(n1038), .B0(n1569), .B1(n1657),
.Y(n600) );
AOI2BB2XLTS U1277 ( .B0(beg_OP), .B1(n1640), .A0N(n1640), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1040) );
NAND3XLTS U1278 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1640), .C(
n1674), .Y(n1340) );
NOR2X1TS U1279 ( .A(n1720), .B(intDX_EWSW[25]), .Y(n1099) );
NOR2XLTS U1280 ( .A(n1099), .B(intDY_EWSW[24]), .Y(n1041) );
AOI22X1TS U1281 ( .A0(intDX_EWSW[25]), .A1(n1720), .B0(intDX_EWSW[24]), .B1(
n1041), .Y(n1045) );
OAI21X1TS U1282 ( .A0(intDX_EWSW[26]), .A1(n1753), .B0(n1042), .Y(n1100) );
NAND2BXLTS U1283 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n1043) );
NOR2X1TS U1284 ( .A(n1639), .B(intDX_EWSW[30]), .Y(n1048) );
NOR2X1TS U1285 ( .A(n1666), .B(intDX_EWSW[29]), .Y(n1046) );
AOI211X1TS U1286 ( .A0(intDY_EWSW[28]), .A1(n1694), .B0(n1048), .C0(n1046),
.Y(n1098) );
NOR3X1TS U1287 ( .A(n1694), .B(n1046), .C(intDY_EWSW[28]), .Y(n1047) );
AOI221X1TS U1288 ( .A0(intDX_EWSW[30]), .A1(n1639), .B0(intDX_EWSW[29]),
.B1(n1666), .C0(n1047), .Y(n1049) );
AOI2BB2X1TS U1289 ( .B0(n1050), .B1(n1098), .A0N(n1049), .A1N(n1048), .Y(
n1104) );
NOR2X1TS U1290 ( .A(n1679), .B(intDX_EWSW[17]), .Y(n1086) );
OAI22X1TS U1291 ( .A0(n959), .A1(intDX_EWSW[10]), .B0(n1751), .B1(
intDX_EWSW[11]), .Y(n1129) );
INVX2TS U1292 ( .A(n1129), .Y(n1070) );
OAI211XLTS U1293 ( .A0(intDX_EWSW[8]), .A1(n1684), .B0(n1067), .C0(n1070),
.Y(n1081) );
OAI2BB1X1TS U1294 ( .A0N(n1658), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n1051) );
OAI22X1TS U1295 ( .A0(intDY_EWSW[4]), .A1(n1051), .B0(n1658), .B1(
intDY_EWSW[5]), .Y(n1062) );
OAI2BB1X1TS U1296 ( .A0N(n1637), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n1052) );
OAI22X1TS U1297 ( .A0(intDY_EWSW[6]), .A1(n1052), .B0(n1637), .B1(
intDY_EWSW[7]), .Y(n1061) );
OAI21XLTS U1298 ( .A0(intDX_EWSW[1]), .A1(n1683), .B0(intDX_EWSW[0]), .Y(
n1053) );
OAI2BB2XLTS U1299 ( .B0(intDY_EWSW[0]), .B1(n1053), .A0N(intDX_EWSW[1]),
.A1N(n1683), .Y(n1055) );
OAI211XLTS U1300 ( .A0(n1678), .A1(intDX_EWSW[3]), .B0(n1055), .C0(n1054),
.Y(n1058) );
OAI21XLTS U1301 ( .A0(intDX_EWSW[3]), .A1(n1678), .B0(intDX_EWSW[2]), .Y(
n1056) );
AOI2BB2XLTS U1302 ( .B0(intDX_EWSW[3]), .B1(n1678), .A0N(intDY_EWSW[2]),
.A1N(n1056), .Y(n1057) );
AOI222X1TS U1303 ( .A0(intDY_EWSW[4]), .A1(n1636), .B0(n1058), .B1(n1057),
.C0(intDY_EWSW[5]), .C1(n1658), .Y(n1060) );
AOI22X1TS U1304 ( .A0(intDY_EWSW[7]), .A1(n1637), .B0(intDY_EWSW[6]), .B1(
n1663), .Y(n1059) );
OAI32X1TS U1305 ( .A0(n1062), .A1(n1061), .A2(n1060), .B0(n1059), .B1(n1061),
.Y(n1080) );
OA22X1TS U1306 ( .A0(n1688), .A1(intDX_EWSW[14]), .B0(n1752), .B1(
intDX_EWSW[15]), .Y(n1077) );
OAI21XLTS U1307 ( .A0(intDX_EWSW[13]), .A1(n1681), .B0(intDX_EWSW[12]), .Y(
n1064) );
OAI2BB2XLTS U1308 ( .B0(intDY_EWSW[12]), .B1(n1064), .A0N(intDX_EWSW[13]),
.A1N(n1681), .Y(n1076) );
NOR2XLTS U1309 ( .A(n1065), .B(intDY_EWSW[10]), .Y(n1066) );
AOI22X1TS U1310 ( .A0(intDX_EWSW[11]), .A1(n1751), .B0(intDX_EWSW[10]), .B1(
n1066), .Y(n1072) );
NAND2BXLTS U1311 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1069) );
NAND3XLTS U1312 ( .A(n1684), .B(n1067), .C(intDX_EWSW[8]), .Y(n1068) );
AOI21X1TS U1313 ( .A0(n1069), .A1(n1068), .B0(n1079), .Y(n1071) );
OAI2BB2XLTS U1314 ( .B0(n1072), .B1(n1079), .A0N(n1071), .A1N(n1070), .Y(
n1075) );
OAI2BB2XLTS U1315 ( .B0(intDY_EWSW[14]), .B1(n1073), .A0N(intDX_EWSW[15]),
.A1N(n1752), .Y(n1074) );
AOI211X1TS U1316 ( .A0(n1077), .A1(n1076), .B0(n1075), .C0(n1074), .Y(n1078)
);
OAI31X1TS U1317 ( .A0(n1081), .A1(n1080), .A2(n1079), .B0(n1078), .Y(n1084)
);
OA22X1TS U1318 ( .A0(n1643), .A1(intDX_EWSW[22]), .B0(n1693), .B1(
intDX_EWSW[23]), .Y(n1096) );
OAI2BB2XLTS U1319 ( .B0(intDY_EWSW[20]), .B1(n1085), .A0N(intDX_EWSW[21]),
.A1N(n1682), .Y(n1095) );
AOI22X1TS U1320 ( .A0(intDX_EWSW[17]), .A1(n1679), .B0(intDX_EWSW[16]), .B1(
n1087), .Y(n1090) );
OAI32X1TS U1321 ( .A0(n1121), .A1(n1091), .A2(n1090), .B0(n1089), .B1(n1091),
.Y(n1094) );
OAI21XLTS U1322 ( .A0(intDX_EWSW[23]), .A1(n1693), .B0(intDX_EWSW[22]), .Y(
n1092) );
OAI2BB2XLTS U1323 ( .B0(intDY_EWSW[22]), .B1(n1092), .A0N(intDX_EWSW[23]),
.A1N(n1693), .Y(n1093) );
AOI211X1TS U1324 ( .A0(n1096), .A1(n1095), .B0(n1094), .C0(n1093), .Y(n1102)
);
NAND2BXLTS U1325 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1097) );
NAND4BBX1TS U1326 ( .AN(n1100), .BN(n1099), .C(n1098), .D(n1097), .Y(n1101)
);
AOI32X1TS U1327 ( .A0(n1104), .A1(n1103), .A2(n1102), .B0(n1101), .B1(n1104),
.Y(n1105) );
INVX2TS U1328 ( .A(Shift_reg_FLAGS_7_6), .Y(n1106) );
INVX4TS U1329 ( .A(n1111), .Y(n1205) );
BUFX4TS U1330 ( .A(n1106), .Y(n1200) );
AOI22X1TS U1331 ( .A0(intDX_EWSW[6]), .A1(n1151), .B0(DMP_EXP_EWSW[6]), .B1(
n1200), .Y(n1107) );
OAI21XLTS U1332 ( .A0(n1672), .A1(n1205), .B0(n1107), .Y(n828) );
AOI22X1TS U1333 ( .A0(intDX_EWSW[7]), .A1(n1151), .B0(DMP_EXP_EWSW[7]), .B1(
n1408), .Y(n1108) );
OAI21XLTS U1334 ( .A0(n1673), .A1(n1205), .B0(n1108), .Y(n827) );
AOI22X1TS U1335 ( .A0(intDX_EWSW[4]), .A1(n1151), .B0(DMP_EXP_EWSW[4]), .B1(
n1200), .Y(n1109) );
OAI21XLTS U1336 ( .A0(n1686), .A1(n1205), .B0(n1109), .Y(n830) );
AOI22X1TS U1337 ( .A0(intDX_EWSW[5]), .A1(n1151), .B0(DMP_EXP_EWSW[5]), .B1(
n1200), .Y(n1110) );
OAI21XLTS U1338 ( .A0(n1641), .A1(n1205), .B0(n1110), .Y(n829) );
INVX3TS U1339 ( .A(n1151), .Y(n1186) );
AOI22X1TS U1340 ( .A0(intDX_EWSW[16]), .A1(n1111), .B0(DmP_EXP_EWSW[16]),
.B1(n1344), .Y(n1112) );
OAI21XLTS U1341 ( .A0(n1689), .A1(n1186), .B0(n1112), .Y(n659) );
OAI22X1TS U1342 ( .A0(n1720), .A1(intDX_EWSW[25]), .B0(n1753), .B1(
intDX_EWSW[26]), .Y(n1113) );
AOI221X1TS U1343 ( .A0(n1720), .A1(intDX_EWSW[25]), .B0(intDX_EWSW[26]),
.B1(n1753), .C0(n1113), .Y(n1119) );
OAI22X1TS U1344 ( .A0(n1691), .A1(intDX_EWSW[27]), .B0(n1694), .B1(
intDY_EWSW[28]), .Y(n1114) );
OAI22X1TS U1345 ( .A0(n1692), .A1(intDY_EWSW[29]), .B0(n1644), .B1(
intDY_EWSW[30]), .Y(n1115) );
AOI221X1TS U1346 ( .A0(n1692), .A1(intDY_EWSW[29]), .B0(intDY_EWSW[30]),
.B1(n1644), .C0(n1115), .Y(n1117) );
AOI2BB2XLTS U1347 ( .B0(intDX_EWSW[7]), .B1(n1673), .A0N(n1673), .A1N(
intDX_EWSW[7]), .Y(n1116) );
NAND4XLTS U1348 ( .A(n1119), .B(n1118), .C(n1117), .D(n1116), .Y(n1147) );
OAI22X1TS U1349 ( .A0(n1683), .A1(intDX_EWSW[1]), .B0(n1679), .B1(
intDX_EWSW[17]), .Y(n1120) );
OAI22X1TS U1350 ( .A0(n1690), .A1(intDX_EWSW[20]), .B0(n1682), .B1(
intDX_EWSW[21]), .Y(n1122) );
OAI22X1TS U1351 ( .A0(n1643), .A1(intDX_EWSW[22]), .B0(n1693), .B1(
intDX_EWSW[23]), .Y(n1123) );
NAND4XLTS U1352 ( .A(n1127), .B(n1126), .C(n1125), .D(n1124), .Y(n1146) );
OAI22X1TS U1353 ( .A0(n1629), .A1(intDX_EWSW[24]), .B0(n1680), .B1(
intDX_EWSW[9]), .Y(n1128) );
AOI221X1TS U1354 ( .A0(n1629), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1680), .C0(n1128), .Y(n1135) );
OAI22X1TS U1355 ( .A0(n1687), .A1(intDX_EWSW[12]), .B0(n1681), .B1(
intDX_EWSW[13]), .Y(n1130) );
OAI22X1TS U1356 ( .A0(n1688), .A1(intDX_EWSW[14]), .B0(n1752), .B1(
intDX_EWSW[15]), .Y(n1131) );
NAND4XLTS U1357 ( .A(n1135), .B(n1134), .C(n1133), .D(n1132), .Y(n1145) );
OAI22X1TS U1358 ( .A0(n1689), .A1(intDX_EWSW[16]), .B0(n1642), .B1(
intDX_EWSW[0]), .Y(n1136) );
AOI221X1TS U1359 ( .A0(n1689), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n1642), .C0(n1136), .Y(n1143) );
OAI22X1TS U1360 ( .A0(n1685), .A1(intDX_EWSW[2]), .B0(n1678), .B1(
intDX_EWSW[3]), .Y(n1137) );
OAI22X1TS U1361 ( .A0(n1686), .A1(intDX_EWSW[4]), .B0(n1641), .B1(
intDX_EWSW[5]), .Y(n1138) );
AOI221X1TS U1362 ( .A0(n1686), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1641), .C0(n1138), .Y(n1141) );
OAI22X1TS U1363 ( .A0(n1684), .A1(intDX_EWSW[8]), .B0(n1672), .B1(
intDX_EWSW[6]), .Y(n1139) );
NAND4XLTS U1364 ( .A(n1143), .B(n1142), .C(n1141), .D(n1140), .Y(n1144) );
NOR4X1TS U1365 ( .A(n1147), .B(n1146), .C(n1145), .D(n1144), .Y(n1410) );
CLKXOR2X2TS U1366 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1407) );
INVX2TS U1367 ( .A(n1407), .Y(n1150) );
INVX4TS U1368 ( .A(n1111), .Y(n1419) );
OAI21XLTS U1369 ( .A0(n1150), .A1(n1200), .B0(n1186), .Y(n1148) );
AOI22X1TS U1370 ( .A0(intDX_EWSW[31]), .A1(n1148), .B0(SIGN_FLAG_EXP), .B1(
n956), .Y(n1149) );
AOI22X1TS U1371 ( .A0(intDY_EWSW[28]), .A1(n1111), .B0(DMP_EXP_EWSW[28]),
.B1(n1200), .Y(n1152) );
OAI21XLTS U1372 ( .A0(n1694), .A1(n1417), .B0(n1152), .Y(n806) );
AOI22X1TS U1373 ( .A0(intDX_EWSW[19]), .A1(n1111), .B0(DmP_EXP_EWSW[19]),
.B1(n1344), .Y(n1153) );
OAI21XLTS U1374 ( .A0(n1645), .A1(n1417), .B0(n1153), .Y(n653) );
AOI22X1TS U1375 ( .A0(intDX_EWSW[22]), .A1(n1111), .B0(DmP_EXP_EWSW[22]),
.B1(n1344), .Y(n1154) );
OAI21XLTS U1376 ( .A0(n1643), .A1(n1417), .B0(n1154), .Y(n647) );
AOI22X1TS U1377 ( .A0(intDX_EWSW[20]), .A1(n1111), .B0(DmP_EXP_EWSW[20]),
.B1(n1344), .Y(n1155) );
OAI21XLTS U1378 ( .A0(n1690), .A1(n1417), .B0(n1155), .Y(n651) );
AOI22X1TS U1379 ( .A0(intDX_EWSW[17]), .A1(n1111), .B0(DmP_EXP_EWSW[17]),
.B1(n1344), .Y(n1156) );
OAI21XLTS U1380 ( .A0(n1679), .A1(n1417), .B0(n1156), .Y(n657) );
AOI22X1TS U1381 ( .A0(intDX_EWSW[14]), .A1(n1111), .B0(DmP_EXP_EWSW[14]),
.B1(n1106), .Y(n1157) );
OAI21XLTS U1382 ( .A0(n1688), .A1(n1186), .B0(n1157), .Y(n663) );
AOI22X1TS U1383 ( .A0(intDX_EWSW[21]), .A1(n1111), .B0(DmP_EXP_EWSW[21]),
.B1(n1344), .Y(n1158) );
OAI21XLTS U1384 ( .A0(n1682), .A1(n1417), .B0(n1158), .Y(n649) );
AOI22X1TS U1385 ( .A0(intDX_EWSW[13]), .A1(n1111), .B0(DmP_EXP_EWSW[13]),
.B1(n1344), .Y(n1159) );
OAI21XLTS U1386 ( .A0(n1681), .A1(n1186), .B0(n1159), .Y(n665) );
AOI22X1TS U1387 ( .A0(intDX_EWSW[15]), .A1(n1111), .B0(DmP_EXP_EWSW[15]),
.B1(n1344), .Y(n1161) );
OAI21XLTS U1388 ( .A0(n1752), .A1(n1186), .B0(n1161), .Y(n661) );
AOI22X1TS U1389 ( .A0(intDX_EWSW[0]), .A1(n1151), .B0(DMP_EXP_EWSW[0]), .B1(
n1408), .Y(n1162) );
OAI21XLTS U1390 ( .A0(n1642), .A1(n1419), .B0(n1162), .Y(n834) );
AOI22X1TS U1391 ( .A0(intDX_EWSW[9]), .A1(n1151), .B0(DMP_EXP_EWSW[9]), .B1(
n1200), .Y(n1163) );
OAI21XLTS U1392 ( .A0(n1680), .A1(n1205), .B0(n1163), .Y(n825) );
AOI22X1TS U1393 ( .A0(intDX_EWSW[1]), .A1(n1151), .B0(DMP_EXP_EWSW[1]), .B1(
n1408), .Y(n1164) );
AOI22X1TS U1394 ( .A0(intDX_EWSW[2]), .A1(n1151), .B0(DMP_EXP_EWSW[2]), .B1(
n1200), .Y(n1165) );
OAI21XLTS U1395 ( .A0(n1685), .A1(n1205), .B0(n1165), .Y(n832) );
AOI22X1TS U1396 ( .A0(intDX_EWSW[8]), .A1(n1151), .B0(DMP_EXP_EWSW[8]), .B1(
n1344), .Y(n1166) );
OAI21XLTS U1397 ( .A0(n1684), .A1(n1205), .B0(n1166), .Y(n826) );
AOI22X1TS U1398 ( .A0(intDX_EWSW[3]), .A1(n1151), .B0(DMP_EXP_EWSW[3]), .B1(
n1408), .Y(n1167) );
OAI21XLTS U1399 ( .A0(n1678), .A1(n1419), .B0(n1167), .Y(n831) );
BUFX4TS U1400 ( .A(n1111), .Y(n1184) );
AOI22X1TS U1401 ( .A0(intDY_EWSW[29]), .A1(n1184), .B0(DMP_EXP_EWSW[29]),
.B1(n1200), .Y(n1168) );
OAI21XLTS U1402 ( .A0(n1692), .A1(n1417), .B0(n1168), .Y(n805) );
AOI22X1TS U1403 ( .A0(intDY_EWSW[30]), .A1(n1184), .B0(DMP_EXP_EWSW[30]),
.B1(n1200), .Y(n1169) );
OAI21XLTS U1404 ( .A0(n1644), .A1(n1417), .B0(n1169), .Y(n804) );
AOI22X1TS U1405 ( .A0(intDX_EWSW[7]), .A1(n1184), .B0(DmP_EXP_EWSW[7]), .B1(
n1408), .Y(n1170) );
OAI21XLTS U1406 ( .A0(n1673), .A1(n1186), .B0(n1170), .Y(n677) );
AOI22X1TS U1407 ( .A0(intDX_EWSW[5]), .A1(n1184), .B0(DmP_EXP_EWSW[5]), .B1(
n1408), .Y(n1171) );
OAI21XLTS U1408 ( .A0(n1641), .A1(n1186), .B0(n1171), .Y(n681) );
AOI22X1TS U1409 ( .A0(intDX_EWSW[6]), .A1(n1184), .B0(DmP_EXP_EWSW[6]), .B1(
n1408), .Y(n1172) );
OAI21XLTS U1410 ( .A0(n1672), .A1(n1186), .B0(n1172), .Y(n679) );
AOI22X1TS U1411 ( .A0(intDX_EWSW[4]), .A1(n1184), .B0(DmP_EXP_EWSW[4]), .B1(
n1408), .Y(n1173) );
OAI21XLTS U1412 ( .A0(n1686), .A1(n1417), .B0(n1173), .Y(n683) );
AOI22X1TS U1413 ( .A0(intDX_EWSW[18]), .A1(n1184), .B0(DmP_EXP_EWSW[18]),
.B1(n1344), .Y(n1174) );
OAI21XLTS U1414 ( .A0(n1695), .A1(n1417), .B0(n1174), .Y(n655) );
AOI22X1TS U1415 ( .A0(intDX_EWSW[0]), .A1(n1184), .B0(DmP_EXP_EWSW[0]), .B1(
n1200), .Y(n1175) );
OAI21XLTS U1416 ( .A0(n1642), .A1(n1417), .B0(n1175), .Y(n691) );
AOI22X1TS U1417 ( .A0(intDX_EWSW[10]), .A1(n1184), .B0(DmP_EXP_EWSW[10]),
.B1(n1200), .Y(n1176) );
OAI21XLTS U1418 ( .A0(n959), .A1(n1186), .B0(n1176), .Y(n671) );
AOI22X1TS U1419 ( .A0(intDX_EWSW[1]), .A1(n1184), .B0(DmP_EXP_EWSW[1]), .B1(
n1344), .Y(n1177) );
OAI21XLTS U1420 ( .A0(n1683), .A1(n1417), .B0(n1177), .Y(n689) );
AOI22X1TS U1421 ( .A0(intDX_EWSW[9]), .A1(n1184), .B0(DmP_EXP_EWSW[9]), .B1(
n1344), .Y(n1178) );
OAI21XLTS U1422 ( .A0(n1680), .A1(n1186), .B0(n1178), .Y(n673) );
AOI22X1TS U1423 ( .A0(intDX_EWSW[2]), .A1(n1184), .B0(DmP_EXP_EWSW[2]), .B1(
n1200), .Y(n1179) );
OAI21XLTS U1424 ( .A0(n1685), .A1(n1417), .B0(n1179), .Y(n687) );
AOI22X1TS U1425 ( .A0(intDX_EWSW[12]), .A1(n1184), .B0(DmP_EXP_EWSW[12]),
.B1(n1106), .Y(n1180) );
OAI21XLTS U1426 ( .A0(n1687), .A1(n1186), .B0(n1180), .Y(n667) );
AOI22X1TS U1427 ( .A0(intDX_EWSW[8]), .A1(n1184), .B0(DmP_EXP_EWSW[8]), .B1(
n1106), .Y(n1181) );
OAI21XLTS U1428 ( .A0(n1684), .A1(n1186), .B0(n1181), .Y(n675) );
AOI22X1TS U1429 ( .A0(intDX_EWSW[11]), .A1(n1184), .B0(DmP_EXP_EWSW[11]),
.B1(n1106), .Y(n1182) );
OAI21XLTS U1430 ( .A0(n1751), .A1(n1186), .B0(n1182), .Y(n669) );
AOI22X1TS U1431 ( .A0(intDX_EWSW[3]), .A1(n1184), .B0(DmP_EXP_EWSW[3]), .B1(
n1106), .Y(n1183) );
OAI21XLTS U1432 ( .A0(n1678), .A1(n1417), .B0(n1183), .Y(n685) );
AOI22X1TS U1433 ( .A0(DmP_EXP_EWSW[27]), .A1(n1344), .B0(intDX_EWSW[27]),
.B1(n1184), .Y(n1185) );
OAI21XLTS U1434 ( .A0(n1691), .A1(n1186), .B0(n1185), .Y(n641) );
BUFX3TS U1435 ( .A(n1151), .Y(n1203) );
AOI22X1TS U1436 ( .A0(intDX_EWSW[16]), .A1(n1203), .B0(DMP_EXP_EWSW[16]),
.B1(n1200), .Y(n1187) );
OAI21XLTS U1437 ( .A0(n1689), .A1(n1205), .B0(n1187), .Y(n818) );
AOI222X1TS U1438 ( .A0(n1111), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1408), .C0(intDY_EWSW[23]), .C1(n1203), .Y(n1188) );
INVX2TS U1439 ( .A(n1188), .Y(n645) );
AOI22X1TS U1440 ( .A0(intDX_EWSW[22]), .A1(n1151), .B0(DMP_EXP_EWSW[22]),
.B1(n1408), .Y(n1189) );
OAI21XLTS U1441 ( .A0(n1643), .A1(n1419), .B0(n1189), .Y(n812) );
AOI22X1TS U1442 ( .A0(n985), .A1(n1344), .B0(intDX_EWSW[27]), .B1(n1151),
.Y(n1190) );
OAI21XLTS U1443 ( .A0(n1691), .A1(n1419), .B0(n1190), .Y(n807) );
AOI22X1TS U1444 ( .A0(intDX_EWSW[20]), .A1(n1151), .B0(DMP_EXP_EWSW[20]),
.B1(n1408), .Y(n1191) );
OAI21XLTS U1445 ( .A0(n1690), .A1(n1419), .B0(n1191), .Y(n814) );
AOI22X1TS U1446 ( .A0(DMP_EXP_EWSW[23]), .A1(n1344), .B0(intDX_EWSW[23]),
.B1(n1151), .Y(n1192) );
OAI21XLTS U1447 ( .A0(n1693), .A1(n1205), .B0(n1192), .Y(n811) );
AOI22X1TS U1448 ( .A0(intDX_EWSW[21]), .A1(n1151), .B0(DMP_EXP_EWSW[21]),
.B1(n1200), .Y(n1193) );
OAI21XLTS U1449 ( .A0(n1682), .A1(n1419), .B0(n1193), .Y(n813) );
AOI22X1TS U1450 ( .A0(intDX_EWSW[19]), .A1(n1203), .B0(DMP_EXP_EWSW[19]),
.B1(n1200), .Y(n1194) );
OAI21XLTS U1451 ( .A0(n1645), .A1(n1419), .B0(n1194), .Y(n815) );
AOI22X1TS U1452 ( .A0(intDX_EWSW[18]), .A1(n1203), .B0(DMP_EXP_EWSW[18]),
.B1(n1408), .Y(n1195) );
OAI21XLTS U1453 ( .A0(n1695), .A1(n1205), .B0(n1195), .Y(n816) );
AOI22X1TS U1454 ( .A0(intDX_EWSW[10]), .A1(n1203), .B0(DMP_EXP_EWSW[10]),
.B1(n1200), .Y(n1196) );
OAI21XLTS U1455 ( .A0(n959), .A1(n1205), .B0(n1196), .Y(n824) );
AOI22X1TS U1456 ( .A0(intDX_EWSW[14]), .A1(n1203), .B0(DMP_EXP_EWSW[14]),
.B1(n1344), .Y(n1197) );
OAI21XLTS U1457 ( .A0(n1688), .A1(n1205), .B0(n1197), .Y(n820) );
AOI22X1TS U1458 ( .A0(intDX_EWSW[17]), .A1(n1203), .B0(DMP_EXP_EWSW[17]),
.B1(n1408), .Y(n1198) );
OAI21XLTS U1459 ( .A0(n1679), .A1(n1205), .B0(n1198), .Y(n817) );
AOI22X1TS U1460 ( .A0(intDX_EWSW[12]), .A1(n1203), .B0(DMP_EXP_EWSW[12]),
.B1(n1344), .Y(n1199) );
OAI21XLTS U1461 ( .A0(n1687), .A1(n1205), .B0(n1199), .Y(n822) );
AOI22X1TS U1462 ( .A0(intDX_EWSW[11]), .A1(n1203), .B0(DMP_EXP_EWSW[11]),
.B1(n1408), .Y(n1201) );
OAI21XLTS U1463 ( .A0(n1751), .A1(n1205), .B0(n1201), .Y(n823) );
AOI22X1TS U1464 ( .A0(intDX_EWSW[13]), .A1(n1203), .B0(DMP_EXP_EWSW[13]),
.B1(n1408), .Y(n1202) );
OAI21XLTS U1465 ( .A0(n1681), .A1(n1205), .B0(n1202), .Y(n821) );
AOI22X1TS U1466 ( .A0(intDX_EWSW[15]), .A1(n1203), .B0(DMP_EXP_EWSW[15]),
.B1(n1408), .Y(n1204) );
NAND4X1TS U1467 ( .A(n1627), .B(n1011), .C(n957), .D(n1625), .Y(n1329) );
NOR2BX1TS U1468 ( .AN(n1219), .B(Raw_mant_NRM_SWR[18]), .Y(n1321) );
NOR3X1TS U1469 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[15]), .C(
Raw_mant_NRM_SWR[16]), .Y(n1322) );
NAND2X1TS U1470 ( .A(n1320), .B(n1633), .Y(n1206) );
NAND2X1TS U1471 ( .A(n1229), .B(n1634), .Y(n1218) );
NOR2X1TS U1472 ( .A(Raw_mant_NRM_SWR[10]), .B(n1218), .Y(n1224) );
NAND2X1TS U1473 ( .A(n1224), .B(n1653), .Y(n1210) );
NOR3X1TS U1474 ( .A(Raw_mant_NRM_SWR[9]), .B(Raw_mant_NRM_SWR[8]), .C(n1210),
.Y(n1207) );
NAND2X1TS U1475 ( .A(n1207), .B(n1654), .Y(n1227) );
NOR3X2TS U1476 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .C(n1227),
.Y(n1221) );
NOR2XLTS U1477 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1209)
);
NAND2X1TS U1478 ( .A(n1221), .B(n1635), .Y(n1331) );
OAI21X1TS U1479 ( .A0(n1209), .A1(n1331), .B0(n1208), .Y(n1235) );
NOR2XLTS U1480 ( .A(Raw_mant_NRM_SWR[9]), .B(Raw_mant_NRM_SWR[8]), .Y(n1211)
);
OAI21XLTS U1481 ( .A0(n1211), .A1(n1210), .B0(n1332), .Y(n1212) );
AOI211X1TS U1482 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1221), .B0(n1235), .C0(
n1212), .Y(n1214) );
NOR3X1TS U1483 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .C(n1331),
.Y(n1213) );
NAND2X1TS U1484 ( .A(n1213), .B(n990), .Y(n1223) );
NAND2X1TS U1485 ( .A(Raw_mant_NRM_SWR[1]), .B(n1213), .Y(n1324) );
AOI31X1TS U1486 ( .A0(n1214), .A1(n1223), .A2(n1324), .B0(n953), .Y(n1319)
);
NAND2X1TS U1487 ( .A(Raw_mant_NRM_SWR[14]), .B(n1320), .Y(n1237) );
AOI32X1TS U1488 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n957), .A2(n1626), .B0(
Raw_mant_NRM_SWR[22]), .B1(n957), .Y(n1216) );
AOI32X1TS U1489 ( .A0(n1011), .A1(n1237), .A2(n1216), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1237), .Y(n1217) );
NOR3X1TS U1490 ( .A(Raw_mant_NRM_SWR[12]), .B(n1656), .C(n1218), .Y(n1327)
);
AOI21X1TS U1491 ( .A0(n1221), .A1(n1220), .B0(n1228), .Y(n1222) );
NAND2X1TS U1492 ( .A(Raw_mant_NRM_SWR[12]), .B(n1229), .Y(n1325) );
OAI211X1TS U1493 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1223), .B0(n1222), .C0(
n1325), .Y(n1335) );
OR2X2TS U1494 ( .A(n953), .B(n1243), .Y(n1362) );
INVX2TS U1495 ( .A(n1362), .Y(n1358) );
BUFX4TS U1496 ( .A(n1296), .Y(n1370) );
NOR2XLTS U1497 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1233) );
NOR2X1TS U1498 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1231) );
AOI211X1TS U1499 ( .A0(n1233), .A1(n1232), .B0(Raw_mant_NRM_SWR[24]), .C0(
Raw_mant_NRM_SWR[25]), .Y(n1234) );
AOI21X1TS U1500 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n953), .B0(n1337), .Y(
n1239) );
NOR2X2TS U1501 ( .A(n955), .B(n1239), .Y(n1379) );
NAND2X2TS U1502 ( .A(n1243), .B(Shift_reg_FLAGS_7[1]), .Y(n1372) );
INVX2TS U1503 ( .A(n1372), .Y(n1360) );
AOI22X1TS U1504 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1360), .B0(n1296), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1242) );
INVX4TS U1505 ( .A(n1362), .Y(n1380) );
AOI22X1TS U1506 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1358), .B0(n988), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1241) );
NAND2X1TS U1507 ( .A(n1242), .B(n1241), .Y(n1269) );
AOI22X1TS U1508 ( .A0(n1385), .A1(Data_array_SWR[3]), .B0(n1240), .B1(n1269),
.Y(n1245) );
NAND2X1TS U1509 ( .A(n1337), .B(n1243), .Y(n1303) );
NAND2X1TS U1510 ( .A(Raw_mant_NRM_SWR[19]), .B(n1280), .Y(n1244) );
AOI22X1TS U1511 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1360), .B0(n1296), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1247) );
AOI22X1TS U1512 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1358), .B0(n988), .B1(n983), .Y(n1246) );
NAND2X1TS U1513 ( .A(n1247), .B(n1246), .Y(n1285) );
AOI22X1TS U1514 ( .A0(n1385), .A1(Data_array_SWR[7]), .B0(n1240), .B1(n1285),
.Y(n1249) );
NAND2X1TS U1515 ( .A(Raw_mant_NRM_SWR[15]), .B(n1280), .Y(n1248) );
AOI22X1TS U1516 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1360), .B0(n1370), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1251) );
AOI22X1TS U1517 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n1358), .B0(n988), .B1(n984), .Y(n1250) );
NAND2X1TS U1518 ( .A(n1251), .B(n1250), .Y(n1378) );
AOI22X1TS U1519 ( .A0(n1385), .A1(Data_array_SWR[2]), .B0(n1240), .B1(n1378),
.Y(n1253) );
NAND2X1TS U1520 ( .A(Raw_mant_NRM_SWR[20]), .B(n1280), .Y(n1252) );
AOI22X1TS U1521 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1360), .B0(n1296), .B1(
n983), .Y(n1255) );
AOI22X1TS U1522 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n1380), .B0(n988), .B1(n977), .Y(n1254) );
NAND2X1TS U1523 ( .A(n1255), .B(n1254), .Y(n1289) );
AOI22X1TS U1524 ( .A0(n955), .A1(Data_array_SWR[6]), .B0(n1240), .B1(n1289),
.Y(n1257) );
NAND2X1TS U1525 ( .A(Raw_mant_NRM_SWR[16]), .B(n1280), .Y(n1256) );
AOI22X1TS U1526 ( .A0(n955), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1280), .Y(n1260) );
NAND2X1TS U1527 ( .A(n1258), .B(n1360), .Y(n1309) );
AOI22X1TS U1528 ( .A0(n955), .A1(Data_array_SWR[21]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n1280), .Y(n1262) );
AOI22X1TS U1529 ( .A0(n955), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1280), .Y(n1264) );
AOI22X1TS U1530 ( .A0(n1385), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1280), .Y(n1267) );
AOI22X1TS U1531 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n1380), .B0(n1370), .B1(
n984), .Y(n1272) );
AOI22X1TS U1532 ( .A0(n1385), .A1(Data_array_SWR[1]), .B0(
Raw_mant_NRM_SWR[23]), .B1(n1377), .Y(n1271) );
NAND2X1TS U1533 ( .A(n1379), .B(n1269), .Y(n1270) );
AOI22X1TS U1534 ( .A0(n1385), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1280), .Y(n1274) );
AOI22X1TS U1535 ( .A0(n1385), .A1(Data_array_SWR[19]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1280), .Y(n1278) );
AOI22X1TS U1536 ( .A0(n1385), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1280), .Y(n1283) );
AOI22X1TS U1537 ( .A0(n1385), .A1(Data_array_SWR[5]), .B0(n1379), .B1(n1285),
.Y(n1287) );
NAND2X1TS U1538 ( .A(Raw_mant_NRM_SWR[19]), .B(n1377), .Y(n1286) );
AOI22X1TS U1539 ( .A0(n1385), .A1(Data_array_SWR[4]), .B0(n1379), .B1(n1289),
.Y(n1291) );
NAND2X1TS U1540 ( .A(Raw_mant_NRM_SWR[20]), .B(n1377), .Y(n1290) );
AOI21X1TS U1541 ( .A0(n1380), .A1(n990), .B0(n989), .Y(n1357) );
OAI22X1TS U1542 ( .A0(n1293), .A1(n986), .B0(n1387), .B1(n1646), .Y(n1294)
);
AOI21X1TS U1543 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1377), .B0(n1294), .Y(n1295) );
AOI22X1TS U1544 ( .A0(n988), .A1(DmP_mant_SHT1_SW[18]), .B0(n1296), .B1(n978), .Y(n1297) );
AOI21X1TS U1545 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n1380), .B0(n1298), .Y(n1365) );
OAI22X1TS U1546 ( .A0(n1304), .A1(n986), .B0(n1660), .B1(n1309), .Y(n1299)
);
AOI21X1TS U1547 ( .A0(n955), .A1(Data_array_SWR[18]), .B0(n1299), .Y(n1300)
);
AOI22X1TS U1548 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1360), .B0(n1296), .B1(n979), .Y(n1301) );
AOI21X1TS U1549 ( .A0(n989), .A1(DmP_mant_SHT1_SW[14]), .B0(n1302), .Y(n1369) );
OAI22X1TS U1550 ( .A0(n1304), .A1(n1238), .B0(n1660), .B1(n1303), .Y(n1305)
);
AOI21X1TS U1551 ( .A0(n955), .A1(Data_array_SWR[16]), .B0(n1305), .Y(n1306)
);
AOI22X1TS U1552 ( .A0(n988), .A1(DmP_mant_SHT1_SW[8]), .B0(n1296), .B1(n982),
.Y(n1307) );
AOI21X1TS U1553 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1380), .B0(n1308), .Y(
n1375) );
OAI22X1TS U1554 ( .A0(n1310), .A1(n986), .B0(n1631), .B1(n1309), .Y(n1311)
);
AOI21X1TS U1555 ( .A0(n1385), .A1(Data_array_SWR[8]), .B0(n1311), .Y(n1312)
);
INVX2TS U1556 ( .A(n1313), .Y(n1523) );
NOR2XLTS U1557 ( .A(n1523), .B(SIGN_FLAG_SHT1SHT2), .Y(n1314) );
OAI2BB2XLTS U1558 ( .B0(n1314), .B1(n1522), .A0N(n1602), .A1N(
final_result_ieee[31]), .Y(n624) );
AOI2BB2X1TS U1559 ( .B0(DmP_mant_SFG_SWR[13]), .B1(n1012), .A0N(n1012),
.A1N(DmP_mant_SFG_SWR[13]), .Y(n1315) );
AOI2BB2X1TS U1560 ( .B0(DmP_mant_SFG_SWR[12]), .B1(n1459), .A0N(n1638),
.A1N(DmP_mant_SFG_SWR[12]), .Y(n1433) );
NAND2BX1TS U1561 ( .AN(n1433), .B(DMP_SFG[10]), .Y(n1543) );
NAND2X1TS U1562 ( .A(n1315), .B(DMP_SFG[11]), .Y(n1531) );
OAI21X1TS U1563 ( .A0(n1532), .A1(n1543), .B0(n1531), .Y(n1316) );
INVX2TS U1564 ( .A(n1317), .Y(n1318) );
NAND2X1TS U1565 ( .A(n1659), .B(n1318), .Y(DP_OP_15J10_123_2691_n8) );
MX2X1TS U1566 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n692) );
MX2X1TS U1567 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n697) );
MX2X1TS U1568 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n702) );
MX2X1TS U1569 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n707) );
MX2X1TS U1570 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n712) );
MX2X1TS U1571 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n717) );
MX2X1TS U1572 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n722) );
MX2X1TS U1573 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n727) );
AO21XLTS U1574 ( .A0(LZD_output_NRM2_EW[4]), .A1(n953), .B0(n1319), .Y(n610)
);
OAI211X1TS U1575 ( .A0(Raw_mant_NRM_SWR[11]), .A1(Raw_mant_NRM_SWR[13]),
.B0(n1320), .C0(n1633), .Y(n1328) );
OAI2BB1X1TS U1576 ( .A0N(n1322), .A1N(n1633), .B0(n1321), .Y(n1323) );
NAND4XLTS U1577 ( .A(n1325), .B(n1328), .C(n1324), .D(n1323), .Y(n1326) );
OAI21X1TS U1578 ( .A0(n1327), .A1(n1326), .B0(Shift_reg_FLAGS_7[1]), .Y(
n1388) );
OAI2BB1X1TS U1579 ( .A0N(LZD_output_NRM2_EW[3]), .A1N(n953), .B0(n1388), .Y(
n598) );
OAI22X1TS U1580 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1332), .B0(n1331), .B1(
n1702), .Y(n1334) );
OAI31X1TS U1581 ( .A0(n1336), .A1(n1335), .A2(n1334), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1383) );
OAI2BB1X1TS U1582 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n953), .B0(n1383), .Y(
n607) );
AO21XLTS U1583 ( .A0(LZD_output_NRM2_EW[1]), .A1(n953), .B0(n1337), .Y(n604)
);
OAI2BB1X1TS U1584 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n953), .B0(n1372), .Y(
n593) );
OA22X1TS U1585 ( .A0(n1339), .A1(n1338), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[29]), .Y(n836) );
OA21XLTS U1586 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1522),
.Y(n639) );
INVX2TS U1587 ( .A(n1343), .Y(n1341) );
AOI22X1TS U1588 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1341), .B1(n1640), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1589 ( .A(n1341), .B(n1340), .Y(n952) );
NOR2XLTS U1590 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1342) );
AOI32X4TS U1591 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1342), .B1(n1674), .Y(n1346)
);
INVX2TS U1592 ( .A(n1346), .Y(n1345) );
AOI22X1TS U1593 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1343), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1640), .Y(n1347) );
AO22XLTS U1594 ( .A0(n1345), .A1(Shift_reg_FLAGS_7_6), .B0(n1346), .B1(n1347), .Y(n950) );
AOI22X1TS U1595 ( .A0(n1346), .A1(n1344), .B0(n1415), .B1(n1345), .Y(n949)
);
AOI22X1TS U1596 ( .A0(n1346), .A1(n1415), .B0(n1413), .B1(n1345), .Y(n948)
);
AOI22X1TS U1597 ( .A0(n1346), .A1(n1546), .B0(n953), .B1(n1345), .Y(n945) );
AOI22X1TS U1598 ( .A0(n1346), .A1(n953), .B0(n1602), .B1(n1345), .Y(n944) );
BUFX4TS U1599 ( .A(n1351), .Y(n1356) );
BUFX3TS U1600 ( .A(n1351), .Y(n1352) );
AO22XLTS U1601 ( .A0(n1356), .A1(Data_X[1]), .B0(n954), .B1(intDX_EWSW[1]),
.Y(n942) );
BUFX3TS U1602 ( .A(n1351), .Y(n1348) );
AO22XLTS U1603 ( .A0(n1348), .A1(Data_X[2]), .B0(n954), .B1(intDX_EWSW[2]),
.Y(n941) );
BUFX3TS U1604 ( .A(n1351), .Y(n1354) );
AO22XLTS U1605 ( .A0(n1354), .A1(Data_X[3]), .B0(n1355), .B1(intDX_EWSW[3]),
.Y(n940) );
AO22XLTS U1606 ( .A0(n1352), .A1(Data_X[4]), .B0(n954), .B1(intDX_EWSW[4]),
.Y(n939) );
AO22XLTS U1607 ( .A0(n1356), .A1(Data_X[5]), .B0(n954), .B1(intDX_EWSW[5]),
.Y(n938) );
AO22XLTS U1608 ( .A0(n1356), .A1(Data_X[6]), .B0(n1355), .B1(intDX_EWSW[6]),
.Y(n937) );
AO22XLTS U1609 ( .A0(n1351), .A1(Data_X[7]), .B0(n954), .B1(intDX_EWSW[7]),
.Y(n936) );
AO22XLTS U1610 ( .A0(n1354), .A1(Data_X[8]), .B0(n954), .B1(intDX_EWSW[8]),
.Y(n935) );
AO22XLTS U1611 ( .A0(n1354), .A1(Data_X[9]), .B0(n1355), .B1(intDX_EWSW[9]),
.Y(n934) );
AO22XLTS U1612 ( .A0(n1354), .A1(Data_X[11]), .B0(n954), .B1(intDX_EWSW[11]),
.Y(n932) );
INVX2TS U1613 ( .A(n1352), .Y(n1355) );
AO22XLTS U1614 ( .A0(n1356), .A1(Data_X[12]), .B0(n1355), .B1(intDX_EWSW[12]), .Y(n931) );
AO22XLTS U1615 ( .A0(n1352), .A1(Data_X[13]), .B0(n954), .B1(intDX_EWSW[13]),
.Y(n930) );
AO22XLTS U1616 ( .A0(n1351), .A1(Data_X[14]), .B0(n954), .B1(intDX_EWSW[14]),
.Y(n929) );
AO22XLTS U1617 ( .A0(n1356), .A1(Data_X[15]), .B0(n1355), .B1(intDX_EWSW[15]), .Y(n928) );
AO22XLTS U1618 ( .A0(n1348), .A1(Data_X[16]), .B0(n954), .B1(intDX_EWSW[16]),
.Y(n927) );
AO22XLTS U1619 ( .A0(n1356), .A1(Data_X[17]), .B0(n954), .B1(intDX_EWSW[17]),
.Y(n926) );
AO22XLTS U1620 ( .A0(n1351), .A1(Data_X[20]), .B0(n1355), .B1(intDX_EWSW[20]), .Y(n923) );
AO22XLTS U1621 ( .A0(n1352), .A1(Data_X[21]), .B0(n954), .B1(intDX_EWSW[21]),
.Y(n922) );
AO22XLTS U1622 ( .A0(n1352), .A1(Data_X[22]), .B0(n954), .B1(intDX_EWSW[22]),
.Y(n921) );
AO22XLTS U1623 ( .A0(n1348), .A1(Data_X[23]), .B0(n1355), .B1(intDX_EWSW[23]), .Y(n920) );
INVX2TS U1624 ( .A(n1351), .Y(n1349) );
AO22XLTS U1625 ( .A0(n1349), .A1(intDX_EWSW[24]), .B0(n1351), .B1(Data_X[24]), .Y(n919) );
AO22XLTS U1626 ( .A0(n1349), .A1(intDX_EWSW[25]), .B0(n1354), .B1(Data_X[25]), .Y(n918) );
AO22XLTS U1627 ( .A0(n1349), .A1(intDX_EWSW[26]), .B0(n1348), .B1(Data_X[26]), .Y(n917) );
AO22XLTS U1628 ( .A0(n1354), .A1(Data_X[27]), .B0(n1349), .B1(intDX_EWSW[27]), .Y(n916) );
AO22XLTS U1629 ( .A0(n1349), .A1(intDX_EWSW[28]), .B0(n1354), .B1(Data_X[28]), .Y(n915) );
AO22XLTS U1630 ( .A0(n1349), .A1(intDX_EWSW[29]), .B0(n1348), .B1(Data_X[29]), .Y(n914) );
AO22XLTS U1631 ( .A0(n1349), .A1(intDX_EWSW[30]), .B0(n1348), .B1(Data_X[30]), .Y(n913) );
AO22XLTS U1632 ( .A0(n1354), .A1(add_subt), .B0(n1349), .B1(intAS), .Y(n911)
);
AO22XLTS U1633 ( .A0(n1350), .A1(intDY_EWSW[0]), .B0(n1348), .B1(Data_Y[0]),
.Y(n909) );
AO22XLTS U1634 ( .A0(n1349), .A1(intDY_EWSW[1]), .B0(n1348), .B1(Data_Y[1]),
.Y(n908) );
AO22XLTS U1635 ( .A0(n1353), .A1(intDY_EWSW[2]), .B0(n1348), .B1(Data_Y[2]),
.Y(n907) );
INVX2TS U1636 ( .A(n1351), .Y(n1350) );
AO22XLTS U1637 ( .A0(n1353), .A1(intDY_EWSW[3]), .B0(n1348), .B1(Data_Y[3]),
.Y(n906) );
AO22XLTS U1638 ( .A0(n1350), .A1(intDY_EWSW[4]), .B0(n1348), .B1(Data_Y[4]),
.Y(n905) );
AO22XLTS U1639 ( .A0(n1353), .A1(intDY_EWSW[5]), .B0(n1348), .B1(Data_Y[5]),
.Y(n904) );
AO22XLTS U1640 ( .A0(n1350), .A1(intDY_EWSW[6]), .B0(n1351), .B1(Data_Y[6]),
.Y(n903) );
AO22XLTS U1641 ( .A0(n1350), .A1(intDY_EWSW[7]), .B0(n1356), .B1(Data_Y[7]),
.Y(n902) );
AO22XLTS U1642 ( .A0(n1350), .A1(intDY_EWSW[8]), .B0(n1356), .B1(Data_Y[8]),
.Y(n901) );
AO22XLTS U1643 ( .A0(n1353), .A1(intDY_EWSW[9]), .B0(n1351), .B1(Data_Y[9]),
.Y(n900) );
AO22XLTS U1644 ( .A0(n1353), .A1(intDY_EWSW[10]), .B0(n1356), .B1(Data_Y[10]), .Y(n899) );
AO22XLTS U1645 ( .A0(n1353), .A1(intDY_EWSW[11]), .B0(n1356), .B1(Data_Y[11]), .Y(n898) );
AO22XLTS U1646 ( .A0(n1353), .A1(intDY_EWSW[12]), .B0(n1356), .B1(Data_Y[12]), .Y(n897) );
AO22XLTS U1647 ( .A0(n1350), .A1(intDY_EWSW[13]), .B0(n1356), .B1(Data_Y[13]), .Y(n896) );
AO22XLTS U1648 ( .A0(n1353), .A1(intDY_EWSW[14]), .B0(n1356), .B1(Data_Y[14]), .Y(n895) );
AO22XLTS U1649 ( .A0(n1353), .A1(intDY_EWSW[15]), .B0(n1356), .B1(Data_Y[15]), .Y(n894) );
AO22XLTS U1650 ( .A0(n1353), .A1(intDY_EWSW[16]), .B0(n1356), .B1(Data_Y[16]), .Y(n893) );
AO22XLTS U1651 ( .A0(n1350), .A1(intDY_EWSW[17]), .B0(n1356), .B1(Data_Y[17]), .Y(n892) );
AO22XLTS U1652 ( .A0(n1353), .A1(intDY_EWSW[18]), .B0(n1356), .B1(Data_Y[18]), .Y(n891) );
AO22XLTS U1653 ( .A0(n1350), .A1(intDY_EWSW[19]), .B0(n1356), .B1(Data_Y[19]), .Y(n890) );
AO22XLTS U1654 ( .A0(n1353), .A1(intDY_EWSW[20]), .B0(n1354), .B1(Data_Y[20]), .Y(n889) );
AO22XLTS U1655 ( .A0(n1350), .A1(intDY_EWSW[21]), .B0(n1354), .B1(Data_Y[21]), .Y(n888) );
AO22XLTS U1656 ( .A0(n1353), .A1(intDY_EWSW[22]), .B0(n1354), .B1(Data_Y[22]), .Y(n887) );
AO22XLTS U1657 ( .A0(n1353), .A1(intDY_EWSW[23]), .B0(n1352), .B1(Data_Y[23]), .Y(n886) );
AO22XLTS U1658 ( .A0(n1353), .A1(intDY_EWSW[24]), .B0(n1351), .B1(Data_Y[24]), .Y(n885) );
AO22XLTS U1659 ( .A0(n1350), .A1(intDY_EWSW[25]), .B0(n1351), .B1(Data_Y[25]), .Y(n884) );
AO22XLTS U1660 ( .A0(n1353), .A1(intDY_EWSW[26]), .B0(n1351), .B1(Data_Y[26]), .Y(n883) );
AO22XLTS U1661 ( .A0(n1353), .A1(intDY_EWSW[27]), .B0(n1352), .B1(Data_Y[27]), .Y(n882) );
AO22XLTS U1662 ( .A0(n1354), .A1(Data_Y[29]), .B0(n954), .B1(intDY_EWSW[29]),
.Y(n880) );
AO22XLTS U1663 ( .A0(n1354), .A1(Data_Y[30]), .B0(n954), .B1(intDY_EWSW[30]),
.Y(n879) );
OAI2BB2XLTS U1664 ( .B0(n1357), .B1(n986), .A0N(n955), .A1N(
Data_array_SWR[25]), .Y(n877) );
OAI2BB2XLTS U1665 ( .B0(n1364), .B1(n987), .A0N(n955), .A1N(
Data_array_SWR[24]), .Y(n876) );
AOI22X1TS U1666 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1360), .B0(
DmP_mant_SHT1_SW[21]), .B1(n1370), .Y(n1361) );
AOI21X1TS U1667 ( .A0(DmP_mant_SHT1_SW[20]), .A1(n989), .B0(n1363), .Y(n1366) );
OAI222X1TS U1668 ( .A0(n1387), .A1(n1630), .B0(n1238), .B1(n1364), .C0(n987),
.C1(n1366), .Y(n874) );
OAI222X1TS U1669 ( .A0(n1715), .A1(n1387), .B0(n1238), .B1(n1366), .C0(n987),
.C1(n1365), .Y(n872) );
AOI22X1TS U1670 ( .A0(n988), .A1(DmP_mant_SHT1_SW[12]), .B0(n1370), .B1(n980), .Y(n1367) );
AOI21X1TS U1671 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n1380), .B0(n1368), .Y(
n1374) );
OAI222X1TS U1672 ( .A0(n1650), .A1(n1387), .B0(n1238), .B1(n1369), .C0(n987),
.C1(n1374), .Y(n866) );
AOI22X1TS U1673 ( .A0(n988), .A1(DmP_mant_SHT1_SW[10]), .B0(n1370), .B1(n981), .Y(n1371) );
AOI21X1TS U1674 ( .A0(Raw_mant_NRM_SWR[13]), .A1(n1380), .B0(n1373), .Y(
n1376) );
OAI222X1TS U1675 ( .A0(n1709), .A1(n1387), .B0(n1238), .B1(n1374), .C0(n987),
.C1(n1376), .Y(n864) );
OAI222X1TS U1676 ( .A0(n1706), .A1(n1387), .B0(n1238), .B1(n1376), .C0(n987),
.C1(n1375), .Y(n862) );
AOI22X1TS U1677 ( .A0(n955), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1377), .Y(n1382) );
AOI22X1TS U1678 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n1380), .B0(n1379), .B1(
n1378), .Y(n1381) );
NAND2X1TS U1679 ( .A(n1382), .B(n1381), .Y(n852) );
AOI32X1TS U1680 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1387), .A2(n953), .B0(
shift_value_SHT2_EWR[2]), .B1(n955), .Y(n1384) );
NAND2X1TS U1681 ( .A(n1384), .B(n1383), .Y(n851) );
AOI32X1TS U1682 ( .A0(Shift_amount_SHT1_EWR[3]), .A1(n1387), .A2(n953), .B0(
shift_value_SHT2_EWR[3]), .B1(n955), .Y(n1389) );
NAND2X1TS U1683 ( .A(n1389), .B(n1388), .Y(n850) );
INVX4TS U1684 ( .A(n1415), .Y(n1423) );
AOI21X1TS U1685 ( .A0(DMP_EXP_EWSW[23]), .A1(n999), .B0(n1394), .Y(n1390) );
INVX4TS U1686 ( .A(n1415), .Y(n1425) );
AOI2BB2XLTS U1687 ( .B0(n1423), .B1(n1390), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1425), .Y(n847) );
NOR2X1TS U1688 ( .A(n1648), .B(DMP_EXP_EWSW[24]), .Y(n1393) );
AOI21X1TS U1689 ( .A0(DMP_EXP_EWSW[24]), .A1(n1648), .B0(n1393), .Y(n1391)
);
XNOR2X1TS U1690 ( .A(n1394), .B(n1391), .Y(n1392) );
AO22XLTS U1691 ( .A0(n1425), .A1(n1392), .B0(n1415), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n846) );
INVX4TS U1692 ( .A(n1415), .Y(n1412) );
OAI22X1TS U1693 ( .A0(n1394), .A1(n1393), .B0(DmP_EXP_EWSW[24]), .B1(n1649),
.Y(n1397) );
NAND2X1TS U1694 ( .A(DmP_EXP_EWSW[25]), .B(n1701), .Y(n1398) );
XNOR2X1TS U1695 ( .A(n1397), .B(n1395), .Y(n1396) );
AO22XLTS U1696 ( .A0(n1412), .A1(n1396), .B0(n1716), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n845) );
AOI22X1TS U1697 ( .A0(DMP_EXP_EWSW[25]), .A1(n1712), .B0(n1398), .B1(n1397),
.Y(n1401) );
NOR2X1TS U1698 ( .A(n1708), .B(DMP_EXP_EWSW[26]), .Y(n1402) );
AOI21X1TS U1699 ( .A0(DMP_EXP_EWSW[26]), .A1(n1708), .B0(n1402), .Y(n1399)
);
XNOR2X1TS U1700 ( .A(n1401), .B(n1399), .Y(n1400) );
AO22XLTS U1701 ( .A0(n1425), .A1(n1400), .B0(n1716), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n844) );
OAI22X1TS U1702 ( .A0(n1402), .A1(n1401), .B0(DmP_EXP_EWSW[26]), .B1(n1711),
.Y(n1404) );
XNOR2X1TS U1703 ( .A(DmP_EXP_EWSW[27]), .B(n985), .Y(n1403) );
XOR2XLTS U1704 ( .A(n1404), .B(n1403), .Y(n1405) );
BUFX3TS U1705 ( .A(n1716), .Y(n1414) );
AO22XLTS U1706 ( .A0(n1412), .A1(n1405), .B0(n1414), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n843) );
OAI222X1TS U1707 ( .A0(n1417), .A1(n1710), .B0(n1649), .B1(
Shift_reg_FLAGS_7_6), .C0(n1629), .C1(n1419), .Y(n810) );
OAI222X1TS U1708 ( .A0(n1417), .A1(n1651), .B0(n1701), .B1(
Shift_reg_FLAGS_7_6), .C0(n1720), .C1(n1419), .Y(n809) );
OAI222X1TS U1709 ( .A0(n1417), .A1(n1652), .B0(n1711), .B1(
Shift_reg_FLAGS_7_6), .C0(n1753), .C1(n1419), .Y(n808) );
OAI21XLTS U1710 ( .A0(n1407), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1406) );
AOI21X1TS U1711 ( .A0(n1407), .A1(intDX_EWSW[31]), .B0(n1406), .Y(n1409) );
AO21XLTS U1712 ( .A0(OP_FLAG_EXP), .A1(n1408), .B0(n1409), .Y(n803) );
AO22XLTS U1713 ( .A0(n1410), .A1(n1409), .B0(ZERO_FLAG_EXP), .B1(n1408), .Y(
n802) );
AO22XLTS U1714 ( .A0(n1412), .A1(DMP_EXP_EWSW[0]), .B0(n1414), .B1(
DMP_SHT1_EWSW[0]), .Y(n800) );
AO22XLTS U1715 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n1718), .B1(
DMP_SHT2_EWSW[0]), .Y(n799) );
AO22XLTS U1716 ( .A0(n1425), .A1(DMP_EXP_EWSW[1]), .B0(n1414), .B1(
DMP_SHT1_EWSW[1]), .Y(n797) );
AO22XLTS U1717 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n1413), .B1(
DMP_SHT2_EWSW[1]), .Y(n796) );
AO22XLTS U1718 ( .A0(n1412), .A1(DMP_EXP_EWSW[2]), .B0(n1414), .B1(
DMP_SHT1_EWSW[2]), .Y(n794) );
AO22XLTS U1719 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n1413), .B1(
DMP_SHT2_EWSW[2]), .Y(n793) );
AO22XLTS U1720 ( .A0(n1412), .A1(DMP_EXP_EWSW[3]), .B0(n1414), .B1(
DMP_SHT1_EWSW[3]), .Y(n791) );
AO22XLTS U1721 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n1413), .B1(
DMP_SHT2_EWSW[3]), .Y(n790) );
AO22XLTS U1722 ( .A0(n1412), .A1(DMP_EXP_EWSW[4]), .B0(n1414), .B1(
DMP_SHT1_EWSW[4]), .Y(n788) );
AO22XLTS U1723 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n1413), .B1(
DMP_SHT2_EWSW[4]), .Y(n787) );
AO22XLTS U1724 ( .A0(n1412), .A1(DMP_EXP_EWSW[5]), .B0(n1414), .B1(
DMP_SHT1_EWSW[5]), .Y(n785) );
AO22XLTS U1725 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n1413), .B1(
DMP_SHT2_EWSW[5]), .Y(n784) );
AO22XLTS U1726 ( .A0(n1412), .A1(DMP_EXP_EWSW[6]), .B0(n1414), .B1(
DMP_SHT1_EWSW[6]), .Y(n782) );
AO22XLTS U1727 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1413), .B1(
DMP_SHT2_EWSW[6]), .Y(n781) );
AO22XLTS U1728 ( .A0(n1412), .A1(DMP_EXP_EWSW[7]), .B0(n1414), .B1(
DMP_SHT1_EWSW[7]), .Y(n779) );
AO22XLTS U1729 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n1413), .B1(
DMP_SHT2_EWSW[7]), .Y(n778) );
AO22XLTS U1730 ( .A0(n1624), .A1(DMP_SHT2_EWSW[7]), .B0(n1411), .B1(
DMP_SFG[7]), .Y(n777) );
AO22XLTS U1731 ( .A0(n1412), .A1(DMP_EXP_EWSW[8]), .B0(n1414), .B1(
DMP_SHT1_EWSW[8]), .Y(n776) );
AO22XLTS U1732 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n1413), .B1(
DMP_SHT2_EWSW[8]), .Y(n775) );
AO22XLTS U1733 ( .A0(n1412), .A1(DMP_EXP_EWSW[9]), .B0(n1414), .B1(
DMP_SHT1_EWSW[9]), .Y(n773) );
AO22XLTS U1734 ( .A0(n1426), .A1(DMP_SHT1_EWSW[9]), .B0(n1413), .B1(
DMP_SHT2_EWSW[9]), .Y(n772) );
AO22XLTS U1735 ( .A0(n1412), .A1(DMP_EXP_EWSW[10]), .B0(n1414), .B1(
DMP_SHT1_EWSW[10]), .Y(n770) );
BUFX4TS U1736 ( .A(n1413), .Y(n1422) );
AO22XLTS U1737 ( .A0(n1426), .A1(DMP_SHT1_EWSW[10]), .B0(n1422), .B1(
DMP_SHT2_EWSW[10]), .Y(n769) );
AO22XLTS U1738 ( .A0(n1412), .A1(DMP_EXP_EWSW[11]), .B0(n1716), .B1(
DMP_SHT1_EWSW[11]), .Y(n767) );
AO22XLTS U1739 ( .A0(n1426), .A1(DMP_SHT1_EWSW[11]), .B0(n1422), .B1(
DMP_SHT2_EWSW[11]), .Y(n766) );
BUFX4TS U1740 ( .A(n1716), .Y(n1416) );
AO22XLTS U1741 ( .A0(n1412), .A1(DMP_EXP_EWSW[12]), .B0(n1416), .B1(
DMP_SHT1_EWSW[12]), .Y(n764) );
AO22XLTS U1742 ( .A0(n1426), .A1(DMP_SHT1_EWSW[12]), .B0(n1422), .B1(
DMP_SHT2_EWSW[12]), .Y(n763) );
BUFX3TS U1743 ( .A(n1716), .Y(n1424) );
AO22XLTS U1744 ( .A0(n1412), .A1(DMP_EXP_EWSW[13]), .B0(n1424), .B1(
DMP_SHT1_EWSW[13]), .Y(n761) );
AO22XLTS U1745 ( .A0(n1426), .A1(DMP_SHT1_EWSW[13]), .B0(n1422), .B1(
DMP_SHT2_EWSW[13]), .Y(n760) );
BUFX3TS U1746 ( .A(n1411), .Y(n1622) );
AO22XLTS U1747 ( .A0(n1622), .A1(DMP_SFG[13]), .B0(n1528), .B1(
DMP_SHT2_EWSW[13]), .Y(n759) );
AO22XLTS U1748 ( .A0(n1412), .A1(DMP_EXP_EWSW[14]), .B0(n1716), .B1(
DMP_SHT1_EWSW[14]), .Y(n758) );
AO22XLTS U1749 ( .A0(n1426), .A1(DMP_SHT1_EWSW[14]), .B0(n1422), .B1(
DMP_SHT2_EWSW[14]), .Y(n757) );
AO22XLTS U1750 ( .A0(n1611), .A1(DMP_SFG[14]), .B0(n1613), .B1(
DMP_SHT2_EWSW[14]), .Y(n756) );
AO22XLTS U1751 ( .A0(n1412), .A1(DMP_EXP_EWSW[15]), .B0(n1416), .B1(
DMP_SHT1_EWSW[15]), .Y(n755) );
AO22XLTS U1752 ( .A0(n1426), .A1(DMP_SHT1_EWSW[15]), .B0(n1422), .B1(
DMP_SHT2_EWSW[15]), .Y(n754) );
AO22XLTS U1753 ( .A0(n1611), .A1(DMP_SFG[15]), .B0(n1616), .B1(
DMP_SHT2_EWSW[15]), .Y(n753) );
AO22XLTS U1754 ( .A0(n1412), .A1(DMP_EXP_EWSW[16]), .B0(n1424), .B1(
DMP_SHT1_EWSW[16]), .Y(n752) );
AO22XLTS U1755 ( .A0(busy), .A1(DMP_SHT1_EWSW[16]), .B0(n1422), .B1(
DMP_SHT2_EWSW[16]), .Y(n751) );
AO22XLTS U1756 ( .A0(n1622), .A1(DMP_SFG[16]), .B0(n1624), .B1(
DMP_SHT2_EWSW[16]), .Y(n750) );
AO22XLTS U1757 ( .A0(n1425), .A1(DMP_EXP_EWSW[17]), .B0(n1415), .B1(
DMP_SHT1_EWSW[17]), .Y(n749) );
AO22XLTS U1758 ( .A0(busy), .A1(DMP_SHT1_EWSW[17]), .B0(n1422), .B1(
DMP_SHT2_EWSW[17]), .Y(n748) );
AO22XLTS U1759 ( .A0(n1617), .A1(DMP_SFG[17]), .B0(n1528), .B1(
DMP_SHT2_EWSW[17]), .Y(n747) );
AO22XLTS U1760 ( .A0(n1425), .A1(DMP_EXP_EWSW[18]), .B0(n1416), .B1(
DMP_SHT1_EWSW[18]), .Y(n746) );
AO22XLTS U1761 ( .A0(busy), .A1(DMP_SHT1_EWSW[18]), .B0(n1422), .B1(
DMP_SHT2_EWSW[18]), .Y(n745) );
AO22XLTS U1762 ( .A0(n1622), .A1(DMP_SFG[18]), .B0(n1624), .B1(
DMP_SHT2_EWSW[18]), .Y(n744) );
AO22XLTS U1763 ( .A0(n1425), .A1(DMP_EXP_EWSW[19]), .B0(n1424), .B1(
DMP_SHT1_EWSW[19]), .Y(n743) );
AO22XLTS U1764 ( .A0(busy), .A1(DMP_SHT1_EWSW[19]), .B0(n1422), .B1(
DMP_SHT2_EWSW[19]), .Y(n742) );
AO22XLTS U1765 ( .A0(n1617), .A1(DMP_SFG[19]), .B0(n1624), .B1(
DMP_SHT2_EWSW[19]), .Y(n741) );
AO22XLTS U1766 ( .A0(n1425), .A1(DMP_EXP_EWSW[20]), .B0(n1415), .B1(
DMP_SHT1_EWSW[20]), .Y(n740) );
AO22XLTS U1767 ( .A0(busy), .A1(DMP_SHT1_EWSW[20]), .B0(n1422), .B1(
DMP_SHT2_EWSW[20]), .Y(n739) );
AO22XLTS U1768 ( .A0(n1617), .A1(DMP_SFG[20]), .B0(n1616), .B1(
DMP_SHT2_EWSW[20]), .Y(n738) );
AO22XLTS U1769 ( .A0(n1425), .A1(DMP_EXP_EWSW[21]), .B0(n1416), .B1(
DMP_SHT1_EWSW[21]), .Y(n737) );
AO22XLTS U1770 ( .A0(busy), .A1(DMP_SHT1_EWSW[21]), .B0(n1422), .B1(
DMP_SHT2_EWSW[21]), .Y(n736) );
AO22XLTS U1771 ( .A0(n1617), .A1(DMP_SFG[21]), .B0(n1528), .B1(
DMP_SHT2_EWSW[21]), .Y(n735) );
AO22XLTS U1772 ( .A0(n1425), .A1(DMP_EXP_EWSW[22]), .B0(n1424), .B1(
DMP_SHT1_EWSW[22]), .Y(n734) );
AO22XLTS U1773 ( .A0(n1426), .A1(DMP_SHT1_EWSW[22]), .B0(n1413), .B1(
DMP_SHT2_EWSW[22]), .Y(n733) );
AO22XLTS U1774 ( .A0(n1622), .A1(DMP_SFG[22]), .B0(n1624), .B1(
DMP_SHT2_EWSW[22]), .Y(n732) );
AO22XLTS U1775 ( .A0(n1425), .A1(DMP_EXP_EWSW[23]), .B0(n1424), .B1(
DMP_SHT1_EWSW[23]), .Y(n731) );
AO22XLTS U1776 ( .A0(n1426), .A1(DMP_SHT1_EWSW[23]), .B0(n1413), .B1(
DMP_SHT2_EWSW[23]), .Y(n730) );
AO22XLTS U1777 ( .A0(n1624), .A1(DMP_SHT2_EWSW[23]), .B0(n1622), .B1(
DMP_SFG[23]), .Y(n729) );
AO22XLTS U1778 ( .A0(n1487), .A1(DMP_SFG[23]), .B0(n1749), .B1(
DMP_exp_NRM_EW[0]), .Y(n728) );
AO22XLTS U1779 ( .A0(n1425), .A1(DMP_EXP_EWSW[24]), .B0(n1424), .B1(
DMP_SHT1_EWSW[24]), .Y(n726) );
AO22XLTS U1780 ( .A0(n1426), .A1(DMP_SHT1_EWSW[24]), .B0(n1422), .B1(
DMP_SHT2_EWSW[24]), .Y(n725) );
AO22XLTS U1781 ( .A0(n1616), .A1(DMP_SHT2_EWSW[24]), .B0(n1622), .B1(
DMP_SFG[24]), .Y(n724) );
AO22XLTS U1782 ( .A0(n1487), .A1(DMP_SFG[24]), .B0(n1749), .B1(
DMP_exp_NRM_EW[1]), .Y(n723) );
AO22XLTS U1783 ( .A0(n1425), .A1(DMP_EXP_EWSW[25]), .B0(n1424), .B1(
DMP_SHT1_EWSW[25]), .Y(n721) );
AO22XLTS U1784 ( .A0(n1426), .A1(DMP_SHT1_EWSW[25]), .B0(n1422), .B1(
DMP_SHT2_EWSW[25]), .Y(n720) );
AO22XLTS U1785 ( .A0(n1624), .A1(DMP_SHT2_EWSW[25]), .B0(n1622), .B1(
DMP_SFG[25]), .Y(n719) );
AO22XLTS U1786 ( .A0(n1487), .A1(DMP_SFG[25]), .B0(n1567), .B1(
DMP_exp_NRM_EW[2]), .Y(n718) );
AO22XLTS U1787 ( .A0(n1425), .A1(DMP_EXP_EWSW[26]), .B0(n1424), .B1(
DMP_SHT1_EWSW[26]), .Y(n716) );
AO22XLTS U1788 ( .A0(busy), .A1(DMP_SHT1_EWSW[26]), .B0(n1422), .B1(
DMP_SHT2_EWSW[26]), .Y(n715) );
AO22XLTS U1789 ( .A0(n1616), .A1(DMP_SHT2_EWSW[26]), .B0(n1622), .B1(
DMP_SFG[26]), .Y(n714) );
AO22XLTS U1790 ( .A0(n1487), .A1(DMP_SFG[26]), .B0(n1567), .B1(
DMP_exp_NRM_EW[3]), .Y(n713) );
AO22XLTS U1791 ( .A0(n1425), .A1(n985), .B0(n1424), .B1(DMP_SHT1_EWSW[27]),
.Y(n711) );
AO22XLTS U1792 ( .A0(n1426), .A1(DMP_SHT1_EWSW[27]), .B0(n1422), .B1(
DMP_SHT2_EWSW[27]), .Y(n710) );
AO22XLTS U1793 ( .A0(n1624), .A1(DMP_SHT2_EWSW[27]), .B0(n1622), .B1(
DMP_SFG[27]), .Y(n709) );
AO22XLTS U1794 ( .A0(n1487), .A1(DMP_SFG[27]), .B0(n1567), .B1(
DMP_exp_NRM_EW[4]), .Y(n708) );
AO22XLTS U1795 ( .A0(n1425), .A1(DMP_EXP_EWSW[28]), .B0(n1424), .B1(
DMP_SHT1_EWSW[28]), .Y(n706) );
AO22XLTS U1796 ( .A0(n1426), .A1(DMP_SHT1_EWSW[28]), .B0(n1422), .B1(
DMP_SHT2_EWSW[28]), .Y(n705) );
AO22XLTS U1797 ( .A0(n1528), .A1(DMP_SHT2_EWSW[28]), .B0(n1622), .B1(
DMP_SFG[28]), .Y(n704) );
AO22XLTS U1798 ( .A0(n1487), .A1(DMP_SFG[28]), .B0(n1567), .B1(
DMP_exp_NRM_EW[5]), .Y(n703) );
AO22XLTS U1799 ( .A0(n1425), .A1(DMP_EXP_EWSW[29]), .B0(n1424), .B1(
DMP_SHT1_EWSW[29]), .Y(n701) );
AO22XLTS U1800 ( .A0(n1426), .A1(DMP_SHT1_EWSW[29]), .B0(n1422), .B1(
DMP_SHT2_EWSW[29]), .Y(n700) );
AO22XLTS U1801 ( .A0(n1613), .A1(DMP_SHT2_EWSW[29]), .B0(n1622), .B1(
DMP_SFG[29]), .Y(n699) );
AO22XLTS U1802 ( .A0(n1487), .A1(DMP_SFG[29]), .B0(n1567), .B1(
DMP_exp_NRM_EW[6]), .Y(n698) );
AO22XLTS U1803 ( .A0(n1632), .A1(DMP_EXP_EWSW[30]), .B0(n1424), .B1(
DMP_SHT1_EWSW[30]), .Y(n696) );
AO22XLTS U1804 ( .A0(n1426), .A1(DMP_SHT1_EWSW[30]), .B0(n1422), .B1(
DMP_SHT2_EWSW[30]), .Y(n695) );
AO22XLTS U1805 ( .A0(n1624), .A1(DMP_SHT2_EWSW[30]), .B0(n1622), .B1(
DMP_SFG[30]), .Y(n694) );
INVX4TS U1806 ( .A(n1546), .Y(n1536) );
AO22XLTS U1807 ( .A0(n1536), .A1(DMP_SFG[30]), .B0(n1567), .B1(
DMP_exp_NRM_EW[7]), .Y(n693) );
AO22XLTS U1808 ( .A0(n1423), .A1(DmP_EXP_EWSW[16]), .B0(n1716), .B1(
DmP_mant_SHT1_SW[16]), .Y(n658) );
AO22XLTS U1809 ( .A0(n1423), .A1(DmP_EXP_EWSW[17]), .B0(n1415), .B1(
DmP_mant_SHT1_SW[17]), .Y(n656) );
AO22XLTS U1810 ( .A0(n1423), .A1(DmP_EXP_EWSW[19]), .B0(n1415), .B1(n978),
.Y(n652) );
AO22XLTS U1811 ( .A0(n1423), .A1(DmP_EXP_EWSW[21]), .B0(n1415), .B1(
DmP_mant_SHT1_SW[21]), .Y(n648) );
OAI222X1TS U1812 ( .A0(n1419), .A1(n1710), .B0(n1648), .B1(
Shift_reg_FLAGS_7_6), .C0(n1629), .C1(n1417), .Y(n644) );
OAI222X1TS U1813 ( .A0(n1419), .A1(n1651), .B0(n1712), .B1(
Shift_reg_FLAGS_7_6), .C0(n1720), .C1(n1417), .Y(n643) );
OAI222X1TS U1814 ( .A0(n1419), .A1(n1652), .B0(n1708), .B1(
Shift_reg_FLAGS_7_6), .C0(n1753), .C1(n1417), .Y(n642) );
INVX4TS U1815 ( .A(n1420), .Y(n1599) );
NAND2X1TS U1816 ( .A(n1523), .B(Shift_reg_FLAGS_7[0]), .Y(n1421) );
OAI2BB1X1TS U1817 ( .A0N(underflow_flag), .A1N(n1599), .B0(n1421), .Y(n640)
);
AO22XLTS U1818 ( .A0(n1423), .A1(ZERO_FLAG_EXP), .B0(n1415), .B1(
ZERO_FLAG_SHT1), .Y(n638) );
AO22XLTS U1819 ( .A0(n1426), .A1(ZERO_FLAG_SHT1), .B0(n1422), .B1(
ZERO_FLAG_SHT2), .Y(n637) );
AO22XLTS U1820 ( .A0(n1624), .A1(ZERO_FLAG_SHT2), .B0(n1622), .B1(
ZERO_FLAG_SFG), .Y(n636) );
AO22XLTS U1821 ( .A0(n1487), .A1(ZERO_FLAG_SFG), .B0(n1749), .B1(
ZERO_FLAG_NRM), .Y(n635) );
AO22XLTS U1822 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1599), .B1(zero_flag), .Y(n633) );
AO22XLTS U1823 ( .A0(n1423), .A1(OP_FLAG_EXP), .B0(OP_FLAG_SHT1), .B1(n1716),
.Y(n632) );
AO22XLTS U1824 ( .A0(n1426), .A1(OP_FLAG_SHT1), .B0(n1718), .B1(OP_FLAG_SHT2), .Y(n631) );
AO22XLTS U1825 ( .A0(n1617), .A1(n1514), .B0(n1613), .B1(OP_FLAG_SHT2), .Y(
n630) );
AO22XLTS U1826 ( .A0(n1425), .A1(SIGN_FLAG_EXP), .B0(n1424), .B1(
SIGN_FLAG_SHT1), .Y(n629) );
AO22XLTS U1827 ( .A0(n1426), .A1(SIGN_FLAG_SHT1), .B0(n1718), .B1(
SIGN_FLAG_SHT2), .Y(n628) );
AO22XLTS U1828 ( .A0(n1616), .A1(SIGN_FLAG_SHT2), .B0(n1622), .B1(
SIGN_FLAG_SFG), .Y(n627) );
AO22XLTS U1829 ( .A0(n1536), .A1(SIGN_FLAG_SFG), .B0(n1749), .B1(
SIGN_FLAG_NRM), .Y(n626) );
AOI22X1TS U1830 ( .A0(n1514), .A1(n992), .B0(DmP_mant_SFG_SWR[15]), .B1(
n1638), .Y(intadd_4_CI) );
AOI2BB2XLTS U1831 ( .B0(n1536), .B1(intadd_4_SUM_0_), .A0N(
Raw_mant_NRM_SWR[15]), .A1N(n1487), .Y(n623) );
AOI22X1TS U1832 ( .A0(n1514), .A1(n993), .B0(DmP_mant_SFG_SWR[16]), .B1(
n1638), .Y(intadd_4_B_1_) );
AOI22X1TS U1833 ( .A0(n1569), .A1(intadd_4_SUM_1_), .B0(n1631), .B1(n1567),
.Y(n622) );
AOI22X1TS U1834 ( .A0(n1514), .A1(n994), .B0(DmP_mant_SFG_SWR[17]), .B1(
n1638), .Y(intadd_4_B_2_) );
AOI22X1TS U1835 ( .A0(n1569), .A1(intadd_4_SUM_2_), .B0(n1628), .B1(n1567),
.Y(n621) );
AOI22X1TS U1836 ( .A0(n1514), .A1(n995), .B0(DmP_mant_SFG_SWR[18]), .B1(
n1638), .Y(intadd_4_B_3_) );
AOI2BB2XLTS U1837 ( .B0(n1536), .B1(intadd_4_SUM_3_), .A0N(
Raw_mant_NRM_SWR[18]), .A1N(n1487), .Y(n620) );
AOI22X1TS U1838 ( .A0(n1514), .A1(n996), .B0(DmP_mant_SFG_SWR[19]), .B1(
n1638), .Y(intadd_4_B_4_) );
AOI2BB2XLTS U1839 ( .B0(n1536), .B1(intadd_4_SUM_4_), .A0N(
Raw_mant_NRM_SWR[19]), .A1N(n1487), .Y(n619) );
AOI22X1TS U1840 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n1459), .B0(n1514), .B1(
n997), .Y(intadd_4_B_5_) );
AOI2BB2XLTS U1841 ( .B0(n1536), .B1(intadd_4_SUM_5_), .A0N(
Raw_mant_NRM_SWR[20]), .A1N(n1536), .Y(n618) );
AOI22X1TS U1842 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n1459), .B0(n1514), .B1(
n998), .Y(intadd_4_B_6_) );
AOI22X1TS U1843 ( .A0(n1536), .A1(intadd_4_SUM_6_), .B0(n1626), .B1(n1567),
.Y(n617) );
AOI2BB2XLTS U1844 ( .B0(DmP_mant_SFG_SWR[22]), .B1(n1459), .A0N(n1638),
.A1N(DmP_mant_SFG_SWR[22]), .Y(intadd_4_B_7_) );
AOI22X1TS U1845 ( .A0(n1536), .A1(intadd_4_SUM_7_), .B0(n1625), .B1(n1567),
.Y(n616) );
AOI2BB2XLTS U1846 ( .B0(DmP_mant_SFG_SWR[23]), .B1(n1459), .A0N(n1459),
.A1N(DmP_mant_SFG_SWR[23]), .Y(intadd_4_B_8_) );
AOI22X1TS U1847 ( .A0(n1569), .A1(intadd_4_SUM_8_), .B0(n957), .B1(n1567),
.Y(n615) );
AOI22X1TS U1848 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1459), .B0(n1012), .B1(
n1000), .Y(intadd_4_B_9_) );
AOI22X1TS U1849 ( .A0(n1569), .A1(intadd_4_SUM_9_), .B0(n1011), .B1(n1567),
.Y(n614) );
AOI22X1TS U1850 ( .A0(DmP_mant_SFG_SWR[25]), .A1(n1514), .B0(n1638), .B1(
n1001), .Y(n1427) );
XNOR2X1TS U1851 ( .A(intadd_4_n1), .B(n1427), .Y(n1428) );
AOI22X1TS U1852 ( .A0(n1569), .A1(n1428), .B0(n1627), .B1(n1567), .Y(n613)
);
NAND2X2TS U1853 ( .A(n1655), .B(n1455), .Y(n1550) );
NOR2X2TS U1854 ( .A(shift_value_SHT2_EWR[3]), .B(n1664), .Y(n1481) );
INVX2TS U1855 ( .A(n1481), .Y(n1464) );
AOI22X1TS U1856 ( .A0(Data_array_SWR[19]), .A1(n1429), .B0(
Data_array_SWR[15]), .B1(n1430), .Y(n1431) );
OAI21X1TS U1857 ( .A0(n1646), .A1(n1549), .B0(n1431), .Y(n1538) );
INVX2TS U1858 ( .A(n1430), .Y(n1548) );
OAI22X1TS U1859 ( .A0(n1630), .A1(n1550), .B0(n1700), .B1(n1548), .Y(n1539)
);
NOR2X2TS U1860 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1480) );
INVX2TS U1861 ( .A(n1480), .Y(n1463) );
NAND2X2TS U1862 ( .A(n1597), .B(n1467), .Y(n1596) );
NAND2X2TS U1863 ( .A(n1620), .B(n1467), .Y(n1553) );
OAI22X1TS U1864 ( .A0(n1650), .A1(n1596), .B0(n1707), .B1(n1553), .Y(n1432)
);
AOI221X1TS U1865 ( .A0(n1620), .A1(n1538), .B0(n1597), .B1(n1539), .C0(n1432), .Y(n1571) );
AOI22X1TS U1866 ( .A0(n1528), .A1(n1571), .B0(n1002), .B1(n1611), .Y(n612)
);
AOI22X1TS U1867 ( .A0(n1514), .A1(DmP_mant_SFG_SWR[11]), .B0(n1638), .B1(
n1008), .Y(n1529) );
CLKAND2X2TS U1868 ( .A(DMP_SFG[9]), .B(n1529), .Y(n1564) );
NAND2BX1TS U1869 ( .AN(DMP_SFG[10]), .B(n1433), .Y(n1542) );
OAI2BB1X1TS U1870 ( .A0N(n1564), .A1N(n1542), .B0(n1543), .Y(n1530) );
INVX2TS U1871 ( .A(n1530), .Y(n1434) );
OAI21XLTS U1872 ( .A0(n1434), .A1(n1532), .B0(n1531), .Y(n1435) );
XNOR2X1TS U1873 ( .A(n1436), .B(n1435), .Y(n1437) );
AOI22X1TS U1874 ( .A0(n1569), .A1(n1437), .B0(n1633), .B1(n1567), .Y(n611)
);
AOI22X1TS U1875 ( .A0(Data_array_SWR[13]), .A1(n1438), .B0(Data_array_SWR[9]), .B1(n1429), .Y(n1440) );
AOI22X1TS U1876 ( .A0(Data_array_SWR[5]), .A1(n1430), .B0(Data_array_SWR[1]),
.B1(n1467), .Y(n1439) );
OAI211X1TS U1877 ( .A0(n1445), .A1(n1655), .B0(n1440), .C0(n1439), .Y(n1601)
);
AOI22X1TS U1878 ( .A0(Data_array_SWR[24]), .A1(n1593), .B0(n1597), .B1(n1601), .Y(n1441) );
AOI22X1TS U1879 ( .A0(n1616), .A1(n1441), .B0(n1611), .B1(n1003), .Y(n609)
);
AOI22X1TS U1880 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n1459), .B0(n1012), .B1(
n1003), .Y(n1442) );
AOI2BB2XLTS U1881 ( .B0(n1536), .B1(n1442), .A0N(Raw_mant_NRM_SWR[1]), .A1N(
n1536), .Y(n608) );
AOI22X1TS U1882 ( .A0(Data_array_SWR[12]), .A1(n1430), .B0(
Data_array_SWR[16]), .B1(n1429), .Y(n1444) );
NOR2X2TS U1883 ( .A(n1655), .B(n1463), .Y(n1508) );
AOI22X1TS U1884 ( .A0(Data_array_SWR[20]), .A1(n1438), .B0(
Data_array_SWR[24]), .B1(n1508), .Y(n1443) );
NAND2X1TS U1885 ( .A(n1444), .B(n1443), .Y(n1594) );
INVX2TS U1886 ( .A(n1445), .Y(n1592) );
CLKINVX1TS U1887 ( .A(DmP_mant_SFG_SWR[8]), .Y(n1450) );
AOI22X1TS U1888 ( .A0(n1528), .A1(n1590), .B0(n1450), .B1(n1411), .Y(n606)
);
AOI22X1TS U1889 ( .A0(n1514), .A1(n1010), .B0(DmP_mant_SFG_SWR[7]), .B1(
n1638), .Y(n1447) );
NAND2BX1TS U1890 ( .AN(DMP_SFG[5]), .B(n1447), .Y(n1502) );
AOI22X1TS U1891 ( .A0(n1514), .A1(DmP_mant_SFG_SWR[6]), .B0(n1005), .B1(
n1638), .Y(n1446) );
AOI22X1TS U1892 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n1514), .B0(n1638), .B1(
n1007), .Y(n1470) );
NAND2X1TS U1893 ( .A(n1470), .B(DMP_SFG[3]), .Y(n1472) );
NAND2X1TS U1894 ( .A(n1446), .B(DMP_SFG[4]), .Y(n1492) );
OAI21XLTS U1895 ( .A0(n1494), .A1(n1472), .B0(n1492), .Y(n1449) );
INVX2TS U1896 ( .A(n1447), .Y(n1448) );
CLKAND2X2TS U1897 ( .A(DMP_SFG[5]), .B(n1448), .Y(n1500) );
AOI21X1TS U1898 ( .A0(n1502), .A1(n1449), .B0(n1500), .Y(n1453) );
OAI22X1TS U1899 ( .A0(n1459), .A1(n1450), .B0(DmP_mant_SFG_SWR[8]), .B1(
n1514), .Y(n1451) );
NAND2BX1TS U1900 ( .AN(n1451), .B(DMP_SFG[6]), .Y(n1558) );
NAND2BX1TS U1901 ( .AN(DMP_SFG[6]), .B(n1451), .Y(n1501) );
NAND2X1TS U1902 ( .A(n1558), .B(n1501), .Y(n1452) );
XNOR2X1TS U1903 ( .A(n1453), .B(n1452), .Y(n1454) );
AOI2BB2XLTS U1904 ( .B0(n1536), .B1(n1454), .A0N(Raw_mant_NRM_SWR[8]), .A1N(
n1569), .Y(n605) );
INVX2TS U1905 ( .A(n1411), .Y(n1624) );
AOI22X1TS U1906 ( .A0(Data_array_SWR[12]), .A1(n1438), .B0(Data_array_SWR[8]), .B1(n1429), .Y(n1457) );
AOI22X1TS U1907 ( .A0(Data_array_SWR[4]), .A1(n1430), .B0(Data_array_SWR[0]),
.B1(n1467), .Y(n1456) );
OAI211X1TS U1908 ( .A0(n1511), .A1(n1655), .B0(n1457), .C0(n1456), .Y(n1619)
);
AOI22X1TS U1909 ( .A0(Data_array_SWR[25]), .A1(n1593), .B0(n1597), .B1(n1619), .Y(n1458) );
AOI22X1TS U1910 ( .A0(n1528), .A1(n1458), .B0(n1617), .B1(n1004), .Y(n603)
);
AOI22X1TS U1911 ( .A0(DmP_mant_SFG_SWR[0]), .A1(n1459), .B0(n1514), .B1(
n1004), .Y(n1460) );
AOI2BB2XLTS U1912 ( .B0(n1536), .B1(n1460), .A0N(n990), .A1N(n1487), .Y(n602) );
OAI22X1TS U1913 ( .A0(n1650), .A1(n1549), .B0(n1706), .B1(n1550), .Y(n1462)
);
AO22XLTS U1914 ( .A0(n1577), .A1(shift_value_SHT2_EWR[4]), .B0(
Data_array_SWR[6]), .B1(n1430), .Y(n1461) );
AOI211X1TS U1915 ( .A0(Data_array_SWR[2]), .A1(n1467), .B0(n1462), .C0(n1461), .Y(n1598) );
OAI22X1TS U1916 ( .A0(n1620), .A1(n1598), .B0(n1646), .B1(n1553), .Y(n1589)
);
OAI22X1TS U1917 ( .A0(n1647), .A1(n1549), .B0(n1707), .B1(n1550), .Y(n1466)
);
AO22XLTS U1918 ( .A0(n1586), .A1(shift_value_SHT2_EWR[4]), .B0(
Data_array_SWR[7]), .B1(n1430), .Y(n1465) );
AOI211X1TS U1919 ( .A0(Data_array_SWR[3]), .A1(n1467), .B0(n1466), .C0(n1465), .Y(n1595) );
OAI22X1TS U1920 ( .A0(n1620), .A1(n1595), .B0(n1630), .B1(n1553), .Y(n1588)
);
AOI22X1TS U1921 ( .A0(Data_array_SWR[14]), .A1(n1429), .B0(
Data_array_SWR[10]), .B1(n1430), .Y(n1469) );
AOI22X1TS U1922 ( .A0(Data_array_SWR[22]), .A1(n1508), .B0(
Data_array_SWR[18]), .B1(n1438), .Y(n1468) );
NAND2X1TS U1923 ( .A(n1469), .B(n1468), .Y(n1587) );
AOI22X1TS U1924 ( .A0(n1613), .A1(n1585), .B0(n1005), .B1(n1611), .Y(n595)
);
INVX2TS U1925 ( .A(n1492), .Y(n1503) );
NOR2XLTS U1926 ( .A(n1503), .B(n1494), .Y(n1476) );
INVX2TS U1927 ( .A(n1482), .Y(n1473) );
INVX2TS U1928 ( .A(n1472), .Y(n1483) );
XNOR2X1TS U1929 ( .A(n1476), .B(n1475), .Y(n1477) );
AOI22X1TS U1930 ( .A0(n1569), .A1(n1477), .B0(n1660), .B1(n1546), .Y(n594)
);
AOI22X1TS U1931 ( .A0(Data_array_SWR[20]), .A1(n1480), .B0(
Data_array_SWR[24]), .B1(n1481), .Y(n1491) );
AOI22X1TS U1932 ( .A0(Data_array_SWR[12]), .A1(n1429), .B0(Data_array_SWR[8]), .B1(n1430), .Y(n1479) );
NAND2X1TS U1933 ( .A(Data_array_SWR[16]), .B(n1438), .Y(n1478) );
OAI211X1TS U1934 ( .A0(n1491), .A1(n1655), .B0(n1479), .C0(n1478), .Y(n1584)
);
AO22X1TS U1935 ( .A0(Data_array_SWR[25]), .A1(n1481), .B0(Data_array_SWR[21]), .B1(n1480), .Y(n1583) );
AOI22X1TS U1936 ( .A0(n1616), .A1(n1582), .B0(n1006), .B1(n1611), .Y(n592)
);
CMPR32X2TS U1937 ( .A(DMP_SFG[2]), .B(n975), .C(n1484), .CO(n1485), .S(n1017) );
XNOR2X1TS U1938 ( .A(n1486), .B(n1485), .Y(n1488) );
AOI2BB2XLTS U1939 ( .B0(n1536), .B1(n1488), .A0N(Raw_mant_NRM_SWR[5]), .A1N(
n1487), .Y(n591) );
AOI22X1TS U1940 ( .A0(Data_array_SWR[13]), .A1(n1429), .B0(Data_array_SWR[9]), .B1(n1430), .Y(n1490) );
AOI22X1TS U1941 ( .A0(Data_array_SWR[17]), .A1(n1438), .B0(
shift_value_SHT2_EWR[4]), .B1(n1583), .Y(n1489) );
NAND2X1TS U1942 ( .A(n1490), .B(n1489), .Y(n1581) );
INVX2TS U1943 ( .A(n1491), .Y(n1580) );
AOI22X1TS U1944 ( .A0(n1616), .A1(n1579), .B0(n1007), .B1(n1617), .Y(n590)
);
NOR2BX1TS U1945 ( .AN(n1502), .B(n1500), .Y(n1496) );
OAI21XLTS U1946 ( .A0(n1494), .A1(n1493), .B0(n1492), .Y(n1495) );
XNOR2X1TS U1947 ( .A(n1496), .B(n1495), .Y(n1497) );
AOI22X1TS U1948 ( .A0(n1569), .A1(n1497), .B0(n1654), .B1(n1546), .Y(n589)
);
AOI22X1TS U1949 ( .A0(Data_array_SWR[15]), .A1(n1429), .B0(
Data_array_SWR[11]), .B1(n1430), .Y(n1499) );
AOI22X1TS U1950 ( .A0(Data_array_SWR[23]), .A1(n1508), .B0(
Data_array_SWR[19]), .B1(n1438), .Y(n1498) );
NAND2X1TS U1951 ( .A(n1499), .B(n1498), .Y(n1578) );
AOI22X1TS U1952 ( .A0(n1528), .A1(n1576), .B0(n1010), .B1(n1617), .Y(n588)
);
OAI2BB1X1TS U1953 ( .A0N(n1500), .A1N(n1501), .B0(n1558), .Y(n1516) );
AOI31XLTS U1954 ( .A0(n1503), .A1(n1502), .A2(n1501), .B0(n1516), .Y(n1506)
);
AOI22X1TS U1955 ( .A0(n1514), .A1(DmP_mant_SFG_SWR[9]), .B0(n1009), .B1(
n1638), .Y(n1504) );
NAND2X1TS U1956 ( .A(n1504), .B(DMP_SFG[7]), .Y(n1557) );
NOR2BX1TS U1957 ( .AN(n1557), .B(n1559), .Y(n1505) );
XOR2X1TS U1958 ( .A(n1506), .B(n1505), .Y(n1507) );
AOI22X1TS U1959 ( .A0(n1569), .A1(n1507), .B0(n1661), .B1(n1546), .Y(n587)
);
AOI22X1TS U1960 ( .A0(Data_array_SWR[17]), .A1(n1429), .B0(
Data_array_SWR[13]), .B1(n1430), .Y(n1510) );
AOI22X1TS U1961 ( .A0(Data_array_SWR[21]), .A1(n1438), .B0(
Data_array_SWR[25]), .B1(n1508), .Y(n1509) );
NAND2X1TS U1962 ( .A(n1510), .B(n1509), .Y(n1575) );
INVX2TS U1963 ( .A(n1511), .Y(n1574) );
AOI22X1TS U1964 ( .A0(n1613), .A1(n1573), .B0(n1009), .B1(n1617), .Y(n586)
);
AOI22X1TS U1965 ( .A0(n1514), .A1(DmP_mant_SFG_SWR[10]), .B0(n1638), .B1(
n991), .Y(n1515) );
NAND2X1TS U1966 ( .A(n1515), .B(DMP_SFG[8]), .Y(n1540) );
INVX2TS U1967 ( .A(n1540), .Y(n1562) );
NOR2X2TS U1968 ( .A(n1515), .B(DMP_SFG[8]), .Y(n1560) );
NOR2XLTS U1969 ( .A(n1562), .B(n1560), .Y(n1519) );
INVX2TS U1970 ( .A(n1516), .Y(n1517) );
OAI21XLTS U1971 ( .A0(n1559), .A1(n1517), .B0(n1557), .Y(n1518) );
XNOR2X1TS U1972 ( .A(n1519), .B(n1518), .Y(n1520) );
AOI22X1TS U1973 ( .A0(n1569), .A1(n1520), .B0(n1656), .B1(n1546), .Y(n585)
);
AOI22X1TS U1974 ( .A0(Data_array_SWR[12]), .A1(n1621), .B0(
Data_array_SWR[13]), .B1(n1593), .Y(n1521) );
OAI221X1TS U1975 ( .A0(n1620), .A1(n1526), .B0(n1597), .B1(n1527), .C0(n1521), .Y(n1524) );
AO22XLTS U1976 ( .A0(n1600), .A1(n1524), .B0(final_result_ieee[10]), .B1(
n1599), .Y(n583) );
AOI22X1TS U1977 ( .A0(Data_array_SWR[12]), .A1(n1593), .B0(
Data_array_SWR[13]), .B1(n1621), .Y(n1525) );
OAI221X1TS U1978 ( .A0(n1620), .A1(n1527), .B0(n1597), .B1(n1526), .C0(n1525), .Y(n1572) );
OR2X1TS U1979 ( .A(DMP_SFG[9]), .B(n1529), .Y(n1563) );
AOI31XLTS U1980 ( .A0(n1562), .A1(n1542), .A2(n1563), .B0(n1530), .Y(n1534)
);
XNOR2X1TS U1981 ( .A(n1534), .B(n1533), .Y(n1535) );
AOI2BB2XLTS U1982 ( .B0(n1536), .B1(n1535), .A0N(Raw_mant_NRM_SWR[13]),
.A1N(n1536), .Y(n581) );
OAI22X1TS U1983 ( .A0(n1650), .A1(n1553), .B0(n1707), .B1(n1596), .Y(n1537)
);
AOI221X1TS U1984 ( .A0(n1620), .A1(n1539), .B0(n1597), .B1(n1538), .C0(n1537), .Y(n1570) );
AOI22X1TS U1985 ( .A0(n1528), .A1(n1570), .B0(n1617), .B1(n1008), .Y(n580)
);
OAI21XLTS U1986 ( .A0(n1560), .A1(n1557), .B0(n1540), .Y(n1541) );
AOI21X1TS U1987 ( .A0(n1563), .A1(n1541), .B0(n1564), .Y(n1545) );
NAND2X1TS U1988 ( .A(n1543), .B(n1542), .Y(n1544) );
XNOR2X1TS U1989 ( .A(n1545), .B(n1544), .Y(n1547) );
AOI22X1TS U1990 ( .A0(n1569), .A1(n1547), .B0(n1653), .B1(n1546), .Y(n579)
);
OAI22X1TS U1991 ( .A0(n1646), .A1(n1550), .B0(n1696), .B1(n1548), .Y(n1555)
);
OAI222X1TS U1992 ( .A0(n1550), .A1(n1700), .B0(n1549), .B1(n1630), .C0(n1548), .C1(n1650), .Y(n1556) );
OAI22X1TS U1993 ( .A0(n1706), .A1(n1596), .B0(n1647), .B1(n1553), .Y(n1551)
);
AOI221X1TS U1994 ( .A0(n1620), .A1(n1555), .B0(n1597), .B1(n1556), .C0(n1551), .Y(n1552) );
AOI22X1TS U1995 ( .A0(n1616), .A1(n1552), .B0(n1617), .B1(n991), .Y(n578) );
INVX4TS U1996 ( .A(n1600), .Y(n1603) );
OAI2BB2XLTS U1997 ( .B0(n1552), .B1(n1603), .A0N(final_result_ieee[8]),
.A1N(n1599), .Y(n577) );
OAI22X1TS U1998 ( .A0(n1706), .A1(n1553), .B0(n1647), .B1(n1596), .Y(n1554)
);
AOI221X1TS U1999 ( .A0(n1620), .A1(n1556), .B0(n1597), .B1(n1555), .C0(n1554), .Y(n1604) );
OAI2BB2XLTS U2000 ( .B0(n1604), .B1(n1603), .A0N(final_result_ieee[13]),
.A1N(n1599), .Y(n576) );
OAI32X1TS U2001 ( .A0(n1560), .A1(n1559), .A2(n1558), .B0(n1557), .B1(n1560),
.Y(n1561) );
NOR2XLTS U2002 ( .A(n1562), .B(n1561), .Y(n1566) );
NAND2BXLTS U2003 ( .AN(n1564), .B(n1563), .Y(n1565) );
XNOR2X1TS U2004 ( .A(n1566), .B(n1565), .Y(n1568) );
AOI22X1TS U2005 ( .A0(n1569), .A1(n1568), .B0(n1634), .B1(n1567), .Y(n575)
);
OAI2BB2XLTS U2006 ( .B0(n1570), .B1(n1603), .A0N(final_result_ieee[9]),
.A1N(n1599), .Y(n574) );
OAI2BB2XLTS U2007 ( .B0(n1571), .B1(n1603), .A0N(final_result_ieee[12]),
.A1N(n1599), .Y(n573) );
AO22XLTS U2008 ( .A0(n1600), .A1(n1572), .B0(final_result_ieee[11]), .B1(
n1599), .Y(n572) );
OAI2BB2XLTS U2009 ( .B0(n1573), .B1(n1603), .A0N(final_result_ieee[7]),
.A1N(n1599), .Y(n571) );
OAI2BB2XLTS U2010 ( .B0(n1605), .B1(n1603), .A0N(final_result_ieee[14]),
.A1N(n1599), .Y(n570) );
OAI2BB2XLTS U2011 ( .B0(n1576), .B1(n1603), .A0N(final_result_ieee[5]),
.A1N(n1602), .Y(n569) );
OAI2BB2XLTS U2012 ( .B0(n1607), .B1(n1603), .A0N(final_result_ieee[16]),
.A1N(n1602), .Y(n568) );
OAI2BB2XLTS U2013 ( .B0(n1579), .B1(n1603), .A0N(final_result_ieee[3]),
.A1N(n1602), .Y(n567) );
OAI2BB2XLTS U2014 ( .B0(n1610), .B1(n1603), .A0N(final_result_ieee[18]),
.A1N(n1602), .Y(n566) );
OAI2BB2XLTS U2015 ( .B0(n1582), .B1(n1603), .A0N(final_result_ieee[2]),
.A1N(n1602), .Y(n565) );
OAI2BB2XLTS U2016 ( .B0(n1612), .B1(n1603), .A0N(final_result_ieee[19]),
.A1N(n1602), .Y(n564) );
OAI2BB2XLTS U2017 ( .B0(n1585), .B1(n1603), .A0N(final_result_ieee[4]),
.A1N(n1602), .Y(n563) );
OAI2BB2XLTS U2018 ( .B0(n1609), .B1(n1603), .A0N(final_result_ieee[17]),
.A1N(n1602), .Y(n562) );
AO22XLTS U2019 ( .A0(n1600), .A1(n1588), .B0(final_result_ieee[1]), .B1(
n1599), .Y(n561) );
AO22XLTS U2020 ( .A0(n1600), .A1(n1589), .B0(final_result_ieee[0]), .B1(
n1599), .Y(n560) );
OAI2BB2XLTS U2021 ( .B0(n1590), .B1(n1603), .A0N(final_result_ieee[6]),
.A1N(n1602), .Y(n559) );
OAI2BB2XLTS U2022 ( .B0(n1606), .B1(n1603), .A0N(final_result_ieee[15]),
.A1N(n1599), .Y(n558) );
OAI22X1TS U2023 ( .A0(n1595), .A1(n1597), .B0(n1630), .B1(n1596), .Y(n1614)
);
AO22XLTS U2024 ( .A0(n1600), .A1(n1614), .B0(final_result_ieee[20]), .B1(
n1599), .Y(n557) );
OAI22X1TS U2025 ( .A0(n1598), .A1(n1597), .B0(n1646), .B1(n1596), .Y(n1615)
);
AO22XLTS U2026 ( .A0(n1600), .A1(n1615), .B0(final_result_ieee[21]), .B1(
n1599), .Y(n556) );
AOI22X1TS U2027 ( .A0(Data_array_SWR[24]), .A1(n1621), .B0(n1620), .B1(n1601), .Y(n1618) );
OAI2BB2XLTS U2028 ( .B0(n1618), .B1(n1603), .A0N(final_result_ieee[22]),
.A1N(n1602), .Y(n555) );
AOI22X1TS U2029 ( .A0(n1528), .A1(n1604), .B0(n992), .B1(n1617), .Y(n554) );
AOI22X1TS U2030 ( .A0(n1613), .A1(n1605), .B0(n993), .B1(n1617), .Y(n553) );
AOI22X1TS U2031 ( .A0(n1616), .A1(n1606), .B0(n994), .B1(n1411), .Y(n552) );
AOI22X1TS U2032 ( .A0(n1528), .A1(n1607), .B0(n995), .B1(n1617), .Y(n551) );
AOI22X1TS U2033 ( .A0(n1616), .A1(n1609), .B0(n996), .B1(n1617), .Y(n550) );
AOI22X1TS U2034 ( .A0(n1528), .A1(n1610), .B0(n1611), .B1(n997), .Y(n549) );
AOI22X1TS U2035 ( .A0(n1616), .A1(n1612), .B0(n1411), .B1(n998), .Y(n548) );
AO22XLTS U2036 ( .A0(n1617), .A1(DmP_mant_SFG_SWR[22]), .B0(n1528), .B1(
n1614), .Y(n547) );
AO22XLTS U2037 ( .A0(n1617), .A1(DmP_mant_SFG_SWR[23]), .B0(n1613), .B1(
n1615), .Y(n546) );
AOI22X1TS U2038 ( .A0(n1613), .A1(n1618), .B0(n1611), .B1(n1000), .Y(n545)
);
AOI22X1TS U2039 ( .A0(Data_array_SWR[25]), .A1(n1621), .B0(n1620), .B1(n1619), .Y(n1623) );
AOI22X1TS U2040 ( .A0(n1616), .A1(n1623), .B0(n1611), .B1(n1001), .Y(n544)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk30.tcl_ACAIN16Q4_syn.sdf");
endmodule
|
module alu_issue_logic
(/*AUTOARG*/
// Outputs
c_issued_valid, c_simd0_alu_select, c_simd1_alu_select,
c_simd2_alu_select, c_simd3_alu_select, c_simf0_alu_select,
c_simf1_alu_select, c_simf2_alu_select, c_simf3_alu_select,
c_lsu_lsu_select, c_salu_alu_select, c_issued_wfid,
// Inputs
clk, rst, f_lsu_ready, f_salu_alu_ready, f_simf3_alu_ready,
f_simf2_alu_ready, f_simf1_alu_ready, f_simf0_alu_ready,
f_simd3_alu_ready, f_simd2_alu_ready, f_simd1_alu_ready,
f_simd0_alu_ready, lsu_wf_valid, simd_wf_valid, simf_wf_valid,
salu_wf_valid, lsu_wf_chosen, simd_wf_choosen, simf_wf_choosen,
salu_wf_choosen
);
input clk,rst;
input f_lsu_ready, f_salu_alu_ready,
f_simf3_alu_ready,f_simf2_alu_ready,
f_simf1_alu_ready,f_simf0_alu_ready,
f_simd3_alu_ready,f_simd2_alu_ready,
f_simd1_alu_ready,f_simd0_alu_ready;
input lsu_wf_valid, simd_wf_valid, simf_wf_valid ,salu_wf_valid;
input [`WF_ID_LENGTH-1:0] lsu_wf_chosen, simd_wf_choosen, simf_wf_choosen, salu_wf_choosen;
output c_issued_valid;
output c_simd0_alu_select, c_simd1_alu_select,
c_simd2_alu_select, c_simd3_alu_select,
c_simf0_alu_select, c_simf1_alu_select,
c_simf2_alu_select, c_simf3_alu_select,
c_lsu_lsu_select, c_salu_alu_select;
output [`WF_ID_LENGTH-1:0] c_issued_wfid;
reg [`WF_ID_LENGTH-1:0] c_issued_wfid;
wire [1:0] last_fu_selected;
reg [1:0] curr_fu_selected;
reg_param #(2) last_fu(.out(last_fu_selected), .in(curr_fu_selected),
.wr_en(c_issued_valid), .clk(clk), .rst(rst));
reg c_issued_valid;
reg c_simd0_alu_select, c_simd1_alu_select,
c_simd2_alu_select, c_simd3_alu_select,
c_simf0_alu_select, c_simf1_alu_select,
c_simf2_alu_select, c_simf3_alu_select,
c_lsu_lsu_select, c_salu_alu_select;
reg [3:0] fu_ready_shifted, fu_selected_shifted;
reg [3:0] fu_ready_arry, fu_selected_arry;
always @(*) begin
fu_ready_arry <= { (f_simd0_alu_ready | f_simd1_alu_ready | f_simd2_alu_ready |
f_simd3_alu_ready) & simd_wf_valid,
(f_simf0_alu_ready | f_simf1_alu_ready | f_simf2_alu_ready |
f_simf3_alu_ready) & simf_wf_valid,
f_lsu_ready & lsu_wf_valid,
f_salu_alu_ready & salu_wf_valid };
// Select one fu based on round robin between fu classes
case( last_fu_selected )
2'b00 : fu_ready_shifted <= fu_ready_arry;
2'b01 : fu_ready_shifted <= {fu_ready_arry[0], fu_ready_arry[3:1]};
2'b10 : fu_ready_shifted <= {fu_ready_arry[1:0], fu_ready_arry[3:2]};
2'b11 : fu_ready_shifted <= {fu_ready_arry[2:0], fu_ready_arry[3]};
endcase
casex( fu_ready_shifted )
4'b1??? : begin
fu_selected_shifted <= fu_ready_shifted & 4'b1000;
curr_fu_selected <= 2'h3;
end
4'b01?? : begin
fu_selected_shifted <= fu_ready_shifted & 4'b0100;
curr_fu_selected <= 2'h2;
end
4'b001? : begin
fu_selected_shifted <= fu_ready_shifted & 4'b0010;
curr_fu_selected <= 2'h1;
end
4'b0001 : begin
fu_selected_shifted <= fu_ready_shifted & 4'b0001;
curr_fu_selected <= 2'h0;
end
default : begin
fu_selected_shifted <= 4'b0000;
curr_fu_selected <= last_fu_selected;
end
endcase // casex ( fu_ready_shifted )
case( last_fu_selected )
2'b00 : fu_selected_arry <= fu_selected_shifted;
2'b01 : fu_selected_arry <= {fu_selected_shifted[2:0], fu_selected_shifted[3]};
2'b10 : fu_selected_arry <= {fu_selected_shifted[1:0], fu_selected_shifted[3:2]};
2'b11 : fu_selected_arry <= {fu_selected_shifted[0], fu_selected_shifted[3:1]};
endcase // case ( last_fu_selected )
// With the class selected, we select the correct alu
casex( { f_simd0_alu_ready,f_simd1_alu_ready,f_simd2_alu_ready,f_simd3_alu_ready} )
4'b1??? : begin
c_simd0_alu_select <= fu_selected_arry[3];
c_simd1_alu_select <= 1'b0;
c_simd2_alu_select <= 1'b0;
c_simd3_alu_select <= 1'b0;
end
4'b01?? : begin
c_simd0_alu_select <= 1'b0;
c_simd1_alu_select <= fu_selected_arry[3];
c_simd2_alu_select <= 1'b0;
c_simd3_alu_select <= 1'b0;
end
4'b001? : begin
c_simd0_alu_select <= 1'b0;
c_simd1_alu_select <= 1'b0;
c_simd2_alu_select <= fu_selected_arry[3];
c_simd3_alu_select <= 1'b0;
end
4'b0001 : begin
c_simd0_alu_select <= 1'b0;
c_simd1_alu_select <= 1'b0;
c_simd2_alu_select <= 1'b0;
c_simd3_alu_select <= fu_selected_arry[3];
end
default : begin
c_simd0_alu_select <= 1'b0;
c_simd1_alu_select <= 1'b0;
c_simd2_alu_select <= 1'b0;
c_simd3_alu_select <= 1'b0;
end
endcase
casex( { f_simf0_alu_ready,f_simf1_alu_ready,f_simf2_alu_ready,f_simf3_alu_ready} )
4'b1??? : begin
c_simf0_alu_select <= fu_selected_arry[2];
c_simf1_alu_select <= 1'b0;
c_simf2_alu_select <= 1'b0;
c_simf3_alu_select <= 1'b0;
end
4'b01?? : begin
c_simf0_alu_select <= 1'b0;
c_simf1_alu_select <= fu_selected_arry[2];
c_simf2_alu_select <= 1'b0;
c_simf3_alu_select <= 1'b0;
end
4'b001? : begin
c_simf0_alu_select <= 1'b0;
c_simf1_alu_select <= 1'b0;
c_simf2_alu_select <= fu_selected_arry[2];
c_simf3_alu_select <= 1'b0;
end
4'b0001 : begin
c_simf0_alu_select <= 1'b0;
c_simf1_alu_select <= 1'b0;
c_simf2_alu_select <= 1'b0;
c_simf3_alu_select <= fu_selected_arry[2];
end
default : begin
c_simf0_alu_select <= 1'b0;
c_simf1_alu_select <= 1'b0;
c_simf2_alu_select <= 1'b0;
c_simf3_alu_select <= 1'b0;
end
endcase
c_lsu_lsu_select <= fu_selected_arry[1];
c_salu_alu_select <= fu_selected_arry[0];
// Select the correct wfid
case( fu_selected_arry )
4'b1000 : c_issued_wfid <= simd_wf_choosen;
4'b0100 : c_issued_wfid <= simf_wf_choosen;
4'b0010 : c_issued_wfid <= lsu_wf_chosen;
4'b0001 : c_issued_wfid <= salu_wf_choosen;
default : c_issued_wfid <= {`WF_ID_LENGTH{1'bx}};
endcase // case ( fu_selected_arry )
c_issued_valid <= |fu_selected_arry;
end
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
// No shared code for this OVL
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression evaluates to a value outside the range specified by parameters min and max");
end
end
end
assign fire_2state_1 = ((test_expr < min) || (test_expr > max));
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
`else
reg fire_xcheck_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
end
wire valid_test_expr = ((test_expr ^ test_expr) == 1'b0);
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
// Auxiliary logic
reg [width-1:0] prev_test_expr;
always @ (posedge clk) begin
// REVISIT: update only if SANITY on?
prev_test_expr <= test_expr; // deliberately not reset
end
wire fire_cover_1, fire_cover_2, fire_cover_3;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_cover_1) begin
ovl_cover_t("test_expr_change covered"); // sanity
end
if (fire_cover_2) begin
ovl_cover_t("test_expr_at_min covered"); // corner
end
if (fire_cover_3) begin
ovl_cover_t("test_expr_at_max covered"); // corner
end
end
end
assign fire_cover_1 = ((OVL_COVER_SANITY_ON > 0) && (test_expr != prev_test_expr));
assign fire_cover_2 = ((OVL_COVER_CORNER_ON > 0) && (test_expr == min));
assign fire_cover_3 = ((OVL_COVER_CORNER_ON > 0) && (test_expr == max));
`endif // OVL_COVER_ON
|
// -----------------------------------------------------------------------
//
// Copyright 2004 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
/*
* Simulate a specific subset of the Altera Shift register
* (lpm_clshift).
*
* Not very ambitious, just the bare minimum.
*/
`timescale 1ns/10ps
module arithshiftbidir(distance,
data,
direction,
result);
parameter lpm_type = "LPM_CLSHIFT";
parameter lpm_shifttype = "ARITHMETIC";
parameter lpm_width = 32;
parameter lpm_widthdist = 5;
input wire [lpm_widthdist-1:0] distance;
input signed [lpm_width-1 :0] data;
input wire direction;
output wire [lpm_width-1 :0] result;
wire [lpm_width-1 :0] lsh = data << distance;
wire [lpm_width-1 :0] rsh = data >> distance;
wire [lpm_width-1 :0] rshN = ~(~data >> distance);
wire [lpm_width-1 :0] arsh = data[lpm_width-1] ? rshN : rsh;
assign result = direction ? arsh : lsh;
endmodule
`ifdef TEST_ARITHSHIFTBIDIR
module test_arithshiftbidir();
reg [31:0] data;
reg [ 4:0] dist;
reg dir;
wire [31:0] resulta, resultl;
arithshiftbidir a(dist, data, dir, resulta);
defparam a.lpm_shifttype = "ARITHMETIC";
initial begin
#0 data = 48; dir = 0; dist = 0;
$monitor("dir %d dist %2d A %8x", dir, dist, resulta);
repeat (2) begin
repeat (32)
#1 dist = dist + 1;
data = 32'h98765432;
dir = ~dir;
end
dir = 1;
data = 32'h08765432;
repeat (32)
#1 dist = dist + 1;
end
endmodule
`endif
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Fri Jul 15 16:37:11 2005
// cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.4 2005/11/30 14:04:15 wig Exp $
// $Date: 2005/11/30 14:04:15 $
// $Log: ent_ba.v,v $
// Revision 1.4 2005/11/30 14:04:15 wig
// Updated testcase references
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
//
// Generator: mix_0.pl Revision: 1.36 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ba
//
// No `defines in this module
module ent_ba
//
// Generated module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
|
module Counter #(
parameter Width = 16
) (
(* intersynth_port = "Reset_n_i" *)
input Reset_n_i,
(* intersynth_port = "Clk_i" *)
input Clk_i,
(* intersynth_conntype = "Bit" *)
input ResetSig_i,
(* intersynth_conntype = "Bit" *)
input Preset_i,
(* intersynth_conntype = "Bit" *)
input Enable_i,
(* intersynth_conntype = "Bit" *)
input Direction_i,
(* intersynth_conntype = "Word" *)
input[Width-1:0] PresetVal_i,
(* intersynth_conntype = "Word" *)
output[Width-1:0] D_o,
(* intersynth_conntype = "Bit" *)
output Overflow_o,
(* intersynth_conntype = "Bit" *)
output Zero_o
);
reg [Width:0] Value;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Value <= 'd0;
end
else
begin
if (ResetSig_i)
Value <= 'd0;
else if (Preset_i)
Value <= {1'b0, PresetVal_i};
else if (Enable_i)
begin
if (!Direction_i)
Value <= {1'b0, Value[Width-1:0]} + 1'b1;
else
Value <= {1'b0, Value[Width-1:0]} - 1'b1;
end
end
end
assign D_o = Value[Width-1:0];
assign Zero_o = (Value[Width-1:0] == 'd0 ? 1'b1 : 1'b0);
assign Overflow_o = Value[Width];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_PP_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk, CLK_N );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_PP_V |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:11:17 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, Sgf_operation_EVEN1_left_N23,
Sgf_operation_EVEN1_left_N22, Sgf_operation_EVEN1_left_N21,
Sgf_operation_EVEN1_left_N20, Sgf_operation_EVEN1_left_N19,
Sgf_operation_EVEN1_left_N18, Sgf_operation_EVEN1_left_N17,
Sgf_operation_EVEN1_left_N16, Sgf_operation_EVEN1_left_N15,
Sgf_operation_EVEN1_left_N14, Sgf_operation_EVEN1_left_N13,
Sgf_operation_EVEN1_left_N12, Sgf_operation_EVEN1_left_N11,
Sgf_operation_EVEN1_left_N10, Sgf_operation_EVEN1_left_N9,
Sgf_operation_EVEN1_left_N8, Sgf_operation_EVEN1_left_N7,
Sgf_operation_EVEN1_left_N6, Sgf_operation_EVEN1_left_N5,
Sgf_operation_EVEN1_left_N4, Sgf_operation_EVEN1_left_N3,
Sgf_operation_EVEN1_left_N2, Sgf_operation_EVEN1_left_N1,
Sgf_operation_EVEN1_left_N0, Sgf_operation_EVEN1_middle_N25,
Sgf_operation_EVEN1_middle_N24, Sgf_operation_EVEN1_middle_N23,
Sgf_operation_EVEN1_middle_N22, Sgf_operation_EVEN1_middle_N21,
Sgf_operation_EVEN1_middle_N20, Sgf_operation_EVEN1_middle_N19,
Sgf_operation_EVEN1_middle_N18, Sgf_operation_EVEN1_middle_N17,
Sgf_operation_EVEN1_middle_N16, Sgf_operation_EVEN1_middle_N15,
Sgf_operation_EVEN1_middle_N14, Sgf_operation_EVEN1_middle_N13,
Sgf_operation_EVEN1_middle_N12, Sgf_operation_EVEN1_middle_N11,
Sgf_operation_EVEN1_middle_N10, Sgf_operation_EVEN1_middle_N9,
Sgf_operation_EVEN1_middle_N8, Sgf_operation_EVEN1_middle_N7,
Sgf_operation_EVEN1_middle_N6, Sgf_operation_EVEN1_middle_N5,
Sgf_operation_EVEN1_middle_N4, Sgf_operation_EVEN1_middle_N3,
Sgf_operation_EVEN1_middle_N2, Sgf_operation_EVEN1_middle_N1,
Sgf_operation_EVEN1_middle_N0, Sgf_operation_EVEN1_right_N23,
Sgf_operation_EVEN1_right_N22, Sgf_operation_EVEN1_right_N21,
Sgf_operation_EVEN1_right_N20, Sgf_operation_EVEN1_right_N19,
Sgf_operation_EVEN1_right_N18, Sgf_operation_EVEN1_right_N17,
Sgf_operation_EVEN1_right_N16, Sgf_operation_EVEN1_right_N15,
Sgf_operation_EVEN1_right_N14, Sgf_operation_EVEN1_right_N13,
Sgf_operation_EVEN1_right_N12, Sgf_operation_EVEN1_right_N11,
Sgf_operation_EVEN1_right_N10, Sgf_operation_EVEN1_right_N9,
Sgf_operation_EVEN1_right_N8, Sgf_operation_EVEN1_right_N7,
Sgf_operation_EVEN1_right_N6, Sgf_operation_EVEN1_right_N5,
Sgf_operation_EVEN1_right_N4, Sgf_operation_EVEN1_right_N3,
Sgf_operation_EVEN1_right_N2, Sgf_operation_EVEN1_right_N1,
Sgf_operation_EVEN1_right_N0, n167, n169, n170, n171, n172, n173,
n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, n184,
n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195,
n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206,
n207, n208, n209, n210, n211, n212, n213, n214, n215, n216, n217,
n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228,
n229, n230, n231, n232, n233, n234, n235, n236, n237, n238, n239,
n240, n241, n242, n243, n244, n245, n246, n247, n248, n249, n250,
n251, n252, n253, n254, n255, n256, n257, n258, n259, n260, n261,
n262, n263, n264, n265, n266, n267, n268, n269, n270, n271, n272,
n273, n274, n275, n276, n277, n278, n279, n280, n281, n282, n283,
n284, n285, n286, n287, n288, n289, n290, n291, n292, n293, n294,
n295, n296, n297, n298, n299, n300, n301, n302, n303, n304, n305,
n306, n307, n308, n309, n310, n311, n313, n314, n315, n316, n319,
n320, n321, n322, n323, n325, n326, n327, n328, n329, n332, n334,
n335, n336, n337, n338, n339, n340, n341, n342, n343, n346, n347,
n348, n349, n350, n351, n352, n353, n354, n359, n360, n361, n362,
n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, n373,
n374, n375, n376, n377, n378, n380, DP_OP_36J18_124_9196_n33,
DP_OP_36J18_124_9196_n22, DP_OP_36J18_124_9196_n21,
DP_OP_36J18_124_9196_n20, DP_OP_36J18_124_9196_n19,
DP_OP_36J18_124_9196_n18, DP_OP_36J18_124_9196_n17,
DP_OP_36J18_124_9196_n16, DP_OP_36J18_124_9196_n15,
DP_OP_36J18_124_9196_n9, DP_OP_36J18_124_9196_n8,
DP_OP_36J18_124_9196_n7, DP_OP_36J18_124_9196_n6,
DP_OP_36J18_124_9196_n5, DP_OP_36J18_124_9196_n4,
DP_OP_36J18_124_9196_n3, DP_OP_36J18_124_9196_n2,
DP_OP_36J18_124_9196_n1, DP_OP_111J18_123_4462_n252,
DP_OP_111J18_123_4462_n251, DP_OP_111J18_123_4462_n250,
DP_OP_111J18_123_4462_n249, DP_OP_111J18_123_4462_n248,
DP_OP_111J18_123_4462_n247, DP_OP_111J18_123_4462_n246,
DP_OP_111J18_123_4462_n245, DP_OP_111J18_123_4462_n240,
DP_OP_111J18_123_4462_n236, DP_OP_111J18_123_4462_n235,
DP_OP_111J18_123_4462_n234, DP_OP_111J18_123_4462_n233,
DP_OP_111J18_123_4462_n232, DP_OP_111J18_123_4462_n231,
DP_OP_111J18_123_4462_n227, DP_OP_111J18_123_4462_n223,
DP_OP_111J18_123_4462_n219, DP_OP_111J18_123_4462_n218,
DP_OP_111J18_123_4462_n217, DP_OP_111J18_123_4462_n216,
DP_OP_111J18_123_4462_n215, DP_OP_111J18_123_4462_n214,
DP_OP_111J18_123_4462_n213, DP_OP_111J18_123_4462_n212,
DP_OP_111J18_123_4462_n210, DP_OP_111J18_123_4462_n204,
DP_OP_111J18_123_4462_n203, DP_OP_111J18_123_4462_n202,
DP_OP_111J18_123_4462_n200, DP_OP_111J18_123_4462_n199,
DP_OP_111J18_123_4462_n198, DP_OP_111J18_123_4462_n197,
DP_OP_111J18_123_4462_n196, DP_OP_111J18_123_4462_n195,
DP_OP_111J18_123_4462_n191, DP_OP_111J18_123_4462_n188,
DP_OP_111J18_123_4462_n187, DP_OP_111J18_123_4462_n186,
DP_OP_111J18_123_4462_n185, DP_OP_111J18_123_4462_n184,
DP_OP_111J18_123_4462_n183, DP_OP_111J18_123_4462_n182,
DP_OP_111J18_123_4462_n181, DP_OP_111J18_123_4462_n180,
DP_OP_111J18_123_4462_n179, DP_OP_111J18_123_4462_n178,
DP_OP_111J18_123_4462_n177, DP_OP_111J18_123_4462_n176,
DP_OP_111J18_123_4462_n175, DP_OP_111J18_123_4462_n172,
DP_OP_111J18_123_4462_n171, DP_OP_111J18_123_4462_n170,
DP_OP_111J18_123_4462_n169, DP_OP_111J18_123_4462_n168,
DP_OP_111J18_123_4462_n167, DP_OP_111J18_123_4462_n166,
DP_OP_111J18_123_4462_n165, DP_OP_111J18_123_4462_n164,
DP_OP_111J18_123_4462_n163, DP_OP_111J18_123_4462_n162,
DP_OP_111J18_123_4462_n156, DP_OP_111J18_123_4462_n155,
DP_OP_111J18_123_4462_n148, DP_OP_111J18_123_4462_n145,
DP_OP_111J18_123_4462_n144, DP_OP_111J18_123_4462_n143,
DP_OP_111J18_123_4462_n142, DP_OP_111J18_123_4462_n140,
DP_OP_111J18_123_4462_n139, DP_OP_111J18_123_4462_n138,
DP_OP_111J18_123_4462_n137, DP_OP_111J18_123_4462_n135,
DP_OP_111J18_123_4462_n134, DP_OP_111J18_123_4462_n133,
DP_OP_111J18_123_4462_n131, DP_OP_111J18_123_4462_n130,
DP_OP_111J18_123_4462_n129, DP_OP_111J18_123_4462_n128,
DP_OP_111J18_123_4462_n127, DP_OP_111J18_123_4462_n126,
DP_OP_111J18_123_4462_n125, DP_OP_111J18_123_4462_n124,
DP_OP_111J18_123_4462_n123, DP_OP_111J18_123_4462_n122,
DP_OP_111J18_123_4462_n121, DP_OP_111J18_123_4462_n120,
DP_OP_111J18_123_4462_n119, DP_OP_111J18_123_4462_n117,
DP_OP_111J18_123_4462_n116, DP_OP_111J18_123_4462_n115,
DP_OP_111J18_123_4462_n114, DP_OP_111J18_123_4462_n113,
DP_OP_111J18_123_4462_n112, DP_OP_111J18_123_4462_n111,
DP_OP_111J18_123_4462_n109, DP_OP_111J18_123_4462_n108,
DP_OP_111J18_123_4462_n107, DP_OP_111J18_123_4462_n106,
DP_OP_111J18_123_4462_n105, DP_OP_111J18_123_4462_n104,
DP_OP_111J18_123_4462_n103, DP_OP_111J18_123_4462_n102,
DP_OP_111J18_123_4462_n101, DP_OP_111J18_123_4462_n100,
DP_OP_111J18_123_4462_n99, DP_OP_111J18_123_4462_n98,
DP_OP_111J18_123_4462_n97, DP_OP_111J18_123_4462_n96,
DP_OP_111J18_123_4462_n94, DP_OP_111J18_123_4462_n93,
DP_OP_111J18_123_4462_n92, DP_OP_111J18_123_4462_n91,
DP_OP_111J18_123_4462_n90, DP_OP_111J18_123_4462_n89,
DP_OP_111J18_123_4462_n88, DP_OP_111J18_123_4462_n87,
DP_OP_111J18_123_4462_n84, DP_OP_111J18_123_4462_n83,
DP_OP_111J18_123_4462_n82, DP_OP_111J18_123_4462_n81,
DP_OP_111J18_123_4462_n80, DP_OP_111J18_123_4462_n79,
DP_OP_111J18_123_4462_n78, DP_OP_111J18_123_4462_n77,
DP_OP_111J18_123_4462_n76, DP_OP_111J18_123_4462_n75,
DP_OP_111J18_123_4462_n74, DP_OP_111J18_123_4462_n73,
DP_OP_111J18_123_4462_n72, DP_OP_111J18_123_4462_n71,
DP_OP_111J18_123_4462_n70, DP_OP_111J18_123_4462_n69,
DP_OP_111J18_123_4462_n68, DP_OP_111J18_123_4462_n67,
DP_OP_111J18_123_4462_n66, DP_OP_111J18_123_4462_n65,
DP_OP_111J18_123_4462_n64, DP_OP_111J18_123_4462_n63,
DP_OP_111J18_123_4462_n62, DP_OP_111J18_123_4462_n61,
DP_OP_111J18_123_4462_n60, DP_OP_111J18_123_4462_n59,
DP_OP_111J18_123_4462_n58, DP_OP_111J18_123_4462_n57,
DP_OP_111J18_123_4462_n56, DP_OP_111J18_123_4462_n55,
DP_OP_111J18_123_4462_n52, DP_OP_111J18_123_4462_n51,
DP_OP_111J18_123_4462_n50, DP_OP_111J18_123_4462_n49,
DP_OP_111J18_123_4462_n48, DP_OP_111J18_123_4462_n47,
DP_OP_111J18_123_4462_n46, DP_OP_111J18_123_4462_n45,
DP_OP_111J18_123_4462_n44, DP_OP_111J18_123_4462_n43,
DP_OP_111J18_123_4462_n42, DP_OP_111J18_123_4462_n41,
DP_OP_111J18_123_4462_n40, DP_OP_111J18_123_4462_n39,
DP_OP_111J18_123_4462_n38, DP_OP_111J18_123_4462_n37,
DP_OP_111J18_123_4462_n36, DP_OP_111J18_123_4462_n35,
DP_OP_110J18_122_9009_n119, DP_OP_110J18_122_9009_n98,
DP_OP_110J18_122_9009_n97, DP_OP_110J18_122_9009_n96,
DP_OP_110J18_122_9009_n74, DP_OP_110J18_122_9009_n73, mult_x_55_n232,
mult_x_55_n228, mult_x_55_n225, mult_x_55_n220, mult_x_55_n219,
mult_x_55_n216, mult_x_55_n215, mult_x_55_n213, mult_x_55_n212,
mult_x_55_n211, mult_x_55_n208, mult_x_55_n207, mult_x_55_n206,
mult_x_55_n205, mult_x_55_n204, mult_x_55_n203, mult_x_55_n202,
mult_x_55_n200, mult_x_55_n199, mult_x_55_n198, mult_x_55_n197,
mult_x_55_n196, mult_x_55_n195, mult_x_55_n194, mult_x_55_n192,
mult_x_55_n191, mult_x_55_n190, mult_x_55_n189, mult_x_55_n186,
mult_x_55_n185, mult_x_55_n183, mult_x_55_n180, mult_x_55_n179,
mult_x_55_n178, mult_x_55_n176, mult_x_55_n175, mult_x_55_n174,
mult_x_55_n173, mult_x_55_n170, mult_x_55_n169, mult_x_55_n168,
mult_x_55_n167, mult_x_55_n166, mult_x_55_n165, mult_x_55_n164,
mult_x_55_n163, mult_x_55_n162, mult_x_55_n161, mult_x_55_n160,
mult_x_55_n159, mult_x_55_n158, mult_x_55_n157, mult_x_55_n151,
mult_x_55_n149, mult_x_55_n136, mult_x_55_n133, mult_x_55_n132,
mult_x_55_n131, mult_x_55_n130, mult_x_55_n129, mult_x_55_n128,
mult_x_55_n127, mult_x_55_n126, mult_x_55_n125, mult_x_55_n124,
mult_x_55_n123, mult_x_55_n122, mult_x_55_n121, mult_x_55_n120,
mult_x_55_n119, mult_x_55_n118, mult_x_55_n117, mult_x_55_n116,
mult_x_55_n115, mult_x_55_n114, mult_x_55_n113, mult_x_55_n112,
mult_x_55_n111, mult_x_55_n110, mult_x_55_n109, mult_x_55_n108,
mult_x_55_n107, mult_x_55_n106, mult_x_55_n105, mult_x_55_n104,
mult_x_55_n103, mult_x_55_n102, mult_x_55_n101, mult_x_55_n100,
mult_x_55_n99, mult_x_55_n98, mult_x_55_n97, mult_x_55_n96,
mult_x_55_n95, mult_x_55_n94, mult_x_55_n93, mult_x_55_n92,
mult_x_55_n90, mult_x_55_n89, mult_x_55_n88, mult_x_55_n87,
mult_x_55_n86, mult_x_55_n85, mult_x_55_n84, mult_x_55_n83,
mult_x_55_n80, mult_x_55_n79, mult_x_55_n78, mult_x_55_n77,
mult_x_55_n76, mult_x_55_n75, mult_x_55_n74, mult_x_55_n73,
mult_x_55_n72, mult_x_55_n71, mult_x_55_n70, mult_x_55_n69,
mult_x_55_n68, mult_x_55_n67, mult_x_55_n66, mult_x_55_n65,
mult_x_55_n64, mult_x_55_n63, mult_x_55_n62, mult_x_55_n61,
mult_x_55_n60, mult_x_55_n59, mult_x_55_n58, mult_x_55_n57,
mult_x_55_n56, mult_x_55_n55, mult_x_55_n54, mult_x_55_n53,
mult_x_55_n52, mult_x_55_n51, mult_x_55_n48, mult_x_55_n47,
mult_x_55_n46, mult_x_55_n45, mult_x_55_n44, mult_x_55_n43,
mult_x_55_n42, mult_x_55_n41, mult_x_55_n40, mult_x_55_n39,
mult_x_55_n38, mult_x_55_n37, mult_x_55_n36, mult_x_55_n35,
mult_x_55_n34, mult_x_55_n33, mult_x_55_n32, mult_x_55_n31,
mult_x_23_n226, mult_x_23_n222, mult_x_23_n219, mult_x_23_n214,
mult_x_23_n213, mult_x_23_n210, mult_x_23_n209, mult_x_23_n207,
mult_x_23_n206, mult_x_23_n205, mult_x_23_n202, mult_x_23_n201,
mult_x_23_n200, mult_x_23_n199, mult_x_23_n198, mult_x_23_n197,
mult_x_23_n196, mult_x_23_n194, mult_x_23_n193, mult_x_23_n192,
mult_x_23_n191, mult_x_23_n189, mult_x_23_n188, mult_x_23_n186,
mult_x_23_n185, mult_x_23_n184, mult_x_23_n183, mult_x_23_n180,
mult_x_23_n179, mult_x_23_n177, mult_x_23_n174, mult_x_23_n173,
mult_x_23_n172, mult_x_23_n170, mult_x_23_n169, mult_x_23_n168,
mult_x_23_n167, mult_x_23_n164, mult_x_23_n163, mult_x_23_n162,
mult_x_23_n161, mult_x_23_n160, mult_x_23_n159, mult_x_23_n158,
mult_x_23_n157, mult_x_23_n156, mult_x_23_n155, mult_x_23_n154,
mult_x_23_n153, mult_x_23_n152, mult_x_23_n151, mult_x_23_n136,
mult_x_23_n133, mult_x_23_n132, mult_x_23_n131, mult_x_23_n130,
mult_x_23_n129, mult_x_23_n128, mult_x_23_n127, mult_x_23_n126,
mult_x_23_n125, mult_x_23_n124, mult_x_23_n123, mult_x_23_n122,
mult_x_23_n121, mult_x_23_n120, mult_x_23_n119, mult_x_23_n118,
mult_x_23_n117, mult_x_23_n116, mult_x_23_n115, mult_x_23_n114,
mult_x_23_n113, mult_x_23_n112, mult_x_23_n111, mult_x_23_n110,
mult_x_23_n109, mult_x_23_n108, mult_x_23_n107, mult_x_23_n106,
mult_x_23_n105, mult_x_23_n104, mult_x_23_n103, mult_x_23_n102,
mult_x_23_n101, mult_x_23_n100, mult_x_23_n99, mult_x_23_n98,
mult_x_23_n97, mult_x_23_n96, mult_x_23_n95, mult_x_23_n94,
mult_x_23_n93, mult_x_23_n92, mult_x_23_n90, mult_x_23_n89,
mult_x_23_n88, mult_x_23_n87, mult_x_23_n86, mult_x_23_n85,
mult_x_23_n84, mult_x_23_n83, mult_x_23_n80, mult_x_23_n79,
mult_x_23_n78, mult_x_23_n77, mult_x_23_n76, mult_x_23_n75,
mult_x_23_n74, mult_x_23_n73, mult_x_23_n72, mult_x_23_n71,
mult_x_23_n70, mult_x_23_n69, mult_x_23_n68, mult_x_23_n67,
mult_x_23_n66, mult_x_23_n65, mult_x_23_n62, mult_x_23_n61,
mult_x_23_n60, mult_x_23_n59, mult_x_23_n58, mult_x_23_n57,
mult_x_23_n56, mult_x_23_n55, mult_x_23_n54, mult_x_23_n53,
mult_x_23_n52, mult_x_23_n51, mult_x_23_n50, mult_x_23_n48,
mult_x_23_n47, mult_x_23_n46, mult_x_23_n45, mult_x_23_n44,
mult_x_23_n43, mult_x_23_n42, mult_x_23_n41, mult_x_23_n40,
mult_x_23_n39, mult_x_23_n36, mult_x_23_n35, mult_x_23_n34,
mult_x_23_n33, mult_x_23_n32, mult_x_23_n31, n390, n391, n392, n394,
n395, n397, n398, n399, n400, n401, n402, n403, n404, n405, n406,
n407, n408, n409, n410, n411, n412, n413, n414, n415, n416, n417,
n418, n419, n420, n421, n422, n423, n424, n425, n426, n427, n428,
n429, n430, n431, n432, n433, n434, n435, n436, n437, n438, n439,
n440, n441, n442, n443, n444, n445, n446, n447, n448, n449, n450,
n451, n452, n453, n454, n455, n456, n457, n458, n459, n460, n461,
n462, n463, n464, n465, n466, n467, n468, n469, n470, n471, n472,
n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, n483,
n484, n485, n486, n487, n488, n489, n490, n492, n494, n495, n496,
n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507,
n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518,
n519, n520, n521, n522, n523, n524, n525, n526, n527, n529, n530,
n531, n532, n533, n534, n536, n537, n538, n539, n540, n541, n542,
n543, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555,
n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566,
n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577,
n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588,
n589, n590, n591, n592, n593, n594, n595, n596, n597, n598, n599,
n600, n601, n602, n603, n604, n605, n606, n607, n608, n609, n610,
n611, n612, n613, n614, n615, n616, n617, n618, n619, n620, n621,
n622, n623, n624, n625, n626, n627, n628, n629, n630, n631, n632,
n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, n643,
n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, n654,
n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665,
n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676,
n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698,
n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720,
n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, n731,
n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742,
n743, n744, n745, n746, n747, n748, n749, n750, n751, n752, n753,
n754, n755, n756, n757, n758, n759, n760, n761, n762, n763, n764,
n765, n766, n767, n768, n769, n770, n771, n772, n773, n774, n775,
n776, n777, n778, n779, n780, n781, n782, n783, n784, n785, n786,
n787, n788, n789, n790, n791, n792, n793, n794, n795, n796, n797,
n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808,
n809, n810, n811, n812, n813, n814, n815, n816, n817, n818, n819,
n820, n821, n822, n823, n824, n825, n826, n827, n828, n829, n830,
n831, n832, n833, n834, n835, n836, n837, n838, n839, n840, n841,
n842, n843, n844, n845, n846, n847, n848, n849, n850, n851, n852,
n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, n863,
n864, n865, n866, n867, n868, n869, n870, n871, n872, n873, n874,
n875, n876, n877, n878, n879, n880, n881, n882, n883, n884, n885,
n886, n887, n888, n889, n890, n891, n892, n893, n894, n895, n896,
n897, n898, n899, n900, n901, n902, n903, n904, n905, n906, n907,
n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, n918,
n919, n920, n921, n922, n924, n925, n926, n927, n928, n929, n930,
n932, n933, n934, n935, n936, n937, n938, n939, n940, n941, n942,
n943, n944, n945, n946, n947, n948, n949, n950, n951, n952, n953,
n954, n955, n956, n957, n958, n959, n960, n961, n962, n963, n964,
n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, n975,
n976, n977, n978, n979, n980, n981, n982, n983, n984, n985, n986,
n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, n997,
n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007,
n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017,
n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027,
n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037,
n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047,
n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057,
n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067,
n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077,
n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087,
n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097,
n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107,
n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117,
n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127,
n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137,
n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147,
n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157,
n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167,
n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177,
n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187,
n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197,
n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207,
n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217,
n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227,
n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237,
n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247,
n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387,
n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397,
n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407,
n1408, n1409, n1410, n1411, n1412, n1414, n1415, n1416, n1417, n1418,
n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428,
n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1438, n1439,
n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449,
n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459,
n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469,
n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479,
n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489,
n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499,
n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509,
n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519,
n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529,
n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539,
n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549,
n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559,
n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569,
n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579,
n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589,
n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599,
n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609,
n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619,
n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629,
n1630;
wire [47:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [31:0] Op_MX;
wire [31:0] Op_MY;
wire [8:0] exp_oper_result;
wire [8:0] S_Oper_A_exp;
wire [23:0] Add_result;
wire [23:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [8:0] Exp_module_Data_S;
wire [11:0] Sgf_operation_Result;
wire [25:0] Sgf_operation_EVEN1_Q_middle;
wire [23:12] Sgf_operation_EVEN1_Q_right;
wire [23:0] Sgf_operation_EVEN1_Q_left;
DFFQX1TS Sgf_operation_EVEN1_left_DatO_reg_3_ ( .D(
Sgf_operation_EVEN1_left_N3), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[3]) );
DFFQX1TS Sgf_operation_EVEN1_left_DatO_reg_4_ ( .D(
Sgf_operation_EVEN1_left_N4), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[4]) );
DFFQX1TS Sgf_operation_EVEN1_left_DatO_reg_5_ ( .D(
Sgf_operation_EVEN1_left_N5), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[5]) );
DFFQX1TS Sgf_operation_EVEN1_left_DatO_reg_6_ ( .D(
Sgf_operation_EVEN1_left_N6), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[6]) );
DFFQX1TS Sgf_operation_EVEN1_left_DatO_reg_7_ ( .D(
Sgf_operation_EVEN1_left_N7), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[7]) );
DFFQX1TS Sgf_operation_EVEN1_left_DatO_reg_8_ ( .D(
Sgf_operation_EVEN1_left_N8), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[8]) );
DFFQX1TS Sgf_operation_EVEN1_left_DatO_reg_9_ ( .D(
Sgf_operation_EVEN1_left_N9), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[9]) );
DFFQX1TS Sgf_operation_EVEN1_left_DatO_reg_10_ ( .D(
Sgf_operation_EVEN1_left_N10), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[10]) );
DFFQX1TS Sgf_operation_EVEN1_left_DatO_reg_11_ ( .D(
Sgf_operation_EVEN1_left_N11), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[11]) );
DFFQX1TS Sgf_operation_EVEN1_left_DatO_reg_12_ ( .D(
Sgf_operation_EVEN1_left_N12), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[12]) );
DFFQX1TS Sgf_operation_EVEN1_left_DatO_reg_13_ ( .D(
Sgf_operation_EVEN1_left_N13), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[13]) );
DFFQX1TS Sgf_operation_EVEN1_left_DatO_reg_14_ ( .D(
Sgf_operation_EVEN1_left_N14), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[14]) );
DFFQX1TS Sgf_operation_EVEN1_left_DatO_reg_15_ ( .D(
Sgf_operation_EVEN1_left_N15), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[15]) );
DFFQX1TS Sgf_operation_EVEN1_left_DatO_reg_16_ ( .D(
Sgf_operation_EVEN1_left_N16), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[16]) );
DFFQX1TS Sgf_operation_EVEN1_left_DatO_reg_17_ ( .D(
Sgf_operation_EVEN1_left_N17), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[17]) );
DFFQX1TS Sgf_operation_EVEN1_left_DatO_reg_18_ ( .D(
Sgf_operation_EVEN1_left_N18), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[18]) );
DFFQX1TS Sgf_operation_EVEN1_left_DatO_reg_19_ ( .D(
Sgf_operation_EVEN1_left_N19), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[19]) );
DFFQX1TS Sgf_operation_EVEN1_left_DatO_reg_20_ ( .D(
Sgf_operation_EVEN1_left_N20), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[20]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_1_ ( .D(
Sgf_operation_EVEN1_middle_N1), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[1]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_2_ ( .D(
Sgf_operation_EVEN1_middle_N2), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[2]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_3_ ( .D(
Sgf_operation_EVEN1_middle_N3), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[3]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_4_ ( .D(
Sgf_operation_EVEN1_middle_N4), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[4]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_5_ ( .D(
Sgf_operation_EVEN1_middle_N5), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[5]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_6_ ( .D(
Sgf_operation_EVEN1_middle_N6), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[6]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_7_ ( .D(
Sgf_operation_EVEN1_middle_N7), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[7]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_8_ ( .D(
Sgf_operation_EVEN1_middle_N8), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[8]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_9_ ( .D(
Sgf_operation_EVEN1_middle_N9), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[9]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_10_ ( .D(
Sgf_operation_EVEN1_middle_N10), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[10]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_11_ ( .D(
Sgf_operation_EVEN1_middle_N11), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[11]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_12_ ( .D(
Sgf_operation_EVEN1_middle_N12), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[12]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_13_ ( .D(
Sgf_operation_EVEN1_middle_N13), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[13]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_14_ ( .D(
Sgf_operation_EVEN1_middle_N14), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[14]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_15_ ( .D(
Sgf_operation_EVEN1_middle_N15), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[15]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_16_ ( .D(
Sgf_operation_EVEN1_middle_N16), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[16]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_17_ ( .D(
Sgf_operation_EVEN1_middle_N17), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[17]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_18_ ( .D(
Sgf_operation_EVEN1_middle_N18), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[18]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_19_ ( .D(
Sgf_operation_EVEN1_middle_N19), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[19]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_20_ ( .D(
Sgf_operation_EVEN1_middle_N20), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[20]) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_21_ ( .D(
Sgf_operation_EVEN1_middle_N21), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[21]) );
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_1_ ( .D(
Sgf_operation_EVEN1_right_N1), .CK(clk), .Q(Sgf_operation_Result[1])
);
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_2_ ( .D(
Sgf_operation_EVEN1_right_N2), .CK(clk), .Q(Sgf_operation_Result[2])
);
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_3_ ( .D(
Sgf_operation_EVEN1_right_N3), .CK(clk), .Q(Sgf_operation_Result[3])
);
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_4_ ( .D(
Sgf_operation_EVEN1_right_N4), .CK(clk), .Q(Sgf_operation_Result[4])
);
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_5_ ( .D(
Sgf_operation_EVEN1_right_N5), .CK(clk), .Q(Sgf_operation_Result[5])
);
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_6_ ( .D(
Sgf_operation_EVEN1_right_N6), .CK(clk), .Q(Sgf_operation_Result[6])
);
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_7_ ( .D(
Sgf_operation_EVEN1_right_N7), .CK(clk), .Q(Sgf_operation_Result[7])
);
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_8_ ( .D(
Sgf_operation_EVEN1_right_N8), .CK(clk), .Q(Sgf_operation_Result[8])
);
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_9_ ( .D(
Sgf_operation_EVEN1_right_N9), .CK(clk), .Q(Sgf_operation_Result[9])
);
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_10_ ( .D(
Sgf_operation_EVEN1_right_N10), .CK(clk), .Q(Sgf_operation_Result[10])
);
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_11_ ( .D(
Sgf_operation_EVEN1_right_N11), .CK(clk), .Q(Sgf_operation_Result[11])
);
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_12_ ( .D(
Sgf_operation_EVEN1_right_N12), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_right[12]) );
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_13_ ( .D(
Sgf_operation_EVEN1_right_N13), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_right[13]) );
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_14_ ( .D(
Sgf_operation_EVEN1_right_N14), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_right[14]) );
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_15_ ( .D(
Sgf_operation_EVEN1_right_N15), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_right[15]) );
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_16_ ( .D(
Sgf_operation_EVEN1_right_N16), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_right[16]) );
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_17_ ( .D(
Sgf_operation_EVEN1_right_N17), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_right[17]) );
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_18_ ( .D(
Sgf_operation_EVEN1_right_N18), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_right[18]) );
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_19_ ( .D(
Sgf_operation_EVEN1_right_N19), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_right[19]) );
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_20_ ( .D(
Sgf_operation_EVEN1_right_N20), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_right[20]) );
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_21_ ( .D(
Sgf_operation_EVEN1_right_N21), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_right[21]) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n310), .CK(clk), .RN(
n1620), .Q(Op_MY[31]) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n378), .CK(clk), .RN(n1615), .Q(
FS_Module_state_reg[0]), .QN(n1609) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n374), .CK(clk), .RN(
n1620), .QN(n435) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n372), .CK(clk), .RN(
n1618), .QN(n406) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n343), .CK(clk), .RN(
n1619), .Q(Op_MX[31]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n284), .CK(clk), .RN(n1620),
.QN(n444) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n285), .CK(clk), .RN(n1616),
.QN(n453) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n286), .CK(clk), .RN(n1619),
.QN(n443) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n287), .CK(clk), .RN(n1618),
.QN(n452) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n288), .CK(clk), .RN(n1616),
.QN(n442) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n289), .CK(clk), .RN(n1625),
.QN(n451) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n290), .CK(clk), .RN(n1620),
.QN(n441) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n291), .CK(clk), .RN(n1625),
.QN(n450) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n292), .CK(clk), .RN(n1619),
.QN(n440) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n293), .CK(clk), .RN(n1616),
.QN(n449) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n294), .CK(clk), .RN(n1619),
.QN(n439) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n295), .CK(clk), .RN(n1619),
.QN(n448) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n296), .CK(clk), .RN(n1618),
.QN(n438) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n297), .CK(clk), .RN(n1616),
.QN(n447) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n298), .CK(clk), .RN(n1619),
.QN(n436) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n299), .CK(clk), .RN(n1625),
.QN(n446) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n300), .CK(clk), .RN(n1619),
.QN(n437) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n301), .CK(clk), .RN(n1622),
.QN(n456) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n302), .CK(clk), .RN(n1620),
.QN(n454) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n303), .CK(clk), .RN(n1626),
.QN(n455) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n305), .CK(clk), .RN(n1623),
.QN(n445) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n306), .CK(clk), .RN(n1626),
.Q(Add_result[0]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n283), .CK(clk), .RN(n1618),
.Q(Add_result[23]) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n341), .CK(clk), .RN(
n1625), .QN(n433) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n340), .CK(clk), .RN(
n1616), .QN(n405) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n337), .CK(clk), .RN(
n1616), .QN(n421) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n336), .CK(clk), .RN(
n1626), .QN(n404) );
DFFRXLTS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n311), .CK(clk),
.RN(n1618), .Q(zero_flag) );
DFFRXLTS Sel_B_Q_reg_0_ ( .D(n309), .CK(clk), .RN(n1616), .Q(
FSM_selector_B[0]), .QN(n1576) );
DFFRXLTS Exp_module_exp_result_m_Q_reg_4_ ( .D(n276), .CK(clk), .RN(n1618),
.QN(n422) );
DFFRXLTS Exp_module_exp_result_m_Q_reg_6_ ( .D(n274), .CK(clk), .RN(n1622),
.QN(n434) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_46_ ( .D(n261), .CK(clk), .RN(
n1613), .Q(P_Sgf[46]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_45_ ( .D(n260), .CK(clk), .RN(
n1615), .Q(P_Sgf[45]), .QN(n1593) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_44_ ( .D(n259), .CK(clk), .RN(
n1612), .Q(P_Sgf[44]), .QN(n1587) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_43_ ( .D(n258), .CK(clk), .RN(
n1613), .Q(P_Sgf[43]), .QN(n1594) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_42_ ( .D(n257), .CK(clk), .RN(
n1615), .Q(P_Sgf[42]), .QN(n1595) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_41_ ( .D(n256), .CK(clk), .RN(
n1612), .Q(P_Sgf[41]), .QN(n1596) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_40_ ( .D(n255), .CK(clk), .RN(
n1613), .Q(P_Sgf[40]), .QN(n1597) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_39_ ( .D(n254), .CK(clk), .RN(
n1615), .Q(P_Sgf[39]), .QN(n1598) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_38_ ( .D(n253), .CK(clk), .RN(
n1613), .Q(P_Sgf[38]), .QN(n1599) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_37_ ( .D(n252), .CK(clk), .RN(
n1615), .Q(P_Sgf[37]), .QN(n1600) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_36_ ( .D(n251), .CK(clk), .RN(
n1612), .Q(P_Sgf[36]), .QN(n1601) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(n250), .CK(clk), .RN(
n1613), .Q(P_Sgf[35]), .QN(n1602) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(n249), .CK(clk), .RN(
n1615), .Q(P_Sgf[34]), .QN(n1603) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(n248), .CK(clk), .RN(
n1612), .Q(P_Sgf[33]), .QN(n1604) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_32_ ( .D(n247), .CK(clk), .RN(
n1613), .Q(P_Sgf[32]), .QN(n1605) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(n246), .CK(clk), .RN(
n1615), .Q(P_Sgf[31]), .QN(n1606) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(n245), .CK(clk), .RN(
n1612), .Q(P_Sgf[30]), .QN(n1607) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(n244), .CK(clk), .RN(
n1613), .Q(P_Sgf[29]), .QN(n1608) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(n243), .CK(clk), .RN(
n1615), .Q(P_Sgf[28]), .QN(n1588) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(n242), .CK(clk), .RN(
n1612), .Q(P_Sgf[27]), .QN(n1589) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(n241), .CK(clk), .RN(
n1615), .Q(P_Sgf[26]), .QN(n1590) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(n240), .CK(clk), .RN(
n1614), .Q(P_Sgf[25]), .QN(n1591) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(n239), .CK(clk), .RN(
n1614), .Q(P_Sgf[24]), .QN(n1592) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(n238), .CK(clk), .RN(
n1614), .Q(P_Sgf[23]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_22_ ( .D(n237), .CK(clk), .RN(
n1614), .Q(P_Sgf[22]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_21_ ( .D(n236), .CK(clk), .RN(
n1614), .Q(P_Sgf[21]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_20_ ( .D(n235), .CK(clk), .RN(
n1614), .Q(P_Sgf[20]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(n234), .CK(clk), .RN(
n1614), .Q(P_Sgf[19]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_18_ ( .D(n233), .CK(clk), .RN(
n1614), .Q(P_Sgf[18]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_17_ ( .D(n232), .CK(clk), .RN(
n1614), .Q(P_Sgf[17]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n231), .CK(clk), .RN(
n1614), .Q(P_Sgf[16]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n230), .CK(clk), .RN(
n1614), .Q(P_Sgf[15]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n229), .CK(clk), .RN(
n1613), .Q(P_Sgf[14]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n228), .CK(clk), .RN(
n1615), .Q(P_Sgf[13]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n226), .CK(clk), .RN(
n1612), .Q(P_Sgf[11]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n225), .CK(clk), .RN(
n1613), .Q(P_Sgf[10]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n224), .CK(clk), .RN(
n1615), .Q(P_Sgf[9]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n223), .CK(clk), .RN(
n1612), .Q(P_Sgf[8]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n217), .CK(clk), .RN(
n1630), .Q(P_Sgf[2]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n216), .CK(clk), .RN(
n1630), .Q(P_Sgf[1]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n215), .CK(clk), .RN(
n1630), .Q(P_Sgf[0]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n193), .CK(clk),
.RN(n1623), .QN(n402) );
CMPR32X2TS DP_OP_36J18_124_9196_U10 ( .A(S_Oper_A_exp[0]), .B(
DP_OP_36J18_124_9196_n33), .C(DP_OP_36J18_124_9196_n22), .CO(
DP_OP_36J18_124_9196_n9), .S(Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_36J18_124_9196_U9 ( .A(DP_OP_36J18_124_9196_n21), .B(
S_Oper_A_exp[1]), .C(DP_OP_36J18_124_9196_n9), .CO(
DP_OP_36J18_124_9196_n8), .S(Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_36J18_124_9196_U8 ( .A(DP_OP_36J18_124_9196_n20), .B(
S_Oper_A_exp[2]), .C(DP_OP_36J18_124_9196_n8), .CO(
DP_OP_36J18_124_9196_n7), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_36J18_124_9196_U7 ( .A(DP_OP_36J18_124_9196_n19), .B(
S_Oper_A_exp[3]), .C(DP_OP_36J18_124_9196_n7), .CO(
DP_OP_36J18_124_9196_n6), .S(Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_36J18_124_9196_U6 ( .A(DP_OP_36J18_124_9196_n18), .B(
S_Oper_A_exp[4]), .C(DP_OP_36J18_124_9196_n6), .CO(
DP_OP_36J18_124_9196_n5), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_36J18_124_9196_U5 ( .A(DP_OP_36J18_124_9196_n17), .B(
S_Oper_A_exp[5]), .C(DP_OP_36J18_124_9196_n5), .CO(
DP_OP_36J18_124_9196_n4), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_36J18_124_9196_U4 ( .A(DP_OP_36J18_124_9196_n16), .B(
S_Oper_A_exp[6]), .C(DP_OP_36J18_124_9196_n4), .CO(
DP_OP_36J18_124_9196_n3), .S(Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_36J18_124_9196_U3 ( .A(DP_OP_36J18_124_9196_n15), .B(
S_Oper_A_exp[7]), .C(DP_OP_36J18_124_9196_n3), .CO(
DP_OP_36J18_124_9196_n2), .S(Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_36J18_124_9196_U2 ( .A(DP_OP_36J18_124_9196_n33), .B(
S_Oper_A_exp[8]), .C(DP_OP_36J18_124_9196_n2), .CO(
DP_OP_36J18_124_9196_n1), .S(Exp_module_Data_S[8]) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n272), .CK(clk), .RN(n1624),
.Q(underflow_flag), .QN(n1611) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n262),
.CK(clk), .RN(n1623), .Q(final_result_ieee[31]), .QN(n1610) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n307), .CK(clk),
.RN(n1627), .Q(Sgf_normalized_result[23]), .QN(n1585) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n213), .CK(clk),
.RN(n1621), .Q(Sgf_normalized_result[22]), .QN(n1583) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n211), .CK(clk),
.RN(n1621), .Q(Sgf_normalized_result[20]), .QN(n1582) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n214), .CK(clk), .RN(n1621), .Q(FSM_selector_C),
.QN(n1581) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n209), .CK(clk),
.RN(n1624), .Q(Sgf_normalized_result[18]), .QN(n1580) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n207), .CK(clk),
.RN(n1628), .Q(Sgf_normalized_result[16]), .QN(n1578) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n308), .CK(clk), .RN(n1617), .Q(
FSM_selector_B[1]), .QN(n1577) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n205), .CK(clk),
.RN(n1624), .Q(Sgf_normalized_result[14]), .QN(n1575) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n203), .CK(clk),
.RN(n1621), .Q(Sgf_normalized_result[12]), .QN(n1574) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n201), .CK(clk),
.RN(n1625), .Q(Sgf_normalized_result[10]), .QN(n1573) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n199), .CK(clk),
.RN(n1617), .Q(Sgf_normalized_result[8]), .QN(n1572) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n197), .CK(clk),
.RN(n1617), .Q(Sgf_normalized_result[6]), .QN(n1571) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n195), .CK(clk),
.RN(n1628), .Q(Sgf_normalized_result[4]), .QN(n1570) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n376), .CK(clk), .RN(n1615), .Q(
FS_Module_state_reg[2]), .QN(n1569) );
DFFRX2TS FS_Module_state_reg_reg_1_ ( .D(n377), .CK(clk), .RN(n1630), .Q(
FS_Module_state_reg[1]), .QN(n1579) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n190),
.CK(clk), .RN(n1626), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n189),
.CK(clk), .RN(n1620), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n188),
.CK(clk), .RN(n1616), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n187),
.CK(clk), .RN(n1620), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n186),
.CK(clk), .RN(n1620), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n185),
.CK(clk), .RN(n1619), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n184),
.CK(clk), .RN(n1626), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n183),
.CK(clk), .RN(n1619), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n182),
.CK(clk), .RN(n1616), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n181),
.CK(clk), .RN(n1625), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n180),
.CK(clk), .RN(n1618), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n179),
.CK(clk), .RN(n1625), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n178),
.CK(clk), .RN(n1619), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n177),
.CK(clk), .RN(n1620), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n176),
.CK(clk), .RN(n1619), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n175),
.CK(clk), .RN(n1619), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n174),
.CK(clk), .RN(n1619), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n173),
.CK(clk), .RN(n1620), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n172),
.CK(clk), .RN(n1620), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n171),
.CK(clk), .RN(n1618), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n170),
.CK(clk), .RN(n1626), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n169),
.CK(clk), .RN(n1622), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n167),
.CK(clk), .RN(n1620), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n270),
.CK(clk), .RN(n1618), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n269),
.CK(clk), .RN(n1622), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n268),
.CK(clk), .RN(n1619), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n267),
.CK(clk), .RN(n1622), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n266),
.CK(clk), .RN(n1620), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n265),
.CK(clk), .RN(n1626), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n264),
.CK(clk), .RN(n1626), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n263),
.CK(clk), .RN(n1626), .Q(final_result_ieee[30]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n271), .CK(clk), .RN(n1626), .Q(
Exp_module_Overflow_flag_A) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n281), .CK(clk), .RN(n1625),
.Q(exp_oper_result[8]) );
CMPR42X1TS DP_OP_111J18_123_4462_U73 ( .A(DP_OP_111J18_123_4462_n143), .B(
DP_OP_111J18_123_4462_n251), .C(DP_OP_111J18_123_4462_n142), .D(
DP_OP_111J18_123_4462_n213), .ICI(DP_OP_111J18_123_4462_n156), .S(
DP_OP_111J18_123_4462_n140), .ICO(DP_OP_111J18_123_4462_n138), .CO(
DP_OP_111J18_123_4462_n139) );
CMPR42X1TS DP_OP_111J18_123_4462_U67 ( .A(DP_OP_111J18_123_4462_n223), .B(
DP_OP_111J18_123_4462_n210), .C(DP_OP_111J18_123_4462_n131), .D(
DP_OP_111J18_123_4462_n236), .ICI(DP_OP_111J18_123_4462_n129), .S(
DP_OP_111J18_123_4462_n125), .ICO(DP_OP_111J18_123_4462_n123), .CO(
DP_OP_111J18_123_4462_n124) );
CMPR42X1TS DP_OP_111J18_123_4462_U64 ( .A(DP_OP_111J18_123_4462_n123), .B(
DP_OP_111J18_123_4462_n235), .C(DP_OP_111J18_123_4462_n119), .D(
DP_OP_111J18_123_4462_n197), .ICI(DP_OP_111J18_123_4462_n124), .S(
DP_OP_111J18_123_4462_n117), .ICO(DP_OP_111J18_123_4462_n115), .CO(
DP_OP_111J18_123_4462_n116) );
CMPR42X1TS DP_OP_111J18_123_4462_U61 ( .A(DP_OP_111J18_123_4462_n196), .B(
DP_OP_111J18_123_4462_n111), .C(DP_OP_111J18_123_4462_n115), .D(
DP_OP_111J18_123_4462_n234), .ICI(DP_OP_111J18_123_4462_n116), .S(
DP_OP_111J18_123_4462_n109), .ICO(DP_OP_111J18_123_4462_n107), .CO(
DP_OP_111J18_123_4462_n108) );
CMPR42X1TS DP_OP_111J18_123_4462_U60 ( .A(DP_OP_111J18_123_4462_n246), .B(
DP_OP_111J18_123_4462_n172), .C(DP_OP_111J18_123_4462_n185), .D(
DP_OP_111J18_123_4462_n109), .ICI(DP_OP_111J18_123_4462_n112), .S(
DP_OP_111J18_123_4462_n106), .ICO(DP_OP_111J18_123_4462_n104), .CO(
DP_OP_111J18_123_4462_n105) );
CMPR42X1TS DP_OP_111J18_123_4462_U58 ( .A(DP_OP_111J18_123_4462_n195), .B(
DP_OP_111J18_123_4462_n245), .C(DP_OP_111J18_123_4462_n103), .D(
DP_OP_111J18_123_4462_n107), .ICI(DP_OP_111J18_123_4462_n233), .S(
DP_OP_111J18_123_4462_n101), .ICO(DP_OP_111J18_123_4462_n99), .CO(
DP_OP_111J18_123_4462_n100) );
CMPR42X1TS DP_OP_111J18_123_4462_U57 ( .A(DP_OP_111J18_123_4462_n108), .B(
DP_OP_111J18_123_4462_n171), .C(DP_OP_111J18_123_4462_n184), .D(
DP_OP_111J18_123_4462_n101), .ICI(DP_OP_111J18_123_4462_n104), .S(
DP_OP_111J18_123_4462_n98), .ICO(DP_OP_111J18_123_4462_n96), .CO(
DP_OP_111J18_123_4462_n97) );
CMPR42X1TS DP_OP_111J18_123_4462_U54 ( .A(DP_OP_111J18_123_4462_n219), .B(
DP_OP_111J18_123_4462_n102), .C(DP_OP_111J18_123_4462_n94), .D(
DP_OP_111J18_123_4462_n99), .ICI(DP_OP_111J18_123_4462_n232), .S(
DP_OP_111J18_123_4462_n92), .ICO(DP_OP_111J18_123_4462_n90), .CO(
DP_OP_111J18_123_4462_n91) );
CMPR42X1TS DP_OP_111J18_123_4462_U53 ( .A(DP_OP_111J18_123_4462_n170), .B(
DP_OP_111J18_123_4462_n183), .C(DP_OP_111J18_123_4462_n100), .D(
DP_OP_111J18_123_4462_n96), .ICI(DP_OP_111J18_123_4462_n92), .S(
DP_OP_111J18_123_4462_n89), .ICO(DP_OP_111J18_123_4462_n87), .CO(
DP_OP_111J18_123_4462_n88) );
CMPR42X1TS DP_OP_111J18_123_4462_U50 ( .A(DP_OP_111J18_123_4462_n231), .B(
DP_OP_111J18_123_4462_n93), .C(DP_OP_111J18_123_4462_n84), .D(
DP_OP_111J18_123_4462_n90), .ICI(DP_OP_111J18_123_4462_n218), .S(
DP_OP_111J18_123_4462_n82), .ICO(DP_OP_111J18_123_4462_n80), .CO(
DP_OP_111J18_123_4462_n81) );
CMPR42X1TS DP_OP_111J18_123_4462_U49 ( .A(DP_OP_111J18_123_4462_n169), .B(
DP_OP_111J18_123_4462_n182), .C(DP_OP_111J18_123_4462_n91), .D(
DP_OP_111J18_123_4462_n87), .ICI(DP_OP_111J18_123_4462_n82), .S(
DP_OP_111J18_123_4462_n79), .ICO(DP_OP_111J18_123_4462_n77), .CO(
DP_OP_111J18_123_4462_n78) );
CMPR42X1TS DP_OP_111J18_123_4462_U47 ( .A(DP_OP_111J18_123_4462_n204), .B(
DP_OP_111J18_123_4462_n83), .C(DP_OP_111J18_123_4462_n76), .D(
DP_OP_111J18_123_4462_n80), .ICI(DP_OP_111J18_123_4462_n217), .S(
DP_OP_111J18_123_4462_n74), .ICO(DP_OP_111J18_123_4462_n72), .CO(
DP_OP_111J18_123_4462_n73) );
CMPR42X1TS DP_OP_111J18_123_4462_U46 ( .A(DP_OP_111J18_123_4462_n168), .B(
DP_OP_111J18_123_4462_n181), .C(DP_OP_111J18_123_4462_n81), .D(
DP_OP_111J18_123_4462_n74), .ICI(DP_OP_111J18_123_4462_n77), .S(
DP_OP_111J18_123_4462_n71), .ICO(DP_OP_111J18_123_4462_n69), .CO(
DP_OP_111J18_123_4462_n70) );
CMPR42X1TS DP_OP_111J18_123_4462_U44 ( .A(DP_OP_111J18_123_4462_n68), .B(
DP_OP_111J18_123_4462_n216), .C(DP_OP_111J18_123_4462_n75), .D(
DP_OP_111J18_123_4462_n72), .ICI(DP_OP_111J18_123_4462_n203), .S(
DP_OP_111J18_123_4462_n66), .ICO(DP_OP_111J18_123_4462_n64), .CO(
DP_OP_111J18_123_4462_n65) );
CMPR42X1TS DP_OP_111J18_123_4462_U43 ( .A(DP_OP_111J18_123_4462_n167), .B(
DP_OP_111J18_123_4462_n180), .C(DP_OP_111J18_123_4462_n73), .D(
DP_OP_111J18_123_4462_n66), .ICI(DP_OP_111J18_123_4462_n69), .S(
DP_OP_111J18_123_4462_n63), .ICO(DP_OP_111J18_123_4462_n61), .CO(
DP_OP_111J18_123_4462_n62) );
CMPR42X1TS DP_OP_111J18_123_4462_U42 ( .A(DP_OP_111J18_123_4462_n215), .B(
DP_OP_111J18_123_4462_n67), .C(DP_OP_111J18_123_4462_n191), .D(
DP_OP_111J18_123_4462_n64), .ICI(DP_OP_111J18_123_4462_n202), .S(
DP_OP_111J18_123_4462_n60), .ICO(DP_OP_111J18_123_4462_n58), .CO(
DP_OP_111J18_123_4462_n59) );
CMPR42X1TS DP_OP_111J18_123_4462_U41 ( .A(DP_OP_111J18_123_4462_n166), .B(
DP_OP_111J18_123_4462_n179), .C(DP_OP_111J18_123_4462_n65), .D(
DP_OP_111J18_123_4462_n60), .ICI(DP_OP_111J18_123_4462_n61), .S(
DP_OP_111J18_123_4462_n57), .ICO(DP_OP_111J18_123_4462_n55), .CO(
DP_OP_111J18_123_4462_n56) );
CMPR42X1TS DP_OP_111J18_123_4462_U38 ( .A(DP_OP_111J18_123_4462_n165), .B(
DP_OP_111J18_123_4462_n178), .C(DP_OP_111J18_123_4462_n52), .D(
DP_OP_111J18_123_4462_n59), .ICI(DP_OP_111J18_123_4462_n55), .S(
DP_OP_111J18_123_4462_n50), .ICO(DP_OP_111J18_123_4462_n48), .CO(
DP_OP_111J18_123_4462_n49) );
CMPR42X1TS DP_OP_111J18_123_4462_U36 ( .A(DP_OP_111J18_123_4462_n164), .B(
DP_OP_111J18_123_4462_n177), .C(DP_OP_111J18_123_4462_n51), .D(
DP_OP_111J18_123_4462_n47), .ICI(DP_OP_111J18_123_4462_n48), .S(
DP_OP_111J18_123_4462_n45), .ICO(DP_OP_111J18_123_4462_n43), .CO(
DP_OP_111J18_123_4462_n44) );
CMPR42X1TS DP_OP_111J18_123_4462_U34 ( .A(DP_OP_111J18_123_4462_n42), .B(
DP_OP_111J18_123_4462_n163), .C(DP_OP_111J18_123_4462_n176), .D(
DP_OP_111J18_123_4462_n46), .ICI(DP_OP_111J18_123_4462_n43), .S(
DP_OP_111J18_123_4462_n40), .ICO(DP_OP_111J18_123_4462_n38), .CO(
DP_OP_111J18_123_4462_n39) );
CMPR42X1TS DP_OP_111J18_123_4462_U33 ( .A(DP_OP_111J18_123_4462_n188), .B(
DP_OP_111J18_123_4462_n41), .C(DP_OP_111J18_123_4462_n162), .D(
DP_OP_111J18_123_4462_n175), .ICI(DP_OP_111J18_123_4462_n38), .S(
DP_OP_111J18_123_4462_n37), .ICO(DP_OP_111J18_123_4462_n35), .CO(
DP_OP_111J18_123_4462_n36) );
CMPR42X1TS mult_x_55_U67 ( .A(mult_x_55_n219), .B(mult_x_55_n195), .C(
mult_x_55_n207), .D(mult_x_55_n131), .ICI(mult_x_55_n130), .S(
mult_x_55_n128), .ICO(mult_x_55_n126), .CO(mult_x_55_n127) );
CMPR42X1TS mult_x_55_U65 ( .A(mult_x_55_n206), .B(mult_x_55_n194), .C(
mult_x_55_n129), .D(mult_x_55_n126), .ICI(mult_x_55_n125), .S(
mult_x_55_n123), .ICO(mult_x_55_n121), .CO(mult_x_55_n122) );
CMPR42X1TS mult_x_55_U62 ( .A(mult_x_55_n205), .B(mult_x_55_n124), .C(
mult_x_55_n120), .D(mult_x_55_n118), .ICI(mult_x_55_n121), .S(
mult_x_55_n116), .ICO(mult_x_55_n114), .CO(mult_x_55_n115) );
CMPR42X1TS mult_x_55_U61 ( .A(mult_x_55_n168), .B(mult_x_55_n228), .C(
mult_x_55_n216), .D(mult_x_55_n204), .ICI(mult_x_55_n180), .S(
mult_x_55_n113), .ICO(mult_x_55_n111), .CO(mult_x_55_n112) );
CMPR42X1TS mult_x_55_U60 ( .A(mult_x_55_n192), .B(mult_x_55_n119), .C(
mult_x_55_n117), .D(mult_x_55_n114), .ICI(mult_x_55_n113), .S(
mult_x_55_n110), .ICO(mult_x_55_n108), .CO(mult_x_55_n109) );
CMPR42X1TS mult_x_55_U58 ( .A(mult_x_55_n215), .B(mult_x_55_n167), .C(
mult_x_55_n203), .D(mult_x_55_n179), .ICI(mult_x_55_n107), .S(
mult_x_55_n105), .ICO(mult_x_55_n103), .CO(mult_x_55_n104) );
CMPR42X1TS mult_x_55_U57 ( .A(mult_x_55_n191), .B(mult_x_55_n111), .C(
mult_x_55_n108), .D(mult_x_55_n112), .ICI(mult_x_55_n105), .S(
mult_x_55_n102), .ICO(mult_x_55_n100), .CO(mult_x_55_n101) );
CMPR42X1TS mult_x_55_U55 ( .A(mult_x_55_n202), .B(mult_x_55_n166), .C(
mult_x_55_n190), .D(mult_x_55_n178), .ICI(mult_x_55_n99), .S(
mult_x_55_n97), .ICO(mult_x_55_n95), .CO(mult_x_55_n96) );
CMPR42X1TS mult_x_55_U54 ( .A(mult_x_55_n106), .B(mult_x_55_n103), .C(
mult_x_55_n104), .D(mult_x_55_n97), .ICI(mult_x_55_n100), .S(
mult_x_55_n94), .ICO(mult_x_55_n92), .CO(mult_x_55_n93) );
CMPR42X1TS mult_x_55_U51 ( .A(mult_x_55_n189), .B(mult_x_55_n165), .C(
mult_x_55_n213), .D(n541), .ICI(mult_x_55_n90), .S(mult_x_55_n88),
.ICO(mult_x_55_n86), .CO(mult_x_55_n87) );
CMPR42X1TS mult_x_55_U50 ( .A(mult_x_55_n95), .B(mult_x_55_n98), .C(
mult_x_55_n96), .D(mult_x_55_n88), .ICI(mult_x_55_n92), .S(
mult_x_55_n85), .ICO(mult_x_55_n83), .CO(mult_x_55_n84) );
CMPR42X1TS mult_x_55_U47 ( .A(mult_x_55_n176), .B(mult_x_55_n212), .C(
mult_x_55_n200), .D(mult_x_55_n164), .ICI(mult_x_55_n89), .S(
mult_x_55_n78), .ICO(mult_x_55_n76), .CO(mult_x_55_n77) );
CMPR42X1TS mult_x_55_U46 ( .A(mult_x_55_n86), .B(mult_x_55_n80), .C(
mult_x_55_n87), .D(mult_x_55_n78), .ICI(mult_x_55_n83), .S(
mult_x_55_n75), .ICO(mult_x_55_n73), .CO(mult_x_55_n74) );
CMPR42X1TS mult_x_55_U44 ( .A(mult_x_55_n175), .B(mult_x_55_n163), .C(
mult_x_55_n199), .D(mult_x_55_n211), .ICI(mult_x_55_n72), .S(
mult_x_55_n70), .ICO(mult_x_55_n68), .CO(mult_x_55_n69) );
CMPR42X1TS mult_x_55_U43 ( .A(mult_x_55_n76), .B(mult_x_55_n79), .C(
mult_x_55_n77), .D(mult_x_55_n70), .ICI(mult_x_55_n73), .S(
mult_x_55_n67), .ICO(mult_x_55_n65), .CO(mult_x_55_n66) );
CMPR42X1TS mult_x_55_U41 ( .A(mult_x_55_n64), .B(mult_x_55_n174), .C(
mult_x_55_n186), .D(mult_x_55_n162), .ICI(mult_x_55_n198), .S(
mult_x_55_n62), .ICO(mult_x_55_n60), .CO(mult_x_55_n61) );
CMPR42X1TS mult_x_55_U40 ( .A(mult_x_55_n68), .B(mult_x_55_n71), .C(
mult_x_55_n69), .D(mult_x_55_n62), .ICI(mult_x_55_n65), .S(
mult_x_55_n59), .ICO(mult_x_55_n57), .CO(mult_x_55_n58) );
CMPR42X1TS mult_x_55_U39 ( .A(mult_x_55_n63), .B(mult_x_55_n151), .C(
mult_x_55_n185), .D(mult_x_55_n173), .ICI(mult_x_55_n161), .S(
mult_x_55_n56), .ICO(mult_x_55_n54), .CO(mult_x_55_n55) );
CMPR42X1TS mult_x_55_U38 ( .A(mult_x_55_n197), .B(mult_x_55_n60), .C(
mult_x_55_n61), .D(mult_x_55_n56), .ICI(mult_x_55_n57), .S(
mult_x_55_n53), .ICO(mult_x_55_n51), .CO(mult_x_55_n52) );
CMPR42X1TS mult_x_55_U35 ( .A(mult_x_55_n160), .B(mult_x_55_n54), .C(
mult_x_55_n48), .D(mult_x_55_n55), .ICI(mult_x_55_n51), .S(
mult_x_55_n46), .ICO(mult_x_55_n44), .CO(mult_x_55_n45) );
CMPR42X1TS mult_x_55_U33 ( .A(mult_x_55_n159), .B(mult_x_55_n183), .C(
mult_x_55_n43), .D(mult_x_55_n47), .ICI(mult_x_55_n44), .S(
mult_x_55_n41), .ICO(mult_x_55_n39), .CO(mult_x_55_n40) );
CMPR42X1TS mult_x_55_U31 ( .A(mult_x_55_n38), .B(mult_x_55_n170), .C(
mult_x_55_n158), .D(mult_x_55_n42), .ICI(mult_x_55_n39), .S(
mult_x_55_n36), .ICO(mult_x_55_n34), .CO(mult_x_55_n35) );
CMPR42X1TS mult_x_55_U30 ( .A(mult_x_55_n37), .B(mult_x_55_n149), .C(
mult_x_55_n157), .D(mult_x_55_n169), .ICI(mult_x_55_n34), .S(
mult_x_55_n33), .ICO(mult_x_55_n31), .CO(mult_x_55_n32) );
CMPR42X1TS mult_x_23_U69 ( .A(n412), .B(mult_x_23_n226), .C(mult_x_23_n214),
.D(mult_x_23_n202), .ICI(mult_x_23_n136), .S(mult_x_23_n133), .ICO(
mult_x_23_n131), .CO(mult_x_23_n132) );
CMPR42X1TS mult_x_23_U67 ( .A(mult_x_23_n213), .B(mult_x_23_n189), .C(
mult_x_23_n201), .D(mult_x_23_n131), .ICI(mult_x_23_n130), .S(
mult_x_23_n128), .ICO(mult_x_23_n126), .CO(mult_x_23_n127) );
CMPR42X1TS mult_x_23_U65 ( .A(mult_x_23_n200), .B(mult_x_23_n188), .C(
mult_x_23_n129), .D(mult_x_23_n126), .ICI(mult_x_23_n125), .S(
mult_x_23_n123), .ICO(mult_x_23_n121), .CO(mult_x_23_n122) );
CMPR42X1TS mult_x_23_U62 ( .A(mult_x_23_n199), .B(mult_x_23_n124), .C(
mult_x_23_n120), .D(mult_x_23_n118), .ICI(mult_x_23_n121), .S(
mult_x_23_n116), .ICO(mult_x_23_n114), .CO(mult_x_23_n115) );
CMPR42X1TS mult_x_23_U61 ( .A(mult_x_23_n162), .B(mult_x_23_n222), .C(
mult_x_23_n210), .D(mult_x_23_n198), .ICI(mult_x_23_n174), .S(
mult_x_23_n113), .ICO(mult_x_23_n111), .CO(mult_x_23_n112) );
CMPR42X1TS mult_x_23_U60 ( .A(mult_x_23_n186), .B(mult_x_23_n119), .C(
mult_x_23_n117), .D(mult_x_23_n114), .ICI(mult_x_23_n113), .S(
mult_x_23_n110), .ICO(mult_x_23_n108), .CO(mult_x_23_n109) );
CMPR42X1TS mult_x_23_U58 ( .A(mult_x_23_n209), .B(mult_x_23_n161), .C(
mult_x_23_n197), .D(mult_x_23_n173), .ICI(mult_x_23_n107), .S(
mult_x_23_n105), .ICO(mult_x_23_n103), .CO(mult_x_23_n104) );
CMPR42X1TS mult_x_23_U57 ( .A(mult_x_23_n185), .B(mult_x_23_n111), .C(
mult_x_23_n108), .D(mult_x_23_n112), .ICI(mult_x_23_n105), .S(
mult_x_23_n102), .ICO(mult_x_23_n100), .CO(mult_x_23_n101) );
CMPR42X1TS mult_x_23_U55 ( .A(mult_x_23_n196), .B(mult_x_23_n160), .C(
mult_x_23_n184), .D(mult_x_23_n172), .ICI(mult_x_23_n99), .S(
mult_x_23_n97), .ICO(mult_x_23_n95), .CO(mult_x_23_n96) );
CMPR42X1TS mult_x_23_U54 ( .A(mult_x_23_n106), .B(mult_x_23_n103), .C(
mult_x_23_n104), .D(mult_x_23_n97), .ICI(mult_x_23_n100), .S(
mult_x_23_n94), .ICO(mult_x_23_n92), .CO(mult_x_23_n93) );
CMPR42X1TS mult_x_23_U51 ( .A(mult_x_23_n183), .B(mult_x_23_n159), .C(
mult_x_23_n207), .D(n539), .ICI(mult_x_23_n90), .S(mult_x_23_n88),
.ICO(mult_x_23_n86), .CO(mult_x_23_n87) );
CMPR42X1TS mult_x_23_U50 ( .A(mult_x_23_n95), .B(mult_x_23_n98), .C(
mult_x_23_n96), .D(mult_x_23_n88), .ICI(mult_x_23_n92), .S(
mult_x_23_n85), .ICO(mult_x_23_n83), .CO(mult_x_23_n84) );
CMPR42X1TS mult_x_23_U47 ( .A(mult_x_23_n170), .B(mult_x_23_n206), .C(
mult_x_23_n194), .D(mult_x_23_n158), .ICI(mult_x_23_n89), .S(
mult_x_23_n78), .ICO(mult_x_23_n76), .CO(mult_x_23_n77) );
CMPR42X1TS mult_x_23_U46 ( .A(mult_x_23_n86), .B(mult_x_23_n80), .C(
mult_x_23_n87), .D(mult_x_23_n78), .ICI(mult_x_23_n83), .S(
mult_x_23_n75), .ICO(mult_x_23_n73), .CO(mult_x_23_n74) );
CMPR42X1TS mult_x_23_U44 ( .A(mult_x_23_n169), .B(mult_x_23_n157), .C(
mult_x_23_n193), .D(mult_x_23_n205), .ICI(mult_x_23_n72), .S(
mult_x_23_n70), .ICO(mult_x_23_n68), .CO(mult_x_23_n69) );
CMPR42X1TS mult_x_23_U43 ( .A(mult_x_23_n76), .B(mult_x_23_n79), .C(
mult_x_23_n77), .D(mult_x_23_n70), .ICI(mult_x_23_n73), .S(
mult_x_23_n67), .ICO(mult_x_23_n65), .CO(mult_x_23_n66) );
CMPR42X1TS mult_x_23_U41 ( .A(n557), .B(mult_x_23_n168), .C(mult_x_23_n180),
.D(mult_x_23_n156), .ICI(mult_x_23_n192), .S(mult_x_23_n62), .ICO(
mult_x_23_n60), .CO(mult_x_23_n61) );
CMPR42X1TS mult_x_23_U40 ( .A(mult_x_23_n68), .B(mult_x_23_n71), .C(
mult_x_23_n69), .D(mult_x_23_n62), .ICI(mult_x_23_n65), .S(
mult_x_23_n59), .ICO(mult_x_23_n57), .CO(mult_x_23_n58) );
CMPR42X1TS mult_x_23_U39 ( .A(Op_MY[16]), .B(Op_MY[17]), .C(mult_x_23_n179),
.D(mult_x_23_n167), .ICI(mult_x_23_n155), .S(mult_x_23_n56), .ICO(
mult_x_23_n54), .CO(mult_x_23_n55) );
CMPR42X1TS mult_x_23_U38 ( .A(mult_x_23_n191), .B(mult_x_23_n60), .C(
mult_x_23_n61), .D(mult_x_23_n56), .ICI(mult_x_23_n57), .S(
mult_x_23_n53), .ICO(mult_x_23_n51), .CO(mult_x_23_n52) );
CMPR42X1TS mult_x_23_U35 ( .A(mult_x_23_n154), .B(mult_x_23_n54), .C(
mult_x_23_n48), .D(mult_x_23_n55), .ICI(mult_x_23_n51), .S(
mult_x_23_n46), .ICO(mult_x_23_n44), .CO(mult_x_23_n45) );
CMPR42X1TS mult_x_23_U33 ( .A(mult_x_23_n153), .B(mult_x_23_n177), .C(
mult_x_23_n43), .D(mult_x_23_n47), .ICI(mult_x_23_n44), .S(
mult_x_23_n41), .ICO(mult_x_23_n39), .CO(mult_x_23_n40) );
CMPR42X1TS mult_x_23_U31 ( .A(n417), .B(mult_x_23_n164), .C(mult_x_23_n152),
.D(mult_x_23_n42), .ICI(mult_x_23_n39), .S(mult_x_23_n36), .ICO(
mult_x_23_n34), .CO(mult_x_23_n35) );
CMPR42X1TS mult_x_23_U30 ( .A(Op_MY[20]), .B(n530), .C(mult_x_23_n151), .D(
mult_x_23_n163), .ICI(mult_x_23_n34), .S(mult_x_23_n33), .ICO(
mult_x_23_n31), .CO(mult_x_23_n32) );
DFFSX2TS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n552), .CK(clk), .SN(
n1625), .Q(n1558), .QN(Op_MX[14]) );
DFFSX2TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n574), .CK(clk), .SN(
n1623), .Q(n1563) );
DFFSX2TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n427), .CK(clk), .SN(
n1622), .Q(mult_x_23_n50) );
DFFSX2TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n573), .CK(clk), .SN(
n1623), .Q(n1564), .QN(Op_MY[5]) );
DFFSX2TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n426), .CK(clk), .SN(
n1623), .Q(n1559) );
DFFSX2TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n429), .CK(clk), .SN(
n1623), .Q(mult_x_23_n219), .QN(Op_MX[13]) );
DFFSX2TS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n424), .CK(clk), .SN(
n1623), .Q(mult_x_55_n225), .QN(Op_MX[1]) );
DFFSX2TS FS_Module_state_reg_reg_3_ ( .D(n1557), .CK(clk), .SN(n1612), .QN(
FS_Module_state_reg[3]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n315), .CK(clk), .RN(
n1621), .Q(Op_MY[3]), .QN(n1565) );
DFFXLTS Sgf_operation_EVEN1_left_DatO_reg_21_ ( .D(
Sgf_operation_EVEN1_left_N21), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[21]), .QN(DP_OP_110J18_122_9009_n98) );
DFFXLTS Sgf_operation_EVEN1_right_DatO_reg_22_ ( .D(
Sgf_operation_EVEN1_right_N22), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_right[22]), .QN(DP_OP_110J18_122_9009_n74) );
DFFXLTS Sgf_operation_EVEN1_left_DatO_reg_22_ ( .D(
Sgf_operation_EVEN1_left_N22), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[22]), .QN(DP_OP_110J18_122_9009_n97) );
DFFXLTS Sgf_operation_EVEN1_middle_DatO_reg_22_ ( .D(
Sgf_operation_EVEN1_middle_N22), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[22]) );
DFFXLTS Sgf_operation_EVEN1_middle_DatO_reg_23_ ( .D(
Sgf_operation_EVEN1_middle_N23), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[23]) );
DFFXLTS Sgf_operation_EVEN1_middle_DatO_reg_24_ ( .D(
Sgf_operation_EVEN1_middle_N24), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[24]) );
DFFXLTS Sgf_operation_EVEN1_middle_DatO_reg_25_ ( .D(
Sgf_operation_EVEN1_middle_N25), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[25]) );
DFFXLTS Sgf_operation_EVEN1_left_DatO_reg_23_ ( .D(
Sgf_operation_EVEN1_left_N23), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[23]), .QN(DP_OP_110J18_122_9009_n96) );
DFFQX1TS Sgf_operation_EVEN1_middle_DatO_reg_0_ ( .D(
Sgf_operation_EVEN1_middle_N0), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[0]) );
DFFQX1TS Sgf_operation_EVEN1_right_DatO_reg_0_ ( .D(
Sgf_operation_EVEN1_right_N0), .CK(clk), .Q(Sgf_operation_Result[0])
);
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n323), .CK(clk), .RN(
n1617), .Q(Op_MY[11]), .QN(n420) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n332), .CK(clk), .RN(
n1616), .Q(Op_MY[20]), .QN(n417) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n334), .CK(clk), .RN(
n1626), .Q(Op_MY[22]), .QN(n564) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n321), .CK(clk), .RN(
n1628), .Q(Op_MY[9]), .QN(n415) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n329), .CK(clk), .RN(
n1629), .Q(Op_MY[17]), .QN(n563) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n314), .CK(clk), .RN(
n1620), .Q(Op_MY[2]), .QN(n414) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n313), .CK(clk), .RN(
n1619), .Q(Op_MY[1]), .QN(n561) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n191), .CK(clk),
.RN(n1621), .Q(Sgf_normalized_result[0]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n354), .CK(clk), .RN(
n1627), .Q(Op_MX[10]), .QN(n554) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n362), .CK(clk), .RN(
n1628), .Q(Op_MX[18]), .QN(n555) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n360), .CK(clk), .RN(
n1629), .Q(Op_MX[16]), .QN(n562) );
DFFSX4TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n432), .CK(clk), .SN(
n1623), .Q(n1567), .QN(Op_MY[0]) );
DFFSX4TS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n431), .CK(clk), .SN(
n1625), .Q(n1561), .QN(Op_MX[12]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n350), .CK(clk), .RN(
n1624), .Q(Op_MX[6]), .QN(n550) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n348), .CK(clk), .RN(
n1628), .Q(Op_MX[4]), .QN(n549) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n198), .CK(clk),
.RN(n1629), .Q(Sgf_normalized_result[7]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n200), .CK(clk),
.RN(n1627), .Q(Sgf_normalized_result[9]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n202), .CK(clk),
.RN(n1621), .Q(Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n204), .CK(clk),
.RN(n1628), .Q(Sgf_normalized_result[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n194), .CK(clk),
.RN(n1627), .Q(Sgf_normalized_result[3]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n196), .CK(clk),
.RN(n1621), .Q(Sgf_normalized_result[5]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n206), .CK(clk),
.RN(n1627), .Q(Sgf_normalized_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n208), .CK(clk),
.RN(n1629), .Q(Sgf_normalized_result[17]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n210), .CK(clk),
.RN(n1621), .Q(Sgf_normalized_result[19]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_47_ ( .D(n380), .CK(clk), .RN(
n1615), .Q(P_Sgf[47]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n371), .CK(clk), .RN(
n1617), .Q(Op_MX[27]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n373), .CK(clk), .RN(
n1624), .Q(Op_MX[29]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n273), .CK(clk), .RN(n1628),
.Q(exp_oper_result[7]) );
DFFRX1TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n282), .CK(clk), .RN(
n1622), .Q(FSM_add_overflow_flag) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n275), .CK(clk), .RN(n1617),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n277), .CK(clk), .RN(n1628),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n278), .CK(clk), .RN(n1627),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n279), .CK(clk), .RN(n1625),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n280), .CK(clk), .RN(n1622),
.Q(exp_oper_result[0]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n342), .CK(clk), .RN(
n1628), .Q(Op_MY[30]) );
DFFX1TS Sgf_operation_EVEN1_right_DatO_reg_23_ ( .D(
Sgf_operation_EVEN1_right_N23), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_right[23]), .QN(DP_OP_110J18_122_9009_n73) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n320), .CK(clk), .RN(
n1624), .Q(Op_MY[8]), .QN(n418) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n322), .CK(clk), .RN(
n1621), .Q(Op_MY[10]), .QN(n403) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n222), .CK(clk), .RN(
n1613), .Q(P_Sgf[7]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n221), .CK(clk), .RN(
n1615), .Q(P_Sgf[6]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n220), .CK(clk), .RN(
n1612), .Q(P_Sgf[5]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n219), .CK(clk), .RN(
n1613), .Q(P_Sgf[4]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n218), .CK(clk), .RN(
n1615), .Q(P_Sgf[3]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n319), .CK(clk), .RN(
n1627), .Q(Op_MY[7]), .QN(n416) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n328), .CK(clk), .RN(
n1624), .Q(Op_MY[16]), .QN(n557) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n327), .CK(clk), .RN(
n1628), .QN(n560) );
DFFSX4TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n572), .CK(clk), .SN(
n1622), .Q(n1562), .QN(Op_MY[12]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n316), .CK(clk), .RN(
n1618), .Q(Op_MY[4]), .QN(n559) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n192), .CK(clk),
.RN(n1617), .Q(Sgf_normalized_result[1]) );
DFFSX4TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n428), .CK(clk), .SN(
n1623), .Q(n1566), .QN(Op_MX[0]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n364), .CK(clk), .RN(
n1629), .Q(Op_MX[20]), .QN(n558) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n352), .CK(clk), .RN(
n1629), .QN(n551) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n361), .CK(clk), .RN(
n1617), .Q(Op_MX[17]), .QN(n398) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n363), .CK(clk), .RN(
n1627), .Q(Op_MX[19]), .QN(n400) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n359), .CK(clk), .RN(
n1621), .Q(Op_MX[15]), .QN(n413) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n347), .CK(clk), .RN(
n1624), .Q(Op_MX[3]), .QN(n397) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n365), .CK(clk), .RN(
n1617), .Q(Op_MX[21]), .QN(n401) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n351), .CK(clk), .RN(
n1624), .Q(Op_MX[7]), .QN(n399) );
DFFSX4TS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n430), .CK(clk), .SN(
n1623), .Q(n1568), .QN(Op_MX[11]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n367), .CK(clk), .RN(
n1624), .Q(Op_MX[23]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n370), .CK(clk), .RN(
n1622), .Q(Op_MX[26]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n369), .CK(clk), .RN(
n1622), .Q(Op_MX[25]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n335), .CK(clk), .RN(
n1617), .Q(Op_MY[23]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n368), .CK(clk), .RN(
n1625), .Q(Op_MX[24]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n338), .CK(clk), .RN(
n1628), .Q(Op_MY[26]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n339), .CK(clk), .RN(
n1624), .Q(Op_MY[27]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n304), .CK(clk), .RN(n1616),
.Q(Add_result[2]), .QN(n1586) );
DFFQX1TS Sgf_operation_EVEN1_left_DatO_reg_1_ ( .D(
Sgf_operation_EVEN1_left_N1), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[1]) );
DFFQX1TS Sgf_operation_EVEN1_left_DatO_reg_2_ ( .D(
Sgf_operation_EVEN1_left_N2), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[2]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n212), .CK(clk),
.RN(n1627), .Q(Sgf_normalized_result[21]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n366), .CK(clk), .RN(
n1617), .Q(Op_MX[22]), .QN(n419) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n346), .CK(clk), .RN(
n1627), .Q(n394), .QN(n556) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n227), .CK(clk), .RN(
n1612), .Q(P_Sgf[12]) );
DFFX1TS Sgf_operation_EVEN1_left_DatO_reg_0_ ( .D(
Sgf_operation_EVEN1_left_N0), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[0]), .QN(DP_OP_110J18_122_9009_n119) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n325), .CK(clk), .RN(
n1623), .Q(n392), .QN(n410) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n326), .CK(clk), .RN(
n1627), .Q(n391), .QN(n553) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n353), .CK(clk), .RN(
n1618), .Q(Op_MX[9]), .QN(n395) );
DFFSX4TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n425), .CK(clk), .SN(
n1623), .Q(n1560), .QN(n390) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n349), .CK(clk), .RN(
n1620), .QN(n411) );
DFFRX2TS Sel_A_Q_reg_0_ ( .D(n375), .CK(clk), .RN(n1622), .Q(FSM_selector_A),
.QN(n1584) );
AO22X1TS U405 ( .A0(n1272), .A1(P_Sgf[46]), .B0(n1549), .B1(n1271), .Y(n261)
);
AO22X1TS U406 ( .A0(n1538), .A1(P_Sgf[42]), .B0(n1549), .B1(n1263), .Y(n257)
);
AO22X1TS U407 ( .A0(n1538), .A1(P_Sgf[41]), .B0(n1549), .B1(n1261), .Y(n256)
);
AO22X1TS U408 ( .A0(n1272), .A1(P_Sgf[45]), .B0(n1549), .B1(n1269), .Y(n260)
);
AO22X1TS U409 ( .A0(n1538), .A1(P_Sgf[40]), .B0(n1549), .B1(n1259), .Y(n255)
);
AO22X1TS U410 ( .A0(n1272), .A1(P_Sgf[44]), .B0(n1549), .B1(n1267), .Y(n259)
);
AO22X1TS U411 ( .A0(n1538), .A1(P_Sgf[43]), .B0(n1549), .B1(n1265), .Y(n258)
);
NOR2X4TS U412 ( .A(n1581), .B(n1364), .Y(n1365) );
CMPR32X2TS U413 ( .A(DP_OP_111J18_123_4462_n40), .B(
DP_OP_111J18_123_4462_n44), .C(n817), .CO(n1170), .S(
Sgf_operation_EVEN1_middle_N21) );
CMPR32X2TS U414 ( .A(mult_x_23_n32), .B(n887), .C(n886), .CO(n890), .S(
Sgf_operation_EVEN1_left_N22) );
CMPR32X2TS U415 ( .A(DP_OP_111J18_123_4462_n49), .B(
DP_OP_111J18_123_4462_n45), .C(n684), .CO(n817), .S(
Sgf_operation_EVEN1_middle_N20) );
CMPR32X2TS U416 ( .A(mult_x_55_n45), .B(mult_x_55_n41), .C(n938), .CO(n939),
.S(Sgf_operation_EVEN1_right_N19) );
CMPR32X2TS U417 ( .A(DP_OP_111J18_123_4462_n50), .B(
DP_OP_111J18_123_4462_n56), .C(n683), .CO(n684), .S(
Sgf_operation_EVEN1_middle_N19) );
NAND2X1TS U418 ( .A(Sgf_normalized_result[19]), .B(n1517), .Y(n1519) );
CMPR32X2TS U419 ( .A(mult_x_55_n53), .B(mult_x_55_n58), .C(n937), .CO(n940),
.S(Sgf_operation_EVEN1_right_N17) );
CMPR32X2TS U420 ( .A(mult_x_23_n45), .B(mult_x_23_n41), .C(n833), .CO(n834),
.S(Sgf_operation_EVEN1_left_N19) );
CMPR32X2TS U421 ( .A(mult_x_23_n46), .B(mult_x_23_n52), .C(n824), .CO(n833),
.S(Sgf_operation_EVEN1_left_N18) );
NAND2X1TS U422 ( .A(Sgf_normalized_result[17]), .B(n1513), .Y(n1515) );
CMPR32X2TS U423 ( .A(mult_x_55_n67), .B(mult_x_55_n74), .C(n675), .CO(n941),
.S(Sgf_operation_EVEN1_right_N15) );
CMPR32X2TS U424 ( .A(mult_x_23_n59), .B(mult_x_23_n66), .C(n826), .CO(n835),
.S(Sgf_operation_EVEN1_left_N16) );
NAND2X1TS U425 ( .A(Sgf_normalized_result[15]), .B(n1509), .Y(n1511) );
CMPR32X2TS U426 ( .A(n1274), .B(Sgf_operation_EVEN1_Q_left[13]), .C(n1273),
.CO(n1276), .S(n1275) );
CMPR32X2TS U427 ( .A(mult_x_23_n67), .B(mult_x_23_n74), .C(n649), .CO(n826),
.S(Sgf_operation_EVEN1_left_N15) );
CMPR32X2TS U428 ( .A(mult_x_55_n85), .B(mult_x_55_n93), .C(n674), .CO(n942),
.S(Sgf_operation_EVEN1_right_N13) );
CMPR32X2TS U429 ( .A(mult_x_23_n75), .B(mult_x_23_n84), .C(n825), .CO(n649),
.S(Sgf_operation_EVEN1_left_N14) );
NAND2X1TS U430 ( .A(Sgf_normalized_result[13]), .B(n1505), .Y(n1507) );
CMPR32X2TS U431 ( .A(n728), .B(Sgf_operation_EVEN1_Q_middle[24]), .C(n727),
.CO(n726), .S(n1353) );
CMPR32X2TS U432 ( .A(mult_x_55_n102), .B(mult_x_55_n109), .C(n673), .CO(n943), .S(Sgf_operation_EVEN1_right_N11) );
CMPR32X2TS U433 ( .A(n1160), .B(n1238), .C(n1159), .CO(
DP_OP_111J18_123_4462_n83), .S(DP_OP_111J18_123_4462_n84) );
CMPR32X2TS U434 ( .A(mult_x_23_n94), .B(mult_x_23_n101), .C(n823), .CO(n836),
.S(Sgf_operation_EVEN1_left_N12) );
CMPR32X2TS U435 ( .A(n1081), .B(n1080), .C(n1079), .CO(mult_x_55_n89), .S(
mult_x_55_n90) );
NAND2X1TS U436 ( .A(Sgf_normalized_result[11]), .B(n1501), .Y(n1503) );
CMPR32X2TS U437 ( .A(n1155), .B(n1238), .C(n1154), .CO(
DP_OP_111J18_123_4462_n93), .S(DP_OP_111J18_123_4462_n94) );
CMPR32X2TS U438 ( .A(mult_x_23_n102), .B(mult_x_23_n109), .C(n648), .CO(n823), .S(Sgf_operation_EVEN1_left_N11) );
CMPR32X2TS U439 ( .A(mult_x_55_n116), .B(mult_x_55_n122), .C(n672), .CO(n944), .S(Sgf_operation_EVEN1_right_N9) );
CMPR32X2TS U440 ( .A(mult_x_23_n110), .B(mult_x_23_n115), .C(n822), .CO(n648), .S(Sgf_operation_EVEN1_left_N10) );
NAND2X1TS U441 ( .A(Sgf_normalized_result[9]), .B(n1497), .Y(n1499) );
CMPR32X2TS U442 ( .A(mult_x_55_n128), .B(mult_x_55_n132), .C(n676), .CO(n945), .S(Sgf_operation_EVEN1_right_N7) );
CMPR32X2TS U443 ( .A(n1072), .B(n1071), .C(n1070), .CO(mult_x_55_n124), .S(
mult_x_55_n125) );
CMPR32X2TS U444 ( .A(mult_x_23_n123), .B(mult_x_23_n127), .C(n827), .CO(n837), .S(Sgf_operation_EVEN1_left_N8) );
CMPR32X2TS U445 ( .A(n1083), .B(DP_OP_111J18_123_4462_n144), .C(
DP_OP_111J18_123_4462_n140), .CO(n1130), .S(
Sgf_operation_EVEN1_middle_N7) );
CMPR42X1TS U446 ( .A(DP_OP_111J18_123_4462_n212), .B(
DP_OP_111J18_123_4462_n137), .C(DP_OP_111J18_123_4462_n138), .D(
DP_OP_111J18_123_4462_n250), .ICI(DP_OP_111J18_123_4462_n200), .S(
DP_OP_111J18_123_4462_n135), .ICO(DP_OP_111J18_123_4462_n133), .CO(
DP_OP_111J18_123_4462_n134) );
INVX2TS U447 ( .A(n1220), .Y(n1219) );
INVX4TS U448 ( .A(n460), .Y(n461) );
CMPR32X2TS U449 ( .A(n936), .B(n935), .C(n934), .CO(mult_x_23_n124), .S(
mult_x_23_n125) );
NAND2X4TS U450 ( .A(n401), .B(n419), .Y(n851) );
CMPR32X2TS U451 ( .A(n1246), .B(n1245), .C(n1244), .CO(n1195), .S(
DP_OP_111J18_123_4462_n137) );
AO22X1TS U452 ( .A0(n475), .A1(n803), .B0(n610), .B1(n1218), .Y(n407) );
NAND2X1TS U453 ( .A(Sgf_normalized_result[5]), .B(n1489), .Y(n1491) );
CMPR32X2TS U454 ( .A(Op_MY[10]), .B(Op_MY[22]), .C(n681), .CO(n682), .S(
n1239) );
CMPR32X2TS U455 ( .A(Op_MX[10]), .B(Op_MX[22]), .C(n609), .CO(n679), .S(n610) );
INVX2TS U456 ( .A(n1199), .Y(n1197) );
INVX2TS U457 ( .A(n1221), .Y(n474) );
CMPR32X2TS U458 ( .A(Op_MY[9]), .B(n530), .C(n680), .CO(n681), .S(n1242) );
CMPR32X2TS U459 ( .A(n536), .B(Op_MX[21]), .C(n608), .CO(n609), .S(n1221) );
CMPR32X2TS U460 ( .A(Op_MY[8]), .B(Op_MY[20]), .C(n678), .CO(n680), .S(n1199) );
CMPR32X2TS U461 ( .A(n910), .B(n909), .C(n908), .CO(n905), .S(
Sgf_operation_EVEN1_left_N3) );
INVX6TS U462 ( .A(n477), .Y(n1215) );
CMPR32X2TS U463 ( .A(n538), .B(Op_MX[20]), .C(n613), .CO(n608), .S(n616) );
CMPR32X2TS U464 ( .A(Op_MY[7]), .B(n390), .C(n1086), .CO(n678), .S(n1172) );
INVX2TS U465 ( .A(n395), .Y(n536) );
CLKBUFX2TS U466 ( .A(Op_MX[21]), .Y(n911) );
INVX2TS U467 ( .A(n468), .Y(n469) );
INVX2TS U468 ( .A(n1225), .Y(n476) );
CMPR32X2TS U469 ( .A(n767), .B(n766), .C(n765), .CO(n762), .S(n1320) );
CMPR32X2TS U470 ( .A(n497), .B(Op_MY[17]), .C(n677), .CO(n1087), .S(n1236)
);
INVX2TS U471 ( .A(n1185), .Y(n1184) );
OAI221X4TS U472 ( .A0(Op_MX[14]), .A1(n478), .B0(n1558), .B1(n489), .C0(n933), .Y(n630) );
CMPR32X2TS U473 ( .A(n1314), .B(Sgf_operation_EVEN1_Q_right[21]), .C(n1313),
.CO(n1316), .S(n1315) );
CMPR32X2TS U474 ( .A(Op_MX[6]), .B(Op_MX[18]), .C(n1109), .CO(n614), .S(
n1110) );
CMPR32X2TS U475 ( .A(Op_MY[4]), .B(Op_MY[16]), .C(n601), .CO(n677), .S(n1185) );
CMPR32X2TS U476 ( .A(Op_MY[3]), .B(n543), .C(n581), .CO(n601), .S(n1178) );
CLKBUFX2TS U477 ( .A(n1249), .Y(n1182) );
CMPR32X2TS U478 ( .A(n1292), .B(Sgf_operation_EVEN1_Q_right[19]), .C(n1291),
.CO(n1310), .S(n1293) );
CMPR32X2TS U479 ( .A(Op_MX[4]), .B(Op_MX[16]), .C(n576), .CO(n606), .S(n577)
);
CMPR32X2TS U480 ( .A(Op_MY[2]), .B(n391), .C(n586), .CO(n581), .S(n1121) );
AOI22X1TS U481 ( .A0(n540), .A1(n1558), .B0(Op_MX[14]), .B1(mult_x_23_n219),
.Y(n629) );
CLKBUFX2TS U482 ( .A(n1238), .Y(n471) );
CMPR32X2TS U483 ( .A(n1298), .B(Sgf_operation_EVEN1_Q_right[17]), .C(n1297),
.CO(n1285), .S(n1299) );
CMPR32X2TS U484 ( .A(n394), .B(Op_MX[14]), .C(n583), .CO(n575), .S(n587) );
CMPR32X2TS U485 ( .A(n791), .B(n790), .C(n789), .CO(n786), .S(n1295) );
INVX2TS U486 ( .A(n537), .Y(n468) );
OAI21XLTS U487 ( .A0(n1251), .A1(n1250), .B0(n1249), .Y(n1257) );
CLKINVX3TS U488 ( .A(n1182), .Y(n547) );
AOI22X1TS U489 ( .A0(n1172), .A1(n547), .B0(n1249), .B1(n1171), .Y(n1192) );
INVX2TS U490 ( .A(n476), .Y(n477) );
NOR2XLTS U491 ( .A(n1059), .B(n1565), .Y(n960) );
OAI21XLTS U492 ( .A0(n1227), .A1(n472), .B0(n1225), .Y(n1231) );
INVX2TS U493 ( .A(n1234), .Y(n1233) );
OAI21XLTS U494 ( .A0(n539), .A1(n1558), .B0(n479), .Y(mult_x_23_n205) );
NOR2XLTS U495 ( .A(mult_x_23_n219), .B(n1561), .Y(n850) );
NOR2XLTS U496 ( .A(n1562), .B(n929), .Y(n935) );
NAND2X1TS U497 ( .A(Sgf_normalized_result[7]), .B(n1493), .Y(n1495) );
NAND2X1TS U498 ( .A(Sgf_normalized_result[21]), .B(n1522), .Y(n1524) );
NOR2XLTS U499 ( .A(n1142), .B(n462), .Y(DP_OP_111J18_123_4462_n214) );
NOR2XLTS U500 ( .A(n1562), .B(n933), .Y(n841) );
XOR2X1TS U501 ( .A(n799), .B(Sgf_operation_EVEN1_Q_left[23]), .Y(n800) );
OAI21XLTS U502 ( .A0(n1528), .A1(Sgf_normalized_result[23]), .B0(n1531), .Y(
n1529) );
OAI211XLTS U503 ( .A0(Sgf_normalized_result[19]), .A1(n1517), .B0(n1521),
.C0(n1519), .Y(n1518) );
OAI211XLTS U504 ( .A0(n1412), .A1(n1598), .B0(n1387), .C0(n1386), .Y(n206)
);
ADDFHX2TS U505 ( .A(n805), .B(DP_OP_111J18_123_4462_n36), .CI(n804), .CO(
n806), .S(Sgf_operation_EVEN1_middle_N23) );
OAI211XLTS U506 ( .A0(n1412), .A1(n1595), .B0(n1408), .C0(n1407), .Y(n209)
);
ADDHX2TS U507 ( .A(Sgf_operation_EVEN1_Q_left[16]), .B(n1258), .CO(n1260),
.S(n1259) );
NAND2X2TS U508 ( .A(n620), .B(n619), .Y(n820) );
AO22X1TS U509 ( .A0(n1542), .A1(P_Sgf[22]), .B0(n1551), .B1(n1318), .Y(n237)
);
AO22XLTS U510 ( .A0(n1532), .A1(n1504), .B0(n1526), .B1(n522), .Y(n294) );
AO22X2TS U511 ( .A0(n1110), .A1(n1226), .B0(n473), .B1(n1227), .Y(n408) );
BUFX3TS U512 ( .A(n1414), .Y(n533) );
INVX2TS U513 ( .A(n1178), .Y(n1177) );
INVX4TS U514 ( .A(n1534), .Y(n1553) );
INVX3TS U515 ( .A(n1527), .Y(n1532) );
INVX4TS U516 ( .A(n411), .Y(n537) );
NAND2BX1TS U517 ( .AN(Sgf_operation_EVEN1_Q_middle[1]), .B(
Sgf_operation_EVEN1_Q_left[1]), .Y(n793) );
INVX4TS U518 ( .A(n1563), .Y(n527) );
ADDHX2TS U519 ( .A(Sgf_operation_EVEN1_Q_left[21]), .B(n1268), .CO(n1270),
.S(n1269) );
ADDHX2TS U520 ( .A(Sgf_operation_EVEN1_Q_left[20]), .B(n1266), .CO(n1268),
.S(n1267) );
ADDHX2TS U521 ( .A(Sgf_operation_EVEN1_Q_left[18]), .B(n1262), .CO(n1264),
.S(n1263) );
ADDHX2TS U522 ( .A(Sgf_operation_EVEN1_Q_left[17]), .B(n1260), .CO(n1262),
.S(n1261) );
AO22X1TS U523 ( .A0(n1538), .A1(P_Sgf[39]), .B0(n1549), .B1(n1279), .Y(n254)
);
AO22X1TS U524 ( .A0(n1538), .A1(P_Sgf[38]), .B0(n1549), .B1(n1277), .Y(n253)
);
XOR2X1TS U525 ( .A(n1011), .B(n1010), .Y(Sgf_operation_EVEN1_right_N23) );
AO22X1TS U526 ( .A0(n1538), .A1(P_Sgf[37]), .B0(n1355), .B1(n1275), .Y(n252)
);
AO22X1TS U527 ( .A0(n1538), .A1(P_Sgf[36]), .B0(n1355), .B1(n1354), .Y(n251)
);
AO22X1TS U528 ( .A0(n1538), .A1(P_Sgf[35]), .B0(n1355), .B1(n1351), .Y(n250)
);
AO22X1TS U529 ( .A0(n1538), .A1(P_Sgf[34]), .B0(n1355), .B1(n1348), .Y(n249)
);
XOR2X1TS U530 ( .A(n617), .B(n611), .Y(Sgf_operation_EVEN1_middle_N17) );
AO22X1TS U531 ( .A0(n1538), .A1(P_Sgf[33]), .B0(n1355), .B1(n1345), .Y(n248)
);
ADDFHX2TS U532 ( .A(DP_OP_111J18_123_4462_n71), .B(DP_OP_111J18_123_4462_n78), .CI(n818), .CO(n617), .S(Sgf_operation_EVEN1_middle_N16) );
AOI2BB1X1TS U533 ( .A0N(n1532), .A1N(FSM_add_overflow_flag), .B0(n1531), .Y(
n282) );
AO21X1TS U534 ( .A0(n518), .A1(n1526), .B0(n1525), .Y(n284) );
ADDFHX2TS U535 ( .A(DP_OP_111J18_123_4462_n79), .B(DP_OP_111J18_123_4462_n88), .CI(n612), .CO(n818), .S(Sgf_operation_EVEN1_middle_N15) );
AO22X1TS U536 ( .A0(n1538), .A1(P_Sgf[32]), .B0(n1355), .B1(n1342), .Y(n247)
);
ADDFHX2TS U537 ( .A(DP_OP_111J18_123_4462_n89), .B(DP_OP_111J18_123_4462_n97), .CI(n819), .CO(n612), .S(Sgf_operation_EVEN1_middle_N14) );
AO22X1TS U538 ( .A0(n1538), .A1(P_Sgf[31]), .B0(n1550), .B1(n1339), .Y(n246)
);
AO22X1TS U539 ( .A0(n1532), .A1(n1520), .B0(n1526), .B1(n526), .Y(n286) );
AO22X1TS U540 ( .A0(n1538), .A1(P_Sgf[30]), .B0(n1355), .B1(n1336), .Y(n245)
);
OAI211X1TS U541 ( .A0(Sgf_normalized_result[21]), .A1(n1522), .B0(n1521),
.C0(n1524), .Y(n1523) );
ADDFHX2TS U542 ( .A(DP_OP_111J18_123_4462_n98), .B(
DP_OP_111J18_123_4462_n105), .CI(n685), .CO(n819), .S(
Sgf_operation_EVEN1_middle_N13) );
AO22X1TS U543 ( .A0(n1538), .A1(P_Sgf[29]), .B0(n1548), .B1(n1537), .Y(n244)
);
ADDFX1TS U544 ( .A(DP_OP_111J18_123_4462_n106), .B(
DP_OP_111J18_123_4462_n113), .CI(n821), .CO(n685), .S(
Sgf_operation_EVEN1_middle_N12) );
AO22X1TS U545 ( .A0(n1542), .A1(P_Sgf[28]), .B0(n1548), .B1(n1541), .Y(n243)
);
AO22X1TS U546 ( .A0(n1532), .A1(n1516), .B0(n1526), .B1(n525), .Y(n288) );
ADDFHX2TS U547 ( .A(DP_OP_111J18_123_4462_n122), .B(
DP_OP_111J18_123_4462_n127), .CI(n1082), .CO(n1152), .S(
Sgf_operation_EVEN1_middle_N10) );
AO22X1TS U548 ( .A0(n1542), .A1(P_Sgf[27]), .B0(n1551), .B1(n1333), .Y(n242)
);
AO22X1TS U549 ( .A0(n1542), .A1(P_Sgf[26]), .B0(n1551), .B1(n1330), .Y(n241)
);
AO22X1TS U550 ( .A0(n1532), .A1(n1512), .B0(n1526), .B1(n524), .Y(n290) );
OAI21X1TS U551 ( .A0(n1139), .A1(n1088), .B0(n813), .Y(n812) );
ADDFHX2TS U552 ( .A(DP_OP_111J18_123_4462_n128), .B(
DP_OP_111J18_123_4462_n134), .CI(n816), .CO(n1082), .S(
Sgf_operation_EVEN1_middle_N9) );
ADDFHX2TS U553 ( .A(DP_OP_111J18_123_4462_n135), .B(
DP_OP_111J18_123_4462_n139), .CI(n1130), .CO(n816), .S(
Sgf_operation_EVEN1_middle_N8) );
AO22X1TS U554 ( .A0(n1542), .A1(P_Sgf[25]), .B0(n1551), .B1(n1327), .Y(n240)
);
AO22X1TS U555 ( .A0(n1542), .A1(P_Sgf[24]), .B0(n1551), .B1(n1324), .Y(n239)
);
OAI32X1TS U556 ( .A0(n460), .A1(n1161), .A2(n467), .B0(n1102), .B1(n1100),
.Y(n1151) );
AO22X1TS U557 ( .A0(n1532), .A1(n1508), .B0(n1526), .B1(n523), .Y(n292) );
AO22X1TS U558 ( .A0(n1542), .A1(P_Sgf[23]), .B0(n1551), .B1(n1321), .Y(n238)
);
OAI32X1TS U559 ( .A0(n1243), .A1(n1242), .A2(n1251), .B0(n1241), .B1(n1240),
.Y(DP_OP_111J18_123_4462_n248) );
NOR2X1TS U560 ( .A(n1142), .B(n1255), .Y(DP_OP_111J18_123_4462_n200) );
NAND3BX1TS U561 ( .AN(Exp_module_Data_S[7]), .B(n1476), .C(n1440), .Y(n1441)
);
OAI211X1TS U562 ( .A0(n1412), .A1(n1604), .B0(n1391), .C0(n1390), .Y(n200)
);
OAI211X1TS U563 ( .A0(n1412), .A1(n1602), .B0(n1393), .C0(n1392), .Y(n202)
);
OAI211X1TS U564 ( .A0(n1412), .A1(n1599), .B0(n1406), .C0(n1405), .Y(n205)
);
OAI211X1TS U565 ( .A0(n1587), .A1(n1404), .B0(n1399), .C0(n1398), .Y(n211)
);
OAI211X1TS U566 ( .A0(n1412), .A1(n1600), .B0(n1389), .C0(n1388), .Y(n204)
);
OAI211X1TS U567 ( .A0(n1404), .A1(n1607), .B0(n1401), .C0(n1400), .Y(n197)
);
OAI211X1TS U568 ( .A0(n1412), .A1(n1597), .B0(n1411), .C0(n1410), .Y(n207)
);
OAI211X1TS U569 ( .A0(n1481), .A1(n1480), .B0(n1416), .C0(n1415), .Y(n213)
);
OAI211X1TS U570 ( .A0(n1404), .A1(n1603), .B0(n1403), .C0(n1402), .Y(n201)
);
OAI211X1TS U571 ( .A0(n1404), .A1(n1601), .B0(n1395), .C0(n1394), .Y(n203)
);
OAI211XLTS U572 ( .A0(n1404), .A1(n1605), .B0(n1397), .C0(n1396), .Y(n199)
);
OAI211XLTS U573 ( .A0(n1404), .A1(n1588), .B0(n1377), .C0(n1376), .Y(n195)
);
OAI211XLTS U574 ( .A0(n1404), .A1(n1591), .B0(n1375), .C0(n1374), .Y(n192)
);
NOR2X1TS U575 ( .A(n1142), .B(n1193), .Y(n1145) );
NOR2X1TS U576 ( .A(n1142), .B(n464), .Y(n589) );
OAI211XLTS U577 ( .A0(n1404), .A1(n1590), .B0(n1367), .C0(n1366), .Y(n193)
);
OAI211XLTS U578 ( .A0(n1404), .A1(n1592), .B0(n1369), .C0(n1368), .Y(n191)
);
OAI211XLTS U579 ( .A0(n1404), .A1(n1589), .B0(n1371), .C0(n1370), .Y(n194)
);
OAI211XLTS U580 ( .A0(n1404), .A1(n1608), .B0(n1373), .C0(n1372), .Y(n196)
);
OAI211XLTS U581 ( .A0(n1404), .A1(n1594), .B0(n1383), .C0(n1382), .Y(n210)
);
OAI211XLTS U582 ( .A0(n1593), .A1(n1404), .B0(n1379), .C0(n1378), .Y(n212)
);
OAI211XLTS U583 ( .A0(n1404), .A1(n1606), .B0(n1385), .C0(n1384), .Y(n198)
);
OAI211XLTS U584 ( .A0(n1404), .A1(n1596), .B0(n1381), .C0(n1380), .Y(n208)
);
OAI221X4TS U585 ( .A0(n587), .A1(n1249), .B0(n1250), .B1(n546), .C0(n585),
.Y(n588) );
NAND3X1TS U586 ( .A(n1445), .B(n1444), .C(n1443), .Y(n376) );
INVX2TS U587 ( .A(n1110), .Y(n1227) );
CMPR32X2TS U588 ( .A(n527), .B(n529), .C(n1087), .CO(n1086), .S(n1234) );
OAI221X4TS U589 ( .A0(Op_MX[6]), .A1(n470), .B0(n550), .B1(n399), .C0(n1054),
.Y(n957) );
OAI221X4TS U590 ( .A0(Op_MX[10]), .A1(n1023), .B0(n554), .B1(n1568), .C0(
n1058), .Y(n962) );
AOI22X1TS U591 ( .A0(n1454), .A1(Data_MY[6]), .B0(n1453), .B1(n527), .Y(n574) );
AOI22X1TS U592 ( .A0(n1454), .A1(Data_MY[5]), .B0(n1446), .B1(Op_MY[5]), .Y(
n573) );
NOR2X4TS U593 ( .A(n1476), .B(n1550), .Y(n1436) );
OR3X2TS U594 ( .A(underflow_flag), .B(overflow_flag), .C(n1553), .Y(n1533)
);
OAI21X1TS U595 ( .A0(Op_MY[12]), .A1(n852), .B0(n851), .Y(n925) );
CLKINVX3TS U596 ( .A(n423), .Y(n531) );
NOR2X1TS U597 ( .A(n1567), .B(n1069), .Y(n949) );
INVX3TS U598 ( .A(n1447), .Y(n1435) );
OAI221X4TS U599 ( .A0(n394), .A1(n1033), .B0(n556), .B1(n397), .C0(n1069),
.Y(n654) );
AOI22X1TS U600 ( .A0(n1478), .A1(Data_MY[12]), .B0(n1453), .B1(Op_MY[12]),
.Y(n572) );
CLKINVX3TS U601 ( .A(n567), .Y(n1409) );
OAI221X4TS U602 ( .A0(Op_MX[4]), .A1(n469), .B0(n549), .B1(n468), .C0(n1078),
.Y(n651) );
NOR2X1TS U603 ( .A(n1562), .B(n878), .Y(n638) );
NOR2X1TS U604 ( .A(n1567), .B(n1075), .Y(n1071) );
OAI21X1TS U605 ( .A0(n488), .A1(n558), .B0(n483), .Y(mult_x_23_n163) );
OAI221X4TS U606 ( .A0(n538), .A1(n536), .B0(n551), .B1(n492), .C0(n1075),
.Y(n952) );
OR2X1TS U607 ( .A(n1481), .B(n1581), .Y(n423) );
OAI21X1TS U608 ( .A0(n541), .A1(n556), .B0(n459), .Y(mult_x_55_n211) );
NOR2X1TS U609 ( .A(n1567), .B(n1078), .Y(n662) );
OAI221X4TS U610 ( .A0(Op_MX[18]), .A1(n485), .B0(n555), .B1(n487), .C0(n917),
.Y(n830) );
OAI32X1TS U611 ( .A0(Op_MX[12]), .A1(n529), .A2(mult_x_23_n219), .B0(n828),
.B1(n1561), .Y(n832) );
OAI32X1TS U612 ( .A0(Op_MX[0]), .A1(Op_MY[5]), .A2(mult_x_55_n225), .B0(n999), .B1(n1566), .Y(mult_x_55_n232) );
NOR2XLTS U613 ( .A(n1142), .B(n1240), .Y(Sgf_operation_EVEN1_middle_N0) );
INVX4TS U614 ( .A(n888), .Y(n852) );
OR2X4TS U615 ( .A(FS_Module_state_reg[1]), .B(n565), .Y(n566) );
NAND3X1TS U616 ( .A(FS_Module_state_reg[1]), .B(FSM_add_overflow_flag), .C(
n1430), .Y(n686) );
NAND3XLTS U617 ( .A(n1306), .B(n1305), .C(n1304), .Y(n1308) );
OA21X2TS U618 ( .A0(n1356), .A1(n1430), .B0(FS_Module_state_reg[1]), .Y(n567) );
ADDFHX2TS U619 ( .A(n797), .B(n796), .CI(n795), .CO(n792), .S(n1544) );
INVX1TS U620 ( .A(n1430), .Y(n1309) );
INVX3TS U621 ( .A(n1161), .Y(n1142) );
NAND2X1TS U622 ( .A(n1609), .B(n571), .Y(n565) );
NAND3X1TS U623 ( .A(FS_Module_state_reg[3]), .B(n1432), .C(n1569), .Y(n1530)
);
BUFX4TS U624 ( .A(n1014), .Y(n470) );
NOR2X1TS U625 ( .A(n1059), .B(n414), .Y(n1032) );
NOR2X1TS U626 ( .A(n1059), .B(n416), .Y(n955) );
NAND2X1TS U627 ( .A(n1432), .B(n571), .Y(n1446) );
OR2X2TS U628 ( .A(exp_oper_result[8]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
INVX2TS U629 ( .A(Sgf_operation_Result[0]), .Y(n798) );
NOR2X1TS U630 ( .A(FS_Module_state_reg[3]), .B(n1609), .Y(n1357) );
OAI21X1TS U631 ( .A0(n419), .A1(n496), .B0(n892), .Y(n891) );
ADDFHX4TS U632 ( .A(DP_OP_111J18_123_4462_n37), .B(DP_OP_111J18_123_4462_n39), .CI(n1170), .CO(n804), .S(Sgf_operation_EVEN1_middle_N22) );
ADDHX4TS U633 ( .A(Sgf_operation_EVEN1_Q_left[15]), .B(n1278), .CO(n1258),
.S(n1279) );
ADDFHX2TS U634 ( .A(n1332), .B(Sgf_operation_EVEN1_Q_left[3]), .CI(n1331),
.CO(n1539), .S(n1333) );
ADDHX4TS U635 ( .A(Sgf_operation_EVEN1_Q_left[14]), .B(n1276), .CO(n1278),
.S(n1277) );
CMPR42X2TS U636 ( .A(DP_OP_111J18_123_4462_n120), .B(
DP_OP_111J18_123_4462_n117), .C(DP_OP_111J18_123_4462_n247), .D(
DP_OP_111J18_123_4462_n121), .ICI(DP_OP_111J18_123_4462_n186), .S(
DP_OP_111J18_123_4462_n114), .ICO(DP_OP_111J18_123_4462_n112), .CO(
DP_OP_111J18_123_4462_n113) );
OAI21X4TS U637 ( .A0(DP_OP_111J18_123_4462_n70), .A1(
DP_OP_111J18_123_4462_n63), .B0(n617), .Y(n620) );
CMPR42X2TS U638 ( .A(DP_OP_111J18_123_4462_n198), .B(
DP_OP_111J18_123_4462_n248), .C(DP_OP_111J18_123_4462_n187), .D(
DP_OP_111J18_123_4462_n126), .ICI(DP_OP_111J18_123_4462_n125), .S(
DP_OP_111J18_123_4462_n122), .ICO(DP_OP_111J18_123_4462_n120), .CO(
DP_OP_111J18_123_4462_n121) );
XNOR2X4TS U639 ( .A(n815), .B(n814), .Y(Sgf_operation_EVEN1_middle_N25) );
ADDFHX4TS U640 ( .A(n808), .B(n807), .CI(n806), .CO(n815), .S(
Sgf_operation_EVEN1_middle_N24) );
INVX2TS U641 ( .A(n1080), .Y(n959) );
BUFX4TS U642 ( .A(n951), .Y(n1075) );
BUFX4TS U643 ( .A(n956), .Y(n1054) );
OAI22X1TS U644 ( .A0(n1255), .A1(n1104), .B0(n1253), .B1(n1106), .Y(
DP_OP_111J18_123_4462_n197) );
OAI22X1TS U645 ( .A0(n1193), .A1(n1125), .B0(n588), .B1(n1127), .Y(
DP_OP_111J18_123_4462_n235) );
OAI22X1TS U646 ( .A0(n1193), .A1(n1191), .B0(n588), .B1(n1183), .Y(n1246) );
BUFX4TS U647 ( .A(n622), .Y(n929) );
ADDHXLTS U648 ( .A(n832), .B(n831), .CO(mult_x_23_n129), .S(mult_x_23_n130)
);
BUFX4TS U649 ( .A(n626), .Y(n878) );
BUFX4TS U650 ( .A(n629), .Y(n933) );
AOI22X1TS U651 ( .A0(n1199), .A1(n1226), .B0(n1198), .B1(n1197), .Y(n1204)
);
OAI22X1TS U652 ( .A0(n1217), .A1(n1216), .B0(n476), .B1(n463), .Y(n1232) );
INVX2TS U653 ( .A(n1139), .Y(n1138) );
ADDHXLTS U654 ( .A(n1203), .B(n1202), .CO(n1209), .S(
DP_OP_111J18_123_4462_n119) );
ADDHXLTS U655 ( .A(n1248), .B(n1247), .CO(DP_OP_111J18_123_4462_n131), .S(
n1194) );
OAI22X1TS U656 ( .A0(n465), .A1(n1190), .B0(n1205), .B1(n1189), .Y(n1248) );
AOI22X1TS U657 ( .A0(n1185), .A1(n1226), .B0(n1198), .B1(n1184), .Y(n1189)
);
AOI22X1TS U658 ( .A0(n1234), .A1(n547), .B0(n1249), .B1(n1233), .Y(n1191) );
AOI22X1TS U659 ( .A0(n1236), .A1(n547), .B0(n1249), .B1(n1175), .Y(n1183) );
INVX2TS U660 ( .A(n577), .Y(n1140) );
ADDFHX2TS U661 ( .A(n776), .B(n775), .CI(n774), .CO(n771), .S(n1311) );
ADDFHX2TS U662 ( .A(n761), .B(n760), .CI(n759), .CO(n756), .S(n1326) );
ADDFHX2TS U663 ( .A(n755), .B(n754), .CI(n753), .CO(n750), .S(n1332) );
ADDFHX2TS U664 ( .A(n749), .B(n748), .CI(n747), .CO(n744), .S(n1536) );
ADDFHX2TS U665 ( .A(n743), .B(n742), .CI(n741), .CO(n738), .S(n1338) );
ADDFHX2TS U666 ( .A(n734), .B(n733), .CI(n732), .CO(n729), .S(n1347) );
INVX2TS U667 ( .A(n1043), .Y(n954) );
BUFX4TS U668 ( .A(n650), .Y(n1078) );
INVX2TS U669 ( .A(n1172), .Y(n1171) );
INVX2TS U670 ( .A(n1236), .Y(n1175) );
INVX2TS U671 ( .A(n587), .Y(n1250) );
OAI32X1TS U672 ( .A0(Op_MX[12]), .A1(n390), .A2(mult_x_23_n219), .B0(n928),
.B1(n1561), .Y(n936) );
BUFX4TS U673 ( .A(n829), .Y(n917) );
ADDFHX2TS U674 ( .A(n1540), .B(Sgf_operation_EVEN1_Q_left[4]), .CI(n1539),
.CO(n1535), .S(n1541) );
ADDFHX2TS U675 ( .A(n1335), .B(Sgf_operation_EVEN1_Q_left[6]), .CI(n1334),
.CO(n1337), .S(n1336) );
ADDFHX2TS U676 ( .A(n1341), .B(Sgf_operation_EVEN1_Q_left[8]), .CI(n1340),
.CO(n1343), .S(n1342) );
ADDFHX2TS U677 ( .A(n1347), .B(Sgf_operation_EVEN1_Q_left[10]), .CI(n1346),
.CO(n1349), .S(n1348) );
ADDFHX2TS U678 ( .A(n1353), .B(Sgf_operation_EVEN1_Q_left[12]), .CI(n1352),
.CO(n1273), .S(n1354) );
NAND2X1TS U679 ( .A(Sgf_normalized_result[3]), .B(n1485), .Y(n1487) );
NAND2X1TS U680 ( .A(n1570), .B(n1487), .Y(n1489) );
NOR2X2TS U681 ( .A(n1571), .B(n1491), .Y(n1493) );
NOR2X2TS U682 ( .A(n1573), .B(n1499), .Y(n1501) );
NOR2X2TS U683 ( .A(n1574), .B(n1503), .Y(n1505) );
NOR2X2TS U684 ( .A(n1575), .B(n1507), .Y(n1509) );
INVX2TS U685 ( .A(DP_OP_111J18_123_4462_n70), .Y(n618) );
CMPR42X1TS U686 ( .A(DP_OP_111J18_123_4462_n240), .B(
DP_OP_111J18_123_4462_n227), .C(DP_OP_111J18_123_4462_n148), .D(
DP_OP_111J18_123_4462_n252), .ICI(DP_OP_111J18_123_4462_n214), .S(
DP_OP_111J18_123_4462_n145), .ICO(DP_OP_111J18_123_4462_n143), .CO(
DP_OP_111J18_123_4462_n144) );
OAI32X1TS U687 ( .A0(Op_MX[12]), .A1(n543), .A2(n927), .B0(n631), .B1(n1561),
.Y(n639) );
OAI32X1TS U688 ( .A0(Op_MX[12]), .A1(n391), .A2(n927), .B0(n640), .B1(n1561),
.Y(n644) );
AO22XLTS U689 ( .A0(n1478), .A1(Data_MY[13]), .B0(n1453), .B1(n392), .Y(n325) );
AO22XLTS U690 ( .A0(Data_MY[27]), .A1(n1435), .B0(n1447), .B1(Op_MY[27]),
.Y(n339) );
AO22XLTS U691 ( .A0(Data_MY[26]), .A1(n1435), .B0(n1452), .B1(Op_MY[26]),
.Y(n338) );
AO22XLTS U692 ( .A0(Data_MX[24]), .A1(n1435), .B0(n1452), .B1(Op_MX[24]),
.Y(n368) );
AO22XLTS U693 ( .A0(Data_MX[25]), .A1(n1435), .B0(n1447), .B1(Op_MX[25]),
.Y(n369) );
AO22XLTS U694 ( .A0(Data_MX[26]), .A1(n1435), .B0(n1447), .B1(Op_MX[26]),
.Y(n370) );
AO22XLTS U695 ( .A0(Data_MX[23]), .A1(n1435), .B0(n1447), .B1(Op_MX[23]),
.Y(n367) );
AO22XLTS U696 ( .A0(n1451), .A1(Data_MX[7]), .B0(n1449), .B1(Op_MX[7]), .Y(
n351) );
AO22XLTS U697 ( .A0(n1451), .A1(Data_MX[21]), .B0(n1450), .B1(Op_MX[21]),
.Y(n365) );
AO22XLTS U698 ( .A0(n1451), .A1(Data_MX[3]), .B0(n1450), .B1(Op_MX[3]), .Y(
n347) );
AO22XLTS U699 ( .A0(n1478), .A1(Data_MX[15]), .B0(n1452), .B1(Op_MX[15]),
.Y(n359) );
AO22XLTS U700 ( .A0(n1451), .A1(Data_MX[19]), .B0(n1450), .B1(Op_MX[19]),
.Y(n363) );
AO22XLTS U701 ( .A0(n1451), .A1(Data_MX[17]), .B0(n1450), .B1(Op_MX[17]),
.Y(n361) );
AO22XLTS U702 ( .A0(n1451), .A1(Data_MX[8]), .B0(n1449), .B1(n538), .Y(n352)
);
AO22XLTS U703 ( .A0(n1451), .A1(Data_MX[20]), .B0(n1446), .B1(Op_MX[20]),
.Y(n364) );
AO22XLTS U704 ( .A0(n1451), .A1(Data_MX[2]), .B0(n1450), .B1(n394), .Y(n346)
);
AO22XLTS U705 ( .A0(n1454), .A1(Data_MX[22]), .B0(n1452), .B1(Op_MX[22]),
.Y(n366) );
AO22XLTS U706 ( .A0(n1454), .A1(Data_MY[4]), .B0(n1453), .B1(Op_MY[4]), .Y(
n316) );
AO22XLTS U707 ( .A0(n1478), .A1(Data_MY[15]), .B0(n1453), .B1(n543), .Y(n327) );
AO22XLTS U708 ( .A0(n1454), .A1(Data_MY[14]), .B0(n1453), .B1(n391), .Y(n326) );
AO22XLTS U709 ( .A0(n1478), .A1(Data_MY[16]), .B0(n1453), .B1(Op_MY[16]),
.Y(n328) );
AO22XLTS U710 ( .A0(n1454), .A1(Data_MY[7]), .B0(n1453), .B1(Op_MY[7]), .Y(
n319) );
AO22XLTS U711 ( .A0(n1552), .A1(P_Sgf[3]), .B0(n1550), .B1(
Sgf_operation_Result[3]), .Y(n218) );
AO22XLTS U712 ( .A0(n1552), .A1(P_Sgf[4]), .B0(n1550), .B1(
Sgf_operation_Result[4]), .Y(n219) );
AO22XLTS U713 ( .A0(n1552), .A1(P_Sgf[5]), .B0(n1550), .B1(
Sgf_operation_Result[5]), .Y(n220) );
AO22XLTS U714 ( .A0(n1552), .A1(P_Sgf[6]), .B0(n1550), .B1(
Sgf_operation_Result[6]), .Y(n221) );
AO22XLTS U715 ( .A0(n1552), .A1(P_Sgf[7]), .B0(n1549), .B1(
Sgf_operation_Result[7]), .Y(n222) );
AO22XLTS U716 ( .A0(n1451), .A1(Data_MY[10]), .B0(n1453), .B1(Op_MY[10]),
.Y(n322) );
AO22XLTS U717 ( .A0(n1454), .A1(Data_MY[8]), .B0(n1453), .B1(Op_MY[8]), .Y(
n320) );
XNOR2X1TS U718 ( .A(n1009), .B(n1008), .Y(n1010) );
AO22XLTS U719 ( .A0(Data_MY[30]), .A1(n1435), .B0(n1452), .B1(Op_MY[30]),
.Y(n342) );
MX2X1TS U720 ( .A(Exp_module_Data_S[7]), .B(exp_oper_result[7]), .S0(n1436),
.Y(n273) );
AO22XLTS U721 ( .A0(Data_MX[29]), .A1(n1478), .B0(n1447), .B1(Op_MX[29]),
.Y(n373) );
AO22XLTS U722 ( .A0(Data_MX[27]), .A1(n1435), .B0(n1447), .B1(Op_MX[27]),
.Y(n371) );
AO22XLTS U723 ( .A0(n1451), .A1(Data_MX[4]), .B0(n1449), .B1(Op_MX[4]), .Y(
n348) );
AO22XLTS U724 ( .A0(n1451), .A1(Data_MX[6]), .B0(n1449), .B1(Op_MX[6]), .Y(
n350) );
AO22XLTS U725 ( .A0(n1454), .A1(Data_MX[16]), .B0(n1447), .B1(Op_MX[16]),
.Y(n360) );
AO22XLTS U726 ( .A0(n1451), .A1(Data_MX[18]), .B0(n1450), .B1(Op_MX[18]),
.Y(n362) );
AO22XLTS U727 ( .A0(n1448), .A1(Data_MX[10]), .B0(n1449), .B1(Op_MX[10]),
.Y(n354) );
AO22XLTS U728 ( .A0(n1454), .A1(Data_MY[1]), .B0(n1453), .B1(Op_MY[1]), .Y(
n313) );
AO22XLTS U729 ( .A0(n1454), .A1(Data_MY[2]), .B0(n1452), .B1(Op_MY[2]), .Y(
n314) );
AO22XLTS U730 ( .A0(n1478), .A1(Data_MY[17]), .B0(n1450), .B1(Op_MY[17]),
.Y(n329) );
AO22XLTS U731 ( .A0(n1454), .A1(Data_MY[9]), .B0(n1453), .B1(Op_MY[9]), .Y(
n321) );
AO22XLTS U732 ( .A0(n1478), .A1(Data_MY[22]), .B0(n1450), .B1(Op_MY[22]),
.Y(n334) );
AO22XLTS U733 ( .A0(n1478), .A1(Data_MY[20]), .B0(n1450), .B1(Op_MY[20]),
.Y(n332) );
AO22XLTS U734 ( .A0(n1451), .A1(Data_MY[11]), .B0(n1453), .B1(Op_MY[11]),
.Y(n323) );
XOR2X1TS U735 ( .A(n890), .B(n889), .Y(n892) );
OAI32X1TS U736 ( .A0(Op_MX[12]), .A1(n392), .A2(n927), .B0(n645), .B1(n1561),
.Y(n842) );
MX2X1TS U737 ( .A(Exp_module_Data_S[8]), .B(exp_oper_result[8]), .S0(n1436),
.Y(n281) );
MX2X1TS U738 ( .A(n1438), .B(Exp_module_Overflow_flag_A), .S0(n1552), .Y(
n271) );
OAI31X1TS U739 ( .A0(FS_Module_state_reg[1]), .A1(n1309), .A2(n1429), .B0(
n1581), .Y(n214) );
AO22XLTS U740 ( .A0(n1552), .A1(P_Sgf[2]), .B0(n1550), .B1(
Sgf_operation_Result[2]), .Y(n217) );
AO22XLTS U741 ( .A0(n1552), .A1(P_Sgf[8]), .B0(n1548), .B1(
Sgf_operation_Result[8]), .Y(n223) );
AO22XLTS U742 ( .A0(n1552), .A1(P_Sgf[9]), .B0(n1551), .B1(
Sgf_operation_Result[9]), .Y(n224) );
AO22XLTS U743 ( .A0(n1552), .A1(P_Sgf[10]), .B0(n1549), .B1(
Sgf_operation_Result[10]), .Y(n225) );
MX2X1TS U744 ( .A(Exp_module_Data_S[6]), .B(n503), .S0(n1436), .Y(n274) );
AO22XLTS U745 ( .A0(n1477), .A1(zero_flag), .B0(n1476), .B1(n1475), .Y(n311)
);
AO22XLTS U746 ( .A0(Data_MY[24]), .A1(n1435), .B0(n1447), .B1(n500), .Y(n336) );
AO22XLTS U747 ( .A0(Data_MY[25]), .A1(n1435), .B0(n1452), .B1(n501), .Y(n337) );
AO22XLTS U748 ( .A0(Data_MY[28]), .A1(n1435), .B0(n1447), .B1(n499), .Y(n340) );
AO22XLTS U749 ( .A0(Data_MY[29]), .A1(n1435), .B0(n1447), .B1(n498), .Y(n341) );
AO22XLTS U750 ( .A0(n1532), .A1(n1488), .B0(n1526), .B1(n507), .Y(n302) );
AO22XLTS U751 ( .A0(n1532), .A1(n1492), .B0(n1526), .B1(n519), .Y(n300) );
AO22XLTS U752 ( .A0(n1532), .A1(n1496), .B0(n1526), .B1(n520), .Y(n298) );
AO22XLTS U753 ( .A0(n1532), .A1(n1500), .B0(n1526), .B1(n521), .Y(n296) );
AO22XLTS U754 ( .A0(n1451), .A1(Data_MX[5]), .B0(n1449), .B1(n537), .Y(n349)
);
AO22XLTS U755 ( .A0(n1451), .A1(Data_MX[9]), .B0(n1449), .B1(n536), .Y(n353)
);
AO22XLTS U756 ( .A0(Data_MX[28]), .A1(n1478), .B0(n1452), .B1(n504), .Y(n372) );
AO22XLTS U757 ( .A0(Data_MX[30]), .A1(n1435), .B0(n1447), .B1(n508), .Y(n374) );
BUFX3TS U758 ( .A(n1363), .Y(n1414) );
BUFX4TS U759 ( .A(n585), .Y(n1193) );
AOI22X1TS U760 ( .A0(n471), .A1(n1250), .B0(n587), .B1(n1251), .Y(n585) );
AO22X1TS U761 ( .A0(n1249), .A1(n1140), .B0(n577), .B1(n546), .Y(n409) );
BUFX4TS U762 ( .A(n615), .Y(n1255) );
CLKBUFX2TS U763 ( .A(Op_MX[7]), .Y(n1014) );
CLKBUFX2TS U764 ( .A(Op_MX[3]), .Y(n1033) );
CLKBUFX2TS U765 ( .A(Op_MX[17]), .Y(n895) );
NOR2X1TS U766 ( .A(n1562), .B(n917), .Y(n412) );
AOI22X1TS U767 ( .A0(n1454), .A1(Data_MX[1]), .B0(n1450), .B1(n542), .Y(n424) );
AOI22X1TS U768 ( .A0(n1478), .A1(Data_MY[19]), .B0(n1450), .B1(n390), .Y(
n425) );
AOI22X1TS U769 ( .A0(n1478), .A1(Data_MY[21]), .B0(n1450), .B1(n530), .Y(
n426) );
AOI22X1TS U770 ( .A0(n1478), .A1(Data_MY[18]), .B0(n1450), .B1(n529), .Y(
n427) );
AOI22X1TS U771 ( .A0(n1454), .A1(Data_MX[0]), .B0(n1450), .B1(Op_MX[0]), .Y(
n428) );
AOI22X1TS U772 ( .A0(n1448), .A1(Data_MX[13]), .B0(n1449), .B1(n540), .Y(
n429) );
AOI22X1TS U773 ( .A0(n1448), .A1(Data_MX[11]), .B0(n1449), .B1(Op_MX[11]),
.Y(n430) );
AOI22X1TS U774 ( .A0(n1448), .A1(Data_MX[12]), .B0(n1449), .B1(Op_MX[12]),
.Y(n431) );
AOI22X1TS U775 ( .A0(n1454), .A1(Data_MY[0]), .B0(n1447), .B1(Op_MY[0]), .Y(
n432) );
INVX2TS U776 ( .A(n1562), .Y(n457) );
INVX4TS U777 ( .A(n567), .Y(n1479) );
INVX2TS U778 ( .A(n1033), .Y(n458) );
INVX4TS U779 ( .A(n458), .Y(n459) );
INVX2TS U780 ( .A(n607), .Y(n460) );
INVX2TS U781 ( .A(n408), .Y(n462) );
INVX4TS U782 ( .A(n408), .Y(n463) );
INVX2TS U783 ( .A(n409), .Y(n464) );
INVX4TS U784 ( .A(n409), .Y(n465) );
INVX2TS U785 ( .A(n407), .Y(n466) );
INVX4TS U786 ( .A(n407), .Y(n467) );
INVX2TS U787 ( .A(n1198), .Y(n472) );
INVX2TS U788 ( .A(n472), .Y(n473) );
INVX4TS U789 ( .A(n474), .Y(n475) );
INVX2TS U790 ( .A(n413), .Y(n478) );
INVX4TS U791 ( .A(n413), .Y(n479) );
INVX2TS U792 ( .A(n895), .Y(n480) );
INVX4TS U793 ( .A(n480), .Y(n481) );
INVX2TS U794 ( .A(n911), .Y(n482) );
INVX4TS U795 ( .A(n482), .Y(n483) );
INVX4TS U796 ( .A(n481), .Y(n484) );
INVX2TS U797 ( .A(n400), .Y(n485) );
INVX4TS U798 ( .A(n400), .Y(n486) );
INVX2TS U799 ( .A(n485), .Y(n487) );
INVX4TS U800 ( .A(n486), .Y(n488) );
INVX2TS U801 ( .A(n478), .Y(n489) );
INVX4TS U802 ( .A(n479), .Y(n490) );
INVX2TS U803 ( .A(n536), .Y(n492) );
INVX4TS U804 ( .A(n459), .Y(n494) );
INVX4TS U805 ( .A(n470), .Y(n495) );
INVX4TS U806 ( .A(n483), .Y(n496) );
NOR2X1TS U807 ( .A(Op_MY[22]), .B(n851), .Y(mult_x_23_n151) );
NOR2X1TS U808 ( .A(n1058), .B(n1567), .Y(mult_x_55_n168) );
NOR4X1TS U809 ( .A(n527), .B(Op_MY[7]), .C(Op_MY[8]), .D(Op_MY[9]), .Y(n1459) );
NOR4X1TS U810 ( .A(Op_MY[10]), .B(Op_MY[11]), .C(Op_MY[12]), .D(n392), .Y(
n1460) );
NOR4X1TS U811 ( .A(Op_MX[10]), .B(Op_MX[11]), .C(Op_MX[12]), .D(n540), .Y(
n1468) );
NOR4X1TS U812 ( .A(n529), .B(n390), .C(Op_MY[20]), .D(n530), .Y(n1458) );
OAI32X1TS U813 ( .A0(Op_MX[12]), .A1(Op_MY[22]), .A2(mult_x_23_n219), .B0(
n540), .B1(n1561), .Y(n924) );
OAI32X1TS U814 ( .A0(Op_MX[0]), .A1(Op_MY[7]), .A2(mult_x_55_n225), .B0(
n1066), .B1(n1566), .Y(n1072) );
BUFX4TS U815 ( .A(n1449), .Y(n1450) );
BUFX4TS U816 ( .A(n1446), .Y(n1449) );
BUFX4TS U817 ( .A(n566), .Y(n1619) );
INVX2TS U818 ( .A(n1564), .Y(n497) );
NOR4X1TS U819 ( .A(Op_MY[2]), .B(Op_MY[3]), .C(Op_MY[4]), .D(Op_MY[5]), .Y(
n1462) );
ADDHXLTS U820 ( .A(n625), .B(n624), .CO(mult_x_23_n119), .S(mult_x_23_n120)
);
OAI32X1TS U821 ( .A0(Op_MX[12]), .A1(Op_MY[20]), .A2(mult_x_23_n219), .B0(
n621), .B1(n1561), .Y(n625) );
OAI32X1TS U822 ( .A0(Op_MX[0]), .A1(Op_MY[9]), .A2(mult_x_55_n225), .B0(n998), .B1(n1566), .Y(mult_x_55_n228) );
OAI22X2TS U823 ( .A0(beg_FSM), .A1(n1623), .B0(ack_FSM), .B1(n568), .Y(n1442) );
BUFX4TS U824 ( .A(n566), .Y(n1623) );
INVX2TS U825 ( .A(n433), .Y(n498) );
INVX2TS U826 ( .A(n405), .Y(n499) );
NOR4X1TS U827 ( .A(Op_MY[22]), .B(n498), .C(n499), .D(Op_MY[27]), .Y(n1455)
);
INVX2TS U828 ( .A(n404), .Y(n500) );
INVX2TS U829 ( .A(n421), .Y(n501) );
NOR4X1TS U830 ( .A(Op_MY[26]), .B(n501), .C(Op_MY[30]), .D(n500), .Y(n1456)
);
NOR3XLTS U831 ( .A(Op_MX[24]), .B(Op_MX[0]), .C(n542), .Y(n1469) );
NOR3XLTS U832 ( .A(Op_MY[23]), .B(Op_MY[0]), .C(Op_MY[1]), .Y(n1461) );
INVX2TS U833 ( .A(n422), .Y(n502) );
INVX2TS U834 ( .A(n434), .Y(n503) );
INVX2TS U835 ( .A(n406), .Y(n504) );
INVX2TS U836 ( .A(n455), .Y(n505) );
INVX2TS U837 ( .A(n456), .Y(n506) );
INVX2TS U838 ( .A(n454), .Y(n507) );
INVX2TS U839 ( .A(n435), .Y(n508) );
INVX2TS U840 ( .A(n446), .Y(n509) );
INVX2TS U841 ( .A(n447), .Y(n510) );
INVX2TS U842 ( .A(n448), .Y(n511) );
INVX2TS U843 ( .A(n449), .Y(n512) );
INVX2TS U844 ( .A(n450), .Y(n513) );
INVX2TS U845 ( .A(n451), .Y(n514) );
INVX2TS U846 ( .A(n452), .Y(n515) );
INVX2TS U847 ( .A(n453), .Y(n516) );
INVX2TS U848 ( .A(n445), .Y(n517) );
INVX2TS U849 ( .A(n444), .Y(n518) );
INVX2TS U850 ( .A(n437), .Y(n519) );
INVX2TS U851 ( .A(n436), .Y(n520) );
INVX2TS U852 ( .A(n438), .Y(n521) );
INVX2TS U853 ( .A(n439), .Y(n522) );
INVX2TS U854 ( .A(n440), .Y(n523) );
INVX2TS U855 ( .A(n441), .Y(n524) );
INVX2TS U856 ( .A(n442), .Y(n525) );
INVX2TS U857 ( .A(n443), .Y(n526) );
BUFX4TS U858 ( .A(n1412), .Y(n1404) );
INVX3TS U859 ( .A(n1533), .Y(n1555) );
INVX4TS U860 ( .A(mult_x_23_n50), .Y(n529) );
INVX4TS U861 ( .A(n1559), .Y(n530) );
INVX3TS U862 ( .A(n423), .Y(n532) );
INVX2TS U863 ( .A(n402), .Y(n534) );
NOR4X1TS U864 ( .A(Op_MX[6]), .B(Op_MX[7]), .C(n538), .D(n536), .Y(n1467) );
NOR4X1TS U865 ( .A(Op_MX[18]), .B(Op_MX[19]), .C(Op_MX[20]), .D(Op_MX[21]),
.Y(n1466) );
NOR4X1TS U866 ( .A(n394), .B(Op_MX[3]), .C(Op_MX[4]), .D(n537), .Y(n1470) );
NOR4X1TS U867 ( .A(Op_MX[14]), .B(Op_MX[15]), .C(Op_MX[16]), .D(Op_MX[17]),
.Y(n1465) );
INVX2TS U868 ( .A(n551), .Y(n538) );
OAI221X4TS U869 ( .A0(Op_MX[20]), .A1(n911), .B0(n558), .B1(n401), .C0(n929),
.Y(n623) );
OAI32X1TS U870 ( .A0(Op_MX[0]), .A1(Op_MY[2]), .A2(n1065), .B0(n664), .B1(
n1566), .Y(n668) );
OAI32X1TS U871 ( .A0(Op_MX[0]), .A1(Op_MY[1]), .A2(n1065), .B0(n669), .B1(
n1566), .Y(n950) );
OAI32X1TS U872 ( .A0(Op_MX[0]), .A1(Op_MY[4]), .A2(mult_x_55_n225), .B0(n660), .B1(n1566), .Y(n1028) );
INVX2TS U873 ( .A(Op_MX[13]), .Y(n539) );
INVX4TS U874 ( .A(n539), .Y(n540) );
INVX2TS U875 ( .A(Op_MX[1]), .Y(n541) );
INVX4TS U876 ( .A(n541), .Y(n542) );
ADDHX4TS U877 ( .A(n457), .B(Op_MY[0]), .CO(n579), .S(n1161) );
INVX4TS U878 ( .A(n560), .Y(n543) );
CLKINVX3TS U879 ( .A(n607), .Y(n1100) );
INVX2TS U880 ( .A(n1182), .Y(n546) );
INVX4TS U881 ( .A(n473), .Y(n1226) );
AOI22X1TS U882 ( .A0(n616), .A1(n1215), .B0(n477), .B1(n1141), .Y(n615) );
INVX4TS U883 ( .A(n1221), .Y(n1218) );
INVX1TS U884 ( .A(zero_flag), .Y(n1417) );
BUFX4TS U885 ( .A(n1527), .Y(n1526) );
BUFX4TS U886 ( .A(n1630), .Y(n1615) );
BUFX4TS U887 ( .A(n566), .Y(n1620) );
BUFX4TS U888 ( .A(n1548), .Y(n1551) );
ADDFHX2TS U889 ( .A(n1320), .B(Sgf_operation_EVEN1_Q_right[23]), .CI(n1319),
.CO(n1322), .S(n1321) );
AO22X2TS U890 ( .A0(n1272), .A1(P_Sgf[47]), .B0(n1355), .B1(n800), .Y(n380)
);
BUFX4TS U891 ( .A(n1365), .Y(n548) );
OAI32X1TS U892 ( .A0(Op_MX[12]), .A1(Op_MY[17]), .A2(n927), .B0(n926), .B1(
n1561), .Y(mult_x_23_n226) );
NOR2X1TS U893 ( .A(n1567), .B(n1054), .Y(mult_x_55_n196) );
OAI221X4TS U894 ( .A0(Op_MX[16]), .A1(n895), .B0(n562), .B1(n398), .C0(n878),
.Y(n627) );
OR3X1TS U895 ( .A(n534), .B(Sgf_normalized_result[1]), .C(
Sgf_normalized_result[0]), .Y(n1485) );
AOI22X1TS U896 ( .A0(n1448), .A1(Data_MX[14]), .B0(n1449), .B1(Op_MX[14]),
.Y(n552) );
BUFX4TS U897 ( .A(n584), .Y(n1251) );
OAI22X1TS U898 ( .A0(n1193), .A1(n1192), .B0(n588), .B1(n1191), .Y(n1247) );
INVX2TS U899 ( .A(n1239), .Y(n1237) );
OAI21XLTS U900 ( .A0(FSM_selector_B[0]), .A1(n1427), .B0(n1426), .Y(n1428)
);
INVX2TS U901 ( .A(n1242), .Y(n1133) );
NOR2X2TS U902 ( .A(n1572), .B(n1495), .Y(n1497) );
BUFX4TS U903 ( .A(n653), .Y(n1069) );
NAND2BX1TS U904 ( .AN(n618), .B(DP_OP_111J18_123_4462_n63), .Y(n619) );
ADDHXLTS U905 ( .A(n1188), .B(n1187), .CO(n1244), .S(
DP_OP_111J18_123_4462_n142) );
CMPR42X1TS U906 ( .A(mult_x_55_n196), .B(mult_x_55_n232), .C(mult_x_55_n220),
.D(mult_x_55_n208), .ICI(mult_x_55_n136), .S(mult_x_55_n133), .ICO(
mult_x_55_n131), .CO(mult_x_55_n132) );
ADDHXLTS U907 ( .A(n1169), .B(n1168), .CO(DP_OP_111J18_123_4462_n148), .S(
n1166) );
ADDHXLTS U908 ( .A(n922), .B(n921), .CO(mult_x_23_n136), .S(n897) );
NOR3X2TS U909 ( .A(n1569), .B(FS_Module_state_reg[0]), .C(
FS_Module_state_reg[3]), .Y(n1362) );
AND2X4TS U910 ( .A(n1362), .B(n1579), .Y(DP_OP_36J18_124_9196_n33) );
NOR2X1TS U911 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]), .Y(
n571) );
CLKBUFX2TS U912 ( .A(n566), .Y(n1629) );
NAND2X1TS U913 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]), .Y(
n1431) );
NOR3X1TS U914 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[0]), .C(
n1431), .Y(ready) );
INVX2TS U915 ( .A(DP_OP_36J18_124_9196_n33), .Y(n1444) );
NOR2X1TS U916 ( .A(FS_Module_state_reg[3]), .B(n1569), .Y(n1356) );
NAND2X1TS U917 ( .A(FS_Module_state_reg[3]), .B(n1569), .Y(n1280) );
NOR2X2TS U918 ( .A(FS_Module_state_reg[0]), .B(n1280), .Y(n1430) );
INVX2TS U919 ( .A(ready), .Y(n568) );
OAI21XLTS U920 ( .A0(n1569), .A1(n1442), .B0(FS_Module_state_reg[3]), .Y(
n569) );
OAI211X1TS U921 ( .A0(n1417), .A1(n1444), .B0(n1409), .C0(n569), .Y(n570) );
INVX2TS U922 ( .A(n570), .Y(n1557) );
NOR2X2TS U923 ( .A(FS_Module_state_reg[1]), .B(n1609), .Y(n1432) );
BUFX3TS U924 ( .A(n1446), .Y(n1453) );
INVX4TS U925 ( .A(n1453), .Y(n1478) );
BUFX3TS U926 ( .A(n1449), .Y(n1452) );
INVX4TS U927 ( .A(n1452), .Y(n1454) );
INVX2TS U928 ( .A(n1452), .Y(n1448) );
CMPR32X4TS U929 ( .A(Op_MX[3]), .B(Op_MX[15]), .C(n575), .CO(n576), .S(n1249) );
INVX2TS U930 ( .A(n1114), .Y(n1113) );
AOI22X1TS U931 ( .A0(n1114), .A1(n1226), .B0(n1198), .B1(n1113), .Y(n1122)
);
OAI221X4TS U932 ( .A0(n577), .A1(n473), .B0(n1140), .B1(n1226), .C0(n464),
.Y(n1205) );
AOI22X1TS U933 ( .A0(n1161), .A1(n1226), .B0(n1198), .B1(n1142), .Y(n578) );
OAI22X1TS U934 ( .A0(n464), .A1(n1122), .B0(n1205), .B1(n578), .Y(n605) );
ADDHX4TS U935 ( .A(Op_MX[12]), .B(Op_MX[0]), .CO(n580), .S(n1243) );
CMPR32X2TS U936 ( .A(Op_MY[1]), .B(n392), .C(n579), .CO(n586), .S(n1114) );
CMPR32X4TS U937 ( .A(Op_MX[1]), .B(Op_MX[13]), .C(n580), .CO(n583), .S(n1238) );
INVX4TS U938 ( .A(n471), .Y(n584) );
AOI22X1TS U939 ( .A0(n1185), .A1(n584), .B0(n1238), .B1(n1184), .Y(n582) );
INVX4TS U940 ( .A(n1243), .Y(n1240) );
OAI32X1TS U941 ( .A0(n1243), .A1(n1178), .A2(n584), .B0(n582), .B1(n1240),
.Y(n591) );
INVX2TS U942 ( .A(n1121), .Y(n1120) );
AOI22X1TS U943 ( .A0(n1121), .A1(n546), .B0(n1182), .B1(n1120), .Y(n600) );
AOI22X1TS U944 ( .A0(n1114), .A1(n546), .B0(n1249), .B1(n1113), .Y(n594) );
OAI22X1TS U945 ( .A0(n1193), .A1(n600), .B0(n588), .B1(n594), .Y(n590) );
OAI32X1TS U946 ( .A0(n1226), .A1(n1161), .A2(n465), .B0(n1205), .B1(n1226),
.Y(n603) );
CMPR32X2TS U947 ( .A(n591), .B(n590), .C(n589), .CO(n604), .S(n1148) );
AOI22X1TS U948 ( .A0(n1178), .A1(n584), .B0(n1238), .B1(n1177), .Y(n592) );
OAI32X1TS U949 ( .A0(n1243), .A1(n1121), .A2(n1251), .B0(n592), .B1(n1240),
.Y(n599) );
AOI22X1TS U950 ( .A0(n1161), .A1(n546), .B0(n1182), .B1(n1142), .Y(n593) );
OAI22X1TS U951 ( .A0(n1193), .A1(n594), .B0(n588), .B1(n593), .Y(n598) );
OAI32X1TS U952 ( .A0(n546), .A1(n1161), .A2(n1193), .B0(n588), .B1(n546),
.Y(n1164) );
AOI22X1TS U953 ( .A0(n1121), .A1(n584), .B0(n1238), .B1(n1120), .Y(n595) );
OAI32X1TS U954 ( .A0(n1243), .A1(n1114), .A2(n1251), .B0(n595), .B1(n1240),
.Y(n1144) );
AOI21X1TS U955 ( .A0(n1161), .A1(n1243), .B0(n1251), .Y(n1085) );
NAND2X1TS U956 ( .A(n1238), .B(n1240), .Y(n597) );
AOI22X1TS U957 ( .A0(n1114), .A1(n1251), .B0(n471), .B1(n1113), .Y(n596) );
OAI22X1TS U958 ( .A0(n1161), .A1(n597), .B0(n596), .B1(n1240), .Y(n1084) );
ADDHXLTS U959 ( .A(n599), .B(n598), .CO(n1147), .S(n1162) );
AOI22X1TS U960 ( .A0(n1178), .A1(n546), .B0(n1249), .B1(n1177), .Y(n1128) );
OAI22X1TS U961 ( .A0(n1193), .A1(n1128), .B0(n588), .B1(n600), .Y(n1169) );
AOI22X1TS U962 ( .A0(n1236), .A1(n584), .B0(n1238), .B1(n1175), .Y(n602) );
OAI32X1TS U963 ( .A0(n1243), .A1(n1185), .A2(n584), .B0(n602), .B1(n1240),
.Y(n1168) );
CMPR32X2TS U964 ( .A(n605), .B(n604), .C(n603), .CO(n1150), .S(n1165) );
CMPR32X4TS U965 ( .A(n537), .B(Op_MX[17]), .C(n606), .CO(n1109), .S(n1198)
);
XNOR2X1TS U966 ( .A(n679), .B(Op_MX[11]), .Y(n607) );
INVX2TS U967 ( .A(n610), .Y(n803) );
OAI221X4TS U968 ( .A0(n610), .A1(n461), .B0(n803), .B1(n1100), .C0(n466),
.Y(n1102) );
XOR2X1TS U969 ( .A(DP_OP_111J18_123_4462_n63), .B(DP_OP_111J18_123_4462_n70),
.Y(n611) );
CMPR32X4TS U970 ( .A(Op_MX[7]), .B(Op_MX[19]), .C(n614), .CO(n613), .S(n1225) );
INVX2TS U971 ( .A(n616), .Y(n1141) );
AOI22X1TS U972 ( .A0(n475), .A1(n1177), .B0(n1178), .B1(n1218), .Y(n1104) );
OAI221X4TS U973 ( .A0(n616), .A1(n1221), .B0(n1141), .B1(n1218), .C0(n615),
.Y(n1253) );
AOI22X1TS U974 ( .A0(n475), .A1(n1120), .B0(n1121), .B1(n1218), .Y(n1106) );
BUFX4TS U975 ( .A(mult_x_23_n219), .Y(n927) );
AOI22X1TS U976 ( .A0(n540), .A1(n1559), .B0(n530), .B1(n927), .Y(n621) );
AOI22X1TS U977 ( .A0(n485), .A1(n558), .B0(Op_MX[20]), .B1(n487), .Y(n622)
);
OAI32X1TS U978 ( .A0(n482), .A1(Op_MY[12]), .A2(n929), .B0(n623), .B1(n496),
.Y(n624) );
AOI22X1TS U979 ( .A0(n478), .A1(n562), .B0(Op_MX[16]), .B1(n489), .Y(n626)
);
AOI22X1TS U980 ( .A0(n895), .A1(n410), .B0(n392), .B1(n398), .Y(n876) );
AOI22X1TS U981 ( .A0(Op_MY[12]), .A1(n480), .B0(n481), .B1(n1562), .Y(n628)
);
OAI22X1TS U982 ( .A0(n878), .A1(n876), .B0(n627), .B1(n628), .Y(n635) );
AOI22X1TS U983 ( .A0(n479), .A1(n560), .B0(n543), .B1(n490), .Y(n882) );
AOI22X1TS U984 ( .A0(n479), .A1(n553), .B0(n391), .B1(n489), .Y(n632) );
OAI22X1TS U985 ( .A0(n933), .A1(n882), .B0(n630), .B1(n632), .Y(n634) );
AOI22X1TS U986 ( .A0(n540), .A1(n557), .B0(Op_MY[16]), .B1(n927), .Y(n631)
);
AOI22X1TS U987 ( .A0(n478), .A1(n410), .B0(n392), .B1(n489), .Y(n642) );
OAI22X1TS U988 ( .A0(n933), .A1(n632), .B0(n630), .B1(n642), .Y(n637) );
CMPR32X2TS U989 ( .A(n635), .B(n634), .C(n633), .CO(n839), .S(n898) );
AOI22X1TS U990 ( .A0(n540), .A1(n563), .B0(Op_MY[17]), .B1(mult_x_23_n219),
.Y(n636) );
OAI32X1TS U991 ( .A0(Op_MX[12]), .A1(Op_MY[16]), .A2(n927), .B0(n636), .B1(
n1561), .Y(n922) );
OAI32X1TS U992 ( .A0(n484), .A1(Op_MY[12]), .A2(n878), .B0(n627), .B1(n484),
.Y(n921) );
CMPR32X2TS U993 ( .A(n639), .B(n638), .C(n637), .CO(n633), .S(n907) );
AOI22X1TS U994 ( .A0(n540), .A1(n560), .B0(n543), .B1(n927), .Y(n640) );
AOI22X1TS U995 ( .A0(n457), .A1(n489), .B0(n479), .B1(n1562), .Y(n641) );
OAI22X1TS U996 ( .A0(n933), .A1(n642), .B0(n630), .B1(n641), .Y(n643) );
ADDHXLTS U997 ( .A(n644), .B(n643), .CO(n906), .S(n910) );
OAI32X1TS U998 ( .A0(n490), .A1(Op_MY[12]), .A2(n933), .B0(n630), .B1(n490),
.Y(n909) );
AOI22X1TS U999 ( .A0(n540), .A1(n553), .B0(n391), .B1(n927), .Y(n645) );
AOI21X1TS U1000 ( .A0(Op_MY[12]), .A1(Op_MX[12]), .B0(n927), .Y(n904) );
NAND2X1TS U1001 ( .A(n540), .B(n1561), .Y(n647) );
AOI22X1TS U1002 ( .A0(n540), .A1(n410), .B0(n392), .B1(n927), .Y(n646) );
OAI22X1TS U1003 ( .A0(Op_MY[12]), .A1(n647), .B0(n646), .B1(n1561), .Y(n903)
);
AOI22X1TS U1004 ( .A0(n1033), .A1(n549), .B0(Op_MX[4]), .B1(n397), .Y(n650)
);
AOI22X1TS U1005 ( .A0(n469), .A1(n561), .B0(Op_MY[1]), .B1(n468), .Y(n992)
);
AOI22X1TS U1006 ( .A0(Op_MY[0]), .A1(n468), .B0(n537), .B1(n1567), .Y(n652)
);
OAI22X1TS U1007 ( .A0(n1078), .A1(n992), .B0(n651), .B1(n652), .Y(n659) );
BUFX4TS U1008 ( .A(mult_x_55_n225), .Y(n1065) );
AOI22X1TS U1009 ( .A0(n542), .A1(n556), .B0(n394), .B1(n1065), .Y(n653) );
AOI22X1TS U1010 ( .A0(n459), .A1(n1565), .B0(Op_MY[3]), .B1(n494), .Y(n996)
);
AOI22X1TS U1011 ( .A0(n459), .A1(n414), .B0(Op_MY[2]), .B1(n458), .Y(n656)
);
OAI22X1TS U1012 ( .A0(n1069), .A1(n996), .B0(n654), .B1(n656), .Y(n658) );
AOI22X1TS U1013 ( .A0(n542), .A1(n559), .B0(Op_MY[4]), .B1(n1065), .Y(n655)
);
OAI32X1TS U1014 ( .A0(Op_MX[0]), .A1(Op_MY[3]), .A2(mult_x_55_n225), .B0(
n655), .B1(n1566), .Y(n663) );
AOI22X1TS U1015 ( .A0(n1033), .A1(n561), .B0(Op_MY[1]), .B1(n397), .Y(n666)
);
OAI22X1TS U1016 ( .A0(n1069), .A1(n656), .B0(n654), .B1(n666), .Y(n661) );
CMPR32X2TS U1017 ( .A(n659), .B(n658), .C(n657), .CO(n947), .S(n1026) );
AOI22X1TS U1018 ( .A0(n542), .A1(n1564), .B0(Op_MY[5]), .B1(n1065), .Y(n660)
);
OAI32X1TS U1019 ( .A0(n411), .A1(Op_MY[0]), .A2(n1078), .B0(n651), .B1(n411),
.Y(n1027) );
CMPR32X2TS U1020 ( .A(n663), .B(n662), .C(n661), .CO(n657), .S(n1038) );
AOI22X1TS U1021 ( .A0(n542), .A1(n1565), .B0(Op_MY[3]), .B1(n1065), .Y(n664)
);
AOI22X1TS U1022 ( .A0(Op_MY[0]), .A1(n397), .B0(n459), .B1(n1567), .Y(n665)
);
OAI22X1TS U1023 ( .A0(n1069), .A1(n666), .B0(n654), .B1(n665), .Y(n667) );
ADDHXLTS U1024 ( .A(n668), .B(n667), .CO(n1037), .S(n1047) );
OAI32X1TS U1025 ( .A0(n494), .A1(Op_MY[0]), .A2(n1069), .B0(n654), .B1(n494),
.Y(n1046) );
AOI22X1TS U1026 ( .A0(n542), .A1(n414), .B0(Op_MY[2]), .B1(n1065), .Y(n669)
);
AOI21X1TS U1027 ( .A0(Op_MY[0]), .A1(Op_MX[0]), .B0(n1065), .Y(n1035) );
NAND2X1TS U1028 ( .A(n542), .B(n1566), .Y(n671) );
AOI22X1TS U1029 ( .A0(n542), .A1(n561), .B0(Op_MY[1]), .B1(n1065), .Y(n670)
);
OAI22X1TS U1030 ( .A0(Op_MY[0]), .A1(n671), .B0(n670), .B1(n1566), .Y(n1034)
);
AOI22X1TS U1031 ( .A0(n1242), .A1(n547), .B0(n1249), .B1(n1133), .Y(n1125)
);
AOI22X1TS U1032 ( .A0(n1199), .A1(n547), .B0(n1249), .B1(n1197), .Y(n1127)
);
NAND2X4TS U1033 ( .A(n679), .B(Op_MX[11]), .Y(n1088) );
CLKXOR2X4TS U1034 ( .A(Op_MY[11]), .B(n682), .Y(n1220) );
INVX4TS U1035 ( .A(n1088), .Y(n1137) );
OAI22X1TS U1036 ( .A0(n1088), .A1(n1239), .B0(n1219), .B1(n1137), .Y(n802)
);
NOR2X4TS U1037 ( .A(Op_MY[11]), .B(n682), .Y(n1139) );
AOI22X1TS U1038 ( .A0(n460), .A1(n1138), .B0(n1139), .B1(n461), .Y(n1089) );
OAI22X1TS U1039 ( .A0(n460), .A1(n467), .B0(n1089), .B1(n1102), .Y(n801) );
NAND2BX2TS U1040 ( .AN(n1362), .B(n686), .Y(n1548) );
BUFX3TS U1041 ( .A(n1548), .Y(n1355) );
INVX2TS U1042 ( .A(n1355), .Y(n1272) );
CMPR32X2TS U1043 ( .A(DP_OP_110J18_122_9009_n96), .B(
Sgf_operation_EVEN1_Q_middle[23]), .C(DP_OP_110J18_122_9009_n73), .CO(
n728), .S(n731) );
CMPR32X2TS U1044 ( .A(DP_OP_110J18_122_9009_n97), .B(
Sgf_operation_EVEN1_Q_middle[22]), .C(DP_OP_110J18_122_9009_n74), .CO(
n730), .S(n734) );
INVX2TS U1045 ( .A(Sgf_operation_EVEN1_Q_right[21]), .Y(n687) );
CMPR32X2TS U1046 ( .A(DP_OP_110J18_122_9009_n98), .B(
Sgf_operation_EVEN1_Q_middle[21]), .C(n687), .CO(n733), .S(n737) );
INVX2TS U1047 ( .A(Sgf_operation_EVEN1_Q_left[20]), .Y(n689) );
INVX2TS U1048 ( .A(Sgf_operation_EVEN1_Q_right[20]), .Y(n688) );
CMPR32X2TS U1049 ( .A(n689), .B(Sgf_operation_EVEN1_Q_middle[20]), .C(n688),
.CO(n736), .S(n740) );
INVX2TS U1050 ( .A(Sgf_operation_EVEN1_Q_left[19]), .Y(n691) );
INVX2TS U1051 ( .A(Sgf_operation_EVEN1_Q_right[19]), .Y(n690) );
CMPR32X2TS U1052 ( .A(n691), .B(Sgf_operation_EVEN1_Q_middle[19]), .C(n690),
.CO(n739), .S(n743) );
INVX2TS U1053 ( .A(Sgf_operation_EVEN1_Q_left[18]), .Y(n693) );
INVX2TS U1054 ( .A(Sgf_operation_EVEN1_Q_right[18]), .Y(n692) );
CMPR32X2TS U1055 ( .A(n693), .B(Sgf_operation_EVEN1_Q_middle[18]), .C(n692),
.CO(n742), .S(n746) );
INVX2TS U1056 ( .A(Sgf_operation_EVEN1_Q_left[17]), .Y(n695) );
INVX2TS U1057 ( .A(Sgf_operation_EVEN1_Q_right[17]), .Y(n694) );
CMPR32X2TS U1058 ( .A(n695), .B(Sgf_operation_EVEN1_Q_middle[17]), .C(n694),
.CO(n745), .S(n749) );
INVX2TS U1059 ( .A(Sgf_operation_EVEN1_Q_left[16]), .Y(n697) );
INVX2TS U1060 ( .A(Sgf_operation_EVEN1_Q_right[16]), .Y(n696) );
CMPR32X2TS U1061 ( .A(n697), .B(Sgf_operation_EVEN1_Q_middle[16]), .C(n696),
.CO(n748), .S(n752) );
INVX2TS U1062 ( .A(Sgf_operation_EVEN1_Q_left[15]), .Y(n699) );
INVX2TS U1063 ( .A(Sgf_operation_EVEN1_Q_right[15]), .Y(n698) );
CMPR32X2TS U1064 ( .A(n699), .B(Sgf_operation_EVEN1_Q_middle[15]), .C(n698),
.CO(n751), .S(n755) );
INVX2TS U1065 ( .A(Sgf_operation_EVEN1_Q_left[14]), .Y(n701) );
INVX2TS U1066 ( .A(Sgf_operation_EVEN1_Q_right[14]), .Y(n700) );
CMPR32X2TS U1067 ( .A(n701), .B(Sgf_operation_EVEN1_Q_middle[14]), .C(n700),
.CO(n754), .S(n758) );
INVX2TS U1068 ( .A(Sgf_operation_EVEN1_Q_left[13]), .Y(n703) );
INVX2TS U1069 ( .A(Sgf_operation_EVEN1_Q_right[13]), .Y(n702) );
CMPR32X2TS U1070 ( .A(n703), .B(Sgf_operation_EVEN1_Q_middle[13]), .C(n702),
.CO(n757), .S(n761) );
INVX2TS U1071 ( .A(Sgf_operation_EVEN1_Q_left[12]), .Y(n705) );
INVX2TS U1072 ( .A(Sgf_operation_EVEN1_Q_right[12]), .Y(n704) );
CMPR32X2TS U1073 ( .A(n705), .B(Sgf_operation_EVEN1_Q_middle[12]), .C(n704),
.CO(n760), .S(n764) );
INVX2TS U1074 ( .A(Sgf_operation_EVEN1_Q_left[11]), .Y(n707) );
INVX2TS U1075 ( .A(Sgf_operation_Result[11]), .Y(n706) );
CMPR32X2TS U1076 ( .A(n707), .B(Sgf_operation_EVEN1_Q_middle[11]), .C(n706),
.CO(n763), .S(n767) );
INVX2TS U1077 ( .A(Sgf_operation_EVEN1_Q_left[10]), .Y(n709) );
INVX2TS U1078 ( .A(Sgf_operation_Result[10]), .Y(n708) );
CMPR32X2TS U1079 ( .A(n709), .B(Sgf_operation_EVEN1_Q_middle[10]), .C(n708),
.CO(n766), .S(n770) );
INVX2TS U1080 ( .A(Sgf_operation_EVEN1_Q_left[9]), .Y(n711) );
INVX2TS U1081 ( .A(Sgf_operation_Result[9]), .Y(n710) );
CMPR32X2TS U1082 ( .A(n711), .B(Sgf_operation_EVEN1_Q_middle[9]), .C(n710),
.CO(n769), .S(n773) );
INVX2TS U1083 ( .A(Sgf_operation_EVEN1_Q_left[8]), .Y(n713) );
INVX2TS U1084 ( .A(Sgf_operation_Result[8]), .Y(n712) );
CMPR32X2TS U1085 ( .A(n713), .B(Sgf_operation_EVEN1_Q_middle[8]), .C(n712),
.CO(n772), .S(n776) );
INVX2TS U1086 ( .A(Sgf_operation_EVEN1_Q_left[7]), .Y(n715) );
INVX2TS U1087 ( .A(Sgf_operation_Result[7]), .Y(n714) );
CMPR32X2TS U1088 ( .A(n715), .B(Sgf_operation_EVEN1_Q_middle[7]), .C(n714),
.CO(n775), .S(n779) );
INVX2TS U1089 ( .A(Sgf_operation_EVEN1_Q_left[6]), .Y(n717) );
INVX2TS U1090 ( .A(Sgf_operation_Result[6]), .Y(n716) );
CMPR32X2TS U1091 ( .A(n717), .B(Sgf_operation_EVEN1_Q_middle[6]), .C(n716),
.CO(n778), .S(n782) );
INVX2TS U1092 ( .A(Sgf_operation_EVEN1_Q_left[5]), .Y(n719) );
INVX2TS U1093 ( .A(Sgf_operation_Result[5]), .Y(n718) );
CMPR32X2TS U1094 ( .A(n719), .B(Sgf_operation_EVEN1_Q_middle[5]), .C(n718),
.CO(n781), .S(n785) );
INVX2TS U1095 ( .A(Sgf_operation_EVEN1_Q_left[4]), .Y(n721) );
INVX2TS U1096 ( .A(Sgf_operation_Result[4]), .Y(n720) );
CMPR32X2TS U1097 ( .A(n721), .B(Sgf_operation_EVEN1_Q_middle[4]), .C(n720),
.CO(n784), .S(n788) );
INVX2TS U1098 ( .A(Sgf_operation_EVEN1_Q_left[3]), .Y(n723) );
INVX2TS U1099 ( .A(Sgf_operation_Result[3]), .Y(n722) );
CMPR32X2TS U1100 ( .A(n723), .B(Sgf_operation_EVEN1_Q_middle[3]), .C(n722),
.CO(n787), .S(n791) );
INVX2TS U1101 ( .A(Sgf_operation_EVEN1_Q_left[2]), .Y(n725) );
INVX2TS U1102 ( .A(Sgf_operation_Result[2]), .Y(n724) );
CMPR32X2TS U1103 ( .A(n725), .B(Sgf_operation_EVEN1_Q_middle[2]), .C(n724),
.CO(n790), .S(n794) );
INVX2TS U1104 ( .A(Sgf_operation_Result[1]), .Y(n796) );
XOR2X1TS U1105 ( .A(Sgf_operation_EVEN1_Q_middle[1]), .B(
Sgf_operation_EVEN1_Q_left[1]), .Y(n795) );
XNOR2X1TS U1106 ( .A(Sgf_operation_EVEN1_Q_middle[25]), .B(n726), .Y(n1274)
);
CMPR32X2TS U1107 ( .A(n731), .B(n730), .C(n729), .CO(n727), .S(n1350) );
CMPR32X2TS U1108 ( .A(n737), .B(n736), .C(n735), .CO(n732), .S(n1344) );
CMPR32X2TS U1109 ( .A(n740), .B(n739), .C(n738), .CO(n735), .S(n1341) );
CMPR32X2TS U1110 ( .A(n746), .B(n745), .C(n744), .CO(n741), .S(n1335) );
CMPR32X2TS U1111 ( .A(n752), .B(n751), .C(n750), .CO(n747), .S(n1540) );
CMPR32X2TS U1112 ( .A(n758), .B(n757), .C(n756), .CO(n753), .S(n1329) );
CMPR32X2TS U1113 ( .A(n764), .B(n763), .C(n762), .CO(n759), .S(n1323) );
CMPR32X2TS U1114 ( .A(n770), .B(n769), .C(n768), .CO(n765), .S(n1317) );
CMPR32X2TS U1115 ( .A(n773), .B(n772), .C(n771), .CO(n768), .S(n1314) );
CMPR32X2TS U1116 ( .A(n779), .B(n778), .C(n777), .CO(n774), .S(n1292) );
CMPR32X2TS U1117 ( .A(n782), .B(n781), .C(n780), .CO(n777), .S(n1286) );
CMPR32X2TS U1118 ( .A(n785), .B(n784), .C(n783), .CO(n780), .S(n1298) );
CMPR32X2TS U1119 ( .A(n788), .B(n787), .C(n786), .CO(n783), .S(n1289) );
CMPR32X2TS U1120 ( .A(n794), .B(n793), .C(n792), .CO(n789), .S(n1283) );
CMPR32X2TS U1121 ( .A(DP_OP_110J18_122_9009_n119), .B(
Sgf_operation_EVEN1_Q_middle[0]), .C(n798), .CO(n797), .S(n1546) );
CMPR32X2TS U1122 ( .A(n802), .B(n801), .C(DP_OP_111J18_123_4462_n35), .CO(
n808), .S(n805) );
AOI22X1TS U1123 ( .A0(n1137), .A1(n1220), .B0(n1139), .B1(n1088), .Y(n811)
);
INVX2TS U1124 ( .A(n802), .Y(n810) );
OAI21X1TS U1125 ( .A0(n474), .A1(n803), .B0(n461), .Y(n809) );
CMPR32X2TS U1126 ( .A(n811), .B(n810), .C(n809), .CO(n813), .S(n807) );
OAI31X1TS U1127 ( .A0(n1139), .A1(n813), .A2(n1088), .B0(n812), .Y(n814) );
ADDFHX4TS U1128 ( .A(DP_OP_111J18_123_4462_n57), .B(
DP_OP_111J18_123_4462_n62), .CI(n820), .CO(n683), .S(
Sgf_operation_EVEN1_middle_N18) );
AOI22X1TS U1129 ( .A0(n540), .A1(n1560), .B0(n390), .B1(n927), .Y(n828) );
AOI22X1TS U1130 ( .A0(n895), .A1(n555), .B0(Op_MX[18]), .B1(n398), .Y(n829)
);
OAI32X1TS U1131 ( .A0(n488), .A1(Op_MY[12]), .A2(n917), .B0(n830), .B1(n488),
.Y(n831) );
CMPR32X2TS U1132 ( .A(mult_x_23_n40), .B(mult_x_23_n36), .C(n834), .CO(n885),
.S(Sgf_operation_EVEN1_left_N20) );
CMPR32X2TS U1133 ( .A(mult_x_23_n53), .B(mult_x_23_n58), .C(n835), .CO(n824),
.S(Sgf_operation_EVEN1_left_N17) );
CMPR32X2TS U1134 ( .A(mult_x_23_n85), .B(mult_x_23_n93), .C(n836), .CO(n825),
.S(Sgf_operation_EVEN1_left_N13) );
CMPR32X2TS U1135 ( .A(mult_x_23_n116), .B(mult_x_23_n122), .C(n837), .CO(
n822), .S(Sgf_operation_EVEN1_left_N9) );
CMPR32X2TS U1136 ( .A(mult_x_23_n133), .B(n839), .C(n838), .CO(n894), .S(
Sgf_operation_EVEN1_left_N6) );
CMPR32X2TS U1137 ( .A(n842), .B(n841), .C(n840), .CO(n908), .S(
Sgf_operation_EVEN1_left_N2) );
AOI22X1TS U1138 ( .A0(n483), .A1(n564), .B0(Op_MY[22]), .B1(n496), .Y(n900)
);
OAI22X1TS U1139 ( .A0(n483), .A1(n929), .B0(n900), .B1(n623), .Y(n843) );
CMPR32X2TS U1140 ( .A(n390), .B(n529), .C(n843), .CO(mult_x_23_n42), .S(
mult_x_23_n43) );
AOI22X1TS U1141 ( .A0(n486), .A1(n1559), .B0(n530), .B1(n488), .Y(n860) );
AOI22X1TS U1142 ( .A0(n486), .A1(n417), .B0(Op_MY[20]), .B1(n488), .Y(n845)
);
OAI22X1TS U1143 ( .A0(n917), .A1(n860), .B0(n830), .B1(n845), .Y(n844) );
CMPR32X2TS U1144 ( .A(n543), .B(n392), .C(n844), .CO(mult_x_23_n71), .S(
mult_x_23_n72) );
AOI22X1TS U1145 ( .A0(n486), .A1(n1560), .B0(n390), .B1(n488), .Y(n862) );
OAI22X1TS U1146 ( .A0(n917), .A1(n845), .B0(n830), .B1(n862), .Y(n846) );
CMPR32X2TS U1147 ( .A(n410), .B(n391), .C(n846), .CO(mult_x_23_n79), .S(
mult_x_23_n80) );
AOI22X1TS U1148 ( .A0(n483), .A1(n563), .B0(Op_MY[17]), .B1(n496), .Y(n855)
);
AOI22X1TS U1149 ( .A0(n483), .A1(n557), .B0(Op_MY[16]), .B1(n496), .Y(n857)
);
OAI22X1TS U1150 ( .A0(n929), .A1(n855), .B0(n623), .B1(n857), .Y(n848) );
AOI22X1TS U1151 ( .A0(n481), .A1(n1559), .B0(n530), .B1(n484), .Y(n868) );
AOI22X1TS U1152 ( .A0(n481), .A1(n417), .B0(Op_MY[20]), .B1(n484), .Y(n870)
);
OAI22X1TS U1153 ( .A0(n878), .A1(n868), .B0(n627), .B1(n870), .Y(n847) );
CMPR32X2TS U1154 ( .A(n848), .B(n410), .C(n847), .CO(mult_x_23_n89), .S(
mult_x_23_n90) );
AOI22X1TS U1155 ( .A0(n479), .A1(n564), .B0(Op_MY[22]), .B1(n490), .Y(n879)
);
AOI22X1TS U1156 ( .A0(n479), .A1(n1559), .B0(n530), .B1(n490), .Y(n880) );
OAI22X1TS U1157 ( .A0(n933), .A1(n879), .B0(n630), .B1(n880), .Y(n849) );
CMPR32X2TS U1158 ( .A(n850), .B(Op_MY[12]), .C(n849), .CO(mult_x_23_n98),
.S(mult_x_23_n99) );
AOI22X1TS U1159 ( .A0(n911), .A1(Op_MX[22]), .B0(n419), .B1(n401), .Y(n888)
);
OAI22X1TS U1160 ( .A0(n530), .A1(n851), .B0(Op_MY[22]), .B1(n852), .Y(
mult_x_23_n152) );
OAI22X1TS U1161 ( .A0(Op_MY[20]), .A1(n851), .B0(n530), .B1(n852), .Y(
mult_x_23_n153) );
OAI22X1TS U1162 ( .A0(n390), .A1(n851), .B0(Op_MY[20]), .B1(n852), .Y(
mult_x_23_n154) );
OAI22X1TS U1163 ( .A0(n529), .A1(n851), .B0(n390), .B1(n852), .Y(
mult_x_23_n155) );
OAI22X1TS U1164 ( .A0(Op_MY[17]), .A1(n851), .B0(n529), .B1(n852), .Y(
mult_x_23_n156) );
OAI22X1TS U1165 ( .A0(Op_MY[16]), .A1(n851), .B0(Op_MY[17]), .B1(n852), .Y(
mult_x_23_n157) );
OAI22X1TS U1166 ( .A0(n543), .A1(n851), .B0(Op_MY[16]), .B1(n852), .Y(
mult_x_23_n158) );
OAI22X1TS U1167 ( .A0(n391), .A1(n851), .B0(n543), .B1(n852), .Y(
mult_x_23_n159) );
OAI22X1TS U1168 ( .A0(n392), .A1(n851), .B0(n391), .B1(n852), .Y(
mult_x_23_n160) );
OAI22X1TS U1169 ( .A0(n392), .A1(n852), .B0(Op_MY[12]), .B1(n851), .Y(
mult_x_23_n161) );
AOI22X1TS U1170 ( .A0(n483), .A1(n929), .B0(n623), .B1(n496), .Y(
mult_x_23_n164) );
AOI22X1TS U1171 ( .A0(n483), .A1(n1559), .B0(n530), .B1(n496), .Y(n899) );
AOI22X1TS U1172 ( .A0(n483), .A1(n417), .B0(Op_MY[20]), .B1(n496), .Y(n853)
);
OAI22X1TS U1173 ( .A0(n929), .A1(n899), .B0(n623), .B1(n853), .Y(
mult_x_23_n167) );
AOI22X1TS U1174 ( .A0(n483), .A1(n1560), .B0(n390), .B1(n496), .Y(n854) );
OAI22X1TS U1175 ( .A0(n929), .A1(n853), .B0(n623), .B1(n854), .Y(
mult_x_23_n168) );
AOI22X1TS U1176 ( .A0(n483), .A1(mult_x_23_n50), .B0(n529), .B1(n496), .Y(
n856) );
OAI22X1TS U1177 ( .A0(n929), .A1(n854), .B0(n623), .B1(n856), .Y(
mult_x_23_n169) );
OAI22X1TS U1178 ( .A0(n929), .A1(n856), .B0(n623), .B1(n855), .Y(
mult_x_23_n170) );
AOI22X1TS U1179 ( .A0(n483), .A1(n560), .B0(n543), .B1(n496), .Y(n858) );
OAI22X1TS U1180 ( .A0(n929), .A1(n857), .B0(n623), .B1(n858), .Y(
mult_x_23_n172) );
AOI22X1TS U1181 ( .A0(n483), .A1(n553), .B0(n391), .B1(n496), .Y(n859) );
OAI22X1TS U1182 ( .A0(n929), .A1(n858), .B0(n623), .B1(n859), .Y(
mult_x_23_n173) );
AOI22X1TS U1183 ( .A0(n911), .A1(n410), .B0(n392), .B1(n401), .Y(n913) );
OAI22X1TS U1184 ( .A0(n929), .A1(n859), .B0(n623), .B1(n913), .Y(
mult_x_23_n174) );
AOI22X1TS U1185 ( .A0(n486), .A1(n564), .B0(Op_MY[22]), .B1(n488), .Y(n861)
);
OAI22X1TS U1186 ( .A0(n486), .A1(n917), .B0(n861), .B1(n830), .Y(
mult_x_23_n179) );
OAI22X1TS U1187 ( .A0(n917), .A1(n861), .B0(n830), .B1(n860), .Y(
mult_x_23_n180) );
AOI22X1TS U1188 ( .A0(n486), .A1(mult_x_23_n50), .B0(n529), .B1(n488), .Y(
n863) );
OAI22X1TS U1189 ( .A0(n917), .A1(n862), .B0(n830), .B1(n863), .Y(
mult_x_23_n183) );
AOI22X1TS U1190 ( .A0(n486), .A1(n563), .B0(Op_MY[17]), .B1(n488), .Y(n864)
);
OAI22X1TS U1191 ( .A0(n917), .A1(n863), .B0(n830), .B1(n864), .Y(
mult_x_23_n184) );
AOI22X1TS U1192 ( .A0(n486), .A1(n557), .B0(Op_MY[16]), .B1(n488), .Y(n865)
);
OAI22X1TS U1193 ( .A0(n917), .A1(n864), .B0(n830), .B1(n865), .Y(
mult_x_23_n185) );
AOI22X1TS U1194 ( .A0(n486), .A1(n560), .B0(n543), .B1(n488), .Y(n916) );
OAI22X1TS U1195 ( .A0(n917), .A1(n865), .B0(n830), .B1(n916), .Y(
mult_x_23_n186) );
AOI22X1TS U1196 ( .A0(n486), .A1(n553), .B0(n391), .B1(n488), .Y(n915) );
AOI22X1TS U1197 ( .A0(n486), .A1(n410), .B0(n392), .B1(n487), .Y(n867) );
OAI22X1TS U1198 ( .A0(n917), .A1(n915), .B0(n830), .B1(n867), .Y(
mult_x_23_n188) );
AOI22X1TS U1199 ( .A0(Op_MY[12]), .A1(n487), .B0(n486), .B1(n1562), .Y(n866)
);
OAI22X1TS U1200 ( .A0(n917), .A1(n867), .B0(n830), .B1(n866), .Y(
mult_x_23_n189) );
AOI22X1TS U1201 ( .A0(n481), .A1(n878), .B0(n627), .B1(n484), .Y(
mult_x_23_n192) );
AOI22X1TS U1202 ( .A0(n481), .A1(n564), .B0(Op_MY[22]), .B1(n484), .Y(n869)
);
OAI22X1TS U1203 ( .A0(n481), .A1(n878), .B0(n869), .B1(n627), .Y(
mult_x_23_n193) );
OAI22X1TS U1204 ( .A0(n878), .A1(n869), .B0(n627), .B1(n868), .Y(
mult_x_23_n194) );
AOI22X1TS U1205 ( .A0(n481), .A1(n1560), .B0(n390), .B1(n484), .Y(n871) );
OAI22X1TS U1206 ( .A0(n878), .A1(n870), .B0(n627), .B1(n871), .Y(
mult_x_23_n196) );
AOI22X1TS U1207 ( .A0(n481), .A1(mult_x_23_n50), .B0(n529), .B1(n484), .Y(
n872) );
OAI22X1TS U1208 ( .A0(n878), .A1(n871), .B0(n627), .B1(n872), .Y(
mult_x_23_n197) );
AOI22X1TS U1209 ( .A0(n481), .A1(n563), .B0(Op_MY[17]), .B1(n484), .Y(n873)
);
OAI22X1TS U1210 ( .A0(n878), .A1(n872), .B0(n627), .B1(n873), .Y(
mult_x_23_n198) );
AOI22X1TS U1211 ( .A0(n481), .A1(n557), .B0(Op_MY[16]), .B1(n484), .Y(n874)
);
OAI22X1TS U1212 ( .A0(n878), .A1(n873), .B0(n627), .B1(n874), .Y(
mult_x_23_n199) );
AOI22X1TS U1213 ( .A0(n481), .A1(n560), .B0(n543), .B1(n484), .Y(n875) );
OAI22X1TS U1214 ( .A0(n878), .A1(n874), .B0(n627), .B1(n875), .Y(
mult_x_23_n200) );
AOI22X1TS U1215 ( .A0(n481), .A1(n553), .B0(n391), .B1(n398), .Y(n877) );
OAI22X1TS U1216 ( .A0(n878), .A1(n875), .B0(n627), .B1(n877), .Y(
mult_x_23_n201) );
OAI22X1TS U1217 ( .A0(n878), .A1(n877), .B0(n627), .B1(n876), .Y(
mult_x_23_n202) );
AOI22X1TS U1218 ( .A0(n479), .A1(n933), .B0(n630), .B1(n490), .Y(
mult_x_23_n206) );
OAI22X1TS U1219 ( .A0(n479), .A1(n933), .B0(n879), .B1(n630), .Y(
mult_x_23_n207) );
AOI22X1TS U1220 ( .A0(n479), .A1(n417), .B0(Op_MY[20]), .B1(n490), .Y(n881)
);
OAI22X1TS U1221 ( .A0(n933), .A1(n880), .B0(n630), .B1(n881), .Y(
mult_x_23_n209) );
AOI22X1TS U1222 ( .A0(n479), .A1(n1560), .B0(n390), .B1(n490), .Y(n914) );
OAI22X1TS U1223 ( .A0(n933), .A1(n881), .B0(n630), .B1(n914), .Y(
mult_x_23_n210) );
AOI22X1TS U1224 ( .A0(n479), .A1(n563), .B0(Op_MY[17]), .B1(n490), .Y(n930)
);
AOI22X1TS U1225 ( .A0(n479), .A1(n557), .B0(Op_MY[16]), .B1(n490), .Y(n883)
);
OAI22X1TS U1226 ( .A0(n933), .A1(n930), .B0(n630), .B1(n883), .Y(
mult_x_23_n213) );
OAI22X1TS U1227 ( .A0(n933), .A1(n883), .B0(n630), .B1(n882), .Y(
mult_x_23_n214) );
AOI22X1TS U1228 ( .A0(n540), .A1(n564), .B0(Op_MY[22]), .B1(n927), .Y(n884)
);
OAI32X1TS U1229 ( .A0(Op_MX[12]), .A1(n530), .A2(mult_x_23_n219), .B0(n884),
.B1(n1561), .Y(mult_x_23_n222) );
CMPR32X2TS U1230 ( .A(mult_x_23_n35), .B(mult_x_23_n33), .C(n885), .CO(n886),
.S(Sgf_operation_EVEN1_left_N21) );
CMPR32X2TS U1231 ( .A(n888), .B(n564), .C(mult_x_23_n31), .CO(n889), .S(n887) );
OAI31X1TS U1232 ( .A0(n892), .A1(n419), .A2(n496), .B0(n891), .Y(n893) );
XNOR2X1TS U1233 ( .A(Op_MY[22]), .B(n893), .Y(Sgf_operation_EVEN1_left_N23)
);
CMPR32X2TS U1234 ( .A(mult_x_23_n128), .B(mult_x_23_n132), .C(n894), .CO(
n827), .S(Sgf_operation_EVEN1_left_N7) );
OAI21X1TS U1235 ( .A0(n484), .A1(n555), .B0(n486), .Y(mult_x_23_n177) );
NOR2X1TS U1236 ( .A(n1562), .B(n852), .Y(mult_x_23_n162) );
OAI21X1TS U1237 ( .A0(n490), .A1(n562), .B0(n481), .Y(mult_x_23_n191) );
CMPR32X2TS U1238 ( .A(n898), .B(n897), .C(n896), .CO(n838), .S(
Sgf_operation_EVEN1_left_N5) );
OAI22X1TS U1239 ( .A0(n929), .A1(n900), .B0(n623), .B1(n899), .Y(n902) );
AOI22X1TS U1240 ( .A0(n486), .A1(n917), .B0(n830), .B1(n488), .Y(n901) );
CMPR32X2TS U1241 ( .A(n902), .B(mult_x_23_n50), .C(n901), .CO(mult_x_23_n47),
.S(mult_x_23_n48) );
ADDHXLTS U1242 ( .A(n904), .B(n903), .CO(n840), .S(
Sgf_operation_EVEN1_left_N1) );
CMPR32X2TS U1243 ( .A(n907), .B(n906), .C(n905), .CO(n896), .S(
Sgf_operation_EVEN1_left_N4) );
NOR2XLTS U1244 ( .A(n1562), .B(n1561), .Y(Sgf_operation_EVEN1_left_N0) );
AOI22X1TS U1245 ( .A0(n483), .A1(n1562), .B0(Op_MY[12]), .B1(n482), .Y(n912)
);
OAI22X1TS U1246 ( .A0(n929), .A1(n913), .B0(n623), .B1(n912), .Y(n920) );
AOI22X1TS U1247 ( .A0(n479), .A1(mult_x_23_n50), .B0(n529), .B1(n490), .Y(
n932) );
OAI22X1TS U1248 ( .A0(n933), .A1(n914), .B0(n630), .B1(n932), .Y(n919) );
OAI22X1TS U1249 ( .A0(n917), .A1(n916), .B0(n830), .B1(n915), .Y(n918) );
CMPR32X2TS U1250 ( .A(n920), .B(n919), .C(n918), .CO(mult_x_23_n117), .S(
mult_x_23_n118) );
ADDHXLTS U1251 ( .A(n925), .B(n924), .CO(mult_x_23_n106), .S(mult_x_23_n107)
);
AOI22X1TS U1252 ( .A0(n540), .A1(mult_x_23_n50), .B0(n529), .B1(n927), .Y(
n926) );
AOI22X1TS U1253 ( .A0(n540), .A1(n417), .B0(Op_MY[20]), .B1(n927), .Y(n928)
);
OAI22X1TS U1254 ( .A0(n933), .A1(n932), .B0(n630), .B1(n930), .Y(n934) );
CMPR32X2TS U1255 ( .A(mult_x_55_n40), .B(mult_x_55_n36), .C(n939), .CO(n1001), .S(Sgf_operation_EVEN1_right_N20) );
CMPR32X2TS U1256 ( .A(mult_x_55_n46), .B(mult_x_55_n52), .C(n940), .CO(n938),
.S(Sgf_operation_EVEN1_right_N18) );
CMPR32X2TS U1257 ( .A(mult_x_55_n59), .B(mult_x_55_n66), .C(n941), .CO(n937),
.S(Sgf_operation_EVEN1_right_N16) );
CMPR32X2TS U1258 ( .A(mult_x_55_n75), .B(mult_x_55_n84), .C(n942), .CO(n675),
.S(Sgf_operation_EVEN1_right_N14) );
CMPR32X2TS U1259 ( .A(mult_x_55_n94), .B(mult_x_55_n101), .C(n943), .CO(n674), .S(Sgf_operation_EVEN1_right_N12) );
CMPR32X2TS U1260 ( .A(mult_x_55_n110), .B(mult_x_55_n115), .C(n944), .CO(
n673), .S(Sgf_operation_EVEN1_right_N10) );
CMPR32X2TS U1261 ( .A(mult_x_55_n123), .B(mult_x_55_n127), .C(n945), .CO(
n672), .S(Sgf_operation_EVEN1_right_N8) );
CMPR32X2TS U1262 ( .A(mult_x_55_n133), .B(n947), .C(n946), .CO(n676), .S(
Sgf_operation_EVEN1_right_N6) );
CMPR32X2TS U1263 ( .A(n950), .B(n949), .C(n948), .CO(n1045), .S(
Sgf_operation_EVEN1_right_N2) );
INVX4TS U1264 ( .A(Op_MX[11]), .Y(n1059) );
BUFX3TS U1265 ( .A(Op_MX[11]), .Y(n1023) );
NAND2X1TS U1266 ( .A(n1023), .B(n527), .Y(n1043) );
AOI22X1TS U1267 ( .A0(n1014), .A1(n551), .B0(n538), .B1(n399), .Y(n951) );
AOI22X1TS U1268 ( .A0(Op_MX[9]), .A1(n420), .B0(Op_MY[11]), .B1(n492), .Y(
n972) );
AOI22X1TS U1269 ( .A0(Op_MX[9]), .A1(n403), .B0(Op_MY[10]), .B1(n492), .Y(
n1040) );
OAI22X1TS U1270 ( .A0(n1075), .A1(n972), .B0(n952), .B1(n1040), .Y(n953) );
CMPR32X2TS U1271 ( .A(n955), .B(n954), .C(n953), .CO(mult_x_55_n42), .S(
mult_x_55_n43) );
NAND2X1TS U1272 ( .A(n1023), .B(Op_MY[1]), .Y(n1080) );
AOI22X1TS U1273 ( .A0(n469), .A1(n550), .B0(Op_MX[6]), .B1(n468), .Y(n956)
);
AOI22X1TS U1274 ( .A0(n470), .A1(n415), .B0(Op_MY[9]), .B1(n495), .Y(n978)
);
AOI22X1TS U1275 ( .A0(n470), .A1(n418), .B0(Op_MY[8]), .B1(n495), .Y(n1030)
);
OAI22X1TS U1276 ( .A0(n1054), .A1(n978), .B0(n957), .B1(n1030), .Y(n958) );
CMPR32X2TS U1277 ( .A(n960), .B(n959), .C(n958), .CO(mult_x_55_n71), .S(
mult_x_55_n72) );
AOI22X1TS U1278 ( .A0(Op_MX[10]), .A1(n492), .B0(n536), .B1(n554), .Y(n961)
);
BUFX4TS U1279 ( .A(n961), .Y(n1058) );
AOI22X1TS U1280 ( .A0(Op_MX[11]), .A1(n420), .B0(Op_MY[11]), .B1(n1059), .Y(
n1000) );
AOI22X1TS U1281 ( .A0(Op_MX[11]), .A1(n403), .B0(Op_MY[10]), .B1(n1059), .Y(
n963) );
OAI22X1TS U1282 ( .A0(n1058), .A1(n1000), .B0(n962), .B1(n963), .Y(
mult_x_55_n157) );
AOI22X1TS U1283 ( .A0(Op_MX[11]), .A1(n415), .B0(Op_MY[9]), .B1(n1059), .Y(
n964) );
OAI22X1TS U1284 ( .A0(n1058), .A1(n963), .B0(n962), .B1(n964), .Y(
mult_x_55_n158) );
AOI22X1TS U1285 ( .A0(Op_MX[11]), .A1(n418), .B0(Op_MY[8]), .B1(n1059), .Y(
n965) );
OAI22X1TS U1286 ( .A0(n1058), .A1(n964), .B0(n962), .B1(n965), .Y(
mult_x_55_n159) );
AOI22X1TS U1287 ( .A0(Op_MX[11]), .A1(n416), .B0(Op_MY[7]), .B1(n1568), .Y(
n966) );
OAI22X1TS U1288 ( .A0(n1058), .A1(n965), .B0(n962), .B1(n966), .Y(
mult_x_55_n160) );
AOI22X1TS U1289 ( .A0(n1023), .A1(n1563), .B0(n527), .B1(n1568), .Y(n967) );
OAI22X1TS U1290 ( .A0(n1058), .A1(n966), .B0(n962), .B1(n967), .Y(
mult_x_55_n161) );
AOI22X1TS U1291 ( .A0(n1023), .A1(n1564), .B0(Op_MY[5]), .B1(n1568), .Y(n968) );
OAI22X1TS U1292 ( .A0(n1058), .A1(n967), .B0(n962), .B1(n968), .Y(
mult_x_55_n162) );
AOI22X1TS U1293 ( .A0(n1023), .A1(n559), .B0(Op_MY[4]), .B1(n1568), .Y(n969)
);
OAI22X1TS U1294 ( .A0(n1058), .A1(n968), .B0(n962), .B1(n969), .Y(
mult_x_55_n163) );
AOI22X1TS U1295 ( .A0(n1023), .A1(n1565), .B0(Op_MY[3]), .B1(n1568), .Y(n970) );
OAI22X1TS U1296 ( .A0(n1058), .A1(n969), .B0(n962), .B1(n970), .Y(
mult_x_55_n164) );
AOI22X1TS U1297 ( .A0(n1023), .A1(n414), .B0(Op_MY[2]), .B1(n1568), .Y(n971)
);
OAI22X1TS U1298 ( .A0(n1058), .A1(n970), .B0(n962), .B1(n971), .Y(
mult_x_55_n165) );
AOI22X1TS U1299 ( .A0(n1023), .A1(n561), .B0(Op_MY[1]), .B1(n1568), .Y(n1012) );
OAI22X1TS U1300 ( .A0(n1058), .A1(n971), .B0(n962), .B1(n1012), .Y(
mult_x_55_n166) );
OAI22X1TS U1301 ( .A0(n492), .A1(n1075), .B0(n952), .B1(n972), .Y(
mult_x_55_n170) );
AOI22X1TS U1302 ( .A0(Op_MX[9]), .A1(n415), .B0(Op_MY[9]), .B1(n492), .Y(
n1039) );
AOI22X1TS U1303 ( .A0(Op_MX[9]), .A1(n418), .B0(Op_MY[8]), .B1(n395), .Y(
n973) );
OAI22X1TS U1304 ( .A0(n1075), .A1(n1039), .B0(n952), .B1(n973), .Y(
mult_x_55_n173) );
AOI22X1TS U1305 ( .A0(Op_MX[9]), .A1(n416), .B0(Op_MY[7]), .B1(n395), .Y(
n974) );
OAI22X1TS U1306 ( .A0(n1075), .A1(n973), .B0(n952), .B1(n974), .Y(
mult_x_55_n174) );
AOI22X1TS U1307 ( .A0(Op_MX[9]), .A1(n1563), .B0(n527), .B1(n395), .Y(n975)
);
OAI22X1TS U1308 ( .A0(n1075), .A1(n974), .B0(n952), .B1(n975), .Y(
mult_x_55_n175) );
AOI22X1TS U1309 ( .A0(Op_MX[9]), .A1(n1564), .B0(Op_MY[5]), .B1(n395), .Y(
n1074) );
OAI22X1TS U1310 ( .A0(n1075), .A1(n975), .B0(n952), .B1(n1074), .Y(
mult_x_55_n176) );
AOI22X1TS U1311 ( .A0(Op_MX[9]), .A1(n559), .B0(Op_MY[4]), .B1(n395), .Y(
n1073) );
AOI22X1TS U1312 ( .A0(Op_MX[9]), .A1(n1565), .B0(Op_MY[3]), .B1(n395), .Y(
n976) );
OAI22X1TS U1313 ( .A0(n1075), .A1(n1073), .B0(n952), .B1(n976), .Y(
mult_x_55_n178) );
AOI22X1TS U1314 ( .A0(Op_MX[9]), .A1(n414), .B0(Op_MY[2]), .B1(n395), .Y(
n977) );
OAI22X1TS U1315 ( .A0(n1075), .A1(n976), .B0(n952), .B1(n977), .Y(
mult_x_55_n179) );
AOI22X1TS U1316 ( .A0(Op_MX[9]), .A1(n561), .B0(Op_MY[1]), .B1(n492), .Y(
n1016) );
OAI22X1TS U1317 ( .A0(n1075), .A1(n977), .B0(n952), .B1(n1016), .Y(
mult_x_55_n180) );
AOI22X1TS U1318 ( .A0(Op_MY[11]), .A1(n495), .B0(n470), .B1(n420), .Y(n1041)
);
AOI22X1TS U1319 ( .A0(Op_MY[10]), .A1(n495), .B0(n470), .B1(n403), .Y(n979)
);
OAI22X1TS U1320 ( .A0(n1054), .A1(n1041), .B0(n957), .B1(n979), .Y(
mult_x_55_n185) );
OAI22X1TS U1321 ( .A0(n1054), .A1(n979), .B0(n957), .B1(n978), .Y(
mult_x_55_n186) );
AOI22X1TS U1322 ( .A0(n470), .A1(n416), .B0(Op_MY[7]), .B1(n495), .Y(n1029)
);
AOI22X1TS U1323 ( .A0(n470), .A1(n1563), .B0(n527), .B1(n495), .Y(n980) );
OAI22X1TS U1324 ( .A0(n1054), .A1(n1029), .B0(n957), .B1(n980), .Y(
mult_x_55_n189) );
AOI22X1TS U1325 ( .A0(n470), .A1(n1564), .B0(Op_MY[5]), .B1(n495), .Y(n981)
);
OAI22X1TS U1326 ( .A0(n1054), .A1(n980), .B0(n957), .B1(n981), .Y(
mult_x_55_n190) );
AOI22X1TS U1327 ( .A0(n470), .A1(n559), .B0(Op_MY[4]), .B1(n495), .Y(n982)
);
OAI22X1TS U1328 ( .A0(n1054), .A1(n981), .B0(n957), .B1(n982), .Y(
mult_x_55_n191) );
AOI22X1TS U1329 ( .A0(n470), .A1(n1565), .B0(Op_MY[3]), .B1(n495), .Y(n1019)
);
OAI22X1TS U1330 ( .A0(n1054), .A1(n982), .B0(n957), .B1(n1019), .Y(
mult_x_55_n192) );
AOI22X1TS U1331 ( .A0(n470), .A1(n414), .B0(Op_MY[2]), .B1(n495), .Y(n1018)
);
AOI22X1TS U1332 ( .A0(n470), .A1(n561), .B0(Op_MY[1]), .B1(n399), .Y(n984)
);
OAI22X1TS U1333 ( .A0(n1054), .A1(n1018), .B0(n957), .B1(n984), .Y(
mult_x_55_n194) );
AOI22X1TS U1334 ( .A0(Op_MY[0]), .A1(n399), .B0(n470), .B1(n1567), .Y(n983)
);
OAI22X1TS U1335 ( .A0(n1054), .A1(n984), .B0(n957), .B1(n983), .Y(
mult_x_55_n195) );
AOI22X1TS U1336 ( .A0(Op_MY[11]), .A1(n411), .B0(n469), .B1(n420), .Y(n985)
);
OAI22X1TS U1337 ( .A0(n411), .A1(n1078), .B0(n651), .B1(n985), .Y(
mult_x_55_n198) );
AOI22X1TS U1338 ( .A0(Op_MY[10]), .A1(n411), .B0(n469), .B1(n403), .Y(n986)
);
OAI22X1TS U1339 ( .A0(n1078), .A1(n985), .B0(n651), .B1(n986), .Y(
mult_x_55_n199) );
AOI22X1TS U1340 ( .A0(n469), .A1(n415), .B0(Op_MY[9]), .B1(n411), .Y(n1077)
);
OAI22X1TS U1341 ( .A0(n1078), .A1(n986), .B0(n651), .B1(n1077), .Y(
mult_x_55_n200) );
AOI22X1TS U1342 ( .A0(n469), .A1(n418), .B0(Op_MY[8]), .B1(n411), .Y(n1076)
);
AOI22X1TS U1343 ( .A0(n469), .A1(n416), .B0(Op_MY[7]), .B1(n411), .Y(n987)
);
OAI22X1TS U1344 ( .A0(n1078), .A1(n1076), .B0(n651), .B1(n987), .Y(
mult_x_55_n202) );
AOI22X1TS U1345 ( .A0(n469), .A1(n1563), .B0(n527), .B1(n411), .Y(n988) );
OAI22X1TS U1346 ( .A0(n1078), .A1(n987), .B0(n651), .B1(n988), .Y(
mult_x_55_n203) );
AOI22X1TS U1347 ( .A0(n537), .A1(n1564), .B0(Op_MY[5]), .B1(n411), .Y(n989)
);
OAI22X1TS U1348 ( .A0(n1078), .A1(n988), .B0(n651), .B1(n989), .Y(
mult_x_55_n204) );
AOI22X1TS U1349 ( .A0(n537), .A1(n559), .B0(Op_MY[4]), .B1(n411), .Y(n990)
);
OAI22X1TS U1350 ( .A0(n1078), .A1(n989), .B0(n651), .B1(n990), .Y(
mult_x_55_n205) );
AOI22X1TS U1351 ( .A0(n537), .A1(n1565), .B0(Op_MY[3]), .B1(n411), .Y(n991)
);
OAI22X1TS U1352 ( .A0(n1078), .A1(n990), .B0(n651), .B1(n991), .Y(
mult_x_55_n206) );
AOI22X1TS U1353 ( .A0(n537), .A1(n414), .B0(Op_MY[2]), .B1(n468), .Y(n993)
);
OAI22X1TS U1354 ( .A0(n1078), .A1(n991), .B0(n651), .B1(n993), .Y(
mult_x_55_n207) );
OAI22X1TS U1355 ( .A0(n1078), .A1(n993), .B0(n651), .B1(n992), .Y(
mult_x_55_n208) );
AOI22X1TS U1356 ( .A0(Op_MY[11]), .A1(n494), .B0(n459), .B1(n420), .Y(n994)
);
OAI22X1TS U1357 ( .A0(n494), .A1(n1069), .B0(n654), .B1(n994), .Y(
mult_x_55_n212) );
AOI22X1TS U1358 ( .A0(Op_MY[10]), .A1(n494), .B0(n459), .B1(n403), .Y(n1049)
);
OAI22X1TS U1359 ( .A0(n1069), .A1(n994), .B0(n654), .B1(n1049), .Y(
mult_x_55_n213) );
AOI22X1TS U1360 ( .A0(n459), .A1(n415), .B0(Op_MY[9]), .B1(n494), .Y(n1048)
);
AOI22X1TS U1361 ( .A0(n459), .A1(n418), .B0(Op_MY[8]), .B1(n494), .Y(n995)
);
OAI22X1TS U1362 ( .A0(n1069), .A1(n1048), .B0(n654), .B1(n995), .Y(
mult_x_55_n215) );
AOI22X1TS U1363 ( .A0(n459), .A1(n416), .B0(Op_MY[7]), .B1(n494), .Y(n1017)
);
OAI22X1TS U1364 ( .A0(n1069), .A1(n995), .B0(n654), .B1(n1017), .Y(
mult_x_55_n216) );
AOI22X1TS U1365 ( .A0(n459), .A1(n1564), .B0(Op_MY[5]), .B1(n494), .Y(n1067)
);
AOI22X1TS U1366 ( .A0(n459), .A1(n559), .B0(Op_MY[4]), .B1(n494), .Y(n997)
);
OAI22X1TS U1367 ( .A0(n1069), .A1(n1067), .B0(n654), .B1(n997), .Y(
mult_x_55_n219) );
OAI22X1TS U1368 ( .A0(n1069), .A1(n997), .B0(n654), .B1(n996), .Y(
mult_x_55_n220) );
AOI22X1TS U1369 ( .A0(Op_MY[10]), .A1(mult_x_55_n225), .B0(n542), .B1(n403),
.Y(n998) );
AOI22X1TS U1370 ( .A0(n542), .A1(n1563), .B0(n527), .B1(n1065), .Y(n999) );
OAI22X1TS U1371 ( .A0(n1059), .A1(n1058), .B0(n962), .B1(n1000), .Y(n1007)
);
NAND2X1TS U1372 ( .A(n1023), .B(Op_MY[10]), .Y(n1006) );
CMPR32X2TS U1373 ( .A(mult_x_55_n35), .B(mult_x_55_n33), .C(n1001), .CO(
n1004), .S(Sgf_operation_EVEN1_right_N21) );
AOI21X1TS U1374 ( .A0(Op_MX[10]), .A1(Op_MX[9]), .B0(n1568), .Y(n1003) );
OAI221XLTS U1375 ( .A0(Op_MY[10]), .A1(Op_MY[11]), .B0(n403), .B1(n420),
.C0(Op_MX[11]), .Y(n1002) );
XNOR2X1TS U1376 ( .A(n1003), .B(n1002), .Y(n1011) );
CMPR32X2TS U1377 ( .A(mult_x_55_n32), .B(n1005), .C(n1004), .CO(n1009), .S(
Sgf_operation_EVEN1_right_N22) );
CMPR32X2TS U1378 ( .A(n1007), .B(n1006), .C(mult_x_55_n31), .CO(n1008), .S(
n1005) );
OAI21XLTS U1379 ( .A0(n495), .A1(n551), .B0(Op_MX[9]), .Y(mult_x_55_n169) );
NOR2X1TS U1380 ( .A(n1059), .B(n1567), .Y(n1051) );
NOR2XLTS U1381 ( .A(n1023), .B(Op_MY[0]), .Y(n1013) );
OAI32X1TS U1382 ( .A0(n1051), .A1(n1013), .A2(n962), .B0(n1058), .B1(n1012),
.Y(mult_x_55_n167) );
OAI21X1TS U1383 ( .A0(n411), .A1(n550), .B0(n470), .Y(mult_x_55_n183) );
AOI22X1TS U1384 ( .A0(Op_MX[9]), .A1(n1567), .B0(Op_MY[0]), .B1(n395), .Y(
n1015) );
OAI22X1TS U1385 ( .A0(n1075), .A1(n1016), .B0(n952), .B1(n1015), .Y(n1022)
);
AOI22X1TS U1386 ( .A0(n459), .A1(n1563), .B0(n527), .B1(n494), .Y(n1068) );
OAI22X1TS U1387 ( .A0(n1069), .A1(n1017), .B0(n654), .B1(n1068), .Y(n1021)
);
OAI22X1TS U1388 ( .A0(n1054), .A1(n1019), .B0(n957), .B1(n1018), .Y(n1020)
);
CMPR32X2TS U1389 ( .A(n1022), .B(n1021), .C(n1020), .CO(mult_x_55_n117), .S(
mult_x_55_n118) );
NOR2X1TS U1390 ( .A(n1059), .B(n1564), .Y(mult_x_55_n151) );
NOR2X1TS U1391 ( .A(n1059), .B(n415), .Y(mult_x_55_n149) );
NAND2X1TS U1392 ( .A(n1023), .B(Op_MY[4]), .Y(mult_x_55_n64) );
INVX2TS U1393 ( .A(mult_x_55_n64), .Y(mult_x_55_n63) );
NAND2X1TS U1394 ( .A(Op_MX[11]), .B(Op_MY[8]), .Y(mult_x_55_n38) );
OAI21X1TS U1395 ( .A0(n494), .A1(n549), .B0(n537), .Y(mult_x_55_n197) );
CMPR32X2TS U1396 ( .A(n1026), .B(n1025), .C(n1024), .CO(n946), .S(
Sgf_operation_EVEN1_right_N5) );
ADDHXLTS U1397 ( .A(n1028), .B(n1027), .CO(mult_x_55_n136), .S(n1025) );
OAI22X1TS U1398 ( .A0(n1054), .A1(n1030), .B0(n957), .B1(n1029), .Y(n1031)
);
CMPR32X2TS U1399 ( .A(n1080), .B(n1032), .C(n1031), .CO(mult_x_55_n79), .S(
mult_x_55_n80) );
ADDHXLTS U1400 ( .A(n1035), .B(n1034), .CO(n948), .S(
Sgf_operation_EVEN1_right_N1) );
CMPR32X2TS U1401 ( .A(n1038), .B(n1037), .C(n1036), .CO(n1024), .S(
Sgf_operation_EVEN1_right_N4) );
OAI22X1TS U1402 ( .A0(n1075), .A1(n1040), .B0(n952), .B1(n1039), .Y(n1044)
);
OAI22X1TS U1403 ( .A0(n495), .A1(n1054), .B0(n957), .B1(n1041), .Y(n1042) );
CMPR32X2TS U1404 ( .A(n1044), .B(n1043), .C(n1042), .CO(mult_x_55_n47), .S(
mult_x_55_n48) );
CMPR32X2TS U1405 ( .A(n1047), .B(n1046), .C(n1045), .CO(n1036), .S(
Sgf_operation_EVEN1_right_N3) );
INVX2TS U1406 ( .A(mult_x_55_n38), .Y(mult_x_55_n37) );
AOI21X1TS U1407 ( .A0(Op_MY[11]), .A1(n1566), .B0(n1065), .Y(n1052) );
OAI22X1TS U1408 ( .A0(n1069), .A1(n1049), .B0(n654), .B1(n1048), .Y(n1050)
);
CMPR32X2TS U1409 ( .A(n1052), .B(n1051), .C(n1050), .CO(mult_x_55_n98), .S(
mult_x_55_n99) );
AOI22X1TS U1410 ( .A0(n542), .A1(n416), .B0(Op_MY[7]), .B1(n1065), .Y(n1053)
);
OAI32X1TS U1411 ( .A0(Op_MX[0]), .A1(n527), .A2(mult_x_55_n225), .B0(n1053),
.B1(n1566), .Y(n1056) );
OAI32X1TS U1412 ( .A0(n495), .A1(Op_MY[0]), .A2(n1054), .B0(n957), .B1(n495),
.Y(n1055) );
ADDHXLTS U1413 ( .A(n1056), .B(n1055), .CO(mult_x_55_n129), .S(
mult_x_55_n130) );
AOI22X1TS U1414 ( .A0(Op_MY[11]), .A1(n1065), .B0(n542), .B1(n420), .Y(n1057) );
OAI32X1TS U1415 ( .A0(Op_MX[0]), .A1(Op_MY[10]), .A2(n541), .B0(n1057), .B1(
n1566), .Y(n1061) );
OAI32X1TS U1416 ( .A0(n1059), .A1(Op_MY[0]), .A2(n1058), .B0(n962), .B1(
n1059), .Y(n1060) );
ADDHXLTS U1417 ( .A(n1061), .B(n1060), .CO(mult_x_55_n106), .S(
mult_x_55_n107) );
AOI22X1TS U1418 ( .A0(n542), .A1(n415), .B0(Op_MY[9]), .B1(n1065), .Y(n1062)
);
OAI32X1TS U1419 ( .A0(Op_MX[0]), .A1(Op_MY[8]), .A2(mult_x_55_n225), .B0(
n1062), .B1(n1566), .Y(n1064) );
OAI32X1TS U1420 ( .A0(n492), .A1(Op_MY[0]), .A2(n1075), .B0(n952), .B1(n395),
.Y(n1063) );
ADDHXLTS U1421 ( .A(n1064), .B(n1063), .CO(mult_x_55_n119), .S(
mult_x_55_n120) );
AOI22X1TS U1422 ( .A0(n542), .A1(n418), .B0(Op_MY[8]), .B1(n1065), .Y(n1066)
);
OAI22X1TS U1423 ( .A0(n1069), .A1(n1068), .B0(n654), .B1(n1067), .Y(n1070)
);
OAI22X1TS U1424 ( .A0(n1075), .A1(n1074), .B0(n952), .B1(n1073), .Y(n1081)
);
OAI22X1TS U1425 ( .A0(n1078), .A1(n1077), .B0(n651), .B1(n1076), .Y(n1079)
);
NOR2XLTS U1426 ( .A(n1567), .B(n1566), .Y(Sgf_operation_EVEN1_right_N0) );
ADDHXLTS U1427 ( .A(n1085), .B(n1084), .CO(n1143), .S(
Sgf_operation_EVEN1_middle_N1) );
AOI22X1TS U1428 ( .A0(n1137), .A1(n1133), .B0(n1237), .B1(n1088), .Y(
DP_OP_111J18_123_4462_n162) );
AOI22X1TS U1429 ( .A0(n1137), .A1(n1197), .B0(n1133), .B1(n1088), .Y(
DP_OP_111J18_123_4462_n163) );
AOI22X1TS U1430 ( .A0(n1137), .A1(n1171), .B0(n1197), .B1(n1088), .Y(
DP_OP_111J18_123_4462_n164) );
AOI22X1TS U1431 ( .A0(n1137), .A1(n1233), .B0(n1171), .B1(n1088), .Y(
DP_OP_111J18_123_4462_n165) );
AOI22X1TS U1432 ( .A0(n1137), .A1(n1175), .B0(n1233), .B1(n1088), .Y(
DP_OP_111J18_123_4462_n166) );
AOI22X1TS U1433 ( .A0(n1137), .A1(n1184), .B0(n1175), .B1(n1088), .Y(
DP_OP_111J18_123_4462_n167) );
AOI22X1TS U1434 ( .A0(n1137), .A1(n1177), .B0(n1184), .B1(n1088), .Y(
DP_OP_111J18_123_4462_n168) );
AOI22X1TS U1435 ( .A0(n1137), .A1(n1120), .B0(n1177), .B1(n1088), .Y(
DP_OP_111J18_123_4462_n169) );
AOI22X1TS U1436 ( .A0(n1137), .A1(n1113), .B0(n1120), .B1(n1088), .Y(
DP_OP_111J18_123_4462_n170) );
AOI22X1TS U1437 ( .A0(n1137), .A1(n1142), .B0(n1113), .B1(n1088), .Y(
DP_OP_111J18_123_4462_n171) );
AOI22X1TS U1438 ( .A0(n460), .A1(n1219), .B0(n1220), .B1(n461), .Y(n1090) );
OAI22X1TS U1439 ( .A0(n467), .A1(n1089), .B0(n1102), .B1(n1090), .Y(
DP_OP_111J18_123_4462_n175) );
AOI22X1TS U1440 ( .A0(n460), .A1(n1239), .B0(n1237), .B1(n461), .Y(n1091) );
OAI22X1TS U1441 ( .A0(n1091), .A1(n1102), .B0(n467), .B1(n1090), .Y(
DP_OP_111J18_123_4462_n176) );
AOI22X1TS U1442 ( .A0(n460), .A1(n1242), .B0(n1133), .B1(n461), .Y(n1092) );
OAI22X1TS U1443 ( .A0(n1091), .A1(n467), .B0(n1092), .B1(n1102), .Y(
DP_OP_111J18_123_4462_n177) );
AOI22X1TS U1444 ( .A0(n460), .A1(n1199), .B0(n1197), .B1(n461), .Y(n1093) );
OAI22X1TS U1445 ( .A0(n1092), .A1(n467), .B0(n1093), .B1(n1102), .Y(
DP_OP_111J18_123_4462_n178) );
AOI22X1TS U1446 ( .A0(n1100), .A1(n1172), .B0(n1171), .B1(n461), .Y(n1094)
);
OAI22X1TS U1447 ( .A0(n1093), .A1(n467), .B0(n1094), .B1(n1102), .Y(
DP_OP_111J18_123_4462_n179) );
AOI22X1TS U1448 ( .A0(n1100), .A1(n1234), .B0(n1233), .B1(n461), .Y(n1095)
);
OAI22X1TS U1449 ( .A0(n1094), .A1(n467), .B0(n1095), .B1(n1102), .Y(
DP_OP_111J18_123_4462_n180) );
AOI22X1TS U1450 ( .A0(n1100), .A1(n1236), .B0(n1175), .B1(n461), .Y(n1096)
);
OAI22X1TS U1451 ( .A0(n1095), .A1(n467), .B0(n1096), .B1(n1102), .Y(
DP_OP_111J18_123_4462_n181) );
AOI22X1TS U1452 ( .A0(n1100), .A1(n1185), .B0(n1184), .B1(n461), .Y(n1097)
);
OAI22X1TS U1453 ( .A0(n1096), .A1(n467), .B0(n1097), .B1(n1102), .Y(
DP_OP_111J18_123_4462_n182) );
AOI22X1TS U1454 ( .A0(n1100), .A1(n1178), .B0(n1177), .B1(n461), .Y(n1098)
);
OAI22X1TS U1455 ( .A0(n1097), .A1(n467), .B0(n1098), .B1(n1102), .Y(
DP_OP_111J18_123_4462_n183) );
AOI22X1TS U1456 ( .A0(n1100), .A1(n1121), .B0(n1120), .B1(n461), .Y(n1099)
);
OAI22X1TS U1457 ( .A0(n1098), .A1(n467), .B0(n1099), .B1(n1102), .Y(
DP_OP_111J18_123_4462_n184) );
AOI22X1TS U1458 ( .A0(n1100), .A1(n1114), .B0(n1113), .B1(n461), .Y(n1103)
);
OAI22X1TS U1459 ( .A0(n1099), .A1(n466), .B0(n1103), .B1(n1102), .Y(
DP_OP_111J18_123_4462_n185) );
AOI22X1TS U1460 ( .A0(n1100), .A1(n1161), .B0(n1142), .B1(n461), .Y(n1101)
);
OAI22X1TS U1461 ( .A0(n1103), .A1(n467), .B0(n1102), .B1(n1101), .Y(
DP_OP_111J18_123_4462_n186) );
AOI22X1TS U1462 ( .A0(n475), .A1(n1237), .B0(n1239), .B1(n1218), .Y(n1222)
);
AOI22X1TS U1463 ( .A0(n475), .A1(n1133), .B0(n1242), .B1(n1218), .Y(n1136)
);
OAI22X1TS U1464 ( .A0(n1255), .A1(n1222), .B0(n1253), .B1(n1136), .Y(
DP_OP_111J18_123_4462_n191) );
AOI22X1TS U1465 ( .A0(n475), .A1(n1175), .B0(n1236), .B1(n1218), .Y(n1153)
);
AOI22X1TS U1466 ( .A0(n475), .A1(n1184), .B0(n1185), .B1(n1218), .Y(n1105)
);
OAI22X1TS U1467 ( .A0(n1255), .A1(n1153), .B0(n1253), .B1(n1105), .Y(
DP_OP_111J18_123_4462_n195) );
OAI22X1TS U1468 ( .A0(n1255), .A1(n1105), .B0(n1253), .B1(n1104), .Y(
DP_OP_111J18_123_4462_n196) );
AOI22X1TS U1469 ( .A0(n475), .A1(n1113), .B0(n1114), .B1(n1218), .Y(n1108)
);
OAI22X1TS U1470 ( .A0(n1255), .A1(n1106), .B0(n1253), .B1(n1108), .Y(
DP_OP_111J18_123_4462_n198) );
AOI22X1TS U1471 ( .A0(n1161), .A1(n1218), .B0(n475), .B1(n1142), .Y(n1107)
);
OAI22X1TS U1472 ( .A0(n1255), .A1(n1108), .B0(n1253), .B1(n1107), .Y(
DP_OP_111J18_123_4462_n199) );
AOI22X1TS U1473 ( .A0(n1139), .A1(n1225), .B0(n476), .B1(n1138), .Y(n1217)
);
AOI22X1TS U1474 ( .A0(n1220), .A1(n1225), .B0(n476), .B1(n1219), .Y(n1111)
);
OAI221X4TS U1475 ( .A0(n1110), .A1(n477), .B0(n1227), .B1(n1215), .C0(n462),
.Y(n1216) );
OAI22X1TS U1476 ( .A0(n1217), .A1(n463), .B0(n1111), .B1(n1216), .Y(
DP_OP_111J18_123_4462_n202) );
AOI22X1TS U1477 ( .A0(n1239), .A1(n1215), .B0(n1225), .B1(n1237), .Y(n1112)
);
OAI22X1TS U1478 ( .A0(n1111), .A1(n463), .B0(n1216), .B1(n1112), .Y(
DP_OP_111J18_123_4462_n203) );
AOI22X1TS U1479 ( .A0(n1242), .A1(n1215), .B0(n1225), .B1(n1133), .Y(n1157)
);
OAI22X1TS U1480 ( .A0(n463), .A1(n1112), .B0(n1216), .B1(n1157), .Y(
DP_OP_111J18_123_4462_n204) );
AOI22X1TS U1481 ( .A0(n1185), .A1(n1215), .B0(n477), .B1(n1184), .Y(n1174)
);
AOI22X1TS U1482 ( .A0(n1178), .A1(n1215), .B0(n1225), .B1(n1177), .Y(n1181)
);
OAI22X1TS U1483 ( .A0(n462), .A1(n1174), .B0(n1216), .B1(n1181), .Y(
DP_OP_111J18_123_4462_n210) );
AOI22X1TS U1484 ( .A0(n1121), .A1(n1215), .B0(n1225), .B1(n1120), .Y(n1180)
);
AOI22X1TS U1485 ( .A0(n1114), .A1(n1215), .B0(n1225), .B1(n1113), .Y(n1116)
);
OAI22X1TS U1486 ( .A0(n463), .A1(n1180), .B0(n1216), .B1(n1116), .Y(
DP_OP_111J18_123_4462_n212) );
AOI22X1TS U1487 ( .A0(n1161), .A1(n1215), .B0(n1225), .B1(n1142), .Y(n1115)
);
OAI22X1TS U1488 ( .A0(n462), .A1(n1116), .B0(n1216), .B1(n1115), .Y(
DP_OP_111J18_123_4462_n213) );
AOI22X1TS U1489 ( .A0(n1139), .A1(n1198), .B0(n472), .B1(n1138), .Y(n1117)
);
OAI22X1TS U1490 ( .A0(n1117), .A1(n1205), .B0(n472), .B1(n465), .Y(
DP_OP_111J18_123_4462_n216) );
AOI22X1TS U1491 ( .A0(n1220), .A1(n1198), .B0(n472), .B1(n1219), .Y(n1118)
);
OAI22X1TS U1492 ( .A0(n1117), .A1(n465), .B0(n1118), .B1(n1205), .Y(
DP_OP_111J18_123_4462_n217) );
AOI22X1TS U1493 ( .A0(n1239), .A1(n1226), .B0(n1198), .B1(n1237), .Y(n1119)
);
OAI22X1TS U1494 ( .A0(n1118), .A1(n465), .B0(n1205), .B1(n1119), .Y(
DP_OP_111J18_123_4462_n218) );
AOI22X1TS U1495 ( .A0(n1242), .A1(n1226), .B0(n1198), .B1(n1133), .Y(n1206)
);
OAI22X1TS U1496 ( .A0(n465), .A1(n1119), .B0(n1205), .B1(n1206), .Y(
DP_OP_111J18_123_4462_n219) );
AOI22X1TS U1497 ( .A0(n1234), .A1(n1226), .B0(n1198), .B1(n1233), .Y(n1173)
);
AOI22X1TS U1498 ( .A0(n1236), .A1(n1226), .B0(n1198), .B1(n1175), .Y(n1190)
);
OAI22X1TS U1499 ( .A0(n465), .A1(n1173), .B0(n1205), .B1(n1190), .Y(
DP_OP_111J18_123_4462_n223) );
AOI22X1TS U1500 ( .A0(n1121), .A1(n1226), .B0(n1198), .B1(n1120), .Y(n1179)
);
OAI22X1TS U1501 ( .A0(n464), .A1(n1179), .B0(n1205), .B1(n1122), .Y(
DP_OP_111J18_123_4462_n227) );
AOI22X1TS U1502 ( .A0(n1139), .A1(n1249), .B0(n547), .B1(n1138), .Y(n1123)
);
OAI22X1TS U1503 ( .A0(n1123), .A1(n588), .B0(n547), .B1(n1193), .Y(
DP_OP_111J18_123_4462_n231) );
AOI22X1TS U1504 ( .A0(n1220), .A1(n1249), .B0(n547), .B1(n1219), .Y(n1124)
);
OAI22X1TS U1505 ( .A0(n1123), .A1(n1193), .B0(n1124), .B1(n588), .Y(
DP_OP_111J18_123_4462_n232) );
AOI22X1TS U1506 ( .A0(n1239), .A1(n547), .B0(n1249), .B1(n1237), .Y(n1126)
);
OAI22X1TS U1507 ( .A0(n1124), .A1(n1193), .B0(n588), .B1(n1126), .Y(
DP_OP_111J18_123_4462_n233) );
OAI22X1TS U1508 ( .A0(n1193), .A1(n1126), .B0(n588), .B1(n1125), .Y(
DP_OP_111J18_123_4462_n234) );
OAI22X1TS U1509 ( .A0(n1193), .A1(n1127), .B0(n588), .B1(n1192), .Y(
DP_OP_111J18_123_4462_n236) );
AOI22X1TS U1510 ( .A0(n1185), .A1(n546), .B0(n1249), .B1(n1184), .Y(n1176)
);
OAI22X1TS U1511 ( .A0(n1193), .A1(n1176), .B0(n588), .B1(n1128), .Y(
DP_OP_111J18_123_4462_n240) );
AOI21X1TS U1512 ( .A0(n1138), .A1(n1240), .B0(n1251), .Y(
DP_OP_111J18_123_4462_n245) );
AOI22X1TS U1513 ( .A0(n1139), .A1(n1238), .B0(n1251), .B1(n1138), .Y(n1129)
);
OAI32X1TS U1514 ( .A0(n1243), .A1(n1219), .A2(n1251), .B0(n1129), .B1(n1240),
.Y(DP_OP_111J18_123_4462_n246) );
AOI22X1TS U1515 ( .A0(n1172), .A1(n584), .B0(n1238), .B1(n1171), .Y(n1131)
);
OAI32X1TS U1516 ( .A0(n1243), .A1(n1234), .A2(n584), .B0(n1131), .B1(n1240),
.Y(DP_OP_111J18_123_4462_n251) );
AOI22X1TS U1517 ( .A0(n1199), .A1(n584), .B0(n1238), .B1(n1197), .Y(n1132)
);
OAI32X1TS U1518 ( .A0(n1243), .A1(n1172), .A2(n1251), .B0(n1132), .B1(n1240),
.Y(DP_OP_111J18_123_4462_n250) );
AOI22X1TS U1519 ( .A0(n1242), .A1(n584), .B0(n1238), .B1(n1133), .Y(n1134)
);
OAI32X1TS U1520 ( .A0(n1243), .A1(n1199), .A2(n1251), .B0(n1134), .B1(n1240),
.Y(DP_OP_111J18_123_4462_n249) );
AOI22X1TS U1521 ( .A0(n1220), .A1(n1238), .B0(n1251), .B1(n1219), .Y(n1135)
);
OAI32X1TS U1522 ( .A0(n1243), .A1(n1239), .A2(n1251), .B0(n1135), .B1(n1240),
.Y(DP_OP_111J18_123_4462_n247) );
OAI32X1TS U1523 ( .A0(n1218), .A1(n1161), .A2(n1255), .B0(n1253), .B1(n1218),
.Y(DP_OP_111J18_123_4462_n155) );
NOR2X1TS U1524 ( .A(n1142), .B(n466), .Y(DP_OP_111J18_123_4462_n187) );
AOI22X1TS U1525 ( .A0(n475), .A1(n1197), .B0(n1199), .B1(n1218), .Y(n1254)
);
OAI22X1TS U1526 ( .A0(n1255), .A1(n1136), .B0(n1253), .B1(n1254), .Y(
DP_OP_111J18_123_4462_n67) );
INVX2TS U1527 ( .A(DP_OP_111J18_123_4462_n67), .Y(DP_OP_111J18_123_4462_n68)
);
NOR2X1TS U1528 ( .A(n1137), .B(n1142), .Y(DP_OP_111J18_123_4462_n172) );
AOI22X1TS U1529 ( .A0(n475), .A1(n1139), .B0(n1138), .B1(n474), .Y(n1229) );
OAI22X1TS U1530 ( .A0(n1229), .A1(n1253), .B0(n474), .B1(n1255), .Y(
DP_OP_111J18_123_4462_n41) );
INVX2TS U1531 ( .A(DP_OP_111J18_123_4462_n41), .Y(DP_OP_111J18_123_4462_n42)
);
OAI21X1TS U1532 ( .A0(n547), .A1(n1140), .B0(n1198), .Y(
DP_OP_111J18_123_4462_n215) );
OAI21X1TS U1533 ( .A0(n1141), .A1(n476), .B0(n475), .Y(
DP_OP_111J18_123_4462_n188) );
CMPR32X2TS U1534 ( .A(n1145), .B(n1144), .C(n1143), .CO(n1163), .S(
Sgf_operation_EVEN1_middle_N2) );
CMPR32X2TS U1535 ( .A(n1148), .B(n1147), .C(n1146), .CO(n1167), .S(
Sgf_operation_EVEN1_middle_N4) );
CMPR32X2TS U1536 ( .A(DP_OP_111J18_123_4462_n145), .B(n1150), .C(n1149),
.CO(n1083), .S(Sgf_operation_EVEN1_middle_N6) );
CMPR32X2TS U1537 ( .A(n1152), .B(n1151), .C(DP_OP_111J18_123_4462_n114),
.CO(n821), .S(Sgf_operation_EVEN1_middle_N11) );
AOI22X1TS U1538 ( .A0(n1199), .A1(n1215), .B0(n1225), .B1(n1197), .Y(n1156)
);
AOI22X1TS U1539 ( .A0(n1172), .A1(n1215), .B0(n1225), .B1(n1171), .Y(n1208)
);
OAI22X1TS U1540 ( .A0(n463), .A1(n1156), .B0(n1216), .B1(n1208), .Y(n1155)
);
AOI22X1TS U1541 ( .A0(n475), .A1(n1233), .B0(n1234), .B1(n1218), .Y(n1158)
);
OAI22X1TS U1542 ( .A0(n1255), .A1(n1158), .B0(n1253), .B1(n1153), .Y(n1154)
);
OAI22X1TS U1543 ( .A0(n463), .A1(n1157), .B0(n1216), .B1(n1156), .Y(n1160)
);
AOI22X1TS U1544 ( .A0(n475), .A1(n1171), .B0(n1172), .B1(n1218), .Y(n1252)
);
OAI22X1TS U1545 ( .A0(n1255), .A1(n1252), .B0(n1253), .B1(n1158), .Y(n1159)
);
OAI32X1TS U1546 ( .A0(n1215), .A1(n1161), .A2(n463), .B0(n1216), .B1(n1215),
.Y(DP_OP_111J18_123_4462_n156) );
CMPR32X2TS U1547 ( .A(n1164), .B(n1163), .C(n1162), .CO(n1146), .S(
Sgf_operation_EVEN1_middle_N3) );
CMPR32X2TS U1548 ( .A(n1167), .B(n1166), .C(n1165), .CO(n1149), .S(
Sgf_operation_EVEN1_middle_N5) );
AOI22X1TS U1549 ( .A0(n1172), .A1(n1226), .B0(n1198), .B1(n1171), .Y(n1200)
);
OAI22X1TS U1550 ( .A0(n465), .A1(n1200), .B0(n1205), .B1(n1173), .Y(n1203)
);
AOI22X1TS U1551 ( .A0(n1236), .A1(n1215), .B0(n1225), .B1(n1175), .Y(n1201)
);
OAI22X1TS U1552 ( .A0(n463), .A1(n1201), .B0(n1216), .B1(n1174), .Y(n1202)
);
OAI22X1TS U1553 ( .A0(n1193), .A1(n1183), .B0(n588), .B1(n1176), .Y(n1188)
);
AOI22X1TS U1554 ( .A0(n1178), .A1(n1226), .B0(n473), .B1(n1177), .Y(n1186)
);
OAI22X1TS U1555 ( .A0(n464), .A1(n1186), .B0(n1205), .B1(n1179), .Y(n1187)
);
OAI22X1TS U1556 ( .A0(n463), .A1(n1181), .B0(n1216), .B1(n1180), .Y(n1196)
);
OAI22X1TS U1557 ( .A0(n465), .A1(n1189), .B0(n1205), .B1(n1186), .Y(n1245)
);
CMPR32X2TS U1558 ( .A(n1196), .B(n1195), .C(n1194), .CO(
DP_OP_111J18_123_4462_n129), .S(DP_OP_111J18_123_4462_n130) );
OAI22X1TS U1559 ( .A0(n465), .A1(n1204), .B0(n1205), .B1(n1200), .Y(n1211)
);
AOI22X1TS U1560 ( .A0(n1234), .A1(n1215), .B0(n1225), .B1(n1233), .Y(n1207)
);
OAI22X1TS U1561 ( .A0(n463), .A1(n1207), .B0(n1216), .B1(n1201), .Y(n1210)
);
OAI22X1TS U1562 ( .A0(n465), .A1(n1206), .B0(n1205), .B1(n1204), .Y(n1214)
);
OAI22X1TS U1563 ( .A0(n463), .A1(n1208), .B0(n1216), .B1(n1207), .Y(n1213)
);
CMPR32X2TS U1564 ( .A(n1211), .B(n1210), .C(n1209), .CO(n1212), .S(
DP_OP_111J18_123_4462_n111) );
CMPR32X2TS U1565 ( .A(n1214), .B(n1213), .C(n1212), .CO(
DP_OP_111J18_123_4462_n102), .S(DP_OP_111J18_123_4462_n103) );
INVX2TS U1566 ( .A(n1232), .Y(n1224) );
AOI22X1TS U1567 ( .A0(n475), .A1(n1220), .B0(n1219), .B1(n474), .Y(n1228) );
OAI22X1TS U1568 ( .A0(n1228), .A1(n1255), .B0(n1253), .B1(n1222), .Y(n1223)
);
CMPR32X2TS U1569 ( .A(n1224), .B(DP_OP_111J18_123_4462_n58), .C(n1223), .CO(
DP_OP_111J18_123_4462_n51), .S(DP_OP_111J18_123_4462_n52) );
OAI22X1TS U1570 ( .A0(n1229), .A1(n1255), .B0(n1228), .B1(n1253), .Y(n1230)
);
CMPR32X2TS U1571 ( .A(n1232), .B(n1231), .C(n1230), .CO(
DP_OP_111J18_123_4462_n46), .S(DP_OP_111J18_123_4462_n47) );
AOI22X1TS U1572 ( .A0(n1234), .A1(n584), .B0(n1238), .B1(n1233), .Y(n1235)
);
OAI32X1TS U1573 ( .A0(n1243), .A1(n1236), .A2(n1251), .B0(n1235), .B1(n1240),
.Y(DP_OP_111J18_123_4462_n252) );
AOI22X1TS U1574 ( .A0(n1239), .A1(n584), .B0(n1238), .B1(n1237), .Y(n1241)
);
OAI22X1TS U1575 ( .A0(n1255), .A1(n1254), .B0(n1253), .B1(n1252), .Y(n1256)
);
CMPR32X2TS U1576 ( .A(n1257), .B(n584), .C(n1256), .CO(
DP_OP_111J18_123_4462_n75), .S(DP_OP_111J18_123_4462_n76) );
INVX4TS U1577 ( .A(n1355), .Y(n1538) );
BUFX3TS U1578 ( .A(n1548), .Y(n1549) );
ADDHX1TS U1579 ( .A(Sgf_operation_EVEN1_Q_left[19]), .B(n1264), .CO(n1266),
.S(n1265) );
CMPR22X2TS U1580 ( .A(Sgf_operation_EVEN1_Q_left[22]), .B(n1270), .CO(n799),
.S(n1271) );
INVX2TS U1581 ( .A(rst), .Y(n1630) );
BUFX3TS U1582 ( .A(n1630), .Y(n1613) );
BUFX3TS U1583 ( .A(n1630), .Y(n1614) );
BUFX3TS U1584 ( .A(n566), .Y(n1621) );
BUFX3TS U1585 ( .A(n566), .Y(n1618) );
BUFX3TS U1586 ( .A(n566), .Y(n1617) );
BUFX3TS U1587 ( .A(n1630), .Y(n1612) );
BUFX3TS U1588 ( .A(n566), .Y(n1616) );
BUFX3TS U1589 ( .A(n566), .Y(n1628) );
BUFX3TS U1590 ( .A(n566), .Y(n1627) );
BUFX3TS U1591 ( .A(n566), .Y(n1626) );
BUFX3TS U1592 ( .A(n566), .Y(n1622) );
BUFX3TS U1593 ( .A(n566), .Y(n1625) );
BUFX3TS U1594 ( .A(n566), .Y(n1624) );
NOR3X1TS U1595 ( .A(n1280), .B(n1579), .C(n1609), .Y(n1281) );
BUFX3TS U1596 ( .A(n1281), .Y(n1534) );
OA22X1TS U1597 ( .A0(n1534), .A1(final_result_ieee[27]), .B0(n502), .B1(
n1533), .Y(n266) );
INVX4TS U1598 ( .A(n1355), .Y(n1542) );
CMPR32X2TS U1599 ( .A(n1283), .B(Sgf_operation_EVEN1_Q_right[14]), .C(n1282),
.CO(n1294), .S(n1284) );
AO22XLTS U1600 ( .A0(n1542), .A1(P_Sgf[14]), .B0(n1549), .B1(n1284), .Y(n229) );
CMPR32X2TS U1601 ( .A(n1286), .B(Sgf_operation_EVEN1_Q_right[18]), .C(n1285),
.CO(n1291), .S(n1287) );
AO22XLTS U1602 ( .A0(n1542), .A1(P_Sgf[18]), .B0(n1551), .B1(n1287), .Y(n233) );
CMPR32X2TS U1603 ( .A(n1289), .B(Sgf_operation_EVEN1_Q_right[16]), .C(n1288),
.CO(n1297), .S(n1290) );
AO22XLTS U1604 ( .A0(n1542), .A1(P_Sgf[16]), .B0(n1551), .B1(n1290), .Y(n231) );
AO22XLTS U1605 ( .A0(n1542), .A1(P_Sgf[19]), .B0(n1551), .B1(n1293), .Y(n234) );
CMPR32X2TS U1606 ( .A(n1295), .B(Sgf_operation_EVEN1_Q_right[15]), .C(n1294),
.CO(n1288), .S(n1296) );
AO22XLTS U1607 ( .A0(n1542), .A1(P_Sgf[15]), .B0(n1549), .B1(n1296), .Y(n230) );
AO22XLTS U1608 ( .A0(n1542), .A1(P_Sgf[17]), .B0(n1549), .B1(n1299), .Y(n232) );
NOR4X1TS U1609 ( .A(P_Sgf[13]), .B(P_Sgf[17]), .C(P_Sgf[15]), .D(P_Sgf[16]),
.Y(n1306) );
NOR4X1TS U1610 ( .A(P_Sgf[20]), .B(P_Sgf[18]), .C(P_Sgf[19]), .D(P_Sgf[21]),
.Y(n1305) );
NOR4X1TS U1611 ( .A(P_Sgf[1]), .B(P_Sgf[5]), .C(P_Sgf[3]), .D(P_Sgf[4]), .Y(
n1303) );
NOR3XLTS U1612 ( .A(P_Sgf[22]), .B(P_Sgf[2]), .C(P_Sgf[0]), .Y(n1302) );
NOR4X1TS U1613 ( .A(P_Sgf[9]), .B(P_Sgf[10]), .C(P_Sgf[14]), .D(P_Sgf[12]),
.Y(n1301) );
NOR4X1TS U1614 ( .A(P_Sgf[8]), .B(P_Sgf[6]), .C(P_Sgf[7]), .D(P_Sgf[11]),
.Y(n1300) );
AND4X1TS U1615 ( .A(n1303), .B(n1302), .C(n1301), .D(n1300), .Y(n1304) );
XOR2X1TS U1616 ( .A(Op_MY[31]), .B(Op_MX[31]), .Y(n1358) );
MXI2X1TS U1617 ( .A(round_mode[0]), .B(round_mode[1]), .S0(n1358), .Y(n1307)
);
OAI211X1TS U1618 ( .A0(round_mode[0]), .A1(round_mode[1]), .B0(n1308), .C0(
n1307), .Y(n1429) );
CMPR32X2TS U1619 ( .A(n1311), .B(Sgf_operation_EVEN1_Q_right[20]), .C(n1310),
.CO(n1313), .S(n1312) );
AO22XLTS U1620 ( .A0(n1542), .A1(P_Sgf[20]), .B0(n1551), .B1(n1312), .Y(n235) );
AO22XLTS U1621 ( .A0(n1542), .A1(P_Sgf[21]), .B0(n1551), .B1(n1315), .Y(n236) );
CMPR32X2TS U1622 ( .A(n1317), .B(Sgf_operation_EVEN1_Q_right[22]), .C(n1316),
.CO(n1319), .S(n1318) );
CMPR32X2TS U1623 ( .A(n1323), .B(Sgf_operation_EVEN1_Q_left[0]), .C(n1322),
.CO(n1325), .S(n1324) );
CMPR32X2TS U1624 ( .A(n1326), .B(Sgf_operation_EVEN1_Q_left[1]), .C(n1325),
.CO(n1328), .S(n1327) );
CMPR32X2TS U1625 ( .A(n1329), .B(Sgf_operation_EVEN1_Q_left[2]), .C(n1328),
.CO(n1331), .S(n1330) );
BUFX3TS U1626 ( .A(n1548), .Y(n1550) );
CMPR32X2TS U1627 ( .A(n1338), .B(Sgf_operation_EVEN1_Q_left[7]), .C(n1337),
.CO(n1340), .S(n1339) );
CMPR32X2TS U1628 ( .A(n1344), .B(Sgf_operation_EVEN1_Q_left[9]), .C(n1343),
.CO(n1346), .S(n1345) );
CMPR32X2TS U1629 ( .A(n1350), .B(Sgf_operation_EVEN1_Q_left[11]), .C(n1349),
.CO(n1352), .S(n1351) );
NAND2X1TS U1630 ( .A(n1432), .B(n1356), .Y(n1443) );
NOR2BX1TS U1631 ( .AN(P_Sgf[47]), .B(n1443), .Y(n1360) );
BUFX3TS U1632 ( .A(n1530), .Y(n1527) );
NOR2X1TS U1633 ( .A(n1579), .B(FS_Module_state_reg[2]), .Y(n1434) );
NAND2X1TS U1634 ( .A(n1434), .B(n1357), .Y(n1477) );
OAI211XLTS U1635 ( .A0(n1360), .A1(n1576), .B0(n1527), .C0(n1477), .Y(n309)
);
NOR2XLTS U1636 ( .A(n1358), .B(underflow_flag), .Y(n1359) );
OAI32X1TS U1637 ( .A0(n1553), .A1(n1359), .A2(overflow_flag), .B0(n1534),
.B1(n1610), .Y(n262) );
INVX2TS U1638 ( .A(n1477), .Y(n1476) );
INVX2TS U1639 ( .A(n1360), .Y(n1361) );
OAI31X1TS U1640 ( .A0(n1476), .A1(n1532), .A2(n1577), .B0(n1361), .Y(n308)
);
AOI32X4TS U1641 ( .A0(FSM_add_overflow_flag), .A1(FS_Module_state_reg[1]),
.A2(n1430), .B0(n1362), .B1(FS_Module_state_reg[1]), .Y(n1481) );
OR2X2TS U1642 ( .A(n1481), .B(FSM_selector_C), .Y(n1412) );
AOI22X1TS U1643 ( .A0(n534), .A1(n1479), .B0(n531), .B1(n505), .Y(n1367) );
NAND2X1TS U1644 ( .A(n567), .B(n1481), .Y(n1364) );
NOR2X1TS U1645 ( .A(FSM_selector_C), .B(n1364), .Y(n1363) );
AOI22X1TS U1646 ( .A0(n1414), .A1(P_Sgf[25]), .B0(n1365), .B1(Add_result[2]),
.Y(n1366) );
AOI22X1TS U1647 ( .A0(Sgf_normalized_result[0]), .A1(n1479), .B0(n532), .B1(
n517), .Y(n1369) );
AOI22X1TS U1648 ( .A0(n1414), .A1(P_Sgf[23]), .B0(n1365), .B1(Add_result[0]),
.Y(n1368) );
AOI22X1TS U1649 ( .A0(Sgf_normalized_result[3]), .A1(n1479), .B0(n531), .B1(
n507), .Y(n1371) );
AOI22X1TS U1650 ( .A0(n1414), .A1(P_Sgf[26]), .B0(n1365), .B1(n505), .Y(
n1370) );
AOI22X1TS U1651 ( .A0(Sgf_normalized_result[5]), .A1(n1479), .B0(n519), .B1(
n531), .Y(n1373) );
AOI22X1TS U1652 ( .A0(n1363), .A1(P_Sgf[28]), .B0(n1365), .B1(n506), .Y(
n1372) );
AOI22X1TS U1653 ( .A0(Sgf_normalized_result[1]), .A1(n1479), .B0(n531), .B1(
Add_result[2]), .Y(n1375) );
AOI22X1TS U1654 ( .A0(n1414), .A1(P_Sgf[24]), .B0(n1365), .B1(n517), .Y(
n1374) );
AOI22X1TS U1655 ( .A0(Sgf_normalized_result[4]), .A1(n1409), .B0(n532), .B1(
n506), .Y(n1377) );
AOI22X1TS U1656 ( .A0(n1414), .A1(P_Sgf[27]), .B0(n1365), .B1(n507), .Y(
n1376) );
AOI22X1TS U1657 ( .A0(Sgf_normalized_result[21]), .A1(n1479), .B0(n518),
.B1(n531), .Y(n1379) );
AOI22X1TS U1658 ( .A0(n516), .A1(n548), .B0(n1414), .B1(P_Sgf[44]), .Y(n1378) );
AOI22X1TS U1659 ( .A0(Sgf_normalized_result[17]), .A1(n1479), .B0(n525),
.B1(n531), .Y(n1381) );
AOI22X1TS U1660 ( .A0(n514), .A1(n548), .B0(n1414), .B1(P_Sgf[40]), .Y(n1380) );
AOI22X1TS U1661 ( .A0(Sgf_normalized_result[19]), .A1(n1479), .B0(n526),
.B1(n531), .Y(n1383) );
AOI22X1TS U1662 ( .A0(n515), .A1(n548), .B0(n1414), .B1(P_Sgf[42]), .Y(n1382) );
AOI22X1TS U1663 ( .A0(Sgf_normalized_result[7]), .A1(n1479), .B0(n520), .B1(
n531), .Y(n1385) );
AOI22X1TS U1664 ( .A0(n509), .A1(n548), .B0(n1414), .B1(P_Sgf[30]), .Y(n1384) );
AOI22X1TS U1665 ( .A0(Sgf_normalized_result[15]), .A1(n1409), .B0(n524),
.B1(n532), .Y(n1387) );
AOI22X1TS U1666 ( .A0(n513), .A1(n548), .B0(n533), .B1(P_Sgf[38]), .Y(n1386)
);
AOI22X1TS U1667 ( .A0(Sgf_normalized_result[13]), .A1(n1479), .B0(n523),
.B1(n532), .Y(n1389) );
AOI22X1TS U1668 ( .A0(n512), .A1(n548), .B0(n533), .B1(P_Sgf[36]), .Y(n1388)
);
AOI22X1TS U1669 ( .A0(Sgf_normalized_result[9]), .A1(n1409), .B0(n521), .B1(
n532), .Y(n1391) );
AOI22X1TS U1670 ( .A0(n510), .A1(n548), .B0(n533), .B1(P_Sgf[32]), .Y(n1390)
);
AOI22X1TS U1671 ( .A0(Sgf_normalized_result[11]), .A1(n1409), .B0(n522),
.B1(n532), .Y(n1393) );
AOI22X1TS U1672 ( .A0(n511), .A1(n548), .B0(n533), .B1(P_Sgf[34]), .Y(n1392)
);
AOI22X1TS U1673 ( .A0(Sgf_normalized_result[12]), .A1(n1409), .B0(n512),
.B1(n531), .Y(n1395) );
AOI22X1TS U1674 ( .A0(n522), .A1(n548), .B0(n533), .B1(P_Sgf[35]), .Y(n1394)
);
AOI22X1TS U1675 ( .A0(Sgf_normalized_result[8]), .A1(n1479), .B0(n510), .B1(
n531), .Y(n1397) );
AOI22X1TS U1676 ( .A0(n520), .A1(n1365), .B0(n1414), .B1(P_Sgf[31]), .Y(
n1396) );
AOI22X1TS U1677 ( .A0(Sgf_normalized_result[20]), .A1(n1479), .B0(n516),
.B1(n532), .Y(n1399) );
AOI22X1TS U1678 ( .A0(n526), .A1(n548), .B0(n533), .B1(P_Sgf[43]), .Y(n1398)
);
AOI22X1TS U1679 ( .A0(Sgf_normalized_result[6]), .A1(n1409), .B0(n509), .B1(
n532), .Y(n1401) );
AOI22X1TS U1680 ( .A0(n519), .A1(n548), .B0(n533), .B1(P_Sgf[29]), .Y(n1400)
);
AOI22X1TS U1681 ( .A0(Sgf_normalized_result[10]), .A1(n1409), .B0(n511),
.B1(n532), .Y(n1403) );
AOI22X1TS U1682 ( .A0(n521), .A1(n548), .B0(n533), .B1(P_Sgf[33]), .Y(n1402)
);
AOI22X1TS U1683 ( .A0(Sgf_normalized_result[14]), .A1(n1479), .B0(n513),
.B1(n532), .Y(n1406) );
AOI22X1TS U1684 ( .A0(n523), .A1(n548), .B0(n533), .B1(P_Sgf[37]), .Y(n1405)
);
AOI22X1TS U1685 ( .A0(Sgf_normalized_result[18]), .A1(n1409), .B0(n515),
.B1(n532), .Y(n1408) );
AOI22X1TS U1686 ( .A0(n525), .A1(n548), .B0(n533), .B1(P_Sgf[41]), .Y(n1407)
);
AOI22X1TS U1687 ( .A0(Sgf_normalized_result[16]), .A1(n1479), .B0(n514),
.B1(n532), .Y(n1411) );
AOI22X1TS U1688 ( .A0(n524), .A1(n548), .B0(n533), .B1(P_Sgf[39]), .Y(n1410)
);
AOI22X1TS U1689 ( .A0(FSM_selector_C), .A1(Add_result[23]), .B0(P_Sgf[46]),
.B1(n1581), .Y(n1480) );
AOI22X1TS U1690 ( .A0(Sgf_normalized_result[22]), .A1(n1479), .B0(n518),
.B1(n1365), .Y(n1416) );
NAND2X1TS U1691 ( .A(n533), .B(P_Sgf[45]), .Y(n1415) );
AOI22X1TS U1692 ( .A0(DP_OP_36J18_124_9196_n33), .A1(n1417), .B0(n1569),
.B1(n1609), .Y(n1418) );
OAI22X1TS U1693 ( .A0(n1418), .A1(n1442), .B0(P_Sgf[47]), .B1(n1443), .Y(
n378) );
NOR3BX1TS U1694 ( .AN(Op_MY[30]), .B(FSM_selector_B[0]), .C(
FSM_selector_B[1]), .Y(n1419) );
XOR2X1TS U1695 ( .A(DP_OP_36J18_124_9196_n33), .B(n1419), .Y(
DP_OP_36J18_124_9196_n15) );
OR2X2TS U1696 ( .A(FSM_selector_B[1]), .B(n1576), .Y(n1426) );
OAI2BB1X1TS U1697 ( .A0N(n498), .A1N(n1577), .B0(n1426), .Y(n1420) );
XOR2X1TS U1698 ( .A(DP_OP_36J18_124_9196_n33), .B(n1420), .Y(
DP_OP_36J18_124_9196_n16) );
OAI2BB1X1TS U1699 ( .A0N(n499), .A1N(n1577), .B0(n1426), .Y(n1421) );
XOR2X1TS U1700 ( .A(DP_OP_36J18_124_9196_n33), .B(n1421), .Y(
DP_OP_36J18_124_9196_n17) );
OAI2BB1X1TS U1701 ( .A0N(Op_MY[27]), .A1N(n1577), .B0(n1426), .Y(n1422) );
XOR2X1TS U1702 ( .A(DP_OP_36J18_124_9196_n33), .B(n1422), .Y(
DP_OP_36J18_124_9196_n18) );
OAI2BB1X1TS U1703 ( .A0N(Op_MY[26]), .A1N(n1577), .B0(n1426), .Y(n1423) );
XOR2X1TS U1704 ( .A(DP_OP_36J18_124_9196_n33), .B(n1423), .Y(
DP_OP_36J18_124_9196_n19) );
OAI2BB1X1TS U1705 ( .A0N(n501), .A1N(n1577), .B0(n1426), .Y(n1424) );
XOR2X1TS U1706 ( .A(DP_OP_36J18_124_9196_n33), .B(n1424), .Y(
DP_OP_36J18_124_9196_n20) );
OAI2BB1X1TS U1707 ( .A0N(n500), .A1N(n1577), .B0(n1426), .Y(n1425) );
XOR2X1TS U1708 ( .A(DP_OP_36J18_124_9196_n33), .B(n1425), .Y(
DP_OP_36J18_124_9196_n21) );
NOR2XLTS U1709 ( .A(FSM_selector_B[1]), .B(Op_MY[23]), .Y(n1427) );
XOR2X1TS U1710 ( .A(DP_OP_36J18_124_9196_n33), .B(n1428), .Y(
DP_OP_36J18_124_9196_n22) );
AOI22X1TS U1711 ( .A0(n1432), .A1(n1431), .B0(n1430), .B1(n1429), .Y(n1433)
);
OAI2BB1X1TS U1712 ( .A0N(n1434), .A1N(n1609), .B0(n1433), .Y(n377) );
BUFX3TS U1713 ( .A(n1449), .Y(n1447) );
MX2X1TS U1714 ( .A(Op_MY[23]), .B(Data_MY[23]), .S0(n1435), .Y(n335) );
NAND2X1TS U1715 ( .A(n1477), .B(n1584), .Y(n375) );
NOR2BX1TS U1716 ( .AN(exp_oper_result[8]), .B(n1584), .Y(S_Oper_A_exp[8]) );
MX2X1TS U1717 ( .A(n508), .B(exp_oper_result[7]), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[7]) );
MX2X1TS U1718 ( .A(Op_MX[29]), .B(n503), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[6]) );
MX2X1TS U1719 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(n1436),
.Y(n275) );
MX2X1TS U1720 ( .A(n504), .B(exp_oper_result[5]), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[5]) );
MX2X1TS U1721 ( .A(Exp_module_Data_S[4]), .B(n502), .S0(n1436), .Y(n276) );
MX2X1TS U1722 ( .A(Op_MX[27]), .B(n502), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[4]) );
MX2X1TS U1723 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(n1436),
.Y(n277) );
MX2X1TS U1724 ( .A(Op_MX[26]), .B(exp_oper_result[3]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[3]) );
MX2X1TS U1725 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(n1436),
.Y(n278) );
MX2X1TS U1726 ( .A(Op_MX[25]), .B(exp_oper_result[2]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[2]) );
MX2X1TS U1727 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(n1436),
.Y(n279) );
MX2X1TS U1728 ( .A(Op_MX[24]), .B(exp_oper_result[1]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[1]) );
MX2X1TS U1729 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(n1436),
.Y(n280) );
MX2X1TS U1730 ( .A(Op_MX[23]), .B(exp_oper_result[0]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[0]) );
XNOR2X1TS U1731 ( .A(DP_OP_36J18_124_9196_n1), .B(n1444), .Y(n1438) );
INVX4TS U1732 ( .A(n1550), .Y(n1552) );
NAND4XLTS U1733 ( .A(Exp_module_Data_S[3]), .B(Exp_module_Data_S[2]), .C(
Exp_module_Data_S[1]), .D(Exp_module_Data_S[0]), .Y(n1439) );
NAND4BXLTS U1734 ( .AN(n1439), .B(Exp_module_Data_S[6]), .C(
Exp_module_Data_S[5]), .D(Exp_module_Data_S[4]), .Y(n1440) );
OAI22X1TS U1735 ( .A0(Exp_module_Data_S[8]), .A1(n1441), .B0(n1476), .B1(
n1611), .Y(n272) );
AOI32X1TS U1736 ( .A0(FS_Module_state_reg[1]), .A1(n1569), .A2(
FS_Module_state_reg[0]), .B0(FS_Module_state_reg[2]), .B1(n1442), .Y(
n1445) );
INVX4TS U1737 ( .A(n1452), .Y(n1451) );
AO22XLTS U1738 ( .A0(n1478), .A1(Data_MX[31]), .B0(n1450), .B1(Op_MX[31]),
.Y(n343) );
AO22XLTS U1739 ( .A0(n1454), .A1(Data_MY[3]), .B0(n1452), .B1(Op_MY[3]), .Y(
n315) );
NOR4X1TS U1740 ( .A(n391), .B(n543), .C(Op_MY[16]), .D(Op_MY[17]), .Y(n1457)
);
NAND4XLTS U1741 ( .A(n1458), .B(n1457), .C(n1456), .D(n1455), .Y(n1474) );
NAND4XLTS U1742 ( .A(n1462), .B(n1461), .C(n1460), .D(n1459), .Y(n1473) );
NOR4X1TS U1743 ( .A(Op_MX[27]), .B(Op_MX[26]), .C(Op_MX[23]), .D(Op_MX[25]),
.Y(n1464) );
NOR4X1TS U1744 ( .A(Op_MX[22]), .B(n508), .C(Op_MX[29]), .D(n504), .Y(n1463)
);
NAND4XLTS U1745 ( .A(n1466), .B(n1465), .C(n1464), .D(n1463), .Y(n1472) );
NAND4XLTS U1746 ( .A(n1470), .B(n1469), .C(n1468), .D(n1467), .Y(n1471) );
OAI22X1TS U1747 ( .A0(n1474), .A1(n1473), .B0(n1472), .B1(n1471), .Y(n1475)
);
AO22XLTS U1748 ( .A0(n1478), .A1(Data_MY[31]), .B0(n1452), .B1(Op_MY[31]),
.Y(n310) );
AOI32X1TS U1749 ( .A0(n1481), .A1(n567), .A2(n1480), .B0(n1585), .B1(n1409),
.Y(n307) );
INVX4TS U1750 ( .A(n1527), .Y(n1521) );
AOI2BB2XLTS U1751 ( .B0(n1521), .B1(Sgf_normalized_result[0]), .A0N(
Add_result[0]), .A1N(n1532), .Y(n306) );
NOR2XLTS U1752 ( .A(Sgf_normalized_result[1]), .B(Sgf_normalized_result[0]),
.Y(n1482) );
AOI21X1TS U1753 ( .A0(Sgf_normalized_result[0]), .A1(
Sgf_normalized_result[1]), .B0(n1482), .Y(n1483) );
AOI2BB2XLTS U1754 ( .B0(n1521), .B1(n1483), .A0N(n517), .A1N(n1532), .Y(n305) );
OAI21XLTS U1755 ( .A0(Sgf_normalized_result[1]), .A1(
Sgf_normalized_result[0]), .B0(n534), .Y(n1484) );
AOI32X1TS U1756 ( .A0(n1485), .A1(n1521), .A2(n1484), .B0(n1586), .B1(n1527),
.Y(n304) );
OAI211XLTS U1757 ( .A0(Sgf_normalized_result[3]), .A1(n1485), .B0(n1521),
.C0(n1487), .Y(n1486) );
OAI2BB1X1TS U1758 ( .A0N(n505), .A1N(n1526), .B0(n1486), .Y(n303) );
OAI21XLTS U1759 ( .A0(n1487), .A1(n1570), .B0(n1489), .Y(n1488) );
OAI211XLTS U1760 ( .A0(Sgf_normalized_result[5]), .A1(n1489), .B0(n1521),
.C0(n1491), .Y(n1490) );
OAI2BB1X1TS U1761 ( .A0N(n506), .A1N(n1526), .B0(n1490), .Y(n301) );
AOI21X1TS U1762 ( .A0(n1571), .A1(n1491), .B0(n1493), .Y(n1492) );
OAI211XLTS U1763 ( .A0(Sgf_normalized_result[7]), .A1(n1493), .B0(n1521),
.C0(n1495), .Y(n1494) );
OAI2BB1X1TS U1764 ( .A0N(n509), .A1N(n1527), .B0(n1494), .Y(n299) );
AOI21X1TS U1765 ( .A0(n1572), .A1(n1495), .B0(n1497), .Y(n1496) );
OAI211XLTS U1766 ( .A0(Sgf_normalized_result[9]), .A1(n1497), .B0(n1521),
.C0(n1499), .Y(n1498) );
OAI2BB1X1TS U1767 ( .A0N(n510), .A1N(n1527), .B0(n1498), .Y(n297) );
AOI21X1TS U1768 ( .A0(n1573), .A1(n1499), .B0(n1501), .Y(n1500) );
OAI211XLTS U1769 ( .A0(Sgf_normalized_result[11]), .A1(n1501), .B0(n1521),
.C0(n1503), .Y(n1502) );
OAI2BB1X1TS U1770 ( .A0N(n511), .A1N(n1527), .B0(n1502), .Y(n295) );
AOI21X1TS U1771 ( .A0(n1574), .A1(n1503), .B0(n1505), .Y(n1504) );
OAI211XLTS U1772 ( .A0(Sgf_normalized_result[13]), .A1(n1505), .B0(n1521),
.C0(n1507), .Y(n1506) );
OAI2BB1X1TS U1773 ( .A0N(n512), .A1N(n1526), .B0(n1506), .Y(n293) );
AOI21X1TS U1774 ( .A0(n1575), .A1(n1507), .B0(n1509), .Y(n1508) );
OAI211XLTS U1775 ( .A0(Sgf_normalized_result[15]), .A1(n1509), .B0(n1521),
.C0(n1511), .Y(n1510) );
OAI2BB1X1TS U1776 ( .A0N(n513), .A1N(n1526), .B0(n1510), .Y(n291) );
NOR2X2TS U1777 ( .A(n1578), .B(n1511), .Y(n1513) );
AOI21X1TS U1778 ( .A0(n1578), .A1(n1511), .B0(n1513), .Y(n1512) );
OAI211XLTS U1779 ( .A0(Sgf_normalized_result[17]), .A1(n1513), .B0(n1521),
.C0(n1515), .Y(n1514) );
OAI2BB1X1TS U1780 ( .A0N(n514), .A1N(n1527), .B0(n1514), .Y(n289) );
NOR2X2TS U1781 ( .A(n1580), .B(n1515), .Y(n1517) );
AOI21X1TS U1782 ( .A0(n1580), .A1(n1515), .B0(n1517), .Y(n1516) );
OAI2BB1X1TS U1783 ( .A0N(n515), .A1N(n1527), .B0(n1518), .Y(n287) );
NOR2X2TS U1784 ( .A(n1582), .B(n1519), .Y(n1522) );
AOI21X1TS U1785 ( .A0(n1582), .A1(n1519), .B0(n1522), .Y(n1520) );
OAI2BB1X1TS U1786 ( .A0N(n516), .A1N(n1526), .B0(n1523), .Y(n285) );
NOR2X2TS U1787 ( .A(n1583), .B(n1524), .Y(n1528) );
AOI211X1TS U1788 ( .A0(n1583), .A1(n1524), .B0(n1528), .C0(n1527), .Y(n1525)
);
AOI21X1TS U1789 ( .A0(n1528), .A1(Sgf_normalized_result[23]), .B0(n1527),
.Y(n1531) );
OAI2BB1X1TS U1790 ( .A0N(Add_result[23]), .A1N(n1530), .B0(n1529), .Y(n283)
);
OA22X1TS U1791 ( .A0(n1534), .A1(final_result_ieee[23]), .B0(
exp_oper_result[0]), .B1(n1533), .Y(n270) );
OA22X1TS U1792 ( .A0(n1534), .A1(final_result_ieee[24]), .B0(
exp_oper_result[1]), .B1(n1533), .Y(n269) );
OA22X1TS U1793 ( .A0(n1534), .A1(final_result_ieee[25]), .B0(
exp_oper_result[2]), .B1(n1533), .Y(n268) );
OA22X1TS U1794 ( .A0(n1534), .A1(final_result_ieee[26]), .B0(
exp_oper_result[3]), .B1(n1533), .Y(n267) );
OA22X1TS U1795 ( .A0(n1534), .A1(final_result_ieee[28]), .B0(
exp_oper_result[5]), .B1(n1533), .Y(n265) );
OA22X1TS U1796 ( .A0(n1534), .A1(final_result_ieee[29]), .B0(n503), .B1(
n1533), .Y(n264) );
OA22X1TS U1797 ( .A0(n1534), .A1(final_result_ieee[30]), .B0(
exp_oper_result[7]), .B1(n1533), .Y(n263) );
CMPR32X2TS U1798 ( .A(n1536), .B(Sgf_operation_EVEN1_Q_left[5]), .C(n1535),
.CO(n1334), .S(n1537) );
CMPR32X2TS U1799 ( .A(n1544), .B(Sgf_operation_EVEN1_Q_right[13]), .C(n1543),
.CO(n1282), .S(n1545) );
AO22XLTS U1800 ( .A0(n1552), .A1(P_Sgf[13]), .B0(n1551), .B1(n1545), .Y(n228) );
ADDHXLTS U1801 ( .A(Sgf_operation_EVEN1_Q_right[12]), .B(n1546), .CO(n1543),
.S(n1547) );
AO22XLTS U1802 ( .A0(n1552), .A1(P_Sgf[12]), .B0(n1551), .B1(n1547), .Y(n227) );
AO22XLTS U1803 ( .A0(n1552), .A1(P_Sgf[11]), .B0(n1548), .B1(
Sgf_operation_Result[11]), .Y(n226) );
AO22XLTS U1804 ( .A0(n1552), .A1(P_Sgf[1]), .B0(n1550), .B1(
Sgf_operation_Result[1]), .Y(n216) );
AO22XLTS U1805 ( .A0(n1552), .A1(P_Sgf[0]), .B0(n1551), .B1(
Sgf_operation_Result[0]), .Y(n215) );
AO22XLTS U1806 ( .A0(Sgf_normalized_result[0]), .A1(n1555), .B0(
final_result_ieee[0]), .B1(n1553), .Y(n190) );
CLKBUFX3TS U1807 ( .A(n1553), .Y(n1554) );
AO22XLTS U1808 ( .A0(Sgf_normalized_result[1]), .A1(n1555), .B0(
final_result_ieee[1]), .B1(n1554), .Y(n189) );
AO22XLTS U1809 ( .A0(n534), .A1(n1555), .B0(final_result_ieee[2]), .B1(n1554), .Y(n188) );
AO22XLTS U1810 ( .A0(Sgf_normalized_result[3]), .A1(n1555), .B0(
final_result_ieee[3]), .B1(n1554), .Y(n187) );
AO22XLTS U1811 ( .A0(Sgf_normalized_result[4]), .A1(n1555), .B0(
final_result_ieee[4]), .B1(n1554), .Y(n186) );
AO22XLTS U1812 ( .A0(Sgf_normalized_result[5]), .A1(n1555), .B0(
final_result_ieee[5]), .B1(n1554), .Y(n185) );
AO22XLTS U1813 ( .A0(Sgf_normalized_result[6]), .A1(n1555), .B0(
final_result_ieee[6]), .B1(n1554), .Y(n184) );
AO22XLTS U1814 ( .A0(Sgf_normalized_result[7]), .A1(n1555), .B0(
final_result_ieee[7]), .B1(n1554), .Y(n183) );
AO22XLTS U1815 ( .A0(Sgf_normalized_result[8]), .A1(n1555), .B0(
final_result_ieee[8]), .B1(n1554), .Y(n182) );
AO22XLTS U1816 ( .A0(Sgf_normalized_result[9]), .A1(n1555), .B0(
final_result_ieee[9]), .B1(n1554), .Y(n181) );
AO22XLTS U1817 ( .A0(Sgf_normalized_result[10]), .A1(n1555), .B0(
final_result_ieee[10]), .B1(n1554), .Y(n180) );
AO22XLTS U1818 ( .A0(Sgf_normalized_result[11]), .A1(n1555), .B0(
final_result_ieee[11]), .B1(n1554), .Y(n179) );
AO22XLTS U1819 ( .A0(Sgf_normalized_result[12]), .A1(n1555), .B0(
final_result_ieee[12]), .B1(n1553), .Y(n178) );
INVX2TS U1820 ( .A(n1533), .Y(n1556) );
AO22XLTS U1821 ( .A0(Sgf_normalized_result[13]), .A1(n1556), .B0(
final_result_ieee[13]), .B1(n1553), .Y(n177) );
AO22XLTS U1822 ( .A0(Sgf_normalized_result[14]), .A1(n1556), .B0(
final_result_ieee[14]), .B1(n1553), .Y(n176) );
AO22XLTS U1823 ( .A0(Sgf_normalized_result[15]), .A1(n1556), .B0(
final_result_ieee[15]), .B1(n1553), .Y(n175) );
AO22XLTS U1824 ( .A0(Sgf_normalized_result[16]), .A1(n1556), .B0(
final_result_ieee[16]), .B1(n1553), .Y(n174) );
AO22XLTS U1825 ( .A0(Sgf_normalized_result[17]), .A1(n1556), .B0(
final_result_ieee[17]), .B1(n1553), .Y(n173) );
AO22XLTS U1826 ( .A0(Sgf_normalized_result[18]), .A1(n1556), .B0(
final_result_ieee[18]), .B1(n1553), .Y(n172) );
AO22XLTS U1827 ( .A0(Sgf_normalized_result[19]), .A1(n1556), .B0(
final_result_ieee[19]), .B1(n1553), .Y(n171) );
AO22XLTS U1828 ( .A0(Sgf_normalized_result[20]), .A1(n1556), .B0(
final_result_ieee[20]), .B1(n1553), .Y(n170) );
AO22XLTS U1829 ( .A0(Sgf_normalized_result[21]), .A1(n1556), .B0(
final_result_ieee[21]), .B1(n1553), .Y(n169) );
AO22XLTS U1830 ( .A0(Sgf_normalized_result[22]), .A1(n1556), .B0(
final_result_ieee[22]), .B1(n1553), .Y(n167) );
CMPR42X2TS U1831 ( .A(DP_OP_111J18_123_4462_n133), .B(
DP_OP_111J18_123_4462_n249), .C(DP_OP_111J18_123_4462_n130), .D(
DP_OP_111J18_123_4462_n199), .ICI(DP_OP_111J18_123_4462_n155), .S(
DP_OP_111J18_123_4462_n128), .ICO(DP_OP_111J18_123_4462_n126), .CO(
DP_OP_111J18_123_4462_n127) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_clk20.tcl_KOA_2STAGE_syn.sdf");
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A21O_FUNCTIONAL_PP_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21O_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A311O_FUNCTIONAL_PP_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a311o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311O_FUNCTIONAL_PP_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dramctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dramctl (/*AUTOARG*/
// Outputs
l2if_ucb_trig, dram_sctag_chunk_id, dram_sctag_data_vld,
dram_sctag_rd_req_id, dram_sctag_data, dram_sctag_mecc_err,
dram_sctag_pa_err, dram_sctag_secc_err, dram_sctag_ecc,
dram_sctag_rd_ack, dram_sctag_wr_ack, dram_io_data_out,
dram_io_addr, dram_io_bank, dram_io_cas_l, dram_io_cke,
dram_io_cs_l, dram_io_drive_data, dram_io_drive_enable,
dram_io_ras_l, dram_io_write_en_l, dram_io_pad_enable,
dram_io_clk_enable, dram_io_ptr_clk_inv, dram_io_pad_clk_inv,
dram_io_channel_disabled, dram_ucb_ack_vld, dram_ucb_nack_vld,
dram_ucb_data, l2if_err_intr, dram_local_pt_opened_bank,
que_max_banks_open_valid, que_max_banks_open, que_max_time_valid,
dram_sctag_scb_mecc_err,
dram_sctag_scb_secc_err, que_int_pos, que_int_wr_que_inv_info,
que_ras_int_picked, que_b0_data_addr, que_l2req_valids,
que_b0_addr_picked, que_b0_id_picked, que_b0_index_picked,
que_b0_cmd_picked, que_channel_picked, dp_data_valid_d1,
dram_data_val_other_ch, que_mem_data, dp_data_mecc0,
dp_data_mecc1, dp_data_mecc2, dp_data_mecc3, dp_data_mecc4,
dp_data_mecc5, dp_data_mecc6, dp_data_mecc7, err_syn, err_loc,
que_channel_disabled, l2if_channel_disabled, listen_out,
que_cas_int_picked, que_wr_cas_ch01_picked, que_mux_write_en,
// Inputs
ucb_l2if_selfrsh, dram_dbginit_l, sctag_dram_rd_req,
sctag_dram_rd_dummy_req, sctag_dram_data_vld,
sctag_dram_rd_req_id, sctag_dram_addr, sctag_dram_wr_req,
sctag_dram_wr_data, sctag_dram_data_mecc, cmp_clk, dram_clk,
cmp_rst_l, dram_rst_l, dram_arst_l, io_dram_data_valid, io_dram_data_in,
io_dram_ecc_in, ucb_dram_rd_req_vld, ucb_dram_wr_req_vld,
ucb_dram_addr, ucb_dram_data, pt_ch_blk_new_openbank,
pt_max_banks_open, pt_max_time, dram_dram_rx_sync,
dram_dram_tx_sync, dram_jbus_rx_sync, dram_jbus_tx_sync,
ch0_que_ras_int_picked, ch0_que_b0_data_addr,
ch0_que_channel_picked, ch1_que_l2req_valids,
ch1_que_b0_addr_picked, ch1_que_b0_id_picked,
ch1_que_b0_index_picked, ch1_que_b0_cmd_picked,
ch1_que_int_wr_que_inv_info, other_que_pos,
ch0_dram_data_val_other_ch, ch0_dram_sctag_chunk_id,
ch0_dram_sctag_rd_req_id, ch0_dram_sctag_data, ch0_dram_sctag_ecc,
ch0_dram_sctag_mecc_err, ch0_dram_sctag_pa_err,
ch0_dram_sctag_secc_err, ch0_dp_data_valid_d1, ch0_err_syn,
ch0_err_loc, ch1_que_mem_data, ch1_dp_data_mecc0,
ch1_dp_data_mecc1, ch1_dp_data_mecc2, ch1_dp_data_mecc3,
ch1_dp_data_mecc4, ch1_dp_data_mecc5, ch1_dp_data_mecc6,
ch1_dp_data_mecc7, other_channel_disabled,
other_que_channel_disabled, sehold, mem_bypass,
ch0_que_cas_int_picked, ch0_que_wr_cas_ch01_picked,
ch0_que_mux_write_en
);
// DRAM controller interface
input ucb_l2if_selfrsh;
input dram_dbginit_l;
output l2if_ucb_trig;
// rd interface
input sctag_dram_rd_req;
input sctag_dram_rd_dummy_req;
input sctag_dram_data_vld;
input [2:0] sctag_dram_rd_req_id;
input [39:5] sctag_dram_addr;
// wr interface
input sctag_dram_wr_req;
input [63:0] sctag_dram_wr_data;
input sctag_dram_data_mecc;
// rd interface
output [1:0] dram_sctag_chunk_id;
output dram_sctag_data_vld;
output [2:0] dram_sctag_rd_req_id;
output [127:0] dram_sctag_data;
output dram_sctag_mecc_err;
output dram_sctag_pa_err;
output dram_sctag_secc_err;
output [27:0] dram_sctag_ecc;
output dram_sctag_rd_ack;
// wr interface
output dram_sctag_wr_ack;
input cmp_clk;
input dram_clk;
input cmp_rst_l;
input dram_rst_l;
input dram_arst_l;
// FROM THE PADS
input io_dram_data_valid;
input [255:0] io_dram_data_in;
input [31:0] io_dram_ecc_in;
// TO THE PADS
output [287:0] dram_io_data_out;
output [14:0] dram_io_addr;
output [2:0] dram_io_bank;
output dram_io_cas_l;
output dram_io_cke;
output [3:0] dram_io_cs_l;
output dram_io_drive_data;
output dram_io_drive_enable;
output dram_io_ras_l;
output dram_io_write_en_l;
output dram_io_pad_enable;
output dram_io_clk_enable;
output [4:0] dram_io_ptr_clk_inv;
output dram_io_pad_clk_inv;
output dram_io_channel_disabled;
// FROM UCB
input ucb_dram_rd_req_vld;
input ucb_dram_wr_req_vld;
input [31:0] ucb_dram_addr;
input [63:0] ucb_dram_data;
// TO UCB
output dram_ucb_ack_vld;
output dram_ucb_nack_vld;
output [63:0] dram_ucb_data;
output l2if_err_intr;
// FROM POWER THROTTLE
output dram_local_pt_opened_bank;
output que_max_banks_open_valid;
output [16:0] que_max_banks_open;
output que_max_time_valid;
input pt_ch_blk_new_openbank;
input [16:0] pt_max_banks_open;
input [15:0] pt_max_time;
// Async scrub error signals
output dram_sctag_scb_mecc_err;
output dram_sctag_scb_secc_err;
// SYNC Pulse
input dram_dram_rx_sync;
input dram_dram_tx_sync;
input dram_jbus_rx_sync;
input dram_jbus_tx_sync;
// NEW ADDITION DUE TO 2 CHANNEL MODE
input [7:0] ch0_que_ras_int_picked;
input [5:0] ch0_que_b0_data_addr;
input ch0_que_channel_picked;
input [7:0] ch1_que_l2req_valids;
input [35:0] ch1_que_b0_addr_picked;
input [2:0] ch1_que_b0_id_picked;
input [2:0] ch1_que_b0_index_picked;
input ch1_que_b0_cmd_picked;
input [6:0] ch1_que_int_wr_que_inv_info;
input [4:0] other_que_pos;
output [4:0] que_int_pos;
output [6:0] que_int_wr_que_inv_info;
output [7:0] que_ras_int_picked;
output [5:0] que_b0_data_addr;
output [7:0] que_l2req_valids;
output [35:0] que_b0_addr_picked;
output [2:0] que_b0_id_picked;
output [2:0] que_b0_index_picked;
output que_b0_cmd_picked;
output que_channel_picked;
output dp_data_valid_d1;
// NEW ADDITION DUE TO 2 CHANNEL MODE
output dram_data_val_other_ch;
input ch0_dram_data_val_other_ch;
input [1:0] ch0_dram_sctag_chunk_id;
input [2:0] ch0_dram_sctag_rd_req_id;
input [127:0] ch0_dram_sctag_data;
input [27:0] ch0_dram_sctag_ecc;
input ch0_dram_sctag_mecc_err;
input ch0_dram_sctag_pa_err;
input ch0_dram_sctag_secc_err;
input ch0_dp_data_valid_d1;
input [15:0] ch0_err_syn;
input [35:0] ch0_err_loc;
input [255:0] ch1_que_mem_data;
output [255:0] que_mem_data;
input [3:0] ch1_dp_data_mecc0;
input [3:0] ch1_dp_data_mecc1;
input [3:0] ch1_dp_data_mecc2;
input [3:0] ch1_dp_data_mecc3;
input [3:0] ch1_dp_data_mecc4;
input [3:0] ch1_dp_data_mecc5;
input [3:0] ch1_dp_data_mecc6;
input [3:0] ch1_dp_data_mecc7;
output [3:0] dp_data_mecc0;
output [3:0] dp_data_mecc1;
output [3:0] dp_data_mecc2;
output [3:0] dp_data_mecc3;
output [3:0] dp_data_mecc4;
output [3:0] dp_data_mecc5;
output [3:0] dp_data_mecc6;
output [3:0] dp_data_mecc7;
output [15:0] err_syn;
output [35:0] err_loc;
input other_channel_disabled;
input other_que_channel_disabled;
output que_channel_disabled;
output l2if_channel_disabled;
// MEM RELATED
output [64:0] listen_out;
input sehold;
input mem_bypass;
// FOR PERF
input [7:0] ch0_que_cas_int_picked;
input ch0_que_wr_cas_ch01_picked;
input ch0_que_mux_write_en;
output [7:0] que_cas_int_picked;
output que_wr_cas_ch01_picked;
output que_mux_write_en;
//////////////////////////////////////////////////////////////////
// Wires
//////////////////////////////////////////////////////////////////
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [8:0] config_reg; // From dram_dctl of dram_dctl.v
wire [255:0] dp_data_in; // From dram_dctl of dram_dctl.v
wire dp_data_valid; // From dram_dctl of dram_dctl.v
wire [31:0] dp_ecc_in; // From dram_dctl of dram_dctl.v
wire [3:0] dram_cpu_wr_addr; // From dram_l2if of dram_l2if.v
wire [63:0] dram_cpu_wr_data; // From dram_l2if of dram_l2if.v
wire [3:0] dram_cpu_wr_en; // From dram_l2if of dram_l2if.v
wire dram_fail_over_mode; // From dram_dctl of dram_dctl.v
wire [3:0] l2if_data_mecc0; // From dram_l2if of dram_l2if.v
wire [3:0] l2if_data_mecc1; // From dram_l2if of dram_l2if.v
wire [3:0] l2if_data_mecc2; // From dram_l2if of dram_l2if.v
wire [3:0] l2if_data_mecc3; // From dram_l2if of dram_l2if.v
wire [3:0] l2if_data_mecc4; // From dram_l2if of dram_l2if.v
wire [3:0] l2if_data_mecc5; // From dram_l2if of dram_l2if.v
wire [3:0] l2if_data_mecc6; // From dram_l2if of dram_l2if.v
wire [3:0] l2if_data_mecc7; // From dram_l2if of dram_l2if.v
wire [2:0] l2if_data_wr_addr; // From dram_l2if of dram_l2if.v
wire l2if_dbg_trig_en; // From dram_l2if of dram_l2if.v
wire [35:0] l2if_err_addr_reg; // From dram_l2if of dram_l2if.v
wire [17:0] l2if_err_cnt; // From dram_l2if of dram_l2if.v
wire [35:0] l2if_err_loc; // From dram_l2if of dram_l2if.v
wire [22:0] l2if_err_sts_reg; // From dram_l2if of dram_l2if.v
wire [31:0] l2if_que_addr; // From dram_l2if of dram_l2if.v
wire [63:0] l2if_que_data; // From dram_l2if of dram_l2if.v
wire l2if_que_rd_req_vld; // From dram_l2if of dram_l2if.v
wire l2if_que_wr_req_vld; // From dram_l2if of dram_l2if.v
wire [35:0] l2if_rd_addr; // From dram_l2if of dram_l2if.v
wire [2:0] l2if_rd_id; // From dram_l2if of dram_l2if.v
wire l2if_rd_req; // From dram_l2if of dram_l2if.v
wire [255:0] l2if_scrb_data; // From dram_l2if of dram_l2if.v
wire l2if_scrb_data_en; // From dram_l2if of dram_l2if.v
wire [33:0] l2if_scrb_ecc; // From dram_l2if of dram_l2if.v
wire [35:0] l2if_wr_addr; // From dram_l2if of dram_l2if.v
wire l2if_wr_req; // From dram_l2if of dram_l2if.v
wire que_addr_bank_low_sel; // From dram_dctl of dram_dctl.v
wire que_dram_clk_toggle; // From dram_dctl of dram_dctl.v
wire que_eight_bank_mode; // From dram_dctl of dram_dctl.v
wire que_l2if_ack_vld; // From dram_dctl of dram_dctl.v
wire [63:0] que_l2if_data; // From dram_dctl of dram_dctl.v
wire que_l2if_nack_vld; // From dram_dctl of dram_dctl.v
wire [9:0] que_l2if_send_info; // From dram_dctl of dram_dctl.v
wire [4:0] que_margin_reg; // From dram_dctl of dram_dctl.v
wire [4:0] que_mem_addr; // From dram_dctl of dram_dctl.v
wire que_rank1_present; // From dram_dctl of dram_dctl.v
wire [32:0] que_scrb_addr; // From dram_dctl of dram_dctl.v
wire [3:0] que_wr_entry_free; // From dram_dctl of dram_dctl.v
wire que_wr_req; // From dram_dctl of dram_dctl.v
wire readqbank0vld0; // From dram_dctl of dram_dctl.v
wire readqbank0vld1; // From dram_dctl of dram_dctl.v
wire readqbank0vld2; // From dram_dctl of dram_dctl.v
wire readqbank0vld3; // From dram_dctl of dram_dctl.v
wire readqbank0vld4; // From dram_dctl of dram_dctl.v
wire readqbank0vld5; // From dram_dctl of dram_dctl.v
wire readqbank0vld6; // From dram_dctl of dram_dctl.v
wire readqbank0vld7; // From dram_dctl of dram_dctl.v
wire writeqbank0vld0; // From dram_dctl of dram_dctl.v
wire writeqbank0vld1; // From dram_dctl of dram_dctl.v
wire writeqbank0vld2; // From dram_dctl of dram_dctl.v
wire writeqbank0vld3; // From dram_dctl of dram_dctl.v
wire writeqbank0vld4; // From dram_dctl of dram_dctl.v
wire writeqbank0vld5; // From dram_dctl of dram_dctl.v
wire writeqbank0vld6; // From dram_dctl of dram_dctl.v
wire writeqbank0vld7; // From dram_dctl of dram_dctl.v
// End of automatics
/*dram_l2if AUTO_TEMPLATE( .clk(cmp_clk),
.arst_l(dram_arst_l),
.rst_l(cmp_rst_l)); */
dram_l2if dram_l2if(/*AUTOINST*/
// Outputs
.dram_ucb_ack_vld (dram_ucb_ack_vld),
.dram_ucb_nack_vld (dram_ucb_nack_vld),
.dram_ucb_data (dram_ucb_data[63:0]),
.l2if_que_rd_req_vld(l2if_que_rd_req_vld),
.l2if_que_wr_req_vld(l2if_que_wr_req_vld),
.l2if_que_addr (l2if_que_addr[31:0]),
.l2if_que_data (l2if_que_data[63:0]),
.dram_sctag_chunk_id(dram_sctag_chunk_id[1:0]),
.dram_sctag_data_vld(dram_sctag_data_vld),
.dram_sctag_rd_req_id(dram_sctag_rd_req_id[2:0]),
.dram_sctag_data (dram_sctag_data[127:0]),
.dram_sctag_mecc_err(dram_sctag_mecc_err),
.dram_sctag_pa_err (dram_sctag_pa_err),
.dram_sctag_secc_err(dram_sctag_secc_err),
.dram_sctag_ecc (dram_sctag_ecc[27:0]),
.dram_sctag_rd_ack (dram_sctag_rd_ack),
.dram_sctag_wr_ack (dram_sctag_wr_ack),
.l2if_data_mecc0 (l2if_data_mecc0[3:0]),
.l2if_data_mecc1 (l2if_data_mecc1[3:0]),
.l2if_data_mecc2 (l2if_data_mecc2[3:0]),
.l2if_data_mecc3 (l2if_data_mecc3[3:0]),
.l2if_data_mecc4 (l2if_data_mecc4[3:0]),
.l2if_data_mecc5 (l2if_data_mecc5[3:0]),
.l2if_data_mecc6 (l2if_data_mecc6[3:0]),
.l2if_data_mecc7 (l2if_data_mecc7[3:0]),
.l2if_data_wr_addr (l2if_data_wr_addr[2:0]),
.dram_cpu_wr_addr (dram_cpu_wr_addr[3:0]),
.dram_cpu_wr_en (dram_cpu_wr_en[3:0]),
.dram_cpu_wr_data (dram_cpu_wr_data[63:0]),
.l2if_wr_req (l2if_wr_req),
.l2if_rd_req (l2if_rd_req),
.l2if_rd_addr (l2if_rd_addr[35:0]),
.l2if_wr_addr (l2if_wr_addr[35:0]),
.l2if_rd_id (l2if_rd_id[2:0]),
.l2if_scrb_data_en (l2if_scrb_data_en),
.l2if_scrb_data (l2if_scrb_data[255:0]),
.l2if_scrb_ecc (l2if_scrb_ecc[33:0]),
.l2if_err_loc (l2if_err_loc[35:0]),
.l2if_err_cnt (l2if_err_cnt[17:0]),
.l2if_dbg_trig_en (l2if_dbg_trig_en),
.l2if_err_intr (l2if_err_intr),
.dram_sctag_scb_mecc_err(dram_sctag_scb_mecc_err),
.dram_sctag_scb_secc_err(dram_sctag_scb_secc_err),
.l2if_err_addr_reg (l2if_err_addr_reg[35:0]),
.l2if_err_sts_reg (l2if_err_sts_reg[22:0]),
.dram_data_val_other_ch(dram_data_val_other_ch),
.dp_data_valid_d1 (dp_data_valid_d1),
.l2if_channel_disabled(l2if_channel_disabled),
.err_loc (err_loc[35:0]),
.err_syn (err_syn[15:0]),
.l2if_ucb_trig (l2if_ucb_trig),
.l2if_que_selfrsh (l2if_que_selfrsh),
// Inputs
.clk (cmp_clk), // Templated
.rst_l (cmp_rst_l), // Templated
.arst_l (dram_arst_l), // Templated
.ucb_l2if_selfrsh (ucb_l2if_selfrsh),
.sctag_dram_rd_req (sctag_dram_rd_req),
.sctag_dram_rd_dummy_req(sctag_dram_rd_dummy_req),
.sctag_dram_rd_req_id(sctag_dram_rd_req_id[2:0]),
.sctag_dram_addr (sctag_dram_addr[39:5]),
.sctag_dram_wr_req (sctag_dram_wr_req),
.sctag_dram_data_vld(sctag_dram_data_vld),
.sctag_dram_wr_data (sctag_dram_wr_data[63:0]),
.sctag_dram_data_mecc(sctag_dram_data_mecc),
.readqbank0vld0 (readqbank0vld0),
.readqbank0vld1 (readqbank0vld1),
.readqbank0vld2 (readqbank0vld2),
.readqbank0vld3 (readqbank0vld3),
.writeqbank0vld0 (writeqbank0vld0),
.writeqbank0vld1 (writeqbank0vld1),
.writeqbank0vld2 (writeqbank0vld2),
.writeqbank0vld3 (writeqbank0vld3),
.readqbank0vld4 (readqbank0vld4),
.readqbank0vld5 (readqbank0vld5),
.readqbank0vld6 (readqbank0vld6),
.readqbank0vld7 (readqbank0vld7),
.writeqbank0vld4 (writeqbank0vld4),
.writeqbank0vld5 (writeqbank0vld5),
.writeqbank0vld6 (writeqbank0vld6),
.writeqbank0vld7 (writeqbank0vld7),
.que_wr_req (que_wr_req),
.que_scrb_addr (que_scrb_addr[32:0]),
.dram_fail_over_mode(dram_fail_over_mode),
.que_wr_entry_free (que_wr_entry_free[3:0]),
.config_reg (config_reg[8:0]),
.que_rank1_present (que_rank1_present),
.ucb_dram_rd_req_vld(ucb_dram_rd_req_vld),
.ucb_dram_wr_req_vld(ucb_dram_wr_req_vld),
.ucb_dram_addr (ucb_dram_addr[31:0]),
.ucb_dram_data (ucb_dram_data[63:0]),
.que_eight_bank_mode(que_eight_bank_mode),
.que_l2if_ack_vld (que_l2if_ack_vld),
.que_l2if_nack_vld (que_l2if_nack_vld),
.que_l2if_data (que_l2if_data[63:0]),
.que_dram_clk_toggle(que_dram_clk_toggle),
.dp_data_valid (dp_data_valid),
.que_l2if_send_info (que_l2if_send_info[9:0]),
.dp_data_in (dp_data_in[255:0]),
.dp_ecc_in (dp_ecc_in[31:0]),
.dram_dram_rx_sync (dram_dram_rx_sync),
.dram_dram_tx_sync (dram_dram_tx_sync),
.dram_jbus_rx_sync (dram_jbus_rx_sync),
.dram_jbus_tx_sync (dram_jbus_tx_sync),
.que_addr_bank_low_sel(que_addr_bank_low_sel),
.que_channel_disabled(que_channel_disabled),
.other_channel_disabled(other_channel_disabled),
.ch0_err_loc (ch0_err_loc[35:0]),
.ch0_err_syn (ch0_err_syn[15:0]),
.ch0_dp_data_valid_d1(ch0_dp_data_valid_d1),
.ch0_dram_data_val_other_ch(ch0_dram_data_val_other_ch),
.ch0_dram_sctag_chunk_id(ch0_dram_sctag_chunk_id[1:0]),
.ch0_dram_sctag_rd_req_id(ch0_dram_sctag_rd_req_id[2:0]),
.ch0_dram_sctag_data(ch0_dram_sctag_data[127:0]),
.ch0_dram_sctag_ecc (ch0_dram_sctag_ecc[27:0]),
.ch0_dram_sctag_mecc_err(ch0_dram_sctag_mecc_err),
.ch0_dram_sctag_pa_err(ch0_dram_sctag_pa_err),
.ch0_dram_sctag_secc_err(ch0_dram_sctag_secc_err));
/*dram_dctl AUTO_TEMPLATE( .clk(dram_clk),
.arst_l(dram_arst_l),
.rst_l(dram_rst_l)); */
dram_dctl dram_dctl(/*AUTOINST*/
// Outputs
.que_margin_reg(que_margin_reg[4:0]),
.readqbank0vld0(readqbank0vld0),
.readqbank0vld1(readqbank0vld1),
.readqbank0vld2(readqbank0vld2),
.readqbank0vld3(readqbank0vld3),
.writeqbank0vld0(writeqbank0vld0),
.writeqbank0vld1(writeqbank0vld1),
.writeqbank0vld2(writeqbank0vld2),
.writeqbank0vld3(writeqbank0vld3),
.readqbank0vld4(readqbank0vld4),
.readqbank0vld5(readqbank0vld5),
.readqbank0vld6(readqbank0vld6),
.readqbank0vld7(readqbank0vld7),
.writeqbank0vld4(writeqbank0vld4),
.writeqbank0vld5(writeqbank0vld5),
.writeqbank0vld6(writeqbank0vld6),
.writeqbank0vld7(writeqbank0vld7),
.que_wr_req (que_wr_req),
.dp_data_in (dp_data_in[255:0]),
.dp_ecc_in (dp_ecc_in[31:0]),
.que_scrb_addr(que_scrb_addr[32:0]),
.dram_fail_over_mode(dram_fail_over_mode),
.que_wr_entry_free(que_wr_entry_free[3:0]),
.config_reg (config_reg[8:0]),
.que_rank1_present(que_rank1_present),
.que_addr_bank_low_sel(que_addr_bank_low_sel),
.que_eight_bank_mode(que_eight_bank_mode),
.que_mem_addr (que_mem_addr[4:0]),
.dram_io_data_out(dram_io_data_out[287:0]),
.dram_io_addr (dram_io_addr[14:0]),
.dram_io_bank (dram_io_bank[2:0]),
.dram_io_cas_l(dram_io_cas_l),
.dram_io_cke (dram_io_cke),
.dram_io_cs_l (dram_io_cs_l[3:0]),
.dram_io_drive_data(dram_io_drive_data),
.dram_io_drive_enable(dram_io_drive_enable),
.dram_io_ras_l(dram_io_ras_l),
.dram_io_write_en_l(dram_io_write_en_l),
.dram_io_pad_enable(dram_io_pad_enable),
.dram_io_clk_enable(dram_io_clk_enable),
.dram_io_pad_clk_inv(dram_io_pad_clk_inv),
.dram_io_ptr_clk_inv(dram_io_ptr_clk_inv[4:0]),
.dram_io_channel_disabled(dram_io_channel_disabled),
.que_l2if_ack_vld(que_l2if_ack_vld),
.que_l2if_nack_vld(que_l2if_nack_vld),
.que_l2if_data(que_l2if_data[63:0]),
.que_dram_clk_toggle(que_dram_clk_toggle),
.dp_data_valid(dp_data_valid),
.que_l2if_send_info(que_l2if_send_info[9:0]),
.dram_local_pt_opened_bank(dram_local_pt_opened_bank),
.que_max_banks_open_valid(que_max_banks_open_valid),
.que_max_banks_open(que_max_banks_open[16:0]),
.que_max_time_valid(que_max_time_valid),
.que_int_wr_que_inv_info(que_int_wr_que_inv_info[6:0]),
.que_ras_int_picked(que_ras_int_picked[7:0]),
.que_b0_data_addr(que_b0_data_addr[5:0]),
.que_l2req_valids(que_l2req_valids[7:0]),
.que_b0_addr_picked(que_b0_addr_picked[35:0]),
.que_b0_id_picked(que_b0_id_picked[2:0]),
.que_b0_index_picked(que_b0_index_picked[2:0]),
.que_b0_cmd_picked(que_b0_cmd_picked),
.que_channel_picked(que_channel_picked),
.que_int_pos (que_int_pos[4:0]),
.que_channel_disabled(que_channel_disabled),
.dp_data_mecc0(dp_data_mecc0[3:0]),
.dp_data_mecc1(dp_data_mecc1[3:0]),
.dp_data_mecc2(dp_data_mecc2[3:0]),
.dp_data_mecc3(dp_data_mecc3[3:0]),
.dp_data_mecc4(dp_data_mecc4[3:0]),
.dp_data_mecc5(dp_data_mecc5[3:0]),
.dp_data_mecc6(dp_data_mecc6[3:0]),
.dp_data_mecc7(dp_data_mecc7[3:0]),
.que_cas_int_picked(que_cas_int_picked[7:0]),
.que_wr_cas_ch01_picked(que_wr_cas_ch01_picked),
.que_mux_write_en(que_mux_write_en),
// Inputs
.clk (dram_clk), // Templated
.rst_l (dram_rst_l), // Templated
.arst_l (dram_arst_l), // Templated
.sehold (sehold),
.l2if_que_selfrsh(l2if_que_selfrsh),
.dram_dbginit_l(dram_dbginit_l),
.l2if_data_mecc0(l2if_data_mecc0[3:0]),
.l2if_data_mecc1(l2if_data_mecc1[3:0]),
.l2if_data_mecc2(l2if_data_mecc2[3:0]),
.l2if_data_mecc3(l2if_data_mecc3[3:0]),
.l2if_data_mecc4(l2if_data_mecc4[3:0]),
.l2if_data_mecc5(l2if_data_mecc5[3:0]),
.l2if_data_mecc6(l2if_data_mecc6[3:0]),
.l2if_data_mecc7(l2if_data_mecc7[3:0]),
.l2if_rd_id (l2if_rd_id[2:0]),
.l2if_rd_addr (l2if_rd_addr[35:0]),
.l2if_wr_addr (l2if_wr_addr[35:0]),
.l2if_wr_req (l2if_wr_req),
.l2if_rd_req (l2if_rd_req),
.l2if_dbg_trig_en(l2if_dbg_trig_en),
.l2if_data_wr_addr(l2if_data_wr_addr[2:0]),
.l2if_err_addr_reg(l2if_err_addr_reg[35:0]),
.l2if_err_sts_reg(l2if_err_sts_reg[22:0]),
.l2if_err_loc (l2if_err_loc[35:0]),
.l2if_err_cnt (l2if_err_cnt[17:0]),
.que_mem_data (que_mem_data[255:0]),
.io_dram_data_valid(io_dram_data_valid),
.io_dram_data_in(io_dram_data_in[255:0]),
.io_dram_ecc_in(io_dram_ecc_in[31:0]),
.l2if_que_rd_req_vld(l2if_que_rd_req_vld),
.l2if_que_wr_req_vld(l2if_que_wr_req_vld),
.l2if_que_addr(l2if_que_addr[31:0]),
.l2if_que_data(l2if_que_data[63:0]),
.l2if_scrb_data_en(l2if_scrb_data_en),
.l2if_scrb_data(l2if_scrb_data[255:0]),
.l2if_scrb_ecc(l2if_scrb_ecc[33:0]),
.pt_ch_blk_new_openbank(pt_ch_blk_new_openbank),
.pt_max_banks_open(pt_max_banks_open[16:0]),
.pt_max_time (pt_max_time[15:0]),
.ch0_que_ras_int_picked(ch0_que_ras_int_picked[7:0]),
.ch0_que_b0_data_addr(ch0_que_b0_data_addr[5:0]),
.ch0_que_channel_picked(ch0_que_channel_picked),
.ch1_que_l2req_valids(ch1_que_l2req_valids[7:0]),
.ch1_que_b0_addr_picked(ch1_que_b0_addr_picked[35:0]),
.ch1_que_b0_id_picked(ch1_que_b0_id_picked[2:0]),
.ch1_que_b0_index_picked(ch1_que_b0_index_picked[2:0]),
.ch1_que_b0_cmd_picked(ch1_que_b0_cmd_picked),
.other_que_channel_disabled(other_que_channel_disabled),
.ch1_que_int_wr_que_inv_info(ch1_que_int_wr_que_inv_info[6:0]),
.other_que_pos(other_que_pos[4:0]),
.ch1_que_mem_data(ch1_que_mem_data[255:0]),
.ch1_dp_data_mecc0(ch1_dp_data_mecc0[3:0]),
.ch1_dp_data_mecc1(ch1_dp_data_mecc1[3:0]),
.ch1_dp_data_mecc2(ch1_dp_data_mecc2[3:0]),
.ch1_dp_data_mecc3(ch1_dp_data_mecc3[3:0]),
.ch1_dp_data_mecc4(ch1_dp_data_mecc4[3:0]),
.ch1_dp_data_mecc5(ch1_dp_data_mecc5[3:0]),
.ch1_dp_data_mecc6(ch1_dp_data_mecc6[3:0]),
.ch1_dp_data_mecc7(ch1_dp_data_mecc7[3:0]),
.ch0_que_cas_int_picked(ch0_que_cas_int_picked[7:0]),
.ch0_que_wr_cas_ch01_picked(ch0_que_wr_cas_ch01_picked),
.ch0_que_mux_write_en(ch0_que_mux_write_en));
/*dram_mem AUTO_TEMPLATE( .clk(cmp_clk),
.margin(que_margin_reg[4:0])); */
dram_mem dram_mem(/*AUTOINST*/
// Outputs
.que_mem_data (que_mem_data[255:0]),
.listen_out (listen_out[64:0]),
// Inputs
.que_mem_addr (que_mem_addr[4:0]),
.dram_cpu_wr_addr(dram_cpu_wr_addr[3:0]),
.dram_cpu_wr_data(dram_cpu_wr_data[63:0]),
.dram_clk (dram_clk),
.clk (cmp_clk), // Templated
.dram_cpu_wr_en(dram_cpu_wr_en[3:0]),
.margin (que_margin_reg[4:0]), // Templated
.sehold (sehold),
.mem_bypass (mem_bypass));
endmodule // dramctl
|
(* Default settings (from HsToCoq.Coq.Preamble) *)
Generalizable All Variables.
Unset Implicit Arguments.
Set Maximal Implicit Insertion.
Unset Strict Implicit.
Unset Printing Implicit Defensive.
Require Coq.Program.Tactics.
Require Coq.Program.Wf.
(* Converted imports: *)
Require Data.Function.
Require Datatypes.
Require FastString.
Require GHC.Base.
Require GHC.Err.
Require GHC.Num.
Require GHC.Prim.
Require GHC.Real.
Require Panic.
Require SrcLoc.
Import GHC.Base.Notations.
Import GHC.Num.Notations.
(* Converted type declarations: *)
Definition Version :=
GHC.Num.Int%type.
Inductive TyPrec : Type
:= | TopPrec : TyPrec
| FunPrec : TyPrec
| TyOpPrec : TyPrec
| TyConPrec : TyPrec.
Inductive TupleSort : Type
:= | BoxedTuple : TupleSort
| UnboxedTuple : TupleSort
| ConstraintTuple : TupleSort.
Inductive TopLevelFlag : Type
:= | TopLevel : TopLevelFlag
| NotTopLevel : TopLevelFlag.
Inductive SwapFlag : Type := | NotSwapped : SwapFlag | IsSwapped : SwapFlag.
Inductive SuccessFlag : Type
:= | Succeeded : SuccessFlag
| Failed : SuccessFlag.
Inductive SpliceExplicitFlag : Type
:= | ExplicitSplice : SpliceExplicitFlag
| ImplicitSplice : SpliceExplicitFlag.
Inductive SourceText : Type
:= | Mk_SourceText : GHC.Base.String -> SourceText
| NoSourceText : SourceText.
Inductive StringLiteral : Type
:= | Mk_StringLiteral (sl_st : SourceText) (sl_fs : FastString.FastString)
: StringLiteral.
Inductive WarningTxt : Type
:= | Mk_WarningTxt
: (SrcLoc.Located SourceText) ->
list (SrcLoc.Located StringLiteral) -> WarningTxt
| DeprecatedTxt
: (SrcLoc.Located SourceText) ->
list (SrcLoc.Located StringLiteral) -> WarningTxt.
Definition RulesOnly :=
bool%type.
Definition RuleName :=
FastString.FastString%type.
Inductive RuleMatchInfo : Type
:= | ConLike : RuleMatchInfo
| FunLike : RuleMatchInfo.
Definition RepArity :=
nat.
Inductive RecFlag : Type := | Recursive : RecFlag | NonRecursive : RecFlag.
Definition PhaseNum :=
nat.
Inductive OverlapMode : Type
:= | NoOverlap : SourceText -> OverlapMode
| Overlappable : SourceText -> OverlapMode
| Overlapping : SourceText -> OverlapMode
| Overlaps : SourceText -> OverlapMode
| Incoherent : SourceText -> OverlapMode.
Inductive OverlapFlag : Type
:= | Mk_OverlapFlag (overlapMode : OverlapMode) (isSafeOverlap : bool)
: OverlapFlag.
Inductive Origin : Type := | FromSource : Origin | Generated : Origin.
Inductive OneShotInfo : Type
:= | NoOneShotInfo : OneShotInfo
| OneShotLam : OneShotInfo.
Definition OneBranch :=
bool%type.
Inductive LexicalFixity : Type
:= | Prefix : LexicalFixity
| Infix : LexicalFixity.
Inductive LeftOrRight : Type := | CLeft : LeftOrRight | CRight : LeftOrRight.
Definition JoinArity :=
nat.
Inductive TailCallInfo : Type
:= | AlwaysTailCalled : JoinArity -> TailCallInfo
| NoTailCallInfo : TailCallInfo.
Definition InterestingCxt :=
bool%type.
Inductive IntegralLit : Type
:= | IL (il_text : SourceText) (il_neg : bool) (il_value : GHC.Num.Integer)
: IntegralLit.
Inductive IntWithInf : Type
:= | Int : GHC.Num.Int -> IntWithInf
| Infinity : IntWithInf.
Definition InsideLam :=
bool%type.
Inductive OccInfo : Type
:= | ManyOccs (occ_tail : TailCallInfo) : OccInfo
| IAmDead : OccInfo
| OneOcc (occ_in_lam : InsideLam) (occ_one_br : OneBranch) (occ_int_cxt
: InterestingCxt) (occ_tail : TailCallInfo)
: OccInfo
| IAmALoopBreaker (occ_rules_only : RulesOnly) (occ_tail : TailCallInfo)
: OccInfo.
Inductive InlineSpec : Type
:= | Inline : InlineSpec
| Inlinable : InlineSpec
| NoInline : InlineSpec
| NoUserInline : InlineSpec.
Inductive FunctionOrData : Type
:= | IsFunction : FunctionOrData
| IsData : FunctionOrData.
Inductive FractionalLit : Type
:= | FL (fl_text : SourceText) (fl_neg : bool) (fl_value : GHC.Real.Rational)
: FractionalLit.
Inductive FixityDirection : Type
:= | InfixL : FixityDirection
| InfixR : FixityDirection
| InfixN : FixityDirection.
Inductive Fixity : Type
:= | Mk_Fixity : SourceText -> GHC.Num.Int -> FixityDirection -> Fixity.
Inductive EP a : Type := | Mk_EP (fromEP : a) (toEP : a) : EP a.
Inductive DerivStrategy : Type
:= | StockStrategy : DerivStrategy
| AnyclassStrategy : DerivStrategy
| NewtypeStrategy : DerivStrategy.
Inductive DefMethSpec ty : Type
:= | VanillaDM : DefMethSpec ty
| GenericDM : ty -> DefMethSpec ty.
Definition ConTagZ :=
GHC.Num.Int%type.
Definition ConTag :=
GHC.Num.Int%type.
Inductive CompilerPhase : Type
:= | Phase : PhaseNum -> CompilerPhase
| InitialPhase : CompilerPhase.
Inductive Boxity : Type := | Boxed : Boxity | Unboxed : Boxity.
Definition Arity :=
nat.
Definition Alignment :=
GHC.Num.Int%type.
Inductive Activation : Type
:= | NeverActive : Activation
| AlwaysActive : Activation
| ActiveBefore : SourceText -> PhaseNum -> Activation
| ActiveAfter : SourceText -> PhaseNum -> Activation.
Inductive InlinePragma : Type
:= | Mk_InlinePragma (inl_src : SourceText) (inl_inline : InlineSpec) (inl_sat
: option Arity) (inl_act : Activation) (inl_rule : RuleMatchInfo)
: InlinePragma.
Arguments Mk_EP {_} _ _.
Arguments VanillaDM {_}.
Arguments GenericDM {_} _.
Instance Default__TyPrec : GHC.Err.Default TyPrec :=
GHC.Err.Build_Default _ TopPrec.
Instance Default__TupleSort : GHC.Err.Default TupleSort :=
GHC.Err.Build_Default _ BoxedTuple.
Instance Default__TopLevelFlag : GHC.Err.Default TopLevelFlag :=
GHC.Err.Build_Default _ TopLevel.
Instance Default__SwapFlag : GHC.Err.Default SwapFlag :=
GHC.Err.Build_Default _ NotSwapped.
Instance Default__SuccessFlag : GHC.Err.Default SuccessFlag :=
GHC.Err.Build_Default _ Succeeded.
Instance Default__SpliceExplicitFlag : GHC.Err.Default SpliceExplicitFlag :=
GHC.Err.Build_Default _ ExplicitSplice.
Instance Default__SourceText : GHC.Err.Default SourceText :=
GHC.Err.Build_Default _ NoSourceText.
Instance Default__StringLiteral : GHC.Err.Default StringLiteral :=
GHC.Err.Build_Default _ (Mk_StringLiteral GHC.Err.default GHC.Err.default).
Instance Default__RuleMatchInfo : GHC.Err.Default RuleMatchInfo :=
GHC.Err.Build_Default _ ConLike.
Instance Default__RecFlag : GHC.Err.Default RecFlag :=
GHC.Err.Build_Default _ Recursive.
Instance Default__Origin : GHC.Err.Default Origin :=
GHC.Err.Build_Default _ FromSource.
Instance Default__OneShotInfo : GHC.Err.Default OneShotInfo :=
GHC.Err.Build_Default _ NoOneShotInfo.
Instance Default__LexicalFixity : GHC.Err.Default LexicalFixity :=
GHC.Err.Build_Default _ Prefix.
Instance Default__LeftOrRight : GHC.Err.Default LeftOrRight :=
GHC.Err.Build_Default _ CLeft.
Instance Default__TailCallInfo : GHC.Err.Default TailCallInfo :=
GHC.Err.Build_Default _ NoTailCallInfo.
Instance Default__IntegralLit : GHC.Err.Default IntegralLit :=
GHC.Err.Build_Default _ (IL GHC.Err.default GHC.Err.default GHC.Err.default).
Instance Default__IntWithInf : GHC.Err.Default IntWithInf :=
GHC.Err.Build_Default _ Infinity.
Instance Default__OccInfo : GHC.Err.Default OccInfo :=
GHC.Err.Build_Default _ (ManyOccs GHC.Err.default).
Instance Default__InlineSpec : GHC.Err.Default InlineSpec :=
GHC.Err.Build_Default _ Inline.
Instance Default__FunctionOrData : GHC.Err.Default FunctionOrData :=
GHC.Err.Build_Default _ IsFunction.
Instance Default__FractionalLit : GHC.Err.Default FractionalLit :=
GHC.Err.Build_Default _ (FL GHC.Err.default GHC.Err.default GHC.Err.default).
Instance Default__FixityDirection : GHC.Err.Default FixityDirection :=
GHC.Err.Build_Default _ InfixL.
Instance Default__DerivStrategy : GHC.Err.Default DerivStrategy :=
GHC.Err.Build_Default _ StockStrategy.
Instance Default__CompilerPhase : GHC.Err.Default CompilerPhase :=
GHC.Err.Build_Default _ InitialPhase.
Instance Default__Boxity : GHC.Err.Default Boxity :=
GHC.Err.Build_Default _ Boxed.
Instance Default__Activation : GHC.Err.Default Activation :=
GHC.Err.Build_Default _ NeverActive.
Definition sl_fs (arg_0__ : StringLiteral) :=
let 'Mk_StringLiteral _ sl_fs := arg_0__ in
sl_fs.
Definition sl_st (arg_0__ : StringLiteral) :=
let 'Mk_StringLiteral sl_st _ := arg_0__ in
sl_st.
Definition isSafeOverlap (arg_0__ : OverlapFlag) :=
let 'Mk_OverlapFlag _ isSafeOverlap := arg_0__ in
isSafeOverlap.
Definition overlapMode (arg_0__ : OverlapFlag) :=
let 'Mk_OverlapFlag overlapMode _ := arg_0__ in
overlapMode.
Definition il_neg (arg_0__ : IntegralLit) :=
let 'IL _ il_neg _ := arg_0__ in
il_neg.
Definition il_text (arg_0__ : IntegralLit) :=
let 'IL il_text _ _ := arg_0__ in
il_text.
Definition il_value (arg_0__ : IntegralLit) :=
let 'IL _ _ il_value := arg_0__ in
il_value.
Definition occ_in_lam (arg_0__ : OccInfo) :=
match arg_0__ with
| ManyOccs _ =>
GHC.Err.error (GHC.Base.hs_string__
"Partial record selector: field `occ_in_lam' has no match in constructor `ManyOccs' of type `OccInfo'")
| IAmDead =>
GHC.Err.error (GHC.Base.hs_string__
"Partial record selector: field `occ_in_lam' has no match in constructor `IAmDead' of type `OccInfo'")
| OneOcc occ_in_lam _ _ _ => occ_in_lam
| IAmALoopBreaker _ _ =>
GHC.Err.error (GHC.Base.hs_string__
"Partial record selector: field `occ_in_lam' has no match in constructor `IAmALoopBreaker' of type `OccInfo'")
end.
Definition occ_int_cxt (arg_0__ : OccInfo) :=
match arg_0__ with
| ManyOccs _ =>
GHC.Err.error (GHC.Base.hs_string__
"Partial record selector: field `occ_int_cxt' has no match in constructor `ManyOccs' of type `OccInfo'")
| IAmDead =>
GHC.Err.error (GHC.Base.hs_string__
"Partial record selector: field `occ_int_cxt' has no match in constructor `IAmDead' of type `OccInfo'")
| OneOcc _ _ occ_int_cxt _ => occ_int_cxt
| IAmALoopBreaker _ _ =>
GHC.Err.error (GHC.Base.hs_string__
"Partial record selector: field `occ_int_cxt' has no match in constructor `IAmALoopBreaker' of type `OccInfo'")
end.
Definition occ_one_br (arg_0__ : OccInfo) :=
match arg_0__ with
| ManyOccs _ =>
GHC.Err.error (GHC.Base.hs_string__
"Partial record selector: field `occ_one_br' has no match in constructor `ManyOccs' of type `OccInfo'")
| IAmDead =>
GHC.Err.error (GHC.Base.hs_string__
"Partial record selector: field `occ_one_br' has no match in constructor `IAmDead' of type `OccInfo'")
| OneOcc _ occ_one_br _ _ => occ_one_br
| IAmALoopBreaker _ _ =>
GHC.Err.error (GHC.Base.hs_string__
"Partial record selector: field `occ_one_br' has no match in constructor `IAmALoopBreaker' of type `OccInfo'")
end.
Definition occ_rules_only (arg_0__ : OccInfo) :=
match arg_0__ with
| ManyOccs _ =>
GHC.Err.error (GHC.Base.hs_string__
"Partial record selector: field `occ_rules_only' has no match in constructor `ManyOccs' of type `OccInfo'")
| IAmDead =>
GHC.Err.error (GHC.Base.hs_string__
"Partial record selector: field `occ_rules_only' has no match in constructor `IAmDead' of type `OccInfo'")
| OneOcc _ _ _ _ =>
GHC.Err.error (GHC.Base.hs_string__
"Partial record selector: field `occ_rules_only' has no match in constructor `OneOcc' of type `OccInfo'")
| IAmALoopBreaker occ_rules_only _ => occ_rules_only
end.
Definition occ_tail (arg_0__ : OccInfo) :=
match arg_0__ with
| ManyOccs occ_tail => occ_tail
| IAmDead =>
GHC.Err.error (GHC.Base.hs_string__
"Partial record selector: field `occ_tail' has no match in constructor `IAmDead' of type `OccInfo'")
| OneOcc _ _ _ occ_tail => occ_tail
| IAmALoopBreaker _ occ_tail => occ_tail
end.
Definition fl_neg (arg_0__ : FractionalLit) :=
let 'FL _ fl_neg _ := arg_0__ in
fl_neg.
Definition fl_text (arg_0__ : FractionalLit) :=
let 'FL fl_text _ _ := arg_0__ in
fl_text.
Definition fl_value (arg_0__ : FractionalLit) :=
let 'FL _ _ fl_value := arg_0__ in
fl_value.
Definition fromEP {a} (arg_0__ : EP a) :=
let 'Mk_EP fromEP _ := arg_0__ in
fromEP.
Definition toEP {a} (arg_0__ : EP a) :=
let 'Mk_EP _ toEP := arg_0__ in
toEP.
Definition inl_act (arg_0__ : InlinePragma) :=
let 'Mk_InlinePragma _ _ _ inl_act _ := arg_0__ in
inl_act.
Definition inl_inline (arg_0__ : InlinePragma) :=
let 'Mk_InlinePragma _ inl_inline _ _ _ := arg_0__ in
inl_inline.
Definition inl_rule (arg_0__ : InlinePragma) :=
let 'Mk_InlinePragma _ _ _ _ inl_rule := arg_0__ in
inl_rule.
Definition inl_sat (arg_0__ : InlinePragma) :=
let 'Mk_InlinePragma _ _ inl_sat _ _ := arg_0__ in
inl_sat.
Definition inl_src (arg_0__ : InlinePragma) :=
let 'Mk_InlinePragma inl_src _ _ _ _ := arg_0__ in
inl_src.
(* Midamble *)
Require GHC.Err.
Instance Default__OverlapMode : GHC.Err.Default OverlapMode :=
GHC.Err.Build_Default _ (NoOverlap GHC.Err.default).
Instance Default__OverlapFlag : GHC.Err.Default OverlapFlag :=
GHC.Err.Build_Default _ (Mk_OverlapFlag GHC.Err.default GHC.Err.default).
Instance Default__Fixity : GHC.Err.Default Fixity :=
GHC.Err.Build_Default _ (Mk_Fixity GHC.Err.default GHC.Err.default GHC.Err.default).
Instance Default__InlinePragma : GHC.Err.Default InlinePragma :=
GHC.Err.Build_Default _ (Mk_InlinePragma GHC.Err.default GHC.Err.default GHC.Err.default GHC.Err.default GHC.Err.default).
(* Converted value declarations: *)
Local Definition Eq___LeftOrRight_op_zeze__
: LeftOrRight -> LeftOrRight -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| CLeft, CLeft => true
| CRight, CRight => true
| _, _ => false
end.
Local Definition Eq___LeftOrRight_op_zsze__
: LeftOrRight -> LeftOrRight -> bool :=
fun x y => negb (Eq___LeftOrRight_op_zeze__ x y).
Program Instance Eq___LeftOrRight : GHC.Base.Eq_ LeftOrRight :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___LeftOrRight_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___LeftOrRight_op_zsze__ |}.
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__LeftOrRight' *)
Local Definition Eq___OneShotInfo_op_zeze__
: OneShotInfo -> OneShotInfo -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| NoOneShotInfo, NoOneShotInfo => true
| OneShotLam, OneShotLam => true
| _, _ => false
end.
Local Definition Eq___OneShotInfo_op_zsze__
: OneShotInfo -> OneShotInfo -> bool :=
fun x y => negb (Eq___OneShotInfo_op_zeze__ x y).
Program Instance Eq___OneShotInfo : GHC.Base.Eq_ OneShotInfo :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___OneShotInfo_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___OneShotInfo_op_zsze__ |}.
Local Definition Eq___FunctionOrData_op_zeze__
: FunctionOrData -> FunctionOrData -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| IsFunction, IsFunction => true
| IsData, IsData => true
| _, _ => false
end.
Local Definition Eq___FunctionOrData_op_zsze__
: FunctionOrData -> FunctionOrData -> bool :=
fun x y => negb (Eq___FunctionOrData_op_zeze__ x y).
Program Instance Eq___FunctionOrData : GHC.Base.Eq_ FunctionOrData :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___FunctionOrData_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___FunctionOrData_op_zsze__ |}.
Local Definition Ord__FunctionOrData_op_zl__
: FunctionOrData -> FunctionOrData -> bool :=
fun a b =>
match a with
| IsFunction => match b with | IsFunction => false | _ => true end
| IsData => match b with | IsData => false | _ => false end
end.
Local Definition Ord__FunctionOrData_op_zlze__
: FunctionOrData -> FunctionOrData -> bool :=
fun a b => negb (Ord__FunctionOrData_op_zl__ b a).
Local Definition Ord__FunctionOrData_op_zg__
: FunctionOrData -> FunctionOrData -> bool :=
fun a b => Ord__FunctionOrData_op_zl__ b a.
Local Definition Ord__FunctionOrData_op_zgze__
: FunctionOrData -> FunctionOrData -> bool :=
fun a b => negb (Ord__FunctionOrData_op_zl__ a b).
Local Definition Ord__FunctionOrData_compare
: FunctionOrData -> FunctionOrData -> comparison :=
fun a b =>
match a with
| IsFunction => match b with | IsFunction => Eq | _ => Lt end
| IsData => match b with | IsData => Eq | _ => Gt end
end.
Local Definition Ord__FunctionOrData_max
: FunctionOrData -> FunctionOrData -> FunctionOrData :=
fun x y => if Ord__FunctionOrData_op_zlze__ x y : bool then y else x.
Local Definition Ord__FunctionOrData_min
: FunctionOrData -> FunctionOrData -> FunctionOrData :=
fun x y => if Ord__FunctionOrData_op_zlze__ x y : bool then x else y.
Program Instance Ord__FunctionOrData : GHC.Base.Ord FunctionOrData :=
fun _ k__ =>
k__ {| GHC.Base.op_zl____ := Ord__FunctionOrData_op_zl__ ;
GHC.Base.op_zlze____ := Ord__FunctionOrData_op_zlze__ ;
GHC.Base.op_zg____ := Ord__FunctionOrData_op_zg__ ;
GHC.Base.op_zgze____ := Ord__FunctionOrData_op_zgze__ ;
GHC.Base.compare__ := Ord__FunctionOrData_compare ;
GHC.Base.max__ := Ord__FunctionOrData_max ;
GHC.Base.min__ := Ord__FunctionOrData_min |}.
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__FunctionOrData' *)
Local Definition Eq___FixityDirection_op_zeze__
: FixityDirection -> FixityDirection -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| InfixL, InfixL => true
| InfixR, InfixR => true
| InfixN, InfixN => true
| _, _ => false
end.
Local Definition Eq___FixityDirection_op_zsze__
: FixityDirection -> FixityDirection -> bool :=
fun x y => negb (Eq___FixityDirection_op_zeze__ x y).
Program Instance Eq___FixityDirection : GHC.Base.Eq_ FixityDirection :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___FixityDirection_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___FixityDirection_op_zsze__ |}.
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__FixityDirection' *)
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__LexicalFixity' *)
Local Definition Eq___LexicalFixity_op_zeze__
: LexicalFixity -> LexicalFixity -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| Prefix, Prefix => true
| Infix, Infix => true
| _, _ => false
end.
Local Definition Eq___LexicalFixity_op_zsze__
: LexicalFixity -> LexicalFixity -> bool :=
fun x y => negb (Eq___LexicalFixity_op_zeze__ x y).
Program Instance Eq___LexicalFixity : GHC.Base.Eq_ LexicalFixity :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___LexicalFixity_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___LexicalFixity_op_zsze__ |}.
Local Definition Eq___Boxity_op_zeze__ : Boxity -> Boxity -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| Boxed, Boxed => true
| Unboxed, Unboxed => true
| _, _ => false
end.
Local Definition Eq___Boxity_op_zsze__ : Boxity -> Boxity -> bool :=
fun x y => negb (Eq___Boxity_op_zeze__ x y).
Program Instance Eq___Boxity : GHC.Base.Eq_ Boxity :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___Boxity_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___Boxity_op_zsze__ |}.
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__Boxity' *)
Local Definition Eq___RecFlag_op_zeze__ : RecFlag -> RecFlag -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| Recursive, Recursive => true
| NonRecursive, NonRecursive => true
| _, _ => false
end.
Local Definition Eq___RecFlag_op_zsze__ : RecFlag -> RecFlag -> bool :=
fun x y => negb (Eq___RecFlag_op_zeze__ x y).
Program Instance Eq___RecFlag : GHC.Base.Eq_ RecFlag :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___RecFlag_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___RecFlag_op_zsze__ |}.
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__RecFlag' *)
Local Definition Eq___Origin_op_zeze__ : Origin -> Origin -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| FromSource, FromSource => true
| Generated, Generated => true
| _, _ => false
end.
Local Definition Eq___Origin_op_zsze__ : Origin -> Origin -> bool :=
fun x y => negb (Eq___Origin_op_zeze__ x y).
Program Instance Eq___Origin : GHC.Base.Eq_ Origin :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___Origin_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___Origin_op_zsze__ |}.
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__Origin' *)
Local Definition Eq___DerivStrategy_op_zeze__
: DerivStrategy -> DerivStrategy -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| StockStrategy, StockStrategy => true
| AnyclassStrategy, AnyclassStrategy => true
| NewtypeStrategy, NewtypeStrategy => true
| _, _ => false
end.
Local Definition Eq___DerivStrategy_op_zsze__
: DerivStrategy -> DerivStrategy -> bool :=
fun x y => negb (Eq___DerivStrategy_op_zeze__ x y).
Program Instance Eq___DerivStrategy : GHC.Base.Eq_ DerivStrategy :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___DerivStrategy_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___DerivStrategy_op_zsze__ |}.
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__DerivStrategy' *)
Local Definition Eq___TupleSort_op_zeze__ : TupleSort -> TupleSort -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| BoxedTuple, BoxedTuple => true
| UnboxedTuple, UnboxedTuple => true
| ConstraintTuple, ConstraintTuple => true
| _, _ => false
end.
Local Definition Eq___TupleSort_op_zsze__ : TupleSort -> TupleSort -> bool :=
fun x y => negb (Eq___TupleSort_op_zeze__ x y).
Program Instance Eq___TupleSort : GHC.Base.Eq_ TupleSort :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___TupleSort_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___TupleSort_op_zsze__ |}.
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__TupleSort' *)
Local Definition Eq___TailCallInfo_op_zeze__
: TailCallInfo -> TailCallInfo -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| AlwaysTailCalled a1, AlwaysTailCalled b1 => ((a1 GHC.Base.== b1))
| NoTailCallInfo, NoTailCallInfo => true
| _, _ => false
end.
Local Definition Eq___TailCallInfo_op_zsze__
: TailCallInfo -> TailCallInfo -> bool :=
fun x y => negb (Eq___TailCallInfo_op_zeze__ x y).
Program Instance Eq___TailCallInfo : GHC.Base.Eq_ TailCallInfo :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___TailCallInfo_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___TailCallInfo_op_zsze__ |}.
Local Definition Eq___OccInfo_op_zeze__ : OccInfo -> OccInfo -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| ManyOccs a1, ManyOccs b1 => ((a1 GHC.Base.== b1))
| IAmDead, IAmDead => true
| OneOcc a1 a2 a3 a4, OneOcc b1 b2 b3 b4 =>
(andb (andb (andb ((a1 GHC.Base.== b1)) ((a2 GHC.Base.== b2))) ((a3 GHC.Base.==
b3))) ((a4 GHC.Base.== b4)))
| IAmALoopBreaker a1 a2, IAmALoopBreaker b1 b2 =>
(andb ((a1 GHC.Base.== b1)) ((a2 GHC.Base.== b2)))
| _, _ => false
end.
Local Definition Eq___OccInfo_op_zsze__ : OccInfo -> OccInfo -> bool :=
fun x y => negb (Eq___OccInfo_op_zeze__ x y).
Program Instance Eq___OccInfo : GHC.Base.Eq_ OccInfo :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___OccInfo_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___OccInfo_op_zsze__ |}.
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__SourceText' *)
(* Skipping all instances of class `GHC.Show.Show', including
`BasicTypes.Show__SourceText' *)
Local Definition Eq___SourceText_op_zeze__ : SourceText -> SourceText -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| Mk_SourceText a1, Mk_SourceText b1 => ((a1 GHC.Base.== b1))
| NoSourceText, NoSourceText => true
| _, _ => false
end.
Local Definition Eq___SourceText_op_zsze__ : SourceText -> SourceText -> bool :=
fun x y => negb (Eq___SourceText_op_zeze__ x y).
Program Instance Eq___SourceText : GHC.Base.Eq_ SourceText :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___SourceText_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___SourceText_op_zsze__ |}.
Local Definition Eq___OverlapMode_op_zeze__
: OverlapMode -> OverlapMode -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| NoOverlap a1, NoOverlap b1 => ((a1 GHC.Base.== b1))
| Overlappable a1, Overlappable b1 => ((a1 GHC.Base.== b1))
| Overlapping a1, Overlapping b1 => ((a1 GHC.Base.== b1))
| Overlaps a1, Overlaps b1 => ((a1 GHC.Base.== b1))
| Incoherent a1, Incoherent b1 => ((a1 GHC.Base.== b1))
| _, _ => false
end.
Local Definition Eq___OverlapMode_op_zsze__
: OverlapMode -> OverlapMode -> bool :=
fun x y => negb (Eq___OverlapMode_op_zeze__ x y).
Program Instance Eq___OverlapMode : GHC.Base.Eq_ OverlapMode :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___OverlapMode_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___OverlapMode_op_zsze__ |}.
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__OverlapMode' *)
Local Definition Eq___OverlapFlag_op_zeze__
: OverlapFlag -> OverlapFlag -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| Mk_OverlapFlag a1 a2, Mk_OverlapFlag b1 b2 =>
(andb ((a1 GHC.Base.== b1)) ((a2 GHC.Base.== b2)))
end.
Local Definition Eq___OverlapFlag_op_zsze__
: OverlapFlag -> OverlapFlag -> bool :=
fun x y => negb (Eq___OverlapFlag_op_zeze__ x y).
Program Instance Eq___OverlapFlag : GHC.Base.Eq_ OverlapFlag :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___OverlapFlag_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___OverlapFlag_op_zsze__ |}.
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__OverlapFlag' *)
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__Fixity' *)
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__StringLiteral' *)
Local Definition Eq___StringLiteral_op_zeze__
: StringLiteral -> StringLiteral -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| Mk_StringLiteral _ a, Mk_StringLiteral _ b => a GHC.Base.== b
end.
Local Definition Eq___StringLiteral_op_zsze__
: StringLiteral -> StringLiteral -> bool :=
fun x y => negb (Eq___StringLiteral_op_zeze__ x y).
Program Instance Eq___StringLiteral : GHC.Base.Eq_ StringLiteral :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___StringLiteral_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___StringLiteral_op_zsze__ |}.
Local Definition Eq___WarningTxt_op_zeze__ : WarningTxt -> WarningTxt -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| Mk_WarningTxt a1 a2, Mk_WarningTxt b1 b2 =>
(andb ((a1 GHC.Base.== b1)) ((a2 GHC.Base.== b2)))
| DeprecatedTxt a1 a2, DeprecatedTxt b1 b2 =>
(andb ((a1 GHC.Base.== b1)) ((a2 GHC.Base.== b2)))
| _, _ => false
end.
Local Definition Eq___WarningTxt_op_zsze__ : WarningTxt -> WarningTxt -> bool :=
fun x y => negb (Eq___WarningTxt_op_zeze__ x y).
Program Instance Eq___WarningTxt : GHC.Base.Eq_ WarningTxt :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___WarningTxt_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___WarningTxt_op_zsze__ |}.
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__WarningTxt' *)
Local Definition Eq___Activation_op_zeze__ : Activation -> Activation -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| NeverActive, NeverActive => true
| AlwaysActive, AlwaysActive => true
| ActiveBefore a1 a2, ActiveBefore b1 b2 =>
(andb ((a1 GHC.Base.== b1)) ((a2 GHC.Base.== b2)))
| ActiveAfter a1 a2, ActiveAfter b1 b2 =>
(andb ((a1 GHC.Base.== b1)) ((a2 GHC.Base.== b2)))
| _, _ => false
end.
Local Definition Eq___Activation_op_zsze__ : Activation -> Activation -> bool :=
fun x y => negb (Eq___Activation_op_zeze__ x y).
Program Instance Eq___Activation : GHC.Base.Eq_ Activation :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___Activation_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___Activation_op_zsze__ |}.
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__Activation' *)
Local Definition Eq___RuleMatchInfo_op_zeze__
: RuleMatchInfo -> RuleMatchInfo -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| ConLike, ConLike => true
| FunLike, FunLike => true
| _, _ => false
end.
Local Definition Eq___RuleMatchInfo_op_zsze__
: RuleMatchInfo -> RuleMatchInfo -> bool :=
fun x y => negb (Eq___RuleMatchInfo_op_zeze__ x y).
Program Instance Eq___RuleMatchInfo : GHC.Base.Eq_ RuleMatchInfo :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___RuleMatchInfo_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___RuleMatchInfo_op_zsze__ |}.
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__RuleMatchInfo' *)
(* Skipping all instances of class `GHC.Show.Show', including
`BasicTypes.Show__RuleMatchInfo' *)
Local Definition Eq___InlineSpec_op_zeze__ : InlineSpec -> InlineSpec -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| Inline, Inline => true
| Inlinable, Inlinable => true
| NoInline, NoInline => true
| NoUserInline, NoUserInline => true
| _, _ => false
end.
Local Definition Eq___InlineSpec_op_zsze__ : InlineSpec -> InlineSpec -> bool :=
fun x y => negb (Eq___InlineSpec_op_zeze__ x y).
Program Instance Eq___InlineSpec : GHC.Base.Eq_ InlineSpec :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___InlineSpec_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___InlineSpec_op_zsze__ |}.
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__InlineSpec' *)
(* Skipping all instances of class `GHC.Show.Show', including
`BasicTypes.Show__InlineSpec' *)
Local Definition Eq___InlinePragma_op_zeze__
: InlinePragma -> InlinePragma -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| Mk_InlinePragma a1 a2 a3 a4 a5, Mk_InlinePragma b1 b2 b3 b4 b5 =>
(andb (andb (andb (andb ((a1 GHC.Base.== b1)) ((a2 GHC.Base.== b2))) ((a3
GHC.Base.==
b3))) ((a4 GHC.Base.== b4))) ((a5 GHC.Base.== b5)))
end.
Local Definition Eq___InlinePragma_op_zsze__
: InlinePragma -> InlinePragma -> bool :=
fun x y => negb (Eq___InlinePragma_op_zeze__ x y).
Program Instance Eq___InlinePragma : GHC.Base.Eq_ InlinePragma :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___InlinePragma_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___InlinePragma_op_zsze__ |}.
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__InlinePragma' *)
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__IntegralLit' *)
(* Skipping all instances of class `GHC.Show.Show', including
`BasicTypes.Show__IntegralLit' *)
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__FractionalLit' *)
(* Skipping all instances of class `GHC.Show.Show', including
`BasicTypes.Show__FractionalLit' *)
Local Definition Eq___IntWithInf_op_zeze__ : IntWithInf -> IntWithInf -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| Int a1, Int b1 => ((a1 GHC.Base.== b1))
| Infinity, Infinity => true
| _, _ => false
end.
Local Definition Eq___IntWithInf_op_zsze__ : IntWithInf -> IntWithInf -> bool :=
fun x y => negb (Eq___IntWithInf_op_zeze__ x y).
Program Instance Eq___IntWithInf : GHC.Base.Eq_ IntWithInf :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___IntWithInf_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___IntWithInf_op_zsze__ |}.
(* Skipping all instances of class `Data.Data.Data', including
`BasicTypes.Data__SpliceExplicitFlag' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__LeftOrRight' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__OneShotInfo' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__SwapFlag' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__FunctionOrData' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__StringLiteral' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__WarningTxt' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__Fixity' *)
Local Definition Eq___Fixity_op_zeze__ : Fixity -> Fixity -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| Mk_Fixity _ p1 dir1, Mk_Fixity _ p2 dir2 =>
andb (p1 GHC.Base.== p2) (dir1 GHC.Base.== dir2)
end.
Local Definition Eq___Fixity_op_zsze__ : Fixity -> Fixity -> bool :=
fun x y => negb (Eq___Fixity_op_zeze__ x y).
Program Instance Eq___Fixity : GHC.Base.Eq_ Fixity :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___Fixity_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___Fixity_op_zsze__ |}.
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__FixityDirection' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__LexicalFixity' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__TopLevelFlag' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__Boxity' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__RecFlag' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__Origin' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__DerivStrategy' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__OverlapFlag' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__OverlapMode' *)
(* Skipping instance `BasicTypes.Eq___TyPrec' of class `GHC.Base.Eq_' *)
(* Skipping instance `BasicTypes.Ord__TyPrec' of class `GHC.Base.Ord' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__TailCallInfo' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__OccInfo' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__DefMethSpec' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__SuccessFlag' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__SourceText' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__CompilerPhase' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__Activation' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__RuleMatchInfo' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__InlineSpec' *)
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__InlinePragma' *)
Local Definition Eq___IntegralLit_op_zeze__
: IntegralLit -> IntegralLit -> bool :=
Data.Function.on _GHC.Base.==_ il_value.
Local Definition Eq___IntegralLit_op_zsze__
: IntegralLit -> IntegralLit -> bool :=
fun x y => negb (Eq___IntegralLit_op_zeze__ x y).
Program Instance Eq___IntegralLit : GHC.Base.Eq_ IntegralLit :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___IntegralLit_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___IntegralLit_op_zsze__ |}.
Local Definition Ord__IntegralLit_compare
: IntegralLit -> IntegralLit -> comparison :=
Data.Function.on GHC.Base.compare il_value.
Local Definition Ord__IntegralLit_op_zl__
: IntegralLit -> IntegralLit -> bool :=
fun x y => Ord__IntegralLit_compare x y GHC.Base.== Lt.
Local Definition Ord__IntegralLit_op_zlze__
: IntegralLit -> IntegralLit -> bool :=
fun x y => Ord__IntegralLit_compare x y GHC.Base./= Gt.
Local Definition Ord__IntegralLit_op_zg__
: IntegralLit -> IntegralLit -> bool :=
fun x y => Ord__IntegralLit_compare x y GHC.Base.== Gt.
Local Definition Ord__IntegralLit_op_zgze__
: IntegralLit -> IntegralLit -> bool :=
fun x y => Ord__IntegralLit_compare x y GHC.Base./= Lt.
Local Definition Ord__IntegralLit_max
: IntegralLit -> IntegralLit -> IntegralLit :=
fun x y => if Ord__IntegralLit_op_zlze__ x y : bool then y else x.
Local Definition Ord__IntegralLit_min
: IntegralLit -> IntegralLit -> IntegralLit :=
fun x y => if Ord__IntegralLit_op_zlze__ x y : bool then x else y.
Program Instance Ord__IntegralLit : GHC.Base.Ord IntegralLit :=
fun _ k__ =>
k__ {| GHC.Base.op_zl____ := Ord__IntegralLit_op_zl__ ;
GHC.Base.op_zlze____ := Ord__IntegralLit_op_zlze__ ;
GHC.Base.op_zg____ := Ord__IntegralLit_op_zg__ ;
GHC.Base.op_zgze____ := Ord__IntegralLit_op_zgze__ ;
GHC.Base.compare__ := Ord__IntegralLit_compare ;
GHC.Base.max__ := Ord__IntegralLit_max ;
GHC.Base.min__ := Ord__IntegralLit_min |}.
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__IntegralLit' *)
Local Definition Eq___FractionalLit_op_zeze__
: FractionalLit -> FractionalLit -> bool :=
Data.Function.on _GHC.Base.==_ fl_value.
Local Definition Eq___FractionalLit_op_zsze__
: FractionalLit -> FractionalLit -> bool :=
fun x y => negb (Eq___FractionalLit_op_zeze__ x y).
Program Instance Eq___FractionalLit : GHC.Base.Eq_ FractionalLit :=
fun _ k__ =>
k__ {| GHC.Base.op_zeze____ := Eq___FractionalLit_op_zeze__ ;
GHC.Base.op_zsze____ := Eq___FractionalLit_op_zsze__ |}.
Local Definition Ord__FractionalLit_compare
: FractionalLit -> FractionalLit -> comparison :=
Data.Function.on GHC.Base.compare fl_value.
Local Definition Ord__FractionalLit_op_zl__
: FractionalLit -> FractionalLit -> bool :=
fun x y => Ord__FractionalLit_compare x y GHC.Base.== Lt.
Local Definition Ord__FractionalLit_op_zlze__
: FractionalLit -> FractionalLit -> bool :=
fun x y => Ord__FractionalLit_compare x y GHC.Base./= Gt.
Local Definition Ord__FractionalLit_op_zg__
: FractionalLit -> FractionalLit -> bool :=
fun x y => Ord__FractionalLit_compare x y GHC.Base.== Gt.
Local Definition Ord__FractionalLit_op_zgze__
: FractionalLit -> FractionalLit -> bool :=
fun x y => Ord__FractionalLit_compare x y GHC.Base./= Lt.
Local Definition Ord__FractionalLit_max
: FractionalLit -> FractionalLit -> FractionalLit :=
fun x y => if Ord__FractionalLit_op_zlze__ x y : bool then y else x.
Local Definition Ord__FractionalLit_min
: FractionalLit -> FractionalLit -> FractionalLit :=
fun x y => if Ord__FractionalLit_op_zlze__ x y : bool then x else y.
Program Instance Ord__FractionalLit : GHC.Base.Ord FractionalLit :=
fun _ k__ =>
k__ {| GHC.Base.op_zl____ := Ord__FractionalLit_op_zl__ ;
GHC.Base.op_zlze____ := Ord__FractionalLit_op_zlze__ ;
GHC.Base.op_zg____ := Ord__FractionalLit_op_zg__ ;
GHC.Base.op_zgze____ := Ord__FractionalLit_op_zgze__ ;
GHC.Base.compare__ := Ord__FractionalLit_compare ;
GHC.Base.max__ := Ord__FractionalLit_max ;
GHC.Base.min__ := Ord__FractionalLit_min |}.
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__FractionalLit' *)
Local Definition Ord__IntWithInf_compare
: IntWithInf -> IntWithInf -> comparison :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| Infinity, Infinity => Eq
| Int _, Infinity => Lt
| Infinity, Int _ => Gt
| Int a, Int b => GHC.Base.compare a b
end.
Local Definition Ord__IntWithInf_op_zl__ : IntWithInf -> IntWithInf -> bool :=
fun x y => Ord__IntWithInf_compare x y GHC.Base.== Lt.
Local Definition Ord__IntWithInf_op_zlze__ : IntWithInf -> IntWithInf -> bool :=
fun x y => Ord__IntWithInf_compare x y GHC.Base./= Gt.
Local Definition Ord__IntWithInf_op_zg__ : IntWithInf -> IntWithInf -> bool :=
fun x y => Ord__IntWithInf_compare x y GHC.Base.== Gt.
Local Definition Ord__IntWithInf_op_zgze__ : IntWithInf -> IntWithInf -> bool :=
fun x y => Ord__IntWithInf_compare x y GHC.Base./= Lt.
Local Definition Ord__IntWithInf_max : IntWithInf -> IntWithInf -> IntWithInf :=
fun x y => if Ord__IntWithInf_op_zlze__ x y : bool then y else x.
Local Definition Ord__IntWithInf_min : IntWithInf -> IntWithInf -> IntWithInf :=
fun x y => if Ord__IntWithInf_op_zlze__ x y : bool then x else y.
Program Instance Ord__IntWithInf : GHC.Base.Ord IntWithInf :=
fun _ k__ =>
k__ {| GHC.Base.op_zl____ := Ord__IntWithInf_op_zl__ ;
GHC.Base.op_zlze____ := Ord__IntWithInf_op_zlze__ ;
GHC.Base.op_zg____ := Ord__IntWithInf_op_zg__ ;
GHC.Base.op_zgze____ := Ord__IntWithInf_op_zgze__ ;
GHC.Base.compare__ := Ord__IntWithInf_compare ;
GHC.Base.max__ := Ord__IntWithInf_max ;
GHC.Base.min__ := Ord__IntWithInf_min |}.
(* Skipping all instances of class `Outputable.Outputable', including
`BasicTypes.Outputable__IntWithInf' *)
(* Skipping all instances of class `GHC.Num.Num', including
`BasicTypes.Num__IntWithInf' *)
Definition pickLR {a} : LeftOrRight -> (a * a)%type -> a :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| CLeft, pair l _ => l
| CRight, pair _ r => r
end.
Definition fIRST_TAG : ConTag :=
#1.
Definition noOneShotInfo : OneShotInfo :=
NoOneShotInfo.
Definition isOneShotInfo : OneShotInfo -> bool :=
fun arg_0__ => match arg_0__ with | OneShotLam => true | _ => false end.
Definition hasNoOneShotInfo : OneShotInfo -> bool :=
fun arg_0__ => match arg_0__ with | NoOneShotInfo => true | _ => false end.
Definition worstOneShot : OneShotInfo -> OneShotInfo -> OneShotInfo :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| NoOneShotInfo, _ => NoOneShotInfo
| OneShotLam, os => os
end.
Definition bestOneShot : OneShotInfo -> OneShotInfo -> OneShotInfo :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| NoOneShotInfo, os => os
| OneShotLam, _ => OneShotLam
end.
(* Skipping definition `BasicTypes.pprOneShotInfo' *)
Definition flipSwap : SwapFlag -> SwapFlag :=
fun arg_0__ =>
match arg_0__ with
| IsSwapped => NotSwapped
| NotSwapped => IsSwapped
end.
Definition isSwapped : SwapFlag -> bool :=
fun arg_0__ => match arg_0__ with | IsSwapped => true | NotSwapped => false end.
Definition unSwap {a} {b} : SwapFlag -> (a -> a -> b) -> a -> a -> b :=
fun arg_0__ arg_1__ arg_2__ arg_3__ =>
match arg_0__, arg_1__, arg_2__, arg_3__ with
| NotSwapped, f, a, b => f a b
| IsSwapped, f, a, b => f b a
end.
Definition bumpVersion : Version -> Version :=
fun v => v GHC.Num.+ #1.
Definition initialVersion : Version :=
#1.
Definition pp_ws : list (SrcLoc.Located StringLiteral) -> GHC.Base.String :=
fun arg_0__ =>
match arg_0__ with
| cons l nil => Panic.someSDoc
| ws =>
GHC.Base.mappend (GHC.Base.mappend (Datatypes.id (GHC.Base.hs_string__ "["))
Panic.someSDoc) (Datatypes.id (GHC.Base.hs_string__ "]"))
end.
Definition pprWarningTxtForMsg : WarningTxt -> GHC.Base.String :=
fun arg_0__ =>
match arg_0__ with
| Mk_WarningTxt _ ws => Panic.someSDoc
| DeprecatedTxt _ ds =>
GHC.Base.mappend (Datatypes.id (GHC.Base.hs_string__ "Deprecated:"))
Panic.someSDoc
end.
(* Skipping definition `BasicTypes.pprRuleName' *)
Definition maxPrecedence : GHC.Num.Int :=
#9.
Definition minPrecedence : GHC.Num.Int :=
#0.
(* Skipping definition `BasicTypes.defaultFixity' *)
Definition negateFixity : Fixity :=
Mk_Fixity NoSourceText #6 InfixL.
Definition funTyFixity : Fixity :=
Mk_Fixity NoSourceText #0 InfixR.
Definition compareFixity : Fixity -> Fixity -> (bool * bool)%type :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| Mk_Fixity _ prec1 dir1, Mk_Fixity _ prec2 dir2 =>
let error_please := pair true false in
let left_ := pair false false in
let right_ := pair false true in
match GHC.Base.compare prec1 prec2 with
| Gt => left_
| Lt => right_
| Eq =>
match pair dir1 dir2 with
| pair InfixR InfixR => right_
| pair InfixL InfixL => left_
| _ => error_please
end
end
end.
Definition isNotTopLevel : TopLevelFlag -> bool :=
fun arg_0__ => match arg_0__ with | NotTopLevel => true | TopLevel => false end.
Definition isTopLevel : TopLevelFlag -> bool :=
fun arg_0__ => match arg_0__ with | TopLevel => true | NotTopLevel => false end.
Definition isBoxed : Boxity -> bool :=
fun arg_0__ => match arg_0__ with | Boxed => true | Unboxed => false end.
Definition isRec : RecFlag -> bool :=
fun arg_0__ =>
match arg_0__ with
| Recursive => true
| NonRecursive => false
end.
Definition isNonRec : RecFlag -> bool :=
fun arg_0__ =>
match arg_0__ with
| Recursive => false
| NonRecursive => true
end.
Definition boolToRecFlag : bool -> RecFlag :=
fun arg_0__ =>
match arg_0__ with
| true => Recursive
| false => NonRecursive
end.
Definition isGenerated : Origin -> bool :=
fun arg_0__ => match arg_0__ with | Generated => true | FromSource => false end.
Definition setOverlapModeMaybe
: OverlapFlag -> option OverlapMode -> OverlapFlag :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| f, None => f
| f, Some m =>
let 'Mk_OverlapFlag overlapMode_2__ isSafeOverlap_3__ := f in
Mk_OverlapFlag m isSafeOverlap_3__
end.
Definition hasIncoherentFlag : OverlapMode -> bool :=
fun mode => match mode with | Incoherent _ => true | _ => false end.
Definition hasOverlappableFlag : OverlapMode -> bool :=
fun mode =>
match mode with
| Overlappable _ => true
| Overlaps _ => true
| Incoherent _ => true
| _ => false
end.
Definition hasOverlappingFlag : OverlapMode -> bool :=
fun mode =>
match mode with
| Overlapping _ => true
| Overlaps _ => true
| Incoherent _ => true
| _ => false
end.
(* Skipping definition `BasicTypes.pprSafeOverlap' *)
(* Skipping definition `BasicTypes.maybeParen' *)
Definition tupleSortBoxity : TupleSort -> Boxity :=
fun arg_0__ =>
match arg_0__ with
| BoxedTuple => Boxed
| UnboxedTuple => Unboxed
| ConstraintTuple => Boxed
end.
Definition boxityTupleSort : Boxity -> TupleSort :=
fun arg_0__ =>
match arg_0__ with
| Boxed => BoxedTuple
| Unboxed => UnboxedTuple
end.
(* Skipping definition `BasicTypes.tupleParens' *)
Definition sumParens : GHC.Base.String -> GHC.Base.String :=
fun p => GHC.Base.mappend (GHC.Base.mappend Panic.someSDoc p) Panic.someSDoc.
(* Skipping definition `BasicTypes.pprAlternative' *)
Definition noOccInfo : OccInfo :=
ManyOccs NoTailCallInfo.
Definition isManyOccs : OccInfo -> bool :=
fun arg_0__ => match arg_0__ with | ManyOccs _ => true | _ => false end.
Definition seqOccInfo : OccInfo -> unit :=
fun occ => GHC.Prim.seq occ tt.
Definition insideLam : InsideLam :=
true.
Definition notInsideLam : InsideLam :=
false.
Definition oneBranch : OneBranch :=
true.
Definition notOneBranch : OneBranch :=
false.
Definition tailCallInfo : OccInfo -> TailCallInfo :=
fun arg_0__ =>
match arg_0__ with
| IAmDead => NoTailCallInfo
| other => occ_tail other
end.
Definition zapOccTailCallInfo : OccInfo -> OccInfo :=
fun arg_0__ =>
match arg_0__ with
| IAmDead => IAmDead
| occ =>
match occ with
| ManyOccs occ_tail_1__ => ManyOccs NoTailCallInfo
| IAmDead => GHC.Err.error (GHC.Base.hs_string__ "Partial record update")
| OneOcc occ_in_lam_2__ occ_one_br_3__ occ_int_cxt_4__ occ_tail_5__ =>
OneOcc occ_in_lam_2__ occ_one_br_3__ occ_int_cxt_4__ NoTailCallInfo
| IAmALoopBreaker occ_rules_only_6__ occ_tail_7__ =>
IAmALoopBreaker occ_rules_only_6__ NoTailCallInfo
end
end.
Definition isAlwaysTailCalled : OccInfo -> bool :=
fun occ =>
match tailCallInfo occ with
| AlwaysTailCalled _ => true
| NoTailCallInfo => false
end.
Definition strongLoopBreaker : OccInfo :=
IAmALoopBreaker false NoTailCallInfo.
Definition weakLoopBreaker : OccInfo :=
IAmALoopBreaker true NoTailCallInfo.
Definition isWeakLoopBreaker : OccInfo -> bool :=
fun arg_0__ =>
match arg_0__ with
| IAmALoopBreaker _ _ => true
| _ => false
end.
Definition isStrongLoopBreaker : OccInfo -> bool :=
fun arg_0__ =>
match arg_0__ with
| IAmALoopBreaker false _ => true
| _ => false
end.
Definition isDeadOcc : OccInfo -> bool :=
fun arg_0__ => match arg_0__ with | IAmDead => true | _ => false end.
Definition isOneOcc : OccInfo -> bool :=
fun arg_0__ => match arg_0__ with | OneOcc _ _ _ _ => true | _ => false end.
Definition zapFragileOcc : OccInfo -> OccInfo :=
fun arg_0__ =>
match arg_0__ with
| OneOcc _ _ _ _ => noOccInfo
| occ => zapOccTailCallInfo occ
end.
Definition pprShortTailCallInfo : TailCallInfo -> GHC.Base.String :=
fun arg_0__ =>
match arg_0__ with
| AlwaysTailCalled ar => GHC.Base.mappend Panic.someSDoc Panic.someSDoc
| NoTailCallInfo => Panic.someSDoc
end.
Definition successIf : bool -> SuccessFlag :=
fun arg_0__ => match arg_0__ with | true => Succeeded | false => Failed end.
Definition succeeded : SuccessFlag -> bool :=
fun arg_0__ => match arg_0__ with | Succeeded => true | Failed => false end.
Definition failed : SuccessFlag -> bool :=
fun arg_0__ => match arg_0__ with | Succeeded => false | Failed => true end.
Definition pprWithSourceText
: SourceText -> GHC.Base.String -> GHC.Base.String :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| NoSourceText, d => d
| Mk_SourceText src, _ => Datatypes.id src
end.
Definition isConLike : RuleMatchInfo -> bool :=
fun arg_0__ => match arg_0__ with | ConLike => true | _ => false end.
Definition isFunLike : RuleMatchInfo -> bool :=
fun arg_0__ => match arg_0__ with | FunLike => true | _ => false end.
Definition noUserInlineSpec : InlineSpec -> bool :=
fun arg_0__ => match arg_0__ with | NoUserInline => true | _ => false end.
Definition defaultInlinePragma : InlinePragma :=
Mk_InlinePragma (Mk_SourceText (GHC.Base.hs_string__ "{-# INLINE")) NoUserInline
None AlwaysActive FunLike.
Definition alwaysInlinePragma : InlinePragma :=
let 'Mk_InlinePragma inl_src_0__ inl_inline_1__ inl_sat_2__ inl_act_3__
inl_rule_4__ := defaultInlinePragma in
Mk_InlinePragma inl_src_0__ Inline inl_sat_2__ inl_act_3__ inl_rule_4__.
Definition neverInlinePragma : InlinePragma :=
let 'Mk_InlinePragma inl_src_0__ inl_inline_1__ inl_sat_2__ inl_act_3__
inl_rule_4__ := defaultInlinePragma in
Mk_InlinePragma inl_src_0__ inl_inline_1__ inl_sat_2__ NeverActive inl_rule_4__.
Definition inlinePragmaSpec : InlinePragma -> InlineSpec :=
inl_inline.
Definition dfunInlinePragma : InlinePragma :=
let 'Mk_InlinePragma inl_src_0__ inl_inline_1__ inl_sat_2__ inl_act_3__
inl_rule_4__ := defaultInlinePragma in
Mk_InlinePragma inl_src_0__ inl_inline_1__ inl_sat_2__ AlwaysActive ConLike.
Definition isAlwaysActive : Activation -> bool :=
fun arg_0__ => match arg_0__ with | AlwaysActive => true | _ => false end.
Definition isDefaultInlinePragma : InlinePragma -> bool :=
fun '(Mk_InlinePragma _ inline _ activation match_info) =>
andb (noUserInlineSpec inline) (andb (isAlwaysActive activation) (isFunLike
match_info)).
Definition isInlinePragma : InlinePragma -> bool :=
fun prag => match inl_inline prag with | Inline => true | _ => false end.
Definition isInlinablePragma : InlinePragma -> bool :=
fun prag => match inl_inline prag with | Inlinable => true | _ => false end.
Definition isAnyInlinePragma : InlinePragma -> bool :=
fun prag =>
match inl_inline prag with
| Inline => true
| Inlinable => true
| _ => false
end.
Definition inlinePragmaSat : InlinePragma -> option Arity :=
inl_sat.
Definition inlinePragmaActivation : InlinePragma -> Activation :=
fun '(Mk_InlinePragma _ _ _ activation _) => activation.
Definition inlinePragmaRuleMatchInfo : InlinePragma -> RuleMatchInfo :=
fun '(Mk_InlinePragma _ _ _ _ info) => info.
Definition setInlinePragmaActivation
: InlinePragma -> Activation -> InlinePragma :=
fun prag activation =>
let 'Mk_InlinePragma inl_src_0__ inl_inline_1__ inl_sat_2__ inl_act_3__
inl_rule_4__ := prag in
Mk_InlinePragma inl_src_0__ inl_inline_1__ inl_sat_2__ activation inl_rule_4__.
Definition setInlinePragmaRuleMatchInfo
: InlinePragma -> RuleMatchInfo -> InlinePragma :=
fun prag info =>
let 'Mk_InlinePragma inl_src_0__ inl_inline_1__ inl_sat_2__ inl_act_3__
inl_rule_4__ := prag in
Mk_InlinePragma inl_src_0__ inl_inline_1__ inl_sat_2__ inl_act_3__ info.
Definition pprInline' : bool -> InlinePragma -> GHC.Base.String :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| emptyInline, Mk_InlinePragma _ inline mb_arity activation info =>
let pp_info :=
if isFunLike info : bool then Panic.someSDoc else
Panic.someSDoc in
let pp_sat :=
match mb_arity with
| Some ar =>
GHC.Base.mappend (Datatypes.id (GHC.Base.hs_string__ "sat-args="))
Panic.someSDoc
| _ => Panic.someSDoc
end in
let pp_act :=
fun arg_4__ arg_5__ =>
match arg_4__, arg_5__ with
| Inline, AlwaysActive => Panic.someSDoc
| NoInline, NeverActive => Panic.someSDoc
| _, act => Panic.someSDoc
end in
let pp_inl :=
fun x => if emptyInline : bool then Panic.someSDoc else Panic.someSDoc in
GHC.Base.mappend (GHC.Base.mappend (GHC.Base.mappend (pp_inl inline) (pp_act
inline activation)) pp_sat) pp_info
end.
Definition pprInline : InlinePragma -> GHC.Base.String :=
pprInline' true.
Definition pprInlineDebug : InlinePragma -> GHC.Base.String :=
pprInline' false.
Definition isActiveIn : PhaseNum -> Activation -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| _, NeverActive => false
| _, AlwaysActive => true
| p, ActiveAfter _ n => p GHC.Base.<= n
| p, ActiveBefore _ n => p GHC.Base.> n
end.
Definition isActive : CompilerPhase -> Activation -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| InitialPhase, AlwaysActive => true
| InitialPhase, ActiveBefore _ _ => true
| InitialPhase, _ => false
| Phase p, act => isActiveIn p act
end.
Definition competesWith : Activation -> Activation -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| NeverActive, _ => false
| _, NeverActive => false
| AlwaysActive, _ => true
| ActiveBefore _ _, AlwaysActive => true
| ActiveBefore _ _, ActiveBefore _ _ => true
| ActiveBefore _ a, ActiveAfter _ b => a GHC.Base.< b
| ActiveAfter _ _, AlwaysActive => false
| ActiveAfter _ _, ActiveBefore _ _ => false
| ActiveAfter _ a, ActiveAfter _ b => a GHC.Base.>= b
end.
Definition isNeverActive : Activation -> bool :=
fun arg_0__ => match arg_0__ with | NeverActive => true | _ => false end.
Definition isEarlyActive : Activation -> bool :=
fun arg_0__ =>
match arg_0__ with
| AlwaysActive => true
| ActiveBefore _ _ => true
| _ => false
end.
(* Skipping definition `BasicTypes.mkIntegralLit' *)
(* Skipping definition `BasicTypes.negateIntegralLit' *)
(* Skipping definition `BasicTypes.mkFractionalLit' *)
(* Skipping definition `BasicTypes.negateFractionalLit' *)
(* Skipping definition `BasicTypes.integralFractionalLit' *)
Definition infinity : IntWithInf :=
Infinity.
Definition intGtLimit : GHC.Num.Int -> IntWithInf -> bool :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| _, Infinity => false
| n, Int m => n GHC.Base.> m
end.
Definition plusWithInf : IntWithInf -> IntWithInf -> IntWithInf :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| Infinity, _ => Infinity
| _, Infinity => Infinity
| Int a, Int b => Int (a GHC.Num.+ b)
end.
Definition mulWithInf : IntWithInf -> IntWithInf -> IntWithInf :=
fun arg_0__ arg_1__ =>
match arg_0__, arg_1__ with
| Infinity, _ => Infinity
| _, Infinity => Infinity
| Int a, Int b => Int (a GHC.Num.* b)
end.
Definition treatZeroAsInf : GHC.Num.Int -> IntWithInf :=
fun arg_0__ =>
let 'num_1__ := arg_0__ in
if num_1__ GHC.Base.== #0 : bool then Infinity else
let 'n := arg_0__ in
Int n.
Definition mkIntWithInf : GHC.Num.Int -> IntWithInf :=
Int.
(* External variables:
Eq Gt Lt None Some andb bool comparison cons false list nat negb op_zt__ option
pair true tt unit Data.Function.on Datatypes.id FastString.FastString
GHC.Base.Eq_ GHC.Base.Ord GHC.Base.String GHC.Base.compare GHC.Base.compare__
GHC.Base.mappend GHC.Base.max__ GHC.Base.min__ GHC.Base.op_zeze__
GHC.Base.op_zeze____ GHC.Base.op_zg__ GHC.Base.op_zg____ GHC.Base.op_zgze__
GHC.Base.op_zgze____ GHC.Base.op_zl__ GHC.Base.op_zl____ GHC.Base.op_zlze__
GHC.Base.op_zlze____ GHC.Base.op_zsze__ GHC.Base.op_zsze____
GHC.Err.Build_Default GHC.Err.Default GHC.Err.default GHC.Err.error GHC.Num.Int
GHC.Num.Integer GHC.Num.fromInteger GHC.Num.op_zp__ GHC.Num.op_zt__ GHC.Prim.seq
GHC.Real.Rational Panic.someSDoc SrcLoc.Located
*)
|
(** * RecordSub: Subtyping with Records *)
Require Export MoreStlc.
(* ###################################################### *)
(** * Core Definitions *)
(* ################################### *)
(** *** Syntax *)
Inductive ty : Type :=
(* proper types *)
| TTop : ty
| TBase : id -> ty
| TArrow : ty -> ty -> ty
(* record types *)
| TRNil : ty
| TRCons : id -> ty -> ty -> ty.
Tactic Notation "T_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "TTop" | Case_aux c "TBase" | Case_aux c "TArrow"
| Case_aux c "TRNil" | Case_aux c "TRCons" ].
Inductive tm : Type :=
(* proper terms *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| tproj : tm -> id -> tm
(* record terms *)
| trnil : tm
| trcons : id -> tm -> tm -> tm.
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp" | Case_aux c "tabs"
| Case_aux c "tproj" | Case_aux c "trnil" | Case_aux c "trcons" ].
(* ################################### *)
(** *** Well-Formedness *)
Inductive record_ty : ty -> Prop :=
| RTnil :
record_ty TRNil
| RTcons : forall i T1 T2,
record_ty (TRCons i T1 T2).
Inductive record_tm : tm -> Prop :=
| rtnil :
record_tm trnil
| rtcons : forall i t1 t2,
record_tm (trcons i t1 t2).
Inductive well_formed_ty : ty -> Prop :=
| wfTTop :
well_formed_ty TTop
| wfTBase : forall i,
well_formed_ty (TBase i)
| wfTArrow : forall T1 T2,
well_formed_ty T1 ->
well_formed_ty T2 ->
well_formed_ty (TArrow T1 T2)
| wfTRNil :
well_formed_ty TRNil
| wfTRCons : forall i T1 T2,
well_formed_ty T1 ->
well_formed_ty T2 ->
record_ty T2 ->
well_formed_ty (TRCons i T1 T2).
Hint Constructors record_ty record_tm well_formed_ty.
(* ################################### *)
(** *** Substitution *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y => if eq_id_dec x y then s else t
| tabs y T t1 => tabs y T (if eq_id_dec x y then t1 else (subst x s t1))
| tapp t1 t2 => tapp (subst x s t1) (subst x s t2)
| tproj t1 i => tproj (subst x s t1) i
| trnil => trnil
| trcons i t1 tr2 => trcons i (subst x s t1) (subst x s tr2)
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ################################### *)
(** *** Reduction *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_rnil : value trnil
| v_rcons : forall i v vr,
value v ->
value vr ->
value (trcons i v vr).
Hint Constructors value.
Fixpoint Tlookup (i:id) (Tr:ty) : option ty :=
match Tr with
| TRCons i' T Tr' => if eq_id_dec i i' then Some T else Tlookup i Tr'
| _ => None
end.
Fixpoint tlookup (i:id) (tr:tm) : option tm :=
match tr with
| trcons i' t tr' => if eq_id_dec i i' then Some t else tlookup i tr'
| _ => None
end.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
| ST_Proj1 : forall tr tr' i,
tr ==> tr' ->
(tproj tr i) ==> (tproj tr' i)
| ST_ProjRcd : forall tr i vi,
value tr ->
tlookup i tr = Some vi ->
(tproj tr i) ==> vi
| ST_Rcd_Head : forall i t1 t1' tr2,
t1 ==> t1' ->
(trcons i t1 tr2) ==> (trcons i t1' tr2)
| ST_Rcd_Tail : forall i v1 tr2 tr2',
value v1 ->
tr2 ==> tr2' ->
(trcons i v1 tr2) ==> (trcons i v1 tr2')
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1" | Case_aux c "ST_App2"
| Case_aux c "ST_Proj1" | Case_aux c "ST_ProjRcd" | Case_aux c "ST_Rcd"
| Case_aux c "ST_Rcd_Head" | Case_aux c "ST_Rcd_Tail" ].
Hint Constructors step.
(* ###################################################################### *)
(** * Subtyping *)
(** Now we come to the interesting part. We begin by defining
the subtyping relation and developing some of its important
technical properties. *)
(* ################################### *)
(** ** Definition *)
(** The definition of subtyping is essentially just what we
sketched in the motivating discussion, but we need to add
well-formedness side conditions to some of the rules. *)
Inductive subtype : ty -> ty -> Prop :=
(* Subtyping between proper types *)
| S_Refl : forall T,
well_formed_ty T ->
subtype T T
| S_Trans : forall S U T,
subtype S U ->
subtype U T ->
subtype S T
| S_Top : forall S,
well_formed_ty S ->
subtype S TTop
| S_Arrow : forall S1 S2 T1 T2,
subtype T1 S1 ->
subtype S2 T2 ->
subtype (TArrow S1 S2) (TArrow T1 T2)
(* Subtyping between record types *)
| S_RcdWidth : forall i T1 T2,
well_formed_ty (TRCons i T1 T2) ->
subtype (TRCons i T1 T2) TRNil
| S_RcdDepth : forall i S1 T1 Sr2 Tr2,
subtype S1 T1 ->
subtype Sr2 Tr2 ->
record_ty Sr2 ->
record_ty Tr2 ->
subtype (TRCons i S1 Sr2) (TRCons i T1 Tr2)
| S_RcdPerm : forall i1 i2 T1 T2 Tr3,
well_formed_ty (TRCons i1 T1 (TRCons i2 T2 Tr3)) ->
i1 <> i2 ->
subtype (TRCons i1 T1 (TRCons i2 T2 Tr3))
(TRCons i2 T2 (TRCons i1 T1 Tr3)).
Hint Constructors subtype.
Tactic Notation "subtype_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "S_Refl" | Case_aux c "S_Trans" | Case_aux c "S_Top"
| Case_aux c "S_Arrow" | Case_aux c "S_RcdWidth"
| Case_aux c "S_RcdDepth" | Case_aux c "S_RcdPerm" ].
(* ############################################### *)
(** ** Subtyping Examples and Exercises *)
Module Examples.
Notation x := (Id 0).
Notation y := (Id 1).
Notation z := (Id 2).
Notation j := (Id 3).
Notation k := (Id 4).
Notation i := (Id 5).
Notation A := (TBase (Id 6)).
Notation B := (TBase (Id 7)).
Notation C := (TBase (Id 8)).
Definition TRcd_j :=
(TRCons j (TArrow B B) TRNil). (* {j:B->B} *)
Definition TRcd_kj :=
TRCons k (TArrow A A) TRcd_j. (* {k:C->C,j:B->B} *)
Example subtyping_example_0 :
subtype (TArrow C TRcd_kj)
(TArrow C TRNil).
(* C->{k:A->A,j:B->B} <: C->{} *)
Proof.
apply S_Arrow.
apply S_Refl. auto.
unfold TRcd_kj, TRcd_j. apply S_RcdWidth; auto.
Qed.
(** The following facts are mostly easy to prove in Coq. To get
full benefit from the exercises, make sure you also
understand how to prove them on paper! *)
(** **** Exercise: 2 stars *)
Example subtyping_example_1 :
subtype TRcd_kj TRcd_j.
(* {k:A->A,j:B->B} <: {j:B->B} *)
Proof with eauto.
unfold TRcd_kj.
unfold TRcd_j.
econstructor.
apply S_RcdPerm...
intros H; inversion H.
apply S_RcdDepth...
Qed.
(** [] *)
(** **** Exercise: 1 star *)
Example subtyping_example_2 :
subtype (TArrow TTop TRcd_kj)
(TArrow (TArrow C C) TRcd_j).
(* Top->{k:A->A,j:B->B} <: (C->C)->{j:B->B} *)
Proof with eauto.
constructor...
apply subtyping_example_1.
Qed.
(** [] *)
(** **** Exercise: 1 star *)
Example subtyping_example_3 :
subtype (TArrow TRNil (TRCons j A TRNil))
(TArrow (TRCons k B TRNil) TRNil).
(* {}->{j:A} <: {k:B}->{} *)
Proof with eauto.
constructor...
Qed.
(** [] *)
(** **** Exercise: 2 stars *)
Example subtyping_example_4 :
subtype (TRCons x A (TRCons y B (TRCons z C TRNil)))
(TRCons z C (TRCons y B (TRCons x A TRNil))).
(* {x:A,y:B,z:C} <: {z:C,y:B,x:A} *)
Proof with eauto.
econstructor.
apply S_RcdPerm...
intros H; inversion H.
econstructor.
apply S_RcdDepth.
constructor...
apply S_RcdPerm...
intros H; inversion H.
eauto.
eauto.
constructor...
intros H; inversion H.
Qed.
(** [] *)
Definition trcd_kj :=
(trcons k (tabs z A (tvar z))
(trcons j (tabs z B (tvar z))
trnil)).
End Examples.
(* ###################################################################### *)
(** ** Properties of Subtyping *)
(** *** Well-Formedness *)
Lemma subtype__wf : forall S T,
subtype S T ->
well_formed_ty T /\ well_formed_ty S.
Proof with eauto.
intros S T Hsub.
subtype_cases (induction Hsub) Case;
intros; try (destruct IHHsub1; destruct IHHsub2)...
Case "S_RcdPerm".
split... inversion H. subst. inversion H5... Qed.
Lemma wf_rcd_lookup : forall i T Ti,
well_formed_ty T ->
Tlookup i T = Some Ti ->
well_formed_ty Ti.
Proof with eauto.
intros i T.
T_cases (induction T) Case; intros; try solve by inversion.
Case "TRCons".
inversion H. subst. unfold Tlookup in H0.
destruct (eq_id_dec i i0)... inversion H0; subst... Qed.
(** *** Field Lookup *)
(** Our record matching lemmas get a little more complicated in
the presence of subtyping for two reasons: First, record
types no longer necessarily describe the exact structure of
corresponding terms. Second, reasoning by induction on
[has_type] derivations becomes harder in general, because
[has_type] is no longer syntax directed. *)
Lemma rcd_types_match : forall S T i Ti,
subtype S T ->
Tlookup i T = Some Ti ->
exists Si, Tlookup i S = Some Si /\ subtype Si Ti.
Proof with (eauto using wf_rcd_lookup).
intros S T i Ti Hsub Hget. generalize dependent Ti.
subtype_cases (induction Hsub) Case; intros Ti Hget;
try solve by inversion.
Case "S_Refl".
exists Ti...
Case "S_Trans".
destruct (IHHsub2 Ti) as [Ui Hui]... destruct Hui.
destruct (IHHsub1 Ui) as [Si Hsi]... destruct Hsi.
exists Si...
Case "S_RcdDepth".
rename i0 into k.
unfold Tlookup. unfold Tlookup in Hget.
destruct (eq_id_dec i k)...
SCase "i = k -- we're looking up the first field".
inversion Hget. subst. exists S1...
Case "S_RcdPerm".
exists Ti. split.
SCase "lookup".
unfold Tlookup. unfold Tlookup in Hget.
destruct (eq_id_dec i i1)...
SSCase "i = i1 -- we're looking up the first field".
destruct (eq_id_dec i i2)...
SSSCase "i = i2 - -contradictory".
destruct H0.
subst...
SCase "subtype".
inversion H. subst. inversion H5. subst... Qed.
(** **** Exercise: 3 stars (rcd_types_match_informal) *)
(** Write a careful informal proof of the [rcd_types_match]
lemma. *)
(*
Induction on [S <: T].
Just apply the constructor and induction hypothesis.
*)
(** [] *)
(** *** Inversion Lemmas *)
(** **** Exercise: 3 stars, optional (sub_inversion_arrow) *)
Lemma sub_inversion_arrow : forall U V1 V2,
subtype U (TArrow V1 V2) ->
exists U1, exists U2,
(U=(TArrow U1 U2)) /\ (subtype V1 U1) /\ (subtype U2 V2).
Proof with eauto.
intros U V1 V2 Hs.
remember (TArrow V1 V2) as V.
generalize dependent V2. generalize dependent V1.
subtype_cases (induction Hs) Case; intros;
try solve by inversion; subst.
Case "S_Refl".
inversion H; subst; clear H.
repeat eapply ex_intro...
Case "S_Trans".
edestruct IHHs2...
destruct H.
destruct H.
destruct H0.
apply IHHs1 in H.
destruct H.
destruct H.
destruct H.
destruct H2.
subst.
repeat eapply ex_intro...
Case "S_Arrow".
inversion HeqV; subst; clear HeqV.
repeat eapply ex_intro...
Qed.
(** [] *)
(* ###################################################################### *)
(** * Typing *)
Definition context := id -> (option ty).
Definition empty : context := (fun _ => None).
Definition extend (Gamma : context) (x:id) (T : ty) :=
fun x' => if eq_id_dec x x' then Some T else Gamma x'.
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
well_formed_ty T ->
has_type Gamma (tvar x) T
| T_Abs : forall Gamma x T11 T12 t12,
well_formed_ty T11 ->
has_type (extend Gamma x T11) t12 T12 ->
has_type Gamma (tabs x T11 t12) (TArrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
has_type Gamma t1 (TArrow T1 T2) ->
has_type Gamma t2 T1 ->
has_type Gamma (tapp t1 t2) T2
| T_Proj : forall Gamma i t T Ti,
has_type Gamma t T ->
Tlookup i T = Some Ti ->
has_type Gamma (tproj t i) Ti
(* Subsumption *)
| T_Sub : forall Gamma t S T,
has_type Gamma t S ->
subtype S T ->
has_type Gamma t T
(* Rules for record terms *)
| T_RNil : forall Gamma,
has_type Gamma trnil TRNil
| T_RCons : forall Gamma i t T tr Tr,
has_type Gamma t T ->
has_type Gamma tr Tr ->
record_ty Tr ->
record_tm tr ->
has_type Gamma (trcons i t tr) (TRCons i T Tr)
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs" | Case_aux c "T_App"
| Case_aux c "T_Proj" | Case_aux c "T_Sub"
| Case_aux c "T_RNil" | Case_aux c "T_RCons" ].
(* ############################################### *)
(** ** Typing Examples *)
Module Examples2.
Import Examples.
(** **** Exercise: 1 star *)
Example typing_example_0 :
has_type empty
(trcons k (tabs z A (tvar z))
(trcons j (tabs z B (tvar z))
trnil))
TRcd_kj.
(* empty |- {k=(\z:A.z), j=(\z:B.z)} : {k:A->A,j:B->B} *)
Proof.
unfold TRcd_kj.
unfold TRcd_j.
auto.
Qed.
(** [] *)
(** **** Exercise: 2 stars *)
Example typing_example_1 :
has_type empty
(tapp (tabs x TRcd_j (tproj (tvar x) j))
(trcd_kj))
(TArrow B B).
(* empty |- (\x:{k:A->A,j:B->B}. x.j) {k=(\z:A.z), j=(\z:B.z)} : B->B *)
Proof with eauto.
econstructor...
econstructor...
econstructor...
eapply T_Sub.
apply typing_example_0.
apply subtyping_example_1.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional *)
Example typing_example_2 :
has_type empty
(tapp (tabs z (TArrow (TArrow C C) TRcd_j)
(tproj (tapp (tvar z)
(tabs x C (tvar x)))
j))
(tabs z (TArrow C C) trcd_kj))
(TArrow B B).
(* empty |- (\z:(C->C)->{j:B->B}. (z (\x:C.x)).j)
(\z:C->C. {k=(\z:A.z), j=(\z:B.z)})
: B->B *)
Proof with eauto.
econstructor...
econstructor...
econstructor...
econstructor...
econstructor...
econstructor...
econstructor...
econstructor...
econstructor...
apply T_Sub with TRcd_kj.
unfold trcd_kj.
unfold TRcd_kj.
unfold TRcd_j.
apply T_RCons...
apply subtyping_example_1.
Qed.
(** [] *)
End Examples2.
(* ###################################################################### *)
(** ** Properties of Typing *)
(** *** Well-Formedness *)
Lemma has_type__wf : forall Gamma t T,
has_type Gamma t T -> well_formed_ty T.
Proof with eauto.
intros Gamma t T Htyp.
has_type_cases (induction Htyp) Case...
Case "T_App".
inversion IHHtyp1...
Case "T_Proj".
eapply wf_rcd_lookup...
Case "T_Sub".
apply subtype__wf in H.
destruct H...
Qed.
Lemma step_preserves_record_tm : forall tr tr',
record_tm tr ->
tr ==> tr' ->
record_tm tr'.
Proof.
intros tr tr' Hrt Hstp.
inversion Hrt; subst; inversion Hstp; subst; eauto.
Qed.
(** *** Field Lookup *)
Lemma lookup_field_in_value : forall v T i Ti,
value v ->
has_type empty v T ->
Tlookup i T = Some Ti ->
exists vi, tlookup i v = Some vi /\ has_type empty vi Ti.
Proof with eauto.
remember empty as Gamma.
intros t T i Ti Hval Htyp. revert Ti HeqGamma Hval.
has_type_cases (induction Htyp) Case; intros; subst; try solve by inversion.
Case "T_Sub".
apply (rcd_types_match S) in H0... destruct H0 as [Si [HgetSi Hsub]].
destruct (IHHtyp Si) as [vi [Hget Htyvi]]...
Case "T_RCons".
simpl in H0. simpl. simpl in H1.
destruct (eq_id_dec i i0).
SCase "i is first".
inversion H1. subst. exists t...
SCase "i in tail".
destruct (IHHtyp2 Ti) as [vi [get Htyvi]]...
inversion Hval... Qed.
(* ########################################## *)
(** *** Progress *)
(** **** Exercise: 3 stars (canonical_forms_of_arrow_types) *)
Lemma canonical_forms_of_arrow_types : forall Gamma s T1 T2,
has_type Gamma s (TArrow T1 T2) ->
value s ->
exists x, exists S1, exists s2,
s = tabs x S1 s2.
Proof with eauto.
intros Gamma s T1 T2 Hty Hv.
remember (TArrow T1 T2) as T.
generalize dependent T1.
generalize dependent T2.
has_type_cases (induction Hty) Case; intros; try solve by inversion...
Case "T_Sub".
subst.
apply sub_inversion_arrow in H.
destruct H.
destruct H.
destruct H.
destruct H0.
eapply IHHty in Hv...
Qed.
(** [] *)
Theorem progress : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
intros t T Ht.
remember empty as Gamma.
revert HeqGamma.
has_type_cases (induction Ht) Case;
intros HeqGamma; subst...
Case "T_Var".
inversion H.
Case "T_App".
right.
destruct IHHt1; subst...
SCase "t1 is a value".
destruct IHHt2; subst...
SSCase "t2 is a value".
destruct (canonical_forms_of_arrow_types empty t1 T1 T2)
as [x [S1 [t12 Heqt1]]]...
subst. exists ([x:=t2]t12)...
SSCase "t2 steps".
destruct H0 as [t2' Hstp]. exists (tapp t1 t2')...
SCase "t1 steps".
destruct H as [t1' Hstp]. exists (tapp t1' t2)...
Case "T_Proj".
right. destruct IHHt...
SCase "rcd is value".
destruct (lookup_field_in_value t T i Ti) as [t' [Hget Ht']]...
SCase "rcd_steps".
destruct H0 as [t' Hstp]. exists (tproj t' i)...
Case "T_RCons".
destruct IHHt1...
SCase "head is a value".
destruct IHHt2...
SSCase "tail steps".
right. destruct H2 as [tr' Hstp].
exists (trcons i t tr')...
SCase "head steps".
right. destruct H1 as [t' Hstp].
exists (trcons i t' tr)... Qed.
(** Informal proof of progress:
Theorem : For any term [t] and type [T], if [empty |- t : T]
then [t] is a value or [t ==> t'] for some term [t'].
Proof : Let [t] and [T] be given such that [empty |- t : T]. We go
by induction on the typing derivation. Cases [T_Abs] and
[T_RNil] are immediate because abstractions and [{}] are always
values. Case [T_Var] is vacuous because variables cannot be
typed in the empty context.
- If the last step in the typing derivation is by [T_App], then
there are terms [t1] [t2] and types [T1] [T2] such that
[t = t1 t2], [T = T2], [empty |- t1 : T1 -> T2] and
[empty |- t2 : T1].
The induction hypotheses for these typing derivations yield
that [t1] is a value or steps, and that [t2] is a value or
steps. We consider each case:
- Suppose [t1 ==> t1'] for some term [t1']. Then
[t1 t2 ==> t1' t2] by [ST_App1].
- Otherwise [t1] is a value.
- Suppose [t2 ==> t2'] for some term [t2']. Then
[t1 t2 ==> t1 t2'] by rule [ST_App2] because [t1] is a value.
- Otherwise, [t2] is a value. By lemma
[canonical_forms_for_arrow_types], [t1 = \x:S1.s2] for some
[x], [S1], and [s2]. And [(\x:S1.s2) t2 ==> [x:=t2]s2] by
[ST_AppAbs], since [t2] is a value.
- If the last step of the derivation is by [T_Proj], then there
is a term [tr], type [Tr] and label [i] such that [t = tr.i],
[empty |- tr : Tr], and [Tlookup i Tr = Some T].
The IH for the typing subderivation gives us that either [tr]
is a value or it steps. If [tr ==> tr'] for some term [tr'],
then [tr.i ==> tr'.i] by rule [ST_Proj1].
Otherwise, [tr] is a value. In this case, lemma
[lookup_field_in_value] yields that there is a term [ti] such
that [tlookup i tr = Some ti]. It follows that [tr.i ==> ti]
by rule [ST_ProjRcd].
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
desired result is exactly the induction hypothesis for the
typing subderivation.
- If the final step of the derivation is by [T_RCons], then there
exist some terms [t1] [tr], types [T1 Tr] and a label [t] such
that [t = {i=t1, tr}], [T = {i:T1, Tr}], [record_tm tr],
[record_tm Tr], [empty |- t1 : T1] and [empty |- tr : Tr].
The induction hypotheses for these typing derivations yield
that [t1] is a value or steps, and that [tr] is a value or
steps. We consider each case:
- Suppose [t1 ==> t1'] for some term [t1']. Then
[{i=t1, tr} ==> {i=t1', tr}] by rule [ST_Rcd_Head].
- Otherwise [t1] is a value.
- Suppose [tr ==> tr'] for some term [tr']. Then
[{i=t1, tr} ==> {i=t1, tr'}] by rule [ST_Rcd_Tail],
since [t1] is a value.
- Otherwise, [tr] is also a value. So, [{i=t1, tr}] is a
value by [v_rcons]. *)
(* ########################################## *)
(** *** Inversion Lemmas *)
Lemma typing_inversion_var : forall Gamma x T,
has_type Gamma (tvar x) T ->
exists S,
Gamma x = Some S /\ subtype S T.
Proof with eauto.
intros Gamma x T Hty.
remember (tvar x) as t.
has_type_cases (induction Hty) Case; intros;
inversion Heqt; subst; try solve by inversion.
Case "T_Var".
exists T...
Case "T_Sub".
destruct IHHty as [U [Hctx HsubU]]... Qed.
Lemma typing_inversion_app : forall Gamma t1 t2 T2,
has_type Gamma (tapp t1 t2) T2 ->
exists T1,
has_type Gamma t1 (TArrow T1 T2) /\
has_type Gamma t2 T1.
Proof with eauto.
intros Gamma t1 t2 T2 Hty.
remember (tapp t1 t2) as t.
has_type_cases (induction Hty) Case; intros;
inversion Heqt; subst; try solve by inversion.
Case "T_App".
exists T1...
Case "T_Sub".
destruct IHHty as [U1 [Hty1 Hty2]]...
assert (Hwf := has_type__wf _ _ _ Hty2).
exists U1... Qed.
Lemma typing_inversion_abs : forall Gamma x S1 t2 T,
has_type Gamma (tabs x S1 t2) T ->
(exists S2, subtype (TArrow S1 S2) T
/\ has_type (extend Gamma x S1) t2 S2).
Proof with eauto.
intros Gamma x S1 t2 T H.
remember (tabs x S1 t2) as t.
has_type_cases (induction H) Case;
inversion Heqt; subst; intros; try solve by inversion.
Case "T_Abs".
assert (Hwf := has_type__wf _ _ _ H0).
exists T12...
Case "T_Sub".
destruct IHhas_type as [S2 [Hsub Hty]]...
Qed.
Lemma typing_inversion_proj : forall Gamma i t1 Ti,
has_type Gamma (tproj t1 i) Ti ->
exists T, exists Si,
Tlookup i T = Some Si /\ subtype Si Ti /\ has_type Gamma t1 T.
Proof with eauto.
intros Gamma i t1 Ti H.
remember (tproj t1 i) as t.
has_type_cases (induction H) Case;
inversion Heqt; subst; intros; try solve by inversion.
Case "T_Proj".
assert (well_formed_ty Ti) as Hwf.
SCase "pf of assertion".
apply (wf_rcd_lookup i T Ti)...
apply has_type__wf in H...
exists T. exists Ti...
Case "T_Sub".
destruct IHhas_type as [U [Ui [Hget [Hsub Hty]]]]...
exists U. exists Ui... Qed.
Lemma typing_inversion_rcons : forall Gamma i ti tr T,
has_type Gamma (trcons i ti tr) T ->
exists Si, exists Sr,
subtype (TRCons i Si Sr) T /\ has_type Gamma ti Si /\
record_tm tr /\ has_type Gamma tr Sr.
Proof with eauto.
intros Gamma i ti tr T Hty.
remember (trcons i ti tr) as t.
has_type_cases (induction Hty) Case;
inversion Heqt; subst...
Case "T_Sub".
apply IHHty in H0.
destruct H0 as [Ri [Rr [HsubRS [HtypRi HtypRr]]]].
exists Ri. exists Rr...
Case "T_RCons".
assert (well_formed_ty (TRCons i T Tr)) as Hwf.
SCase "pf of assertion".
apply has_type__wf in Hty1.
apply has_type__wf in Hty2...
exists T. exists Tr... Qed.
Lemma abs_arrow : forall x S1 s2 T1 T2,
has_type empty (tabs x S1 s2) (TArrow T1 T2) ->
subtype T1 S1
/\ has_type (extend empty x S1) s2 T2.
Proof with eauto.
intros x S1 s2 T1 T2 Hty.
apply typing_inversion_abs in Hty.
destruct Hty as [S2 [Hsub Hty]].
apply sub_inversion_arrow in Hsub.
destruct Hsub as [U1 [U2 [Heq [Hsub1 Hsub2]]]].
inversion Heq; subst... Qed.
(* ########################################## *)
(** *** Context Invariance *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_proj : forall x t i,
appears_free_in x t ->
appears_free_in x (tproj t i)
| afi_rhead : forall x i t tr,
appears_free_in x t ->
appears_free_in x (trcons i t tr)
| afi_rtail : forall x i t tr,
appears_free_in x tr ->
appears_free_in x (trcons i t tr).
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t S,
has_type Gamma t S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
has_type Gamma' t S.
Proof with eauto.
intros. generalize dependent Gamma'.
has_type_cases (induction H) Case;
intros Gamma' Heqv...
Case "T_Var".
apply T_Var... rewrite <- Heqv...
Case "T_Abs".
apply T_Abs... apply IHhas_type. intros x0 Hafi.
unfold extend. destruct (eq_id_dec x x0)...
Case "T_App".
apply T_App with T1...
Case "T_RCons".
apply T_RCons... Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
has_type Gamma t T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
has_type_cases (induction Htyp) Case; subst; inversion Hafi; subst...
Case "T_Abs".
destruct (IHHtyp H5) as [T Hctx]. exists T.
unfold extend in Hctx. rewrite neq_id in Hctx... Qed.
(* ########################################## *)
(** *** Preservation *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (extend Gamma x U) t S ->
has_type empty v U ->
has_type Gamma ([x:=v]t) S.
Proof with eauto.
intros Gamma x U v t S Htypt Htypv.
generalize dependent S. generalize dependent Gamma.
t_cases (induction t) Case; intros; simpl.
Case "tvar".
rename i into y.
destruct (typing_inversion_var _ _ _ Htypt) as [T [Hctx Hsub]].
unfold extend in Hctx.
destruct (eq_id_dec x y)...
SCase "x=y".
subst.
inversion Hctx; subst. clear Hctx.
apply context_invariance with empty...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
destruct (subtype__wf _ _ Hsub)...
Case "tapp".
destruct (typing_inversion_app _ _ _ _ Htypt) as [T1 [Htypt1 Htypt2]].
eapply T_App...
Case "tabs".
rename i into y. rename t into T1.
destruct (typing_inversion_abs _ _ _ _ _ Htypt)
as [T2 [Hsub Htypt2]].
destruct (subtype__wf _ _ Hsub) as [Hwf1 Hwf2].
inversion Hwf2. subst.
apply T_Sub with (TArrow T1 T2)... apply T_Abs...
destruct (eq_id_dec x y).
SCase "x=y".
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
SCase "x<>y".
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
Case "tproj".
destruct (typing_inversion_proj _ _ _ _ Htypt)
as [T [Ti [Hget [Hsub Htypt1]]]]...
Case "trnil".
eapply context_invariance...
intros y Hcontra. inversion Hcontra.
Case "trcons".
destruct (typing_inversion_rcons _ _ _ _ _ Htypt) as
[Ti [Tr [Hsub [HtypTi [Hrcdt2 HtypTr]]]]].
apply T_Sub with (TRCons i Ti Tr)...
apply T_RCons...
SCase "record_ty Tr".
apply subtype__wf in Hsub. destruct Hsub. inversion H0...
SCase "record_tm ([x:=v]t2)".
inversion Hrcdt2; subst; simpl... Qed.
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
intros t t' T HT.
remember empty as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
has_type_cases (induction HT) Case;
intros t' HeqGamma HE; subst; inversion HE; subst...
Case "T_App".
inversion HE; subst...
SCase "ST_AppAbs".
destruct (abs_arrow _ _ _ _ _ HT1) as [HA1 HA2].
apply substitution_preserves_typing with T...
Case "T_Proj".
destruct (lookup_field_in_value _ _ _ _ H2 HT H)
as [vi [Hget Hty]].
rewrite H4 in Hget. inversion Hget. subst...
Case "T_RCons".
eauto using step_preserves_record_tm. Qed.
(** Informal proof of [preservation]:
Theorem: If [t], [t'] are terms and [T] is a type such that
[empty |- t : T] and [t ==> t'], then [empty |- t' : T].
Proof: Let [t] and [T] be given such that [empty |- t : T]. We go
by induction on the structure of this typing derivation, leaving
[t'] general. Cases [T_Abs] and [T_RNil] are vacuous because
abstractions and {} don't step. Case [T_Var] is vacuous as well,
since the context is empty.
- If the final step of the derivation is by [T_App], then there
are terms [t1] [t2] and types [T1] [T2] such that [t = t1 t2],
[T = T2], [empty |- t1 : T1 -> T2] and [empty |- t2 : T1].
By inspection of the definition of the step relation, there are
three ways [t1 t2] can step. Cases [ST_App1] and [ST_App2]
follow immediately by the induction hypotheses for the typing
subderivations and a use of [T_App].
Suppose instead [t1 t2] steps by [ST_AppAbs]. Then
[t1 = \x:S.t12] for some type [S] and term [t12], and
[t' = [x:=t2]t12].
By Lemma [abs_arrow], we have [T1 <: S] and [x:S1 |- s2 : T2].
It then follows by lemma [substitution_preserves_typing] that
[empty |- [x:=t2] t12 : T2] as desired.
- If the final step of the derivation is by [T_Proj], then there
is a term [tr], type [Tr] and label [i] such that [t = tr.i],
[empty |- tr : Tr], and [Tlookup i Tr = Some T].
The IH for the typing derivation gives us that, for any term
[tr'], if [tr ==> tr'] then [empty |- tr' Tr]. Inspection of
the definition of the step relation reveals that there are two
ways a projection can step. Case [ST_Proj1] follows
immediately by the IH.
Instead suppose [tr.i] steps by [ST_ProjRcd]. Then [tr] is a
value and there is some term [vi] such that
[tlookup i tr = Some vi] and [t' = vi]. But by lemma
[lookup_field_in_value], [empty |- vi : Ti] as desired.
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
result is immediate by the induction hypothesis for the typing
subderivation and an application of [T_Sub].
- If the final step of the derivation is by [T_RCons], then there
exist some terms [t1] [tr], types [T1 Tr] and a label [t] such
that [t = {i=t1, tr}], [T = {i:T1, Tr}], [record_tm tr],
[record_tm Tr], [empty |- t1 : T1] and [empty |- tr : Tr].
By the definition of the step relation, [t] must have stepped
by [ST_Rcd_Head] or [ST_Rcd_Tail]. In the first case, the
result follows by the IH for [t1]'s typing derivation and
[T_RCons]. In the second case, the result follows by the IH
for [tr]'s typing derivation, [T_RCons], and a use of the
[step_preserves_record_tm] lemma. *)
(* ###################################################### *)
(** ** Exercises on Typing *)
(** **** Exercise: 2 stars, optional (variations) *)
(** Each part of this problem suggests a different way of
changing the definition of the STLC with records and
subtyping. (These changes are not cumulative: each part
starts from the original language.) In each part, list which
properties (Progress, Preservation, both, or neither) become
false. If a property becomes false, give a counterexample.
- Suppose we add the following typing rule:
Gamma |- t : S1->S2
S1 <: T1 T1 <: S1 S2 <: T2
----------------------------------- (T_Funny1)
Gamma |- t : T1->T2
neither
- Suppose we add the following reduction rule:
------------------ (ST_Funny21)
{} ==> (\x:Top. x)
preservation
[{}] : [RNil]
[\x:Top. x] : [Top -> Top]
- Suppose we add the following subtyping rule:
-------------- (S_Funny3)
{} <: Top->Top
progress
[{} {}]
- Suppose we add the following subtyping rule:
-------------- (S_Funny4)
Top->Top <: {}
progress
[(\x:RNil. x) (\x:Top. x)]
- Suppose we add the following evaluation rule:
----------------- (ST_Funny5)
({} t) ==> (t {})
neither
- Suppose we add the same evaluation rule *and* a new typing rule:
----------------- (ST_Funny5)
({} t) ==> (t {})
---------------------- (T_Funny6)
empty |- {} : Top->Top
preservation
[{} (\x:Nat. x)] : [Top]
[(\x:Nat. x) {}] : None
- Suppose we *change* the arrow subtyping rule to:
S1 <: T1 S2 <: T2
----------------------- (S_Arrow')
S1->S2 <: T1->T2
preservation
[(\f:Person->Nat. (f P)) (\x:Student. (x.gpa))] : [Nat]
[(\x.Student (x.gpa)) P] : None
(** [] *)
*)
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFBBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DFBBP_BEHAVIORAL_PP_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire CLK_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFBBP_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05.03.2016 20:20:22
// Design Name:
// Module Name: data_formatter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module data_formatter
(
input wire GCLK,
input wire RST,
input wire dec,
input wire [7:0] temp_data_in,
input wire [15:0] x_axis_in,
input wire [15:0] y_axis_in,
input wire [15:0] z_axis_in,
output wire [15:0] x_axis_out,
output wire [15:0] y_axis_out,
output wire [15:0] z_axis_out,
output wire [15:0] temp_data_out,
//input wire tx_end,
output wire [15:0] ang_x,
output wire [15:0] ang_y,
output wire [15:0] ang_z
);
//---------------------------------------------------
// Clock for Pmod components
//---------------------------------------------------
wire dclk;
display_clk C1(
.clk(GCLK),
.RST(RST),
.dclk(dclk)
);
//---------------------------------------------------
// Formats data received from PmodGYRO
//---------------------------------------------------
data_controller C0_X(
.clk(GCLK),
.dclk(dclk),
.rst(RST),
.display_sel(dec),
.sel(2'b00),
.data(x_axis_in),
.frmt(x_axis_out)
);
data_controller C0_Y(
.clk(GCLK),
.dclk(dclk),
.rst(RST),
.display_sel(dec),
.sel(2'b01),
.data(y_axis_in),
.frmt(y_axis_out)
);
data_controller C0_Z(
.clk(GCLK),
.dclk(dclk),
.rst(RST),
.display_sel(dec),
.sel(2'b10),
.data(z_axis_in),
.frmt(z_axis_out)
);
data_controller C0_T(
.clk(GCLK),
.dclk(dclk),
.rst(RST),
.display_sel(dec),
.sel(2'b11),
.data({8'd0, temp_data_in}),
.frmt(temp_data_out)
);
reg [15:0] ax_acc = 0;
reg [15:0] ay_acc = 0;
reg [15:0] az_acc = 0;
always @(ang_x) begin
ax_acc <= RST ? 0 : ax_acc + ang_x;
end
data_controller C0_X_ACC(
.clk(GCLK),
.dclk(dclk),
.rst(RST),
.display_sel(dec),
.sel(2'b00),
.data(ax_acc),
.frmt(ang_x)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A41OI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A41OI_BEHAVIORAL_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a41oi (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
// Local signals
wire A4 and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A41OI_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A32O_FUNCTIONAL_PP_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a32o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
and and1 (and1_out , B1, B2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32O_FUNCTIONAL_PP_V |
// Copyright (c) 2013 Andrew Downing
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// Executes a series of instructions. The individual instructions and data are passed in as inputs.
// The instruction and data memories are stored separately because
// I mistakenly thought that only 1 element of a packed array may be read or written in a single clock.
// If I didn't have that misconception, the design could have been simpler.
module Operate
(clk, reset, start, ack, instruc, rdData,
rdEn, wrEn, addr, wrData, pc, done);
// constants
localparam INSTRUC_SIZE = 32, ARG_SIZE = 8, DATA_SIZE = 8,
OP_ADD = 8'h0, OP_SUB = 8'h1, OP_RSHIFT = 8'h2, OP_LSHIFT = 8'h3,
OP_AND = 8'h4, OP_OR = 8'h5, OP_XOR = 8'h6, OP_INV = 8'h7,
OP_JMP = 8'h8, OP_JEQ0 = 8'h9, OP_JGT0 = 8'hA, OP_JLT0 = 8'hB,
OP_LDC = 8'hC, OP_COPY = 8'hD, OP_HALT = 8'hF,
INIT = 3'd0, FETCH = 3'd1, RD_DATA2 = 3'd2, RD_DATA3 = 3'd3, RD_DATA_FINISH = 3'd4, OPERATE = 3'd5, DONE = 3'd6;
// inputs
input clk, reset, start, ack;
input [(INSTRUC_SIZE - 1) : 0] instruc;
input [(DATA_SIZE - 1) : 0] rdData;
// outputs
output reg rdEn; // data read enable
output reg wrEn; // data write enable
output reg [(ARG_SIZE - 1) : 0] addr; // data read/write address
output reg [(DATA_SIZE - 1) : 0] wrData; // data write value
output reg [(ARG_SIZE - 1) : 0] pc; // program counter
output wire done;
reg [2:0] state;
assign done = (state == DONE);
always @(posedge clk, posedge reset)
begin
// set default outputs
rdEn <= 1'b0;
wrEn <= 1'b0;
addr <= 8'bx;
wrData <= 8'bx;
if (reset)
begin
state <= INIT;
end
else
begin : OPERATE_BLOCK
// extract op code and arguments
reg [(ARG_SIZE - 1) : 0] opCode, arg1, arg2, arg3;
reg [(DATA_SIZE - 1) : 0] argData2, argData3; // data corresponding to args 2 and 3
opCode = instruc[31:24];
arg1 = instruc[23:16];
arg2 = instruc[15:8];
arg3 = instruc[7:0];
case (state)
INIT:
begin
if (start) state <= FETCH;
pc <= 1'b0;
end
FETCH:
begin
state <= RD_DATA2;
argData2 <= 8'bx;
argData3 <= 8'bx;
end
RD_DATA2:
begin
if (opCode == OP_JMP || opCode == OP_LDC || opCode == OP_HALT)
state <= OPERATE;
else if (opCode >= OP_INV)
state <= RD_DATA_FINISH;
else
state <= RD_DATA3;
rdEn <= 1'b1;
addr <= arg2;
end
RD_DATA3:
begin
state <= RD_DATA_FINISH;
rdEn <= 1'b1;
addr <= arg3;
end
RD_DATA_FINISH:
begin
state <= OPERATE;
argData2 = rdData;
end
OPERATE:
begin
state <= FETCH;
if (opCode >= OP_INV)
argData2 = rdData;
else
argData3 = rdData;
wrEn <= 1'b1;
addr <= arg1;
wrData <= 8'bx;
pc <= pc + 1'b1;
case (opCode)
OP_ADD:
begin
wrData <= argData2 + argData3;
end
OP_SUB:
begin
wrData <= argData2 - argData3;
end
OP_RSHIFT:
begin
wrData <= argData2 >> argData3;
end
OP_LSHIFT:
begin
wrData <= argData2 << argData3;
end
OP_AND:
begin
wrData <= argData2 & argData3;
end
OP_OR:
begin
wrData <= argData2 | argData3;
end
OP_XOR:
begin
wrData <= argData2 ^ argData3;
end
OP_INV:
begin
wrData <= ~argData2;
end
OP_JMP:
begin
wrEn <= 1'b0;
pc <= arg1;
end
OP_JEQ0:
begin
wrEn <= 1'b0;
if (argData2 == 0) pc <= arg1;
end
OP_JGT0:
begin
wrEn <= 1'b0;
if (argData2 != 0 && argData2[DATA_SIZE - 1] == 1'b0) pc <= arg1;
end
OP_JLT0:
begin
wrEn <= 1'b0;
if (argData2[DATA_SIZE - 1] == 1'b1) pc <= arg1;
end
OP_LDC:
begin
wrData <= arg2;
end
OP_COPY:
begin
wrData <= argData2;
end
OP_HALT:
begin
state <= DONE;
end
endcase
end
DONE:
begin
if (ack) state <= INIT;
end
endcase
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// CLK_DIV2.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao ([email protected]) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2006/06/22 09:01:41 Administrator
// no message
//
// Revision 1.2 2005/12/16 06:44:20 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
//////////////////////////////////////////////////////////////////////
// This file can only used for simulation .
// You need to replace it with your own element according to technology
//////////////////////////////////////////////////////////////////////
module CLK_DIV2 (
input Reset,
input IN,
output reg OUT
);
always @ (posedge IN or posedge Reset)
if (Reset)
OUT <=0;
else
OUT <=!OUT;
endmodule |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:29:48 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_processing_system7_0_2/zynq_design_1_processing_system7_0_2_sim_netlist.v
// Design : zynq_design_1_processing_system7_0_2
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "zynq_design_1_processing_system7_0_2,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.2" *)
(* NotValidForBitStream *)
module zynq_design_1_processing_system7_0_2
(TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *)
(* C_GP1_EN_MODIFIABLE_TXN = "1" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg484" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "zynq_design_1_processing_system7_0_2.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
.GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
.I2C0_SCL_I(1'b0),
.I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
.I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
.I2C0_SDA_I(1'b0),
.I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
.I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(1'b0),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(1'b0),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg484" *) (* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "zynq_design_1_processing_system7_0_2.hwdef" *) (* ORIG_REF_NAME = "processing_system7_v5_5_processing_system7" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module zynq_design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire \<const1> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [0:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]\^M_AXI_GP0_ARCACHE ;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]\^M_AXI_GP0_AWCACHE ;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]\^M_AXI_GP1_ARCACHE ;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]\^M_AXI_GP1_AWCACHE ;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2];
assign M_AXI_GP0_ARCACHE[1] = \<const1> ;
assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0];
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2];
assign M_AXI_GP0_AWCACHE[1] = \<const1> ;
assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2];
assign M_AXI_GP1_ARCACHE[1] = \<const1> ;
assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2];
assign M_AXI_GP1_AWCACHE[1] = \<const1> ;
assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
VCC VCC
(.P(\<const1> ));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module ram_dual_memsplit_2banks
#(
parameter init_type="hex", init_data="data.hex", dat_width=32, adr_width=32, mem_size=1024, P0_FRAC="NO", P1_FRAC="NO"
)
(
input clk_i,
input rst_i,
input [0:0] bus0_bank0_req_i,
input [0:0] bus0_bank0_we_i,
input [31:0] bus0_bank0_addr_bi,
input [3:0] bus0_bank0_be_bi,
input [31:0] bus0_bank0_wdata_bi,
output reg [0:0] bus0_bank0_ack_o,
output reg [0:0] bus0_bank0_resp_o,
output reg [31:0] bus0_bank0_rdata_bo,
input [0:0] bus0_bank1_req_i,
input [0:0] bus0_bank1_we_i,
input [31:0] bus0_bank1_addr_bi,
input [3:0] bus0_bank1_be_bi,
input [31:0] bus0_bank1_wdata_bi,
output reg [0:0] bus0_bank1_ack_o,
output reg [0:0] bus0_bank1_resp_o,
output reg [31:0] bus0_bank1_rdata_bo,
input [0:0] bus1_bank0_req_i,
input [0:0] bus1_bank0_we_i,
input [31:0] bus1_bank0_addr_bi,
input [3:0] bus1_bank0_be_bi,
input [31:0] bus1_bank0_wdata_bi,
output reg [0:0] bus1_bank0_ack_o,
output reg [0:0] bus1_bank0_resp_o,
output reg [31:0] bus1_bank0_rdata_bo,
input [0:0] bus1_bank1_req_i,
input [0:0] bus1_bank1_we_i,
input [31:0] bus1_bank1_addr_bi,
input [3:0] bus1_bank1_be_bi,
input [31:0] bus1_bank1_wdata_bi,
output reg [0:0] bus1_bank1_ack_o,
output reg [0:0] bus1_bank1_resp_o,
output reg [31:0] bus1_bank1_rdata_bo
);
reg bus0_bank0_wb, bus0_bank0_wb_next;
reg bus0_bank1_wb, bus0_bank1_wb_next;
reg bus1_bank0_wb, bus1_bank0_wb_next;
reg bus1_bank1_wb, bus1_bank1_wb_next;
always @(posedge clk_i) bus0_bank0_wb <= rst_i ? 1'b0 : bus0_bank0_wb_next;
always @(posedge clk_i) bus0_bank1_wb <= rst_i ? 1'b0 : bus0_bank1_wb_next;
always @(posedge clk_i) bus1_bank0_wb <= rst_i ? 1'b0 : bus1_bank0_wb_next;
always @(posedge clk_i) bus1_bank1_wb <= rst_i ? 1'b0 : bus1_bank1_wb_next;
reg [31:0] bus0_bank0_addr, bus0_bank0_addr_buf;
reg [3:0] bus0_bank0_be, bus0_bank0_be_buf;
reg bus0_bank0_we;
reg [31:0] bus0_bank0_wdata, bus0_bank0_wdata_buf;
reg bus0_bank0_resp, bus0_bank0_resp_next;
wire [31:0] bus0_bank0_rdata;
reg [31:0] bus0_bank1_addr, bus0_bank1_addr_buf;
reg [3:0] bus0_bank1_be, bus0_bank1_be_buf;
reg bus0_bank1_we;
reg [31:0] bus0_bank1_wdata, bus0_bank1_wdata_buf;
reg bus0_bank1_resp, bus0_bank1_resp_next;
wire [31:0] bus0_bank1_rdata;
reg [31:0] bus1_bank0_addr, bus1_bank0_addr_buf;
reg [3:0] bus1_bank0_be, bus1_bank0_be_buf;
reg bus1_bank0_we;
reg [31:0] bus1_bank0_wdata, bus1_bank0_wdata_buf;
reg bus1_bank0_resp, bus1_bank0_resp_next;
wire [31:0] bus1_bank0_rdata;
reg [31:0] bus1_bank1_addr, bus1_bank1_addr_buf;
reg [3:0] bus1_bank1_be, bus1_bank1_be_buf;
reg bus1_bank1_we;
reg [31:0] bus1_bank1_wdata, bus1_bank1_wdata_buf;
reg bus1_bank1_resp, bus1_bank1_resp_next;
wire [31:0] bus1_bank1_rdata;
reg bus0_rdata_xchg, bus0_rdata_xchg_next;
reg bus1_rdata_xchg, bus1_rdata_xchg_next;
always @(posedge clk_i) bus0_bank0_resp <= rst_i ? 0 : bus0_bank0_resp_next;
always @(posedge clk_i) bus0_bank1_resp <= rst_i ? 0 : bus0_bank1_resp_next;
always @(posedge clk_i) bus1_bank0_resp <= rst_i ? 0 : bus1_bank0_resp_next;
always @(posedge clk_i) bus1_bank1_resp <= rst_i ? 0 : bus1_bank1_resp_next;
always @(posedge clk_i) bus0_rdata_xchg <= rst_i ? 0 : bus0_rdata_xchg_next;
always @(posedge clk_i) bus1_rdata_xchg <= rst_i ? 0 : bus1_rdata_xchg_next;
wire bus0_bank0_we_mask;
wire bus0_bank1_we_mask;
wire bus1_bank0_we_mask;
wire bus1_bank1_we_mask;
assign bus0_bank0_we_mask = bus0_bank0_req_i & bus0_bank0_we_i;
assign bus0_bank1_we_mask = bus0_bank1_req_i & bus0_bank1_we_i;
assign bus1_bank0_we_mask = bus1_bank0_req_i & bus1_bank0_we_i;
assign bus1_bank1_we_mask = bus1_bank1_req_i & bus1_bank1_we_i;
wire bus0_bank0_we_fullword;
wire bus0_bank1_we_fullword;
wire bus1_bank0_we_fullword;
wire bus1_bank1_we_fullword;
assign bus0_bank0_we_fullword = bus0_bank0_we_mask & (bus0_bank0_be_bi == 4'hf);
assign bus0_bank1_we_fullword = bus0_bank1_we_mask & (bus0_bank1_be_bi == 4'hf);
assign bus1_bank0_we_fullword = bus1_bank0_we_mask & (bus1_bank0_be_bi == 4'hf);
assign bus1_bank1_we_fullword = bus1_bank1_we_mask & (bus1_bank1_be_bi == 4'hf);
wire bus0_bank0_we_nfullword;
wire bus0_bank1_we_nfullword;
wire bus1_bank0_we_nfullword;
wire bus1_bank1_we_nfullword;
assign bus0_bank0_we_nfullword = bus0_bank0_we_mask & (bus0_bank0_be_bi != 4'hf);
assign bus0_bank1_we_nfullword = bus0_bank1_we_mask & (bus0_bank1_be_bi != 4'hf);
assign bus1_bank0_we_nfullword = bus1_bank0_we_mask & (bus1_bank0_be_bi != 4'hf);
assign bus1_bank1_we_nfullword = bus1_bank1_we_mask & (bus1_bank1_be_bi != 4'hf);
always @*
begin
bus0_bank0_wb_next = 1'b0;
bus0_bank1_wb_next = 1'b0;
bus0_bank0_addr = bus0_bank0_addr_bi;
bus0_bank0_we = bus0_bank0_we_fullword;
bus0_bank0_be = bus0_bank0_be_bi;
bus0_bank0_wdata = bus0_bank0_wdata_bi;
bus0_bank0_ack_o = bus0_bank0_req_i & !bus0_bank0_wb;
if (P0_FRAC=="YES") bus0_bank0_wb_next = bus0_bank0_we_nfullword & !bus0_bank0_wb;
bus0_bank0_resp_next = bus0_bank0_req_i & !bus0_bank0_we;
bus0_bank1_addr = bus0_bank1_addr_bi;
bus0_bank1_we = bus0_bank1_we_fullword;
bus0_bank1_be = bus0_bank1_be_bi;
bus0_bank1_wdata = bus0_bank1_wdata_bi;
bus0_bank1_ack_o = bus0_bank1_req_i & !bus0_bank1_wb;
if (P0_FRAC=="YES") bus0_bank1_wb_next = bus0_bank1_we_nfullword & !bus0_bank1_wb;
bus0_bank1_resp_next = bus0_bank1_req_i & !bus0_bank1_we;
bus0_rdata_xchg_next = 1'b0;
if (bus0_bank0_req_i)
begin
if (bus0_bank0_addr_bi[2])
begin
bus0_bank1_addr = bus0_bank0_addr_bi;
bus0_bank1_we = bus0_bank0_we_fullword;
bus0_bank1_be = bus0_bank0_be_bi;
bus0_bank1_wdata = bus0_bank0_wdata_bi;
bus0_bank0_we = 1'b0;
bus0_bank0_ack_o = bus0_bank0_req_i & !bus0_bank1_wb;
if (P0_FRAC=="YES") bus0_bank0_wb_next = 1'b0;
if (P0_FRAC=="YES") bus0_bank1_wb_next = bus0_bank0_we_nfullword & !bus0_bank1_wb;
bus0_bank0_resp_next = 1'b0;
bus0_bank1_resp_next = bus0_bank0_req_i & !bus0_bank0_we;
bus0_rdata_xchg_next = 1'b1;
end
end
if (bus0_bank1_req_i)
begin
if (bus0_bank0_req_i && (bus0_bank0_addr_bi[2] == bus0_bank1_addr_bi[2]))
begin
bus0_bank1_ack_o = 1'b0;
if (!bus0_bank1_addr_bi[2]) bus0_bank1_resp_next = 1'b0;
end
else if (!bus0_bank1_addr_bi[2])
begin
bus0_bank0_addr = bus0_bank1_addr_bi;
bus0_bank0_we = bus0_bank1_we_fullword;
bus0_bank0_be = bus0_bank1_be_bi;
bus0_bank0_wdata = bus0_bank1_wdata_bi;
bus0_bank1_ack_o = bus0_bank1_req_i & !bus0_bank0_wb;
if (P0_FRAC=="YES") bus0_bank0_wb_next = bus0_bank1_we_nfullword & !bus0_bank0_wb;
bus0_bank0_resp_next = bus0_bank1_req_i & !bus0_bank1_we;
if (!bus0_bank0_req_i) bus0_bank1_resp_next = 1'b0;
bus0_rdata_xchg_next = 1'b1;
end
end
if (P0_FRAC=="YES")
begin
if (bus0_bank0_wb)
begin
bus0_bank0_addr = bus0_bank0_addr_buf;
bus0_bank0_we = 1'b1;
bus0_bank0_wdata = bus0_bank0_rdata;
case (bus0_bank0_addr_buf[1:0])
2'd0 :
begin
if (bus0_bank0_be_buf[0]) bus0_bank0_wdata[7:0] = bus0_bank0_wdata_buf[7:0];
if (bus0_bank0_be_buf[1]) bus0_bank0_wdata[15:8] = bus0_bank0_wdata_buf[15:8];
if (bus0_bank0_be_buf[2]) bus0_bank0_wdata[23:16] = bus0_bank0_wdata_buf[23:16];
if (bus0_bank0_be_buf[3]) bus0_bank0_wdata[31:24] = bus0_bank0_wdata_buf[31:24];
end
2'd1:
begin
if (bus0_bank0_be_buf[0]) bus0_bank0_wdata[15:8] = bus0_bank0_wdata_buf[7:0];
if (bus0_bank0_be_buf[1]) bus0_bank0_wdata[23:16] = bus0_bank0_wdata_buf[15:8];
if (bus0_bank0_be_buf[2]) bus0_bank0_wdata[31:24] = bus0_bank0_wdata_buf[23:16];
end
2'd2:
begin
if (bus0_bank0_be_buf[0]) bus0_bank0_wdata[23:16] = bus0_bank0_wdata_buf[7:0];
if (bus0_bank0_be_buf[1]) bus0_bank0_wdata[31:24] = bus0_bank0_wdata_buf[15:8];
end
2'd3:
begin
if (bus0_bank0_be_buf[0]) bus0_bank0_wdata[31:24] = bus0_bank0_wdata_buf[7:0];
end
endcase
end
if (bus0_bank1_wb)
begin
bus0_bank1_addr = bus0_bank1_addr_buf;
bus0_bank1_we = 1'b1;
bus0_bank1_wdata = bus0_bank1_rdata;
case (bus0_bank1_addr_buf[1:0])
2'd0 :
begin
if (bus0_bank1_be_buf[0]) bus0_bank1_wdata[7:0] = bus0_bank1_wdata_buf[7:0];
if (bus0_bank1_be_buf[1]) bus0_bank1_wdata[15:8] = bus0_bank1_wdata_buf[15:8];
if (bus0_bank1_be_buf[2]) bus0_bank1_wdata[23:16] = bus0_bank1_wdata_buf[23:16];
if (bus0_bank1_be_buf[3]) bus0_bank1_wdata[31:24] = bus0_bank1_wdata_buf[31:24];
end
2'd1:
begin
if (bus0_bank1_be_buf[0]) bus0_bank1_wdata[15:8] = bus0_bank1_wdata_buf[7:0];
if (bus0_bank1_be_buf[1]) bus0_bank1_wdata[23:16] = bus0_bank1_wdata_buf[15:8];
if (bus0_bank1_be_buf[2]) bus0_bank1_wdata[31:24] = bus0_bank1_wdata_buf[23:16];
end
2'd2:
begin
if (bus0_bank1_be_buf[0]) bus0_bank1_wdata[23:16] = bus0_bank1_wdata_buf[7:0];
if (bus0_bank1_be_buf[1]) bus0_bank1_wdata[31:24] = bus0_bank1_wdata_buf[15:8];
end
2'd3:
begin
if (bus0_bank1_be_buf[0]) bus0_bank1_wdata[31:24] = bus0_bank1_wdata_buf[7:0];
end
endcase
end
end
end
always @*
begin
bus1_bank0_wb_next = 1'b0;
bus1_bank1_wb_next = 1'b0;
bus1_bank0_addr = bus1_bank0_addr_bi;
bus1_bank0_we = bus1_bank0_we_fullword;
bus1_bank0_be = bus1_bank0_be_bi;
bus1_bank0_wdata = bus1_bank0_wdata_bi;
bus1_bank0_ack_o = bus1_bank0_req_i & !bus1_bank0_wb;
if (P1_FRAC=="YES") bus1_bank0_wb_next = bus1_bank0_we_nfullword & !bus1_bank0_wb;
bus1_bank0_resp_next = bus1_bank0_req_i & !bus1_bank0_we;
bus1_bank1_addr = bus1_bank1_addr_bi;
bus1_bank1_we = bus1_bank1_we_fullword;
bus1_bank1_be = bus1_bank1_be_bi;
bus1_bank1_wdata = bus1_bank1_wdata_bi;
bus1_bank1_ack_o = bus1_bank1_req_i & !bus1_bank1_wb;
if (P1_FRAC=="YES") bus1_bank1_wb_next = bus1_bank1_we_nfullword & !bus1_bank1_wb;
bus1_bank1_resp_next = bus1_bank1_req_i & !bus1_bank1_we;
bus1_rdata_xchg_next = 1'b0;
if (bus1_bank0_req_i)
begin
if (bus1_bank0_addr_bi[2])
begin
bus1_bank1_addr = bus1_bank0_addr_bi;
bus1_bank1_we = bus1_bank0_we_fullword;
bus1_bank1_be = bus1_bank0_be_bi;
bus1_bank1_wdata = bus1_bank0_wdata_bi;
bus1_bank0_we = 1'b0;
bus1_bank0_ack_o = bus1_bank0_req_i & !bus1_bank1_wb;
if (P1_FRAC=="YES") bus1_bank0_wb_next = 1'b0;
if (P1_FRAC=="YES") bus1_bank1_wb_next = bus1_bank0_we_nfullword & !bus1_bank1_wb;
bus1_bank0_resp_next = 1'b0;
bus1_bank1_resp_next = bus1_bank0_req_i & !bus1_bank0_we;
bus1_rdata_xchg_next = 1'b1;
end
end
if (bus1_bank1_req_i)
begin
if (bus1_bank0_req_i && (bus1_bank0_addr_bi[2] == bus1_bank1_addr_bi[2]))
begin
bus1_bank1_ack_o = 1'b0;
if (!bus1_bank1_addr_bi[2]) bus1_bank1_resp_next = 1'b0;
end
else if (!bus1_bank1_addr_bi[2])
begin
bus1_bank0_addr = bus1_bank1_addr_bi;
bus1_bank0_we = bus1_bank1_we_fullword;
bus1_bank0_be = bus1_bank1_be_bi;
bus1_bank0_wdata = bus1_bank1_wdata_bi;
bus1_bank1_ack_o = bus1_bank1_req_i & !bus1_bank0_wb;
if (P1_FRAC=="YES") bus1_bank0_wb_next = bus1_bank1_we_nfullword & !bus1_bank0_wb;
bus1_bank0_resp_next = bus1_bank1_req_i & !bus1_bank1_we;
if (!bus1_bank0_req_i) bus1_bank1_resp_next = 1'b0;
bus1_rdata_xchg_next = 1'b1;
end
end
if (P1_FRAC=="YES")
begin
if (bus1_bank0_wb)
begin
bus1_bank0_addr = bus1_bank0_addr_buf;
bus1_bank0_we = 1'b1;
bus1_bank0_wdata = bus1_bank0_rdata;
case (bus1_bank0_addr_buf[1:0])
2'd0 :
begin
if (bus1_bank0_be_buf[0]) bus1_bank0_wdata[7:0] = bus1_bank0_wdata_buf[7:0];
if (bus1_bank0_be_buf[1]) bus1_bank0_wdata[15:8] = bus1_bank0_wdata_buf[15:8];
if (bus1_bank0_be_buf[2]) bus1_bank0_wdata[23:16] = bus1_bank0_wdata_buf[23:16];
if (bus1_bank0_be_buf[3]) bus1_bank0_wdata[31:24] = bus1_bank0_wdata_buf[31:24];
end
2'd1:
begin
if (bus1_bank0_be_buf[0]) bus1_bank0_wdata[15:8] = bus1_bank0_wdata_buf[7:0];
if (bus1_bank0_be_buf[1]) bus1_bank0_wdata[23:16] = bus1_bank0_wdata_buf[15:8];
if (bus1_bank0_be_buf[2]) bus1_bank0_wdata[31:24] = bus1_bank0_wdata_buf[23:16];
end
2'd2:
begin
if (bus1_bank0_be_buf[0]) bus1_bank0_wdata[23:16] = bus1_bank0_wdata_buf[7:0];
if (bus1_bank0_be_buf[1]) bus1_bank0_wdata[31:24] = bus1_bank0_wdata_buf[15:8];
end
2'd3:
begin
if (bus1_bank0_be_buf[0]) bus1_bank0_wdata[31:24] = bus1_bank0_wdata_buf[7:0];
end
endcase
end
if (bus1_bank1_wb)
begin
bus1_bank1_addr = bus1_bank1_addr_buf;
bus1_bank1_we = 1'b1;
bus1_bank1_wdata = bus1_bank1_rdata;
case (bus1_bank1_addr_buf[1:0])
2'd0 :
begin
if (bus1_bank1_be_buf[0]) bus1_bank1_wdata[7:0] = bus1_bank1_wdata_buf[7:0];
if (bus1_bank1_be_buf[1]) bus1_bank1_wdata[15:8] = bus1_bank1_wdata_buf[15:8];
if (bus1_bank1_be_buf[2]) bus1_bank1_wdata[23:16] = bus1_bank1_wdata_buf[23:16];
if (bus1_bank1_be_buf[3]) bus1_bank1_wdata[31:24] = bus1_bank1_wdata_buf[31:24];
end
2'd1:
begin
if (bus1_bank1_be_buf[0]) bus1_bank1_wdata[15:8] = bus1_bank1_wdata_buf[7:0];
if (bus1_bank1_be_buf[1]) bus1_bank1_wdata[23:16] = bus1_bank1_wdata_buf[15:8];
if (bus1_bank1_be_buf[2]) bus1_bank1_wdata[31:24] = bus1_bank1_wdata_buf[23:16];
end
2'd2:
begin
if (bus1_bank1_be_buf[0]) bus1_bank1_wdata[23:16] = bus1_bank1_wdata_buf[7:0];
if (bus1_bank1_be_buf[1]) bus1_bank1_wdata[31:24] = bus1_bank1_wdata_buf[15:8];
end
2'd3:
begin
if (bus1_bank1_be_buf[0]) bus1_bank1_wdata[31:24] = bus1_bank1_wdata_buf[7:0];
end
endcase
end
end
end
always @*
begin
bus0_bank0_resp_o = bus0_bank0_resp;
bus0_bank1_resp_o = bus0_bank1_resp;
bus0_bank0_rdata_bo = bus0_bank0_rdata;
bus0_bank1_rdata_bo = bus0_bank1_rdata;
if (P0_FRAC == "YES")
begin
if (bus0_bank0_addr_buf[1:0] == 2'd1) bus0_bank0_rdata_bo = bus0_bank0_rdata >> 8;
if (bus0_bank0_addr_buf[1:0] == 2'd2) bus0_bank0_rdata_bo = bus0_bank0_rdata >> 16;
if (bus0_bank0_addr_buf[1:0] == 2'd3) bus0_bank0_rdata_bo = bus0_bank0_rdata >> 24;
if (bus0_bank1_addr_buf[1:0] == 2'd1) bus0_bank1_rdata_bo = bus0_bank1_rdata >> 8;
if (bus0_bank1_addr_buf[1:0] == 2'd2) bus0_bank1_rdata_bo = bus0_bank1_rdata >> 16;
if (bus0_bank1_addr_buf[1:0] == 2'd3) bus0_bank1_rdata_bo = bus0_bank1_rdata >> 24;
end
if (bus0_rdata_xchg)
begin
{bus0_bank0_resp_o, bus0_bank1_resp_o} = {bus0_bank1_resp_o, bus0_bank0_resp_o};
{bus0_bank0_rdata_bo, bus0_bank1_rdata_bo} = {bus0_bank1_rdata_bo, bus0_bank0_rdata_bo};
end
end
always @*
begin
bus1_bank0_resp_o = bus1_bank0_resp;
bus1_bank1_resp_o = bus1_bank1_resp;
bus1_bank0_rdata_bo = bus1_bank0_rdata;
bus1_bank1_rdata_bo = bus1_bank1_rdata;
if (P1_FRAC == "YES")
begin
if (bus1_bank0_addr_buf[1:0] == 2'd1) bus1_bank0_rdata_bo = bus1_bank0_rdata >> 8;
if (bus1_bank0_addr_buf[1:0] == 2'd2) bus1_bank0_rdata_bo = bus1_bank0_rdata >> 16;
if (bus1_bank0_addr_buf[1:0] == 2'd3) bus1_bank0_rdata_bo = bus1_bank0_rdata >> 24;
if (bus1_bank1_addr_buf[1:0] == 2'd1) bus1_bank1_rdata_bo = bus1_bank1_rdata >> 8;
if (bus1_bank1_addr_buf[1:0] == 2'd2) bus1_bank1_rdata_bo = bus1_bank1_rdata >> 16;
if (bus1_bank1_addr_buf[1:0] == 2'd3) bus1_bank1_rdata_bo = bus1_bank1_rdata >> 24;
end
if (bus1_rdata_xchg)
begin
{bus1_bank0_resp_o, bus1_bank1_resp_o} = {bus1_bank1_resp_o, bus1_bank0_resp_o};
{bus1_bank0_rdata_bo, bus1_bank1_rdata_bo} = {bus1_bank1_rdata_bo, bus1_bank0_rdata_bo};
end
end
always @(posedge clk_i)
begin
bus0_bank0_addr_buf <= bus0_bank0_addr;
bus0_bank0_be_buf <= bus0_bank0_be;
bus0_bank0_wdata_buf <= bus0_bank0_wdata;
bus0_bank1_addr_buf <= bus0_bank1_addr;
bus0_bank1_be_buf <= bus0_bank1_be;
bus0_bank1_wdata_buf <= bus0_bank1_wdata;
end
always @(posedge clk_i)
begin
bus1_bank0_addr_buf <= bus1_bank0_addr;
bus1_bank0_be_buf <= bus1_bank0_be;
bus1_bank0_wdata_buf <= bus1_bank0_wdata;
bus1_bank1_addr_buf <= bus1_bank1_addr;
bus1_bank1_be_buf <= bus1_bank1_be;
bus1_bank1_wdata_buf <= bus1_bank1_wdata;
end
ram_dual
#(
.init_type("none")
, .init_data("nodata.hex")
, .dat_width(dat_width)
, .adr_width(adr_width-1)
, .mem_size(mem_size >> 1)
) ram_dual_bank0 (
.clk(clk_i)
, .dat0_i(bus0_bank0_wdata)
, .adr0_i(bus0_bank0_addr[31:3])
, .we0_i(bus0_bank0_we)
, .dat0_o(bus0_bank0_rdata)
, .dat1_i(bus1_bank0_wdata)
, .adr1_i(bus1_bank0_addr[31:3])
, .we1_i(bus1_bank0_we)
, .dat1_o(bus1_bank0_rdata)
);
ram_dual
#(
.init_type("none")
, .init_data("nodata.hex")
, .dat_width(dat_width)
, .adr_width(adr_width-1)
, .mem_size(mem_size >> 1)
) ram_dual_bank1 (
.clk(clk_i)
, .dat0_i(bus0_bank1_wdata)
, .adr0_i(bus0_bank1_addr[31:3])
, .we0_i(bus0_bank1_we)
, .dat0_o(bus0_bank1_rdata)
, .dat1_i(bus1_bank1_wdata)
, .adr1_i(bus1_bank1_addr[31:3])
, .we1_i(bus1_bank1_we)
, .dat1_o(bus1_bank1_rdata)
);
// elf processing
integer File_ID, Rd_Status;
reg [7:0] File_Rdata [0 : (mem_size * (dat_width / 8)) - 1] ;
integer File_ptr, header_idx;
integer e_machine, e_phnum, p_offset, p_vaddr, p_filesz, elf_param;
integer bytes_in_word, load_byte_counter;
integer ram_ptr, wrword_byte_counter;
reg [dat_width-1:0] wrword;
reg [8*8:0] e_machine_str;
initial
begin
if (init_type != "none")
begin
if (init_type == "elf")
begin
File_ID = $fopen(init_data, "rb");
Rd_Status = $fread(File_Rdata, File_ID);
if (Rd_Status == 0) $fatal("File %s not found!", init_data);
$display("\n##################################");
$display("#### Loading elf file: %s", init_data);
// parsing ELF header
if ((File_Rdata[0] != 8'h7f) || (File_Rdata[1] != 8'h45) || (File_Rdata[2] != 8'h4c) || (File_Rdata[3] != 8'h46)) $fatal("%s: elf format incorrect!", init_data);
e_machine = File_Rdata[18] + (File_Rdata[19] << 8);
e_machine_str = "UNKNOWN";
if (e_machine == 32'hF3) e_machine_str = "RISC-V";
$display("e_machine: 0x%x (%s)", e_machine, e_machine_str);
e_phnum = File_Rdata[44] + (File_Rdata[45] << 8);
$display("e_phnum: 0x%x", e_phnum);
File_ptr = 52;
for (header_idx = 0; header_idx < e_phnum; header_idx = header_idx + 1)
begin
// parsing program header
$display("---- HEADER: %0d ----", header_idx);
elf_param = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_type: 0x%x", elf_param);
File_ptr = File_ptr + 4;
p_offset = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_offset: 0x%x", p_offset);
File_ptr = File_ptr + 4;
p_vaddr = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_vaddr: 0x%x", p_vaddr);
File_ptr = File_ptr + 4;
elf_param = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_paddr: 0x%x", elf_param);
File_ptr = File_ptr + 4;
p_filesz = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_filesz: 0x%x", p_filesz);
File_ptr = File_ptr + 4;
elf_param = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_memsz: 0x%x", elf_param);
File_ptr = File_ptr + 4;
elf_param = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_flags: 0x%x", elf_param);
File_ptr = File_ptr + 4;
elf_param = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_align: 0x%x", elf_param);
File_ptr = File_ptr + 4;
// loading segment to memory
bytes_in_word = dat_width / 8;
for (load_byte_counter = 0; load_byte_counter < p_filesz; load_byte_counter = load_byte_counter + bytes_in_word)
begin
wrword = 0;
for (wrword_byte_counter = 0; wrword_byte_counter < bytes_in_word; wrword_byte_counter = wrword_byte_counter + 1)
begin
wrword = {File_Rdata[p_offset + load_byte_counter + wrword_byte_counter], wrword[dat_width-1:8]};
end
ram_ptr = (p_vaddr + load_byte_counter) / bytes_in_word;
if (ram_ptr[0] == 1'b0) ram_dual_bank0.ram[ram_ptr >> 1] = wrword;
else ram_dual_bank1.ram[ram_ptr >> 1] = wrword;
end
end
$display("##################################\n");
$fclose(File_ID);
end
else $fatal("init_type parameter incorrect!");
end
end
endmodule
|
// dig
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
`include "cog.v" // cog logic and memory (8 instances)
`include "hub.v" // hub logic and memory
module dig
(
input nres, // reset input (active low)
output [7:0] cfg, // configuration output (set by clkset instruction)
input clk_cog, // cog clock input
input clk_pll, // pll simulator clock input (2x cog clock)
input [31:0] pin_in, // pin state inputs
output [31:0] pin_out, // pin state outputs
output [31:0] pin_dir, // pin direction outputs
output [7:0] cog_led // led outputs to show which cogs are active
);
parameter INVERT_COG_LEDS = 0;
// cnt
reg [31:0] cnt;
always @(posedge clk_cog)
if (nres)
cnt <= cnt + 1'b1;
// bus enable
reg ena_bus;
always @(posedge clk_cog or negedge nres)
if (!nres)
ena_bus <= 1'b0;
else
ena_bus <= !ena_bus;
// bus select
reg [7:0] bus_sel;
always @(posedge clk_cog or negedge nres)
if (!nres)
bus_sel <= 8'b0;
else if (ena_bus)
bus_sel <= {bus_sel[6:0], ~|bus_sel[6:0]};
// cogs
wire [7:0] bus_r;
wire [7:0] bus_e;
wire [7:0] bus_w;
wire [7:0] [1:0] bus_s;
wire [7:0] [15:0] bus_a;
wire [7:0] [31:0] bus_d;
wire [7:0] pll;
wire [7:0] [31:0] outx;
wire [7:0] [31:0] dirx;
genvar i;
generate
for (i=0; i<8; i++)
begin : coggen
cog cog_( .nres (nres),
.clk_cog (clk_cog),
.clk_pll (clk_pll),
.ena_bus (ena_bus),
.ptr_w (ptr_w[i]),
.ptr_d (ptr_d),
.ena (cog_ena[i]),
.bus_sel (bus_sel[i]),
.bus_r (bus_r[i]),
.bus_e (bus_e[i]),
.bus_w (bus_w[i]),
.bus_s (bus_s[i]),
.bus_a (bus_a[i]),
.bus_d (bus_d[i]),
.bus_q (bus_q),
.bus_c (bus_c),
.bus_ack (bus_ack[i]),
.cnt (cnt),
.pll_in (pll),
.pll_out (pll[i]),
.pin_in (pin_in),
.pin_out (outx[i]),
.pin_dir (dirx[i]) );
end
endgenerate
// hub
wire hub_bus_r = |bus_r;
wire hub_bus_e = |bus_e;
wire hub_bus_w = |bus_w;
wire [1:0] hub_bus_s = bus_s[7] | bus_s[6] | bus_s[5] | bus_s[4] | bus_s[3] | bus_s[2] | bus_s[1] | bus_s[0];
wire [15:0] hub_bus_a = bus_a[7] | bus_a[6] | bus_a[5] | bus_a[4] | bus_a[3] | bus_a[2] | bus_a[1] | bus_a[0];
wire [31:0] hub_bus_d = bus_d[7] | bus_d[6] | bus_d[5] | bus_d[4] | bus_d[3] | bus_d[2] | bus_d[1] | bus_d[0];
wire [31:0] bus_q;
wire bus_c;
wire [7:0] bus_ack;
wire [7:0] cog_ena;
wire [7:0] ptr_w;
wire [27:0] ptr_d;
hub hub_ ( .clk_cog (clk_cog),
.ena_bus (ena_bus),
.nres (nres),
.bus_sel (bus_sel),
.bus_r (hub_bus_r),
.bus_e (hub_bus_e),
.bus_w (hub_bus_w),
.bus_s (hub_bus_s),
.bus_a (hub_bus_a),
.bus_d (hub_bus_d),
.bus_q (bus_q),
.bus_c (bus_c),
.bus_ack (bus_ack),
.cog_ena (cog_ena),
.ptr_w (ptr_w),
.ptr_d (ptr_d),
.cfg (cfg) );
// pins
assign pin_out = outx[7] | outx[6] | outx[5] | outx[4] | outx[3] | outx[2] | outx[1] | outx[0];
assign pin_dir = dirx[7] | dirx[6] | dirx[5] | dirx[4] | dirx[3] | dirx[2] | dirx[1] | dirx[0];
// cog leds
assign cog_led = cog_ena ^ { 8{|INVERT_COG_LEDS} };
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211AI_TB_V
`define SKY130_FD_SC_LP__O211AI_TB_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o211ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 C1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 C1 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 C1 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_lp__o211ai dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211AI_TB_V
|
'
//v 20081221 2
//T 56300 40900 9 20 1 0 0 0 1
//gschem place buffers
//T 56300 40600 9 10 1 0 0 0 1
//gschem_buffers.sch
//T 56300 40300 9 10 1 0 0 0 1
//1
//T 57800 40300 9 10 1 0 0 0 1
//1
//T 60300 40600 9 10 1 0 0 0 1
//1.0
//T 60300 40300 9 10 1 0 0 0 1
//Peter Clifton
//B 42000 49400 4200 3600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
//L 41700 49900 41700 53400 3 0 0 0 -1 -1
//L 41700 53400 45900 53400 3 0 0 0 -1 -1
//L 45900 53000 45900 53400 3 0 0 0 -1 -1
//L 45600 53400 45600 53800 3 0 0 0 -1 -1
//L 41400 53800 45600 53800 3 0 0 0 -1 -1
//L 41400 50300 41400 53800 3 0 0 0 -1 -1
//L 41100 50700 41100 54200 3 0 0 0 -1 -1
//L 45300 53800 45300 54200 3 0 0 0 -1 -1
//L 41100 54200 45300 54200 3 0 0 0 -1 -1
//L 41100 51100 40800 51100 3 0 0 0 -1 -1
//L 40800 51100 40800 54600 3 0 0 0 -1 -1
//L 45000 54200 45000 54600 3 0 0 0 -1 -1
//L 40800 54600 45000 54600 3 0 0 0 -1 -1
//L 41400 50700 41100 50700 3 0 0 0 -1 -1
//L 41700 50300 41400 50300 3 0 0 0 -1 -1
//L 42000 49900 41700 49900 3 0 0 0 -1 -1
//T 42200 52600 9 20 1 0 0 0 1
//Paste buffers
//B 47600 46500 6000 4800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
//T 47900 50700 9 20 1 0 0 0 1
//Schematic page
//B 56700 48700 4200 3600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
//T 57000 51700 9 20 1 0 0 0 1
//Place buffer
//B 57400 42200 4500 3000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
//B 57700 42500 3900 1300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
//T 57900 43500 9 10 1 0 0 0 1
//words here
//T 57700 44600 9 20 1 0 0 0 1
//Text entry
//L 52200 43000 52200 44500 3 0 0 0 -1 -1
//L 55200 44500 55200 43000 3 0 0 0 -1 -1
//A 53696 44499 1497 0 180 3 0 0 0 -1 -1
//A 53704 43001 1494 180 180 3 0 0 0 -1 -1
//A 53696 44501 1496 180 180 3 0 0 0 -1 -1
//T 52800 44100 9 20 1 0 0 0 2
//Component
//Library
place #(.x(53300),.y(41900)) (.port(node_8192));
place #(.x(53300),.y(42300)) (.port(node_6573));
place #(.x(53800),.y(41700)) (.port(node_5055));
place #(.x(54300),.y(42100)) (.port(node_6042));
place #(.x(53800),.y(42500)) (.port(node_3395));
!_lm741-1.sym #(.basename(lm741-1.sym)) U? (._(node_8192),._(node_6573),._(node_5055),._(node_6042),._(node_3395));
//T 58400 46600 9 20 1 0 0 0 1
//new
place #(.x(51100),.y(49100)) (.port(node_8330));
place #(.x(49800),.y(48900)) (.port(node_6666));
place #(.x(49800),.y(49300)) (.port(node_773));
!_7400-1.sym #(.basename(7400-1.sym)) U1 (.Y_out(node_8330),.B_in(node_6666),.A_in(node_773));
place #(.x(51100),.y(48000)) (.port(node_5609));
place #(.x(49800),.y(47800)) (.port(node_3090));
place #(.x(49800),.y(48200)) (.port(node_6786));
!_7400-1.sym #(.basename(7400-1.sym)) U2 (.Y_out(node_5609),.B_in(node_3090),.A_in(node_6786));
place #(.x(49600),.y(48900)) (.port(node3756));
net #() net4201 (.p(node_6666),.n(node3756));
place #(.x(49600),.y(48600)) (.port(node6886));
net #() net8588 (.p(node3756),.n(node6886));
place #(.x(51300),.y(48600)) (.port(node3857));
net #() net7372 (.p(node6886),.n(node3857));
place #(.x(51300),.y(48000)) (.port(node7515));
net #() net3984 (.p(node3857),.n(node7515));
place #(.x(51100),.y(48500)) (.port(node3957));
net #() net9012 (.p(node_8330),.n(node3957));
place #(.x(49800),.y(48500)) (.port(node7929));
net #() net1844 (.p(node3957),.n(node7929));
net #() net5902 (.p(node7929),.n(node_6786));
place #(.x(49300),.y(47800)) (.port(node5382));
net #() net5183 (.p(node_3090),.n(node5382));
place #(.x(49300),.y(49300)) (.port(node226));
net #() net1372 (.p(node_773),.n(node226));
place #(.x(51900),.y(49100)) (.port(node7326));
net #() net990 (.p(node_8330),.n(node7326));
place #(.x(51900),.y(48000)) (.port(node5535));
net #() net4087 (.p(node_5609),.n(node5535));
place #(.x(44700),.y(51500)) (.port(node_3899));
place #(.x(43400),.y(51300)) (.port(node_5495));
place #(.x(43400),.y(51700)) (.port(node_1577));
!_7400-1.sym #(.basename(7400-1.sym)) U1 (.Y_out(node_3899),.B_in(node_5495),.A_in(node_1577));
place #(.x(44700),.y(50400)) (.port(node_7294));
place #(.x(43400),.y(50200)) (.port(node_3825));
place #(.x(43400),.y(50600)) (.port(node_4595));
!_7400-1.sym #(.basename(7400-1.sym)) U2 (.Y_out(node_7294),.B_in(node_3825),.A_in(node_4595));
place #(.x(43200),.y(51300)) (.port(node9434));
net #() net4419 (.p(node_5495),.n(node9434));
place #(.x(43200),.y(51000)) (.port(node1206));
net #() net7685 (.p(node9434),.n(node1206));
place #(.x(44900),.y(51000)) (.port(node7793));
net #() net9987 (.p(node1206),.n(node7793));
place #(.x(44900),.y(50400)) (.port(node6874));
net #() net6146 (.p(node7793),.n(node6874));
place #(.x(44700),.y(50900)) (.port(node4));
net #() net5166 (.p(node_3899),.n(node4));
place #(.x(43400),.y(50900)) (.port(node9033));
net #() net7210 (.p(node4),.n(node9033));
net #() net5368 (.p(node9033),.n(node_4595));
place #(.x(42900),.y(50200)) (.port(node877));
net #() net1167 (.p(node_3825),.n(node877));
place #(.x(42900),.y(51700)) (.port(node3421));
net #() net3297 (.p(node_1577),.n(node3421));
place #(.x(45500),.y(51500)) (.port(node5031));
net #() net6060 (.p(node_3899),.n(node5031));
place #(.x(45500),.y(50400)) (.port(node2638));
net #() net4793 (.p(node_7294),.n(node2638));
//A 47707 50297 2996 193 102 3 0 0 0 -1 -1
//L 44700 49800 44700 49500 3 0 0 0 -1 -1
//L 44700 49800 44900 49600 3 0 0 0 -1 -1
//A 50098 39887 13440 56 56 3 0 0 0 -1 -1
//L 57400 51000 57700 51000 3 0 0 0 -1 -1
//L 57700 51000 57500 51200 3 0 0 0 -1 -1
//L 54100 42500 57500 49300 3 0 0 0 -1 -1
//L 59700 43500 58900 49200 3 0 0 0 -1 -1
//L 57500 49300 57200 49100 3 0 0 0 -1 -1
//L 57500 49300 57500 48900 3 0 0 0 -1 -1
//L 58900 49200 58800 48900 3 0 0 0 -1 -1
//L 58900 49200 59100 48900 3 0 0 0 -1 -1
//L 53000 49400 57200 49400 3 0 0 0 -1 -1
//L 57200 50700 53000 50700 3 0 0 0 -1 -1
//L 57200 49400 56900 49500 3 0 0 0 -1 -1
//L 57200 49400 56900 49300 3 0 0 0 -1 -1
//L 53000 50700 53300 50800 3 0 0 0 -1 -1
//L 53000 50700 53300 50600 3 0 0 0 -1 -1
//T 49700 53600 9 20 1 0 0 0 1
//deep copy
//T 45800 48200 9 20 1 0 0 0 1
//deep copy
//T 55400 46700 9 20 1 0 0 0 1
//new
//T 54600 50800 9 20 1 0 0 0 1
//deep copy
//T 54600 51200 9 20 1 0 0 0 1
//move
//T 41700 41800 9 20 1 0 0 0 8
//1 Copy
//2 Copy Multiple
//3 Move (incl. dragging)
//4 Copy (to) Buffer
//5 Paste (from) Buffer
//6 Place component
//7 Place text
//8 Delete
//T 54400 49600 9 20 1 0 0 0 1
//deep copy
//T 54500 51200 9 20 1 0 0 6 1
//1,5,7
//T 54500 50800 9 20 1 0 0 6 1
//2,6
//T 49300 53600 9 20 1 0 0 0 1
//5
//T 55400 47100 9 20 1 0 0 0 1
//6
//T 58400 47000 9 20 1 0 0 0 1
//7
//T 45800 48600 9 20 1 0 0 0 1
//4
//T 54300 49600 9 20 1 0 0 6 1
//1,2
//T 53300 53800 9 20 1 0 0 0 5
//NB: Can always free objects in the place buffer
//All but "move" have a trivial cancel operation
//Can rotate / mirror the place buffer as it does not
//reference any schematic page or paste-buffer objects
//except inside the "move" action
//A 48504 43001 1494 180 180 3 0 0 0 -1 -1
//L 47000 43000 47000 44600 3 0 0 0 -1 -1
//L 50000 43000 50000 44700 3 0 0 0 -1 -1
//A 48496 44701 1496 180 180 3 0 0 0 -1 -1
//A 48496 44699 1497 0 180 3 0 0 0 -1 -1
//L 47300 43600 47300 42500 3 0 0 0 -1 -1
//L 47500 43300 47500 42200 3 0 0 0 -1 -1
//L 47800 43100 47800 42000 3 0 0 0 -1 -1
//L 48200 42900 48200 41800 3 0 0 0 -1 -1
//L 48600 42900 48600 41800 3 0 0 0 -1 -1
//L 49000 43000 49000 41900 3 0 0 0 -1 -1
//L 49400 43200 49400 42100 3 0 0 0 -1 -1
//L 49700 43500 49700 42400 3 0 0 0 -1 -1
//B 47900 44900 1200 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
//L 47900 44900 47900 44700 3 0 0 0 -1 -1
//L 49100 44900 49100 44700 3 0 0 0 -1 -1
//L 53900 44600 53700 44700 3 0 0 0 -1 -1
//T 48000 43800 9 20 1 0 0 0 2
//Delete
//items
//L 50300 47400 48900 45500 3 0 0 0 -1 -1
//L 48900 45500 48900 45700 3 0 0 0 -1 -1
//L 48900 45500 49100 45500 3 0 0 0 -1 -1
//T 49700 46100 9 20 1 0 0 0 1
//8
//T 49700 45700 9 20 1 0 0 0 1
//delete
//A 48496 44601 1496 180 180 3 0 0 0 -1 -1
//T 54300 49000 9 20 1 0 0 6 1
//3
//T 54400 49000 9 20 1 0 0 0 1
//shallow copy
//T 54600 50300 9 20 1 0 0 0 1
//shallow free
//T 54500 50300 9 20 1 0 0 6 1
//3
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: ddr2_idelay_ctrl.v
// /___/ /\ Date Last Modified: $Date: 2009/11/03 04:43:17 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module instantiates the IDELAYCTRL primitive of the Virtex-5 device
// which continuously calibrates the IDELAY elements in the region in case of
// varying operating conditions. It takes a 200MHz clock as an input
//Reference:
//Revision History:
// Rev 1.1 - Parameter IODELAY_GRP added and constraint IODELAY_GROUP added
// on IOELAYCTRL primitive. Generate logic on IDELAYCTRL removed
// since tools will replicate idelactrl primitives.PK. 11/27/08
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_idelay_ctrl #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_v3_4 module. Please refer to
// the mig_v3_4 module for actual values.
parameter IODELAY_GRP = "IODELAY_MIG"
)
(
input clk200,
input rst200,
output idelay_ctrl_rdy
);
/*
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYCTRL u_idelayctrl
(
.RDY(idelay_ctrl_rdy),
.REFCLK(clk200),
.RST(rst200)
);
*/
assign idelay_ctrl_rdy = 1'b1; //FIXME
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVN_4_V
`define SKY130_FD_SC_LP__EINVN_4_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvn_4 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvn_4 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVN_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X, nand0_out, or0_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Andrew Skreen
//
// Create Date: 07/11/2012
// Module Name: data_select
// Project Name: PmodGYRO_Demo
// Target Devices: Nexys3
// Tool versions: ISE 14.1
// Description: Uses "sel" input signals to select data to output on "data" bus.
//
// Revision History:
// Revision 0.01 - File Created (Andrew Skreen)
// Revision 1.00 - Added Comments and Converted to Verilog (Josh Sackos)
//////////////////////////////////////////////////////////////////////////////////////////
// ==============================================================================
// Define Module
// ==============================================================================
module data_select(
x_axis,
y_axis,
z_axis,
temp_data,
data,
sel
);
// ==============================================================================
// Port Declarations
// ==============================================================================
input [15:0] x_axis;
input [15:0] y_axis;
input [15:0] z_axis;
input [7:0] temp_data;
input [1:0] sel;
output [15:0] data;
// ==============================================================================
// Parameters, Registers, and Wires
// ==============================================================================
reg [15:0] data;
// ==============================================================================
// Implementation
// ==============================================================================
always @(sel, x_axis, y_axis, z_axis, temp_data) begin
case (sel)
2'b00 : data <= x_axis;
2'b01 : data <= y_axis;
2'b10 : data <= z_axis;
2'b11 : data <= {8'h00, temp_data};
endcase
end
endmodule
|
module vga(
clk,
reset,
// Horizontal counter
h_counter_next,
// Horizontal sync
h_sync,
// Vertical counter
v_counter_next,
// Veritcal sync
v_sync,
// The next pixel will be displayed.
will_display
);
// Initialize parameters as 640 x 480 @ 60Hz
parameter HORIZONTAL_SYNC_POLARITY = 1'b0;
parameter TIME_HORIZONTAL_VIDEO = 640;
parameter TIME_HORIZONTAL_FRONT_PORCH = 16;
parameter TIME_HORIZONTAL_SYNC_PULSE = 96;
parameter TIME_HORIZONTAL_BACK_PORCH = 48;
parameter TIME_HORIZONTAL =
TIME_HORIZONTAL_VIDEO +
TIME_HORIZONTAL_FRONT_PORCH +
TIME_HORIZONTAL_SYNC_PULSE +
TIME_HORIZONTAL_BACK_PORCH;
parameter VERTICAL_SYNC_POLARITY = 1'b0;
parameter TIME_VERTICAL_VIDEO = 480;
parameter TIME_VERTICAL_FRONT_PORCH = 10;
parameter TIME_VERTICAL_SYNC_PULSE = 2;
parameter TIME_VERTICAL_BACK_PORCH = 33;
parameter TIME_VERTICAL =
TIME_VERTICAL_VIDEO +
TIME_VERTICAL_FRONT_PORCH +
TIME_VERTICAL_SYNC_PULSE +
TIME_VERTICAL_BACK_PORCH;
parameter HORIZONTAL_COUNTER_WIDTH = 10;
parameter VERTICAL_COUNTER_WIDTH = 10;
input clk, reset;
output reg [HORIZONTAL_COUNTER_WIDTH-1:0] h_counter_next;
output h_sync;
output reg [VERTICAL_COUNTER_WIDTH-1:0] v_counter_next;
output v_sync;
output will_display;
reg [HORIZONTAL_COUNTER_WIDTH-1:0] h_counter;
reg [VERTICAL_COUNTER_WIDTH-1:0] v_counter;
assign h_sync =
((h_counter >= (TIME_HORIZONTAL_VIDEO + TIME_HORIZONTAL_FRONT_PORCH)) &&
(h_counter < (TIME_HORIZONTAL_VIDEO + TIME_HORIZONTAL_FRONT_PORCH + TIME_HORIZONTAL_SYNC_PULSE))) ?
HORIZONTAL_SYNC_POLARITY : ~HORIZONTAL_SYNC_POLARITY;
assign v_sync =
((v_counter >= (TIME_VERTICAL_VIDEO + TIME_VERTICAL_FRONT_PORCH)) &&
(v_counter < (TIME_VERTICAL_VIDEO + TIME_VERTICAL_FRONT_PORCH + TIME_VERTICAL_SYNC_PULSE))) ?
VERTICAL_SYNC_POLARITY : ~VERTICAL_SYNC_POLARITY;
assign will_display = h_counter_next < TIME_HORIZONTAL_VIDEO && v_counter_next < TIME_VERTICAL_VIDEO;
always @* begin
if (reset) begin
h_counter_next = 0;
v_counter_next = 0;
end else begin
if (h_counter == TIME_HORIZONTAL - 1) begin
h_counter_next = 0;
if (v_counter == TIME_VERTICAL - 1)
v_counter_next = 0;
else
v_counter_next = v_counter + 1;
end else
h_counter_next = h_counter + 1;
end
end
always @(posedge clk) begin
h_counter <= h_counter_next;
v_counter <= v_counter_next;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:23:11 10/29/2012
// Design Name:
// Module Name: IP_ROM
// Project Name:
// Target Devices:
// Tool versions:
// Description:
// Ö¸Áî´æ´¢Æ÷Ä£¿é
// ÊäÈëÐźţºa
// Êä³öÐźţºinst
// aΪָÁîµØÖ·£¬¸ù¾ÝaµÄµØÖ·´Ó´æ´¢Æ÷ÖÐÈ¡µÃÖ¸ÁʹÓÃinst½«Ö¸ÁîÊä³ö
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module IP_ROM(a,inst
);
input [31:0] a;
output [31:0] inst;
wire [31:0] rom [0:63];
/*
assign rom[6'h00]=32'h20230000;//load r1,0(r3)
assign rom[6'h01]=32'h20430000;//load r2,0(r3)
assign rom[6'h02]=32'h14420001;//addi r2,r2,4
assign rom[6'h03]=32'hffffffff;
assign rom[6'h04]=32'hffffffff;//32'h14210001;//addi r1,r1,1
assign rom[6'h05]=32'h1c210080;//subi r1,r1,128
assign rom[6'h06]=32'hffffffff;
assign rom[6'h07]=32'h28000078;//beq 16'h0078 1EλÖÃÖ¸Áî store r1,0(r3)
assign rom[6'h08]=32'hffffffff;
assign rom[6'h09]=32'hffffffff;
assign rom[6'h0A]=32'h28000078;//beq 16'h0078 1EλÖÃÖ¸Áî store r1,0(r3)*/
assign rom[6'h00]= 32'h20230000;//load r1,0(r3)
assign rom[6'h01]= 32'h14210001;//addi r1,r1,1
assign rom[6'h02]= 32'h24230000;//store r1,0(r3)
assign rom[6'h03]= 32'h1c210080;//subi r1,r1,128
assign rom[6'h04]= 32'h28000020;//beq 16'h0020 -> rom[6'h08] load r1,0(r3)
assign rom[6'h05]= 32'hffffffff;//nop
assign rom[6'h06]= 32'h30000000;//brach 0
assign rom[6'h07]= 32'hffffffff;//nop
assign rom[6'h08]= 32'h20230000;//load r1,0(r3)
assign rom[6'h09]= 32'h20430000;//load r2,0(r3)
assign rom[6'h0A]= 32'h3c410002;//srl r2,r2,1
assign rom[6'h0B]= 32'h08210002;//or r1,r1,r2
assign rom[6'h0C]= 32'h24230000;//store r1,0(r3)
assign rom[6'h0D]= 32'hffffffff;
assign rom[6'h0E]= 32'hffffffff;
assign rom[6'h0F]= 32'hffffffff;
assign rom[6'h10]= 32'hffffffff;
assign rom[6'h11]= 32'hffffffff;
assign rom[6'h12]= 32'hffffffff;
assign rom[6'h13]= 32'hffffffff;
assign rom[6'h14]= 32'hffffffff;
assign rom[6'h15]= 32'hffffffff;
assign rom[6'h16]=32'hffffffff;
assign rom[6'h17]=32'hffffffff;
assign rom[6'h18]=32'hffffffff;
assign rom[6'h19]=32'hffffffff;
assign rom[6'h1A]=32'hffffffff;
assign rom[6'h1B]=32'hffffffff;
assign rom[6'h1C]=32'hffffffff;
assign rom[6'h1D]=32'hffffffff;
assign rom[6'h1E]=32'h24230000;
assign rom[6'h1F]=32'hffffffff;
assign rom[6'h20]=32'hffffffff;
assign rom[6'h21]=32'hffffffff;
assign rom[6'h22]=32'hffffffff;
assign rom[6'h23]=32'hffffffff;
assign rom[6'h24]=32'hffffffff;
assign rom[6'h25]=32'h00000000;
assign rom[6'h26]=32'h00000000;
assign rom[6'h27]=32'h00000000;
assign rom[6'h28]=32'h00000000;
assign rom[6'h29]=32'h00000000;
assign rom[6'h2A]=32'h00000000;
assign rom[6'h2B]=32'h00000000;
assign rom[6'h2C]=32'h00000000;
assign rom[6'h2D]=32'h00000000;
assign rom[6'h2E]=32'h00000000;
assign rom[6'h2F]=32'h00000000;
assign rom[6'h30]=32'h00000000;
assign rom[6'h31]=32'h00000000;
assign rom[6'h32]=32'h00000000;
assign rom[6'h33]=32'h00000000;
assign rom[6'h34]=32'h00000000;
assign rom[6'h35]=32'h00000000;
assign rom[6'h36]=32'h00000000;
assign rom[6'h37]=32'h00000000;
assign rom[6'h38]=32'h00000000;
assign rom[6'h39]=32'h00000000;
assign rom[6'h3A]=32'h00000000;
assign rom[6'h3B]=32'h00000000;
assign rom[6'h3C]=32'h00000000;
assign rom[6'h3D]=32'h00000000;
assign rom[6'h3E]=32'h00000000;
assign rom[6'h3F]=32'h00000000;
assign inst=rom[a[7:2]];
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_axi_basic_tx_thrtl_ctl.v
// Version : 1.11
// //
// Description: //
// TX throttle controller. Anticipates back-pressure from PCIe block and //
// preemptively back-pressures user design (packet boundary throttling). //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// axi_basic_tx_thrtl_ctl //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module PCIEBus_axi_basic_tx_thrtl_ctl #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter TCQ = 1 // Clock to Q time
) (
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
input [3:0] s_axis_tx_tuser, // TX user signals
input s_axis_tx_tlast, // TX data is last
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
// TRN TX
//-----------
input [5:0] trn_tbuf_av, // TX buffers available
input trn_tdst_rdy, // TX destination ready
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // TX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output reg cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output reg tready_thrtl, // TREADY to pipeline
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Thrtl user when TBUF hits this val
localparam TBUF_AV_MIN = (C_DATA_WIDTH == 128) ? 5 :
(C_DATA_WIDTH == 64) ? 1 : 0;
// Pause user when TBUF hits this val
localparam TBUF_AV_GAP = TBUF_AV_MIN + 1;
// GAP pause time - the latency from the time a packet is accepted on the TRN
// interface to the time trn_tbuf_av from the Block will decrement.
localparam TBUF_GAP_TIME = (C_DATA_WIDTH == 128) ? 4 : 1;
// Latency time from when tcfg_gnt is asserted to when PCIe block will throttle
localparam TCFG_LATENCY_TIME = 2'd2;
// Number of pipeline stages to delay trn_tcfg_gnt. For V6 128-bit only
localparam TCFG_GNT_PIPE_STAGES = 3;
// Throttle condition registers and constants
reg lnk_up_thrtl;
wire lnk_up_trig;
wire lnk_up_exit;
reg tbuf_av_min_thrtl;
wire tbuf_av_min_trig;
reg tbuf_av_gap_thrtl;
reg [2:0] tbuf_gap_cnt;
wire tbuf_av_gap_trig;
wire tbuf_av_gap_exit;
wire gap_trig_tlast;
wire gap_trig_decr;
reg [5:0] tbuf_av_d;
reg tcfg_req_thrtl;
reg [1:0] tcfg_req_cnt;
reg trn_tdst_rdy_d;
wire tcfg_req_trig;
wire tcfg_req_exit;
reg tcfg_gnt_log;
wire pre_throttle;
wire reg_throttle;
wire exit_crit;
reg reg_tcfg_gnt;
reg trn_tcfg_req_d;
reg tcfg_gnt_pending;
wire wire_to_turnoff;
reg reg_turnoff_ok;
reg tready_thrtl_mux;
localparam LINKSTATE_L0 = 3'b000;
localparam LINKSTATE_PPM_L1 = 3'b001;
localparam LINKSTATE_PPM_L1_TRANS = 3'b101;
localparam LINKSTATE_PPM_L23R_TRANS = 3'b110;
localparam PM_ENTER_L1 = 8'h20;
localparam POWERSTATE_D0 = 2'b00;
reg ppm_L1_thrtl;
wire ppm_L1_trig;
wire ppm_L1_exit;
reg [2:0] cfg_pcie_link_state_d;
reg trn_rdllp_src_rdy_d;
reg ppm_L23_thrtl;
wire ppm_L23_trig;
reg cfg_turnoff_ok_pending;
reg reg_tlast;
// Throttle control state machine states and registers
localparam IDLE = 0;
localparam THROTTLE = 1;
reg cur_state;
reg next_state;
reg reg_axi_in_pkt;
wire axi_in_pkt;
wire axi_pkt_ending;
wire axi_throttled;
wire axi_thrtl_ok;
wire tx_ecrc_pause;
//----------------------------------------------------------------------------//
// THROTTLE REASON: PCIe link is down //
// - When to throttle: trn_lnk_up deasserted //
// - When to stop: trn_tdst_rdy assesrted //
//----------------------------------------------------------------------------//
assign lnk_up_trig = !trn_lnk_up;
assign lnk_up_exit = trn_tdst_rdy;
always @(posedge user_clk) begin
if(user_rst) begin
lnk_up_thrtl <= #TCQ 1'b1;
end
else begin
if(lnk_up_trig) begin
lnk_up_thrtl <= #TCQ 1'b1;
end
else if(lnk_up_exit) begin
lnk_up_thrtl <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Transmit buffers depleted //
// - When to throttle: trn_tbuf_av falls to 0 //
// - When to stop: trn_tbuf_av rises above 0 again //
//----------------------------------------------------------------------------//
assign tbuf_av_min_trig = (trn_tbuf_av <= TBUF_AV_MIN);
always @(posedge user_clk) begin
if(user_rst) begin
tbuf_av_min_thrtl <= #TCQ 1'b0;
end
else begin
if(tbuf_av_min_trig) begin
tbuf_av_min_thrtl <= #TCQ 1'b1;
end
// The exit condition for tbuf_av_min_thrtl is !tbuf_av_min_trig
else begin
tbuf_av_min_thrtl <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Transmit buffers getting low //
// - When to throttle: trn_tbuf_av falls below "gap" threshold TBUF_AV_GAP //
// - When to stop: after TBUF_GAP_TIME cycles elapse //
// //
// If we're about to run out of transmit buffers, throttle the user for a //
// few clock cycles to give the PCIe block time to catch up. This is //
// needed to compensate for latency in decrementing trn_tbuf_av in the PCIe //
// Block transmit path. //
//----------------------------------------------------------------------------//
// Detect two different scenarios for buffers getting low:
// 1) If we see a TLAST. a new packet has been inserted into the buffer, and
// we need to pause and let that packet "soak in"
assign gap_trig_tlast = (trn_tbuf_av <= TBUF_AV_GAP) &&
s_axis_tx_tvalid && tready_thrtl && s_axis_tx_tlast;
// 2) Any time tbug_avail decrements to the TBUF_AV_GAP threshold, we need to
// pause and make sure no other packets are about to soak in and cause the
// buffer availability to drop further.
assign gap_trig_decr = (trn_tbuf_av == (TBUF_AV_GAP)) &&
(tbuf_av_d == (TBUF_AV_GAP+1));
assign gap_trig_tcfg = (tcfg_req_thrtl && tcfg_req_exit);
assign tbuf_av_gap_trig = gap_trig_tlast || gap_trig_decr || gap_trig_tcfg;
assign tbuf_av_gap_exit = (tbuf_gap_cnt == 0);
always @(posedge user_clk) begin
if(user_rst) begin
tbuf_av_gap_thrtl <= #TCQ 1'b0;
tbuf_gap_cnt <= #TCQ 3'h0;
tbuf_av_d <= #TCQ 6'h00;
end
else begin
if(tbuf_av_gap_trig) begin
tbuf_av_gap_thrtl <= #TCQ 1'b1;
end
else if(tbuf_av_gap_exit) begin
tbuf_av_gap_thrtl <= #TCQ 1'b0;
end
// tbuf gap counter:
// This logic controls the length of the throttle condition when tbufs are
// getting low.
if(tbuf_av_gap_thrtl && (cur_state == THROTTLE)) begin
if(tbuf_gap_cnt > 0) begin
tbuf_gap_cnt <= #TCQ tbuf_gap_cnt - 3'd1;
end
end
else begin
tbuf_gap_cnt <= #TCQ TBUF_GAP_TIME;
end
tbuf_av_d <= #TCQ trn_tbuf_av;
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Block needs to send a CFG response //
// - When to throttle: trn_tcfg_req and user_tcfg_gnt asserted //
// - When to stop: after trn_tdst_rdy transitions to unasserted //
// //
// If the block needs to send a response to a CFG packet, this will cause //
// the subsequent deassertion of trn_tdst_rdy. When the user design permits, //
// grant permission to the block to service request and throttle the user. //
//----------------------------------------------------------------------------//
assign tcfg_req_trig = trn_tcfg_req && reg_tcfg_gnt;
assign tcfg_req_exit = (tcfg_req_cnt == 2'd0) && !trn_tdst_rdy_d &&
trn_tdst_rdy;
always @(posedge user_clk) begin
if(user_rst) begin
tcfg_req_thrtl <= #TCQ 1'b0;
trn_tcfg_req_d <= #TCQ 1'b0;
trn_tdst_rdy_d <= #TCQ 1'b1;
reg_tcfg_gnt <= #TCQ 1'b0;
tcfg_req_cnt <= #TCQ 2'd0;
tcfg_gnt_pending <= #TCQ 1'b0;
end
else begin
if(tcfg_req_trig) begin
tcfg_req_thrtl <= #TCQ 1'b1;
end
else if(tcfg_req_exit) begin
tcfg_req_thrtl <= #TCQ 1'b0;
end
// We need to wait the appropriate amount of time for the tcfg_gnt to
// "sink in" to the PCIe block. After that, we know that the PCIe block will
// not reassert trn_tdst_rdy until the CFG request has been serviced. If a
// new request is being service (tcfg_gnt_log == 1), then reset the timer.
if((trn_tcfg_req && !trn_tcfg_req_d) || tcfg_gnt_pending) begin
tcfg_req_cnt <= #TCQ TCFG_LATENCY_TIME;
end
else begin
if(tcfg_req_cnt > 0) begin
tcfg_req_cnt <= #TCQ tcfg_req_cnt - 2'd1;
end
end
// Make sure tcfg_gnt_log pulses once for one clock cycle for every
// cfg packet request.
if(trn_tcfg_req && !trn_tcfg_req_d) begin
tcfg_gnt_pending <= #TCQ 1'b1;
end
else if(tcfg_gnt_log) begin
tcfg_gnt_pending <= #TCQ 1'b0;
end
trn_tcfg_req_d <= #TCQ trn_tcfg_req;
trn_tdst_rdy_d <= #TCQ trn_tdst_rdy;
reg_tcfg_gnt <= #TCQ user_tcfg_gnt;
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Block needs to transition to low power state PPM L1 //
// - When to throttle: appropriate low power state signal asserted //
// (architecture dependent) //
// - When to stop: cfg_pcie_link_state goes to proper value (C_ROOT_PORT //
// dependent) //
// //
// If the block needs to transition to PM state PPM L1, we need to finish //
// up what we're doing and throttle immediately. //
//----------------------------------------------------------------------------//
generate
// PPM L1 signals for 7 Series in RC mode
if((C_FAMILY == "X7") && (C_ROOT_PORT == "TRUE")) begin : x7_L1_thrtl_rp
assign ppm_L1_trig = (cfg_pcie_link_state_d == LINKSTATE_L0) &&
(cfg_pcie_link_state == LINKSTATE_PPM_L1_TRANS);
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_PPM_L1;
end
// PPM L1 signals for 7 Series in EP mode
else if((C_FAMILY == "X7") && (C_ROOT_PORT == "FALSE")) begin : x7_L1_thrtl_ep
assign ppm_L1_trig = (cfg_pcie_link_state_d == LINKSTATE_L0) &&
(cfg_pcie_link_state == LINKSTATE_PPM_L1_TRANS);
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_L0;
end
// PPM L1 signals for V6 in RC mode
else if((C_FAMILY == "V6") && (C_ROOT_PORT == "TRUE")) begin : v6_L1_thrtl_rp
assign ppm_L1_trig = (trn_rdllp_data[31:24] == PM_ENTER_L1) &&
trn_rdllp_src_rdy && !trn_rdllp_src_rdy_d;
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_PPM_L1;
end
// PPM L1 signals for V6 in EP mode
else if((C_FAMILY == "V6") && (C_ROOT_PORT == "FALSE")) begin : v6_L1_thrtl_ep
assign ppm_L1_trig = (cfg_pmcsr_powerstate != POWERSTATE_D0);
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_L0;
end
// PPM L1 detection not supported for S6
else begin : s6_L1_thrtl
assign ppm_L1_trig = 1'b0;
assign ppm_L1_exit = 1'b1;
end
endgenerate
always @(posedge user_clk) begin
if(user_rst) begin
ppm_L1_thrtl <= #TCQ 1'b0;
cfg_pcie_link_state_d <= #TCQ 3'b0;
trn_rdllp_src_rdy_d <= #TCQ 1'b0;
end
else begin
if(ppm_L1_trig) begin
ppm_L1_thrtl <= #TCQ 1'b1;
end
else if(ppm_L1_exit) begin
ppm_L1_thrtl <= #TCQ 1'b0;
end
cfg_pcie_link_state_d <= #TCQ cfg_pcie_link_state;
trn_rdllp_src_rdy_d <= #TCQ trn_rdllp_src_rdy;
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Block needs to transition to low power state PPM L2/3 //
// - When to throttle: appropriate PM signal indicates a transition to //
// L2/3 is pending or in progress (family and role dependent) //
// - When to stop: never (the only path out of L2/3 is a full reset) //
// //
// If the block needs to transition to PM state PPM L2/3, we need to finish //
// up what we're doing and throttle when the user gives permission. //
//----------------------------------------------------------------------------//
generate
// PPM L2/3 signals for 7 Series in RC mode
if((C_FAMILY == "X7") && (C_ROOT_PORT == "TRUE")) begin : x7_L23_thrtl_rp
assign ppm_L23_trig = (cfg_pcie_link_state_d == LINKSTATE_PPM_L23R_TRANS);
assign wire_to_turnoff = 1'b0;
end
// PPM L2/3 signals for V6 in RC mode
else if((C_FAMILY == "V6") && (C_ROOT_PORT == "TRUE")) begin : v6_L23_thrtl_rp
assign ppm_L23_trig = cfg_pm_send_pme_to;
assign wire_to_turnoff = 1'b0;
end
// PPM L2/3 signals in EP mode
else begin : L23_thrtl_ep
assign ppm_L23_trig = wire_to_turnoff && reg_turnoff_ok;
// PPM L2/3 signals for 7 Series in EP mode
// For 7 Series, cfg_to_turnoff pulses once when a turnoff request is
// outstanding, so we need a "sticky" register that grabs the request.
if(C_FAMILY == "X7") begin : x7_L23_thrtl_ep
reg reg_to_turnoff;
always @(posedge user_clk) begin
if(user_rst) begin
reg_to_turnoff <= #TCQ 1'b0;
end
else begin
if(cfg_to_turnoff) begin
reg_to_turnoff <= #TCQ 1'b1;
end
end
end
assign wire_to_turnoff = reg_to_turnoff;
end
// PPM L2/3 signals for V6/S6 in EP mode
// In V6 and S6, the to_turnoff signal asserts and remains asserted until
// turnoff_ok is asserted, so a sticky reg is not necessary.
else begin : v6_s6_L23_thrtl_ep
assign wire_to_turnoff = cfg_to_turnoff;
end
always @(posedge user_clk) begin
if(user_rst) begin
reg_turnoff_ok <= #TCQ 1'b0;
end
else begin
reg_turnoff_ok <= #TCQ user_turnoff_ok;
end
end
end
endgenerate
always @(posedge user_clk) begin
if(user_rst) begin
ppm_L23_thrtl <= #TCQ 1'b0;
cfg_turnoff_ok_pending <= #TCQ 1'b0;
end
else begin
if(ppm_L23_trig) begin
ppm_L23_thrtl <= #TCQ 1'b1;
end
// Make sure cfg_turnoff_ok pulses once for one clock cycle for every
// turnoff request.
if(ppm_L23_trig && !ppm_L23_thrtl) begin
cfg_turnoff_ok_pending <= #TCQ 1'b1;
end
else if(cfg_turnoff_ok) begin
cfg_turnoff_ok_pending <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// Create axi_thrtl_ok. This signal determines if it's OK to throttle the //
// user design on the AXI interface. Since TREADY is registered, this signal //
// needs to assert on the cycle ~before~ we actually intend to throttle. //
// The only time it's OK to throttle when TVALID is asserted is on the first //
// beat of a new packet. Therefore, assert axi_thrtl_ok if one of the //
// is true: //
// 1) The user is not in a packet and is not starting one //
// 2) The user is just finishing a packet //
// 3) We're already throttled, so it's OK to continue throttling //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
reg_axi_in_pkt <= #TCQ 1'b0;
end
else begin
if(s_axis_tx_tvalid && s_axis_tx_tlast) begin
reg_axi_in_pkt <= #TCQ 1'b0;
end
else if(tready_thrtl && s_axis_tx_tvalid) begin
reg_axi_in_pkt <= #TCQ 1'b1;
end
end
end
assign axi_in_pkt = s_axis_tx_tvalid || reg_axi_in_pkt;
assign axi_pkt_ending = s_axis_tx_tvalid && s_axis_tx_tlast;
assign axi_throttled = !tready_thrtl;
assign axi_thrtl_ok = !axi_in_pkt || axi_pkt_ending || axi_throttled;
//----------------------------------------------------------------------------//
// Throttle CTL State Machine: //
// Throttle user design when a throttle trigger (or triggers) occur. //
// Keep user throttled until all exit criteria have been met. //
//----------------------------------------------------------------------------//
// Immediate throttle signal. Used to "pounce" on a throttle opportunity when
// we're seeking one
assign pre_throttle = tbuf_av_min_trig || tbuf_av_gap_trig || lnk_up_trig
|| tcfg_req_trig || ppm_L1_trig || ppm_L23_trig;
// Registered throttle signals. Used to control throttle state machine
assign reg_throttle = tbuf_av_min_thrtl || tbuf_av_gap_thrtl || lnk_up_thrtl
|| tcfg_req_thrtl || ppm_L1_thrtl || ppm_L23_thrtl;
assign exit_crit = !tbuf_av_min_thrtl && !tbuf_av_gap_thrtl && !lnk_up_thrtl
&& !tcfg_req_thrtl && !ppm_L1_thrtl && !ppm_L23_thrtl;
always @(*) begin
case(cur_state)
// IDLE: in this state we're waiting for a trigger event to occur. As
// soon as an event occurs and the user isn't transmitting a packet, we
// throttle the PCIe block and the user and next state is THROTTLE.
IDLE: begin
if(reg_throttle && axi_thrtl_ok) begin
// Throttle user
tready_thrtl_mux = 1'b0;
next_state = THROTTLE;
// Assert appropriate grant signal depending on the throttle type.
if(tcfg_req_thrtl) begin
tcfg_gnt_log = 1'b1; // For cfg request, grant the request
cfg_turnoff_ok = 1'b0; //
end
else if(ppm_L23_thrtl) begin
tcfg_gnt_log = 1'b0; //
cfg_turnoff_ok = 1'b1; // For PM request, permit transition
end
else begin
tcfg_gnt_log = 1'b0; // Otherwise do nothing
cfg_turnoff_ok = 1'b0; //
end
end
// If there's not throttle event, do nothing
else begin
// Throttle user as soon as possible
tready_thrtl_mux = !(axi_thrtl_ok && pre_throttle);
next_state = IDLE;
tcfg_gnt_log = 1'b0;
cfg_turnoff_ok = 1'b0;
end
end
// THROTTLE: in this state the user is throttle and we're waiting for
// exit criteria, which tells us that the throttle event is over. When
// the exit criteria is satisfied, de-throttle the user and next state
// is IDLE.
THROTTLE: begin
if(exit_crit) begin
// Dethrottle user
tready_thrtl_mux = !pre_throttle;
next_state = IDLE;
end
else begin
// Throttle user
tready_thrtl_mux = 1'b0;
next_state = THROTTLE;
end
// Assert appropriate grant signal depending on the throttle type.
if(tcfg_req_thrtl && tcfg_gnt_pending) begin
tcfg_gnt_log = 1'b1; // For cfg request, grant the request
cfg_turnoff_ok = 1'b0; //
end
else if(cfg_turnoff_ok_pending) begin
tcfg_gnt_log = 1'b0; //
cfg_turnoff_ok = 1'b1; // For PM request, permit transition
end
else begin
tcfg_gnt_log = 1'b0; // Otherwise do nothing
cfg_turnoff_ok = 1'b0; //
end
end
default: begin
tready_thrtl_mux = 1'b0;
next_state = IDLE;
tcfg_gnt_log = 1'b0;
cfg_turnoff_ok = 1'b0;
end
endcase
end
// Synchronous logic
always @(posedge user_clk) begin
if(user_rst) begin
// Throttle user by default until link comes up
cur_state <= #TCQ THROTTLE;
reg_tlast <= #TCQ 1'b0;
tready_thrtl <= #TCQ 1'b0;
end
else begin
cur_state <= #TCQ next_state;
tready_thrtl <= #TCQ tready_thrtl_mux && !tx_ecrc_pause;
reg_tlast <= #TCQ s_axis_tx_tlast;
end
end
// For X7, the PCIe block will generate the ECRC for a packet if trn_tecrc_gen
// is asserted at SOF. In this case, the Block needs an extra data beat to
// calculate the ECRC, but only if the following conditions are met:
// 1) there is no empty DWORDS at the end of the packet
// (i.e. packet length % C_DATA_WIDTH == 0)
//
// 2) There isn't a ECRC in the TLP already, as indicated by the TD bit in the
// TLP header
//
// If both conditions are met, the Block will stall the TRN interface for one
// data beat after EOF. We need to predict this stall and preemptively stall the
// User for one beat.
generate
if(C_FAMILY == "X7") begin : ecrc_pause_enabled
wire tx_ecrc_pkt;
reg reg_tx_ecrc_pkt;
wire [1:0] packet_fmt;
wire packet_td;
wire [2:0] header_len;
wire [9:0] payload_len;
wire [13:0] packet_len;
wire pause_needed;
// Grab necessary packet fields
assign packet_fmt = s_axis_tx_tdata[30:29];
assign packet_td = s_axis_tx_tdata[15];
// Calculate total packet length
assign header_len = packet_fmt[0] ? 3'd4 : 3'd3;
assign payload_len = packet_fmt[1] ? s_axis_tx_tdata[9:0] : 10'h0;
assign packet_len = {10'h000, header_len} + {4'h0, payload_len};
// Determine if packet a ECRC pause is needed
if(C_DATA_WIDTH == 128) begin : packet_len_check_128
assign pause_needed = (packet_len[1:0] == 2'b00) && !packet_td;
end
else begin : packet_len_check_64
assign pause_needed = (packet_len[0] == 1'b0) && !packet_td;
end
// Create flag to alert TX pipeline to insert a stall
assign tx_ecrc_pkt = s_axis_tx_tuser[0] && pause_needed &&
tready_thrtl && s_axis_tx_tvalid && !reg_axi_in_pkt;
always @(posedge user_clk) begin
if(user_rst) begin
reg_tx_ecrc_pkt <= #TCQ 1'b0;
end
else begin
if(tx_ecrc_pkt && !s_axis_tx_tlast) begin
reg_tx_ecrc_pkt <= #TCQ 1'b1;
end
else if(tready_thrtl && s_axis_tx_tvalid && s_axis_tx_tlast) begin
reg_tx_ecrc_pkt <= #TCQ 1'b0;
end
end
end
// Insert the stall now
assign tx_ecrc_pause = ((tx_ecrc_pkt || reg_tx_ecrc_pkt) &&
s_axis_tx_tlast && s_axis_tx_tvalid && tready_thrtl);
end
else begin : ecrc_pause_disabled
assign tx_ecrc_pause = 1'b0;
end
endgenerate
// Logic for 128-bit single cycle bug fix.
// This tcfg_gnt pipeline addresses an issue with 128-bit V6 designs where a
// single cycle packet transmitted simultaneously with an assertion of tcfg_gnt
// from AXI Basic causes the packet to be dropped. The packet drop occurs
// because the 128-bit shim doesn't know about the tcfg_req/gnt, and therefor
// isn't expecting trn_tdst_rdy to go low. Since the 128-bit shim does throttle
// prediction just as we do, it ignores the value of trn_tdst_rdy, and
// ultimately drops the packet when transmitting the packet to the block.
generate
if(C_DATA_WIDTH == 128 && C_FAMILY == "V6") begin : tcfg_gnt_pipeline
genvar stage;
reg tcfg_gnt_pipe [TCFG_GNT_PIPE_STAGES:0];
// Create a configurable depth FF delay pipeline
for(stage = 0; stage < TCFG_GNT_PIPE_STAGES; stage = stage + 1)
begin : tcfg_gnt_pipeline_stage
always @(posedge user_clk) begin
if(user_rst) begin
tcfg_gnt_pipe[stage] <= #TCQ 1'b0;
end
else begin
// For stage 0, insert the actual tcfg_gnt signal from logic
if(stage == 0) begin
tcfg_gnt_pipe[stage] <= #TCQ tcfg_gnt_log;
end
// For stages 1+, chain together
else begin
tcfg_gnt_pipe[stage] <= #TCQ tcfg_gnt_pipe[stage - 1];
end
end
end
// tcfg_gnt output to block assigned the last pipeline stage
assign trn_tcfg_gnt = tcfg_gnt_pipe[TCFG_GNT_PIPE_STAGES-1];
end
end
else begin : tcfg_gnt_no_pipeline
// For all other architectures, no pipeline delay needed for tcfg_gnt
assign trn_tcfg_gnt = tcfg_gnt_log;
end
endgenerate
endmodule
|
`timescale 1ps / 1ps
/* JTAG TAP interface
This module can be replaced with special JTAG TAP primitives on Xilinx and Altera FPGAs.
Those primitives have similar interfaces; if you plan to modify this module's interface,
make sure you do not make it incompatible with the other ones.
About the clock: it would have been easier to use the system clock in this module,
but the JTAG TAP interface should be able to work and do boundary scans
even when the main system clock is disabled. Relying on the JTAG clock
means that somewhere down the line crossing clock domains becomes necessary,
which can slow JTAG firmware transfers down.
About the delay in the is_tap_state_xxx signals:
The is_tap_state_xxx are all delivered to the submodules delayed by 1 TCK posedge, see
the comment below for more information. I am not sure whether these signals also
get delayed when using the JTAG TAP primitives on Xilinx or Altera FPGAs.
Author(s):
Igor Mohor ([email protected])
Nathan Yawn ([email protected])
R. Diez (in 2012)
NOTE: R. Diez has rewritten this module substantially and since then
it has only been tested against the OR10 OpenRISC implementation.
Copyright (C) 2000 - 2012 Authors
This source file may be used and distributed without
restriction provided that this copyright statement is not
removed from the file and that any derivative work contains
the original copyright notice and the associated disclaimer.
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License version 3
as published by the Free Software Foundation.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License version 3 for more details.
You should have received a copy of the GNU Lesser General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/////////////////////////////
//`include "simulator_features.v"
/////////////////////////////
`define UNIQUE //unique
`define FINISH_WITH_ERROR_EXIT_CODE //$finish
`define ASSERT_FALSE $display( "ERROR: Assertion failed at %0s:%0d in module %m.", `__FILE__, `__LINE__ ); `FINISH_WITH_ERROR_EXIT_CODE
/////////////////////////////
//`include "tap_defines.v"
////////////////////////////
// This is similar to the IDCODE that the or1200 CPU uses,
// only the new part number (IQ) is the or1200's value + 100 (decimal).
`define OPENRISC_CPU_JTAG_IDCODE_VALUE 32'h149B51C3 // or1200 uses 32'h149511c3.
// 0001 bits [31:28], version
// 0100100110110101 bits [27:12], part number (IQ), 01001001010101010001 + 100 (decimal)
// 00011100001 bits [11: 1], manufacturer id (flextronics)
// 1 bit 0, always "1" as required by the JTAG standard
// JTAG Instructions. The Instruction Register is 4 bits long at the moment,
// but 3 bits would do. However, this optimisation is probably not worth the trouble.
`define JTAG_INSTRUCTION_EXTEST 4'b0000 // Not supported at the moment.
`define JTAG_INSTRUCTION_SAMPLE_PRELOAD 4'b0001 // Not supported at the moment.
`define JTAG_INSTRUCTION_IDCODE 4'b0010 // Supported.
// The following command is specific to OR10. Because the Xilinx TAP primitives have just 1 or 2 user-defined
// JTAG instructions, all OR10 debug operations is performed with a single DEBUG instruction,
// which can be mapped to one of Xilinx' user-defined instructions when using that interface.
// If it weren't for this limitation, it would have been more comfortable to define
// several JTAG instructions for the different types of OR10 debug operations.
`define JTAG_INSTRUCTION_DEBUG 4'b1000 // Specific to OR10, see comment above.
`define JTAG_INSTRUCTION_MBIST 4'b1001 // Not supported at the moment.
`define JTAG_INSTRUCTION_BYPASS 4'b1111 // Supported. According to the JTAG specification, the BYPASS instruction opcode must be all 1's.
module jtag_tap
#( parameter TRACE_JTAG_DATA = 0,
parameter TRACE_STATE_MACHINE_TRANSITIONS = 0 )
(
// JTAG pads
input jtag_tms_i, // If unconnected or not used, the JTAG standard requires a value of 1.
input jtag_tck_i,
input jtag_trstn_i, // Test reset. Asynchronous, active at logic level 0. Therefore, if unconnected or not used, apply a value of 1.
input jtag_tdi_i, // If unconnected or not used, the JTAG standard requires a value of 1.
output reg jtag_tdo_o, // This pin should be tri-stated when not shifting data,
// but this module does not support an extra jtag_tdo_enable_o signal yet.
// These previous state signals are delayed by one TCK clock cycle:
// when a TAP submodule gets the next TCK rising edge, these signals
// indicate what state the TAP was in at the last TCK rising edge.
output reg is_tap_state_test_logic_reset_o, // One TCK posedge delay to reset the submodule is fine, as long as
// the next TCK posedge comes soon enough.
output reg is_tap_state_shift_dr_o, // One TCK posedge delay is fine, as bits are shifted on the next TCK posedge
// after entering the Shift-DR state.
output reg is_tap_state_update_dr_o, // One TCK posedge delay is usually fine, the register update will happen a little later.
// This may be a problem if the next TCK posedge does not come, or takes a long time to come.
output reg is_tap_state_capture_dr_o, // One TCK posedge delay is usually fine, the register capture will happen a little later.
// This may be a problem if the next TCK posedge does not come, or takes a long time to come.
// This signal is also delayed by one TCK clock cycle,
// but that does not matter, as the current instruction changes only
// in state Update-IR, and in that state all the is_tap_state_xxx signals are zero.
// When any of the is_tap_state_xxx signals become active again,
// this signal is already available.
output reg is_tap_current_instruction_debug_o,
// TDI signal from the debug submodule.
//input debug_tdo_i //TH
output reg [31:0] debug_reg //TH
);
// Length of the Instruction register.
localparam IR_LENGTH = 4;
localparam TRACE_PREFIX = "JTAG TAP: ";
// TAP State Machine, fully JTAG compliant.
localparam STATE_test_logic_reset = 4'd0; // The actual state values do not matter.
localparam STATE_run_test_idle = 4'd1;
localparam STATE_select_dr_scan = 4'd2;
localparam STATE_capture_dr = 4'd3;
localparam STATE_shift_dr = 4'd4;
localparam STATE_exit1_dr = 4'd5;
localparam STATE_pause_dr = 4'd6;
localparam STATE_exit2_dr = 4'd7;
localparam STATE_update_dr = 4'd8;
localparam STATE_select_ir_scan = 4'd9;
localparam STATE_capture_ir = 4'd10;
localparam STATE_shift_ir = 4'd11; // Once you enter this state, you'll shift at least 1 bit of information, as the TCK posedge that exits the state does also transfer 1 bit.
localparam STATE_exit1_ir = 4'd12;
localparam STATE_pause_ir = 4'd13;
localparam STATE_exit2_ir = 4'd14;
localparam STATE_update_ir = 4'd15;
reg [3:0] current_state; // Current state of the TAP controller.
reg [IR_LENGTH-1:0] jtag_ir; // The instruction register, when in state Capture-IR, gets a device-dependent status value.
reg [IR_LENGTH-1:0] current_instruction; // This is the content of jtag_ir register latched in state Update-IR.
reg [31:0] idcode_reg;
reg bypass_reg;
function automatic [3:0] get_next_state;
input reg [3:0] prev_state;
begin
`UNIQUE case ( prev_state )
STATE_test_logic_reset:
begin
if(jtag_tms_i) get_next_state = STATE_test_logic_reset;
else get_next_state = STATE_run_test_idle;
end
STATE_run_test_idle:
begin
if(jtag_tms_i) get_next_state = STATE_select_dr_scan;
else get_next_state = STATE_run_test_idle;
end
STATE_select_dr_scan:
begin
if(jtag_tms_i) get_next_state = STATE_select_ir_scan;
else get_next_state = STATE_capture_dr;
end
STATE_capture_dr:
begin
if(jtag_tms_i) get_next_state = STATE_exit1_dr;
else get_next_state = STATE_shift_dr;
end
STATE_shift_dr:
begin
if(jtag_tms_i) get_next_state = STATE_exit1_dr;
else get_next_state = STATE_shift_dr;
end
STATE_exit1_dr:
begin
if(jtag_tms_i) get_next_state = STATE_update_dr;
else get_next_state = STATE_pause_dr;
end
STATE_pause_dr:
begin
if(jtag_tms_i) get_next_state = STATE_exit2_dr;
else get_next_state = STATE_pause_dr;
end
STATE_exit2_dr:
begin
if(jtag_tms_i) get_next_state = STATE_update_dr;
else get_next_state = STATE_shift_dr;
end
STATE_update_dr:
begin
if(jtag_tms_i) get_next_state = STATE_select_dr_scan;
else get_next_state = STATE_run_test_idle;
end
STATE_select_ir_scan:
begin
if(jtag_tms_i) get_next_state = STATE_test_logic_reset;
else get_next_state = STATE_capture_ir;
end
STATE_capture_ir:
begin
if(jtag_tms_i) get_next_state = STATE_exit1_ir;
else get_next_state = STATE_shift_ir;
end
STATE_shift_ir:
begin
if(jtag_tms_i) get_next_state = STATE_exit1_ir;
else get_next_state = STATE_shift_ir;
end
STATE_exit1_ir:
begin
if(jtag_tms_i) get_next_state = STATE_update_ir;
else get_next_state = STATE_pause_ir;
end
STATE_pause_ir:
begin
if(jtag_tms_i) get_next_state = STATE_exit2_ir;
else get_next_state = STATE_pause_ir;
end
STATE_exit2_ir:
begin
if(jtag_tms_i) get_next_state = STATE_update_ir;
else get_next_state = STATE_shift_ir;
end
STATE_update_ir:
begin
if(jtag_tms_i) get_next_state = STATE_select_dr_scan;
else get_next_state = STATE_run_test_idle;
end
endcase
end
endfunction
function [16*8-1:0] get_state_name;
input [3:0] state;
begin
`UNIQUE case ( state )
STATE_test_logic_reset: get_state_name = "Test Logic Reset";
STATE_run_test_idle: get_state_name = "Run-Test / Idle";
STATE_select_dr_scan: get_state_name = "Select-DR";
STATE_capture_dr: get_state_name = "Capture-DR";
STATE_shift_dr: get_state_name = "Shift-DR";
STATE_exit1_dr: get_state_name = "Exit1-DR";
STATE_pause_dr: get_state_name = "Pause-DR";
STATE_exit2_dr: get_state_name = "Exit2-DR";
STATE_update_dr: get_state_name = "Update-DR";
STATE_select_ir_scan: get_state_name = "Select-IR";
STATE_capture_ir: get_state_name = "Capture-IR";
STATE_shift_ir: get_state_name = "Shift-IR";
STATE_exit1_ir: get_state_name = "Exit1-IR";
STATE_pause_ir: get_state_name = "Pause-IR";
STATE_exit2_ir: get_state_name = "Exit2-IR";
STATE_update_ir: get_state_name = "Update-IR";
endcase
end
endfunction
function [14*8-1:0] get_instruction_name;
input [IR_LENGTH-1:0] state;
begin
`UNIQUE case ( state )
`JTAG_INSTRUCTION_EXTEST: get_instruction_name = "EXTEST";
`JTAG_INSTRUCTION_SAMPLE_PRELOAD: get_instruction_name = "SAMPLE/PRELOAD";
`JTAG_INSTRUCTION_IDCODE: get_instruction_name = "IDCODE";
`JTAG_INSTRUCTION_DEBUG: get_instruction_name = "DEBUG";
`JTAG_INSTRUCTION_MBIST: get_instruction_name = "MBIST";
`JTAG_INSTRUCTION_BYPASS: get_instruction_name = "BYPASS";
default: get_instruction_name = "<unknown>";
endcase
end
endfunction
task automatic reset_initial;
begin
// See the comments in sibling task 'reset_sync' for more information.
current_state = STATE_test_logic_reset;
current_instruction = `JTAG_INSTRUCTION_IDCODE;
jtag_ir = {IR_LENGTH{1'bx}};
bypass_reg = 1'bx;
idcode_reg = {32{1'bx}};
debug_reg = {32{1'b0}}; //TH
is_tap_current_instruction_debug_o = 0;
is_tap_state_test_logic_reset_o = 0;
is_tap_state_shift_dr_o = 0;
is_tap_state_update_dr_o = 0;
is_tap_state_capture_dr_o = 0;
end
endtask
task automatic reset_sync;
begin
// If you change this task, please update sibling task 'reset_initial' too.
current_state <= STATE_test_logic_reset;
// As this JTAG TAP does support the IDCODE instruction, that's the one
// selected upon reset. Otherwise, we should select the BYPASS instruction.
current_instruction <= `JTAG_INSTRUCTION_IDCODE;
// We do not need to initialise the other registers, as the TAP state machine
// always goes through states Capture-IR or Capture-DR, which initialises them
// when they are needed.
jtag_ir <= {IR_LENGTH{1'bx}};
bypass_reg <= 1'bx;
idcode_reg <= {32{1'bx}};
debug_reg <= {32{1'b0}};
is_tap_current_instruction_debug_o <= 0;
is_tap_state_test_logic_reset_o <= 0;
is_tap_state_shift_dr_o <= 0;
is_tap_state_update_dr_o <= 0;
is_tap_state_capture_dr_o <= 0;
end
endtask
reg [16*8-1:0] initial_state_name; // We need this temporary variable because of a limitation in Verilator.
initial
begin
// This is so that, in FPGAs, there is no need to trigger the reset signal at the beginning,
// it can then be hard-wired to '1' and optimised away by the synthesiser.
reset_initial;
if ( TRACE_STATE_MACHINE_TRANSITIONS )
begin
initial_state_name = get_state_name( current_state );
$display( "%sStarting up in initial state '%0s'.", TRACE_PREFIX, initial_state_name );
end
end
task do_capture_dr;
reg [14*8-1:0] instruction_name;
begin
instruction_name = get_instruction_name( current_instruction );
case ( current_instruction )
`JTAG_INSTRUCTION_IDCODE: idcode_reg <= `OPENRISC_CPU_JTAG_IDCODE_VALUE;
`JTAG_INSTRUCTION_BYPASS: bypass_reg <= 0; // Must be 0 according to the JTAG specification.
`JTAG_INSTRUCTION_DEBUG:
begin
// Nothing to do here, a submodule will do all the processing for this command.
end
`JTAG_INSTRUCTION_EXTEST,
`JTAG_INSTRUCTION_SAMPLE_PRELOAD,
`JTAG_INSTRUCTION_MBIST:
begin
$display( "%sInstruction %0s is not supported or has not been fully tested yet.", TRACE_PREFIX, instruction_name );
`FINISH_WITH_ERROR_EXIT_CODE;
end
default:
begin
`ASSERT_FALSE;
// For all unknown JTAG instructions, the standard requires the bypass register.
bypass_reg <= 0;
end
endcase
end
endtask
task do_shift_dr;
begin
case ( current_instruction )
`JTAG_INSTRUCTION_IDCODE:
idcode_reg <= { jtag_tdi_i, idcode_reg[31:1] }; // Note that this overwrites the IDCODE register. It shouldn't really matter.
`JTAG_INSTRUCTION_BYPASS:
bypass_reg <= jtag_tdi_i;
`JTAG_INSTRUCTION_DEBUG:
begin
// Nothing to do here, a submodule will do all the processing for this command.
debug_reg <= { jtag_tdi_i, debug_reg[31:1] }; //TH
end
default:
begin
// Note that task 'do_capture_dr' already catches all default cases.
`ASSERT_FALSE;
// For all unknown JTAG instructions, the standard requires the bypass register.
bypass_reg <= jtag_tdi_i;
end
endcase
end
endtask
task automatic tck_posedge;
reg [14*8-1:0] instruction_name;
begin
case ( current_state )
STATE_test_logic_reset: reset_sync;
STATE_capture_ir:
jtag_ir <= { 2'b01, // Some fixed status value to help debugging this module,
// we don't actually have any status to report.
2'b01 }; // Bits [1:0] must be "01" according to the JTAG specification,
// which helps tell whether a device in the JTAG chain supports the IDCODE instruction
// or not (in which case it would be in BYPASS mode, and its first bit would then be 0).
STATE_update_ir:
begin
if ( TRACE_STATE_MACHINE_TRANSITIONS )
begin
instruction_name = get_instruction_name( jtag_ir );
$display( "%sCurrent instruction set to %0s.", TRACE_PREFIX, instruction_name );
end
current_instruction <= jtag_ir;
is_tap_current_instruction_debug_o <= 0;
case ( jtag_ir )
`JTAG_INSTRUCTION_DEBUG: is_tap_current_instruction_debug_o <= 1;
default:
begin
// Nothing to do here.
end
endcase
end
STATE_shift_ir:
jtag_ir <= { jtag_tdi_i, jtag_ir[IR_LENGTH-1:1] };
STATE_capture_dr:
do_capture_dr;
STATE_shift_dr:
do_shift_dr;
default:
begin
// Nothing to do here.
end
endcase
end
endtask
task automatic switch_to_next_state;
reg [3:0] next_state;
reg [16*8-1:0] prev_state_name;
reg [16*8-1:0] next_state_name;
begin
next_state = get_next_state( current_state );
if ( TRACE_JTAG_DATA || TRACE_STATE_MACHINE_TRANSITIONS )
begin
prev_state_name = get_state_name( current_state );
if ( next_state == current_state )
begin
if ( TRACE_JTAG_DATA )
$display( "%sTCK posedge, TMS=%0d, TDI=%0d while in state '%0s'.",
TRACE_PREFIX, jtag_tms_i, jtag_tdi_i, prev_state_name );
end
else
begin
next_state_name = get_state_name( next_state );
if ( TRACE_JTAG_DATA )
$display( "%sTCK posedge, TMS=%0d, TDI=%0d, changing state from '%0s' to '%0s'.",
TRACE_PREFIX, jtag_tms_i, jtag_tdi_i, prev_state_name, next_state_name );
if ( TRACE_STATE_MACHINE_TRANSITIONS )
$display( "%sChanging state from '%0s' to '%0s'.",
TRACE_PREFIX, prev_state_name, next_state_name );
end
end
current_state <= next_state;
is_tap_state_test_logic_reset_o <= 0;
is_tap_state_shift_dr_o <= 0;
is_tap_state_update_dr_o <= 0;
is_tap_state_capture_dr_o <= 0;
case ( next_state )
STATE_test_logic_reset: is_tap_state_test_logic_reset_o <= 1;
STATE_shift_dr: is_tap_state_shift_dr_o <= 1;
STATE_update_dr: is_tap_state_update_dr_o <= 1;
STATE_capture_dr: is_tap_state_capture_dr_o <= 1;
default:
begin
// Nothing to do here.
end
endcase
end
endtask
task automatic tck_negedge;
reg [16*8-1:0] state_name;
begin
if ( TRACE_JTAG_DATA )
begin
state_name = get_state_name( current_state );
$display( "%sTCK negedge, TMS=%0d, TDI=%0d while in state '%0s'.",
TRACE_PREFIX, jtag_tms_i, jtag_tdi_i, state_name );
end
// According to the JTAG specification TDO changes state at the negative edge of TCK.
// This is from the documentation about Xilinx BSCAN_SPARTAN6 (which allows access to the FPGA's JTAG TAP):
// TDO input driven from the user fabric logic. This signal is
// internally sampled on the falling edge before being driven out
// to the FPGA TDO pin.
if ( current_state == STATE_shift_ir )
jtag_tdo_o <= jtag_ir[0];
else
begin
case ( current_instruction )
`JTAG_INSTRUCTION_IDCODE: jtag_tdo_o <= idcode_reg[0];
`JTAG_INSTRUCTION_DEBUG: jtag_tdo_o <= debug_reg[0]; //debug_tdo_i; TH
`JTAG_INSTRUCTION_SAMPLE_PRELOAD: jtag_tdo_o <= 0; // Boundary scan not supported.
`JTAG_INSTRUCTION_EXTEST: jtag_tdo_o <= 0; // Boundary scan not supported.
`JTAG_INSTRUCTION_MBIST: jtag_tdo_o <= 0; // MBIST not supported.
default: jtag_tdo_o <= bypass_reg;
endcase
end
end
endtask
always @( posedge jtag_tck_i or negedge jtag_trstn_i )
begin
// These 2 conditions must be combined in a single always block,
// otherwise Verilator complains that current_state has 2 drivers,
// as the reset is asynchronous.
if ( jtag_trstn_i == 0 )
begin
if ( TRACE_STATE_MACHINE_TRANSITIONS )
$display( "%sAsync reset signal TRST asserted (the value is now 0).", TRACE_PREFIX );
reset_sync;
end
else
begin
tck_posedge;
switch_to_next_state;
end
end
always @( negedge jtag_tck_i )
begin
tck_negedge;
end
always @( posedge jtag_trstn_i )
begin
if ( TRACE_STATE_MACHINE_TRANSITIONS )
$display( "%sAsync reset signal TRST deasserted (the value is now 1).", TRACE_PREFIX );
end
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram_32_1.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram_32_1 (
aclr,
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q);
input aclr;
input clock;
input [0:0] data;
input [4:0] rdaddress;
input rden;
input [4:0] wraddress;
input wren;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
tri1 rden;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire0;
wire [0:0] q = sub_wire0[0:0];
altsyncram altsyncram_component (
.aclr0 (aclr),
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.rden_b (rden),
.wren_a (wren),
.q_b (sub_wire0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "CLEAR0",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Stratix V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32,
altsyncram_component.numwords_b = 32,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "CLEAR0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 5,
altsyncram_component.widthad_b = 5,
altsyncram_component.width_a = 1,
altsyncram_component.width_b = 1,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "1"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "1"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "CLEAR0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 1 0 INPUT NODEFVAL "data[0..0]"
// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 5 0 INPUT NODEFVAL "rdaddress[4..0]"
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
// Retrieval info: USED_PORT: wraddress 0 0 5 0 INPUT NODEFVAL "wraddress[4..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @address_a 0 0 5 0 wraddress 0 0 5 0
// Retrieval info: CONNECT: @address_b 0 0 5 0 rdaddress 0 0 5 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 1 0 data 0 0 1 0
// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 1 0 @q_b 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32_1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32_1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32_1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32_1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32_1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32_1_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %Shift register (RAM-based)%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altshift_taps
// ============================================================
// File Name: shiftreg_data.v
// Megafunction Name(s):
// altshift_taps
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 8.0 Build 215 05/29/2008 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module shiftreg_data (
aclr,
clken,
clock,
shiftin,
shiftout,
taps);
input aclr;
input clken;
input clock;
input [63:0] shiftin;
output [63:0] shiftout;
output [63:0] taps;
wire [63:0] sub_wire0;
wire [63:0] sub_wire1;
wire [63:0] taps = sub_wire0[63:0];
wire [63:0] shiftout = sub_wire1[63:0];
altshift_taps altshift_taps_component (
.clken (clken),
.aclr (aclr),
.clock (clock),
.shiftin (shiftin),
.taps (sub_wire0),
.shiftout (sub_wire1));
defparam
altshift_taps_component.lpm_hint = "RAM_BLOCK_TYPE=M512",
altshift_taps_component.lpm_type = "altshift_taps",
altshift_taps_component.number_of_taps = 1,
altshift_taps_component.tap_distance = 7,
altshift_taps_component.width = 64;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
// Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
// Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "7"
// Retrieval info: PRIVATE: WIDTH NUMERIC "64"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M512"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps"
// Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "1"
// Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "7"
// Retrieval info: CONSTANT: WIDTH NUMERIC "64"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT VCC aclr
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: shiftin 0 0 64 0 INPUT NODEFVAL shiftin[63..0]
// Retrieval info: USED_PORT: shiftout 0 0 64 0 OUTPUT NODEFVAL shiftout[63..0]
// Retrieval info: USED_PORT: taps 0 0 64 0 OUTPUT NODEFVAL taps[63..0]
// Retrieval info: CONNECT: @shiftin 0 0 64 0 shiftin 0 0 64 0
// Retrieval info: CONNECT: shiftout 0 0 64 0 @shiftout 0 0 64 0
// Retrieval info: CONNECT: taps 0 0 64 0 @taps 0 0 64 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_data.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_data.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_data.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_data.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_data_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_data_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_data_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_data_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
module uart_tx
#(parameter BAUD_DIV=2,
parameter BAUD_DIV_WIDTH=8,
parameter W=8) // data width
(input c,
input [W-1:0] in,
input in_en,
output in_ack,
output out,
output busy);
// as implemented below, BAUD_DIV must be >= 2. Lower values are ignored.
wire tx_r_en, tx_sel;
wire [W+1:0] tx;
r #(W+2) tx_r
(.c(c), .en(tx_r_en), .rst(1'b0), .q(tx),
.d(tx_sel ? {1'b1, in, 1'b0} : {1'b0, tx[W+1:1]}));
wire [BAUD_DIV_WIDTH-1:0] baud_div_count;
r #(BAUD_DIV_WIDTH) baud_div_count_r
(.c(c), .en(1'b1), .rst(baud_div_count == BAUD_DIV-1),
.d(baud_div_count + 1'b1), .q(baud_div_count));
wire tx_edge = ~|baud_div_count;
localparam CW = 4;
localparam SW = 3;
localparam ST_IDLE = 3'd0;
localparam ST_SYNC = 3'd1; // line up with baud clock
localparam ST_TX = 3'd2; // this includes the start and stop bits in tx_r
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[CW+SW-1:CW];
r #(SW) state_r(.c(c), .d(next_state), .rst(1'b0), .en(1'b1), .q(state));
always @* begin
case (state)
ST_IDLE:
if (in_en) ctrl = {ST_SYNC , 4'b0111};
else ctrl = {ST_IDLE , 4'b0000};
ST_SYNC:
if (tx_edge) ctrl = {ST_TX , 4'b0000};
else ctrl = {ST_SYNC , 4'b0000};
ST_TX:
if (tx_edge)
if (~|tx[W+1:1]) ctrl = {ST_IDLE, 4'b1001};
else ctrl = {ST_TX, 4'b1001};
else ctrl = {ST_TX, 4'b1000};
default: ctrl = {ST_IDLE , 4'b0000};
endcase
end
assign tx_r_en = ctrl[0];
assign in_ack = ctrl[1];
assign tx_sel = ctrl[2];
assign out = ctrl[3] ? tx[0] : 1'b1;
assign busy = (state != ST_IDLE);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_r_rf32x152b.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: DCache Fill Queue of Load Store Unit.
// - Contains invalidates and loads.
// - loads will bypass and/or fill dcache.
// - Entry at head of queue may have to
// be held for multiple passes.
//
*/
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
//FPGA_SYN enables all FPGA related modifications
`ifdef FPGA_SYN
`define FPGA_SYN_32x152
`endif
`ifdef FPGA_SYN_32x152
module bw_r_rf32x152b(dout, so, rd_en, rd_adr, wr_en, wr_adr, din, si, se,
sehold, rclk, rst_tri_en, reset_l);
parameter NUMENTRIES = 32;
input [4:0] rd_adr;
input rd_en;
input wr_en;
input [4:0] wr_adr;
input [151:0] din;
input rclk;
input reset_l;
input rst_tri_en;
input sehold;
input si;
input se;
output [151:0] dout;
reg [151:0] dout;
output so;
wire clk;
wire wr_vld;
reg [151:0] dfq_mem[(NUMENTRIES - 1):0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
assign clk = rclk;
assign wr_vld = ((wr_en & (~rst_tri_en)) & reset_l);
always @(posedge clk) begin
if (wr_vld) begin
dfq_mem[wr_adr] = din;
end
end
always @(posedge clk) begin
if (rd_en) begin
dout[151:0] <= dfq_mem[rd_adr[4:0]];
end
end
endmodule
`else
module bw_r_rf32x152b (/*AUTOARG*/
// Outputs
dout, so,
// Inputs
rd_en, rd_adr, wr_en, wr_adr, din,
si, se, sehold, rclk, rst_tri_en, reset_l);
parameter NUMENTRIES = 32 ; // number of entries in dfq
input [4:0] rd_adr; // read adr.
input rd_en; // read pointer
input wr_en; // write pointer vld
input [4:0] wr_adr; // write adr.
input [151:0] din; // wr data
input rclk; // clock
input reset_l; // active low reset
input rst_tri_en; // reset and scan
input sehold; // scan hold
input si; // scan in
input se; // scan enable
output [151:0] dout ; // data read out
output so ; // scan out
wire [151:0] dout;
wire clk;
wire wr_vld;
reg [151:0] dfq_mem [NUMENTRIES-1:0];
reg [151:0] local_dout;
// reg so;
integer i,j;
//
// added for atpg support
wire [4:0] sehold_rd_adr; // output of sehold mux - read adr.
wire sehold_rd_en; // output of sehold mux - read pointer
wire sehold_wr_en; // output of sehold mux - write pointer vld
wire [4:0] sehold_wr_adr; // output of sehold mux - write adr.
wire [151:0] sehold_din; // wr data
wire [4:0] rd_adr_d1; // flopped read adr.
wire rd_en_d1; // flopped read pointer
wire wr_en_d1; // flopped write pointer vld
wire [4:0] wr_adr_d1; // flopped write adr.
wire [151:0] din_d1; // flopped wr data
//
// creating local clock
assign clk=rclk;
//
//=========================================================================================
// support for atpg pattern generation
//=========================================================================================
//
// read controls
dp_mux2es #(6) mux_sehold_rd_ctrl (
.in0 ({rd_adr[4:0], rd_en}),
.in1 ({rd_adr_d1[4:0], rd_en_d1}),
.sel (sehold),
.dout ({sehold_rd_adr[4:0],sehold_rd_en})
);
dff_s #(6) dff_rd_ctrl_d1(
.din ({sehold_rd_adr[4:0], sehold_rd_en}),
.q ({rd_adr_d1[4:0], rd_en_d1}),
.clk (clk),
.se (se),
.si (),
.so ()
);
//
// write controls
dp_mux2es #(6) mux_sehold_wr_ctrl (
.in0 ({wr_adr[4:0], wr_en}),
.in1 ({wr_adr_d1[4:0], wr_en_d1}),
.sel (sehold),
.dout ({sehold_wr_adr[4:0],sehold_wr_en})
);
dff_s #(6) dff_wr_ctrl_d1(
.din ({sehold_wr_adr[4:0], sehold_wr_en}),
.q ({wr_adr_d1[4:0], wr_en_d1}),
.clk (clk),
.se (se),
.si (),
.so ()
);
//
// write data
dp_mux2es #(152) mux_sehold_din (
.in0 (din[151:0]),
.in1 (din_d1[151:0]),
.sel (sehold),
.dout (sehold_din[151:0])
);
dff_s #(152) dff_din_d1(
.din (sehold_din[151:0]),
.q (din_d1[151:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
//
// diable write to register file during reset or scan
assign wr_vld = sehold_wr_en & ~rst_tri_en & reset_l;
// always @ (posedge clk)
// begin
// so <= 1'bx;
// end
//=========================================================================================
// generate wordlines
//=========================================================================================
// Word-Line Generation skipped. Implicit in read and write.
//=========================================================================================
// write or read to/from memory
//=========================================================================================
always @ ( posedge clk )
begin
if (wr_vld)
dfq_mem[sehold_wr_adr] = sehold_din[151:0] ;
end
always @ ( posedge clk )
begin
if (sehold_rd_en)
begin
if (wr_vld & (sehold_wr_adr[4:0] == sehold_rd_adr[4:0]) )
local_dout[151:0] <= 152'hx;
else
for (j=0;j<NUMENTRIES;j=j+1)
begin
if (sehold_rd_adr[4:0] == j)
local_dout[151:0] <= dfq_mem[j] ;
end
end
end
always @ ( ~reset_l )
begin
local_dout[151:0] <=
152'hxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx ;
end
assign dout[151:0] = local_dout[151:0];
// Error Checking : Termination Conditions
always @ (posedge clk)
begin
if ((rd_en == 1'bx) | // wr is undefined, thus terminate
(sehold_rd_en & (sehold_rd_adr[4:0] == 5'hxx)) & reset_l) // check outside reset.
if (sehold_rd_adr[4:0] == 5'hxx)
begin
`ifdef INNO_MUXEX
`else
`ifdef DEFINE_0IN
// 0in <fire -message "rf32x152b_error, read pointer error (X)"
$display("rf32x152b_error"," read pointer error (X) %h ", rd_adr[4:0]);
`else
`ifdef MODELSIM
$display("rf32x152b_error"," read pointer error (X) %h ", rd_adr[4:0]);
`else
$error("rf32x152b_error"," read pointer error (X) %h ", rd_adr[4:0]);
`endif
`endif
`endif
end
if ((wr_vld == 1'bx) | // wr is undefined, thus terminate
(wr_vld & (sehold_wr_adr[4:0] == 5'hxx)) & reset_l) // check outside reset.
begin
`ifdef INNO_MUXEX
`else
`ifdef DEFINE_0IN
// 0in <fire -message "rf32x152b_error, write error (X)"
$display("rf32x152b_error"," write error (X) %h ", wr_adr[4:0]);
`else
`ifdef MODELSIM
$display("rf32x152b_error"," write error (X) %h ", wr_adr[4:0]);
`else
$error("rf32x152b_error"," write error (X) %h ", wr_adr[4:0]);
`endif
`endif
`endif
end
end
endmodule
`endif
|
module alu(
input [3:0] ctl,
input [31:0] a, b,
output reg [31:0] out,
output zero );
wire [31:0] sub_ab;
wire [31:0] add_ab;
always @(*) begin
case (ctl)
4'b0000: out = a & b; /* and */
4'b0001: out = a | b; /* or */
4'b0010: out = a + b; /* add */
4'b0110: out = a - b; /* sub */
4'b0111: out = (a < b) ? 32'b00000000000000000000000000000001 : 32'b0; //slt
default: out = 0;
endcase
end
assign zero = (0 == out)? 1 : out;
endmodule
module alu_control(ALUOp,funct,ALUCon);
input [1:0] ALUOp;
input [5:0] funct;
output [3:0] ALUCon;
reg [3:0] ALUCon;
always @(*) begin
case(ALUOp)
2'b00: ALUCon <= 4'b0010; // lw, sw
2'b01: ALUCon <= 4'b0110; // beq
2'b10 :
begin
case (funct)
6'b100000: ALUCon <= 4'b0010;
6'b100010: ALUCon <= 4'b0110;
6'b100101: ALUCon <= 4'b0001;
6'b100100: ALUCon <= 4'b0000;
6'b101010: ALUCon <= 4'b0111;
default: ALUCon <= 4'b0000;
endcase
end
default: ALUCon <= 4'b0000;
endcase
end
endmodule
module control_unit (
input[5:0] op,
output reg [1:0] regdst,
output reg regwrite,
output reg branch,
output reg jump,
output reg memread,
output reg [1:0]memtoreg,
output reg memwrite,
output reg [1:0] aluop,
output reg aluscr );
always @(*) begin
// default
// R-type
branch <= 1'b0;
jump <= 1'b0;
memread <= 1'b0;
memtoreg[1:0] <= 2'b00;
memwrite <= 1'b0;
aluop[1:0] <= 2'b10;
aluscr <= 1'b0;
regdst[1:0] <= 2'b01;
regwrite <= 1'b1;
case(op)
6'b10_0011: begin // lw
regdst[1:0] <= 2'b00;
memread <= 1'b1;
aluop[1:0] <= 2'b00;
aluscr <= 1'b1;
memtoreg[1:0] <= 2'b01;
end
6'b10_1011: begin // sw
aluop[1] <= 1'b0;
aluscr <= 1'b1;
memwrite <= 1'b1;
regwrite <= 1'b0;
end
6'b00_0100: begin // beq
branch <= 1'b1;
aluop[1:0] <= 2'b01;
regwrite <= 1'b0;
end
6'b00_1000: begin // addi
regdst[1:0] <= 2'b00;
aluop[1] <= 1'b0;
aluscr <= 1'b1;
end
6'b00_0010: begin //jump
jump <= 1'b1;
regwrite <= 1'b0;
end
6'b00_0011: begin
jump <= 1'b1;
regdst[1:0] <= 2'b10;
memtoreg[1:0] <= 2'b10;
end
6'b00_0000: begin // add
end
endcase
end
endmodule
module datamem(dataOut, address, dataIn, readmode, writemode);
output reg [31:0] dataOut;
input [31:0] address;
input [31:0] dataIn;
input readmode;
input writemode;
reg [31:0] dMemory [2499:250];
always@ (readmode or writemode)
begin
if (writemode == 1)
dMemory[address >> 2]=dataIn; //store data
if (readmode == 1)
dataOut = dMemory[address >> 2]; //load data
end
endmodule
module instr_mem ( input [31:0] address,
output [31:0] instruction );
reg [31:0] memory [249:0];
integer i;
initial
begin
for (i=0; i<250; i=i+1)
memory[i] = 32'b0;
// Insert MIPS's assembly here start at memory[10] = ...
//memory[10] = 32'b000000_01000_01001_01010_00000_100000; // add $t2, $t0, $1
//memory[11] = 32'b000100_01000_01000_0000000000000100; // beq $t0, $t0,
//memory[12] = 32'b000010_00000_00000_00000_00000_101000;
memory[10] = 32'b001000_00000_01000_00000_00000_000101; // addi $t0, $0, 5
memory[11] = 32'b101011_00100_00101_00000_00000_000000; //110100 sw
memory[12] = 32'b100011_00100_00110_00000_00000_000000; // 111000 lw
end
assign instruction = memory[address >> 2];
endmodule
module mux32_2to1(out, in0, in1, sel);
output reg [31:0] out;
input [31:0] in0;
input [31:0] in1;
input sel;
always @(sel)
begin
case (sel)
1'b0: out = in0;
1'b1: out = in1;
endcase
end
endmodule
module mux32_3to1 (out, in0, in1, in2, sel);
output reg [31:0] out;
input [31:0] in0;
input [31:0] in1;
input [31:0] in2;
input [1:0] sel;
always @(sel)
begin
case (sel)
2'b00: out = in0;
2'b01: out = in1;
2'b10: out = in2;
endcase
end
endmodule
module mux5_2to1(out, in0, in1, sel);
output reg [4:0] out;
input [4:0] in0;
input [4:0] in1;
input sel;
always @(sel)
begin
case (sel)
1'b0: out = in0;
1'b1: out = in1;
endcase
end
endmodule
module mux5_3to1 (out, in0, in1, in2, sel);
output reg [4:0] out;
input [4:0] in0;
input [4:0] in1;
input [4:0] in2;
input [1:0] sel;
always @(sel)
begin
case (sel)
2'b00: out = in0;
2'b01: out = in1;
2'b10: out = in2;
endcase
end
endmodule
module registerMemory (
input[4:0]reg_read1,
input[4:0]reg_read2,
input[4:0]reg_write,
input[1:0] regwrite_con, //register wirte from control unit
input[31:0] write_data,
output reg[31:0] data1,
output reg[31:0] data2
);
reg[31:0]reg_mem[31:0];
integer i;
initial
begin
for (i=0;i<32;i++) reg_mem[i] = 0;
//reg_mem[reg_read1] = 32'b00_0000000000_0000000000_000000100;
reg_mem[8] = 32'b00_0000000000_0000000000_111101000; //MEM(1000)
reg_mem[9] = 32'b00_0000000000_0000000000_0000000010; //data to MEM(1000)
//reg_mem[10] = 32'b00_0000000000_0000000000_0000000010; //data to MEM(1000)
end
always @(*) begin
if (reg_read1 == 0)
data1 = 0;
else if ((reg_read1 == reg_write) && regwrite_con)
data1 = write_data;
else
data1 = reg_mem[reg_read1][31:0];
end
always @(*) begin
if (reg_read2 == 0)
data2 = 0;
else if ((reg_read2 == reg_write) && regwrite_con)
data2 = write_data;
else
data2 = reg_mem[reg_read2][31:0];
end
always @(*) begin
if (regwrite_con && reg_write != 0)
// write a non $zero register
reg_mem[reg_write] <= write_data;
end
endmodule
module sign_extended (
output signed [31:0] out,
input signed [15:0] in);
assign out = in;
endmodule
module cpu (
input clk,
output reg [31:0] addr,
output reg [31:0] pc,
output [31:0] instruction,
output [1:0] cu_regdst,
output cu_jump, cu_branch, cu_memread,
output [1:0] cu_memtoreg,
output [1:0] cu_aluop,
output cu_memwrite, cu_aluscr, cu_regwrite,
output [4:0] mux1_regwrite,
output [31:0] mux3_writedata,
output [31:0] reg_readdata1, reg_readdata2,
output [31:0] signext_out,
output [31:0] mux2_out,
output [31:0] alu_out,
output alu_zero,
output [3:0] aluctrl_out,
output [31:0] dmem_readdata,
output bBranch
);
reg[31:0] pc;
initial begin
addr = 32'b0000_0000_0000_0000_0000_0000_0010_1000;
end
reg [31:0] ra;
parameter ra_addr = 5'b11111;
instr_mem instrmem (addr,instruction);
control_unit contrlu (instruction[31:26],
cu_regdst, cu_regwrite, cu_branch,
cu_jump, cu_memread, cu_memtoreg,
cu_memwrite, cu_aluop, cu_aluscr );
mux5_3to1 mux01 (mux1_regwrite, instruction[20:16], instruction[15:11], ra_addr, cu_regdst[1:0]);
registerMemory regmem ( .reg_read1(instruction[25:21]),
.reg_read2(instruction[20:16]),
.reg_write(mux1_regwrite[4:0]),
.regwrite_con(cu_regwrite),
.write_data(mux3_writedata),
.data1(reg_readdata1),
.data2(reg_readdata2));
sign_extended signext (signext_out[31:0], instruction[15:0]);
mux32_2to1 mux02 (mux2_out, reg_readdata2, signext_out, cu_aluscr);
alu_control aluctrl (cu_aluop, instruction[5:0], aluctrl_out);
alu ALU (aluctrl_out, reg_readdata1, mux2_out, alu_out, alu_zero);
datamem data_mem (dmem_readdata, alu_out, reg_readdata2, cu_memread, cu_memwrite);
always @(posedge clk) begin
pc <= addr + 4;
end
//assign addr = pc;
mux32_3to1 mux03(mux3_writedata, alu_out, dmem_readdata, pc, cu_memtoreg);
and AND1(bBranch, cu_branch, alu_zero );
reg[31:0] branch_shiftl2_result;
assign branch_shiftl2_result = signext_out << 2;
reg[31:0] j_addr;
assign j_addr = {pc[31:28],(instruction[25:0] << 2)};
reg[31:0] b_addr;
assign b_addr = pc + branch_shiftl2_result;
reg[31:0] mux04_result;
mux32_2to1 mux04 (mux04_result, pc, b_addr, bBranch);
mux32_2to1 mux05 (mux05_result, mux04_result, j_addr, cu_jump);
//always @(posedge clk) begin
//end
//assign out = mux05_result; //next address output
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//Register map:
//addr register type
//0 read data r
//1 write data w
//2 status r/w
//3 control r/w
//4 reserved
//5 slave-enable r/w
//6 end-of-packet-value r/w
//INPUT_CLOCK: 50000000
//ISMASTER: 1
//DATABITS: 8
//TARGETCLOCK: 20000000
//NUMSLAVES: 1
//CPOL: 0
//CPHA: 0
//LSBFIRST: 0
//EXTRADELAY: 0
//TARGETSSDELAY: 0.0001
module epcs_flash_controller_sub (
// inputs:
MISO,
clk,
data_from_cpu,
epcs_select,
mem_addr,
read_n,
reset_n,
write_n,
// outputs:
MOSI,
SCLK,
SS_n,
data_to_cpu,
dataavailable,
endofpacket,
irq,
readyfordata
)
;
output MOSI;
output SCLK;
output SS_n;
output [ 15: 0] data_to_cpu;
output dataavailable;
output endofpacket;
output irq;
output readyfordata;
input MISO;
input clk;
input [ 15: 0] data_from_cpu;
input epcs_select;
input [ 2: 0] mem_addr;
input read_n;
input reset_n;
input write_n;
wire E;
reg EOP;
reg MISO_reg;
wire MOSI;
reg ROE;
reg RRDY;
wire SCLK;
reg SCLK_reg;
reg SSO_reg;
wire SS_n;
wire TMT;
reg TOE;
wire TRDY;
wire control_wr_strobe;
reg data_rd_strobe;
reg [ 15: 0] data_to_cpu;
reg data_wr_strobe;
wire dataavailable;
wire ds_MISO;
wire enableSS;
wire endofpacket;
reg [ 15: 0] endofpacketvalue_reg;
wire endofpacketvalue_wr_strobe;
wire [ 10: 0] epcs_control;
reg [ 15: 0] epcs_slave_select_holding_reg;
reg [ 15: 0] epcs_slave_select_reg;
wire [ 10: 0] epcs_status;
reg iEOP_reg;
reg iE_reg;
reg iROE_reg;
reg iRRDY_reg;
reg iTMT_reg;
reg iTOE_reg;
reg iTRDY_reg;
wire irq;
reg irq_reg;
wire p1_data_rd_strobe;
wire [ 15: 0] p1_data_to_cpu;
wire p1_data_wr_strobe;
wire p1_rd_strobe;
wire [ 1: 0] p1_slowcount;
wire p1_wr_strobe;
reg rd_strobe;
wire readyfordata;
reg [ 7: 0] rx_holding_reg;
reg [ 7: 0] shift_reg;
wire slaveselect_wr_strobe;
wire slowclock;
reg [ 1: 0] slowcount;
reg [ 4: 0] state;
reg stateZero;
wire status_wr_strobe;
reg transmitting;
reg tx_holding_primed;
reg [ 7: 0] tx_holding_reg;
reg wr_strobe;
wire write_shift_reg;
wire write_tx_holding;
//epcs_control_port, which is an e_avalon_slave
assign p1_rd_strobe = ~rd_strobe & epcs_select & ~read_n;
// Read is a two-cycle event.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_strobe <= 0;
else
rd_strobe <= p1_rd_strobe;
end
assign p1_data_rd_strobe = p1_rd_strobe & (mem_addr == 0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_rd_strobe <= 0;
else
data_rd_strobe <= p1_data_rd_strobe;
end
assign p1_wr_strobe = ~wr_strobe & epcs_select & ~write_n;
// Write is a two-cycle event.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wr_strobe <= 0;
else
wr_strobe <= p1_wr_strobe;
end
assign p1_data_wr_strobe = p1_wr_strobe & (mem_addr == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_wr_strobe <= 0;
else
data_wr_strobe <= p1_data_wr_strobe;
end
assign control_wr_strobe = wr_strobe & (mem_addr == 3);
assign status_wr_strobe = wr_strobe & (mem_addr == 2);
assign slaveselect_wr_strobe = wr_strobe & (mem_addr == 5);
assign endofpacketvalue_wr_strobe = wr_strobe & (mem_addr == 6);
assign TMT = ~transmitting & ~tx_holding_primed;
assign E = ROE | TOE;
assign epcs_status = {EOP, E, RRDY, TRDY, TMT, TOE, ROE, 3'b0};
// Streaming data ready for pickup.
assign dataavailable = RRDY;
// Ready to accept streaming data.
assign readyfordata = TRDY;
// Endofpacket condition detected.
assign endofpacket = EOP;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
iEOP_reg <= 0;
iE_reg <= 0;
iRRDY_reg <= 0;
iTRDY_reg <= 0;
iTMT_reg <= 0;
iTOE_reg <= 0;
iROE_reg <= 0;
SSO_reg <= 0;
end
else if (control_wr_strobe)
begin
iEOP_reg <= data_from_cpu[9];
iE_reg <= data_from_cpu[8];
iRRDY_reg <= data_from_cpu[7];
iTRDY_reg <= data_from_cpu[6];
iTMT_reg <= data_from_cpu[5];
iTOE_reg <= data_from_cpu[4];
iROE_reg <= data_from_cpu[3];
SSO_reg <= data_from_cpu[10];
end
end
assign epcs_control = {SSO_reg, iEOP_reg, iE_reg, iRRDY_reg, iTRDY_reg, 1'b0, iTOE_reg, iROE_reg, 3'b0};
// IRQ output.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_reg <= 0;
else
irq_reg <= (EOP & iEOP_reg) | ((TOE | ROE) & iE_reg) | (RRDY & iRRDY_reg) | (TRDY & iTRDY_reg) | (TOE & iTOE_reg) | (ROE & iROE_reg);
end
assign irq = irq_reg;
// Slave select register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
epcs_slave_select_reg <= 1;
else if (write_shift_reg || control_wr_strobe & data_from_cpu[10] & ~SSO_reg)
epcs_slave_select_reg <= epcs_slave_select_holding_reg;
end
// Slave select holding register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
epcs_slave_select_holding_reg <= 1;
else if (slaveselect_wr_strobe)
epcs_slave_select_holding_reg <= data_from_cpu;
end
// slowclock is active once every 2 system clock pulses.
assign slowclock = slowcount == 2'h1;
assign p1_slowcount = ({2 {(transmitting && !slowclock)}} & (slowcount + 1)) |
({2 {(~((transmitting && !slowclock)))}} & 0);
// Divide counter for SPI clock.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
slowcount <= 0;
else
slowcount <= p1_slowcount;
end
// End-of-packet value register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
endofpacketvalue_reg <= 0;
else if (endofpacketvalue_wr_strobe)
endofpacketvalue_reg <= data_from_cpu;
end
assign p1_data_to_cpu = ((mem_addr == 2))? epcs_status :
((mem_addr == 3))? epcs_control :
((mem_addr == 6))? endofpacketvalue_reg :
((mem_addr == 5))? epcs_slave_select_reg :
rx_holding_reg;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_to_cpu <= 0;
else
// Data to cpu.
data_to_cpu <= p1_data_to_cpu;
end
// 'state' counts from 0 to 17.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
state <= 0;
stateZero <= 1;
end
else if (transmitting & slowclock)
begin
stateZero <= state == 17;
if (state == 17)
state <= 0;
else
state <= state + 1;
end
end
assign enableSS = transmitting & ~stateZero;
assign MOSI = shift_reg[7];
assign SS_n = (enableSS | SSO_reg) ? ~epcs_slave_select_reg : {1 {1'b1} };
assign SCLK = SCLK_reg;
// As long as there's an empty spot somewhere,
//it's safe to write data.
assign TRDY = ~(transmitting & tx_holding_primed);
// Enable write to tx_holding_register.
assign write_tx_holding = data_wr_strobe & TRDY;
// Enable write to shift register.
assign write_shift_reg = tx_holding_primed & ~transmitting;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
shift_reg <= 0;
rx_holding_reg <= 0;
EOP <= 0;
RRDY <= 0;
ROE <= 0;
TOE <= 0;
tx_holding_reg <= 0;
tx_holding_primed <= 0;
transmitting <= 0;
SCLK_reg <= 0;
MISO_reg <= 0;
end
else
begin
if (write_tx_holding)
begin
tx_holding_reg <= data_from_cpu;
tx_holding_primed <= 1;
end
if (data_wr_strobe & ~TRDY)
// You wrote when I wasn't ready.
TOE <= 1;
// EOP must be updated by the last (2nd) cycle of access.
if ((p1_data_rd_strobe && (rx_holding_reg == endofpacketvalue_reg)) || (p1_data_wr_strobe && (data_from_cpu[7 : 0] == endofpacketvalue_reg)))
EOP <= 1;
if (write_shift_reg)
begin
shift_reg <= tx_holding_reg;
transmitting <= 1;
end
if (write_shift_reg & ~write_tx_holding)
// Clear tx_holding_primed
tx_holding_primed <= 0;
if (data_rd_strobe)
// On data read, clear the RRDY bit.
RRDY <= 0;
if (status_wr_strobe)
begin
// On status write, clear all status bits (ignore the data).
EOP <= 0;
RRDY <= 0;
ROE <= 0;
TOE <= 0;
end
if (slowclock)
begin
if (state == 17)
begin
transmitting <= 0;
RRDY <= 1;
rx_holding_reg <= shift_reg;
SCLK_reg <= 0;
if (RRDY)
ROE <= 1;
end
else if (state != 0)
if (transmitting)
SCLK_reg <= ~SCLK_reg;
if (SCLK_reg ^ 0 ^ 0)
begin
if (1)
shift_reg <= {shift_reg[6 : 0], MISO_reg};
end
else
MISO_reg <= ds_MISO;
end
end
end
assign ds_MISO = MISO;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module tornado_epcs_flash_controller_atom (
// inputs:
dclkin,
oe,
scein,
sdoin,
// outputs:
data0out
)
;
output data0out;
input dclkin;
input oe;
input scein;
input sdoin;
wire data0out;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign data0out = sdoin | scein | dclkin | oe;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// tornado_spiblock the_tornado_spiblock
// (
// .data0out (data0out),
// .dclkin (dclkin),
// .oe (oe),
// .scein (scein),
// .sdoin (sdoin)
// );
//
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module epcs_flash_controller (
// inputs:
address,
chipselect,
clk,
read_n,
reset_n,
write_n,
writedata,
// outputs:
dataavailable,
endofpacket,
irq,
readdata,
readyfordata
)
;
parameter INIT_FILE = "epcs_flash_controller_boot_rom.hex";
output dataavailable;
output endofpacket;
output irq;
output [ 31: 0] readdata;
output readyfordata;
input [ 8: 0] address;
input chipselect;
input clk;
input read_n;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire MISO;
wire MOSI;
wire SCLK;
wire SS_n;
wire [ 15: 0] data_from_cpu;
wire [ 15: 0] data_to_cpu;
wire dataavailable;
wire endofpacket;
wire epcs_select;
wire irq;
wire [ 2: 0] mem_addr;
wire [ 31: 0] readdata;
wire readyfordata;
wire [ 31: 0] rom_readdata;
epcs_flash_controller_sub the_epcs_flash_controller_sub
(
.MISO (MISO),
.MOSI (MOSI),
.SCLK (SCLK),
.SS_n (SS_n),
.clk (clk),
.data_from_cpu (data_from_cpu),
.data_to_cpu (data_to_cpu),
.dataavailable (dataavailable),
.endofpacket (endofpacket),
.epcs_select (epcs_select),
.irq (irq),
.mem_addr (mem_addr),
.read_n (read_n),
.readyfordata (readyfordata),
.reset_n (reset_n),
.write_n (write_n)
);
//epcs_control_port, which is an e_avalon_slave
tornado_epcs_flash_controller_atom the_tornado_epcs_flash_controller_atom
(
.data0out (MISO),
.dclkin (SCLK),
.oe (1'b0),
.scein (SS_n),
.sdoin (MOSI)
);
assign epcs_select = chipselect && (address[7] );
assign mem_addr = address;
assign data_from_cpu = writedata;
assign readdata = epcs_select ? data_to_cpu : rom_readdata;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_boot_copier_rom
(
.address_a (address[6 : 0]),
.clock0 (clk),
.q_a (rom_readdata)
);
defparam the_boot_copier_rom.byte_size = 8,
the_boot_copier_rom.init_file = INIT_FILE,
the_boot_copier_rom.lpm_type = "altsyncram",
the_boot_copier_rom.numwords_a = 128,
the_boot_copier_rom.operation_mode = "ROM",
the_boot_copier_rom.outdata_reg_a = "UNREGISTERED",
the_boot_copier_rom.read_during_write_mode_mixed_ports = "DONT_CARE",
the_boot_copier_rom.width_a = 32,
the_boot_copier_rom.widthad_a = 7;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_boot_copier_rom
// (
// .address_a (address[6 : 0]),
// .clock0 (clk),
// .q_a (rom_readdata)
// );
//
// defparam the_boot_copier_rom.byte_size = 8,
// the_boot_copier_rom.init_file = "epcs_flash_controller_boot_rom_synth.hex",
// the_boot_copier_rom.lpm_type = "altsyncram",
// the_boot_copier_rom.numwords_a = 128,
// the_boot_copier_rom.operation_mode = "ROM",
// the_boot_copier_rom.outdata_reg_a = "UNREGISTERED",
// the_boot_copier_rom.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_boot_copier_rom.width_a = 32,
// the_boot_copier_rom.widthad_a = 7;
//
//synthesis read_comments_as_HDL off
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: ADM7V3_Gen1x8If64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
// the Xilinx 7V3 Development Board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "functions.vh"
`include "riffa.vh"
`include "ultrascale.vh"
`timescale 1ps / 1ps
module ADM7V3_Gen1x8If64
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes
parameter C_NUM_LANES = 8,
// Settings from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 64,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 6)
(output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN,
output [5:0] LED,
input PCIE_REFCLK_P,
input PCIE_REFCLK_N,
input PCIE_RESET_N
);
// Clocks, etc
wire user_lnk_up;
wire user_clk;
wire user_reset;
wire pcie_refclk;
wire pcie_reset_n;
// Interface: RQ (TXC)
wire s_axis_rq_tlast;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata;
wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep;
wire s_axis_rq_tready;
wire s_axis_rq_tvalid;
// Interface: RC (RXC)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata;
wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser;
wire m_axis_rc_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep;
wire m_axis_rc_tvalid;
wire m_axis_rc_tready;
// Interface: CQ (RXR)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata;
wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser;
wire m_axis_cq_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep;
wire m_axis_cq_tvalid;
wire m_axis_cq_tready;
// Interface: CC (TXC)
wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata;
wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser;
wire s_axis_cc_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep;
wire s_axis_cc_tvalid;
wire s_axis_cc_tready;
// Configuration (CFG) Interface
wire [3:0] pcie_rq_seq_num;
wire pcie_rq_seq_num_vld;
wire [5:0] pcie_rq_tag;
wire pcie_rq_tag_vld;
wire pcie_cq_np_req;
wire [5:0] pcie_cq_np_req_count;
wire cfg_phy_link_down;
wire [3:0] cfg_negotiated_width; // CONFIG_LINK_WIDTH
wire [2:0] cfg_current_speed; // CONFIG_LINK_RATE
wire [2:0] cfg_max_payload; // CONFIG_MAX_PAYLOAD
wire [2:0] cfg_max_read_req; // CONFIG_MAX_READ_REQUEST
wire [7:0] cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE
wire [5:0] cfg_function_power_state; // Ignorable but not removable
wire [11:0] cfg_vf_status; // Ignorable but not removable
wire [17:0] cfg_vf_power_state; // Ignorable but not removable
wire [1:0] cfg_link_power_state; // Ignorable but not removable
// Error Reporting Interface
wire cfg_err_cor_out;
wire cfg_err_nonfatal_out;
wire cfg_err_fatal_out;
wire cfg_ltr_enable;
wire [5:0] cfg_ltssm_state;// TODO: Connect to LED's
wire [1:0] cfg_rcb_status;
wire [1:0] cfg_dpa_substate_change;
wire [1:0] cfg_obff_enable;
wire cfg_pl_status_change;
wire [1:0] cfg_tph_requester_enable;
wire [5:0] cfg_tph_st_mode;
wire [5:0] cfg_vf_tph_requester_enable;
wire [17:0] cfg_vf_tph_st_mode;
wire [7:0] cfg_fc_ph;
wire [11:0] cfg_fc_pd;
wire [7:0] cfg_fc_nph;
wire [11:0] cfg_fc_npd;
wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel;
// Interrupt Interface Signals
wire [3:0] cfg_interrupt_int;
wire [1:0] cfg_interrupt_pending;
wire cfg_interrupt_sent;
wire [1:0] cfg_interrupt_msi_enable;
wire [5:0] cfg_interrupt_msi_vf_enable;
wire [5:0] cfg_interrupt_msi_mmenable;
wire cfg_interrupt_msi_mask_update;
wire [31:0] cfg_interrupt_msi_data;
wire [3:0] cfg_interrupt_msi_select;
wire [31:0] cfg_interrupt_msi_int;
wire [63:0] cfg_interrupt_msi_pending_status;
wire cfg_interrupt_msi_sent;
wire cfg_interrupt_msi_fail;
wire [2:0] cfg_interrupt_msi_attr;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [2:0] cfg_interrupt_msi_function_number;
wire rst_out;
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
genvar chnl;
IBUF
#()
pci_reset_n_ibuf
(.O(pcie_reset_n),
.I(PCIE_RESET_N));
IBUFDS_GTE2
#()
refclk_ibuf
(.O(pcie_refclk),
.ODIV2(),
.I(PCIE_REFCLK_P),
.CEB(1'b0),
.IB(PCIE_REFCLK_N));
OBUF
#()
led_0_obuf
(.O(LED[0]),
.I(cfg_ltssm_state[0]));
OBUF
#()
led_1_obuf
(.O(LED[1]),
.I(cfg_ltssm_state[1]));
OBUF
#()
led_2_obuf
(.O(LED[2]),
.I(cfg_ltssm_state[2]));
OBUF
#()
led_3_obuf
(.O(LED[3]),
.I(cfg_ltssm_state[3]));
OBUF
#()
led_4_obuf
(.O(LED[4]),
.I(cfg_ltssm_state[4]));
OBUF
#()
led_5_obuf
(.O(LED[5]),
.I(cfg_ltssm_state[5]));
OBUF
#()
led_6_obuf
(.O(LED[6]),
.I(pcie_reset_n));
OBUF
#()
led_7_obuf
(.O(LED[7]),
.I(rst_out));
// Core Top Level Wrapper
PCIeGen1x8If64
#()
pcie3_7x_0_i
(//---------------------------------------------------------------------
// PCI Express (pci_exp) Interface
//---------------------------------------------------------------------
.pci_exp_txn ( PCI_EXP_TXN ),
.pci_exp_txp ( PCI_EXP_TXP ),
.pci_exp_rxn ( PCI_EXP_RXN ),
.pci_exp_rxp ( PCI_EXP_RXP ),
//---------------------------------------------------------------------
// AXI Interface
//---------------------------------------------------------------------
.user_clk ( user_clk ),
.user_reset ( user_reset ),
.user_lnk_up ( user_lnk_up ),
.user_app_rdy ( ),
.s_axis_rq_tlast ( s_axis_rq_tlast ),
.s_axis_rq_tdata ( s_axis_rq_tdata ),
.s_axis_rq_tuser ( s_axis_rq_tuser ),
.s_axis_rq_tkeep ( s_axis_rq_tkeep ),
.s_axis_rq_tready ( s_axis_rq_tready ),
.s_axis_rq_tvalid ( s_axis_rq_tvalid ),
.m_axis_rc_tdata ( m_axis_rc_tdata ),
.m_axis_rc_tuser ( m_axis_rc_tuser ),
.m_axis_rc_tlast ( m_axis_rc_tlast ),
.m_axis_rc_tkeep ( m_axis_rc_tkeep ),
.m_axis_rc_tvalid ( m_axis_rc_tvalid ),
.m_axis_rc_tready ( {22{m_axis_rc_tready}} ),
.m_axis_cq_tdata ( m_axis_cq_tdata ),
.m_axis_cq_tuser ( m_axis_cq_tuser ),
.m_axis_cq_tlast ( m_axis_cq_tlast ),
.m_axis_cq_tkeep ( m_axis_cq_tkeep ),
.m_axis_cq_tvalid ( m_axis_cq_tvalid ),
.m_axis_cq_tready ( {22{m_axis_cq_tready}} ),
.s_axis_cc_tdata ( s_axis_cc_tdata ),
.s_axis_cc_tuser ( s_axis_cc_tuser ),
.s_axis_cc_tlast ( s_axis_cc_tlast ),
.s_axis_cc_tkeep ( s_axis_cc_tkeep ),
.s_axis_cc_tvalid ( s_axis_cc_tvalid ),
.s_axis_cc_tready ( s_axis_cc_tready ),
//---------------------------------------------------------------------
// Configuration (CFG) Interface
//---------------------------------------------------------------------
.pcie_rq_seq_num ( pcie_rq_seq_num ),
.pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ),
.pcie_rq_tag ( pcie_rq_tag ),
.pcie_rq_tag_vld ( pcie_rq_tag_vld ),
.pcie_cq_np_req ( pcie_cq_np_req ),
.pcie_cq_np_req_count ( pcie_cq_np_req_count ),
.cfg_phy_link_down ( cfg_phy_link_down ),
.cfg_phy_link_status ( cfg_phy_link_status),
.cfg_negotiated_width ( cfg_negotiated_width ),
.cfg_current_speed ( cfg_current_speed ),
.cfg_max_payload ( cfg_max_payload ),
.cfg_max_read_req ( cfg_max_read_req ),
.cfg_function_status ( cfg_function_status ),
.cfg_function_power_state ( cfg_function_power_state ),
.cfg_vf_status ( cfg_vf_status ),
.cfg_vf_power_state ( cfg_vf_power_state ),
.cfg_link_power_state ( cfg_link_power_state ),
// Error Reporting Interface
.cfg_err_cor_out ( cfg_err_cor_out ),
.cfg_err_nonfatal_out ( cfg_err_nonfatal_out ),
.cfg_err_fatal_out ( cfg_err_fatal_out ),
.cfg_ltr_enable ( cfg_ltr_enable ),
.cfg_ltssm_state ( cfg_ltssm_state ),
.cfg_rcb_status ( cfg_rcb_status ),
.cfg_dpa_substate_change ( cfg_dpa_substate_change ),
.cfg_obff_enable ( cfg_obff_enable ),
.cfg_pl_status_change ( cfg_pl_status_change ),
.cfg_tph_requester_enable ( cfg_tph_requester_enable ),
.cfg_tph_st_mode ( cfg_tph_st_mode ),
.cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ),
.cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ),
.cfg_fc_ph ( cfg_fc_ph ),
.cfg_fc_pd ( cfg_fc_pd ),
.cfg_fc_nph ( cfg_fc_nph ),
.cfg_fc_npd ( cfg_fc_npd ),
.cfg_fc_cplh ( cfg_fc_cplh ),
.cfg_fc_cpld ( cfg_fc_cpld ),
.cfg_fc_sel ( cfg_fc_sel ),
//---------------------------------------------------------------------
// EP Only
//---------------------------------------------------------------------
// Interrupt Interface Signals
.cfg_interrupt_int ( cfg_interrupt_int ),
.cfg_interrupt_pending ( cfg_interrupt_pending ),
.cfg_interrupt_sent ( cfg_interrupt_sent ),
.cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ),
.cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ),
.cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ),
.cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ),
.cfg_interrupt_msi_data ( cfg_interrupt_msi_data ),
.cfg_interrupt_msi_select ( cfg_interrupt_msi_select ),
.cfg_interrupt_msi_int ( cfg_interrupt_msi_int ),
.cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status ),
.cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ),
.cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ),
.cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ),
.cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ),
.cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ),
.cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ),
.cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ),
//---------------------------------------------------------------------
// System(SYS) Interface
//---------------------------------------------------------------------
.sys_clk (pcie_refclk),
.sys_reset (~pcie_reset_n));
riffa_wrapper_adm7V3
#(/*AUTOINSTPARAM*/
// Parameters
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES),
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS))
riffa
(// Outputs
.M_AXIS_CQ_TREADY (m_axis_cq_tready),
.M_AXIS_RC_TREADY (m_axis_rc_tready),
.S_AXIS_CC_TVALID (s_axis_cc_tvalid),
.S_AXIS_CC_TLAST (s_axis_cc_tlast),
.S_AXIS_CC_TDATA (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (s_axis_rq_tvalid),
.S_AXIS_RQ_TLAST (s_axis_rq_tlast),
.S_AXIS_RQ_TDATA (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]),
.USER_CLK (user_clk),
.USER_RESET (user_reset),
.CFG_INTERRUPT_INT (cfg_interrupt_int[3:0]),
.CFG_INTERRUPT_PENDING (cfg_interrupt_pending[1:0]),
.CFG_INTERRUPT_MSI_SELECT (cfg_interrupt_msi_select[3:0]),
.CFG_INTERRUPT_MSI_INT (cfg_interrupt_msi_int[31:0]),
.CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]),
.CFG_INTERRUPT_MSI_ATTR (cfg_interrupt_msi_attr[2:0]),
.CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present),
.CFG_INTERRUPT_MSI_TPH_TYPE (cfg_interrupt_msi_tph_type[1:0]),
.CFG_INTERRUPT_MSI_TPH_ST_TAG (cfg_interrupt_msi_tph_st_tag[8:0]),
.CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]),
.CFG_FC_SEL (cfg_fc_sel[2:0]),
.PCIE_CQ_NP_REQ (pcie_cq_np_req),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (m_axis_cq_tvalid),
.M_AXIS_CQ_TLAST (m_axis_cq_tlast),
.M_AXIS_CQ_TDATA (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (m_axis_rc_tvalid),
.M_AXIS_RC_TLAST (m_axis_rc_tlast),
.M_AXIS_RC_TDATA (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (s_axis_cc_tready),
.S_AXIS_RQ_TREADY (s_axis_rq_tready),
.CFG_INTERRUPT_MSI_ENABLE (cfg_interrupt_msi_enable[1:0]),
.CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update),
.CFG_INTERRUPT_MSI_DATA (cfg_interrupt_msi_data[31:0]),
.CFG_INTERRUPT_MSI_SENT (cfg_interrupt_msi_sent),
.CFG_INTERRUPT_MSI_FAIL (cfg_interrupt_msi_fail),
.CFG_FC_CPLH (cfg_fc_cplh[7:0]),
.CFG_FC_CPLD (cfg_fc_cpld[11:0]),
.CFG_NEGOTIATED_WIDTH (cfg_negotiated_width[3:0]),
.CFG_CURRENT_SPEED (cfg_current_speed[2:0]),
.CFG_MAX_PAYLOAD (cfg_max_payload[2:0]),
.CFG_MAX_READ_REQ (cfg_max_read_req[2:0]),
.CFG_FUNCTION_STATUS (cfg_function_status[7:0]),
.CFG_RCB_STATUS (cfg_rcb_status[1:0]),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0])
/*AUTOINST*/);
generate
for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
chnl_tester
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH))
module1
(.CLK(user_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[chnl]),
.CHNL_RX(chnl_rx[chnl]),
.CHNL_RX_ACK(chnl_rx_ack[chnl]),
.CHNL_RX_LAST(chnl_rx_last[chnl]),
.CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[chnl]),
.CHNL_TX(chnl_tx[chnl]),
.CHNL_TX_ACK(chnl_tx_ack[chnl]),
.CHNL_TX_LAST(chnl_tx_last[chnl]),
.CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
/*AUTOINST*/);
end
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("../../../../riffa_hdl/" "../../")
// End:
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 1.2
// \ \ Application : MIG
// / / Filename : wiredly.v
// /___/ /\ Date Last Modified : $Date: 2011/05/27 14:30:47 $
// \ \ / \ Date Created : Tue Sept 21 2010
// \___\/\___\
//
// Device : 7Series
// Design Name : DDR3 SDRAM
// Purpose :
// This module provide the definition of a zero ohm component (A, B).
//
// The applications of this component include:
// . Normal operation of a jumper wire (data flowing in both directions)
// This can corrupt data from DRAM to FPGA useful for verifying ECC function.
//
// The component consists of 2 ports:
// . Port A: One side of the pass-through switch
// . Port B: The other side of the pass-through switch
// The model is sensitive to transactions on all ports. Once a transaction
// is detected, all other transactions are ignored for that simulation time
// (i.e. further transactions in that delta time are ignored).
// Model Limitations and Restrictions:
// Signals asserted on the ports of the error injector should not have
// transactions occuring in multiple delta times because the model
// is sensitive to transactions on port A, B ONLY ONCE during
// a simulation time. Thus, once fired, a process will
// not refire if there are multiple transactions occuring in delta times.
// This condition may occur in gate level simulations with
// ZERO delays because transactions may occur in multiple delta times.
//
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ns / 1ps
module WireDelay # (
parameter Delay_g = 0,
parameter Delay_rd = 0,
parameter ERR_INSERT = "OFF"
)
(
inout A,
inout B,
input reset,
input phy_init_done
);
reg A_r;
reg B_r;
reg B_inv ;
reg line_en;
assign A = A_r;
assign B = B_r;
always@(*)
if((B == 'b1) || (B == 'b0))
B_inv <= #0 ~B ;
else
B_inv <= #0 'bz ;
// B_inv = (B == 1'bz) ? 1'bz : ~B;
always @(*) begin
if (!reset) begin
A_r <= 1'bz;
B_r <= 1'bz;
line_en <= 1'b0;
end else begin
if (line_en) begin
B_r <= 1'bz;
if ((ERR_INSERT == "ON") & (phy_init_done))
A_r <= #Delay_rd B_inv;
else
A_r <= #Delay_rd B;
end else begin
B_r <= #Delay_g A;
A_r <= 1'bz;
end
end
end
always @(A or B) begin
if (!reset) begin
line_en <= 1'b0;
end else if (A !== A_r) begin
line_en <= 1'b0;
end else if (B_r !== B) begin
line_en <= 1'b1;
end else begin
line_en <= line_en;
end
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:dragster_configurator:1.0
// IP Revision: 1
(* X_CORE_INFO = "dragster_configurator,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "image_processing_2d_design_dragster_configurator_0_0,dragster_configurator,{}" *)
(* CORE_GENERATION_INFO = "image_processing_2d_design_dragster_configurator_0_0,dragster_configurator,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=dragster_configurator,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_dragster_configurator_0_0 (
clk,
reset_n,
miso,
mosi,
sclk,
ss_n
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset_n RST" *)
input wire reset_n;
input wire miso;
output wire mosi;
output wire sclk;
output wire [1 : 0] ss_n;
dragster_configurator inst (
.clk(clk),
.reset_n(reset_n),
.miso(miso),
.mosi(mosi),
.sclk(sclk),
.ss_n(ss_n)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_BLACKBOX_V
`define SKY130_FD_SC_HVL__BUF_BLACKBOX_V
/**
* buf: Buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__buf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_BLACKBOX_V
|
`timescale 1ps/1ps
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner ([email protected])
//
// Copyright (c) 2004 Guy Hutchison ([email protected])
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
module tv80_core (/*AUTOARG*/
// Outputs
m1_n, iorq, no_read, write, rfsh_n, halt_n, busak_n, A, dout, mc,
ts, intcycle_n, IntE, stop,
// Inputs
reset_n, clk, cen, wait_n, int_n, nmi_n, busrq_n, dinst, di
);
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
parameter Mode = 1; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
parameter Flag_C = 0;
parameter Flag_N = 1;
parameter Flag_P = 2;
parameter Flag_X = 3;
parameter Flag_H = 4;
parameter Flag_Y = 5;
parameter Flag_Z = 6;
parameter Flag_S = 7;
input reset_n;
input clk;
input cen;
input wait_n;
input int_n;
input nmi_n;
input busrq_n;
output m1_n;
output iorq;
output no_read;
output write;
output rfsh_n;
output halt_n;
output busak_n;
output [15:0] A;
input [7:0] dinst;
input [7:0] di;
output [7:0] dout;
output [6:0] mc;
output [6:0] ts;
output intcycle_n;
output IntE;
output stop;
reg m1_n;
reg iorq;
`ifdef TV80_REFRESH
reg rfsh_n;
`endif
reg halt_n;
reg busak_n;
reg [15:0] A;
reg [7:0] dout;
reg [6:0] mc;
reg [6:0] ts;
reg intcycle_n;
reg IntE;
reg stop;
parameter aNone = 3'b111;
parameter aBC = 3'b000;
parameter aDE = 3'b001;
parameter aXY = 3'b010;
parameter aIOA = 3'b100;
parameter aSP = 3'b101;
parameter aZI = 3'b110;
// Registers
reg [7:0] ACC, F;
reg [7:0] Ap, Fp;
reg [7:0] I;
`ifdef TV80_REFRESH
reg [7:0] R;
`endif
reg [15:0] SP, PC;
reg [7:0] RegDIH;
reg [7:0] RegDIL;
wire [15:0] RegBusA;
wire [15:0] RegBusB;
wire [15:0] RegBusC;
reg [2:0] RegAddrA_r;
reg [2:0] RegAddrA;
reg [2:0] RegAddrB_r;
reg [2:0] RegAddrB;
reg [2:0] RegAddrC;
reg RegWEH;
reg RegWEL;
reg Alternate;
// Help Registers
reg [15:0] TmpAddr; // Temporary address register
reg [7:0] IR; // Instruction register
reg [1:0] ISet; // Instruction set selector
reg [15:0] RegBusA_r;
reg [15:0] ID16;
reg [7:0] Save_Mux;
reg [6:0] tstate;
reg [6:0] mcycle;
reg last_mcycle, last_tstate;
reg IntE_FF1;
reg IntE_FF2;
reg Halt_FF;
reg BusReq_s;
reg BusAck;
reg ClkEn;
reg NMI_s;
reg INT_s;
reg [1:0] IStatus;
reg [7:0] DI_Reg;
reg T_Res;
reg [1:0] XY_State;
reg [2:0] Pre_XY_F_M;
reg NextIs_XY_Fetch;
reg XY_Ind;
reg No_BTR;
reg BTR_r;
reg Auto_Wait;
reg Auto_Wait_t1;
reg Auto_Wait_t2;
reg IncDecZ;
// ALU signals
reg [7:0] BusB;
reg [7:0] BusA;
wire [7:0] ALU_Q;
wire [7:0] F_Out;
// Registered micro code outputs
reg [4:0] Read_To_Reg_r;
reg Arith16_r;
reg Z16_r;
reg [3:0] ALU_Op_r;
reg Save_ALU_r;
reg PreserveC_r;
reg [2:0] mcycles;
// Micro code outputs
wire [2:0] mcycles_d;
wire [2:0] tstates;
reg IntCycle;
reg NMICycle;
wire Inc_PC;
wire Inc_WZ;
wire [3:0] IncDec_16;
wire [1:0] Prefix;
wire Read_To_Acc;
wire Read_To_Reg;
wire [3:0] Set_BusB_To;
wire [3:0] Set_BusA_To;
wire [3:0] ALU_Op;
wire Save_ALU;
wire PreserveC;
wire Arith16;
wire [2:0] Set_Addr_To;
wire Jump;
wire JumpE;
wire JumpXY;
wire Call;
wire RstP;
wire LDZ;
wire LDW;
wire LDSPHL;
wire iorq_i;
wire [2:0] Special_LD;
wire ExchangeDH;
wire ExchangeRp;
wire ExchangeAF;
wire ExchangeRS;
wire I_DJNZ;
wire I_CPL;
wire I_CCF;
wire I_SCF;
wire I_RETN;
wire I_BT;
wire I_BC;
wire I_BTR;
wire I_RLD;
wire I_RRD;
wire I_INRC;
wire SetDI;
wire SetEI;
wire [1:0] IMode;
wire Halt;
reg [15:0] PC16;
reg [15:0] PC16_B;
reg [15:0] SP16, SP16_A, SP16_B;
reg [15:0] ID16_B;
reg Oldnmi_n;
tv80_mcode #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_mcode
(
.IR (IR),
.ISet (ISet),
.MCycle (mcycle),
.F (F),
.NMICycle (NMICycle),
.IntCycle (IntCycle),
.MCycles (mcycles_d),
.TStates (tstates),
.Prefix (Prefix),
.Inc_PC (Inc_PC),
.Inc_WZ (Inc_WZ),
.IncDec_16 (IncDec_16),
.Read_To_Acc (Read_To_Acc),
.Read_To_Reg (Read_To_Reg),
.Set_BusB_To (Set_BusB_To),
.Set_BusA_To (Set_BusA_To),
.ALU_Op (ALU_Op),
.Save_ALU (Save_ALU),
.PreserveC (PreserveC),
.Arith16 (Arith16),
.Set_Addr_To (Set_Addr_To),
.IORQ (iorq_i),
.Jump (Jump),
.JumpE (JumpE),
.JumpXY (JumpXY),
.Call (Call),
.RstP (RstP),
.LDZ (LDZ),
.LDW (LDW),
.LDSPHL (LDSPHL),
.Special_LD (Special_LD),
.ExchangeDH (ExchangeDH),
.ExchangeRp (ExchangeRp),
.ExchangeAF (ExchangeAF),
.ExchangeRS (ExchangeRS),
.I_DJNZ (I_DJNZ),
.I_CPL (I_CPL),
.I_CCF (I_CCF),
.I_SCF (I_SCF),
.I_RETN (I_RETN),
.I_BT (I_BT),
.I_BC (I_BC),
.I_BTR (I_BTR),
.I_RLD (I_RLD),
.I_RRD (I_RRD),
.I_INRC (I_INRC),
.SetDI (SetDI),
.SetEI (SetEI),
.IMode (IMode),
.Halt (Halt),
.NoRead (no_read),
.Write (write)
);
tv80_alu #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_alu
(
.Arith16 (Arith16_r),
.Z16 (Z16_r),
.ALU_Op (ALU_Op_r),
.IR (IR[5:0]),
.ISet (ISet),
.BusA (BusA),
.BusB (BusB),
.F_In (F),
.Q (ALU_Q),
.F_Out (F_Out)
);
function [6:0] number_to_bitvec;
input [2:0] num;
begin
case (num)
1 : number_to_bitvec = 7'b0000001;
2 : number_to_bitvec = 7'b0000010;
3 : number_to_bitvec = 7'b0000100;
4 : number_to_bitvec = 7'b0001000;
5 : number_to_bitvec = 7'b0010000;
6 : number_to_bitvec = 7'b0100000;
7 : number_to_bitvec = 7'b1000000;
default : number_to_bitvec = 7'bx;
endcase // case(num)
end
endfunction // number_to_bitvec
function [2:0] mcyc_to_number;
input [6:0] mcyc;
begin
casez (mcyc)
7'b1zzzzzz : mcyc_to_number = 3'h7;
7'b01zzzzz : mcyc_to_number = 3'h6;
7'b001zzzz : mcyc_to_number = 3'h5;
7'b0001zzz : mcyc_to_number = 3'h4;
7'b00001zz : mcyc_to_number = 3'h3;
7'b000001z : mcyc_to_number = 3'h2;
7'b0000001 : mcyc_to_number = 3'h1;
default : mcyc_to_number = 3'h1;
endcase
end
endfunction
always @(/*AUTOSENSE*/mcycle or mcycles or tstate or tstates)
begin
case (mcycles)
1 : last_mcycle = mcycle[0];
2 : last_mcycle = mcycle[1];
3 : last_mcycle = mcycle[2];
4 : last_mcycle = mcycle[3];
5 : last_mcycle = mcycle[4];
6 : last_mcycle = mcycle[5];
7 : last_mcycle = mcycle[6];
default : last_mcycle = 1'bx;
endcase // case(mcycles)
case (tstates)
0 : last_tstate = tstate[0];
1 : last_tstate = tstate[1];
2 : last_tstate = tstate[2];
3 : last_tstate = tstate[3];
4 : last_tstate = tstate[4];
5 : last_tstate = tstate[5];
6 : last_tstate = tstate[6];
default : last_tstate = 1'bx;
endcase
end // always @ (...
always @(/*AUTOSENSE*/ALU_Q or BusAck or BusB or DI_Reg
or ExchangeRp or IR or Save_ALU_r or Set_Addr_To or XY_Ind
or XY_State or cen or last_tstate or mcycle)
begin
ClkEn = cen && ~ BusAck;
if (last_tstate)
T_Res = 1'b1;
else T_Res = 1'b0;
if (XY_State != 2'b00 && XY_Ind == 1'b0 &&
((Set_Addr_To == aXY) ||
(mcycle[0] && IR == 8'b11001011) ||
(mcycle[0] && IR == 8'b00110110)))
NextIs_XY_Fetch = 1'b1;
else
NextIs_XY_Fetch = 1'b0;
if (ExchangeRp)
Save_Mux = BusB;
else if (!Save_ALU_r)
Save_Mux = DI_Reg;
else
Save_Mux = ALU_Q;
end // always @ *
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0 )
begin
PC <= #1 0; // Program Counter
A <= #1 0;
TmpAddr <= #1 0;
IR <= #1 8'b00000000;
ISet <= #1 2'b00;
XY_State <= #1 2'b00;
IStatus <= #1 2'b00;
mcycles <= #1 3'b000;
dout <= #1 8'b00000000;
ACC <= #1 8'hFF;
F <= #1 8'hFF;
Ap <= #1 8'hFF;
Fp <= #1 8'hFF;
I <= #1 0;
`ifdef TV80_REFRESH
R <= #1 0;
`endif
SP <= #1 16'hFFFF;
Alternate <= #1 1'b0;
Read_To_Reg_r <= #1 5'b00000;
Arith16_r <= #1 1'b0;
BTR_r <= #1 1'b0;
Z16_r <= #1 1'b0;
ALU_Op_r <= #1 4'b0000;
Save_ALU_r <= #1 1'b0;
PreserveC_r <= #1 1'b0;
XY_Ind <= #1 1'b0;
end
else
begin
if (ClkEn == 1'b1 )
begin
ALU_Op_r <= #1 4'b0000;
Save_ALU_r <= #1 1'b0;
Read_To_Reg_r <= #1 5'b00000;
mcycles <= #1 mcycles_d;
if (IMode != 2'b11 )
begin
IStatus <= #1 IMode;
end
Arith16_r <= #1 Arith16;
PreserveC_r <= #1 PreserveC;
if (ISet == 2'b10 && ALU_Op[2] == 1'b0 && ALU_Op[0] == 1'b1 && mcycle[2] )
begin
Z16_r <= #1 1'b1;
end
else
begin
Z16_r <= #1 1'b0;
end
if (mcycle[0] && (tstate[1] | tstate[2] | tstate[3] ))
begin
// mcycle == 1 && tstate == 1, 2, || 3
if (tstate[2] && wait_n == 1'b1 )
begin
`ifdef TV80_REFRESH
if (Mode < 2 )
begin
A[7:0] <= #1 R;
A[15:8] <= #1 I;
R[6:0] <= #1 R[6:0] + 1;
end
`endif
if (Jump == 1'b0 && Call == 1'b0 && NMICycle == 1'b0 && IntCycle == 1'b0 && ~ (Halt_FF == 1'b1 || Halt == 1'b1) )
begin
PC <= #1 PC16;
end
if (IntCycle == 1'b1 && IStatus == 2'b01 )
begin
IR <= #1 8'b11111111;
end
else if (Halt_FF == 1'b1 || (IntCycle == 1'b1 && IStatus == 2'b10) || NMICycle == 1'b1 )
begin
IR <= #1 8'b00000000;
TmpAddr[7:0] <= #1 dinst; // Special M1 vector fetch
end
else
begin
IR <= #1 dinst;
end
ISet <= #1 2'b00;
if (Prefix != 2'b00 )
begin
if (Prefix == 2'b11 )
begin
if (IR[5] == 1'b1 )
begin
XY_State <= #1 2'b10;
end
else
begin
XY_State <= #1 2'b01;
end
end
else
begin
if (Prefix == 2'b10 )
begin
XY_State <= #1 2'b00;
XY_Ind <= #1 1'b0;
end
ISet <= #1 Prefix;
end
end
else
begin
XY_State <= #1 2'b00;
XY_Ind <= #1 1'b0;
end
end // if (tstate == 2 && wait_n == 1'b1 )
end
else
begin
// either (mcycle > 1) OR (mcycle == 1 AND tstate > 3)
if (mcycle[5] )
begin
XY_Ind <= #1 1'b1;
if (Prefix == 2'b01 )
begin
ISet <= #1 2'b01;
end
end
if (T_Res == 1'b1 )
begin
BTR_r <= #1 (I_BT || I_BC || I_BTR) && ~ No_BTR;
if (Jump == 1'b1 )
begin
A[15:8] <= #1 DI_Reg;
A[7:0] <= #1 TmpAddr[7:0];
PC[15:8] <= #1 DI_Reg;
PC[7:0] <= #1 TmpAddr[7:0];
end
else if (JumpXY == 1'b1 )
begin
A <= #1 RegBusC;
PC <= #1 RegBusC;
end else if (Call == 1'b1 || RstP == 1'b1 )
begin
A <= #1 TmpAddr;
PC <= #1 TmpAddr;
end
else if (last_mcycle && NMICycle == 1'b1 )
begin
A <= #1 16'b0000000001100110;
PC <= #1 16'b0000000001100110;
end
else if (mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 )
begin
A[15:8] <= #1 I;
A[7:0] <= #1 TmpAddr[7:0];
PC[15:8] <= #1 I;
PC[7:0] <= #1 TmpAddr[7:0];
end
else
begin
case (Set_Addr_To)
aXY :
begin
if (XY_State == 2'b00 )
begin
A <= #1 RegBusC;
end
else
begin
if (NextIs_XY_Fetch == 1'b1 )
begin
A <= #1 PC;
end
else
begin
A <= #1 TmpAddr;
end
end // else: !if(XY_State == 2'b00 )
end // case: aXY
aIOA :
begin
if (Mode == 3 )
begin
// Memory map I/O on GBZ80
A[15:8] <= #1 8'hFF;
end
else if (Mode == 2 )
begin
// Duplicate I/O address on 8080
A[15:8] <= #1 DI_Reg;
end
else
begin
A[15:8] <= #1 ACC;
end
A[7:0] <= #1 DI_Reg;
end // case: aIOA
aSP :
begin
A <= #1 SP;
end
aBC :
begin
if (Mode == 3 && iorq_i == 1'b1 )
begin
// Memory map I/O on GBZ80
A[15:8] <= #1 8'hFF;
A[7:0] <= #1 RegBusC[7:0];
end
else
begin
A <= #1 RegBusC;
end
end // case: aBC
aDE :
begin
A <= #1 RegBusC;
end
aZI :
begin
if (Inc_WZ == 1'b1 )
begin
A <= #1 TmpAddr + 1;
end
else
begin
A[15:8] <= #1 DI_Reg;
A[7:0] <= #1 TmpAddr[7:0];
end
end // case: aZI
default :
begin
A <= #1 PC;
end
endcase // case(Set_Addr_To)
end // else: !if(mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 )
Save_ALU_r <= #1 Save_ALU;
ALU_Op_r <= #1 ALU_Op;
if (I_CPL == 1'b1 )
begin
// CPL
ACC <= #1 ~ ACC;
F[Flag_Y] <= #1 ~ ACC[5];
F[Flag_H] <= #1 1'b1;
F[Flag_X] <= #1 ~ ACC[3];
F[Flag_N] <= #1 1'b1;
end
if (I_CCF == 1'b1 )
begin
// CCF
F[Flag_C] <= #1 ~ F[Flag_C];
F[Flag_Y] <= #1 ACC[5];
F[Flag_H] <= #1 F[Flag_C];
F[Flag_X] <= #1 ACC[3];
F[Flag_N] <= #1 1'b0;
end
if (I_SCF == 1'b1 )
begin
// SCF
F[Flag_C] <= #1 1'b1;
F[Flag_Y] <= #1 ACC[5];
F[Flag_H] <= #1 1'b0;
F[Flag_X] <= #1 ACC[3];
F[Flag_N] <= #1 1'b0;
end
end // if (T_Res == 1'b1 )
if (tstate[2] && wait_n == 1'b1 )
begin
if (ISet == 2'b01 && mcycle[6] )
begin
IR <= #1 dinst;
end
if (JumpE == 1'b1 )
begin
PC <= #1 PC16;
end
else if (Inc_PC == 1'b1 )
begin
//PC <= #1 PC + 1;
PC <= #1 PC16;
end
if (BTR_r == 1'b1 )
begin
//PC <= #1 PC - 2;
PC <= #1 PC16;
end
if (RstP == 1'b1 )
begin
TmpAddr <= #1 { 10'h0, IR[5:3], 3'h0 };
//TmpAddr <= #1 (others =>1'b0);
//TmpAddr[5:3] <= #1 IR[5:3];
end
end
if (tstate[3] && mcycle[5] )
begin
TmpAddr <= #1 SP16;
end
if ((tstate[2] && wait_n == 1'b1) || (tstate[4] && mcycle[0]) )
begin
if (IncDec_16[2:0] == 3'b111 )
begin
SP <= #1 SP16;
end
end
if (LDSPHL == 1'b1 )
begin
SP <= #1 RegBusC;
end
if (ExchangeAF == 1'b1 )
begin
Ap <= #1 ACC;
ACC <= #1 Ap;
Fp <= #1 F;
F <= #1 Fp;
end
if (ExchangeRS == 1'b1 )
begin
Alternate <= #1 ~ Alternate;
end
end // else: !if(mcycle == 3'b001 && tstate(2) == 1'b0 )
if (tstate[3] )
begin
if (LDZ == 1'b1 )
begin
TmpAddr[7:0] <= #1 DI_Reg;
end
if (LDW == 1'b1 )
begin
TmpAddr[15:8] <= #1 DI_Reg;
end
if (Special_LD[2] == 1'b1 )
begin
case (Special_LD[1:0])
2'b00 :
begin
ACC <= #1 I;
F[Flag_P] <= #1 IntE_FF2;
F[Flag_Z] <= (I == 0);
F[Flag_S] <= I[7];
F[Flag_H] <= 0;
F[Flag_N] <= 0;
end
2'b01 :
begin
`ifdef TV80_REFRESH
ACC <= #1 R;
`else
ACC <= #1 0;
`endif
F[Flag_P] <= #1 IntE_FF2;
F[Flag_Z] <= (I == 0);
F[Flag_S] <= I[7];
F[Flag_H] <= 0;
F[Flag_N] <= 0;
end
2'b10 :
I <= #1 ACC;
`ifdef TV80_REFRESH
default :
R <= #1 ACC;
`else
default : ;
`endif
endcase
end
end // if (tstate == 3 )
if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 )
begin
if (Mode == 3 )
begin
F[6] <= #1 F_Out[6];
F[5] <= #1 F_Out[5];
F[7] <= #1 F_Out[7];
if (PreserveC_r == 1'b0 )
begin
F[4] <= #1 F_Out[4];
end
end
else
begin
F[7:1] <= #1 F_Out[7:1];
if (PreserveC_r == 1'b0 )
begin
F[Flag_C] <= #1 F_Out[0];
end
end
end // if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 )
if (T_Res == 1'b1 && I_INRC == 1'b1 )
begin
F[Flag_H] <= #1 1'b0;
F[Flag_N] <= #1 1'b0;
if (DI_Reg[7:0] == 8'b00000000 )
begin
F[Flag_Z] <= #1 1'b1;
end
else
begin
F[Flag_Z] <= #1 1'b0;
end
F[Flag_S] <= #1 DI_Reg[7];
F[Flag_P] <= #1 ~ (^DI_Reg[7:0]);
end // if (T_Res == 1'b1 && I_INRC == 1'b1 )
if (tstate[1] && Auto_Wait_t1 == 1'b0 )
begin
dout <= #1 BusB;
if (I_RLD == 1'b1 )
begin
dout[3:0] <= #1 BusA[3:0];
dout[7:4] <= #1 BusB[3:0];
end
if (I_RRD == 1'b1 )
begin
dout[3:0] <= #1 BusB[7:4];
dout[7:4] <= #1 BusA[3:0];
end
end
if (T_Res == 1'b1 )
begin
Read_To_Reg_r[3:0] <= #1 Set_BusA_To;
Read_To_Reg_r[4] <= #1 Read_To_Reg;
if (Read_To_Acc == 1'b1 )
begin
Read_To_Reg_r[3:0] <= #1 4'b0111;
Read_To_Reg_r[4] <= #1 1'b1;
end
end
if (tstate[1] && I_BT == 1'b1 )
begin
F[Flag_X] <= #1 ALU_Q[3];
F[Flag_Y] <= #1 ALU_Q[1];
F[Flag_H] <= #1 1'b0;
F[Flag_N] <= #1 1'b0;
end
if (I_BC == 1'b1 || I_BT == 1'b1 )
begin
F[Flag_P] <= #1 IncDecZ;
end
if ((tstate[1] && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||
(Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) )
begin
case (Read_To_Reg_r)
5'b10111 :
ACC <= #1 Save_Mux;
5'b10110 :
dout <= #1 Save_Mux;
5'b11000 :
SP[7:0] <= #1 Save_Mux;
5'b11001 :
SP[15:8] <= #1 Save_Mux;
5'b11011 :
F <= #1 Save_Mux;
default : ;
endcase
end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...
end // if (ClkEn == 1'b1 )
end // else: !if(reset_n == 1'b0 )
end
//-------------------------------------------------------------------------
//
// BC('), DE('), HL('), IX && IY
//
//-------------------------------------------------------------------------
always @ (posedge clk)
begin
if (ClkEn == 1'b1 )
begin
// Bus A / Write
RegAddrA_r <= #1 { Alternate, Set_BusA_To[2:1] };
if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusA_To[2:1] == 2'b10 )
begin
RegAddrA_r <= #1 { XY_State[1], 2'b11 };
end
// Bus B
RegAddrB_r <= #1 { Alternate, Set_BusB_To[2:1] };
if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusB_To[2:1] == 2'b10 )
begin
RegAddrB_r <= #1 { XY_State[1], 2'b11 };
end
// Address from register
RegAddrC <= #1 { Alternate, Set_Addr_To[1:0] };
// Jump (HL), LD SP,HL
if ((JumpXY == 1'b1 || LDSPHL == 1'b1) )
begin
RegAddrC <= #1 { Alternate, 2'b10 };
end
if (((JumpXY == 1'b1 || LDSPHL == 1'b1) && XY_State != 2'b00) || (mcycle[5]) )
begin
RegAddrC <= #1 { XY_State[1], 2'b11 };
end
if (I_DJNZ == 1'b1 && Save_ALU_r == 1'b1 && Mode < 2 )
begin
IncDecZ <= #1 F_Out[Flag_Z];
end
if ((tstate[2] || (tstate[3] && mcycle[0])) && IncDec_16[2:0] == 3'b100 )
begin
if (ID16 == 0 )
begin
IncDecZ <= #1 1'b0;
end
else
begin
IncDecZ <= #1 1'b1;
end
end
RegBusA_r <= #1 RegBusA;
end
end // always @ (posedge clk)
always @(/*AUTOSENSE*/Alternate or ExchangeDH or IncDec_16
or RegAddrA_r or RegAddrB_r or XY_State or mcycle or tstate)
begin
if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && XY_State == 2'b00)
RegAddrA = { Alternate, IncDec_16[1:0] };
else if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && IncDec_16[1:0] == 2'b10)
RegAddrA = { XY_State[1], 2'b11 };
else if (ExchangeDH == 1'b1 && tstate[3])
RegAddrA = { Alternate, 2'b10 };
else if (ExchangeDH == 1'b1 && tstate[4])
RegAddrA = { Alternate, 2'b01 };
else
RegAddrA = RegAddrA_r;
if (ExchangeDH == 1'b1 && tstate[3])
RegAddrB = { Alternate, 2'b01 };
else
RegAddrB = RegAddrB_r;
end // always @ *
always @(/*AUTOSENSE*/ALU_Op_r or Auto_Wait_t1 or ExchangeDH
or IncDec_16 or Read_To_Reg_r or Save_ALU_r or mcycle
or tstate or wait_n)
begin
RegWEH = 1'b0;
RegWEL = 1'b0;
if ((tstate[1] && ~Save_ALU_r && ~Auto_Wait_t1) ||
(Save_ALU_r && (ALU_Op_r != 4'b0111)) )
begin
case (Read_To_Reg_r)
5'b10000 , 5'b10001 , 5'b10010 , 5'b10011 , 5'b10100 , 5'b10101 :
begin
RegWEH = ~ Read_To_Reg_r[0];
RegWEL = Read_To_Reg_r[0];
end // UNMATCHED !!
default : ;
endcase // case(Read_To_Reg_r)
end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...
if (ExchangeDH && (tstate[3] || tstate[4]) )
begin
RegWEH = 1'b1;
RegWEL = 1'b1;
end
if (IncDec_16[2] && ((tstate[2] && wait_n && ~mcycle[0]) || (tstate[3] && mcycle[0])) )
begin
case (IncDec_16[1:0])
2'b00 , 2'b01 , 2'b10 :
begin
RegWEH = 1'b1;
RegWEL = 1'b1;
end // UNMATCHED !!
default : ;
endcase
end
end // always @ *
always @(/*AUTOSENSE*/ExchangeDH or ID16 or IncDec_16 or RegBusA_r
or RegBusB or Save_Mux or mcycle or tstate)
begin
RegDIH = Save_Mux;
RegDIL = Save_Mux;
if (ExchangeDH == 1'b1 && tstate[3] )
begin
RegDIH = RegBusB[15:8];
RegDIL = RegBusB[7:0];
end
else if (ExchangeDH == 1'b1 && tstate[4] )
begin
RegDIH = RegBusA_r[15:8];
RegDIL = RegBusA_r[7:0];
end
else if (IncDec_16[2] == 1'b1 && ((tstate[2] && ~mcycle[0]) || (tstate[3] && mcycle[0])) )
begin
RegDIH = ID16[15:8];
RegDIL = ID16[7:0];
end
end
tv80_reg i_reg
(
.clk (clk),
.CEN (ClkEn),
.WEH (RegWEH),
.WEL (RegWEL),
.AddrA (RegAddrA),
.AddrB (RegAddrB),
.AddrC (RegAddrC),
.DIH (RegDIH),
.DIL (RegDIL),
.DOAH (RegBusA[15:8]),
.DOAL (RegBusA[7:0]),
.DOBH (RegBusB[15:8]),
.DOBL (RegBusB[7:0]),
.DOCH (RegBusC[15:8]),
.DOCL (RegBusC[7:0])
);
//-------------------------------------------------------------------------
//
// Buses
//
//-------------------------------------------------------------------------
always @ (posedge clk)
begin
if (ClkEn == 1'b1 )
begin
case (Set_BusB_To)
4'b0111 :
BusB <= #1 ACC;
4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 :
begin
if (Set_BusB_To[0] == 1'b1 )
begin
BusB <= #1 RegBusB[7:0];
end
else
begin
BusB <= #1 RegBusB[15:8];
end
end
4'b0110 :
BusB <= #1 DI_Reg;
4'b1000 :
BusB <= #1 SP[7:0];
4'b1001 :
BusB <= #1 SP[15:8];
4'b1010 :
BusB <= #1 8'b00000001;
4'b1011 :
BusB <= #1 F;
4'b1100 :
BusB <= #1 PC[7:0];
4'b1101 :
BusB <= #1 PC[15:8];
4'b1110 :
BusB <= #1 8'b00000000;
default :
BusB <= #1 8'h0;
endcase
case (Set_BusA_To)
4'b0111 :
BusA <= #1 ACC;
4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 :
begin
if (Set_BusA_To[0] == 1'b1 )
begin
BusA <= #1 RegBusA[7:0];
end
else
begin
BusA <= #1 RegBusA[15:8];
end
end
4'b0110 :
BusA <= #1 DI_Reg;
4'b1000 :
BusA <= #1 SP[7:0];
4'b1001 :
BusA <= #1 SP[15:8];
4'b1010 :
BusA <= #1 8'b00000000;
default :
BusA <= #1 8'h0;
endcase
end
end
//-------------------------------------------------------------------------
//
// Generate external control signals
//
//-------------------------------------------------------------------------
`ifdef TV80_REFRESH
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0 )
begin
rfsh_n <= #1 1'b1;
end
else
begin
if (cen == 1'b1 )
begin
if (mcycle[0] && ((tstate[2] && wait_n == 1'b1) || tstate[3]) )
begin
rfsh_n <= #1 1'b0;
end
else
begin
rfsh_n <= #1 1'b1;
end
end
end
end // always @ (posedge clk or negedge reset_n)
`else // !`ifdef TV80_REFRESH
assign rfsh_n = 1'b1;
`endif
always @(/*AUTOSENSE*/BusAck or Halt_FF or I_DJNZ or IntCycle
or IntE_FF1 or di or iorq_i or mcycle or tstate)
begin
mc = mcycle;
ts = tstate;
DI_Reg = di;
halt_n = ~ Halt_FF;
busak_n = ~ BusAck;
intcycle_n = ~ IntCycle;
IntE = IntE_FF1;
iorq = iorq_i;
stop = I_DJNZ;
end
//-----------------------------------------------------------------------
//
// Syncronise inputs
//
//-----------------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : sync_inputs
if (~reset_n)
begin
BusReq_s <= #1 1'b0;
INT_s <= #1 1'b0;
NMI_s <= #1 1'b0;
Oldnmi_n <= #1 1'b0;
end
else
begin
if (cen == 1'b1 )
begin
BusReq_s <= #1 ~ busrq_n;
INT_s <= #1 ~ int_n;
if (NMICycle == 1'b1 )
begin
NMI_s <= #1 1'b0;
end
else if (nmi_n == 1'b0 && Oldnmi_n == 1'b1 )
begin
NMI_s <= #1 1'b1;
end
Oldnmi_n <= #1 nmi_n;
end
end
end
//-----------------------------------------------------------------------
//
// Main state machine
//
//-----------------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0 )
begin
mcycle <= #1 7'b0000001;
tstate <= #1 7'b0000001;
Pre_XY_F_M <= #1 3'b000;
Halt_FF <= #1 1'b0;
BusAck <= #1 1'b0;
NMICycle <= #1 1'b0;
IntCycle <= #1 1'b0;
IntE_FF1 <= #1 1'b0;
IntE_FF2 <= #1 1'b0;
No_BTR <= #1 1'b0;
Auto_Wait_t1 <= #1 1'b0;
Auto_Wait_t2 <= #1 1'b0;
m1_n <= #1 1'b1;
end
else
begin
if (cen == 1'b1 )
begin
if (T_Res == 1'b1 )
begin
Auto_Wait_t1 <= #1 1'b0;
end
else
begin
Auto_Wait_t1 <= #1 Auto_Wait || (iorq_i & ~Auto_Wait_t2);
end
Auto_Wait_t2 <= #1 Auto_Wait_t1 & !T_Res;
No_BTR <= #1 (I_BT && (~ IR[4] || ~ F[Flag_P])) ||
(I_BC && (~ IR[4] || F[Flag_Z] || ~ F[Flag_P])) ||
(I_BTR && (~ IR[4] || F[Flag_Z]));
if (tstate[2] )
begin
if (SetEI == 1'b1 )
begin
if (!NMICycle)
IntE_FF1 <= #1 1'b1;
IntE_FF2 <= #1 1'b1;
end
if (I_RETN == 1'b1 )
begin
IntE_FF1 <= #1 IntE_FF2;
end
end
if (tstate[3] )
begin
if (SetDI == 1'b1 )
begin
IntE_FF1 <= #1 1'b0;
IntE_FF2 <= #1 1'b0;
end
end
if (IntCycle == 1'b1 || NMICycle == 1'b1 )
begin
Halt_FF <= #1 1'b0;
end
if (mcycle[0] && tstate[2] && wait_n == 1'b1 )
begin
m1_n <= #1 1'b1;
end
if (BusReq_s == 1'b1 && BusAck == 1'b1 )
begin
end
else
begin
BusAck <= #1 1'b0;
if (tstate[2] && wait_n == 1'b0 )
begin
end
else if (T_Res == 1'b1 )
begin
if (Halt == 1'b1 )
begin
Halt_FF <= #1 1'b1;
end
if (BusReq_s == 1'b1 )
begin
BusAck <= #1 1'b1;
end
else
begin
tstate <= #1 7'b0000010;
if (NextIs_XY_Fetch == 1'b1 )
begin
mcycle <= #1 7'b0100000;
Pre_XY_F_M <= #1 mcyc_to_number(mcycle);
if (IR == 8'b00110110 && Mode == 0 )
begin
Pre_XY_F_M <= #1 3'b010;
end
end
else if ((mcycle[6]) || (mcycle[5] && Mode == 1 && ISet != 2'b01) )
begin
mcycle <= #1 number_to_bitvec(Pre_XY_F_M + 1);
end
else if ((last_mcycle) ||
No_BTR == 1'b1 ||
(mcycle[1] && I_DJNZ == 1'b1 && IncDecZ == 1'b1) )
begin
m1_n <= #1 1'b0;
mcycle <= #1 7'b0000001;
IntCycle <= #1 1'b0;
NMICycle <= #1 1'b0;
if (NMI_s == 1'b1 && Prefix == 2'b00 )
begin
NMICycle <= #1 1'b1;
IntE_FF1 <= #1 1'b0;
end
else if ((IntE_FF1 == 1'b1 && INT_s == 1'b1) && Prefix == 2'b00 && SetEI == 1'b0 )
begin
IntCycle <= #1 1'b1;
IntE_FF1 <= #1 1'b0;
IntE_FF2 <= #1 1'b0;
end
end
else
begin
mcycle <= #1 { mcycle[5:0], mcycle[6] };
end
end
end
else
begin // verilog has no "nor" operator
if ( ~(Auto_Wait == 1'b1 && Auto_Wait_t2 == 1'b0) &&
~(IOWait == 1 && iorq_i == 1'b1 && Auto_Wait_t1 == 1'b0) )
begin
tstate <= #1 { tstate[5:0], tstate[6] };
end
end
end
if (tstate[0])
begin
m1_n <= #1 1'b0;
end
end
end
end
always @(/*AUTOSENSE*/BTR_r or DI_Reg or IncDec_16 or JumpE or PC
or RegBusA or RegBusC or SP or tstate)
begin
if (JumpE == 1'b1 )
begin
PC16_B = { {8{DI_Reg[7]}}, DI_Reg };
end
else if (BTR_r == 1'b1 )
begin
PC16_B = -2;
end
else
begin
PC16_B = 1;
end
if (tstate[3])
begin
SP16_A = RegBusC;
SP16_B = { {8{DI_Reg[7]}}, DI_Reg };
end
else
begin
// suspect that ID16 and SP16 could be shared
SP16_A = SP;
if (IncDec_16[3] == 1'b1)
SP16_B = -1;
else
SP16_B = 1;
end
if (IncDec_16[3])
ID16_B = -1;
else
ID16_B = 1;
ID16 = RegBusA + ID16_B;
PC16 = PC + PC16_B;
SP16 = SP16_A + SP16_B;
end // always @ *
always @(/*AUTOSENSE*/IntCycle or NMICycle or mcycle)
begin
Auto_Wait = 1'b0;
if (IntCycle == 1'b1 || NMICycle == 1'b1 )
begin
if (mcycle[0] )
begin
Auto_Wait = 1'b1;
end
end
end // always @ *
endmodule // T80
|
/*
This is the top level design for the DE1-SoC boards of UviSpace project.
The ghrd_top() module; hps processor instantiation and connection; and
the connection of the module's input/output signals to the corresponding
pins were obtained from the Terasic DE1-SoC Golden Hardware Reference
Design (GHRD) project. For more information about this basic project and
the board, you can visit their website (http://www.terasic.com/).
Some of the remaining modules are based on demonstrations provided by
Terasic for the DE1-Soc and the DM5 Camera.
The purpose of the design is to provide an FPGA circuit for configuring
and acquiring images from a camera attached to the GPIO1 port. Hence,
the following modules are used:
- soc_system_u0: This module provides an interface with the Qsys design.
The main component is the interface with the HPS processor and its main
peripherals. Moreover, there are the following Qsys components: led_pio,
dipsw_pio (for the switches), button_pio, clk_0, and pll_vga_clks.
- CCD_Capture: This module serves as an interface with the attached
camera. It reads pixels values and control inputs. Besides, it allows to
decide when to start and stop acquiring images. The clock input is fed
by the pixel clock.
- RAW2RGB: It formats the raw data obtained from the camera peripheral
to RGB values. Each pixel contains 3 components (Red, Green and Blue),
defined by 12 bits each one.
- rgb2hue: Gets the Hue component of the pixels from an RGB input. The
Hue is a very useful value for evaluating the colour properties of an
image, and thus for getting a red triangle in the image.
- Sdram_Control: This module is used for connecting to the external DRAM
memory and use it as a buffer between the camera input and the VGA
output, as both are run with different clock rates. For this purpose,
FIFO memories allowing simultaneous read and write operations are used.
- vga_controller: Module for sending control bits to the VGA peripheral.
The module has a set of parameters that defines the output resolution,
being by default 640x480.
- SEG7_LUT_8: This componet is used for showing the fram rate on the
hexadecimal 8-segments peripherals.
- camera_config: This module sends the default configuration to the
camera using the I2C standard.
NOTE: The desired design should have 2 FIFOs, in order to send 8 bits
per component to the VGA controller. However, there is a synchronization
error, and the values obtained in the second FIFO have an offset
relative to the first one i.e. The component sent by the second FIFO
corresponds to the one that was sent by the first one several iterations
ago, resulting on an horizontal shift. For this reason, the size per
pixel was reduced to 15 bits (1 zero and 5 bits per colour).
*/
`define ENABLE_HPS
//Top level entity. Contains the inputs and outputs wired to external pins.
module uvispace_top(
///////// ADC /////////
inout ADC_CS_N,
output ADC_DIN,
input ADC_DOUT,
output ADC_SCLK,
///////// AUD /////////
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
///////// CLOCK2 /////////
input CLOCK2_50,
///////// CLOCK3 /////////
input CLOCK3_50,
///////// CLOCK4 /////////
input CLOCK4_50,
///////// CLOCK /////////
input CLOCK_50,
///////// DRAM /////////
output [12:0] DRAM_ADDR, //Address Bus
output [1:0] DRAM_BA, //Bank address
output DRAM_CAS_N, //Column address strobe
output DRAM_CKE, //Clock enable
output DRAM_CLK, //Clock
output DRAM_CS_N, //Chip select
inout [15:0] DRAM_DQ, //Data Bus
output DRAM_LDQM, //Low-byte data mask
output DRAM_RAS_N, //Row adress strobe
output DRAM_UDQM, //High-byte data mask
output DRAM_WE_N, //Write enable
///////// FAN /////////
output FAN_CTRL,
///////// FPGA /////////
output FPGA_I2C_SCLK,
inout FPGA_I2C_SDAT,
///////// GPIO /////////
inout [35:0] GPIO_0,
inout [35:0] GPIO_1,
///////// HEX /////////
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
///////// HPS /////////
`ifdef ENABLE_HPS
inout HPS_CONV_USB_N,
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CKE,
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input [3:0] HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout [3:0] HPS_FLASH_DATA,
output HPS_FLASH_DCLK,
output HPS_FLASH_NCSO,
inout HPS_GSENSOR_INT,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_I2C2_SCLK,
inout HPS_I2C2_SDAT,
inout HPS_I2C_CONTROL,
inout HPS_KEY,
inout HPS_LED,
inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
output HPS_SPIM_CLK,
input HPS_SPIM_MISO,
output HPS_SPIM_MOSI,
inout HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout [7:0] HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
`endif /*ENABLE_HPS*/
///////// IRDA /////////
input IRDA_RXD,
output IRDA_TXD,
///////// KEY /////////
input [3:0] KEY,
///////// LEDR /////////
output [9:0] LEDR,
///////// PS2 /////////
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
///////// SW /////////
input [9:0] SW,
///////// TD /////////
input TD_CLK27,
input [7:0] TD_DATA,
input TD_HS,
output TD_RESET_N,
input TD_VS,
///////// VGA /////////
output [7:0] VGA_B,
output VGA_BLANK_N,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS
);
//=======================================================
// REG/WIRE declarations
//=======================================================
//HPS signals
wire hps2fpga_reset_n;
wire camera_soft_reset_n;
wire video_stream_reset_n;
wire clk_25;
wire clk_193;
wire clk_120;
wire clk_24;
//VGA signals
wire vga_enable;
integer vga_row;
integer vga_col;
//CCD peripheral signal
wire [11:0] CCD_DATA;
//CCD_Capture signals
wire [11:0] ccd_data_captured; //output data from CCD_Capture
wire ccd_dval; //valid output data
wire [15:0] X_Cont;
wire [15:0] Y_Cont;
reg [11:0] ccd_data_raw; //input raw data to CCD_Capture
reg ccd_fval_raw; //frame valid
reg ccd_lval_raw; //line valid
wire ccd_pixel_clk;
wire ccd_reset;
wire [31:0] Frame_Cont;
//RAW2RGB signals
wire [11:0] raw_rgb_red;
wire [11:0] raw_rgb_green;
wire [11:0] raw_rgb_blue;
wire raw_rgb_dval; //valid output data
//SDRAM FIFOs data
reg [15:0] fifo1_writedata;
reg [15:0] fifo2_writedata;
wire [15:0] fifo1_readdata;
wire [15:0] fifo2_readdata;
//=======================================================
// Structural coding
//=======================================================
soc_system u0 (
//Input clocks
.clk_50_clk ( CLOCK_50 ),
.ccd_pixel_clock_bridge_clk ( ccd_pixel_clk ),
//Output clocks
.pll_vga_clks_25_clk ( clk_25 ),
.pll_vga_clks_191_clk ( clk_193 ),
.pll_camera_clks_24_clk ( clk_24 ),
//HPS reset output
.h2f_reset_reset_n ( hps2fpga_reset_n ),
// Avalon camera capture_image signals
.avalon_camera_export_start_capture ( start_capture ),
.avalon_camera_export_capture_imgsize ( capture_imgsize ),
.avalon_camera_export_buff ( capture_buff ),
.avalon_camera_export_image_captured ( image_captured ),
.avalon_camera_export_capture_standby ( capture_standby ),
// Avalon camera camera_config signals
.avalon_camera_export_width ( in_width ),
.avalon_camera_export_height ( in_height ),
.avalon_camera_export_startrow ( start_row ),
.avalon_camera_export_startcol ( start_column ),
.avalon_camera_export_colmode ( in_column_mode ),
.avalon_camera_export_exposure ( in_exposure ),
.avalon_camera_export_rowsize ( in_row_size ),
.avalon_camera_export_colsize ( in_column_size ),
.avalon_camera_export_rowmode ( in_row_mode ),
.avalon_camera_export_soft_reset_n ( camera_soft_reset_n ),
// Bus for the image_capture component to write images in HPS-OCR
.avalon_write_bridge_0_avalon_slave_address ( image_capture_address ),
.avalon_write_bridge_0_avalon_slave_write ( image_capture_write ),
.avalon_write_bridge_0_avalon_slave_byteenable ( image_capture_byteenable ),
.avalon_write_bridge_0_avalon_slave_writedata ( image_capture_write_data ),
.avalon_write_bridge_0_avalon_slave_waitrequest ( image_capture_waitrequest),
.avalon_write_bridge_0_avalon_slave_burstcount ( image_capture_burstcount ),
//HPS ddr3
.memory_mem_a ( HPS_DDR3_ADDR ),
.memory_mem_ba ( HPS_DDR3_BA ),
.memory_mem_ck ( HPS_DDR3_CK_P ),
.memory_mem_ck_n ( HPS_DDR3_CK_N ),
.memory_mem_cke ( HPS_DDR3_CKE ),
.memory_mem_cs_n ( HPS_DDR3_CS_N ),
.memory_mem_ras_n ( HPS_DDR3_RAS_N ),
.memory_mem_cas_n ( HPS_DDR3_CAS_N ),
.memory_mem_we_n ( HPS_DDR3_WE_N ),
.memory_mem_reset_n ( HPS_DDR3_RESET_N) ,
.memory_mem_dq ( HPS_DDR3_DQ ),
.memory_mem_dqs_n ( HPS_DDR3_DQS_N ),
.memory_mem_dqs ( HPS_DDR3_DQS_P ),
.memory_mem_odt ( HPS_DDR3_ODT ),
.memory_mem_dm ( HPS_DDR3_DM ),
.memory_oct_rzqin ( HPS_DDR3_RZQ ),
//HPS ethernet
.hps_0_hps_io_hps_io_emac1_inst_TX_CLK ( HPS_ENET_GTX_CLK ),
.hps_0_hps_io_hps_io_emac1_inst_TXD0 ( HPS_ENET_TX_DATA[0] ),
.hps_0_hps_io_hps_io_emac1_inst_TXD1 ( HPS_ENET_TX_DATA[1] ),
.hps_0_hps_io_hps_io_emac1_inst_TXD2 ( HPS_ENET_TX_DATA[2] ),
.hps_0_hps_io_hps_io_emac1_inst_TXD3 ( HPS_ENET_TX_DATA[3] ),
.hps_0_hps_io_hps_io_emac1_inst_RXD0 ( HPS_ENET_RX_DATA[0] ),
.hps_0_hps_io_hps_io_emac1_inst_MDIO ( HPS_ENET_MDIO ),
.hps_0_hps_io_hps_io_emac1_inst_MDC ( HPS_ENET_MDC ),
.hps_0_hps_io_hps_io_emac1_inst_RX_CTL ( HPS_ENET_RX_DV ),
.hps_0_hps_io_hps_io_emac1_inst_TX_CTL ( HPS_ENET_TX_EN ),
.hps_0_hps_io_hps_io_emac1_inst_RX_CLK ( HPS_ENET_RX_CLK ),
.hps_0_hps_io_hps_io_emac1_inst_RXD1 ( HPS_ENET_RX_DATA[1] ),
.hps_0_hps_io_hps_io_emac1_inst_RXD2 ( HPS_ENET_RX_DATA[2] ),
.hps_0_hps_io_hps_io_emac1_inst_RXD3 ( HPS_ENET_RX_DATA[3] ),
//HPS QSPI
.hps_0_hps_io_hps_io_qspi_inst_IO0 ( HPS_FLASH_DATA[0] ),
.hps_0_hps_io_hps_io_qspi_inst_IO1 ( HPS_FLASH_DATA[1] ),
.hps_0_hps_io_hps_io_qspi_inst_IO2 ( HPS_FLASH_DATA[2] ),
.hps_0_hps_io_hps_io_qspi_inst_IO3 ( HPS_FLASH_DATA[3] ),
.hps_0_hps_io_hps_io_qspi_inst_SS0 ( HPS_FLASH_NCSO ),
.hps_0_hps_io_hps_io_qspi_inst_CLK ( HPS_FLASH_DCLK ),
//HPS SD card
.hps_0_hps_io_hps_io_sdio_inst_CMD ( HPS_SD_CMD ),
.hps_0_hps_io_hps_io_sdio_inst_D0 ( HPS_SD_DATA[0] ),
.hps_0_hps_io_hps_io_sdio_inst_D1 ( HPS_SD_DATA[1] ),
.hps_0_hps_io_hps_io_sdio_inst_CLK ( HPS_SD_CLK ),
.hps_0_hps_io_hps_io_sdio_inst_D2 ( HPS_SD_DATA[2] ),
.hps_0_hps_io_hps_io_sdio_inst_D3 ( HPS_SD_DATA[3] ),
//HPS USB
.hps_0_hps_io_hps_io_usb1_inst_D0 ( HPS_USB_DATA[0] ),
.hps_0_hps_io_hps_io_usb1_inst_D1 ( HPS_USB_DATA[1] ),
.hps_0_hps_io_hps_io_usb1_inst_D2 ( HPS_USB_DATA[2] ),
.hps_0_hps_io_hps_io_usb1_inst_D3 ( HPS_USB_DATA[3] ),
.hps_0_hps_io_hps_io_usb1_inst_D4 ( HPS_USB_DATA[4] ),
.hps_0_hps_io_hps_io_usb1_inst_D5 ( HPS_USB_DATA[5] ),
.hps_0_hps_io_hps_io_usb1_inst_D6 ( HPS_USB_DATA[6] ),
.hps_0_hps_io_hps_io_usb1_inst_D7 ( HPS_USB_DATA[7] ),
.hps_0_hps_io_hps_io_usb1_inst_CLK ( HPS_USB_CLKOUT ),
.hps_0_hps_io_hps_io_usb1_inst_STP ( HPS_USB_STP ),
.hps_0_hps_io_hps_io_usb1_inst_DIR ( HPS_USB_DIR ),
.hps_0_hps_io_hps_io_usb1_inst_NXT ( HPS_USB_NXT ),
//HPS SPI
.hps_0_hps_io_hps_io_spim1_inst_CLK ( HPS_SPIM_CLK ),
.hps_0_hps_io_hps_io_spim1_inst_MOSI ( HPS_SPIM_MOSI ),
.hps_0_hps_io_hps_io_spim1_inst_MISO ( HPS_SPIM_MISO ),
.hps_0_hps_io_hps_io_spim1_inst_SS0 ( HPS_SPIM_SS ),
//HPS UART
.hps_0_hps_io_hps_io_uart0_inst_RX ( HPS_UART_RX ),
.hps_0_hps_io_hps_io_uart0_inst_TX ( HPS_UART_TX ),
//HPS I2C1
.hps_0_hps_io_hps_io_i2c0_inst_SDA ( HPS_I2C1_SDAT ),
.hps_0_hps_io_hps_io_i2c0_inst_SCL ( HPS_I2C1_SCLK ),
//HPS I2C2
.hps_0_hps_io_hps_io_i2c1_inst_SDA ( HPS_I2C2_SDAT ),
.hps_0_hps_io_hps_io_i2c1_inst_SCL ( HPS_I2C2_SCLK ),
//HPS GPIO
.hps_0_hps_io_hps_io_gpio_inst_GPIO09 ( HPS_CONV_USB_N ),
.hps_0_hps_io_hps_io_gpio_inst_GPIO35 ( HPS_ENET_INT_N ),
.hps_0_hps_io_hps_io_gpio_inst_GPIO40 ( HPS_LTC_GPIO ),
//.hps_0_hps_io_hps_io_gpio_inst_GPIO41 ( HPS_GPIO[1]),
.hps_0_hps_io_hps_io_gpio_inst_GPIO48 ( HPS_I2C_CONTROL ),
.hps_0_hps_io_hps_io_gpio_inst_GPIO53 ( HPS_LED ),
.hps_0_hps_io_hps_io_gpio_inst_GPIO54 ( HPS_KEY ),
.hps_0_hps_io_hps_io_gpio_inst_GPIO61 ( HPS_GSENSOR_INT ),
//FPGA soft GPIO
.led_pio_external_connection_export ( ),
.dipsw_pio_external_connection_export ( SW ),
.button_pio_external_connection_export ( KEY )
);
camera_capture u3(
.out_data (ccd_data_captured), // component output data
.out_valid (ccd_dval), // data valid signal
.out_count_x (X_Cont_raw),
.out_count_y (Y_Cont_raw),
.oFrame_Cont (Frame_Cont), // Frames counter
.in_data (ccd_data_raw), // 12-bit data
.in_frame_valid (ccd_fval_raw), // Frame valid signal
.in_line_valid (ccd_lval_raw), // Line valid signal
.in_start (SW[9]),
.clock (ccd_pixel_clk),
// Negative logic reset
.reset_n (hps2fpga_reset_n & video_stream_reset_n),
.in_width (in_width[11:0]),
.in_height (in_height[11:0])
);
wire [15:0] in_width;
wire [15:0] in_height;
wire [11:0] X_Cont_raw;
wire [11:0] Y_Cont_raw;
// assign in_width = 11'd1280;
// assign in_height = 11'd960;
assign X_Cont = {4'd0, X_Cont_raw};
assign Y_Cont = {4'd0, Y_Cont_raw};
// CCD_Capture external pinout conections.
assign CCD_DATA[0] = GPIO_1[13]; //Pixel data Bit 0
assign CCD_DATA[1] = GPIO_1[12]; //Pixel data Bit 1
assign CCD_DATA[2] = GPIO_1[11]; //Pixel data Bit 2
assign CCD_DATA[3] = GPIO_1[10]; //Pixel data Bit 3
assign CCD_DATA[4] = GPIO_1[9]; //Pixel data Bit 4
assign CCD_DATA[5] = GPIO_1[8]; //Pixel data Bit 5
assign CCD_DATA[6] = GPIO_1[7]; //Pixel data Bit 6
assign CCD_DATA[7] = GPIO_1[6]; //Pixel data Bit 7
assign CCD_DATA[8] = GPIO_1[5]; //Pixel data Bit 8
assign CCD_DATA[9] = GPIO_1[4]; //Pixel data Bit 9
assign CCD_DATA[10] = GPIO_1[3]; //Pixel data Bit 10
assign CCD_DATA[11] = GPIO_1[1]; //Pixel data Bit 11
assign GPIO_1[16] = clk_24; //External input clock
assign CCD_FVAL = GPIO_1[22]; //frame valid
assign CCD_LVAL = GPIO_1[21]; //line valid
assign ccd_pixel_clk= GPIO_1[0]; //Pixel clock
assign GPIO_1[19] = 1'b1; //trigger
assign GPIO_1[17] = hps2fpga_reset_n & video_stream_reset_n;
assign GPIO_0[0] = hps2fpga_reset_n & video_stream_reset_n;
assign GPIO_0[1] = ccd_pixel_clk;
// Refreshes the data on the CCD camera on every pixel clock pulse.
always@(posedge ccd_pixel_clk)
begin
ccd_data_raw <= CCD_DATA;
ccd_lval_raw <= CCD_LVAL;
ccd_fval_raw <= CCD_FVAL;
end
/* This component converts 'raw' data obtained in the CCD to RGB data.
The output width and height are half of the input ones, as, each pixel consists
in 4 components(RGBG): The number of rows and columns are reduced to the half.
One from every 2 rows are stored on a buffer for getting the components of the
corresponding pixel afterwards.
*/
raw2rgb u4(
.iCLK (ccd_pixel_clk),
// Negative logic reset
.iRST (hps2fpga_reset_n & video_stream_reset_n),
.iDATA (ccd_data_captured), // Component input data
.iDVAL (ccd_dval), // Data valid signal
.oRed (raw_rgb_red), // Output red component
.oGreen (raw_rgb_green), // Output green component
.oBlue (raw_rgb_blue), // Output blue component
.oDVAL (raw_rgb_dval), // Pixel value available
.iX_Cont (X_Cont),
.iY_Cont (Y_Cont)
);
// On each camera cycle (defined by the pixel clock), the 3 components (RGB)
// of a pixel are written to 2 FIFOs on the SDRAM memory. As the VGA controller
// can take only 1 byte per component, only the 8 most significative bits of
// each 'raw' component are sent to the 2 FIFOs created in the SDRAM.
// In case that only one FIFO memory is used, only the 5 most significative
// bits of each component are sent to the SDRAM.
always @(posedge ccd_pixel_clk) begin
if (!hps2fpga_reset_n & video_stream_reset_n) begin
// if reset, do nothing.
end
else begin
if (SW[3]) begin
fifo1_writedata <= {1'b0, raw_rgb_red[11:7], raw_rgb_green[11:7],
raw_rgb_blue[11:7]};
fifo_write_enable <= raw_rgb_dval;
end
else begin
fifo1_writedata <= {8'h00, hue_hue[7:0]};
fifo_write_enable <= out_hue_valid;
end
end
end
rgb2hue hue(
.clock(ccd_pixel_clk),
.reset_n(hps2fpga_reset_n & video_stream_reset_n),
// Data input
.in_red(raw_rgb_red[11:4]),
.in_green(raw_rgb_green[11:4]),
.in_blue(raw_rgb_blue[11:4]),
.in_valid(raw_rgb_dval),
.in_visual(1'b1),
.in_done(1'b1),
// Data output
.out_red(hue_red),
.out_green(hue_green),
.out_blue(hue_blue),
.out_hue(hue_hue),
.out_valid(out_hue_valid),
.out_visual(),
.out_done()
);
wire [7:0] hue_hue;
wire [7:0] hue_red;
wire [7:0] hue_green;
wire [7:0] hue_blue;
wire out_hue_valid;
// image_capture: save RGB and Hue into HPS memory
image_capture imgcap1 (
// Clock and reset
.clk ( ccd_pixel_clk ),
.reset_n (hps2fpga_reset_n & video_stream_reset_n),
// Signals from the video stream
.R( hue_red ),
.G( hue_green ),
.B( hue_blue ),
.Gray( hue_hue ),
.frame_valid( ccd_fval_raw ),
.data_valid( out_hue_valid ),
// Signals to control this component.
.start_capture( start_capture ),
.image_size( capture_imgsize ),
.buff( capture_buff ),
.image_captured( image_captured ),
.standby ( capture_standby ),
// Avalon MM Master port to save data into a memory.
.address ( image_capture_address ),
.write ( image_capture_write ),
.byteenable ( image_capture_byteenable ),
.writedata ( image_capture_write_data ),
.waitrequest ( image_capture_waitrequest ),
.burstcount ( image_capture_burstcount )
);
// image_capture control signals
wire start_capture; // Start a new image capture
wire [23:0] capture_imgsize; //size of the image (in dots or RGB pixels)
wire [31:0] capture_buff; // Address of the buffer to save the image
wire image_captured; // image has been completely capture
wire capture_standby; // image_capture component is in standby state
// Avalon signals to write the pixels into memory
wire [31:0]image_capture_address;
wire image_capture_write;
wire [15:0]image_capture_byteenable;
wire [127:0]image_capture_write_data;
wire image_capture_waitrequest;
wire [6:0] image_capture_burstcount;
// SDRAM memory based on DE1-SOC demonstration
Sdram_Control u1(
// HOST Side
.REF_CLK(CLOCK_50),
.RESET_N(1'b1),
// FIFO Write Side 1
.WR1_DATA(fifo1_writedata), //data bus size: 16 bits
.WR1(fifo_write_enable),
.WR1_ADDR(0),
.WR1_MAX_ADDR(640*480), //address bus size: 25 bits
.WR1_LENGTH(9'h80), //Max allowed size: 8 bits
.WR1_LOAD(!(hps2fpga_reset_n & video_stream_reset_n)),
.WR1_CLK(~ccd_pixel_clk),
// FIFO Write Side 2 (Unused. Needed if 8 bits per pixel are used)
.WR2_DATA(fifo1_writedata), //data bus size: 16 bits
.WR2(fifo_write_enable),
.WR2_ADDR(22'h100000),
.WR2_MAX_ADDR(22'h100000+640*480), //address bus size: 25 bits
.WR2_LENGTH(9'h80), //Max allowed size: 8 bits
.WR2_LOAD(!(hps2fpga_reset_n & video_stream_reset_n)),
.WR2_CLK(~ccd_pixel_clk),
// FIFO Read Side 1
.RD1_DATA(fifo1_readdata), //data bus size: 16 bits
.RD1(vga_enable), //Read enable
.RD1_ADDR(0),
.RD1_MAX_ADDR(640*480), //address bus size: 25 bits
.RD1_LENGTH(9'h80), //Max allowed size: 8 bits
.RD1_LOAD(!(hps2fpga_reset_n & video_stream_reset_n)),
.RD1_CLK(~clk_25),
// FIFO Read Side 2 (Unused. Needed if 8 bits per pixel are used)
.RD2_DATA(fifo2_readdata), //data bus size: 16 bits
.RD2(vga_enable), //Read enable
.RD2_ADDR(22'h100000),
.RD2_MAX_ADDR(22'h100000+640*480), //address bus size: 25 bits
.RD2_LENGTH(9'h80), //Max allowed size: 8 bits
.RD2_LOAD(!(hps2fpga_reset_n & video_stream_reset_n)),
.RD2_CLK(~clk_25),
// SDRAM Side
.SA(DRAM_ADDR),
.BA(DRAM_BA),
.CS_N(DRAM_CS_N),
.CKE(DRAM_CKE),
.RAS_N(DRAM_RAS_N),
.CAS_N(DRAM_CAS_N),
.WE_N(DRAM_WE_N),
.DQ(DRAM_DQ),
.DQM({DRAM_UDQM,DRAM_LDQM}),
.SDR_CLK(DRAM_CLK)
);
reg fifo_write_enable;
// VGA controller component.
vga_controller vga_component(
.pixel_clk ( clk_25 ),
.reset_n ( hps2fpga_reset_n & video_stream_reset_n ),
.h_sync ( VGA_HS ),
.v_sync ( VGA_VS ),
.disp_ena ( vga_enable ),
.column (),
.row (),
.n_blank ( VGA_BLANK_N ),
.n_sync ( VGA_SYNC_N ),
.data_req ( vga_request )
);
// Send the data on the FIFO memory to the VGA outputs.
assign VGA_R = (!vga_enable) ? 0 :
(!SW[3]) ? fifo1_readdata[7:0] :
(SW[0]) ? {fifo1_readdata[14:10], 3'd0} :
0;
assign VGA_G = (!vga_enable) ? 0 :
(!SW[3]) ? fifo1_readdata[7:0] :
(SW[1]) ? {fifo1_readdata[9:5], 3'd0} :
0;
assign VGA_B = (!vga_enable) ? 0 :
(!SW[3]) ? fifo1_readdata[7:0] :
(SW[2]) ? {fifo1_readdata[4:0], 3'd0} :
0;
// Set the VGA clock to 25 MHz.
assign VGA_CLK = clk_25;
/*
Instantiation of the 7-segment displays module.
Depending on the status of the 8th switch (SW[8]), it will display the
exposure value (if SW[8] = 1) or the frame rate (if SW[8] = 0).
For getting the frame rate, a 1 second temporizer is created, and the
number of frames between pulses is displayed. Moreover, a seconds pulse
is wired to the first led of the board (LEDR[0])
*/
SEG7_LUT_8 u5(
.oSEG0 (HEX0),
.oSEG1 (HEX1),
.oSEG2 (HEX2),
.oSEG3 (HEX3),
.oSEG4 (HEX4),
.oSEG5 (HEX5),
.oSEG6 (),
.oSEG7 (),
.iDIG (display)
);
wire [31:0] display;
reg [31:0] count;
reg [31:0] rate;
reg [31:0] _Frame_Cont;
reg seconds_pulse;
reg pulse;
assign LEDR[0] = pulse;
assign display = (SW[8]) ? {16'h0, in_exposure} : rate;
// Calculate the frame rate.
// Seconds counter. The output will be 1 during one pulse after 1 second.
always @(posedge CLOCK_50) begin
if (count < 50000000) begin
count = count + 1;
// seconds_pulse = 0;
end
else begin
count = 0;
// seconds_pulse = 1;
pulse = ~pulse;
rate = Frame_Cont - _Frame_Cont;
_Frame_Cont = Frame_Cont;
end
end
// Component for writing configuration to the camera peripheral.
camera_config #(
.CLK_FREQ(25000000), // 25 MHz
.I2C_FREQ(20000) // 20 kHz
) camera_conf(
// Host Side
.clock(ccd_pixel_clk),
.reset_n(hps2fpga_reset_n & video_stream_reset_n),
// Configuration registers
.exposure(in_exposure),
.start_row(in_start_row),
.start_column(in_start_column),
.row_size(in_row_size),
.column_size(in_column_size),
.row_mode(in_row_mode),
.column_mode(in_column_mode),
// Ready signal
.out_ready(ready),
// I2C Side
.I2C_SCLK(GPIO_1[24]),
.I2C_SDAT(GPIO_1[23])
);
// Camera config (I2C)
wire ready;
wire [15:0] in_exposure;
wire [15:0] start_row;
wire [15:0] start_column;
wire [15:0] in_row_size;
wire [15:0] in_column_size;
wire [15:0] in_row_mode;
wire [15:0] in_column_mode;
// assign in_exposure = 16'h07C0;
// assign start_row = 16'h0000;
// assign start_column = 16'h0000;
// assign in_row_size = 16'h077F;
// assign in_column_size = 16'h09FF;
// assign in_row_mode = 16'h0011;
// assign in_column_mode = 16'h0011;
// Reset logic
assign video_stream_reset_n = (camera_soft_reset_n & KEY[0]);
endmodule
|
`timescale 500ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10/05/2015 11:27:42 AM
// Design Name:
// Module Name: PWM_FPGA
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PWM_FPGA(
input wire clk100MHz,
input wire rst,
input wire [1:0] ctrl,
input wire [2:0] sweep_speed,
input wire [9:0] pin_pos,
input wire sclk,
input wire serial,
input wire flush,
output wire [2:0] spi,
output wire [PWMS-1:0] pwm,
output wire clk1MHz,
output wire clk200Hz,
output wire clk5KHz,
output wire [7:0] LEDOUT,
output wire [7:0] LEDSEL
);
parameter RC_SIGNAL_WIDTH = 11;
parameter PIN_POS_WIDTH = 10;
parameter BCD_WIDTH = 4;
parameter POSITION_FILE_WIDTH = 32;
parameter POSITION_WIDTH = 11;
parameter PWMS = 17;
parameter CHANNEL_WIDTH = 5;
assign spi = { sclk, flush, serial };
wire [RC_SIGNAL_WIDTH-1:0] sweep_pos;
wire [RC_SIGNAL_WIDTH-1:0] out_pos;
wire [RC_SIGNAL_WIDTH-1:0] ser_pos;
wire [CHANNEL_WIDTH-1:0] ser_channel;
wire [15:0] pos [0:RC_SIGNAL_WIDTH-1];
wire [BCD_WIDTH-1:0] ones;
wire [BCD_WIDTH-1:0] tens;
wire [BCD_WIDTH-1:0] hundreds;
wire [BCD_WIDTH-1:0] thousands;
wire [BCD_WIDTH-1:0] channel_ones;
wire [BCD_WIDTH-1:0] channel_tens;
wire [BCD_WIDTH-1:0] channel_hundreds;
wire [BCD_WIDTH-1:0] channel_thousands;
supply1 [7:0] vcc;
wire [7:0] d5;
wire [7:0] d4;
wire [7:0] d3;
wire [7:0] d2;
wire [7:0] d1;
wire [7:0] d0;
assign d5[7] = 1'b1;
assign d4[7] = 1'b1;
assign d3[7] = 1'b1;
assign d2[7] = 1'b1;
assign d1[7] = 1'b1;
assign d0[7] = 1'b1;
clk_gen U0 (.clk100MHz(clk100MHz),
.rst(rst),
.clk1MHz(clk1MHz),
.clk200Hz(clk200Hz),
.clk5KHz(clk5KHz)
);
SerialHandler SerH0 (
.clk100MHz(clk100MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.ser_pos(ser_pos),
.ser_channel(ser_channel),
.channel(5'h00)
);
SerialHandler SerH1 (
.clk100MHz(clk100MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.ser_pos(pos[1]),
.channel(5'h01)
);
AngleToPWM ATP1 (
.pos(pos[1]),
.clk1MHz(clk1MHz),
.rst(rst),
.pwm(pwm[1])
);
SerialHandler SerH2 (
.clk100MHz(clk100MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.ser_pos(pos[2]),
.channel(5'h02)
);
AngleToPWM ATP2 (
.pos(pos[2]),
.clk1MHz(clk1MHz),
.rst(rst),
.pwm(pwm[2])
);
SerialHandler SerH3 (
.clk100MHz(clk100MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.ser_pos(pos[3]),
.channel(5'h03)
);
AngleToPWM ATP3 (
.pos(pos[3]),
.clk1MHz(clk1MHz),
.rst(rst),
.pwm(pwm[3])
);
SerialHandler SerH4 (
.clk100MHz(clk100MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.ser_pos(pos[4]),
.channel(5'h04)
);
AngleToPWM ATP4 (
.pos(pos[4]),
.clk1MHz(clk1MHz),
.rst(rst),
.pwm(pwm[4])
);
SerialHandler SerH5 (
.clk100MHz(clk100MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.ser_pos(pos[5]),
.channel(5'h05)
);
AngleToPWM ATP5 (
.pos(pos[5]),
.clk1MHz(clk1MHz),
.rst(rst),
.pwm(pwm[5])
);
SerialHandler SerH6 (
.clk100MHz(clk100MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.ser_pos(pos[6]),
.channel(5'h06)
);
AngleToPWM ATP6 (
.pos(pos[6]),
.clk1MHz(clk1MHz),
.rst(rst),
.pwm(pwm[6])
);
SerialHandler SerH7 (
.clk100MHz(clk100MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.ser_pos(pos[7]),
.channel(5'h07)
);
AngleToPWM ATP7 (
.pos(pos[7]),
.clk1MHz(clk1MHz),
.rst(rst),
.pwm(pwm[7])
);
SerialHandler SerH8 (
.clk100MHz(clk100MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.ser_pos(pos[8]),
.channel(5'h08)
);
AngleToPWM ATP8 (
.pos(pos[8]),
.clk1MHz(clk1MHz),
.rst(rst),
.pwm(pwm[8])
);
SerialHandler SerH9 (
.clk100MHz(clk100MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.ser_pos(pos[9]),
.channel(5'h09)
);
AngleToPWM ATP9 (
.pos(pos[9]),
.clk1MHz(clk1MHz),
.rst(rst),
.pwm(pwm[9])
);
SerialHandler SerH10 (
.clk100MHz(clk100MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.ser_pos(pos[10]),
.channel(5'h10)
);
AngleToPWM ATP10 (
.pos(pos[10]),
.clk1MHz(clk1MHz),
.rst(rst),
.pwm(pwm[10])
);
SerialHandler SerH11 (
.clk100MHz(clk100MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.ser_pos(pos[12]),
.channel(5'h11)
);
AngleToPWM ATP11 (
.pos(pos[11]),
.clk1MHz(clk1MHz),
.rst(rst),
.pwm(pwm[11])
);
SerialHandler SerH12 (
.clk100MHz(clk100MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.ser_pos(pos[12]),
.channel(5'h12)
);
AngleToPWM ATP12 (
.pos(pos[12]),
.clk1MHz(clk1MHz),
.rst(rst),
.pwm(pwm[12])
);
SerialHandler SerH13 (
.clk100MHz(clk100MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.ser_pos(pos[13]),
.channel(5'h13)
);
AngleToPWM ATP13 (
.pos(pos[13]),
.clk1MHz(clk1MHz),
.rst(rst),
.pwm(pwm[13])
);
SerialHandler SerH14 (
.clk100MHz(clk100MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.ser_pos(pos[14]),
.channel(5'h14)
);
AngleToPWM ATP14 (
.pos(pos[14]),
.clk1MHz(clk1MHz),
.rst(rst),
.pwm(pwm[14])
);
SerialHandler SerH15 (
.clk100MHz(clk100MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.ser_pos(pos[15]),
.channel(5'h15)
);
AngleToPWM ATP15 (
.pos(pos[15]),
.clk1MHz(clk1MHz),
.rst(rst),
.pwm(pwm[15])
);
/********** Serial Servo **********/
/******** Sweep ********/
SweepPosition U1(
.clk200Hz(clk200Hz),
.rst(rst),
.speed(sweep_speed),
.pos(sweep_pos)
);
PositionMux U2(
.ctrl(ctrl),
.sweep_pos(sweep_pos),
.pin_pos(pin_pos),
.ser_pos(ser_pos),
.out_pos(out_pos)
);
AngleToPWM ATP0 (
.pos(out_pos),
.clk1MHz(clk1MHz),
.rst(rst),
.pwm(pwm[0])
);
bin_to_bcd U4 (
.bin(out_pos),
.ones(ones),
.tens(tens),
.hundreds(hundreds),
.thousands(thousands)
);
bin_to_bcd binbcd_channel (
.bin(ser_channel),
.ones(channel_ones),
.tens(channel_tens),
.hundreds(channel_hundreds),
.thousands(channel_thousands)
);
bcd_to_7seg U5 (ones, d0[6:0]);
bcd_to_7seg U6 (tens, d1[6:0]);
bcd_to_7seg U7 (hundreds, d2[6:0]);
bcd_to_7seg U8 (thousands, d3[6:0]);
bcd_to_7seg bcd7seg_channel0 (channel_ones, d4[6:0]);
bcd_to_7seg bcd7seg_channel1 (channel_tens, d5[6:0]);
led_mux U9 (.clk(clk5KHz),
.rst(rst),
.LED0({ d5[7], d5[6], d5[5], d5[4], d5[3], d5[2], d5[1], d5[0] }),
.LED1({ d4[7], d4[6], d4[5], d4[4], d4[3], d4[2], d4[1], d4[0] }),
.LED2(vcc),
.LED3(vcc),
.LED4({ d3[7], d3[6], d3[5], d3[4], d3[3], d3[2], d3[1], d3[0] }),
.LED5({ d2[7], d2[6], d2[5], d2[4], d2[3], d2[2], d2[1], d2[0] }),
.LED6({ d1[7], d1[6], d1[5], d1[4], d1[3], d1[2], d1[1], d1[0] }),
.LED7({ d0[7], d0[6], d0[5], d0[4], d0[3], d0[2], d0[1], d0[0] }),
.LEDSEL(LEDOUT),
.LEDOUT(LEDSEL)
);
endmodule
/*
SerialServo Servo1 (
.clk100MHz(clk100MHz),
.clk1MHz(clk1MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.channel(5'h01),
.pwm(pwm[1])
);
SerialServo Servo2 (
.clk100MHz(clk100MHz),
.clk1MHz(clk1MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.channel(5'h01),
.pwm(pwm[2])
);
SerialServo Servo3 (
.clk100MHz(clk100MHz),
.clk1MHz(clk1MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.channel(5'h02),
.pwm(pwm[3])
);
SerialServo Servo4 (
.clk100MHz(clk100MHz),
.clk1MHz(clk1MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.channel(5'h03),
.pwm(pwm[4])
);
SerialServo Servo5 (
.clk100MHz(clk100MHz),
.clk1MHz(clk1MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.channel(5'h04),
.pwm(pwm[5])
);
SerialServo Servo6 (
.clk100MHz(clk100MHz),
.clk1MHz(clk1MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.channel(5'h05),
.pwm(pwm[6])
);
SerialServo Servo7 (
.clk100MHz(clk100MHz),
.clk1MHz(clk1MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.channel(5'h06),
.pwm(pwm[7])
);
SerialServo Servo8 (
.clk100MHz(clk100MHz),
.clk1MHz(clk1MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.channel(5'h07),
.pwm(pwm[8])
);
SerialServo Servo9 (
.clk100MHz(clk100MHz),
.clk1MHz(clk1MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.channel(5'h08),
.pwm(pwm[9])
);
SerialServo Servo10 (
.clk100MHz(clk100MHz),
.clk1MHz(clk1MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.channel(5'h09),
.pwm(pwm[10])
);
SerialServo Servo11 (
.clk100MHz(clk100MHz),
.clk1MHz(clk1MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.channel(5'h0A),
.pwm(pwm[11])
);
SerialServo Servo12 (
.clk100MHz(clk100MHz),
.clk1MHz(clk1MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.channel(5'h0B),
.pwm(pwm[12])
);
SerialServo Servo13 (
.clk100MHz(clk100MHz),
.clk1MHz(clk1MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.channel(5'h0C),
.pwm(pwm[13])
);
SerialServo Servo14 (
.clk100MHz(clk100MHz),
.clk1MHz(clk1MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.channel(5'h0D),
.pwm(pwm[14])
);
SerialServo Servo15 (
.clk100MHz(clk100MHz),
.clk1MHz(clk1MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.channel(5'h0E),
.pwm(pwm[15])
);
SerialServo Servo16 (
.clk100MHz(clk100MHz),
.clk1MHz(clk1MHz),
.rst(rst),
.ext_clk(sclk),
.ext_flush(flush),
.serial(serial),
.channel(5'h0F),
.pwm(pwm[16])
);
*/ |
///////////////////////////////////////////////////////////////
// sha1_round.v version 0.1
//
// Primitive SHA1 Round
//
// Described in Stalling, page 284
//
// Paul Hartke, [email protected], Copyright (c)2002
//
// The information and description contained herein is the
// property of Paul Hartke.
//
// Permission is granted for any reuse of this information
// and description as long as this copyright notice is
// preserved. Modifications may be made as long as this
// notice is preserved.
// This code is made available "as is". There is no warranty,
// so use it at your own risk.
// Documentation? "Use the source, Luke!"
///////////////////////////////////////////////////////////////
module sha1_round (cv_in, w, round, cv_out);
input [159:0] cv_in;
input [31:0] w;
input [6:0] round;
output [159:0] cv_out;
reg [31:0] k;
reg [31:0] f;
wire [31:0] a_shift;
wire [31:0] b_shift;
wire [31:0] add_result;
wire [31:0] a = cv_in[159:128];
wire [31:0] b = cv_in[127:96];
wire [31:0] c = cv_in[95:64];
wire [31:0] d = cv_in[63:32];
wire [31:0] e = cv_in[31:0];
// Perhaps this should be a case statement?
// I want it to create 4 parallel comparators...
always @(round)
begin
k = 32'd0;
if ((round >= 7'd0) && (round <= 7'd19))
k = 32'h5A827999;
if ((round >= 7'd20) && (round <= 7'd39))
k = 32'h6ED9EBA1;
if ((round >= 7'd40) && (round <= 7'd59))
k = 32'h8F1BBCDC;
if ((round >= 7'd60) && (round <= 7'd79))
k = 32'hCA62C1D6;
end // always @ (round)
// Perhaps this should be a case statement?
// I want it to create 4 parallel comparators...
always @(round or b or c or d)
begin
f = 32'd0;
if ((round >= 7'd0) && (round <= 7'd19))
f = ((b & c) | (~b & d));
if ((round >= 7'd20) && (round <= 7'd39))
f = (b ^ c ^ d);
if ((round >= 7'd40) && (round <= 7'd59))
f = ((b & c) | (b & d) | (c & d));
if ((round >= 7'd60) && (round <= 7'd79))
f = (b ^ c ^ d);
end // always @ (round or b or c or d)
assign a_shift = {a[26:0], a[31:27]};
assign b_shift = {b[1:0], b[31:2]};
// Attempt to group early signals early...
// e and w come from register outputs
// k is 6 bit comparator & mux delay
// f is 6 bit comparator & mux delay & computation
// a is shift 5 from previous round
assign add_result = (a_shift + ((f + k) + (e + w)));
assign cv_out = {add_result, a, b_shift, c, d};
endmodule // sha1_round
|
//-----------------------------------------------------------------------------
// File : wb_slave_spi_master.v
// Creation date : 18.04.2017
// Creation time : 13:45:46
// Description : Template component for wishbone slave. Address space is assumed to be contiguous.
// Created by : TermosPullo
// Tool : Kactus2 3.4.79 32-bit
// Plugin : Verilog generator 2.0d
// This file was generated based on IP-XACT component tut.fi:communication:wb_slave_spi_master:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/communication/wb_slave_spi_master/1.0/wb_slave_spi_master.1.0.xml
//-----------------------------------------------------------------------------
module wb_slave_spi_master #(
parameter BUFFER_SIZE = 16, // How many bytes is allocated for a buffer.
parameter ADDR_WIDTH = 16, // The width of the address.
parameter DATA_WIDTH = 32, // The width of the both transferred and inputted data.
parameter BASE_ADDRESS = 'h0F00, // The first referred address of the master.
parameter BUFFER_INDEX_WIDTH = $clog2(BUFFER_SIZE), // How many bits are needed to index the buffer.
parameter CONTROL_SIZE = 1, // How many bytes asre reserved for the control data.
parameter STATUS_SIZE = 1 // How many bytes asre reserved for the status data.
) (
// Interface: master_if
input data_in,
output clk_out,
output reg data_out,
output reg slave_select_out,
// Interface: wb_slave
input [ADDR_WIDTH-1:0] adr_i, // The address of the data.
input cyc_i, // Asserted by master for transfer.
input [DATA_WIDTH-1:0] dat_i, // Data from master to slave.
input stb_i, // Asserted, when this specific slave is selected.
input we_i, // Write = 1, Read = 0.
output reg ack_o, // Slave asserts acknowledge.
output reg [DATA_WIDTH-1:0] dat_o, // Data from slave to master.
output reg err_o, // Indicates abnormal cycle termination.
// Interface: wb_system
input clk_i, // The mandatory clock, as this is synchronous logic.
input rst_i // The mandatory reset, as this is synchronous logic.
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
localparam BYTE_SIZE = 8; // How many bits are transferred per transaction
localparam BYTE_INDEX_SIZE = $clog2(BYTE_SIZE); // How many bits are needed to index a byte.
localparam BUFFER_INDEX_SIZE = $clog2(BUFFER_SIZE); // How many bits are needed to index a buffer.
// Input and output bytes.
reg [BYTE_SIZE-1:0] buffer_recv [STATUS_SIZE+BUFFER_SIZE-1:0];
reg [BYTE_SIZE-1:0] buffer_send [CONTROL_SIZE+BUFFER_SIZE-1:0];
// The state.
reg [0:0] wb_state;
// The available states.
parameter [0:0]
S_WB_WAIT = 1'd0, // Waiting for cyc_i & stb_i
S_WB_DEASSERT = 1'd1; // Deassert acknowledgement.
// The address is ok = 1, else not ok.
integer addr_ok;
wire start_transfer = buffer_send[BUFFER_SIZE][0];
reg transfer_complete;
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
ack_o <= 0; // Obviously, there is nothing to acknowledge by default.
dat_o <= 0; // No output by default.
err_o <= 0; // No error by default.
wb_state <= S_WB_WAIT; // Wait signals from the masters at reset.
buffer_send[BUFFER_SIZE] = 0;
end
else begin
buffer_recv[BUFFER_SIZE][BYTE_SIZE-1:0] = {7'b0000000,transfer_complete};
if (wb_state == S_WB_WAIT) begin
if (we_i == 1) begin
if (adr_i < BASE_ADDRESS + BUFFER_SIZE*2 + CONTROL_SIZE + STATUS_SIZE && adr_i >= BASE_ADDRESS + BUFFER_SIZE + STATUS_SIZE) begin
addr_ok = 1;
end
else begin
addr_ok = 0;
end
end
else begin
if (adr_i < BASE_ADDRESS + BUFFER_SIZE + STATUS_SIZE && adr_i >= BASE_ADDRESS) begin
addr_ok = 1;
end
else begin
addr_ok = 0;
end
end
// Wait signal from the master.
if ( cyc_i == 1 && stb_i == 1 ) begin
if (addr_ok) begin
// The specified address in accessible -> proceed.
ack_o <= 1;
if ( we_i == 1 ) begin
buffer_send[adr_i - BASE_ADDRESS - BUFFER_SIZE - STATUS_SIZE] <= dat_i[BYTE_SIZE-1:0];
end
else begin
dat_o[DATA_WIDTH-1:0] <= {{DATA_WIDTH-BYTE_SIZE{1'b0}},buffer_recv[adr_i - BASE_ADDRESS]};
end
end
else begin
// The specified address out-of-scope -> error!
err_o <= 1;
end
// Next thing is to deassert.
wb_state <= S_WB_DEASSERT;
end
end
else if (wb_state == S_WB_DEASSERT) begin
// Deassert acknowlegement, get ready to receive next one.
ack_o <= 0;
err_o <= 0;
wb_state <= S_WB_WAIT;
// Must deassert transfer start as well.
buffer_send[BUFFER_SIZE][0] <= 0;
end
else
$display("ERROR: Unkown wb_state: %d", wb_state);
end
end
// Used to iterate through the buffers.
reg [BUFFER_INDEX_SIZE-1:0] buffer_index;
// Used to iterate through the bytes.
reg [BYTE_INDEX_SIZE-1:0] send_iterator;
reg [BYTE_INDEX_SIZE-1:0] recv_iterator;
reg [BYTE_SIZE-2:0] data_recv;
reg [BYTE_SIZE-1:0] data_send;
// The state.
reg [1:0] spi_state;
// The available states.
parameter [1:0]
S_SPI_WAIT = 2'd0,
S_SPI_INIT_NEXT = 2'd1,
S_SPI_TRANSFER = 2'd2,
S_SPI_DEASSERT = 2'd3;
assign clk_out = clk_i;
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
spi_state <= S_SPI_WAIT; // Wait signals from the masters at reset.
data_recv <= 0;
data_send <= 8'h55;
data_out <= 1'bz;
send_iterator <= 0;
recv_iterator <= 0;
buffer_index <= 0;
data_recv <= 0;
data_send <= 0;
// These are active low -> Initiallty high.
slave_select_out <= 1;
transfer_complete <= 1;
end
else begin
case(spi_state)
S_SPI_WAIT: begin
if (start_transfer && transfer_complete) begin
spi_state <= S_SPI_INIT_NEXT;
transfer_complete <= 0;
end
end
S_SPI_INIT_NEXT: begin
data_send <= buffer_send[buffer_index];
slave_select_out <= 0;
spi_state <= S_SPI_TRANSFER;
end
S_SPI_TRANSFER: begin
data_out <= data_send[send_iterator];
if (send_iterator > 0 && recv_iterator < BYTE_SIZE-1) begin
data_recv[recv_iterator] <= data_in;
recv_iterator = recv_iterator +1;
end
if (recv_iterator >= BYTE_SIZE-1) begin
spi_state <= S_SPI_DEASSERT;
end
else
send_iterator <= send_iterator + 1;
end
S_SPI_DEASSERT: begin
slave_select_out <= 1;
data_out <= 1'bz;
buffer_recv[buffer_index] <= {data_in,data_recv[6:0]};
send_iterator <= 0;
recv_iterator <= 0;
data_recv <= 0;
data_send <= 0;
if (buffer_index < BUFFER_SIZE-1) begin
buffer_index = buffer_index + 1;
spi_state <= S_SPI_INIT_NEXT;
end
else begin
spi_state <= S_SPI_WAIT;
transfer_complete <= 1;
buffer_index <= 0;
end
end
default: begin
$display("ERROR: Unkown spi_state: %d", spi_state);
end
endcase
end
end
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: syn_clk_gen.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module syn_clk_gen (
areset,
inclk0,
c0,
c1,
locked);
input areset;
input inclk0;
output c0;
output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire6 = 1'h0;
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 42,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 7,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 18518,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=syn_clk_gen",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "ON",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "42"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "7"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.285714"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "7.714286"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "54.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "syn_clk_gen.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "42"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "7"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "18518"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL syn_clk_gen.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL syn_clk_gen.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL syn_clk_gen.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL syn_clk_gen.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL syn_clk_gen.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL syn_clk_gen_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL syn_clk_gen_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FA_2_V
`define SKY130_FD_SC_HD__FA_2_V
/**
* fa: Full adder.
*
* Verilog wrapper for fa with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__fa.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__fa_2 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__fa_2 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__FA_2_V
|
module Computer_Datapath_RegisterFile(
output reg [WORD_WIDTH-1:0] ADDR_bus_out,
output reg [WORD_WIDTH-1:0] B_data_out,
input [CNTRL_WIDTH-1:0] CNTRL_bus_in,
input [WORD_WIDTH-1:0] D_bus_in,
input CLK,
input RST
);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SB_WIDTH = DR_WIDTH;
parameter SA_WIDTH = DR_WIDTH;
parameter OPCODE_WIDTH = 7;
parameter CNTRL_WIDTH = DR_WIDTH+SB_WIDTH+SA_WIDTH+11;
parameter COUNTER_WIDTH = 4;
wire RW = CNTRL_bus_in[4];
wire [SA_WIDTH-1:0] DA = CNTRL_bus_in[19:17];
wire [SA_WIDTH-1:0] AA = CNTRL_bus_in[16:14];
wire [SA_WIDTH-1:0] BA = CNTRL_bus_in[13:11];
reg [WORD_WIDTH-1:0] SYNC_RAM0 [2**DR_WIDTH-1:0];
reg [WORD_WIDTH-1:0] SYNC_RAM1 [2**DR_WIDTH-1:0];
reg [DR_WIDTH-1:0] i;
always@(posedge CLK) begin
/*
if (RST)
for (i=3'b0;i<2**DR_WIDTH-3'b1;i = i + 3'b1) begin
SYNC_RAM1[i] <= 0;
SYNC_RAM0[i] <= 0;
end
else if (RW) begin
*/
if(RW) begin
SYNC_RAM0[DA] <= D_bus_in;
SYNC_RAM1[DA] <= D_bus_in;
end
end
always@(*) begin
ADDR_bus_out <= SYNC_RAM0[AA];
B_data_out <= SYNC_RAM1[BA];
end
endmodule |
/*
Copyright (c) 2014-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench axis_mt19937_64
*/
module test_axis_mt19937_64;
// Parameters
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] seed_val = 0;
reg seed_start = 0;
reg output_axis_tready = 0;
// Outputs
wire [63:0] output_axis_tdata;
wire output_axis_tvalid;
wire busy;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
seed_val,
seed_start,
output_axis_tready
);
$to_myhdl(
output_axis_tdata,
output_axis_tvalid,
busy
);
// dump file
$dumpfile("test_axis_mt19937_64.lxt");
$dumpvars(0, test_axis_mt19937_64);
end
axis_mt19937_64
UUT (
.clk(clk),
.rst(rst),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
// Configuration
.seed_val(seed_val),
.seed_start(seed_start),
// Status
.busy(busy)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__SDFRTP_FUNCTIONAL_PP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTP_FUNCTIONAL_PP_V |
// soc_system_hps.v
// This file was auto-generated from altera_hps_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module soc_system_hps #(
parameter F2S_Width = 1,
parameter S2F_Width = 1
) (
output wire h2f_rst_n, // h2f_reset.reset_n
input wire f2h_axi_clk, // f2h_axi_clock.clk
input wire [7:0] f2h_AWID, // f2h_axi_slave.awid
input wire [31:0] f2h_AWADDR, // .awaddr
input wire [3:0] f2h_AWLEN, // .awlen
input wire [2:0] f2h_AWSIZE, // .awsize
input wire [1:0] f2h_AWBURST, // .awburst
input wire [1:0] f2h_AWLOCK, // .awlock
input wire [3:0] f2h_AWCACHE, // .awcache
input wire [2:0] f2h_AWPROT, // .awprot
input wire f2h_AWVALID, // .awvalid
output wire f2h_AWREADY, // .awready
input wire [4:0] f2h_AWUSER, // .awuser
input wire [7:0] f2h_WID, // .wid
input wire [31:0] f2h_WDATA, // .wdata
input wire [3:0] f2h_WSTRB, // .wstrb
input wire f2h_WLAST, // .wlast
input wire f2h_WVALID, // .wvalid
output wire f2h_WREADY, // .wready
output wire [7:0] f2h_BID, // .bid
output wire [1:0] f2h_BRESP, // .bresp
output wire f2h_BVALID, // .bvalid
input wire f2h_BREADY, // .bready
input wire [7:0] f2h_ARID, // .arid
input wire [31:0] f2h_ARADDR, // .araddr
input wire [3:0] f2h_ARLEN, // .arlen
input wire [2:0] f2h_ARSIZE, // .arsize
input wire [1:0] f2h_ARBURST, // .arburst
input wire [1:0] f2h_ARLOCK, // .arlock
input wire [3:0] f2h_ARCACHE, // .arcache
input wire [2:0] f2h_ARPROT, // .arprot
input wire f2h_ARVALID, // .arvalid
output wire f2h_ARREADY, // .arready
input wire [4:0] f2h_ARUSER, // .aruser
output wire [7:0] f2h_RID, // .rid
output wire [31:0] f2h_RDATA, // .rdata
output wire [1:0] f2h_RRESP, // .rresp
output wire f2h_RLAST, // .rlast
output wire f2h_RVALID, // .rvalid
input wire f2h_RREADY, // .rready
input wire h2f_axi_clk, // h2f_axi_clock.clk
output wire [11:0] h2f_AWID, // h2f_axi_master.awid
output wire [29:0] h2f_AWADDR, // .awaddr
output wire [3:0] h2f_AWLEN, // .awlen
output wire [2:0] h2f_AWSIZE, // .awsize
output wire [1:0] h2f_AWBURST, // .awburst
output wire [1:0] h2f_AWLOCK, // .awlock
output wire [3:0] h2f_AWCACHE, // .awcache
output wire [2:0] h2f_AWPROT, // .awprot
output wire h2f_AWVALID, // .awvalid
input wire h2f_AWREADY, // .awready
output wire [11:0] h2f_WID, // .wid
output wire [31:0] h2f_WDATA, // .wdata
output wire [3:0] h2f_WSTRB, // .wstrb
output wire h2f_WLAST, // .wlast
output wire h2f_WVALID, // .wvalid
input wire h2f_WREADY, // .wready
input wire [11:0] h2f_BID, // .bid
input wire [1:0] h2f_BRESP, // .bresp
input wire h2f_BVALID, // .bvalid
output wire h2f_BREADY, // .bready
output wire [11:0] h2f_ARID, // .arid
output wire [29:0] h2f_ARADDR, // .araddr
output wire [3:0] h2f_ARLEN, // .arlen
output wire [2:0] h2f_ARSIZE, // .arsize
output wire [1:0] h2f_ARBURST, // .arburst
output wire [1:0] h2f_ARLOCK, // .arlock
output wire [3:0] h2f_ARCACHE, // .arcache
output wire [2:0] h2f_ARPROT, // .arprot
output wire h2f_ARVALID, // .arvalid
input wire h2f_ARREADY, // .arready
input wire [11:0] h2f_RID, // .rid
input wire [31:0] h2f_RDATA, // .rdata
input wire [1:0] h2f_RRESP, // .rresp
input wire h2f_RLAST, // .rlast
input wire h2f_RVALID, // .rvalid
output wire h2f_RREADY, // .rready
input wire f2h_dma_req0_req, // f2h_dma_req0.dma_req
input wire f2h_dma_req0_single, // .dma_single
output wire f2h_dma_req0_ack, // .dma_ack
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_io_gpio_inst_GPIO61 // .hps_io_gpio_inst_GPIO61
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (F2S_Width != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
f2s_width_check ( .error(1'b1) );
end
if (S2F_Width != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
soc_system_hps_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.f2h_axi_clk (f2h_axi_clk), // f2h_axi_clock.clk
.f2h_AWID (f2h_AWID), // f2h_axi_slave.awid
.f2h_AWADDR (f2h_AWADDR), // .awaddr
.f2h_AWLEN (f2h_AWLEN), // .awlen
.f2h_AWSIZE (f2h_AWSIZE), // .awsize
.f2h_AWBURST (f2h_AWBURST), // .awburst
.f2h_AWLOCK (f2h_AWLOCK), // .awlock
.f2h_AWCACHE (f2h_AWCACHE), // .awcache
.f2h_AWPROT (f2h_AWPROT), // .awprot
.f2h_AWVALID (f2h_AWVALID), // .awvalid
.f2h_AWREADY (f2h_AWREADY), // .awready
.f2h_AWUSER (f2h_AWUSER), // .awuser
.f2h_WID (f2h_WID), // .wid
.f2h_WDATA (f2h_WDATA), // .wdata
.f2h_WSTRB (f2h_WSTRB), // .wstrb
.f2h_WLAST (f2h_WLAST), // .wlast
.f2h_WVALID (f2h_WVALID), // .wvalid
.f2h_WREADY (f2h_WREADY), // .wready
.f2h_BID (f2h_BID), // .bid
.f2h_BRESP (f2h_BRESP), // .bresp
.f2h_BVALID (f2h_BVALID), // .bvalid
.f2h_BREADY (f2h_BREADY), // .bready
.f2h_ARID (f2h_ARID), // .arid
.f2h_ARADDR (f2h_ARADDR), // .araddr
.f2h_ARLEN (f2h_ARLEN), // .arlen
.f2h_ARSIZE (f2h_ARSIZE), // .arsize
.f2h_ARBURST (f2h_ARBURST), // .arburst
.f2h_ARLOCK (f2h_ARLOCK), // .arlock
.f2h_ARCACHE (f2h_ARCACHE), // .arcache
.f2h_ARPROT (f2h_ARPROT), // .arprot
.f2h_ARVALID (f2h_ARVALID), // .arvalid
.f2h_ARREADY (f2h_ARREADY), // .arready
.f2h_ARUSER (f2h_ARUSER), // .aruser
.f2h_RID (f2h_RID), // .rid
.f2h_RDATA (f2h_RDATA), // .rdata
.f2h_RRESP (f2h_RRESP), // .rresp
.f2h_RLAST (f2h_RLAST), // .rlast
.f2h_RVALID (f2h_RVALID), // .rvalid
.f2h_RREADY (f2h_RREADY), // .rready
.h2f_axi_clk (h2f_axi_clk), // h2f_axi_clock.clk
.h2f_AWID (h2f_AWID), // h2f_axi_master.awid
.h2f_AWADDR (h2f_AWADDR), // .awaddr
.h2f_AWLEN (h2f_AWLEN), // .awlen
.h2f_AWSIZE (h2f_AWSIZE), // .awsize
.h2f_AWBURST (h2f_AWBURST), // .awburst
.h2f_AWLOCK (h2f_AWLOCK), // .awlock
.h2f_AWCACHE (h2f_AWCACHE), // .awcache
.h2f_AWPROT (h2f_AWPROT), // .awprot
.h2f_AWVALID (h2f_AWVALID), // .awvalid
.h2f_AWREADY (h2f_AWREADY), // .awready
.h2f_WID (h2f_WID), // .wid
.h2f_WDATA (h2f_WDATA), // .wdata
.h2f_WSTRB (h2f_WSTRB), // .wstrb
.h2f_WLAST (h2f_WLAST), // .wlast
.h2f_WVALID (h2f_WVALID), // .wvalid
.h2f_WREADY (h2f_WREADY), // .wready
.h2f_BID (h2f_BID), // .bid
.h2f_BRESP (h2f_BRESP), // .bresp
.h2f_BVALID (h2f_BVALID), // .bvalid
.h2f_BREADY (h2f_BREADY), // .bready
.h2f_ARID (h2f_ARID), // .arid
.h2f_ARADDR (h2f_ARADDR), // .araddr
.h2f_ARLEN (h2f_ARLEN), // .arlen
.h2f_ARSIZE (h2f_ARSIZE), // .arsize
.h2f_ARBURST (h2f_ARBURST), // .arburst
.h2f_ARLOCK (h2f_ARLOCK), // .arlock
.h2f_ARCACHE (h2f_ARCACHE), // .arcache
.h2f_ARPROT (h2f_ARPROT), // .arprot
.h2f_ARVALID (h2f_ARVALID), // .arvalid
.h2f_ARREADY (h2f_ARREADY), // .arready
.h2f_RID (h2f_RID), // .rid
.h2f_RDATA (h2f_RDATA), // .rdata
.h2f_RRESP (h2f_RRESP), // .rresp
.h2f_RLAST (h2f_RLAST), // .rlast
.h2f_RVALID (h2f_RVALID), // .rvalid
.h2f_RREADY (h2f_RREADY), // .rready
.f2h_dma_req0_req (f2h_dma_req0_req), // f2h_dma_req0.dma_req
.f2h_dma_req0_single (f2h_dma_req0_single), // .dma_single
.f2h_dma_req0_ack (f2h_dma_req0_ack) // .dma_ack
);
soc_system_hps_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO53 (hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_io_gpio_inst_GPIO61) // .hps_io_gpio_inst_GPIO61
);
endmodule
|
`include "oled_init.v"
`include "oled_cls.v"
module fpga (
input CLK,
input RST,
output CSN,
output SDIN,
output SCLK,
output DCN,
output RESN,
output VBATN,
output VDDN,
output [1:0] Led
);
reg [7:0] clock_counter='b0;
reg init_fin_latched='b1;
reg cls_fin_latched='b1;
assign Led[0]=init_fin_latched;
oled_init i_oled_init(
.clk(CLK),
.reset(RST),
.init_start(init_start),
.init_fin(init_fin),
.spi_csn(init_csn),
.spi_sdo(init_sdin),
.spi_sclk(init_sclk),
.spi_dcn(init_dcn),
.spi_resn(RESN),
.spi_vbatn(VBATN),
.spi_vddn(VDDN)
);
oled_cls i_oled_cls(
.clk(CLK),
.reset(RST),
.cls_start(cls_start),
.cls_fin(cls_fin),
.spi_csn(cls_csn),
.spi_sdo(cls_sdin),
.spi_sclk(cls_sclk),
.spi_dcn(cls_dcn)
);
assign init_start = (((&clock_counter)==1'b1) && (init_fin_latched==1'b0)) ? 1'b1 : 1'b0;
assign CSN = init_fin_latched ? cls_csn : init_csn;
assign SDIN = init_fin_latched ? cls_sdin : init_sdin;
assign SCLK = init_fin_latched ? cls_sclk : init_sclk;
assign DCN = init_fin_latched ? cls_dcn : init_dcn;
always @(posedge CLK) begin
if (RST) begin
clock_counter <= 'b0;
init_fin_latched <= 'b0;
cls_fin_latched <= 'b0;
end else begin
clock_counter <= clock_counter + 1;
if (init_fin)
init_fin_latched <= 'b1;
if (cls_fin)
cls_fin_latched <= 'b1;
end
end
assign cls_start = init_fin;
assign Led[1] = cls_fin_latched;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3B_TB_V
`define SKY130_FD_SC_MS__NAND3B_TB_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand3b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A_N = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A_N = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A_N = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A_N = 1'bx;
end
sky130_fd_sc_ms__nand3b dut (.A_N(A_N), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3B_TB_V
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll_25_37p5.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_25_37p5 (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [6:0] sub_wire1;
wire [0:0] sub_wire5 = 1'h0;
wire locked = sub_wire0;
wire [0:0] sub_wire2 = sub_wire1[0:0];
wire c0 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire4),
.locked (sub_wire0),
.clk (sub_wire1),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 2,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 3,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 40000,
altpll_component.intended_device_family = "Arria II GX",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_25_37p5",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "Left_Right",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clk6 = "PORT_UNUSED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "ON",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.width_clock = 7;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "3"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "37.500000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "3"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "37.50000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_25_37p5.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
// Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_25_37p5.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_25_37p5.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_25_37p5.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_25_37p5.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_25_37p5.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_25_37p5_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_25_37p5_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//======================================================================
//
// cmac.v
// ------
// Top level wrapper for the CMAC core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2016, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module cmac(
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam CTRL_FINAL_BIT = 2;
localparam ADDR_CONFIG = 8'h09;
localparam CONFIG_KEYLEN_BIT = 0;
localparam ADDR_STATUS = 8'h0a;
localparam STATUS_READY_BIT = 0;
localparam STATUS_VALID_BIT = 1;
localparam ADDR_FINAL_SIZE = 8'h0b;
localparam ADDR_KEY0 = 8'h10;
localparam ADDR_KEY7 = 8'h17;
localparam ADDR_BLOCK0 = 8'h20;
localparam ADDR_BLOCK1 = 8'h21;
localparam ADDR_BLOCK2 = 8'h22;
localparam ADDR_BLOCK3 = 8'h23;
localparam ADDR_RESULT0 = 8'h30;
localparam ADDR_RESULT1 = 8'h31;
localparam ADDR_RESULT2 = 8'h32;
localparam ADDR_RESULT3 = 8'h33;
localparam CORE_NAME0 = 32'h636d6163; // "cmac"
localparam CORE_NAME1 = 32'h2d616573; // "-aes"
localparam CORE_VERSION = 32'h302e3032; // "0.02"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg keylen_reg;
reg config_we;
reg [7 : 0] final_size_reg;
reg final_size_we;
reg [31 : 0] block_reg [0 : 3];
reg block_we;
reg [31 : 0] key_reg [0 : 7];
reg key_we;
reg init_reg;
reg init_new;
reg next_reg;
reg next_new;
reg finalize_reg;
reg finalize_new;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_read_data;
wire core_ready;
wire core_valid;
wire [255 : 0] core_key;
wire [127 : 0] core_block;
wire [127 : 0] core_result;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign core_key = {key_reg[0], key_reg[1], key_reg[2], key_reg[3],
key_reg[4], key_reg[5], key_reg[6], key_reg[7]};
assign core_block = {block_reg[0], block_reg[1],
block_reg[2], block_reg[3]};
//----------------------------------------------------------------
// CMAC core instantiation.
//----------------------------------------------------------------
cmac_core cmac_inst(
.clk(clk),
.reset_n(reset_n),
.key(core_key),
.keylen(keylen_reg),
.final_size(final_size_reg),
.init(init_reg),
.next(next_reg),
.finalize(finalize_reg),
.block(core_block),
.result(core_result),
.ready(core_ready),
.valid(core_valid)
);
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
integer i;
if (!reset_n)
begin
for (i = 0; i < 4; i = i + 1)
block_reg[i] <= 32'h0;
for (i = 0; i < 8; i = i + 1)
key_reg[i] <= 32'h0;
keylen_reg <= 1'h0;
final_size_reg <= 8'h0;
init_reg <= 1'h0;
next_reg <= 1'h0;
finalize_reg <= 1'h0;
end
else
begin
init_reg <= init_new;
next_reg <= next_new;
finalize_reg <= finalize_new;
if (config_we)
begin
keylen_reg <= write_data[CONFIG_KEYLEN_BIT];
end
if (final_size_we)
final_size_reg <= write_data[7 : 0];
if (key_we)
key_reg[address[2 : 0]] <= write_data;
if (block_we)
block_reg[address[1 : 0]] <= write_data;
end
end // reg_update
//----------------------------------------------------------------
// api
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
init_new = 1'h0;
next_new = 1'h0;
finalize_new = 1'h0;
final_size_we = 1'h0;
config_we = 1'h0;
key_we = 1'h0;
block_we = 1'h0;
tmp_read_data = 32'h0;
if (cs)
begin
if (we)
begin
if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
key_we = 1'h1;
if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3))
block_we = 1'h1;
case (address)
ADDR_CTRL:
begin
init_new = write_data[CTRL_INIT_BIT];
next_new = write_data[CTRL_NEXT_BIT];
finalize_new = write_data[CTRL_FINAL_BIT];
end
ADDR_CONFIG: config_we = 1'h1;
ADDR_FINAL_SIZE: final_size_we = 1'h1;
default:
begin
end
endcase // case (address)
end // if (we)
else
begin
case (address)
ADDR_NAME0: tmp_read_data = CORE_NAME0;
ADDR_NAME1: tmp_read_data = CORE_NAME1;
ADDR_VERSION: tmp_read_data = CORE_VERSION;
ADDR_CTRL: tmp_read_data = {31'h0, keylen_reg};
ADDR_STATUS: tmp_read_data = {30'h0, core_valid, core_ready};
ADDR_FINAL_SIZE: tmp_read_data = {24'h0, final_size_reg};
ADDR_RESULT0: tmp_read_data = core_result[127 : 96];
ADDR_RESULT1: tmp_read_data = core_result[95 : 64];
ADDR_RESULT2: tmp_read_data = core_result[63 : 32];
ADDR_RESULT3: tmp_read_data = core_result[31 : 0];
default:
begin
end
endcase // case (address)
end
end
end // addr_decoder
endmodule // cmac
//======================================================================
// EOF cmac.v
//======================================================================
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211A_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__O211A_BEHAVIORAL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o211a (
X ,
A1,
A2,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211A_BEHAVIORAL_V |
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6.1
// \ \ Application: MIG
// / / Filename: mig_36_1.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:26:02 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// Top-level module. Simple model for what the user might use
// typically, the user will only instantiate MEM_INTERFACE_TOP in their
// code, and generate all the other infrastructure logic separately.
// This module serves both as an example, and allows the user
// to synthesize a self-contained design, which they can use to test their
// hardware.
// In addition to the memory controller, the module instantiates:
// 1. Reset logic based on user clocks
// 2. IDELAY control block
// 3. Synthesizable testbench - used to model user's backend logic
//Reference:
//Revision History:
// Rev 1.1 - Parameter USE_DM_PORT added. PK. 6/25/08
// Rev 1.2 - Parameter HIGH_PERFORMANCE_MODE added. PK. 7/10/08
// Rev 1.3 - Parameter IODELAY_GRP added. PK. 11/27/08
//*****************************************************************************
`timescale 1ns/1ps
(* X_CORE_INFO = "mig_v3_61_ddr2_v5, Coregen 12.4" , CORE_GENERATION_INFO = "ddr2_v5,mig_v3_61,{component_name=mig_36_1, BANK_WIDTH=2, CKE_WIDTH=1, CLK_WIDTH=2, COL_WIDTH=10, CS_NUM=1, CS_WIDTH=1, DM_WIDTH=8, DQ_WIDTH=64, DQ_PER_DQS=8, DQS_WIDTH=8, ODT_WIDTH=1, ROW_WIDTH=13, ADDITIVE_LAT=0, BURST_LEN=4, BURST_TYPE=0, CAS_LAT=4, ECC_ENABLE=0, MULTI_BANK_EN=1, TWO_T_TIME_EN=1, ODT_TYPE=1, REDUCE_DRV=0, REG_ENABLE=0, TREFI_NS=7800, TRAS=40000, TRCD=15000, TRFC=105000, TRP=15000, TRTP=7500, TWR=15000, TWTR=7500, CLK_PERIOD=3750, RST_ACT_LOW=1, INTERFACE_TYPE=DDR2_SDRAM, LANGUAGE=Verilog, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1}" *)
module mig_36_1 #
(
parameter BANK_WIDTH = 2,
// # of memory bank addr bits.
parameter CKE_WIDTH = 1,
// # of memory clock enable outputs.
parameter CLK_WIDTH = 2,
// # of clock outputs.
parameter COL_WIDTH = 10,
// # of memory column bits.
parameter CS_NUM = 1,
// # of separate memory chip selects.
parameter CS_WIDTH = 1,
// # of total memory chip selects.
parameter CS_BITS = 0,
// set to log2(CS_NUM) (rounded up).
parameter DM_WIDTH = 8,
// # of data mask bits.
parameter DQ_WIDTH = 64,
// # of data width.
parameter DQ_PER_DQS = 8,
// # of DQ data bits per strobe.
parameter DQS_WIDTH = 8,
// # of DQS strobes.
parameter DQ_BITS = 6,
// set to log2(DQS_WIDTH*DQ_PER_DQS).
parameter DQS_BITS = 3,
// set to log2(DQS_WIDTH).
parameter ODT_WIDTH = 1,
// # of memory on-die term enables.
parameter ROW_WIDTH = 13,
// # of memory row and # of addr bits.
parameter ADDITIVE_LAT = 0,
// additive write latency.
parameter BURST_LEN = 4,
// burst length (in double words).
parameter BURST_TYPE = 0,
// burst type (=0 seq; =1 interleaved).
parameter CAS_LAT = 4,
// CAS latency.
parameter ECC_ENABLE = 0,
// enable ECC (=1 enable).
parameter APPDATA_WIDTH = 128,
// # of usr read/write data bus bits.
parameter MULTI_BANK_EN = 1,
// Keeps multiple banks open. (= 1 enable).
parameter TWO_T_TIME_EN = 1,
// 2t timing for unbuffered dimms.
parameter ODT_TYPE = 1,
// ODT (=0(none),=1(75),=2(150),=3(50)).
parameter REDUCE_DRV = 0,
// reduced strength mem I/O (=1 yes).
parameter REG_ENABLE = 0,
// registered addr/ctrl (=1 yes).
parameter TREFI_NS = 7800,
// auto refresh interval (ns).
parameter TRAS = 40000,
// active->precharge delay.
parameter TRCD = 15000,
// active->read/write delay.
parameter TRFC = 105000,
// refresh->refresh, refresh->active delay.
parameter TRP = 15000,
// precharge->command delay.
parameter TRTP = 7500,
// read->precharge delay.
parameter TWR = 15000,
// used to determine write->precharge.
parameter TWTR = 7500,
// write->read delay.
parameter HIGH_PERFORMANCE_MODE = "TRUE",
// # = TRUE, the IODELAY performance mode is set
// to high.
// # = FALSE, the IODELAY performance mode is set
// to low.
parameter SIM_ONLY = 0,
// = 1 to skip SDRAM power up delay.
parameter DEBUG_EN = 0,
// Enable debug signals/controls.
// When this parameter is changed from 0 to 1,
// make sure to uncomment the coregen commands
// in ise_flow.bat or create_ise.bat files in
// par folder.
parameter CLK_PERIOD = 3750,
// Core/Memory clock period (in ps).
parameter DLL_FREQ_MODE = "HIGH",
// DCM Frequency range.
parameter CLK_TYPE = "DIFFERENTIAL",
// # = "DIFFERENTIAL " ->; Differential input clocks ,
// # = "SINGLE_ENDED" -> Single ended input clocks.
parameter NOCLK200 = 0,
// clk200 enable and disable.
parameter RST_ACT_LOW = 1
// =1 for active low reset, =0 for active high.
)
(
inout [DQ_WIDTH-1:0] ddr2_dq,
output [ROW_WIDTH-1:0] ddr2_a,
output [BANK_WIDTH-1:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [CS_WIDTH-1:0] ddr2_cs_n,
output [ODT_WIDTH-1:0] ddr2_odt,
output [CKE_WIDTH-1:0] ddr2_cke,
output [DM_WIDTH-1:0] ddr2_dm,
input sys_clk_p,
input sys_clk_n,
input clk200_p,
input clk200_n,
input sys_rst_n,
output phy_init_done,
output error,
inout [DQS_WIDTH-1:0] ddr2_dqs,
inout [DQS_WIDTH-1:0] ddr2_dqs_n,
output [CLK_WIDTH-1:0] ddr2_ck,
output [CLK_WIDTH-1:0] ddr2_ck_n,
//For debugging
output wire [7:0] LED //8 optional LEDs for visual feedback & debugging
);
//***************************************************************************
// IODELAY Group Name: Replication and placement of IDELAYCTRLs will be
// handled automatically by software tools if IDELAYCTRLs have same refclk,
// reset and rdy nets. Designs with a unique RESET will commonly create a
// unique RDY. Constraint IODELAY_GROUP is associated to a set of IODELAYs
// with an IDELAYCTRL. The parameter IODELAY_GRP value can be any string.
//***************************************************************************
localparam IODELAY_GRP = "IODELAY_MIG";
wire sys_clk;
wire idly_clk_200;
wire error_cmp;
wire rst0;
wire rst90;
wire rstdiv0;
wire rst200;
wire clk0;
wire clk90;
wire clkdiv0;
wire clk200;
wire idelay_ctrl_rdy;
wire app_wdf_afull;
wire app_af_afull;
wire rd_data_valid;
wire app_wdf_wren;
wire app_af_wren;
wire [30:0] app_af_addr;
wire [2:0] app_af_cmd;
wire [(APPDATA_WIDTH)-1:0] rd_data_fifo_out;
wire [(APPDATA_WIDTH)-1:0] app_wdf_data;
wire [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data;
//Debug signals
wire [3:0] dbg_calib_done;
wire [3:0] dbg_calib_err;
wire [(6*DQ_WIDTH)-1:0] dbg_calib_dq_tap_cnt;
wire [(6*DQS_WIDTH)-1:0] dbg_calib_dqs_tap_cnt;
wire [(6*DQS_WIDTH)-1:0] dbg_calib_gate_tap_cnt;
wire [DQS_WIDTH-1:0] dbg_calib_rd_data_sel;
wire [(5*DQS_WIDTH)-1:0] dbg_calib_rden_dly;
wire [(5*DQS_WIDTH)-1:0] dbg_calib_gate_dly;
wire dbg_idel_up_all;
wire dbg_idel_down_all;
wire dbg_idel_up_dq;
wire dbg_idel_down_dq;
wire dbg_idel_up_dqs;
wire dbg_idel_down_dqs;
wire dbg_idel_up_gate;
wire dbg_idel_down_gate;
wire [DQ_BITS-1:0] dbg_sel_idel_dq;
wire dbg_sel_all_idel_dq;
wire [DQS_BITS:0] dbg_sel_idel_dqs;
wire dbg_sel_all_idel_dqs;
wire [DQS_BITS:0] dbg_sel_idel_gate;
wire dbg_sel_all_idel_gate;
// Debug signals (optional use)
//***********************************
// PHY Debug Port demo
//***********************************
wire [35:0] cs_control0;
wire [35:0] cs_control1;
wire [35:0] cs_control2;
wire [35:0] cs_control3;
wire [191:0] vio0_in;
wire [95:0] vio1_in;
wire [99:0] vio2_in;
wire [31:0] vio3_out;
//***************************************************************************
assign sys_clk = 1'b0;
assign idly_clk_200 = 1'b0;
ddr2_idelay_ctrl #
(
.IODELAY_GRP (IODELAY_GRP)
)
u_ddr2_idelay_ctrl
(
.rst200 (rst200),
.clk200 (clk200),
.idelay_ctrl_rdy (idelay_ctrl_rdy)
);
ddr2_infrastructure #
(
.CLK_PERIOD (CLK_PERIOD),
.DLL_FREQ_MODE (DLL_FREQ_MODE),
.CLK_TYPE (CLK_TYPE),
.NOCLK200 (NOCLK200),
.RST_ACT_LOW (RST_ACT_LOW)
)
u_ddr2_infrastructure
(
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.sys_clk (sys_clk),
.clk200_p (clk200_p),
.clk200_n (clk200_n),
.idly_clk_200 (idly_clk_200),
.sys_rst_n (sys_rst_n),
.rst0 (rst0),
.rst90 (rst90),
.rstdiv0 (rstdiv0),
.rst200 (rst200),
.clk0 (clk0),
.clk90 (clk90),
.clkdiv0 (clkdiv0),
.clk200 (clk200),
.idelay_ctrl_rdy (idelay_ctrl_rdy)
);
ddr2_top #
(
.BANK_WIDTH (BANK_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.CLK_WIDTH (CLK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_NUM (CS_NUM),
.CS_WIDTH (CS_WIDTH),
.CS_BITS (CS_BITS),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQ_PER_DQS (DQ_PER_DQS),
.DQS_WIDTH (DQS_WIDTH),
.DQ_BITS (DQ_BITS),
.DQS_BITS (DQS_BITS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.ADDITIVE_LAT (ADDITIVE_LAT),
.BURST_LEN (BURST_LEN),
.BURST_TYPE (BURST_TYPE),
.CAS_LAT (CAS_LAT),
.ECC_ENABLE (ECC_ENABLE),
.APPDATA_WIDTH (APPDATA_WIDTH),
.MULTI_BANK_EN (MULTI_BANK_EN),
.TWO_T_TIME_EN (TWO_T_TIME_EN),
.ODT_TYPE (ODT_TYPE),
.REDUCE_DRV (REDUCE_DRV),
.REG_ENABLE (REG_ENABLE),
.TREFI_NS (TREFI_NS),
.TRAS (TRAS),
.TRCD (TRCD),
.TRFC (TRFC),
.TRP (TRP),
.TRTP (TRTP),
.TWR (TWR),
.TWTR (TWTR),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.IODELAY_GRP (IODELAY_GRP),
.SIM_ONLY (SIM_ONLY),
.DEBUG_EN (DEBUG_EN),
.FPGA_SPEED_GRADE (1),
.USE_DM_PORT (1),
.CLK_PERIOD (CLK_PERIOD)
)
u_ddr2_top_0
(
.ddr2_dq (ddr2_dq),
.ddr2_a (ddr2_a),
.ddr2_ba (ddr2_ba),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_we_n (ddr2_we_n),
.ddr2_cs_n (ddr2_cs_n),
.ddr2_odt (ddr2_odt),
.ddr2_cke (ddr2_cke),
.ddr2_dm (ddr2_dm),
.phy_init_done (phy_init_done),
.rst0 (rst0),
.rst90 (rst90),
.rstdiv0 (rstdiv0),
.clk0 (clk0),
.clk90 (clk90),
.clkdiv0 (clkdiv0),
.app_wdf_afull (app_wdf_afull),
.app_af_afull (app_af_afull),
.rd_data_valid (rd_data_valid),
.app_wdf_wren (app_wdf_wren),
.app_af_wren (app_af_wren),
.app_af_addr (app_af_addr),
.app_af_cmd (app_af_cmd),
.rd_data_fifo_out (rd_data_fifo_out),
.app_wdf_data (app_wdf_data),
.app_wdf_mask_data (app_wdf_mask_data),
.ddr2_dqs (ddr2_dqs),
.ddr2_dqs_n (ddr2_dqs_n),
.ddr2_ck (ddr2_ck),
.rd_ecc_error (),
.ddr2_ck_n (ddr2_ck_n),
.dbg_calib_done (dbg_calib_done),
.dbg_calib_err (dbg_calib_err),
.dbg_calib_dq_tap_cnt (dbg_calib_dq_tap_cnt),
.dbg_calib_dqs_tap_cnt (dbg_calib_dqs_tap_cnt),
.dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
.dbg_calib_rd_data_sel (dbg_calib_rd_data_sel),
.dbg_calib_rden_dly (dbg_calib_rden_dly),
.dbg_calib_gate_dly (dbg_calib_gate_dly),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_dq (dbg_idel_up_dq),
.dbg_idel_down_dq (dbg_idel_down_dq),
.dbg_idel_up_dqs (dbg_idel_up_dqs),
.dbg_idel_down_dqs (dbg_idel_down_dqs),
.dbg_idel_up_gate (dbg_idel_up_gate),
.dbg_idel_down_gate (dbg_idel_down_gate),
.dbg_sel_idel_dq (dbg_sel_idel_dq),
.dbg_sel_all_idel_dq (dbg_sel_all_idel_dq),
.dbg_sel_idel_dqs (dbg_sel_idel_dqs),
.dbg_sel_all_idel_dqs (dbg_sel_all_idel_dqs),
.dbg_sel_idel_gate (dbg_sel_idel_gate),
.dbg_sel_all_idel_gate (dbg_sel_all_idel_gate)
);
ddr2_tb_top #
(
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.BURST_LEN (BURST_LEN),
.ECC_ENABLE (ECC_ENABLE),
.APPDATA_WIDTH (APPDATA_WIDTH)
)
u_ddr2_tb_top_0
(
.phy_init_done (phy_init_done),
.error (error),
.error_cmp (error_cmp),
.rst0 (rst0),
.clk0 (clk0),
.app_wdf_afull (app_wdf_afull),
.app_af_afull (app_af_afull),
.rd_data_valid (rd_data_valid),
.app_wdf_wren (app_wdf_wren),
.app_af_wren (app_af_wren),
.app_af_addr (app_af_addr),
.app_af_cmd (app_af_cmd),
.rd_data_fifo_out (rd_data_fifo_out),
.app_wdf_data (app_wdf_data),
.app_wdf_mask_data (app_wdf_mask_data),
.LED (LED)
);
//*****************************************************************
// Hooks to prevent sim/syn compilation errors (mainly for VHDL - but
// keep it also in Verilog version of code) w/ floating inputs if
// DEBUG_EN = 0.
//*****************************************************************
generate
if (DEBUG_EN == 0) begin: gen_dbg_tie_off
assign dbg_idel_up_all = 'b0;
assign dbg_idel_down_all = 'b0;
assign dbg_idel_up_dq = 'b0;
assign dbg_idel_down_dq = 'b0;
assign dbg_idel_up_dqs = 'b0;
assign dbg_idel_down_dqs = 'b0;
assign dbg_idel_up_gate = 'b0;
assign dbg_idel_down_gate = 'b0;
assign dbg_sel_idel_dq = 'b0;
assign dbg_sel_all_idel_dq = 'b0;
assign dbg_sel_idel_dqs = 'b0;
assign dbg_sel_all_idel_dqs = 'b0;
assign dbg_sel_idel_gate = 'b0;
assign dbg_sel_all_idel_gate = 'b0;
end else begin: gen_dbg_enable
//*****************************************************************
// PHY Debug Port example - see MIG User's Guide, XAPP858 or
// Answer Record 29443
// This logic supports up to 32 DQ and 8 DQS I/O
// NOTES:
// 1. PHY Debug Port demo connects to 4 VIO modules:
// - 3 VIO modules with only asynchronous inputs
// * Monitor IDELAY taps for DQ, DQS, DQS Gate
// * Calibration status
// - 1 VIO module with synchronous outputs
// * Allow dynamic adjustment o f IDELAY taps
// 2. User may need to modify this code to incorporate other
// chipscope-related modules in their larger design (e.g.
// if they have other ILA/VIO modules, they will need to
// for example instantiate a larger ICON module). In addition
// user may want to instantiate more VIO modules to control
// IDELAY for more DQ, DQS than is shown here
//*****************************************************************
icon4 u_icon
(
.control0 (cs_control0),
.control1 (cs_control1),
.control2 (cs_control2),
.control3 (cs_control3)
);
//*****************************************************************
// VIO ASYNC input: Display current IDELAY setting for up to 32
// DQ taps (32x6) = 192
//*****************************************************************
vio_async_in192 u_vio0
(
.control (cs_control0),
.async_in (vio0_in)
);
//*****************************************************************
// VIO ASYNC input: Display current IDELAY setting for up to 8 DQS
// and DQS Gate taps (8x6x2) = 96
//*****************************************************************
vio_async_in96 u_vio1
(
.control (cs_control1),
.async_in (vio1_in)
);
//*****************************************************************
// VIO ASYNC input: Display other calibration results
//*****************************************************************
vio_async_in100 u_vio2
(
.control (cs_control2),
.async_in (vio2_in)
);
//*****************************************************************
// VIO SYNC output: Dynamically change IDELAY taps
//*****************************************************************
vio_sync_out32 u_vio3
(
.control (cs_control3),
.clk (clkdiv0),
.sync_out (vio3_out)
);
//*****************************************************************
// Bit assignments:
// NOTE: Not all VIO, ILA inputs/outputs may be used - these will
// be dependent on the user's particular bit width
//*****************************************************************
if (DQ_WIDTH <= 32) begin: gen_dq_le_32
assign vio0_in[(6*DQ_WIDTH)-1:0]
= dbg_calib_dq_tap_cnt[(6*DQ_WIDTH)-1:0];
end else begin: gen_dq_gt_32
assign vio0_in = dbg_calib_dq_tap_cnt[191:0];
end
if (DQS_WIDTH <= 8) begin: gen_dqs_le_8
assign vio1_in[(6*DQS_WIDTH)-1:0]
= dbg_calib_dqs_tap_cnt[(6*DQS_WIDTH)-1:0];
assign vio1_in[(12*DQS_WIDTH)-1:(6*DQS_WIDTH)]
= dbg_calib_gate_tap_cnt[(6*DQS_WIDTH)-1:0];
end else begin: gen_dqs_gt_32
assign vio1_in[47:0] = dbg_calib_dqs_tap_cnt[47:0];
assign vio1_in[95:48] = dbg_calib_gate_tap_cnt[47:0];
end
//dbg_calib_rd_data_sel
if (DQS_WIDTH <= 8) begin: gen_rdsel_le_8
assign vio2_in[(DQS_WIDTH)+7:8]
= dbg_calib_rd_data_sel[(DQS_WIDTH)-1:0];
end else begin: gen_rdsel_gt_32
assign vio2_in[15:8]
= dbg_calib_rd_data_sel[7:0];
end
//dbg_calib_rden_dly
if (DQS_WIDTH <= 8) begin: gen_calrd_le_8
assign vio2_in[(5*DQS_WIDTH)+19:20]
= dbg_calib_rden_dly[(5*DQS_WIDTH)-1:0];
end else begin: gen_calrd_gt_32
assign vio2_in[59:20]
= dbg_calib_rden_dly[39:0];
end
//dbg_calib_gate_dly
if (DQS_WIDTH <= 8) begin: gen_calgt_le_8
assign vio2_in[(5*DQS_WIDTH)+59:60]
= dbg_calib_gate_dly[(5*DQS_WIDTH)-1:0];
end else begin: gen_calgt_gt_32
assign vio2_in[99:60]
= dbg_calib_gate_dly[39:0];
end
//dbg_sel_idel_dq
if (DQ_BITS <= 5) begin: gen_selid_le_5
assign dbg_sel_idel_dq[DQ_BITS-1:0]
= vio3_out[DQ_BITS+7:8];
end else begin: gen_selid_gt_32
assign dbg_sel_idel_dq[4:0]
= vio3_out[12:8];
end
//dbg_sel_idel_dqs
if (DQS_BITS <= 3) begin: gen_seldqs_le_3
assign dbg_sel_idel_dqs[DQS_BITS:0]
= vio3_out[(DQS_BITS+16):16];
end else begin: gen_seldqs_gt_32
assign dbg_sel_idel_dqs[3:0]
= vio3_out[19:16];
end
//dbg_sel_idel_gate
if (DQS_BITS <= 3) begin: gen_gtdqs_le_3
assign dbg_sel_idel_gate[DQS_BITS:0]
= vio3_out[(DQS_BITS+21):21];
end else begin: gen_gtdqs_gt_32
assign dbg_sel_idel_gate[3:0]
= vio3_out[24:21];
end
assign vio2_in[3:0] = dbg_calib_done;
assign vio2_in[7:4] = dbg_calib_err;
assign dbg_idel_up_all = vio3_out[0];
assign dbg_idel_down_all = vio3_out[1];
assign dbg_idel_up_dq = vio3_out[2];
assign dbg_idel_down_dq = vio3_out[3];
assign dbg_idel_up_dqs = vio3_out[4];
assign dbg_idel_down_dqs = vio3_out[5];
assign dbg_idel_up_gate = vio3_out[6];
assign dbg_idel_down_gate = vio3_out[7];
assign dbg_sel_all_idel_dq = vio3_out[15];
assign dbg_sel_all_idel_dqs = vio3_out[20];
assign dbg_sel_all_idel_gate = vio3_out[25];
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__DFRTP_FUNCTIONAL_PP_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFRTP_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__NOR4BB_BEHAVIORAL_PP_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nor4bb (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , nor0_out, C_N, D_N );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4BB_BEHAVIORAL_PP_V |
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Idle Inserter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_idle_inserter (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & out_ready) begin
if ((idle_char | escape_char) & ~received_esc & out_ready) begin
received_esc <= 1;
end else begin
received_esc <= 0;
end
end
end
end
always @* begin
//we are always valid
out_valid = 1'b1;
in_ready = out_ready & (~in_valid | ((~idle_char & ~escape_char) | received_esc));
out_data = (~in_valid) ? 8'h4a : //if input is not valid, insert idle
(received_esc) ? in_data ^ 8'h20 : //escaped once, send data XOR'd
(idle_char | escape_char) ? 8'h4d : //input needs escaping, send escape_char
in_data; //send data
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 1
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2015.1" *)
(* CHECK_LICENSE_TYPE = "week1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "week1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=true,C_FCLK_CLK1_BUF=false,C_FCLK_CLK2_BUF=false,C_FCLK_CLK3_BUF=false,C_PACKAGE_NAME=clg484}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module week1_processing_system7_0_0 (
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_RX" *)
output wire ENET0_PTP_DELAY_REQ_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_TX" *)
output wire ENET0_PTP_DELAY_REQ_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_REQ_RX" *)
output wire ENET0_PTP_PDELAY_REQ_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_REQ_TX" *)
output wire ENET0_PTP_PDELAY_REQ_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_RESP_RX" *)
output wire ENET0_PTP_PDELAY_RESP_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_RESP_TX" *)
output wire ENET0_PTP_PDELAY_RESP_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SYNC_FRAME_RX" *)
output wire ENET0_PTP_SYNC_FRAME_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SYNC_FRAME_TX" *)
output wire ENET0_PTP_SYNC_FRAME_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SOF_RX" *)
output wire ENET0_SOF_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SOF_TX" *)
output wire ENET0_SOF_TX;
output wire TTC0_WAVE0_OUT;
output wire TTC0_WAVE1_OUT;
output wire TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *)
output wire [1 : 0] USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *)
output wire USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *)
input wire USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
output wire M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
output wire M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
output wire M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
output wire M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
output wire M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
output wire M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
output wire [11 : 0] M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
output wire [11 : 0] M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
output wire [11 : 0] M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
output wire [1 : 0] M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
output wire [1 : 0] M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
output wire [2 : 0] M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
output wire [1 : 0] M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
output wire [1 : 0] M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
output wire [2 : 0] M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
output wire [2 : 0] M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
output wire [2 : 0] M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
output wire [31 : 0] M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
output wire [31 : 0] M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
output wire [31 : 0] M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
output wire [3 : 0] M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
output wire [3 : 0] M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
output wire [3 : 0] M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
output wire [3 : 0] M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
output wire [3 : 0] M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
output wire [3 : 0] M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
output wire [3 : 0] M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
input wire M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
input wire M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
input wire M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
input wire M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
input wire M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
input wire M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
input wire M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
input wire [11 : 0] M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
input wire [11 : 0] M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
input wire [1 : 0] M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
input wire [1 : 0] M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
input wire [31 : 0] M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *)
input wire [0 : 0] IRQ_F2P;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(1),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_USE_AXI_NONSECURE(0),
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_USE_S_AXI_ACP(0),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("true"),
.C_FCLK_CLK1_BUF("false"),
.C_FCLK_CLK2_BUF("false"),
.C_FCLK_CLK3_BUF("false"),
.C_PACKAGE_NAME("clg484")
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(ENET0_PTP_DELAY_REQ_RX),
.ENET0_PTP_DELAY_REQ_TX(ENET0_PTP_DELAY_REQ_TX),
.ENET0_PTP_PDELAY_REQ_RX(ENET0_PTP_PDELAY_REQ_RX),
.ENET0_PTP_PDELAY_REQ_TX(ENET0_PTP_PDELAY_REQ_TX),
.ENET0_PTP_PDELAY_RESP_RX(ENET0_PTP_PDELAY_RESP_RX),
.ENET0_PTP_PDELAY_RESP_TX(ENET0_PTP_PDELAY_RESP_TX),
.ENET0_PTP_SYNC_FRAME_RX(ENET0_PTP_SYNC_FRAME_RX),
.ENET0_PTP_SYNC_FRAME_TX(ENET0_PTP_SYNC_FRAME_TX),
.ENET0_SOF_RX(ENET0_SOF_RX),
.ENET0_SOF_TX(ENET0_SOF_TX),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(1'B0),
.I2C0_SDA_O(),
.I2C0_SDA_T(),
.I2C0_SCL_I(1'B0),
.I2C0_SCL_O(),
.I2C0_SCL_T(),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(1'B0),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_RCOUNT(),
.S_AXI_HP0_WCOUNT(),
.S_AXI_HP0_RACOUNT(),
.S_AXI_HP0_WACOUNT(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RDISSUECAP1_EN(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WRISSUECAP1_EN(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(IRQ_F2P),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
// megafunction wizard: %Altera PLL v13.0%
// GENERATION: XML
// pll_vga.v
// Generated using ACDS version 13.0 144 at 2013.03.27.20:21:13
`timescale 1 ps / 1 ps
module pll_vga (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0 // outclk0.clk
);
pll_vga_0002 pll_vga_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.locked () // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2013 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="13.0" >
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="gui_device_speed_grade" value="8" />
// Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="normal" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="false" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="1" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="25.0" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0" />
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0" />
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0" />
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0" />
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0" />
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0" />
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0" />
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0" />
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0" />
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0" />
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0" />
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0" />
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0" />
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0" />
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="false" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_mif_generate" value="false" />
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
// Retrieval info: <generic name="gui_dps_num" value="1" />
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: <generic name="AUTO_REFCLK_CLOCK_RATE" value="-1" />
// Retrieval info: </instance>
// IPFS_FILES : pll_vga.vo
// RELATED_FILES: pll_vga.v, pll_vga_0002.v
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXTN_2_V
`define SKY130_FD_SC_MS__DLXTN_2_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog wrapper for dlxtn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlxtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlxtn_2 (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlxtn_2 (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXTN_2_V
|
`timescale 1ns / 1ps
/*
Instruction decode pipeline stage
*/
module id_stage( input clk, rst,
input reg_write,
input [4:0] wreg_addr, // write register number
input [31:0] wreg_data, // data to write into regfile
input [31:0] instruction, next_i_addr, // instruction fetched, next instruction address
//inputs to support forwarding
input [1:0] rs_fwd_sel, rt_fwd_sel, // forwarding control signals
input [31:0] mem_fwd_val, wb_fwd_val, // forwarded data values
input hazard,
input pstop_i,
//outputs
output [4:0] id_rs,
output [4:0] id_rt,
output [5:0] id_opcode,
output reg [31:0] ID_EX_A,
output reg [31:0] ID_EX_B,
output reg [4:0] ID_EX_rt,
output reg [4:0] ID_EX_rs,
output reg [4:0] ID_EX_rd,
output reg [5:0] ID_EX_opcode,
output reg [31:0] ID_EX_sign_extend_offset,
output reg ID_EX_wb_reg_write,
output reg ID_EX_wb_mem_to_reg,
output reg ID_EX_mem_read,
output reg ID_EX_mem_write,
output reg ID_EX_ex_imm_command,
output reg ID_EX_ex_alu_src_b,
output reg ID_EX_ex_alu_rslt_src,
output reg [1:0] ID_EX_ex_dst_reg_sel,
output reg [1:0] ID_EX_ex_alu_op,
output [31:0] branch_addr, jump_addr, // branch and jump adresses
output id_rt_is_source,
output [1:0] if_pc_source );
reg [31:0] A, B;
wire [31:0] a_out;
wire [31:0] b_out;
wire [31:0] sign_extend_offset;
wire ex_imm_command;
wire ex_alu_src_b;
wire ex_alu_rslt_src;
wire [1:0] ex_dst_reg_sel;
wire [1:0] ex_alu_op;
wire mem_read;
wire mem_write;
wire wb_mem_to_reg;
wire wb_reg_write;
wire is_nop;
wire branch_eq;
regfile regfile_inst (
.clk( clk ),
.rst( rst ),
.raddr1( instruction[25:21] ),
.raddr2( instruction[20:16] ),
.waddr( wreg_addr ),
.wdata( wreg_data ),
.w_en( reg_write ),
.rdata1( a_out ),
.rdata2( b_out ));
// Forwarding muxes
always @* begin
A = 0;
case (rs_fwd_sel)
0: A = a_out;
1: A = mem_fwd_val;
2: A = wb_fwd_val;
endcase
end
always @* begin
B = 0;
case (rt_fwd_sel)
0: B = b_out;
1: B = mem_fwd_val;
2: B = wb_fwd_val;
endcase
end
assign sign_extend_offset = { { 16{instruction[15]} }, instruction [15:0]};
assign branch_addr = next_i_addr + ( sign_extend_offset << 2 );
assign jump_addr = {next_i_addr[31:28], instruction[25:0], 2'b00 };
assign branch_eq = ( A == B);
assign id_rs = instruction[25:21];
assign id_rt = instruction[20:16];
assign id_opcode = instruction[31:26];
assign is_nop = ~|instruction;
//Control Unit -- Opcode Decoder
control cunit_instance (
.opcode( instruction [31:26] ),
.special( instruction [5:0] ),
.branch_eq( branch_eq ),
.id_rt_is_source(id_rt_is_source),
.if_pc_source(if_pc_source),
.ex_imm_command(ex_imm_command),
.ex_alu_src_b(ex_alu_src_b),
.ex_alu_rslt_src(ex_alu_rslt_src),
.ex_dst_reg_sel(ex_dst_reg_sel),
.ex_alu_op(ex_alu_op),
.mem_read(mem_read),
.mem_write(mem_write),
.wb_mem_to_reg(wb_mem_to_reg),
.wb_reg_write(wb_reg_write));
//ID/EX Pipeline register
always @(posedge clk) begin
if (rst) begin
ID_EX_A <= 0;
ID_EX_B <= 0;
ID_EX_rt <= 0;
ID_EX_rs <= 0;
ID_EX_rd <= 0;
ID_EX_opcode <= 0;
ID_EX_sign_extend_offset <= 0;
ID_EX_wb_reg_write <= 0;
ID_EX_wb_mem_to_reg <= 0;
ID_EX_mem_read <= 0;
ID_EX_mem_write <= 0;
ID_EX_ex_imm_command <= 0;
ID_EX_ex_alu_src_b <= 0;
ID_EX_ex_alu_rslt_src <= 0;
ID_EX_ex_dst_reg_sel <= 0;
ID_EX_ex_alu_op <= 0;
end
else begin
if(!pstop_i) begin
ID_EX_A <= A;
ID_EX_B <= B;
ID_EX_rt <= id_rt;
ID_EX_rs <= id_rs;
ID_EX_rd <= instruction[15:11];
ID_EX_opcode <= id_opcode;
ID_EX_sign_extend_offset <= sign_extend_offset;
end
if(!pstop_i) begin
if (is_nop || hazard) begin
ID_EX_wb_reg_write <= 0;
ID_EX_wb_mem_to_reg <= 0;
ID_EX_mem_read <= 0;
ID_EX_mem_write <= 0;
ID_EX_ex_imm_command <= 0;
ID_EX_ex_alu_src_b <= 0;
ID_EX_ex_alu_rslt_src <= 0;
ID_EX_ex_dst_reg_sel <= 0;
ID_EX_ex_alu_op <= 0;
end
else begin
ID_EX_wb_reg_write <= wb_reg_write;
ID_EX_wb_mem_to_reg <= wb_mem_to_reg;
ID_EX_mem_read <= mem_read;
ID_EX_mem_write <= mem_write;
ID_EX_ex_imm_command <= ex_imm_command;
ID_EX_ex_alu_src_b <= ex_alu_src_b;
ID_EX_ex_alu_rslt_src <= ex_alu_rslt_src;
ID_EX_ex_dst_reg_sel <= ex_dst_reg_sel;
ID_EX_ex_alu_op <= ex_alu_op;
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4B_4_V
`define SKY130_FD_SC_HD__AND4B_4_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog wrapper for and4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4b_4 (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4b_4 (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4B_4_V
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: [email protected]
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: rx_lane_logic
*
*/
`default_nettype none
module rx_lane_logic #(
parameter DWIDTH = 512,
parameter NUM_LANES = 8,
parameter LANE_DWIDTH = (DWIDTH/NUM_LANES),
parameter CTRL_LANE_POLARITY = 1,
parameter BITSLIP_SHIFT_RIGHT= 1
) (
//----------------------------------
//----SYSTEM INTERFACE
//----------------------------------
input wire clk,
input wire res_n,
//----------------------------------
//----CONNECT
//----------------------------------
input wire [LANE_DWIDTH-1:0] scrambled_data_in,
input wire bit_slip, //bit slip per lane
input wire lane_polarity,
output wire [LANE_DWIDTH-1:0] descrambled_data_out,
output wire descrambler_locked,
input wire descrambler_disable
);
wire [LANE_DWIDTH-1:0] descrambled_data_out_tmp;
wire [LANE_DWIDTH-1:0] data_2_descrambler;
wire descrambler_locked_tmp;
assign descrambler_locked = descrambler_disable ? 1'b1 : descrambler_locked_tmp;
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------ACTUAL LOGIC STARTS HERE--------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
generate
if(CTRL_LANE_POLARITY==1) begin
reg [LANE_DWIDTH-1:0] scrambled_data_in_reg;
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
scrambled_data_in_reg <= {LANE_DWIDTH{1'b0}};
end
else begin
scrambled_data_in_reg <= scrambled_data_in^{LANE_DWIDTH{lane_polarity}};
end
end
assign data_2_descrambler = scrambled_data_in_reg;
assign descrambled_data_out = descrambler_disable ? scrambled_data_in_reg : descrambled_data_out_tmp;
end else begin
assign data_2_descrambler = scrambled_data_in;
assign descrambled_data_out = descrambler_disable ? scrambled_data_in : descrambled_data_out_tmp;
end
endgenerate
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
//Descrambler Init
rx_descrambler #(
.DWIDTH(LANE_DWIDTH),
.BITSLIP_SHIFT_RIGHT(BITSLIP_SHIFT_RIGHT)
) descrambler_I (
.clk(clk),
.res_n(res_n),
.bit_slip(bit_slip),
.locked(descrambler_locked_tmp),
.data_in(data_2_descrambler),
.data_out(descrambled_data_out_tmp)
);
endmodule
`default_nettype wire |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SEDFXTP_2_V
`define SKY130_FD_SC_HS__SEDFXTP_2_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog wrapper for sedfxtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sedfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sedfxtp_2 (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND
);
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
sky130_fd_sc_hs__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sedfxtp_2 (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SEDFXTP_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211OI_0_V
`define SKY130_FD_SC_LP__A211OI_0_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a211oi_0 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a211oi_0 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211OI_0_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:54:28 2016
/////////////////////////////////////////////////////////////
module GeAr_N8_R1_P3 ( in1, in2, res );
input [7:0] in1;
input [7:0] in2;
output [8:0] res;
wire n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38,
n39, n40, n41, n42, n43, n44, n45, n46, n47, n48;
CLKAND2X2TS U31 ( .A(in1[0]), .B(in2[0]), .Y(n42) );
OAI21XLTS U32 ( .A0(n37), .A1(n39), .B0(n36), .Y(n35) );
OAI21XLTS U33 ( .A0(n32), .A1(n39), .B0(n31), .Y(n29) );
OAI211XLTS U34 ( .A0(in1[2]), .A1(in2[2]), .B0(in1[1]), .C0(in2[1]), .Y(n33)
);
OAI21XLTS U35 ( .A0(n27), .A1(n34), .B0(n26), .Y(n25) );
AOI2BB1XLTS U36 ( .A0N(in1[0]), .A1N(in2[0]), .B0(n42), .Y(res[0]) );
NAND2X1TS U37 ( .A(in1[3]), .B(in2[3]), .Y(n38) );
INVX2TS U38 ( .A(n38), .Y(n27) );
NOR2X2TS U39 ( .A(in1[3]), .B(in2[3]), .Y(n34) );
OAI31X1TS U40 ( .A0(n27), .A1(n26), .A2(n34), .B0(n25), .Y(res[3]) );
NOR2X2TS U41 ( .A(in2[5]), .B(in1[5]), .Y(n47) );
AOI21X1TS U42 ( .A0(in1[5]), .A1(in2[5]), .B0(n47), .Y(n30) );
INVX2TS U43 ( .A(n34), .Y(n28) );
AOI31X1TS U44 ( .A0(in1[2]), .A1(in2[2]), .A2(n28), .B0(n27), .Y(n32) );
NOR2X2TS U45 ( .A(in2[4]), .B(in1[4]), .Y(n39) );
NAND2X1TS U46 ( .A(in2[4]), .B(in1[4]), .Y(n31) );
XOR2XLTS U47 ( .A(n30), .B(n29), .Y(res[5]) );
INVX2TS U48 ( .A(n31), .Y(n37) );
OAI21X1TS U49 ( .A0(n34), .A1(n33), .B0(n32), .Y(n36) );
OAI31X1TS U50 ( .A0(n37), .A1(n36), .A2(n39), .B0(n35), .Y(res[4]) );
NOR2X1TS U51 ( .A(in1[6]), .B(in2[6]), .Y(n45) );
AOI21X1TS U52 ( .A0(in1[6]), .A1(in2[6]), .B0(n45), .Y(n41) );
AOI21X1TS U53 ( .A0(in2[5]), .A1(in1[5]), .B0(n37), .Y(n46) );
OAI32X1TS U54 ( .A0(n47), .A1(n39), .A2(n38), .B0(n46), .B1(n47), .Y(n40) );
XOR2XLTS U55 ( .A(n41), .B(n40), .Y(res[6]) );
CMPR32X2TS U56 ( .A(in2[1]), .B(in1[1]), .C(n42), .CO(n43), .S(res[1]) );
CMPR32X2TS U57 ( .A(in1[2]), .B(in2[2]), .C(n43), .CO(n26), .S(res[2]) );
NAND2X1TS U58 ( .A(in1[6]), .B(in2[6]), .Y(n44) );
OAI31X1TS U59 ( .A0(n47), .A1(n46), .A2(n45), .B0(n44), .Y(n48) );
CMPR32X2TS U60 ( .A(in1[7]), .B(in2[7]), .C(n48), .CO(res[8]), .S(res[7]) );
initial $sdf_annotate("GeAr_N8_R1_P3_syn.sdf");
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DFSTP_BEHAVIORAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ms__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ms__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSTP_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08/14/2016 05:02:16 PM
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// select 300 DPI or 600 DPI mode
`define DPI_300
// `define DPI_600
// Period of CIS clock is equal to 60MHz/USB_CLK_DIV
// Must be an even number
`define USB_CLK_DIV 'd12
// Sample ADC 16.7ns before the next rising edge of CIS_CLK
`define ADC_CLK_DELAY (`USB_CLK_DIV/2)-1
// Issue write pulse immediately before next rising edge of ADC_CLK
// `define WR_PULSE_DELAY (`USB_CLK_DIV/2)-2
`define WR_PULSE_DELAY 4
// define the clock window when the LED needs to be off
`define CIS_LED_OFF 'd40
`define CIS_LED_ON 'd70
// define the clock cycle at which the oscilloscope should be triggered
`define SCOPE_SYNC_POS 'd1000
`ifdef DPI_300
`define CIS_CLK_PER_LINE 'd2700
`else
`define CIS_CLK_PER_LINE 'd5300
`endif
module top(
// Inputs from USB IC
input USB_CLK,
// Inputs from ADC
input [7:0] ADC_DATA,
// Outputs to CIS module
output CIS_MODE,
output reg CIS_CLK,
output reg CIS_SP,
output reg CIS_LED_BLUE,
output reg CIS_LED_GREEN,
output reg CIS_LED_RED,
// Outputs to USB IC
output [7:0] USB_DATA,
output reg USB_WR_L,
// Outputs to ADC
output reg ADC_CLK,
// Outputs to oscilloscope
output reg SCOPE_SYNC
);
// internal reg variables
reg [3:0] counter_usb_clk;
reg [12:0] counter_cis_clk;
// Set the DPI mode of the scanner
`ifdef DPI_300
assign CIS_MODE = 'b0;
`else
assign CIS_MODE = 'b1;
`endif
assign USB_DATA = ADC_DATA;
initial begin
// output initializations
USB_WR_L = 'b0;
CIS_CLK = 'b0;
CIS_SP = 'b1;
CIS_LED_BLUE = 'b1;
CIS_LED_GREEN = 'b1;
CIS_LED_RED = 'b1;
SCOPE_SYNC = 'b0;
// internal counter variables
counter_usb_clk = 'd1;
counter_cis_clk = 'd1;
end
// Generate the clock used to read out from the CIS module
// by dividing down the 60MHz clock
always @(posedge USB_CLK) begin
// Generate the CIS clock signal
if (0 <= counter_usb_clk && counter_usb_clk < (`USB_CLK_DIV/2)) begin
CIS_CLK <= 'b1;
end else begin
CIS_CLK <= 'b0;
end
// Generate the shifted ADC sampling clock
if (`ADC_CLK_DELAY <= counter_usb_clk && counter_usb_clk < (`ADC_CLK_DELAY+`USB_CLK_DIV/2)) begin
ADC_CLK <= 'b1;
end else begin
ADC_CLK <= 'b0;
end
// Increment the clock counter
if (counter_usb_clk == (`USB_CLK_DIV-1)) begin
counter_usb_clk <= 'd0;
end else begin
counter_usb_clk <= counter_usb_clk + 'd1;
end
end
always @(negedge USB_CLK) begin
if (counter_usb_clk == `WR_PULSE_DELAY) begin
USB_WR_L <= 'b0;
end else begin
USB_WR_L <= 'b1;
end
end
always @(posedge CIS_CLK) begin
// update LED settings
if (counter_cis_clk == `CIS_LED_OFF) begin
CIS_LED_BLUE <= 'b0;
CIS_LED_GREEN <= 'b0;
CIS_LED_RED <= 'b0;
end else if (counter_cis_clk == `CIS_LED_ON) begin
CIS_LED_BLUE <= 'b1;
CIS_LED_GREEN <= 'b1;
CIS_LED_RED <= 'b1;
end
// update CIS counter
if (counter_cis_clk == `CIS_CLK_PER_LINE) begin
counter_cis_clk <= 'd1;
CIS_SP <= 'b1;
end else begin
counter_cis_clk <= counter_cis_clk + 'd1;
CIS_SP <= 'b0;
end
// update SCOPE_SYNC signal
if (counter_cis_clk == `SCOPE_SYNC_POS) begin
SCOPE_SYNC <= 1'b1;
end else begin
SCOPE_SYNC <= 1'b0;
end
end
endmodule
|
//==================================================================================================
// Filename : memory.v
// Created On : 2014-09-28 20:35:52
// Last Modified : 2015-05-31 21:18:35
// Revision :
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : Dual-port memory
//==================================================================================================
`include "musb_defines.v"
module memory#(
parameter addr_size = 8 // Default: 256 words/1 KB
)(
input clk,
input rst,
//port A
input [addr_size-1:0] a_addr, // Address
input [31:0] a_din, // Data input
input [3:0] a_wr, // Write/Read
input a_enable, // Valid operation
output reg [31:0] a_dout, // Data output
output reg a_ready, // Data output ready (valid)
// port B
input [addr_size-1:0] b_addr, // Address
input [31:0] b_din, // Data input
input [3:0] b_wr, // Write/Read
input b_enable, // Valid operation
output reg [31:0] b_dout, // Data output
output reg b_ready // Data output ready (valid)
);
//--------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg [31:0] a_data_out;
reg [31:0] b_data_out;
//--------------------------------------------------------------------------
// Set the ready signal
//--------------------------------------------------------------------------
always @(posedge clk) begin
a_ready <= (rst) ? 1'b0 : a_enable;
b_ready <= (rst) ? 1'b0 : b_enable;
end
//--------------------------------------------------------------------------
// assigment
//--------------------------------------------------------------------------
always @(*) begin
a_dout <= (a_ready) ? a_data_out : 32'bz;
b_dout <= (b_ready) ? b_data_out : 32'bz;
end
//--------------------------------------------------------------------------
// inicializar memoria
//--------------------------------------------------------------------------
reg [31:0] mem [0:(2**addr_size)-1];
initial begin
$readmemh("mem.hex", mem);
end
//--------------------------------------------------------------------------
// Port A
//--------------------------------------------------------------------------
always @(posedge clk) begin
a_data_out <= mem[a_addr];
if(a_wr) begin
a_data_out <= a_din;
mem[a_addr][7:0] <= (a_wr[0] & a_enable) ? a_din[7:0] : mem[a_addr][7:0];
mem[a_addr][15:8] <= (a_wr[1] & a_enable) ? a_din[15:8] : mem[a_addr][15:8];
mem[a_addr][23:16] <= (a_wr[2] & a_enable) ? a_din[23:16] : mem[a_addr][23:16];
mem[a_addr][31:24] <= (a_wr[3] & a_enable) ? a_din[31:24] : mem[a_addr][31:24];
end
end
//--------------------------------------------------------------------------
// Port B
//--------------------------------------------------------------------------
always @(posedge clk) begin
b_data_out <= mem[b_addr];
if(b_wr) begin
b_data_out <= b_din;
mem[b_addr][7:0] <= (b_wr[0] & b_enable) ? b_din[7:0] : mem[b_addr][7:0];
mem[b_addr][15:8] <= (b_wr[1] & b_enable) ? b_din[15:8] : mem[b_addr][15:8];
mem[b_addr][23:16] <= (b_wr[2] & b_enable) ? b_din[23:16] : mem[b_addr][23:16];
mem[b_addr][31:24] <= (b_wr[3] & b_enable) ? b_din[31:24] : mem[b_addr][31:24];
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKBUF_PP_SYMBOL_V
`define SKY130_FD_SC_HS__CLKBUF_PP_SYMBOL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkbuf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKBUF_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4_SYMBOL_V
`define SKY130_FD_SC_HS__NAND4_SYMBOL_V
/**
* nand4: 4-input NAND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4_SYMBOL_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: iop.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
`include "sys.h"
`include "iop.h"
module OpenSPARCT1 (/*AUTOARG*/
// Outputs
DRAM0_RAS_L, DRAM0_CAS_L, DRAM0_WE_L, DRAM0_CS_L, DRAM0_CKE,
DRAM0_ADDR, DRAM0_BA, DRAM0_CK_P, DRAM0_CK_N, DRAM1_RAS_L,
DRAM1_CAS_L, DRAM1_WE_L, DRAM1_CS_L, DRAM1_CKE, DRAM1_ADDR,
DRAM1_BA, DRAM1_CK_P, DRAM1_CK_N, DRAM2_RAS_L, DRAM2_CAS_L,
DRAM2_WE_L, DRAM2_CS_L, DRAM2_CKE, DRAM2_ADDR, DRAM2_BA,
DRAM2_CK_P, DRAM2_CK_N, DRAM3_RAS_L, DRAM3_CAS_L, DRAM3_WE_L,
DRAM3_CS_L, DRAM3_CKE, DRAM3_ADDR, DRAM3_BA, DRAM3_CK_P,
DRAM3_CK_N, J_PACK0, J_PACK1, J_REQ0_OUT_L, J_REQ1_OUT_L, J_ERR,
TSR_TESTIO, TDO,
// Inouts
DRAM0_DQ, DRAM0_CB, DRAM0_DQS, SPARE_DDR0_PIN, DRAM1_DQ, DRAM1_CB,
DRAM1_DQS, CLKOBS, SPARE_DDR1_PIN, DRAM2_DQ, DRAM2_CB, DRAM2_DQS,
SPARE_DDR2_PIN, DRAM3_DQ, DRAM3_CB, DRAM3_DQS, SPARE_DDR3_PIN,
J_AD, J_ADP, J_ADTYPE, SPARE_JBUSR_PIN, DBG_DQ, DBG_CK_P,
DBG_CK_N, VDDA, VDDBO, VDDCO, VDDTO, VDDL18, VDDR18, DIODE_TOP,
DIODE_BOT, VPP, SSI_MISO, SSI_MOSI, SSI_SCK, PMO, VDD_SENSE,
VSS_SENSE, SPARE_MISC_PIN, SPARE_MISC_PAD, SPARE_DDR0_PAD,
SPARE_DDR1_PAD, SPARE_DDR2_PAD, SPARE_DDR3_PAD, SPARE_DBG_PAD,
// Inputs
DRAM01_P_REF_RES, DRAM01_N_REF_RES, DRAM23_P_REF_RES,
DRAM23_N_REF_RES, J_PAR, J_PACK4, J_PACK5, J_REQ4_IN_L,
J_REQ5_IN_L, J_RST_L, DTL_L_VREF, DTL_R_VREF, JBUS_P_REF_RES,
JBUS_N_REF_RES, DBG_VREF, J_CLK, TCK, TCK2, TRST_L, TDI, TMS,
TEST_MODE, TEMP_TRIG, PWRON_RST_L, CLK_STRETCH, DO_BIST,
EXT_INT_L, BURNIN, PMI, PGRM_EN, PLL_CHAR_IN, VREG_SELBG_L,
TRIGIN, HSTL_VREF
);
output DRAM0_RAS_L; // From pad_ddr0 of pad_ddr0.v
output DRAM0_CAS_L; // From pad_ddr0 of pad_ddr0.v
output DRAM0_WE_L; // From pad_ddr0 of pad_ddr0.v
output [3:0] DRAM0_CS_L; // From pad_ddr0 of pad_ddr0.v
output DRAM0_CKE; // From pad_ddr0 of pad_ddr0.v
output [14:0] DRAM0_ADDR; // From pad_ddr0 of pad_ddr0.v
output [2:0] DRAM0_BA; // From pad_ddr0 of pad_ddr0.v
inout [127:0] DRAM0_DQ; // To/From pad_ddr0 of pad_ddr0.v
inout [15:0] DRAM0_CB; // To/From pad_ddr0 of pad_ddr0.v
inout [35:0] DRAM0_DQS; // To/From pad_ddr0 of pad_ddr0.v
output [3:0] DRAM0_CK_P; // From pad_ddr0 of pad_ddr0.v
output [3:0] DRAM0_CK_N; // From pad_ddr0 of pad_ddr0.v
input DRAM01_P_REF_RES; // To pad_ddr0 of pad_ddr0.v
input DRAM01_N_REF_RES; // To pad_ddr0 of pad_ddr0.v
inout SPARE_DDR0_PIN; // To/From pad_ddr0 of pad_ddr0.v
output DRAM1_RAS_L; // From pad_ddr1 of pad_ddr1.v
output DRAM1_CAS_L; // From pad_ddr1 of pad_ddr1.v
output DRAM1_WE_L; // From pad_ddr1 of pad_ddr1.v
output [3:0] DRAM1_CS_L; // From pad_ddr1 of pad_ddr1.v
output DRAM1_CKE; // From pad_ddr1 of pad_ddr1.v
output [14:0] DRAM1_ADDR; // From pad_ddr1 of pad_ddr1.v
output [2:0] DRAM1_BA; // From pad_ddr1 of pad_ddr1.v
inout [127:0] DRAM1_DQ; // To/From pad_ddr1 of pad_ddr1.v
inout [15:0] DRAM1_CB; // To/From pad_ddr1 of pad_ddr1.v
inout [35:0] DRAM1_DQS; // To/From pad_ddr1 of pad_ddr1.v
output [3:0] DRAM1_CK_P; // From pad_ddr1 of pad_ddr1.v
output [3:0] DRAM1_CK_N; // From pad_ddr1 of pad_ddr1.v
input DRAM23_P_REF_RES; // To pad_ddr1 of pad_ddr1.v
input DRAM23_N_REF_RES; // To pad_ddr1 of pad_ddr1.v
inout [1:0] CLKOBS; // From pad_ddr1 of pad_ddr1.v
inout [2:0] SPARE_DDR1_PIN; // To/From pad_ddr1 of pad_ddr1.v
output DRAM2_RAS_L; // From pad_ddr2 of pad_ddr2.v
output DRAM2_CAS_L; // From pad_ddr2 of pad_ddr2.v
output DRAM2_WE_L; // From pad_ddr2 of pad_ddr2.v
output [3:0] DRAM2_CS_L; // From pad_ddr2 of pad_ddr2.v
output DRAM2_CKE; // From pad_ddr2 of pad_ddr2.v
output [14:0] DRAM2_ADDR; // From pad_ddr2 of pad_ddr2.v
output [2:0] DRAM2_BA; // From pad_ddr2 of pad_ddr2.v
inout [127:0] DRAM2_DQ; // To/From pad_ddr2 of pad_ddr2.v
inout [15:0] DRAM2_CB; // To/From pad_ddr2 of pad_ddr2.v
inout [35:0] DRAM2_DQS; // To/From pad_ddr2 of pad_ddr2.v
output [3:0] DRAM2_CK_P; // From pad_ddr2 of pad_ddr2.v
output [3:0] DRAM2_CK_N; // From pad_ddr2 of pad_ddr2.v
inout [2:0] SPARE_DDR2_PIN; // To/From pad_ddr2 of pad_ddr2.v
output DRAM3_RAS_L; // From pad_ddr3 of pad_ddr3.v
output DRAM3_CAS_L; // From pad_ddr3 of pad_ddr3.v
output DRAM3_WE_L; // From pad_ddr3 of pad_ddr3.v
output [3:0] DRAM3_CS_L; // From pad_ddr3 of pad_ddr3.v
output DRAM3_CKE; // From pad_ddr3 of pad_ddr3.v
output [14:0] DRAM3_ADDR; // From pad_ddr3 of pad_ddr3.v
output [2:0] DRAM3_BA; // From pad_ddr3 of pad_ddr3.v
inout [127:0] DRAM3_DQ; // To/From pad_ddr3 of pad_ddr3.v
inout [15:0] DRAM3_CB; // To/From pad_ddr3 of pad_ddr3.v
inout [35:0] DRAM3_DQS; // To/From pad_ddr3 of pad_ddr3.v
output [3:0] DRAM3_CK_P; // From pad_ddr3 of pad_ddr3.v
output [3:0] DRAM3_CK_N; // From pad_ddr3 of pad_ddr3.v
inout [2:0] SPARE_DDR3_PIN; // To/From pad_ddr3 of pad_ddr3.v
inout [127:0] J_AD; // To/From pad_jbusl/r of pad_jbusl/r.v
inout [3:0] J_ADP; // To/From pad_jbusr of pad_jbusr.v
inout [7:0] J_ADTYPE; // To/From pad_jbusr of pad_jbusr.v
input J_PAR; // To/From pad_jbusr of pad_jbusr.v
output [2:0] J_PACK0; // From pad_jbusr of pad_jbusr.v
output [2:0] J_PACK1; // From pad_jbusr of pad_jbusr.v
input [2:0] J_PACK4; // To pad_jbusr of pad_jbusr.v
input [2:0] J_PACK5; // To pad_jbusr of pad_jbusr.v
output J_REQ0_OUT_L; // From pad_jbusr of pad_jbusr.v
output J_REQ1_OUT_L; // From pad_jbusr of pad_jbusr.v
input J_REQ4_IN_L; // To pad_jbusr of pad_jbusr.v
input J_REQ5_IN_L; // To pad_jbusr of pad_jbusr.v
output J_ERR; // From pad_jbusr of pad_jbusr.v
input J_RST_L; // To pad_jbusr of pad_jbusr.v
input DTL_L_VREF; // To pad_jbusl of pad_jbusl.v
input DTL_R_VREF; // To pad_jbusr of pad_jbusr.v
input JBUS_P_REF_RES; // To pad_jbusr of pad_jbusr.v
input JBUS_N_REF_RES; // To pad_jbusr of pad_jbusr.v
inout [0:0] SPARE_JBUSR_PIN; // To/From pad_jbusr of pad_jbusr.v
inout [39:0] DBG_DQ; // From pad_dbg of pad_jbusl.v
inout [2:0] DBG_CK_P; // From pad_dbg of pad_jbusl.v
inout [2:0] DBG_CK_N; // From pad_dbg of pad_jbusl.v
input DBG_VREF; // To pad_dbg of pad_jbusl.v
input [1:0] J_CLK; // To pad_ctu of pad_ctu.v
output [1:0] TSR_TESTIO; // From pad_ctu of pad_ctu.v
inout VDDA; //
inout VDDBO; //
inout VDDCO; //
inout VDDTO; //
inout VDDL18; // Left side - ddr0 and ddr1.
inout VDDR18; // Right side - ddr2 anbd ddr3.
inout [2:0] DIODE_TOP; // From pad_diode0 of pad_diode.v
inout [2:0] DIODE_BOT; // From pad_diode1 of pad_diode.v
inout VPP; // To/From pad_efc of pad_efc.v
input TCK; // To pad_misc of pad_misc.v
input TCK2; // To pad_misc of pad_misc.v
input TRST_L; // To pad_misc of pad_misc.v
input TDI; // To pad_misc of pad_misc.v
output TDO; // From pad_misc of pad_misc.v
input TMS; // To pad_misc of pad_misc.v
input TEST_MODE; // To pad_misc of pad_misc.v
input TEMP_TRIG; // To pad_misc of pad_misc.v
input PWRON_RST_L; // To pad_misc of pad_misc.v
inout SSI_MISO; // To pad_misc of pad_misc.v
inout SSI_MOSI; // From pad_misc of pad_misc.v
inout SSI_SCK; // From pad_misc of pad_misc.v
input CLK_STRETCH; // To pad_misc of pad_misc.v
input DO_BIST; // To pad_misc of pad_misc.v
input EXT_INT_L; // To pad_misc of pad_misc.v
input BURNIN; // To pad_misc of pad_misc.v
input PMI; // To pad_misc of pad_misc.v
inout PMO; // From pad_misc of pad_misc.v
input PGRM_EN; // To pad_misc of pad_misc.v
input PLL_CHAR_IN; // To pad_misc of pad_misc.v
input VREG_SELBG_L; // To pad_misc of pad_misc.v
input TRIGIN; // To pad_misc of pad_misc.v
inout VDD_SENSE; // From pad_misc of pad_misc.v
inout VSS_SENSE; // From pad_misc of pad_misc.v
input HSTL_VREF; // To pad_misc of pad_misc.v
inout SPARE_MISC_PIN; // To/From pad_misc of pad_misc.v
inout [2:0] SPARE_MISC_PAD; // To/From pad_misc of pad_misc.v
inout [6:0] SPARE_DDR0_PAD; // To/From pad_ddr0 of pad_ddr0.v
inout [6:0] SPARE_DDR1_PAD; // To/From pad_ddr1 of pad_ddr1.v
inout [6:0] SPARE_DDR2_PAD; // To/From pad_ddr2 of pad_ddr2.v
inout [6:0] SPARE_DDR3_PAD; // To/From pad_ddr3 of pad_ddr3.v
inout [23:0] SPARE_DBG_PAD; // To/From pad_dbg of pad_jbusl.v
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire afi_bist_mode; // To/From v_m_help of v_m_help.v
wire afi_bypass_mode; // To/From v_m_help of v_m_help.v
wire afi_pll_char_mode; // To/From v_m_help of v_m_help.v
wire afi_pll_clamp_fltr; // To/From v_m_help of v_m_help.v
wire [5:0] afi_pll_div2; // To/From v_m_help of v_m_help.v
wire afi_pll_trst_l; // To/From v_m_help of v_m_help.v
wire [2:0] afi_rng_ctl; // To/From v_m_help of v_m_help.v
wire afi_rt_addr_data; // To/From v_m_help of v_m_help.v
wire [31:0] afi_rt_data_in; // To/From v_m_help of v_m_help.v
wire afi_rt_high_low; // To/From v_m_help of v_m_help.v
wire afi_rt_read_write; // To/From v_m_help of v_m_help.v
wire afi_rt_valid; // To/From v_m_help of v_m_help.v
wire [9:1] afi_tsr_div; // To/From v_m_help of v_m_help.v
wire afi_tsr_mode; // To/From v_m_help of v_m_help.v
wire [7:0] afi_tsr_tsel; // To/From v_m_help of v_m_help.v
wire afo_rng_clk; // To/From v_m_help of v_m_help.v, ...
wire afo_rng_data; // To/From v_m_help of v_m_help.v, ...
wire afo_rt_ack; // To/From v_m_help of v_m_help.v, ...
wire [31:0] afo_rt_data_out; // To/From v_m_help of v_m_help.v, ...
wire [7:0] afo_tsr_dout; // To/From v_m_help of v_m_help.v, ...
wire ccx_rclk; // From ccx of ccx.v
wire [`CLK_IOB_WIDTH-1:0]clsp_iob_data; // From ctu of ctu.v
wire clsp_iob_stall; // From ctu of ctu.v
wire clsp_iob_vld; // From ctu of ctu.v
wire cmp_adbginit_l; // From ctu of ctu.v
wire cmp_arst_l; // From ctu of ctu.v
wire cmp_gclk; // From ctu of ctu.v
wire [7:0] cmp_gclk_c0_r; // From bw_clk_gl of bw_clk_gl.v
wire [7:0] cmp_gclk_c1_r; // From bw_clk_gl of bw_clk_gl.v
wire [7:0] cmp_gclk_c2_r; // From bw_clk_gl of bw_clk_gl.v
wire [7:0] cmp_gclk_c3_r; // From bw_clk_gl of bw_clk_gl.v
wire cmp_gdbginit_out_l; // From ctu of ctu.v
wire cmp_grst_out_l; // From ctu of ctu.v
wire [7:0] cpx_iob_grant_cx2; // To/From v_m_help of v_m_help.v, ...
wire [7:0] cpx_sctag0_grant_cx; // To/From v_m_help of v_m_help.v, ...
wire [7:0] cpx_sctag1_grant_cx; // To/From v_m_help of v_m_help.v, ...
wire [7:0] cpx_sctag2_grant_cx; // To/From v_m_help of v_m_help.v, ...
wire [7:0] cpx_sctag3_grant_cx; // To/From v_m_help of v_m_help.v, ...
wire [`CPX_WIDTH-1:0]cpx_spc0_data_cx2; // From ccx of ccx.v
wire [`CPX_WIDTH-1:0]cpx_spc0_data_cx2_buf1; // From ccx_spc_rpt0 of ccx_spc_rpt.v
wire cpx_spc0_data_rdy_cx2; // From ccx of ccx.v
wire cpx_spc0_data_rdy_cx2_buf1;// From ccx_spc_rpt0 of ccx_spc_rpt.v
wire [`CPX_WIDTH-1:0]cpx_spc1_data_cx2; // From ccx of ccx.v
wire [`CPX_WIDTH-1:0]cpx_spc1_data_cx2_buf1; // From ccx_spc_rpt1 of ccx_spc_rpt.v
wire cpx_spc1_data_rdy_cx2; // From ccx of ccx.v
wire cpx_spc1_data_rdy_cx2_buf1;// From ccx_spc_rpt1 of ccx_spc_rpt.v
wire [`CPX_WIDTH-1:0]cpx_spc2_data_cx2; // From ccx of ccx.v
wire [`CPX_WIDTH-1:0]cpx_spc2_data_cx2_buf1; // From ccx_spc_rpt2 of ccx_spc_rpt.v
wire cpx_spc2_data_rdy_cx2; // From ccx of ccx.v
wire cpx_spc2_data_rdy_cx2_buf1;// From ccx_spc_rpt2 of ccx_spc_rpt.v
wire [`CPX_WIDTH-1:0]cpx_spc3_data_cx2; // From ccx of ccx.v
wire [`CPX_WIDTH-1:0]cpx_spc3_data_cx2_buf1; // From ccx_spc_rpt3 of ccx_spc_rpt.v
wire cpx_spc3_data_rdy_cx2; // From ccx of ccx.v
wire cpx_spc3_data_rdy_cx2_buf1;// From ccx_spc_rpt3 of ccx_spc_rpt.v
wire [`CPX_WIDTH-1:0]cpx_spc4_data_cx2; // From ccx of ccx.v
wire [`CPX_WIDTH-1:0]cpx_spc4_data_cx2_buf1; // From ccx_spc_rpt4 of ccx_spc_rpt.v
wire cpx_spc4_data_rdy_cx2; // From ccx of ccx.v
wire cpx_spc4_data_rdy_cx2_buf1;// From ccx_spc_rpt4 of ccx_spc_rpt.v
wire [`CPX_WIDTH-1:0]cpx_spc5_data_cx2; // From ccx of ccx.v
wire [`CPX_WIDTH-1:0]cpx_spc5_data_cx2_buf1; // From ccx_spc_rpt5 of ccx_spc_rpt.v
wire cpx_spc5_data_rdy_cx2; // From ccx of ccx.v
wire cpx_spc5_data_rdy_cx2_buf1;// From ccx_spc_rpt5 of ccx_spc_rpt.v
wire [`CPX_WIDTH-1:0]cpx_spc6_data_cx2; // From ccx of ccx.v
wire [`CPX_WIDTH-1:0]cpx_spc6_data_cx2_buf1; // From ccx_spc_rpt6 of ccx_spc_rpt.v
wire cpx_spc6_data_rdy_cx2; // From ccx of ccx.v
wire cpx_spc6_data_rdy_cx2_buf1;// From ccx_spc_rpt6 of ccx_spc_rpt.v
wire [`CPX_WIDTH-1:0]cpx_spc7_data_cx2; // From ccx of ccx.v
wire [`CPX_WIDTH-1:0]cpx_spc7_data_cx2_buf1; // From ccx_spc_rpt7 of ccx_spc_rpt.v
wire cpx_spc7_data_rdy_cx2; // From ccx of ccx.v
wire cpx_spc7_data_rdy_cx2_buf1;// From ccx_spc_rpt7 of ccx_spc_rpt.v
wire ctu_ccx_cmp_cken; // From ctu of ctu.v
wire ctu_dbg_jbus_cken; // From ctu of ctu.v
wire ctu_ddr0_clock_dr; // From ctu of ctu.v
wire [2:0] ctu_ddr0_dll_delayctr; // From ctu of ctu.v
wire ctu_ddr0_dram_cken; // From ctu of ctu.v
wire ctu_ddr0_hiz_l; // From ctu of ctu.v
wire ctu_ddr0_iodll_rst_l; // From ctu of ctu.v
wire ctu_ddr0_mode_ctl; // From ctu of ctu.v
wire ctu_ddr0_shift_dr; // From ctu of ctu.v
wire ctu_ddr0_update_dr; // From ctu of ctu.v
wire ctu_ddr1_bso; // From ctu of ctu.v
wire ctu_ddr1_clock_dr; // From ctu of ctu.v
wire [2:0] ctu_ddr1_dll_delayctr; // From ctu of ctu.v
wire ctu_ddr1_dram_cken; // From ctu of ctu.v
wire ctu_ddr1_hiz_l; // From ctu of ctu.v
wire ctu_ddr1_iodll_rst_l; // From ctu of ctu.v
wire ctu_ddr1_mode_ctl; // From ctu of ctu.v
wire ctu_ddr1_shift_dr; // From ctu of ctu.v
wire ctu_ddr1_update_dr; // From ctu of ctu.v
wire ctu_ddr2_clock_dr; // From ctu of ctu.v
wire [2:0] ctu_ddr2_dll_delayctr; // From ctu of ctu.v
wire ctu_ddr2_dram_cken; // From ctu of ctu.v
wire ctu_ddr2_hiz_l; // From ctu of ctu.v
wire ctu_ddr2_iodll_rst_l; // From ctu of ctu.v
wire ctu_ddr2_mode_ctl; // From ctu of ctu.v
wire ctu_ddr2_shift_dr; // From ctu of ctu.v
wire ctu_ddr2_update_dr; // From ctu of ctu.v
wire ctu_ddr3_clock_dr; // From ctu of ctu.v
wire [2:0] ctu_ddr3_dll_delayctr; // From ctu of ctu.v
wire ctu_ddr3_dram_cken; // From ctu of ctu.v
wire ctu_ddr3_hiz_l; // From ctu of ctu.v
wire ctu_ddr3_iodll_rst_l; // From ctu of ctu.v
wire ctu_ddr3_mode_ctl; // From ctu of ctu.v
wire ctu_ddr3_shift_dr; // From ctu of ctu.v
wire ctu_ddr3_update_dr; // From ctu of ctu.v
wire ctu_ddr_testmode_l; // From ctu of ctu.v
wire ctu_debug_clock_dr; // From ctu of ctu.v
wire ctu_debug_hiz_l; // From ctu of ctu.v
wire ctu_debug_mode_ctl; // From ctu of ctu.v
wire ctu_debug_shift_dr; // From ctu of ctu.v
wire ctu_debug_update_dr; // From ctu of ctu.v
wire ctu_dll0_byp_l; // From ctu of ctu.v
wire [4:0] ctu_dll0_byp_val; // From ctu of ctu.v
wire [4:0] ctu_dll0_ctu_ctrl; // From pad_ddr0 of pad_ddr0.v
wire ctu_dll1_byp_l; // From ctu of ctu.v
wire [4:0] ctu_dll1_byp_val; // From ctu of ctu.v
wire [4:0] ctu_dll1_ctu_ctrl; // From pad_ddr1 of pad_ddr1.v
wire ctu_dll2_byp_l; // From ctu of ctu.v
wire [4:0] ctu_dll2_byp_val; // From ctu of ctu.v
wire [4:0] ctu_dll2_ctu_ctrl; // From pad_ddr2 of pad_ddr2.v
wire ctu_dll3_byp_l; // From ctu of ctu.v
wire [4:0] ctu_dll3_byp_val; // From ctu of ctu.v
wire [4:0] ctu_dll3_ctu_ctrl; // From pad_ddr3 of pad_ddr3.v
wire ctu_dram02_cmp_cken; // From ctu of ctu.v
wire ctu_dram02_dram_cken; // From ctu of ctu.v
wire ctu_dram02_jbus_cken; // From ctu of ctu.v
wire ctu_dram13_cmp_cken; // From ctu of ctu.v
wire ctu_dram13_dram_cken; // From ctu of ctu.v
wire ctu_dram13_jbus_cken; // From ctu of ctu.v
wire ctu_dram_rx_sync_out; // From ctu of ctu.v
wire ctu_dram_selfrsh; // From ctu of ctu.v
wire ctu_dram_tx_sync_out; // From ctu of ctu.v
wire ctu_efc_capturedr; // From ctu of ctu.v
wire [4:0] ctu_efc_coladdr; // From ctu of ctu.v
wire ctu_efc_data_in; // From ctu of ctu.v
wire ctu_efc_dest_sample; // From ctu of ctu.v
wire ctu_efc_fuse_bypass; // From ctu of ctu.v
wire ctu_efc_jbus_cken; // From ctu of ctu.v
wire ctu_efc_read_en; // From ctu of ctu.v
wire [2:0] ctu_efc_read_mode; // From ctu of ctu.v
wire ctu_efc_read_start; // From ctu of ctu.v
wire [6:0] ctu_efc_rowaddr; // From ctu of ctu.v
wire ctu_efc_shiftdr; // From ctu of ctu.v
wire ctu_efc_tck; // From ctu of ctu.v
wire ctu_efc_updatedr; // From ctu of ctu.v
wire ctu_fpu_cmp_cken; // From ctu of ctu.v
wire ctu_global_snap; // From ctu of ctu.v
wire [1:0] ctu_io_clkobs; // From ctu of ctu.v
wire ctu_io_j_err; // From ctu of ctu.v
wire ctu_io_tdo; // From ctu of ctu.v
wire ctu_io_tdo_en; // From ctu of ctu.v
wire ctu_iob_cmp_cken; // From ctu of ctu.v
wire ctu_iob_jbus_cken; // From ctu of ctu.v
wire [2:0] ctu_iob_resetstat; // From ctu of ctu.v
wire ctu_iob_resetstat_wr; // From ctu of ctu.v
wire ctu_iob_wake_thr; // From ctu of ctu.v
wire ctu_jbi_cmp_cken; // From ctu of ctu.v
wire ctu_jbi_jbus_cken; // From ctu of ctu.v
wire ctu_jbi_ssiclk; // From ctu of ctu.v
wire ctu_jbus_rx_sync_out; // From ctu of ctu.v
wire ctu_jbus_tx_sync_out; // From ctu of ctu.v
wire ctu_jbusl_clock_dr; // From ctu of ctu.v
wire ctu_jbusl_hiz_l; // From ctu of ctu.v
wire ctu_jbusl_jbus_cken; // From ctu of ctu.v
wire ctu_jbusl_mode_ctl; // From ctu of ctu.v
wire ctu_jbusl_shift_dr; // From ctu of ctu.v
wire ctu_jbusl_update_dr; // From ctu of ctu.v
wire ctu_jbusr_clock_dr; // From ctu of ctu.v
wire ctu_jbusr_hiz_l; // From ctu of ctu.v
wire ctu_jbusr_jbus_cken; // From ctu of ctu.v
wire ctu_jbusr_mode_ctl; // From ctu of ctu.v
wire ctu_jbusr_shift_dr; // From ctu of ctu.v
wire ctu_jbusr_update_dr; // From ctu of ctu.v
wire ctu_misc_clock_dr; // From ctu of ctu.v
wire ctu_misc_hiz_l; // From ctu of ctu.v
wire ctu_misc_jbus_cken; // From ctu of ctu.v
wire ctu_misc_mode_ctl; // From ctu of ctu.v
wire ctu_misc_shift_dr; // From ctu of ctu.v
wire ctu_misc_update_dr; // From ctu of ctu.v
wire ctu_pads_sscan_update; // From ctu of ctu.v
wire ctu_rtop2_so; // From ctu of ctu.v
wire ctu_scdata0_cmp_cken; // From ctu of ctu.v
wire ctu_scdata1_cmp_cken; // From ctu of ctu.v
wire ctu_scdata2_cmp_cken; // From ctu of ctu.v
wire ctu_scdata3_cmp_cken; // From ctu of ctu.v
wire ctu_sctag0_cmp_cken; // From ctu of ctu.v
wire ctu_sctag0_mbisten; // To/From v_m_help of v_m_help.v, ...
wire ctu_sctag0_mbisten_buf2;// To/From v_m_help of v_m_help.v, ...
wire ctu_sctag1_cmp_cken; // From ctu of ctu.v
wire ctu_sctag1_mbisten; // To/From v_m_help of v_m_help.v, ...
wire ctu_sctag1_mbisten_buf2;// To/From v_m_help of v_m_help.v, ...
wire ctu_sctag2_cmp_cken; // From ctu of ctu.v
wire ctu_sctag2_mbisten; // To/From v_m_help of v_m_help.v, ...
wire ctu_sctag2_mbisten_buf2;// To/From v_m_help of v_m_help.v, ...
wire ctu_sctag3_cmp_cken; // From ctu of ctu.v
wire ctu_sctag3_mbisten; // To/From v_m_help of v_m_help.v, ...
wire ctu_sctag3_mbisten_buf2;// To/From v_m_help of v_m_help.v, ...
wire ctu_spc0_cmp_cken; // From ctu of ctu.v
wire ctu_spc0_mbisten; // To/From v_m_help of v_m_help.v, ...
wire ctu_spc0_mbisten_buf2; // To/From v_m_help of v_m_help.v, ...
wire ctu_spc0_sscan_se; // From ctu of ctu.v
wire ctu_spc0_tck; // From ctu of ctu.v
wire ctu_spc1_cmp_cken; // From ctu of ctu.v
wire ctu_spc1_mbisten; // To/From v_m_help of v_m_help.v, ...
wire ctu_spc1_mbisten_buf2; // To/From v_m_help of v_m_help.v, ...
wire ctu_spc1_sscan_se; // From ctu of ctu.v
wire ctu_spc1_tck; // From ctu of ctu.v
wire ctu_spc2_cmp_cken; // From ctu of ctu.v
wire ctu_spc2_mbisten; // To/From v_m_help of v_m_help.v, ...
wire ctu_spc2_mbisten_buf2; // To/From v_m_help of v_m_help.v, ...
wire ctu_spc2_sscan_se; // From ctu of ctu.v
wire ctu_spc2_tck; // From ctu of ctu.v
wire ctu_spc3_cmp_cken; // From ctu of ctu.v
wire ctu_spc3_mbisten; // To/From v_m_help of v_m_help.v, ...
wire ctu_spc3_mbisten_buf2; // To/From v_m_help of v_m_help.v, ...
wire ctu_spc3_sscan_se; // From ctu of ctu.v
wire ctu_spc3_tck; // From ctu of ctu.v
wire ctu_spc4_cmp_cken; // From ctu of ctu.v
wire ctu_spc4_mbisten; // To/From v_m_help of v_m_help.v, ...
wire ctu_spc4_mbisten_buf2; // To/From v_m_help of v_m_help.v, ...
wire ctu_spc4_sscan_se; // From ctu of ctu.v
wire ctu_spc4_tck; // From ctu of ctu.v
wire ctu_spc5_cmp_cken; // From ctu of ctu.v
wire ctu_spc5_mbisten; // To/From v_m_help of v_m_help.v, ...
wire ctu_spc5_mbisten_buf2; // To/From v_m_help of v_m_help.v, ...
wire ctu_spc5_sscan_se; // From ctu of ctu.v
wire ctu_spc5_tck; // From ctu of ctu.v
wire ctu_spc6_cmp_cken; // From ctu of ctu.v
wire ctu_spc6_mbisten; // To/From v_m_help of v_m_help.v, ...
wire ctu_spc6_mbisten_buf2; // To/From v_m_help of v_m_help.v, ...
wire ctu_spc6_sscan_se; // From ctu of ctu.v
wire ctu_spc6_tck; // From ctu of ctu.v
wire ctu_spc7_cmp_cken; // From ctu of ctu.v
wire ctu_spc7_mbisten; // To/From v_m_help of v_m_help.v, ...
wire ctu_spc7_mbisten_buf2; // To/From v_m_help of v_m_help.v, ...
wire ctu_spc7_sscan_se; // From ctu of ctu.v
wire ctu_spc7_tck; // From ctu of ctu.v
wire [7:0] ctu_spc_const_maskid; // From ctu of ctu.v
wire [3:0] ctu_spc_sscan_tid; // From ctu of ctu.v
wire ctu_tst_macrotest; // From ctu of ctu.v
wire ctu_tst_pre_grst_l; // From ctu of ctu.v
wire ctu_tst_scan_disable; // From ctu of ctu.v
wire ctu_tst_scanmode; // From ctu of ctu.v
wire ctu_tst_short_chain; // From ctu of ctu.v
wire dbg_ddr0_bso; // From pad_dbg of pad_jbusl.v
wire dbg_en_01; // From sc_0_1_dbg_rptr of sc_0_1_dbg_rptr.v
wire dbg_en_23; // From sc_2_3_dbg_rptr of sc_2_3_dbg_rptr.v
wire ddr0_ctu_bso; // From pad_ddr0 of pad_ddr0.v
wire ddr0_ctu_dll_lock; // From pad_ddr0 of pad_ddr0.v
wire ddr0_ctu_dll_overflow; // From pad_ddr0 of pad_ddr0.v
wire ddr0_ddr0_bso; // From pad_ddr0 of pad_ddr0.v
wire [8:1] ddr0_ddr1_cbd; // From pad_ddr0 of pad_ddr0.v
wire [8:1] ddr0_ddr1_cbu; // From pad_ddr0 of pad_ddr0.v
wire ddr1_ctu_dll_lock; // From pad_ddr1 of pad_ddr1.v
wire ddr1_ctu_dll_overflow; // From pad_ddr1 of pad_ddr1.v
wire ddr1_jbusl_bso; // From pad_ddr1 of pad_ddr1.v
wire ddr2_ctu_dll_lock; // From pad_ddr2 of pad_ddr2.v
wire ddr2_ctu_dll_overflow; // From pad_ddr2 of pad_ddr2.v
wire ddr2_ddr2_bso; // From pad_ddr2 of pad_ddr2.v
wire [8:1] ddr2_ddr3_cbd; // From pad_ddr2 of pad_ddr2.v
wire [8:1] ddr2_ddr3_cbu; // From pad_ddr2 of pad_ddr2.v
wire ddr2_misc_sscan_out; // From pad_ddr2 of pad_ddr2.v
wire ddr3_ctu_dll_lock; // From pad_ddr3 of pad_ddr3.v
wire ddr3_ctu_dll_overflow; // From pad_ddr3 of pad_ddr3.v
wire ddr3_ddr2_bso; // From pad_ddr3 of pad_ddr3.v
wire dram02_ctu_tr; // From dram02 of dram.v
wire [3:0] dram02_iob_data; // From dram02 of dram.v
wire dram02_iob_stall; // From dram02 of dram.v
wire dram02_iob_vld; // From dram02 of dram.v
wire [127:0] dram02_scbuf0_data_r2; // From dram02 of dram.v
wire [127:0] dram02_scbuf0_data_r2_buf1;// From dram_sc_0_rep1 of dram_l2_buf2.v
wire [127:0] dram02_scbuf0_data_r2_buf2;// From dram_sc_0_rep2 of dram_sc_0_rep2.v
wire [127:0] dram02_scbuf0_data_r2_buf3;// From dram_sc_0_rep3 of dram_l2_buf2.v
wire [127:0] dram02_scbuf0_data_r2_d1;// From ff_dram_sc_bank0 of ff_dram_sc_bank0.v
wire [27:0] dram02_scbuf0_ecc_r2; // From dram02 of dram.v
wire [27:0] dram02_scbuf0_ecc_r2_buf1;// From dram_sc_0_rep1 of dram_l2_buf2.v
wire [27:0] dram02_scbuf0_ecc_r2_buf2;// From dram_sc_0_rep2 of dram_sc_0_rep2.v
wire [27:0] dram02_scbuf0_ecc_r2_buf3;// From dram_sc_0_rep3 of dram_l2_buf2.v
wire [27:0] dram02_scbuf0_ecc_r2_d1;// From ff_dram_sc_bank0 of ff_dram_sc_bank0.v
wire [127:0] dram02_scbuf2_data_r2; // From dram02 of dram.v
wire [127:0] dram02_scbuf2_data_r2_buf1;// From dram_sc_2_rep1 of dram_l2_buf2.v
wire [127:0] dram02_scbuf2_data_r2_buf2;// From dram_sc_2_rep2 of dram_sc_2_rep2.v
wire [127:0] dram02_scbuf2_data_r2_buf3;// From dram_sc_2_rep3 of dram_l2_buf2.v
wire [127:0] dram02_scbuf2_data_r2_d1;// From ff_dram_sc_bank2 of ff_dram_sc_bank2.v
wire [27:0] dram02_scbuf2_ecc_r2; // From dram02 of dram.v
wire [27:0] dram02_scbuf2_ecc_r2_buf1;// From dram_sc_2_rep1 of dram_l2_buf2.v
wire [27:0] dram02_scbuf2_ecc_r2_buf2;// From dram_sc_2_rep2 of dram_sc_2_rep2.v
wire [27:0] dram02_scbuf2_ecc_r2_buf3;// From dram_sc_2_rep3 of dram_l2_buf2.v
wire [27:0] dram02_scbuf2_ecc_r2_d1;// From ff_dram_sc_bank2 of ff_dram_sc_bank2.v
wire [1:0] dram02_sctag0_chunk_id_r0;// From dram02 of dram.v
wire [1:0] dram02_sctag0_chunk_id_r0_buf1;// From dram_sc_0_rep1 of dram_l2_buf2.v
wire [1:0] dram02_sctag0_chunk_id_r0_buf2;// From dram_sc_0_rep2 of dram_sc_0_rep2.v
wire [1:0] dram02_sctag0_chunk_id_r0_d1;// From ff_dram_sc_bank0 of ff_dram_sc_bank0.v
wire dram02_sctag0_data_vld_r0;// From dram02 of dram.v
wire dram02_sctag0_data_vld_r0_buf1;// From dram_sc_0_rep1 of dram_l2_buf2.v
wire dram02_sctag0_data_vld_r0_buf2;// From dram_sc_0_rep2 of dram_sc_0_rep2.v
wire dram02_sctag0_data_vld_r0_d1;// From ff_dram_sc_bank0 of ff_dram_sc_bank0.v
wire dram02_sctag0_mecc_err_r2;// From dram02 of dram.v
wire dram02_sctag0_mecc_err_r2_buf1;// From dram_sc_0_rep1 of dram_l2_buf2.v
wire dram02_sctag0_mecc_err_r2_buf2;// From dram_sc_0_rep2 of dram_sc_0_rep2.v
wire dram02_sctag0_mecc_err_r2_d1;// From ff_dram_sc_bank0 of ff_dram_sc_bank0.v
wire dram02_sctag0_rd_ack; // From dram02 of dram.v
wire dram02_sctag0_rd_ack_buf1;// From dram_sc_0_rep1 of dram_l2_buf2.v
wire dram02_sctag0_rd_ack_buf2;// From dram_sc_0_rep2 of dram_sc_0_rep2.v
wire dram02_sctag0_rd_ack_d1;// From ff_dram_sc_bank0 of ff_dram_sc_bank0.v
wire [2:0] dram02_sctag0_rd_req_id_r0;// From dram02 of dram.v
wire [2:0] dram02_sctag0_rd_req_id_r0_buf1;// From dram_sc_0_rep1 of dram_l2_buf2.v
wire [2:0] dram02_sctag0_rd_req_id_r0_buf2;// From dram_sc_0_rep2 of dram_sc_0_rep2.v
wire [2:0] dram02_sctag0_rd_req_id_r0_d1;// From ff_dram_sc_bank0 of ff_dram_sc_bank0.v
wire dram02_sctag0_scb_mecc_err;// From dram02 of dram.v
wire dram02_sctag0_scb_mecc_err_buf1;// From dram_sc_0_rep1 of dram_l2_buf2.v
wire dram02_sctag0_scb_mecc_err_buf2;// From dram_sc_0_rep2 of dram_sc_0_rep2.v
wire dram02_sctag0_scb_mecc_err_d1;// From ff_dram_sc_bank0 of ff_dram_sc_bank0.v
wire dram02_sctag0_scb_secc_err;// From dram02 of dram.v
wire dram02_sctag0_scb_secc_err_buf1;// From dram_sc_0_rep1 of dram_l2_buf2.v
wire dram02_sctag0_scb_secc_err_buf2;// From dram_sc_0_rep2 of dram_sc_0_rep2.v
wire dram02_sctag0_scb_secc_err_d1;// From ff_dram_sc_bank0 of ff_dram_sc_bank0.v
wire dram02_sctag0_secc_err_r2;// From dram02 of dram.v
wire dram02_sctag0_secc_err_r2_buf1;// From dram_sc_0_rep1 of dram_l2_buf2.v
wire dram02_sctag0_secc_err_r2_buf2;// From dram_sc_0_rep2 of dram_sc_0_rep2.v
wire dram02_sctag0_secc_err_r2_d1;// From ff_dram_sc_bank0 of ff_dram_sc_bank0.v
wire dram02_sctag0_wr_ack; // From dram02 of dram.v
wire dram02_sctag0_wr_ack_buf1;// From dram_sc_0_rep1 of dram_l2_buf2.v
wire dram02_sctag0_wr_ack_buf2;// From dram_sc_0_rep2 of dram_sc_0_rep2.v
wire dram02_sctag0_wr_ack_d1;// From ff_dram_sc_bank0 of ff_dram_sc_bank0.v
wire [1:0] dram02_sctag2_chunk_id_r0;// From dram02 of dram.v
wire [1:0] dram02_sctag2_chunk_id_r0_buf1;// From dram_sc_2_rep1 of dram_l2_buf2.v
wire [1:0] dram02_sctag2_chunk_id_r0_buf2;// From dram_sc_2_rep2 of dram_sc_2_rep2.v
wire [1:0] dram02_sctag2_chunk_id_r0_d1;// From ff_dram_sc_bank2 of ff_dram_sc_bank2.v
wire dram02_sctag2_data_vld_r0;// From dram02 of dram.v
wire dram02_sctag2_data_vld_r0_buf1;// From dram_sc_2_rep1 of dram_l2_buf2.v
wire dram02_sctag2_data_vld_r0_buf2;// From dram_sc_2_rep2 of dram_sc_2_rep2.v
wire dram02_sctag2_data_vld_r0_d1;// From ff_dram_sc_bank2 of ff_dram_sc_bank2.v
wire dram02_sctag2_mecc_err_r2;// From dram02 of dram.v
wire dram02_sctag2_mecc_err_r2_buf1;// From dram_sc_2_rep1 of dram_l2_buf2.v
wire dram02_sctag2_mecc_err_r2_buf2;// From dram_sc_2_rep2 of dram_sc_2_rep2.v
wire dram02_sctag2_mecc_err_r2_d1;// From ff_dram_sc_bank2 of ff_dram_sc_bank2.v
wire dram02_sctag2_rd_ack; // From dram02 of dram.v
wire dram02_sctag2_rd_ack_buf1;// From dram_sc_2_rep1 of dram_l2_buf2.v
wire dram02_sctag2_rd_ack_buf2;// From dram_sc_2_rep2 of dram_sc_2_rep2.v
wire dram02_sctag2_rd_ack_d1;// From ff_dram_sc_bank2 of ff_dram_sc_bank2.v
wire [2:0] dram02_sctag2_rd_req_id_r0;// From dram02 of dram.v
wire [2:0] dram02_sctag2_rd_req_id_r0_buf1;// From dram_sc_2_rep1 of dram_l2_buf2.v
wire [2:0] dram02_sctag2_rd_req_id_r0_buf2;// From dram_sc_2_rep2 of dram_sc_2_rep2.v
wire [2:0] dram02_sctag2_rd_req_id_r0_d1;// From ff_dram_sc_bank2 of ff_dram_sc_bank2.v
wire dram02_sctag2_scb_mecc_err;// From dram02 of dram.v
wire dram02_sctag2_scb_mecc_err_buf1;// From dram_sc_2_rep1 of dram_l2_buf2.v
wire dram02_sctag2_scb_mecc_err_buf2;// From dram_sc_2_rep2 of dram_sc_2_rep2.v
wire dram02_sctag2_scb_mecc_err_d1;// From ff_dram_sc_bank2 of ff_dram_sc_bank2.v
wire dram02_sctag2_scb_secc_err;// From dram02 of dram.v
wire dram02_sctag2_scb_secc_err_buf1;// From dram_sc_2_rep1 of dram_l2_buf2.v
wire dram02_sctag2_scb_secc_err_buf2;// From dram_sc_2_rep2 of dram_sc_2_rep2.v
wire dram02_sctag2_scb_secc_err_d1;// From ff_dram_sc_bank2 of ff_dram_sc_bank2.v
wire dram02_sctag2_secc_err_r2;// From dram02 of dram.v
wire dram02_sctag2_secc_err_r2_buf1;// From dram_sc_2_rep1 of dram_l2_buf2.v
wire dram02_sctag2_secc_err_r2_buf2;// From dram_sc_2_rep2 of dram_sc_2_rep2.v
wire dram02_sctag2_secc_err_r2_d1;// From ff_dram_sc_bank2 of ff_dram_sc_bank2.v
wire dram02_sctag2_wr_ack; // From dram02 of dram.v
wire dram02_sctag2_wr_ack_buf1;// From dram_sc_2_rep1 of dram_l2_buf2.v
wire dram02_sctag2_wr_ack_buf2;// From dram_sc_2_rep2 of dram_sc_2_rep2.v
wire dram02_sctag2_wr_ack_d1;// From ff_dram_sc_bank2 of ff_dram_sc_bank2.v
wire [14:0] dram0_io_addr; // To/From v_m_help of v_m_help.v, ...
wire [2:0] dram0_io_bank; // To/From v_m_help of v_m_help.v, ...
wire dram0_io_cas_l; // To/From v_m_help of v_m_help.v, ...
wire dram0_io_cas_l_buf2; // To/From v_m_help of v_m_help.v
wire dram0_io_channel_disabled;// To/From v_m_help of v_m_help.v, ...
wire dram0_io_channel_disabled_buf2;// To/From v_m_help of v_m_help.v
wire dram0_io_cke; // To/From v_m_help of v_m_help.v, ...
wire dram0_io_cke_buf2; // To/From v_m_help of v_m_help.v
wire dram0_io_clk_enable; // To/From v_m_help of v_m_help.v, ...
wire dram0_io_clk_enable_buf2;// To/From v_m_help of v_m_help.v
wire [3:0] dram0_io_cs_l; // To/From v_m_help of v_m_help.v, ...
wire [287:0] dram0_io_data_out; // To/From v_m_help of v_m_help.v, ...
wire dram0_io_drive_data; // To/From v_m_help of v_m_help.v, ...
wire dram0_io_drive_data_buf2;// To/From v_m_help of v_m_help.v
wire dram0_io_drive_enable; // To/From v_m_help of v_m_help.v, ...
wire dram0_io_drive_enable_buf2;// To/From v_m_help of v_m_help.v
wire dram0_io_pad_clk_inv; // To/From v_m_help of v_m_help.v, ...
wire dram0_io_pad_clk_inv_buf2;// To/From v_m_help of v_m_help.v
wire dram0_io_pad_enable; // To/From v_m_help of v_m_help.v, ...
wire dram0_io_pad_enable_buf2;// To/From v_m_help of v_m_help.v
wire [4:0] dram0_io_ptr_clk_inv; // To/From v_m_help of v_m_help.v, ...
wire dram0_io_ras_l; // To/From v_m_help of v_m_help.v, ...
wire dram0_io_ras_l_buf2; // To/From v_m_help of v_m_help.v
wire dram0_io_write_en_l; // To/From v_m_help of v_m_help.v, ...
wire dram0_io_write_en_l_buf2;// To/From v_m_help of v_m_help.v
wire dram13_ctu_tr; // From dram13 of dram.v
wire [3:0] dram13_iob_data; // From dram13 of dram.v
wire dram13_iob_stall; // From dram13 of dram.v
wire dram13_iob_vld; // From dram13 of dram.v
wire [127:0] dram13_scbuf1_data_r2; // From dram13 of dram.v
wire [127:0] dram13_scbuf1_data_r2_buf1;// From dram_sc_1_rep1 of dram_l2_buf2.v
wire [127:0] dram13_scbuf1_data_r2_buf2;// From dram_sc_1_rep2 of dram_sc_1_rep2.v
wire [127:0] dram13_scbuf1_data_r2_buf3;// From dram_sc_1_rep3 of dram_l2_buf2.v
wire [127:0] dram13_scbuf1_data_r2_d1;// From ff_dram_sc_bank1 of ff_dram_sc_bank1.v
wire [27:0] dram13_scbuf1_ecc_r2; // From dram13 of dram.v
wire [27:0] dram13_scbuf1_ecc_r2_buf1;// From dram_sc_1_rep1 of dram_l2_buf2.v
wire [27:0] dram13_scbuf1_ecc_r2_buf2;// From dram_sc_1_rep2 of dram_sc_1_rep2.v
wire [27:0] dram13_scbuf1_ecc_r2_buf3;// From dram_sc_1_rep3 of dram_l2_buf2.v
wire [27:0] dram13_scbuf1_ecc_r2_d1;// From ff_dram_sc_bank1 of ff_dram_sc_bank1.v
wire [127:0] dram13_scbuf3_data_r2; // From dram13 of dram.v
wire [127:0] dram13_scbuf3_data_r2_buf1;// From dram_sc_3_rep1 of dram_l2_buf2.v
wire [127:0] dram13_scbuf3_data_r2_buf2;// From dram_sc_3_rep2 of dram_sc_3_rep2.v
wire [127:0] dram13_scbuf3_data_r2_buf3;// From dram_sc_3_rep3 of dram_l2_buf2.v
wire [127:0] dram13_scbuf3_data_r2_d1;// From ff_dram_sc_bank3 of ff_dram_sc_bank3.v
wire [27:0] dram13_scbuf3_ecc_r2; // From dram13 of dram.v
wire [27:0] dram13_scbuf3_ecc_r2_buf1;// From dram_sc_3_rep1 of dram_l2_buf2.v
wire [27:0] dram13_scbuf3_ecc_r2_buf2;// From dram_sc_3_rep2 of dram_sc_3_rep2.v
wire [27:0] dram13_scbuf3_ecc_r2_buf3;// From dram_sc_3_rep3 of dram_l2_buf2.v
wire [27:0] dram13_scbuf3_ecc_r2_d1;// From ff_dram_sc_bank3 of ff_dram_sc_bank3.v
wire [1:0] dram13_sctag1_chunk_id_r0;// From dram13 of dram.v
wire [1:0] dram13_sctag1_chunk_id_r0_buf1;// From dram_sc_1_rep1 of dram_l2_buf2.v
wire [1:0] dram13_sctag1_chunk_id_r0_buf2;// From dram_sc_1_rep2 of dram_sc_1_rep2.v
wire [1:0] dram13_sctag1_chunk_id_r0_d1;// From ff_dram_sc_bank1 of ff_dram_sc_bank1.v
wire dram13_sctag1_data_vld_r0;// From dram13 of dram.v
wire dram13_sctag1_data_vld_r0_buf1;// From dram_sc_1_rep1 of dram_l2_buf2.v
wire dram13_sctag1_data_vld_r0_buf2;// From dram_sc_1_rep2 of dram_sc_1_rep2.v
wire dram13_sctag1_data_vld_r0_d1;// From ff_dram_sc_bank1 of ff_dram_sc_bank1.v
wire dram13_sctag1_mecc_err_r2;// From dram13 of dram.v
wire dram13_sctag1_mecc_err_r2_buf1;// From dram_sc_1_rep1 of dram_l2_buf2.v
wire dram13_sctag1_mecc_err_r2_buf2;// From dram_sc_1_rep2 of dram_sc_1_rep2.v
wire dram13_sctag1_mecc_err_r2_d1;// From ff_dram_sc_bank1 of ff_dram_sc_bank1.v
wire dram13_sctag1_rd_ack; // From dram13 of dram.v
wire dram13_sctag1_rd_ack_buf1;// From dram_sc_1_rep1 of dram_l2_buf2.v
wire dram13_sctag1_rd_ack_buf2;// From dram_sc_1_rep2 of dram_sc_1_rep2.v
wire dram13_sctag1_rd_ack_d1;// From ff_dram_sc_bank1 of ff_dram_sc_bank1.v
wire [2:0] dram13_sctag1_rd_req_id_r0;// From dram13 of dram.v
wire [2:0] dram13_sctag1_rd_req_id_r0_buf1;// From dram_sc_1_rep1 of dram_l2_buf2.v
wire [2:0] dram13_sctag1_rd_req_id_r0_buf2;// From dram_sc_1_rep2 of dram_sc_1_rep2.v
wire [2:0] dram13_sctag1_rd_req_id_r0_d1;// From ff_dram_sc_bank1 of ff_dram_sc_bank1.v
wire dram13_sctag1_scb_mecc_err;// From dram13 of dram.v
wire dram13_sctag1_scb_mecc_err_buf1;// From dram_sc_1_rep1 of dram_l2_buf2.v
wire dram13_sctag1_scb_mecc_err_buf2;// From dram_sc_1_rep2 of dram_sc_1_rep2.v
wire dram13_sctag1_scb_mecc_err_d1;// From ff_dram_sc_bank1 of ff_dram_sc_bank1.v
wire dram13_sctag1_scb_secc_err;// From dram13 of dram.v
wire dram13_sctag1_scb_secc_err_buf1;// From dram_sc_1_rep1 of dram_l2_buf2.v
wire dram13_sctag1_scb_secc_err_buf2;// From dram_sc_1_rep2 of dram_sc_1_rep2.v
wire dram13_sctag1_scb_secc_err_d1;// From ff_dram_sc_bank1 of ff_dram_sc_bank1.v
wire dram13_sctag1_secc_err_r2;// From dram13 of dram.v
wire dram13_sctag1_secc_err_r2_buf1;// From dram_sc_1_rep1 of dram_l2_buf2.v
wire dram13_sctag1_secc_err_r2_buf2;// From dram_sc_1_rep2 of dram_sc_1_rep2.v
wire dram13_sctag1_secc_err_r2_d1;// From ff_dram_sc_bank1 of ff_dram_sc_bank1.v
wire dram13_sctag1_wr_ack; // From dram13 of dram.v
wire dram13_sctag1_wr_ack_buf1;// From dram_sc_1_rep1 of dram_l2_buf2.v
wire dram13_sctag1_wr_ack_buf2;// From dram_sc_1_rep2 of dram_sc_1_rep2.v
wire dram13_sctag1_wr_ack_d1;// From ff_dram_sc_bank1 of ff_dram_sc_bank1.v
wire [1:0] dram13_sctag3_chunk_id_r0;// From dram13 of dram.v
wire [1:0] dram13_sctag3_chunk_id_r0_buf1;// From dram_sc_3_rep1 of dram_l2_buf2.v
wire [1:0] dram13_sctag3_chunk_id_r0_buf2;// From dram_sc_3_rep2 of dram_sc_3_rep2.v
wire [1:0] dram13_sctag3_chunk_id_r0_d1;// From ff_dram_sc_bank3 of ff_dram_sc_bank3.v
wire dram13_sctag3_data_vld_r0;// From dram13 of dram.v
wire dram13_sctag3_data_vld_r0_buf1;// From dram_sc_3_rep1 of dram_l2_buf2.v
wire dram13_sctag3_data_vld_r0_buf2;// From dram_sc_3_rep2 of dram_sc_3_rep2.v
wire dram13_sctag3_data_vld_r0_d1;// From ff_dram_sc_bank3 of ff_dram_sc_bank3.v
wire dram13_sctag3_mecc_err_r2;// From dram13 of dram.v
wire dram13_sctag3_mecc_err_r2_buf1;// From dram_sc_3_rep1 of dram_l2_buf2.v
wire dram13_sctag3_mecc_err_r2_buf2;// From dram_sc_3_rep2 of dram_sc_3_rep2.v
wire dram13_sctag3_mecc_err_r2_d1;// From ff_dram_sc_bank3 of ff_dram_sc_bank3.v
wire dram13_sctag3_rd_ack; // From dram13 of dram.v
wire dram13_sctag3_rd_ack_buf1;// From dram_sc_3_rep1 of dram_l2_buf2.v
wire dram13_sctag3_rd_ack_buf2;// From dram_sc_3_rep2 of dram_sc_3_rep2.v
wire dram13_sctag3_rd_ack_d1;// From ff_dram_sc_bank3 of ff_dram_sc_bank3.v
wire [2:0] dram13_sctag3_rd_req_id_r0;// From dram13 of dram.v
wire [2:0] dram13_sctag3_rd_req_id_r0_buf1;// From dram_sc_3_rep1 of dram_l2_buf2.v
wire [2:0] dram13_sctag3_rd_req_id_r0_buf2;// From dram_sc_3_rep2 of dram_sc_3_rep2.v
wire [2:0] dram13_sctag3_rd_req_id_r0_d1;// From ff_dram_sc_bank3 of ff_dram_sc_bank3.v
wire dram13_sctag3_scb_mecc_err;// From dram13 of dram.v
wire dram13_sctag3_scb_mecc_err_buf1;// From dram_sc_3_rep1 of dram_l2_buf2.v
wire dram13_sctag3_scb_mecc_err_buf2;// From dram_sc_3_rep2 of dram_sc_3_rep2.v
wire dram13_sctag3_scb_mecc_err_d1;// From ff_dram_sc_bank3 of ff_dram_sc_bank3.v
wire dram13_sctag3_scb_secc_err;// From dram13 of dram.v
wire dram13_sctag3_scb_secc_err_buf1;// From dram_sc_3_rep1 of dram_l2_buf2.v
wire dram13_sctag3_scb_secc_err_buf2;// From dram_sc_3_rep2 of dram_sc_3_rep2.v
wire dram13_sctag3_scb_secc_err_d1;// From ff_dram_sc_bank3 of ff_dram_sc_bank3.v
wire dram13_sctag3_secc_err_r2;// From dram13 of dram.v
wire dram13_sctag3_secc_err_r2_buf1;// From dram_sc_3_rep1 of dram_l2_buf2.v
wire dram13_sctag3_secc_err_r2_buf2;// From dram_sc_3_rep2 of dram_sc_3_rep2.v
wire dram13_sctag3_secc_err_r2_d1;// From ff_dram_sc_bank3 of ff_dram_sc_bank3.v
wire dram13_sctag3_wr_ack; // From dram13 of dram.v
wire dram13_sctag3_wr_ack_buf1;// From dram_sc_3_rep1 of dram_l2_buf2.v
wire dram13_sctag3_wr_ack_buf2;// From dram_sc_3_rep2 of dram_sc_3_rep2.v
wire dram13_sctag3_wr_ack_d1;// From ff_dram_sc_bank3 of ff_dram_sc_bank3.v
wire [14:0] dram1_io_addr; // To/From v_m_help of v_m_help.v, ...
wire [2:0] dram1_io_bank; // To/From v_m_help of v_m_help.v, ...
wire dram1_io_cas_l; // To/From v_m_help of v_m_help.v, ...
wire dram1_io_cas_l_buf2; // To/From v_m_help of v_m_help.v
wire dram1_io_channel_disabled;// To/From v_m_help of v_m_help.v, ...
wire dram1_io_channel_disabled_buf2;// To/From v_m_help of v_m_help.v
wire dram1_io_cke; // To/From v_m_help of v_m_help.v, ...
wire dram1_io_cke_buf2; // To/From v_m_help of v_m_help.v
wire dram1_io_clk_enable; // To/From v_m_help of v_m_help.v, ...
wire dram1_io_clk_enable_buf2;// To/From v_m_help of v_m_help.v
wire [3:0] dram1_io_cs_l; // To/From v_m_help of v_m_help.v, ...
wire [287:0] dram1_io_data_out; // To/From v_m_help of v_m_help.v, ...
wire dram1_io_drive_data; // To/From v_m_help of v_m_help.v, ...
wire dram1_io_drive_data_buf2;// To/From v_m_help of v_m_help.v
wire dram1_io_drive_enable; // To/From v_m_help of v_m_help.v, ...
wire dram1_io_drive_enable_buf2;// To/From v_m_help of v_m_help.v
wire dram1_io_pad_clk_inv; // To/From v_m_help of v_m_help.v, ...
wire dram1_io_pad_clk_inv_buf2;// To/From v_m_help of v_m_help.v
wire dram1_io_pad_enable; // To/From v_m_help of v_m_help.v, ...
wire dram1_io_pad_enable_buf2;// To/From v_m_help of v_m_help.v
wire [4:0] dram1_io_ptr_clk_inv; // To/From v_m_help of v_m_help.v, ...
wire dram1_io_ras_l; // To/From v_m_help of v_m_help.v, ...
wire dram1_io_ras_l_buf2; // To/From v_m_help of v_m_help.v
wire dram1_io_write_en_l; // To/From v_m_help of v_m_help.v, ...
wire dram1_io_write_en_l_buf2;// To/From v_m_help of v_m_help.v
wire [14:0] dram2_io_addr; // To/From v_m_help of v_m_help.v, ...
wire [2:0] dram2_io_bank; // To/From v_m_help of v_m_help.v, ...
wire dram2_io_cas_l; // To/From v_m_help of v_m_help.v, ...
wire dram2_io_cas_l_buf2; // To/From v_m_help of v_m_help.v
wire dram2_io_channel_disabled;// To/From v_m_help of v_m_help.v, ...
wire dram2_io_channel_disabled_buf2;// To/From v_m_help of v_m_help.v
wire dram2_io_cke; // To/From v_m_help of v_m_help.v, ...
wire dram2_io_cke_buf2; // To/From v_m_help of v_m_help.v
wire dram2_io_clk_enable; // To/From v_m_help of v_m_help.v, ...
wire dram2_io_clk_enable_buf2;// To/From v_m_help of v_m_help.v
wire [3:0] dram2_io_cs_l; // To/From v_m_help of v_m_help.v, ...
wire [287:0] dram2_io_data_out; // To/From v_m_help of v_m_help.v, ...
wire dram2_io_drive_data; // To/From v_m_help of v_m_help.v, ...
wire dram2_io_drive_data_buf2;// To/From v_m_help of v_m_help.v
wire dram2_io_drive_enable; // To/From v_m_help of v_m_help.v, ...
wire dram2_io_drive_enable_buf2;// To/From v_m_help of v_m_help.v
wire dram2_io_pad_clk_inv; // To/From v_m_help of v_m_help.v, ...
wire dram2_io_pad_clk_inv_buf2;// To/From v_m_help of v_m_help.v
wire dram2_io_pad_enable; // To/From v_m_help of v_m_help.v, ...
wire dram2_io_pad_enable_buf2;// To/From v_m_help of v_m_help.v
wire [4:0] dram2_io_ptr_clk_inv; // To/From v_m_help of v_m_help.v, ...
wire dram2_io_ras_l; // To/From v_m_help of v_m_help.v, ...
wire dram2_io_ras_l_buf2; // To/From v_m_help of v_m_help.v
wire dram2_io_write_en_l; // To/From v_m_help of v_m_help.v, ...
wire dram2_io_write_en_l_buf2;// To/From v_m_help of v_m_help.v
wire [14:0] dram3_io_addr; // To/From v_m_help of v_m_help.v, ...
wire [2:0] dram3_io_bank; // To/From v_m_help of v_m_help.v, ...
wire dram3_io_cas_l; // To/From v_m_help of v_m_help.v, ...
wire dram3_io_cas_l_buf2; // To/From v_m_help of v_m_help.v
wire dram3_io_channel_disabled;// To/From v_m_help of v_m_help.v, ...
wire dram3_io_channel_disabled_buf2;// To/From v_m_help of v_m_help.v
wire dram3_io_cke; // To/From v_m_help of v_m_help.v, ...
wire dram3_io_cke_buf2; // To/From v_m_help of v_m_help.v
wire dram3_io_clk_enable; // To/From v_m_help of v_m_help.v, ...
wire dram3_io_clk_enable_buf2;// To/From v_m_help of v_m_help.v
wire [3:0] dram3_io_cs_l; // To/From v_m_help of v_m_help.v, ...
wire [287:0] dram3_io_data_out; // To/From v_m_help of v_m_help.v, ...
wire dram3_io_drive_data; // To/From v_m_help of v_m_help.v, ...
wire dram3_io_drive_data_buf2;// To/From v_m_help of v_m_help.v
wire dram3_io_drive_enable; // To/From v_m_help of v_m_help.v, ...
wire dram3_io_drive_enable_buf2;// To/From v_m_help of v_m_help.v
wire dram3_io_pad_clk_inv; // To/From v_m_help of v_m_help.v, ...
wire dram3_io_pad_clk_inv_buf2;// To/From v_m_help of v_m_help.v
wire dram3_io_pad_enable; // To/From v_m_help of v_m_help.v, ...
wire dram3_io_pad_enable_buf2;// To/From v_m_help of v_m_help.v
wire [4:0] dram3_io_ptr_clk_inv; // To/From v_m_help of v_m_help.v, ...
wire dram3_io_ras_l; // To/From v_m_help of v_m_help.v, ...
wire dram3_io_ras_l_buf2; // To/From v_m_help of v_m_help.v
wire dram3_io_write_en_l; // To/From v_m_help of v_m_help.v, ...
wire dram3_io_write_en_l_buf2;// To/From v_m_help of v_m_help.v
wire dram_adbginit_l; // From ctu of ctu.v
wire dram_arst_l; // From ctu of ctu.v
wire dram_gclk; // From ctu of ctu.v
wire [7:0] dram_gclk_c0_r; // To/From v_m_help of v_m_help.v, ...
wire [7:0] dram_gclk_c1_r; // From bw_clk_gl of bw_clk_gl.v
wire [7:0] dram_gclk_c2_r; // To/From v_m_help of v_m_help.v, ...
wire [7:0] dram_gclk_c3_r; // To/From v_m_help of v_m_help.v, ...
wire dram_gdbginit_l; // From ctu of ctu.v
wire dram_grst_l; // From ctu of ctu.v
wire dram_pt02_max_banks_open_valid;// From dram02 of dram.v
wire dram_pt02_max_time_valid;// From dram02 of dram.v
wire [16:0] dram_pt02_ucb_data; // From dram02 of dram.v
wire dram_pt0_opened_bank; // From dram02 of dram.v
wire dram_pt13_max_banks_open_valid;// From dram13 of dram.v
wire dram_pt13_max_time_valid;// From dram13 of dram.v
wire [16:0] dram_pt13_ucb_data; // From dram13 of dram.v
wire dram_pt1_opened_bank; // From dram13 of dram.v
wire dram_pt2_opened_bank; // From dram02 of dram.v
wire dram_pt3_opened_bank; // From dram13 of dram.v
wire efc_ctu_data_out; // From efc of efc.v
wire efc_iob_coreavail_dshift;// From efc of efc.v
wire efc_iob_fuse_clk1; // From efc of efc.v
wire efc_iob_fuse_data; // From efc of efc.v
wire efc_iob_fusestat_dshift;// From efc of efc.v
wire efc_iob_sernum0_dshift; // From efc of efc.v
wire efc_iob_sernum1_dshift; // From efc of efc.v
wire efc_iob_sernum2_dshift; // From efc of efc.v
wire efc_scdata02_fuse_clk1; // From efc of efc.v
wire efc_scdata02_fuse_clk2; // From efc of efc.v
wire efc_scdata02_fuse_data; // From efc of efc.v
wire efc_scdata0_fuse_ashift;// From efc of efc.v
wire efc_scdata0_fuse_dshift;// From efc of efc.v
wire efc_scdata13_fuse_clk1; // From efc of efc.v
wire efc_scdata13_fuse_clk2; // From efc of efc.v
wire efc_scdata13_fuse_data; // From efc of efc.v
wire efc_scdata1_fuse_ashift;// From efc of efc.v
wire efc_scdata1_fuse_dshift;// From efc of efc.v
wire efc_scdata2_fuse_ashift;// From efc of efc.v
wire efc_scdata2_fuse_dshift;// From efc of efc.v
wire efc_scdata3_fuse_ashift;// From efc of efc.v
wire efc_scdata3_fuse_dshift;// From efc of efc.v
wire efc_sctag02_fuse_clk1; // From efc of efc.v
wire efc_sctag02_fuse_clk2; // From efc of efc.v
wire efc_sctag02_fuse_data; // From efc of efc.v
wire efc_sctag0_fuse_ashift; // From efc of efc.v
wire efc_sctag0_fuse_dshift; // From efc of efc.v
wire efc_sctag13_fuse_clk1; // From efc of efc.v
wire efc_sctag13_fuse_clk2; // From efc of efc.v
wire efc_sctag13_fuse_data; // From efc of efc.v
wire efc_sctag1_fuse_ashift; // From efc of efc.v
wire efc_sctag1_fuse_dshift; // From efc of efc.v
wire efc_sctag2_fuse_ashift; // From efc of efc.v
wire efc_sctag2_fuse_dshift; // From efc of efc.v
wire efc_sctag3_fuse_ashift; // From efc of efc.v
wire efc_sctag3_fuse_dshift; // From efc of efc.v
wire efc_spc0246_fuse_clk1; // From efc of efc.v
wire efc_spc0246_fuse_clk2; // From efc of efc.v
wire efc_spc0246_fuse_data; // From efc of efc.v
wire efc_spc0_dfuse_ashift; // From efc of efc.v
wire efc_spc0_dfuse_dshift; // From efc of efc.v
wire efc_spc0_ifuse_ashift; // From efc of efc.v
wire efc_spc0_ifuse_dshift; // From efc of efc.v
wire efc_spc1357_fuse_clk1; // From efc of efc.v
wire efc_spc1357_fuse_clk2; // From efc of efc.v
wire efc_spc1357_fuse_data; // From efc of efc.v
wire efc_spc1_dfuse_ashift; // From efc of efc.v
wire efc_spc1_dfuse_dshift; // From efc of efc.v
wire efc_spc1_ifuse_ashift; // From efc of efc.v
wire efc_spc1_ifuse_dshift; // From efc of efc.v
wire efc_spc2_dfuse_ashift; // From efc of efc.v
wire efc_spc2_dfuse_dshift; // From efc of efc.v
wire efc_spc2_ifuse_ashift; // From efc of efc.v
wire efc_spc2_ifuse_dshift; // From efc of efc.v
wire efc_spc3_dfuse_ashift; // From efc of efc.v
wire efc_spc3_dfuse_dshift; // From efc of efc.v
wire efc_spc3_ifuse_ashift; // From efc of efc.v
wire efc_spc3_ifuse_dshift; // From efc of efc.v
wire efc_spc4_dfuse_ashift; // From efc of efc.v
wire efc_spc4_dfuse_dshift; // From efc of efc.v
wire efc_spc4_ifuse_ashift; // From efc of efc.v
wire efc_spc4_ifuse_dshift; // From efc of efc.v
wire efc_spc5_dfuse_ashift; // From efc of efc.v
wire efc_spc5_dfuse_dshift; // From efc of efc.v
wire efc_spc5_ifuse_ashift; // From efc of efc.v
wire efc_spc5_ifuse_dshift; // From efc of efc.v
wire efc_spc6_dfuse_ashift; // From efc of efc.v
wire efc_spc6_dfuse_dshift; // From efc of efc.v
wire efc_spc6_ifuse_ashift; // From efc of efc.v
wire efc_spc6_ifuse_dshift; // From efc of efc.v
wire efc_spc7_dfuse_ashift; // From efc of efc.v
wire efc_spc7_dfuse_dshift; // From efc of efc.v
wire efc_spc7_ifuse_ashift; // From efc of efc.v
wire efc_spc7_ifuse_dshift; // From efc of efc.v
wire [144:0] fp_cpx_data_ca; // From fpu of fpu.v
wire [7:0] fp_cpx_req_cq; // From fpu of fpu.v
wire fpu_rdram3_so; // From fpu of fpu.v
wire global_scan_bypass_en; // From ctu of ctu.v
wire global_shift_enable; // From ctu of ctu.v
wire io_clk_stretch; // From pad_misc of pad_misc.v
wire io_do_bist; // To/From v_m_help of v_m_help.v
wire [255:0] io_dram0_data_in; // To/From v_m_help of v_m_help.v, ...
wire io_dram0_data_valid; // To/From v_m_help of v_m_help.v, ...
wire io_dram0_data_valid_buf0;// To/From v_m_help of v_m_help.v
wire [31:0] io_dram0_ecc_in; // To/From v_m_help of v_m_help.v, ...
wire [255:0] io_dram1_data_in; // To/From v_m_help of v_m_help.v, ...
wire io_dram1_data_valid; // To/From v_m_help of v_m_help.v, ...
wire io_dram1_data_valid_buf0;// To/From v_m_help of v_m_help.v
wire [31:0] io_dram1_ecc_in; // To/From v_m_help of v_m_help.v, ...
wire [255:0] io_dram2_data_in; // To/From v_m_help of v_m_help.v, ...
wire io_dram2_data_valid; // To/From v_m_help of v_m_help.v, ...
wire io_dram2_data_valid_buf0;// To/From v_m_help of v_m_help.v
wire [31:0] io_dram2_ecc_in; // To/From v_m_help of v_m_help.v, ...
wire [255:0] io_dram3_data_in; // To/From v_m_help of v_m_help.v, ...
wire io_dram3_data_valid; // To/From v_m_help of v_m_help.v, ...
wire io_dram3_data_valid_buf0;// To/From v_m_help of v_m_help.v
wire [31:0] io_dram3_ecc_in; // To/From v_m_help of v_m_help.v, ...
wire io_ext_int_l; // From pad_misc of pad_misc.v
wire io_j_rst_l; // From pad_jbusr of pad_jbusr.v
wire [127:0] io_jbi_j_ad; // From pad_jbusr of pad_jbusr.v, ...
wire [3:0] io_jbi_j_adp; // From pad_jbusr of pad_jbusr.v
wire [7:0] io_jbi_j_adtype; // From pad_jbusr of pad_jbusr.v
wire [2:0] io_jbi_j_pack4; // From pad_jbusr of pad_jbusr.v
wire [2:0] io_jbi_j_pack5; // From pad_jbusr of pad_jbusr.v
wire io_jbi_j_par; // From pad_jbusr of pad_jbusr.v
wire io_jbi_j_req4_in_l; // From pad_jbusr of pad_jbusr.v
wire io_jbi_j_req5_in_l; // From pad_jbusr of pad_jbusr.v
wire io_jbi_ssi_miso; // From pad_misc of pad_misc.v
wire io_pcm_pmi; // From pad_misc of pad_misc.v
wire io_pgrm_en; // From pad_misc of pad_misc.v
wire io_pll_char_in; // From pad_misc of pad_misc.v
wire io_pwron_rst_l; // From pad_misc of pad_misc.v
wire io_tck; // From pad_misc of pad_misc.v
wire io_tck2; // From pad_misc of pad_misc.v
wire io_tdi; // From pad_misc of pad_misc.v
wire io_temp_trig; // From pad_misc of pad_misc.v
wire io_test_mode; // From pad_misc of pad_misc.v
wire io_tms; // From pad_misc of pad_misc.v
wire io_trigin; // From pad_misc of pad_misc.v
wire io_trst_l; // From pad_misc of pad_misc.v
wire io_vreg_selbg_l; // From pad_misc of pad_misc.v
wire [`IOB_CLK_WIDTH-1:0]iob_clsp_data; // From iobdg of iobdg.v
wire iob_clsp_stall; // From iobdg of iobdg.v
wire iob_clsp_vld; // From iobdg of iobdg.v
wire [`CPX_WIDTH-1:0]iob_cpx_data_ca; // To/From v_m_help of v_m_help.v, ...
wire [`IOB_CPU_WIDTH-1:0]iob_cpx_req_cq; // To/From v_m_help of v_m_help.v, ...
wire [`IOB_CPU_WIDTH-1:0]iob_ctu_coreavail; // From iobdg of iobdg.v
wire iob_ctu_l2_tr; // From iobdg of iobdg.v
wire iob_ctu_tr; // From iobdg of iobdg.v
wire [`IOB_DRAM_WIDTH-1:0]iob_dram02_data; // From iobdg of iobdg.v
wire iob_dram02_stall; // From iobdg of iobdg.v
wire iob_dram02_vld; // From iobdg of iobdg.v
wire [`IOB_DRAM_WIDTH-1:0]iob_dram13_data; // From iobdg of iobdg.v
wire iob_dram13_stall; // From iobdg of iobdg.v
wire iob_dram13_vld; // From iobdg of iobdg.v
wire [2:0] iob_io_dbg_ck_n; // To/From v_m_help of v_m_help.v, ...
wire [2:0] iob_io_dbg_ck_p; // To/From v_m_help of v_m_help.v, ...
wire [39:0] iob_io_dbg_data; // To/From v_m_help of v_m_help.v, ...
wire iob_io_dbg_en; // To/From v_m_help of v_m_help.v, ...
wire [47:0] iob_jbi_dbg_hi_data; // To/From v_m_help of v_m_help.v, ...
wire iob_jbi_dbg_hi_vld; // To/From v_m_help of v_m_help.v, ...
wire [47:0] iob_jbi_dbg_lo_data; // To/From v_m_help of v_m_help.v, ...
wire iob_jbi_dbg_lo_vld; // To/From v_m_help of v_m_help.v, ...
wire iob_jbi_mondo_ack; // To/From v_m_help of v_m_help.v, ...
wire iob_jbi_mondo_nack; // To/From v_m_help of v_m_help.v, ...
wire [`IOB_JBI_WIDTH-1:0]iob_jbi_pio_data; // To/From v_m_help of v_m_help.v, ...
wire iob_jbi_pio_stall; // To/From v_m_help of v_m_help.v, ...
wire iob_jbi_pio_vld; // To/From v_m_help of v_m_help.v, ...
wire [`IOB_SPI_WIDTH-1:0]iob_jbi_spi_data; // To/From v_m_help of v_m_help.v, ...
wire iob_jbi_spi_stall; // To/From v_m_help of v_m_help.v, ...
wire iob_jbi_spi_vld; // To/From v_m_help of v_m_help.v, ...
wire iob_pcx_stall_pq; // To/From v_m_help of v_m_help.v, ...
wire [`IOB_TAP_WIDTH-1:0]iob_tap_data; // From iobdg of iobdg.v
wire iob_tap_stall; // From iobdg of iobdg.v
wire iob_tap_vld; // From iobdg of iobdg.v
wire jbi_ctu_tr; // From jbi of jbi.v
wire [1:0] jbi_io_config_dtl; // From jbi of jbi.v
wire [127:0] jbi_io_j_ad; // From jbi of jbi.v
wire [3:0] jbi_io_j_ad_en; // From jbi of jbi.v
wire [3:0] jbi_io_j_adp; // From jbi of jbi.v
wire jbi_io_j_adp_en; // From jbi of jbi.v
wire [7:0] jbi_io_j_adtype; // From jbi of jbi.v
wire jbi_io_j_adtype_en; // From jbi of jbi.v
wire [2:0] jbi_io_j_pack0; // From jbi of jbi.v
wire jbi_io_j_pack0_en; // From jbi of jbi.v
wire [2:0] jbi_io_j_pack1; // From jbi of jbi.v
wire jbi_io_j_pack1_en; // From jbi of jbi.v
wire jbi_io_j_req0_out_en; // From jbi of jbi.v
wire jbi_io_j_req0_out_l; // From jbi of jbi.v
wire jbi_io_ssi_mosi; // From jbi of jbi.v
wire jbi_io_ssi_sck; // From jbi of jbi.v
wire [`JBI_IOB_MONDO_BUS_WIDTH-1:0]jbi_iob_mondo_data;// To/From v_m_help of v_m_help.v, ...
wire jbi_iob_mondo_vld; // To/From v_m_help of v_m_help.v, ...
wire [`JBI_IOB_WIDTH-1:0]jbi_iob_pio_data; // To/From v_m_help of v_m_help.v, ...
wire jbi_iob_pio_stall; // To/From v_m_help of v_m_help.v, ...
wire jbi_iob_pio_vld; // To/From v_m_help of v_m_help.v, ...
wire [`SPI_IOB_WIDTH-1:0]jbi_iob_spi_data; // To/From v_m_help of v_m_help.v, ...
wire jbi_iob_spi_stall; // To/From v_m_help of v_m_help.v, ...
wire jbi_iob_spi_vld; // To/From v_m_help of v_m_help.v, ...
wire [6:0] jbi_scbuf0_ecc; // From jbi of jbi.v
wire [6:0] jbi_scbuf0_ecc_d1; // From ff_jbi_sc0_1 of ff_jbi_sc0_1.v
wire [6:0] jbi_scbuf0_ecc_d1_buf1; // From rep_jbi_sc0_1 of jbi_l2_buf2.v
wire [6:0] jbi_scbuf0_ecc_d2; // From ff_jbi_sc0_2 of ff_jbi_sc0_2.v
wire [6:0] jbi_scbuf0_ecc_d2_buf1; // From rep_jbi_sc0_2 of rep_jbi_sc0_2.v
wire [6:0] jbi_scbuf1_ecc; // From jbi of jbi.v
wire [6:0] jbi_scbuf1_ecc_d1; // From ff_jbi_sc1_1 of ff_jbi_sc1_1.v
wire [6:0] jbi_scbuf1_ecc_d1_buf1; // From rep_jbi_sc1_1 of jbi_l2_buf2.v
wire [6:0] jbi_scbuf1_ecc_d2; // From ff_jbi_sc1_2 of ff_jbi_sc1_2.v
wire [6:0] jbi_scbuf1_ecc_d2_buf1; // From rep_jbi_sc1_2 of rep_jbi_sc1_2.v
wire [6:0] jbi_scbuf2_ecc; // From jbi of jbi.v
wire [6:0] jbi_scbuf2_ecc_d1; // From ff_jbi_sc2_1 of ff_jbi_sc2_1.v
wire [6:0] jbi_scbuf2_ecc_d1_buf1; // From rep_jbi_sc2_1 of jbi_l2_buf2.v
wire [6:0] jbi_scbuf2_ecc_d2; // From ff_jbi_sc2_2 of ff_jbi_sc2_2.v
wire [6:0] jbi_scbuf2_ecc_d2_buf1; // From rep_jbi_sc2_2 of rep_jbi_sc2_2.v
wire [6:0] jbi_scbuf3_ecc; // From jbi of jbi.v
wire [6:0] jbi_scbuf3_ecc_d1; // From ff_jbi_sc3_1 of ff_jbi_sc3_1.v
wire [6:0] jbi_scbuf3_ecc_d1_buf1; // From rep_jbi_sc3_1 of jbi_l2_buf2.v
wire [6:0] jbi_scbuf3_ecc_d2; // From ff_jbi_sc3_2 of ff_jbi_sc3_2.v
wire [6:0] jbi_scbuf3_ecc_d2_buf1; // From rep_jbi_sc3_2 of rep_jbi_sc3_2.v
wire [31:0] jbi_sctag0_req; // From jbi of jbi.v
wire [31:0] jbi_sctag0_req_d1; // From ff_jbi_sc0_1 of ff_jbi_sc0_1.v
wire [31:0] jbi_sctag0_req_d1_buf1; // From rep_jbi_sc0_1 of jbi_l2_buf2.v
wire [31:0] jbi_sctag0_req_d2; // From ff_jbi_sc0_2 of ff_jbi_sc0_2.v
wire [31:0] jbi_sctag0_req_d2_buf1; // From rep_jbi_sc0_2 of rep_jbi_sc0_2.v
wire jbi_sctag0_req_vld; // From jbi of jbi.v
wire jbi_sctag0_req_vld_d1; // From ff_jbi_sc0_1 of ff_jbi_sc0_1.v
wire jbi_sctag0_req_vld_d1_buf1;// From rep_jbi_sc0_1 of jbi_l2_buf2.v
wire jbi_sctag0_req_vld_d2; // From ff_jbi_sc0_2 of ff_jbi_sc0_2.v
wire [31:0] jbi_sctag1_req; // From jbi of jbi.v
wire [31:0] jbi_sctag1_req_d1; // From ff_jbi_sc1_1 of ff_jbi_sc1_1.v
wire [31:0] jbi_sctag1_req_d1_buf1; // From rep_jbi_sc1_1 of jbi_l2_buf2.v
wire [31:0] jbi_sctag1_req_d2; // From ff_jbi_sc1_2 of ff_jbi_sc1_2.v
wire [31:0] jbi_sctag1_req_d2_buf1; // From rep_jbi_sc1_2 of rep_jbi_sc1_2.v
wire jbi_sctag1_req_vld; // From jbi of jbi.v
wire jbi_sctag1_req_vld_d1; // From ff_jbi_sc1_1 of ff_jbi_sc1_1.v
wire jbi_sctag1_req_vld_d1_buf1;// From rep_jbi_sc1_1 of jbi_l2_buf2.v
wire jbi_sctag1_req_vld_d2; // From ff_jbi_sc1_2 of ff_jbi_sc1_2.v
wire [31:0] jbi_sctag2_req; // From jbi of jbi.v
wire [31:0] jbi_sctag2_req_d1; // From ff_jbi_sc2_1 of ff_jbi_sc2_1.v
wire [31:0] jbi_sctag2_req_d1_buf1; // From rep_jbi_sc2_1 of jbi_l2_buf2.v
wire [31:0] jbi_sctag2_req_d2; // From ff_jbi_sc2_2 of ff_jbi_sc2_2.v
wire [31:0] jbi_sctag2_req_d2_buf1; // From rep_jbi_sc2_2 of rep_jbi_sc2_2.v
wire jbi_sctag2_req_vld; // From jbi of jbi.v
wire jbi_sctag2_req_vld_d1; // From ff_jbi_sc2_1 of ff_jbi_sc2_1.v
wire jbi_sctag2_req_vld_d1_buf1;// From rep_jbi_sc2_1 of jbi_l2_buf2.v
wire jbi_sctag2_req_vld_d2; // From ff_jbi_sc2_2 of ff_jbi_sc2_2.v
wire [31:0] jbi_sctag3_req; // From jbi of jbi.v
wire [31:0] jbi_sctag3_req_d1; // From ff_jbi_sc3_1 of ff_jbi_sc3_1.v
wire [31:0] jbi_sctag3_req_d1_buf1; // From rep_jbi_sc3_1 of jbi_l2_buf2.v
wire [31:0] jbi_sctag3_req_d2; // From ff_jbi_sc3_2 of ff_jbi_sc3_2.v
wire [31:0] jbi_sctag3_req_d2_buf1; // From rep_jbi_sc3_2 of rep_jbi_sc3_2.v
wire jbi_sctag3_req_vld; // From jbi of jbi.v
wire jbi_sctag3_req_vld_d1; // From ff_jbi_sc3_1 of ff_jbi_sc3_1.v
wire jbi_sctag3_req_vld_d1_buf1;// From rep_jbi_sc3_1 of jbi_l2_buf2.v
wire jbi_sctag3_req_vld_d2; // From ff_jbi_sc3_2 of ff_jbi_sc3_2.v
wire jbus_adbginit_l; // From ctu of ctu.v
wire jbus_arst_l; // From ctu of ctu.v
wire jbus_gclk; // From ctu of ctu.v
wire [7:0] jbus_gclk_c0_r; // From bw_clk_gl of bw_clk_gl.v
wire [7:0] jbus_gclk_c1_r; // From bw_clk_gl of bw_clk_gl.v
wire [7:0] jbus_gclk_c2_r; // From bw_clk_gl of bw_clk_gl.v
wire [7:0] jbus_gclk_c3_r; // From bw_clk_gl of bw_clk_gl.v
wire jbus_gclk_dup; // From bw_clk_gl of bw_clk_gl.v
wire jbus_gclk_dup_out; // From ctu of ctu.v
wire jbus_gdbginit_l; // From ctu of ctu.v
wire jbus_grst_l; // From ctu of ctu.v
wire jbusl_jbusr_bso; // From pad_jbusl of pad_jbusl.v
wire jbusr_ddr3_sscan_out; // From pad_jbusr of pad_jbusr.v
wire [8:1] jbusr_jbusl_cbd; // From pad_jbusr of pad_jbusr.v
wire [8:1] jbusr_jbusl_cbu; // From pad_jbusr of pad_jbusr.v
wire jbusr_jbusr_bso; // From pad_jbusr of pad_jbusr.v
wire [39:0] l2_dbgbus_01; // From sc_0_1_dbg_rptr of sc_0_1_dbg_rptr.v
wire [39:0] l2_dbgbus_23; // From sc_2_3_dbg_rptr of sc_2_3_dbg_rptr.v
wire misc_dbg_bso; // From pad_misc of pad_misc.v
wire [30:0] par_scan_head; // To/From v_m_help of v_m_help.v
wire [30:0] par_scan_tail; // To/From v_m_help of v_m_help.v, ...
wire pcm_io_burnin; // From pad_misc of pad_misc.v
wire pcm_io_pmo; // From pcm of pcm.v
wire pcm_misc_oe; // From pcm of pcm.v
wire [`PCX_WIDTH-1:0]pcx_fp_data_px2; // From ccx of ccx.v
wire pcx_fp_data_rdy_px2; // From ccx of ccx.v
wire [`PCX_WIDTH-1:0]pcx_iob_data_px2; // To/From v_m_help of v_m_help.v, ...
wire pcx_iob_data_rdy_px2; // To/From v_m_help of v_m_help.v, ...
wire pcx_sctag0_atm_px1; // To/From v_m_help of v_m_help.v, ...
wire [`PCX_WIDTH-1:0]pcx_sctag0_data_px2; // To/From v_m_help of v_m_help.v, ...
wire pcx_sctag0_data_rdy_px1;// To/From v_m_help of v_m_help.v, ...
wire pcx_sctag1_atm_px1; // To/From v_m_help of v_m_help.v, ...
wire [`PCX_WIDTH-1:0]pcx_sctag1_data_px2; // To/From v_m_help of v_m_help.v, ...
wire pcx_sctag1_data_rdy_px1;// To/From v_m_help of v_m_help.v, ...
wire pcx_sctag2_atm_px1; // To/From v_m_help of v_m_help.v, ...
wire [`PCX_WIDTH-1:0]pcx_sctag2_data_px2; // To/From v_m_help of v_m_help.v, ...
wire pcx_sctag2_data_rdy_px1;// To/From v_m_help of v_m_help.v, ...
wire pcx_sctag3_atm_px1; // To/From v_m_help of v_m_help.v, ...
wire [`PCX_WIDTH-1:0]pcx_sctag3_data_px2; // To/From v_m_help of v_m_help.v, ...
wire pcx_sctag3_data_rdy_px1;// To/From v_m_help of v_m_help.v, ...
wire [4:0] pcx_spc0_grant_px; // From ccx of ccx.v
wire [4:0] pcx_spc0_grant_px_buf; // From ccx_spc_rpt0 of ccx_spc_rpt.v
wire [4:0] pcx_spc0_grant_px_buf1; // From buf_pcx_0 of spc_pcx_buf.v
wire [4:0] pcx_spc1_grant_px; // From ccx of ccx.v
wire [4:0] pcx_spc1_grant_px_buf; // From ccx_spc_rpt1 of ccx_spc_rpt.v
wire [4:0] pcx_spc1_grant_px_buf1; // From buf_pcx_1 of spc_pcx_buf.v
wire [4:0] pcx_spc2_grant_px; // From ccx of ccx.v
wire [4:0] pcx_spc2_grant_px_buf; // From ccx_spc_rpt2 of ccx_spc_rpt.v
wire [4:0] pcx_spc2_grant_px_buf1; // From buf_pcx_2 of spc_pcx_buf.v
wire [4:0] pcx_spc3_grant_px; // From ccx of ccx.v
wire [4:0] pcx_spc3_grant_px_buf; // From ccx_spc_rpt3 of ccx_spc_rpt.v
wire [4:0] pcx_spc3_grant_px_buf1; // From buf_pcx_3 of spc_pcx_buf.v
wire [4:0] pcx_spc4_grant_px; // From ccx of ccx.v
wire [4:0] pcx_spc4_grant_px_buf; // From ccx_spc_rpt4 of ccx_spc_rpt.v
wire [4:0] pcx_spc4_grant_px_buf1; // From buf_pcx_4 of spc_pcx_buf.v
wire [4:0] pcx_spc5_grant_px; // From ccx of ccx.v
wire [4:0] pcx_spc5_grant_px_buf; // From ccx_spc_rpt5 of ccx_spc_rpt.v
wire [4:0] pcx_spc5_grant_px_buf1; // From buf_pcx_5 of spc_pcx_buf.v
wire [4:0] pcx_spc6_grant_px; // From ccx of ccx.v
wire [4:0] pcx_spc6_grant_px_buf; // From ccx_spc_rpt6 of ccx_spc_rpt.v
wire [4:0] pcx_spc6_grant_px_buf1; // From buf_pcx_6 of spc_pcx_buf.v
wire [4:0] pcx_spc7_grant_px; // From ccx of ccx.v
wire [4:0] pcx_spc7_grant_px_buf; // From ccx_spc_rpt7 of ccx_spc_rpt.v
wire [4:0] pcx_spc7_grant_px_buf1; // From buf_pcx_7 of spc_pcx_buf.v
wire pdbg_pddr1_so; // From pad_dbg of pad_jbusl.v
wire pddr0_jbi_so; // From pad_ddr0 of pad_ddr0.v
wire pddr1_pjbusl_so; // From pad_ddr1 of pad_ddr1.v
wire pddr2_rsc22_so; // From pad_ddr2 of pad_ddr2.v
wire pddr3_pjbusr_so; // From pad_ddr3 of pad_ddr3.v
wire pjbusl_rptrs_so; // To/From v_m_help of v_m_help.v, ...
wire pjbusr_rptrs_so; // To/From v_m_help of v_m_help.v, ...
wire pmisc_pddr2_so; // From pad_misc of pad_misc.v
wire pscan_select; // From ctu of ctu.v
wire rbot2_ctu_so; // From ctu_bottom_rptr2 of ctu_bottom_rptr2.v
wire rbot_rdram1_so; // From ctu_bottom_rptr of ctu_bottom_rptr.v
wire rdbg01_rsc02_so; // From sc_0_1_dbg_rptr of sc_0_1_dbg_rptr.v
wire rdbg23_rdbg01_so; // From sc_2_3_dbg_rptr of sc_2_3_dbg_rptr.v
wire rdram0_rtop_so; // From ff_dram_sc_bank0 of ff_dram_sc_bank0.v
wire rdram1_rbot2_so; // From ff_dram_sc_bank1 of ff_dram_sc_bank1.v
wire rdram2_fpu_so; // From ff_dram_sc_bank2 of ff_dram_sc_bank2.v
wire rdram3_rbot_so; // From ff_dram_sc_bank3 of ff_dram_sc_bank3.v
wire rpt_ccx_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_dram_rx_sync_c1;// From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_dram_rx_sync_c6;// From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_dram_tx_sync_c1;// From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_dram_tx_sync_c6;// From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_gdbginit_l_c0; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_gdbginit_l_c1; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_gdbginit_l_c2; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_gdbginit_l_c3; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_gdbginit_l_c4; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_gdbginit_l_c5; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_gdbginit_l_c7; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_grst_l_c0; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_grst_l_c1; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_grst_l_c2; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_grst_l_c3; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_grst_l_c4; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_grst_l_c5; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_grst_l_c6; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_grst_l_c7; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_jbus_rx_sync_c1;// From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_jbus_rx_sync_c4;// From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_jbus_rx_sync_c6;// From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_jbus_tx_sync_c1;// From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_jbus_tx_sync_c4;// From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_cmp_jbus_tx_sync_c6;// From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_dram02_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_dram13_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_fpu_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_iob_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_jbi_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_scbuf0_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_scbuf1_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_scbuf2_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_scbuf3_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_scdata0_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_scdata1_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_scdata2_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_scdata3_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_sctag0_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_sctag1_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_sctag2_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_sctag3_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_spc0_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_spc1_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_spc2_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_spc3_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_spc4_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_spc5_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_spc6_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rpt_spc7_cmp_cken; // From flop_rptrs of bw_clk_gl_rstce_rtl.v
wire rptrs_pdbg_so; // To/From v_m_help of v_m_help.v
wire rptrs_pmisc_so; // To/From v_m_help of v_m_help.v
wire rptrs_rsc12_so; // To/From v_m_help of v_m_help.v
wire rsc01_rsc11_so; // From ff_jbi_sc0_1 of ff_jbi_sc0_1.v
wire rsc02_rptrs_so; // To/From v_m_help of v_m_help.v, ...
wire rsc11_rsc21_so; // From ff_jbi_sc1_1 of ff_jbi_sc1_1.v
wire rsc12_rsc01_so; // From ff_jbi_sc1_2 of ff_jbi_sc1_2.v
wire rsc21_rsc31_so; // From ff_jbi_sc2_1 of ff_jbi_sc2_1.v
wire rsc21_rsc32_so; // From ff_jbi_sc3_1 of ff_jbi_sc3_1.v
wire rsc22_rdbg23_so; // From ff_jbi_sc2_2 of ff_jbi_sc2_2.v
wire rsc32_efc_so; // From ff_jbi_sc3_2 of ff_jbi_sc3_2.v
wire rtop2_rdram0_so; // From ctu_top_rptr2 of ctu_top_rptr2.v
wire rtop_rdram2_so; // From ctu_top_rptr of ctu_top_rptr.v
wire scbuf0_dram02_data_mecc_r5;// From scbuf0 of scbuf.v
wire scbuf0_dram02_data_mecc_r5_buf1;// From dram_sc_0_rep3 of dram_l2_buf2.v
wire scbuf0_dram02_data_mecc_r5_buf2;// From dram_sc_0_rep2 of dram_sc_0_rep2.v
wire scbuf0_dram02_data_mecc_r5_buf3;// From dram_sc_0_rep1 of dram_l2_buf2.v
wire scbuf0_dram02_data_mecc_r5_d1;// From ff_dram_sc_bank0 of ff_dram_sc_bank0.v
wire scbuf0_dram02_data_vld_r5;// From scbuf0 of scbuf.v
wire scbuf0_dram02_data_vld_r5_buf1;// From dram_sc_0_rep3 of dram_l2_buf2.v
wire scbuf0_dram02_data_vld_r5_buf2;// From dram_sc_0_rep2 of dram_sc_0_rep2.v
wire scbuf0_dram02_data_vld_r5_buf3;// From dram_sc_0_rep1 of dram_l2_buf2.v
wire scbuf0_dram02_data_vld_r5_d1;// From ff_dram_sc_bank0 of ff_dram_sc_bank0.v
wire [63:0] scbuf0_dram02_wr_data_r5;// From scbuf0 of scbuf.v
wire [63:0] scbuf0_dram02_wr_data_r5_buf1;// From dram_sc_0_rep3 of dram_l2_buf2.v
wire [63:0] scbuf0_dram02_wr_data_r5_buf2;// From dram_sc_0_rep2 of dram_sc_0_rep2.v
wire [63:0] scbuf0_dram02_wr_data_r5_buf3;// From dram_sc_0_rep1 of dram_l2_buf2.v
wire [63:0] scbuf0_dram02_wr_data_r5_d1;// From ff_dram_sc_bank0 of ff_dram_sc_bank0.v
wire scbuf0_jbi_ctag_vld; // From scbuf0 of scbuf.v
wire scbuf0_jbi_ctag_vld_buf1;// From rep_jbi_sc0_2 of rep_jbi_sc0_2.v
wire scbuf0_jbi_ctag_vld_d1; // From ff_jbi_sc0_2 of ff_jbi_sc0_2.v
wire scbuf0_jbi_ctag_vld_d1_buf1;// From rep_jbi_sc0_1 of jbi_l2_buf2.v
wire scbuf0_jbi_ctag_vld_d2; // From ff_jbi_sc0_1 of ff_jbi_sc0_1.v
wire [31:0] scbuf0_jbi_data; // From scbuf0 of scbuf.v
wire [31:0] scbuf0_jbi_data_buf1; // From rep_jbi_sc0_2 of rep_jbi_sc0_2.v
wire [31:0] scbuf0_jbi_data_d1; // From ff_jbi_sc0_2 of ff_jbi_sc0_2.v
wire [31:0] scbuf0_jbi_data_d1_buf1;// From rep_jbi_sc0_1 of jbi_l2_buf2.v
wire [31:0] scbuf0_jbi_data_d2; // From ff_jbi_sc0_1 of ff_jbi_sc0_1.v
wire scbuf0_jbi_ue_err; // From scbuf0 of scbuf.v
wire scbuf0_jbi_ue_err_buf1; // From rep_jbi_sc0_2 of rep_jbi_sc0_2.v
wire scbuf0_jbi_ue_err_d1; // From ff_jbi_sc0_2 of ff_jbi_sc0_2.v
wire scbuf0_jbi_ue_err_d1_buf1;// From rep_jbi_sc0_1 of jbi_l2_buf2.v
wire scbuf0_jbi_ue_err_d2; // From ff_jbi_sc0_1 of ff_jbi_sc0_1.v
wire [623:0] scbuf0_scdata0_fbdecc_c4;// From scbuf0 of scbuf.v
wire scbuf0_scdata0_scanout; // From scbuf0 of scbuf.v
wire scbuf0_sctag0_ev_cerr_r5;// From scbuf0 of scbuf.v
wire scbuf0_sctag0_ev_cerr_r5_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire scbuf0_sctag0_ev_uerr_r5;// From scbuf0 of scbuf.v
wire scbuf0_sctag0_ev_uerr_r5_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire scbuf0_sctag0_rdma_cerr_c10;// From scbuf0 of scbuf.v
wire scbuf0_sctag0_rdma_cerr_c10_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire scbuf0_sctag0_rdma_uerr_c10;// From scbuf0 of scbuf.v
wire scbuf0_sctag0_rdma_uerr_c10_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire scbuf1_dram13_data_mecc_r5;// From scbuf1 of scbuf.v
wire scbuf1_dram13_data_mecc_r5_buf1;// From dram_sc_1_rep3 of dram_l2_buf2.v
wire scbuf1_dram13_data_mecc_r5_buf2;// From dram_sc_1_rep2 of dram_sc_1_rep2.v
wire scbuf1_dram13_data_mecc_r5_buf3;// From dram_sc_1_rep1 of dram_l2_buf2.v
wire scbuf1_dram13_data_mecc_r5_d1;// From ff_dram_sc_bank1 of ff_dram_sc_bank1.v
wire scbuf1_dram13_data_vld_r5;// From scbuf1 of scbuf.v
wire scbuf1_dram13_data_vld_r5_buf1;// From dram_sc_1_rep3 of dram_l2_buf2.v
wire scbuf1_dram13_data_vld_r5_buf2;// From dram_sc_1_rep2 of dram_sc_1_rep2.v
wire scbuf1_dram13_data_vld_r5_buf3;// From dram_sc_1_rep1 of dram_l2_buf2.v
wire scbuf1_dram13_data_vld_r5_d1;// From ff_dram_sc_bank1 of ff_dram_sc_bank1.v
wire [63:0] scbuf1_dram13_wr_data_r5;// From scbuf1 of scbuf.v
wire [63:0] scbuf1_dram13_wr_data_r5_buf1;// From dram_sc_1_rep3 of dram_l2_buf2.v
wire [63:0] scbuf1_dram13_wr_data_r5_buf2;// From dram_sc_1_rep2 of dram_sc_1_rep2.v
wire [63:0] scbuf1_dram13_wr_data_r5_buf3;// From dram_sc_1_rep1 of dram_l2_buf2.v
wire [63:0] scbuf1_dram13_wr_data_r5_d1;// From ff_dram_sc_bank1 of ff_dram_sc_bank1.v
wire scbuf1_jbi_ctag_vld; // From scbuf1 of scbuf.v
wire scbuf1_jbi_ctag_vld_buf1;// From rep_jbi_sc1_2 of rep_jbi_sc1_2.v
wire scbuf1_jbi_ctag_vld_d1; // From ff_jbi_sc1_2 of ff_jbi_sc1_2.v
wire scbuf1_jbi_ctag_vld_d1_buf1;// From rep_jbi_sc1_1 of jbi_l2_buf2.v
wire scbuf1_jbi_ctag_vld_d2; // From ff_jbi_sc1_1 of ff_jbi_sc1_1.v
wire [31:0] scbuf1_jbi_data; // From scbuf1 of scbuf.v
wire [31:0] scbuf1_jbi_data_buf1; // From rep_jbi_sc1_2 of rep_jbi_sc1_2.v
wire [31:0] scbuf1_jbi_data_d1; // From ff_jbi_sc1_2 of ff_jbi_sc1_2.v
wire [31:0] scbuf1_jbi_data_d1_buf1;// From rep_jbi_sc1_1 of jbi_l2_buf2.v
wire [31:0] scbuf1_jbi_data_d2; // From ff_jbi_sc1_1 of ff_jbi_sc1_1.v
wire scbuf1_jbi_ue_err; // From scbuf1 of scbuf.v
wire scbuf1_jbi_ue_err_buf1; // From rep_jbi_sc1_2 of rep_jbi_sc1_2.v
wire scbuf1_jbi_ue_err_d1; // From ff_jbi_sc1_2 of ff_jbi_sc1_2.v
wire scbuf1_jbi_ue_err_d1_buf1;// From rep_jbi_sc1_1 of jbi_l2_buf2.v
wire scbuf1_jbi_ue_err_d2; // From ff_jbi_sc1_1 of ff_jbi_sc1_1.v
wire [623:0] scbuf1_scdata1_fbdecc_c4;// From scbuf1 of scbuf.v
wire scbuf1_scdata1_scanout; // From scbuf1 of scbuf.v
wire scbuf1_sctag1_ev_cerr_r5;// From scbuf1 of scbuf.v
wire scbuf1_sctag1_ev_cerr_r5_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire scbuf1_sctag1_ev_uerr_r5;// From scbuf1 of scbuf.v
wire scbuf1_sctag1_ev_uerr_r5_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire scbuf1_sctag1_rdma_cerr_c10;// From scbuf1 of scbuf.v
wire scbuf1_sctag1_rdma_cerr_c10_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire scbuf1_sctag1_rdma_uerr_c10;// From scbuf1 of scbuf.v
wire scbuf1_sctag1_rdma_uerr_c10_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire scbuf2_dram02_data_mecc_r5;// From scbuf2 of scbuf.v
wire scbuf2_dram02_data_mecc_r5_buf1;// From dram_sc_2_rep3 of dram_l2_buf2.v
wire scbuf2_dram02_data_mecc_r5_buf2;// From dram_sc_2_rep2 of dram_sc_2_rep2.v
wire scbuf2_dram02_data_mecc_r5_buf3;// From dram_sc_2_rep1 of dram_l2_buf2.v
wire scbuf2_dram02_data_mecc_r5_d1;// From ff_dram_sc_bank2 of ff_dram_sc_bank2.v
wire scbuf2_dram02_data_vld_r5;// From scbuf2 of scbuf.v
wire scbuf2_dram02_data_vld_r5_buf1;// From dram_sc_2_rep3 of dram_l2_buf2.v
wire scbuf2_dram02_data_vld_r5_buf2;// From dram_sc_2_rep2 of dram_sc_2_rep2.v
wire scbuf2_dram02_data_vld_r5_buf3;// From dram_sc_2_rep1 of dram_l2_buf2.v
wire scbuf2_dram02_data_vld_r5_d1;// From ff_dram_sc_bank2 of ff_dram_sc_bank2.v
wire [63:0] scbuf2_dram02_wr_data_r5;// From scbuf2 of scbuf.v
wire [63:0] scbuf2_dram02_wr_data_r5_buf1;// From dram_sc_2_rep3 of dram_l2_buf2.v
wire [63:0] scbuf2_dram02_wr_data_r5_buf2;// From dram_sc_2_rep2 of dram_sc_2_rep2.v
wire [63:0] scbuf2_dram02_wr_data_r5_buf3;// From dram_sc_2_rep1 of dram_l2_buf2.v
wire [63:0] scbuf2_dram02_wr_data_r5_d1;// From ff_dram_sc_bank2 of ff_dram_sc_bank2.v
wire scbuf2_jbi_ctag_vld; // From scbuf2 of scbuf.v
wire scbuf2_jbi_ctag_vld_buf1;// From rep_jbi_sc2_2 of rep_jbi_sc2_2.v
wire scbuf2_jbi_ctag_vld_d1; // From ff_jbi_sc2_2 of ff_jbi_sc2_2.v
wire scbuf2_jbi_ctag_vld_d1_buf1;// From rep_jbi_sc2_1 of jbi_l2_buf2.v
wire scbuf2_jbi_ctag_vld_d2; // From ff_jbi_sc2_1 of ff_jbi_sc2_1.v
wire [31:0] scbuf2_jbi_data; // From scbuf2 of scbuf.v
wire [31:0] scbuf2_jbi_data_buf1; // From rep_jbi_sc2_2 of rep_jbi_sc2_2.v
wire [31:0] scbuf2_jbi_data_d1; // From ff_jbi_sc2_2 of ff_jbi_sc2_2.v
wire [31:0] scbuf2_jbi_data_d1_buf1;// From rep_jbi_sc2_1 of jbi_l2_buf2.v
wire [31:0] scbuf2_jbi_data_d2; // From ff_jbi_sc2_1 of ff_jbi_sc2_1.v
wire scbuf2_jbi_ue_err; // From scbuf2 of scbuf.v
wire scbuf2_jbi_ue_err_buf1; // From rep_jbi_sc2_2 of rep_jbi_sc2_2.v
wire scbuf2_jbi_ue_err_d1; // From ff_jbi_sc2_2 of ff_jbi_sc2_2.v
wire scbuf2_jbi_ue_err_d1_buf1;// From rep_jbi_sc2_1 of jbi_l2_buf2.v
wire scbuf2_jbi_ue_err_d2; // From ff_jbi_sc2_1 of ff_jbi_sc2_1.v
wire [623:0] scbuf2_scdata2_fbdecc_c4;// From scbuf2 of scbuf.v
wire scbuf2_scdata2_scanout; // From scbuf2 of scbuf.v
wire scbuf2_sctag2_ev_cerr_r5;// From scbuf2 of scbuf.v
wire scbuf2_sctag2_ev_cerr_r5_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire scbuf2_sctag2_ev_uerr_r5;// From scbuf2 of scbuf.v
wire scbuf2_sctag2_ev_uerr_r5_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire scbuf2_sctag2_rdma_cerr_c10;// From scbuf2 of scbuf.v
wire scbuf2_sctag2_rdma_cerr_c10_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire scbuf2_sctag2_rdma_uerr_c10;// From scbuf2 of scbuf.v
wire scbuf2_sctag2_rdma_uerr_c10_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire scbuf3_dram13_data_mecc_r5;// From scbuf3 of scbuf.v
wire scbuf3_dram13_data_mecc_r5_buf1;// From dram_sc_3_rep3 of dram_l2_buf2.v
wire scbuf3_dram13_data_mecc_r5_buf2;// From dram_sc_3_rep2 of dram_sc_3_rep2.v
wire scbuf3_dram13_data_mecc_r5_buf3;// From dram_sc_3_rep1 of dram_l2_buf2.v
wire scbuf3_dram13_data_mecc_r5_d1;// From ff_dram_sc_bank3 of ff_dram_sc_bank3.v
wire scbuf3_dram13_data_vld_r5;// From scbuf3 of scbuf.v
wire scbuf3_dram13_data_vld_r5_buf1;// From dram_sc_3_rep3 of dram_l2_buf2.v
wire scbuf3_dram13_data_vld_r5_buf2;// From dram_sc_3_rep2 of dram_sc_3_rep2.v
wire scbuf3_dram13_data_vld_r5_buf3;// From dram_sc_3_rep1 of dram_l2_buf2.v
wire scbuf3_dram13_data_vld_r5_d1;// From ff_dram_sc_bank3 of ff_dram_sc_bank3.v
wire [63:0] scbuf3_dram13_wr_data_r5;// From scbuf3 of scbuf.v
wire [63:0] scbuf3_dram13_wr_data_r5_buf1;// From dram_sc_3_rep3 of dram_l2_buf2.v
wire [63:0] scbuf3_dram13_wr_data_r5_buf2;// From dram_sc_3_rep2 of dram_sc_3_rep2.v
wire [63:0] scbuf3_dram13_wr_data_r5_buf3;// From dram_sc_3_rep1 of dram_l2_buf2.v
wire [63:0] scbuf3_dram13_wr_data_r5_d1;// From ff_dram_sc_bank3 of ff_dram_sc_bank3.v
wire scbuf3_jbi_ctag_vld; // From scbuf3 of scbuf.v
wire scbuf3_jbi_ctag_vld_buf1;// From rep_jbi_sc3_2 of rep_jbi_sc3_2.v
wire scbuf3_jbi_ctag_vld_d1; // From ff_jbi_sc3_2 of ff_jbi_sc3_2.v
wire scbuf3_jbi_ctag_vld_d1_buf1;// From rep_jbi_sc3_1 of jbi_l2_buf2.v
wire scbuf3_jbi_ctag_vld_d2; // From ff_jbi_sc3_1 of ff_jbi_sc3_1.v
wire [31:0] scbuf3_jbi_data; // From scbuf3 of scbuf.v
wire [31:0] scbuf3_jbi_data_buf1; // From rep_jbi_sc3_2 of rep_jbi_sc3_2.v
wire [31:0] scbuf3_jbi_data_d1; // From ff_jbi_sc3_2 of ff_jbi_sc3_2.v
wire [31:0] scbuf3_jbi_data_d1_buf1;// From rep_jbi_sc3_1 of jbi_l2_buf2.v
wire [31:0] scbuf3_jbi_data_d2; // From ff_jbi_sc3_1 of ff_jbi_sc3_1.v
wire scbuf3_jbi_ue_err; // From scbuf3 of scbuf.v
wire scbuf3_jbi_ue_err_buf1; // From rep_jbi_sc3_2 of rep_jbi_sc3_2.v
wire scbuf3_jbi_ue_err_d1; // From ff_jbi_sc3_2 of ff_jbi_sc3_2.v
wire scbuf3_jbi_ue_err_d1_buf1;// From rep_jbi_sc3_1 of jbi_l2_buf2.v
wire scbuf3_jbi_ue_err_d2; // From ff_jbi_sc3_1 of ff_jbi_sc3_1.v
wire [623:0] scbuf3_scdata3_fbdecc_c4;// From scbuf3 of scbuf.v
wire scbuf3_scdata3_scanout; // From scbuf3 of scbuf.v
wire scbuf3_sctag3_ev_cerr_r5;// From scbuf3 of scbuf.v
wire scbuf3_sctag3_ev_cerr_r5_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire scbuf3_sctag3_ev_uerr_r5;// From scbuf3 of scbuf.v
wire scbuf3_sctag3_ev_uerr_r5_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire scbuf3_sctag3_rdma_cerr_c10;// From scbuf3 of scbuf.v
wire scbuf3_sctag3_rdma_cerr_c10_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire scbuf3_sctag3_rdma_uerr_c10;// From scbuf3 of scbuf.v
wire scbuf3_sctag3_rdma_uerr_c10_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire scdata0_efc_fuse_data; // From scdata0 of scdata.v
wire [623:0] scdata0_scbuf0_decc_out_c7;// From scdata0 of scdata.v
wire [155:0] scdata0_sctag0_decc_c6; // From scdata0 of scdata.v
wire scdata1_efc_fuse_data; // From scdata1 of scdata.v
wire [623:0] scdata1_scbuf1_decc_out_c7;// From scdata1 of scdata.v
wire [155:0] scdata1_sctag1_decc_c6; // From scdata1 of scdata.v
wire scdata2_efc_fuse_data; // From scdata2 of scdata.v
wire [623:0] scdata2_scbuf2_decc_out_c7;// From scdata2 of scdata.v
wire [155:0] scdata2_sctag2_decc_c6; // From scdata2 of scdata.v
wire scdata3_efc_fuse_data; // From scdata3 of scdata.v
wire [623:0] scdata3_scbuf3_decc_out_c7;// From scdata3 of scdata.v
wire [155:0] scdata3_sctag3_decc_c6; // From scdata3 of scdata.v
wire sctag0_cpx_atom_cq; // To/From v_m_help of v_m_help.v, ...
wire [`CPX_WIDTH-1:0]sctag0_cpx_data_ca; // To/From v_m_help of v_m_help.v, ...
wire [7:0] sctag0_cpx_req_cq; // To/From v_m_help of v_m_help.v, ...
wire sctag0_ctu_mbistdone; // To/From v_m_help of v_m_help.v, ...
wire sctag0_ctu_mbistdone_buf2;// To/From v_m_help of v_m_help.v, ...
wire sctag0_ctu_mbisterr; // To/From v_m_help of v_m_help.v, ...
wire sctag0_ctu_mbisterr_buf2;// To/From v_m_help of v_m_help.v, ...
wire sctag0_ctu_tr; // To/From v_m_help of v_m_help.v, ...
wire sctag0_ctu_tr_buf2; // To/From v_m_help of v_m_help.v, ...
wire [40:0] sctag0_dbgbus_out; // From sctag0 of sctag.v
wire [39:5] sctag0_dram02_addr; // From sctag0 of sctag.v
wire [39:5] sctag0_dram02_addr_buf2;// From dram_sc_0_rep2 of dram_sc_0_rep2.v
wire [39:5] sctag0_dram02_addr_buf3;// From dram_sc_0_rep1 of dram_l2_buf2.v
wire [39:5] sctag0_dram02_addr_d1; // From ff_dram_sc_bank0 of ff_dram_sc_bank0.v
wire sctag0_dram02_rd_dummy_req;// From sctag0 of sctag.v
wire sctag0_dram02_rd_dummy_req_buf2;// From dram_sc_0_rep2 of dram_sc_0_rep2.v
wire sctag0_dram02_rd_dummy_req_buf3;// From dram_sc_0_rep1 of dram_l2_buf2.v
wire sctag0_dram02_rd_dummy_req_d1;// From ff_dram_sc_bank0 of ff_dram_sc_bank0.v
wire sctag0_dram02_rd_req; // From sctag0 of sctag.v
wire sctag0_dram02_rd_req_buf2;// From dram_sc_0_rep2 of dram_sc_0_rep2.v
wire sctag0_dram02_rd_req_buf3;// From dram_sc_0_rep1 of dram_l2_buf2.v
wire sctag0_dram02_rd_req_d1;// From ff_dram_sc_bank0 of ff_dram_sc_bank0.v
wire [2:0] sctag0_dram02_rd_req_id;// From sctag0 of sctag.v
wire [2:0] sctag0_dram02_rd_req_id_buf2;// From dram_sc_0_rep2 of dram_sc_0_rep2.v
wire [2:0] sctag0_dram02_rd_req_id_buf3;// From dram_sc_0_rep1 of dram_l2_buf2.v
wire [2:0] sctag0_dram02_rd_req_id_d1;// From ff_dram_sc_bank0 of ff_dram_sc_bank0.v
wire sctag0_dram02_wr_req; // From sctag0 of sctag.v
wire sctag0_dram02_wr_req_buf2;// From dram_sc_0_rep2 of dram_sc_0_rep2.v
wire sctag0_dram02_wr_req_buf3;// From dram_sc_0_rep1 of dram_l2_buf2.v
wire sctag0_dram02_wr_req_d1;// From ff_dram_sc_bank0 of ff_dram_sc_bank0.v
wire sctag0_efc_fuse_data; // From sctag0 of sctag.v
wire sctag0_jbi_iq_dequeue; // From sctag0 of sctag.v
wire sctag0_jbi_iq_dequeue_d1;// From ff_jbi_sc0_2 of ff_jbi_sc0_2.v
wire sctag0_jbi_iq_dequeue_d1_buf1;// From rep_jbi_sc0_1 of jbi_l2_buf2.v
wire sctag0_jbi_iq_dequeue_d2;// From ff_jbi_sc0_1 of ff_jbi_sc0_1.v
wire sctag0_jbi_por_req; // From sctag0 of sctag.v
wire sctag0_jbi_por_req_d1; // From ff_jbi_sc0_2 of ff_jbi_sc0_2.v
wire sctag0_jbi_por_req_d1_buf1;// From rep_jbi_sc0_1 of jbi_l2_buf2.v
wire sctag0_jbi_por_req_d2; // From ff_jbi_sc0_1 of ff_jbi_sc0_1.v
wire sctag0_jbi_wib_dequeue; // From sctag0 of sctag.v
wire sctag0_jbi_wib_dequeue_d1;// From ff_jbi_sc0_2 of ff_jbi_sc0_2.v
wire sctag0_jbi_wib_dequeue_d1_buf1;// From rep_jbi_sc0_1 of jbi_l2_buf2.v
wire sctag0_jbi_wib_dequeue_d2;// From ff_jbi_sc0_1 of ff_jbi_sc0_1.v
wire sctag0_pcx_stall_pq; // To/From v_m_help of v_m_help.v, ...
wire [14:0] sctag0_scbuf0_ctag_c7; // From sctag0 of sctag.v
wire [14:0] sctag0_scbuf0_ctag_c7_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire sctag0_scbuf0_ctag_en_c7;// From sctag0 of sctag.v
wire sctag0_scbuf0_ctag_en_c7_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire [2:0] sctag0_scbuf0_ev_dword_r0;// From sctag0 of sctag.v
wire [2:0] sctag0_scbuf0_ev_dword_r0_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire sctag0_scbuf0_evict_en_r0;// From sctag0 of sctag.v
wire sctag0_scbuf0_evict_en_r0_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire sctag0_scbuf0_fbd_stdatasel_c3;// From sctag0 of sctag.v
wire sctag0_scbuf0_fbd_stdatasel_c3_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire sctag0_scbuf0_fbrd_en_c3;// From sctag0 of sctag.v
wire sctag0_scbuf0_fbrd_en_c3_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire [2:0] sctag0_scbuf0_fbrd_wl_c3;// From sctag0 of sctag.v
wire [2:0] sctag0_scbuf0_fbrd_wl_c3_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire [15:0] sctag0_scbuf0_fbwr_wen_r2;// From sctag0 of sctag.v
wire [15:0] sctag0_scbuf0_fbwr_wen_r2_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire [2:0] sctag0_scbuf0_fbwr_wl_r2;// From sctag0 of sctag.v
wire [2:0] sctag0_scbuf0_fbwr_wl_r2_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire sctag0_scbuf0_rdma_rden_r0;// From sctag0 of sctag.v
wire sctag0_scbuf0_rdma_rden_r0_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire [1:0] sctag0_scbuf0_rdma_rdwl_r0;// From sctag0 of sctag.v
wire [1:0] sctag0_scbuf0_rdma_rdwl_r0_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire [15:0] sctag0_scbuf0_rdma_wren_s2;// From sctag0 of sctag.v
wire [15:0] sctag0_scbuf0_rdma_wren_s2_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire [1:0] sctag0_scbuf0_rdma_wrwl_s2;// From sctag0 of sctag.v
wire [1:0] sctag0_scbuf0_rdma_wrwl_s2_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire sctag0_scbuf0_req_en_c7;// From sctag0 of sctag.v
wire sctag0_scbuf0_req_en_c7_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire [77:0] sctag0_scbuf0_stdecc_c3;// From sctag0 of sctag.v
wire [77:0] sctag0_scbuf0_stdecc_c3_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire sctag0_scbuf0_wbrd_en_r0;// From sctag0 of sctag.v
wire sctag0_scbuf0_wbrd_en_r0_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire [2:0] sctag0_scbuf0_wbrd_wl_r0;// From sctag0 of sctag.v
wire [2:0] sctag0_scbuf0_wbrd_wl_r0_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire [3:0] sctag0_scbuf0_wbwr_wen_c6;// From sctag0 of sctag.v
wire [3:0] sctag0_scbuf0_wbwr_wen_c6_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire [2:0] sctag0_scbuf0_wbwr_wl_c6;// From sctag0 of sctag.v
wire [2:0] sctag0_scbuf0_wbwr_wl_c6_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire [3:0] sctag0_scbuf0_word_c7; // From sctag0 of sctag.v
wire [3:0] sctag0_scbuf0_word_c7_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire sctag0_scbuf0_word_vld_c7;// From sctag0 of sctag.v
wire sctag0_scbuf0_word_vld_c7_buf;// From sctag_scbuf_rptr0 of sctag_scbuf_rptr0.v
wire [3:0] sctag0_scdata0_col_offset_c2;// From sctag0 of sctag.v
wire sctag0_scdata0_fb_hit_c3;// From sctag0 of sctag.v
wire sctag0_scdata0_fbrd_c3; // From sctag0 of sctag.v
wire sctag0_scdata0_rd_wr_c2;// From sctag0 of sctag.v
wire [9:0] sctag0_scdata0_set_c2; // From sctag0 of sctag.v
wire [77:0] sctag0_scdata0_stdecc_c2;// From sctag0 of sctag.v
wire [11:0] sctag0_scdata0_way_sel_c2;// From sctag0 of sctag.v
wire [15:0] sctag0_scdata0_word_en_c2;// From sctag0 of sctag.v
wire sctag1_cpx_atom_cq; // To/From v_m_help of v_m_help.v, ...
wire [`CPX_WIDTH-1:0]sctag1_cpx_data_ca; // To/From v_m_help of v_m_help.v, ...
wire [7:0] sctag1_cpx_req_cq; // To/From v_m_help of v_m_help.v, ...
wire sctag1_ctu_mbistdone; // To/From v_m_help of v_m_help.v, ...
wire sctag1_ctu_mbistdone_buf2;// To/From v_m_help of v_m_help.v, ...
wire sctag1_ctu_mbisterr; // To/From v_m_help of v_m_help.v, ...
wire sctag1_ctu_mbisterr_buf2;// To/From v_m_help of v_m_help.v, ...
wire sctag1_ctu_tr; // To/From v_m_help of v_m_help.v, ...
wire sctag1_ctu_tr_buf2; // To/From v_m_help of v_m_help.v, ...
wire [40:0] sctag1_dbgbus_out; // From sctag1 of sctag.v
wire [39:5] sctag1_dram13_addr; // From sctag1 of sctag.v
wire [39:5] sctag1_dram13_addr_buf2;// From dram_sc_1_rep2 of dram_sc_1_rep2.v
wire [39:5] sctag1_dram13_addr_buf3;// From dram_sc_1_rep1 of dram_l2_buf2.v
wire [39:5] sctag1_dram13_addr_d1; // From ff_dram_sc_bank1 of ff_dram_sc_bank1.v
wire sctag1_dram13_rd_dummy_req;// From sctag1 of sctag.v
wire sctag1_dram13_rd_dummy_req_buf2;// From dram_sc_1_rep2 of dram_sc_1_rep2.v
wire sctag1_dram13_rd_dummy_req_buf3;// From dram_sc_1_rep1 of dram_l2_buf2.v
wire sctag1_dram13_rd_dummy_req_d1;// From ff_dram_sc_bank1 of ff_dram_sc_bank1.v
wire sctag1_dram13_rd_req; // From sctag1 of sctag.v
wire sctag1_dram13_rd_req_buf2;// From dram_sc_1_rep2 of dram_sc_1_rep2.v
wire sctag1_dram13_rd_req_buf3;// From dram_sc_1_rep1 of dram_l2_buf2.v
wire sctag1_dram13_rd_req_d1;// From ff_dram_sc_bank1 of ff_dram_sc_bank1.v
wire [2:0] sctag1_dram13_rd_req_id;// From sctag1 of sctag.v
wire [2:0] sctag1_dram13_rd_req_id_buf2;// From dram_sc_1_rep2 of dram_sc_1_rep2.v
wire [2:0] sctag1_dram13_rd_req_id_buf3;// From dram_sc_1_rep1 of dram_l2_buf2.v
wire [2:0] sctag1_dram13_rd_req_id_d1;// From ff_dram_sc_bank1 of ff_dram_sc_bank1.v
wire sctag1_dram13_wr_req; // From sctag1 of sctag.v
wire sctag1_dram13_wr_req_buf2;// From dram_sc_1_rep2 of dram_sc_1_rep2.v
wire sctag1_dram13_wr_req_buf3;// From dram_sc_1_rep1 of dram_l2_buf2.v
wire sctag1_dram13_wr_req_d1;// From ff_dram_sc_bank1 of ff_dram_sc_bank1.v
wire sctag1_efc_fuse_data; // From sctag1 of sctag.v
wire sctag1_jbi_iq_dequeue; // From sctag1 of sctag.v
wire sctag1_jbi_iq_dequeue_d1;// From ff_jbi_sc1_2 of ff_jbi_sc1_2.v
wire sctag1_jbi_iq_dequeue_d1_buf1;// From rep_jbi_sc1_1 of jbi_l2_buf2.v
wire sctag1_jbi_iq_dequeue_d2;// From ff_jbi_sc1_1 of ff_jbi_sc1_1.v
wire sctag1_jbi_por_req; // From sctag1 of sctag.v
wire sctag1_jbi_por_req_d1; // From ff_jbi_sc1_2 of ff_jbi_sc1_2.v
wire sctag1_jbi_por_req_d1_buf1;// From rep_jbi_sc1_1 of jbi_l2_buf2.v
wire sctag1_jbi_por_req_d2; // From ff_jbi_sc1_1 of ff_jbi_sc1_1.v
wire sctag1_jbi_wib_dequeue; // From sctag1 of sctag.v
wire sctag1_jbi_wib_dequeue_d1;// From ff_jbi_sc1_2 of ff_jbi_sc1_2.v
wire sctag1_jbi_wib_dequeue_d1_buf1;// From rep_jbi_sc1_1 of jbi_l2_buf2.v
wire sctag1_jbi_wib_dequeue_d2;// From ff_jbi_sc1_1 of ff_jbi_sc1_1.v
wire sctag1_pcx_stall_pq; // To/From v_m_help of v_m_help.v, ...
wire [14:0] sctag1_scbuf1_ctag_c7; // From sctag1 of sctag.v
wire [14:0] sctag1_scbuf1_ctag_c7_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire sctag1_scbuf1_ctag_en_c7;// From sctag1 of sctag.v
wire sctag1_scbuf1_ctag_en_c7_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire [2:0] sctag1_scbuf1_ev_dword_r0;// From sctag1 of sctag.v
wire [2:0] sctag1_scbuf1_ev_dword_r0_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire sctag1_scbuf1_evict_en_r0;// From sctag1 of sctag.v
wire sctag1_scbuf1_evict_en_r0_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire sctag1_scbuf1_fbd_stdatasel_c3;// From sctag1 of sctag.v
wire sctag1_scbuf1_fbd_stdatasel_c3_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire sctag1_scbuf1_fbrd_en_c3;// From sctag1 of sctag.v
wire sctag1_scbuf1_fbrd_en_c3_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire [2:0] sctag1_scbuf1_fbrd_wl_c3;// From sctag1 of sctag.v
wire [2:0] sctag1_scbuf1_fbrd_wl_c3_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire [15:0] sctag1_scbuf1_fbwr_wen_r2;// From sctag1 of sctag.v
wire [15:0] sctag1_scbuf1_fbwr_wen_r2_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire [2:0] sctag1_scbuf1_fbwr_wl_r2;// From sctag1 of sctag.v
wire [2:0] sctag1_scbuf1_fbwr_wl_r2_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire sctag1_scbuf1_rdma_rden_r0;// From sctag1 of sctag.v
wire sctag1_scbuf1_rdma_rden_r0_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire [1:0] sctag1_scbuf1_rdma_rdwl_r0;// From sctag1 of sctag.v
wire [1:0] sctag1_scbuf1_rdma_rdwl_r0_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire [15:0] sctag1_scbuf1_rdma_wren_s2;// From sctag1 of sctag.v
wire [15:0] sctag1_scbuf1_rdma_wren_s2_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire [1:0] sctag1_scbuf1_rdma_wrwl_s2;// From sctag1 of sctag.v
wire [1:0] sctag1_scbuf1_rdma_wrwl_s2_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire sctag1_scbuf1_req_en_c7;// From sctag1 of sctag.v
wire sctag1_scbuf1_req_en_c7_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire [77:0] sctag1_scbuf1_stdecc_c3;// From sctag1 of sctag.v
wire [77:0] sctag1_scbuf1_stdecc_c3_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire sctag1_scbuf1_wbrd_en_r0;// From sctag1 of sctag.v
wire sctag1_scbuf1_wbrd_en_r0_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire [2:0] sctag1_scbuf1_wbrd_wl_r0;// From sctag1 of sctag.v
wire [2:0] sctag1_scbuf1_wbrd_wl_r0_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire [3:0] sctag1_scbuf1_wbwr_wen_c6;// From sctag1 of sctag.v
wire [3:0] sctag1_scbuf1_wbwr_wen_c6_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire [2:0] sctag1_scbuf1_wbwr_wl_c6;// From sctag1 of sctag.v
wire [2:0] sctag1_scbuf1_wbwr_wl_c6_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire [3:0] sctag1_scbuf1_word_c7; // From sctag1 of sctag.v
wire [3:0] sctag1_scbuf1_word_c7_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire sctag1_scbuf1_word_vld_c7;// From sctag1 of sctag.v
wire sctag1_scbuf1_word_vld_c7_buf;// From sctag_scbuf_rptr1 of sctag_scbuf_rptr1.v
wire [3:0] sctag1_scdata1_col_offset_c2;// From sctag1 of sctag.v
wire sctag1_scdata1_fb_hit_c3;// From sctag1 of sctag.v
wire sctag1_scdata1_fbrd_c3; // From sctag1 of sctag.v
wire sctag1_scdata1_rd_wr_c2;// From sctag1 of sctag.v
wire [9:0] sctag1_scdata1_set_c2; // From sctag1 of sctag.v
wire [77:0] sctag1_scdata1_stdecc_c2;// From sctag1 of sctag.v
wire [11:0] sctag1_scdata1_way_sel_c2;// From sctag1 of sctag.v
wire [15:0] sctag1_scdata1_word_en_c2;// From sctag1 of sctag.v
wire sctag2_cpx_atom_cq; // To/From v_m_help of v_m_help.v, ...
wire [`CPX_WIDTH-1:0]sctag2_cpx_data_ca; // To/From v_m_help of v_m_help.v, ...
wire [7:0] sctag2_cpx_req_cq; // To/From v_m_help of v_m_help.v, ...
wire sctag2_ctu_mbistdone; // To/From v_m_help of v_m_help.v, ...
wire sctag2_ctu_mbistdone_buf2;// To/From v_m_help of v_m_help.v, ...
wire sctag2_ctu_mbisterr; // To/From v_m_help of v_m_help.v, ...
wire sctag2_ctu_mbisterr_buf2;// To/From v_m_help of v_m_help.v, ...
wire sctag2_ctu_tr; // To/From v_m_help of v_m_help.v, ...
wire sctag2_ctu_tr_buf2; // To/From v_m_help of v_m_help.v, ...
wire [40:0] sctag2_dbgbus_out; // From sctag2 of sctag.v
wire [39:5] sctag2_dram02_addr; // From sctag2 of sctag.v
wire [39:5] sctag2_dram02_addr_buf2;// From dram_sc_2_rep2 of dram_sc_2_rep2.v
wire [39:5] sctag2_dram02_addr_buf3;// From dram_sc_2_rep1 of dram_l2_buf2.v
wire [39:5] sctag2_dram02_addr_d1; // From ff_dram_sc_bank2 of ff_dram_sc_bank2.v
wire sctag2_dram02_rd_dummy_req;// From sctag2 of sctag.v
wire sctag2_dram02_rd_dummy_req_buf2;// From dram_sc_2_rep2 of dram_sc_2_rep2.v
wire sctag2_dram02_rd_dummy_req_buf3;// From dram_sc_2_rep1 of dram_l2_buf2.v
wire sctag2_dram02_rd_dummy_req_d1;// From ff_dram_sc_bank2 of ff_dram_sc_bank2.v
wire sctag2_dram02_rd_req; // From sctag2 of sctag.v
wire sctag2_dram02_rd_req_buf2;// From dram_sc_2_rep2 of dram_sc_2_rep2.v
wire sctag2_dram02_rd_req_buf3;// From dram_sc_2_rep1 of dram_l2_buf2.v
wire sctag2_dram02_rd_req_d1;// From ff_dram_sc_bank2 of ff_dram_sc_bank2.v
wire [2:0] sctag2_dram02_rd_req_id;// From sctag2 of sctag.v
wire [2:0] sctag2_dram02_rd_req_id_buf2;// From dram_sc_2_rep2 of dram_sc_2_rep2.v
wire [2:0] sctag2_dram02_rd_req_id_buf3;// From dram_sc_2_rep1 of dram_l2_buf2.v
wire [2:0] sctag2_dram02_rd_req_id_d1;// From ff_dram_sc_bank2 of ff_dram_sc_bank2.v
wire sctag2_dram02_wr_req; // From sctag2 of sctag.v
wire sctag2_dram02_wr_req_buf2;// From dram_sc_2_rep2 of dram_sc_2_rep2.v
wire sctag2_dram02_wr_req_buf3;// From dram_sc_2_rep1 of dram_l2_buf2.v
wire sctag2_dram02_wr_req_d1;// From ff_dram_sc_bank2 of ff_dram_sc_bank2.v
wire sctag2_efc_fuse_data; // From sctag2 of sctag.v
wire sctag2_jbi_iq_dequeue; // From sctag2 of sctag.v
wire sctag2_jbi_iq_dequeue_d1;// From ff_jbi_sc2_2 of ff_jbi_sc2_2.v
wire sctag2_jbi_iq_dequeue_d1_buf1;// From rep_jbi_sc2_1 of jbi_l2_buf2.v
wire sctag2_jbi_iq_dequeue_d2;// From ff_jbi_sc2_1 of ff_jbi_sc2_1.v
wire sctag2_jbi_por_req; // From sctag2 of sctag.v
wire sctag2_jbi_por_req_d1; // From ff_jbi_sc2_2 of ff_jbi_sc2_2.v
wire sctag2_jbi_por_req_d1_buf1;// From rep_jbi_sc2_1 of jbi_l2_buf2.v
wire sctag2_jbi_por_req_d2; // From ff_jbi_sc2_1 of ff_jbi_sc2_1.v
wire sctag2_jbi_wib_dequeue; // From sctag2 of sctag.v
wire sctag2_jbi_wib_dequeue_d1;// From ff_jbi_sc2_2 of ff_jbi_sc2_2.v
wire sctag2_jbi_wib_dequeue_d1_buf1;// From rep_jbi_sc2_1 of jbi_l2_buf2.v
wire sctag2_jbi_wib_dequeue_d2;// From ff_jbi_sc2_1 of ff_jbi_sc2_1.v
wire sctag2_pcx_stall_pq; // To/From v_m_help of v_m_help.v, ...
wire [14:0] sctag2_scbuf2_ctag_c7; // From sctag2 of sctag.v
wire [14:0] sctag2_scbuf2_ctag_c7_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire sctag2_scbuf2_ctag_en_c7;// From sctag2 of sctag.v
wire sctag2_scbuf2_ctag_en_c7_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire [2:0] sctag2_scbuf2_ev_dword_r0;// From sctag2 of sctag.v
wire [2:0] sctag2_scbuf2_ev_dword_r0_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire sctag2_scbuf2_evict_en_r0;// From sctag2 of sctag.v
wire sctag2_scbuf2_evict_en_r0_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire sctag2_scbuf2_fbd_stdatasel_c3;// From sctag2 of sctag.v
wire sctag2_scbuf2_fbd_stdatasel_c3_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire sctag2_scbuf2_fbrd_en_c3;// From sctag2 of sctag.v
wire sctag2_scbuf2_fbrd_en_c3_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire [2:0] sctag2_scbuf2_fbrd_wl_c3;// From sctag2 of sctag.v
wire [2:0] sctag2_scbuf2_fbrd_wl_c3_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire [15:0] sctag2_scbuf2_fbwr_wen_r2;// From sctag2 of sctag.v
wire [15:0] sctag2_scbuf2_fbwr_wen_r2_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire [2:0] sctag2_scbuf2_fbwr_wl_r2;// From sctag2 of sctag.v
wire [2:0] sctag2_scbuf2_fbwr_wl_r2_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire sctag2_scbuf2_rdma_rden_r0;// From sctag2 of sctag.v
wire sctag2_scbuf2_rdma_rden_r0_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire [1:0] sctag2_scbuf2_rdma_rdwl_r0;// From sctag2 of sctag.v
wire [1:0] sctag2_scbuf2_rdma_rdwl_r0_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire [15:0] sctag2_scbuf2_rdma_wren_s2;// From sctag2 of sctag.v
wire [15:0] sctag2_scbuf2_rdma_wren_s2_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire [1:0] sctag2_scbuf2_rdma_wrwl_s2;// From sctag2 of sctag.v
wire [1:0] sctag2_scbuf2_rdma_wrwl_s2_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire sctag2_scbuf2_req_en_c7;// From sctag2 of sctag.v
wire sctag2_scbuf2_req_en_c7_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire [77:0] sctag2_scbuf2_stdecc_c3;// From sctag2 of sctag.v
wire [77:0] sctag2_scbuf2_stdecc_c3_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire sctag2_scbuf2_wbrd_en_r0;// From sctag2 of sctag.v
wire sctag2_scbuf2_wbrd_en_r0_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire [2:0] sctag2_scbuf2_wbrd_wl_r0;// From sctag2 of sctag.v
wire [2:0] sctag2_scbuf2_wbrd_wl_r0_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire [3:0] sctag2_scbuf2_wbwr_wen_c6;// From sctag2 of sctag.v
wire [3:0] sctag2_scbuf2_wbwr_wen_c6_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire [2:0] sctag2_scbuf2_wbwr_wl_c6;// From sctag2 of sctag.v
wire [2:0] sctag2_scbuf2_wbwr_wl_c6_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire [3:0] sctag2_scbuf2_word_c7; // From sctag2 of sctag.v
wire [3:0] sctag2_scbuf2_word_c7_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire sctag2_scbuf2_word_vld_c7;// From sctag2 of sctag.v
wire sctag2_scbuf2_word_vld_c7_buf;// From sctag_scbuf_rptr2 of sctag_scbuf_rptr2.v
wire [3:0] sctag2_scdata2_col_offset_c2;// From sctag2 of sctag.v
wire sctag2_scdata2_fb_hit_c3;// From sctag2 of sctag.v
wire sctag2_scdata2_fbrd_c3; // From sctag2 of sctag.v
wire sctag2_scdata2_rd_wr_c2;// From sctag2 of sctag.v
wire [9:0] sctag2_scdata2_set_c2; // From sctag2 of sctag.v
wire [77:0] sctag2_scdata2_stdecc_c2;// From sctag2 of sctag.v
wire [11:0] sctag2_scdata2_way_sel_c2;// From sctag2 of sctag.v
wire [15:0] sctag2_scdata2_word_en_c2;// From sctag2 of sctag.v
wire sctag3_cpx_atom_cq; // To/From v_m_help of v_m_help.v, ...
wire [`CPX_WIDTH-1:0]sctag3_cpx_data_ca; // To/From v_m_help of v_m_help.v, ...
wire [7:0] sctag3_cpx_req_cq; // To/From v_m_help of v_m_help.v, ...
wire sctag3_ctu_mbistdone; // To/From v_m_help of v_m_help.v, ...
wire sctag3_ctu_mbistdone_buf2;// To/From v_m_help of v_m_help.v, ...
wire sctag3_ctu_mbisterr; // To/From v_m_help of v_m_help.v, ...
wire sctag3_ctu_mbisterr_buf2;// To/From v_m_help of v_m_help.v, ...
wire sctag3_ctu_tr; // To/From v_m_help of v_m_help.v, ...
wire sctag3_ctu_tr_buf2; // To/From v_m_help of v_m_help.v, ...
wire [40:0] sctag3_dbgbus_out; // From sctag3 of sctag.v
wire [39:5] sctag3_dram13_addr; // From sctag3 of sctag.v
wire [39:5] sctag3_dram13_addr_buf2;// From dram_sc_3_rep2 of dram_sc_3_rep2.v
wire [39:5] sctag3_dram13_addr_buf3;// From dram_sc_3_rep1 of dram_l2_buf2.v
wire [39:5] sctag3_dram13_addr_d1; // From ff_dram_sc_bank3 of ff_dram_sc_bank3.v
wire sctag3_dram13_rd_dummy_req;// From sctag3 of sctag.v
wire sctag3_dram13_rd_dummy_req_buf2;// From dram_sc_3_rep2 of dram_sc_3_rep2.v
wire sctag3_dram13_rd_dummy_req_buf3;// From dram_sc_3_rep1 of dram_l2_buf2.v
wire sctag3_dram13_rd_dummy_req_d1;// From ff_dram_sc_bank3 of ff_dram_sc_bank3.v
wire sctag3_dram13_rd_req; // From sctag3 of sctag.v
wire sctag3_dram13_rd_req_buf2;// From dram_sc_3_rep2 of dram_sc_3_rep2.v
wire sctag3_dram13_rd_req_buf3;// From dram_sc_3_rep1 of dram_l2_buf2.v
wire sctag3_dram13_rd_req_d1;// From ff_dram_sc_bank3 of ff_dram_sc_bank3.v
wire [2:0] sctag3_dram13_rd_req_id;// From sctag3 of sctag.v
wire [2:0] sctag3_dram13_rd_req_id_buf2;// From dram_sc_3_rep2 of dram_sc_3_rep2.v
wire [2:0] sctag3_dram13_rd_req_id_buf3;// From dram_sc_3_rep1 of dram_l2_buf2.v
wire [2:0] sctag3_dram13_rd_req_id_d1;// From ff_dram_sc_bank3 of ff_dram_sc_bank3.v
wire sctag3_dram13_wr_req; // From sctag3 of sctag.v
wire sctag3_dram13_wr_req_buf2;// From dram_sc_3_rep2 of dram_sc_3_rep2.v
wire sctag3_dram13_wr_req_buf3;// From dram_sc_3_rep1 of dram_l2_buf2.v
wire sctag3_dram13_wr_req_d1;// From ff_dram_sc_bank3 of ff_dram_sc_bank3.v
wire sctag3_efc_fuse_data; // From sctag3 of sctag.v
wire sctag3_jbi_iq_dequeue; // From sctag3 of sctag.v
wire sctag3_jbi_iq_dequeue_d1;// From ff_jbi_sc3_2 of ff_jbi_sc3_2.v
wire sctag3_jbi_iq_dequeue_d1_buf1;// From rep_jbi_sc3_1 of jbi_l2_buf2.v
wire sctag3_jbi_iq_dequeue_d2;// From ff_jbi_sc3_1 of ff_jbi_sc3_1.v
wire sctag3_jbi_por_req; // From sctag3 of sctag.v
wire sctag3_jbi_por_req_d1; // From ff_jbi_sc3_2 of ff_jbi_sc3_2.v
wire sctag3_jbi_por_req_d1_buf1;// From rep_jbi_sc3_1 of jbi_l2_buf2.v
wire sctag3_jbi_por_req_d2; // From ff_jbi_sc3_1 of ff_jbi_sc3_1.v
wire sctag3_jbi_wib_dequeue; // From sctag3 of sctag.v
wire sctag3_jbi_wib_dequeue_d1;// From ff_jbi_sc3_2 of ff_jbi_sc3_2.v
wire sctag3_jbi_wib_dequeue_d1_buf1;// From rep_jbi_sc3_1 of jbi_l2_buf2.v
wire sctag3_jbi_wib_dequeue_d2;// From ff_jbi_sc3_1 of ff_jbi_sc3_1.v
wire sctag3_pcx_stall_pq; // To/From v_m_help of v_m_help.v, ...
wire [14:0] sctag3_scbuf3_ctag_c7; // From sctag3 of sctag.v
wire [14:0] sctag3_scbuf3_ctag_c7_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire sctag3_scbuf3_ctag_en_c7;// From sctag3 of sctag.v
wire sctag3_scbuf3_ctag_en_c7_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire [2:0] sctag3_scbuf3_ev_dword_r0;// From sctag3 of sctag.v
wire [2:0] sctag3_scbuf3_ev_dword_r0_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire sctag3_scbuf3_evict_en_r0;// From sctag3 of sctag.v
wire sctag3_scbuf3_evict_en_r0_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire sctag3_scbuf3_fbd_stdatasel_c3;// From sctag3 of sctag.v
wire sctag3_scbuf3_fbd_stdatasel_c3_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire sctag3_scbuf3_fbrd_en_c3;// From sctag3 of sctag.v
wire sctag3_scbuf3_fbrd_en_c3_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire [2:0] sctag3_scbuf3_fbrd_wl_c3;// From sctag3 of sctag.v
wire [2:0] sctag3_scbuf3_fbrd_wl_c3_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire [15:0] sctag3_scbuf3_fbwr_wen_r2;// From sctag3 of sctag.v
wire [15:0] sctag3_scbuf3_fbwr_wen_r2_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire [2:0] sctag3_scbuf3_fbwr_wl_r2;// From sctag3 of sctag.v
wire [2:0] sctag3_scbuf3_fbwr_wl_r2_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire sctag3_scbuf3_rdma_rden_r0;// From sctag3 of sctag.v
wire sctag3_scbuf3_rdma_rden_r0_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire [1:0] sctag3_scbuf3_rdma_rdwl_r0;// From sctag3 of sctag.v
wire [1:0] sctag3_scbuf3_rdma_rdwl_r0_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire [15:0] sctag3_scbuf3_rdma_wren_s2;// From sctag3 of sctag.v
wire [15:0] sctag3_scbuf3_rdma_wren_s2_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire [1:0] sctag3_scbuf3_rdma_wrwl_s2;// From sctag3 of sctag.v
wire [1:0] sctag3_scbuf3_rdma_wrwl_s2_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire sctag3_scbuf3_req_en_c7;// From sctag3 of sctag.v
wire sctag3_scbuf3_req_en_c7_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire [77:0] sctag3_scbuf3_stdecc_c3;// From sctag3 of sctag.v
wire [77:0] sctag3_scbuf3_stdecc_c3_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire sctag3_scbuf3_wbrd_en_r0;// From sctag3 of sctag.v
wire sctag3_scbuf3_wbrd_en_r0_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire [2:0] sctag3_scbuf3_wbrd_wl_r0;// From sctag3 of sctag.v
wire [2:0] sctag3_scbuf3_wbrd_wl_r0_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire [3:0] sctag3_scbuf3_wbwr_wen_c6;// From sctag3 of sctag.v
wire [3:0] sctag3_scbuf3_wbwr_wen_c6_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire [2:0] sctag3_scbuf3_wbwr_wl_c6;// From sctag3 of sctag.v
wire [2:0] sctag3_scbuf3_wbwr_wl_c6_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire [3:0] sctag3_scbuf3_word_c7; // From sctag3 of sctag.v
wire [3:0] sctag3_scbuf3_word_c7_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire sctag3_scbuf3_word_vld_c7;// From sctag3 of sctag.v
wire sctag3_scbuf3_word_vld_c7_buf;// From sctag_scbuf_rptr3 of sctag_scbuf_rptr3.v
wire [3:0] sctag3_scdata3_col_offset_c2;// From sctag3 of sctag.v
wire sctag3_scdata3_fb_hit_c3;// From sctag3 of sctag.v
wire sctag3_scdata3_fbrd_c3; // From sctag3 of sctag.v
wire sctag3_scdata3_rd_wr_c2;// From sctag3 of sctag.v
wire [9:0] sctag3_scdata3_set_c2; // From sctag3 of sctag.v
wire [77:0] sctag3_scdata3_stdecc_c2;// From sctag3 of sctag.v
wire [11:0] sctag3_scdata3_way_sel_c2;// From sctag3 of sctag.v
wire [15:0] sctag3_scdata3_word_en_c2;// From sctag3 of sctag.v
wire [30:0] ser_scan_out; // To/From v_m_help of v_m_help.v
wire spc0_ctu_mbistdone; // To/From v_m_help of v_m_help.v, ...
wire spc0_ctu_mbistdone_buf2;// To/From v_m_help of v_m_help.v, ...
wire spc0_ctu_mbisterr; // To/From v_m_help of v_m_help.v, ...
wire spc0_ctu_mbisterr_buf2; // To/From v_m_help of v_m_help.v, ...
wire spc0_ctu_sscan_out; // From sparc0 of sparc.v
wire spc0_efc_dfuse_data; // From sparc0 of sparc.v
wire spc0_efc_ifuse_data; // From sparc0 of sparc.v
wire spc0_pcx_atom_pq; // From sparc0 of sparc.v
wire spc0_pcx_atom_pq_buf; // From buf_pcx_0 of spc_pcx_buf.v
wire spc0_pcx_atom_pq_buf1; // From ccx_spc_rpt0 of ccx_spc_rpt.v
wire [`PCX_WIDTH-1:0]spc0_pcx_data_pa; // From sparc0 of sparc.v
wire [`PCX_WIDTH-1:0]spc0_pcx_data_pa_buf; // From buf_pcx_0 of spc_pcx_buf.v
wire [`PCX_WIDTH-1:0]spc0_pcx_data_pa_buf1; // From ccx_spc_rpt0 of ccx_spc_rpt.v
wire [4:0] spc0_pcx_req_pq; // From sparc0 of sparc.v
wire [4:0] spc0_pcx_req_pq_buf; // From buf_pcx_0 of spc_pcx_buf.v
wire [4:0] spc0_pcx_req_pq_buf1; // From ccx_spc_rpt0 of ccx_spc_rpt.v
wire spc1_ctu_mbistdone; // To/From v_m_help of v_m_help.v, ...
wire spc1_ctu_mbistdone_buf2;// To/From v_m_help of v_m_help.v, ...
wire spc1_ctu_mbisterr; // To/From v_m_help of v_m_help.v, ...
wire spc1_ctu_mbisterr_buf2; // To/From v_m_help of v_m_help.v, ...
wire spc1_ctu_sscan_out; // From sparc1 of sparc.v
wire spc1_efc_dfuse_data; // From sparc1 of sparc.v
wire spc1_efc_ifuse_data; // From sparc1 of sparc.v
wire spc1_pcx_atom_pq; // From sparc1 of sparc.v
wire spc1_pcx_atom_pq_buf; // From buf_pcx_1 of spc_pcx_buf.v
wire spc1_pcx_atom_pq_buf1; // From ccx_spc_rpt1 of ccx_spc_rpt.v
wire [`PCX_WIDTH-1:0]spc1_pcx_data_pa; // From sparc1 of sparc.v
wire [`PCX_WIDTH-1:0]spc1_pcx_data_pa_buf; // From buf_pcx_1 of spc_pcx_buf.v
wire [`PCX_WIDTH-1:0]spc1_pcx_data_pa_buf1; // From ccx_spc_rpt1 of ccx_spc_rpt.v
wire [4:0] spc1_pcx_req_pq; // From sparc1 of sparc.v
wire [4:0] spc1_pcx_req_pq_buf; // From buf_pcx_1 of spc_pcx_buf.v
wire [4:0] spc1_pcx_req_pq_buf1; // From ccx_spc_rpt1 of ccx_spc_rpt.v
wire spc2_ctu_mbistdone; // To/From v_m_help of v_m_help.v, ...
wire spc2_ctu_mbistdone_buf2;// To/From v_m_help of v_m_help.v, ...
wire spc2_ctu_mbisterr; // To/From v_m_help of v_m_help.v, ...
wire spc2_ctu_mbisterr_buf2; // To/From v_m_help of v_m_help.v, ...
wire spc2_ctu_sscan_out; // From sparc2 of sparc.v
wire spc2_efc_dfuse_data; // From sparc2 of sparc.v
wire spc2_efc_ifuse_data; // From sparc2 of sparc.v
wire spc2_pcx_atom_pq; // From sparc2 of sparc.v
wire spc2_pcx_atom_pq_buf; // From buf_pcx_2 of spc_pcx_buf.v
wire spc2_pcx_atom_pq_buf1; // From ccx_spc_rpt2 of ccx_spc_rpt.v
wire [`PCX_WIDTH-1:0]spc2_pcx_data_pa; // From sparc2 of sparc.v
wire [`PCX_WIDTH-1:0]spc2_pcx_data_pa_buf; // From buf_pcx_2 of spc_pcx_buf.v
wire [`PCX_WIDTH-1:0]spc2_pcx_data_pa_buf1; // From ccx_spc_rpt2 of ccx_spc_rpt.v
wire [4:0] spc2_pcx_req_pq; // From sparc2 of sparc.v
wire [4:0] spc2_pcx_req_pq_buf; // From buf_pcx_2 of spc_pcx_buf.v
wire [4:0] spc2_pcx_req_pq_buf1; // From ccx_spc_rpt2 of ccx_spc_rpt.v
wire spc3_ctu_mbistdone; // To/From v_m_help of v_m_help.v, ...
wire spc3_ctu_mbistdone_buf2;// To/From v_m_help of v_m_help.v, ...
wire spc3_ctu_mbisterr; // To/From v_m_help of v_m_help.v, ...
wire spc3_ctu_mbisterr_buf2; // To/From v_m_help of v_m_help.v, ...
wire spc3_ctu_sscan_out; // From sparc3 of sparc.v
wire spc3_efc_dfuse_data; // From sparc3 of sparc.v
wire spc3_efc_ifuse_data; // From sparc3 of sparc.v
wire spc3_pcx_atom_pq; // From sparc3 of sparc.v
wire spc3_pcx_atom_pq_buf; // From buf_pcx_3 of spc_pcx_buf.v
wire spc3_pcx_atom_pq_buf1; // From ccx_spc_rpt3 of ccx_spc_rpt.v
wire [`PCX_WIDTH-1:0]spc3_pcx_data_pa; // From sparc3 of sparc.v
wire [`PCX_WIDTH-1:0]spc3_pcx_data_pa_buf; // From buf_pcx_3 of spc_pcx_buf.v
wire [`PCX_WIDTH-1:0]spc3_pcx_data_pa_buf1; // From ccx_spc_rpt3 of ccx_spc_rpt.v
wire [4:0] spc3_pcx_req_pq; // From sparc3 of sparc.v
wire [4:0] spc3_pcx_req_pq_buf; // From buf_pcx_3 of spc_pcx_buf.v
wire [4:0] spc3_pcx_req_pq_buf1; // From ccx_spc_rpt3 of ccx_spc_rpt.v
wire spc4_ctu_mbistdone; // To/From v_m_help of v_m_help.v, ...
wire spc4_ctu_mbistdone_buf2;// To/From v_m_help of v_m_help.v, ...
wire spc4_ctu_mbisterr; // To/From v_m_help of v_m_help.v, ...
wire spc4_ctu_mbisterr_buf2; // To/From v_m_help of v_m_help.v, ...
wire spc4_ctu_sscan_out; // From sparc4 of sparc.v
wire spc4_efc_dfuse_data; // From sparc4 of sparc.v
wire spc4_efc_ifuse_data; // From sparc4 of sparc.v
wire spc4_pcx_atom_pq; // From sparc4 of sparc.v
wire spc4_pcx_atom_pq_buf; // From buf_pcx_4 of spc_pcx_buf.v
wire spc4_pcx_atom_pq_buf1; // From ccx_spc_rpt4 of ccx_spc_rpt.v
wire [`PCX_WIDTH-1:0]spc4_pcx_data_pa; // From sparc4 of sparc.v
wire [`PCX_WIDTH-1:0]spc4_pcx_data_pa_buf; // From buf_pcx_4 of spc_pcx_buf.v
wire [`PCX_WIDTH-1:0]spc4_pcx_data_pa_buf1; // From ccx_spc_rpt4 of ccx_spc_rpt.v
wire [4:0] spc4_pcx_req_pq; // From sparc4 of sparc.v
wire [4:0] spc4_pcx_req_pq_buf; // From buf_pcx_4 of spc_pcx_buf.v
wire [4:0] spc4_pcx_req_pq_buf1; // From ccx_spc_rpt4 of ccx_spc_rpt.v
wire spc5_ctu_mbistdone; // To/From v_m_help of v_m_help.v, ...
wire spc5_ctu_mbistdone_buf2;// To/From v_m_help of v_m_help.v, ...
wire spc5_ctu_mbisterr; // To/From v_m_help of v_m_help.v, ...
wire spc5_ctu_mbisterr_buf2; // To/From v_m_help of v_m_help.v, ...
wire spc5_ctu_sscan_out; // From sparc5 of sparc.v
wire spc5_efc_dfuse_data; // From sparc5 of sparc.v
wire spc5_efc_ifuse_data; // From sparc5 of sparc.v
wire spc5_pcx_atom_pq; // From sparc5 of sparc.v
wire spc5_pcx_atom_pq_buf; // From buf_pcx_5 of spc_pcx_buf.v
wire spc5_pcx_atom_pq_buf1; // From ccx_spc_rpt5 of ccx_spc_rpt.v
wire [`PCX_WIDTH-1:0]spc5_pcx_data_pa; // From sparc5 of sparc.v
wire [`PCX_WIDTH-1:0]spc5_pcx_data_pa_buf; // From buf_pcx_5 of spc_pcx_buf.v
wire [`PCX_WIDTH-1:0]spc5_pcx_data_pa_buf1; // From ccx_spc_rpt5 of ccx_spc_rpt.v
wire [4:0] spc5_pcx_req_pq; // From sparc5 of sparc.v
wire [4:0] spc5_pcx_req_pq_buf; // From buf_pcx_5 of spc_pcx_buf.v
wire [4:0] spc5_pcx_req_pq_buf1; // From ccx_spc_rpt5 of ccx_spc_rpt.v
wire spc6_ctu_mbistdone; // To/From v_m_help of v_m_help.v, ...
wire spc6_ctu_mbistdone_buf2;// To/From v_m_help of v_m_help.v, ...
wire spc6_ctu_mbisterr; // To/From v_m_help of v_m_help.v, ...
wire spc6_ctu_mbisterr_buf2; // To/From v_m_help of v_m_help.v, ...
wire spc6_ctu_sscan_out; // From sparc6 of sparc.v
wire spc6_efc_dfuse_data; // From sparc6 of sparc.v
wire spc6_efc_ifuse_data; // From sparc6 of sparc.v
wire spc6_pcx_atom_pq; // From sparc6 of sparc.v
wire spc6_pcx_atom_pq_buf; // From buf_pcx_6 of spc_pcx_buf.v
wire spc6_pcx_atom_pq_buf1; // From ccx_spc_rpt6 of ccx_spc_rpt.v
wire [`PCX_WIDTH-1:0]spc6_pcx_data_pa; // From sparc6 of sparc.v
wire [`PCX_WIDTH-1:0]spc6_pcx_data_pa_buf; // From buf_pcx_6 of spc_pcx_buf.v
wire [`PCX_WIDTH-1:0]spc6_pcx_data_pa_buf1; // From ccx_spc_rpt6 of ccx_spc_rpt.v
wire [4:0] spc6_pcx_req_pq; // From sparc6 of sparc.v
wire [4:0] spc6_pcx_req_pq_buf; // From buf_pcx_6 of spc_pcx_buf.v
wire [4:0] spc6_pcx_req_pq_buf1; // From ccx_spc_rpt6 of ccx_spc_rpt.v
wire spc7_ctu_mbistdone; // To/From v_m_help of v_m_help.v, ...
wire spc7_ctu_mbistdone_buf2;// To/From v_m_help of v_m_help.v, ...
wire spc7_ctu_mbisterr; // To/From v_m_help of v_m_help.v, ...
wire spc7_ctu_mbisterr_buf2; // To/From v_m_help of v_m_help.v, ...
wire spc7_ctu_sscan_out; // From sparc7 of sparc.v
wire spc7_efc_dfuse_data; // From sparc7 of sparc.v
wire spc7_efc_ifuse_data; // From sparc7 of sparc.v
wire spc7_pcx_atom_pq; // From sparc7 of sparc.v
wire spc7_pcx_atom_pq_buf; // From buf_pcx_7 of spc_pcx_buf.v
wire spc7_pcx_atom_pq_buf1; // From ccx_spc_rpt7 of ccx_spc_rpt.v
wire [`PCX_WIDTH-1:0]spc7_pcx_data_pa; // From sparc7 of sparc.v
wire [`PCX_WIDTH-1:0]spc7_pcx_data_pa_buf; // From buf_pcx_7 of spc_pcx_buf.v
wire [`PCX_WIDTH-1:0]spc7_pcx_data_pa_buf1; // From ccx_spc_rpt7 of ccx_spc_rpt.v
wire [4:0] spc7_pcx_req_pq; // From sparc7 of sparc.v
wire [4:0] spc7_pcx_req_pq_buf; // From buf_pcx_7 of spc_pcx_buf.v
wire [4:0] spc7_pcx_req_pq_buf1; // From ccx_spc_rpt7 of ccx_spc_rpt.v
wire [7:0] tap_iob_data; // From ctu of ctu.v
wire tap_iob_stall; // From ctu of ctu.v
wire tap_iob_vld; // From ctu of ctu.v
// End of automatics
wire [143:0] ddr0_afo = 144'b0;
wire [143:0] ddr1_afo = 144'b0;
wire [143:0] ddr2_afo = 144'b0;
wire [143:0] ddr3_afo = 144'b0;
wire [143:0] ddr0_sin = 144'b0;
wire [143:0] ddr1_sin = 144'b0;
wire [143:0] ddr2_sin = 144'b0;
wire [143:0] ddr3_sin = 144'b0;
wire [ 56: 0] jbusr_sin= 57'b0;
wire [127:57] jbusl_sin= 71'b0;
wire [127:57] dbg_sin = 71'b0;
wire [127:57] dbg_from_core_unused = 71'b0;
wire [143:0] ddr0_sot;
wire [143:0] ddr1_sot;
wire [143:0] ddr2_sot;
wire [143:0] ddr3_sot;
wire [ 56: 0] jbusr_sot;
wire [127:57] jbusl_sot;
wire [127:57] dbg_sot;
wire [143:0] ddr0_afi;
wire [143:0] ddr1_afi;
wire [143:0] ddr2_afi;
wire [143:0] ddr3_afi;
wire [255:0] io_dram0_data_in_buf0;
wire [31:0] io_dram0_ecc_in_buf0;
wire [255:0] io_dram0_data_in_buf2;
wire [31:0] io_dram0_ecc_in_buf2;
wire [255:0] io_dram0_data_in_buf1;
wire [31:0] io_dram0_ecc_in_buf1;
wire [255:0] io_dram1_data_in_buf0;
wire [31:0] io_dram1_ecc_in_buf0;
wire [255:0] io_dram1_data_in_buf2;
wire [31:0] io_dram1_ecc_in_buf2;
wire [255:0] io_dram1_data_in_buf1;
wire [31:0] io_dram1_ecc_in_buf1;
wire [255:0] io_dram2_data_in_buf0;
wire [31:0] io_dram2_ecc_in_buf0;
wire [255:0] io_dram2_data_in_buf2;
wire [31:0] io_dram2_ecc_in_buf2;
wire [255:0] io_dram2_data_in_buf1;
wire [31:0] io_dram2_ecc_in_buf1;
wire [255:0] io_dram3_data_in_buf0;
wire [31:0] io_dram3_ecc_in_buf0;
wire [255:0] io_dram3_data_in_buf2;
wire [31:0] io_dram3_ecc_in_buf2;
wire [255:0] io_dram3_data_in_buf1;
wire [31:0] io_dram3_ecc_in_buf1;
wire [4:0] dram0_io_ptr_clk_inv_buf0;
wire [14:0] dram0_io_addr_buf0;
wire [287:0] dram0_io_data_out_buf0;
wire [3:0] dram0_io_cs_l_buf0;
wire [2:0] dram0_io_bank_buf0;
wire [4:0] dram0_io_ptr_clk_inv_buf1;
wire [14:0] dram0_io_addr_buf1;
wire [287:0] dram0_io_data_out_buf1;
wire [3:0] dram0_io_cs_l_buf1;
wire [2:0] dram0_io_bank_buf1;
wire [4:0] dram0_io_ptr_clk_inv_buf2;
wire [14:0] dram0_io_addr_buf2;
wire [287:0] dram0_io_data_out_buf2;
wire [3:0] dram0_io_cs_l_buf2;
wire [2:0] dram0_io_bank_buf2;
wire [4:0] dram1_io_ptr_clk_inv_buf0;
wire [14:0] dram1_io_addr_buf0;
wire [287:0] dram1_io_data_out_buf0;
wire [3:0] dram1_io_cs_l_buf0;
wire [2:0] dram1_io_bank_buf0;
wire [4:0] dram1_io_ptr_clk_inv_buf1;
wire [14:0] dram1_io_addr_buf1;
wire [287:0] dram1_io_data_out_buf1;
wire [3:0] dram1_io_cs_l_buf1;
wire [2:0] dram1_io_bank_buf1;
wire [4:0] dram1_io_ptr_clk_inv_buf2;
wire [14:0] dram1_io_addr_buf2;
wire [287:0] dram1_io_data_out_buf2;
wire [3:0] dram1_io_cs_l_buf2;
wire [2:0] dram1_io_bank_buf2;
wire [4:0] dram2_io_ptr_clk_inv_buf0;
wire [14:0] dram2_io_addr_buf0;
wire [287:0] dram2_io_data_out_buf0;
wire [3:0] dram2_io_cs_l_buf0;
wire [2:0] dram2_io_bank_buf0;
wire [4:0] dram2_io_ptr_clk_inv_buf1;
wire [14:0] dram2_io_addr_buf1;
wire [287:0] dram2_io_data_out_buf1;
wire [3:0] dram2_io_cs_l_buf1;
wire [2:0] dram2_io_bank_buf1;
wire [4:0] dram2_io_ptr_clk_inv_buf2;
wire [14:0] dram2_io_addr_buf2;
wire [287:0] dram2_io_data_out_buf2;
wire [3:0] dram2_io_cs_l_buf2;
wire [2:0] dram2_io_bank_buf2;
wire [4:0] dram3_io_ptr_clk_inv_buf0;
wire [14:0] dram3_io_addr_buf0;
wire [287:0] dram3_io_data_out_buf0;
wire [3:0] dram3_io_cs_l_buf0;
wire [2:0] dram3_io_bank_buf0;
wire [4:0] dram3_io_ptr_clk_inv_buf1;
wire [14:0] dram3_io_addr_buf1;
wire [287:0] dram3_io_data_out_buf1;
wire [3:0] dram3_io_cs_l_buf1;
wire [2:0] dram3_io_bank_buf1;
wire [4:0] dram3_io_ptr_clk_inv_buf2;
wire [14:0] dram3_io_addr_buf2;
wire [287:0] dram3_io_data_out_buf2;
wire [3:0] dram3_io_cs_l_buf2;
wire [2:0] dram3_io_bank_buf2;
wire [127:57] dbg_to_core_unused;
wire [19:0] ctu_top_rptr_unused;
wire [19:0] ctu_top_rptr2_unused;
wire [19:0] ctu_bottom_rptr_unused;
wire [19:0] ctu_bottom_rptr2_unused;
wire [36:0] unused_sctag_pcx_rptr_0i;
wire [36:0] unused_sctag_pcx_rptr_0;
wire [36:0] unused_sctag_pcx_rptr_1i;
wire [36:0] unused_sctag_pcx_rptr_1;
wire [36:0] unused_sctag_pcx_rptr_2i;
wire [36:0] unused_sctag_pcx_rptr_2;
wire [36:0] unused_sctag_pcx_rptr_3i;
wire [36:0] unused_sctag_pcx_rptr_3;
wire [`PCX_WIDTH-1:0]pcx_sctag0_data_px2_buf;
wire [`PCX_WIDTH-1:0]pcx_sctag1_data_px2_buf;
wire [`PCX_WIDTH-1:0]pcx_sctag2_data_px2_buf;
wire [`PCX_WIDTH-1:0]pcx_sctag3_data_px2_buf;
wire sctag0_pcx_stall_pq_buf;
wire sctag1_pcx_stall_pq_buf;
wire sctag2_pcx_stall_pq_buf;
wire sctag3_pcx_stall_pq_buf;
wire pcx_sctag0_data_rdy_px1_buf;
wire pcx_sctag1_data_rdy_px1_buf;
wire pcx_sctag2_data_rdy_px1_buf;
wire pcx_sctag3_data_rdy_px1_buf;
wire pcx_sctag0_atm_px1_buf;
wire pcx_sctag1_atm_px1_buf;
wire pcx_sctag2_atm_px1_buf;
wire pcx_sctag3_atm_px1_buf;
wire [1:0] unused_sctag_cpx_rptr_0i;
wire [1:0] unused_sctag_cpx_rptr_0;
wire [1:0] unused_sctag_cpx_rptr_1i;
wire [1:0] unused_sctag_cpx_rptr_1;
wire [1:0] unused_sctag_cpx_rptr_2i;
wire [1:0] unused_sctag_cpx_rptr_2;
wire [1:0] unused_sctag_cpx_rptr_3i;
wire [1:0] unused_sctag_cpx_rptr_3;
wire [7:0] cpx_sctag0_grant_cx_buf;
wire [7:0] cpx_sctag1_grant_cx_buf;
wire [7:0] cpx_sctag2_grant_cx_buf;
wire [7:0] cpx_sctag3_grant_cx_buf;
wire [7:0] sctag0_cpx_req_cq_buf;
wire [7:0] sctag1_cpx_req_cq_buf;
wire [7:0] sctag2_cpx_req_cq_buf;
wire [7:0] sctag3_cpx_req_cq_buf;
wire sctag0_cpx_atom_cq_buf;
wire sctag1_cpx_atom_cq_buf;
wire sctag2_cpx_atom_cq_buf;
wire sctag3_cpx_atom_cq_buf;
wire [`CPX_WIDTH-1:0]sctag0_cpx_data_ca_buf;
wire [`CPX_WIDTH-1:0]sctag1_cpx_data_ca_buf;
wire [`CPX_WIDTH-1:0]sctag2_cpx_data_ca_buf;
wire [`CPX_WIDTH-1:0]sctag3_cpx_data_ca_buf;
wire [7:0] cpx_iob_grant_cx2_buf;
wire [`PCX_WIDTH-1:0]pcx_iob_data_px2_buf;
wire pcx_iob_data_rdy_px2_buf;
wire [2:0] unused_ccx_iob_rptri;
wire [2:0] unused_ccx_iob_rptr;
wire [`CPX_WIDTH-1:0]iob_cpx_data_ca_buf;
wire [`IOB_CPU_WIDTH-1:0]iob_cpx_req_cq_buf;
wire iob_pcx_stall_pq_buf;
wire [9:0] unused_iob_ccx_rptr_bufi;
wire [9:0] unused_iob_ccx_rptr_buf;
wire [47:0] iob_jbi_dbg_hi_data_buf;
wire [47:0] iob_jbi_dbg_lo_data_buf;
wire [`IOB_JBI_WIDTH-1:0]iob_jbi_pio_data_buf;
wire [`IOB_SPI_WIDTH-1:0]iob_jbi_spi_data_buf;
wire [`JBI_IOB_MONDO_BUS_WIDTH-1:0]jbi_iob_mondo_data_buf;
wire jbi_iob_mondo_vld_buf;
wire [`JBI_IOB_WIDTH-1:0]jbi_iob_pio_data_buf;
wire jbi_iob_pio_stall_buf;
wire jbi_iob_pio_vld_buf;
wire [`SPI_IOB_WIDTH-1:0]jbi_iob_spi_data_buf;
wire jbi_iob_spi_stall_buf;
wire jbi_iob_spi_vld_buf;
wire iob_jbi_dbg_hi_vld_buf;
wire iob_jbi_dbg_lo_vld_buf;
wire iob_jbi_mondo_ack_buf;
wire iob_jbi_mondo_nack_buf;
wire iob_jbi_pio_stall_buf;
wire iob_jbi_pio_vld_buf;
wire iob_jbi_spi_stall_buf;
wire iob_jbi_spi_vld_buf;
wire [94:0] unused_iob_jbi_rptr_1i;
wire [94:0] unused_iob_jbi_rptr_1;
assign VDD_SENSE = 1'b1;
assign VSS_SENSE = 1'b0;
`ifdef DO_NOT_DEFINE_VERILOG_MODE_EXPAND
v_m_help v_m_help
(/*AUTOINST*/
// Inouts
.afi_bist_mode (afi_bist_mode),
.afi_bypass_mode (afi_bypass_mode),
.afi_pll_char_mode (afi_pll_char_mode),
.afi_pll_clamp_fltr (afi_pll_clamp_fltr),
.afi_pll_div2 (afi_pll_div2[5:0]),
.afi_pll_trst_l (afi_pll_trst_l),
.afi_rng_ctl (afi_rng_ctl[2:0]),
.afi_rt_addr_data (afi_rt_addr_data),
.afi_rt_data_in (afi_rt_data_in[31:0]),
.afi_rt_high_low (afi_rt_high_low),
.afi_rt_read_write (afi_rt_read_write),
.afi_rt_valid (afi_rt_valid),
.afi_tsr_div (afi_tsr_div[9:1]),
.afi_tsr_mode (afi_tsr_mode),
.afi_tsr_tsel (afi_tsr_tsel[7:0]),
.afo_rng_clk (afo_rng_clk),
.afo_rng_data (afo_rng_data),
.afo_rt_ack (afo_rt_ack),
.afo_rt_data_out (afo_rt_data_out[31:0]),
.afo_tsr_dout (afo_tsr_dout[7:0]),
.cpx_iob_grant_cx2 (cpx_iob_grant_cx2[7:0]),
.cpx_sctag0_grant_cx (cpx_sctag0_grant_cx[7:0]),
.cpx_sctag1_grant_cx (cpx_sctag1_grant_cx[7:0]),
.cpx_sctag2_grant_cx (cpx_sctag2_grant_cx[7:0]),
.cpx_sctag3_grant_cx (cpx_sctag3_grant_cx[7:0]),
.ctu_sctag0_mbisten (ctu_sctag0_mbisten),
.ctu_sctag0_mbisten_buf2 (ctu_sctag0_mbisten_buf2),
.ctu_sctag0_mbisten_buf2 (ctu_sctag0_mbisten_buf2),
.ctu_sctag1_mbisten (ctu_sctag1_mbisten),
.ctu_sctag1_mbisten_buf2 (ctu_sctag1_mbisten_buf2),
.ctu_sctag1_mbisten_buf2 (ctu_sctag1_mbisten_buf2),
.ctu_sctag2_mbisten (ctu_sctag2_mbisten),
.ctu_sctag2_mbisten_buf2 (ctu_sctag2_mbisten_buf2),
.ctu_sctag2_mbisten_buf2 (ctu_sctag2_mbisten_buf2),
.ctu_sctag3_mbisten (ctu_sctag3_mbisten),
.ctu_sctag3_mbisten_buf2 (ctu_sctag3_mbisten_buf2),
.ctu_sctag3_mbisten_buf2 (ctu_sctag3_mbisten_buf2),
.ctu_spc0_mbisten (ctu_spc0_mbisten),
.ctu_spc0_mbisten_buf2 (ctu_spc0_mbisten_buf2),
.ctu_spc0_mbisten_buf2 (ctu_spc0_mbisten_buf2),
.ctu_spc1_mbisten (ctu_spc1_mbisten),
.ctu_spc1_mbisten_buf2 (ctu_spc1_mbisten_buf2),
.ctu_spc1_mbisten_buf2 (ctu_spc1_mbisten_buf2),
.ctu_spc2_mbisten (ctu_spc2_mbisten),
.ctu_spc2_mbisten_buf2 (ctu_spc2_mbisten_buf2),
.ctu_spc2_mbisten_buf2 (ctu_spc2_mbisten_buf2),
.ctu_spc3_mbisten (ctu_spc3_mbisten),
.ctu_spc3_mbisten_buf2 (ctu_spc3_mbisten_buf2),
.ctu_spc3_mbisten_buf2 (ctu_spc3_mbisten_buf2),
.ctu_spc4_mbisten (ctu_spc4_mbisten),
.ctu_spc4_mbisten_buf2 (ctu_spc4_mbisten_buf2),
.ctu_spc4_mbisten_buf2 (ctu_spc4_mbisten_buf2),
.ctu_spc5_mbisten (ctu_spc5_mbisten),
.ctu_spc5_mbisten_buf2 (ctu_spc5_mbisten_buf2),
.ctu_spc5_mbisten_buf2 (ctu_spc5_mbisten_buf2),
.ctu_spc6_mbisten (ctu_spc6_mbisten),
.ctu_spc6_mbisten_buf2 (ctu_spc6_mbisten_buf2),
.ctu_spc6_mbisten_buf2 (ctu_spc6_mbisten_buf2),
.ctu_spc7_mbisten (ctu_spc7_mbisten),
.ctu_spc7_mbisten_buf2 (ctu_spc7_mbisten_buf2),
.ctu_spc7_mbisten_buf2 (ctu_spc7_mbisten_buf2),
.dram0_io_addr (dram0_io_addr[14:0]),
.dram0_io_bank (dram0_io_bank[2:0]),
.dram0_io_cas_l (dram0_io_cas_l),
.dram0_io_cas_l_buf2 (dram0_io_cas_l_buf2),
.dram0_io_channel_disabled (dram0_io_channel_disabled),
.dram0_io_channel_disabled_buf2 (dram0_io_channel_disabled_buf2),
.dram0_io_cke (dram0_io_cke),
.dram0_io_cke_buf2 (dram0_io_cke_buf2),
.dram0_io_clk_enable (dram0_io_clk_enable),
.dram0_io_clk_enable_buf2 (dram0_io_clk_enable_buf2),
.dram0_io_cs_l (dram0_io_cs_l[3:0]),
.dram0_io_data_out (dram0_io_data_out[287:0]),
.dram0_io_drive_data (dram0_io_drive_data),
.dram0_io_drive_data_buf2 (dram0_io_drive_data_buf2),
.dram0_io_drive_enable (dram0_io_drive_enable),
.dram0_io_drive_enable_buf2 (dram0_io_drive_enable_buf2),
.dram0_io_pad_clk_inv (dram0_io_pad_clk_inv),
.dram0_io_pad_clk_inv_buf2 (dram0_io_pad_clk_inv_buf2),
.dram0_io_pad_enable (dram0_io_pad_enable),
.dram0_io_pad_enable_buf2 (dram0_io_pad_enable_buf2),
.dram0_io_ptr_clk_inv (dram0_io_ptr_clk_inv[4:0]),
.dram0_io_ras_l (dram0_io_ras_l),
.dram0_io_ras_l_buf2 (dram0_io_ras_l_buf2),
.dram0_io_write_en_l (dram0_io_write_en_l),
.dram0_io_write_en_l_buf2 (dram0_io_write_en_l_buf2),
.dram1_io_addr (dram1_io_addr[14:0]),
.dram1_io_bank (dram1_io_bank[2:0]),
.dram1_io_cas_l (dram1_io_cas_l),
.dram1_io_cas_l_buf2 (dram1_io_cas_l_buf2),
.dram1_io_channel_disabled (dram1_io_channel_disabled),
.dram1_io_channel_disabled_buf2 (dram1_io_channel_disabled_buf2),
.dram1_io_cke (dram1_io_cke),
.dram1_io_cke_buf2 (dram1_io_cke_buf2),
.dram1_io_clk_enable (dram1_io_clk_enable),
.dram1_io_clk_enable_buf2 (dram1_io_clk_enable_buf2),
.dram1_io_cs_l (dram1_io_cs_l[3:0]),
.dram1_io_data_out (dram1_io_data_out[287:0]),
.dram1_io_drive_data (dram1_io_drive_data),
.dram1_io_drive_data_buf2 (dram1_io_drive_data_buf2),
.dram1_io_drive_enable (dram1_io_drive_enable),
.dram1_io_drive_enable_buf2 (dram1_io_drive_enable_buf2),
.dram1_io_pad_clk_inv (dram1_io_pad_clk_inv),
.dram1_io_pad_clk_inv_buf2 (dram1_io_pad_clk_inv_buf2),
.dram1_io_pad_enable (dram1_io_pad_enable),
.dram1_io_pad_enable_buf2 (dram1_io_pad_enable_buf2),
.dram1_io_ptr_clk_inv (dram1_io_ptr_clk_inv[4:0]),
.dram1_io_ras_l (dram1_io_ras_l),
.dram1_io_ras_l_buf2 (dram1_io_ras_l_buf2),
.dram1_io_write_en_l (dram1_io_write_en_l),
.dram1_io_write_en_l_buf2 (dram1_io_write_en_l_buf2),
.dram2_io_addr (dram2_io_addr[14:0]),
.dram2_io_bank (dram2_io_bank[2:0]),
.dram2_io_cas_l (dram2_io_cas_l),
.dram2_io_cas_l_buf2 (dram2_io_cas_l_buf2),
.dram2_io_channel_disabled (dram2_io_channel_disabled),
.dram2_io_channel_disabled_buf2 (dram2_io_channel_disabled_buf2),
.dram2_io_cke (dram2_io_cke),
.dram2_io_cke_buf2 (dram2_io_cke_buf2),
.dram2_io_clk_enable (dram2_io_clk_enable),
.dram2_io_clk_enable_buf2 (dram2_io_clk_enable_buf2),
.dram2_io_cs_l (dram2_io_cs_l[3:0]),
.dram2_io_data_out (dram2_io_data_out[287:0]),
.dram2_io_drive_data (dram2_io_drive_data),
.dram2_io_drive_data_buf2 (dram2_io_drive_data_buf2),
.dram2_io_drive_enable (dram2_io_drive_enable),
.dram2_io_drive_enable_buf2 (dram2_io_drive_enable_buf2),
.dram2_io_pad_clk_inv (dram2_io_pad_clk_inv),
.dram2_io_pad_clk_inv_buf2 (dram2_io_pad_clk_inv_buf2),
.dram2_io_pad_enable (dram2_io_pad_enable),
.dram2_io_pad_enable_buf2 (dram2_io_pad_enable_buf2),
.dram2_io_ptr_clk_inv (dram2_io_ptr_clk_inv[4:0]),
.dram2_io_ras_l (dram2_io_ras_l),
.dram2_io_ras_l_buf2 (dram2_io_ras_l_buf2),
.dram2_io_write_en_l (dram2_io_write_en_l),
.dram2_io_write_en_l_buf2 (dram2_io_write_en_l_buf2),
.dram3_io_addr (dram3_io_addr[14:0]),
.dram3_io_bank (dram3_io_bank[2:0]),
.dram3_io_cas_l (dram3_io_cas_l),
.dram3_io_cas_l_buf2 (dram3_io_cas_l_buf2),
.dram3_io_channel_disabled (dram3_io_channel_disabled),
.dram3_io_channel_disabled_buf2 (dram3_io_channel_disabled_buf2),
.dram3_io_cke (dram3_io_cke),
.dram3_io_cke_buf2 (dram3_io_cke_buf2),
.dram3_io_clk_enable (dram3_io_clk_enable),
.dram3_io_clk_enable_buf2 (dram3_io_clk_enable_buf2),
.dram3_io_cs_l (dram3_io_cs_l[3:0]),
.dram3_io_data_out (dram3_io_data_out[287:0]),
.dram3_io_drive_data (dram3_io_drive_data),
.dram3_io_drive_data_buf2 (dram3_io_drive_data_buf2),
.dram3_io_drive_enable (dram3_io_drive_enable),
.dram3_io_drive_enable_buf2 (dram3_io_drive_enable_buf2),
.dram3_io_pad_clk_inv (dram3_io_pad_clk_inv),
.dram3_io_pad_clk_inv_buf2 (dram3_io_pad_clk_inv_buf2),
.dram3_io_pad_enable (dram3_io_pad_enable),
.dram3_io_pad_enable_buf2 (dram3_io_pad_enable_buf2),
.dram3_io_ptr_clk_inv (dram3_io_ptr_clk_inv[4:0]),
.dram3_io_ras_l (dram3_io_ras_l),
.dram3_io_ras_l_buf2 (dram3_io_ras_l_buf2),
.dram3_io_write_en_l (dram3_io_write_en_l),
.dram3_io_write_en_l_buf2 (dram3_io_write_en_l_buf2),
.dram_gclk_c0_r (dram_gclk_c0_r[7:0]),
.dram_gclk_c2_r (dram_gclk_c2_r[7:0]),
.dram_gclk_c3_r (dram_gclk_c3_r[7:0]),
.io_do_bist (io_do_bist),
.io_dram0_data_in (io_dram0_data_in[255:0]),
.io_dram0_data_valid (io_dram0_data_valid),
.io_dram0_data_valid_buf0 (io_dram0_data_valid_buf0),
.io_dram0_ecc_in (io_dram0_ecc_in[31:0]),
.io_dram1_data_in (io_dram1_data_in[255:0]),
.io_dram1_data_valid (io_dram1_data_valid),
.io_dram1_data_valid_buf0 (io_dram1_data_valid_buf0),
.io_dram1_ecc_in (io_dram1_ecc_in[31:0]),
.io_dram2_data_in (io_dram2_data_in[255:0]),
.io_dram2_data_valid (io_dram2_data_valid),
.io_dram2_data_valid_buf0 (io_dram2_data_valid_buf0),
.io_dram2_ecc_in (io_dram2_ecc_in[31:0]),
.io_dram3_data_in (io_dram3_data_in[255:0]),
.io_dram3_data_valid (io_dram3_data_valid),
.io_dram3_data_valid_buf0 (io_dram3_data_valid_buf0),
.io_dram3_ecc_in (io_dram3_ecc_in[31:0]),
.iob_cpx_data_ca (iob_cpx_data_ca[`CPX_WIDTH-1:0]),
.iob_cpx_req_cq (iob_cpx_req_cq[`IOB_CPU_WIDTH-1:0]),
.iob_io_dbg_ck_n (iob_io_dbg_ck_n[2:0]),
.iob_io_dbg_ck_p (iob_io_dbg_ck_p[2:0]),
.iob_io_dbg_data (iob_io_dbg_data[39:0]),
.iob_io_dbg_en (iob_io_dbg_en),
.iob_jbi_dbg_hi_data (iob_jbi_dbg_hi_data[47:0]),
.iob_jbi_dbg_hi_vld (iob_jbi_dbg_hi_vld),
.iob_jbi_dbg_lo_data (iob_jbi_dbg_lo_data[47:0]),
.iob_jbi_dbg_lo_vld (iob_jbi_dbg_lo_vld),
.iob_jbi_mondo_ack (iob_jbi_mondo_ack),
.iob_jbi_mondo_nack (iob_jbi_mondo_nack),
.iob_jbi_pio_data (iob_jbi_pio_data[`IOB_JBI_WIDTH-1:0]),
.iob_jbi_pio_stall (iob_jbi_pio_stall),
.iob_jbi_pio_vld (iob_jbi_pio_vld),
.iob_jbi_spi_data (iob_jbi_spi_data[`IOB_SPI_WIDTH-1:0]),
.iob_jbi_spi_stall (iob_jbi_spi_stall),
.iob_jbi_spi_vld (iob_jbi_spi_vld),
.iob_pcx_stall_pq (iob_pcx_stall_pq),
.jbi_iob_mondo_data (jbi_iob_mondo_data[`JBI_IOB_MONDO_BUS_WIDTH-1:0]),
.jbi_iob_mondo_vld (jbi_iob_mondo_vld),
.jbi_iob_pio_data (jbi_iob_pio_data[`JBI_IOB_WIDTH-1:0]),
.jbi_iob_pio_stall (jbi_iob_pio_stall),
.jbi_iob_pio_vld (jbi_iob_pio_vld),
.jbi_iob_spi_data (jbi_iob_spi_data[`SPI_IOB_WIDTH-1:0]),
.jbi_iob_spi_stall (jbi_iob_spi_stall),
.jbi_iob_spi_vld (jbi_iob_spi_vld),
.par_scan_head (par_scan_head[30:0]),
.par_scan_tail (par_scan_tail[30:0]),
.pcx_iob_data_px2 (pcx_iob_data_px2[`PCX_WIDTH-1:0]),
.pcx_iob_data_rdy_px2 (pcx_iob_data_rdy_px2),
.pcx_sctag0_atm_px1 (pcx_sctag0_atm_px1),
.pcx_sctag0_data_px2 (pcx_sctag0_data_px2[`PCX_WIDTH-1:0]),
.pcx_sctag0_data_rdy_px1 (pcx_sctag0_data_rdy_px1),
.pcx_sctag1_atm_px1 (pcx_sctag1_atm_px1),
.pcx_sctag1_data_px2 (pcx_sctag1_data_px2[`PCX_WIDTH-1:0]),
.pcx_sctag1_data_rdy_px1 (pcx_sctag1_data_rdy_px1),
.pcx_sctag2_atm_px1 (pcx_sctag2_atm_px1),
.pcx_sctag2_data_px2 (pcx_sctag2_data_px2[`PCX_WIDTH-1:0]),
.pcx_sctag2_data_rdy_px1 (pcx_sctag2_data_rdy_px1),
.pcx_sctag3_atm_px1 (pcx_sctag3_atm_px1),
.pcx_sctag3_data_px2 (pcx_sctag3_data_px2[`PCX_WIDTH-1:0]),
.pcx_sctag3_data_rdy_px1 (pcx_sctag3_data_rdy_px1),
.pjbusl_rptrs_so (pjbusl_rptrs_so),
.pjbusr_rptrs_so (pjbusr_rptrs_so),
.rptrs_pdbg_so (rptrs_pdbg_so),
.rptrs_pmisc_so (rptrs_pmisc_so),
.rptrs_rsc12_so (rptrs_rsc12_so),
.rsc02_rptrs_so (rsc02_rptrs_so),
.sctag0_cpx_atom_cq (sctag0_cpx_atom_cq),
.sctag0_cpx_data_ca (sctag0_cpx_data_ca[`CPX_WIDTH-1:0]),
.sctag0_cpx_req_cq (sctag0_cpx_req_cq[7:0]),
.sctag0_ctu_mbistdone (sctag0_ctu_mbistdone),
.sctag0_ctu_mbistdone_buf2 (sctag0_ctu_mbistdone_buf2),
.sctag0_ctu_mbistdone_buf2 (sctag0_ctu_mbistdone_buf2),
.sctag0_ctu_mbisterr (sctag0_ctu_mbisterr),
.sctag0_ctu_mbisterr_buf2 (sctag0_ctu_mbisterr_buf2),
.sctag0_ctu_mbisterr_buf2 (sctag0_ctu_mbisterr_buf2),
.sctag0_ctu_tr (sctag0_ctu_tr),
.sctag0_ctu_tr_buf2 (sctag0_ctu_tr_buf2),
.sctag0_ctu_tr_buf2 (sctag0_ctu_tr_buf2),
.sctag0_pcx_stall_pq (sctag0_pcx_stall_pq),
.sctag1_cpx_atom_cq (sctag1_cpx_atom_cq),
.sctag1_cpx_data_ca (sctag1_cpx_data_ca[`CPX_WIDTH-1:0]),
.sctag1_cpx_req_cq (sctag1_cpx_req_cq[7:0]),
.sctag1_ctu_mbistdone (sctag1_ctu_mbistdone),
.sctag1_ctu_mbistdone_buf2 (sctag1_ctu_mbistdone_buf2),
.sctag1_ctu_mbistdone_buf2 (sctag1_ctu_mbistdone_buf2),
.sctag1_ctu_mbisterr (sctag1_ctu_mbisterr),
.sctag1_ctu_mbisterr_buf2 (sctag1_ctu_mbisterr_buf2),
.sctag1_ctu_mbisterr_buf2 (sctag1_ctu_mbisterr_buf2),
.sctag1_ctu_tr (sctag1_ctu_tr),
.sctag1_ctu_tr_buf2 (sctag1_ctu_tr_buf2),
.sctag1_ctu_tr_buf2 (sctag1_ctu_tr_buf2),
.sctag1_pcx_stall_pq (sctag1_pcx_stall_pq),
.sctag2_cpx_atom_cq (sctag2_cpx_atom_cq),
.sctag2_cpx_data_ca (sctag2_cpx_data_ca[`CPX_WIDTH-1:0]),
.sctag2_cpx_req_cq (sctag2_cpx_req_cq[7:0]),
.sctag2_ctu_mbistdone (sctag2_ctu_mbistdone),
.sctag2_ctu_mbistdone_buf2 (sctag2_ctu_mbistdone_buf2),
.sctag2_ctu_mbistdone_buf2 (sctag2_ctu_mbistdone_buf2),
.sctag2_ctu_mbisterr (sctag2_ctu_mbisterr),
.sctag2_ctu_mbisterr_buf2 (sctag2_ctu_mbisterr_buf2),
.sctag2_ctu_mbisterr_buf2 (sctag2_ctu_mbisterr_buf2),
.sctag2_ctu_tr (sctag2_ctu_tr),
.sctag2_ctu_tr_buf2 (sctag2_ctu_tr_buf2),
.sctag2_ctu_tr_buf2 (sctag2_ctu_tr_buf2),
.sctag2_pcx_stall_pq (sctag2_pcx_stall_pq),
.sctag3_cpx_atom_cq (sctag3_cpx_atom_cq),
.sctag3_cpx_data_ca (sctag3_cpx_data_ca[`CPX_WIDTH-1:0]),
.sctag3_cpx_req_cq (sctag3_cpx_req_cq[7:0]),
.sctag3_ctu_mbistdone (sctag3_ctu_mbistdone),
.sctag3_ctu_mbistdone_buf2 (sctag3_ctu_mbistdone_buf2),
.sctag3_ctu_mbistdone_buf2 (sctag3_ctu_mbistdone_buf2),
.sctag3_ctu_mbisterr (sctag3_ctu_mbisterr),
.sctag3_ctu_mbisterr_buf2 (sctag3_ctu_mbisterr_buf2),
.sctag3_ctu_mbisterr_buf2 (sctag3_ctu_mbisterr_buf2),
.sctag3_ctu_tr (sctag3_ctu_tr),
.sctag3_ctu_tr_buf2 (sctag3_ctu_tr_buf2),
.sctag3_ctu_tr_buf2 (sctag3_ctu_tr_buf2),
.sctag3_pcx_stall_pq (sctag3_pcx_stall_pq),
.ser_scan_out (ser_scan_out[30:0]),
.spc0_ctu_mbistdone (spc0_ctu_mbistdone),
.spc0_ctu_mbistdone_buf2 (spc0_ctu_mbistdone_buf2),
.spc0_ctu_mbistdone_buf2 (spc0_ctu_mbistdone_buf2),
.spc0_ctu_mbisterr (spc0_ctu_mbisterr),
.spc0_ctu_mbisterr_buf2 (spc0_ctu_mbisterr_buf2),
.spc0_ctu_mbisterr_buf2 (spc0_ctu_mbisterr_buf2),
.spc1_ctu_mbistdone (spc1_ctu_mbistdone),
.spc1_ctu_mbistdone_buf2 (spc1_ctu_mbistdone_buf2),
.spc1_ctu_mbistdone_buf2 (spc1_ctu_mbistdone_buf2),
.spc1_ctu_mbisterr (spc1_ctu_mbisterr),
.spc1_ctu_mbisterr_buf2 (spc1_ctu_mbisterr_buf2),
.spc1_ctu_mbisterr_buf2 (spc1_ctu_mbisterr_buf2),
.spc2_ctu_mbistdone (spc2_ctu_mbistdone),
.spc2_ctu_mbistdone_buf2 (spc2_ctu_mbistdone_buf2),
.spc2_ctu_mbistdone_buf2 (spc2_ctu_mbistdone_buf2),
.spc2_ctu_mbisterr (spc2_ctu_mbisterr),
.spc2_ctu_mbisterr_buf2 (spc2_ctu_mbisterr_buf2),
.spc2_ctu_mbisterr_buf2 (spc2_ctu_mbisterr_buf2),
.spc3_ctu_mbistdone (spc3_ctu_mbistdone),
.spc3_ctu_mbistdone_buf2 (spc3_ctu_mbistdone_buf2),
.spc3_ctu_mbistdone_buf2 (spc3_ctu_mbistdone_buf2),
.spc3_ctu_mbisterr (spc3_ctu_mbisterr),
.spc3_ctu_mbisterr_buf2 (spc3_ctu_mbisterr_buf2),
.spc3_ctu_mbisterr_buf2 (spc3_ctu_mbisterr_buf2),
.spc4_ctu_mbistdone (spc4_ctu_mbistdone),
.spc4_ctu_mbistdone_buf2 (spc4_ctu_mbistdone_buf2),
.spc4_ctu_mbistdone_buf2 (spc4_ctu_mbistdone_buf2),
.spc4_ctu_mbisterr (spc4_ctu_mbisterr),
.spc4_ctu_mbisterr_buf2 (spc4_ctu_mbisterr_buf2),
.spc4_ctu_mbisterr_buf2 (spc4_ctu_mbisterr_buf2),
.spc5_ctu_mbistdone (spc5_ctu_mbistdone),
.spc5_ctu_mbistdone_buf2 (spc5_ctu_mbistdone_buf2),
.spc5_ctu_mbistdone_buf2 (spc5_ctu_mbistdone_buf2),
.spc5_ctu_mbisterr (spc5_ctu_mbisterr),
.spc5_ctu_mbisterr_buf2 (spc5_ctu_mbisterr_buf2),
.spc5_ctu_mbisterr_buf2 (spc5_ctu_mbisterr_buf2),
.spc6_ctu_mbistdone (spc6_ctu_mbistdone),
.spc6_ctu_mbistdone_buf2 (spc6_ctu_mbistdone_buf2),
.spc6_ctu_mbistdone_buf2 (spc6_ctu_mbistdone_buf2),
.spc6_ctu_mbisterr (spc6_ctu_mbisterr),
.spc6_ctu_mbisterr_buf2 (spc6_ctu_mbisterr_buf2),
.spc6_ctu_mbisterr_buf2 (spc6_ctu_mbisterr_buf2),
.spc7_ctu_mbistdone (spc7_ctu_mbistdone),
.spc7_ctu_mbistdone_buf2 (spc7_ctu_mbistdone_buf2),
.spc7_ctu_mbistdone_buf2 (spc7_ctu_mbistdone_buf2),
.spc7_ctu_mbisterr (spc7_ctu_mbisterr),
.spc7_ctu_mbisterr_buf2 (spc7_ctu_mbisterr_buf2),
.spc7_ctu_mbisterr_buf2 (spc7_ctu_mbisterr_buf2));
`endif
//
/* bw_temp_diode AUTO_TEMPLATE (
.b (DIODE_TOP[0]),
.c (DIODE_TOP[1]),
.e (DIODE_TOP[2]),
); */
//
bw_temp_diode pad_diode0
(/*AUTOINST*/
// Inouts
.b (DIODE_TOP[0]), // Templated
.c (DIODE_TOP[1]), // Templated
.e (DIODE_TOP[2])); // Templated
//
/* bw_temp_diode AUTO_TEMPLATE (
.b (DIODE_BOT[0]),
.c (DIODE_BOT[1]),
.e (DIODE_BOT[2]),
); */
//
bw_temp_diode pad_diode1
(/*AUTOINST*/
// Inouts
.b (DIODE_BOT[0]), // Templated
.c (DIODE_BOT[1]), // Templated
.e (DIODE_BOT[2])); // Templated
//
/* ctu AUTO_TEMPLATE (
.io_vdda_pll (VDDA),
.io_vdda_rng (VDDA),
.io_vdda_tsr (VDDA),
.io_j_clk (J_CLK[]),
.ctu_io_tsr_testio (TSR_TESTIO[]),
.cmp_gclk_out (cmp_gclk),
.dram_gclk_out (dram_gclk),
.jbus_gclk_out (jbus_gclk),
.cmp_gclk (cmp_gclk_c1_r[4]),
.cmp_gclk_cts (cmp_gclk_c1_r[4]),
.dram_gclk_cts (dram_gclk_c1_r[4]),
.jbus_gclk (jbus_gclk_c1_r[4]),
.jbus_gclk_cts (jbus_gclk_c1_r[4]),
.dram_grst_out_l (dram_grst_l),
.dram_gdbginit_out_l (dram_gdbginit_l),
.jbus_grst_out_l (jbus_grst_l),
.jbus_gdbginit_out_l (jbus_gdbginit_l),
.cmp_grst_l (rpt_cmp_grst_l_c3),
.pads_ctu_bsi (ddr0_ctu_bso),
.pads_ctu_si (rbot2_ctu_so),
.ctu_fpu_so (ctu_rtop2_so),
.ctu_pads_bso (ctu_ddr1_bso),
.ctu_pads_so (),
.spc\([01234567]\)_ctu_mbistdone (spc\1_ctu_mbistdone_buf2),
.spc\([01234567]\)_ctu_mbisterr (spc\1_ctu_mbisterr_buf2),
.sctag\([0123]\)_ctu_mbistdone (sctag\1_ctu_mbistdone_buf2),
.sctag\([0123]\)_ctu_mbisterr (sctag\1_ctu_mbisterr_buf2),
.sctag\([0123]\)_ctu_tr (sctag\1_ctu_tr_buf2),
.dll\([0123]\)_ctu_ctrl (ctu_dll\1_ctu_ctrl[]),
.sctag2_ctu_serial_scan_in (ser_scan_out[30]),
); */
//
`ifdef RTL_CTU
ctu ctu
(/*AUTOINST*/
// Outputs
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.global_shift_enable (global_shift_enable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_short_chain (ctu_tst_short_chain),
.ctu_efc_read_start (ctu_efc_read_start),
.ctu_jbi_ssiclk (ctu_jbi_ssiclk),
.ctu_dram_rx_sync_out (ctu_dram_rx_sync_out),
.ctu_dram_tx_sync_out (ctu_dram_tx_sync_out),
.ctu_jbus_rx_sync_out (ctu_jbus_rx_sync_out),
.ctu_jbus_tx_sync_out (ctu_jbus_tx_sync_out),
.cmp_grst_out_l (cmp_grst_out_l),
.afo_rng_clk (afo_rng_clk),
.afo_rng_data (afo_rng_data),
.afo_rt_ack (afo_rt_ack),
.afo_rt_data_out (afo_rt_data_out[31:0]),
.afo_tsr_dout (afo_tsr_dout[7:0]),
.clsp_iob_data (clsp_iob_data[`CLK_IOB_WIDTH-1:0]),
.clsp_iob_stall (clsp_iob_stall),
.clsp_iob_vld (clsp_iob_vld),
.cmp_adbginit_l (cmp_adbginit_l),
.cmp_arst_l (cmp_arst_l),
.cmp_gclk_out (cmp_gclk), // Templated
.cmp_gdbginit_out_l (cmp_gdbginit_out_l),
.ctu_ccx_cmp_cken (ctu_ccx_cmp_cken),
.ctu_dbg_jbus_cken (ctu_dbg_jbus_cken),
.ctu_ddr0_clock_dr (ctu_ddr0_clock_dr),
.ctu_ddr0_dll_delayctr (ctu_ddr0_dll_delayctr[2:0]),
.ctu_ddr0_dram_cken (ctu_ddr0_dram_cken),
.ctu_ddr0_hiz_l (ctu_ddr0_hiz_l),
.ctu_ddr0_iodll_rst_l (ctu_ddr0_iodll_rst_l),
.ctu_ddr0_mode_ctl (ctu_ddr0_mode_ctl),
.ctu_ddr0_shift_dr (ctu_ddr0_shift_dr),
.ctu_ddr0_update_dr (ctu_ddr0_update_dr),
.ctu_ddr1_clock_dr (ctu_ddr1_clock_dr),
.ctu_ddr1_dll_delayctr (ctu_ddr1_dll_delayctr[2:0]),
.ctu_ddr1_dram_cken (ctu_ddr1_dram_cken),
.ctu_ddr1_hiz_l (ctu_ddr1_hiz_l),
.ctu_ddr1_iodll_rst_l (ctu_ddr1_iodll_rst_l),
.ctu_ddr1_mode_ctl (ctu_ddr1_mode_ctl),
.ctu_ddr1_shift_dr (ctu_ddr1_shift_dr),
.ctu_ddr1_update_dr (ctu_ddr1_update_dr),
.ctu_ddr2_clock_dr (ctu_ddr2_clock_dr),
.ctu_ddr2_dll_delayctr (ctu_ddr2_dll_delayctr[2:0]),
.ctu_ddr2_dram_cken (ctu_ddr2_dram_cken),
.ctu_ddr2_hiz_l (ctu_ddr2_hiz_l),
.ctu_ddr2_iodll_rst_l (ctu_ddr2_iodll_rst_l),
.ctu_ddr2_mode_ctl (ctu_ddr2_mode_ctl),
.ctu_ddr2_shift_dr (ctu_ddr2_shift_dr),
.ctu_ddr2_update_dr (ctu_ddr2_update_dr),
.ctu_ddr3_clock_dr (ctu_ddr3_clock_dr),
.ctu_ddr3_dll_delayctr (ctu_ddr3_dll_delayctr[2:0]),
.ctu_ddr3_dram_cken (ctu_ddr3_dram_cken),
.ctu_ddr3_hiz_l (ctu_ddr3_hiz_l),
.ctu_ddr3_iodll_rst_l (ctu_ddr3_iodll_rst_l),
.ctu_ddr3_mode_ctl (ctu_ddr3_mode_ctl),
.ctu_ddr3_shift_dr (ctu_ddr3_shift_dr),
.ctu_ddr3_update_dr (ctu_ddr3_update_dr),
.ctu_ddr_testmode_l (ctu_ddr_testmode_l),
.ctu_debug_clock_dr (ctu_debug_clock_dr),
.ctu_debug_hiz_l (ctu_debug_hiz_l),
.ctu_debug_mode_ctl (ctu_debug_mode_ctl),
.ctu_debug_shift_dr (ctu_debug_shift_dr),
.ctu_debug_update_dr (ctu_debug_update_dr),
.ctu_dll0_byp_l (ctu_dll0_byp_l),
.ctu_dll0_byp_val (ctu_dll0_byp_val[4:0]),
.ctu_dll1_byp_l (ctu_dll1_byp_l),
.ctu_dll1_byp_val (ctu_dll1_byp_val[4:0]),
.ctu_dll2_byp_l (ctu_dll2_byp_l),
.ctu_dll2_byp_val (ctu_dll2_byp_val[4:0]),
.ctu_dll3_byp_l (ctu_dll3_byp_l),
.ctu_dll3_byp_val (ctu_dll3_byp_val[4:0]),
.ctu_dram02_cmp_cken (ctu_dram02_cmp_cken),
.ctu_dram02_dram_cken (ctu_dram02_dram_cken),
.ctu_dram02_jbus_cken (ctu_dram02_jbus_cken),
.ctu_dram13_cmp_cken (ctu_dram13_cmp_cken),
.ctu_dram13_dram_cken (ctu_dram13_dram_cken),
.ctu_dram13_jbus_cken (ctu_dram13_jbus_cken),
.ctu_dram_selfrsh (ctu_dram_selfrsh),
.ctu_efc_capturedr (ctu_efc_capturedr),
.ctu_efc_coladdr (ctu_efc_coladdr[4:0]),
.ctu_efc_data_in (ctu_efc_data_in),
.ctu_efc_dest_sample (ctu_efc_dest_sample),
.ctu_efc_fuse_bypass (ctu_efc_fuse_bypass),
.ctu_efc_jbus_cken (ctu_efc_jbus_cken),
.ctu_efc_read_en (ctu_efc_read_en),
.ctu_efc_read_mode (ctu_efc_read_mode[2:0]),
.ctu_efc_rowaddr (ctu_efc_rowaddr[6:0]),
.ctu_efc_shiftdr (ctu_efc_shiftdr),
.ctu_efc_tck (ctu_efc_tck),
.ctu_efc_updatedr (ctu_efc_updatedr),
.ctu_fpu_cmp_cken (ctu_fpu_cmp_cken),
.ctu_fpu_so (ctu_rtop2_so), // Templated
.ctu_global_snap (ctu_global_snap),
.ctu_io_clkobs (ctu_io_clkobs[1:0]),
.ctu_io_j_err (ctu_io_j_err),
.ctu_io_tdo (ctu_io_tdo),
.ctu_io_tdo_en (ctu_io_tdo_en),
.ctu_io_tsr_testio (TSR_TESTIO[1:0]), // Templated
.ctu_iob_cmp_cken (ctu_iob_cmp_cken),
.ctu_iob_jbus_cken (ctu_iob_jbus_cken),
.ctu_iob_resetstat (ctu_iob_resetstat[2:0]),
.ctu_iob_resetstat_wr (ctu_iob_resetstat_wr),
.ctu_iob_wake_thr (ctu_iob_wake_thr),
.ctu_jbi_cmp_cken (ctu_jbi_cmp_cken),
.ctu_jbi_jbus_cken (ctu_jbi_jbus_cken),
.ctu_jbusl_clock_dr (ctu_jbusl_clock_dr),
.ctu_jbusl_hiz_l (ctu_jbusl_hiz_l),
.ctu_jbusl_jbus_cken (ctu_jbusl_jbus_cken),
.ctu_jbusl_mode_ctl (ctu_jbusl_mode_ctl),
.ctu_jbusl_shift_dr (ctu_jbusl_shift_dr),
.ctu_jbusl_update_dr (ctu_jbusl_update_dr),
.ctu_jbusr_clock_dr (ctu_jbusr_clock_dr),
.ctu_jbusr_hiz_l (ctu_jbusr_hiz_l),
.ctu_jbusr_jbus_cken (ctu_jbusr_jbus_cken),
.ctu_jbusr_mode_ctl (ctu_jbusr_mode_ctl),
.ctu_jbusr_shift_dr (ctu_jbusr_shift_dr),
.ctu_jbusr_update_dr (ctu_jbusr_update_dr),
.ctu_misc_clock_dr (ctu_misc_clock_dr),
.ctu_misc_hiz_l (ctu_misc_hiz_l),
.ctu_misc_jbus_cken (ctu_misc_jbus_cken),
.ctu_misc_mode_ctl (ctu_misc_mode_ctl),
.ctu_misc_shift_dr (ctu_misc_shift_dr),
.ctu_misc_update_dr (ctu_misc_update_dr),
.ctu_pads_bso (ctu_ddr1_bso), // Templated
.ctu_pads_so (), // Templated
.ctu_pads_sscan_update (ctu_pads_sscan_update),
.ctu_scdata0_cmp_cken (ctu_scdata0_cmp_cken),
.ctu_scdata1_cmp_cken (ctu_scdata1_cmp_cken),
.ctu_scdata2_cmp_cken (ctu_scdata2_cmp_cken),
.ctu_scdata3_cmp_cken (ctu_scdata3_cmp_cken),
.ctu_sctag0_cmp_cken (ctu_sctag0_cmp_cken),
.ctu_sctag0_mbisten (ctu_sctag0_mbisten),
.ctu_sctag1_cmp_cken (ctu_sctag1_cmp_cken),
.ctu_sctag1_mbisten (ctu_sctag1_mbisten),
.ctu_sctag2_cmp_cken (ctu_sctag2_cmp_cken),
.ctu_sctag2_mbisten (ctu_sctag2_mbisten),
.ctu_sctag3_cmp_cken (ctu_sctag3_cmp_cken),
.ctu_sctag3_mbisten (ctu_sctag3_mbisten),
.ctu_spc0_cmp_cken (ctu_spc0_cmp_cken),
.ctu_spc0_mbisten (ctu_spc0_mbisten),
.ctu_spc0_sscan_se (ctu_spc0_sscan_se),
.ctu_spc0_tck (ctu_spc0_tck),
.ctu_spc1_cmp_cken (ctu_spc1_cmp_cken),
.ctu_spc1_mbisten (ctu_spc1_mbisten),
.ctu_spc1_sscan_se (ctu_spc1_sscan_se),
.ctu_spc1_tck (ctu_spc1_tck),
.ctu_spc2_cmp_cken (ctu_spc2_cmp_cken),
.ctu_spc2_mbisten (ctu_spc2_mbisten),
.ctu_spc2_sscan_se (ctu_spc2_sscan_se),
.ctu_spc2_tck (ctu_spc2_tck),
.ctu_spc3_cmp_cken (ctu_spc3_cmp_cken),
.ctu_spc3_mbisten (ctu_spc3_mbisten),
.ctu_spc3_sscan_se (ctu_spc3_sscan_se),
.ctu_spc3_tck (ctu_spc3_tck),
.ctu_spc4_cmp_cken (ctu_spc4_cmp_cken),
.ctu_spc4_mbisten (ctu_spc4_mbisten),
.ctu_spc4_sscan_se (ctu_spc4_sscan_se),
.ctu_spc4_tck (ctu_spc4_tck),
.ctu_spc5_cmp_cken (ctu_spc5_cmp_cken),
.ctu_spc5_mbisten (ctu_spc5_mbisten),
.ctu_spc5_sscan_se (ctu_spc5_sscan_se),
.ctu_spc5_tck (ctu_spc5_tck),
.ctu_spc6_cmp_cken (ctu_spc6_cmp_cken),
.ctu_spc6_mbisten (ctu_spc6_mbisten),
.ctu_spc6_sscan_se (ctu_spc6_sscan_se),
.ctu_spc6_tck (ctu_spc6_tck),
.ctu_spc7_cmp_cken (ctu_spc7_cmp_cken),
.ctu_spc7_mbisten (ctu_spc7_mbisten),
.ctu_spc7_sscan_se (ctu_spc7_sscan_se),
.ctu_spc7_tck (ctu_spc7_tck),
.ctu_spc_const_maskid (ctu_spc_const_maskid[7:0]),
.ctu_spc_sscan_tid (ctu_spc_sscan_tid[3:0]),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.dram_adbginit_l (dram_adbginit_l),
.dram_arst_l (dram_arst_l),
.dram_gclk_out (dram_gclk), // Templated
.dram_gdbginit_out_l (dram_gdbginit_l), // Templated
.dram_grst_out_l (dram_grst_l), // Templated
.global_scan_bypass_en (global_scan_bypass_en),
.jbus_adbginit_l (jbus_adbginit_l),
.jbus_arst_l (jbus_arst_l),
.jbus_gclk_dup_out (jbus_gclk_dup_out),
.jbus_gclk_out (jbus_gclk), // Templated
.jbus_gdbginit_out_l (jbus_gdbginit_l), // Templated
.jbus_grst_out_l (jbus_grst_l), // Templated
.pscan_select (pscan_select),
.tap_iob_data (tap_iob_data[7:0]),
.tap_iob_stall (tap_iob_stall),
.tap_iob_vld (tap_iob_vld),
// Inputs
.afi_pll_trst_l (afi_pll_trst_l),
.afi_tsr_mode (afi_tsr_mode),
.io_j_clk (J_CLK[1:0]), // Templated
.afi_bist_mode (afi_bist_mode),
.afi_bypass_mode (afi_bypass_mode),
.afi_pll_char_mode (afi_pll_char_mode),
.afi_pll_clamp_fltr (afi_pll_clamp_fltr),
.afi_pll_div2 (afi_pll_div2[5:0]),
.afi_rng_ctl (afi_rng_ctl[2:0]),
.afi_rt_addr_data (afi_rt_addr_data),
.afi_rt_data_in (afi_rt_data_in[31:0]),
.afi_rt_high_low (afi_rt_high_low),
.afi_rt_read_write (afi_rt_read_write),
.afi_rt_valid (afi_rt_valid),
.afi_tsr_div (afi_tsr_div[9:1]),
.afi_tsr_tsel (afi_tsr_tsel[7:0]),
.cmp_gclk (cmp_gclk_c1_r[4]), // Templated
.cmp_gclk_cts (cmp_gclk_c1_r[4]), // Templated
.ddr0_ctu_dll_lock (ddr0_ctu_dll_lock),
.ddr0_ctu_dll_overflow (ddr0_ctu_dll_overflow),
.ddr1_ctu_dll_lock (ddr1_ctu_dll_lock),
.ddr1_ctu_dll_overflow (ddr1_ctu_dll_overflow),
.ddr2_ctu_dll_lock (ddr2_ctu_dll_lock),
.ddr2_ctu_dll_overflow (ddr2_ctu_dll_overflow),
.ddr3_ctu_dll_lock (ddr3_ctu_dll_lock),
.ddr3_ctu_dll_overflow (ddr3_ctu_dll_overflow),
.dll0_ctu_ctrl (ctu_dll0_ctu_ctrl[4:0]), // Templated
.dll1_ctu_ctrl (ctu_dll1_ctu_ctrl[4:0]), // Templated
.dll2_ctu_ctrl (ctu_dll2_ctu_ctrl[4:0]), // Templated
.dll3_ctu_ctrl (ctu_dll3_ctu_ctrl[4:0]), // Templated
.dram02_ctu_tr (dram02_ctu_tr),
.dram13_ctu_tr (dram13_ctu_tr),
.dram_gclk_cts (dram_gclk_c1_r[4]), // Templated
.efc_ctu_data_out (efc_ctu_data_out),
.io_clk_stretch (io_clk_stretch),
.io_do_bist (io_do_bist),
.io_j_rst_l (io_j_rst_l),
.io_pll_char_in (io_pll_char_in),
.io_pwron_rst_l (io_pwron_rst_l),
.io_tck (io_tck),
.io_tck2 (io_tck2),
.io_tdi (io_tdi),
.io_test_mode (io_test_mode),
.io_tms (io_tms),
.io_trst_l (io_trst_l),
.io_vdda_pll (VDDA), // Templated
.io_vdda_rng (VDDA), // Templated
.io_vdda_tsr (VDDA), // Templated
.io_vreg_selbg_l (io_vreg_selbg_l),
.iob_clsp_data (iob_clsp_data[`IOB_CLK_WIDTH-1:0]),
.iob_clsp_stall (iob_clsp_stall),
.iob_clsp_vld (iob_clsp_vld),
.iob_ctu_coreavail (iob_ctu_coreavail[`IOB_CPU_WIDTH-1:0]),
.iob_ctu_l2_tr (iob_ctu_l2_tr),
.iob_ctu_tr (iob_ctu_tr),
.iob_tap_data (iob_tap_data[7:0]),
.iob_tap_stall (iob_tap_stall),
.iob_tap_vld (iob_tap_vld),
.jbi_ctu_tr (jbi_ctu_tr),
.jbus_gclk (jbus_gclk_c1_r[4]), // Templated
.jbus_gclk_cts (jbus_gclk_c1_r[4]), // Templated
.jbus_gclk_dup (jbus_gclk_dup),
.jbus_grst_l (jbus_grst_l),
.pads_ctu_bsi (ddr0_ctu_bso), // Templated
.pads_ctu_si (rbot2_ctu_so), // Templated
.sctag0_ctu_mbistdone (sctag0_ctu_mbistdone_buf2), // Templated
.sctag0_ctu_mbisterr (sctag0_ctu_mbisterr_buf2), // Templated
.sctag0_ctu_tr (sctag0_ctu_tr_buf2), // Templated
.sctag1_ctu_mbistdone (sctag1_ctu_mbistdone_buf2), // Templated
.sctag1_ctu_mbisterr (sctag1_ctu_mbisterr_buf2), // Templated
.sctag1_ctu_tr (sctag1_ctu_tr_buf2), // Templated
.sctag2_ctu_mbistdone (sctag2_ctu_mbistdone_buf2), // Templated
.sctag2_ctu_mbisterr (sctag2_ctu_mbisterr_buf2), // Templated
.sctag2_ctu_serial_scan_in (ser_scan_out[30]), // Templated
.sctag2_ctu_tr (sctag2_ctu_tr_buf2), // Templated
.sctag3_ctu_mbistdone (sctag3_ctu_mbistdone_buf2), // Templated
.sctag3_ctu_mbisterr (sctag3_ctu_mbisterr_buf2), // Templated
.sctag3_ctu_tr (sctag3_ctu_tr_buf2), // Templated
.spc0_ctu_mbistdone (spc0_ctu_mbistdone_buf2), // Templated
.spc0_ctu_mbisterr (spc0_ctu_mbisterr_buf2), // Templated
.spc0_ctu_sscan_out (spc0_ctu_sscan_out),
.spc1_ctu_mbistdone (spc1_ctu_mbistdone_buf2), // Templated
.spc1_ctu_mbisterr (spc1_ctu_mbisterr_buf2), // Templated
.spc1_ctu_sscan_out (spc1_ctu_sscan_out),
.spc2_ctu_mbistdone (spc2_ctu_mbistdone_buf2), // Templated
.spc2_ctu_mbisterr (spc2_ctu_mbisterr_buf2), // Templated
.spc2_ctu_sscan_out (spc2_ctu_sscan_out),
.spc3_ctu_mbistdone (spc3_ctu_mbistdone_buf2), // Templated
.spc3_ctu_mbisterr (spc3_ctu_mbisterr_buf2), // Templated
.spc3_ctu_sscan_out (spc3_ctu_sscan_out),
.spc4_ctu_mbistdone (spc4_ctu_mbistdone_buf2), // Templated
.spc4_ctu_mbisterr (spc4_ctu_mbisterr_buf2), // Templated
.spc4_ctu_sscan_out (spc4_ctu_sscan_out),
.spc5_ctu_mbistdone (spc5_ctu_mbistdone_buf2), // Templated
.spc5_ctu_mbisterr (spc5_ctu_mbisterr_buf2), // Templated
.spc5_ctu_sscan_out (spc5_ctu_sscan_out),
.spc6_ctu_mbistdone (spc6_ctu_mbistdone_buf2), // Templated
.spc6_ctu_mbisterr (spc6_ctu_mbisterr_buf2), // Templated
.spc6_ctu_sscan_out (spc6_ctu_sscan_out),
.spc7_ctu_mbistdone (spc7_ctu_mbistdone_buf2), // Templated
.spc7_ctu_mbisterr (spc7_ctu_mbisterr_buf2), // Templated
.spc7_ctu_sscan_out (spc7_ctu_sscan_out));
`endif
//
/* ctu_top_rptr AUTO_TEMPLATE (
.rclk (ccx_rclk),
.se (global_shift_enable),
.si (rdram0_rtop_so),
.so (rtop_rdram2_so),
.dbgbus_b0 ({1'b0, 40'b0}),
.dbgbus_b1 ({1'b0, 20'b0, ctu_sctag0_mbisten_buf, ctu_sctag2_mbisten_buf, ctu_spc0_mbisten_buf, ctu_spc2_mbisten_buf, ctu_spc4_mbisten_buf, ctu_spc6_mbisten_buf, sctag0_ctu_mbistdone, sctag0_ctu_mbisterr, sctag2_ctu_mbistdone, sctag2_ctu_mbisterr, spc0_ctu_mbistdone, spc0_ctu_mbisterr, spc2_ctu_mbistdone, spc2_ctu_mbisterr, spc4_ctu_mbistdone, spc4_ctu_mbisterr, spc6_ctu_mbistdone, spc6_ctu_mbisterr, sctag0_ctu_tr, sctag2_ctu_tr}),
.enable_01 (),
.l2_dbgbus_out ({ctu_top_rptr_unused[19:0], ctu_sctag0_mbisten_buf2, ctu_sctag2_mbisten_buf2, ctu_spc0_mbisten_buf2, ctu_spc2_mbisten_buf2, ctu_spc4_mbisten_buf2, ctu_spc6_mbisten_buf2, sctag0_ctu_mbistdone_buf, sctag0_ctu_mbisterr_buf, sctag2_ctu_mbistdone_buf, sctag2_ctu_mbisterr_buf, spc0_ctu_mbistdone_buf, spc0_ctu_mbisterr_buf, spc2_ctu_mbistdone_buf, spc2_ctu_mbisterr_buf, spc4_ctu_mbistdone_buf, spc4_ctu_mbisterr_buf, spc6_ctu_mbistdone_buf, spc6_ctu_mbisterr_buf, sctag0_ctu_tr_buf, sctag2_ctu_tr_buf}),
); */
//
ctu_top_rptr ctu_top_rptr
(/*AUTOINST*/
// Outputs
.l2_dbgbus_out ({ctu_top_rptr_unused[19:0], ctu_sctag0_mbisten_buf2, ctu_sctag2_mbisten_buf2, ctu_spc0_mbisten_buf2, ctu_spc2_mbisten_buf2, ctu_spc4_mbisten_buf2, ctu_spc6_mbisten_buf2, sctag0_ctu_mbistdone_buf, sctag0_ctu_mbisterr_buf, sctag2_ctu_mbistdone_buf, sctag2_ctu_mbisterr_buf, spc0_ctu_mbistdone_buf, spc0_ctu_mbisterr_buf, spc2_ctu_mbistdone_buf, spc2_ctu_mbisterr_buf, spc4_ctu_mbistdone_buf, spc4_ctu_mbisterr_buf, spc6_ctu_mbistdone_buf, spc6_ctu_mbisterr_buf, sctag0_ctu_tr_buf, sctag2_ctu_tr_buf}), // Templated
.enable_01 (), // Templated
.so (rtop_rdram2_so), // Templated
// Inputs
.dbgbus_b0 ({1'b0, 40'b0}), // Templated
.dbgbus_b1 ({1'b0, 20'b0, ctu_sctag0_mbisten_buf, ctu_sctag2_mbisten_buf, ctu_spc0_mbisten_buf, ctu_spc2_mbisten_buf, ctu_spc4_mbisten_buf, ctu_spc6_mbisten_buf, sctag0_ctu_mbistdone, sctag0_ctu_mbisterr, sctag2_ctu_mbistdone, sctag2_ctu_mbisterr, spc0_ctu_mbistdone, spc0_ctu_mbisterr, spc2_ctu_mbistdone, spc2_ctu_mbisterr, spc4_ctu_mbistdone, spc4_ctu_mbisterr, spc6_ctu_mbistdone, spc6_ctu_mbisterr, sctag0_ctu_tr, sctag2_ctu_tr}), // Templated
.rclk (ccx_rclk), // Templated
.si (rdram0_rtop_so), // Templated
.se (global_shift_enable)); // Templated
//
/* ctu_top_rptr2 AUTO_TEMPLATE (
.rclk (ccx_rclk),
.se (global_shift_enable),
.si (ctu_rtop2_so),
.so (rtop2_rdram0_so),
.dbgbus_b0 ({1'b0, 40'b0}),
.dbgbus_b1 ({1'b0, 20'b0, ctu_sctag0_mbisten, ctu_sctag2_mbisten, ctu_spc0_mbisten, ctu_spc2_mbisten, ctu_spc4_mbisten, ctu_spc6_mbisten, sctag0_ctu_mbistdone_buf, sctag0_ctu_mbisterr_buf, sctag2_ctu_mbistdone_buf, sctag2_ctu_mbisterr_buf, spc0_ctu_mbistdone_buf, spc0_ctu_mbisterr_buf, spc2_ctu_mbistdone_buf, spc2_ctu_mbisterr_buf, spc4_ctu_mbistdone_buf, spc4_ctu_mbisterr_buf, spc6_ctu_mbistdone_buf, spc6_ctu_mbisterr_buf, sctag0_ctu_tr_buf, sctag2_ctu_tr_buf}),
.enable_01 (),
.l2_dbgbus_out ({ctu_top_rptr2_unused[19:0], ctu_sctag0_mbisten_buf, ctu_sctag2_mbisten_buf, ctu_spc0_mbisten_buf, ctu_spc2_mbisten_buf, ctu_spc4_mbisten_buf, ctu_spc6_mbisten_buf, sctag0_ctu_mbistdone_buf2, sctag0_ctu_mbisterr_buf2, sctag2_ctu_mbistdone_buf2, sctag2_ctu_mbisterr_buf2, spc0_ctu_mbistdone_buf2, spc0_ctu_mbisterr_buf2, spc2_ctu_mbistdone_buf2, spc2_ctu_mbisterr_buf2, spc4_ctu_mbistdone_buf2, spc4_ctu_mbisterr_buf2, spc6_ctu_mbistdone_buf2, spc6_ctu_mbisterr_buf2, sctag0_ctu_tr_buf2, sctag2_ctu_tr_buf2}),
); */
//
ctu_top_rptr2 ctu_top_rptr2
(/*AUTOINST*/
// Outputs
.l2_dbgbus_out ({ctu_top_rptr2_unused[19:0], ctu_sctag0_mbisten_buf, ctu_sctag2_mbisten_buf, ctu_spc0_mbisten_buf, ctu_spc2_mbisten_buf, ctu_spc4_mbisten_buf, ctu_spc6_mbisten_buf, sctag0_ctu_mbistdone_buf2, sctag0_ctu_mbisterr_buf2, sctag2_ctu_mbistdone_buf2, sctag2_ctu_mbisterr_buf2, spc0_ctu_mbistdone_buf2, spc0_ctu_mbisterr_buf2, spc2_ctu_mbistdone_buf2, spc2_ctu_mbisterr_buf2, spc4_ctu_mbistdone_buf2, spc4_ctu_mbisterr_buf2, spc6_ctu_mbistdone_buf2, spc6_ctu_mbisterr_buf2, sctag0_ctu_tr_buf2, sctag2_ctu_tr_buf2}), // Templated
.enable_01 (), // Templated
.so (rtop2_rdram0_so), // Templated
// Inputs
.dbgbus_b0 ({1'b0, 40'b0}), // Templated
.dbgbus_b1 ({1'b0, 20'b0, ctu_sctag0_mbisten, ctu_sctag2_mbisten, ctu_spc0_mbisten, ctu_spc2_mbisten, ctu_spc4_mbisten, ctu_spc6_mbisten, sctag0_ctu_mbistdone_buf, sctag0_ctu_mbisterr_buf, sctag2_ctu_mbistdone_buf, sctag2_ctu_mbisterr_buf, spc0_ctu_mbistdone_buf, spc0_ctu_mbisterr_buf, spc2_ctu_mbistdone_buf, spc2_ctu_mbisterr_buf, spc4_ctu_mbistdone_buf, spc4_ctu_mbisterr_buf, spc6_ctu_mbistdone_buf, spc6_ctu_mbisterr_buf, sctag0_ctu_tr_buf, sctag2_ctu_tr_buf}), // Templated
.rclk (ccx_rclk), // Templated
.si (ctu_rtop2_so), // Templated
.se (global_shift_enable)); // Templated
//
/* ctu_bottom_rptr AUTO_TEMPLATE (
.rclk (ccx_rclk),
.se (global_shift_enable),
.si (rdram3_rbot_so),
.so (rbot_rdram1_so),
.dbgbus_b0 ({1'b0, 40'b0}),
.dbgbus_b1 ({1'b0, 20'b0, ctu_sctag1_mbisten_buf, ctu_sctag3_mbisten_buf, ctu_spc1_mbisten_buf, ctu_spc3_mbisten_buf, ctu_spc5_mbisten_buf, ctu_spc7_mbisten_buf, sctag1_ctu_mbistdone, sctag1_ctu_mbisterr, sctag3_ctu_mbistdone, sctag3_ctu_mbisterr, spc1_ctu_mbistdone, spc1_ctu_mbisterr, spc3_ctu_mbistdone, spc3_ctu_mbisterr, spc5_ctu_mbistdone, spc5_ctu_mbisterr, spc7_ctu_mbistdone, spc7_ctu_mbisterr, sctag1_ctu_tr, sctag3_ctu_tr}),
.enable_01 (),
.l2_dbgbus_out ({ctu_bottom_rptr_unused[19:0], ctu_sctag1_mbisten_buf2, ctu_sctag3_mbisten_buf2, ctu_spc1_mbisten_buf2, ctu_spc3_mbisten_buf2, ctu_spc5_mbisten_buf2, ctu_spc7_mbisten_buf2, sctag1_ctu_mbistdone_buf, sctag1_ctu_mbisterr_buf, sctag3_ctu_mbistdone_buf, sctag3_ctu_mbisterr_buf, spc1_ctu_mbistdone_buf, spc1_ctu_mbisterr_buf, spc3_ctu_mbistdone_buf, spc3_ctu_mbisterr_buf, spc5_ctu_mbistdone_buf, spc5_ctu_mbisterr_buf, spc7_ctu_mbistdone_buf, spc7_ctu_mbisterr_buf, sctag1_ctu_tr_buf, sctag3_ctu_tr_buf}),
); */
//
ctu_bottom_rptr ctu_bottom_rptr
(/*AUTOINST*/
// Outputs
.l2_dbgbus_out ({ctu_bottom_rptr_unused[19:0], ctu_sctag1_mbisten_buf2, ctu_sctag3_mbisten_buf2, ctu_spc1_mbisten_buf2, ctu_spc3_mbisten_buf2, ctu_spc5_mbisten_buf2, ctu_spc7_mbisten_buf2, sctag1_ctu_mbistdone_buf, sctag1_ctu_mbisterr_buf, sctag3_ctu_mbistdone_buf, sctag3_ctu_mbisterr_buf, spc1_ctu_mbistdone_buf, spc1_ctu_mbisterr_buf, spc3_ctu_mbistdone_buf, spc3_ctu_mbisterr_buf, spc5_ctu_mbistdone_buf, spc5_ctu_mbisterr_buf, spc7_ctu_mbistdone_buf, spc7_ctu_mbisterr_buf, sctag1_ctu_tr_buf, sctag3_ctu_tr_buf}), // Templated
.enable_01 (), // Templated
.so (rbot_rdram1_so), // Templated
// Inputs
.dbgbus_b0 ({1'b0, 40'b0}), // Templated
.dbgbus_b1 ({1'b0, 20'b0, ctu_sctag1_mbisten_buf, ctu_sctag3_mbisten_buf, ctu_spc1_mbisten_buf, ctu_spc3_mbisten_buf, ctu_spc5_mbisten_buf, ctu_spc7_mbisten_buf, sctag1_ctu_mbistdone, sctag1_ctu_mbisterr, sctag3_ctu_mbistdone, sctag3_ctu_mbisterr, spc1_ctu_mbistdone, spc1_ctu_mbisterr, spc3_ctu_mbistdone, spc3_ctu_mbisterr, spc5_ctu_mbistdone, spc5_ctu_mbisterr, spc7_ctu_mbistdone, spc7_ctu_mbisterr, sctag1_ctu_tr, sctag3_ctu_tr}), // Templated
.rclk (ccx_rclk), // Templated
.si (rdram3_rbot_so), // Templated
.se (global_shift_enable)); // Templated
//
/* ctu_bottom_rptr2 AUTO_TEMPLATE (
.rclk (ccx_rclk),
.se (global_shift_enable),
.si (rdram1_rbot2_so),
.so (rbot2_ctu_so),
.dbgbus_b0 ({1'b0, 40'b0}),
.dbgbus_b1 ({1'b0, 20'b0, ctu_sctag1_mbisten, ctu_sctag3_mbisten, ctu_spc1_mbisten, ctu_spc3_mbisten, ctu_spc5_mbisten, ctu_spc7_mbisten, sctag1_ctu_mbistdone_buf, sctag1_ctu_mbisterr_buf, sctag3_ctu_mbistdone_buf, sctag3_ctu_mbisterr_buf, spc1_ctu_mbistdone_buf, spc1_ctu_mbisterr_buf, spc3_ctu_mbistdone_buf, spc3_ctu_mbisterr_buf, spc5_ctu_mbistdone_buf, spc5_ctu_mbisterr_buf, spc7_ctu_mbistdone_buf, spc7_ctu_mbisterr_buf, sctag1_ctu_tr_buf, sctag3_ctu_tr_buf}),
.enable_01 (),
.l2_dbgbus_out ({ctu_bottom_rptr2_unused[19:0], ctu_sctag1_mbisten_buf, ctu_sctag3_mbisten_buf, ctu_spc1_mbisten_buf, ctu_spc3_mbisten_buf, ctu_spc5_mbisten_buf, ctu_spc7_mbisten_buf, sctag1_ctu_mbistdone_buf2, sctag1_ctu_mbisterr_buf2, sctag3_ctu_mbistdone_buf2, sctag3_ctu_mbisterr_buf2, spc1_ctu_mbistdone_buf2, spc1_ctu_mbisterr_buf2, spc3_ctu_mbistdone_buf2, spc3_ctu_mbisterr_buf2, spc5_ctu_mbistdone_buf2, spc5_ctu_mbisterr_buf2, spc7_ctu_mbistdone_buf2, spc7_ctu_mbisterr_buf2, sctag1_ctu_tr_buf2, sctag3_ctu_tr_buf2}),
); */
//
ctu_bottom_rptr2 ctu_bottom_rptr2
(/*AUTOINST*/
// Outputs
.l2_dbgbus_out ({ctu_bottom_rptr2_unused[19:0], ctu_sctag1_mbisten_buf, ctu_sctag3_mbisten_buf, ctu_spc1_mbisten_buf, ctu_spc3_mbisten_buf, ctu_spc5_mbisten_buf, ctu_spc7_mbisten_buf, sctag1_ctu_mbistdone_buf2, sctag1_ctu_mbisterr_buf2, sctag3_ctu_mbistdone_buf2, sctag3_ctu_mbisterr_buf2, spc1_ctu_mbistdone_buf2, spc1_ctu_mbisterr_buf2, spc3_ctu_mbistdone_buf2, spc3_ctu_mbisterr_buf2, spc5_ctu_mbistdone_buf2, spc5_ctu_mbisterr_buf2, spc7_ctu_mbistdone_buf2, spc7_ctu_mbisterr_buf2, sctag1_ctu_tr_buf2, sctag3_ctu_tr_buf2}), // Templated
.enable_01 (), // Templated
.so (rbot2_ctu_so), // Templated
// Inputs
.dbgbus_b0 ({1'b0, 40'b0}), // Templated
.dbgbus_b1 ({1'b0, 20'b0, ctu_sctag1_mbisten, ctu_sctag3_mbisten, ctu_spc1_mbisten, ctu_spc3_mbisten, ctu_spc5_mbisten, ctu_spc7_mbisten, sctag1_ctu_mbistdone_buf, sctag1_ctu_mbisterr_buf, sctag3_ctu_mbistdone_buf, sctag3_ctu_mbisterr_buf, spc1_ctu_mbistdone_buf, spc1_ctu_mbisterr_buf, spc3_ctu_mbistdone_buf, spc3_ctu_mbisterr_buf, spc5_ctu_mbistdone_buf, spc5_ctu_mbisterr_buf, spc7_ctu_mbistdone_buf, spc7_ctu_mbisterr_buf, sctag1_ctu_tr_buf, sctag3_ctu_tr_buf}), // Templated
.rclk (ccx_rclk), // Templated
.si (rdram1_rbot2_so), // Templated
.se (global_shift_enable)); // Templated
//
`ifdef RTL_FLOP_RPTRS
/* bw_clk_gl AUTO_TEMPLATE (
.gclk_cmp\(.*\) (cmp_gclk\1[]),
.gclk_ddr\(.*\) (dram_gclk\1[]),
.gclk_jbus\(.*\) (jbus_gclk\1[]),
.clk_fdbk_in (jbus_gclk_dup_out),
.clk_fdbk_out (jbus_gclk_dup),
); */
//
bw_clk_gl bw_clk_gl
(/*AUTOINST*/
// Outputs
.gclk_jbus_c0_r (jbus_gclk_c0_r[7:0]), // Templated
.gclk_cmp_c3_r (cmp_gclk_c3_r[7:0]), // Templated
.gclk_ddr_c3_r (dram_gclk_c3_r[7:0]), // Templated
.gclk_jbus_c2_r (jbus_gclk_c2_r[7:0]), // Templated
.gclk_cmp_c2_r (cmp_gclk_c2_r[7:0]), // Templated
.gclk_ddr_c2_r (dram_gclk_c2_r[7:0]), // Templated
.gclk_jbus_c1_r (jbus_gclk_c1_r[7:0]), // Templated
.gclk_cmp_c1_r (cmp_gclk_c1_r[7:0]), // Templated
.gclk_ddr_c1_r (dram_gclk_c1_r[7:0]), // Templated
.gclk_cmp_c0_r (cmp_gclk_c0_r[7:0]), // Templated
.gclk_jbus_c3_r (jbus_gclk_c3_r[7:0]), // Templated
.gclk_ddr_c0_r (dram_gclk_c0_r[7:0]), // Templated
.clk_fdbk_out (jbus_gclk_dup), // Templated
// Inputs
.clk_fdbk_in (jbus_gclk_dup_out), // Templated
.gclk_jbus (jbus_gclk), // Templated
.gclk_ddr (dram_gclk), // Templated
.gclk_cmp (cmp_gclk)); // Templated
//
/* bw_clk_gl_rstce_rtl AUTO_TEMPLATE (
.se (global_shift_enable),
.sd ({rptrs_xc7_so, pjbusr_rptrs_so, pjbusl_rptrs_so, rptrs_xc4_so, rptrs_xa1_so, rptrs_xb1_so, rptrs_xa0_so, rptrs_xc1_so, rptrs_xc6_so, rptrs_xc5_so, rptrs_xb3_so, rptrs_xc0_so, rptrs_xb2_so, rsc02_rptrs_so}),
.so ({rptrs_xc6_so, rptrs_xc7_so, rptrs_xc4_so, rptrs_xc5_so, rptrs_rsc12_so, rptrs_pmisc_so, rptrs_xc1_so, rptrs_xc0_so, rptrs_xb3_so, rptrs_xb2_so, rptrs_xb1_so, rptrs_pdbg_so, rptrs_xa1_so, rptrs_xa0_so}),
.gclk_a0 (cmp_gclk_c1_r[3] ),
.gclk_a1 (cmp_gclk_c1_r[4] ),
.gclk_b0 (cmp_gclk_c1_r[2] ),
.gclk_b1 (cmp_gclk_c2_r[3] ),
.gclk_b2 (cmp_gclk_c1_r[5] ),
.gclk_b3 (cmp_gclk_c2_r[4] ),
.gclk_c0 (cmp_gclk_c1_r[1] ),
.gclk_c1 (cmp_gclk_c1_r[2] ),
.gclk_c2 (cmp_gclk_c2_r[2] ),
.gclk_c3 (cmp_gclk_c1_r[4] ),
.gclk_c4 (cmp_gclk_c1_r[5] ),
.gclk_c5 (cmp_gclk_c1_r[6] ),
.gclk_c6 (cmp_gclk_c2_r[4] ),
.gclk_c7 (cmp_gclk_c2_r[5] ),
.cmp_ag\(.*\) (cmp_a\1),
.cmp_grst_l (cmp_grst_out_l),
.cmp_gdbginit_l (cmp_gdbginit_out_l),
.ctu_scbuf\([0-3]\)_cken (ctu_scdata\1_cmp_cken),
.ctu_\(.*\)_cken (ctu_\1_cmp_cken),
.gclk_\(.*\)_cken (rpt_\1_cmp_cken),
.ctu_\(.*\)_sync (ctu_\1_sync_out),
.grst_l_c\([0-7]\) (rpt_cmp_grst_l_c\1),
.gdbginit_l_c\([0123457]\) (rpt_cmp_gdbginit_l_c\1),
.dram_rx_sync_c\([16]\) (rpt_cmp_dram_rx_sync_c\1),
.dram_tx_sync_c\([16]\) (rpt_cmp_dram_tx_sync_c\1),
.jbus_rx_sync_c\([146]\) (rpt_cmp_jbus_rx_sync_c\1),
.jbus_tx_sync_c\([146]\) (rpt_cmp_jbus_tx_sync_c\1),
.\(.*\)_c\([0-7]\) (),
); */
//
bw_clk_gl_rstce_rtl flop_rptrs
(/*AUTOINST*/
// Outputs
.so ({rptrs_xc6_so, rptrs_xc7_so, rptrs_xc4_so, rptrs_xc5_so, rptrs_rsc12_so, rptrs_pmisc_so, rptrs_xc1_so, rptrs_xc0_so, rptrs_xb3_so, rptrs_xb2_so, rptrs_xb1_so, rptrs_pdbg_so, rptrs_xa1_so, rptrs_xa0_so}), // Templated
.grst_l_c0 (rpt_cmp_grst_l_c0), // Templated
.grst_l_c1 (rpt_cmp_grst_l_c1), // Templated
.grst_l_c2 (rpt_cmp_grst_l_c2), // Templated
.grst_l_c3 (rpt_cmp_grst_l_c3), // Templated
.grst_l_c4 (rpt_cmp_grst_l_c4), // Templated
.grst_l_c5 (rpt_cmp_grst_l_c5), // Templated
.grst_l_c6 (rpt_cmp_grst_l_c6), // Templated
.grst_l_c7 (rpt_cmp_grst_l_c7), // Templated
.gdbginit_l_c0 (rpt_cmp_gdbginit_l_c0), // Templated
.gdbginit_l_c1 (rpt_cmp_gdbginit_l_c1), // Templated
.gdbginit_l_c2 (rpt_cmp_gdbginit_l_c2), // Templated
.gdbginit_l_c3 (rpt_cmp_gdbginit_l_c3), // Templated
.gdbginit_l_c4 (rpt_cmp_gdbginit_l_c4), // Templated
.gdbginit_l_c5 (rpt_cmp_gdbginit_l_c5), // Templated
.gdbginit_l_c6 (), // Templated
.gdbginit_l_c7 (rpt_cmp_gdbginit_l_c7), // Templated
.dram_rx_sync_c0 (), // Templated
.dram_rx_sync_c1 (rpt_cmp_dram_rx_sync_c1), // Templated
.dram_rx_sync_c2 (), // Templated
.dram_rx_sync_c3 (), // Templated
.dram_rx_sync_c4 (), // Templated
.dram_rx_sync_c5 (), // Templated
.dram_rx_sync_c6 (rpt_cmp_dram_rx_sync_c6), // Templated
.dram_rx_sync_c7 (), // Templated
.dram_tx_sync_c0 (), // Templated
.dram_tx_sync_c1 (rpt_cmp_dram_tx_sync_c1), // Templated
.dram_tx_sync_c2 (), // Templated
.dram_tx_sync_c3 (), // Templated
.dram_tx_sync_c4 (), // Templated
.dram_tx_sync_c5 (), // Templated
.dram_tx_sync_c6 (rpt_cmp_dram_tx_sync_c6), // Templated
.dram_tx_sync_c7 (), // Templated
.jbus_rx_sync_c0 (), // Templated
.jbus_rx_sync_c1 (rpt_cmp_jbus_rx_sync_c1), // Templated
.jbus_rx_sync_c2 (), // Templated
.jbus_rx_sync_c3 (), // Templated
.jbus_rx_sync_c4 (rpt_cmp_jbus_rx_sync_c4), // Templated
.jbus_rx_sync_c5 (), // Templated
.jbus_rx_sync_c6 (rpt_cmp_jbus_rx_sync_c6), // Templated
.jbus_rx_sync_c7 (), // Templated
.jbus_tx_sync_c0 (), // Templated
.jbus_tx_sync_c1 (rpt_cmp_jbus_tx_sync_c1), // Templated
.jbus_tx_sync_c2 (), // Templated
.jbus_tx_sync_c3 (), // Templated
.jbus_tx_sync_c4 (rpt_cmp_jbus_tx_sync_c4), // Templated
.jbus_tx_sync_c5 (), // Templated
.jbus_tx_sync_c6 (rpt_cmp_jbus_tx_sync_c6), // Templated
.jbus_tx_sync_c7 (), // Templated
.gclk_spc0_cken (rpt_spc0_cmp_cken), // Templated
.gclk_spc1_cken (rpt_spc1_cmp_cken), // Templated
.gclk_spc2_cken (rpt_spc2_cmp_cken), // Templated
.gclk_spc3_cken (rpt_spc3_cmp_cken), // Templated
.gclk_spc4_cken (rpt_spc4_cmp_cken), // Templated
.gclk_spc5_cken (rpt_spc5_cmp_cken), // Templated
.gclk_spc6_cken (rpt_spc6_cmp_cken), // Templated
.gclk_spc7_cken (rpt_spc7_cmp_cken), // Templated
.gclk_scbuf0_cken (rpt_scbuf0_cmp_cken), // Templated
.gclk_scbuf1_cken (rpt_scbuf1_cmp_cken), // Templated
.gclk_scbuf2_cken (rpt_scbuf2_cmp_cken), // Templated
.gclk_scbuf3_cken (rpt_scbuf3_cmp_cken), // Templated
.gclk_scdata0_cken (rpt_scdata0_cmp_cken), // Templated
.gclk_scdata1_cken (rpt_scdata1_cmp_cken), // Templated
.gclk_scdata2_cken (rpt_scdata2_cmp_cken), // Templated
.gclk_scdata3_cken (rpt_scdata3_cmp_cken), // Templated
.gclk_sctag0_cken (rpt_sctag0_cmp_cken), // Templated
.gclk_sctag1_cken (rpt_sctag1_cmp_cken), // Templated
.gclk_sctag2_cken (rpt_sctag2_cmp_cken), // Templated
.gclk_sctag3_cken (rpt_sctag3_cmp_cken), // Templated
.gclk_dram02_cken (rpt_dram02_cmp_cken), // Templated
.gclk_dram13_cken (rpt_dram13_cmp_cken), // Templated
.gclk_ccx_cken (rpt_ccx_cmp_cken), // Templated
.gclk_fpu_cken (rpt_fpu_cmp_cken), // Templated
.gclk_iob_cken (rpt_iob_cmp_cken), // Templated
.gclk_jbi_cken (rpt_jbi_cmp_cken), // Templated
// Inputs
.se (global_shift_enable), // Templated
.sd ({rptrs_xc7_so, pjbusr_rptrs_so, pjbusl_rptrs_so, rptrs_xc4_so, rptrs_xa1_so, rptrs_xb1_so, rptrs_xa0_so, rptrs_xc1_so, rptrs_xc6_so, rptrs_xc5_so, rptrs_xb3_so, rptrs_xc0_so, rptrs_xb2_so, rsc02_rptrs_so}), // Templated
.gclk_a0 (cmp_gclk_c1_r[3] ), // Templated
.gclk_a1 (cmp_gclk_c1_r[4] ), // Templated
.gclk_b0 (cmp_gclk_c1_r[2] ), // Templated
.gclk_b1 (cmp_gclk_c2_r[3] ), // Templated
.gclk_b2 (cmp_gclk_c1_r[5] ), // Templated
.gclk_b3 (cmp_gclk_c2_r[4] ), // Templated
.gclk_c0 (cmp_gclk_c1_r[1] ), // Templated
.gclk_c1 (cmp_gclk_c1_r[2] ), // Templated
.gclk_c2 (cmp_gclk_c2_r[2] ), // Templated
.gclk_c3 (cmp_gclk_c1_r[4] ), // Templated
.gclk_c4 (cmp_gclk_c1_r[5] ), // Templated
.gclk_c5 (cmp_gclk_c1_r[6] ), // Templated
.gclk_c6 (cmp_gclk_c2_r[4] ), // Templated
.gclk_c7 (cmp_gclk_c2_r[5] ), // Templated
.cmp_agrst_l (cmp_arst_l), // Templated
.cmp_agdbginit_l (cmp_adbginit_l), // Templated
.cmp_grst_l (cmp_grst_out_l), // Templated
.cmp_gdbginit_l (cmp_gdbginit_out_l), // Templated
.ctu_dram_rx_sync (ctu_dram_rx_sync_out), // Templated
.ctu_dram_tx_sync (ctu_dram_tx_sync_out), // Templated
.ctu_jbus_rx_sync (ctu_jbus_rx_sync_out), // Templated
.ctu_jbus_tx_sync (ctu_jbus_tx_sync_out), // Templated
.ctu_spc0_cken (ctu_spc0_cmp_cken), // Templated
.ctu_spc1_cken (ctu_spc1_cmp_cken), // Templated
.ctu_spc2_cken (ctu_spc2_cmp_cken), // Templated
.ctu_spc3_cken (ctu_spc3_cmp_cken), // Templated
.ctu_spc4_cken (ctu_spc4_cmp_cken), // Templated
.ctu_spc5_cken (ctu_spc5_cmp_cken), // Templated
.ctu_spc6_cken (ctu_spc6_cmp_cken), // Templated
.ctu_spc7_cken (ctu_spc7_cmp_cken), // Templated
.ctu_scbuf0_cken (ctu_scdata0_cmp_cken), // Templated
.ctu_scbuf1_cken (ctu_scdata1_cmp_cken), // Templated
.ctu_scbuf2_cken (ctu_scdata2_cmp_cken), // Templated
.ctu_scbuf3_cken (ctu_scdata3_cmp_cken), // Templated
.ctu_scdata0_cken (ctu_scdata0_cmp_cken), // Templated
.ctu_scdata1_cken (ctu_scdata1_cmp_cken), // Templated
.ctu_scdata2_cken (ctu_scdata2_cmp_cken), // Templated
.ctu_scdata3_cken (ctu_scdata3_cmp_cken), // Templated
.ctu_sctag0_cken (ctu_sctag0_cmp_cken), // Templated
.ctu_sctag3_cken (ctu_sctag3_cmp_cken), // Templated
.ctu_sctag2_cken (ctu_sctag2_cmp_cken), // Templated
.ctu_sctag1_cken (ctu_sctag1_cmp_cken), // Templated
.ctu_dram02_cken (ctu_dram02_cmp_cken), // Templated
.ctu_dram13_cken (ctu_dram13_cmp_cken), // Templated
.ctu_ccx_cken (ctu_ccx_cmp_cken), // Templated
.ctu_fpu_cken (ctu_fpu_cmp_cken), // Templated
.ctu_iob_cken (ctu_iob_cmp_cken), // Templated
.ctu_jbi_cken (ctu_jbi_cmp_cken)); // Templated
`endif
//
/* efc AUTO_TEMPLATE (
.jbus_gclk (jbus_gclk_c3_r[3]),
.tck (ctu_efc_tck),
.clk_efc_cken (ctu_efc_jbus_cken),
.efc_ctu_scanout (par_scan_tail[21]),
.ctu_efc_scanin (rsc32_efc_so),
.vddo (VDDCO),
.io_vpp (VPP),
); */
//
`ifdef RTL_EFC
efc efc
(/*AUTOINST*/
// Outputs
.efc_ctu_scanout (par_scan_tail[21]), // Templated
.efc_ctu_data_out (efc_ctu_data_out),
.efc_spc1357_fuse_clk1 (efc_spc1357_fuse_clk1),
.efc_spc1357_fuse_clk2 (efc_spc1357_fuse_clk2),
.efc_spc0246_fuse_clk1 (efc_spc0246_fuse_clk1),
.efc_spc0246_fuse_clk2 (efc_spc0246_fuse_clk2),
.efc_spc1357_fuse_data (efc_spc1357_fuse_data),
.efc_spc0246_fuse_data (efc_spc0246_fuse_data),
.efc_spc7_ifuse_ashift (efc_spc7_ifuse_ashift),
.efc_spc7_ifuse_dshift (efc_spc7_ifuse_dshift),
.efc_spc7_dfuse_ashift (efc_spc7_dfuse_ashift),
.efc_spc7_dfuse_dshift (efc_spc7_dfuse_dshift),
.efc_spc6_ifuse_ashift (efc_spc6_ifuse_ashift),
.efc_spc6_ifuse_dshift (efc_spc6_ifuse_dshift),
.efc_spc6_dfuse_ashift (efc_spc6_dfuse_ashift),
.efc_spc6_dfuse_dshift (efc_spc6_dfuse_dshift),
.efc_spc5_ifuse_ashift (efc_spc5_ifuse_ashift),
.efc_spc5_ifuse_dshift (efc_spc5_ifuse_dshift),
.efc_spc5_dfuse_ashift (efc_spc5_dfuse_ashift),
.efc_spc5_dfuse_dshift (efc_spc5_dfuse_dshift),
.efc_spc4_ifuse_ashift (efc_spc4_ifuse_ashift),
.efc_spc4_ifuse_dshift (efc_spc4_ifuse_dshift),
.efc_spc4_dfuse_ashift (efc_spc4_dfuse_ashift),
.efc_spc4_dfuse_dshift (efc_spc4_dfuse_dshift),
.efc_spc3_ifuse_ashift (efc_spc3_ifuse_ashift),
.efc_spc3_ifuse_dshift (efc_spc3_ifuse_dshift),
.efc_spc3_dfuse_ashift (efc_spc3_dfuse_ashift),
.efc_spc3_dfuse_dshift (efc_spc3_dfuse_dshift),
.efc_spc2_ifuse_ashift (efc_spc2_ifuse_ashift),
.efc_spc2_ifuse_dshift (efc_spc2_ifuse_dshift),
.efc_spc2_dfuse_ashift (efc_spc2_dfuse_ashift),
.efc_spc2_dfuse_dshift (efc_spc2_dfuse_dshift),
.efc_spc1_ifuse_ashift (efc_spc1_ifuse_ashift),
.efc_spc1_ifuse_dshift (efc_spc1_ifuse_dshift),
.efc_spc1_dfuse_ashift (efc_spc1_dfuse_ashift),
.efc_spc1_dfuse_dshift (efc_spc1_dfuse_dshift),
.efc_spc0_ifuse_ashift (efc_spc0_ifuse_ashift),
.efc_spc0_ifuse_dshift (efc_spc0_ifuse_dshift),
.efc_spc0_dfuse_ashift (efc_spc0_dfuse_ashift),
.efc_spc0_dfuse_dshift (efc_spc0_dfuse_dshift),
.efc_sctag02_fuse_clk1 (efc_sctag02_fuse_clk1),
.efc_sctag02_fuse_clk2 (efc_sctag02_fuse_clk2),
.efc_sctag02_fuse_data (efc_sctag02_fuse_data),
.efc_sctag13_fuse_clk1 (efc_sctag13_fuse_clk1),
.efc_sctag13_fuse_clk2 (efc_sctag13_fuse_clk2),
.efc_sctag13_fuse_data (efc_sctag13_fuse_data),
.efc_sctag3_fuse_ashift (efc_sctag3_fuse_ashift),
.efc_sctag3_fuse_dshift (efc_sctag3_fuse_dshift),
.efc_sctag2_fuse_ashift (efc_sctag2_fuse_ashift),
.efc_sctag2_fuse_dshift (efc_sctag2_fuse_dshift),
.efc_sctag1_fuse_ashift (efc_sctag1_fuse_ashift),
.efc_sctag1_fuse_dshift (efc_sctag1_fuse_dshift),
.efc_sctag0_fuse_ashift (efc_sctag0_fuse_ashift),
.efc_sctag0_fuse_dshift (efc_sctag0_fuse_dshift),
.efc_scdata02_fuse_clk1 (efc_scdata02_fuse_clk1),
.efc_scdata02_fuse_clk2 (efc_scdata02_fuse_clk2),
.efc_scdata02_fuse_data (efc_scdata02_fuse_data),
.efc_scdata13_fuse_clk1 (efc_scdata13_fuse_clk1),
.efc_scdata13_fuse_clk2 (efc_scdata13_fuse_clk2),
.efc_scdata13_fuse_data (efc_scdata13_fuse_data),
.efc_scdata3_fuse_ashift (efc_scdata3_fuse_ashift),
.efc_scdata3_fuse_dshift (efc_scdata3_fuse_dshift),
.efc_scdata2_fuse_ashift (efc_scdata2_fuse_ashift),
.efc_scdata2_fuse_dshift (efc_scdata2_fuse_dshift),
.efc_scdata1_fuse_ashift (efc_scdata1_fuse_ashift),
.efc_scdata1_fuse_dshift (efc_scdata1_fuse_dshift),
.efc_scdata0_fuse_ashift (efc_scdata0_fuse_ashift),
.efc_scdata0_fuse_dshift (efc_scdata0_fuse_dshift),
.efc_iob_fuse_clk1 (efc_iob_fuse_clk1),
.efc_iob_fuse_data (efc_iob_fuse_data),
.efc_iob_sernum0_dshift (efc_iob_sernum0_dshift),
.efc_iob_sernum1_dshift (efc_iob_sernum1_dshift),
.efc_iob_sernum2_dshift (efc_iob_sernum2_dshift),
.efc_iob_fusestat_dshift (efc_iob_fusestat_dshift),
.efc_iob_coreavail_dshift (efc_iob_coreavail_dshift),
// Inputs
.io_vpp (VPP), // Templated
.vddo (VDDCO), // Templated
.jbus_gclk (jbus_gclk_c3_r[3]), // Templated
.jbus_arst_l (jbus_arst_l),
.jbus_grst_l (jbus_grst_l),
.ctu_tst_scanmode (ctu_tst_scanmode),
.clk_efc_cken (ctu_efc_jbus_cken), // Templated
.global_shift_enable (global_shift_enable),
.ctu_efc_scanin (rsc32_efc_so), // Templated
.jbus_adbginit_l (jbus_adbginit_l),
.jbus_gdbginit_l (jbus_gdbginit_l),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_short_chain (ctu_tst_short_chain),
.ctu_efc_rowaddr (ctu_efc_rowaddr[6:0]),
.ctu_efc_coladdr (ctu_efc_coladdr[4:0]),
.io_pgrm_en (io_pgrm_en),
.ctu_efc_read_en (ctu_efc_read_en),
.ctu_efc_read_mode (ctu_efc_read_mode[2:0]),
.ctu_efc_read_start (ctu_efc_read_start),
.ctu_efc_fuse_bypass (ctu_efc_fuse_bypass),
.ctu_efc_dest_sample (ctu_efc_dest_sample),
.ctu_efc_data_in (ctu_efc_data_in),
.ctu_efc_updatedr (ctu_efc_updatedr),
.ctu_efc_shiftdr (ctu_efc_shiftdr),
.ctu_efc_capturedr (ctu_efc_capturedr),
.tck (ctu_efc_tck), // Templated
.spc7_efc_ifuse_data (spc7_efc_ifuse_data),
.spc7_efc_dfuse_data (spc7_efc_dfuse_data),
.spc6_efc_ifuse_data (spc6_efc_ifuse_data),
.spc6_efc_dfuse_data (spc6_efc_dfuse_data),
.spc5_efc_ifuse_data (spc5_efc_ifuse_data),
.spc5_efc_dfuse_data (spc5_efc_dfuse_data),
.spc4_efc_ifuse_data (spc4_efc_ifuse_data),
.spc4_efc_dfuse_data (spc4_efc_dfuse_data),
.spc3_efc_ifuse_data (spc3_efc_ifuse_data),
.spc3_efc_dfuse_data (spc3_efc_dfuse_data),
.spc2_efc_ifuse_data (spc2_efc_ifuse_data),
.spc2_efc_dfuse_data (spc2_efc_dfuse_data),
.spc1_efc_ifuse_data (spc1_efc_ifuse_data),
.spc1_efc_dfuse_data (spc1_efc_dfuse_data),
.spc0_efc_ifuse_data (spc0_efc_ifuse_data),
.spc0_efc_dfuse_data (spc0_efc_dfuse_data),
.sctag3_efc_fuse_data (sctag3_efc_fuse_data),
.sctag2_efc_fuse_data (sctag2_efc_fuse_data),
.sctag1_efc_fuse_data (sctag1_efc_fuse_data),
.sctag0_efc_fuse_data (sctag0_efc_fuse_data),
.scdata3_efc_fuse_data (scdata3_efc_fuse_data),
.scdata2_efc_fuse_data (scdata2_efc_fuse_data),
.scdata1_efc_fuse_data (scdata1_efc_fuse_data),
.scdata0_efc_fuse_data (scdata0_efc_fuse_data));
`endif
//
/* iobdg AUTO_TEMPLATE (
.iob_scanin (par_scan_head[10]),
.iob_scanout (par_scan_tail[10]),
.jbus_gclk (jbus_gclk_c1_r[3]),
.cmp_gclk (cmp_gclk_c1_r[3]),
.cmp_grst_l (rpt_cmp_grst_l_c1),
.cmp_gdbginit_l (rpt_cmp_gdbginit_l_c2),
.clspine_jbus_rx_sync (rpt_cmp_jbus_rx_sync_c1),
.clspine_jbus_tx_sync (rpt_cmp_jbus_tx_sync_c1),
.clk_iob_cmp_cken (rpt_iob_cmp_cken),
.clk_iob_jbus_cken (ctu_iob_jbus_cken),
.clspine_iob_resetstat_wr (ctu_iob_resetstat_wr),
.clspine_iob_resetstat (ctu_iob_resetstat[]),
.iob_clk_l2_tr (iob_ctu_l2_tr),
.iob_clk_tr (iob_ctu_tr),
.clk_iob_stall (clsp_iob_stall),
.clk_iob_vld (clsp_iob_vld),
.clk_iob_data (clsp_iob_data[]),
.iob_clk_stall (iob_clsp_stall),
.iob_clk_vld (iob_clsp_vld),
.iob_clk_data (iob_clsp_data[]),
.cpx_iob_\(.*\) (cpx_iob_\1_buf[]),
.jbi_iob_\(.*\) (jbi_iob_\1_buf[]),
.pcx_iob_\(.*\) (pcx_iob_\1_buf[]),
); */
//
`ifdef RTL_IOBDG
iobdg iobdg
(/*AUTOINST*/
// Outputs
.iob_clk_l2_tr (iob_ctu_l2_tr), // Templated
.iob_clk_tr (iob_ctu_tr), // Templated
.iob_cpx_data_ca (iob_cpx_data_ca[`CPX_WIDTH-1:0]),
.iob_cpx_req_cq (iob_cpx_req_cq[`IOB_CPU_WIDTH-1:0]),
.iob_ctu_coreavail (iob_ctu_coreavail[`IOB_CPU_WIDTH-1:0]),
.iob_io_dbg_ck_n (iob_io_dbg_ck_n[2:0]),
.iob_io_dbg_ck_p (iob_io_dbg_ck_p[2:0]),
.iob_io_dbg_data (iob_io_dbg_data[39:0]),
.iob_io_dbg_en (iob_io_dbg_en),
.iob_jbi_dbg_hi_data (iob_jbi_dbg_hi_data[47:0]),
.iob_jbi_dbg_hi_vld (iob_jbi_dbg_hi_vld),
.iob_jbi_dbg_lo_data (iob_jbi_dbg_lo_data[47:0]),
.iob_jbi_dbg_lo_vld (iob_jbi_dbg_lo_vld),
.iob_jbi_mondo_ack (iob_jbi_mondo_ack),
.iob_jbi_mondo_nack (iob_jbi_mondo_nack),
.iob_pcx_stall_pq (iob_pcx_stall_pq),
.iob_clk_data (iob_clsp_data[`IOB_CLK_WIDTH-1:0]), // Templated
.iob_clk_stall (iob_clsp_stall), // Templated
.iob_clk_vld (iob_clsp_vld), // Templated
.iob_dram02_data (iob_dram02_data[`IOB_DRAM_WIDTH-1:0]),
.iob_dram02_stall (iob_dram02_stall),
.iob_dram02_vld (iob_dram02_vld),
.iob_dram13_data (iob_dram13_data[`IOB_DRAM_WIDTH-1:0]),
.iob_dram13_stall (iob_dram13_stall),
.iob_dram13_vld (iob_dram13_vld),
.iob_jbi_pio_data (iob_jbi_pio_data[`IOB_JBI_WIDTH-1:0]),
.iob_jbi_pio_stall (iob_jbi_pio_stall),
.iob_jbi_pio_vld (iob_jbi_pio_vld),
.iob_jbi_spi_data (iob_jbi_spi_data[`IOB_SPI_WIDTH-1:0]),
.iob_jbi_spi_stall (iob_jbi_spi_stall),
.iob_jbi_spi_vld (iob_jbi_spi_vld),
.iob_tap_data (iob_tap_data[`IOB_TAP_WIDTH-1:0]),
.iob_tap_stall (iob_tap_stall),
.iob_tap_vld (iob_tap_vld),
.iob_scanout (par_scan_tail[10]), // Templated
// Inputs
.clk_iob_cmp_cken (rpt_iob_cmp_cken), // Templated
.clk_iob_data (clsp_iob_data[`CLK_IOB_WIDTH-1:0]), // Templated
.clk_iob_jbus_cken (ctu_iob_jbus_cken), // Templated
.clk_iob_stall (clsp_iob_stall), // Templated
.clk_iob_vld (clsp_iob_vld), // Templated
.clspine_iob_resetstat (ctu_iob_resetstat[`IOB_RESET_STAT_WIDTH-1:0]), // Templated
.clspine_iob_resetstat_wr (ctu_iob_resetstat_wr), // Templated
.clspine_jbus_rx_sync (rpt_cmp_jbus_rx_sync_c1), // Templated
.clspine_jbus_tx_sync (rpt_cmp_jbus_tx_sync_c1), // Templated
.cmp_adbginit_l (cmp_adbginit_l),
.cmp_arst_l (cmp_arst_l),
.cmp_gclk (cmp_gclk_c1_r[3]), // Templated
.cmp_gdbginit_l (rpt_cmp_gdbginit_l_c2), // Templated
.cmp_grst_l (rpt_cmp_grst_l_c1), // Templated
.cpx_iob_grant_cx2 (cpx_iob_grant_cx2_buf[`IOB_CPU_WIDTH-1:0]), // Templated
.ctu_iob_wake_thr (ctu_iob_wake_thr),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_short_chain (ctu_tst_short_chain),
.dbg_en_01 (dbg_en_01),
.dbg_en_23 (dbg_en_23),
.dram02_iob_data (dram02_iob_data[`DRAM_IOB_WIDTH-1:0]),
.dram02_iob_stall (dram02_iob_stall),
.dram02_iob_vld (dram02_iob_vld),
.dram13_iob_data (dram13_iob_data[`DRAM_IOB_WIDTH-1:0]),
.dram13_iob_stall (dram13_iob_stall),
.dram13_iob_vld (dram13_iob_vld),
.efc_iob_coreavail_dshift (efc_iob_coreavail_dshift),
.efc_iob_fuse_data (efc_iob_fuse_data),
.efc_iob_fusestat_dshift (efc_iob_fusestat_dshift),
.efc_iob_sernum0_dshift (efc_iob_sernum0_dshift),
.efc_iob_sernum1_dshift (efc_iob_sernum1_dshift),
.efc_iob_sernum2_dshift (efc_iob_sernum2_dshift),
.global_shift_enable (global_shift_enable),
.io_temp_trig (io_temp_trig),
.io_trigin (io_trigin),
.jbi_iob_mondo_data (jbi_iob_mondo_data_buf[`JBI_IOB_MONDO_BUS_WIDTH-1:0]), // Templated
.jbi_iob_mondo_vld (jbi_iob_mondo_vld_buf), // Templated
.jbi_iob_pio_data (jbi_iob_pio_data_buf[`JBI_IOB_WIDTH-1:0]), // Templated
.jbi_iob_pio_stall (jbi_iob_pio_stall_buf), // Templated
.jbi_iob_pio_vld (jbi_iob_pio_vld_buf), // Templated
.jbi_iob_spi_data (jbi_iob_spi_data_buf[`SPI_IOB_WIDTH-1:0]), // Templated
.jbi_iob_spi_stall (jbi_iob_spi_stall_buf), // Templated
.jbi_iob_spi_vld (jbi_iob_spi_vld_buf), // Templated
.jbus_adbginit_l (jbus_adbginit_l),
.jbus_arst_l (jbus_arst_l),
.jbus_gclk (jbus_gclk_c1_r[3]), // Templated
.jbus_gdbginit_l (jbus_gdbginit_l),
.jbus_grst_l (jbus_grst_l),
.l2_dbgbus_01 (l2_dbgbus_01[39:0]),
.l2_dbgbus_23 (l2_dbgbus_23[39:0]),
.pcx_iob_data_px2 (pcx_iob_data_px2_buf[`PCX_WIDTH-1:0]), // Templated
.pcx_iob_data_rdy_px2 (pcx_iob_data_rdy_px2_buf), // Templated
.tap_iob_data (tap_iob_data[`TAP_IOB_WIDTH-1:0]),
.tap_iob_stall (tap_iob_stall),
.tap_iob_vld (tap_iob_vld),
.efc_iob_fuse_clk1 (efc_iob_fuse_clk1),
.iob_scanin (par_scan_head[10])); // Templated
`endif
//
/* jbi AUTO_TEMPLATE (
.ddr3_jbi_scanin18 (pddr0_jbi_so),
.jbi_ddr3_scanout18 (par_scan_tail[6]),
.jbusr_jbi_si (),
.jbi_jbusr_se (),
.jbi_jbusr_so (),
.jbus_gclk (jbus_gclk_c2_r[5]),
.cmp_gclk (cmp_gclk_c2_r[5]),
.cmp_grst_l (rpt_cmp_grst_l_c4),
.ctu_jbi_rx_en (rpt_cmp_jbus_rx_sync_c4),
.ctu_jbi_tx_en (rpt_cmp_jbus_tx_sync_c4),
.clk_jbi_cmp_cken (rpt_jbi_cmp_cken),
.clk_jbi_jbus_cken (ctu_jbi_jbus_cken),
.jbi_clk_tr (jbi_ctu_tr),
.io_jbi_ext_int_l (io_ext_int_l),
.ctu_jbi_fst_rst_l (io_j_rst_l),
.scbuf\([0-3]\)_jbi_\(.*\)_buf (scbuf\1_jbi_\2_d2),
.scbuf\([0-3]\)_jbi_\(.*\) (scbuf\1_jbi_\2_d2),
.sctag\([0-3]\)_jbi_\(.*\)_buf (sctag\1_jbi_\2_d2),
.sctag\([0-3]\)_jbi_\(.*\) (sctag\1_jbi_\2_d2),
.iob_jbi_\(.*\) (iob_jbi_\1_buf[]),
); */
//
`ifdef RTL_JBI
jbi jbi
(/*AUTOINST*/
// Outputs
.jbi_ddr3_scanout18 (par_scan_tail[6]), // Templated
.jbi_clk_tr (jbi_ctu_tr), // Templated
.jbi_jbusr_so (), // Templated
.jbi_jbusr_se (), // Templated
.jbi_sctag0_req (jbi_sctag0_req[31:0]),
.jbi_scbuf0_ecc (jbi_scbuf0_ecc[6:0]),
.jbi_sctag0_req_vld (jbi_sctag0_req_vld),
.jbi_sctag1_req (jbi_sctag1_req[31:0]),
.jbi_scbuf1_ecc (jbi_scbuf1_ecc[6:0]),
.jbi_sctag1_req_vld (jbi_sctag1_req_vld),
.jbi_sctag2_req (jbi_sctag2_req[31:0]),
.jbi_scbuf2_ecc (jbi_scbuf2_ecc[6:0]),
.jbi_sctag2_req_vld (jbi_sctag2_req_vld),
.jbi_sctag3_req (jbi_sctag3_req[31:0]),
.jbi_scbuf3_ecc (jbi_scbuf3_ecc[6:0]),
.jbi_sctag3_req_vld (jbi_sctag3_req_vld),
.jbi_iob_pio_vld (jbi_iob_pio_vld),
.jbi_iob_pio_data (jbi_iob_pio_data[`JBI_IOB_WIDTH-1:0]),
.jbi_iob_pio_stall (jbi_iob_pio_stall),
.jbi_iob_mondo_vld (jbi_iob_mondo_vld),
.jbi_iob_mondo_data (jbi_iob_mondo_data[`JBI_IOB_MONDO_BUS_WIDTH-1:0]),
.jbi_io_ssi_mosi (jbi_io_ssi_mosi),
.jbi_io_ssi_sck (jbi_io_ssi_sck),
.jbi_iob_spi_vld (jbi_iob_spi_vld),
.jbi_iob_spi_data (jbi_iob_spi_data[`SPI_IOB_WIDTH-1:0]),
.jbi_iob_spi_stall (jbi_iob_spi_stall),
.jbi_io_j_req0_out_l (jbi_io_j_req0_out_l),
.jbi_io_j_req0_out_en (jbi_io_j_req0_out_en),
.jbi_io_j_adtype (jbi_io_j_adtype[7:0]),
.jbi_io_j_adtype_en (jbi_io_j_adtype_en),
.jbi_io_j_ad (jbi_io_j_ad[127:0]),
.jbi_io_j_ad_en (jbi_io_j_ad_en[3:0]),
.jbi_io_j_pack0 (jbi_io_j_pack0[2:0]),
.jbi_io_j_pack0_en (jbi_io_j_pack0_en),
.jbi_io_j_pack1 (jbi_io_j_pack1[2:0]),
.jbi_io_j_pack1_en (jbi_io_j_pack1_en),
.jbi_io_j_adp (jbi_io_j_adp[3:0]),
.jbi_io_j_adp_en (jbi_io_j_adp_en),
.jbi_io_config_dtl (jbi_io_config_dtl[1:0]),
// Inputs
.cmp_gclk (cmp_gclk_c2_r[5]), // Templated
.cmp_arst_l (cmp_arst_l),
.cmp_grst_l (rpt_cmp_grst_l_c4), // Templated
.jbus_gclk (jbus_gclk_c2_r[5]), // Templated
.jbus_arst_l (jbus_arst_l),
.jbus_grst_l (jbus_grst_l),
.ctu_jbi_ssiclk (ctu_jbi_ssiclk),
.ctu_jbi_tx_en (rpt_cmp_jbus_tx_sync_c4), // Templated
.ctu_jbi_rx_en (rpt_cmp_jbus_rx_sync_c4), // Templated
.ctu_jbi_fst_rst_l (io_j_rst_l), // Templated
.clk_jbi_jbus_cken (ctu_jbi_jbus_cken), // Templated
.clk_jbi_cmp_cken (rpt_jbi_cmp_cken), // Templated
.global_shift_enable (global_shift_enable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_short_chain (ctu_tst_short_chain),
.ddr3_jbi_scanin18 (pddr0_jbi_so), // Templated
.jbusr_jbi_si (), // Templated
.sctag0_jbi_iq_dequeue (sctag0_jbi_iq_dequeue_d2), // Templated
.sctag0_jbi_wib_dequeue (sctag0_jbi_wib_dequeue_d2), // Templated
.scbuf0_jbi_data (scbuf0_jbi_data_d2), // Templated
.scbuf0_jbi_ctag_vld (scbuf0_jbi_ctag_vld_d2), // Templated
.scbuf0_jbi_ue_err (scbuf0_jbi_ue_err_d2), // Templated
.sctag0_jbi_por_req_buf (sctag0_jbi_por_req_d2), // Templated
.sctag1_jbi_iq_dequeue (sctag1_jbi_iq_dequeue_d2), // Templated
.sctag1_jbi_wib_dequeue (sctag1_jbi_wib_dequeue_d2), // Templated
.scbuf1_jbi_data (scbuf1_jbi_data_d2), // Templated
.scbuf1_jbi_ctag_vld (scbuf1_jbi_ctag_vld_d2), // Templated
.scbuf1_jbi_ue_err (scbuf1_jbi_ue_err_d2), // Templated
.sctag1_jbi_por_req_buf (sctag1_jbi_por_req_d2), // Templated
.sctag2_jbi_iq_dequeue (sctag2_jbi_iq_dequeue_d2), // Templated
.sctag2_jbi_wib_dequeue (sctag2_jbi_wib_dequeue_d2), // Templated
.scbuf2_jbi_data (scbuf2_jbi_data_d2), // Templated
.scbuf2_jbi_ctag_vld (scbuf2_jbi_ctag_vld_d2), // Templated
.scbuf2_jbi_ue_err (scbuf2_jbi_ue_err_d2), // Templated
.sctag2_jbi_por_req_buf (sctag2_jbi_por_req_d2), // Templated
.sctag3_jbi_iq_dequeue (sctag3_jbi_iq_dequeue_d2), // Templated
.sctag3_jbi_wib_dequeue (sctag3_jbi_wib_dequeue_d2), // Templated
.scbuf3_jbi_data (scbuf3_jbi_data_d2), // Templated
.scbuf3_jbi_ctag_vld (scbuf3_jbi_ctag_vld_d2), // Templated
.scbuf3_jbi_ue_err (scbuf3_jbi_ue_err_d2), // Templated
.sctag3_jbi_por_req_buf (sctag3_jbi_por_req_d2), // Templated
.iob_jbi_pio_stall (iob_jbi_pio_stall_buf), // Templated
.iob_jbi_pio_vld (iob_jbi_pio_vld_buf), // Templated
.iob_jbi_pio_data (iob_jbi_pio_data_buf[`IOB_JBI_WIDTH-1:0]), // Templated
.iob_jbi_mondo_ack (iob_jbi_mondo_ack_buf), // Templated
.iob_jbi_mondo_nack (iob_jbi_mondo_nack_buf), // Templated
.io_jbi_ssi_miso (io_jbi_ssi_miso),
.io_jbi_ext_int_l (io_ext_int_l), // Templated
.iob_jbi_spi_vld (iob_jbi_spi_vld_buf), // Templated
.iob_jbi_spi_data (iob_jbi_spi_data_buf[`IOB_SPI_WIDTH-1:0]), // Templated
.iob_jbi_spi_stall (iob_jbi_spi_stall_buf), // Templated
.io_jbi_j_req4_in_l (io_jbi_j_req4_in_l),
.io_jbi_j_req5_in_l (io_jbi_j_req5_in_l),
.io_jbi_j_adtype (io_jbi_j_adtype[7:0]),
.io_jbi_j_ad (io_jbi_j_ad[127:0]),
.io_jbi_j_pack4 (io_jbi_j_pack4[2:0]),
.io_jbi_j_pack5 (io_jbi_j_pack5[2:0]),
.io_jbi_j_adp (io_jbi_j_adp[3:0]),
.io_jbi_j_par (io_jbi_j_par),
.iob_jbi_dbg_hi_data (iob_jbi_dbg_hi_data_buf[47:0]), // Templated
.iob_jbi_dbg_hi_vld (iob_jbi_dbg_hi_vld_buf), // Templated
.iob_jbi_dbg_lo_data (iob_jbi_dbg_lo_data_buf[47:0]), // Templated
.iob_jbi_dbg_lo_vld (iob_jbi_dbg_lo_vld_buf)); // Templated
`endif
//
/* sparc AUTO_TEMPLATE (
.const_cpuid (4'h@),
.const_maskid (ctu_spc_const_maskid[]),
.gclk (cmp_gclk_c1_r[0]),
.adbginit_l (cmp_adbginit_l),
.cmp_grst_l (rpt_cmp_grst_l_c0),
.gdbginit_l (rpt_cmp_gdbginit_l_c0),
.cluster_cken (rpt_spc@_cmp_cken),
.spc_scanin0 (par_scan_head[3]),
.spc_scanout0 (par_scan_tail[3]),
.spc_scanin1 (par_scan_head[4]),
.spc_scanout1 (par_scan_tail[4]),
.ctu_sscan_snap (ctu_global_snap),
.ctu_sscan_tid (ctu_spc_sscan_tid[]),
.ctu_sscan_se (ctu_spc@_sscan_se),
.spc_sscan_so (spc@_ctu_sscan_out),
.ctu_tck (ctu_spc@_tck),
.ctu_tst_mbist_enable (ctu_spc@_mbisten_buf2),
.tst_ctu_mbist_done (spc@_ctu_mbistdone),
.tst_ctu_mbist_fail (spc@_ctu_mbisterr),
.efc_spc_fuse_clk1 (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_clk1),
.efc_spc_fuse_clk2 (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_clk2),
.efc_spc_ifuse_data (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_data),
.efc_spc_dfuse_data (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_data),
.pcx_spc_grant_px (pcx_spc@_grant_px_buf1[4:0]),
.cpx_spc_data_rdy_cx2 (cpx_spc@_data_rdy_cx2_buf1),
.cpx_spc_data_cx2 (cpx_spc@_data_cx2_buf1[]),
.\(.*\)spc\(.*\) (\1spc@\2[]),
); */
//
`ifdef RTL_SPARC0
sparc sparc0
(/*AUTOINST*/
// Outputs
.spc_pcx_req_pq (spc0_pcx_req_pq[4:0]), // Templated
.spc_pcx_atom_pq (spc0_pcx_atom_pq), // Templated
.spc_pcx_data_pa (spc0_pcx_data_pa[`PCX_WIDTH-1:0]), // Templated
.spc_sscan_so (spc0_ctu_sscan_out), // Templated
.spc_scanout0 (par_scan_tail[3]), // Templated
.spc_scanout1 (par_scan_tail[4]), // Templated
.tst_ctu_mbist_done (spc0_ctu_mbistdone), // Templated
.tst_ctu_mbist_fail (spc0_ctu_mbisterr), // Templated
.spc_efc_ifuse_data (spc0_efc_ifuse_data), // Templated
.spc_efc_dfuse_data (spc0_efc_dfuse_data), // Templated
// Inputs
.pcx_spc_grant_px (pcx_spc0_grant_px_buf1[4:0]), // Templated
.cpx_spc_data_rdy_cx2 (cpx_spc0_data_rdy_cx2_buf1), // Templated
.cpx_spc_data_cx2 (cpx_spc0_data_cx2_buf1[`CPX_WIDTH-1:0]), // Templated
.const_cpuid (4'h0), // Templated
.const_maskid (ctu_spc_const_maskid[7:0]), // Templated
.ctu_tck (ctu_spc0_tck), // Templated
.ctu_sscan_se (ctu_spc0_sscan_se), // Templated
.ctu_sscan_snap (ctu_global_snap), // Templated
.ctu_sscan_tid (ctu_spc_sscan_tid[3:0]), // Templated
.ctu_tst_mbist_enable (ctu_spc0_mbisten_buf2), // Templated
.efc_spc_fuse_clk1 (efc_spc0246_fuse_clk1), // Templated
.efc_spc_fuse_clk2 (efc_spc0246_fuse_clk2), // Templated
.efc_spc_ifuse_ashift (efc_spc0_ifuse_ashift), // Templated
.efc_spc_ifuse_dshift (efc_spc0_ifuse_dshift), // Templated
.efc_spc_ifuse_data (efc_spc0246_fuse_data), // Templated
.efc_spc_dfuse_ashift (efc_spc0_dfuse_ashift), // Templated
.efc_spc_dfuse_dshift (efc_spc0_dfuse_dshift), // Templated
.efc_spc_dfuse_data (efc_spc0246_fuse_data), // Templated
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_short_chain (ctu_tst_short_chain),
.global_shift_enable (global_shift_enable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.spc_scanin0 (par_scan_head[3]), // Templated
.spc_scanin1 (par_scan_head[4]), // Templated
.cluster_cken (rpt_spc0_cmp_cken), // Templated
.gclk (cmp_gclk_c1_r[0]), // Templated
.cmp_grst_l (rpt_cmp_grst_l_c0), // Templated
.cmp_arst_l (cmp_arst_l),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.adbginit_l (cmp_adbginit_l), // Templated
.gdbginit_l (rpt_cmp_gdbginit_l_c0)); // Templated
`endif
//
/* sparc AUTO_TEMPLATE (
.const_cpuid (4'h@),
.const_maskid (ctu_spc_const_maskid[]),
.gclk (cmp_gclk_c1_r[7]),
.adbginit_l (cmp_adbginit_l),
.cmp_grst_l (rpt_cmp_grst_l_c5),
.gdbginit_l (rpt_cmp_gdbginit_l_c5),
.cluster_cken (rpt_spc@_cmp_cken),
.spc_scanin0 (par_scan_head[11]),
.spc_scanout0 (par_scan_tail[11]),
.spc_scanin1 (par_scan_head[12]),
.spc_scanout1 (par_scan_tail[12]),
.ctu_sscan_snap (ctu_global_snap),
.ctu_sscan_tid (ctu_spc_sscan_tid[]),
.ctu_sscan_se (ctu_spc@_sscan_se),
.spc_sscan_so (spc@_ctu_sscan_out),
.ctu_tck (ctu_spc@_tck),
.ctu_tst_mbist_enable (ctu_spc@_mbisten_buf2),
.tst_ctu_mbist_done (spc@_ctu_mbistdone),
.tst_ctu_mbist_fail (spc@_ctu_mbisterr),
.efc_spc_fuse_clk1 (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_clk1),
.efc_spc_fuse_clk2 (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_clk2),
.efc_spc_ifuse_data (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_data),
.efc_spc_dfuse_data (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_data),
.pcx_spc_grant_px (pcx_spc@_grant_px_buf1[4:0]),
.cpx_spc_data_rdy_cx2 (cpx_spc@_data_rdy_cx2_buf1),
.cpx_spc_data_cx2 (cpx_spc@_data_cx2_buf1[]),
.\(.*\)spc\(.*\) (\1spc@\2[]),
); */
//
`ifdef RTL_SPARC1
sparc sparc1
(/*AUTOINST*/
// Outputs
.spc_pcx_req_pq (spc1_pcx_req_pq[4:0]), // Templated
.spc_pcx_atom_pq (spc1_pcx_atom_pq), // Templated
.spc_pcx_data_pa (spc1_pcx_data_pa[`PCX_WIDTH-1:0]), // Templated
.spc_sscan_so (spc1_ctu_sscan_out), // Templated
.spc_scanout0 (par_scan_tail[11]), // Templated
.spc_scanout1 (par_scan_tail[12]), // Templated
.tst_ctu_mbist_done (spc1_ctu_mbistdone), // Templated
.tst_ctu_mbist_fail (spc1_ctu_mbisterr), // Templated
.spc_efc_ifuse_data (spc1_efc_ifuse_data), // Templated
.spc_efc_dfuse_data (spc1_efc_dfuse_data), // Templated
// Inputs
.pcx_spc_grant_px (pcx_spc1_grant_px_buf1[4:0]), // Templated
.cpx_spc_data_rdy_cx2 (cpx_spc1_data_rdy_cx2_buf1), // Templated
.cpx_spc_data_cx2 (cpx_spc1_data_cx2_buf1[`CPX_WIDTH-1:0]), // Templated
.const_cpuid (4'h1), // Templated
.const_maskid (ctu_spc_const_maskid[7:0]), // Templated
.ctu_tck (ctu_spc1_tck), // Templated
.ctu_sscan_se (ctu_spc1_sscan_se), // Templated
.ctu_sscan_snap (ctu_global_snap), // Templated
.ctu_sscan_tid (ctu_spc_sscan_tid[3:0]), // Templated
.ctu_tst_mbist_enable (ctu_spc1_mbisten_buf2), // Templated
.efc_spc_fuse_clk1 (efc_spc1357_fuse_clk1), // Templated
.efc_spc_fuse_clk2 (efc_spc1357_fuse_clk2), // Templated
.efc_spc_ifuse_ashift (efc_spc1_ifuse_ashift), // Templated
.efc_spc_ifuse_dshift (efc_spc1_ifuse_dshift), // Templated
.efc_spc_ifuse_data (efc_spc1357_fuse_data), // Templated
.efc_spc_dfuse_ashift (efc_spc1_dfuse_ashift), // Templated
.efc_spc_dfuse_dshift (efc_spc1_dfuse_dshift), // Templated
.efc_spc_dfuse_data (efc_spc1357_fuse_data), // Templated
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_short_chain (ctu_tst_short_chain),
.global_shift_enable (global_shift_enable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.spc_scanin0 (par_scan_head[11]), // Templated
.spc_scanin1 (par_scan_head[12]), // Templated
.cluster_cken (rpt_spc1_cmp_cken), // Templated
.gclk (cmp_gclk_c1_r[7]), // Templated
.cmp_grst_l (rpt_cmp_grst_l_c5), // Templated
.cmp_arst_l (cmp_arst_l),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.adbginit_l (cmp_adbginit_l), // Templated
.gdbginit_l (rpt_cmp_gdbginit_l_c5)); // Templated
`endif
//
/* sparc AUTO_TEMPLATE (
.const_cpuid (4'h@),
.const_maskid (ctu_spc_const_maskid[]),
.gclk (cmp_gclk_c1_r[0]),
.adbginit_l (cmp_adbginit_l),
.cmp_grst_l (rpt_cmp_grst_l_c0),
.gdbginit_l (rpt_cmp_gdbginit_l_c0),
.cluster_cken (rpt_spc@_cmp_cken),
.spc_scanin0 (par_scan_head[1]),
.spc_scanout0 (par_scan_tail[1]),
.spc_scanin1 (par_scan_head[2]),
.spc_scanout1 (par_scan_tail[2]),
.ctu_sscan_snap (ctu_global_snap),
.ctu_sscan_tid (ctu_spc_sscan_tid[]),
.ctu_sscan_se (ctu_spc@_sscan_se),
.spc_sscan_so (spc@_ctu_sscan_out),
.ctu_tck (ctu_spc@_tck),
.ctu_tst_mbist_enable (ctu_spc@_mbisten_buf2),
.tst_ctu_mbist_done (spc@_ctu_mbistdone),
.tst_ctu_mbist_fail (spc@_ctu_mbisterr),
.efc_spc_fuse_clk1 (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_clk1),
.efc_spc_fuse_clk2 (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_clk2),
.efc_spc_ifuse_data (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_data),
.efc_spc_dfuse_data (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_data),
.pcx_spc_grant_px (pcx_spc@_grant_px_buf1[4:0]),
.cpx_spc_data_rdy_cx2 (cpx_spc@_data_rdy_cx2_buf1),
.cpx_spc_data_cx2 (cpx_spc@_data_cx2_buf1[]),
.\(.*\)spc\(.*\) (\1spc@\2[]),
); */
//
`ifdef RTL_SPARC2
sparc sparc2
(/*AUTOINST*/
// Outputs
.spc_pcx_req_pq (spc2_pcx_req_pq[4:0]), // Templated
.spc_pcx_atom_pq (spc2_pcx_atom_pq), // Templated
.spc_pcx_data_pa (spc2_pcx_data_pa[`PCX_WIDTH-1:0]), // Templated
.spc_sscan_so (spc2_ctu_sscan_out), // Templated
.spc_scanout0 (par_scan_tail[1]), // Templated
.spc_scanout1 (par_scan_tail[2]), // Templated
.tst_ctu_mbist_done (spc2_ctu_mbistdone), // Templated
.tst_ctu_mbist_fail (spc2_ctu_mbisterr), // Templated
.spc_efc_ifuse_data (spc2_efc_ifuse_data), // Templated
.spc_efc_dfuse_data (spc2_efc_dfuse_data), // Templated
// Inputs
.pcx_spc_grant_px (pcx_spc2_grant_px_buf1[4:0]), // Templated
.cpx_spc_data_rdy_cx2 (cpx_spc2_data_rdy_cx2_buf1), // Templated
.cpx_spc_data_cx2 (cpx_spc2_data_cx2_buf1[`CPX_WIDTH-1:0]), // Templated
.const_cpuid (4'h2), // Templated
.const_maskid (ctu_spc_const_maskid[7:0]), // Templated
.ctu_tck (ctu_spc2_tck), // Templated
.ctu_sscan_se (ctu_spc2_sscan_se), // Templated
.ctu_sscan_snap (ctu_global_snap), // Templated
.ctu_sscan_tid (ctu_spc_sscan_tid[3:0]), // Templated
.ctu_tst_mbist_enable (ctu_spc2_mbisten_buf2), // Templated
.efc_spc_fuse_clk1 (efc_spc0246_fuse_clk1), // Templated
.efc_spc_fuse_clk2 (efc_spc0246_fuse_clk2), // Templated
.efc_spc_ifuse_ashift (efc_spc2_ifuse_ashift), // Templated
.efc_spc_ifuse_dshift (efc_spc2_ifuse_dshift), // Templated
.efc_spc_ifuse_data (efc_spc0246_fuse_data), // Templated
.efc_spc_dfuse_ashift (efc_spc2_dfuse_ashift), // Templated
.efc_spc_dfuse_dshift (efc_spc2_dfuse_dshift), // Templated
.efc_spc_dfuse_data (efc_spc0246_fuse_data), // Templated
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_short_chain (ctu_tst_short_chain),
.global_shift_enable (global_shift_enable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.spc_scanin0 (par_scan_head[1]), // Templated
.spc_scanin1 (par_scan_head[2]), // Templated
.cluster_cken (rpt_spc2_cmp_cken), // Templated
.gclk (cmp_gclk_c1_r[0]), // Templated
.cmp_grst_l (rpt_cmp_grst_l_c0), // Templated
.cmp_arst_l (cmp_arst_l),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.adbginit_l (cmp_adbginit_l), // Templated
.gdbginit_l (rpt_cmp_gdbginit_l_c0)); // Templated
`endif
//
/* sparc AUTO_TEMPLATE (
.const_cpuid (4'h@),
.const_maskid (ctu_spc_const_maskid[]),
.gclk (cmp_gclk_c1_r[7]),
.adbginit_l (cmp_adbginit_l),
.cmp_grst_l (rpt_cmp_grst_l_c5),
.gdbginit_l (rpt_cmp_gdbginit_l_c5),
.cluster_cken (rpt_spc@_cmp_cken),
.spc_scanin0 (par_scan_head[13]),
.spc_scanout0 (par_scan_tail[13]),
.spc_scanin1 (par_scan_head[14]),
.spc_scanout1 (par_scan_tail[14]),
.ctu_sscan_snap (ctu_global_snap),
.ctu_sscan_tid (ctu_spc_sscan_tid[]),
.ctu_sscan_se (ctu_spc@_sscan_se),
.spc_sscan_so (spc@_ctu_sscan_out),
.ctu_tck (ctu_spc@_tck),
.ctu_tst_mbist_enable (ctu_spc@_mbisten_buf2),
.tst_ctu_mbist_done (spc@_ctu_mbistdone),
.tst_ctu_mbist_fail (spc@_ctu_mbisterr),
.efc_spc_fuse_clk1 (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_clk1),
.efc_spc_fuse_clk2 (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_clk2),
.efc_spc_ifuse_data (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_data),
.efc_spc_dfuse_data (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_data),
.pcx_spc_grant_px (pcx_spc@_grant_px_buf1[4:0]),
.cpx_spc_data_rdy_cx2 (cpx_spc@_data_rdy_cx2_buf1),
.cpx_spc_data_cx2 (cpx_spc@_data_cx2_buf1[]),
.\(.*\)spc\(.*\) (\1spc@\2[]),
); */
//
`ifdef RTL_SPARC3
sparc sparc3
(/*AUTOINST*/
// Outputs
.spc_pcx_req_pq (spc3_pcx_req_pq[4:0]), // Templated
.spc_pcx_atom_pq (spc3_pcx_atom_pq), // Templated
.spc_pcx_data_pa (spc3_pcx_data_pa[`PCX_WIDTH-1:0]), // Templated
.spc_sscan_so (spc3_ctu_sscan_out), // Templated
.spc_scanout0 (par_scan_tail[13]), // Templated
.spc_scanout1 (par_scan_tail[14]), // Templated
.tst_ctu_mbist_done (spc3_ctu_mbistdone), // Templated
.tst_ctu_mbist_fail (spc3_ctu_mbisterr), // Templated
.spc_efc_ifuse_data (spc3_efc_ifuse_data), // Templated
.spc_efc_dfuse_data (spc3_efc_dfuse_data), // Templated
// Inputs
.pcx_spc_grant_px (pcx_spc3_grant_px_buf1[4:0]), // Templated
.cpx_spc_data_rdy_cx2 (cpx_spc3_data_rdy_cx2_buf1), // Templated
.cpx_spc_data_cx2 (cpx_spc3_data_cx2_buf1[`CPX_WIDTH-1:0]), // Templated
.const_cpuid (4'h3), // Templated
.const_maskid (ctu_spc_const_maskid[7:0]), // Templated
.ctu_tck (ctu_spc3_tck), // Templated
.ctu_sscan_se (ctu_spc3_sscan_se), // Templated
.ctu_sscan_snap (ctu_global_snap), // Templated
.ctu_sscan_tid (ctu_spc_sscan_tid[3:0]), // Templated
.ctu_tst_mbist_enable (ctu_spc3_mbisten_buf2), // Templated
.efc_spc_fuse_clk1 (efc_spc1357_fuse_clk1), // Templated
.efc_spc_fuse_clk2 (efc_spc1357_fuse_clk2), // Templated
.efc_spc_ifuse_ashift (efc_spc3_ifuse_ashift), // Templated
.efc_spc_ifuse_dshift (efc_spc3_ifuse_dshift), // Templated
.efc_spc_ifuse_data (efc_spc1357_fuse_data), // Templated
.efc_spc_dfuse_ashift (efc_spc3_dfuse_ashift), // Templated
.efc_spc_dfuse_dshift (efc_spc3_dfuse_dshift), // Templated
.efc_spc_dfuse_data (efc_spc1357_fuse_data), // Templated
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_short_chain (ctu_tst_short_chain),
.global_shift_enable (global_shift_enable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.spc_scanin0 (par_scan_head[13]), // Templated
.spc_scanin1 (par_scan_head[14]), // Templated
.cluster_cken (rpt_spc3_cmp_cken), // Templated
.gclk (cmp_gclk_c1_r[7]), // Templated
.cmp_grst_l (rpt_cmp_grst_l_c5), // Templated
.cmp_arst_l (cmp_arst_l),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.adbginit_l (cmp_adbginit_l), // Templated
.gdbginit_l (rpt_cmp_gdbginit_l_c5)); // Templated
`endif
//
/* sparc AUTO_TEMPLATE (
.const_cpuid (4'h@),
.const_maskid (ctu_spc_const_maskid[]),
.gclk (cmp_gclk_c2_r[0]),
.adbginit_l (cmp_adbginit_l),
.cmp_grst_l (rpt_cmp_grst_l_c2),
.gdbginit_l (rpt_cmp_gdbginit_l_c2),
.cluster_cken (rpt_spc@_cmp_cken),
.spc_scanin0 (par_scan_head[26]),
.spc_scanout0 (par_scan_tail[26]),
.spc_scanin1 (par_scan_head[27]),
.spc_scanout1 (par_scan_tail[27]),
.ctu_sscan_snap (ctu_global_snap),
.ctu_sscan_tid (ctu_spc_sscan_tid[]),
.ctu_sscan_se (ctu_spc@_sscan_se),
.spc_sscan_so (spc@_ctu_sscan_out),
.ctu_tck (ctu_spc@_tck),
.ctu_tst_mbist_enable (ctu_spc@_mbisten_buf2),
.tst_ctu_mbist_done (spc@_ctu_mbistdone),
.tst_ctu_mbist_fail (spc@_ctu_mbisterr),
.efc_spc_fuse_clk1 (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_clk1),
.efc_spc_fuse_clk2 (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_clk2),
.efc_spc_ifuse_data (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_data),
.efc_spc_dfuse_data (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_data),
.pcx_spc_grant_px (pcx_spc@_grant_px_buf1[4:0]),
.cpx_spc_data_rdy_cx2 (cpx_spc@_data_rdy_cx2_buf1),
.cpx_spc_data_cx2 (cpx_spc@_data_cx2_buf1[]),
.\(.*\)spc\(.*\) (\1spc@\2[]),
); */
//
`ifdef RTL_SPARC4
sparc sparc4
(/*AUTOINST*/
// Outputs
.spc_pcx_req_pq (spc4_pcx_req_pq[4:0]), // Templated
.spc_pcx_atom_pq (spc4_pcx_atom_pq), // Templated
.spc_pcx_data_pa (spc4_pcx_data_pa[`PCX_WIDTH-1:0]), // Templated
.spc_sscan_so (spc4_ctu_sscan_out), // Templated
.spc_scanout0 (par_scan_tail[26]), // Templated
.spc_scanout1 (par_scan_tail[27]), // Templated
.tst_ctu_mbist_done (spc4_ctu_mbistdone), // Templated
.tst_ctu_mbist_fail (spc4_ctu_mbisterr), // Templated
.spc_efc_ifuse_data (spc4_efc_ifuse_data), // Templated
.spc_efc_dfuse_data (spc4_efc_dfuse_data), // Templated
// Inputs
.pcx_spc_grant_px (pcx_spc4_grant_px_buf1[4:0]), // Templated
.cpx_spc_data_rdy_cx2 (cpx_spc4_data_rdy_cx2_buf1), // Templated
.cpx_spc_data_cx2 (cpx_spc4_data_cx2_buf1[`CPX_WIDTH-1:0]), // Templated
.const_cpuid (4'h4), // Templated
.const_maskid (ctu_spc_const_maskid[7:0]), // Templated
.ctu_tck (ctu_spc4_tck), // Templated
.ctu_sscan_se (ctu_spc4_sscan_se), // Templated
.ctu_sscan_snap (ctu_global_snap), // Templated
.ctu_sscan_tid (ctu_spc_sscan_tid[3:0]), // Templated
.ctu_tst_mbist_enable (ctu_spc4_mbisten_buf2), // Templated
.efc_spc_fuse_clk1 (efc_spc0246_fuse_clk1), // Templated
.efc_spc_fuse_clk2 (efc_spc0246_fuse_clk2), // Templated
.efc_spc_ifuse_ashift (efc_spc4_ifuse_ashift), // Templated
.efc_spc_ifuse_dshift (efc_spc4_ifuse_dshift), // Templated
.efc_spc_ifuse_data (efc_spc0246_fuse_data), // Templated
.efc_spc_dfuse_ashift (efc_spc4_dfuse_ashift), // Templated
.efc_spc_dfuse_dshift (efc_spc4_dfuse_dshift), // Templated
.efc_spc_dfuse_data (efc_spc0246_fuse_data), // Templated
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_short_chain (ctu_tst_short_chain),
.global_shift_enable (global_shift_enable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.spc_scanin0 (par_scan_head[26]), // Templated
.spc_scanin1 (par_scan_head[27]), // Templated
.cluster_cken (rpt_spc4_cmp_cken), // Templated
.gclk (cmp_gclk_c2_r[0]), // Templated
.cmp_grst_l (rpt_cmp_grst_l_c2), // Templated
.cmp_arst_l (cmp_arst_l),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.adbginit_l (cmp_adbginit_l), // Templated
.gdbginit_l (rpt_cmp_gdbginit_l_c2)); // Templated
`endif
//
/* sparc AUTO_TEMPLATE (
.const_cpuid (4'h@),
.const_maskid (ctu_spc_const_maskid[]),
.gclk (cmp_gclk_c2_r[7]),
.adbginit_l (cmp_adbginit_l),
.cmp_grst_l (rpt_cmp_grst_l_c7),
.gdbginit_l (rpt_cmp_gdbginit_l_c7),
.cluster_cken (rpt_spc@_cmp_cken),
.spc_scanin0 (par_scan_head[15]),
.spc_scanout0 (par_scan_tail[15]),
.spc_scanin1 (par_scan_head[16]),
.spc_scanout1 (par_scan_tail[16]),
.ctu_sscan_snap (ctu_global_snap),
.ctu_sscan_tid (ctu_spc_sscan_tid[]),
.ctu_sscan_se (ctu_spc@_sscan_se),
.spc_sscan_so (spc@_ctu_sscan_out),
.ctu_tck (ctu_spc@_tck),
.ctu_tst_mbist_enable (ctu_spc@_mbisten_buf2),
.tst_ctu_mbist_done (spc@_ctu_mbistdone),
.tst_ctu_mbist_fail (spc@_ctu_mbisterr),
.efc_spc_fuse_clk1 (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_clk1),
.efc_spc_fuse_clk2 (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_clk2),
.efc_spc_ifuse_data (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_data),
.efc_spc_dfuse_data (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_data),
.pcx_spc_grant_px (pcx_spc@_grant_px_buf1[4:0]),
.cpx_spc_data_rdy_cx2 (cpx_spc@_data_rdy_cx2_buf1),
.cpx_spc_data_cx2 (cpx_spc@_data_cx2_buf1[]),
.\(.*\)spc\(.*\) (\1spc@\2[]),
); */
//
`ifdef RTL_SPARC5
sparc sparc5
(/*AUTOINST*/
// Outputs
.spc_pcx_req_pq (spc5_pcx_req_pq[4:0]), // Templated
.spc_pcx_atom_pq (spc5_pcx_atom_pq), // Templated
.spc_pcx_data_pa (spc5_pcx_data_pa[`PCX_WIDTH-1:0]), // Templated
.spc_sscan_so (spc5_ctu_sscan_out), // Templated
.spc_scanout0 (par_scan_tail[15]), // Templated
.spc_scanout1 (par_scan_tail[16]), // Templated
.tst_ctu_mbist_done (spc5_ctu_mbistdone), // Templated
.tst_ctu_mbist_fail (spc5_ctu_mbisterr), // Templated
.spc_efc_ifuse_data (spc5_efc_ifuse_data), // Templated
.spc_efc_dfuse_data (spc5_efc_dfuse_data), // Templated
// Inputs
.pcx_spc_grant_px (pcx_spc5_grant_px_buf1[4:0]), // Templated
.cpx_spc_data_rdy_cx2 (cpx_spc5_data_rdy_cx2_buf1), // Templated
.cpx_spc_data_cx2 (cpx_spc5_data_cx2_buf1[`CPX_WIDTH-1:0]), // Templated
.const_cpuid (4'h5), // Templated
.const_maskid (ctu_spc_const_maskid[7:0]), // Templated
.ctu_tck (ctu_spc5_tck), // Templated
.ctu_sscan_se (ctu_spc5_sscan_se), // Templated
.ctu_sscan_snap (ctu_global_snap), // Templated
.ctu_sscan_tid (ctu_spc_sscan_tid[3:0]), // Templated
.ctu_tst_mbist_enable (ctu_spc5_mbisten_buf2), // Templated
.efc_spc_fuse_clk1 (efc_spc1357_fuse_clk1), // Templated
.efc_spc_fuse_clk2 (efc_spc1357_fuse_clk2), // Templated
.efc_spc_ifuse_ashift (efc_spc5_ifuse_ashift), // Templated
.efc_spc_ifuse_dshift (efc_spc5_ifuse_dshift), // Templated
.efc_spc_ifuse_data (efc_spc1357_fuse_data), // Templated
.efc_spc_dfuse_ashift (efc_spc5_dfuse_ashift), // Templated
.efc_spc_dfuse_dshift (efc_spc5_dfuse_dshift), // Templated
.efc_spc_dfuse_data (efc_spc1357_fuse_data), // Templated
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_short_chain (ctu_tst_short_chain),
.global_shift_enable (global_shift_enable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.spc_scanin0 (par_scan_head[15]), // Templated
.spc_scanin1 (par_scan_head[16]), // Templated
.cluster_cken (rpt_spc5_cmp_cken), // Templated
.gclk (cmp_gclk_c2_r[7]), // Templated
.cmp_grst_l (rpt_cmp_grst_l_c7), // Templated
.cmp_arst_l (cmp_arst_l),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.adbginit_l (cmp_adbginit_l), // Templated
.gdbginit_l (rpt_cmp_gdbginit_l_c7)); // Templated
`endif
//
/* sparc AUTO_TEMPLATE (
.const_cpuid (4'h@),
.const_maskid (ctu_spc_const_maskid[]),
.gclk (cmp_gclk_c2_r[0]),
.adbginit_l (cmp_adbginit_l),
.cmp_grst_l (rpt_cmp_grst_l_c2),
.gdbginit_l (rpt_cmp_gdbginit_l_c2),
.cluster_cken (rpt_spc@_cmp_cken),
.spc_scanin0 (par_scan_head[28]),
.spc_scanout0 (par_scan_tail[28]),
.spc_scanin1 (par_scan_head[29]),
.spc_scanout1 (par_scan_tail[29]),
.ctu_sscan_snap (ctu_global_snap),
.ctu_sscan_tid (ctu_spc_sscan_tid[]),
.ctu_sscan_se (ctu_spc@_sscan_se),
.spc_sscan_so (spc@_ctu_sscan_out),
.ctu_tck (ctu_spc@_tck),
.ctu_tst_mbist_enable (ctu_spc@_mbisten_buf2),
.tst_ctu_mbist_done (spc@_ctu_mbistdone),
.tst_ctu_mbist_fail (spc@_ctu_mbisterr),
.efc_spc_fuse_clk1 (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_clk1),
.efc_spc_fuse_clk2 (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_clk2),
.efc_spc_ifuse_data (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_data),
.efc_spc_dfuse_data (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_data),
.pcx_spc_grant_px (pcx_spc@_grant_px_buf1[4:0]),
.cpx_spc_data_rdy_cx2 (cpx_spc@_data_rdy_cx2_buf1),
.cpx_spc_data_cx2 (cpx_spc@_data_cx2_buf1[]),
.\(.*\)spc\(.*\) (\1spc@\2[]),
); */
//
`ifdef RTL_SPARC6
sparc sparc6
(/*AUTOINST*/
// Outputs
.spc_pcx_req_pq (spc6_pcx_req_pq[4:0]), // Templated
.spc_pcx_atom_pq (spc6_pcx_atom_pq), // Templated
.spc_pcx_data_pa (spc6_pcx_data_pa[`PCX_WIDTH-1:0]), // Templated
.spc_sscan_so (spc6_ctu_sscan_out), // Templated
.spc_scanout0 (par_scan_tail[28]), // Templated
.spc_scanout1 (par_scan_tail[29]), // Templated
.tst_ctu_mbist_done (spc6_ctu_mbistdone), // Templated
.tst_ctu_mbist_fail (spc6_ctu_mbisterr), // Templated
.spc_efc_ifuse_data (spc6_efc_ifuse_data), // Templated
.spc_efc_dfuse_data (spc6_efc_dfuse_data), // Templated
// Inputs
.pcx_spc_grant_px (pcx_spc6_grant_px_buf1[4:0]), // Templated
.cpx_spc_data_rdy_cx2 (cpx_spc6_data_rdy_cx2_buf1), // Templated
.cpx_spc_data_cx2 (cpx_spc6_data_cx2_buf1[`CPX_WIDTH-1:0]), // Templated
.const_cpuid (4'h6), // Templated
.const_maskid (ctu_spc_const_maskid[7:0]), // Templated
.ctu_tck (ctu_spc6_tck), // Templated
.ctu_sscan_se (ctu_spc6_sscan_se), // Templated
.ctu_sscan_snap (ctu_global_snap), // Templated
.ctu_sscan_tid (ctu_spc_sscan_tid[3:0]), // Templated
.ctu_tst_mbist_enable (ctu_spc6_mbisten_buf2), // Templated
.efc_spc_fuse_clk1 (efc_spc0246_fuse_clk1), // Templated
.efc_spc_fuse_clk2 (efc_spc0246_fuse_clk2), // Templated
.efc_spc_ifuse_ashift (efc_spc6_ifuse_ashift), // Templated
.efc_spc_ifuse_dshift (efc_spc6_ifuse_dshift), // Templated
.efc_spc_ifuse_data (efc_spc0246_fuse_data), // Templated
.efc_spc_dfuse_ashift (efc_spc6_dfuse_ashift), // Templated
.efc_spc_dfuse_dshift (efc_spc6_dfuse_dshift), // Templated
.efc_spc_dfuse_data (efc_spc0246_fuse_data), // Templated
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_short_chain (ctu_tst_short_chain),
.global_shift_enable (global_shift_enable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.spc_scanin0 (par_scan_head[28]), // Templated
.spc_scanin1 (par_scan_head[29]), // Templated
.cluster_cken (rpt_spc6_cmp_cken), // Templated
.gclk (cmp_gclk_c2_r[0]), // Templated
.cmp_grst_l (rpt_cmp_grst_l_c2), // Templated
.cmp_arst_l (cmp_arst_l),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.adbginit_l (cmp_adbginit_l), // Templated
.gdbginit_l (rpt_cmp_gdbginit_l_c2)); // Templated
`endif
//
/* sparc AUTO_TEMPLATE (
.const_cpuid (4'h@),
.const_maskid (ctu_spc_const_maskid[]),
.gclk (cmp_gclk_c2_r[7]),
.adbginit_l (cmp_adbginit_l),
.cmp_grst_l (rpt_cmp_grst_l_c7),
.gdbginit_l (rpt_cmp_gdbginit_l_c7),
.cluster_cken (rpt_spc@_cmp_cken),
.spc_scanin0 (par_scan_head[18]),
.spc_scanout0 (par_scan_tail[18]),
.spc_scanin1 (par_scan_head[19]),
.spc_scanout1 (par_scan_tail[19]),
.ctu_sscan_snap (ctu_global_snap),
.ctu_sscan_tid (ctu_spc_sscan_tid[]),
.ctu_sscan_se (ctu_spc@_sscan_se),
.spc_sscan_so (spc@_ctu_sscan_out),
.ctu_tck (ctu_spc@_tck),
.ctu_tst_mbist_enable (ctu_spc@_mbisten_buf2),
.tst_ctu_mbist_done (spc@_ctu_mbistdone),
.tst_ctu_mbist_fail (spc@_ctu_mbisterr),
.efc_spc_fuse_clk1 (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_clk1),
.efc_spc_fuse_clk2 (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_clk2),
.efc_spc_ifuse_data (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_data),
.efc_spc_dfuse_data (efc_spc@"(% @ 2)"@"(+ (% @ 2) 2)"@"(+ (% @ 2) 4)"@"(+ (% @ 2) 6)"_fuse_data),
.pcx_spc_grant_px (pcx_spc@_grant_px_buf1[4:0]),
.cpx_spc_data_rdy_cx2 (cpx_spc@_data_rdy_cx2_buf1),
.cpx_spc_data_cx2 (cpx_spc@_data_cx2_buf1[]),
.\(.*\)spc\(.*\) (\1spc@\2[]),
); */
//
`ifdef RTL_SPARC7
sparc sparc7
(/*AUTOINST*/
// Outputs
.spc_pcx_req_pq (spc7_pcx_req_pq[4:0]), // Templated
.spc_pcx_atom_pq (spc7_pcx_atom_pq), // Templated
.spc_pcx_data_pa (spc7_pcx_data_pa[`PCX_WIDTH-1:0]), // Templated
.spc_sscan_so (spc7_ctu_sscan_out), // Templated
.spc_scanout0 (par_scan_tail[18]), // Templated
.spc_scanout1 (par_scan_tail[19]), // Templated
.tst_ctu_mbist_done (spc7_ctu_mbistdone), // Templated
.tst_ctu_mbist_fail (spc7_ctu_mbisterr), // Templated
.spc_efc_ifuse_data (spc7_efc_ifuse_data), // Templated
.spc_efc_dfuse_data (spc7_efc_dfuse_data), // Templated
// Inputs
.pcx_spc_grant_px (pcx_spc7_grant_px_buf1[4:0]), // Templated
.cpx_spc_data_rdy_cx2 (cpx_spc7_data_rdy_cx2_buf1), // Templated
.cpx_spc_data_cx2 (cpx_spc7_data_cx2_buf1[`CPX_WIDTH-1:0]), // Templated
.const_cpuid (4'h7), // Templated
.const_maskid (ctu_spc_const_maskid[7:0]), // Templated
.ctu_tck (ctu_spc7_tck), // Templated
.ctu_sscan_se (ctu_spc7_sscan_se), // Templated
.ctu_sscan_snap (ctu_global_snap), // Templated
.ctu_sscan_tid (ctu_spc_sscan_tid[3:0]), // Templated
.ctu_tst_mbist_enable (ctu_spc7_mbisten_buf2), // Templated
.efc_spc_fuse_clk1 (efc_spc1357_fuse_clk1), // Templated
.efc_spc_fuse_clk2 (efc_spc1357_fuse_clk2), // Templated
.efc_spc_ifuse_ashift (efc_spc7_ifuse_ashift), // Templated
.efc_spc_ifuse_dshift (efc_spc7_ifuse_dshift), // Templated
.efc_spc_ifuse_data (efc_spc1357_fuse_data), // Templated
.efc_spc_dfuse_ashift (efc_spc7_dfuse_ashift), // Templated
.efc_spc_dfuse_dshift (efc_spc7_dfuse_dshift), // Templated
.efc_spc_dfuse_data (efc_spc1357_fuse_data), // Templated
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_short_chain (ctu_tst_short_chain),
.global_shift_enable (global_shift_enable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.spc_scanin0 (par_scan_head[18]), // Templated
.spc_scanin1 (par_scan_head[19]), // Templated
.cluster_cken (rpt_spc7_cmp_cken), // Templated
.gclk (cmp_gclk_c2_r[7]), // Templated
.cmp_grst_l (rpt_cmp_grst_l_c7), // Templated
.cmp_arst_l (cmp_arst_l),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.adbginit_l (cmp_adbginit_l), // Templated
.gdbginit_l (rpt_cmp_gdbginit_l_c7)); // Templated
`endif
//
/* fpu AUTO_TEMPLATE (
.se (global_shift_enable),
.si (rdram2_fpu_so),
.so (fpu_rdram3_so),
.gclk (cmp_gclk_c2_r[4]),
.arst_l (cmp_arst_l),
.grst_l (rpt_cmp_grst_l_c6),
.cluster_cken (rpt_fpu_cmp_cken),
.pcx_fpio_\(.*\) (pcx_fp_\1[]),
); */
//
`ifdef RTL_FPU
fpu fpu
(/*AUTOINST*/
// Outputs
.fp_cpx_req_cq (fp_cpx_req_cq[7:0]),
.fp_cpx_data_ca (fp_cpx_data_ca[144:0]),
.so (fpu_rdram3_so), // Templated
// Inputs
.pcx_fpio_data_rdy_px2 (pcx_fp_data_rdy_px2), // Templated
.pcx_fpio_data_px2 (pcx_fp_data_px2[123:0]), // Templated
.arst_l (cmp_arst_l), // Templated
.grst_l (rpt_cmp_grst_l_c6), // Templated
.gclk (cmp_gclk_c2_r[4]), // Templated
.cluster_cken (rpt_fpu_cmp_cken), // Templated
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.global_shift_enable (global_shift_enable),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_short_chain (ctu_tst_short_chain),
.si (rdram2_fpu_so)); // Templated
`endif
//
/* ccx AUTO_TEMPLATE (
.ccx_scanin0 (par_scan_head[24]),
.ccx_scanout0 (par_scan_tail[24]),
.ccx_scanin1 (par_scan_head[25]),
.ccx_scanout1 (par_scan_tail[25]),
.gclk ({cmp_gclk_c2_r[3],cmp_gclk_c2_r[3]}),
.adbginit_l (cmp_adbginit_l),
.cmp_grst_l (rpt_cmp_grst_l_c3),
.gdbginit_l (rpt_cmp_gdbginit_l_c3),
.clk_ccx_cken (rpt_ccx_cmp_cken),
.spc\(.*\)_pcx\(.*\) (spc\1_pcx\2_buf1[]),
.sctag\(.*\)_cpx\(.*\) (sctag\1_cpx\2_buf[]),
.sctag\(.*\)_pcx\(.*\) (sctag\1_pcx\2_buf[]),
.rclk (ccx_rclk),
.iob_cpx_\(.*\) (iob_cpx_\1_buf[]),
.iob_pcx_\(.*\) (iob_pcx_\1_buf[]),
); */
//
`ifdef RTL_CCX
ccx ccx
(/*AUTOINST*/
// Outputs
.ccx_scanout0 (par_scan_tail[24]), // Templated
.ccx_scanout1 (par_scan_tail[25]), // Templated
.cpx_iob_grant_cx2 (cpx_iob_grant_cx2[7:0]),
.cpx_sctag0_grant_cx (cpx_sctag0_grant_cx[7:0]),
.cpx_sctag1_grant_cx (cpx_sctag1_grant_cx[7:0]),
.cpx_sctag2_grant_cx (cpx_sctag2_grant_cx[7:0]),
.cpx_sctag3_grant_cx (cpx_sctag3_grant_cx[7:0]),
.cpx_spc0_data_cx2 (cpx_spc0_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc0_data_rdy_cx2 (cpx_spc0_data_rdy_cx2),
.cpx_spc1_data_cx2 (cpx_spc1_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc1_data_rdy_cx2 (cpx_spc1_data_rdy_cx2),
.cpx_spc2_data_cx2 (cpx_spc2_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc2_data_rdy_cx2 (cpx_spc2_data_rdy_cx2),
.cpx_spc3_data_cx2 (cpx_spc3_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc3_data_rdy_cx2 (cpx_spc3_data_rdy_cx2),
.cpx_spc4_data_cx2 (cpx_spc4_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc4_data_rdy_cx2 (cpx_spc4_data_rdy_cx2),
.cpx_spc5_data_cx2 (cpx_spc5_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc5_data_rdy_cx2 (cpx_spc5_data_rdy_cx2),
.cpx_spc6_data_cx2 (cpx_spc6_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc6_data_rdy_cx2 (cpx_spc6_data_rdy_cx2),
.cpx_spc7_data_cx2 (cpx_spc7_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc7_data_rdy_cx2 (cpx_spc7_data_rdy_cx2),
.pcx_fp_data_px2 (pcx_fp_data_px2[`PCX_WIDTH-1:0]),
.pcx_fp_data_rdy_px2 (pcx_fp_data_rdy_px2),
.pcx_iob_data_px2 (pcx_iob_data_px2[`PCX_WIDTH-1:0]),
.pcx_iob_data_rdy_px2 (pcx_iob_data_rdy_px2),
.pcx_sctag0_atm_px1 (pcx_sctag0_atm_px1),
.pcx_sctag0_data_px2 (pcx_sctag0_data_px2[`PCX_WIDTH-1:0]),
.pcx_sctag0_data_rdy_px1 (pcx_sctag0_data_rdy_px1),
.pcx_sctag1_atm_px1 (pcx_sctag1_atm_px1),
.pcx_sctag1_data_px2 (pcx_sctag1_data_px2[`PCX_WIDTH-1:0]),
.pcx_sctag1_data_rdy_px1 (pcx_sctag1_data_rdy_px1),
.pcx_sctag2_atm_px1 (pcx_sctag2_atm_px1),
.pcx_sctag2_data_px2 (pcx_sctag2_data_px2[`PCX_WIDTH-1:0]),
.pcx_sctag2_data_rdy_px1 (pcx_sctag2_data_rdy_px1),
.pcx_sctag3_atm_px1 (pcx_sctag3_atm_px1),
.pcx_sctag3_data_px2 (pcx_sctag3_data_px2[`PCX_WIDTH-1:0]),
.pcx_sctag3_data_rdy_px1 (pcx_sctag3_data_rdy_px1),
.pcx_spc0_grant_px (pcx_spc0_grant_px[4:0]),
.pcx_spc1_grant_px (pcx_spc1_grant_px[4:0]),
.pcx_spc2_grant_px (pcx_spc2_grant_px[4:0]),
.pcx_spc3_grant_px (pcx_spc3_grant_px[4:0]),
.pcx_spc4_grant_px (pcx_spc4_grant_px[4:0]),
.pcx_spc5_grant_px (pcx_spc5_grant_px[4:0]),
.pcx_spc6_grant_px (pcx_spc6_grant_px[4:0]),
.pcx_spc7_grant_px (pcx_spc7_grant_px[4:0]),
.rclk (ccx_rclk), // Templated
// Inputs
.adbginit_l (cmp_adbginit_l), // Templated
.ccx_scanin0 (par_scan_head[24]), // Templated
.ccx_scanin1 (par_scan_head[25]), // Templated
.clk_ccx_cken (rpt_ccx_cmp_cken), // Templated
.cmp_arst_l (cmp_arst_l),
.cmp_grst_l (rpt_cmp_grst_l_c3), // Templated
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_short_chain (ctu_tst_short_chain),
.fp_cpx_data_ca (fp_cpx_data_ca[`CPX_WIDTH-1:0]),
.fp_cpx_req_cq (fp_cpx_req_cq[7:0]),
.gclk ({cmp_gclk_c2_r[3],cmp_gclk_c2_r[3]}), // Templated
.gdbginit_l (rpt_cmp_gdbginit_l_c3), // Templated
.global_shift_enable (global_shift_enable),
.iob_cpx_data_ca (iob_cpx_data_ca_buf[`CPX_WIDTH-1:0]), // Templated
.iob_cpx_req_cq (iob_cpx_req_cq_buf[7:0]), // Templated
.sctag0_cpx_atom_cq (sctag0_cpx_atom_cq_buf), // Templated
.sctag0_cpx_data_ca (sctag0_cpx_data_ca_buf[`CPX_WIDTH-1:0]), // Templated
.sctag0_cpx_req_cq (sctag0_cpx_req_cq_buf[7:0]), // Templated
.sctag0_pcx_stall_pq (sctag0_pcx_stall_pq_buf), // Templated
.sctag1_cpx_atom_cq (sctag1_cpx_atom_cq_buf), // Templated
.sctag1_cpx_data_ca (sctag1_cpx_data_ca_buf[`CPX_WIDTH-1:0]), // Templated
.sctag1_cpx_req_cq (sctag1_cpx_req_cq_buf[7:0]), // Templated
.sctag1_pcx_stall_pq (sctag1_pcx_stall_pq_buf), // Templated
.sctag2_cpx_atom_cq (sctag2_cpx_atom_cq_buf), // Templated
.sctag2_cpx_data_ca (sctag2_cpx_data_ca_buf[`CPX_WIDTH-1:0]), // Templated
.sctag2_cpx_req_cq (sctag2_cpx_req_cq_buf[7:0]), // Templated
.sctag2_pcx_stall_pq (sctag2_pcx_stall_pq_buf), // Templated
.sctag3_cpx_atom_cq (sctag3_cpx_atom_cq_buf), // Templated
.sctag3_cpx_data_ca (sctag3_cpx_data_ca_buf[`CPX_WIDTH-1:0]), // Templated
.sctag3_cpx_req_cq (sctag3_cpx_req_cq_buf[7:0]), // Templated
.sctag3_pcx_stall_pq (sctag3_pcx_stall_pq_buf), // Templated
.spc0_pcx_atom_pq (spc0_pcx_atom_pq_buf1), // Templated
.spc0_pcx_data_pa (spc0_pcx_data_pa_buf1[`PCX_WIDTH-1:0]), // Templated
.spc0_pcx_req_pq (spc0_pcx_req_pq_buf1[4:0]), // Templated
.spc1_pcx_atom_pq (spc1_pcx_atom_pq_buf1), // Templated
.spc1_pcx_data_pa (spc1_pcx_data_pa_buf1[`PCX_WIDTH-1:0]), // Templated
.spc1_pcx_req_pq (spc1_pcx_req_pq_buf1[4:0]), // Templated
.spc2_pcx_atom_pq (spc2_pcx_atom_pq_buf1), // Templated
.spc2_pcx_data_pa (spc2_pcx_data_pa_buf1[`PCX_WIDTH-1:0]), // Templated
.spc2_pcx_req_pq (spc2_pcx_req_pq_buf1[4:0]), // Templated
.spc3_pcx_atom_pq (spc3_pcx_atom_pq_buf1), // Templated
.spc3_pcx_data_pa (spc3_pcx_data_pa_buf1[`PCX_WIDTH-1:0]), // Templated
.spc3_pcx_req_pq (spc3_pcx_req_pq_buf1[4:0]), // Templated
.spc4_pcx_atom_pq (spc4_pcx_atom_pq_buf1), // Templated
.spc4_pcx_data_pa (spc4_pcx_data_pa_buf1[`PCX_WIDTH-1:0]), // Templated
.spc4_pcx_req_pq (spc4_pcx_req_pq_buf1[4:0]), // Templated
.spc5_pcx_atom_pq (spc5_pcx_atom_pq_buf1), // Templated
.spc5_pcx_data_pa (spc5_pcx_data_pa_buf1[`PCX_WIDTH-1:0]), // Templated
.spc5_pcx_req_pq (spc5_pcx_req_pq_buf1[4:0]), // Templated
.spc6_pcx_atom_pq (spc6_pcx_atom_pq_buf1), // Templated
.spc6_pcx_data_pa (spc6_pcx_data_pa_buf1[`PCX_WIDTH-1:0]), // Templated
.spc6_pcx_req_pq (spc6_pcx_req_pq_buf1[4:0]), // Templated
.spc7_pcx_atom_pq (spc7_pcx_atom_pq_buf1), // Templated
.spc7_pcx_data_pa (spc7_pcx_data_pa_buf1[`PCX_WIDTH-1:0]), // Templated
.spc7_pcx_req_pq (spc7_pcx_req_pq_buf1[4:0]), // Templated
.iob_pcx_stall_pq (iob_pcx_stall_pq_buf)); // Templated
`endif
// sctag <-> ccx repeaters.
sctag_pcx_rptr_0 sctag_pcx_rptr_0 (
.sig ({ unused_sctag_pcx_rptr_0i[36:0], pcx_sctag0_data_px2[123:0], sctag0_pcx_stall_pq, pcx_sctag0_data_rdy_px1, pcx_sctag0_atm_px1 }),
.sig_buf ({ unused_sctag_pcx_rptr_0[36:0], pcx_sctag0_data_px2_buf[123:0], sctag0_pcx_stall_pq_buf, pcx_sctag0_data_rdy_px1_buf, pcx_sctag0_atm_px1_buf }));
sctag_pcx_rptr_1 sctag_pcx_rptr_1 (
.sig ({ unused_sctag_pcx_rptr_1i[36:0], pcx_sctag1_data_px2[123:0], sctag1_pcx_stall_pq, pcx_sctag1_data_rdy_px1, pcx_sctag1_atm_px1 }),
.sig_buf ({ unused_sctag_pcx_rptr_1[36:0], pcx_sctag1_data_px2_buf[123:0], sctag1_pcx_stall_pq_buf, pcx_sctag1_data_rdy_px1_buf, pcx_sctag1_atm_px1_buf }));
sctag_pcx_rptr_2 sctag_pcx_rptr_2 (
.sig ({ unused_sctag_pcx_rptr_2i[36:0], pcx_sctag2_data_px2[123:0], sctag2_pcx_stall_pq, pcx_sctag2_data_rdy_px1, pcx_sctag2_atm_px1 }),
.sig_buf ({ unused_sctag_pcx_rptr_2[36:0], pcx_sctag2_data_px2_buf[123:0], sctag2_pcx_stall_pq_buf, pcx_sctag2_data_rdy_px1_buf, pcx_sctag2_atm_px1_buf }));
sctag_pcx_rptr_3 sctag_pcx_rptr_3 (
.sig ({ unused_sctag_pcx_rptr_3i[36:0], pcx_sctag3_data_px2[123:0], sctag3_pcx_stall_pq, pcx_sctag3_data_rdy_px1, pcx_sctag3_atm_px1 }),
.sig_buf ({ unused_sctag_pcx_rptr_3[36:0], pcx_sctag3_data_px2_buf[123:0], sctag3_pcx_stall_pq_buf, pcx_sctag3_data_rdy_px1_buf, pcx_sctag3_atm_px1_buf }));
sctag_cpx_rptr_0 sctag_cpx_rptr_0 (
.sig ({ unused_sctag_cpx_rptr_0i[1:0], cpx_sctag0_grant_cx[7:0], sctag0_cpx_req_cq[7:0], sctag0_cpx_atom_cq, sctag0_cpx_data_ca[144:0] }),
.sig_buf ({ unused_sctag_cpx_rptr_0[1:0], cpx_sctag0_grant_cx_buf[7:0], sctag0_cpx_req_cq_buf[7:0], sctag0_cpx_atom_cq_buf, sctag0_cpx_data_ca_buf[144:0] }));
sctag_cpx_rptr_1 sctag_cpx_rptr_1 (
.sig ({ unused_sctag_cpx_rptr_1i[1:0], cpx_sctag1_grant_cx[7:0], sctag1_cpx_req_cq[7:0], sctag1_cpx_atom_cq, sctag1_cpx_data_ca[144:0] }),
.sig_buf ({ unused_sctag_cpx_rptr_1[1:0], cpx_sctag1_grant_cx_buf[7:0], sctag1_cpx_req_cq_buf[7:0], sctag1_cpx_atom_cq_buf, sctag1_cpx_data_ca_buf[144:0] }));
sctag_cpx_rptr_2 sctag_cpx_rptr_2 (
.sig ({ unused_sctag_cpx_rptr_2i[1:0], cpx_sctag2_grant_cx[7:0], sctag2_cpx_req_cq[7:0], sctag2_cpx_atom_cq, sctag2_cpx_data_ca[144:0] }),
.sig_buf ({ unused_sctag_cpx_rptr_2[1:0], cpx_sctag2_grant_cx_buf[7:0], sctag2_cpx_req_cq_buf[7:0], sctag2_cpx_atom_cq_buf, sctag2_cpx_data_ca_buf[144:0] }));
sctag_cpx_rptr_3 sctag_cpx_rptr_3 (
.sig ({ unused_sctag_cpx_rptr_3i[1:0], cpx_sctag3_grant_cx[7:0], sctag3_cpx_req_cq[7:0], sctag3_cpx_atom_cq, sctag3_cpx_data_ca[144:0] }),
.sig_buf ({ unused_sctag_cpx_rptr_3[1:0], cpx_sctag3_grant_cx_buf[7:0], sctag3_cpx_req_cq_buf[7:0], sctag3_cpx_atom_cq_buf, sctag3_cpx_data_ca_buf[144:0] }));
// ccx <-> iob repeaters.
ccx_iob_rptr ccx_iob_rptr (
.sig ({ cpx_iob_grant_cx2[7:0], pcx_iob_data_px2[123:0], pcx_iob_data_rdy_px2, unused_ccx_iob_rptri[2:0] }),
.sig_buf ({ cpx_iob_grant_cx2_buf[7:0], pcx_iob_data_px2_buf[123:0], pcx_iob_data_rdy_px2_buf, unused_ccx_iob_rptr[2:0] }));
iob_ccx_rptr iob_ccx_rptr (
.sig ({ iob_cpx_data_ca[115], iob_cpx_data_ca[113], iob_cpx_data_ca[111], iob_cpx_data_ca[109], iob_cpx_data_ca[107],
iob_cpx_data_ca[105], iob_cpx_data_ca[103], iob_cpx_data_ca[101], iob_cpx_data_ca[99], iob_cpx_data_ca[97],
iob_cpx_data_ca[95], iob_cpx_data_ca[93], iob_cpx_data_ca[91], iob_cpx_data_ca[89], iob_cpx_data_ca[87],
iob_cpx_data_ca[85], iob_cpx_data_ca[83], iob_cpx_data_ca[81], iob_cpx_data_ca[79], iob_cpx_data_ca[77],
iob_cpx_data_ca[75], iob_cpx_data_ca[73], iob_cpx_data_ca[71], iob_cpx_data_ca[69], iob_cpx_data_ca[67],
iob_cpx_data_ca[65], iob_cpx_data_ca[63], iob_cpx_data_ca[61], iob_cpx_data_ca[59], iob_cpx_data_ca[57],
iob_cpx_data_ca[55], iob_cpx_data_ca[53], iob_cpx_data_ca[51], iob_cpx_data_ca[49], iob_cpx_data_ca[47],
iob_cpx_data_ca[45], iob_cpx_data_ca[43], iob_cpx_data_ca[41], iob_cpx_data_ca[39], iob_cpx_data_ca[37],
iob_cpx_data_ca[35], iob_cpx_data_ca[33], iob_cpx_data_ca[32], iob_cpx_data_ca[30], iob_cpx_data_ca[28],
iob_cpx_data_ca[26], iob_cpx_data_ca[24], iob_cpx_data_ca[22], iob_cpx_data_ca[20], iob_cpx_data_ca[18],
iob_cpx_data_ca[16], iob_cpx_data_ca[14], iob_cpx_data_ca[12], iob_cpx_data_ca[10], iob_cpx_data_ca[8],
iob_cpx_data_ca[6], iob_cpx_data_ca[4], iob_cpx_data_ca[2], iob_cpx_data_ca[0], iob_cpx_req_cq[6],
iob_cpx_req_cq[4], iob_cpx_req_cq[2], iob_cpx_req_cq[0], iob_cpx_data_ca[143], iob_cpx_data_ca[141],
iob_cpx_data_ca[139], iob_cpx_data_ca[137], iob_cpx_data_ca[135], iob_cpx_data_ca[133], iob_cpx_data_ca[131],
iob_cpx_data_ca[129], iob_cpx_data_ca[127], iob_cpx_data_ca[125], iob_cpx_data_ca[123], iob_cpx_data_ca[121],
iob_cpx_data_ca[119], iob_cpx_data_ca[117], iob_cpx_data_ca[118], iob_cpx_data_ca[120], iob_cpx_data_ca[122],
iob_cpx_data_ca[124], iob_cpx_data_ca[126], iob_cpx_data_ca[128], iob_cpx_data_ca[130], iob_cpx_data_ca[132],
iob_cpx_data_ca[134], iob_cpx_data_ca[136], iob_cpx_data_ca[138], iob_cpx_data_ca[140], iob_cpx_data_ca[142],
iob_cpx_data_ca[144], iob_cpx_req_cq[1], iob_cpx_req_cq[3], iob_cpx_req_cq[5], iob_cpx_req_cq[7],
iob_cpx_data_ca[1], iob_cpx_data_ca[3], iob_cpx_data_ca[5], iob_cpx_data_ca[7], iob_cpx_data_ca[9],
iob_cpx_data_ca[11], iob_cpx_data_ca[13], iob_cpx_data_ca[15], iob_cpx_data_ca[17], iob_cpx_data_ca[19],
iob_cpx_data_ca[21], iob_cpx_data_ca[23], iob_cpx_data_ca[25], iob_cpx_data_ca[27], iob_cpx_data_ca[29],
iob_cpx_data_ca[31], iob_cpx_data_ca[34], iob_cpx_data_ca[36], iob_cpx_data_ca[38], iob_cpx_data_ca[40],
iob_cpx_data_ca[42], iob_cpx_data_ca[44], iob_cpx_data_ca[46], iob_cpx_data_ca[48], iob_cpx_data_ca[50],
iob_cpx_data_ca[52], iob_cpx_data_ca[54], iob_cpx_data_ca[56], iob_cpx_data_ca[58], iob_cpx_data_ca[60],
iob_cpx_data_ca[62], iob_cpx_data_ca[64], iob_cpx_data_ca[66], iob_cpx_data_ca[68], iob_cpx_data_ca[70],
iob_cpx_data_ca[72], iob_cpx_data_ca[74], iob_cpx_data_ca[76], iob_cpx_data_ca[78], iob_cpx_data_ca[80],
iob_cpx_data_ca[82], iob_cpx_data_ca[84], iob_cpx_data_ca[86], iob_cpx_data_ca[88], iob_cpx_data_ca[90],
iob_cpx_data_ca[92], iob_cpx_data_ca[94], iob_cpx_data_ca[96], iob_cpx_data_ca[98], iob_cpx_data_ca[100],
iob_cpx_data_ca[102], iob_cpx_data_ca[104], iob_cpx_data_ca[106], iob_cpx_data_ca[108], iob_cpx_data_ca[110],
iob_cpx_data_ca[112], iob_cpx_data_ca[114], iob_cpx_data_ca[116], iob_pcx_stall_pq, unused_iob_ccx_rptr_bufi[9:0] }),
.sig_buf ({ iob_cpx_data_ca_buf[115], iob_cpx_data_ca_buf[113], iob_cpx_data_ca_buf[111], iob_cpx_data_ca_buf[109], iob_cpx_data_ca_buf[107],
iob_cpx_data_ca_buf[105], iob_cpx_data_ca_buf[103], iob_cpx_data_ca_buf[101], iob_cpx_data_ca_buf[99], iob_cpx_data_ca_buf[97],
iob_cpx_data_ca_buf[95], iob_cpx_data_ca_buf[93], iob_cpx_data_ca_buf[91], iob_cpx_data_ca_buf[89], iob_cpx_data_ca_buf[87],
iob_cpx_data_ca_buf[85], iob_cpx_data_ca_buf[83], iob_cpx_data_ca_buf[81], iob_cpx_data_ca_buf[79], iob_cpx_data_ca_buf[77],
iob_cpx_data_ca_buf[75], iob_cpx_data_ca_buf[73], iob_cpx_data_ca_buf[71], iob_cpx_data_ca_buf[69], iob_cpx_data_ca_buf[67],
iob_cpx_data_ca_buf[65], iob_cpx_data_ca_buf[63], iob_cpx_data_ca_buf[61], iob_cpx_data_ca_buf[59], iob_cpx_data_ca_buf[57],
iob_cpx_data_ca_buf[55], iob_cpx_data_ca_buf[53], iob_cpx_data_ca_buf[51], iob_cpx_data_ca_buf[49], iob_cpx_data_ca_buf[47],
iob_cpx_data_ca_buf[45], iob_cpx_data_ca_buf[43], iob_cpx_data_ca_buf[41], iob_cpx_data_ca_buf[39], iob_cpx_data_ca_buf[37],
iob_cpx_data_ca_buf[35], iob_cpx_data_ca_buf[33], iob_cpx_data_ca_buf[32], iob_cpx_data_ca_buf[30], iob_cpx_data_ca_buf[28],
iob_cpx_data_ca_buf[26], iob_cpx_data_ca_buf[24], iob_cpx_data_ca_buf[22], iob_cpx_data_ca_buf[20], iob_cpx_data_ca_buf[18],
iob_cpx_data_ca_buf[16], iob_cpx_data_ca_buf[14], iob_cpx_data_ca_buf[12], iob_cpx_data_ca_buf[10], iob_cpx_data_ca_buf[8],
iob_cpx_data_ca_buf[6], iob_cpx_data_ca_buf[4], iob_cpx_data_ca_buf[2], iob_cpx_data_ca_buf[0], iob_cpx_req_cq_buf[6],
iob_cpx_req_cq_buf[4], iob_cpx_req_cq_buf[2], iob_cpx_req_cq_buf[0], iob_cpx_data_ca_buf[143], iob_cpx_data_ca_buf[141],
iob_cpx_data_ca_buf[139], iob_cpx_data_ca_buf[137], iob_cpx_data_ca_buf[135], iob_cpx_data_ca_buf[133], iob_cpx_data_ca_buf[131],
iob_cpx_data_ca_buf[129], iob_cpx_data_ca_buf[127], iob_cpx_data_ca_buf[125], iob_cpx_data_ca_buf[123], iob_cpx_data_ca_buf[121],
iob_cpx_data_ca_buf[119], iob_cpx_data_ca_buf[117], iob_cpx_data_ca_buf[118], iob_cpx_data_ca_buf[120], iob_cpx_data_ca_buf[122],
iob_cpx_data_ca_buf[124], iob_cpx_data_ca_buf[126], iob_cpx_data_ca_buf[128], iob_cpx_data_ca_buf[130], iob_cpx_data_ca_buf[132],
iob_cpx_data_ca_buf[134], iob_cpx_data_ca_buf[136], iob_cpx_data_ca_buf[138], iob_cpx_data_ca_buf[140], iob_cpx_data_ca_buf[142],
iob_cpx_data_ca_buf[144], iob_cpx_req_cq_buf[1], iob_cpx_req_cq_buf[3], iob_cpx_req_cq_buf[5], iob_cpx_req_cq_buf[7],
iob_cpx_data_ca_buf[1], iob_cpx_data_ca_buf[3], iob_cpx_data_ca_buf[5], iob_cpx_data_ca_buf[7], iob_cpx_data_ca_buf[9],
iob_cpx_data_ca_buf[11], iob_cpx_data_ca_buf[13], iob_cpx_data_ca_buf[15], iob_cpx_data_ca_buf[17], iob_cpx_data_ca_buf[19],
iob_cpx_data_ca_buf[21], iob_cpx_data_ca_buf[23], iob_cpx_data_ca_buf[25], iob_cpx_data_ca_buf[27], iob_cpx_data_ca_buf[29],
iob_cpx_data_ca_buf[31], iob_cpx_data_ca_buf[34], iob_cpx_data_ca_buf[36], iob_cpx_data_ca_buf[38], iob_cpx_data_ca_buf[40],
iob_cpx_data_ca_buf[42], iob_cpx_data_ca_buf[44], iob_cpx_data_ca_buf[46], iob_cpx_data_ca_buf[48], iob_cpx_data_ca_buf[50],
iob_cpx_data_ca_buf[52], iob_cpx_data_ca_buf[54], iob_cpx_data_ca_buf[56], iob_cpx_data_ca_buf[58], iob_cpx_data_ca_buf[60],
iob_cpx_data_ca_buf[62], iob_cpx_data_ca_buf[64], iob_cpx_data_ca_buf[66], iob_cpx_data_ca_buf[68], iob_cpx_data_ca_buf[70],
iob_cpx_data_ca_buf[72], iob_cpx_data_ca_buf[74], iob_cpx_data_ca_buf[76], iob_cpx_data_ca_buf[78], iob_cpx_data_ca_buf[80],
iob_cpx_data_ca_buf[82], iob_cpx_data_ca_buf[84], iob_cpx_data_ca_buf[86], iob_cpx_data_ca_buf[88], iob_cpx_data_ca_buf[90],
iob_cpx_data_ca_buf[92], iob_cpx_data_ca_buf[94], iob_cpx_data_ca_buf[96], iob_cpx_data_ca_buf[98], iob_cpx_data_ca_buf[100],
iob_cpx_data_ca_buf[102], iob_cpx_data_ca_buf[104], iob_cpx_data_ca_buf[106], iob_cpx_data_ca_buf[108], iob_cpx_data_ca_buf[110],
iob_cpx_data_ca_buf[112], iob_cpx_data_ca_buf[114], iob_cpx_data_ca_buf[116], iob_pcx_stall_pq_buf, unused_iob_ccx_rptr_buf[9:0] }));
// ccx <-> jbi repeaters.
iob_jbi_rptr_0 iob_jbi_rptr_0 (
.sig ({ iob_jbi_pio_data[49], iob_jbi_pio_data[47], iob_jbi_pio_data[45], iob_jbi_pio_data[43], iob_jbi_pio_data[41],
iob_jbi_pio_data[39], iob_jbi_pio_data[37], iob_jbi_pio_data[35], iob_jbi_pio_data[33], iob_jbi_pio_data[31],
iob_jbi_pio_data[29], iob_jbi_pio_data[27], iob_jbi_pio_data[25], iob_jbi_pio_data[23], iob_jbi_pio_data[21],
iob_jbi_pio_data[19], iob_jbi_pio_data[17], iob_jbi_pio_data[15], iob_jbi_pio_data[13], iob_jbi_pio_data[11],
iob_jbi_pio_data[9], iob_jbi_pio_data[7], iob_jbi_pio_data[5], iob_jbi_pio_data[3], iob_jbi_pio_data[1],
iob_jbi_pio_data[0], iob_jbi_dbg_lo_data[47], iob_jbi_dbg_lo_data[45], iob_jbi_dbg_lo_data[43], iob_jbi_dbg_lo_data[41],
iob_jbi_dbg_lo_data[39], iob_jbi_dbg_lo_data[37], iob_jbi_dbg_lo_data[34], iob_jbi_dbg_lo_data[32], iob_jbi_dbg_lo_data[30],
iob_jbi_dbg_lo_data[28], iob_jbi_dbg_lo_data[26], iob_jbi_dbg_lo_data[24], iob_jbi_dbg_lo_data[22], iob_jbi_dbg_lo_data[20],
iob_jbi_dbg_lo_data[18], iob_jbi_dbg_lo_data[16], iob_jbi_dbg_lo_data[14], iob_jbi_dbg_lo_data[12], iob_jbi_dbg_lo_data[10],
iob_jbi_dbg_lo_data[9], iob_jbi_dbg_lo_data[7], iob_jbi_dbg_lo_data[5], iob_jbi_dbg_lo_data[2], iob_jbi_dbg_lo_data[0],
iob_jbi_dbg_hi_data[47], iob_jbi_dbg_hi_data[45], iob_jbi_dbg_hi_data[43], iob_jbi_dbg_hi_data[41], iob_jbi_dbg_hi_data[39],
iob_jbi_dbg_hi_data[37], iob_jbi_dbg_hi_data[35], iob_jbi_dbg_hi_data[33], iob_jbi_dbg_hi_data[31], iob_jbi_dbg_hi_data[30],
iob_jbi_dbg_hi_data[29], iob_jbi_dbg_hi_data[28], iob_jbi_dbg_hi_data[27], iob_jbi_dbg_hi_data[25], iob_jbi_dbg_hi_data[23],
iob_jbi_dbg_hi_data[21], iob_jbi_dbg_hi_data[19], iob_jbi_dbg_hi_data[17], iob_jbi_dbg_hi_data[16], iob_jbi_dbg_hi_data[15],
iob_jbi_dbg_hi_data[14], iob_jbi_dbg_hi_data[13], iob_jbi_dbg_hi_data[12], iob_jbi_dbg_hi_data[11], iob_jbi_dbg_hi_data[10],
iob_jbi_dbg_hi_data[9], iob_jbi_dbg_hi_data[8], iob_jbi_dbg_hi_data[7], iob_jbi_dbg_hi_data[6], iob_jbi_dbg_hi_data[5],
iob_jbi_dbg_hi_data[4], iob_jbi_dbg_hi_data[3], iob_jbi_spi_data[3], iob_jbi_spi_data[1], iob_jbi_pio_data[63],
iob_jbi_pio_data[61], iob_jbi_pio_data[60], iob_jbi_pio_data[59], iob_jbi_pio_data[58], iob_jbi_pio_data[57],
iob_jbi_pio_data[56], iob_jbi_pio_data[55], iob_jbi_pio_data[54], iob_jbi_pio_data[53], iob_jbi_pio_data[52],
iob_jbi_pio_data[51], iob_jbi_pio_data[50], iob_jbi_dbg_hi_data[2], iob_jbi_dbg_hi_data[1], iob_jbi_dbg_hi_data[0],
iob_jbi_pio_data[62], iob_jbi_spi_data[0], iob_jbi_spi_data[2], iob_jbi_dbg_hi_data[18], iob_jbi_dbg_hi_data[20],
iob_jbi_dbg_hi_data[22], iob_jbi_dbg_hi_data[24], iob_jbi_dbg_hi_data[26], iob_jbi_dbg_hi_data[32], iob_jbi_dbg_hi_data[34],
iob_jbi_dbg_hi_data[36], iob_jbi_dbg_hi_data[38], iob_jbi_dbg_hi_data[40], iob_jbi_dbg_hi_data[42], iob_jbi_dbg_hi_data[44],
iob_jbi_dbg_hi_data[46], iob_jbi_dbg_lo_data[1], iob_jbi_dbg_lo_data[3], iob_jbi_dbg_lo_data[4], iob_jbi_dbg_lo_data[6],
iob_jbi_dbg_lo_data[8], iob_jbi_dbg_lo_data[11], iob_jbi_dbg_lo_data[13], iob_jbi_dbg_lo_data[15], iob_jbi_dbg_lo_data[17],
iob_jbi_dbg_lo_data[19], iob_jbi_dbg_lo_data[21], iob_jbi_dbg_lo_data[23], iob_jbi_dbg_lo_data[25], iob_jbi_dbg_lo_data[27],
iob_jbi_dbg_lo_data[29], iob_jbi_dbg_lo_data[31], iob_jbi_dbg_lo_data[33], iob_jbi_dbg_lo_data[35], iob_jbi_dbg_lo_data[36],
iob_jbi_dbg_lo_data[38], iob_jbi_dbg_lo_data[40], iob_jbi_dbg_lo_data[42], iob_jbi_dbg_lo_data[44], iob_jbi_dbg_lo_data[46],
iob_jbi_pio_data[2], iob_jbi_pio_data[4], iob_jbi_pio_data[6], iob_jbi_pio_data[8], iob_jbi_pio_data[10],
iob_jbi_pio_data[12], iob_jbi_pio_data[14], iob_jbi_pio_data[16], iob_jbi_pio_data[18], iob_jbi_pio_data[20],
iob_jbi_pio_data[22], iob_jbi_pio_data[24], iob_jbi_pio_data[26], iob_jbi_pio_data[28], iob_jbi_pio_data[30],
iob_jbi_pio_data[32], iob_jbi_pio_data[34], iob_jbi_pio_data[36], iob_jbi_pio_data[38], iob_jbi_pio_data[40],
iob_jbi_pio_data[42], iob_jbi_pio_data[44], iob_jbi_pio_data[46], iob_jbi_pio_data[48] }),
.sig_buf ({ iob_jbi_pio_data_buf[49], iob_jbi_pio_data_buf[47], iob_jbi_pio_data_buf[45], iob_jbi_pio_data_buf[43], iob_jbi_pio_data_buf[41],
iob_jbi_pio_data_buf[39], iob_jbi_pio_data_buf[37], iob_jbi_pio_data_buf[35], iob_jbi_pio_data_buf[33], iob_jbi_pio_data_buf[31],
iob_jbi_pio_data_buf[29], iob_jbi_pio_data_buf[27], iob_jbi_pio_data_buf[25], iob_jbi_pio_data_buf[23], iob_jbi_pio_data_buf[21],
iob_jbi_pio_data_buf[19], iob_jbi_pio_data_buf[17], iob_jbi_pio_data_buf[15], iob_jbi_pio_data_buf[13], iob_jbi_pio_data_buf[11],
iob_jbi_pio_data_buf[9], iob_jbi_pio_data_buf[7], iob_jbi_pio_data_buf[5], iob_jbi_pio_data_buf[3], iob_jbi_pio_data_buf[1],
iob_jbi_pio_data_buf[0], iob_jbi_dbg_lo_data_buf[47], iob_jbi_dbg_lo_data_buf[45], iob_jbi_dbg_lo_data_buf[43], iob_jbi_dbg_lo_data_buf[41],
iob_jbi_dbg_lo_data_buf[39], iob_jbi_dbg_lo_data_buf[37], iob_jbi_dbg_lo_data_buf[34], iob_jbi_dbg_lo_data_buf[32], iob_jbi_dbg_lo_data_buf[30],
iob_jbi_dbg_lo_data_buf[28], iob_jbi_dbg_lo_data_buf[26], iob_jbi_dbg_lo_data_buf[24], iob_jbi_dbg_lo_data_buf[22], iob_jbi_dbg_lo_data_buf[20],
iob_jbi_dbg_lo_data_buf[18], iob_jbi_dbg_lo_data_buf[16], iob_jbi_dbg_lo_data_buf[14], iob_jbi_dbg_lo_data_buf[12], iob_jbi_dbg_lo_data_buf[10],
iob_jbi_dbg_lo_data_buf[9], iob_jbi_dbg_lo_data_buf[7], iob_jbi_dbg_lo_data_buf[5], iob_jbi_dbg_lo_data_buf[2], iob_jbi_dbg_lo_data_buf[0],
iob_jbi_dbg_hi_data_buf[47], iob_jbi_dbg_hi_data_buf[45], iob_jbi_dbg_hi_data_buf[43], iob_jbi_dbg_hi_data_buf[41], iob_jbi_dbg_hi_data_buf[39],
iob_jbi_dbg_hi_data_buf[37], iob_jbi_dbg_hi_data_buf[35], iob_jbi_dbg_hi_data_buf[33], iob_jbi_dbg_hi_data_buf[31], iob_jbi_dbg_hi_data_buf[30],
iob_jbi_dbg_hi_data_buf[29], iob_jbi_dbg_hi_data_buf[28], iob_jbi_dbg_hi_data_buf[27], iob_jbi_dbg_hi_data_buf[25], iob_jbi_dbg_hi_data_buf[23],
iob_jbi_dbg_hi_data_buf[21], iob_jbi_dbg_hi_data_buf[19], iob_jbi_dbg_hi_data_buf[17], iob_jbi_dbg_hi_data_buf[16], iob_jbi_dbg_hi_data_buf[15],
iob_jbi_dbg_hi_data_buf[14], iob_jbi_dbg_hi_data_buf[13], iob_jbi_dbg_hi_data_buf[12], iob_jbi_dbg_hi_data_buf[11], iob_jbi_dbg_hi_data_buf[10],
iob_jbi_dbg_hi_data_buf[9], iob_jbi_dbg_hi_data_buf[8], iob_jbi_dbg_hi_data_buf[7], iob_jbi_dbg_hi_data_buf[6], iob_jbi_dbg_hi_data_buf[5],
iob_jbi_dbg_hi_data_buf[4], iob_jbi_dbg_hi_data_buf[3], iob_jbi_spi_data_buf[3], iob_jbi_spi_data_buf[1], iob_jbi_pio_data_buf[63],
iob_jbi_pio_data_buf[61], iob_jbi_pio_data_buf[60], iob_jbi_pio_data_buf[59], iob_jbi_pio_data_buf[58], iob_jbi_pio_data_buf[57],
iob_jbi_pio_data_buf[56], iob_jbi_pio_data_buf[55], iob_jbi_pio_data_buf[54], iob_jbi_pio_data_buf[53], iob_jbi_pio_data_buf[52],
iob_jbi_pio_data_buf[51], iob_jbi_pio_data_buf[50], iob_jbi_dbg_hi_data_buf[2], iob_jbi_dbg_hi_data_buf[1], iob_jbi_dbg_hi_data_buf[0],
iob_jbi_pio_data_buf[62], iob_jbi_spi_data_buf[0], iob_jbi_spi_data_buf[2], iob_jbi_dbg_hi_data_buf[18], iob_jbi_dbg_hi_data_buf[20],
iob_jbi_dbg_hi_data_buf[22], iob_jbi_dbg_hi_data_buf[24], iob_jbi_dbg_hi_data_buf[26], iob_jbi_dbg_hi_data_buf[32], iob_jbi_dbg_hi_data_buf[34],
iob_jbi_dbg_hi_data_buf[36], iob_jbi_dbg_hi_data_buf[38], iob_jbi_dbg_hi_data_buf[40], iob_jbi_dbg_hi_data_buf[42], iob_jbi_dbg_hi_data_buf[44],
iob_jbi_dbg_hi_data_buf[46], iob_jbi_dbg_lo_data_buf[1], iob_jbi_dbg_lo_data_buf[3], iob_jbi_dbg_lo_data_buf[4], iob_jbi_dbg_lo_data_buf[6],
iob_jbi_dbg_lo_data_buf[8], iob_jbi_dbg_lo_data_buf[11], iob_jbi_dbg_lo_data_buf[13], iob_jbi_dbg_lo_data_buf[15], iob_jbi_dbg_lo_data_buf[17],
iob_jbi_dbg_lo_data_buf[19], iob_jbi_dbg_lo_data_buf[21], iob_jbi_dbg_lo_data_buf[23], iob_jbi_dbg_lo_data_buf[25], iob_jbi_dbg_lo_data_buf[27],
iob_jbi_dbg_lo_data_buf[29], iob_jbi_dbg_lo_data_buf[31], iob_jbi_dbg_lo_data_buf[33], iob_jbi_dbg_lo_data_buf[35], iob_jbi_dbg_lo_data_buf[36],
iob_jbi_dbg_lo_data_buf[38], iob_jbi_dbg_lo_data_buf[40], iob_jbi_dbg_lo_data_buf[42], iob_jbi_dbg_lo_data_buf[44], iob_jbi_dbg_lo_data_buf[46],
iob_jbi_pio_data_buf[2], iob_jbi_pio_data_buf[4], iob_jbi_pio_data_buf[6], iob_jbi_pio_data_buf[8], iob_jbi_pio_data_buf[10],
iob_jbi_pio_data_buf[12], iob_jbi_pio_data_buf[14], iob_jbi_pio_data_buf[16], iob_jbi_pio_data_buf[18], iob_jbi_pio_data_buf[20],
iob_jbi_pio_data_buf[22], iob_jbi_pio_data_buf[24], iob_jbi_pio_data_buf[26], iob_jbi_pio_data_buf[28], iob_jbi_pio_data_buf[30],
iob_jbi_pio_data_buf[32], iob_jbi_pio_data_buf[34], iob_jbi_pio_data_buf[36], iob_jbi_pio_data_buf[38], iob_jbi_pio_data_buf[40],
iob_jbi_pio_data_buf[42], iob_jbi_pio_data_buf[44], iob_jbi_pio_data_buf[46], iob_jbi_pio_data_buf[48] }));
iob_jbi_rptr_1 iob_jbi_rptr_1 (
.sig ({ jbi_iob_spi_stall, jbi_iob_spi_data[2], jbi_iob_spi_data[0], jbi_iob_pio_stall, jbi_iob_pio_data[14],
jbi_iob_pio_data[12], jbi_iob_pio_data[10], jbi_iob_pio_data[8], jbi_iob_pio_data[6], jbi_iob_pio_data[4],
jbi_iob_pio_data[2], jbi_iob_pio_data[0], jbi_iob_mondo_data[7], jbi_iob_mondo_data[5], jbi_iob_mondo_data[3],
jbi_iob_mondo_data[1], iob_jbi_mondo_ack, iob_jbi_spi_vld, iob_jbi_pio_vld, iob_jbi_pio_stall,
iob_jbi_spi_stall, iob_jbi_dbg_hi_vld, iob_jbi_dbg_lo_vld, iob_jbi_mondo_nack, jbi_iob_mondo_data[0],
jbi_iob_mondo_data[2], jbi_iob_mondo_data[4], jbi_iob_mondo_data[6], jbi_iob_mondo_vld, jbi_iob_pio_data[1],
jbi_iob_pio_data[3], jbi_iob_pio_data[5], jbi_iob_pio_data[7], jbi_iob_pio_data[9], jbi_iob_pio_data[11],
jbi_iob_pio_data[13], jbi_iob_pio_data[15], jbi_iob_pio_vld, jbi_iob_spi_data[1], jbi_iob_spi_data[3],
jbi_iob_spi_vld, unused_iob_jbi_rptr_1i[94:0] }),
.sig_buf ({ jbi_iob_spi_stall_buf, jbi_iob_spi_data_buf[2], jbi_iob_spi_data_buf[0], jbi_iob_pio_stall_buf, jbi_iob_pio_data_buf[14],
jbi_iob_pio_data_buf[12], jbi_iob_pio_data_buf[10], jbi_iob_pio_data_buf[8], jbi_iob_pio_data_buf[6], jbi_iob_pio_data_buf[4],
jbi_iob_pio_data_buf[2], jbi_iob_pio_data_buf[0], jbi_iob_mondo_data_buf[7], jbi_iob_mondo_data_buf[5], jbi_iob_mondo_data_buf[3],
jbi_iob_mondo_data_buf[1], iob_jbi_mondo_ack_buf, iob_jbi_spi_vld_buf, iob_jbi_pio_vld_buf, iob_jbi_pio_stall_buf,
iob_jbi_spi_stall_buf, iob_jbi_dbg_hi_vld_buf, iob_jbi_dbg_lo_vld_buf, iob_jbi_mondo_nack_buf, jbi_iob_mondo_data_buf[0],
jbi_iob_mondo_data_buf[2], jbi_iob_mondo_data_buf[4], jbi_iob_mondo_data_buf[6], jbi_iob_mondo_vld_buf, jbi_iob_pio_data_buf[1],
jbi_iob_pio_data_buf[3], jbi_iob_pio_data_buf[5], jbi_iob_pio_data_buf[7], jbi_iob_pio_data_buf[9], jbi_iob_pio_data_buf[11],
jbi_iob_pio_data_buf[13], jbi_iob_pio_data_buf[15], jbi_iob_pio_vld_buf, jbi_iob_spi_data_buf[1], jbi_iob_spi_data_buf[3],
jbi_iob_spi_vld_buf, unused_iob_jbi_rptr_1[94:0] }));
//
/* dram AUTO_TEMPLATE (
.dram_si (par_scan_head[0]),
.dram_so (par_scan_tail[0]),
.jbus_gclk (jbus_gclk_c1_r[3]),
.dram_gclk (dram_gclk_c1_r[3]),
.cmp_gclk (cmp_gclk_c1_r[3]),
.cmp_grst_l (rpt_cmp_grst_l_c@"(+ 1 (* 6 (% @ 2)))"),
.cmp_gdbginit_l (rpt_cmp_gdbginit_l_c@"(+ 1 (* 6 (% @ 2)))"),
.clspine_\(.*\)_sync (rpt_cmp_\1_sync_c@"(+ 1 (* 6 (% @ 2)))"),
.clk_dram_cmp_cken (rpt_dram@"(/ @ 10)"@"(% @ 10)"_cmp_cken),
.clk_dram_dram_cken (ctu_dram@"(/ @ 10)"@"(% @ 10)"_dram_cken),
.clk_dram_jbus_cken (ctu_dram@"(/ @ 10)"@"(% @ 10)"_jbus_cken),
.clspine_dram_selfrsh (ctu_dram_selfrsh),
.dram_clk_tr (dram@_ctu_tr),
.dram_pad_ddr\([01]\)\(.*\) (dram@_pad_ddr@"(+ (/ @ 10) (* \1 2))"\2[]),
.dram_pt_\(.*\) (dram_pt@_\1[]),
.dram_other_pt_\(.*\) (dram_pt@"(% (+ @ 1) 2)"@"(+ (% (+ @ 1) 2) 2)"_\1[]),
.dram_other_pt\([01]\)_\(.*\) (dram_pt@"(+ (% (+ @ 1) 2) (* 2 \1) )"_\2[]),
.dram_local_pt\([01]\)_\(.*\) (dram_pt@"(+ (% @ 2) (* 2 \1) )"_\2[]),
.dram_sctag\([01]\)\(.*\) (dram@_sctag@"(+ (/ @ 10) (* \1 2))"\2[]),
.sctag\([01]\)_dram\(.*\) (sctag@"(+ (/ @ 10) (* \1 2))"_dram@\2_d1[]),
.dram_scbuf\([01]\)\(.*\) (dram@_scbuf@"(+ (/ @ 10) (* \1 2))"\2[]),
.scbuf\([01]\)_dram\(.*\) (scbuf@"(+ (/ @ 10) (* \1 2))"_dram@\2_d1[]),
.dram\([01]\)_ddr\([01]\)\(.*\) (dram@"(+ (/ @ 10) (* \1 2))"_ddr@"(+ (/ @ 10) (* \1 2))"\3[]),
.ddr\([01]\)_dram\([01]\)\(.*\) (ddr@"(+ (/ @ 10) (* \1 2))"_dram@"(+ (/ @ 10) (* \1 2))"\3[]),
.ucb_iob\(.*\) (dram@_iob\1[]),
.iob_ucb\(.*\) (iob_dram@\1[]),
.pad\(.*\) (io_dram@\1[]),
.dram_io\(.*\)\([0-1]\)\(.*\) (dram@"(+ (/ @ 10) (* \2 2))"_io\1\3[]),
.io_dram\(.*\)\([0-1]\)\(.*\) (io_dram@"(+ (/ @ 10) (* \2 2))"\1\3_buf0[]),
); */
//
`ifdef RTL_DRAM02
dram dram02
(/*AUTOINST*/
// Outputs
.dram_io_addr0 (dram0_io_addr[14:0]), // Templated
.dram_io_addr1 (dram2_io_addr[14:0]), // Templated
.dram_io_bank0 (dram0_io_bank[2:0]), // Templated
.dram_io_bank1 (dram2_io_bank[2:0]), // Templated
.dram_io_cas0_l (dram0_io_cas_l), // Templated
.dram_io_cas1_l (dram2_io_cas_l), // Templated
.dram_io_channel_disabled0 (dram0_io_channel_disabled), // Templated
.dram_io_channel_disabled1 (dram2_io_channel_disabled), // Templated
.dram_io_cke0 (dram0_io_cke), // Templated
.dram_io_cke1 (dram2_io_cke), // Templated
.dram_io_clk_enable0 (dram0_io_clk_enable), // Templated
.dram_io_clk_enable1 (dram2_io_clk_enable), // Templated
.dram_io_cs0_l (dram0_io_cs_l[3:0]), // Templated
.dram_io_cs1_l (dram2_io_cs_l[3:0]), // Templated
.dram_io_data0_out (dram0_io_data_out[287:0]), // Templated
.dram_io_data1_out (dram2_io_data_out[287:0]), // Templated
.dram_io_drive_data0 (dram0_io_drive_data), // Templated
.dram_io_drive_data1 (dram2_io_drive_data), // Templated
.dram_io_drive_enable0 (dram0_io_drive_enable), // Templated
.dram_io_drive_enable1 (dram2_io_drive_enable), // Templated
.dram_io_pad_clk_inv0 (dram0_io_pad_clk_inv), // Templated
.dram_io_pad_clk_inv1 (dram2_io_pad_clk_inv), // Templated
.dram_io_pad_enable0 (dram0_io_pad_enable), // Templated
.dram_io_pad_enable1 (dram2_io_pad_enable), // Templated
.dram_io_ptr_clk_inv0 (dram0_io_ptr_clk_inv[4:0]), // Templated
.dram_io_ptr_clk_inv1 (dram2_io_ptr_clk_inv[4:0]), // Templated
.dram_io_ras0_l (dram0_io_ras_l), // Templated
.dram_io_ras1_l (dram2_io_ras_l), // Templated
.dram_io_write_en0_l (dram0_io_write_en_l), // Templated
.dram_io_write_en1_l (dram2_io_write_en_l), // Templated
.dram_sctag0_data_vld_r0 (dram02_sctag0_data_vld_r0), // Templated
.dram_sctag0_rd_ack (dram02_sctag0_rd_ack), // Templated
.dram_sctag0_scb_mecc_err (dram02_sctag0_scb_mecc_err), // Templated
.dram_sctag0_scb_secc_err (dram02_sctag0_scb_secc_err), // Templated
.dram_sctag0_wr_ack (dram02_sctag0_wr_ack), // Templated
.dram_sctag1_data_vld_r0 (dram02_sctag2_data_vld_r0), // Templated
.dram_sctag1_rd_ack (dram02_sctag2_rd_ack), // Templated
.dram_sctag1_scb_mecc_err (dram02_sctag2_scb_mecc_err), // Templated
.dram_sctag1_scb_secc_err (dram02_sctag2_scb_secc_err), // Templated
.dram_sctag1_wr_ack (dram02_sctag2_wr_ack), // Templated
.ucb_iob_data (dram02_iob_data[3:0]), // Templated
.ucb_iob_stall (dram02_iob_stall), // Templated
.ucb_iob_vld (dram02_iob_vld), // Templated
.dram_sctag0_chunk_id_r0 (dram02_sctag0_chunk_id_r0[1:0]), // Templated
.dram_sctag0_mecc_err_r2 (dram02_sctag0_mecc_err_r2), // Templated
.dram_sctag0_rd_req_id_r0 (dram02_sctag0_rd_req_id_r0[2:0]), // Templated
.dram_sctag0_secc_err_r2 (dram02_sctag0_secc_err_r2), // Templated
.dram_sctag1_chunk_id_r0 (dram02_sctag2_chunk_id_r0[1:0]), // Templated
.dram_sctag1_mecc_err_r2 (dram02_sctag2_mecc_err_r2), // Templated
.dram_sctag1_rd_req_id_r0 (dram02_sctag2_rd_req_id_r0[2:0]), // Templated
.dram_sctag1_secc_err_r2 (dram02_sctag2_secc_err_r2), // Templated
.dram_scbuf0_data_r2 (dram02_scbuf0_data_r2[127:0]), // Templated
.dram_scbuf0_ecc_r2 (dram02_scbuf0_ecc_r2[27:0]), // Templated
.dram_scbuf1_data_r2 (dram02_scbuf2_data_r2[127:0]), // Templated
.dram_scbuf1_ecc_r2 (dram02_scbuf2_ecc_r2[27:0]), // Templated
.dram_local_pt0_opened_bank (dram_pt0_opened_bank), // Templated
.dram_local_pt1_opened_bank (dram_pt2_opened_bank), // Templated
.dram_pt_max_banks_open_valid (dram_pt02_max_banks_open_valid), // Templated
.dram_pt_max_time_valid (dram_pt02_max_time_valid), // Templated
.dram_pt_ucb_data (dram_pt02_ucb_data[16:0]), // Templated
.dram_clk_tr (dram02_ctu_tr), // Templated
.dram_so (par_scan_tail[0]), // Templated
// Inputs
.dram_other_pt_max_banks_open_valid(dram_pt13_max_banks_open_valid), // Templated
.dram_other_pt_max_time_valid (dram_pt13_max_time_valid), // Templated
.dram_other_pt_ucb_data (dram_pt13_ucb_data[16:0]), // Templated
.dram_other_pt0_opened_bank (dram_pt1_opened_bank), // Templated
.dram_other_pt1_opened_bank (dram_pt3_opened_bank), // Templated
.io_dram0_data_in (io_dram0_data_in_buf0[255:0]), // Templated
.io_dram0_data_valid (io_dram0_data_valid_buf0), // Templated
.io_dram0_ecc_in (io_dram0_ecc_in_buf0[31:0]), // Templated
.io_dram1_data_in (io_dram2_data_in_buf0[255:0]), // Templated
.io_dram1_data_valid (io_dram2_data_valid_buf0), // Templated
.io_dram1_ecc_in (io_dram2_ecc_in_buf0[31:0]), // Templated
.iob_ucb_data (iob_dram02_data[3:0]), // Templated
.iob_ucb_stall (iob_dram02_stall), // Templated
.iob_ucb_vld (iob_dram02_vld), // Templated
.scbuf0_dram_data_mecc_r5 (scbuf0_dram02_data_mecc_r5_d1), // Templated
.scbuf0_dram_data_vld_r5 (scbuf0_dram02_data_vld_r5_d1), // Templated
.scbuf0_dram_wr_data_r5 (scbuf0_dram02_wr_data_r5_d1[63:0]), // Templated
.scbuf1_dram_data_mecc_r5 (scbuf2_dram02_data_mecc_r5_d1), // Templated
.scbuf1_dram_data_vld_r5 (scbuf2_dram02_data_vld_r5_d1), // Templated
.scbuf1_dram_wr_data_r5 (scbuf2_dram02_wr_data_r5_d1[63:0]), // Templated
.sctag0_dram_addr (sctag0_dram02_addr_d1[39:5]), // Templated
.sctag0_dram_rd_dummy_req (sctag0_dram02_rd_dummy_req_d1), // Templated
.sctag0_dram_rd_req (sctag0_dram02_rd_req_d1), // Templated
.sctag0_dram_rd_req_id (sctag0_dram02_rd_req_id_d1[2:0]), // Templated
.sctag0_dram_wr_req (sctag0_dram02_wr_req_d1), // Templated
.sctag1_dram_addr (sctag2_dram02_addr_d1[39:5]), // Templated
.sctag1_dram_rd_dummy_req (sctag2_dram02_rd_dummy_req_d1), // Templated
.sctag1_dram_rd_req (sctag2_dram02_rd_req_d1), // Templated
.sctag1_dram_rd_req_id (sctag2_dram02_rd_req_id_d1[2:0]), // Templated
.sctag1_dram_wr_req (sctag2_dram02_wr_req_d1), // Templated
.clspine_dram_rx_sync (rpt_cmp_dram_rx_sync_c1), // Templated
.clspine_dram_tx_sync (rpt_cmp_dram_tx_sync_c1), // Templated
.clspine_jbus_rx_sync (rpt_cmp_jbus_rx_sync_c1), // Templated
.clspine_jbus_tx_sync (rpt_cmp_jbus_tx_sync_c1), // Templated
.dram_gdbginit_l (dram_gdbginit_l),
.clk_dram_jbus_cken (ctu_dram02_jbus_cken), // Templated
.clk_dram_dram_cken (ctu_dram02_dram_cken), // Templated
.clk_dram_cmp_cken (rpt_dram02_cmp_cken), // Templated
.clspine_dram_selfrsh (ctu_dram_selfrsh), // Templated
.global_shift_enable (global_shift_enable),
.dram_si (par_scan_head[0]), // Templated
.jbus_gclk (jbus_gclk_c1_r[3]), // Templated
.dram_gclk (dram_gclk_c1_r[3]), // Templated
.cmp_gclk (cmp_gclk_c1_r[3]), // Templated
.dram_adbginit_l (dram_adbginit_l),
.dram_arst_l (dram_arst_l),
.jbus_grst_l (jbus_grst_l),
.dram_grst_l (dram_grst_l),
.cmp_grst_l (rpt_cmp_grst_l_c1), // Templated
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_short_chain (ctu_tst_short_chain));
`endif
//
/* dram AUTO_TEMPLATE (
.dram_si (par_scan_head[20]),
.dram_so (par_scan_tail[20]),
.jbus_gclk (jbus_gclk_c1_r[5]),
.dram_gclk (dram_gclk_c1_r[5]),
.cmp_gclk (cmp_gclk_c1_r[5]),
.cmp_grst_l (rpt_cmp_grst_l_c6),
.cmp_gdbginit_l (rpt_cmp_gdbginit_l_c@"(+ 1 (* 6 (% @ 2)))"),
.clspine_dram_rx_sync (rpt_cmp_dram_rx_sync_c6),
.clspine_dram_tx_sync (rpt_cmp_dram_tx_sync_c6),
.clspine_jbus_rx_sync (rpt_cmp_jbus_rx_sync_c6),
.clspine_jbus_tx_sync (rpt_cmp_jbus_tx_sync_c6),
.clk_dram_cmp_cken (rpt_dram@"(/ @ 10)"@"(% @ 10)"_cmp_cken),
.clk_dram_dram_cken (ctu_dram@"(/ @ 10)"@"(% @ 10)"_dram_cken),
.clk_dram_jbus_cken (ctu_dram@"(/ @ 10)"@"(% @ 10)"_jbus_cken),
.clspine_dram_selfrsh (ctu_dram_selfrsh),
.dram_clk_tr (dram@_ctu_tr),
.dram_pad_ddr\([01]\)\(.*\) (dram@_pad_ddr@"(+ (/ @ 10) (* \1 2))"\2[]),
.dram_pt_\(.*\) (dram_pt@_\1[]),
.dram_other_pt_\(.*\) (dram_pt@"(% (+ @ 1) 2)"@"(+ (% (+ @ 1) 2) 2)"_\1[]),
.dram_other_pt\([01]\)_\(.*\) (dram_pt@"(+ (% (+ @ 1) 2) (* 2 \1) )"_\2[]),
.dram_local_pt\([01]\)_\(.*\) (dram_pt@"(+ (% @ 2) (* 2 \1) )"_\2[]),
.dram_sctag\([01]\)\(.*\) (dram@_sctag@"(+ (/ @ 10) (* \1 2))"\2[]),
.sctag\([01]\)_dram\(.*\) (sctag@"(+ (/ @ 10) (* \1 2))"_dram@\2_d1[]),
.dram_scbuf\([01]\)\(.*\) (dram@_scbuf@"(+ (/ @ 10) (* \1 2))"\2[]),
.scbuf\([01]\)_dram\(.*\) (scbuf@"(+ (/ @ 10) (* \1 2))"_dram@\2_d1[]),
.dram\([01]\)_ddr\([01]\)\(.*\) (dram@"(+ (/ @ 10) (* \1 2))"_ddr@"(+ (/ @ 10) (* \1 2))"\3[]),
.ddr\([01]\)_dram\([01]\)\(.*\) (ddr@"(+ (/ @ 10) (* \1 2))"_dram@"(+ (/ @ 10) (* \1 2))"\3[]),
.ucb_iob\(.*\) (dram@_iob\1[]),
.iob_ucb\(.*\) (iob_dram@\1[]),
.pad\(.*\) (io_dram@\1[]),
.dram_io\(.*\)\([0-1]\)\(.*\) (dram@"(+ (/ @ 10) (* \2 2))"_io\1\3[]),
.io_dram\(.*\)\([0-1]\)\(.*\) (io_dram@"(+ (/ @ 10) (* \2 2))"\1\3_buf0[]),
); */
//
`ifdef RTL_DRAM13
dram dram13
(/*AUTOINST*/
// Outputs
.dram_io_addr0 (dram1_io_addr[14:0]), // Templated
.dram_io_addr1 (dram3_io_addr[14:0]), // Templated
.dram_io_bank0 (dram1_io_bank[2:0]), // Templated
.dram_io_bank1 (dram3_io_bank[2:0]), // Templated
.dram_io_cas0_l (dram1_io_cas_l), // Templated
.dram_io_cas1_l (dram3_io_cas_l), // Templated
.dram_io_channel_disabled0 (dram1_io_channel_disabled), // Templated
.dram_io_channel_disabled1 (dram3_io_channel_disabled), // Templated
.dram_io_cke0 (dram1_io_cke), // Templated
.dram_io_cke1 (dram3_io_cke), // Templated
.dram_io_clk_enable0 (dram1_io_clk_enable), // Templated
.dram_io_clk_enable1 (dram3_io_clk_enable), // Templated
.dram_io_cs0_l (dram1_io_cs_l[3:0]), // Templated
.dram_io_cs1_l (dram3_io_cs_l[3:0]), // Templated
.dram_io_data0_out (dram1_io_data_out[287:0]), // Templated
.dram_io_data1_out (dram3_io_data_out[287:0]), // Templated
.dram_io_drive_data0 (dram1_io_drive_data), // Templated
.dram_io_drive_data1 (dram3_io_drive_data), // Templated
.dram_io_drive_enable0 (dram1_io_drive_enable), // Templated
.dram_io_drive_enable1 (dram3_io_drive_enable), // Templated
.dram_io_pad_clk_inv0 (dram1_io_pad_clk_inv), // Templated
.dram_io_pad_clk_inv1 (dram3_io_pad_clk_inv), // Templated
.dram_io_pad_enable0 (dram1_io_pad_enable), // Templated
.dram_io_pad_enable1 (dram3_io_pad_enable), // Templated
.dram_io_ptr_clk_inv0 (dram1_io_ptr_clk_inv[4:0]), // Templated
.dram_io_ptr_clk_inv1 (dram3_io_ptr_clk_inv[4:0]), // Templated
.dram_io_ras0_l (dram1_io_ras_l), // Templated
.dram_io_ras1_l (dram3_io_ras_l), // Templated
.dram_io_write_en0_l (dram1_io_write_en_l), // Templated
.dram_io_write_en1_l (dram3_io_write_en_l), // Templated
.dram_sctag0_data_vld_r0 (dram13_sctag1_data_vld_r0), // Templated
.dram_sctag0_rd_ack (dram13_sctag1_rd_ack), // Templated
.dram_sctag0_scb_mecc_err (dram13_sctag1_scb_mecc_err), // Templated
.dram_sctag0_scb_secc_err (dram13_sctag1_scb_secc_err), // Templated
.dram_sctag0_wr_ack (dram13_sctag1_wr_ack), // Templated
.dram_sctag1_data_vld_r0 (dram13_sctag3_data_vld_r0), // Templated
.dram_sctag1_rd_ack (dram13_sctag3_rd_ack), // Templated
.dram_sctag1_scb_mecc_err (dram13_sctag3_scb_mecc_err), // Templated
.dram_sctag1_scb_secc_err (dram13_sctag3_scb_secc_err), // Templated
.dram_sctag1_wr_ack (dram13_sctag3_wr_ack), // Templated
.ucb_iob_data (dram13_iob_data[3:0]), // Templated
.ucb_iob_stall (dram13_iob_stall), // Templated
.ucb_iob_vld (dram13_iob_vld), // Templated
.dram_sctag0_chunk_id_r0 (dram13_sctag1_chunk_id_r0[1:0]), // Templated
.dram_sctag0_mecc_err_r2 (dram13_sctag1_mecc_err_r2), // Templated
.dram_sctag0_rd_req_id_r0 (dram13_sctag1_rd_req_id_r0[2:0]), // Templated
.dram_sctag0_secc_err_r2 (dram13_sctag1_secc_err_r2), // Templated
.dram_sctag1_chunk_id_r0 (dram13_sctag3_chunk_id_r0[1:0]), // Templated
.dram_sctag1_mecc_err_r2 (dram13_sctag3_mecc_err_r2), // Templated
.dram_sctag1_rd_req_id_r0 (dram13_sctag3_rd_req_id_r0[2:0]), // Templated
.dram_sctag1_secc_err_r2 (dram13_sctag3_secc_err_r2), // Templated
.dram_scbuf0_data_r2 (dram13_scbuf1_data_r2[127:0]), // Templated
.dram_scbuf0_ecc_r2 (dram13_scbuf1_ecc_r2[27:0]), // Templated
.dram_scbuf1_data_r2 (dram13_scbuf3_data_r2[127:0]), // Templated
.dram_scbuf1_ecc_r2 (dram13_scbuf3_ecc_r2[27:0]), // Templated
.dram_local_pt0_opened_bank (dram_pt1_opened_bank), // Templated
.dram_local_pt1_opened_bank (dram_pt3_opened_bank), // Templated
.dram_pt_max_banks_open_valid (dram_pt13_max_banks_open_valid), // Templated
.dram_pt_max_time_valid (dram_pt13_max_time_valid), // Templated
.dram_pt_ucb_data (dram_pt13_ucb_data[16:0]), // Templated
.dram_clk_tr (dram13_ctu_tr), // Templated
.dram_so (par_scan_tail[20]), // Templated
// Inputs
.dram_other_pt_max_banks_open_valid(dram_pt02_max_banks_open_valid), // Templated
.dram_other_pt_max_time_valid (dram_pt02_max_time_valid), // Templated
.dram_other_pt_ucb_data (dram_pt02_ucb_data[16:0]), // Templated
.dram_other_pt0_opened_bank (dram_pt0_opened_bank), // Templated
.dram_other_pt1_opened_bank (dram_pt2_opened_bank), // Templated
.io_dram0_data_in (io_dram1_data_in_buf0[255:0]), // Templated
.io_dram0_data_valid (io_dram1_data_valid_buf0), // Templated
.io_dram0_ecc_in (io_dram1_ecc_in_buf0[31:0]), // Templated
.io_dram1_data_in (io_dram3_data_in_buf0[255:0]), // Templated
.io_dram1_data_valid (io_dram3_data_valid_buf0), // Templated
.io_dram1_ecc_in (io_dram3_ecc_in_buf0[31:0]), // Templated
.iob_ucb_data (iob_dram13_data[3:0]), // Templated
.iob_ucb_stall (iob_dram13_stall), // Templated
.iob_ucb_vld (iob_dram13_vld), // Templated
.scbuf0_dram_data_mecc_r5 (scbuf1_dram13_data_mecc_r5_d1), // Templated
.scbuf0_dram_data_vld_r5 (scbuf1_dram13_data_vld_r5_d1), // Templated
.scbuf0_dram_wr_data_r5 (scbuf1_dram13_wr_data_r5_d1[63:0]), // Templated
.scbuf1_dram_data_mecc_r5 (scbuf3_dram13_data_mecc_r5_d1), // Templated
.scbuf1_dram_data_vld_r5 (scbuf3_dram13_data_vld_r5_d1), // Templated
.scbuf1_dram_wr_data_r5 (scbuf3_dram13_wr_data_r5_d1[63:0]), // Templated
.sctag0_dram_addr (sctag1_dram13_addr_d1[39:5]), // Templated
.sctag0_dram_rd_dummy_req (sctag1_dram13_rd_dummy_req_d1), // Templated
.sctag0_dram_rd_req (sctag1_dram13_rd_req_d1), // Templated
.sctag0_dram_rd_req_id (sctag1_dram13_rd_req_id_d1[2:0]), // Templated
.sctag0_dram_wr_req (sctag1_dram13_wr_req_d1), // Templated
.sctag1_dram_addr (sctag3_dram13_addr_d1[39:5]), // Templated
.sctag1_dram_rd_dummy_req (sctag3_dram13_rd_dummy_req_d1), // Templated
.sctag1_dram_rd_req (sctag3_dram13_rd_req_d1), // Templated
.sctag1_dram_rd_req_id (sctag3_dram13_rd_req_id_d1[2:0]), // Templated
.sctag1_dram_wr_req (sctag3_dram13_wr_req_d1), // Templated
.clspine_dram_rx_sync (rpt_cmp_dram_rx_sync_c6), // Templated
.clspine_dram_tx_sync (rpt_cmp_dram_tx_sync_c6), // Templated
.clspine_jbus_rx_sync (rpt_cmp_jbus_rx_sync_c6), // Templated
.clspine_jbus_tx_sync (rpt_cmp_jbus_tx_sync_c6), // Templated
.dram_gdbginit_l (dram_gdbginit_l),
.clk_dram_jbus_cken (ctu_dram13_jbus_cken), // Templated
.clk_dram_dram_cken (ctu_dram13_dram_cken), // Templated
.clk_dram_cmp_cken (rpt_dram13_cmp_cken), // Templated
.clspine_dram_selfrsh (ctu_dram_selfrsh), // Templated
.global_shift_enable (global_shift_enable),
.dram_si (par_scan_head[20]), // Templated
.jbus_gclk (jbus_gclk_c1_r[5]), // Templated
.dram_gclk (dram_gclk_c1_r[5]), // Templated
.cmp_gclk (cmp_gclk_c1_r[5]), // Templated
.dram_adbginit_l (dram_adbginit_l),
.dram_arst_l (dram_arst_l),
.jbus_grst_l (jbus_grst_l),
.dram_grst_l (dram_grst_l),
.cmp_grst_l (rpt_cmp_grst_l_c6), // Templated
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_short_chain (ctu_tst_short_chain));
`endif
//
/* scbuf AUTO_TEMPLATE (
.cmp_gclk (cmp_gclk_c0_r[3]),
.arst_l (cmp_arst_l),
.grst_l (rpt_cmp_grst_l_c@"(+ 3 (* 4 (% @ 2)))"),
.gdbginit_l (rpt_cmp_gdbginit_l_c@"(+ 3 (* 4 (% @ 2)))"),
.cluster_cken (rpt_scbuf@_cmp_cken),
.si (par_scan_head[7]),
.so (scbuf0_scdata0_scanout),
.ctu_scbuf\(.*\) (ctu_scbuf@\1[]),
.scbuf_ctu\(.*\) (scbuf@_ctu\1[]),
.dram_scbuf\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_scbuf@\1_buf3[]),
.scbuf_dram\(.*\) (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1[]),
.scdata_scbuf\(.*\) (scdata@_scbuf@\1[]),
.scbuf_scdata\(.*\) (scbuf@_scdata@\1[]),
.sctag_scbuf\(.*\) (sctag@_scbuf@\1_buf[]),
.scbuf_sctag\(.*\) (scbuf@_sctag@\1[]),
.jbi_scbuf\(.*\) (jbi_scbuf@\1_d2_buf1[]),
.scbuf_jbi\(.*\) (scbuf@_jbi\1[]),
.sctag_scdata\(.*\) (sctag@_scdata@\1[]),
.jbi_sctag\(.*\) (jbi_sctag@\1_d2_buf1[]),
); */
//
`ifdef RTL_SCBUF0
scbuf scbuf0
(/*AUTOINST*/
// Outputs
.scbuf_sctag_ev_uerr_r5 (scbuf0_sctag0_ev_uerr_r5), // Templated
.scbuf_sctag_ev_cerr_r5 (scbuf0_sctag0_ev_cerr_r5), // Templated
.scbuf_jbi_ctag_vld (scbuf0_jbi_ctag_vld), // Templated
.scbuf_jbi_data (scbuf0_jbi_data[31:0]), // Templated
.scbuf_jbi_ue_err (scbuf0_jbi_ue_err), // Templated
.scbuf_sctag_rdma_uerr_c10 (scbuf0_sctag0_rdma_uerr_c10), // Templated
.scbuf_sctag_rdma_cerr_c10 (scbuf0_sctag0_rdma_cerr_c10), // Templated
.scbuf_scdata_fbdecc_c4 (scbuf0_scdata0_fbdecc_c4[623:0]), // Templated
.scbuf_dram_data_mecc_r5 (scbuf0_dram02_data_mecc_r5), // Templated
.scbuf_dram_wr_data_r5 (scbuf0_dram02_wr_data_r5[63:0]), // Templated
.scbuf_dram_data_vld_r5 (scbuf0_dram02_data_vld_r5), // Templated
.so (scbuf0_scdata0_scanout), // Templated
// Inputs
.sctag_scbuf_fbrd_en_c3 (sctag0_scbuf0_fbrd_en_c3_buf), // Templated
.sctag_scbuf_fbrd_wl_c3 (sctag0_scbuf0_fbrd_wl_c3_buf[2:0]), // Templated
.sctag_scbuf_fbwr_wen_r2 (sctag0_scbuf0_fbwr_wen_r2_buf[15:0]), // Templated
.sctag_scbuf_fbwr_wl_r2 (sctag0_scbuf0_fbwr_wl_r2_buf[2:0]), // Templated
.sctag_scbuf_fbd_stdatasel_c3 (sctag0_scbuf0_fbd_stdatasel_c3_buf), // Templated
.sctag_scbuf_stdecc_c3 (sctag0_scbuf0_stdecc_c3_buf[77:0]), // Templated
.sctag_scbuf_evict_en_r0 (sctag0_scbuf0_evict_en_r0_buf), // Templated
.sctag_scbuf_wbwr_wen_c6 (sctag0_scbuf0_wbwr_wen_c6_buf[3:0]), // Templated
.sctag_scbuf_wbwr_wl_c6 (sctag0_scbuf0_wbwr_wl_c6_buf[2:0]), // Templated
.sctag_scbuf_wbrd_en_r0 (sctag0_scbuf0_wbrd_en_r0_buf), // Templated
.sctag_scbuf_wbrd_wl_r0 (sctag0_scbuf0_wbrd_wl_r0_buf[2:0]), // Templated
.sctag_scbuf_ev_dword_r0 (sctag0_scbuf0_ev_dword_r0_buf[2:0]), // Templated
.sctag_scbuf_rdma_wren_s2 (sctag0_scbuf0_rdma_wren_s2_buf[15:0]), // Templated
.sctag_scbuf_rdma_wrwl_s2 (sctag0_scbuf0_rdma_wrwl_s2_buf[1:0]), // Templated
.jbi_sctag_req (jbi_sctag0_req_d2_buf1[31:0]), // Templated
.jbi_scbuf_ecc (jbi_scbuf0_ecc_d2_buf1[6:0]), // Templated
.sctag_scbuf_rdma_rden_r0 (sctag0_scbuf0_rdma_rden_r0_buf), // Templated
.sctag_scbuf_rdma_rdwl_r0 (sctag0_scbuf0_rdma_rdwl_r0_buf[1:0]), // Templated
.sctag_scbuf_ctag_en_c7 (sctag0_scbuf0_ctag_en_c7_buf), // Templated
.sctag_scbuf_ctag_c7 (sctag0_scbuf0_ctag_c7_buf[14:0]), // Templated
.sctag_scbuf_req_en_c7 (sctag0_scbuf0_req_en_c7_buf), // Templated
.sctag_scbuf_word_c7 (sctag0_scbuf0_word_c7_buf[3:0]), // Templated
.sctag_scbuf_word_vld_c7 (sctag0_scbuf0_word_vld_c7_buf), // Templated
.scdata_scbuf_decc_out_c7 (scdata0_scbuf0_decc_out_c7[623:0]), // Templated
.dram_scbuf_data_r2 (dram02_scbuf0_data_r2_buf3[127:0]), // Templated
.dram_scbuf_ecc_r2 (dram02_scbuf0_ecc_r2_buf3[27:0]), // Templated
.cmp_gclk (cmp_gclk_c0_r[3]), // Templated
.arst_l (cmp_arst_l), // Templated
.grst_l (rpt_cmp_grst_l_c3), // Templated
.global_shift_enable (global_shift_enable),
.si (par_scan_head[7]), // Templated
.cluster_cken (rpt_scbuf0_cmp_cken), // Templated
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_short_chain (ctu_tst_short_chain));
`endif
//
/* scbuf AUTO_TEMPLATE (
.cmp_gclk (cmp_gclk_c0_r[4]),
.arst_l (cmp_arst_l),
.grst_l (rpt_cmp_grst_l_c3),
.gdbginit_l (rpt_cmp_gdbginit_l_c@"(+ 3 (* 4 (% @ 2)))"),
.cluster_cken (rpt_scbuf@_cmp_cken),
.si (par_scan_head[8]),
.so (scbuf1_scdata1_scanout),
.ctu_scbuf\(.*\) (ctu_scbuf@\1[]),
.scbuf_ctu\(.*\) (scbuf@_ctu\1[]),
.dram_scbuf\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_scbuf@\1_buf3[]),
.scbuf_dram\(.*\) (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1[]),
.scdata_scbuf\(.*\) (scdata@_scbuf@\1[]),
.scbuf_scdata\(.*\) (scbuf@_scdata@\1[]),
.sctag_scbuf\(.*\) (sctag@_scbuf@\1_buf[]),
.scbuf_sctag\(.*\) (scbuf@_sctag@\1[]),
.jbi_scbuf\(.*\) (jbi_scbuf@\1_d2_buf1[]),
.scbuf_jbi\(.*\) (scbuf@_jbi\1[]),
.sctag_scdata\(.*\) (sctag@_scdata@\1[]),
.jbi_sctag\(.*\) (jbi_sctag@\1_d2_buf1[]),
); */
//
`ifdef RTL_SCBUF1
scbuf scbuf1
(/*AUTOINST*/
// Outputs
.scbuf_sctag_ev_uerr_r5 (scbuf1_sctag1_ev_uerr_r5), // Templated
.scbuf_sctag_ev_cerr_r5 (scbuf1_sctag1_ev_cerr_r5), // Templated
.scbuf_jbi_ctag_vld (scbuf1_jbi_ctag_vld), // Templated
.scbuf_jbi_data (scbuf1_jbi_data[31:0]), // Templated
.scbuf_jbi_ue_err (scbuf1_jbi_ue_err), // Templated
.scbuf_sctag_rdma_uerr_c10 (scbuf1_sctag1_rdma_uerr_c10), // Templated
.scbuf_sctag_rdma_cerr_c10 (scbuf1_sctag1_rdma_cerr_c10), // Templated
.scbuf_scdata_fbdecc_c4 (scbuf1_scdata1_fbdecc_c4[623:0]), // Templated
.scbuf_dram_data_mecc_r5 (scbuf1_dram13_data_mecc_r5), // Templated
.scbuf_dram_wr_data_r5 (scbuf1_dram13_wr_data_r5[63:0]), // Templated
.scbuf_dram_data_vld_r5 (scbuf1_dram13_data_vld_r5), // Templated
.so (scbuf1_scdata1_scanout), // Templated
// Inputs
.sctag_scbuf_fbrd_en_c3 (sctag1_scbuf1_fbrd_en_c3_buf), // Templated
.sctag_scbuf_fbrd_wl_c3 (sctag1_scbuf1_fbrd_wl_c3_buf[2:0]), // Templated
.sctag_scbuf_fbwr_wen_r2 (sctag1_scbuf1_fbwr_wen_r2_buf[15:0]), // Templated
.sctag_scbuf_fbwr_wl_r2 (sctag1_scbuf1_fbwr_wl_r2_buf[2:0]), // Templated
.sctag_scbuf_fbd_stdatasel_c3 (sctag1_scbuf1_fbd_stdatasel_c3_buf), // Templated
.sctag_scbuf_stdecc_c3 (sctag1_scbuf1_stdecc_c3_buf[77:0]), // Templated
.sctag_scbuf_evict_en_r0 (sctag1_scbuf1_evict_en_r0_buf), // Templated
.sctag_scbuf_wbwr_wen_c6 (sctag1_scbuf1_wbwr_wen_c6_buf[3:0]), // Templated
.sctag_scbuf_wbwr_wl_c6 (sctag1_scbuf1_wbwr_wl_c6_buf[2:0]), // Templated
.sctag_scbuf_wbrd_en_r0 (sctag1_scbuf1_wbrd_en_r0_buf), // Templated
.sctag_scbuf_wbrd_wl_r0 (sctag1_scbuf1_wbrd_wl_r0_buf[2:0]), // Templated
.sctag_scbuf_ev_dword_r0 (sctag1_scbuf1_ev_dword_r0_buf[2:0]), // Templated
.sctag_scbuf_rdma_wren_s2 (sctag1_scbuf1_rdma_wren_s2_buf[15:0]), // Templated
.sctag_scbuf_rdma_wrwl_s2 (sctag1_scbuf1_rdma_wrwl_s2_buf[1:0]), // Templated
.jbi_sctag_req (jbi_sctag1_req_d2_buf1[31:0]), // Templated
.jbi_scbuf_ecc (jbi_scbuf1_ecc_d2_buf1[6:0]), // Templated
.sctag_scbuf_rdma_rden_r0 (sctag1_scbuf1_rdma_rden_r0_buf), // Templated
.sctag_scbuf_rdma_rdwl_r0 (sctag1_scbuf1_rdma_rdwl_r0_buf[1:0]), // Templated
.sctag_scbuf_ctag_en_c7 (sctag1_scbuf1_ctag_en_c7_buf), // Templated
.sctag_scbuf_ctag_c7 (sctag1_scbuf1_ctag_c7_buf[14:0]), // Templated
.sctag_scbuf_req_en_c7 (sctag1_scbuf1_req_en_c7_buf), // Templated
.sctag_scbuf_word_c7 (sctag1_scbuf1_word_c7_buf[3:0]), // Templated
.sctag_scbuf_word_vld_c7 (sctag1_scbuf1_word_vld_c7_buf), // Templated
.scdata_scbuf_decc_out_c7 (scdata1_scbuf1_decc_out_c7[623:0]), // Templated
.dram_scbuf_data_r2 (dram13_scbuf1_data_r2_buf3[127:0]), // Templated
.dram_scbuf_ecc_r2 (dram13_scbuf1_ecc_r2_buf3[27:0]), // Templated
.cmp_gclk (cmp_gclk_c0_r[4]), // Templated
.arst_l (cmp_arst_l), // Templated
.grst_l (rpt_cmp_grst_l_c3), // Templated
.global_shift_enable (global_shift_enable),
.si (par_scan_head[8]), // Templated
.cluster_cken (rpt_scbuf1_cmp_cken), // Templated
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_short_chain (ctu_tst_short_chain));
`endif
//
/* scbuf AUTO_TEMPLATE (
.cmp_gclk (cmp_gclk_c3_r[3]),
.arst_l (cmp_arst_l),
.grst_l (rpt_cmp_grst_l_c6),
.gdbginit_l (rpt_cmp_gdbginit_l_c@"(+ 3 (* 4 (% @ 2)))"),
.cluster_cken (rpt_scbuf@_cmp_cken),
.si (par_scan_head[23]),
.so (scbuf2_scdata2_scanout),
.ctu_scbuf\(.*\) (ctu_scbuf@\1[]),
.scbuf_ctu\(.*\) (scbuf@_ctu\1[]),
.dram_scbuf\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_scbuf@\1_buf3[]),
.scbuf_dram\(.*\) (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1[]),
.scdata_scbuf\(.*\) (scdata@_scbuf@\1[]),
.scbuf_scdata\(.*\) (scbuf@_scdata@\1[]),
.sctag_scbuf\(.*\) (sctag@_scbuf@\1_buf[]),
.scbuf_sctag\(.*\) (scbuf@_sctag@\1[]),
.jbi_scbuf\(.*\) (jbi_scbuf@\1_d2_buf1[]),
.scbuf_jbi\(.*\) (scbuf@_jbi\1[]),
.sctag_scdata\(.*\) (sctag@_scdata@\1[]),
.jbi_sctag\(.*\) (jbi_sctag@\1_d2_buf1[]),
); */
//
`ifdef RTL_SCBUF2
scbuf scbuf2
(/*AUTOINST*/
// Outputs
.scbuf_sctag_ev_uerr_r5 (scbuf2_sctag2_ev_uerr_r5), // Templated
.scbuf_sctag_ev_cerr_r5 (scbuf2_sctag2_ev_cerr_r5), // Templated
.scbuf_jbi_ctag_vld (scbuf2_jbi_ctag_vld), // Templated
.scbuf_jbi_data (scbuf2_jbi_data[31:0]), // Templated
.scbuf_jbi_ue_err (scbuf2_jbi_ue_err), // Templated
.scbuf_sctag_rdma_uerr_c10 (scbuf2_sctag2_rdma_uerr_c10), // Templated
.scbuf_sctag_rdma_cerr_c10 (scbuf2_sctag2_rdma_cerr_c10), // Templated
.scbuf_scdata_fbdecc_c4 (scbuf2_scdata2_fbdecc_c4[623:0]), // Templated
.scbuf_dram_data_mecc_r5 (scbuf2_dram02_data_mecc_r5), // Templated
.scbuf_dram_wr_data_r5 (scbuf2_dram02_wr_data_r5[63:0]), // Templated
.scbuf_dram_data_vld_r5 (scbuf2_dram02_data_vld_r5), // Templated
.so (scbuf2_scdata2_scanout), // Templated
// Inputs
.sctag_scbuf_fbrd_en_c3 (sctag2_scbuf2_fbrd_en_c3_buf), // Templated
.sctag_scbuf_fbrd_wl_c3 (sctag2_scbuf2_fbrd_wl_c3_buf[2:0]), // Templated
.sctag_scbuf_fbwr_wen_r2 (sctag2_scbuf2_fbwr_wen_r2_buf[15:0]), // Templated
.sctag_scbuf_fbwr_wl_r2 (sctag2_scbuf2_fbwr_wl_r2_buf[2:0]), // Templated
.sctag_scbuf_fbd_stdatasel_c3 (sctag2_scbuf2_fbd_stdatasel_c3_buf), // Templated
.sctag_scbuf_stdecc_c3 (sctag2_scbuf2_stdecc_c3_buf[77:0]), // Templated
.sctag_scbuf_evict_en_r0 (sctag2_scbuf2_evict_en_r0_buf), // Templated
.sctag_scbuf_wbwr_wen_c6 (sctag2_scbuf2_wbwr_wen_c6_buf[3:0]), // Templated
.sctag_scbuf_wbwr_wl_c6 (sctag2_scbuf2_wbwr_wl_c6_buf[2:0]), // Templated
.sctag_scbuf_wbrd_en_r0 (sctag2_scbuf2_wbrd_en_r0_buf), // Templated
.sctag_scbuf_wbrd_wl_r0 (sctag2_scbuf2_wbrd_wl_r0_buf[2:0]), // Templated
.sctag_scbuf_ev_dword_r0 (sctag2_scbuf2_ev_dword_r0_buf[2:0]), // Templated
.sctag_scbuf_rdma_wren_s2 (sctag2_scbuf2_rdma_wren_s2_buf[15:0]), // Templated
.sctag_scbuf_rdma_wrwl_s2 (sctag2_scbuf2_rdma_wrwl_s2_buf[1:0]), // Templated
.jbi_sctag_req (jbi_sctag2_req_d2_buf1[31:0]), // Templated
.jbi_scbuf_ecc (jbi_scbuf2_ecc_d2_buf1[6:0]), // Templated
.sctag_scbuf_rdma_rden_r0 (sctag2_scbuf2_rdma_rden_r0_buf), // Templated
.sctag_scbuf_rdma_rdwl_r0 (sctag2_scbuf2_rdma_rdwl_r0_buf[1:0]), // Templated
.sctag_scbuf_ctag_en_c7 (sctag2_scbuf2_ctag_en_c7_buf), // Templated
.sctag_scbuf_ctag_c7 (sctag2_scbuf2_ctag_c7_buf[14:0]), // Templated
.sctag_scbuf_req_en_c7 (sctag2_scbuf2_req_en_c7_buf), // Templated
.sctag_scbuf_word_c7 (sctag2_scbuf2_word_c7_buf[3:0]), // Templated
.sctag_scbuf_word_vld_c7 (sctag2_scbuf2_word_vld_c7_buf), // Templated
.scdata_scbuf_decc_out_c7 (scdata2_scbuf2_decc_out_c7[623:0]), // Templated
.dram_scbuf_data_r2 (dram02_scbuf2_data_r2_buf3[127:0]), // Templated
.dram_scbuf_ecc_r2 (dram02_scbuf2_ecc_r2_buf3[27:0]), // Templated
.cmp_gclk (cmp_gclk_c3_r[3]), // Templated
.arst_l (cmp_arst_l), // Templated
.grst_l (rpt_cmp_grst_l_c6), // Templated
.global_shift_enable (global_shift_enable),
.si (par_scan_head[23]), // Templated
.cluster_cken (rpt_scbuf2_cmp_cken), // Templated
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_short_chain (ctu_tst_short_chain));
`endif
//
/* scbuf AUTO_TEMPLATE (
.cmp_gclk (cmp_gclk_c3_r[4]),
.arst_l (cmp_arst_l),
.grst_l (rpt_cmp_grst_l_c6),
.gdbginit_l (rpt_cmp_gdbginit_l_c@"(+ 3 (* 4 (% @ 2)))"),
.cluster_cken (rpt_scbuf@_cmp_cken),
.si (par_scan_head[22]),
.so (scbuf3_scdata3_scanout),
.ctu_scbuf\(.*\) (ctu_scbuf@\1[]),
.scbuf_ctu\(.*\) (scbuf@_ctu\1[]),
.dram_scbuf\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_scbuf@\1_buf3[]),
.scbuf_dram\(.*\) (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1[]),
.scdata_scbuf\(.*\) (scdata@_scbuf@\1[]),
.scbuf_scdata\(.*\) (scbuf@_scdata@\1[]),
.sctag_scbuf\(.*\) (sctag@_scbuf@\1_buf[]),
.scbuf_sctag\(.*\) (scbuf@_sctag@\1[]),
.jbi_scbuf\(.*\) (jbi_scbuf@\1_d2_buf1[]),
.scbuf_jbi\(.*\) (scbuf@_jbi\1[]),
.sctag_scdata\(.*\) (sctag@_scdata@\1[]),
.jbi_sctag\(.*\) (jbi_sctag@\1_d2_buf1[]),
); */
//
`ifdef RTL_SCBUF3
scbuf scbuf3
(/*AUTOINST*/
// Outputs
.scbuf_sctag_ev_uerr_r5 (scbuf3_sctag3_ev_uerr_r5), // Templated
.scbuf_sctag_ev_cerr_r5 (scbuf3_sctag3_ev_cerr_r5), // Templated
.scbuf_jbi_ctag_vld (scbuf3_jbi_ctag_vld), // Templated
.scbuf_jbi_data (scbuf3_jbi_data[31:0]), // Templated
.scbuf_jbi_ue_err (scbuf3_jbi_ue_err), // Templated
.scbuf_sctag_rdma_uerr_c10 (scbuf3_sctag3_rdma_uerr_c10), // Templated
.scbuf_sctag_rdma_cerr_c10 (scbuf3_sctag3_rdma_cerr_c10), // Templated
.scbuf_scdata_fbdecc_c4 (scbuf3_scdata3_fbdecc_c4[623:0]), // Templated
.scbuf_dram_data_mecc_r5 (scbuf3_dram13_data_mecc_r5), // Templated
.scbuf_dram_wr_data_r5 (scbuf3_dram13_wr_data_r5[63:0]), // Templated
.scbuf_dram_data_vld_r5 (scbuf3_dram13_data_vld_r5), // Templated
.so (scbuf3_scdata3_scanout), // Templated
// Inputs
.sctag_scbuf_fbrd_en_c3 (sctag3_scbuf3_fbrd_en_c3_buf), // Templated
.sctag_scbuf_fbrd_wl_c3 (sctag3_scbuf3_fbrd_wl_c3_buf[2:0]), // Templated
.sctag_scbuf_fbwr_wen_r2 (sctag3_scbuf3_fbwr_wen_r2_buf[15:0]), // Templated
.sctag_scbuf_fbwr_wl_r2 (sctag3_scbuf3_fbwr_wl_r2_buf[2:0]), // Templated
.sctag_scbuf_fbd_stdatasel_c3 (sctag3_scbuf3_fbd_stdatasel_c3_buf), // Templated
.sctag_scbuf_stdecc_c3 (sctag3_scbuf3_stdecc_c3_buf[77:0]), // Templated
.sctag_scbuf_evict_en_r0 (sctag3_scbuf3_evict_en_r0_buf), // Templated
.sctag_scbuf_wbwr_wen_c6 (sctag3_scbuf3_wbwr_wen_c6_buf[3:0]), // Templated
.sctag_scbuf_wbwr_wl_c6 (sctag3_scbuf3_wbwr_wl_c6_buf[2:0]), // Templated
.sctag_scbuf_wbrd_en_r0 (sctag3_scbuf3_wbrd_en_r0_buf), // Templated
.sctag_scbuf_wbrd_wl_r0 (sctag3_scbuf3_wbrd_wl_r0_buf[2:0]), // Templated
.sctag_scbuf_ev_dword_r0 (sctag3_scbuf3_ev_dword_r0_buf[2:0]), // Templated
.sctag_scbuf_rdma_wren_s2 (sctag3_scbuf3_rdma_wren_s2_buf[15:0]), // Templated
.sctag_scbuf_rdma_wrwl_s2 (sctag3_scbuf3_rdma_wrwl_s2_buf[1:0]), // Templated
.jbi_sctag_req (jbi_sctag3_req_d2_buf1[31:0]), // Templated
.jbi_scbuf_ecc (jbi_scbuf3_ecc_d2_buf1[6:0]), // Templated
.sctag_scbuf_rdma_rden_r0 (sctag3_scbuf3_rdma_rden_r0_buf), // Templated
.sctag_scbuf_rdma_rdwl_r0 (sctag3_scbuf3_rdma_rdwl_r0_buf[1:0]), // Templated
.sctag_scbuf_ctag_en_c7 (sctag3_scbuf3_ctag_en_c7_buf), // Templated
.sctag_scbuf_ctag_c7 (sctag3_scbuf3_ctag_c7_buf[14:0]), // Templated
.sctag_scbuf_req_en_c7 (sctag3_scbuf3_req_en_c7_buf), // Templated
.sctag_scbuf_word_c7 (sctag3_scbuf3_word_c7_buf[3:0]), // Templated
.sctag_scbuf_word_vld_c7 (sctag3_scbuf3_word_vld_c7_buf), // Templated
.scdata_scbuf_decc_out_c7 (scdata3_scbuf3_decc_out_c7[623:0]), // Templated
.dram_scbuf_data_r2 (dram13_scbuf3_data_r2_buf3[127:0]), // Templated
.dram_scbuf_ecc_r2 (dram13_scbuf3_ecc_r2_buf3[27:0]), // Templated
.cmp_gclk (cmp_gclk_c3_r[4]), // Templated
.arst_l (cmp_arst_l), // Templated
.grst_l (rpt_cmp_grst_l_c6), // Templated
.global_shift_enable (global_shift_enable),
.si (par_scan_head[22]), // Templated
.cluster_cken (rpt_scbuf3_cmp_cken), // Templated
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_short_chain (ctu_tst_short_chain));
`endif
//
/* scdata AUTO_TEMPLATE (
.cmp_gclk ({cmp_gclk_c0_r[1],cmp_gclk_c0_r[2]}),
.arst_l (cmp_arst_l),
.grst_l (rpt_cmp_grst_l_c@"(+ 1 (% @ 2) (* 4 (/ @ 2)))"),
.gdbginit_l (rpt_cmp_gdbginit_l_c@"(+ 1 (% @ 2) (* 4 (/ @ 2)))"),
.cluster_cken (rpt_scdata@_cmp_cken),
.si (scbuf0_scdata0_scanout),
.so (par_scan_tail[7]),
.efc_scdata_fuse_ashift (efc_scdata@_fuse_ashift),
.efc_scdata_fuse_dshift (efc_scdata@_fuse_dshift),
.efc_scdata\(.*\) (efc_scdata@"(% @ 2)"@"(+ (% @ 2) 2)"\1),
.scdata_efc\(.*\) (scdata@_efc\1),
.ctu_scdata\(.*\) (ctu_scdata@\1[]),
.scdata_ctu\(.*\) (scdata@_ctu\1[]),
.scbuf_scdata\(.*\) (scbuf@_scdata@\1[]),
.scdata_scbuf\(.*\) (scdata@_scbuf@\1[]),
.sctag_scdata\(.*\) (sctag@_scdata@\1[]),
.scdata_sctag\(.*\) (scdata@_sctag@\1[]),
); */
//
`ifdef RTL_SCDATA0
scdata scdata0
(/*AUTOINST*/
// Outputs
.so (par_scan_tail[7]), // Templated
.scdata_efc_fuse_data (scdata0_efc_fuse_data), // Templated
.scdata_scbuf_decc_out_c7 (scdata0_scbuf0_decc_out_c7[623:0]), // Templated
.scdata_sctag_decc_c6 (scdata0_sctag0_decc_c6[155:0]), // Templated
// Inputs
.cmp_gclk ({cmp_gclk_c0_r[1],cmp_gclk_c0_r[2]}), // Templated
.global_shift_enable (global_shift_enable),
.si (scbuf0_scdata0_scanout), // Templated
.arst_l (cmp_arst_l), // Templated
.grst_l (rpt_cmp_grst_l_c1), // Templated
.cluster_cken (rpt_scdata0_cmp_cken), // Templated
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_short_chain (ctu_tst_short_chain),
.efc_scdata_fuse_ashift (efc_scdata0_fuse_ashift), // Templated
.efc_scdata_fuse_clk1 (efc_scdata02_fuse_clk1), // Templated
.efc_scdata_fuse_clk2 (efc_scdata02_fuse_clk2), // Templated
.efc_scdata_fuse_data (efc_scdata02_fuse_data), // Templated
.efc_scdata_fuse_dshift (efc_scdata0_fuse_dshift), // Templated
.scbuf_scdata_fbdecc_c4 (scbuf0_scdata0_fbdecc_c4[623:0]), // Templated
.sctag_scdata_col_offset_c2 (sctag0_scdata0_col_offset_c2[3:0]), // Templated
.sctag_scdata_fb_hit_c3 (sctag0_scdata0_fb_hit_c3), // Templated
.sctag_scdata_fbrd_c3 (sctag0_scdata0_fbrd_c3), // Templated
.sctag_scdata_rd_wr_c2 (sctag0_scdata0_rd_wr_c2), // Templated
.sctag_scdata_set_c2 (sctag0_scdata0_set_c2[9:0]), // Templated
.sctag_scdata_stdecc_c2 (sctag0_scdata0_stdecc_c2[77:0]), // Templated
.sctag_scdata_way_sel_c2 (sctag0_scdata0_way_sel_c2[11:0]), // Templated
.sctag_scdata_word_en_c2 (sctag0_scdata0_word_en_c2[15:0])); // Templated
`endif
//
/* scdata AUTO_TEMPLATE (
.cmp_gclk ({cmp_gclk_c0_r[6],cmp_gclk_c0_r[5]}),
.arst_l (cmp_arst_l),
.grst_l (rpt_cmp_grst_l_c4),
.gdbginit_l (rpt_cmp_gdbginit_l_c@"(+ 1 (% @ 2) (* 4 (/ @ 2)))"),
.cluster_cken (rpt_scdata@_cmp_cken),
.si (scbuf1_scdata1_scanout),
.so (par_scan_tail[8]),
.efc_scdata_fuse_ashift (efc_scdata@_fuse_ashift),
.efc_scdata_fuse_dshift (efc_scdata@_fuse_dshift),
.efc_scdata\(.*\) (efc_scdata@"(% @ 2)"@"(+ (% @ 2) 2)"\1),
.scdata_efc\(.*\) (scdata@_efc\1),
.ctu_scdata\(.*\) (ctu_scdata@\1[]),
.scdata_ctu\(.*\) (scdata@_ctu\1[]),
.scbuf_scdata\(.*\) (scbuf@_scdata@\1[]),
.scdata_scbuf\(.*\) (scdata@_scbuf@\1[]),
.sctag_scdata\(.*\) (sctag@_scdata@\1[]),
.scdata_sctag\(.*\) (scdata@_sctag@\1[]),
); */
//
`ifdef RTL_SCDATA1
scdata scdata1
(/*AUTOINST*/
// Outputs
.so (par_scan_tail[8]), // Templated
.scdata_efc_fuse_data (scdata1_efc_fuse_data), // Templated
.scdata_scbuf_decc_out_c7 (scdata1_scbuf1_decc_out_c7[623:0]), // Templated
.scdata_sctag_decc_c6 (scdata1_sctag1_decc_c6[155:0]), // Templated
// Inputs
.cmp_gclk ({cmp_gclk_c0_r[6],cmp_gclk_c0_r[5]}), // Templated
.global_shift_enable (global_shift_enable),
.si (scbuf1_scdata1_scanout), // Templated
.arst_l (cmp_arst_l), // Templated
.grst_l (rpt_cmp_grst_l_c4), // Templated
.cluster_cken (rpt_scdata1_cmp_cken), // Templated
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_short_chain (ctu_tst_short_chain),
.efc_scdata_fuse_ashift (efc_scdata1_fuse_ashift), // Templated
.efc_scdata_fuse_clk1 (efc_scdata13_fuse_clk1), // Templated
.efc_scdata_fuse_clk2 (efc_scdata13_fuse_clk2), // Templated
.efc_scdata_fuse_data (efc_scdata13_fuse_data), // Templated
.efc_scdata_fuse_dshift (efc_scdata1_fuse_dshift), // Templated
.scbuf_scdata_fbdecc_c4 (scbuf1_scdata1_fbdecc_c4[623:0]), // Templated
.sctag_scdata_col_offset_c2 (sctag1_scdata1_col_offset_c2[3:0]), // Templated
.sctag_scdata_fb_hit_c3 (sctag1_scdata1_fb_hit_c3), // Templated
.sctag_scdata_fbrd_c3 (sctag1_scdata1_fbrd_c3), // Templated
.sctag_scdata_rd_wr_c2 (sctag1_scdata1_rd_wr_c2), // Templated
.sctag_scdata_set_c2 (sctag1_scdata1_set_c2[9:0]), // Templated
.sctag_scdata_stdecc_c2 (sctag1_scdata1_stdecc_c2[77:0]), // Templated
.sctag_scdata_way_sel_c2 (sctag1_scdata1_way_sel_c2[11:0]), // Templated
.sctag_scdata_word_en_c2 (sctag1_scdata1_word_en_c2[15:0])); // Templated
`endif
//
/* scdata AUTO_TEMPLATE (
.cmp_gclk ({cmp_gclk_c3_r[1],cmp_gclk_c3_r[2]}),
.arst_l (cmp_arst_l),
.grst_l (rpt_cmp_grst_l_c2),
.gdbginit_l (rpt_cmp_gdbginit_l_c@"(+ 1 (% @ 2) (* 4 (/ @ 2)))"),
.cluster_cken (rpt_scdata@_cmp_cken),
.si (scbuf2_scdata2_scanout),
.so (par_scan_tail[23]),
.efc_scdata_fuse_ashift (efc_scdata@_fuse_ashift),
.efc_scdata_fuse_dshift (efc_scdata@_fuse_dshift),
.efc_scdata\(.*\) (efc_scdata@"(% @ 2)"@"(+ (% @ 2) 2)"\1),
.scdata_efc\(.*\) (scdata@_efc\1),
.ctu_scdata\(.*\) (ctu_scdata@\1[]),
.scdata_ctu\(.*\) (scdata@_ctu\1[]),
.scbuf_scdata\(.*\) (scbuf@_scdata@\1[]),
.scdata_scbuf\(.*\) (scdata@_scbuf@\1[]),
.sctag_scdata\(.*\) (sctag@_scdata@\1[]),
.scdata_sctag\(.*\) (scdata@_sctag@\1[]),
); */
//
`ifdef RTL_SCDATA2
scdata scdata2
(/*AUTOINST*/
// Outputs
.so (par_scan_tail[23]), // Templated
.scdata_efc_fuse_data (scdata2_efc_fuse_data), // Templated
.scdata_scbuf_decc_out_c7 (scdata2_scbuf2_decc_out_c7[623:0]), // Templated
.scdata_sctag_decc_c6 (scdata2_sctag2_decc_c6[155:0]), // Templated
// Inputs
.cmp_gclk ({cmp_gclk_c3_r[1],cmp_gclk_c3_r[2]}), // Templated
.global_shift_enable (global_shift_enable),
.si (scbuf2_scdata2_scanout), // Templated
.arst_l (cmp_arst_l), // Templated
.grst_l (rpt_cmp_grst_l_c2), // Templated
.cluster_cken (rpt_scdata2_cmp_cken), // Templated
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_short_chain (ctu_tst_short_chain),
.efc_scdata_fuse_ashift (efc_scdata2_fuse_ashift), // Templated
.efc_scdata_fuse_clk1 (efc_scdata02_fuse_clk1), // Templated
.efc_scdata_fuse_clk2 (efc_scdata02_fuse_clk2), // Templated
.efc_scdata_fuse_data (efc_scdata02_fuse_data), // Templated
.efc_scdata_fuse_dshift (efc_scdata2_fuse_dshift), // Templated
.scbuf_scdata_fbdecc_c4 (scbuf2_scdata2_fbdecc_c4[623:0]), // Templated
.sctag_scdata_col_offset_c2 (sctag2_scdata2_col_offset_c2[3:0]), // Templated
.sctag_scdata_fb_hit_c3 (sctag2_scdata2_fb_hit_c3), // Templated
.sctag_scdata_fbrd_c3 (sctag2_scdata2_fbrd_c3), // Templated
.sctag_scdata_rd_wr_c2 (sctag2_scdata2_rd_wr_c2), // Templated
.sctag_scdata_set_c2 (sctag2_scdata2_set_c2[9:0]), // Templated
.sctag_scdata_stdecc_c2 (sctag2_scdata2_stdecc_c2[77:0]), // Templated
.sctag_scdata_way_sel_c2 (sctag2_scdata2_way_sel_c2[11:0]), // Templated
.sctag_scdata_word_en_c2 (sctag2_scdata2_word_en_c2[15:0])); // Templated
`endif
//
/* scdata AUTO_TEMPLATE (
.cmp_gclk ({cmp_gclk_c3_r[6],cmp_gclk_c3_r[5]}),
.arst_l (cmp_arst_l),
.grst_l (rpt_cmp_grst_l_c7),
.gdbginit_l (rpt_cmp_gdbginit_l_c@"(+ 1 (% @ 2) (* 4 (/ @ 2)))"),
.cluster_cken (rpt_scdata@_cmp_cken),
.si (scbuf3_scdata3_scanout),
.so (par_scan_tail[22]),
.efc_scdata_fuse_ashift (efc_scdata@_fuse_ashift),
.efc_scdata_fuse_dshift (efc_scdata@_fuse_dshift),
.efc_scdata\(.*\) (efc_scdata@"(% @ 2)"@"(+ (% @ 2) 2)"\1),
.scdata_efc\(.*\) (scdata@_efc\1),
.ctu_scdata\(.*\) (ctu_scdata@\1[]),
.scdata_ctu\(.*\) (scdata@_ctu\1[]),
.scbuf_scdata\(.*\) (scbuf@_scdata@\1[]),
.scdata_scbuf\(.*\) (scdata@_scbuf@\1[]),
.sctag_scdata\(.*\) (sctag@_scdata@\1[]),
.scdata_sctag\(.*\) (scdata@_sctag@\1[]),
); */
//
`ifdef RTL_SCDATA3
scdata scdata3
(/*AUTOINST*/
// Outputs
.so (par_scan_tail[22]), // Templated
.scdata_efc_fuse_data (scdata3_efc_fuse_data), // Templated
.scdata_scbuf_decc_out_c7 (scdata3_scbuf3_decc_out_c7[623:0]), // Templated
.scdata_sctag_decc_c6 (scdata3_sctag3_decc_c6[155:0]), // Templated
// Inputs
.cmp_gclk ({cmp_gclk_c3_r[6],cmp_gclk_c3_r[5]}), // Templated
.global_shift_enable (global_shift_enable),
.si (scbuf3_scdata3_scanout), // Templated
.arst_l (cmp_arst_l), // Templated
.grst_l (rpt_cmp_grst_l_c7), // Templated
.cluster_cken (rpt_scdata3_cmp_cken), // Templated
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_short_chain (ctu_tst_short_chain),
.efc_scdata_fuse_ashift (efc_scdata3_fuse_ashift), // Templated
.efc_scdata_fuse_clk1 (efc_scdata13_fuse_clk1), // Templated
.efc_scdata_fuse_clk2 (efc_scdata13_fuse_clk2), // Templated
.efc_scdata_fuse_data (efc_scdata13_fuse_data), // Templated
.efc_scdata_fuse_dshift (efc_scdata3_fuse_dshift), // Templated
.scbuf_scdata_fbdecc_c4 (scbuf3_scdata3_fbdecc_c4[623:0]), // Templated
.sctag_scdata_col_offset_c2 (sctag3_scdata3_col_offset_c2[3:0]), // Templated
.sctag_scdata_fb_hit_c3 (sctag3_scdata3_fb_hit_c3), // Templated
.sctag_scdata_fbrd_c3 (sctag3_scdata3_fbrd_c3), // Templated
.sctag_scdata_rd_wr_c2 (sctag3_scdata3_rd_wr_c2), // Templated
.sctag_scdata_set_c2 (sctag3_scdata3_set_c2[9:0]), // Templated
.sctag_scdata_stdecc_c2 (sctag3_scdata3_stdecc_c2[77:0]), // Templated
.sctag_scdata_way_sel_c2 (sctag3_scdata3_way_sel_c2[11:0]), // Templated
.sctag_scdata_word_en_c2 (sctag3_scdata3_word_en_c2[15:0])); // Templated
`endif
//
/* sctag AUTO_TEMPLATE (
.cmp_gclk (cmp_gclk_c1_r[2]),
.arst_l (cmp_arst_l),
.adbginit_l (cmp_adbginit_l),
.grst_l (rpt_cmp_grst_l_c@"(+ 1 (% @ 2) (* 4 (/ @ 2)))"),
.gdbginit_l (rpt_cmp_gdbginit_l_c@"(+ 1 (% @ 2) (* 4 (/ @ 2)))"),
.cluster_cken (rpt_sctag@_cmp_cken),
.sctag_dbgbus_out (sctag@_dbgbus_out[]),
.efc_sctag_fuse_ashift (efc_sctag@_fuse_ashift),
.efc_sctag_fuse_dshift (efc_sctag@_fuse_dshift),
.efc_sctag_fuse_\(.*\) (efc_sctag@"(% @ 2)"@"(+ (% @ 2) 2)"_fuse_\1),
.sctag_efc_fuse_data (sctag@_efc_fuse_data),
.ctu_sctag_scanin (par_scan_head[5]),
.sctag_ctu_scanout (par_scan_tail[5]),
.sctag_scbuf_scanout (),
.scdata_sctag_scanout (1'b0),
.sctag_scbuf\(.*\) (sctag@_scbuf@\1[]),
.scbuf_sctag\(.*\) (scbuf@_sctag@\1_buf[]),
.sctag_scdata\(.*\) (sctag@_scdata@\1[]),
.scdata_sctag\(.*\) (scdata@_sctag@\1[]),
.sctag_dram\(.*\) (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1[]),
.dram_sctag\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_sctag@\1_buf2[]),
.sctag_jbi\(.*\) (sctag@_jbi\1[]),
.jbi_sctag\(.*\) (jbi_sctag@\1_d2[]),
.sctag_cpx\(.*\) (sctag@_cpx\1[]),
.sctag_pcx\(.*\) (sctag@_pcx\1[]),
.cpx_sctag\(.*\) (cpx_sctag@\1_buf[]),
.pcx_sctag\(.*\) (pcx_sctag@\1_buf[]),
.sctag_ctu_mbistdone (sctag@_ctu_mbistdone),
.sctag_ctu_mbisterr (sctag@_ctu_mbisterr),
.sctag_ctu\(.*\) (sctag@_ctu\1[]),
.ctu_sctag_mbisten (ctu_sctag@_mbisten_buf2),
.ctu_sctag\(.*\) (ctu_sctag@\1[]),
.sctag_clk_tr (sctag@_ctu_tr),
); */
//
`ifdef RTL_SCTAG0
sctag sctag0
(/*AUTOINST*/
// Outputs
.sctag_cpx_req_cq (sctag0_cpx_req_cq[7:0]), // Templated
.sctag_cpx_atom_cq (sctag0_cpx_atom_cq), // Templated
.sctag_cpx_data_ca (sctag0_cpx_data_ca[`CPX_WIDTH-1:0]), // Templated
.sctag_pcx_stall_pq (sctag0_pcx_stall_pq), // Templated
.sctag_jbi_por_req (sctag0_jbi_por_req), // Templated
.sctag_scdata_way_sel_c2 (sctag0_scdata0_way_sel_c2[11:0]), // Templated
.sctag_scdata_rd_wr_c2 (sctag0_scdata0_rd_wr_c2), // Templated
.sctag_scdata_set_c2 (sctag0_scdata0_set_c2[9:0]), // Templated
.sctag_scdata_col_offset_c2 (sctag0_scdata0_col_offset_c2[3:0]), // Templated
.sctag_scdata_word_en_c2 (sctag0_scdata0_word_en_c2[15:0]), // Templated
.sctag_scdata_fbrd_c3 (sctag0_scdata0_fbrd_c3), // Templated
.sctag_scdata_fb_hit_c3 (sctag0_scdata0_fb_hit_c3), // Templated
.sctag_scdata_stdecc_c2 (sctag0_scdata0_stdecc_c2[77:0]), // Templated
.sctag_scbuf_stdecc_c3 (sctag0_scbuf0_stdecc_c3[77:0]), // Templated
.sctag_scbuf_fbrd_en_c3 (sctag0_scbuf0_fbrd_en_c3), // Templated
.sctag_scbuf_fbrd_wl_c3 (sctag0_scbuf0_fbrd_wl_c3[2:0]), // Templated
.sctag_scbuf_fbwr_wen_r2 (sctag0_scbuf0_fbwr_wen_r2[15:0]), // Templated
.sctag_scbuf_fbwr_wl_r2 (sctag0_scbuf0_fbwr_wl_r2[2:0]), // Templated
.sctag_scbuf_fbd_stdatasel_c3 (sctag0_scbuf0_fbd_stdatasel_c3), // Templated
.sctag_scbuf_wbwr_wen_c6 (sctag0_scbuf0_wbwr_wen_c6[3:0]), // Templated
.sctag_scbuf_wbwr_wl_c6 (sctag0_scbuf0_wbwr_wl_c6[2:0]), // Templated
.sctag_scbuf_wbrd_en_r0 (sctag0_scbuf0_wbrd_en_r0), // Templated
.sctag_scbuf_wbrd_wl_r0 (sctag0_scbuf0_wbrd_wl_r0[2:0]), // Templated
.sctag_scbuf_ev_dword_r0 (sctag0_scbuf0_ev_dword_r0[2:0]), // Templated
.sctag_scbuf_evict_en_r0 (sctag0_scbuf0_evict_en_r0), // Templated
.sctag_scbuf_rdma_wren_s2 (sctag0_scbuf0_rdma_wren_s2[15:0]), // Templated
.sctag_scbuf_rdma_wrwl_s2 (sctag0_scbuf0_rdma_wrwl_s2[1:0]), // Templated
.sctag_scbuf_rdma_rdwl_r0 (sctag0_scbuf0_rdma_rdwl_r0[1:0]), // Templated
.sctag_scbuf_rdma_rden_r0 (sctag0_scbuf0_rdma_rden_r0), // Templated
.sctag_scbuf_ctag_en_c7 (sctag0_scbuf0_ctag_en_c7), // Templated
.sctag_scbuf_ctag_c7 (sctag0_scbuf0_ctag_c7[14:0]), // Templated
.sctag_scbuf_word_c7 (sctag0_scbuf0_word_c7[3:0]), // Templated
.sctag_scbuf_req_en_c7 (sctag0_scbuf0_req_en_c7), // Templated
.sctag_scbuf_word_vld_c7 (sctag0_scbuf0_word_vld_c7), // Templated
.sctag_dram_rd_req (sctag0_dram02_rd_req), // Templated
.sctag_dram_rd_dummy_req (sctag0_dram02_rd_dummy_req), // Templated
.sctag_dram_rd_req_id (sctag0_dram02_rd_req_id[2:0]), // Templated
.sctag_dram_addr (sctag0_dram02_addr[39:5]), // Templated
.sctag_dram_wr_req (sctag0_dram02_wr_req), // Templated
.sctag_jbi_iq_dequeue (sctag0_jbi_iq_dequeue), // Templated
.sctag_jbi_wib_dequeue (sctag0_jbi_wib_dequeue), // Templated
.sctag_dbgbus_out (sctag0_dbgbus_out[40:0]), // Templated
.sctag_clk_tr (sctag0_ctu_tr), // Templated
.sctag_ctu_mbistdone (sctag0_ctu_mbistdone), // Templated
.sctag_ctu_mbisterr (sctag0_ctu_mbisterr), // Templated
.sctag_ctu_scanout (par_scan_tail[5]), // Templated
.sctag_scbuf_scanout (), // Templated
.sctag_efc_fuse_data (sctag0_efc_fuse_data), // Templated
// Inputs
.pcx_sctag_data_rdy_px1 (pcx_sctag0_data_rdy_px1_buf), // Templated
.pcx_sctag_data_px2 (pcx_sctag0_data_px2_buf[`PCX_WIDTH-1:0]), // Templated
.pcx_sctag_atm_px1 (pcx_sctag0_atm_px1_buf), // Templated
.cpx_sctag_grant_cx (cpx_sctag0_grant_cx_buf[7:0]), // Templated
.scdata_sctag_decc_c6 (scdata0_sctag0_decc_c6[155:0]), // Templated
.scbuf_sctag_ev_uerr_r5 (scbuf0_sctag0_ev_uerr_r5_buf), // Templated
.scbuf_sctag_ev_cerr_r5 (scbuf0_sctag0_ev_cerr_r5_buf), // Templated
.scbuf_sctag_rdma_uerr_c10 (scbuf0_sctag0_rdma_uerr_c10_buf), // Templated
.scbuf_sctag_rdma_cerr_c10 (scbuf0_sctag0_rdma_cerr_c10_buf), // Templated
.dram_sctag_rd_ack (dram02_sctag0_rd_ack_buf2), // Templated
.dram_sctag_wr_ack (dram02_sctag0_wr_ack_buf2), // Templated
.dram_sctag_chunk_id_r0 (dram02_sctag0_chunk_id_r0_buf2[1:0]), // Templated
.dram_sctag_data_vld_r0 (dram02_sctag0_data_vld_r0_buf2), // Templated
.dram_sctag_rd_req_id_r0 (dram02_sctag0_rd_req_id_r0_buf2[2:0]), // Templated
.dram_sctag_secc_err_r2 (dram02_sctag0_secc_err_r2_buf2), // Templated
.dram_sctag_mecc_err_r2 (dram02_sctag0_mecc_err_r2_buf2), // Templated
.dram_sctag_scb_mecc_err (dram02_sctag0_scb_mecc_err_buf2), // Templated
.dram_sctag_scb_secc_err (dram02_sctag0_scb_secc_err_buf2), // Templated
.jbi_sctag_req_vld (jbi_sctag0_req_vld_d2), // Templated
.jbi_sctag_req (jbi_sctag0_req_d2[31:0]), // Templated
.arst_l (cmp_arst_l), // Templated
.grst_l (rpt_cmp_grst_l_c1), // Templated
.adbginit_l (cmp_adbginit_l), // Templated
.gdbginit_l (rpt_cmp_gdbginit_l_c1), // Templated
.cluster_cken (rpt_sctag0_cmp_cken), // Templated
.cmp_gclk (cmp_gclk_c1_r[2]), // Templated
.global_shift_enable (global_shift_enable),
.ctu_sctag_mbisten (ctu_sctag0_mbisten_buf2), // Templated
.ctu_sctag_scanin (par_scan_head[5]), // Templated
.scdata_sctag_scanout (1'b0), // Templated
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_short_chain (ctu_tst_short_chain),
.efc_sctag_fuse_clk1 (efc_sctag02_fuse_clk1), // Templated
.efc_sctag_fuse_clk2 (efc_sctag02_fuse_clk2), // Templated
.efc_sctag_fuse_ashift (efc_sctag0_fuse_ashift), // Templated
.efc_sctag_fuse_dshift (efc_sctag0_fuse_dshift), // Templated
.efc_sctag_fuse_data (efc_sctag02_fuse_data)); // Templated
`endif
//
/* sctag AUTO_TEMPLATE (
.cmp_gclk (cmp_gclk_c1_r[4]),
.arst_l (cmp_arst_l),
.adbginit_l (cmp_adbginit_l),
.grst_l (rpt_cmp_grst_l_c4),
.gdbginit_l (rpt_cmp_gdbginit_l_c4),
.cluster_cken (rpt_sctag@_cmp_cken),
.sctag_dbgbus_out (sctag@_dbgbus_out[]),
.efc_sctag_fuse_ashift (efc_sctag@_fuse_ashift),
.efc_sctag_fuse_dshift (efc_sctag@_fuse_dshift),
.efc_sctag_fuse_\(.*\) (efc_sctag@"(% @ 2)"@"(+ (% @ 2) 2)"_fuse_\1),
.sctag_efc_fuse_data (sctag@_efc_fuse_data),
.ctu_sctag_scanin (par_scan_head[9]),
.sctag_ctu_scanout (par_scan_tail[9]),
.sctag_scbuf_scanout (),
.scdata_sctag_scanout (1'b0),
.sctag_scbuf\(.*\) (sctag@_scbuf@\1[]),
.scbuf_sctag\(.*\) (scbuf@_sctag@\1_buf[]),
.sctag_scdata\(.*\) (sctag@_scdata@\1[]),
.scdata_sctag\(.*\) (scdata@_sctag@\1[]),
.sctag_dram\(.*\) (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1[]),
.dram_sctag\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_sctag@\1_buf2[]),
.sctag_jbi\(.*\) (sctag@_jbi\1[]),
.jbi_sctag\(.*\) (jbi_sctag@\1_d2[]),
.sctag_cpx\(.*\) (sctag@_cpx\1[]),
.sctag_pcx\(.*\) (sctag@_pcx\1[]),
.cpx_sctag\(.*\) (cpx_sctag@\1_buf[]),
.pcx_sctag\(.*\) (pcx_sctag@\1_buf[]),
.sctag_ctu_mbistdone (sctag@_ctu_mbistdone),
.sctag_ctu_mbisterr (sctag@_ctu_mbisterr),
.sctag_ctu\(.*\) (sctag@_ctu\1[]),
.ctu_sctag_mbisten (ctu_sctag@_mbisten_buf2),
.ctu_sctag\(.*\) (ctu_sctag@\1[]),
.sctag_clk_tr (sctag@_ctu_tr),
); */
//
`ifdef RTL_SCTAG1
sctag sctag1
(/*AUTOINST*/
// Outputs
.sctag_cpx_req_cq (sctag1_cpx_req_cq[7:0]), // Templated
.sctag_cpx_atom_cq (sctag1_cpx_atom_cq), // Templated
.sctag_cpx_data_ca (sctag1_cpx_data_ca[`CPX_WIDTH-1:0]), // Templated
.sctag_pcx_stall_pq (sctag1_pcx_stall_pq), // Templated
.sctag_jbi_por_req (sctag1_jbi_por_req), // Templated
.sctag_scdata_way_sel_c2 (sctag1_scdata1_way_sel_c2[11:0]), // Templated
.sctag_scdata_rd_wr_c2 (sctag1_scdata1_rd_wr_c2), // Templated
.sctag_scdata_set_c2 (sctag1_scdata1_set_c2[9:0]), // Templated
.sctag_scdata_col_offset_c2 (sctag1_scdata1_col_offset_c2[3:0]), // Templated
.sctag_scdata_word_en_c2 (sctag1_scdata1_word_en_c2[15:0]), // Templated
.sctag_scdata_fbrd_c3 (sctag1_scdata1_fbrd_c3), // Templated
.sctag_scdata_fb_hit_c3 (sctag1_scdata1_fb_hit_c3), // Templated
.sctag_scdata_stdecc_c2 (sctag1_scdata1_stdecc_c2[77:0]), // Templated
.sctag_scbuf_stdecc_c3 (sctag1_scbuf1_stdecc_c3[77:0]), // Templated
.sctag_scbuf_fbrd_en_c3 (sctag1_scbuf1_fbrd_en_c3), // Templated
.sctag_scbuf_fbrd_wl_c3 (sctag1_scbuf1_fbrd_wl_c3[2:0]), // Templated
.sctag_scbuf_fbwr_wen_r2 (sctag1_scbuf1_fbwr_wen_r2[15:0]), // Templated
.sctag_scbuf_fbwr_wl_r2 (sctag1_scbuf1_fbwr_wl_r2[2:0]), // Templated
.sctag_scbuf_fbd_stdatasel_c3 (sctag1_scbuf1_fbd_stdatasel_c3), // Templated
.sctag_scbuf_wbwr_wen_c6 (sctag1_scbuf1_wbwr_wen_c6[3:0]), // Templated
.sctag_scbuf_wbwr_wl_c6 (sctag1_scbuf1_wbwr_wl_c6[2:0]), // Templated
.sctag_scbuf_wbrd_en_r0 (sctag1_scbuf1_wbrd_en_r0), // Templated
.sctag_scbuf_wbrd_wl_r0 (sctag1_scbuf1_wbrd_wl_r0[2:0]), // Templated
.sctag_scbuf_ev_dword_r0 (sctag1_scbuf1_ev_dword_r0[2:0]), // Templated
.sctag_scbuf_evict_en_r0 (sctag1_scbuf1_evict_en_r0), // Templated
.sctag_scbuf_rdma_wren_s2 (sctag1_scbuf1_rdma_wren_s2[15:0]), // Templated
.sctag_scbuf_rdma_wrwl_s2 (sctag1_scbuf1_rdma_wrwl_s2[1:0]), // Templated
.sctag_scbuf_rdma_rdwl_r0 (sctag1_scbuf1_rdma_rdwl_r0[1:0]), // Templated
.sctag_scbuf_rdma_rden_r0 (sctag1_scbuf1_rdma_rden_r0), // Templated
.sctag_scbuf_ctag_en_c7 (sctag1_scbuf1_ctag_en_c7), // Templated
.sctag_scbuf_ctag_c7 (sctag1_scbuf1_ctag_c7[14:0]), // Templated
.sctag_scbuf_word_c7 (sctag1_scbuf1_word_c7[3:0]), // Templated
.sctag_scbuf_req_en_c7 (sctag1_scbuf1_req_en_c7), // Templated
.sctag_scbuf_word_vld_c7 (sctag1_scbuf1_word_vld_c7), // Templated
.sctag_dram_rd_req (sctag1_dram13_rd_req), // Templated
.sctag_dram_rd_dummy_req (sctag1_dram13_rd_dummy_req), // Templated
.sctag_dram_rd_req_id (sctag1_dram13_rd_req_id[2:0]), // Templated
.sctag_dram_addr (sctag1_dram13_addr[39:5]), // Templated
.sctag_dram_wr_req (sctag1_dram13_wr_req), // Templated
.sctag_jbi_iq_dequeue (sctag1_jbi_iq_dequeue), // Templated
.sctag_jbi_wib_dequeue (sctag1_jbi_wib_dequeue), // Templated
.sctag_dbgbus_out (sctag1_dbgbus_out[40:0]), // Templated
.sctag_clk_tr (sctag1_ctu_tr), // Templated
.sctag_ctu_mbistdone (sctag1_ctu_mbistdone), // Templated
.sctag_ctu_mbisterr (sctag1_ctu_mbisterr), // Templated
.sctag_ctu_scanout (par_scan_tail[9]), // Templated
.sctag_scbuf_scanout (), // Templated
.sctag_efc_fuse_data (sctag1_efc_fuse_data), // Templated
// Inputs
.pcx_sctag_data_rdy_px1 (pcx_sctag1_data_rdy_px1_buf), // Templated
.pcx_sctag_data_px2 (pcx_sctag1_data_px2_buf[`PCX_WIDTH-1:0]), // Templated
.pcx_sctag_atm_px1 (pcx_sctag1_atm_px1_buf), // Templated
.cpx_sctag_grant_cx (cpx_sctag1_grant_cx_buf[7:0]), // Templated
.scdata_sctag_decc_c6 (scdata1_sctag1_decc_c6[155:0]), // Templated
.scbuf_sctag_ev_uerr_r5 (scbuf1_sctag1_ev_uerr_r5_buf), // Templated
.scbuf_sctag_ev_cerr_r5 (scbuf1_sctag1_ev_cerr_r5_buf), // Templated
.scbuf_sctag_rdma_uerr_c10 (scbuf1_sctag1_rdma_uerr_c10_buf), // Templated
.scbuf_sctag_rdma_cerr_c10 (scbuf1_sctag1_rdma_cerr_c10_buf), // Templated
.dram_sctag_rd_ack (dram13_sctag1_rd_ack_buf2), // Templated
.dram_sctag_wr_ack (dram13_sctag1_wr_ack_buf2), // Templated
.dram_sctag_chunk_id_r0 (dram13_sctag1_chunk_id_r0_buf2[1:0]), // Templated
.dram_sctag_data_vld_r0 (dram13_sctag1_data_vld_r0_buf2), // Templated
.dram_sctag_rd_req_id_r0 (dram13_sctag1_rd_req_id_r0_buf2[2:0]), // Templated
.dram_sctag_secc_err_r2 (dram13_sctag1_secc_err_r2_buf2), // Templated
.dram_sctag_mecc_err_r2 (dram13_sctag1_mecc_err_r2_buf2), // Templated
.dram_sctag_scb_mecc_err (dram13_sctag1_scb_mecc_err_buf2), // Templated
.dram_sctag_scb_secc_err (dram13_sctag1_scb_secc_err_buf2), // Templated
.jbi_sctag_req_vld (jbi_sctag1_req_vld_d2), // Templated
.jbi_sctag_req (jbi_sctag1_req_d2[31:0]), // Templated
.arst_l (cmp_arst_l), // Templated
.grst_l (rpt_cmp_grst_l_c4), // Templated
.adbginit_l (cmp_adbginit_l), // Templated
.gdbginit_l (rpt_cmp_gdbginit_l_c4), // Templated
.cluster_cken (rpt_sctag1_cmp_cken), // Templated
.cmp_gclk (cmp_gclk_c1_r[4]), // Templated
.global_shift_enable (global_shift_enable),
.ctu_sctag_mbisten (ctu_sctag1_mbisten_buf2), // Templated
.ctu_sctag_scanin (par_scan_head[9]), // Templated
.scdata_sctag_scanout (1'b0), // Templated
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_short_chain (ctu_tst_short_chain),
.efc_sctag_fuse_clk1 (efc_sctag13_fuse_clk1), // Templated
.efc_sctag_fuse_clk2 (efc_sctag13_fuse_clk2), // Templated
.efc_sctag_fuse_ashift (efc_sctag1_fuse_ashift), // Templated
.efc_sctag_fuse_dshift (efc_sctag1_fuse_dshift), // Templated
.efc_sctag_fuse_data (efc_sctag13_fuse_data)); // Templated
`endif
//
/* sctag AUTO_TEMPLATE (
.cmp_gclk (cmp_gclk_c2_r[2]),
.arst_l (cmp_arst_l),
.adbginit_l (cmp_adbginit_l),
.grst_l (rpt_cmp_grst_l_c2),
.gdbginit_l (rpt_cmp_gdbginit_l_c2),
.cluster_cken (rpt_sctag@_cmp_cken),
.sctag_dbgbus_out (sctag@_dbgbus_out[]),
.efc_sctag_fuse_ashift (efc_sctag@_fuse_ashift),
.efc_sctag_fuse_dshift (efc_sctag@_fuse_dshift),
.efc_sctag_fuse_\(.*\) (efc_sctag@"(% @ 2)"@"(+ (% @ 2) 2)"_fuse_\1),
.sctag_efc_fuse_data (sctag@_efc_fuse_data),
.ctu_sctag_scanin (par_scan_head[30]),
.sctag_ctu_scanout (par_scan_tail[30]),
.sctag_scbuf_scanout (),
.scdata_sctag_scanout (1'b0),
.sctag_scbuf\(.*\) (sctag@_scbuf@\1[]),
.scbuf_sctag\(.*\) (scbuf@_sctag@\1_buf[]),
.sctag_scdata\(.*\) (sctag@_scdata@\1[]),
.scdata_sctag\(.*\) (scdata@_sctag@\1[]),
.sctag_dram\(.*\) (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1[]),
.dram_sctag\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_sctag@\1_buf2[]),
.sctag_jbi\(.*\) (sctag@_jbi\1[]),
.jbi_sctag\(.*\) (jbi_sctag@\1_d2[]),
.sctag_cpx\(.*\) (sctag@_cpx\1[]),
.sctag_pcx\(.*\) (sctag@_pcx\1[]),
.cpx_sctag\(.*\) (cpx_sctag@\1_buf[]),
.pcx_sctag\(.*\) (pcx_sctag@\1_buf[]),
.sctag_ctu_mbistdone (sctag@_ctu_mbistdone),
.sctag_ctu_mbisterr (sctag@_ctu_mbisterr),
.sctag_ctu\(.*\) (sctag@_ctu\1[]),
.ctu_sctag_mbisten (ctu_sctag@_mbisten_buf2),
.ctu_sctag\(.*\) (ctu_sctag@\1[]),
.sctag_clk_tr (sctag@_ctu_tr),
); */
//
`ifdef RTL_SCTAG2
sctag sctag2
(/*AUTOINST*/
// Outputs
.sctag_cpx_req_cq (sctag2_cpx_req_cq[7:0]), // Templated
.sctag_cpx_atom_cq (sctag2_cpx_atom_cq), // Templated
.sctag_cpx_data_ca (sctag2_cpx_data_ca[`CPX_WIDTH-1:0]), // Templated
.sctag_pcx_stall_pq (sctag2_pcx_stall_pq), // Templated
.sctag_jbi_por_req (sctag2_jbi_por_req), // Templated
.sctag_scdata_way_sel_c2 (sctag2_scdata2_way_sel_c2[11:0]), // Templated
.sctag_scdata_rd_wr_c2 (sctag2_scdata2_rd_wr_c2), // Templated
.sctag_scdata_set_c2 (sctag2_scdata2_set_c2[9:0]), // Templated
.sctag_scdata_col_offset_c2 (sctag2_scdata2_col_offset_c2[3:0]), // Templated
.sctag_scdata_word_en_c2 (sctag2_scdata2_word_en_c2[15:0]), // Templated
.sctag_scdata_fbrd_c3 (sctag2_scdata2_fbrd_c3), // Templated
.sctag_scdata_fb_hit_c3 (sctag2_scdata2_fb_hit_c3), // Templated
.sctag_scdata_stdecc_c2 (sctag2_scdata2_stdecc_c2[77:0]), // Templated
.sctag_scbuf_stdecc_c3 (sctag2_scbuf2_stdecc_c3[77:0]), // Templated
.sctag_scbuf_fbrd_en_c3 (sctag2_scbuf2_fbrd_en_c3), // Templated
.sctag_scbuf_fbrd_wl_c3 (sctag2_scbuf2_fbrd_wl_c3[2:0]), // Templated
.sctag_scbuf_fbwr_wen_r2 (sctag2_scbuf2_fbwr_wen_r2[15:0]), // Templated
.sctag_scbuf_fbwr_wl_r2 (sctag2_scbuf2_fbwr_wl_r2[2:0]), // Templated
.sctag_scbuf_fbd_stdatasel_c3 (sctag2_scbuf2_fbd_stdatasel_c3), // Templated
.sctag_scbuf_wbwr_wen_c6 (sctag2_scbuf2_wbwr_wen_c6[3:0]), // Templated
.sctag_scbuf_wbwr_wl_c6 (sctag2_scbuf2_wbwr_wl_c6[2:0]), // Templated
.sctag_scbuf_wbrd_en_r0 (sctag2_scbuf2_wbrd_en_r0), // Templated
.sctag_scbuf_wbrd_wl_r0 (sctag2_scbuf2_wbrd_wl_r0[2:0]), // Templated
.sctag_scbuf_ev_dword_r0 (sctag2_scbuf2_ev_dword_r0[2:0]), // Templated
.sctag_scbuf_evict_en_r0 (sctag2_scbuf2_evict_en_r0), // Templated
.sctag_scbuf_rdma_wren_s2 (sctag2_scbuf2_rdma_wren_s2[15:0]), // Templated
.sctag_scbuf_rdma_wrwl_s2 (sctag2_scbuf2_rdma_wrwl_s2[1:0]), // Templated
.sctag_scbuf_rdma_rdwl_r0 (sctag2_scbuf2_rdma_rdwl_r0[1:0]), // Templated
.sctag_scbuf_rdma_rden_r0 (sctag2_scbuf2_rdma_rden_r0), // Templated
.sctag_scbuf_ctag_en_c7 (sctag2_scbuf2_ctag_en_c7), // Templated
.sctag_scbuf_ctag_c7 (sctag2_scbuf2_ctag_c7[14:0]), // Templated
.sctag_scbuf_word_c7 (sctag2_scbuf2_word_c7[3:0]), // Templated
.sctag_scbuf_req_en_c7 (sctag2_scbuf2_req_en_c7), // Templated
.sctag_scbuf_word_vld_c7 (sctag2_scbuf2_word_vld_c7), // Templated
.sctag_dram_rd_req (sctag2_dram02_rd_req), // Templated
.sctag_dram_rd_dummy_req (sctag2_dram02_rd_dummy_req), // Templated
.sctag_dram_rd_req_id (sctag2_dram02_rd_req_id[2:0]), // Templated
.sctag_dram_addr (sctag2_dram02_addr[39:5]), // Templated
.sctag_dram_wr_req (sctag2_dram02_wr_req), // Templated
.sctag_jbi_iq_dequeue (sctag2_jbi_iq_dequeue), // Templated
.sctag_jbi_wib_dequeue (sctag2_jbi_wib_dequeue), // Templated
.sctag_dbgbus_out (sctag2_dbgbus_out[40:0]), // Templated
.sctag_clk_tr (sctag2_ctu_tr), // Templated
.sctag_ctu_mbistdone (sctag2_ctu_mbistdone), // Templated
.sctag_ctu_mbisterr (sctag2_ctu_mbisterr), // Templated
.sctag_ctu_scanout (par_scan_tail[30]), // Templated
.sctag_scbuf_scanout (), // Templated
.sctag_efc_fuse_data (sctag2_efc_fuse_data), // Templated
// Inputs
.pcx_sctag_data_rdy_px1 (pcx_sctag2_data_rdy_px1_buf), // Templated
.pcx_sctag_data_px2 (pcx_sctag2_data_px2_buf[`PCX_WIDTH-1:0]), // Templated
.pcx_sctag_atm_px1 (pcx_sctag2_atm_px1_buf), // Templated
.cpx_sctag_grant_cx (cpx_sctag2_grant_cx_buf[7:0]), // Templated
.scdata_sctag_decc_c6 (scdata2_sctag2_decc_c6[155:0]), // Templated
.scbuf_sctag_ev_uerr_r5 (scbuf2_sctag2_ev_uerr_r5_buf), // Templated
.scbuf_sctag_ev_cerr_r5 (scbuf2_sctag2_ev_cerr_r5_buf), // Templated
.scbuf_sctag_rdma_uerr_c10 (scbuf2_sctag2_rdma_uerr_c10_buf), // Templated
.scbuf_sctag_rdma_cerr_c10 (scbuf2_sctag2_rdma_cerr_c10_buf), // Templated
.dram_sctag_rd_ack (dram02_sctag2_rd_ack_buf2), // Templated
.dram_sctag_wr_ack (dram02_sctag2_wr_ack_buf2), // Templated
.dram_sctag_chunk_id_r0 (dram02_sctag2_chunk_id_r0_buf2[1:0]), // Templated
.dram_sctag_data_vld_r0 (dram02_sctag2_data_vld_r0_buf2), // Templated
.dram_sctag_rd_req_id_r0 (dram02_sctag2_rd_req_id_r0_buf2[2:0]), // Templated
.dram_sctag_secc_err_r2 (dram02_sctag2_secc_err_r2_buf2), // Templated
.dram_sctag_mecc_err_r2 (dram02_sctag2_mecc_err_r2_buf2), // Templated
.dram_sctag_scb_mecc_err (dram02_sctag2_scb_mecc_err_buf2), // Templated
.dram_sctag_scb_secc_err (dram02_sctag2_scb_secc_err_buf2), // Templated
.jbi_sctag_req_vld (jbi_sctag2_req_vld_d2), // Templated
.jbi_sctag_req (jbi_sctag2_req_d2[31:0]), // Templated
.arst_l (cmp_arst_l), // Templated
.grst_l (rpt_cmp_grst_l_c2), // Templated
.adbginit_l (cmp_adbginit_l), // Templated
.gdbginit_l (rpt_cmp_gdbginit_l_c2), // Templated
.cluster_cken (rpt_sctag2_cmp_cken), // Templated
.cmp_gclk (cmp_gclk_c2_r[2]), // Templated
.global_shift_enable (global_shift_enable),
.ctu_sctag_mbisten (ctu_sctag2_mbisten_buf2), // Templated
.ctu_sctag_scanin (par_scan_head[30]), // Templated
.scdata_sctag_scanout (1'b0), // Templated
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_short_chain (ctu_tst_short_chain),
.efc_sctag_fuse_clk1 (efc_sctag02_fuse_clk1), // Templated
.efc_sctag_fuse_clk2 (efc_sctag02_fuse_clk2), // Templated
.efc_sctag_fuse_ashift (efc_sctag2_fuse_ashift), // Templated
.efc_sctag_fuse_dshift (efc_sctag2_fuse_dshift), // Templated
.efc_sctag_fuse_data (efc_sctag02_fuse_data)); // Templated
`endif
//
/* sctag AUTO_TEMPLATE (
.cmp_gclk (cmp_gclk_c2_r[4]),
.arst_l (cmp_arst_l),
.adbginit_l (cmp_adbginit_l),
.grst_l (rpt_cmp_grst_l_c7),
.gdbginit_l (rpt_cmp_gdbginit_l_c7),
.cluster_cken (rpt_sctag@_cmp_cken),
.sctag_dbgbus_out (sctag@_dbgbus_out[]),
.efc_sctag_fuse_ashift (efc_sctag@_fuse_ashift),
.efc_sctag_fuse_dshift (efc_sctag@_fuse_dshift),
.efc_sctag_fuse_\(.*\) (efc_sctag@"(% @ 2)"@"(+ (% @ 2) 2)"_fuse_\1),
.sctag_efc_fuse_data (sctag@_efc_fuse_data),
.ctu_sctag_scanin (par_scan_head[17]),
.sctag_ctu_scanout (par_scan_tail[17]),
.sctag_scbuf_scanout (),
.scdata_sctag_scanout (1'b0),
.sctag_scbuf\(.*\) (sctag@_scbuf@\1[]),
.scbuf_sctag\(.*\) (scbuf@_sctag@\1_buf[]),
.sctag_scdata\(.*\) (sctag@_scdata@\1[]),
.scdata_sctag\(.*\) (scdata@_sctag@\1[]),
.sctag_dram\(.*\) (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1[]),
.dram_sctag\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_sctag@\1_buf2[]),
.sctag_jbi\(.*\) (sctag@_jbi\1[]),
.jbi_sctag\(.*\) (jbi_sctag@\1_d2[]),
.sctag_cpx\(.*\) (sctag@_cpx\1[]),
.sctag_pcx\(.*\) (sctag@_pcx\1[]),
.cpx_sctag\(.*\) (cpx_sctag@\1_buf[]),
.pcx_sctag\(.*\) (pcx_sctag@\1_buf[]),
.sctag_ctu_mbistdone (sctag@_ctu_mbistdone),
.sctag_ctu_mbisterr (sctag@_ctu_mbisterr),
.sctag_ctu\(.*\) (sctag@_ctu\1[]),
.ctu_sctag_mbisten (ctu_sctag@_mbisten_buf2),
.ctu_sctag\(.*\) (ctu_sctag@\1[]),
.sctag_clk_tr (sctag@_ctu_tr),
); */
//
`ifdef RTL_SCTAG3
sctag sctag3
(/*AUTOINST*/
// Outputs
.sctag_cpx_req_cq (sctag3_cpx_req_cq[7:0]), // Templated
.sctag_cpx_atom_cq (sctag3_cpx_atom_cq), // Templated
.sctag_cpx_data_ca (sctag3_cpx_data_ca[`CPX_WIDTH-1:0]), // Templated
.sctag_pcx_stall_pq (sctag3_pcx_stall_pq), // Templated
.sctag_jbi_por_req (sctag3_jbi_por_req), // Templated
.sctag_scdata_way_sel_c2 (sctag3_scdata3_way_sel_c2[11:0]), // Templated
.sctag_scdata_rd_wr_c2 (sctag3_scdata3_rd_wr_c2), // Templated
.sctag_scdata_set_c2 (sctag3_scdata3_set_c2[9:0]), // Templated
.sctag_scdata_col_offset_c2 (sctag3_scdata3_col_offset_c2[3:0]), // Templated
.sctag_scdata_word_en_c2 (sctag3_scdata3_word_en_c2[15:0]), // Templated
.sctag_scdata_fbrd_c3 (sctag3_scdata3_fbrd_c3), // Templated
.sctag_scdata_fb_hit_c3 (sctag3_scdata3_fb_hit_c3), // Templated
.sctag_scdata_stdecc_c2 (sctag3_scdata3_stdecc_c2[77:0]), // Templated
.sctag_scbuf_stdecc_c3 (sctag3_scbuf3_stdecc_c3[77:0]), // Templated
.sctag_scbuf_fbrd_en_c3 (sctag3_scbuf3_fbrd_en_c3), // Templated
.sctag_scbuf_fbrd_wl_c3 (sctag3_scbuf3_fbrd_wl_c3[2:0]), // Templated
.sctag_scbuf_fbwr_wen_r2 (sctag3_scbuf3_fbwr_wen_r2[15:0]), // Templated
.sctag_scbuf_fbwr_wl_r2 (sctag3_scbuf3_fbwr_wl_r2[2:0]), // Templated
.sctag_scbuf_fbd_stdatasel_c3 (sctag3_scbuf3_fbd_stdatasel_c3), // Templated
.sctag_scbuf_wbwr_wen_c6 (sctag3_scbuf3_wbwr_wen_c6[3:0]), // Templated
.sctag_scbuf_wbwr_wl_c6 (sctag3_scbuf3_wbwr_wl_c6[2:0]), // Templated
.sctag_scbuf_wbrd_en_r0 (sctag3_scbuf3_wbrd_en_r0), // Templated
.sctag_scbuf_wbrd_wl_r0 (sctag3_scbuf3_wbrd_wl_r0[2:0]), // Templated
.sctag_scbuf_ev_dword_r0 (sctag3_scbuf3_ev_dword_r0[2:0]), // Templated
.sctag_scbuf_evict_en_r0 (sctag3_scbuf3_evict_en_r0), // Templated
.sctag_scbuf_rdma_wren_s2 (sctag3_scbuf3_rdma_wren_s2[15:0]), // Templated
.sctag_scbuf_rdma_wrwl_s2 (sctag3_scbuf3_rdma_wrwl_s2[1:0]), // Templated
.sctag_scbuf_rdma_rdwl_r0 (sctag3_scbuf3_rdma_rdwl_r0[1:0]), // Templated
.sctag_scbuf_rdma_rden_r0 (sctag3_scbuf3_rdma_rden_r0), // Templated
.sctag_scbuf_ctag_en_c7 (sctag3_scbuf3_ctag_en_c7), // Templated
.sctag_scbuf_ctag_c7 (sctag3_scbuf3_ctag_c7[14:0]), // Templated
.sctag_scbuf_word_c7 (sctag3_scbuf3_word_c7[3:0]), // Templated
.sctag_scbuf_req_en_c7 (sctag3_scbuf3_req_en_c7), // Templated
.sctag_scbuf_word_vld_c7 (sctag3_scbuf3_word_vld_c7), // Templated
.sctag_dram_rd_req (sctag3_dram13_rd_req), // Templated
.sctag_dram_rd_dummy_req (sctag3_dram13_rd_dummy_req), // Templated
.sctag_dram_rd_req_id (sctag3_dram13_rd_req_id[2:0]), // Templated
.sctag_dram_addr (sctag3_dram13_addr[39:5]), // Templated
.sctag_dram_wr_req (sctag3_dram13_wr_req), // Templated
.sctag_jbi_iq_dequeue (sctag3_jbi_iq_dequeue), // Templated
.sctag_jbi_wib_dequeue (sctag3_jbi_wib_dequeue), // Templated
.sctag_dbgbus_out (sctag3_dbgbus_out[40:0]), // Templated
.sctag_clk_tr (sctag3_ctu_tr), // Templated
.sctag_ctu_mbistdone (sctag3_ctu_mbistdone), // Templated
.sctag_ctu_mbisterr (sctag3_ctu_mbisterr), // Templated
.sctag_ctu_scanout (par_scan_tail[17]), // Templated
.sctag_scbuf_scanout (), // Templated
.sctag_efc_fuse_data (sctag3_efc_fuse_data), // Templated
// Inputs
.pcx_sctag_data_rdy_px1 (pcx_sctag3_data_rdy_px1_buf), // Templated
.pcx_sctag_data_px2 (pcx_sctag3_data_px2_buf[`PCX_WIDTH-1:0]), // Templated
.pcx_sctag_atm_px1 (pcx_sctag3_atm_px1_buf), // Templated
.cpx_sctag_grant_cx (cpx_sctag3_grant_cx_buf[7:0]), // Templated
.scdata_sctag_decc_c6 (scdata3_sctag3_decc_c6[155:0]), // Templated
.scbuf_sctag_ev_uerr_r5 (scbuf3_sctag3_ev_uerr_r5_buf), // Templated
.scbuf_sctag_ev_cerr_r5 (scbuf3_sctag3_ev_cerr_r5_buf), // Templated
.scbuf_sctag_rdma_uerr_c10 (scbuf3_sctag3_rdma_uerr_c10_buf), // Templated
.scbuf_sctag_rdma_cerr_c10 (scbuf3_sctag3_rdma_cerr_c10_buf), // Templated
.dram_sctag_rd_ack (dram13_sctag3_rd_ack_buf2), // Templated
.dram_sctag_wr_ack (dram13_sctag3_wr_ack_buf2), // Templated
.dram_sctag_chunk_id_r0 (dram13_sctag3_chunk_id_r0_buf2[1:0]), // Templated
.dram_sctag_data_vld_r0 (dram13_sctag3_data_vld_r0_buf2), // Templated
.dram_sctag_rd_req_id_r0 (dram13_sctag3_rd_req_id_r0_buf2[2:0]), // Templated
.dram_sctag_secc_err_r2 (dram13_sctag3_secc_err_r2_buf2), // Templated
.dram_sctag_mecc_err_r2 (dram13_sctag3_mecc_err_r2_buf2), // Templated
.dram_sctag_scb_mecc_err (dram13_sctag3_scb_mecc_err_buf2), // Templated
.dram_sctag_scb_secc_err (dram13_sctag3_scb_secc_err_buf2), // Templated
.jbi_sctag_req_vld (jbi_sctag3_req_vld_d2), // Templated
.jbi_sctag_req (jbi_sctag3_req_d2[31:0]), // Templated
.arst_l (cmp_arst_l), // Templated
.grst_l (rpt_cmp_grst_l_c7), // Templated
.adbginit_l (cmp_adbginit_l), // Templated
.gdbginit_l (rpt_cmp_gdbginit_l_c7), // Templated
.cluster_cken (rpt_sctag3_cmp_cken), // Templated
.cmp_gclk (cmp_gclk_c2_r[4]), // Templated
.global_shift_enable (global_shift_enable),
.ctu_sctag_mbisten (ctu_sctag3_mbisten_buf2), // Templated
.ctu_sctag_scanin (par_scan_head[17]), // Templated
.scdata_sctag_scanout (1'b0), // Templated
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_short_chain (ctu_tst_short_chain),
.efc_sctag_fuse_clk1 (efc_sctag13_fuse_clk1), // Templated
.efc_sctag_fuse_clk2 (efc_sctag13_fuse_clk2), // Templated
.efc_sctag_fuse_ashift (efc_sctag3_fuse_ashift), // Templated
.efc_sctag_fuse_dshift (efc_sctag3_fuse_dshift), // Templated
.efc_sctag_fuse_data (efc_sctag13_fuse_data)); // Templated
`endif
//
/* bw_ctu_pad_cluster AUTO_TEMPLATE (
.jclk (J_CLK[]),
.tsr_testio (TSR_TESTIO[]),
.vdda (VDDA),
.vddo (VDDCO),
); */
//
`ifdef RTL_PAD_CTU
bw_ctu_pad_cluster pad_ctu
(/*AUTOINST*/
// Inouts
.jclk (J_CLK[1:0]), // Templated
.tsr_testio (TSR_TESTIO[1:0]), // Templated
.vddo (VDDCO), // Templated
.vdda (VDDA)); // Templated
`endif
//
/* pad_ddr0 AUTO_TEMPLATE (
.dram0_ras_l (DRAM0_RAS_L),
.dram0_cas_l (DRAM0_CAS_L),
.dram0_we_l (DRAM0_WE_L),
.dram0_cs_l (DRAM0_CS_L[]),
.dram0_cke (DRAM0_CKE),
.dram0_addr (DRAM0_ADDR[]),
.dram0_ba (DRAM0_BA[]),
.dram0_dq (DRAM0_DQ[]),
.dram0_cb (DRAM0_CB[]),
.dram0_dqs (DRAM0_DQS[]),
.dram0_ck_p (DRAM0_CK_P[]),
.dram0_ck_n (DRAM0_CK_N[]),
.dram01_p_ref_res (DRAM01_P_REF_RES),
.dram01_n_ref_res (DRAM01_N_REF_RES),
.spare_ddr0_pin (SPARE_DDR0_PIN),
.spare_ddr0_pindata (1'b0),
.spare_ddr0_pad (SPARE_DDR0_PAD[]),
.spare_ddr0_paddata (7'b0101010),
.clkobs (CLKOBS[]),
.dram_gclk ({dram_gclk_c0_r[3],dram_gclk_c0_r[1]}),
.io_pwron_rst_l (dram_arst_l),
.clk_ddr0_cken (ctu_ddr0_dram_cken),
.bscan_\(.*\)_out (),
.pad_ddr0_bsi (dbg_ddr0_bso),
.ddr_si (par_scan_head[6]),
.bscan_\(.*\)_in (ctu_ddr0_\1),
.pad_ddr0_bso (ddr0_ddr0_bso),
.ddr_so (pddr0_jbi_so),
.ddr_se (global_shift_enable),
.tck (ctu_ddr0_clock_dr),
.ctu_io_sscan_se (ctu_ddr0_shift_dr),
.ctu_io_sscan_update (ctu_pads_sscan_update),
.pad_ddr0_sscan_in (ddr0_ddr0_bso),
.pad_ddr0_sscan_out (ddr0_ctu_bso),
.test_mode (io_test_mode),
.ddr_testmode_l (ctu_ddr_testmode_l),
.bypass_enable (global_scan_bypass_en),
.bypass_enable_out (),
.ps_select (pscan_select),
.ps_select_out (),
.vdd18 (VDDL18),
.dram0_io_ptr_clk_inv (dram0_io_ptr_clk_inv_buf2[]),
.dram0_io_addr (dram0_io_addr_buf2[]),
.dram0_io_data_out (dram0_io_data_out_buf2[]),
.dram0_io_cs_l (dram0_io_cs_l_buf2[]),
.dram0_io_bank (dram0_io_bank_buf2[]),
.dram0_io_write_en_l (dram0_io_write_en_l_buf2),
.dram0_io_ras_l (dram0_io_ras_l_buf2),
.dram0_io_cke (dram0_io_cke_buf2),
.dram0_io_drive_data (dram0_io_drive_data_buf2),
.dram0_io_pad_enable (dram0_io_pad_enable_buf2),
.dram0_io_drive_enable (dram0_io_drive_enable_buf2),
.dram0_io_channel_disabled (dram0_io_channel_disabled_buf2),
.dram0_io_cas_l (dram0_io_cas_l_buf2),
.dram0_io_clk_enable (dram0_io_clk_enable_buf2),
.dram0_io_pad_clk_inv (dram0_io_pad_clk_inv_buf2),
.ddr0_dll_bypass_l (ctu_dll0_byp_l),
.ddr0_bypass_data (ctu_dll0_byp_val[]),
.ddr0_lpf_code (ctu_dll0_ctu_ctrl[]),
); */
//
`ifdef RTL_PAD_DDR0
pad_ddr0 pad_ddr0
(
.serial_out ({ddr0_sot[143:124],
/*ddr0_sot[ 123]=DQ[ 59]*/ ser_scan_out[6],
/*ddr0_sot[ 122]=DQ[ 58]*/ par_scan_head[6],
/*ddr0_sot[ 121]=DQ[ 57]*/ ser_scan_out[5],
/*ddr0_sot[ 120]=DQ[ 56]*/ par_scan_head[5],
ddr0_sot[119: 76],
/*ddr0_sot[ 75]=DQ[ 35]*/ ser_scan_out[4],
/*ddr0_sot[ 74]=DQ[ 34]*/ par_scan_head[4],
/*ddr0_sot[ 73]=DQ[ 33]*/ ser_scan_out[3],
/*ddr0_sot[ 72]=DQ[ 32]*/ par_scan_head[3],
ddr0_sot[ 71: 36],
/*ddr0_sot[ 35]=DQ[ 19]*/ ser_scan_out[2],
/*ddr0_sot[ 34]=DQ[ 18]*/ par_scan_head[2],
/*ddr0_sot[ 33]=DQ[ 17]*/ ser_scan_out[1],
/*ddr0_sot[ 32]=DQ[ 16]*/ par_scan_head[1],
ddr0_sot[ 31: 0]}),
.serial_in ({ddr0_sin[143:124],
/*ddr0_sin[ 123]=DQ[ 59]*/ par_scan_tail[6],
/*ddr0_sin[ 122]=DQ[ 58]*/ ser_scan_out[5],
/*ddr0_sin[ 121]=DQ[ 57]*/ par_scan_tail[5],
/*ddr0_sin[ 120]=DQ[ 56]*/ ser_scan_out[4],
ddr0_sin[119: 76],
/*ddr0_sin[ 75]=DQ[ 35]*/ par_scan_tail[4],
/*ddr0_sin[ 74]=DQ[ 34]*/ ser_scan_out[3],
/*ddr0_sin[ 73]=DQ[ 33]*/ par_scan_tail[3],
/*ddr0_sin[ 72]=DQ[ 32]*/ ser_scan_out[2],
ddr0_sin[ 71: 36],
/*ddr0_sin[ 35]=DQ[ 19]*/ par_scan_tail[2],
/*ddr0_sin[ 34]=DQ[ 18]*/ ser_scan_out[1],
/*ddr0_sin[ 33]=DQ[ 17]*/ par_scan_tail[1],
/*ddr0_sot[ 32]=DQ[ 16]*/ ser_scan_out[0],
ddr0_sin[ 31: 0]}),
.afi ({ddr0_afi[143:131],
/*ddr0_afi[ 130]=DQ[122]*/ afi_tsr_tsel[5],
ddr0_afi[ 129],
/*ddr0_afi[ 128]=DQ[120]*/ afi_tsr_tsel[4],
ddr0_afi[ 127],
/*ddr0_afi[ 126]=DQ[ 62]*/ afi_tsr_tsel[7],
ddr0_afi[ 125],
/*ddr0_afi[ 124]=DQ[ 60]*/ afi_tsr_tsel[6],
ddr0_afi[ 123],
/*ddr0_afi[ 122]=DQ[ 58]*/ afi_rt_data_in[6],
ddr0_afi[ 121],
/*ddr0_afi[ 120]=DQ[ 56]*/ afi_rt_data_in[5],
ddr0_afi[ 119],
/*ddr0_afi[ 118]=DQ[118]*/ afi_rng_ctl[2],
ddr0_afi[ 117],
/*ddr0_afi[ 116]=DQ[116]*/ afi_rng_ctl[1],
ddr0_afi[ 115],
/*ddr0_afi[ 114]=DQ[114]*/ afi_tsr_tsel[1],
ddr0_afi[ 113],
/*ddr0_afi[ 112]=DQ[112]*/ afi_tsr_tsel[0],
ddr0_afi[ 111],
/*ddr0_afi[ 110]=DQ[ 54]*/ afi_tsr_tsel[3],
ddr0_afi[ 109],
/*ddr0_afi[ 108]=DQ[ 52]*/ afi_tsr_tsel[2],
ddr0_afi[ 107],
ddr0_afi[106:103],
/*ddr0_afi[ 102]=DQ[110]*/ afi_rng_ctl[0],
ddr0_afi[101: 75],
/*ddr0_afi[ 74]=DQ[ 34]*/ afi_rt_data_in[4],
ddr0_afi[ 73],
/*ddr0_afi[ 72]=DQ[ 32]*/ afi_rt_data_in[3],
ddr0_afi[ 71: 35],
/*ddr0_afi[ 34]=DQ[ 18]*/ afi_rt_data_in[2],
ddr0_afi[ 33],
/*ddr0_afi[ 32]=DQ[ 16]*/ afi_rt_data_in[1],
ddr0_afi[ 31: 3],
/*ddr0_afi[ 2]=DQ[ 2]*/ afi_rt_data_in[0],
ddr0_afi[ 1: 0]}),
.afo ({ddr0_afo[143:132],
/*ddr0_afo[ 131]=DQ[123]*/ afo_tsr_dout[5],
ddr0_afo[ 130],
/*ddr0_afo[ 129]=DQ[121]*/ afo_tsr_dout[4],
ddr0_afo[ 128],
/*ddr0_afo[ 127]=DQ[ 63]*/ afo_tsr_dout[7],
ddr0_afo[ 126],
/*ddr0_afo[ 125]=DQ[ 61]*/ afo_tsr_dout[6],
ddr0_afo[ 124],
/*ddr0_afo[ 123]=DQ[ 59]*/ afo_rt_data_out[6],
ddr0_afo[ 122],
/*ddr0_afo[ 121]=DQ[ 57]*/ afo_rt_data_out[5],
ddr0_afo[ 120],
/*ddr0_afo[ 119]=DQ[119]*/ afo_rng_data,
ddr0_afo[118:116],
/*ddr0_afo[ 115]=DQ[115]*/ afo_tsr_dout[1],
ddr0_afo[114:112],
/*ddr0_afo[ 111]=DQ[ 55]*/ afo_tsr_dout[3],
ddr0_afo[ 110],
/*ddr0_afo[ 109]=DQ[ 53]*/ afo_tsr_dout[2],
ddr0_afo[ 108],
/*ddr0_afo[ 107]=DQ[ 51]*/ afo_rng_clk,
ddr0_afo[ 106],
/*ddr0_afo[ 105]=DQ[ 49]*/ afo_tsr_dout[0],
ddr0_afo[104: 76],
/*ddr0_afo[ 75]=DQ[ 35]*/ afo_rt_data_out[4],
ddr0_afo[ 74],
/*ddr0_afo[ 73]=DQ[ 33]*/ afo_rt_data_out[3],
ddr0_afo[ 72: 36],
/*ddr0_afo[ 35]=DQ[ 19]*/ afo_rt_data_out[2],
ddr0_afo[ 34],
/*ddr0_afo[ 33]=DQ[ 17]*/ afo_rt_data_out[1],
ddr0_afo[ 32: 4],
/*ddr0_afo[ 3]=DQ[ 3]*/ afo_rt_data_out[0],
ddr0_afo[ 2: 0]}),
/*AUTOINST*/
// Outputs
.ddr0_lpf_code (ctu_dll0_ctu_ctrl[4:0]), // Templated
.dram0_addr (DRAM0_ADDR[14:0]), // Templated
.dram0_ba (DRAM0_BA[2:0]), // Templated
.dram0_cs_l (DRAM0_CS_L[3:0]), // Templated
.dram0_ck_n (DRAM0_CK_N[3:0]), // Templated
.dram0_ck_p (DRAM0_CK_P[3:0]), // Templated
.ddr0_ddr1_cbd (ddr0_ddr1_cbd[8:1]),
.ddr0_ddr1_cbu (ddr0_ddr1_cbu[8:1]),
.io_dram0_data_in (io_dram0_data_in[255:0]),
.io_dram0_ecc_in (io_dram0_ecc_in[31:0]),
.ddr_so (pddr0_jbi_so), // Templated
.pad_ddr0_sscan_out (ddr0_ctu_bso), // Templated
.bscan_hiz_l_out (), // Templated
.bscan_shift_dr_out (), // Templated
.ps_select_out (), // Templated
.bscan_update_dr_out (), // Templated
.bypass_enable_out (), // Templated
.bscan_clock_dr_out (), // Templated
.bscan_mode_ctl_out (), // Templated
.dram0_we_l (DRAM0_WE_L), // Templated
.dram0_cas_l (DRAM0_CAS_L), // Templated
.dram0_ras_l (DRAM0_RAS_L), // Templated
.dram0_cke (DRAM0_CKE), // Templated
.pad_ddr0_bso (ddr0_ddr0_bso), // Templated
.ddr0_ctu_dll_overflow (ddr0_ctu_dll_overflow),
.io_dram0_data_valid (io_dram0_data_valid),
.ddr0_ctu_dll_lock (ddr0_ctu_dll_lock),
// Inouts
.spare_ddr0_pin (SPARE_DDR0_PIN), // Templated
.clkobs (CLKOBS[1:0]), // Templated
.spare_ddr0_pad (SPARE_DDR0_PAD[6:0]), // Templated
.dram0_dq (DRAM0_DQ[127:0]), // Templated
.dram0_dqs (DRAM0_DQS[35:0]), // Templated
.dram0_cb (DRAM0_CB[15:0]), // Templated
// Inputs
.spare_ddr0_paddata (7'b0101010), // Templated
.ddr0_bypass_data (ctu_dll0_byp_val[4:0]), // Templated
.spare_ddr0_pindata (1'b0), // Templated
.ctu_io_clkobs (ctu_io_clkobs[1:0]),
.ctu_ddr0_dll_delayctr (ctu_ddr0_dll_delayctr[2:0]),
.dram0_io_ptr_clk_inv (dram0_io_ptr_clk_inv_buf2[4:0]), // Templated
.dram_gclk ({dram_gclk_c0_r[3],dram_gclk_c0_r[1]}), // Templated
.dram0_io_addr (dram0_io_addr_buf2[14:0]), // Templated
.dram0_io_data_out (dram0_io_data_out_buf2[287:0]), // Templated
.dram0_io_cs_l (dram0_io_cs_l_buf2[3:0]), // Templated
.dram0_io_bank (dram0_io_bank_buf2[2:0]), // Templated
.bscan_mode_ctl_in (ctu_ddr0_mode_ctl), // Templated
.ddr_si (par_scan_head[6]), // Templated
.ddr0_dll_bypass_l (ctu_dll0_byp_l), // Templated
.tck (ctu_ddr0_clock_dr), // Templated
.ddr_testmode_l (ctu_ddr_testmode_l), // Templated
.ddr_se (global_shift_enable), // Templated
.ps_select (pscan_select), // Templated
.bypass_enable (global_scan_bypass_en), // Templated
.vdd18 (VDDL18), // Templated
.test_mode (io_test_mode), // Templated
.bscan_hiz_l_in (ctu_ddr0_hiz_l), // Templated
.ctu_ddr0_iodll_rst_l (ctu_ddr0_iodll_rst_l),
.dram_adbginit_l (dram_adbginit_l),
.dram_arst_l (dram_arst_l),
.dram_gdbginit_l (dram_gdbginit_l),
.bscan_clock_dr_in (ctu_ddr0_clock_dr), // Templated
.pad_ddr0_bsi (dbg_ddr0_bso), // Templated
.pad_ddr0_sscan_in (ddr0_ddr0_bso), // Templated
.ctu_io_sscan_se (ctu_ddr0_shift_dr), // Templated
.ctu_io_sscan_update (ctu_pads_sscan_update), // Templated
.ctu_global_snap (ctu_global_snap),
.dram01_p_ref_res (DRAM01_P_REF_RES), // Templated
.bscan_shift_dr_in (ctu_ddr0_shift_dr), // Templated
.dram01_n_ref_res (DRAM01_N_REF_RES), // Templated
.bscan_update_dr_in (ctu_ddr0_update_dr), // Templated
.dram0_io_write_en_l (dram0_io_write_en_l_buf2), // Templated
.dram0_io_ras_l (dram0_io_ras_l_buf2), // Templated
.dram0_io_cke (dram0_io_cke_buf2), // Templated
.dram0_io_drive_data (dram0_io_drive_data_buf2), // Templated
.dram0_io_pad_enable (dram0_io_pad_enable_buf2), // Templated
.dram0_io_drive_enable (dram0_io_drive_enable_buf2), // Templated
.dram0_io_channel_disabled (dram0_io_channel_disabled_buf2), // Templated
.dram_grst_l (dram_grst_l),
.clk_ddr0_cken (ctu_ddr0_dram_cken), // Templated
.dram0_io_cas_l (dram0_io_cas_l_buf2), // Templated
.dram0_io_clk_enable (dram0_io_clk_enable_buf2), // Templated
.dram0_io_pad_clk_inv (dram0_io_pad_clk_inv_buf2)); // Templated
`endif
//
/* pad_ddr1 AUTO_TEMPLATE (
.dram1_ras_l (DRAM1_RAS_L),
.dram1_cas_l (DRAM1_CAS_L),
.dram1_we_l (DRAM1_WE_L),
.dram1_cs_l (DRAM1_CS_L[]),
.dram1_cke (DRAM1_CKE),
.dram1_addr (DRAM1_ADDR[]),
.dram1_ba (DRAM1_BA[]),
.dram1_dq (DRAM1_DQ[]),
.dram1_cb (DRAM1_CB[]),
.dram1_dqs (DRAM1_DQS[]),
.dram1_ck_p (DRAM1_CK_P[]),
.dram1_ck_n (DRAM1_CK_N[]),
.spare_ddr1_pin (SPARE_DDR1_PIN[]),
.spare_ddr1_pindata (3'b010),
.spare_ddr1_pad (SPARE_DDR1_PAD[]),
.spare_ddr1_paddata (7'b0101010),
.dram_gclk ({dram_gclk_c0_r[7],dram_gclk_c0_r[5]}),
.clk_ddr1_cken (ctu_ddr1_dram_cken),
.bscan_\(.*\)_out (),
.pad_ddr1_bsi (ctu_ddr1_bso),
.ddr_si (pdbg_pddr1_so),
.bscan_\(.*\)_in (ctu_ddr1_\1),
.pad_ddr1_bso (ddr1_jbusl_bso),
.ddr_so (pddr1_pjbusl_so),
.ddr_se (global_shift_enable),
.test_mode (io_test_mode),
.ddr_testmode_l (ctu_ddr_testmode_l),
.bypass_enable (global_scan_bypass_en),
.bypass_enable_out (),
.ps_select (pscan_select),
.ps_select_out (),
.vdd18 (VDDL18),
.io_dram1_data_in (io_dram1_data_in[]),
.io_dram1_ecc_in (io_dram1_ecc_in[]),
.io_dram1_data_valid (io_dram1_data_valid),
.dram1_io_bank (dram1_io_bank_buf2[]),
.dram1_io_cs_l (dram1_io_cs_l_buf2[]),
.dram1_io_ptr_clk_inv (dram1_io_ptr_clk_inv_buf2[]),
.dram1_io_addr (dram1_io_addr_buf2[]),
.dram1_io_data_out (dram1_io_data_out_buf2[]),
.dram1_io_pad_enable (dram1_io_pad_enable_buf2),
.dram1_io_drive_enable (dram1_io_drive_enable_buf2),
.dram1_io_write_en_l (dram1_io_write_en_l_buf2),
.dram1_io_cas_l (dram1_io_cas_l_buf2),
.dram1_io_ras_l (dram1_io_ras_l_buf2),
.dram1_io_clk_enable (dram1_io_clk_enable_buf2),
.dram1_io_channel_disabled (dram1_io_channel_disabled_buf2),
.dram1_io_drive_data (dram1_io_drive_data_buf2),
.dram1_io_cke (dram1_io_cke_buf2),
.dram1_io_pad_clk_inv (dram1_io_pad_clk_inv_buf2),
.ddr1_dll_bypass_l (ctu_dll1_byp_l),
.ddr1_bypass_data (ctu_dll1_byp_val[]),
.ddr1_lpf_code (ctu_dll1_ctu_ctrl[]),
); */
//
`ifdef RTL_PAD_DDR1
pad_ddr1 pad_ddr1
(
.serial_out ({ddr1_sot[143:92],
/*ddr1_sot[ 91]=DQ[ 43]*/ ser_scan_out[12],
/*ddr1_sot[ 90]=DQ[ 42]*/ par_scan_head[12],
/*ddr1_sot[ 89]=DQ[ 41]*/ ser_scan_out[11],
/*ddr1_sot[ 88]=DQ[ 40]*/ par_scan_head[11],
ddr1_sot[ 87: 52],
/*ddr1_sot[ 51]=DQ[ 27]*/ ser_scan_out[10],
/*ddr1_sot[ 50]=DQ[ 26]*/ par_scan_head[10],
/*ddr1_sot[ 49]=DQ[ 25]*/ ser_scan_out[9],
/*ddr1_sot[ 48]=DQ[ 24]*/ par_scan_head[9],
ddr1_sot[ 47: 4],
/*ddr1_sot[ 3]=DQ[ 3]*/ ser_scan_out[8],
/*ddr1_sot[ 2]=DQ[ 2]*/ par_scan_head[8],
/*ddr1_sot[ 1]=DQ[ 1]*/ ser_scan_out[7],
/*ddr1_sot[ 0]=DQ[ 0]*/ par_scan_head[7]}),
.serial_in ({ddr1_sin[143:92],
/*ddr1_sin[ 91]=DQ[ 43]*/ par_scan_tail[12],
/*ddr1_sin[ 90]=DQ[ 42]*/ ser_scan_out[11],
/*ddr1_sin[ 89]=DQ[ 41]*/ par_scan_tail[11],
/*ddr1_sin[ 88]=DQ[ 40]*/ ser_scan_out[10],
ddr1_sin[ 87: 52],
/*ddr1_sin[ 51]=DQ[ 27]*/ par_scan_tail[10],
/*ddr1_sin[ 50]=DQ[ 26]*/ ser_scan_out[9],
/*ddr1_sin[ 49]=DQ[ 25]*/ par_scan_tail[9],
/*ddr1_sin[ 48]=DQ[ 24]*/ ser_scan_out[8],
ddr1_sin[ 47: 4],
/*ddr1_sin[ 3]=DQ[ 3]*/ par_scan_tail[8],
/*ddr1_sin[ 2]=DQ[ 2]*/ ser_scan_out[7],
/*ddr1_sin[ 1]=DQ[ 1]*/ par_scan_tail[7],
/*ddr1_sin[ 0]=DQ[ 0]*/ ser_scan_out[6]}),
.afi ({ddr1_afi[143:105],
/*ddr1_afi[ 104]=DQ[ 48]*/ afi_bist_mode,
ddr1_afi[103: 91],
/*ddr1_afi[ 90]=DQ[ 42]*/ afi_rt_data_in[12],
ddr1_afi[ 89],
/*ddr1_afi[ 88]=DQ[ 40]*/ afi_rt_data_in[11],
ddr1_afi[ 87: 75],
/*ddr1_afi[ 74]=DQ[ 34]*/ afi_bypass_mode,
ddr1_afi[ 73: 71],
/*ddr1_afi[ 70]=DQ[ 94]*/ afi_pll_trst_l,
ddr1_afi[ 69],
/*ddr1_afi[ 68]=DQ[ 92]*/ afi_pll_div2[5],
ddr1_afi[ 67 :65],
/*ddr1_afi[ 64]=DQ[ 88]*/ afi_pll_char_mode,
ddr1_afi[ 63: 55],
/*ddr1_afi[ 54]=DQ[ 30]*/ afi_pll_div2[4],
ddr1_afi[ 53],
/*ddr1_afi[ 52]=DQ[ 28]*/ afi_pll_div2[3],
ddr1_afi[ 51],
/*ddr1_afi[ 50]=DQ[ 26]*/ afi_rt_data_in[10],
ddr1_afi[ 49],
/*ddr1_afi[ 48]=DQ[ 24]*/ afi_rt_data_in[9],
ddr1_afi[ 47],
/*ddr1_afi[ 46]=DQ[ 86]*/ afi_pll_div2[2],
ddr1_afi[ 45],
/*ddr1_afi[ 44]=DQ[ 84]*/ afi_pll_div2[1],
ddr1_afi[ 43],
/*ddr1_afi[ 42]=DQ[ 82]*/ afi_pll_div2[0],
ddr1_afi[ 41],
/*ddr1_afi[ 40]=DQ[ 80]*/ afi_pll_clamp_fltr,
ddr1_afi[ 39: 35],
/*ddr1_afi[ 34]=DQ[ 18]*/ afi_rt_read_write,
ddr1_afi[ 33],
/*ddr1_afi[ 32]=DQ[ 16]*/ afi_rt_high_low,
ddr1_afi[ 31],
/*ddr1_afi[ 30]=DQ[ 78]*/ afi_tsr_mode,
ddr1_afi[ 29],
/*ddr1_afi[ 28]=DQ[ 76]*/ afi_tsr_div[9],
ddr1_afi[ 27],
/*ddr1_afi[ 26]=DQ[ 74]*/ afi_tsr_div[8],
ddr1_afi[ 25],
/*ddr1_afi[ 24]=DQ[ 72]*/ afi_tsr_div[7],
ddr1_afi[ 23: 19],
/*ddr1_afi[ 18]=DQ[ 10]*/ afi_rt_valid,
ddr1_afi[ 17],
/*ddr1_afi[ 16]=DQ[ 8]*/ afi_rt_addr_data,
ddr1_afi[ 15],
/*ddr1_afi[ 14]=DQ[ 70]*/ afi_tsr_div[6],
ddr1_afi[ 13],
/*ddr1_afi[ 12]=DQ[ 68]*/ afi_tsr_div[5],
ddr1_afi[ 11],
/*ddr1_afi[ 10]=DQ[ 66]*/ afi_tsr_div[4],
ddr1_afi[ 9],
/*ddr1_afi[ 8]=DQ[ 64]*/ afi_tsr_div[3],
ddr1_afi[ 7],
/*ddr1_afi[ 6]=DQ[ 6]*/ afi_tsr_div[2],
ddr1_afi[ 5],
/*ddr1_afi[ 4]=DQ[ 4]*/ afi_tsr_div[1],
ddr1_afi[ 3],
/*ddr1_afi[ 2]=DQ[ 2]*/ afi_rt_data_in[8],
ddr1_afi[ 1],
/*ddr1_afi[ 0]=DQ[ 0]*/ afi_rt_data_in[7]}),
.afo ({ddr1_afo[143:92],
/*ddr1_afo[ 91]=DQ[ 43]*/ afo_rt_data_out[12],
ddr1_afo[ 90],
/*ddr1_afo[ 89]=DQ[ 41]*/ afo_rt_data_out[11],
ddr1_afo[ 88: 52],
/*ddr1_afo[ 51]=DQ[ 27]*/ afo_rt_data_out[10],
ddr1_afo[ 50],
/*ddr1_afo[ 49]=DQ[ 25]*/ afo_rt_data_out[9],
ddr1_afo[ 48: 18],
/*ddr1_afo[ 17]=DQ[ 9]*/ afo_rt_ack,
ddr1_afo[ 16: 4],
/*ddr1_afo[ 3]=DQ[ 3]*/ afo_rt_data_out[8],
ddr1_afo[ 2],
/*ddr1_afo[ 1]=DQ[ 1]*/ afo_rt_data_out[7],
ddr1_afo[ 0]}),
/*AUTOINST*/
// Outputs
.ddr1_lpf_code (ctu_dll1_ctu_ctrl[4:0]), // Templated
.dram1_ck_p (DRAM1_CK_P[3:0]), // Templated
.dram1_ba (DRAM1_BA[2:0]), // Templated
.dram1_addr (DRAM1_ADDR[14:0]), // Templated
.dram1_ck_n (DRAM1_CK_N[3:0]), // Templated
.io_dram1_data_in (io_dram1_data_in[255:0]), // Templated
.io_dram1_ecc_in (io_dram1_ecc_in[31:0]), // Templated
.dram1_cs_l (DRAM1_CS_L[3:0]), // Templated
.ddr_so (pddr1_pjbusl_so), // Templated
.bscan_update_dr_out (), // Templated
.bscan_shift_dr_out (), // Templated
.bscan_clock_dr_out (), // Templated
.bscan_hiz_l_out (), // Templated
.bypass_enable_out (), // Templated
.ps_select_out (), // Templated
.bscan_mode_ctl_out (), // Templated
.pad_ddr1_bso (ddr1_jbusl_bso), // Templated
.dram1_cas_l (DRAM1_CAS_L), // Templated
.dram1_ras_l (DRAM1_RAS_L), // Templated
.dram1_cke (DRAM1_CKE), // Templated
.ddr1_ctu_dll_lock (ddr1_ctu_dll_lock),
.dram1_we_l (DRAM1_WE_L), // Templated
.ddr1_ctu_dll_overflow (ddr1_ctu_dll_overflow),
.io_dram1_data_valid (io_dram1_data_valid), // Templated
// Inouts
.spare_ddr1_pin (SPARE_DDR1_PIN[2:0]), // Templated
.spare_ddr1_pad (SPARE_DDR1_PAD[6:0]), // Templated
.dram1_dq (DRAM1_DQ[127:0]), // Templated
.dram1_cb (DRAM1_CB[15:0]), // Templated
.dram1_dqs (DRAM1_DQS[35:0]), // Templated
// Inputs
.ddr1_bypass_data (ctu_dll1_byp_val[4:0]), // Templated
.spare_ddr1_pindata (3'b010), // Templated
.spare_ddr1_paddata (7'b0101010), // Templated
.ddr0_ddr1_cbu (ddr0_ddr1_cbu[8:1]),
.dram1_io_ptr_clk_inv (dram1_io_ptr_clk_inv_buf2[4:0]), // Templated
.dram1_io_bank (dram1_io_bank_buf2[2:0]), // Templated
.dram_gclk ({dram_gclk_c0_r[7],dram_gclk_c0_r[5]}), // Templated
.ddr0_ddr1_cbd (ddr0_ddr1_cbd[8:1]),
.ctu_ddr1_dll_delayctr (ctu_ddr1_dll_delayctr[2:0]),
.dram1_io_cs_l (dram1_io_cs_l_buf2[3:0]), // Templated
.dram1_io_addr (dram1_io_addr_buf2[14:0]), // Templated
.dram1_io_data_out (dram1_io_data_out_buf2[287:0]), // Templated
.ddr_testmode_l (ctu_ddr_testmode_l), // Templated
.ddr1_dll_bypass_l (ctu_dll1_byp_l), // Templated
.bscan_mode_ctl_in (ctu_ddr1_mode_ctl), // Templated
.ps_select (pscan_select), // Templated
.ddr_se (global_shift_enable), // Templated
.ddr_si (pdbg_pddr1_so), // Templated
.bscan_hiz_l_in (ctu_ddr1_hiz_l), // Templated
.test_mode (io_test_mode), // Templated
.bypass_enable (global_scan_bypass_en), // Templated
.dram_arst_l (dram_arst_l),
.dram_gdbginit_l (dram_gdbginit_l),
.clk_ddr1_cken (ctu_ddr1_dram_cken), // Templated
.dram_grst_l (dram_grst_l),
.vdd18 (VDDL18), // Templated
.bscan_clock_dr_in (ctu_ddr1_clock_dr), // Templated
.ctu_ddr1_iodll_rst_l (ctu_ddr1_iodll_rst_l),
.dram1_io_pad_enable (dram1_io_pad_enable_buf2), // Templated
.pad_ddr1_bsi (ctu_ddr1_bso), // Templated
.dram_adbginit_l (dram_adbginit_l),
.bscan_shift_dr_in (ctu_ddr1_shift_dr), // Templated
.dram1_io_write_en_l (dram1_io_write_en_l_buf2), // Templated
.bscan_update_dr_in (ctu_ddr1_update_dr), // Templated
.dram1_io_drive_enable (dram1_io_drive_enable_buf2), // Templated
.dram1_io_cas_l (dram1_io_cas_l_buf2), // Templated
.dram1_io_ras_l (dram1_io_ras_l_buf2), // Templated
.dram1_io_clk_enable (dram1_io_clk_enable_buf2), // Templated
.dram1_io_channel_disabled (dram1_io_channel_disabled_buf2), // Templated
.dram1_io_drive_data (dram1_io_drive_data_buf2), // Templated
.dram1_io_cke (dram1_io_cke_buf2), // Templated
.dram1_io_pad_clk_inv (dram1_io_pad_clk_inv_buf2)); // Templated
`endif
//
/* pad_ddr2 AUTO_TEMPLATE (
.dram2_ras_l (DRAM2_RAS_L),
.dram2_cas_l (DRAM2_CAS_L),
.dram2_we_l (DRAM2_WE_L),
.dram2_cs_l (DRAM2_CS_L[]),
.dram2_cke (DRAM2_CKE),
.dram2_addr (DRAM2_ADDR[]),
.dram2_ba (DRAM2_BA[]),
.dram2_dq (DRAM2_DQ[]),
.dram2_cb (DRAM2_CB[]),
.dram2_dqs (DRAM2_DQS[]),
.dram2_ck_p (DRAM2_CK_P[]),
.dram2_ck_n (DRAM2_CK_N[]),
.dram23_p_ref_res (DRAM23_P_REF_RES),
.dram23_n_ref_res (DRAM23_N_REF_RES),
.spare_ddr2_pin (SPARE_DDR2_PIN[]),
.spare_ddr2_pindata (3'b010),
.spare_ddr2_pad (SPARE_DDR2_PAD[]),
.spare_ddr2_paddata (7'b0101010),
.dram_gclk ({dram_gclk_c3_r[3],dram_gclk_c3_r[1]}),
.io_pwron_rst_l (dram_arst_l),
.clk_ddr2_cken (ctu_ddr2_dram_cken),
.bscan_\(.*\)_out (),
.pad_ddr2_bsi (ddr3_ddr2_bso),
.ddr_si (pmisc_pddr2_so),
.bscan_\(.*\)_in (ctu_ddr2_\1),
.pad_ddr2_bso (ddr2_ddr2_bso),
.ddr_so (pddr2_rsc22_so),
.ddr_se (global_shift_enable),
.test_mode (io_test_mode),
.tck (ctu_ddr2_clock_dr),
.ddr_testmode_l (ctu_ddr_testmode_l),
.pad_ddr2_sscan_in (ddr2_ddr2_bso),
.pad_ddr2_sscan_out (ddr2_misc_sscan_out),
.ctu_io_sscan_se (ctu_ddr2_shift_dr),
.ctu_io_sscan_update (ctu_pads_sscan_update),
.bypass_enable (global_scan_bypass_en),
.bypass_enable_out (),
.ps_select (pscan_select),
.ps_select_out (),
.vdd18 (VDDR18),
.io_dram2_data_in (io_dram2_data_in[]),
.io_dram2_ecc_in (io_dram2_ecc_in[]),
.io_dram2_data_valid (io_dram2_data_valid),
.dram2_io_bank (dram2_io_bank_buf2[]),
.dram2_io_cs_l (dram2_io_cs_l_buf2[]),
.dram2_io_ptr_clk_inv (dram2_io_ptr_clk_inv_buf2[]),
.dram2_io_addr (dram2_io_addr_buf2[]),
.dram2_io_data_out (dram2_io_data_out_buf2[]),
.dram2_io_pad_enable (dram2_io_pad_enable_buf2),
.dram2_io_drive_enable (dram2_io_drive_enable_buf2),
.dram2_io_write_en_l (dram2_io_write_en_l_buf2),
.dram2_io_cas_l (dram2_io_cas_l_buf2),
.dram2_io_ras_l (dram2_io_ras_l_buf2),
.dram2_io_clk_enable (dram2_io_clk_enable_buf2),
.dram2_io_channel_disabled (dram2_io_channel_disabled_buf2),
.dram2_io_drive_data (dram2_io_drive_data_buf2),
.dram2_io_cke (dram2_io_cke_buf2),
.dram2_io_pad_clk_inv (dram2_io_pad_clk_inv_buf2),
.ddr2_dll_bypass_l (ctu_dll2_byp_l),
.ddr2_bypass_data (ctu_dll2_byp_val[]),
.ddr2_lpf_code (ctu_dll2_ctu_ctrl[]),
); */
//
`ifdef RTL_PAD_DDR2
pad_ddr2 pad_ddr2
(
.serial_out ({ddr2_sot[143:92],
/*ddr2_sot[ 91]=DQ[ 43]*/ ser_scan_out[24],
/*ddr2_sot[ 90]=DQ[ 42]*/ par_scan_head[24],
/*ddr2_sot[ 89]=DQ[ 41]*/ ser_scan_out[25],
/*ddr2_sot[ 88]=DQ[ 40]*/ par_scan_head[25],
ddr2_sot[ 87: 68],
/*ddr2_sot[ 67]=DQ[ 91]*/ ser_scan_out[26],
/*ddr2_sot[ 66]=DQ[ 90]*/ par_scan_head[26],
/*ddr2_sot[ 65]=DQ[ 89]*/ ser_scan_out[27],
/*ddr2_sot[ 64]=DQ[ 88]*/ par_scan_head[27],
ddr2_sot[ 63: 36],
/*ddr2_sot[ 35]=DQ[ 19]*/ ser_scan_out[28],
/*ddr2_sot[ 34]=DQ[ 18]*/ par_scan_head[28],
/*ddr2_sot[ 33]=DQ[ 17]*/ ser_scan_out[29],
/*ddr2_sot[ 32]=DQ[ 16]*/ par_scan_head[29],
ddr2_sot[ 31: 18],
/*ddr2_sot[ 17]=DQ[ 9]*/ ser_scan_out[30],
/*ddr2_sot[ 16]=DQ[ 8]*/ par_scan_head[30],
ddr2_sot[ 15: 0]}),
.serial_in ({ddr2_sin[143:92],
/*ddr2_sin[ 91]=DQ[ 43]*/ par_scan_tail[24],
/*ddr2_sin[ 90]=DQ[ 42]*/ ser_scan_out[23],
/*ddr2_sin[ 89]=DQ[ 41]*/ par_scan_tail[25],
/*ddr2_sin[ 88]=DQ[ 40]*/ ser_scan_out[24],
ddr2_sin[ 87: 68],
/*ddr2_sin[ 67]=DQ[ 91]*/ par_scan_tail[26],
/*ddr2_sin[ 66]=DQ[ 90]*/ ser_scan_out[25],
/*ddr2_sin[ 65]=DQ[ 89]*/ par_scan_tail[27],
/*ddr2_sin[ 64]=DQ[ 88]*/ ser_scan_out[26],
ddr2_sin[ 63: 36],
/*ddr2_sin[ 35]=DQ[ 19]*/ par_scan_tail[28],
/*ddr2_sin[ 34]=DQ[ 18]*/ ser_scan_out[27],
/*ddr2_sin[ 33]=DQ[ 17]*/ par_scan_tail[29],
/*ddr2_sin[ 32]=DQ[ 16]*/ ser_scan_out[28],
ddr2_sin[ 31: 18],
/*ddr2_sin[ 17]=DQ[ 9]*/ par_scan_tail[30],
/*ddr2_sin[ 16]=DQ[ 8]*/ ser_scan_out[29],
ddr2_sin[ 15: 0]}),
.afi ({ddr2_afi[143: 91],
/*ddr2_afi[ 90]=DQ[ 42]*/ afi_rt_data_in[24],
ddr2_afi[ 89],
/*ddr2_afi[ 88]=DQ[ 40]*/ afi_rt_data_in[25],
ddr2_afi[ 87: 67],
/*ddr2_afi[ 66]=DQ[ 90]*/ afi_rt_data_in[26],
ddr2_afi[ 65],
/*ddr2_afi[ 64]=DQ[ 88]*/ afi_rt_data_in[27],
ddr2_afi[ 63: 35],
/*ddr2_afi[ 34]=DQ[ 18]*/ afi_rt_data_in[28],
ddr2_afi[ 33],
/*ddr2_afi[ 32]=DQ[ 16]*/ afi_rt_data_in[29],
ddr2_afi[ 31: 17],
/*ddr2_afi[ 16]=DQ[ 8]*/ afi_rt_data_in[30],
ddr2_afi[ 15: 3],
/*ddr2_afi[ 2]=DQ[ 2]*/ afi_rt_data_in[31],
ddr2_afi[ 1: 0]}),
.afo ({ddr2_afo[143:92],
/*ddr2_afo[ 91]=DQ[ 43]*/ afo_rt_data_out[24],
ddr2_afo[ 90],
/*ddr2_afo[ 89]=DQ[ 41]*/ afo_rt_data_out[25],
ddr2_afo[ 88: 68],
/*ddr2_afo[ 67]=DQ[ 91]*/ afo_rt_data_out[26],
ddr2_afo[ 66],
/*ddr2_afo[ 65]=DQ[ 89]*/ afo_rt_data_out[27],
ddr2_afo[ 64: 36],
/*ddr2_afo[ 35]=DQ[ 19]*/ afo_rt_data_out[28],
ddr2_afo[ 34],
/*ddr2_afo[ 33]=DQ[ 17]*/ afo_rt_data_out[29],
ddr2_afo[ 32: 18],
/*ddr2_afo[ 17]=DQ[ 9]*/ afo_rt_data_out[30],
ddr2_afo[ 16: 4],
/*ddr2_afo[ 3]=DQ[ 3]*/ afo_rt_data_out[31],
ddr2_afo[ 2: 0]}),
/*AUTOINST*/
// Outputs
.ddr2_lpf_code (ctu_dll2_ctu_ctrl[4:0]), // Templated
.dram2_ba (DRAM2_BA[2:0]), // Templated
.dram2_ck_p (DRAM2_CK_P[3:0]), // Templated
.ddr2_ddr3_cbd (ddr2_ddr3_cbd[8:1]),
.dram2_addr (DRAM2_ADDR[14:0]), // Templated
.dram2_ck_n (DRAM2_CK_N[3:0]), // Templated
.ddr2_ddr3_cbu (ddr2_ddr3_cbu[8:1]),
.io_dram2_data_in (io_dram2_data_in[255:0]), // Templated
.io_dram2_ecc_in (io_dram2_ecc_in[31:0]), // Templated
.dram2_cs_l (DRAM2_CS_L[3:0]), // Templated
.pad_ddr2_sscan_out (ddr2_misc_sscan_out), // Templated
.dram2_cas_l (DRAM2_CAS_L), // Templated
.dram2_ras_l (DRAM2_RAS_L), // Templated
.dram2_cke (DRAM2_CKE), // Templated
.bypass_enable_out (), // Templated
.bscan_shift_dr_out (), // Templated
.bscan_clock_dr_out (), // Templated
.bscan_hiz_l_out (), // Templated
.ps_select_out (), // Templated
.bscan_update_dr_out (), // Templated
.ddr2_ctu_dll_overflow (ddr2_ctu_dll_overflow),
.bscan_mode_ctl_out (), // Templated
.ddr_so (pddr2_rsc22_so), // Templated
.pad_ddr2_bso (ddr2_ddr2_bso), // Templated
.dram2_we_l (DRAM2_WE_L), // Templated
.ddr2_ctu_dll_lock (ddr2_ctu_dll_lock),
.io_dram2_data_valid (io_dram2_data_valid), // Templated
// Inouts
.spare_ddr2_pin (SPARE_DDR2_PIN[2:0]), // Templated
.spare_ddr2_pad (SPARE_DDR2_PAD[6:0]), // Templated
.dram2_dq (DRAM2_DQ[127:0]), // Templated
.dram2_cb (DRAM2_CB[15:0]), // Templated
.dram2_dqs (DRAM2_DQS[35:0]), // Templated
// Inputs
.ddr2_bypass_data (ctu_dll2_byp_val[4:0]), // Templated
.dram2_io_bank (dram2_io_bank_buf2[2:0]), // Templated
.ctu_ddr2_dll_delayctr (ctu_ddr2_dll_delayctr[2:0]),
.dram2_io_cs_l (dram2_io_cs_l_buf2[3:0]), // Templated
.dram_gclk ({dram_gclk_c3_r[3],dram_gclk_c3_r[1]}), // Templated
.dram2_io_ptr_clk_inv (dram2_io_ptr_clk_inv_buf2[4:0]), // Templated
.spare_ddr2_paddata (7'b0101010), // Templated
.dram2_io_addr (dram2_io_addr_buf2[14:0]), // Templated
.dram2_io_data_out (dram2_io_data_out_buf2[287:0]), // Templated
.spare_ddr2_pindata (3'b010), // Templated
.ddr2_dll_bypass_l (ctu_dll2_byp_l), // Templated
.clk_ddr2_cken (ctu_ddr2_dram_cken), // Templated
.bscan_mode_ctl_in (ctu_ddr2_mode_ctl), // Templated
.bscan_hiz_l_in (ctu_ddr2_hiz_l), // Templated
.ddr_si (pmisc_pddr2_so), // Templated
.tck (ctu_ddr2_clock_dr), // Templated
.pad_ddr2_sscan_in (ddr2_ddr2_bso), // Templated
.ddr_testmode_l (ctu_ddr_testmode_l), // Templated
.bypass_enable (global_scan_bypass_en), // Templated
.vdd18 (VDDR18), // Templated
.pad_ddr2_bsi (ddr3_ddr2_bso), // Templated
.dram_arst_l (dram_arst_l),
.dram_grst_l (dram_grst_l),
.ctu_global_snap (ctu_global_snap),
.dram_gdbginit_l (dram_gdbginit_l),
.ctu_ddr2_iodll_rst_l (ctu_ddr2_iodll_rst_l),
.test_mode (io_test_mode), // Templated
.bscan_clock_dr_in (ctu_ddr2_clock_dr), // Templated
.ctu_io_sscan_update (ctu_pads_sscan_update), // Templated
.ctu_io_sscan_se (ctu_ddr2_shift_dr), // Templated
.dram23_p_ref_res (DRAM23_P_REF_RES), // Templated
.ps_select (pscan_select), // Templated
.dram23_n_ref_res (DRAM23_N_REF_RES), // Templated
.ddr_se (global_shift_enable), // Templated
.dram_adbginit_l (dram_adbginit_l),
.bscan_shift_dr_in (ctu_ddr2_shift_dr), // Templated
.dram2_io_pad_enable (dram2_io_pad_enable_buf2), // Templated
.bscan_update_dr_in (ctu_ddr2_update_dr), // Templated
.dram2_io_drive_enable (dram2_io_drive_enable_buf2), // Templated
.dram2_io_write_en_l (dram2_io_write_en_l_buf2), // Templated
.dram2_io_cas_l (dram2_io_cas_l_buf2), // Templated
.dram2_io_ras_l (dram2_io_ras_l_buf2), // Templated
.dram2_io_clk_enable (dram2_io_clk_enable_buf2), // Templated
.dram2_io_channel_disabled (dram2_io_channel_disabled_buf2), // Templated
.dram2_io_drive_data (dram2_io_drive_data_buf2), // Templated
.dram2_io_cke (dram2_io_cke_buf2), // Templated
.dram2_io_pad_clk_inv (dram2_io_pad_clk_inv_buf2)); // Templated
`endif
//
/* pad_ddr3 AUTO_TEMPLATE (
.dram3_ras_l (DRAM3_RAS_L),
.dram3_cas_l (DRAM3_CAS_L),
.dram3_we_l (DRAM3_WE_L),
.dram3_cs_l (DRAM3_CS_L[]),
.dram3_cke (DRAM3_CKE),
.dram3_addr (DRAM3_ADDR[]),
.dram3_ba (DRAM3_BA[]),
.dram3_dq (DRAM3_DQ[]),
.dram3_cb (DRAM3_CB[]),
.dram3_dqs (DRAM3_DQS[]),
.dram3_ck_p (DRAM3_CK_P[]),
.dram3_ck_n (DRAM3_CK_N[]),
.spare_ddr3_pin (SPARE_DDR3_PIN[]),
.spare_ddr3_pindata (3'b010),
.spare_ddr3_pad (SPARE_DDR3_PAD[]),
.spare_ddr3_paddata (7'b0101010),
.dram_gclk ({dram_gclk_c3_r[7],dram_gclk_c3_r[5]}),
.clk_ddr3_cken (ctu_ddr3_dram_cken),
.bscan_\(.*\)_out (),
.pad_ddr3_bsi (jbusr_ddr3_sscan_out),
.ddr_si (par_scan_head[21]),
.bscan_\(.*\)_in (ctu_ddr3_\1),
.pad_ddr3_bso (ddr3_ddr2_bso),
.ddr_so (pddr3_pjbusr_so),
.ddr_se (global_shift_enable),
.test_mode (io_test_mode),
.ddr_testmode_l (ctu_ddr_testmode_l),
.bypass_enable (global_scan_bypass_en),
.bypass_enable_out (),
.ps_select (pscan_select),
.ps_select_out (),
.vdd18 (VDDR18),
.dram3_io_ptr_clk_inv (dram3_io_ptr_clk_inv_buf2[]),
.dram3_io_addr (dram3_io_addr_buf2[]),
.dram3_io_data_out (dram3_io_data_out_buf2[]),
.dram3_io_cs_l (dram3_io_cs_l_buf2[]),
.dram3_io_bank (dram3_io_bank_buf2[]),
.dram3_io_write_en_l (dram3_io_write_en_l_buf2),
.dram3_io_ras_l (dram3_io_ras_l_buf2),
.dram3_io_cke (dram3_io_cke_buf2),
.dram3_io_drive_data (dram3_io_drive_data_buf2),
.dram3_io_pad_enable (dram3_io_pad_enable_buf2),
.dram3_io_drive_enable (dram3_io_drive_enable_buf2),
.dram3_io_channel_disabled (dram3_io_channel_disabled_buf2),
.dram3_io_cas_l (dram3_io_cas_l_buf2),
.dram3_io_clk_enable (dram3_io_clk_enable_buf2),
.dram3_io_pad_clk_inv (dram3_io_pad_clk_inv_buf2),
.ddr3_dll_bypass_l (ctu_dll3_byp_l),
.ddr3_bypass_data (ctu_dll3_byp_val[]),
.ddr3_lpf_code (ctu_dll3_ctu_ctrl[]),
); */
//
`ifdef RTL_PAD_DDR3
pad_ddr3 pad_ddr3
(
.serial_out ({ddr3_sot[143: 76],
/*ddr3_sot[ 75]=DQ[ 35]*/ ser_scan_out[18],
/*ddr3_sot[ 74]=DQ[ 34]*/ par_scan_head[18],
/*ddr3_sot[ 73]=DQ[ 33]*/ ser_scan_out[19],
/*ddr3_sot[ 72]=DQ[ 32]*/ par_scan_head[19],
ddr3_sot[ 71: 52],
/*ddr3_sot[ 51]=DQ[ 27]*/ ser_scan_out[20],
/*ddr3_sot[ 50]=DQ[ 26]*/ par_scan_head[20],
/*ddr3_sot[ 49]=DQ[ 25]*/ ser_scan_out[21],
/*ddr3_sot[ 48]=DQ[ 24]*/ par_scan_head[21],
ddr3_sot[ 47: 36],
/*ddr3_sot[ 35]=DQ[ 19]*/ ser_scan_out[22],
/*ddr3_sot[ 34]=DQ[ 18]*/ par_scan_head[22],
/*ddr3_sot[ 33]=DQ[ 17]*/ ser_scan_out[23],
/*ddr3_sot[ 32]=DQ[ 16]*/ par_scan_head[23],
ddr3_sot[ 31: 0]}),
.serial_in ({ddr3_sin[143: 76],
/*ddr3_sin[ 75]=DQ[ 35]*/ par_scan_tail[18],
/*ddr3_sin[ 74]=DQ[ 34]*/ ser_scan_out[17],
/*ddr3_sin[ 73]=DQ[ 33]*/ par_scan_tail[19],
/*ddr3_sin[ 72]=DQ[ 32]*/ ser_scan_out[18],
ddr3_sin[ 71: 52],
/*ddr3_sin[ 51]=DQ[ 27]*/ par_scan_tail[20],
/*ddr3_sin[ 50]=DQ[ 26]*/ ser_scan_out[19],
/*ddr3_sin[ 49]=DQ[ 25]*/ par_scan_tail[21],
/*ddr3_sin[ 48]=DQ[ 24]*/ ser_scan_out[20],
ddr3_sin[ 47: 36],
/*ddr3_sin[ 35]=DQ[ 19]*/ par_scan_tail[22],
/*ddr3_sin[ 34]=DQ[ 18]*/ ser_scan_out[21],
/*ddr3_sin[ 33]=DQ[ 17]*/ par_scan_tail[23],
/*ddr3_sin[ 32]=DQ[ 16]*/ ser_scan_out[22],
ddr3_sin[ 31: 0]}),
.afi ({ddr3_afi[143:121],
/*ddr3_afi[ 120]=DQ[ 56]*/ afi_rt_data_in[13],
ddr3_afi[119:107],
/*ddr3_afi[ 106]=DQ[ 50]*/ afi_rt_data_in[14],
ddr3_afi[ 105],
/*ddr3_afi[ 104]=DQ[ 48]*/ afi_rt_data_in[15],
ddr3_afi[103: 91],
/*ddr3_afi[ 90]=DQ[ 42]*/ afi_rt_data_in[16],
ddr3_afi[ 89],
/*ddr3_afi[ 88]=DQ[ 40]*/ afi_rt_data_in[17],
ddr3_afi[ 87: 75],
/*ddr3_afi[ 74]=DQ[ 34]*/ afi_rt_data_in[18],
ddr3_afi[ 73],
/*ddr3_afi[ 72]=DQ[ 32]*/ afi_rt_data_in[19],
ddr3_afi[ 71: 51],
/*ddr3_afi[ 50]=DQ[ 26]*/ afi_rt_data_in[20],
ddr3_afi[ 49],
/*ddr3_afi[ 48]=DQ[ 24]*/ afi_rt_data_in[21],
ddr3_afi[ 47: 35],
/*ddr3_afi[ 34]=DQ[ 18]*/ afi_rt_data_in[22],
ddr3_afi[ 33],
/*ddr3_afi[ 32]=DQ[ 16]*/ afi_rt_data_in[23],
ddr3_afi[ 31: 0]}),
.afo ({ddr3_afo[143:122],
/*ddr3_afo[ 121]=DQ[ 57]*/ afo_rt_data_out[13],
ddr3_afo[120:108],
/*ddr3_afo[ 107]=DQ[ 51]*/ afo_rt_data_out[14],
ddr3_afo[ 106],
/*ddr3_afo[ 105]=DQ[ 49]*/ afo_rt_data_out[15],
ddr3_afo[104:92],
/*ddr3_afo[ 91]=DQ[ 43]*/ afo_rt_data_out[16],
ddr3_afo[ 90],
/*ddr3_afo[ 89]=DQ[ 41]*/ afo_rt_data_out[17],
ddr3_afo[ 88: 76],
/*ddr3_afo[ 75]=DQ[ 35]*/ afo_rt_data_out[18],
ddr3_afo[ 74],
/*ddr3_afo[ 73]=DQ[ 33]*/ afo_rt_data_out[19],
ddr3_afo[ 72: 52],
/*ddr3_afo[ 51]=DQ[ 27]*/ afo_rt_data_out[20],
ddr3_afo[ 50],
/*ddr3_afo[ 49]=DQ[ 25]*/ afo_rt_data_out[21],
ddr3_afo[ 48: 36],
/*ddr3_afo[ 35]=DQ[ 19]*/ afo_rt_data_out[22],
ddr3_afo[ 34],
/*ddr3_afo[ 33]=DQ[ 17]*/ afo_rt_data_out[23],
ddr3_afo[ 32: 0]}),
/*AUTOINST*/
// Outputs
.ddr3_lpf_code (ctu_dll3_ctu_ctrl[4:0]), // Templated
.dram3_ck_p (DRAM3_CK_P[3:0]), // Templated
.dram3_ba (DRAM3_BA[2:0]), // Templated
.dram3_addr (DRAM3_ADDR[14:0]), // Templated
.dram3_ck_n (DRAM3_CK_N[3:0]), // Templated
.io_dram3_data_in (io_dram3_data_in[255:0]),
.io_dram3_ecc_in (io_dram3_ecc_in[31:0]),
.dram3_cs_l (DRAM3_CS_L[3:0]), // Templated
.bscan_mode_ctl_out (), // Templated
.pad_ddr3_bso (ddr3_ddr2_bso), // Templated
.dram3_cas_l (DRAM3_CAS_L), // Templated
.dram3_ras_l (DRAM3_RAS_L), // Templated
.dram3_cke (DRAM3_CKE), // Templated
.bscan_hiz_l_out (), // Templated
.bypass_enable_out (), // Templated
.bscan_shift_dr_out (), // Templated
.bscan_clock_dr_out (), // Templated
.bscan_update_dr_out (), // Templated
.ddr_so (pddr3_pjbusr_so), // Templated
.ps_select_out (), // Templated
.ddr3_ctu_dll_lock (ddr3_ctu_dll_lock),
.dram3_we_l (DRAM3_WE_L), // Templated
.ddr3_ctu_dll_overflow (ddr3_ctu_dll_overflow),
.io_dram3_data_valid (io_dram3_data_valid),
// Inouts
.spare_ddr3_pad (SPARE_DDR3_PAD[6:0]), // Templated
.spare_ddr3_pin (SPARE_DDR3_PIN[2:0]), // Templated
.dram3_dq (DRAM3_DQ[127:0]), // Templated
.dram3_cb (DRAM3_CB[15:0]), // Templated
.dram3_dqs (DRAM3_DQS[35:0]), // Templated
// Inputs
.spare_ddr3_paddata (7'b0101010), // Templated
.ddr3_bypass_data (ctu_dll3_byp_val[4:0]), // Templated
.spare_ddr3_pindata (3'b010), // Templated
.dram_gclk ({dram_gclk_c3_r[7],dram_gclk_c3_r[5]}), // Templated
.ddr2_ddr3_cbd (ddr2_ddr3_cbd[8:1]),
.ctu_ddr3_dll_delayctr (ctu_ddr3_dll_delayctr[2:0]),
.dram3_io_bank (dram3_io_bank_buf2[2:0]), // Templated
.dram3_io_ptr_clk_inv (dram3_io_ptr_clk_inv_buf2[4:0]), // Templated
.dram3_io_cs_l (dram3_io_cs_l_buf2[3:0]), // Templated
.dram3_io_addr (dram3_io_addr_buf2[14:0]), // Templated
.ddr2_ddr3_cbu (ddr2_ddr3_cbu[8:1]),
.dram3_io_data_out (dram3_io_data_out_buf2[287:0]), // Templated
.ps_select (pscan_select), // Templated
.bscan_mode_ctl_in (ctu_ddr3_mode_ctl), // Templated
.ddr_testmode_l (ctu_ddr_testmode_l), // Templated
.bscan_clock_dr_in (ctu_ddr3_clock_dr), // Templated
.ddr3_dll_bypass_l (ctu_dll3_byp_l), // Templated
.dram_adbginit_l (dram_adbginit_l),
.clk_ddr3_cken (ctu_ddr3_dram_cken), // Templated
.dram_arst_l (dram_arst_l),
.dram_gdbginit_l (dram_gdbginit_l),
.bscan_hiz_l_in (ctu_ddr3_hiz_l), // Templated
.dram3_io_pad_enable (dram3_io_pad_enable_buf2), // Templated
.vdd18 (VDDR18), // Templated
.ctu_ddr3_iodll_rst_l (ctu_ddr3_iodll_rst_l),
.bypass_enable (global_scan_bypass_en), // Templated
.pad_ddr3_bsi (jbusr_ddr3_sscan_out), // Templated
.test_mode (io_test_mode), // Templated
.ddr_si (par_scan_head[21]), // Templated
.dram_grst_l (dram_grst_l),
.ddr_se (global_shift_enable), // Templated
.bscan_shift_dr_in (ctu_ddr3_shift_dr), // Templated
.dram3_io_write_en_l (dram3_io_write_en_l_buf2), // Templated
.bscan_update_dr_in (ctu_ddr3_update_dr), // Templated
.dram3_io_drive_enable (dram3_io_drive_enable_buf2), // Templated
.dram3_io_cas_l (dram3_io_cas_l_buf2), // Templated
.dram3_io_ras_l (dram3_io_ras_l_buf2), // Templated
.dram3_io_clk_enable (dram3_io_clk_enable_buf2), // Templated
.dram3_io_channel_disabled (dram3_io_channel_disabled_buf2), // Templated
.dram3_io_drive_data (dram3_io_drive_data_buf2), // Templated
.dram3_io_cke (dram3_io_cke_buf2), // Templated
.dram3_io_pad_clk_inv (dram3_io_pad_clk_inv_buf2)); // Templated
`endif
//
/* pad_efc AUTO_TEMPLATE (
.vpp (VPP),
.vddo (VDDCO),
); */
//
`ifdef RTL_PAD_EFC
pad_efc pad_efc
(/*AUTOINST*/
// Inouts
.vpp (VPP), // Templated
.vddo (VDDCO)); // Templated
`endif
//
/* pad_jbusr AUTO_TEMPLATE (
.j_ad (J_AD[]),
.j_adp (J_ADP[]),
.j_adtype (J_ADTYPE[]),
.j_par (J_PAR),
.j_pack0 (J_PACK0[]),
.j_pack1 (J_PACK1[]),
.j_pack4 (J_PACK4[]),
.j_pack5 (J_PACK5[]),
.j_req0_out_l (J_REQ0_OUT_L),
.j_req1_out_l (J_REQ1_OUT_L),
.j_req4_in_l (J_REQ4_IN_L),
.j_req5_in_l (J_REQ5_IN_L),
.j_err (J_ERR),
.j_rst_l (J_RST_L),
.dtl_r_vref (DTL_R_VREF),
.jbus_p_ref_res (JBUS_P_REF_RES),
.jbus_n_ref_res (JBUS_N_REF_RES),
.spare_jbusr_pin (SPARE_JBUSR_PIN[]),
.spare_jbusr_to_core (),
.spare_jbusr_data (1'b0),
.spare_jbusr_oe (1'b0),
.io_jbi_j_rst_l (io_j_rst_l),
.jbi_io_j_err (ctu_io_j_err),
.jbus_gclk (jbus_gclk_c3_r[7]),
.clk_jbusr_cken (ctu_jbusr_jbus_cken),
.jbus_grst_l (1'b1),
.bscan_\(.*\)_out (),
.pad_jbusr_bsi (jbusl_jbusr_bso),
.pad_jbusr_si (pddr3_pjbusr_so),
.bscan_\(.*\)_in (ctu_jbusr_\1),
.pad_jbusr_bso (jbusr_jbusr_bso),
.pad_jbusr_so (pjbusr_rptrs_so),
.pad_jbusr_se (global_shift_enable),
.ctu_io_sscan_se (ctu_jbusr_shift_dr),
.ctu_io_sscan_update (ctu_pads_sscan_update),
.pad_jbusr_sscan_out (jbusr_ddr3_sscan_out),
.pad_jbusr_sscan_in (jbusr_jbusr_bso),
.bypass_enable (global_scan_bypass_en),
.bypass_enable_out (),
.ps_select (pscan_select),
.ps_select_out (),
.por_l (jbus_arst_l),
.hard_rst_l (jbus_grst_l),
.rst_io_l (1'b1),
.rst_val_dn (1'b1),
.rst_val_up (1'b1),
.scan_mode (1'b0),
.sel_bypass (1'b0),
.up_open (1'b0),
.down_25 (1'b0),
.tclk (ctu_jbusr_clock_dr),
.jbi_io_j_par_en (1'b0),
.jbi_io_j_par (1'b0),
.jbi_io_dsbl_sampling (1'b0),
.jbi_io_j_req1_out_en (jbi_io_j_req0_out_en),
.jbi_io_j_req1_out_l (jbi_io_j_req0_out_l),
.vddo (VDDBO),
); */
//
`ifdef RTL_PAD_JBUSR
pad_jbusr pad_jbusr
(
.serial_out ({jbusr_sot[ 56: 39],
/*jbusr_sot[ 38]=J_AD[38]*/ par_scan_head[15],
/*jbusr_sot[ 37]=J_AD[37]*/ ser_scan_out[15],
jbusr_sot[ 36: 35],
/*jbusr_sot[ 34]=J_AD[32]*/ par_scan_head[16],
/*jbusr_sot[ 33]=J_AD[33]*/ ser_scan_out[16],
jbusr_sot[ 32: 14],
/*jbusr_sot[ 13]=J_AD[13]*/ par_scan_head[17],
/*jbusr_sot[ 12]=J_AD[12]*/ ser_scan_out[17],
jbusr_sot[ 11: 0]}),
.serial_in ({jbusr_sin[ 56: 39],
/*jbusr_sin[ 38]=J_AD[38]*/ ser_scan_out[14],
/*jbusr_sin[ 37]=J_AD[37]*/ par_scan_tail[15],
jbusr_sin[ 36: 35],
/*jbusr_sin[ 34]=J_AD[34]*/ ser_scan_out[15],
/*jbusr_sin[ 33]=J_AD[33]*/ par_scan_tail[16],
jbusr_sin[ 32: 14],
/*jbusr_sin[ 13]=J_AD[13]*/ ser_scan_out[16],
/*jbusr_sin[ 12]=J_AD[12]*/ par_scan_tail[17],
jbusr_sin[ 11: 0]}),
/*AUTOINST*/
// Outputs
.j_pack1 (J_PACK1[2:0]), // Templated
.j_pack0 (J_PACK0[2:0]), // Templated
.io_jbi_j_ad (io_jbi_j_ad[56:0]),
.spare_jbusr_to_core (), // Templated
.io_jbi_j_adtype (io_jbi_j_adtype[7:0]),
.io_jbi_j_pack4 (io_jbi_j_pack4[2:0]),
.io_jbi_j_adp (io_jbi_j_adp[3:0]),
.io_jbi_j_pack5 (io_jbi_j_pack5[2:0]),
.jbusr_jbusl_cbu (jbusr_jbusl_cbu[8:1]),
.jbusr_jbusl_cbd (jbusr_jbusl_cbd[8:1]),
.bscan_hiz_l_out (), // Templated
.bscan_update_dr_out (), // Templated
.bscan_clock_dr_out (), // Templated
.bscan_shift_dr_out (), // Templated
.bscan_mode_ctl_out (), // Templated
.j_req1_out_l (J_REQ1_OUT_L), // Templated
.ps_select_out (), // Templated
.bypass_enable_out (), // Templated
.j_req0_out_l (J_REQ0_OUT_L), // Templated
.pad_jbusr_sscan_out (jbusr_ddr3_sscan_out), // Templated
.pad_jbusr_so (pjbusr_rptrs_so), // Templated
.pad_jbusr_bso (jbusr_jbusr_bso), // Templated
.j_err (J_ERR), // Templated
.io_jbi_j_req5_in_l (io_jbi_j_req5_in_l),
.io_jbi_j_req4_in_l (io_jbi_j_req4_in_l),
.io_jbi_j_par (io_jbi_j_par),
.io_jbi_j_rst_l (io_j_rst_l), // Templated
// Inouts
.j_adp (J_ADP[3:0]), // Templated
.j_adtype (J_ADTYPE[7:0]), // Templated
.j_ad (J_AD[56:0]), // Templated
.spare_jbusr_pin (SPARE_JBUSR_PIN[0:0]), // Templated
.dtl_r_vref (DTL_R_VREF), // Templated
.j_par (J_PAR), // Templated
// Inputs
.jbi_io_j_ad (jbi_io_j_ad[56:0]),
.j_pack5 (J_PACK5[2:0]), // Templated
.j_pack4 (J_PACK4[2:0]), // Templated
.jbi_io_config_dtl (jbi_io_config_dtl[1:0]),
.jbi_io_j_adtype (jbi_io_j_adtype[7:0]),
.jbi_io_j_ad_en (jbi_io_j_ad_en[1:0]),
.jbi_io_j_pack0 (jbi_io_j_pack0[2:0]),
.jbi_io_j_pack1 (jbi_io_j_pack1[2:0]),
.spare_jbusr_data (1'b0), // Templated
.jbi_io_j_adp (jbi_io_j_adp[3:0]),
.spare_jbusr_oe (1'b0), // Templated
.bscan_clock_dr_in (ctu_jbusr_clock_dr), // Templated
.jbus_n_ref_res (JBUS_N_REF_RES), // Templated
.j_req4_in_l (J_REQ4_IN_L), // Templated
.jbus_p_ref_res (JBUS_P_REF_RES), // Templated
.jbi_io_j_req1_out_en (jbi_io_j_req0_out_en), // Templated
.jbi_io_j_req1_out_l (jbi_io_j_req0_out_l), // Templated
.ps_select (pscan_select), // Templated
.bypass_enable (global_scan_bypass_en), // Templated
.clk_jbusr_cken (ctu_jbusr_jbus_cken), // Templated
.jbus_gclk (jbus_gclk_c3_r[7]), // Templated
.jbus_grst_l (1'b1), // Templated
.jbus_arst_l (jbus_arst_l),
.jbus_gdbginit_l (jbus_gdbginit_l),
.jbus_adbginit_l (jbus_adbginit_l),
.pad_jbusr_se (global_shift_enable), // Templated
.bscan_shift_dr_in (ctu_jbusr_shift_dr), // Templated
.jbi_io_j_err (ctu_io_j_err), // Templated
.tclk (ctu_jbusr_clock_dr), // Templated
.pad_jbusr_si (pddr3_pjbusr_so), // Templated
.pad_jbusr_bsi (jbusl_jbusr_bso), // Templated
.vddo (VDDBO), // Templated
.rst_val_up (1'b1), // Templated
.bscan_hiz_l_in (ctu_jbusr_hiz_l), // Templated
.sel_bypass (1'b0), // Templated
.bscan_mode_ctl_in (ctu_jbusr_mode_ctl), // Templated
.bscan_update_dr_in (ctu_jbusr_update_dr), // Templated
.rst_val_dn (1'b1), // Templated
.rst_io_l (1'b1), // Templated
.por_l (jbus_arst_l), // Templated
.jbi_io_j_adp_en (jbi_io_j_adp_en),
.jbi_io_j_pack0_en (jbi_io_j_pack0_en),
.jbi_io_j_pack1_en (jbi_io_j_pack1_en),
.jbi_io_j_adtype_en (jbi_io_j_adtype_en),
.hard_rst_l (jbus_grst_l), // Templated
.jbi_io_j_par_en (1'b0), // Templated
.jbi_io_j_req0_out_en (jbi_io_j_req0_out_en),
.ctu_io_sscan_update (ctu_pads_sscan_update), // Templated
.jbi_io_j_req0_out_l (jbi_io_j_req0_out_l),
.jbi_io_j_par (1'b0), // Templated
.pad_jbusr_sscan_in (jbusr_jbusr_bso), // Templated
.ctu_io_sscan_se (ctu_jbusr_shift_dr), // Templated
.j_req5_in_l (J_REQ5_IN_L), // Templated
.j_rst_l (J_RST_L), // Templated
.ctu_global_snap (ctu_global_snap));
`endif
//
/* pad_jbusl AUTO_TEMPLATE (
.jbus_gclk (jbus_gclk_c0_r[7]),
.clk_jbusl_cken (ctu_jbusl_jbus_cken),
.jbus_grst_l (1'b1),
.j_ad (J_AD[]),
.dtl_l_vref (DTL_L_VREF),
.bscan_\(.*\)_out (),
.pad_jbusl_bsi (ddr1_jbusl_bso),
.pad_jbusl_si (pddr1_pjbusl_so),
.bscan_\(.*\)_in (ctu_jbusl_\1),
.pad_jbusl_bso (jbusl_jbusr_bso),
.pad_jbusl_so (pjbusl_rptrs_so),
.pad_jbusl_se (global_shift_enable),
.bypass_enable (global_scan_bypass_en),
.bypass_enable_out (),
.ps_select (pscan_select),
.ps_select_out (),
.por_l (jbus_arst_l),
.rst_io_l (1'b1),
.rst_val_dn (1'b1),
.rst_val_up (1'b1),
.scan_mode (1'b0),
.up_open (1'b0),
.down_25 (1'b0),
.sel_bypass (1'b0),
.jbi_io_dsbl_sampling (1'b0),
.jbi_io_config_dtl_chunk0 (jbi_io_config_dtl[0]), // Same as other chunks.
.jbi_io_j_ad_en_chunk56 (jbi_io_j_ad_en[3]), // Same as other chunks.
.vddo (VDDBO),
); */
//
`ifdef RTL_PAD_JBUSL
pad_jbusl pad_jbusl
(
.serial_out ({jbusl_sot[127:110],
/*jbusl_sot[ 109]=J_AD[109]*/ par_scan_head[13],
/*jbusl_sot[ 108]=J_AD[108]*/ ser_scan_out[13],
jbusl_sot[107:106],
/*jbusl_sot[ 105]=J_AD[105]*/ par_scan_head[14],
/*jbusl_sot[ 104]=J_AD[104]*/ ser_scan_out[14],
jbusl_sot[103: 57]}),
.serial_in ({jbusl_sin[127:110],
/*jbusl_sin[ 109]=J_AD[109]*/ ser_scan_out[12],
/*jbusl_sin[ 108]=J_AD[108]*/ par_scan_tail[13],
jbusl_sin[107:106],
/*jbusl_sin[ 105]=J_AD[105]*/ ser_scan_out[13],
/*jbusl_sin[ 104]=J_AD[104]*/ par_scan_tail[14],
jbusl_sin[103: 57]}),
/*AUTOINST*/
// Outputs
.io_jbi_j_ad (io_jbi_j_ad[127:57]),
.bscan_hiz_l_out (), // Templated
.bscan_mode_ctl_out (), // Templated
.bscan_update_dr_out (), // Templated
.bscan_shift_dr_out (), // Templated
.bscan_clock_dr_out (), // Templated
.bypass_enable_out (), // Templated
.ps_select_out (), // Templated
.pad_jbusl_bso (jbusl_jbusr_bso), // Templated
.pad_jbusl_so (pjbusl_rptrs_so), // Templated
// Inouts
.j_ad (J_AD[127:57]), // Templated
.dtl_l_vref (DTL_L_VREF), // Templated
// Inputs
.jbi_io_config_dtl_chunk0 (jbi_io_config_dtl[0]), // Templated
.jbi_io_config_dtl (jbi_io_config_dtl[1:0]),
.jbi_io_j_ad (jbi_io_j_ad[127:57]),
.jbusr_jbusl_cbd (jbusr_jbusl_cbd[8:1]),
.jbi_io_j_ad_en (jbi_io_j_ad_en[3:2]),
.jbusr_jbusl_cbu (jbusr_jbusl_cbu[8:1]),
.jbi_io_j_ad_en_chunk56 (jbi_io_j_ad_en[3]), // Templated
.bscan_hiz_l_in (ctu_jbusl_hiz_l), // Templated
.pad_jbusl_se (global_shift_enable), // Templated
.jbus_arst_l (jbus_arst_l),
.jbus_adbginit_l (jbus_adbginit_l),
.jbus_gclk (jbus_gclk_c0_r[7]), // Templated
.jbus_grst_l (1'b1), // Templated
.clk_jbusl_cken (ctu_jbusl_jbus_cken), // Templated
.jbus_gdbginit_l (jbus_gdbginit_l),
.bscan_update_dr_in (ctu_jbusl_update_dr), // Templated
.pad_jbusl_si (pddr1_pjbusl_so), // Templated
.bscan_mode_ctl_in (ctu_jbusl_mode_ctl), // Templated
.bscan_clock_dr_in (ctu_jbusl_clock_dr), // Templated
.bypass_enable (global_scan_bypass_en), // Templated
.ps_select (pscan_select), // Templated
.bscan_shift_dr_in (ctu_jbusl_shift_dr), // Templated
.pad_jbusl_bsi (ddr1_jbusl_bso), // Templated
.por_l (jbus_arst_l), // Templated
.rst_io_l (1'b1), // Templated
.rst_val_up (1'b1), // Templated
.rst_val_dn (1'b1), // Templated
.vddo (VDDBO), // Templated
.sel_bypass (1'b0)); // Templated
`endif
//
/* pad_jbusl AUTO_TEMPLATE (
.dtl_l_vref (DBG_VREF),
.jbus_gclk (jbus_gclk_c0_r[0]),
.clk_jbusl_cken (ctu_dbg_jbus_cken),
.bscan_\(.*\)_out (),
.pad_jbusl_bsi (misc_dbg_bso),
.pad_jbusl_si (rptrs_pdbg_so),
.bscan_\(.*\)_in (ctu_debug_\1),
.pad_jbusl_bso (dbg_ddr0_bso),
.pad_jbusl_so (pdbg_pddr1_so),
.pad_jbusl_se (global_shift_enable),
.bypass_enable (global_scan_bypass_en),
.bypass_enable_out (),
.ps_select (pscan_select),
.ps_select_out (),
.por_l (jbus_arst_l),
.rst_io_l (1'b1),
.rst_val_dn (1'b1),
.rst_val_up (1'b1),
.scan_mode (1'b0),
.up_open (1'b0),
.down_25 (1'b0),
.sel_bypass (1'b0),
.jbi_io_dsbl_sampling (1'b0),
.jbi_io_config_dtl (2'b00), // 50 ohm pullup (DTL-END).
.jbi_io_j_ad_en ({iob_io_dbg_en,iob_io_dbg_en}), // Output enable control.
.jbi_io_config_dtl_chunk0 (1'b1), // No termination.
.jbi_io_j_ad_en_chunk56 (1'b0), // Input only.
.jbus_grst_l (1'b1), // Disabled for DO_BIST to propagate sooner. (Bug 4614)
.vddo (VDDTO),
); */
//
`ifdef RTL_PAD_DBG
pad_jbusl pad_dbg
(
.serial_out ({dbg_sot[127:59],
/*dbg_sot[ 58]=DBG_DQ[1]*/ par_scan_head[0],
/*dbg_sot[ 57]=DBG_DQ[0]*/ ser_scan_out[0]}),
.serial_in ({dbg_sin[127:59],
/*dbg_sot[ 58]=DBG_DQ[1]*/ io_tdi,
/*dbg_sot[ 57]=DBG_DQ[0]*/ par_scan_tail[0]}),
.j_ad ({/*[127:105]*/ SPARE_DBG_PAD[23:1],
/*[ 104]*/ DO_BIST,
/*[ 103]*/ SPARE_DBG_PAD[0],
/*[102:100]*/ DBG_CK_P[2:0],
/*[ 99: 97]*/ DBG_CK_N[2:0],
/*[ 96: 57]*/ DBG_DQ[39:0]}),
// Inputs
.jbi_io_j_ad ({/*[127:103]*/ dbg_from_core_unused[127:103],
/*[102:100]*/ iob_io_dbg_ck_p[2:0],
/*[ 99: 97]*/ iob_io_dbg_ck_n[2:0],
/*[ 96: 57]*/ iob_io_dbg_data[39:0]}),
// Outputs
.io_jbi_j_ad ({/*[127:105]*/ dbg_to_core_unused[127:105],
/*[ 104]*/ io_do_bist,
/*[103: 57]*/ dbg_to_core_unused[103:57]}),
/*AUTOINST*/
// Outputs
.bscan_hiz_l_out (), // Templated
.bscan_mode_ctl_out (), // Templated
.bscan_update_dr_out (), // Templated
.bscan_shift_dr_out (), // Templated
.bscan_clock_dr_out (), // Templated
.bypass_enable_out (), // Templated
.ps_select_out (), // Templated
.pad_jbusl_bso (dbg_ddr0_bso), // Templated
.pad_jbusl_so (pdbg_pddr1_so), // Templated
// Inouts
.dtl_l_vref (DBG_VREF), // Templated
// Inputs
.jbi_io_config_dtl_chunk0 (1'b1), // Templated
.jbi_io_config_dtl (2'b00), // Templated
.jbusr_jbusl_cbd (jbusr_jbusl_cbd[8:1]),
.jbi_io_j_ad_en ({iob_io_dbg_en,iob_io_dbg_en}), // Templated
.jbusr_jbusl_cbu (jbusr_jbusl_cbu[8:1]),
.jbi_io_j_ad_en_chunk56 (1'b0), // Templated
.bscan_hiz_l_in (ctu_debug_hiz_l), // Templated
.pad_jbusl_se (global_shift_enable), // Templated
.jbus_arst_l (jbus_arst_l),
.jbus_adbginit_l (jbus_adbginit_l),
.jbus_gclk (jbus_gclk_c0_r[0]), // Templated
.jbus_grst_l (1'b1), // Templated
.clk_jbusl_cken (ctu_dbg_jbus_cken), // Templated
.jbus_gdbginit_l (jbus_gdbginit_l),
.bscan_update_dr_in (ctu_debug_update_dr), // Templated
.pad_jbusl_si (rptrs_pdbg_so), // Templated
.bscan_mode_ctl_in (ctu_debug_mode_ctl), // Templated
.bscan_clock_dr_in (ctu_debug_clock_dr), // Templated
.bypass_enable (global_scan_bypass_en), // Templated
.ps_select (pscan_select), // Templated
.bscan_shift_dr_in (ctu_debug_shift_dr), // Templated
.pad_jbusl_bsi (misc_dbg_bso), // Templated
.por_l (jbus_arst_l), // Templated
.rst_io_l (1'b1), // Templated
.rst_val_up (1'b1), // Templated
.rst_val_dn (1'b1), // Templated
.vddo (VDDTO), // Templated
.sel_bypass (1'b0)); // Templated
`endif
/* pad_misc AUTO_TEMPLATE (
.tck (TCK),
.trst_l (TRST_L),
.tdi (TDI),
.tdo (TDO),
.tms (TMS),
.test_mode (TEST_MODE),
.pwron_rst_l (PWRON_RST_L),
.ssi_miso (SSI_MISO),
.ssi_mosi (SSI_MOSI),
.ssi_sck (SSI_SCK),
.clk_stretch (CLK_STRETCH),
.do_bist (DO_BIST),
.ext_int_l (EXT_INT_L),
.pll_char_in (PLL_CHAR_IN),
.burnin (BURNIN),
.pmi (PMI),
.pmo (PMO),
.pgrm_en (PGRM_EN),
.vreg_selbg_l (VREG_SELBG_L),
.temp_trig (TEMP_TRIG),
.trigin (TRIGIN),
.vdd_sense (VDD_SENSE),
.vss_sense (VSS_SENSE),
.hstl_vref (HSTL_VREF),
.tck2 (TCK2),
.spare_misc_pin (SPARE_MISC_PIN),
.spare_misc_pin_to_core (),
.spare_misc_pindata (1'b0),
.spare_misc_pinoe (1'b1),
.spare_misc_pad (SPARE_MISC_PAD[]),
.spare_misc_pad_to_core (),
.spare_misc_paddata (3'b0),
.spare_misc_padoe (3'b0),
.bscan_\(.*\)_out (),
.pad_misc_bsi (ddr2_misc_sscan_out),
.pad_misc_si (rptrs_pmisc_so),
.bscan_\(.*\)_in (ctu_misc_\1),
.pad_misc_bso (misc_dbg_bso),
.pad_misc_so (pmisc_pddr2_so),
.pad_misc_se (global_shift_enable),
.io_burnin (pcm_io_burnin),
.io_pmi (io_pcm_pmi),
.io_pmo (pcm_io_pmo),
.io_tdo (ctu_io_tdo),
.io_tdo_en (ctu_io_tdo_en),
.jbus_grst_l (1'b1),
.jbus_gclk (jbus_gclk_c3_r[0]),
.clk_misc_cken (ctu_misc_jbus_cken),
.io_pll_char_in (io_pll_char_in),
.vddo (VDDTO),
); */
//
`ifdef RTL_PAD_MISC
pad_misc pad_misc
(/*AUTOINST*/
// Outputs
.spare_misc_pad_to_core (), // Templated
.io_burnin (pcm_io_burnin), // Templated
.io_pmi (io_pcm_pmi), // Templated
.pad_misc_so (pmisc_pddr2_so), // Templated
.bscan_shift_dr_out (), // Templated
.bscan_update_dr_out (), // Templated
.bscan_clock_dr_out (), // Templated
.bscan_mode_ctl_out (), // Templated
.io_ext_int_l (io_ext_int_l),
.io_trigin (io_trigin),
.io_test_mode (io_test_mode),
.io_pwron_rst_l (io_pwron_rst_l),
.io_tms (io_tms),
.io_pgrm_en (io_pgrm_en),
.io_pll_char_in (io_pll_char_in), // Templated
.io_trst_l (io_trst_l),
.io_tck (io_tck),
.io_tdi (io_tdi),
.io_temp_trig (io_temp_trig),
.spare_misc_pin_to_core (), // Templated
.io_jbi_ssi_miso (io_jbi_ssi_miso),
.bscan_hiz_l_out (), // Templated
.pad_misc_bso (misc_dbg_bso), // Templated
.io_tck2 (io_tck2),
.io_vreg_selbg_l (io_vreg_selbg_l),
.io_clk_stretch (io_clk_stretch),
// Inouts
.spare_misc_pad (SPARE_MISC_PAD[2:0]), // Templated
.tdi (TDI), // Templated
.spare_misc_pin (SPARE_MISC_PIN), // Templated
.burnin (BURNIN), // Templated
.vreg_selbg_l (VREG_SELBG_L), // Templated
.tck2 (TCK2), // Templated
.ssi_miso (SSI_MISO), // Templated
.ssi_mosi (SSI_MOSI), // Templated
.temp_trig (TEMP_TRIG), // Templated
.ext_int_l (EXT_INT_L), // Templated
.vdd_sense (VDD_SENSE), // Templated
.pmi (PMI), // Templated
.pll_char_in (PLL_CHAR_IN), // Templated
.vss_sense (VSS_SENSE), // Templated
.clk_stretch (CLK_STRETCH), // Templated
.pwron_rst_l (PWRON_RST_L), // Templated
.test_mode (TEST_MODE), // Templated
.pmo (PMO), // Templated
.pgrm_en (PGRM_EN), // Templated
.hstl_vref (HSTL_VREF), // Templated
.tms (TMS), // Templated
.tck (TCK), // Templated
.tdo (TDO), // Templated
.trst_l (TRST_L), // Templated
.ssi_sck (SSI_SCK), // Templated
.trigin (TRIGIN), // Templated
// Inputs
.spare_misc_paddata (3'b0), // Templated
.spare_misc_padoe (3'b0), // Templated
.io_tdo_en (ctu_io_tdo_en), // Templated
.bscan_hiz_l_in (ctu_misc_hiz_l), // Templated
.bscan_update_dr_in (ctu_misc_update_dr), // Templated
.spare_misc_pindata (1'b0), // Templated
.pad_misc_bsi (ddr2_misc_sscan_out), // Templated
.pad_misc_se (global_shift_enable), // Templated
.pad_misc_si (rptrs_pmisc_so), // Templated
.bscan_clock_dr_in (ctu_misc_clock_dr), // Templated
.jbus_arst_l (jbus_arst_l),
.jbus_adbginit_l (jbus_adbginit_l),
.jbus_gdbginit_l (jbus_gdbginit_l),
.jbus_grst_l (1'b1), // Templated
.jbus_gclk (jbus_gclk_c3_r[0]), // Templated
.vddo (VDDTO), // Templated
.clk_misc_cken (ctu_misc_jbus_cken), // Templated
.pcm_misc_oe (pcm_misc_oe),
.io_pmo (pcm_io_pmo), // Templated
.io_tdo (ctu_io_tdo), // Templated
.jbi_io_ssi_sck (jbi_io_ssi_sck),
.jbi_io_ssi_mosi (jbi_io_ssi_mosi),
.bscan_mode_ctl_in (ctu_misc_mode_ctl), // Templated
.bscan_shift_dr_in (ctu_misc_shift_dr), // Templated
.spare_misc_pinoe (1'b1)); // Templated
`endif
//
/* sctag_scbuf_rptr0 AUTO_TEMPLATE (
.sctag_scbuf\(.*\) (sctag0_scbuf0\1[]),
.scbuf_sctag\(.*\) (scbuf0_sctag0\1[]),
); */
//
sctag_scbuf_rptr0 sctag_scbuf_rptr0
(/*AUTOINST*/
// Outputs
.sctag_scbuf_fbrd_en_c3_buf (sctag0_scbuf0_fbrd_en_c3_buf), // Templated
.sctag_scbuf_fbrd_wl_c3_buf (sctag0_scbuf0_fbrd_wl_c3_buf[2:0]), // Templated
.sctag_scbuf_fbwr_wen_r2_buf (sctag0_scbuf0_fbwr_wen_r2_buf[15:0]), // Templated
.sctag_scbuf_fbwr_wl_r2_buf (sctag0_scbuf0_fbwr_wl_r2_buf[2:0]), // Templated
.sctag_scbuf_fbd_stdatasel_c3_buf (sctag0_scbuf0_fbd_stdatasel_c3_buf), // Templated
.sctag_scbuf_stdecc_c3_buf (sctag0_scbuf0_stdecc_c3_buf[77:0]), // Templated
.sctag_scbuf_ev_dword_r0_buf (sctag0_scbuf0_ev_dword_r0_buf[2:0]), // Templated
.sctag_scbuf_evict_en_r0_buf (sctag0_scbuf0_evict_en_r0_buf), // Templated
.sctag_scbuf_wbwr_wen_c6_buf (sctag0_scbuf0_wbwr_wen_c6_buf[3:0]), // Templated
.sctag_scbuf_wbwr_wl_c6_buf (sctag0_scbuf0_wbwr_wl_c6_buf[2:0]), // Templated
.sctag_scbuf_wbrd_en_r0_buf (sctag0_scbuf0_wbrd_en_r0_buf), // Templated
.sctag_scbuf_wbrd_wl_r0_buf (sctag0_scbuf0_wbrd_wl_r0_buf[2:0]), // Templated
.sctag_scbuf_rdma_wren_s2_buf (sctag0_scbuf0_rdma_wren_s2_buf[15:0]), // Templated
.sctag_scbuf_rdma_wrwl_s2_buf (sctag0_scbuf0_rdma_wrwl_s2_buf[1:0]), // Templated
.sctag_scbuf_rdma_rden_r0_buf (sctag0_scbuf0_rdma_rden_r0_buf), // Templated
.sctag_scbuf_rdma_rdwl_r0_buf (sctag0_scbuf0_rdma_rdwl_r0_buf[1:0]), // Templated
.sctag_scbuf_ctag_en_c7_buf (sctag0_scbuf0_ctag_en_c7_buf), // Templated
.sctag_scbuf_ctag_c7_buf (sctag0_scbuf0_ctag_c7_buf[14:0]), // Templated
.sctag_scbuf_req_en_c7_buf (sctag0_scbuf0_req_en_c7_buf), // Templated
.sctag_scbuf_word_c7_buf (sctag0_scbuf0_word_c7_buf[3:0]), // Templated
.sctag_scbuf_word_vld_c7_buf (sctag0_scbuf0_word_vld_c7_buf), // Templated
.scbuf_sctag_ev_uerr_r5_buf (scbuf0_sctag0_ev_uerr_r5_buf), // Templated
.scbuf_sctag_ev_cerr_r5_buf (scbuf0_sctag0_ev_cerr_r5_buf), // Templated
.scbuf_sctag_rdma_uerr_c10_buf (scbuf0_sctag0_rdma_uerr_c10_buf), // Templated
.scbuf_sctag_rdma_cerr_c10_buf (scbuf0_sctag0_rdma_cerr_c10_buf), // Templated
// Inputs
.sctag_scbuf_fbrd_en_c3 (sctag0_scbuf0_fbrd_en_c3), // Templated
.sctag_scbuf_fbrd_wl_c3 (sctag0_scbuf0_fbrd_wl_c3[2:0]), // Templated
.sctag_scbuf_fbwr_wen_r2 (sctag0_scbuf0_fbwr_wen_r2[15:0]), // Templated
.sctag_scbuf_fbwr_wl_r2 (sctag0_scbuf0_fbwr_wl_r2[2:0]), // Templated
.sctag_scbuf_fbd_stdatasel_c3 (sctag0_scbuf0_fbd_stdatasel_c3), // Templated
.sctag_scbuf_stdecc_c3 (sctag0_scbuf0_stdecc_c3[77:0]), // Templated
.sctag_scbuf_ev_dword_r0 (sctag0_scbuf0_ev_dword_r0[2:0]), // Templated
.sctag_scbuf_evict_en_r0 (sctag0_scbuf0_evict_en_r0), // Templated
.sctag_scbuf_wbwr_wen_c6 (sctag0_scbuf0_wbwr_wen_c6[3:0]), // Templated
.sctag_scbuf_wbwr_wl_c6 (sctag0_scbuf0_wbwr_wl_c6[2:0]), // Templated
.sctag_scbuf_wbrd_en_r0 (sctag0_scbuf0_wbrd_en_r0), // Templated
.sctag_scbuf_wbrd_wl_r0 (sctag0_scbuf0_wbrd_wl_r0[2:0]), // Templated
.sctag_scbuf_rdma_wren_s2 (sctag0_scbuf0_rdma_wren_s2[15:0]), // Templated
.sctag_scbuf_rdma_wrwl_s2 (sctag0_scbuf0_rdma_wrwl_s2[1:0]), // Templated
.sctag_scbuf_rdma_rden_r0 (sctag0_scbuf0_rdma_rden_r0), // Templated
.sctag_scbuf_rdma_rdwl_r0 (sctag0_scbuf0_rdma_rdwl_r0[1:0]), // Templated
.sctag_scbuf_ctag_en_c7 (sctag0_scbuf0_ctag_en_c7), // Templated
.sctag_scbuf_ctag_c7 (sctag0_scbuf0_ctag_c7[14:0]), // Templated
.sctag_scbuf_req_en_c7 (sctag0_scbuf0_req_en_c7), // Templated
.sctag_scbuf_word_c7 (sctag0_scbuf0_word_c7[3:0]), // Templated
.sctag_scbuf_word_vld_c7 (sctag0_scbuf0_word_vld_c7), // Templated
.scbuf_sctag_ev_uerr_r5 (scbuf0_sctag0_ev_uerr_r5), // Templated
.scbuf_sctag_ev_cerr_r5 (scbuf0_sctag0_ev_cerr_r5), // Templated
.scbuf_sctag_rdma_uerr_c10 (scbuf0_sctag0_rdma_uerr_c10), // Templated
.scbuf_sctag_rdma_cerr_c10 (scbuf0_sctag0_rdma_cerr_c10)); // Templated
//
/* sctag_scbuf_rptr1 AUTO_TEMPLATE (
.sctag_scbuf\(.*\) (sctag1_scbuf1\1[]),
.scbuf_sctag\(.*\) (scbuf1_sctag1\1[]),
); */
//
sctag_scbuf_rptr1 sctag_scbuf_rptr1
(/*AUTOINST*/
// Outputs
.sctag_scbuf_fbrd_en_c3_buf (sctag1_scbuf1_fbrd_en_c3_buf), // Templated
.sctag_scbuf_fbrd_wl_c3_buf (sctag1_scbuf1_fbrd_wl_c3_buf[2:0]), // Templated
.sctag_scbuf_fbwr_wen_r2_buf (sctag1_scbuf1_fbwr_wen_r2_buf[15:0]), // Templated
.sctag_scbuf_fbwr_wl_r2_buf (sctag1_scbuf1_fbwr_wl_r2_buf[2:0]), // Templated
.sctag_scbuf_fbd_stdatasel_c3_buf (sctag1_scbuf1_fbd_stdatasel_c3_buf), // Templated
.sctag_scbuf_stdecc_c3_buf (sctag1_scbuf1_stdecc_c3_buf[77:0]), // Templated
.sctag_scbuf_ev_dword_r0_buf (sctag1_scbuf1_ev_dword_r0_buf[2:0]), // Templated
.sctag_scbuf_evict_en_r0_buf (sctag1_scbuf1_evict_en_r0_buf), // Templated
.sctag_scbuf_wbwr_wen_c6_buf (sctag1_scbuf1_wbwr_wen_c6_buf[3:0]), // Templated
.sctag_scbuf_wbwr_wl_c6_buf (sctag1_scbuf1_wbwr_wl_c6_buf[2:0]), // Templated
.sctag_scbuf_wbrd_en_r0_buf (sctag1_scbuf1_wbrd_en_r0_buf), // Templated
.sctag_scbuf_wbrd_wl_r0_buf (sctag1_scbuf1_wbrd_wl_r0_buf[2:0]), // Templated
.sctag_scbuf_rdma_wren_s2_buf (sctag1_scbuf1_rdma_wren_s2_buf[15:0]), // Templated
.sctag_scbuf_rdma_wrwl_s2_buf (sctag1_scbuf1_rdma_wrwl_s2_buf[1:0]), // Templated
.sctag_scbuf_rdma_rden_r0_buf (sctag1_scbuf1_rdma_rden_r0_buf), // Templated
.sctag_scbuf_rdma_rdwl_r0_buf (sctag1_scbuf1_rdma_rdwl_r0_buf[1:0]), // Templated
.sctag_scbuf_ctag_en_c7_buf (sctag1_scbuf1_ctag_en_c7_buf), // Templated
.sctag_scbuf_ctag_c7_buf (sctag1_scbuf1_ctag_c7_buf[14:0]), // Templated
.sctag_scbuf_req_en_c7_buf (sctag1_scbuf1_req_en_c7_buf), // Templated
.sctag_scbuf_word_c7_buf (sctag1_scbuf1_word_c7_buf[3:0]), // Templated
.sctag_scbuf_word_vld_c7_buf (sctag1_scbuf1_word_vld_c7_buf), // Templated
.scbuf_sctag_ev_uerr_r5_buf (scbuf1_sctag1_ev_uerr_r5_buf), // Templated
.scbuf_sctag_ev_cerr_r5_buf (scbuf1_sctag1_ev_cerr_r5_buf), // Templated
.scbuf_sctag_rdma_uerr_c10_buf (scbuf1_sctag1_rdma_uerr_c10_buf), // Templated
.scbuf_sctag_rdma_cerr_c10_buf (scbuf1_sctag1_rdma_cerr_c10_buf), // Templated
// Inputs
.sctag_scbuf_fbrd_en_c3 (sctag1_scbuf1_fbrd_en_c3), // Templated
.sctag_scbuf_fbrd_wl_c3 (sctag1_scbuf1_fbrd_wl_c3[2:0]), // Templated
.sctag_scbuf_fbwr_wen_r2 (sctag1_scbuf1_fbwr_wen_r2[15:0]), // Templated
.sctag_scbuf_fbwr_wl_r2 (sctag1_scbuf1_fbwr_wl_r2[2:0]), // Templated
.sctag_scbuf_fbd_stdatasel_c3 (sctag1_scbuf1_fbd_stdatasel_c3), // Templated
.sctag_scbuf_stdecc_c3 (sctag1_scbuf1_stdecc_c3[77:0]), // Templated
.sctag_scbuf_ev_dword_r0 (sctag1_scbuf1_ev_dword_r0[2:0]), // Templated
.sctag_scbuf_evict_en_r0 (sctag1_scbuf1_evict_en_r0), // Templated
.sctag_scbuf_wbwr_wen_c6 (sctag1_scbuf1_wbwr_wen_c6[3:0]), // Templated
.sctag_scbuf_wbwr_wl_c6 (sctag1_scbuf1_wbwr_wl_c6[2:0]), // Templated
.sctag_scbuf_wbrd_en_r0 (sctag1_scbuf1_wbrd_en_r0), // Templated
.sctag_scbuf_wbrd_wl_r0 (sctag1_scbuf1_wbrd_wl_r0[2:0]), // Templated
.sctag_scbuf_rdma_wren_s2 (sctag1_scbuf1_rdma_wren_s2[15:0]), // Templated
.sctag_scbuf_rdma_wrwl_s2 (sctag1_scbuf1_rdma_wrwl_s2[1:0]), // Templated
.sctag_scbuf_rdma_rden_r0 (sctag1_scbuf1_rdma_rden_r0), // Templated
.sctag_scbuf_rdma_rdwl_r0 (sctag1_scbuf1_rdma_rdwl_r0[1:0]), // Templated
.sctag_scbuf_ctag_en_c7 (sctag1_scbuf1_ctag_en_c7), // Templated
.sctag_scbuf_ctag_c7 (sctag1_scbuf1_ctag_c7[14:0]), // Templated
.sctag_scbuf_req_en_c7 (sctag1_scbuf1_req_en_c7), // Templated
.sctag_scbuf_word_c7 (sctag1_scbuf1_word_c7[3:0]), // Templated
.sctag_scbuf_word_vld_c7 (sctag1_scbuf1_word_vld_c7), // Templated
.scbuf_sctag_ev_uerr_r5 (scbuf1_sctag1_ev_uerr_r5), // Templated
.scbuf_sctag_ev_cerr_r5 (scbuf1_sctag1_ev_cerr_r5), // Templated
.scbuf_sctag_rdma_uerr_c10 (scbuf1_sctag1_rdma_uerr_c10), // Templated
.scbuf_sctag_rdma_cerr_c10 (scbuf1_sctag1_rdma_cerr_c10)); // Templated
//
/* sctag_scbuf_rptr2 AUTO_TEMPLATE (
.sctag_scbuf\(.*\) (sctag2_scbuf2\1[]),
.scbuf_sctag\(.*\) (scbuf2_sctag2\1[]),
); */
//
sctag_scbuf_rptr2 sctag_scbuf_rptr2
(/*AUTOINST*/
// Outputs
.sctag_scbuf_fbrd_en_c3_buf (sctag2_scbuf2_fbrd_en_c3_buf), // Templated
.sctag_scbuf_fbrd_wl_c3_buf (sctag2_scbuf2_fbrd_wl_c3_buf[2:0]), // Templated
.sctag_scbuf_fbwr_wen_r2_buf (sctag2_scbuf2_fbwr_wen_r2_buf[15:0]), // Templated
.sctag_scbuf_fbwr_wl_r2_buf (sctag2_scbuf2_fbwr_wl_r2_buf[2:0]), // Templated
.sctag_scbuf_fbd_stdatasel_c3_buf (sctag2_scbuf2_fbd_stdatasel_c3_buf), // Templated
.sctag_scbuf_stdecc_c3_buf (sctag2_scbuf2_stdecc_c3_buf[77:0]), // Templated
.sctag_scbuf_ev_dword_r0_buf (sctag2_scbuf2_ev_dword_r0_buf[2:0]), // Templated
.sctag_scbuf_evict_en_r0_buf (sctag2_scbuf2_evict_en_r0_buf), // Templated
.sctag_scbuf_wbwr_wen_c6_buf (sctag2_scbuf2_wbwr_wen_c6_buf[3:0]), // Templated
.sctag_scbuf_wbwr_wl_c6_buf (sctag2_scbuf2_wbwr_wl_c6_buf[2:0]), // Templated
.sctag_scbuf_wbrd_en_r0_buf (sctag2_scbuf2_wbrd_en_r0_buf), // Templated
.sctag_scbuf_wbrd_wl_r0_buf (sctag2_scbuf2_wbrd_wl_r0_buf[2:0]), // Templated
.sctag_scbuf_rdma_wren_s2_buf (sctag2_scbuf2_rdma_wren_s2_buf[15:0]), // Templated
.sctag_scbuf_rdma_wrwl_s2_buf (sctag2_scbuf2_rdma_wrwl_s2_buf[1:0]), // Templated
.sctag_scbuf_rdma_rden_r0_buf (sctag2_scbuf2_rdma_rden_r0_buf), // Templated
.sctag_scbuf_rdma_rdwl_r0_buf (sctag2_scbuf2_rdma_rdwl_r0_buf[1:0]), // Templated
.sctag_scbuf_ctag_en_c7_buf (sctag2_scbuf2_ctag_en_c7_buf), // Templated
.sctag_scbuf_ctag_c7_buf (sctag2_scbuf2_ctag_c7_buf[14:0]), // Templated
.sctag_scbuf_req_en_c7_buf (sctag2_scbuf2_req_en_c7_buf), // Templated
.sctag_scbuf_word_c7_buf (sctag2_scbuf2_word_c7_buf[3:0]), // Templated
.sctag_scbuf_word_vld_c7_buf (sctag2_scbuf2_word_vld_c7_buf), // Templated
.scbuf_sctag_ev_uerr_r5_buf (scbuf2_sctag2_ev_uerr_r5_buf), // Templated
.scbuf_sctag_ev_cerr_r5_buf (scbuf2_sctag2_ev_cerr_r5_buf), // Templated
.scbuf_sctag_rdma_uerr_c10_buf (scbuf2_sctag2_rdma_uerr_c10_buf), // Templated
.scbuf_sctag_rdma_cerr_c10_buf (scbuf2_sctag2_rdma_cerr_c10_buf), // Templated
// Inputs
.sctag_scbuf_fbrd_en_c3 (sctag2_scbuf2_fbrd_en_c3), // Templated
.sctag_scbuf_fbrd_wl_c3 (sctag2_scbuf2_fbrd_wl_c3[2:0]), // Templated
.sctag_scbuf_fbwr_wen_r2 (sctag2_scbuf2_fbwr_wen_r2[15:0]), // Templated
.sctag_scbuf_fbwr_wl_r2 (sctag2_scbuf2_fbwr_wl_r2[2:0]), // Templated
.sctag_scbuf_fbd_stdatasel_c3 (sctag2_scbuf2_fbd_stdatasel_c3), // Templated
.sctag_scbuf_stdecc_c3 (sctag2_scbuf2_stdecc_c3[77:0]), // Templated
.sctag_scbuf_ev_dword_r0 (sctag2_scbuf2_ev_dword_r0[2:0]), // Templated
.sctag_scbuf_evict_en_r0 (sctag2_scbuf2_evict_en_r0), // Templated
.sctag_scbuf_wbwr_wen_c6 (sctag2_scbuf2_wbwr_wen_c6[3:0]), // Templated
.sctag_scbuf_wbwr_wl_c6 (sctag2_scbuf2_wbwr_wl_c6[2:0]), // Templated
.sctag_scbuf_wbrd_en_r0 (sctag2_scbuf2_wbrd_en_r0), // Templated
.sctag_scbuf_wbrd_wl_r0 (sctag2_scbuf2_wbrd_wl_r0[2:0]), // Templated
.sctag_scbuf_rdma_wren_s2 (sctag2_scbuf2_rdma_wren_s2[15:0]), // Templated
.sctag_scbuf_rdma_wrwl_s2 (sctag2_scbuf2_rdma_wrwl_s2[1:0]), // Templated
.sctag_scbuf_rdma_rden_r0 (sctag2_scbuf2_rdma_rden_r0), // Templated
.sctag_scbuf_rdma_rdwl_r0 (sctag2_scbuf2_rdma_rdwl_r0[1:0]), // Templated
.sctag_scbuf_ctag_en_c7 (sctag2_scbuf2_ctag_en_c7), // Templated
.sctag_scbuf_ctag_c7 (sctag2_scbuf2_ctag_c7[14:0]), // Templated
.sctag_scbuf_req_en_c7 (sctag2_scbuf2_req_en_c7), // Templated
.sctag_scbuf_word_c7 (sctag2_scbuf2_word_c7[3:0]), // Templated
.sctag_scbuf_word_vld_c7 (sctag2_scbuf2_word_vld_c7), // Templated
.scbuf_sctag_ev_uerr_r5 (scbuf2_sctag2_ev_uerr_r5), // Templated
.scbuf_sctag_ev_cerr_r5 (scbuf2_sctag2_ev_cerr_r5), // Templated
.scbuf_sctag_rdma_uerr_c10 (scbuf2_sctag2_rdma_uerr_c10), // Templated
.scbuf_sctag_rdma_cerr_c10 (scbuf2_sctag2_rdma_cerr_c10)); // Templated
//
/* sctag_scbuf_rptr3 AUTO_TEMPLATE (
.sctag_scbuf\(.*\) (sctag3_scbuf3\1[]),
.scbuf_sctag\(.*\) (scbuf3_sctag3\1[]),
); */
//
sctag_scbuf_rptr3 sctag_scbuf_rptr3
(/*AUTOINST*/
// Outputs
.sctag_scbuf_fbrd_en_c3_buf (sctag3_scbuf3_fbrd_en_c3_buf), // Templated
.sctag_scbuf_fbrd_wl_c3_buf (sctag3_scbuf3_fbrd_wl_c3_buf[2:0]), // Templated
.sctag_scbuf_fbwr_wen_r2_buf (sctag3_scbuf3_fbwr_wen_r2_buf[15:0]), // Templated
.sctag_scbuf_fbwr_wl_r2_buf (sctag3_scbuf3_fbwr_wl_r2_buf[2:0]), // Templated
.sctag_scbuf_fbd_stdatasel_c3_buf (sctag3_scbuf3_fbd_stdatasel_c3_buf), // Templated
.sctag_scbuf_stdecc_c3_buf (sctag3_scbuf3_stdecc_c3_buf[77:0]), // Templated
.sctag_scbuf_ev_dword_r0_buf (sctag3_scbuf3_ev_dword_r0_buf[2:0]), // Templated
.sctag_scbuf_evict_en_r0_buf (sctag3_scbuf3_evict_en_r0_buf), // Templated
.sctag_scbuf_wbwr_wen_c6_buf (sctag3_scbuf3_wbwr_wen_c6_buf[3:0]), // Templated
.sctag_scbuf_wbwr_wl_c6_buf (sctag3_scbuf3_wbwr_wl_c6_buf[2:0]), // Templated
.sctag_scbuf_wbrd_en_r0_buf (sctag3_scbuf3_wbrd_en_r0_buf), // Templated
.sctag_scbuf_wbrd_wl_r0_buf (sctag3_scbuf3_wbrd_wl_r0_buf[2:0]), // Templated
.sctag_scbuf_rdma_wren_s2_buf (sctag3_scbuf3_rdma_wren_s2_buf[15:0]), // Templated
.sctag_scbuf_rdma_wrwl_s2_buf (sctag3_scbuf3_rdma_wrwl_s2_buf[1:0]), // Templated
.sctag_scbuf_rdma_rden_r0_buf (sctag3_scbuf3_rdma_rden_r0_buf), // Templated
.sctag_scbuf_rdma_rdwl_r0_buf (sctag3_scbuf3_rdma_rdwl_r0_buf[1:0]), // Templated
.sctag_scbuf_ctag_en_c7_buf (sctag3_scbuf3_ctag_en_c7_buf), // Templated
.sctag_scbuf_ctag_c7_buf (sctag3_scbuf3_ctag_c7_buf[14:0]), // Templated
.sctag_scbuf_req_en_c7_buf (sctag3_scbuf3_req_en_c7_buf), // Templated
.sctag_scbuf_word_c7_buf (sctag3_scbuf3_word_c7_buf[3:0]), // Templated
.sctag_scbuf_word_vld_c7_buf (sctag3_scbuf3_word_vld_c7_buf), // Templated
.scbuf_sctag_ev_uerr_r5_buf (scbuf3_sctag3_ev_uerr_r5_buf), // Templated
.scbuf_sctag_ev_cerr_r5_buf (scbuf3_sctag3_ev_cerr_r5_buf), // Templated
.scbuf_sctag_rdma_uerr_c10_buf (scbuf3_sctag3_rdma_uerr_c10_buf), // Templated
.scbuf_sctag_rdma_cerr_c10_buf (scbuf3_sctag3_rdma_cerr_c10_buf), // Templated
// Inputs
.sctag_scbuf_fbrd_en_c3 (sctag3_scbuf3_fbrd_en_c3), // Templated
.sctag_scbuf_fbrd_wl_c3 (sctag3_scbuf3_fbrd_wl_c3[2:0]), // Templated
.sctag_scbuf_fbwr_wen_r2 (sctag3_scbuf3_fbwr_wen_r2[15:0]), // Templated
.sctag_scbuf_fbwr_wl_r2 (sctag3_scbuf3_fbwr_wl_r2[2:0]), // Templated
.sctag_scbuf_fbd_stdatasel_c3 (sctag3_scbuf3_fbd_stdatasel_c3), // Templated
.sctag_scbuf_stdecc_c3 (sctag3_scbuf3_stdecc_c3[77:0]), // Templated
.sctag_scbuf_ev_dword_r0 (sctag3_scbuf3_ev_dword_r0[2:0]), // Templated
.sctag_scbuf_evict_en_r0 (sctag3_scbuf3_evict_en_r0), // Templated
.sctag_scbuf_wbwr_wen_c6 (sctag3_scbuf3_wbwr_wen_c6[3:0]), // Templated
.sctag_scbuf_wbwr_wl_c6 (sctag3_scbuf3_wbwr_wl_c6[2:0]), // Templated
.sctag_scbuf_wbrd_en_r0 (sctag3_scbuf3_wbrd_en_r0), // Templated
.sctag_scbuf_wbrd_wl_r0 (sctag3_scbuf3_wbrd_wl_r0[2:0]), // Templated
.sctag_scbuf_rdma_wren_s2 (sctag3_scbuf3_rdma_wren_s2[15:0]), // Templated
.sctag_scbuf_rdma_wrwl_s2 (sctag3_scbuf3_rdma_wrwl_s2[1:0]), // Templated
.sctag_scbuf_rdma_rden_r0 (sctag3_scbuf3_rdma_rden_r0), // Templated
.sctag_scbuf_rdma_rdwl_r0 (sctag3_scbuf3_rdma_rdwl_r0[1:0]), // Templated
.sctag_scbuf_ctag_en_c7 (sctag3_scbuf3_ctag_en_c7), // Templated
.sctag_scbuf_ctag_c7 (sctag3_scbuf3_ctag_c7[14:0]), // Templated
.sctag_scbuf_req_en_c7 (sctag3_scbuf3_req_en_c7), // Templated
.sctag_scbuf_word_c7 (sctag3_scbuf3_word_c7[3:0]), // Templated
.sctag_scbuf_word_vld_c7 (sctag3_scbuf3_word_vld_c7), // Templated
.scbuf_sctag_ev_uerr_r5 (scbuf3_sctag3_ev_uerr_r5), // Templated
.scbuf_sctag_ev_cerr_r5 (scbuf3_sctag3_ev_cerr_r5), // Templated
.scbuf_sctag_rdma_uerr_c10 (scbuf3_sctag3_rdma_uerr_c10), // Templated
.scbuf_sctag_rdma_cerr_c10 (scbuf3_sctag3_rdma_cerr_c10)); // Templated
//
/* ff_dram_sc_bank0 AUTO_TEMPLATE (
.rclk (ccx_rclk),
.se (global_shift_enable),
.si (rtop2_rdram0_so),
.so (rdram0_rtop_so),
.dram_scbuf\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_scbuf@\1[]),
.scbuf_dram\(.*\)_d1 (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_d1[]),
.scbuf_dram\(.*\) (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf3[]),
.dram_sctag\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_sctag@\1[]),
.sctag_dram\(.*\)_d1 (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_d1[]),
.sctag_dram\(.*\) (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf3[]),
); */
//
ff_dram_sc_bank0 ff_dram_sc_bank0
(/*AUTOINST*/
// Outputs
.dram_scbuf_data_r2_d1 (dram02_scbuf0_data_r2_d1[127:0]), // Templated
.dram_scbuf_ecc_r2_d1 (dram02_scbuf0_ecc_r2_d1[27:0]), // Templated
.scbuf_dram_wr_data_r5_d1 (scbuf0_dram02_wr_data_r5_d1[63:0]), // Templated
.scbuf_dram_data_vld_r5_d1 (scbuf0_dram02_data_vld_r5_d1), // Templated
.scbuf_dram_data_mecc_r5_d1 (scbuf0_dram02_data_mecc_r5_d1), // Templated
.sctag_dram_rd_req_d1 (sctag0_dram02_rd_req_d1), // Templated
.sctag_dram_rd_dummy_req_d1 (sctag0_dram02_rd_dummy_req_d1), // Templated
.sctag_dram_rd_req_id_d1 (sctag0_dram02_rd_req_id_d1[2:0]), // Templated
.sctag_dram_addr_d1 (sctag0_dram02_addr_d1[39:5]), // Templated
.sctag_dram_wr_req_d1 (sctag0_dram02_wr_req_d1), // Templated
.dram_sctag_rd_ack_d1 (dram02_sctag0_rd_ack_d1), // Templated
.dram_sctag_wr_ack_d1 (dram02_sctag0_wr_ack_d1), // Templated
.dram_sctag_chunk_id_r0_d1 (dram02_sctag0_chunk_id_r0_d1[1:0]), // Templated
.dram_sctag_data_vld_r0_d1 (dram02_sctag0_data_vld_r0_d1), // Templated
.dram_sctag_rd_req_id_r0_d1 (dram02_sctag0_rd_req_id_r0_d1[2:0]), // Templated
.dram_sctag_secc_err_r2_d1 (dram02_sctag0_secc_err_r2_d1), // Templated
.dram_sctag_mecc_err_r2_d1 (dram02_sctag0_mecc_err_r2_d1), // Templated
.dram_sctag_scb_mecc_err_d1 (dram02_sctag0_scb_mecc_err_d1), // Templated
.dram_sctag_scb_secc_err_d1 (dram02_sctag0_scb_secc_err_d1), // Templated
.so (rdram0_rtop_so), // Templated
// Inputs
.dram_scbuf_data_r2 (dram02_scbuf0_data_r2[127:0]), // Templated
.dram_scbuf_ecc_r2 (dram02_scbuf0_ecc_r2[27:0]), // Templated
.scbuf_dram_wr_data_r5 (scbuf0_dram02_wr_data_r5_buf3[63:0]), // Templated
.scbuf_dram_data_vld_r5 (scbuf0_dram02_data_vld_r5_buf3), // Templated
.scbuf_dram_data_mecc_r5 (scbuf0_dram02_data_mecc_r5_buf3), // Templated
.sctag_dram_rd_req (sctag0_dram02_rd_req_buf3), // Templated
.sctag_dram_rd_dummy_req (sctag0_dram02_rd_dummy_req_buf3), // Templated
.sctag_dram_rd_req_id (sctag0_dram02_rd_req_id_buf3[2:0]), // Templated
.sctag_dram_addr (sctag0_dram02_addr_buf3[39:5]), // Templated
.sctag_dram_wr_req (sctag0_dram02_wr_req_buf3), // Templated
.dram_sctag_rd_ack (dram02_sctag0_rd_ack), // Templated
.dram_sctag_wr_ack (dram02_sctag0_wr_ack), // Templated
.dram_sctag_chunk_id_r0 (dram02_sctag0_chunk_id_r0[1:0]), // Templated
.dram_sctag_data_vld_r0 (dram02_sctag0_data_vld_r0), // Templated
.dram_sctag_rd_req_id_r0 (dram02_sctag0_rd_req_id_r0[2:0]), // Templated
.dram_sctag_secc_err_r2 (dram02_sctag0_secc_err_r2), // Templated
.dram_sctag_mecc_err_r2 (dram02_sctag0_mecc_err_r2), // Templated
.dram_sctag_scb_mecc_err (dram02_sctag0_scb_mecc_err), // Templated
.dram_sctag_scb_secc_err (dram02_sctag0_scb_secc_err), // Templated
.rclk (ccx_rclk), // Templated
.si (rtop2_rdram0_so), // Templated
.se (global_shift_enable)); // Templated
//
/* ff_dram_sc_bank2 AUTO_TEMPLATE (
.rclk (ccx_rclk),
.se (global_shift_enable),
.si (rtop_rdram2_so),
.so (rdram2_fpu_so),
.dram_scbuf\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_scbuf@\1[]),
.scbuf_dram\(.*\)_d1 (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_d1[]),
.scbuf_dram\(.*\) (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf3[]),
.dram_sctag\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_sctag@\1[]),
.sctag_dram\(.*\)_d1 (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_d1[]),
.sctag_dram\(.*\) (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf3[]),
); */
//
ff_dram_sc_bank2 ff_dram_sc_bank2
(/*AUTOINST*/
// Outputs
.dram_scbuf_data_r2_d1 (dram02_scbuf2_data_r2_d1[127:0]), // Templated
.dram_scbuf_ecc_r2_d1 (dram02_scbuf2_ecc_r2_d1[27:0]), // Templated
.scbuf_dram_wr_data_r5_d1 (scbuf2_dram02_wr_data_r5_d1[63:0]), // Templated
.scbuf_dram_data_vld_r5_d1 (scbuf2_dram02_data_vld_r5_d1), // Templated
.scbuf_dram_data_mecc_r5_d1 (scbuf2_dram02_data_mecc_r5_d1), // Templated
.sctag_dram_rd_req_d1 (sctag2_dram02_rd_req_d1), // Templated
.sctag_dram_rd_dummy_req_d1 (sctag2_dram02_rd_dummy_req_d1), // Templated
.sctag_dram_rd_req_id_d1 (sctag2_dram02_rd_req_id_d1[2:0]), // Templated
.sctag_dram_addr_d1 (sctag2_dram02_addr_d1[39:5]), // Templated
.sctag_dram_wr_req_d1 (sctag2_dram02_wr_req_d1), // Templated
.dram_sctag_rd_ack_d1 (dram02_sctag2_rd_ack_d1), // Templated
.dram_sctag_wr_ack_d1 (dram02_sctag2_wr_ack_d1), // Templated
.dram_sctag_chunk_id_r0_d1 (dram02_sctag2_chunk_id_r0_d1[1:0]), // Templated
.dram_sctag_data_vld_r0_d1 (dram02_sctag2_data_vld_r0_d1), // Templated
.dram_sctag_rd_req_id_r0_d1 (dram02_sctag2_rd_req_id_r0_d1[2:0]), // Templated
.dram_sctag_secc_err_r2_d1 (dram02_sctag2_secc_err_r2_d1), // Templated
.dram_sctag_mecc_err_r2_d1 (dram02_sctag2_mecc_err_r2_d1), // Templated
.dram_sctag_scb_mecc_err_d1 (dram02_sctag2_scb_mecc_err_d1), // Templated
.dram_sctag_scb_secc_err_d1 (dram02_sctag2_scb_secc_err_d1), // Templated
.so (rdram2_fpu_so), // Templated
// Inputs
.dram_scbuf_data_r2 (dram02_scbuf2_data_r2[127:0]), // Templated
.dram_scbuf_ecc_r2 (dram02_scbuf2_ecc_r2[27:0]), // Templated
.scbuf_dram_wr_data_r5 (scbuf2_dram02_wr_data_r5_buf3[63:0]), // Templated
.scbuf_dram_data_vld_r5 (scbuf2_dram02_data_vld_r5_buf3), // Templated
.scbuf_dram_data_mecc_r5 (scbuf2_dram02_data_mecc_r5_buf3), // Templated
.sctag_dram_rd_req (sctag2_dram02_rd_req_buf3), // Templated
.sctag_dram_rd_dummy_req (sctag2_dram02_rd_dummy_req_buf3), // Templated
.sctag_dram_rd_req_id (sctag2_dram02_rd_req_id_buf3[2:0]), // Templated
.sctag_dram_addr (sctag2_dram02_addr_buf3[39:5]), // Templated
.sctag_dram_wr_req (sctag2_dram02_wr_req_buf3), // Templated
.dram_sctag_rd_ack (dram02_sctag2_rd_ack), // Templated
.dram_sctag_wr_ack (dram02_sctag2_wr_ack), // Templated
.dram_sctag_chunk_id_r0 (dram02_sctag2_chunk_id_r0[1:0]), // Templated
.dram_sctag_data_vld_r0 (dram02_sctag2_data_vld_r0), // Templated
.dram_sctag_rd_req_id_r0 (dram02_sctag2_rd_req_id_r0[2:0]), // Templated
.dram_sctag_secc_err_r2 (dram02_sctag2_secc_err_r2), // Templated
.dram_sctag_mecc_err_r2 (dram02_sctag2_mecc_err_r2), // Templated
.dram_sctag_scb_mecc_err (dram02_sctag2_scb_mecc_err), // Templated
.dram_sctag_scb_secc_err (dram02_sctag2_scb_secc_err), // Templated
.rclk (ccx_rclk), // Templated
.si (rtop_rdram2_so), // Templated
.se (global_shift_enable)); // Templated
//
/* ff_dram_sc_bank1 AUTO_TEMPLATE (
.rclk (ccx_rclk),
.se (global_shift_enable),
.si (rbot_rdram1_so),
.so (rdram1_rbot2_so),
.dram_scbuf\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_scbuf@\1[]),
.scbuf_dram\(.*\)_d1 (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_d1[]),
.scbuf_dram\(.*\) (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf3[]),
.dram_sctag\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_sctag@\1[]),
.sctag_dram\(.*\)_d1 (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_d1[]),
.sctag_dram\(.*\) (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf3[]),
); */
//
ff_dram_sc_bank1 ff_dram_sc_bank1
(/*AUTOINST*/
// Outputs
.dram_scbuf_data_r2_d1 (dram13_scbuf1_data_r2_d1[127:0]), // Templated
.dram_scbuf_ecc_r2_d1 (dram13_scbuf1_ecc_r2_d1[27:0]), // Templated
.scbuf_dram_wr_data_r5_d1 (scbuf1_dram13_wr_data_r5_d1[63:0]), // Templated
.scbuf_dram_data_vld_r5_d1 (scbuf1_dram13_data_vld_r5_d1), // Templated
.scbuf_dram_data_mecc_r5_d1 (scbuf1_dram13_data_mecc_r5_d1), // Templated
.sctag_dram_rd_req_d1 (sctag1_dram13_rd_req_d1), // Templated
.sctag_dram_rd_dummy_req_d1 (sctag1_dram13_rd_dummy_req_d1), // Templated
.sctag_dram_rd_req_id_d1 (sctag1_dram13_rd_req_id_d1[2:0]), // Templated
.sctag_dram_addr_d1 (sctag1_dram13_addr_d1[39:5]), // Templated
.sctag_dram_wr_req_d1 (sctag1_dram13_wr_req_d1), // Templated
.dram_sctag_rd_ack_d1 (dram13_sctag1_rd_ack_d1), // Templated
.dram_sctag_wr_ack_d1 (dram13_sctag1_wr_ack_d1), // Templated
.dram_sctag_chunk_id_r0_d1 (dram13_sctag1_chunk_id_r0_d1[1:0]), // Templated
.dram_sctag_data_vld_r0_d1 (dram13_sctag1_data_vld_r0_d1), // Templated
.dram_sctag_rd_req_id_r0_d1 (dram13_sctag1_rd_req_id_r0_d1[2:0]), // Templated
.dram_sctag_secc_err_r2_d1 (dram13_sctag1_secc_err_r2_d1), // Templated
.dram_sctag_mecc_err_r2_d1 (dram13_sctag1_mecc_err_r2_d1), // Templated
.dram_sctag_scb_mecc_err_d1 (dram13_sctag1_scb_mecc_err_d1), // Templated
.dram_sctag_scb_secc_err_d1 (dram13_sctag1_scb_secc_err_d1), // Templated
.so (rdram1_rbot2_so), // Templated
// Inputs
.dram_scbuf_data_r2 (dram13_scbuf1_data_r2[127:0]), // Templated
.dram_scbuf_ecc_r2 (dram13_scbuf1_ecc_r2[27:0]), // Templated
.scbuf_dram_wr_data_r5 (scbuf1_dram13_wr_data_r5_buf3[63:0]), // Templated
.scbuf_dram_data_vld_r5 (scbuf1_dram13_data_vld_r5_buf3), // Templated
.scbuf_dram_data_mecc_r5 (scbuf1_dram13_data_mecc_r5_buf3), // Templated
.sctag_dram_rd_req (sctag1_dram13_rd_req_buf3), // Templated
.sctag_dram_rd_dummy_req (sctag1_dram13_rd_dummy_req_buf3), // Templated
.sctag_dram_rd_req_id (sctag1_dram13_rd_req_id_buf3[2:0]), // Templated
.sctag_dram_addr (sctag1_dram13_addr_buf3[39:5]), // Templated
.sctag_dram_wr_req (sctag1_dram13_wr_req_buf3), // Templated
.dram_sctag_rd_ack (dram13_sctag1_rd_ack), // Templated
.dram_sctag_wr_ack (dram13_sctag1_wr_ack), // Templated
.dram_sctag_chunk_id_r0 (dram13_sctag1_chunk_id_r0[1:0]), // Templated
.dram_sctag_data_vld_r0 (dram13_sctag1_data_vld_r0), // Templated
.dram_sctag_rd_req_id_r0 (dram13_sctag1_rd_req_id_r0[2:0]), // Templated
.dram_sctag_secc_err_r2 (dram13_sctag1_secc_err_r2), // Templated
.dram_sctag_mecc_err_r2 (dram13_sctag1_mecc_err_r2), // Templated
.dram_sctag_scb_mecc_err (dram13_sctag1_scb_mecc_err), // Templated
.dram_sctag_scb_secc_err (dram13_sctag1_scb_secc_err), // Templated
.rclk (ccx_rclk), // Templated
.si (rbot_rdram1_so), // Templated
.se (global_shift_enable)); // Templated
//
/* ff_dram_sc_bank3 AUTO_TEMPLATE (
.rclk (ccx_rclk),
.se (global_shift_enable),
.si (fpu_rdram3_so),
.so (rdram3_rbot_so),
.dram_scbuf\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_scbuf@\1[]),
.scbuf_dram\(.*\)_d1 (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_d1[]),
.scbuf_dram\(.*\) (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf3[]),
.dram_sctag\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_sctag@\1[]),
.sctag_dram\(.*\)_d1 (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_d1[]),
.sctag_dram\(.*\) (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf3[]),
); */
//
ff_dram_sc_bank3 ff_dram_sc_bank3
(/*AUTOINST*/
// Outputs
.dram_scbuf_data_r2_d1 (dram13_scbuf3_data_r2_d1[127:0]), // Templated
.dram_scbuf_ecc_r2_d1 (dram13_scbuf3_ecc_r2_d1[27:0]), // Templated
.scbuf_dram_wr_data_r5_d1 (scbuf3_dram13_wr_data_r5_d1[63:0]), // Templated
.scbuf_dram_data_vld_r5_d1 (scbuf3_dram13_data_vld_r5_d1), // Templated
.scbuf_dram_data_mecc_r5_d1 (scbuf3_dram13_data_mecc_r5_d1), // Templated
.sctag_dram_rd_req_d1 (sctag3_dram13_rd_req_d1), // Templated
.sctag_dram_rd_dummy_req_d1 (sctag3_dram13_rd_dummy_req_d1), // Templated
.sctag_dram_rd_req_id_d1 (sctag3_dram13_rd_req_id_d1[2:0]), // Templated
.sctag_dram_addr_d1 (sctag3_dram13_addr_d1[39:5]), // Templated
.sctag_dram_wr_req_d1 (sctag3_dram13_wr_req_d1), // Templated
.dram_sctag_rd_ack_d1 (dram13_sctag3_rd_ack_d1), // Templated
.dram_sctag_wr_ack_d1 (dram13_sctag3_wr_ack_d1), // Templated
.dram_sctag_chunk_id_r0_d1 (dram13_sctag3_chunk_id_r0_d1[1:0]), // Templated
.dram_sctag_data_vld_r0_d1 (dram13_sctag3_data_vld_r0_d1), // Templated
.dram_sctag_rd_req_id_r0_d1 (dram13_sctag3_rd_req_id_r0_d1[2:0]), // Templated
.dram_sctag_secc_err_r2_d1 (dram13_sctag3_secc_err_r2_d1), // Templated
.dram_sctag_mecc_err_r2_d1 (dram13_sctag3_mecc_err_r2_d1), // Templated
.dram_sctag_scb_mecc_err_d1 (dram13_sctag3_scb_mecc_err_d1), // Templated
.dram_sctag_scb_secc_err_d1 (dram13_sctag3_scb_secc_err_d1), // Templated
.so (rdram3_rbot_so), // Templated
// Inputs
.dram_scbuf_data_r2 (dram13_scbuf3_data_r2[127:0]), // Templated
.dram_scbuf_ecc_r2 (dram13_scbuf3_ecc_r2[27:0]), // Templated
.scbuf_dram_wr_data_r5 (scbuf3_dram13_wr_data_r5_buf3[63:0]), // Templated
.scbuf_dram_data_vld_r5 (scbuf3_dram13_data_vld_r5_buf3), // Templated
.scbuf_dram_data_mecc_r5 (scbuf3_dram13_data_mecc_r5_buf3), // Templated
.sctag_dram_rd_req (sctag3_dram13_rd_req_buf3), // Templated
.sctag_dram_rd_dummy_req (sctag3_dram13_rd_dummy_req_buf3), // Templated
.sctag_dram_rd_req_id (sctag3_dram13_rd_req_id_buf3[2:0]), // Templated
.sctag_dram_addr (sctag3_dram13_addr_buf3[39:5]), // Templated
.sctag_dram_wr_req (sctag3_dram13_wr_req_buf3), // Templated
.dram_sctag_rd_ack (dram13_sctag3_rd_ack), // Templated
.dram_sctag_wr_ack (dram13_sctag3_wr_ack), // Templated
.dram_sctag_chunk_id_r0 (dram13_sctag3_chunk_id_r0[1:0]), // Templated
.dram_sctag_data_vld_r0 (dram13_sctag3_data_vld_r0), // Templated
.dram_sctag_rd_req_id_r0 (dram13_sctag3_rd_req_id_r0[2:0]), // Templated
.dram_sctag_secc_err_r2 (dram13_sctag3_secc_err_r2), // Templated
.dram_sctag_mecc_err_r2 (dram13_sctag3_mecc_err_r2), // Templated
.dram_sctag_scb_mecc_err (dram13_sctag3_scb_mecc_err), // Templated
.dram_sctag_scb_secc_err (dram13_sctag3_scb_secc_err), // Templated
.rclk (ccx_rclk), // Templated
.si (fpu_rdram3_so), // Templated
.se (global_shift_enable)); // Templated
//
/* dram_l2_buf2 AUTO_TEMPLATE (
.dram_scbuf\(.*\)_buf (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_scbuf@\1_buf1[]),
.dram_scbuf\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_scbuf@\1_d1[]),
.scbuf_dram\(.*\)_buf (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf3[]),
.scbuf_dram\(.*\) (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf2[]),
.dram_sctag\(.*\)_buf (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_sctag@\1_buf1[]),
.dram_sctag\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_sctag@\1_d1[]),
.sctag_dram\(.*\)_buf (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf3[]),
.sctag_dram\(.*\) (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf2[]),
);*/
//
dram_l2_buf2 dram_sc_0_rep1
(/*AUTOINST*/
// Outputs
.dram_scbuf_data_r2_buf (dram02_scbuf0_data_r2_buf1[127:0]), // Templated
.dram_scbuf_ecc_r2_buf (dram02_scbuf0_ecc_r2_buf1[27:0]), // Templated
.scbuf_dram_wr_data_r5_buf (scbuf0_dram02_wr_data_r5_buf3[63:0]), // Templated
.scbuf_dram_data_vld_r5_buf (scbuf0_dram02_data_vld_r5_buf3), // Templated
.scbuf_dram_data_mecc_r5_buf (scbuf0_dram02_data_mecc_r5_buf3), // Templated
.sctag_dram_rd_req_buf (sctag0_dram02_rd_req_buf3), // Templated
.sctag_dram_rd_dummy_req_buf (sctag0_dram02_rd_dummy_req_buf3), // Templated
.sctag_dram_rd_req_id_buf (sctag0_dram02_rd_req_id_buf3[2:0]), // Templated
.sctag_dram_addr_buf (sctag0_dram02_addr_buf3[39:5]), // Templated
.sctag_dram_wr_req_buf (sctag0_dram02_wr_req_buf3), // Templated
.dram_sctag_rd_ack_buf (dram02_sctag0_rd_ack_buf1), // Templated
.dram_sctag_wr_ack_buf (dram02_sctag0_wr_ack_buf1), // Templated
.dram_sctag_chunk_id_r0_buf (dram02_sctag0_chunk_id_r0_buf1[1:0]), // Templated
.dram_sctag_data_vld_r0_buf (dram02_sctag0_data_vld_r0_buf1), // Templated
.dram_sctag_rd_req_id_r0_buf (dram02_sctag0_rd_req_id_r0_buf1[2:0]), // Templated
.dram_sctag_secc_err_r2_buf (dram02_sctag0_secc_err_r2_buf1), // Templated
.dram_sctag_mecc_err_r2_buf (dram02_sctag0_mecc_err_r2_buf1), // Templated
.dram_sctag_scb_mecc_err_buf (dram02_sctag0_scb_mecc_err_buf1), // Templated
.dram_sctag_scb_secc_err_buf (dram02_sctag0_scb_secc_err_buf1), // Templated
// Inputs
.dram_scbuf_data_r2 (dram02_scbuf0_data_r2_d1[127:0]), // Templated
.dram_scbuf_ecc_r2 (dram02_scbuf0_ecc_r2_d1[27:0]), // Templated
.scbuf_dram_wr_data_r5 (scbuf0_dram02_wr_data_r5_buf2[63:0]), // Templated
.scbuf_dram_data_vld_r5 (scbuf0_dram02_data_vld_r5_buf2), // Templated
.scbuf_dram_data_mecc_r5 (scbuf0_dram02_data_mecc_r5_buf2), // Templated
.sctag_dram_rd_req (sctag0_dram02_rd_req_buf2), // Templated
.sctag_dram_rd_dummy_req (sctag0_dram02_rd_dummy_req_buf2), // Templated
.sctag_dram_rd_req_id (sctag0_dram02_rd_req_id_buf2[2:0]), // Templated
.sctag_dram_addr (sctag0_dram02_addr_buf2[39:5]), // Templated
.sctag_dram_wr_req (sctag0_dram02_wr_req_buf2), // Templated
.dram_sctag_rd_ack (dram02_sctag0_rd_ack_d1), // Templated
.dram_sctag_wr_ack (dram02_sctag0_wr_ack_d1), // Templated
.dram_sctag_chunk_id_r0 (dram02_sctag0_chunk_id_r0_d1[1:0]), // Templated
.dram_sctag_data_vld_r0 (dram02_sctag0_data_vld_r0_d1), // Templated
.dram_sctag_rd_req_id_r0 (dram02_sctag0_rd_req_id_r0_d1[2:0]), // Templated
.dram_sctag_secc_err_r2 (dram02_sctag0_secc_err_r2_d1), // Templated
.dram_sctag_mecc_err_r2 (dram02_sctag0_mecc_err_r2_d1), // Templated
.dram_sctag_scb_mecc_err (dram02_sctag0_scb_mecc_err_d1), // Templated
.dram_sctag_scb_secc_err (dram02_sctag0_scb_secc_err_d1)); // Templated
//
dram_l2_buf2 dram_sc_1_rep1
(/*AUTOINST*/
// Outputs
.dram_scbuf_data_r2_buf (dram13_scbuf1_data_r2_buf1[127:0]), // Templated
.dram_scbuf_ecc_r2_buf (dram13_scbuf1_ecc_r2_buf1[27:0]), // Templated
.scbuf_dram_wr_data_r5_buf (scbuf1_dram13_wr_data_r5_buf3[63:0]), // Templated
.scbuf_dram_data_vld_r5_buf (scbuf1_dram13_data_vld_r5_buf3), // Templated
.scbuf_dram_data_mecc_r5_buf (scbuf1_dram13_data_mecc_r5_buf3), // Templated
.sctag_dram_rd_req_buf (sctag1_dram13_rd_req_buf3), // Templated
.sctag_dram_rd_dummy_req_buf (sctag1_dram13_rd_dummy_req_buf3), // Templated
.sctag_dram_rd_req_id_buf (sctag1_dram13_rd_req_id_buf3[2:0]), // Templated
.sctag_dram_addr_buf (sctag1_dram13_addr_buf3[39:5]), // Templated
.sctag_dram_wr_req_buf (sctag1_dram13_wr_req_buf3), // Templated
.dram_sctag_rd_ack_buf (dram13_sctag1_rd_ack_buf1), // Templated
.dram_sctag_wr_ack_buf (dram13_sctag1_wr_ack_buf1), // Templated
.dram_sctag_chunk_id_r0_buf (dram13_sctag1_chunk_id_r0_buf1[1:0]), // Templated
.dram_sctag_data_vld_r0_buf (dram13_sctag1_data_vld_r0_buf1), // Templated
.dram_sctag_rd_req_id_r0_buf (dram13_sctag1_rd_req_id_r0_buf1[2:0]), // Templated
.dram_sctag_secc_err_r2_buf (dram13_sctag1_secc_err_r2_buf1), // Templated
.dram_sctag_mecc_err_r2_buf (dram13_sctag1_mecc_err_r2_buf1), // Templated
.dram_sctag_scb_mecc_err_buf (dram13_sctag1_scb_mecc_err_buf1), // Templated
.dram_sctag_scb_secc_err_buf (dram13_sctag1_scb_secc_err_buf1), // Templated
// Inputs
.dram_scbuf_data_r2 (dram13_scbuf1_data_r2_d1[127:0]), // Templated
.dram_scbuf_ecc_r2 (dram13_scbuf1_ecc_r2_d1[27:0]), // Templated
.scbuf_dram_wr_data_r5 (scbuf1_dram13_wr_data_r5_buf2[63:0]), // Templated
.scbuf_dram_data_vld_r5 (scbuf1_dram13_data_vld_r5_buf2), // Templated
.scbuf_dram_data_mecc_r5 (scbuf1_dram13_data_mecc_r5_buf2), // Templated
.sctag_dram_rd_req (sctag1_dram13_rd_req_buf2), // Templated
.sctag_dram_rd_dummy_req (sctag1_dram13_rd_dummy_req_buf2), // Templated
.sctag_dram_rd_req_id (sctag1_dram13_rd_req_id_buf2[2:0]), // Templated
.sctag_dram_addr (sctag1_dram13_addr_buf2[39:5]), // Templated
.sctag_dram_wr_req (sctag1_dram13_wr_req_buf2), // Templated
.dram_sctag_rd_ack (dram13_sctag1_rd_ack_d1), // Templated
.dram_sctag_wr_ack (dram13_sctag1_wr_ack_d1), // Templated
.dram_sctag_chunk_id_r0 (dram13_sctag1_chunk_id_r0_d1[1:0]), // Templated
.dram_sctag_data_vld_r0 (dram13_sctag1_data_vld_r0_d1), // Templated
.dram_sctag_rd_req_id_r0 (dram13_sctag1_rd_req_id_r0_d1[2:0]), // Templated
.dram_sctag_secc_err_r2 (dram13_sctag1_secc_err_r2_d1), // Templated
.dram_sctag_mecc_err_r2 (dram13_sctag1_mecc_err_r2_d1), // Templated
.dram_sctag_scb_mecc_err (dram13_sctag1_scb_mecc_err_d1), // Templated
.dram_sctag_scb_secc_err (dram13_sctag1_scb_secc_err_d1)); // Templated
//
dram_l2_buf2 dram_sc_2_rep1
(/*AUTOINST*/
// Outputs
.dram_scbuf_data_r2_buf (dram02_scbuf2_data_r2_buf1[127:0]), // Templated
.dram_scbuf_ecc_r2_buf (dram02_scbuf2_ecc_r2_buf1[27:0]), // Templated
.scbuf_dram_wr_data_r5_buf (scbuf2_dram02_wr_data_r5_buf3[63:0]), // Templated
.scbuf_dram_data_vld_r5_buf (scbuf2_dram02_data_vld_r5_buf3), // Templated
.scbuf_dram_data_mecc_r5_buf (scbuf2_dram02_data_mecc_r5_buf3), // Templated
.sctag_dram_rd_req_buf (sctag2_dram02_rd_req_buf3), // Templated
.sctag_dram_rd_dummy_req_buf (sctag2_dram02_rd_dummy_req_buf3), // Templated
.sctag_dram_rd_req_id_buf (sctag2_dram02_rd_req_id_buf3[2:0]), // Templated
.sctag_dram_addr_buf (sctag2_dram02_addr_buf3[39:5]), // Templated
.sctag_dram_wr_req_buf (sctag2_dram02_wr_req_buf3), // Templated
.dram_sctag_rd_ack_buf (dram02_sctag2_rd_ack_buf1), // Templated
.dram_sctag_wr_ack_buf (dram02_sctag2_wr_ack_buf1), // Templated
.dram_sctag_chunk_id_r0_buf (dram02_sctag2_chunk_id_r0_buf1[1:0]), // Templated
.dram_sctag_data_vld_r0_buf (dram02_sctag2_data_vld_r0_buf1), // Templated
.dram_sctag_rd_req_id_r0_buf (dram02_sctag2_rd_req_id_r0_buf1[2:0]), // Templated
.dram_sctag_secc_err_r2_buf (dram02_sctag2_secc_err_r2_buf1), // Templated
.dram_sctag_mecc_err_r2_buf (dram02_sctag2_mecc_err_r2_buf1), // Templated
.dram_sctag_scb_mecc_err_buf (dram02_sctag2_scb_mecc_err_buf1), // Templated
.dram_sctag_scb_secc_err_buf (dram02_sctag2_scb_secc_err_buf1), // Templated
// Inputs
.dram_scbuf_data_r2 (dram02_scbuf2_data_r2_d1[127:0]), // Templated
.dram_scbuf_ecc_r2 (dram02_scbuf2_ecc_r2_d1[27:0]), // Templated
.scbuf_dram_wr_data_r5 (scbuf2_dram02_wr_data_r5_buf2[63:0]), // Templated
.scbuf_dram_data_vld_r5 (scbuf2_dram02_data_vld_r5_buf2), // Templated
.scbuf_dram_data_mecc_r5 (scbuf2_dram02_data_mecc_r5_buf2), // Templated
.sctag_dram_rd_req (sctag2_dram02_rd_req_buf2), // Templated
.sctag_dram_rd_dummy_req (sctag2_dram02_rd_dummy_req_buf2), // Templated
.sctag_dram_rd_req_id (sctag2_dram02_rd_req_id_buf2[2:0]), // Templated
.sctag_dram_addr (sctag2_dram02_addr_buf2[39:5]), // Templated
.sctag_dram_wr_req (sctag2_dram02_wr_req_buf2), // Templated
.dram_sctag_rd_ack (dram02_sctag2_rd_ack_d1), // Templated
.dram_sctag_wr_ack (dram02_sctag2_wr_ack_d1), // Templated
.dram_sctag_chunk_id_r0 (dram02_sctag2_chunk_id_r0_d1[1:0]), // Templated
.dram_sctag_data_vld_r0 (dram02_sctag2_data_vld_r0_d1), // Templated
.dram_sctag_rd_req_id_r0 (dram02_sctag2_rd_req_id_r0_d1[2:0]), // Templated
.dram_sctag_secc_err_r2 (dram02_sctag2_secc_err_r2_d1), // Templated
.dram_sctag_mecc_err_r2 (dram02_sctag2_mecc_err_r2_d1), // Templated
.dram_sctag_scb_mecc_err (dram02_sctag2_scb_mecc_err_d1), // Templated
.dram_sctag_scb_secc_err (dram02_sctag2_scb_secc_err_d1)); // Templated
//
dram_l2_buf2 dram_sc_3_rep1
(/*AUTOINST*/
// Outputs
.dram_scbuf_data_r2_buf (dram13_scbuf3_data_r2_buf1[127:0]), // Templated
.dram_scbuf_ecc_r2_buf (dram13_scbuf3_ecc_r2_buf1[27:0]), // Templated
.scbuf_dram_wr_data_r5_buf (scbuf3_dram13_wr_data_r5_buf3[63:0]), // Templated
.scbuf_dram_data_vld_r5_buf (scbuf3_dram13_data_vld_r5_buf3), // Templated
.scbuf_dram_data_mecc_r5_buf (scbuf3_dram13_data_mecc_r5_buf3), // Templated
.sctag_dram_rd_req_buf (sctag3_dram13_rd_req_buf3), // Templated
.sctag_dram_rd_dummy_req_buf (sctag3_dram13_rd_dummy_req_buf3), // Templated
.sctag_dram_rd_req_id_buf (sctag3_dram13_rd_req_id_buf3[2:0]), // Templated
.sctag_dram_addr_buf (sctag3_dram13_addr_buf3[39:5]), // Templated
.sctag_dram_wr_req_buf (sctag3_dram13_wr_req_buf3), // Templated
.dram_sctag_rd_ack_buf (dram13_sctag3_rd_ack_buf1), // Templated
.dram_sctag_wr_ack_buf (dram13_sctag3_wr_ack_buf1), // Templated
.dram_sctag_chunk_id_r0_buf (dram13_sctag3_chunk_id_r0_buf1[1:0]), // Templated
.dram_sctag_data_vld_r0_buf (dram13_sctag3_data_vld_r0_buf1), // Templated
.dram_sctag_rd_req_id_r0_buf (dram13_sctag3_rd_req_id_r0_buf1[2:0]), // Templated
.dram_sctag_secc_err_r2_buf (dram13_sctag3_secc_err_r2_buf1), // Templated
.dram_sctag_mecc_err_r2_buf (dram13_sctag3_mecc_err_r2_buf1), // Templated
.dram_sctag_scb_mecc_err_buf (dram13_sctag3_scb_mecc_err_buf1), // Templated
.dram_sctag_scb_secc_err_buf (dram13_sctag3_scb_secc_err_buf1), // Templated
// Inputs
.dram_scbuf_data_r2 (dram13_scbuf3_data_r2_d1[127:0]), // Templated
.dram_scbuf_ecc_r2 (dram13_scbuf3_ecc_r2_d1[27:0]), // Templated
.scbuf_dram_wr_data_r5 (scbuf3_dram13_wr_data_r5_buf2[63:0]), // Templated
.scbuf_dram_data_vld_r5 (scbuf3_dram13_data_vld_r5_buf2), // Templated
.scbuf_dram_data_mecc_r5 (scbuf3_dram13_data_mecc_r5_buf2), // Templated
.sctag_dram_rd_req (sctag3_dram13_rd_req_buf2), // Templated
.sctag_dram_rd_dummy_req (sctag3_dram13_rd_dummy_req_buf2), // Templated
.sctag_dram_rd_req_id (sctag3_dram13_rd_req_id_buf2[2:0]), // Templated
.sctag_dram_addr (sctag3_dram13_addr_buf2[39:5]), // Templated
.sctag_dram_wr_req (sctag3_dram13_wr_req_buf2), // Templated
.dram_sctag_rd_ack (dram13_sctag3_rd_ack_d1), // Templated
.dram_sctag_wr_ack (dram13_sctag3_wr_ack_d1), // Templated
.dram_sctag_chunk_id_r0 (dram13_sctag3_chunk_id_r0_d1[1:0]), // Templated
.dram_sctag_data_vld_r0 (dram13_sctag3_data_vld_r0_d1), // Templated
.dram_sctag_rd_req_id_r0 (dram13_sctag3_rd_req_id_r0_d1[2:0]), // Templated
.dram_sctag_secc_err_r2 (dram13_sctag3_secc_err_r2_d1), // Templated
.dram_sctag_mecc_err_r2 (dram13_sctag3_mecc_err_r2_d1), // Templated
.dram_sctag_scb_mecc_err (dram13_sctag3_scb_mecc_err_d1), // Templated
.dram_sctag_scb_secc_err (dram13_sctag3_scb_secc_err_d1)); // Templated
//
/* dram_sc_0_rep2 AUTO_TEMPLATE (
.dram_scbuf\(.*\)_buf (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_scbuf@\1_buf2[]),
.dram_scbuf\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_scbuf@\1_buf1[]),
.dram_sctag\(.*\)_buf (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_sctag@\1_buf2[]),
.dram_sctag\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_sctag@\1_buf1[]),
.scbuf_dram\(.*\)_buf (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf2[]),
.scbuf_dram\(.*\) (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf1[]),
.sctag_dram\(.*\)_buf (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf2[]),
.sctag_dram\(.*\) (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1[]),
);*/
//
dram_sc_0_rep2 dram_sc_0_rep2
(/*AUTOINST*/
// Outputs
.dram_scbuf_data_r2_buf (dram02_scbuf0_data_r2_buf2[127:0]), // Templated
.dram_scbuf_ecc_r2_buf (dram02_scbuf0_ecc_r2_buf2[27:0]), // Templated
.scbuf_dram_wr_data_r5_buf (scbuf0_dram02_wr_data_r5_buf2[63:0]), // Templated
.scbuf_dram_data_vld_r5_buf (scbuf0_dram02_data_vld_r5_buf2), // Templated
.scbuf_dram_data_mecc_r5_buf (scbuf0_dram02_data_mecc_r5_buf2), // Templated
.sctag_dram_rd_req_buf (sctag0_dram02_rd_req_buf2), // Templated
.sctag_dram_rd_dummy_req_buf (sctag0_dram02_rd_dummy_req_buf2), // Templated
.sctag_dram_rd_req_id_buf (sctag0_dram02_rd_req_id_buf2[2:0]), // Templated
.sctag_dram_addr_buf (sctag0_dram02_addr_buf2[39:5]), // Templated
.sctag_dram_wr_req_buf (sctag0_dram02_wr_req_buf2), // Templated
.dram_sctag_rd_ack_buf (dram02_sctag0_rd_ack_buf2), // Templated
.dram_sctag_wr_ack_buf (dram02_sctag0_wr_ack_buf2), // Templated
.dram_sctag_chunk_id_r0_buf (dram02_sctag0_chunk_id_r0_buf2[1:0]), // Templated
.dram_sctag_data_vld_r0_buf (dram02_sctag0_data_vld_r0_buf2), // Templated
.dram_sctag_rd_req_id_r0_buf (dram02_sctag0_rd_req_id_r0_buf2[2:0]), // Templated
.dram_sctag_secc_err_r2_buf (dram02_sctag0_secc_err_r2_buf2), // Templated
.dram_sctag_mecc_err_r2_buf (dram02_sctag0_mecc_err_r2_buf2), // Templated
.dram_sctag_scb_mecc_err_buf (dram02_sctag0_scb_mecc_err_buf2), // Templated
.dram_sctag_scb_secc_err_buf (dram02_sctag0_scb_secc_err_buf2), // Templated
// Inputs
.dram_scbuf_data_r2 (dram02_scbuf0_data_r2_buf1[127:0]), // Templated
.dram_scbuf_ecc_r2 (dram02_scbuf0_ecc_r2_buf1[27:0]), // Templated
.scbuf_dram_wr_data_r5 (scbuf0_dram02_wr_data_r5_buf1[63:0]), // Templated
.scbuf_dram_data_vld_r5 (scbuf0_dram02_data_vld_r5_buf1), // Templated
.scbuf_dram_data_mecc_r5 (scbuf0_dram02_data_mecc_r5_buf1), // Templated
.sctag_dram_rd_req (sctag0_dram02_rd_req), // Templated
.sctag_dram_rd_dummy_req (sctag0_dram02_rd_dummy_req), // Templated
.sctag_dram_rd_req_id (sctag0_dram02_rd_req_id[2:0]), // Templated
.sctag_dram_addr (sctag0_dram02_addr[39:5]), // Templated
.sctag_dram_wr_req (sctag0_dram02_wr_req), // Templated
.dram_sctag_rd_ack (dram02_sctag0_rd_ack_buf1), // Templated
.dram_sctag_wr_ack (dram02_sctag0_wr_ack_buf1), // Templated
.dram_sctag_chunk_id_r0 (dram02_sctag0_chunk_id_r0_buf1[1:0]), // Templated
.dram_sctag_data_vld_r0 (dram02_sctag0_data_vld_r0_buf1), // Templated
.dram_sctag_rd_req_id_r0 (dram02_sctag0_rd_req_id_r0_buf1[2:0]), // Templated
.dram_sctag_secc_err_r2 (dram02_sctag0_secc_err_r2_buf1), // Templated
.dram_sctag_mecc_err_r2 (dram02_sctag0_mecc_err_r2_buf1), // Templated
.dram_sctag_scb_mecc_err (dram02_sctag0_scb_mecc_err_buf1), // Templated
.dram_sctag_scb_secc_err (dram02_sctag0_scb_secc_err_buf1)); // Templated
//
/* dram_sc_1_rep2 AUTO_TEMPLATE (
.dram_scbuf\(.*\)_buf (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_scbuf@\1_buf2[]),
.dram_scbuf\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_scbuf@\1_buf1[]),
.dram_sctag\(.*\)_buf (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_sctag@\1_buf2[]),
.dram_sctag\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_sctag@\1_buf1[]),
.scbuf_dram\(.*\)_buf (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf2[]),
.scbuf_dram\(.*\) (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf1[]),
.sctag_dram\(.*\)_buf (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf2[]),
.sctag_dram\(.*\) (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1[]),
);*/
//
dram_sc_1_rep2 dram_sc_1_rep2
(/*AUTOINST*/
// Outputs
.dram_scbuf_data_r2_buf (dram13_scbuf1_data_r2_buf2[127:0]), // Templated
.dram_scbuf_ecc_r2_buf (dram13_scbuf1_ecc_r2_buf2[27:0]), // Templated
.scbuf_dram_wr_data_r5_buf (scbuf1_dram13_wr_data_r5_buf2[63:0]), // Templated
.scbuf_dram_data_vld_r5_buf (scbuf1_dram13_data_vld_r5_buf2), // Templated
.scbuf_dram_data_mecc_r5_buf (scbuf1_dram13_data_mecc_r5_buf2), // Templated
.sctag_dram_rd_req_buf (sctag1_dram13_rd_req_buf2), // Templated
.sctag_dram_rd_dummy_req_buf (sctag1_dram13_rd_dummy_req_buf2), // Templated
.sctag_dram_rd_req_id_buf (sctag1_dram13_rd_req_id_buf2[2:0]), // Templated
.sctag_dram_addr_buf (sctag1_dram13_addr_buf2[39:5]), // Templated
.sctag_dram_wr_req_buf (sctag1_dram13_wr_req_buf2), // Templated
.dram_sctag_rd_ack_buf (dram13_sctag1_rd_ack_buf2), // Templated
.dram_sctag_wr_ack_buf (dram13_sctag1_wr_ack_buf2), // Templated
.dram_sctag_chunk_id_r0_buf (dram13_sctag1_chunk_id_r0_buf2[1:0]), // Templated
.dram_sctag_data_vld_r0_buf (dram13_sctag1_data_vld_r0_buf2), // Templated
.dram_sctag_rd_req_id_r0_buf (dram13_sctag1_rd_req_id_r0_buf2[2:0]), // Templated
.dram_sctag_secc_err_r2_buf (dram13_sctag1_secc_err_r2_buf2), // Templated
.dram_sctag_mecc_err_r2_buf (dram13_sctag1_mecc_err_r2_buf2), // Templated
.dram_sctag_scb_mecc_err_buf (dram13_sctag1_scb_mecc_err_buf2), // Templated
.dram_sctag_scb_secc_err_buf (dram13_sctag1_scb_secc_err_buf2), // Templated
// Inputs
.dram_scbuf_data_r2 (dram13_scbuf1_data_r2_buf1[127:0]), // Templated
.dram_scbuf_ecc_r2 (dram13_scbuf1_ecc_r2_buf1[27:0]), // Templated
.scbuf_dram_wr_data_r5 (scbuf1_dram13_wr_data_r5_buf1[63:0]), // Templated
.scbuf_dram_data_vld_r5 (scbuf1_dram13_data_vld_r5_buf1), // Templated
.scbuf_dram_data_mecc_r5 (scbuf1_dram13_data_mecc_r5_buf1), // Templated
.sctag_dram_rd_req (sctag1_dram13_rd_req), // Templated
.sctag_dram_rd_dummy_req (sctag1_dram13_rd_dummy_req), // Templated
.sctag_dram_rd_req_id (sctag1_dram13_rd_req_id[2:0]), // Templated
.sctag_dram_addr (sctag1_dram13_addr[39:5]), // Templated
.sctag_dram_wr_req (sctag1_dram13_wr_req), // Templated
.dram_sctag_rd_ack (dram13_sctag1_rd_ack_buf1), // Templated
.dram_sctag_wr_ack (dram13_sctag1_wr_ack_buf1), // Templated
.dram_sctag_chunk_id_r0 (dram13_sctag1_chunk_id_r0_buf1[1:0]), // Templated
.dram_sctag_data_vld_r0 (dram13_sctag1_data_vld_r0_buf1), // Templated
.dram_sctag_rd_req_id_r0 (dram13_sctag1_rd_req_id_r0_buf1[2:0]), // Templated
.dram_sctag_secc_err_r2 (dram13_sctag1_secc_err_r2_buf1), // Templated
.dram_sctag_mecc_err_r2 (dram13_sctag1_mecc_err_r2_buf1), // Templated
.dram_sctag_scb_mecc_err (dram13_sctag1_scb_mecc_err_buf1), // Templated
.dram_sctag_scb_secc_err (dram13_sctag1_scb_secc_err_buf1)); // Templated
//
/* dram_sc_2_rep2 AUTO_TEMPLATE (
.dram_scbuf\(.*\)_buf (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_scbuf@\1_buf2[]),
.dram_scbuf\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_scbuf@\1_buf1[]),
.dram_sctag\(.*\)_buf (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_sctag@\1_buf2[]),
.dram_sctag\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_sctag@\1_buf1[]),
.scbuf_dram\(.*\)_buf (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf2[]),
.scbuf_dram\(.*\) (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf1[]),
.sctag_dram\(.*\)_buf (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf2[]),
.sctag_dram\(.*\) (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1[]),
);*/
//
dram_sc_2_rep2 dram_sc_2_rep2
(/*AUTOINST*/
// Outputs
.dram_scbuf_data_r2_buf (dram02_scbuf2_data_r2_buf2[127:0]), // Templated
.dram_scbuf_ecc_r2_buf (dram02_scbuf2_ecc_r2_buf2[27:0]), // Templated
.scbuf_dram_wr_data_r5_buf (scbuf2_dram02_wr_data_r5_buf2[63:0]), // Templated
.scbuf_dram_data_vld_r5_buf (scbuf2_dram02_data_vld_r5_buf2), // Templated
.scbuf_dram_data_mecc_r5_buf (scbuf2_dram02_data_mecc_r5_buf2), // Templated
.sctag_dram_rd_req_buf (sctag2_dram02_rd_req_buf2), // Templated
.sctag_dram_rd_dummy_req_buf (sctag2_dram02_rd_dummy_req_buf2), // Templated
.sctag_dram_rd_req_id_buf (sctag2_dram02_rd_req_id_buf2[2:0]), // Templated
.sctag_dram_addr_buf (sctag2_dram02_addr_buf2[39:5]), // Templated
.sctag_dram_wr_req_buf (sctag2_dram02_wr_req_buf2), // Templated
.dram_sctag_rd_ack_buf (dram02_sctag2_rd_ack_buf2), // Templated
.dram_sctag_wr_ack_buf (dram02_sctag2_wr_ack_buf2), // Templated
.dram_sctag_chunk_id_r0_buf (dram02_sctag2_chunk_id_r0_buf2[1:0]), // Templated
.dram_sctag_data_vld_r0_buf (dram02_sctag2_data_vld_r0_buf2), // Templated
.dram_sctag_rd_req_id_r0_buf (dram02_sctag2_rd_req_id_r0_buf2[2:0]), // Templated
.dram_sctag_secc_err_r2_buf (dram02_sctag2_secc_err_r2_buf2), // Templated
.dram_sctag_mecc_err_r2_buf (dram02_sctag2_mecc_err_r2_buf2), // Templated
.dram_sctag_scb_mecc_err_buf (dram02_sctag2_scb_mecc_err_buf2), // Templated
.dram_sctag_scb_secc_err_buf (dram02_sctag2_scb_secc_err_buf2), // Templated
// Inputs
.dram_scbuf_data_r2 (dram02_scbuf2_data_r2_buf1[127:0]), // Templated
.dram_scbuf_ecc_r2 (dram02_scbuf2_ecc_r2_buf1[27:0]), // Templated
.scbuf_dram_wr_data_r5 (scbuf2_dram02_wr_data_r5_buf1[63:0]), // Templated
.scbuf_dram_data_vld_r5 (scbuf2_dram02_data_vld_r5_buf1), // Templated
.scbuf_dram_data_mecc_r5 (scbuf2_dram02_data_mecc_r5_buf1), // Templated
.sctag_dram_rd_req (sctag2_dram02_rd_req), // Templated
.sctag_dram_rd_dummy_req (sctag2_dram02_rd_dummy_req), // Templated
.sctag_dram_rd_req_id (sctag2_dram02_rd_req_id[2:0]), // Templated
.sctag_dram_addr (sctag2_dram02_addr[39:5]), // Templated
.sctag_dram_wr_req (sctag2_dram02_wr_req), // Templated
.dram_sctag_rd_ack (dram02_sctag2_rd_ack_buf1), // Templated
.dram_sctag_wr_ack (dram02_sctag2_wr_ack_buf1), // Templated
.dram_sctag_chunk_id_r0 (dram02_sctag2_chunk_id_r0_buf1[1:0]), // Templated
.dram_sctag_data_vld_r0 (dram02_sctag2_data_vld_r0_buf1), // Templated
.dram_sctag_rd_req_id_r0 (dram02_sctag2_rd_req_id_r0_buf1[2:0]), // Templated
.dram_sctag_secc_err_r2 (dram02_sctag2_secc_err_r2_buf1), // Templated
.dram_sctag_mecc_err_r2 (dram02_sctag2_mecc_err_r2_buf1), // Templated
.dram_sctag_scb_mecc_err (dram02_sctag2_scb_mecc_err_buf1), // Templated
.dram_sctag_scb_secc_err (dram02_sctag2_scb_secc_err_buf1)); // Templated
//
/* dram_sc_3_rep2 AUTO_TEMPLATE (
.dram_scbuf\(.*\)_buf (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_scbuf@\1_buf2[]),
.dram_scbuf\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_scbuf@\1_buf1[]),
.dram_sctag\(.*\)_buf (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_sctag@\1_buf2[]),
.dram_sctag\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_sctag@\1_buf1[]),
.scbuf_dram\(.*\)_buf (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf2[]),
.scbuf_dram\(.*\) (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf1[]),
.sctag_dram\(.*\)_buf (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf2[]),
.sctag_dram\(.*\) (sctag@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1[]),
);*/
//
dram_sc_3_rep2 dram_sc_3_rep2
(/*AUTOINST*/
// Outputs
.dram_scbuf_data_r2_buf (dram13_scbuf3_data_r2_buf2[127:0]), // Templated
.dram_scbuf_ecc_r2_buf (dram13_scbuf3_ecc_r2_buf2[27:0]), // Templated
.scbuf_dram_wr_data_r5_buf (scbuf3_dram13_wr_data_r5_buf2[63:0]), // Templated
.scbuf_dram_data_vld_r5_buf (scbuf3_dram13_data_vld_r5_buf2), // Templated
.scbuf_dram_data_mecc_r5_buf (scbuf3_dram13_data_mecc_r5_buf2), // Templated
.sctag_dram_rd_req_buf (sctag3_dram13_rd_req_buf2), // Templated
.sctag_dram_rd_dummy_req_buf (sctag3_dram13_rd_dummy_req_buf2), // Templated
.sctag_dram_rd_req_id_buf (sctag3_dram13_rd_req_id_buf2[2:0]), // Templated
.sctag_dram_addr_buf (sctag3_dram13_addr_buf2[39:5]), // Templated
.sctag_dram_wr_req_buf (sctag3_dram13_wr_req_buf2), // Templated
.dram_sctag_rd_ack_buf (dram13_sctag3_rd_ack_buf2), // Templated
.dram_sctag_wr_ack_buf (dram13_sctag3_wr_ack_buf2), // Templated
.dram_sctag_chunk_id_r0_buf (dram13_sctag3_chunk_id_r0_buf2[1:0]), // Templated
.dram_sctag_data_vld_r0_buf (dram13_sctag3_data_vld_r0_buf2), // Templated
.dram_sctag_rd_req_id_r0_buf (dram13_sctag3_rd_req_id_r0_buf2[2:0]), // Templated
.dram_sctag_secc_err_r2_buf (dram13_sctag3_secc_err_r2_buf2), // Templated
.dram_sctag_mecc_err_r2_buf (dram13_sctag3_mecc_err_r2_buf2), // Templated
.dram_sctag_scb_mecc_err_buf (dram13_sctag3_scb_mecc_err_buf2), // Templated
.dram_sctag_scb_secc_err_buf (dram13_sctag3_scb_secc_err_buf2), // Templated
// Inputs
.dram_scbuf_data_r2 (dram13_scbuf3_data_r2_buf1[127:0]), // Templated
.dram_scbuf_ecc_r2 (dram13_scbuf3_ecc_r2_buf1[27:0]), // Templated
.scbuf_dram_wr_data_r5 (scbuf3_dram13_wr_data_r5_buf1[63:0]), // Templated
.scbuf_dram_data_vld_r5 (scbuf3_dram13_data_vld_r5_buf1), // Templated
.scbuf_dram_data_mecc_r5 (scbuf3_dram13_data_mecc_r5_buf1), // Templated
.sctag_dram_rd_req (sctag3_dram13_rd_req), // Templated
.sctag_dram_rd_dummy_req (sctag3_dram13_rd_dummy_req), // Templated
.sctag_dram_rd_req_id (sctag3_dram13_rd_req_id[2:0]), // Templated
.sctag_dram_addr (sctag3_dram13_addr[39:5]), // Templated
.sctag_dram_wr_req (sctag3_dram13_wr_req), // Templated
.dram_sctag_rd_ack (dram13_sctag3_rd_ack_buf1), // Templated
.dram_sctag_wr_ack (dram13_sctag3_wr_ack_buf1), // Templated
.dram_sctag_chunk_id_r0 (dram13_sctag3_chunk_id_r0_buf1[1:0]), // Templated
.dram_sctag_data_vld_r0 (dram13_sctag3_data_vld_r0_buf1), // Templated
.dram_sctag_rd_req_id_r0 (dram13_sctag3_rd_req_id_r0_buf1[2:0]), // Templated
.dram_sctag_secc_err_r2 (dram13_sctag3_secc_err_r2_buf1), // Templated
.dram_sctag_mecc_err_r2 (dram13_sctag3_mecc_err_r2_buf1), // Templated
.dram_sctag_scb_mecc_err (dram13_sctag3_scb_mecc_err_buf1), // Templated
.dram_sctag_scb_secc_err (dram13_sctag3_scb_secc_err_buf1)); // Templated
//
/* dram_l2_buf2 AUTO_TEMPLATE (
.dram_scbuf\(.*\)_buf (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_scbuf@\1_buf3[]),
.dram_scbuf\(.*\) (dram@"(% @ 2)"@"(+ (% @ 2) 2)"_scbuf@\1_buf2[]),
.scbuf_dram\(.*\)_buf (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1_buf1[]),
.scbuf_dram\(.*\) (scbuf@_dram@"(% @ 2)"@"(+ (% @ 2) 2)"\1[]),
.sctag_dram_rd_req (1'b0),
.sctag_dram_rd_dummy_req (1'b0),
.sctag_dram_rd_req_id (3'b0),
.sctag_dram_addr (35'b0),
.sctag_dram_wr_req (1'b0),
.dram_sctag_rd_ack (1'b0),
.dram_sctag_wr_ack (1'b0),
.dram_sctag_chunk_id_r0 (2'b0),
.dram_sctag_data_vld_r0 (1'b0),
.dram_sctag_rd_req_id_r0 (3'b0),
.dram_sctag_secc_err_r2 (1'b0),
.dram_sctag_mecc_err_r2 (1'b0),
.dram_sctag_scb_mecc_err (1'b0),
.dram_sctag_scb_secc_err (1'b0),
.dram_sctag\(.*\) (),
.sctag_dram\(.*\) (),
);*/
//
dram_l2_buf2 dram_sc_0_rep3
(/*AUTOINST*/
// Outputs
.dram_scbuf_data_r2_buf (dram02_scbuf0_data_r2_buf3[127:0]), // Templated
.dram_scbuf_ecc_r2_buf (dram02_scbuf0_ecc_r2_buf3[27:0]), // Templated
.scbuf_dram_wr_data_r5_buf (scbuf0_dram02_wr_data_r5_buf1[63:0]), // Templated
.scbuf_dram_data_vld_r5_buf (scbuf0_dram02_data_vld_r5_buf1), // Templated
.scbuf_dram_data_mecc_r5_buf (scbuf0_dram02_data_mecc_r5_buf1), // Templated
.sctag_dram_rd_req_buf (), // Templated
.sctag_dram_rd_dummy_req_buf (), // Templated
.sctag_dram_rd_req_id_buf (), // Templated
.sctag_dram_addr_buf (), // Templated
.sctag_dram_wr_req_buf (), // Templated
.dram_sctag_rd_ack_buf (), // Templated
.dram_sctag_wr_ack_buf (), // Templated
.dram_sctag_chunk_id_r0_buf (), // Templated
.dram_sctag_data_vld_r0_buf (), // Templated
.dram_sctag_rd_req_id_r0_buf (), // Templated
.dram_sctag_secc_err_r2_buf (), // Templated
.dram_sctag_mecc_err_r2_buf (), // Templated
.dram_sctag_scb_mecc_err_buf (), // Templated
.dram_sctag_scb_secc_err_buf (), // Templated
// Inputs
.dram_scbuf_data_r2 (dram02_scbuf0_data_r2_buf2[127:0]), // Templated
.dram_scbuf_ecc_r2 (dram02_scbuf0_ecc_r2_buf2[27:0]), // Templated
.scbuf_dram_wr_data_r5 (scbuf0_dram02_wr_data_r5[63:0]), // Templated
.scbuf_dram_data_vld_r5 (scbuf0_dram02_data_vld_r5), // Templated
.scbuf_dram_data_mecc_r5 (scbuf0_dram02_data_mecc_r5), // Templated
.sctag_dram_rd_req (1'b0), // Templated
.sctag_dram_rd_dummy_req (1'b0), // Templated
.sctag_dram_rd_req_id (3'b0), // Templated
.sctag_dram_addr (35'b0), // Templated
.sctag_dram_wr_req (1'b0), // Templated
.dram_sctag_rd_ack (1'b0), // Templated
.dram_sctag_wr_ack (1'b0), // Templated
.dram_sctag_chunk_id_r0 (2'b0), // Templated
.dram_sctag_data_vld_r0 (1'b0), // Templated
.dram_sctag_rd_req_id_r0 (3'b0), // Templated
.dram_sctag_secc_err_r2 (1'b0), // Templated
.dram_sctag_mecc_err_r2 (1'b0), // Templated
.dram_sctag_scb_mecc_err (1'b0), // Templated
.dram_sctag_scb_secc_err (1'b0)); // Templated
//
dram_l2_buf2 dram_sc_1_rep3
(/*AUTOINST*/
// Outputs
.dram_scbuf_data_r2_buf (dram13_scbuf1_data_r2_buf3[127:0]), // Templated
.dram_scbuf_ecc_r2_buf (dram13_scbuf1_ecc_r2_buf3[27:0]), // Templated
.scbuf_dram_wr_data_r5_buf (scbuf1_dram13_wr_data_r5_buf1[63:0]), // Templated
.scbuf_dram_data_vld_r5_buf (scbuf1_dram13_data_vld_r5_buf1), // Templated
.scbuf_dram_data_mecc_r5_buf (scbuf1_dram13_data_mecc_r5_buf1), // Templated
.sctag_dram_rd_req_buf (), // Templated
.sctag_dram_rd_dummy_req_buf (), // Templated
.sctag_dram_rd_req_id_buf (), // Templated
.sctag_dram_addr_buf (), // Templated
.sctag_dram_wr_req_buf (), // Templated
.dram_sctag_rd_ack_buf (), // Templated
.dram_sctag_wr_ack_buf (), // Templated
.dram_sctag_chunk_id_r0_buf (), // Templated
.dram_sctag_data_vld_r0_buf (), // Templated
.dram_sctag_rd_req_id_r0_buf (), // Templated
.dram_sctag_secc_err_r2_buf (), // Templated
.dram_sctag_mecc_err_r2_buf (), // Templated
.dram_sctag_scb_mecc_err_buf (), // Templated
.dram_sctag_scb_secc_err_buf (), // Templated
// Inputs
.dram_scbuf_data_r2 (dram13_scbuf1_data_r2_buf2[127:0]), // Templated
.dram_scbuf_ecc_r2 (dram13_scbuf1_ecc_r2_buf2[27:0]), // Templated
.scbuf_dram_wr_data_r5 (scbuf1_dram13_wr_data_r5[63:0]), // Templated
.scbuf_dram_data_vld_r5 (scbuf1_dram13_data_vld_r5), // Templated
.scbuf_dram_data_mecc_r5 (scbuf1_dram13_data_mecc_r5), // Templated
.sctag_dram_rd_req (1'b0), // Templated
.sctag_dram_rd_dummy_req (1'b0), // Templated
.sctag_dram_rd_req_id (3'b0), // Templated
.sctag_dram_addr (35'b0), // Templated
.sctag_dram_wr_req (1'b0), // Templated
.dram_sctag_rd_ack (1'b0), // Templated
.dram_sctag_wr_ack (1'b0), // Templated
.dram_sctag_chunk_id_r0 (2'b0), // Templated
.dram_sctag_data_vld_r0 (1'b0), // Templated
.dram_sctag_rd_req_id_r0 (3'b0), // Templated
.dram_sctag_secc_err_r2 (1'b0), // Templated
.dram_sctag_mecc_err_r2 (1'b0), // Templated
.dram_sctag_scb_mecc_err (1'b0), // Templated
.dram_sctag_scb_secc_err (1'b0)); // Templated
//
dram_l2_buf2 dram_sc_2_rep3
(/*AUTOINST*/
// Outputs
.dram_scbuf_data_r2_buf (dram02_scbuf2_data_r2_buf3[127:0]), // Templated
.dram_scbuf_ecc_r2_buf (dram02_scbuf2_ecc_r2_buf3[27:0]), // Templated
.scbuf_dram_wr_data_r5_buf (scbuf2_dram02_wr_data_r5_buf1[63:0]), // Templated
.scbuf_dram_data_vld_r5_buf (scbuf2_dram02_data_vld_r5_buf1), // Templated
.scbuf_dram_data_mecc_r5_buf (scbuf2_dram02_data_mecc_r5_buf1), // Templated
.sctag_dram_rd_req_buf (), // Templated
.sctag_dram_rd_dummy_req_buf (), // Templated
.sctag_dram_rd_req_id_buf (), // Templated
.sctag_dram_addr_buf (), // Templated
.sctag_dram_wr_req_buf (), // Templated
.dram_sctag_rd_ack_buf (), // Templated
.dram_sctag_wr_ack_buf (), // Templated
.dram_sctag_chunk_id_r0_buf (), // Templated
.dram_sctag_data_vld_r0_buf (), // Templated
.dram_sctag_rd_req_id_r0_buf (), // Templated
.dram_sctag_secc_err_r2_buf (), // Templated
.dram_sctag_mecc_err_r2_buf (), // Templated
.dram_sctag_scb_mecc_err_buf (), // Templated
.dram_sctag_scb_secc_err_buf (), // Templated
// Inputs
.dram_scbuf_data_r2 (dram02_scbuf2_data_r2_buf2[127:0]), // Templated
.dram_scbuf_ecc_r2 (dram02_scbuf2_ecc_r2_buf2[27:0]), // Templated
.scbuf_dram_wr_data_r5 (scbuf2_dram02_wr_data_r5[63:0]), // Templated
.scbuf_dram_data_vld_r5 (scbuf2_dram02_data_vld_r5), // Templated
.scbuf_dram_data_mecc_r5 (scbuf2_dram02_data_mecc_r5), // Templated
.sctag_dram_rd_req (1'b0), // Templated
.sctag_dram_rd_dummy_req (1'b0), // Templated
.sctag_dram_rd_req_id (3'b0), // Templated
.sctag_dram_addr (35'b0), // Templated
.sctag_dram_wr_req (1'b0), // Templated
.dram_sctag_rd_ack (1'b0), // Templated
.dram_sctag_wr_ack (1'b0), // Templated
.dram_sctag_chunk_id_r0 (2'b0), // Templated
.dram_sctag_data_vld_r0 (1'b0), // Templated
.dram_sctag_rd_req_id_r0 (3'b0), // Templated
.dram_sctag_secc_err_r2 (1'b0), // Templated
.dram_sctag_mecc_err_r2 (1'b0), // Templated
.dram_sctag_scb_mecc_err (1'b0), // Templated
.dram_sctag_scb_secc_err (1'b0)); // Templated
//
dram_l2_buf2 dram_sc_3_rep3
(/*AUTOINST*/
// Outputs
.dram_scbuf_data_r2_buf (dram13_scbuf3_data_r2_buf3[127:0]), // Templated
.dram_scbuf_ecc_r2_buf (dram13_scbuf3_ecc_r2_buf3[27:0]), // Templated
.scbuf_dram_wr_data_r5_buf (scbuf3_dram13_wr_data_r5_buf1[63:0]), // Templated
.scbuf_dram_data_vld_r5_buf (scbuf3_dram13_data_vld_r5_buf1), // Templated
.scbuf_dram_data_mecc_r5_buf (scbuf3_dram13_data_mecc_r5_buf1), // Templated
.sctag_dram_rd_req_buf (), // Templated
.sctag_dram_rd_dummy_req_buf (), // Templated
.sctag_dram_rd_req_id_buf (), // Templated
.sctag_dram_addr_buf (), // Templated
.sctag_dram_wr_req_buf (), // Templated
.dram_sctag_rd_ack_buf (), // Templated
.dram_sctag_wr_ack_buf (), // Templated
.dram_sctag_chunk_id_r0_buf (), // Templated
.dram_sctag_data_vld_r0_buf (), // Templated
.dram_sctag_rd_req_id_r0_buf (), // Templated
.dram_sctag_secc_err_r2_buf (), // Templated
.dram_sctag_mecc_err_r2_buf (), // Templated
.dram_sctag_scb_mecc_err_buf (), // Templated
.dram_sctag_scb_secc_err_buf (), // Templated
// Inputs
.dram_scbuf_data_r2 (dram13_scbuf3_data_r2_buf2[127:0]), // Templated
.dram_scbuf_ecc_r2 (dram13_scbuf3_ecc_r2_buf2[27:0]), // Templated
.scbuf_dram_wr_data_r5 (scbuf3_dram13_wr_data_r5[63:0]), // Templated
.scbuf_dram_data_vld_r5 (scbuf3_dram13_data_vld_r5), // Templated
.scbuf_dram_data_mecc_r5 (scbuf3_dram13_data_mecc_r5), // Templated
.sctag_dram_rd_req (1'b0), // Templated
.sctag_dram_rd_dummy_req (1'b0), // Templated
.sctag_dram_rd_req_id (3'b0), // Templated
.sctag_dram_addr (35'b0), // Templated
.sctag_dram_wr_req (1'b0), // Templated
.dram_sctag_rd_ack (1'b0), // Templated
.dram_sctag_wr_ack (1'b0), // Templated
.dram_sctag_chunk_id_r0 (2'b0), // Templated
.dram_sctag_data_vld_r0 (1'b0), // Templated
.dram_sctag_rd_req_id_r0 (3'b0), // Templated
.dram_sctag_secc_err_r2 (1'b0), // Templated
.dram_sctag_mecc_err_r2 (1'b0), // Templated
.dram_sctag_scb_mecc_err (1'b0), // Templated
.dram_sctag_scb_secc_err (1'b0)); // Templated
//
/* ff_jbi_sc0_1 AUTO_TEMPLATE (
.rclk (ccx_rclk),
.se (global_shift_enable),
.si (rsc12_rsc01_so),
.so (rsc01_rsc11_so),
.scbuf_jbi_\(.*\)_d1 (scbuf@_jbi_\1_d2[]),
.scbuf_jbi_\(.*\) (scbuf@_jbi_\1_d1_buf1[]),
.sctag_jbi_\(.*\)_d1 (sctag@_jbi_\1_d2[]),
.sctag_jbi_\(.*\) (sctag@_jbi_\1_d1_buf1[]),
.jbi_scbuf_\(.*\) (jbi_scbuf@_\1[]),
.jbi_sctag_\(.*\) (jbi_sctag@_\1[]),
);*/
//
ff_jbi_sc0_1 ff_jbi_sc0_1
(/*AUTOINST*/
// Outputs
.jbi_sctag_req_d1 (jbi_sctag0_req_d1[31:0]), // Templated
.scbuf_jbi_data_d1 (scbuf0_jbi_data_d2[31:0]), // Templated
.jbi_scbuf_ecc_d1 (jbi_scbuf0_ecc_d1[6:0]), // Templated
.jbi_sctag_req_vld_d1 (jbi_sctag0_req_vld_d1), // Templated
.scbuf_jbi_ctag_vld_d1 (scbuf0_jbi_ctag_vld_d2), // Templated
.scbuf_jbi_ue_err_d1 (scbuf0_jbi_ue_err_d2), // Templated
.sctag_jbi_iq_dequeue_d1 (sctag0_jbi_iq_dequeue_d2), // Templated
.sctag_jbi_wib_dequeue_d1 (sctag0_jbi_wib_dequeue_d2), // Templated
.sctag_jbi_por_req_d1 (sctag0_jbi_por_req_d2), // Templated
.so (rsc01_rsc11_so), // Templated
// Inputs
.jbi_sctag_req (jbi_sctag0_req[31:0]), // Templated
.scbuf_jbi_data (scbuf0_jbi_data_d1_buf1[31:0]), // Templated
.jbi_scbuf_ecc (jbi_scbuf0_ecc[6:0]), // Templated
.jbi_sctag_req_vld (jbi_sctag0_req_vld), // Templated
.scbuf_jbi_ctag_vld (scbuf0_jbi_ctag_vld_d1_buf1), // Templated
.scbuf_jbi_ue_err (scbuf0_jbi_ue_err_d1_buf1), // Templated
.sctag_jbi_iq_dequeue (sctag0_jbi_iq_dequeue_d1_buf1), // Templated
.sctag_jbi_wib_dequeue (sctag0_jbi_wib_dequeue_d1_buf1), // Templated
.sctag_jbi_por_req (sctag0_jbi_por_req_d1_buf1), // Templated
.rclk (ccx_rclk), // Templated
.si (rsc12_rsc01_so), // Templated
.se (global_shift_enable)); // Templated
//
/* ff_jbi_sc1_1 AUTO_TEMPLATE (
.rclk (ccx_rclk),
.se (global_shift_enable),
.si (rsc01_rsc11_so),
.so (rsc11_rsc21_so),
.scbuf_jbi_\(.*\)_d1 (scbuf@_jbi_\1_d2[]),
.scbuf_jbi_\(.*\) (scbuf@_jbi_\1_d1_buf1[]),
.sctag_jbi_\(.*\)_d1 (sctag@_jbi_\1_d2[]),
.sctag_jbi_\(.*\) (sctag@_jbi_\1_d1_buf1[]),
.jbi_sctag_\(.*\)_d1 (jbi_sctag@_\1_d1[]),
.jbi_sctag_\(.*\) (jbi_sctag@_\1[]),
.jbi_scbuf_\(.*\)_d1 (jbi_scbuf@_\1_d1[]),
.jbi_scbuf_\(.*\) (jbi_scbuf@_\1[]),
);*/
//
ff_jbi_sc1_1 ff_jbi_sc1_1
(/*AUTOINST*/
// Outputs
.jbi_sctag_req_d1 (jbi_sctag1_req_d1[31:0]), // Templated
.scbuf_jbi_data_d1 (scbuf1_jbi_data_d2[31:0]), // Templated
.jbi_scbuf_ecc_d1 (jbi_scbuf1_ecc_d1[6:0]), // Templated
.jbi_sctag_req_vld_d1 (jbi_sctag1_req_vld_d1), // Templated
.scbuf_jbi_ctag_vld_d1 (scbuf1_jbi_ctag_vld_d2), // Templated
.scbuf_jbi_ue_err_d1 (scbuf1_jbi_ue_err_d2), // Templated
.sctag_jbi_iq_dequeue_d1 (sctag1_jbi_iq_dequeue_d2), // Templated
.sctag_jbi_wib_dequeue_d1 (sctag1_jbi_wib_dequeue_d2), // Templated
.sctag_jbi_por_req_d1 (sctag1_jbi_por_req_d2), // Templated
.so (rsc11_rsc21_so), // Templated
// Inputs
.jbi_sctag_req (jbi_sctag1_req[31:0]), // Templated
.scbuf_jbi_data (scbuf1_jbi_data_d1_buf1[31:0]), // Templated
.jbi_scbuf_ecc (jbi_scbuf1_ecc[6:0]), // Templated
.jbi_sctag_req_vld (jbi_sctag1_req_vld), // Templated
.scbuf_jbi_ctag_vld (scbuf1_jbi_ctag_vld_d1_buf1), // Templated
.scbuf_jbi_ue_err (scbuf1_jbi_ue_err_d1_buf1), // Templated
.sctag_jbi_iq_dequeue (sctag1_jbi_iq_dequeue_d1_buf1), // Templated
.sctag_jbi_wib_dequeue (sctag1_jbi_wib_dequeue_d1_buf1), // Templated
.sctag_jbi_por_req (sctag1_jbi_por_req_d1_buf1), // Templated
.rclk (ccx_rclk), // Templated
.si (rsc01_rsc11_so), // Templated
.se (global_shift_enable)); // Templated
//
/* ff_jbi_sc2_1 AUTO_TEMPLATE (
.rclk (ccx_rclk),
.se (global_shift_enable),
.si (rsc11_rsc21_so),
.so (rsc21_rsc31_so),
.scbuf_jbi_\(.*\)_d1 (scbuf@_jbi_\1_d2[]),
.scbuf_jbi_\(.*\) (scbuf@_jbi_\1_d1_buf1[]),
.sctag_jbi_\(.*\)_d1 (sctag@_jbi_\1_d2[]),
.sctag_jbi_\(.*\) (sctag@_jbi_\1_d1_buf1[]),
.jbi_sctag_\(.*\)_d1 (jbi_sctag@_\1_d1[]),
.jbi_sctag_\(.*\) (jbi_sctag@_\1[]),
.jbi_scbuf_\(.*\)_d1 (jbi_scbuf@_\1_d1[]),
.jbi_scbuf_\(.*\) (jbi_scbuf@_\1[]),
);*/
//
ff_jbi_sc2_1 ff_jbi_sc2_1
(/*AUTOINST*/
// Outputs
.jbi_sctag_req_d1 (jbi_sctag2_req_d1[31:0]), // Templated
.scbuf_jbi_data_d1 (scbuf2_jbi_data_d2[31:0]), // Templated
.jbi_scbuf_ecc_d1 (jbi_scbuf2_ecc_d1[6:0]), // Templated
.jbi_sctag_req_vld_d1 (jbi_sctag2_req_vld_d1), // Templated
.scbuf_jbi_ctag_vld_d1 (scbuf2_jbi_ctag_vld_d2), // Templated
.scbuf_jbi_ue_err_d1 (scbuf2_jbi_ue_err_d2), // Templated
.sctag_jbi_iq_dequeue_d1 (sctag2_jbi_iq_dequeue_d2), // Templated
.sctag_jbi_wib_dequeue_d1 (sctag2_jbi_wib_dequeue_d2), // Templated
.sctag_jbi_por_req_d1 (sctag2_jbi_por_req_d2), // Templated
.so (rsc21_rsc31_so), // Templated
// Inputs
.jbi_sctag_req (jbi_sctag2_req[31:0]), // Templated
.scbuf_jbi_data (scbuf2_jbi_data_d1_buf1[31:0]), // Templated
.jbi_scbuf_ecc (jbi_scbuf2_ecc[6:0]), // Templated
.jbi_sctag_req_vld (jbi_sctag2_req_vld), // Templated
.scbuf_jbi_ctag_vld (scbuf2_jbi_ctag_vld_d1_buf1), // Templated
.scbuf_jbi_ue_err (scbuf2_jbi_ue_err_d1_buf1), // Templated
.sctag_jbi_iq_dequeue (sctag2_jbi_iq_dequeue_d1_buf1), // Templated
.sctag_jbi_wib_dequeue (sctag2_jbi_wib_dequeue_d1_buf1), // Templated
.sctag_jbi_por_req (sctag2_jbi_por_req_d1_buf1), // Templated
.rclk (ccx_rclk), // Templated
.si (rsc11_rsc21_so), // Templated
.se (global_shift_enable)); // Templated
//
/* ff_jbi_sc3_1 AUTO_TEMPLATE (
.rclk (ccx_rclk),
.se (global_shift_enable),
.si (rsc21_rsc31_so),
.so (rsc21_rsc32_so),
.scbuf_jbi_\(.*\)_d1 (scbuf@_jbi_\1_d2[]),
.scbuf_jbi_\(.*\) (scbuf@_jbi_\1_d1_buf1[]),
.sctag_jbi_\(.*\)_d1 (sctag@_jbi_\1_d2[]),
.sctag_jbi_\(.*\) (sctag@_jbi_\1_d1_buf1[]),
.jbi_sctag_\(.*\)_d1 (jbi_sctag@_\1_d1[]),
.jbi_sctag_\(.*\) (jbi_sctag@_\1[]),
.jbi_scbuf_\(.*\)_d1 (jbi_scbuf@_\1_d1[]),
.jbi_scbuf_\(.*\) (jbi_scbuf@_\1[]),
);*/
//
ff_jbi_sc3_1 ff_jbi_sc3_1
(/*AUTOINST*/
// Outputs
.jbi_sctag_req_d1 (jbi_sctag3_req_d1[31:0]), // Templated
.scbuf_jbi_data_d1 (scbuf3_jbi_data_d2[31:0]), // Templated
.jbi_scbuf_ecc_d1 (jbi_scbuf3_ecc_d1[6:0]), // Templated
.jbi_sctag_req_vld_d1 (jbi_sctag3_req_vld_d1), // Templated
.scbuf_jbi_ctag_vld_d1 (scbuf3_jbi_ctag_vld_d2), // Templated
.scbuf_jbi_ue_err_d1 (scbuf3_jbi_ue_err_d2), // Templated
.sctag_jbi_iq_dequeue_d1 (sctag3_jbi_iq_dequeue_d2), // Templated
.sctag_jbi_wib_dequeue_d1 (sctag3_jbi_wib_dequeue_d2), // Templated
.sctag_jbi_por_req_d1 (sctag3_jbi_por_req_d2), // Templated
.so (rsc21_rsc32_so), // Templated
// Inputs
.jbi_sctag_req (jbi_sctag3_req[31:0]), // Templated
.scbuf_jbi_data (scbuf3_jbi_data_d1_buf1[31:0]), // Templated
.jbi_scbuf_ecc (jbi_scbuf3_ecc[6:0]), // Templated
.jbi_sctag_req_vld (jbi_sctag3_req_vld), // Templated
.scbuf_jbi_ctag_vld (scbuf3_jbi_ctag_vld_d1_buf1), // Templated
.scbuf_jbi_ue_err (scbuf3_jbi_ue_err_d1_buf1), // Templated
.sctag_jbi_iq_dequeue (sctag3_jbi_iq_dequeue_d1_buf1), // Templated
.sctag_jbi_wib_dequeue (sctag3_jbi_wib_dequeue_d1_buf1), // Templated
.sctag_jbi_por_req (sctag3_jbi_por_req_d1_buf1), // Templated
.rclk (ccx_rclk), // Templated
.si (rsc21_rsc31_so), // Templated
.se (global_shift_enable)); // Templated
//
/* jbi_l2_buf2 AUTO_TEMPLATE (
.scbuf_jbi_\(.*\)_buf (scbuf@_jbi_\1_d1_buf1[]),
.scbuf_jbi_\(.*\) (scbuf@_jbi_\1_d1[]),
.sctag_jbi_\(.*\)_buf (sctag@_jbi_\1_d1_buf1[]),
.sctag_jbi_\(.*\) (sctag@_jbi_\1_d1[]),
.jbi_scbuf\(.*\)_buf (jbi_scbuf@\1_d1_buf1[]),
.jbi_scbuf_\(.*\) (jbi_scbuf@_\1_d1[]),
.jbi_sctag_\(.*\)_buf (jbi_sctag@_\1_d1_buf1[]),
.jbi_sctag_\(.*\) (jbi_sctag@_\1_d1[]),
);*/
//
jbi_l2_buf2 rep_jbi_sc0_1
(/*AUTOINST*/
// Outputs
.jbi_sctag_req_buf (jbi_sctag0_req_d1_buf1[31:0]), // Templated
.scbuf_jbi_data_buf (scbuf0_jbi_data_d1_buf1[31:0]), // Templated
.jbi_scbuf_ecc_buf (jbi_scbuf0_ecc_d1_buf1[6:0]), // Templated
.jbi_sctag_req_vld_buf (jbi_sctag0_req_vld_d1_buf1), // Templated
.scbuf_jbi_ctag_vld_buf (scbuf0_jbi_ctag_vld_d1_buf1), // Templated
.scbuf_jbi_ue_err_buf (scbuf0_jbi_ue_err_d1_buf1), // Templated
.sctag_jbi_iq_dequeue_buf (sctag0_jbi_iq_dequeue_d1_buf1), // Templated
.sctag_jbi_wib_dequeue_buf (sctag0_jbi_wib_dequeue_d1_buf1), // Templated
.sctag_jbi_por_req_buf (sctag0_jbi_por_req_d1_buf1), // Templated
// Inputs
.jbi_sctag_req (jbi_sctag0_req_d1[31:0]), // Templated
.scbuf_jbi_data (scbuf0_jbi_data_d1[31:0]), // Templated
.jbi_scbuf_ecc (jbi_scbuf0_ecc_d1[6:0]), // Templated
.jbi_sctag_req_vld (jbi_sctag0_req_vld_d1), // Templated
.scbuf_jbi_ctag_vld (scbuf0_jbi_ctag_vld_d1), // Templated
.scbuf_jbi_ue_err (scbuf0_jbi_ue_err_d1), // Templated
.sctag_jbi_iq_dequeue (sctag0_jbi_iq_dequeue_d1), // Templated
.sctag_jbi_wib_dequeue (sctag0_jbi_wib_dequeue_d1), // Templated
.sctag_jbi_por_req (sctag0_jbi_por_req_d1)); // Templated
//
jbi_l2_buf2 rep_jbi_sc1_1
(/*AUTOINST*/
// Outputs
.jbi_sctag_req_buf (jbi_sctag1_req_d1_buf1[31:0]), // Templated
.scbuf_jbi_data_buf (scbuf1_jbi_data_d1_buf1[31:0]), // Templated
.jbi_scbuf_ecc_buf (jbi_scbuf1_ecc_d1_buf1[6:0]), // Templated
.jbi_sctag_req_vld_buf (jbi_sctag1_req_vld_d1_buf1), // Templated
.scbuf_jbi_ctag_vld_buf (scbuf1_jbi_ctag_vld_d1_buf1), // Templated
.scbuf_jbi_ue_err_buf (scbuf1_jbi_ue_err_d1_buf1), // Templated
.sctag_jbi_iq_dequeue_buf (sctag1_jbi_iq_dequeue_d1_buf1), // Templated
.sctag_jbi_wib_dequeue_buf (sctag1_jbi_wib_dequeue_d1_buf1), // Templated
.sctag_jbi_por_req_buf (sctag1_jbi_por_req_d1_buf1), // Templated
// Inputs
.jbi_sctag_req (jbi_sctag1_req_d1[31:0]), // Templated
.scbuf_jbi_data (scbuf1_jbi_data_d1[31:0]), // Templated
.jbi_scbuf_ecc (jbi_scbuf1_ecc_d1[6:0]), // Templated
.jbi_sctag_req_vld (jbi_sctag1_req_vld_d1), // Templated
.scbuf_jbi_ctag_vld (scbuf1_jbi_ctag_vld_d1), // Templated
.scbuf_jbi_ue_err (scbuf1_jbi_ue_err_d1), // Templated
.sctag_jbi_iq_dequeue (sctag1_jbi_iq_dequeue_d1), // Templated
.sctag_jbi_wib_dequeue (sctag1_jbi_wib_dequeue_d1), // Templated
.sctag_jbi_por_req (sctag1_jbi_por_req_d1)); // Templated
//
jbi_l2_buf2 rep_jbi_sc2_1
(/*AUTOINST*/
// Outputs
.jbi_sctag_req_buf (jbi_sctag2_req_d1_buf1[31:0]), // Templated
.scbuf_jbi_data_buf (scbuf2_jbi_data_d1_buf1[31:0]), // Templated
.jbi_scbuf_ecc_buf (jbi_scbuf2_ecc_d1_buf1[6:0]), // Templated
.jbi_sctag_req_vld_buf (jbi_sctag2_req_vld_d1_buf1), // Templated
.scbuf_jbi_ctag_vld_buf (scbuf2_jbi_ctag_vld_d1_buf1), // Templated
.scbuf_jbi_ue_err_buf (scbuf2_jbi_ue_err_d1_buf1), // Templated
.sctag_jbi_iq_dequeue_buf (sctag2_jbi_iq_dequeue_d1_buf1), // Templated
.sctag_jbi_wib_dequeue_buf (sctag2_jbi_wib_dequeue_d1_buf1), // Templated
.sctag_jbi_por_req_buf (sctag2_jbi_por_req_d1_buf1), // Templated
// Inputs
.jbi_sctag_req (jbi_sctag2_req_d1[31:0]), // Templated
.scbuf_jbi_data (scbuf2_jbi_data_d1[31:0]), // Templated
.jbi_scbuf_ecc (jbi_scbuf2_ecc_d1[6:0]), // Templated
.jbi_sctag_req_vld (jbi_sctag2_req_vld_d1), // Templated
.scbuf_jbi_ctag_vld (scbuf2_jbi_ctag_vld_d1), // Templated
.scbuf_jbi_ue_err (scbuf2_jbi_ue_err_d1), // Templated
.sctag_jbi_iq_dequeue (sctag2_jbi_iq_dequeue_d1), // Templated
.sctag_jbi_wib_dequeue (sctag2_jbi_wib_dequeue_d1), // Templated
.sctag_jbi_por_req (sctag2_jbi_por_req_d1)); // Templated
//
jbi_l2_buf2 rep_jbi_sc3_1
(/*AUTOINST*/
// Outputs
.jbi_sctag_req_buf (jbi_sctag3_req_d1_buf1[31:0]), // Templated
.scbuf_jbi_data_buf (scbuf3_jbi_data_d1_buf1[31:0]), // Templated
.jbi_scbuf_ecc_buf (jbi_scbuf3_ecc_d1_buf1[6:0]), // Templated
.jbi_sctag_req_vld_buf (jbi_sctag3_req_vld_d1_buf1), // Templated
.scbuf_jbi_ctag_vld_buf (scbuf3_jbi_ctag_vld_d1_buf1), // Templated
.scbuf_jbi_ue_err_buf (scbuf3_jbi_ue_err_d1_buf1), // Templated
.sctag_jbi_iq_dequeue_buf (sctag3_jbi_iq_dequeue_d1_buf1), // Templated
.sctag_jbi_wib_dequeue_buf (sctag3_jbi_wib_dequeue_d1_buf1), // Templated
.sctag_jbi_por_req_buf (sctag3_jbi_por_req_d1_buf1), // Templated
// Inputs
.jbi_sctag_req (jbi_sctag3_req_d1[31:0]), // Templated
.scbuf_jbi_data (scbuf3_jbi_data_d1[31:0]), // Templated
.jbi_scbuf_ecc (jbi_scbuf3_ecc_d1[6:0]), // Templated
.jbi_sctag_req_vld (jbi_sctag3_req_vld_d1), // Templated
.scbuf_jbi_ctag_vld (scbuf3_jbi_ctag_vld_d1), // Templated
.scbuf_jbi_ue_err (scbuf3_jbi_ue_err_d1), // Templated
.sctag_jbi_iq_dequeue (sctag3_jbi_iq_dequeue_d1), // Templated
.sctag_jbi_wib_dequeue (sctag3_jbi_wib_dequeue_d1), // Templated
.sctag_jbi_por_req (sctag3_jbi_por_req_d1)); // Templated
//
/* ff_jbi_sc0_2 AUTO_TEMPLATE (
.rclk (ccx_rclk),
.se (global_shift_enable),
.si (rdbg01_rsc02_so),
.so (rsc02_rptrs_so),
.scbuf_jbi_\(.*\)_d1 (scbuf@_jbi_\1_d1[]),
.scbuf_jbi_\(.*\) (scbuf@_jbi_\1_buf1[]),
.sctag_jbi_\(.*\) (sctag@_jbi_\1[]),
.jbi_sctag_\(.*\)_d1 (jbi_sctag@_\1_d2[]),
.jbi_sctag_\(.*\) (jbi_sctag@_\1_d1_buf1[]),
.jbi_scbuf_\(.*\)_d1 (jbi_scbuf@_\1_d2[]),
.jbi_scbuf_\(.*\) (jbi_scbuf@_\1_d1_buf1[]),
);*/
//
ff_jbi_sc0_2 ff_jbi_sc0_2
(/*AUTOINST*/
// Outputs
.jbi_sctag_req_d1 (jbi_sctag0_req_d2[31:0]), // Templated
.scbuf_jbi_data_d1 (scbuf0_jbi_data_d1[31:0]), // Templated
.jbi_scbuf_ecc_d1 (jbi_scbuf0_ecc_d2[6:0]), // Templated
.jbi_sctag_req_vld_d1 (jbi_sctag0_req_vld_d2), // Templated
.scbuf_jbi_ctag_vld_d1 (scbuf0_jbi_ctag_vld_d1), // Templated
.scbuf_jbi_ue_err_d1 (scbuf0_jbi_ue_err_d1), // Templated
.sctag_jbi_iq_dequeue_d1 (sctag0_jbi_iq_dequeue_d1), // Templated
.sctag_jbi_wib_dequeue_d1 (sctag0_jbi_wib_dequeue_d1), // Templated
.sctag_jbi_por_req_d1 (sctag0_jbi_por_req_d1), // Templated
.so (rsc02_rptrs_so), // Templated
// Inputs
.jbi_sctag_req (jbi_sctag0_req_d1_buf1[31:0]), // Templated
.scbuf_jbi_data (scbuf0_jbi_data_buf1[31:0]), // Templated
.jbi_scbuf_ecc (jbi_scbuf0_ecc_d1_buf1[6:0]), // Templated
.jbi_sctag_req_vld (jbi_sctag0_req_vld_d1_buf1), // Templated
.scbuf_jbi_ctag_vld (scbuf0_jbi_ctag_vld_buf1), // Templated
.scbuf_jbi_ue_err (scbuf0_jbi_ue_err_buf1), // Templated
.sctag_jbi_iq_dequeue (sctag0_jbi_iq_dequeue), // Templated
.sctag_jbi_wib_dequeue (sctag0_jbi_wib_dequeue), // Templated
.sctag_jbi_por_req (sctag0_jbi_por_req), // Templated
.rclk (ccx_rclk), // Templated
.si (rdbg01_rsc02_so), // Templated
.se (global_shift_enable)); // Templated
//
/* ff_jbi_sc1_2 AUTO_TEMPLATE (
.rclk (ccx_rclk),
.se (global_shift_enable),
.si (rptrs_rsc12_so),
.so (rsc12_rsc01_so),
.scbuf_jbi_\(.*\)_d1 (scbuf@_jbi_\1_d1[]),
.scbuf_jbi_\(.*\) (scbuf@_jbi_\1_buf1[]),
.sctag_jbi_\(.*\) (sctag@_jbi_\1[]),
.jbi_sctag_\(.*\)_d1 (jbi_sctag@_\1_d2[]),
.jbi_sctag_\(.*\) (jbi_sctag@_\1_d1_buf1[]),
.jbi_scbuf_\(.*\)_d1 (jbi_scbuf@_\1_d2[]),
.jbi_scbuf_\(.*\) (jbi_scbuf@_\1_d1_buf1[]),
);*/
//
ff_jbi_sc1_2 ff_jbi_sc1_2
(/*AUTOINST*/
// Outputs
.jbi_sctag_req_d1 (jbi_sctag1_req_d2[31:0]), // Templated
.scbuf_jbi_data_d1 (scbuf1_jbi_data_d1[31:0]), // Templated
.jbi_scbuf_ecc_d1 (jbi_scbuf1_ecc_d2[6:0]), // Templated
.jbi_sctag_req_vld_d1 (jbi_sctag1_req_vld_d2), // Templated
.scbuf_jbi_ctag_vld_d1 (scbuf1_jbi_ctag_vld_d1), // Templated
.scbuf_jbi_ue_err_d1 (scbuf1_jbi_ue_err_d1), // Templated
.sctag_jbi_iq_dequeue_d1 (sctag1_jbi_iq_dequeue_d1), // Templated
.sctag_jbi_wib_dequeue_d1 (sctag1_jbi_wib_dequeue_d1), // Templated
.sctag_jbi_por_req_d1 (sctag1_jbi_por_req_d1), // Templated
.so (rsc12_rsc01_so), // Templated
// Inputs
.jbi_sctag_req (jbi_sctag1_req_d1_buf1[31:0]), // Templated
.scbuf_jbi_data (scbuf1_jbi_data_buf1[31:0]), // Templated
.jbi_scbuf_ecc (jbi_scbuf1_ecc_d1_buf1[6:0]), // Templated
.jbi_sctag_req_vld (jbi_sctag1_req_vld_d1_buf1), // Templated
.scbuf_jbi_ctag_vld (scbuf1_jbi_ctag_vld_buf1), // Templated
.scbuf_jbi_ue_err (scbuf1_jbi_ue_err_buf1), // Templated
.sctag_jbi_iq_dequeue (sctag1_jbi_iq_dequeue), // Templated
.sctag_jbi_wib_dequeue (sctag1_jbi_wib_dequeue), // Templated
.sctag_jbi_por_req (sctag1_jbi_por_req), // Templated
.rclk (ccx_rclk), // Templated
.si (rptrs_rsc12_so), // Templated
.se (global_shift_enable)); // Templated
//
/* ff_jbi_sc2_2 AUTO_TEMPLATE (
.rclk (ccx_rclk),
.se (global_shift_enable),
.si (pddr2_rsc22_so),
.so (rsc22_rdbg23_so),
.scbuf_jbi_\(.*\)_d1 (scbuf@_jbi_\1_d1[]),
.scbuf_jbi_\(.*\) (scbuf@_jbi_\1_buf1[]),
.sctag_jbi_\(.*\) (sctag@_jbi_\1[]),
.jbi_sctag_\(.*\)_d1 (jbi_sctag@_\1_d2[]),
.jbi_sctag_\(.*\) (jbi_sctag@_\1_d1_buf1[]),
.jbi_scbuf_\(.*\)_d1 (jbi_scbuf@_\1_d2[]),
.jbi_scbuf_\(.*\) (jbi_scbuf@_\1_d1_buf1[]),
);*/
//
ff_jbi_sc2_2 ff_jbi_sc2_2
(/*AUTOINST*/
// Outputs
.jbi_sctag_req_d1 (jbi_sctag2_req_d2[31:0]), // Templated
.scbuf_jbi_data_d1 (scbuf2_jbi_data_d1[31:0]), // Templated
.jbi_scbuf_ecc_d1 (jbi_scbuf2_ecc_d2[6:0]), // Templated
.jbi_sctag_req_vld_d1 (jbi_sctag2_req_vld_d2), // Templated
.scbuf_jbi_ctag_vld_d1 (scbuf2_jbi_ctag_vld_d1), // Templated
.scbuf_jbi_ue_err_d1 (scbuf2_jbi_ue_err_d1), // Templated
.sctag_jbi_iq_dequeue_d1 (sctag2_jbi_iq_dequeue_d1), // Templated
.sctag_jbi_wib_dequeue_d1 (sctag2_jbi_wib_dequeue_d1), // Templated
.sctag_jbi_por_req_d1 (sctag2_jbi_por_req_d1), // Templated
.so (rsc22_rdbg23_so), // Templated
// Inputs
.jbi_sctag_req (jbi_sctag2_req_d1_buf1[31:0]), // Templated
.scbuf_jbi_data (scbuf2_jbi_data_buf1[31:0]), // Templated
.jbi_scbuf_ecc (jbi_scbuf2_ecc_d1_buf1[6:0]), // Templated
.jbi_sctag_req_vld (jbi_sctag2_req_vld_d1_buf1), // Templated
.scbuf_jbi_ctag_vld (scbuf2_jbi_ctag_vld_buf1), // Templated
.scbuf_jbi_ue_err (scbuf2_jbi_ue_err_buf1), // Templated
.sctag_jbi_iq_dequeue (sctag2_jbi_iq_dequeue), // Templated
.sctag_jbi_wib_dequeue (sctag2_jbi_wib_dequeue), // Templated
.sctag_jbi_por_req (sctag2_jbi_por_req), // Templated
.rclk (ccx_rclk), // Templated
.si (pddr2_rsc22_so), // Templated
.se (global_shift_enable)); // Templated
//
/* ff_jbi_sc3_2 AUTO_TEMPLATE (
.rclk (ccx_rclk),
.se (global_shift_enable),
.si (rsc21_rsc32_so),
.so (rsc32_efc_so),
.scbuf_jbi_\(.*\)_d1 (scbuf@_jbi_\1_d1[]),
.scbuf_jbi_\(.*\) (scbuf@_jbi_\1_buf1[]),
.sctag_jbi_\(.*\) (sctag@_jbi_\1[]),
.jbi_sctag_\(.*\)_d1 (jbi_sctag@_\1_d2[]),
.jbi_sctag_\(.*\) (jbi_sctag@_\1_d1_buf1[]),
.jbi_scbuf_\(.*\)_d1 (jbi_scbuf@_\1_d2[]),
.jbi_scbuf_\(.*\) (jbi_scbuf@_\1_d1_buf1[]),
);*/
//
ff_jbi_sc3_2 ff_jbi_sc3_2
(/*AUTOINST*/
// Outputs
.jbi_sctag_req_d1 (jbi_sctag3_req_d2[31:0]), // Templated
.scbuf_jbi_data_d1 (scbuf3_jbi_data_d1[31:0]), // Templated
.jbi_scbuf_ecc_d1 (jbi_scbuf3_ecc_d2[6:0]), // Templated
.jbi_sctag_req_vld_d1 (jbi_sctag3_req_vld_d2), // Templated
.scbuf_jbi_ctag_vld_d1 (scbuf3_jbi_ctag_vld_d1), // Templated
.scbuf_jbi_ue_err_d1 (scbuf3_jbi_ue_err_d1), // Templated
.sctag_jbi_iq_dequeue_d1 (sctag3_jbi_iq_dequeue_d1), // Templated
.sctag_jbi_wib_dequeue_d1 (sctag3_jbi_wib_dequeue_d1), // Templated
.sctag_jbi_por_req_d1 (sctag3_jbi_por_req_d1), // Templated
.so (rsc32_efc_so), // Templated
// Inputs
.jbi_sctag_req (jbi_sctag3_req_d1_buf1[31:0]), // Templated
.scbuf_jbi_data (scbuf3_jbi_data_buf1[31:0]), // Templated
.jbi_scbuf_ecc (jbi_scbuf3_ecc_d1_buf1[6:0]), // Templated
.jbi_sctag_req_vld (jbi_sctag3_req_vld_d1_buf1), // Templated
.scbuf_jbi_ctag_vld (scbuf3_jbi_ctag_vld_buf1), // Templated
.scbuf_jbi_ue_err (scbuf3_jbi_ue_err_buf1), // Templated
.sctag_jbi_iq_dequeue (sctag3_jbi_iq_dequeue), // Templated
.sctag_jbi_wib_dequeue (sctag3_jbi_wib_dequeue), // Templated
.sctag_jbi_por_req (sctag3_jbi_por_req), // Templated
.rclk (ccx_rclk), // Templated
.si (rsc21_rsc32_so), // Templated
.se (global_shift_enable)); // Templated
//
/* rep_jbi_sc0_2 AUTO_TEMPLATE (
.jbi_scbuf_\(.*\)_buf (jbi_scbuf@_\1_d2_buf1[]),
.jbi_scbuf_\(.*\) (jbi_scbuf@_\1_d2[]),
.scbuf_jbi_\(.*\)_buf (scbuf@_jbi_\1_buf1[]),
.scbuf_jbi_\(.*\) (scbuf@_jbi_\1[]),
.jbi_sctag_req_buf (jbi_sctag@_req_d2_buf1[]),
.jbi_sctag_req (jbi_sctag@_req_d2[]),
.jbi_sctag_req_vld_buf (),
.jbi_sctag_req_vld (1'b0),
.sctag_jbi_\(.*\)_buf (),
.sctag_jbi_\(.*\) (1'b0),
);*/
//
rep_jbi_sc0_2 rep_jbi_sc0_2
(/*AUTOINST*/
// Outputs
.jbi_sctag_req_buf (jbi_sctag0_req_d2_buf1[31:0]), // Templated
.scbuf_jbi_data_buf (scbuf0_jbi_data_buf1[31:0]), // Templated
.jbi_scbuf_ecc_buf (jbi_scbuf0_ecc_d2_buf1[6:0]), // Templated
.jbi_sctag_req_vld_buf (), // Templated
.scbuf_jbi_ctag_vld_buf (scbuf0_jbi_ctag_vld_buf1), // Templated
.scbuf_jbi_ue_err_buf (scbuf0_jbi_ue_err_buf1), // Templated
.sctag_jbi_iq_dequeue_buf (), // Templated
.sctag_jbi_wib_dequeue_buf (), // Templated
.sctag_jbi_por_req_buf (), // Templated
// Inputs
.jbi_sctag_req (jbi_sctag0_req_d2[31:0]), // Templated
.scbuf_jbi_data (scbuf0_jbi_data[31:0]), // Templated
.jbi_scbuf_ecc (jbi_scbuf0_ecc_d2[6:0]), // Templated
.jbi_sctag_req_vld (1'b0), // Templated
.scbuf_jbi_ctag_vld (scbuf0_jbi_ctag_vld), // Templated
.scbuf_jbi_ue_err (scbuf0_jbi_ue_err), // Templated
.sctag_jbi_iq_dequeue (1'b0), // Templated
.sctag_jbi_wib_dequeue (1'b0), // Templated
.sctag_jbi_por_req (1'b0)); // Templated
//
/* rep_jbi_sc1_2 AUTO_TEMPLATE (
.jbi_scbuf_\(.*\)_buf (jbi_scbuf@_\1_d2_buf1[]),
.jbi_scbuf_\(.*\) (jbi_scbuf@_\1_d2[]),
.scbuf_jbi_\(.*\)_buf (scbuf@_jbi_\1_buf1[]),
.scbuf_jbi_\(.*\) (scbuf@_jbi_\1[]),
.jbi_sctag_req_buf (jbi_sctag@_req_d2_buf1[]),
.jbi_sctag_req (jbi_sctag@_req_d2[]),
.jbi_sctag_req_vld_buf (),
.jbi_sctag_req_vld (1'b0),
.sctag_jbi_\(.*\)_buf (),
.sctag_jbi_\(.*\) (1'b0),
);*/
//
rep_jbi_sc1_2 rep_jbi_sc1_2
(/*AUTOINST*/
// Outputs
.jbi_sctag_req_buf (jbi_sctag1_req_d2_buf1[31:0]), // Templated
.scbuf_jbi_data_buf (scbuf1_jbi_data_buf1[31:0]), // Templated
.jbi_scbuf_ecc_buf (jbi_scbuf1_ecc_d2_buf1[6:0]), // Templated
.jbi_sctag_req_vld_buf (), // Templated
.scbuf_jbi_ctag_vld_buf (scbuf1_jbi_ctag_vld_buf1), // Templated
.scbuf_jbi_ue_err_buf (scbuf1_jbi_ue_err_buf1), // Templated
.sctag_jbi_iq_dequeue_buf (), // Templated
.sctag_jbi_wib_dequeue_buf (), // Templated
.sctag_jbi_por_req_buf (), // Templated
// Inputs
.jbi_sctag_req (jbi_sctag1_req_d2[31:0]), // Templated
.scbuf_jbi_data (scbuf1_jbi_data[31:0]), // Templated
.jbi_scbuf_ecc (jbi_scbuf1_ecc_d2[6:0]), // Templated
.jbi_sctag_req_vld (1'b0), // Templated
.scbuf_jbi_ctag_vld (scbuf1_jbi_ctag_vld), // Templated
.scbuf_jbi_ue_err (scbuf1_jbi_ue_err), // Templated
.sctag_jbi_iq_dequeue (1'b0), // Templated
.sctag_jbi_wib_dequeue (1'b0), // Templated
.sctag_jbi_por_req (1'b0)); // Templated
//
/* rep_jbi_sc2_2 AUTO_TEMPLATE (
.jbi_scbuf_\(.*\)_buf (jbi_scbuf@_\1_d2_buf1[]),
.jbi_scbuf_\(.*\) (jbi_scbuf@_\1_d2[]),
.scbuf_jbi_\(.*\)_buf (scbuf@_jbi_\1_buf1[]),
.scbuf_jbi_\(.*\) (scbuf@_jbi_\1[]),
.jbi_sctag_req_buf (jbi_sctag@_req_d2_buf1[]),
.jbi_sctag_req (jbi_sctag@_req_d2[]),
.jbi_sctag_req_vld_buf (),
.jbi_sctag_req_vld (1'b0),
.sctag_jbi_\(.*\)_buf (),
.sctag_jbi_\(.*\) (1'b0),
);*/
//
rep_jbi_sc2_2 rep_jbi_sc2_2
(/*AUTOINST*/
// Outputs
.jbi_sctag_req_buf (jbi_sctag2_req_d2_buf1[31:0]), // Templated
.scbuf_jbi_data_buf (scbuf2_jbi_data_buf1[31:0]), // Templated
.jbi_scbuf_ecc_buf (jbi_scbuf2_ecc_d2_buf1[6:0]), // Templated
.jbi_sctag_req_vld_buf (), // Templated
.scbuf_jbi_ctag_vld_buf (scbuf2_jbi_ctag_vld_buf1), // Templated
.scbuf_jbi_ue_err_buf (scbuf2_jbi_ue_err_buf1), // Templated
.sctag_jbi_iq_dequeue_buf (), // Templated
.sctag_jbi_wib_dequeue_buf (), // Templated
.sctag_jbi_por_req_buf (), // Templated
// Inputs
.jbi_sctag_req (jbi_sctag2_req_d2[31:0]), // Templated
.scbuf_jbi_data (scbuf2_jbi_data[31:0]), // Templated
.jbi_scbuf_ecc (jbi_scbuf2_ecc_d2[6:0]), // Templated
.jbi_sctag_req_vld (1'b0), // Templated
.scbuf_jbi_ctag_vld (scbuf2_jbi_ctag_vld), // Templated
.scbuf_jbi_ue_err (scbuf2_jbi_ue_err), // Templated
.sctag_jbi_iq_dequeue (1'b0), // Templated
.sctag_jbi_wib_dequeue (1'b0), // Templated
.sctag_jbi_por_req (1'b0)); // Templated
//
/* rep_jbi_sc3_2 AUTO_TEMPLATE (
.jbi_scbuf_\(.*\)_buf (jbi_scbuf@_\1_d2_buf1[]),
.jbi_scbuf_\(.*\) (jbi_scbuf@_\1_d2[]),
.scbuf_jbi_\(.*\)_buf (scbuf@_jbi_\1_buf1[]),
.scbuf_jbi_\(.*\) (scbuf@_jbi_\1[]),
.jbi_sctag_req_buf (jbi_sctag@_req_d2_buf1[]),
.jbi_sctag_req (jbi_sctag@_req_d2[]),
.jbi_sctag_req_vld_buf (),
.jbi_sctag_req_vld (1'b0),
.sctag_jbi_\(.*\)_buf (),
.sctag_jbi_\(.*\) (1'b0),
);*/
//
rep_jbi_sc3_2 rep_jbi_sc3_2
(/*AUTOINST*/
// Outputs
.jbi_sctag_req_buf (jbi_sctag3_req_d2_buf1[31:0]), // Templated
.scbuf_jbi_data_buf (scbuf3_jbi_data_buf1[31:0]), // Templated
.jbi_scbuf_ecc_buf (jbi_scbuf3_ecc_d2_buf1[6:0]), // Templated
.jbi_sctag_req_vld_buf (), // Templated
.scbuf_jbi_ctag_vld_buf (scbuf3_jbi_ctag_vld_buf1), // Templated
.scbuf_jbi_ue_err_buf (scbuf3_jbi_ue_err_buf1), // Templated
.sctag_jbi_iq_dequeue_buf (), // Templated
.sctag_jbi_wib_dequeue_buf (), // Templated
.sctag_jbi_por_req_buf (), // Templated
// Inputs
.jbi_sctag_req (jbi_sctag3_req_d2[31:0]), // Templated
.scbuf_jbi_data (scbuf3_jbi_data[31:0]), // Templated
.jbi_scbuf_ecc (jbi_scbuf3_ecc_d2[6:0]), // Templated
.jbi_sctag_req_vld (1'b0), // Templated
.scbuf_jbi_ctag_vld (scbuf3_jbi_ctag_vld), // Templated
.scbuf_jbi_ue_err (scbuf3_jbi_ue_err), // Templated
.sctag_jbi_iq_dequeue (1'b0), // Templated
.sctag_jbi_wib_dequeue (1'b0), // Templated
.sctag_jbi_por_req (1'b0)); // Templated
//
/* sc_0_1_dbg_rptr AUTO_TEMPLATE (
.rclk (ccx_rclk),
.se (global_shift_enable),
.si (rdbg23_rdbg01_so),
.so (rdbg01_rsc02_so),
.dbgbus_b\([01]\) (sctag@"(+ @ \1)"_dbgbus_out[]),
.enable_01 (dbg_en_@@"(+ @ 1)"),
.l2_dbgbus_out (l2_dbgbus_@@"(+ @ 1)"[]),
); */
//
sc_0_1_dbg_rptr sc_0_1_dbg_rptr
(/*AUTOINST*/
// Outputs
.l2_dbgbus_out (l2_dbgbus_01[39:0]), // Templated
.enable_01 (dbg_en_01), // Templated
.so (rdbg01_rsc02_so), // Templated
// Inputs
.dbgbus_b0 (sctag0_dbgbus_out[40:0]), // Templated
.dbgbus_b1 (sctag1_dbgbus_out[40:0]), // Templated
.rclk (ccx_rclk), // Templated
.si (rdbg23_rdbg01_so), // Templated
.se (global_shift_enable)); // Templated
//
/* sc_2_3_dbg_rptr AUTO_TEMPLATE (
.rclk (ccx_rclk),
.se (global_shift_enable),
.si (rsc22_rdbg23_so),
.so (rdbg23_rdbg01_so),
.dbgbus_b\([01]\) (sctag@"(+ @ \1)"_dbgbus_out[]),
.enable_01 (dbg_en_@@"(+ @ 1)"),
.l2_dbgbus_out (l2_dbgbus_@@"(+ @ 1)"[]),
); */
//
sc_2_3_dbg_rptr sc_2_3_dbg_rptr
(/*AUTOINST*/
// Outputs
.l2_dbgbus_out (l2_dbgbus_23[39:0]), // Templated
.enable_01 (dbg_en_23), // Templated
.so (rdbg23_rdbg01_so), // Templated
// Inputs
.dbgbus_b0 (sctag2_dbgbus_out[40:0]), // Templated
.dbgbus_b1 (sctag3_dbgbus_out[40:0]), // Templated
.rclk (ccx_rclk), // Templated
.si (rsc22_rdbg23_so), // Templated
.se (global_shift_enable)); // Templated
//
/* spc_pcx_buf AUTO_TEMPLATE (
.spc_pcx_data_pa (spc@_pcx_data_pa_buf[]),
.spc_pcx_atom_pq (spc@_pcx_atom_pq_buf),
.spc_pcx_req_pq (spc@_pcx_req_pq_buf[]),
.pcx_spc_grant_px_buf (pcx_spc@_grant_px_buf1[]),
.spc_pcx_data_pa_buf (spc@_pcx_data_pa[]),
.spc_pcx_atom_pq_buf (spc@_pcx_atom_pq),
.spc_pcx_req_pq_buf (spc@_pcx_req_pq[]),
.pcx_spc_grant_px (pcx_spc@_grant_px_buf[]),
); */
//
spc_pcx_buf buf_pcx_0
(/*AUTOINST*/
// Outputs
.spc_pcx_data_pa (spc0_pcx_data_pa_buf[`PCX_WIDTH-1:0]), // Templated
.spc_pcx_atom_pq (spc0_pcx_atom_pq_buf), // Templated
.spc_pcx_req_pq (spc0_pcx_req_pq_buf[4:0]), // Templated
.pcx_spc_grant_px_buf (pcx_spc0_grant_px_buf1[4:0]), // Templated
// Inputs
.spc_pcx_data_pa_buf (spc0_pcx_data_pa[`PCX_WIDTH-1:0]), // Templated
.spc_pcx_atom_pq_buf (spc0_pcx_atom_pq), // Templated
.spc_pcx_req_pq_buf (spc0_pcx_req_pq[4:0]), // Templated
.pcx_spc_grant_px (pcx_spc0_grant_px_buf[4:0])); // Templated
//
spc_pcx_buf buf_pcx_1
(/*AUTOINST*/
// Outputs
.spc_pcx_data_pa (spc1_pcx_data_pa_buf[`PCX_WIDTH-1:0]), // Templated
.spc_pcx_atom_pq (spc1_pcx_atom_pq_buf), // Templated
.spc_pcx_req_pq (spc1_pcx_req_pq_buf[4:0]), // Templated
.pcx_spc_grant_px_buf (pcx_spc1_grant_px_buf1[4:0]), // Templated
// Inputs
.spc_pcx_data_pa_buf (spc1_pcx_data_pa[`PCX_WIDTH-1:0]), // Templated
.spc_pcx_atom_pq_buf (spc1_pcx_atom_pq), // Templated
.spc_pcx_req_pq_buf (spc1_pcx_req_pq[4:0]), // Templated
.pcx_spc_grant_px (pcx_spc1_grant_px_buf[4:0])); // Templated
//
spc_pcx_buf buf_pcx_2
(/*AUTOINST*/
// Outputs
.spc_pcx_data_pa (spc2_pcx_data_pa_buf[`PCX_WIDTH-1:0]), // Templated
.spc_pcx_atom_pq (spc2_pcx_atom_pq_buf), // Templated
.spc_pcx_req_pq (spc2_pcx_req_pq_buf[4:0]), // Templated
.pcx_spc_grant_px_buf (pcx_spc2_grant_px_buf1[4:0]), // Templated
// Inputs
.spc_pcx_data_pa_buf (spc2_pcx_data_pa[`PCX_WIDTH-1:0]), // Templated
.spc_pcx_atom_pq_buf (spc2_pcx_atom_pq), // Templated
.spc_pcx_req_pq_buf (spc2_pcx_req_pq[4:0]), // Templated
.pcx_spc_grant_px (pcx_spc2_grant_px_buf[4:0])); // Templated
//
spc_pcx_buf buf_pcx_3
(/*AUTOINST*/
// Outputs
.spc_pcx_data_pa (spc3_pcx_data_pa_buf[`PCX_WIDTH-1:0]), // Templated
.spc_pcx_atom_pq (spc3_pcx_atom_pq_buf), // Templated
.spc_pcx_req_pq (spc3_pcx_req_pq_buf[4:0]), // Templated
.pcx_spc_grant_px_buf (pcx_spc3_grant_px_buf1[4:0]), // Templated
// Inputs
.spc_pcx_data_pa_buf (spc3_pcx_data_pa[`PCX_WIDTH-1:0]), // Templated
.spc_pcx_atom_pq_buf (spc3_pcx_atom_pq), // Templated
.spc_pcx_req_pq_buf (spc3_pcx_req_pq[4:0]), // Templated
.pcx_spc_grant_px (pcx_spc3_grant_px_buf[4:0])); // Templated
//
spc_pcx_buf buf_pcx_4
(/*AUTOINST*/
// Outputs
.spc_pcx_data_pa (spc4_pcx_data_pa_buf[`PCX_WIDTH-1:0]), // Templated
.spc_pcx_atom_pq (spc4_pcx_atom_pq_buf), // Templated
.spc_pcx_req_pq (spc4_pcx_req_pq_buf[4:0]), // Templated
.pcx_spc_grant_px_buf (pcx_spc4_grant_px_buf1[4:0]), // Templated
// Inputs
.spc_pcx_data_pa_buf (spc4_pcx_data_pa[`PCX_WIDTH-1:0]), // Templated
.spc_pcx_atom_pq_buf (spc4_pcx_atom_pq), // Templated
.spc_pcx_req_pq_buf (spc4_pcx_req_pq[4:0]), // Templated
.pcx_spc_grant_px (pcx_spc4_grant_px_buf[4:0])); // Templated
//
spc_pcx_buf buf_pcx_5
(/*AUTOINST*/
// Outputs
.spc_pcx_data_pa (spc5_pcx_data_pa_buf[`PCX_WIDTH-1:0]), // Templated
.spc_pcx_atom_pq (spc5_pcx_atom_pq_buf), // Templated
.spc_pcx_req_pq (spc5_pcx_req_pq_buf[4:0]), // Templated
.pcx_spc_grant_px_buf (pcx_spc5_grant_px_buf1[4:0]), // Templated
// Inputs
.spc_pcx_data_pa_buf (spc5_pcx_data_pa[`PCX_WIDTH-1:0]), // Templated
.spc_pcx_atom_pq_buf (spc5_pcx_atom_pq), // Templated
.spc_pcx_req_pq_buf (spc5_pcx_req_pq[4:0]), // Templated
.pcx_spc_grant_px (pcx_spc5_grant_px_buf[4:0])); // Templated
//
spc_pcx_buf buf_pcx_6
(/*AUTOINST*/
// Outputs
.spc_pcx_data_pa (spc6_pcx_data_pa_buf[`PCX_WIDTH-1:0]), // Templated
.spc_pcx_atom_pq (spc6_pcx_atom_pq_buf), // Templated
.spc_pcx_req_pq (spc6_pcx_req_pq_buf[4:0]), // Templated
.pcx_spc_grant_px_buf (pcx_spc6_grant_px_buf1[4:0]), // Templated
// Inputs
.spc_pcx_data_pa_buf (spc6_pcx_data_pa[`PCX_WIDTH-1:0]), // Templated
.spc_pcx_atom_pq_buf (spc6_pcx_atom_pq), // Templated
.spc_pcx_req_pq_buf (spc6_pcx_req_pq[4:0]), // Templated
.pcx_spc_grant_px (pcx_spc6_grant_px_buf[4:0])); // Templated
//
spc_pcx_buf buf_pcx_7
(/*AUTOINST*/
// Outputs
.spc_pcx_data_pa (spc7_pcx_data_pa_buf[`PCX_WIDTH-1:0]), // Templated
.spc_pcx_atom_pq (spc7_pcx_atom_pq_buf), // Templated
.spc_pcx_req_pq (spc7_pcx_req_pq_buf[4:0]), // Templated
.pcx_spc_grant_px_buf (pcx_spc7_grant_px_buf1[4:0]), // Templated
// Inputs
.spc_pcx_data_pa_buf (spc7_pcx_data_pa[`PCX_WIDTH-1:0]), // Templated
.spc_pcx_atom_pq_buf (spc7_pcx_atom_pq), // Templated
.spc_pcx_req_pq_buf (spc7_pcx_req_pq[4:0]), // Templated
.pcx_spc_grant_px (pcx_spc7_grant_px_buf[4:0])); // Templated
//
/* ccx_spc_rpt AUTO_TEMPLATE (
// Outputs
.spc_pcx_req_pq_buf (spc@_pcx_req_pq_buf1[4:0]),
.spc_pcx_atom_pq_buf (spc@_pcx_atom_pq_buf1),
.spc_pcx_data_pa_buf (spc@_pcx_data_pa_buf1[`PCX_WIDTH-1:0]),
.pcx_spc_grant_px_buf (pcx_spc@_grant_px_buf[4:0]),
.cpx_spc_data_cx2_buf (cpx_spc@_data_cx2_buf1[`CPX_WIDTH-1:0]),
.cpx_spc_data_rdy_cx2_buf (cpx_spc@_data_rdy_cx2_buf1),
// Inputs
.spc_pcx_req_pq (spc@_pcx_req_pq_buf[4:0]),
.spc_pcx_atom_pq (spc@_pcx_atom_pq_buf),
.spc_pcx_data_pa (spc@_pcx_data_pa_buf[`PCX_WIDTH-1:0]),
.pcx_spc_grant_px (pcx_spc@_grant_px[4:0]),
.cpx_spc_data_cx2 (cpx_spc@_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc_data_rdy_cx2 (cpx_spc@_data_rdy_cx2),
); */
//
ccx_spc_rpt ccx_spc_rpt0
(/*AUTOINST*/
// Outputs
.spc_pcx_req_pq_buf (spc0_pcx_req_pq_buf1[4:0]), // Templated
.spc_pcx_atom_pq_buf (spc0_pcx_atom_pq_buf1), // Templated
.spc_pcx_data_pa_buf (spc0_pcx_data_pa_buf1[`PCX_WIDTH-1:0]), // Templated
.pcx_spc_grant_px_buf (pcx_spc0_grant_px_buf[4:0]), // Templated
.cpx_spc_data_cx2_buf (cpx_spc0_data_cx2_buf1[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2_buf (cpx_spc0_data_rdy_cx2_buf1), // Templated
// Inputs
.spc_pcx_req_pq (spc0_pcx_req_pq_buf[4:0]), // Templated
.spc_pcx_atom_pq (spc0_pcx_atom_pq_buf), // Templated
.spc_pcx_data_pa (spc0_pcx_data_pa_buf[`PCX_WIDTH-1:0]), // Templated
.pcx_spc_grant_px (pcx_spc0_grant_px[4:0]), // Templated
.cpx_spc_data_cx2 (cpx_spc0_data_cx2[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2 (cpx_spc0_data_rdy_cx2)); // Templated
//
ccx_spc_rpt ccx_spc_rpt1
(/*AUTOINST*/
// Outputs
.spc_pcx_req_pq_buf (spc1_pcx_req_pq_buf1[4:0]), // Templated
.spc_pcx_atom_pq_buf (spc1_pcx_atom_pq_buf1), // Templated
.spc_pcx_data_pa_buf (spc1_pcx_data_pa_buf1[`PCX_WIDTH-1:0]), // Templated
.pcx_spc_grant_px_buf (pcx_spc1_grant_px_buf[4:0]), // Templated
.cpx_spc_data_cx2_buf (cpx_spc1_data_cx2_buf1[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2_buf (cpx_spc1_data_rdy_cx2_buf1), // Templated
// Inputs
.spc_pcx_req_pq (spc1_pcx_req_pq_buf[4:0]), // Templated
.spc_pcx_atom_pq (spc1_pcx_atom_pq_buf), // Templated
.spc_pcx_data_pa (spc1_pcx_data_pa_buf[`PCX_WIDTH-1:0]), // Templated
.pcx_spc_grant_px (pcx_spc1_grant_px[4:0]), // Templated
.cpx_spc_data_cx2 (cpx_spc1_data_cx2[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2 (cpx_spc1_data_rdy_cx2)); // Templated
//
ccx_spc_rpt ccx_spc_rpt2
(/*AUTOINST*/
// Outputs
.spc_pcx_req_pq_buf (spc2_pcx_req_pq_buf1[4:0]), // Templated
.spc_pcx_atom_pq_buf (spc2_pcx_atom_pq_buf1), // Templated
.spc_pcx_data_pa_buf (spc2_pcx_data_pa_buf1[`PCX_WIDTH-1:0]), // Templated
.pcx_spc_grant_px_buf (pcx_spc2_grant_px_buf[4:0]), // Templated
.cpx_spc_data_cx2_buf (cpx_spc2_data_cx2_buf1[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2_buf (cpx_spc2_data_rdy_cx2_buf1), // Templated
// Inputs
.spc_pcx_req_pq (spc2_pcx_req_pq_buf[4:0]), // Templated
.spc_pcx_atom_pq (spc2_pcx_atom_pq_buf), // Templated
.spc_pcx_data_pa (spc2_pcx_data_pa_buf[`PCX_WIDTH-1:0]), // Templated
.pcx_spc_grant_px (pcx_spc2_grant_px[4:0]), // Templated
.cpx_spc_data_cx2 (cpx_spc2_data_cx2[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2 (cpx_spc2_data_rdy_cx2)); // Templated
//
ccx_spc_rpt ccx_spc_rpt3
(/*AUTOINST*/
// Outputs
.spc_pcx_req_pq_buf (spc3_pcx_req_pq_buf1[4:0]), // Templated
.spc_pcx_atom_pq_buf (spc3_pcx_atom_pq_buf1), // Templated
.spc_pcx_data_pa_buf (spc3_pcx_data_pa_buf1[`PCX_WIDTH-1:0]), // Templated
.pcx_spc_grant_px_buf (pcx_spc3_grant_px_buf[4:0]), // Templated
.cpx_spc_data_cx2_buf (cpx_spc3_data_cx2_buf1[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2_buf (cpx_spc3_data_rdy_cx2_buf1), // Templated
// Inputs
.spc_pcx_req_pq (spc3_pcx_req_pq_buf[4:0]), // Templated
.spc_pcx_atom_pq (spc3_pcx_atom_pq_buf), // Templated
.spc_pcx_data_pa (spc3_pcx_data_pa_buf[`PCX_WIDTH-1:0]), // Templated
.pcx_spc_grant_px (pcx_spc3_grant_px[4:0]), // Templated
.cpx_spc_data_cx2 (cpx_spc3_data_cx2[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2 (cpx_spc3_data_rdy_cx2)); // Templated
//
ccx_spc_rpt ccx_spc_rpt4
(/*AUTOINST*/
// Outputs
.spc_pcx_req_pq_buf (spc4_pcx_req_pq_buf1[4:0]), // Templated
.spc_pcx_atom_pq_buf (spc4_pcx_atom_pq_buf1), // Templated
.spc_pcx_data_pa_buf (spc4_pcx_data_pa_buf1[`PCX_WIDTH-1:0]), // Templated
.pcx_spc_grant_px_buf (pcx_spc4_grant_px_buf[4:0]), // Templated
.cpx_spc_data_cx2_buf (cpx_spc4_data_cx2_buf1[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2_buf (cpx_spc4_data_rdy_cx2_buf1), // Templated
// Inputs
.spc_pcx_req_pq (spc4_pcx_req_pq_buf[4:0]), // Templated
.spc_pcx_atom_pq (spc4_pcx_atom_pq_buf), // Templated
.spc_pcx_data_pa (spc4_pcx_data_pa_buf[`PCX_WIDTH-1:0]), // Templated
.pcx_spc_grant_px (pcx_spc4_grant_px[4:0]), // Templated
.cpx_spc_data_cx2 (cpx_spc4_data_cx2[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2 (cpx_spc4_data_rdy_cx2)); // Templated
//
ccx_spc_rpt ccx_spc_rpt5
(/*AUTOINST*/
// Outputs
.spc_pcx_req_pq_buf (spc5_pcx_req_pq_buf1[4:0]), // Templated
.spc_pcx_atom_pq_buf (spc5_pcx_atom_pq_buf1), // Templated
.spc_pcx_data_pa_buf (spc5_pcx_data_pa_buf1[`PCX_WIDTH-1:0]), // Templated
.pcx_spc_grant_px_buf (pcx_spc5_grant_px_buf[4:0]), // Templated
.cpx_spc_data_cx2_buf (cpx_spc5_data_cx2_buf1[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2_buf (cpx_spc5_data_rdy_cx2_buf1), // Templated
// Inputs
.spc_pcx_req_pq (spc5_pcx_req_pq_buf[4:0]), // Templated
.spc_pcx_atom_pq (spc5_pcx_atom_pq_buf), // Templated
.spc_pcx_data_pa (spc5_pcx_data_pa_buf[`PCX_WIDTH-1:0]), // Templated
.pcx_spc_grant_px (pcx_spc5_grant_px[4:0]), // Templated
.cpx_spc_data_cx2 (cpx_spc5_data_cx2[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2 (cpx_spc5_data_rdy_cx2)); // Templated
//
ccx_spc_rpt ccx_spc_rpt6
(/*AUTOINST*/
// Outputs
.spc_pcx_req_pq_buf (spc6_pcx_req_pq_buf1[4:0]), // Templated
.spc_pcx_atom_pq_buf (spc6_pcx_atom_pq_buf1), // Templated
.spc_pcx_data_pa_buf (spc6_pcx_data_pa_buf1[`PCX_WIDTH-1:0]), // Templated
.pcx_spc_grant_px_buf (pcx_spc6_grant_px_buf[4:0]), // Templated
.cpx_spc_data_cx2_buf (cpx_spc6_data_cx2_buf1[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2_buf (cpx_spc6_data_rdy_cx2_buf1), // Templated
// Inputs
.spc_pcx_req_pq (spc6_pcx_req_pq_buf[4:0]), // Templated
.spc_pcx_atom_pq (spc6_pcx_atom_pq_buf), // Templated
.spc_pcx_data_pa (spc6_pcx_data_pa_buf[`PCX_WIDTH-1:0]), // Templated
.pcx_spc_grant_px (pcx_spc6_grant_px[4:0]), // Templated
.cpx_spc_data_cx2 (cpx_spc6_data_cx2[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2 (cpx_spc6_data_rdy_cx2)); // Templated
//
ccx_spc_rpt ccx_spc_rpt7
(/*AUTOINST*/
// Outputs
.spc_pcx_req_pq_buf (spc7_pcx_req_pq_buf1[4:0]), // Templated
.spc_pcx_atom_pq_buf (spc7_pcx_atom_pq_buf1), // Templated
.spc_pcx_data_pa_buf (spc7_pcx_data_pa_buf1[`PCX_WIDTH-1:0]), // Templated
.pcx_spc_grant_px_buf (pcx_spc7_grant_px_buf[4:0]), // Templated
.cpx_spc_data_cx2_buf (cpx_spc7_data_cx2_buf1[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2_buf (cpx_spc7_data_rdy_cx2_buf1), // Templated
// Inputs
.spc_pcx_req_pq (spc7_pcx_req_pq_buf[4:0]), // Templated
.spc_pcx_atom_pq (spc7_pcx_atom_pq_buf), // Templated
.spc_pcx_data_pa (spc7_pcx_data_pa_buf[`PCX_WIDTH-1:0]), // Templated
.pcx_spc_grant_px (pcx_spc7_grant_px[4:0]), // Templated
.cpx_spc_data_cx2 (cpx_spc7_data_cx2[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2 (cpx_spc7_data_rdy_cx2)); // Templated
//
dram0_ddr0_rptr dram0_ddr0_rptr0 (
// Outputs
.io_dram_data_valid_buf (io_dram0_data_valid_buf0),
.io_dram_ecc_in_buf (io_dram0_ecc_in_buf0[31:0]),
.io_dram_data_in_buf (io_dram0_data_in_buf0[255:0]),
.dram_io_cas_l_buf (dram0_io_cas_l_buf0),
.dram_io_channel_disabled_buf (dram0_io_channel_disabled_buf0),
.dram_io_cke_buf (dram0_io_cke_buf0),
.dram_io_clk_enable_buf (dram0_io_clk_enable_buf0),
.dram_io_drive_data_buf (dram0_io_drive_data_buf0),
.dram_io_drive_enable_buf (dram0_io_drive_enable_buf0),
.dram_io_pad_clk_inv_buf (dram0_io_pad_clk_inv_buf0),
.dram_io_pad_enable_buf (dram0_io_pad_enable_buf0),
.dram_io_ras_l_buf (dram0_io_ras_l_buf0),
.dram_io_write_en_l_buf (dram0_io_write_en_l_buf0),
.dram_io_addr_buf (dram0_io_addr_buf0[14:0]),
.dram_io_bank_buf (dram0_io_bank_buf0[2:0]),
.dram_io_cs_l_buf (dram0_io_cs_l_buf0[3:0]),
.dram_io_data_out_buf (dram0_io_data_out_buf0[287:0]),
.dram_io_ptr_clk_inv_buf (dram0_io_ptr_clk_inv_buf0[4:0]),
// Inputs
.io_dram_data_valid (io_dram0_data_valid_buf1),
.io_dram_ecc_in (io_dram0_ecc_in_buf1[31:0]),
.io_dram_data_in (io_dram0_data_in_buf1[255:0]),
.dram_io_cas_l (dram0_io_cas_l),
.dram_io_channel_disabled (dram0_io_channel_disabled),
.dram_io_cke (dram0_io_cke),
.dram_io_clk_enable (dram0_io_clk_enable),
.dram_io_drive_data (dram0_io_drive_data),
.dram_io_drive_enable (dram0_io_drive_enable),
.dram_io_pad_clk_inv (dram0_io_pad_clk_inv),
.dram_io_pad_enable (dram0_io_pad_enable),
.dram_io_ras_l (dram0_io_ras_l),
.dram_io_write_en_l (dram0_io_write_en_l),
.dram_io_addr (dram0_io_addr[14:0]),
.dram_io_bank (dram0_io_bank[2:0]),
.dram_io_cs_l (dram0_io_cs_l[3:0]),
.dram_io_data_out (dram0_io_data_out[287:0]),
.dram_io_ptr_clk_inv (dram0_io_ptr_clk_inv[4:0]));
//
dram_ddr_rptr dram0_ddr0_rptr1 (
// Outputs
.io_dram_data_valid_buf (io_dram0_data_valid_buf1),
.io_dram_ecc_in_buf (io_dram0_ecc_in_buf1[31:0]),
.io_dram_data_in_buf (io_dram0_data_in_buf1[255:0]),
.dram_io_cas_l_buf (dram0_io_cas_l_buf1),
.dram_io_channel_disabled_buf (dram0_io_channel_disabled_buf1),
.dram_io_cke_buf (dram0_io_cke_buf1),
.dram_io_clk_enable_buf (dram0_io_clk_enable_buf1),
.dram_io_drive_data_buf (dram0_io_drive_data_buf1),
.dram_io_drive_enable_buf (dram0_io_drive_enable_buf1),
.dram_io_pad_clk_inv_buf (dram0_io_pad_clk_inv_buf1),
.dram_io_pad_enable_buf (dram0_io_pad_enable_buf1),
.dram_io_ras_l_buf (dram0_io_ras_l_buf1),
.dram_io_write_en_l_buf (dram0_io_write_en_l_buf1),
.dram_io_addr_buf (dram0_io_addr_buf1[14:0]),
.dram_io_bank_buf (dram0_io_bank_buf1[2:0]),
.dram_io_cs_l_buf (dram0_io_cs_l_buf1[3:0]),
.dram_io_data_out_buf (dram0_io_data_out_buf1[287:0]),
.dram_io_ptr_clk_inv_buf (dram0_io_ptr_clk_inv_buf1[4:0]),
// Inputs
.io_dram_data_valid (io_dram0_data_valid_buf2),
.io_dram_ecc_in (io_dram0_ecc_in_buf2[31:0]),
.io_dram_data_in (io_dram0_data_in_buf2[255:0]),
.dram_io_cas_l (dram0_io_cas_l_buf0),
.dram_io_channel_disabled (dram0_io_channel_disabled_buf0),
.dram_io_cke (dram0_io_cke_buf0),
.dram_io_clk_enable (dram0_io_clk_enable_buf0),
.dram_io_drive_data (dram0_io_drive_data_buf0),
.dram_io_drive_enable (dram0_io_drive_enable_buf0),
.dram_io_pad_clk_inv (dram0_io_pad_clk_inv_buf0),
.dram_io_pad_enable (dram0_io_pad_enable_buf0),
.dram_io_ras_l (dram0_io_ras_l_buf0),
.dram_io_write_en_l (dram0_io_write_en_l_buf0),
.dram_io_addr (dram0_io_addr_buf0[14:0]),
.dram_io_bank (dram0_io_bank_buf0[2:0]),
.dram_io_cs_l (dram0_io_cs_l_buf0[3:0]),
.dram_io_data_out (dram0_io_data_out_buf0[287:0]),
.dram_io_ptr_clk_inv (dram0_io_ptr_clk_inv_buf0[4:0]));
//
dram_ddr_pad_rptr dram0_ddr0_rptr2 (
// Outputs
.io_dram_data_valid_buf (io_dram0_data_valid_buf2),
.io_dram_ecc_in_buf (io_dram0_ecc_in_buf2[31:0]),
.io_dram_data_in_buf (io_dram0_data_in_buf2[255:0]),
.dram_io_cas_l_buf (dram0_io_cas_l_buf2),
.dram_io_channel_disabled_buf (dram0_io_channel_disabled_buf2),
.dram_io_cke_buf (dram0_io_cke_buf2),
.dram_io_clk_enable_buf (dram0_io_clk_enable_buf2),
.dram_io_drive_data_buf (dram0_io_drive_data_buf2),
.dram_io_drive_enable_buf (dram0_io_drive_enable_buf2),
.dram_io_pad_clk_inv_buf (dram0_io_pad_clk_inv_buf2),
.dram_io_pad_enable_buf (dram0_io_pad_enable_buf2),
.dram_io_ras_l_buf (dram0_io_ras_l_buf2),
.dram_io_write_en_l_buf (dram0_io_write_en_l_buf2),
.dram_io_addr_buf (dram0_io_addr_buf2[14:0]),
.dram_io_bank_buf (dram0_io_bank_buf2[2:0]),
.dram_io_cs_l_buf (dram0_io_cs_l_buf2[3:0]),
.dram_io_data_out_buf (dram0_io_data_out_buf2[287:0]),
.dram_io_ptr_clk_inv_buf (dram0_io_ptr_clk_inv_buf2[4:0]),
// Inputs
.io_dram_data_valid (io_dram0_data_valid),
.io_dram_ecc_in (io_dram0_ecc_in[31:0]),
.io_dram_data_in (io_dram0_data_in[255:0]),
.dram_io_cas_l (dram0_io_cas_l_buf1),
.dram_io_channel_disabled (dram0_io_channel_disabled_buf1),
.dram_io_cke (dram0_io_cke_buf1),
.dram_io_clk_enable (dram0_io_clk_enable_buf1),
.dram_io_drive_data (dram0_io_drive_data_buf1),
.dram_io_drive_enable (dram0_io_drive_enable_buf1),
.dram_io_pad_clk_inv (dram0_io_pad_clk_inv_buf1),
.dram_io_pad_enable (dram0_io_pad_enable_buf1),
.dram_io_ras_l (dram0_io_ras_l_buf1),
.dram_io_write_en_l (dram0_io_write_en_l_buf1),
.dram_io_addr (dram0_io_addr_buf1[14:0]),
.dram_io_bank (dram0_io_bank_buf1[2:0]),
.dram_io_cs_l (dram0_io_cs_l_buf1[3:0]),
.dram_io_data_out (dram0_io_data_out_buf1[287:0]),
.dram_io_ptr_clk_inv (dram0_io_ptr_clk_inv_buf1[4:0]));
//
dram1_ddr1_rptr dram1_ddr1_rptr0 (
// Outputs
.io_dram_data_valid_buf (io_dram1_data_valid_buf0),
.io_dram_ecc_in_buf (io_dram1_ecc_in_buf0[31:0]),
.io_dram_data_in_buf (io_dram1_data_in_buf0[255:0]),
.dram_io_cas_l_buf (dram1_io_cas_l_buf0),
.dram_io_channel_disabled_buf (dram1_io_channel_disabled_buf0),
.dram_io_cke_buf (dram1_io_cke_buf0),
.dram_io_clk_enable_buf (dram1_io_clk_enable_buf0),
.dram_io_drive_data_buf (dram1_io_drive_data_buf0),
.dram_io_drive_enable_buf (dram1_io_drive_enable_buf0),
.dram_io_pad_clk_inv_buf (dram1_io_pad_clk_inv_buf0),
.dram_io_pad_enable_buf (dram1_io_pad_enable_buf0),
.dram_io_ras_l_buf (dram1_io_ras_l_buf0),
.dram_io_write_en_l_buf (dram1_io_write_en_l_buf0),
.dram_io_addr_buf (dram1_io_addr_buf0[14:0]),
.dram_io_bank_buf (dram1_io_bank_buf0[2:0]),
.dram_io_cs_l_buf (dram1_io_cs_l_buf0[3:0]),
.dram_io_data_out_buf (dram1_io_data_out_buf0[287:0]),
.dram_io_ptr_clk_inv_buf (dram1_io_ptr_clk_inv_buf0[4:0]),
// Inputs
.io_dram_data_valid (io_dram1_data_valid_buf1),
.io_dram_ecc_in (io_dram1_ecc_in_buf1[31:0]),
.io_dram_data_in (io_dram1_data_in_buf1[255:0]),
.dram_io_cas_l (dram1_io_cas_l),
.dram_io_channel_disabled (dram1_io_channel_disabled),
.dram_io_cke (dram1_io_cke),
.dram_io_clk_enable (dram1_io_clk_enable),
.dram_io_drive_data (dram1_io_drive_data),
.dram_io_drive_enable (dram1_io_drive_enable),
.dram_io_pad_clk_inv (dram1_io_pad_clk_inv),
.dram_io_pad_enable (dram1_io_pad_enable),
.dram_io_ras_l (dram1_io_ras_l),
.dram_io_write_en_l (dram1_io_write_en_l),
.dram_io_addr (dram1_io_addr[14:0]),
.dram_io_bank (dram1_io_bank[2:0]),
.dram_io_cs_l (dram1_io_cs_l[3:0]),
.dram_io_data_out (dram1_io_data_out[287:0]),
.dram_io_ptr_clk_inv (dram1_io_ptr_clk_inv[4:0]));
//
dram_ddr_rptr_south dram1_ddr1_rptr1 (
// Outputs
.io_dram_data_valid_buf (io_dram1_data_valid_buf1),
.io_dram_ecc_in_buf (io_dram1_ecc_in_buf1[31:0]),
.io_dram_data_in_buf (io_dram1_data_in_buf1[255:0]),
.dram_io_cas_l_buf (dram1_io_cas_l_buf1),
.dram_io_channel_disabled_buf (dram1_io_channel_disabled_buf1),
.dram_io_cke_buf (dram1_io_cke_buf1),
.dram_io_clk_enable_buf (dram1_io_clk_enable_buf1),
.dram_io_drive_data_buf (dram1_io_drive_data_buf1),
.dram_io_drive_enable_buf (dram1_io_drive_enable_buf1),
.dram_io_pad_clk_inv_buf (dram1_io_pad_clk_inv_buf1),
.dram_io_pad_enable_buf (dram1_io_pad_enable_buf1),
.dram_io_ras_l_buf (dram1_io_ras_l_buf1),
.dram_io_write_en_l_buf (dram1_io_write_en_l_buf1),
.dram_io_addr_buf (dram1_io_addr_buf1[14:0]),
.dram_io_bank_buf (dram1_io_bank_buf1[2:0]),
.dram_io_cs_l_buf (dram1_io_cs_l_buf1[3:0]),
.dram_io_data_out_buf (dram1_io_data_out_buf1[287:0]),
.dram_io_ptr_clk_inv_buf (dram1_io_ptr_clk_inv_buf1[4:0]),
// Inputs
.io_dram_data_valid (io_dram1_data_valid_buf2),
.io_dram_ecc_in (io_dram1_ecc_in_buf2[31:0]),
.io_dram_data_in (io_dram1_data_in_buf2[255:0]),
.dram_io_cas_l (dram1_io_cas_l_buf0),
.dram_io_channel_disabled (dram1_io_channel_disabled_buf0),
.dram_io_cke (dram1_io_cke_buf0),
.dram_io_clk_enable (dram1_io_clk_enable_buf0),
.dram_io_drive_data (dram1_io_drive_data_buf0),
.dram_io_drive_enable (dram1_io_drive_enable_buf0),
.dram_io_pad_clk_inv (dram1_io_pad_clk_inv_buf0),
.dram_io_pad_enable (dram1_io_pad_enable_buf0),
.dram_io_ras_l (dram1_io_ras_l_buf0),
.dram_io_write_en_l (dram1_io_write_en_l_buf0),
.dram_io_addr (dram1_io_addr_buf0[14:0]),
.dram_io_bank (dram1_io_bank_buf0[2:0]),
.dram_io_cs_l (dram1_io_cs_l_buf0[3:0]),
.dram_io_data_out (dram1_io_data_out_buf0[287:0]),
.dram_io_ptr_clk_inv (dram1_io_ptr_clk_inv_buf0[4:0]));
//
dram_ddr_pad_rptr_south dram1_ddr1_rptr2 (
// Outputs
.io_dram_data_valid_buf (io_dram1_data_valid_buf2),
.io_dram_ecc_in_buf (io_dram1_ecc_in_buf2[31:0]),
.io_dram_data_in_buf (io_dram1_data_in_buf2[255:0]),
.dram_io_cas_l_buf (dram1_io_cas_l_buf2),
.dram_io_channel_disabled_buf (dram1_io_channel_disabled_buf2),
.dram_io_cke_buf (dram1_io_cke_buf2),
.dram_io_clk_enable_buf (dram1_io_clk_enable_buf2),
.dram_io_drive_data_buf (dram1_io_drive_data_buf2),
.dram_io_drive_enable_buf (dram1_io_drive_enable_buf2),
.dram_io_pad_clk_inv_buf (dram1_io_pad_clk_inv_buf2),
.dram_io_pad_enable_buf (dram1_io_pad_enable_buf2),
.dram_io_ras_l_buf (dram1_io_ras_l_buf2),
.dram_io_write_en_l_buf (dram1_io_write_en_l_buf2),
.dram_io_addr_buf (dram1_io_addr_buf2[14:0]),
.dram_io_bank_buf (dram1_io_bank_buf2[2:0]),
.dram_io_cs_l_buf (dram1_io_cs_l_buf2[3:0]),
.dram_io_data_out_buf (dram1_io_data_out_buf2[287:0]),
.dram_io_ptr_clk_inv_buf (dram1_io_ptr_clk_inv_buf2[4:0]),
// Inputs
.io_dram_data_valid (io_dram1_data_valid),
.io_dram_ecc_in (io_dram1_ecc_in[31:0]),
.io_dram_data_in (io_dram1_data_in[255:0]),
.dram_io_cas_l (dram1_io_cas_l_buf1),
.dram_io_channel_disabled (dram1_io_channel_disabled_buf1),
.dram_io_cke (dram1_io_cke_buf1),
.dram_io_clk_enable (dram1_io_clk_enable_buf1),
.dram_io_drive_data (dram1_io_drive_data_buf1),
.dram_io_drive_enable (dram1_io_drive_enable_buf1),
.dram_io_pad_clk_inv (dram1_io_pad_clk_inv_buf1),
.dram_io_pad_enable (dram1_io_pad_enable_buf1),
.dram_io_ras_l (dram1_io_ras_l_buf1),
.dram_io_write_en_l (dram1_io_write_en_l_buf1),
.dram_io_addr (dram1_io_addr_buf1[14:0]),
.dram_io_bank (dram1_io_bank_buf1[2:0]),
.dram_io_cs_l (dram1_io_cs_l_buf1[3:0]),
.dram_io_data_out (dram1_io_data_out_buf1[287:0]),
.dram_io_ptr_clk_inv (dram1_io_ptr_clk_inv_buf1[4:0]));
//
dram2_ddr2_rptr dram2_ddr2_rptr0 (
// Outputs
.io_dram_data_valid_buf (io_dram2_data_valid_buf0),
.io_dram_ecc_in_buf (io_dram2_ecc_in_buf0[31:0]),
.io_dram_data_in_buf (io_dram2_data_in_buf0[255:0]),
.dram_io_cas_l_buf (dram2_io_cas_l_buf0),
.dram_io_channel_disabled_buf (dram2_io_channel_disabled_buf0),
.dram_io_cke_buf (dram2_io_cke_buf0),
.dram_io_clk_enable_buf (dram2_io_clk_enable_buf0),
.dram_io_drive_data_buf (dram2_io_drive_data_buf0),
.dram_io_drive_enable_buf (dram2_io_drive_enable_buf0),
.dram_io_pad_clk_inv_buf (dram2_io_pad_clk_inv_buf0),
.dram_io_pad_enable_buf (dram2_io_pad_enable_buf0),
.dram_io_ras_l_buf (dram2_io_ras_l_buf0),
.dram_io_write_en_l_buf (dram2_io_write_en_l_buf0),
.dram_io_addr_buf (dram2_io_addr_buf0[14:0]),
.dram_io_bank_buf (dram2_io_bank_buf0[2:0]),
.dram_io_cs_l_buf (dram2_io_cs_l_buf0[3:0]),
.dram_io_data_out_buf (dram2_io_data_out_buf0[287:0]),
.dram_io_ptr_clk_inv_buf (dram2_io_ptr_clk_inv_buf0[4:0]),
// Inputs
.io_dram_data_valid (io_dram2_data_valid_buf1),
.io_dram_ecc_in (io_dram2_ecc_in_buf1[31:0]),
.io_dram_data_in (io_dram2_data_in_buf1[255:0]),
.dram_io_cas_l (dram2_io_cas_l),
.dram_io_channel_disabled (dram2_io_channel_disabled),
.dram_io_cke (dram2_io_cke),
.dram_io_clk_enable (dram2_io_clk_enable),
.dram_io_drive_data (dram2_io_drive_data),
.dram_io_drive_enable (dram2_io_drive_enable),
.dram_io_pad_clk_inv (dram2_io_pad_clk_inv),
.dram_io_pad_enable (dram2_io_pad_enable),
.dram_io_ras_l (dram2_io_ras_l),
.dram_io_write_en_l (dram2_io_write_en_l),
.dram_io_addr (dram2_io_addr[14:0]),
.dram_io_bank (dram2_io_bank[2:0]),
.dram_io_cs_l (dram2_io_cs_l[3:0]),
.dram_io_data_out (dram2_io_data_out[287:0]),
.dram_io_ptr_clk_inv (dram2_io_ptr_clk_inv[4:0]));
//
dram_ddr_rptr dram2_ddr2_rptr1 (
// Outputs
.io_dram_data_valid_buf (io_dram2_data_valid_buf1),
.io_dram_ecc_in_buf (io_dram2_ecc_in_buf1[31:0]),
.io_dram_data_in_buf (io_dram2_data_in_buf1[255:0]),
.dram_io_cas_l_buf (dram2_io_cas_l_buf1),
.dram_io_channel_disabled_buf (dram2_io_channel_disabled_buf1),
.dram_io_cke_buf (dram2_io_cke_buf1),
.dram_io_clk_enable_buf (dram2_io_clk_enable_buf1),
.dram_io_drive_data_buf (dram2_io_drive_data_buf1),
.dram_io_drive_enable_buf (dram2_io_drive_enable_buf1),
.dram_io_pad_clk_inv_buf (dram2_io_pad_clk_inv_buf1),
.dram_io_pad_enable_buf (dram2_io_pad_enable_buf1),
.dram_io_ras_l_buf (dram2_io_ras_l_buf1),
.dram_io_write_en_l_buf (dram2_io_write_en_l_buf1),
.dram_io_addr_buf (dram2_io_addr_buf1[14:0]),
.dram_io_bank_buf (dram2_io_bank_buf1[2:0]),
.dram_io_cs_l_buf (dram2_io_cs_l_buf1[3:0]),
.dram_io_data_out_buf (dram2_io_data_out_buf1[287:0]),
.dram_io_ptr_clk_inv_buf (dram2_io_ptr_clk_inv_buf1[4:0]),
// Inputs
.io_dram_data_valid (io_dram2_data_valid_buf2),
.io_dram_ecc_in (io_dram2_ecc_in_buf2[31:0]),
.io_dram_data_in (io_dram2_data_in_buf2[255:0]),
.dram_io_cas_l (dram2_io_cas_l_buf0),
.dram_io_channel_disabled (dram2_io_channel_disabled_buf0),
.dram_io_cke (dram2_io_cke_buf0),
.dram_io_clk_enable (dram2_io_clk_enable_buf0),
.dram_io_drive_data (dram2_io_drive_data_buf0),
.dram_io_drive_enable (dram2_io_drive_enable_buf0),
.dram_io_pad_clk_inv (dram2_io_pad_clk_inv_buf0),
.dram_io_pad_enable (dram2_io_pad_enable_buf0),
.dram_io_ras_l (dram2_io_ras_l_buf0),
.dram_io_write_en_l (dram2_io_write_en_l_buf0),
.dram_io_addr (dram2_io_addr_buf0[14:0]),
.dram_io_bank (dram2_io_bank_buf0[2:0]),
.dram_io_cs_l (dram2_io_cs_l_buf0[3:0]),
.dram_io_data_out (dram2_io_data_out_buf0[287:0]),
.dram_io_ptr_clk_inv (dram2_io_ptr_clk_inv_buf0[4:0]));
//
dram_ddr_pad_rptr dram2_ddr2_rptr2 (
// Outputs
.io_dram_data_valid_buf (io_dram2_data_valid_buf2),
.io_dram_ecc_in_buf (io_dram2_ecc_in_buf2[31:0]),
.io_dram_data_in_buf (io_dram2_data_in_buf2[255:0]),
.dram_io_cas_l_buf (dram2_io_cas_l_buf2),
.dram_io_channel_disabled_buf (dram2_io_channel_disabled_buf2),
.dram_io_cke_buf (dram2_io_cke_buf2),
.dram_io_clk_enable_buf (dram2_io_clk_enable_buf2),
.dram_io_drive_data_buf (dram2_io_drive_data_buf2),
.dram_io_drive_enable_buf (dram2_io_drive_enable_buf2),
.dram_io_pad_clk_inv_buf (dram2_io_pad_clk_inv_buf2),
.dram_io_pad_enable_buf (dram2_io_pad_enable_buf2),
.dram_io_ras_l_buf (dram2_io_ras_l_buf2),
.dram_io_write_en_l_buf (dram2_io_write_en_l_buf2),
.dram_io_addr_buf (dram2_io_addr_buf2[14:0]),
.dram_io_bank_buf (dram2_io_bank_buf2[2:0]),
.dram_io_cs_l_buf (dram2_io_cs_l_buf2[3:0]),
.dram_io_data_out_buf (dram2_io_data_out_buf2[287:0]),
.dram_io_ptr_clk_inv_buf (dram2_io_ptr_clk_inv_buf2[4:0]),
// Inputs
.io_dram_data_valid (io_dram2_data_valid),
.io_dram_ecc_in (io_dram2_ecc_in[31:0]),
.io_dram_data_in (io_dram2_data_in[255:0]),
.dram_io_cas_l (dram2_io_cas_l_buf1),
.dram_io_channel_disabled (dram2_io_channel_disabled_buf1),
.dram_io_cke (dram2_io_cke_buf1),
.dram_io_clk_enable (dram2_io_clk_enable_buf1),
.dram_io_drive_data (dram2_io_drive_data_buf1),
.dram_io_drive_enable (dram2_io_drive_enable_buf1),
.dram_io_pad_clk_inv (dram2_io_pad_clk_inv_buf1),
.dram_io_pad_enable (dram2_io_pad_enable_buf1),
.dram_io_ras_l (dram2_io_ras_l_buf1),
.dram_io_write_en_l (dram2_io_write_en_l_buf1),
.dram_io_addr (dram2_io_addr_buf1[14:0]),
.dram_io_bank (dram2_io_bank_buf1[2:0]),
.dram_io_cs_l (dram2_io_cs_l_buf1[3:0]),
.dram_io_data_out (dram2_io_data_out_buf1[287:0]),
.dram_io_ptr_clk_inv (dram2_io_ptr_clk_inv_buf1[4:0]));
//
dram3_ddr3_rptr dram3_ddr3_rptr0 (
// Outputs
.io_dram_data_valid_buf (io_dram3_data_valid_buf0),
.io_dram_ecc_in_buf (io_dram3_ecc_in_buf0[31:0]),
.io_dram_data_in_buf (io_dram3_data_in_buf0[255:0]),
.dram_io_cas_l_buf (dram3_io_cas_l_buf0),
.dram_io_channel_disabled_buf (dram3_io_channel_disabled_buf0),
.dram_io_cke_buf (dram3_io_cke_buf0),
.dram_io_clk_enable_buf (dram3_io_clk_enable_buf0),
.dram_io_drive_data_buf (dram3_io_drive_data_buf0),
.dram_io_drive_enable_buf (dram3_io_drive_enable_buf0),
.dram_io_pad_clk_inv_buf (dram3_io_pad_clk_inv_buf0),
.dram_io_pad_enable_buf (dram3_io_pad_enable_buf0),
.dram_io_ras_l_buf (dram3_io_ras_l_buf0),
.dram_io_write_en_l_buf (dram3_io_write_en_l_buf0),
.dram_io_addr_buf (dram3_io_addr_buf0[14:0]),
.dram_io_bank_buf (dram3_io_bank_buf0[2:0]),
.dram_io_cs_l_buf (dram3_io_cs_l_buf0[3:0]),
.dram_io_data_out_buf (dram3_io_data_out_buf0[287:0]),
.dram_io_ptr_clk_inv_buf (dram3_io_ptr_clk_inv_buf0[4:0]),
// Inputs
.io_dram_data_valid (io_dram3_data_valid_buf1),
.io_dram_ecc_in (io_dram3_ecc_in_buf1[31:0]),
.io_dram_data_in (io_dram3_data_in_buf1[255:0]),
.dram_io_cas_l (dram3_io_cas_l),
.dram_io_channel_disabled (dram3_io_channel_disabled),
.dram_io_cke (dram3_io_cke),
.dram_io_clk_enable (dram3_io_clk_enable),
.dram_io_drive_data (dram3_io_drive_data),
.dram_io_drive_enable (dram3_io_drive_enable),
.dram_io_pad_clk_inv (dram3_io_pad_clk_inv),
.dram_io_pad_enable (dram3_io_pad_enable),
.dram_io_ras_l (dram3_io_ras_l),
.dram_io_write_en_l (dram3_io_write_en_l),
.dram_io_addr (dram3_io_addr[14:0]),
.dram_io_bank (dram3_io_bank[2:0]),
.dram_io_cs_l (dram3_io_cs_l[3:0]),
.dram_io_data_out (dram3_io_data_out[287:0]),
.dram_io_ptr_clk_inv (dram3_io_ptr_clk_inv[4:0]));
//
dram_ddr_rptr_south dram3_ddr3_rptr1 (
// Outputs
.io_dram_data_valid_buf (io_dram3_data_valid_buf1),
.io_dram_ecc_in_buf (io_dram3_ecc_in_buf1[31:0]),
.io_dram_data_in_buf (io_dram3_data_in_buf1[255:0]),
.dram_io_cas_l_buf (dram3_io_cas_l_buf1),
.dram_io_channel_disabled_buf (dram3_io_channel_disabled_buf1),
.dram_io_cke_buf (dram3_io_cke_buf1),
.dram_io_clk_enable_buf (dram3_io_clk_enable_buf1),
.dram_io_drive_data_buf (dram3_io_drive_data_buf1),
.dram_io_drive_enable_buf (dram3_io_drive_enable_buf1),
.dram_io_pad_clk_inv_buf (dram3_io_pad_clk_inv_buf1),
.dram_io_pad_enable_buf (dram3_io_pad_enable_buf1),
.dram_io_ras_l_buf (dram3_io_ras_l_buf1),
.dram_io_write_en_l_buf (dram3_io_write_en_l_buf1),
.dram_io_addr_buf (dram3_io_addr_buf1[14:0]),
.dram_io_bank_buf (dram3_io_bank_buf1[2:0]),
.dram_io_cs_l_buf (dram3_io_cs_l_buf1[3:0]),
.dram_io_data_out_buf (dram3_io_data_out_buf1[287:0]),
.dram_io_ptr_clk_inv_buf (dram3_io_ptr_clk_inv_buf1[4:0]),
// Inputs
.io_dram_data_valid (io_dram3_data_valid_buf2),
.io_dram_ecc_in (io_dram3_ecc_in_buf2[31:0]),
.io_dram_data_in (io_dram3_data_in_buf2[255:0]),
.dram_io_cas_l (dram3_io_cas_l_buf0),
.dram_io_channel_disabled (dram3_io_channel_disabled_buf0),
.dram_io_cke (dram3_io_cke_buf0),
.dram_io_clk_enable (dram3_io_clk_enable_buf0),
.dram_io_drive_data (dram3_io_drive_data_buf0),
.dram_io_drive_enable (dram3_io_drive_enable_buf0),
.dram_io_pad_clk_inv (dram3_io_pad_clk_inv_buf0),
.dram_io_pad_enable (dram3_io_pad_enable_buf0),
.dram_io_ras_l (dram3_io_ras_l_buf0),
.dram_io_write_en_l (dram3_io_write_en_l_buf0),
.dram_io_addr (dram3_io_addr_buf0[14:0]),
.dram_io_bank (dram3_io_bank_buf0[2:0]),
.dram_io_cs_l (dram3_io_cs_l_buf0[3:0]),
.dram_io_data_out (dram3_io_data_out_buf0[287:0]),
.dram_io_ptr_clk_inv (dram3_io_ptr_clk_inv_buf0[4:0]));
//
dram_ddr_pad_rptr_south dram3_ddr3_rptr2 (
// Outputs
.io_dram_data_valid_buf (io_dram3_data_valid_buf2),
.io_dram_ecc_in_buf (io_dram3_ecc_in_buf2[31:0]),
.io_dram_data_in_buf (io_dram3_data_in_buf2[255:0]),
.dram_io_cas_l_buf (dram3_io_cas_l_buf2),
.dram_io_channel_disabled_buf (dram3_io_channel_disabled_buf2),
.dram_io_cke_buf (dram3_io_cke_buf2),
.dram_io_clk_enable_buf (dram3_io_clk_enable_buf2),
.dram_io_drive_data_buf (dram3_io_drive_data_buf2),
.dram_io_drive_enable_buf (dram3_io_drive_enable_buf2),
.dram_io_pad_clk_inv_buf (dram3_io_pad_clk_inv_buf2),
.dram_io_pad_enable_buf (dram3_io_pad_enable_buf2),
.dram_io_ras_l_buf (dram3_io_ras_l_buf2),
.dram_io_write_en_l_buf (dram3_io_write_en_l_buf2),
.dram_io_addr_buf (dram3_io_addr_buf2[14:0]),
.dram_io_bank_buf (dram3_io_bank_buf2[2:0]),
.dram_io_cs_l_buf (dram3_io_cs_l_buf2[3:0]),
.dram_io_data_out_buf (dram3_io_data_out_buf2[287:0]),
.dram_io_ptr_clk_inv_buf (dram3_io_ptr_clk_inv_buf2[4:0]),
// Inputs
.io_dram_data_valid (io_dram3_data_valid),
.io_dram_ecc_in (io_dram3_ecc_in[31:0]),
.io_dram_data_in (io_dram3_data_in[255:0]),
.dram_io_cas_l (dram3_io_cas_l_buf1),
.dram_io_channel_disabled (dram3_io_channel_disabled_buf1),
.dram_io_cke (dram3_io_cke_buf1),
.dram_io_clk_enable (dram3_io_clk_enable_buf1),
.dram_io_drive_data (dram3_io_drive_data_buf1),
.dram_io_drive_enable (dram3_io_drive_enable_buf1),
.dram_io_pad_clk_inv (dram3_io_pad_clk_inv_buf1),
.dram_io_pad_enable (dram3_io_pad_enable_buf1),
.dram_io_ras_l (dram3_io_ras_l_buf1),
.dram_io_write_en_l (dram3_io_write_en_l_buf1),
.dram_io_addr (dram3_io_addr_buf1[14:0]),
.dram_io_bank (dram3_io_bank_buf1[2:0]),
.dram_io_cs_l (dram3_io_cs_l_buf1[3:0]),
.dram_io_data_out (dram3_io_data_out_buf1[287:0]),
.dram_io_ptr_clk_inv (dram3_io_ptr_clk_inv_buf1[4:0]));
//
/* pcm AUTO_TEMPLATE (
.pmo_bump (PMO),
.pmi_bump (PMI),
.pmo_oe (pcm_misc_oe),
.io_pmo (pcm_io_pmo),
.io_pmi (io_pcm_pmi),
.io_burnin (pcm_io_burnin),
.io_pwron_rst_l (io_pwron_rst_l),
.pi_state_in_44 (rpt_cmp_grst_l_c1),
.pi_state_in_45 (jbus_grst_l),
.pi_state_in_46 (cmp_adbginit_l),
.pi_state_in_47 (rpt_cmp_jbus_rx_sync_c1),
.pi_state_in_48 (rpt_cmp_jbus_tx_sync_c1),
.rclk (cmp_gclk_c3_r[0]),
.reset_m3 (1'b0),
.pmo_m3 (PMO),
.pmi_m3 (1'b0),
.sel_m3 (1'b0),
.vddto (VDDTO),
.vddbo (VDDBO),
); */
//
`ifdef RTL_PAD_PCM
pcm pcm
(/*AUTOINST*/
// Outputs
.pmo_oe (pcm_misc_oe), // Templated
.io_pmo (pcm_io_pmo), // Templated
// Inouts
.pmo_bump (PMO), // Templated
.pmi_bump (PMI), // Templated
.vddto (VDDTO), // Templated
.vddbo (VDDBO), // Templated
// Inputs
.io_pmi (io_pcm_pmi), // Templated
.io_burnin (pcm_io_burnin), // Templated
.io_pll_char_in (io_pll_char_in),
.io_pwron_rst_l (io_pwron_rst_l), // Templated
.pi_state_in_44 (rpt_cmp_grst_l_c1), // Templated
.pi_state_in_45 (jbus_grst_l), // Templated
.pi_state_in_46 (cmp_adbginit_l), // Templated
.pi_state_in_47 (rpt_cmp_jbus_rx_sync_c1), // Templated
.pi_state_in_48 (rpt_cmp_jbus_tx_sync_c1), // Templated
.rclk (cmp_gclk_c3_r[0]), // Templated
.reset_m3 (1'b0), // Templated
.pmo_m3 (PMO), // Templated
.pmi_m3 (1'b0), // Templated
.sel_m3 (1'b0)); // Templated
`endif
endmodule // iop
// Local Variables:
// verilog-library-directories:("." "../cmp/rtl" "../ctu/rtl" "../iobdg/rtl" "../jbi/rtl" "../fpu/rtl" "../sparc/rtl" "../ccx/rtl" "../dram/rtl" "../scbuf/rtl" "../sctag/rtl" "../scdata/rtl" "../pads/pad_ddr0/rtl" "../pads/pad_ddr1/rtl" "../pads/pad_ddr2/rtl" "../pads/pad_ddr3/rtl" "../pads/pad_efc/rtl" "../pads/pad_fcram/rtl" "../pads/pad_jbusl/rtl" "../pads/pad_jbusr/rtl" "../pads/pad_rtbi/rtl" "../pads/pad_misc/rtl" "../pads/pad_pcm/rtl" "../efc/rtl" "../analog/bw_temp_diode/rtl" "../analog/bw_clk/rtl" "../analog/bw_ctu_pad_cluster/rtl")
// End:
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:29 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_axi_gpio_1_0_stub.v
// Design : ip_design_axi_gpio_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio2_io_i)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[4:0],gpio2_io_i[7:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [4:0]gpio_io_i;
input [7:0]gpio2_io_i;
endmodule
|
Require Import Iron.Language.SimplePCF.Preservation.
Require Export Iron.Language.SimplePCF.SubstExpExp.
Require Export Iron.Language.SimplePCF.Step.
Require Export Iron.Language.SimplePCF.Ty.
Require Export Iron.Language.SimplePCF.Exp.
(* Big Step Evaluation.
This is also called 'Natural Semantics'.
It provides a relation between the expression to be reduced
and its final value. *)
Inductive EVAL : exp -> exp -> Prop :=
(* Values are already evaluated ******)
| EvDone
: forall v2
, wnfX v2
-> EVAL v2 v2
(* Function Applications *************)
| EvLamApp
: forall x1 t11 x12 x2 v2 v3
, EVAL x1 (XLam t11 x12) -> EVAL x2 v2 -> EVAL (substX 0 v2 x12) v3
-> EVAL (XApp x1 x2) v3
(* Fixpoint recursion ****************)
| EvFix
: forall t11 x12 v3
, EVAL (substX 0 (XFix t11 x12) x12) v3
-> EVAL (XFix t11 x12) v3
(* Naturals **************************)
| EvSucc
: forall x1 n
, EVAL x1 (XNat n)
-> EVAL (XSucc x1) (XNat (S n))
| EvPredZero
: forall x1
, EVAL x1 (XNat O)
-> EVAL (XPred x1) (XNat O)
| EvPredSucc
: forall x1 n
, EVAL x1 (XNat (S n))
-> EVAL (XPred x1) (XNat n)
(* Booleans **************************)
| EvIsZeroTrue
: forall x1
, EVAL x1 (XNat O)
-> EVAL (XIsZero x1) XTrue
| EvIsZeroFalse
: forall x1 n
, EVAL x1 (XNat (S n))
-> EVAL (XIsZero x1) XFalse
(* Branching *************************)
| EvIfThen
: forall x1 x2 x3 v2
, EVAL x1 XTrue -> EVAL x2 v2
-> EVAL (XIf x1 x2 x3) v2
| EvIfElse
: forall x1 x2 x3 v3
, EVAL x1 XFalse -> EVAL x3 v3
-> EVAL (XIf x1 x2 x3) v3.
Hint Constructors EVAL.
(* A terminating big-step evaluation always produces a whnf.
The fact that the evaluation terminated is implied by the fact
that we have a finite proof of EVAL to pass to this lemma. *)
Lemma eval_produces_wnfX
: forall x1 v1
, EVAL x1 v1
-> wnfX v1.
Proof.
intros. induction H; eauto.
Qed.
Hint Resolve eval_produces_wnfX.
(********************************************************************)
(* Big to Small steps.
Convert a big-step evaluation into a list of individual
machine steps. *)
Lemma steps_of_eval
: forall x1 t1 x2
, TYPE nil x1 t1
-> EVAL x1 x2
-> STEPS x1 x2.
Proof.
intros x1 t1 v2 HT HE.
gen t1.
induction HE;
intros;
inverts keep HT; eauto;
(* This gets simple expressions with a single context *)
try ( eapply EsAppend ;
[ eapply steps_context ; [ eauto | eapply IHHE ; eauto ]
| eauto ]).
Case "EvLamApp".
lets E1: IHHE1 H2.
lets E2: IHHE2 H4.
lets T1: preservation_steps H2 E1. inverts keep T1.
lets T2: preservation_steps H4 E2.
lets T3: subst_exp_exp H1 T2.
lets E3: IHHE3 T3.
eapply EsAppend.
lets D: steps_context XcApp1. eapply D. eauto.
eapply EsAppend.
eapply steps_context; eauto.
eapply EsAppend.
eapply EsStep.
eapply EsLamApp. eauto. eauto.
Case "EvFix".
lets T1: subst_exp_exp H3 HT.
lets E1: IHHE T1.
eapply EsAppend.
eapply EsStep.
eapply EsFix. eauto.
Case "EVIfTrue".
lets S1: IHHE1 H3.
lets S2: IHHE2 H5.
eapply EsAppend.
eapply (steps_context (fun xx => XIf xx x2 x3)); eauto.
eauto.
Case "EVIfFalse".
lets S1: IHHE1 H3.
lets S2: IHHE2 H6.
eapply EsAppend.
eapply (steps_context (fun xx => XIf xx x2 x3)); eauto.
eauto.
Qed.
(********************************************************************)
(* Small to Big steps.
Convert a list of individual machine steps to a big-step
evaluation. The main part of this is the expansion lemma, which
we use to build up the overall big-step evaluation one small-step
at a time. The other lemmas are used to feed it small-steps.
*)
(* Given an existing big-step evalution, we can produce a new one
that does an extra step before returning the original value.
*)
Lemma eval_expansion
: forall te x1 t1 x2 v3
, TYPE te x1 t1
-> STEP x1 x2 -> EVAL x2 v3
-> EVAL x1 v3.
Proof.
intros te x1 t1 x2 v3 HT HS. gen te t1 v3.
induction HS; intros;
try (solve [inverts H; eauto]); eauto.
Case "Context".
destruct H.
eauto.
inverts HT; inverts H0; try (inverts H); eauto.
inverts HT; inverts H0; try (inverts H1); eauto.
inverts HT; inverts H0; try (inverts H); eauto.
inverts HT; inverts H0; try (inverts H); eauto.
inverts HT; inverts H0; try (inverts H); eauto.
inverts HT; inverts H0; try (inverts H); eauto.
Qed.
(* Convert a list of small steps to a big-step evaluation. *)
Lemma eval_of_stepsl
: forall x1 t1 v2
, TYPE nil x1 t1
-> STEPSL x1 v2 -> value v2
-> EVAL x1 v2.
Proof.
intros x1 t1 v2 HT HS HV.
induction HS; burn.
Case "ESLCons".
eapply eval_expansion;
burn using preservation.
Qed.
(* Convert a multi-step evaluation to a big-step evaluation.
We use stepsl_of_steps to flatten out the append constructors
in the multi-step evaluation, leaving a list of individual
small-steps. *)
Lemma eval_of_steps
: forall x1 t1 v2
, TYPE nil x1 t1
-> STEPS x1 v2 -> value v2
-> EVAL x1 v2.
Proof.
intros.
eapply eval_of_stepsl; burn.
apply stepsl_of_steps; burn.
Qed.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFBBN_1_V
`define SKY130_FD_SC_LS__DFBBN_1_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog wrapper for dfbbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dfbbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfbbn_1 (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfbbn_1 (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFBBN_1_V
|
/*
Partial Decoder, handles 8Exx_xxx and CExx_xxxx blocks.
This will be speculative, and the main decoder will integrate the results
of the various decoder paths, selecting the one which matches.
Results of this decoder are to be ignored if the block doesn't match.
I-Forms
XEst_OnmO
XEst_Onmo
XEii_OnmO
XEii_Onii
8Exx will be [15:0], and opcode word will be [31:16].
*/
`include "CoreDefs.v"
module DecOp4_XE(
/* verilator lint_off UNUSED */
istrWord,
idRegN,
idRegS,
idRegT,
idImm,
idUCmd
);
input[31:0] istrWord; //source instruction word
output[6:0] idRegN;
output[6:0] idRegS;
output[6:0] idRegT;
output[31:0] idImm;
output[7:0] idUCmd;
reg[6:0] opRegN;
reg[6:0] opRegS;
reg[6:0] opRegT; //Index for mem ops
reg[31:0] opImm; //Disp for mem ops
reg[7:0] opUCmd;
assign idRegN = opRegN;
assign idRegS = opRegS;
assign idRegT = opRegT;
assign idImm = opImm;
assign idUCmd = opUCmd;
reg[6:0] opRegN_Dfl;
reg[6:0] opRegM_Dfl;
reg[6:0] opRegO_Dfl;
reg[6:0] opRegS_Dfl;
reg[6:0] opRegT_Dfl;
reg[6:0] opRegN_FR;
reg[6:0] opRegM_FR;
reg[6:0] opRegS_FR;
reg[6:0] opRegT_FR;
reg[31:0] opImm8_Sx8E;
reg[31:0] opImm8_Zx8E;
reg[31:0] opImm8_Nx8E;
reg[31:0] opImm16_Sx8E;
reg[31:0] opImm20_Sx8E;
reg[31:0] opImmM12_Sx8E;
reg[31:0] opImmO12_Sx8E;
// reg[31:0] opImmO12_Zx8E;
reg[31:0] opImm4_ZxXE;
reg[15:0] opPfxWord;
reg[15:0] opCmdWord;
reg[4:0] tOpDecXfrm;
reg[2:0] tOpDecXfrmZx;
always @*
begin
opCmdWord=istrWord[31:16];
opPfxWord=istrWord[15: 0];
// opIsCE = (istrWord[15:14]==2'b11);
// opIsCE = 0;
opRegN_Dfl = {3'h0, opCmdWord[11: 8]};
opRegM_Dfl = {3'h0, opCmdWord[ 7: 4]};
opRegO_Dfl = {3'h0, opCmdWord[ 3: 0]};
opRegS_Dfl = {3'h0, opPfxWord[ 7: 4]};
opRegT_Dfl = {3'h0, opPfxWord[ 3: 0]};
opRegN_FR = {3'h4, opCmdWord[11: 8]};
opRegM_FR = {3'h4, opCmdWord[ 7: 4]};
opRegS_FR = {3'h4, opPfxWord[ 7: 4]};
opRegT_FR = {3'h4, opPfxWord[ 3: 0]};
opImm8_Sx8E = {opPfxWord[7] ? 24'hFFFFFF : 24'h0, opPfxWord[ 7:0]};
opImm8_Zx8E = {24'h000000, opPfxWord[ 7:0]};
opImm8_Nx8E = {24'hFFFFFF, opPfxWord[ 7:0]};
opImmM12_Sx8E = {opPfxWord[7] ? 20'hFFFFF : 20'h0,
opPfxWord[ 7:0], opCmdWord[ 7:4]};
opImmO12_Sx8E = {opPfxWord[7] ? 20'hFFFFF : 20'h0,
opPfxWord[ 7:0], opCmdWord[ 3:0]};
// opImmO12_Zx8E = { 20'h0, opPfxWord[ 7:0], opCmdWord[ 3:0] };
opImm16_Sx8E = {opPfxWord[7] ? 16'hFFFF : 16'h0000,
opPfxWord[ 7:0], opCmdWord[ 7:0]};
opImm20_Sx8E = {opPfxWord[7] ? 12'hFFF : 12'h000,
opPfxWord[ 7:0], opCmdWord[11:0]};
opImm4_ZxXE = {28'h000000, opPfxWord[ 3:0]};
opUCmd=UCMD_UDBRK;
opImm=0;
opRegN=UREG_ZZR;
opRegS=UREG_ZZR;
opRegT=UREG_ZZR;
tOpDecXfrm=UXFORM_INVALID;
tOpDecXfrmZx=UXFORMZX_SX;
casez(opCmdWord[15:12])
4'h0: case(opCmdWord[3:0])
4'h4: begin //0xx4
opUCmd = UCMD_MOVB_RM;
tOpDecXfrm=UXFORM_MOV_NSO;
end
4'h5: begin //0xx5
opUCmd = UCMD_MOVW_RM;
tOpDecXfrm=UXFORM_MOV_NSO;
end
4'h6: begin //0xx6
opUCmd = UCMD_MOVL_RM;
tOpDecXfrm=UXFORM_MOV_NSO;
end
4'h7: begin //0xx7
opUCmd = UCMD_MOVQ_RM;
tOpDecXfrm=UXFORM_MOV_NSO;
end
4'hC: begin //0xxC
opUCmd = UCMD_MOVB_MR;
tOpDecXfrm=UXFORM_MOV_NSO;
end
4'hD: begin //0xxD
opUCmd = UCMD_MOVW_MR;
tOpDecXfrm=UXFORM_MOV_NSO;
end
4'hE: begin //0xxE
opUCmd = UCMD_MOVL_MR;
tOpDecXfrm=UXFORM_MOV_NSO;
end
4'hF: begin //0xxF
opUCmd = UCMD_MOVQ_MR;
tOpDecXfrm=UXFORM_MOV_NSO;
end
default: begin end
endcase
4'h1: begin //1nmd, MOV.L Rm, @(Rn, disp4)
opUCmd = UCMD_MOVL_RM;
tOpDecXfrm=UXFORM_MOV_NSJ;
end
4'h2: case(opCmdWord[3:0])
4'h0: begin //2xx0, MOV.B Rm, @Rn
opUCmd = UCMD_MOVB_RM;
tOpDecXfrm=UXFORM_MOV_NS;
end
4'h1: begin //2xx1, MOV.W Rm, @Rn
opUCmd = UCMD_MOVW_RM;
tOpDecXfrm=UXFORM_MOV_NS;
end
4'h2: begin //2xx2, MOV.L Rm, @Rn
opUCmd = UCMD_MOVL_RM;
tOpDecXfrm=UXFORM_MOV_NS;
end
4'h3: begin //2xx3, MOV.Q Rm, @Rn
opUCmd = UCMD_MOVQ_RM;
end
4'h9: begin //2xx9, AND Rm, Rn
opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
4'hA: begin //2xxA, XOR Rm, Rn
opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
4'hB: begin //2xxB, OR Rm, Rn
opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
4'hE: begin //2xxE, MUL Rm, Rn
opUCmd=UCMD_ALU_MUL; tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
4'hF: begin //2xxF, MUL Rm, Rn
opUCmd=UCMD_ALU_MUL; tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_NX;
end
default: begin end
endcase
4'h3: case(opCmdWord[3:0])
4'h0: begin //3xx0, CMP/EQ Rm, Rn
opUCmd=UCMD_CMP_EQ;
tOpDecXfrm=UXFORM_CMP_ST;
end
4'h2: begin //3xx2, CMP/HS Rm, Rn
opUCmd=UCMD_CMP_HS;
tOpDecXfrm=UXFORM_CMP_ST;
end
4'h3: begin //3xx3, CMP/GE Rm, Rn
opUCmd=UCMD_CMP_GE;
tOpDecXfrm=UXFORM_CMP_ST;
end
4'h6: begin //3xx6, CMP/HI Rm, Rn
opUCmd=UCMD_CMP_HI;
tOpDecXfrm=UXFORM_CMP_ST;
end
4'h7: begin //3xx7, CMP/GT Rm, Rn
opUCmd=UCMD_CMP_GT;
tOpDecXfrm=UXFORM_CMP_ST;
end
4'h8: begin //3xx8, SUB Rm, Rn
opUCmd=UCMD_ALU_SUB;
tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
4'hC: begin //3xxC, ADD Rm, Rn
opUCmd=UCMD_ALU_ADD;
tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
default: begin end
endcase
4'h4: case(opCmdWord[3:0])
4'h3: begin //4xx3
case(opCmdWord[7:4])
4'h0: begin
opUCmd=UCMD_ALU_ADD; tOpDecXfrm=UXFORM_NST_8E;
end
4'h1: begin
opUCmd=UCMD_ALU_SUB; tOpDecXfrm=UXFORM_NST_8E;
end
4'h2: begin
opUCmd=UCMD_ALU_MUL; tOpDecXfrm=UXFORM_NST_8E;
end
4'h3: begin
opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_NST_8E;
end
4'h4: begin
opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_NST_8E;
end
4'h5: begin
opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_NST_8E;
end
4'h6: begin
opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_NST_8E;
end
4'h7: begin
opUCmd=UCMD_ALU_SHLDR; tOpDecXfrm=UXFORM_NST_8E;
end
4'h8: begin
opUCmd=UCMD_ALU_SHAD; tOpDecXfrm=UXFORM_NST_8E;
end
4'h9: begin
opUCmd=UCMD_ALU_SHADR; tOpDecXfrm=UXFORM_NST_8E;
end
4'hC: begin
opUCmd=UCMD_FPU_FADD;
tOpDecXfrm=UXFORM_FPARI_NST_8E;
// tOpDecXfrm=UXFORM_NST_8E; tOpDecXfrmZx=UXFORMZX_FF;
end
4'hD: begin
opUCmd=UCMD_FPU_FSUB;
tOpDecXfrm=UXFORM_FPARI_NST_8E;
// tOpDecXfrm=UXFORM_NST_8E; tOpDecXfrmZx=UXFORMZX_FF;
end
4'hE: begin
opUCmd=UCMD_FPU_FMUL;
tOpDecXfrm=UXFORM_FPARI_NST_8E;
// tOpDecXfrm=UXFORM_NST_8E; tOpDecXfrmZx=UXFORMZX_FF;
end
default: begin end
endcase
end
4'hC: begin //4xxC
opUCmd=UCMD_ALU_SHAD;
tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_SX;
end
4'hD: begin //4xxD
opUCmd=UCMD_ALU_SHLD;
tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_SX;
end
4'hE: begin //4xxE, LDC
case(opCmdWord[7:4])
4'h0: begin
opUCmd=UCMD_MOVUB_MR;
tOpDecXfrm=UXFORM_NST_8E;
end
4'h1: begin
opUCmd=UCMD_MOVUW_MR;
tOpDecXfrm=UXFORM_NST_8E;
end
default: begin end
endcase
end
default: begin end
endcase
4'h5: begin //5xxx
opUCmd = UCMD_MOVL_MR;
tOpDecXfrm=UXFORM_MOV_NSJ;
end
4'h6: case(opCmdWord[3:0])
4'h0: begin //6xx0
opUCmd=UCMD_MOVB_MR;
tOpDecXfrm=UXFORM_MOV_NS;
end
4'h1: begin //6xx1
opUCmd = UCMD_MOVW_MR;
tOpDecXfrm=UXFORM_MOV_NS;
end
4'h2: begin //6xx2
opUCmd = UCMD_MOVL_MR;
tOpDecXfrm=UXFORM_MOV_NS;
end
4'h3: begin //6xx3
opUCmd=UCMD_MOVQ_MR;
tOpDecXfrm=UXFORM_MOV_NS;
end
4'h4: begin //6xx4
opUCmd=UCMD_LEAB_MR;
tOpDecXfrm=UXFORM_MOV_NSO;
end
4'h5: begin //6xx5
opUCmd=UCMD_LEAW_MR;
tOpDecXfrm=UXFORM_MOV_NSO;
end
4'h6: begin //6xx6
opUCmd=UCMD_LEAL_MR;
tOpDecXfrm=UXFORM_MOV_NSO;
end
4'h7: begin
opUCmd=UCMD_LEAQ_MR;
tOpDecXfrm=UXFORM_MOV_NSO;
end
4'h8: begin
opUCmd=UCMD_LEAB_MR;
tOpDecXfrm=UXFORM_MOV_NS;
end
4'h9: begin
opUCmd=UCMD_LEAW_MR;
tOpDecXfrm=UXFORM_MOV_NS;
end
4'hA: begin
opUCmd=UCMD_LEAL_MR;
tOpDecXfrm=UXFORM_MOV_NS;
end
4'hB: begin
opUCmd=UCMD_LEAQ_MR;
tOpDecXfrm=UXFORM_MOV_NS;
end
4'hC: begin
opUCmd=UCMD_MOVUB_MR;
tOpDecXfrm=UXFORM_MOV_NS;
end
4'hD: begin
opUCmd=UCMD_MOVUW_MR;
tOpDecXfrm=UXFORM_MOV_NS;
end
4'hE: begin
opUCmd=UCMD_MOVUL_MR;
tOpDecXfrm=UXFORM_MOV_NS;
end
4'hF: begin
opUCmd=UCMD_MOVQ_MR;
tOpDecXfrm=UXFORM_MOV_NS;
end
default: begin end
endcase
4'h7: begin //7xxx
opUCmd=UCMD_ALU_ADD;
tOpDecXfrm=UXFORM_ARI_NNI;
end
4'h8: case(opCmdWord[11:8])
4'h2: begin //82xx
opUCmd=UCMD_BRAN; tOpDecXfrm=UXFORM_BR_D8;
end
4'h3: begin //83xx
opUCmd=UCMD_BSRN; tOpDecXfrm=UXFORM_BR_D8;
end
4'h8: begin //88xx
opUCmd=UCMD_CMP_EQ;
tOpDecXfrm=UXFORM_ARI_I8R0;
end
4'h9: begin //89xx
opUCmd=UCMD_BT; tOpDecXfrm=UXFORM_BR_D8;
end
4'hA: begin //8Axx-xxxx
end
4'hB: begin //8Bxx, BF disp
opUCmd=UCMD_BF; tOpDecXfrm=UXFORM_BR_D8;
end
4'hC: begin //8Cxx
end
4'hD: begin //8Dxx, BTS disp
opUCmd=UCMD_BTS; tOpDecXfrm=UXFORM_BR_D8;
end
4'hF: begin //8Fxx, BFS disp
opUCmd=UCMD_BFS; tOpDecXfrm=UXFORM_BR_D8;
end
default: begin end
endcase
4'h9: begin //9xxx
opUCmd=UCMD_ALU_LDSH16;
tOpDecXfrm=UXFORM_ARI_NNI;
end
4'hA: begin //Axxx
opUCmd=UCMD_BRA; tOpDecXfrm=UXFORM_BR_D12;
end
4'hB: begin //Bxxx
opUCmd=UCMD_BSR; tOpDecXfrm=UXFORM_BR_D12;
end
4'hC: case(opCmdWord[11:8])
4'h0: begin
opUCmd=UCMD_MOVB_RM;
// tOpDecXfrm=UXFORM_MOV_GD8R0;
// tOpDecXfrmZx=UXFORMZX_RM;
tOpDecXfrm=UXFORM_MOV_GD8R0_RM;
end
4'h1: begin
opUCmd=UCMD_MOVW_RM;
// tOpDecXfrm=UXFORM_MOV_GD8R0;
// tOpDecXfrmZx=UXFORMZX_RM;
tOpDecXfrm=UXFORM_MOV_GD8R0_RM;
end
4'h2: begin
opUCmd=UCMD_MOVL_RM;
// tOpDecXfrm=UXFORM_MOV_GD8R0;
// tOpDecXfrmZx=UXFORMZX_RM;
tOpDecXfrm=UXFORM_MOV_GD8R0_RM;
end
4'h4: begin
opUCmd=UCMD_MOVB_MR;
// tOpDecXfrm=UXFORM_MOV_GD8R0;
// tOpDecXfrmZx=UXFORMZX_MR;
tOpDecXfrm=UXFORM_MOV_GD8R0_MR;
end
4'h5: begin
opUCmd=UCMD_MOVW_MR;
// tOpDecXfrm=UXFORM_MOV_GD8R0;
// tOpDecXfrmZx=UXFORMZX_MR;
tOpDecXfrm=UXFORM_MOV_GD8R0_MR;
end
4'h6: begin
opUCmd=UCMD_MOVL_MR;
// tOpDecXfrm=UXFORM_MOV_GD8R0;
// tOpDecXfrmZx=UXFORMZX_MR;
tOpDecXfrm=UXFORM_MOV_GD8R0_MR;
end
4'h8: begin //CMP/EQ #imm, R0
opUCmd=UCMD_CMP_TST;
tOpDecXfrm=UXFORM_CMP_I8R0;
end
4'h9: begin //AND #imm, R0
opUCmd=UCMD_ALU_AND;
tOpDecXfrm=UXFORM_ARI_I8R0;
end
4'hA: begin //XOR #imm, R0
opUCmd=UCMD_ALU_XOR;
tOpDecXfrm=UXFORM_ARI_I8R0;
end
4'hB: begin //OR #imm, R0
opUCmd=UCMD_ALU_OR;
tOpDecXfrm=UXFORM_ARI_I8R0;
end
default: begin end
endcase
// 4'hD: begin //Dxxx, MOV @(PC,disp), Rn
// end
4'hE: begin //Exxx, MOV #imm, Rn
opUCmd=UCMD_MOV_RI;
tOpDecXfrm=UXFORM_ARI_NNI;
end
default: begin end
endcase
case(tOpDecXfrm)
UXFORM_CST: begin
end
UXFORM_N: begin
opRegN=opRegN_Dfl;
opRegS=opRegN;
end
UXFORM_MOV_NS: begin
opRegN = opRegN_Dfl; opRegS = opRegM_Dfl;
opImm = opImm8_Sx8E;
end
UXFORM_MOV_NSO: begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
opRegT=opRegS_Dfl; opImm=opImm4_ZxXE;
end
UXFORM_MOV_NSJ: begin
opRegN = opRegN_Dfl; opRegS = opRegM_Dfl;
opRegT = opRegO_Dfl; opImm = opImm8_Sx8E;
end
// UXFORM_FPARI_NS: begin
// opRegN=opRegN_FR;
// opRegS=opRegM_FR;
// end
// UXFORM_ARI_NS: begin
// opRegN=opRegN_Dfl;
// opRegS=opRegM_Dfl;
// end
UXFORM_ARI_NST: begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
opRegT=UREG_MR_IMM;
case(tOpDecXfrmZx)
UXFORMZX_SX: opImm=opImm8_Sx8E;
UXFORMZX_ZX: opImm=opImm8_Zx8E;
UXFORMZX_NX: opImm=opImm8_Nx8E;
default: begin opImm=UV32_XX; end
endcase
end
UXFORM_CMP_ST: begin
opRegS=opRegN_Dfl;
opRegT=UREG_MR_IMM;
opImm=opImmM12_Sx8E;
end
UXFORM_ARI_ST: begin
opRegN=opRegN_Dfl;
opRegS=opRegM_Dfl;
end
UXFORM_ARI_NNI: begin
// opRegN={2'h0, opIsCE, opCmdWord[11:8]};
opRegN={3'h0, opCmdWord[11:8]};
opRegS=opRegN;
opRegT=UREG_MR_IMM; opImm=opImm16_Sx8E;
end
UXFORM_BR_D8: begin
opImm = opImm16_Sx8E;
end
UXFORM_BR_D12: begin
opImm = opImm20_Sx8E;
end
UXFORM_ARI_I8R0: begin
opRegN=opRegM_Dfl; opRegS=opRegM_Dfl;
opRegT=UREG_MR_IMM; opImm=opImmO12_Sx8E;
end
UXFORM_N_C: begin
opRegN=opRegN_Dfl; opRegS=opRegN_Dfl;
opRegT=UREG_MR_IMM;
end
/*
UXFORM_MOV_GD8R0: begin
case(tOpDecXfrmZx)
UXFORMZX_RM: begin
opRegN=UREG_GBR; opRegS=opRegM_Dfl;
opRegT=UREG_MR_IMM; opImm=opImmO12_Sx8E;
end
UXFORMZX_MR: begin
opRegN=opRegM_Dfl; opRegS=UREG_GBR;
opRegT=UREG_MR_IMM; opImm=opImmO12_Sx8E;
end
default: begin
opRegN=UREG_XX; opRegS=UREG_XX;
opRegT=UREG_XX; opImm=32'hXXXXXXXX;
end
endcase
end
*/
UXFORM_MOV_GD8R0_RM: begin
opRegN=UREG_GBR; opRegS=opRegM_Dfl;
opRegT=UREG_MR_IMM; opImm=opImmO12_Sx8E;
end
UXFORM_MOV_GD8R0_MR: begin
opRegN=opRegM_Dfl; opRegS=UREG_GBR;
opRegT=UREG_MR_IMM; opImm=opImmO12_Sx8E;
end
UXFORM_FPARI_NST_8E: begin
// opRegN=opRegN_FR;
// opRegS=opRegM_FR;
opRegN=opRegN_FR;
opRegS=opRegS_FR;
opRegT=opRegT_FR;
end
UXFORM_NST_8E: begin
opRegN=opRegN_Dfl;
opRegS=opRegS_Dfl;
opRegT=opRegT_Dfl;
/*
case(tOpDecXfrmZx)
UXFORMZX_RR: begin
opRegN=opRegN_Dfl;
opRegS=opRegS_Dfl;
opRegT=opRegT_Dfl;
end
UXFORMZX_FF: begin
opRegN=opRegN_FR;
opRegS=opRegS_FR;
opRegT=opRegT_FR;
end
default: begin
opRegN=UREG_XX; opRegS=UREG_XX;
opRegT=UREG_XX; opImm=32'hXXXXXXXX;
end
endcase
*/
end
UXFORM_INVALID: begin
opRegN=UREG_XX; opRegS=UREG_XX;
opRegT=UREG_XX; opImm=32'hXXXXXXXX;
end
default: begin
opRegN=UREG_XX; opRegS=UREG_XX;
opRegT=UREG_XX; opImm=32'hXXXXXXXX;
end
endcase
end
endmodule
|
// AUTOGENERATED FILE; DO NOT MODIFY.
// run with topX= 8 and topY= 8
//
`include "bsg_defines.v"
module bsg_mesh_to_ring_stitch #(parameter `BSG_INV_PARAM(y_max_p)
,parameter `BSG_INV_PARAM(x_max_p)
,parameter `BSG_INV_PARAM(width_back_p)
,parameter `BSG_INV_PARAM(width_fwd_p)
,parameter b_lp = $clog2(x_max_p*y_max_p)
) (output [x_max_p-1:0][y_max_p-1:0][b_lp-1:0] id_o
,output [x_max_p-1:0][y_max_p-1:0][width_back_p-1:0] back_data_in_o
,input [x_max_p-1:0][y_max_p-1:0][width_back_p-1:0] back_data_out_i
,output [x_max_p-1:0][y_max_p-1:0][width_fwd_p-1:0] fwd_data_in_o
,input [x_max_p-1:0][y_max_p-1:0][width_fwd_p-1:0] fwd_data_out_i
);
if (x_max_p == 2 && y_max_p == 2 )
begin
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 1 ][ 1 ]; // 0 <- 1
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 1 ][ 1 ]; // 1 -> 2
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 3 <- 0
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 1 ][ 0 ]; // 1 <- 2
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 2 -> 3
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 2 <- 3
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 3 -> 0
assign id_o =
{
// y = 0, 1,
{ b_lp ' (3) , b_lp ' (0) }, // x = 0
{ b_lp ' (2) , b_lp ' (1) } // x = 1
};
end
if (x_max_p == 2 && y_max_p == 3 )
begin
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 1 ][ 2 ]; // 1 <- 2
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 2 -> 3
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 2 <- 3
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 1 ][ 1 ]; // 3 -> 4
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 5 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 1 ][ 0 ]; // 3 <- 4
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 4 -> 5
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 4 <- 5
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 5 -> 0
assign id_o =
{
// y = 0, 1, 2,
{ b_lp ' (5) , b_lp ' (0) , b_lp ' (1) }, // x = 0
{ b_lp ' (4) , b_lp ' (3) , b_lp ' (2) } // x = 1
};
end
if (x_max_p == 2 && y_max_p == 4 )
begin
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 1 ][ 3 ]; // 2 <- 3
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 3 ]; // 3 -> 4
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 3 ]; // 1 <- 2
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 0 ][ 3 ]; // 2 -> 3
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 2 ]; // 3 <- 4
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 4 -> 5
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 4 <- 5
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 1 ][ 1 ]; // 5 -> 6
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 7 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 1 ][ 0 ]; // 5 <- 6
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 6 -> 7
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 6 <- 7
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 7 -> 0
assign id_o =
{
// y = 0, 1, 2, 3,
{ b_lp ' (7) , b_lp ' (0) , b_lp ' (1) , b_lp ' (2) }, // x = 0
{ b_lp ' (6) , b_lp ' (5) , b_lp ' (4) , b_lp ' (3) } // x = 1
};
end
if (x_max_p == 2 && y_max_p == 5 )
begin
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 1 ][ 4 ]; // 3 <- 4
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 1 ][ 4 ]; // 4 -> 5
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 4 ]; // 2 <- 3
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 0 ][ 4 ]; // 3 -> 4
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 1 ][ 3 ]; // 4 <- 5
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 3 ]; // 5 -> 6
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 3 ]; // 1 <- 2
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 3 ]; // 2 -> 3
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 2 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 6 -> 7
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 6 <- 7
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 1 ][ 1 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 9 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 1 ][ 0 ]; // 7 <- 8
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 8 -> 9
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 8 <- 9
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 9 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4,
{ b_lp ' (9) , b_lp ' (0) , b_lp ' (1) , b_lp ' (2) , b_lp ' (3) }, // x = 0
{ b_lp ' (8) , b_lp ' (7) , b_lp ' (6) , b_lp ' (5) , b_lp ' (4) } // x = 1
};
end
if (x_max_p == 2 && y_max_p == 6 )
begin
assign back_data_in_o[ 0 ][ 5 ] = back_data_out_i[ 1 ][ 5 ]; // 4 <- 5
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 1 ][ 5 ]; // 5 -> 6
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 0 ][ 5 ]; // 3 <- 4
assign fwd_data_in_o [ 1 ][ 5 ] = fwd_data_out_i [ 0 ][ 5 ]; // 4 -> 5
assign back_data_in_o[ 1 ][ 5 ] = back_data_out_i[ 1 ][ 4 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 1 ][ 4 ]; // 6 -> 7
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 4 ]; // 2 <- 3
assign fwd_data_in_o [ 0 ][ 5 ] = fwd_data_out_i [ 0 ][ 4 ]; // 3 -> 4
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 1 ][ 3 ]; // 6 <- 7
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 3 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 3 ]; // 1 <- 2
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 3 ]; // 2 -> 3
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 2 ]; // 7 <- 8
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 8 -> 9
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 8 <- 9
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 1 ][ 1 ]; // 9 -> 10
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 11 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 1 ][ 0 ]; // 9 <- 10
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 10 -> 11
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 10 <- 11
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 11 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4, 5,
{ b_lp ' (11) , b_lp ' (0) , b_lp ' (1) , b_lp ' (2) , b_lp ' (3) , b_lp ' (4) }, // x = 0
{ b_lp ' (10) , b_lp ' (9) , b_lp ' (8) , b_lp ' (7) , b_lp ' (6) , b_lp ' (5) } // x = 1
};
end
if (x_max_p == 2 && y_max_p == 7 )
begin
assign back_data_in_o[ 0 ][ 6 ] = back_data_out_i[ 1 ][ 6 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 5 ] = fwd_data_out_i [ 1 ][ 6 ]; // 6 -> 7
assign back_data_in_o[ 0 ][ 5 ] = back_data_out_i[ 0 ][ 6 ]; // 4 <- 5
assign fwd_data_in_o [ 1 ][ 6 ] = fwd_data_out_i [ 0 ][ 6 ]; // 5 -> 6
assign back_data_in_o[ 1 ][ 6 ] = back_data_out_i[ 1 ][ 5 ]; // 6 <- 7
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 1 ][ 5 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 0 ][ 5 ]; // 3 <- 4
assign fwd_data_in_o [ 0 ][ 6 ] = fwd_data_out_i [ 0 ][ 5 ]; // 4 -> 5
assign back_data_in_o[ 1 ][ 5 ] = back_data_out_i[ 1 ][ 4 ]; // 7 <- 8
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 1 ][ 4 ]; // 8 -> 9
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 4 ]; // 2 <- 3
assign fwd_data_in_o [ 0 ][ 5 ] = fwd_data_out_i [ 0 ][ 4 ]; // 3 -> 4
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 1 ][ 3 ]; // 8 <- 9
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 3 ]; // 9 -> 10
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 3 ]; // 1 <- 2
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 3 ]; // 2 -> 3
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 2 ]; // 9 <- 10
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 10 -> 11
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 10 <- 11
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 1 ][ 1 ]; // 11 -> 12
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 13 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 1 ][ 0 ]; // 11 <- 12
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 12 -> 13
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 12 <- 13
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 13 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4, 5, 6,
{ b_lp ' (13) , b_lp ' (0) , b_lp ' (1) , b_lp ' (2) , b_lp ' (3) , b_lp ' (4) , b_lp ' (5) }, // x = 0
{ b_lp ' (12) , b_lp ' (11) , b_lp ' (10) , b_lp ' (9) , b_lp ' (8) , b_lp ' (7) , b_lp ' (6) } // x = 1
};
end
if (x_max_p == 2 && y_max_p == 8 )
begin
assign back_data_in_o[ 0 ][ 7 ] = back_data_out_i[ 1 ][ 7 ]; // 6 <- 7
assign fwd_data_in_o [ 1 ][ 6 ] = fwd_data_out_i [ 1 ][ 7 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 6 ] = back_data_out_i[ 0 ][ 7 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 7 ] = fwd_data_out_i [ 0 ][ 7 ]; // 6 -> 7
assign back_data_in_o[ 1 ][ 7 ] = back_data_out_i[ 1 ][ 6 ]; // 7 <- 8
assign fwd_data_in_o [ 1 ][ 5 ] = fwd_data_out_i [ 1 ][ 6 ]; // 8 -> 9
assign back_data_in_o[ 0 ][ 5 ] = back_data_out_i[ 0 ][ 6 ]; // 4 <- 5
assign fwd_data_in_o [ 0 ][ 7 ] = fwd_data_out_i [ 0 ][ 6 ]; // 5 -> 6
assign back_data_in_o[ 1 ][ 6 ] = back_data_out_i[ 1 ][ 5 ]; // 8 <- 9
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 1 ][ 5 ]; // 9 -> 10
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 0 ][ 5 ]; // 3 <- 4
assign fwd_data_in_o [ 0 ][ 6 ] = fwd_data_out_i [ 0 ][ 5 ]; // 4 -> 5
assign back_data_in_o[ 1 ][ 5 ] = back_data_out_i[ 1 ][ 4 ]; // 9 <- 10
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 1 ][ 4 ]; // 10 -> 11
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 4 ]; // 2 <- 3
assign fwd_data_in_o [ 0 ][ 5 ] = fwd_data_out_i [ 0 ][ 4 ]; // 3 -> 4
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 1 ][ 3 ]; // 10 <- 11
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 3 ]; // 11 -> 12
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 3 ]; // 1 <- 2
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 3 ]; // 2 -> 3
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 2 ]; // 11 <- 12
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 12 -> 13
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 12 <- 13
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 1 ][ 1 ]; // 13 -> 14
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 15 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 1 ][ 0 ]; // 13 <- 14
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 14 -> 15
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 14 <- 15
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 15 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4, 5, 6, 7,
{ b_lp ' (15) , b_lp ' (0) , b_lp ' (1) , b_lp ' (2) , b_lp ' (3) , b_lp ' (4) , b_lp ' (5) , b_lp ' (6) }, // x = 0
{ b_lp ' (14) , b_lp ' (13) , b_lp ' (12) , b_lp ' (11) , b_lp ' (10) , b_lp ' (9) , b_lp ' (8) , b_lp ' (7) } // x = 1
};
end
if (x_max_p == 4 && y_max_p == 2 )
begin
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 3 ][ 1 ]; // 2 <- 3
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 3 ][ 1 ]; // 3 -> 4
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 1 <- 2
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 2 ][ 1 ]; // 2 -> 3
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 1 ][ 1 ]; // 0 <- 1
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 1 -> 2
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 7 <- 0
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 3 ][ 0 ]; // 3 <- 4
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 4 -> 5
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 4 <- 5
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 5 -> 6
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 5 <- 6
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 6 -> 7
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 6 <- 7
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 7 -> 0
assign id_o =
{
// y = 0, 1,
{ b_lp ' (7) , b_lp ' (0) }, // x = 0
{ b_lp ' (6) , b_lp ' (1) }, // x = 1
{ b_lp ' (5) , b_lp ' (2) }, // x = 2
{ b_lp ' (4) , b_lp ' (3) } // x = 3
};
end
if (x_max_p == 4 && y_max_p == 3 )
begin
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 3 ][ 2 ]; // 5 <- 6
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 3 ][ 2 ]; // 6 -> 7
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 2 ][ 2 ]; // 4 <- 5
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 2 ][ 2 ]; // 5 -> 6
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 1 ][ 2 ]; // 1 <- 2
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 2 -> 3
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 3 ][ 1 ]; // 6 <- 7
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 3 ][ 1 ]; // 7 -> 8
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 3 <- 4
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 2 ][ 1 ]; // 4 -> 5
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 2 <- 3
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 3 -> 4
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 11 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 3 ][ 0 ]; // 7 <- 8
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 8 -> 9
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 8 <- 9
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 9 -> 10
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 9 <- 10
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 10 -> 11
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 10 <- 11
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 11 -> 0
assign id_o =
{
// y = 0, 1, 2,
{ b_lp ' (11) , b_lp ' (0) , b_lp ' (1) }, // x = 0
{ b_lp ' (10) , b_lp ' (3) , b_lp ' (2) }, // x = 1
{ b_lp ' (9) , b_lp ' (4) , b_lp ' (5) }, // x = 2
{ b_lp ' (8) , b_lp ' (7) , b_lp ' (6) } // x = 3
};
end
if (x_max_p == 4 && y_max_p == 4 )
begin
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 3 ][ 3 ]; // 8 <- 9
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 3 ][ 3 ]; // 9 -> 10
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 2 ][ 3 ]; // 7 <- 8
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 2 ][ 3 ]; // 8 -> 9
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 1 ][ 3 ]; // 2 <- 3
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 3 ]; // 3 -> 4
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 3 ]; // 1 <- 2
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 0 ][ 3 ]; // 2 -> 3
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 3 ][ 2 ]; // 9 <- 10
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 3 ][ 2 ]; // 10 -> 11
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 2 ][ 2 ]; // 6 <- 7
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 2 ][ 2 ]; // 7 -> 8
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 2 ]; // 3 <- 4
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 4 -> 5
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 3 ][ 1 ]; // 10 <- 11
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 3 ][ 1 ]; // 11 -> 12
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 5 <- 6
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 2 ][ 1 ]; // 6 -> 7
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 4 <- 5
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 5 -> 6
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 15 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 3 ][ 0 ]; // 11 <- 12
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 12 -> 13
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 12 <- 13
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 13 -> 14
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 13 <- 14
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 14 -> 15
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 14 <- 15
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 15 -> 0
assign id_o =
{
// y = 0, 1, 2, 3,
{ b_lp ' (15) , b_lp ' (0) , b_lp ' (1) , b_lp ' (2) }, // x = 0
{ b_lp ' (14) , b_lp ' (5) , b_lp ' (4) , b_lp ' (3) }, // x = 1
{ b_lp ' (13) , b_lp ' (6) , b_lp ' (7) , b_lp ' (8) }, // x = 2
{ b_lp ' (12) , b_lp ' (11) , b_lp ' (10) , b_lp ' (9) } // x = 3
};
end
if (x_max_p == 4 && y_max_p == 5 )
begin
assign back_data_in_o[ 2 ][ 4 ] = back_data_out_i[ 3 ][ 4 ]; // 11 <- 12
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 3 ][ 4 ]; // 12 -> 13
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 2 ][ 4 ]; // 10 <- 11
assign fwd_data_in_o [ 3 ][ 4 ] = fwd_data_out_i [ 2 ][ 4 ]; // 11 -> 12
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 1 ][ 4 ]; // 3 <- 4
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 1 ][ 4 ]; // 4 -> 5
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 4 ]; // 2 <- 3
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 0 ][ 4 ]; // 3 -> 4
assign back_data_in_o[ 3 ][ 4 ] = back_data_out_i[ 3 ][ 3 ]; // 12 <- 13
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 3 ][ 3 ]; // 13 -> 14
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 2 ][ 3 ]; // 9 <- 10
assign fwd_data_in_o [ 2 ][ 4 ] = fwd_data_out_i [ 2 ][ 3 ]; // 10 -> 11
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 1 ][ 3 ]; // 4 <- 5
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 3 ]; // 5 -> 6
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 3 ]; // 1 <- 2
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 3 ]; // 2 -> 3
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 3 ][ 2 ]; // 13 <- 14
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 3 ][ 2 ]; // 14 -> 15
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 2 ][ 2 ]; // 8 <- 9
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 2 ][ 2 ]; // 9 -> 10
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 2 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 6 -> 7
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 3 ][ 1 ]; // 14 <- 15
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 3 ][ 1 ]; // 15 -> 16
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 7 <- 8
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 2 ][ 1 ]; // 8 -> 9
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 6 <- 7
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 19 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 3 ][ 0 ]; // 15 <- 16
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 16 -> 17
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 16 <- 17
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 17 -> 18
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 17 <- 18
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 18 -> 19
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 18 <- 19
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 19 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4,
{ b_lp ' (19) , b_lp ' (0) , b_lp ' (1) , b_lp ' (2) , b_lp ' (3) }, // x = 0
{ b_lp ' (18) , b_lp ' (7) , b_lp ' (6) , b_lp ' (5) , b_lp ' (4) }, // x = 1
{ b_lp ' (17) , b_lp ' (8) , b_lp ' (9) , b_lp ' (10) , b_lp ' (11) }, // x = 2
{ b_lp ' (16) , b_lp ' (15) , b_lp ' (14) , b_lp ' (13) , b_lp ' (12) } // x = 3
};
end
if (x_max_p == 4 && y_max_p == 6 )
begin
assign back_data_in_o[ 2 ][ 5 ] = back_data_out_i[ 3 ][ 5 ]; // 14 <- 15
assign fwd_data_in_o [ 3 ][ 4 ] = fwd_data_out_i [ 3 ][ 5 ]; // 15 -> 16
assign back_data_in_o[ 2 ][ 4 ] = back_data_out_i[ 2 ][ 5 ]; // 13 <- 14
assign fwd_data_in_o [ 3 ][ 5 ] = fwd_data_out_i [ 2 ][ 5 ]; // 14 -> 15
assign back_data_in_o[ 0 ][ 5 ] = back_data_out_i[ 1 ][ 5 ]; // 4 <- 5
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 1 ][ 5 ]; // 5 -> 6
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 0 ][ 5 ]; // 3 <- 4
assign fwd_data_in_o [ 1 ][ 5 ] = fwd_data_out_i [ 0 ][ 5 ]; // 4 -> 5
assign back_data_in_o[ 3 ][ 5 ] = back_data_out_i[ 3 ][ 4 ]; // 15 <- 16
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 3 ][ 4 ]; // 16 -> 17
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 2 ][ 4 ]; // 12 <- 13
assign fwd_data_in_o [ 2 ][ 5 ] = fwd_data_out_i [ 2 ][ 4 ]; // 13 -> 14
assign back_data_in_o[ 1 ][ 5 ] = back_data_out_i[ 1 ][ 4 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 1 ][ 4 ]; // 6 -> 7
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 4 ]; // 2 <- 3
assign fwd_data_in_o [ 0 ][ 5 ] = fwd_data_out_i [ 0 ][ 4 ]; // 3 -> 4
assign back_data_in_o[ 3 ][ 4 ] = back_data_out_i[ 3 ][ 3 ]; // 16 <- 17
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 3 ][ 3 ]; // 17 -> 18
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 2 ][ 3 ]; // 11 <- 12
assign fwd_data_in_o [ 2 ][ 4 ] = fwd_data_out_i [ 2 ][ 3 ]; // 12 -> 13
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 1 ][ 3 ]; // 6 <- 7
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 3 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 3 ]; // 1 <- 2
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 3 ]; // 2 -> 3
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 3 ][ 2 ]; // 17 <- 18
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 3 ][ 2 ]; // 18 -> 19
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 2 ][ 2 ]; // 10 <- 11
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 2 ][ 2 ]; // 11 -> 12
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 2 ]; // 7 <- 8
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 8 -> 9
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 3 ][ 1 ]; // 18 <- 19
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 3 ][ 1 ]; // 19 -> 20
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 9 <- 10
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 2 ][ 1 ]; // 10 -> 11
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 8 <- 9
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 9 -> 10
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 23 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 3 ][ 0 ]; // 19 <- 20
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 20 -> 21
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 20 <- 21
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 21 -> 22
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 21 <- 22
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 22 -> 23
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 22 <- 23
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 23 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4, 5,
{ b_lp ' (23) , b_lp ' (0) , b_lp ' (1) , b_lp ' (2) , b_lp ' (3) , b_lp ' (4) }, // x = 0
{ b_lp ' (22) , b_lp ' (9) , b_lp ' (8) , b_lp ' (7) , b_lp ' (6) , b_lp ' (5) }, // x = 1
{ b_lp ' (21) , b_lp ' (10) , b_lp ' (11) , b_lp ' (12) , b_lp ' (13) , b_lp ' (14) }, // x = 2
{ b_lp ' (20) , b_lp ' (19) , b_lp ' (18) , b_lp ' (17) , b_lp ' (16) , b_lp ' (15) } // x = 3
};
end
if (x_max_p == 4 && y_max_p == 7 )
begin
assign back_data_in_o[ 2 ][ 6 ] = back_data_out_i[ 3 ][ 6 ]; // 17 <- 18
assign fwd_data_in_o [ 3 ][ 5 ] = fwd_data_out_i [ 3 ][ 6 ]; // 18 -> 19
assign back_data_in_o[ 2 ][ 5 ] = back_data_out_i[ 2 ][ 6 ]; // 16 <- 17
assign fwd_data_in_o [ 3 ][ 6 ] = fwd_data_out_i [ 2 ][ 6 ]; // 17 -> 18
assign back_data_in_o[ 0 ][ 6 ] = back_data_out_i[ 1 ][ 6 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 5 ] = fwd_data_out_i [ 1 ][ 6 ]; // 6 -> 7
assign back_data_in_o[ 0 ][ 5 ] = back_data_out_i[ 0 ][ 6 ]; // 4 <- 5
assign fwd_data_in_o [ 1 ][ 6 ] = fwd_data_out_i [ 0 ][ 6 ]; // 5 -> 6
assign back_data_in_o[ 3 ][ 6 ] = back_data_out_i[ 3 ][ 5 ]; // 18 <- 19
assign fwd_data_in_o [ 3 ][ 4 ] = fwd_data_out_i [ 3 ][ 5 ]; // 19 -> 20
assign back_data_in_o[ 2 ][ 4 ] = back_data_out_i[ 2 ][ 5 ]; // 15 <- 16
assign fwd_data_in_o [ 2 ][ 6 ] = fwd_data_out_i [ 2 ][ 5 ]; // 16 -> 17
assign back_data_in_o[ 1 ][ 6 ] = back_data_out_i[ 1 ][ 5 ]; // 6 <- 7
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 1 ][ 5 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 0 ][ 5 ]; // 3 <- 4
assign fwd_data_in_o [ 0 ][ 6 ] = fwd_data_out_i [ 0 ][ 5 ]; // 4 -> 5
assign back_data_in_o[ 3 ][ 5 ] = back_data_out_i[ 3 ][ 4 ]; // 19 <- 20
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 3 ][ 4 ]; // 20 -> 21
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 2 ][ 4 ]; // 14 <- 15
assign fwd_data_in_o [ 2 ][ 5 ] = fwd_data_out_i [ 2 ][ 4 ]; // 15 -> 16
assign back_data_in_o[ 1 ][ 5 ] = back_data_out_i[ 1 ][ 4 ]; // 7 <- 8
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 1 ][ 4 ]; // 8 -> 9
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 4 ]; // 2 <- 3
assign fwd_data_in_o [ 0 ][ 5 ] = fwd_data_out_i [ 0 ][ 4 ]; // 3 -> 4
assign back_data_in_o[ 3 ][ 4 ] = back_data_out_i[ 3 ][ 3 ]; // 20 <- 21
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 3 ][ 3 ]; // 21 -> 22
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 2 ][ 3 ]; // 13 <- 14
assign fwd_data_in_o [ 2 ][ 4 ] = fwd_data_out_i [ 2 ][ 3 ]; // 14 -> 15
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 1 ][ 3 ]; // 8 <- 9
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 3 ]; // 9 -> 10
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 3 ]; // 1 <- 2
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 3 ]; // 2 -> 3
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 3 ][ 2 ]; // 21 <- 22
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 3 ][ 2 ]; // 22 -> 23
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 2 ][ 2 ]; // 12 <- 13
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 2 ][ 2 ]; // 13 -> 14
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 2 ]; // 9 <- 10
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 10 -> 11
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 3 ][ 1 ]; // 22 <- 23
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 3 ][ 1 ]; // 23 -> 24
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 11 <- 12
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 2 ][ 1 ]; // 12 -> 13
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 10 <- 11
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 11 -> 12
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 27 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 3 ][ 0 ]; // 23 <- 24
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 24 -> 25
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 24 <- 25
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 25 -> 26
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 25 <- 26
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 26 -> 27
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 26 <- 27
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 27 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4, 5, 6,
{ b_lp ' (27) , b_lp ' (0) , b_lp ' (1) , b_lp ' (2) , b_lp ' (3) , b_lp ' (4) , b_lp ' (5) }, // x = 0
{ b_lp ' (26) , b_lp ' (11) , b_lp ' (10) , b_lp ' (9) , b_lp ' (8) , b_lp ' (7) , b_lp ' (6) }, // x = 1
{ b_lp ' (25) , b_lp ' (12) , b_lp ' (13) , b_lp ' (14) , b_lp ' (15) , b_lp ' (16) , b_lp ' (17) }, // x = 2
{ b_lp ' (24) , b_lp ' (23) , b_lp ' (22) , b_lp ' (21) , b_lp ' (20) , b_lp ' (19) , b_lp ' (18) } // x = 3
};
end
if (x_max_p == 4 && y_max_p == 8 )
begin
assign back_data_in_o[ 2 ][ 7 ] = back_data_out_i[ 3 ][ 7 ]; // 20 <- 21
assign fwd_data_in_o [ 3 ][ 6 ] = fwd_data_out_i [ 3 ][ 7 ]; // 21 -> 22
assign back_data_in_o[ 2 ][ 6 ] = back_data_out_i[ 2 ][ 7 ]; // 19 <- 20
assign fwd_data_in_o [ 3 ][ 7 ] = fwd_data_out_i [ 2 ][ 7 ]; // 20 -> 21
assign back_data_in_o[ 0 ][ 7 ] = back_data_out_i[ 1 ][ 7 ]; // 6 <- 7
assign fwd_data_in_o [ 1 ][ 6 ] = fwd_data_out_i [ 1 ][ 7 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 6 ] = back_data_out_i[ 0 ][ 7 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 7 ] = fwd_data_out_i [ 0 ][ 7 ]; // 6 -> 7
assign back_data_in_o[ 3 ][ 7 ] = back_data_out_i[ 3 ][ 6 ]; // 21 <- 22
assign fwd_data_in_o [ 3 ][ 5 ] = fwd_data_out_i [ 3 ][ 6 ]; // 22 -> 23
assign back_data_in_o[ 2 ][ 5 ] = back_data_out_i[ 2 ][ 6 ]; // 18 <- 19
assign fwd_data_in_o [ 2 ][ 7 ] = fwd_data_out_i [ 2 ][ 6 ]; // 19 -> 20
assign back_data_in_o[ 1 ][ 7 ] = back_data_out_i[ 1 ][ 6 ]; // 7 <- 8
assign fwd_data_in_o [ 1 ][ 5 ] = fwd_data_out_i [ 1 ][ 6 ]; // 8 -> 9
assign back_data_in_o[ 0 ][ 5 ] = back_data_out_i[ 0 ][ 6 ]; // 4 <- 5
assign fwd_data_in_o [ 0 ][ 7 ] = fwd_data_out_i [ 0 ][ 6 ]; // 5 -> 6
assign back_data_in_o[ 3 ][ 6 ] = back_data_out_i[ 3 ][ 5 ]; // 22 <- 23
assign fwd_data_in_o [ 3 ][ 4 ] = fwd_data_out_i [ 3 ][ 5 ]; // 23 -> 24
assign back_data_in_o[ 2 ][ 4 ] = back_data_out_i[ 2 ][ 5 ]; // 17 <- 18
assign fwd_data_in_o [ 2 ][ 6 ] = fwd_data_out_i [ 2 ][ 5 ]; // 18 -> 19
assign back_data_in_o[ 1 ][ 6 ] = back_data_out_i[ 1 ][ 5 ]; // 8 <- 9
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 1 ][ 5 ]; // 9 -> 10
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 0 ][ 5 ]; // 3 <- 4
assign fwd_data_in_o [ 0 ][ 6 ] = fwd_data_out_i [ 0 ][ 5 ]; // 4 -> 5
assign back_data_in_o[ 3 ][ 5 ] = back_data_out_i[ 3 ][ 4 ]; // 23 <- 24
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 3 ][ 4 ]; // 24 -> 25
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 2 ][ 4 ]; // 16 <- 17
assign fwd_data_in_o [ 2 ][ 5 ] = fwd_data_out_i [ 2 ][ 4 ]; // 17 -> 18
assign back_data_in_o[ 1 ][ 5 ] = back_data_out_i[ 1 ][ 4 ]; // 9 <- 10
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 1 ][ 4 ]; // 10 -> 11
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 4 ]; // 2 <- 3
assign fwd_data_in_o [ 0 ][ 5 ] = fwd_data_out_i [ 0 ][ 4 ]; // 3 -> 4
assign back_data_in_o[ 3 ][ 4 ] = back_data_out_i[ 3 ][ 3 ]; // 24 <- 25
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 3 ][ 3 ]; // 25 -> 26
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 2 ][ 3 ]; // 15 <- 16
assign fwd_data_in_o [ 2 ][ 4 ] = fwd_data_out_i [ 2 ][ 3 ]; // 16 -> 17
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 1 ][ 3 ]; // 10 <- 11
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 3 ]; // 11 -> 12
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 3 ]; // 1 <- 2
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 3 ]; // 2 -> 3
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 3 ][ 2 ]; // 25 <- 26
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 3 ][ 2 ]; // 26 -> 27
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 2 ][ 2 ]; // 14 <- 15
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 2 ][ 2 ]; // 15 -> 16
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 2 ]; // 11 <- 12
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 12 -> 13
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 3 ][ 1 ]; // 26 <- 27
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 3 ][ 1 ]; // 27 -> 28
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 13 <- 14
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 2 ][ 1 ]; // 14 -> 15
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 12 <- 13
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 13 -> 14
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 31 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 3 ][ 0 ]; // 27 <- 28
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 28 -> 29
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 28 <- 29
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 29 -> 30
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 29 <- 30
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 30 -> 31
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 30 <- 31
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 31 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4, 5, 6, 7,
{ b_lp ' (31) , b_lp ' (0) , b_lp ' (1) , b_lp ' (2) , b_lp ' (3) , b_lp ' (4) , b_lp ' (5) , b_lp ' (6) }, // x = 0
{ b_lp ' (30) , b_lp ' (13) , b_lp ' (12) , b_lp ' (11) , b_lp ' (10) , b_lp ' (9) , b_lp ' (8) , b_lp ' (7) }, // x = 1
{ b_lp ' (29) , b_lp ' (14) , b_lp ' (15) , b_lp ' (16) , b_lp ' (17) , b_lp ' (18) , b_lp ' (19) , b_lp ' (20) }, // x = 2
{ b_lp ' (28) , b_lp ' (27) , b_lp ' (26) , b_lp ' (25) , b_lp ' (24) , b_lp ' (23) , b_lp ' (22) , b_lp ' (21) } // x = 3
};
end
if (x_max_p == 6 && y_max_p == 2 )
begin
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 5 ][ 1 ]; // 4 <- 5
assign fwd_data_in_o [ 5 ][ 0 ] = fwd_data_out_i [ 5 ][ 1 ]; // 5 -> 6
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 4 ][ 1 ]; // 3 <- 4
assign fwd_data_in_o [ 5 ][ 1 ] = fwd_data_out_i [ 4 ][ 1 ]; // 4 -> 5
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 3 ][ 1 ]; // 2 <- 3
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 3 -> 4
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 1 <- 2
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 2 ][ 1 ]; // 2 -> 3
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 1 ][ 1 ]; // 0 <- 1
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 1 -> 2
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 11 <- 0
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 5 ][ 1 ] = back_data_out_i[ 5 ][ 0 ]; // 5 <- 6
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 5 ][ 0 ]; // 6 -> 7
assign back_data_in_o[ 5 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 6 <- 7
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 4 ][ 0 ]; // 7 -> 8
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 7 <- 8
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 8 -> 9
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 8 <- 9
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 9 -> 10
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 9 <- 10
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 10 -> 11
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 10 <- 11
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 11 -> 0
assign id_o =
{
// y = 0, 1,
{ b_lp ' (11) , b_lp ' (0) }, // x = 0
{ b_lp ' (10) , b_lp ' (1) }, // x = 1
{ b_lp ' (9) , b_lp ' (2) }, // x = 2
{ b_lp ' (8) , b_lp ' (3) }, // x = 3
{ b_lp ' (7) , b_lp ' (4) }, // x = 4
{ b_lp ' (6) , b_lp ' (5) } // x = 5
};
end
if (x_max_p == 6 && y_max_p == 3 )
begin
assign back_data_in_o[ 4 ][ 2 ] = back_data_out_i[ 5 ][ 2 ]; // 9 <- 10
assign fwd_data_in_o [ 5 ][ 1 ] = fwd_data_out_i [ 5 ][ 2 ]; // 10 -> 11
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 4 ][ 2 ]; // 8 <- 9
assign fwd_data_in_o [ 5 ][ 2 ] = fwd_data_out_i [ 4 ][ 2 ]; // 9 -> 10
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 3 ][ 2 ]; // 5 <- 6
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 3 ][ 2 ]; // 6 -> 7
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 2 ][ 2 ]; // 4 <- 5
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 2 ][ 2 ]; // 5 -> 6
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 1 ][ 2 ]; // 1 <- 2
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 2 -> 3
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 5 ][ 2 ] = back_data_out_i[ 5 ][ 1 ]; // 10 <- 11
assign fwd_data_in_o [ 5 ][ 0 ] = fwd_data_out_i [ 5 ][ 1 ]; // 11 -> 12
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 4 ][ 1 ]; // 7 <- 8
assign fwd_data_in_o [ 4 ][ 2 ] = fwd_data_out_i [ 4 ][ 1 ]; // 8 -> 9
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 3 ][ 1 ]; // 6 <- 7
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 7 -> 8
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 3 <- 4
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 2 ][ 1 ]; // 4 -> 5
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 2 <- 3
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 3 -> 4
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 17 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 5 ][ 1 ] = back_data_out_i[ 5 ][ 0 ]; // 11 <- 12
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 5 ][ 0 ]; // 12 -> 13
assign back_data_in_o[ 5 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 12 <- 13
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 4 ][ 0 ]; // 13 -> 14
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 13 <- 14
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 14 -> 15
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 14 <- 15
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 15 -> 16
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 15 <- 16
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 16 -> 17
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 16 <- 17
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 17 -> 0
assign id_o =
{
// y = 0, 1, 2,
{ b_lp ' (17) , b_lp ' (0) , b_lp ' (1) }, // x = 0
{ b_lp ' (16) , b_lp ' (3) , b_lp ' (2) }, // x = 1
{ b_lp ' (15) , b_lp ' (4) , b_lp ' (5) }, // x = 2
{ b_lp ' (14) , b_lp ' (7) , b_lp ' (6) }, // x = 3
{ b_lp ' (13) , b_lp ' (8) , b_lp ' (9) }, // x = 4
{ b_lp ' (12) , b_lp ' (11) , b_lp ' (10) } // x = 5
};
end
if (x_max_p == 6 && y_max_p == 4 )
begin
assign back_data_in_o[ 4 ][ 3 ] = back_data_out_i[ 5 ][ 3 ]; // 14 <- 15
assign fwd_data_in_o [ 5 ][ 2 ] = fwd_data_out_i [ 5 ][ 3 ]; // 15 -> 16
assign back_data_in_o[ 4 ][ 2 ] = back_data_out_i[ 4 ][ 3 ]; // 13 <- 14
assign fwd_data_in_o [ 5 ][ 3 ] = fwd_data_out_i [ 4 ][ 3 ]; // 14 -> 15
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 3 ][ 3 ]; // 8 <- 9
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 3 ][ 3 ]; // 9 -> 10
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 2 ][ 3 ]; // 7 <- 8
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 2 ][ 3 ]; // 8 -> 9
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 1 ][ 3 ]; // 2 <- 3
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 3 ]; // 3 -> 4
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 3 ]; // 1 <- 2
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 0 ][ 3 ]; // 2 -> 3
assign back_data_in_o[ 5 ][ 3 ] = back_data_out_i[ 5 ][ 2 ]; // 15 <- 16
assign fwd_data_in_o [ 5 ][ 1 ] = fwd_data_out_i [ 5 ][ 2 ]; // 16 -> 17
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 4 ][ 2 ]; // 12 <- 13
assign fwd_data_in_o [ 4 ][ 3 ] = fwd_data_out_i [ 4 ][ 2 ]; // 13 -> 14
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 3 ][ 2 ]; // 9 <- 10
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 3 ][ 2 ]; // 10 -> 11
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 2 ][ 2 ]; // 6 <- 7
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 2 ][ 2 ]; // 7 -> 8
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 2 ]; // 3 <- 4
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 4 -> 5
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 5 ][ 2 ] = back_data_out_i[ 5 ][ 1 ]; // 16 <- 17
assign fwd_data_in_o [ 5 ][ 0 ] = fwd_data_out_i [ 5 ][ 1 ]; // 17 -> 18
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 4 ][ 1 ]; // 11 <- 12
assign fwd_data_in_o [ 4 ][ 2 ] = fwd_data_out_i [ 4 ][ 1 ]; // 12 -> 13
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 3 ][ 1 ]; // 10 <- 11
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 11 -> 12
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 5 <- 6
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 2 ][ 1 ]; // 6 -> 7
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 4 <- 5
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 5 -> 6
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 23 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 5 ][ 1 ] = back_data_out_i[ 5 ][ 0 ]; // 17 <- 18
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 5 ][ 0 ]; // 18 -> 19
assign back_data_in_o[ 5 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 18 <- 19
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 4 ][ 0 ]; // 19 -> 20
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 19 <- 20
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 20 -> 21
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 20 <- 21
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 21 -> 22
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 21 <- 22
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 22 -> 23
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 22 <- 23
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 23 -> 0
assign id_o =
{
// y = 0, 1, 2, 3,
{ b_lp ' (23) , b_lp ' (0) , b_lp ' (1) , b_lp ' (2) }, // x = 0
{ b_lp ' (22) , b_lp ' (5) , b_lp ' (4) , b_lp ' (3) }, // x = 1
{ b_lp ' (21) , b_lp ' (6) , b_lp ' (7) , b_lp ' (8) }, // x = 2
{ b_lp ' (20) , b_lp ' (11) , b_lp ' (10) , b_lp ' (9) }, // x = 3
{ b_lp ' (19) , b_lp ' (12) , b_lp ' (13) , b_lp ' (14) }, // x = 4
{ b_lp ' (18) , b_lp ' (17) , b_lp ' (16) , b_lp ' (15) } // x = 5
};
end
if (x_max_p == 6 && y_max_p == 5 )
begin
assign back_data_in_o[ 4 ][ 4 ] = back_data_out_i[ 5 ][ 4 ]; // 19 <- 20
assign fwd_data_in_o [ 5 ][ 3 ] = fwd_data_out_i [ 5 ][ 4 ]; // 20 -> 21
assign back_data_in_o[ 4 ][ 3 ] = back_data_out_i[ 4 ][ 4 ]; // 18 <- 19
assign fwd_data_in_o [ 5 ][ 4 ] = fwd_data_out_i [ 4 ][ 4 ]; // 19 -> 20
assign back_data_in_o[ 2 ][ 4 ] = back_data_out_i[ 3 ][ 4 ]; // 11 <- 12
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 3 ][ 4 ]; // 12 -> 13
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 2 ][ 4 ]; // 10 <- 11
assign fwd_data_in_o [ 3 ][ 4 ] = fwd_data_out_i [ 2 ][ 4 ]; // 11 -> 12
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 1 ][ 4 ]; // 3 <- 4
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 1 ][ 4 ]; // 4 -> 5
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 4 ]; // 2 <- 3
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 0 ][ 4 ]; // 3 -> 4
assign back_data_in_o[ 5 ][ 4 ] = back_data_out_i[ 5 ][ 3 ]; // 20 <- 21
assign fwd_data_in_o [ 5 ][ 2 ] = fwd_data_out_i [ 5 ][ 3 ]; // 21 -> 22
assign back_data_in_o[ 4 ][ 2 ] = back_data_out_i[ 4 ][ 3 ]; // 17 <- 18
assign fwd_data_in_o [ 4 ][ 4 ] = fwd_data_out_i [ 4 ][ 3 ]; // 18 -> 19
assign back_data_in_o[ 3 ][ 4 ] = back_data_out_i[ 3 ][ 3 ]; // 12 <- 13
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 3 ][ 3 ]; // 13 -> 14
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 2 ][ 3 ]; // 9 <- 10
assign fwd_data_in_o [ 2 ][ 4 ] = fwd_data_out_i [ 2 ][ 3 ]; // 10 -> 11
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 1 ][ 3 ]; // 4 <- 5
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 3 ]; // 5 -> 6
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 3 ]; // 1 <- 2
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 3 ]; // 2 -> 3
assign back_data_in_o[ 5 ][ 3 ] = back_data_out_i[ 5 ][ 2 ]; // 21 <- 22
assign fwd_data_in_o [ 5 ][ 1 ] = fwd_data_out_i [ 5 ][ 2 ]; // 22 -> 23
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 4 ][ 2 ]; // 16 <- 17
assign fwd_data_in_o [ 4 ][ 3 ] = fwd_data_out_i [ 4 ][ 2 ]; // 17 -> 18
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 3 ][ 2 ]; // 13 <- 14
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 3 ][ 2 ]; // 14 -> 15
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 2 ][ 2 ]; // 8 <- 9
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 2 ][ 2 ]; // 9 -> 10
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 2 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 6 -> 7
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 5 ][ 2 ] = back_data_out_i[ 5 ][ 1 ]; // 22 <- 23
assign fwd_data_in_o [ 5 ][ 0 ] = fwd_data_out_i [ 5 ][ 1 ]; // 23 -> 24
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 4 ][ 1 ]; // 15 <- 16
assign fwd_data_in_o [ 4 ][ 2 ] = fwd_data_out_i [ 4 ][ 1 ]; // 16 -> 17
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 3 ][ 1 ]; // 14 <- 15
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 15 -> 16
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 7 <- 8
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 2 ][ 1 ]; // 8 -> 9
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 6 <- 7
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 29 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 5 ][ 1 ] = back_data_out_i[ 5 ][ 0 ]; // 23 <- 24
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 5 ][ 0 ]; // 24 -> 25
assign back_data_in_o[ 5 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 24 <- 25
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 4 ][ 0 ]; // 25 -> 26
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 25 <- 26
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 26 -> 27
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 26 <- 27
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 27 -> 28
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 27 <- 28
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 28 -> 29
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 28 <- 29
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 29 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4,
{ b_lp ' (29) , b_lp ' (0) , b_lp ' (1) , b_lp ' (2) , b_lp ' (3) }, // x = 0
{ b_lp ' (28) , b_lp ' (7) , b_lp ' (6) , b_lp ' (5) , b_lp ' (4) }, // x = 1
{ b_lp ' (27) , b_lp ' (8) , b_lp ' (9) , b_lp ' (10) , b_lp ' (11) }, // x = 2
{ b_lp ' (26) , b_lp ' (15) , b_lp ' (14) , b_lp ' (13) , b_lp ' (12) }, // x = 3
{ b_lp ' (25) , b_lp ' (16) , b_lp ' (17) , b_lp ' (18) , b_lp ' (19) }, // x = 4
{ b_lp ' (24) , b_lp ' (23) , b_lp ' (22) , b_lp ' (21) , b_lp ' (20) } // x = 5
};
end
if (x_max_p == 6 && y_max_p == 6 )
begin
assign back_data_in_o[ 4 ][ 5 ] = back_data_out_i[ 5 ][ 5 ]; // 24 <- 25
assign fwd_data_in_o [ 5 ][ 4 ] = fwd_data_out_i [ 5 ][ 5 ]; // 25 -> 26
assign back_data_in_o[ 4 ][ 4 ] = back_data_out_i[ 4 ][ 5 ]; // 23 <- 24
assign fwd_data_in_o [ 5 ][ 5 ] = fwd_data_out_i [ 4 ][ 5 ]; // 24 -> 25
assign back_data_in_o[ 2 ][ 5 ] = back_data_out_i[ 3 ][ 5 ]; // 14 <- 15
assign fwd_data_in_o [ 3 ][ 4 ] = fwd_data_out_i [ 3 ][ 5 ]; // 15 -> 16
assign back_data_in_o[ 2 ][ 4 ] = back_data_out_i[ 2 ][ 5 ]; // 13 <- 14
assign fwd_data_in_o [ 3 ][ 5 ] = fwd_data_out_i [ 2 ][ 5 ]; // 14 -> 15
assign back_data_in_o[ 0 ][ 5 ] = back_data_out_i[ 1 ][ 5 ]; // 4 <- 5
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 1 ][ 5 ]; // 5 -> 6
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 0 ][ 5 ]; // 3 <- 4
assign fwd_data_in_o [ 1 ][ 5 ] = fwd_data_out_i [ 0 ][ 5 ]; // 4 -> 5
assign back_data_in_o[ 5 ][ 5 ] = back_data_out_i[ 5 ][ 4 ]; // 25 <- 26
assign fwd_data_in_o [ 5 ][ 3 ] = fwd_data_out_i [ 5 ][ 4 ]; // 26 -> 27
assign back_data_in_o[ 4 ][ 3 ] = back_data_out_i[ 4 ][ 4 ]; // 22 <- 23
assign fwd_data_in_o [ 4 ][ 5 ] = fwd_data_out_i [ 4 ][ 4 ]; // 23 -> 24
assign back_data_in_o[ 3 ][ 5 ] = back_data_out_i[ 3 ][ 4 ]; // 15 <- 16
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 3 ][ 4 ]; // 16 -> 17
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 2 ][ 4 ]; // 12 <- 13
assign fwd_data_in_o [ 2 ][ 5 ] = fwd_data_out_i [ 2 ][ 4 ]; // 13 -> 14
assign back_data_in_o[ 1 ][ 5 ] = back_data_out_i[ 1 ][ 4 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 1 ][ 4 ]; // 6 -> 7
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 4 ]; // 2 <- 3
assign fwd_data_in_o [ 0 ][ 5 ] = fwd_data_out_i [ 0 ][ 4 ]; // 3 -> 4
assign back_data_in_o[ 5 ][ 4 ] = back_data_out_i[ 5 ][ 3 ]; // 26 <- 27
assign fwd_data_in_o [ 5 ][ 2 ] = fwd_data_out_i [ 5 ][ 3 ]; // 27 -> 28
assign back_data_in_o[ 4 ][ 2 ] = back_data_out_i[ 4 ][ 3 ]; // 21 <- 22
assign fwd_data_in_o [ 4 ][ 4 ] = fwd_data_out_i [ 4 ][ 3 ]; // 22 -> 23
assign back_data_in_o[ 3 ][ 4 ] = back_data_out_i[ 3 ][ 3 ]; // 16 <- 17
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 3 ][ 3 ]; // 17 -> 18
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 2 ][ 3 ]; // 11 <- 12
assign fwd_data_in_o [ 2 ][ 4 ] = fwd_data_out_i [ 2 ][ 3 ]; // 12 -> 13
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 1 ][ 3 ]; // 6 <- 7
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 3 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 3 ]; // 1 <- 2
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 3 ]; // 2 -> 3
assign back_data_in_o[ 5 ][ 3 ] = back_data_out_i[ 5 ][ 2 ]; // 27 <- 28
assign fwd_data_in_o [ 5 ][ 1 ] = fwd_data_out_i [ 5 ][ 2 ]; // 28 -> 29
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 4 ][ 2 ]; // 20 <- 21
assign fwd_data_in_o [ 4 ][ 3 ] = fwd_data_out_i [ 4 ][ 2 ]; // 21 -> 22
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 3 ][ 2 ]; // 17 <- 18
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 3 ][ 2 ]; // 18 -> 19
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 2 ][ 2 ]; // 10 <- 11
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 2 ][ 2 ]; // 11 -> 12
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 2 ]; // 7 <- 8
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 8 -> 9
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 5 ][ 2 ] = back_data_out_i[ 5 ][ 1 ]; // 28 <- 29
assign fwd_data_in_o [ 5 ][ 0 ] = fwd_data_out_i [ 5 ][ 1 ]; // 29 -> 30
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 4 ][ 1 ]; // 19 <- 20
assign fwd_data_in_o [ 4 ][ 2 ] = fwd_data_out_i [ 4 ][ 1 ]; // 20 -> 21
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 3 ][ 1 ]; // 18 <- 19
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 19 -> 20
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 9 <- 10
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 2 ][ 1 ]; // 10 -> 11
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 8 <- 9
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 9 -> 10
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 35 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 5 ][ 1 ] = back_data_out_i[ 5 ][ 0 ]; // 29 <- 30
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 5 ][ 0 ]; // 30 -> 31
assign back_data_in_o[ 5 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 30 <- 31
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 4 ][ 0 ]; // 31 -> 32
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 31 <- 32
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 32 -> 33
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 32 <- 33
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 33 -> 34
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 33 <- 34
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 34 -> 35
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 34 <- 35
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 35 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4, 5,
{ b_lp ' (35) , b_lp ' (0) , b_lp ' (1) , b_lp ' (2) , b_lp ' (3) , b_lp ' (4) }, // x = 0
{ b_lp ' (34) , b_lp ' (9) , b_lp ' (8) , b_lp ' (7) , b_lp ' (6) , b_lp ' (5) }, // x = 1
{ b_lp ' (33) , b_lp ' (10) , b_lp ' (11) , b_lp ' (12) , b_lp ' (13) , b_lp ' (14) }, // x = 2
{ b_lp ' (32) , b_lp ' (19) , b_lp ' (18) , b_lp ' (17) , b_lp ' (16) , b_lp ' (15) }, // x = 3
{ b_lp ' (31) , b_lp ' (20) , b_lp ' (21) , b_lp ' (22) , b_lp ' (23) , b_lp ' (24) }, // x = 4
{ b_lp ' (30) , b_lp ' (29) , b_lp ' (28) , b_lp ' (27) , b_lp ' (26) , b_lp ' (25) } // x = 5
};
end
if (x_max_p == 6 && y_max_p == 7 )
begin
assign back_data_in_o[ 4 ][ 6 ] = back_data_out_i[ 5 ][ 6 ]; // 29 <- 30
assign fwd_data_in_o [ 5 ][ 5 ] = fwd_data_out_i [ 5 ][ 6 ]; // 30 -> 31
assign back_data_in_o[ 4 ][ 5 ] = back_data_out_i[ 4 ][ 6 ]; // 28 <- 29
assign fwd_data_in_o [ 5 ][ 6 ] = fwd_data_out_i [ 4 ][ 6 ]; // 29 -> 30
assign back_data_in_o[ 2 ][ 6 ] = back_data_out_i[ 3 ][ 6 ]; // 17 <- 18
assign fwd_data_in_o [ 3 ][ 5 ] = fwd_data_out_i [ 3 ][ 6 ]; // 18 -> 19
assign back_data_in_o[ 2 ][ 5 ] = back_data_out_i[ 2 ][ 6 ]; // 16 <- 17
assign fwd_data_in_o [ 3 ][ 6 ] = fwd_data_out_i [ 2 ][ 6 ]; // 17 -> 18
assign back_data_in_o[ 0 ][ 6 ] = back_data_out_i[ 1 ][ 6 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 5 ] = fwd_data_out_i [ 1 ][ 6 ]; // 6 -> 7
assign back_data_in_o[ 0 ][ 5 ] = back_data_out_i[ 0 ][ 6 ]; // 4 <- 5
assign fwd_data_in_o [ 1 ][ 6 ] = fwd_data_out_i [ 0 ][ 6 ]; // 5 -> 6
assign back_data_in_o[ 5 ][ 6 ] = back_data_out_i[ 5 ][ 5 ]; // 30 <- 31
assign fwd_data_in_o [ 5 ][ 4 ] = fwd_data_out_i [ 5 ][ 5 ]; // 31 -> 32
assign back_data_in_o[ 4 ][ 4 ] = back_data_out_i[ 4 ][ 5 ]; // 27 <- 28
assign fwd_data_in_o [ 4 ][ 6 ] = fwd_data_out_i [ 4 ][ 5 ]; // 28 -> 29
assign back_data_in_o[ 3 ][ 6 ] = back_data_out_i[ 3 ][ 5 ]; // 18 <- 19
assign fwd_data_in_o [ 3 ][ 4 ] = fwd_data_out_i [ 3 ][ 5 ]; // 19 -> 20
assign back_data_in_o[ 2 ][ 4 ] = back_data_out_i[ 2 ][ 5 ]; // 15 <- 16
assign fwd_data_in_o [ 2 ][ 6 ] = fwd_data_out_i [ 2 ][ 5 ]; // 16 -> 17
assign back_data_in_o[ 1 ][ 6 ] = back_data_out_i[ 1 ][ 5 ]; // 6 <- 7
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 1 ][ 5 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 0 ][ 5 ]; // 3 <- 4
assign fwd_data_in_o [ 0 ][ 6 ] = fwd_data_out_i [ 0 ][ 5 ]; // 4 -> 5
assign back_data_in_o[ 5 ][ 5 ] = back_data_out_i[ 5 ][ 4 ]; // 31 <- 32
assign fwd_data_in_o [ 5 ][ 3 ] = fwd_data_out_i [ 5 ][ 4 ]; // 32 -> 33
assign back_data_in_o[ 4 ][ 3 ] = back_data_out_i[ 4 ][ 4 ]; // 26 <- 27
assign fwd_data_in_o [ 4 ][ 5 ] = fwd_data_out_i [ 4 ][ 4 ]; // 27 -> 28
assign back_data_in_o[ 3 ][ 5 ] = back_data_out_i[ 3 ][ 4 ]; // 19 <- 20
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 3 ][ 4 ]; // 20 -> 21
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 2 ][ 4 ]; // 14 <- 15
assign fwd_data_in_o [ 2 ][ 5 ] = fwd_data_out_i [ 2 ][ 4 ]; // 15 -> 16
assign back_data_in_o[ 1 ][ 5 ] = back_data_out_i[ 1 ][ 4 ]; // 7 <- 8
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 1 ][ 4 ]; // 8 -> 9
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 4 ]; // 2 <- 3
assign fwd_data_in_o [ 0 ][ 5 ] = fwd_data_out_i [ 0 ][ 4 ]; // 3 -> 4
assign back_data_in_o[ 5 ][ 4 ] = back_data_out_i[ 5 ][ 3 ]; // 32 <- 33
assign fwd_data_in_o [ 5 ][ 2 ] = fwd_data_out_i [ 5 ][ 3 ]; // 33 -> 34
assign back_data_in_o[ 4 ][ 2 ] = back_data_out_i[ 4 ][ 3 ]; // 25 <- 26
assign fwd_data_in_o [ 4 ][ 4 ] = fwd_data_out_i [ 4 ][ 3 ]; // 26 -> 27
assign back_data_in_o[ 3 ][ 4 ] = back_data_out_i[ 3 ][ 3 ]; // 20 <- 21
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 3 ][ 3 ]; // 21 -> 22
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 2 ][ 3 ]; // 13 <- 14
assign fwd_data_in_o [ 2 ][ 4 ] = fwd_data_out_i [ 2 ][ 3 ]; // 14 -> 15
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 1 ][ 3 ]; // 8 <- 9
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 3 ]; // 9 -> 10
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 3 ]; // 1 <- 2
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 3 ]; // 2 -> 3
assign back_data_in_o[ 5 ][ 3 ] = back_data_out_i[ 5 ][ 2 ]; // 33 <- 34
assign fwd_data_in_o [ 5 ][ 1 ] = fwd_data_out_i [ 5 ][ 2 ]; // 34 -> 35
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 4 ][ 2 ]; // 24 <- 25
assign fwd_data_in_o [ 4 ][ 3 ] = fwd_data_out_i [ 4 ][ 2 ]; // 25 -> 26
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 3 ][ 2 ]; // 21 <- 22
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 3 ][ 2 ]; // 22 -> 23
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 2 ][ 2 ]; // 12 <- 13
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 2 ][ 2 ]; // 13 -> 14
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 2 ]; // 9 <- 10
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 10 -> 11
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 5 ][ 2 ] = back_data_out_i[ 5 ][ 1 ]; // 34 <- 35
assign fwd_data_in_o [ 5 ][ 0 ] = fwd_data_out_i [ 5 ][ 1 ]; // 35 -> 36
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 4 ][ 1 ]; // 23 <- 24
assign fwd_data_in_o [ 4 ][ 2 ] = fwd_data_out_i [ 4 ][ 1 ]; // 24 -> 25
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 3 ][ 1 ]; // 22 <- 23
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 23 -> 24
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 11 <- 12
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 2 ][ 1 ]; // 12 -> 13
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 10 <- 11
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 11 -> 12
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 41 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 5 ][ 1 ] = back_data_out_i[ 5 ][ 0 ]; // 35 <- 36
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 5 ][ 0 ]; // 36 -> 37
assign back_data_in_o[ 5 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 36 <- 37
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 4 ][ 0 ]; // 37 -> 38
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 37 <- 38
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 38 -> 39
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 38 <- 39
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 39 -> 40
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 39 <- 40
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 40 -> 41
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 40 <- 41
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 41 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4, 5, 6,
{ b_lp ' (41) , b_lp ' (0) , b_lp ' (1) , b_lp ' (2) , b_lp ' (3) , b_lp ' (4) , b_lp ' (5) }, // x = 0
{ b_lp ' (40) , b_lp ' (11) , b_lp ' (10) , b_lp ' (9) , b_lp ' (8) , b_lp ' (7) , b_lp ' (6) }, // x = 1
{ b_lp ' (39) , b_lp ' (12) , b_lp ' (13) , b_lp ' (14) , b_lp ' (15) , b_lp ' (16) , b_lp ' (17) }, // x = 2
{ b_lp ' (38) , b_lp ' (23) , b_lp ' (22) , b_lp ' (21) , b_lp ' (20) , b_lp ' (19) , b_lp ' (18) }, // x = 3
{ b_lp ' (37) , b_lp ' (24) , b_lp ' (25) , b_lp ' (26) , b_lp ' (27) , b_lp ' (28) , b_lp ' (29) }, // x = 4
{ b_lp ' (36) , b_lp ' (35) , b_lp ' (34) , b_lp ' (33) , b_lp ' (32) , b_lp ' (31) , b_lp ' (30) } // x = 5
};
end
if (x_max_p == 6 && y_max_p == 8 )
begin
assign back_data_in_o[ 4 ][ 7 ] = back_data_out_i[ 5 ][ 7 ]; // 34 <- 35
assign fwd_data_in_o [ 5 ][ 6 ] = fwd_data_out_i [ 5 ][ 7 ]; // 35 -> 36
assign back_data_in_o[ 4 ][ 6 ] = back_data_out_i[ 4 ][ 7 ]; // 33 <- 34
assign fwd_data_in_o [ 5 ][ 7 ] = fwd_data_out_i [ 4 ][ 7 ]; // 34 -> 35
assign back_data_in_o[ 2 ][ 7 ] = back_data_out_i[ 3 ][ 7 ]; // 20 <- 21
assign fwd_data_in_o [ 3 ][ 6 ] = fwd_data_out_i [ 3 ][ 7 ]; // 21 -> 22
assign back_data_in_o[ 2 ][ 6 ] = back_data_out_i[ 2 ][ 7 ]; // 19 <- 20
assign fwd_data_in_o [ 3 ][ 7 ] = fwd_data_out_i [ 2 ][ 7 ]; // 20 -> 21
assign back_data_in_o[ 0 ][ 7 ] = back_data_out_i[ 1 ][ 7 ]; // 6 <- 7
assign fwd_data_in_o [ 1 ][ 6 ] = fwd_data_out_i [ 1 ][ 7 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 6 ] = back_data_out_i[ 0 ][ 7 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 7 ] = fwd_data_out_i [ 0 ][ 7 ]; // 6 -> 7
assign back_data_in_o[ 5 ][ 7 ] = back_data_out_i[ 5 ][ 6 ]; // 35 <- 36
assign fwd_data_in_o [ 5 ][ 5 ] = fwd_data_out_i [ 5 ][ 6 ]; // 36 -> 37
assign back_data_in_o[ 4 ][ 5 ] = back_data_out_i[ 4 ][ 6 ]; // 32 <- 33
assign fwd_data_in_o [ 4 ][ 7 ] = fwd_data_out_i [ 4 ][ 6 ]; // 33 -> 34
assign back_data_in_o[ 3 ][ 7 ] = back_data_out_i[ 3 ][ 6 ]; // 21 <- 22
assign fwd_data_in_o [ 3 ][ 5 ] = fwd_data_out_i [ 3 ][ 6 ]; // 22 -> 23
assign back_data_in_o[ 2 ][ 5 ] = back_data_out_i[ 2 ][ 6 ]; // 18 <- 19
assign fwd_data_in_o [ 2 ][ 7 ] = fwd_data_out_i [ 2 ][ 6 ]; // 19 -> 20
assign back_data_in_o[ 1 ][ 7 ] = back_data_out_i[ 1 ][ 6 ]; // 7 <- 8
assign fwd_data_in_o [ 1 ][ 5 ] = fwd_data_out_i [ 1 ][ 6 ]; // 8 -> 9
assign back_data_in_o[ 0 ][ 5 ] = back_data_out_i[ 0 ][ 6 ]; // 4 <- 5
assign fwd_data_in_o [ 0 ][ 7 ] = fwd_data_out_i [ 0 ][ 6 ]; // 5 -> 6
assign back_data_in_o[ 5 ][ 6 ] = back_data_out_i[ 5 ][ 5 ]; // 36 <- 37
assign fwd_data_in_o [ 5 ][ 4 ] = fwd_data_out_i [ 5 ][ 5 ]; // 37 -> 38
assign back_data_in_o[ 4 ][ 4 ] = back_data_out_i[ 4 ][ 5 ]; // 31 <- 32
assign fwd_data_in_o [ 4 ][ 6 ] = fwd_data_out_i [ 4 ][ 5 ]; // 32 -> 33
assign back_data_in_o[ 3 ][ 6 ] = back_data_out_i[ 3 ][ 5 ]; // 22 <- 23
assign fwd_data_in_o [ 3 ][ 4 ] = fwd_data_out_i [ 3 ][ 5 ]; // 23 -> 24
assign back_data_in_o[ 2 ][ 4 ] = back_data_out_i[ 2 ][ 5 ]; // 17 <- 18
assign fwd_data_in_o [ 2 ][ 6 ] = fwd_data_out_i [ 2 ][ 5 ]; // 18 -> 19
assign back_data_in_o[ 1 ][ 6 ] = back_data_out_i[ 1 ][ 5 ]; // 8 <- 9
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 1 ][ 5 ]; // 9 -> 10
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 0 ][ 5 ]; // 3 <- 4
assign fwd_data_in_o [ 0 ][ 6 ] = fwd_data_out_i [ 0 ][ 5 ]; // 4 -> 5
assign back_data_in_o[ 5 ][ 5 ] = back_data_out_i[ 5 ][ 4 ]; // 37 <- 38
assign fwd_data_in_o [ 5 ][ 3 ] = fwd_data_out_i [ 5 ][ 4 ]; // 38 -> 39
assign back_data_in_o[ 4 ][ 3 ] = back_data_out_i[ 4 ][ 4 ]; // 30 <- 31
assign fwd_data_in_o [ 4 ][ 5 ] = fwd_data_out_i [ 4 ][ 4 ]; // 31 -> 32
assign back_data_in_o[ 3 ][ 5 ] = back_data_out_i[ 3 ][ 4 ]; // 23 <- 24
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 3 ][ 4 ]; // 24 -> 25
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 2 ][ 4 ]; // 16 <- 17
assign fwd_data_in_o [ 2 ][ 5 ] = fwd_data_out_i [ 2 ][ 4 ]; // 17 -> 18
assign back_data_in_o[ 1 ][ 5 ] = back_data_out_i[ 1 ][ 4 ]; // 9 <- 10
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 1 ][ 4 ]; // 10 -> 11
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 4 ]; // 2 <- 3
assign fwd_data_in_o [ 0 ][ 5 ] = fwd_data_out_i [ 0 ][ 4 ]; // 3 -> 4
assign back_data_in_o[ 5 ][ 4 ] = back_data_out_i[ 5 ][ 3 ]; // 38 <- 39
assign fwd_data_in_o [ 5 ][ 2 ] = fwd_data_out_i [ 5 ][ 3 ]; // 39 -> 40
assign back_data_in_o[ 4 ][ 2 ] = back_data_out_i[ 4 ][ 3 ]; // 29 <- 30
assign fwd_data_in_o [ 4 ][ 4 ] = fwd_data_out_i [ 4 ][ 3 ]; // 30 -> 31
assign back_data_in_o[ 3 ][ 4 ] = back_data_out_i[ 3 ][ 3 ]; // 24 <- 25
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 3 ][ 3 ]; // 25 -> 26
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 2 ][ 3 ]; // 15 <- 16
assign fwd_data_in_o [ 2 ][ 4 ] = fwd_data_out_i [ 2 ][ 3 ]; // 16 -> 17
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 1 ][ 3 ]; // 10 <- 11
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 3 ]; // 11 -> 12
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 3 ]; // 1 <- 2
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 3 ]; // 2 -> 3
assign back_data_in_o[ 5 ][ 3 ] = back_data_out_i[ 5 ][ 2 ]; // 39 <- 40
assign fwd_data_in_o [ 5 ][ 1 ] = fwd_data_out_i [ 5 ][ 2 ]; // 40 -> 41
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 4 ][ 2 ]; // 28 <- 29
assign fwd_data_in_o [ 4 ][ 3 ] = fwd_data_out_i [ 4 ][ 2 ]; // 29 -> 30
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 3 ][ 2 ]; // 25 <- 26
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 3 ][ 2 ]; // 26 -> 27
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 2 ][ 2 ]; // 14 <- 15
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 2 ][ 2 ]; // 15 -> 16
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 2 ]; // 11 <- 12
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 12 -> 13
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 5 ][ 2 ] = back_data_out_i[ 5 ][ 1 ]; // 40 <- 41
assign fwd_data_in_o [ 5 ][ 0 ] = fwd_data_out_i [ 5 ][ 1 ]; // 41 -> 42
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 4 ][ 1 ]; // 27 <- 28
assign fwd_data_in_o [ 4 ][ 2 ] = fwd_data_out_i [ 4 ][ 1 ]; // 28 -> 29
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 3 ][ 1 ]; // 26 <- 27
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 27 -> 28
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 13 <- 14
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 2 ][ 1 ]; // 14 -> 15
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 12 <- 13
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 13 -> 14
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 47 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 5 ][ 1 ] = back_data_out_i[ 5 ][ 0 ]; // 41 <- 42
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 5 ][ 0 ]; // 42 -> 43
assign back_data_in_o[ 5 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 42 <- 43
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 4 ][ 0 ]; // 43 -> 44
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 43 <- 44
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 44 -> 45
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 44 <- 45
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 45 -> 46
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 45 <- 46
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 46 -> 47
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 46 <- 47
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 47 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4, 5, 6, 7,
{ b_lp ' (47) , b_lp ' (0) , b_lp ' (1) , b_lp ' (2) , b_lp ' (3) , b_lp ' (4) , b_lp ' (5) , b_lp ' (6) }, // x = 0
{ b_lp ' (46) , b_lp ' (13) , b_lp ' (12) , b_lp ' (11) , b_lp ' (10) , b_lp ' (9) , b_lp ' (8) , b_lp ' (7) }, // x = 1
{ b_lp ' (45) , b_lp ' (14) , b_lp ' (15) , b_lp ' (16) , b_lp ' (17) , b_lp ' (18) , b_lp ' (19) , b_lp ' (20) }, // x = 2
{ b_lp ' (44) , b_lp ' (27) , b_lp ' (26) , b_lp ' (25) , b_lp ' (24) , b_lp ' (23) , b_lp ' (22) , b_lp ' (21) }, // x = 3
{ b_lp ' (43) , b_lp ' (28) , b_lp ' (29) , b_lp ' (30) , b_lp ' (31) , b_lp ' (32) , b_lp ' (33) , b_lp ' (34) }, // x = 4
{ b_lp ' (42) , b_lp ' (41) , b_lp ' (40) , b_lp ' (39) , b_lp ' (38) , b_lp ' (37) , b_lp ' (36) , b_lp ' (35) } // x = 5
};
end
if (x_max_p == 8 && y_max_p == 2 )
begin
assign back_data_in_o[ 6 ][ 1 ] = back_data_out_i[ 7 ][ 1 ]; // 6 <- 7
assign fwd_data_in_o [ 7 ][ 0 ] = fwd_data_out_i [ 7 ][ 1 ]; // 7 -> 8
assign back_data_in_o[ 5 ][ 1 ] = back_data_out_i[ 6 ][ 1 ]; // 5 <- 6
assign fwd_data_in_o [ 7 ][ 1 ] = fwd_data_out_i [ 6 ][ 1 ]; // 6 -> 7
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 5 ][ 1 ]; // 4 <- 5
assign fwd_data_in_o [ 6 ][ 1 ] = fwd_data_out_i [ 5 ][ 1 ]; // 5 -> 6
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 4 ][ 1 ]; // 3 <- 4
assign fwd_data_in_o [ 5 ][ 1 ] = fwd_data_out_i [ 4 ][ 1 ]; // 4 -> 5
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 3 ][ 1 ]; // 2 <- 3
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 3 -> 4
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 1 <- 2
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 2 ][ 1 ]; // 2 -> 3
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 1 ][ 1 ]; // 0 <- 1
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 1 -> 2
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 15 <- 0
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 7 ][ 1 ] = back_data_out_i[ 7 ][ 0 ]; // 7 <- 8
assign fwd_data_in_o [ 6 ][ 0 ] = fwd_data_out_i [ 7 ][ 0 ]; // 8 -> 9
assign back_data_in_o[ 7 ][ 0 ] = back_data_out_i[ 6 ][ 0 ]; // 8 <- 9
assign fwd_data_in_o [ 5 ][ 0 ] = fwd_data_out_i [ 6 ][ 0 ]; // 9 -> 10
assign back_data_in_o[ 6 ][ 0 ] = back_data_out_i[ 5 ][ 0 ]; // 9 <- 10
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 5 ][ 0 ]; // 10 -> 11
assign back_data_in_o[ 5 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 10 <- 11
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 4 ][ 0 ]; // 11 -> 12
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 11 <- 12
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 12 -> 13
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 12 <- 13
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 13 -> 14
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 13 <- 14
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 14 -> 15
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 14 <- 15
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 15 -> 0
assign id_o =
{
// y = 0, 1,
{ b_lp ' (15) , b_lp ' (0) }, // x = 0
{ b_lp ' (14) , b_lp ' (1) }, // x = 1
{ b_lp ' (13) , b_lp ' (2) }, // x = 2
{ b_lp ' (12) , b_lp ' (3) }, // x = 3
{ b_lp ' (11) , b_lp ' (4) }, // x = 4
{ b_lp ' (10) , b_lp ' (5) }, // x = 5
{ b_lp ' (9) , b_lp ' (6) }, // x = 6
{ b_lp ' (8) , b_lp ' (7) } // x = 7
};
end
if (x_max_p == 8 && y_max_p == 3 )
begin
assign back_data_in_o[ 6 ][ 2 ] = back_data_out_i[ 7 ][ 2 ]; // 13 <- 14
assign fwd_data_in_o [ 7 ][ 1 ] = fwd_data_out_i [ 7 ][ 2 ]; // 14 -> 15
assign back_data_in_o[ 6 ][ 1 ] = back_data_out_i[ 6 ][ 2 ]; // 12 <- 13
assign fwd_data_in_o [ 7 ][ 2 ] = fwd_data_out_i [ 6 ][ 2 ]; // 13 -> 14
assign back_data_in_o[ 4 ][ 2 ] = back_data_out_i[ 5 ][ 2 ]; // 9 <- 10
assign fwd_data_in_o [ 5 ][ 1 ] = fwd_data_out_i [ 5 ][ 2 ]; // 10 -> 11
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 4 ][ 2 ]; // 8 <- 9
assign fwd_data_in_o [ 5 ][ 2 ] = fwd_data_out_i [ 4 ][ 2 ]; // 9 -> 10
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 3 ][ 2 ]; // 5 <- 6
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 3 ][ 2 ]; // 6 -> 7
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 2 ][ 2 ]; // 4 <- 5
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 2 ][ 2 ]; // 5 -> 6
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 1 ][ 2 ]; // 1 <- 2
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 2 -> 3
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 7 ][ 2 ] = back_data_out_i[ 7 ][ 1 ]; // 14 <- 15
assign fwd_data_in_o [ 7 ][ 0 ] = fwd_data_out_i [ 7 ][ 1 ]; // 15 -> 16
assign back_data_in_o[ 5 ][ 1 ] = back_data_out_i[ 6 ][ 1 ]; // 11 <- 12
assign fwd_data_in_o [ 6 ][ 2 ] = fwd_data_out_i [ 6 ][ 1 ]; // 12 -> 13
assign back_data_in_o[ 5 ][ 2 ] = back_data_out_i[ 5 ][ 1 ]; // 10 <- 11
assign fwd_data_in_o [ 6 ][ 1 ] = fwd_data_out_i [ 5 ][ 1 ]; // 11 -> 12
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 4 ][ 1 ]; // 7 <- 8
assign fwd_data_in_o [ 4 ][ 2 ] = fwd_data_out_i [ 4 ][ 1 ]; // 8 -> 9
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 3 ][ 1 ]; // 6 <- 7
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 7 -> 8
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 3 <- 4
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 2 ][ 1 ]; // 4 -> 5
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 2 <- 3
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 3 -> 4
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 23 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 7 ][ 1 ] = back_data_out_i[ 7 ][ 0 ]; // 15 <- 16
assign fwd_data_in_o [ 6 ][ 0 ] = fwd_data_out_i [ 7 ][ 0 ]; // 16 -> 17
assign back_data_in_o[ 7 ][ 0 ] = back_data_out_i[ 6 ][ 0 ]; // 16 <- 17
assign fwd_data_in_o [ 5 ][ 0 ] = fwd_data_out_i [ 6 ][ 0 ]; // 17 -> 18
assign back_data_in_o[ 6 ][ 0 ] = back_data_out_i[ 5 ][ 0 ]; // 17 <- 18
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 5 ][ 0 ]; // 18 -> 19
assign back_data_in_o[ 5 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 18 <- 19
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 4 ][ 0 ]; // 19 -> 20
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 19 <- 20
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 20 -> 21
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 20 <- 21
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 21 -> 22
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 21 <- 22
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 22 -> 23
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 22 <- 23
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 23 -> 0
assign id_o =
{
// y = 0, 1, 2,
{ b_lp ' (23) , b_lp ' (0) , b_lp ' (1) }, // x = 0
{ b_lp ' (22) , b_lp ' (3) , b_lp ' (2) }, // x = 1
{ b_lp ' (21) , b_lp ' (4) , b_lp ' (5) }, // x = 2
{ b_lp ' (20) , b_lp ' (7) , b_lp ' (6) }, // x = 3
{ b_lp ' (19) , b_lp ' (8) , b_lp ' (9) }, // x = 4
{ b_lp ' (18) , b_lp ' (11) , b_lp ' (10) }, // x = 5
{ b_lp ' (17) , b_lp ' (12) , b_lp ' (13) }, // x = 6
{ b_lp ' (16) , b_lp ' (15) , b_lp ' (14) } // x = 7
};
end
if (x_max_p == 8 && y_max_p == 4 )
begin
assign back_data_in_o[ 6 ][ 3 ] = back_data_out_i[ 7 ][ 3 ]; // 20 <- 21
assign fwd_data_in_o [ 7 ][ 2 ] = fwd_data_out_i [ 7 ][ 3 ]; // 21 -> 22
assign back_data_in_o[ 6 ][ 2 ] = back_data_out_i[ 6 ][ 3 ]; // 19 <- 20
assign fwd_data_in_o [ 7 ][ 3 ] = fwd_data_out_i [ 6 ][ 3 ]; // 20 -> 21
assign back_data_in_o[ 4 ][ 3 ] = back_data_out_i[ 5 ][ 3 ]; // 14 <- 15
assign fwd_data_in_o [ 5 ][ 2 ] = fwd_data_out_i [ 5 ][ 3 ]; // 15 -> 16
assign back_data_in_o[ 4 ][ 2 ] = back_data_out_i[ 4 ][ 3 ]; // 13 <- 14
assign fwd_data_in_o [ 5 ][ 3 ] = fwd_data_out_i [ 4 ][ 3 ]; // 14 -> 15
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 3 ][ 3 ]; // 8 <- 9
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 3 ][ 3 ]; // 9 -> 10
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 2 ][ 3 ]; // 7 <- 8
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 2 ][ 3 ]; // 8 -> 9
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 1 ][ 3 ]; // 2 <- 3
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 3 ]; // 3 -> 4
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 3 ]; // 1 <- 2
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 0 ][ 3 ]; // 2 -> 3
assign back_data_in_o[ 7 ][ 3 ] = back_data_out_i[ 7 ][ 2 ]; // 21 <- 22
assign fwd_data_in_o [ 7 ][ 1 ] = fwd_data_out_i [ 7 ][ 2 ]; // 22 -> 23
assign back_data_in_o[ 6 ][ 1 ] = back_data_out_i[ 6 ][ 2 ]; // 18 <- 19
assign fwd_data_in_o [ 6 ][ 3 ] = fwd_data_out_i [ 6 ][ 2 ]; // 19 -> 20
assign back_data_in_o[ 5 ][ 3 ] = back_data_out_i[ 5 ][ 2 ]; // 15 <- 16
assign fwd_data_in_o [ 5 ][ 1 ] = fwd_data_out_i [ 5 ][ 2 ]; // 16 -> 17
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 4 ][ 2 ]; // 12 <- 13
assign fwd_data_in_o [ 4 ][ 3 ] = fwd_data_out_i [ 4 ][ 2 ]; // 13 -> 14
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 3 ][ 2 ]; // 9 <- 10
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 3 ][ 2 ]; // 10 -> 11
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 2 ][ 2 ]; // 6 <- 7
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 2 ][ 2 ]; // 7 -> 8
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 2 ]; // 3 <- 4
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 4 -> 5
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 7 ][ 2 ] = back_data_out_i[ 7 ][ 1 ]; // 22 <- 23
assign fwd_data_in_o [ 7 ][ 0 ] = fwd_data_out_i [ 7 ][ 1 ]; // 23 -> 24
assign back_data_in_o[ 5 ][ 1 ] = back_data_out_i[ 6 ][ 1 ]; // 17 <- 18
assign fwd_data_in_o [ 6 ][ 2 ] = fwd_data_out_i [ 6 ][ 1 ]; // 18 -> 19
assign back_data_in_o[ 5 ][ 2 ] = back_data_out_i[ 5 ][ 1 ]; // 16 <- 17
assign fwd_data_in_o [ 6 ][ 1 ] = fwd_data_out_i [ 5 ][ 1 ]; // 17 -> 18
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 4 ][ 1 ]; // 11 <- 12
assign fwd_data_in_o [ 4 ][ 2 ] = fwd_data_out_i [ 4 ][ 1 ]; // 12 -> 13
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 3 ][ 1 ]; // 10 <- 11
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 11 -> 12
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 5 <- 6
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 2 ][ 1 ]; // 6 -> 7
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 4 <- 5
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 5 -> 6
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 31 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 7 ][ 1 ] = back_data_out_i[ 7 ][ 0 ]; // 23 <- 24
assign fwd_data_in_o [ 6 ][ 0 ] = fwd_data_out_i [ 7 ][ 0 ]; // 24 -> 25
assign back_data_in_o[ 7 ][ 0 ] = back_data_out_i[ 6 ][ 0 ]; // 24 <- 25
assign fwd_data_in_o [ 5 ][ 0 ] = fwd_data_out_i [ 6 ][ 0 ]; // 25 -> 26
assign back_data_in_o[ 6 ][ 0 ] = back_data_out_i[ 5 ][ 0 ]; // 25 <- 26
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 5 ][ 0 ]; // 26 -> 27
assign back_data_in_o[ 5 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 26 <- 27
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 4 ][ 0 ]; // 27 -> 28
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 27 <- 28
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 28 -> 29
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 28 <- 29
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 29 -> 30
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 29 <- 30
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 30 -> 31
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 30 <- 31
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 31 -> 0
assign id_o =
{
// y = 0, 1, 2, 3,
{ b_lp ' (31) , b_lp ' (0) , b_lp ' (1) , b_lp ' (2) }, // x = 0
{ b_lp ' (30) , b_lp ' (5) , b_lp ' (4) , b_lp ' (3) }, // x = 1
{ b_lp ' (29) , b_lp ' (6) , b_lp ' (7) , b_lp ' (8) }, // x = 2
{ b_lp ' (28) , b_lp ' (11) , b_lp ' (10) , b_lp ' (9) }, // x = 3
{ b_lp ' (27) , b_lp ' (12) , b_lp ' (13) , b_lp ' (14) }, // x = 4
{ b_lp ' (26) , b_lp ' (17) , b_lp ' (16) , b_lp ' (15) }, // x = 5
{ b_lp ' (25) , b_lp ' (18) , b_lp ' (19) , b_lp ' (20) }, // x = 6
{ b_lp ' (24) , b_lp ' (23) , b_lp ' (22) , b_lp ' (21) } // x = 7
};
end
if (x_max_p == 8 && y_max_p == 5 )
begin
assign back_data_in_o[ 6 ][ 4 ] = back_data_out_i[ 7 ][ 4 ]; // 27 <- 28
assign fwd_data_in_o [ 7 ][ 3 ] = fwd_data_out_i [ 7 ][ 4 ]; // 28 -> 29
assign back_data_in_o[ 6 ][ 3 ] = back_data_out_i[ 6 ][ 4 ]; // 26 <- 27
assign fwd_data_in_o [ 7 ][ 4 ] = fwd_data_out_i [ 6 ][ 4 ]; // 27 -> 28
assign back_data_in_o[ 4 ][ 4 ] = back_data_out_i[ 5 ][ 4 ]; // 19 <- 20
assign fwd_data_in_o [ 5 ][ 3 ] = fwd_data_out_i [ 5 ][ 4 ]; // 20 -> 21
assign back_data_in_o[ 4 ][ 3 ] = back_data_out_i[ 4 ][ 4 ]; // 18 <- 19
assign fwd_data_in_o [ 5 ][ 4 ] = fwd_data_out_i [ 4 ][ 4 ]; // 19 -> 20
assign back_data_in_o[ 2 ][ 4 ] = back_data_out_i[ 3 ][ 4 ]; // 11 <- 12
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 3 ][ 4 ]; // 12 -> 13
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 2 ][ 4 ]; // 10 <- 11
assign fwd_data_in_o [ 3 ][ 4 ] = fwd_data_out_i [ 2 ][ 4 ]; // 11 -> 12
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 1 ][ 4 ]; // 3 <- 4
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 1 ][ 4 ]; // 4 -> 5
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 4 ]; // 2 <- 3
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 0 ][ 4 ]; // 3 -> 4
assign back_data_in_o[ 7 ][ 4 ] = back_data_out_i[ 7 ][ 3 ]; // 28 <- 29
assign fwd_data_in_o [ 7 ][ 2 ] = fwd_data_out_i [ 7 ][ 3 ]; // 29 -> 30
assign back_data_in_o[ 6 ][ 2 ] = back_data_out_i[ 6 ][ 3 ]; // 25 <- 26
assign fwd_data_in_o [ 6 ][ 4 ] = fwd_data_out_i [ 6 ][ 3 ]; // 26 -> 27
assign back_data_in_o[ 5 ][ 4 ] = back_data_out_i[ 5 ][ 3 ]; // 20 <- 21
assign fwd_data_in_o [ 5 ][ 2 ] = fwd_data_out_i [ 5 ][ 3 ]; // 21 -> 22
assign back_data_in_o[ 4 ][ 2 ] = back_data_out_i[ 4 ][ 3 ]; // 17 <- 18
assign fwd_data_in_o [ 4 ][ 4 ] = fwd_data_out_i [ 4 ][ 3 ]; // 18 -> 19
assign back_data_in_o[ 3 ][ 4 ] = back_data_out_i[ 3 ][ 3 ]; // 12 <- 13
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 3 ][ 3 ]; // 13 -> 14
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 2 ][ 3 ]; // 9 <- 10
assign fwd_data_in_o [ 2 ][ 4 ] = fwd_data_out_i [ 2 ][ 3 ]; // 10 -> 11
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 1 ][ 3 ]; // 4 <- 5
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 3 ]; // 5 -> 6
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 3 ]; // 1 <- 2
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 3 ]; // 2 -> 3
assign back_data_in_o[ 7 ][ 3 ] = back_data_out_i[ 7 ][ 2 ]; // 29 <- 30
assign fwd_data_in_o [ 7 ][ 1 ] = fwd_data_out_i [ 7 ][ 2 ]; // 30 -> 31
assign back_data_in_o[ 6 ][ 1 ] = back_data_out_i[ 6 ][ 2 ]; // 24 <- 25
assign fwd_data_in_o [ 6 ][ 3 ] = fwd_data_out_i [ 6 ][ 2 ]; // 25 -> 26
assign back_data_in_o[ 5 ][ 3 ] = back_data_out_i[ 5 ][ 2 ]; // 21 <- 22
assign fwd_data_in_o [ 5 ][ 1 ] = fwd_data_out_i [ 5 ][ 2 ]; // 22 -> 23
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 4 ][ 2 ]; // 16 <- 17
assign fwd_data_in_o [ 4 ][ 3 ] = fwd_data_out_i [ 4 ][ 2 ]; // 17 -> 18
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 3 ][ 2 ]; // 13 <- 14
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 3 ][ 2 ]; // 14 -> 15
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 2 ][ 2 ]; // 8 <- 9
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 2 ][ 2 ]; // 9 -> 10
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 2 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 6 -> 7
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 7 ][ 2 ] = back_data_out_i[ 7 ][ 1 ]; // 30 <- 31
assign fwd_data_in_o [ 7 ][ 0 ] = fwd_data_out_i [ 7 ][ 1 ]; // 31 -> 32
assign back_data_in_o[ 5 ][ 1 ] = back_data_out_i[ 6 ][ 1 ]; // 23 <- 24
assign fwd_data_in_o [ 6 ][ 2 ] = fwd_data_out_i [ 6 ][ 1 ]; // 24 -> 25
assign back_data_in_o[ 5 ][ 2 ] = back_data_out_i[ 5 ][ 1 ]; // 22 <- 23
assign fwd_data_in_o [ 6 ][ 1 ] = fwd_data_out_i [ 5 ][ 1 ]; // 23 -> 24
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 4 ][ 1 ]; // 15 <- 16
assign fwd_data_in_o [ 4 ][ 2 ] = fwd_data_out_i [ 4 ][ 1 ]; // 16 -> 17
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 3 ][ 1 ]; // 14 <- 15
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 15 -> 16
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 7 <- 8
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 2 ][ 1 ]; // 8 -> 9
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 6 <- 7
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 39 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 7 ][ 1 ] = back_data_out_i[ 7 ][ 0 ]; // 31 <- 32
assign fwd_data_in_o [ 6 ][ 0 ] = fwd_data_out_i [ 7 ][ 0 ]; // 32 -> 33
assign back_data_in_o[ 7 ][ 0 ] = back_data_out_i[ 6 ][ 0 ]; // 32 <- 33
assign fwd_data_in_o [ 5 ][ 0 ] = fwd_data_out_i [ 6 ][ 0 ]; // 33 -> 34
assign back_data_in_o[ 6 ][ 0 ] = back_data_out_i[ 5 ][ 0 ]; // 33 <- 34
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 5 ][ 0 ]; // 34 -> 35
assign back_data_in_o[ 5 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 34 <- 35
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 4 ][ 0 ]; // 35 -> 36
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 35 <- 36
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 36 -> 37
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 36 <- 37
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 37 -> 38
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 37 <- 38
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 38 -> 39
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 38 <- 39
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 39 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4,
{ b_lp ' (39) , b_lp ' (0) , b_lp ' (1) , b_lp ' (2) , b_lp ' (3) }, // x = 0
{ b_lp ' (38) , b_lp ' (7) , b_lp ' (6) , b_lp ' (5) , b_lp ' (4) }, // x = 1
{ b_lp ' (37) , b_lp ' (8) , b_lp ' (9) , b_lp ' (10) , b_lp ' (11) }, // x = 2
{ b_lp ' (36) , b_lp ' (15) , b_lp ' (14) , b_lp ' (13) , b_lp ' (12) }, // x = 3
{ b_lp ' (35) , b_lp ' (16) , b_lp ' (17) , b_lp ' (18) , b_lp ' (19) }, // x = 4
{ b_lp ' (34) , b_lp ' (23) , b_lp ' (22) , b_lp ' (21) , b_lp ' (20) }, // x = 5
{ b_lp ' (33) , b_lp ' (24) , b_lp ' (25) , b_lp ' (26) , b_lp ' (27) }, // x = 6
{ b_lp ' (32) , b_lp ' (31) , b_lp ' (30) , b_lp ' (29) , b_lp ' (28) } // x = 7
};
end
if (x_max_p == 8 && y_max_p == 6 )
begin
assign back_data_in_o[ 6 ][ 5 ] = back_data_out_i[ 7 ][ 5 ]; // 34 <- 35
assign fwd_data_in_o [ 7 ][ 4 ] = fwd_data_out_i [ 7 ][ 5 ]; // 35 -> 36
assign back_data_in_o[ 6 ][ 4 ] = back_data_out_i[ 6 ][ 5 ]; // 33 <- 34
assign fwd_data_in_o [ 7 ][ 5 ] = fwd_data_out_i [ 6 ][ 5 ]; // 34 -> 35
assign back_data_in_o[ 4 ][ 5 ] = back_data_out_i[ 5 ][ 5 ]; // 24 <- 25
assign fwd_data_in_o [ 5 ][ 4 ] = fwd_data_out_i [ 5 ][ 5 ]; // 25 -> 26
assign back_data_in_o[ 4 ][ 4 ] = back_data_out_i[ 4 ][ 5 ]; // 23 <- 24
assign fwd_data_in_o [ 5 ][ 5 ] = fwd_data_out_i [ 4 ][ 5 ]; // 24 -> 25
assign back_data_in_o[ 2 ][ 5 ] = back_data_out_i[ 3 ][ 5 ]; // 14 <- 15
assign fwd_data_in_o [ 3 ][ 4 ] = fwd_data_out_i [ 3 ][ 5 ]; // 15 -> 16
assign back_data_in_o[ 2 ][ 4 ] = back_data_out_i[ 2 ][ 5 ]; // 13 <- 14
assign fwd_data_in_o [ 3 ][ 5 ] = fwd_data_out_i [ 2 ][ 5 ]; // 14 -> 15
assign back_data_in_o[ 0 ][ 5 ] = back_data_out_i[ 1 ][ 5 ]; // 4 <- 5
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 1 ][ 5 ]; // 5 -> 6
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 0 ][ 5 ]; // 3 <- 4
assign fwd_data_in_o [ 1 ][ 5 ] = fwd_data_out_i [ 0 ][ 5 ]; // 4 -> 5
assign back_data_in_o[ 7 ][ 5 ] = back_data_out_i[ 7 ][ 4 ]; // 35 <- 36
assign fwd_data_in_o [ 7 ][ 3 ] = fwd_data_out_i [ 7 ][ 4 ]; // 36 -> 37
assign back_data_in_o[ 6 ][ 3 ] = back_data_out_i[ 6 ][ 4 ]; // 32 <- 33
assign fwd_data_in_o [ 6 ][ 5 ] = fwd_data_out_i [ 6 ][ 4 ]; // 33 -> 34
assign back_data_in_o[ 5 ][ 5 ] = back_data_out_i[ 5 ][ 4 ]; // 25 <- 26
assign fwd_data_in_o [ 5 ][ 3 ] = fwd_data_out_i [ 5 ][ 4 ]; // 26 -> 27
assign back_data_in_o[ 4 ][ 3 ] = back_data_out_i[ 4 ][ 4 ]; // 22 <- 23
assign fwd_data_in_o [ 4 ][ 5 ] = fwd_data_out_i [ 4 ][ 4 ]; // 23 -> 24
assign back_data_in_o[ 3 ][ 5 ] = back_data_out_i[ 3 ][ 4 ]; // 15 <- 16
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 3 ][ 4 ]; // 16 -> 17
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 2 ][ 4 ]; // 12 <- 13
assign fwd_data_in_o [ 2 ][ 5 ] = fwd_data_out_i [ 2 ][ 4 ]; // 13 -> 14
assign back_data_in_o[ 1 ][ 5 ] = back_data_out_i[ 1 ][ 4 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 1 ][ 4 ]; // 6 -> 7
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 4 ]; // 2 <- 3
assign fwd_data_in_o [ 0 ][ 5 ] = fwd_data_out_i [ 0 ][ 4 ]; // 3 -> 4
assign back_data_in_o[ 7 ][ 4 ] = back_data_out_i[ 7 ][ 3 ]; // 36 <- 37
assign fwd_data_in_o [ 7 ][ 2 ] = fwd_data_out_i [ 7 ][ 3 ]; // 37 -> 38
assign back_data_in_o[ 6 ][ 2 ] = back_data_out_i[ 6 ][ 3 ]; // 31 <- 32
assign fwd_data_in_o [ 6 ][ 4 ] = fwd_data_out_i [ 6 ][ 3 ]; // 32 -> 33
assign back_data_in_o[ 5 ][ 4 ] = back_data_out_i[ 5 ][ 3 ]; // 26 <- 27
assign fwd_data_in_o [ 5 ][ 2 ] = fwd_data_out_i [ 5 ][ 3 ]; // 27 -> 28
assign back_data_in_o[ 4 ][ 2 ] = back_data_out_i[ 4 ][ 3 ]; // 21 <- 22
assign fwd_data_in_o [ 4 ][ 4 ] = fwd_data_out_i [ 4 ][ 3 ]; // 22 -> 23
assign back_data_in_o[ 3 ][ 4 ] = back_data_out_i[ 3 ][ 3 ]; // 16 <- 17
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 3 ][ 3 ]; // 17 -> 18
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 2 ][ 3 ]; // 11 <- 12
assign fwd_data_in_o [ 2 ][ 4 ] = fwd_data_out_i [ 2 ][ 3 ]; // 12 -> 13
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 1 ][ 3 ]; // 6 <- 7
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 3 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 3 ]; // 1 <- 2
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 3 ]; // 2 -> 3
assign back_data_in_o[ 7 ][ 3 ] = back_data_out_i[ 7 ][ 2 ]; // 37 <- 38
assign fwd_data_in_o [ 7 ][ 1 ] = fwd_data_out_i [ 7 ][ 2 ]; // 38 -> 39
assign back_data_in_o[ 6 ][ 1 ] = back_data_out_i[ 6 ][ 2 ]; // 30 <- 31
assign fwd_data_in_o [ 6 ][ 3 ] = fwd_data_out_i [ 6 ][ 2 ]; // 31 -> 32
assign back_data_in_o[ 5 ][ 3 ] = back_data_out_i[ 5 ][ 2 ]; // 27 <- 28
assign fwd_data_in_o [ 5 ][ 1 ] = fwd_data_out_i [ 5 ][ 2 ]; // 28 -> 29
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 4 ][ 2 ]; // 20 <- 21
assign fwd_data_in_o [ 4 ][ 3 ] = fwd_data_out_i [ 4 ][ 2 ]; // 21 -> 22
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 3 ][ 2 ]; // 17 <- 18
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 3 ][ 2 ]; // 18 -> 19
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 2 ][ 2 ]; // 10 <- 11
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 2 ][ 2 ]; // 11 -> 12
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 2 ]; // 7 <- 8
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 8 -> 9
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 7 ][ 2 ] = back_data_out_i[ 7 ][ 1 ]; // 38 <- 39
assign fwd_data_in_o [ 7 ][ 0 ] = fwd_data_out_i [ 7 ][ 1 ]; // 39 -> 40
assign back_data_in_o[ 5 ][ 1 ] = back_data_out_i[ 6 ][ 1 ]; // 29 <- 30
assign fwd_data_in_o [ 6 ][ 2 ] = fwd_data_out_i [ 6 ][ 1 ]; // 30 -> 31
assign back_data_in_o[ 5 ][ 2 ] = back_data_out_i[ 5 ][ 1 ]; // 28 <- 29
assign fwd_data_in_o [ 6 ][ 1 ] = fwd_data_out_i [ 5 ][ 1 ]; // 29 -> 30
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 4 ][ 1 ]; // 19 <- 20
assign fwd_data_in_o [ 4 ][ 2 ] = fwd_data_out_i [ 4 ][ 1 ]; // 20 -> 21
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 3 ][ 1 ]; // 18 <- 19
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 19 -> 20
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 9 <- 10
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 2 ][ 1 ]; // 10 -> 11
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 8 <- 9
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 9 -> 10
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 47 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 7 ][ 1 ] = back_data_out_i[ 7 ][ 0 ]; // 39 <- 40
assign fwd_data_in_o [ 6 ][ 0 ] = fwd_data_out_i [ 7 ][ 0 ]; // 40 -> 41
assign back_data_in_o[ 7 ][ 0 ] = back_data_out_i[ 6 ][ 0 ]; // 40 <- 41
assign fwd_data_in_o [ 5 ][ 0 ] = fwd_data_out_i [ 6 ][ 0 ]; // 41 -> 42
assign back_data_in_o[ 6 ][ 0 ] = back_data_out_i[ 5 ][ 0 ]; // 41 <- 42
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 5 ][ 0 ]; // 42 -> 43
assign back_data_in_o[ 5 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 42 <- 43
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 4 ][ 0 ]; // 43 -> 44
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 43 <- 44
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 44 -> 45
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 44 <- 45
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 45 -> 46
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 45 <- 46
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 46 -> 47
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 46 <- 47
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 47 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4, 5,
{ b_lp ' (47) , b_lp ' (0) , b_lp ' (1) , b_lp ' (2) , b_lp ' (3) , b_lp ' (4) }, // x = 0
{ b_lp ' (46) , b_lp ' (9) , b_lp ' (8) , b_lp ' (7) , b_lp ' (6) , b_lp ' (5) }, // x = 1
{ b_lp ' (45) , b_lp ' (10) , b_lp ' (11) , b_lp ' (12) , b_lp ' (13) , b_lp ' (14) }, // x = 2
{ b_lp ' (44) , b_lp ' (19) , b_lp ' (18) , b_lp ' (17) , b_lp ' (16) , b_lp ' (15) }, // x = 3
{ b_lp ' (43) , b_lp ' (20) , b_lp ' (21) , b_lp ' (22) , b_lp ' (23) , b_lp ' (24) }, // x = 4
{ b_lp ' (42) , b_lp ' (29) , b_lp ' (28) , b_lp ' (27) , b_lp ' (26) , b_lp ' (25) }, // x = 5
{ b_lp ' (41) , b_lp ' (30) , b_lp ' (31) , b_lp ' (32) , b_lp ' (33) , b_lp ' (34) }, // x = 6
{ b_lp ' (40) , b_lp ' (39) , b_lp ' (38) , b_lp ' (37) , b_lp ' (36) , b_lp ' (35) } // x = 7
};
end
if (x_max_p == 8 && y_max_p == 7 )
begin
assign back_data_in_o[ 6 ][ 6 ] = back_data_out_i[ 7 ][ 6 ]; // 41 <- 42
assign fwd_data_in_o [ 7 ][ 5 ] = fwd_data_out_i [ 7 ][ 6 ]; // 42 -> 43
assign back_data_in_o[ 6 ][ 5 ] = back_data_out_i[ 6 ][ 6 ]; // 40 <- 41
assign fwd_data_in_o [ 7 ][ 6 ] = fwd_data_out_i [ 6 ][ 6 ]; // 41 -> 42
assign back_data_in_o[ 4 ][ 6 ] = back_data_out_i[ 5 ][ 6 ]; // 29 <- 30
assign fwd_data_in_o [ 5 ][ 5 ] = fwd_data_out_i [ 5 ][ 6 ]; // 30 -> 31
assign back_data_in_o[ 4 ][ 5 ] = back_data_out_i[ 4 ][ 6 ]; // 28 <- 29
assign fwd_data_in_o [ 5 ][ 6 ] = fwd_data_out_i [ 4 ][ 6 ]; // 29 -> 30
assign back_data_in_o[ 2 ][ 6 ] = back_data_out_i[ 3 ][ 6 ]; // 17 <- 18
assign fwd_data_in_o [ 3 ][ 5 ] = fwd_data_out_i [ 3 ][ 6 ]; // 18 -> 19
assign back_data_in_o[ 2 ][ 5 ] = back_data_out_i[ 2 ][ 6 ]; // 16 <- 17
assign fwd_data_in_o [ 3 ][ 6 ] = fwd_data_out_i [ 2 ][ 6 ]; // 17 -> 18
assign back_data_in_o[ 0 ][ 6 ] = back_data_out_i[ 1 ][ 6 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 5 ] = fwd_data_out_i [ 1 ][ 6 ]; // 6 -> 7
assign back_data_in_o[ 0 ][ 5 ] = back_data_out_i[ 0 ][ 6 ]; // 4 <- 5
assign fwd_data_in_o [ 1 ][ 6 ] = fwd_data_out_i [ 0 ][ 6 ]; // 5 -> 6
assign back_data_in_o[ 7 ][ 6 ] = back_data_out_i[ 7 ][ 5 ]; // 42 <- 43
assign fwd_data_in_o [ 7 ][ 4 ] = fwd_data_out_i [ 7 ][ 5 ]; // 43 -> 44
assign back_data_in_o[ 6 ][ 4 ] = back_data_out_i[ 6 ][ 5 ]; // 39 <- 40
assign fwd_data_in_o [ 6 ][ 6 ] = fwd_data_out_i [ 6 ][ 5 ]; // 40 -> 41
assign back_data_in_o[ 5 ][ 6 ] = back_data_out_i[ 5 ][ 5 ]; // 30 <- 31
assign fwd_data_in_o [ 5 ][ 4 ] = fwd_data_out_i [ 5 ][ 5 ]; // 31 -> 32
assign back_data_in_o[ 4 ][ 4 ] = back_data_out_i[ 4 ][ 5 ]; // 27 <- 28
assign fwd_data_in_o [ 4 ][ 6 ] = fwd_data_out_i [ 4 ][ 5 ]; // 28 -> 29
assign back_data_in_o[ 3 ][ 6 ] = back_data_out_i[ 3 ][ 5 ]; // 18 <- 19
assign fwd_data_in_o [ 3 ][ 4 ] = fwd_data_out_i [ 3 ][ 5 ]; // 19 -> 20
assign back_data_in_o[ 2 ][ 4 ] = back_data_out_i[ 2 ][ 5 ]; // 15 <- 16
assign fwd_data_in_o [ 2 ][ 6 ] = fwd_data_out_i [ 2 ][ 5 ]; // 16 -> 17
assign back_data_in_o[ 1 ][ 6 ] = back_data_out_i[ 1 ][ 5 ]; // 6 <- 7
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 1 ][ 5 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 0 ][ 5 ]; // 3 <- 4
assign fwd_data_in_o [ 0 ][ 6 ] = fwd_data_out_i [ 0 ][ 5 ]; // 4 -> 5
assign back_data_in_o[ 7 ][ 5 ] = back_data_out_i[ 7 ][ 4 ]; // 43 <- 44
assign fwd_data_in_o [ 7 ][ 3 ] = fwd_data_out_i [ 7 ][ 4 ]; // 44 -> 45
assign back_data_in_o[ 6 ][ 3 ] = back_data_out_i[ 6 ][ 4 ]; // 38 <- 39
assign fwd_data_in_o [ 6 ][ 5 ] = fwd_data_out_i [ 6 ][ 4 ]; // 39 -> 40
assign back_data_in_o[ 5 ][ 5 ] = back_data_out_i[ 5 ][ 4 ]; // 31 <- 32
assign fwd_data_in_o [ 5 ][ 3 ] = fwd_data_out_i [ 5 ][ 4 ]; // 32 -> 33
assign back_data_in_o[ 4 ][ 3 ] = back_data_out_i[ 4 ][ 4 ]; // 26 <- 27
assign fwd_data_in_o [ 4 ][ 5 ] = fwd_data_out_i [ 4 ][ 4 ]; // 27 -> 28
assign back_data_in_o[ 3 ][ 5 ] = back_data_out_i[ 3 ][ 4 ]; // 19 <- 20
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 3 ][ 4 ]; // 20 -> 21
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 2 ][ 4 ]; // 14 <- 15
assign fwd_data_in_o [ 2 ][ 5 ] = fwd_data_out_i [ 2 ][ 4 ]; // 15 -> 16
assign back_data_in_o[ 1 ][ 5 ] = back_data_out_i[ 1 ][ 4 ]; // 7 <- 8
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 1 ][ 4 ]; // 8 -> 9
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 4 ]; // 2 <- 3
assign fwd_data_in_o [ 0 ][ 5 ] = fwd_data_out_i [ 0 ][ 4 ]; // 3 -> 4
assign back_data_in_o[ 7 ][ 4 ] = back_data_out_i[ 7 ][ 3 ]; // 44 <- 45
assign fwd_data_in_o [ 7 ][ 2 ] = fwd_data_out_i [ 7 ][ 3 ]; // 45 -> 46
assign back_data_in_o[ 6 ][ 2 ] = back_data_out_i[ 6 ][ 3 ]; // 37 <- 38
assign fwd_data_in_o [ 6 ][ 4 ] = fwd_data_out_i [ 6 ][ 3 ]; // 38 -> 39
assign back_data_in_o[ 5 ][ 4 ] = back_data_out_i[ 5 ][ 3 ]; // 32 <- 33
assign fwd_data_in_o [ 5 ][ 2 ] = fwd_data_out_i [ 5 ][ 3 ]; // 33 -> 34
assign back_data_in_o[ 4 ][ 2 ] = back_data_out_i[ 4 ][ 3 ]; // 25 <- 26
assign fwd_data_in_o [ 4 ][ 4 ] = fwd_data_out_i [ 4 ][ 3 ]; // 26 -> 27
assign back_data_in_o[ 3 ][ 4 ] = back_data_out_i[ 3 ][ 3 ]; // 20 <- 21
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 3 ][ 3 ]; // 21 -> 22
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 2 ][ 3 ]; // 13 <- 14
assign fwd_data_in_o [ 2 ][ 4 ] = fwd_data_out_i [ 2 ][ 3 ]; // 14 -> 15
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 1 ][ 3 ]; // 8 <- 9
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 3 ]; // 9 -> 10
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 3 ]; // 1 <- 2
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 3 ]; // 2 -> 3
assign back_data_in_o[ 7 ][ 3 ] = back_data_out_i[ 7 ][ 2 ]; // 45 <- 46
assign fwd_data_in_o [ 7 ][ 1 ] = fwd_data_out_i [ 7 ][ 2 ]; // 46 -> 47
assign back_data_in_o[ 6 ][ 1 ] = back_data_out_i[ 6 ][ 2 ]; // 36 <- 37
assign fwd_data_in_o [ 6 ][ 3 ] = fwd_data_out_i [ 6 ][ 2 ]; // 37 -> 38
assign back_data_in_o[ 5 ][ 3 ] = back_data_out_i[ 5 ][ 2 ]; // 33 <- 34
assign fwd_data_in_o [ 5 ][ 1 ] = fwd_data_out_i [ 5 ][ 2 ]; // 34 -> 35
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 4 ][ 2 ]; // 24 <- 25
assign fwd_data_in_o [ 4 ][ 3 ] = fwd_data_out_i [ 4 ][ 2 ]; // 25 -> 26
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 3 ][ 2 ]; // 21 <- 22
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 3 ][ 2 ]; // 22 -> 23
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 2 ][ 2 ]; // 12 <- 13
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 2 ][ 2 ]; // 13 -> 14
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 2 ]; // 9 <- 10
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 10 -> 11
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 7 ][ 2 ] = back_data_out_i[ 7 ][ 1 ]; // 46 <- 47
assign fwd_data_in_o [ 7 ][ 0 ] = fwd_data_out_i [ 7 ][ 1 ]; // 47 -> 48
assign back_data_in_o[ 5 ][ 1 ] = back_data_out_i[ 6 ][ 1 ]; // 35 <- 36
assign fwd_data_in_o [ 6 ][ 2 ] = fwd_data_out_i [ 6 ][ 1 ]; // 36 -> 37
assign back_data_in_o[ 5 ][ 2 ] = back_data_out_i[ 5 ][ 1 ]; // 34 <- 35
assign fwd_data_in_o [ 6 ][ 1 ] = fwd_data_out_i [ 5 ][ 1 ]; // 35 -> 36
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 4 ][ 1 ]; // 23 <- 24
assign fwd_data_in_o [ 4 ][ 2 ] = fwd_data_out_i [ 4 ][ 1 ]; // 24 -> 25
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 3 ][ 1 ]; // 22 <- 23
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 23 -> 24
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 11 <- 12
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 2 ][ 1 ]; // 12 -> 13
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 10 <- 11
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 11 -> 12
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 55 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 7 ][ 1 ] = back_data_out_i[ 7 ][ 0 ]; // 47 <- 48
assign fwd_data_in_o [ 6 ][ 0 ] = fwd_data_out_i [ 7 ][ 0 ]; // 48 -> 49
assign back_data_in_o[ 7 ][ 0 ] = back_data_out_i[ 6 ][ 0 ]; // 48 <- 49
assign fwd_data_in_o [ 5 ][ 0 ] = fwd_data_out_i [ 6 ][ 0 ]; // 49 -> 50
assign back_data_in_o[ 6 ][ 0 ] = back_data_out_i[ 5 ][ 0 ]; // 49 <- 50
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 5 ][ 0 ]; // 50 -> 51
assign back_data_in_o[ 5 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 50 <- 51
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 4 ][ 0 ]; // 51 -> 52
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 51 <- 52
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 52 -> 53
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 52 <- 53
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 53 -> 54
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 53 <- 54
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 54 -> 55
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 54 <- 55
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 55 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4, 5, 6,
{ b_lp ' (55) , b_lp ' (0) , b_lp ' (1) , b_lp ' (2) , b_lp ' (3) , b_lp ' (4) , b_lp ' (5) }, // x = 0
{ b_lp ' (54) , b_lp ' (11) , b_lp ' (10) , b_lp ' (9) , b_lp ' (8) , b_lp ' (7) , b_lp ' (6) }, // x = 1
{ b_lp ' (53) , b_lp ' (12) , b_lp ' (13) , b_lp ' (14) , b_lp ' (15) , b_lp ' (16) , b_lp ' (17) }, // x = 2
{ b_lp ' (52) , b_lp ' (23) , b_lp ' (22) , b_lp ' (21) , b_lp ' (20) , b_lp ' (19) , b_lp ' (18) }, // x = 3
{ b_lp ' (51) , b_lp ' (24) , b_lp ' (25) , b_lp ' (26) , b_lp ' (27) , b_lp ' (28) , b_lp ' (29) }, // x = 4
{ b_lp ' (50) , b_lp ' (35) , b_lp ' (34) , b_lp ' (33) , b_lp ' (32) , b_lp ' (31) , b_lp ' (30) }, // x = 5
{ b_lp ' (49) , b_lp ' (36) , b_lp ' (37) , b_lp ' (38) , b_lp ' (39) , b_lp ' (40) , b_lp ' (41) }, // x = 6
{ b_lp ' (48) , b_lp ' (47) , b_lp ' (46) , b_lp ' (45) , b_lp ' (44) , b_lp ' (43) , b_lp ' (42) } // x = 7
};
end
if (x_max_p == 8 && y_max_p == 8 )
begin
assign back_data_in_o[ 6 ][ 7 ] = back_data_out_i[ 7 ][ 7 ]; // 48 <- 49
assign fwd_data_in_o [ 7 ][ 6 ] = fwd_data_out_i [ 7 ][ 7 ]; // 49 -> 50
assign back_data_in_o[ 6 ][ 6 ] = back_data_out_i[ 6 ][ 7 ]; // 47 <- 48
assign fwd_data_in_o [ 7 ][ 7 ] = fwd_data_out_i [ 6 ][ 7 ]; // 48 -> 49
assign back_data_in_o[ 4 ][ 7 ] = back_data_out_i[ 5 ][ 7 ]; // 34 <- 35
assign fwd_data_in_o [ 5 ][ 6 ] = fwd_data_out_i [ 5 ][ 7 ]; // 35 -> 36
assign back_data_in_o[ 4 ][ 6 ] = back_data_out_i[ 4 ][ 7 ]; // 33 <- 34
assign fwd_data_in_o [ 5 ][ 7 ] = fwd_data_out_i [ 4 ][ 7 ]; // 34 -> 35
assign back_data_in_o[ 2 ][ 7 ] = back_data_out_i[ 3 ][ 7 ]; // 20 <- 21
assign fwd_data_in_o [ 3 ][ 6 ] = fwd_data_out_i [ 3 ][ 7 ]; // 21 -> 22
assign back_data_in_o[ 2 ][ 6 ] = back_data_out_i[ 2 ][ 7 ]; // 19 <- 20
assign fwd_data_in_o [ 3 ][ 7 ] = fwd_data_out_i [ 2 ][ 7 ]; // 20 -> 21
assign back_data_in_o[ 0 ][ 7 ] = back_data_out_i[ 1 ][ 7 ]; // 6 <- 7
assign fwd_data_in_o [ 1 ][ 6 ] = fwd_data_out_i [ 1 ][ 7 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 6 ] = back_data_out_i[ 0 ][ 7 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 7 ] = fwd_data_out_i [ 0 ][ 7 ]; // 6 -> 7
assign back_data_in_o[ 7 ][ 7 ] = back_data_out_i[ 7 ][ 6 ]; // 49 <- 50
assign fwd_data_in_o [ 7 ][ 5 ] = fwd_data_out_i [ 7 ][ 6 ]; // 50 -> 51
assign back_data_in_o[ 6 ][ 5 ] = back_data_out_i[ 6 ][ 6 ]; // 46 <- 47
assign fwd_data_in_o [ 6 ][ 7 ] = fwd_data_out_i [ 6 ][ 6 ]; // 47 -> 48
assign back_data_in_o[ 5 ][ 7 ] = back_data_out_i[ 5 ][ 6 ]; // 35 <- 36
assign fwd_data_in_o [ 5 ][ 5 ] = fwd_data_out_i [ 5 ][ 6 ]; // 36 -> 37
assign back_data_in_o[ 4 ][ 5 ] = back_data_out_i[ 4 ][ 6 ]; // 32 <- 33
assign fwd_data_in_o [ 4 ][ 7 ] = fwd_data_out_i [ 4 ][ 6 ]; // 33 -> 34
assign back_data_in_o[ 3 ][ 7 ] = back_data_out_i[ 3 ][ 6 ]; // 21 <- 22
assign fwd_data_in_o [ 3 ][ 5 ] = fwd_data_out_i [ 3 ][ 6 ]; // 22 -> 23
assign back_data_in_o[ 2 ][ 5 ] = back_data_out_i[ 2 ][ 6 ]; // 18 <- 19
assign fwd_data_in_o [ 2 ][ 7 ] = fwd_data_out_i [ 2 ][ 6 ]; // 19 -> 20
assign back_data_in_o[ 1 ][ 7 ] = back_data_out_i[ 1 ][ 6 ]; // 7 <- 8
assign fwd_data_in_o [ 1 ][ 5 ] = fwd_data_out_i [ 1 ][ 6 ]; // 8 -> 9
assign back_data_in_o[ 0 ][ 5 ] = back_data_out_i[ 0 ][ 6 ]; // 4 <- 5
assign fwd_data_in_o [ 0 ][ 7 ] = fwd_data_out_i [ 0 ][ 6 ]; // 5 -> 6
assign back_data_in_o[ 7 ][ 6 ] = back_data_out_i[ 7 ][ 5 ]; // 50 <- 51
assign fwd_data_in_o [ 7 ][ 4 ] = fwd_data_out_i [ 7 ][ 5 ]; // 51 -> 52
assign back_data_in_o[ 6 ][ 4 ] = back_data_out_i[ 6 ][ 5 ]; // 45 <- 46
assign fwd_data_in_o [ 6 ][ 6 ] = fwd_data_out_i [ 6 ][ 5 ]; // 46 -> 47
assign back_data_in_o[ 5 ][ 6 ] = back_data_out_i[ 5 ][ 5 ]; // 36 <- 37
assign fwd_data_in_o [ 5 ][ 4 ] = fwd_data_out_i [ 5 ][ 5 ]; // 37 -> 38
assign back_data_in_o[ 4 ][ 4 ] = back_data_out_i[ 4 ][ 5 ]; // 31 <- 32
assign fwd_data_in_o [ 4 ][ 6 ] = fwd_data_out_i [ 4 ][ 5 ]; // 32 -> 33
assign back_data_in_o[ 3 ][ 6 ] = back_data_out_i[ 3 ][ 5 ]; // 22 <- 23
assign fwd_data_in_o [ 3 ][ 4 ] = fwd_data_out_i [ 3 ][ 5 ]; // 23 -> 24
assign back_data_in_o[ 2 ][ 4 ] = back_data_out_i[ 2 ][ 5 ]; // 17 <- 18
assign fwd_data_in_o [ 2 ][ 6 ] = fwd_data_out_i [ 2 ][ 5 ]; // 18 -> 19
assign back_data_in_o[ 1 ][ 6 ] = back_data_out_i[ 1 ][ 5 ]; // 8 <- 9
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 1 ][ 5 ]; // 9 -> 10
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 0 ][ 5 ]; // 3 <- 4
assign fwd_data_in_o [ 0 ][ 6 ] = fwd_data_out_i [ 0 ][ 5 ]; // 4 -> 5
assign back_data_in_o[ 7 ][ 5 ] = back_data_out_i[ 7 ][ 4 ]; // 51 <- 52
assign fwd_data_in_o [ 7 ][ 3 ] = fwd_data_out_i [ 7 ][ 4 ]; // 52 -> 53
assign back_data_in_o[ 6 ][ 3 ] = back_data_out_i[ 6 ][ 4 ]; // 44 <- 45
assign fwd_data_in_o [ 6 ][ 5 ] = fwd_data_out_i [ 6 ][ 4 ]; // 45 -> 46
assign back_data_in_o[ 5 ][ 5 ] = back_data_out_i[ 5 ][ 4 ]; // 37 <- 38
assign fwd_data_in_o [ 5 ][ 3 ] = fwd_data_out_i [ 5 ][ 4 ]; // 38 -> 39
assign back_data_in_o[ 4 ][ 3 ] = back_data_out_i[ 4 ][ 4 ]; // 30 <- 31
assign fwd_data_in_o [ 4 ][ 5 ] = fwd_data_out_i [ 4 ][ 4 ]; // 31 -> 32
assign back_data_in_o[ 3 ][ 5 ] = back_data_out_i[ 3 ][ 4 ]; // 23 <- 24
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 3 ][ 4 ]; // 24 -> 25
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 2 ][ 4 ]; // 16 <- 17
assign fwd_data_in_o [ 2 ][ 5 ] = fwd_data_out_i [ 2 ][ 4 ]; // 17 -> 18
assign back_data_in_o[ 1 ][ 5 ] = back_data_out_i[ 1 ][ 4 ]; // 9 <- 10
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 1 ][ 4 ]; // 10 -> 11
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 4 ]; // 2 <- 3
assign fwd_data_in_o [ 0 ][ 5 ] = fwd_data_out_i [ 0 ][ 4 ]; // 3 -> 4
assign back_data_in_o[ 7 ][ 4 ] = back_data_out_i[ 7 ][ 3 ]; // 52 <- 53
assign fwd_data_in_o [ 7 ][ 2 ] = fwd_data_out_i [ 7 ][ 3 ]; // 53 -> 54
assign back_data_in_o[ 6 ][ 2 ] = back_data_out_i[ 6 ][ 3 ]; // 43 <- 44
assign fwd_data_in_o [ 6 ][ 4 ] = fwd_data_out_i [ 6 ][ 3 ]; // 44 -> 45
assign back_data_in_o[ 5 ][ 4 ] = back_data_out_i[ 5 ][ 3 ]; // 38 <- 39
assign fwd_data_in_o [ 5 ][ 2 ] = fwd_data_out_i [ 5 ][ 3 ]; // 39 -> 40
assign back_data_in_o[ 4 ][ 2 ] = back_data_out_i[ 4 ][ 3 ]; // 29 <- 30
assign fwd_data_in_o [ 4 ][ 4 ] = fwd_data_out_i [ 4 ][ 3 ]; // 30 -> 31
assign back_data_in_o[ 3 ][ 4 ] = back_data_out_i[ 3 ][ 3 ]; // 24 <- 25
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 3 ][ 3 ]; // 25 -> 26
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 2 ][ 3 ]; // 15 <- 16
assign fwd_data_in_o [ 2 ][ 4 ] = fwd_data_out_i [ 2 ][ 3 ]; // 16 -> 17
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 1 ][ 3 ]; // 10 <- 11
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 3 ]; // 11 -> 12
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 3 ]; // 1 <- 2
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 3 ]; // 2 -> 3
assign back_data_in_o[ 7 ][ 3 ] = back_data_out_i[ 7 ][ 2 ]; // 53 <- 54
assign fwd_data_in_o [ 7 ][ 1 ] = fwd_data_out_i [ 7 ][ 2 ]; // 54 -> 55
assign back_data_in_o[ 6 ][ 1 ] = back_data_out_i[ 6 ][ 2 ]; // 42 <- 43
assign fwd_data_in_o [ 6 ][ 3 ] = fwd_data_out_i [ 6 ][ 2 ]; // 43 -> 44
assign back_data_in_o[ 5 ][ 3 ] = back_data_out_i[ 5 ][ 2 ]; // 39 <- 40
assign fwd_data_in_o [ 5 ][ 1 ] = fwd_data_out_i [ 5 ][ 2 ]; // 40 -> 41
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 4 ][ 2 ]; // 28 <- 29
assign fwd_data_in_o [ 4 ][ 3 ] = fwd_data_out_i [ 4 ][ 2 ]; // 29 -> 30
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 3 ][ 2 ]; // 25 <- 26
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 3 ][ 2 ]; // 26 -> 27
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 2 ][ 2 ]; // 14 <- 15
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 2 ][ 2 ]; // 15 -> 16
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 2 ]; // 11 <- 12
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 1 ][ 2 ]; // 12 -> 13
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 2 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 2 ]; // 1 -> 2
assign back_data_in_o[ 7 ][ 2 ] = back_data_out_i[ 7 ][ 1 ]; // 54 <- 55
assign fwd_data_in_o [ 7 ][ 0 ] = fwd_data_out_i [ 7 ][ 1 ]; // 55 -> 56
assign back_data_in_o[ 5 ][ 1 ] = back_data_out_i[ 6 ][ 1 ]; // 41 <- 42
assign fwd_data_in_o [ 6 ][ 2 ] = fwd_data_out_i [ 6 ][ 1 ]; // 42 -> 43
assign back_data_in_o[ 5 ][ 2 ] = back_data_out_i[ 5 ][ 1 ]; // 40 <- 41
assign fwd_data_in_o [ 6 ][ 1 ] = fwd_data_out_i [ 5 ][ 1 ]; // 41 -> 42
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 4 ][ 1 ]; // 27 <- 28
assign fwd_data_in_o [ 4 ][ 2 ] = fwd_data_out_i [ 4 ][ 1 ]; // 28 -> 29
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 3 ][ 1 ]; // 26 <- 27
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 27 -> 28
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 13 <- 14
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 2 ][ 1 ]; // 14 -> 15
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 1 ][ 1 ]; // 12 <- 13
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 13 -> 14
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 63 <- 0
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 1 ]; // 0 -> 1
assign back_data_in_o[ 7 ][ 1 ] = back_data_out_i[ 7 ][ 0 ]; // 55 <- 56
assign fwd_data_in_o [ 6 ][ 0 ] = fwd_data_out_i [ 7 ][ 0 ]; // 56 -> 57
assign back_data_in_o[ 7 ][ 0 ] = back_data_out_i[ 6 ][ 0 ]; // 56 <- 57
assign fwd_data_in_o [ 5 ][ 0 ] = fwd_data_out_i [ 6 ][ 0 ]; // 57 -> 58
assign back_data_in_o[ 6 ][ 0 ] = back_data_out_i[ 5 ][ 0 ]; // 57 <- 58
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 5 ][ 0 ]; // 58 -> 59
assign back_data_in_o[ 5 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 58 <- 59
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 4 ][ 0 ]; // 59 -> 60
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 59 <- 60
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 60 -> 61
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 60 <- 61
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 61 -> 62
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 61 <- 62
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 62 -> 63
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 62 <- 63
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 63 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4, 5, 6, 7,
{ b_lp ' (63) , b_lp ' (0) , b_lp ' (1) , b_lp ' (2) , b_lp ' (3) , b_lp ' (4) , b_lp ' (5) , b_lp ' (6) }, // x = 0
{ b_lp ' (62) , b_lp ' (13) , b_lp ' (12) , b_lp ' (11) , b_lp ' (10) , b_lp ' (9) , b_lp ' (8) , b_lp ' (7) }, // x = 1
{ b_lp ' (61) , b_lp ' (14) , b_lp ' (15) , b_lp ' (16) , b_lp ' (17) , b_lp ' (18) , b_lp ' (19) , b_lp ' (20) }, // x = 2
{ b_lp ' (60) , b_lp ' (27) , b_lp ' (26) , b_lp ' (25) , b_lp ' (24) , b_lp ' (23) , b_lp ' (22) , b_lp ' (21) }, // x = 3
{ b_lp ' (59) , b_lp ' (28) , b_lp ' (29) , b_lp ' (30) , b_lp ' (31) , b_lp ' (32) , b_lp ' (33) , b_lp ' (34) }, // x = 4
{ b_lp ' (58) , b_lp ' (41) , b_lp ' (40) , b_lp ' (39) , b_lp ' (38) , b_lp ' (37) , b_lp ' (36) , b_lp ' (35) }, // x = 5
{ b_lp ' (57) , b_lp ' (42) , b_lp ' (43) , b_lp ' (44) , b_lp ' (45) , b_lp ' (46) , b_lp ' (47) , b_lp ' (48) }, // x = 6
{ b_lp ' (56) , b_lp ' (55) , b_lp ' (54) , b_lp ' (53) , b_lp ' (52) , b_lp ' (51) , b_lp ' (50) , b_lp ' (49) } // x = 7
};
end
if (x_max_p == 3 && y_max_p == 2 )
begin
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 2 ][ 1 ]; // 1 <- 2
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 2 ][ 1 ]; // 2 -> 3
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 1 ][ 1 ]; // 2 <- 3
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 3 -> 4
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 0 ][ 1 ]; // 3 <- 4
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 0 ][ 1 ]; // 4 -> 5
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 0 <- 1
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 2 ][ 0 ]; // 1 -> 2
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 5 <- 0
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 0 -> 1
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 0 ]; // 4 <- 5
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 0 ][ 0 ]; // 5 -> 0
assign id_o =
{
// y = 0, 1,
{ b_lp ' (5) , b_lp ' (4) }, // x = 0
{ b_lp ' (0) , b_lp ' (3) }, // x = 1
{ b_lp ' (1) , b_lp ' (2) } // x = 2
};
end
if (x_max_p == 3 && y_max_p == 4 )
begin
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 2 ][ 3 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 2 ][ 3 ]; // 6 -> 7
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 1 ][ 3 ]; // 6 <- 7
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 1 ][ 3 ]; // 7 -> 8
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 0 ][ 3 ]; // 7 <- 8
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 3 ]; // 8 -> 9
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 2 ][ 2 ]; // 4 <- 5
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 2 ][ 2 ]; // 5 -> 6
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 1 ][ 2 ]; // 3 <- 4
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 1 ][ 2 ]; // 4 -> 5
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 2 ]; // 8 <- 9
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 2 ]; // 9 -> 10
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 2 ][ 1 ]; // 1 <- 2
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 2 ][ 1 ]; // 2 -> 3
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 1 ][ 1 ]; // 2 <- 3
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 1 ]; // 3 -> 4
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 1 ]; // 9 <- 10
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 0 ][ 1 ]; // 10 -> 11
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 0 <- 1
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 2 ][ 0 ]; // 1 -> 2
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 11 <- 0
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 0 -> 1
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 0 ]; // 10 <- 11
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 0 ][ 0 ]; // 11 -> 0
assign id_o =
{
// y = 0, 1, 2, 3,
{ b_lp ' (11) , b_lp ' (10) , b_lp ' (9) , b_lp ' (8) }, // x = 0
{ b_lp ' (0) , b_lp ' (3) , b_lp ' (4) , b_lp ' (7) }, // x = 1
{ b_lp ' (1) , b_lp ' (2) , b_lp ' (5) , b_lp ' (6) } // x = 2
};
end
if (x_max_p == 3 && y_max_p == 6 )
begin
assign back_data_in_o[ 2 ][ 4 ] = back_data_out_i[ 2 ][ 5 ]; // 9 <- 10
assign fwd_data_in_o [ 1 ][ 5 ] = fwd_data_out_i [ 2 ][ 5 ]; // 10 -> 11
assign back_data_in_o[ 2 ][ 5 ] = back_data_out_i[ 1 ][ 5 ]; // 10 <- 11
assign fwd_data_in_o [ 0 ][ 5 ] = fwd_data_out_i [ 1 ][ 5 ]; // 11 -> 12
assign back_data_in_o[ 1 ][ 5 ] = back_data_out_i[ 0 ][ 5 ]; // 11 <- 12
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 5 ]; // 12 -> 13
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 2 ][ 4 ]; // 8 <- 9
assign fwd_data_in_o [ 2 ][ 5 ] = fwd_data_out_i [ 2 ][ 4 ]; // 9 -> 10
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 4 ]; // 7 <- 8
assign fwd_data_in_o [ 2 ][ 4 ] = fwd_data_out_i [ 1 ][ 4 ]; // 8 -> 9
assign back_data_in_o[ 0 ][ 5 ] = back_data_out_i[ 0 ][ 4 ]; // 12 <- 13
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 4 ]; // 13 -> 14
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 2 ][ 3 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 2 ][ 3 ]; // 6 -> 7
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 1 ][ 3 ]; // 6 <- 7
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 1 ][ 3 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 0 ][ 3 ]; // 13 <- 14
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 3 ]; // 14 -> 15
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 2 ][ 2 ]; // 4 <- 5
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 2 ][ 2 ]; // 5 -> 6
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 1 ][ 2 ]; // 3 <- 4
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 1 ][ 2 ]; // 4 -> 5
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 2 ]; // 14 <- 15
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 2 ]; // 15 -> 16
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 2 ][ 1 ]; // 1 <- 2
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 2 ][ 1 ]; // 2 -> 3
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 1 ][ 1 ]; // 2 <- 3
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 1 ]; // 3 -> 4
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 1 ]; // 15 <- 16
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 0 ][ 1 ]; // 16 -> 17
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 0 <- 1
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 2 ][ 0 ]; // 1 -> 2
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 17 <- 0
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 0 -> 1
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 0 ]; // 16 <- 17
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 0 ][ 0 ]; // 17 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4, 5,
{ b_lp ' (17) , b_lp ' (16) , b_lp ' (15) , b_lp ' (14) , b_lp ' (13) , b_lp ' (12) }, // x = 0
{ b_lp ' (0) , b_lp ' (3) , b_lp ' (4) , b_lp ' (7) , b_lp ' (8) , b_lp ' (11) }, // x = 1
{ b_lp ' (1) , b_lp ' (2) , b_lp ' (5) , b_lp ' (6) , b_lp ' (9) , b_lp ' (10) } // x = 2
};
end
if (x_max_p == 3 && y_max_p == 8 )
begin
assign back_data_in_o[ 2 ][ 6 ] = back_data_out_i[ 2 ][ 7 ]; // 13 <- 14
assign fwd_data_in_o [ 1 ][ 7 ] = fwd_data_out_i [ 2 ][ 7 ]; // 14 -> 15
assign back_data_in_o[ 2 ][ 7 ] = back_data_out_i[ 1 ][ 7 ]; // 14 <- 15
assign fwd_data_in_o [ 0 ][ 7 ] = fwd_data_out_i [ 1 ][ 7 ]; // 15 -> 16
assign back_data_in_o[ 1 ][ 7 ] = back_data_out_i[ 0 ][ 7 ]; // 15 <- 16
assign fwd_data_in_o [ 0 ][ 6 ] = fwd_data_out_i [ 0 ][ 7 ]; // 16 -> 17
assign back_data_in_o[ 1 ][ 6 ] = back_data_out_i[ 2 ][ 6 ]; // 12 <- 13
assign fwd_data_in_o [ 2 ][ 7 ] = fwd_data_out_i [ 2 ][ 6 ]; // 13 -> 14
assign back_data_in_o[ 1 ][ 5 ] = back_data_out_i[ 1 ][ 6 ]; // 11 <- 12
assign fwd_data_in_o [ 2 ][ 6 ] = fwd_data_out_i [ 1 ][ 6 ]; // 12 -> 13
assign back_data_in_o[ 0 ][ 7 ] = back_data_out_i[ 0 ][ 6 ]; // 16 <- 17
assign fwd_data_in_o [ 0 ][ 5 ] = fwd_data_out_i [ 0 ][ 6 ]; // 17 -> 18
assign back_data_in_o[ 2 ][ 4 ] = back_data_out_i[ 2 ][ 5 ]; // 9 <- 10
assign fwd_data_in_o [ 1 ][ 5 ] = fwd_data_out_i [ 2 ][ 5 ]; // 10 -> 11
assign back_data_in_o[ 2 ][ 5 ] = back_data_out_i[ 1 ][ 5 ]; // 10 <- 11
assign fwd_data_in_o [ 1 ][ 6 ] = fwd_data_out_i [ 1 ][ 5 ]; // 11 -> 12
assign back_data_in_o[ 0 ][ 6 ] = back_data_out_i[ 0 ][ 5 ]; // 17 <- 18
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 5 ]; // 18 -> 19
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 2 ][ 4 ]; // 8 <- 9
assign fwd_data_in_o [ 2 ][ 5 ] = fwd_data_out_i [ 2 ][ 4 ]; // 9 -> 10
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 4 ]; // 7 <- 8
assign fwd_data_in_o [ 2 ][ 4 ] = fwd_data_out_i [ 1 ][ 4 ]; // 8 -> 9
assign back_data_in_o[ 0 ][ 5 ] = back_data_out_i[ 0 ][ 4 ]; // 18 <- 19
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 4 ]; // 19 -> 20
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 2 ][ 3 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 2 ][ 3 ]; // 6 -> 7
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 1 ][ 3 ]; // 6 <- 7
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 1 ][ 3 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 0 ][ 3 ]; // 19 <- 20
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 3 ]; // 20 -> 21
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 2 ][ 2 ]; // 4 <- 5
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 2 ][ 2 ]; // 5 -> 6
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 1 ][ 2 ]; // 3 <- 4
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 1 ][ 2 ]; // 4 -> 5
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 2 ]; // 20 <- 21
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 2 ]; // 21 -> 22
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 2 ][ 1 ]; // 1 <- 2
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 2 ][ 1 ]; // 2 -> 3
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 1 ][ 1 ]; // 2 <- 3
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 1 ]; // 3 -> 4
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 1 ]; // 21 <- 22
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 0 ][ 1 ]; // 22 -> 23
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 0 <- 1
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 2 ][ 0 ]; // 1 -> 2
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 23 <- 0
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 0 -> 1
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 0 ]; // 22 <- 23
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 0 ][ 0 ]; // 23 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4, 5, 6, 7,
{ b_lp ' (23) , b_lp ' (22) , b_lp ' (21) , b_lp ' (20) , b_lp ' (19) , b_lp ' (18) , b_lp ' (17) , b_lp ' (16) }, // x = 0
{ b_lp ' (0) , b_lp ' (3) , b_lp ' (4) , b_lp ' (7) , b_lp ' (8) , b_lp ' (11) , b_lp ' (12) , b_lp ' (15) }, // x = 1
{ b_lp ' (1) , b_lp ' (2) , b_lp ' (5) , b_lp ' (6) , b_lp ' (9) , b_lp ' (10) , b_lp ' (13) , b_lp ' (14) } // x = 2
};
end
if (x_max_p == 5 && y_max_p == 2 )
begin
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 4 ][ 1 ]; // 3 <- 4
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 4 ][ 1 ]; // 4 -> 5
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 3 ][ 1 ]; // 4 <- 5
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 5 -> 6
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 2 ][ 1 ]; // 6 -> 7
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 1 ][ 1 ]; // 6 <- 7
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 7 -> 8
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 0 ][ 1 ]; // 7 <- 8
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 0 ][ 1 ]; // 8 -> 9
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 2 <- 3
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 4 ][ 0 ]; // 3 -> 4
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 1 <- 2
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 2 -> 3
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 0 <- 1
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 1 -> 2
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 9 <- 0
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 0 -> 1
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 0 ]; // 8 <- 9
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 0 ][ 0 ]; // 9 -> 0
assign id_o =
{
// y = 0, 1,
{ b_lp ' (9) , b_lp ' (8) }, // x = 0
{ b_lp ' (0) , b_lp ' (7) }, // x = 1
{ b_lp ' (1) , b_lp ' (6) }, // x = 2
{ b_lp ' (2) , b_lp ' (5) }, // x = 3
{ b_lp ' (3) , b_lp ' (4) } // x = 4
};
end
if (x_max_p == 5 && y_max_p == 4 )
begin
assign back_data_in_o[ 4 ][ 2 ] = back_data_out_i[ 4 ][ 3 ]; // 11 <- 12
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 4 ][ 3 ]; // 12 -> 13
assign back_data_in_o[ 4 ][ 3 ] = back_data_out_i[ 3 ][ 3 ]; // 12 <- 13
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 3 ][ 3 ]; // 13 -> 14
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 2 ][ 3 ]; // 13 <- 14
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 2 ][ 3 ]; // 14 -> 15
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 1 ][ 3 ]; // 14 <- 15
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 1 ][ 3 ]; // 15 -> 16
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 0 ][ 3 ]; // 15 <- 16
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 3 ]; // 16 -> 17
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 4 ][ 2 ]; // 10 <- 11
assign fwd_data_in_o [ 4 ][ 3 ] = fwd_data_out_i [ 4 ][ 2 ]; // 11 -> 12
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 3 ][ 2 ]; // 9 <- 10
assign fwd_data_in_o [ 4 ][ 2 ] = fwd_data_out_i [ 3 ][ 2 ]; // 10 -> 11
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 2 ][ 2 ]; // 8 <- 9
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 2 ][ 2 ]; // 9 -> 10
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 1 ][ 2 ]; // 7 <- 8
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 1 ][ 2 ]; // 8 -> 9
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 2 ]; // 16 <- 17
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 2 ]; // 17 -> 18
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 4 ][ 1 ]; // 3 <- 4
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 4 ][ 1 ]; // 4 -> 5
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 3 ][ 1 ]; // 4 <- 5
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 5 -> 6
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 2 ][ 1 ]; // 6 -> 7
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 1 ][ 1 ]; // 6 <- 7
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 1 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 1 ]; // 17 <- 18
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 0 ][ 1 ]; // 18 -> 19
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 2 <- 3
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 4 ][ 0 ]; // 3 -> 4
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 1 <- 2
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 2 -> 3
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 0 <- 1
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 1 -> 2
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 19 <- 0
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 0 -> 1
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 0 ]; // 18 <- 19
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 0 ][ 0 ]; // 19 -> 0
assign id_o =
{
// y = 0, 1, 2, 3,
{ b_lp ' (19) , b_lp ' (18) , b_lp ' (17) , b_lp ' (16) }, // x = 0
{ b_lp ' (0) , b_lp ' (7) , b_lp ' (8) , b_lp ' (15) }, // x = 1
{ b_lp ' (1) , b_lp ' (6) , b_lp ' (9) , b_lp ' (14) }, // x = 2
{ b_lp ' (2) , b_lp ' (5) , b_lp ' (10) , b_lp ' (13) }, // x = 3
{ b_lp ' (3) , b_lp ' (4) , b_lp ' (11) , b_lp ' (12) } // x = 4
};
end
if (x_max_p == 5 && y_max_p == 6 )
begin
assign back_data_in_o[ 4 ][ 4 ] = back_data_out_i[ 4 ][ 5 ]; // 19 <- 20
assign fwd_data_in_o [ 3 ][ 5 ] = fwd_data_out_i [ 4 ][ 5 ]; // 20 -> 21
assign back_data_in_o[ 4 ][ 5 ] = back_data_out_i[ 3 ][ 5 ]; // 20 <- 21
assign fwd_data_in_o [ 2 ][ 5 ] = fwd_data_out_i [ 3 ][ 5 ]; // 21 -> 22
assign back_data_in_o[ 3 ][ 5 ] = back_data_out_i[ 2 ][ 5 ]; // 21 <- 22
assign fwd_data_in_o [ 1 ][ 5 ] = fwd_data_out_i [ 2 ][ 5 ]; // 22 -> 23
assign back_data_in_o[ 2 ][ 5 ] = back_data_out_i[ 1 ][ 5 ]; // 22 <- 23
assign fwd_data_in_o [ 0 ][ 5 ] = fwd_data_out_i [ 1 ][ 5 ]; // 23 -> 24
assign back_data_in_o[ 1 ][ 5 ] = back_data_out_i[ 0 ][ 5 ]; // 23 <- 24
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 5 ]; // 24 -> 25
assign back_data_in_o[ 3 ][ 4 ] = back_data_out_i[ 4 ][ 4 ]; // 18 <- 19
assign fwd_data_in_o [ 4 ][ 5 ] = fwd_data_out_i [ 4 ][ 4 ]; // 19 -> 20
assign back_data_in_o[ 2 ][ 4 ] = back_data_out_i[ 3 ][ 4 ]; // 17 <- 18
assign fwd_data_in_o [ 4 ][ 4 ] = fwd_data_out_i [ 3 ][ 4 ]; // 18 -> 19
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 2 ][ 4 ]; // 16 <- 17
assign fwd_data_in_o [ 3 ][ 4 ] = fwd_data_out_i [ 2 ][ 4 ]; // 17 -> 18
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 4 ]; // 15 <- 16
assign fwd_data_in_o [ 2 ][ 4 ] = fwd_data_out_i [ 1 ][ 4 ]; // 16 -> 17
assign back_data_in_o[ 0 ][ 5 ] = back_data_out_i[ 0 ][ 4 ]; // 24 <- 25
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 4 ]; // 25 -> 26
assign back_data_in_o[ 4 ][ 2 ] = back_data_out_i[ 4 ][ 3 ]; // 11 <- 12
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 4 ][ 3 ]; // 12 -> 13
assign back_data_in_o[ 4 ][ 3 ] = back_data_out_i[ 3 ][ 3 ]; // 12 <- 13
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 3 ][ 3 ]; // 13 -> 14
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 2 ][ 3 ]; // 13 <- 14
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 2 ][ 3 ]; // 14 -> 15
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 1 ][ 3 ]; // 14 <- 15
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 1 ][ 3 ]; // 15 -> 16
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 0 ][ 3 ]; // 25 <- 26
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 3 ]; // 26 -> 27
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 4 ][ 2 ]; // 10 <- 11
assign fwd_data_in_o [ 4 ][ 3 ] = fwd_data_out_i [ 4 ][ 2 ]; // 11 -> 12
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 3 ][ 2 ]; // 9 <- 10
assign fwd_data_in_o [ 4 ][ 2 ] = fwd_data_out_i [ 3 ][ 2 ]; // 10 -> 11
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 2 ][ 2 ]; // 8 <- 9
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 2 ][ 2 ]; // 9 -> 10
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 1 ][ 2 ]; // 7 <- 8
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 1 ][ 2 ]; // 8 -> 9
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 2 ]; // 26 <- 27
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 2 ]; // 27 -> 28
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 4 ][ 1 ]; // 3 <- 4
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 4 ][ 1 ]; // 4 -> 5
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 3 ][ 1 ]; // 4 <- 5
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 5 -> 6
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 2 ][ 1 ]; // 6 -> 7
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 1 ][ 1 ]; // 6 <- 7
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 1 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 1 ]; // 27 <- 28
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 0 ][ 1 ]; // 28 -> 29
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 2 <- 3
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 4 ][ 0 ]; // 3 -> 4
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 1 <- 2
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 2 -> 3
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 0 <- 1
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 1 -> 2
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 29 <- 0
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 0 -> 1
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 0 ]; // 28 <- 29
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 0 ][ 0 ]; // 29 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4, 5,
{ b_lp ' (29) , b_lp ' (28) , b_lp ' (27) , b_lp ' (26) , b_lp ' (25) , b_lp ' (24) }, // x = 0
{ b_lp ' (0) , b_lp ' (7) , b_lp ' (8) , b_lp ' (15) , b_lp ' (16) , b_lp ' (23) }, // x = 1
{ b_lp ' (1) , b_lp ' (6) , b_lp ' (9) , b_lp ' (14) , b_lp ' (17) , b_lp ' (22) }, // x = 2
{ b_lp ' (2) , b_lp ' (5) , b_lp ' (10) , b_lp ' (13) , b_lp ' (18) , b_lp ' (21) }, // x = 3
{ b_lp ' (3) , b_lp ' (4) , b_lp ' (11) , b_lp ' (12) , b_lp ' (19) , b_lp ' (20) } // x = 4
};
end
if (x_max_p == 5 && y_max_p == 8 )
begin
assign back_data_in_o[ 4 ][ 6 ] = back_data_out_i[ 4 ][ 7 ]; // 27 <- 28
assign fwd_data_in_o [ 3 ][ 7 ] = fwd_data_out_i [ 4 ][ 7 ]; // 28 -> 29
assign back_data_in_o[ 4 ][ 7 ] = back_data_out_i[ 3 ][ 7 ]; // 28 <- 29
assign fwd_data_in_o [ 2 ][ 7 ] = fwd_data_out_i [ 3 ][ 7 ]; // 29 -> 30
assign back_data_in_o[ 3 ][ 7 ] = back_data_out_i[ 2 ][ 7 ]; // 29 <- 30
assign fwd_data_in_o [ 1 ][ 7 ] = fwd_data_out_i [ 2 ][ 7 ]; // 30 -> 31
assign back_data_in_o[ 2 ][ 7 ] = back_data_out_i[ 1 ][ 7 ]; // 30 <- 31
assign fwd_data_in_o [ 0 ][ 7 ] = fwd_data_out_i [ 1 ][ 7 ]; // 31 -> 32
assign back_data_in_o[ 1 ][ 7 ] = back_data_out_i[ 0 ][ 7 ]; // 31 <- 32
assign fwd_data_in_o [ 0 ][ 6 ] = fwd_data_out_i [ 0 ][ 7 ]; // 32 -> 33
assign back_data_in_o[ 3 ][ 6 ] = back_data_out_i[ 4 ][ 6 ]; // 26 <- 27
assign fwd_data_in_o [ 4 ][ 7 ] = fwd_data_out_i [ 4 ][ 6 ]; // 27 -> 28
assign back_data_in_o[ 2 ][ 6 ] = back_data_out_i[ 3 ][ 6 ]; // 25 <- 26
assign fwd_data_in_o [ 4 ][ 6 ] = fwd_data_out_i [ 3 ][ 6 ]; // 26 -> 27
assign back_data_in_o[ 1 ][ 6 ] = back_data_out_i[ 2 ][ 6 ]; // 24 <- 25
assign fwd_data_in_o [ 3 ][ 6 ] = fwd_data_out_i [ 2 ][ 6 ]; // 25 -> 26
assign back_data_in_o[ 1 ][ 5 ] = back_data_out_i[ 1 ][ 6 ]; // 23 <- 24
assign fwd_data_in_o [ 2 ][ 6 ] = fwd_data_out_i [ 1 ][ 6 ]; // 24 -> 25
assign back_data_in_o[ 0 ][ 7 ] = back_data_out_i[ 0 ][ 6 ]; // 32 <- 33
assign fwd_data_in_o [ 0 ][ 5 ] = fwd_data_out_i [ 0 ][ 6 ]; // 33 -> 34
assign back_data_in_o[ 4 ][ 4 ] = back_data_out_i[ 4 ][ 5 ]; // 19 <- 20
assign fwd_data_in_o [ 3 ][ 5 ] = fwd_data_out_i [ 4 ][ 5 ]; // 20 -> 21
assign back_data_in_o[ 4 ][ 5 ] = back_data_out_i[ 3 ][ 5 ]; // 20 <- 21
assign fwd_data_in_o [ 2 ][ 5 ] = fwd_data_out_i [ 3 ][ 5 ]; // 21 -> 22
assign back_data_in_o[ 3 ][ 5 ] = back_data_out_i[ 2 ][ 5 ]; // 21 <- 22
assign fwd_data_in_o [ 1 ][ 5 ] = fwd_data_out_i [ 2 ][ 5 ]; // 22 -> 23
assign back_data_in_o[ 2 ][ 5 ] = back_data_out_i[ 1 ][ 5 ]; // 22 <- 23
assign fwd_data_in_o [ 1 ][ 6 ] = fwd_data_out_i [ 1 ][ 5 ]; // 23 -> 24
assign back_data_in_o[ 0 ][ 6 ] = back_data_out_i[ 0 ][ 5 ]; // 33 <- 34
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 5 ]; // 34 -> 35
assign back_data_in_o[ 3 ][ 4 ] = back_data_out_i[ 4 ][ 4 ]; // 18 <- 19
assign fwd_data_in_o [ 4 ][ 5 ] = fwd_data_out_i [ 4 ][ 4 ]; // 19 -> 20
assign back_data_in_o[ 2 ][ 4 ] = back_data_out_i[ 3 ][ 4 ]; // 17 <- 18
assign fwd_data_in_o [ 4 ][ 4 ] = fwd_data_out_i [ 3 ][ 4 ]; // 18 -> 19
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 2 ][ 4 ]; // 16 <- 17
assign fwd_data_in_o [ 3 ][ 4 ] = fwd_data_out_i [ 2 ][ 4 ]; // 17 -> 18
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 4 ]; // 15 <- 16
assign fwd_data_in_o [ 2 ][ 4 ] = fwd_data_out_i [ 1 ][ 4 ]; // 16 -> 17
assign back_data_in_o[ 0 ][ 5 ] = back_data_out_i[ 0 ][ 4 ]; // 34 <- 35
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 4 ]; // 35 -> 36
assign back_data_in_o[ 4 ][ 2 ] = back_data_out_i[ 4 ][ 3 ]; // 11 <- 12
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 4 ][ 3 ]; // 12 -> 13
assign back_data_in_o[ 4 ][ 3 ] = back_data_out_i[ 3 ][ 3 ]; // 12 <- 13
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 3 ][ 3 ]; // 13 -> 14
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 2 ][ 3 ]; // 13 <- 14
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 2 ][ 3 ]; // 14 -> 15
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 1 ][ 3 ]; // 14 <- 15
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 1 ][ 3 ]; // 15 -> 16
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 0 ][ 3 ]; // 35 <- 36
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 3 ]; // 36 -> 37
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 4 ][ 2 ]; // 10 <- 11
assign fwd_data_in_o [ 4 ][ 3 ] = fwd_data_out_i [ 4 ][ 2 ]; // 11 -> 12
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 3 ][ 2 ]; // 9 <- 10
assign fwd_data_in_o [ 4 ][ 2 ] = fwd_data_out_i [ 3 ][ 2 ]; // 10 -> 11
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 2 ][ 2 ]; // 8 <- 9
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 2 ][ 2 ]; // 9 -> 10
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 1 ][ 2 ]; // 7 <- 8
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 1 ][ 2 ]; // 8 -> 9
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 2 ]; // 36 <- 37
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 2 ]; // 37 -> 38
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 4 ][ 1 ]; // 3 <- 4
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 4 ][ 1 ]; // 4 -> 5
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 3 ][ 1 ]; // 4 <- 5
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 5 -> 6
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 5 <- 6
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 2 ][ 1 ]; // 6 -> 7
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 1 ][ 1 ]; // 6 <- 7
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 1 ]; // 7 -> 8
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 1 ]; // 37 <- 38
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 0 ][ 1 ]; // 38 -> 39
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 2 <- 3
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 4 ][ 0 ]; // 3 -> 4
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 1 <- 2
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 2 -> 3
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 0 <- 1
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 1 -> 2
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 39 <- 0
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 0 -> 1
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 0 ]; // 38 <- 39
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 0 ][ 0 ]; // 39 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4, 5, 6, 7,
{ b_lp ' (39) , b_lp ' (38) , b_lp ' (37) , b_lp ' (36) , b_lp ' (35) , b_lp ' (34) , b_lp ' (33) , b_lp ' (32) }, // x = 0
{ b_lp ' (0) , b_lp ' (7) , b_lp ' (8) , b_lp ' (15) , b_lp ' (16) , b_lp ' (23) , b_lp ' (24) , b_lp ' (31) }, // x = 1
{ b_lp ' (1) , b_lp ' (6) , b_lp ' (9) , b_lp ' (14) , b_lp ' (17) , b_lp ' (22) , b_lp ' (25) , b_lp ' (30) }, // x = 2
{ b_lp ' (2) , b_lp ' (5) , b_lp ' (10) , b_lp ' (13) , b_lp ' (18) , b_lp ' (21) , b_lp ' (26) , b_lp ' (29) }, // x = 3
{ b_lp ' (3) , b_lp ' (4) , b_lp ' (11) , b_lp ' (12) , b_lp ' (19) , b_lp ' (20) , b_lp ' (27) , b_lp ' (28) } // x = 4
};
end
if (x_max_p == 7 && y_max_p == 2 )
begin
assign back_data_in_o[ 6 ][ 0 ] = back_data_out_i[ 6 ][ 1 ]; // 5 <- 6
assign fwd_data_in_o [ 5 ][ 1 ] = fwd_data_out_i [ 6 ][ 1 ]; // 6 -> 7
assign back_data_in_o[ 6 ][ 1 ] = back_data_out_i[ 5 ][ 1 ]; // 6 <- 7
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 5 ][ 1 ]; // 7 -> 8
assign back_data_in_o[ 5 ][ 1 ] = back_data_out_i[ 4 ][ 1 ]; // 7 <- 8
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 4 ][ 1 ]; // 8 -> 9
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 3 ][ 1 ]; // 8 <- 9
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 9 -> 10
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 9 <- 10
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 2 ][ 1 ]; // 10 -> 11
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 1 ][ 1 ]; // 10 <- 11
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 1 ][ 1 ]; // 11 -> 12
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 0 ][ 1 ]; // 11 <- 12
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 0 ][ 1 ]; // 12 -> 13
assign back_data_in_o[ 5 ][ 0 ] = back_data_out_i[ 6 ][ 0 ]; // 4 <- 5
assign fwd_data_in_o [ 6 ][ 1 ] = fwd_data_out_i [ 6 ][ 0 ]; // 5 -> 6
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 5 ][ 0 ]; // 3 <- 4
assign fwd_data_in_o [ 6 ][ 0 ] = fwd_data_out_i [ 5 ][ 0 ]; // 4 -> 5
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 2 <- 3
assign fwd_data_in_o [ 5 ][ 0 ] = fwd_data_out_i [ 4 ][ 0 ]; // 3 -> 4
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 1 <- 2
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 2 -> 3
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 0 <- 1
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 1 -> 2
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 13 <- 0
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 0 -> 1
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 0 ]; // 12 <- 13
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 0 ][ 0 ]; // 13 -> 0
assign id_o =
{
// y = 0, 1,
{ b_lp ' (13) , b_lp ' (12) }, // x = 0
{ b_lp ' (0) , b_lp ' (11) }, // x = 1
{ b_lp ' (1) , b_lp ' (10) }, // x = 2
{ b_lp ' (2) , b_lp ' (9) }, // x = 3
{ b_lp ' (3) , b_lp ' (8) }, // x = 4
{ b_lp ' (4) , b_lp ' (7) }, // x = 5
{ b_lp ' (5) , b_lp ' (6) } // x = 6
};
end
if (x_max_p == 7 && y_max_p == 4 )
begin
assign back_data_in_o[ 6 ][ 2 ] = back_data_out_i[ 6 ][ 3 ]; // 17 <- 18
assign fwd_data_in_o [ 5 ][ 3 ] = fwd_data_out_i [ 6 ][ 3 ]; // 18 -> 19
assign back_data_in_o[ 6 ][ 3 ] = back_data_out_i[ 5 ][ 3 ]; // 18 <- 19
assign fwd_data_in_o [ 4 ][ 3 ] = fwd_data_out_i [ 5 ][ 3 ]; // 19 -> 20
assign back_data_in_o[ 5 ][ 3 ] = back_data_out_i[ 4 ][ 3 ]; // 19 <- 20
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 4 ][ 3 ]; // 20 -> 21
assign back_data_in_o[ 4 ][ 3 ] = back_data_out_i[ 3 ][ 3 ]; // 20 <- 21
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 3 ][ 3 ]; // 21 -> 22
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 2 ][ 3 ]; // 21 <- 22
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 2 ][ 3 ]; // 22 -> 23
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 1 ][ 3 ]; // 22 <- 23
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 1 ][ 3 ]; // 23 -> 24
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 0 ][ 3 ]; // 23 <- 24
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 3 ]; // 24 -> 25
assign back_data_in_o[ 5 ][ 2 ] = back_data_out_i[ 6 ][ 2 ]; // 16 <- 17
assign fwd_data_in_o [ 6 ][ 3 ] = fwd_data_out_i [ 6 ][ 2 ]; // 17 -> 18
assign back_data_in_o[ 4 ][ 2 ] = back_data_out_i[ 5 ][ 2 ]; // 15 <- 16
assign fwd_data_in_o [ 6 ][ 2 ] = fwd_data_out_i [ 5 ][ 2 ]; // 16 -> 17
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 4 ][ 2 ]; // 14 <- 15
assign fwd_data_in_o [ 5 ][ 2 ] = fwd_data_out_i [ 4 ][ 2 ]; // 15 -> 16
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 3 ][ 2 ]; // 13 <- 14
assign fwd_data_in_o [ 4 ][ 2 ] = fwd_data_out_i [ 3 ][ 2 ]; // 14 -> 15
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 2 ][ 2 ]; // 12 <- 13
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 2 ][ 2 ]; // 13 -> 14
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 1 ][ 2 ]; // 11 <- 12
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 1 ][ 2 ]; // 12 -> 13
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 2 ]; // 24 <- 25
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 2 ]; // 25 -> 26
assign back_data_in_o[ 6 ][ 0 ] = back_data_out_i[ 6 ][ 1 ]; // 5 <- 6
assign fwd_data_in_o [ 5 ][ 1 ] = fwd_data_out_i [ 6 ][ 1 ]; // 6 -> 7
assign back_data_in_o[ 6 ][ 1 ] = back_data_out_i[ 5 ][ 1 ]; // 6 <- 7
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 5 ][ 1 ]; // 7 -> 8
assign back_data_in_o[ 5 ][ 1 ] = back_data_out_i[ 4 ][ 1 ]; // 7 <- 8
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 4 ][ 1 ]; // 8 -> 9
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 3 ][ 1 ]; // 8 <- 9
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 9 -> 10
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 9 <- 10
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 2 ][ 1 ]; // 10 -> 11
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 1 ][ 1 ]; // 10 <- 11
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 1 ]; // 11 -> 12
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 1 ]; // 25 <- 26
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 0 ][ 1 ]; // 26 -> 27
assign back_data_in_o[ 5 ][ 0 ] = back_data_out_i[ 6 ][ 0 ]; // 4 <- 5
assign fwd_data_in_o [ 6 ][ 1 ] = fwd_data_out_i [ 6 ][ 0 ]; // 5 -> 6
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 5 ][ 0 ]; // 3 <- 4
assign fwd_data_in_o [ 6 ][ 0 ] = fwd_data_out_i [ 5 ][ 0 ]; // 4 -> 5
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 2 <- 3
assign fwd_data_in_o [ 5 ][ 0 ] = fwd_data_out_i [ 4 ][ 0 ]; // 3 -> 4
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 1 <- 2
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 2 -> 3
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 0 <- 1
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 1 -> 2
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 27 <- 0
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 0 -> 1
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 0 ]; // 26 <- 27
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 0 ][ 0 ]; // 27 -> 0
assign id_o =
{
// y = 0, 1, 2, 3,
{ b_lp ' (27) , b_lp ' (26) , b_lp ' (25) , b_lp ' (24) }, // x = 0
{ b_lp ' (0) , b_lp ' (11) , b_lp ' (12) , b_lp ' (23) }, // x = 1
{ b_lp ' (1) , b_lp ' (10) , b_lp ' (13) , b_lp ' (22) }, // x = 2
{ b_lp ' (2) , b_lp ' (9) , b_lp ' (14) , b_lp ' (21) }, // x = 3
{ b_lp ' (3) , b_lp ' (8) , b_lp ' (15) , b_lp ' (20) }, // x = 4
{ b_lp ' (4) , b_lp ' (7) , b_lp ' (16) , b_lp ' (19) }, // x = 5
{ b_lp ' (5) , b_lp ' (6) , b_lp ' (17) , b_lp ' (18) } // x = 6
};
end
if (x_max_p == 7 && y_max_p == 6 )
begin
assign back_data_in_o[ 6 ][ 4 ] = back_data_out_i[ 6 ][ 5 ]; // 29 <- 30
assign fwd_data_in_o [ 5 ][ 5 ] = fwd_data_out_i [ 6 ][ 5 ]; // 30 -> 31
assign back_data_in_o[ 6 ][ 5 ] = back_data_out_i[ 5 ][ 5 ]; // 30 <- 31
assign fwd_data_in_o [ 4 ][ 5 ] = fwd_data_out_i [ 5 ][ 5 ]; // 31 -> 32
assign back_data_in_o[ 5 ][ 5 ] = back_data_out_i[ 4 ][ 5 ]; // 31 <- 32
assign fwd_data_in_o [ 3 ][ 5 ] = fwd_data_out_i [ 4 ][ 5 ]; // 32 -> 33
assign back_data_in_o[ 4 ][ 5 ] = back_data_out_i[ 3 ][ 5 ]; // 32 <- 33
assign fwd_data_in_o [ 2 ][ 5 ] = fwd_data_out_i [ 3 ][ 5 ]; // 33 -> 34
assign back_data_in_o[ 3 ][ 5 ] = back_data_out_i[ 2 ][ 5 ]; // 33 <- 34
assign fwd_data_in_o [ 1 ][ 5 ] = fwd_data_out_i [ 2 ][ 5 ]; // 34 -> 35
assign back_data_in_o[ 2 ][ 5 ] = back_data_out_i[ 1 ][ 5 ]; // 34 <- 35
assign fwd_data_in_o [ 0 ][ 5 ] = fwd_data_out_i [ 1 ][ 5 ]; // 35 -> 36
assign back_data_in_o[ 1 ][ 5 ] = back_data_out_i[ 0 ][ 5 ]; // 35 <- 36
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 5 ]; // 36 -> 37
assign back_data_in_o[ 5 ][ 4 ] = back_data_out_i[ 6 ][ 4 ]; // 28 <- 29
assign fwd_data_in_o [ 6 ][ 5 ] = fwd_data_out_i [ 6 ][ 4 ]; // 29 -> 30
assign back_data_in_o[ 4 ][ 4 ] = back_data_out_i[ 5 ][ 4 ]; // 27 <- 28
assign fwd_data_in_o [ 6 ][ 4 ] = fwd_data_out_i [ 5 ][ 4 ]; // 28 -> 29
assign back_data_in_o[ 3 ][ 4 ] = back_data_out_i[ 4 ][ 4 ]; // 26 <- 27
assign fwd_data_in_o [ 5 ][ 4 ] = fwd_data_out_i [ 4 ][ 4 ]; // 27 -> 28
assign back_data_in_o[ 2 ][ 4 ] = back_data_out_i[ 3 ][ 4 ]; // 25 <- 26
assign fwd_data_in_o [ 4 ][ 4 ] = fwd_data_out_i [ 3 ][ 4 ]; // 26 -> 27
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 2 ][ 4 ]; // 24 <- 25
assign fwd_data_in_o [ 3 ][ 4 ] = fwd_data_out_i [ 2 ][ 4 ]; // 25 -> 26
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 4 ]; // 23 <- 24
assign fwd_data_in_o [ 2 ][ 4 ] = fwd_data_out_i [ 1 ][ 4 ]; // 24 -> 25
assign back_data_in_o[ 0 ][ 5 ] = back_data_out_i[ 0 ][ 4 ]; // 36 <- 37
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 4 ]; // 37 -> 38
assign back_data_in_o[ 6 ][ 2 ] = back_data_out_i[ 6 ][ 3 ]; // 17 <- 18
assign fwd_data_in_o [ 5 ][ 3 ] = fwd_data_out_i [ 6 ][ 3 ]; // 18 -> 19
assign back_data_in_o[ 6 ][ 3 ] = back_data_out_i[ 5 ][ 3 ]; // 18 <- 19
assign fwd_data_in_o [ 4 ][ 3 ] = fwd_data_out_i [ 5 ][ 3 ]; // 19 -> 20
assign back_data_in_o[ 5 ][ 3 ] = back_data_out_i[ 4 ][ 3 ]; // 19 <- 20
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 4 ][ 3 ]; // 20 -> 21
assign back_data_in_o[ 4 ][ 3 ] = back_data_out_i[ 3 ][ 3 ]; // 20 <- 21
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 3 ][ 3 ]; // 21 -> 22
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 2 ][ 3 ]; // 21 <- 22
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 2 ][ 3 ]; // 22 -> 23
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 1 ][ 3 ]; // 22 <- 23
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 1 ][ 3 ]; // 23 -> 24
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 0 ][ 3 ]; // 37 <- 38
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 3 ]; // 38 -> 39
assign back_data_in_o[ 5 ][ 2 ] = back_data_out_i[ 6 ][ 2 ]; // 16 <- 17
assign fwd_data_in_o [ 6 ][ 3 ] = fwd_data_out_i [ 6 ][ 2 ]; // 17 -> 18
assign back_data_in_o[ 4 ][ 2 ] = back_data_out_i[ 5 ][ 2 ]; // 15 <- 16
assign fwd_data_in_o [ 6 ][ 2 ] = fwd_data_out_i [ 5 ][ 2 ]; // 16 -> 17
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 4 ][ 2 ]; // 14 <- 15
assign fwd_data_in_o [ 5 ][ 2 ] = fwd_data_out_i [ 4 ][ 2 ]; // 15 -> 16
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 3 ][ 2 ]; // 13 <- 14
assign fwd_data_in_o [ 4 ][ 2 ] = fwd_data_out_i [ 3 ][ 2 ]; // 14 -> 15
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 2 ][ 2 ]; // 12 <- 13
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 2 ][ 2 ]; // 13 -> 14
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 1 ][ 2 ]; // 11 <- 12
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 1 ][ 2 ]; // 12 -> 13
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 2 ]; // 38 <- 39
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 2 ]; // 39 -> 40
assign back_data_in_o[ 6 ][ 0 ] = back_data_out_i[ 6 ][ 1 ]; // 5 <- 6
assign fwd_data_in_o [ 5 ][ 1 ] = fwd_data_out_i [ 6 ][ 1 ]; // 6 -> 7
assign back_data_in_o[ 6 ][ 1 ] = back_data_out_i[ 5 ][ 1 ]; // 6 <- 7
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 5 ][ 1 ]; // 7 -> 8
assign back_data_in_o[ 5 ][ 1 ] = back_data_out_i[ 4 ][ 1 ]; // 7 <- 8
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 4 ][ 1 ]; // 8 -> 9
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 3 ][ 1 ]; // 8 <- 9
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 9 -> 10
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 9 <- 10
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 2 ][ 1 ]; // 10 -> 11
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 1 ][ 1 ]; // 10 <- 11
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 1 ]; // 11 -> 12
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 1 ]; // 39 <- 40
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 0 ][ 1 ]; // 40 -> 41
assign back_data_in_o[ 5 ][ 0 ] = back_data_out_i[ 6 ][ 0 ]; // 4 <- 5
assign fwd_data_in_o [ 6 ][ 1 ] = fwd_data_out_i [ 6 ][ 0 ]; // 5 -> 6
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 5 ][ 0 ]; // 3 <- 4
assign fwd_data_in_o [ 6 ][ 0 ] = fwd_data_out_i [ 5 ][ 0 ]; // 4 -> 5
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 2 <- 3
assign fwd_data_in_o [ 5 ][ 0 ] = fwd_data_out_i [ 4 ][ 0 ]; // 3 -> 4
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 1 <- 2
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 2 -> 3
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 0 <- 1
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 1 -> 2
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 41 <- 0
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 0 -> 1
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 0 ]; // 40 <- 41
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 0 ][ 0 ]; // 41 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4, 5,
{ b_lp ' (41) , b_lp ' (40) , b_lp ' (39) , b_lp ' (38) , b_lp ' (37) , b_lp ' (36) }, // x = 0
{ b_lp ' (0) , b_lp ' (11) , b_lp ' (12) , b_lp ' (23) , b_lp ' (24) , b_lp ' (35) }, // x = 1
{ b_lp ' (1) , b_lp ' (10) , b_lp ' (13) , b_lp ' (22) , b_lp ' (25) , b_lp ' (34) }, // x = 2
{ b_lp ' (2) , b_lp ' (9) , b_lp ' (14) , b_lp ' (21) , b_lp ' (26) , b_lp ' (33) }, // x = 3
{ b_lp ' (3) , b_lp ' (8) , b_lp ' (15) , b_lp ' (20) , b_lp ' (27) , b_lp ' (32) }, // x = 4
{ b_lp ' (4) , b_lp ' (7) , b_lp ' (16) , b_lp ' (19) , b_lp ' (28) , b_lp ' (31) }, // x = 5
{ b_lp ' (5) , b_lp ' (6) , b_lp ' (17) , b_lp ' (18) , b_lp ' (29) , b_lp ' (30) } // x = 6
};
end
if (x_max_p == 7 && y_max_p == 8 )
begin
assign back_data_in_o[ 6 ][ 6 ] = back_data_out_i[ 6 ][ 7 ]; // 41 <- 42
assign fwd_data_in_o [ 5 ][ 7 ] = fwd_data_out_i [ 6 ][ 7 ]; // 42 -> 43
assign back_data_in_o[ 6 ][ 7 ] = back_data_out_i[ 5 ][ 7 ]; // 42 <- 43
assign fwd_data_in_o [ 4 ][ 7 ] = fwd_data_out_i [ 5 ][ 7 ]; // 43 -> 44
assign back_data_in_o[ 5 ][ 7 ] = back_data_out_i[ 4 ][ 7 ]; // 43 <- 44
assign fwd_data_in_o [ 3 ][ 7 ] = fwd_data_out_i [ 4 ][ 7 ]; // 44 -> 45
assign back_data_in_o[ 4 ][ 7 ] = back_data_out_i[ 3 ][ 7 ]; // 44 <- 45
assign fwd_data_in_o [ 2 ][ 7 ] = fwd_data_out_i [ 3 ][ 7 ]; // 45 -> 46
assign back_data_in_o[ 3 ][ 7 ] = back_data_out_i[ 2 ][ 7 ]; // 45 <- 46
assign fwd_data_in_o [ 1 ][ 7 ] = fwd_data_out_i [ 2 ][ 7 ]; // 46 -> 47
assign back_data_in_o[ 2 ][ 7 ] = back_data_out_i[ 1 ][ 7 ]; // 46 <- 47
assign fwd_data_in_o [ 0 ][ 7 ] = fwd_data_out_i [ 1 ][ 7 ]; // 47 -> 48
assign back_data_in_o[ 1 ][ 7 ] = back_data_out_i[ 0 ][ 7 ]; // 47 <- 48
assign fwd_data_in_o [ 0 ][ 6 ] = fwd_data_out_i [ 0 ][ 7 ]; // 48 -> 49
assign back_data_in_o[ 5 ][ 6 ] = back_data_out_i[ 6 ][ 6 ]; // 40 <- 41
assign fwd_data_in_o [ 6 ][ 7 ] = fwd_data_out_i [ 6 ][ 6 ]; // 41 -> 42
assign back_data_in_o[ 4 ][ 6 ] = back_data_out_i[ 5 ][ 6 ]; // 39 <- 40
assign fwd_data_in_o [ 6 ][ 6 ] = fwd_data_out_i [ 5 ][ 6 ]; // 40 -> 41
assign back_data_in_o[ 3 ][ 6 ] = back_data_out_i[ 4 ][ 6 ]; // 38 <- 39
assign fwd_data_in_o [ 5 ][ 6 ] = fwd_data_out_i [ 4 ][ 6 ]; // 39 -> 40
assign back_data_in_o[ 2 ][ 6 ] = back_data_out_i[ 3 ][ 6 ]; // 37 <- 38
assign fwd_data_in_o [ 4 ][ 6 ] = fwd_data_out_i [ 3 ][ 6 ]; // 38 -> 39
assign back_data_in_o[ 1 ][ 6 ] = back_data_out_i[ 2 ][ 6 ]; // 36 <- 37
assign fwd_data_in_o [ 3 ][ 6 ] = fwd_data_out_i [ 2 ][ 6 ]; // 37 -> 38
assign back_data_in_o[ 1 ][ 5 ] = back_data_out_i[ 1 ][ 6 ]; // 35 <- 36
assign fwd_data_in_o [ 2 ][ 6 ] = fwd_data_out_i [ 1 ][ 6 ]; // 36 -> 37
assign back_data_in_o[ 0 ][ 7 ] = back_data_out_i[ 0 ][ 6 ]; // 48 <- 49
assign fwd_data_in_o [ 0 ][ 5 ] = fwd_data_out_i [ 0 ][ 6 ]; // 49 -> 50
assign back_data_in_o[ 6 ][ 4 ] = back_data_out_i[ 6 ][ 5 ]; // 29 <- 30
assign fwd_data_in_o [ 5 ][ 5 ] = fwd_data_out_i [ 6 ][ 5 ]; // 30 -> 31
assign back_data_in_o[ 6 ][ 5 ] = back_data_out_i[ 5 ][ 5 ]; // 30 <- 31
assign fwd_data_in_o [ 4 ][ 5 ] = fwd_data_out_i [ 5 ][ 5 ]; // 31 -> 32
assign back_data_in_o[ 5 ][ 5 ] = back_data_out_i[ 4 ][ 5 ]; // 31 <- 32
assign fwd_data_in_o [ 3 ][ 5 ] = fwd_data_out_i [ 4 ][ 5 ]; // 32 -> 33
assign back_data_in_o[ 4 ][ 5 ] = back_data_out_i[ 3 ][ 5 ]; // 32 <- 33
assign fwd_data_in_o [ 2 ][ 5 ] = fwd_data_out_i [ 3 ][ 5 ]; // 33 -> 34
assign back_data_in_o[ 3 ][ 5 ] = back_data_out_i[ 2 ][ 5 ]; // 33 <- 34
assign fwd_data_in_o [ 1 ][ 5 ] = fwd_data_out_i [ 2 ][ 5 ]; // 34 -> 35
assign back_data_in_o[ 2 ][ 5 ] = back_data_out_i[ 1 ][ 5 ]; // 34 <- 35
assign fwd_data_in_o [ 1 ][ 6 ] = fwd_data_out_i [ 1 ][ 5 ]; // 35 -> 36
assign back_data_in_o[ 0 ][ 6 ] = back_data_out_i[ 0 ][ 5 ]; // 49 <- 50
assign fwd_data_in_o [ 0 ][ 4 ] = fwd_data_out_i [ 0 ][ 5 ]; // 50 -> 51
assign back_data_in_o[ 5 ][ 4 ] = back_data_out_i[ 6 ][ 4 ]; // 28 <- 29
assign fwd_data_in_o [ 6 ][ 5 ] = fwd_data_out_i [ 6 ][ 4 ]; // 29 -> 30
assign back_data_in_o[ 4 ][ 4 ] = back_data_out_i[ 5 ][ 4 ]; // 27 <- 28
assign fwd_data_in_o [ 6 ][ 4 ] = fwd_data_out_i [ 5 ][ 4 ]; // 28 -> 29
assign back_data_in_o[ 3 ][ 4 ] = back_data_out_i[ 4 ][ 4 ]; // 26 <- 27
assign fwd_data_in_o [ 5 ][ 4 ] = fwd_data_out_i [ 4 ][ 4 ]; // 27 -> 28
assign back_data_in_o[ 2 ][ 4 ] = back_data_out_i[ 3 ][ 4 ]; // 25 <- 26
assign fwd_data_in_o [ 4 ][ 4 ] = fwd_data_out_i [ 3 ][ 4 ]; // 26 -> 27
assign back_data_in_o[ 1 ][ 4 ] = back_data_out_i[ 2 ][ 4 ]; // 24 <- 25
assign fwd_data_in_o [ 3 ][ 4 ] = fwd_data_out_i [ 2 ][ 4 ]; // 25 -> 26
assign back_data_in_o[ 1 ][ 3 ] = back_data_out_i[ 1 ][ 4 ]; // 23 <- 24
assign fwd_data_in_o [ 2 ][ 4 ] = fwd_data_out_i [ 1 ][ 4 ]; // 24 -> 25
assign back_data_in_o[ 0 ][ 5 ] = back_data_out_i[ 0 ][ 4 ]; // 50 <- 51
assign fwd_data_in_o [ 0 ][ 3 ] = fwd_data_out_i [ 0 ][ 4 ]; // 51 -> 52
assign back_data_in_o[ 6 ][ 2 ] = back_data_out_i[ 6 ][ 3 ]; // 17 <- 18
assign fwd_data_in_o [ 5 ][ 3 ] = fwd_data_out_i [ 6 ][ 3 ]; // 18 -> 19
assign back_data_in_o[ 6 ][ 3 ] = back_data_out_i[ 5 ][ 3 ]; // 18 <- 19
assign fwd_data_in_o [ 4 ][ 3 ] = fwd_data_out_i [ 5 ][ 3 ]; // 19 -> 20
assign back_data_in_o[ 5 ][ 3 ] = back_data_out_i[ 4 ][ 3 ]; // 19 <- 20
assign fwd_data_in_o [ 3 ][ 3 ] = fwd_data_out_i [ 4 ][ 3 ]; // 20 -> 21
assign back_data_in_o[ 4 ][ 3 ] = back_data_out_i[ 3 ][ 3 ]; // 20 <- 21
assign fwd_data_in_o [ 2 ][ 3 ] = fwd_data_out_i [ 3 ][ 3 ]; // 21 -> 22
assign back_data_in_o[ 3 ][ 3 ] = back_data_out_i[ 2 ][ 3 ]; // 21 <- 22
assign fwd_data_in_o [ 1 ][ 3 ] = fwd_data_out_i [ 2 ][ 3 ]; // 22 -> 23
assign back_data_in_o[ 2 ][ 3 ] = back_data_out_i[ 1 ][ 3 ]; // 22 <- 23
assign fwd_data_in_o [ 1 ][ 4 ] = fwd_data_out_i [ 1 ][ 3 ]; // 23 -> 24
assign back_data_in_o[ 0 ][ 4 ] = back_data_out_i[ 0 ][ 3 ]; // 51 <- 52
assign fwd_data_in_o [ 0 ][ 2 ] = fwd_data_out_i [ 0 ][ 3 ]; // 52 -> 53
assign back_data_in_o[ 5 ][ 2 ] = back_data_out_i[ 6 ][ 2 ]; // 16 <- 17
assign fwd_data_in_o [ 6 ][ 3 ] = fwd_data_out_i [ 6 ][ 2 ]; // 17 -> 18
assign back_data_in_o[ 4 ][ 2 ] = back_data_out_i[ 5 ][ 2 ]; // 15 <- 16
assign fwd_data_in_o [ 6 ][ 2 ] = fwd_data_out_i [ 5 ][ 2 ]; // 16 -> 17
assign back_data_in_o[ 3 ][ 2 ] = back_data_out_i[ 4 ][ 2 ]; // 14 <- 15
assign fwd_data_in_o [ 5 ][ 2 ] = fwd_data_out_i [ 4 ][ 2 ]; // 15 -> 16
assign back_data_in_o[ 2 ][ 2 ] = back_data_out_i[ 3 ][ 2 ]; // 13 <- 14
assign fwd_data_in_o [ 4 ][ 2 ] = fwd_data_out_i [ 3 ][ 2 ]; // 14 -> 15
assign back_data_in_o[ 1 ][ 2 ] = back_data_out_i[ 2 ][ 2 ]; // 12 <- 13
assign fwd_data_in_o [ 3 ][ 2 ] = fwd_data_out_i [ 2 ][ 2 ]; // 13 -> 14
assign back_data_in_o[ 1 ][ 1 ] = back_data_out_i[ 1 ][ 2 ]; // 11 <- 12
assign fwd_data_in_o [ 2 ][ 2 ] = fwd_data_out_i [ 1 ][ 2 ]; // 12 -> 13
assign back_data_in_o[ 0 ][ 3 ] = back_data_out_i[ 0 ][ 2 ]; // 52 <- 53
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 2 ]; // 53 -> 54
assign back_data_in_o[ 6 ][ 0 ] = back_data_out_i[ 6 ][ 1 ]; // 5 <- 6
assign fwd_data_in_o [ 5 ][ 1 ] = fwd_data_out_i [ 6 ][ 1 ]; // 6 -> 7
assign back_data_in_o[ 6 ][ 1 ] = back_data_out_i[ 5 ][ 1 ]; // 6 <- 7
assign fwd_data_in_o [ 4 ][ 1 ] = fwd_data_out_i [ 5 ][ 1 ]; // 7 -> 8
assign back_data_in_o[ 5 ][ 1 ] = back_data_out_i[ 4 ][ 1 ]; // 7 <- 8
assign fwd_data_in_o [ 3 ][ 1 ] = fwd_data_out_i [ 4 ][ 1 ]; // 8 -> 9
assign back_data_in_o[ 4 ][ 1 ] = back_data_out_i[ 3 ][ 1 ]; // 8 <- 9
assign fwd_data_in_o [ 2 ][ 1 ] = fwd_data_out_i [ 3 ][ 1 ]; // 9 -> 10
assign back_data_in_o[ 3 ][ 1 ] = back_data_out_i[ 2 ][ 1 ]; // 9 <- 10
assign fwd_data_in_o [ 1 ][ 1 ] = fwd_data_out_i [ 2 ][ 1 ]; // 10 -> 11
assign back_data_in_o[ 2 ][ 1 ] = back_data_out_i[ 1 ][ 1 ]; // 10 <- 11
assign fwd_data_in_o [ 1 ][ 2 ] = fwd_data_out_i [ 1 ][ 1 ]; // 11 -> 12
assign back_data_in_o[ 0 ][ 2 ] = back_data_out_i[ 0 ][ 1 ]; // 53 <- 54
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 0 ][ 1 ]; // 54 -> 55
assign back_data_in_o[ 5 ][ 0 ] = back_data_out_i[ 6 ][ 0 ]; // 4 <- 5
assign fwd_data_in_o [ 6 ][ 1 ] = fwd_data_out_i [ 6 ][ 0 ]; // 5 -> 6
assign back_data_in_o[ 4 ][ 0 ] = back_data_out_i[ 5 ][ 0 ]; // 3 <- 4
assign fwd_data_in_o [ 6 ][ 0 ] = fwd_data_out_i [ 5 ][ 0 ]; // 4 -> 5
assign back_data_in_o[ 3 ][ 0 ] = back_data_out_i[ 4 ][ 0 ]; // 2 <- 3
assign fwd_data_in_o [ 5 ][ 0 ] = fwd_data_out_i [ 4 ][ 0 ]; // 3 -> 4
assign back_data_in_o[ 2 ][ 0 ] = back_data_out_i[ 3 ][ 0 ]; // 1 <- 2
assign fwd_data_in_o [ 4 ][ 0 ] = fwd_data_out_i [ 3 ][ 0 ]; // 2 -> 3
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 2 ][ 0 ]; // 0 <- 1
assign fwd_data_in_o [ 3 ][ 0 ] = fwd_data_out_i [ 2 ][ 0 ]; // 1 -> 2
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 55 <- 0
assign fwd_data_in_o [ 2 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 0 -> 1
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 0 ]; // 54 <- 55
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 0 ][ 0 ]; // 55 -> 0
assign id_o =
{
// y = 0, 1, 2, 3, 4, 5, 6, 7,
{ b_lp ' (55) , b_lp ' (54) , b_lp ' (53) , b_lp ' (52) , b_lp ' (51) , b_lp ' (50) , b_lp ' (49) , b_lp ' (48) }, // x = 0
{ b_lp ' (0) , b_lp ' (11) , b_lp ' (12) , b_lp ' (23) , b_lp ' (24) , b_lp ' (35) , b_lp ' (36) , b_lp ' (47) }, // x = 1
{ b_lp ' (1) , b_lp ' (10) , b_lp ' (13) , b_lp ' (22) , b_lp ' (25) , b_lp ' (34) , b_lp ' (37) , b_lp ' (46) }, // x = 2
{ b_lp ' (2) , b_lp ' (9) , b_lp ' (14) , b_lp ' (21) , b_lp ' (26) , b_lp ' (33) , b_lp ' (38) , b_lp ' (45) }, // x = 3
{ b_lp ' (3) , b_lp ' (8) , b_lp ' (15) , b_lp ' (20) , b_lp ' (27) , b_lp ' (32) , b_lp ' (39) , b_lp ' (44) }, // x = 4
{ b_lp ' (4) , b_lp ' (7) , b_lp ' (16) , b_lp ' (19) , b_lp ' (28) , b_lp ' (31) , b_lp ' (40) , b_lp ' (43) }, // x = 5
{ b_lp ' (5) , b_lp ' (6) , b_lp ' (17) , b_lp ' (18) , b_lp ' (29) , b_lp ' (30) , b_lp ' (41) , b_lp ' (42) } // x = 6
};
end
if (x_max_p == 1 && y_max_p == 2 )
begin
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 0 ][ 1 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 0 ][ 1 ]; // 1 -> 0
assign back_data_in_o[ 0 ][ 1 ] = back_data_out_i[ 0 ][ 0 ]; // 1 <- 0
assign fwd_data_in_o [ 0 ][ 1 ] = fwd_data_out_i [ 0 ][ 0 ]; // 0 -> 1
assign id_o =
{
// y = 0, 1,
{ b_lp ' (0) , b_lp ' (1) } // x = 0
};
end
if (x_max_p == 2 && y_max_p == 1 )
begin
assign back_data_in_o[ 0 ][ 0 ] = back_data_out_i[ 1 ][ 0 ]; // 0 <- 1
assign fwd_data_in_o [ 0 ][ 0 ] = fwd_data_out_i [ 1 ][ 0 ]; // 1 -> 0
assign back_data_in_o[ 1 ][ 0 ] = back_data_out_i[ 0 ][ 0 ]; // 1 <- 0
assign fwd_data_in_o [ 1 ][ 0 ] = fwd_data_out_i [ 0 ][ 0 ]; // 0 -> 1
assign id_o =
{
// y = 0,
{ b_lp ' (0) }, // x = 0
{ b_lp ' (1) } // x = 1
};
end
initial assert ((x_max_p <= 8) && (y_max_p <= 8)) else begin $error("%m x_max_p %d or y_max_p %d too large; rerun generator with larger size than %d/%d",x_max_p,y_max_p,8,8); $finish(); end
endmodule
`BSG_ABSTRACT_MODULE(bsg_mesh_to_ring_stitch)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAP_2_V
`define SKY130_FD_SC_LP__TAP_2_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog wrapper for tap with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__tap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__tap_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__tap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__tap_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__tap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAP_2_V
|
`define DdrCtl1_NOP 4'h0
`define DdrCtl1_LA0 4'h1
`define DdrCtl1_LA1 4'h2
`define DdrCtl1_LA2 4'h3
`define DdrCtl1_LA3 4'h4
`define DdrCtl1_LD0 4'h5
`define DdrCtl1_LD1 4'h6
`define DdrCtl1_LD2 4'h7
`define DdrCtl1_LD3 4'h8
`define DdrCtl1_RDP 4'h9
`define DdrCtl1_WRP 4'hA
`define DdrCtl1_DdrCommand_PowerUp 5'b00000
`define DdrCtl1_DdrCommand_Deselect 5'b11000
`define DdrCtl1_DdrCommand_NoOperation 5'b10111
`define DdrCtl1_DdrCommand_Activate 5'b10011
`define DdrCtl1_DdrCommand_Read 5'b10101
`define DdrCtl1_DdrCommand_Write 5'b10100
`define DdrCtl1_DdrCommand_BurtTerminate 5'b10110
`define DdrCtl1_DdrCommand_PreCharge 5'b10010
`define DdrCtl1_DdrCommand_AutoRefresh 5'b10001
`define DdrCtl1_DdrCommand_SelfRefresh 5'b00001
`define DdrCtl1_DdrCommand_LoadModeRegister 5'b10000
`define DdrCtl1_DdrMode_BurstLength_2 3'b001
`define DdrCtl1_DdrMode_BurstLength_4 3'b010
`define DdrCtl1_DdrMode_BurstLength_8 3'b011
`define DdrCtl1_DdrMode_BurstType_Sequential 1'b0
`define DdrCtl1_DdrMode_BurstType_Interleaved 1'b1
`define DdrCtl1_DdrMode_CASLatency_2 3'b010
`define DdrCtl1_DdrMode_CASLatency_3 3'b011
`define DdrCtl1_DdrMode_CASLatency_2_5 3'b110
`define DdrCtl1_DdrMode_OperatingMode_Normal 6'b000000
`define DdrCtl1_DdrMode_OperatingMode_NormalResetDLL 6'b000010
`define DdrCtl1_DdrModeExtend_DLL_Enable 1'b0
`define DdrCtl1_DdrModeExtend_DLL_Disable 1'b1
`define DdrCtl1_DdrModeExtend_DriveStrength_Normal 1'b0
`define DdrCtl1_DdrModeExtend_DriveStrength_Reduced 1'b1
`define DdrCtl1_DdrModeExtend_OperatingMode_Reserved 11'b00000000000
`define DdrCtl1_SelectModeRegister_Normal 2'b00
`define DdrCtl1_SelectModeRegister_Extended 2'b01
`define DdrCtl1_IntfState_Reset 3'h0
`define DdrCtl1_IntfState_WaitInit 3'h1
`define DdrCtl1_IntfState_Ready 3'h2
`define DdrCtl1_IntfState_WaitRead 3'h3
`define DdrCtl1_IntfState_WaitWrite 3'h4
`define DdrCtl1_IntfState_Error 3'h5
`define DdrCtl1_CoreState_Reset 4'h0
`define DdrCtl1_CoreState_WaitInit 4'h1
`define DdrCtl1_CoreState_Ready 4'h2
`define DdrCtl1_CoreState_Refresh_AutoRefresh 4'h3
`define DdrCtl1_CoreState_Refresh_Wait0 4'h4
`define DdrCtl1_CoreState_Refresh_Wait1 4'h5
`define DdrCtl1_CoreState_Refresh_Wait2 4'h6
`define DdrCtl1_CoreState_Read_Activate 4'h7
`define DdrCtl1_CoreState_Read_Read 4'h8
`define DdrCtl1_CoreState_Read_Wait0 4'h9
`define DdrCtl1_CoreState_Read_Wait1 4'hA
`define DdrCtl1_CoreState_Write_Activate 4'hB
`define DdrCtl1_CoreState_Write_Write 4'hC
`define DdrCtl1_CoreState_Write_Wait0 4'hD
`define DdrCtl1_CoreState_Write_Wait1 4'hE
`define DdrCtl1_CoreState_Error 4'hF
`define DdrCtl1_InitState_Reset 5'h00
`define DdrCtl1_InitState_PowerUp 5'h01
`define DdrCtl1_InitState_Wait200us 5'h02
`define DdrCtl1_InitState_BringCKEHigh 5'h03
`define DdrCtl1_InitState_PreChargeAll0 5'h04
`define DdrCtl1_InitState_EnableDLL 5'h05
`define DdrCtl1_InitState_ProgramMRResetDLL 5'h06
`define DdrCtl1_InitState_WaitMRD200 5'h07
`define DdrCtl1_InitState_PreChargeAll1 5'h08
`define DdrCtl1_InitState_Refresh0_AutoRefresh 5'h09
`define DdrCtl1_InitState_Refresh0_Wait0 5'h0A
`define DdrCtl1_InitState_Refresh0_Wait1 5'h0B
`define DdrCtl1_InitState_Refresh0_Wait2 5'h0C
`define DdrCtl1_InitState_Refresh1_AutoRefresh 5'h0D
`define DdrCtl1_InitState_Refresh1_Wait0 5'h0E
`define DdrCtl1_InitState_Refresh1_Wait1 5'h0F
`define DdrCtl1_InitState_Refresh1_Wait2 5'h10
`define DdrCtl1_InitState_ClearDLL 5'h11
`define DdrCtl1_InitState_Initialized 5'h12
`define DdrCtl1_InitState_Error 5'h13
module DdrCtl1(clock0,clock90,reset,inst,inst_en,page,ready,ddr_clock0,ddr_clock90,ddr_clock270,ddr_cke,ddr_csn,ddr_rasn,ddr_casn,ddr_wen,ddr_ba,ddr_addr,ddr_dm,ddr_dq,ddr_dqs);
input wire clock0;
input wire clock90;
input wire reset;
input wire [11:0] inst;
input wire inst_en;
output wire [31:0] page;
output wire ready;
input wire ddr_clock0;
input wire ddr_clock90;
input wire ddr_clock270;
output reg ddr_cke;
output reg ddr_csn;
output reg ddr_rasn;
output reg ddr_casn;
output reg ddr_wen;
output reg [1:0] ddr_ba;
output reg [12:0] ddr_addr;
output wire [1:0] ddr_dm;
inout wire [15:0] ddr_dq;
inout wire [1:0] ddr_dqs;
wire i_Ready;
reg [2:0] s_IntfState;
reg [31:0] s_IntfAddress;
reg [31:0] s_IntfPage;
reg i_IntfDoRead;
reg i_IntfDoWrite;
reg [3:0] s_CoreState;
reg [4:0] i_CoreCommand;
reg [1:0] i_CoreBank;
reg [12:0] i_CoreAddr;
reg i_CoreTakeCommand0;
reg i_CoreTakeCommand1;
reg i_CoreTakeCommand2;
reg i_CoreTakeCommand3;
reg i_CoreRefreshDone;
reg i_CoreReadDone;
reg i_CoreWriteDone;
reg [4:0] s_InitState;
reg [4:0] i_InitCommand;
reg [1:0] i_InitBank;
reg [12:0] i_InitAddr;
reg i_InitTakeCommand0;
reg i_InitTakeCommand1;
reg i_InitDone;
reg i_InitDo200us;
reg i_InitDo200;
reg [8:0] s_AutoRefreshCounter;
reg i_AutoRefreshDoRefresh;
reg [13:0] s_InitCnt200usCounter;
reg i_InitCnt200usDone;
reg [7:0] s_InitCnt200Counter;
reg i_InitCnt200Done;
reg [15:0] s_HalfPage0;
reg [15:0] s_HalfPage1;
wire [3:0] w_InstCode;
wire [7:0] w_InstImm;
reg [256*8-1:0] d_Input;
reg [256*8-1:0] d_IntfState;
reg [256*8-1:0] d_CoreState;
reg [256*8-1:0] d_InitState;
reg [256*8-1:0] d_AutoRefreshCounter;
reg [256*8-1:0] d_InitCnt200usCounter;
reg [256*8-1:0] d_InitCnt200Counter;
// synthesis attribute fsm_encoding of s_IntfState is speed1;
// synthesis attribute fsm_encoding of s_CoreState is speed1;
// synthesis attribute fsm_encoding of s_InitState is speed1;
assign page = s_IntfPage;
assign ready = i_Ready;
always @ * begin
if (i_InitDone) begin
if (i_CoreTakeCommand0 && clock90 == 1) begin
ddr_cke = i_CoreCommand[4];
ddr_csn = i_CoreCommand[3];
ddr_rasn = i_CoreCommand[2];
ddr_casn = i_CoreCommand[1];
ddr_wen = i_CoreCommand[0];
ddr_ba = i_CoreBank;
ddr_addr = i_CoreAddr;
end
else begin
ddr_cke = 1;
ddr_csn = 0;
ddr_rasn = 1;
ddr_casn = 1;
ddr_wen = 1;
ddr_ba = 2'b00;
ddr_addr = 13'b0000000000000;
end
end // if (i_InitDone)
else begin
if (i_InitTakeCommand0 || (i_InitTakeCommand1 && clock90 == 1)) begin
ddr_cke = i_InitCommand[4];
ddr_csn = i_InitCommand[3];
ddr_rasn = i_InitCommand[2];
ddr_casn = i_InitCommand[1];
ddr_wen = i_InitCommand[0];
ddr_ba = i_InitBank;
ddr_addr = i_InitAddr;
end
else begin
ddr_cke = 1;
ddr_csn = 0;
ddr_rasn = 1;
ddr_casn = 1;
ddr_wen = 1;
ddr_ba = 2'b00;
ddr_addr = 13'b0000000000000;
end
end // else: !if(i_InitDone)
end // always @ *
assign ddr_dm = 2'b00;
assign ddr_dq = i_CoreTakeCommand1 ? (ddr_clock90 == 0 ? s_IntfPage[31:16] : s_IntfPage[15:0]) : 16'bzzzzzzzzzzzzzzzz;
assign ddr_dqs = (i_CoreTakeCommand2 || i_CoreTakeCommand3) ? {ddr_clock0,ddr_clock0} : 2'bzz;
assign w_InstCode = inst[11:8];
assign w_InstImm = inst[7:0];
assign i_Ready = s_IntfState == `DdrCtl1_IntfState_Ready &&
s_CoreState == `DdrCtl1_CoreState_Ready &&
w_InstCode != `DdrCtl1_RDP &&
w_InstCode != `DdrCtl1_WRP;
always @ (posedge clock0) begin
if (reset) begin
s_IntfState <= `DdrCtl1_IntfState_Reset;
s_IntfAddress <= 0;
s_IntfPage <= 0;
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end
else begin
case (s_IntfState)
`DdrCtl1_IntfState_Reset: begin
s_IntfState <= `DdrCtl1_IntfState_WaitInit;
s_IntfAddress <= 0;
s_IntfPage <= 0;
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end
`DdrCtl1_IntfState_WaitInit: begin
if (i_InitDone) begin
s_IntfState <= `DdrCtl1_IntfState_Ready;
s_IntfAddress <= 0;
s_IntfPage <= 0;
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end
else begin
s_IntfState <= `DdrCtl1_IntfState_WaitInit;
s_IntfAddress <= 0;
s_IntfPage <= 0;
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end
end // case: `DdrCtl1_IntfState_WaitInit
`DdrCtl1_IntfState_Ready: begin
if (inst_en) begin
case (w_InstCode)
`DdrCtl1_NOP: begin
s_IntfState <= `DdrCtl1_IntfState_Ready;
s_IntfAddress <= s_IntfAddress;
s_IntfPage <= s_IntfPage;
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end
`DdrCtl1_LA0: begin
s_IntfState <= `DdrCtl1_IntfState_Ready;
s_IntfAddress <= {s_IntfAddress[31:8],w_InstImm};
s_IntfPage <= s_IntfPage;
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end
`DdrCtl1_LA1: begin
s_IntfState <= `DdrCtl1_IntfState_Ready;
s_IntfAddress <= {s_IntfAddress[31:16],w_InstImm,s_IntfAddress[7:0]};
s_IntfPage <= s_IntfPage;
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end
`DdrCtl1_LA2: begin
s_IntfState <= `DdrCtl1_IntfState_Ready;
s_IntfAddress <= {s_IntfAddress[31:24],w_InstImm,s_IntfAddress[15:0]};
s_IntfPage <= s_IntfPage;
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end
`DdrCtl1_LA3: begin
s_IntfState <= `DdrCtl1_IntfState_Ready;
s_IntfAddress <= {w_InstImm,s_IntfAddress[23:0]};
s_IntfPage <= s_IntfPage;
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end
`DdrCtl1_LD0: begin
s_IntfState <= `DdrCtl1_IntfState_Ready;
s_IntfAddress <= s_IntfAddress;
s_IntfPage <= {s_IntfPage[31:8],w_InstImm};
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end
`DdrCtl1_LD1: begin
s_IntfState <= `DdrCtl1_IntfState_Ready;
s_IntfAddress <= s_IntfAddress;
s_IntfPage <= {s_IntfPage[31:16],w_InstImm,s_IntfPage[7:0]};
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end
`DdrCtl1_LD2: begin
s_IntfState <= `DdrCtl1_IntfState_Ready;
s_IntfAddress <= s_IntfAddress;
s_IntfPage <= {s_IntfPage[31:24],w_InstImm,s_IntfPage[15:0]};
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end
`DdrCtl1_LD3: begin
s_IntfState <= `DdrCtl1_IntfState_Ready;
s_IntfAddress <= s_IntfAddress;
s_IntfPage <= {w_InstImm,s_IntfPage[23:0]};
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end
`DdrCtl1_RDP: begin
s_IntfState <= `DdrCtl1_IntfState_WaitRead;
s_IntfAddress <= s_IntfAddress;
s_IntfPage <= s_IntfPage;
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end
`DdrCtl1_WRP: begin
s_IntfState <= `DdrCtl1_IntfState_WaitWrite;
s_IntfAddress <= s_IntfAddress;
s_IntfPage <= s_IntfPage;
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end
default: begin
s_IntfState <= `DdrCtl1_IntfState_Error;
s_IntfAddress <= 0;
s_IntfPage <= 0;
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
s_IntfState <= `DdrCtl1_IntfState_Ready;
s_IntfAddress <= s_IntfAddress;
s_IntfPage <= s_IntfPage;
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end // else: !if(inst_en)
end // case: `DdrCtl1_IntfState_Ready
`DdrCtl1_IntfState_WaitRead: begin
if (i_CoreReadDone) begin
s_IntfState <= `DdrCtl1_IntfState_Ready;
s_IntfAddress <= s_IntfAddress;
s_IntfPage <= {s_HalfPage0,s_HalfPage1};
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end
else begin
s_IntfState <= `DdrCtl1_IntfState_WaitRead;
s_IntfAddress <= s_IntfAddress;
s_IntfPage <= s_IntfPage;
i_IntfDoRead <= 1;
i_IntfDoWrite <= 0;
end
end // case: `DdrCtl1_IntfState_WaitRead
`DdrCtl1_IntfState_WaitWrite: begin
if (i_CoreWriteDone) begin
s_IntfState <= `DdrCtl1_IntfState_Ready;
s_IntfAddress <= s_IntfAddress;
s_IntfPage <= s_IntfPage;
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end
else begin
s_IntfState <= `DdrCtl1_IntfState_WaitWrite;
s_IntfAddress <= s_IntfAddress;
s_IntfPage <= s_IntfPage;
i_IntfDoRead <= 0;
i_IntfDoWrite <= 1;
end
end // case: `DdrCtl1_IntfState_WaitRead
`DdrCtl1_IntfState_Error: begin
s_IntfState <= `DdrCtl1_IntfState_Error;
s_IntfAddress <= 0;
s_IntfPage <= 0;
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end
default: begin
s_IntfState <= `DdrCtl1_IntfState_Error;
s_IntfAddress <= 0;
s_IntfPage <= 0;
i_IntfDoRead <= 0;
i_IntfDoWrite <= 0;
end
endcase // case (s_IntfState)
end // else: !if(reset)
end // always @ (posedge clock0)
always @ (posedge clock0) begin
if (reset) begin
s_CoreState <= `DdrCtl1_CoreState_Reset;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
else begin
case (s_CoreState)
`DdrCtl1_CoreState_Reset: begin
s_CoreState <= `DdrCtl1_CoreState_WaitInit;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
`DdrCtl1_CoreState_WaitInit: begin
if (i_InitDone) begin
s_CoreState <= `DdrCtl1_CoreState_Ready;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
else begin
s_CoreState <= `DdrCtl1_CoreState_WaitInit;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
end
`DdrCtl1_CoreState_Ready: begin
case ({i_AutoRefreshDoRefresh,i_IntfDoRead,i_IntfDoWrite})
3'b000: begin
s_CoreState <= `DdrCtl1_CoreState_Ready;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
3'b001: begin
s_CoreState <= `DdrCtl1_CoreState_Write_Activate;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
3'b010: begin
s_CoreState <= `DdrCtl1_CoreState_Read_Activate;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
3'b011: begin
s_CoreState <= `DdrCtl1_CoreState_Read_Activate;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
3'b100: begin
s_CoreState <= `DdrCtl1_CoreState_Refresh_AutoRefresh;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
3'b101: begin
s_CoreState <= `DdrCtl1_CoreState_Refresh_AutoRefresh;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
3'b110: begin
s_CoreState <= `DdrCtl1_CoreState_Refresh_AutoRefresh;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
3'b111: begin
s_CoreState <= `DdrCtl1_CoreState_Refresh_AutoRefresh;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
endcase // case ({i_RefreshDoAutoRefresh,i_IntfDoRead,i_IntfDoWrite})
end // case: `DdrCtl1_CoreState_Ready
`DdrCtl1_CoreState_Refresh_AutoRefresh: begin
s_CoreState <= `DdrCtl1_CoreState_Refresh_Wait0;
i_CoreCommand <= `DdrCtl1_DdrCommand_AutoRefresh;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 1;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
`DdrCtl1_CoreState_Refresh_Wait0: begin
s_CoreState <= `DdrCtl1_CoreState_Refresh_Wait1;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
`DdrCtl1_CoreState_Refresh_Wait1: begin
s_CoreState <= `DdrCtl1_CoreState_Refresh_Wait2;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 1;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
`DdrCtl1_CoreState_Refresh_Wait2: begin
s_CoreState <= `DdrCtl1_CoreState_Ready;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
`DdrCtl1_CoreState_Read_Activate: begin
s_CoreState <= `DdrCtl1_CoreState_Read_Read;
i_CoreCommand <= `DdrCtl1_DdrCommand_Activate;
i_CoreBank <= s_IntfAddress[24:23];
i_CoreAddr <= s_IntfAddress[22:10];
i_CoreTakeCommand0 <= 1;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
`DdrCtl1_CoreState_Read_Read: begin
s_CoreState <= `DdrCtl1_CoreState_Read_Wait0;
i_CoreCommand <= `DdrCtl1_DdrCommand_Read;
i_CoreBank <= s_IntfAddress[24:23];
i_CoreAddr <= {3'b001,s_IntfAddress[9:0]};
i_CoreTakeCommand0 <= 1;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
`DdrCtl1_CoreState_Read_Wait0: begin
s_CoreState <= `DdrCtl1_CoreState_Read_Wait1;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 1;
i_CoreWriteDone <= 0;
end
`DdrCtl1_CoreState_Read_Wait1: begin
s_CoreState <= `DdrCtl1_CoreState_Ready;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
`DdrCtl1_CoreState_Write_Activate: begin
s_CoreState <= `DdrCtl1_CoreState_Write_Write;
i_CoreCommand <= `DdrCtl1_DdrCommand_Activate;
i_CoreBank <= s_IntfAddress[24:23];
i_CoreAddr <= s_IntfAddress[22:10];
i_CoreTakeCommand0 <= 1;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
`DdrCtl1_CoreState_Write_Write: begin
s_CoreState <= `DdrCtl1_CoreState_Write_Wait0;
i_CoreCommand <= `DdrCtl1_DdrCommand_Write;
i_CoreBank <= s_IntfAddress[24:23];
i_CoreAddr <= {3'b001,s_IntfAddress[9:0]};
i_CoreTakeCommand0 <= 1;
i_CoreTakeCommand1 <= 1;
i_CoreTakeCommand2 <= 1;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
`DdrCtl1_CoreState_Write_Wait0: begin
s_CoreState <= `DdrCtl1_CoreState_Write_Wait1;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 1;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 1;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 1;
end
`DdrCtl1_CoreState_Write_Wait1: begin
s_CoreState <= `DdrCtl1_CoreState_Ready;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end // case: `DdrCtl1_CoreState_Write_Wait1
`DdrCtl1_CoreState_Error: begin
s_CoreState <= `DdrCtl1_CoreState_Error;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
default: begin
s_CoreState <= `DdrCtl1_CoreState_Error;
i_CoreCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_CoreBank <= 0;
i_CoreAddr <= 0;
i_CoreTakeCommand0 <= 0;
i_CoreTakeCommand1 <= 0;
i_CoreTakeCommand2 <= 0;
i_CoreTakeCommand3 <= 0;
i_CoreRefreshDone <= 0;
i_CoreReadDone <= 0;
i_CoreWriteDone <= 0;
end
endcase // case (s_CoreState)
end // else: !if(reset)
end // always @ (posedge clock0)
always @ (posedge clock0) begin
if (reset) begin
s_InitState <= `DdrCtl1_InitState_Reset;
i_InitCommand <= `DdrCtl1_DdrCommand_PowerUp;
i_InitBank <= 0;
i_InitAddr <= 0;
i_InitTakeCommand0 <= 1;
i_InitTakeCommand1 <= 0;
i_InitDone <= 0;
i_InitDo200us <= 0;
i_InitDo200 <= 0;
end
else begin
case (s_InitState)
`DdrCtl1_InitState_Reset: begin
s_InitState <= `DdrCtl1_InitState_PowerUp;
i_InitCommand <= `DdrCtl1_DdrCommand_PowerUp;
i_InitBank <= 0;
i_InitAddr <= 0;
i_InitTakeCommand0 <= 1;
i_InitTakeCommand1 <= 0;
i_InitDone <= 0;
i_InitDo200us <= 0;
i_InitDo200 <= 0;
end
`DdrCtl1_InitState_PowerUp: begin
s_InitState <= `DdrCtl1_InitState_Wait200us;
i_InitCommand <= `DdrCtl1_DdrCommand_PowerUp;
i_InitBank <= 0;
i_InitAddr <= 0;
i_InitTakeCommand0 <= 1;
i_InitTakeCommand1 <= 0;
i_InitDone <= 0;
i_InitDo200us <= 0;
i_InitDo200 <= 0;
end
`DdrCtl1_InitState_Wait200us: begin
if (i_InitCnt200usDone) begin
s_InitState <= `DdrCtl1_InitState_BringCKEHigh;
i_InitCommand <= `DdrCtl1_DdrCommand_PowerUp;
i_InitBank <= 0;
i_InitAddr <= 0;
i_InitTakeCommand0 <= 1;
i_InitTakeCommand1 <= 0;
i_InitDone <= 0;
i_InitDo200us <= 1;
i_InitDo200 <= 0;
end
else begin
s_InitState <= `DdrCtl1_InitState_Wait200us;
i_InitCommand <= `DdrCtl1_DdrCommand_PowerUp;
i_InitBank <= 0;
i_InitAddr <= 0;
i_InitTakeCommand0 <= 1;
i_InitTakeCommand1 <= 0;
i_InitDone <= 0;
i_InitDo200us <= 1;
i_InitDo200 <= 0;
end
end
`DdrCtl1_InitState_BringCKEHigh: begin
s_InitState <= `DdrCtl1_InitState_PreChargeAll0;
i_InitCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_InitBank <= 0;
i_InitAddr <= 0;
i_InitTakeCommand0 <= 0;
i_InitTakeCommand1 <= 0;
i_InitDone <= 0;
i_InitDo200us <= 0;
i_InitDo200 <= 0;
end
`DdrCtl1_InitState_PreChargeAll0: begin
s_InitState <= `DdrCtl1_InitState_EnableDLL;
i_InitCommand <= `DdrCtl1_DdrCommand_PreCharge;
i_InitBank <= 0;
i_InitTakeCommand0 <= 0;
i_InitTakeCommand1 <= 1;
i_InitAddr <= 13'b0010000000000;
i_InitDone <= 0;
i_InitDo200us <= 0;
i_InitDo200 <= 0;
end
`DdrCtl1_InitState_EnableDLL: begin
s_InitState <= `DdrCtl1_InitState_ProgramMRResetDLL;
i_InitCommand <= `DdrCtl1_DdrCommand_LoadModeRegister;
i_InitBank <= `DdrCtl1_SelectModeRegister_Extended;
i_InitAddr <= {`DdrCtl1_DdrModeExtend_OperatingMode_Reserved,
`DdrCtl1_DdrModeExtend_DriveStrength_Normal,
`DdrCtl1_DdrModeExtend_DLL_Enable};
i_InitTakeCommand0 <= 0;
i_InitTakeCommand1 <= 1;
i_InitDone <= 0;
i_InitDo200us <= 0;
i_InitDo200 <= 0;
end
`DdrCtl1_InitState_ProgramMRResetDLL: begin
s_InitState <= `DdrCtl1_InitState_WaitMRD200;
i_InitCommand <= `DdrCtl1_DdrCommand_LoadModeRegister;
i_InitBank <= `DdrCtl1_SelectModeRegister_Normal;
i_InitAddr <= {`DdrCtl1_DdrMode_OperatingMode_NormalResetDLL,
`DdrCtl1_DdrMode_CASLatency_2,
`DdrCtl1_DdrMode_BurstType_Sequential,
`DdrCtl1_DdrMode_BurstLength_2};
i_InitTakeCommand0 <= 0;
i_InitTakeCommand1 <= 1;
i_InitDone <= 0;
i_InitDo200us <= 0;
i_InitDo200 <= 0;
end
`DdrCtl1_InitState_WaitMRD200: begin
if (i_InitCnt200Done) begin
s_InitState <= `DdrCtl1_InitState_PreChargeAll1;
i_InitCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_InitBank <= 0;
i_InitTakeCommand0 <= 0;
i_InitTakeCommand1 <= 0;
i_InitAddr <= 0;
i_InitDone <= 0;
i_InitDo200us <= 0;
i_InitDo200 <= 1;
end
else begin
s_InitState <= `DdrCtl1_InitState_WaitMRD200;
i_InitCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_InitBank <= 0;
i_InitTakeCommand0 <= 0;
i_InitTakeCommand1 <= 0;
i_InitAddr <= 0;
i_InitDone <= 0;
i_InitDo200us <= 0;
i_InitDo200 <= 1;
end
end
`DdrCtl1_InitState_PreChargeAll1: begin
s_InitState <= `DdrCtl1_InitState_Refresh0_AutoRefresh;
i_InitCommand <= `DdrCtl1_DdrCommand_PreCharge;
i_InitBank <= 0;
i_InitAddr <= 13'b0010000000000;
i_InitTakeCommand0 <= 0;
i_InitTakeCommand1 <= 1;
i_InitDone <= 0;
i_InitDo200us <= 0;
i_InitDo200 <= 0;
end
`DdrCtl1_InitState_Refresh0_AutoRefresh: begin
s_InitState <= `DdrCtl1_InitState_Refresh0_Wait0;
i_InitCommand <= `DdrCtl1_DdrCommand_AutoRefresh;
i_InitBank <= 0;
i_InitAddr <= 0;
i_InitTakeCommand0 <= 0;
i_InitTakeCommand1 <= 1;
i_InitDone <= 0;
i_InitDo200us <= 0;
i_InitDo200 <= 0;
end
`DdrCtl1_InitState_Refresh0_Wait0: begin
s_InitState <= `DdrCtl1_InitState_Refresh0_Wait1;
i_InitCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_InitBank <= 0;
i_InitAddr <= 0;
i_InitTakeCommand0 <= 0;
i_InitTakeCommand1 <= 0;
i_InitDone <= 0;
i_InitDo200us <= 0;
i_InitDo200 <= 0;
end
`DdrCtl1_InitState_Refresh0_Wait1: begin
s_InitState <= `DdrCtl1_InitState_Refresh0_Wait2;
i_InitCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_InitBank <= 0;
i_InitAddr <= 0;
i_InitTakeCommand0 <= 0;
i_InitTakeCommand1 <= 0;
i_InitDone <= 0;
i_InitDo200us <= 0;
i_InitDo200 <= 0;
end
`DdrCtl1_InitState_Refresh0_Wait2: begin
s_InitState <= `DdrCtl1_InitState_Refresh1_AutoRefresh;
i_InitCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_InitBank <= 0;
i_InitAddr <= 0;
i_InitTakeCommand0 <= 0;
i_InitTakeCommand1 <= 0;
i_InitDone <= 0;
i_InitDo200us <= 0;
i_InitDo200 <= 0;
end
`DdrCtl1_InitState_Refresh1_AutoRefresh: begin
s_InitState <= `DdrCtl1_InitState_Refresh1_Wait0;
i_InitCommand <= `DdrCtl1_DdrCommand_AutoRefresh;
i_InitBank <= 0;
i_InitAddr <= 0;
i_InitTakeCommand0 <= 0;
i_InitTakeCommand1 <= 1;
i_InitDone <= 0;
i_InitDo200us <= 0;
i_InitDo200 <= 0;
end
`DdrCtl1_InitState_Refresh1_Wait0: begin
s_InitState <= `DdrCtl1_InitState_Refresh1_Wait1;
i_InitCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_InitBank <= 0;
i_InitAddr <= 0;
i_InitTakeCommand0 <= 0;
i_InitTakeCommand1 <= 0;
i_InitDone <= 0;
i_InitDo200us <= 0;
i_InitDo200 <= 0;
end
`DdrCtl1_InitState_Refresh1_Wait1: begin
s_InitState <= `DdrCtl1_InitState_Refresh1_Wait2;
i_InitCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_InitBank <= 0;
i_InitAddr <= 0;
i_InitTakeCommand0 <= 0;
i_InitTakeCommand1 <= 0;
i_InitDone <= 0;
i_InitDo200us <= 0;
i_InitDo200 <= 0;
end
`DdrCtl1_InitState_Refresh1_Wait2: begin
s_InitState <= `DdrCtl1_InitState_ClearDLL;
i_InitCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_InitBank <= 0;
i_InitAddr <= 0;
i_InitTakeCommand0 <= 0;
i_InitTakeCommand1 <= 0;
i_InitDone <= 0;
i_InitDo200us <= 0;
i_InitDo200 <= 0;
end
`DdrCtl1_InitState_ClearDLL: begin
s_InitState <= `DdrCtl1_InitState_Initialized;
i_InitCommand <= `DdrCtl1_DdrCommand_LoadModeRegister;
i_InitBank <= `DdrCtl1_SelectModeRegister_Normal;
i_InitAddr <= {`DdrCtl1_DdrMode_OperatingMode_Normal,
`DdrCtl1_DdrMode_CASLatency_2,
`DdrCtl1_DdrMode_BurstType_Sequential,
`DdrCtl1_DdrMode_BurstLength_2};
i_InitDone <= 0;
i_InitTakeCommand0 <= 0;
i_InitTakeCommand1 <= 1;
i_InitDo200us <= 0;
i_InitDo200 <= 0;
end
`DdrCtl1_InitState_Initialized: begin
s_InitState <= `DdrCtl1_InitState_Initialized;
i_InitCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_InitBank <= 0;
i_InitAddr <= 0;
i_InitTakeCommand0 <= 0;
i_InitTakeCommand1 <= 0;
i_InitDone <= 1;
i_InitDo200us <= 0;
i_InitDo200 <= 0;
end // case: `DdrCtl1_InitState_Initialized
`DdrCtl1_InitState_Error: begin
s_InitState <= `DdrCtl1_InitState_Error;
i_InitCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_InitBank <= 0;
i_InitAddr <= 0;
i_InitTakeCommand0 <= 0;
i_InitTakeCommand1 <= 0;
i_InitDone <= 1;
i_InitDo200us <= 0;
i_InitDo200 <= 0;
end
default: begin
s_InitState <= `DdrCtl1_InitState_Error;
i_InitCommand <= `DdrCtl1_DdrCommand_NoOperation;
i_InitBank <= 0;
i_InitAddr <= 0;
i_InitTakeCommand0 <= 0;
i_InitTakeCommand1 <= 0;
i_InitDone <= 1;
i_InitDo200us <= 0;
i_InitDo200 <= 0;
end
endcase // case (s_InitState)
end // else: !if(reset)
end // always @ (posedge init0)
always @ (posedge clock0) begin
if (reset) begin
s_AutoRefreshCounter <= 0;
i_AutoRefreshDoRefresh <= 0;
end
else begin
if (i_InitDone) begin
if (s_AutoRefreshCounter == 320) begin
if (i_CoreRefreshDone) begin
s_AutoRefreshCounter <= 0;
i_AutoRefreshDoRefresh <= 0;
end
else begin
s_AutoRefreshCounter <= s_AutoRefreshCounter;
i_AutoRefreshDoRefresh <= 1;
end
end
else begin
s_AutoRefreshCounter <= s_AutoRefreshCounter + 1;
i_AutoRefreshDoRefresh <= 0;
end // else: !if(i_InitDone)
end // if (i_InitDone)
else begin
s_AutoRefreshCounter <= 0;
end // else: !if(i_InitDone)
end // else: !if(reset)
end // always @ (posedge clock0)
always @ (posedge clock0) begin
if (reset) begin
s_InitCnt200usCounter <= 0;
i_InitCnt200usDone <= 0;
end
else begin
if (i_InitDo200us) begin
if (s_InitCnt200usCounter == 10000) begin
s_InitCnt200usCounter <= s_InitCnt200usCounter;
i_InitCnt200usDone <= 1;
end
else begin
s_InitCnt200usCounter <= s_InitCnt200usCounter + 1;
i_InitCnt200usDone <= 0;
end
end
else begin
s_InitCnt200usCounter <= 0;
i_InitCnt200usDone <= 0;
end
end // else: !if(reset)
end // always @ (posedge clock0)
always @ (posedge clock0) begin
if (reset) begin
s_InitCnt200Counter <= 0;
i_InitCnt200Done <= 0;
end
else begin
if (i_InitDo200) begin
if (s_InitCnt200Counter == 200) begin
s_InitCnt200Counter <= s_InitCnt200Counter;
i_InitCnt200Done <= 1;
end
else begin
s_InitCnt200Counter <= s_InitCnt200Counter + 1;
i_InitCnt200Done <= 0;
end
end
else begin
s_InitCnt200Counter <= 0;
i_InitCnt200Done <= 0;
end
end // else: !if(reset)
end // always @ (posedge clock0)
always @ (posedge ddr_clock90) begin
s_HalfPage0 <= ddr_dq;
end
always @ (negedge ddr_clock90) begin
s_HalfPage1 <= ddr_dq;
end
`ifdef SIM
always @ * begin
if (inst_en) begin
case (w_InstCode)
`DdrCtl1_NOP: begin
$sformat(d_Input,"EN NOP");
end
`DdrCtl1_LA0: begin
$sformat(d_Input,"EN (LA0 %2X)",w_InstImm);
end
`DdrCtl1_LA1: begin
$sformat(d_Input,"EN (LA1 %2X)",w_InstImm);
end
`DdrCtl1_LA2: begin
$sformat(d_Input,"EN (LA2 %2X)",w_InstImm);
end
`DdrCtl1_LA3: begin
$sformat(d_Input,"EN (LA3 %2X)",w_InstImm);
end
`DdrCtl1_LD0: begin
$sformat(d_Input,"EN (LD0 %2X)",w_InstImm);
end
`DdrCtl1_LD1: begin
$sformat(d_Input,"EN (LD1 %2X)",w_InstImm);
end
`DdrCtl1_LD2: begin
$sformat(d_Input,"EN (LD2 %2X)",w_InstImm);
end
`DdrCtl1_LD3: begin
$sformat(d_Input,"EN (LD3 %2X)",w_InstImm);
end
`DdrCtl1_RDP: begin
$sformat(d_Input,"EN RDP");
end
`DdrCtl1_WRP: begin
$sformat(d_Input,"EN WRP");
end
default: begin
$sformat(d_Input,"EN (? %2X)",w_InstImm);
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
$sformat(d_Input,"NN");
end // else: !if(inst_en)
end // always @ *
always @ * begin
case (s_IntfState)
`DdrCtl1_IntfState_Reset: begin
$sformat(d_IntfState,"X");
end
`DdrCtl1_IntfState_WaitInit: begin
$sformat(d_IntfState,"I %S",
i_InitDone ? "InitDone" : "InitNotDone");
end
`DdrCtl1_IntfState_Ready: begin
$sformat(d_IntfState,"R %4X %4X (%S %S) (%S %S)",
s_IntfAddress,
s_IntfPage,
i_IntfDoRead ? "DoRead" : "NoRead",
i_IntfDoWrite ? "DoWrite" : "NoWrite",
i_CoreReadDone ? "ReadDone" : "ReadNotDone",
i_CoreWriteDone ? "WriteDone" : "WriteNotDone");
end
`DdrCtl1_IntfState_WaitRead: begin
$sformat(d_IntfState,"r %4X %4X (%S %S) (%S %S)",
s_IntfAddress,
s_IntfPage,
i_IntfDoRead ? "DoRead" : "NoRead",
i_IntfDoWrite ? "DoWrite" : "NoWrite",
i_CoreReadDone ? "ReadDone" : "ReadNotDone",
i_CoreWriteDone ? "WriteDone" : "WriteNotDone");
end
`DdrCtl1_IntfState_WaitWrite: begin
$sformat(d_IntfState,"w %4X %4X (%S %S) (%S %S)",
s_IntfAddress,
s_IntfPage,
i_IntfDoRead ? "DoRead" : "NoRead",
i_IntfDoWrite ? "DoWrite" : "NoWrite",
i_CoreReadDone ? "ReadDone" : "ReadNotDone",
i_CoreWriteDone ? "WriteDone" : "WriteNotDone");
end
`DdrCtl1_IntfState_Error: begin
$sformat(d_IntfState,"E");
end
default: begin
$sformat(d_IntfState,"?");
end
endcase // case (s_IntfState)
end // always @ *
always @ * begin
case (s_CoreState)
`DdrCtl1_CoreState_Reset: begin
$sformat(d_CoreState,"X");
end
`DdrCtl1_CoreState_WaitInit: begin
$sformat(d_CoreState,"I %S",
i_InitDone ? "InitDone" : "InitNotDone");
end
`DdrCtl1_CoreState_Ready: begin
$sformat(d_CoreState,"R %5B %2B %4X (%S %S %S) (%S %S %S)",
i_CoreCommand,
i_CoreBank,
i_CoreAddr,
i_CoreRefreshDone ? "RefreshDone" : "RefreshNotDone",
i_CoreReadDone ? "ReadDone" : "ReadNotDone",
i_CoreWriteDone ? "WriteDone" : "WriteNotDone",
i_AutoRefreshDoRefresh ? "DoRefresh" : "NoRefresh",
i_IntfDoRead ? "DoRead" : "NoRead",
i_IntfDoWrite ? "DoWrite" : "NoWrite");
end
`DdrCtl1_CoreState_Refresh_AutoRefresh: begin
$sformat(d_CoreState,"A AutoRefresh %5B %2B %4X (%S %S %S) (%S %S %S)",
i_CoreCommand,
i_CoreBank,
i_CoreAddr,
i_CoreRefreshDone ? "RefreshDone" : "RefreshNotDone",
i_CoreReadDone ? "ReadDone" : "ReadNotDone",
i_CoreWriteDone ? "WriteDone" : "WriteNotDone",
i_AutoRefreshDoRefresh ? "DoRefresh" : "NoRefresh",
i_IntfDoRead ? "DoRead" : "NoRead",
i_IntfDoWrite ? "DoWrite" : "NoWrite");
end
`DdrCtl1_CoreState_Refresh_Wait0: begin
$sformat(d_CoreState,"A Wait0 %5B %2B %4X (%S %S %S) (%S %S %S)",
i_CoreCommand,
i_CoreBank,
i_CoreAddr,
i_CoreRefreshDone ? "RefreshDone" : "RefreshNotDone",
i_CoreReadDone ? "ReadDone" : "ReadNotDone",
i_CoreWriteDone ? "WriteDone" : "WriteNotDone",
i_AutoRefreshDoRefresh ? "DoRefresh" : "NoRefresh",
i_IntfDoRead ? "DoRead" : "NoRead",
i_IntfDoWrite ? "DoWrite" : "NoWrite");
end
`DdrCtl1_CoreState_Refresh_Wait1: begin
$sformat(d_CoreState,"A Wait1 %5B %2B %4X (%S %S %S) (%S %S %S)",
i_CoreCommand,
i_CoreBank,
i_CoreAddr,
i_CoreRefreshDone ? "RefreshDone" : "RefreshNotDone",
i_CoreReadDone ? "ReadDone" : "ReadNotDone",
i_CoreWriteDone ? "WriteDone" : "WriteNotDone",
i_AutoRefreshDoRefresh ? "DoRefresh" : "NoRefresh",
i_IntfDoRead ? "DoRead" : "NoRead",
i_IntfDoWrite ? "DoWrite" : "NoWrite");
end
`DdrCtl1_CoreState_Refresh_Wait2: begin
$sformat(d_CoreState,"A Wait2 %5B %2B %4X (%S %S %S) (%S %S %S)",
i_CoreCommand,
i_CoreBank,
i_CoreAddr,
i_CoreRefreshDone ? "RefreshDone" : "RefreshNotDone",
i_CoreReadDone ? "ReadDone" : "ReadNotDone",
i_CoreWriteDone ? "WriteDone" : "WriteNotDone",
i_AutoRefreshDoRefresh ? "DoRefresh" : "NoRefresh",
i_IntfDoRead ? "DoRead" : "NoRead",
i_IntfDoWrite ? "DoWrite" : "NoWrite");
end // case: `DdrCtl1_CoreState_Refresh_Wait2
`DdrCtl1_CoreState_Read_Activate: begin
$sformat(d_CoreState,"r Activate %5B %2B %4X (%S %S %S) (%S %S %S)",
i_CoreCommand,
i_CoreBank,
i_CoreAddr,
i_CoreRefreshDone ? "RefreshDone" : "RefreshNotDone",
i_CoreReadDone ? "ReadDone" : "ReadNotDone",
i_CoreWriteDone ? "WriteDone" : "WriteNotDone",
i_AutoRefreshDoRefresh ? "DoRefresh" : "NoRefresh",
i_IntfDoRead ? "DoRead" : "NoRead",
i_IntfDoWrite ? "DoWrite" : "NoWrite");
end // case: `DdrCtl1_CoreState_Read_Activate
`DdrCtl1_CoreState_Read_Read: begin
$sformat(d_CoreState,"r Read %5B %2B %4X (%S %S %S) (%S %S %S)",
i_CoreCommand,
i_CoreBank,
i_CoreAddr,
i_CoreRefreshDone ? "RefreshDone" : "RefreshNotDone",
i_CoreReadDone ? "ReadDone" : "ReadNotDone",
i_CoreWriteDone ? "WriteDone" : "WriteNotDone",
i_AutoRefreshDoRefresh ? "DoRefresh" : "NoRefresh",
i_IntfDoRead ? "DoRead" : "NoRead",
i_IntfDoWrite ? "DoWrite" : "NoWrite");
end
`DdrCtl1_CoreState_Read_Wait0: begin
$sformat(d_CoreState,"r Wait0 %5B %2B %4X (%S %S %S) (%S %S %S)",
i_CoreCommand,
i_CoreBank,
i_CoreAddr,
i_CoreRefreshDone ? "RefreshDone" : "RefreshNotDone",
i_CoreReadDone ? "ReadDone" : "ReadNotDone",
i_CoreWriteDone ? "WriteDone" : "WriteNotDone",
i_AutoRefreshDoRefresh ? "DoRefresh" : "NoRefresh",
i_IntfDoRead ? "DoRead" : "NoRead",
i_IntfDoWrite ? "DoWrite" : "NoWrite");
end // case: `DdrCtl1_CoreState_Read_Wait0
`DdrCtl1_CoreState_Read_Wait1: begin
$sformat(d_CoreState,"r Wait1 %5B %2B %4X (%S %S %S) (%S %S %S)",
i_CoreCommand,
i_CoreBank,
i_CoreAddr,
i_CoreRefreshDone ? "RefreshDone" : "RefreshNotDone",
i_CoreReadDone ? "ReadDone" : "ReadNotDone",
i_CoreWriteDone ? "WriteDone" : "WriteNotDone",
i_AutoRefreshDoRefresh ? "DoRefresh" : "NoRefresh",
i_IntfDoRead ? "DoRead" : "NoRead",
i_IntfDoWrite ? "DoWrite" : "NoWrite");
end
`DdrCtl1_CoreState_Write_Activate: begin
$sformat(d_CoreState,"w Activate %5B %2B %4X (%S %S %S) (%S %S %S)",
i_CoreCommand,
i_CoreBank,
i_CoreAddr,
i_CoreRefreshDone ? "RefreshDone" : "RefreshNotDone",
i_CoreReadDone ? "ReadDone" : "ReadNotDone",
i_CoreWriteDone ? "WriteDone" : "WriteNotDone",
i_AutoRefreshDoRefresh ? "DoRefresh" : "NoRefresh",
i_IntfDoRead ? "DoRead" : "NoRead",
i_IntfDoWrite ? "DoWrite" : "NoWrite");
end
`DdrCtl1_CoreState_Write_Write: begin
$sformat(d_CoreState,"w Write %5B %2B %4X (%S %S %S) (%S %S %S)",
i_CoreCommand,
i_CoreBank,
i_CoreAddr,
i_CoreRefreshDone ? "RefreshDone" : "RefreshNotDone",
i_CoreReadDone ? "ReadDone" : "ReadNotDone",
i_CoreWriteDone ? "WriteDone" : "WriteNotDone",
i_AutoRefreshDoRefresh ? "DoRefresh" : "NoRefresh",
i_IntfDoRead ? "DoRead" : "NoRead",
i_IntfDoWrite ? "DoWrite" : "NoWrite");
end
`DdrCtl1_CoreState_Write_Wait0: begin
$sformat(d_CoreState,"w Wait0 %5B %2B %4X (%S %S %S) (%S %S %S)",
i_CoreCommand,
i_CoreBank,
i_CoreAddr,
i_CoreRefreshDone ? "RefreshDone" : "RefreshNotDone",
i_CoreReadDone ? "ReadDone" : "ReadNotDone",
i_CoreWriteDone ? "WriteDone" : "WriteNotDone",
i_AutoRefreshDoRefresh ? "DoRefresh" : "NoRefresh",
i_IntfDoRead ? "DoRead" : "NoRead",
i_IntfDoWrite ? "DoWrite" : "NoWrite");
end
`DdrCtl1_CoreState_Write_Wait1: begin
$sformat(d_CoreState,"w Wait1 %5B %2B %4X (%S %S %S) (%S %S %S)",
i_CoreCommand,
i_CoreBank,
i_CoreAddr,
i_CoreRefreshDone ? "RefreshDone" : "RefreshNotDone",
i_CoreReadDone ? "ReadDone" : "ReadNotDone",
i_CoreWriteDone ? "WriteDone" : "WriteNotDone",
i_AutoRefreshDoRefresh ? "DoRefresh" : "NoRefresh",
i_IntfDoRead ? "DoRead" : "NoRead",
i_IntfDoWrite ? "DoWrite" : "NoWrite");
end
default: begin
$sformat(d_CoreState,"?");
end
endcase // case (s_CoreState)
end // always @ *
always @ * begin
case (s_InitState)
`DdrCtl1_InitState_Reset: begin
$sformat(d_InitState,"R");
end
`DdrCtl1_InitState_PowerUp: begin
$sformat(d_InitState,"I PowerUp %5B %2B %4X",
i_InitCommand,
i_InitBank,
i_InitAddr);
end
`DdrCtl1_InitState_Wait200us: begin
$sformat(d_InitState,"I Wait200us %5B %2B %4X %S %S",
i_InitCommand,
i_InitBank,
i_InitAddr,
i_InitDo200us ? "Do200us" : "No200us",
i_InitCnt200usDone ? "200usDone" : "200usNotDone");
end
`DdrCtl1_InitState_BringCKEHigh: begin
$sformat(d_InitState,"I BringCKEHigh %5B %2B %4X",
i_InitCommand,
i_InitBank,
i_InitAddr);
end
`DdrCtl1_InitState_PreChargeAll0: begin
$sformat(d_InitState,"I PreChargeAll0 %5B %2B %4X",
i_InitCommand,
i_InitBank,
i_InitAddr);
end
`DdrCtl1_InitState_EnableDLL: begin
$sformat(d_InitState,"I EnableDLL %5B %2B %4X",
i_InitCommand,
i_InitBank,
i_InitAddr);
end
`DdrCtl1_InitState_ProgramMRResetDLL: begin
$sformat(d_InitState,"I ProgramMRResetDLL %5B %2B %4X",
i_InitCommand,
i_InitBank,
i_InitAddr);
end
`DdrCtl1_InitState_WaitMRD200: begin
$sformat(d_InitState,"I Wait200 %5B %2B %4X %S %S",
i_InitCommand,
i_InitBank,
i_InitAddr,
i_InitDo200 ? "Do200" : "No200",
i_InitCnt200Done ? "200Done" : "200NotDone");
end
`DdrCtl1_InitState_PreChargeAll1: begin
$sformat(d_InitState,"I PreChargeAll1 %5B %2B %4X",
i_InitCommand,
i_InitBank,
i_InitAddr);
end
`DdrCtl1_InitState_Refresh0_AutoRefresh: begin
$sformat(d_InitState,"I Refresh0 AutoRefresh %5B %2B %4X",
i_InitCommand,
i_InitBank,
i_InitAddr);
end
`DdrCtl1_InitState_Refresh0_Wait0: begin
$sformat(d_InitState,"I Refresh0 Wait0 %5B %2B %4X",
i_InitCommand,
i_InitBank,
i_InitAddr);
end
`DdrCtl1_InitState_Refresh0_Wait1: begin
$sformat(d_InitState,"I Refresh0 Wait1 %5B %2B %4X",
i_InitCommand,
i_InitBank,
i_InitAddr);
end
`DdrCtl1_InitState_Refresh0_Wait2: begin
$sformat(d_InitState,"I Refresh0 Wait2 %5B %2B %4X",
i_InitCommand,
i_InitBank,
i_InitAddr);
end
`DdrCtl1_InitState_Refresh1_AutoRefresh: begin
$sformat(d_InitState,"I Refresh1 AutoRefresh %5B %2B %4X",
i_InitCommand,
i_InitBank,
i_InitAddr);
end
`DdrCtl1_InitState_Refresh1_Wait0: begin
$sformat(d_InitState,"I Refresh1 Wait0 %5B %2B %4X",
i_InitCommand,
i_InitBank,
i_InitAddr);
end
`DdrCtl1_InitState_Refresh1_Wait1: begin
$sformat(d_InitState,"I Refresh1 Wait1 %5B %2B %4X",
i_InitCommand,
i_InitBank,
i_InitAddr);
end
`DdrCtl1_InitState_Refresh1_Wait2: begin
$sformat(d_InitState,"I Refresh1 Wait2 %5B %2B %4X",
i_InitCommand,
i_InitBank,
i_InitAddr);
end
`DdrCtl1_InitState_ClearDLL: begin
$sformat(d_InitState,"I ClearDLL %5B %2B %4X",
i_InitCommand,
i_InitBank,
i_InitAddr);
end
`DdrCtl1_InitState_Initialized: begin
$sformat(d_InitState,"I Initialized %5B %2B %4X",
i_InitCommand,
i_InitBank,
i_InitAddr);
end
default: begin
$sformat(d_InitState,"?");
end
endcase // case (s_InitState)
end // always @ *
always @ * begin
$sformat(d_AutoRefreshCounter,"%3D %S %S",
s_AutoRefreshCounter,
i_AutoRefreshDoRefresh ? "DoRefresh" : "NoRefresh",
i_CoreRefreshDone ? "RefreshDone" : "RefreshNotDone");
end
always @ * begin
$sformat(d_InitCnt200usCounter,"%5D %S %S",
s_InitCnt200usCounter,
i_InitCnt200usDone ? "200usDone" : "200usNotDone",
i_InitDo200us ? "Do200us" : "No200us");
end
always @ * begin
$sformat(d_InitCnt200Counter,"%3D %S %S",
s_InitCnt200Counter,
i_InitCnt200Done ? "200Done" : "200NotDone",
i_InitDo200 ? "Do200" : "No200");
end
`endif // `ifdef SIM
endmodule // DdrCtl1
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module tdc_s3 #(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter CLKDV = 4,
parameter DATA_IDENTIFIER = 4'b0100,
parameter ABUSWIDTH = 16,
parameter FAST_TDC = 1,
parameter FAST_TRIGGER = 1
)(
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
input wire CLK320,
input wire CLK160,
input wire DV_CLK, // clock synchronous to CLK160 division factor can be set by CLKDV parameter
input wire TDC_IN,
output wire TDC_OUT,
input wire TRIG_IN,
output wire TRIG_OUT,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
input wire ARM_TDC,
input wire EXT_EN,
input wire [15:0] TIMESTAMP
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
tdc_s3_core #(
.DATA_IDENTIFIER(DATA_IDENTIFIER),
.CLKDV(CLKDV),
.ABUSWIDTH(ABUSWIDTH),
.FAST_TDC(FAST_TDC),
.FAST_TRIGGER(FAST_TRIGGER)
) i_tdc_s3_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.CLK320(CLK320),
.CLK160(CLK160),
.DV_CLK(DV_CLK),
.TDC_IN(TDC_IN),
.TDC_OUT(TDC_OUT),
.TRIG_IN(TRIG_IN),
.TRIG_OUT(TRIG_OUT),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.ARM_TDC(ARM_TDC),
.EXT_EN(EXT_EN),
.TIMESTAMP(TIMESTAMP)
);
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 15:23:02 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Clock8346/Clock8346_stub.v
// Design : Clock8346
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module Clock8346(clk_in1, clk_out1, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,locked" */;
input clk_in1;
output clk_out1;
output locked;
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Spartan-6 Integrated Block for PCI Express
// File : axi_basic_rx.v
//----------------------------------------------------------------------------//
// File: axi_basic_rx.v //
// //
// Description: //
// TRN to AXI RX module. Instantiates pipeline and null generator RX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_rx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter STRB_WIDTH = C_DATA_WIDTH / 8 // tkeep width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [STRB_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires
wire null_rx_tvalid;
wire null_rx_tlast;
wire [STRB_WIDTH-1:0] null_rx_tkeep;
wire null_rdst_rdy;
wire [4:0] null_is_eof;
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
axi_basic_rx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) rx_pipeline_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// Null Inputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// RX Null Packet Generator //
//---------------------------------------------//
axi_basic_rx_null_gen #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.TCQ( TCQ ),
.STRB_WIDTH( STRB_WIDTH )
) rx_null_gen_inst (
// Inputs
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Null Outputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:16:32 11/23/2014
// Design Name: hex_to_sseg
// Module Name: /home/aneez/workspace/vSevenSegmentDisplay/hexToSSEG_tb.v
// Project Name: vSevenSegmentDisplay
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: hex_to_sseg
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module hexToSSEG_tb;
// Inputs
reg [3:0] hex;
reg dp;
// Outputs
wire [7:0] sseg;
// Instantiate the Unit Under Test (UUT)
hex_to_sseg uut (
.hex(hex),
.sseg(sseg),
.dp(dp)
);
initial begin
// Initialize Inputs
hex = 0;
dp = 0;
// Wait 100 ns for global reset to finish
#100 hex = 1;
#200 hex = 3;
// Add stimulus here
#400 $finish;
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// mrram_swt.v: Multiread-RAM based on bank replication & generic dual-ported RAM //
// * switched read ports support //
// * optional single-stage or 2-stage bypass //
// //
// Author: Ameer M.S. Abdelhadi ([email protected], [email protected]) //
// Switched SRAM-based Multi-ported RAM; University of British Columbia, 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module mrram_swt
#( parameter MEMD = 16, // memory depth
parameter DATW = 32, // data width
parameter nRPF = 2 , // number of fixed read ports
parameter nRPS = 2 , // number of switched read ports
parameter BYPS = 1 , // bypass? 0:none; 1: single-stage; 2:two-stages
parameter ZERO = 0 , // binary / Initial RAM with zeros (has priority over FILE)
parameter FILE = "" // initialization mif file (don't pass extension), optional
)( input clk , // clock
input rdWr , // switch read/write (write is active low)
input WEnb , // write enable (1 port)
input [`log2(MEMD) -1:0] WAddr, // write address (1 port)
input [DATW -1:0] WData, // write data (1 port)
input [`log2(MEMD)*(nRPS+nRPF)-1:0] RAddr, // read addresses - packed from nRPF fixed & nRPS switched read ports
output reg [DATW *(nRPS+nRPF)-1:0] RData); // read data - packed from nRPF fixed & nRPS switched read ports
localparam nRPT = nRPS+nRPF ; // total number of read ports
localparam ADRW = `log2(MEMD); // address width
// unpacked read addresses/data
reg [ADRW-1:0] RAddr_upk [nRPT-1:0]; // read addresses - unpacked 2D array
wire [DATW-1:0] RData_upk [nRPT-1:0]; // read data - unpacked 2D array
// unpack read addresses; pack read data
`ARRINIT;
always @* begin
// packing/unpacking arrays into 1D/2D/3D structures; see utils.vh for definitions
`ARR1D2D(nRPT,ADRW,RAddr,RAddr_upk);
`ARR2D1D(nRPT,DATW,RData_upk,RData);
end
// generate and instantiate generic RAM blocks
genvar rpi;
generate
for (rpi=0 ; rpi<nRPF ; rpi=rpi+1) begin: RPORTrpi
// generic dual-ported ram instantiation
if (rpi<(nRPF-nRPS)) begin
dpram_bbs #( .MEMD (MEMD ), // memory depth
.DATW (DATW ), // data width
.BYPS (BYPS ), // bypass? 0: none; 1: single-stage; 2:two-stages
.ZERO (ZERO ), // binary / Initial RAM with zeros (has priority over INITFILE)
.FILE (FILE )) // initialization file, optional
dpram_bbsi ( .clk (clk ), // clock - in
.WEnb_A (1'b0 ), // write enable - in
.WEnb_B (WEnb && (!rdWr)), // write enable - in
.Addr_A (RAddr_upk[rpi] ), // write address - in : [`log2(MEMD)-1:0]
.Addr_B (WAddr ), // write address - in : [`log2(MEMD)-1:0]
.WData_A ({DATW{1'b1}} ), // change to 1'b0
.WData_B (WData ), // write data - in : [DATW -1:0]
.RData_A (RData_upk[rpi] ), // read data - out: [DATW -1:0]
.RData_B ( )); // read data - out: [DATW -1:0]
end
else begin
dpram_bbs #( .MEMD (MEMD ), // memory depth
.DATW (DATW ), // data width
.BYPS (BYPS ), // bypass? 0: none; 1: single-stage; 2:two-stages
.ZERO (ZERO ), // binary / Initial RAM with zeros (has priority over INITFILE)
.FILE (FILE )) // initialization file, optional
dpram_bbsi ( .clk (clk ), // clock - in
.WEnb_A (1'b0 ), // write enable - in
.WEnb_B (WEnb && (!rdWr) ), // write enable - in
.Addr_A ( RAddr_upk[rpi] ), // write address - in : [`log2(MEMD)-1:0]
.Addr_B (rdWr?RAddr_upk[rpi+nRPS]:WAddr), // write address - in : [`log2(MEMD)-1:0]
.WData_A ({DATW{1'b1}} ), // change to 1'b0
.WData_B (WData ), // write data - in : [DATW -1:0]
.RData_A (RData_upk[rpi] ), // read data - out: [DATW -1:0]
.RData_B (RData_upk[rpi+nRPS] )); // read data - out: [DATW -1:0]
end
end
endgenerate
endmodule
|
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs.
As of Coq 8.4 [admit] is in the standard library, but we include
it here for backwards compatibility.
*)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
mathematics: If a procedure or method has no side effects, then
pretty much all you need to understand about it is how it maps
inputs to outputs -- that is, you can think of its behavior as
just computing a mathematical function. This is one reason for
the word "functional" in "functional programming." This direct
connection between programs and simple mathematical objects
supports both sound informal reasoning and formal proofs of
correctness.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful idioms, as we will see.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code.
To see how this works, let's start with a very simple example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second through eighth lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often work out these types even if
they are not given explicitly -- i.e., it performs some _type
inference_ -- but we'll always include them to make reading
easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq. First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, now would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to "extract," from a [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters.
More information can also be found in the Coq'Art book by Bertot
and Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the type [bool] of booleans,
with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] will automatically perform
simplification.) *)
(** _A note on notation_: We use square brackets to delimit
fragments of Coq code in comments in .v files; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => negb b2
| false => true
end.
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
Proof. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
Proof. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
match andb b1 b2 with
| true => b3
| false => false
end.
Example test_andb31: (andb3 true true true) = true.
Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval compute in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => S O
| S n' => mult n (factorial n')
end.
Example test_factorial1: (factorial 3) = 6.
Proof. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
(************************************************************)
(* Notation "x + y" := (plus x y) *)
(* (at level 50, left associativity) *)
(* : nat_scope. *)
(* Notation "x - y" := (minus x y) *)
(* (at level 50, left associativity) *)
(* : nat_scope. *)
(* Notation "x * y" := (mult x y) *)
(* (at level 40, left associativity) *)
(* : nat_scope. *)
(* Above already there, but the definitions are nice *)
(************************************************************)
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Optional Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function.
Note: If you have trouble with the [simpl] tactic, try using
[compute], which is like [simpl] on steroids. However, there is a
simple, elegant solution for which [simpl] suffices. *)
Definition blt_nat (n m : nat) : bool :=
andb (ble_nat n m) (negb (beq_nat n m)).
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than [simpl]
does -- for example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** Step through these proofs in Coq and notice how the goal and
context change. *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof. intro n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof. intro n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros n m o.
intros p1 p2.
rewrite -> p1.
rewrite -> p2.
reflexivity. Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros n m.
intro p.
rewrite -> plus_1_l.
rewrite -> p.
reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
destruct n; reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros.
rewrite -> H.
rewrite -> H.
reflexivity.
Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
(* FILL IN HERE *)
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Lemma andb_true :
forall (b c : bool),
(andb b c = true) -> b = true /\ c = true.
Proof.
intros.
destruct b, c; auto.
Qed.
Lemma orb_false :
forall (b c : bool),
(orb b c = false) -> b = false /\ c = false.
Proof.
intros.
destruct b, c; auto.
Qed.
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros.
destruct b, c; auto.
Qed.
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function for binary numbers, and a
function to convert binary numbers to unary numbers.
(c) Write some unit tests for your increment and binary-to-unary
functions. Notice that incrementing a binary number and
then converting it to unary should yield the same result as first
converting it to unary and then incrementing.
*)
(* Inductive bin : Type := *)
(* | BO : bin *)
(* | TwoB : bin -> bin *)
(* | SucB : bin -> bin. *)
(* Fixpoint bintonat (b : bin) : nat := *)
(* match b with *)
(* | BO => O *)
(* | TwoB nb => 2 * (bintonat nb) *)
(* | SucB nb => S (2 * bintonat nb) *)
(* end. *)
(* (** [] *) *)
(* Fixpoint incb (b : bin) : bin := *)
(* match b with *)
(* | BO => SucB BO *)
(* | TwoB nb => SucB nb *)
(* | SucB nb => TwoB (incb nb) *)
(* end. *)
(* Fixpoint nattobin (n : nat) : bin := *)
(* match n with *)
(* | 0 => BO *)
(* | S n' => incb (nattobin n') *)
(* end. *)
(* ###################################################################### *)
(** * Optional Material *)
(** ** More on Notation *)
(*************************************************************)
(* Notation "x + y" := (plus x y) *)
(* (at level 50, left associativity) *)
(* : nat_scope. *)
(* Notation "x * y" := (mult x y) *)
(* (at level 40, left associativity) *)
(* : nat_scope. *)
(*************************************************************)
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** ** [Fixpoint]s and Structural Recursion *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| 0 => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will _not_ accept
because of this restriction. *)
Fixpoint eq (n : nat) (m : nat) : bool :=
match n, m with
| 0 , 0 => true
| S n' , S m' => eq n' m'
| _ , _ => false
end.
(* Fixpoint fix (iters : nat) (n : nat) (f : nat -> nat) : nat := *)
(* match ble_nat iters 1000 , eq (f n) n with *)
(* | false, _ => n *)
(* | _ , false => fix (iters + 1) (f n) f *)
(* | _ , _ => n *)
(* end. *)
(** [] *)
(* $Date: 2013-12-03 07:45:41 -0500 (Tue, 03 Dec 2013) $ *)
|
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// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 3
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2015.4.2" *)
(* CHECK_LICENSE_TYPE = "design_TEST_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "design_TEST_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=32,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_HP0=1,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=true,C_FCLK_CLK1_BUF=false,C_FCLK_CLK2_BUF=false,C_FCLK_CLK3_BUF=false,C_PACKAGE_NAME=clg400}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_TEST_processing_system7_0_0 (
SDIO0_WP,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 WP" *)
input wire SDIO0_WP;
output wire TTC0_WAVE0_OUT;
output wire TTC0_WAVE1_OUT;
output wire TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *)
output wire [1 : 0] USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *)
output wire USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *)
input wire USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
output wire M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
output wire M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
output wire M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
output wire M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
output wire M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
output wire M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
output wire [11 : 0] M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
output wire [11 : 0] M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
output wire [11 : 0] M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
output wire [1 : 0] M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
output wire [1 : 0] M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
output wire [2 : 0] M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
output wire [1 : 0] M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
output wire [1 : 0] M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
output wire [2 : 0] M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
output wire [2 : 0] M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
output wire [2 : 0] M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
output wire [31 : 0] M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
output wire [31 : 0] M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
output wire [31 : 0] M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
output wire [3 : 0] M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
output wire [3 : 0] M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
output wire [3 : 0] M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
output wire [3 : 0] M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
output wire [3 : 0] M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
output wire [3 : 0] M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
output wire [3 : 0] M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
input wire M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
input wire M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
input wire M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
input wire M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
input wire M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
input wire M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
input wire M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
input wire [11 : 0] M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
input wire [11 : 0] M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
input wire [1 : 0] M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
input wire [1 : 0] M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
input wire [31 : 0] M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARREADY" *)
output wire S_AXI_HP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWREADY" *)
output wire S_AXI_HP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BVALID" *)
output wire S_AXI_HP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RLAST" *)
output wire S_AXI_HP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RVALID" *)
output wire S_AXI_HP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WREADY" *)
output wire S_AXI_HP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BRESP" *)
output wire [1 : 0] S_AXI_HP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RRESP" *)
output wire [1 : 0] S_AXI_HP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BID" *)
output wire [5 : 0] S_AXI_HP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RID" *)
output wire [5 : 0] S_AXI_HP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RDATA" *)
output wire [31 : 0] S_AXI_HP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RCOUNT" *)
output wire [7 : 0] S_AXI_HP0_RCOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WCOUNT" *)
output wire [7 : 0] S_AXI_HP0_WCOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RACOUNT" *)
output wire [2 : 0] S_AXI_HP0_RACOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WACOUNT" *)
output wire [5 : 0] S_AXI_HP0_WACOUNT;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXI_HP0_ACLK CLK" *)
input wire S_AXI_HP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARVALID" *)
input wire S_AXI_HP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWVALID" *)
input wire S_AXI_HP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BREADY" *)
input wire S_AXI_HP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RDISSUECAPEN" *)
input wire S_AXI_HP0_RDISSUECAP1_EN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RREADY" *)
input wire S_AXI_HP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WLAST" *)
input wire S_AXI_HP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WRISSUECAPEN" *)
input wire S_AXI_HP0_WRISSUECAP1_EN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WVALID" *)
input wire S_AXI_HP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARBURST" *)
input wire [1 : 0] S_AXI_HP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLOCK" *)
input wire [1 : 0] S_AXI_HP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARSIZE" *)
input wire [2 : 0] S_AXI_HP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWBURST" *)
input wire [1 : 0] S_AXI_HP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLOCK" *)
input wire [1 : 0] S_AXI_HP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWSIZE" *)
input wire [2 : 0] S_AXI_HP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARPROT" *)
input wire [2 : 0] S_AXI_HP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWPROT" *)
input wire [2 : 0] S_AXI_HP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARADDR" *)
input wire [31 : 0] S_AXI_HP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWADDR" *)
input wire [31 : 0] S_AXI_HP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARCACHE" *)
input wire [3 : 0] S_AXI_HP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLEN" *)
input wire [3 : 0] S_AXI_HP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARQOS" *)
input wire [3 : 0] S_AXI_HP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWCACHE" *)
input wire [3 : 0] S_AXI_HP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLEN" *)
input wire [3 : 0] S_AXI_HP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWQOS" *)
input wire [3 : 0] S_AXI_HP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARID" *)
input wire [5 : 0] S_AXI_HP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWID" *)
input wire [5 : 0] S_AXI_HP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WID" *)
input wire [5 : 0] S_AXI_HP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WDATA" *)
input wire [31 : 0] S_AXI_HP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WSTRB" *)
input wire [3 : 0] S_AXI_HP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *)
input wire [0 : 0] IRQ_F2P;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(32),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(1),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_USE_AXI_NONSECURE(0),
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_HP0(1),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_USE_S_AXI_ACP(0),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("true"),
.C_FCLK_CLK1_BUF("false"),
.C_FCLK_CLK2_BUF("false"),
.C_FCLK_CLK3_BUF("false"),
.C_PACKAGE_NAME("clg400")
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(),
.ENET0_PTP_DELAY_REQ_TX(),
.ENET0_PTP_PDELAY_REQ_RX(),
.ENET0_PTP_PDELAY_REQ_TX(),
.ENET0_PTP_PDELAY_RESP_RX(),
.ENET0_PTP_PDELAY_RESP_TX(),
.ENET0_PTP_SYNC_FRAME_RX(),
.ENET0_PTP_SYNC_FRAME_TX(),
.ENET0_SOF_RX(),
.ENET0_SOF_TX(),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(1'B0),
.I2C0_SDA_O(),
.I2C0_SDA_T(),
.I2C0_SCL_I(1'B0),
.I2C0_SCL_O(),
.I2C0_SCL_T(),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(SDIO0_WP),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY),
.S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY),
.S_AXI_HP0_BVALID(S_AXI_HP0_BVALID),
.S_AXI_HP0_RLAST(S_AXI_HP0_RLAST),
.S_AXI_HP0_RVALID(S_AXI_HP0_RVALID),
.S_AXI_HP0_WREADY(S_AXI_HP0_WREADY),
.S_AXI_HP0_BRESP(S_AXI_HP0_BRESP),
.S_AXI_HP0_RRESP(S_AXI_HP0_RRESP),
.S_AXI_HP0_BID(S_AXI_HP0_BID),
.S_AXI_HP0_RID(S_AXI_HP0_RID),
.S_AXI_HP0_RDATA(S_AXI_HP0_RDATA),
.S_AXI_HP0_RCOUNT(S_AXI_HP0_RCOUNT),
.S_AXI_HP0_WCOUNT(S_AXI_HP0_WCOUNT),
.S_AXI_HP0_RACOUNT(S_AXI_HP0_RACOUNT),
.S_AXI_HP0_WACOUNT(S_AXI_HP0_WACOUNT),
.S_AXI_HP0_ACLK(S_AXI_HP0_ACLK),
.S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID),
.S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID),
.S_AXI_HP0_BREADY(S_AXI_HP0_BREADY),
.S_AXI_HP0_RDISSUECAP1_EN(S_AXI_HP0_RDISSUECAP1_EN),
.S_AXI_HP0_RREADY(S_AXI_HP0_RREADY),
.S_AXI_HP0_WLAST(S_AXI_HP0_WLAST),
.S_AXI_HP0_WRISSUECAP1_EN(S_AXI_HP0_WRISSUECAP1_EN),
.S_AXI_HP0_WVALID(S_AXI_HP0_WVALID),
.S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST),
.S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK),
.S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE),
.S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST),
.S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK),
.S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE),
.S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT),
.S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT),
.S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR),
.S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR),
.S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE),
.S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN),
.S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS),
.S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE),
.S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN),
.S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS),
.S_AXI_HP0_ARID(S_AXI_HP0_ARID),
.S_AXI_HP0_AWID(S_AXI_HP0_AWID),
.S_AXI_HP0_WID(S_AXI_HP0_WID),
.S_AXI_HP0_WDATA(S_AXI_HP0_WDATA),
.S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(IRQ_F2P),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
module visualizacion (
input clk,
input ECHO,
input orden,
output trigg,
output [3:0] anodo,
output [6:0] seg
);
wire [7:0] d;
wire [7:0] distancia;
wire [1:0] mostrar;
wire [3:0] digito;
wire [3:0] anodo;
wire [6:0] seg;
wire [3:0] centenas;
wire [3:0] decenas;
wire [3:0] unidades;
divisorfrecdisp divisorfrecdisp0 (
.clk ( clk ),
.CLKOUTseg ( CLKOUTseg )
);
/////////////////////////////////////////////
anteconmutador anteconmutador0 (
.clk ( clk ),
.d ( d ),
.DONE ( DONE ),
.centenas ( centenas ),
.decenas ( decenas ),
.unidades ( unidades ),
.C ( C ),
.D ( D ),
.U ( U )
);
/////////////////////////////////////////////
conmutacion conmutacion0 (
.centenas ( centenas ),
.decenas ( decenas ),
.unidades ( unidades ),
.C ( C ),
.D ( D ),
.U ( U ),
.CLKOUTseg ( CLKOUTseg ),
.mostrar ( mostrar ),
.digito ( digito )
);
/////////////////////////////////////////////
display display (
.mostrar ( mostrar ),
.digito ( digito ),
.anodo ( anodo ),
.seg ( seg )
);/*
/////////////////////////////////////////////
pulsodisplay pulsodisplay (
.DONE ( DONE ),
.d ( d ),
.CLKOUTseg ( CLKOUTseg ), // Esto Toca Cambiarlo
.pulse ( pulse ),
.distancia ( distancia )
);*/
/////////////////////////////////////////////
bloqueultrasonido bloqueultrasonido (
.d ( d ),
.trigg ( trigg ),
.DONE ( DONE ),
.clk ( clk ),
.orden ( orden ),
.ECHO ( ECHO )
);
endmodule
|
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