text
stringlengths 938
1.05M
|
|---|
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-26 23:25:59
// Last Modified : 2016-10-27 19:57:00
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
//=========================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-26 23:25:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`define STOP_SW1 3
`define STOP_SW2 4
module Simple_KOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output reg [2*SW-1:0] sgf_result_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
localparam half = SW/2;
generate
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
reg [SW-1:0] Q_left;
reg [SW-1:0] Q_right;
reg [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
mult #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
mult #(.SW(SW/2)) right(
// .clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
mult #(.SW((SW/2)+1)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : EVEN
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2):0] <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
reg [2*(SW/2)-1:0] Q_left;
reg [2*(SW/2+1)-1:0] Q_right;
reg [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
mult #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
mult #(.SW(SW/2)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
mult #(.SW(SW/2+2)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : ODD
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2)+2:0]<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
endgenerate
endmodule
|
`timescale 1ns / 1ps
/*
Group Members: Kevin Ingram and Warren Seto
Lab Name: Traffic Light Controller (Lab 3)
Project Name: eng312_proj3
Design Name: Traffic_Test_C_eng312_proj3.v
Design Description: Verilog Test Bench to Implement Test C (9 AM)
*/
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire[4:0] count1;
wire[3:0] count2;
wire[1:0] count3;
// Counter Modules
nsCounter clock1(clk, count1); // Count a total of 32 seconds
ewCounter clock2(clk, count2); // Counts a total of 16 seconds
yellowCounter clock3(clk, count3); // Counts a total of 4 seconds
// Main Traffic Module
Traffic CORE (count1, count2, count3, NS_VEHICLE_DETECT, EW_VEHICLE_DETECT, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
initial begin
clk = 0;
NS_VEHICLE_DETECT = 0;
EW_VEHICLE_DETECT = 1;
$display(" NS | EW ");
$display(" (Time) | R Y G R Y G ");
$monitor("%d | %h %h %h %h %h %h", $time, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
#1000 $finish;
end
always begin
#1 clk = ~clk;
end
always @ (clk) begin
if ($time % 15 == 0) begin
NS_VEHICLE_DETECT = ~NS_VEHICLE_DETECT;
end
if ($time % 6 == 0) begin
EW_VEHICLE_DETECT = ~EW_VEHICLE_DETECT;
end
end
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module pulse_gen_core #(
parameter ABUSWIDTH = 16
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
input wire BUS_RD,
input wire BUS_WR,
output reg [7:0] BUS_DATA_OUT,
input wire PULSE_CLK,
input wire EXT_START,
output reg PULSE
);
localparam VERSION = 3;
wire SOFT_RST;
wire START;
reg CONF_EN;
reg [31:0] CONF_DELAY;
reg [31:0] CONF_WIDTH;
reg [31:0] CONF_REPEAT;
reg CONF_DONE;
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT <= {7'b0, CONF_DONE};
else if(BUS_ADD == 2)
BUS_DATA_OUT <= {7'b0, CONF_EN};
else if(BUS_ADD == 3)
BUS_DATA_OUT <= CONF_DELAY[7:0];
else if(BUS_ADD == 4)
BUS_DATA_OUT <= CONF_DELAY[15:8];
else if(BUS_ADD == 5)
BUS_DATA_OUT <= CONF_DELAY[23:16];
else if(BUS_ADD == 6)
BUS_DATA_OUT <= CONF_DELAY[31:24];
else if(BUS_ADD == 7)
BUS_DATA_OUT <= CONF_WIDTH[7:0];
else if(BUS_ADD == 8)
BUS_DATA_OUT <= CONF_WIDTH[15:8];
else if(BUS_ADD == 9)
BUS_DATA_OUT <= CONF_WIDTH[23:16];
else if(BUS_ADD == 10)
BUS_DATA_OUT <= CONF_WIDTH[31:24];
else if(BUS_ADD == 11)
BUS_DATA_OUT <= CONF_REPEAT[7:0];
else if(BUS_ADD == 12)
BUS_DATA_OUT <= CONF_REPEAT[15:8];
else if(BUS_ADD == 13)
BUS_DATA_OUT <= CONF_REPEAT[23:16];
else if(BUS_ADD == 14)
BUS_DATA_OUT <= CONF_REPEAT[31:24];
else
BUS_DATA_OUT <= 8'b0;
end
end
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
assign START = (BUS_ADD==1 && BUS_WR);
wire RST;
assign RST = BUS_RST | SOFT_RST;
always @(posedge BUS_CLK) begin
if(RST) begin
CONF_EN <= 0;
CONF_DELAY <= 0;
CONF_WIDTH <= 0;
CONF_REPEAT <= 1;
end
else if(BUS_WR) begin
if(BUS_ADD == 2)
CONF_EN <= BUS_DATA_IN[0];
else if(BUS_ADD == 3)
CONF_DELAY[7:0] <= BUS_DATA_IN;
else if(BUS_ADD == 4)
CONF_DELAY[15:8] <= BUS_DATA_IN;
else if(BUS_ADD == 5)
CONF_DELAY[23:16] <= BUS_DATA_IN;
else if(BUS_ADD == 6)
CONF_DELAY[31:24] <= BUS_DATA_IN;
else if(BUS_ADD == 7)
CONF_WIDTH[7:0] <= BUS_DATA_IN;
else if(BUS_ADD == 8)
CONF_WIDTH[15:8] <= BUS_DATA_IN;
else if(BUS_ADD == 9)
CONF_WIDTH[23:16] <= BUS_DATA_IN;
else if(BUS_ADD == 10)
CONF_WIDTH[31:24] <= BUS_DATA_IN;
else if(BUS_ADD == 11)
CONF_REPEAT[7:0] <= BUS_DATA_IN;
else if(BUS_ADD == 12)
CONF_REPEAT[15:8] <= BUS_DATA_IN;
else if(BUS_ADD == 13)
CONF_REPEAT[23:16] <= BUS_DATA_IN;
else if(BUS_ADD == 14)
CONF_REPEAT[31:24] <= BUS_DATA_IN;
end
end
wire CONF_EN_SYNC;
three_stage_synchronizer conf_en_sync (
.CLK(PULSE_CLK),
.IN(CONF_EN),
.OUT(CONF_EN_SYNC)
);
wire [31:0] CONF_DELAY_SYNC;
three_stage_synchronizer #(
.WIDTH(32)
) conf_dely_sync (
.CLK(PULSE_CLK),
.IN(CONF_DELAY),
.OUT(CONF_DELAY_SYNC)
);
wire [31:0] CONF_WIDTH_SYNC;
three_stage_synchronizer #(
.WIDTH(32)
) conf_width_sync (
.CLK(PULSE_CLK),
.IN(CONF_WIDTH),
.OUT(CONF_WIDTH_SYNC)
);
wire [31:0] CONF_REPEAT_SYNC;
three_stage_synchronizer #(
.WIDTH(32)
) conf_repeat_sync (
.CLK(PULSE_CLK),
.IN(CONF_REPEAT),
.OUT(CONF_REPEAT_SYNC)
);
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(PULSE_CLK), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC || BUS_RST;
wire START_SYNC;
cdc_pulse_sync start_pulse_sync (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(PULSE_CLK), .pulse_out(START_SYNC));
wire EXT_START_SYNC;
reg [2:0] EXT_START_FF;
always @(posedge PULSE_CLK) // first stage
begin
EXT_START_FF[0] <= EXT_START;
EXT_START_FF[1] <= EXT_START_FF[0];
EXT_START_FF[2] <= EXT_START_FF[1];
end
assign EXT_START_SYNC = !EXT_START_FF[2] & EXT_START_FF[1];
reg [31:0] CNT;
wire [32:0] LAST_CNT;
assign LAST_CNT = CONF_DELAY_SYNC + CONF_WIDTH_SYNC;
reg [31:0] REAPAT_CNT;
always @(posedge PULSE_CLK) begin
if (RST_SYNC)
REAPAT_CNT <= 0;
else if(START_SYNC || (EXT_START_SYNC && CONF_EN_SYNC))
REAPAT_CNT <= CONF_REPEAT_SYNC;
else if(REAPAT_CNT != 0 && CNT == 1)
REAPAT_CNT <= REAPAT_CNT - 1;
end
always @(posedge PULSE_CLK) begin
if (RST_SYNC)
CNT <= 0; //IS THIS RIGHT?
else if(START_SYNC || (EXT_START_SYNC && CONF_EN_SYNC))
CNT <= 1;
else if(CNT == LAST_CNT && REAPAT_CNT != 0)
CNT <= 1;
else if(CNT == LAST_CNT && CONF_REPEAT_SYNC == 0)
CNT <= 1;
else if(CNT == LAST_CNT && REAPAT_CNT == 0)
CNT <= 0;
else if(CNT != 0)
CNT <= CNT + 1;
end
always @(posedge PULSE_CLK) begin
if(RST_SYNC || START_SYNC || (EXT_START_SYNC && CONF_EN_SYNC))
PULSE <= 0;
else if(CNT == CONF_DELAY_SYNC && CNT > 0)
PULSE <= 1;
else if(CNT == LAST_CNT)
PULSE <= 0;
end
wire DONE;
assign DONE = (CNT == 0);
wire DONE_SYNC;
cdc_pulse_sync done_pulse_sync (.clk_in(PULSE_CLK), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC));
wire EXT_START_SYNC_BUS;
cdc_pulse_sync ex_start_pulse_sync (.clk_in(PULSE_CLK), .pulse_in(EXT_START && CONF_EN), .clk_out(BUS_CLK), .pulse_out(EXT_START_SYNC_BUS));
always @(posedge BUS_CLK)
if(RST)
CONF_DONE <= 1;
else if(START || EXT_START_SYNC_BUS)
CONF_DONE <= 0;
else if(DONE_SYNC)
CONF_DONE <= 1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211AI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O211AI_BLACKBOX_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o211ai (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211AI_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 29.11.2016 16:55:54
// Design Name:
// Module Name: frequency_analyzer_testbench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module frequency_analyzer_synch_testbench;
reg clock;
reg reset;
reg enable;
wire start_analyzer_0;
wire stop_analyzer_0;
wire start_analyzer_1;
wire stop_analyzer_1;
frequency_analyzer_synch #(.FREQUENCY(2000), .CLOCK(100000000)) f(
.clock(clock),
.enable(enable),
.reset(reset),
.start_analyzer_0(start_analyzer_0),
.stop_analyzer_0(stop_analyzer_0),
.start_analyzer_1(start_analyzer_1),
.stop_analyzer_1(stop_analyzer_1));
initial begin
clock <= 1'b0;
reset <= 1'b0;
enable <= 1'b0;
reset <= #10 1'b1;
enable <= #10 1'b1;
end
always #5 clock <= ~clock;
endmodule |
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Sun Sep 22 03:32:42 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_processing_system7_0_2_stub.v
// Design : gcd_block_design_processing_system7_0_2
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(SDIO0_WP, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE,
DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr,
DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
input [0:0]IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [14:0] address_a;
input [14:0] address_b;
input clock;
input [7:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
altsyncram altsyncram_component (
.clock0 (clock),
.wren_a (wren_a),
.address_b (address_b),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32768,
altsyncram_component.numwords_b = 32768,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 15,
altsyncram_component.widthad_b = 15,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "262144"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 15 0 INPUT NODEFVAL "address_a[14..0]"
// Retrieval info: USED_PORT: address_b 0 0 15 0 INPUT NODEFVAL "address_b[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address_a 0 0 15 0
// Retrieval info: CONNECT: @address_b 0 0 15 0 address_b 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22O_0_V
`define SKY130_FD_SC_LP__A22O_0_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22o_0 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22o_0 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22O_0_V
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2000-2001 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised
// by a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement
// from Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: [email protected]
// =============================================================================
// FILE DETAILS
// Project : pci_express_top
// File : pci_express_top.v
// Title :
// Dependencies :
// Description : Top level for core.
// =============================================================================
module pcie_top (
// Clock and Reset
input wire refclkp, // 100MHz from board
input wire refclkn, // 100MHz from board
input wire rst_n,
// ASIC side pins for PCSA. These pins must exist for the PCS core.
input wire hdinp0,
input wire hdinn0,
output wire hdoutp0,
output wire hdoutn0,
input wire flip_lanes ,
input wire inta_n,
input wire [7:0] msi,
input wire [15:0] vendor_id ,
input wire [15:0] device_id ,
input wire [7:0] rev_id ,
input wire [23:0] class_code ,
input wire [15:0] subsys_ven_id ,
input wire [15:0] subsys_id ,
input wire load_id ,
input wire force_lsm_active, // Force LSM Status Active
input wire force_rec_ei, // Force Received Electrical Idle
input wire force_phy_status, // Force PHY Connection Status
input wire force_disable_scr,// Force Disable Scrambler to PCS
input wire hl_snd_beacon, // HL req. to Send Beacon
input wire hl_disable_scr, // HL req. to Disable Scrambling bit in TS1/TS2
input wire hl_gto_dis, // HL req a jump to Disable
input wire hl_gto_det, // HL req a jump to detect
input wire hl_gto_hrst, // HL req a jump to Hot reset
input wire hl_gto_l0stx, // HL req a jump to TX L0s
input wire hl_gto_l1, // HL req a jump to L1
input wire hl_gto_l2, // HL req a jump to L2
input wire hl_gto_l0stxfts, // HL req a jump to L0s TX FTS
input wire hl_gto_lbk, // HL req a jump to Loopback
input wire hl_gto_rcvry, // HL req a jump to recovery
input wire hl_gto_cfg, // HL req a jump to CFG
input wire no_pcie_train, // Disable the training process
// Power Management Interface
input wire [1:0] tx_dllp_val, // Req for Sending PM/Vendor type DLLP
input wire [2:0] tx_pmtype, // Power Management Type
input wire [23:0] tx_vsd_data, // Vendor Type DLLP contents
// For VC Inputs
input wire tx_req_vc0, // VC0 Request from User
input wire [15:0] tx_data_vc0, // VC0 Input data from user logic
input wire tx_st_vc0, // VC0 start of pkt from user logic.
input wire tx_end_vc0, // VC0 End of pkt from user logic.
input wire tx_nlfy_vc0, // VC0 End of nullified pkt from user logic.
input wire ph_buf_status_vc0, // VC0 Indicate the Full/alm.Full status of the PH buffers
input wire pd_buf_status_vc0, // VC0 Indicate PD Buffer has got space less than Max Pkt size
input wire nph_buf_status_vc0, // VC0 For NPH
input wire npd_buf_status_vc0, // VC0 For NPD
input wire ph_processed_vc0, // VC0 TL has processed one TLP Header - PH Type
input wire pd_processed_vc0, // VC0 TL has processed one TLP Data - PD TYPE
input wire nph_processed_vc0, // VC0 For NPH
input wire npd_processed_vc0, // VC0 For NPD
input wire [7:0] pd_num_vc0, // VC0 For PD -- No. of Data processed
input wire [7:0] npd_num_vc0, // VC0 For PD
// From User logic
input wire cmpln_tout , // Completion time out.
input wire cmpltr_abort_np , // Completor abort.
input wire cmpltr_abort_p , // Completor abort.
input wire unexp_cmpln , // Unexpexted completion.
input wire ur_np_ext , // UR for NP type.
input wire ur_p_ext , // UR for P type.
input wire np_req_pend , // Non posted request is pending.
input wire pme_status , // PME status to reg 044h.
// User Loop back data
input wire [15:0] tx_lbk_data, // TX User Master Loopback data
input wire [1:0] tx_lbk_kcntl, // TX User Master Loopback control
output wire tx_lbk_rdy, // TX loop back is ready to accept data
output wire [15:0] rx_lbk_data, // RX User Master Loopback data
output wire [1:0] rx_lbk_kcntl, // RX User Master Loopback control
// Power Management/ Vendor specific DLLP
output wire tx_dllp_sent, // Requested PM DLLP is sent
output wire [2:0] rxdp_pmd_type, // PM DLLP type bits.
output wire [23:0] rxdp_vsd_data , // Vendor specific DLLP data.
output wire [1:0] rxdp_dllp_val, // PM/Vendor specific DLLP valid.
output wire phy_pol_compliance, // Polling compliance
output wire [3:0] phy_ltssm_state, // Indicates the states of the ltssm
output wire [2:0] phy_ltssm_substate, // sub-states of the ltssm_state
//---------Outputs------------
output wire tx_rdy_vc0, // VC0 TX ready indicating signal
output wire [8:0] tx_ca_ph_vc0, // VC0 Available credit for Posted Type Headers
output wire [12:0] tx_ca_pd_vc0, // VC0 For Posted - Data
output wire [8:0] tx_ca_nph_vc0, // VC0 For Non-posted - Header
output wire [12:0] tx_ca_npd_vc0, // VC0 For Non-posted - Data
output wire [8:0] tx_ca_cplh_vc0, // VC0 For Completion - Header
output wire [12:0] tx_ca_cpld_vc0, // VC0 For Completion - Data
output wire tx_ca_p_recheck_vc0, //
output wire tx_ca_cpl_recheck_vc0, //
output wire [15:0] rx_data_vc0, // VC0 Receive data
output wire rx_st_vc0, // VC0 Receive data start
output wire rx_end_vc0, // VC0 Receive data end
output wire rx_us_req_vc0 , // VC0 unsupported req received
output wire rx_malf_tlp_vc0 ,// VC0 malformed TLP in received data
output wire [6:0] rx_bar_hit , // Bar hit
output wire [2:0] mm_enable , // Multiple message enable bits of Register
output wire msi_enable , // MSI enable bit of Register
// From Config Registers
output wire [7:0] bus_num , // Bus number
output wire [4:0] dev_num , // Device number
output wire [2:0] func_num , // Function number
output wire [1:0] pm_power_state , // Power state bits of Register at 044h
output wire pme_en , // PME_En at 044h
output wire [5:0] cmd_reg_out , // Bits 10,8,6,2,1,0 From register 004h
output wire [14:0] dev_cntl_out , // Divice control register at 060h
output wire [7:0] lnk_cntl_out , // Link control register at 068h
// Datal Link Control SM Status
output wire dl_inactive, // Data Link Control SM is in INACTIVE state
output wire dl_init, // INIT state
output wire dl_active, // ACTIVE state
output wire dl_up, // Data Link Layer is UP
output wire sys_clk_125 // 125MHz output clock from core
);
// =============================================================================
// Define Wires & Regs
// =============================================================================
reg [19:0] rstn_cnt;
reg core_rst_n;
wire irst_n ;
wire [1:0] power_down;
wire tx_detect_rx_lb;
wire phy_status;
wire [7:0] txp_data;
wire txp_data_k;
wire txp_elec_idle;
wire txp_compliance;
wire [7:0] rxp_data;
wire rxp_data_k;
wire rxp_valid;
wire rxp_polarity;
wire rxp_elec_idle;
wire [2:0] rxp_status;
wire pclk; //250MHz clk from PCS PIPE for 8 bit data
wire phy_l0;
assign phy_l0 = (phy_ltssm_state == 'd3) ;
// =============================================================================
// Reset management
// =============================================================================
reg sync_rst_n0, sync_rst_n1;
wire sync_rst_n;
always @(posedge sys_clk_125 or negedge rst_n) begin
if (!rst_n) begin
sync_rst_n0 <= 0;
sync_rst_n1 <= 0;
end
else begin
sync_rst_n0 <= rst_n;
sync_rst_n1 <= sync_rst_n0;
end
end
assign sync_rst_n = sync_rst_n1;
always @(posedge sys_clk_125 or negedge sync_rst_n) begin
if (!sync_rst_n) begin
rstn_cnt <= 20'd0 ;
core_rst_n <= 1'b0 ;
end
else begin
if (rstn_cnt[19]) // 4ms in real hardware
core_rst_n <= 1'b1 ;
// synthesis translate_off
else if (rstn_cnt[7]) // 128 clocks
core_rst_n <= 1'b1 ;
// synthesis translate_on
else
rstn_cnt <= rstn_cnt + 1'b1 ;
end
end
//GSR GSR_INST (.GSR(rst_n));
PUR PUR_INST (.PUR(1'b1));
// Connect rst_n pin to GSR, pipe wrapper, core and user logic
// assign irst_n = rst_n ;
// Connect rst_n pin to pipe wrapper, 4ms delayed rst_n to core and user logic
//assign irst_n = core_rst_n ;
// =============================================================================
// SERDES/PCS instantiation in PIPE mode
// =============================================================================
pcs_pipe_top u1_pcs_pipe (
.refclkp ( refclkp ),
.refclkn ( refclkn ),
// .ffc_quad_rst ( ~rst_n ),
.RESET_n ( rst_n ),
.pcie_ip_rstn ( irst_n ),
.hdinp0 ( hdinp0 ),
.hdinn0 ( hdinn0 ),
.hdoutp0 ( hdoutp0 ),
.hdoutn0 ( hdoutn0 ),
.TxData_0 ( txp_data ),
.TxDataK_0 ( txp_data_k ),
.TxCompliance_0 ( txp_compliance ),
.TxElecIdle_0 ( txp_elec_idle ),
.RxData_0 ( rxp_data ),
.RxDataK_0 ( rxp_data_k ),
.RxValid_0 ( rxp_valid ),
.RxPolarity_0 ( rxp_polarity ),
.RxElecIdle_0 ( rxp_elec_idle ),
.RxStatus_0 ( rxp_status ),
.scisel_0 ( 1'b0 ),
.scien_0 ( 1'b0 ),
.sciwritedata ( 8'h0 ),
.sciaddress ( 6'h0 ),
.scireaddata ( ),
.scienaux ( 1'b0 ),
.sciselaux ( 1'b0 ),
.scird ( 1'b0 ),
.sciwstn ( 1'b0 ),
.ffs_plol ( ),
.ffs_rlol_ch0 ( ),
.flip_lanes ( flip_lanes ),
.PCLK ( pclk ),
.PCLK_by_2 ( sys_clk_125 ),
.TxDetectRx_Loopback ( tx_detect_rx_lb ),
.PhyStatus ( phy_status ),
.PowerDown ( power_down ),
.phy_l0 ( phy_l0 ),
.phy_cfgln ( 4'b0000 ), //Not required (unused in X1 mode)
.ctc_disable ( 1'b0 )
);
// =============================================================================
// PCI Express Core
// =============================================================================
pcie u1_dut(
// Clock and Reset
.sys_clk_250 ( pclk ) ,
.sys_clk_125 ( sys_clk_125 ) ,
.rst_n ( irst_n ),
.inta_n ( inta_n ),
.msi ( msi ),
.vendor_id ( vendor_id ),
.device_id ( device_id ),
.rev_id ( rev_id ),
.class_code ( class_code ),
.subsys_ven_id ( subsys_ven_id ),
.subsys_id ( subsys_id ),
.load_id ( load_id ),
// Inputs
.force_lsm_active ( force_lsm_active ),
.force_rec_ei ( force_rec_ei ),
.force_phy_status ( force_phy_status ),
.force_disable_scr ( force_disable_scr ),
.hl_snd_beacon ( hl_snd_beacon ),
.hl_disable_scr ( hl_disable_scr ),
.hl_gto_dis ( hl_gto_dis ),
.hl_gto_det ( hl_gto_det ),
.hl_gto_hrst ( hl_gto_hrst ),
.hl_gto_l0stx ( hl_gto_l0stx ),
.hl_gto_l1 ( hl_gto_l1 ),
.hl_gto_l2 ( hl_gto_l2 ),
.hl_gto_l0stxfts ( hl_gto_l0stxfts ),
.hl_gto_lbk ( hl_gto_lbk ),
.hl_gto_rcvry ( hl_gto_rcvry ),
.hl_gto_cfg ( hl_gto_cfg ),
.no_pcie_train ( no_pcie_train ),
// Power Management Interface
.tx_dllp_val (tx_dllp_val ),
.tx_pmtype (tx_pmtype ),
.tx_vsd_data (tx_vsd_data ),
.tx_req_vc0 ( tx_req_vc0 ),
.tx_data_vc0 ( tx_data_vc0 ),
.tx_st_vc0 ( tx_st_vc0 ),
.tx_end_vc0 ( tx_end_vc0 ),
.tx_nlfy_vc0 ( tx_nlfy_vc0 ),
.ph_buf_status_vc0 ( ph_buf_status_vc0 ),
.pd_buf_status_vc0 ( pd_buf_status_vc0 ),
.nph_buf_status_vc0 ( nph_buf_status_vc0 ),
.npd_buf_status_vc0 ( npd_buf_status_vc0 ),
.ph_processed_vc0 ( ph_processed_vc0 ),
.pd_processed_vc0 ( pd_processed_vc0 ),
.nph_processed_vc0 ( nph_processed_vc0 ),
.npd_processed_vc0 ( npd_processed_vc0 ),
.pd_num_vc0 ( pd_num_vc0 ),
.npd_num_vc0 ( npd_num_vc0 ),
// From External PHY (PIPE I/F)
.rxp_data ( rxp_data ),
.rxp_data_k ( rxp_data_k ),
.rxp_valid ( rxp_valid ),
.rxp_elec_idle ( rxp_elec_idle ),
.rxp_status ( rxp_status ),
.phy_status ( phy_status),
// From User logic
.cmpln_tout ( cmpln_tout ),
.cmpltr_abort_np ( cmpltr_abort_np ),
.cmpltr_abort_p ( cmpltr_abort_p ),
.unexp_cmpln ( unexp_cmpln ),
.ur_np_ext ( ur_np_ext ) ,
.ur_p_ext ( ur_p_ext ) ,
.np_req_pend ( np_req_pend ),
.pme_status ( pme_status ),
.tx_lbk_data ( tx_lbk_data ),
.tx_lbk_kcntl ( tx_lbk_kcntl ),
.tx_lbk_rdy ( tx_lbk_rdy ),
.rx_lbk_data ( rx_lbk_data ),
.rx_lbk_kcntl ( rx_lbk_kcntl ),
// Power Management
.tx_dllp_sent ( tx_dllp_sent ),
.rxdp_pmd_type ( rxdp_pmd_type ),
.rxdp_vsd_data ( rxdp_vsd_data ),
.rxdp_dllp_val ( rxdp_dllp_val ),
//-------- Outputs
// To External PHY (PIPE I/F)
.txp_data ( txp_data ),
.txp_data_k ( txp_data_k ),
.txp_elec_idle ( txp_elec_idle ),
.txp_compliance ( txp_compliance ),
.rxp_polarity ( rxp_polarity ),
.txp_detect_rx_lb ( tx_detect_rx_lb ),
.reset_n ( ),
.power_down ( power_down ),
// From TX User Interface
.phy_ltssm_state ( phy_ltssm_state ),
.phy_ltssm_substate ( phy_ltssm_substate),
.phy_pol_compliance ( phy_pol_compliance),
.tx_rdy_vc0 ( tx_rdy_vc0),
.tx_ca_ph_vc0 ( tx_ca_ph_vc0),
.tx_ca_pd_vc0 ( tx_ca_pd_vc0),
.tx_ca_nph_vc0 ( tx_ca_nph_vc0),
.tx_ca_npd_vc0 ( tx_ca_npd_vc0),
.tx_ca_cplh_vc0 ( tx_ca_cplh_vc0),
.tx_ca_cpld_vc0 ( tx_ca_cpld_vc0),
.tx_ca_p_recheck_vc0 ( tx_ca_p_recheck_vc0 ),
.tx_ca_cpl_recheck_vc0 ( tx_ca_cpl_recheck_vc0 ),
.rx_data_vc0 ( rx_data_vc0),
.rx_st_vc0 ( rx_st_vc0),
.rx_end_vc0 ( rx_end_vc0),
.rx_us_req_vc0 ( rx_us_req_vc0 ),
.rx_malf_tlp_vc0 ( rx_malf_tlp_vc0 ),
.rx_bar_hit ( rx_bar_hit ),
.mm_enable ( mm_enable ) ,
.msi_enable ( msi_enable ) ,
// From Config Registers
.bus_num ( bus_num ) ,
.dev_num ( dev_num ) ,
.func_num ( func_num ) ,
.pm_power_state ( pm_power_state ) ,
.pme_en ( pme_en ) ,
.cmd_reg_out ( cmd_reg_out ),
.dev_cntl_out ( dev_cntl_out ),
.lnk_cntl_out ( lnk_cntl_out ),
// To ASPM implementation outside the IP
.tx_rbuf_empty ( ),
.tx_dllp_pend ( ),
.rx_tlp_rcvd ( ),
// Datal Link Control SM Status
.dl_inactive ( dl_inactive ),
.dl_init ( dl_init ),
.dl_active ( dl_active ),
.dl_up ( dl_up )
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_PP_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_PP_V |
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 1.1
// \ \ Application : MIG
// / / Filename : mig_7series_v1_1.v
// /___/ /\ Date Last Modified : $Date: 2010/11/09 17:40:54 $
// \ \ / \ Date Created : Mon Jun 23 2008
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR3 SDRAM
// Purpose :
// Top-level module. This module can be instantiated in the
// system and interconnect as shown in example design (example_top module).
// In addition to the memory controller, the module instantiates:
// 1. Clock generation/distribution, reset logic
// 2. IDELAY control block
// 3. Debug logic
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_1 #
(
//***************************************************************************
// The following parameters refer to width of various ports
//***************************************************************************
parameter BANK_WIDTH = 3,
// # of memory Bank Address bits.
parameter CK_WIDTH = 1,
// # of CK/CK# outputs to memory.
parameter COL_WIDTH = 10,
// # of memory Column Address bits.
parameter CS_WIDTH = 1,
// # of unique CS outputs to memory.
parameter nCS_PER_RANK = 1,
// # of unique CS outputs per rank for phy
parameter CKE_WIDTH = 1,
// # of CKE outputs to memory.
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DQ_CNT_WIDTH = 6,
// = ceil(log2(DQ_WIDTH))
parameter DQ_PER_DM = 8,
parameter DM_WIDTH = 8,
// # of DM (data mask)
parameter DQ_WIDTH = 64,
// # of DQ (data)
parameter DQS_WIDTH = 8,
parameter DQS_CNT_WIDTH = 3,
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8,
// # of DQ per DQS
parameter DATA_WIDTH = 64,
parameter ECC_TEST = "OFF",
parameter PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH,
parameter ECC = "OFF",
parameter ECC_WIDTH = 8,
parameter MC_ERR_ADDR_WIDTH = 31,
parameter nBANK_MACHS = 4,
parameter RANKS = 1,
// # of Ranks.
parameter ROW_WIDTH = 14,
// # of memory Row Address bits.
parameter ADDR_WIDTH = 28,
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
parameter USE_DM_PORT = 1,
// # = 1, When Data Mask option is enabled
// = 0, When Data Mask option is disbaled
// When Data Mask option is disabled in
// MIG Controller Options page, the logic
// related to Data Mask should not get
// synthesized
parameter USE_ODT_PORT = 1,
// # = 1, When ODT output is enabled
// = 0, When ODT output is disabled
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter AL = "0",
// DDR3 SDRAM:
// Additive Latency (Mode Register 1).
// # = "0", "CL-1", "CL-2".
// DDR2 SDRAM:
// Additive Latency (Extended Mode Register).
parameter nAL = 0,
// # Additive Latency in number of clock
// cycles.
parameter BURST_MODE = "8",
// DDR3 SDRAM:
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
// DDR2 SDRAM:
// Burst Length (Mode Register).
// # = "8", "4".
parameter BURST_TYPE = "SEQ",
// DDR3 SDRAM: Burst Type (Mode Register 0).
// DDR2 SDRAM: Burst Type (Mode Register).
// # = "SEQ" - (Sequential),
// = "INT" - (Interleaved).
parameter CL = 6,
// in number of clock cycles
// DDR3 SDRAM: CAS Latency (Mode Register 0).
// DDR2 SDRAM: CAS Latency (Mode Register).
parameter CWL = 5,
// in number of clock cycles
// DDR3 SDRAM: CAS Write Latency (Mode Register 2).
// DDR2 SDRAM: Can be ignored
parameter DDR2_DQSN_ENABLE = "YES",
// Enable differential DQS for DDR2
parameter OUTPUT_DRV = "HIGH",
// Output Driver Impedance Control (Mode Register 1).
// # = "HIGH" - RZQ/7,
// = "LOW" - RZQ/6.
parameter RTT_NOM = "60",
// RTT_NOM (ODT) (Mode Register 1).
// # = "DISABLED" - RTT_NOM disabled,
// = "120" - RZQ/2,
// = "60" - RZQ/4,
// = "40" - RZQ/6.
parameter RTT_WR = "OFF",
// RTT_WR (ODT) (Mode Register 2).
// # = "OFF" - Dynamic ODT off,
// = "120" - RZQ/2,
// = "60" - RZQ/4,
parameter ADDR_CMD_MODE = "1T" ,
// # = "1T", "2T".
parameter REG_CTRL = "OFF",
// # = "ON" - RDIMMs,
// = "OFF" - Components, SODIMMs, UDIMMs.
//***************************************************************************
// The following parameters are multiplier and divisor factors for MMCM.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
parameter CLKFBOUT_MULT_F = 4,
// write PLL VCO multiplier
parameter DIVCLK_DIVIDE = 1,
// write PLL VCO divisor
parameter CLKOUT_DIVIDE = 4,
// VCO output divisor for fast (memory) clocks
//***************************************************************************
// Memory Timing Parameters. These parameters varies based on the selected
// memory part.
//***************************************************************************
parameter tFAW = 30000,
// memory tRAW paramter in pS.
parameter tPRDI = 1_000_000,
// memory tPRDI paramter in pS.
parameter tRAS = 35000,
// memory tRAS paramter in pS.
parameter tRCD = 13750,
// memory tRCD paramter in pS.
parameter tREFI = 7800000,
// memory tREFI paramter in pS.
parameter tRFC = 110000,
// memory tRFC paramter in pS.
parameter tRP = 13750,
// memory tRP paramter in pS.
parameter tRRD = 6000,
// memory tRRD paramter in pS.
parameter tRTP = 7500,
// memory tRTP paramter in pS.
parameter tWTR = 7500,
// memory tWTR paramter in pS.
parameter tZQI = 128_000_000,
// memory tZQI paramter in nS.
parameter tZQCS = 64,
// memory tZQCS paramter in clock cycles.
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIM_BYPASS_INIT_CAL = "OFF",
// # = "OFF" - Complete memory init &
// calibration sequence
// # = "SKIP" - Not supported
// # = "FAST" - Complete memory init & use
// abbreviated calib sequence
//***************************************************************************
// The following parameters varies based on the pin out entered in MIG GUI.
// Do not change any of these parameters directly by editing the RTL.
// Any changes required should be done through GUI and the design regenerated.
//***************************************************************************
parameter BYTE_LANES_B0 = 4'b1111,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B1 = 4'b1110,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B2 = 4'b1111,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B3 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B4 = 4'b0000,
// Byte lanes used in an IO column.
parameter DATA_CTL_B0 = 4'hF,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B1 = 4'h0,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B2 = 4'hF,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B3 = 4'h0,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B4 = 4'h0,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter PHY_0_BITLANES = 48'h3FE_3FE_3FE_2FF,
parameter PHY_1_BITLANES = 48'hFFF_FFE_000_000,
parameter PHY_2_BITLANES = 48'h3FE_3FE_3FE_2FF,
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_13,
parameter ADDR_MAP
= 192'h000_000_139_138_137_136_135_134_133_132_131_130_129_128_127_126,
parameter BANK_MAP = 36'h12B_12A_125,
parameter CAS_MAP = 12'h123,
parameter CKE_ODT_BYTE_MAP = 8'h13,
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_121,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h124,
parameter WE_MAP = 12'h122,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_20_21_22_23_00_01_02_03,
parameter DATA0_MAP = 96'h031_032_033_034_035_036_037_038,
parameter DATA1_MAP = 96'h021_022_023_024_025_026_027_028,
parameter DATA2_MAP = 96'h011_012_013_014_015_016_017_018,
parameter DATA3_MAP = 96'h000_001_002_003_004_005_006_007,
parameter DATA4_MAP = 96'h231_232_233_234_235_236_237_238,
parameter DATA5_MAP = 96'h221_222_223_224_225_226_227_228,
parameter DATA6_MAP = 96'h211_212_213_214_215_216_217_218,
parameter DATA7_MAP = 96'h200_201_202_203_204_205_206_207,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter MASK0_MAP = 108'h000_209_219_229_239_009_019_029_039,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter SLOT_0_CONFIG = 8'b0000_0001,
// Mapping of Ranks.
parameter SLOT_1_CONFIG = 8'b0000_0000,
// Mapping of Ranks.
parameter MEM_ADDR_ORDER
= "ROW_BANK_COLUMN",
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter IODELAY_HP_MODE = "ON",
// to phy_top
parameter IBUF_LPWR_MODE = "OFF",
// to phy_top
parameter WRLVL = "ON",
// # = "ON" - DDR3 SDRAM
// = "OFF" - DDR2 SDRAM.
parameter ORDERING = "NORM",
// # = "NORM", "STRICT", "RELAXED".
parameter CALIB_ROW_ADD = 16'h0000,
// Calibration row address will be used for
// calibration read and write operations
parameter CALIB_COL_ADD = 12'h000,
// Calibration column address will be used for
// calibration read and write operations
parameter CALIB_BA_ADD = 3'h0,
// Calibration bank address will be used for
// calibration read and write operations
parameter TCQ = 100,
parameter IODELAY_GRP = "IODELAY_MIG",
// It is associated to a set of IODELAYs with
// an IDELAYCTRL that have same IODELAY CONTROLLER
// clock frequency.
parameter INPUT_CLK_TYPE = "DIFFERENTIAL",
// input clock type DIFFERNTIAL or SINGLE_ENDED
parameter RST_ACT_LOW = 1,
// =1 for active low reset,
// =0 for active high.
parameter CAL_WIDTH = "HALF",
parameter STARVE_LIMIT = 2,
// # = 2,3,4.
parameter CMD_PIPE_PLUS1 = "ON",
// add pipeline stage between MC and PHY
//***************************************************************************
// System clock and Referece clock frequency parameters
//***************************************************************************
parameter REFCLK_FREQ = 200.0,
// IODELAYCTRL reference clock frequency
parameter tCK = 2500,
// memory tCK paramter.
// # = Clock Period in pS.
parameter nCK_PER_CLK = 4,
// # of memory CKs per fabric CLK
parameter DIFF_TERM = "FALSE",
// Differential Termination
//***************************************************************************
// Debug parameters
//***************************************************************************
parameter DEBUG_PORT = "OFF",
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
parameter DRAM_TYPE = "DDR3"
)
(
// Inouts
inout [DQ_WIDTH-1:0] ddr3_dq,
inout [DQS_WIDTH-1:0] ddr3_dqs_n,
inout [DQS_WIDTH-1:0] ddr3_dqs_p,
// Outputs
output [ROW_WIDTH-1:0] ddr3_addr,
output [BANK_WIDTH-1:0] ddr3_ba,
output ddr3_ras_n,
output ddr3_cas_n,
output ddr3_we_n,
output ddr3_reset_n,
output [CK_WIDTH-1:0] ddr3_ck_p,
output [CK_WIDTH-1:0] ddr3_ck_n,
output [CKE_WIDTH-1:0] ddr3_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr3_cs_n,
output [DM_WIDTH-1:0] ddr3_dm,
output [RANKS-1:0] ddr3_odt,
// Inputs
// Differential system clocks
input sys_clk_p,
input sys_clk_n,
// differential iodelayctrl clk (reference clock)
input clk_ref_p,
input clk_ref_n,
// user interface signals
input [ADDR_WIDTH-1:0] app_addr,
input [2:0] app_cmd,
input app_en,
input [(nCK_PER_CLK*2*PAYLOAD_WIDTH)-1:0] app_wdf_data,
input app_wdf_end,
input [(nCK_PER_CLK*2*PAYLOAD_WIDTH)/8-1:0] app_wdf_mask,
input app_wdf_wren,
output [(nCK_PER_CLK*2*PAYLOAD_WIDTH)-1:0] app_rd_data,
output app_rd_data_valid,
output app_rdy,
output app_wdf_rdy,
output tb_clk,
output tb_rst,
output init_calib_complete,
// System reset
input sys_rst
);
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam BM_CNT_WIDTH = clogb2(nBANK_MACHS);
localparam RANK_WIDTH = clogb2(RANKS);
localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
// Wire declarations
wire [BM_CNT_WIDTH-1:0] bank_mach_next;
wire clk;
wire clk_ref;
wire idelay_ctrl_rdy;
wire freq_refclk ;
wire mem_refclk ;
wire pll_lock ;
wire sync_pulse;
wire rst;
wire [2*nCK_PER_CLK-1:0] app_ecc_multiple_err_i;
wire sys_clk_i;
wire mmcm_clk;
wire clk_ref_i;
// Debug port signals
wire dbg_idel_down_all;
wire dbg_idel_down_cpt;
wire dbg_idel_up_all;
wire dbg_idel_up_cpt;
wire dbg_sel_all_idel_cpt;
wire [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt;
wire [255:0] dbg_calib_top;
wire [5*DQS_WIDTH-1:0] dbg_cpt_first_edge_cnt;
wire [5*DQS_WIDTH-1:0] dbg_cpt_second_edge_cnt;
wire [255:0] dbg_phy_rdlvl;
wire [15:0] dbg_phy_wrcal;
wire [DQS_WIDTH-1:0] dbg_rd_data_edge_detect;
wire [4*DQ_WIDTH-1:0] dbg_rddata;
wire [1:0] dbg_rdlvl_done;
wire [1:0] dbg_rdlvl_err;
wire [1:0] dbg_rdlvl_start;
wire [4:0] dbg_tap_cnt_during_wrlvl;
wire dbg_wl_edge_detect_valid;
wire dbg_wrlvl_done;
wire dbg_wrlvl_err;
wire dbg_wrlvl_start;
//
wire [383:0] ddr3_ila_data;
wire [7:0] ddr3_ila_trig;
wire [255:0] ddr3_vio0_async_in;
wire [255:0] ddr3_vio1_async_in;
wire [255:0] ddr3_vio2_async_in;
wire [31:0] ddr3_vio3_sync_out;
//***************************************************************************
assign tb_clk = clk;
assign tb_rst = rst;
assign sys_clk_i = 1'b0;
assign clk_ref_i = 1'b0;
iodelay_ctrl #
(
.TCQ (TCQ),
.IODELAY_GRP (IODELAY_GRP),
.INPUT_CLK_TYPE (INPUT_CLK_TYPE),
.RST_ACT_LOW (RST_ACT_LOW)
)
u_iodelay_ctrl
(
// Outputs
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.clk_ref (clk_ref),
// Inputs
.clk_ref_p (clk_ref_p),
.clk_ref_n (clk_ref_n),
.clk_ref_i (clk_ref_i),
.sys_rst (sys_rst)
);
clk_ibuf#
(
.INPUT_CLK_TYPE (INPUT_CLK_TYPE),
.DIFF_TERM (DIFF_TERM)
)
u_ddr3_clk_ibuf
(
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.sys_clk_i (sys_clk_i),
.mmcm_clk (mmcm_clk)
);
infrastructure #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (tCK),
.INPUT_CLK_TYPE (INPUT_CLK_TYPE),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKOUT_DIVIDE (CLKOUT_DIVIDE),
.RST_ACT_LOW (RST_ACT_LOW)
)
u_ddr3_infrastructure
(
// Outputs
.rstdiv0 (rst),
.clk (clk),
.mem_refclk (mem_refclk),
.freq_refclk (freq_refclk),
.sync_pulse (sync_pulse),
.pll_locked (pll_locked),
// Inputs
.mmcm_clk (mmcm_clk),
.sys_rst (sys_rst),
.iodelay_ctrl_rdy (iodelay_ctrl_rdy)
);
memc_ui_top_std #
(
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.ECC_TEST (ECC_TEST),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.IODELAY_GRP (IODELAY_GRP),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.CL (CL),
.CWL (CWL),
.tCK (tCK),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
.STARVE_LIMIT (STARVE_LIMIT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT)
)
u_memc_ui_top_std
(
.clk (clk),
.clk_ref (clk_ref),
.mem_refclk (mem_refclk), //memory clock
.freq_refclk (freq_refclk),
.pll_lock (pll_locked),
.sync_pulse (sync_pulse),
.rst (rst),
// Memory interface ports
.ddr_dq (ddr3_dq),
.ddr_dqs_n (ddr3_dqs_n),
.ddr_dqs (ddr3_dqs_p),
.ddr_addr (ddr3_addr),
.ddr_ba (ddr3_ba),
.ddr_cas_n (ddr3_cas_n),
.ddr_ck_n (ddr3_ck_n),
.ddr_ck (ddr3_ck_p),
.ddr_cke (ddr3_cke),
.ddr_cs_n (ddr3_cs_n),
.ddr_dm (ddr3_dm),
.ddr_odt (ddr3_odt),
.ddr_ras_n (ddr3_ras_n),
.ddr_reset_n (ddr3_reset_n),
.ddr_parity (ddr3_parity),
.ddr_we_n (ddr3_we_n),
.bank_mach_next (bank_mach_next),
// Application interface ports
.app_addr (app_addr),
.app_cmd (app_cmd),
.app_en (app_en),
.app_hi_pri (1'b1),
.app_sz (1'b1),
.app_wdf_data (app_wdf_data),
.app_wdf_end (app_wdf_end),
.app_wdf_mask (app_wdf_mask),
.app_wdf_wren (app_wdf_wren),
.app_ecc_multiple_err (app_ecc_multiple_err_i),
.app_rd_data (app_rd_data),
.app_rd_data_end (app_rd_data_end),
.app_rd_data_valid (app_rd_data_valid),
.app_rdy (app_rdy),
.app_wdf_rdy (app_wdf_rdy),
// Debug logic ports
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.init_calib_complete (init_calib_complete)
);
//*****************************************************************
// PHY Debug Port Example:
// * This provides a limited Chipscope Interface for observing
// PHY signals (outputs of read and write timing calibration,
// general status, synchronized read data), and a mechanism for
// dynamically changing some of the IODELAY elements used to
// adjust timing in the read data path.
// * This logic supports up to the first 72 DQ and 18 DQS groups.
// Larger interfaces will require manual modification and
// additional Chipscope blocks to support monitoring of the
// additional DQS groups. Smaller interfaces can also obviously
// use smaller ILA cores (user will have to generate these
// themselves) if resources or timing is a concern
//*****************************************************************
// If debug port is not enabled, then make certain control input
// to Debug Port are disabled
generate
if (DEBUG_PORT != "ON") begin: gen_dbg_tie_off
assign dbg_idel_down_all = 1'b0;
assign dbg_idel_down_cpt = 1'b0;
assign dbg_idel_up_all = 1'b0;
assign dbg_idel_up_cpt = 1'b0;
assign dbg_sel_all_idel_cpt = 1'b0;
assign dbg_sel_idel_cpt = 'b0;
end else begin: gen_dbg_enable
// Connect these to VIO if changing output IODELAY taps desired
// IODELAY taps desired
assign dbg_idel_down_all = 1'b0;
assign dbg_idel_down_cpt = 1'b0;
assign dbg_idel_up_all = 1'b0;
assign dbg_idel_up_cpt = 1'b0;
assign dbg_sel_all_idel_cpt = 1'b0;
assign dbg_sel_idel_cpt = 'b0;
//*******************************************************
// CS0 - ILA for monitoring PHY status, testbench error,
// and synchronized read data
//*******************************************************
// Assignments for ILA monitoring general PHY
// status and synchronized read data
assign ddr3_ila_trig[1:0] = dbg_rdlvl_done;
assign ddr3_ila_trig[3:2] = dbg_rdlvl_err;
assign ddr3_ila_trig[4] = init_calib_complete;
assign ddr3_ila_trig[5] = 1'b0; // Reserve for ERROR from TrafficGen
assign ddr3_ila_trig[7:5] = 'b0;
// Support for only up to 72-bits of data
if (DQ_WIDTH <= 72) begin: gen_dq_le_72
assign ddr3_ila_data[4*DQ_WIDTH-1:0] = dbg_rddata;
end else begin: gen_dq_gt_72
assign ddr3_ila_data[287:0] = dbg_rddata[287:0];
end
assign ddr3_ila_data[289:288] = dbg_rdlvl_done;
assign ddr3_ila_data[291:290] = dbg_rdlvl_err;
assign ddr3_ila_data[292] = init_calib_complete;
assign ddr3_ila_data[293] = 1'b0; // Reserve for ERROR from TrafficGen
assign ddr3_ila_data[383:294] = 'b0;
//*******************************************************
// CS1 - Input VIO for monitoring PHY status and
// write leveling/calibration delays
//*******************************************************
// Currently unused
assign ddr3_vio0_async_in = 'b0;
//*******************************************************
// CS2 - Input VIO for monitoring Read Calibration
// results.
//*******************************************************
// Currently unused
assign ddr3_vio1_async_in = 'b0;
//*******************************************************
// CS3 - Input VIO for monitoring more Read Calibration
// results.
//*******************************************************
// Support for only up to 18 DQS groups
if (DQS_WIDTH <= 18) begin: gen_dqs_le_18_cs3
assign ddr3_vio2_async_in[5*DQS_WIDTH-1:0] = dbg_cpt_first_edge_cnt;
assign ddr3_vio2_async_in[5*DQS_WIDTH+89:90] = dbg_cpt_second_edge_cnt;
end else begin: gen_dqs_gt_18_cs3
assign ddr3_vio2_async_in[89:0] = dbg_cpt_first_edge_cnt[89:0];
assign ddr3_vio2_async_in[179:90] = dbg_cpt_second_edge_cnt[89:0];
end
assign ddr3_vio2_async_in[255:180] = 'b0;
//*******************************************************
// CS4 - Output VIO for disabling OCB monitor, Read Phase
// Detector, and dynamically changing various
// IODELAY values used for adjust read data capture
// timing
//*******************************************************
// Currently unused
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__AND3_FUNCTIONAL_PP_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , C, A, B );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3_FUNCTIONAL_PP_V |
module ultrasonic_control (
input clk ,
input enable ,
input signal ,
output [15:0] value ,
output reg busy
) ;
reg [2:0] state ;
reg rst_clk_n ;
reg rst_ult_n ;
reg enableClk ;
reg enable_fisico ;
wire [31:0] clkValue ;
wire start ;
wire done_ult ;
// Definición de estados
localparam S0 = 3'b000 ; // Estado reset
localparam S1 = 3'b001 ; // Envia señal al físico
localparam S2 = 3'b010 ; // Espera nuevo ciclo
always @ ( negedge clk )
if ( enable )
case ( state )
S0:
state <= S1 ;
S1:
if ( !busy )
state <= S2 ;
else
state <= S1 ;
S2:
state <= state ;
default:
state <= S0 ;
endcase
else
state <= S0 ;
// Logica de estados
always @ ( posedge clk)
case ( state )
S0: begin
rst_clk_n <= 0 ;
rst_ult_n <= 0 ;
enableClk <= 0 ;
enable_fisico <= 0 ;
end S1: begin
rst_clk_n <= 1 ;
rst_ult_n <= 1 ;
enableClk <= 1 ;
enable_fisico <= 1 ;
busy <= 1 ;
end S2: begin
rst_clk_n <= 1 ;
rst_ult_n <= 1 ;
enableClk <= 1 ;
enable_fisico <= 0 ;
busy <= 0 ;
end default: begin
rst_clk_n <= 0 ;
rst_ult_n <= 0 ;
enableClk <= 0 ;
enable_fisico <= 0 ;
busy <= 0 ;
end
endcase
// Modulos instanciados
// Mide el tiempo total desde el inicio del iclo hasta el final
clk_counter medidorDeTiempo (
.clk (clk) ,
.enable (enableClk) ,
.rst_n (rst_clk_n) ,
.clkValue(clkValue)
) ;
// Mide la duración de la señal del módulo físico
ultrasonic modulo (
.clk (clk) ,
.signal (signal) ,
.rst_n (rst_ult_n) ,
.value (value) ,
.done (done_ult)
);
// Controla el módulo físico
control_fisico control_fisico (
.clk(clk),
.enable(enable_fisico) ,
.clkValue(clkValue) ,
.start(start)
);
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* IPv4 block, ethernet frame interface
*/
module ip
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [7:0] s_eth_payload_axis_tdata,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire s_eth_payload_axis_tuser,
/*
* Ethernet frame output
*/
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [7:0] m_eth_payload_axis_tdata,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire m_eth_payload_axis_tuser,
/*
* ARP requests
*/
output wire arp_request_valid,
input wire arp_request_ready,
output wire [31:0] arp_request_ip,
input wire arp_response_valid,
output wire arp_response_ready,
input wire arp_response_error,
input wire [47:0] arp_response_mac,
/*
* IP input
*/
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [7:0] s_ip_payload_axis_tdata,
input wire s_ip_payload_axis_tvalid,
output wire s_ip_payload_axis_tready,
input wire s_ip_payload_axis_tlast,
input wire s_ip_payload_axis_tuser,
/*
* IP output
*/
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [47:0] m_ip_eth_dest_mac,
output wire [47:0] m_ip_eth_src_mac,
output wire [15:0] m_ip_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [7:0] m_ip_payload_axis_tdata,
output wire m_ip_payload_axis_tvalid,
input wire m_ip_payload_axis_tready,
output wire m_ip_payload_axis_tlast,
output wire m_ip_payload_axis_tuser,
/*
* Status
*/
output wire rx_busy,
output wire tx_busy,
output wire rx_error_header_early_termination,
output wire rx_error_payload_early_termination,
output wire rx_error_invalid_header,
output wire rx_error_invalid_checksum,
output wire tx_error_payload_early_termination,
output wire tx_error_arp_failed,
/*
* Configuration
*/
input wire [47:0] local_mac,
input wire [31:0] local_ip
);
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_ARP_QUERY = 2'd1,
STATE_WAIT_PACKET = 2'd2;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg outgoing_ip_hdr_valid_reg = 1'b0, outgoing_ip_hdr_valid_next;
wire outgoing_ip_hdr_ready;
reg [47:0] outgoing_eth_dest_mac_reg = 48'h000000000000, outgoing_eth_dest_mac_next;
wire outgoing_ip_payload_axis_tready;
/*
* IP frame processing
*/
ip_eth_rx
ip_eth_rx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(m_ip_hdr_valid),
.m_ip_hdr_ready(m_ip_hdr_ready),
.m_eth_dest_mac(m_ip_eth_dest_mac),
.m_eth_src_mac(m_ip_eth_src_mac),
.m_eth_type(m_ip_eth_type),
.m_ip_version(m_ip_version),
.m_ip_ihl(m_ip_ihl),
.m_ip_dscp(m_ip_dscp),
.m_ip_ecn(m_ip_ecn),
.m_ip_length(m_ip_length),
.m_ip_identification(m_ip_identification),
.m_ip_flags(m_ip_flags),
.m_ip_fragment_offset(m_ip_fragment_offset),
.m_ip_ttl(m_ip_ttl),
.m_ip_protocol(m_ip_protocol),
.m_ip_header_checksum(m_ip_header_checksum),
.m_ip_source_ip(m_ip_source_ip),
.m_ip_dest_ip(m_ip_dest_ip),
.m_ip_payload_axis_tdata(m_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(m_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(m_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(m_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(m_ip_payload_axis_tuser),
// Status signals
.busy(rx_busy),
.error_header_early_termination(rx_error_header_early_termination),
.error_payload_early_termination(rx_error_payload_early_termination),
.error_invalid_header(rx_error_invalid_header),
.error_invalid_checksum(rx_error_invalid_checksum)
);
ip_eth_tx
ip_eth_tx_inst (
.clk(clk),
.rst(rst),
// IP frame input
.s_ip_hdr_valid(outgoing_ip_hdr_valid_reg),
.s_ip_hdr_ready(outgoing_ip_hdr_ready),
.s_eth_dest_mac(outgoing_eth_dest_mac_reg),
.s_eth_src_mac(local_mac),
.s_eth_type(16'h0800),
.s_ip_dscp(s_ip_dscp),
.s_ip_ecn(s_ip_ecn),
.s_ip_length(s_ip_length),
.s_ip_identification(16'd0),
.s_ip_flags(3'b010),
.s_ip_fragment_offset(13'd0),
.s_ip_ttl(s_ip_ttl),
.s_ip_protocol(s_ip_protocol),
.s_ip_source_ip(s_ip_source_ip),
.s_ip_dest_ip(s_ip_dest_ip),
.s_ip_payload_axis_tdata(s_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(s_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(outgoing_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(s_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(s_ip_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// Status signals
.busy(tx_busy),
.error_payload_early_termination(tx_error_payload_early_termination)
);
reg s_ip_hdr_ready_reg = 1'b0, s_ip_hdr_ready_next;
reg arp_request_valid_reg = 1'b0, arp_request_valid_next;
reg arp_response_ready_reg = 1'b0, arp_response_ready_next;
reg drop_packet_reg = 1'b0, drop_packet_next;
assign s_ip_hdr_ready = s_ip_hdr_ready_reg;
assign s_ip_payload_axis_tready = outgoing_ip_payload_axis_tready || drop_packet_reg;
assign arp_request_valid = arp_request_valid_reg;
assign arp_request_ip = s_ip_dest_ip;
assign arp_response_ready = arp_response_ready_reg;
assign tx_error_arp_failed = arp_response_error;
always @* begin
state_next = STATE_IDLE;
arp_request_valid_next = arp_request_valid_reg && !arp_request_ready;
arp_response_ready_next = 1'b0;
drop_packet_next = 1'b0;
s_ip_hdr_ready_next = 1'b0;
outgoing_ip_hdr_valid_next = outgoing_ip_hdr_valid_reg && !outgoing_ip_hdr_ready;
outgoing_eth_dest_mac_next = outgoing_eth_dest_mac_reg;
case (state_reg)
STATE_IDLE: begin
// wait for outgoing packet
if (s_ip_hdr_valid) begin
// initiate ARP request
arp_request_valid_next = 1'b1;
arp_response_ready_next = 1'b1;
state_next = STATE_ARP_QUERY;
end else begin
state_next = STATE_IDLE;
end
end
STATE_ARP_QUERY: begin
arp_response_ready_next = 1'b1;
if (arp_response_valid) begin
// wait for ARP reponse
if (arp_response_error) begin
// did not get MAC address; drop packet
s_ip_hdr_ready_next = 1'b1;
drop_packet_next = 1'b1;
state_next = STATE_WAIT_PACKET;
end else begin
// got MAC address; send packet
s_ip_hdr_ready_next = 1'b1;
outgoing_ip_hdr_valid_next = 1'b1;
outgoing_eth_dest_mac_next = arp_response_mac;
state_next = STATE_WAIT_PACKET;
end
end else begin
state_next = STATE_ARP_QUERY;
end
end
STATE_WAIT_PACKET: begin
drop_packet_next = drop_packet_reg;
// wait for packet transfer to complete
if (s_ip_payload_axis_tlast && s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_PACKET;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
arp_request_valid_reg <= 1'b0;
arp_response_ready_reg <= 1'b0;
drop_packet_reg <= 1'b0;
s_ip_hdr_ready_reg <= 1'b0;
outgoing_ip_hdr_valid_reg <= 1'b0;
end else begin
state_reg <= state_next;
arp_request_valid_reg <= arp_request_valid_next;
arp_response_ready_reg <= arp_response_ready_next;
drop_packet_reg <= drop_packet_next;
s_ip_hdr_ready_reg <= s_ip_hdr_ready_next;
outgoing_ip_hdr_valid_reg <= outgoing_ip_hdr_valid_next;
end
outgoing_eth_dest_mac_reg <= outgoing_eth_dest_mac_next;
end
endmodule
|
module control(OP, CISEL, BSEL, OSEL, SHIFT_LA, SHIFT_LR, LOGICAL_OP); // add other inputs and outputs here
// inputs (add others here)
input [2:0] OP;
// outputs (add others here)
output CISEL;
output BSEL;
output [1:0] OSEL;
output SHIFT_LA;
output SHIFT_LR;
output LOGICAL_OP;
// reg and internal variable definitions
reg [1:0] OSEL;
reg SHIFT_LA;
reg SHIFT_LR;
reg LOGICAL_OP;
localparam ADD = 3'b000;
localparam SUB = 3'b001;
localparam SRA = 3'b010;
localparam SRL = 3'b011;
localparam SLL = 3'b100;
localparam AND = 3'b101;
localparam OR = 3'b110;
// implement module here (add other control signals below)
assign CISEL = (OP == 3'b001) ? 1'b1 : 1'b0;
assign BSEL = (OP == 3'b001) ? 1'b1 : 1'b0;
always @(*) begin
case (OP)
ADD: begin
OSEL = 2'b0;
SHIFT_LA = 1'b0;
SHIFT_LR = 1'b0;
LOGICAL_OP = 1'b0;
end
SUB: begin
OSEL = 2'b0;
SHIFT_LA = 1'b0;
SHIFT_LR = 1'b0;
LOGICAL_OP = 1'b0;
end
SRA: begin
OSEL = 2'b01;
SHIFT_LA = 1'b1;
SHIFT_LR = 1'b1;
LOGICAL_OP = 1'b0;
end
SRL: begin
OSEL = 2'b01;
SHIFT_LA = 1'b0;
SHIFT_LR = 1'b1;
LOGICAL_OP = 1'b0;
end
SLL: begin
OSEL = 2'b01;
SHIFT_LA = 1'b1;
SHIFT_LR = 1'b0;
LOGICAL_OP = 1'b0;
end
AND: begin
OSEL = 2'b10;
SHIFT_LA = 1'b0;
SHIFT_LR = 1'b0;
LOGICAL_OP = 1'b1;
end
OR: begin
OSEL = 2'b10;
SHIFT_LA = 1'b0;
SHIFT_LR = 1'b0;
LOGICAL_OP = 1'b0;
end
default: begin
OSEL = 2'b11;
SHIFT_LA = 1'b0;
SHIFT_LR = 1'b0;
LOGICAL_OP = 1'b0;
end
endcase
end
endmodule
|
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
`default_nettype none
module zap_shifter_shift
#(
parameter SHIFT_OPS = 5
)
(
// Source value.
input wire [31:0] i_source,
// Shift amount.
input wire [7:0] i_amount,
// Carry in.
input wire i_carry,
// Shift type.
input wire [$clog2(SHIFT_OPS)-1:0] i_shift_type,
// Output result and output carry.
output reg [31:0] o_result,
output reg o_carry,
output reg o_sat
);
`include "zap_defines.vh"
`include "zap_localparams.vh"
`include "zap_functions.vh"
///////////////////////////////////////////////////////////////////////////////
always @*
begin:blk1
reg signed [32:0] res, res1;
res = 0;
res1 = 0;
// Prevent latch inference.
o_result = i_source;
o_carry = 0;
o_sat = 0;
case ( i_shift_type )
// Logical shift left, logical shift right and
// arithmetic shift right.
LSL: {o_carry, o_result} = {i_carry, i_source} << i_amount;
LSR: {o_result, o_carry} = {i_source, i_carry} >> i_amount;
ASR:
begin
res = {i_source, i_carry};
res1 = $signed(res) >>> i_amount;
{o_result, o_carry} = res1;
end
ROR: // Rotate right.
begin
o_result = ( i_source >> i_amount[4:0] ) |
( i_source << (32 - i_amount[4:0] ) );
o_carry = ( i_amount[7:0] == 0) ?
i_carry : ( (i_amount[4:0] == 0) ?
i_source[31] : o_result[31] );
end
RORI, ROR_1:
begin
// ROR #n (ROR_1)
o_result = ( i_source >> i_amount[4:0] ) |
(i_source << (32 - i_amount[4:0] ) );
o_carry = i_amount ? o_result[31] : i_carry;
end
// ROR #0 becomes this.
RRC: {o_result, o_carry} = {i_carry, i_source};
// LSL_SAT. Always #1 in length.
LSL_SAT:
begin
o_result = i_source << 1;
if ( o_result[31] != i_source[31] )
o_sat = 1'd1;
if ( o_sat == 1'd1 )
begin
if ( i_source[31] == 1'd0 )
o_result = {1'd0, {31{1'd1}}}; // Max positive.
else
o_result = {1'd1, {31{1'd0}}}; // Max negative.
end
end
default: // For lint.
begin
end
endcase
end
///////////////////////////////////////////////////////////////////////////////
endmodule // zap_shift_shifter.v
`default_nettype wire
// ----------------------------------------------------------------------------
// EOF
// ----------------------------------------------------------------------------
|
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module processing_unit
(
// Closk & reset
input wire CLK,
input wire RST,
// Data input
input wire I_STB,
input wire [31:0] I_DAT,
// Data output
output wire O_STB,
output wire [31:0] O_DAT
);
// ============================================================================
wire [15:0] i_dat_a = I_DAT[15: 0];
wire [15:0] i_dat_b = I_DAT[31:16];
reg o_stb;
reg [31:0] o_dat;
always @(posedge CLK)
o_dat <= i_dat_a * i_dat_b;
always @(posedge CLK or posedge RST)
if (RST) o_stb <= 1'd0;
else o_stb <= I_STB;
assign O_STB = o_stb;
assign O_DAT = o_dat;
// ============================================================================
endmodule
|
/**
* bsg_fpu_add_sub.v
*
* @author tommy
*
* parameterized floating-point adder/subtractor.
*
*/
`include "bsg_defines.v"
`include "bsg_fpu_defines.vh"
module bsg_fpu_add_sub
#(parameter `BSG_INV_PARAM(e_p) // exponent width
, parameter `BSG_INV_PARAM(m_p) // mantissa width
)
(
input clk_i
, input reset_i
, input en_i // enable
, input v_i
, input [e_p+m_p:0] a_i
, input [e_p+m_p:0] b_i
, input sub_i
, output logic ready_o
, output logic v_o
, output logic [e_p+m_p:0] z_o
, output logic unimplemented_o
, output logic invalid_o
, output logic overflow_o
, output logic underflow_o
, input yumi_i // when yumi_i is high, en_i also has to be high
);
// pipeline states/signals
logic v_1_r, v_2_r, v_3_r;
logic stall;
assign stall = v_3_r & ~yumi_i;
assign v_o = v_3_r;
assign ready_o = ~stall & en_i;
// preprocessors
logic a_zero, a_nan, a_sig_nan, a_infty, exp_a_zero, a_denormal;
logic b_zero, b_nan, b_sig_nan, b_infty, exp_b_zero, b_denormal;
logic sign_a, sign_b;
logic [e_p-1:0] exp_a, exp_b;
logic [m_p-1:0] man_a, man_b;
bsg_fpu_preprocess #(
.e_p(e_p)
,.m_p(m_p)
) a_preprocess (
.a_i(a_i)
,.zero_o(a_zero)
,.nan_o(a_nan)
,.sig_nan_o(a_sig_nan)
,.infty_o(a_infty)
,.exp_zero_o(exp_a_zero)
,.man_zero_o()
,.denormal_o(a_denormal)
,.sign_o(sign_a)
,.exp_o(exp_a)
,.man_o(man_a)
);
bsg_fpu_preprocess #(
.e_p(e_p)
,.m_p(m_p)
) b_preprocess (
.a_i(b_i)
,.zero_o(b_zero)
,.nan_o(b_nan)
,.sig_nan_o(b_sig_nan)
,.infty_o(b_infty)
,.exp_zero_o(exp_b_zero)
,.man_zero_o()
,.denormal_o(b_denormal)
,.sign_o(sign_b)
,.exp_o(exp_b)
,.man_o(man_b)
);
// process exponents
logic exp_a_less;
logic [e_p-1:0] larger_exp;
(* keep = "true" *) logic [e_p-1:0] exp_diff;
bsg_less_than #(
.width_p(e_p)
) lt_exp (
.a_i(exp_a)
,.b_i(exp_b)
,.o(exp_a_less)
);
assign larger_exp = (exp_a_less ? exp_b : exp_a) + 1'b1;
// The following KEEP attribute prevents the following warning in the Xilinx
// toolchain. It may stop the tool from inferring a timing loop in the FPU:
// [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is
// shared. To prevent sharing consider applying a KEEP on the output of the
// operator [<path>/bsg_fpu_add_sub.v:104]. (Xilinx Vivado 2018.2)
(* keep = "true" *) logic [e_p-1:0] diff_ab, diff_ba;
assign diff_ab = exp_a - exp_b;
assign diff_ba = exp_b - exp_a;
assign exp_diff = exp_a_less ? diff_ba : diff_ab;
// hidden bit of mantissa
// filtered out denormalized input
logic [m_p:0] man_a_norm, man_b_norm;
assign man_a_norm = {1'b1, man_a};
assign man_b_norm = {1'b1, man_b};
// which mantissa is the one of larger exp?
logic [m_p:0] larger_exp_man, smaller_exp_man;
assign larger_exp_man = exp_a_less
? man_b_norm
: man_a_norm;
assign smaller_exp_man = exp_a_less
? man_a_norm
: man_b_norm;
// determine sticky bit
logic sticky;
bsg_fpu_sticky #(
.width_p(m_p+3)
) sticky0 (
.i({smaller_exp_man[m_p:0], 2'b0})
,.shamt_i(exp_diff[`BSG_WIDTH(m_p+3)-1:0])
,.sticky_o(sticky)
);
// determine final sign
logic final_sign;
logic mag_a_less;
bsg_less_than #(
.width_p(e_p+m_p)
) lt_mag (
.a_i(a_i[e_p+m_p-1:0])
,.b_i(b_i[e_p+m_p-1:0])
,.o(mag_a_less)
);
assign final_sign = (sign_a & ~mag_a_less)
| (~sign_b & mag_a_less & sub_i)
| (sign_b & mag_a_less & ~sub_i);
// add or sub mantissa?
logic do_sub;
assign do_sub = sub_i ^ sign_a ^ sign_b;
logic [m_p+3:0] larger_exp_man_padded;
assign larger_exp_man_padded = {larger_exp_man, 3'b0};
logic [m_p+3:0] smaller_exp_man_shifted;
assign smaller_exp_man_shifted = {
({smaller_exp_man, 2'b0} >> exp_diff),
sticky
};
/////////// first pipeline stage /////////////////
logic final_sign_1_r;
logic do_sub_1_r;
logic [e_p-1:0] larger_exp_1_r;
logic [m_p+3:0] smaller_exp_man_shifted_1_r;
logic [m_p+3:0] larger_exp_man_padded_1_r;
logic a_sig_nan_1_r, b_sig_nan_1_r;
logic a_nan_1_r, b_nan_1_r;
logic a_infty_1_r, b_infty_1_r;
logic a_denormal_1_r, b_denormal_1_r;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
v_1_r <= 1'b0;
end
else begin
if (~stall & en_i) begin
v_1_r <= v_i;
if (v_i) begin
final_sign_1_r <= final_sign;
do_sub_1_r <= do_sub;
larger_exp_1_r <= larger_exp;
smaller_exp_man_shifted_1_r <= smaller_exp_man_shifted;
larger_exp_man_padded_1_r <= larger_exp_man_padded;
a_sig_nan_1_r <= a_sig_nan;
b_sig_nan_1_r <= b_sig_nan;
a_nan_1_r <= a_nan;
b_nan_1_r <= b_nan;
a_infty_1_r <= a_infty;
b_infty_1_r <= b_infty;
a_denormal_1_r <= a_denormal;
b_denormal_1_r <= b_denormal;
end
end
end
end
// which mantissa has smaller magnitude?
logic larger_exp_man_less;
bsg_less_than #(
.width_p(m_p+4)
) lt_man_norm (
.a_i(larger_exp_man_padded_1_r)
,.b_i(smaller_exp_man_shifted_1_r)
,.o(larger_exp_man_less)
);
logic [m_p+3:0] larger_mag_man, smaller_mag_man;
assign larger_mag_man = larger_exp_man_less
? smaller_exp_man_shifted_1_r
: larger_exp_man_padded_1_r;
assign smaller_mag_man = larger_exp_man_less
? larger_exp_man_padded_1_r
: smaller_exp_man_shifted_1_r;
// add or sub two mantissas
logic [m_p+4:0] adder_output;
assign adder_output = {1'b0, larger_mag_man}
+ {do_sub_1_r, ({(m_p+4){do_sub_1_r}} ^ smaller_mag_man)}
+ do_sub_1_r;
/////////// second pipeline stage /////////////////
logic [e_p-1:0] larger_exp_2_r;
logic [m_p+4:0] adder_output_2_r;
logic final_sign_2_r;
logic a_sig_nan_2_r, b_sig_nan_2_r;
logic a_nan_2_r, b_nan_2_r;
logic a_infty_2_r, b_infty_2_r;
logic do_sub_2_r;
logic a_denormal_2_r, b_denormal_2_r;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
v_2_r <= 1'b0;
end
else begin
if (~stall & en_i) begin
v_2_r <= v_1_r;
if (v_1_r) begin
larger_exp_2_r <= larger_exp_1_r;
adder_output_2_r <= adder_output;
final_sign_2_r <= final_sign_1_r;
do_sub_2_r <= do_sub_1_r;
a_sig_nan_2_r <= a_sig_nan_1_r;
b_sig_nan_2_r <= b_sig_nan_1_r;
a_nan_2_r <= a_nan_1_r;
b_nan_2_r <= b_nan_1_r;
a_infty_2_r <= a_infty_1_r;
b_infty_2_r <= b_infty_1_r;
a_denormal_2_r <= a_denormal_1_r;
b_denormal_2_r <= b_denormal_1_r;
end
end
end
end
// count leading zero
logic [`BSG_SAFE_CLOG2(m_p+5)-1:0] num_zero;
logic reduce_o;
logic all_zero;
bsg_fpu_clz #(
.width_p(m_p+5)
) clz (
.i(adder_output_2_r)
,.num_zero_o(num_zero)
);
bsg_reduce #(
.width_p(m_p+5)
,.or_p(1)
) reduce0 (
.i(adder_output_2_r)
,.o(reduce_o)
);
assign all_zero = ~reduce_o;
// shift adder output
logic [m_p+4:0] shifted_adder_output;
assign shifted_adder_output = all_zero
? (m_p+5)'(1'b0)
: (adder_output_2_r << num_zero); // might not need mux here.
// subtract from the larger exp by the amount the mantissa was shifted (number of leading zeros).
logic [e_p-1:0] adjusted_exp;
logic adjusted_exp_cout;
assign {adjusted_exp_cout, adjusted_exp} = larger_exp_2_r - num_zero;
// pre_roundup
logic [e_p+m_p-1:0] pre_roundup;
assign pre_roundup = {adjusted_exp, shifted_adder_output[4+:m_p]};
// round up condition
logic round_up;
assign round_up = shifted_adder_output[3]
& ((|shifted_adder_output[2:0]) | shifted_adder_output[4]);
/////////// third pipeline stage /////////////////
logic [e_p+m_p-1:0] pre_roundup_3_r;
logic round_up_3_r;
logic all_zero_3_r;
logic a_sig_nan_3_r, b_sig_nan_3_r;
logic a_nan_3_r, b_nan_3_r;
logic a_infty_3_r, b_infty_3_r;
logic do_sub_3_r;
logic a_denormal_3_r, b_denormal_3_r;
logic adjusted_exp_cout_3_r;
logic final_sign_3_r;
logic [e_p+m_p-1:0] pre_roundup_3_n;
logic round_up_3_n;
logic all_zero_3_n;
logic a_sig_nan_3_n, b_sig_nan_3_n;
logic a_nan_3_n, b_nan_3_n;
logic a_infty_3_n, b_infty_3_n;
logic do_sub_3_n;
logic a_denormal_3_n, b_denormal_3_n;
logic adjusted_exp_cout_3_n;
logic final_sign_3_n;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
v_3_r <= 1'b0;
end
else begin
if (~stall & en_i) begin
v_3_r <= v_2_r;
if (v_2_r) begin
pre_roundup_3_r <= pre_roundup;
round_up_3_r <= round_up;
all_zero_3_r <= all_zero;
a_sig_nan_3_r <= a_sig_nan_2_r;
b_sig_nan_3_r <= b_sig_nan_2_r;
a_nan_3_r <= a_nan_2_r;
b_nan_3_r <= b_nan_2_r;
a_infty_3_r <= a_infty_2_r;
b_infty_3_r <= b_infty_2_r;
do_sub_3_r <= do_sub_2_r;
a_denormal_3_r <= a_denormal_2_r;
b_denormal_3_r <= b_denormal_2_r;
adjusted_exp_cout_3_r <= adjusted_exp_cout;
final_sign_3_r <= final_sign_2_r;
end
end
end
end
// carry going into exp when rounding up
// (important for distinguishing between overflow and underflow)
logic carry_into_exp;
assign carry_into_exp = &{round_up_3_r, pre_roundup_3_r[m_p-1:0]};
// round up for the final result
logic [e_p+m_p-1:0] rounded;
assign rounded = pre_roundup_3_r + round_up_3_r;
// final output stage
logic sgn;
always_comb begin
sgn = final_sign_3_r;
if (a_sig_nan_3_r | b_sig_nan_3_r) begin
unimplemented_o = 1'b0;
invalid_o = 1'b1;
overflow_o = 1'b0;
underflow_o = 1'b0;
z_o = `BSG_FPU_SIGNAN(e_p,m_p);
end
else if (a_nan_3_r | b_nan_3_r) begin
unimplemented_o = 1'b0;
invalid_o = 1'b0;
overflow_o = 1'b0;
underflow_o = 1'b0;
z_o = `BSG_FPU_QUIETNAN(e_p,m_p);
end
else if (a_infty_3_r & b_infty_3_r) begin
unimplemented_o = 1'b0;
invalid_o = do_sub_3_r;
overflow_o = 1'b0;
underflow_o = 1'b0;
z_o = do_sub_3_r
? `BSG_FPU_QUIETNAN(e_p,m_p)
: `BSG_FPU_INFTY(sgn,e_p,m_p);
end
else if (a_infty_3_r & ~b_infty_3_r) begin
unimplemented_o = 1'b0;
invalid_o = 1'b0;
overflow_o = 1'b0;
underflow_o = 1'b0;
z_o = `BSG_FPU_INFTY(sgn,e_p,m_p);
end
else if (~a_infty_3_r & b_infty_3_r) begin
unimplemented_o = 1'b0;
invalid_o = 1'b0;
overflow_o = 1'b0;
underflow_o = 1'b0;
z_o = `BSG_FPU_INFTY(sgn,e_p,m_p);
end
else if (a_denormal_3_r | b_denormal_3_r) begin
unimplemented_o = 1'b1;
invalid_o = 1'b0;
overflow_o = 1'b0;
underflow_o = 1'b0;
z_o =`BSG_FPU_QUIETNAN(e_p,m_p);
end
else if(all_zero_3_r) begin
unimplemented_o = 1'b0;
invalid_o = 1'b0;
overflow_o = 1'b0;
underflow_o = 1'b0;
z_o = `BSG_FPU_ZERO(sgn,e_p,m_p);
end
else if (adjusted_exp_cout_3_r) begin
unimplemented_o = 1'b0;
invalid_o = 1'b0;
overflow_o = 1'b0;
underflow_o = 1'b1;
z_o = `BSG_FPU_ZERO(sgn,e_p,m_p);
end
else begin
if (pre_roundup_3_r[m_p+:e_p] == {e_p{1'b1}} & (pre_roundup_3_r[m_p] | carry_into_exp)) begin
unimplemented_o = 1'b0;
invalid_o = 1'b0;
overflow_o = 1'b1;
underflow_o = 1'b0;
z_o =`BSG_FPU_INFTY(sgn,e_p,m_p);
end
else if (pre_roundup_3_r[m_p+:e_p] == {e_p{1'b0}} & ~carry_into_exp) begin
unimplemented_o = 1'b0;
invalid_o = 1'b0;
overflow_o = 1'b0;
underflow_o = 1'b1;
z_o = `BSG_FPU_ZERO(sgn,e_p,m_p);
end
else begin
unimplemented_o = 1'b0;
invalid_o = 1'b0;
overflow_o = 1'b0;
underflow_o = 1'b0;
z_o = {sgn, rounded}; // happy case
end
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_fpu_add_sub)
|
//
// Copyright (c) 2014 Jan Adelsbach <[email protected]>.
// All Rights Reserved.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module nova_io_pio_snooper(pclk, prst, bs_stb, bs_we, bs_adr, bs_din, bs_dout);
input pclk;
input prst;
input bs_stb;
input bs_we;
input [0:7] bs_adr;
input [0:15] bs_din;
output [0:15] bs_dout;
always @(posedge pclk) begin
if(bs_stb) begin
$display("%m Device %o Strobe! %h %b %b",
bs_adr[0:5], bs_din, bs_adr[6:7], bs_we);
if(bs_we) begin
case(bs_adr[6:7])
2'b00:
begin
case(bs_din[14:15])
2'b00:
$display("%m Spurious Update");
2'b01:
$display("%m Start");
2'b10:
$display("%m Clear");
2'b11:
$display("%m Pulse");
endcase // case (bs_din[0:1])
end
2'b01:
$display("%m DOA %h", bs_din);
2'b10:
$display("%m DOB %h", bs_din);
2'b11:
$display("%m DOC %h", bs_din);
endcase // case (bs_adr[6:7])
end // if (bs_we)
else begin
case(bs_adr[6:7])
2'b00:
$display("%m Flag Read");
2'b01:
$display("%m DIA");
2'b10:
$display("%m DIB");
2'b11:
$display("%m DIC");
endcase // case (bs_adr[6:7])
end // else: !if(bs_we)
end
end
endmodule // nova_io_pio_snooper
|
module VGA1Interface(clock,reset,framebuffer,vga_hsync,vga_vsync,vga_r,vga_g,vga_b);
input wire clock;
input wire reset;
input wire [63:0] framebuffer;
output wire vga_hsync;
output wire vga_vsync;
output wire vga_r;
output wire vga_g;
output wire vga_b;
reg [9:0] CounterX;
reg [8:0] CounterY;
wire value;
reg clock2 = 0;
always @ (posedge clock) begin
if (reset) begin
clock2 = 0;
end
else begin
clock2 = ~clock2;
end
end
reg vga_HS;
reg vga_VS;
wire inDisplayArea = CounterX < 640 && CounterY < 480;
wire CounterXmaxed = (CounterX==767);
always @ (posedge clock2) begin
if(CounterXmaxed) begin
CounterX <= 0;
end
else begin
CounterX <= CounterX + 1;
end
end
always @ (posedge clock2) begin
if(CounterXmaxed) begin
CounterY <= CounterY + 1;
end
end
always @ (posedge clock2) begin
vga_HS <= (CounterX[9:4]==0);
vga_VS <= (CounterY==0);
end
assign vga_hsync = ~vga_HS;
assign vga_vsync = ~vga_VS;
reg [2:0] ix;
reg [2:0] iy;
always @ (posedge clock2) begin
if (CounterX < 80) begin
ix = 0;
end
else if (CounterX < 160) begin
ix = 1;
end
else if (CounterX < 240) begin
ix = 2;
end
else if (CounterX < 320) begin
ix = 3;
end
else if (CounterX < 400) begin
ix = 4;
end
else if (CounterX < 480) begin
ix = 5;
end
else if (CounterX < 560) begin
ix = 6;
end
else if (CounterX < 640) begin
ix = 7;
end
end // always @ (posedge clock2)
always @ (posedge clock2) begin
if (CounterY < 60) begin
iy = 0;
end
else if (CounterY < 120) begin
iy = 1;
end
else if (CounterY < 180) begin
iy = 2;
end
else if (CounterY < 240) begin
iy = 3;
end
else if (CounterY < 300) begin
iy = 4;
end
else if (CounterY < 360) begin
iy = 5;
end
else if (CounterY < 420) begin
iy = 6;
end
else if (CounterY < 480) begin
iy = 7;
end
end // always @ (posedge clock2)
assign value = framebuffer[{iy,ix}];
assign vga_r = value & inDisplayArea;
assign vga_g = value & inDisplayArea;
assign vga_b = value & inDisplayArea;
endmodule // VGA1Interface
|
// Simple test of the SDRAM interface.
module SDRAM_test(
input wire clock,
input wire reset_n,
output reg [28:0] address,
output wire [7:0] burstcount,
input wire waitrequest,
input wire [63:0] readdata,
input wire readdatavalid,
output reg read,
output reg [63:0] writedata,
output wire [7:0] byteenable,
output reg write,
output wire [31:0] debug_value0,
output wire [31:0] debug_value1
);
// State machine.
localparam STATE_INIT = 4'h0;
localparam STATE_WRITE_START = 4'h1;
localparam STATE_WRITE_WAIT = 4'h2;
localparam STATE_READ_START = 4'h3;
localparam STATE_READ_WAIT = 4'h4;
localparam STATE_DONE = 4'h5;
reg [3:0] state;
// Registers and assignments.
assign burstcount = 8'h01;
assign byteenable = 8'hFF;
reg [63:0] data;
// 1G minus 128M, in 64-bit units:
localparam TEST_ADDRESS = 29'h0700_0000;
// Debug output.
assign debug_value0 = { 3'b0, waitrequest, 3'b0, readdatavalid, 3'b0, read, 3'b0, write, 12'b0, state };
assign debug_value1 = data[47:16];
always @(posedge clock or negedge reset_n) begin
if (!reset_n) begin
state <= STATE_INIT;
address <= 29'h0;
read <= 1'b0;
writedata <= 64'h0;
write <= 1'b0;
end else begin
case (state)
STATE_INIT: begin
// Dummy state to start.
state <= STATE_WRITE_START;
data <= 64'h2357_1113_1719_2329;
end
STATE_WRITE_START: begin
// Initiate a write.
address <= TEST_ADDRESS;
writedata <= 64'hDEAD_BEEF_CAFE_BABE;
write <= 1;
state <= STATE_WRITE_WAIT;
end
STATE_WRITE_WAIT: begin
// Wait until we're not requested to wait.
if (!waitrequest) begin
address <= 29'h0;
writedata <= 64'h0;
write <= 1'b0;
state <= STATE_READ_START;
end
end
STATE_READ_START: begin
// Initiate a read.
address <= TEST_ADDRESS;
read <= 1'b1;
state <= STATE_READ_WAIT;
end
STATE_READ_WAIT: begin
// When no longer told to wait, deassert the request lines.
if (!waitrequest) begin
address <= 29'h0;
read <= 1'b0;
end
// If we have data, grab it and we're done.
if (readdatavalid) begin
data <= readdata;
state <= STATE_DONE;
end
end
STATE_DONE: begin
// Nothing, stay here.
end
default: begin
// Bug. Just restart.
state <= STATE_INIT;
end
endcase
end
end
endmodule
|
//faux_hd_command_layer.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
module faux_hd_command_layer (
input rst, //reset
input clk,
output command_layer_ready,
output command_layer_busy,
output hd_read_from_host,
output [31:0] hd_data_from_host,
output hd_write_to_host,
input [31:0] hd_data_to_host,
input transport_layer_ready,
output reg send_reg_stb,
output reg send_dma_act_stb,
output reg send_data_stb,
output reg send_pio_stb,
output reg send_dev_bits_stb,
input remote_abort,
input xmit_error,
input read_crc_fail,
input h2d_reg_stb,
input h2d_data_stb,
input pio_request,
output reg [15:0] pio_transfer_count,
output reg pio_direction,
output reg [7:0] pio_e_status,
//FIS Structure
input [7:0] h2d_command,
input [15:0] h2d_features,
input h2d_cmd_bit,
input [3:0] h2d_port_mult,
input [7:0] h2d_control,
input [7:0] h2d_device,
input [47:0] h2d_lba,
input [15:0] h2d_sector_count,
output reg d2h_interrupt,
output reg d2h_notification,
output reg [7:0] d2h_status,
output reg [7:0] d2h_error,
output reg [3:0] d2h_port_mult,
output reg [7:0] d2h_device,
output reg [47:0] d2h_lba,
output reg [15:0] d2h_sector_count,
//command layer data interface
input cl_if_strobe,
output [31:0] cl_if_data,
output cl_if_ready,
input cl_if_activate,
output [23:0] cl_if_size,
input cl_of_strobe,
input [31:0] cl_of_data,
output [1:0] cl_of_ready,
input [1:0] cl_of_activate,
output [23:0] cl_of_size,
output [3:0] cl_state
);
//Parameters
parameter SLEEP_START = 4'h0;
parameter SEND_DIAGNOSTICS = 4'h1;
parameter IDLE = 4'h2;
parameter DMA_READY = 4'h3;
parameter READ_DATA = 4'h4;
parameter SEND_DATA = 4'h5;
parameter SEND_STATUS = 4'h6;
parameter TEST_FOR_END = 4'h7;
//Registers/Wires
reg [3:0] state = SLEEP_START;
wire idle;
reg [8:0] byte_count = 0;
reg [15:0] sector_count = 0;
reg [15:0] sector_size = 16'h0000;
reg [15:0] sleep_count = 0;
reg [15:0] sleep_size = 1000;
wire soft_reset;
//Asynchronous Logic
assign idle = (state == IDLE);
assign command_layer_busy = !idle;
assign command_layer_ready = idle;
//Short circuit the ping pong fifos
assign hd_read_from_host = cl_of_strobe;
assign hd_data_from_host = cl_of_data;
assign cl_of_ready = 1;
assign cl_of_size = 2048;
assign hd_write_to_host = cl_if_strobe;
assign cl_if_data = hd_data_to_host;
assign cl_if_ready = 1;
assign cl_if_size = 24'h0100;
assign soft_reset = h2d_control[`CONTROL_SRST_BIT];
assign cl_state = state;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= SLEEP_START;
send_reg_stb <= 0;
send_dma_act_stb <= 0;
send_data_stb <= 0;
send_pio_stb <= 0;
send_dev_bits_stb <= 0;
sector_count <= 0;
sector_size <= 1000;
sleep_count <= 0;
sleep_size <= 1000;
pio_transfer_count <= 0;
pio_direction <= 0;
pio_e_status <= 0;
d2h_interrupt <= 0;
d2h_notification <= 0;
d2h_status <= 8'h50;
d2h_error <= 1;
d2h_port_mult <= 0;
d2h_lba <= 1;
d2h_sector_count <= 1;
d2h_device <= 0;
byte_count <= 0;
end
else begin
//Strobe Lines
send_reg_stb <= 0;
send_dma_act_stb <= 0;
send_data_stb <= 0;
send_pio_stb <= 0;
send_dev_bits_stb <= 0;
if (soft_reset) begin
state <= SLEEP_START;
sleep_count <= 0;
sleep_size <= 1000;
end
case (state)
SLEEP_START: begin
if (sleep_count < sleep_size) begin
sleep_count <= sleep_count + 1;
end
else begin
state <= SEND_DIAGNOSTICS;
end
end
SEND_DIAGNOSTICS: begin
send_reg_stb <= 1;
state <= IDLE;
end
IDLE: begin
if (h2d_reg_stb) begin
if (h2d_cmd_bit) begin
d2h_lba <= h2d_lba;
d2h_sector_count <= h2d_sector_count;
sector_size <= h2d_sector_count;
case (h2d_command)
`COMMAND_DMA_READ_EX: begin
send_data_stb <= 1;
sector_count <= 0;
sector_size <= h2d_sector_count;
state <= SEND_DATA;
end
`COMMAND_DMA_WRITE_EX: begin
send_dma_act_stb <= 1;
sector_count <= 0;
sector_size <= h2d_sector_count;
state <= DMA_READY;
end
default: begin
//unrecognized command
$display ("fcl: Unrecognized command from host");
end
endcase
end
end
end
DMA_READY: begin
if (transport_layer_ready) begin
send_dma_act_stb <= 1;
byte_count <= 0;
state <= READ_DATA;
end
end
READ_DATA: begin
if (cl_of_activate && cl_of_strobe) begin
byte_count <= byte_count + 4;
end
if(byte_count == 508) begin
sector_count <= sector_count + 1;
end
if (h2d_data_stb) begin
if (sector_count < sector_size) begin
state <= DMA_READY;
end
else begin
state <= SEND_STATUS;
end
end
end
SEND_DATA: begin
if (transport_layer_ready) begin
if (sector_count < sector_size) begin
sector_count <= sector_count + 1;
send_data_stb <= 1;
state <= TEST_FOR_END;
end
else begin
end
end
end
TEST_FOR_END: begin
if (sector_count < sector_size) begin
state <= SEND_DATA;
end
else begin
if (transport_layer_ready) begin
send_reg_stb <= 1;
//Send a done register
state <= IDLE;
end
end
end
SEND_STATUS: begin
if (transport_layer_ready) begin
send_reg_stb <= 1;
//Send a done register
state <= IDLE;
end
end
default: begin
$display ("fcl: Entered illegal state, restart");
state <= SLEEP_START;
sleep_count <= 0;
sleep_size <= 1000;
end
endcase
end
end
endmodule
|
/*!
* \file ram_subcell.v
* \brief RAM cell instance, uses feedback signal to perform read-modify-write operations
* \author Luca Maggiani
* \version 1.0
* \date Jan 2014
* \pre It needs ram_module instances
* \see ram_subcell
* \see ram_module
*/
module ram_subcell(
clk,
reset_n,
data_a,
data_b,
data_valid_in,
address_a_valid,
memory_clear,
enable_wire,
q_b,
q_a,
address_a,
address_b
);
parameter HISTOGRAM_WIDTH = 16;
parameter HISTMEM_WORD = 1024;
localparam HISTMEM_ADDR_WIDTH = $clog2(HISTMEM_WORD);
localparam READ_STATE = 2'b01;
localparam WRITE_STATE = 2'b10;
input clk, reset_n;
input [(HISTOGRAM_WIDTH-1):0] data_a, data_b;
input data_valid_in, memory_clear;
input address_a_valid;
input enable_wire;
output [(HISTOGRAM_WIDTH-1):0] q_a, q_b;
input [(HISTMEM_ADDR_WIDTH-1):0] address_a;
input [(HISTMEM_ADDR_WIDTH-1):0] address_b;
reg memory_clear_reg;
wire wren_a;
wire wren_b;
wire [(HISTOGRAM_WIDTH-1):0] ram_data_in;
reg [(HISTMEM_ADDR_WIDTH-1):0] address_a_reg;
reg [1:0] state, state_new;
/* ######################
#
# FSM subcell control
#
######################
*/
always@(posedge clk or negedge reset_n)
if (reset_n == 1'b0)
address_a_reg <= {HISTOGRAM_WIDTH{1'b0}};
else
if (address_a_valid)
address_a_reg <= address_a;
else
address_a_reg <= address_a_reg;
always@(posedge clk or negedge reset_n)
if (reset_n == 1'b0)
state <= READ_STATE;
else
state <= state_new;
always@(*)
case(state)
READ_STATE:
begin
if (data_valid_in)
state_new = WRITE_STATE;
else
state_new = READ_STATE;
end
WRITE_STATE:
begin
state_new = READ_STATE;
end
default:
state_new = READ_STATE;
endcase
altsyncram #(
.address_reg_b("CLOCK0"),
.clock_enable_input_a("NORMAL"),
.clock_enable_input_b("NORMAL"),
.clock_enable_output_a("NORMAL"),
.clock_enable_output_b("NORMAL"),
.indata_reg_b("CLOCK0"),
.intended_device_family("Cyclone IV E"),
.lpm_type("altsyncram"),
.numwords_a(HISTMEM_WORD),
.numwords_b(HISTMEM_WORD),
.operation_mode("BIDIR_DUAL_PORT"),
.outdata_aclr_a("NONE"),
.outdata_aclr_b("NONE"),
.outdata_reg_b("CLOCK0"),
.power_up_uninitialized("FALSE"),
.ram_block_type("M9K"),
.read_during_write_mode_mixed_ports("OLD_DATA"),
.widthad_a(HISTMEM_ADDR_WIDTH),
.widthad_b(HISTMEM_ADDR_WIDTH),
.width_a(HISTOGRAM_WIDTH),
.width_b(HISTOGRAM_WIDTH),
.width_byteena_a(1),
.width_byteena_b(1),
.wrcontrol_wraddress_reg_b("CLOCK0")
)
ram_module_inst (
.clock0 (clk),
.wren_a (wren_a),
.address_b (address_b),
.clocken0 (enable_wire),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a_reg),
.data_a (ram_data_in),
.q_a (q_a),
.q_b (q_b),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1)
);
assign wren_a = (state == WRITE_STATE)? 1'b1: 1'b0;
assign wren_b = memory_clear;
assign ram_data_in = data_a + q_a;
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_change (clock, reset, enable, start_event, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter num_cks = 1;
parameter action_on_new_start = `OVL_ACTION_ON_NEW_START_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input start_event;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_CHANGE";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SYNTHESIS
`else
// Sanity Checks
initial begin
if (~((action_on_new_start == `OVL_IGNORE_NEW_START) ||
(action_on_new_start == `OVL_RESET_ON_NEW_START) ||
(action_on_new_start == `OVL_ERROR_ON_NEW_START)))
begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal value set for parameter action_on_new_start");
end
end
`endif
`ifdef OVL_VERILOG
`include "./vlog95/assert_change_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_change_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_change_psl_logic.v"
`else
`endmodule // ovl_change
`endif
|
`ifndef _REGFILE
`define _REGFILE
`include "../misc/demux.v"
`include "../misc/mux.v"
`include "../reg-file/register.v"
module register_file(clk, out1, out2, readAdd1, readAdd2, write, writeAdd, writeR7, inR7, in, reset); // Modify to include R7 effects
output [15:0] out1, out2;
input [15:0] in, inR7;
input [2:0] readAdd1, readAdd2, writeAdd;
input write, clk, reset, writeR7;
wire [15:0] data0, data1, data2, data3, data4, data5, data6, data7;
wire [7:0] writeLinesInit, writeLines;
decode8 dem(writeAdd, writeLinesInit);
mux16x8 mux1(data0, data1, data2, data3, data4, data5, data6, data7, readAdd1, out1);
mux16x8 mux2(data0, data1, data2, data3, data4, data5, data6, data7, readAdd2, out2);
or a0(writeLines[0], write, ~writeLinesInit[0]);
or a1(writeLines[1], write, ~writeLinesInit[1]);
or a2(writeLines[2], write, ~writeLinesInit[2]);
or a3(writeLines[3], write, ~writeLinesInit[3]);
or a4(writeLines[4], write, ~writeLinesInit[4]);
or a5(writeLines[5], write, ~writeLinesInit[5]);
or a6(writeLines[6], write, ~writeLinesInit[6]);
register16 r0(clk, data0, in, writeLines[0], reset);
register16 r1(clk, data1, in, writeLines[1], reset);
register16 r2(clk, data2, in, writeLines[2], reset);
register16 r3(clk, data3, in, writeLines[3], reset);
register16 r4(clk, data4, in, writeLines[4], reset);
register16 r5(clk, data5, in, writeLines[5], reset);
register16 r6(clk, data6, in, writeLines[6], reset);
register16 r7(clk, data7, (writeR7==1'b1)?inR7:in, ~(writeLines[7] & (~write + ~writeR7)), reset);
endmodule
`endif
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Testbench of CONTROL module for HIGHT Crypto Core ////
//// ////
//// This file is part of the HIGHT Crypto Core project ////
//// http://github.com/OpenSoCPlus/hight_crypto_core ////
//// http://www.opencores.org/project,hight ////
//// ////
//// Description ////
//// __description__ ////
//// ////
//// Author(s): ////
//// - JoonSoo Ha, [email protected] ////
//// - Younjoo Kim, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module tb_CONTROL;
event do_finish;
//=====================================
//
// PARAMETERS
//
//=====================================
parameter HP_CLK = 5; // Half period of clock
//=====================================
//
// I/O PORTS
//
//=====================================
reg rstn ;
reg clk ;
reg i_mk_rdy ;
reg i_post_rdy ;
reg i_text_val ;
wire o_rdy ;
wire o_text_done ;
wire[2:0] o_xf_sel ;
wire o_rf_final ;
wire o_key_sel ;
wire[4:0] o_rnd_idx ;
wire o_wf_post_pre ;
//=====================================
//
// PORT MAPPING
//
//=====================================
CONTROL uut_CONTROL(
.rstn (rstn ) ,
.clk (clk ) ,
.i_mk_rdy (i_mk_rdy ) ,
.i_post_rdy (i_post_rdy ) ,
.i_text_val (i_text_val ) ,
.o_rdy (o_rdy ) ,
.o_text_done (o_text_done ) ,
.o_xf_sel (o_xf_sel ) ,
.o_rf_final (o_rf_final ) ,
.o_key_sel (o_key_sel ) ,
.o_rnd_idx (o_rnd_idx ) ,
.o_wf_post_pre (o_wf_post_pre)
);
//=====================================
//
// STIMULUS
//
//=====================================
// clock generation
initial begin
clk = 1'b0;
forever clk = #(HP_CLK) ~clk;
end
// reset generation
initial begin
rstn = 1'b1;
@(posedge clk);
@(negedge clk);
rstn = 1'b0;
repeat(2) @(negedge clk);
rstn = 1'b1;
end
// input generation
initial begin
$display("===== SIM START =====");
// insert your code
// initial input value
i_mk_rdy = 1'b1;
i_post_rdy = 1'b1;
i_text_val = 1'b0;
// reset time
@(negedge rstn);
@(posedge rstn);
@(negedge clk);
// Key Config Phase
@(negedge clk);
i_mk_rdy = 1'b0;
repeat(4) @(posedge clk);
@(negedge clk);
i_mk_rdy = 1'b1;
//// first ciphering ////
// insert 2 clock delay
@(posedge clk);
repeat(2) @(posedge clk);
// insert text
@(negedge clk);
i_text_val = 1'b1;
@(negedge clk);
i_text_val = 1'b0;
// wait text done
wait(o_text_done)
@(posedge clk);
// post rdy inactive
@(negedge clk);
i_post_rdy = 1'b0;
//// second ciphering ////
// insert text
@(negedge clk);
i_text_val = 1'b1;
@(negedge clk);
i_text_val = 1'b0;
// wait done state
wait(uut_CONTROL.r_pstate == uut_CONTROL.S_DONE)
@(posedge clk);
// insert 3clk delay
repeat(3) @(posedge clk);
// post rdy active
i_post_rdy = 1'b1;
repeat(10) @(posedge clk);
-> do_finish;
end
// state monitoring
reg[20*8:1] state;
always @(uut_CONTROL.r_pstate) begin
case(uut_CONTROL.r_pstate)
uut_CONTROL.S_IDLE : state <= "IDLE ";
uut_CONTROL.S_KEY_CONFIG : state <= "KEY_CONFIG";
uut_CONTROL.S_RDY : state <= "RDY ";
uut_CONTROL.S_WF1 : state <= "WF1 ";
uut_CONTROL.S_RF1 : state <= "RF1 ";
uut_CONTROL.S_RF2 : state <= "RF2 ";
uut_CONTROL.S_RF3 : state <= "RF3 ";
uut_CONTROL.S_RF4 : state <= "RF4 ";
uut_CONTROL.S_RF5 : state <= "RF5 ";
uut_CONTROL.S_RF6 : state <= "RF6 ";
uut_CONTROL.S_RF7 : state <= "RF7 ";
uut_CONTROL.S_RF8 : state <= "RF8 ";
uut_CONTROL.S_RF9 : state <= "RF9 ";
uut_CONTROL.S_RF10 : state <= "RF10 ";
uut_CONTROL.S_RF11 : state <= "RF11 ";
uut_CONTROL.S_RF12 : state <= "RF12 ";
uut_CONTROL.S_RF13 : state <= "RF13 ";
uut_CONTROL.S_RF14 : state <= "RF14 ";
uut_CONTROL.S_RF15 : state <= "RF15 ";
uut_CONTROL.S_RF16 : state <= "RF16 ";
uut_CONTROL.S_RF17 : state <= "RF17 ";
uut_CONTROL.S_RF18 : state <= "RF18 ";
uut_CONTROL.S_RF19 : state <= "RF19 ";
uut_CONTROL.S_RF20 : state <= "RF20 ";
uut_CONTROL.S_RF21 : state <= "RF21 ";
uut_CONTROL.S_RF22 : state <= "RF22 ";
uut_CONTROL.S_RF23 : state <= "RF23 ";
uut_CONTROL.S_RF24 : state <= "RF24 ";
uut_CONTROL.S_RF25 : state <= "RF25 ";
uut_CONTROL.S_RF26 : state <= "RF26 ";
uut_CONTROL.S_RF27 : state <= "RF27 ";
uut_CONTROL.S_RF28 : state <= "RF28 ";
uut_CONTROL.S_RF29 : state <= "RF29 ";
uut_CONTROL.S_RF30 : state <= "RF30 ";
uut_CONTROL.S_RF31 : state <= "RF31 ";
uut_CONTROL.S_RF32 : state <= "RF32 ";
uut_CONTROL.S_DONE : state <= "DONE ";
uut_CONTROL.S_ERROR : state <= "ERROR ";
endcase
end
// finish
initial begin
@do_finish
$finish;
end
// vcd dump
initial begin
$dumpfile("dump/sim_tb_CONTROL.vcd");
$dumpvars(0, tb_CONTROL);
end
endmodule
|
// MBT: This module has a broken interface because it uses bypass_i as a live input, which could use glitching
// MBT: This module should never be used in actual synthesized RTL; it must be hardened.
// For this reason, I am guarding it with an ifndef SYNTHESIS and we can fix it later.
`include "bsg_defines.v"
`ifndef SYNTHESIS
// This is an integrated clock cell using a negative latch and an AND gate
// This logic may be susceptible bug if en_i changes multiple times within a clk cyle
module bsg_clkgate_optional (input clk_i
,input en_i
,input bypass_i
,output gated_clock_o
);
//wire en_latch;
//assign en_latch = (reset_i) ? 1'b0 :
// (~clk_i) ? en_i : en_latch;
wire latched_en_lo;
bsg_dlatch #(.width_p(1), .i_know_this_is_a_bad_idea_p(1))
en_latch
( .clk_i ( ~clk_i )
, .data_i ( en_i )
, .data_o ( latched_en_lo )
);
assign gated_clock_o = (latched_en_lo|bypass_i) & clk_i;
endmodule
`endif
|
//////////////////////////////////////////////////////////////////////
//// ////
//// hostSlaveMuxBI.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbHostSlave_h.v"
module hostSlaveMuxBI (dataIn, dataOut, address, writeEn, strobe_i, busClk, usbClk,
hostMode, hostSlaveMuxSel, rstFromWire, rstSyncToBusClkOut, rstSyncToUsbClkOut);
input [7:0] dataIn;
input address;
input writeEn;
input strobe_i;
input busClk;
input usbClk;
output [7:0] dataOut;
input hostSlaveMuxSel;
output hostMode;
input rstFromWire;
output rstSyncToBusClkOut;
output rstSyncToUsbClkOut;
wire [7:0] dataIn;
wire address;
wire writeEn;
wire strobe_i;
wire busClk;
wire usbClk;
reg [7:0] dataOut;
wire hostSlaveMuxSel;
reg hostMode;
wire rstFromWire;
reg rstSyncToBusClkOut;
reg rstSyncToUsbClkOut;
//internal wire and regs
reg [5:0] rstShift;
reg rstFromBus;
reg rstSyncToUsbClkFirst;
//sync write demux
always @(posedge busClk)
begin
if (rstSyncToBusClkOut == 1'b1)
hostMode <= 1'b0;
else begin
if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG )
hostMode <= dataIn[0];
end
if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG && dataIn[1] == 1'b1 )
rstFromBus <= 1'b1;
else
rstFromBus <= 1'b0;
end
// async read mux
always @(address or hostMode)
begin
case (address)
`HOST_SLAVE_CONTROL_REG: dataOut <= {7'h0, hostMode};
`HOST_SLAVE_VERSION_REG: dataOut <= `USBHOSTSLAVE_VERSION_NUM;
endcase
end
// reset control
//generate 'rstSyncToBusClk'
//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz
always @(posedge busClk) begin
if (rstFromWire == 1'b1 || rstFromBus == 1'b1)
rstShift <= 6'b111111;
else
rstShift <= {1'b0, rstShift[5:1]};
end
always @(rstShift)
rstSyncToBusClkOut <= rstShift[0];
// double sync across clock domains to generate 'forceEmptySyncToWrClk'
always @(posedge usbClk) begin
rstSyncToUsbClkFirst <= rstSyncToBusClkOut;
rstSyncToUsbClkOut <= rstSyncToUsbClkFirst;
end
endmodule
|
`include "yf32_define.v"
`include "NF_2.1_defines.v"
`include "reg_defines_reference_router.v"
`include "registers.v"
module CAM_monitor_ipv4
(
input clk,
input statemac_clk,
input [3:0] four_bit_hash,
input [11:0] pcin,
input new_inst_signal,
input reset,
output packet_drop_signal,
input cam_we,
input [3:0] cam_wr_addr,
input [31:0] cam_din,
input proc_ack,
output out_ack_reset,
output cam_wr_ack,
input processor_reset_seq,
input packet_done
);
parameter LUT_DEPTH = `ROUTER_OP_LUT_DST_IP_FILTER_TABLE_DEPTH;
//parameter LUT_DEPTH_BITS = 4;
wire [11:0] address_a;
wire [3:0] four_bit_hash_out_one;
reg packet_drop_signal_reg;
reg pre_jump_instr2;
wire [31:0] dfa_ram_output;
reg [31:0] dfa_ram_output_reg;
reg [15:0] encoded_hash_output;
reg [15:0] encoded_hash_output_reg;
reg [15:0] masked_hash_ouput;
reg [13:0] base_address_reg;
reg [3:0] four_bit_hash_reg;
reg new_inst_signal_reg;
reg start_rom_read;
always@(posedge clk)
begin
if (reset) begin
four_bit_hash_reg <= 4'h0;
dfa_ram_output_reg <= 32'h0;
new_inst_signal_reg <= 1'b0;
encoded_hash_output_reg <= 16'h0;
end
else begin
four_bit_hash_reg <= four_bit_hash;
dfa_ram_output_reg <= dfa_ram_output;
new_inst_signal_reg <= new_inst_signal;
encoded_hash_output_reg <= encoded_hash_output;
end
end
always@(posedge clk)
begin
if (reset) begin
start_rom_read <= 1'b0;
end
else begin
if (new_inst_signal)
start_rom_read <= 1'b1;
end
end
reg pkt_done_sig_next,pkt_done_sig;
// Add Hash memory block
rom_shared_ipv4 rom(
.address_a(address_a),
.address_b(),
.rden_a(new_inst_signal),
.clock(clk),
.q_a(dfa_ram_output),
.q_b()
);
// Combinational circuit for new architecture
// Once the ouput of RAM is available
// 1. First do the decoder stage 4 to 16
// 2. Calculate the value of k
// 3. Get the base address along with step 2
// 4. Calculate the next address location
// Size of RAM output (2 bit(state bit) + 14 bit (next state) + 16 bit (input valid bit))
// This state machine generates encoded_hash_output & masked_hash_ouput
// encoded_hash_output is used to check whether the input hash is correct
// masked_hash_ouput is used to calculate k
always@(dfa_ram_output) begin // dfa_ram_output
if (reset) begin
encoded_hash_output = 16'h0;
masked_hash_ouput = 16'h0;
end
else begin
//four_bit_hash_reg = four_bit_hash;
//if (new_inst_signal_reg) begin
case (four_bit_hash_reg)
4'b0000: begin
encoded_hash_output = 16'h0001;
masked_hash_ouput = {15'b0,1'b0};
end
4'b0001: begin
encoded_hash_output = 16'h0002;
masked_hash_ouput = {15'b0,dfa_ram_output[0]};
end
4'b0010: begin
encoded_hash_output = 16'h0004;
masked_hash_ouput = {14'b0,dfa_ram_output[1:0]};
end
4'b0011: begin
encoded_hash_output = 16'h0008;
masked_hash_ouput = {13'b0,dfa_ram_output[2:0]};
end
4'b0100: begin
encoded_hash_output = 16'h0010;
masked_hash_ouput = {12'b0,dfa_ram_output[3:0]};
end
4'b0101: begin
encoded_hash_output = 16'h0020;
masked_hash_ouput = {11'b0,dfa_ram_output[4:0]};
end
4'b0110: begin
encoded_hash_output = 16'h0040;
masked_hash_ouput = {10'b0,dfa_ram_output[5:0]};
end
4'b0111: begin
encoded_hash_output = 16'h0080;
masked_hash_ouput = {9'b0,dfa_ram_output[6:0]};
end
4'b1000: begin
encoded_hash_output = 16'h0100;
masked_hash_ouput = {8'b0,dfa_ram_output[7:0]};
end
4'b1001: begin
encoded_hash_output = 16'h0200;
masked_hash_ouput = {7'b0,dfa_ram_output[8:0]};
end
4'b1010: begin
encoded_hash_output = 16'h0400;
masked_hash_ouput = {6'b0,dfa_ram_output[9:0]};
end
4'b1011: begin
encoded_hash_output = 16'h0800;
masked_hash_ouput = {5'b0,dfa_ram_output[10:0]};
end
4'b1100: begin
encoded_hash_output = 16'h1000;
masked_hash_ouput = {4'b0,dfa_ram_output[11:0]};
end
4'b1101: begin
encoded_hash_output = 16'h2000;
masked_hash_ouput = {3'b0,dfa_ram_output[12:0]};
end
4'b1110: begin
encoded_hash_output = 16'h4000;
masked_hash_ouput = {2'b0,dfa_ram_output[13:0]};
end
4'b1111: begin
encoded_hash_output = 16'h8000;
masked_hash_ouput = {1'b0,dfa_ram_output[14:0]};
end
//default: begin
//encoded_hash_output = 16'h0;
//masked_hash_ouput = 16'h0;
//end
endcase
//end
end
end
// This state machine generates the base address, used for calculating the next RAM address input.
//reg [13:0] base_address_reg;
reg [2:0] state_bit_reg;
always @(dfa_ram_output) begin //dfa_ram_output
if (reset) begin
base_address_reg = 14'h0;
state_bit_reg = 3'h1;
end
else begin
case(dfa_ram_output[31:28])
4'b0000: begin
base_address_reg = 14'h0;
state_bit_reg = 3'h0;
end
4'b0001: begin
base_address_reg = 14'h0;
state_bit_reg = 3'h1;
end
4'b0010: begin
base_address_reg = 14'h200;
state_bit_reg = 3'h2;
end
4'b0011: begin
base_address_reg = 14'h800;
state_bit_reg = 3'h3;
end
default: begin
base_address_reg = 14'h0;
end
endcase
end
end
// This state machine checks for valid input case
reg [15:0] valid_bit_and_value;
reg [15:0] test_valid_bit;
reg hash_valid;
reg drop_signal_reg;
always@(encoded_hash_output)begin //encoded_hash_output
if (reset) begin
valid_bit_and_value = 16'h0;
drop_signal_reg = 1'b0;
hash_valid = 1'b0;
test_valid_bit = 16'b0;
end
else begin
test_valid_bit = (encoded_hash_output|dfa_ram_output[15:0]);
valid_bit_and_value = (encoded_hash_output&dfa_ram_output[15:0]);
if(!valid_bit_and_value) begin // added new_inst_signal
hash_valid = 1'b0;
drop_signal_reg = 1'b1;
end
else begin
hash_valid = 1'b1;
drop_signal_reg = 1'b0;
end
end
end
reg addr_reset,addr_reset_next;
// This state machine generates k value
reg [3:0] k_reg;
always@(*) begin // masked_hash_ouput
if (reset | addr_reset | pkt_done_sig) begin
k_reg = 4'h0;
end
else begin
k_reg = masked_hash_ouput[0] + masked_hash_ouput[1] + masked_hash_ouput[2] + masked_hash_ouput[3] + masked_hash_ouput[4] + masked_hash_ouput[5] + masked_hash_ouput[6] + masked_hash_ouput[7] + masked_hash_ouput[8] + masked_hash_ouput[9] + masked_hash_ouput[10] + masked_hash_ouput[11] + masked_hash_ouput[12] + masked_hash_ouput[13] + masked_hash_ouput[14] + masked_hash_ouput[15];
end
end
// This calculates the next address location
reg [13:0] dfa_address_reg;
always@(*) begin
if(reset | addr_reset | pkt_done_sig) begin
dfa_address_reg = 14'h0;
end
else begin
dfa_address_reg = base_address_reg + dfa_ram_output[27:16]*state_bit_reg + k_reg;
end
end
reg out_drop_signal,out_drop_signal_next;
reg [2:0] drop_state,drop_state_next;
reg ack_reset,ack_reset_next;
always@(*)begin
drop_state_next = drop_state;
out_drop_signal_next = out_drop_signal;
ack_reset_next = ack_reset;
addr_reset_next = addr_reset;
case (drop_state)
3'b000: begin
if (drop_signal_reg)begin
out_drop_signal_next = 1'b1;
drop_state_next = 3'b001;
addr_reset_next = 1'b1;
ack_reset_next = 1'b1;
end
else begin
out_drop_signal_next = 1'b0;
addr_reset_next = 1'b0;
ack_reset_next = 1'b0;
end
end
3'b001: begin
out_drop_signal_next = 1'b0;
if (!processor_reset_seq)begin
ack_reset_next = 1'b1;
drop_state_next = 3'b010;
addr_reset_next = 1'b1;
end
else
drop_state_next = 3'b001;
end
3'b010: begin
out_drop_signal_next = 1'b0;
ack_reset_next = 1'b1;
drop_state_next = 3'b011;
addr_reset_next = 1'b1;
end
3'b011: begin
ack_reset_next = 1'b0;
if (new_inst_signal)begin
drop_state_next = 3'b100;
addr_reset_next = 1'b1;
end
else
drop_state_next = 3'b011;
end
3'b100: begin
addr_reset_next = 1'b0;
drop_state_next = 3'b101;
end
3'b101: begin
drop_state_next = 3'b000;
end
default:begin
drop_state_next = 3'b000;
out_drop_signal_next = 1'b0;
ack_reset_next = 1'b0;
addr_reset_next = 1'b0;
end
endcase
end
always@(posedge clk)
begin
if(reset) begin
drop_state <= 3'b000;
out_drop_signal <= 1'b0;
ack_reset <= 1'b0;
addr_reset <= 1'b0;
end
else begin
drop_state <= drop_state_next;
out_drop_signal <= out_drop_signal_next;
ack_reset <= ack_reset_next;
addr_reset <= addr_reset_next;
end
end
reg [1:0] pkt_done_state_next,pkt_done_state;
always@(*)begin
pkt_done_state_next = pkt_done_state;
pkt_done_sig_next = pkt_done_sig;
case(pkt_done_state)
2'b00: begin
if (packet_done)begin
pkt_done_sig_next = 1'b1;
pkt_done_state_next = 2'b01;
end
else begin
pkt_done_sig_next = 1'b0;
end
end
2'b01: begin
if(new_inst_signal) begin
pkt_done_sig_next = 1'b0;
pkt_done_state_next = 2'b00;
end
else
pkt_done_sig_next = 1'b1;
end
default: begin
pkt_done_sig_next = 1'b0;
pkt_done_state_next = 2'b00;
end
endcase
end
always@(posedge clk)
begin
if(reset) begin
pkt_done_state <= 2'b00;
pkt_done_sig <= 1'b0;
end
else begin
pkt_done_state <= pkt_done_state_next;
pkt_done_sig <= pkt_done_sig_next;
end
end
assign address_a = pkt_done_sig ? 14'h0 : dfa_address_reg;
assign packet_drop_signal = out_drop_signal;
assign out_ack_reset = ack_reset;
endmodule |
(** * Basics: Functional Programming in Coq *)
(* REMINDER:
#####################################################
### PLEASE DO NOT DISTRIBUTE SOLUTIONS PUBLICLY ###
#####################################################
(See the [Preface] for why.)
*)
(* ################################################################# *)
(** * Introduction *)
(** The functional programming style is founded on simple, everyday
mathematical intuition: If a procedure or method has no side
effects, then (ignoring efficiency) all we need to understand
about it is how it maps inputs to outputs -- that is, we can think
of it as just a concrete method for computing a mathematical
function. This is one sense of the word "functional" in
"functional programming." The direct connection between programs
and simple mathematical objects supports both formal correctness
proofs and sound informal reasoning about program behavior.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, included in
data structures, etc. The recognition that functions can be
treated as data gives rise to a host of useful and powerful
programming idioms.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to
construct and manipulate rich data structures, and sophisticated
_polymorphic type systems_ supporting abstraction and code reuse.
Coq offers all of these features.
The first half of this chapter introduces the most essential
elements of Coq's functional programming language, called
_Gallina_. The second half introduces some basic _tactics_ that
can be used to prove properties of Coq programs. *)
(* ################################################################# *)
(** * Enumerated Types *)
(** One notable aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers a powerful mechanism for defining new
data types from scratch, with all these familiar types as
instances.
Naturally, the Coq distribution comes preloaded with an extensive
standard library providing definitions of booleans, numbers, and
many common data structures like lists and hash tables. But there
is nothing magic or primitive about these library definitions. To
illustrate this, we will explicitly recapitulate all the
definitions we need in this course, rather than just getting them
implicitly from the library. *)
(* ================================================================= *)
(** ** Days of the Week *)
(** To see how this definition mechanism works, let's start with
a very simple example. The following declaration tells Coq that
we are defining a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second and following lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often figure out these types for
itself when they are not given explicitly -- i.e., it can do _type
inference_ -- but we'll generally include them to make reading
easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq. First, we can use the command [Compute] to evaluate a
compound expression involving [next_weekday]. *)
Compute (next_weekday friday).
(* ==> monday : day *)
Compute (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** (We show Coq's responses in comments, but, if you have a
computer handy, this would be an excellent moment to fire up the
Coq interpreter under your favorite IDE -- either CoqIde or Proof
General -- and try this for yourself. Load this file, [Basics.v],
from the book's Coq sources, find the above example, submit it to
Coq, and observe the result.)
Second, we can record what we _expect_ the result to be in the
form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. Having made the assertion, we can also ask Coq to verify
it, like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification."
Third, we can ask Coq to _extract_, from our [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to go from proved-correct algorithms written in Gallina to
efficient machine code. (Of course, we are trusting the
correctness of the OCaml/Haskell/Scheme compiler, and of Coq's
extraction facility itself, but this is still a big step forward
from the way most software is developed today.) Indeed, this is
one of the main uses for which Coq was developed. We'll come back
to this topic in later chapters. *)
(* ================================================================= *)
(** ** Homework Submission Guidelines *)
(** If you are using Software Foundations in a course, your instructor
may use automatic scripts to help grade your homework assignments.
In order for these scripts to work correctly (so that you get full
credit for your work!), please be careful to follow these rules:
- The grading scripts work by extracting marked regions of the
.v files that you submit. It is therefore important that you
do not alter the "markup" that delimits exercises: the
Exercise header, the name of the exercise, the "empty square
bracket" marker at the end, etc. Please leave this markup
exactly as you find it.
- Do not delete exercises. If you skip an exercise (e.g.,
because it is marked Optional, or because you can't solve it),
it is OK to leave a partial proof in your .v file, but in this
case please make sure it ends with [Admitted] (not, for
example [Abort]). *)
(* ================================================================= *)
(** ** Booleans *)
(** In a similar way, we can define the standard type [bool] of
booleans, with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans, together with a
multitude of useful functions and lemmas. (Take a look at
[Coq.Init.Datatypes] in the Coq library documentation if you're
interested.) Whenever possible, we'll name our own definitions
and theorems so that they exactly coincide with the ones in the
standard library.
Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two of these illustrate Coq's syntax for
multi-argument function definitions. The corresponding
multi-argument application syntax is illustrated by the following
"unit tests," which constitute a complete specification -- a truth
table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. simpl. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. simpl. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. simpl. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. simpl. reflexivity. Qed.
(** We can also introduce some familiar syntax for the boolean
operations we have just defined. The [Infix] command defines a new
symbolic notation for an existing definition. *)
Infix "&&" := andb.
Infix "||" := orb.
Example test_orb5: false || false || true = true.
Proof. simpl. reflexivity. Qed.
(** _A note on notation_: In [.v] files, we use square brackets
to delimit fragments of Coq code within comments; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font].
The command [Admitted] can be used as a placeholder for an
incomplete proof. We'll use it in exercises, to indicate the
parts that we're leaving for you -- i.e., your job is to replace
[Admitted]s with real proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Remove "[Admitted.]" and complete the definition of the following
function; then make sure that the [Example] assertions below can
each be verified by Coq. (Remove "[Admitted.]" and fill in each
proof, following the model of the [orb] tests above.) The function
should return [true] if either or both of its inputs are
[false]. *)
Definition nandb (b1:bool) (b2:bool) : bool
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example test_nandb1: (nandb true false) = true.
(* FILL IN HERE *) Admitted.
Example test_nandb2: (nandb false false) = true.
(* FILL IN HERE *) Admitted.
Example test_nandb3: (nandb false true) = true.
(* FILL IN HERE *) Admitted.
Example test_nandb4: (nandb true true) = false.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example test_andb31: (andb3 true true true) = true.
(* FILL IN HERE *) Admitted.
Example test_andb32: (andb3 false true true) = false.
(* FILL IN HERE *) Admitted.
Example test_andb33: (andb3 true false true) = false.
(* FILL IN HERE *) Admitted.
Example test_andb34: (andb3 true true false) = false.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Function Types *)
(** Every expression in Coq has a type, describing what sort of
thing it computes. The [Check] command asks Coq to print the type
of an expression. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ================================================================= *)
(** ** Modules *)
(** Coq provides a _module system_, to aid in organizing large
developments. In this course we won't need most of its features,
but one is useful: If we enclose a collection of declarations
between [Module X] and [End X] markers, then, in the remainder of
the file after the [End], these definitions are referred to by
names like [X.foo] instead of just [foo]. We will use this
feature to introduce the definition of the type [nat] in an inner
module so that it does not interfere with the one from the
standard library (which we want to use in the rest because it
comes with a tiny bit of convenient special notation). *)
Module NatPlayground.
(* ================================================================= *)
(** ** Numbers *)
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of _inductive rules_ describing its elements. For
example, we can define (a unary representation of) the natural
numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O],"
not the numeral "[0]").
- [S] can be put in front of a natural number to yield another
one -- if [n] is a natural number, then [S n] is too. *)
(** Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_ built from _constructors_
like [O], [S], [true], [false], [monday], etc. The definition of
[nat] says how expressions in the set [nat] can be built:
- [O] and [S] are constructors;
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat]. *)
(** The same rules apply for our definitions of [day] and
[bool]. (The annotations we used for their constructors are
analogous to the one for the [O] constructor, indicating that they
don't take any arguments.)
The above conditions are the precise force of the [Inductive]
declaration. They imply that the expression [O], the expression
[S O], the expression [S (S O)], the expression [S (S (S O))], and
so on all belong to the set [nat], while other expressions built
from data constructors, like [true], [andb true false], [S (S
false)], and [O (O (O S))] do not.
A critical point here is that what we've done so far is just to
define a _representation_ of numbers: a way of writing them down.
The names [O] and [S] are arbitrary, and at this point they have
no special meaning -- they are just two different marks that we
can use to write down numbers (together with a rule that says any
[nat] will be written as some string of [S] marks followed by an
[O]). If we like, we can write essentially the same definition
this way: *)
Inductive nat' : Type :=
| stop : nat'
| tick : nat' -> nat'.
(** The _interpretation_ of these marks comes from how we use them to
compute. *)
(** We can do this by writing functions that pattern match on
representations of natural numbers just as we did above with
booleans and days -- for example, here is the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End NatPlayground.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
(* ===> 4 : nat *)
Compute (minustwo 4).
(* ===> 2 : nat *)
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference between the
first one and the other two: functions like [pred] and [minustwo]
come with _computation rules_ -- e.g., the definition of [pred]
says that [pred 2] can be simplified to [1] -- while the
definition of [S] has no such behavior attached. Although it is
like a function in the sense that it can be applied to an
argument, it does not _do_ anything at all! It is just a way of
writing down numbers. (Think about standard arabic numerals: the
numeral [1] is not a computation; it's a piece of data. When we
write [111] to mean the number one hundred and eleven, we are
using [1], three times, to write down a concrete representation of
a number.)
For most function definitions over numbers, just pattern matching
is not enough: we also need recursion. For example, to check that
a number [n] is even, we may need to recursively check whether
[n-2] is even. To write such functions, we use the keyword
[Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: oddb 1 = true.
Proof. simpl. reflexivity. Qed.
Example test_oddb2: oddb 4 = false.
Proof. simpl. reflexivity. Qed.
(** (You will notice if you step through these proofs that
[simpl] actually has no effect on the goal -- all of the work is
done by [reflexivity]. We'll see more about why that is shortly.)
Naturally, we can also define multi-argument functions by
recursion. *)
Module NatPlayground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Compute (plus 3 2).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))]
by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))]
by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))]
by the second clause of the [match]
==> [S (S (S (S (S O))))]
by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. simpl. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a variable
name. *)
End NatPlayground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard mathematical factorial function:
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example test_factorial1: (factorial 3) = 6.
(* FILL IN HERE *) Admitted.
Example test_factorial2: (factorial 5) = (mult 10 12).
(* FILL IN HERE *) Admitted.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing _notations_ for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important for our purposes, but interested readers
can refer to the optional "More on Notation" section at the end of
this chapter.)
Note that these do not change the definitions we've already made:
they are simply instructions to the Coq parser to accept [x + y]
in place of [plus x y] and, conversely, to the Coq pretty-printer
to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with almost nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! We now define a function [beq_nat], which tests
[nat]ural numbers for [eq]uality, yielding a [b]oolean. Note the
use of nested [match]es (we could also have used a simultaneous
match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** The [leb] function tests whether its first argument is less than or
equal to its second argument, yielding a boolean. *)
Fixpoint leb (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => leb n' m'
end
end.
Example test_leb1: (leb 2 2) = true.
Proof. simpl. reflexivity. Qed.
Example test_leb2: (leb 2 4) = true.
Proof. simpl. reflexivity. Qed.
Example test_leb3: (leb 4 2) = false.
Proof. simpl. reflexivity. Qed.
(** **** Exercise: 1 star (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function. *)
Definition blt_nat (n m : nat) : bool
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example test_blt_nat1: (blt_nat 2 2) = false.
(* FILL IN HERE *) Admitted.
Example test_blt_nat2: (blt_nat 2 4) = true.
(* FILL IN HERE *) Admitted.
Example test_blt_nat3: (blt_nat 4 2) = false.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to stating and proving properties of their behavior.
Actually, we've already started doing this: each [Example] in the
previous sections makes a precise claim about the behavior of some
function on some particular inputs. The proofs of these claims
were always the same: use [simpl] to simplify both sides of the
equation, then use [reflexivity] to check that both sides contain
identical values.
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved just
by observing that [0 + n] reduces to [n] no matter what [n] is, a
fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. simpl. reflexivity. Qed.
(** (You may notice that the above statement looks different in
the [.v] file in your IDE than it does in the HTML rendition in
your browser, if you are viewing both. In [.v] files, we write the
[forall] universal quantifier using the reserved identifier
"forall." When the [.v] files are converted to HTML, this gets
transformed into an upside-down-A symbol.)
This is a good place to mention that [reflexivity] is a bit
more powerful than we have admitted. In the examples we have seen,
the calls to [simpl] were actually not needed, because
[reflexivity] can perform some simplification automatically when
checking that two sides are equal; [simpl] was just added so that
we could see the intermediate state -- after simplification but
before finishing the proof. Here is a shorter proof of the
theorem: *)
Theorem plus_O_n' : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** Moreover, it will be useful later to know that [reflexivity]
does somewhat _more_ simplification than [simpl] does -- for
example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
if reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
created by all this simplification and unfolding; by contrast,
[simpl] is used in situations where we may have to read and
understand the new goal that it creates, so we would not want it
blindly expanding definitions and leaving the goal in a messy
state.
The form of the theorem we just stated and its proof are almost
exactly the same as the simpler examples we saw earlier; there are
just a few differences.
First, we've used the keyword [Theorem] instead of [Example].
This difference is purely a matter of style; the keywords
[Example] and [Theorem] (and a few others, including [Lemma],
[Fact], and [Remark]) mean exactly the same thing to Coq.
Second, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. Informally, to
prove theorems of this form, we generally start by saying "Suppose
[n] is some number..." Formally, this is achieved in the proof by
[intros n], which moves [n] from the quantifier in the goal to a
_context_ of current assumptions.
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to guide the process of checking some claim we are making.
We will see several more tactics in the rest of this chapter and
yet more in future chapters.
Other similar theorems can be proved with the same pattern. *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(** It is worth stepping through these proofs to observe how the
context and the goal change. You may want to add calls to [simpl]
before [reflexivity] to see the simplifications that Coq performs
on the terms before checking that they are equal.
Although simplification is powerful enough to prove some fairly
general facts, there are many statements that cannot be handled by
simplification alone. For instance, we cannot use it to prove
that [0] is also a neutral element for [+] _on the right_. *)
Theorem plus_n_O : forall n, n = n + 0.
Proof.
intros n. simpl. (* Doesn't do anything! *)
(** (Can you explain why this happens? Step through both proofs
with Coq and notice how the goal and context change.)
When stuck in the middle of a proof, we can use the [Abort]
command to give up on it for the moment. *)
Abort.
(** The next chapter will introduce _induction_, a powerful
technique that can be used for proving this goal. For the moment,
though, let's look at a few more simple tactics. *)
(* ################################################################# *)
(** * Proof by Rewriting *)
(** This theorem is a bit more interesting than the others we've
seen: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a universal claim about all numbers [n] and [m],
it talks about a more specialized property that only holds when [n
= m]. The arrow symbol is pronounced "implies."
As before, we need to be able to reason by assuming we are given such
numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
(* move both quantifiers into the context: *)
intros n m.
(* move the hypothesis into the context: *)
intros H.
(* rewrite the goal using the hypothesis: *)
rewrite -> H.
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the name [H].
The third tells Coq to rewrite the current goal ([n + n = m + m])
by replacing the left side of the equality hypothesis [H] with the
right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** The [Admitted] command tells Coq that we want to skip trying
to prove this theorem and just accept it as a given. This can be
useful for developing longer proofs, since we can state subsidiary
lemmas that we believe will be useful for making some larger
argument, use [Admitted] to accept them on faith for the moment,
and continue working on the main argument until we are sure it
makes sense; then we can go back and fill in the proofs we
skipped. Be careful, though: every time you say [Admitted] you
are leaving a door open for total nonsense to enter Coq's nice,
rigorous, formally checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. If the statement
of the previously proved theorem involves quantified variables,
as in the example below, Coq tries to instantiate them
by matching with the current goal. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
(* FILL IN HERE *) Admitted.
(* (N.b. This proof can actually be completed without using [rewrite],
but please do use [rewrite] for the sake of the exercise.) *)
(** [] *)
(* ################################################################# *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation and rewriting: In general, unknown, hypothetical
values (arbitrary numbers, booleans, lists, etc.) can block
simplification. For example, if we try to prove the following
fact using the [simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
To make progress, we need to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false]. And
if [n = S n'] for some [n'], then, although we don't know exactly
what number [n + 1] yields, we can calculate that, at least, it
will begin with one [S], and this is enough to calculate that,
again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
- reflexivity.
- reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem. The
annotation "[as [| n']]" is called an _intro pattern_. It tells
Coq what variable names to introduce in each subgoal. In general,
what goes between the square brackets is a _list of lists_ of
names, separated by [|]. In this case, the first component is
empty, since the [O] constructor is nullary (it doesn't have any
arguments). The second component gives a single name, [n'], since
[S] is a unary constructor.
The [-] signs on the second and third lines are called _bullets_,
and they mark the parts of the proof that correspond to each
generated subgoal. The proof script that comes after a bullet is
the entire proof for a subgoal. In this example, each of the
subgoals is easily proved by a single use of [reflexivity], which
itself performs some simplification -- e.g., the first one
simplifies [beq_nat (S n' + 1) 0] to [false] by first rewriting
[(S n' + 1)] to [S (n' + 1)], then unfolding [beq_nat], and then
simplifying the [match].
Marking cases with bullets is entirely optional: if bullets are
not present, Coq simply asks you to prove each subgoal in
sequence, one at a time. But it is a good idea to use bullets.
For one thing, they make the structure of a proof apparent, making
it more readable. Also, bullets instruct Coq to ensure that a
subgoal is complete before trying to verify the next one,
preventing proofs for different subgoals from getting mixed
up. These issues become especially important in large
developments, where fragile proofs lead to long debugging
sessions.
There are no hard and fast rules for how proofs should be
formatted in Coq -- in particular, where lines should be broken
and how sections of the proof should be indented to indicate their
nested structure. However, if the places where multiple subgoals
are generated are marked with explicit bullets at the beginning of
lines, then the proof will be readable almost no matter what
choices are made about other aspects of layout.
This is also a good place to mention one other piece of somewhat
obvious advice about line lengths. Beginning Coq users sometimes
tend to the extremes, either writing each tactic on its own line
or writing entire proofs on one line. Good style lies somewhere
in the middle. One reasonable convention is to limit yourself to
80-character lines.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it next to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
- reflexivity.
- reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. This is generally considered bad style, since Coq
often makes confusing choices of names when left to its own
devices.
It is sometimes useful to invoke [destruct] inside a subgoal,
generating yet more proof obligations. In this case, we use
different kinds of bullets to mark goals on different "levels."
For example: *)
Theorem andb_commutative : forall b c, andb b c = andb c b.
Proof.
intros b c. destruct b.
- destruct c.
+ reflexivity.
+ reflexivity.
- destruct c.
+ reflexivity.
+ reflexivity.
Qed.
(** Each pair of calls to [reflexivity] corresponds to the
subgoals that were generated after the execution of the [destruct c]
line right above it. *)
(** Besides [-] and [+], we can use [*] (asterisk) as a third kind of
bullet. We can also enclose sub-proofs in curly braces, which is
useful in case we ever encounter a proof that generates more than
three levels of subgoals: *)
Theorem andb_commutative' : forall b c, andb b c = andb c b.
Proof.
intros b c. destruct b.
{ destruct c.
{ reflexivity. }
{ reflexivity. } }
{ destruct c.
{ reflexivity. }
{ reflexivity. } }
Qed.
(** Since curly braces mark both the beginning and the end of a
proof, they can be used for multiple subgoal levels, as this
example shows. Furthermore, curly braces allow us to reuse the
same bullet shapes at multiple levels in a proof: *)
Theorem andb3_exchange :
forall b c d, andb (andb b c) d = andb (andb b d) c.
Proof.
intros b c d. destruct b.
- destruct c.
{ destruct d.
- reflexivity.
- reflexivity. }
{ destruct d.
- reflexivity.
- reflexivity. }
- destruct c.
{ destruct d.
- reflexivity.
- reflexivity. }
{ destruct d.
- reflexivity.
- reflexivity. }
Qed.
(** Before closing the chapter, let's mention one final
convenience. As you may have noticed, many proofs perform case
analysis on a variable right after introducing it:
intros x y. destruct y as [|y].
This pattern is so common that Coq provides a shorthand for it: we
can perform case analysis on a variable when introducing it by
using an intro pattern instead of a variable name. For instance,
here is a shorter proof of the [plus_1_neq_0] theorem above. *)
Theorem plus_1_neq_0' : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros [|n].
- reflexivity.
- reflexivity. Qed.
(** If there are no arguments to name, we can just write [[]]. *)
Theorem andb_commutative'' :
forall b c, andb b c = andb c b.
Proof.
intros [] [].
- reflexivity.
- reflexivity.
- reflexivity.
- reflexivity.
Qed.
(** **** Exercise: 2 stars (andb_true_elim2) *)
(** Prove the following claim, marking cases (and subcases) with
bullets when you use [destruct]. *)
Theorem andb_true_elim2 : forall b c : bool,
andb b c = true -> c = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** More on Notation (Optional) *)
(** (In general, sections marked Optional are not needed to follow the
rest of the book, except possibly other Optional sections. On a
first reading, you might want to skim these sections so that you
know what's there for future reference.)
Recall the notation definitions for infix plus and times: *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation symbol in Coq, we can specify its _precedence
level_ and its _associativity_. The precedence level [n] is
specified by writing [at level n]; this helps Coq parse compound
expressions. The associativity setting helps to disambiguate
expressions containing multiple occurrences of the same
symbol. For example, the parameters specified above for [+] and
[*] say that the expression [1+2*3*4] is shorthand for
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity. We will see more examples
of this later, e.g., in the [Lists]
chapter.
Each notation symbol is also associated with a _notation scope_.
Coq tries to guess what scope is meant from context, so when it
sees [S(O*O)] it guesses [nat_scope], but when it sees the
cartesian product (tuple) type [bool*bool] (which we'll see in
later chapters) it guesses [type_scope]. Occasionally, it is
necessary to help it out with percent-notation by writing
[(x*y)%nat], and sometimes in what Coq prints it will use [%nat]
to indicate what scope a notation is in.
Notation scopes also apply to numeral notation ([3], [4], [5],
etc.), so you may sometimes see [0%nat], which means [O] (the
natural number [0] that we're using in this chapter), or [0%Z],
which means the Integer zero (which comes from a different part of
the standard library).
Pro tip: Coq's notation mechanism is not especially powerful.
Don't expect too much from it! *)
(* ================================================================= *)
(** ** Fixpoints and Structural Recursion (Optional) *)
(** Here is a copy of the definition of addition: *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing."
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will reject because
of this restriction. *)
(* FILL IN HERE *)
(** [] *)
(* ################################################################# *)
(** * More Exercises *)
(** **** Exercise: 2 starsM (boolean_functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
(* FILL IN HERE *) Admitted.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 starsM (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] above,
Inductive nat : Type := | O : nat | S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function [incr] for binary numbers,
and a function [bin_to_nat] to convert binary numbers to unary
numbers.
(c) Write five unit tests [test_bin_incr1], [test_bin_incr2], etc.
for your increment and binary-to-unary functions. (A "unit
test" in Coq is a specific [Example] that can be proved with
just [reflexivity], as we've done for several of our
definitions.) Notice that incrementing a binary number and
then converting it to unary should yield the same result as
first converting it to unary and then incrementing. *)
(* FILL IN HERE *)
(** [] *)
(** $Date: 2017-06-20 14:46:24 -0400 (Tue, 20 Jun 2017) $ *)
|
//////////////////////////////////////////////////////////////////////////////////
//
// Author : Praveen Kumar Pendyala
// Create Date : 05/27/13
// Modify Date : 16/01/14
// Module Name : mapping
// Project Name : PDL
// Target Devices : Xilinx Vertix 5, XUPV5 110T
// Tool versions : 13.2 ISE
//
// Description:
// This module maps the data received by the SircHandler (from PC) to the AluPuf.
// Issues appropriate trigger signals to start puf execution.
// Maintain state of the PUF operation - Idle or execute
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`default_nettype none
module mapping #(
parameter IN_WIDTH = 128,
parameter OUT_WIDTH = 16
)(
input wire clk,
input wire reset,
input wire trigger,
input wire [IN_WIDTH-1:0] dataIn,
output reg done,
output reg [OUT_WIDTH-1:0] dataOut,
output reg xorOut // Will use this later after output network is implemented.
);
// Input network also has to be implemented.
wire [15:0] response;
reg startPUF;
reg PUFreset;
reg [4:0] countWait;
integer ind;
reg [15:0] sum;
//FSM States
localparam IDLE = 0;
localparam COMPUTE = 1;
//State Register
reg mp_state;
reg [IN_WIDTH-1:0] buffer;
always @ (posedge clk) begin
if (reset) begin
done <= 0;
dataOut <= 0;
mp_state <= IDLE;
startPUF <= 0;
countWait <= 0;
PUFreset <=1;
end
else begin
case(mp_state)
IDLE: begin
done <= 0;
sum <= 0;
PUFreset <= 0;
countWait <=0;
startPUF <=0;
if(trigger == 1)
mp_state <= COMPUTE;
buffer <= dataIn;
end
COMPUTE: begin
startPUF <=1;
countWait <= countWait + 1;
if (countWait == 15) begin //wait for 10 clock cycles
startPUF<=0;
dataOut <= response;
done <= 1;
mp_state <= IDLE;
PUFreset <=1;
end
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32O_1_V
`define SKY130_FD_SC_LS__A32O_1_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a32o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a32o_1 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32O_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FILL_2_V
`define SKY130_FD_SC_LP__FILL_2_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fill_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fill_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__FILL_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32AI_LP_V
`define SKY130_FD_SC_LP__O32AI_LP_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32ai_lp (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32ai_lp (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32AI_LP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311OI_1_V
`define SKY130_FD_SC_LS__A311OI_1_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a311oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a311oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a311oi_1 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311OI_1_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 22:27:55 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_ov7670_controller_1_0 -prefix
// system_ov7670_controller_1_0_ system_ov7670_controller_1_0_stub.v
// Design : system_ov7670_controller_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_controller,Vivado 2016.4" *)
module system_ov7670_controller_1_0(clk, resend, config_finished, sioc, siod, reset,
pwdn, xclk)
/* synthesis syn_black_box black_box_pad_pin="clk,resend,config_finished,sioc,siod,reset,pwdn,xclk" */;
input clk;
input resend;
output config_finished;
output sioc;
inout siod;
output reset;
output pwdn;
output xclk;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef USE_VPI_NOT_DPI
//We call it via $c so we can verify DPI isn't required - see bug572
`else
import "DPI-C" context function integer mon_check();
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
`ifdef VERILATOR
`systemc_header
extern "C" int mon_check();
`verilog
`endif
input clk;
integer status;
wire a, b, x;
A mod_a(/*AUTOINST*/
// Outputs
.x (x),
// Inputs
.clk (clk),
.a (a),
.b (b));
// Test loop
initial begin
`ifdef VERILATOR
status = $c32("mon_check()");
`endif
`ifdef iverilog
status = $mon_check();
`endif
`ifndef USE_VPI_NOT_DPI
status = mon_check();
`endif
if (status!=0) begin
$write("%%Error: t_vpi_module.cpp:%0d: C Test failed\n", status);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule : t
module A(/*AUTOARG*/
// Outputs
x,
// Inputs
clk, a, b
);
input clk;
input a, b;
output x;
wire y, c;
B mod_b(/*AUTOINST*/
// Outputs
.y (y),
// Inputs
.b (b),
.c (c));
C \mod_c. (/*AUTOINST*/
// Outputs
.x (x),
// Inputs
.clk (clk),
.a (a),
.y (y));
endmodule : A
module B(/*AUTOARG*/
// Outputs
y,
// Inputs
b, c
); /*verilator public_module*/
input b, c;
output reg y;
always @(*) begin : myproc
y = b ^ c;
end
endmodule
module C(/*AUTOARG*/
// Outputs
x,
// Inputs
clk, a, y
);
input clk;
input a, y;
output reg x /* verilator public_flat_rw */;
always @(posedge clk) begin
x <= a & y;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_gclk_center_3inv.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// ------------------------------------------------------------------
module bw_clk_gclk_center_3inv(jbus_out ,ddr_out ,cmp_out ,jbus_in ,
ddr_in ,cmp_in );
output jbus_out ;
output ddr_out ;
output cmp_out ;
input jbus_in ;
input ddr_in ;
input cmp_in ;
bw_clk_gclk_inv_224x xddr (
.clkout (ddr_out ),
.clkin (ddr_in ) );
bw_clk_gclk_inv_224x xjbus (
.clkout (jbus_out ),
.clkin (jbus_in ) );
bw_clk_gclk_inv_224x xcmp (
.clkout (cmp_out ),
.clkin (cmp_in ) );
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: PLLM.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module PLLM (
inclk0,
c0,
c1,
locked);
input inclk0;
output c0;
output c1;
output locked;
wire [5:0] sub_wire0;
wire sub_wire3;
wire [0:0] sub_wire6 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire locked = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire3),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 2,
altpll_component.clk1_phase_shift = "-2778",
altpll_component.compensate_clock = "CLK0",
altpll_component.gate_lock_signal = "NO",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.invalid_lock_multiplier = 5,
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=PLLM",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.valid_lock_multiplier = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-100.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "PLLM.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2778"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL PLLM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLLM.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLLM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLLM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLLM.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLLM_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLLM_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLLM_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLLM_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//altdq_dqs CBX_SINGLE_OUTPUT_FILE="ON" DELAY_BUFFER_MODE="HIGH" DELAY_DQS_ENABLE_BY_HALF_CYCLE="TRUE" device_family="arriaii" DQ_HALF_RATE_USE_DATAOUTBYPASS="FALSE" DQ_INPUT_REG_ASYNC_MODE="NONE" DQ_INPUT_REG_CLK_SOURCE="INVERTED_DQS_BUS" DQ_INPUT_REG_MODE="DDIO" DQ_INPUT_REG_POWER_UP="LOW" DQ_INPUT_REG_SYNC_MODE="NONE" DQ_INPUT_REG_USE_CLKN="FALSE" DQ_IPA_ADD_INPUT_CYCLE_DELAY="FALSE" DQ_IPA_ADD_PHASE_TRANSFER_REG="FALSE" DQ_IPA_BYPASS_OUTPUT_REGISTER="FALSE" DQ_IPA_INVERT_PHASE="FALSE" DQ_IPA_PHASE_SETTING=0 DQ_OE_REG_ASYNC_MODE="NONE" DQ_OE_REG_MODE="FF" DQ_OE_REG_POWER_UP="LOW" DQ_OE_REG_SYNC_MODE="NONE" DQ_OUTPUT_REG_ASYNC_MODE="CLEAR" DQ_OUTPUT_REG_MODE="DDIO" DQ_OUTPUT_REG_POWER_UP="LOW" DQ_OUTPUT_REG_SYNC_MODE="NONE" DQS_CTRL_LATCHES_ENABLE="FALSE" DQS_DELAY_CHAIN_DELAYCTRLIN_SOURCE="DLL" DQS_DELAY_CHAIN_PHASE_SETTING=2 DQS_DQSN_MODE="DIFFERENTIAL" DQS_ENABLE_CTRL_ADD_PHASE_TRANSFER_REG="FALSE" DQS_ENABLE_CTRL_INVERT_PHASE="FALSE" DQS_ENABLE_CTRL_PHASE_SETTING=0 DQS_INPUT_FREQUENCY="333.0 MHz" DQS_OE_REG_ASYNC_MODE="NONE" DQS_OE_REG_MODE="FF" DQS_OE_REG_POWER_UP="LOW" DQS_OE_REG_SYNC_MODE="NONE" DQS_OFFSETCTRL_ENABLE="FALSE" DQS_OUTPUT_REG_ASYNC_MODE="NONE" DQS_OUTPUT_REG_MODE="DDIO" DQS_OUTPUT_REG_POWER_UP="LOW" DQS_OUTPUT_REG_SYNC_MODE="NONE" DQS_PHASE_SHIFT=7200 IO_CLOCK_DIVIDER_CLK_SOURCE="CORE" IO_CLOCK_DIVIDER_INVERT_PHASE="FALSE" IO_CLOCK_DIVIDER_PHASE_SETTING=0 LEVEL_DQS_ENABLE="FALSE" NUMBER_OF_BIDIR_DQ=8 NUMBER_OF_CLK_DIVIDER=0 NUMBER_OF_INPUT_DQ=0 NUMBER_OF_OUTPUT_DQ=1 OCT_REG_MODE="NONE" USE_DQ_INPUT_DELAY_CHAIN="FALSE" USE_DQ_IPA="FALSE" USE_DQ_IPA_PHASECTRLIN="FALSE" USE_DQ_OE_DELAY_CHAIN1="FALSE" USE_DQ_OE_DELAY_CHAIN2="FALSE" USE_DQ_OE_PATH="TRUE" USE_DQ_OUTPUT_DELAY_CHAIN1="FALSE" USE_DQ_OUTPUT_DELAY_CHAIN2="FALSE" USE_DQS="TRUE" USE_DQS_DELAY_CHAIN="TRUE" USE_DQS_DELAY_CHAIN_PHASECTRLIN="FALSE" USE_DQS_ENABLE="TRUE" USE_DQS_ENABLE_CTRL="TRUE" USE_DQS_ENABLE_CTRL_PHASECTRLIN="FALSE" USE_DQS_INPUT_DELAY_CHAIN="FALSE" USE_DQS_INPUT_PATH="TRUE" USE_DQS_OE_DELAY_CHAIN1="FALSE" USE_DQS_OE_DELAY_CHAIN2="FALSE" USE_DQS_OE_PATH="TRUE" USE_DQS_OUTPUT_DELAY_CHAIN1="FALSE" USE_DQS_OUTPUT_DELAY_CHAIN2="FALSE" USE_DQS_OUTPUT_PATH="TRUE" USE_DQSBUSOUT_DELAY_CHAIN="FALSE" USE_DQSENABLE_DELAY_CHAIN="FALSE" USE_DYNAMIC_OCT="FALSE" USE_HALF_RATE="FALSE" USE_IO_CLOCK_DIVIDER_MASTERIN="FALSE" USE_IO_CLOCK_DIVIDER_PHASECTRLIN="FALSE" USE_OCT_DELAY_CHAIN1="FALSE" USE_OCT_DELAY_CHAIN2="FALSE" bidir_dq_areset bidir_dq_input_data_in bidir_dq_input_data_out_high bidir_dq_input_data_out_low bidir_dq_oe_in bidir_dq_oe_out bidir_dq_output_data_in_high bidir_dq_output_data_in_low bidir_dq_output_data_out dll_delayctrlin dq_input_reg_clk dq_output_reg_clk dqs_enable_ctrl_clk dqs_enable_ctrl_in dqs_input_data_in dqs_oe_in dqs_oe_out dqs_output_data_in_high dqs_output_data_in_low dqs_output_data_out dqs_output_reg_clk dqsn_oe_in dqsn_oe_out output_dq_oe_in output_dq_oe_out output_dq_output_data_in_high output_dq_output_data_in_low output_dq_output_data_out
//VERSION_BEGIN 11.1 cbx_altdq_dqs 2011:10:31:21:11:05:SJ cbx_mgl 2011:10:31:21:12:31:SJ cbx_stratixiii 2011:10:31:21:11:05:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = arriaii_ddio_in 8 arriaii_ddio_out 10 arriaii_dqs_delay_chain 1 arriaii_dqs_enable 1 arriaii_dqs_enable_ctrl 1 reg 11
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"-name DQ_GROUP 9 -from dqs_0_delay_chain_inst -to bidir_dq_0_output_ddio_out_inst;-name DQ_GROUP 9 -from dqs_0_delay_chain_inst -to bidir_dq_1_output_ddio_out_inst;-name DQ_GROUP 9 -from dqs_0_delay_chain_inst -to bidir_dq_2_output_ddio_out_inst;-name DQ_GROUP 9 -from dqs_0_delay_chain_inst -to bidir_dq_3_output_ddio_out_inst;-name DQ_GROUP 9 -from dqs_0_delay_chain_inst -to bidir_dq_4_output_ddio_out_inst;-name DQ_GROUP 9 -from dqs_0_delay_chain_inst -to bidir_dq_5_output_ddio_out_inst;-name DQ_GROUP 9 -from dqs_0_delay_chain_inst -to bidir_dq_6_output_ddio_out_inst;-name DQ_GROUP 9 -from dqs_0_delay_chain_inst -to bidir_dq_7_output_ddio_out_inst;-name DQ_GROUP 9 -from dqs_0_delay_chain_inst -to output_dq_0_output_ddio_out_inst"} *)
module ddr3_int_phy_alt_mem_phy_dq_dqs
(
bidir_dq_areset,
bidir_dq_input_data_in,
bidir_dq_input_data_out_high,
bidir_dq_input_data_out_low,
bidir_dq_oe_in,
bidir_dq_oe_out,
bidir_dq_output_data_in_high,
bidir_dq_output_data_in_low,
bidir_dq_output_data_out,
dll_delayctrlin,
dq_input_reg_clk,
dq_output_reg_clk,
dqs_enable_ctrl_clk,
dqs_enable_ctrl_in,
dqs_input_data_in,
dqs_oe_in,
dqs_oe_out,
dqs_output_data_in_high,
dqs_output_data_in_low,
dqs_output_data_out,
dqs_output_reg_clk,
dqsn_oe_in,
dqsn_oe_out,
output_dq_oe_in,
output_dq_oe_out,
output_dq_output_data_in_high,
output_dq_output_data_in_low,
output_dq_output_data_out) /* synthesis synthesis_clearbox=1 */;
input [7:0] bidir_dq_areset;
input [7:0] bidir_dq_input_data_in;
output [7:0] bidir_dq_input_data_out_high;
output [7:0] bidir_dq_input_data_out_low;
input [7:0] bidir_dq_oe_in;
output [7:0] bidir_dq_oe_out;
input [7:0] bidir_dq_output_data_in_high;
input [7:0] bidir_dq_output_data_in_low;
output [7:0] bidir_dq_output_data_out;
input [5:0] dll_delayctrlin;
input dq_input_reg_clk;
input dq_output_reg_clk;
input dqs_enable_ctrl_clk;
input dqs_enable_ctrl_in;
input [0:0] dqs_input_data_in;
input [0:0] dqs_oe_in;
output [0:0] dqs_oe_out;
input [0:0] dqs_output_data_in_high;
input [0:0] dqs_output_data_in_low;
output [0:0] dqs_output_data_out;
input dqs_output_reg_clk;
input [0:0] dqsn_oe_in;
output [0:0] dqsn_oe_out;
input [0:0] output_dq_oe_in;
output [0:0] output_dq_oe_out;
input [0:0] output_dq_output_data_in_high;
input [0:0] output_dq_output_data_in_low;
output [0:0] output_dq_output_data_out;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [7:0] bidir_dq_areset;
tri0 [7:0] bidir_dq_input_data_in;
tri0 [7:0] bidir_dq_oe_in;
tri0 [7:0] bidir_dq_output_data_in_high;
tri0 [7:0] bidir_dq_output_data_in_low;
tri0 [5:0] dll_delayctrlin;
tri0 dq_input_reg_clk;
tri0 dq_output_reg_clk;
tri1 dqs_enable_ctrl_clk;
tri1 dqs_enable_ctrl_in;
tri0 [0:0] dqs_input_data_in;
tri0 [0:0] dqs_oe_in;
tri0 [0:0] dqs_output_data_in_high;
tri0 [0:0] dqs_output_data_in_low;
tri0 dqs_output_reg_clk;
tri0 [0:0] dqsn_oe_in;
tri0 [0:0] output_dq_oe_in;
tri0 [0:0] output_dq_output_data_in_high;
tri0 [0:0] output_dq_output_data_in_low;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg bidir_dq_0_oe_ff_inst;
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg bidir_dq_1_oe_ff_inst;
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg bidir_dq_2_oe_ff_inst;
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg bidir_dq_3_oe_ff_inst;
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg bidir_dq_4_oe_ff_inst;
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg bidir_dq_5_oe_ff_inst;
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg bidir_dq_6_oe_ff_inst;
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg bidir_dq_7_oe_ff_inst;
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg dqs_0_oe_ff_inst;
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg dqsn_0_oe_ff_inst;
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg output_dq_0_oe_ff_inst;
wire wire_bidir_dq_0_ddio_in_inst_regouthi;
wire wire_bidir_dq_0_ddio_in_inst_regoutlo;
wire wire_bidir_dq_1_ddio_in_inst_regouthi;
wire wire_bidir_dq_1_ddio_in_inst_regoutlo;
wire wire_bidir_dq_2_ddio_in_inst_regouthi;
wire wire_bidir_dq_2_ddio_in_inst_regoutlo;
wire wire_bidir_dq_3_ddio_in_inst_regouthi;
wire wire_bidir_dq_3_ddio_in_inst_regoutlo;
wire wire_bidir_dq_4_ddio_in_inst_regouthi;
wire wire_bidir_dq_4_ddio_in_inst_regoutlo;
wire wire_bidir_dq_5_ddio_in_inst_regouthi;
wire wire_bidir_dq_5_ddio_in_inst_regoutlo;
wire wire_bidir_dq_6_ddio_in_inst_regouthi;
wire wire_bidir_dq_6_ddio_in_inst_regoutlo;
wire wire_bidir_dq_7_ddio_in_inst_regouthi;
wire wire_bidir_dq_7_ddio_in_inst_regoutlo;
wire wire_bidir_dq_0_output_ddio_out_inst_dataout;
wire wire_bidir_dq_1_output_ddio_out_inst_dataout;
wire wire_bidir_dq_2_output_ddio_out_inst_dataout;
wire wire_bidir_dq_3_output_ddio_out_inst_dataout;
wire wire_bidir_dq_4_output_ddio_out_inst_dataout;
wire wire_bidir_dq_5_output_ddio_out_inst_dataout;
wire wire_bidir_dq_6_output_ddio_out_inst_dataout;
wire wire_bidir_dq_7_output_ddio_out_inst_dataout;
wire wire_dqs_0_output_ddio_out_inst_dataout;
wire wire_output_dq_0_output_ddio_out_inst_dataout;
wire wire_dqs_0_delay_chain_inst_dqsbusout;
wire wire_dqs_0_enable_inst_dqsbusout;
wire wire_dqs_0_enable_ctrl_inst_dqsenableout;
wire [0:0] dqs_bus_wire;
// synopsys translate_off
initial
bidir_dq_0_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dq_output_reg_clk)
bidir_dq_0_oe_ff_inst <= (~ bidir_dq_oe_in[0]);
// synopsys translate_off
initial
bidir_dq_1_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dq_output_reg_clk)
bidir_dq_1_oe_ff_inst <= (~ bidir_dq_oe_in[1]);
// synopsys translate_off
initial
bidir_dq_2_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dq_output_reg_clk)
bidir_dq_2_oe_ff_inst <= (~ bidir_dq_oe_in[2]);
// synopsys translate_off
initial
bidir_dq_3_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dq_output_reg_clk)
bidir_dq_3_oe_ff_inst <= (~ bidir_dq_oe_in[3]);
// synopsys translate_off
initial
bidir_dq_4_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dq_output_reg_clk)
bidir_dq_4_oe_ff_inst <= (~ bidir_dq_oe_in[4]);
// synopsys translate_off
initial
bidir_dq_5_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dq_output_reg_clk)
bidir_dq_5_oe_ff_inst <= (~ bidir_dq_oe_in[5]);
// synopsys translate_off
initial
bidir_dq_6_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dq_output_reg_clk)
bidir_dq_6_oe_ff_inst <= (~ bidir_dq_oe_in[6]);
// synopsys translate_off
initial
bidir_dq_7_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dq_output_reg_clk)
bidir_dq_7_oe_ff_inst <= (~ bidir_dq_oe_in[7]);
// synopsys translate_off
initial
dqs_0_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dqs_output_reg_clk)
dqs_0_oe_ff_inst <= (~ dqs_oe_in[0]);
// synopsys translate_off
initial
dqsn_0_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dqs_output_reg_clk)
dqsn_0_oe_ff_inst <= (~ dqsn_oe_in[0]);
// synopsys translate_off
initial
output_dq_0_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dq_output_reg_clk)
output_dq_0_oe_ff_inst <= (~ output_dq_oe_in[0]);
arriaii_ddio_in bidir_dq_0_ddio_in_inst
(
.clk((~ dqs_bus_wire[0])),
.datain(bidir_dq_input_data_in[0]),
.regouthi(wire_bidir_dq_0_ddio_in_inst_regouthi),
.regoutlo(wire_bidir_dq_0_ddio_in_inst_regoutlo)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkn(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_0_ddio_in_inst.async_mode = "none",
bidir_dq_0_ddio_in_inst.sync_mode = "none",
bidir_dq_0_ddio_in_inst.use_clkn = "false",
bidir_dq_0_ddio_in_inst.lpm_type = "arriaii_ddio_in";
arriaii_ddio_in bidir_dq_1_ddio_in_inst
(
.clk((~ dqs_bus_wire[0])),
.datain(bidir_dq_input_data_in[1]),
.regouthi(wire_bidir_dq_1_ddio_in_inst_regouthi),
.regoutlo(wire_bidir_dq_1_ddio_in_inst_regoutlo)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkn(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_1_ddio_in_inst.async_mode = "none",
bidir_dq_1_ddio_in_inst.sync_mode = "none",
bidir_dq_1_ddio_in_inst.use_clkn = "false",
bidir_dq_1_ddio_in_inst.lpm_type = "arriaii_ddio_in";
arriaii_ddio_in bidir_dq_2_ddio_in_inst
(
.clk((~ dqs_bus_wire[0])),
.datain(bidir_dq_input_data_in[2]),
.regouthi(wire_bidir_dq_2_ddio_in_inst_regouthi),
.regoutlo(wire_bidir_dq_2_ddio_in_inst_regoutlo)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkn(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_2_ddio_in_inst.async_mode = "none",
bidir_dq_2_ddio_in_inst.sync_mode = "none",
bidir_dq_2_ddio_in_inst.use_clkn = "false",
bidir_dq_2_ddio_in_inst.lpm_type = "arriaii_ddio_in";
arriaii_ddio_in bidir_dq_3_ddio_in_inst
(
.clk((~ dqs_bus_wire[0])),
.datain(bidir_dq_input_data_in[3]),
.regouthi(wire_bidir_dq_3_ddio_in_inst_regouthi),
.regoutlo(wire_bidir_dq_3_ddio_in_inst_regoutlo)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkn(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_3_ddio_in_inst.async_mode = "none",
bidir_dq_3_ddio_in_inst.sync_mode = "none",
bidir_dq_3_ddio_in_inst.use_clkn = "false",
bidir_dq_3_ddio_in_inst.lpm_type = "arriaii_ddio_in";
arriaii_ddio_in bidir_dq_4_ddio_in_inst
(
.clk((~ dqs_bus_wire[0])),
.datain(bidir_dq_input_data_in[4]),
.regouthi(wire_bidir_dq_4_ddio_in_inst_regouthi),
.regoutlo(wire_bidir_dq_4_ddio_in_inst_regoutlo)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkn(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_4_ddio_in_inst.async_mode = "none",
bidir_dq_4_ddio_in_inst.sync_mode = "none",
bidir_dq_4_ddio_in_inst.use_clkn = "false",
bidir_dq_4_ddio_in_inst.lpm_type = "arriaii_ddio_in";
arriaii_ddio_in bidir_dq_5_ddio_in_inst
(
.clk((~ dqs_bus_wire[0])),
.datain(bidir_dq_input_data_in[5]),
.regouthi(wire_bidir_dq_5_ddio_in_inst_regouthi),
.regoutlo(wire_bidir_dq_5_ddio_in_inst_regoutlo)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkn(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_5_ddio_in_inst.async_mode = "none",
bidir_dq_5_ddio_in_inst.sync_mode = "none",
bidir_dq_5_ddio_in_inst.use_clkn = "false",
bidir_dq_5_ddio_in_inst.lpm_type = "arriaii_ddio_in";
arriaii_ddio_in bidir_dq_6_ddio_in_inst
(
.clk((~ dqs_bus_wire[0])),
.datain(bidir_dq_input_data_in[6]),
.regouthi(wire_bidir_dq_6_ddio_in_inst_regouthi),
.regoutlo(wire_bidir_dq_6_ddio_in_inst_regoutlo)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkn(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_6_ddio_in_inst.async_mode = "none",
bidir_dq_6_ddio_in_inst.sync_mode = "none",
bidir_dq_6_ddio_in_inst.use_clkn = "false",
bidir_dq_6_ddio_in_inst.lpm_type = "arriaii_ddio_in";
arriaii_ddio_in bidir_dq_7_ddio_in_inst
(
.clk((~ dqs_bus_wire[0])),
.datain(bidir_dq_input_data_in[7]),
.regouthi(wire_bidir_dq_7_ddio_in_inst_regouthi),
.regoutlo(wire_bidir_dq_7_ddio_in_inst_regoutlo)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkn(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_7_ddio_in_inst.async_mode = "none",
bidir_dq_7_ddio_in_inst.sync_mode = "none",
bidir_dq_7_ddio_in_inst.use_clkn = "false",
bidir_dq_7_ddio_in_inst.lpm_type = "arriaii_ddio_in";
arriaii_ddio_out bidir_dq_0_output_ddio_out_inst
(
.areset(bidir_dq_areset[0]),
.clkhi(dq_output_reg_clk),
.clklo(dq_output_reg_clk),
.datainhi(bidir_dq_output_data_in_high[0]),
.datainlo(bidir_dq_output_data_in_low[0]),
.dataout(wire_bidir_dq_0_output_ddio_out_inst_dataout),
.muxsel(dq_output_reg_clk)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dffhi(),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_0_output_ddio_out_inst.async_mode = "clear",
bidir_dq_0_output_ddio_out_inst.half_rate_mode = "false",
bidir_dq_0_output_ddio_out_inst.power_up = "low",
bidir_dq_0_output_ddio_out_inst.sync_mode = "none",
bidir_dq_0_output_ddio_out_inst.use_new_clocking_model = "true",
bidir_dq_0_output_ddio_out_inst.lpm_type = "arriaii_ddio_out";
arriaii_ddio_out bidir_dq_1_output_ddio_out_inst
(
.areset(bidir_dq_areset[1]),
.clkhi(dq_output_reg_clk),
.clklo(dq_output_reg_clk),
.datainhi(bidir_dq_output_data_in_high[1]),
.datainlo(bidir_dq_output_data_in_low[1]),
.dataout(wire_bidir_dq_1_output_ddio_out_inst_dataout),
.muxsel(dq_output_reg_clk)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dffhi(),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_1_output_ddio_out_inst.async_mode = "clear",
bidir_dq_1_output_ddio_out_inst.half_rate_mode = "false",
bidir_dq_1_output_ddio_out_inst.power_up = "low",
bidir_dq_1_output_ddio_out_inst.sync_mode = "none",
bidir_dq_1_output_ddio_out_inst.use_new_clocking_model = "true",
bidir_dq_1_output_ddio_out_inst.lpm_type = "arriaii_ddio_out";
arriaii_ddio_out bidir_dq_2_output_ddio_out_inst
(
.areset(bidir_dq_areset[2]),
.clkhi(dq_output_reg_clk),
.clklo(dq_output_reg_clk),
.datainhi(bidir_dq_output_data_in_high[2]),
.datainlo(bidir_dq_output_data_in_low[2]),
.dataout(wire_bidir_dq_2_output_ddio_out_inst_dataout),
.muxsel(dq_output_reg_clk)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dffhi(),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_2_output_ddio_out_inst.async_mode = "clear",
bidir_dq_2_output_ddio_out_inst.half_rate_mode = "false",
bidir_dq_2_output_ddio_out_inst.power_up = "low",
bidir_dq_2_output_ddio_out_inst.sync_mode = "none",
bidir_dq_2_output_ddio_out_inst.use_new_clocking_model = "true",
bidir_dq_2_output_ddio_out_inst.lpm_type = "arriaii_ddio_out";
arriaii_ddio_out bidir_dq_3_output_ddio_out_inst
(
.areset(bidir_dq_areset[3]),
.clkhi(dq_output_reg_clk),
.clklo(dq_output_reg_clk),
.datainhi(bidir_dq_output_data_in_high[3]),
.datainlo(bidir_dq_output_data_in_low[3]),
.dataout(wire_bidir_dq_3_output_ddio_out_inst_dataout),
.muxsel(dq_output_reg_clk)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dffhi(),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_3_output_ddio_out_inst.async_mode = "clear",
bidir_dq_3_output_ddio_out_inst.half_rate_mode = "false",
bidir_dq_3_output_ddio_out_inst.power_up = "low",
bidir_dq_3_output_ddio_out_inst.sync_mode = "none",
bidir_dq_3_output_ddio_out_inst.use_new_clocking_model = "true",
bidir_dq_3_output_ddio_out_inst.lpm_type = "arriaii_ddio_out";
arriaii_ddio_out bidir_dq_4_output_ddio_out_inst
(
.areset(bidir_dq_areset[4]),
.clkhi(dq_output_reg_clk),
.clklo(dq_output_reg_clk),
.datainhi(bidir_dq_output_data_in_high[4]),
.datainlo(bidir_dq_output_data_in_low[4]),
.dataout(wire_bidir_dq_4_output_ddio_out_inst_dataout),
.muxsel(dq_output_reg_clk)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dffhi(),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_4_output_ddio_out_inst.async_mode = "clear",
bidir_dq_4_output_ddio_out_inst.half_rate_mode = "false",
bidir_dq_4_output_ddio_out_inst.power_up = "low",
bidir_dq_4_output_ddio_out_inst.sync_mode = "none",
bidir_dq_4_output_ddio_out_inst.use_new_clocking_model = "true",
bidir_dq_4_output_ddio_out_inst.lpm_type = "arriaii_ddio_out";
arriaii_ddio_out bidir_dq_5_output_ddio_out_inst
(
.areset(bidir_dq_areset[5]),
.clkhi(dq_output_reg_clk),
.clklo(dq_output_reg_clk),
.datainhi(bidir_dq_output_data_in_high[5]),
.datainlo(bidir_dq_output_data_in_low[5]),
.dataout(wire_bidir_dq_5_output_ddio_out_inst_dataout),
.muxsel(dq_output_reg_clk)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dffhi(),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_5_output_ddio_out_inst.async_mode = "clear",
bidir_dq_5_output_ddio_out_inst.half_rate_mode = "false",
bidir_dq_5_output_ddio_out_inst.power_up = "low",
bidir_dq_5_output_ddio_out_inst.sync_mode = "none",
bidir_dq_5_output_ddio_out_inst.use_new_clocking_model = "true",
bidir_dq_5_output_ddio_out_inst.lpm_type = "arriaii_ddio_out";
arriaii_ddio_out bidir_dq_6_output_ddio_out_inst
(
.areset(bidir_dq_areset[6]),
.clkhi(dq_output_reg_clk),
.clklo(dq_output_reg_clk),
.datainhi(bidir_dq_output_data_in_high[6]),
.datainlo(bidir_dq_output_data_in_low[6]),
.dataout(wire_bidir_dq_6_output_ddio_out_inst_dataout),
.muxsel(dq_output_reg_clk)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dffhi(),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_6_output_ddio_out_inst.async_mode = "clear",
bidir_dq_6_output_ddio_out_inst.half_rate_mode = "false",
bidir_dq_6_output_ddio_out_inst.power_up = "low",
bidir_dq_6_output_ddio_out_inst.sync_mode = "none",
bidir_dq_6_output_ddio_out_inst.use_new_clocking_model = "true",
bidir_dq_6_output_ddio_out_inst.lpm_type = "arriaii_ddio_out";
arriaii_ddio_out bidir_dq_7_output_ddio_out_inst
(
.areset(bidir_dq_areset[7]),
.clkhi(dq_output_reg_clk),
.clklo(dq_output_reg_clk),
.datainhi(bidir_dq_output_data_in_high[7]),
.datainlo(bidir_dq_output_data_in_low[7]),
.dataout(wire_bidir_dq_7_output_ddio_out_inst_dataout),
.muxsel(dq_output_reg_clk)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dffhi(),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_7_output_ddio_out_inst.async_mode = "clear",
bidir_dq_7_output_ddio_out_inst.half_rate_mode = "false",
bidir_dq_7_output_ddio_out_inst.power_up = "low",
bidir_dq_7_output_ddio_out_inst.sync_mode = "none",
bidir_dq_7_output_ddio_out_inst.use_new_clocking_model = "true",
bidir_dq_7_output_ddio_out_inst.lpm_type = "arriaii_ddio_out";
arriaii_ddio_out dqs_0_output_ddio_out_inst
(
.clkhi(dqs_output_reg_clk),
.clklo(dqs_output_reg_clk),
.datainhi(dqs_output_data_in_high[0]),
.datainlo(dqs_output_data_in_low[0]),
.dataout(wire_dqs_0_output_ddio_out_inst_dataout),
.muxsel(dqs_output_reg_clk)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clk(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dffhi(),
.dfflo()
// synopsys translate_on
);
defparam
dqs_0_output_ddio_out_inst.async_mode = "none",
dqs_0_output_ddio_out_inst.half_rate_mode = "false",
dqs_0_output_ddio_out_inst.sync_mode = "none",
dqs_0_output_ddio_out_inst.use_new_clocking_model = "true",
dqs_0_output_ddio_out_inst.lpm_type = "arriaii_ddio_out";
arriaii_ddio_out output_dq_0_output_ddio_out_inst
(
.clkhi(dq_output_reg_clk),
.clklo(dq_output_reg_clk),
.datainhi(output_dq_output_data_in_high[0]),
.datainlo(output_dq_output_data_in_low[0]),
.dataout(wire_output_dq_0_output_ddio_out_inst_dataout),
.muxsel(dq_output_reg_clk)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clk(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dffhi(),
.dfflo()
// synopsys translate_on
);
defparam
output_dq_0_output_ddio_out_inst.async_mode = "clear",
output_dq_0_output_ddio_out_inst.half_rate_mode = "false",
output_dq_0_output_ddio_out_inst.sync_mode = "none",
output_dq_0_output_ddio_out_inst.use_new_clocking_model = "true",
output_dq_0_output_ddio_out_inst.lpm_type = "arriaii_ddio_out";
arriaii_dqs_delay_chain dqs_0_delay_chain_inst
(
.delayctrlin(dll_delayctrlin),
.dqsbusout(wire_dqs_0_delay_chain_inst_dqsbusout),
.dqsin(dqs_input_data_in[0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dqsupdateen(1'b0),
.offsetctrlin({6{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
dqs_0_delay_chain_inst.delay_buffer_mode = "high",
dqs_0_delay_chain_inst.dqs_ctrl_latches_enable = "false",
dqs_0_delay_chain_inst.dqs_input_frequency = "333.0 MHz",
dqs_0_delay_chain_inst.dqs_offsetctrl_enable = "false",
dqs_0_delay_chain_inst.dqs_phase_shift = 7200,
dqs_0_delay_chain_inst.phase_setting = 2,
dqs_0_delay_chain_inst.lpm_type = "arriaii_dqs_delay_chain";
arriaii_dqs_enable dqs_0_enable_inst
(
.dqsbusout(wire_dqs_0_enable_inst_dqsbusout),
.dqsenable(wire_dqs_0_enable_ctrl_inst_dqsenableout),
.dqsin(wire_dqs_0_delay_chain_inst_dqsbusout)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
arriaii_dqs_enable_ctrl dqs_0_enable_ctrl_inst
(
.clk(dqs_enable_ctrl_clk),
.dqsenablein(dqs_enable_ctrl_in),
.dqsenableout(wire_dqs_0_enable_ctrl_inst_dqsenableout)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
dqs_0_enable_ctrl_inst.delay_dqs_enable_by_half_cycle = "true",
dqs_0_enable_ctrl_inst.lpm_type = "arriaii_dqs_enable_ctrl";
assign
bidir_dq_input_data_out_high = {wire_bidir_dq_7_ddio_in_inst_regouthi, wire_bidir_dq_6_ddio_in_inst_regouthi, wire_bidir_dq_5_ddio_in_inst_regouthi, wire_bidir_dq_4_ddio_in_inst_regouthi, wire_bidir_dq_3_ddio_in_inst_regouthi, wire_bidir_dq_2_ddio_in_inst_regouthi, wire_bidir_dq_1_ddio_in_inst_regouthi, wire_bidir_dq_0_ddio_in_inst_regouthi},
bidir_dq_input_data_out_low = {wire_bidir_dq_7_ddio_in_inst_regoutlo, wire_bidir_dq_6_ddio_in_inst_regoutlo, wire_bidir_dq_5_ddio_in_inst_regoutlo, wire_bidir_dq_4_ddio_in_inst_regoutlo, wire_bidir_dq_3_ddio_in_inst_regoutlo, wire_bidir_dq_2_ddio_in_inst_regoutlo, wire_bidir_dq_1_ddio_in_inst_regoutlo, wire_bidir_dq_0_ddio_in_inst_regoutlo},
bidir_dq_oe_out = {(~ bidir_dq_7_oe_ff_inst), (~ bidir_dq_6_oe_ff_inst), (~ bidir_dq_5_oe_ff_inst), (~ bidir_dq_4_oe_ff_inst), (~ bidir_dq_3_oe_ff_inst), (~ bidir_dq_2_oe_ff_inst), (~ bidir_dq_1_oe_ff_inst), (~ bidir_dq_0_oe_ff_inst)},
bidir_dq_output_data_out = {wire_bidir_dq_7_output_ddio_out_inst_dataout, wire_bidir_dq_6_output_ddio_out_inst_dataout, wire_bidir_dq_5_output_ddio_out_inst_dataout, wire_bidir_dq_4_output_ddio_out_inst_dataout, wire_bidir_dq_3_output_ddio_out_inst_dataout, wire_bidir_dq_2_output_ddio_out_inst_dataout, wire_bidir_dq_1_output_ddio_out_inst_dataout, wire_bidir_dq_0_output_ddio_out_inst_dataout},
dqs_bus_wire = {wire_dqs_0_enable_inst_dqsbusout},
dqs_oe_out = {(~ dqs_0_oe_ff_inst)},
dqs_output_data_out = {wire_dqs_0_output_ddio_out_inst_dataout},
dqsn_oe_out = {(~ dqsn_0_oe_ff_inst)},
output_dq_oe_out = {(~ output_dq_0_oe_ff_inst)},
output_dq_output_data_out = {wire_output_dq_0_output_ddio_out_inst_dataout};
endmodule //ddr3_int_phy_alt_mem_phy_dq_dqs
//VALID FILE
|
`timescale 1ns / 1ps
/*
-- Module Name: network core
-- Description: Top level de router NoC.
-- Dependencies: -- system.vh
-- router.v *
-- data_path.v
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- 05 de Junio 2015: Creacion
-- 11 de Junio 2015: Actualizacion de instancias de camino de
datos y camino de control.
-- 14 de Junio 2015: Actualizacion de instancias de camino de
datos y camino de control.
*/
`include "system.vh"
module des_network_core
(
input wire clk,
input wire reset,
// -- inports ----------------------------------------------- >>>>>
input wire [0:(`Y_WIDTH * `CHANNEL_WIDTH)-1] xpos_inports,
output wire [0:`Y_WIDTH-1] xpos_credits_outports,
input wire [0:(`Y_WIDTH * `CHANNEL_WIDTH)-1] xneg_inports,
output wire [0:`Y_WIDTH-1] xneg_credits_outports,
input wire [0:(`X_WIDTH * `CHANNEL_WIDTH)-1] ypos_inports,
output wire [0:`X_WIDTH-1] ypos_credits_outports,
input wire [0:(`X_WIDTH * `CHANNEL_WIDTH)-1] yneg_inports,
output wire [0:`X_WIDTH-1] yneg_credits_outports,
// -- outports ----------------------------------------------- >>>>>
output wire [0:(`Y_WIDTH * `CHANNEL_WIDTH)-1] xpos_outports,
input wire [0:`Y_WIDTH-1] xpos_credits_inports,
output wire [0:(`Y_WIDTH * `CHANNEL_WIDTH)-1] xneg_outports,
input wire [0:`Y_WIDTH-1] xneg_credits_inports,
output wire [0:(`X_WIDTH * `CHANNEL_WIDTH)-1] ypos_outports,
input wire [0:`X_WIDTH-1] ypos_credits_inports,
output wire [0:(`X_WIDTH * `CHANNEL_WIDTH)-1] yneg_outports,
input wire [0:`X_WIDTH-1] yneg_credits_inports
);
// -- Declaracion temprana de señales ---------------------------- >>>>>
wire [`CHANNEL_WIDTH-1:0] row_right_channels [0:`X_WIDTH][0:`Y_WIDTH-1];
wire row_left_credit [0:`X_WIDTH][0:`Y_WIDTH-1];
wire [`CHANNEL_WIDTH-1:0] row_left_channels [0:`X_WIDTH][0:`Y_WIDTH-1];
wire row_right_credit [0:`X_WIDTH][0:`Y_WIDTH-1];
wire [`CHANNEL_WIDTH-1:0] col_down_channels [0:`X_WIDTH-1][0:`Y_WIDTH];
wire col_up_credit [0:`X_WIDTH-1][0:`Y_WIDTH];
wire [`CHANNEL_WIDTH-1:0] col_up_channels [0:`X_WIDTH-1][0:`Y_WIDTH];
wire col_down_credit [0:`X_WIDTH-1][0:`Y_WIDTH];
// -- Andamiaje para interconexion de buses de puertos ----------- >>>>>
genvar rows;
genvar cols;
generate
for (rows = 0; rows < `Y_WIDTH; rows = rows + 1)
begin
// -- inport / outport X- bus ------------------------ >>>>>
assign row_right_channels [0][rows] = xneg_inports [rows * `CHANNEL_WIDTH:(rows * `CHANNEL_WIDTH + `CHANNEL_WIDTH) - 1];
assign xneg_credits_outports [rows] = row_left_credit [0][rows];
assign xneg_outports [rows*`CHANNEL_WIDTH:(rows * `CHANNEL_WIDTH + `CHANNEL_WIDTH) - 1] = row_left_channels [0][rows];
assign row_right_credit [0][rows] = xneg_credits_inports [rows];
// -- inport / outport X+ bus ------------------------ >>>>>
assign row_left_channels [`X_WIDTH][rows] = xpos_inports [rows * `CHANNEL_WIDTH:(rows * `CHANNEL_WIDTH + `CHANNEL_WIDTH) - 1];
assign xpos_credits_outports [rows] = row_right_credit [`X_WIDTH][rows];
assign xpos_outports [rows*`CHANNEL_WIDTH:(rows * `CHANNEL_WIDTH + `CHANNEL_WIDTH) - 1] = row_right_channels[`X_WIDTH][rows];
assign row_left_credit [`X_WIDTH][rows] = xpos_credits_inports [rows];
end
endgenerate
generate
for (cols = 0; cols < `X_WIDTH; cols = cols + 1)
begin
// -- inport / outport Y+ bus ------------------------ >>>>>
assign col_down_channels [cols][`Y_WIDTH] = ypos_inports [cols * `CHANNEL_WIDTH:(cols * `CHANNEL_WIDTH + `CHANNEL_WIDTH) - 1];
assign ypos_credits_outports [cols] = col_up_credit [cols][`Y_WIDTH];
assign ypos_outports [cols * `CHANNEL_WIDTH:(cols * `CHANNEL_WIDTH + `CHANNEL_WIDTH) - 1] = col_up_channels [cols][`Y_WIDTH];
assign col_down_credit [cols][`Y_WIDTH] = ypos_credits_inports [cols];
// -- inport / outport Y- bus ------------------------ >>>>>
assign col_up_channels [cols][0] = yneg_inports [cols * `CHANNEL_WIDTH:(cols * `CHANNEL_WIDTH + `CHANNEL_WIDTH) - 1];
assign yneg_credits_outports [cols] = col_down_credit [cols][0];
assign yneg_outports [cols * `CHANNEL_WIDTH:(cols * `CHANNEL_WIDTH + `CHANNEL_WIDTH) - 1] = col_down_channels[cols][0];
assign col_up_credit [cols][0] = yneg_credits_inports [cols];
end
endgenerate
// -- Instancia de Nodos ----------------------------------------- >>>>>
generate
for (cols = 0; cols < `X_WIDTH; cols = cols + 1)
begin: columna
for (rows = 0; rows < `Y_WIDTH; rows = rows + 1)
begin: lancetfish_node
des_node
#(
.X_LOCAL(cols + 1),
.Y_LOCAL(rows + 1)
)
des_node
(
.clk (clk),
.reset (reset),
// -- puertos de entrada ------------------------------------- >>>>>
.channel_xneg_din (row_right_channels [cols][rows]),
.credit_out_xneg_dout (row_left_credit [cols][rows]),
.channel_xpos_din (row_left_channels [cols+1][rows]),
.credit_out_xpos_dout (row_right_credit [cols+1][rows]),
.channel_ypos_din (col_down_channels [cols][rows+1]),
.credit_out_ypos_dout (col_up_credit [cols][rows+1]),
.channel_yneg_din (col_up_channels [cols][rows]),
.credit_out_yneg_dout (col_down_credit [cols][rows]),
// -- puertos de salida -------------------------------------- >>>>>
.channel_xneg_dout (row_left_channels [cols][rows]),
.credit_in_xneg_din (row_right_credit [cols][rows]),
.channel_xpos_dout (row_right_channels [cols+1][rows]),
.credit_in_xpos_din (row_left_credit [cols+1][rows]),
.channel_ypos_dout (col_up_channels [cols][rows+1]),
.credit_in_ypos_din (col_down_credit [cols][rows+1]),
.channel_yneg_dout (col_down_channels [cols][rows]),
.credit_in_yneg_din (col_up_credit [cols][rows])
);
end
end
endgenerate
endmodule
/* -- Plantilla de instancia ------------------------------------- >>>>>
// -- Ancho de Frente de red (X)
// canales :: [0:(`X_WIDTH * `CHANNEL_WIDTH)-1]
// creditos :: [0:`X_WIDTH-1]
// -- Ancho de Frente de red (Y)
// canales :: [0:(`X_WIDTH * `CHANNEL_WIDTH)-1]
// creditos :: [0:`X_WIDTH-1]
module lancetfish_network_core
(
.clk(clk),
.reset(reset),
// -- inports ----------------------------------------------- >>>>>
.xpos_inports (xpos_inports),
.xpos_credits_outports (xpos_credits_outports),
.xneg_inports (xneg_inports),
.xneg_credits_outports (xneg_credits_outports),
.ypos_inports (ypos_inports),
.ypos_credits_outports (ypos_credits_outports),
.yneg_inports (yneg_inports),
.yneg_credits_outports (yneg_credits_outports),
// -- outports ----------------------------------------------- >>>>>
.xpos_outports (xpos_outports),
.xpos_credits_inports (xpos_credits_inports),
.xneg_outports (xneg_outports),
.xneg_credits_inports (xneg_credits_inports),
.ypos_outports (ypos_outports),
.ypos_credits_inports (ypos_credits_inports),
.yneg_outports (yneg_outports),
.yneg_credits_inports (yneg_credits_inports)
);
// --------------------------------------------------------------- >>>>>*/ |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR3_TB_V
`define SKY130_FD_SC_LS__XOR3_TB_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__xor3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ls__xor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR3_TB_V
|
module var23_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, valid);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W;
output valid;
wire [8:0] min_value = 9'd120;
wire [8:0] max_weight = 9'd60;
wire [8:0] max_volume = 9'd60;
wire [8:0] total_value =
A * 9'd4
+ B * 9'd8
+ C * 9'd0
+ D * 9'd20
+ E * 9'd10
+ F * 9'd12
+ G * 9'd18
+ H * 9'd14
+ I * 9'd6
+ J * 9'd15
+ K * 9'd30
+ L * 9'd8
+ M * 9'd16
+ N * 9'd18
+ O * 9'd18
+ P * 9'd14
+ Q * 9'd7
+ R * 9'd7
+ S * 9'd29
+ T * 9'd23
+ U * 9'd24
+ V * 9'd3
+ W * 9'd18;
wire [8:0] total_weight =
A * 9'd28
+ B * 9'd8
+ C * 9'd27
+ D * 9'd18
+ E * 9'd27
+ F * 9'd28
+ G * 9'd6
+ H * 9'd1
+ I * 9'd20
+ J * 9'd0
+ K * 9'd5
+ L * 9'd13
+ M * 9'd8
+ N * 9'd14
+ O * 9'd22
+ P * 9'd12
+ Q * 9'd23
+ R * 9'd26
+ S * 9'd1
+ T * 9'd22
+ U * 9'd26
+ V * 9'd15
+ W * 9'd0;
wire [8:0] total_volume =
A * 9'd27
+ B * 9'd27
+ C * 9'd4
+ D * 9'd4
+ E * 9'd0
+ F * 9'd24
+ G * 9'd4
+ H * 9'd20
+ I * 9'd12
+ J * 9'd15
+ K * 9'd5
+ L * 9'd2
+ M * 9'd9
+ N * 9'd28
+ O * 9'd19
+ P * 9'd18
+ Q * 9'd30
+ R * 9'd12
+ S * 9'd28
+ T * 9'd13
+ U * 9'd18
+ V * 9'd16
+ W * 9'd26;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: denise_colortable_ram_mf.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module denise_colortable_ram_mf (
byteena_a,
clock,
data,
enable,
rdaddress,
wraddress,
wren,
q);
input [3:0] byteena_a;
input clock;
input [31:0] data;
input enable;
input [7:0] rdaddress;
input [7:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena_a;
tri1 clock;
tri1 enable;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.byteena_a (byteena_a),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.clocken0 (enable),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_input_b = "NORMAL",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "1"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC "byteena_a[3..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: enable 0 0 0 0 INPUT VCC "enable"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 enable 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL denise_colortable_ram_mf.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL denise_colortable_ram_mf.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL denise_colortable_ram_mf.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL denise_colortable_ram_mf.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL denise_colortable_ram_mf_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL denise_colortable_ram_mf_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Based on Sauraen VHDL version of OPN/OPN2, which is based on die shots.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-1-2017
*/
module jt12_opram
(
input [4:0] wr_addr,
input [4:0] rd_addr,
input clk,
input clk_en,
input [43:0] data,
output reg [43:0] q
);
reg [43:0] ram[31:0];
always @ (posedge clk) if(clk_en) begin
q <= ram[rd_addr];
ram[wr_addr] <= data;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2I_4_V
`define SKY130_FD_SC_HD__MUX2I_4_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__mux2i_4 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__mux2i_4 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2I_4_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/13/2017 05:18:39 PM
// Design Name:
// Module Name: SHA1_out
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SHA1_out(input clk,
input rst,
input start,
input [159:0]digest_in,
output reg done,
output reg [31:0]hash_out
);
//reg done;
//reg [31:0]hash_out;
reg [2:0]count;
always@(posedge clk or negedge rst) begin
if(rst == 0) begin
done <= 0;
hash_out <= 0;
count <= 0;
end else begin
if(start)
if(count < 6)
count <= count + 1;
end
end
always@(count) begin
if(count == 1) begin
done = 1;
hash_out = digest_in[31:0];
end
else if(count == 2)
hash_out = digest_in[63:32];
else if(count == 3)
hash_out = digest_in[95:64];
else if(count == 4)
hash_out = digest_in[127:96];
else if(count == 5)
hash_out = digest_in[159:128];
else if (count == 6) begin
done = 0;
hash_out = 0;
end
else begin end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUF_SYMBOL_V
`define SKY130_FD_SC_MS__BUF_SYMBOL_V
/**
* buf: Buffer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__buf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUF_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 08 17:42:47 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_rgb888_to_rgb565_0_0 -prefix
// system_rgb888_to_rgb565_0_0_ system_rgb888_to_rgb565_0_0_stub.v
// Design : system_rgb888_to_rgb565_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "rgb888_to_rgb565,Vivado 2016.4" *)
module system_rgb888_to_rgb565_0_0(rgb_888, rgb_565)
/* synthesis syn_black_box black_box_pad_pin="rgb_888[23:0],rgb_565[15:0]" */;
input [23:0]rgb_888;
output [15:0]rgb_565;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3_FUNCTIONAL_V
`define SKY130_FD_SC_HD__NAND3_FUNCTIONAL_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nand3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3_FUNCTIONAL_V |
//-----------------------------------------------------------------
// USB Device Core
// V1.0
// Ultra-Embedded.com
// Copyright 2014-2019
//
// Email: [email protected]
//
// License: GPL
// If you would like a version with a more permissive license for
// use in closed source commercial applications please contact me
// for details.
//-----------------------------------------------------------------
//
// This file is open source HDL; you can redistribute it and/or
// modify it under the terms of the GNU General Public License as
// published by the Free Software Foundation; either version 2 of
// the License, or (at your option) any later version.
//
// This file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this file; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
// USA
//-----------------------------------------------------------------
//`include "usbf_device_defs.v"
`define USB_FUNC_CTRL 8'h0
`define USB_FUNC_CTRL_HS_CHIRP_EN 8
`define USB_FUNC_CTRL_HS_CHIRP_EN_DEFAULT 0
`define USB_FUNC_CTRL_HS_CHIRP_EN_B 8
`define USB_FUNC_CTRL_HS_CHIRP_EN_T 8
`define USB_FUNC_CTRL_HS_CHIRP_EN_W 1
`define USB_FUNC_CTRL_HS_CHIRP_EN_R 8:8
`define USB_FUNC_CTRL_PHY_DMPULLDOWN 7
`define USB_FUNC_CTRL_PHY_DMPULLDOWN_DEFAULT 0
`define USB_FUNC_CTRL_PHY_DMPULLDOWN_B 7
`define USB_FUNC_CTRL_PHY_DMPULLDOWN_T 7
`define USB_FUNC_CTRL_PHY_DMPULLDOWN_W 1
`define USB_FUNC_CTRL_PHY_DMPULLDOWN_R 7:7
`define USB_FUNC_CTRL_PHY_DPPULLDOWN 6
`define USB_FUNC_CTRL_PHY_DPPULLDOWN_DEFAULT 0
`define USB_FUNC_CTRL_PHY_DPPULLDOWN_B 6
`define USB_FUNC_CTRL_PHY_DPPULLDOWN_T 6
`define USB_FUNC_CTRL_PHY_DPPULLDOWN_W 1
`define USB_FUNC_CTRL_PHY_DPPULLDOWN_R 6:6
`define USB_FUNC_CTRL_PHY_TERMSELECT 5
`define USB_FUNC_CTRL_PHY_TERMSELECT_DEFAULT 0
`define USB_FUNC_CTRL_PHY_TERMSELECT_B 5
`define USB_FUNC_CTRL_PHY_TERMSELECT_T 5
`define USB_FUNC_CTRL_PHY_TERMSELECT_W 1
`define USB_FUNC_CTRL_PHY_TERMSELECT_R 5:5
`define USB_FUNC_CTRL_PHY_XCVRSELECT_DEFAULT 0
`define USB_FUNC_CTRL_PHY_XCVRSELECT_B 3
`define USB_FUNC_CTRL_PHY_XCVRSELECT_T 4
`define USB_FUNC_CTRL_PHY_XCVRSELECT_W 2
`define USB_FUNC_CTRL_PHY_XCVRSELECT_R 4:3
`define USB_FUNC_CTRL_PHY_OPMODE_DEFAULT 0
`define USB_FUNC_CTRL_PHY_OPMODE_B 1
`define USB_FUNC_CTRL_PHY_OPMODE_T 2
`define USB_FUNC_CTRL_PHY_OPMODE_W 2
`define USB_FUNC_CTRL_PHY_OPMODE_R 2:1
`define USB_FUNC_CTRL_INT_EN_SOF 0
`define USB_FUNC_CTRL_INT_EN_SOF_DEFAULT 0
`define USB_FUNC_CTRL_INT_EN_SOF_B 0
`define USB_FUNC_CTRL_INT_EN_SOF_T 0
`define USB_FUNC_CTRL_INT_EN_SOF_W 1
`define USB_FUNC_CTRL_INT_EN_SOF_R 0:0
`define USB_FUNC_STAT 8'h4
`define USB_FUNC_STAT_RST 13
`define USB_FUNC_STAT_RST_DEFAULT 0
`define USB_FUNC_STAT_RST_B 13
`define USB_FUNC_STAT_RST_T 13
`define USB_FUNC_STAT_RST_W 1
`define USB_FUNC_STAT_RST_R 13:13
`define USB_FUNC_STAT_LINESTATE_DEFAULT 0
`define USB_FUNC_STAT_LINESTATE_B 11
`define USB_FUNC_STAT_LINESTATE_T 12
`define USB_FUNC_STAT_LINESTATE_W 2
`define USB_FUNC_STAT_LINESTATE_R 12:11
`define USB_FUNC_STAT_FRAME_DEFAULT 0
`define USB_FUNC_STAT_FRAME_B 0
`define USB_FUNC_STAT_FRAME_T 10
`define USB_FUNC_STAT_FRAME_W 11
`define USB_FUNC_STAT_FRAME_R 10:0
`define USB_FUNC_ADDR 8'h8
`define USB_FUNC_ADDR_DEV_ADDR_DEFAULT 0
`define USB_FUNC_ADDR_DEV_ADDR_B 0
`define USB_FUNC_ADDR_DEV_ADDR_T 6
`define USB_FUNC_ADDR_DEV_ADDR_W 7
`define USB_FUNC_ADDR_DEV_ADDR_R 6:0
`define USB_EP0_CFG 8'hc
`define USB_EP0_CFG_INT_RX 3
`define USB_EP0_CFG_INT_RX_DEFAULT 0
`define USB_EP0_CFG_INT_RX_B 3
`define USB_EP0_CFG_INT_RX_T 3
`define USB_EP0_CFG_INT_RX_W 1
`define USB_EP0_CFG_INT_RX_R 3:3
`define USB_EP0_CFG_INT_TX 2
`define USB_EP0_CFG_INT_TX_DEFAULT 0
`define USB_EP0_CFG_INT_TX_B 2
`define USB_EP0_CFG_INT_TX_T 2
`define USB_EP0_CFG_INT_TX_W 1
`define USB_EP0_CFG_INT_TX_R 2:2
`define USB_EP0_CFG_STALL_EP 1
`define USB_EP0_CFG_STALL_EP_DEFAULT 0
`define USB_EP0_CFG_STALL_EP_B 1
`define USB_EP0_CFG_STALL_EP_T 1
`define USB_EP0_CFG_STALL_EP_W 1
`define USB_EP0_CFG_STALL_EP_R 1:1
`define USB_EP0_CFG_ISO 0
`define USB_EP0_CFG_ISO_DEFAULT 0
`define USB_EP0_CFG_ISO_B 0
`define USB_EP0_CFG_ISO_T 0
`define USB_EP0_CFG_ISO_W 1
`define USB_EP0_CFG_ISO_R 0:0
`define USB_EP0_TX_CTRL 8'h10
`define USB_EP0_TX_CTRL_TX_FLUSH 17
`define USB_EP0_TX_CTRL_TX_FLUSH_DEFAULT 0
`define USB_EP0_TX_CTRL_TX_FLUSH_B 17
`define USB_EP0_TX_CTRL_TX_FLUSH_T 17
`define USB_EP0_TX_CTRL_TX_FLUSH_W 1
`define USB_EP0_TX_CTRL_TX_FLUSH_R 17:17
`define USB_EP0_TX_CTRL_TX_START 16
`define USB_EP0_TX_CTRL_TX_START_DEFAULT 0
`define USB_EP0_TX_CTRL_TX_START_B 16
`define USB_EP0_TX_CTRL_TX_START_T 16
`define USB_EP0_TX_CTRL_TX_START_W 1
`define USB_EP0_TX_CTRL_TX_START_R 16:16
`define USB_EP0_TX_CTRL_TX_LEN_DEFAULT 0
`define USB_EP0_TX_CTRL_TX_LEN_B 0
`define USB_EP0_TX_CTRL_TX_LEN_T 10
`define USB_EP0_TX_CTRL_TX_LEN_W 11
`define USB_EP0_TX_CTRL_TX_LEN_R 10:0
`define USB_EP0_RX_CTRL 8'h14
`define USB_EP0_RX_CTRL_RX_FLUSH 1
`define USB_EP0_RX_CTRL_RX_FLUSH_DEFAULT 0
`define USB_EP0_RX_CTRL_RX_FLUSH_B 1
`define USB_EP0_RX_CTRL_RX_FLUSH_T 1
`define USB_EP0_RX_CTRL_RX_FLUSH_W 1
`define USB_EP0_RX_CTRL_RX_FLUSH_R 1:1
`define USB_EP0_RX_CTRL_RX_ACCEPT 0
`define USB_EP0_RX_CTRL_RX_ACCEPT_DEFAULT 0
`define USB_EP0_RX_CTRL_RX_ACCEPT_B 0
`define USB_EP0_RX_CTRL_RX_ACCEPT_T 0
`define USB_EP0_RX_CTRL_RX_ACCEPT_W 1
`define USB_EP0_RX_CTRL_RX_ACCEPT_R 0:0
`define USB_EP0_STS 8'h18
`define USB_EP0_STS_TX_ERR 20
`define USB_EP0_STS_TX_ERR_DEFAULT 0
`define USB_EP0_STS_TX_ERR_B 20
`define USB_EP0_STS_TX_ERR_T 20
`define USB_EP0_STS_TX_ERR_W 1
`define USB_EP0_STS_TX_ERR_R 20:20
`define USB_EP0_STS_TX_BUSY 19
`define USB_EP0_STS_TX_BUSY_DEFAULT 0
`define USB_EP0_STS_TX_BUSY_B 19
`define USB_EP0_STS_TX_BUSY_T 19
`define USB_EP0_STS_TX_BUSY_W 1
`define USB_EP0_STS_TX_BUSY_R 19:19
`define USB_EP0_STS_RX_ERR 18
`define USB_EP0_STS_RX_ERR_DEFAULT 0
`define USB_EP0_STS_RX_ERR_B 18
`define USB_EP0_STS_RX_ERR_T 18
`define USB_EP0_STS_RX_ERR_W 1
`define USB_EP0_STS_RX_ERR_R 18:18
`define USB_EP0_STS_RX_SETUP 17
`define USB_EP0_STS_RX_SETUP_DEFAULT 0
`define USB_EP0_STS_RX_SETUP_B 17
`define USB_EP0_STS_RX_SETUP_T 17
`define USB_EP0_STS_RX_SETUP_W 1
`define USB_EP0_STS_RX_SETUP_R 17:17
`define USB_EP0_STS_RX_READY 16
`define USB_EP0_STS_RX_READY_DEFAULT 0
`define USB_EP0_STS_RX_READY_B 16
`define USB_EP0_STS_RX_READY_T 16
`define USB_EP0_STS_RX_READY_W 1
`define USB_EP0_STS_RX_READY_R 16:16
`define USB_EP0_STS_RX_COUNT_DEFAULT 0
`define USB_EP0_STS_RX_COUNT_B 0
`define USB_EP0_STS_RX_COUNT_T 10
`define USB_EP0_STS_RX_COUNT_W 11
`define USB_EP0_STS_RX_COUNT_R 10:0
`define USB_EP0_DATA 8'h1c
`define USB_EP0_DATA_DATA_DEFAULT 0
`define USB_EP0_DATA_DATA_B 0
`define USB_EP0_DATA_DATA_T 7
`define USB_EP0_DATA_DATA_W 8
`define USB_EP0_DATA_DATA_R 7:0
`define USB_EP1_CFG 8'h20
`define USB_EP1_CFG_INT_RX 3
`define USB_EP1_CFG_INT_RX_DEFAULT 0
`define USB_EP1_CFG_INT_RX_B 3
`define USB_EP1_CFG_INT_RX_T 3
`define USB_EP1_CFG_INT_RX_W 1
`define USB_EP1_CFG_INT_RX_R 3:3
`define USB_EP1_CFG_INT_TX 2
`define USB_EP1_CFG_INT_TX_DEFAULT 0
`define USB_EP1_CFG_INT_TX_B 2
`define USB_EP1_CFG_INT_TX_T 2
`define USB_EP1_CFG_INT_TX_W 1
`define USB_EP1_CFG_INT_TX_R 2:2
`define USB_EP1_CFG_STALL_EP 1
`define USB_EP1_CFG_STALL_EP_DEFAULT 0
`define USB_EP1_CFG_STALL_EP_B 1
`define USB_EP1_CFG_STALL_EP_T 1
`define USB_EP1_CFG_STALL_EP_W 1
`define USB_EP1_CFG_STALL_EP_R 1:1
`define USB_EP1_CFG_ISO 0
`define USB_EP1_CFG_ISO_DEFAULT 0
`define USB_EP1_CFG_ISO_B 0
`define USB_EP1_CFG_ISO_T 0
`define USB_EP1_CFG_ISO_W 1
`define USB_EP1_CFG_ISO_R 0:0
`define USB_EP1_TX_CTRL 8'h24
`define USB_EP1_TX_CTRL_TX_FLUSH 17
`define USB_EP1_TX_CTRL_TX_FLUSH_DEFAULT 0
`define USB_EP1_TX_CTRL_TX_FLUSH_B 17
`define USB_EP1_TX_CTRL_TX_FLUSH_T 17
`define USB_EP1_TX_CTRL_TX_FLUSH_W 1
`define USB_EP1_TX_CTRL_TX_FLUSH_R 17:17
`define USB_EP1_TX_CTRL_TX_START 16
`define USB_EP1_TX_CTRL_TX_START_DEFAULT 0
`define USB_EP1_TX_CTRL_TX_START_B 16
`define USB_EP1_TX_CTRL_TX_START_T 16
`define USB_EP1_TX_CTRL_TX_START_W 1
`define USB_EP1_TX_CTRL_TX_START_R 16:16
`define USB_EP1_TX_CTRL_TX_LEN_DEFAULT 0
`define USB_EP1_TX_CTRL_TX_LEN_B 0
`define USB_EP1_TX_CTRL_TX_LEN_T 10
`define USB_EP1_TX_CTRL_TX_LEN_W 11
`define USB_EP1_TX_CTRL_TX_LEN_R 10:0
`define USB_EP1_RX_CTRL 8'h28
`define USB_EP1_RX_CTRL_RX_FLUSH 1
`define USB_EP1_RX_CTRL_RX_FLUSH_DEFAULT 0
`define USB_EP1_RX_CTRL_RX_FLUSH_B 1
`define USB_EP1_RX_CTRL_RX_FLUSH_T 1
`define USB_EP1_RX_CTRL_RX_FLUSH_W 1
`define USB_EP1_RX_CTRL_RX_FLUSH_R 1:1
`define USB_EP1_RX_CTRL_RX_ACCEPT 0
`define USB_EP1_RX_CTRL_RX_ACCEPT_DEFAULT 0
`define USB_EP1_RX_CTRL_RX_ACCEPT_B 0
`define USB_EP1_RX_CTRL_RX_ACCEPT_T 0
`define USB_EP1_RX_CTRL_RX_ACCEPT_W 1
`define USB_EP1_RX_CTRL_RX_ACCEPT_R 0:0
`define USB_EP1_STS 8'h2c
`define USB_EP1_STS_TX_ERR 20
`define USB_EP1_STS_TX_ERR_DEFAULT 0
`define USB_EP1_STS_TX_ERR_B 20
`define USB_EP1_STS_TX_ERR_T 20
`define USB_EP1_STS_TX_ERR_W 1
`define USB_EP1_STS_TX_ERR_R 20:20
`define USB_EP1_STS_TX_BUSY 19
`define USB_EP1_STS_TX_BUSY_DEFAULT 0
`define USB_EP1_STS_TX_BUSY_B 19
`define USB_EP1_STS_TX_BUSY_T 19
`define USB_EP1_STS_TX_BUSY_W 1
`define USB_EP1_STS_TX_BUSY_R 19:19
`define USB_EP1_STS_RX_ERR 18
`define USB_EP1_STS_RX_ERR_DEFAULT 0
`define USB_EP1_STS_RX_ERR_B 18
`define USB_EP1_STS_RX_ERR_T 18
`define USB_EP1_STS_RX_ERR_W 1
`define USB_EP1_STS_RX_ERR_R 18:18
`define USB_EP1_STS_RX_SETUP 17
`define USB_EP1_STS_RX_SETUP_DEFAULT 0
`define USB_EP1_STS_RX_SETUP_B 17
`define USB_EP1_STS_RX_SETUP_T 17
`define USB_EP1_STS_RX_SETUP_W 1
`define USB_EP1_STS_RX_SETUP_R 17:17
`define USB_EP1_STS_RX_READY 16
`define USB_EP1_STS_RX_READY_DEFAULT 0
`define USB_EP1_STS_RX_READY_B 16
`define USB_EP1_STS_RX_READY_T 16
`define USB_EP1_STS_RX_READY_W 1
`define USB_EP1_STS_RX_READY_R 16:16
`define USB_EP1_STS_RX_COUNT_DEFAULT 0
`define USB_EP1_STS_RX_COUNT_B 0
`define USB_EP1_STS_RX_COUNT_T 10
`define USB_EP1_STS_RX_COUNT_W 11
`define USB_EP1_STS_RX_COUNT_R 10:0
`define USB_EP1_DATA 8'h30
`define USB_EP1_DATA_DATA_DEFAULT 0
`define USB_EP1_DATA_DATA_B 0
`define USB_EP1_DATA_DATA_T 7
`define USB_EP1_DATA_DATA_W 8
`define USB_EP1_DATA_DATA_R 7:0
`define USB_EP2_CFG 8'h34
`define USB_EP2_CFG_INT_RX 3
`define USB_EP2_CFG_INT_RX_DEFAULT 0
`define USB_EP2_CFG_INT_RX_B 3
`define USB_EP2_CFG_INT_RX_T 3
`define USB_EP2_CFG_INT_RX_W 1
`define USB_EP2_CFG_INT_RX_R 3:3
`define USB_EP2_CFG_INT_TX 2
`define USB_EP2_CFG_INT_TX_DEFAULT 0
`define USB_EP2_CFG_INT_TX_B 2
`define USB_EP2_CFG_INT_TX_T 2
`define USB_EP2_CFG_INT_TX_W 1
`define USB_EP2_CFG_INT_TX_R 2:2
`define USB_EP2_CFG_STALL_EP 1
`define USB_EP2_CFG_STALL_EP_DEFAULT 0
`define USB_EP2_CFG_STALL_EP_B 1
`define USB_EP2_CFG_STALL_EP_T 1
`define USB_EP2_CFG_STALL_EP_W 1
`define USB_EP2_CFG_STALL_EP_R 1:1
`define USB_EP2_CFG_ISO 0
`define USB_EP2_CFG_ISO_DEFAULT 0
`define USB_EP2_CFG_ISO_B 0
`define USB_EP2_CFG_ISO_T 0
`define USB_EP2_CFG_ISO_W 1
`define USB_EP2_CFG_ISO_R 0:0
`define USB_EP2_TX_CTRL 8'h38
`define USB_EP2_TX_CTRL_TX_FLUSH 17
`define USB_EP2_TX_CTRL_TX_FLUSH_DEFAULT 0
`define USB_EP2_TX_CTRL_TX_FLUSH_B 17
`define USB_EP2_TX_CTRL_TX_FLUSH_T 17
`define USB_EP2_TX_CTRL_TX_FLUSH_W 1
`define USB_EP2_TX_CTRL_TX_FLUSH_R 17:17
`define USB_EP2_TX_CTRL_TX_START 16
`define USB_EP2_TX_CTRL_TX_START_DEFAULT 0
`define USB_EP2_TX_CTRL_TX_START_B 16
`define USB_EP2_TX_CTRL_TX_START_T 16
`define USB_EP2_TX_CTRL_TX_START_W 1
`define USB_EP2_TX_CTRL_TX_START_R 16:16
`define USB_EP2_TX_CTRL_TX_LEN_DEFAULT 0
`define USB_EP2_TX_CTRL_TX_LEN_B 0
`define USB_EP2_TX_CTRL_TX_LEN_T 10
`define USB_EP2_TX_CTRL_TX_LEN_W 11
`define USB_EP2_TX_CTRL_TX_LEN_R 10:0
`define USB_EP2_RX_CTRL 8'h3c
`define USB_EP2_RX_CTRL_RX_FLUSH 1
`define USB_EP2_RX_CTRL_RX_FLUSH_DEFAULT 0
`define USB_EP2_RX_CTRL_RX_FLUSH_B 1
`define USB_EP2_RX_CTRL_RX_FLUSH_T 1
`define USB_EP2_RX_CTRL_RX_FLUSH_W 1
`define USB_EP2_RX_CTRL_RX_FLUSH_R 1:1
`define USB_EP2_RX_CTRL_RX_ACCEPT 0
`define USB_EP2_RX_CTRL_RX_ACCEPT_DEFAULT 0
`define USB_EP2_RX_CTRL_RX_ACCEPT_B 0
`define USB_EP2_RX_CTRL_RX_ACCEPT_T 0
`define USB_EP2_RX_CTRL_RX_ACCEPT_W 1
`define USB_EP2_RX_CTRL_RX_ACCEPT_R 0:0
`define USB_EP2_STS 8'h40
`define USB_EP2_STS_TX_ERR 20
`define USB_EP2_STS_TX_ERR_DEFAULT 0
`define USB_EP2_STS_TX_ERR_B 20
`define USB_EP2_STS_TX_ERR_T 20
`define USB_EP2_STS_TX_ERR_W 1
`define USB_EP2_STS_TX_ERR_R 20:20
`define USB_EP2_STS_TX_BUSY 19
`define USB_EP2_STS_TX_BUSY_DEFAULT 0
`define USB_EP2_STS_TX_BUSY_B 19
`define USB_EP2_STS_TX_BUSY_T 19
`define USB_EP2_STS_TX_BUSY_W 1
`define USB_EP2_STS_TX_BUSY_R 19:19
`define USB_EP2_STS_RX_ERR 18
`define USB_EP2_STS_RX_ERR_DEFAULT 0
`define USB_EP2_STS_RX_ERR_B 18
`define USB_EP2_STS_RX_ERR_T 18
`define USB_EP2_STS_RX_ERR_W 1
`define USB_EP2_STS_RX_ERR_R 18:18
`define USB_EP2_STS_RX_SETUP 17
`define USB_EP2_STS_RX_SETUP_DEFAULT 0
`define USB_EP2_STS_RX_SETUP_B 17
`define USB_EP2_STS_RX_SETUP_T 17
`define USB_EP2_STS_RX_SETUP_W 1
`define USB_EP2_STS_RX_SETUP_R 17:17
`define USB_EP2_STS_RX_READY 16
`define USB_EP2_STS_RX_READY_DEFAULT 0
`define USB_EP2_STS_RX_READY_B 16
`define USB_EP2_STS_RX_READY_T 16
`define USB_EP2_STS_RX_READY_W 1
`define USB_EP2_STS_RX_READY_R 16:16
`define USB_EP2_STS_RX_COUNT_DEFAULT 0
`define USB_EP2_STS_RX_COUNT_B 0
`define USB_EP2_STS_RX_COUNT_T 10
`define USB_EP2_STS_RX_COUNT_W 11
`define USB_EP2_STS_RX_COUNT_R 10:0
`define USB_EP2_DATA 8'h44
`define USB_EP2_DATA_DATA_DEFAULT 0
`define USB_EP2_DATA_DATA_B 0
`define USB_EP2_DATA_DATA_T 7
`define USB_EP2_DATA_DATA_W 8
`define USB_EP2_DATA_DATA_R 7:0
`define USB_EP3_CFG 8'h48
`define USB_EP3_CFG_INT_RX 3
`define USB_EP3_CFG_INT_RX_DEFAULT 0
`define USB_EP3_CFG_INT_RX_B 3
`define USB_EP3_CFG_INT_RX_T 3
`define USB_EP3_CFG_INT_RX_W 1
`define USB_EP3_CFG_INT_RX_R 3:3
`define USB_EP3_CFG_INT_TX 2
`define USB_EP3_CFG_INT_TX_DEFAULT 0
`define USB_EP3_CFG_INT_TX_B 2
`define USB_EP3_CFG_INT_TX_T 2
`define USB_EP3_CFG_INT_TX_W 1
`define USB_EP3_CFG_INT_TX_R 2:2
`define USB_EP3_CFG_STALL_EP 1
`define USB_EP3_CFG_STALL_EP_DEFAULT 0
`define USB_EP3_CFG_STALL_EP_B 1
`define USB_EP3_CFG_STALL_EP_T 1
`define USB_EP3_CFG_STALL_EP_W 1
`define USB_EP3_CFG_STALL_EP_R 1:1
`define USB_EP3_CFG_ISO 0
`define USB_EP3_CFG_ISO_DEFAULT 0
`define USB_EP3_CFG_ISO_B 0
`define USB_EP3_CFG_ISO_T 0
`define USB_EP3_CFG_ISO_W 1
`define USB_EP3_CFG_ISO_R 0:0
`define USB_EP3_TX_CTRL 8'h4c
`define USB_EP3_TX_CTRL_TX_FLUSH 17
`define USB_EP3_TX_CTRL_TX_FLUSH_DEFAULT 0
`define USB_EP3_TX_CTRL_TX_FLUSH_B 17
`define USB_EP3_TX_CTRL_TX_FLUSH_T 17
`define USB_EP3_TX_CTRL_TX_FLUSH_W 1
`define USB_EP3_TX_CTRL_TX_FLUSH_R 17:17
`define USB_EP3_TX_CTRL_TX_START 16
`define USB_EP3_TX_CTRL_TX_START_DEFAULT 0
`define USB_EP3_TX_CTRL_TX_START_B 16
`define USB_EP3_TX_CTRL_TX_START_T 16
`define USB_EP3_TX_CTRL_TX_START_W 1
`define USB_EP3_TX_CTRL_TX_START_R 16:16
`define USB_EP3_TX_CTRL_TX_LEN_DEFAULT 0
`define USB_EP3_TX_CTRL_TX_LEN_B 0
`define USB_EP3_TX_CTRL_TX_LEN_T 10
`define USB_EP3_TX_CTRL_TX_LEN_W 11
`define USB_EP3_TX_CTRL_TX_LEN_R 10:0
`define USB_EP3_RX_CTRL 8'h50
`define USB_EP3_RX_CTRL_RX_FLUSH 1
`define USB_EP3_RX_CTRL_RX_FLUSH_DEFAULT 0
`define USB_EP3_RX_CTRL_RX_FLUSH_B 1
`define USB_EP3_RX_CTRL_RX_FLUSH_T 1
`define USB_EP3_RX_CTRL_RX_FLUSH_W 1
`define USB_EP3_RX_CTRL_RX_FLUSH_R 1:1
`define USB_EP3_RX_CTRL_RX_ACCEPT 0
`define USB_EP3_RX_CTRL_RX_ACCEPT_DEFAULT 0
`define USB_EP3_RX_CTRL_RX_ACCEPT_B 0
`define USB_EP3_RX_CTRL_RX_ACCEPT_T 0
`define USB_EP3_RX_CTRL_RX_ACCEPT_W 1
`define USB_EP3_RX_CTRL_RX_ACCEPT_R 0:0
`define USB_EP3_STS 8'h54
`define USB_EP3_STS_TX_ERR 20
`define USB_EP3_STS_TX_ERR_DEFAULT 0
`define USB_EP3_STS_TX_ERR_B 20
`define USB_EP3_STS_TX_ERR_T 20
`define USB_EP3_STS_TX_ERR_W 1
`define USB_EP3_STS_TX_ERR_R 20:20
`define USB_EP3_STS_TX_BUSY 19
`define USB_EP3_STS_TX_BUSY_DEFAULT 0
`define USB_EP3_STS_TX_BUSY_B 19
`define USB_EP3_STS_TX_BUSY_T 19
`define USB_EP3_STS_TX_BUSY_W 1
`define USB_EP3_STS_TX_BUSY_R 19:19
`define USB_EP3_STS_RX_ERR 18
`define USB_EP3_STS_RX_ERR_DEFAULT 0
`define USB_EP3_STS_RX_ERR_B 18
`define USB_EP3_STS_RX_ERR_T 18
`define USB_EP3_STS_RX_ERR_W 1
`define USB_EP3_STS_RX_ERR_R 18:18
`define USB_EP3_STS_RX_SETUP 17
`define USB_EP3_STS_RX_SETUP_DEFAULT 0
`define USB_EP3_STS_RX_SETUP_B 17
`define USB_EP3_STS_RX_SETUP_T 17
`define USB_EP3_STS_RX_SETUP_W 1
`define USB_EP3_STS_RX_SETUP_R 17:17
`define USB_EP3_STS_RX_READY 16
`define USB_EP3_STS_RX_READY_DEFAULT 0
`define USB_EP3_STS_RX_READY_B 16
`define USB_EP3_STS_RX_READY_T 16
`define USB_EP3_STS_RX_READY_W 1
`define USB_EP3_STS_RX_READY_R 16:16
`define USB_EP3_STS_RX_COUNT_DEFAULT 0
`define USB_EP3_STS_RX_COUNT_B 0
`define USB_EP3_STS_RX_COUNT_T 10
`define USB_EP3_STS_RX_COUNT_W 11
`define USB_EP3_STS_RX_COUNT_R 10:0
`define USB_EP3_DATA 8'h58
`define USB_EP3_DATA_DATA_DEFAULT 0
`define USB_EP3_DATA_DATA_B 0
`define USB_EP3_DATA_DATA_T 7
`define USB_EP3_DATA_DATA_W 8
`define USB_EP3_DATA_DATA_R 7:0
//-----------------------------------------------------------------
// Module: USB Device Endpoint
//-----------------------------------------------------------------
module usbf_device
(
// Inputs
input clk_i
,input rst_i
,input cfg_awvalid_i
,input [31:0] cfg_awaddr_i
,input cfg_wvalid_i
,input [31:0] cfg_wdata_i
,input [3:0] cfg_wstrb_i
,input cfg_bready_i
,input cfg_arvalid_i
,input [31:0] cfg_araddr_i
,input cfg_rready_i
,input [7:0] utmi_data_in_i
,input utmi_txready_i
,input utmi_rxvalid_i
,input utmi_rxactive_i
,input utmi_rxerror_i
,input [1:0] utmi_linestate_i
// Outputs
,output cfg_awready_o
,output cfg_wready_o
,output cfg_bvalid_o
,output [1:0] cfg_bresp_o
,output cfg_arready_o
,output cfg_rvalid_o
,output [31:0] cfg_rdata_o
,output [1:0] cfg_rresp_o
,output intr_o
,output [7:0] utmi_data_out_o
,output utmi_txvalid_o
,output [1:0] utmi_op_mode_o
,output [1:0] utmi_xcvrselect_o
,output utmi_termselect_o
,output utmi_dppulldown_o
,output utmi_dmpulldown_o
);
//-----------------------------------------------------------------
// Retime write data
//-----------------------------------------------------------------
reg [31:0] wr_data_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
wr_data_q <= 32'b0;
else
wr_data_q <= cfg_wdata_i;
//-----------------------------------------------------------------
// Request Logic
//-----------------------------------------------------------------
wire read_en_w = cfg_arvalid_i & cfg_arready_o;
wire write_en_w = cfg_awvalid_i & cfg_awready_o;
//-----------------------------------------------------------------
// Accept Logic
//-----------------------------------------------------------------
assign cfg_arready_o = ~cfg_rvalid_o;
assign cfg_awready_o = ~cfg_bvalid_o && ~cfg_arvalid_i;
assign cfg_wready_o = cfg_awready_o;
//-----------------------------------------------------------------
// Register usb_func_ctrl
//-----------------------------------------------------------------
reg usb_func_ctrl_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_func_ctrl_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_FUNC_CTRL))
usb_func_ctrl_wr_q <= 1'b1;
else
usb_func_ctrl_wr_q <= 1'b0;
// usb_func_ctrl_hs_chirp_en [internal]
reg usb_func_ctrl_hs_chirp_en_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_func_ctrl_hs_chirp_en_q <= 1'd`USB_FUNC_CTRL_HS_CHIRP_EN_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_FUNC_CTRL))
usb_func_ctrl_hs_chirp_en_q <= cfg_wdata_i[`USB_FUNC_CTRL_HS_CHIRP_EN_R];
wire usb_func_ctrl_hs_chirp_en_out_w = usb_func_ctrl_hs_chirp_en_q;
// usb_func_ctrl_phy_dmpulldown [internal]
reg usb_func_ctrl_phy_dmpulldown_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_func_ctrl_phy_dmpulldown_q <= 1'd`USB_FUNC_CTRL_PHY_DMPULLDOWN_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_FUNC_CTRL))
usb_func_ctrl_phy_dmpulldown_q <= cfg_wdata_i[`USB_FUNC_CTRL_PHY_DMPULLDOWN_R];
wire usb_func_ctrl_phy_dmpulldown_out_w = usb_func_ctrl_phy_dmpulldown_q;
// usb_func_ctrl_phy_dppulldown [internal]
reg usb_func_ctrl_phy_dppulldown_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_func_ctrl_phy_dppulldown_q <= 1'd`USB_FUNC_CTRL_PHY_DPPULLDOWN_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_FUNC_CTRL))
usb_func_ctrl_phy_dppulldown_q <= cfg_wdata_i[`USB_FUNC_CTRL_PHY_DPPULLDOWN_R];
wire usb_func_ctrl_phy_dppulldown_out_w = usb_func_ctrl_phy_dppulldown_q;
// usb_func_ctrl_phy_termselect [internal]
reg usb_func_ctrl_phy_termselect_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_func_ctrl_phy_termselect_q <= 1'd`USB_FUNC_CTRL_PHY_TERMSELECT_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_FUNC_CTRL))
usb_func_ctrl_phy_termselect_q <= cfg_wdata_i[`USB_FUNC_CTRL_PHY_TERMSELECT_R];
wire usb_func_ctrl_phy_termselect_out_w = usb_func_ctrl_phy_termselect_q;
// usb_func_ctrl_phy_xcvrselect [internal]
reg [1:0] usb_func_ctrl_phy_xcvrselect_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_func_ctrl_phy_xcvrselect_q <= 2'd`USB_FUNC_CTRL_PHY_XCVRSELECT_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_FUNC_CTRL))
usb_func_ctrl_phy_xcvrselect_q <= cfg_wdata_i[`USB_FUNC_CTRL_PHY_XCVRSELECT_R];
wire [1:0] usb_func_ctrl_phy_xcvrselect_out_w = usb_func_ctrl_phy_xcvrselect_q;
// usb_func_ctrl_phy_opmode [internal]
reg [1:0] usb_func_ctrl_phy_opmode_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_func_ctrl_phy_opmode_q <= 2'd`USB_FUNC_CTRL_PHY_OPMODE_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_FUNC_CTRL))
usb_func_ctrl_phy_opmode_q <= cfg_wdata_i[`USB_FUNC_CTRL_PHY_OPMODE_R];
wire [1:0] usb_func_ctrl_phy_opmode_out_w = usb_func_ctrl_phy_opmode_q;
// usb_func_ctrl_int_en_sof [internal]
reg usb_func_ctrl_int_en_sof_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_func_ctrl_int_en_sof_q <= 1'd`USB_FUNC_CTRL_INT_EN_SOF_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_FUNC_CTRL))
usb_func_ctrl_int_en_sof_q <= cfg_wdata_i[`USB_FUNC_CTRL_INT_EN_SOF_R];
wire usb_func_ctrl_int_en_sof_out_w = usb_func_ctrl_int_en_sof_q;
//-----------------------------------------------------------------
// Register usb_func_stat
//-----------------------------------------------------------------
reg usb_func_stat_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_func_stat_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_FUNC_STAT))
usb_func_stat_wr_q <= 1'b1;
else
usb_func_stat_wr_q <= 1'b0;
// usb_func_stat_rst [external]
wire usb_func_stat_rst_out_w = wr_data_q[`USB_FUNC_STAT_RST_R];
// usb_func_stat_linestate [external]
wire [1:0] usb_func_stat_linestate_out_w = wr_data_q[`USB_FUNC_STAT_LINESTATE_R];
// usb_func_stat_frame [external]
wire [10:0] usb_func_stat_frame_out_w = wr_data_q[`USB_FUNC_STAT_FRAME_R];
//-----------------------------------------------------------------
// Register usb_func_addr
//-----------------------------------------------------------------
reg usb_func_addr_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_func_addr_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_FUNC_ADDR))
usb_func_addr_wr_q <= 1'b1;
else
usb_func_addr_wr_q <= 1'b0;
// usb_func_addr_dev_addr [internal]
reg [6:0] usb_func_addr_dev_addr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_func_addr_dev_addr_q <= 7'd`USB_FUNC_ADDR_DEV_ADDR_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_FUNC_ADDR))
usb_func_addr_dev_addr_q <= cfg_wdata_i[`USB_FUNC_ADDR_DEV_ADDR_R];
wire [6:0] usb_func_addr_dev_addr_out_w = usb_func_addr_dev_addr_q;
//-----------------------------------------------------------------
// Register usb_ep0_cfg
//-----------------------------------------------------------------
reg usb_ep0_cfg_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep0_cfg_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP0_CFG))
usb_ep0_cfg_wr_q <= 1'b1;
else
usb_ep0_cfg_wr_q <= 1'b0;
// usb_ep0_cfg_int_rx [internal]
reg usb_ep0_cfg_int_rx_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep0_cfg_int_rx_q <= 1'd`USB_EP0_CFG_INT_RX_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP0_CFG))
usb_ep0_cfg_int_rx_q <= cfg_wdata_i[`USB_EP0_CFG_INT_RX_R];
wire usb_ep0_cfg_int_rx_out_w = usb_ep0_cfg_int_rx_q;
// usb_ep0_cfg_int_tx [internal]
reg usb_ep0_cfg_int_tx_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep0_cfg_int_tx_q <= 1'd`USB_EP0_CFG_INT_TX_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP0_CFG))
usb_ep0_cfg_int_tx_q <= cfg_wdata_i[`USB_EP0_CFG_INT_TX_R];
wire usb_ep0_cfg_int_tx_out_w = usb_ep0_cfg_int_tx_q;
// usb_ep0_cfg_stall_ep [clearable]
reg usb_ep0_cfg_stall_ep_q;
wire usb_ep0_cfg_stall_ep_ack_in_w;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep0_cfg_stall_ep_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP0_CFG))
usb_ep0_cfg_stall_ep_q <= cfg_wdata_i[`USB_EP0_CFG_STALL_EP_R];
else if (usb_ep0_cfg_stall_ep_ack_in_w)
usb_ep0_cfg_stall_ep_q <= 1'b0;
wire usb_ep0_cfg_stall_ep_out_w = usb_ep0_cfg_stall_ep_q;
// usb_ep0_cfg_iso [internal]
reg usb_ep0_cfg_iso_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep0_cfg_iso_q <= 1'd`USB_EP0_CFG_ISO_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP0_CFG))
usb_ep0_cfg_iso_q <= cfg_wdata_i[`USB_EP0_CFG_ISO_R];
wire usb_ep0_cfg_iso_out_w = usb_ep0_cfg_iso_q;
//-----------------------------------------------------------------
// Register usb_ep0_tx_ctrl
//-----------------------------------------------------------------
reg usb_ep0_tx_ctrl_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep0_tx_ctrl_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP0_TX_CTRL))
usb_ep0_tx_ctrl_wr_q <= 1'b1;
else
usb_ep0_tx_ctrl_wr_q <= 1'b0;
// usb_ep0_tx_ctrl_tx_flush [auto_clr]
reg usb_ep0_tx_ctrl_tx_flush_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep0_tx_ctrl_tx_flush_q <= 1'd`USB_EP0_TX_CTRL_TX_FLUSH_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP0_TX_CTRL))
usb_ep0_tx_ctrl_tx_flush_q <= cfg_wdata_i[`USB_EP0_TX_CTRL_TX_FLUSH_R];
else
usb_ep0_tx_ctrl_tx_flush_q <= 1'd`USB_EP0_TX_CTRL_TX_FLUSH_DEFAULT;
wire usb_ep0_tx_ctrl_tx_flush_out_w = usb_ep0_tx_ctrl_tx_flush_q;
// usb_ep0_tx_ctrl_tx_start [auto_clr]
reg usb_ep0_tx_ctrl_tx_start_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep0_tx_ctrl_tx_start_q <= 1'd`USB_EP0_TX_CTRL_TX_START_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP0_TX_CTRL))
usb_ep0_tx_ctrl_tx_start_q <= cfg_wdata_i[`USB_EP0_TX_CTRL_TX_START_R];
else
usb_ep0_tx_ctrl_tx_start_q <= 1'd`USB_EP0_TX_CTRL_TX_START_DEFAULT;
wire usb_ep0_tx_ctrl_tx_start_out_w = usb_ep0_tx_ctrl_tx_start_q;
// usb_ep0_tx_ctrl_tx_len [internal]
reg [10:0] usb_ep0_tx_ctrl_tx_len_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep0_tx_ctrl_tx_len_q <= 11'd`USB_EP0_TX_CTRL_TX_LEN_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP0_TX_CTRL))
usb_ep0_tx_ctrl_tx_len_q <= cfg_wdata_i[`USB_EP0_TX_CTRL_TX_LEN_R];
wire [10:0] usb_ep0_tx_ctrl_tx_len_out_w = usb_ep0_tx_ctrl_tx_len_q;
//-----------------------------------------------------------------
// Register usb_ep0_rx_ctrl
//-----------------------------------------------------------------
reg usb_ep0_rx_ctrl_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep0_rx_ctrl_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP0_RX_CTRL))
usb_ep0_rx_ctrl_wr_q <= 1'b1;
else
usb_ep0_rx_ctrl_wr_q <= 1'b0;
// usb_ep0_rx_ctrl_rx_flush [auto_clr]
reg usb_ep0_rx_ctrl_rx_flush_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep0_rx_ctrl_rx_flush_q <= 1'd`USB_EP0_RX_CTRL_RX_FLUSH_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP0_RX_CTRL))
usb_ep0_rx_ctrl_rx_flush_q <= cfg_wdata_i[`USB_EP0_RX_CTRL_RX_FLUSH_R];
else
usb_ep0_rx_ctrl_rx_flush_q <= 1'd`USB_EP0_RX_CTRL_RX_FLUSH_DEFAULT;
wire usb_ep0_rx_ctrl_rx_flush_out_w = usb_ep0_rx_ctrl_rx_flush_q;
// usb_ep0_rx_ctrl_rx_accept [auto_clr]
reg usb_ep0_rx_ctrl_rx_accept_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep0_rx_ctrl_rx_accept_q <= 1'd`USB_EP0_RX_CTRL_RX_ACCEPT_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP0_RX_CTRL))
usb_ep0_rx_ctrl_rx_accept_q <= cfg_wdata_i[`USB_EP0_RX_CTRL_RX_ACCEPT_R];
else
usb_ep0_rx_ctrl_rx_accept_q <= 1'd`USB_EP0_RX_CTRL_RX_ACCEPT_DEFAULT;
wire usb_ep0_rx_ctrl_rx_accept_out_w = usb_ep0_rx_ctrl_rx_accept_q;
//-----------------------------------------------------------------
// Register usb_ep0_sts
//-----------------------------------------------------------------
reg usb_ep0_sts_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep0_sts_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP0_STS))
usb_ep0_sts_wr_q <= 1'b1;
else
usb_ep0_sts_wr_q <= 1'b0;
//-----------------------------------------------------------------
// Register usb_ep0_data
//-----------------------------------------------------------------
reg usb_ep0_data_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep0_data_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP0_DATA))
usb_ep0_data_wr_q <= 1'b1;
else
usb_ep0_data_wr_q <= 1'b0;
// usb_ep0_data_data [external]
wire [7:0] usb_ep0_data_data_out_w = wr_data_q[`USB_EP0_DATA_DATA_R];
//-----------------------------------------------------------------
// Register usb_ep1_cfg
//-----------------------------------------------------------------
reg usb_ep1_cfg_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep1_cfg_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP1_CFG))
usb_ep1_cfg_wr_q <= 1'b1;
else
usb_ep1_cfg_wr_q <= 1'b0;
// usb_ep1_cfg_int_rx [internal]
reg usb_ep1_cfg_int_rx_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep1_cfg_int_rx_q <= 1'd`USB_EP1_CFG_INT_RX_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP1_CFG))
usb_ep1_cfg_int_rx_q <= cfg_wdata_i[`USB_EP1_CFG_INT_RX_R];
wire usb_ep1_cfg_int_rx_out_w = usb_ep1_cfg_int_rx_q;
// usb_ep1_cfg_int_tx [internal]
reg usb_ep1_cfg_int_tx_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep1_cfg_int_tx_q <= 1'd`USB_EP1_CFG_INT_TX_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP1_CFG))
usb_ep1_cfg_int_tx_q <= cfg_wdata_i[`USB_EP1_CFG_INT_TX_R];
wire usb_ep1_cfg_int_tx_out_w = usb_ep1_cfg_int_tx_q;
// usb_ep1_cfg_stall_ep [clearable]
reg usb_ep1_cfg_stall_ep_q;
wire usb_ep1_cfg_stall_ep_ack_in_w;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep1_cfg_stall_ep_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP1_CFG))
usb_ep1_cfg_stall_ep_q <= cfg_wdata_i[`USB_EP1_CFG_STALL_EP_R];
else if (usb_ep1_cfg_stall_ep_ack_in_w)
usb_ep1_cfg_stall_ep_q <= 1'b0;
wire usb_ep1_cfg_stall_ep_out_w = usb_ep1_cfg_stall_ep_q;
// usb_ep1_cfg_iso [internal]
reg usb_ep1_cfg_iso_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep1_cfg_iso_q <= 1'd`USB_EP1_CFG_ISO_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP1_CFG))
usb_ep1_cfg_iso_q <= cfg_wdata_i[`USB_EP1_CFG_ISO_R];
wire usb_ep1_cfg_iso_out_w = usb_ep1_cfg_iso_q;
//-----------------------------------------------------------------
// Register usb_ep1_tx_ctrl
//-----------------------------------------------------------------
reg usb_ep1_tx_ctrl_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep1_tx_ctrl_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP1_TX_CTRL))
usb_ep1_tx_ctrl_wr_q <= 1'b1;
else
usb_ep1_tx_ctrl_wr_q <= 1'b0;
// usb_ep1_tx_ctrl_tx_flush [auto_clr]
reg usb_ep1_tx_ctrl_tx_flush_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep1_tx_ctrl_tx_flush_q <= 1'd`USB_EP1_TX_CTRL_TX_FLUSH_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP1_TX_CTRL))
usb_ep1_tx_ctrl_tx_flush_q <= cfg_wdata_i[`USB_EP1_TX_CTRL_TX_FLUSH_R];
else
usb_ep1_tx_ctrl_tx_flush_q <= 1'd`USB_EP1_TX_CTRL_TX_FLUSH_DEFAULT;
wire usb_ep1_tx_ctrl_tx_flush_out_w = usb_ep1_tx_ctrl_tx_flush_q;
// usb_ep1_tx_ctrl_tx_start [auto_clr]
reg usb_ep1_tx_ctrl_tx_start_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep1_tx_ctrl_tx_start_q <= 1'd`USB_EP1_TX_CTRL_TX_START_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP1_TX_CTRL))
usb_ep1_tx_ctrl_tx_start_q <= cfg_wdata_i[`USB_EP1_TX_CTRL_TX_START_R];
else
usb_ep1_tx_ctrl_tx_start_q <= 1'd`USB_EP1_TX_CTRL_TX_START_DEFAULT;
wire usb_ep1_tx_ctrl_tx_start_out_w = usb_ep1_tx_ctrl_tx_start_q;
// usb_ep1_tx_ctrl_tx_len [internal]
reg [10:0] usb_ep1_tx_ctrl_tx_len_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep1_tx_ctrl_tx_len_q <= 11'd`USB_EP1_TX_CTRL_TX_LEN_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP1_TX_CTRL))
usb_ep1_tx_ctrl_tx_len_q <= cfg_wdata_i[`USB_EP1_TX_CTRL_TX_LEN_R];
wire [10:0] usb_ep1_tx_ctrl_tx_len_out_w = usb_ep1_tx_ctrl_tx_len_q;
//-----------------------------------------------------------------
// Register usb_ep1_rx_ctrl
//-----------------------------------------------------------------
reg usb_ep1_rx_ctrl_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep1_rx_ctrl_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP1_RX_CTRL))
usb_ep1_rx_ctrl_wr_q <= 1'b1;
else
usb_ep1_rx_ctrl_wr_q <= 1'b0;
// usb_ep1_rx_ctrl_rx_flush [auto_clr]
reg usb_ep1_rx_ctrl_rx_flush_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep1_rx_ctrl_rx_flush_q <= 1'd`USB_EP1_RX_CTRL_RX_FLUSH_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP1_RX_CTRL))
usb_ep1_rx_ctrl_rx_flush_q <= cfg_wdata_i[`USB_EP1_RX_CTRL_RX_FLUSH_R];
else
usb_ep1_rx_ctrl_rx_flush_q <= 1'd`USB_EP1_RX_CTRL_RX_FLUSH_DEFAULT;
wire usb_ep1_rx_ctrl_rx_flush_out_w = usb_ep1_rx_ctrl_rx_flush_q;
// usb_ep1_rx_ctrl_rx_accept [auto_clr]
reg usb_ep1_rx_ctrl_rx_accept_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep1_rx_ctrl_rx_accept_q <= 1'd`USB_EP1_RX_CTRL_RX_ACCEPT_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP1_RX_CTRL))
usb_ep1_rx_ctrl_rx_accept_q <= cfg_wdata_i[`USB_EP1_RX_CTRL_RX_ACCEPT_R];
else
usb_ep1_rx_ctrl_rx_accept_q <= 1'd`USB_EP1_RX_CTRL_RX_ACCEPT_DEFAULT;
wire usb_ep1_rx_ctrl_rx_accept_out_w = usb_ep1_rx_ctrl_rx_accept_q;
//-----------------------------------------------------------------
// Register usb_ep1_sts
//-----------------------------------------------------------------
reg usb_ep1_sts_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep1_sts_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP1_STS))
usb_ep1_sts_wr_q <= 1'b1;
else
usb_ep1_sts_wr_q <= 1'b0;
//-----------------------------------------------------------------
// Register usb_ep1_data
//-----------------------------------------------------------------
reg usb_ep1_data_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep1_data_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP1_DATA))
usb_ep1_data_wr_q <= 1'b1;
else
usb_ep1_data_wr_q <= 1'b0;
// usb_ep1_data_data [external]
wire [7:0] usb_ep1_data_data_out_w = wr_data_q[`USB_EP1_DATA_DATA_R];
//-----------------------------------------------------------------
// Register usb_ep2_cfg
//-----------------------------------------------------------------
reg usb_ep2_cfg_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep2_cfg_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP2_CFG))
usb_ep2_cfg_wr_q <= 1'b1;
else
usb_ep2_cfg_wr_q <= 1'b0;
// usb_ep2_cfg_int_rx [internal]
reg usb_ep2_cfg_int_rx_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep2_cfg_int_rx_q <= 1'd`USB_EP2_CFG_INT_RX_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP2_CFG))
usb_ep2_cfg_int_rx_q <= cfg_wdata_i[`USB_EP2_CFG_INT_RX_R];
wire usb_ep2_cfg_int_rx_out_w = usb_ep2_cfg_int_rx_q;
// usb_ep2_cfg_int_tx [internal]
reg usb_ep2_cfg_int_tx_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep2_cfg_int_tx_q <= 1'd`USB_EP2_CFG_INT_TX_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP2_CFG))
usb_ep2_cfg_int_tx_q <= cfg_wdata_i[`USB_EP2_CFG_INT_TX_R];
wire usb_ep2_cfg_int_tx_out_w = usb_ep2_cfg_int_tx_q;
// usb_ep2_cfg_stall_ep [clearable]
reg usb_ep2_cfg_stall_ep_q;
wire usb_ep2_cfg_stall_ep_ack_in_w;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep2_cfg_stall_ep_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP2_CFG))
usb_ep2_cfg_stall_ep_q <= cfg_wdata_i[`USB_EP2_CFG_STALL_EP_R];
else if (usb_ep2_cfg_stall_ep_ack_in_w)
usb_ep2_cfg_stall_ep_q <= 1'b0;
wire usb_ep2_cfg_stall_ep_out_w = usb_ep2_cfg_stall_ep_q;
// usb_ep2_cfg_iso [internal]
reg usb_ep2_cfg_iso_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep2_cfg_iso_q <= 1'd`USB_EP2_CFG_ISO_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP2_CFG))
usb_ep2_cfg_iso_q <= cfg_wdata_i[`USB_EP2_CFG_ISO_R];
wire usb_ep2_cfg_iso_out_w = usb_ep2_cfg_iso_q;
//-----------------------------------------------------------------
// Register usb_ep2_tx_ctrl
//-----------------------------------------------------------------
reg usb_ep2_tx_ctrl_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep2_tx_ctrl_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP2_TX_CTRL))
usb_ep2_tx_ctrl_wr_q <= 1'b1;
else
usb_ep2_tx_ctrl_wr_q <= 1'b0;
// usb_ep2_tx_ctrl_tx_flush [auto_clr]
reg usb_ep2_tx_ctrl_tx_flush_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep2_tx_ctrl_tx_flush_q <= 1'd`USB_EP2_TX_CTRL_TX_FLUSH_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP2_TX_CTRL))
usb_ep2_tx_ctrl_tx_flush_q <= cfg_wdata_i[`USB_EP2_TX_CTRL_TX_FLUSH_R];
else
usb_ep2_tx_ctrl_tx_flush_q <= 1'd`USB_EP2_TX_CTRL_TX_FLUSH_DEFAULT;
wire usb_ep2_tx_ctrl_tx_flush_out_w = usb_ep2_tx_ctrl_tx_flush_q;
// usb_ep2_tx_ctrl_tx_start [auto_clr]
reg usb_ep2_tx_ctrl_tx_start_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep2_tx_ctrl_tx_start_q <= 1'd`USB_EP2_TX_CTRL_TX_START_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP2_TX_CTRL))
usb_ep2_tx_ctrl_tx_start_q <= cfg_wdata_i[`USB_EP2_TX_CTRL_TX_START_R];
else
usb_ep2_tx_ctrl_tx_start_q <= 1'd`USB_EP2_TX_CTRL_TX_START_DEFAULT;
wire usb_ep2_tx_ctrl_tx_start_out_w = usb_ep2_tx_ctrl_tx_start_q;
// usb_ep2_tx_ctrl_tx_len [internal]
reg [10:0] usb_ep2_tx_ctrl_tx_len_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep2_tx_ctrl_tx_len_q <= 11'd`USB_EP2_TX_CTRL_TX_LEN_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP2_TX_CTRL))
usb_ep2_tx_ctrl_tx_len_q <= cfg_wdata_i[`USB_EP2_TX_CTRL_TX_LEN_R];
wire [10:0] usb_ep2_tx_ctrl_tx_len_out_w = usb_ep2_tx_ctrl_tx_len_q;
//-----------------------------------------------------------------
// Register usb_ep2_rx_ctrl
//-----------------------------------------------------------------
reg usb_ep2_rx_ctrl_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep2_rx_ctrl_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP2_RX_CTRL))
usb_ep2_rx_ctrl_wr_q <= 1'b1;
else
usb_ep2_rx_ctrl_wr_q <= 1'b0;
// usb_ep2_rx_ctrl_rx_flush [auto_clr]
reg usb_ep2_rx_ctrl_rx_flush_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep2_rx_ctrl_rx_flush_q <= 1'd`USB_EP2_RX_CTRL_RX_FLUSH_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP2_RX_CTRL))
usb_ep2_rx_ctrl_rx_flush_q <= cfg_wdata_i[`USB_EP2_RX_CTRL_RX_FLUSH_R];
else
usb_ep2_rx_ctrl_rx_flush_q <= 1'd`USB_EP2_RX_CTRL_RX_FLUSH_DEFAULT;
wire usb_ep2_rx_ctrl_rx_flush_out_w = usb_ep2_rx_ctrl_rx_flush_q;
// usb_ep2_rx_ctrl_rx_accept [auto_clr]
reg usb_ep2_rx_ctrl_rx_accept_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep2_rx_ctrl_rx_accept_q <= 1'd`USB_EP2_RX_CTRL_RX_ACCEPT_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP2_RX_CTRL))
usb_ep2_rx_ctrl_rx_accept_q <= cfg_wdata_i[`USB_EP2_RX_CTRL_RX_ACCEPT_R];
else
usb_ep2_rx_ctrl_rx_accept_q <= 1'd`USB_EP2_RX_CTRL_RX_ACCEPT_DEFAULT;
wire usb_ep2_rx_ctrl_rx_accept_out_w = usb_ep2_rx_ctrl_rx_accept_q;
//-----------------------------------------------------------------
// Register usb_ep2_sts
//-----------------------------------------------------------------
reg usb_ep2_sts_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep2_sts_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP2_STS))
usb_ep2_sts_wr_q <= 1'b1;
else
usb_ep2_sts_wr_q <= 1'b0;
//-----------------------------------------------------------------
// Register usb_ep2_data
//-----------------------------------------------------------------
reg usb_ep2_data_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep2_data_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP2_DATA))
usb_ep2_data_wr_q <= 1'b1;
else
usb_ep2_data_wr_q <= 1'b0;
// usb_ep2_data_data [external]
wire [7:0] usb_ep2_data_data_out_w = wr_data_q[`USB_EP2_DATA_DATA_R];
//-----------------------------------------------------------------
// Register usb_ep3_cfg
//-----------------------------------------------------------------
reg usb_ep3_cfg_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep3_cfg_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP3_CFG))
usb_ep3_cfg_wr_q <= 1'b1;
else
usb_ep3_cfg_wr_q <= 1'b0;
// usb_ep3_cfg_int_rx [internal]
reg usb_ep3_cfg_int_rx_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep3_cfg_int_rx_q <= 1'd`USB_EP3_CFG_INT_RX_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP3_CFG))
usb_ep3_cfg_int_rx_q <= cfg_wdata_i[`USB_EP3_CFG_INT_RX_R];
wire usb_ep3_cfg_int_rx_out_w = usb_ep3_cfg_int_rx_q;
// usb_ep3_cfg_int_tx [internal]
reg usb_ep3_cfg_int_tx_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep3_cfg_int_tx_q <= 1'd`USB_EP3_CFG_INT_TX_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP3_CFG))
usb_ep3_cfg_int_tx_q <= cfg_wdata_i[`USB_EP3_CFG_INT_TX_R];
wire usb_ep3_cfg_int_tx_out_w = usb_ep3_cfg_int_tx_q;
// usb_ep3_cfg_stall_ep [clearable]
reg usb_ep3_cfg_stall_ep_q;
wire usb_ep3_cfg_stall_ep_ack_in_w;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep3_cfg_stall_ep_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP3_CFG))
usb_ep3_cfg_stall_ep_q <= cfg_wdata_i[`USB_EP3_CFG_STALL_EP_R];
else if (usb_ep3_cfg_stall_ep_ack_in_w)
usb_ep3_cfg_stall_ep_q <= 1'b0;
wire usb_ep3_cfg_stall_ep_out_w = usb_ep3_cfg_stall_ep_q;
// usb_ep3_cfg_iso [internal]
reg usb_ep3_cfg_iso_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep3_cfg_iso_q <= 1'd`USB_EP3_CFG_ISO_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP3_CFG))
usb_ep3_cfg_iso_q <= cfg_wdata_i[`USB_EP3_CFG_ISO_R];
wire usb_ep3_cfg_iso_out_w = usb_ep3_cfg_iso_q;
//-----------------------------------------------------------------
// Register usb_ep3_tx_ctrl
//-----------------------------------------------------------------
reg usb_ep3_tx_ctrl_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep3_tx_ctrl_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP3_TX_CTRL))
usb_ep3_tx_ctrl_wr_q <= 1'b1;
else
usb_ep3_tx_ctrl_wr_q <= 1'b0;
// usb_ep3_tx_ctrl_tx_flush [auto_clr]
reg usb_ep3_tx_ctrl_tx_flush_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep3_tx_ctrl_tx_flush_q <= 1'd`USB_EP3_TX_CTRL_TX_FLUSH_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP3_TX_CTRL))
usb_ep3_tx_ctrl_tx_flush_q <= cfg_wdata_i[`USB_EP3_TX_CTRL_TX_FLUSH_R];
else
usb_ep3_tx_ctrl_tx_flush_q <= 1'd`USB_EP3_TX_CTRL_TX_FLUSH_DEFAULT;
wire usb_ep3_tx_ctrl_tx_flush_out_w = usb_ep3_tx_ctrl_tx_flush_q;
// usb_ep3_tx_ctrl_tx_start [auto_clr]
reg usb_ep3_tx_ctrl_tx_start_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep3_tx_ctrl_tx_start_q <= 1'd`USB_EP3_TX_CTRL_TX_START_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP3_TX_CTRL))
usb_ep3_tx_ctrl_tx_start_q <= cfg_wdata_i[`USB_EP3_TX_CTRL_TX_START_R];
else
usb_ep3_tx_ctrl_tx_start_q <= 1'd`USB_EP3_TX_CTRL_TX_START_DEFAULT;
wire usb_ep3_tx_ctrl_tx_start_out_w = usb_ep3_tx_ctrl_tx_start_q;
// usb_ep3_tx_ctrl_tx_len [internal]
reg [10:0] usb_ep3_tx_ctrl_tx_len_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep3_tx_ctrl_tx_len_q <= 11'd`USB_EP3_TX_CTRL_TX_LEN_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP3_TX_CTRL))
usb_ep3_tx_ctrl_tx_len_q <= cfg_wdata_i[`USB_EP3_TX_CTRL_TX_LEN_R];
wire [10:0] usb_ep3_tx_ctrl_tx_len_out_w = usb_ep3_tx_ctrl_tx_len_q;
//-----------------------------------------------------------------
// Register usb_ep3_rx_ctrl
//-----------------------------------------------------------------
reg usb_ep3_rx_ctrl_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep3_rx_ctrl_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP3_RX_CTRL))
usb_ep3_rx_ctrl_wr_q <= 1'b1;
else
usb_ep3_rx_ctrl_wr_q <= 1'b0;
// usb_ep3_rx_ctrl_rx_flush [auto_clr]
reg usb_ep3_rx_ctrl_rx_flush_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep3_rx_ctrl_rx_flush_q <= 1'd`USB_EP3_RX_CTRL_RX_FLUSH_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP3_RX_CTRL))
usb_ep3_rx_ctrl_rx_flush_q <= cfg_wdata_i[`USB_EP3_RX_CTRL_RX_FLUSH_R];
else
usb_ep3_rx_ctrl_rx_flush_q <= 1'd`USB_EP3_RX_CTRL_RX_FLUSH_DEFAULT;
wire usb_ep3_rx_ctrl_rx_flush_out_w = usb_ep3_rx_ctrl_rx_flush_q;
// usb_ep3_rx_ctrl_rx_accept [auto_clr]
reg usb_ep3_rx_ctrl_rx_accept_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep3_rx_ctrl_rx_accept_q <= 1'd`USB_EP3_RX_CTRL_RX_ACCEPT_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP3_RX_CTRL))
usb_ep3_rx_ctrl_rx_accept_q <= cfg_wdata_i[`USB_EP3_RX_CTRL_RX_ACCEPT_R];
else
usb_ep3_rx_ctrl_rx_accept_q <= 1'd`USB_EP3_RX_CTRL_RX_ACCEPT_DEFAULT;
wire usb_ep3_rx_ctrl_rx_accept_out_w = usb_ep3_rx_ctrl_rx_accept_q;
//-----------------------------------------------------------------
// Register usb_ep3_sts
//-----------------------------------------------------------------
reg usb_ep3_sts_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep3_sts_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP3_STS))
usb_ep3_sts_wr_q <= 1'b1;
else
usb_ep3_sts_wr_q <= 1'b0;
//-----------------------------------------------------------------
// Register usb_ep3_data
//-----------------------------------------------------------------
reg usb_ep3_data_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_ep3_data_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `USB_EP3_DATA))
usb_ep3_data_wr_q <= 1'b1;
else
usb_ep3_data_wr_q <= 1'b0;
// usb_ep3_data_data [external]
wire [7:0] usb_ep3_data_data_out_w = wr_data_q[`USB_EP3_DATA_DATA_R];
wire usb_func_stat_rst_in_w;
wire [1:0] usb_func_stat_linestate_in_w;
wire [10:0] usb_func_stat_frame_in_w;
wire usb_ep0_sts_tx_err_in_w;
wire usb_ep0_sts_tx_busy_in_w;
wire usb_ep0_sts_rx_err_in_w;
wire usb_ep0_sts_rx_setup_in_w;
wire usb_ep0_sts_rx_ready_in_w;
wire [10:0] usb_ep0_sts_rx_count_in_w;
wire [7:0] usb_ep0_data_data_in_w;
wire usb_ep1_sts_tx_err_in_w;
wire usb_ep1_sts_tx_busy_in_w;
wire usb_ep1_sts_rx_err_in_w;
wire usb_ep1_sts_rx_setup_in_w;
wire usb_ep1_sts_rx_ready_in_w;
wire [10:0] usb_ep1_sts_rx_count_in_w;
wire [7:0] usb_ep1_data_data_in_w;
wire usb_ep2_sts_tx_err_in_w;
wire usb_ep2_sts_tx_busy_in_w;
wire usb_ep2_sts_rx_err_in_w;
wire usb_ep2_sts_rx_setup_in_w;
wire usb_ep2_sts_rx_ready_in_w;
wire [10:0] usb_ep2_sts_rx_count_in_w;
wire [7:0] usb_ep2_data_data_in_w;
wire usb_ep3_sts_tx_err_in_w;
wire usb_ep3_sts_tx_busy_in_w;
wire usb_ep3_sts_rx_err_in_w;
wire usb_ep3_sts_rx_setup_in_w;
wire usb_ep3_sts_rx_ready_in_w;
wire [10:0] usb_ep3_sts_rx_count_in_w;
wire [7:0] usb_ep3_data_data_in_w;
//-----------------------------------------------------------------
// Read mux
//-----------------------------------------------------------------
reg [31:0] data_r;
always @ *
begin
data_r = 32'b0;
case (cfg_araddr_i[7:0])
`USB_FUNC_CTRL:
begin
data_r[`USB_FUNC_CTRL_HS_CHIRP_EN_R] = usb_func_ctrl_hs_chirp_en_q;
data_r[`USB_FUNC_CTRL_PHY_DMPULLDOWN_R] = usb_func_ctrl_phy_dmpulldown_q;
data_r[`USB_FUNC_CTRL_PHY_DPPULLDOWN_R] = usb_func_ctrl_phy_dppulldown_q;
data_r[`USB_FUNC_CTRL_PHY_TERMSELECT_R] = usb_func_ctrl_phy_termselect_q;
data_r[`USB_FUNC_CTRL_PHY_XCVRSELECT_R] = usb_func_ctrl_phy_xcvrselect_q;
data_r[`USB_FUNC_CTRL_PHY_OPMODE_R] = usb_func_ctrl_phy_opmode_q;
data_r[`USB_FUNC_CTRL_INT_EN_SOF_R] = usb_func_ctrl_int_en_sof_q;
end
`USB_FUNC_STAT:
begin
data_r[`USB_FUNC_STAT_RST_R] = usb_func_stat_rst_in_w;
data_r[`USB_FUNC_STAT_LINESTATE_R] = usb_func_stat_linestate_in_w;
data_r[`USB_FUNC_STAT_FRAME_R] = usb_func_stat_frame_in_w;
end
`USB_FUNC_ADDR:
begin
data_r[`USB_FUNC_ADDR_DEV_ADDR_R] = usb_func_addr_dev_addr_q;
end
`USB_EP0_CFG:
begin
data_r[`USB_EP0_CFG_INT_RX_R] = usb_ep0_cfg_int_rx_q;
data_r[`USB_EP0_CFG_INT_TX_R] = usb_ep0_cfg_int_tx_q;
data_r[`USB_EP0_CFG_ISO_R] = usb_ep0_cfg_iso_q;
end
`USB_EP0_TX_CTRL:
begin
data_r[`USB_EP0_TX_CTRL_TX_LEN_R] = usb_ep0_tx_ctrl_tx_len_q;
end
`USB_EP0_STS:
begin
data_r[`USB_EP0_STS_TX_ERR_R] = usb_ep0_sts_tx_err_in_w;
data_r[`USB_EP0_STS_TX_BUSY_R] = usb_ep0_sts_tx_busy_in_w;
data_r[`USB_EP0_STS_RX_ERR_R] = usb_ep0_sts_rx_err_in_w;
data_r[`USB_EP0_STS_RX_SETUP_R] = usb_ep0_sts_rx_setup_in_w;
data_r[`USB_EP0_STS_RX_READY_R] = usb_ep0_sts_rx_ready_in_w;
data_r[`USB_EP0_STS_RX_COUNT_R] = usb_ep0_sts_rx_count_in_w;
end
`USB_EP0_DATA:
begin
data_r[`USB_EP0_DATA_DATA_R] = usb_ep0_data_data_in_w;
end
`USB_EP1_CFG:
begin
data_r[`USB_EP1_CFG_INT_RX_R] = usb_ep1_cfg_int_rx_q;
data_r[`USB_EP1_CFG_INT_TX_R] = usb_ep1_cfg_int_tx_q;
data_r[`USB_EP1_CFG_ISO_R] = usb_ep1_cfg_iso_q;
end
`USB_EP1_TX_CTRL:
begin
data_r[`USB_EP1_TX_CTRL_TX_LEN_R] = usb_ep1_tx_ctrl_tx_len_q;
end
`USB_EP1_STS:
begin
data_r[`USB_EP1_STS_TX_ERR_R] = usb_ep1_sts_tx_err_in_w;
data_r[`USB_EP1_STS_TX_BUSY_R] = usb_ep1_sts_tx_busy_in_w;
data_r[`USB_EP1_STS_RX_ERR_R] = usb_ep1_sts_rx_err_in_w;
data_r[`USB_EP1_STS_RX_SETUP_R] = usb_ep1_sts_rx_setup_in_w;
data_r[`USB_EP1_STS_RX_READY_R] = usb_ep1_sts_rx_ready_in_w;
data_r[`USB_EP1_STS_RX_COUNT_R] = usb_ep1_sts_rx_count_in_w;
end
`USB_EP1_DATA:
begin
data_r[`USB_EP1_DATA_DATA_R] = usb_ep1_data_data_in_w;
end
`USB_EP2_CFG:
begin
data_r[`USB_EP2_CFG_INT_RX_R] = usb_ep2_cfg_int_rx_q;
data_r[`USB_EP2_CFG_INT_TX_R] = usb_ep2_cfg_int_tx_q;
data_r[`USB_EP2_CFG_ISO_R] = usb_ep2_cfg_iso_q;
end
`USB_EP2_TX_CTRL:
begin
data_r[`USB_EP2_TX_CTRL_TX_LEN_R] = usb_ep2_tx_ctrl_tx_len_q;
end
`USB_EP2_STS:
begin
data_r[`USB_EP2_STS_TX_ERR_R] = usb_ep2_sts_tx_err_in_w;
data_r[`USB_EP2_STS_TX_BUSY_R] = usb_ep2_sts_tx_busy_in_w;
data_r[`USB_EP2_STS_RX_ERR_R] = usb_ep2_sts_rx_err_in_w;
data_r[`USB_EP2_STS_RX_SETUP_R] = usb_ep2_sts_rx_setup_in_w;
data_r[`USB_EP2_STS_RX_READY_R] = usb_ep2_sts_rx_ready_in_w;
data_r[`USB_EP2_STS_RX_COUNT_R] = usb_ep2_sts_rx_count_in_w;
end
`USB_EP2_DATA:
begin
data_r[`USB_EP2_DATA_DATA_R] = usb_ep2_data_data_in_w;
end
`USB_EP3_CFG:
begin
data_r[`USB_EP3_CFG_INT_RX_R] = usb_ep3_cfg_int_rx_q;
data_r[`USB_EP3_CFG_INT_TX_R] = usb_ep3_cfg_int_tx_q;
data_r[`USB_EP3_CFG_ISO_R] = usb_ep3_cfg_iso_q;
end
`USB_EP3_TX_CTRL:
begin
data_r[`USB_EP3_TX_CTRL_TX_LEN_R] = usb_ep3_tx_ctrl_tx_len_q;
end
`USB_EP3_STS:
begin
data_r[`USB_EP3_STS_TX_ERR_R] = usb_ep3_sts_tx_err_in_w;
data_r[`USB_EP3_STS_TX_BUSY_R] = usb_ep3_sts_tx_busy_in_w;
data_r[`USB_EP3_STS_RX_ERR_R] = usb_ep3_sts_rx_err_in_w;
data_r[`USB_EP3_STS_RX_SETUP_R] = usb_ep3_sts_rx_setup_in_w;
data_r[`USB_EP3_STS_RX_READY_R] = usb_ep3_sts_rx_ready_in_w;
data_r[`USB_EP3_STS_RX_COUNT_R] = usb_ep3_sts_rx_count_in_w;
end
`USB_EP3_DATA:
begin
data_r[`USB_EP3_DATA_DATA_R] = usb_ep3_data_data_in_w;
end
default :
data_r = 32'b0;
endcase
end
//-----------------------------------------------------------------
// RVALID
//-----------------------------------------------------------------
reg rvalid_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
rvalid_q <= 1'b0;
else if (read_en_w)
rvalid_q <= 1'b1;
else if (cfg_rready_i)
rvalid_q <= 1'b0;
assign cfg_rvalid_o = rvalid_q;
//-----------------------------------------------------------------
// Retime read response
//-----------------------------------------------------------------
reg [31:0] rd_data_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
rd_data_q <= 32'b0;
else if (!cfg_rvalid_o || cfg_rready_i)
rd_data_q <= data_r;
assign cfg_rdata_o = rd_data_q;
assign cfg_rresp_o = 2'b0;
//-----------------------------------------------------------------
// BVALID
//-----------------------------------------------------------------
reg bvalid_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
bvalid_q <= 1'b0;
else if (write_en_w)
bvalid_q <= 1'b1;
else if (cfg_bready_i)
bvalid_q <= 1'b0;
assign cfg_bvalid_o = bvalid_q;
assign cfg_bresp_o = 2'b0;
wire usb_ep0_data_rd_req_w = read_en_w & (cfg_araddr_i[7:0] == `USB_EP0_DATA);
wire usb_ep1_data_rd_req_w = read_en_w & (cfg_araddr_i[7:0] == `USB_EP1_DATA);
wire usb_ep2_data_rd_req_w = read_en_w & (cfg_araddr_i[7:0] == `USB_EP2_DATA);
wire usb_ep3_data_rd_req_w = read_en_w & (cfg_araddr_i[7:0] == `USB_EP3_DATA);
wire usb_func_stat_wr_req_w = usb_func_stat_wr_q;
wire usb_ep0_data_wr_req_w = usb_ep0_data_wr_q;
wire usb_ep1_data_wr_req_w = usb_ep1_data_wr_q;
wire usb_ep2_data_wr_req_w = usb_ep2_data_wr_q;
wire usb_ep3_data_wr_req_w = usb_ep3_data_wr_q;
//-----------------------------------------------------------------
// Wires
//-----------------------------------------------------------------
wire stat_rst_w;
wire [10:0] stat_frame_w;
wire stat_rst_clr_w = usb_func_stat_rst_out_w;
wire stat_wr_req_w = usb_func_stat_wr_req_w;
wire usb_ep0_tx_rd_w;
wire [7:0] usb_ep0_tx_data_w;
wire usb_ep0_tx_empty_w;
wire usb_ep0_rx_wr_w;
wire [7:0] usb_ep0_rx_data_w;
wire usb_ep0_rx_full_w;
wire usb_ep1_tx_rd_w;
wire [7:0] usb_ep1_tx_data_w;
wire usb_ep1_tx_empty_w;
wire usb_ep1_rx_wr_w;
wire [7:0] usb_ep1_rx_data_w;
wire usb_ep1_rx_full_w;
wire usb_ep2_tx_rd_w;
wire [7:0] usb_ep2_tx_data_w;
wire usb_ep2_tx_empty_w;
wire usb_ep2_rx_wr_w;
wire [7:0] usb_ep2_rx_data_w;
wire usb_ep2_rx_full_w;
wire usb_ep3_tx_rd_w;
wire [7:0] usb_ep3_tx_data_w;
wire usb_ep3_tx_empty_w;
wire usb_ep3_rx_wr_w;
wire [7:0] usb_ep3_rx_data_w;
wire usb_ep3_rx_full_w;
// Rx SIE Interface (shared)
wire rx_strb_w;
wire [7:0] rx_data_w;
wire rx_last_w;
wire rx_crc_err_w;
// EP0 Rx SIE Interface
wire ep0_rx_space_w;
wire ep0_rx_valid_w;
wire ep0_rx_setup_w;
// EP0 Tx SIE Interface
wire ep0_tx_ready_w;
wire ep0_tx_data_valid_w;
wire ep0_tx_data_strb_w;
wire [7:0] ep0_tx_data_w;
wire ep0_tx_data_last_w;
wire ep0_tx_data_accept_w;
// EP1 Rx SIE Interface
wire ep1_rx_space_w;
wire ep1_rx_valid_w;
wire ep1_rx_setup_w;
// EP1 Tx SIE Interface
wire ep1_tx_ready_w;
wire ep1_tx_data_valid_w;
wire ep1_tx_data_strb_w;
wire [7:0] ep1_tx_data_w;
wire ep1_tx_data_last_w;
wire ep1_tx_data_accept_w;
// EP2 Rx SIE Interface
wire ep2_rx_space_w;
wire ep2_rx_valid_w;
wire ep2_rx_setup_w;
// EP2 Tx SIE Interface
wire ep2_tx_ready_w;
wire ep2_tx_data_valid_w;
wire ep2_tx_data_strb_w;
wire [7:0] ep2_tx_data_w;
wire ep2_tx_data_last_w;
wire ep2_tx_data_accept_w;
// EP3 Rx SIE Interface
wire ep3_rx_space_w;
wire ep3_rx_valid_w;
wire ep3_rx_setup_w;
// EP3 Tx SIE Interface
wire ep3_tx_ready_w;
wire ep3_tx_data_valid_w;
wire ep3_tx_data_strb_w;
wire [7:0] ep3_tx_data_w;
wire ep3_tx_data_last_w;
wire ep3_tx_data_accept_w;
// Transceiver Control
assign utmi_dmpulldown_o = usb_func_ctrl_phy_dmpulldown_out_w;
assign utmi_dppulldown_o = usb_func_ctrl_phy_dppulldown_out_w;
assign utmi_termselect_o = usb_func_ctrl_phy_termselect_out_w;
assign utmi_xcvrselect_o = usb_func_ctrl_phy_xcvrselect_out_w;
assign utmi_op_mode_o = usb_func_ctrl_phy_opmode_out_w;
// Status
assign usb_func_stat_rst_in_w = stat_rst_w;
assign usb_func_stat_linestate_in_w = utmi_linestate_i;
assign usb_func_stat_frame_in_w = stat_frame_w;
//-----------------------------------------------------------------
// Core
//-----------------------------------------------------------------
usbf_device_core
u_core
(
.clk_i(clk_i),
.rst_i(rst_i),
.intr_o(intr_o),
// UTMI interface
.utmi_data_o(utmi_data_out_o),
.utmi_data_i(utmi_data_in_i),
.utmi_txvalid_o(utmi_txvalid_o),
.utmi_txready_i(utmi_txready_i),
.utmi_rxvalid_i(utmi_rxvalid_i),
.utmi_rxactive_i(utmi_rxactive_i),
.utmi_rxerror_i(utmi_rxerror_i),
.utmi_linestate_i(utmi_linestate_i),
.reg_chirp_en_i(usb_func_ctrl_hs_chirp_en_out_w),
.reg_int_en_sof_i(usb_func_ctrl_int_en_sof_out_w),
.reg_dev_addr_i(usb_func_addr_dev_addr_out_w),
// Rx SIE Interface (shared)
.rx_strb_o(rx_strb_w),
.rx_data_o(rx_data_w),
.rx_last_o(rx_last_w),
.rx_crc_err_o(rx_crc_err_w),
// EP0 Config
.ep0_iso_i(usb_ep0_cfg_iso_out_w),
.ep0_stall_i(usb_ep0_cfg_stall_ep_out_w),
.ep0_cfg_int_rx_i(usb_ep0_cfg_int_rx_out_w),
.ep0_cfg_int_tx_i(usb_ep0_cfg_int_tx_out_w),
// EP0 Rx SIE Interface
.ep0_rx_setup_o(ep0_rx_setup_w),
.ep0_rx_valid_o(ep0_rx_valid_w),
.ep0_rx_space_i(ep0_rx_space_w),
// EP0 Tx SIE Interface
.ep0_tx_ready_i(ep0_tx_ready_w),
.ep0_tx_data_valid_i(ep0_tx_data_valid_w),
.ep0_tx_data_strb_i(ep0_tx_data_strb_w),
.ep0_tx_data_i(ep0_tx_data_w),
.ep0_tx_data_last_i(ep0_tx_data_last_w),
.ep0_tx_data_accept_o(ep0_tx_data_accept_w),
// EP1 Config
.ep1_iso_i(usb_ep1_cfg_iso_out_w),
.ep1_stall_i(usb_ep1_cfg_stall_ep_out_w),
.ep1_cfg_int_rx_i(usb_ep1_cfg_int_rx_out_w),
.ep1_cfg_int_tx_i(usb_ep1_cfg_int_tx_out_w),
// EP1 Rx SIE Interface
.ep1_rx_setup_o(ep1_rx_setup_w),
.ep1_rx_valid_o(ep1_rx_valid_w),
.ep1_rx_space_i(ep1_rx_space_w),
// EP1 Tx SIE Interface
.ep1_tx_ready_i(ep1_tx_ready_w),
.ep1_tx_data_valid_i(ep1_tx_data_valid_w),
.ep1_tx_data_strb_i(ep1_tx_data_strb_w),
.ep1_tx_data_i(ep1_tx_data_w),
.ep1_tx_data_last_i(ep1_tx_data_last_w),
.ep1_tx_data_accept_o(ep1_tx_data_accept_w),
// EP2 Config
.ep2_iso_i(usb_ep2_cfg_iso_out_w),
.ep2_stall_i(usb_ep2_cfg_stall_ep_out_w),
.ep2_cfg_int_rx_i(usb_ep2_cfg_int_rx_out_w),
.ep2_cfg_int_tx_i(usb_ep2_cfg_int_tx_out_w),
// EP2 Rx SIE Interface
.ep2_rx_setup_o(ep2_rx_setup_w),
.ep2_rx_valid_o(ep2_rx_valid_w),
.ep2_rx_space_i(ep2_rx_space_w),
// EP2 Tx SIE Interface
.ep2_tx_ready_i(ep2_tx_ready_w),
.ep2_tx_data_valid_i(ep2_tx_data_valid_w),
.ep2_tx_data_strb_i(ep2_tx_data_strb_w),
.ep2_tx_data_i(ep2_tx_data_w),
.ep2_tx_data_last_i(ep2_tx_data_last_w),
.ep2_tx_data_accept_o(ep2_tx_data_accept_w),
// EP3 Config
.ep3_iso_i(usb_ep3_cfg_iso_out_w),
.ep3_stall_i(usb_ep3_cfg_stall_ep_out_w),
.ep3_cfg_int_rx_i(usb_ep3_cfg_int_rx_out_w),
.ep3_cfg_int_tx_i(usb_ep3_cfg_int_tx_out_w),
// EP3 Rx SIE Interface
.ep3_rx_setup_o(ep3_rx_setup_w),
.ep3_rx_valid_o(ep3_rx_valid_w),
.ep3_rx_space_i(ep3_rx_space_w),
// EP3 Tx SIE Interface
.ep3_tx_ready_i(ep3_tx_ready_w),
.ep3_tx_data_valid_i(ep3_tx_data_valid_w),
.ep3_tx_data_strb_i(ep3_tx_data_strb_w),
.ep3_tx_data_i(ep3_tx_data_w),
.ep3_tx_data_last_i(ep3_tx_data_last_w),
.ep3_tx_data_accept_o(ep3_tx_data_accept_w),
// Status
.reg_sts_rst_clr_i(stat_rst_clr_w & stat_wr_req_w),
.reg_sts_rst_o(stat_rst_w),
.reg_sts_frame_num_o(stat_frame_w)
);
assign usb_ep0_cfg_stall_ep_ack_in_w = ep0_rx_setup_w;
assign usb_ep1_cfg_stall_ep_ack_in_w = ep1_rx_setup_w;
assign usb_ep2_cfg_stall_ep_ack_in_w = ep2_rx_setup_w;
assign usb_ep3_cfg_stall_ep_ack_in_w = ep3_rx_setup_w;
//-----------------------------------------------------------------
// FIFOs
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Endpoint 0: Host -> Device
//-----------------------------------------------------------------
usbf_fifo
#(
.WIDTH(8),
.DEPTH(8),
.ADDR_W(3)
)
u_fifo_rx_ep0
(
.clk_i(clk_i),
.rst_i(rst_i),
.data_i(usb_ep0_rx_data_w),
.push_i(usb_ep0_rx_wr_w),
.flush_i(usb_ep0_rx_ctrl_rx_flush_out_w),
.full_o(usb_ep0_rx_full_w),
.empty_o(),
// Output to register block
.data_o(usb_ep0_data_data_in_w),
.pop_i(usb_ep0_data_rd_req_w)
);
//-----------------------------------------------------------------
// Endpoint 0: Device -> Host
//-----------------------------------------------------------------
usbf_fifo
#(
.WIDTH(8),
.DEPTH(8),
.ADDR_W(3)
)
u_fifo_tx_ep0
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input from register block
.data_i(usb_ep0_data_data_out_w),
.push_i(usb_ep0_data_wr_req_w),
.flush_i(usb_ep0_tx_ctrl_tx_flush_out_w),
.full_o(),
.empty_o(usb_ep0_tx_empty_w),
.data_o(usb_ep0_tx_data_w),
.pop_i(usb_ep0_tx_rd_w)
);
//-----------------------------------------------------------------
// Endpoint 1: Host -> Device
//-----------------------------------------------------------------
usbf_fifo
#(
.WIDTH(8),
.DEPTH(64),
.ADDR_W(6)
)
u_fifo_rx_ep1
(
.clk_i(clk_i),
.rst_i(rst_i),
.data_i(usb_ep1_rx_data_w),
.push_i(usb_ep1_rx_wr_w),
.flush_i(usb_ep1_rx_ctrl_rx_flush_out_w),
.full_o(usb_ep1_rx_full_w),
.empty_o(),
// Output to register block
.data_o(usb_ep1_data_data_in_w),
.pop_i(usb_ep1_data_rd_req_w)
);
//-----------------------------------------------------------------
// Endpoint 1: Device -> Host
//-----------------------------------------------------------------
usbf_fifo
#(
.WIDTH(8),
.DEPTH(64),
.ADDR_W(6)
)
u_fifo_tx_ep1
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input from register block
.data_i(usb_ep1_data_data_out_w),
.push_i(usb_ep1_data_wr_req_w),
.flush_i(usb_ep1_tx_ctrl_tx_flush_out_w),
.full_o(),
.empty_o(usb_ep1_tx_empty_w),
.data_o(usb_ep1_tx_data_w),
.pop_i(usb_ep1_tx_rd_w)
);
//-----------------------------------------------------------------
// Endpoint 2: Host -> Device
//-----------------------------------------------------------------
usbf_fifo
#(
.WIDTH(8),
.DEPTH(64),
.ADDR_W(6)
)
u_fifo_rx_ep2
(
.clk_i(clk_i),
.rst_i(rst_i),
.data_i(usb_ep2_rx_data_w),
.push_i(usb_ep2_rx_wr_w),
.flush_i(usb_ep2_rx_ctrl_rx_flush_out_w),
.full_o(usb_ep2_rx_full_w),
.empty_o(),
// Output to register block
.data_o(usb_ep2_data_data_in_w),
.pop_i(usb_ep2_data_rd_req_w)
);
//-----------------------------------------------------------------
// Endpoint 2: Device -> Host
//-----------------------------------------------------------------
usbf_fifo
#(
.WIDTH(8),
.DEPTH(64),
.ADDR_W(6)
)
u_fifo_tx_ep2
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input from register block
.data_i(usb_ep2_data_data_out_w),
.push_i(usb_ep2_data_wr_req_w),
.flush_i(usb_ep2_tx_ctrl_tx_flush_out_w),
.full_o(),
.empty_o(usb_ep2_tx_empty_w),
.data_o(usb_ep2_tx_data_w),
.pop_i(usb_ep2_tx_rd_w)
);
//-----------------------------------------------------------------
// Endpoint 3: Host -> Device
//-----------------------------------------------------------------
usbf_fifo
#(
.WIDTH(8),
.DEPTH(64),
.ADDR_W(6)
)
u_fifo_rx_ep3
(
.clk_i(clk_i),
.rst_i(rst_i),
.data_i(usb_ep3_rx_data_w),
.push_i(usb_ep3_rx_wr_w),
.flush_i(usb_ep3_rx_ctrl_rx_flush_out_w),
.full_o(usb_ep3_rx_full_w),
.empty_o(),
// Output to register block
.data_o(usb_ep3_data_data_in_w),
.pop_i(usb_ep3_data_rd_req_w)
);
//-----------------------------------------------------------------
// Endpoint 3: Device -> Host
//-----------------------------------------------------------------
usbf_fifo
#(
.WIDTH(8),
.DEPTH(64),
.ADDR_W(6)
)
u_fifo_tx_ep3
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input from register block
.data_i(usb_ep3_data_data_out_w),
.push_i(usb_ep3_data_wr_req_w),
.flush_i(usb_ep3_tx_ctrl_tx_flush_out_w),
.full_o(),
.empty_o(usb_ep3_tx_empty_w),
.data_o(usb_ep3_tx_data_w),
.pop_i(usb_ep3_tx_rd_w)
);
//-----------------------------------------------------------------
// Endpoint 0: Control
//-----------------------------------------------------------------
usbf_sie_ep
u_ep0
(
.clk_i(clk_i),
.rst_i(rst_i),
// Rx SIE Interface
.rx_space_o(ep0_rx_space_w),
.rx_valid_i(ep0_rx_valid_w),
.rx_setup_i(ep0_rx_setup_w),
.rx_strb_i(rx_strb_w),
.rx_data_i(rx_data_w),
.rx_last_i(rx_last_w),
.rx_crc_err_i(rx_crc_err_w),
// Rx FIFO Interface
.rx_push_o(usb_ep0_rx_wr_w),
.rx_data_o(usb_ep0_rx_data_w),
.rx_full_i(usb_ep0_rx_full_w),
// Rx Register Interface
.rx_length_o(usb_ep0_sts_rx_count_in_w),
.rx_ready_o(usb_ep0_sts_rx_ready_in_w),
.rx_err_o(usb_ep0_sts_rx_err_in_w),
.rx_setup_o(usb_ep0_sts_rx_setup_in_w),
.rx_ack_i(usb_ep0_rx_ctrl_rx_accept_out_w),
// Tx FIFO Interface
.tx_pop_o(usb_ep0_tx_rd_w),
.tx_data_i(usb_ep0_tx_data_w),
.tx_empty_i(usb_ep0_tx_empty_w),
// Tx Register Interface
.tx_flush_i(usb_ep0_tx_ctrl_tx_flush_out_w),
.tx_length_i(usb_ep0_tx_ctrl_tx_len_out_w),
.tx_start_i(usb_ep0_tx_ctrl_tx_start_out_w),
.tx_busy_o(usb_ep0_sts_tx_busy_in_w),
.tx_err_o(usb_ep0_sts_tx_err_in_w),
// Tx SIE Interface
.tx_ready_o(ep0_tx_ready_w),
.tx_data_valid_o(ep0_tx_data_valid_w),
.tx_data_strb_o(ep0_tx_data_strb_w),
.tx_data_o(ep0_tx_data_w),
.tx_data_last_o(ep0_tx_data_last_w),
.tx_data_accept_i(ep0_tx_data_accept_w)
);
//-----------------------------------------------------------------
// Endpoint 1: Control
//-----------------------------------------------------------------
usbf_sie_ep
u_ep1
(
.clk_i(clk_i),
.rst_i(rst_i),
// Rx SIE Interface
.rx_space_o(ep1_rx_space_w),
.rx_valid_i(ep1_rx_valid_w),
.rx_setup_i(ep1_rx_setup_w),
.rx_strb_i(rx_strb_w),
.rx_data_i(rx_data_w),
.rx_last_i(rx_last_w),
.rx_crc_err_i(rx_crc_err_w),
// Rx FIFO Interface
.rx_push_o(usb_ep1_rx_wr_w),
.rx_data_o(usb_ep1_rx_data_w),
.rx_full_i(usb_ep1_rx_full_w),
// Rx Register Interface
.rx_length_o(usb_ep1_sts_rx_count_in_w),
.rx_ready_o(usb_ep1_sts_rx_ready_in_w),
.rx_err_o(usb_ep1_sts_rx_err_in_w),
.rx_setup_o(usb_ep1_sts_rx_setup_in_w),
.rx_ack_i(usb_ep1_rx_ctrl_rx_accept_out_w),
// Tx FIFO Interface
.tx_pop_o(usb_ep1_tx_rd_w),
.tx_data_i(usb_ep1_tx_data_w),
.tx_empty_i(usb_ep1_tx_empty_w),
// Tx Register Interface
.tx_flush_i(usb_ep1_tx_ctrl_tx_flush_out_w),
.tx_length_i(usb_ep1_tx_ctrl_tx_len_out_w),
.tx_start_i(usb_ep1_tx_ctrl_tx_start_out_w),
.tx_busy_o(usb_ep1_sts_tx_busy_in_w),
.tx_err_o(usb_ep1_sts_tx_err_in_w),
// Tx SIE Interface
.tx_ready_o(ep1_tx_ready_w),
.tx_data_valid_o(ep1_tx_data_valid_w),
.tx_data_strb_o(ep1_tx_data_strb_w),
.tx_data_o(ep1_tx_data_w),
.tx_data_last_o(ep1_tx_data_last_w),
.tx_data_accept_i(ep1_tx_data_accept_w)
);
//-----------------------------------------------------------------
// Endpoint 2: Control
//-----------------------------------------------------------------
usbf_sie_ep
u_ep2
(
.clk_i(clk_i),
.rst_i(rst_i),
// Rx SIE Interface
.rx_space_o(ep2_rx_space_w),
.rx_valid_i(ep2_rx_valid_w),
.rx_setup_i(ep2_rx_setup_w),
.rx_strb_i(rx_strb_w),
.rx_data_i(rx_data_w),
.rx_last_i(rx_last_w),
.rx_crc_err_i(rx_crc_err_w),
// Rx FIFO Interface
.rx_push_o(usb_ep2_rx_wr_w),
.rx_data_o(usb_ep2_rx_data_w),
.rx_full_i(usb_ep2_rx_full_w),
// Rx Register Interface
.rx_length_o(usb_ep2_sts_rx_count_in_w),
.rx_ready_o(usb_ep2_sts_rx_ready_in_w),
.rx_err_o(usb_ep2_sts_rx_err_in_w),
.rx_setup_o(usb_ep2_sts_rx_setup_in_w),
.rx_ack_i(usb_ep2_rx_ctrl_rx_accept_out_w),
// Tx FIFO Interface
.tx_pop_o(usb_ep2_tx_rd_w),
.tx_data_i(usb_ep2_tx_data_w),
.tx_empty_i(usb_ep2_tx_empty_w),
// Tx Register Interface
.tx_flush_i(usb_ep2_tx_ctrl_tx_flush_out_w),
.tx_length_i(usb_ep2_tx_ctrl_tx_len_out_w),
.tx_start_i(usb_ep2_tx_ctrl_tx_start_out_w),
.tx_busy_o(usb_ep2_sts_tx_busy_in_w),
.tx_err_o(usb_ep2_sts_tx_err_in_w),
// Tx SIE Interface
.tx_ready_o(ep2_tx_ready_w),
.tx_data_valid_o(ep2_tx_data_valid_w),
.tx_data_strb_o(ep2_tx_data_strb_w),
.tx_data_o(ep2_tx_data_w),
.tx_data_last_o(ep2_tx_data_last_w),
.tx_data_accept_i(ep2_tx_data_accept_w)
);
//-----------------------------------------------------------------
// Endpoint 3: Control
//-----------------------------------------------------------------
usbf_sie_ep
u_ep3
(
.clk_i(clk_i),
.rst_i(rst_i),
// Rx SIE Interface
.rx_space_o(ep3_rx_space_w),
.rx_valid_i(ep3_rx_valid_w),
.rx_setup_i(ep3_rx_setup_w),
.rx_strb_i(rx_strb_w),
.rx_data_i(rx_data_w),
.rx_last_i(rx_last_w),
.rx_crc_err_i(rx_crc_err_w),
// Rx FIFO Interface
.rx_push_o(usb_ep3_rx_wr_w),
.rx_data_o(usb_ep3_rx_data_w),
.rx_full_i(usb_ep3_rx_full_w),
// Rx Register Interface
.rx_length_o(usb_ep3_sts_rx_count_in_w),
.rx_ready_o(usb_ep3_sts_rx_ready_in_w),
.rx_err_o(usb_ep3_sts_rx_err_in_w),
.rx_setup_o(usb_ep3_sts_rx_setup_in_w),
.rx_ack_i(usb_ep3_rx_ctrl_rx_accept_out_w),
// Tx FIFO Interface
.tx_pop_o(usb_ep3_tx_rd_w),
.tx_data_i(usb_ep3_tx_data_w),
.tx_empty_i(usb_ep3_tx_empty_w),
// Tx Register Interface
.tx_flush_i(usb_ep3_tx_ctrl_tx_flush_out_w),
.tx_length_i(usb_ep3_tx_ctrl_tx_len_out_w),
.tx_start_i(usb_ep3_tx_ctrl_tx_start_out_w),
.tx_busy_o(usb_ep3_sts_tx_busy_in_w),
.tx_err_o(usb_ep3_sts_tx_err_in_w),
// Tx SIE Interface
.tx_ready_o(ep3_tx_ready_w),
.tx_data_valid_o(ep3_tx_data_valid_w),
.tx_data_strb_o(ep3_tx_data_strb_w),
.tx_data_o(ep3_tx_data_w),
.tx_data_last_o(ep3_tx_data_last_w),
.tx_data_accept_i(ep3_tx_data_accept_w)
);
endmodule
module usbf_device_core
(
// Inputs
input clk_i
,input rst_i
,input [ 7:0] utmi_data_i
,input utmi_txready_i
,input utmi_rxvalid_i
,input utmi_rxactive_i
,input utmi_rxerror_i
,input [ 1:0] utmi_linestate_i
,input ep0_stall_i
,input ep0_iso_i
,input ep0_cfg_int_rx_i
,input ep0_cfg_int_tx_i
,input ep0_rx_space_i
,input ep0_tx_ready_i
,input ep0_tx_data_valid_i
,input ep0_tx_data_strb_i
,input [ 7:0] ep0_tx_data_i
,input ep0_tx_data_last_i
,input ep1_stall_i
,input ep1_iso_i
,input ep1_cfg_int_rx_i
,input ep1_cfg_int_tx_i
,input ep1_rx_space_i
,input ep1_tx_ready_i
,input ep1_tx_data_valid_i
,input ep1_tx_data_strb_i
,input [ 7:0] ep1_tx_data_i
,input ep1_tx_data_last_i
,input ep2_stall_i
,input ep2_iso_i
,input ep2_cfg_int_rx_i
,input ep2_cfg_int_tx_i
,input ep2_rx_space_i
,input ep2_tx_ready_i
,input ep2_tx_data_valid_i
,input ep2_tx_data_strb_i
,input [ 7:0] ep2_tx_data_i
,input ep2_tx_data_last_i
,input ep3_stall_i
,input ep3_iso_i
,input ep3_cfg_int_rx_i
,input ep3_cfg_int_tx_i
,input ep3_rx_space_i
,input ep3_tx_ready_i
,input ep3_tx_data_valid_i
,input ep3_tx_data_strb_i
,input [ 7:0] ep3_tx_data_i
,input ep3_tx_data_last_i
,input reg_chirp_en_i
,input reg_int_en_sof_i
,input reg_sts_rst_clr_i
,input [ 6:0] reg_dev_addr_i
// Outputs
,output intr_o
,output [ 7:0] utmi_data_o
,output utmi_txvalid_o
,output rx_strb_o
,output [ 7:0] rx_data_o
,output rx_last_o
,output rx_crc_err_o
,output ep0_rx_setup_o
,output ep0_rx_valid_o
,output ep0_tx_data_accept_o
,output ep1_rx_setup_o
,output ep1_rx_valid_o
,output ep1_tx_data_accept_o
,output ep2_rx_setup_o
,output ep2_rx_valid_o
,output ep2_tx_data_accept_o
,output ep3_rx_setup_o
,output ep3_rx_valid_o
,output ep3_tx_data_accept_o
,output reg_sts_rst_o
,output [ 10:0] reg_sts_frame_num_o
);
//-----------------------------------------------------------------
// Defines:
//-----------------------------------------------------------------
//`include "usbf_defs.v"
// Tokens
`define PID_OUT 8'hE1
`define PID_IN 8'h69
`define PID_SOF 8'hA5
`define PID_SETUP 8'h2D
// Data
`define PID_DATA0 8'hC3
`define PID_DATA1 8'h4B
`define PID_DATA2 8'h87
`define PID_MDATA 8'h0F
// Handshake
`define PID_ACK 8'hD2
`define PID_NAK 8'h5A
`define PID_STALL 8'h1E
`define PID_NYET 8'h96
// Special
`define PID_PRE 8'h3C
`define PID_ERR 8'h3C
`define PID_SPLIT 8'h78
`define PID_PING 8'hB4
`define USB_RESET_CNT_W 15
localparam STATE_W = 3;
localparam STATE_RX_IDLE = 3'd0;
localparam STATE_RX_DATA = 3'd1;
localparam STATE_RX_DATA_READY = 3'd2;
localparam STATE_RX_DATA_IGNORE = 3'd3;
localparam STATE_TX_DATA = 3'd4;
localparam STATE_TX_DATA_COMPLETE = 3'd5;
localparam STATE_TX_HANDSHAKE = 3'd6;
localparam STATE_TX_CHIRP = 3'd7;
reg [STATE_W-1:0] state_q;
//-----------------------------------------------------------------
// Reset detection
//-----------------------------------------------------------------
reg [`USB_RESET_CNT_W-1:0] se0_cnt_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
se0_cnt_q <= `USB_RESET_CNT_W'b0;
else if (utmi_linestate_i == 2'b0)
begin
if (!se0_cnt_q[`USB_RESET_CNT_W-1])
se0_cnt_q <= se0_cnt_q + `USB_RESET_CNT_W'd1;
end
else
se0_cnt_q <= `USB_RESET_CNT_W'b0;
wire usb_rst_w = se0_cnt_q[`USB_RESET_CNT_W-1];
//-----------------------------------------------------------------
// Wire / Regs
//-----------------------------------------------------------------
`define USB_FRAME_W 11
wire [`USB_FRAME_W-1:0] frame_num_w;
wire frame_valid_w;
`define USB_DEV_W 7
wire [`USB_DEV_W-1:0] token_dev_w;
`define USB_EP_W 4
wire [`USB_EP_W-1:0] token_ep_w;
`define USB_PID_W 8
wire [`USB_PID_W-1:0] token_pid_w;
wire token_valid_w;
wire rx_data_valid_w;
wire rx_data_complete_w;
wire rx_handshake_w;
reg tx_data_valid_r;
reg tx_data_strb_r;
reg [7:0] tx_data_r;
reg tx_data_last_r;
wire tx_data_accept_w;
reg tx_valid_q;
reg [7:0] tx_pid_q;
wire tx_accept_w;
reg rx_space_q;
reg rx_space_r;
reg tx_ready_r;
reg ep_data_bit_r;
reg ep_stall_r;
reg ep_iso_r;
reg rx_enable_q;
reg rx_setup_q;
reg ep0_data_bit_q;
reg ep1_data_bit_q;
reg ep2_data_bit_q;
reg ep3_data_bit_q;
wire status_stage_w;
reg [`USB_DEV_W-1:0] current_addr_q;
//-----------------------------------------------------------------
// SIE - TX
//-----------------------------------------------------------------
usbf_sie_tx
u_sie_tx
(
.clk_i(clk_i),
.rst_i(rst_i),
.enable_i(~usb_rst_w),
.chirp_i(reg_chirp_en_i),
// UTMI Interface
.utmi_data_o(utmi_data_o),
.utmi_txvalid_o(utmi_txvalid_o),
.utmi_txready_i(utmi_txready_i),
// Request
.tx_valid_i(tx_valid_q),
.tx_pid_i(tx_pid_q),
.tx_accept_o(tx_accept_w),
// Data
.data_valid_i(tx_data_valid_r),
.data_strb_i(tx_data_strb_r),
.data_i(tx_data_r),
.data_last_i(tx_data_last_r),
.data_accept_o(tx_data_accept_w)
);
always @ *
begin
tx_data_valid_r = 1'b0;
tx_data_strb_r = 1'b0;
tx_data_r = 8'b0;
tx_data_last_r = 1'b0;
case (token_ep_w)
4'd0:
begin
tx_data_valid_r = ep0_tx_data_valid_i;
tx_data_strb_r = ep0_tx_data_strb_i;
tx_data_r = ep0_tx_data_i;
tx_data_last_r = ep0_tx_data_last_i;
end
4'd1:
begin
tx_data_valid_r = ep1_tx_data_valid_i;
tx_data_strb_r = ep1_tx_data_strb_i;
tx_data_r = ep1_tx_data_i;
tx_data_last_r = ep1_tx_data_last_i;
end
4'd2:
begin
tx_data_valid_r = ep2_tx_data_valid_i;
tx_data_strb_r = ep2_tx_data_strb_i;
tx_data_r = ep2_tx_data_i;
tx_data_last_r = ep2_tx_data_last_i;
end
4'd3:
begin
tx_data_valid_r = ep3_tx_data_valid_i;
tx_data_strb_r = ep3_tx_data_strb_i;
tx_data_r = ep3_tx_data_i;
tx_data_last_r = ep3_tx_data_last_i;
end
default:
;
endcase
end
assign ep0_tx_data_accept_o = tx_data_accept_w & (token_ep_w == 4'd0);
assign ep1_tx_data_accept_o = tx_data_accept_w & (token_ep_w == 4'd1);
assign ep2_tx_data_accept_o = tx_data_accept_w & (token_ep_w == 4'd2);
assign ep3_tx_data_accept_o = tx_data_accept_w & (token_ep_w == 4'd3);
always @ *
begin
rx_space_r = 1'b0;
tx_ready_r = 1'b0;
ep_data_bit_r = 1'b0;
ep_stall_r = 1'b0;
ep_iso_r = 1'b0;
case (token_ep_w)
4'd0:
begin
rx_space_r = ep0_rx_space_i;
tx_ready_r = ep0_tx_ready_i;
ep_data_bit_r = ep0_data_bit_q | status_stage_w;
ep_stall_r = ep0_stall_i;
ep_iso_r = ep0_iso_i;
end
4'd1:
begin
rx_space_r = ep1_rx_space_i;
tx_ready_r = ep1_tx_ready_i;
ep_data_bit_r = ep1_data_bit_q | status_stage_w;
ep_stall_r = ep1_stall_i;
ep_iso_r = ep1_iso_i;
end
4'd2:
begin
rx_space_r = ep2_rx_space_i;
tx_ready_r = ep2_tx_ready_i;
ep_data_bit_r = ep2_data_bit_q | status_stage_w;
ep_stall_r = ep2_stall_i;
ep_iso_r = ep2_iso_i;
end
4'd3:
begin
rx_space_r = ep3_rx_space_i;
tx_ready_r = ep3_tx_ready_i;
ep_data_bit_r = ep3_data_bit_q | status_stage_w;
ep_stall_r = ep3_stall_i;
ep_iso_r = ep3_iso_i;
end
default:
;
endcase
end
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
rx_space_q <= 1'b0;
else if (state_q == STATE_RX_IDLE)
rx_space_q <= rx_space_r;
//-----------------------------------------------------------------
// SIE - RX
//-----------------------------------------------------------------
usbf_sie_rx
u_sie_rx
(
.clk_i(clk_i),
.rst_i(rst_i),
.enable_i(~usb_rst_w && ~reg_chirp_en_i),
// UTMI Interface
.utmi_data_i(utmi_data_i),
.utmi_rxvalid_i(utmi_rxvalid_i),
.utmi_rxactive_i(utmi_rxactive_i),
.current_addr_i(current_addr_q),
.pid_o(token_pid_w),
.frame_valid_o(frame_valid_w),
.frame_number_o(reg_sts_frame_num_o),
.token_valid_o(token_valid_w),
.token_addr_o(token_dev_w),
.token_ep_o(token_ep_w),
.token_crc_err_o(),
.handshake_valid_o(rx_handshake_w),
.data_valid_o(rx_data_valid_w),
.data_strb_o(rx_strb_o),
.data_o(rx_data_o),
.data_last_o(rx_last_o),
.data_complete_o(rx_data_complete_w),
.data_crc_err_o(rx_crc_err_o)
);
assign ep0_rx_valid_o = rx_enable_q & rx_data_valid_w & (token_ep_w == 4'd0);
assign ep0_rx_setup_o = rx_setup_q & (token_ep_w == 4'd0);
assign ep1_rx_valid_o = rx_enable_q & rx_data_valid_w & (token_ep_w == 4'd1);
assign ep1_rx_setup_o = rx_setup_q & (token_ep_w == 4'd0);
assign ep2_rx_valid_o = rx_enable_q & rx_data_valid_w & (token_ep_w == 4'd2);
assign ep2_rx_setup_o = rx_setup_q & (token_ep_w == 4'd0);
assign ep3_rx_valid_o = rx_enable_q & rx_data_valid_w & (token_ep_w == 4'd3);
assign ep3_rx_setup_o = rx_setup_q & (token_ep_w == 4'd0);
//-----------------------------------------------------------------
// Next state
//-----------------------------------------------------------------
reg [STATE_W-1:0] next_state_r;
always @ *
begin
next_state_r = state_q;
//-----------------------------------------
// State Machine
//-----------------------------------------
case (state_q)
//-----------------------------------------
// IDLE
//-----------------------------------------
STATE_RX_IDLE :
begin
// Token received (OUT, IN, SETUP, PING)
if (token_valid_w)
begin
//-------------------------------
// IN transfer (device -> host)
//-------------------------------
if (token_pid_w == `PID_IN)
begin
// Stalled endpoint?
if (ep_stall_r)
next_state_r = STATE_TX_HANDSHAKE;
// Some data to TX?
else if (tx_ready_r)
next_state_r = STATE_TX_DATA;
// No data to TX
else
next_state_r = STATE_TX_HANDSHAKE;
end
//-------------------------------
// PING transfer (device -> host)
//-------------------------------
else if (token_pid_w == `PID_PING)
begin
next_state_r = STATE_TX_HANDSHAKE;
end
//-------------------------------
// OUT transfer (host -> device)
//-------------------------------
else if (token_pid_w == `PID_OUT)
begin
// Stalled endpoint?
if (ep_stall_r)
next_state_r = STATE_RX_DATA_IGNORE;
// Some space to rx
else if (rx_space_r)
next_state_r = STATE_RX_DATA;
// No rx space, ignore receive
else
next_state_r = STATE_RX_DATA_IGNORE;
end
//-------------------------------
// SETUP transfer (host -> device)
//-------------------------------
else if (token_pid_w == `PID_SETUP)
begin
// Some space to rx
if (rx_space_r)
next_state_r = STATE_RX_DATA;
// No rx space, ignore receive
else
next_state_r = STATE_RX_DATA_IGNORE;
end
end
else if (reg_chirp_en_i)
next_state_r = STATE_TX_CHIRP;
end
//-----------------------------------------
// RX_DATA
//-----------------------------------------
STATE_RX_DATA :
begin
// TODO: Exit data state handling?
// TODO: Sort out ISO data bit handling
// Check for expected DATAx PID
if ((token_pid_w == `PID_DATA0 && ep_data_bit_r && !ep_iso_r) ||
(token_pid_w == `PID_DATA1 && !ep_data_bit_r && !ep_iso_r))
next_state_r = STATE_RX_DATA_IGNORE;
// Receive complete
else if (rx_data_valid_w && rx_last_o)
next_state_r = STATE_RX_DATA_READY;
end
//-----------------------------------------
// RX_DATA_IGNORE
//-----------------------------------------
STATE_RX_DATA_IGNORE :
begin
// Receive complete
if (rx_data_valid_w && rx_last_o)
next_state_r = STATE_RX_DATA_READY;
end
//-----------------------------------------
// RX_DATA_READY
//-----------------------------------------
STATE_RX_DATA_READY :
begin
if (rx_data_complete_w)
begin
// No response on CRC16 error
if (rx_crc_err_o)
next_state_r = STATE_RX_IDLE;
// ISO endpoint, no response?
else if (ep_iso_r)
next_state_r = STATE_RX_IDLE;
else
next_state_r = STATE_TX_HANDSHAKE;
end
end
//-----------------------------------------
// TX_DATA
//-----------------------------------------
STATE_TX_DATA :
begin
if (!tx_valid_q || tx_accept_w)
if (tx_data_valid_r && tx_data_last_r && tx_data_accept_w)
next_state_r = STATE_TX_DATA_COMPLETE;
end
//-----------------------------------------
// TX_HANDSHAKE
//-----------------------------------------
STATE_TX_DATA_COMPLETE :
begin
next_state_r = STATE_RX_IDLE;
end
//-----------------------------------------
// TX_HANDSHAKE
//-----------------------------------------
STATE_TX_HANDSHAKE :
begin
if (tx_accept_w)
next_state_r = STATE_RX_IDLE;
end
//-----------------------------------------
// TX_CHIRP
//-----------------------------------------
STATE_TX_CHIRP :
begin
if (!reg_chirp_en_i)
next_state_r = STATE_RX_IDLE;
end
default :
;
endcase
//-----------------------------------------
// USB Bus Reset (HOST->DEVICE)
//-----------------------------------------
if (usb_rst_w && !reg_chirp_en_i)
next_state_r = STATE_RX_IDLE;
end
// Update state
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
state_q <= STATE_RX_IDLE;
else
state_q <= next_state_r;
//-----------------------------------------------------------------
// Response
//-----------------------------------------------------------------
reg tx_valid_r;
reg [7:0] tx_pid_r;
always @ *
begin
tx_valid_r = 1'b0;
tx_pid_r = 8'b0;
case (state_q)
//-----------------------------------------
// IDLE
//-----------------------------------------
STATE_RX_IDLE :
begin
// Token received (OUT, IN, SETUP, PING)
if (token_valid_w)
begin
//-------------------------------
// IN transfer (device -> host)
//-------------------------------
if (token_pid_w == `PID_IN)
begin
// Stalled endpoint?
if (ep_stall_r)
begin
tx_valid_r = 1'b1;
tx_pid_r = `PID_STALL;
end
// Some data to TX?
else if (tx_ready_r)
begin
tx_valid_r = 1'b1;
// TODO: Handle MDATA for ISOs
tx_pid_r = ep_data_bit_r ? `PID_DATA1 : `PID_DATA0;
end
// No data to TX
else
begin
tx_valid_r = 1'b1;
tx_pid_r = `PID_NAK;
end
end
//-------------------------------
// PING transfer (device -> host)
//-------------------------------
else if (token_pid_w == `PID_PING)
begin
// Stalled endpoint?
if (ep_stall_r)
begin
tx_valid_r = 1'b1;
tx_pid_r = `PID_STALL;
end
// Data ready to RX
else if (rx_space_r)
begin
tx_valid_r = 1'b1;
tx_pid_r = `PID_ACK;
end
// No data to TX
else
begin
tx_valid_r = 1'b1;
tx_pid_r = `PID_NAK;
end
end
end
end
//-----------------------------------------
// RX_DATA_READY
//-----------------------------------------
STATE_RX_DATA_READY :
begin
// Receive complete
if (rx_data_complete_w)
begin
// No response on CRC16 error
if (rx_crc_err_o)
;
// ISO endpoint, no response?
else if (ep_iso_r)
;
// Send STALL?
else if (ep_stall_r)
begin
tx_valid_r = 1'b1;
tx_pid_r = `PID_STALL;
end
// DATAx bit mismatch
else if ( (token_pid_w == `PID_DATA0 && ep_data_bit_r) ||
(token_pid_w == `PID_DATA1 && !ep_data_bit_r) )
begin
// Ack transfer to resync
tx_valid_r = 1'b1;
tx_pid_r = `PID_ACK;
end
// Send NAK
else if (!rx_space_q)
begin
tx_valid_r = 1'b1;
tx_pid_r = `PID_NAK;
end
// TODO: USB 2.0, no more buffer space, return NYET
else
begin
tx_valid_r = 1'b1;
tx_pid_r = `PID_ACK;
end
end
end
//-----------------------------------------
// TX_CHIRP
//-----------------------------------------
STATE_TX_CHIRP :
begin
tx_valid_r = 1'b1;
tx_pid_r = 8'b0;
end
default :
;
endcase
end
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
tx_valid_q <= 1'b0;
else if (!tx_valid_q || tx_accept_w)
tx_valid_q <= tx_valid_r;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
tx_pid_q <= 8'b0;
else if (!tx_valid_q || tx_accept_w)
tx_pid_q <= tx_pid_r;
//-----------------------------------------------------------------
// Receive enable
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
rx_enable_q <= 1'b0;
else if (usb_rst_w ||reg_chirp_en_i)
rx_enable_q <= 1'b0;
else
rx_enable_q <= (state_q == STATE_RX_DATA);
//-----------------------------------------------------------------
// Receive SETUP: Pulse on SETUP packet receive
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
rx_setup_q <= 1'b0;
else if (usb_rst_w ||reg_chirp_en_i)
rx_setup_q <= 1'b0;
else if ((state_q == STATE_RX_IDLE) && token_valid_w && (token_pid_w == `PID_SETUP) && (token_ep_w == 4'd0))
rx_setup_q <= 1'b1;
else
rx_setup_q <= 1'b0;
//-----------------------------------------------------------------
// Set Address
//-----------------------------------------------------------------
reg addr_update_pending_q;
wire ep0_tx_zlp_w = ep0_tx_data_valid_i && (ep0_tx_data_strb_i == 1'b0) &&
ep0_tx_data_last_i && ep0_tx_data_accept_o;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
addr_update_pending_q <= 1'b0;
else if (ep0_tx_zlp_w || usb_rst_w)
addr_update_pending_q <= 1'b0;
// TODO: Use write strobe
else if (reg_dev_addr_i != current_addr_q)
addr_update_pending_q <= 1'b1;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
current_addr_q <= `USB_DEV_W'b0;
else if (usb_rst_w)
current_addr_q <= `USB_DEV_W'b0;
else if (ep0_tx_zlp_w && addr_update_pending_q)
current_addr_q <= reg_dev_addr_i;
//-----------------------------------------------------------------
// SETUP request tracking
//-----------------------------------------------------------------
reg ep0_dir_in_q;
reg ep0_dir_out_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
ep0_dir_in_q <= 1'b0;
else if (usb_rst_w ||reg_chirp_en_i)
ep0_dir_in_q <= 1'b0;
else if ((state_q == STATE_RX_IDLE) && token_valid_w && (token_pid_w == `PID_SETUP) && (token_ep_w == 4'd0))
ep0_dir_in_q <= 1'b0;
else if ((state_q == STATE_RX_IDLE) && token_valid_w && (token_pid_w == `PID_IN) && (token_ep_w == 4'd0))
ep0_dir_in_q <= 1'b1;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
ep0_dir_out_q <= 1'b0;
else if (usb_rst_w ||reg_chirp_en_i)
ep0_dir_out_q <= 1'b0;
else if ((state_q == STATE_RX_IDLE) && token_valid_w && (token_pid_w == `PID_SETUP) && (token_ep_w == 4'd0))
ep0_dir_out_q <= 1'b0;
else if ((state_q == STATE_RX_IDLE) && token_valid_w && (token_pid_w == `PID_OUT) && (token_ep_w == 4'd0))
ep0_dir_out_q <= 1'b1;
assign status_stage_w = ep0_dir_in_q && ep0_dir_out_q && (token_ep_w == 4'd0);
//-----------------------------------------------------------------
// Endpoint data bit toggle
//-----------------------------------------------------------------
reg new_data_bit_r;
always @ *
begin
new_data_bit_r = ep_data_bit_r;
case (state_q)
//-----------------------------------------
// RX_DATA_READY
//-----------------------------------------
STATE_RX_DATA_READY :
begin
// Receive complete
if (rx_data_complete_w)
begin
// No toggle on CRC16 error
if (rx_crc_err_o)
;
// ISO endpoint, no response?
else if (ep_iso_r)
; // TODO: HS handling
// STALL?
else if (ep_stall_r)
;
// DATAx bit mismatch
else if ( (token_pid_w == `PID_DATA0 && ep_data_bit_r) ||
(token_pid_w == `PID_DATA1 && !ep_data_bit_r) )
;
// NAKd
else if (!rx_space_q)
;
// Data accepted - toggle data bit
else
new_data_bit_r = !ep_data_bit_r;
end
end
//-----------------------------------------
// RX_IDLE
//-----------------------------------------
STATE_RX_IDLE :
begin
// Token received (OUT, IN, SETUP, PING)
if (token_valid_w)
begin
// SETUP packets always start with DATA0
if (token_pid_w == `PID_SETUP)
new_data_bit_r = 1'b0;
end
// ACK received
else if (rx_handshake_w && token_pid_w == `PID_ACK)
begin
new_data_bit_r = !ep_data_bit_r;
end
end
default:
;
endcase
end
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
ep0_data_bit_q <= 1'b0;
else if (usb_rst_w)
ep0_data_bit_q <= 1'b0;
else if (token_ep_w == 4'd0)
ep0_data_bit_q <= new_data_bit_r;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
ep1_data_bit_q <= 1'b0;
else if (usb_rst_w)
ep1_data_bit_q <= 1'b0;
else if (token_ep_w == 4'd1)
ep1_data_bit_q <= new_data_bit_r;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
ep2_data_bit_q <= 1'b0;
else if (usb_rst_w)
ep2_data_bit_q <= 1'b0;
else if (token_ep_w == 4'd2)
ep2_data_bit_q <= new_data_bit_r;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
ep3_data_bit_q <= 1'b0;
else if (usb_rst_w)
ep3_data_bit_q <= 1'b0;
else if (token_ep_w == 4'd3)
ep3_data_bit_q <= new_data_bit_r;
//-----------------------------------------------------------------
// Reset event
//-----------------------------------------------------------------
reg rst_event_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
rst_event_q <= 1'b0;
else if (usb_rst_w)
rst_event_q <= 1'b1;
else if (reg_sts_rst_clr_i)
rst_event_q <= 1'b0;
assign reg_sts_rst_o = rst_event_q;
//-----------------------------------------------------------------
// Interrupts
//-----------------------------------------------------------------
reg intr_q;
reg cfg_int_rx_r;
reg cfg_int_tx_r;
always @ *
begin
cfg_int_rx_r = 1'b0;
cfg_int_tx_r = 1'b0;
case (token_ep_w)
4'd0:
begin
cfg_int_rx_r = ep0_cfg_int_rx_i;
cfg_int_tx_r = ep0_cfg_int_tx_i;
end
4'd1:
begin
cfg_int_rx_r = ep1_cfg_int_rx_i;
cfg_int_tx_r = ep1_cfg_int_tx_i;
end
4'd2:
begin
cfg_int_rx_r = ep2_cfg_int_rx_i;
cfg_int_tx_r = ep2_cfg_int_tx_i;
end
4'd3:
begin
cfg_int_rx_r = ep3_cfg_int_rx_i;
cfg_int_tx_r = ep3_cfg_int_tx_i;
end
default:
;
endcase
end
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
intr_q <= 1'b0;
// SOF
else if (frame_valid_w && reg_int_en_sof_i)
intr_q <= 1'b1;
// Reset event
else if (!rst_event_q && usb_rst_w)
intr_q <= 1'b1;
// Rx ready
else if (state_q == STATE_RX_DATA_READY && rx_space_q && cfg_int_rx_r)
intr_q <= 1'b1;
// Tx complete
else if (state_q == STATE_TX_DATA_COMPLETE && cfg_int_tx_r)
intr_q <= 1'b1;
else
intr_q <= 1'b0;
assign intr_o = intr_q;
//-------------------------------------------------------------------
// Debug
//-------------------------------------------------------------------
`ifdef verilator
/* verilator lint_off WIDTH */
reg [79:0] dbg_state;
always @ *
begin
dbg_state = "-";
case (state_q)
STATE_RX_IDLE: dbg_state = "IDLE";
STATE_RX_DATA: dbg_state = "RX_DATA";
STATE_RX_DATA_READY: dbg_state = "RX_DATA_READY";
STATE_RX_DATA_IGNORE: dbg_state = "RX_IGNORE";
STATE_TX_DATA: dbg_state = "TX_DATA";
STATE_TX_DATA_COMPLETE: dbg_state = "TX_DATA_COMPLETE";
STATE_TX_HANDSHAKE: dbg_state = "TX_HANDSHAKE";
STATE_TX_CHIRP: dbg_state = "CHIRP";
endcase
end
reg [79:0] dbg_pid;
reg [7:0] dbg_pid_r;
always @ *
begin
dbg_pid = "-";
if (tx_valid_q && tx_accept_w)
dbg_pid_r = tx_pid_q;
else if (token_valid_w || rx_handshake_w || rx_data_valid_w)
dbg_pid_r = token_pid_w;
else
dbg_pid_r = 8'b0;
case (dbg_pid_r)
// Token
`PID_OUT:
dbg_pid = "OUT";
`PID_IN:
dbg_pid = "IN";
`PID_SOF:
dbg_pid = "SOF";
`PID_SETUP:
dbg_pid = "SETUP";
`PID_PING:
dbg_pid = "PING";
// Data
`PID_DATA0:
dbg_pid = "DATA0";
`PID_DATA1:
dbg_pid = "DATA1";
`PID_DATA2:
dbg_pid = "DATA2";
`PID_MDATA:
dbg_pid = "MDATA";
// Handshake
`PID_ACK:
dbg_pid = "ACK";
`PID_NAK:
dbg_pid = "NAK";
`PID_STALL:
dbg_pid = "STALL";
`PID_NYET:
dbg_pid = "NYET";
// Special
`PID_PRE:
dbg_pid = "PRE/ERR";
`PID_SPLIT:
dbg_pid = "SPLIT";
default:
;
endcase
end
/* verilator lint_on WIDTH */
`endif
endmodule
module usbf_fifo
(
// Inputs
input clk_i
,input rst_i
,input [ 7:0] data_i
,input push_i
,input pop_i
,input flush_i
// Outputs
,output full_o
,output empty_o
,output [ 7:0] data_o
);
parameter WIDTH = 8;
parameter DEPTH = 4;
parameter ADDR_W = 2;
//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [ADDR_W-1:0] rd_ptr;
reg [ADDR_W-1:0] wr_ptr;
reg [COUNT_W-1:0] count;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
count <= {(COUNT_W) {1'b0}};
rd_ptr <= {(ADDR_W) {1'b0}};
wr_ptr <= {(ADDR_W) {1'b0}};
end
else
begin
if (flush_i)
begin
count <= {(COUNT_W) {1'b0}};
rd_ptr <= {(ADDR_W) {1'b0}};
wr_ptr <= {(ADDR_W) {1'b0}};
end
// Push
if (push_i & ~full_o)
begin
ram[wr_ptr] <= data_i;
wr_ptr <= wr_ptr + 1;
end
// Pop
if (pop_i & ~empty_o)
begin
rd_ptr <= rd_ptr + 1;
end
// Count up
if ((push_i & ~full_o) & ~(pop_i & ~empty_o))
begin
count <= count + 1;
end
// Count down
else if (~(push_i & ~full_o) & (pop_i & ~empty_o))
begin
count <= count - 1;
end
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign full_o = (count == DEPTH);
assign empty_o = (count == 0);
/* verilator lint_on WIDTH */
assign data_o = ram[rd_ptr];
endmodule
module usbf_sie_ep
(
// Inputs
input clk_i
,input rst_i
,input rx_setup_i
,input rx_valid_i
,input rx_strb_i
,input [ 7:0] rx_data_i
,input rx_last_i
,input rx_crc_err_i
,input rx_full_i
,input rx_ack_i
,input [ 7:0] tx_data_i
,input tx_empty_i
,input tx_flush_i
,input [ 10:0] tx_length_i
,input tx_start_i
,input tx_data_accept_i
// Outputs
,output rx_space_o
,output rx_push_o
,output [ 7:0] rx_data_o
,output [ 10:0] rx_length_o
,output rx_ready_o
,output rx_err_o
,output rx_setup_o
,output tx_pop_o
,output tx_busy_o
,output tx_err_o
,output tx_ready_o
,output tx_data_valid_o
,output tx_data_strb_o
,output [ 7:0] tx_data_o
,output tx_data_last_o
);
//-----------------------------------------------------------------
// Rx
//-----------------------------------------------------------------
reg rx_ready_q;
reg rx_err_q;
reg [10:0] rx_len_q;
reg rx_setup_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
rx_ready_q <= 1'b0;
else if (rx_ack_i)
rx_ready_q <= 1'b0;
else if (rx_valid_i && rx_last_i)
rx_ready_q <= 1'b1;
assign rx_space_o = !rx_ready_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
rx_len_q <= 11'b0;
else if (rx_ack_i)
rx_len_q <= 11'b0;
else if (rx_valid_i && rx_strb_i)
rx_len_q <= rx_len_q + 11'd1;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
rx_err_q <= 1'b0;
else if (rx_ack_i)
rx_err_q <= 1'b0;
else if (rx_valid_i && rx_last_i && rx_crc_err_i)
rx_err_q <= 1'b1;
else if (rx_full_i && rx_push_o)
rx_err_q <= 1'b1;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
rx_setup_q <= 1'b0;
else if (rx_ack_i)
rx_setup_q <= 1'b0;
else if (rx_setup_i)
rx_setup_q <= 1'b1;
assign rx_length_o = rx_len_q;
assign rx_ready_o = rx_ready_q;
assign rx_err_o = rx_err_q;
assign rx_setup_o = rx_setup_q;
assign rx_push_o = rx_valid_i & rx_strb_i;
assign rx_data_o = rx_data_i;
//-----------------------------------------------------------------
// Tx
//-----------------------------------------------------------------
reg tx_active_q;
reg tx_err_q;
reg tx_zlp_q;
reg [10:0] tx_len_q;
// Tx active
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
tx_active_q <= 1'b0;
else if (tx_flush_i)
tx_active_q <= 1'b0;
else if (tx_start_i)
tx_active_q <= 1'b1;
else if (tx_data_valid_o && tx_data_last_o && tx_data_accept_i)
tx_active_q <= 1'b0;
assign tx_ready_o = tx_active_q;
// Tx zero length packet
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
tx_zlp_q <= 1'b0;
else if (tx_flush_i)
tx_zlp_q <= 1'b0;
else if (tx_start_i)
tx_zlp_q <= (tx_length_i == 11'b0);
// Tx length
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
tx_len_q <= 11'b0;
else if (tx_flush_i)
tx_len_q <= 11'b0;
else if (tx_start_i)
tx_len_q <= tx_length_i;
else if (tx_data_valid_o && tx_data_accept_i && !tx_zlp_q)
tx_len_q <= tx_len_q - 11'd1;
// Tx SIE Interface
assign tx_data_valid_o = tx_active_q;
assign tx_data_strb_o = !tx_zlp_q;
assign tx_data_last_o = tx_zlp_q || (tx_len_q == 11'd1);
assign tx_data_o = tx_data_i;
// Error: Buffer underrun
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
tx_err_q <= 1'b0;
else if (tx_flush_i)
tx_err_q <= 1'b0;
else if (tx_start_i)
tx_err_q <= 1'b0;
else if (!tx_zlp_q && tx_empty_i && tx_data_valid_o)
tx_err_q <= 1'b1;
// Tx Register Interface
assign tx_err_o = tx_err_q;
assign tx_busy_o = tx_active_q;
// Tx FIFO Interface
assign tx_pop_o = tx_data_accept_i & tx_active_q;
endmodule
module usbf_sie_rx
(
// Inputs
input clk_i
,input rst_i
,input enable_i
,input [ 7:0] utmi_data_i
,input utmi_rxvalid_i
,input utmi_rxactive_i
,input [ 6:0] current_addr_i
// Outputs
,output [ 7:0] pid_o
,output frame_valid_o
,output [ 10:0] frame_number_o
,output token_valid_o
,output [ 6:0] token_addr_o
,output [ 3:0] token_ep_o
,output token_crc_err_o
,output handshake_valid_o
,output data_valid_o
,output data_strb_o
,output [ 7:0] data_o
,output data_last_o
,output data_crc_err_o
,output data_complete_o
);
//-----------------------------------------------------------------
// Defines:
//-----------------------------------------------------------------
//`include "usbf_defs.v"
// Tokens
`define PID_OUT 8'hE1
`define PID_IN 8'h69
`define PID_SOF 8'hA5
`define PID_SETUP 8'h2D
// Data
`define PID_DATA0 8'hC3
`define PID_DATA1 8'h4B
`define PID_DATA2 8'h87
`define PID_MDATA 8'h0F
// Handshake
`define PID_ACK 8'hD2
`define PID_NAK 8'h5A
`define PID_STALL 8'h1E
`define PID_NYET 8'h96
// Special
`define PID_PRE 8'h3C
`define PID_ERR 8'h3C
`define PID_SPLIT 8'h78
`define PID_PING 8'hB4
localparam STATE_W = 4;
localparam STATE_RX_IDLE = 4'd0;
localparam STATE_RX_TOKEN2 = 4'd1;
localparam STATE_RX_TOKEN3 = 4'd2;
localparam STATE_RX_TOKEN_COMPLETE = 4'd3;
localparam STATE_RX_SOF2 = 4'd4;
localparam STATE_RX_SOF3 = 4'd5;
localparam STATE_RX_DATA = 4'd6;
localparam STATE_RX_DATA_COMPLETE = 4'd7;
localparam STATE_RX_IGNORED = 4'd8;
reg [STATE_W-1:0] state_q;
//-----------------------------------------------------------------
// Wire / Regs
//-----------------------------------------------------------------
`define USB_FRAME_W 11
reg [`USB_FRAME_W-1:0] frame_num_q;
`define USB_DEV_W 7
reg [`USB_DEV_W-1:0] token_dev_q;
`define USB_EP_W 4
reg [`USB_EP_W-1:0] token_ep_q;
`define USB_PID_W 8
reg [`USB_PID_W-1:0] token_pid_q;
//-----------------------------------------------------------------
// Data delay (to strip the CRC16 trailing bytes)
//-----------------------------------------------------------------
reg [31:0] data_buffer_q;
reg [3:0] data_valid_q;
reg [3:0] rx_active_q;
wire shift_en_w = (utmi_rxvalid_i & utmi_rxactive_i) || !utmi_rxactive_i;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
data_buffer_q <= 32'b0;
else if (shift_en_w)
data_buffer_q <= {utmi_data_i, data_buffer_q[31:8]};
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
data_valid_q <= 4'b0;
else if (shift_en_w)
data_valid_q <= {(utmi_rxvalid_i & utmi_rxactive_i), data_valid_q[3:1]};
else
data_valid_q <= {data_valid_q[3:1], 1'b0};
reg [1:0] data_crc_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
data_crc_q <= 2'b0;
else if (shift_en_w)
data_crc_q <= {!utmi_rxactive_i, data_crc_q[1]};
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
rx_active_q <= 4'b0;
else
rx_active_q <= {utmi_rxactive_i, rx_active_q[3:1]};
wire [7:0] data_w = data_buffer_q[7:0];
wire data_ready_w = data_valid_q[0];
wire crc_byte_w = data_crc_q[0];
wire rx_active_w = rx_active_q[0];
wire address_match_w = (token_dev_q == current_addr_i);
//-----------------------------------------------------------------
// Next state
//-----------------------------------------------------------------
reg [STATE_W-1:0] next_state_r;
always @ *
begin
next_state_r = state_q;
case (state_q)
//-----------------------------------------
// IDLE
//-----------------------------------------
STATE_RX_IDLE :
begin
if (data_ready_w)
begin
// Decode PID
case (data_w)
`PID_OUT, `PID_IN, `PID_SETUP, `PID_PING:
next_state_r = STATE_RX_TOKEN2;
`PID_SOF:
next_state_r = STATE_RX_SOF2;
`PID_DATA0, `PID_DATA1, `PID_DATA2, `PID_MDATA:
begin
next_state_r = STATE_RX_DATA;
end
`PID_ACK, `PID_NAK, `PID_STALL, `PID_NYET:
next_state_r = STATE_RX_IDLE;
default : // SPLIT / ERR
next_state_r = STATE_RX_IGNORED;
endcase
end
end
//-----------------------------------------
// RX_IGNORED: Unknown / unsupported
//-----------------------------------------
STATE_RX_IGNORED :
begin
// Wait until the end of the packet
if (!rx_active_w)
next_state_r = STATE_RX_IDLE;
end
//-----------------------------------------
// SOF (BYTE 2)
//-----------------------------------------
STATE_RX_SOF2 :
begin
if (data_ready_w)
next_state_r = STATE_RX_SOF3;
else if (!rx_active_w)
next_state_r = STATE_RX_IDLE;
end
//-----------------------------------------
// SOF (BYTE 3)
//-----------------------------------------
STATE_RX_SOF3 :
begin
if (data_ready_w || !rx_active_w)
next_state_r = STATE_RX_IDLE;
end
//-----------------------------------------
// TOKEN (IN/OUT/SETUP) (Address/Endpoint)
//-----------------------------------------
STATE_RX_TOKEN2 :
begin
if (data_ready_w)
next_state_r = STATE_RX_TOKEN3;
else if (!rx_active_w)
next_state_r = STATE_RX_IDLE;
end
//-----------------------------------------
// TOKEN (IN/OUT/SETUP) (Endpoint/CRC)
//-----------------------------------------
STATE_RX_TOKEN3 :
begin
if (data_ready_w)
next_state_r = STATE_RX_TOKEN_COMPLETE;
else if (!rx_active_w)
next_state_r = STATE_RX_IDLE;
end
//-----------------------------------------
// RX_TOKEN_COMPLETE
//-----------------------------------------
STATE_RX_TOKEN_COMPLETE :
begin
next_state_r = STATE_RX_IDLE;
end
//-----------------------------------------
// RX_DATA
//-----------------------------------------
STATE_RX_DATA :
begin
// Receive complete
if (crc_byte_w)
next_state_r = STATE_RX_DATA_COMPLETE;
end
//-----------------------------------------
// RX_DATA_COMPLETE
//-----------------------------------------
STATE_RX_DATA_COMPLETE :
begin
if (!rx_active_w)
next_state_r = STATE_RX_IDLE;
end
default :
;
endcase
end
// Update state
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
state_q <= STATE_RX_IDLE;
else if (!enable_i)
state_q <= STATE_RX_IDLE;
else
state_q <= next_state_r;
//-----------------------------------------------------------------
// Handshake:
//-----------------------------------------------------------------
reg handshake_valid_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
handshake_valid_q <= 1'b0;
else if (state_q == STATE_RX_IDLE && data_ready_w)
begin
case (data_w)
`PID_ACK, `PID_NAK, `PID_STALL, `PID_NYET:
handshake_valid_q <= address_match_w;
default :
handshake_valid_q <= 1'b0;
endcase
end
else
handshake_valid_q <= 1'b0;
assign handshake_valid_o = handshake_valid_q;
//-----------------------------------------------------------------
// SOF: Frame number
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
frame_num_q <= `USB_FRAME_W'b0;
else if (state_q == STATE_RX_SOF2 && data_ready_w)
frame_num_q <= {3'b0, data_w};
else if (state_q == STATE_RX_SOF3 && data_ready_w)
frame_num_q <= {data_w[2:0], frame_num_q[7:0]};
else if (!enable_i)
frame_num_q <= `USB_FRAME_W'b0;
assign frame_number_o = frame_num_q;
reg frame_valid_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
frame_valid_q <= 1'b0;
else
frame_valid_q <= (state_q == STATE_RX_SOF3 && data_ready_w);
assign frame_valid_o = frame_valid_q;
//-----------------------------------------------------------------
// Token: PID
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
token_pid_q <= `USB_PID_W'b0;
else if (state_q == STATE_RX_IDLE && data_ready_w)
token_pid_q <= data_w;
else if (!enable_i)
token_pid_q <= `USB_PID_W'b0;
assign pid_o = token_pid_q;
reg token_valid_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
token_valid_q <= 1'b0;
else
token_valid_q <= (state_q == STATE_RX_TOKEN_COMPLETE) && address_match_w;
assign token_valid_o = token_valid_q;
//-----------------------------------------------------------------
// Token: Device Address
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
token_dev_q <= `USB_DEV_W'b0;
else if (state_q == STATE_RX_TOKEN2 && data_ready_w)
token_dev_q <= data_w[6:0];
else if (!enable_i)
token_dev_q <= `USB_DEV_W'b0;
assign token_addr_o = token_dev_q;
//-----------------------------------------------------------------
// Token: Endpoint
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
token_ep_q <= `USB_EP_W'b0;
else if (state_q == STATE_RX_TOKEN2 && data_ready_w)
token_ep_q[0] <= data_w[7];
else if (state_q == STATE_RX_TOKEN3 && data_ready_w)
token_ep_q[3:1] <= data_w[2:0];
else if (!enable_i)
token_ep_q <= `USB_EP_W'b0;
assign token_ep_o = token_ep_q;
assign token_crc_err_o = 1'b0;
wire [7:0] input_data_w = data_w;
wire input_ready_w = state_q == STATE_RX_DATA && data_ready_w && !crc_byte_w;
//-----------------------------------------------------------------
// CRC16: Generate CRC16 on incoming data bytes
//-----------------------------------------------------------------
reg [15:0] crc_sum_q;
wire [15:0] crc_out_w;
reg crc_err_q;
usbf_crc16
u_crc16
(
.crc_in_i(crc_sum_q),
.din_i(data_w),
.crc_out_o(crc_out_w)
);
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
crc_sum_q <= 16'hFFFF;
else if (state_q == STATE_RX_IDLE)
crc_sum_q <= 16'hFFFF;
else if (data_ready_w)
crc_sum_q <= crc_out_w;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
crc_err_q <= 1'b0;
else if (state_q == STATE_RX_IDLE)
crc_err_q <= 1'b0;
else if (state_q == STATE_RX_DATA_COMPLETE && next_state_r == STATE_RX_IDLE)
crc_err_q <= (crc_sum_q != 16'hB001);
assign data_crc_err_o = crc_err_q;
reg data_complete_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
data_complete_q <= 1'b0;
else if (state_q == STATE_RX_DATA_COMPLETE && next_state_r == STATE_RX_IDLE)
data_complete_q <= 1'b1;
else
data_complete_q <= 1'b0;
assign data_complete_o = data_complete_q;
reg data_zlp_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
data_zlp_q <= 1'b0;
else if (state_q == STATE_RX_IDLE && next_state_r == STATE_RX_DATA)
data_zlp_q <= 1'b1;
else if (input_ready_w)
data_zlp_q <= 1'b0;
//-----------------------------------------------------------------
// Data Output
//-----------------------------------------------------------------
reg valid_q;
reg last_q;
reg [7:0] data_q;
reg mask_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
valid_q <= 1'b0;
data_q <= 8'b0;
mask_q <= 1'b0;
last_q <= 1'b0;
end
else
begin
valid_q <= input_ready_w || ((state_q == STATE_RX_DATA) && crc_byte_w && data_zlp_q);
data_q <= input_data_w;
mask_q <= input_ready_w;
last_q <= (state_q == STATE_RX_DATA) && crc_byte_w;
end
// Data
assign data_valid_o = valid_q;
assign data_strb_o = mask_q;
assign data_o = data_q;
assign data_last_o = last_q | crc_byte_w;
endmodule
module usbf_sie_tx
(
// Inputs
input clk_i
,input rst_i
,input enable_i
,input chirp_i
,input utmi_txready_i
,input tx_valid_i
,input [ 7:0] tx_pid_i
,input data_valid_i
,input data_strb_i
,input [ 7:0] data_i
,input data_last_i
// Outputs
,output [ 7:0] utmi_data_o
,output utmi_txvalid_o
,output tx_accept_o
,output data_accept_o
);
//-----------------------------------------------------------------
// Defines:
//-----------------------------------------------------------------
//`include "usbf_defs.v"
// Tokens
`define PID_OUT 8'hE1
`define PID_IN 8'h69
`define PID_SOF 8'hA5
`define PID_SETUP 8'h2D
// Data
`define PID_DATA0 8'hC3
`define PID_DATA1 8'h4B
`define PID_DATA2 8'h87
`define PID_MDATA 8'h0F
// Handshake
`define PID_ACK 8'hD2
`define PID_NAK 8'h5A
`define PID_STALL 8'h1E
`define PID_NYET 8'h96
// Special
`define PID_PRE 8'h3C
`define PID_ERR 8'h3C
`define PID_SPLIT 8'h78
`define PID_PING 8'hB4
localparam STATE_W = 3;
localparam STATE_TX_IDLE = 3'd0;
localparam STATE_TX_PID = 3'd1;
localparam STATE_TX_DATA = 3'd2;
localparam STATE_TX_CRC1 = 3'd3;
localparam STATE_TX_CRC2 = 3'd4;
localparam STATE_TX_DONE = 3'd5;
localparam STATE_TX_CHIRP = 3'd6;
reg [STATE_W-1:0] state_q;
reg [STATE_W-1:0] next_state_r;
//-----------------------------------------------------------------
// Wire / Regs
//-----------------------------------------------------------------
reg last_q;
//-----------------------------------------------------------------
// Request Type
//-----------------------------------------------------------------
reg data_pid_q;
reg data_zlp_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
data_pid_q <= 1'b0;
data_zlp_q <= 1'b0;
end
else if (!enable_i)
begin
data_pid_q <= 1'b0;
data_zlp_q <= 1'b0;
end
else if (tx_valid_i && tx_accept_o)
begin
case (tx_pid_i)
`PID_MDATA, `PID_DATA2, `PID_DATA0, `PID_DATA1:
begin
data_pid_q <= 1'b1;
data_zlp_q <= data_valid_i && (data_strb_i == 1'b0) && data_last_i;
end
default :
begin
data_pid_q <= 1'b0;
data_zlp_q <= 1'b0;
end
endcase
end
else if (next_state_r == STATE_TX_CRC1)
begin
data_pid_q <= 1'b0;
data_zlp_q <= 1'b0;
end
assign tx_accept_o = (state_q == STATE_TX_IDLE);
//-----------------------------------------------------------------
// Next state
//-----------------------------------------------------------------
always @ *
begin
next_state_r = state_q;
//-----------------------------------------
// State Machine
//-----------------------------------------
case (state_q)
//-----------------------------------------
// IDLE
//-----------------------------------------
STATE_TX_IDLE :
begin
if (chirp_i)
next_state_r = STATE_TX_CHIRP;
else if (tx_valid_i)
next_state_r = STATE_TX_PID;
end
//-----------------------------------------
// TX_PID
//-----------------------------------------
STATE_TX_PID :
begin
// Data accepted
if (utmi_txready_i)
begin
if (data_zlp_q)
next_state_r = STATE_TX_CRC1;
else if (data_pid_q)
next_state_r = STATE_TX_DATA;
else
next_state_r = STATE_TX_DONE;
end
end
//-----------------------------------------
// TX_DATA
//-----------------------------------------
STATE_TX_DATA :
begin
// Data accepted
if (utmi_txready_i)
begin
// Generate CRC16 at end of packet
if (data_last_i)
next_state_r = STATE_TX_CRC1;
end
end
//-----------------------------------------
// TX_CRC1 (first byte)
//-----------------------------------------
STATE_TX_CRC1 :
begin
// Data sent?
if (utmi_txready_i)
next_state_r = STATE_TX_CRC2;
end
//-----------------------------------------
// TX_CRC (second byte)
//-----------------------------------------
STATE_TX_CRC2 :
begin
// Data sent?
if (utmi_txready_i)
next_state_r = STATE_TX_DONE;
end
//-----------------------------------------
// TX_DONE
//-----------------------------------------
STATE_TX_DONE :
begin
// Data sent?
if (!utmi_txvalid_o || utmi_txready_i)
next_state_r = STATE_TX_IDLE;
end
//-----------------------------------------
// TX_CHIRP
//-----------------------------------------
STATE_TX_CHIRP :
begin
if (!chirp_i)
next_state_r = STATE_TX_IDLE;
end
default :
;
endcase
// USB reset but not chirping...
if (!enable_i && !chirp_i)
next_state_r = STATE_TX_IDLE;
end
// Update state
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
state_q <= STATE_TX_IDLE;
else
state_q <= next_state_r;
//-----------------------------------------------------------------
// Data Input
//-----------------------------------------------------------------
reg input_valid_r;
reg [7:0] input_byte_r;
reg input_last_r;
always @ *
begin
input_valid_r = data_strb_i & data_pid_q;
input_byte_r = data_i;
input_last_r = data_last_i;
end
reg data_accept_r;
always @ *
begin
if (state_q == STATE_TX_DATA)
data_accept_r = utmi_txready_i;
else if (state_q == STATE_TX_PID && data_zlp_q)
data_accept_r = utmi_txready_i;
else
data_accept_r = 1'b0;
end
assign data_accept_o = data_accept_r;
//-----------------------------------------------------------------
// CRC16: Generate CRC16 on outgoing data
//-----------------------------------------------------------------
reg [15:0] crc_sum_q;
wire [15:0] crc_out_w;
reg crc_err_q;
usbf_crc16
u_crc16
(
.crc_in_i(crc_sum_q),
.din_i(utmi_data_o),
.crc_out_o(crc_out_w)
);
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
crc_sum_q <= 16'hFFFF;
else if (state_q == STATE_TX_IDLE)
crc_sum_q <= 16'hFFFF;
else if (state_q == STATE_TX_DATA && utmi_txvalid_o && utmi_txready_i)
crc_sum_q <= crc_out_w;
//-----------------------------------------------------------------
// Output
//-----------------------------------------------------------------
reg valid_q;
reg [7:0] data_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
valid_q <= 1'b0;
data_q <= 8'b0;
last_q <= 1'b0;
end
else if (!enable_i)
begin
valid_q <= 1'b0;
data_q <= 8'b0;
last_q <= 1'b0;
end
else if (tx_valid_i && tx_accept_o)
begin
valid_q <= 1'b1;
data_q <= tx_pid_i;
last_q <= 1'b0;
end
else if (utmi_txready_i)
begin
valid_q <= 1'b0;
data_q <= 8'b0;
last_q <= 1'b0;
end
reg utmi_txvalid_r;
reg [7:0] utmi_data_r;
always @ *
begin
if (state_q == STATE_TX_CHIRP)
begin
utmi_txvalid_r = 1'b1;
utmi_data_r = 8'b0;
end
else if (state_q == STATE_TX_CRC1)
begin
utmi_txvalid_r = 1'b1;
utmi_data_r = crc_sum_q[7:0] ^ 8'hFF;
end
else if (state_q == STATE_TX_CRC2)
begin
utmi_txvalid_r = 1'b1;
utmi_data_r = crc_sum_q[15:8] ^ 8'hFF;
end
else if (state_q == STATE_TX_DATA)
begin
utmi_txvalid_r = data_valid_i;
utmi_data_r = data_i;
end
else
begin
utmi_txvalid_r = valid_q;
utmi_data_r = data_q;
end
end
assign utmi_txvalid_o = utmi_txvalid_r;
assign utmi_data_o = utmi_data_r;
endmodule
module usbf_crc16
(
// Inputs
input [ 15:0] crc_in_i
,input [ 7:0] din_i
// Outputs
,output [ 15:0] crc_out_o
);
//-----------------------------------------------------------------
// Logic
//-----------------------------------------------------------------
assign crc_out_o[15] = din_i[0] ^ din_i[1] ^ din_i[2] ^ din_i[3] ^ din_i[4] ^ din_i[5] ^ din_i[6] ^ din_i[7] ^
crc_in_i[7] ^ crc_in_i[6] ^ crc_in_i[5] ^ crc_in_i[4] ^ crc_in_i[3] ^ crc_in_i[2] ^ crc_in_i[1] ^ crc_in_i[0];
assign crc_out_o[14] = din_i[0] ^ din_i[1] ^ din_i[2] ^ din_i[3] ^ din_i[4] ^ din_i[5] ^ din_i[6] ^
crc_in_i[6] ^ crc_in_i[5] ^ crc_in_i[4] ^ crc_in_i[3] ^ crc_in_i[2] ^ crc_in_i[1] ^ crc_in_i[0];
assign crc_out_o[13] = din_i[6] ^ din_i[7] ^
crc_in_i[7] ^ crc_in_i[6];
assign crc_out_o[12] = din_i[5] ^ din_i[6] ^
crc_in_i[6] ^ crc_in_i[5];
assign crc_out_o[11] = din_i[4] ^ din_i[5] ^
crc_in_i[5] ^ crc_in_i[4];
assign crc_out_o[10] = din_i[3] ^ din_i[4] ^
crc_in_i[4] ^ crc_in_i[3];
assign crc_out_o[9] = din_i[2] ^ din_i[3] ^
crc_in_i[3] ^ crc_in_i[2];
assign crc_out_o[8] = din_i[1] ^ din_i[2] ^
crc_in_i[2] ^ crc_in_i[1];
assign crc_out_o[7] = din_i[0] ^ din_i[1] ^
crc_in_i[15] ^ crc_in_i[1] ^ crc_in_i[0];
assign crc_out_o[6] = din_i[0] ^
crc_in_i[14] ^ crc_in_i[0];
assign crc_out_o[5] = crc_in_i[13];
assign crc_out_o[4] = crc_in_i[12];
assign crc_out_o[3] = crc_in_i[11];
assign crc_out_o[2] = crc_in_i[10];
assign crc_out_o[1] = crc_in_i[9];
assign crc_out_o[0] = din_i[0] ^ din_i[1] ^ din_i[2] ^ din_i[3] ^ din_i[4] ^ din_i[5] ^ din_i[6] ^ din_i[7] ^
crc_in_i[8] ^ crc_in_i[7] ^ crc_in_i[6] ^ crc_in_i[5] ^ crc_in_i[4] ^ crc_in_i[3] ^ crc_in_i[2] ^ crc_in_i[1] ^ crc_in_i[0];
endmodule |
//==================================================================================================
// Filename : musb_memwb_register.v
// Created On : 2014-09-27 20:36:16
// Last Modified : 2015-05-31 13:04:39
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : Pipeline register: MEM -> WB
//==================================================================================================
module musb_memwb_register(
input clk, // main clock
input rst, // main reset
input [31:0] mem_read_data, // data from Memory
input [31:0] mem_alu_data, // data from ALU
input [4:0] mem_gpr_wa, // GPR write enable
input mem_mem_to_gpr_select, // select MEM/ALU to GPR
input mem_gpr_we, // GPR write enable
input mem_flush,
input mem_stall, // stall MEM stage
input wb_stall, // stall WB stage
output reg [31:0] wb_read_data, // data from Memory
output reg [31:0] wb_alu_data, // data from ALU
output reg [4:0] wb_gpr_wa, // GPR write address
output reg wb_mem_to_gpr_select, // select MEM/ALU to GPR
output reg wb_gpr_we // GPR write enable
);
//--------------------------------------------------------------------------
// Propagate signals
//--------------------------------------------------------------------------
always @(posedge clk) begin
wb_read_data <= (rst) ? 31'b0 : ((wb_stall) ? wb_read_data : mem_read_data);
wb_alu_data <= (rst) ? 31'b0 : ((wb_stall) ? wb_alu_data : mem_alu_data);
wb_gpr_wa <= (rst) ? 5'b0 : ((wb_stall) ? wb_gpr_wa : mem_gpr_wa);
wb_mem_to_gpr_select <= (rst) ? 1'b0 : ((wb_stall) ? wb_mem_to_gpr_select : mem_mem_to_gpr_select);
wb_gpr_we <= (rst) ? 1'b0 : ((wb_stall) ? wb_gpr_we : ((mem_stall | mem_flush) ? 1'b0 : mem_gpr_we));
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:25:10 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W64_EW11_SW52 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [63:0] Data_MX;
input [63:0] Data_MY;
input [1:0] round_mode;
output [63:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, Sgf_operation_Result_28_, n287, n289,
n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, n300,
n301, n302, n303, n304, n305, n306, n307, n308, n309, n310, n311,
n312, n313, n314, n315, n316, n317, n318, n319, n320, n321, n322,
n323, n324, n325, n326, n327, n328, n329, n330, n331, n332, n333,
n334, n335, n336, n337, n338, n339, n340, n341, n342, n343, n344,
n345, n346, n347, n348, n349, n350, n351, n352, n353, n354, n355,
n356, n357, n358, n359, n360, n361, n362, n363, n364, n365, n366,
n367, n368, n369, n370, n400, n405, n406, n407, n408, n409, n410,
n411, n412, n413, n414, n415, n416, n418, n419, n421, n423, n424,
n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435,
n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446,
n447, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458,
n459, n460, n461, n462, n463, n464, n465, n467, n468, n469, n470,
n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481,
n482, n483, n484, n485, n486, n487, n488, n489, n490, n492, n493,
n494, n495, n496, n497, n498, n499, n526, n527, n528, n529, n530,
n531, n532, n533, n534, n535, n536, n537, n538, n539, n540, n541,
n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552,
n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, n563,
n564, n565, n566, n567, n568, n569, n570, n571, n572, n573, n574,
n575, n576, n577, n578, n579, n580, n581, n582, n583, n584, n585,
n586, n587, n588, n589, n590, n591, n592, n593, n594, n595, n596,
n597, n598, n599, n600, n601, n602, n603, n604, n605, n606, n607,
n608, n609, n611, n613, n614, n615, n616, n617, n618, n619, n620,
n621, n622, n623, n624, n625, n626, n627, n628, n629, n630, n631,
n632, n633, n634, n635, n636, n637, n638, n639, n640, n641, n642,
n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, n653,
n654, n656, n658, n660, n661, n662, n664, n665, n666, n668, n670,
n671, n672, n673, n674, n675, n677, n679, n680, n681, n683, n684,
n685, n686, n688, n690, n691, n693, n694, n695, n696, n698, n699,
n700, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n714, n715, DP_OP_168J26_122_4811_n8545,
DP_OP_168J26_122_4811_n8544, DP_OP_168J26_122_4811_n8543,
DP_OP_168J26_122_4811_n8539, DP_OP_168J26_122_4811_n8538,
DP_OP_168J26_122_4811_n8537, DP_OP_168J26_122_4811_n8535,
DP_OP_168J26_122_4811_n8534, DP_OP_168J26_122_4811_n8533,
DP_OP_168J26_122_4811_n8529, DP_OP_168J26_122_4811_n8527,
DP_OP_168J26_122_4811_n8525, DP_OP_168J26_122_4811_n8520,
DP_OP_168J26_122_4811_n8518, DP_OP_168J26_122_4811_n8517,
DP_OP_168J26_122_4811_n8516, DP_OP_168J26_122_4811_n8513,
DP_OP_168J26_122_4811_n8511, DP_OP_168J26_122_4811_n8510,
DP_OP_168J26_122_4811_n8507, DP_OP_168J26_122_4811_n8506,
DP_OP_168J26_122_4811_n8504, DP_OP_168J26_122_4811_n8503,
DP_OP_168J26_122_4811_n8502, DP_OP_168J26_122_4811_n8501,
DP_OP_168J26_122_4811_n8500, DP_OP_168J26_122_4811_n8499,
DP_OP_168J26_122_4811_n8498, DP_OP_168J26_122_4811_n8493,
DP_OP_168J26_122_4811_n8490, DP_OP_168J26_122_4811_n8489,
DP_OP_168J26_122_4811_n8488, DP_OP_168J26_122_4811_n8487,
DP_OP_168J26_122_4811_n8486, DP_OP_168J26_122_4811_n8484,
DP_OP_168J26_122_4811_n8482, DP_OP_168J26_122_4811_n8481,
DP_OP_168J26_122_4811_n8480, DP_OP_168J26_122_4811_n8479,
DP_OP_168J26_122_4811_n8478, DP_OP_168J26_122_4811_n8477,
DP_OP_168J26_122_4811_n8474, DP_OP_168J26_122_4811_n8473,
DP_OP_168J26_122_4811_n8472, DP_OP_168J26_122_4811_n8471,
DP_OP_168J26_122_4811_n8469, DP_OP_168J26_122_4811_n8467,
DP_OP_168J26_122_4811_n8465, DP_OP_168J26_122_4811_n8464,
DP_OP_168J26_122_4811_n8463, DP_OP_168J26_122_4811_n8461,
DP_OP_168J26_122_4811_n8460, DP_OP_168J26_122_4811_n8459,
DP_OP_168J26_122_4811_n8456, DP_OP_168J26_122_4811_n8453,
DP_OP_168J26_122_4811_n8451, DP_OP_168J26_122_4811_n8449,
DP_OP_168J26_122_4811_n8448, DP_OP_168J26_122_4811_n8447,
DP_OP_168J26_122_4811_n8446, DP_OP_168J26_122_4811_n8250,
DP_OP_168J26_122_4811_n8249, DP_OP_168J26_122_4811_n8246,
DP_OP_168J26_122_4811_n8245, DP_OP_168J26_122_4811_n8242,
DP_OP_168J26_122_4811_n8223, DP_OP_168J26_122_4811_n8221,
DP_OP_168J26_122_4811_n8220, DP_OP_168J26_122_4811_n8218,
DP_OP_168J26_122_4811_n8216, DP_OP_168J26_122_4811_n8200,
DP_OP_168J26_122_4811_n8199, DP_OP_168J26_122_4811_n8198,
DP_OP_168J26_122_4811_n8197, DP_OP_168J26_122_4811_n8196,
DP_OP_168J26_122_4811_n8194, DP_OP_168J26_122_4811_n8193,
DP_OP_168J26_122_4811_n8191, DP_OP_168J26_122_4811_n8190,
DP_OP_168J26_122_4811_n8189, DP_OP_168J26_122_4811_n8187,
DP_OP_168J26_122_4811_n8177, DP_OP_168J26_122_4811_n8166,
DP_OP_168J26_122_4811_n8163, DP_OP_168J26_122_4811_n8034,
DP_OP_168J26_122_4811_n8030, DP_OP_168J26_122_4811_n8003,
DP_OP_168J26_122_4811_n7949, DP_OP_168J26_122_4811_n7818,
DP_OP_168J26_122_4811_n6794, DP_OP_168J26_122_4811_n6782,
DP_OP_168J26_122_4811_n6776, DP_OP_168J26_122_4811_n6644,
DP_OP_168J26_122_4811_n6643, DP_OP_168J26_122_4811_n6641,
DP_OP_168J26_122_4811_n6620, DP_OP_168J26_122_4811_n6619,
DP_OP_168J26_122_4811_n6618, DP_OP_168J26_122_4811_n6617,
DP_OP_168J26_122_4811_n6616, DP_OP_168J26_122_4811_n6615,
DP_OP_168J26_122_4811_n6614, DP_OP_168J26_122_4811_n6613,
DP_OP_168J26_122_4811_n6611, DP_OP_168J26_122_4811_n6610,
DP_OP_168J26_122_4811_n6609, DP_OP_168J26_122_4811_n6608,
DP_OP_168J26_122_4811_n6594, DP_OP_168J26_122_4811_n6591,
DP_OP_168J26_122_4811_n6589, DP_OP_168J26_122_4811_n6588,
DP_OP_168J26_122_4811_n6587, DP_OP_168J26_122_4811_n6586,
DP_OP_168J26_122_4811_n6584, DP_OP_168J26_122_4811_n6579,
DP_OP_168J26_122_4811_n6569, DP_OP_168J26_122_4811_n6563,
DP_OP_168J26_122_4811_n6562, DP_OP_168J26_122_4811_n6559,
DP_OP_168J26_122_4811_n6172, DP_OP_168J26_122_4811_n6171,
DP_OP_168J26_122_4811_n5214, DP_OP_168J26_122_4811_n5162,
DP_OP_168J26_122_4811_n5160, DP_OP_168J26_122_4811_n5154,
DP_OP_168J26_122_4811_n3609, DP_OP_168J26_122_4811_n3607,
DP_OP_168J26_122_4811_n3605, DP_OP_168J26_122_4811_n3603,
DP_OP_168J26_122_4811_n3602, DP_OP_168J26_122_4811_n3596,
DP_OP_168J26_122_4811_n3595, DP_OP_168J26_122_4811_n3590,
DP_OP_168J26_122_4811_n3581, DP_OP_168J26_122_4811_n3579,
DP_OP_168J26_122_4811_n3578, DP_OP_168J26_122_4811_n3572,
DP_OP_168J26_122_4811_n3571, DP_OP_168J26_122_4811_n3560,
DP_OP_168J26_122_4811_n3553, DP_OP_168J26_122_4811_n3552,
DP_OP_168J26_122_4811_n3542, DP_OP_168J26_122_4811_n3541,
DP_OP_168J26_122_4811_n3536, DP_OP_168J26_122_4811_n3520,
DP_OP_168J26_122_4811_n3519, DP_OP_168J26_122_4811_n3508,
DP_OP_168J26_122_4811_n3498, DP_OP_168J26_122_4811_n3497,
DP_OP_168J26_122_4811_n3486, DP_OP_168J26_122_4811_n3475,
DP_OP_168J26_122_4811_n3445, DP_OP_168J26_122_4811_n3258,
DP_OP_168J26_122_4811_n3245, DP_OP_168J26_122_4811_n3238,
DP_OP_168J26_122_4811_n3232, DP_OP_168J26_122_4811_n3229,
DP_OP_168J26_122_4811_n3228, DP_OP_168J26_122_4811_n3227,
DP_OP_168J26_122_4811_n3224, DP_OP_168J26_122_4811_n3223,
DP_OP_168J26_122_4811_n3219, DP_OP_168J26_122_4811_n3215,
DP_OP_168J26_122_4811_n3214, DP_OP_168J26_122_4811_n3212,
DP_OP_168J26_122_4811_n1487, DP_OP_168J26_122_4811_n1456,
DP_OP_168J26_122_4811_n1455, DP_OP_168J26_122_4811_n1422,
DP_OP_168J26_122_4811_n1421, DP_OP_168J26_122_4811_n1389,
DP_OP_168J26_122_4811_n1388, DP_OP_168J26_122_4811_n1387,
DP_OP_168J26_122_4811_n1358, DP_OP_168J26_122_4811_n1356,
DP_OP_168J26_122_4811_n1320, DP_OP_168J26_122_4811_n1319,
DP_OP_168J26_122_4811_n1286, DP_OP_168J26_122_4811_n1285,
DP_OP_168J26_122_4811_n1254, DP_OP_168J26_122_4811_n1253,
DP_OP_168J26_122_4811_n1222, DP_OP_168J26_122_4811_n1221,
DP_OP_168J26_122_4811_n1193, DP_OP_168J26_122_4811_n1192,
DP_OP_168J26_122_4811_n1191, DP_OP_168J26_122_4811_n1166,
DP_OP_168J26_122_4811_n1165, DP_OP_168J26_122_4811_n1164,
DP_OP_168J26_122_4811_n1163, DP_OP_168J26_122_4811_n1136,
DP_OP_168J26_122_4811_n1106, DP_OP_168J26_122_4811_n1105,
DP_OP_168J26_122_4811_n1080, DP_OP_168J26_122_4811_n1079,
DP_OP_168J26_122_4811_n1054, DP_OP_168J26_122_4811_n1053,
DP_OP_168J26_122_4811_n1030, DP_OP_168J26_122_4811_n1029,
DP_OP_168J26_122_4811_n1006, DP_OP_168J26_122_4811_n1005,
DP_OP_168J26_122_4811_n984, DP_OP_168J26_122_4811_n776,
DP_OP_168J26_122_4811_n768, DP_OP_168J26_122_4811_n745,
DP_OP_168J26_122_4811_n743, DP_OP_168J26_122_4811_n662,
DP_OP_168J26_122_4811_n654, DP_OP_168J26_122_4811_n643,
DP_OP_168J26_122_4811_n638, DP_OP_168J26_122_4811_n637,
DP_OP_168J26_122_4811_n627, DP_OP_168J26_122_4811_n626,
DP_OP_168J26_122_4811_n619, DP_OP_168J26_122_4811_n614,
DP_OP_168J26_122_4811_n613, DP_OP_168J26_122_4811_n606,
DP_OP_168J26_122_4811_n592, DP_OP_168J26_122_4811_n591,
DP_OP_168J26_122_4811_n588, DP_OP_168J26_122_4811_n586,
DP_OP_168J26_122_4811_n579, DP_OP_168J26_122_4811_n575,
DP_OP_168J26_122_4811_n572, DP_OP_168J26_122_4811_n564,
DP_OP_168J26_122_4811_n553, DP_OP_168J26_122_4811_n551,
DP_OP_168J26_122_4811_n543, DP_OP_168J26_122_4811_n534,
DP_OP_168J26_122_4811_n525, DP_OP_168J26_122_4811_n514,
DP_OP_168J26_122_4811_n376, DP_OP_168J26_122_4811_n374,
DP_OP_168J26_122_4811_n365, DP_OP_168J26_122_4811_n348,
DP_OP_168J26_122_4811_n333, DP_OP_168J26_122_4811_n318,
DP_OP_168J26_122_4811_n303, DP_OP_168J26_122_4811_n288,
DP_OP_168J26_122_4811_n285, DP_OP_168J26_122_4811_n265,
DP_OP_168J26_122_4811_n254, DP_OP_168J26_122_4811_n203,
DP_OP_168J26_122_4811_n201, DP_OP_168J26_122_4811_n200,
DP_OP_168J26_122_4811_n183, DP_OP_168J26_122_4811_n173,
DP_OP_168J26_122_4811_n172, DP_OP_168J26_122_4811_n170,
DP_OP_168J26_122_4811_n160, DP_OP_168J26_122_4811_n137,
DP_OP_168J26_122_4811_n136, DP_OP_168J26_122_4811_n135,
DP_OP_168J26_122_4811_n134, DP_OP_168J26_122_4811_n133,
DP_OP_168J26_122_4811_n132, DP_OP_168J26_122_4811_n131,
DP_OP_168J26_122_4811_n130, DP_OP_168J26_122_4811_n129,
DP_OP_168J26_122_4811_n128, DP_OP_168J26_122_4811_n127,
DP_OP_168J26_122_4811_n107, DP_OP_168J26_122_4811_n106,
DP_OP_168J26_122_4811_n105, DP_OP_168J26_122_4811_n104,
DP_OP_168J26_122_4811_n103, DP_OP_168J26_122_4811_n102,
DP_OP_168J26_122_4811_n101, DP_OP_168J26_122_4811_n100,
DP_OP_168J26_122_4811_n99, DP_OP_168J26_122_4811_n98,
DP_OP_168J26_122_4811_n97, DP_OP_168J26_122_4811_n96,
DP_OP_168J26_122_4811_n95, add_x_19_n830, add_x_19_n774,
add_x_19_n770, add_x_19_n763, add_x_19_n762, add_x_19_n755,
add_x_19_n754, add_x_19_n748, add_x_19_n747, add_x_19_n745,
add_x_19_n739, add_x_19_n738, add_x_19_n734, add_x_19_n733,
add_x_19_n725, add_x_19_n718, add_x_19_n705, add_x_19_n703,
add_x_19_n702, add_x_19_n322, add_x_19_n313, add_x_19_n310,
add_x_19_n289, add_x_19_n278, add_x_19_n263, add_x_19_n252,
add_x_19_n239, add_x_19_n228, add_x_19_n213, add_x_19_n202,
add_x_19_n189, add_x_19_n178, add_x_19_n165, add_x_19_n154,
add_x_19_n130, add_x_19_n121, add_x_19_n120, add_x_19_n108,
add_x_19_n97, add_x_19_n84, add_x_19_n70, add_x_19_n69, add_x_19_n68,
add_x_19_n67, n728, n729, n730, n731, n732, n733, n734, n735, n736,
n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747,
n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, n758,
n759, n760, n762, n763, n764, n765, n766, n767, n768, n769, n770,
n771, n772, n773, n774, n775, n776, n777, n778, n779, n780, n781,
n782, n783, n784, n785, n786, n787, n788, n789, n790, n791, n793,
n794, n795, n796, n797, n798, n799, n800, n801, n803, n804, n805,
n806, n807, n808, n809, n810, n811, n812, n813, n814, n815, n816,
n817, n818, n819, n820, n821, n822, n823, n824, n825, n826, n827,
n828, n829, n830, n831, n832, n834, n835, n836, n837, n838, n839,
n840, n841, n843, n844, n845, n848, n849, n850, n851, n852, n853,
n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, n864,
n865, n866, n867, n868, n869, n871, n872, n873, n874, n875, n876,
n877, n878, n879, n880, n881, n882, n883, n886, n887, n888, n889,
n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, n902,
n904, n905, n906, n907, n908, n909, n910, n911, n912, n913, n914,
n915, n916, n917, n918, n919, n920, n921, n922, n923, n924, n925,
n926, n927, n928, n929, n930, n931, n932, n933, n934, n935, n936,
n937, n938, n940, n941, n942, n943, n944, n945, n947, n948, n949,
n950, n951, n952, n953, n954, n955, n956, n958, n959, n960, n961,
n962, n963, n964, n965, n966, n967, n969, n970, n971, n972, n973,
n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n989,
n990, n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000,
n1001, n1002, n1003, n1004, n1005, n1006, n1008, n1009, n1010, n1011,
n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021,
n1022, n1023, n1024, n1025, n1027, n1028, n1029, n1030, n1031, n1032,
n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1042, n1043,
n1044, n1045, n1046, n1048, n1049, n1050, n1051, n1052, n1053, n1054,
n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064,
n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074,
n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084,
n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094,
n1095, n1096, n1097, n1098, n1099, n1100, n1102, n1103, n1104, n1105,
n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115,
n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125,
n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135,
n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145,
n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155,
n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165,
n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175,
n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185,
n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195,
n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205,
n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215,
n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225,
n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235,
n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245,
n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255,
n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265,
n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275,
n1276, n1277, n1278, n1279, n1280, n1281, n1283, n1284, n1285, n1286,
n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1329, n1330, n1331, n1332, n1333, n1334, n1336, n1337, n1338, n1339,
n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349,
n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359,
n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369,
n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379,
n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389,
n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399,
n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409,
n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419,
n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429,
n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439,
n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449,
n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459,
n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469,
n1470, n1471, n1472, n1473, n1474, n1475, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512,
n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522,
n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532,
n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542,
n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552,
n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563,
n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573,
n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583,
n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593,
n1594, n1595, n1596, n1598, n1599, n1600, n1601, n1602, n1603, n1604,
n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614,
n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624,
n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634,
n1635, n1636, n1637, n1638, n1639, n1640, n1642, n1643, n1644, n1645,
n1647, n1649, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658,
n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1668, n1669,
n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679,
n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689,
n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699,
n1700, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710,
n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1721,
n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731,
n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741,
n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1752,
n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772,
n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782,
n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822,
n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832,
n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842,
n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852,
n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862,
n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872,
n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882,
n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892,
n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902,
n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912,
n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922,
n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932,
n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942,
n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952,
n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962,
n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972,
n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982,
n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992,
n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002,
n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012,
n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022,
n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032,
n2033, n2034, n2035, n2036, n2037, n2038, n2040, n2041, n2042, n2043,
n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053,
n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063,
n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073,
n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083,
n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093,
n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2102, n2103, n2104,
n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114,
n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124,
n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2134, n2135,
n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145,
n2146, n2147, n2148, n2149, n2150, n2152, n2153, n2154, n2155, n2156,
n2157, n2158, n2159, n2160, n2161, n2162, n2164, n2165, n2167, n2168,
n2169, n2170, n2171, n2172, n2173, n2175, n2176, n2177, n2178, n2179,
n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189,
n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199,
n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209,
n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219,
n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229,
n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239,
n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249,
n2250, n2251, n2252, n2254, n2255, n2256, n2257, n2258, n2259, n2261,
n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271,
n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281,
n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291,
n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301,
n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311,
n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321,
n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2330, n2331, n2332,
n2333, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2344,
n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354,
n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364,
n2365, n2366, n2367, n2369, n2370, n2371, n2372, n2373, n2374, n2375,
n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2384, n2385, n2386,
n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396,
n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406,
n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416,
n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426,
n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437,
n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447,
n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457,
n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467,
n2469, n2470, n2471, n2473, n2474, n2475, n2476, n2477, n2479, n2480,
n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490,
n2491, n2492, n2493, n2494, n2495, n2497, n2498, n2499, n2500, n2501,
n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2512,
n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522,
n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2533,
n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543,
n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553,
n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563,
n2564, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574,
n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584,
n2585, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595,
n2596, n2597, n2599, n2600, n2601, n2602, n2603, n2604, n2605, n2606,
n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616,
n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626,
n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636,
n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646,
n2647, n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657,
n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667,
n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677,
n2679, n2680, n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689,
n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699,
n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709,
n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719,
n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729,
n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739,
n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749,
n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759,
n2761, n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771,
n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781,
n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791,
n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801,
n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811,
n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821,
n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831,
n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841,
n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851,
n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861,
n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871,
n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881,
n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891,
n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901,
n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911,
n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921,
n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931,
n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941,
n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951,
n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961,
n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971,
n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981,
n2982, n2983, n2984, n2985, n2987, n2988, n2989, n2990, n2991, n2992,
n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002,
n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012,
n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022,
n3023, n3024, n3025, n3026, n3027, n3028, n3030, n3031, n3032, n3033,
n3034, n3035, n3036, n3037, n3038, n3040, n3041, n3042, n3043, n3044,
n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054,
n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064,
n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074,
n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084,
n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094,
n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104,
n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114,
n3115, n3116, n3117, n3118, n3119, n3120, n3122, n3123, n3124, n3125,
n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134, n3135,
n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144, n3145,
n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154, n3155,
n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164, n3165,
n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174, n3175,
n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184, n3185,
n3186, n3187, n3188, n3189, n3191, n3193, n3194, n3195, n3196, n3197,
n3198, n3199, n3200, n3201, n3202, n3203, n3204, n3205, n3206, n3207,
n3208, n3209, n3210, n3211, n3212, n3213, n3214, n3215, n3216, n3217,
n3218, n3219, n3220, n3221, n3222, n3223, n3224, n3225, n3226, n3227,
n3228, n3229, n3230, n3231, n3232, n3233, n3234, n3235, n3236, n3237,
n3238, n3239, n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3247,
n3248, n3249, n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257,
n3258, n3259, n3260, n3261, n3262, n3263, n3264, n3265, n3266, n3267,
n3269, n3270, n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278,
n3279, n3280, n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289,
n3290, n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299,
n3300, n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309,
n3310, n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319,
n3320, n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329,
n3330, n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339,
n3340, n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349,
n3350, n3351, n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359,
n3360, n3361, n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369,
n3370, n3371, n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379,
n3380, n3381, n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389,
n3390, n3391, n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399,
n3400, n3401, n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409,
n3410, n3411, n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419,
n3420, n3421, n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429,
n3430, n3431, n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439,
n3440, n3441, n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449,
n3450, n3451, n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459,
n3460, n3461, n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469,
n3470, n3471, n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479,
n3480, n3481, n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489,
n3490, n3491, n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499,
n3500, n3501, n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509,
n3510, n3511, n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519,
n3520, n3521, n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529,
n3530, n3531, n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539,
n3540, n3541, n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549,
n3550, n3551, n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559,
n3560, n3561, n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569,
n3570, n3571, n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579,
n3580, n3581, n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589,
n3590, n3591, n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599,
n3600, n3601, n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609,
n3610, n3611, n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619,
n3620, n3621, n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629,
n3630, n3631, n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639,
n3640, n3641, n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649,
n3650, n3651, n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659,
n3660, n3661, n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669,
n3670, n3671, n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679,
n3680, n3681, n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689,
n3690, n3691, n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699,
n3700, n3701, n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709,
n3710, n3711, n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719,
n3720, n3721, n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729,
n3730, n3731, n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739,
n3740, n3741, n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749,
n3750, n3751, n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759,
n3760, n3761, n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769,
n3770, n3771, n3772, n3773, n3774, n3775, n3776, n3777, n3778, n3779,
n3780, n3781, n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789,
n3790, n3791, n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799,
n3800, n3801, n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809,
n3810, n3811, n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819,
n3820, n3821, n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829,
n3830, n3831, n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839,
n3840, n3841, n3842, n3844, n3845, n3846, n3847, n3848, n3849, n3850,
n3851, n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860,
n3861, n3862, n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870,
n3871, n3872, n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880,
n3881, n3882, n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890,
n3891, n3892, n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900,
n3901, n3902, n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910,
n3911, n3912, n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920,
n3921, n3922, n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930,
n3931, n3932, n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940,
n3941, n3942, n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950,
n3951, n3952, n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960,
n3961, n3962, n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970,
n3971, n3972, n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980,
n3981, n3982, n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990,
n3991, n3992, n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000,
n4001, n4002, n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010,
n4011, n4012, n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020,
n4021, n4022, n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030,
n4031, n4032, n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040,
n4041, n4042, n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050,
n4051, n4052, n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060,
n4061, n4062, n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070,
n4071, n4072, n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080,
n4081, n4082, n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090,
n4091, n4092, n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100,
n4101, n4102, n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110,
n4111, n4112, n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120,
n4121, n4122, n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130,
n4131, n4132, n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140,
n4141, n4142, n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150,
n4151, n4152, n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160,
n4161, n4162, n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170,
n4171, n4172, n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180,
n4181, n4182, n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190,
n4191, n4192, n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200,
n4201, n4202, n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210,
n4211, n4212, n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220,
n4221, n4222, n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230,
n4231, n4232, n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240,
n4241, n4242, n4243, n4244, n4245, n4246, n4247, n4248, n4249, n4250,
n4251, n4252, n4253, n4254, n4255, n4256, n4257, n4258, n4259, n4260,
n4261, n4262, n4263, n4264, n4265, n4266, n4267, n4268, n4269, n4270,
n4271, n4272, n4273, n4274, n4275, n4276, n4277, n4278, n4279, n4280,
n4281, n4282, n4283, n4284, n4285, n4286, n4287, n4288, n4289, n4290,
n4291, n4292, n4293, n4294, n4295, n4296, n4297, n4298, n4299, n4300,
n4301, n4302, n4303, n4304, n4305, n4306, n4307, n4308, n4309, n4310,
n4311, n4312, n4313, n4314, n4315, n4316, n4317, n4318, n4319, n4320,
n4321, n4322, n4323, n4324, n4325, n4326, n4327, n4328, n4329, n4330,
n4331, n4332, n4333, n4334, n4335, n4336, n4337, n4338, n4339, n4340,
n4341, n4342, n4343, n4344, n4345, n4346, n4347, n4348, n4349, n4350,
n4351, n4352, n4353, n4354, n4355, n4356, n4357, n4358, n4359, n4360,
n4361, n4362, n4363, n4364, n4365, n4366, n4367, n4368, n4369, n4370,
n4371, n4372, n4373, n4374, n4375, n4376, n4377, n4378, n4379, n4380,
n4381, n4382, n4383, n4384, n4385, n4386, n4387, n4388, n4389, n4390,
n4391, n4392, n4393, n4394, n4395, n4396, n4397, n4398, n4399, n4400,
n4401, n4402, n4403, n4404, n4405, n4406, n4407, n4408, n4409, n4410,
n4411, n4412, n4413, n4414, n4415, n4416, n4417, n4418, n4419, n4420,
n4421, n4422, n4423, n4424, n4425, n4426, n4427, n4428, n4429, n4430,
n4431, n4432, n4433, n4434, n4435, n4436, n4437, n4438, n4439, n4440,
n4441, n4442, n4443, n4444, n4445, n4446, n4447, n4448, n4449, n4450,
n4451, n4452, n4453, n4454, n4455, n4456, n4457, n4458, n4459, n4460,
n4461, n4462, n4463, n4464, n4465, n4466, n4467, n4468, n4469, n4470,
n4471, n4472, n4473, n4474, n4475, n4476, n4477, n4478, n4479, n4480,
n4481, n4482, n4483, n4484, n4485, n4487, n4488, n4489, n4490, n4491,
n4492, n4493, n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501,
n4502, n4503, n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511,
n4512, n4513, n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521,
n4522, n4523, n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531,
n4532, n4533, n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541,
n4542, n4543, n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551,
n4552, n4553, n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561,
n4562, n4563, n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571,
n4572, n4573, n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581,
n4582, n4583, n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591,
n4592, n4593, n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601,
n4602, n4603, n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611,
n4612, n4613, n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621,
n4622, n4623, n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631,
n4632, n4633, n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641,
n4642, n4643, n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651,
n4652, n4653, n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661,
n4662, n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671,
n4672, n4673, n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681,
n4682, n4683, n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691,
n4692, n4693, n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701,
n4702, n4703, n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711,
n4712, n4713, n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721,
n4722, n4723, n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731,
n4732, n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741,
n4742, n4743, n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751,
n4752, n4753, n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761,
n4762, n4763, n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771,
n4772, n4773, n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781,
n4782, n4783, n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791,
n4792, n4793, n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801,
n4802, n4803, n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811,
n4812, n4813, n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821,
n4822, n4823, n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831,
n4832, n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841,
n4842, n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851,
n4852, n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861,
n4862, n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871,
n4872, n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881,
n4882, n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891,
n4892, n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901,
n4902, n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911,
n4912, n4913, n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4922,
n4923, n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931, n4932,
n4933, n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941, n4942,
n4943, n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951, n4952,
n4953, n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961, n4962,
n4963, n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971, n4972,
n4973, n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981, n4982,
n4983, n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991, n4992,
n4993, n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001, n5002,
n5003, n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011, n5012,
n5013, n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021, n5022,
n5023, n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031, n5032,
n5033, n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041, n5042,
n5043, n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051, n5052,
n5053, n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061, n5062,
n5063, n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071, n5072,
n5073, n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081, n5082,
n5083, n5084, n5085, n5086, n5087, n5088, n5089, n5090, n5091, n5092,
n5093, n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101, n5102,
n5103, n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111, n5112,
n5113, n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121, n5122,
n5123, n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131, n5132,
n5133, n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141, n5142,
n5143, n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151, n5152,
n5153, n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161, n5162,
n5163, n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171, n5172,
n5173, n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181, n5182,
n5183, n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191, n5192,
n5193, n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201, n5202,
n5203, n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211, n5212,
n5213, n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221, n5222,
n5223, n5224, n5225, n5226, n5227, n5228, n5229, n5230, n5231, n5232,
n5233, n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241, n5242,
n5243, n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251, n5252,
n5253, n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261, n5262,
n5263, n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271, n5272,
n5273, n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281, n5282,
n5283, n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291, n5292,
n5293, n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301, n5302,
n5303, n5304, n5305, n5306, n5307, n5308, n5309, n5310, n5311, n5312,
n5313, n5314, n5315, n5316, n5317, n5318, n5319, n5320, n5321, n5322,
n5323, n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5331, n5332,
n5333, n5334, n5335, n5336, n5337, n5338, n5339, n5340, n5341, n5342,
n5343, n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352,
n5353, n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5361, n5362,
n5363, n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372,
n5373, n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382,
n5383, n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392,
n5393, n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402,
n5403, n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411, n5412,
n5413, n5414, n5415, n5416, n5417, n5418, n5419, n5420, n5421, n5422,
n5423, n5424, n5425, n5426, n5427, n5428, n5429, n5430, n5431, n5432,
n5433, n5434, n5435, n5436, n5437, n5438, n5439, n5440, n5441, n5442,
n5443, n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451, n5452,
n5453, n5454, n5455, n5456, n5457, n5458, n5459, n5460, n5461, n5462,
n5463, n5464, n5465, n5466, n5467, n5468, n5469, n5470, n5471, n5472,
n5473, n5474, n5475, n5476, n5477, n5478, n5479, n5480, n5481, n5482,
n5483, n5484, n5485, n5486, n5487, n5488, n5489, n5490, n5491, n5492,
n5493, n5494, n5495, n5496, n5497, n5498, n5499, n5500, n5501, n5502,
n5503, n5504, n5505, n5506, n5507, n5508, n5509, n5510, n5511, n5512,
n5513, n5514, n5515, n5516, n5517, n5518, n5519, n5520, n5521, n5522,
n5523, n5524, n5525, n5526, n5527, n5528, n5529, n5530, n5531, n5532,
n5533, n5534, n5535, n5536, n5537, n5538, n5539, n5540, n5541, n5542,
n5543, n5544, n5545, n5546, n5547, n5548, n5549, n5550, n5551, n5552,
n5553, n5554, n5555, n5556, n5557, n5558, n5559, n5560, n5561, n5562,
n5563, n5564, n5565, n5566, n5567, n5568, n5569, n5570, n5571, n5572,
n5573, n5574, n5575, n5576, n5577, n5578, n5579, n5580, n5581, n5582,
n5583, n5584, n5585, n5586, n5587, n5588, n5589, n5590, n5591, n5592,
n5593, n5594, n5595, n5596, n5597, n5598, n5599, n5600, n5601, n5602,
n5603, n5604, n5605, n5606, n5607, n5608, n5609, n5610, n5611, n5612,
n5613, n5614, n5615, n5616, n5617, n5618, n5619, n5620, n5621, n5622,
n5623, n5624, n5625, n5626, n5627, n5628, n5629, n5630, n5631, n5632,
n5633, n5634, n5635, n5636, n5637, n5638, n5639, n5640, n5641, n5642,
n5643, n5644, n5645, n5646, n5647, n5648, n5649, n5650, n5651, n5652,
n5653, n5654, n5655, n5656, n5657, n5658, n5659, n5660, n5661, n5662,
n5663, n5665, n5666, n5667, n5668, n5669, n5670, n5671, n5672, n5673,
n5674, n5675, n5676, n5677, n5678, n5679, n5680, n5681, n5682, n5683,
n5684, n5685, n5686, n5687, n5688, n5689, n5690, n5691, n5692, n5693,
n5694, n5695, n5696, n5697, n5698, n5699, n5700, n5701, n5702, n5703,
n5704, n5705, n5706, n5707, n5708, n5709, n5710, n5711, n5712, n5713,
n5714, n5715, n5716, n5717, n5718, n5719, n5720, n5721, n5722, n5723,
n5724, n5725, n5726, n5727, n5728, n5729, n5730, n5731, n5732, n5733,
n5734, n5735, n5736, n5737, n5738, n5739, n5740, n5741, n5742, n5743,
n5744, n5745, n5746, n5747, n5748, n5749, n5750, n5751, n5752, n5753,
n5754, n5755, n5756, n5757, n5758, n5759, n5760, n5761, n5762, n5763,
n5764, n5765, n5766, n5767, n5768, n5769, n5770, n5771, n5772, n5773,
n5774, n5775, n5776, n5777, n5779, n5780, n5781, n5782, n5783, n5784,
n5785, n5786, n5787, n5788, n5789, n5790, n5791, n5792, n5793, n5794,
n5795, n5796, n5797, n5798, n5799, n5800, n5801, n5802, n5803, n5804,
n5805, n5806, n5807, n5808, n5809, n5810, n5811, n5812, n5813, n5814,
n5815, n5816, n5817, n5818, n5819, n5820, n5821, n5822, n5823, n5824,
n5825, n5826, n5827, n5828, n5829, n5830, n5831, n5832, n5833, n5834,
n5835, n5836, n5837, n5838, n5839, n5840, n5841, n5842, n5843, n5844,
n5845, n5846, n5847, n5848, n5849, n5850, n5851, n5852, n5853, n5854,
n5855, n5856, n5857, n5858, n5859, n5860, n5861, n5862, n5863, n5864,
n5865, n5866, n5867, n5868, n5869, n5870, n5871, n5872, n5873, n5874,
n5875, n5876, n5877, n5878, n5879, n5880, n5881, n5882, n5883, n5884,
n5885, n5886, n5887, n5888, n5889, n5890, n5891, n5892, n5893, n5894,
n5895, n5896, n5897, n5898, n5899, n5900, n5901, n5902, n5903, n5904,
n5905, n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5913, n5914,
n5915, n5916, n5917, n5918, n5919, n5920, n5921, n5922, n5923, n5924,
n5925, n5926, n5927, n5928, n5929, n5930, n5931, n5932, n5933, n5934,
n5935, n5936, n5937, n5938, n5939, n5940, n5941, n5942, n5943, n5944,
n5945, n5946, n5947, n5948, n5949, n5950, n5951, n5952, n5953, n5954,
n5955, n5956, n5957, n5958, n5959, n5960, n5961, n5962, n5963, n5964,
n5965, n5966, n5967, n5968, n5969, n5970, n5971, n5972, n5973, n5974,
n5975, n5976, n5977, n5978, n5979, n5980, n5981, n5982, n5983, n5984,
n5985, n5986, n5987, n5988, n5989, n5990, n5991, n5992, n5993, n5994,
n5995, n5996, n5997, n5998, n5999, n6000, n6001, n6002, n6003, n6004,
n6005, n6006, n6007, n6008, n6009, n6010, n6011, n6012, n6013, n6014,
n6015, n6016, n6017, n6018, n6019, n6020, n6021, n6022, n6023, n6024,
n6025, n6026, n6027, n6028, n6029, n6030, n6031, n6032, n6033, n6034,
n6035, n6036, n6037, n6038, n6039, n6040, n6041, n6042, n6043, n6044,
n6045, n6046, n6047, n6048, n6049, n6050, n6051, n6052, n6053, n6054,
n6055, n6056, n6058, n6059, n6060, n6061, n6062, n6063, n6064, n6065,
n6066, n6067, n6068, n6069, n6070, n6071, n6072, n6073, n6074, n6075,
n6076, n6077, n6078, n6079, n6080, n6081, n6082, n6083, n6084, n6085,
n6086, n6087, n6088, n6089, n6090, n6091, n6092, n6093, n6094, n6095,
n6096, n6097, n6098, n6099, n6100, n6101, n6102, n6103, n6104, n6105,
n6106, n6107, n6108, n6109, n6110, n6111, n6112, n6113, n6114, n6115,
n6116, n6117, n6118, n6119, n6120, n6121, n6122, n6123, n6124, n6125,
n6126, n6127, n6128, n6129, n6130, n6131, n6132, n6133, n6134, n6135,
n6136, n6137, n6138, n6139, n6140, n6141, n6142, n6143, n6145, n6146,
n6147, n6148, n6149, n6150, n6151, n6152, n6153, n6154, n6155, n6156,
n6157, n6158, n6159, n6160, n6161, n6162, n6163, n6164, n6165, n6166,
n6167, n6168, n6169, n6170, n6171, n6172, n6173, n6174, n6175, n6176,
n6177, n6178, n6179, n6180, n6181, n6182, n6183, n6184, n6185, n6186,
n6187, n6188, n6189, n6190, n6191, n6192, n6193, n6194, n6195, n6196,
n6197, n6198, n6199, n6200, n6201, n6202, n6203, n6204, n6205, n6206,
n6207, n6208, n6209, n6210, n6211, n6212, n6213, n6214, n6215, n6216,
n6217, n6218, n6219, n6220, n6221, n6222, n6223, n6224, n6225, n6226,
n6227, n6228, n6229, n6230, n6231, n6232, n6233, n6234, n6235, n6236,
n6237, n6238, n6239, n6240, n6241, n6242, n6243, n6244, n6245, n6246,
n6247, n6248, n6249, n6250, n6251, n6252, n6253, n6254, n6255, n6256,
n6257, n6258, n6259, n6260, n6261, n6262, n6263, n6264, n6265, n6266,
n6267, n6268, n6269, n6270, n6271, n6272, n6273, n6274, n6275, n6276,
n6277, n6278, n6279, n6280, n6281, n6282, n6283, n6284, n6285, n6286,
n6287, n6288, n6289, n6290, n6291, n6292, n6293, n6294, n6295, n6296,
n6297, n6298, n6299, n6300, n6301, n6302, n6303, n6304, n6305, n6307,
n6309, n6310, n6311, n6312, n6313, n6314, n6315, n6316, n6317, n6318,
n6319, n6320, n6321, n6322, n6323, n6324, n6325, n6326, n6327, n6328,
n6329, n6330, n6331, n6332, n6333, n6334, n6335, n6336, n6337, n6338,
n6339, n6340, n6341, n6342, n6343, n6344, n6345, n6346, n6347, n6348,
n6349, n6350, n6351, n6352, n6353, n6354, n6355, n6356, n6357, n6358,
n6359, n6360, n6361, n6362, n6363, n6364, n6365, n6366, n6367, n6368,
n6369, n6370, n6371, n6372, n6373, n6374, n6375, n6376, n6377, n6378,
n6379, n6380, n6381, n6382, n6383, n6384, n6385, n6386, n6387, n6388,
n6389, n6390, n6391, n6392, n6393, n6394, n6395, n6396, n6397, n6398,
n6399, n6400, n6401, n6402, n6403, n6404, n6405, n6406, n6407, n6408,
n6409, n6410, n6411, n6412, n6413, n6414, n6415, n6416, n6417, n6418,
n6419, n6420, n6421, n6422, n6423, n6424, n6425, n6426, n6427, n6428,
n6429, n6430, n6431, n6432, n6433, n6434, n6435, n6436, n6437, n6438,
n6439, n6440, n6441, n6442, n6443, n6444, n6445, n6446, n6447, n6448,
n6449, n6450, n6451, n6452, n6453, n6454, n6455, n6456, n6457, n6458,
n6459, n6460, n6461, n6462, n6463, n6464, n6465, n6466, n6467, n6468,
n6469, n6470, n6471, n6472, n6473, n6474, n6475, n6476, n6477, n6478,
n6479, n6480, n6481, n6482, n6483, n6484, n6485, n6486, n6487, n6488,
n6489, n6490, n6491, n6492, n6493, n6494, n6495, n6496, n6497, n6498,
n6499, n6500, n6501, n6502, n6503, n6504, n6505, n6506, n6507, n6508,
n6509, n6510, n6511, n6512, n6513, n6514, n6515, n6516, n6517, n6518,
n6519, n6520, n6521, n6522, n6523, n6524, n6525, n6526, n6527, n6528,
n6529, n6530, n6531, n6532, n6533, n6534, n6535, n6536, n6537, n6538,
n6539, n6540, n6541, n6542, n6543, n6544, n6545, n6546, n6547, n6548,
n6549, n6550, n6551, n6552, n6553, n6554, n6555, n6556, n6557, n6558,
n6559, n6560, n6561, n6562, n6563, n6564, n6565, n6566, n6567, n6568,
n6569, n6570, n6571, n6572, n6573, n6574, n6575, n6576, n6577, n6578,
n6579, n6580, n6581, n6582, n6583, n6584, n6585, n6586, n6587, n6588,
n6589, n6590, n6591, n6592, n6593, n6594, n6595, n6596, n6597, n6598,
n6599, n6600, n6601, n6602, n6603, n6604, n6605, n6606, n6607, n6608,
n6609, n6610, n6611, n6612, n6613, n6614, n6615, n6616, n6617, n6618,
n6619, n6620, n6621, n6622, n6623, n6624, n6625, n6626, n6627, n6628,
n6629, n6630, n6631, n6632, n6633, n6634, n6635, n6636, n6637, n6638,
n6639, n6640, n6641, n6642, n6643, n6644, n6645, n6646, n6647, n6648,
n6649, n6650, n6651, n6652, n6653, n6654, n6655, n6656, n6657, n6658,
n6659, n6660, n6661, n6662, n6663, n6664, n6665, n6666, n6667, n6668,
n6669, n6670, n6671, n6672, n6673, n6674, n6675, n6676, n6677, n6678,
n6679, n6680, n6681, n6682, n6683, n6684, n6685, n6686, n6687, n6688,
n6689, n6690, n6691, n6692, n6693, n6694, n6695, n6696, n6697, n6698,
n6699, n6700, n6701, n6702, n6703, n6704, n6705, n6706, n6707, n6708,
n6709, n6710, n6711, n6712, n6713, n6714, n6715, n6716, n6717, n6718,
n6719, n6720, n6721, n6722, n6723, n6724, n6725, n6726, n6727, n6728,
n6729, n6730, n6731, n6732, n6733, n6734, n6735, n6736, n6737, n6738,
n6739, n6740, n6741, n6742, n6743, n6744, n6745, n6746, n6747, n6748,
n6749, n6750, n6751, n6752, n6753, n6754, n6755, n6756, n6757, n6758,
n6759, n6760, n6761, n6762, n6763, n6764, n6765, n6766, n6767, n6768,
n6769, n6770, n6771, n6772, n6773, n6774, n6775, n6776, n6777, n6778,
n6779, n6780, n6781, n6782, n6783, n6784, n6785, n6786, n6787, n6788,
n6789, n6790, n6791, n6792, n6793, n6794, n6795, n6796, n6797, n6798,
n6799, n6800, n6801, n6802, n6803, n6804, n6805, n6806, n6807, n6808,
n6809, n6810, n6811, n6812, n6813, n6814, n6815, n6816, n6817, n6818,
n6819, n6820, n6821, n6822, n6823, n6824, n6825, n6826, n6827, n6828,
n6829, n6830, n6831, n6832, n6833, n6834, n6835, n6836, n6837, n6838,
n6839, n6840, n6841, n6842, n6843, n6844, n6845, n6846, n6847, n6848,
n6849, n6850, n6851, n6852, n6853, n6854, n6855, n6856, n6857, n6858,
n6859, n6860, n6861, n6862, n6863, n6864, n6865, n6866, n6867, n6868,
n6869, n6870, n6871, n6872, n6873, n6874, n6875, n6876, n6877, n6878,
n6879, n6880, n6881, n6882, n6883, n6884, n6885, n6886, n6887, n6888,
n6889, n6890, n6891, n6892, n6893, n6894, n6895, n6896, n6897, n6898,
n6899, n6900, n6901, n6902, n6903, n6904, n6905, n6906, n6907, n6908,
n6909, n6910, n6911, n6912, n6913, n6914, n6915, n6916, n6917, n6918,
n6919, n6920, n6921, n6922, n6923, n6924, n6925, n6926, n6927, n6928,
n6929, n6930, n6931, n6932, n6933, n6934, n6935, n6936, n6937, n6938,
n6939, n6940, n6941, n6942, n6943, n6944, n6945, n6946, n6947, n6948,
n6949, n6950, n6951, n6952, n6953, n6954, n6955, n6956, n6957, n6958,
n6959, n6960, n6961, n6962, n6963, n6964, n6965, n6966, n6967, n6968,
n6969, n6970, n6971, n6972, n6973, n6974, n6975, n6976, n6977, n6978,
n6979, n6980, n6981, n6982, n6983, n6984, n6985, n6986, n6987, n6988,
n6989, n6990, n6991, n6992, n6993, n6994, n6995, n6996, n6997, n6998,
n6999, n7000, n7001, n7002, n7003, n7004, n7005, n7006, n7007, n7008,
n7009, n7010, n7011, n7012, n7013, n7014, n7015, n7016, n7017, n7018,
n7019, n7020, n7021, n7022, n7023, n7024, n7025, n7026, n7027, n7028,
n7029, n7030, n7031, n7032, n7033, n7034, n7035, n7036, n7037, n7038,
n7039, n7040, n7041, n7042, n7043, n7044, n7045, n7046, n7047, n7048,
n7049, n7050, n7051, n7052, n7053, n7054, n7055, n7056, n7057, n7058,
n7059, n7060, n7061, n7062, n7063, n7064, n7065, n7066, n7067, n7068,
n7069, n7070, n7071, n7072, n7073, n7074, n7075, n7076, n7077, n7078,
n7079, n7080, n7081, n7082, n7083, n7084, n7085, n7086, n7087, n7088,
n7089, n7090, n7091, n7092, n7093, n7094, n7095, n7096, n7097, n7098,
n7099, n7100, n7101, n7102, n7103, n7104, n7105, n7106, n7107, n7108,
n7109, n7110, n7111, n7112, n7113, n7114, n7115, n7116, n7117, n7118,
n7119, n7120, n7121, n7122, n7123, n7124, n7125, n7126, n7127, n7128,
n7129, n7130, n7131, n7132, n7133, n7134, n7135, n7136, n7137, n7138,
n7139, n7140, n7141, n7142, n7143, n7144, n7145, n7146, n7147, n7148,
n7149, n7150, n7151, n7152, n7153, n7154, n7155, n7156, n7157, n7158,
n7159, n7160, n7161, n7162, n7163, n7164, n7165, n7166, n7167, n7168,
n7169, n7170, n7171, n7172, n7173, n7174, n7175, n7176, n7177, n7178,
n7179, n7180, n7181, n7182, n7183, n7184, n7185, n7186, n7187, n7188,
n7189, n7190, n7191, n7192, n7193, n7194, n7195, n7196, n7197, n7198,
n7199, n7200, n7201, n7202, n7203, n7204, n7205, n7206, n7207, n7208,
n7209, n7210, n7211, n7212, n7213, n7214, n7215, n7216, n7217, n7218,
n7219, n7220, n7221, n7222, n7223, n7224, n7225, n7226, n7227, n7228,
n7229, n7230, n7231, n7232, n7233, n7234, n7235, n7236, n7237, n7238,
n7239, n7240, n7241, n7242, n7243, n7244, n7245, n7246, n7247, n7248,
n7249, n7250, n7251, n7252, n7253, n7254, n7255, n7256, n7257, n7258,
n7259, n7260, n7261, n7262, n7263, n7264, n7265, n7266, n7267, n7268,
n7269, n7270, n7271, n7272, n7273, n7274, n7275, n7276, n7277, n7278,
n7279, n7280, n7281, n7282, n7283, n7284, n7285, n7286, n7287, n7288,
n7289, n7290, n7291, n7292, n7293, n7294, n7295, n7296, n7297, n7298,
n7299, n7300, n7301, n7302, n7303, n7304, n7305, n7306, n7307, n7308,
n7309, n7310, n7311, n7312, n7313, n7314, n7315, n7316, n7317, n7318,
n7319, n7320, n7321, n7322, n7323, n7324, n7325, n7326, n7327, n7328,
n7329, n7330, n7331, n7332, n7333, n7334, n7335, n7336, n7337, n7338,
n7339, n7340, n7341, n7342, n7343, n7344, n7345, n7346, n7347, n7348,
n7349, n7350, n7351, n7352, n7353, n7354, n7355, n7356, n7357, n7358,
n7359, n7360, n7361, n7362, n7363, n7364, n7365, n7366, n7367, n7368,
n7369, n7370, n7371, n7372, n7373, n7374, n7375, n7376, n7377, n7378,
n7379, n7380, n7381, n7382, n7383, n7384, n7385, n7386, n7387, n7388,
n7389, n7390, n7391, n7392, n7393, n7394, n7395, n7396, n7397, n7398,
n7399, n7400, n7401, n7402, n7403, n7404, n7405, n7406, n7407, n7408,
n7409, n7410, n7411, n7412, n7413, n7414, n7415, n7416, n7417, n7418,
n7419, n7420, n7421, n7422, n7423, n7424, n7425, n7426, n7427, n7428,
n7429, n7430, n7431, n7432, n7433, n7434, n7435, n7436, n7437, n7438,
n7439, n7440, n7441, n7442, n7443, n7444, n7445, n7446, n7447, n7448,
n7449, n7450, n7451, n7452, n7453, n7454, n7455, n7456, n7457, n7458,
n7459, n7460, n7461, n7462, n7463, n7464, n7465, n7466, n7467, n7468,
n7469, n7470, n7471, n7472, n7473, n7474, n7475, n7476, n7477, n7478,
n7479, n7480, n7481, n7482, n7483, n7484, n7485, n7486, n7487, n7488,
n7489, n7490, n7491, n7492, n7493, n7494, n7495, n7496, n7497, n7498,
n7499, n7500, n7501, n7502, n7503, n7504, n7505, n7506, n7507, n7508,
n7509, n7510, n7511, n7512, n7513, n7514, n7515, n7516, n7517, n7518,
n7519, n7520, n7521, n7522, n7523, n7524, n7525, n7526, n7527, n7528,
n7529, n7530, n7531, n7532, n7533, n7534, n7535, n7536, n7537, n7538,
n7539, n7540, n7541, n7542, n7543, n7544, n7545, n7546, n7547, n7548,
n7549, n7550, n7551, n7552, n7553, n7554, n7555, n7556, n7557, n7558,
n7559, n7560, n7561, n7562, n7563, n7564, n7565, n7566, n7567, n7568,
n7569, n7570, n7571, n7572, n7573, n7574, n7575, n7576, n7577, n7578,
n7579, n7580, n7581, n7582, n7583, n7584, n7585, n7586, n7587, n7588,
n7589, n7590, n7591, n7592, n7593, n7594, n7595, n7596, n7597, n7598,
n7599, n7600, n7601, n7602, n7603, n7604, n7605, n7606, n7607, n7608,
n7609, n7610, n7611, n7612, n7613, n7614, n7615, n7616, n7617, n7618,
n7619, n7620, n7621, n7622, n7623, n7624, n7625, n7626, n7627, n7628,
n7629, n7630, n7631, n7632, n7633, n7634, n7635, n7636, n7637, n7638,
n7639, n7640, n7641, n7642, n7643, n7644, n7645, n7646, n7647, n7648,
n7649, n7650, n7651, n7652, n7653, n7654, n7655, n7656, n7657, n7658,
n7659, n7660, n7661, n7662, n7663, n7664, n7665, n7666, n7667, n7668,
n7669, n7670, n7671, n7672, n7673, n7674, n7675, n7676, n7677, n7678,
n7679, n7680, n7681, n7682, n7683, n7684, n7685, n7686, n7687, n7688,
n7689, n7690, n7691, n7692, n7693, n7694, n7695, n7696, n7697, n7698,
n7699, n7700, n7701, n7702, n7703, n7704, n7705, n7706, n7707, n7708,
n7709, n7710, n7711, n7712, n7713, n7714, n7715, n7716, n7717, n7718,
n7719, n7720, n7721, n7722, n7723, n7724, n7725, n7726, n7727, n7728,
n7729, n7730, n7731, n7732, n7733, n7734, n7735, n7736, n7737, n7738,
n7739, n7740, n7741, n7742, n7743, n7744, n7745, n7746, n7747, n7748,
n7749, n7750, n7751, n7752, n7753, n7754, n7755, n7756, n7757, n7758,
n7759, n7760, n7761, n7762, n7763, n7764, n7765, n7766, n7767, n7768,
n7769, n7770, n7771, n7772, n7773, n7774, n7775, n7776, n7777, n7778,
n7779, n7780, n7781, n7782, n7783, n7784, n7785, n7786, n7787, n7788,
n7789, n7790, n7791, n7792, n7793, n7794, n7795, n7796, n7797, n7798,
n7799, n7800, n7801, n7802, n7803, n7804, n7805, n7806, n7807, n7808,
n7809, n7810, n7811, n7812, n7813, n7814, n7815, n7816, n7817, n7818,
n7819, n7820, n7821, n7822, n7823, n7824, n7825, n7826, n7827, n7828,
n7829, n7830, n7831, n7832, n7833, n7834, n7835, n7836, n7837, n7838,
n7839, n7840, n7841, n7842, n7843, n7844, n7845, n7846, n7847, n7848,
n7849, n7850, n7851, n7852, n7853, n7854, n7855, n7856, n7857, n7858,
n7859, n7860, n7861, n7862, n7863, n7864, n7865, n7866, n7867, n7868,
n7869, n7870, n7871, n7872, n7873, n7874, n7875, n7876, n7877, n7878,
n7879, n7880, n7881, n7882, n7883, n7884, n7885, n7886, n7887, n7888,
n7889, n7890, n7891, n7892, n7893, n7894, n7895, n7896, n7897, n7898,
n7899, n7900, n7901, n7902, n7903, n7904, n7905, n7906, n7907, n7908,
n7909, n7910, n7911, n7912, n7913, n7914, n7915, n7916, n7917, n7918,
n7919, n7920, n7921, n7922, n7923, n7924, n7925, n7926, n7927, n7928,
n7929, n7930, n7931, n7932, n7933, n7934, n7935, n7936, n7937, n7938,
n7939, n7940, n7941, n7942, n7943, n7944, n7945, n7946, n7947, n7948,
n7949, n7950, n7951, n7952, n7953, n7954, n7955, n7956, n7957, n7958,
n7959, n7960, n7961, n7962, n7963, n7964, n7965, n7966, n7967, n7968,
n7969, n7970, n7971, n7972, n7973, n7974, n7975, n7976, n7977, n7978,
n7979, n7980, n7981, n7982, n7983, n7984, n7985, n7986, n7987, n7988,
n7989, n7990, n7991, n7992, n7993, n7994, n7995, n7996, n7997, n7998,
n7999, n8000, n8001, n8002, n8003, n8004, n8005, n8006, n8007, n8008,
n8009, n8010, n8011, n8012, n8013, n8014, n8015, n8016, n8017, n8018,
n8019, n8020, n8021, n8022, n8023, n8024, n8025, n8026, n8027, n8028,
n8029, n8030, n8031, n8032, n8033, n8034, n8035, n8036, n8037, n8038,
n8039, n8040, n8041, n8042, n8043, n8044, n8045, n8046, n8047, n8048,
n8049, n8050, n8051, n8052, n8053, n8054, n8055, n8056, n8057, n8058,
n8059, n8060, n8061, n8062, n8063, n8064, n8065, n8066, n8067, n8068,
n8069, n8070, n8071, n8072, n8073, n8074, n8075, n8076, n8077, n8078,
n8079, n8080, n8081, n8082, n8083, n8084, n8085, n8086, n8087, n8088,
n8089, n8090, n8091, n8092, n8093, n8094, n8095, n8096, n8097, n8098,
n8099, n8100, n8101, n8102, n8103, n8104, n8105, n8106, n8107, n8108,
n8109, n8110, n8111, n8112, n8113, n8114, n8115, n8116, n8117, n8118,
n8119, n8120, n8121, n8122, n8123, n8124, n8125, n8126, n8127, n8128,
n8129, n8130, n8131, n8132, n8133, n8134, n8135, n8136, n8137, n8138,
n8139, n8140, n8141, n8142, n8143, n8144, n8145, n8146, n8147, n8148,
n8149, n8150, n8151, n8152, n8153, n8154, n8155, n8156, n8157, n8158,
n8159, n8160, n8161, n8162, n8163, n8164, n8165, n8166, n8167, n8168,
n8169, n8170, n8171, n8172, n8173, n8174, n8175, n8176, n8177, n8178,
n8179, n8180, n8181, n8182, n8183, n8184, n8185, n8186, n8187, n8188,
n8189, n8190, n8191, n8192, n8193, n8194, n8195, n8196, n8197, n8198,
n8199, n8200, n8201, n8202, n8203, n8204, n8205, n8206, n8207, n8208,
n8209, n8210, n8211, n8212, n8213, n8214, n8215, n8216, n8217, n8218,
n8219, n8220, n8221, n8222, n8223, n8224, n8225, n8226, n8227, n8228,
n8229, n8230, n8231, n8232, n8233, n8234, n8235, n8236, n8237, n8238,
n8239, n8240, n8241, n8242, n8243, n8244, n8245, n8246, n8247, n8248,
n8249, n8250, n8251, n8252, n8253, n8254, n8255, n8256, n8257, n8258,
n8259, n8260, n8261, n8262, n8263, n8264, n8265, n8266, n8267, n8268,
n8269, n8270, n8271, n8272, n8273, n8274, n8275, n8276, n8277, n8278,
n8279, n8280, n8281, n8282, n8283, n8284, n8285, n8286, n8287, n8288,
n8289, n8290, n8291, n8292, n8293, n8294, n8295, n8296, n8297, n8298,
n8299, n8300, n8301, n8302, n8303, n8304, n8305, n8306, n8307, n8308,
n8309, n8310, n8311, n8312, n8313, n8314, n8315, n8316, n8317, n8318,
n8319, n8320, n8321, n8322, n8323, n8324, n8325, n8326, n8327, n8328,
n8329, n8330, n8331, n8332, n8333, n8334, n8335, n8336, n8337, n8338,
n8339, n8340, n8341, n8342, n8343, n8344, n8345, n8346, n8347, n8348,
n8349, n8350, n8351, n8352, n8353, n8354, n8355, n8356, n8357, n8358,
n8359, n8360, n8361, n8362, n8363, n8364, n8365, n8366, n8367, n8368,
n8369, n8370, n8371, n8372, n8373, n8374, n8375, n8376, n8377, n8378,
n8379, n8380, n8381, n8382, n8383, n8384, n8385, n8386, n8387, n8388,
n8389, n8390, n8391, n8392, n8393, n8394, n8395, n8396, n8397, n8398,
n8399, n8400, n8401, n8402, n8403, n8404, n8405, n8406, n8407, n8408,
n8409, n8410, n8411, n8412, n8413, n8414, n8415, n8416, n8417, n8418,
n8419, n8420, n8421, n8422, n8423, n8424, n8425, n8426, n8427, n8428,
n8429, n8430, n8431, n8432, n8433, n8434, n8435, n8436, n8437, n8438,
n8439, n8440, n8441, n8442, n8443, n8444, n8445, n8446, n8447, n8448,
n8449, n8450, n8451, n8452, n8453, n8454, n8455, n8456, n8457, n8458,
n8459, n8460, n8461, n8462, n8463, n8464, n8466, n8467, n8468, n8469,
n8470, n8471, n8472, n8473, n8474, n8475, n8476, n8477, n8478, n8479,
n8480, n8481, n8482, n8483, n8484, n8485, n8486, n8487, n8488, n8489,
n8490, n8491, n8492, n8493, n8494, n8495, n8496, n8497, n8498, n8499,
n8500, n8501, n8502, n8503, n8504, n8505, n8506, n8507, n8508, n8509,
n8510, n8511, n8512, n8513, n8514, n8515, n8516, n8517, n8518, n8519,
n8520, n8521, n8522, n8523, n8524, n8525, n8526, n8527, n8528, n8529,
n8530, n8531, n8532, n8533, n8534, n8535, n8536, n8537, n8538, n8539,
n8540, n8541, n8542, n8543, n8544, n8545, n8546, n8547, n8548, n8549,
n8550, n8551, n8552, n8553, n8554, n8555, n8556, n8557, n8558, n8559,
n8560, n8561, n8562, n8563, n8564, n8565, n8566, n8567, n8568, n8569,
n8570, n8571, n8572, n8573, n8574, n8575, n8576, n8577, n8578, n8579,
n8580, n8581, n8582, n8583, n8584, n8585, n8586, n8587, n8588, n8589,
n8590, n8591, n8592, n8593, n8594, n8595, n8596, n8597, n8598, n8599,
n8600, n8601, n8602, n8603, n8604, n8605, n8606, n8607, n8608, n8609,
n8610, n8611, n8612, n8613, n8614, n8615, n8616, n8617, n8618, n8619,
n8620, n8621, n8622, n8623, n8624, n8625, n8626, n8627, n8628, n8629,
n8630, n8631, n8632, n8633, n8634, n8635, n8636, n8637, n8638, n8639,
n8640, n8641, n8642, n8643, n8644, n8645, n8646, n8647, n8648, n8649,
n8650, n8651, n8652, n8653, n8654, n8655, n8656, n8657, n8658, n8659,
n8660, n8661, n8662, n8663, n8664, n8665, n8666, n8667, n8668, n8669,
n8670, n8671, n8672, n8673, n8674, n8675, n8676, n8677, n8678, n8679,
n8680, n8681, n8682, n8683, n8684, n8685, n8686, n8687, n8688, n8689,
n8690, n8691, n8692, n8693, n8694, n8695, n8696, n8697, n8698, n8699,
n8700, n8701, n8702, n8703, n8704, n8705, n8706, n8707, n8708, n8709,
n8710, n8711, n8712, n8713, n8714, n8715, n8716, n8717, n8718, n8719,
n8720, n8721, n8722, n8723, n8724, n8725, n8726, n8727, n8728, n8729,
n8730, n8731, n8732, n8733, n8734, n8735, n8736, n8737, n8738, n8739,
n8740, n8741, n8742, n8743, n8744, n8745, n8746, n8747, n8748, n8749,
n8750, n8751, n8752, n8753, n8754, n8755, n8756, n8757, n8758, n8759,
n8760, n8761, n8762, n8763, n8764, n8765, n8766, n8767, n8768, n8769,
n8770, n8771, n8772, n8773, n8774, n8775, n8776, n8777, n8778, n8779,
n8780, n8781, n8782, n8783, n8784, n8785, n8786, n8787, n8788, n8789,
n8790, n8791, n8792, n8793, n8794, n8795, n8796, n8797, n8798, n8799,
n8800, n8801, n8802, n8803, n8804, n8805, n8806, n8807, n8808, n8809,
n8810, n8811, n8812, n8813, n8814, n8815, n8816, n8817, n8818, n8819,
n8820, n8821, n8822, n8823, n8824, n8825, n8826, n8827, n8828, n8829,
n8830, n8831, n8832, n8833, n8834, n8835, n8836, n8837, n8838, n8839,
n8840, n8841, n8842, n8843, n8844, n8845, n8846, n8847, n8848, n8849,
n8850, n8851, n8852, n8853, n8854, n8855, n8856, n8857, n8858, n8859,
n8860, n8861, n8862, n8863, n8864, n8865, n8866, n8867, n8868, n8869,
n8870, n8871, n8872, n8873, n8874, n8875, n8876, n8877, n8878, n8879,
n8880, n8881, n8882, n8883, n8884, n8885, n8886, n8887, n8888, n8889,
n8890, n8891, n8892, n8893, n8894, n8895, n8896, n8897, n8898, n8899,
n8900, n8901, n8902, n8903, n8904, n8905, n8906, n8907, n8908, n8909,
n8910, n8911, n8912, n8913, n8914, n8915, n8916, n8917, n8918, n8919,
n8920, n8921, n8922, n8923, n8924, n8925, n8926, n8927, n8928, n8929,
n8930, n8931, n8932, n8933, n8934, n8935, n8936, n8937, n8938, n8939,
n8940, n8941, n8942, n8943, n8944, n8945, n8946, n8947, n8948, n8949,
n8950, n8951, n8952, n8953, n8954, n8955, n8956, n8957, n8958, n8959,
n8960, n8961, n8962, n8963, n8964, n8965, n8966, n8967, n8968, n8969,
n8970, n8971, n8972, n8973, n8974, n8975, n8976, n8977, n8978, n8979,
n8980, n8981, n8982, n8983, n8984, n8985, n8986, n8987, n8988, n8989,
n8990, n8991, n8992, n8993, n8994, n8995, n8996, n8997, n8998, n8999,
n9000, n9001, n9002, n9003, n9004, n9005, n9006, n9007, n9008, n9009,
n9010, n9011, n9012, n9013, n9014, n9015, n9016, n9017, n9018, n9019,
n9020, n9021, n9022, n9023, n9024, n9025, n9026, n9027, n9028, n9029,
n9030, n9031, n9032, n9033, n9034, n9035, n9036, n9037, n9038, n9039,
n9040, n9041, n9042, n9043, n9044, n9045, n9046, n9047, n9048, n9049,
n9050, n9051, n9052, n9053, n9054, n9055, n9056, n9057, n9058, n9059,
n9060, n9061, n9062, n9063, n9064, n9065, n9066, n9067, n9068, n9069,
n9070, n9071, n9072, n9073, n9074, n9075, n9076, n9077, n9078, n9079,
n9080, n9081, n9082, n9083, n9084, n9085, n9086, n9087, n9088, n9089,
n9090, n9091, n9092, n9093, n9094, n9095, n9096, n9097, n9098, n9099,
n9100, n9101, n9102, n9103, n9104, n9105, n9106, n9107, n9108, n9109,
n9110, n9111, n9112, n9113, n9114, n9115, n9116, n9117, n9118, n9119,
n9120, n9121, n9122, n9123, n9124, n9125, n9126, n9127, n9128, n9129,
n9130, n9131, n9132, n9133, n9134, n9135, n9136, n9137, n9138, n9139,
n9140, n9141, n9142, n9143, n9144, n9145, n9146, n9147, n9148, n9149,
n9150, n9151, n9152, n9153, n9154, n9155, n9156, n9157, n9158, n9159,
n9160, n9161, n9162, n9163, n9164, n9165, n9166, n9167, n9168, n9169,
n9170, n9171, n9172, n9173, n9174, n9175, n9176, n9177, n9178, n9179,
n9180, n9181, n9182, n9183, n9184, n9185, n9186, n9187, n9188, n9189,
n9190, n9191, n9192, n9193, n9194, n9195, n9196, n9197, n9198, n9199,
n9200, n9201, n9202, n9203, n9204, n9205, n9206, n9207, n9208, n9209,
n9210, n9211, n9212, n9213, n9214, n9215, n9216, n9217, n9218, n9219,
n9220, n9221, n9222, n9223, n9224, n9225, n9226, n9227, n9228, n9229,
n9230, n9231, n9232, n9233, n9234, n9235, n9236, n9237, n9238, n9239,
n9240, n9241, n9242, n9243, n9244, n9245, n9246, n9247, n9248, n9249,
n9250, n9251, n9252, n9253, n9254, n9255, n9256, n9257, n9258, n9259,
n9260, n9261, n9262, n9263, n9264, n9265, n9266, n9267, n9268, n9269,
n9270, n9271, n9272, n9273, n9274, n9275, n9276, n9277, n9278, n9279,
n9280, n9281, n9282, n9283, n9284, n9285, n9286, n9287, n9288, n9289,
n9290, n9291, n9292, n9293, n9294, n9295, n9296, n9297, n9298, n9299,
n9300, n9301, n9302, n9303, n9304, n9305, n9306, n9307, n9308, n9309,
n9310, n9311, n9312, n9313, n9314, n9315, n9316, n9317, n9318, n9319,
n9320, n9321, n9322, n9323, n9324, n9325, n9326, n9327, n9328, n9329,
n9330, n9331, n9332, n9333, n9334, n9335, n9336, n9337, n9338, n9339,
n9340, n9341, n9342, n9343, n9344, n9345, n9346, n9347, n9348, n9349,
n9350, n9351, n9352, n9353, n9354, n9355, n9356, n9357, n9358, n9359,
n9360, n9361, n9362, n9363, n9364, n9365, n9366, n9367, n9368, n9369,
n9370, n9371, n9372, n9373, n9374, n9375, n9376, n9377, n9378, n9379,
n9380, n9381, n9382, n9383, n9384, n9385, n9386, n9387, n9388, n9389,
n9390, n9391, n9392, n9393, n9394, n9395, n9396, n9397, n9398, n9399,
n9400, n9401, n9402, n9403, n9404, n9405, n9406, n9407, n9408, n9409,
n9410, n9411, n9412, n9413, n9414, n9415, n9416, n9417, n9418, n9419,
n9420, n9421, n9422, n9423, n9424, n9425, n9426, n9427, n9428, n9429,
n9430, n9431, n9432, n9433, n9434, n9435, n9436, n9437, n9438, n9439,
n9440, n9441, n9442, n9443, n9444, n9445, n9446, n9447, n9448, n9449,
n9450, n9451, n9452, n9453, n9454, n9455, n9456, n9457, n9458, n9459,
n9460, n9461, n9462, n9463, n9464, n9465, n9466, n9467, n9468, n9469,
n9470, n9471, n9472, n9473, n9474, n9475, n9476, n9477, n9478, n9479,
n9480, n9481, n9482, n9483, n9484, n9485, n9486, n9487, n9488, n9489,
n9490, n9491, n9492, n9493, n9494, n9495, n9496, n9497, n9498, n9499,
n9500, n9501, n9502, n9503, n9504, n9505, n9506, n9507, n9508, n9509,
n9510, n9511, n9512, n9513, n9514, n9515, n9516, n9517, n9518, n9519,
n9520, n9521, n9522, n9523, n9524, n9525, n9526, n9527, n9528, n9529,
n9530, n9531, n9532, n9533, n9534, n9535, n9536, n9537, n9538, n9539,
n9540, n9541, n9542, n9543, n9544, n9545, n9546, n9547, n9548, n9549,
n9550, n9551, n9552, n9553, n9554, n9555, n9556, n9557, n9558, n9559,
n9560, n9561, n9562, n9563, n9564, n9565, n9566, n9567, n9568, n9569,
n9570, n9571, n9572, n9573, n9574, n9575, n9576, n9577, n9578, n9579,
n9580, n9581, n9582, n9583, n9584, n9585, n9586, n9587, n9588, n9589,
n9590, n9591, n9592, n9593, n9594, n9595, n9596, n9597, n9598, n9599,
n9600, n9601, n9602, n9603, n9604, n9605, n9606, n9607, n9608, n9609,
n9610, n9611, n9612, n9613, n9614, n9615, n9616, n9617, n9618, n9619,
n9620, n9621, n9622, n9623, n9624, n9625, n9626, n9627, n9628, n9629,
n9630, n9631, n9632, n9633, n9634, n9635, n9636, n9637, n9638, n9639,
n9640, n9641, n9642, n9643, n9644, n9645, n9646, n9647, n9648, n9649,
n9650, n9651, n9652, n9653, n9654, n9655, n9656, n9657, n9658, n9659,
n9660, n9661, n9662, n9663, n9664, n9665, n9666, n9667, n9668, n9669,
n9670, n9671, n9672, n9673, n9674, n9675, n9676, n9677, n9678, n9679,
n9680, n9681, n9682, n9683, n9684, n9685, n9686, n9687, n9688, n9689,
n9690, n9691, n9692, n9693, n9694, n9695, n9696, n9697, n9698, n9699,
n9700, n9701, n9702, n9703, n9704, n9705, n9706, n9707, n9708, n9709,
n9710, n9711, n9712, n9713, n9714, n9715, n9716, n9717, n9718, n9719,
n9720, n9721, n9722, n9723, n9724, n9725, n9726, n9727, n9728, n9729,
n9730, n9731, n9732, n9733, n9734, n9735, n9736, n9737, n9738, n9739,
n9740, n9741, n9742, n9743, n9744, n9745, n9746, n9747, n9748, n9749,
n9750, n9751, n9752, n9753, n9754, n9755, n9756, n9757, n9758, n9759,
n9760, n9761, n9762, n9763, n9764, n9765, n9766, n9767, n9768, n9769,
n9770, n9771, n9772, n9773, n9774, n9775, n9776, n9777, n9778, n9779,
n9780, n9781, n9782, n9783, n9784, n9785, n9786, n9787, n9788, n9789,
n9790, n9791, n9792, n9793, n9794, n9795, n9796, n9797, n9798, n9799,
n9800, n9801, n9802, n9803, n9804, n9805, n9806, n9807, n9808, n9809,
n9810, n9811, n9812, n9813, n9814, n9815, n9816, n9817, n9818, n9819,
n9820, n9821, n9822, n9823, n9824, n9825, n9826, n9827, n9828, n9829,
n9830, n9831, n9832, n9833, n9834, n9835, n9836, n9837, n9838, n9839,
n9840, n9841, n9842, n9843, n9844, n9845, n9846, n9847, n9848, n9849,
n9850, n9851, n9852, n9853, n9854, n9855, n9856, n9857, n9858, n9859,
n9860, n9861, n9862, n9863, n9864, n9865, n9866, n9867, n9868, n9869,
n9870, n9871, n9872, n9873, n9874, n9875, n9876, n9877, n9878, n9879,
n9880, n9881, n9882, n9883, n9884, n9885, n9886, n9887, n9888, n9889,
n9890, n9891, n9892, n9893, n9894, n9895, n9896, n9897, n9898, n9899,
n9900, n9901, n9902, n9903, n9904, n9905, n9906, n9907, n9908, n9909,
n9910, n9911, n9912, n9913, n9914, n9915, n9916, n9917, n9918, n9919,
n9920, n9921, n9922, n9923, n9924, n9925, n9926, n9927, n9928, n9929,
n9930, n9931, n9932, n9933, n9934, n9935, n9936, n9937, n9938, n9939,
n9940, n9941, n9942, n9943, n9944, n9945, n9946, n9947, n9948, n9949,
n9950, n9951, n9952, n9953, n9954, n9955, n9956, n9957, n9958, n9959,
n9960, n9961, n9962, n9963, n9964, n9965, n9966, n9967, n9968, n9969,
n9970, n9971, n9972, n9973, n9974, n9975, n9976, n9977, n9978, n9979,
n9980, n9981, n9982, n9983, n9984, n9985, n9986, n9987, n9988, n9989,
n9990, n9991, n9992, n9993, n9994, n9995, n9996, n9997, n9998, n9999,
n10000, n10001, n10002, n10003, n10004, n10005, n10006, n10007,
n10008, n10009, n10010, n10011, n10012, n10013, n10014, n10015,
n10016, n10017, n10018, n10019, n10020, n10021, n10022, n10023,
n10024, n10025, n10026, n10027, n10028, n10029, n10030, n10031,
n10032, n10033, n10034, n10035, n10036, n10037, n10038, n10039,
n10040, n10041, n10042, n10043, n10044, n10045, n10046, n10047,
n10048, n10049, n10050, n10051, n10052, n10053, n10054, n10055,
n10056, n10057, n10058, n10059, n10060, n10061, n10062, n10063,
n10064, n10065, n10066, n10067, n10068, n10069, n10070, n10071,
n10072, n10073, n10074, n10075, n10076, n10077, n10078, n10079,
n10080, n10081, n10082, n10083, n10084, n10085, n10086, n10087,
n10088, n10089, n10090, n10091, n10092, n10093, n10094, n10095,
n10096, n10097, n10098, n10099, n10100, n10101, n10102, n10103,
n10104, n10105, n10106, n10107, n10108, n10109, n10110, n10111,
n10112, n10113, n10114, n10115, n10116, n10117, n10118, n10119,
n10120, n10121, n10122, n10123, n10124, n10125, n10126, n10127,
n10128, n10129, n10130, n10131, n10132, n10133, n10134, n10135,
n10136, n10137, n10138, n10139, n10140, n10141, n10142, n10143,
n10144, n10145, n10146, n10147, n10148, n10149, n10150, n10151,
n10152, n10153, n10154, n10155, n10156, n10157, n10158, n10159,
n10160, n10161, n10162, n10163, n10164, n10165, n10166, n10167,
n10168, n10169, n10170, n10171, n10172, n10173, n10174, n10175,
n10176, n10177, n10178, n10179, n10180, n10181, n10182, n10183,
n10184, n10185, n10186, n10187, n10188, n10189, n10190, n10191,
n10192, n10193, n10194, n10195, n10196, n10197, n10198, n10199,
n10200, n10201, n10202, n10203, n10204, n10205, n10206, n10207,
n10208, n10209, n10210, n10211, n10212, n10213, n10214, n10215,
n10216, n10217, n10218, n10219, n10220, n10221, n10222, n10223,
n10224, n10225, n10226, n10227, n10228, n10229, n10230, n10231,
n10232, n10233, n10234, n10235, n10236, n10237, n10238, n10239,
n10240, n10241, n10242, n10243, n10244, n10245, n10246, n10247,
n10248, n10249, n10250, n10251, n10252, n10253, n10254, n10255,
n10256, n10257, n10258, n10259, n10260, n10261, n10262, n10263,
n10264, n10265, n10266, n10267, n10268, n10269, n10270, n10271,
n10272, n10273, n10274, n10275, n10276, n10277, n10278, n10279,
n10280, n10281, n10282, n10283, n10284, n10285, n10286, n10287,
n10288, n10289, n10290, n10291, n10292, n10293, n10294, n10295,
n10296, n10297, n10298, n10299, n10300, n10301, n10302, n10303,
n10304, n10305, n10306, n10307, n10308, n10309, n10310, n10311,
n10312, n10313, n10314, n10315, n10316, n10317, n10318, n10319,
n10320, n10321, n10322, n10323, n10324, n10325, n10326, n10327,
n10328, n10329, n10330, n10331, n10332, n10333, n10334, n10335,
n10336, n10337, n10338, n10339, n10340, n10341, n10342, n10343,
n10344, n10345, n10346, n10347, n10348, n10349, n10350, n10351,
n10352, n10353, n10354, n10355, n10356, n10357, n10358, n10359,
n10360, n10361, n10362, n10363, n10364, n10365, n10366, n10367,
n10368, n10369, n10370, n10371, n10372, n10373, n10374, n10375,
n10376, n10377, n10378, n10379, n10380, n10381, n10382, n10383,
n10384, n10385, n10386, n10387, n10388, n10389, n10390, n10391,
n10392, n10393, n10394, n10395, n10396, n10397, n10398, n10399,
n10400, n10401, n10402, n10403, n10404, n10405, n10406, n10407,
n10408, n10409, n10410, n10411, n10412, n10413, n10414, n10415,
n10416, n10417, n10418, n10419, n10420, n10421, n10422, n10423,
n10424, n10425, n10426, n10427, n10428, n10429, n10430, n10431,
n10432, n10433, n10434, n10435, n10436, n10437, n10438, n10439,
n10440, n10441, n10442, n10443, n10444, n10445, n10446, n10447,
n10448, n10449, n10450, n10451, n10452, n10453, n10454, n10455,
n10456, n10457, n10458, n10459, n10460, n10461, n10462, n10463,
n10464, n10465, n10466, n10467, n10468, n10469, n10470, n10471,
n10472, n10473, n10474, n10475, n10476, n10477, n10478, n10479,
n10480, n10481, n10482, n10483, n10484, n10485, n10486, n10487,
n10488, n10489, n10490, n10491, n10492, n10493, n10494, n10495,
n10496, n10497, n10498, n10499, n10500, n10501, n10502, n10503,
n10504, n10505, n10506, n10507, n10508, n10509, n10510, n10511,
n10512, n10513, n10514, n10515, n10516, n10517, n10518, n10519,
n10520, n10521, n10522, n10523, n10524, n10525, n10526, n10527,
n10528, n10529, n10530, n10531, n10532, n10533, n10534, n10535,
n10536, n10537, n10538, n10539, n10540, n10541, n10542, n10543,
n10544, n10545, n10546, n10547, n10548, n10549, n10550, n10551,
n10552, n10553, n10554, n10555, n10556, n10557, n10558, n10559,
n10560, n10561, n10562, n10563, n10564, n10565, n10566, n10567,
n10568, n10569, n10570, n10571, n10572, n10573, n10574, n10575,
n10576, n10577, n10578, n10579, n10580, n10581, n10582, n10583,
n10584, n10585, n10586, n10587, n10588, n10589, n10590, n10591,
n10592, n10593, n10594, n10595, n10596, n10597, n10598, n10599,
n10600, n10601, n10602, n10603, n10604, n10605, n10606, n10607,
n10608, n10609, n10610, n10611, n10612, n10613, n10614, n10615,
n10616, n10617, n10618, n10619, n10620, n10621, n10622, n10623,
n10624, n10625, n10626, n10627, n10628, n10629, n10630, n10631,
n10632, n10633, n10634, n10635, n10636, n10637, n10638, n10639,
n10640, n10641, n10642, n10643, n10644, n10645, n10646, n10647,
n10648, n10649, n10650, n10651, n10652, n10653, n10654, n10655,
n10656, n10657, n10658, n10659, n10660, n10661, n10662, n10663,
n10664, n10665, n10666, n10667, n10668, n10669, n10670, n10671,
n10672, n10673, n10674, n10675, n10676, n10677, n10678, n10679,
n10680, n10681, n10682, n10683, n10684, n10685, n10686, n10687,
n10688, n10689, n10690, n10691, n10692, n10693, n10694, n10695,
n10696, n10697, n10698, n10699, n10700, n10701, n10702, n10703,
n10704, n10705, n10706, n10707, n10708, n10709, n10710, n10711,
n10712, n10713, n10714, n10715, n10716, n10717, n10718, n10719,
n10720, n10721, n10722, n10723, n10724, n10725, n10726, n10727,
n10728, n10729, n10730, n10731, n10732, n10733, n10734, n10735,
n10736, n10737, n10738, n10739, n10740, n10741, n10742, n10743,
n10744, n10745, n10746, n10747, n10748, n10749, n10750, n10751,
n10752, n10753, n10754, n10755, n10756, n10757, n10758, n10759,
n10760, n10761, n10762, n10763, n10764, n10765, n10766, n10767,
n10768, n10769, n10770, n10771, n10772, n10773, n10774, n10775,
n10776, n10777, n10778, n10779, n10780, n10781, n10782, n10783,
n10784, n10785, n10786, n10787, n10788, n10789, n10790, n10791,
n10792, n10793, n10794, n10795, n10796, n10797, n10798, n10799,
n10800, n10801, n10802, n10803, n10804, n10805, n10806, n10807,
n10808, n10809, n10810, n10811, n10812, n10813, n10814, n10815,
n10816, n10817, n10818, n10819, n10820, n10821, n10822, n10823,
n10824, n10825, n10826, n10827, n10828, n10829, n10830, n10831,
n10832, n10833, n10834, n10835, n10836, n10837, n10838, n10839,
n10840, n10841, n10842, n10843, n10844, n10845, n10846, n10847,
n10848, n10849, n10850, n10851, n10852, n10853, n10854, n10855,
n10856, n10857, n10858, n10859, n10860, n10861, n10862, n10863,
n10864, n10865, n10866, n10867, n10868, n10869, n10870, n10871,
n10872, n10873, n10874, n10875, n10876, n10877, n10878, n10879,
n10880, n10881, n10882, n10883, n10884, n10885, n10886, n10887,
n10888, n10889, n10890, n10891, n10892, n10893, n10894, n10895,
n10896, n10897, n10898, n10899, n10900, n10901, n10902, n10903,
n10904, n10905, n10906, n10907, n10908, n10909, n10910, n10911,
n10912, n10913, n10914, n10915, n10916, n10917, n10918, n10919,
n10920, n10921, n10922, n10923, n10924, n10925, n10926, n10927,
n10928, n10929, n10930, n10931, n10932, n10933, n10934, n10935,
n10936, n10937, n10938, n10939, n10940, n10941, n10942, n10943,
n10944, n10945, n10946, n10947, n10948, n10949, n10950, n10951,
n10952, n10953, n10954, n10955, n10956, n10957, n10958, n10959,
n10960, n10961, n10962, n10963, n10964, n10965, n10966, n10967,
n10968, n10969, n10970, n10971, n10972, n10973, n10974, n10975,
n10976, n10977, n10978, n10979, n10980, n10981, n10982, n10983,
n10984, n10985, n10986, n10987, n10988, n10989, n10990, n10991,
n10992, n10993, n10994, n10995, n10996, n10997, n10998, n10999,
n11000, n11001, n11002, n11003, n11004, n11005, n11006, n11007,
n11008, n11009, n11010, n11011, n11012, n11013, n11014, n11015,
n11016, n11017, n11018, n11019, n11020, n11021, n11022, n11023,
n11024, n11025, n11026, n11027, n11028, n11029, n11030, n11031,
n11032, n11033, n11034, n11035, n11036, n11037, n11038, n11039,
n11040, n11041, n11042, n11043, n11044, n11045, n11046, n11047,
n11048, n11049, n11050, n11051, n11052, n11053, n11054, n11055,
n11056, n11057, n11058, n11059, n11060, n11061, n11062, n11063,
n11064, n11065, n11066, n11067, n11068, n11069, n11070, n11071,
n11072, n11073, n11074, n11075, n11076, n11077, n11078, n11079,
n11080, n11081, n11082, n11083, n11084, n11085, n11086, n11087,
n11088, n11089, n11090, n11091, n11092, n11093, n11094, n11095,
n11096, n11097, n11098, n11099, n11100, n11101, n11102, n11103,
n11104, n11105, n11106, n11107, n11108, n11109, n11110, n11111,
n11112, n11113, n11114, n11115, n11116, n11117, n11118, n11119,
n11120, n11121, n11122, n11123, n11124, n11125, n11126, n11127,
n11128, n11129, n11130, n11131, n11132, n11133, n11134, n11135,
n11136, n11137, n11138, n11139, n11140, n11141, n11142, n11143,
n11144, n11145, n11146, n11147, n11148, n11149, n11150, n11151,
n11152, n11153, n11154, n11155, n11156, n11157, n11158, n11159,
n11160, n11161, n11162, n11163, n11164, n11165, n11166, n11167,
n11168, n11169, n11170, n11171, n11172, n11173, n11174, n11175,
n11176, n11177, n11178, n11179, n11180, n11181, n11182, n11183,
n11184, n11185, n11186, n11187, n11188, n11189, n11190, n11191,
n11192, n11193, n11194, n11195, n11196, n11197, n11198, n11199,
n11200, n11201, n11202, n11203, n11204, n11205, n11206, n11207,
n11208, n11209, n11210, n11211, n11212, n11213, n11214, n11215,
n11216, n11217, n11218, n11219, n11220, n11221, n11222, n11223,
n11224, n11225, n11226, n11227, n11228, n11229, n11230, n11231,
n11232, n11233, n11234, n11235, n11236, n11237, n11238, n11239,
n11240, n11241, n11242, n11243, n11244, n11245, n11246, n11247,
n11248, n11249, n11250, n11251, n11252, n11253, n11254, n11255,
n11256, n11257, n11258, n11259, n11260, n11261, n11262, n11263,
n11264, n11265, n11266, n11267, n11268, n11269, n11270, n11271,
n11272, n11273, n11274, n11275, n11276, n11277, n11278, n11279,
n11280, n11281, n11282, n11283, n11284, n11285, n11286, n11287,
n11288, n11289, n11290, n11291, n11292, n11293, n11294, n11295,
n11296, n11297, n11298, n11299, n11300, n11301, n11302, n11303,
n11304, n11305, n11306, n11307, n11308, n11309, n11310, n11311,
n11312, n11313, n11314, n11315, n11316, n11317, n11318, n11319,
n11320, n11321, n11322, n11323, n11324, n11325, n11326, n11327,
n11328, n11329, n11330, n11331, n11332, n11333, n11334, n11335,
n11336, n11337, n11338, n11339, n11340, n11341, n11342, n11343,
n11344, n11345, n11347, n11348, n11349, n11350, n11351, n11352,
n11353, n11354, n11355, n11356, n11357, n11358, n11359, n11360,
n11361, n11362, n11363, n11364, n11365, n11366, n11367, n11368,
n11369, n11370, n11371, n11372, n11373, n11374, n11375, n11376,
n11377, n11378, n11379, n11380, n11381, n11382, n11383, n11384,
n11385, n11386, n11387, n11388, n11389, n11390, n11391, n11392,
n11393, n11394, n11395, n11396, n11397, n11398, n11399, n11400,
n11401, n11402, n11403, n11404, n11405, n11406, n11407, n11408,
n11409, n11410, n11411, n11412, n11413, n11414, n11415, n11416,
n11417, n11418, n11419, n11420, n11421, n11422, n11423, n11424,
n11425, n11426, n11427, n11428, n11429, n11430, n11431, n11432,
n11433, n11434, n11435, n11436, n11437, n11438, n11439, n11440,
n11441, n11442, n11443, n11444, n11445, n11446, n11447, n11448,
n11449, n11450, n11451, n11452, n11453, n11454, n11455, n11456,
n11457, n11458, n11459, n11460, n11461, n11462, n11463, n11464,
n11465, n11466, n11467, n11468, n11469, n11470, n11471, n11472,
n11473, n11474, n11475, n11476, n11477, n11478, n11479, n11480,
n11481, n11482, n11483, n11484, n11485, n11486, n11487, n11488,
n11489, n11490, n11491, n11492, n11493, n11494, n11495, n11496,
n11497, n11498, n11499, n11500, n11501, n11502, n11503, n11504,
n11505, n11506, n11507, n11508, n11509, n11510, n11511, n11512,
n11513, n11514, n11515, n11516, n11517, n11518, n11519, n11520,
n11521, n11522, n11523, n11524, n11525, n11526, n11527, n11528,
n11529, n11530, n11531, n11532, n11533, n11534, n11535, n11536,
n11537, n11538, n11539, n11540, n11541, n11542, n11543, n11544,
n11545, n11546, n11547, n11548, n11549, n11550, n11551, n11552,
n11553, n11554, n11555, n11556, n11557, n11558, n11559, n11560,
n11561, n11562, n11563, n11564, n11565, n11566, n11567, n11568,
n11569, n11570, n11571, n11572, n11573, n11574, n11575, n11576,
n11577, n11578, n11579, n11580, n11581, n11582, n11583, n11584,
n11585, n11586, n11587, n11588, n11589, n11590, n11591, n11592,
n11593, n11594, n11595, n11596, n11597, n11598, n11599, n11600,
n11601, n11602, n11603, n11604, n11605, n11606, n11607, n11608,
n11609, n11610, n11611, n11612, n11613, n11614, n11615, n11616,
n11617, n11618, n11619, n11620, n11621, n11622, n11623, n11624,
n11625, n11626, n11627, n11628, n11629, n11630, n11631, n11632,
n11633, n11634, n11635, n11636, n11637, n11638, n11639, n11640,
n11641, n11642, n11643, n11644, n11645, n11646, n11647, n11648,
n11649, n11650, n11651, n11652, n11653, n11654, n11655, n11656,
n11657, n11658, n11659, n11660, n11661, n11662, n11663, n11664,
n11665, n11666, n11667, n11668, n11669, n11670, n11671, n11672,
n11673, n11674, n11675, n11676, n11677, n11678, n11679, n11680,
n11681, n11682, n11683, n11684, n11685, n11686, n11687, n11688,
n11689, n11690, n11691, n11692, n11693, n11694, n11695, n11696,
n11697, n11698, n11699, n11700, n11701, n11702, n11703, n11704,
n11705, n11706, n11707, n11708, n11709, n11710, n11711, n11712,
n11713, n11714, n11715, n11716, n11717, n11718, n11719, n11720,
n11721, n11722, n11723, n11724, n11725, n11726, n11727, n11728,
n11729, n11730, n11731, n11732, n11733, n11734, n11735, n11736,
n11737, n11738, n11739, n11740, n11741, n11742, n11743, n11744,
n11745, n11746, n11747, n11748, n11749, n11750, n11751, n11752,
n11753, n11754, n11755, n11756, n11757, n11758, n11759, n11760,
n11761, n11762, n11763, n11764, n11765, n11766, n11767, n11768,
n11769, n11770, n11771, n11772, n11773, n11774, n11775, n11776,
n11777, n11778, n11779, n11780, n11781, n11782, n11783, n11784,
n11785, n11786, n11787, n11788, n11789, n11790, n11791, n11792,
n11793, n11794, n11795, n11796, n11797, n11798, n11799, n11800,
n11801, n11802, n11803, n11804, n11805, n11806, n11807, n11808,
n11809, n11810, n11811, n11812, n11813, n11814, n11815, n11816,
n11817, n11818, n11819, n11820, n11821, n11822, n11823, n11824,
n11825, n11826, n11827, n11828, n11829, n11830, n11831, n11832,
n11833, n11834, n11835, n11836, n11837, n11838, n11839, n11840,
n11841, n11842, n11843, n11844, n11845, n11846, n11847, n11848,
n11849, n11850, n11851, n11852, n11853, n11854, n11855, n11856,
n11857, n11858, n11859, n11860, n11861, n11862, n11863, n11864,
n11865, n11866, n11867, n11868, n11869, n11870, n11871, n11872,
n11873, n11874, n11875, n11876, n11877, n11878, n11879, n11880,
n11881, n11882, n11883, n11884, n11885, n11886, n11887, n11888,
n11889, n11890, n11891, n11892, n11893, n11894, n11895, n11896,
n11897, n11898, n11899, n11900, n11901, n11902, n11903, n11904,
n11905, n11906, n11907, n11908, n11909, n11910, n11911, n11912,
n11913, n11914, n11915, n11916, n11917, n11918, n11919, n11920,
n11921, n11922, n11923, n11924, n11925, n11926, n11927, n11928,
n11929, n11930, n11931, n11932, n11933, n11934, n11935, n11936,
n11937, n11938, n11939, n11940, n11941, n11942, n11943, n11944,
n11945, n11946, n11947, n11948, n11949, n11950, n11951, n11952,
n11953, n11954, n11955, n11956, n11957, n11958, n11959, n11960,
n11961, n11962, n11963, n11964, n11965, n11966, n11967, n11968,
n11969, n11970, n11971, n11972, n11973, n11974, n11975, n11976,
n11977, n11978, n11979, n11980, n11981, n11982, n11983, n11984,
n11985, n11986, n11987, n11988, n11989, n11990, n11991, n11992,
n11993, n11994, n11995, n11996, n11997, n11998, n11999, n12000,
n12001, n12002, n12003, n12004, n12005, n12006, n12007, n12008,
n12009, n12010, n12011, n12012, n12013, n12014, n12015, n12016,
n12017, n12018, n12019, n12020, n12021, n12022, n12023, n12024,
n12025, n12026, n12027, n12028, n12029, n12030, n12031, n12032,
n12033, n12034, n12035, n12036, n12037, n12038, n12039, n12040,
n12041, n12042, n12043, n12044, n12045, n12046, n12047, n12048,
n12049, n12050, n12051, n12052, n12053, n12054, n12055, n12056,
n12057, n12058, n12059, n12060, n12061, n12062, n12063, n12064,
n12065, n12066, n12067, n12068, n12069, n12070, n12071, n12072,
n12073, n12074, n12075, n12076, n12077, n12078, n12079, n12080,
n12081, n12082, n12083, n12084, n12085, n12086, n12087, n12088,
n12089, n12090, n12091, n12092, n12093, n12094, n12095, n12096,
n12097, n12098, n12099, n12100, n12101, n12102, n12103, n12104,
n12105, n12106, n12107, n12108, n12109, n12110, n12111, n12112,
n12113, n12114, n12115, n12116, n12117, n12118, n12119, n12120,
n12121, n12122, n12123, n12124, n12125, n12126, n12127, n12128,
n12129, n12130, n12131, n12132, n12133, n12134, n12135, n12136,
n12137, n12138, n12139, n12140, n12141, n12142, n12143, n12144,
n12145, n12146, n12147, n12148, n12149, n12150, n12151, n12152,
n12153, n12154, n12155, n12156, n12157, n12158, n12159, n12160,
n12161, n12163, n12164, n12166, n12167, n12168, n12169, n12170,
n12171, n12172, n12173, n12174, n12175, n12176, n12177, n12178,
n12179, n12180, n12181, n12182, n12183, n12184, n12185, n12186,
n12187, n12188, n12189, n12190, n12191, n12192, n12193, n12194,
n12195, n12196, n12197, n12198, n12199, n12200, n12201, n12202,
n12203, n12204, n12205, n12206, n12207, n12208, n12209, n12210,
n12211, n12212, n12213, n12214, n12215, n12216, n12217, n12218,
n12219, n12220, n12221, n12222, n12223, n12224, n12225, n12226,
n12227, n12228, n12229, n12230, n12231, n12232, n12233, n12234,
n12235, n12236, n12237, n12238, n12239, n12240, n12241, n12242,
n12243, n12244, n12245, n12246, n12247, n12248, n12249, n12250,
n12251, n12252, n12253, n12254, n12255, n12256, n12257, n12258,
n12259, n12260, n12261, n12262, n12263, n12264, n12265, n12266,
n12267, n12268, n12269, n12270, n12271, n12272, n12273, n12274,
n12275, n12276, n12277, n12278, n12279, n12280, n12281, n12282,
n12283, n12284, n12285, n12286, n12287, n12288, n12289, n12290,
n12291, n12292, n12293, n12294, n12295, n12296, n12297, n12298,
n12299, n12300, n12301, n12302, n12303, n12304, n12305, n12306,
n12307, n12308, n12309, n12310, n12311, n12312, n12313, n12314,
n12315, n12316, n12317, n12318, n12319, n12320, n12321, n12322,
n12323, n12324, n12325, n12326, n12327, n12328, n12329, n12330,
n12331, n12332, n12333, n12334, n12335, n12336, n12337, n12338,
n12339, n12340, n12341, n12342, n12343, n12344, n12345, n12346,
n12347, n12348, n12349, n12350, n12351, n12352, n12353, n12354,
n12355, n12356, n12357, n12358, n12359, n12360, n12361, n12362,
n12363, n12364, n12365, n12366, n12367, n12368, n12369, n12370,
n12371, n12372, n12373, n12374, n12375, n12376, n12377, n12378,
n12379, n12380, n12381, n12382, n12383, n12384, n12385, n12386,
n12387, n12388, n12389, n12390, n12391, n12392, n12394, n12395;
wire [26:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [63:0] Op_MX;
wire [63:0] Op_MY;
wire [11:0] exp_oper_result;
wire [52:1] Add_result;
wire [47:0] Sgf_normalized_result;
wire [3:1] FS_Module_state_reg;
wire [11:6] Sgf_operation_ODD1_S_B;
wire [53:33] Sgf_operation_ODD1_Q_right;
wire [50:0] Sgf_operation_ODD1_Q_left;
DFFRX4TS FS_Module_state_reg_reg_1_ ( .D(n712), .CK(clk), .RN(n11975), .Q(
FS_Module_state_reg[1]), .QN(n11820) );
DFFRX4TS FS_Module_state_reg_reg_2_ ( .D(n711), .CK(clk), .RN(n11975), .Q(
FS_Module_state_reg[2]), .QN(n11887) );
DFFRX4TS FS_Module_state_reg_reg_3_ ( .D(n714), .CK(clk), .RN(n11975), .Q(
FS_Module_state_reg[3]), .QN(n11798) );
DFFRX2TS R_910 ( .D(n691), .CK(clk), .RN(n11986), .Q(Op_MX[45]), .QN(n11903)
);
DFFRX2TS R_529 ( .D(n685), .CK(clk), .RN(n11987), .Q(Op_MX[39]), .QN(n11905)
);
DFFRX2TS R_716 ( .D(n671), .CK(clk), .RN(n12240), .Q(Op_MX[25]), .QN(n11904)
);
DFFRX2TS R_541 ( .D(n668), .CK(clk), .RN(n12240), .Q(Op_MX[22]), .QN(n11899)
);
DFFRX2TS R_771 ( .D(n656), .CK(clk), .RN(n1854), .Q(Op_MX[10]), .QN(n11901)
);
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n558), .CK(clk), .RN(n11996),
.Q(Add_result[21]), .QN(n11838) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n559), .CK(clk), .RN(n11713),
.Q(Add_result[20]), .QN(n11839) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_62_ ( .D(n644), .CK(clk), .RN(
n12231), .Q(Op_MY[62]), .QN(n11799) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_59_ ( .D(n641), .CK(clk), .RN(
n1827), .Q(Op_MY[59]), .QN(n11792) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_57_ ( .D(n639), .CK(clk), .RN(
n11996), .Q(Op_MY[57]), .QN(n11790) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_56_ ( .D(n638), .CK(clk), .RN(
n11972), .Q(Op_MY[56]), .QN(n11791) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_55_ ( .D(n637), .CK(clk), .RN(
n1854), .Q(Op_MY[55]), .QN(n11797) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_54_ ( .D(n636), .CK(clk), .RN(
n11994), .Q(Op_MY[54]), .QN(n11818) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_53_ ( .D(n635), .CK(clk), .RN(
n11994), .Q(Op_MY[53]), .QN(n11819) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_47_ ( .D(n629), .CK(clk), .RN(
n11993), .Q(Op_MY[47]), .QN(n12112) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n608), .CK(clk), .RN(
n11997), .Q(Op_MY[26]), .QN(n11955) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n607), .CK(clk), .RN(
n11997), .Q(Op_MY[25]), .QN(n12030) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n605), .CK(clk), .RN(
n11995), .Q(Op_MY[23]), .QN(n12046) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n603), .CK(clk), .RN(
n11995), .Q(Op_MY[21]), .QN(n12029) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_24_ ( .D(n445), .CK(clk), .RN(
n12223), .Q(P_Sgf[24]), .QN(n2129) );
DFFRX4TS Sel_B_Q_reg_1_ ( .D(n418), .CK(clk), .RN(n12234), .Q(
FSM_selector_B[1]), .QN(n1873) );
DFFSX1TS R_11 ( .D(n12309), .CK(clk), .SN(n11983), .Q(n12205) );
DFFSX1TS R_17 ( .D(n12297), .CK(clk), .SN(n11982), .Q(n12203) );
DFFSX1TS R_20 ( .D(n12293), .CK(clk), .SN(n11983), .Q(n12202) );
DFFSX1TS R_23 ( .D(n12289), .CK(clk), .SN(n11983), .QN(n1693) );
DFFSX1TS R_26 ( .D(n12277), .CK(clk), .SN(n11985), .Q(n12201) );
DFFSX1TS R_29 ( .D(n12273), .CK(clk), .SN(n12227), .Q(n12200) );
DFFSX1TS R_32 ( .D(n12269), .CK(clk), .SN(n9664), .Q(n12199) );
DFFSX1TS R_44 ( .D(n12260), .CK(clk), .SN(n11985), .Q(n12194) );
DFFSX1TS R_47 ( .D(n12256), .CK(clk), .SN(n11985), .Q(n12193) );
DFFSX1TS R_50 ( .D(n12252), .CK(clk), .SN(n12227), .Q(n12192) );
DFFSX1TS R_65 ( .D(n12345), .CK(clk), .SN(n11984), .Q(n12187) );
DFFSX1TS R_68 ( .D(n12337), .CK(clk), .SN(n11448), .Q(n12186) );
DFFSX1TS R_71 ( .D(n12333), .CK(clk), .SN(n11984), .Q(n12185) );
DFFSX1TS R_74 ( .D(n12329), .CK(clk), .SN(n11715), .Q(n12184) );
DFFSX1TS R_77 ( .D(n12325), .CK(clk), .SN(n12221), .Q(n12183) );
DFFSX1TS R_80 ( .D(n12321), .CK(clk), .SN(n11983), .Q(n12182) );
DFFSX1TS R_83 ( .D(n12317), .CK(clk), .SN(n11983), .Q(n12181) );
DFFSX1TS R_86 ( .D(n12313), .CK(clk), .SN(n11984), .Q(n12180) );
DFFSX1TS R_89 ( .D(n12305), .CK(clk), .SN(n11984), .Q(n12179) );
DFFSX1TS R_92 ( .D(n12285), .CK(clk), .SN(n11984), .Q(n12178) );
DFFSX1TS R_95 ( .D(n12281), .CK(clk), .SN(n12227), .Q(n12177) );
DFFSX1TS R_98 ( .D(n12341), .CK(clk), .SN(n12226), .Q(n12176) );
DFFRXLTS R_787 ( .D(n9726), .CK(clk), .RN(n10318), .QN(n11896) );
DFFRXLTS R_808 ( .D(n696), .CK(clk), .RN(n1957), .QN(n11895) );
DFFRXLTS R_904 ( .D(n694), .CK(clk), .RN(n1957), .QN(n11894) );
DFFRXLTS R_2038 ( .D(n455), .CK(clk), .RN(n12225), .Q(n12119) );
DFFRXLTS R_2200 ( .D(n451), .CK(clk), .RN(n1023), .Q(n12115) );
DFFSX1TS R_2766 ( .D(n12379), .CK(clk), .SN(n12223), .QN(n11834) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_57_ ( .D(n703), .CK(clk), .RN(
n11974), .Q(Op_MX[57]), .QN(n11827) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_58_ ( .D(n704), .CK(clk), .RN(
n11973), .Q(Op_MX[58]), .QN(n11826) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_63_ ( .D(n287),
.CK(clk), .RN(n12240), .Q(final_result_ieee[63]), .QN(n11971) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n326),
.CK(clk), .RN(n1976), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n325),
.CK(clk), .RN(n1828), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n324),
.CK(clk), .RN(n12238), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n323),
.CK(clk), .RN(n11974), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n322),
.CK(clk), .RN(n11702), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n321),
.CK(clk), .RN(n11702), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n320),
.CK(clk), .RN(n1891), .Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_32_ ( .D(n319),
.CK(clk), .RN(n1867), .Q(final_result_ieee[32]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_33_ ( .D(n318),
.CK(clk), .RN(n11998), .Q(final_result_ieee[33]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_34_ ( .D(n317),
.CK(clk), .RN(n11129), .Q(final_result_ieee[34]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_35_ ( .D(n316),
.CK(clk), .RN(n12239), .Q(final_result_ieee[35]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_36_ ( .D(n315),
.CK(clk), .RN(n12239), .Q(final_result_ieee[36]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_37_ ( .D(n314),
.CK(clk), .RN(n12239), .Q(final_result_ieee[37]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_38_ ( .D(n313),
.CK(clk), .RN(n12239), .Q(final_result_ieee[38]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_39_ ( .D(n312),
.CK(clk), .RN(n12239), .Q(final_result_ieee[39]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_40_ ( .D(n311),
.CK(clk), .RN(n12239), .Q(final_result_ieee[40]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_41_ ( .D(n310),
.CK(clk), .RN(n12239), .Q(final_result_ieee[41]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_42_ ( .D(n309),
.CK(clk), .RN(n12239), .Q(final_result_ieee[42]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_43_ ( .D(n308),
.CK(clk), .RN(n12239), .Q(final_result_ieee[43]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_44_ ( .D(n307),
.CK(clk), .RN(n12239), .Q(final_result_ieee[44]) );
DFFRX1TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_54_ ( .D(n297),
.CK(clk), .RN(n11994), .Q(final_result_ieee[54]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n556), .CK(clk), .RN(n1891),
.Q(Add_result[23]), .QN(n11868) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_42_ ( .D(n537), .CK(clk), .RN(n10321),
.Q(Add_result[42]), .QN(n11849) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_45_ ( .D(n534), .CK(clk), .RN(n12241),
.Q(Add_result[45]), .QN(n11846) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_49_ ( .D(n530), .CK(clk), .RN(n1827),
.Q(Add_result[49]), .QN(n11843) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_50_ ( .D(n529), .CK(clk), .RN(n2006),
.Q(Add_result[50]), .QN(n11842) );
DFFRXLTS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n581), .CK(clk),
.RN(n11972), .Q(zero_flag), .QN(n11807) );
DFFRXLTS R_886 ( .D(n592), .CK(clk), .RN(n12233), .Q(Op_MY[10]), .QN(n11928)
);
DFFRXLTS R_806 ( .D(n1446), .CK(clk), .RN(n2006), .Q(n12146), .QN(n11925) );
DFFRXLTS R_545 ( .D(n11804), .CK(clk), .RN(n1829), .Q(n12213), .QN(n11919)
);
DFFRXLTS R_2230 ( .D(n596), .CK(clk), .RN(n11998), .Q(Op_MY[14]), .QN(n11965) );
DFFRXLTS R_729 ( .D(n654), .CK(clk), .RN(n1974), .Q(Op_MX[8]), .QN(n11922)
);
DFFRXLTS R_776 ( .D(n658), .CK(clk), .RN(n10318), .Q(Op_MX[12]), .QN(n11921)
);
DFFRXLTS R_2889 ( .D(n580), .CK(clk), .RN(n11990), .Q(n12102) );
DFFRXLTS R_2126 ( .D(n626), .CK(clk), .RN(n12232), .Q(Op_MY[44]), .QN(n11917) );
DFFRXLTS R_1542 ( .D(n589), .CK(clk), .RN(n12233), .Q(Op_MY[7]), .QN(n11967)
);
DFFRXLTS R_1278 ( .D(n619), .CK(clk), .RN(n12232), .QN(n11950) );
DFFRXLTS R_780 ( .D(n9729), .CK(clk), .RN(n11990), .Q(n12211), .QN(n11953)
);
DFFRXLTS R_1954 ( .D(n622), .CK(clk), .RN(n12232), .Q(Op_MY[40]), .QN(n11968) );
DFFRXLTS R_2214 ( .D(n600), .CK(clk), .RN(n11995), .Q(Op_MY[18]), .QN(n11926) );
DFFRXLTS R_2268 ( .D(n599), .CK(clk), .RN(n12232), .Q(Op_MY[17]), .QN(n11927) );
DFFRXLTS R_722 ( .D(n11806), .CK(clk), .RN(n11996), .Q(n12210), .QN(n11929)
);
DFFRXLTS R_811 ( .D(n9693), .CK(clk), .RN(n1974), .Q(n12212), .QN(n11918) );
DFFRXLTS R_1978 ( .D(n590), .CK(clk), .RN(n12233), .Q(Op_MY[8]), .QN(n11914)
);
DFFRXLTS R_781 ( .D(n662), .CK(clk), .RN(n972), .Q(Op_MX[16]), .QN(n11900)
);
DFFRXLTS R_2208 ( .D(n624), .CK(clk), .RN(n12232), .Q(Op_MY[42]), .QN(n11963) );
DFFRXLTS R_2258 ( .D(n594), .CK(clk), .RN(n12233), .Q(Op_MY[12]), .QN(n11961) );
DFFRXLTS R_2257 ( .D(n621), .CK(clk), .RN(n11995), .Q(Op_MY[39]), .QN(n11964) );
DFFRXLTS R_719 ( .D(n585), .CK(clk), .RN(n12234), .Q(Op_MY[3]), .QN(n11962)
);
DFFSX2TS R_2890 ( .D(n12216), .CK(clk), .SN(n1975), .Q(n12101) );
DFFRXLTS R_846 ( .D(n695), .CK(clk), .RN(n1957), .Q(Op_MX[49]), .QN(n11912)
);
DFFRXLTS R_1974 ( .D(n593), .CK(clk), .RN(n12233), .Q(Op_MY[11]), .QN(n11913) );
DFFRXLTS R_752 ( .D(n587), .CK(clk), .RN(n12233), .Q(Op_MY[5]), .QN(n11908)
);
DFFRXLTS R_801 ( .D(n696), .CK(clk), .RN(n1957), .Q(n11952) );
DFFRXLTS R_890 ( .D(n588), .CK(clk), .RN(n12233), .Q(Op_MY[6]), .QN(n11957)
);
DFFRXLTS R_881 ( .D(n12137), .CK(clk), .RN(n1829), .QN(n11811) );
DFFSX1TS R_3150 ( .D(n12258), .CK(clk), .SN(n11990), .Q(n12032) );
DFFSX2TS R_3149 ( .D(n12259), .CK(clk), .SN(n1976), .Q(n12033) );
DFFSX1TS R_3151 ( .D(n12257), .CK(clk), .SN(n11999), .Q(n12031) );
DFFRXLTS R_537 ( .D(n649), .CK(clk), .RN(n2006), .QN(n11942) );
DFFRX2TS R_740 ( .D(n661), .CK(clk), .RN(n971), .QN(n11795) );
DFFRX2TS R_556 ( .D(n679), .CK(clk), .RN(n12242), .QN(n11815) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n352), .CK(clk), .RN(n12236),
.Q(underflow_flag), .QN(n11835) );
DFFRXLTS R_919 ( .D(n681), .CK(clk), .RN(n11987), .QN(n11931) );
DFFRX2TS R_871 ( .D(n12139), .CK(clk), .RN(n12238), .QN(n11947) );
DFFSX2TS R_877 ( .D(n11805), .CK(clk), .SN(n1976), .Q(n12244) );
DFFRX2TS R_767 ( .D(n1441), .CK(clk), .RN(n11988), .QN(n11793) );
DFFSX1TS R_3244 ( .D(n12254), .CK(clk), .SN(n1855), .Q(n12003) );
DFFSX2TS R_3243 ( .D(n12255), .CK(clk), .SN(n1975), .Q(n12004) );
DFFSX1TS R_3245 ( .D(n12253), .CK(clk), .SN(n11989), .Q(n12002) );
DFFRXLTS R_2477 ( .D(n633), .CK(clk), .RN(n11993), .QN(n11817) );
DFFRX2TS R_826 ( .D(n686), .CK(clk), .RN(n11987), .Q(n12215), .QN(n12246) );
DFFSX1TS R_2667 ( .D(Sgf_operation_Result_28_), .CK(clk), .SN(n11978), .Q(
n12111) );
DFFSX1TS R_2878 ( .D(n12291), .CK(clk), .SN(n12243), .Q(n12108) );
DFFSX1TS R_2892 ( .D(n12307), .CK(clk), .SN(n12243), .Q(n12099) );
DFFSX1TS R_2898 ( .D(n12299), .CK(clk), .SN(n1867), .Q(n12093) );
DFFSX1TS R_2907 ( .D(n12279), .CK(clk), .SN(n1855), .Q(n12084) );
DFFSX1TS R_2919 ( .D(n12262), .CK(clk), .SN(n2006), .Q(n12072) );
DFFSX1TS R_2925 ( .D(n12347), .CK(clk), .SN(n11999), .Q(n12066) );
DFFSX1TS R_3229 ( .D(n12339), .CK(clk), .SN(n11989), .Q(n12018) );
DFFSX2TS R_2877 ( .D(n12292), .CK(clk), .SN(n12243), .Q(n12109) );
DFFSX2TS R_2891 ( .D(n12308), .CK(clk), .SN(n12243), .Q(n12100) );
DFFSX2TS R_2897 ( .D(n12300), .CK(clk), .SN(n1975), .Q(n12094) );
DFFSX2TS R_2906 ( .D(n12280), .CK(clk), .SN(n1976), .Q(n12085) );
DFFSX2TS R_2909 ( .D(n12276), .CK(clk), .SN(n11989), .Q(n12082) );
DFFSX2TS R_2918 ( .D(n12263), .CK(clk), .SN(n1854), .Q(n12073) );
DFFSX2TS R_2924 ( .D(n12348), .CK(clk), .SN(n1974), .Q(n12067) );
DFFSX2TS R_3099 ( .D(n12344), .CK(clk), .SN(n12001), .Q(n12049) );
DFFSX2TS R_3228 ( .D(n12340), .CK(clk), .SN(n11989), .Q(n12019) );
DFFSX1TS R_2879 ( .D(n12290), .CK(clk), .SN(n11988), .Q(n12107) );
DFFSX1TS R_2893 ( .D(n12306), .CK(clk), .SN(n12243), .Q(n12098) );
DFFSX1TS R_2899 ( .D(n12298), .CK(clk), .SN(n11987), .Q(n12092) );
DFFSX1TS R_2920 ( .D(n12261), .CK(clk), .SN(n2010), .Q(n12071) );
DFFSX1TS R_3133 ( .D(n12322), .CK(clk), .SN(n12001), .Q(n12037) );
DFFSX1TS R_2881 ( .D(n12359), .CK(clk), .SN(n11992), .Q(n12105) );
DFFSX1TS R_2895 ( .D(n12303), .CK(clk), .SN(n12242), .Q(n12096) );
DFFSX1TS R_2901 ( .D(n12295), .CK(clk), .SN(n2009), .Q(n12090) );
DFFSX1TS R_2904 ( .D(n12283), .CK(clk), .SN(n1974), .Q(n12087) );
DFFSX1TS R_2913 ( .D(n12315), .CK(clk), .SN(n1829), .Q(n12078) );
DFFSX1TS R_2916 ( .D(n12266), .CK(clk), .SN(n1867), .Q(n12075) );
DFFSX1TS R_2922 ( .D(n12350), .CK(clk), .SN(n1855), .Q(n12069) );
DFFSX1TS R_2930 ( .D(n12365), .CK(clk), .SN(n11992), .Q(n12063) );
DFFSX1TS R_2933 ( .D(n12356), .CK(clk), .SN(n11989), .Q(n12060) );
DFFSX1TS R_3077 ( .D(n12362), .CK(clk), .SN(n10318), .Q(n12051) );
DFFSX1TS R_3126 ( .D(n12287), .CK(clk), .SN(n11995), .Q(n12044) );
DFFSX1TS R_3129 ( .D(n12311), .CK(clk), .SN(n11995), .Q(n12041) );
DFFSX1TS R_3147 ( .D(n12271), .CK(clk), .SN(n1855), .Q(n12035) );
DFFSX1TS R_3220 ( .D(n12319), .CK(clk), .SN(n11995), .Q(n12027) );
DFFSX1TS R_3226 ( .D(n12331), .CK(clk), .SN(n11990), .Q(n12021) );
DFFSX1TS R_3232 ( .D(n12335), .CK(clk), .SN(n11999), .Q(n12015) );
DFFSX1TS R_3235 ( .D(n12371), .CK(clk), .SN(n10318), .Q(n12012) );
DFFSX1TS R_3238 ( .D(n12375), .CK(clk), .SN(n11998), .Q(n12009) );
DFFSX1TS R_3241 ( .D(n12368), .CK(clk), .SN(n1956), .Q(n12006) );
DFFSX2TS R_2880 ( .D(n12360), .CK(clk), .SN(n12238), .Q(n12106) );
DFFSX2TS R_2900 ( .D(n12296), .CK(clk), .SN(n1976), .Q(n12091) );
DFFSX2TS R_2903 ( .D(n12284), .CK(clk), .SN(n1975), .Q(n12088) );
DFFSX2TS R_2912 ( .D(n12316), .CK(clk), .SN(n1828), .Q(n12079) );
DFFSX2TS R_2915 ( .D(n12267), .CK(clk), .SN(n11696), .Q(n12076) );
DFFSX2TS R_2921 ( .D(n12351), .CK(clk), .SN(n11992), .Q(n12070) );
DFFSX2TS R_2929 ( .D(n12366), .CK(clk), .SN(n1867), .Q(n12064) );
DFFSX2TS R_2932 ( .D(n12357), .CK(clk), .SN(n11996), .Q(n12061) );
DFFSX2TS R_2935 ( .D(n12354), .CK(clk), .SN(n12001), .Q(n12058) );
DFFSX2TS R_3076 ( .D(n12363), .CK(clk), .SN(n11973), .Q(n12052) );
DFFSX2TS R_3125 ( .D(n12288), .CK(clk), .SN(n1828), .Q(n12045) );
DFFSX2TS R_3128 ( .D(n12312), .CK(clk), .SN(n1830), .Q(n12042) );
DFFSX2TS R_3146 ( .D(n12272), .CK(clk), .SN(n1956), .Q(n12036) );
DFFSX2TS R_3219 ( .D(n12320), .CK(clk), .SN(n1829), .Q(n12028) );
DFFSX2TS R_3222 ( .D(n12328), .CK(clk), .SN(n11990), .Q(n12025) );
DFFSX2TS R_3225 ( .D(n12332), .CK(clk), .SN(n11999), .Q(n12022) );
DFFSX2TS R_3231 ( .D(n12336), .CK(clk), .SN(n11989), .Q(n12016) );
DFFSX2TS R_3234 ( .D(n12372), .CK(clk), .SN(n1867), .Q(n12013) );
DFFSX2TS R_3237 ( .D(n12376), .CK(clk), .SN(n1828), .Q(n12010) );
DFFSX2TS R_3240 ( .D(n12369), .CK(clk), .SN(n1830), .Q(n12007) );
DFFSX1TS R_2882 ( .D(n12358), .CK(clk), .SN(n10318), .Q(n12104) );
DFFSX1TS R_2896 ( .D(n12302), .CK(clk), .SN(n12243), .Q(n12095) );
DFFSX1TS R_2905 ( .D(n12282), .CK(clk), .SN(n1855), .Q(n12086) );
DFFSX1TS R_2923 ( .D(n12349), .CK(clk), .SN(n11990), .Q(n12068) );
DFFSX1TS R_2931 ( .D(n12364), .CK(clk), .SN(n1855), .Q(n12062) );
DFFSX1TS R_2934 ( .D(n12355), .CK(clk), .SN(n1976), .Q(n12059) );
DFFSX1TS R_3078 ( .D(n12361), .CK(clk), .SN(n10318), .Q(n12050) );
DFFSX1TS R_3127 ( .D(n12286), .CK(clk), .SN(n1829), .Q(n12043) );
DFFSX1TS R_3148 ( .D(n12270), .CK(clk), .SN(n11989), .Q(n12034) );
DFFSX1TS R_3221 ( .D(n12318), .CK(clk), .SN(n1830), .Q(n12026) );
DFFSX1TS R_3233 ( .D(n12334), .CK(clk), .SN(n1855), .Q(n12014) );
DFFSX1TS R_3236 ( .D(n12370), .CK(clk), .SN(n11694), .Q(n12011) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n365), .CK(clk),
.RN(n2010), .Q(Sgf_normalized_result[12]), .QN(n11885) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n366), .CK(clk),
.RN(n2009), .Q(Sgf_normalized_result[13]), .QN(n11934) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n362), .CK(clk),
.RN(n11696), .Q(Sgf_normalized_result[9]), .QN(n11938) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n368), .CK(clk),
.RN(n10318), .Q(Sgf_normalized_result[15]), .QN(n11935) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n360), .CK(clk),
.RN(n11695), .Q(Sgf_normalized_result[7]), .QN(n11939) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n367), .CK(clk),
.RN(n1854), .Q(Sgf_normalized_result[14]), .QN(n11836) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n356), .CK(clk),
.RN(n12236), .Q(Sgf_normalized_result[3]), .QN(n11932) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n364), .CK(clk),
.RN(n11697), .Q(Sgf_normalized_result[11]), .QN(n11936) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n369), .CK(clk),
.RN(n1867), .Q(Sgf_normalized_result[16]), .QN(n11937) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n361), .CK(clk),
.RN(n11694), .Q(Sgf_normalized_result[8]), .QN(n11940) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n363), .CK(clk),
.RN(n2009), .Q(Sgf_normalized_result[10]), .QN(n11941) );
DFFSX1TS DP_OP_168J26_122_4811_R_2831 ( .D(DP_OP_168J26_122_4811_n662), .CK(
clk), .SN(n11977), .Q(n11624) );
DFFSX2TS DP_OP_168J26_122_4811_R_3024 ( .D(DP_OP_168J26_122_4811_n1456),
.CK(clk), .SN(n11723), .Q(n11661) );
DFFSX2TS DP_OP_168J26_122_4811_R_3025 ( .D(DP_OP_168J26_122_4811_n1487),
.CK(clk), .SN(n11722), .Q(n11662) );
DFFSX2TS DP_OP_168J26_122_4811_R_2693 ( .D(DP_OP_168J26_122_4811_n1221),
.CK(clk), .SN(n11455), .Q(n11596) );
DFFSX2TS DP_OP_168J26_122_4811_R_2817 ( .D(DP_OP_168J26_122_4811_n1388),
.CK(clk), .SN(n11721), .Q(n11614) );
DFFSX2TS DP_OP_168J26_122_4811_R_2818 ( .D(DP_OP_168J26_122_4811_n1421),
.CK(clk), .SN(n11721), .Q(n11615) );
DFFSX2TS DP_OP_168J26_122_4811_R_3015 ( .D(DP_OP_168J26_122_4811_n1005),
.CK(clk), .SN(n12221), .Q(n11660) );
DFFSX2TS DP_OP_168J26_122_4811_R_2952 ( .D(DP_OP_168J26_122_4811_n637), .CK(
clk), .SN(n11977), .Q(n11645) );
DFFRX2TS DP_OP_168J26_122_4811_R_2740 ( .D(DP_OP_168J26_122_4811_n614), .CK(
clk), .RN(n11723), .Q(n11603) );
DFFSX1TS DP_OP_168J26_122_4811_R_2713 ( .D(DP_OP_168J26_122_4811_n643), .CK(
clk), .SN(n11720), .Q(n11598) );
DFFSX1TS DP_OP_168J26_122_4811_R_3210 ( .D(n11686), .CK(clk), .SN(n1957),
.Q(DP_OP_168J26_122_4811_n8003) );
DFFRX4TS DP_OP_168J26_122_4811_R_3211 ( .D(n684), .CK(clk), .RN(n11713), .Q(
DP_OP_168J26_122_4811_n6782), .QN(n1872) );
DFFSX2TS DP_OP_168J26_122_4811_R_2577 ( .D(DP_OP_168J26_122_4811_n606), .CK(
clk), .SN(n9664), .Q(n11586) );
DFFRX4TS DP_OP_168J26_122_4811_R_3179 ( .D(n11685), .CK(clk), .RN(n11710),
.Q(DP_OP_168J26_122_4811_n8189) );
DFFSX4TS DP_OP_168J26_122_4811_R_3176 ( .D(n11684), .CK(clk), .SN(n11694),
.Q(DP_OP_168J26_122_4811_n3572) );
DFFRX4TS DP_OP_168J26_122_4811_R_3169 ( .D(n1446), .CK(clk), .RN(n11987),
.Q(DP_OP_168J26_122_4811_n8249), .QN(n11779) );
DFFRX4TS DP_OP_168J26_122_4811_R_3167 ( .D(n604), .CK(clk), .RN(n12000), .Q(
DP_OP_168J26_122_4811_n8493), .QN(n11772) );
DFFRX4TS DP_OP_168J26_122_4811_R_3161 ( .D(n11681), .CK(clk), .RN(n11713),
.Q(n11490), .QN(n3321) );
DFFSX4TS DP_OP_168J26_122_4811_R_3158 ( .D(n11680), .CK(clk), .SN(n11696),
.Q(DP_OP_168J26_122_4811_n3596), .QN(n1411) );
DFFRX4TS DP_OP_168J26_122_4811_R_3153 ( .D(n9733), .CK(clk), .RN(n11706),
.Q(DP_OP_168J26_122_4811_n6643), .QN(n11770) );
DFFSX1TS DP_OP_168J26_122_4811_R_3143 ( .D(n11678), .CK(clk), .SN(n11705),
.Q(DP_OP_168J26_122_4811_n7949) );
DFFRX4TS DP_OP_168J26_122_4811_R_3144 ( .D(n688), .CK(clk), .RN(n11708), .Q(
DP_OP_168J26_122_4811_n6794), .QN(n1391) );
DFFSX1TS DP_OP_168J26_122_4811_R_3138 ( .D(n11677), .CK(clk), .SN(n11713),
.Q(DP_OP_168J26_122_4811_n8030) );
DFFRX4TS DP_OP_168J26_122_4811_R_3069 ( .D(n11665), .CK(clk), .RN(n1891),
.Q(n11478), .QN(n3320) );
DFFRX4TS DP_OP_168J26_122_4811_R_3209 ( .D(n632), .CK(clk), .RN(n11704), .Q(
n11676), .QN(n904) );
DFFSX1TS DP_OP_168J26_122_4811_R_3123 ( .D(n11675), .CK(clk), .SN(n12395),
.Q(DP_OP_168J26_122_4811_n8034) );
DFFRX4TS DP_OP_168J26_122_4811_R_3137 ( .D(n9682), .CK(clk), .RN(n11713),
.Q(DP_OP_168J26_122_4811_n6776), .QN(n1659) );
DFFRX4TS DP_OP_168J26_122_4811_R_3120 ( .D(n671), .CK(clk), .RN(n12242), .Q(
DP_OP_168J26_122_4811_n5154), .QN(n11683) );
DFFRX4TS DP_OP_168J26_122_4811_R_3121 ( .D(n9682), .CK(clk), .RN(n12238),
.Q(DP_OP_168J26_122_4811_n8246), .QN(n11674) );
DFFRX4TS DP_OP_168J26_122_4811_R_3117 ( .D(n630), .CK(clk), .RN(n11702), .Q(
DP_OP_168J26_122_4811_n8166), .QN(n11687) );
DFFRX4TS DP_OP_168J26_122_4811_R_3118 ( .D(n630), .CK(clk), .RN(n11702), .Q(
DP_OP_168J26_122_4811_n8467) );
DFFRX4TS DP_OP_168J26_122_4811_R_3114 ( .D(n602), .CK(clk), .RN(n12000), .Q(
DP_OP_168J26_122_4811_n6559), .QN(n3319) );
DFFRX4TS DP_OP_168J26_122_4811_R_3115 ( .D(n602), .CK(clk), .RN(n12000), .Q(
n1343), .QN(n11771) );
DFFRX4TS DP_OP_168J26_122_4811_R_3112 ( .D(n11673), .CK(clk), .RN(n11704),
.Q(DP_OP_168J26_122_4811_n3238) );
DFFSX1TS DP_OP_168J26_122_4811_R_3107 ( .D(n11553), .CK(clk), .SN(n11698),
.Q(DP_OP_168J26_122_4811_n3520) );
DFFSX4TS DP_OP_168J26_122_4811_R_3106 ( .D(n11551), .CK(clk), .SN(n11698),
.Q(DP_OP_168J26_122_4811_n3519), .QN(n11748) );
DFFRX4TS DP_OP_168J26_122_4811_R_3096 ( .D(n601), .CK(clk), .RN(n12000), .Q(
DP_OP_168J26_122_4811_n8490) );
DFFSX4TS DP_OP_168J26_122_4811_R_3093 ( .D(n11671), .CK(clk), .SN(n11705),
.Q(DP_OP_168J26_122_4811_n8218), .QN(n1398) );
DFFSX4TS DP_OP_168J26_122_4811_R_3090 ( .D(n11670), .CK(clk), .SN(n11695),
.QN(n11749) );
DFFRX2TS DP_OP_168J26_122_4811_R_3085 ( .D(n11668), .CK(clk), .RN(n11707),
.Q(DP_OP_168J26_122_4811_n6587) );
DFFSX2TS DP_OP_168J26_122_4811_R_3082 ( .D(n11667), .CK(clk), .SN(n11704),
.Q(DP_OP_168J26_122_4811_n3224) );
DFFSX4TS DP_OP_168J26_122_4811_R_3072 ( .D(n11666), .CK(clk), .SN(n1891),
.Q(DP_OP_168J26_122_4811_n6609), .QN(n1922) );
DFFSX1TS DP_OP_168J26_122_4811_R_2984 ( .D(DP_OP_168J26_122_4811_n200), .CK(
clk), .SN(n2004), .Q(n11773), .QN(n11729) );
DFFSX1TS DP_OP_168J26_122_4811_R_2977 ( .D(DP_OP_168J26_122_4811_n553), .CK(
clk), .SN(n11725), .Q(n11650) );
DFFRXLTS DP_OP_168J26_122_4811_R_2948 ( .D(DP_OP_168J26_122_4811_n318), .CK(
clk), .RN(n11718), .Q(n11643) );
DFFSX1TS DP_OP_168J26_122_4811_R_2867 ( .D(DP_OP_168J26_122_4811_n203), .CK(
clk), .SN(n11455), .Q(n11635) );
DFFRXLTS DP_OP_168J26_122_4811_R_2839 ( .D(n11626), .CK(clk), .RN(n11972),
.Q(DP_OP_168J26_122_4811_n5214), .QN(n11752) );
DFFSX4TS DP_OP_168J26_122_4811_R_2840 ( .D(n11627), .CK(clk), .SN(n11709),
.Q(DP_OP_168J26_122_4811_n6172), .QN(n1661) );
DFFSX4TS DP_OP_168J26_122_4811_R_2841 ( .D(n11628), .CK(clk), .SN(n11996),
.Q(DP_OP_168J26_122_4811_n6171), .QN(n1623) );
DFFSX4TS DP_OP_168J26_122_4811_R_2842 ( .D(n1432), .CK(clk), .SN(n11709),
.Q(DP_OP_168J26_122_4811_n5160) );
DFFSX2TS DP_OP_168J26_122_4811_R_2821 ( .D(DP_OP_168J26_122_4811_n1029),
.CK(clk), .SN(n2004), .Q(n11616) );
DFFSX1TS DP_OP_168J26_122_4811_R_2819 ( .D(DP_OP_168J26_122_4811_n374), .CK(
clk), .SN(n11717), .QN(n11774) );
DFFRX4TS DP_OP_168J26_122_4811_R_2837 ( .D(n599), .CK(clk), .RN(n11700), .Q(
DP_OP_168J26_122_4811_n6562), .QN(n1637) );
DFFSX1TS DP_OP_168J26_122_4811_R_2389_RW_0 ( .D(n9985), .CK(clk), .SN(n11719), .Q(n11572) );
DFFRX2TS DP_OP_168J26_122_4811_R_2790 ( .D(DP_OP_168J26_122_4811_n1221),
.CK(clk), .RN(n2008), .Q(n11607) );
DFFSX2TS DP_OP_168J26_122_4811_R_2696 ( .D(DP_OP_168J26_122_4811_n348), .CK(
clk), .SN(n2008), .Q(n11597) );
DFFSX1TS DP_OP_168J26_122_4811_R_2662 ( .D(DP_OP_168J26_122_4811_n579), .CK(
clk), .SN(n11455), .Q(n11592) );
DFFRX4TS DP_OP_168J26_122_4811_R_2623 ( .D(n11590), .CK(clk), .RN(n11710),
.QN(n11784) );
DFFRXLTS DP_OP_168J26_122_4811_R_2493_RW_0 ( .D(DP_OP_168J26_122_4811_n303),
.CK(clk), .RN(n11719), .Q(n11578) );
DFFSX4TS DP_OP_168J26_122_4811_R_2835 ( .D(n11575), .CK(clk), .SN(n11709),
.Q(DP_OP_168J26_122_4811_n5162) );
DFFSX4TS DP_OP_168J26_122_4811_R_2580 ( .D(n11575), .CK(clk), .SN(n11709),
.Q(DP_OP_168J26_122_4811_n6594), .QN(n1856) );
DFFRX1TS DP_OP_168J26_122_4811_R_2578 ( .D(n1528), .CK(clk), .RN(n11723),
.Q(n11587) );
DFFSX4TS DP_OP_168J26_122_4811_R_2575 ( .D(n11585), .CK(clk), .SN(n11705),
.Q(DP_OP_168J26_122_4811_n6613), .QN(n2047) );
DFFRX4TS DP_OP_168J26_122_4811_R_2836 ( .D(n598), .CK(clk), .RN(n11995), .Q(
DP_OP_168J26_122_4811_n6563), .QN(n854) );
DFFRX4TS DP_OP_168J26_122_4811_R_2572 ( .D(n598), .CK(clk), .RN(n12232), .Q(
DP_OP_168J26_122_4811_n8487), .QN(n895) );
DFFRX4TS DP_OP_168J26_122_4811_R_2564 ( .D(n600), .CK(clk), .RN(n11703), .Q(
DP_OP_168J26_122_4811_n8489) );
DFFRX4TS DP_OP_168J26_122_4811_R_2479 ( .D(n633), .CK(clk), .RN(n11703),
.QN(n3317) );
DFFRX1TS DP_OP_168J26_122_4811_R_2423 ( .D(n628), .CK(clk), .RN(n11702), .Q(
DP_OP_168J26_122_4811_n7818) );
DFFRX4TS DP_OP_168J26_122_4811_R_2421 ( .D(n628), .CK(clk), .RN(n11703), .Q(
DP_OP_168J26_122_4811_n8465) );
DFFSX4TS DP_OP_168J26_122_4811_R_2838 ( .D(n1432), .CK(clk), .SN(n11709),
.Q(DP_OP_168J26_122_4811_n6608), .QN(n2012) );
DFFSX1TS DP_OP_168J26_122_4811_R_2405 ( .D(DP_OP_168J26_122_4811_n129), .CK(
clk), .SN(n11716), .Q(n11574) );
DFFRX1TS DP_OP_168J26_122_4811_R_2386 ( .D(DP_OP_168J26_122_4811_n131), .CK(
clk), .RN(n11977), .Q(n11571) );
DFFRX1TS DP_OP_168J26_122_4811_R_2330 ( .D(DP_OP_168J26_122_4811_n130), .CK(
clk), .RN(n11724), .Q(n11570) );
DFFRX4TS DP_OP_168J26_122_4811_R_2269 ( .D(n11567), .CK(clk), .RN(n11699),
.Q(n11555), .QN(n11756) );
DFFSX4TS DP_OP_168J26_122_4811_R_2259 ( .D(n11566), .CK(clk), .SN(n11699),
.Q(DP_OP_168J26_122_4811_n3508), .QN(n11732) );
DFFSX1TS DP_OP_168J26_122_4811_R_2254 ( .D(n11552), .CK(clk), .SN(n11699),
.Q(DP_OP_168J26_122_4811_n3553) );
DFFSX4TS DP_OP_168J26_122_4811_R_2253 ( .D(n11491), .CK(clk), .SN(n11699),
.Q(DP_OP_168J26_122_4811_n3541), .QN(n11733) );
DFFSX1TS DP_OP_168J26_122_4811_R_2256 ( .D(n11565), .CK(clk), .SN(n11699),
.Q(DP_OP_168J26_122_4811_n3542) );
DFFRX4TS DP_OP_168J26_122_4811_R_2245 ( .D(n11563), .CK(clk), .RN(n11710),
.Q(n11505), .QN(n1364) );
DFFRX4TS DP_OP_168J26_122_4811_R_2234 ( .D(n590), .CK(clk), .RN(n11700), .Q(
DP_OP_168J26_122_4811_n8479), .QN(n11782) );
DFFSX4TS DP_OP_168J26_122_4811_R_2235 ( .D(n11561), .CK(clk), .SN(n11698),
.Q(DP_OP_168J26_122_4811_n3552), .QN(n11746) );
DFFSX4TS DP_OP_168J26_122_4811_R_2231 ( .D(n11560), .CK(clk), .SN(n11699),
.Q(DP_OP_168J26_122_4811_n3486), .QN(n11744) );
DFFRX4TS DP_OP_168J26_122_4811_R_2232 ( .D(n623), .CK(clk), .RN(n11701), .Q(
DP_OP_168J26_122_4811_n8460), .QN(n11737) );
DFFRX4TS DP_OP_168J26_122_4811_R_2225 ( .D(n595), .CK(clk), .RN(n11699), .Q(
DP_OP_168J26_122_4811_n8484), .QN(n11765) );
DFFRX4TS DP_OP_168J26_122_4811_R_2224 ( .D(n622), .CK(clk), .RN(n11700), .Q(
DP_OP_168J26_122_4811_n8459), .QN(n1912) );
DFFSX4TS DP_OP_168J26_122_4811_R_2210 ( .D(n11557), .CK(clk), .SN(n11699),
.Q(DP_OP_168J26_122_4811_n3475), .QN(n11731) );
DFFRX4TS DP_OP_168J26_122_4811_R_2211 ( .D(n624), .CK(clk), .RN(n11701), .Q(
DP_OP_168J26_122_4811_n8461), .QN(n1714) );
DFFRX4TS DP_OP_168J26_122_4811_R_2212 ( .D(n597), .CK(clk), .RN(n11701), .Q(
DP_OP_168J26_122_4811_n8486), .QN(n11781) );
DFFRX4TS DP_OP_168J26_122_4811_R_2213 ( .D(n627), .CK(clk), .RN(n11703), .Q(
DP_OP_168J26_122_4811_n8464) );
DFFRXLTS DP_OP_168J26_122_4811_R_2165 ( .D(DP_OP_168J26_122_4811_n525), .CK(
clk), .RN(n11723), .Q(n11556) );
DFFRX4TS DP_OP_168J26_122_4811_R_2140 ( .D(n690), .CK(clk), .RN(n11710), .Q(
DP_OP_168J26_122_4811_n8242), .QN(n11688) );
DFFRX2TS DP_OP_168J26_122_4811_R_2267 ( .D(n626), .CK(clk), .RN(n11701), .Q(
DP_OP_168J26_122_4811_n8463) );
DFFRX4TS DP_OP_168J26_122_4811_R_1981 ( .D(n593), .CK(clk), .RN(n11699), .Q(
DP_OP_168J26_122_4811_n8482), .QN(n11764) );
DFFSX4TS DP_OP_168J26_122_4811_R_1956 ( .D(n11550), .CK(clk), .SN(n11698),
.Q(DP_OP_168J26_122_4811_n3497), .QN(n11743) );
DFFSX1TS DP_OP_168J26_122_4811_R_1758 ( .D(DP_OP_168J26_122_4811_n102), .CK(
clk), .SN(n2004), .Q(n11547) );
DFFSX1TS DP_OP_168J26_122_4811_R_1755 ( .D(DP_OP_168J26_122_4811_n103), .CK(
clk), .SN(n11716), .Q(n11546) );
DFFSX1TS DP_OP_168J26_122_4811_R_1670 ( .D(DP_OP_168J26_122_4811_n104), .CK(
clk), .SN(n2008), .Q(n11538) );
DFFSX1TS DP_OP_168J26_122_4811_R_1623 ( .D(DP_OP_168J26_122_4811_n106), .CK(
clk), .SN(n11717), .Q(n11537) );
DFFSX1TS DP_OP_168J26_122_4811_R_1605 ( .D(DP_OP_168J26_122_4811_n100), .CK(
clk), .SN(n11981), .Q(n11535) );
DFFSX4TS DP_OP_168J26_122_4811_R_1544 ( .D(n11534), .CK(clk), .SN(n1891),
.Q(DP_OP_168J26_122_4811_n3560), .QN(n11745) );
DFFRX4TS DP_OP_168J26_122_4811_R_1545 ( .D(n589), .CK(clk), .RN(n11998), .Q(
DP_OP_168J26_122_4811_n8478), .QN(n11768) );
DFFRX4TS DP_OP_168J26_122_4811_R_1493 ( .D(n672), .CK(clk), .RN(n11710), .Q(
n3322), .QN(n11766) );
DFFRX2TS DP_OP_168J26_122_4811_R_1308 ( .D(n11530), .CK(clk), .RN(n12228),
.Q(n11502) );
DFFRX4TS DP_OP_168J26_122_4811_R_1309 ( .D(n646), .CK(clk), .RN(n10321), .Q(
DP_OP_168J26_122_4811_n8525), .QN(n11758) );
DFFSX4TS DP_OP_168J26_122_4811_R_1283 ( .D(n11529), .CK(clk), .SN(n11705),
.Q(DP_OP_168J26_122_4811_n6614), .QN(n1413) );
DFFRX4TS DP_OP_168J26_122_4811_R_3208 ( .D(n684), .CK(clk), .RN(n11713), .Q(
DP_OP_168J26_122_4811_n8245), .QN(n11526) );
DFFRX4TS DP_OP_168J26_122_4811_R_1279 ( .D(n619), .CK(clk), .RN(n11701), .Q(
DP_OP_168J26_122_4811_n8177), .QN(n3308) );
DFFRX4TS DP_OP_168J26_122_4811_R_3104 ( .D(n619), .CK(clk), .RN(n11701), .Q(
DP_OP_168J26_122_4811_n8456) );
DFFRX2TS DP_OP_168J26_122_4811_R_1275 ( .D(n11524), .CK(clk), .RN(n11710),
.Q(DP_OP_168J26_122_4811_n6584) );
DFFSX4TS DP_OP_168J26_122_4811_R_1272 ( .D(n11523), .CK(clk), .SN(n11695),
.Q(DP_OP_168J26_122_4811_n3602), .QN(n11739) );
DFFRX4TS DP_OP_168J26_122_4811_R_1269 ( .D(n653), .CK(clk), .RN(n11708), .Q(
DP_OP_168J26_122_4811_n6644), .QN(n11581) );
DFFSX1TS DP_OP_168J26_122_4811_R_1263 ( .D(n11510), .CK(clk), .SN(n11697),
.Q(DP_OP_168J26_122_4811_n3581) );
DFFRX4TS DP_OP_168J26_122_4811_R_1273 ( .D(n664), .CK(clk), .RN(n11710), .Q(
DP_OP_168J26_122_4811_n8543), .QN(n953) );
DFFRX4TS DP_OP_168J26_122_4811_R_949 ( .D(n11519), .CK(clk), .RN(n11710),
.QN(n11753) );
DFFRX4TS DP_OP_168J26_122_4811_R_946 ( .D(n11518), .CK(clk), .RN(n11713),
.Q(n11487), .QN(n11754) );
DFFRX4TS DP_OP_168J26_122_4811_R_941 ( .D(n11517), .CK(clk), .RN(n12234),
.Q(n11486), .QN(n11757) );
DFFRX4TS DP_OP_168J26_122_4811_R_938 ( .D(n11515), .CK(clk), .RN(n11706),
.Q(DP_OP_168J26_122_4811_n3232) );
DFFRX2TS DP_OP_168J26_122_4811_R_927 ( .D(n11512), .CK(clk), .RN(n1976), .Q(
DP_OP_168J26_122_4811_n8194) );
DFFRX4TS DP_OP_168J26_122_4811_R_921 ( .D(n11511), .CK(clk), .RN(n11711),
.Q(DP_OP_168J26_122_4811_n8196) );
DFFRX4TS DP_OP_168J26_122_4811_R_3067 ( .D(n681), .CK(clk), .RN(n11711), .Q(
DP_OP_168J26_122_4811_n8506), .QN(n11735) );
DFFRX4TS DP_OP_168J26_122_4811_R_916 ( .D(n614), .CK(clk), .RN(n11694), .Q(
DP_OP_168J26_122_4811_n8451), .QN(n1849) );
DFFRX4TS DP_OP_168J26_122_4811_R_912 ( .D(n11508), .CK(clk), .RN(n11712),
.Q(DP_OP_168J26_122_4811_n8191) );
DFFRX4TS DP_OP_168J26_122_4811_R_3159 ( .D(n691), .CK(clk), .RN(n11712), .Q(
DP_OP_168J26_122_4811_n8516) );
DFFRX4TS DP_OP_168J26_122_4811_R_909 ( .D(n11507), .CK(clk), .RN(n11996),
.Q(n11475), .QN(n3307) );
DFFRX4TS DP_OP_168J26_122_4811_R_899 ( .D(n609), .CK(clk), .RN(n11695), .Q(
DP_OP_168J26_122_4811_n8187), .QN(n1405) );
DFFRX4TS DP_OP_168J26_122_4811_R_898 ( .D(n609), .CK(clk), .RN(n11696), .Q(
DP_OP_168J26_122_4811_n8446) );
DFFSX4TS DP_OP_168J26_122_4811_R_891 ( .D(n11504), .CK(clk), .SN(n2009), .Q(
DP_OP_168J26_122_4811_n3571), .QN(n11747) );
DFFRX4TS DP_OP_168J26_122_4811_R_3175 ( .D(n588), .CK(clk), .RN(n2009), .Q(
DP_OP_168J26_122_4811_n8477), .QN(n11785) );
DFFRX4TS DP_OP_168J26_122_4811_R_887 ( .D(n592), .CK(clk), .RN(n1891), .Q(
DP_OP_168J26_122_4811_n6569), .QN(n3312) );
DFFRX4TS DP_OP_168J26_122_4811_R_3105 ( .D(n592), .CK(clk), .RN(n1891), .Q(
DP_OP_168J26_122_4811_n8481) );
DFFRX4TS DP_OP_168J26_122_4811_R_885 ( .D(n582), .CK(clk), .RN(n2010), .Q(
DP_OP_168J26_122_4811_n6579), .QN(n11509) );
DFFRX4TS DP_OP_168J26_122_4811_R_884 ( .D(n582), .CK(clk), .RN(n11697), .Q(
DP_OP_168J26_122_4811_n8471) );
DFFRX4TS DP_OP_168J26_122_4811_R_914 ( .D(n12137), .CK(clk), .RN(n11708),
.Q(DP_OP_168J26_122_4811_n6641), .QN(n11740) );
DFFRX4TS DP_OP_168J26_122_4811_R_3084 ( .D(n12137), .CK(clk), .RN(n11707),
.Q(DP_OP_168J26_122_4811_n8538), .QN(n1415) );
DFFRX4TS DP_OP_168J26_122_4811_R_875 ( .D(n11503), .CK(clk), .RN(n971), .QN(
n11755) );
DFFRX4TS DP_OP_168J26_122_4811_R_869 ( .D(n11501), .CK(clk), .RN(n11712),
.Q(DP_OP_168J26_122_4811_n8193) );
DFFRX4TS DP_OP_168J26_122_4811_R_2246 ( .D(n591), .CK(clk), .RN(n11701), .Q(
DP_OP_168J26_122_4811_n8480), .QN(n11767) );
DFFSX2TS DP_OP_168J26_122_4811_R_860 ( .D(n11498), .CK(clk), .SN(n11706),
.Q(DP_OP_168J26_122_4811_n3223) );
DFFSX4TS DP_OP_168J26_122_4811_R_851 ( .D(n11497), .CK(clk), .SN(n11998),
.Q(DP_OP_168J26_122_4811_n6611), .QN(n1649) );
DFFRX4TS DP_OP_168J26_122_4811_R_852 ( .D(n666), .CK(clk), .RN(n972), .Q(
DP_OP_168J26_122_4811_n8545), .QN(n858) );
DFFRX4TS DP_OP_168J26_122_4811_R_3073 ( .D(n665), .CK(clk), .RN(n11990), .Q(
DP_OP_168J26_122_4811_n8544), .QN(n11583) );
DFFRX4TS DP_OP_168J26_122_4811_R_847 ( .D(n11496), .CK(clk), .RN(n971), .Q(
DP_OP_168J26_122_4811_n3229) );
DFFRX4TS DP_OP_168J26_122_4811_R_3177 ( .D(n695), .CK(clk), .RN(n11989), .Q(
DP_OP_168J26_122_4811_n8520), .QN(n11562) );
DFFSX4TS DP_OP_168J26_122_4811_R_842 ( .D(n11495), .CK(clk), .SN(n11704),
.Q(DP_OP_168J26_122_4811_n6620), .QN(n1346) );
DFFRX4TS DP_OP_168J26_122_4811_R_843 ( .D(n648), .CK(clk), .RN(n10321), .Q(
DP_OP_168J26_122_4811_n8527), .QN(n1632) );
DFFRX4TS DP_OP_168J26_122_4811_R_837 ( .D(n11494), .CK(clk), .RN(n11711),
.Q(DP_OP_168J26_122_4811_n8199) );
DFFRX4TS DP_OP_168J26_122_4811_R_944 ( .D(n675), .CK(clk), .RN(n11711), .Q(
DP_OP_168J26_122_4811_n8500) );
DFFSX4TS DP_OP_168J26_122_4811_R_830 ( .D(n11476), .CK(clk), .SN(n11696),
.Q(DP_OP_168J26_122_4811_n3609) );
DFFSX4TS DP_OP_168J26_122_4811_R_834 ( .D(n11493), .CK(clk), .SN(n11694),
.Q(DP_OP_168J26_122_4811_n3607) );
DFFRX4TS DP_OP_168J26_122_4811_R_833 ( .D(n11492), .CK(clk), .RN(n2010), .Q(
DP_OP_168J26_122_4811_n3605), .QN(n11741) );
DFFRX4TS DP_OP_168J26_122_4811_R_926 ( .D(n686), .CK(clk), .RN(n11712), .Q(
DP_OP_168J26_122_4811_n8511) );
DFFRX4TS DP_OP_168J26_122_4811_R_818 ( .D(n674), .CK(clk), .RN(n11711), .Q(
DP_OP_168J26_122_4811_n8250), .QN(n11528) );
DFFRX4TS DP_OP_168J26_122_4811_R_1251 ( .D(n674), .CK(clk), .RN(n11711), .Q(
DP_OP_168J26_122_4811_n8499) );
DFFSX4TS DP_OP_168J26_122_4811_R_809 ( .D(n11489), .CK(clk), .SN(n11709),
.Q(DP_OP_168J26_122_4811_n3215) );
DFFRX4TS DP_OP_168J26_122_4811_R_3178 ( .D(n696), .CK(clk), .RN(n11973), .Q(
n1634), .QN(n11500) );
DFFSX4TS DP_OP_168J26_122_4811_R_804 ( .D(n11488), .CK(clk), .SN(n11704),
.Q(DP_OP_168J26_122_4811_n3212) );
DFFRX4TS DP_OP_168J26_122_4811_R_3168 ( .D(n1446), .CK(clk), .RN(n12228),
.Q(DP_OP_168J26_122_4811_n8501), .QN(n11527) );
DFFRX4TS DP_OP_168J26_122_4811_R_1543 ( .D(n616), .CK(clk), .RN(n12235), .Q(
DP_OP_168J26_122_4811_n8453) );
DFFRX2TS DP_OP_168J26_122_4811_R_791 ( .D(n11484), .CK(clk), .RN(n12242),
.Q(DP_OP_168J26_122_4811_n3228) );
DFFSX2TS DP_OP_168J26_122_4811_R_784 ( .D(n11483), .CK(clk), .SN(n11706),
.Q(DP_OP_168J26_122_4811_n3245) );
DFFSX4TS DP_OP_168J26_122_4811_R_777 ( .D(n11482), .CK(clk), .SN(n11706),
.Q(DP_OP_168J26_122_4811_n6615), .QN(n1879) );
DFFRX4TS DP_OP_168J26_122_4811_R_3083 ( .D(n658), .CK(clk), .RN(n11707), .Q(
DP_OP_168J26_122_4811_n8537) );
DFFSX4TS DP_OP_168J26_122_4811_R_772 ( .D(n11481), .CK(clk), .SN(n11706),
.Q(DP_OP_168J26_122_4811_n6616), .QN(n1421) );
DFFRX4TS DP_OP_168J26_122_4811_R_933 ( .D(n656), .CK(clk), .RN(n11707), .Q(
DP_OP_168J26_122_4811_n8535) );
DFFRX4TS DP_OP_168J26_122_4811_R_3152 ( .D(n9733), .CK(clk), .RN(n11707),
.Q(DP_OP_168J26_122_4811_n8534), .QN(n11584) );
DFFSX4TS DP_OP_168J26_122_4811_R_768 ( .D(n11480), .CK(clk), .SN(n1957), .Q(
DP_OP_168J26_122_4811_n8216) );
DFFRX4TS DP_OP_168J26_122_4811_R_903 ( .D(n693), .CK(clk), .RN(n1956), .Q(
DP_OP_168J26_122_4811_n8518) );
DFFRX4TS DP_OP_168J26_122_4811_R_3172 ( .D(n1441), .CK(clk), .RN(n1956), .Q(
DP_OP_168J26_122_4811_n8517), .QN(n11485) );
DFFRX4TS DP_OP_168J26_122_4811_R_3141 ( .D(n688), .CK(clk), .RN(n11707), .Q(
DP_OP_168J26_122_4811_n8513), .QN(n11525) );
DFFRX4TS DP_OP_168J26_122_4811_R_3162 ( .D(n660), .CK(clk), .RN(n11708), .Q(
DP_OP_168J26_122_4811_n8539) );
DFFSX4TS DP_OP_168J26_122_4811_R_736 ( .D(n11473), .CK(clk), .SN(n11697),
.Q(DP_OP_168J26_122_4811_n3603) );
DFFRX4TS DP_OP_168J26_122_4811_R_1270 ( .D(n611), .CK(clk), .RN(n11696), .Q(
DP_OP_168J26_122_4811_n8448), .QN(n1930) );
DFFRX4TS DP_OP_168J26_122_4811_R_1271 ( .D(n584), .CK(clk), .RN(n12235), .Q(
DP_OP_168J26_122_4811_n8473), .QN(n11769) );
DFFSX4TS DP_OP_168J26_122_4811_R_731 ( .D(n11472), .CK(clk), .SN(n11706),
.Q(DP_OP_168J26_122_4811_n6617), .QN(n1942) );
DFFRX4TS DP_OP_168J26_122_4811_R_1813 ( .D(n654), .CK(clk), .RN(n11708), .Q(
DP_OP_168J26_122_4811_n8533), .QN(n11477) );
DFFSX4TS DP_OP_168J26_122_4811_R_720 ( .D(n11471), .CK(clk), .SN(n2009), .Q(
DP_OP_168J26_122_4811_n3595), .QN(n11738) );
DFFRX4TS DP_OP_168J26_122_4811_R_3156 ( .D(n11806), .CK(clk), .RN(n11695),
.Q(DP_OP_168J26_122_4811_n8449), .QN(n1875) );
DFFRX4TS DP_OP_168J26_122_4811_R_3157 ( .D(n585), .CK(clk), .RN(n11694), .Q(
DP_OP_168J26_122_4811_n8474), .QN(n11736) );
DFFRX4TS DP_OP_168J26_122_4811_R_714 ( .D(n11470), .CK(clk), .RN(n11711),
.Q(DP_OP_168J26_122_4811_n8198) );
DFFRX4TS DP_OP_168J26_122_4811_R_3111 ( .D(n677), .CK(clk), .RN(n11711), .Q(
DP_OP_168J26_122_4811_n8502), .QN(n11516) );
DFFSX4TS DP_OP_168J26_122_4811_R_829 ( .D(n11469), .CK(clk), .SN(n2010),
.QN(n3310) );
DFFRX4TS DP_OP_168J26_122_4811_R_832 ( .D(n583), .CK(clk), .RN(n11696), .Q(
DP_OP_168J26_122_4811_n8472), .QN(n11783) );
DFFSX4TS DP_OP_168J26_122_4811_R_557 ( .D(n11468), .CK(clk), .SN(n12238),
.Q(DP_OP_168J26_122_4811_n8223), .QN(n1947) );
DFFRX4TS DP_OP_168J26_122_4811_R_1539 ( .D(n679), .CK(clk), .RN(n11711), .Q(
DP_OP_168J26_122_4811_n8504) );
DFFRX4TS DP_OP_168J26_122_4811_R_3081 ( .D(n1355), .CK(clk), .RN(n11711),
.Q(DP_OP_168J26_122_4811_n8503) );
DFFSX4TS DP_OP_168J26_122_4811_R_552 ( .D(n11467), .CK(clk), .SN(n11713),
.Q(DP_OP_168J26_122_4811_n8221), .QN(n1349) );
DFFRX4TS DP_OP_168J26_122_4811_R_3102 ( .D(n9682), .CK(clk), .RN(n11712),
.Q(DP_OP_168J26_122_4811_n8507), .QN(n11499) );
DFFSX4TS DP_OP_168J26_122_4811_R_548 ( .D(n11466), .CK(clk), .SN(n11704),
.Q(DP_OP_168J26_122_4811_n6618), .QN(n1406) );
DFFSX4TS DP_OP_168J26_122_4811_R_542 ( .D(n11465), .CK(clk), .SN(n11709),
.Q(DP_OP_168J26_122_4811_n6610), .QN(n1420) );
DFFSX4TS DP_OP_168J26_122_4811_R_538 ( .D(n11464), .CK(clk), .SN(n11704),
.Q(DP_OP_168J26_122_4811_n6619), .QN(n1389) );
DFFRX4TS DP_OP_168J26_122_4811_R_3110 ( .D(n650), .CK(clk), .RN(n12395), .Q(
DP_OP_168J26_122_4811_n8529), .QN(n1737) );
DFFSX4TS DP_OP_168J26_122_4811_R_531 ( .D(n11463), .CK(clk), .SN(n2006), .Q(
DP_OP_168J26_122_4811_n8220), .QN(n1395) );
DFFRX4TS DP_OP_168J26_122_4811_R_925 ( .D(n685), .CK(clk), .RN(n10318), .Q(
DP_OP_168J26_122_4811_n8510) );
DFFSX2TS add_x_19_R_2993 ( .D(Sgf_operation_ODD1_S_B[10]), .CK(clk), .SN(
n12222), .Q(n11432) );
DFFSX2TS add_x_19_R_2938 ( .D(Sgf_operation_ODD1_Q_right[33]), .CK(clk),
.SN(n11453), .Q(n11421) );
DFFSX2TS add_x_19_R_2994 ( .D(Sgf_operation_ODD1_Q_right[37]), .CK(clk),
.SN(n9663), .Q(n11433) );
DFFSX2TS add_x_19_R_2974 ( .D(Sgf_operation_ODD1_S_B[9]), .CK(clk), .SN(
n9663), .Q(n11429) );
DFFSX2TS add_x_19_R_3027 ( .D(Sgf_operation_ODD1_S_B[11]), .CK(clk), .SN(
n11719), .Q(n11442) );
DFFRX2TS add_x_19_R_3028 ( .D(Sgf_operation_ODD1_Q_right[38]), .CK(clk),
.RN(n10320), .Q(n11443) );
DFFSX2TS add_x_19_R_2959 ( .D(Sgf_operation_ODD1_Q_left[36]), .CK(clk), .SN(
n11447), .Q(n11427) );
DFFSX2TS add_x_19_R_2958 ( .D(Sgf_operation_ODD1_Q_left[35]), .CK(clk), .SN(
n11447), .Q(n11426) );
DFFSX2TS add_x_19_R_2956 ( .D(Sgf_operation_ODD1_Q_left[39]), .CK(clk), .SN(
n11447), .Q(n11424) );
DFFSX2TS add_x_19_R_2973 ( .D(Sgf_operation_ODD1_Q_right[36]), .CK(clk),
.SN(n9663), .Q(n11428) );
DFFSX2TS add_x_19_R_2969_RW_0 ( .D(add_x_19_n705), .CK(clk), .SN(n11978),
.QN(n11458) );
DFFSX1TS add_x_19_R_2776 ( .D(add_x_19_n763), .CK(clk), .SN(n11982), .Q(
n11415) );
DFFRX1TS add_x_19_R_2765_RW_0 ( .D(add_x_19_n718), .CK(clk), .RN(n10320),
.Q(n11412) );
DFFSX2TS add_x_19_R_3021 ( .D(Sgf_operation_ODD1_Q_left[34]), .CK(clk), .SN(
n11446), .Q(n11441) );
DFFSX2TS add_x_19_R_3020 ( .D(Sgf_operation_ODD1_Q_left[33]), .CK(clk), .SN(
n11446), .Q(n11440) );
DFFSX2TS add_x_19_R_2992 ( .D(Sgf_operation_ODD1_Q_left[44]), .CK(clk), .SN(
n11447), .Q(n11431) );
DFFSX2TS add_x_19_R_2991 ( .D(Sgf_operation_ODD1_Q_left[43]), .CK(clk), .SN(
n1012), .Q(n11430) );
DFFSX2TS add_x_19_R_2957 ( .D(Sgf_operation_ODD1_Q_left[40]), .CK(clk), .SN(
n11447), .Q(n11425) );
DFFSX2TS add_x_19_R_2757 ( .D(add_x_19_n748), .CK(clk), .SN(n11982), .Q(
n11410) );
DFFRX1TS add_x_19_R_2720 ( .D(Sgf_operation_ODD1_Q_right[41]), .CK(clk),
.RN(n10320), .Q(n11409) );
DFFSX1TS add_x_19_R_2628_RW_0 ( .D(Sgf_operation_ODD1_Q_right[42]), .CK(clk),
.SN(n11451), .Q(n11408) );
DFFRX1TS add_x_19_R_2604 ( .D(add_x_19_n755), .CK(clk), .RN(n11454), .Q(
n11407) );
DFFRX1TS add_x_19_R_2507 ( .D(Sgf_operation_ODD1_Q_right[44]), .CK(clk),
.RN(n11445), .Q(n11400) );
DFFSX1TS add_x_19_R_2220_RW_0 ( .D(Sgf_operation_ODD1_Q_right[47]), .CK(clk),
.SN(n10319), .Q(n11390) );
DFFSX1TS add_x_19_R_2320 ( .D(Sgf_operation_ODD1_Q_right[49]), .CK(clk),
.SN(n11981), .Q(n11394) );
DFFSX1TS add_x_19_R_2237_RW_0 ( .D(Sgf_operation_ODD1_Q_right[50]), .CK(clk),
.SN(n11981), .Q(n11391) );
DFFRXLTS add_x_19_R_2307 ( .D(Sgf_operation_ODD1_Q_right[47]), .CK(clk),
.RN(n11453), .Q(n11393) );
DFFSX1TS add_x_19_R_2145 ( .D(add_x_19_n120), .CK(clk), .SN(n11447), .Q(
n11386) );
DFFSX1TS add_x_19_R_1879_RW_0 ( .D(Sgf_operation_ODD1_Q_left[2]), .CK(clk),
.SN(n11725), .Q(n11380) );
DFFRXLTS add_x_19_R_1987 ( .D(Sgf_operation_ODD1_Q_left[2]), .CK(clk), .RN(
n12221), .Q(n11384) );
DFFSX1TS add_x_19_R_1890_RW_0 ( .D(Sgf_operation_ODD1_Q_left[1]), .CK(clk),
.SN(n11452), .Q(n11381) );
DFFRXLTS add_x_19_R_1951 ( .D(Sgf_operation_ODD1_Q_left[1]), .CK(clk), .RN(
n10319), .Q(n11382) );
DFFRXLTS add_x_19_R_1547_RW_0 ( .D(Sgf_operation_ODD1_Q_left[11]), .CK(clk),
.RN(n11985), .QN(n11457) );
DFFSX1TS add_x_19_R_1388 ( .D(Sgf_operation_ODD1_Q_left[28]), .CK(clk), .SN(
n11444), .Q(n11352) );
DFFRXLTS add_x_19_R_130 ( .D(add_x_19_n154), .CK(clk), .RN(n11445), .Q(
n11343) );
DFFSX4TS DP_OP_168J26_122_4811_R_3213 ( .D(DP_OP_168J26_122_4811_n1389),
.CK(clk), .SN(n11726), .Q(n11690) );
DFFSX4TS DP_OP_168J26_122_4811_R_3212 ( .D(DP_OP_168J26_122_4811_n1358),
.CK(clk), .SN(n11726), .Q(n11689) );
DFFSX2TS DP_OP_168J26_122_4811_R_2797 ( .D(DP_OP_168J26_122_4811_n1285),
.CK(clk), .SN(n11718), .Q(n11608) );
DFFRX4TS DP_OP_168J26_122_4811_R_3006 ( .D(DP_OP_168J26_122_4811_n1193),
.CK(clk), .RN(n11724), .Q(n11656) );
DFFRXLTS R_183 ( .D(n12220), .CK(clk), .RN(n11980), .Q(n12168) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n578), .CK(clk), .RN(n12230),
.Q(Add_result[1]), .QN(n12378) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n579), .CK(clk), .RN(n12230),
.QN(n12384) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n577), .CK(clk), .RN(n12230),
.Q(Add_result[2]), .QN(n12377) );
DFFRXLTS R_821 ( .D(n591), .CK(clk), .RN(n12233), .Q(n2124), .QN(n12249) );
DFFRXLTS R_761 ( .D(n688), .CK(clk), .RN(n11988), .QN(n12245) );
DFFRXLTS R_2142 ( .D(n452), .CK(clk), .RN(n12227), .Q(n12116) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n350),
.CK(clk), .RN(n12236), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n351),
.CK(clk), .RN(n12236), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n349),
.CK(clk), .RN(n12236), .Q(final_result_ieee[2]) );
DFFRXLTS R_2121 ( .D(n454), .CK(clk), .RN(n12225), .Q(n12117) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_52_ ( .D(n299),
.CK(clk), .RN(n12241), .Q(final_result_ieee[52]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_62_ ( .D(n289),
.CK(clk), .RN(n12395), .Q(final_result_ieee[62]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_61_ ( .D(n290),
.CK(clk), .RN(n12395), .Q(final_result_ieee[61]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_60_ ( .D(n291),
.CK(clk), .RN(n1827), .Q(final_result_ieee[60]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_59_ ( .D(n292),
.CK(clk), .RN(n1827), .Q(final_result_ieee[59]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_58_ ( .D(n293),
.CK(clk), .RN(n11712), .Q(final_result_ieee[58]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_57_ ( .D(n294),
.CK(clk), .RN(n12241), .Q(final_result_ieee[57]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_56_ ( .D(n295),
.CK(clk), .RN(n12241), .Q(final_result_ieee[56]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_55_ ( .D(n296),
.CK(clk), .RN(n12241), .Q(final_result_ieee[55]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_53_ ( .D(n298),
.CK(clk), .RN(n1891), .Q(final_result_ieee[53]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n327),
.CK(clk), .RN(n11986), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n328),
.CK(clk), .RN(n11987), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n329),
.CK(clk), .RN(n11988), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n330),
.CK(clk), .RN(n11986), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n331),
.CK(clk), .RN(n11988), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n332),
.CK(clk), .RN(n12238), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n333),
.CK(clk), .RN(n11986), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n334),
.CK(clk), .RN(n12238), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n335),
.CK(clk), .RN(n11987), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n336),
.CK(clk), .RN(n11986), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n337),
.CK(clk), .RN(n12237), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n338),
.CK(clk), .RN(n12237), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n339),
.CK(clk), .RN(n12237), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n340),
.CK(clk), .RN(n12237), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n341),
.CK(clk), .RN(n12237), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n342),
.CK(clk), .RN(n12237), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n343),
.CK(clk), .RN(n12237), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n344),
.CK(clk), .RN(n12237), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n345),
.CK(clk), .RN(n12237), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n348),
.CK(clk), .RN(n12236), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n346),
.CK(clk), .RN(n12237), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n347),
.CK(clk), .RN(n12236), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_51_ ( .D(n300),
.CK(clk), .RN(n12231), .Q(final_result_ieee[51]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_50_ ( .D(n301),
.CK(clk), .RN(n12240), .Q(final_result_ieee[50]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_49_ ( .D(n302),
.CK(clk), .RN(n12240), .Q(final_result_ieee[49]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_48_ ( .D(n303),
.CK(clk), .RN(n12240), .Q(final_result_ieee[48]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_47_ ( .D(n304),
.CK(clk), .RN(n12240), .Q(final_result_ieee[47]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_46_ ( .D(n305),
.CK(clk), .RN(n11998), .Q(final_result_ieee[46]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_45_ ( .D(n306),
.CK(clk), .RN(n11972), .Q(final_result_ieee[45]) );
DFFRXLTS R_1472_RW_0 ( .D(n12219), .CK(clk), .RN(n12227), .Q(n12127) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_1_ ( .D(n11888), .CK(clk), .RN(
n12222), .Q(P_Sgf[1]), .QN(n1998) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_63_ ( .D(n645), .CK(clk), .RN(
n1828), .Q(Op_MX[63]), .QN(n11893) );
DFFRHQX1TS Operands_load_reg_YMRegister_Q_reg_63_ ( .D(n715), .CK(clk), .RN(
n1828), .Q(Op_MY[63]) );
DFFRHQX1TS R_900 ( .D(n694), .CK(clk), .RN(n1827), .Q(n11339) );
DFFRHQX1TS R_757 ( .D(n688), .CK(clk), .RN(n1828), .Q(n12138) );
DFFSX2TS R_782_IP ( .D(n11338), .CK(clk), .SN(n1827), .Q(n12151) );
DFFRHQX1TS R_872 ( .D(n673), .CK(clk), .RN(n1829), .Q(n11814) );
DFFRHQX1TS R_2419 ( .D(n628), .CK(clk), .RN(n1830), .Q(Op_MY[46]) );
DFFRHQX1TS R_1250 ( .D(n673), .CK(clk), .RN(n1827), .Q(n11337) );
DFFSX4TS add_x_19_R_1844 ( .D(Sgf_operation_ODD1_Q_left[7]), .CK(clk), .SN(
n11980), .Q(n11379) );
DFFSX4TS DP_OP_168J26_122_4811_R_2593 ( .D(DP_OP_168J26_122_4811_n160), .CK(
clk), .SN(n1012), .Q(n11588) );
DFFSX4TS add_x_19_R_1405_RW_1 ( .D(Sgf_operation_ODD1_Q_left[12]), .CK(clk),
.SN(n10319), .Q(n11353) );
DFFSX4TS add_x_19_R_1474_RW_1 ( .D(Sgf_operation_ODD1_Q_left[11]), .CK(clk),
.SN(n10319), .Q(n11359) );
DFFSX4TS add_x_19_R_1487_RW_0 ( .D(Sgf_operation_ODD1_Q_left[15]), .CK(clk),
.SN(n10319), .Q(n11360) );
DFFSX4TS add_x_19_R_1418 ( .D(Sgf_operation_ODD1_Q_left[14]), .CK(clk), .SN(
n10319), .Q(n11355) );
DFFRXLTS R_1738 ( .D(n459), .CK(clk), .RN(n11977), .Q(n12123) );
DFFRXLTS R_1783 ( .D(n458), .CK(clk), .RN(n11978), .Q(n12120) );
DFFRXLTS R_1777 ( .D(n457), .CK(clk), .RN(n12221), .Q(n12122) );
DFFRXLTS R_1780 ( .D(n456), .CK(clk), .RN(n12226), .Q(n12121) );
DFFRXLTS R_1722 ( .D(n461), .CK(clk), .RN(n11977), .Q(n12124) );
DFFRXLTS R_1719 ( .D(n460), .CK(clk), .RN(n1023), .Q(n12125) );
DFFRXLTS R_1315 ( .D(n467), .CK(clk), .RN(n1023), .Q(n12132) );
DFFRXLTS R_1615 ( .D(n462), .CK(clk), .RN(n11977), .Q(n12126) );
DFFRXLTS add_x_19_R_1741_RW_0 ( .D(Sgf_operation_ODD1_Q_left[7]), .CK(clk),
.RN(n11444), .Q(n11374) );
DFFRXLTS add_x_19_R_1786 ( .D(Sgf_operation_ODD1_Q_left[8]), .CK(clk), .RN(
n11452), .Q(n11376) );
DFFRXLTS R_1336 ( .D(n464), .CK(clk), .RN(n1023), .Q(n12131) );
DFFRXLTS R_1339 ( .D(n463), .CK(clk), .RN(n1023), .Q(n12130) );
DFFRXLTS R_1342 ( .D(n465), .CK(clk), .RN(n1023), .Q(n12129) );
DFFRXLTS R_707 ( .D(n469), .CK(clk), .RN(n11975), .Q(n12153) );
DFFRXLTS add_x_19_R_1790 ( .D(Sgf_operation_ODD1_Q_left[9]), .CK(clk), .RN(
n11985), .Q(n11377) );
DFFRXLTS R_1170 ( .D(n468), .CK(clk), .RN(n1023), .Q(n12135) );
DFFRXLTS R_691 ( .D(n472), .CK(clk), .RN(n11975), .Q(n12155) );
DFFRXLTS R_710 ( .D(n471), .CK(clk), .RN(n11975), .Q(n12152) );
DFFRXLTS R_704 ( .D(n470), .CK(clk), .RN(n11975), .Q(n12154) );
DFFRXLTS R_863 ( .D(n473), .CK(clk), .RN(n11976), .Q(n12140) );
DFFRXLTS R_815 ( .D(n475), .CK(clk), .RN(n11978), .Q(n12144) );
DFFRXLTS R_439 ( .D(n474), .CK(clk), .RN(n12226), .Q(n12157) );
DFFRXLTS R_445 ( .D(n476), .CK(clk), .RN(n11979), .Q(n12156) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_10_ ( .D(n431), .CK(clk), .RN(
n12224), .Q(P_Sgf[10]), .QN(n2126) );
DFFRXLTS add_x_19_R_1552_RW_2 ( .D(Sgf_operation_ODD1_Q_left[13]), .CK(clk),
.RN(n12222), .Q(n11363) );
DFFRXLTS R_199 ( .D(n483), .CK(clk), .RN(n11985), .Q(n12167) );
DFFRXLTS add_x_19_R_1516_RW_0 ( .D(Sgf_operation_ODD1_Q_left[12]), .CK(clk),
.RN(n12225), .Q(n11361) );
DFFRXLTS add_x_19_R_1581_RW_0 ( .D(Sgf_operation_ODD1_Q_left[15]), .CK(clk),
.RN(n11444), .Q(n11367) );
DFFRXLTS R_212 ( .D(n488), .CK(clk), .RN(n11980), .Q(n12164) );
DFFRXLTS R_226 ( .D(n477), .CK(clk), .RN(n11979), .Q(n12160) );
DFFRXLTS R_223 ( .D(n479), .CK(clk), .RN(n12225), .Q(n12161) );
DFFRXLTS R_232 ( .D(n478), .CK(clk), .RN(n11979), .Q(n12158) );
DFFRXLTS R_106 ( .D(n480), .CK(clk), .RN(n11979), .Q(n12173) );
DFFRXLTS DP_OP_168J26_122_4811_R_3011 ( .D(n2957), .CK(clk), .RN(n11719),
.Q(n11658) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_20_ ( .D(n441), .CK(clk), .RN(
n12223), .Q(P_Sgf[20]), .QN(n1445) );
DFFRXLTS add_x_19_R_1530_RW_0 ( .D(Sgf_operation_ODD1_Q_left[14]), .CK(clk),
.RN(n11444), .Q(n11362) );
DFFRXLTS DP_OP_168J26_122_4811_R_2869 ( .D(DP_OP_168J26_122_4811_n173), .CK(
clk), .RN(n11716), .Q(n11637) );
DFFRXLTS DP_OP_168J26_122_4811_R_2985 ( .D(DP_OP_168J26_122_4811_n183), .CK(
clk), .RN(n2008), .Q(n11651) );
DFFRXLTS R_115 ( .D(n489), .CK(clk), .RN(n11980), .Q(n12170) );
DFFRXLTS add_x_19_R_1588 ( .D(Sgf_operation_ODD1_Q_left[25]), .CK(clk), .RN(
n11448), .Q(n11368) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_16_ ( .D(n437), .CK(clk), .RN(
n12224), .Q(P_Sgf[16]), .QN(n991) );
DFFRXLTS R_152 ( .D(n482), .CK(clk), .RN(n9663), .Q(n12169) );
DFFRXLTS R_229 ( .D(n481), .CK(clk), .RN(n11979), .Q(n12159) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_25_ ( .D(n446), .CK(clk), .RN(
n12223), .Q(P_Sgf[25]), .QN(n1994) );
DFFRXLTS R_207 ( .D(n484), .CK(clk), .RN(n11453), .QN(n999) );
DFFRXLTS R_202 ( .D(n486), .CK(clk), .RN(n11980), .Q(n12166) );
DFFRXLTS R_61 ( .D(n487), .CK(clk), .RN(n11984), .Q(n12188) );
DFFRXLTS R_218 ( .D(n485), .CK(clk), .RN(n11979), .QN(n992) );
DFFRXLTS add_x_19_R_171 ( .D(add_x_19_n313), .CK(clk), .RN(n11449), .Q(
n11348) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_22_ ( .D(n443), .CK(clk), .RN(
n12223), .Q(P_Sgf[22]), .QN(n1443) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_21_ ( .D(n442), .CK(clk), .RN(
n12223), .Q(P_Sgf[21]), .QN(n1353) );
DFFRXLTS DP_OP_168J26_122_4811_R_2874 ( .D(DP_OP_168J26_122_4811_n136), .CK(
clk), .RN(n11977), .Q(n11638) );
DFFRXLTS R_215 ( .D(n490), .CK(clk), .RN(n11980), .Q(n12163) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n357), .CK(clk),
.RN(n2010), .Q(Sgf_normalized_result[4]), .QN(n2136) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_18_ ( .D(n439), .CK(clk), .RN(
n12223), .Q(P_Sgf[18]), .QN(n1354) );
DFFRXLTS R_112 ( .D(n498), .CK(clk), .RN(n11981), .Q(n12171) );
DFFRXLTS R_109 ( .D(n496), .CK(clk), .RN(n11984), .Q(n12172) );
DFFRXLTS R_1 ( .D(n497), .CK(clk), .RN(n11984), .Q(n12208) );
DFFRXLTS R_7 ( .D(n499), .CK(clk), .RN(n11984), .Q(n12206) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n358), .CK(clk),
.RN(n11697), .Q(Sgf_normalized_result[5]), .QN(n2134) );
DFFRXLTS add_x_19_R_134 ( .D(add_x_19_n97), .CK(clk), .RN(n11445), .Q(n11344) );
DFFRXLTS add_x_19_R_1554 ( .D(Sgf_operation_ODD1_Q_left[27]), .CK(clk), .RN(
n11449), .Q(n11364) );
DFFRXLTS add_x_19_R_1557 ( .D(Sgf_operation_ODD1_Q_left[26]), .CK(clk), .RN(
n11449), .Q(n11365) );
DFFRXLTS add_x_19_R_2195 ( .D(Sgf_operation_ODD1_Q_right[48]), .CK(clk),
.RN(n11450), .Q(n11389) );
DFFRXLTS add_x_19_R_126 ( .D(add_x_19_n252), .CK(clk), .RN(n11449), .Q(
n11341) );
DFFRXLTS add_x_19_R_124 ( .D(add_x_19_n278), .CK(clk), .RN(n11448), .Q(
n11340) );
DFFRXLTS add_x_19_R_132 ( .D(add_x_19_n84), .CK(clk), .RN(n11445), .QN(n1453) );
DFFRXLTS add_x_19_R_136 ( .D(add_x_19_n178), .CK(clk), .RN(n11445), .Q(
n11345) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_23_ ( .D(n444), .CK(clk), .RN(
n12223), .Q(P_Sgf[23]), .QN(n1444) );
DFFRXLTS add_x_19_R_1576 ( .D(Sgf_operation_ODD1_Q_left[28]), .CK(clk), .RN(
n11445), .Q(n11366) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_19_ ( .D(n440), .CK(clk), .RN(
n12223), .Q(P_Sgf[19]), .QN(n1352) );
DFFRXLTS R_55 ( .D(n494), .CK(clk), .RN(n12222), .Q(n12190) );
DFFRXLTS R_58 ( .D(n492), .CK(clk), .RN(n12394), .Q(n12189) );
DFFRXLTS R_103 ( .D(n493), .CK(clk), .RN(n12221), .Q(n12174) );
DFFRXLTS R_4 ( .D(n495), .CK(clk), .RN(n11980), .Q(n12207) );
DFFRXLTS add_x_19_R_2153_RW_0 ( .D(Sgf_operation_ODD1_Q_right[49]), .CK(clk),
.RN(n11450), .Q(n11387) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_17_ ( .D(n438), .CK(clk), .RN(
n12224), .Q(P_Sgf[17]), .QN(n1442) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_26_ ( .D(n447), .CK(clk), .RN(
n12223), .Q(P_Sgf[26]), .QN(n1996) );
DFFRXLTS add_x_19_R_140 ( .D(add_x_19_n121), .CK(clk), .RN(n11445), .QN(n990) );
DFFRXLTS add_x_19_R_2170_RW_0 ( .D(add_x_19_n705), .CK(clk), .RN(n10320),
.Q(n11388) );
DFFRXLTS DP_OP_168J26_122_4811_R_2750 ( .D(DP_OP_168J26_122_4811_n1105),
.CK(clk), .RN(n2004), .Q(n11604) );
DFFRXLTS add_x_19_R_3075 ( .D(add_x_19_n774), .CK(clk), .RN(n11454), .QN(
n3316) );
DFFRHQX4TS DP_OP_168J26_122_4811_R_1307 ( .D(n673), .CK(clk), .RN(n1830),
.Q(DP_OP_168J26_122_4811_n8498) );
DFFSX4TS DP_OP_168J26_122_4811_R_2827 ( .D(DP_OP_168J26_122_4811_n1163),
.CK(clk), .SN(n11722), .Q(n11622) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n353), .CK(clk),
.RN(n12236), .Q(Sgf_normalized_result[0]), .QN(n11892) );
DFFRXLTS R_841 ( .D(n647), .CK(clk), .RN(n2006), .Q(n12214), .QN(n11898) );
DFFRXLTS DP_OP_168J26_122_4811_R_2663 ( .D(DP_OP_168J26_122_4811_n588), .CK(
clk), .RN(n11716), .Q(n11593) );
DFFRXLTS add_x_19_R_2854 ( .D(add_x_19_n770), .CK(clk), .RN(n11454), .Q(
n11418) );
DFFRXLTS add_x_19_R_2536_RW_0 ( .D(Sgf_operation_ODD1_Q_right[42]), .CK(clk),
.RN(n12226), .Q(n11402) );
DFFRXLTS add_x_19_R_2251_RW_0 ( .D(Sgf_operation_ODD1_Q_right[43]), .CK(clk),
.RN(n11976), .Q(n11392) );
DFFSX1TS add_x_19_R_1729_RW_0 ( .D(Sgf_operation_ODD1_Q_left[5]), .CK(clk),
.SN(n11456), .Q(n11372) );
DFFSX1TS DP_OP_168J26_122_4811_R_1736 ( .D(DP_OP_168J26_122_4811_n96), .CK(
clk), .SN(n11714), .Q(n11539) );
DFFSX1TS add_x_19_R_1460 ( .D(Sgf_operation_ODD1_Q_left[25]), .CK(clk), .SN(
n1012), .Q(n11358) );
DFFSX1TS R_53 ( .D(n12373), .CK(clk), .SN(n1012), .Q(n12191) );
DFFRX4TS Sel_A_Q_reg_0_ ( .D(n710), .CK(clk), .RN(n11973), .Q(FSM_selector_A), .QN(n11802) );
DFFSX4TS DP_OP_168J26_122_4811_R_3214 ( .D(DP_OP_168J26_122_4811_n1356),
.CK(clk), .SN(n11726), .Q(n11691) );
DFFSX4TS DP_OP_168J26_122_4811_R_2963 ( .D(DP_OP_168J26_122_4811_n586), .CK(
clk), .SN(n11722), .Q(n11648) );
DFFRX1TS add_x_19_R_2971_RW_0 ( .D(add_x_19_n702), .CK(clk), .RN(n11715),
.QN(n11461) );
DFFSX4TS DP_OP_168J26_122_4811_R_2826 ( .D(DP_OP_168J26_122_4811_n1165),
.CK(clk), .SN(n11721), .Q(n11621) );
DFFSX4TS DP_OP_168J26_122_4811_R_3005 ( .D(DP_OP_168J26_122_4811_n1166),
.CK(clk), .SN(n11723), .Q(n11655) );
DFFRX1TS DP_OP_168J26_122_4811_R_2947 ( .D(DP_OP_168J26_122_4811_n333), .CK(
clk), .RN(n2008), .Q(n11642) );
DFFRX4TS DP_OP_168J26_122_4811_R_3007 ( .D(DP_OP_168J26_122_4811_n1164),
.CK(clk), .RN(n11724), .Q(n11657) );
DFFSX2TS DP_OP_168J26_122_4811_R_2861 ( .D(DP_OP_168J26_122_4811_n1080),
.CK(clk), .SN(n11719), .Q(n11631) );
DFFSX2TS DP_OP_168J26_122_4811_R_2964 ( .D(DP_OP_168J26_122_4811_n575), .CK(
clk), .SN(n11978), .Q(n11649) );
DFFRX4TS add_x_19_R_181 ( .D(n3324), .CK(clk), .RN(n11456), .Q(n11350) );
DFFSX2TS DP_OP_168J26_122_4811_R_2860 ( .D(DP_OP_168J26_122_4811_n1105),
.CK(clk), .SN(n11717), .Q(n11630) );
DFFRX4TS DP_OP_168J26_122_4811_R_1815 ( .D(n11549), .CK(clk), .RN(n11706),
.Q(DP_OP_168J26_122_4811_n6589) );
DFFRX4TS DP_OP_168J26_122_4811_R_905 ( .D(n11506), .CK(clk), .RN(n1956), .Q(
DP_OP_168J26_122_4811_n8190) );
DFFSX2TS R_3130 ( .D(n12310), .CK(clk), .SN(n1830), .Q(n12040) );
DFFSX2TS R_3242 ( .D(n12367), .CK(clk), .SN(n11973), .Q(n12005) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n416), .CK(clk), .RN(n12234),
.QN(n1433) );
DFFSX2TS add_x_19_R_1442 ( .D(Sgf_operation_ODD1_Q_left[29]), .CK(clk), .SN(
n11444), .Q(n11356) );
DFFRX4TS DP_OP_168J26_122_4811_R_3089 ( .D(n11669), .CK(clk), .RN(n11696),
.Q(DP_OP_168J26_122_4811_n3578), .QN(n1409) );
DFFRX4TS DP_OP_168J26_122_4811_R_2828 ( .D(DP_OP_168J26_122_4811_n1136),
.CK(clk), .RN(n11724), .Q(n11623) );
DFFSX4TS DP_OP_168J26_122_4811_R_2962 ( .D(n1843), .CK(clk), .SN(n11722),
.Q(n11647) );
DFFRX4TS DP_OP_168J26_122_4811_R_935 ( .D(n11514), .CK(clk), .RN(n11706),
.Q(DP_OP_168J26_122_4811_n6588) );
DFFRX4TS DP_OP_168J26_122_4811_R_1541 ( .D(n11533), .CK(clk), .RN(n12233),
.Q(DP_OP_168J26_122_4811_n8197) );
DFFSX2TS R_2996 ( .D(n12381), .CK(clk), .SN(n11976), .Q(n12054) );
DFFSX4TS DP_OP_168J26_122_4811_R_762 ( .D(n11479), .CK(clk), .SN(n11706),
.Q(DP_OP_168J26_122_4811_n3219) );
DFFRX4TS DP_OP_168J26_122_4811_R_3119 ( .D(n671), .CK(clk), .RN(n12242), .Q(
DP_OP_168J26_122_4811_n3214), .QN(n11580) );
DFFSX4TS R_2997 ( .D(n12383), .CK(clk), .SN(n11976), .Q(n12053) );
DFFRX4TS DP_OP_168J26_122_4811_R_2471 ( .D(DP_OP_168J26_122_4811_n134), .CK(
clk), .RN(n11724), .Q(n11577) );
DFFRXLTS DP_OP_168J26_122_4811_R_2928 ( .D(DP_OP_168J26_122_4811_n572), .CK(
clk), .RN(n11724), .Q(n11641) );
DFFRX4TS DP_OP_168J26_122_4811_R_2462 ( .D(DP_OP_168J26_122_4811_n132), .CK(
clk), .RN(n11724), .Q(n11576) );
DFFRX4TS DP_OP_168J26_122_4811_R_2806 ( .D(DP_OP_168J26_122_4811_n619), .CK(
clk), .RN(n11724), .Q(n11610) );
DFFRX4TS DP_OP_168J26_122_4811_R_2714 ( .D(DP_OP_168J26_122_4811_n135), .CK(
clk), .RN(n11724), .Q(n11599) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_47_ ( .D(n400), .CK(clk),
.RN(n1830), .Q(Sgf_normalized_result[47]), .QN(n11890) );
DFFSX2TS R_2917 ( .D(n12265), .CK(clk), .SN(n1854), .Q(n12074) );
DFFSX2TS R_2902 ( .D(n12294), .CK(clk), .SN(n11990), .Q(n12089) );
DFFSX2TS R_3224 ( .D(n12326), .CK(clk), .SN(n12001), .Q(n12023) );
DFFRX4TS R_849 ( .D(n666), .CK(clk), .RN(n971), .QN(n11816) );
DFFSX2TS R_14 ( .D(n12301), .CK(clk), .SN(n11982), .Q(n12204) );
DFFSX2TS R_2914 ( .D(n12314), .CK(clk), .SN(n11999), .Q(n12077) );
DFFSX2TS R_2926 ( .D(n12346), .CK(clk), .SN(n1975), .Q(n12065) );
DFFRX4TS R_850 ( .D(n665), .CK(clk), .RN(n12240), .QN(n12145) );
DFFRX4TS R_1299 ( .D(n672), .CK(clk), .RN(n11994), .QN(n11794) );
DFFSX2TS DP_OP_168J26_122_4811_R_2762 ( .D(DP_OP_168J26_122_4811_n201), .CK(
clk), .SN(n11714), .Q(n11606), .QN(n11728) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_24_ ( .D(n555), .CK(clk), .RN(n1827),
.Q(Add_result[24]), .QN(n11867) );
DFFSX2TS R_2911 ( .D(n12274), .CK(clk), .SN(n1976), .Q(n12080) );
DFFSX2TS R_3227 ( .D(n12330), .CK(clk), .SN(n11990), .Q(n12020) );
DFFSX2TS R_3230 ( .D(n12338), .CK(clk), .SN(n11999), .Q(n12017) );
DFFRX4TS R_794 ( .D(n616), .CK(clk), .RN(n1891), .QN(n11943) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_44_ ( .D(n535), .CK(clk), .RN(n12228),
.Q(Add_result[44]), .QN(n11847) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_25_ ( .D(n554), .CK(clk), .RN(n11705),
.Q(Add_result[25]), .QN(n11866) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_47_ ( .D(n532), .CK(clk), .RN(n1830),
.Q(Add_result[47]), .QN(n11844) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_52_ ( .D(n634), .CK(clk), .RN(
n11993), .Q(Op_MY[52]), .QN(n11956) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_54_ ( .D(n700), .CK(clk), .RN(
n1956), .Q(Op_MX[54]), .QN(n11830) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n354), .CK(clk),
.RN(n12236), .Q(Sgf_normalized_result[1]), .QN(n11891) );
DFFRXLTS add_x_19_R_2596 ( .D(add_x_19_n748), .CK(clk), .RN(n11454), .Q(
n11405) );
DFFRX1TS add_x_19_R_2856 ( .D(add_x_19_n747), .CK(clk), .RN(n11454), .Q(
n11419) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n414), .CK(clk), .RN(n1974),
.Q(exp_oper_result[3]), .QN(n12385) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n413), .CK(clk), .RN(n1854),
.Q(exp_oper_result[4]), .QN(n12386) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n411), .CK(clk), .RN(n1974),
.Q(exp_oper_result[6]), .QN(n12388) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_14_ ( .D(n435), .CK(clk), .RN(
n12224), .Q(P_Sgf[14]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_15_ ( .D(n436), .CK(clk), .RN(
n12224), .Q(P_Sgf[15]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_12_ ( .D(n433), .CK(clk), .RN(
n12224), .Q(P_Sgf[12]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_11_ ( .D(n432), .CK(clk), .RN(
n12224), .Q(P_Sgf[11]) );
DFFRX2TS add_x_19_R_169 ( .D(add_x_19_n202), .CK(clk), .RN(n11449), .Q(
n11347) );
DFFRX2TS add_x_19_R_128 ( .D(add_x_19_n228), .CK(clk), .RN(n11449), .Q(
n11342) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n571), .CK(clk), .RN(n12230),
.Q(Add_result[8]), .QN(n11879) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n570), .CK(clk), .RN(n12230),
.Q(Add_result[9]), .QN(n11878) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n573), .CK(clk), .RN(n12230),
.Q(Add_result[6]), .QN(n11881) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n574), .CK(clk), .RN(n12230),
.Q(Add_result[5]), .QN(n11882) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n575), .CK(clk), .RN(n12230),
.Q(Add_result[4]), .QN(n11883) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n576), .CK(clk), .RN(n12230),
.Q(Add_result[3]), .QN(n11884) );
DFFRX4TS DP_OP_168J26_122_4811_R_2739 ( .D(DP_OP_168J26_122_4811_n613), .CK(
clk), .RN(n11723), .Q(n11602) );
DFFRX4TS DP_OP_168J26_122_4811_R_2562 ( .D(DP_OP_168J26_122_4811_n133), .CK(
clk), .RN(n11723), .Q(n11579) );
DFFRX4TS DP_OP_168J26_122_4811_R_2397 ( .D(n1339), .CK(clk), .RN(n11726),
.Q(n11573) );
DFFRX4TS add_x_19_R_2096_RW_0 ( .D(Sgf_operation_ODD1_Q_right[50]), .CK(clk),
.RN(n11450), .Q(n11385) );
DFFSX2TS R_2910 ( .D(n12275), .CK(clk), .SN(n1975), .Q(n12081) );
DFFSX2TS R_2908 ( .D(n12278), .CK(clk), .SN(n1976), .Q(n12083) );
DFFSX2TS R_2888 ( .D(n12251), .CK(clk), .SN(n1975), .Q(n12103) );
DFFRX1TS R_2668 ( .D(n449), .CK(clk), .RN(n1023), .Q(n12110) );
DFFRX2TS DP_OP_168J26_122_4811_R_2718 ( .D(n7424), .CK(clk), .RN(n11714),
.Q(n11601) );
DFFRX4TS R_747 ( .D(n582), .CK(clk), .RN(n12234), .Q(Op_MY[0]), .QN(n11910)
);
DFFRX4TS R_929 ( .D(n586), .CK(clk), .RN(n12234), .Q(Op_MY[4]), .QN(n11909)
);
DFFSX2TS R_41 ( .D(n12264), .CK(clk), .SN(n11985), .Q(n12195) );
DFFSX2TS R_35 ( .D(n12250), .CK(clk), .SN(n11985), .Q(n12198) );
DFFSX4TS DP_OP_168J26_122_4811_R_3003 ( .D(DP_OP_168J26_122_4811_n288), .CK(
clk), .SN(n11722), .Q(n11654) );
DFFRX4TS R_734 ( .D(n611), .CK(clk), .RN(n11997), .QN(n11970) );
DFFRX2TS R_566 ( .D(n3314), .CK(clk), .RN(n11997), .QN(n11946) );
DFFRX2TS R_928 ( .D(n613), .CK(clk), .RN(n11997), .QN(n12147) );
DFFRX4TS R_889 ( .D(n615), .CK(clk), .RN(n11997), .Q(Op_MY[33]), .QN(n11959)
);
DFFRX2TS R_746 ( .D(n609), .CK(clk), .RN(n11997), .Q(Op_MY[27]), .QN(n11915)
);
DFFSX4TS add_x_19_R_2775 ( .D(add_x_19_n762), .CK(clk), .SN(n11453), .Q(
n11414) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n564), .CK(clk), .RN(n12229),
.Q(Add_result[15]), .QN(n11873) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n563), .CK(clk), .RN(n12229),
.Q(Add_result[16]), .QN(n11872) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n567), .CK(clk), .RN(n12229),
.Q(Add_result[12]), .QN(n11876) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n565), .CK(clk), .RN(n12229),
.Q(Add_result[14]), .QN(n11874) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n568), .CK(clk), .RN(n12229),
.Q(Add_result[11]), .QN(n11877) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n566), .CK(clk), .RN(n12229),
.Q(Add_result[13]), .QN(n11875) );
DFFRX4TS R_555 ( .D(n9682), .CK(clk), .RN(n11987), .QN(n11944) );
DFFRX4TS R_551 ( .D(n683), .CK(clk), .RN(n11988), .QN(n11969) );
DFFRX4TS R_874 ( .D(n690), .CK(clk), .RN(n11986), .QN(n11813) );
DFFRX4TS R_530 ( .D(n684), .CK(clk), .RN(n12238), .QN(n11945) );
DFFRX2TS R_835 ( .D(n675), .CK(clk), .RN(n12238), .Q(Op_MX[29]), .QN(n11907)
);
DFFRX4TS R_859 ( .D(n680), .CK(clk), .RN(n11988), .QN(n11810) );
DFFRX4TS R_817 ( .D(n674), .CK(clk), .RN(n11986), .QN(n11809) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n370), .CK(clk),
.RN(n11992), .Q(Sgf_normalized_result[17]), .QN(n11933) );
DFFSX2TS add_x_19_R_3012 ( .D(Sgf_operation_ODD1_Q_left[48]), .CK(clk), .SN(
n11446), .Q(n11434) );
DFFSX2TS add_x_19_R_3019 ( .D(Sgf_operation_ODD1_Q_left[38]), .CK(clk), .SN(
n11446), .Q(n11439) );
DFFSX2TS add_x_19_R_3017 ( .D(Sgf_operation_ODD1_Q_left[41]), .CK(clk), .SN(
n11446), .Q(n11437) );
DFFSX2TS add_x_19_R_3016 ( .D(Sgf_operation_ODD1_Q_left[42]), .CK(clk), .SN(
n11446), .Q(n11436) );
DFFRX4TS R_547 ( .D(n651), .CK(clk), .RN(n12231), .QN(n11787) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_10_ ( .D(n407), .CK(clk), .RN(n11989),
.Q(exp_oper_result[10]), .QN(n12392) );
DFFRX4TS R_730 ( .D(n653), .CK(clk), .RN(n11999), .QN(n11808) );
DFFRX4TS R_3094 ( .D(n601), .CK(clk), .RN(n12232), .QN(n11954) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n415), .CK(clk), .RN(n11999),
.Q(exp_oper_result[2]), .QN(n3315) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n409), .CK(clk), .RN(n11990),
.Q(exp_oper_result[8]), .QN(n12390) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n412), .CK(clk), .RN(n11989),
.Q(exp_oper_result[5]), .QN(n12387) );
DFFRX4TS Sgf_operation_ODD1_finalreg_Q_reg_2_ ( .D(n423), .CK(clk), .RN(
n11978), .Q(P_Sgf[2]) );
DFFRX4TS Sgf_operation_ODD1_finalreg_Q_reg_3_ ( .D(n424), .CK(clk), .RN(
n12225), .Q(P_Sgf[3]) );
DFFRX4TS Sgf_operation_ODD1_finalreg_Q_reg_5_ ( .D(n426), .CK(clk), .RN(
n12225), .Q(P_Sgf[5]) );
DFFRX4TS Sgf_operation_ODD1_finalreg_Q_reg_6_ ( .D(n427), .CK(clk), .RN(
n12225), .Q(P_Sgf[6]) );
DFFRX4TS Sgf_operation_ODD1_finalreg_Q_reg_13_ ( .D(n434), .CK(clk), .RN(
n12224), .Q(P_Sgf[13]) );
DFFRX4TS Sgf_operation_ODD1_finalreg_Q_reg_9_ ( .D(n430), .CK(clk), .RN(
n12224), .Q(P_Sgf[9]) );
DFFRX4TS Sgf_operation_ODD1_finalreg_Q_reg_7_ ( .D(n428), .CK(clk), .RN(
n11982), .Q(P_Sgf[7]) );
DFFRX4TS R_2570 ( .D(n598), .CK(clk), .RN(n12000), .QN(n12247) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n557), .CK(clk), .RN(n11996),
.Q(Add_result[22]), .QN(n11837) );
DFFRX2TS Sgf_operation_ODD1_finalreg_Q_reg_0_ ( .D(n421), .CK(clk), .RN(
n12394), .Q(P_Sgf[0]) );
DFFRX4TS Sgf_operation_ODD1_finalreg_Q_reg_4_ ( .D(n425), .CK(clk), .RN(
n12221), .Q(P_Sgf[4]) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_38_ ( .D(n541), .CK(clk), .RN(n11698),
.Q(Add_result[38]), .QN(n11853) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_37_ ( .D(n542), .CK(clk), .RN(n12228),
.Q(Add_result[37]), .QN(n11854) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_36_ ( .D(n543), .CK(clk), .RN(n12243),
.Q(Add_result[36]), .QN(n11855) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_35_ ( .D(n544), .CK(clk), .RN(n10321),
.Q(Add_result[35]), .QN(n11856) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_28_ ( .D(n551), .CK(clk), .RN(n11695),
.Q(Add_result[28]), .QN(n11863) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_26_ ( .D(n553), .CK(clk), .RN(n11696),
.Q(Add_result[26]), .QN(n11865) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_27_ ( .D(n552), .CK(clk), .RN(n1855),
.Q(Add_result[27]), .QN(n11864) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_41_ ( .D(n538), .CK(clk), .RN(n12241),
.Q(Add_result[41]), .QN(n11850) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_43_ ( .D(n536), .CK(clk), .RN(n12243),
.Q(Add_result[43]), .QN(n11848) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_48_ ( .D(n531), .CK(clk), .RN(n12241),
.Q(Add_result[48]), .QN(n11869) );
DFFSX2TS DP_OP_168J26_122_4811_R_1761 ( .D(DP_OP_168J26_122_4811_n105), .CK(
clk), .SN(n11717), .Q(n11548) );
DFFRX2TS R_789 ( .D(n670), .CK(clk), .RN(n11973), .QN(n11949) );
DFFRX4TS DP_OP_168J26_122_4811_R_2812 ( .D(n599), .CK(clk), .RN(n11700), .Q(
DP_OP_168J26_122_4811_n8488) );
DFFRX4TS DP_OP_168J26_122_4811_R_2255 ( .D(n11564), .CK(clk), .RN(n11700),
.Q(DP_OP_168J26_122_4811_n3536), .QN(n3318) );
DFFRX4TS R_3165 ( .D(n604), .CK(clk), .RN(n12000), .QN(n11948) );
DFFRX4TS DP_OP_168J26_122_4811_R_1538 ( .D(n11532), .CK(clk), .RN(n11704),
.Q(DP_OP_168J26_122_4811_n6591) );
DFFRX4TS Sgf_operation_ODD1_finalreg_Q_reg_8_ ( .D(n429), .CK(clk), .RN(
n12224), .Q(P_Sgf[8]) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_3071 ( .D(n9693), .CK(clk), .RN(n1974),
.Q(n1837) );
DFFSX2TS DP_OP_168J26_122_4811_R_2807 ( .D(DP_OP_168J26_122_4811_n1286),
.CK(clk), .SN(n2004), .Q(n11611) );
DFFRX1TS add_x_19_R_2941_RW_1 ( .D(add_x_19_n703), .CK(clk), .RN(n10320),
.Q(n11423) );
DFFRXLTS DP_OP_168J26_122_4811_R_2824_RW_0 ( .D(DP_OP_168J26_122_4811_n1286),
.CK(clk), .RN(n11726), .Q(n11619) );
DFFRX4TS DP_OP_168J26_122_4811_R_831 ( .D(n3314), .CK(clk), .RN(n11694), .Q(
DP_OP_168J26_122_4811_n8447), .QN(n11780) );
DFFSX1TS DP_OP_168J26_122_4811_R_2862 ( .D(DP_OP_168J26_122_4811_n627), .CK(
clk), .SN(n11715), .Q(n11632) );
DFFSX2TS DP_OP_168J26_122_4811_R_2619 ( .D(DP_OP_168J26_122_4811_n572), .CK(
clk), .SN(n11725), .Q(n11589) );
DFFRX1TS DP_OP_168J26_122_4811_R_2319 ( .D(DP_OP_168J26_122_4811_n128), .CK(
clk), .RN(n11716), .Q(n11569) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n606), .CK(clk), .RN(
n12000), .Q(n1730) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_3080 ( .D(n651), .CK(clk), .RN(n12228),
.Q(n1725) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_3095 ( .D(n601), .CK(clk), .RN(n12000),
.Q(n1717) );
DFFSHQX8TS DP_OP_168J26_122_4811_R_1246 ( .D(n11520), .CK(clk), .SN(n11709),
.Q(n1713) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_2233 ( .D(n596), .CK(clk), .RN(n11700),
.Q(n1711) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_2574 ( .D(n661), .CK(clk), .RN(n11708),
.Q(n1705) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_3160 ( .D(n690), .CK(clk), .RN(n11710),
.Q(n1703) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_3091 ( .D(n9726), .CK(clk), .RN(n11707),
.Q(n1702) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_3122 ( .D(n628), .CK(clk), .RN(n11703),
.Q(n1694) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_2566 ( .D(n12143), .CK(clk), .RN(n11999),
.Q(n1690) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_2583 ( .D(n12143), .CK(clk), .RN(n12240),
.Q(n1688) );
DFFRXLTS DP_OP_168J26_122_4811_R_2823 ( .D(DP_OP_168J26_122_4811_n376), .CK(
clk), .RN(n11719), .Q(n11618) );
DFFSX2TS DP_OP_168J26_122_4811_R_2634 ( .D(DP_OP_168J26_122_4811_n376), .CK(
clk), .SN(n2004), .Q(n11591) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_3086 ( .D(n613), .CK(clk), .RN(n12235),
.Q(n1686) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_553 ( .D(n683), .CK(clk), .RN(n11712),
.Q(n1682) );
DFFSX4TS DP_OP_168J26_122_4811_R_2886 ( .D(DP_OP_168J26_122_4811_n1422),
.CK(clk), .SN(n11980), .Q(n11639) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_2260 ( .D(n621), .CK(clk), .RN(n11700),
.Q(n1669) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_3166 ( .D(n604), .CK(clk), .RN(n11995),
.Q(n1644) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_1300 ( .D(n671), .CK(clk), .RN(n11994),
.Q(n1629) );
DFFSHQX8TS DP_OP_168J26_122_4811_R_2553 ( .D(n11727), .CK(clk), .SN(n11709),
.Q(n1624) );
DFFSX4TS add_x_19_R_2939 ( .D(Sgf_operation_ODD1_S_B[6]), .CK(clk), .SN(
n11453), .Q(n11422) );
DFFRX2TS R_2229 ( .D(n623), .CK(clk), .RN(n12000), .QN(n12141) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_32_ ( .D(n547), .CK(clk), .RN(n10321),
.Q(Add_result[32]), .QN(n11859) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_33_ ( .D(n546), .CK(clk), .RN(n10321),
.Q(Add_result[33]), .QN(n11858) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_30_ ( .D(n549), .CK(clk), .RN(n10321),
.Q(Add_result[30]), .QN(n11861) );
DFFRX2TS R_3134 ( .D(n632), .CK(clk), .RN(n11993), .QN(n12113) );
DFFRX2TS R_2189 ( .D(n627), .CK(clk), .RN(n11993), .QN(n12134) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n561), .CK(clk), .RN(n12229),
.Q(Add_result[18]), .QN(n11870) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_31_ ( .D(n548), .CK(clk), .RN(n10321),
.Q(Add_result[31]), .QN(n11860) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_29_ ( .D(n550), .CK(clk), .RN(n1957),
.Q(Add_result[29]), .QN(n11862) );
DFFRX4TS R_2209 ( .D(n597), .CK(clk), .RN(n12232), .QN(n12248) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n560), .CK(clk), .RN(n12229),
.Q(Add_result[19]), .QN(n11840) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_51_ ( .D(n528), .CK(clk), .RN(n2006),
.Q(Add_result[51]), .QN(n11841) );
DFFRX2TS R_3116 ( .D(n630), .CK(clk), .RN(n11993), .QN(n12133) );
DFFRX2TS R_1284 ( .D(n617), .CK(clk), .RN(n11998), .QN(n12142) );
DFFRX2TS R_820 ( .D(n618), .CK(clk), .RN(n12232), .QN(n12148) );
DFFRX2TS R_766 ( .D(n693), .CK(clk), .RN(n1957), .QN(n12150) );
DFFRX2TS R_1244 ( .D(n664), .CK(clk), .RN(n12240), .QN(n12136) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n359), .CK(clk),
.RN(n11694), .Q(Sgf_normalized_result[6]), .QN(n11889) );
DFFRX2TS R_855 ( .D(n620), .CK(clk), .RN(n11996), .QN(n11812) );
DFFRX4TS R_790 ( .D(n9666), .CK(clk), .RN(n1957), .QN(n11930) );
DFFRX1TS DP_OP_168J26_122_4811_R_2309 ( .D(DP_OP_168J26_122_4811_n127), .CK(
clk), .RN(n11716), .Q(n11568) );
DFFSX4TS DP_OP_168J26_122_4811_R_2950 ( .D(n1339), .CK(clk), .SN(n11451),
.Q(n11644) );
DFFSX1TS DP_OP_168J26_122_4811_R_2864 ( .D(DP_OP_168J26_122_4811_n592), .CK(
clk), .SN(n11715), .Q(n11634) );
DFFSX2TS DP_OP_168J26_122_4811_R_2808 ( .D(DP_OP_168J26_122_4811_n1319),
.CK(clk), .SN(n11719), .Q(n11612) );
DFFRX1TS DP_OP_168J26_122_4811_R_2825_RW_0 ( .D(DP_OP_168J26_122_4811_n1319),
.CK(clk), .RN(n11726), .Q(n11620) );
DFFRX1TS DP_OP_168J26_122_4811_R_2816_RW_0 ( .D(DP_OP_168J26_122_4811_n551),
.CK(clk), .RN(n11723), .Q(n11613) );
DFFRXLTS DP_OP_168J26_122_4811_R_3215 ( .D(DP_OP_168J26_122_4811_n1320),
.CK(clk), .RN(n11726), .Q(n11692) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_827 ( .D(n686), .CK(clk), .RN(n11712),
.Q(n1320) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_1285 ( .D(n617), .CK(clk), .RN(n11701),
.Q(n1291) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_844 ( .D(n647), .CK(clk), .RN(n10321),
.Q(n1286) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_2190 ( .D(n627), .CK(clk), .RN(n11703),
.Q(n1284) );
DFFRXLTS R_2464 ( .D(n450), .CK(clk), .RN(n11982), .Q(n12114) );
DFFSX2TS DP_OP_168J26_122_4811_R_2822 ( .D(DP_OP_168J26_122_4811_n1006),
.CK(clk), .SN(n11718), .Q(n11617) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_1268 ( .D(n653), .CK(clk), .RN(n11708),
.Q(n1278) );
DFFSX4TS DP_OP_168J26_122_4811_R_2226 ( .D(n11559), .CK(clk), .SN(n11699),
.Q(DP_OP_168J26_122_4811_n3498) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_3068 ( .D(n680), .CK(clk), .RN(n11707),
.Q(n1270) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_943 ( .D(n1355), .CK(clk), .RN(n11988),
.Q(n1267) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_2621 ( .D(n11804), .CK(clk), .RN(n11972),
.Q(n1260) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_795 ( .D(n616), .CK(clk), .RN(n12235),
.Q(n1256) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_3171 ( .D(n696), .CK(clk), .RN(n11972),
.Q(n1242) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_49_ ( .D(n631), .CK(clk), .RN(
n11993), .Q(n1237) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_3174 ( .D(n615), .CK(clk), .RN(n11694),
.Q(n1228) );
DFFSHQX8TS DP_OP_168J26_122_4811_R_1310 ( .D(n11531), .CK(clk), .SN(n11704),
.Q(n1226) );
DFFRX4TS R_3246 ( .D(n649), .CK(clk), .RN(n970), .QN(n11582) );
DFFRX4TS R_3247 ( .D(n649), .CK(clk), .RN(n970), .Q(n1240) );
DFFSX2TS R_3252 ( .D(n3290), .CK(clk), .SN(n11982), .Q(n1217), .QN(n1216) );
DFFSX2TS R_3253 ( .D(n12217), .CK(clk), .SN(n11976), .Q(n1215) );
DFFRX2TS R_3254 ( .D(n3290), .CK(clk), .RN(n11981), .Q(n1214) );
DFFSX2TS R_3255 ( .D(n1011), .CK(clk), .SN(n11980), .Q(n1213), .QN(n1212) );
DFFSX2TS R_3256 ( .D(n12219), .CK(clk), .SN(n11978), .Q(n1211), .QN(n1210)
);
DFFSX2TS R_3257 ( .D(n12220), .CK(clk), .SN(n12227), .Q(n1209) );
DFFSX2TS R_3258 ( .D(n2138), .CK(clk), .SN(n12221), .Q(n1208), .QN(n1207) );
DFFSX2TS R_3259 ( .D(n1011), .CK(clk), .SN(n12394), .Q(n1206), .QN(n1205) );
DFFSX2TS R_3260 ( .D(n12218), .CK(clk), .SN(n1012), .Q(n1204) );
DFFSX2TS R_3261 ( .D(add_x_19_n725), .CK(clk), .SN(n11453), .Q(n1203) );
DFFSX4TS R_3262 ( .D(n11763), .CK(clk), .SN(n11725), .Q(n1202) );
DFFSX2TS R_3263 ( .D(add_x_19_n310), .CK(clk), .SN(n11447), .Q(n1201) );
DFFSX2TS R_3264 ( .D(n9587), .CK(clk), .SN(n2004), .Q(n1200) );
DFFSX2TS R_3265 ( .D(DP_OP_168J26_122_4811_n170), .CK(clk), .SN(n11717), .Q(
n1199) );
DFFSX2TS R_3266 ( .D(n1357), .CK(clk), .SN(n11983), .Q(n1198) );
DFFSX2TS R_3267 ( .D(n3290), .CK(clk), .SN(n1012), .Q(n1197) );
DFFSX2TS R_3269 ( .D(n1357), .CK(clk), .SN(n12227), .Q(n1195) );
DFFSX2TS R_3270 ( .D(n2138), .CK(clk), .SN(n11445), .Q(n1194), .QN(n1193) );
DFFSX2TS R_3271 ( .D(n10976), .CK(clk), .SN(n11978), .Q(n1192) );
DFFSX2TS R_3272 ( .D(add_x_19_n739), .CK(clk), .SN(n11455), .Q(n1191), .QN(
n1190) );
DFFSX2TS R_3273 ( .D(Sgf_operation_ODD1_Q_left[4]), .CK(clk), .SN(n12226),
.Q(n1189) );
DFFSX2TS R_3274 ( .D(Sgf_operation_ODD1_Q_left[6]), .CK(clk), .SN(n12226),
.Q(n1188) );
DFFSX2TS R_3275 ( .D(Sgf_operation_ODD1_Q_left[22]), .CK(clk), .SN(n11450),
.Q(n1187) );
DFFSX2TS R_3276 ( .D(Sgf_operation_ODD1_Q_left[18]), .CK(clk), .SN(n11451),
.Q(n1186) );
DFFSX2TS R_3277 ( .D(Sgf_operation_ODD1_Q_left[20]), .CK(clk), .SN(n9663),
.Q(n1185) );
DFFSX2TS R_3278 ( .D(Sgf_operation_ODD1_Q_left[16]), .CK(clk), .SN(n9663),
.Q(n1184) );
DFFSX2TS R_3279 ( .D(Sgf_operation_ODD1_Q_left[10]), .CK(clk), .SN(n11452),
.Q(n1183) );
DFFSX2TS R_3280 ( .D(n11778), .CK(clk), .SN(n11717), .Q(n1182), .QN(n1181)
);
DFFSX2TS R_3281 ( .D(n11761), .CK(clk), .SN(n11718), .Q(n1180) );
DFFSX2TS R_3282 ( .D(DP_OP_168J26_122_4811_n1053), .CK(clk), .SN(n11722),
.Q(n1179) );
DFFSX2TS R_3283 ( .D(DP_OP_168J26_122_4811_n1054), .CK(clk), .SN(n11721),
.Q(n1178) );
DFFSX2TS R_3284 ( .D(DP_OP_168J26_122_4811_n1387), .CK(clk), .SN(n11725),
.Q(n1177) );
DFFSX2TS R_3285 ( .D(DP_OP_168J26_122_4811_n1253), .CK(clk), .SN(n2004), .Q(
n1176) );
DFFSX2TS R_3286 ( .D(DP_OP_168J26_122_4811_n1254), .CK(clk), .SN(n11718),
.Q(n1175) );
DFFSX2TS R_3287 ( .D(DP_OP_168J26_122_4811_n534), .CK(clk), .SN(n11720), .Q(
n1174) );
DFFSX2TS R_3288 ( .D(n11776), .CK(clk), .SN(n11718), .Q(n1173) );
DFFSX2TS R_3289 ( .D(Sgf_operation_ODD1_Q_left[30]), .CK(clk), .SN(n1012),
.Q(n1172) );
DFFSX2TS R_3290 ( .D(Sgf_operation_ODD1_Q_right[40]), .CK(clk), .SN(n11455),
.Q(n1171) );
DFFSX2TS R_3291 ( .D(DP_OP_168J26_122_4811_n1191), .CK(clk), .SN(n11720),
.Q(n1170) );
DFFSX2TS R_3292 ( .D(DP_OP_168J26_122_4811_n1192), .CK(clk), .SN(n2004), .Q(
n1169) );
DFFSX2TS R_3293 ( .D(Sgf_operation_ODD1_Q_left[24]), .CK(clk), .SN(n11450),
.Q(n1168) );
DFFSX2TS R_3294 ( .D(n11760), .CK(clk), .SN(n11446), .Q(n1167) );
DFFRX2TS R_3295 ( .D(add_x_19_n263), .CK(clk), .RN(n11449), .Q(n1166) );
DFFSX2TS R_3296 ( .D(n11730), .CK(clk), .SN(n11717), .Q(n1165) );
DFFSX2TS R_3297 ( .D(Sgf_operation_ODD1_Q_left[17]), .CK(clk), .SN(n9663),
.Q(n1164) );
DFFSX2TS R_3298 ( .D(Sgf_operation_ODD1_Q_left[23]), .CK(clk), .SN(n11981),
.Q(n1163) );
DFFSX2TS R_3299 ( .D(Sgf_operation_ODD1_Q_left[21]), .CK(clk), .SN(n11450),
.Q(n1162) );
DFFRX2TS R_3300 ( .D(n3311), .CK(clk), .RN(n11447), .Q(n1161) );
DFFSX2TS R_3301 ( .D(Sgf_operation_ODD1_Q_left[19]), .CK(clk), .SN(n9663),
.Q(n1160) );
DFFSX2TS R_3302 ( .D(DP_OP_168J26_122_4811_n543), .CK(clk), .SN(n11722), .Q(
n1159), .QN(n1158) );
DFFSX2TS R_3303 ( .D(DP_OP_168J26_122_4811_n525), .CK(clk), .SN(n11720), .Q(
n1157) );
DFFSX2TS R_3304 ( .D(DP_OP_168J26_122_4811_n254), .CK(clk), .SN(n11714), .Q(
n1156) );
DFFSX2TS R_3305 ( .D(Sgf_operation_ODD1_Q_right[52]), .CK(clk), .SN(n11456),
.Q(n1155) );
DFFSX2TS R_3306 ( .D(Sgf_operation_ODD1_Q_right[53]), .CK(clk), .SN(n11451),
.Q(n1154) );
DFFSX2TS R_3307 ( .D(Sgf_operation_ODD1_Q_right[51]), .CK(clk), .SN(n11456),
.Q(n1153) );
DFFSX2TS R_3308 ( .D(Sgf_operation_ODD1_Q_right[46]), .CK(clk), .SN(n11455),
.Q(n1152) );
DFFSX2TS R_3309 ( .D(add_x_19_n733), .CK(clk), .SN(n11979), .Q(n1151) );
DFFRX2TS R_3310 ( .D(add_x_19_n130), .CK(clk), .RN(n11445), .Q(n1150), .QN(
n989) );
DFFRX2TS R_3311 ( .D(add_x_19_n165), .CK(clk), .RN(n11448), .Q(n1149), .QN(
n1148) );
DFFSX2TS R_3312 ( .D(DP_OP_168J26_122_4811_n1030), .CK(clk), .SN(n11722),
.Q(n1147) );
DFFRX2TS R_3313 ( .D(add_x_19_n239), .CK(clk), .RN(n11449), .Q(n1146) );
DFFSX2TS R_3314 ( .D(DP_OP_168J26_122_4811_n1079), .CK(clk), .SN(n11977),
.Q(n1145) );
DFFRX2TS R_3315 ( .D(add_x_19_n213), .CK(clk), .RN(n11449), .Q(n1144) );
DFFRX2TS R_3316 ( .D(add_x_19_n108), .CK(clk), .RN(n11448), .Q(n1143), .QN(
n1142) );
DFFSX2TS R_3317 ( .D(n11312), .CK(clk), .SN(n1023), .Q(n1141) );
DFFSX2TS R_3318 ( .D(n1978), .CK(clk), .SN(n1023), .Q(n1140) );
DFFSX2TS R_3319 ( .D(n1977), .CK(clk), .SN(n11978), .Q(n1139) );
DFFSX2TS R_3320 ( .D(n1797), .CK(clk), .SN(n11720), .Q(n1138), .QN(n1137) );
DFFSX2TS R_3321 ( .D(DP_OP_168J26_122_4811_n743), .CK(clk), .SN(n2004), .Q(
n1136) );
DFFSX2TS R_3322 ( .D(DP_OP_168J26_122_4811_n1222), .CK(clk), .SN(n11448),
.Q(n1135) );
DFFSX2TS R_3323 ( .D(DP_OP_168J26_122_4811_n285), .CK(clk), .SN(n11717), .Q(
n1134) );
DFFRX2TS R_3324 ( .D(add_x_19_n289), .CK(clk), .RN(n11449), .Q(n1133) );
DFFSX2TS R_3325 ( .D(Sgf_operation_ODD1_Q_right[45]), .CK(clk), .SN(n11456),
.Q(n1132) );
DFFSX2TS R_3326 ( .D(n1021), .CK(clk), .SN(n12227), .Q(n1131) );
DFFSX2TS R_3327 ( .D(Sgf_operation_ODD1_Q_left[0]), .CK(clk), .SN(n11452),
.Q(n1130) );
DFFSX2TS R_3328 ( .D(DP_OP_168J26_122_4811_n654), .CK(clk), .SN(n11720), .Q(
n1129) );
DFFRX2TS R_3329 ( .D(DP_OP_168J26_122_4811_n564), .CK(clk), .RN(n11726), .Q(
n1128) );
DFFRX2TS R_3330 ( .D(add_x_19_n745), .CK(clk), .RN(n11454), .Q(n1127) );
DFFRX2TS R_3332 ( .D(add_x_19_n189), .CK(clk), .RN(n11444), .Q(n1124) );
DFFSX2TS R_3333 ( .D(DP_OP_168J26_122_4811_n1106), .CK(clk), .SN(n11722),
.Q(n1123) );
DFFSX2TS R_3334 ( .D(Sgf_operation_ODD1_Q_left[32]), .CK(clk), .SN(n11446),
.Q(n1122), .QN(n1121) );
DFFSX2TS R_3335 ( .D(add_x_19_n734), .CK(clk), .SN(n11455), .Q(n1120) );
DFFSX2TS R_3336 ( .D(add_x_19_n738), .CK(clk), .SN(n11453), .Q(n1119), .QN(
n1118) );
DFFSX2TS R_3337 ( .D(DP_OP_168J26_122_4811_n745), .CK(clk), .SN(n11455), .Q(
n1117) );
DFFSX2TS R_3338 ( .D(DP_OP_168J26_122_4811_n514), .CK(clk), .SN(n11720), .Q(
n1116) );
DFFRX4TS DP_OP_168J26_122_4811_R_2751 ( .D(DP_OP_168J26_122_4811_n1080),
.CK(clk), .RN(n11719), .Q(n11605) );
DFFSX4TS DP_OP_168J26_122_4811_R_3164 ( .D(n11682), .CK(clk), .SN(n11705),
.Q(DP_OP_168J26_122_4811_n3258) );
DFFSX2TS R_2995 ( .D(n12382), .CK(clk), .SN(n9664), .Q(n12055) );
DFFRXLTS add_x_19_R_2443 ( .D(add_x_19_n68), .CK(clk), .RN(n11454), .Q(
n11398) );
DFFSX1TS add_x_19_R_1682 ( .D(Sgf_operation_ODD1_Q_left[8]), .CK(clk), .SN(
n11451), .Q(n11370) );
DFFSX2TS DP_OP_168J26_122_4811_R_2832 ( .D(DP_OP_168J26_122_4811_n137), .CK(
clk), .SN(n11977), .Q(n11625) );
DFFRHQX2TS DP_OP_168J26_122_4811_R_3140_IP ( .D(n632), .CK(clk), .RN(n1828),
.Q(n11777) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_2622 ( .D(n694), .CK(clk), .RN(n1956),
.Q(n964) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_2560 ( .D(n633), .CK(clk), .RN(n11703),
.Q(n951) );
DFFRX4TS DP_OP_168J26_122_4811_R_741 ( .D(n11474), .CK(clk), .RN(n11708),
.Q(DP_OP_168J26_122_4811_n6586) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_2565 ( .D(n600), .CK(clk), .RN(n11703),
.Q(n944) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_934 ( .D(n9729), .CK(clk), .RN(n11707),
.Q(n931) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_3145 ( .D(n688), .CK(clk), .RN(n11708),
.Q(n927) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_3173 ( .D(n1441), .CK(clk), .RN(n1957),
.Q(n925) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_3070 ( .D(n670), .CK(clk), .RN(n11994),
.Q(n1238) );
DFFRX1TS R_3331 ( .D(DP_OP_168J26_122_4811_n365), .CK(clk), .RN(n11455), .Q(
n1126), .QN(n1125) );
DFFRX1TS DP_OP_168J26_122_4811_R_3037 ( .D(DP_OP_168J26_122_4811_n543), .CK(
clk), .RN(n11716), .Q(n11664) );
DFFSX2TS DP_OP_168J26_122_4811_R_3036 ( .D(DP_OP_168J26_122_4811_n768), .CK(
clk), .SN(n11981), .Q(n11663) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_3087 ( .D(n586), .CK(clk), .RN(n12235),
.Q(n882) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_917 ( .D(n587), .CK(clk), .RN(n11697),
.Q(n878) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_915 ( .D(n12137), .CK(clk), .RN(n11708),
.Q(n868) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_3074 ( .D(n665), .CK(clk), .RN(n11994),
.Q(n865) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_856 ( .D(n620), .CK(clk), .RN(n11700),
.Q(n863) );
DFFRHQX2TS Operands_load_reg_YMRegister_Q_reg_43_ ( .D(n625), .CK(clk), .RN(
n12232), .Q(n857) );
DFFSX2TS add_x_19_R_3026_RW_0 ( .D(add_x_19_n703), .CK(clk), .SN(n2008),
.QN(n11459) );
DFFRX4TS DP_OP_168J26_122_4811_R_2436 ( .D(n672), .CK(clk), .RN(n11710), .Q(
DP_OP_168J26_122_4811_n3227), .QN(n11786) );
DFFRX4TS DP_OP_168J26_122_4811_R_1252 ( .D(n11521), .CK(clk), .RN(n11986),
.Q(DP_OP_168J26_122_4811_n8200) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_2127 ( .D(n626), .CK(clk), .RN(n11701),
.Q(n1257) );
DFFSX4TS DP_OP_168J26_122_4811_R_2887 ( .D(DP_OP_168J26_122_4811_n1455),
.CK(clk), .SN(n11721), .Q(n11640) );
DFFSX2TS DP_OP_168J26_122_4811_R_2863 ( .D(DP_OP_168J26_122_4811_n591), .CK(
clk), .SN(n11715), .Q(n11633) );
DFFRHQX4TS DP_OP_168J26_122_4811_R_845 ( .D(n668), .CK(clk), .RN(n11972),
.Q(n1716) );
DFFRHQX4TS DP_OP_168J26_122_4811_R_2573 ( .D(n662), .CK(clk), .RN(n11707),
.Q(n1294) );
DFFSX2TS DP_OP_168J26_122_4811_R_1262 ( .D(n11513), .CK(clk), .SN(n1830),
.Q(DP_OP_168J26_122_4811_n3590), .QN(n11750) );
DFFRHQX4TS DP_OP_168J26_122_4811_R_2261 ( .D(n594), .CK(clk), .RN(n11700),
.Q(n955) );
DFFRHQX4TS DP_OP_168J26_122_4811_R_549 ( .D(n652), .CK(clk), .RN(n12228),
.Q(n1262) );
DFFRHQX2TS DP_OP_168J26_122_4811_R_1264 ( .D(n11522), .CK(clk), .RN(n1830),
.Q(DP_OP_168J26_122_4811_n3579) );
DFFSX2TS DP_OP_168J26_122_4811_R_2215 ( .D(n11558), .CK(clk), .SN(n11702),
.Q(DP_OP_168J26_122_4811_n3445), .QN(n11775) );
DFFRX2TS DP_OP_168J26_122_4811_R_3108 ( .D(n11672), .CK(clk), .RN(n11700),
.QN(n1362) );
DFFRHQX4TS DP_OP_168J26_122_4811_R_3097 ( .D(n9666), .CK(clk), .RN(n12242),
.Q(n922) );
DFFRHQX4TS DP_OP_168J26_122_4811_R_923 ( .D(n684), .CK(clk), .RN(n11712),
.Q(n1684) );
DFFRHQX1TS DP_OP_168J26_122_4811_R_3088_IP ( .D(n10269), .CK(clk), .RN(n1829), .Q(n11742) );
DFFSHQX2TS DP_OP_168J26_122_4811_R_3098 ( .D(n11462), .CK(clk), .SN(n11709),
.Q(n1275) );
DFFSX1TS DP_OP_168J26_122_4811_R_2980 ( .D(DP_OP_168J26_122_4811_n1320),
.CK(clk), .SN(n11726), .QN(n11693) );
DFFRHQX2TS DP_OP_168J26_122_4811_R_3109_IP ( .D(n11335), .CK(clk), .RN(n1827), .Q(n11751) );
DFFRX2TS DP_OP_168J26_122_4811_R_3136 ( .D(n632), .CK(clk), .RN(n11703), .Q(
DP_OP_168J26_122_4811_n8469), .QN(n1410) );
DFFRX1TS DP_OP_168J26_122_4811_R_3155 ( .D(DP_OP_168J26_122_4811_n1285),
.CK(clk), .RN(n11726), .Q(n11679) );
DFFSX2TS DP_OP_168J26_122_4811_R_3014 ( .D(DP_OP_168J26_122_4811_n984), .CK(
clk), .SN(n11719), .Q(n11659) );
DFFRHQX4TS DP_OP_168J26_122_4811_R_3163 ( .D(n12139), .CK(clk), .RN(n11712),
.Q(n1333) );
DFFRHQX8TS DP_OP_168J26_122_4811_R_866 ( .D(n618), .CK(clk), .RN(n11701),
.Q(n916) );
DFFSX1TS DP_OP_168J26_122_4811_R_3002 ( .D(DP_OP_168J26_122_4811_n303), .CK(
clk), .SN(n11722), .Q(n11653) );
DFFSX1TS DP_OP_168J26_122_4811_R_3001 ( .D(n11734), .CK(clk), .SN(n11721),
.Q(n11652) );
DFFRX2TS DP_OP_168J26_122_4811_R_2558 ( .D(n633), .CK(clk), .RN(n11703), .Q(
DP_OP_168J26_122_4811_n8163) );
DFFSX1TS DP_OP_168J26_122_4811_R_2868 ( .D(DP_OP_168J26_122_4811_n172), .CK(
clk), .SN(n11447), .Q(n11636) );
DFFRX2TS DP_OP_168J26_122_4811_R_2953 ( .D(DP_OP_168J26_122_4811_n638), .CK(
clk), .RN(n11723), .Q(n11646) );
DFFSX1TS add_x_19_R_2774 ( .D(n1293), .CK(clk), .SN(n11453), .Q(n11413) );
DFFSX1TS DP_OP_168J26_122_4811_R_2848 ( .D(n1014), .CK(clk), .SN(n11982),
.Q(n11629) );
DFFSX2TS R_3268 ( .D(DP_OP_168J26_122_4811_n626), .CK(clk), .SN(n12222), .Q(
n1196) );
DFFRX1TS DP_OP_168J26_122_4811_R_2805 ( .D(DP_OP_168J26_122_4811_n776), .CK(
clk), .RN(n11724), .Q(n11609) );
DFFRX1TS DP_OP_168J26_122_4811_R_2688 ( .D(n10108), .CK(clk), .RN(n11714),
.Q(n11595) );
DFFRXLTS add_x_19_R_1733 ( .D(Sgf_operation_ODD1_Q_left[3]), .CK(clk), .RN(
n11456), .Q(n11373) );
DFFSX1TS DP_OP_168J26_122_4811_R_2687 ( .D(DP_OP_168J26_122_4811_n183), .CK(
clk), .SN(n11714), .Q(n11594) );
DFFSX1TS add_x_19_R_2393_RW_0 ( .D(Sgf_operation_ODD1_Q_right[43]), .CK(clk),
.SN(n11452), .Q(n11396) );
DFFSX1TS add_x_19_R_2563 ( .D(Sgf_operation_ODD1_Q_right[44]), .CK(clk),
.SN(n11451), .Q(n11403) );
DFFSX1TS add_x_19_R_2531 ( .D(Sgf_operation_ODD1_Q_right[41]), .CK(clk),
.SN(n11455), .Q(n11401) );
DFFSX1TS DP_OP_168J26_122_4811_R_2717 ( .D(n2957), .CK(clk), .SN(n11714),
.Q(n11600) );
DFFSX1TS DP_OP_168J26_122_4811_R_1990 ( .D(DP_OP_168J26_122_4811_n265), .CK(
clk), .SN(n11446), .Q(n11554) );
DFFSX1TS DP_OP_168J26_122_4811_R_1743 ( .D(n10205), .CK(clk), .SN(n11716),
.Q(n11540) );
DFFSX1TS DP_OP_168J26_122_4811_R_1747 ( .D(DP_OP_168J26_122_4811_n95), .CK(
clk), .SN(n9664), .Q(n11542) );
DFFSX1TS add_x_19_R_3018 ( .D(Sgf_operation_ODD1_Q_left[37]), .CK(clk), .SN(
n11446), .Q(n11438) );
DFFRXLTS add_x_19_R_1839 ( .D(Sgf_operation_ODD1_Q_left[5]), .CK(clk), .RN(
n11456), .Q(n11378) );
DFFSX1TS add_x_19_R_1775_RW_0 ( .D(Sgf_operation_ODD1_Q_left[3]), .CK(clk),
.SN(n11456), .Q(n11375) );
DFFSX1TS add_x_19_R_2351_RW_0 ( .D(Sgf_operation_ODD1_Q_right[48]), .CK(clk),
.SN(n11450), .Q(n11395) );
DFFRXLTS add_x_19_R_1590 ( .D(Sgf_operation_ODD1_Q_left[29]), .CK(clk), .RN(
n11450), .Q(n11369) );
DFFSX1TS DP_OP_168J26_122_4811_R_1751 ( .D(DP_OP_168J26_122_4811_n99), .CK(
clk), .SN(n11714), .Q(n11544) );
DFFSX1TS DP_OP_168J26_122_4811_R_1753 ( .D(DP_OP_168J26_122_4811_n97), .CK(
clk), .SN(n11714), .Q(n11545) );
DFFSX1TS DP_OP_168J26_122_4811_R_1745 ( .D(DP_OP_168J26_122_4811_n101), .CK(
clk), .SN(n11716), .Q(n11541) );
DFFSX1TS DP_OP_168J26_122_4811_R_1749 ( .D(DP_OP_168J26_122_4811_n98), .CK(
clk), .SN(n11714), .Q(n11543) );
DFFSX1TS DP_OP_168J26_122_4811_R_1620 ( .D(DP_OP_168J26_122_4811_n107), .CK(
clk), .SN(n11978), .Q(n11536) );
DFFRX2TS Sel_B_Q_reg_0_ ( .D(n419), .CK(clk), .RN(n12234), .Q(
FSM_selector_B[0]), .QN(n11821) );
DFFSX1TS add_x_19_R_1726_RW_0 ( .D(Sgf_operation_ODD1_Q_left[9]), .CK(clk),
.SN(n11452), .Q(n11371) );
DFFSX1TS add_x_19_R_1412_RW_1 ( .D(Sgf_operation_ODD1_Q_left[13]), .CK(clk),
.SN(n11451), .Q(n11354) );
DFFSX1TS add_x_19_R_1444 ( .D(Sgf_operation_ODD1_Q_left[27]), .CK(clk), .SN(
n1012), .Q(n11357) );
DFFSX1TS add_x_19_R_1384 ( .D(Sgf_operation_ODD1_Q_left[26]), .CK(clk), .SN(
n1012), .Q(n11351) );
DFFSHQX1TS Operands_load_reg_XMRegister_Q_reg_55_ ( .D(n11336), .CK(clk),
.SN(n1828), .Q(n11829) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_58_ ( .D(n640), .CK(clk), .RN(
n1829), .Q(Op_MY[58]), .QN(n11789) );
DFFSX2TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n3323), .CK(clk), .SN(n1829),
.Q(n11796), .QN(exp_oper_result[0]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_53_ ( .D(n699), .CK(clk), .RN(
n1956), .Q(Op_MX[53]), .QN(n11831) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_52_ ( .D(n698), .CK(clk), .RN(
n1956), .Q(Op_MX[52]), .QN(n11832) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_56_ ( .D(n702), .CK(clk), .RN(
n1956), .Q(Op_MX[56]), .QN(n11828) );
DFFSX1TS add_x_19_R_3013 ( .D(Sgf_operation_ODD1_Q_left[49]), .CK(clk), .SN(
n1012), .Q(n11435) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_60_ ( .D(n642), .CK(clk), .RN(
n12231), .Q(Op_MY[60]), .QN(n11801) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_61_ ( .D(n643), .CK(clk), .RN(
n12231), .Q(Op_MY[61]), .QN(n11800) );
DFFRXLTS add_x_19_R_2853 ( .D(n11460), .CK(clk), .RN(n11454), .Q(n11417) );
DFFSX1TS R_3131 ( .D(n12324), .CK(clk), .SN(n12001), .Q(n12039) );
DFFSX1TS add_x_19_R_2595 ( .D(add_x_19_n747), .CK(clk), .SN(n11451), .Q(
n11404) );
DFFSX1TS add_x_19_R_2783 ( .D(add_x_19_n718), .CK(clk), .SN(n11453), .Q(
n11416) );
DFFSX1TS R_2937 ( .D(n12352), .CK(clk), .SN(n1975), .Q(n12056) );
DFFSX1TS add_x_19_R_2857 ( .D(add_x_19_n830), .CK(clk), .SN(n11453), .Q(
n11420) );
DFFSX1TS R_3239 ( .D(n12374), .CK(clk), .SN(n11992), .Q(n12008) );
DFFSX1TS add_x_19_R_2603 ( .D(add_x_19_n754), .CK(clk), .SN(n11452), .Q(
n11406) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_62_ ( .D(n708), .CK(clk), .RN(
n11974), .Q(Op_MX[62]), .QN(n11823) );
DFFSX1TS R_3101 ( .D(n12342), .CK(clk), .SN(n12001), .Q(n12047) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_59_ ( .D(n705), .CK(clk), .RN(
n11973), .Q(Op_MX[59]), .QN(n11825) );
DFFSX1TS R_3132 ( .D(n12323), .CK(clk), .SN(n12001), .Q(n12038) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_61_ ( .D(n707), .CK(clk), .RN(
n11974), .QN(n12149) );
DFFSX1TS R_3100 ( .D(n12343), .CK(clk), .SN(n12001), .Q(n12048) );
DFFSX1TS R_2936 ( .D(n12353), .CK(clk), .SN(n12001), .Q(n12057) );
DFFSX1TS add_x_19_R_1970 ( .D(Sgf_operation_ODD1_Q_left[50]), .CK(clk), .SN(
n11447), .Q(n11383) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_60_ ( .D(n706), .CK(clk), .RN(
n11973), .Q(Op_MX[60]), .QN(n11824) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n410), .CK(clk), .RN(n1854),
.Q(exp_oper_result[7]), .QN(n12389) );
DFFSX1TS R_3223 ( .D(n12327), .CK(clk), .SN(n12001), .Q(n12024) );
DFFRX2TS Exp_module_exp_result_m_Q_reg_9_ ( .D(n408), .CK(clk), .RN(n11999),
.Q(exp_oper_result[9]), .QN(n12391) );
DFFRXLTS add_x_19_R_2502 ( .D(add_x_19_n69), .CK(clk), .RN(n11454), .Q(
n11399) );
DFFSX1TS add_x_19_R_2429 ( .D(add_x_19_n67), .CK(clk), .SN(n11456), .Q(
n11397) );
DFFSX1TS add_x_19_R_2761 ( .D(add_x_19_n70), .CK(clk), .SN(n11725), .Q(
n11411) );
DFFSX1TS R_2894 ( .D(n12304), .CK(clk), .SN(n11988), .Q(n12097) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n355), .CK(clk),
.RN(n12236), .Q(Sgf_normalized_result[2]) );
DFFRXLTS R_2118 ( .D(n453), .CK(clk), .RN(n12225), .Q(n12118) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_11_ ( .D(n406), .CK(clk), .RN(n1867),
.Q(exp_oper_result[11]), .QN(n11886) );
DFFRX2TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n526), .CK(clk), .RN(
n11972), .Q(FSM_add_overflow_flag), .QN(n11803) );
DFFSX1TS R_1471_RW_0 ( .D(n11822), .CK(clk), .SN(n12227), .Q(n12128) );
DFFRX1TS R_3113 ( .D(n602), .CK(clk), .RN(n12000), .Q(Op_MY[20]), .QN(n11916) );
DFFRX2TS R_560 ( .D(n1355), .CK(clk), .RN(n11986), .Q(n12209), .QN(n11924)
);
DFFRX2TS R_1955 ( .D(n595), .CK(clk), .RN(n12233), .QN(n11966) );
DFFRX2TS Sel_C_Q_reg_0_ ( .D(n709), .CK(clk), .RN(n1974), .Q(FSM_selector_C),
.QN(n11833) );
DFFRXLTS R_712 ( .D(n677), .CK(clk), .RN(n12238), .Q(Op_MX[31]), .QN(n11906)
);
DFFRXLTS R_536 ( .D(n650), .CK(clk), .RN(n12231), .Q(Op_MX[4]), .QN(n11911)
);
DFFRX1TS R_775 ( .D(n9733), .CK(clk), .RN(n1854), .QN(n11788) );
DFFRXLTS R_563 ( .D(n583), .CK(clk), .RN(n12234), .Q(Op_MY[1]), .QN(n11897)
);
DFFRXLTS R_735 ( .D(n584), .CK(clk), .RN(n12234), .Q(Op_MY[2]), .QN(n11958)
);
DFFRX1TS R_739 ( .D(n660), .CK(clk), .RN(n972), .Q(Op_MX[14]), .QN(n11920)
);
DFFRX1TS R_751 ( .D(n614), .CK(clk), .RN(n11997), .QN(n11951) );
DFFRX1TS R_1306 ( .D(n646), .CK(clk), .RN(n2006), .Q(Op_MX[0]), .QN(n11960)
);
DFFRXLTS R_546 ( .D(n652), .CK(clk), .RN(n12231), .Q(Op_MX[6]), .QN(n11923)
);
DFFRX1TS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n405), .CK(clk), .RN(n12234),
.Q(Exp_module_Overflow_flag_A) );
DFFRX2TS R_840 ( .D(n648), .CK(clk), .RN(n2006), .Q(Op_MX[2]), .QN(n11902)
);
DFFSX1TS R_101 ( .D(n12380), .CK(clk), .SN(n11976), .Q(n12175) );
DFFRHQX2TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n569), .CK(clk), .RN(n1829), .Q(Add_result[10]) );
DFFRXLTS add_x_19_R_179 ( .D(add_x_19_n322), .CK(clk), .RN(n11450), .Q(
n11349) );
DFFSX1TS R_38 ( .D(n12268), .CK(clk), .SN(n11985), .Q(n12197) );
DFFSX1TS R_39 ( .D(n3290), .CK(clk), .SN(n11985), .Q(n12196) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n562), .CK(clk), .RN(n12229),
.Q(Add_result[17]), .QN(n11871) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n572), .CK(clk), .RN(n12230),
.Q(Add_result[7]), .QN(n11880) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_52_ ( .D(n527), .CK(clk), .RN(n972),
.Q(Add_result[52]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_46_ ( .D(n533), .CK(clk), .RN(n12231),
.Q(Add_result[46]), .QN(n11845) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_40_ ( .D(n539), .CK(clk), .RN(n12395),
.Q(Add_result[40]), .QN(n11851) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_39_ ( .D(n540), .CK(clk), .RN(n970),
.Q(Add_result[39]), .QN(n11852) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_34_ ( .D(n545), .CK(clk), .RN(n11698),
.Q(Add_result[34]), .QN(n11857) );
CLKINVX2TS U746 ( .A(n969), .Y(n971) );
CLKINVX2TS U747 ( .A(n969), .Y(n972) );
NAND2X2TS U748 ( .A(n9634), .B(n11460), .Y(add_x_19_n70) );
OR2X6TS U749 ( .A(n9994), .B(n9995), .Y(n11761) );
OR2X6TS U750 ( .A(n9627), .B(n9626), .Y(n11460) );
BUFX3TS U751 ( .A(n10949), .Y(n11097) );
BUFX3TS U752 ( .A(n10949), .Y(n11071) );
INVX6TS U753 ( .A(n3098), .Y(n9637) );
NAND2X1TS U754 ( .A(n10221), .B(n10220), .Y(n10222) );
INVX2TS U755 ( .A(n2779), .Y(n10032) );
INVX2TS U756 ( .A(n1356), .Y(n12216) );
BUFX3TS U757 ( .A(n10029), .Y(n938) );
NAND2X6TS U758 ( .A(n10007), .B(n2351), .Y(DP_OP_168J26_122_4811_n588) );
NOR2X4TS U759 ( .A(n10004), .B(n10023), .Y(DP_OP_168J26_122_4811_n613) );
BUFX8TS U760 ( .A(n2291), .Y(n1528) );
INVX4TS U761 ( .A(n11251), .Y(n2011) );
INVX4TS U762 ( .A(n11251), .Y(n11290) );
INVX4TS U763 ( .A(n3290), .Y(n2138) );
MXI2X2TS U764 ( .A(n10300), .B(n11967), .S0(n10299), .Y(n589) );
INVX2TS U765 ( .A(n1431), .Y(n11286) );
INVX2TS U766 ( .A(n1431), .Y(n11288) );
NAND2X2TS U767 ( .A(n10181), .B(n10180), .Y(n10182) );
NAND2X1TS U768 ( .A(n1835), .B(n486), .Y(n10743) );
NAND2X1TS U769 ( .A(n10882), .B(n490), .Y(n10805) );
NAND2XLTS U770 ( .A(n10235), .B(n10234), .Y(n10236) );
NAND2XLTS U771 ( .A(n10210), .B(n10209), .Y(n10211) );
NAND2XLTS U772 ( .A(n10057), .B(n10056), .Y(n10058) );
BUFX3TS U773 ( .A(n11126), .Y(n11068) );
NAND2XLTS U774 ( .A(n10177), .B(n10176), .Y(n10178) );
NAND2X1TS U775 ( .A(n1834), .B(n479), .Y(n10718) );
NAND2X1TS U776 ( .A(n1835), .B(n483), .Y(n10761) );
AOI21X2TS U777 ( .A0(n485), .A1(n10674), .B0(n2224), .Y(n2223) );
NAND2XLTS U778 ( .A(n10151), .B(n10150), .Y(n10152) );
AOI21X2TS U779 ( .A0(n10174), .A1(n10173), .B0(n10172), .Y(n10179) );
NAND2XLTS U780 ( .A(n10158), .B(n10157), .Y(n10159) );
INVX6TS U781 ( .A(n2615), .Y(n10030) );
INVX2TS U782 ( .A(n10122), .Y(n10106) );
BUFX4TS U783 ( .A(n10949), .Y(n11329) );
NAND2X1TS U784 ( .A(n10228), .B(n10227), .Y(n10229) );
NAND2XLTS U785 ( .A(n10129), .B(n10128), .Y(n10130) );
NAND2XLTS U786 ( .A(n8718), .B(n8719), .Y(n8720) );
NAND2XLTS U787 ( .A(n8386), .B(n8385), .Y(n8387) );
NAND2XLTS U788 ( .A(n9561), .B(n9560), .Y(n9562) );
NAND2XLTS U789 ( .A(n10248), .B(n10247), .Y(n10249) );
NAND2XLTS U790 ( .A(n10242), .B(n10241), .Y(n10243) );
NAND2X2TS U791 ( .A(n10109), .B(n10123), .Y(DP_OP_168J26_122_4811_n172) );
INVX4TS U792 ( .A(n9624), .Y(n9586) );
NAND2XLTS U793 ( .A(n9044), .B(n10074), .Y(n9045) );
NAND2XLTS U794 ( .A(n10096), .B(n10095), .Y(n10097) );
CLKBUFX2TS U795 ( .A(n10949), .Y(n11037) );
NAND2X6TS U796 ( .A(n2707), .B(n2706), .Y(n11759) );
CLKBUFX3TS U797 ( .A(n10760), .Y(n2007) );
INVX2TS U798 ( .A(n11991), .Y(n969) );
XNOR2X2TS U799 ( .A(n9495), .B(n9494), .Y(n9588) );
INVX1TS U800 ( .A(n2237), .Y(n10039) );
NAND2X2TS U801 ( .A(n1836), .B(n480), .Y(n10689) );
NAND2X1TS U802 ( .A(n10998), .B(n2533), .Y(n10999) );
OA21X2TS U803 ( .A0(n2702), .A1(n1470), .B0(n1426), .Y(n1350) );
NAND2X4TS U804 ( .A(n2807), .B(n9295), .Y(n9297) );
INVX2TS U805 ( .A(n10092), .Y(n8717) );
NAND2X1TS U806 ( .A(n9493), .B(n9492), .Y(n9494) );
INVX2TS U807 ( .A(n9951), .Y(n1264) );
INVX6TS U808 ( .A(n8429), .Y(n2528) );
OAI21X2TS U809 ( .A0(n11009), .A1(n11008), .B0(n2533), .Y(n11014) );
BUFX4TS U810 ( .A(n10028), .Y(n2615) );
BUFX4TS U811 ( .A(n10681), .Y(n10803) );
CLKINVX3TS U812 ( .A(n3163), .Y(n9308) );
NAND2X1TS U813 ( .A(n3108), .B(n9632), .Y(n9495) );
BUFX6TS U814 ( .A(n1431), .Y(n11251) );
CLKBUFX3TS U815 ( .A(n10681), .Y(n10674) );
CLKINVX2TS U816 ( .A(n10125), .Y(n10126) );
NAND2XLTS U817 ( .A(n1367), .B(n8421), .Y(n7554) );
NAND2XLTS U818 ( .A(n9053), .B(n9052), .Y(n9054) );
NAND2X4TS U819 ( .A(n8307), .B(n8308), .Y(n10024) );
BUFX3TS U820 ( .A(n10682), .Y(n10870) );
INVX2TS U821 ( .A(Data_MY[50]), .Y(n9720) );
BUFX3TS U822 ( .A(n10682), .Y(n10860) );
NAND2XLTS U823 ( .A(n7976), .B(n7975), .Y(n7977) );
NAND2XLTS U824 ( .A(n5486), .B(n8183), .Y(n5487) );
NAND2XLTS U825 ( .A(n8427), .B(n8426), .Y(n8428) );
NAND2XLTS U826 ( .A(n6399), .B(n7527), .Y(n6400) );
NAND2XLTS U827 ( .A(n8393), .B(n7573), .Y(n7574) );
NAND2XLTS U828 ( .A(n8328), .B(n8326), .Y(n7560) );
NAND2XLTS U829 ( .A(n7565), .B(n7564), .Y(n7566) );
CLKBUFX2TS U830 ( .A(n11974), .Y(n11991) );
NAND2X6TS U831 ( .A(n3189), .B(n9808), .Y(n3188) );
NOR2X2TS U832 ( .A(n11018), .B(n11017), .Y(n10620) );
AND2X4TS U833 ( .A(n10088), .B(n9563), .Y(n2888) );
ADDFHX2TS U834 ( .A(n10013), .B(n10012), .CI(n10011), .CO(n10022), .S(n9766)
);
CLKINVX6TS U835 ( .A(n8714), .Y(n2706) );
XOR2X1TS U836 ( .A(n2370), .B(n10045), .Y(n2369) );
AND2X4TS U837 ( .A(n10088), .B(n2869), .Y(n1429) );
CLKAND2X2TS U838 ( .A(n9631), .B(n2587), .Y(n1373) );
BUFX3TS U839 ( .A(n10682), .Y(n10760) );
AOI21X1TS U840 ( .A0(n2676), .A1(n10983), .B0(n10982), .Y(n10987) );
INVX2TS U841 ( .A(n9901), .Y(n1668) );
INVX4TS U842 ( .A(n1356), .Y(n11270) );
INVX4TS U843 ( .A(n1356), .Y(n11281) );
NAND2XLTS U844 ( .A(n8334), .B(n8333), .Y(n8335) );
NAND2XLTS U845 ( .A(n8348), .B(n8347), .Y(n8349) );
NAND2XLTS U846 ( .A(n9572), .B(n9571), .Y(n9573) );
AOI21X1TS U847 ( .A0(n2676), .A1(n10991), .B0(n1790), .Y(n10996) );
NAND2X2TS U848 ( .A(n1009), .B(n8382), .Y(n8384) );
NAND2XLTS U849 ( .A(n9503), .B(n9502), .Y(n9504) );
CLKINVX6TS U850 ( .A(n10804), .Y(n1835) );
NAND3X4TS U851 ( .A(n10101), .B(n1014), .C(n10036), .Y(n3179) );
INVX4TS U852 ( .A(n10804), .Y(n1821) );
INVX4TS U853 ( .A(n10804), .Y(n1836) );
INVX4TS U854 ( .A(n10804), .Y(n1834) );
NAND2X2TS U855 ( .A(n10124), .B(n10129), .Y(n10117) );
CMPR32X2TS U856 ( .A(n10200), .B(n10199), .C(n10198), .CO(n10204), .S(n10180) );
NOR2X2TS U857 ( .A(n2874), .B(n1397), .Y(n2873) );
INVX16TS U858 ( .A(n2767), .Y(n1468) );
BUFX16TS U859 ( .A(n11139), .Y(n9724) );
OAI21X1TS U860 ( .A0(n2016), .A1(n9407), .B0(n9408), .Y(n8837) );
NAND2X4TS U861 ( .A(n10092), .B(n10085), .Y(n2875) );
BUFX16TS U862 ( .A(n11139), .Y(n9718) );
OAI21X1TS U863 ( .A0(n2016), .A1(n10771), .B0(n10772), .Y(n8812) );
INVX2TS U864 ( .A(n9758), .Y(n10174) );
BUFX3TS U865 ( .A(n9899), .Y(n1769) );
NOR2X6TS U866 ( .A(n9485), .B(n9486), .Y(n10026) );
INVX2TS U867 ( .A(n9745), .Y(n10193) );
INVX2TS U868 ( .A(n10622), .Y(n11114) );
CLKBUFX2TS U869 ( .A(n3275), .Y(n2576) );
AO21X1TS U870 ( .A0(n10079), .A1(n10078), .B0(n10077), .Y(n1386) );
INVX2TS U871 ( .A(n10115), .Y(n10129) );
BUFX12TS U872 ( .A(n2721), .Y(n1465) );
OR2X1TS U873 ( .A(n6566), .B(n2526), .Y(n1796) );
NAND2X1TS U874 ( .A(n10323), .B(n10322), .Y(n10329) );
NOR2X4TS U875 ( .A(n2702), .B(n1105), .Y(n1104) );
INVX6TS U876 ( .A(n3141), .Y(n10101) );
NAND2XLTS U877 ( .A(n9595), .B(n9594), .Y(n9596) );
NAND2XLTS U878 ( .A(n9067), .B(n9066), .Y(n9068) );
NAND2XLTS U879 ( .A(n8810), .B(n8809), .Y(n8811) );
INVX2TS U880 ( .A(n9969), .Y(n1112) );
NAND2XLTS U881 ( .A(n7967), .B(n7968), .Y(n7965) );
NAND2X2TS U882 ( .A(n10344), .B(FS_Module_state_reg[3]), .Y(n10949) );
NAND2X1TS U883 ( .A(n8182), .B(n7427), .Y(n5483) );
INVX2TS U884 ( .A(n10132), .Y(n10151) );
NAND2X1TS U885 ( .A(n10087), .B(n10086), .Y(n1397) );
NAND2X2TS U886 ( .A(n11173), .B(n11798), .Y(n11242) );
NAND2X6TS U887 ( .A(n10028), .B(n10029), .Y(n2679) );
NAND2X1TS U888 ( .A(n9047), .B(n8398), .Y(n8400) );
NAND2XLTS U889 ( .A(n8830), .B(n8829), .Y(n8831) );
NAND2XLTS U890 ( .A(n9435), .B(n9433), .Y(n8836) );
NOR2X4TS U891 ( .A(n2781), .B(n6678), .Y(n3112) );
CLKBUFX3TS U892 ( .A(n8177), .Y(n920) );
OAI21X1TS U893 ( .A0(n10062), .A1(n8213), .B0(n10061), .Y(n10063) );
BUFX3TS U894 ( .A(n10682), .Y(n10946) );
CLKINVX6TS U895 ( .A(n10037), .Y(n1014) );
NOR2X1TS U896 ( .A(n11100), .B(n11102), .Y(n11105) );
INVX2TS U897 ( .A(n10053), .Y(n2808) );
AO21XLTS U898 ( .A0(n10982), .A1(n10985), .B0(n2695), .Y(n1790) );
AOI21X2TS U899 ( .A0(n1033), .A1(n8408), .B0(n8407), .Y(n8409) );
AOI21X2TS U900 ( .A0(n1033), .A1(n7568), .B0(n9048), .Y(n9050) );
NOR2X6TS U901 ( .A(n1013), .B(n2866), .Y(n2865) );
AOI21X2TS U902 ( .A0(n9654), .A1(n1367), .B0(n9576), .Y(n9577) );
INVX2TS U903 ( .A(n9056), .Y(n9058) );
NAND2X2TS U904 ( .A(n10092), .B(n8771), .Y(n2734) );
INVX2TS U905 ( .A(n9293), .Y(n9295) );
CLKAND2X4TS U906 ( .A(n1009), .B(n8376), .Y(n3276) );
AOI21X2TS U907 ( .A0(n9654), .A1(n9647), .B0(n9652), .Y(n7603) );
INVX1TS U908 ( .A(n10788), .Y(n3152) );
AOI21X1TS U909 ( .A0(n5478), .A1(n7427), .B0(n5481), .Y(n5482) );
XOR2X2TS U910 ( .A(n10571), .B(n10570), .Y(n11125) );
CLKXOR2X2TS U911 ( .A(n3065), .B(n3061), .Y(n9584) );
NAND2X2TS U912 ( .A(n9648), .B(n9499), .Y(n9501) );
INVX16TS U913 ( .A(n2975), .Y(n3163) );
NOR2X2TS U914 ( .A(n9046), .B(n8389), .Y(n7570) );
OAI21X1TS U915 ( .A0(n8406), .A1(n8389), .B0(n8391), .Y(n7569) );
INVX6TS U916 ( .A(n1050), .Y(n9848) );
NAND2X4TS U917 ( .A(n7008), .B(n7009), .Y(n10031) );
INVX4TS U918 ( .A(n7525), .Y(n9047) );
INVX2TS U919 ( .A(n8376), .Y(n10060) );
AND4X1TS U920 ( .A(n11214), .B(n11813), .C(n11969), .D(n11793), .Y(n11217)
);
INVX6TS U921 ( .A(n2807), .Y(n1013) );
CLKINVX6TS U922 ( .A(n10477), .Y(n11077) );
NOR2X1TS U923 ( .A(n9575), .B(n9579), .Y(n8422) );
NAND2X1TS U924 ( .A(n10835), .B(n9071), .Y(n10837) );
NAND2X4TS U925 ( .A(n7420), .B(n7421), .Y(n10037) );
INVX2TS U926 ( .A(n8431), .Y(n8798) );
NAND2XLTS U927 ( .A(n8368), .B(n8367), .Y(n8369) );
NAND2XLTS U928 ( .A(n9441), .B(n9440), .Y(n9442) );
NAND2X6TS U929 ( .A(n813), .B(n812), .Y(n9277) );
NAND2X2TS U930 ( .A(n8700), .B(n8701), .Y(n1474) );
INVX2TS U931 ( .A(n7524), .Y(n7565) );
INVX2TS U932 ( .A(n7559), .Y(n8328) );
CLKAND2X2TS U933 ( .A(n9289), .B(n9288), .Y(n1388) );
INVX6TS U934 ( .A(n2016), .Y(n2618) );
NAND2X1TS U935 ( .A(n10952), .B(n10951), .Y(n11174) );
NAND2XLTS U936 ( .A(n10751), .B(n10750), .Y(n10752) );
NAND2XLTS U937 ( .A(n9402), .B(n9401), .Y(n9403) );
NAND2XLTS U938 ( .A(n8783), .B(n8782), .Y(n8784) );
INVX8TS U939 ( .A(n2778), .Y(n2779) );
NAND2XLTS U940 ( .A(n10695), .B(n10694), .Y(n10696) );
NAND2XLTS U941 ( .A(n8872), .B(n8871), .Y(n8873) );
NOR2X1TS U942 ( .A(n11117), .B(n11116), .Y(n11321) );
NAND2XLTS U943 ( .A(n9518), .B(n9517), .Y(n9519) );
ADDFHX2TS U944 ( .A(n8167), .B(n8165), .CI(n8166), .CO(n8176), .S(n8171) );
NOR2X4TS U945 ( .A(n7964), .B(n1321), .Y(n7971) );
ADDFHX2TS U946 ( .A(n9019), .B(n9018), .CI(n9017), .CO(n9972), .S(n9969) );
NAND2XLTS U947 ( .A(n9549), .B(n9546), .Y(n9525) );
NOR2BX2TS U948 ( .AN(n2321), .B(n9252), .Y(n2320) );
NOR2X2TS U949 ( .A(n9506), .B(n9497), .Y(n9499) );
CLKAND2X2TS U950 ( .A(n8182), .B(n7428), .Y(n1458) );
NOR2X2TS U951 ( .A(n9566), .B(n8338), .Y(n8343) );
NAND2X2TS U952 ( .A(n2064), .B(n9310), .Y(n9312) );
CLKINVX1TS U953 ( .A(n2587), .Y(n3223) );
OAI21X2TS U954 ( .A0(n10667), .A1(n10644), .B0(n10661), .Y(n10647) );
NOR2X2TS U955 ( .A(n8756), .B(n9565), .Y(n10091) );
NAND2X2TS U956 ( .A(n10956), .B(n9606), .Y(n9608) );
AOI21X1TS U957 ( .A0(n8826), .A1(n8830), .B0(n8816), .Y(n8817) );
NAND2X1TS U958 ( .A(n9071), .B(n10845), .Y(n10847) );
OAI21X1TS U959 ( .A0(n9507), .A1(n9497), .B0(n9511), .Y(n9498) );
OAI21X1TS U960 ( .A0(n10076), .A1(n10075), .B0(n10074), .Y(n10077) );
NOR2X1TS U961 ( .A(n10072), .B(n10075), .Y(n10078) );
CLKINVX1TS U962 ( .A(n2364), .Y(n9754) );
OR2X6TS U963 ( .A(n9885), .B(n9884), .Y(n1273) );
CLKBUFX2TS U964 ( .A(n9630), .Y(n2587) );
NAND2X1TS U965 ( .A(n9043), .B(n9042), .Y(n10074) );
NAND2X1TS U966 ( .A(n7606), .B(n7605), .Y(n9649) );
NOR2X4TS U967 ( .A(n1609), .B(n9400), .Y(n2205) );
INVX4TS U968 ( .A(n8220), .Y(n10062) );
NAND2X4TS U969 ( .A(n2743), .B(n2741), .Y(n4423) );
INVX6TS U970 ( .A(n7538), .Y(n9049) );
NOR2X2TS U971 ( .A(n9043), .B(n9042), .Y(n10075) );
NOR2X1TS U972 ( .A(n9480), .B(n1920), .Y(n1436) );
NAND2X1TS U973 ( .A(n11107), .B(n10554), .Y(n11101) );
BUFX2TS U974 ( .A(n4737), .Y(n1334) );
INVX2TS U975 ( .A(n8815), .Y(n8830) );
INVX4TS U976 ( .A(n9048), .Y(n8406) );
NAND2X4TS U977 ( .A(n2887), .B(n2886), .Y(n9901) );
NAND2X6TS U978 ( .A(n2811), .B(n2823), .Y(n9274) );
INVX3TS U979 ( .A(n9769), .Y(n3007) );
BUFX3TS U980 ( .A(n8242), .Y(n1672) );
CLKINVX6TS U981 ( .A(n7556), .Y(n7557) );
NOR2X4TS U982 ( .A(n2076), .B(n9616), .Y(n9618) );
INVX2TS U983 ( .A(n8214), .Y(n8718) );
NAND2X6TS U984 ( .A(n3226), .B(n1455), .Y(n2271) );
NOR2X1TS U985 ( .A(n2076), .B(n10942), .Y(n10944) );
INVX2TS U986 ( .A(n11280), .Y(n11117) );
NAND2X6TS U987 ( .A(n3073), .B(n1455), .Y(n2821) );
INVX2TS U988 ( .A(n11291), .Y(n11079) );
INVX2TS U989 ( .A(n9325), .Y(n9327) );
ADDFHX2TS U990 ( .A(n8098), .B(n8097), .CI(n8096), .CO(n8154), .S(n9025) );
NOR2X2TS U991 ( .A(n9600), .B(n9603), .Y(n9606) );
NAND2X4TS U992 ( .A(n817), .B(n816), .Y(n1764) );
NAND2X6TS U993 ( .A(n1756), .B(n1304), .Y(n813) );
NAND2X2TS U994 ( .A(n10956), .B(n9392), .Y(n9394) );
NAND2X2TS U995 ( .A(n9040), .B(n9303), .Y(n10072) );
NOR2X4TS U996 ( .A(n2075), .B(n10825), .Y(n10827) );
NOR2X2TS U997 ( .A(n8756), .B(n10084), .Y(n10085) );
NOR2X6TS U998 ( .A(n2075), .B(n10833), .Y(n10835) );
NOR2X4TS U999 ( .A(n2076), .B(n10897), .Y(n10899) );
INVX4TS U1000 ( .A(n982), .Y(n983) );
INVX12TS U1001 ( .A(n6678), .Y(n1015) );
NOR2X4TS U1002 ( .A(n2075), .B(n10815), .Y(n10817) );
NOR2X4TS U1003 ( .A(n2075), .B(n7949), .Y(n7951) );
NAND2X2TS U1004 ( .A(n2085), .B(n10813), .Y(n10815) );
NAND2X1TS U1005 ( .A(n2040), .B(n10912), .Y(n10913) );
NAND2X2TS U1006 ( .A(n2085), .B(n9345), .Y(n9347) );
BUFX3TS U1007 ( .A(n8318), .Y(n2555) );
CLKINVX1TS U1008 ( .A(n2570), .Y(n9480) );
BUFX6TS U1009 ( .A(n8243), .Y(n1239) );
BUFX3TS U1010 ( .A(n8188), .Y(n5478) );
INVX2TS U1011 ( .A(n9408), .Y(n9436) );
CLKINVX3TS U1012 ( .A(n5470), .Y(n9771) );
INVX6TS U1013 ( .A(n1478), .Y(n1756) );
BUFX6TS U1014 ( .A(n8313), .Y(n949) );
INVX2TS U1015 ( .A(n7960), .Y(n7969) );
INVX2TS U1016 ( .A(n9845), .Y(n1554) );
NOR2X6TS U1017 ( .A(n7005), .B(n7004), .Y(n2237) );
INVX1TS U1018 ( .A(n8765), .Y(n10083) );
NAND2X1TS U1019 ( .A(n10940), .B(n7947), .Y(n7948) );
CLKBUFX2TS U1020 ( .A(n2941), .Y(n837) );
INVX2TS U1021 ( .A(n8777), .Y(n9518) );
CLKMX2X2TS U1022 ( .A(n8748), .B(n12129), .S0(n1215), .Y(n465) );
INVX2TS U1023 ( .A(n9642), .Y(n9644) );
CLKMX2X2TS U1024 ( .A(n8728), .B(n12128), .S0(n12127), .Y(n11822) );
INVX8TS U1025 ( .A(n2377), .Y(n9536) );
NAND2XLTS U1026 ( .A(n9476), .B(n9753), .Y(n9752) );
NAND2X6TS U1027 ( .A(n1075), .B(n1074), .Y(n2910) );
CLKINVX2TS U1028 ( .A(n9926), .Y(n1069) );
NAND2X4TS U1029 ( .A(n2085), .B(n1172), .Y(n10897) );
AOI21X2TS U1030 ( .A0(n10565), .A1(n10551), .B0(n10550), .Y(n11103) );
NAND2X4TS U1031 ( .A(n2951), .B(n2953), .Y(n9894) );
ADDFHX2TS U1032 ( .A(n9104), .B(n9103), .CI(n9102), .CO(n9117), .S(n9114) );
NAND2X2TS U1033 ( .A(n2086), .B(n7947), .Y(n7949) );
NOR2X2TS U1034 ( .A(n9382), .B(n9379), .Y(n9384) );
ADDFHX2TS U1035 ( .A(n9098), .B(n9097), .CI(n9096), .CO(n9119), .S(n9115) );
NAND2X2TS U1036 ( .A(n10954), .B(n10922), .Y(n10924) );
ADDFHX2TS U1037 ( .A(n4289), .B(n4288), .CI(n4287), .CO(n4412), .S(n4277) );
CLKINVX6TS U1038 ( .A(n8755), .Y(n10084) );
NAND2X2TS U1039 ( .A(n2086), .B(n1201), .Y(n9616) );
NAND2X1TS U1040 ( .A(n10957), .B(n10851), .Y(n10852) );
NAND2X2TS U1041 ( .A(n10046), .B(n2370), .Y(n2367) );
ADDFHX2TS U1042 ( .A(n8639), .B(n8640), .CI(n8638), .CO(n8655), .S(n8604) );
NOR2X2TS U1043 ( .A(n10955), .B(n10797), .Y(n10799) );
NAND2X4TS U1044 ( .A(n1665), .B(n8415), .Y(n2791) );
NAND2X4TS U1045 ( .A(n1310), .B(n8316), .Y(n816) );
NAND2X2TS U1046 ( .A(n2040), .B(n1201), .Y(n9615) );
INVX2TS U1047 ( .A(n1090), .Y(n2790) );
NAND2X2TS U1048 ( .A(n2544), .B(n2543), .Y(n2542) );
NOR2X4TS U1049 ( .A(n9528), .B(n9532), .Y(n9535) );
NOR2X2TS U1050 ( .A(n9034), .B(n9037), .Y(n9040) );
NOR2X6TS U1051 ( .A(n2075), .B(n9390), .Y(n9392) );
NOR2X2TS U1052 ( .A(n8338), .B(n8346), .Y(n7600) );
NOR4X1TS U1053 ( .A(n459), .B(n460), .C(n457), .D(n458), .Y(n9240) );
XNOR2X1TS U1054 ( .A(n2364), .B(n1972), .Y(n9481) );
INVX2TS U1055 ( .A(n9014), .Y(n1633) );
NAND2X1TS U1056 ( .A(n7586), .B(n7585), .Y(n9643) );
NAND2X1TS U1057 ( .A(n8769), .B(n8770), .Y(n9298) );
NAND2X1TS U1058 ( .A(n7596), .B(n7595), .Y(n9571) );
NAND2X1TS U1059 ( .A(n8773), .B(n8772), .Y(n9036) );
CLKINVX6TS U1060 ( .A(n8100), .Y(n8094) );
NAND2X1TS U1061 ( .A(n7598), .B(n7597), .Y(n8347) );
INVX6TS U1062 ( .A(n9925), .Y(n1068) );
NOR2X1TS U1063 ( .A(n11802), .B(n11886), .Y(n10554) );
INVX3TS U1064 ( .A(n7986), .Y(n8095) );
NAND2XLTS U1065 ( .A(n10957), .B(n10795), .Y(n10796) );
OAI2BB1X2TS U1066 ( .A0N(n4409), .A1N(n4410), .B0(n772), .Y(n9911) );
NAND2X2TS U1067 ( .A(n9512), .B(n9503), .Y(n7594) );
NAND2X2TS U1068 ( .A(n2673), .B(n6988), .Y(n3234) );
NOR2X2TS U1069 ( .A(n7586), .B(n7585), .Y(n9642) );
NOR2X2TS U1070 ( .A(n7595), .B(n7596), .Y(n8338) );
NOR2X2TS U1071 ( .A(n8773), .B(n8772), .Y(n9037) );
NAND2X1TS U1072 ( .A(n10940), .B(n10920), .Y(n8801) );
NAND2X4TS U1073 ( .A(n2879), .B(n2878), .Y(n4743) );
INVX2TS U1074 ( .A(n2574), .Y(n2543) );
NOR2X2TS U1075 ( .A(n7598), .B(n7597), .Y(n8346) );
NAND2X6TS U1076 ( .A(n998), .B(n6983), .Y(n9306) );
INVX8TS U1077 ( .A(n1674), .Y(n1675) );
INVX6TS U1078 ( .A(n10863), .Y(n2076) );
CLKINVX6TS U1079 ( .A(n8181), .Y(n7427) );
NOR2X1TS U1080 ( .A(n9358), .B(n1144), .Y(n7947) );
NOR2X4TS U1081 ( .A(n2075), .B(n10959), .Y(n10962) );
NAND2X2TS U1082 ( .A(n4740), .B(n4741), .Y(n1074) );
NOR2X1TS U1083 ( .A(n10812), .B(n1150), .Y(n10813) );
INVX4TS U1084 ( .A(n5638), .Y(n1246) );
NOR2X1TS U1085 ( .A(n10903), .B(n1146), .Y(n10904) );
NAND2X2TS U1086 ( .A(n8666), .B(n8667), .Y(n2558) );
INVX2TS U1087 ( .A(n9527), .Y(n9528) );
NOR2X1TS U1088 ( .A(n10850), .B(n1124), .Y(n10851) );
NOR2X1TS U1089 ( .A(n10840), .B(n1149), .Y(n10841) );
ADDFHX2TS U1090 ( .A(n7332), .B(n7331), .CI(n7330), .CO(n7385), .S(n7326) );
ADDFX2TS U1091 ( .A(n7378), .B(n7377), .CI(n7376), .CO(n7412), .S(n7386) );
ADDFHX2TS U1092 ( .A(n9089), .B(n9088), .CI(n9087), .CO(n9111), .S(n9090) );
ADDFHX2TS U1093 ( .A(n7405), .B(n7404), .CI(n7403), .CO(n9468), .S(n7413) );
ADDFHX2TS U1094 ( .A(n7189), .B(n7191), .CI(n7190), .CO(n7416), .S(n7225) );
NAND2X1TS U1095 ( .A(n7918), .B(n9380), .Y(n9382) );
XNOR2X2TS U1096 ( .A(n9463), .B(n9462), .Y(n10082) );
CLKINVX1TS U1097 ( .A(n9039), .Y(n3197) );
INVX3TS U1098 ( .A(n2608), .Y(n2394) );
INVX6TS U1099 ( .A(n818), .Y(n9338) );
OAI22X2TS U1100 ( .A0(n4317), .A1(n8977), .B0(n3929), .B1(n8516), .Y(n4058)
);
NOR2X4TS U1101 ( .A(n2531), .B(n2278), .Y(n7528) );
NAND2X1TS U1102 ( .A(n6389), .B(n6388), .Y(n8333) );
INVX4TS U1103 ( .A(n6387), .Y(n9917) );
INVX6TS U1104 ( .A(n8657), .Y(n2825) );
INVX2TS U1105 ( .A(n9206), .Y(n10667) );
BUFX3TS U1106 ( .A(n6987), .Y(n2673) );
OR2X2TS U1107 ( .A(n7590), .B(n7589), .Y(n9503) );
INVX4TS U1108 ( .A(n2610), .Y(n2954) );
INVX4TS U1109 ( .A(n5699), .Y(n3030) );
INVX8TS U1110 ( .A(n10863), .Y(n2075) );
INVX2TS U1111 ( .A(n8658), .Y(n2824) );
NAND2X4TS U1112 ( .A(n2375), .B(n6393), .Y(n7564) );
NAND2X1TS U1113 ( .A(n10920), .B(n10887), .Y(n10903) );
NOR2X1TS U1114 ( .A(n7361), .B(n1920), .Y(n7405) );
INVX3TS U1115 ( .A(n6285), .Y(n5981) );
NAND2X2TS U1116 ( .A(n2085), .B(n1360), .Y(n10959) );
NAND2X6TS U1117 ( .A(n1512), .B(n1515), .Y(n1113) );
NAND2X2TS U1118 ( .A(n2278), .B(n2531), .Y(n7527) );
NOR2X1TS U1119 ( .A(n7402), .B(n1920), .Y(n9453) );
NAND2X1TS U1120 ( .A(n10939), .B(n9343), .Y(n10850) );
AOI21X2TS U1121 ( .A0(n9231), .A1(n9223), .B0(n9225), .Y(n9221) );
NAND2X1TS U1122 ( .A(n10537), .B(n10536), .Y(n10561) );
INVX3TS U1123 ( .A(n8225), .Y(n8103) );
NAND2X4TS U1124 ( .A(n8393), .B(n8402), .Y(n7533) );
NAND2X4TS U1125 ( .A(n2608), .B(n3212), .Y(n3211) );
OR2X2TS U1126 ( .A(n8768), .B(n8767), .Y(n9303) );
INVX2TS U1127 ( .A(n8787), .Y(n8788) );
OA21XLTS U1128 ( .A0(n9212), .A1(n8722), .B0(n9211), .Y(n9217) );
NAND3X6TS U1129 ( .A(n2694), .B(n2692), .C(n2693), .Y(n1760) );
OAI22X2TS U1130 ( .A0(n8142), .A1(n9457), .B0(n8065), .B1(n9456), .Y(n8148)
);
INVX6TS U1131 ( .A(n10863), .Y(n10955) );
INVX4TS U1132 ( .A(n9344), .Y(n10940) );
NOR2X1TS U1133 ( .A(n10822), .B(n1143), .Y(n10795) );
NOR2X1TS U1134 ( .A(n2434), .B(n11955), .Y(n9462) );
NOR2X2TS U1135 ( .A(n9861), .B(n9862), .Y(n2761) );
CLKBUFX2TS U1136 ( .A(n9320), .Y(n818) );
ADDFHX2TS U1137 ( .A(n9107), .B(n9106), .CI(n9105), .CO(n9011), .S(n9125) );
CLKBUFX2TS U1138 ( .A(n9856), .Y(n777) );
ADDFHX2TS U1139 ( .A(n6721), .B(n6720), .CI(n6719), .CO(n8299), .S(n8306) );
ADDFHX2TS U1140 ( .A(n8684), .B(n8685), .CI(n8686), .CO(n9867), .S(n8691) );
NOR2X6TS U1141 ( .A(n898), .B(n2551), .Y(n8332) );
NAND2X2TS U1142 ( .A(n5902), .B(n1791), .Y(n1787) );
OAI22X1TS U1143 ( .A0(n7327), .A1(n1894), .B0(n4684), .B1(n2814), .Y(n7378)
);
ADDFHX2TS U1144 ( .A(n7335), .B(n7334), .CI(n7333), .CO(n7360), .S(n7330) );
NOR2X2TS U1145 ( .A(n10537), .B(n10536), .Y(n10560) );
INVX4TS U1146 ( .A(n8222), .Y(n2759) );
OAI22X2TS U1147 ( .A0(n8137), .A1(n8977), .B0(n1862), .B1(n8087), .Y(n8101)
);
NOR2X6TS U1148 ( .A(n10143), .B(n10161), .Y(n10148) );
CLKINVX6TS U1149 ( .A(n1679), .Y(n764) );
OAI22X2TS U1150 ( .A0(n8060), .A1(n2036), .B0(n8064), .B1(n2165), .Y(n8105)
);
OR2X2TS U1151 ( .A(n8941), .B(n8940), .Y(n8412) );
NAND2X1TS U1152 ( .A(n7590), .B(n7589), .Y(n9502) );
INVX6TS U1153 ( .A(n6276), .Y(n6507) );
INVX8TS U1154 ( .A(n6286), .Y(n5904) );
INVX1TS U1155 ( .A(n9052), .Y(n8404) );
INVX6TS U1156 ( .A(n6393), .Y(n4718) );
INVX2TS U1157 ( .A(n9918), .Y(n9920) );
OR2X6TS U1158 ( .A(n2342), .B(n2475), .Y(n8393) );
INVX2TS U1159 ( .A(n9212), .Y(n9231) );
INVX6TS U1160 ( .A(n5361), .Y(n2693) );
INVX4TS U1161 ( .A(n6414), .Y(n6502) );
INVX4TS U1162 ( .A(n8563), .Y(n9821) );
INVX4TS U1163 ( .A(n6275), .Y(n6494) );
INVX4TS U1164 ( .A(n8662), .Y(n8688) );
NAND2X1TS U1165 ( .A(n9207), .B(n1153), .Y(n10650) );
NOR2X1TS U1166 ( .A(n3770), .B(n1907), .Y(n3927) );
INVX6TS U1167 ( .A(n6388), .Y(n9921) );
INVX6TS U1168 ( .A(n5479), .Y(n9924) );
BUFX4TS U1169 ( .A(n6398), .Y(n2278) );
OAI21X2TS U1170 ( .A0(n2967), .A1(n8768), .B0(n2966), .Y(n7383) );
NOR2X1TS U1171 ( .A(n7341), .B(n7031), .Y(n7382) );
INVX4TS U1172 ( .A(n4312), .Y(n1842) );
XNOR2X2TS U1173 ( .A(n3591), .B(n2034), .Y(n5494) );
INVX4TS U1174 ( .A(n9932), .Y(n2502) );
OAI22X2TS U1175 ( .A0(n8067), .A1(n1986), .B0(n8066), .B1(n2356), .Y(n8074)
);
BUFX4TS U1176 ( .A(n11011), .Y(n2248) );
NAND2X2TS U1177 ( .A(n2387), .B(n788), .Y(n9580) );
NAND2X6TS U1178 ( .A(n2396), .B(n784), .Y(n8296) );
NAND2X2TS U1179 ( .A(n2463), .B(n7582), .Y(n8426) );
BUFX3TS U1180 ( .A(n6397), .Y(n2531) );
INVX8TS U1181 ( .A(n8471), .Y(n8667) );
OAI21X1TS U1182 ( .A0(n7394), .A1(n1073), .B0(n7393), .Y(n1071) );
OAI22X1TS U1183 ( .A0(n4072), .A1(n2331), .B0(n3790), .B1(n2050), .Y(n3925)
);
BUFX3TS U1184 ( .A(n5903), .Y(n836) );
CLKINVX6TS U1185 ( .A(n8766), .Y(n2934) );
CLKXOR2X2TS U1186 ( .A(n11107), .B(n10532), .Y(n10539) );
NAND2XLTS U1187 ( .A(n11458), .B(n9165), .Y(n9163) );
XNOR2X1TS U1188 ( .A(n2570), .B(n1972), .Y(n9452) );
NAND2X2TS U1189 ( .A(n10195), .B(n10190), .Y(n9762) );
CLKINVX6TS U1190 ( .A(n4337), .Y(n2746) );
CLKXOR2X2TS U1191 ( .A(n10530), .B(n10529), .Y(n10537) );
NAND2X6TS U1192 ( .A(n8376), .B(n8221), .Y(n8222) );
XOR2X1TS U1193 ( .A(n10530), .B(n10528), .Y(n10535) );
BUFX8TS U1194 ( .A(n10957), .Y(n2040) );
INVX6TS U1195 ( .A(n2727), .Y(n1773) );
BUFX12TS U1196 ( .A(n10954), .Y(n2085) );
NAND2X6TS U1197 ( .A(n10119), .B(n2300), .Y(n2299) );
OAI21X1TS U1198 ( .A0(n9166), .A1(n11388), .B0(n9165), .Y(n9168) );
ADDFHX2TS U1199 ( .A(n8650), .B(n8649), .CI(n8648), .CO(n8686), .S(n8681) );
NAND2X2TS U1200 ( .A(n9837), .B(n1728), .Y(n10118) );
NAND2X2TS U1201 ( .A(n2903), .B(n3267), .Y(n1299) );
ADDFHX2TS U1202 ( .A(n4512), .B(n4511), .CI(n4510), .CO(n4805), .S(n4709) );
NAND2X2TS U1203 ( .A(n2467), .B(n2386), .Y(n8436) );
NOR2X2TS U1204 ( .A(n10585), .B(n10611), .Y(n10601) );
XNOR2X2TS U1205 ( .A(n2364), .B(n2057), .Y(n7409) );
OAI22X2TS U1206 ( .A0(n4803), .A1(n2588), .B0(n8947), .B1(n8945), .Y(n9003)
);
CLKINVX2TS U1207 ( .A(n9735), .Y(n3325) );
XNOR2X2TS U1208 ( .A(n2573), .B(n1024), .Y(n7410) );
MXI2X2TS U1209 ( .A(n11824), .B(n12390), .S0(FSM_selector_A), .Y(n10536) );
MXI2X2TS U1210 ( .A(n12149), .B(n12391), .S0(FSM_selector_A), .Y(n10538) );
INVX6TS U1211 ( .A(n1521), .Y(n898) );
OAI22X2TS U1212 ( .A0(n5988), .A1(n8614), .B0(n5743), .B1(n6921), .Y(n8253)
);
XNOR2X2TS U1213 ( .A(n9458), .B(n1361), .Y(n9464) );
INVX8TS U1214 ( .A(n780), .Y(n998) );
XNOR2X2TS U1215 ( .A(n2505), .B(n2058), .Y(n4802) );
BUFX16TS U1216 ( .A(n6374), .Y(n2574) );
INVX2TS U1217 ( .A(n5987), .Y(n1662) );
INVX6TS U1218 ( .A(n8668), .Y(n3022) );
INVX3TS U1219 ( .A(n8216), .Y(n8884) );
INVX6TS U1220 ( .A(n8928), .Y(n8886) );
CLKINVX6TS U1221 ( .A(n6464), .Y(n6512) );
INVX2TS U1222 ( .A(n8996), .Y(n9008) );
INVX6TS U1223 ( .A(n6384), .Y(n4395) );
NOR2X1TS U1224 ( .A(n11099), .B(FS_Module_state_reg[3]), .Y(n9734) );
CLKBUFX2TS U1225 ( .A(n6284), .Y(n2494) );
AND2X6TS U1226 ( .A(n9601), .B(n7943), .Y(n1109) );
INVX2TS U1227 ( .A(n10186), .Y(n6277) );
NOR2X4TS U1228 ( .A(n2546), .B(n1505), .Y(n8366) );
BUFX3TS U1229 ( .A(n7580), .Y(n2387) );
INVX8TS U1230 ( .A(n1331), .Y(n1332) );
INVX8TS U1231 ( .A(n6389), .Y(n1521) );
INVX4TS U1232 ( .A(n2466), .Y(n2793) );
NAND2X2TS U1233 ( .A(n5473), .B(n2831), .Y(n9288) );
INVX4TS U1234 ( .A(n8602), .Y(n1652) );
CLKBUFX2TS U1235 ( .A(n6283), .Y(n2597) );
CLKINVX2TS U1236 ( .A(n8770), .Y(n7364) );
XNOR2X2TS U1237 ( .A(n8620), .B(n3322), .Y(n7224) );
XNOR2X2TS U1238 ( .A(n2505), .B(n3322), .Y(n7329) );
NOR2X1TS U1239 ( .A(n951), .B(n7401), .Y(n1361) );
OAI22X1TS U1240 ( .A0(n3930), .A1(n2293), .B0(n4692), .B1(n1893), .Y(n4760)
);
NAND2X4TS U1241 ( .A(n9416), .B(n7934), .Y(n7936) );
BUFX3TS U1242 ( .A(n7986), .Y(n788) );
CLKBUFX3TS U1243 ( .A(n7581), .Y(n2463) );
CLKBUFX3TS U1244 ( .A(n8100), .Y(n2262) );
XOR2X2TS U1245 ( .A(n10530), .B(n10518), .Y(n10523) );
NOR2X2TS U1246 ( .A(n10519), .B(n1435), .Y(n10585) );
XNOR2X2TS U1247 ( .A(n2348), .B(n2251), .Y(n8099) );
OR2X4TS U1248 ( .A(n2161), .B(n6276), .Y(n10187) );
OAI22X1TS U1249 ( .A0(n5694), .A1(n8629), .B0(n5927), .B1(n1969), .Y(n5935)
);
OAI22X2TS U1250 ( .A0(n8631), .A1(n1969), .B0(n8630), .B1(n1932), .Y(n8677)
);
NAND2X2TS U1251 ( .A(n10510), .B(n10509), .Y(n10590) );
NAND2X1TS U1252 ( .A(n6510), .B(n6511), .Y(n3019) );
INVX8TS U1253 ( .A(n8451), .Y(n2711) );
OAI22X1TS U1254 ( .A0(n8582), .A1(n2259), .B0(n4367), .B1(n2056), .Y(n8527)
);
INVX2TS U1255 ( .A(n9358), .Y(n10939) );
BUFX3TS U1256 ( .A(n6377), .Y(n2535) );
INVX3TS U1257 ( .A(n8598), .Y(n1680) );
NAND2X6TS U1258 ( .A(n9801), .B(n9800), .Y(n1511) );
NAND2X4TS U1259 ( .A(n8764), .B(n8755), .Y(n8766) );
OAI22X2TS U1260 ( .A0(n2889), .A1(n1960), .B0(n4702), .B1(n2112), .Y(n4730)
);
NAND2X4TS U1261 ( .A(n2312), .B(n5470), .Y(n9285) );
BUFX16TS U1262 ( .A(n8471), .Y(n740) );
INVX2TS U1263 ( .A(n9086), .Y(n899) );
NOR2X2TS U1264 ( .A(n7113), .B(n1920), .Y(n7151) );
OAI22X1TS U1265 ( .A0(n5512), .A1(n2067), .B0(n5632), .B1(n1940), .Y(n5524)
);
NOR3X1TS U1266 ( .A(n11799), .B(n1874), .C(FSM_selector_B[0]), .Y(n1384) );
INVX4TS U1267 ( .A(n10128), .Y(n2300) );
INVX6TS U1268 ( .A(n5788), .Y(n935) );
ADDFHX2TS U1269 ( .A(n8077), .B(n8076), .CI(n8075), .CO(n8159), .S(n8162) );
OAI21X1TS U1270 ( .A0(n8762), .A1(n10086), .B0(n8761), .Y(n8763) );
XNOR2X2TS U1271 ( .A(n3591), .B(n8513), .Y(n4804) );
NOR2X2TS U1272 ( .A(n2522), .B(n839), .Y(n8214) );
OAI22X1TS U1273 ( .A0(n5828), .A1(n8629), .B0(n5694), .B1(n1968), .Y(n5732)
);
OAI22X2TS U1274 ( .A0(n5983), .A1(n2108), .B0(n5815), .B1(n8641), .Y(n5986)
);
OAI22X2TS U1275 ( .A0(n8912), .A1(n1894), .B0(n8112), .B1(n8935), .Y(n8885)
);
XNOR2X2TS U1276 ( .A(n8889), .B(n2033), .Y(n5988) );
OAI22X1TS U1277 ( .A0(n6475), .A1(n1968), .B0(n6474), .B1(n1932), .Y(n6485)
);
NOR2X4TS U1278 ( .A(n10215), .B(n10213), .Y(n10208) );
OR2X4TS U1279 ( .A(n2477), .B(n2572), .Y(n10190) );
MXI2X2TS U1280 ( .A(n11827), .B(n12387), .S0(FSM_selector_A), .Y(n10521) );
OAI22X2TS U1281 ( .A0(n8922), .A1(n5488), .B0(n8930), .B1(n9457), .Y(n8929)
);
OAI22X2TS U1282 ( .A0(n8142), .A1(n5488), .B0(n8922), .B1(n9457), .Y(n8906)
);
OAI22X2TS U1283 ( .A0(n4296), .A1(n2019), .B0(n4082), .B1(n1895), .Y(n4291)
);
OAI22X2TS U1284 ( .A0(n5513), .A1(n1965), .B0(n5506), .B1(n2052), .Y(n5525)
);
NAND2X4TS U1285 ( .A(n3002), .B(n3003), .Y(n2563) );
OAI22X2TS U1286 ( .A0(n4622), .A1(n2036), .B0(n4635), .B1(n1973), .Y(n4733)
);
OAI22X2TS U1287 ( .A0(n6456), .A1(n2099), .B0(n6479), .B1(n6885), .Y(n6514)
);
XNOR2X2TS U1288 ( .A(n3591), .B(n2031), .Y(n8570) );
XNOR2X2TS U1289 ( .A(n8911), .B(n1929), .Y(n8559) );
XNOR2X2TS U1290 ( .A(n2473), .B(n8920), .Y(n8922) );
XOR2X2TS U1291 ( .A(n3591), .B(n1058), .Y(n8111) );
XNOR2X2TS U1292 ( .A(n2363), .B(n8896), .Y(n3930) );
AND2X6TS U1293 ( .A(n6938), .B(n6937), .Y(n9370) );
INVX6TS U1294 ( .A(n8985), .Y(n9086) );
NAND2X1TS U1295 ( .A(n2537), .B(n8231), .Y(n10095) );
INVX6TS U1296 ( .A(n5471), .Y(n3003) );
INVX2TS U1297 ( .A(n8230), .Y(n7183) );
INVX6TS U1298 ( .A(n3267), .Y(n11010) );
INVX4TS U1299 ( .A(n8231), .Y(n7290) );
INVX8TS U1300 ( .A(n6288), .Y(n1331) );
NOR2X2TS U1301 ( .A(n6605), .B(n6578), .Y(n10213) );
AO21X2TS U1302 ( .A0(n8950), .A1(n2053), .B0(n5496), .Y(n7347) );
INVX3TS U1303 ( .A(n6378), .Y(n3171) );
XNOR2X2TS U1304 ( .A(n8911), .B(n3322), .Y(n8061) );
NOR2X6TS U1305 ( .A(n2488), .B(n3042), .Y(n9629) );
INVX6TS U1306 ( .A(n7946), .Y(n9344) );
XNOR2X2TS U1307 ( .A(n1019), .B(n8552), .Y(n6479) );
XNOR2X2TS U1308 ( .A(n2573), .B(n1929), .Y(n3767) );
XNOR2X2TS U1309 ( .A(n2505), .B(n2057), .Y(n7171) );
OAI22X2TS U1310 ( .A0(n3629), .A1(n2098), .B0(n2446), .B1(n1022), .Y(n4696)
);
INVX4TS U1311 ( .A(n8772), .Y(n7394) );
XNOR2X2TS U1312 ( .A(n8889), .B(n8920), .Y(n8062) );
OAI22X2TS U1313 ( .A0(n3923), .A1(n2098), .B0(n1961), .B1(n3629), .Y(n3762)
);
NAND2X2TS U1314 ( .A(n2600), .B(n2461), .Y(n3002) );
XNOR2X2TS U1315 ( .A(n2363), .B(n2057), .Y(n7182) );
XNOR2X2TS U1316 ( .A(n2473), .B(n3322), .Y(n8060) );
XOR2X2TS U1317 ( .A(n1037), .B(n1040), .Y(n7305) );
XNOR2X2TS U1318 ( .A(n1818), .B(n2033), .Y(n5743) );
XNOR2X2TS U1319 ( .A(n2182), .B(n2037), .Y(n8081) );
NOR2X4TS U1320 ( .A(n8234), .B(n8762), .Y(n8764) );
OAI22X1TS U1321 ( .A0(n4636), .A1(n8945), .B0(n4294), .B1(n2588), .Y(n4756)
);
NOR2X4TS U1322 ( .A(n2467), .B(n2386), .Y(n8435) );
NAND2X2TS U1323 ( .A(n7940), .B(n11365), .Y(n9602) );
NAND2X6TS U1324 ( .A(n3099), .B(n789), .Y(n11002) );
BUFX4TS U1325 ( .A(n5471), .Y(n2312) );
NAND2X6TS U1326 ( .A(n3162), .B(n3161), .Y(n3248) );
NOR2X6TS U1327 ( .A(n2560), .B(n3127), .Y(n8355) );
CLKBUFX2TS U1328 ( .A(n9457), .Y(n1935) );
NOR2X2TS U1329 ( .A(n8063), .B(n1907), .Y(n8140) );
NAND2X2TS U1330 ( .A(n7941), .B(n11364), .Y(n9610) );
NOR2X6TS U1331 ( .A(n8815), .B(n7926), .Y(n7928) );
NAND2X4TS U1332 ( .A(n6725), .B(n1617), .Y(n1618) );
INVX12TS U1333 ( .A(n6282), .Y(n5987) );
ADDFHX2TS U1334 ( .A(n5636), .B(n5637), .CI(n5635), .CO(n8450), .S(n5842) );
XNOR2X2TS U1335 ( .A(n3591), .B(n2033), .Y(n5830) );
XNOR2X2TS U1336 ( .A(n2348), .B(n8897), .Y(n8981) );
XNOR2X2TS U1337 ( .A(n2549), .B(n1024), .Y(n4622) );
XNOR2X2TS U1338 ( .A(n3640), .B(n8619), .Y(n5694) );
ADDFHX2TS U1339 ( .A(n7581), .B(n7297), .CI(n7296), .CO(n7307), .S(n8075) );
XNOR2X2TS U1340 ( .A(n8540), .B(n6435), .Y(n5944) );
XNOR2X2TS U1341 ( .A(n2936), .B(n3322), .Y(n7229) );
ADDFHX2TS U1342 ( .A(n6619), .B(n6618), .CI(n6617), .CO(n6648), .S(n6713) );
XNOR2X2TS U1343 ( .A(n3640), .B(n2408), .Y(n8565) );
XNOR2X2TS U1344 ( .A(n8620), .B(n2037), .Y(n8891) );
INVX2TS U1345 ( .A(n1063), .Y(n1061) );
XNOR2X2TS U1346 ( .A(n8534), .B(n8508), .Y(n5940) );
XOR2X2TS U1347 ( .A(n8889), .B(n1903), .Y(n4645) );
OAI21X1TS U1348 ( .A0(n7747), .A1(n10661), .B0(n7746), .Y(n7748) );
XNOR2X2TS U1349 ( .A(n8898), .B(n1926), .Y(n8146) );
XNOR2X2TS U1350 ( .A(n3640), .B(n966), .Y(n4723) );
XNOR2X2TS U1351 ( .A(n1819), .B(n2057), .Y(n7306) );
OAI22X2TS U1352 ( .A0(n8530), .A1(n5528), .B0(n8980), .B1(n1557), .Y(n5923)
);
MXI2X2TS U1353 ( .A(n11830), .B(n3315), .S0(FSM_selector_A), .Y(n10511) );
NOR2X4TS U1354 ( .A(n7156), .B(n7587), .Y(n2685) );
NOR2X4TS U1355 ( .A(n10749), .B(n10747), .Y(n9545) );
OAI22X2TS U1356 ( .A0(n5549), .A1(n1823), .B0(n5528), .B1(n8980), .Y(n5746)
);
OAI22X2TS U1357 ( .A0(n4317), .A1(n1862), .B0(n4316), .B1(n1965), .Y(n4335)
);
OAI22X2TS U1358 ( .A0(n7082), .A1(n2588), .B0(n2056), .B1(n5500), .Y(n7033)
);
ADDFHX2TS U1359 ( .A(n4321), .B(n4323), .CI(n4322), .CO(n4289), .S(n4333) );
BUFX6TS U1360 ( .A(n6468), .Y(n2477) );
INVX2TS U1361 ( .A(n2238), .Y(n4811) );
BUFX4TS U1362 ( .A(n5485), .Y(n2557) );
XNOR2X2TS U1363 ( .A(n2473), .B(n1926), .Y(n4636) );
INVX1TS U1364 ( .A(n1037), .Y(n7032) );
INVX2TS U1365 ( .A(n2376), .Y(n7048) );
INVX2TS U1366 ( .A(n4717), .Y(n1300) );
OR2X6TS U1367 ( .A(n5471), .B(n5470), .Y(n1370) );
INVX1TS U1368 ( .A(n8091), .Y(n877) );
INVX6TS U1369 ( .A(n7585), .Y(n7154) );
INVX2TS U1370 ( .A(n7580), .Y(n8083) );
BUFX3TS U1371 ( .A(n6528), .Y(n6919) );
BUFX3TS U1372 ( .A(n5480), .Y(n2495) );
BUFX3TS U1373 ( .A(n6539), .Y(n2493) );
BUFX3TS U1374 ( .A(n6464), .Y(n2523) );
BUFX3TS U1375 ( .A(n8950), .Y(n2545) );
BUFX6TS U1376 ( .A(n8563), .Y(n1307) );
NAND2X4TS U1377 ( .A(n3284), .B(n3283), .Y(n6958) );
BUFX4TS U1378 ( .A(n6452), .Y(n2572) );
INVX3TS U1379 ( .A(n7588), .Y(n7156) );
NOR2BX2TS U1380 ( .AN(n6849), .B(n8948), .Y(n5531) );
OR2X4TS U1381 ( .A(n6710), .B(n6708), .Y(n10242) );
XNOR2X2TS U1382 ( .A(n2573), .B(n2031), .Y(n3924) );
AO21X2TS U1383 ( .A0(n8977), .A1(n1862), .B0(n8087), .Y(n8085) );
XNOR2X2TS U1384 ( .A(n2238), .B(n8552), .Y(n6456) );
XNOR2X2TS U1385 ( .A(n2364), .B(n8510), .Y(n7082) );
INVX2TS U1386 ( .A(n1791), .Y(n5829) );
OR2X6TS U1387 ( .A(n1847), .B(n2622), .Y(n10069) );
AO21X2TS U1388 ( .A0(n1986), .A1(n2356), .B0(n1903), .Y(n7155) );
CLKBUFX3TS U1389 ( .A(n6527), .Y(n2516) );
CLKXOR2X4TS U1390 ( .A(n2282), .B(n5534), .Y(n5637) );
INVX2TS U1391 ( .A(n9085), .Y(n1671) );
NOR2X4TS U1392 ( .A(n7807), .B(n11374), .Y(n8854) );
OAI22X2TS U1393 ( .A0(n4092), .A1(n1886), .B0(n4081), .B1(n2054), .Y(n4321)
);
INVX2TS U1394 ( .A(n4647), .Y(n1709) );
BUFX3TS U1395 ( .A(n5638), .Y(n789) );
CLKINVX12TS U1396 ( .A(n2338), .Y(n8086) );
BUFX3TS U1397 ( .A(n5479), .Y(n2661) );
AO21X2TS U1398 ( .A0(n1985), .A1(n8629), .B0(n2950), .Y(n3949) );
BUFX3TS U1399 ( .A(n8191), .Y(n2467) );
XNOR2X2TS U1400 ( .A(n914), .B(n6435), .Y(n8937) );
NOR2X4TS U1401 ( .A(n7924), .B(n1186), .Y(n8815) );
NOR2X4TS U1402 ( .A(n7819), .B(n11353), .Y(n8777) );
NAND2X6TS U1403 ( .A(n1605), .B(n1604), .Y(n11011) );
OAI22X2TS U1404 ( .A0(n4405), .A1(n8583), .B0(n4516), .B1(n2055), .Y(n4693)
);
BUFX3TS U1405 ( .A(n2356), .Y(n2051) );
NAND2X6TS U1406 ( .A(n2561), .B(n1233), .Y(n9337) );
NOR2X6TS U1407 ( .A(n7813), .B(n11371), .Y(n10749) );
NAND2X4TS U1408 ( .A(n7924), .B(n1186), .Y(n8829) );
BUFX4TS U1409 ( .A(n8977), .Y(n1965) );
AO21X1TS U1410 ( .A0(n8574), .A1(n6883), .B0(n6635), .Y(n4727) );
NOR2X6TS U1411 ( .A(n1064), .B(n1065), .Y(n1063) );
NOR2X2TS U1412 ( .A(n7230), .B(n1920), .Y(n7297) );
XNOR2X2TS U1413 ( .A(n8894), .B(n1946), .Y(n6475) );
NOR2X6TS U1414 ( .A(n7932), .B(n1163), .Y(n9425) );
NAND2X6TS U1415 ( .A(n3167), .B(n997), .Y(n3108) );
OAI22X2TS U1416 ( .A0(n4404), .A1(n9755), .B0(n4634), .B1(n8908), .Y(n4694)
);
INVX4TS U1417 ( .A(n4353), .Y(n2057) );
XNOR2X2TS U1418 ( .A(n8534), .B(n8513), .Y(n5528) );
XNOR2X2TS U1419 ( .A(n8911), .B(n8887), .Y(n4317) );
XNOR2X2TS U1420 ( .A(n2473), .B(n8552), .Y(n5550) );
OR2X4TS U1421 ( .A(n1735), .B(n2614), .Y(n10983) );
AOI21X2TS U1422 ( .A0(n8865), .A1(n7800), .B0(n7799), .Y(n7801) );
NAND2X2TS U1423 ( .A(n7925), .B(n1160), .Y(n8819) );
ADDFHX2TS U1424 ( .A(n3519), .B(n3518), .CI(n3517), .CO(n3516), .S(n4315) );
XNOR2X2TS U1425 ( .A(n2021), .B(n8508), .Y(n5924) );
OAI22X1TS U1426 ( .A0(n6473), .A1(n1945), .B0(n6449), .B1(n8574), .Y(n6427)
);
XNOR2X2TS U1427 ( .A(n8444), .B(n1926), .Y(n8512) );
BUFX3TS U1428 ( .A(n1973), .Y(n2165) );
XNOR2X2TS U1429 ( .A(n8540), .B(n8887), .Y(n5532) );
NOR2X1TS U1430 ( .A(n4403), .B(n1907), .Y(n4695) );
OAI22X1TS U1431 ( .A0(n6602), .A1(n1953), .B0(n6554), .B1(n6921), .Y(n6594)
);
NAND2X2TS U1432 ( .A(n1580), .B(n4407), .Y(n1578) );
CLKINVX1TS U1433 ( .A(n1024), .Y(n1040) );
XNOR2X2TS U1434 ( .A(n3640), .B(n8542), .Y(n6467) );
CLKINVX1TS U1435 ( .A(n8552), .Y(n829) );
INVX8TS U1436 ( .A(n6726), .Y(n1617) );
OAI22X2TS U1437 ( .A0(n5541), .A1(n1908), .B0(n8472), .B1(n8516), .Y(n8460)
);
NAND2X2TS U1438 ( .A(n7945), .B(n11369), .Y(n9314) );
INVX2TS U1439 ( .A(n6655), .Y(n6703) );
INVX1TS U1440 ( .A(n2473), .Y(n7230) );
INVX2TS U1441 ( .A(n2456), .Y(n4685) );
INVX6TS U1442 ( .A(n6527), .Y(n6550) );
OR2X6TS U1443 ( .A(n6873), .B(n6872), .Y(n997) );
OAI2BB1X2TS U1444 ( .A0N(n3509), .A1N(n3510), .B0(n2372), .Y(n3518) );
INVX8TS U1445 ( .A(n8087), .Y(n2058) );
BUFX3TS U1446 ( .A(n8215), .Y(n2491) );
AO21X1TS U1447 ( .A0(n2221), .A1(n2046), .B0(n1838), .Y(n7375) );
INVX4TS U1448 ( .A(n8190), .Y(n4647) );
INVX4TS U1449 ( .A(n5484), .Y(n4717) );
BUFX3TS U1450 ( .A(n2577), .Y(n1892) );
BUFX8TS U1451 ( .A(n8583), .Y(n1886) );
NAND2X2TS U1452 ( .A(n6708), .B(n6710), .Y(n10241) );
INVX6TS U1453 ( .A(n8228), .Y(n8091) );
CLKBUFX2TS U1454 ( .A(n8233), .Y(n2426) );
NOR2BX2TS U1455 ( .AN(n2044), .B(n8577), .Y(n5548) );
BUFX4TS U1456 ( .A(n8533), .Y(n1967) );
BUFX4TS U1457 ( .A(n8547), .Y(n2561) );
XNOR2X2TS U1458 ( .A(n8894), .B(n8896), .Y(n8507) );
OAI22X1TS U1459 ( .A0(n2411), .A1(n7368), .B0(n1950), .B1(n11683), .Y(n7397)
);
INVX4TS U1460 ( .A(n6579), .Y(n6628) );
XNOR2X2TS U1461 ( .A(n2473), .B(n1928), .Y(n8476) );
OR2X4TS U1462 ( .A(n940), .B(n2474), .Y(n10057) );
NOR2BX2TS U1463 ( .AN(n6849), .B(n8530), .Y(n6463) );
CLKBUFX3TS U1464 ( .A(n8900), .Y(n2622) );
CLKBUFX3TS U1465 ( .A(n8913), .Y(n1847) );
CLKINVX2TS U1466 ( .A(n2349), .Y(n4403) );
BUFX12TS U1467 ( .A(n8938), .Y(n2067) );
BUFX8TS U1468 ( .A(n8948), .Y(n2055) );
BUFX16TS U1469 ( .A(n2259), .Y(n967) );
CLKINVX6TS U1470 ( .A(n8719), .Y(n9558) );
NAND2X1TS U1471 ( .A(n9356), .B(n9377), .Y(n9357) );
BUFX6TS U1472 ( .A(n8672), .Y(n2175) );
NAND2BX2TS U1473 ( .AN(n1022), .B(n2715), .Y(n4643) );
OAI22X2TS U1474 ( .A0(n4296), .A1(n1894), .B0(n4295), .B1(n2019), .Y(n4406)
);
NAND2X2TS U1475 ( .A(n5876), .B(n5875), .Y(n2149) );
BUFX8TS U1476 ( .A(n8230), .Y(n2537) );
NAND2X6TS U1477 ( .A(n10731), .B(n1251), .Y(n2921) );
BUFX8TS U1478 ( .A(n2453), .Y(n8920) );
OR2X4TS U1479 ( .A(n7804), .B(n1188), .Y(n8845) );
NAND2X6TS U1480 ( .A(n1347), .B(n10764), .Y(n10777) );
BUFX3TS U1481 ( .A(n5540), .Y(n2128) );
INVX4TS U1482 ( .A(n3057), .Y(n1962) );
INVX4TS U1483 ( .A(n2979), .Y(n1983) );
NAND2X4TS U1484 ( .A(n2466), .B(n2280), .Y(n10767) );
XNOR2X2TS U1485 ( .A(n8534), .B(n8533), .Y(n8576) );
OAI22X2TS U1486 ( .A0(n6599), .A1(n1961), .B0(n6639), .B1(n2098), .Y(n6620)
);
BUFX3TS U1487 ( .A(n3644), .Y(n1987) );
BUFX12TS U1488 ( .A(n2577), .Y(n1940) );
OAI22X2TS U1489 ( .A0(n8530), .A1(n1557), .B0(n8980), .B1(n5779), .Y(n5930)
);
ADDFHX2TS U1490 ( .A(n5943), .B(n5942), .CI(n5941), .CO(n5929), .S(n6419) );
NOR2X2TS U1491 ( .A(n4402), .B(n2113), .Y(n1065) );
ADDFHX2TS U1492 ( .A(n6609), .B(n6608), .CI(n6607), .CO(n6588), .S(n6653) );
INVX4TS U1493 ( .A(n3176), .Y(n1973) );
ADDFHX2TS U1494 ( .A(n4388), .B(n4386), .CI(n4387), .CO(n9770), .S(n9804) );
XNOR2X2TS U1495 ( .A(n2484), .B(n6775), .Y(n5784) );
INVX12TS U1496 ( .A(n2573), .Y(n2181) );
NAND2X2TS U1497 ( .A(n2933), .B(n2932), .Y(n8760) );
INVX3TS U1498 ( .A(n995), .Y(n1993) );
BUFX6TS U1499 ( .A(n8945), .Y(n2056) );
OR2X6TS U1500 ( .A(n5876), .B(n5875), .Y(n1316) );
INVX2TS U1501 ( .A(n6668), .Y(n6705) );
XOR2X1TS U1502 ( .A(n8511), .B(n8897), .Y(n995) );
INVX2TS U1503 ( .A(n1565), .Y(n4633) );
OR2X6TS U1504 ( .A(n2177), .B(n2393), .Y(n10789) );
INVX4TS U1505 ( .A(n8241), .Y(n2933) );
BUFX4TS U1506 ( .A(n5735), .Y(n2614) );
INVX4TS U1507 ( .A(n6452), .Y(n6453) );
BUFX8TS U1508 ( .A(n2504), .Y(n1960) );
OR2X6TS U1509 ( .A(n6439), .B(n2608), .Y(n10764) );
NAND2X4TS U1510 ( .A(n2522), .B(n839), .Y(n8719) );
NAND2X2TS U1511 ( .A(n6871), .B(n6870), .Y(n9291) );
BUFX6TS U1512 ( .A(n913), .Y(n2233) );
BUFX4TS U1513 ( .A(n8931), .Y(n2331) );
NOR2X1TS U1514 ( .A(n4064), .B(n7031), .Y(n4091) );
NOR2BX2TS U1515 ( .AN(n1859), .B(n2577), .Y(n6609) );
NAND2XLTS U1516 ( .A(n7656), .B(n7658), .Y(n7657) );
BUFX8TS U1517 ( .A(n8516), .Y(n1862) );
XNOR2X2TS U1518 ( .A(n8540), .B(n1024), .Y(n4293) );
BUFX12TS U1519 ( .A(n8892), .Y(n886) );
NAND2X6TS U1520 ( .A(n8470), .B(n8477), .Y(n11007) );
XOR2X2TS U1521 ( .A(n2549), .B(n2814), .Y(n4296) );
BUFX12TS U1522 ( .A(n2632), .Y(n1027) );
BUFX6TS U1523 ( .A(n8530), .Y(n1823) );
BUFX16TS U1524 ( .A(n8950), .Y(n8583) );
XNOR2X2TS U1525 ( .A(n6966), .B(n6967), .Y(n2796) );
BUFX16TS U1526 ( .A(n1020), .Y(n1894) );
XNOR2X2TS U1527 ( .A(n8894), .B(n8626), .Y(n6530) );
XNOR2X2TS U1528 ( .A(n8444), .B(n1024), .Y(n4404) );
CLKINVX6TS U1529 ( .A(n6635), .Y(n1928) );
CLKINVX6TS U1530 ( .A(n2035), .Y(n2036) );
XOR2X2TS U1531 ( .A(n5790), .B(n5791), .Y(n3218) );
NOR2X4TS U1532 ( .A(n7734), .B(n11387), .Y(n9227) );
INVX3TS U1533 ( .A(n6874), .Y(n2850) );
OAI22X2TS U1534 ( .A0(n2434), .A1(n3202), .B0(n2550), .B1(n12030), .Y(n9461)
);
BUFX4TS U1535 ( .A(n8533), .Y(n1966) );
NAND2X2TS U1536 ( .A(n7798), .B(n1189), .Y(n8864) );
NAND2X2TS U1537 ( .A(n7797), .B(n11375), .Y(n8879) );
BUFX4TS U1538 ( .A(n8518), .Y(n1908) );
NAND2X2TS U1539 ( .A(n7744), .B(n1130), .Y(n10668) );
NAND2X2TS U1540 ( .A(n7743), .B(n1154), .Y(n10645) );
NAND2XLTS U1541 ( .A(n7791), .B(n7790), .Y(n7792) );
NAND2XLTS U1542 ( .A(n7637), .B(n7642), .Y(n7638) );
NAND2XLTS U1543 ( .A(n7685), .B(n7684), .Y(n7686) );
NAND2XLTS U1544 ( .A(n7676), .B(n7675), .Y(n7677) );
NAND2X2TS U1545 ( .A(n7795), .B(n11380), .Y(n10694) );
NAND2X2TS U1546 ( .A(n7804), .B(n1188), .Y(n8844) );
ADDFHX2TS U1547 ( .A(n6343), .B(n6342), .CI(n6341), .CO(n6340), .S(n6358) );
NAND2XLTS U1548 ( .A(n7634), .B(n7643), .Y(n7631) );
NAND2X1TS U1549 ( .A(n7720), .B(n9142), .Y(n7722) );
NAND2XLTS U1550 ( .A(n7836), .B(n1126), .Y(n7654) );
BUFX4TS U1551 ( .A(n3644), .Y(n1986) );
INVX4TS U1552 ( .A(n8539), .Y(n1058) );
BUFX6TS U1553 ( .A(n6964), .Y(n2980) );
BUFX8TS U1554 ( .A(n8577), .Y(n2019) );
NOR2X2TS U1555 ( .A(n7732), .B(n11393), .Y(n8722) );
INVX4TS U1556 ( .A(n1906), .Y(n1907) );
OR2X2TS U1557 ( .A(n6673), .B(n6674), .Y(n3237) );
CLKBUFX2TS U1558 ( .A(n5505), .Y(n785) );
CLKXOR2X2TS U1559 ( .A(n1571), .B(n1570), .Y(n1569) );
BUFX4TS U1560 ( .A(n3600), .Y(n2113) );
XNOR2X2TS U1561 ( .A(n1028), .B(n6775), .Y(n6553) );
ADDFHX2TS U1562 ( .A(n4477), .B(n4476), .CI(n4475), .CO(n4478), .S(n4495) );
XOR2X2TS U1563 ( .A(n3345), .B(n2814), .Y(n4295) );
ADDFHX2TS U1564 ( .A(n7197), .B(n7196), .CI(n7195), .CO(n7351), .S(n7199) );
AOI21X1TS U1565 ( .A0(n7720), .A1(n9141), .B0(n7719), .Y(n7721) );
INVX2TS U1566 ( .A(n5819), .Y(n1636) );
INVX4TS U1567 ( .A(n5496), .Y(n966) );
INVX2TS U1568 ( .A(n7158), .Y(n940) );
BUFX12TS U1569 ( .A(n8579), .Y(n2259) );
BUFX6TS U1570 ( .A(n8539), .Y(n1255) );
INVX2TS U1571 ( .A(n2687), .Y(n2769) );
OR2X6TS U1572 ( .A(n6870), .B(n6871), .Y(n2805) );
BUFX8TS U1573 ( .A(n8933), .Y(n1020) );
INVX2TS U1574 ( .A(n1970), .Y(n1972) );
INVX2TS U1575 ( .A(n6926), .Y(n2132) );
NAND2X1TS U1576 ( .A(n11440), .B(n11441), .Y(n7919) );
INVX3TS U1577 ( .A(n6686), .Y(n6965) );
INVX4TS U1578 ( .A(n1800), .Y(n2770) );
BUFX4TS U1579 ( .A(n6422), .Y(n2177) );
BUFX4TS U1580 ( .A(n8224), .Y(n2522) );
INVX12TS U1581 ( .A(n6561), .Y(n1927) );
BUFX4TS U1582 ( .A(n2577), .Y(n1893) );
XNOR2X2TS U1583 ( .A(n4003), .B(n4488), .Y(n4368) );
OAI22X2TS U1584 ( .A0(n6685), .A1(n1968), .B0(n6630), .B1(n1933), .Y(n6674)
);
XNOR2X2TS U1585 ( .A(n2041), .B(n6562), .Y(n6559) );
BUFX4TS U1586 ( .A(n6241), .Y(n1338) );
BUFX8TS U1587 ( .A(n8938), .Y(n2293) );
XNOR2X2TS U1588 ( .A(n2021), .B(n2283), .Y(n6580) );
XOR2X2TS U1589 ( .A(n8889), .B(n6561), .Y(n4262) );
CLKINVX6TS U1590 ( .A(n1903), .Y(n1904) );
BUFX3TS U1591 ( .A(n8225), .Y(n839) );
BUFX12TS U1592 ( .A(n6404), .Y(n2280) );
CLKINVX2TS U1593 ( .A(n6693), .Y(n2994) );
BUFX12TS U1594 ( .A(n2484), .Y(n2338) );
NAND2X1TS U1595 ( .A(n7910), .B(n1200), .Y(n7883) );
INVX4TS U1596 ( .A(n2714), .Y(n2098) );
NAND2X1TS U1597 ( .A(n1571), .B(n1570), .Y(n1566) );
BUFX3TS U1598 ( .A(n5730), .Y(n872) );
BUFX12TS U1599 ( .A(n8510), .Y(n1926) );
INVX12TS U1600 ( .A(n1022), .Y(n2031) );
OR2X4TS U1601 ( .A(n1800), .B(n2687), .Y(n10724) );
INVX6TS U1602 ( .A(n2714), .Y(n2099) );
AOI21X2TS U1603 ( .A0(n7785), .A1(n7784), .B0(n7783), .Y(n7786) );
INVX4TS U1604 ( .A(n2979), .Y(n1982) );
NAND2BX2TS U1605 ( .AN(n1859), .B(n8510), .Y(n5499) );
BUFX12TS U1606 ( .A(n2504), .Y(n2575) );
INVX4TS U1607 ( .A(n2596), .Y(n2863) );
INVX2TS U1608 ( .A(n7031), .Y(n1906) );
AO21X1TS U1609 ( .A0(n1914), .A1(n2060), .B0(n926), .Y(n7101) );
INVX2TS U1610 ( .A(n8908), .Y(n2035) );
OAI21X2TS U1611 ( .A0(n10313), .A1(n10316), .B0(n10314), .Y(n9696) );
BUFX12TS U1612 ( .A(n8539), .Y(n2251) );
ADDFHX2TS U1613 ( .A(n4797), .B(n4798), .CI(n4796), .CO(n7458), .S(n4781) );
AOI21X2TS U1614 ( .A0(n7913), .A1(n7890), .B0(n7889), .Y(n7891) );
ADDFHX2TS U1615 ( .A(n3484), .B(n3485), .CI(n3483), .CO(n3495), .S(n3538) );
XNOR2X2TS U1616 ( .A(n8443), .B(n8619), .Y(n6586) );
BUFX4TS U1617 ( .A(n3600), .Y(n2112) );
XNOR2X2TS U1618 ( .A(n7702), .B(n7701), .Y(n7740) );
INVX4TS U1619 ( .A(n4324), .Y(n2914) );
XNOR2X2TS U1620 ( .A(n7729), .B(n11568), .Y(n7735) );
BUFX3TS U1621 ( .A(n3964), .Y(n1683) );
ADDFHX2TS U1622 ( .A(n7266), .B(n7265), .CI(n7264), .CO(n7253), .S(n8058) );
ADDFHX2TS U1623 ( .A(n7512), .B(n7513), .CI(n7511), .CO(n7549), .S(n7553) );
INVX2TS U1624 ( .A(n2814), .Y(n1036) );
ADDFHX2TS U1625 ( .A(n4453), .B(n4452), .CI(n4451), .CO(n4790), .S(n4479) );
INVX6TS U1626 ( .A(n8539), .Y(n5496) );
XOR2X2TS U1627 ( .A(n7730), .B(n11574), .Y(n7733) );
NAND2X2TS U1628 ( .A(n1568), .B(n1567), .Y(n1564) );
INVX6TS U1629 ( .A(n6552), .Y(n1016) );
INVX3TS U1630 ( .A(n5364), .Y(n871) );
ADDFHX2TS U1631 ( .A(n7349), .B(n801), .CI(n7348), .CO(n7365), .S(n7350) );
NOR2X6TS U1632 ( .A(n9133), .B(n9135), .Y(n9142) );
BUFX6TS U1633 ( .A(n6445), .Y(n2687) );
OAI22X2TS U1634 ( .A0(n1915), .A1(n976), .B0(n2059), .B1(n926), .Y(n7071) );
BUFX4TS U1635 ( .A(n2296), .Y(n1944) );
AO21X2TS U1636 ( .A0(n1853), .A1(n2063), .B0(n11674), .Y(n4469) );
CLKINVX6TS U1637 ( .A(n2154), .Y(n7072) );
OAI21X1TS U1638 ( .A0(n7065), .A1(n7064), .B0(n7063), .Y(n2441) );
NAND2X1TS U1639 ( .A(n7716), .B(n11408), .Y(n9136) );
NOR2X1TS U1640 ( .A(n11729), .B(n11651), .Y(n7890) );
INVX4TS U1641 ( .A(n1984), .Y(n1968) );
BUFX3TS U1642 ( .A(n5454), .Y(n2518) );
NOR2X1TS U1643 ( .A(n7899), .B(n11658), .Y(n7902) );
OAI21X2TS U1644 ( .A0(n7788), .A1(n7775), .B0(n7774), .Y(n7780) );
INVX8TS U1645 ( .A(n8237), .Y(n7158) );
INVX4TS U1646 ( .A(n6891), .Y(n6914) );
CLKINVX2TS U1647 ( .A(n6296), .Y(n1274) );
INVX6TS U1648 ( .A(n8533), .Y(n2814) );
XNOR2X2TS U1649 ( .A(n1565), .B(n8619), .Y(n6685) );
NOR2X2TS U1650 ( .A(n7715), .B(n11401), .Y(n9133) );
NAND2X6TS U1651 ( .A(n1642), .B(n1643), .Y(n6799) );
NAND2X2TS U1652 ( .A(n2961), .B(n2960), .Y(n7222) );
BUFX6TS U1653 ( .A(n888), .Y(n8530) );
OAI2BB1X2TS U1654 ( .A0N(n2257), .A1N(n2256), .B0(n4658), .Y(n2279) );
INVX4TS U1655 ( .A(n8510), .Y(n5500) );
OAI21X2TS U1656 ( .A0(n7730), .A1(n11592), .B0(n11593), .Y(n7731) );
INVX6TS U1657 ( .A(n3055), .Y(n2108) );
INVX3TS U1658 ( .A(n6710), .Y(n6881) );
BUFX8TS U1659 ( .A(n888), .Y(n2356) );
INVX8TS U1660 ( .A(n7668), .Y(n7785) );
OAI21X1TS U1661 ( .A0(n11728), .A1(n11594), .B0(n11595), .Y(n7889) );
AOI21X2TS U1662 ( .A0(n7702), .A1(n1137), .B0(n1158), .Y(n7696) );
NOR2X2TS U1663 ( .A(n7712), .B(n1171), .Y(n9157) );
NAND2BX2TS U1664 ( .AN(n3009), .B(n3521), .Y(n3008) );
NOR2X2TS U1665 ( .A(n4070), .B(n7031), .Y(n4099) );
NAND2X4TS U1666 ( .A(n1114), .B(n1115), .Y(n4786) );
BUFX12TS U1667 ( .A(n4351), .Y(n2050) );
OAI22X2TS U1668 ( .A0(n6691), .A1(n8616), .B0(n6886), .B1(n2097), .Y(n6915)
);
NOR2X6TS U1669 ( .A(n3277), .B(n3062), .Y(n8372) );
NAND2X2TS U1670 ( .A(n6792), .B(n6761), .Y(n10314) );
ADDFHX1TS U1671 ( .A(n2464), .B(n824), .CI(n7245), .CO(n7248), .S(n7511) );
INVX4TS U1672 ( .A(n8513), .Y(n1558) );
XNOR2X2TS U1673 ( .A(n8511), .B(n6529), .Y(n6700) );
OAI22X2TS U1674 ( .A0(n7475), .A1(n7477), .B0(n1454), .B1(n7474), .Y(n7513)
);
NAND2X6TS U1675 ( .A(n8418), .B(n1017), .Y(n3278) );
NAND2XLTS U1676 ( .A(n7778), .B(n7777), .Y(n7779) );
NOR2X6TS U1677 ( .A(n2646), .B(n2585), .Y(n10714) );
NAND2X2TS U1678 ( .A(n2479), .B(n2284), .Y(n10639) );
AOI2BB2X1TS U1679 ( .B0(n1599), .B1(n1952), .A0N(n6907), .A1N(n1852), .Y(
n6926) );
ADDFHX2TS U1680 ( .A(n6866), .B(n6865), .CI(n6864), .CO(n6872), .S(n6871) );
XNOR2X2TS U1681 ( .A(n2549), .B(n6529), .Y(n6631) );
OAI22X2TS U1682 ( .A0(n3467), .A1(n1915), .B0(n2059), .B1(n3418), .Y(n3461)
);
ADDFHX2TS U1683 ( .A(n3493), .B(n3492), .CI(n3491), .CO(n3510), .S(n3549) );
OAI22X2TS U1684 ( .A0(n6178), .A1(n5758), .B0(n6176), .B1(n5704), .Y(n5769)
);
BUFX8TS U1685 ( .A(n4351), .Y(n5488) );
CLKINVX1TS U1686 ( .A(n1929), .Y(n811) );
INVX2TS U1687 ( .A(n2044), .Y(n1259) );
OAI21X1TS U1688 ( .A0(n7859), .A1(n1181), .B0(n11572), .Y(n7843) );
INVX12TS U1689 ( .A(n8551), .Y(n1818) );
OAI22X4TS U1690 ( .A0(n6544), .A1(n1969), .B0(n6451), .B1(n1933), .Y(n6552)
);
XNOR2X2TS U1691 ( .A(n4003), .B(n6636), .Y(n6643) );
INVX6TS U1692 ( .A(n2686), .Y(n6566) );
BUFX6TS U1693 ( .A(n4488), .Y(n2453) );
INVX6TS U1694 ( .A(n6623), .Y(n2646) );
AO21X2TS U1695 ( .A0(n2105), .A1(n1921), .B0(n7444), .Y(n7464) );
BUFX4TS U1696 ( .A(n2592), .Y(n801) );
OAI2BB1X2TS U1697 ( .A0N(n6818), .A1N(n6819), .B0(n3173), .Y(n6867) );
BUFX6TS U1698 ( .A(n6542), .Y(n2526) );
INVX2TS U1699 ( .A(n4094), .Y(n2469) );
NAND2X6TS U1700 ( .A(n3036), .B(n3035), .Y(n3034) );
NAND2X4TS U1701 ( .A(n11020), .B(n10632), .Y(n10637) );
NAND2X1TS U1702 ( .A(n1614), .B(n7756), .Y(n2232) );
INVX2TS U1703 ( .A(n4660), .Y(n2256) );
OAI22X2TS U1704 ( .A0(n1911), .A1(n3406), .B0(n2030), .B1(n4432), .Y(n4436)
);
INVX2TS U1705 ( .A(n4659), .Y(n2257) );
INVX4TS U1706 ( .A(n6708), .Y(n6882) );
BUFX8TS U1707 ( .A(n4358), .Y(n8897) );
BUFX4TS U1708 ( .A(n6579), .Y(n2585) );
OR2X4TS U1709 ( .A(n1916), .B(n4791), .Y(n1115) );
OR2X6TS U1710 ( .A(n2100), .B(n4458), .Y(n1114) );
INVX12TS U1711 ( .A(n8441), .Y(n2020) );
BUFX4TS U1712 ( .A(n2265), .Y(n8626) );
INVX4TS U1713 ( .A(n2190), .Y(n7668) );
OAI2BB1X2TS U1714 ( .A0N(DP_OP_168J26_122_4811_n8218), .A1N(n7477), .B0(
n1454), .Y(n7043) );
XNOR2X2TS U1715 ( .A(n2041), .B(n6775), .Y(n6886) );
CLKINVX6TS U1716 ( .A(n2459), .Y(n1852) );
BUFX12TS U1717 ( .A(n3600), .Y(n8907) );
NAND2X6TS U1718 ( .A(n934), .B(n933), .Y(n3434) );
INVX12TS U1719 ( .A(n1082), .Y(n4684) );
XNOR2X2TS U1720 ( .A(n1596), .B(n5459), .Y(n1595) );
OAI21X2TS U1721 ( .A0(n1151), .A1(n1191), .B0(n1120), .Y(n9177) );
NOR2X1TS U1722 ( .A(n7854), .B(n7866), .Y(n7849) );
NAND2X1TS U1723 ( .A(n7910), .B(n7909), .Y(n7915) );
NAND2X6TS U1724 ( .A(n1542), .B(n1541), .Y(n5431) );
XNOR2X2TS U1725 ( .A(n7442), .B(n1810), .Y(n7069) );
BUFX3TS U1726 ( .A(n4279), .Y(n881) );
CLKBUFX2TS U1727 ( .A(n5458), .Y(n905) );
INVX4TS U1728 ( .A(n7868), .Y(n7855) );
BUFX8TS U1729 ( .A(n6434), .Y(n8938) );
NAND2X6TS U1730 ( .A(n2912), .B(n2599), .Y(n4054) );
NAND2X1TS U1731 ( .A(n1281), .B(n7772), .Y(n7765) );
XNOR2X2TS U1732 ( .A(n1881), .B(n951), .Y(n4457) );
ADDFHX2TS U1733 ( .A(n7988), .B(n7989), .CI(n7987), .CO(n8059), .S(n8035) );
ADDFHX2TS U1734 ( .A(n3951), .B(n3952), .CI(n3953), .CO(n4625), .S(n3984) );
NOR2X6TS U1735 ( .A(n2479), .B(n2284), .Y(n10638) );
ADDFHX2TS U1736 ( .A(n6193), .B(n6192), .CI(n6191), .CO(n6215), .S(n6202) );
OAI22X2TS U1737 ( .A0(n2077), .A1(n1816), .B0(n2571), .B1(n2440), .Y(n7245)
);
NAND2X6TS U1738 ( .A(n2972), .B(n1408), .Y(n2971) );
INVX8TS U1739 ( .A(n3168), .Y(n8418) );
NAND2BX1TS U1740 ( .AN(n1859), .B(n6562), .Y(n6560) );
ADDFHX2TS U1741 ( .A(n3860), .B(n3859), .CI(n3858), .CO(n4011), .S(n4250) );
INVX4TS U1742 ( .A(n8417), .Y(n2803) );
XNOR2X2TS U1743 ( .A(n1031), .B(n952), .Y(n7070) );
XNOR2X2TS U1744 ( .A(n4003), .B(n6435), .Y(n6430) );
XNOR2X2TS U1745 ( .A(n6562), .B(n2044), .Y(n6563) );
OAI22X2TS U1746 ( .A0(n5884), .A1(n1853), .B0(n2063), .B1(n5883), .Y(n6316)
);
OAI22X2TS U1747 ( .A0(n2103), .A1(n6007), .B0(n6176), .B1(n6056), .Y(n6061)
);
OAI21X1TS U1748 ( .A0(n7859), .A1(n7866), .B0(n7870), .Y(n7848) );
INVX6TS U1749 ( .A(n8370), .Y(n1017) );
CLKXOR2X2TS U1750 ( .A(n3349), .B(DP_OP_168J26_122_4811_n3215), .Y(n3350) );
INVX12TS U1751 ( .A(n6635), .Y(n1929) );
NAND2X2TS U1752 ( .A(n6853), .B(n6852), .Y(n8358) );
NOR2X4TS U1753 ( .A(n6855), .B(n6854), .Y(n8370) );
OR2X4TS U1754 ( .A(n6698), .B(n6668), .Y(n11020) );
INVX2TS U1755 ( .A(n7697), .Y(n7730) );
INVX2TS U1756 ( .A(n6767), .Y(n6769) );
INVX6TS U1757 ( .A(n6600), .Y(n6623) );
NAND2X1TS U1758 ( .A(n3628), .B(n3381), .Y(n1408) );
INVX2TS U1759 ( .A(n6743), .Y(n6748) );
NAND2X4TS U1760 ( .A(n3080), .B(n3079), .Y(n5194) );
INVX2TS U1761 ( .A(n5409), .Y(n3087) );
BUFX3TS U1762 ( .A(n1715), .Y(n824) );
AO21X2TS U1763 ( .A0(n6069), .A1(n2450), .B0(n2521), .Y(n3473) );
INVX2TS U1764 ( .A(n7867), .Y(n7854) );
OAI21X2TS U1765 ( .A0(n6818), .A1(n6819), .B0(n6817), .Y(n3173) );
OAI22X2TS U1766 ( .A0(n7490), .A1(n3451), .B0(n1624), .B1(n6160), .Y(n3420)
);
INVX6TS U1767 ( .A(n1971), .Y(n7031) );
XNOR2X2TS U1768 ( .A(n2070), .B(n951), .Y(n3468) );
NAND2XLTS U1769 ( .A(n11743), .B(DP_OP_168J26_122_4811_n3498), .Y(n3625) );
INVX4TS U1770 ( .A(n3157), .Y(n1933) );
XOR2X2TS U1771 ( .A(n8037), .B(n8038), .Y(n2635) );
INVX6TS U1772 ( .A(n3055), .Y(n2109) );
INVX4TS U1773 ( .A(n7486), .Y(n1877) );
BUFX12TS U1774 ( .A(n2581), .Y(n8516) );
CLKINVX6TS U1775 ( .A(n1984), .Y(n1969) );
BUFX3TS U1776 ( .A(n7773), .Y(n1281) );
AO21X2TS U1777 ( .A0(n8025), .A1(n1900), .B0(n1518), .Y(n7025) );
XOR2X2TS U1778 ( .A(n2643), .B(n6181), .Y(n3470) );
INVX12TS U1779 ( .A(n3282), .Y(n2044) );
INVX8TS U1780 ( .A(n8887), .Y(n8087) );
INVX2TS U1781 ( .A(n7872), .Y(n7859) );
NAND2X6TS U1782 ( .A(n6855), .B(n6854), .Y(n8371) );
INVX3TS U1783 ( .A(n4013), .Y(n1658) );
INVX2TS U1784 ( .A(n10624), .Y(n5090) );
CLKXOR2X2TS U1785 ( .A(n1565), .B(n2032), .Y(n6907) );
BUFX3TS U1786 ( .A(n2647), .Y(n1955) );
NAND2X4TS U1787 ( .A(n936), .B(n937), .Y(n5576) );
XNOR2X2TS U1788 ( .A(n6055), .B(n1669), .Y(n5704) );
NAND2X4TS U1789 ( .A(n3946), .B(n3935), .Y(n3614) );
XOR2X2TS U1790 ( .A(n2349), .B(n1871), .Y(n6923) );
XNOR2X2TS U1791 ( .A(n1220), .B(n1694), .Y(n7472) );
CLKAND2X2TS U1792 ( .A(n3590), .B(n3589), .Y(n1724) );
NAND2BX2TS U1793 ( .AN(n1859), .B(n8508), .Y(n6406) );
ADDFHX2TS U1794 ( .A(n4682), .B(n4681), .CI(n4680), .CO(n8198), .S(n4657) );
CLKXOR2X2TS U1795 ( .A(n3642), .B(n11755), .Y(n3643) );
OR2X4TS U1796 ( .A(n1910), .B(n1622), .Y(n933) );
XNOR2X2TS U1797 ( .A(n2549), .B(n1946), .Y(n6544) );
XNOR2X2TS U1798 ( .A(n5567), .B(n1810), .Y(n7041) );
BUFX16TS U1799 ( .A(n4620), .Y(n4488) );
OR2X4TS U1800 ( .A(n2908), .B(n7492), .Y(n1337) );
OAI22X2TS U1801 ( .A0(n2104), .A1(n5607), .B0(n5681), .B1(n1919), .Y(n5647)
);
CMPR22X2TS U1802 ( .A(n6046), .B(n6045), .CO(n6167), .S(n6060) );
XNOR2X2TS U1803 ( .A(n1881), .B(n2669), .Y(n3419) );
NAND2X4TS U1804 ( .A(n6876), .B(n759), .Y(n832) );
NAND2X6TS U1805 ( .A(n6698), .B(n6668), .Y(n11019) );
XNOR2X2TS U1806 ( .A(n6849), .B(n8508), .Y(n6407) );
OAI22X1TS U1807 ( .A0(n2102), .A1(n6162), .B0(n6176), .B1(n6177), .Y(n6171)
);
OAI22X1TS U1808 ( .A0(n2104), .A1(n5608), .B0(n1919), .B1(n5607), .Y(n5616)
);
NAND2X2TS U1809 ( .A(n6750), .B(n6751), .Y(n3301) );
OAI22X2TS U1810 ( .A0(n1934), .A1(n3729), .B0(n1991), .B1(n3980), .Y(n3974)
);
AO21XLTS U1811 ( .A0(n7911), .A1(n1165), .B0(n11588), .Y(n7912) );
NAND2BX1TS U1812 ( .AN(n7759), .B(n7758), .Y(n7760) );
NAND2X1TS U1813 ( .A(n11731), .B(n766), .Y(n3944) );
INVX2TS U1814 ( .A(n3639), .Y(n892) );
NAND2X1TS U1815 ( .A(n6741), .B(n6757), .Y(n11302) );
INVX2TS U1816 ( .A(n6148), .Y(n2081) );
AO21X2TS U1817 ( .A0(n8022), .A1(n8020), .B0(n1706), .Y(n7261) );
OR2X2TS U1818 ( .A(n7492), .B(n5563), .Y(n936) );
BUFX3TS U1819 ( .A(n4215), .Y(n2268) );
CLKINVX6TS U1820 ( .A(n7243), .Y(n7349) );
CLKINVX6TS U1821 ( .A(n6692), .Y(n3147) );
NOR2X4TS U1822 ( .A(n6772), .B(n6768), .Y(n11059) );
NOR2X2TS U1823 ( .A(n6757), .B(n6741), .Y(n11301) );
INVX2TS U1824 ( .A(n1750), .Y(n11308) );
NAND2X2TS U1825 ( .A(n6746), .B(n6743), .Y(n11309) );
BUFX6TS U1826 ( .A(n1048), .Y(n910) );
CLKXOR2X2TS U1827 ( .A(n1271), .B(n916), .Y(n5954) );
XNOR2X2TS U1828 ( .A(n1881), .B(n916), .Y(n5607) );
OAI21X2TS U1829 ( .A0(n7759), .A1(n7756), .B0(n7758), .Y(n7761) );
XNOR2X2TS U1830 ( .A(n1807), .B(n1694), .Y(n5569) );
INVX4TS U1831 ( .A(n6773), .Y(n6879) );
BUFX16TS U1832 ( .A(n838), .Y(n2030) );
NAND2X2TS U1833 ( .A(n2451), .B(n759), .Y(n11111) );
XNOR2X2TS U1834 ( .A(n2074), .B(n2643), .Y(n7484) );
INVX6TS U1835 ( .A(n6435), .Y(n6433) );
BUFX4TS U1836 ( .A(n4216), .Y(n2281) );
BUFX12TS U1837 ( .A(n8511), .Y(n1028) );
XNOR2X2TS U1838 ( .A(n1882), .B(n1253), .Y(n5764) );
INVX4TS U1839 ( .A(n2658), .Y(n3233) );
INVX2TS U1840 ( .A(n7757), .Y(n1614) );
OAI22X2TS U1841 ( .A0(n1084), .A1(n5675), .B0(n2080), .B1(n5674), .Y(n5855)
);
INVX6TS U1842 ( .A(n1970), .Y(n1024) );
CLKBUFX2TS U1843 ( .A(n3943), .Y(n766) );
NAND2X2TS U1844 ( .A(n6851), .B(n6850), .Y(n9330) );
BUFX12TS U1845 ( .A(n4357), .Y(n2581) );
NAND2X1TS U1846 ( .A(n11744), .B(n2274), .Y(n4079) );
NAND2X1TS U1847 ( .A(n11732), .B(n2275), .Y(n3353) );
XOR2X2TS U1848 ( .A(n2964), .B(n7137), .Y(n2963) );
CLKINVX3TS U1849 ( .A(n3942), .Y(n781) );
CLKXOR2X2TS U1850 ( .A(n6181), .B(n1291), .Y(n5608) );
NAND2X2TS U1851 ( .A(n5462), .B(n1731), .Y(n3120) );
XOR2X2TS U1852 ( .A(n6161), .B(n6160), .Y(n6177) );
NAND2BX2TS U1853 ( .AN(n1859), .B(n6435), .Y(n6432) );
XNOR2X2TS U1854 ( .A(n3772), .B(DP_OP_168J26_122_4811_n3214), .Y(n4620) );
NOR2X2TS U1855 ( .A(n3641), .B(DP_OP_168J26_122_4811_n3232), .Y(n3642) );
OAI22X2TS U1856 ( .A0(n6003), .A1(n1223), .B0(n973), .B1(n6002), .Y(n6045)
);
XNOR2X2TS U1857 ( .A(DP_OP_168J26_122_4811_n3229), .B(n11784), .Y(n3347) );
XNOR2X2TS U1858 ( .A(n2323), .B(n6160), .Y(n5766) );
NAND2X2TS U1859 ( .A(n1615), .B(n3834), .Y(n1765) );
XOR2X2TS U1860 ( .A(n1608), .B(n2930), .Y(n7019) );
XOR2X2TS U1861 ( .A(n1685), .B(n916), .Y(n5591) );
XNOR2X2TS U1862 ( .A(n6145), .B(n6160), .Y(n6044) );
ADDFHX2TS U1863 ( .A(n3544), .B(n3545), .CI(n3543), .CO(n3554), .S(n3888) );
XNOR2X2TS U1864 ( .A(n1805), .B(n7441), .Y(n5570) );
AOI21X2TS U1865 ( .A0(n7873), .A1(n7872), .B0(n7871), .Y(n1098) );
XNOR2X2TS U1866 ( .A(n2397), .B(n6145), .Y(n5800) );
INVX8TS U1867 ( .A(n856), .Y(n3946) );
XOR2X2TS U1868 ( .A(n1292), .B(n6055), .Y(n6175) );
OAI22X2TS U1869 ( .A0(n2222), .A1(n7259), .B0(n8009), .B1(n7053), .Y(n7262)
);
ADDFHX2TS U1870 ( .A(n6839), .B(n6838), .CI(n6837), .CO(n6854), .S(n6853) );
INVX2TS U1871 ( .A(n4236), .Y(n924) );
ADDFHX2TS U1872 ( .A(n4610), .B(n4608), .CI(n4609), .CO(n4680), .S(n4614) );
BUFX6TS U1873 ( .A(DP_OP_168J26_122_4811_n8218), .Y(n7474) );
INVX2TS U1874 ( .A(n840), .Y(n1685) );
NAND2BX2TS U1875 ( .AN(n5666), .B(n2403), .Y(n5553) );
OR2X2TS U1876 ( .A(n6737), .B(n6739), .Y(n11297) );
INVX12TS U1877 ( .A(n7479), .Y(n2059) );
BUFX6TS U1878 ( .A(n5505), .Y(n2504) );
INVX12TS U1879 ( .A(n7479), .Y(n2060) );
XNOR2X2TS U1880 ( .A(n1807), .B(n7488), .Y(n6221) );
NOR2X4TS U1881 ( .A(n2180), .B(n2891), .Y(n2247) );
XNOR2X2TS U1882 ( .A(n6055), .B(n2643), .Y(n5859) );
BUFX16TS U1883 ( .A(n7473), .Y(n729) );
INVX6TS U1884 ( .A(n1025), .Y(n1814) );
OAI22X1TS U1885 ( .A0(n4546), .A1(n1822), .B0(n1923), .B1(n4595), .Y(n4609)
);
OAI22X1TS U1886 ( .A0(n2029), .A1(n6015), .B0(n11754), .B1(n6014), .Y(n6019)
);
INVX2TS U1887 ( .A(n3580), .Y(n3586) );
XOR2X2TS U1888 ( .A(n5273), .B(n3202), .Y(n7052) );
BUFX12TS U1889 ( .A(n7441), .Y(n2440) );
BUFX6TS U1890 ( .A(n6709), .Y(n2290) );
XNOR2X2TS U1891 ( .A(n2323), .B(n1302), .Y(n6059) );
INVX12TS U1892 ( .A(n3758), .Y(n1497) );
NAND2X2TS U1893 ( .A(n3136), .B(n3135), .Y(n8054) );
CLKINVX3TS U1894 ( .A(n4604), .Y(n4542) );
OAI22X2TS U1895 ( .A0(n2159), .A1(n6147), .B0(n973), .B1(n6140), .Y(n6227)
);
BUFX3TS U1896 ( .A(n6601), .Y(n8542) );
INVX3TS U1897 ( .A(n6757), .Y(n6764) );
INVX8TS U1898 ( .A(n1025), .Y(n1914) );
NAND2X6TS U1899 ( .A(n2701), .B(n2700), .Y(n3745) );
INVX12TS U1900 ( .A(n2979), .Y(n8574) );
OAI22X2TS U1901 ( .A0(n3976), .A1(n1806), .B0(n5320), .B1(n4539), .Y(n4532)
);
NAND2X2TS U1902 ( .A(n3753), .B(n12030), .Y(n3628) );
BUFX2TS U1903 ( .A(n3601), .Y(n739) );
BUFX12TS U1904 ( .A(n3393), .Y(n2073) );
OAI22X2TS U1905 ( .A0(n795), .A1(n4670), .B0(n2115), .B1(n7994), .Y(n8114)
);
OAI22X1TS U1906 ( .A0(n6836), .A1(n6921), .B0(n6847), .B1(n8614), .Y(n6837)
);
ADDFHX2TS U1907 ( .A(n3721), .B(n3719), .CI(n3720), .CO(n3726), .S(n3862) );
NAND2X1TS U1908 ( .A(n5033), .B(n5031), .Y(n3130) );
INVX6TS U1909 ( .A(n6636), .Y(n6635) );
XNOR2X2TS U1910 ( .A(n2677), .B(n1228), .Y(n5563) );
CLKBUFX2TS U1911 ( .A(n6891), .Y(n2451) );
XNOR2X2TS U1912 ( .A(n2677), .B(n1291), .Y(n5651) );
OAI2BB2X2TS U1913 ( .B0(n4596), .B1(n4984), .A0N(n1421), .A1N(n2406), .Y(
n4666) );
NAND2X1TS U1914 ( .A(n4248), .B(n4249), .Y(n3239) );
OAI22X1TS U1915 ( .A0(n8025), .A1(n4593), .B0(n1900), .B1(n4671), .Y(n4672)
);
NAND2X2TS U1916 ( .A(n7867), .B(n7873), .Y(n7874) );
NAND2X6TS U1917 ( .A(n1793), .B(n1792), .Y(n805) );
XNOR2X2TS U1918 ( .A(n6714), .B(n2323), .Y(n6001) );
XNOR2X2TS U1919 ( .A(n6145), .B(n6156), .Y(n5963) );
ADDFHX2TS U1920 ( .A(n8049), .B(n8050), .CI(n8048), .CO(n8056), .S(n8126) );
INVX2TS U1921 ( .A(n3598), .Y(n3101) );
ADDFHX2TS U1922 ( .A(n8018), .B(n8016), .CI(n8017), .CO(n8038), .S(n8055) );
NAND2X2TS U1923 ( .A(n4073), .B(n3229), .Y(n4077) );
XOR2X2TS U1924 ( .A(n1243), .B(n1275), .Y(n3363) );
CLKINVX2TS U1925 ( .A(n923), .Y(n8004) );
XNOR2X2TS U1926 ( .A(n6055), .B(n7441), .Y(n5860) );
XNOR2X2TS U1927 ( .A(n1261), .B(n1645), .Y(n7060) );
BUFX8TS U1928 ( .A(n2296), .Y(n1945) );
CLKINVX2TS U1929 ( .A(n2677), .Y(n783) );
INVX2TS U1930 ( .A(n1423), .Y(n918) );
INVX2TS U1931 ( .A(n2074), .Y(n880) );
BUFX16TS U1932 ( .A(n3394), .Y(n2100) );
INVX12TS U1933 ( .A(n5665), .Y(n1910) );
XNOR2X2TS U1934 ( .A(n5254), .B(n790), .Y(n3668) );
XOR2X2TS U1935 ( .A(n1931), .B(n11780), .Y(n2358) );
INVX6TS U1936 ( .A(n1395), .Y(n1921) );
INVX6TS U1937 ( .A(n1917), .Y(n1918) );
OR2X6TS U1938 ( .A(n3878), .B(n3307), .Y(n1298) );
INVX6TS U1939 ( .A(n6148), .Y(n973) );
AO21X2TS U1940 ( .A0(n5302), .A1(n1925), .B0(n5283), .Y(n4529) );
BUFX8TS U1941 ( .A(n964), .Y(n1220) );
INVX6TS U1942 ( .A(n6745), .Y(n6750) );
CLKINVX3TS U1943 ( .A(n8011), .Y(n1663) );
INVX2TS U1944 ( .A(n7140), .Y(n2965) );
INVX6TS U1945 ( .A(n1242), .Y(n1243) );
INVX3TS U1946 ( .A(n7275), .Y(n1095) );
INVX6TS U1947 ( .A(n1952), .Y(n1953) );
NOR2X2TS U1948 ( .A(n3578), .B(n3256), .Y(n3255) );
INVX12TS U1949 ( .A(n6006), .Y(n1853) );
OAI2BB1X2TS U1950 ( .A0N(n3137), .A1N(n3138), .B0(n8116), .Y(n3136) );
NAND2X6TS U1951 ( .A(DP_OP_168J26_122_4811_n8191), .B(n3417), .Y(n1222) );
XNOR2X2TS U1952 ( .A(n1805), .B(n1228), .Y(n6016) );
XNOR2X2TS U1953 ( .A(n1608), .B(n2566), .Y(n4670) );
BUFX16TS U1954 ( .A(n3411), .Y(n7445) );
INVX4TS U1955 ( .A(n5461), .Y(n1793) );
BUFX12TS U1956 ( .A(n1086), .Y(n1083) );
BUFX16TS U1957 ( .A(n4455), .Y(n7486) );
XNOR2X2TS U1958 ( .A(n1808), .B(n1669), .Y(n6222) );
NAND2X2TS U1959 ( .A(n6737), .B(n6739), .Y(n11296) );
BUFX16TS U1960 ( .A(n7477), .Y(n2379) );
OR2X6TS U1961 ( .A(n974), .B(n4140), .Y(n874) );
BUFX16TS U1962 ( .A(n3411), .Y(n2104) );
INVX2TS U1963 ( .A(n4597), .Y(n1664) );
NAND2X1TS U1964 ( .A(n3369), .B(n3368), .Y(n3370) );
CLKBUFX2TS U1965 ( .A(n3621), .Y(n2275) );
BUFX4TS U1966 ( .A(n4067), .Y(n6921) );
BUFX8TS U1967 ( .A(n3391), .Y(n2103) );
NAND2X2TS U1968 ( .A(n6781), .B(n6780), .Y(n10334) );
NAND2X1TS U1969 ( .A(n5220), .B(n2710), .Y(n2708) );
INVX8TS U1970 ( .A(n1917), .Y(n1919) );
INVX6TS U1971 ( .A(n8619), .Y(n2950) );
BUFX12TS U1972 ( .A(n3411), .Y(n2105) );
OR2X4TS U1973 ( .A(n4114), .B(n2450), .Y(n1248) );
NAND2X6TS U1974 ( .A(n2816), .B(n775), .Y(n3360) );
OR2X4TS U1975 ( .A(n4134), .B(n5950), .Y(n1297) );
XNOR2X2TS U1976 ( .A(n1861), .B(n1717), .Y(n4667) );
NAND2X2TS U1977 ( .A(n11780), .B(n1931), .Y(n2332) );
XNOR2X2TS U1978 ( .A(n7273), .B(n944), .Y(n4594) );
XNOR2X2TS U1979 ( .A(n5256), .B(n1644), .Y(n4591) );
XOR2X2TS U1980 ( .A(n932), .B(n1644), .Y(n3729) );
AOI21X2TS U1981 ( .A0(n11179), .A1(n11180), .B0(n5035), .Y(n10336) );
CLKINVX2TS U1982 ( .A(n3754), .Y(n2891) );
XNOR2X2TS U1983 ( .A(n1808), .B(n1291), .Y(n6014) );
XNOR2X2TS U1984 ( .A(n2045), .B(n790), .Y(n4592) );
OR2X4TS U1985 ( .A(n928), .B(n2448), .Y(n1428) );
XNOR2X2TS U1986 ( .A(n6775), .B(n2022), .Y(n2976) );
NAND2BX2TS U1987 ( .AN(n3138), .B(n3139), .Y(n3135) );
CLKBUFX3TS U1988 ( .A(n4078), .Y(n2274) );
ADDFHX2TS U1989 ( .A(n4871), .B(n4870), .CI(n4869), .CO(n5144), .S(n4872) );
XOR2X2TS U1990 ( .A(n868), .B(n3202), .Y(n4598) );
XNOR2X2TS U1991 ( .A(n2022), .B(n6906), .Y(n6847) );
OAI22X2TS U1992 ( .A0(n2090), .A1(n6097), .B0(n6096), .B1(n1226), .Y(n6124)
);
INVX4TS U1993 ( .A(n5462), .Y(n1792) );
BUFX8TS U1994 ( .A(n5561), .Y(n976) );
XOR2X2TS U1995 ( .A(n7441), .B(n6181), .Y(n3486) );
XOR2X2TS U1996 ( .A(n5174), .B(n2930), .Y(n4553) );
CLKXOR2X2TS U1997 ( .A(n2521), .B(n1291), .Y(n6146) );
XNOR2X1TS U1998 ( .A(n6884), .B(n6906), .Y(n6846) );
INVX4TS U1999 ( .A(n5561), .Y(n769) );
BUFX20TS U2000 ( .A(n4428), .Y(n838) );
CLKINVX2TS U2001 ( .A(n2970), .Y(n3380) );
OAI22X2TS U2002 ( .A0(n5167), .A1(n2107), .B0(n1943), .B1(n5238), .Y(n5233)
);
XNOR2X2TS U2003 ( .A(n2094), .B(n1717), .Y(n7259) );
XNOR2X2TS U2004 ( .A(n1808), .B(n1228), .Y(n6035) );
BUFX6TS U2005 ( .A(n964), .Y(n2403) );
INVX8TS U2006 ( .A(n2757), .Y(n2090) );
INVX8TS U2007 ( .A(n7491), .Y(n2042) );
BUFX16TS U2008 ( .A(n7490), .Y(n2399) );
BUFX8TS U2009 ( .A(n1257), .Y(n7441) );
INVX8TS U2010 ( .A(n1291), .Y(n1292) );
BUFX16TS U2011 ( .A(n8540), .Y(n2349) );
INVX12TS U2012 ( .A(n6006), .Y(n1866) );
AND2X6TS U2013 ( .A(n2969), .B(n2970), .Y(n1387) );
NAND2X2TS U2014 ( .A(n7624), .B(n7623), .Y(n7675) );
CLKINVX6TS U2015 ( .A(n1230), .Y(n5137) );
CLKINVX2TS U2016 ( .A(n1256), .Y(n1219) );
INVX4TS U2017 ( .A(n925), .Y(n926) );
BUFX8TS U2018 ( .A(n925), .Y(n5561) );
XNOR2X2TS U2019 ( .A(n1807), .B(n1253), .Y(n6098) );
CLKINVX6TS U2020 ( .A(n864), .Y(n1860) );
OR2X6TS U2021 ( .A(n2063), .B(n4127), .Y(n909) );
XNOR2X2TS U2022 ( .A(n1805), .B(n1931), .Y(n6100) );
CLKINVX6TS U2023 ( .A(n6832), .Y(n1954) );
OAI22X2TS U2024 ( .A0(n1516), .A1(n4977), .B0(n1901), .B1(n4976), .Y(n5030)
);
NOR2X4TS U2025 ( .A(n11616), .B(n11617), .Y(n7837) );
INVX2TS U2026 ( .A(n6148), .Y(n2082) );
XOR2X2TS U2027 ( .A(n2930), .B(n2094), .Y(n3184) );
BUFX16TS U2028 ( .A(n3524), .Y(n1815) );
INVX1TS U2029 ( .A(n6737), .Y(n6796) );
XNOR2X2TS U2030 ( .A(n6529), .B(n2041), .Y(n6785) );
XNOR2X2TS U2031 ( .A(n2341), .B(n1808), .Y(n6015) );
BUFX16TS U2032 ( .A(n3524), .Y(n5950) );
BUFX12TS U2033 ( .A(n1242), .Y(n2074) );
NAND2X2TS U2034 ( .A(DP_OP_168J26_122_4811_n8520), .B(n1716), .Y(n2816) );
OAI22X2TS U2035 ( .A0(n2088), .A1(n4043), .B0(n1924), .B1(n3851), .Y(n4049)
);
BUFX8TS U2036 ( .A(n1694), .Y(n2669) );
XOR2X2TS U2037 ( .A(Op_MY[25]), .B(n1518), .Y(n7260) );
NOR2X6TS U2038 ( .A(n8616), .B(n3282), .Y(n6751) );
NAND2X6TS U2039 ( .A(n3058), .B(n3056), .Y(n6827) );
INVX4TS U2040 ( .A(n2450), .Y(n6068) );
BUFX12TS U2041 ( .A(n3417), .Y(n782) );
OAI22X2TS U2042 ( .A0(n4240), .A1(n5343), .B0(n2095), .B1(n5344), .Y(n5382)
);
BUFX4TS U2043 ( .A(n2780), .Y(n768) );
BUFX12TS U2044 ( .A(n5938), .Y(n8552) );
NAND2X2TS U2045 ( .A(n11630), .B(n11631), .Y(n7661) );
NAND2X2TS U2046 ( .A(n1810), .B(DP_OP_168J26_122_4811_n8493), .Y(n1344) );
NOR2X4TS U2047 ( .A(n7768), .B(n7789), .Y(n7665) );
NAND2BX1TS U2048 ( .AN(n1859), .B(n6775), .Y(n6774) );
BUFX6TS U2049 ( .A(n925), .Y(n7439) );
NAND2X2TS U2050 ( .A(n1179), .B(n1147), .Y(n7642) );
BUFX8TS U2051 ( .A(n916), .Y(n2672) );
CLKINVX6TS U2052 ( .A(n1305), .Y(n1306) );
NAND2BX1TS U2053 ( .AN(n6633), .B(n6906), .Y(n6831) );
BUFX4TS U2054 ( .A(n4074), .Y(n2659) );
XNOR2X2TS U2055 ( .A(n1608), .B(n1717), .Y(n7992) );
NAND2X2TS U2056 ( .A(DP_OP_168J26_122_4811_n8469), .B(n820), .Y(n3563) );
OR2X4TS U2057 ( .A(n6793), .B(n6762), .Y(n11179) );
INVX12TS U2058 ( .A(n5721), .Y(n1591) );
XNOR2X2TS U2059 ( .A(n1688), .B(n1730), .Y(n7281) );
NOR2X2TS U2060 ( .A(n7752), .B(n7750), .Y(n7616) );
XNOR2X2TS U2061 ( .A(n1608), .B(n944), .Y(n7994) );
OAI22X1TS U2062 ( .A0(n5236), .A1(n2025), .B0(n1991), .B1(n5271), .Y(n5281)
);
BUFX8TS U2063 ( .A(n11676), .Y(n2592) );
INVX4TS U2064 ( .A(n5113), .Y(n3097) );
XOR2X2TS U2065 ( .A(n1704), .B(n1291), .Y(n5861) );
AND2X4TS U2066 ( .A(n3265), .B(n3263), .Y(n4998) );
NAND2X4TS U2067 ( .A(n3593), .B(n3594), .Y(n3595) );
XNOR2X2TS U2068 ( .A(n11583), .B(DP_OP_168J26_122_4811_n6172), .Y(n4540) );
OAI22X2TS U2069 ( .A0(n5302), .A1(n4979), .B0(n1924), .B1(n4978), .Y(n5029)
);
INVX6TS U2070 ( .A(n1881), .Y(n747) );
ADDFHX2TS U2071 ( .A(n3794), .B(n3796), .CI(n3795), .CO(n3827), .S(n3837) );
OAI22X2TS U2072 ( .A0(n4860), .A1(n1925), .B0(n2087), .B1(n1100), .Y(n4868)
);
XNOR2X2TS U2073 ( .A(n6714), .B(n1006), .Y(n6004) );
XOR2X2TS U2074 ( .A(n2045), .B(n1741), .Y(n1504) );
OAI22X2TS U2075 ( .A0(n2088), .A1(n4965), .B0(n1924), .B1(n4956), .Y(n5104)
);
OAI22X2TS U2076 ( .A0(n2106), .A1(n5238), .B0(n1943), .B1(n5285), .Y(n5280)
);
OAI22X2TS U2077 ( .A0(n3298), .A1(n2110), .B0(n5058), .B1(n3296), .Y(n5066)
);
OAI22X2TS U2078 ( .A0(n2066), .A1(n5158), .B0(n980), .B1(n2904), .Y(n5241)
);
OAI22X2TS U2079 ( .A0(n2107), .A1(n4830), .B0(n1864), .B1(n4857), .Y(n4871)
);
XNOR2X2TS U2080 ( .A(n866), .B(n1645), .Y(n7274) );
NOR2X2TS U2081 ( .A(n5270), .B(n840), .Y(n3258) );
CLKINVX2TS U2082 ( .A(n1704), .Y(n843) );
NOR2X4TS U2083 ( .A(n7622), .B(n1170), .Y(n7683) );
INVX12TS U2084 ( .A(n6181), .Y(n1881) );
INVX2TS U2085 ( .A(n916), .Y(n917) );
INVX4TS U2086 ( .A(n1270), .Y(n1271) );
BUFX16TS U2087 ( .A(n927), .Y(n2677) );
INVX6TS U2088 ( .A(n2521), .Y(n1805) );
INVX6TS U2089 ( .A(n6781), .Y(n6810) );
NOR2X4TS U2090 ( .A(n7624), .B(n7623), .Y(n7674) );
NAND2X1TS U2091 ( .A(n1175), .B(n11679), .Y(n7777) );
INVX6TS U2092 ( .A(n1947), .Y(n1948) );
BUFX6TS U2093 ( .A(n3667), .Y(n887) );
XNOR2X2TS U2094 ( .A(n1807), .B(n1686), .Y(n6099) );
BUFX6TS U2095 ( .A(DP_OP_168J26_122_4811_n8223), .Y(n6176) );
NAND2BX2TS U2096 ( .AN(n2178), .B(n3378), .Y(n1490) );
XNOR2X2TS U2097 ( .A(n1890), .B(n2409), .Y(n4957) );
BUFX16TS U2098 ( .A(n3390), .Y(n7490) );
BUFX16TS U2099 ( .A(n2571), .Y(n1883) );
INVX12TS U2100 ( .A(n2061), .Y(n2063) );
BUFX3TS U2101 ( .A(n3699), .Y(n942) );
BUFX16TS U2102 ( .A(n3391), .Y(n6178) );
BUFX3TS U2103 ( .A(n4224), .Y(n745) );
INVX8TS U2104 ( .A(n8643), .Y(n3055) );
NAND2X2TS U2105 ( .A(DP_OP_168J26_122_4811_n8537), .B(
DP_OP_168J26_122_4811_n8510), .Y(n3575) );
BUFX8TS U2106 ( .A(n863), .Y(n6156) );
BUFX8TS U2107 ( .A(DP_OP_168J26_122_4811_n8246), .Y(n1006) );
NAND2X6TS U2108 ( .A(n3038), .B(n3037), .Y(n5188) );
NAND2X1TS U2109 ( .A(n11746), .B(DP_OP_168J26_122_4811_n3553), .Y(n3780) );
INVX2TS U2110 ( .A(n7758), .Y(n2194) );
NAND2X6TS U2111 ( .A(n1418), .B(n2947), .Y(n3139) );
BUFX12TS U2112 ( .A(n5571), .Y(n6154) );
XNOR2X2TS U2113 ( .A(n2078), .B(n1644), .Y(n3696) );
BUFX12TS U2114 ( .A(n1256), .Y(n6160) );
NAND2X2TS U2115 ( .A(n1294), .B(n1702), .Y(n3634) );
BUFX12TS U2116 ( .A(DP_OP_168J26_122_4811_n5160), .Y(n2550) );
INVX12TS U2117 ( .A(n5567), .Y(n1305) );
XNOR2X2TS U2118 ( .A(n5251), .B(DP_OP_168J26_122_4811_n6563), .Y(n5177) );
NOR2X6TS U2119 ( .A(n8021), .B(n1936), .Y(n2946) );
XOR2X2TS U2120 ( .A(n3265), .B(n3263), .Y(n5010) );
XNOR2X2TS U2121 ( .A(n5175), .B(n2078), .Y(n3852) );
XNOR2X2TS U2122 ( .A(n6813), .B(n6812), .Y(n6842) );
NAND2X6TS U2123 ( .A(n3772), .B(DP_OP_168J26_122_4811_n3214), .Y(n3773) );
XNOR2X2TS U2124 ( .A(n2430), .B(n2079), .Y(n4943) );
XNOR2X2TS U2125 ( .A(n1645), .B(n1726), .Y(n4042) );
NOR2X4TS U2126 ( .A(n2788), .B(n981), .Y(n5018) );
OAI22X2TS U2127 ( .A0(n5307), .A1(n2027), .B0(n1988), .B1(n4231), .Y(n5393)
);
CLKBUFX2TS U2128 ( .A(n2871), .Y(n890) );
OAI22X2TS U2129 ( .A0(n5345), .A1(n5044), .B0(n5052), .B1(n793), .Y(n5069)
);
NAND2X4TS U2130 ( .A(n3566), .B(DP_OP_168J26_122_4811_n3223), .Y(n749) );
INVX2TS U2131 ( .A(n796), .Y(n799) );
INVX3TS U2132 ( .A(n1838), .Y(n965) );
INVX2TS U2133 ( .A(n5419), .Y(n921) );
OAI2BB1X2TS U2134 ( .A0N(n2401), .A1N(n3040), .B0(n3041), .Y(n3038) );
AND2X6TS U2135 ( .A(n5283), .B(n6161), .Y(n3565) );
BUFX8TS U2136 ( .A(n2070), .Y(n3432) );
NOR2X4TS U2137 ( .A(n1816), .B(DP_OP_168J26_122_4811_n8487), .Y(n3637) );
BUFX4TS U2138 ( .A(DP_OP_168J26_122_4811_n6611), .Y(n2114) );
BUFX8TS U2139 ( .A(n3651), .Y(n2411) );
INVX6TS U2140 ( .A(n5572), .Y(n2061) );
INVX8TS U2141 ( .A(n6823), .Y(n4064) );
AND2X6TS U2142 ( .A(n7197), .B(n11772), .Y(n3606) );
INVX12TS U2143 ( .A(n1031), .Y(n5567) );
NAND2X1TS U2144 ( .A(n11742), .B(DP_OP_168J26_122_4811_n3581), .Y(n3771) );
XNOR2X2TS U2145 ( .A(n5251), .B(Op_MY[26]), .Y(n3683) );
BUFX4TS U2146 ( .A(n1226), .Y(n6142) );
CLKINVX2TS U2147 ( .A(n1257), .Y(n1258) );
INVX2TS U2148 ( .A(n1608), .Y(n7139) );
NOR2X4TS U2149 ( .A(n1175), .B(n11608), .Y(n7776) );
CLKINVX6TS U2150 ( .A(n8007), .Y(n1721) );
NAND2BX2TS U2151 ( .AN(n3040), .B(n4827), .Y(n3037) );
NAND2X4TS U2152 ( .A(n3359), .B(n3309), .Y(n3772) );
BUFX4TS U2153 ( .A(DP_OP_168J26_122_4811_n6611), .Y(n2115) );
OAI22X2TS U2154 ( .A0(n1516), .A1(n5057), .B0(n1901), .B1(n5056), .Y(n5078)
);
BUFX8TS U2155 ( .A(n6528), .Y(n8614) );
BUFX6TS U2156 ( .A(n2424), .Y(n8011) );
INVX2TS U2157 ( .A(n3713), .Y(n1722) );
BUFX12TS U2158 ( .A(n3877), .Y(n2150) );
NAND2X2TS U2159 ( .A(n11611), .B(n11612), .Y(n7772) );
XNOR2X2TS U2160 ( .A(n1289), .B(n5175), .Y(n3667) );
OR2X4TS U2161 ( .A(n4857), .B(n5340), .Y(n3016) );
INVX4TS U2162 ( .A(n6529), .Y(n1871) );
OR2X4TS U2163 ( .A(n1865), .B(n5156), .Y(n1404) );
XOR2X2TS U2164 ( .A(n11582), .B(n1661), .Y(n4828) );
INVX3TS U2165 ( .A(n11185), .Y(n6834) );
NAND2BX2TS U2166 ( .AN(n6884), .B(n6529), .Y(n6791) );
CLKXOR2X4TS U2167 ( .A(n5256), .B(n3202), .Y(n8021) );
XNOR2X2TS U2168 ( .A(n2430), .B(n1289), .Y(n4856) );
OAI22X2TS U2169 ( .A0(n2111), .A1(n1726), .B0(n1899), .B1(n5046), .Y(n5059)
);
XNOR2X2TS U2170 ( .A(n1832), .B(n1884), .Y(n4975) );
XNOR2X2TS U2171 ( .A(n1890), .B(n5235), .Y(n4964) );
INVX2TS U2172 ( .A(n2647), .Y(n3057) );
CLKXOR2X2TS U2173 ( .A(n1279), .B(n2265), .Y(n6807) );
XNOR2X2TS U2174 ( .A(n2406), .B(n2591), .Y(n4981) );
XNOR2X2TS U2175 ( .A(n4003), .B(n6906), .Y(n6824) );
CLKXOR2X2TS U2176 ( .A(n944), .B(n869), .Y(n3679) );
ADDFHX2TS U2177 ( .A(n4894), .B(n4892), .CI(n4893), .CO(n4903), .S(n4929) );
CLKXOR2X2TS U2178 ( .A(n3786), .B(DP_OP_168J26_122_4811_n3224), .Y(n3787) );
OR2X6TS U2179 ( .A(n3133), .B(n2087), .Y(n1308) );
NAND2BX2TS U2180 ( .AN(n2591), .B(n2483), .Y(n5046) );
NAND2BX2TS U2181 ( .AN(n4982), .B(n2328), .Y(n4877) );
INVX2TS U2182 ( .A(n1810), .Y(n7197) );
INVX6TS U2183 ( .A(n6141), .Y(n1811) );
BUFX8TS U2184 ( .A(n1837), .Y(n2094) );
INVX8TS U2185 ( .A(n750), .Y(n3129) );
BUFX3TS U2186 ( .A(n3351), .Y(n2605) );
BUFX4TS U2187 ( .A(n1713), .Y(n2568) );
OR2X2TS U2188 ( .A(n2087), .B(n5283), .Y(n893) );
BUFX8TS U2189 ( .A(n3647), .Y(n5302) );
BUFX6TS U2190 ( .A(n1270), .Y(n2070) );
INVX12TS U2191 ( .A(n7036), .Y(n1816) );
INVX8TS U2192 ( .A(n1320), .Y(n6181) );
BUFX6TS U2193 ( .A(n3648), .Y(n2107) );
INVX8TS U2194 ( .A(n2047), .Y(n1900) );
INVX4TS U2195 ( .A(n3844), .Y(n778) );
CLKINVX6TS U2196 ( .A(n3770), .Y(n1909) );
INVX4TS U2197 ( .A(n1705), .Y(n1706) );
XNOR2X1TS U2198 ( .A(n2069), .B(n2591), .Y(n5007) );
INVX6TS U2199 ( .A(n6055), .Y(n6161) );
CLKINVX2TS U2200 ( .A(n1859), .Y(n1279) );
INVX2TS U2201 ( .A(n8024), .Y(n2254) );
BUFX12TS U2202 ( .A(DP_OP_168J26_122_4811_n6616), .Y(n1991) );
BUFX16TS U2203 ( .A(n8007), .Y(n2066) );
BUFX16TS U2204 ( .A(n6069), .Y(n2018) );
OAI22X2TS U2205 ( .A0(n2221), .A1(n3818), .B0(n5320), .B1(n3817), .Y(n3845)
);
INVX8TS U2206 ( .A(n1820), .Y(n2948) );
NAND2X2TS U2207 ( .A(n2788), .B(n2079), .Y(n3264) );
NAND2BX2TS U2208 ( .AN(n4023), .B(n1879), .Y(n2789) );
INVX2TS U2209 ( .A(n6762), .Y(n6812) );
BUFX4TS U2210 ( .A(n6633), .Y(n6884) );
BUFX8TS U2211 ( .A(n3653), .Y(n2110) );
OR2X4TS U2212 ( .A(n12112), .B(n11771), .Y(n3584) );
INVX4TS U2213 ( .A(n3379), .Y(n3589) );
BUFX12TS U2214 ( .A(n3645), .Y(n1981) );
NAND2X2TS U2215 ( .A(n5350), .B(n5351), .Y(n3027) );
NOR2X6TS U2216 ( .A(n2503), .B(n1343), .Y(n3580) );
CLKINVX2TS U2217 ( .A(n4844), .Y(n758) );
INVX4TS U2218 ( .A(n2382), .Y(n980) );
INVX6TS U2219 ( .A(n1879), .Y(n1880) );
OAI22X2TS U2220 ( .A0(n5345), .A1(n4911), .B0(n4887), .B1(n5343), .Y(n4934)
);
XNOR2X2TS U2221 ( .A(n1890), .B(n882), .Y(n5044) );
XNOR2X2TS U2222 ( .A(n5254), .B(DP_OP_168J26_122_4811_n8484), .Y(n3694) );
XNOR2X2TS U2223 ( .A(n2483), .B(n4982), .Y(n5045) );
OR2X4TS U2224 ( .A(n5148), .B(n5304), .Y(n3018) );
XOR2X2TS U2225 ( .A(n1979), .B(n883), .Y(n4974) );
OAI22X2TS U2226 ( .A0(n5338), .A1(n1865), .B0(n2106), .B1(n5339), .Y(n5415)
);
XNOR2X2TS U2227 ( .A(n5273), .B(n2591), .Y(n4825) );
CLKINVX1TS U2228 ( .A(n1717), .Y(n803) );
INVX3TS U2229 ( .A(n878), .Y(n879) );
NAND2X2TS U2230 ( .A(n2418), .B(n1421), .Y(n1540) );
BUFX6TS U2231 ( .A(DP_OP_168J26_122_4811_n6610), .Y(n5320) );
INVX6TS U2232 ( .A(n1863), .Y(n1865) );
INVX6TS U2233 ( .A(n1949), .Y(n1951) );
AND2X6TS U2234 ( .A(n3776), .B(n841), .Y(n3203) );
INVX6TS U2235 ( .A(n2521), .Y(n1804) );
BUFX8TS U2236 ( .A(n1267), .Y(n6145) );
NOR2BX2TS U2237 ( .AN(n6714), .B(n6086), .Y(n6761) );
BUFX8TS U2238 ( .A(n3648), .Y(n5340) );
INVX8TS U2239 ( .A(n1406), .Y(n1925) );
BUFX16TS U2240 ( .A(n2222), .Y(n2221) );
BUFX6TS U2241 ( .A(n1226), .Y(n1227) );
BUFX3TS U2242 ( .A(n1713), .Y(n2157) );
NAND2X4TS U2243 ( .A(n3788), .B(DP_OP_168J26_122_4811_n3224), .Y(n3386) );
INVX4TS U2244 ( .A(n8534), .Y(n3770) );
CLKINVX6TS U2245 ( .A(DP_OP_168J26_122_4811_n8506), .Y(n3564) );
BUFX16TS U2246 ( .A(n2931), .Y(n1606) );
BUFX6TS U2247 ( .A(DP_OP_168J26_122_4811_n6616), .Y(n5325) );
BUFX16TS U2248 ( .A(n7275), .Y(n1608) );
BUFX12TS U2249 ( .A(n1270), .Y(n6055) );
BUFX6TS U2250 ( .A(n865), .Y(n5273) );
XNOR2X2TS U2251 ( .A(n2079), .B(n2625), .Y(n4912) );
BUFX16TS U2252 ( .A(n4022), .Y(n975) );
INVX6TS U2253 ( .A(n1949), .Y(n1950) );
BUFX12TS U2254 ( .A(n3653), .Y(n5331) );
XNOR2X2TS U2255 ( .A(n6093), .B(n1312), .Y(n6075) );
BUFX6TS U2256 ( .A(DP_OP_168J26_122_4811_n6619), .Y(n5058) );
INVX6TS U2257 ( .A(n1942), .Y(n1943) );
INVX4TS U2258 ( .A(n1346), .Y(n1959) );
BUFX12TS U2259 ( .A(n2142), .Y(n2096) );
NAND2X1TS U2260 ( .A(n1405), .B(n1869), .Y(n6085) );
INVX12TS U2261 ( .A(n2026), .Y(n1936) );
XOR2X2TS U2262 ( .A(n1979), .B(n1221), .Y(n4918) );
INVX8TS U2263 ( .A(n1406), .Y(n1924) );
INVX2TS U2264 ( .A(n4021), .Y(n2418) );
BUFX12TS U2265 ( .A(n1686), .Y(n1813) );
BUFX8TS U2266 ( .A(n3651), .Y(n1822) );
INVX4TS U2267 ( .A(n1688), .Y(n1518) );
BUFX4TS U2268 ( .A(n11740), .Y(n8005) );
NAND2X2TS U2269 ( .A(DP_OP_168J26_122_4811_n8504), .B(n1262), .Y(n2977) );
NAND2X2TS U2270 ( .A(DP_OP_168J26_122_4811_n8465), .B(
DP_OP_168J26_122_4811_n8490), .Y(n3573) );
NAND2X6TS U2271 ( .A(n3352), .B(DP_OP_168J26_122_4811_n3536), .Y(n1549) );
BUFX12TS U2272 ( .A(n5174), .Y(n2406) );
BUFX12TS U2273 ( .A(n3647), .Y(n2087) );
BUFX8TS U2274 ( .A(n3677), .Y(n8025) );
INVX2TS U2275 ( .A(n897), .Y(n850) );
INVX8TS U2276 ( .A(n2757), .Y(n2089) );
INVX8TS U2277 ( .A(n3937), .Y(n3229) );
AND2X4TS U2278 ( .A(n2245), .B(DP_OP_168J26_122_4811_n3578), .Y(n1422) );
XNOR2X2TS U2279 ( .A(n5276), .B(n1711), .Y(n4911) );
XNOR2X2TS U2280 ( .A(n1832), .B(n7279), .Y(n4833) );
XOR2X2TS U2281 ( .A(n11581), .B(n790), .Y(n5284) );
XNOR2X2TS U2282 ( .A(n1303), .B(n1807), .Y(n6076) );
XNOR2X2TS U2283 ( .A(n7353), .B(n4982), .Y(n4024) );
XNOR2X2TS U2284 ( .A(n1832), .B(n2409), .Y(n4907) );
OR2X4TS U2285 ( .A(n2095), .B(n5052), .Y(n1630) );
INVX6TS U2286 ( .A(n2653), .Y(n851) );
XNOR2X2TS U2287 ( .A(n2015), .B(n1729), .Y(n5040) );
XNOR2X2TS U2288 ( .A(DP_OP_168J26_122_4811_n8504), .B(
DP_OP_168J26_122_4811_n8503), .Y(n2683) );
XOR2X2TS U2289 ( .A(n4069), .B(n4066), .Y(n4068) );
INVX1TS U2290 ( .A(n11750), .Y(n756) );
INVX6TS U2291 ( .A(n1837), .Y(n1838) );
INVX12TS U2292 ( .A(n5253), .Y(n1885) );
NAND2BX2TS U2293 ( .AN(n4982), .B(n7270), .Y(n5287) );
BUFX12TS U2294 ( .A(n1240), .Y(n1832) );
BUFX8TS U2295 ( .A(n2091), .Y(n754) );
BUFX16TS U2296 ( .A(n2424), .Y(n2222) );
OR2X6TS U2297 ( .A(n2871), .B(n7993), .Y(n1666) );
BUFX12TS U2298 ( .A(n3648), .Y(n2106) );
BUFX6TS U2299 ( .A(DP_OP_168J26_122_4811_n6620), .Y(n1901) );
BUFX8TS U2300 ( .A(n5254), .Y(n2147) );
BUFX12TS U2301 ( .A(n955), .Y(n5235) );
BUFX12TS U2302 ( .A(n931), .Y(n5174) );
INVX8TS U2303 ( .A(n2023), .Y(n2024) );
INVX12TS U2304 ( .A(n1267), .Y(n2521) );
INVX4TS U2305 ( .A(n869), .Y(n2014) );
INVX4TS U2306 ( .A(n865), .Y(n866) );
BUFX8TS U2307 ( .A(DP_OP_168J26_122_4811_n6610), .Y(n2046) );
BUFX6TS U2308 ( .A(n1226), .Y(n2261) );
BUFX12TS U2309 ( .A(n6848), .Y(n793) );
BUFX8TS U2310 ( .A(n2142), .Y(n5345) );
NOR2X2TS U2311 ( .A(n1979), .B(DP_OP_168J26_122_4811_n8503), .Y(n3383) );
INVX2TS U2312 ( .A(n1409), .Y(n841) );
BUFX8TS U2313 ( .A(n931), .Y(n5270) );
INVX6TS U2314 ( .A(n2382), .Y(n981) );
INVX6TS U2315 ( .A(n857), .Y(n7036) );
BUFX8TS U2316 ( .A(n1837), .Y(n2093) );
OR2X6TS U2317 ( .A(n1806), .B(n5321), .Y(n1419) );
INVX8TS U2318 ( .A(n1324), .Y(n2015) );
INVX6TS U2319 ( .A(n1389), .Y(n1898) );
BUFX16TS U2320 ( .A(DP_OP_168J26_122_4811_n6643), .Y(n2079) );
INVX12TS U2321 ( .A(n1644), .Y(n1645) );
BUFX6TS U2322 ( .A(DP_OP_168J26_122_4811_n6614), .Y(n1989) );
INVX12TS U2323 ( .A(n1261), .Y(n2045) );
BUFX12TS U2324 ( .A(n3677), .Y(n5306) );
INVX8TS U2325 ( .A(n2788), .Y(n1902) );
INVX6TS U2326 ( .A(n944), .Y(n945) );
BUFX8TS U2327 ( .A(DP_OP_168J26_122_4811_n6610), .Y(n8009) );
BUFX6TS U2328 ( .A(n1711), .Y(n5237) );
BUFX12TS U2329 ( .A(n4022), .Y(n5318) );
BUFX12TS U2330 ( .A(n1705), .Y(n5256) );
BUFX12TS U2331 ( .A(n3645), .Y(n1980) );
BUFX12TS U2332 ( .A(n3645), .Y(n8015) );
INVX4TS U2333 ( .A(n931), .Y(n932) );
INVX6TS U2334 ( .A(n1346), .Y(n1958) );
INVX4TS U2335 ( .A(DP_OP_168J26_122_4811_n3508), .Y(n3231) );
BUFX12TS U2336 ( .A(n3653), .Y(n2111) );
BUFX8TS U2337 ( .A(n2142), .Y(n2095) );
XNOR2X2TS U2338 ( .A(n7273), .B(n882), .Y(n5274) );
BUFX12TS U2339 ( .A(DP_OP_168J26_122_4811_n6611), .Y(n7993) );
BUFX3TS U2340 ( .A(n3995), .Y(n825) );
BUFX12TS U2341 ( .A(n4022), .Y(n8007) );
BUFX8TS U2342 ( .A(n1240), .Y(n5278) );
INVX12TS U2343 ( .A(n882), .Y(n883) );
BUFX16TS U2344 ( .A(n5254), .Y(n2455) );
BUFX16TS U2345 ( .A(n2424), .Y(n1806) );
INVX4TS U2346 ( .A(n1260), .Y(n1261) );
BUFX8TS U2347 ( .A(n865), .Y(n1861) );
INVX4TS U2348 ( .A(n955), .Y(n956) );
BUFX12TS U2349 ( .A(n1725), .Y(n1979) );
BUFX6TS U2350 ( .A(n1725), .Y(n5251) );
INVX6TS U2351 ( .A(n5343), .Y(n1888) );
BUFX8TS U2352 ( .A(n868), .Y(n1289) );
NAND2X2TS U2353 ( .A(DP_OP_168J26_122_4811_n8500), .B(
DP_OP_168J26_122_4811_n8527), .Y(n3782) );
BUFX8TS U2354 ( .A(n878), .Y(n2430) );
INVX2TS U2355 ( .A(n1420), .Y(n962) );
BUFX8TS U2356 ( .A(n1837), .Y(n7270) );
BUFX12TS U2357 ( .A(DP_OP_168J26_122_4811_n8472), .Y(n1008) );
BUFX12TS U2358 ( .A(n6848), .Y(n5343) );
BUFX12TS U2359 ( .A(n1286), .Y(n5276) );
BUFX12TS U2360 ( .A(n1713), .Y(n8013) );
INVX4TS U2361 ( .A(DP_OP_168J26_122_4811_n3595), .Y(n1561) );
INVX12TS U2362 ( .A(DP_OP_168J26_122_4811_n8525), .Y(n6848) );
INVX2TS U2363 ( .A(n1260), .Y(n915) );
INVX6TS U2364 ( .A(Sgf_operation_ODD1_Q_left[35]), .Y(add_x_19_n263) );
INVX6TS U2365 ( .A(Sgf_operation_ODD1_Q_left[33]), .Y(add_x_19_n289) );
INVX6TS U2366 ( .A(Sgf_operation_ODD1_Q_left[39]), .Y(add_x_19_n213) );
NAND2X8TS U2367 ( .A(n5874), .B(n1316), .Y(n2428) );
NAND2X6TS U2368 ( .A(n1652), .B(n740), .Y(n10144) );
INVX12TS U2369 ( .A(n9859), .Y(n9837) );
OAI21X4TS U2370 ( .A0(n1825), .A1(n9510), .B0(n9509), .Y(n9514) );
NOR2X4TS U2371 ( .A(add_x_19_n121), .B(add_x_19_n130), .Y(add_x_19_n120) );
XOR2X4TS U2372 ( .A(n9844), .B(n9845), .Y(n2498) );
NAND2X4TS U2373 ( .A(n11759), .B(n8716), .Y(DP_OP_168J26_122_4811_n127) );
AOI2BB2X2TS U2374 ( .B0(n10674), .B1(n477), .A0N(n10682), .A1N(n11884), .Y(
n10700) );
MX2X6TS U2375 ( .A(n10698), .B(n12160), .S0(n1206), .Y(n477) );
XOR2X4TS U2376 ( .A(n8858), .B(n8857), .Y(n8859) );
AOI21X2TS U2377 ( .A0(n10693), .A1(n8853), .B0(n8852), .Y(n8858) );
XOR2X4TS U2378 ( .A(n10170), .B(n10169), .Y(Sgf_operation_ODD1_Q_left[22])
);
NAND3X4TS U2379 ( .A(n10784), .B(n10783), .C(n10782), .Y(n367) );
AOI2BB2X4TS U2380 ( .B0(n10803), .B1(n488), .A0N(n10870), .A1N(n11874), .Y(
n10783) );
NAND2X4TS U2381 ( .A(n10739), .B(n10737), .Y(n9260) );
NAND2X8TS U2382 ( .A(n2319), .B(n2318), .Y(n10739) );
NAND3X4TS U2383 ( .A(n10787), .B(n10786), .C(n10785), .Y(n369) );
AOI2BB2X4TS U2384 ( .B0(n10803), .B1(n490), .A0N(n10760), .A1N(n11872), .Y(
n10786) );
BUFX12TS U2385 ( .A(n9515), .Y(n2377) );
XNOR2X4TS U2386 ( .A(n8736), .B(n8735), .Y(n8737) );
OAI21X4TS U2387 ( .A0(n8731), .A1(n8730), .B0(n8729), .Y(n8736) );
OAI21X4TS U2388 ( .A0(n10748), .A1(n7981), .B0(n7980), .Y(n7984) );
OAI21X4TS U2389 ( .A0(n10748), .A1(n10747), .B0(n10746), .Y(n10753) );
OAI21X4TS U2390 ( .A0(n10748), .A1(n9538), .B0(n9537), .Y(n9543) );
INVX6TS U2391 ( .A(n11111), .Y(n10623) );
NAND2X6TS U2392 ( .A(n7423), .B(n7422), .Y(n7424) );
NAND2X8TS U2393 ( .A(n11442), .B(n11443), .Y(n9165) );
NAND2X4TS U2394 ( .A(n6793), .B(n6762), .Y(n11178) );
NOR2X2TS U2395 ( .A(n10567), .B(n10549), .Y(n10551) );
OAI21X4TS U2396 ( .A0(n1609), .A1(n9410), .B0(n9409), .Y(n9413) );
AOI21X2TS U2397 ( .A0(n9436), .A1(n9416), .B0(n9418), .Y(n9409) );
INVX4TS U2398 ( .A(n9165), .Y(n7711) );
NAND2X4TS U2399 ( .A(n10101), .B(n10100), .Y(DP_OP_168J26_122_4811_n98) );
NAND2BX2TS U2400 ( .AN(n3290), .B(n10948), .Y(n12317) );
INVX16TS U2401 ( .A(n7885), .Y(n9400) );
INVX16TS U2402 ( .A(n2616), .Y(n10748) );
BUFX12TS U2403 ( .A(n7979), .Y(n2616) );
XOR2X4TS U2404 ( .A(n9221), .B(n9220), .Y(n9222) );
XNOR2X4TS U2405 ( .A(n10693), .B(n10679), .Y(n10680) );
XNOR2X4TS U2406 ( .A(n8812), .B(n8811), .Y(n8814) );
INVX16TS U2407 ( .A(n9400), .Y(n2064) );
XNOR2X4TS U2408 ( .A(n8832), .B(n8831), .Y(n8834) );
OAI21X4TS U2409 ( .A0(n2016), .A1(n8828), .B0(n8827), .Y(n8832) );
XNOR2X4TS U2410 ( .A(n8837), .B(n8836), .Y(n8839) );
XNOR2X4TS U2411 ( .A(n8822), .B(n8821), .Y(n8824) );
OAI21X4TS U2412 ( .A0(n2016), .A1(n8818), .B0(n8817), .Y(n8822) );
OAI21X4TS U2413 ( .A0(n1609), .A1(n9438), .B0(n9437), .Y(n9443) );
AOI21X2TS U2414 ( .A0(n9436), .A1(n9435), .B0(n9434), .Y(n9437) );
NAND2X2TS U2415 ( .A(n10810), .B(n1834), .Y(n12253) );
XNOR2X4TS U2416 ( .A(n10642), .B(n10641), .Y(n10643) );
XNOR2X4TS U2417 ( .A(n10634), .B(n10633), .Y(n10635) );
AOI21X4TS U2418 ( .A0(n10693), .A1(n8863), .B0(n8862), .Y(n8867) );
XOR2X4TS U2419 ( .A(n10530), .B(n10515), .Y(n10519) );
XOR2X4TS U2420 ( .A(n10530), .B(n10517), .Y(n10522) );
XOR2X4TS U2421 ( .A(n10530), .B(n10504), .Y(n10512) );
XOR2X4TS U2422 ( .A(n10530), .B(n10516), .Y(n10520) );
AOI2BB2X2TS U2423 ( .B0(n10947), .B1(n10975), .A0N(n10760), .A1N(n11856),
.Y(n12315) );
NAND2X8TS U2424 ( .A(n1106), .B(n12192), .Y(n10810) );
NAND2X6TS U2425 ( .A(n1107), .B(n1131), .Y(n1106) );
BUFX12TS U2426 ( .A(n7956), .Y(n2538) );
AOI21X2TS U2427 ( .A0(n10693), .A1(n8870), .B0(n8869), .Y(n8874) );
AOI21X4TS U2428 ( .A0(n1196), .A1(n11602), .B0(n11603), .Y(n7727) );
INVX8TS U2429 ( .A(n2751), .Y(n736) );
OAI21X4TS U2430 ( .A0(n2016), .A1(n10837), .B0(n10836), .Y(n10838) );
AOI21X4TS U2431 ( .A0(n2065), .A1(n10835), .B0(n10834), .Y(n10836) );
NOR2X4TS U2432 ( .A(n10617), .B(n10616), .Y(n10618) );
AOI2BB2X1TS U2433 ( .B0(n10871), .B1(n10885), .A0N(n10760), .A1N(n11860),
.Y(n12331) );
XOR2X4TS U2434 ( .A(n10735), .B(n10734), .Y(n10736) );
AOI2BB2X2TS U2435 ( .B0(n10861), .B1(n10877), .A0N(n10860), .A1N(n11843),
.Y(n12262) );
INVX8TS U2436 ( .A(n8840), .Y(n10693) );
NAND2X4TS U2437 ( .A(n10041), .B(n10040), .Y(DP_OP_168J26_122_4811_n136) );
BUFX20TS U2438 ( .A(n7918), .Y(n10954) );
OAI21X2TS U2439 ( .A0(n7612), .A1(n7698), .B0(n7611), .Y(n7613) );
NAND3X4TS U2440 ( .A(n1502), .B(n3753), .C(n809), .Y(n1501) );
NAND2X8TS U2441 ( .A(n8787), .B(n11820), .Y(n11175) );
OAI21X4TS U2442 ( .A0(n2202), .A1(n9365), .B0(n9364), .Y(n9366) );
OAI21X2TS U2443 ( .A0(n2202), .A1(n10847), .B0(n10846), .Y(n10848) );
OAI21X4TS U2444 ( .A0(n2202), .A1(n9312), .B0(n9311), .Y(n9317) );
OAI21X4TS U2445 ( .A0(n2202), .A1(n9608), .B0(n9607), .Y(n9613) );
NAND2X2TS U2446 ( .A(n2064), .B(n8804), .Y(n8806) );
XOR2X4TS U2447 ( .A(n11107), .B(n3336), .Y(n10505) );
BUFX20TS U2448 ( .A(n10530), .Y(n11107) );
INVX16TS U2449 ( .A(n9400), .Y(n9071) );
NAND2X2TS U2450 ( .A(n10878), .B(n1011), .Y(n12260) );
INVX4TS U2451 ( .A(n8941), .Y(n9006) );
BUFX20TS U2452 ( .A(n2200), .Y(n2016) );
XNOR2X4TS U2453 ( .A(n8785), .B(n8784), .Y(n8786) );
OAI21X4TS U2454 ( .A0(n10748), .A1(n8780), .B0(n8779), .Y(n8785) );
NAND2X4TS U2455 ( .A(n2085), .B(n10904), .Y(n10906) );
OAI21X4TS U2456 ( .A0(n1609), .A1(n7953), .B0(n7952), .Y(n7954) );
OAI21X4TS U2457 ( .A0(n1609), .A1(n9064), .B0(n9063), .Y(n9069) );
XNOR2X4TS U2458 ( .A(n9352), .B(n1124), .Y(n9353) );
XOR2X4TS U2459 ( .A(n10530), .B(n10503), .Y(n10510) );
INVX16TS U2460 ( .A(n11175), .Y(n10530) );
BUFX20TS U2461 ( .A(n9479), .Y(n2570) );
OAI21X4TS U2462 ( .A0(n1609), .A1(n9620), .B0(n9619), .Y(n9621) );
AOI21X4TS U2463 ( .A0(n2065), .A1(n9618), .B0(n9617), .Y(n9619) );
XOR2X4TS U2464 ( .A(n10778), .B(n10741), .Y(n10742) );
INVX8TS U2465 ( .A(n10740), .Y(n10778) );
XOR2X4TS U2466 ( .A(n10046), .B(n2369), .Y(n10051) );
OAI21X4TS U2467 ( .A0(n2201), .A1(n8806), .B0(n8805), .Y(n8807) );
OAI21X4TS U2468 ( .A0(n10165), .A1(n10117), .B0(n10116), .Y(n10121) );
INVX16TS U2469 ( .A(n2202), .Y(n2617) );
INVX8TS U2470 ( .A(n7957), .Y(n10124) );
AOI21X4TS U2471 ( .A0(n9536), .A1(n9527), .B0(n9530), .Y(n7980) );
INVX4TS U2472 ( .A(n9530), .Y(n9533) );
AOI21X4TS U2473 ( .A0(n9530), .A1(n7824), .B0(n7823), .Y(n7825) );
OR2X8TS U2474 ( .A(n7816), .B(n11457), .Y(n9553) );
AOI21X2TS U2475 ( .A0(n7913), .A1(n1200), .B0(n1156), .Y(n7882) );
NOR4X2TS U2476 ( .A(n463), .B(n464), .C(n462), .D(n461), .Y(n9241) );
ADDFHX4TS U2477 ( .A(n952), .B(n1625), .CI(n7365), .CO(n9658), .S(n7605) );
NAND2X4TS U2478 ( .A(n9527), .B(n7824), .Y(n7826) );
OAI21X4TS U2479 ( .A0(n7973), .A1(n10165), .B0(n7972), .Y(n7978) );
XNOR2X4TS U2480 ( .A(n10769), .B(n10768), .Y(n10770) );
OAI21X4TS U2481 ( .A0(n10778), .A1(n10766), .B0(n10765), .Y(n10769) );
AOI2BB2X2TS U2482 ( .B0(n10947), .B1(n10948), .A0N(n10760), .A1N(n11858),
.Y(n12323) );
NOR2X4TS U2483 ( .A(n7938), .B(n1168), .Y(n9061) );
AOI21X4TS U2484 ( .A0(n10945), .A1(n10892), .B0(n10891), .Y(n10893) );
XNOR2X4TS U2485 ( .A(n7984), .B(n7983), .Y(n7985) );
INVX4TS U2486 ( .A(n7582), .Y(n7296) );
AOI21X2TS U2487 ( .A0(n2065), .A1(n10908), .B0(n10907), .Y(n10909) );
MX2X4TS U2488 ( .A(n10727), .B(P_Sgf[15]), .S0(n1978), .Y(n436) );
XOR2X4TS U2489 ( .A(n10726), .B(n10725), .Y(n10727) );
INVX16TS U2490 ( .A(n2538), .Y(n10165) );
AOI21X4TS U2491 ( .A0(n9536), .A1(n9535), .B0(n9534), .Y(n9537) );
AOI21X2TS U2492 ( .A0(n10945), .A1(n10799), .B0(n10798), .Y(n10800) );
NAND2X8TS U2493 ( .A(n2500), .B(n2371), .Y(n2370) );
AOI21X4TS U2494 ( .A0(n10945), .A1(n9402), .B0(n9062), .Y(n9063) );
OAI21X2TS U2495 ( .A0(n2084), .A1(n10843), .B0(n10842), .Y(n10844) );
BUFX20TS U2496 ( .A(n10960), .Y(n2084) );
OAI21X4TS U2497 ( .A0(n2201), .A1(n9424), .B0(n9423), .Y(n9429) );
BUFX20TS U2498 ( .A(n2202), .Y(n2201) );
AOI21X4TS U2499 ( .A0(n10945), .A1(n9384), .B0(n9383), .Y(n9385) );
AOI2BB2X2TS U2500 ( .B0(n10861), .B1(n10809), .A0N(n10870), .A1N(n11841),
.Y(n12254) );
NAND2X8TS U2501 ( .A(n2148), .B(n12198), .Y(n10809) );
BUFX20TS U2502 ( .A(n2380), .Y(n731) );
XNOR2X4TS U2503 ( .A(n10858), .B(n11345), .Y(n10859) );
OAI21X4TS U2504 ( .A0(n2201), .A1(n10857), .B0(n10856), .Y(n10858) );
NAND2X4TS U2505 ( .A(n10030), .B(n938), .Y(DP_OP_168J26_122_4811_n101) );
NAND2X4TS U2506 ( .A(n10956), .B(n9384), .Y(n9386) );
INVX16TS U2507 ( .A(n9400), .Y(n10956) );
AOI21X4TS U2508 ( .A0(n10065), .A1(n8382), .B0(n8381), .Y(n8383) );
AOI21X4TS U2509 ( .A0(n9536), .A1(n9518), .B0(n8778), .Y(n8779) );
INVX16TS U2510 ( .A(n9379), .Y(n10863) );
NAND2X8TS U2511 ( .A(n9599), .B(n7943), .Y(n9379) );
NAND2X6TS U2512 ( .A(n9131), .B(n9132), .Y(n10033) );
OAI21X2TS U2513 ( .A0(n2083), .A1(n10833), .B0(n10832), .Y(n10834) );
NAND2X2TS U2514 ( .A(n10855), .B(n9071), .Y(n10857) );
XNOR2X4TS U2515 ( .A(n1689), .B(n1839), .Y(n4593) );
AOI21X4TS U2516 ( .A0(n2065), .A1(n9599), .B0(n9601), .Y(n9072) );
NAND2X2TS U2517 ( .A(Sgf_operation_ODD1_Q_right[36]), .B(
Sgf_operation_ODD1_S_B[9]), .Y(add_x_19_n725) );
NAND2X6TS U2518 ( .A(n9995), .B(n9994), .Y(n9998) );
NOR2X6TS U2519 ( .A(n7717), .B(n11392), .Y(n9143) );
BUFX8TS U2520 ( .A(n10033), .Y(n3209) );
AOI21X4TS U2521 ( .A0(n2065), .A1(n9310), .B0(n9309), .Y(n9311) );
OAI21X2TS U2522 ( .A0(n2083), .A1(n9593), .B0(n9594), .Y(n9309) );
NAND2X2TS U2523 ( .A(n10956), .B(n10817), .Y(n10819) );
NAND2X4TS U2524 ( .A(n9628), .B(n9292), .Y(add_x_19_n69) );
OR2X8TS U2525 ( .A(n8374), .B(n1363), .Y(n9628) );
INVX8TS U2526 ( .A(n7959), .Y(n10125) );
ADDFHX4TS U2527 ( .A(n8092), .B(n8091), .CI(n8090), .CO(n8161), .S(n8157) );
NAND2X2TS U2528 ( .A(n11776), .B(n10003), .Y(DP_OP_168J26_122_4811_n104) );
AOI21X4TS U2529 ( .A0(n10945), .A1(n10926), .B0(n10925), .Y(n10927) );
OAI21X2TS U2530 ( .A0(n2083), .A1(n10924), .B0(n10923), .Y(n10925) );
INVX6TS U2531 ( .A(n2534), .Y(n9812) );
AOI21X2TS U2532 ( .A0(n10945), .A1(n10865), .B0(n10864), .Y(n10866) );
INVX16TS U2533 ( .A(n9399), .Y(n10945) );
NAND2X4TS U2534 ( .A(n2794), .B(n2466), .Y(n2407) );
INVX6TS U2535 ( .A(n2536), .Y(DP_OP_168J26_122_4811_n265) );
NAND2X4TS U2536 ( .A(DP_OP_168J26_122_4811_n745), .B(n2536), .Y(
DP_OP_168J26_122_4811_n102) );
OAI21X4TS U2537 ( .A0(n2615), .A1(n2536), .B0(n938), .Y(
DP_OP_168J26_122_4811_n254) );
NAND3X6TS U2538 ( .A(n9587), .B(n3178), .C(n10101), .Y(n10009) );
NAND2X2TS U2539 ( .A(DP_OP_168J26_122_4811_n1456), .B(
DP_OP_168J26_122_4811_n1487), .Y(DP_OP_168J26_122_4811_n534) );
OAI22X2TS U2540 ( .A0(n7445), .A1(n7444), .B0(n1919), .B1(n6182), .Y(n6183)
);
OAI22X2TS U2541 ( .A0(n2104), .A1(n5681), .B0(n5680), .B1(n1919), .Y(n5867)
);
OAI22X2TS U2542 ( .A0(n8066), .A1(n1987), .B0(n2356), .B1(n1903), .Y(n8092)
);
XNOR2X4TS U2543 ( .A(n1059), .B(n2251), .Y(n8088) );
NAND2X2TS U2544 ( .A(Sgf_operation_ODD1_Q_right[33]), .B(
Sgf_operation_ODD1_S_B[6]), .Y(add_x_19_n745) );
ADDFHX2TS U2545 ( .A(n7269), .B(n7268), .CI(n7267), .CO(n7265), .S(n8031) );
AOI21X4TS U2546 ( .A0(n10935), .A1(n10916), .B0(n10915), .Y(n10917) );
AOI21X2TS U2547 ( .A0(n10935), .A1(n10827), .B0(n10826), .Y(n10828) );
AOI21X2TS U2548 ( .A0(n10935), .A1(n7951), .B0(n7950), .Y(n7952) );
AOI21X2TS U2549 ( .A0(n10935), .A1(n10934), .B0(n10933), .Y(n10936) );
AOI21X2TS U2550 ( .A0(n10935), .A1(n8804), .B0(n8803), .Y(n8805) );
AOI21X2TS U2551 ( .A0(n10935), .A1(n10899), .B0(n10898), .Y(n10900) );
AOI21X2TS U2552 ( .A0(n10935), .A1(n10845), .B0(n10844), .Y(n10846) );
AOI21X4TS U2553 ( .A0(n10935), .A1(n9606), .B0(n9605), .Y(n9607) );
AOI21X4TS U2554 ( .A0(n10935), .A1(n10962), .B0(n10961), .Y(n10963) );
XOR2X4TS U2555 ( .A(n2498), .B(n2497), .Y(DP_OP_168J26_122_4811_n1358) );
AOI21X2TS U2556 ( .A0(n2065), .A1(n9349), .B0(n9348), .Y(n9350) );
OAI21X2TS U2557 ( .A0(n2083), .A1(n9347), .B0(n9346), .Y(n9348) );
NOR2X8TS U2558 ( .A(n9132), .B(n9131), .Y(n10004) );
INVX6TS U2559 ( .A(n7688), .Y(n7702) );
INVX12TS U2560 ( .A(n2324), .Y(n2702) );
OAI22X2TS U2561 ( .A0(DP_OP_168J26_122_4811_n6594), .A1(n11769), .B0(
DP_OP_168J26_122_4811_n6608), .B1(n11736), .Y(n3712) );
NAND2X2TS U2562 ( .A(n11734), .B(n10010), .Y(DP_OP_168J26_122_4811_n103) );
OAI22X4TS U2563 ( .A0(n8011), .A1(n7014), .B0(n8009), .B1(n7016), .Y(n7020)
);
INVX4TS U2564 ( .A(Sgf_operation_ODD1_Q_left[48]), .Y(add_x_19_n108) );
OAI22X2TS U2565 ( .A0(n8068), .A1(n1895), .B0(n7291), .B1(n8577), .Y(n8077)
);
AND2X6TS U2566 ( .A(n2791), .B(n2790), .Y(n1002) );
AOI21X2TS U2567 ( .A0(n2065), .A1(n10855), .B0(n10854), .Y(n10856) );
OAI21X2TS U2568 ( .A0(n2083), .A1(n10853), .B0(n10852), .Y(n10854) );
INVX4TS U2569 ( .A(Sgf_operation_ODD1_Q_left[42]), .Y(add_x_19_n178) );
NAND2X4TS U2570 ( .A(n3207), .B(n9306), .Y(n3206) );
INVX16TS U2571 ( .A(n9399), .Y(n2065) );
AOI21X2TS U2572 ( .A0(n2065), .A1(n10817), .B0(n10816), .Y(n10818) );
OAI21X2TS U2573 ( .A0(n2084), .A1(n10815), .B0(n10814), .Y(n10816) );
INVX4TS U2574 ( .A(Sgf_operation_ODD1_Q_left[50]), .Y(add_x_19_n84) );
INVX4TS U2575 ( .A(Sgf_operation_ODD1_Q_left[49]), .Y(add_x_19_n97) );
INVX4TS U2576 ( .A(Sgf_operation_ODD1_Q_left[44]), .Y(add_x_19_n154) );
BUFX12TS U2577 ( .A(n1464), .Y(n1455) );
CLKINVX6TS U2578 ( .A(n8716), .Y(DP_OP_168J26_122_4811_n564) );
NAND2X6TS U2579 ( .A(n8715), .B(n8714), .Y(n8716) );
OAI22X2TS U2580 ( .A0(n6150), .A1(n5766), .B0(n2080), .B1(n5592), .Y(n5756)
);
OAI22X2TS U2581 ( .A0(n6150), .A1(n5956), .B0(n974), .B1(n5801), .Y(n5968)
);
BUFX20TS U2582 ( .A(n6425), .Y(n2466) );
OAI21X4TS U2583 ( .A0(n1468), .A1(n8384), .B0(n8383), .Y(n8388) );
CLKINVX12TS U2584 ( .A(n2540), .Y(n1327) );
ADDFHX4TS U2585 ( .A(n8085), .B(n8084), .CI(n8083), .CO(n8076), .S(n8097) );
INVX4TS U2586 ( .A(Sgf_operation_ODD1_Q_left[43]), .Y(add_x_19_n165) );
NAND2X4TS U2587 ( .A(n1535), .B(n1536), .Y(n2416) );
BUFX20TS U2588 ( .A(DP_OP_168J26_122_4811_n8484), .Y(n2409) );
OAI22X4TS U2589 ( .A0(n1815), .A1(n928), .B0(n2043), .B1(n1428), .Y(n6224)
);
INVX16TS U2590 ( .A(n2042), .Y(n2043) );
ADDFHX4TS U2591 ( .A(n5029), .B(n5030), .CI(n5028), .CO(n5114), .S(n5033) );
INVX8TS U2592 ( .A(n6284), .Y(n5823) );
NAND2X4TS U2593 ( .A(n1843), .B(n10006), .Y(DP_OP_168J26_122_4811_n128) );
BUFX3TS U2594 ( .A(n1964), .Y(n728) );
BUFX16TS U2595 ( .A(DP_OP_168J26_122_4811_n8216), .Y(n5677) );
OAI22X4TS U2596 ( .A0(n7473), .A1(n5676), .B0(n4186), .B1(n5677), .Y(n5887)
);
XOR2X4TS U2597 ( .A(n1311), .B(n5567), .Y(n5676) );
BUFX8TS U2598 ( .A(n3394), .Y(n730) );
OAI2BB1X4TS U2599 ( .A0N(n6307), .A1N(n733), .B0(n732), .Y(n4192) );
OAI21X4TS U2600 ( .A0(n733), .A1(n6307), .B0(n735), .Y(n732) );
XOR2X4TS U2601 ( .A(n734), .B(n733), .Y(n6332) );
NAND2X8TS U2602 ( .A(n908), .B(n909), .Y(n733) );
XOR2X4TS U2603 ( .A(n6307), .B(n735), .Y(n734) );
OAI22X4TS U2604 ( .A0(n5863), .A1(n5950), .B0(n2150), .B1(n4135), .Y(n735)
);
NAND2X8TS U2605 ( .A(n736), .B(n3007), .Y(n3006) );
NAND2X8TS U2606 ( .A(n2750), .B(n3193), .Y(n2751) );
NAND2X8TS U2607 ( .A(n9373), .B(n9371), .Y(n6941) );
INVX6TS U2608 ( .A(n4764), .Y(n2881) );
OAI2BB1X4TS U2609 ( .A0N(n2682), .A1N(n8293), .B0(n737), .Y(n6570) );
OAI21X4TS U2610 ( .A0(n8293), .A1(n2682), .B0(n8294), .Y(n737) );
NAND2X4TS U2611 ( .A(n1044), .B(n1043), .Y(n1753) );
OAI2BB1X4TS U2612 ( .A0N(n4508), .A1N(n4509), .B0(n738), .Y(n4519) );
OAI21X4TS U2613 ( .A0(n4508), .A1(n4509), .B0(n4507), .Y(n738) );
BUFX4TS U2614 ( .A(DP_OP_168J26_122_4811_n6776), .Y(n3449) );
NAND2X6TS U2615 ( .A(n2880), .B(n4763), .Y(n2879) );
NAND2X6TS U2616 ( .A(n1616), .B(n6726), .Y(n1619) );
INVX12TS U2617 ( .A(n1937), .Y(n1939) );
OAI22X4TS U2618 ( .A0(n6174), .A1(n5593), .B0(n2450), .B1(n5564), .Y(n5585)
);
INVX16TS U2619 ( .A(n5500), .Y(n2037) );
OAI22X2TS U2620 ( .A0(n6530), .A1(n2108), .B0(n6466), .B1(n1955), .Y(n6533)
);
AO21X4TS U2621 ( .A0(n4984), .A1(n1990), .B0(n932), .Y(n8042) );
OAI22X4TS U2622 ( .A0(n6164), .A1(n2261), .B0(n3880), .B1(n6048), .Y(n6185)
);
OAI22X4TS U2623 ( .A0(n4635), .A1(n2036), .B0(n4634), .B1(n9755), .Y(n4641)
);
OAI22X2TS U2624 ( .A0(n4298), .A1(n2259), .B0(n4297), .B1(n4061), .Y(n4306)
);
BUFX4TS U2625 ( .A(n2013), .Y(n741) );
INVX8TS U2626 ( .A(n742), .Y(n5407) );
XNOR2X4TS U2627 ( .A(n1225), .B(n4217), .Y(n742) );
BUFX12TS U2628 ( .A(n7438), .Y(n743) );
BUFX20TS U2629 ( .A(DP_OP_168J26_122_4811_n8250), .Y(n6093) );
NAND2X8TS U2630 ( .A(n1773), .B(n2611), .Y(n1774) );
OAI22X4TS U2631 ( .A0(n744), .A1(n1896), .B0(n3393), .B1(n5861), .Y(n6307)
);
XOR2X4TS U2632 ( .A(n5721), .B(n917), .Y(n744) );
INVX8TS U2633 ( .A(n9837), .Y(n959) );
OAI22X4TS U2634 ( .A0(n5800), .A1(n11757), .B0(n6174), .B1(n5963), .Y(n5969)
);
INVX6TS U2635 ( .A(n746), .Y(n2944) );
OAI21X4TS U2636 ( .A0(n3375), .A1(n1402), .B0(n3374), .Y(n746) );
INVX12TS U2637 ( .A(n6068), .Y(n2038) );
OAI22X4TS U2638 ( .A0(n7445), .A1(n3899), .B0(n3527), .B1(n1921), .Y(n3905)
);
XOR2X4TS U2639 ( .A(n7449), .B(n747), .Y(n3899) );
OAI2BB1X4TS U2640 ( .A0N(n8243), .A1N(n8244), .B0(n748), .Y(n5998) );
OAI21X4TS U2641 ( .A0(n8244), .A1(n8243), .B0(n8242), .Y(n748) );
INVX12TS U2642 ( .A(n6223), .Y(n2028) );
XOR2X4TS U2643 ( .A(n2985), .B(n749), .Y(n5503) );
OAI22X2TS U2644 ( .A0(n8022), .A1(n1719), .B0(n1989), .B1(n3674), .Y(n3688)
);
OAI22X4TS U2645 ( .A0(n1607), .A1(n3962), .B0(n7993), .B1(n1504), .Y(n4537)
);
OAI22X4TS U2646 ( .A0(n4984), .A1(n5324), .B0(n4239), .B1(n1990), .Y(n5383)
);
OAI22X4TS U2647 ( .A0(n2105), .A1(n3419), .B0(n1921), .B1(n3424), .Y(n3438)
);
BUFX16TS U2648 ( .A(DP_OP_168J26_122_4811_n6569), .Y(n750) );
BUFX4TS U2649 ( .A(DP_OP_168J26_122_4811_n8216), .Y(n808) );
ADDHX4TS U2650 ( .A(n6689), .B(n6690), .CO(n6687), .S(n6916) );
ADDFHX4TS U2651 ( .A(n6841), .B(n6842), .CI(n6840), .CO(n6825), .S(n6852) );
BUFX6TS U2652 ( .A(n9736), .Y(n751) );
XNOR2X2TS U2653 ( .A(n5960), .B(n1220), .Y(n4442) );
OAI22X4TS U2654 ( .A0(n730), .A1(n7472), .B0(n1916), .B1(n7470), .Y(n7520)
);
XNOR2X2TS U2655 ( .A(n3640), .B(n1904), .Y(n4300) );
INVX6TS U2656 ( .A(n8189), .Y(n4650) );
INVX12TS U2657 ( .A(n3652), .Y(n7353) );
INVX16TS U2658 ( .A(n752), .Y(n2017) );
CLKINVX12TS U2659 ( .A(DP_OP_168J26_122_4811_n8166), .Y(n752) );
BUFX4TS U2660 ( .A(n5427), .Y(n753) );
NAND2X6TS U2661 ( .A(n10629), .B(n5095), .Y(n1798) );
BUFX20TS U2662 ( .A(n1607), .Y(n795) );
OAI21X4TS U2663 ( .A0(n11059), .A1(n11309), .B0(n11060), .Y(n5070) );
OAI22X4TS U2664 ( .A0(n4980), .A1(n1990), .B0(n4981), .B1(n2025), .Y(n5015)
);
NAND2X4TS U2665 ( .A(n5062), .B(n5061), .Y(n1744) );
NAND2X8TS U2666 ( .A(n9370), .B(n9373), .Y(n3142) );
INVX6TS U2667 ( .A(n755), .Y(n3166) );
OAI2BB1X4TS U2668 ( .A0N(n11749), .A1N(n3776), .B0(n756), .Y(n755) );
INVX2TS U2669 ( .A(n4845), .Y(n757) );
OAI2BB1X4TS U2670 ( .A0N(n758), .A1N(n757), .B0(n4843), .Y(n1588) );
BUFX12TS U2671 ( .A(n6877), .Y(n759) );
BUFX20TS U2672 ( .A(n3789), .Y(n8441) );
INVX4TS U2673 ( .A(n5737), .Y(n2347) );
XNOR2X4TS U2674 ( .A(n1331), .B(n5737), .Y(n3068) );
BUFX12TS U2675 ( .A(n11676), .Y(n760) );
OR2X8TS U2676 ( .A(n1897), .B(n5720), .Y(n929) );
OAI22X4TS U2677 ( .A0(n1931), .A1(n1883), .B0(n7490), .B1(n1303), .Y(n4126)
);
OAI21X4TS U2678 ( .A0(n1042), .A1(n762), .B0(n2152), .Y(n9849) );
NOR2X4TS U2679 ( .A(n9852), .B(n1675), .Y(n762) );
NOR2X8TS U2680 ( .A(n2512), .B(n1424), .Y(n1042) );
NOR2X6TS U2681 ( .A(n1563), .B(n1411), .Y(n1562) );
OAI22X4TS U2682 ( .A0(n2379), .A1(n3882), .B0(n1897), .B1(n3531), .Y(n3906)
);
INVX6TS U2683 ( .A(n3672), .Y(n3710) );
CLKINVX12TS U2684 ( .A(n2292), .Y(n860) );
OAI22X2TS U2685 ( .A0(n2071), .A1(n2927), .B0(n2828), .B1(n1959), .Y(n5381)
);
BUFX4TS U2686 ( .A(n3307), .Y(n822) );
XOR2X4TS U2687 ( .A(n3508), .B(n3509), .Y(n2373) );
XOR2X4TS U2688 ( .A(n828), .B(n3474), .Y(n3508) );
XOR2X4TS U2689 ( .A(n6729), .B(n6730), .Y(n2584) );
OAI21X4TS U2690 ( .A0(n4248), .A1(n4249), .B0(n4247), .Y(n3240) );
NAND2BX4TS U2691 ( .AN(n1332), .B(n5737), .Y(n3067) );
XNOR2X4TS U2692 ( .A(n8892), .B(n1927), .Y(n5543) );
OAI22X4TS U2693 ( .A0(n1866), .A1(n5577), .B0(n3320), .B1(n5606), .Y(n5603)
);
AOI21X2TS U2694 ( .A0(n9225), .A1(n7737), .B0(n7736), .Y(n7738) );
XOR2X4TS U2695 ( .A(n11525), .B(n2440), .Y(n2908) );
OAI22X4TS U2696 ( .A0(n1084), .A1(n5605), .B0(n2081), .B1(n5675), .Y(n5659)
);
XOR2X4TS U2697 ( .A(n1716), .B(n1837), .Y(n3658) );
NAND2BX4TS U2698 ( .AN(n8005), .B(n11509), .Y(n4922) );
OAI22X4TS U2699 ( .A0(n4128), .A1(n7477), .B0(n1896), .B1(n4113), .Y(n4172)
);
OAI2BB1X4TS U2700 ( .A0N(n4272), .A1N(n4271), .B0(n2395), .Y(n4378) );
INVX6TS U2701 ( .A(n8900), .Y(n8958) );
NAND2X4TS U2702 ( .A(n1675), .B(n9852), .Y(n2152) );
OAI22X4TS U2703 ( .A0(n3525), .A1(n7491), .B0(n3878), .B1(n5950), .Y(n3898)
);
INVX12TS U2704 ( .A(n1912), .Y(n1913) );
BUFX6TS U2705 ( .A(n1311), .Y(n763) );
NAND2X6TS U2706 ( .A(n1513), .B(n6376), .Y(n1512) );
XOR2X4TS U2707 ( .A(n2968), .B(n764), .Y(n3214) );
CLKINVX12TS U2708 ( .A(n3042), .Y(n4413) );
BUFX16TS U2709 ( .A(DP_OP_168J26_122_4811_n5160), .Y(n765) );
XNOR2X4TS U2710 ( .A(n2074), .B(n6160), .Y(n3487) );
INVX8TS U2711 ( .A(n11509), .Y(n1809) );
XOR2X2TS U2712 ( .A(n11509), .B(n2093), .Y(n5286) );
OAI22X4TS U2713 ( .A0(n1516), .A1(n5279), .B0(n1958), .B1(n5327), .Y(n5313)
);
NAND2X8TS U2714 ( .A(n2392), .B(n2391), .Y(n5971) );
XOR2X4TS U2715 ( .A(n767), .B(n9950), .Y(DP_OP_168J26_122_4811_n1106) );
XNOR2X4TS U2716 ( .A(n1848), .B(n1264), .Y(n767) );
OAI22X2TS U2717 ( .A0(n8644), .A1(n2109), .B0(n8642), .B1(n1962), .Y(n8683)
);
INVX12TS U2718 ( .A(n3241), .Y(n8550) );
OAI22X4TS U2719 ( .A0(n5302), .A1(n5179), .B0(n1925), .B1(n5234), .Y(n5219)
);
OAI22X4TS U2720 ( .A0(n8112), .A1(n1894), .B0(n8069), .B1(n8935), .Y(n8147)
);
OAI22X4TS U2721 ( .A0(n8571), .A1(n2112), .B0(n4262), .B1(n2575), .Y(n9835)
);
XNOR2X4TS U2722 ( .A(n6714), .B(n1242), .Y(n1236) );
OAI22X4TS U2723 ( .A0(n3882), .A1(n1896), .B0(n7477), .B1(n4113), .Y(n4121)
);
BUFX16TS U2724 ( .A(n5469), .Y(n2546) );
NOR2X6TS U2725 ( .A(n7759), .B(n7756), .Y(n2193) );
XNOR2X4TS U2726 ( .A(n7277), .B(DP_OP_168J26_122_4811_n8486), .Y(n3695) );
BUFX20TS U2727 ( .A(n1240), .Y(n1831) );
OAI21X4TS U2728 ( .A0(n2388), .A1(n3588), .B0(n3587), .Y(n2298) );
CLKINVX12TS U2729 ( .A(n8820), .Y(n7926) );
NAND2X6TS U2730 ( .A(n850), .B(n2653), .Y(n853) );
NAND2X6TS U2731 ( .A(n897), .B(n851), .Y(n852) );
NAND3X4TS U2732 ( .A(n9398), .B(n9396), .C(n9397), .Y(n400) );
ADDFHX4TS U2733 ( .A(n7466), .B(n7465), .CI(n7464), .CO(n7507), .S(n7497) );
OAI22X4TS U2734 ( .A0(n4174), .A1(n2059), .B0(n1915), .B1(n4190), .Y(n6304)
);
XOR2X4TS U2735 ( .A(n1029), .B(n2341), .Y(n4174) );
OAI22X4TS U2736 ( .A0(n729), .A1(n4791), .B0(n7447), .B1(n5677), .Y(n7454)
);
XOR2X4TS U2737 ( .A(n2440), .B(n1305), .Y(n4791) );
XOR2X4TS U2738 ( .A(n1850), .B(n769), .Y(n5678) );
XNOR2X4TS U2739 ( .A(n6751), .B(n6746), .Y(n3051) );
XNOR2X4TS U2740 ( .A(n7438), .B(n7439), .Y(n7480) );
XOR2X4TS U2741 ( .A(n3808), .B(n2366), .Y(n4010) );
OAI22X4TS U2742 ( .A0(n7170), .A1(n1973), .B0(n7224), .B1(n2339), .Y(n7207)
);
AOI2BB2X4TS U2743 ( .B0(n10871), .B1(n10872), .A0N(n10946), .A1N(n11862),
.Y(n12339) );
AOI21X4TS U2744 ( .A0(n10945), .A1(n10863), .B0(n9590), .Y(n9591) );
OAI21X4TS U2745 ( .A0(n1609), .A1(n9592), .B0(n9591), .Y(n9597) );
ADDFHX4TS U2746 ( .A(n9010), .B(n9009), .CI(n9008), .CO(n9110), .S(n9078) );
BUFX8TS U2747 ( .A(n2018), .Y(n823) );
BUFX4TS U2748 ( .A(DP_OP_168J26_122_4811_n8518), .Y(n770) );
NAND2X4TS U2749 ( .A(n2347), .B(n1332), .Y(n2405) );
OAI22X4TS U2750 ( .A0(n4446), .A1(n7491), .B0(n4444), .B1(n7492), .Y(n4472)
);
CLKINVX12TS U2751 ( .A(n2292), .Y(n1963) );
OAI2BB1X4TS U2752 ( .A0N(n872), .A1N(n5729), .B0(n2264), .Y(n5741) );
NAND2X6TS U2753 ( .A(n2654), .B(n2800), .Y(n2992) );
NAND2X8TS U2754 ( .A(n2859), .B(n2858), .Y(n2800) );
OAI2BB1X4TS U2755 ( .A0N(n5920), .A1N(n5919), .B0(n771), .Y(n8478) );
OAI21X4TS U2756 ( .A0(n5920), .A1(n5919), .B0(n5918), .Y(n771) );
OAI21X2TS U2757 ( .A0(n4410), .A1(n4409), .B0(n4408), .Y(n772) );
XOR2X4TS U2758 ( .A(n773), .B(n4410), .Y(n4411) );
XOR2X4TS U2759 ( .A(n4408), .B(n4409), .Y(n773) );
XOR2X4TS U2760 ( .A(n3034), .B(n1018), .Y(n2838) );
NAND2X8TS U2761 ( .A(n774), .B(n2497), .Y(n1552) );
NAND2X8TS U2762 ( .A(n1555), .B(n1554), .Y(n774) );
INVX8TS U2763 ( .A(n6386), .Y(n4311) );
OAI21X4TS U2764 ( .A0(n7968), .A1(n7974), .B0(n7975), .Y(n1486) );
OAI21X4TS U2765 ( .A0(DP_OP_168J26_122_4811_n8520), .A1(n1716), .B0(n1260),
.Y(n775) );
NAND2X4TS U2766 ( .A(n2367), .B(n776), .Y(n9943) );
OAI21X4TS U2767 ( .A0(n2370), .A1(n10046), .B0(n10045), .Y(n776) );
OAI22X4TS U2768 ( .A0(n1084), .A1(n5592), .B0(n5591), .B1(n973), .Y(n5717)
);
XOR2X4TS U2769 ( .A(n1223), .B(n1291), .Y(n5592) );
NAND2X8TS U2770 ( .A(n778), .B(n860), .Y(n844) );
AND2X8TS U2771 ( .A(n8464), .B(n779), .Y(n8536) );
XOR2X4TS U2772 ( .A(n8464), .B(n779), .Y(n8506) );
OAI22X4TS U2773 ( .A0(n9457), .A1(n4353), .B0(n2050), .B1(n4352), .Y(n779)
);
OAI22X4TS U2774 ( .A0(n5141), .A1(n8015), .B0(n2568), .B1(n5168), .Y(n5171)
);
XOR2X4TS U2775 ( .A(n2486), .B(n6977), .Y(n780) );
OAI22X4TS U2776 ( .A0(n8541), .A1(n8583), .B0(n8584), .B1(n2054), .Y(n8555)
);
OAI22X4TS U2777 ( .A0(n4186), .A1(n2100), .B0(n4166), .B1(n7471), .Y(n4200)
);
OAI2BB1X4TS U2778 ( .A0N(n3233), .A1N(n781), .B0(n3941), .Y(n2433) );
NAND2X4TS U2779 ( .A(n5374), .B(n2897), .Y(n2896) );
XOR2X4TS U2780 ( .A(n1850), .B(n783), .Y(n5622) );
NAND3X4TS U2781 ( .A(n1788), .B(n1787), .C(n1789), .Y(n5911) );
OAI21X4TS U2782 ( .A0(n5421), .A1(n5420), .B0(n5419), .Y(n2901) );
OAI22X4TS U2783 ( .A0(n8934), .A1(n8935), .B0(n4686), .B1(n1895), .Y(n8988)
);
OAI22X4TS U2784 ( .A0(n5275), .A1(n979), .B0(n2904), .B1(n5318), .Y(n5250)
);
OAI22X4TS U2785 ( .A0(n729), .A1(n1031), .B0(n5553), .B1(n5677), .Y(n5609)
);
XNOR2X4TS U2786 ( .A(n2625), .B(n1861), .Y(n5322) );
OAI22X2TS U2787 ( .A0(n4081), .A1(n8583), .B0(n4080), .B1(n2055), .Y(n4292)
);
OAI22X4TS U2788 ( .A0(n4362), .A1(n8980), .B0(n4361), .B1(n1823), .Y(n9775)
);
XOR2X4TS U2789 ( .A(n5350), .B(n5351), .Y(n2895) );
XOR2X4TS U2790 ( .A(n9854), .B(n9855), .Y(n3185) );
XNOR2X4TS U2791 ( .A(n886), .B(n2408), .Y(n8462) );
OAI22X4TS U2792 ( .A0(n3530), .A1(n1222), .B0(n3321), .B1(n3498), .Y(n3544)
);
NAND2X8TS U2793 ( .A(n1802), .B(n1803), .Y(n4242) );
NAND2X4TS U2794 ( .A(n6729), .B(n6730), .Y(n784) );
OAI22X4TS U2795 ( .A0(n6586), .A1(n1985), .B0(n6544), .B1(n1932), .Y(n6581)
);
OAI21X4TS U2796 ( .A0(n2658), .A1(DP_OP_168J26_122_4811_n3552), .B0(
DP_OP_168J26_122_4811_n3553), .Y(n3357) );
XOR2X4TS U2797 ( .A(n3093), .B(n6588), .Y(n6617) );
XOR2X4TS U2798 ( .A(n11528), .B(n1291), .Y(n6025) );
INVX8TS U2799 ( .A(n2302), .Y(n9859) );
BUFX6TS U2800 ( .A(n1364), .Y(n786) );
OAI22X4TS U2801 ( .A0(n861), .A1(n4019), .B0(n7993), .B1(n3844), .Y(n4032)
);
XOR2X4TS U2802 ( .A(n787), .B(n5426), .Y(n1596) );
XOR2X4TS U2803 ( .A(n5425), .B(n5427), .Y(n787) );
BUFX20TS U2804 ( .A(n2292), .Y(n1607) );
ADDFHX2TS U2805 ( .A(n7248), .B(n7247), .CI(n7246), .CO(n7295), .S(n7548) );
XOR2X4TS U2806 ( .A(n8205), .B(n8206), .Y(n2606) );
BUFX16TS U2807 ( .A(DP_OP_168J26_122_4811_n6563), .Y(n790) );
XOR2X4TS U2808 ( .A(n791), .B(n10017), .Y(n4427) );
XOR2X4TS U2809 ( .A(n10019), .B(n10018), .Y(n791) );
INVX8TS U2810 ( .A(n1791), .Y(n1265) );
INVX16TS U2811 ( .A(DP_OP_168J26_122_4811_n6644), .Y(n5283) );
OAI22X4TS U2812 ( .A0(n1980), .A1(n866), .B0(n2568), .B1(n4826), .Y(n5182)
);
NAND2X6TS U2813 ( .A(n814), .B(n797), .Y(n4216) );
INVX4TS U2814 ( .A(n5189), .Y(n3081) );
OAI22X2TS U2815 ( .A0(n6223), .A1(n6035), .B0(n11754), .B1(n6015), .Y(n6032)
);
OAI22X4TS U2816 ( .A0(n1941), .A1(n4840), .B0(n4881), .B1(n2088), .Y(n4892)
);
XNOR2X4TS U2817 ( .A(n2403), .B(n5666), .Y(n5552) );
OAI22X4TS U2818 ( .A0(n6416), .A1(n1940), .B0(n6415), .B1(n8938), .Y(n6428)
);
OAI22X4TS U2819 ( .A0(n4546), .A1(n1923), .B0(n4541), .B1(n2411), .Y(n4543)
);
XNOR2X4TS U2820 ( .A(n790), .B(n2094), .Y(n8010) );
INVX6TS U2821 ( .A(n1686), .Y(n1687) );
ADDFHX2TS U2822 ( .A(n4674), .B(n4673), .CI(n4672), .CO(n8200), .S(n4663) );
NAND3X8TS U2823 ( .A(n794), .B(n5133), .C(n2728), .Y(n2919) );
NAND2X8TS U2824 ( .A(n2144), .B(n2690), .Y(n794) );
XNOR2X4TS U2825 ( .A(n7279), .B(n7273), .Y(n3963) );
XOR2X4TS U2826 ( .A(n1271), .B(n2592), .Y(n3497) );
BUFX6TS U2827 ( .A(n1649), .Y(n796) );
XOR2X4TS U2828 ( .A(n4215), .B(n4216), .Y(n1225) );
NAND2X2TS U2829 ( .A(n4234), .B(n4235), .Y(n797) );
BUFX8TS U2830 ( .A(n8587), .Y(n798) );
OAI22X4TS U2831 ( .A0(n2422), .A1(n890), .B0(n4228), .B1(n799), .Y(n5384) );
BUFX12TS U2832 ( .A(n11767), .Y(n800) );
BUFX20TS U2833 ( .A(DP_OP_168J26_122_4811_n8460), .Y(n5960) );
OAI22X4TS U2834 ( .A0(n3407), .A1(n2100), .B0(n7471), .B1(n4442), .Y(n4435)
);
NAND2X8TS U2835 ( .A(n2764), .B(n2763), .Y(n6726) );
XOR2X4TS U2836 ( .A(n2069), .B(n803), .Y(n4224) );
INVX12TS U2837 ( .A(n8430), .Y(n2529) );
BUFX16TS U2838 ( .A(DP_OP_168J26_122_4811_n6644), .Y(n2590) );
NAND2X8TS U2839 ( .A(n804), .B(n3120), .Y(n1786) );
NAND2X8TS U2840 ( .A(n805), .B(n5460), .Y(n804) );
BUFX20TS U2841 ( .A(DP_OP_168J26_122_4811_n8242), .Y(n7242) );
BUFX20TS U2842 ( .A(n2549), .Y(n2238) );
NAND2X8TS U2843 ( .A(n1562), .B(n1032), .Y(n3776) );
AOI21X4TS U2844 ( .A0(DP_OP_168J26_122_4811_n614), .A1(n10005), .B0(n806),
.Y(DP_OP_168J26_122_4811_n592) );
OAI21X4TS U2845 ( .A0(n9986), .A1(n2291), .B0(n9987), .Y(n806) );
NOR2BX4TS U2846 ( .AN(n8180), .B(n2237), .Y(n1427) );
CLKBUFX2TS U2847 ( .A(n1402), .Y(n807) );
OAI22X4TS U2848 ( .A0(n1939), .A1(n5753), .B0(n5795), .B1(n6087), .Y(n5797)
);
NAND3X6TS U2849 ( .A(n1004), .B(n1497), .C(n3754), .Y(n809) );
XNOR2X4TS U2850 ( .A(n810), .B(n5823), .Y(n1340) );
XNOR2X4TS U2851 ( .A(n5822), .B(n5824), .Y(n810) );
NAND2X6TS U2852 ( .A(n3613), .B(n3612), .Y(n3935) );
OAI22X4TS U2853 ( .A0(n1924), .A1(n3819), .B0(n3851), .B1(n2087), .Y(n3832)
);
ADDFHX4TS U2854 ( .A(n6463), .B(n6462), .CI(n6461), .CO(n6469), .S(n6411) );
OAI22X4TS U2855 ( .A0(n7445), .A1(n5792), .B0(n1918), .B1(n5764), .Y(n5805)
);
XNOR2X4TS U2856 ( .A(n3308), .B(n6181), .Y(n5681) );
OAI22X4TS U2857 ( .A0(n5284), .A1(n2087), .B0(n1924), .B1(n5301), .Y(n5312)
);
OAI22X4TS U2858 ( .A0(n8573), .A1(n1944), .B0(n8575), .B1(n1983), .Y(n9798)
);
XOR2X4TS U2859 ( .A(n1818), .B(n811), .Y(n8573) );
XOR2X4TS U2860 ( .A(n1063), .B(n1066), .Y(n1062) );
OAI22X2TS U2861 ( .A0(n6656), .A1(n6885), .B0(n6666), .B1(n2097), .Y(n6702)
);
OAI21X4TS U2862 ( .A0(n8485), .A1(n1304), .B0(n8484), .Y(n812) );
OAI21X4TS U2863 ( .A0(n4235), .A1(n4234), .B0(n1048), .Y(n814) );
INVX12TS U2864 ( .A(n1714), .Y(n1715) );
NOR2X8TS U2865 ( .A(n6985), .B(n6984), .Y(n8351) );
NAND2X8TS U2866 ( .A(n6848), .B(n5276), .Y(n2142) );
INVX16TS U2867 ( .A(n5283), .Y(n2069) );
INVX16TS U2868 ( .A(n1055), .Y(n8898) );
NAND2X6TS U2869 ( .A(n2525), .B(n9810), .Y(n3187) );
NAND2X6TS U2870 ( .A(n1003), .B(n1497), .Y(n1496) );
AND2X6TS U2871 ( .A(n4074), .B(n3373), .Y(n848) );
XOR2X4TS U2872 ( .A(DP_OP_168J26_122_4811_n8539), .B(n1333), .Y(n3919) );
XOR2X4TS U2873 ( .A(n6351), .B(n6352), .Y(n1471) );
NAND2X8TS U2874 ( .A(n2471), .B(n815), .Y(n8311) );
OAI21X4TS U2875 ( .A0(n6526), .A1(n6525), .B0(n6524), .Y(n815) );
OAI2BB1X4TS U2876 ( .A0N(n8283), .A1N(n1764), .B0(n3125), .Y(n8288) );
OAI21X4TS U2877 ( .A0(n1310), .A1(n8316), .B0(n8314), .Y(n817) );
BUFX12TS U2878 ( .A(n1232), .Y(n1044) );
NAND2X8TS U2879 ( .A(n2849), .B(n6875), .Y(n3162) );
XOR2X4TS U2880 ( .A(n5567), .B(n1219), .Y(n3879) );
XOR2X4TS U2881 ( .A(n4253), .B(n4254), .Y(n1523) );
NAND2X6TS U2882 ( .A(n1522), .B(n819), .Y(n4253) );
NAND2X2TS U2883 ( .A(n5367), .B(n5368), .Y(n819) );
NAND2X6TS U2884 ( .A(n2978), .B(n2977), .Y(n3566) );
OR2X8TS U2885 ( .A(n1516), .B(n2828), .Y(n1802) );
OR2X8TS U2886 ( .A(n1752), .B(n6798), .Y(n1642) );
BUFX6TS U2887 ( .A(Op_MY[23]), .Y(n820) );
ADDFHX2TS U2888 ( .A(n5163), .B(n5165), .CI(n5164), .CO(n5230), .S(n5190) );
OAI22X4TS U2889 ( .A0(n5896), .A1(n6919), .B0(n5895), .B1(n6921), .Y(n5908)
);
XOR2X4TS U2890 ( .A(n6526), .B(n6525), .Y(n2470) );
XOR2X4TS U2891 ( .A(n2929), .B(n7091), .Y(n2345) );
OAI22X4TS U2892 ( .A0(n7085), .A1(n2222), .B0(n5320), .B1(n3184), .Y(n2929)
);
XNOR2X4TS U2893 ( .A(n1818), .B(n6435), .Y(n3931) );
XNOR2X4TS U2894 ( .A(n2147), .B(n750), .Y(n4041) );
XNOR2X4TS U2895 ( .A(n821), .B(n3041), .Y(n4869) );
XOR2X4TS U2896 ( .A(n3040), .B(n4827), .Y(n821) );
OAI22X4TS U2897 ( .A0(n7492), .A1(n5948), .B0(n5796), .B1(n2150), .Y(n5964)
);
XNOR2X4TS U2898 ( .A(n5256), .B(DP_OP_168J26_122_4811_n8482), .Y(n4231) );
ADDFHX2TS U2899 ( .A(n5011), .B(n5009), .CI(n5010), .CO(n5000), .S(n5072) );
BUFX16TS U2900 ( .A(n3214), .Y(n958) );
OR2X8TS U2901 ( .A(n6003), .B(n4194), .Y(n873) );
XNOR2X4TS U2902 ( .A(n2464), .B(DP_OP_168J26_122_4811_n6782), .Y(n4194) );
NAND2X8TS U2903 ( .A(n3998), .B(n6465), .Y(n8643) );
NAND2X8TS U2904 ( .A(DP_OP_168J26_122_4811_n6618), .B(n3646), .Y(n3647) );
NAND2X8TS U2905 ( .A(n1544), .B(n1419), .Y(n5374) );
NAND2X8TS U2906 ( .A(n3877), .B(DP_OP_168J26_122_4811_n8193), .Y(n3524) );
NAND3X4TS U2907 ( .A(n1844), .B(n1846), .C(n1845), .Y(n7246) );
BUFX12TS U2908 ( .A(DP_OP_168J26_122_4811_n8473), .Y(n826) );
XNOR2X4TS U2909 ( .A(n953), .B(DP_OP_168J26_122_4811_n8516), .Y(n3945) );
OAI22X2TS U2910 ( .A0(n7492), .A1(n1035), .B0(n7491), .B1(n928), .Y(n7517)
);
OAI21X4TS U2911 ( .A0(n2841), .A1(n2292), .B0(n1666), .Y(n5371) );
XNOR2X4TS U2912 ( .A(n7438), .B(n2403), .Y(n7234) );
XOR2X4TS U2913 ( .A(n7449), .B(n1872), .Y(n4140) );
XOR2X4TS U2914 ( .A(n11782), .B(n1861), .Y(n4020) );
OAI2BB1X4TS U2915 ( .A0N(n3473), .A1N(n3474), .B0(n827), .Y(n3429) );
OAI21X4TS U2916 ( .A0(n3474), .A1(n3473), .B0(n3475), .Y(n827) );
XOR2X4TS U2917 ( .A(n3475), .B(n3473), .Y(n828) );
BUFX6TS U2918 ( .A(n6940), .Y(n2164) );
ADDFHX2TS U2919 ( .A(n8998), .B(n8997), .CI(n8996), .CO(n9100), .S(n9096) );
NAND2X6TS U2920 ( .A(n1089), .B(n1088), .Y(n3865) );
OAI22X4TS U2921 ( .A0(n5516), .A1(n6885), .B0(n5784), .B1(n2099), .Y(n5697)
);
XOR2X4TS U2922 ( .A(n1027), .B(n829), .Y(n5516) );
XNOR2X4TS U2923 ( .A(n2323), .B(DP_OP_168J26_122_4811_n8448), .Y(n6149) );
OR2X8TS U2924 ( .A(n1621), .B(n9810), .Y(n3189) );
OR2X8TS U2925 ( .A(n5054), .B(n11758), .Y(n1631) );
INVX6TS U2926 ( .A(n1402), .Y(n4075) );
XOR2X4TS U2927 ( .A(n5061), .B(n1742), .Y(n5064) );
XOR2X4TS U2928 ( .A(n830), .B(n1005), .Y(n3752) );
XOR2X4TS U2929 ( .A(n3703), .B(n2801), .Y(n830) );
XOR2X4TS U2930 ( .A(n11500), .B(n4450), .Y(n3459) );
XOR2X4TS U2931 ( .A(n831), .B(n6951), .Y(n6982) );
XNOR2X4TS U2932 ( .A(n6952), .B(n3205), .Y(n831) );
NAND2X8TS U2933 ( .A(n6908), .B(n832), .Y(n3146) );
XNOR2X4TS U2934 ( .A(n6093), .B(n3451), .Y(n6097) );
NAND2X6TS U2935 ( .A(n5904), .B(n5905), .Y(n1697) );
INVX4TS U2936 ( .A(n6289), .Y(n5739) );
XNOR2X4TS U2937 ( .A(n834), .B(n5729), .Y(n5833) );
XNOR2X4TS U2938 ( .A(n5730), .B(n5731), .Y(n834) );
NAND3X8TS U2939 ( .A(n835), .B(n3179), .C(n3140), .Y(
DP_OP_168J26_122_4811_n201) );
NAND4X8TS U2940 ( .A(n2680), .B(n2679), .C(n3178), .D(n10101), .Y(n835) );
NAND2X8TS U2941 ( .A(DP_OP_168J26_122_4811_n8216), .B(
DP_OP_168J26_122_4811_n8190), .Y(n3394) );
NAND2BX2TS U2942 ( .AN(n6633), .B(n2410), .Y(n6758) );
OR2X8TS U2943 ( .A(n9032), .B(n9033), .Y(n11760) );
NOR2X8TS U2944 ( .A(n9325), .B(n9320), .Y(n2892) );
NOR2X8TS U2945 ( .A(n2175), .B(n798), .Y(n9325) );
INVX8TS U2946 ( .A(n6413), .Y(n6492) );
INVX6TS U2947 ( .A(n6749), .Y(n6890) );
NAND2X8TS U2948 ( .A(n1552), .B(n1551), .Y(n9905) );
OAI22X4TS U2949 ( .A0(n6146), .A1(n6174), .B0(n11757), .B1(n6173), .Y(n6159)
);
INVX6TS U2950 ( .A(add_x_19_n830), .Y(add_x_19_n733) );
OR2X8TS U2951 ( .A(n5961), .B(n3880), .Y(n1627) );
OAI22X4TS U2952 ( .A0(n6178), .A1(n6036), .B0(n6008), .B1(n6176), .Y(n6033)
);
XNOR2X2TS U2953 ( .A(DP_OP_168J26_122_4811_n8448), .B(n6055), .Y(n6036) );
NOR2X8TS U2954 ( .A(Sgf_operation_ODD1_S_B[11]), .B(
Sgf_operation_ODD1_Q_right[38]), .Y(add_x_19_n705) );
XNOR2X4TS U2955 ( .A(n3206), .B(n8353), .Y(Sgf_operation_ODD1_S_B[11]) );
INVX16TS U2956 ( .A(n6141), .Y(n1812) );
OAI22X4TS U2957 ( .A0(n1364), .A1(n7443), .B0(n4792), .B1(n7486), .Y(n7453)
);
NAND2X2TS U2958 ( .A(n9648), .B(n1367), .Y(n9578) );
OAI22X4TS U2959 ( .A0(n3499), .A1(n2073), .B0(n1897), .B1(n3458), .Y(n3504)
);
XNOR2X4TS U2960 ( .A(n5960), .B(n7242), .Y(n3458) );
INVX16TS U2961 ( .A(n5665), .Y(n1911) );
ADDFHX4TS U2962 ( .A(n7372), .B(n7371), .CI(n7370), .CO(n7395), .S(n7374) );
NAND2X8TS U2963 ( .A(n1588), .B(n1758), .Y(n4854) );
XOR2X4TS U2964 ( .A(n4395), .B(n4394), .Y(n3245) );
NAND3X8TS U2965 ( .A(n1004), .B(n1497), .C(n3382), .Y(n2972) );
BUFX16TS U2966 ( .A(DP_OP_168J26_122_4811_n6579), .Y(n2591) );
OAI22X2TS U2967 ( .A0(n1981), .A1(n3676), .B0(n2157), .B1(n3665), .Y(n3706)
);
OAI22X4TS U2968 ( .A0(n2053), .A1(n5495), .B0(n5496), .B1(n8950), .Y(n5539)
);
NAND2X8TS U2969 ( .A(n4485), .B(n3619), .Y(n8950) );
ADDFHX2TS U2970 ( .A(n4708), .B(n4707), .CI(n4706), .CO(n4720), .S(n9914) );
BUFX4TS U2971 ( .A(n6388), .Y(n2551) );
OAI21X4TS U2972 ( .A0(n9938), .A1(n9937), .B0(n9936), .Y(n3164) );
OAI2BB1X4TS U2973 ( .A0N(n6231), .A1N(n6230), .B0(n2623), .Y(n1653) );
BUFX6TS U2974 ( .A(n1684), .Y(n840) );
OAI22X4TS U2975 ( .A0(n1981), .A1(n7018), .B0(n8013), .B1(n866), .Y(n7122)
);
OAI21X4TS U2976 ( .A0(n1897), .A1(n5705), .B0(n902), .Y(n5768) );
OAI2BB1X4TS U2977 ( .A0N(n1429), .A1N(n2721), .B0(n2867), .Y(n2699) );
OAI22X4TS U2978 ( .A0(n730), .A1(n7234), .B0(n7471), .B1(n7041), .Y(n7240)
);
XNOR2X4TS U2979 ( .A(n5960), .B(n7442), .Y(n4456) );
OAI2BB1X4TS U2980 ( .A0N(n1737), .A1N(n11516), .B0(n1831), .Y(n3385) );
XOR2X4TS U2981 ( .A(n2380), .B(n880), .Y(n3400) );
OAI22X4TS U2982 ( .A0(n1934), .A1(n3980), .B0(n4553), .B1(n1991), .Y(n4552)
);
XOR2X4TS U2983 ( .A(n2931), .B(n5270), .Y(n3980) );
OAI22X4TS U2984 ( .A0(n1981), .A1(n1590), .B0(n2157), .B1(n7052), .Y(n7263)
);
XOR2X4TS U2985 ( .A(n12046), .B(n5273), .Y(n1590) );
OAI22X4TS U2986 ( .A0(n6154), .A1(n6012), .B0(n3320), .B1(n6017), .Y(n6021)
);
OAI21X4TS U2987 ( .A0(n3478), .A1(n3477), .B0(n3476), .Y(n2139) );
NOR2X4TS U2988 ( .A(n10084), .B(n8234), .Y(n8236) );
ADDFHX2TS U2989 ( .A(n4735), .B(n4733), .CI(n4734), .CO(n4774), .S(n4710) );
BUFX4TS U2990 ( .A(n6413), .Y(n2583) );
BUFX6TS U2991 ( .A(n9792), .Y(n1318) );
XOR2X4TS U2992 ( .A(n3881), .B(n843), .Y(n4113) );
NOR2X6TS U2993 ( .A(n3996), .B(n825), .Y(n3997) );
BUFX16TS U2994 ( .A(n6465), .Y(n2647) );
NOR2X6TS U2995 ( .A(n2185), .B(n5309), .Y(n2696) );
XOR2X4TS U2996 ( .A(n8086), .B(n1946), .Y(n6474) );
NAND2X8TS U2997 ( .A(DP_OP_168J26_122_4811_n8197), .B(
DP_OP_168J26_122_4811_n8223), .Y(n3391) );
OR2X4TS U2998 ( .A(n3801), .B(n7993), .Y(n845) );
NAND2X8TS U2999 ( .A(n844), .B(n845), .Y(n3834) );
BUFX12TS U3000 ( .A(n11485), .Y(n1029) );
NAND2X6TS U3001 ( .A(n10000), .B(n9999), .Y(n10003) );
NAND2BX2TS U3002 ( .AN(n6744), .B(n3055), .Y(n3053) );
XOR2X4TS U3003 ( .A(n2731), .B(n5205), .Y(n2208) );
NOR2X4TS U3004 ( .A(n848), .B(n3372), .Y(n3374) );
NOR2X6TS U3005 ( .A(DP_OP_168J26_122_4811_n3486), .B(
DP_OP_168J26_122_4811_n3475), .Y(n3373) );
XOR2X2TS U3006 ( .A(n2140), .B(n3478), .Y(n3517) );
CLKBUFX3TS U3007 ( .A(n8928), .Y(n2342) );
NAND2X2TS U3008 ( .A(n8940), .B(n8941), .Y(n8411) );
INVX8TS U3009 ( .A(n9826), .Y(n896) );
INVX6TS U3010 ( .A(n6148), .Y(n2080) );
XOR2X4TS U3011 ( .A(n1046), .B(n910), .Y(n849) );
NAND2X8TS U3012 ( .A(n852), .B(n853), .Y(n3854) );
INVX4TS U3013 ( .A(n1890), .Y(n897) );
BUFX8TS U3014 ( .A(DP_OP_168J26_122_4811_n8187), .Y(n5666) );
XNOR2X4TS U3015 ( .A(n932), .B(n854), .Y(n4021) );
ADDFHX4TS U3016 ( .A(n3954), .B(n3955), .CI(n3956), .CO(n4624), .S(n3983) );
ADDFHX4TS U3017 ( .A(n3743), .B(n3741), .CI(n3742), .CO(n3956), .S(n3747) );
OAI22X4TS U3018 ( .A0(n1820), .A1(n3671), .B0(n1900), .B1(n3668), .Y(n3743)
);
XNOR2X4TS U3019 ( .A(n1811), .B(n1253), .Y(n6094) );
XNOR2X4TS U3020 ( .A(n855), .B(n3864), .Y(n1681) );
XOR2X4TS U3021 ( .A(n3866), .B(n3865), .Y(n855) );
ADDFHX4TS U3022 ( .A(n9001), .B(n9000), .CI(n8999), .CO(n9107), .S(n9099) );
XOR2X4TS U3023 ( .A(DP_OP_168J26_122_4811_n8517), .B(
DP_OP_168J26_122_4811_n8544), .Y(n856) );
XNOR2X4TS U3024 ( .A(n858), .B(DP_OP_168J26_122_4811_n8518), .Y(n3616) );
NOR2X6TS U3025 ( .A(n7964), .B(n7974), .Y(n1487) );
BUFX16TS U3026 ( .A(DP_OP_168J26_122_4811_n8460), .Y(n2464) );
XNOR2X4TS U3027 ( .A(n3834), .B(n3833), .Y(n919) );
NAND2X2TS U3028 ( .A(n4014), .B(n4015), .Y(n2599) );
ADDFHX4TS U3029 ( .A(n8273), .B(n950), .CI(n8272), .CO(n1736), .S(n1759) );
OAI22X4TS U3030 ( .A0(n2399), .A1(n11777), .B0(n1883), .B1(n951), .Y(n7196)
);
INVX8TS U3031 ( .A(DP_OP_168J26_122_4811_n8473), .Y(n859) );
INVX8TS U3032 ( .A(DP_OP_168J26_122_4811_n8473), .Y(n3297) );
OAI22X4TS U3033 ( .A0(DP_OP_168J26_122_4811_n6594), .A1(n11782), .B0(
DP_OP_168J26_122_4811_n6608), .B1(n800), .Y(n4604) );
INVX12TS U3034 ( .A(n860), .Y(n861) );
NOR2BX4TS U3035 ( .AN(n2448), .B(n782), .Y(n5725) );
INVX8TS U3036 ( .A(n876), .Y(n5420) );
XOR2X4TS U3037 ( .A(n862), .B(n849), .Y(n5432) );
XOR2X4TS U3038 ( .A(n5388), .B(n5389), .Y(n862) );
INVX8TS U3039 ( .A(n863), .Y(n864) );
XNOR2X4TS U3040 ( .A(n2147), .B(n1644), .Y(n8024) );
NAND2X6TS U3041 ( .A(n2258), .B(n4253), .Y(n2773) );
NAND3X4TS U3042 ( .A(n1496), .B(n2246), .C(n3381), .Y(n1495) );
OAI22X4TS U3043 ( .A0(n8588), .A1(n8643), .B0(n4261), .B1(n8641), .Y(n9836)
);
NOR2X6TS U3044 ( .A(n7776), .B(n7764), .Y(n7621) );
INVX2TS U3045 ( .A(n7764), .Y(n7773) );
ADDFHX4TS U3046 ( .A(n4666), .B(n4665), .CI(n4664), .CO(n8125), .S(n4661) );
XNOR2X4TS U3047 ( .A(n1289), .B(n7369), .Y(n4669) );
INVX4TS U3048 ( .A(n8926), .Y(n867) );
INVX8TS U3049 ( .A(n8109), .Y(n8926) );
INVX6TS U3050 ( .A(n868), .Y(n869) );
ADDFHX4TS U3051 ( .A(DP_OP_168J26_122_4811_n5214), .B(n7021), .CI(n7020),
.CO(n7120), .S(n7029) );
NOR2X2TS U3052 ( .A(n2537), .B(n8231), .Y(n10094) );
XOR2X4TS U3053 ( .A(n5365), .B(n871), .Y(n875) );
OAI21X2TS U3054 ( .A0(n922), .A1(n1238), .B0(n1837), .Y(n3359) );
NAND2X8TS U3055 ( .A(n873), .B(n874), .Y(n4199) );
XOR2X4TS U3056 ( .A(n875), .B(n5363), .Y(n2856) );
INVX12TS U3057 ( .A(n5736), .Y(n8251) );
XNOR2X4TS U3058 ( .A(n912), .B(n1231), .Y(n876) );
NAND2X6TS U3059 ( .A(n3936), .B(n11755), .Y(n2217) );
BUFX20TS U3060 ( .A(n4358), .Y(n8513) );
XNOR2X4TS U3061 ( .A(n2044), .B(n8513), .Y(n5781) );
NAND2X6TS U3062 ( .A(n8309), .B(n8310), .Y(n2291) );
OAI22X2TS U3063 ( .A0(n2071), .A1(n4833), .B0(n4828), .B1(n1958), .Y(n4847)
);
OAI22X2TS U3064 ( .A0(n2071), .A1(n4907), .B0(n4834), .B1(n1901), .Y(n4890)
);
CLKBUFX2TS U3065 ( .A(n10731), .Y(n2353) );
OAI22X4TS U3066 ( .A0(n2434), .A1(DP_OP_168J26_122_4811_n6171), .B0(n2550),
.B1(n945), .Y(n7021) );
INVX8TS U3067 ( .A(n2047), .Y(n2048) );
OAI22X2TS U3068 ( .A0(n5306), .A1(n1529), .B0(n2048), .B1(n1518), .Y(n7055)
);
ADDFHX4TS U3069 ( .A(n7143), .B(n7141), .CI(n7142), .CO(n7220), .S(n7145) );
ADDFHX4TS U3070 ( .A(n8460), .B(n8461), .CI(n8459), .CO(n8652), .S(n8457) );
OAI22X4TS U3071 ( .A0(n2128), .A1(n1987), .B0(n1993), .B1(n1823), .Y(n8461)
);
NOR2X2TS U3072 ( .A(n2216), .B(n3945), .Y(n2215) );
NAND2X8TS U3073 ( .A(n1463), .B(n1462), .Y(n1461) );
XOR2X4TS U3074 ( .A(n3618), .B(n1218), .Y(n3619) );
BUFX20TS U3075 ( .A(n8948), .Y(n2053) );
OAI22X4TS U3076 ( .A0(n5719), .A1(n6154), .B0(n3320), .B1(n5620), .Y(n5709)
);
NAND2X6TS U3077 ( .A(n3220), .B(n3219), .Y(n9831) );
BUFX20TS U3078 ( .A(DP_OP_168J26_122_4811_n6562), .Y(n2566) );
NAND2X4TS U3079 ( .A(n11776), .B(n11734), .Y(DP_OP_168J26_122_4811_n285) );
BUFX12TS U3080 ( .A(n8627), .Y(n1059) );
XNOR2X2TS U3081 ( .A(n886), .B(n2453), .Y(n4621) );
XNOR2X2TS U3082 ( .A(n8892), .B(n8508), .Y(n8519) );
XNOR2X2TS U3083 ( .A(n8892), .B(n6529), .Y(n6565) );
XNOR2X2TS U3084 ( .A(n8892), .B(n2031), .Y(n6478) );
XNOR2X2TS U3085 ( .A(n8892), .B(n1966), .Y(n4514) );
XNOR2X2TS U3086 ( .A(n8892), .B(n1926), .Y(n4260) );
INVX2TS U3087 ( .A(n8892), .Y(n977) );
OAI21X2TS U3088 ( .A0(n3279), .A1(n6748), .B0(n3050), .Y(n3280) );
XOR2X4TS U3089 ( .A(n3636), .B(n3635), .Y(n888) );
BUFX12TS U3090 ( .A(n7523), .Y(n889) );
NAND2X8TS U3091 ( .A(n9486), .B(n9485), .Y(n10027) );
INVX16TS U3092 ( .A(n5283), .Y(n2068) );
NAND2X6TS U3093 ( .A(n3170), .B(n3169), .Y(n4420) );
XOR2X4TS U3094 ( .A(n3758), .B(n892), .Y(n891) );
INVX12TS U3095 ( .A(n891), .Y(n3640) );
XNOR2X2TS U3096 ( .A(n1931), .B(n1808), .Y(n6071) );
OR2X4TS U3097 ( .A(n1924), .B(n5008), .Y(n894) );
NAND2X2TS U3098 ( .A(n893), .B(n894), .Y(n5050) );
NAND2BX2TS U3099 ( .AN(n2591), .B(n2590), .Y(n5008) );
ADDFHX4TS U3100 ( .A(n4121), .B(n4119), .CI(n4120), .CO(n4149), .S(n4129) );
ADDFHX4TS U3101 ( .A(n5100), .B(n5101), .CI(n5099), .CO(n5097), .S(n5119) );
NAND2X4TS U3102 ( .A(n11761), .B(n9998), .Y(DP_OP_168J26_122_4811_n105) );
OR3X8TS U3103 ( .A(n11756), .B(n895), .C(n7036), .Y(n2183) );
XOR2X4TS U3104 ( .A(n896), .B(n1348), .Y(n1249) );
INVX12TS U3105 ( .A(n7036), .Y(n1817) );
NAND2X8TS U3106 ( .A(n1517), .B(DP_OP_168J26_122_4811_n6620), .Y(n5328) );
INVX12TS U3107 ( .A(n1688), .Y(n1689) );
OR2X6TS U3108 ( .A(n9983), .B(n9984), .Y(n11778) );
OAI22X4TS U3109 ( .A0(n2089), .A1(n5554), .B0(n5683), .B1(n6142), .Y(n5642)
);
NAND2X4TS U3110 ( .A(n5063), .B(n5061), .Y(n1743) );
OR2X8TS U3111 ( .A(n2030), .B(n3400), .Y(n934) );
XOR2X4TS U3112 ( .A(n1581), .B(n1904), .Y(n4088) );
OAI2BB1X4TS U3113 ( .A0N(n2888), .A1N(n2721), .B0(n3044), .Y(n2843) );
ADDFHX4TS U3114 ( .A(n8675), .B(n8674), .CI(n8673), .CO(n9855), .S(n8594) );
OAI22X4TS U3115 ( .A0(n3670), .A1(n1934), .B0(n3729), .B1(n1991), .Y(n2220)
);
XNOR2X2TS U3116 ( .A(n2341), .B(n2677), .Y(n5566) );
ADDFHX4TS U3117 ( .A(n5576), .B(n5575), .CI(n5574), .CO(n5641), .S(n5599) );
BUFX12TS U3118 ( .A(n3814), .Y(n8022) );
ADDFHX2TS U3119 ( .A(n3927), .B(n3926), .CI(n3925), .CO(n4400), .S(n4056) );
OAI22X2TS U3120 ( .A0(n4004), .A1(n9755), .B0(n4293), .B1(n8908), .Y(n3926)
);
OAI22X4TS U3121 ( .A0(n6154), .A1(DP_OP_168J26_122_4811_n8034), .B0(n5572),
.B1(n3535), .Y(n3911) );
OAI22X2TS U3122 ( .A0(n7997), .A1(n7996), .B0(n1950), .B1(n7995), .Y(n8046)
);
NAND2X2TS U3123 ( .A(n5365), .B(n5364), .Y(n1052) );
ADDFHX4TS U3124 ( .A(n5004), .B(n5003), .CI(n5002), .CO(n4996), .S(n5074) );
BUFX12TS U3125 ( .A(n2996), .Y(n2569) );
ADDFHX2TS U3126 ( .A(n3988), .B(n3987), .CI(n3986), .CO(n9933), .S(n3989) );
NOR2X2TS U3127 ( .A(n8775), .B(n8776), .Y(n1797) );
XOR2X4TS U3128 ( .A(n11499), .B(n916), .Y(n5751) );
OAI21X2TS U3129 ( .A0(n8136), .A1(n837), .B0(n8135), .Y(n2939) );
BUFX16TS U3130 ( .A(n865), .Y(n7273) );
BUFX12TS U3131 ( .A(n5475), .Y(n2488) );
INVX4TS U3132 ( .A(n5475), .Y(n3933) );
BUFX12TS U3133 ( .A(n10088), .Y(n2807) );
OR2X4TS U3134 ( .A(n5720), .B(n2073), .Y(n902) );
INVX8TS U3135 ( .A(n1398), .Y(n1897) );
BUFX4TS U3136 ( .A(n3866), .Y(n906) );
AND2X6TS U3137 ( .A(n3755), .B(n3382), .Y(n3183) );
XNOR2X4TS U3138 ( .A(n11527), .B(n904), .Y(n4164) );
OAI22X2TS U3139 ( .A0(n1083), .A1(n6059), .B0(n2080), .B1(n6149), .Y(n6188)
);
BUFX20TS U3140 ( .A(n3394), .Y(n7473) );
OAI22X4TS U3141 ( .A0(n6003), .A1(n2666), .B0(n2082), .B1(n1223), .Y(n4461)
);
OAI22X4TS U3142 ( .A0(n5570), .A1(n2038), .B0(n6174), .B1(n5564), .Y(n5575)
);
OAI22X4TS U3143 ( .A0(n1853), .A1(n954), .B0(n2063), .B1(n11674), .Y(n4433)
);
BUFX16TS U3144 ( .A(n9479), .Y(n1492) );
OAI22X2TS U3145 ( .A0(n8613), .A1(n6919), .B0(n6921), .B1(n8543), .Y(n8544)
);
XNOR2X2TS U3146 ( .A(n5270), .B(n878), .Y(n4883) );
INVX4TS U3147 ( .A(n4311), .Y(n907) );
CLKINVX12TS U3148 ( .A(DP_OP_168J26_122_4811_n6559), .Y(n1839) );
OR2X8TS U3149 ( .A(n6154), .B(n5883), .Y(n908) );
OR2X4TS U3150 ( .A(n9997), .B(n9996), .Y(n11763) );
NAND2X6TS U3151 ( .A(n9997), .B(n9996), .Y(DP_OP_168J26_122_4811_n553) );
BUFX8TS U3152 ( .A(n6383), .Y(n2540) );
XNOR2X4TS U3153 ( .A(n8894), .B(n1928), .Y(n5527) );
OAI22X4TS U3154 ( .A0(n5527), .A1(n1982), .B0(n5634), .B1(n1944), .Y(n5521)
);
XOR2X2TS U3155 ( .A(n859), .B(n5174), .Y(n4966) );
NAND2X2TS U3156 ( .A(n2475), .B(n2342), .Y(n7573) );
OAI22X4TS U3157 ( .A0(n8578), .A1(n8933), .B0(n4373), .B1(n8577), .Y(n8566)
);
CLKBUFX2TS U3158 ( .A(n8923), .Y(n2475) );
XNOR2X4TS U3159 ( .A(n911), .B(n4282), .Y(n2255) );
XOR2X4TS U3160 ( .A(n4283), .B(n4281), .Y(n911) );
ADDFHX4TS U3161 ( .A(n4866), .B(n4867), .CI(n4868), .CO(n5136), .S(n4873) );
XOR2X4TS U3162 ( .A(n5374), .B(n5373), .Y(n912) );
XOR2X2TS U3163 ( .A(n1703), .B(DP_OP_168J26_122_4811_n8516), .Y(n2216) );
NAND2XLTS U3164 ( .A(n7691), .B(n1157), .Y(n7692) );
AOI21X2TS U3165 ( .A0(n7616), .A1(n7689), .B0(n7615), .Y(n7617) );
BUFX20TS U3166 ( .A(n2200), .Y(n1609) );
ADDFHX2TS U3167 ( .A(n7998), .B(n7991), .CI(n7990), .CO(n8003), .S(n8053) );
OR2X8TS U3168 ( .A(n2971), .B(n3183), .Y(n913) );
OR2X8TS U3169 ( .A(n2971), .B(n3183), .Y(n914) );
OAI22X2TS U3170 ( .A0(DP_OP_168J26_122_4811_n6594), .A1(n11509), .B0(
DP_OP_168J26_122_4811_n6608), .B1(n11783), .Y(n4018) );
OAI22X4TS U3171 ( .A0(DP_OP_168J26_122_4811_n6594), .A1(n956), .B0(n765),
.B1(n11765), .Y(n7998) );
NOR2X8TS U3172 ( .A(n2804), .B(n2803), .Y(n3054) );
XOR2X4TS U3173 ( .A(DP_OP_168J26_122_4811_n8545), .B(n915), .Y(n1097) );
ADDFHX4TS U3174 ( .A(n8158), .B(n8156), .CI(n8157), .CO(n8167), .S(n8153) );
NOR2X4TS U3175 ( .A(n9565), .B(n10094), .Y(n8755) );
NAND2X6TS U3176 ( .A(n9883), .B(n1273), .Y(n2748) );
XNOR2X4TS U3177 ( .A(n1620), .B(n918), .Y(n2213) );
OAI22X4TS U3178 ( .A0(n2110), .A1(n5012), .B0(n5058), .B1(n4941), .Y(n5101)
);
INVX16TS U3179 ( .A(n3758), .Y(n2902) );
XNOR2X4TS U3180 ( .A(n919), .B(n3835), .Y(n4035) );
NAND2X2TS U3181 ( .A(n8216), .B(n2491), .Y(n8385) );
XNOR2X4TS U3182 ( .A(n943), .B(n921), .Y(n5446) );
INVX16TS U3183 ( .A(n1888), .Y(n1889) );
NAND2X4TS U3184 ( .A(n3302), .B(n3301), .Y(n6888) );
NAND2X8TS U3185 ( .A(n1539), .B(n1538), .Y(n1537) );
OA22X2TS U3186 ( .A0(n8013), .A1(n1590), .B0(n7274), .B1(n1980), .Y(n923) );
OAI22X2TS U3187 ( .A0(n8015), .A1(n8014), .B0(n8013), .B1(n8012), .Y(n8048)
);
OAI21X4TS U3188 ( .A0(n6264), .A1(n6263), .B0(n6262), .Y(n2155) );
NAND2X2TS U3189 ( .A(n2557), .B(n5484), .Y(n8183) );
NOR2X2TS U3190 ( .A(n3758), .B(n3381), .Y(n1491) );
OAI22X4TS U3191 ( .A0(n3469), .A1(n1815), .B0(n7491), .B1(n2908), .Y(n3475)
);
OAI22X4TS U3192 ( .A0(n4365), .A1(n2019), .B0(n1894), .B1(n4373), .Y(n9779)
);
INVX8TS U3193 ( .A(n6953), .Y(n3205) );
INVX4TS U3194 ( .A(n6611), .Y(n6660) );
XOR2X4TS U3195 ( .A(n941), .B(n924), .Y(n3091) );
ADDFHX4TS U3196 ( .A(n8634), .B(n8633), .CI(n8632), .CO(n9797), .S(n8676) );
XOR2X4TS U3197 ( .A(n926), .B(n6156), .Y(n3498) );
INVX16TS U3198 ( .A(n1760), .Y(n11009) );
OAI21X2TS U3199 ( .A0(n1824), .A1(n7604), .B0(n7603), .Y(n7608) );
OAI21X2TS U3200 ( .A0(n1824), .A1(n9578), .B0(n9577), .Y(n9583) );
OAI21X2TS U3201 ( .A0(n1824), .A1(n7541), .B0(n7540), .Y(n7555) );
OAI21X2TS U3202 ( .A0(n1824), .A1(n10110), .B0(n10111), .Y(n9060) );
OAI21X2TS U3203 ( .A0(n1824), .A1(n8410), .B0(n8409), .Y(n8414) );
INVX8TS U3204 ( .A(n927), .Y(n928) );
OR2X8TS U3205 ( .A(n963), .B(n7477), .Y(n930) );
NAND2X8TS U3206 ( .A(n929), .B(n930), .Y(n5760) );
NAND2X2TS U3207 ( .A(n1238), .B(n922), .Y(n3309) );
NAND2X2TS U3208 ( .A(n9844), .B(n9845), .Y(n1551) );
ADDFHX4TS U3209 ( .A(n4503), .B(n4501), .CI(n4502), .CO(n4521), .S(n4498) );
NAND2X6TS U3210 ( .A(n1618), .B(n1619), .Y(n2641) );
XNOR2X4TS U3211 ( .A(n5276), .B(n7272), .Y(n5212) );
XOR2X4TS U3212 ( .A(n9811), .B(n2534), .Y(n1673) );
BUFX20TS U3213 ( .A(n5328), .Y(n2071) );
OAI21X2TS U3214 ( .A0(n6750), .A1(n6751), .B0(n3303), .Y(n3302) );
XNOR2X4TS U3215 ( .A(n5251), .B(n7369), .Y(n3685) );
OAI22X4TS U3216 ( .A0(n8558), .A1(n1983), .B0(n8575), .B1(n1944), .Y(n8674)
);
BUFX16TS U3217 ( .A(n6101), .Y(n2450) );
INVX8TS U3218 ( .A(n9816), .Y(n9780) );
ADDFHX4TS U3219 ( .A(n3410), .B(n3409), .CI(n3408), .CO(n3425), .S(n3496) );
XOR2X4TS U3220 ( .A(n2606), .B(n8204), .Y(n8195) );
OR2X4TS U3221 ( .A(n5566), .B(n3307), .Y(n937) );
INVX8TS U3222 ( .A(n6287), .Y(n5788) );
ADDFHX4TS U3223 ( .A(n3732), .B(n3731), .CI(n3730), .CO(n3973), .S(n3734) );
OAI22X4TS U3224 ( .A0(n3666), .A1(n2066), .B0(n1880), .B1(n3982), .Y(n3972)
);
XNOR2X4TS U3225 ( .A(n1289), .B(n7272), .Y(n3982) );
NAND2X6TS U3226 ( .A(n1247), .B(n1248), .Y(n4171) );
ADDFHX4TS U3227 ( .A(n8245), .B(n8246), .CI(n8247), .CO(n8277), .S(n8280) );
ADDFHX2TS U3228 ( .A(n7211), .B(n7210), .CI(n7209), .CO(n7322), .S(n7203) );
AOI21X1TS U3229 ( .A0(n3756), .A1(n3759), .B0(n11775), .Y(n3571) );
INVX4TS U3230 ( .A(n6421), .Y(n6499) );
INVX12TS U3231 ( .A(DP_OP_168J26_122_4811_n8221), .Y(n6148) );
BUFX6TS U3232 ( .A(n6275), .Y(n2161) );
BUFX12TS U3233 ( .A(n4061), .Y(n8581) );
BUFX12TS U3234 ( .A(n4061), .Y(n8945) );
BUFX20TS U3235 ( .A(n1086), .Y(n1084) );
OAI22X4TS U3236 ( .A0(n7017), .A1(n2411), .B0(n1950), .B1(n7084), .Y(n7094)
);
XOR2X4TS U3237 ( .A(n4237), .B(n4238), .Y(n941) );
OAI22X4TS U3238 ( .A0(n4025), .A1(n1950), .B0(n7997), .B1(n11683), .Y(n5369)
);
AOI21X2TS U3239 ( .A0(n4075), .A1(n3940), .B0(n3939), .Y(n3941) );
OAI22X4TS U3240 ( .A0(n2027), .A1(n5308), .B0(n1989), .B1(n5307), .Y(n5390)
);
XOR2X4TS U3241 ( .A(n5421), .B(n5420), .Y(n943) );
OAI22X4TS U3242 ( .A0(n8572), .A1(n2113), .B0(n8571), .B1(n1960), .Y(n9799)
);
OR2X4TS U3243 ( .A(n8216), .B(n2491), .Y(n8386) );
CLKINVX12TS U3244 ( .A(n5309), .Y(n2026) );
ADDFHX4TS U3245 ( .A(n5511), .B(n5510), .CI(n5509), .CO(n8495), .S(n5917) );
OAI22X2TS U3246 ( .A0(n5831), .A1(n2108), .B0(n5494), .B1(n1962), .Y(n5511)
);
CLKINVX12TS U3247 ( .A(n11475), .Y(n3877) );
INVX4TS U3248 ( .A(n1772), .Y(n947) );
INVX6TS U3249 ( .A(n5448), .Y(n1772) );
BUFX6TS U3250 ( .A(n6294), .Y(n948) );
INVX16TS U3251 ( .A(DP_OP_168J26_122_4811_n5154), .Y(n3652) );
INVX16TS U3252 ( .A(n3652), .Y(n2091) );
OAI2BB1X4TS U3253 ( .A0N(n6261), .A1N(n6260), .B0(n3105), .Y(n6253) );
OAI21X4TS U3254 ( .A0(n6261), .A1(n6260), .B0(n6259), .Y(n3105) );
ADDFHX4TS U3255 ( .A(n4470), .B(n4471), .CI(n4469), .CO(n4466), .S(n4497) );
BUFX3TS U3256 ( .A(n7429), .Y(n2458) );
INVX16TS U3257 ( .A(n1770), .Y(n6529) );
ADDFHX2TS U3258 ( .A(n6508), .B(n6507), .CI(n6506), .S(n950) );
ADDFHX2TS U3259 ( .A(n5993), .B(n5994), .CI(n5992), .CO(n8249), .S(n6506) );
XOR2X2TS U3260 ( .A(n952), .B(DP_OP_168J26_122_4811_n8501), .Y(n4136) );
XNOR2X4TS U3261 ( .A(n9809), .B(n9810), .Y(n1651) );
INVX16TS U3262 ( .A(n951), .Y(n952) );
NAND2X8TS U3263 ( .A(n2305), .B(n2304), .Y(n2885) );
XOR2X4TS U3264 ( .A(n8627), .B(n1022), .Y(n4344) );
XNOR2X4TS U3265 ( .A(n1565), .B(n2265), .Y(n6924) );
NAND2X2TS U3266 ( .A(n4055), .B(n4054), .Y(n2737) );
XNOR2X4TS U3267 ( .A(n859), .B(n1261), .Y(n5272) );
NAND2X8TS U3268 ( .A(n9635), .B(n9636), .Y(n2582) );
OAI22X2TS U3269 ( .A0(n2096), .A1(n5053), .B0(n4971), .B1(n11758), .Y(n5075)
);
INVX6TS U3270 ( .A(n5735), .Y(n8252) );
INVX4TS U3271 ( .A(n5473), .Y(n2742) );
OAI22X2TS U3272 ( .A0(n932), .A1(n4984), .B0(n4983), .B1(n1991), .Y(n5014)
);
INVX4TS U3273 ( .A(n4055), .Y(n2739) );
CLKINVX12TS U3274 ( .A(n5721), .Y(n1480) );
OAI22X2TS U3275 ( .A0(n4258), .A1(n5488), .B0(n4369), .B1(n8931), .Y(n4212)
);
ADDFHX4TS U3276 ( .A(n4762), .B(n4761), .CI(n4760), .CO(n9936), .S(n9930) );
OAI22X4TS U3277 ( .A0(n6174), .A1(n6013), .B0(n11757), .B1(n6016), .Y(n6020)
);
NAND2BX2TS U3278 ( .AN(n6633), .B(n8513), .Y(n5780) );
XOR2X4TS U3279 ( .A(n5721), .B(n917), .Y(n4128) );
NOR2X8TS U3280 ( .A(n2546), .B(n1505), .Y(n1254) );
INVX8TS U3281 ( .A(n1659), .Y(n954) );
INVX8TS U3282 ( .A(n6376), .Y(n9800) );
NOR2X4TS U3283 ( .A(n4633), .B(n1907), .Y(n4642) );
NAND2X6TS U3284 ( .A(n3385), .B(n3384), .Y(n3788) );
OAI22X4TS U3285 ( .A0(n6893), .A1(n1933), .B0(n6766), .B1(n1985), .Y(n6889)
);
XOR2X4TS U3286 ( .A(n1289), .B(n11736), .Y(n4882) );
NOR2X4TS U3287 ( .A(n2535), .B(n6378), .Y(n7974) );
OAI22X2TS U3288 ( .A0(n5631), .A1(n2067), .B0(n8462), .B1(n1940), .Y(n8448)
);
ADDFHX2TS U3289 ( .A(n9775), .B(n9776), .CI(n9774), .CO(n4382), .S(n9818) );
OAI2BB1X4TS U3290 ( .A0N(n5421), .A1N(n5420), .B0(n2901), .Y(n5459) );
INVX12TS U3291 ( .A(n1849), .Y(n1850) );
INVX16TS U3292 ( .A(DP_OP_168J26_122_4811_n8480), .Y(n3078) );
OAI22X2TS U3293 ( .A0(n2111), .A1(n4918), .B0(n5058), .B1(n4888), .Y(n4932)
);
XNOR2X4TS U3294 ( .A(n2634), .B(n5251), .Y(n4888) );
XOR2X4TS U3295 ( .A(n960), .B(n961), .Y(n2818) );
XNOR2X4TS U3296 ( .A(n1786), .B(n5454), .Y(n960) );
XOR2X4TS U3297 ( .A(n1785), .B(n1676), .Y(n961) );
BUFX8TS U3298 ( .A(n1786), .Y(n1531) );
XNOR2X4TS U3299 ( .A(n6055), .B(n7449), .Y(n5604) );
OAI22X4TS U3300 ( .A0(n2399), .A1(n2464), .B0(n1883), .B1(n7449), .Y(n7487)
);
BUFX20TS U3301 ( .A(DP_OP_168J26_122_4811_n8461), .Y(n7449) );
XNOR2X4TS U3302 ( .A(n2078), .B(n820), .Y(n3663) );
BUFX20TS U3303 ( .A(DP_OP_168J26_122_4811_n6643), .Y(n2078) );
ADDFHX4TS U3304 ( .A(n7026), .B(n7027), .CI(n7025), .CO(n7128), .S(n7067) );
OR2X8TS U3305 ( .A(n5319), .B(n962), .Y(n1544) );
BUFX4TS U3306 ( .A(n9809), .Y(n2525) );
XNOR2X4TS U3307 ( .A(n1523), .B(n1283), .Y(n5363) );
XNOR2X4TS U3308 ( .A(n2780), .B(n1480), .Y(n963) );
OAI22X4TS U3309 ( .A0(n8022), .A1(n4556), .B0(n1988), .B1(n4591), .Y(n4605)
);
NOR2X8TS U3310 ( .A(n4394), .B(n4395), .Y(n2832) );
OAI22X4TS U3311 ( .A0(n5302), .A1(n745), .B0(n1924), .B1(n4043), .Y(n4244)
);
INVX6TS U3312 ( .A(n5984), .Y(n2640) );
OAI22X2TS U3313 ( .A0(n8512), .A1(n2259), .B0(n8580), .B1(n8581), .Y(n8661)
);
NAND2X8TS U3314 ( .A(DP_OP_168J26_122_4811_n1422), .B(
DP_OP_168J26_122_4811_n1455), .Y(DP_OP_168J26_122_4811_n525) );
AOI21X2TS U3315 ( .A0(n9654), .A1(n9499), .B0(n9498), .Y(n9500) );
AOI21X2TS U3316 ( .A0(n9654), .A1(n9639), .B0(n9638), .Y(n9640) );
AOI21X2TS U3317 ( .A0(n9654), .A1(n9508), .B0(n2340), .Y(n9509) );
AOI21X2TS U3318 ( .A0(n9654), .A1(n8343), .B0(n8342), .Y(n8344) );
OAI21X2TS U3319 ( .A0(n1824), .A1(n8424), .B0(n8423), .Y(n2277) );
OAI21X2TS U3320 ( .A0(n1825), .A1(n9641), .B0(n9640), .Y(n9646) );
OR2X8TS U3321 ( .A(DP_OP_168J26_122_4811_n8446), .B(
DP_OP_168J26_122_4811_n8471), .Y(n4093) );
BUFX12TS U3322 ( .A(n6633), .Y(n6849) );
XOR2X2TS U3323 ( .A(n6633), .B(n1971), .Y(n1378) );
OAI22X4TS U3324 ( .A0(n4632), .A1(n1982), .B0(n1945), .B1(n6635), .Y(n4511)
);
ADDFHX4TS U3325 ( .A(n5769), .B(n5768), .CI(n5767), .CO(n5763), .S(n5946) );
XOR2X4TS U3326 ( .A(n11584), .B(n790), .Y(n5338) );
XOR2X4TS U3327 ( .A(n1324), .B(n790), .Y(n4832) );
OAI22X2TS U3328 ( .A0(n5743), .A1(n6919), .B0(n5830), .B1(n6921), .Y(n5821)
);
XNOR2X2TS U3329 ( .A(n7275), .B(n955), .Y(n3660) );
BUFX12TS U3330 ( .A(Op_MY[47]), .Y(n2503) );
NAND2X6TS U3331 ( .A(n2295), .B(n2827), .Y(n8711) );
INVX16TS U3332 ( .A(n964), .Y(n1031) );
OAI22X4TS U3333 ( .A0(n5864), .A1(n7492), .B0(n3307), .B1(n5863), .Y(n6300)
);
XOR2X4TS U3334 ( .A(n945), .B(n965), .Y(n7271) );
XOR2X1TS U3335 ( .A(n8627), .B(n1970), .Y(n7380) );
XNOR2X2TS U3336 ( .A(n8627), .B(n2058), .Y(n8978) );
XNOR2X2TS U3337 ( .A(n8627), .B(n1929), .Y(n3768) );
XOR2X2TS U3338 ( .A(n9959), .B(n9960), .Y(n2595) );
INVX12TS U3339 ( .A(n1092), .Y(n8539) );
XNOR2X4TS U3340 ( .A(n5254), .B(n5235), .Y(n3821) );
OAI22X2TS U3341 ( .A0(n5492), .A1(n8581), .B0(n5545), .B1(n967), .Y(n5901)
);
OAI22X2TS U3342 ( .A0(n8512), .A1(n8581), .B0(n8445), .B1(n967), .Y(n8560)
);
OAI22X4TS U3343 ( .A0(n5545), .A1(n8581), .B0(n5544), .B1(n967), .Y(n5827)
);
OAI22X2TS U3344 ( .A0(n5492), .A1(n967), .B0(n8445), .B1(n8581), .Y(n8473)
);
INVX2TS U3345 ( .A(n969), .Y(n970) );
INVX6TS U3346 ( .A(n6148), .Y(n974) );
CLKINVX12TS U3347 ( .A(n977), .Y(n978) );
INVX2TS U3348 ( .A(n978), .Y(n8893) );
CLKINVX12TS U3349 ( .A(DP_OP_168J26_122_4811_n6615), .Y(n2382) );
INVX6TS U3350 ( .A(n2382), .Y(n979) );
OAI22X4TS U3351 ( .A0(n975), .A1(n5275), .B0(n979), .B1(n5317), .Y(n5315) );
INVX2TS U3352 ( .A(n11942), .Y(n982) );
OR2X6TS U3353 ( .A(DP_OP_168J26_122_4811_n3560), .B(
DP_OP_168J26_122_4811_n3572), .Y(n996) );
INVX2TS U3354 ( .A(n4233), .Y(n1535) );
OAI21X2TS U3355 ( .A0(n7684), .A1(n7674), .B0(n7675), .Y(n2188) );
NOR2X4TS U3356 ( .A(n1369), .B(n2891), .Y(n2890) );
NAND2X2TS U3357 ( .A(n1817), .B(DP_OP_168J26_122_4811_n8487), .Y(n2633) );
NAND2X2TS U3358 ( .A(n2176), .B(DP_OP_168J26_122_4811_n8518), .Y(n1093) );
NAND2X1TS U3359 ( .A(n11733), .B(DP_OP_168J26_122_4811_n3542), .Y(n3356) );
NAND2X1TS U3360 ( .A(DP_OP_168J26_122_4811_n8529), .B(
DP_OP_168J26_122_4811_n8502), .Y(n3384) );
INVX2TS U3361 ( .A(n8385), .Y(n3182) );
NOR2BX2TS U3362 ( .AN(n1902), .B(n8020), .Y(n4940) );
NAND2X1TS U3363 ( .A(n3833), .B(n3834), .Y(n1767) );
OR2X4TS U3364 ( .A(n3568), .B(n3567), .Y(n3287) );
NAND2X1TS U3365 ( .A(n2969), .B(n1344), .Y(n3607) );
AOI21X2TS U3366 ( .A0(n8377), .A1(n8386), .B0(n3182), .Y(n8217) );
OAI22X2TS U3367 ( .A0(n2107), .A1(n4993), .B0(n1865), .B1(n4992), .Y(n5023)
);
NOR2X2TS U3368 ( .A(n7640), .B(n7644), .Y(n7646) );
BUFX8TS U3369 ( .A(n3647), .Y(n2088) );
XNOR2X2TS U3370 ( .A(n1838), .B(n1645), .Y(n7016) );
NAND2BX2TS U3371 ( .AN(n6808), .B(n3057), .Y(n3056) );
INVX2TS U3372 ( .A(n4054), .Y(n2740) );
XNOR2X2TS U3373 ( .A(n2070), .B(n1228), .Y(n6162) );
NAND2X2TS U3374 ( .A(n1003), .B(n1491), .Y(n1493) );
NOR2BX2TS U3375 ( .AN(n6849), .B(n8516), .Y(n6538) );
NOR2X1TS U3376 ( .A(n10921), .B(n1166), .Y(n10922) );
INVX2TS U3377 ( .A(n6738), .Y(n6795) );
CLKINVX6TS U3378 ( .A(n8614), .Y(n1952) );
NAND2X2TS U3379 ( .A(n2086), .B(n10811), .Y(n9390) );
OAI22X1TS U3380 ( .A0(n2095), .A1(n4971), .B0(n4972), .B1(n11758), .Y(n5011)
);
BUFX3TS U3381 ( .A(n7442), .Y(n2564) );
INVX2TS U3382 ( .A(n6670), .Y(n1269) );
NOR2XLTS U3383 ( .A(n1244), .B(n7031), .Y(n4302) );
OAI22X2TS U3384 ( .A0(n1866), .A1(n6004), .B0(n3320), .B1(n6012), .Y(n6024)
);
NOR2X1TS U3385 ( .A(n6511), .B(n6510), .Y(n3020) );
OAI2BB1X2TS U3386 ( .A0N(n1016), .A1N(n6445), .B0(n6551), .Y(n2764) );
XNOR2X2TS U3387 ( .A(n2549), .B(n8887), .Y(n8472) );
BUFX12TS U3388 ( .A(n2446), .Y(n6885) );
NAND2X1TS U3389 ( .A(n10957), .B(n10841), .Y(n10842) );
OAI22X2TS U3390 ( .A0(n4704), .A1(n1965), .B0(n4703), .B1(n1862), .Y(n4729)
);
XNOR2X2TS U3391 ( .A(n8889), .B(n2058), .Y(n3950) );
NAND2X1TS U3392 ( .A(n7650), .B(n11618), .Y(n7648) );
XNOR2X2TS U3393 ( .A(n2573), .B(n2057), .Y(n7328) );
INVX2TS U3394 ( .A(n7598), .Y(n7345) );
OAI22X2TS U3395 ( .A0(n4088), .A1(n8980), .B0(n4299), .B1(n2356), .Y(n4084)
);
OAI21X2TS U3396 ( .A0(n10150), .A1(n10138), .B0(n10139), .Y(n1488) );
ADDFHX2TS U3397 ( .A(n4463), .B(n4465), .CI(n4464), .CO(n4780), .S(n4483) );
XNOR2X2TS U3398 ( .A(n6510), .B(n6511), .Y(n3021) );
NOR2X2TS U3399 ( .A(n10955), .B(n10906), .Y(n10908) );
INVX2TS U3400 ( .A(n8771), .Y(n2866) );
INVX6TS U3401 ( .A(n8940), .Y(n9007) );
AND4X1TS U3402 ( .A(n12141), .B(n11970), .C(n12142), .D(n11812), .Y(n11194)
);
NAND2X1TS U3403 ( .A(n9071), .B(n7951), .Y(n7953) );
NAND2X4TS U3404 ( .A(n7944), .B(n11366), .Y(n9594) );
NOR2X2TS U3405 ( .A(n9300), .B(n10072), .Y(n9041) );
NAND2X1TS U3406 ( .A(n9327), .B(n9326), .Y(n9328) );
INVX4TS U3407 ( .A(n8860), .Y(n8878) );
OAI21XLTS U3408 ( .A0(n9179), .A1(n9178), .B0(n1203), .Y(n9180) );
OAI21X1TS U3409 ( .A0(n9567), .A1(n8338), .B0(n9571), .Y(n8342) );
INVX4TS U3410 ( .A(n1906), .Y(n1920) );
NAND2X2TS U3411 ( .A(n2875), .B(n2876), .Y(n2872) );
AOI21X2TS U3412 ( .A0(n10125), .A1(n7958), .B0(n7961), .Y(n7962) );
NAND2X1TS U3413 ( .A(n11012), .B(n2248), .Y(n11013) );
AOI21X2TS U3414 ( .A0(n7971), .A1(n10125), .B0(n7970), .Y(n7972) );
NAND2X1TS U3415 ( .A(n10764), .B(n10765), .Y(n10741) );
NAND2X1TS U3416 ( .A(n8865), .B(n8864), .Y(n8866) );
OAI21X2TS U3417 ( .A0(n10667), .A1(n10666), .B0(n10665), .Y(n10671) );
AOI21X2TS U3418 ( .A0(n10065), .A1(n8798), .B0(n8432), .Y(n8433) );
NAND2X4TS U3419 ( .A(n3235), .B(n3234), .Y(n6715) );
NAND2X1TS U3420 ( .A(n10069), .B(n10068), .Y(n10070) );
NAND2X1TS U3421 ( .A(n9651), .B(n9649), .Y(n7607) );
NAND2X1TS U3422 ( .A(n10217), .B(n10216), .Y(n10218) );
NAND2X1TS U3423 ( .A(n8412), .B(n8411), .Y(n8413) );
BUFX3TS U3424 ( .A(n10681), .Y(n10871) );
AOI2BB2X2TS U3425 ( .B0(n10861), .B1(n10881), .A0N(n2007), .A1N(n11848), .Y(
n12283) );
INVX2TS U3426 ( .A(n11135), .Y(overflow_flag) );
CLKINVX6TS U3427 ( .A(n1292), .Y(n4450) );
OR2X8TS U3428 ( .A(n8025), .B(n4858), .Y(n993) );
AND2X8TS U3429 ( .A(n2489), .B(n9326), .Y(n994) );
AO21X4TS U3430 ( .A0(n1692), .A1(n1198), .B0(n1693), .Y(n1000) );
NAND2X8TS U3431 ( .A(n2834), .B(n2833), .Y(n8470) );
AND2X4TS U3432 ( .A(n3022), .B(n8592), .Y(n1001) );
AND2X8TS U3433 ( .A(n1004), .B(n3754), .Y(n1003) );
AND2X8TS U3434 ( .A(n1387), .B(n2955), .Y(n1004) );
INVX4TS U3435 ( .A(n2957), .Y(n10036) );
OAI22X4TS U3436 ( .A0(n2103), .A1(n3497), .B0(n6040), .B1(n3468), .Y(n3492)
);
OAI22X4TS U3437 ( .A0(n3468), .A1(n6178), .B0(n6040), .B1(n3432), .Y(n3465)
);
XNOR2X4TS U3438 ( .A(n859), .B(n1324), .Y(n5036) );
OAI22X4TS U3439 ( .A0(n2077), .A1(n2672), .B0(n1883), .B1(n2380), .Y(n4434)
);
BUFX12TS U3440 ( .A(n3702), .Y(n1005) );
XNOR2X4TS U3441 ( .A(n8511), .B(n1926), .Y(n8580) );
OAI22X2TS U3442 ( .A0(n8507), .A1(n8938), .B0(n8520), .B1(n1940), .Y(n8649)
);
OAI22X4TS U3443 ( .A0(n2090), .A1(n5683), .B0(n5682), .B1(n1227), .Y(n5866)
);
ADDFHX4TS U3444 ( .A(n8590), .B(n8591), .CI(n8589), .CO(n9794), .S(n8684) );
OAI22X4TS U3445 ( .A0(n8520), .A1(n2067), .B0(n8564), .B1(n1892), .Y(n8590)
);
NAND2X4TS U3446 ( .A(n2736), .B(n2735), .Y(n2864) );
NAND2X4TS U3447 ( .A(n1465), .B(n2865), .Y(n2736) );
INVX4TS U3448 ( .A(n2766), .Y(n1466) );
NAND2X2TS U3449 ( .A(n1392), .B(n9588), .Y(add_x_19_n739) );
AND2X6TS U3450 ( .A(n2734), .B(n2325), .Y(n2735) );
MX2X2TS U3451 ( .A(n11015), .B(n1997), .S0(n1978), .Y(n447) );
NOR2X4TS U3452 ( .A(n10009), .B(DP_OP_168J26_122_4811_n172), .Y(
DP_OP_168J26_122_4811_n170) );
INVX4TS U3453 ( .A(n10009), .Y(DP_OP_168J26_122_4811_n200) );
NAND2X2TS U3454 ( .A(n2228), .B(n1452), .Y(n12302) );
MX2X2TS U3455 ( .A(n11000), .B(n1995), .S0(n11312), .Y(n446) );
NOR2X4TS U3456 ( .A(n2327), .B(n2326), .Y(n2325) );
NOR2X4TS U3457 ( .A(n1104), .B(n9558), .Y(n1103) );
INVX6TS U3458 ( .A(n9987), .Y(n2725) );
MX2X2TS U3459 ( .A(n11006), .B(P_Sgf[23]), .S0(n1977), .Y(n444) );
INVX3TS U3460 ( .A(Sgf_operation_ODD1_Q_left[38]), .Y(add_x_19_n228) );
MX2X2TS U3461 ( .A(n10794), .B(P_Sgf[19]), .S0(n1977), .Y(n440) );
NOR2X4TS U3462 ( .A(n2733), .B(n9034), .Y(n2327) );
INVX4TS U3463 ( .A(n10026), .Y(DP_OP_168J26_122_4811_n745) );
MX2X2TS U3464 ( .A(n10997), .B(P_Sgf[22]), .S0(n11312), .Y(n443) );
MX2X2TS U3465 ( .A(n10988), .B(P_Sgf[21]), .S0(n1978), .Y(n442) );
NAND2X2TS U3466 ( .A(n1834), .B(n10877), .Y(n12257) );
INVX4TS U3467 ( .A(n1462), .Y(n1460) );
MX2X2TS U3468 ( .A(n10981), .B(P_Sgf[20]), .S0(n1978), .Y(n441) );
INVX3TS U3469 ( .A(n9294), .Y(n2733) );
INVX3TS U3470 ( .A(n10108), .Y(n10107) );
NAND2X6TS U3471 ( .A(n10040), .B(n10034), .Y(n3238) );
NAND2X2TS U3472 ( .A(n1836), .B(n488), .Y(n8794) );
MX2X2TS U3473 ( .A(n10781), .B(P_Sgf[18]), .S0(n11312), .Y(n439) );
NAND2X4TS U3474 ( .A(n3198), .B(n3197), .Y(n9294) );
MX2X2TS U3475 ( .A(n10770), .B(P_Sgf[17]), .S0(n11312), .Y(n438) );
NAND2X4TS U3476 ( .A(n3153), .B(n3152), .Y(n3151) );
INVX6TS U3477 ( .A(n10109), .Y(DP_OP_168J26_122_4811_n183) );
MX2X4TS U3478 ( .A(n9544), .B(n12163), .S0(n1192), .Y(n490) );
NAND2X4TS U3479 ( .A(n10103), .B(n10102), .Y(n10108) );
XOR2X2TS U3480 ( .A(n10165), .B(n10164), .Y(Sgf_operation_ODD1_Q_left[24])
);
MX2X4TS U3481 ( .A(n8786), .B(n12164), .S0(n1211), .Y(n488) );
INVX16TS U3482 ( .A(n8797), .Y(n1009) );
INVX2TS U3483 ( .A(n2876), .Y(n2874) );
NAND2X2TS U3484 ( .A(n2226), .B(n2223), .Y(n364) );
OR2X4TS U3485 ( .A(n10181), .B(n10180), .Y(n11730) );
NAND2X2TS U3486 ( .A(n1835), .B(n485), .Y(n10755) );
NAND2X2TS U3487 ( .A(n484), .B(n1836), .Y(n2226) );
NAND2X2TS U3488 ( .A(n10882), .B(n487), .Y(n10782) );
OAI21X2TS U3489 ( .A0(n2016), .A1(n10867), .B0(n10866), .Y(n10868) );
MX2X2TS U3490 ( .A(n10736), .B(P_Sgf[14]), .S0(n11312), .Y(n435) );
BUFX12TS U3491 ( .A(n9049), .Y(n1033) );
XOR2X1TS U3492 ( .A(n10189), .B(n10188), .Y(Sgf_operation_ODD1_Q_left[19])
);
NOR2X4TS U3493 ( .A(n10053), .B(n8239), .Y(n2869) );
NAND2X4TS U3494 ( .A(n3026), .B(n8679), .Y(n3025) );
OR2X4TS U3495 ( .A(n10090), .B(n8766), .Y(n3200) );
NAND2X4TS U3496 ( .A(n2881), .B(n5485), .Y(n2880) );
NAND2X4TS U3497 ( .A(n3024), .B(n8680), .Y(n3023) );
NAND2X2TS U3498 ( .A(n2040), .B(n9345), .Y(n9346) );
XNOR2X1TS U3499 ( .A(n10197), .B(n10196), .Y(Sgf_operation_ODD1_Q_left[17])
);
NAND2X2TS U3500 ( .A(n2040), .B(n10953), .Y(n9360) );
NAND2X2TS U3501 ( .A(n2040), .B(n1172), .Y(n10896) );
INVX2TS U3502 ( .A(n11001), .Y(n11003) );
NAND2X2TS U3503 ( .A(n9266), .B(n9265), .Y(n9267) );
INVX4TS U3504 ( .A(n9564), .Y(n10090) );
NAND2X2TS U3505 ( .A(n2040), .B(n10930), .Y(n10931) );
OAI21X2TS U3506 ( .A0(n10193), .A1(n10192), .B0(n9746), .Y(n10197) );
NAND3X2TS U3507 ( .A(n10688), .B(n10687), .C(n10686), .Y(n361) );
NAND2X4TS U3508 ( .A(n9931), .B(n9932), .Y(n2371) );
NOR2X4TS U3509 ( .A(n10955), .B(n9347), .Y(n9349) );
NAND3X2TS U3510 ( .A(n10691), .B(n10690), .C(n10689), .Y(n360) );
NAND2X2TS U3511 ( .A(n10954), .B(n10831), .Y(n10833) );
INVX2TS U3512 ( .A(n11008), .Y(n10998) );
INVX2TS U3513 ( .A(n8325), .Y(n7558) );
NAND2X2TS U3514 ( .A(n2085), .B(n10851), .Y(n10853) );
NAND2X2TS U3515 ( .A(n2086), .B(n10953), .Y(n9361) );
MXI2X2TS U3516 ( .A(n10621), .B(n11835), .S0(n11242), .Y(n352) );
INVX2TS U3517 ( .A(n8718), .Y(n1105) );
NAND2X2TS U3518 ( .A(n1821), .B(n482), .Y(n10711) );
NAND3X1TS U3519 ( .A(n10701), .B(n10700), .C(n10699), .Y(n356) );
MX2X2TS U3520 ( .A(n11023), .B(n2127), .S0(n1978), .Y(n431) );
NAND2X2TS U3521 ( .A(n2085), .B(n10939), .Y(n10942) );
NAND2X2TS U3522 ( .A(n10620), .B(n10619), .Y(n10621) );
INVX2TS U3523 ( .A(n8435), .Y(n8437) );
NOR2X2TS U3524 ( .A(n9417), .B(n9420), .Y(n9422) );
OAI21X2TS U3525 ( .A0(n10739), .A1(n10738), .B0(n11833), .Y(n709) );
XNOR2X2TS U3526 ( .A(n10237), .B(n10236), .Y(Sgf_operation_ODD1_Q_left[11])
);
NAND2X2TS U3527 ( .A(n1834), .B(n478), .Y(n10702) );
NOR2X4TS U3528 ( .A(n1548), .B(n1960), .Y(n1064) );
NAND2X4TS U3529 ( .A(n10069), .B(n8386), .Y(n8218) );
NAND2X4TS U3530 ( .A(n1578), .B(n1067), .Y(n1066) );
INVX3TS U3531 ( .A(n10206), .Y(n10223) );
NAND2X2TS U3532 ( .A(n9315), .B(n9314), .Y(n9316) );
INVX2TS U3533 ( .A(n9418), .Y(n9421) );
INVX2TS U3534 ( .A(n10138), .Y(n10140) );
NAND2X2TS U3535 ( .A(n9541), .B(n9540), .Y(n9542) );
NAND3X2TS U3536 ( .A(n11127), .B(n11125), .C(n10618), .Y(n10619) );
INVX3TS U3537 ( .A(n9746), .Y(n10191) );
INVX4TS U3538 ( .A(n10194), .Y(n6274) );
MX2X4TS U3539 ( .A(n8875), .B(n12173), .S0(n1194), .Y(n480) );
NAND2X2TS U3540 ( .A(n9611), .B(n9610), .Y(n9612) );
NAND2X2TS U3541 ( .A(n7982), .B(n9531), .Y(n7983) );
INVX1TS U3542 ( .A(n9601), .Y(n9604) );
CLKMX2X2TS U3543 ( .A(n11115), .B(P_Sgf[8]), .S0(n1977), .Y(n429) );
NAND2X2TS U3544 ( .A(n9554), .B(n9553), .Y(n9555) );
AND2X4TS U3545 ( .A(n1847), .B(n2622), .Y(n8377) );
INVX2TS U3546 ( .A(n2936), .Y(n7113) );
INVX3TS U3547 ( .A(n8191), .Y(n9081) );
INVX3TS U3548 ( .A(n1571), .Y(n1568) );
NAND2X1TS U3549 ( .A(n10187), .B(n10186), .Y(n10188) );
INVX2TS U3550 ( .A(n10771), .Y(n10773) );
INVX2TS U3551 ( .A(n6674), .Y(n3273) );
INVX4TS U3552 ( .A(n9739), .Y(n2539) );
NAND2X4TS U3553 ( .A(n2793), .B(n6441), .Y(n2792) );
INVX2TS U3554 ( .A(n10764), .Y(n10766) );
NAND2X4TS U3555 ( .A(n9249), .B(n2320), .Y(n2319) );
INVX2TS U3556 ( .A(n8835), .Y(n9435) );
INVX2TS U3557 ( .A(n10094), .Y(n10096) );
NAND2X4TS U3558 ( .A(n7584), .B(n1367), .Y(n8337) );
NOR2X4TS U3559 ( .A(n7922), .B(n1184), .Y(n10771) );
NOR2X4TS U3560 ( .A(n7929), .B(n1185), .Y(n8835) );
AND3X4TS U3561 ( .A(n9248), .B(n9247), .C(n9246), .Y(n9249) );
MX2X2TS U3562 ( .A(n11110), .B(Exp_module_Overflow_flag_A), .S0(n1977), .Y(
n405) );
MX2X2TS U3563 ( .A(n11127), .B(exp_oper_result[8]), .S0(n11126), .Y(n409) );
MX2X2TS U3564 ( .A(n11125), .B(exp_oper_result[9]), .S0(n11126), .Y(n408) );
INVX4TS U3565 ( .A(n7573), .Y(n8392) );
MX2X2TS U3566 ( .A(n11069), .B(exp_oper_result[4]), .S0(n11068), .Y(n413) );
NAND2X4TS U3567 ( .A(n7822), .B(n11367), .Y(n9540) );
INVX2TS U3568 ( .A(n1570), .Y(n1567) );
INVX3TS U3569 ( .A(n1599), .Y(n1598) );
BUFX16TS U3570 ( .A(n3609), .Y(n8620) );
INVX4TS U3571 ( .A(n8849), .Y(n8870) );
INVX4TS U3572 ( .A(n8421), .Y(n9576) );
NOR2X4TS U3573 ( .A(n10637), .B(n10638), .Y(n5095) );
NOR2X4TS U3574 ( .A(n9579), .B(n8425), .Y(n7584) );
NAND2X2TS U3575 ( .A(n9644), .B(n9643), .Y(n9645) );
XOR2X1TS U3576 ( .A(n11109), .B(n11108), .Y(n11110) );
INVX3TS U3577 ( .A(n6555), .Y(n6593) );
INVX6TS U3578 ( .A(n6659), .Y(n1330) );
INVX3TS U3579 ( .A(n8869), .Y(n8851) );
AND4X2TS U3580 ( .A(n11024), .B(n11123), .C(n10598), .D(n11025), .Y(n10599)
);
INVX8TS U3581 ( .A(n8586), .Y(n1707) );
NAND2X4TS U3582 ( .A(n1611), .B(n8878), .Y(n8849) );
INVX2TS U3583 ( .A(n9512), .Y(n9497) );
XOR2X2TS U3584 ( .A(n10647), .B(n10646), .Y(n10648) );
MX2X2TS U3585 ( .A(n9237), .B(n12152), .S0(n1215), .Y(n471) );
INVX4TS U3586 ( .A(n8358), .Y(n3277) );
NAND2X2TS U3587 ( .A(n9331), .B(n9330), .Y(n9333) );
NAND2X4TS U3588 ( .A(n8032), .B(n2262), .Y(n8421) );
INVX4TS U3589 ( .A(n6671), .Y(n1268) );
BUFX3TS U3590 ( .A(n6747), .Y(n3279) );
NAND2X4TS U3591 ( .A(n8845), .B(n8872), .Y(n8850) );
INVX2TS U3592 ( .A(n9329), .Y(n9331) );
NAND2X4TS U3593 ( .A(n2813), .B(n1036), .Y(n1073) );
CLKMX2X2TS U3594 ( .A(n11300), .B(P_Sgf[4]), .S0(n1977), .Y(n425) );
CLKMX2X2TS U3595 ( .A(n11091), .B(Add_result[41]), .S0(n11097), .Y(n538) );
CLKMX2X2TS U3596 ( .A(n11122), .B(Add_result[52]), .S0(n11333), .Y(n527) );
CLKMX2X2TS U3597 ( .A(n11086), .B(Add_result[39]), .S0(n11097), .Y(n540) );
NAND2X6TS U3598 ( .A(n3001), .B(n3147), .Y(n10625) );
INVX6TS U3599 ( .A(n6610), .Y(n6652) );
CLKMX2X2TS U3600 ( .A(n10435), .B(Add_result[40]), .S0(n11097), .Y(n539) );
OAI21X2TS U3601 ( .A0(n10667), .A1(n10651), .B0(n10650), .Y(n10655) );
INVX2TS U3602 ( .A(n7802), .Y(n1611) );
OAI21X1TS U3603 ( .A0(n10946), .A1(n11877), .B0(n10754), .Y(n2224) );
CLKMX2X2TS U3604 ( .A(n11038), .B(Add_result[48]), .S0(n11037), .Y(n531) );
NOR2BX2TS U3605 ( .AN(n618), .B(n10255), .Y(n10256) );
CLKMX2X2TS U3606 ( .A(n10418), .B(Add_result[28]), .S0(n11071), .Y(n551) );
NOR2BX1TS U3607 ( .AN(n646), .B(n11531), .Y(n11530) );
INVX2TS U3608 ( .A(n10269), .Y(n2001) );
NAND2X4TS U3609 ( .A(n3131), .B(n3130), .Y(n6610) );
CLKMX2X2TS U3610 ( .A(n10407), .B(Add_result[27]), .S0(n11071), .Y(n552) );
INVX3TS U3611 ( .A(n6613), .Y(n6658) );
CLKMX2X2TS U3612 ( .A(n11042), .B(Add_result[26]), .S0(n11071), .Y(n553) );
INVX4TS U3613 ( .A(n10678), .Y(n10692) );
INVX6TS U3614 ( .A(n6694), .Y(n1010) );
CLKMX2X2TS U3615 ( .A(n11056), .B(Add_result[24]), .S0(n11329), .Y(n555) );
CLKMX2X2TS U3616 ( .A(n11072), .B(Add_result[34]), .S0(n11071), .Y(n545) );
CLKMX2X2TS U3617 ( .A(n11051), .B(Add_result[25]), .S0(n11329), .Y(n554) );
NAND2X1TS U3618 ( .A(n8880), .B(n8879), .Y(n8881) );
INVX4TS U3619 ( .A(n8841), .Y(n8872) );
XOR2X1TS U3620 ( .A(n650), .B(n651), .Y(n11532) );
BUFX12TS U3621 ( .A(n4356), .Y(n8518) );
INVX2TS U3622 ( .A(n9694), .Y(n6088) );
AND2X2TS U3623 ( .A(n10664), .B(n10645), .Y(n10646) );
INVX2TS U3624 ( .A(n11296), .Y(n5043) );
BUFX6TS U3625 ( .A(n10321), .Y(n12228) );
NOR2X1TS U3626 ( .A(n10478), .B(n11324), .Y(n10479) );
INVX2TS U3627 ( .A(n9726), .Y(n11338) );
NAND2X4TS U3628 ( .A(n2189), .B(n2187), .Y(n2196) );
NOR2X1TS U3629 ( .A(n11119), .B(n11118), .Y(n11121) );
AO22X1TS U3630 ( .A0(n11287), .A1(n11246), .B0(final_result_ieee[21]), .B1(
n11286), .Y(n330) );
AO22X1TS U3631 ( .A0(n11287), .A1(n11244), .B0(final_result_ieee[20]), .B1(
n11286), .Y(n331) );
AO22X1TS U3632 ( .A0(n11287), .A1(n11245), .B0(final_result_ieee[19]), .B1(
n11286), .Y(n332) );
NAND2BX1TS U3633 ( .AN(n11834), .B(n10976), .Y(n3288) );
CMPR22X2TS U3634 ( .A(n6556), .B(n6557), .CO(n6536), .S(n6590) );
AO22X2TS U3635 ( .A0(n11294), .A1(n11291), .B0(final_result_ieee[44]), .B1(
n11290), .Y(n307) );
AO22X2TS U3636 ( .A0(n11294), .A1(n11289), .B0(final_result_ieee[43]), .B1(
n11290), .Y(n308) );
AO22X2TS U3637 ( .A0(n10340), .A1(n11277), .B0(final_result_ieee[42]), .B1(
n11290), .Y(n309) );
AO22X2TS U3638 ( .A0(n10340), .A1(n11266), .B0(final_result_ieee[41]), .B1(
n11290), .Y(n310) );
AO22X2TS U3639 ( .A0(n10340), .A1(n11262), .B0(final_result_ieee[40]), .B1(
n2011), .Y(n311) );
AO22X2TS U3640 ( .A0(n10340), .A1(n11261), .B0(final_result_ieee[39]), .B1(
n11290), .Y(n312) );
NAND2X4TS U3641 ( .A(n10669), .B(n10664), .Y(n7747) );
AO22X2TS U3642 ( .A0(n10341), .A1(n11272), .B0(final_result_ieee[31]), .B1(
n2011), .Y(n320) );
AO22X2TS U3643 ( .A0(n10341), .A1(n11275), .B0(final_result_ieee[30]), .B1(
n2011), .Y(n321) );
AO22X2TS U3644 ( .A0(n10340), .A1(n11267), .B0(final_result_ieee[34]), .B1(
n11290), .Y(n317) );
AO22X2TS U3645 ( .A0(n10341), .A1(n11271), .B0(final_result_ieee[26]), .B1(
n2011), .Y(n325) );
AO22X2TS U3646 ( .A0(n10341), .A1(n11268), .B0(final_result_ieee[27]), .B1(
n2011), .Y(n324) );
AO22X2TS U3647 ( .A0(n10341), .A1(n11257), .B0(final_result_ieee[25]), .B1(
n2011), .Y(n326) );
AO22X2TS U3648 ( .A0(n10341), .A1(n11263), .B0(final_result_ieee[28]), .B1(
n2011), .Y(n323) );
AO22X2TS U3649 ( .A0(n10340), .A1(n11265), .B0(final_result_ieee[35]), .B1(
n11290), .Y(n316) );
AO22X2TS U3650 ( .A0(n10341), .A1(n11269), .B0(final_result_ieee[32]), .B1(
n2011), .Y(n319) );
AO22X2TS U3651 ( .A0(n10340), .A1(n11273), .B0(final_result_ieee[36]), .B1(
n11290), .Y(n315) );
AO22X2TS U3652 ( .A0(n10340), .A1(n11260), .B0(final_result_ieee[33]), .B1(
n2011), .Y(n318) );
AO22X2TS U3653 ( .A0(n10340), .A1(n11264), .B0(final_result_ieee[37]), .B1(
n11290), .Y(n314) );
NAND2X2TS U3654 ( .A(n609), .B(n582), .Y(n11476) );
AO22X2TS U3655 ( .A0(n10341), .A1(n11259), .B0(final_result_ieee[29]), .B1(
n2011), .Y(n322) );
AO22X2TS U3656 ( .A0(n10340), .A1(n11253), .B0(final_result_ieee[38]), .B1(
n11290), .Y(n313) );
INVX2TS U3657 ( .A(n7913), .Y(n7876) );
MXI2X4TS U3658 ( .A(n10275), .B(n11910), .S0(n11171), .Y(n582) );
MXI2X4TS U3659 ( .A(n9721), .B(n11921), .S0(n9731), .Y(n658) );
INVX6TS U3660 ( .A(n1357), .Y(n12218) );
BUFX8TS U3661 ( .A(n11250), .Y(n11252) );
BUFX12TS U3662 ( .A(n12243), .Y(n10321) );
BUFX8TS U3663 ( .A(n11250), .Y(n11294) );
NAND2X2TS U3664 ( .A(n10544), .B(n10543), .Y(n10548) );
INVX12TS U3665 ( .A(n2714), .Y(n2097) );
NOR2X4TS U3666 ( .A(n10539), .B(n10538), .Y(n10567) );
INVX8TS U3667 ( .A(n1021), .Y(n12217) );
BUFX8TS U3668 ( .A(n11254), .Y(n10758) );
INVX4TS U3669 ( .A(n8920), .Y(n1038) );
AND2X4TS U3670 ( .A(n10649), .B(n10653), .Y(n10660) );
BUFX12TS U3671 ( .A(n1357), .Y(n12220) );
MXI2X4TS U3672 ( .A(n10296), .B(n11962), .S0(n10299), .Y(n585) );
MXI2X4TS U3673 ( .A(n10289), .B(n11957), .S0(n10299), .Y(n588) );
MX2X2TS U3674 ( .A(n9722), .B(n11811), .S0(n9731), .Y(n9723) );
INVX2TS U3675 ( .A(n10505), .Y(n10508) );
INVX4TS U3676 ( .A(n7862), .Y(n7651) );
MXI2X4TS U3677 ( .A(n10290), .B(n11968), .S0(n10310), .Y(n622) );
INVX4TS U3678 ( .A(n7666), .Y(n2197) );
INVX4TS U3679 ( .A(n11186), .Y(n11180) );
INVX8TS U3680 ( .A(n1021), .Y(n1011) );
BUFX20TS U3681 ( .A(n11139), .Y(n11171) );
BUFX8TS U3682 ( .A(n11328), .Y(n2049) );
BUFX8TS U3683 ( .A(n11139), .Y(n11148) );
CLKMX2X2TS U3684 ( .A(n11066), .B(Add_result[7]), .S0(n11319), .Y(n572) );
BUFX12TS U3685 ( .A(n1827), .Y(n12243) );
OR2X4TS U3686 ( .A(n9207), .B(n1153), .Y(n10649) );
NOR2X8TS U3687 ( .A(n9232), .B(n9227), .Y(n7737) );
INVX12TS U3688 ( .A(n5515), .Y(n2714) );
INVX2TS U3689 ( .A(n1967), .Y(n1039) );
NOR2X8TS U3690 ( .A(n9369), .B(n11833), .Y(n11254) );
INVX3TS U3691 ( .A(n1626), .Y(n1533) );
NAND2X2TS U3692 ( .A(n10512), .B(n10511), .Y(n10594) );
NAND2X2TS U3693 ( .A(n11107), .B(n3333), .Y(n10506) );
NAND2X2TS U3694 ( .A(n10520), .B(n1440), .Y(n10612) );
ADDFHX2TS U3695 ( .A(n4220), .B(n4219), .CI(n4218), .CO(n4047), .S(n5377) );
NAND2X2TS U3696 ( .A(n10523), .B(n1434), .Y(n10578) );
NAND2X4TS U3697 ( .A(n2254), .B(n2948), .Y(n2947) );
OR2X4TS U3698 ( .A(n7740), .B(n1155), .Y(n10653) );
INVX4TS U3699 ( .A(n6780), .Y(n6811) );
NOR2X2TS U3700 ( .A(n7854), .B(n7858), .Y(n7861) );
OAI21X1TS U3701 ( .A0(n8740), .A1(n9143), .B0(n9144), .Y(n8741) );
BUFX12TS U3702 ( .A(n6529), .Y(n2265) );
INVX4TS U3703 ( .A(n7522), .Y(n1110) );
NAND2X8TS U3704 ( .A(n8789), .B(FS_Module_state_reg[1]), .Y(n9369) );
NOR2X4TS U3705 ( .A(n7735), .B(n11385), .Y(n9232) );
INVX8TS U3706 ( .A(n1826), .Y(n1827) );
BUFX20TS U3707 ( .A(n9688), .Y(n11139) );
BUFX20TS U3708 ( .A(n9688), .Y(n10259) );
BUFX12TS U3709 ( .A(n8508), .Y(n8887) );
INVX6TS U3710 ( .A(n10429), .Y(n11328) );
NOR2X1TS U3711 ( .A(n8739), .B(n9143), .Y(n8742) );
NAND2X6TS U3712 ( .A(n1287), .B(n3389), .Y(n5515) );
NAND2X2TS U3713 ( .A(n3638), .B(n2633), .Y(n3639) );
BUFX12TS U3714 ( .A(n6601), .Y(n6906) );
NAND2X1TS U3715 ( .A(n10427), .B(n10426), .Y(n10428) );
NOR2X4TS U3716 ( .A(n10386), .B(n10385), .Y(n10429) );
CLKAND2X2TS U3717 ( .A(n11321), .B(n580), .Y(n11322) );
CLKINVX2TS U3718 ( .A(n9142), .Y(n8739) );
AND2X4TS U3719 ( .A(n7024), .B(n11688), .Y(n1423) );
INVX1TS U3720 ( .A(n11173), .Y(n11176) );
INVX6TS U3721 ( .A(n12395), .Y(n1826) );
INVX2TS U3722 ( .A(n9170), .Y(n9191) );
NOR2X4TS U3723 ( .A(n9358), .B(n9357), .Y(n10811) );
INVX2TS U3724 ( .A(n7090), .Y(n7093) );
INVX2TS U3725 ( .A(n3637), .Y(n3638) );
CLKBUFX3TS U3726 ( .A(n9664), .Y(n1012) );
BUFX3TS U3727 ( .A(n12222), .Y(n1023) );
NOR2X8TS U3728 ( .A(n9256), .B(n10950), .Y(n11173) );
INVX2TS U3729 ( .A(n10413), .Y(n10414) );
INVX2TS U3730 ( .A(n10425), .Y(n10396) );
INVX2TS U3731 ( .A(n7660), .Y(n7662) );
NOR2X4TS U3732 ( .A(n11075), .B(n10447), .Y(n10475) );
INVX2TS U3733 ( .A(n3378), .Y(n1489) );
INVX8TS U3734 ( .A(n1804), .Y(n2207) );
BUFX12TS U3735 ( .A(n6835), .Y(n2657) );
CLKAND2X2TS U3736 ( .A(n1776), .B(n2117), .Y(n1449) );
AND2X2TS U3737 ( .A(n9254), .B(n9253), .Y(n2318) );
NOR2X4TS U3738 ( .A(n10497), .B(n10377), .Y(n10493) );
BUFX16TS U3739 ( .A(n5794), .Y(n6087) );
NOR2X4TS U3740 ( .A(n11092), .B(n10431), .Y(n11082) );
NOR2X4TS U3741 ( .A(n10413), .B(n10376), .Y(n10427) );
NOR2X2TS U3742 ( .A(n11046), .B(n10378), .Y(n10379) );
NAND2X2TS U3743 ( .A(n10384), .B(n10383), .Y(n10386) );
INVX8TS U3744 ( .A(n1970), .Y(n1971) );
AND2X2TS U3745 ( .A(n1358), .B(n1451), .Y(n2131) );
INVX12TS U3746 ( .A(n11099), .Y(n10950) );
INVX2TS U3747 ( .A(n11266), .Y(n11089) );
AND2X4TS U3748 ( .A(n2705), .B(n2683), .Y(n3388) );
NOR2X4TS U3749 ( .A(n7718), .B(n11400), .Y(n8743) );
OR2X4TS U3750 ( .A(n3774), .B(DP_OP_168J26_122_4811_n3227), .Y(n3775) );
CLKAND2X2TS U3751 ( .A(n1442), .B(n991), .Y(n1358) );
AND2X2TS U3752 ( .A(n1359), .B(n1450), .Y(n2000) );
INVX2TS U3753 ( .A(n11264), .Y(n11095) );
INVX2TS U3754 ( .A(n11248), .Y(n11327) );
NAND2X4TS U3755 ( .A(n11835), .B(n11135), .Y(n10339) );
NAND2X4TS U3756 ( .A(n11248), .B(n11245), .Y(n10497) );
NOR2X6TS U3757 ( .A(n10929), .B(n7919), .Y(n10920) );
INVX2TS U3758 ( .A(n11283), .Y(n10452) );
NAND2X1TS U3759 ( .A(n11291), .B(n11279), .Y(n10447) );
NAND2X2TS U3760 ( .A(n11282), .B(Sgf_normalized_result[47]), .Y(n11031) );
MXI2X2TS U3761 ( .A(n11823), .B(n12392), .S0(n1851), .Y(n10543) );
INVX2TS U3762 ( .A(n7899), .Y(n7895) );
INVX2TS U3763 ( .A(n7644), .Y(n7637) );
NAND2X2TS U3764 ( .A(n11244), .B(n11246), .Y(n10377) );
NAND2X1TS U3765 ( .A(n11263), .B(n11259), .Y(n10376) );
NAND2X1TS U3766 ( .A(n11258), .B(n11257), .Y(n10378) );
NAND2X2TS U3767 ( .A(n11275), .B(n11272), .Y(n10425) );
NAND2X4TS U3768 ( .A(n11277), .B(n11289), .Y(n11075) );
NAND2X1TS U3769 ( .A(n11273), .B(n11264), .Y(n10431) );
CLKINVX2TS U3770 ( .A(n9256), .Y(n9258) );
NAND2X2TS U3771 ( .A(n11253), .B(n11261), .Y(n10437) );
NOR2X2TS U3772 ( .A(n10382), .B(n10381), .Y(n10383) );
INVX2TS U3773 ( .A(n11263), .Y(n10416) );
NAND2X1TS U3774 ( .A(n11262), .B(n11266), .Y(n10436) );
NAND2X1TS U3775 ( .A(Sgf_normalized_result[12]), .B(
Sgf_normalized_result[13]), .Y(n10360) );
NAND3X2TS U3776 ( .A(n12076), .B(n12075), .C(n12074), .Y(n11278) );
NAND3X2TS U3777 ( .A(n12036), .B(n12035), .C(n12034), .Y(n11282) );
CLKBUFX2TS U3778 ( .A(Add_result[49]), .Y(n1992) );
NAND2X1TS U3779 ( .A(Sgf_normalized_result[16]), .B(
Sgf_normalized_result[17]), .Y(n10381) );
NAND3X2TS U3780 ( .A(n12082), .B(n12081), .C(n12080), .Y(n11279) );
NAND2X1TS U3781 ( .A(Sgf_normalized_result[8]), .B(Sgf_normalized_result[9]),
.Y(n10350) );
INVX6TS U3782 ( .A(n1730), .Y(n2930) );
INVX2TS U3783 ( .A(n11829), .Y(n11231) );
INVX8TS U3784 ( .A(DP_OP_168J26_122_4811_n6617), .Y(n1863) );
NOR2X8TS U3785 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[1]), .Y(
n9735) );
NAND2X4TS U3786 ( .A(n11798), .B(FS_Module_state_reg[2]), .Y(n8790) );
NAND3X2TS U3787 ( .A(n12073), .B(n12072), .C(n12071), .Y(n11283) );
NAND3X2TS U3788 ( .A(n12033), .B(n12032), .C(n12031), .Y(n11280) );
NAND3X2TS U3789 ( .A(n12010), .B(n12009), .C(n12008), .Y(n11248) );
NAND3X2TS U3790 ( .A(n12013), .B(n12012), .C(n12011), .Y(n11245) );
INVX8TS U3791 ( .A(n1237), .Y(n7243) );
BUFX16TS U3792 ( .A(n1284), .Y(n2643) );
CLKBUFX2TS U3793 ( .A(Add_result[21]), .Y(n2118) );
NOR2X4TS U3794 ( .A(n11432), .B(n11433), .Y(n9182) );
NAND2X2TS U3795 ( .A(n1200), .B(n1136), .Y(n7899) );
AOI21X2TS U3796 ( .A0(n1196), .A1(n11609), .B0(n11610), .Y(n7723) );
NAND3X2TS U3797 ( .A(n12058), .B(n12057), .C(n12056), .Y(n11257) );
NAND3X2TS U3798 ( .A(n12067), .B(n12066), .C(n12065), .Y(n11268) );
NAND3X2TS U3799 ( .A(n12049), .B(n12048), .C(n12047), .Y(n11263) );
NAND3X2TS U3800 ( .A(n12019), .B(n12018), .C(n12017), .Y(n11259) );
MXI2X2TS U3801 ( .A(n11825), .B(n12389), .S0(FSM_selector_A), .Y(n10534) );
NAND3X2TS U3802 ( .A(n12016), .B(n12015), .C(n12014), .Y(n11275) );
NAND3X2TS U3803 ( .A(n12022), .B(n12021), .C(n12020), .Y(n11272) );
INVX6TS U3804 ( .A(n1629), .Y(n1241) );
INVX8TS U3805 ( .A(DP_OP_168J26_122_4811_n6609), .Y(n1949) );
NAND2X6TS U3806 ( .A(DP_OP_168J26_122_4811_n6588), .B(
DP_OP_168J26_122_4811_n6616), .Y(n4822) );
OR2X6TS U3807 ( .A(FSM_selector_B[1]), .B(n11821), .Y(n10531) );
INVX8TS U3808 ( .A(n1228), .Y(n1229) );
OAI21X2TS U3809 ( .A0(n11635), .A1(n11636), .B0(n11637), .Y(n7911) );
CLKBUFX2TS U3810 ( .A(Add_result[23]), .Y(n2120) );
CLKAND2X2TS U3811 ( .A(n1352), .B(n1443), .Y(n1359) );
CLKBUFX2TS U3812 ( .A(Add_result[20]), .Y(n2119) );
NAND3X2TS U3813 ( .A(n12100), .B(n12099), .C(n12098), .Y(n11264) );
NAND3X2TS U3814 ( .A(n12042), .B(n12041), .C(n12040), .Y(n11273) );
NAND3X2TS U3815 ( .A(n12094), .B(n12093), .C(n12092), .Y(n11261) );
NOR2X4TS U3816 ( .A(n11421), .B(n11422), .Y(n9196) );
NAND3X2TS U3817 ( .A(n12088), .B(n12087), .C(n12086), .Y(n11289) );
NAND3X2TS U3818 ( .A(n12091), .B(n12090), .C(n12089), .Y(n11262) );
NAND3X2TS U3819 ( .A(n12079), .B(n12078), .C(n12077), .Y(n11265) );
NAND3X2TS U3820 ( .A(n12085), .B(n12084), .C(n12083), .Y(n11291) );
NAND3X2TS U3821 ( .A(n12064), .B(n12063), .C(n12062), .Y(n11246) );
CLKAND2X2TS U3822 ( .A(n1353), .B(n1444), .Y(n1450) );
NAND3X2TS U3823 ( .A(n12106), .B(n12105), .C(n12104), .Y(n11256) );
CLKAND2X2TS U3824 ( .A(n1354), .B(n1445), .Y(n1451) );
NAND3X2TS U3825 ( .A(n12028), .B(n12027), .C(n12026), .Y(n11267) );
NAND3X2TS U3826 ( .A(n12109), .B(n12108), .C(n12107), .Y(n11266) );
NAND3X2TS U3827 ( .A(n12039), .B(n12038), .C(n12037), .Y(n11260) );
NOR4X1TS U3828 ( .A(P_Sgf[6]), .B(P_Sgf[7]), .C(P_Sgf[5]), .D(P_Sgf[4]), .Y(
n9244) );
INVX2TS U3829 ( .A(Data_MX[38]), .Y(n9719) );
INVX6TS U3830 ( .A(DP_OP_168J26_122_4811_n626), .Y(
DP_OP_168J26_122_4811_n627) );
NAND2X6TS U3831 ( .A(n3289), .B(n3288), .Y(n12379) );
NAND2X6TS U3832 ( .A(n3292), .B(n3098), .Y(n3291) );
NAND2X6TS U3833 ( .A(n9584), .B(n9585), .Y(n9624) );
NAND2X6TS U3834 ( .A(n3188), .B(n3187), .Y(n4426) );
ADDFHX2TS U3835 ( .A(n9892), .B(n9891), .CI(n9890), .CO(
DP_OP_168J26_122_4811_n1253), .S(DP_OP_168J26_122_4811_n1254) );
NAND2X6TS U3836 ( .A(n3294), .B(n3293), .Y(n3292) );
NAND2X2TS U3837 ( .A(n9368), .B(n9369), .Y(n12251) );
NAND2X6TS U3838 ( .A(n8776), .B(n8775), .Y(DP_OP_168J26_122_4811_n543) );
ADDFHX2TS U3839 ( .A(n9882), .B(n9881), .CI(n9880), .CO(
DP_OP_168J26_122_4811_n1053), .S(DP_OP_168J26_122_4811_n1054) );
NAND2X4TS U3840 ( .A(n2884), .B(n2883), .Y(n9891) );
NAND2X2TS U3841 ( .A(n1821), .B(n1000), .Y(n12290) );
NAND2X2TS U3842 ( .A(n12219), .B(n10810), .Y(n12252) );
MXI2X4TS U3843 ( .A(n10809), .B(Add_result[52]), .S0(FSM_selector_C), .Y(
n9368) );
NAND2X2TS U3844 ( .A(n1835), .B(n10969), .Y(n12306) );
INVX6TS U3845 ( .A(n10003), .Y(DP_OP_168J26_122_4811_n303) );
NAND2X2TS U3846 ( .A(n12218), .B(n10809), .Y(n12250) );
NAND2X2TS U3847 ( .A(n12219), .B(n10969), .Y(n12305) );
AND2X4TS U3848 ( .A(n10088), .B(n10085), .Y(n1407) );
NAND2X6TS U3849 ( .A(n9945), .B(n1576), .Y(n1575) );
INVX4TS U3850 ( .A(n3209), .Y(DP_OP_168J26_122_4811_n619) );
NAND2X2TS U3851 ( .A(n2138), .B(n10970), .Y(n12301) );
INVX3TS U3852 ( .A(Sgf_operation_ODD1_Q_left[40]), .Y(add_x_19_n202) );
NAND2X2TS U3853 ( .A(n10882), .B(n10973), .Y(n12322) );
NOR2X4TS U3854 ( .A(add_x_19_n322), .B(add_x_19_n313), .Y(add_x_19_n310) );
NAND2X6TS U3855 ( .A(n2308), .B(n12179), .Y(n10969) );
NAND2X2TS U3856 ( .A(n1835), .B(n10972), .Y(n12298) );
NAND2X4TS U3857 ( .A(n10977), .B(FSM_selector_B[0]), .Y(n10978) );
NAND2X2TS U3858 ( .A(n1836), .B(n10878), .Y(n12261) );
NAND2X2TS U3859 ( .A(n10036), .B(n7424), .Y(DP_OP_168J26_122_4811_n99) );
NAND2X2TS U3860 ( .A(n10882), .B(n10948), .Y(n12318) );
NAND2X2TS U3861 ( .A(DP_OP_168J26_122_4811_n743), .B(n10037), .Y(
DP_OP_168J26_122_4811_n100) );
NAND2X2TS U3862 ( .A(n12219), .B(n10974), .Y(n12293) );
INVX4TS U3863 ( .A(Sgf_operation_ODD1_Q_left[41]), .Y(add_x_19_n189) );
NAND2X2TS U3864 ( .A(n1836), .B(n10971), .Y(n12314) );
NAND2X2TS U3865 ( .A(n1835), .B(n10974), .Y(n12294) );
NAND2X4TS U3866 ( .A(n2230), .B(n12204), .Y(n2228) );
NAND2X2TS U3867 ( .A(n1011), .B(n10971), .Y(n12313) );
NAND2X2TS U3868 ( .A(n12219), .B(n10972), .Y(n12297) );
NAND2X2TS U3869 ( .A(n1834), .B(n10875), .Y(n12346) );
NAND2X2TS U3870 ( .A(n10872), .B(n12219), .Y(n12333) );
NAND2X2TS U3871 ( .A(n1834), .B(n10874), .Y(n12330) );
NAND2X4TS U3872 ( .A(n9367), .B(n1209), .Y(n2148) );
NAND2X4TS U3873 ( .A(n2309), .B(n1217), .Y(n2308) );
NAND2X4TS U3874 ( .A(n1091), .B(n9285), .Y(n2820) );
NAND2X2TS U3875 ( .A(n10876), .B(n12219), .Y(n12337) );
NAND2X2TS U3876 ( .A(n1836), .B(n11057), .Y(n12265) );
NAND2X2TS U3877 ( .A(n1821), .B(n10880), .Y(n12274) );
NAND2X2TS U3878 ( .A(n10882), .B(n10876), .Y(n12338) );
NAND2X2TS U3879 ( .A(n10976), .B(n10879), .Y(n12285) );
NAND2X6TS U3880 ( .A(n1009), .B(n2759), .Y(n2758) );
NAND2X2TS U3881 ( .A(n1821), .B(n10872), .Y(n12334) );
NAND2X2TS U3882 ( .A(n1011), .B(n11057), .Y(n12264) );
NAND2X2TS U3883 ( .A(n1835), .B(n10884), .Y(n12270) );
NAND2X2TS U3884 ( .A(n1821), .B(n10879), .Y(n12286) );
NAND3X2TS U3885 ( .A(n10807), .B(n10806), .C(n10805), .Y(n370) );
NAND2X2TS U3886 ( .A(n2138), .B(n11128), .Y(n12380) );
NAND2X2TS U3887 ( .A(n10976), .B(n10874), .Y(n12329) );
NOR2X6TS U3888 ( .A(n5478), .B(n7428), .Y(n1462) );
NAND2X2TS U3889 ( .A(n1011), .B(n10808), .Y(n12268) );
INVX2TS U3890 ( .A(n10041), .Y(n9319) );
NAND2X6TS U3891 ( .A(n1090), .B(n1370), .Y(n1091) );
NAND2X2TS U3892 ( .A(n11730), .B(n10182), .Y(DP_OP_168J26_122_4811_n95) );
NAND2X2TS U3893 ( .A(n10123), .B(n10122), .Y(DP_OP_168J26_122_4811_n96) );
NAND2X2TS U3894 ( .A(n10109), .B(n10108), .Y(DP_OP_168J26_122_4811_n97) );
NAND2X2TS U3895 ( .A(n997), .B(n9632), .Y(n9633) );
AND2X2TS U3896 ( .A(n10204), .B(n10203), .Y(n10205) );
NAND2X4TS U3897 ( .A(n1475), .B(n1474), .Y(n9952) );
MX2X4TS U3898 ( .A(n7985), .B(n12170), .S0(n1213), .Y(n489) );
INVX2TS U3899 ( .A(n9491), .Y(n9493) );
NAND2X4TS U3900 ( .A(n10079), .B(n9303), .Y(n3198) );
NAND2X2TS U3901 ( .A(n1834), .B(n10802), .Y(n12374) );
NAND2X6TS U3902 ( .A(n9632), .B(n2850), .Y(n2849) );
XOR2X2TS U3903 ( .A(n10179), .B(n10178), .Y(Sgf_operation_ODD1_Q_left[21])
);
NAND2X4TS U3904 ( .A(n10105), .B(n10104), .Y(n10122) );
NAND2X2TS U3905 ( .A(n12217), .B(n10802), .Y(n12373) );
NAND2X6TS U3906 ( .A(n3025), .B(n3023), .Y(n9826) );
INVX4TS U3907 ( .A(n10098), .Y(n2991) );
MXI2X4TS U3908 ( .A(n999), .B(n2227), .S0(n1212), .Y(n484) );
NAND2X6TS U3909 ( .A(n2350), .B(n2542), .Y(n8704) );
INVX2TS U3910 ( .A(n1033), .Y(n7562) );
MX2X4TS U3911 ( .A(n9557), .B(n12166), .S0(n1204), .Y(n486) );
MX2X4TS U3912 ( .A(n9521), .B(n12188), .S0(n1204), .Y(n487) );
MXI2X4TS U3913 ( .A(n992), .B(n2225), .S0(n1207), .Y(n485) );
INVX4TS U3914 ( .A(n9584), .Y(n2160) );
NAND2X2TS U3915 ( .A(n9371), .B(n7430), .Y(n7431) );
ADDFHX2TS U3916 ( .A(n9750), .B(n9749), .CI(n9748), .CO(n10181), .S(n10104)
);
ADDFHX2TS U3917 ( .A(n9472), .B(n9471), .CI(n9470), .CO(n10105), .S(n10102)
);
NAND2X6TS U3918 ( .A(n3142), .B(n9374), .Y(n2974) );
NOR2X4TS U3919 ( .A(n9293), .B(n9034), .Y(n8771) );
NAND2X6TS U3920 ( .A(n3199), .B(n3200), .Y(n10079) );
AND2X2TS U3921 ( .A(n2064), .B(n10892), .Y(n1381) );
INVX2TS U3922 ( .A(n10054), .Y(n10055) );
NAND2X6TS U3923 ( .A(n1509), .B(n9832), .Y(n1508) );
AND2X2TS U3924 ( .A(n3114), .B(n10089), .Y(n1426) );
AND2X2TS U3925 ( .A(n2064), .B(n10934), .Y(n1380) );
INVX2TS U3926 ( .A(n9337), .Y(n9322) );
INVX2TS U3927 ( .A(n10992), .Y(n10994) );
AND2X2TS U3928 ( .A(n2064), .B(n10799), .Y(n10801) );
NAND2X4TS U3929 ( .A(n10740), .B(n3155), .Y(n3154) );
NAND2X6TS U3930 ( .A(n2898), .B(n8487), .Y(n2350) );
INVX2TS U3931 ( .A(n10124), .Y(n10127) );
NAND2X4TS U3932 ( .A(n3221), .B(n9863), .Y(n3220) );
AND2X2TS U3933 ( .A(n10956), .B(n10827), .Y(n10829) );
INVX2TS U3934 ( .A(n8180), .Y(n10038) );
MX2X4TS U3935 ( .A(n10710), .B(n12167), .S0(n1208), .Y(n483) );
BUFX16TS U3936 ( .A(n7526), .Y(n9648) );
INVX2TS U3937 ( .A(n7969), .Y(n7961) );
INVX2TS U3938 ( .A(n2346), .Y(n10134) );
INVX2TS U3939 ( .A(n9047), .Y(n7563) );
INVX2TS U3940 ( .A(n10989), .Y(n10991) );
INVX8TS U3941 ( .A(n9300), .Y(n10073) );
OAI21X1TS U3942 ( .A0(n2084), .A1(n10942), .B0(n10941), .Y(n10943) );
NOR2X4TS U3943 ( .A(n3066), .B(n9290), .Y(n3065) );
NOR2X2TS U3944 ( .A(n2076), .B(n8802), .Y(n8804) );
NAND2X6TS U3945 ( .A(n2934), .B(n9563), .Y(n9300) );
NAND2X6TS U3946 ( .A(n3116), .B(n9560), .Y(n9564) );
NAND2X6TS U3947 ( .A(n2862), .B(n3043), .Y(n2720) );
OR2X2TS U3948 ( .A(n10202), .B(n10201), .Y(n10203) );
XOR2X2TS U3949 ( .A(n10212), .B(n10211), .Y(Sgf_operation_ODD1_Q_left[15])
);
XOR2X2TS U3950 ( .A(n10219), .B(n10218), .Y(Sgf_operation_ODD1_Q_left[14])
);
INVX2TS U3951 ( .A(n9264), .Y(n9266) );
MX2X2TS U3952 ( .A(n10635), .B(P_Sgf[11]), .S0(n1978), .Y(n432) );
MX2X2TS U3953 ( .A(n10643), .B(P_Sgf[12]), .S0(n11312), .Y(n433) );
ADDFHX2TS U3954 ( .A(n4057), .B(n4058), .CI(n4056), .CO(n3990), .S(n4278) );
NAND2X2TS U3955 ( .A(n9260), .B(n9259), .Y(n712) );
XNOR2X2TS U3956 ( .A(n10223), .B(n10222), .Y(Sgf_operation_ODD1_Q_left[13])
);
XNOR2X2TS U3957 ( .A(n10230), .B(n10229), .Y(Sgf_operation_ODD1_Q_left[12])
);
NAND2X4TS U3958 ( .A(n9558), .B(n9561), .Y(n3116) );
NOR2X2TS U3959 ( .A(n9754), .B(n1920), .Y(n10202) );
INVX2TS U3960 ( .A(n10061), .Y(n8378) );
INVX2TS U3961 ( .A(n2086), .Y(n10862) );
NAND2X6TS U3962 ( .A(n2614), .B(n1735), .Y(n10979) );
ADDFHX2TS U3963 ( .A(n3763), .B(n3762), .CI(n3761), .CO(n9932), .S(n3934) );
INVX2TS U3964 ( .A(n10150), .Y(n10135) );
MX2X4TS U3965 ( .A(n8859), .B(n12169), .S0(n1211), .Y(n482) );
OAI21X2TS U3966 ( .A0(n2539), .A1(n10233), .B0(n9740), .Y(n10237) );
MX2X4TS U3967 ( .A(n8848), .B(n12159), .S0(n1204), .Y(n481) );
NAND2X2TS U3968 ( .A(n10140), .B(n10139), .Y(n10141) );
INVX2TS U3969 ( .A(n7564), .Y(n6394) );
INVX2TS U3970 ( .A(n8184), .Y(n5481) );
INVX2TS U3971 ( .A(n8185), .Y(n5486) );
NAND2X4TS U3972 ( .A(n3251), .B(n3249), .Y(n6936) );
INVX3TS U3973 ( .A(n8615), .Y(n2460) );
NAND2X2TS U3974 ( .A(n9489), .B(n9488), .Y(n9490) );
INVX2TS U3975 ( .A(n8326), .Y(n8327) );
NAND2X6TS U3976 ( .A(n3236), .B(n3272), .Y(n2988) );
INVX2TS U3977 ( .A(n9313), .Y(n9315) );
INVX2TS U3978 ( .A(n9593), .Y(n9595) );
INVX2TS U3979 ( .A(n9599), .Y(n9600) );
NAND2X2TS U3980 ( .A(n9427), .B(n9426), .Y(n9428) );
INVX12TS U3981 ( .A(n9800), .Y(n1514) );
INVX2TS U3982 ( .A(n10171), .Y(n10172) );
NAND2X4TS U3983 ( .A(n6672), .B(n3237), .Y(n3236) );
NAND2X6TS U3984 ( .A(n2698), .B(n10767), .Y(n2162) );
NAND2X4TS U3985 ( .A(n7818), .B(n9545), .Y(n9516) );
NAND2X2TS U3986 ( .A(n9411), .B(n9419), .Y(n9412) );
INVX3TS U3987 ( .A(n8391), .Y(n8394) );
INVX3TS U3988 ( .A(n4254), .Y(n2774) );
MX2X4TS U3989 ( .A(n8868), .B(n12161), .S0(n1206), .Y(n479) );
XOR2X2TS U3990 ( .A(n8847), .B(n8846), .Y(n8848) );
MX2X4TS U3991 ( .A(n8883), .B(n12158), .S0(n1194), .Y(n478) );
INVX2TS U3992 ( .A(n10143), .Y(n10145) );
INVX2TS U3993 ( .A(n1400), .Y(n10765) );
INVX8TS U3994 ( .A(n8593), .Y(n8668) );
XOR2X2TS U3995 ( .A(n8882), .B(n8881), .Y(n8883) );
NAND2X2TS U3996 ( .A(n8820), .B(n8819), .Y(n8821) );
XOR2X2TS U3997 ( .A(n8867), .B(n8866), .Y(n8868) );
NAND2X4TS U3998 ( .A(n10721), .B(n10724), .Y(n3070) );
INVX2TS U3999 ( .A(n9539), .Y(n9541) );
MX2X4TS U4000 ( .A(n10680), .B(n12156), .S0(n1204), .Y(n476) );
INVX2TS U4001 ( .A(n2348), .Y(n7341) );
INVX2TS U4002 ( .A(n9552), .Y(n9554) );
INVX2TS U4003 ( .A(n8234), .Y(n10087) );
NAND2X2TS U4004 ( .A(n10708), .B(n10746), .Y(n10709) );
INVX2TS U4005 ( .A(n9548), .Y(n9522) );
NAND2X6TS U4006 ( .A(n1700), .B(n4284), .Y(n2829) );
INVX2TS U4007 ( .A(n9517), .Y(n8778) );
INVX2TS U4008 ( .A(n10175), .Y(n10177) );
INVX2TS U4009 ( .A(n9609), .Y(n9611) );
INVX2TS U4010 ( .A(n8781), .Y(n8783) );
INVX3TS U4011 ( .A(n2492), .Y(n3250) );
INVX2TS U4012 ( .A(n9532), .Y(n7982) );
XOR2X2TS U4013 ( .A(n8874), .B(n8873), .Y(n8875) );
CLKINVX2TS U4014 ( .A(n9425), .Y(n9427) );
INVX2TS U4015 ( .A(n9061), .Y(n9402) );
INVX2TS U4016 ( .A(n1708), .Y(n9857) );
INVX2TS U4017 ( .A(n10209), .Y(n6235) );
INVX4TS U4018 ( .A(n8339), .Y(n9638) );
ADDFHX2TS U4019 ( .A(n8529), .B(n8528), .CI(n8527), .CO(n9838), .S(n9814) );
INVX2TS U4020 ( .A(n10226), .Y(n10228) );
INVX4TS U4021 ( .A(n1728), .Y(n2301) );
NAND2X4TS U4022 ( .A(n7819), .B(n11361), .Y(n9517) );
INVX8TS U4023 ( .A(n2442), .Y(n7944) );
MX2X2TS U4024 ( .A(n11017), .B(exp_oper_result[11]), .S0(n11126), .Y(n406)
);
MX2X2TS U4025 ( .A(n11067), .B(exp_oper_result[5]), .S0(n11068), .Y(n412) );
MX2X2TS U4026 ( .A(n11018), .B(exp_oper_result[10]), .S0(n11126), .Y(n407)
);
AND2X2TS U4027 ( .A(n8402), .B(n8401), .Y(n1317) );
NAND2X2TS U4028 ( .A(n2426), .B(n8232), .Y(n10086) );
INVX2TS U4029 ( .A(n10714), .Y(n10730) );
NAND2X6TS U4030 ( .A(n7938), .B(n1168), .Y(n9401) );
INVX2TS U4031 ( .A(n9524), .Y(n9549) );
INVX2TS U4032 ( .A(n9546), .Y(n9547) );
NAND2X4TS U4033 ( .A(n7932), .B(n1163), .Y(n9426) );
OAI21X1TS U4034 ( .A0(n10266), .A1(n10262), .B0(n10263), .Y(n10250) );
INVX2TS U4035 ( .A(n10057), .Y(n8239) );
NAND2X2TS U4036 ( .A(n8341), .B(n7600), .Y(n7602) );
ADDFHX2TS U4037 ( .A(n8557), .B(n8555), .CI(n8556), .CO(n8545), .S(n8611) );
NAND2X4TS U4038 ( .A(n7931), .B(n1187), .Y(n9419) );
XNOR2X2TS U4039 ( .A(n8361), .B(n8360), .Y(n9626) );
NAND2X4TS U4040 ( .A(n7821), .B(n11362), .Y(n9531) );
INVX2TS U4041 ( .A(n8401), .Y(n7531) );
BUFX16TS U4042 ( .A(n8911), .Y(n2376) );
INVX2TS U4043 ( .A(n9053), .Y(n8405) );
OAI22X2TS U4044 ( .A0(n4813), .A1(n1973), .B0(n8910), .B1(n2036), .Y(n8952)
);
NOR2X1TS U4045 ( .A(n8849), .B(n8841), .Y(n8843) );
OAI21X1TS U4046 ( .A0(n11311), .A1(n11308), .B0(n11309), .Y(n11063) );
NOR2X1TS U4047 ( .A(n8849), .B(n8850), .Y(n8853) );
XOR2X2TS U4048 ( .A(n10606), .B(n10605), .Y(n11067) );
INVX2TS U4049 ( .A(n5449), .Y(n1325) );
INVX2TS U4050 ( .A(n10638), .Y(n10640) );
INVX2TS U4051 ( .A(n8425), .Y(n8427) );
INVX2TS U4052 ( .A(n8411), .Y(n7530) );
MX2X2TS U4053 ( .A(n10656), .B(n12140), .S0(n1213), .Y(n473) );
AOI21X4TS U4054 ( .A0(n8845), .A1(n7806), .B0(n7805), .Y(n1691) );
CLKXOR2X2TS U4055 ( .A(n9333), .B(n9332), .Y(n9342) );
XNOR2X2TS U4056 ( .A(n10671), .B(n10670), .Y(n10672) );
NAND2X2TS U4057 ( .A(n8359), .B(n8358), .Y(n8361) );
MX2X2TS U4058 ( .A(n9222), .B(n12154), .S0(n1215), .Y(n470) );
XOR2X2TS U4059 ( .A(n10564), .B(n10563), .Y(n11127) );
XOR2X2TS U4060 ( .A(n10547), .B(n10546), .Y(n11018) );
NOR2X4TS U4061 ( .A(n8893), .B(n1907), .Y(n8919) );
NAND2X2TS U4062 ( .A(n7807), .B(n11379), .Y(n8855) );
NAND2X2TS U4063 ( .A(n7814), .B(n1183), .Y(n9546) );
OAI2BB1X2TS U4064 ( .A0N(n7394), .A1N(n1073), .B0(n1071), .Y(n9455) );
INVX2TS U4065 ( .A(n2465), .Y(n8063) );
CLKINVX6TS U4066 ( .A(n8233), .Y(n7035) );
CLKXOR2X2TS U4067 ( .A(n10285), .B(n10284), .Y(Sgf_operation_ODD1_Q_left[5])
);
NAND2X4TS U4068 ( .A(n7812), .B(n11376), .Y(n10746) );
CLKINVX6TS U4069 ( .A(n5208), .Y(n1018) );
INVX4TS U4070 ( .A(n8229), .Y(n8090) );
OAI21X1TS U4071 ( .A0(n8876), .A1(n8861), .B0(n8879), .Y(n8862) );
XNOR2X2TS U4072 ( .A(n10655), .B(n10654), .Y(n10656) );
INVX2TS U4073 ( .A(n11123), .Y(n11124) );
OAI21X1TS U4074 ( .A0(n2001), .A1(n11513), .B0(n11510), .Y(n11522) );
INVX2TS U4075 ( .A(n8876), .Y(n8877) );
AND2X2TS U4076 ( .A(n10882), .B(n2229), .Y(n1452) );
ADDFHX2TS U4077 ( .A(n8523), .B(n8522), .CI(n8521), .CO(n8526), .S(n8589) );
MX2X2TS U4078 ( .A(n9218), .B(n12153), .S0(n1215), .Y(n469) );
MX2X4TS U4079 ( .A(n9209), .B(n12155), .S0(n1215), .Y(n472) );
INVX2TS U4080 ( .A(n9643), .Y(n9496) );
NAND2X2TS U4081 ( .A(n9303), .B(n9302), .Y(n9304) );
INVX2TS U4082 ( .A(n8757), .Y(n8758) );
NAND2X6TS U4083 ( .A(n2171), .B(n2170), .Y(n6693) );
XOR2X2TS U4084 ( .A(n9236), .B(n9235), .Y(n9237) );
XNOR2X2TS U4085 ( .A(n10597), .B(n10596), .Y(n11025) );
NOR2X1TS U4086 ( .A(n11670), .B(n2001), .Y(n11669) );
NOR2X4TS U4087 ( .A(n6671), .B(n6670), .Y(n2552) );
INVX2TS U4088 ( .A(n10728), .Y(n10729) );
OAI21X2TS U4089 ( .A0(n7673), .A1(n7788), .B0(n7672), .Y(n7678) );
INVX2TS U4090 ( .A(n11103), .Y(n10552) );
NAND2X6TS U4091 ( .A(n1473), .B(n1472), .Y(n1484) );
OAI21X2TS U4092 ( .A0(n7788), .A1(n7682), .B0(n7681), .Y(n7687) );
INVX2TS U4093 ( .A(n10241), .Y(n6134) );
INVX2TS U4094 ( .A(n10231), .Y(n10233) );
INVX4TS U4095 ( .A(n7586), .Y(n7153) );
BUFX20TS U4096 ( .A(n3345), .Y(n1019) );
NAND2X6TS U4097 ( .A(n2585), .B(n6600), .Y(n10728) );
INVX2TS U4098 ( .A(n10804), .Y(n1833) );
ADDFHX2TS U4099 ( .A(n4590), .B(n4589), .CI(n4588), .CO(n4816), .S(n4640) );
NAND2XLTS U4100 ( .A(n12383), .B(FS_Module_state_reg[2]), .Y(n11177) );
OAI21X1TS U4101 ( .A0(n12383), .A1(n11887), .B0(FS_Module_state_reg[3]), .Y(
n10332) );
OAI21X1TS U4102 ( .A0(n11103), .A1(n11102), .B0(n11101), .Y(n11104) );
NOR2X1TS U4103 ( .A(n8860), .B(n8861), .Y(n8863) );
XNOR2X1TS U4104 ( .A(n683), .B(n9682), .Y(n11467) );
INVX2TS U4105 ( .A(n10273), .Y(n11335) );
INVX8TS U4106 ( .A(n6632), .Y(n6694) );
XNOR2X1TS U4107 ( .A(n660), .B(n12137), .Y(n11529) );
INVX2TS U4108 ( .A(n10661), .Y(n10663) );
BUFX16TS U4109 ( .A(n3781), .Y(n8511) );
OAI21X1TS U4110 ( .A0(n11469), .A1(n11476), .B0(n11493), .Y(n11492) );
OAI21X1TS U4111 ( .A0(n10273), .A1(n11551), .B0(n11553), .Y(n11672) );
INVX2TS U4112 ( .A(n9649), .Y(n9650) );
INVX16TS U4113 ( .A(n10882), .Y(n10804) );
CLKMX2X2TS U4114 ( .A(n11326), .B(FSM_add_overflow_flag), .S0(n11333), .Y(
n526) );
NAND2X4TS U4115 ( .A(n10695), .B(n1368), .Y(n8860) );
NOR2X1TS U4116 ( .A(n10573), .B(n10602), .Y(n10576) );
NOR2X1TS U4117 ( .A(n10533), .B(n10567), .Y(n10542) );
OAI21X1TS U4118 ( .A0(n10540), .A1(n10567), .B0(n10568), .Y(n10541) );
CLKBUFX3TS U4119 ( .A(n11718), .Y(n2004) );
NOR2X1TS U4120 ( .A(n11118), .B(n11028), .Y(n11029) );
NOR2X1TS U4121 ( .A(n11118), .B(n11088), .Y(n11090) );
NOR2X1TS U4122 ( .A(n11324), .B(n10432), .Y(n10434) );
NOR2X2TS U4123 ( .A(n613), .B(n586), .Y(n11670) );
NOR2X1TS U4124 ( .A(n11324), .B(n11092), .Y(n10464) );
NOR2X1TS U4125 ( .A(n11118), .B(n11083), .Y(n11085) );
INVX4TS U4126 ( .A(n1447), .Y(n12139) );
NOR2X1TS U4127 ( .A(n11324), .B(n10459), .Y(n10461) );
NOR2X1TS U4128 ( .A(n11118), .B(n11078), .Y(n11080) );
NOR2X1TS U4129 ( .A(n11324), .B(n10455), .Y(n10457) );
NOR2X2TS U4130 ( .A(n620), .B(n593), .Y(n11551) );
NOR2X1TS U4131 ( .A(n11118), .B(n11070), .Y(n10468) );
NOR2X1TS U4132 ( .A(n11118), .B(n10470), .Y(n10471) );
XNOR2X1TS U4133 ( .A(n651), .B(n1355), .Y(n11667) );
NOR2X1TS U4134 ( .A(n11324), .B(n10477), .Y(n10445) );
NOR2X1TS U4135 ( .A(n11324), .B(n10483), .Y(n10484) );
NOR2X1TS U4136 ( .A(n11324), .B(n10440), .Y(n10442) );
NOR2X1TS U4137 ( .A(n11118), .B(n11034), .Y(n11036) );
NOR2X1TS U4138 ( .A(n11324), .B(n10451), .Y(n10453) );
AOI22X1TS U4139 ( .A0(n10758), .A1(Add_result[7]), .B0(
Sgf_normalized_result[6]), .B1(n10717), .Y(n10720) );
NAND2X6TS U4140 ( .A(n3028), .B(n3027), .Y(n5440) );
AOI22X1TS U4141 ( .A0(n11285), .A1(n2123), .B0(n11283), .B1(n12216), .Y(
n12263) );
INVX2TS U4142 ( .A(n10694), .Y(n7796) );
AND2X8TS U4143 ( .A(n9369), .B(n8793), .Y(n10882) );
INVX6TS U4144 ( .A(n9723), .Y(n12137) );
NAND2X4TS U4145 ( .A(n7794), .B(n11381), .Y(n10678) );
NAND2X8TS U4146 ( .A(n9369), .B(n8792), .Y(n10682) );
OR2X6TS U4147 ( .A(n7794), .B(n11382), .Y(n1368) );
INVX4TS U4148 ( .A(n10645), .Y(n10662) );
AOI22X1TS U4149 ( .A0(n11285), .A1(Add_result[51]), .B0(n11280), .B1(n12216),
.Y(n12259) );
NAND2X2TS U4150 ( .A(n620), .B(n593), .Y(n11553) );
XOR2X1TS U4151 ( .A(n650), .B(n677), .Y(n11673) );
NOR2X1TS U4152 ( .A(n11118), .B(n11094), .Y(n11096) );
NAND2X4TS U4153 ( .A(n7803), .B(n11372), .Y(n8871) );
NOR2X2TS U4154 ( .A(n618), .B(n591), .Y(n11491) );
AO22X1TS U4155 ( .A0(n11287), .A1(n11248), .B0(final_result_ieee[18]), .B1(
n11286), .Y(n333) );
NAND2X2TS U4156 ( .A(n617), .B(n590), .Y(n11552) );
AO22X1TS U4157 ( .A0(n11287), .A1(Sgf_normalized_result[17]), .B0(
final_result_ieee[17]), .B1(n11286), .Y(n334) );
NOR2X1TS U4158 ( .A(n621), .B(n594), .Y(n11566) );
OR2X2TS U4159 ( .A(n11804), .B(n694), .Y(n11590) );
AO22X1TS U4160 ( .A0(n11294), .A1(n11280), .B0(final_result_ieee[50]), .B1(
n11293), .Y(n301) );
AO22X1TS U4161 ( .A0(n11294), .A1(n11283), .B0(final_result_ieee[49]), .B1(
n11293), .Y(n302) );
AO22X1TS U4162 ( .A0(n11294), .A1(Sgf_normalized_result[47]), .B0(
final_result_ieee[47]), .B1(n11293), .Y(n304) );
AO22X1TS U4163 ( .A0(n11294), .A1(n11282), .B0(final_result_ieee[46]), .B1(
n11293), .Y(n305) );
NAND2X2TS U4164 ( .A(n1432), .B(n672), .Y(n11575) );
INVX2TS U4165 ( .A(n9043), .Y(n9466) );
INVX2TS U4166 ( .A(n8346), .Y(n8348) );
INVX4TS U4167 ( .A(n8769), .Y(n7366) );
INVX2TS U4168 ( .A(n6740), .Y(n6755) );
INVX12TS U4169 ( .A(n12220), .Y(n1978) );
XNOR2X1TS U4170 ( .A(n652), .B(n651), .Y(n11466) );
XOR2X1TS U4171 ( .A(n677), .B(n1355), .Y(n11470) );
NOR2X1TS U4172 ( .A(n11806), .B(n585), .Y(n11471) );
NAND2X2TS U4173 ( .A(n6742), .B(n6740), .Y(n10282) );
NAND2X2TS U4174 ( .A(n6738), .B(n6759), .Y(n10302) );
OAI21X1TS U4175 ( .A0(n662), .A1(n9726), .B0(n661), .Y(n11483) );
OR2X2TS U4176 ( .A(n6759), .B(n6738), .Y(n10303) );
INVX2TS U4177 ( .A(n649), .Y(n10277) );
NOR2X2TS U4178 ( .A(n3314), .B(n583), .Y(n11469) );
XNOR2X1TS U4179 ( .A(n648), .B(n647), .Y(n11495) );
INVX4TS U4180 ( .A(n11805), .Y(n12143) );
NOR2X1TS U4181 ( .A(n615), .B(n588), .Y(n11504) );
XOR2X1TS U4182 ( .A(n10317), .B(n10316), .Y(Sgf_operation_ODD1_Q_left[2]) );
INVX2TS U4183 ( .A(n677), .Y(n9700) );
OR2X2TS U4184 ( .A(n9693), .B(n696), .Y(n11519) );
NAND2X2TS U4185 ( .A(n614), .B(n587), .Y(n11510) );
NOR2X1TS U4186 ( .A(n611), .B(n584), .Y(n11523) );
INVX2TS U4187 ( .A(n673), .Y(n11531) );
AOI2BB2X1TS U4188 ( .B0(n11252), .B1(n12389), .A0N(n11251), .A1N(
final_result_ieee[59]), .Y(n292) );
NOR2X1TS U4189 ( .A(n622), .B(n595), .Y(n11550) );
NOR2X1TS U4190 ( .A(n623), .B(n596), .Y(n11560) );
NOR2X1TS U4191 ( .A(n617), .B(n590), .Y(n11561) );
INVX12TS U4192 ( .A(n12220), .Y(n11312) );
NAND2X2TS U4193 ( .A(n613), .B(n586), .Y(n11513) );
NOR2X1TS U4194 ( .A(n11325), .B(n11324), .Y(n11326) );
OR2X2TS U4195 ( .A(n614), .B(n587), .Y(n10269) );
INVX12TS U4196 ( .A(n12220), .Y(n1977) );
NAND2X2TS U4197 ( .A(n619), .B(n592), .Y(n10273) );
BUFX8TS U4198 ( .A(n11250), .Y(n11287) );
BUFX8TS U4199 ( .A(n10466), .Y(n11118) );
NOR2X1TS U4200 ( .A(n2049), .B(n10499), .Y(n10501) );
OR2X6TS U4201 ( .A(n7795), .B(n11384), .Y(n10695) );
ADDFHX2TS U4202 ( .A(n5584), .B(n5585), .CI(n5583), .CO(n5580), .S(n5750) );
NOR2X1TS U4203 ( .A(n2049), .B(n10486), .Y(n10488) );
INVX4TS U4204 ( .A(n1357), .Y(n12219) );
OR2X2TS U4205 ( .A(n6782), .B(n6760), .Y(n9695) );
AOI21X4TS U4206 ( .A0(n8725), .A1(n7726), .B0(n1393), .Y(n9212) );
NAND2X2TS U4207 ( .A(n6782), .B(n6760), .Y(n9694) );
BUFX8TS U4208 ( .A(n11254), .Y(n11249) );
ADDFHX2TS U4209 ( .A(n4560), .B(n4558), .CI(n4559), .CO(n4590), .S(n4570) );
NAND2X1TS U4210 ( .A(n10649), .B(n10650), .Y(n9208) );
BUFX8TS U4211 ( .A(n11250), .Y(n10340) );
OR2X6TS U4212 ( .A(n7744), .B(n1130), .Y(n10669) );
NOR2X1TS U4213 ( .A(n2049), .B(n11039), .Y(n11041) );
BUFX8TS U4214 ( .A(n11250), .Y(n10341) );
NOR2X1TS U4215 ( .A(n2049), .B(n11327), .Y(n11044) );
BUFX8TS U4216 ( .A(n10466), .Y(n11324) );
NOR2X1TS U4217 ( .A(n11328), .B(n11053), .Y(n11055) );
BUFX8TS U4218 ( .A(n11250), .Y(n11292) );
NOR2X1TS U4219 ( .A(n2049), .B(n11047), .Y(n10495) );
NOR2X1TS U4220 ( .A(n2049), .B(n10497), .Y(n10491) );
INVX2TS U4221 ( .A(n6782), .Y(n6809) );
ADDFHX2TS U4222 ( .A(n5230), .B(n5229), .CI(n5228), .CO(n5266), .S(n5227) );
MX2X4TS U4223 ( .A(n9680), .B(n12244), .S0(n9731), .Y(n11805) );
NAND2X6TS U4224 ( .A(n3922), .B(n4357), .Y(n4356) );
NOR2X4TS U4225 ( .A(n10717), .B(FSM_selector_C), .Y(n8793) );
NAND2X6TS U4226 ( .A(n1336), .B(n1337), .Y(n3437) );
MX2X2TS U4227 ( .A(n9713), .B(n11947), .S0(n9724), .Y(n1447) );
ADDFHX2TS U4228 ( .A(n7547), .B(n7545), .CI(n7546), .CO(n7579), .S(n7551) );
INVX2TS U4229 ( .A(n10558), .Y(n10583) );
NAND3X4TS U4230 ( .A(n1766), .B(n1765), .C(n1767), .Y(n3860) );
MXI2X4TS U4231 ( .A(n9676), .B(n11787), .S0(n10293), .Y(n651) );
MXI2X4TS U4232 ( .A(n9699), .B(n11906), .S0(n9718), .Y(n677) );
MXI2X4TS U4233 ( .A(n9677), .B(n11911), .S0(n10293), .Y(n650) );
INVX3TS U4234 ( .A(n6759), .Y(n2852) );
MXI2X4TS U4235 ( .A(n9701), .B(n11920), .S0(n9731), .Y(n660) );
XNOR2X1TS U4236 ( .A(n9161), .B(n9160), .Y(n9162) );
MXI2X4TS U4237 ( .A(n9673), .B(n11808), .S0(n10293), .Y(n653) );
INVX2TS U4238 ( .A(n10602), .Y(n10604) );
MXI2X4TS U4239 ( .A(n10274), .B(n11915), .S0(n11153), .Y(n609) );
INVX2TS U4240 ( .A(n10591), .Y(n10587) );
XNOR2X1TS U4241 ( .A(n666), .B(n665), .Y(n11497) );
INVX2TS U4242 ( .A(n10607), .Y(n10608) );
OAI21X1TS U4243 ( .A0(n10577), .A1(n10603), .B0(n10578), .Y(n10524) );
INVX4TS U4244 ( .A(n3157), .Y(n1932) );
MXI2X4TS U4245 ( .A(n3327), .B(n11908), .S0(n10299), .Y(n587) );
BUFX6TS U4246 ( .A(n11254), .Y(n10673) );
NOR2X4TS U4247 ( .A(n10544), .B(n10543), .Y(n10549) );
INVX2TS U4248 ( .A(n8725), .Y(n8731) );
MXI2X4TS U4249 ( .A(n9732), .B(n11788), .S0(n9731), .Y(n9733) );
NOR2X4TS U4250 ( .A(n10558), .B(n10560), .Y(n10566) );
NAND2X2TS U4251 ( .A(n10539), .B(n10538), .Y(n10568) );
MXI2X4TS U4252 ( .A(n9681), .B(n11944), .S0(n9718), .Y(n9682) );
BUFX16TS U4253 ( .A(n4350), .Y(n8931) );
BUFX20TS U4254 ( .A(n10259), .Y(n10293) );
NAND2X2TS U4255 ( .A(n7740), .B(n1155), .Y(n10652) );
INVX4TS U4256 ( .A(n6741), .Y(n6754) );
INVX2TS U4257 ( .A(n10850), .Y(n9345) );
BUFX20TS U4258 ( .A(n10259), .Y(n10310) );
BUFX20TS U4259 ( .A(n11139), .Y(n10299) );
BUFX20TS U4260 ( .A(n10259), .Y(n10326) );
BUFX16TS U4261 ( .A(n6892), .Y(n8534) );
INVX2TS U4262 ( .A(n9223), .Y(n9224) );
INVX2TS U4263 ( .A(n7910), .Y(n7877) );
INVX2TS U4264 ( .A(n9225), .Y(n9228) );
INVX6TS U4265 ( .A(n1356), .Y(n11274) );
MXI2X4TS U4266 ( .A(n9690), .B(n12145), .S0(n11131), .Y(n665) );
NAND2X2TS U4267 ( .A(n10522), .B(n10521), .Y(n10603) );
NOR2X4TS U4268 ( .A(n10510), .B(n10509), .Y(n10591) );
AND2X2TS U4269 ( .A(n9251), .B(n9250), .Y(n2321) );
NOR2X4TS U4270 ( .A(n10520), .B(n1440), .Y(n10611) );
MXI2X4TS U4271 ( .A(n9692), .B(n11918), .S0(n11131), .Y(n9693) );
INVX2TS U4272 ( .A(n10840), .Y(n10831) );
NOR2X4TS U4273 ( .A(n11107), .B(n3333), .Y(n10507) );
ADDFHX2TS U4274 ( .A(n6830), .B(n6829), .CI(n6828), .CO(n6820), .S(n6839) );
INVX2TS U4275 ( .A(n11323), .Y(n11028) );
NOR2X8TS U4276 ( .A(n11293), .B(n10339), .Y(n11250) );
INVX2TS U4277 ( .A(n11087), .Y(n10432) );
INVX12TS U4278 ( .A(n2032), .Y(n2033) );
INVX12TS U4279 ( .A(n1871), .Y(n2034) );
NAND2X1TS U4280 ( .A(n10419), .B(n11271), .Y(n10404) );
ADDFHX2TS U4281 ( .A(n7287), .B(n7286), .CI(n7285), .CO(n7988), .S(n8036) );
BUFX20TS U4282 ( .A(n10259), .Y(n9731) );
BUFX20TS U4283 ( .A(n10259), .Y(n11167) );
BUFX20TS U4284 ( .A(n10259), .Y(n11153) );
NOR2X1TS U4285 ( .A(n11199), .B(n11198), .Y(n11241) );
NAND2X4TS U4286 ( .A(n10430), .B(n10429), .Y(n10466) );
CMPR22X2TS U4287 ( .A(n5587), .B(n5586), .CO(n5583), .S(n5728) );
NAND2X2TS U4288 ( .A(n10939), .B(n9377), .Y(n10840) );
INVX12TS U4289 ( .A(n1431), .Y(n11293) );
BUFX8TS U4290 ( .A(n5379), .Y(n1224) );
NOR2X1TS U4291 ( .A(n11032), .B(n10481), .Y(n10482) );
INVX2TS U4292 ( .A(n11184), .Y(n6845) );
NOR2X1TS U4293 ( .A(n11212), .B(n11211), .Y(n11240) );
INVX2TS U4294 ( .A(n1431), .Y(n11295) );
NAND2X6TS U4295 ( .A(n1627), .B(n1628), .Y(n5952) );
INVX2TS U4296 ( .A(n7771), .Y(n7763) );
INVX6TS U4297 ( .A(n1532), .Y(n1626) );
NAND2X2TS U4298 ( .A(n7735), .B(n11391), .Y(n9233) );
AOI21X2TS U4299 ( .A0(n9191), .A1(n1118), .B0(n1190), .Y(n9188) );
BUFX12TS U4300 ( .A(n9688), .Y(n11131) );
XNOR2X1TS U4301 ( .A(n9191), .B(n9190), .Y(n9192) );
OR2X4TS U4302 ( .A(n6813), .B(n6812), .Y(n6789) );
INVX1TS U4303 ( .A(n9213), .Y(n9215) );
AND4X2TS U4304 ( .A(n9243), .B(n9242), .C(n2131), .D(n2000), .Y(n9251) );
BUFX12TS U4305 ( .A(n1357), .Y(n1021) );
INVX4TS U4306 ( .A(n3606), .Y(n2969) );
NAND2X1TS U4307 ( .A(n11242), .B(n11802), .Y(n710) );
NAND2X4TS U4308 ( .A(n11185), .B(n11184), .Y(n11186) );
NAND2X6TS U4309 ( .A(n2333), .B(n2332), .Y(n3546) );
INVX8TS U4310 ( .A(n1877), .Y(n1878) );
NOR2X1TS U4311 ( .A(n11032), .B(n10449), .Y(n10450) );
NOR2X2TS U4312 ( .A(n11039), .B(n10428), .Y(n10430) );
BUFX3TS U4313 ( .A(n4031), .Y(n1043) );
NAND2X2TS U4314 ( .A(n7734), .B(n11394), .Y(n9226) );
BUFX6TS U4315 ( .A(n3835), .Y(n1615) );
INVX12TS U4316 ( .A(n8552), .Y(n1022) );
INVX3TS U4317 ( .A(n9736), .Y(n6833) );
CLKBUFX3TS U4318 ( .A(n9664), .Y(n11981) );
NOR2X1TS U4319 ( .A(n11237), .B(n11236), .Y(n11238) );
INVX2TS U4320 ( .A(n11082), .Y(n10455) );
NAND2X1TS U4321 ( .A(n11082), .B(n11253), .Y(n11083) );
NAND2X4TS U4322 ( .A(n11082), .B(n10438), .Y(n10477) );
NAND2X1TS U4323 ( .A(n11093), .B(n11273), .Y(n11094) );
NOR2X1TS U4324 ( .A(n10372), .B(n10382), .Y(n10364) );
NAND2X2TS U4325 ( .A(n7662), .B(n7661), .Y(n7663) );
NOR2X1TS U4326 ( .A(n10347), .B(n11314), .Y(n10348) );
NOR2X1TS U4327 ( .A(n11314), .B(n10351), .Y(n10343) );
INVX2TS U4328 ( .A(n7641), .Y(n7630) );
NAND2X4TS U4329 ( .A(n10493), .B(n10379), .Y(n11039) );
INVX3TS U4330 ( .A(n3602), .Y(n3558) );
NOR2X1TS U4331 ( .A(n11224), .B(n11223), .Y(n11239) );
INVX8TS U4332 ( .A(n1934), .Y(n1539) );
INVX2TS U4333 ( .A(n3584), .Y(n3585) );
NAND2X1TS U4334 ( .A(n10498), .B(n11244), .Y(n10499) );
NOR2X1TS U4335 ( .A(n11175), .B(zero_flag), .Y(n12382) );
NOR2X1TS U4336 ( .A(n11314), .B(n11889), .Y(n11065) );
INVX12TS U4337 ( .A(n2657), .Y(n4070) );
NAND2X6TS U4338 ( .A(n3229), .B(n3373), .Y(n3375) );
NAND2X4TS U4339 ( .A(n1412), .B(n5345), .Y(n11185) );
XOR2X2TS U4340 ( .A(n3364), .B(DP_OP_168J26_122_4811_n3214), .Y(n3365) );
BUFX16TS U4341 ( .A(n3651), .Y(n7997) );
NAND2X6TS U4342 ( .A(n1404), .B(n3016), .Y(n3015) );
AND2X6TS U4343 ( .A(n7665), .B(n7625), .Y(n7626) );
NOR2X1TS U4344 ( .A(n8732), .B(n8730), .Y(n7726) );
INVX2TS U4345 ( .A(n9255), .Y(n10737) );
INVX2TS U4346 ( .A(n10329), .Y(ready) );
INVX4TS U4347 ( .A(n7350), .Y(n2337) );
INVX2TS U4348 ( .A(n7674), .Y(n7676) );
NAND2X2TS U4349 ( .A(n7717), .B(n11396), .Y(n9144) );
NAND2X4TS U4350 ( .A(n3915), .B(DP_OP_168J26_122_4811_n3219), .Y(n3635) );
NAND2X2TS U4351 ( .A(n3754), .B(n3753), .Y(n1371) );
NOR2X4TS U4352 ( .A(n7725), .B(n1152), .Y(n8732) );
NAND2X2TS U4353 ( .A(n7725), .B(n1152), .Y(n8733) );
INVX2TS U4354 ( .A(n7258), .Y(n7282) );
INVX2TS U4355 ( .A(n4534), .Y(n3977) );
INVX2TS U4356 ( .A(n10352), .Y(n11314) );
INVX2TS U4357 ( .A(n7683), .Y(n7685) );
NOR2X4TS U4358 ( .A(n7724), .B(n1132), .Y(n8730) );
NAND2X6TS U4359 ( .A(n3650), .B(DP_OP_168J26_122_4811_n6609), .Y(n3651) );
NAND2X4TS U4360 ( .A(DP_OP_168J26_122_4811_n3215), .B(n3360), .Y(n3361) );
BUFX12TS U4361 ( .A(n4067), .Y(n8612) );
INVX2TS U4362 ( .A(n11183), .Y(n9341) );
INVX2TS U4363 ( .A(n7659), .Y(n7656) );
INVX12TS U4364 ( .A(n6086), .Y(n1937) );
INVX2TS U4365 ( .A(n7372), .Y(n7355) );
OAI21X1TS U4366 ( .A0(n9201), .A1(n11404), .B0(n11405), .Y(n9199) );
NAND2X8TS U4367 ( .A(n3330), .B(n10950), .Y(n9255) );
INVX12TS U4368 ( .A(n1808), .Y(n1868) );
NAND2X6TS U4369 ( .A(n1094), .B(n1093), .Y(n3610) );
OAI21X1TS U4370 ( .A0(FSM_selector_B[0]), .A1(n3335), .B0(n10531), .Y(n3336)
);
AND2X4TS U4371 ( .A(n7777), .B(n1351), .Y(n2198) );
INVX2TS U4372 ( .A(n2275), .Y(n3622) );
OAI21X1TS U4373 ( .A0(n11136), .A1(underflow_flag), .B0(n11135), .Y(n11137)
);
NAND2X4TS U4374 ( .A(n10920), .B(n7921), .Y(n9358) );
NOR2X1TS U4375 ( .A(n10950), .B(FS_Module_state_reg[3]), .Y(n10951) );
OAI21X1TS U4376 ( .A0(n7830), .A1(n11774), .B0(n1126), .Y(n7831) );
BUFX16TS U4377 ( .A(n4063), .Y(n6823) );
NOR2X1TS U4378 ( .A(n11031), .B(n10473), .Y(n10474) );
CLKINVX2TS U4379 ( .A(n11092), .Y(n11093) );
NOR2X1TS U4380 ( .A(n10437), .B(n10436), .Y(n10438) );
NOR2X1TS U4381 ( .A(n10425), .B(n10424), .Y(n10426) );
NOR2X1TS U4382 ( .A(n10413), .B(n10416), .Y(n10408) );
NAND2X4TS U4383 ( .A(n9735), .B(n9734), .Y(n12395) );
INVX6TS U4384 ( .A(n2605), .Y(n3369) );
INVX2TS U4385 ( .A(n11031), .Y(n10448) );
CLKBUFX3TS U4386 ( .A(n12226), .Y(n11984) );
OR2X4TS U4387 ( .A(n7772), .B(n7776), .Y(n1351) );
NAND2X4TS U4388 ( .A(n1706), .B(n2609), .Y(n2508) );
INVX1TS U4389 ( .A(n10351), .Y(n10346) );
INVX2TS U4390 ( .A(n7998), .Y(n8045) );
INVX2TS U4391 ( .A(n4827), .Y(n2401) );
INVX2TS U4392 ( .A(n9355), .Y(n9343) );
OAI21X1TS U4393 ( .A0(n11819), .A1(n1874), .B0(n10531), .Y(n10503) );
CLKAND2X2TS U4394 ( .A(n9245), .B(n9244), .Y(n9250) );
OAI21X1TS U4395 ( .A0(n1874), .A1(n11818), .B0(n10531), .Y(n10504) );
BUFX16TS U4396 ( .A(n4822), .Y(n4984) );
OAI21X1TS U4397 ( .A0(FSM_selector_B[1]), .A1(n11797), .B0(n10531), .Y(
n10515) );
INVX1TS U4398 ( .A(n11134), .Y(n11136) );
BUFX16TS U4399 ( .A(n3047), .Y(n2390) );
INVX2TS U4400 ( .A(n11267), .Y(n11070) );
NAND2X6TS U4401 ( .A(n8013), .B(DP_OP_168J26_122_4811_n6584), .Y(n3645) );
INVX2TS U4402 ( .A(n3366), .Y(n3367) );
NAND2X4TS U4403 ( .A(n3783), .B(n3782), .Y(n3999) );
INVX4TS U4404 ( .A(n3991), .Y(n3992) );
NAND2X2TS U4405 ( .A(n10342), .B(n11316), .Y(n10352) );
NOR2X2TS U4406 ( .A(n10351), .B(n10350), .Y(n10353) );
INVX2TS U4407 ( .A(Sgf_operation_ODD1_Q_left[0]), .Y(n9340) );
NOR2X4TS U4408 ( .A(n10361), .B(n10360), .Y(n10384) );
INVX2TS U4409 ( .A(n11316), .Y(n11331) );
NOR2X1TS U4410 ( .A(n10361), .B(n11885), .Y(n10354) );
INVX1TS U4411 ( .A(n10361), .Y(n10357) );
INVX1TS U4412 ( .A(n10382), .Y(n10370) );
NOR2X1TS U4413 ( .A(n9378), .B(n1161), .Y(n9356) );
NOR2X2TS U4414 ( .A(n9355), .B(n9354), .Y(n9377) );
INVX2TS U4415 ( .A(n11275), .Y(n10421) );
NAND2X4TS U4416 ( .A(n3576), .B(n3575), .Y(n3917) );
INVX8TS U4417 ( .A(n4822), .Y(n2023) );
INVX2TS U4418 ( .A(n11282), .Y(n10481) );
OAI21X1TS U4419 ( .A0(FSM_selector_B[1]), .A1(n11790), .B0(n10531), .Y(
n10517) );
INVX2TS U4420 ( .A(n3572), .Y(n3574) );
NAND2X1TS U4421 ( .A(n11278), .B(n11283), .Y(n10473) );
OAI21X1TS U4422 ( .A0(FSM_selector_B[1]), .A1(n11792), .B0(n10531), .Y(
n10528) );
OAI21X1TS U4423 ( .A0(n9182), .A1(n1203), .B0(n11412), .Y(n7707) );
INVX2TS U4424 ( .A(n10886), .Y(n10887) );
CLKAND2X2TS U4425 ( .A(n11956), .B(n2116), .Y(n2117) );
NAND2X6TS U4426 ( .A(n3317), .B(n2930), .Y(n3754) );
INVX2TS U4427 ( .A(n7643), .Y(n7633) );
INVX2TS U4428 ( .A(n7693), .Y(n7694) );
NAND2X2TS U4429 ( .A(n11255), .B(n11256), .Y(n11046) );
INVX2TS U4430 ( .A(n7837), .Y(n7650) );
INVX2TS U4431 ( .A(n7750), .Y(n7691) );
OAI21X1TS U4432 ( .A0(n1874), .A1(n11789), .B0(n10531), .Y(n10518) );
NAND2X1TS U4433 ( .A(n11269), .B(n11260), .Y(n10424) );
INVX2TS U4434 ( .A(n9177), .Y(n9179) );
INVX12TS U4435 ( .A(n782), .Y(n7479) );
INVX2TS U4436 ( .A(n7752), .Y(n7753) );
OAI21X1TS U4437 ( .A0(n1874), .A1(n11801), .B0(n10531), .Y(n10529) );
NOR2X1TS U4438 ( .A(n11099), .B(FS_Module_state_reg[1]), .Y(n10322) );
INVX12TS U4439 ( .A(n3395), .Y(n1025) );
OAI21X1TS U4440 ( .A0(n1874), .A1(n11800), .B0(n10531), .Y(n10532) );
INVX2TS U4441 ( .A(n7776), .Y(n7778) );
OAI21X1TS U4442 ( .A0(FSM_selector_B[1]), .A1(n11791), .B0(n10531), .Y(
n10516) );
NOR2X1TS U4443 ( .A(n1874), .B(Op_MY[52]), .Y(n3335) );
NAND3X4TS U4444 ( .A(n12007), .B(n12006), .C(n12005), .Y(n11244) );
INVX2TS U4445 ( .A(n1284), .Y(n1285) );
NAND2X2TS U4446 ( .A(Sgf_normalized_result[3]), .B(Sgf_normalized_result[2]),
.Y(n11316) );
NOR2X1TS U4447 ( .A(Sgf_normalized_result[4]), .B(Sgf_normalized_result[5]),
.Y(n10342) );
NAND2X2TS U4448 ( .A(n1169), .B(n11607), .Y(n7790) );
NAND2X2TS U4449 ( .A(Sgf_normalized_result[6]), .B(Sgf_normalized_result[7]),
.Y(n10351) );
NOR2X1TS U4450 ( .A(n11887), .B(FS_Module_state_reg[1]), .Y(n10952) );
NOR4X1TS U4451 ( .A(P_Sgf[3]), .B(P_Sgf[1]), .C(P_Sgf[2]), .D(P_Sgf[0]), .Y(
n9248) );
NOR2X4TS U4452 ( .A(exp_oper_result[11]), .B(Exp_module_Overflow_flag_A),
.Y(n11135) );
BUFX16TS U4453 ( .A(n3312), .Y(n1221) );
INVX8TS U4454 ( .A(n1717), .Y(n1718) );
NAND2X2TS U4455 ( .A(n11424), .B(n11425), .Y(n9355) );
AND2X2TS U4456 ( .A(n1199), .B(n1165), .Y(n7909) );
NAND2X2TS U4457 ( .A(n11430), .B(n11431), .Y(n9378) );
INVX12TS U4458 ( .A(DP_OP_168J26_122_4811_n8479), .Y(n3085) );
NAND2X6TS U4459 ( .A(DP_OP_168J26_122_4811_n6617), .B(
DP_OP_168J26_122_4811_n6589), .Y(n3648) );
OAI21X2TS U4460 ( .A0(n11413), .A1(n11414), .B0(n11415), .Y(n9193) );
NOR4X1TS U4461 ( .A(P_Sgf[10]), .B(P_Sgf[11]), .C(P_Sgf[9]), .D(P_Sgf[8]),
.Y(n9245) );
NOR2X4TS U4462 ( .A(n1119), .B(n1151), .Y(n9175) );
NAND2X2TS U4463 ( .A(n11426), .B(n11427), .Y(n10886) );
NAND2X4TS U4464 ( .A(n3310), .B(DP_OP_168J26_122_4811_n3607), .Y(n3246) );
NOR2X2TS U4465 ( .A(n1226), .B(n1405), .Y(Sgf_operation_ODD1_Q_left[0]) );
NAND2X1TS U4466 ( .A(n1216), .B(n12204), .Y(n2229) );
BUFX16TS U4467 ( .A(DP_OP_168J26_122_4811_n8459), .Y(n7488) );
AND4X2TS U4468 ( .A(n11930), .B(n11787), .C(n11808), .D(n12149), .Y(n11233)
);
NAND3X4TS U4469 ( .A(n12061), .B(n12060), .C(n12059), .Y(n11258) );
NAND3X4TS U4470 ( .A(n12025), .B(n12024), .C(n12023), .Y(n11269) );
NAND4BX1TS U4471 ( .AN(n12210), .B(n12147), .C(n11943), .D(n12148), .Y(
n11190) );
BUFX16TS U4472 ( .A(DP_OP_168J26_122_4811_n8245), .Y(n2323) );
BUFX16TS U4473 ( .A(n11526), .Y(n1223) );
NAND2BX2TS U4474 ( .AN(n1205), .B(n12174), .Y(n8833) );
INVX6TS U4475 ( .A(n1873), .Y(n1874) );
NAND2X4TS U4476 ( .A(DP_OP_168J26_122_4811_n8463), .B(
DP_OP_168J26_122_4811_n8488), .Y(n3630) );
INVX6TS U4477 ( .A(n1703), .Y(n1704) );
BUFX16TS U4478 ( .A(n1242), .Y(n7442) );
INVX2TS U4479 ( .A(Add_result[10]), .Y(n10759) );
NAND2BX2TS U4480 ( .AN(n1210), .B(n12207), .Y(n8838) );
NAND2BX2TS U4481 ( .AN(n1210), .B(n12189), .Y(n8813) );
NAND2BX2TS U4482 ( .AN(n1193), .B(n12190), .Y(n8823) );
NAND3X4TS U4483 ( .A(n12070), .B(n12069), .C(n12068), .Y(n11271) );
AND4X2TS U4484 ( .A(n11794), .B(n12136), .C(n11816), .D(n11949), .Y(n11220)
);
INVX2TS U4485 ( .A(n11751), .Y(n3368) );
INVX2TS U4486 ( .A(n11802), .Y(n1851) );
NAND3X4TS U4487 ( .A(n12045), .B(n12044), .C(n12043), .Y(n11277) );
NAND3X4TS U4488 ( .A(n12052), .B(n12051), .C(n12050), .Y(n11255) );
NAND4BBX1TS U4489 ( .AN(Op_MY[10]), .BN(Op_MY[14]), .C(n12248), .D(n12247),
.Y(n11200) );
NAND3X4TS U4490 ( .A(n12097), .B(n12096), .C(n12095), .Y(n11253) );
NAND2X2TS U4491 ( .A(n11748), .B(DP_OP_168J26_122_4811_n3520), .Y(n3343) );
INVX2TS U4492 ( .A(n11339), .Y(n11214) );
CLKBUFX3TS U4493 ( .A(n12394), .Y(n9663) );
INVX2TS U4494 ( .A(Data_MX[42]), .Y(n9714) );
NAND2X1TS U4495 ( .A(round_mode[1]), .B(round_mode[0]), .Y(n9253) );
INVX2TS U4496 ( .A(Data_MX[48]), .Y(n9702) );
INVX2TS U4497 ( .A(Data_MX[50]), .Y(n9667) );
INVX2TS U4498 ( .A(Data_MX[43]), .Y(n3340) );
INVX2TS U4499 ( .A(Data_MY[9]), .Y(n10252) );
INVX2TS U4500 ( .A(Data_MX[27]), .Y(n9672) );
INVX2TS U4501 ( .A(Data_MX[51]), .Y(n9665) );
NAND2X8TS U4502 ( .A(n3779), .B(n996), .Y(n2244) );
OAI22X4TS U4503 ( .A0(n6474), .A1(n1968), .B0(n5927), .B1(n8629), .Y(n6484)
);
OAI21X4TS U4504 ( .A0(n8497), .A1(n8496), .B0(n8495), .Y(n2412) );
NAND2X8TS U4505 ( .A(n3377), .B(n3376), .Y(n2169) );
OAI22X2TS U4506 ( .A0(n4645), .A1(n1987), .B0(n4732), .B1(n2356), .Y(n4699)
);
NOR2X6TS U4507 ( .A(n7421), .B(n7420), .Y(n10035) );
BUFX6TS U4508 ( .A(n7875), .Y(n1030) );
INVX4TS U4509 ( .A(n7589), .Y(n7111) );
OAI2BB1X4TS U4510 ( .A0N(n5458), .A1N(n1596), .B0(n1594), .Y(n1676) );
ADDFHX4TS U4511 ( .A(n4009), .B(n4008), .CI(n4007), .CO(n4337), .S(n9772) );
AOI21X4TS U4512 ( .A0(n7913), .A1(n1199), .B0(n7911), .Y(n7906) );
OAI22X4TS U4513 ( .A0(n1878), .A1(n7097), .B0(n2030), .B1(n7096), .Y(n7106)
);
XNOR2X4TS U4514 ( .A(n2093), .B(DP_OP_168J26_122_4811_n6559), .Y(n7053) );
NOR2BX2TS U4515 ( .AN(n10863), .B(n10862), .Y(n10865) );
XOR2X4TS U4516 ( .A(n2430), .B(n7255), .Y(n4228) );
OAI22X4TS U4517 ( .A0(n6069), .A1(n2521), .B0(n2450), .B1(n6067), .Y(n6103)
);
OAI22X4TS U4518 ( .A0(n4115), .A1(n6178), .B0(n6040), .B1(n3893), .Y(n4109)
);
XOR2X4TS U4519 ( .A(n2017), .B(n1271), .Y(n3893) );
XNOR2X4TS U4520 ( .A(n1707), .B(n9856), .Y(n2315) );
OAI22X4TS U4521 ( .A0(n6087), .A1(n5569), .B0(n1938), .B1(n5685), .Y(n5646)
);
ADDFHX4TS U4522 ( .A(n5647), .B(n5646), .CI(n5645), .CO(n5890), .S(n5639) );
INVX8TS U4523 ( .A(n8554), .Y(n8598) );
INVX6TS U4524 ( .A(Sgf_operation_ODD1_Q_left[37]), .Y(add_x_19_n239) );
NAND2X8TS U4525 ( .A(n1559), .B(n1561), .Y(n1032) );
NAND2X4TS U4526 ( .A(n11760), .B(n9982), .Y(DP_OP_168J26_122_4811_n107) );
NAND2X4TS U4527 ( .A(n9032), .B(n9033), .Y(n9982) );
INVX6TS U4528 ( .A(n5180), .Y(n1941) );
INVX6TS U4529 ( .A(n4239), .Y(n1538) );
BUFX6TS U4530 ( .A(DP_OP_168J26_122_4811_n8479), .Y(n1034) );
OAI21X4TS U4531 ( .A0(n10143), .A1(n10162), .B0(n10144), .Y(n10133) );
OAI22X4TS U4532 ( .A0(n5663), .A1(n838), .B0(n1236), .B1(n1911), .Y(n5885)
);
XNOR2X4TS U4533 ( .A(n3085), .B(n7024), .Y(n5303) );
OAI22X4TS U4534 ( .A0(n4557), .A1(n1989), .B0(n3981), .B1(n8022), .Y(n4551)
);
XNOR2X4TS U4535 ( .A(n2527), .B(n1706), .Y(n4557) );
OAI22X2TS U4536 ( .A0(n4004), .A1(n8908), .B0(n4065), .B1(n9755), .Y(n4301)
);
XNOR2X2TS U4537 ( .A(n4003), .B(n8508), .Y(n6460) );
OR2X8TS U4538 ( .A(n3481), .B(n7491), .Y(n1313) );
BUFX6TS U4539 ( .A(DP_OP_168J26_122_4811_n6794), .Y(n1035) );
BUFX8TS U4540 ( .A(n2818), .Y(n2815) );
OAI2BB2X4TS U4541 ( .B0(n4071), .B1(n8908), .A0N(n2469), .A1N(n3176), .Y(
n4098) );
XOR2X4TS U4542 ( .A(n2814), .B(n4003), .Y(n8535) );
XOR2X4TS U4543 ( .A(n2021), .B(n2814), .Y(n8578) );
XNOR2X4TS U4544 ( .A(n1028), .B(n1036), .Y(n4259) );
XOR2X4TS U4545 ( .A(n1565), .B(n2814), .Y(n4365) );
BUFX16TS U4546 ( .A(n8550), .Y(n1037) );
XOR2X4TS U4547 ( .A(n8550), .B(n1038), .Y(n8065) );
XOR2X4TS U4548 ( .A(n1037), .B(n5496), .Y(n8951) );
XOR2X4TS U4549 ( .A(n1037), .B(n1558), .Y(n1096) );
XOR2X4TS U4550 ( .A(n1037), .B(n1039), .Y(n8912) );
XNOR2X4TS U4551 ( .A(n3360), .B(DP_OP_168J26_122_4811_n3215), .Y(n4484) );
XNOR2X4TS U4552 ( .A(n1341), .B(n1042), .Y(n2755) );
OAI22X4TS U4553 ( .A0(n3842), .A1(n981), .B0(n975), .B1(n4023), .Y(n4034) );
OAI22X4TS U4554 ( .A0(n5316), .A1(n5318), .B0(n979), .B1(n4225), .Y(n5397)
);
OAI22X4TS U4555 ( .A0(n5318), .A1(n4856), .B0(n4862), .B1(n980), .Y(n4866)
);
OAI22X4TS U4556 ( .A0(n981), .A1(n5159), .B0(n4862), .B1(n5318), .Y(n5138)
);
OAI22X4TS U4557 ( .A0(n8005), .A1(n980), .B0(n5318), .B1(n8006), .Y(n8050)
);
OAI22X4TS U4558 ( .A0(n2066), .A1(n5159), .B0(n5158), .B1(n980), .Y(n5163)
);
OAI22X4TS U4559 ( .A0(n2066), .A1(n3094), .B0(n980), .B1(n4913), .Y(n4945)
);
CLKBUFX3TS U4560 ( .A(n4030), .Y(n1045) );
XOR2X4TS U4561 ( .A(n1046), .B(n910), .Y(n5387) );
XOR2X4TS U4562 ( .A(n1049), .B(n1232), .Y(n1048) );
XOR2X4TS U4563 ( .A(n4235), .B(n4234), .Y(n1046) );
OAI22X4TS U4564 ( .A0(n3850), .A1(n1958), .B0(n2071), .B1(n4027), .Y(n1232)
);
XOR2X4TS U4565 ( .A(n4031), .B(n4030), .Y(n1049) );
OAI22X4TS U4566 ( .A0(n1543), .A1(n2568), .B0(n4020), .B1(n1981), .Y(n4030)
);
OAI22X4TS U4567 ( .A0(n4021), .A1(n1934), .B0(n3849), .B1(n1991), .Y(n4031)
);
XNOR2X4TS U4568 ( .A(n5468), .B(n1051), .Y(n1050) );
XNOR2X4TS U4569 ( .A(n9832), .B(n9833), .Y(n1051) );
NAND2X8TS U4570 ( .A(n1053), .B(n1052), .Y(n5468) );
OAI21X4TS U4571 ( .A0(n5364), .A1(n5365), .B0(n5363), .Y(n1053) );
INVX12TS U4572 ( .A(n2902), .Y(n2388) );
XNOR2X4TS U4573 ( .A(n1054), .B(n1371), .Y(n1585) );
AOI21X4TS U4574 ( .A0(n1497), .A1(n1004), .B0(n3755), .Y(n1054) );
NAND2X8TS U4575 ( .A(n2180), .B(n1369), .Y(n3755) );
OA21X4TS U4576 ( .A0(n3380), .A1(n1344), .B0(n3563), .Y(n1369) );
NAND2X8TS U4577 ( .A(n2361), .B(n1387), .Y(n2180) );
AOI21X4TS U4578 ( .A0(n3603), .A1(n3561), .B0(n3560), .Y(n1057) );
XNOR2X4TS U4579 ( .A(n1056), .B(n1383), .Y(n1055) );
OAI21X4TS U4580 ( .A0(n2388), .A1(n3562), .B0(n1057), .Y(n1056) );
OAI2BB1X4TS U4581 ( .A0N(n5477), .A1N(n2263), .B0(n9933), .Y(n2620) );
XOR2X4TS U4582 ( .A(n1582), .B(n1058), .Y(n4516) );
XNOR2X4TS U4583 ( .A(n2465), .B(n966), .Y(n4405) );
XOR2X4TS U4584 ( .A(n8921), .B(n1058), .Y(n4515) );
XOR2X4TS U4585 ( .A(n2936), .B(n1058), .Y(n8949) );
XOR2X4TS U4586 ( .A(n2364), .B(n1058), .Y(n7160) );
XNOR2X4TS U4587 ( .A(n2376), .B(n966), .Y(n4778) );
XNOR2X4TS U4588 ( .A(n1819), .B(n966), .Y(n8890) );
XOR2X4TS U4589 ( .A(n2505), .B(n1058), .Y(n8089) );
OAI2BB1X4TS U4590 ( .A0N(n4691), .A1N(n1061), .B0(n1060), .Y(n9915) );
OAI21X4TS U4591 ( .A0(n4691), .A1(n1061), .B0(n1066), .Y(n1060) );
XNOR2X4TS U4592 ( .A(n4691), .B(n1062), .Y(n9912) );
XOR2X4TS U4593 ( .A(n1059), .B(n6561), .Y(n1548) );
OAI21X4TS U4594 ( .A0(n1580), .A1(n4407), .B0(n4406), .Y(n1067) );
OAI22X4TS U4595 ( .A0(n4404), .A1(n2036), .B0(n4293), .B1(n9755), .Y(n4407)
);
XOR2X4TS U4596 ( .A(n9945), .B(n1577), .Y(DP_OP_168J26_122_4811_n1136) );
NOR2X8TS U4597 ( .A(n2957), .B(n10035), .Y(n3178) );
NOR2X8TS U4598 ( .A(n7422), .B(n7423), .Y(n2957) );
OAI2BB1X4TS U4599 ( .A0N(n1069), .A1N(n1068), .B0(n2899), .Y(n2907) );
XOR2X4TS U4600 ( .A(n1070), .B(n4739), .Y(n2899) );
XOR2X4TS U4601 ( .A(n4740), .B(n4741), .Y(n1070) );
XOR2X4TS U4602 ( .A(n1072), .B(n7393), .Y(n7406) );
XOR2X4TS U4603 ( .A(n7394), .B(n1073), .Y(n1072) );
XNOR2X4TS U4604 ( .A(n978), .B(n1954), .Y(n6645) );
XOR2X4TS U4605 ( .A(n4818), .B(n2910), .Y(n2909) );
OAI21X4TS U4606 ( .A0(n4741), .A1(n4740), .B0(n4739), .Y(n1075) );
NOR2X8TS U4607 ( .A(n1076), .B(n8354), .Y(n2691) );
NOR2X8TS U4608 ( .A(n994), .B(n1076), .Y(n2276) );
NAND2X8TS U4609 ( .A(n8415), .B(n5474), .Y(n1076) );
OAI2BB1X4TS U4610 ( .A0N(n9889), .A1N(n9888), .B0(n1077), .Y(n9811) );
OAI21X4TS U4611 ( .A0(n9888), .A1(n9889), .B0(n2322), .Y(n1077) );
NAND2X8TS U4612 ( .A(n1079), .B(n1078), .Y(n2322) );
NAND2X4TS U4613 ( .A(n9828), .B(n958), .Y(n1078) );
OAI21X4TS U4614 ( .A0(n958), .A1(n9828), .B0(n9827), .Y(n1079) );
XNOR2X4TS U4615 ( .A(n1080), .B(n9792), .Y(n2968) );
NAND2X8TS U4616 ( .A(n1081), .B(n1511), .Y(n1080) );
NAND2X8TS U4617 ( .A(n1515), .B(n1512), .Y(n1081) );
INVX8TS U4618 ( .A(n5469), .Y(n1515) );
NAND2X8TS U4619 ( .A(n4684), .B(n3350), .Y(n8933) );
XNOR2X4TS U4620 ( .A(n3346), .B(n3347), .Y(n1082) );
BUFX4TS U4621 ( .A(n4684), .Y(n8935) );
INVX16TS U4622 ( .A(n1085), .Y(n6150) );
BUFX20TS U4623 ( .A(n6150), .Y(n1086) );
NOR2X8TS U4624 ( .A(n6148), .B(n1087), .Y(n1085) );
XNOR2X4TS U4625 ( .A(n1682), .B(n1684), .Y(n1087) );
NAND2X4TS U4626 ( .A(n3840), .B(n3841), .Y(n1088) );
OAI21X4TS U4627 ( .A0(n3840), .A1(n3841), .B0(n3839), .Y(n1089) );
BUFX16TS U4628 ( .A(n2179), .Y(n1090) );
OAI21X4TS U4629 ( .A0(n8366), .A1(n8362), .B0(n8367), .Y(n2179) );
XOR2X4TS U4630 ( .A(n1218), .B(n3610), .Y(n1092) );
OAI21X4TS U4631 ( .A0(n2176), .A1(DP_OP_168J26_122_4811_n8518), .B0(
DP_OP_168J26_122_4811_n8544), .Y(n1094) );
XOR2X4TS U4632 ( .A(n5567), .B(n1095), .Y(n1218) );
OAI22X4TS U4633 ( .A0(n2051), .A1(n1096), .B0(n3760), .B1(n1986), .Y(n4761)
);
OAI22X4TS U4634 ( .A0(n1096), .A1(n1986), .B0(n2051), .B1(n4645), .Y(n4689)
);
NOR2X8TS U4635 ( .A(n1097), .B(n1649), .Y(n1647) );
AOI21X4TS U4636 ( .A0(n7913), .A1(n7902), .B0(n7901), .Y(n7903) );
NAND2X8TS U4637 ( .A(n1099), .B(n1098), .Y(n7913) );
OR2X8TS U4638 ( .A(n7875), .B(n7874), .Y(n1099) );
AOI21X4TS U4639 ( .A0(n7647), .A1(n7646), .B0(n7645), .Y(n7875) );
OAI22X4TS U4640 ( .A0(n4840), .A1(n2088), .B0(n1925), .B1(n1100), .Y(n4850)
);
XNOR2X4TS U4641 ( .A(n2068), .B(DP_OP_168J26_122_4811_n8482), .Y(n1100) );
XNOR2X4TS U4642 ( .A(n1102), .B(n9562), .Y(Sgf_operation_ODD1_Q_right[43])
);
OAI21X4TS U4643 ( .A0(n9559), .A1(n1468), .B0(n1103), .Y(n1102) );
XNOR2X4TS U4644 ( .A(n1108), .B(n11344), .Y(n1107) );
OAI2BB1X4TS U4645 ( .A0N(n2617), .A1N(n10801), .B0(n10800), .Y(n1108) );
INVX12TS U4646 ( .A(n3652), .Y(n2092) );
OAI22X4TS U4647 ( .A0(n7997), .A1(n3961), .B0(n4541), .B1(n1951), .Y(n4530)
);
XOR2X4TS U4648 ( .A(n3652), .B(n750), .Y(n4541) );
XOR2X4TS U4649 ( .A(n3652), .B(DP_OP_168J26_122_4811_n8480), .Y(n3961) );
NOR2X8TS U4650 ( .A(n7942), .B(n1109), .Y(n10960) );
NOR2X8TS U4651 ( .A(n9603), .B(n9609), .Y(n7943) );
NOR2X8TS U4652 ( .A(n7940), .B(n11351), .Y(n9603) );
OAI21X4TS U4653 ( .A0(n9065), .A1(n9401), .B0(n9066), .Y(n9601) );
NOR2X8TS U4654 ( .A(n7939), .B(n11358), .Y(n9065) );
XOR2X4TS U4655 ( .A(n2677), .B(n1687), .Y(n5623) );
NAND2X2TS U4656 ( .A(n9648), .B(n8343), .Y(n8345) );
OAI22X4TS U4657 ( .A0(n1866), .A1(DP_OP_168J26_122_4811_n8030), .B0(n2063),
.B1(n3397), .Y(n3409) );
INVX12TS U4658 ( .A(n2026), .Y(n2027) );
INVX8TS U4659 ( .A(n8923), .Y(n8927) );
ADDFHX4TS U4660 ( .A(n7516), .B(n7515), .CI(n7514), .CO(n7552), .S(n7510) );
OAI22X2TS U4661 ( .A0(n7271), .A1(n1806), .B0(n8009), .B1(n7259), .Y(n7286)
);
OR2X6TS U4662 ( .A(n9986), .B(n2725), .Y(DP_OP_168J26_122_4811_n130) );
XOR2X2TS U4663 ( .A(n2359), .B(n2358), .Y(n3909) );
ADDFHX4TS U4664 ( .A(n7261), .B(n7263), .CI(n7262), .CO(n7065), .S(n7987) );
OAI2BB1X4TS U4665 ( .A0N(n7064), .A1N(n7065), .B0(n2441), .Y(n7254) );
AO21X4TS U4666 ( .A0(n6087), .A1(n1938), .B0(n11779), .Y(n3532) );
OR2X6TS U4667 ( .A(n4173), .B(n6069), .Y(n1247) );
NAND2X8TS U4668 ( .A(DP_OP_168J26_122_4811_n6591), .B(
DP_OP_168J26_122_4811_n6619), .Y(n3653) );
CLKINVX12TS U4669 ( .A(DP_OP_168J26_122_4811_n3497), .Y(n3230) );
OAI22X4TS U4670 ( .A0(n6466), .A1(n2109), .B0(n6480), .B1(n8641), .Y(n6510)
);
NOR2X4TS U4671 ( .A(n2150), .B(n768), .Y(n6228) );
NOR2X4TS U4672 ( .A(n1897), .B(n768), .Y(n5953) );
XOR2X2TS U4673 ( .A(n2445), .B(n2780), .Y(n6180) );
NAND2X4TS U4674 ( .A(n2780), .B(n1454), .Y(n5722) );
NAND2X4TS U4675 ( .A(DP_OP_168J26_122_4811_n1388), .B(
DP_OP_168J26_122_4811_n1421), .Y(DP_OP_168J26_122_4811_n514) );
XNOR2X4TS U4676 ( .A(n5174), .B(DP_OP_168J26_122_4811_n8480), .Y(n3086) );
NAND2X8TS U4677 ( .A(n2821), .B(n2819), .Y(n3072) );
NAND2X4TS U4678 ( .A(n899), .B(n1671), .Y(n10061) );
XNOR2X4TS U4679 ( .A(n1111), .B(n1110), .Y(n7545) );
XOR2X4TS U4680 ( .A(n889), .B(n7521), .Y(n1111) );
BUFX6TS U4681 ( .A(n9781), .Y(n2600) );
OAI22X2TS U4682 ( .A0(DP_OP_168J26_122_4811_n6594), .A1(n800), .B0(
DP_OP_168J26_122_4811_n6608), .B1(n1221), .Y(n4603) );
XOR2X4TS U4683 ( .A(n9968), .B(n1112), .Y(n1712) );
NOR2X8TS U4684 ( .A(n5473), .B(n2831), .Y(n9287) );
XOR2X4TS U4685 ( .A(n5567), .B(n1687), .Y(n4186) );
OAI22X4TS U4686 ( .A0(n5624), .A1(n2103), .B0(n1948), .B1(n5565), .Y(n5584)
);
XNOR2X4TS U4687 ( .A(n2070), .B(n2464), .Y(n5565) );
NAND2X4TS U4688 ( .A(n1218), .B(n3610), .Y(n3346) );
XNOR2X4TS U4689 ( .A(n2069), .B(n1034), .Y(n4919) );
NAND2X4TS U4690 ( .A(DP_OP_168J26_122_4811_n984), .B(
DP_OP_168J26_122_4811_n1005), .Y(DP_OP_168J26_122_4811_n365) );
NOR2X4TS U4691 ( .A(n10955), .B(n10924), .Y(n10926) );
INVX12TS U4692 ( .A(n6382), .Y(n10114) );
ADDFHX4TS U4693 ( .A(n5613), .B(n5611), .CI(n5612), .CO(n5614), .S(n5619) );
ADDFHX4TS U4694 ( .A(n4567), .B(n4569), .CI(n4568), .CO(n4589), .S(n4582) );
ADDFHX4TS U4695 ( .A(n4537), .B(n4536), .CI(n4535), .CO(n4569), .S(n4561) );
NAND2X6TS U4696 ( .A(DP_OP_168J26_122_4811_n8486), .B(
DP_OP_168J26_122_4811_n8461), .Y(n3943) );
OAI22X4TS U4697 ( .A0(n2379), .A1(n3431), .B0(n7474), .B1(n3399), .Y(n3435)
);
NAND2X8TS U4698 ( .A(n3603), .B(n3602), .Y(n2589) );
XOR2X4TS U4699 ( .A(n1259), .B(n8539), .Y(n5497) );
BUFX12TS U4700 ( .A(n808), .Y(n1916) );
ADDFHX4TS U4701 ( .A(n4787), .B(n4786), .CI(n4785), .CO(n7455), .S(n4788) );
CLKINVX6TS U4702 ( .A(n3034), .Y(n2272) );
INVX6TS U4703 ( .A(n6377), .Y(n4340) );
OAI21X1TS U4704 ( .A0(n7752), .A1(n1157), .B0(n1116), .Y(n7615) );
NAND2X1TS U4705 ( .A(n7753), .B(n1116), .Y(n7754) );
NAND2X1TS U4706 ( .A(n7910), .B(n1117), .Y(n7880) );
AOI21X2TS U4707 ( .A0(n7913), .A1(n1117), .B0(n11554), .Y(n7879) );
NAND2X1TS U4708 ( .A(n11420), .B(n1120), .Y(n9187) );
NAND2X4TS U4709 ( .A(n1122), .B(n1201), .Y(n10929) );
NAND2X8TS U4710 ( .A(n7628), .B(n1123), .Y(n7658) );
NOR2X4TS U4711 ( .A(n1123), .B(n7628), .Y(n7659) );
NAND2X1TS U4712 ( .A(n9197), .B(n1127), .Y(n9198) );
OAI21X2TS U4713 ( .A0(n1129), .A1(n11645), .B0(n11646), .Y(n7704) );
NOR2X1TS U4714 ( .A(n10929), .B(n1133), .Y(n10930) );
CLKMX2X2TS U4715 ( .A(n9153), .B(n12126), .S0(n1139), .Y(n462) );
CLKMX2X2TS U4716 ( .A(n12111), .B(n12110), .S0(n1139), .Y(n449) );
CLKMX2X2TS U4717 ( .A(n9205), .B(n12114), .S0(n1140), .Y(n450) );
CLKMX2X2TS U4718 ( .A(n9195), .B(n12118), .S0(n1140), .Y(n453) );
CLKMX2X2TS U4719 ( .A(n9204), .B(n12115), .S0(n1141), .Y(n451) );
CLKMX2X2TS U4720 ( .A(n9202), .B(n12116), .S0(n1141), .Y(n452) );
NOR2X4TS U4721 ( .A(n1179), .B(n1147), .Y(n7644) );
NAND2X4TS U4722 ( .A(n7930), .B(n1162), .Y(n9440) );
NAND2X4TS U4723 ( .A(n7923), .B(n1164), .Y(n8809) );
NAND2X6TS U4724 ( .A(n7836), .B(n1167), .Y(n7839) );
NAND2X1TS U4725 ( .A(n7712), .B(n1171), .Y(n9158) );
AOI21X1TS U4726 ( .A0(n7856), .A1(n1173), .B0(n11578), .Y(n7857) );
NAND2X1TS U4727 ( .A(n7853), .B(n1173), .Y(n7858) );
NAND2X1TS U4728 ( .A(n7694), .B(n1174), .Y(n7695) );
NOR2X4TS U4729 ( .A(n1135), .B(n1176), .Y(n7768) );
NOR2X4TS U4730 ( .A(n7619), .B(n1177), .Y(n7757) );
NOR2X4TS U4731 ( .A(n1178), .B(n1145), .Y(n7640) );
NAND2X6TS U4732 ( .A(n1182), .B(n1180), .Y(n7866) );
NOR2X2TS U4733 ( .A(n7814), .B(n1183), .Y(n9524) );
NAND2X6TS U4734 ( .A(n7922), .B(n1184), .Y(n10772) );
NAND2X4TS U4735 ( .A(n7929), .B(n1185), .Y(n9433) );
NOR2X6TS U4736 ( .A(n7931), .B(n1187), .Y(n9420) );
NAND2X1TS U4737 ( .A(n1118), .B(n1191), .Y(n9190) );
CLKMX2X2TS U4738 ( .A(n9186), .B(n12120), .S0(n1192), .Y(n458) );
NAND2X1TS U4739 ( .A(n7910), .B(n1199), .Y(n7907) );
NAND2X2TS U4740 ( .A(n1202), .B(n11644), .Y(n7612) );
NAND2X1TS U4741 ( .A(n1202), .B(n11650), .Y(n7699) );
NAND2X1TS U4742 ( .A(n9171), .B(n1203), .Y(n9172) );
CLKMX2X2TS U4743 ( .A(n9174), .B(n12122), .S0(n1204), .Y(n457) );
MX2X4TS U4744 ( .A(n10648), .B(n12157), .S0(n1206), .Y(n474) );
CLKMX2X2TS U4745 ( .A(n9162), .B(n12124), .S0(n1206), .Y(n461) );
CLKMX2X2TS U4746 ( .A(n9169), .B(n12125), .S0(n1208), .Y(n460) );
CLKMX2X2TS U4747 ( .A(n9192), .B(n12119), .S0(n1208), .Y(n455) );
CLKMX2X2TS U4748 ( .A(n9140), .B(n12130), .S0(n1211), .Y(n463) );
CLKMX2X2TS U4749 ( .A(n9189), .B(n12121), .S0(n1211), .Y(n456) );
CLKMX2X2TS U4750 ( .A(n9164), .B(n12123), .S0(n1213), .Y(n459) );
CLKMX2X2TS U4751 ( .A(n9200), .B(n12117), .S0(n1213), .Y(n454) );
MX2X4TS U4752 ( .A(n10672), .B(n12144), .S0(n1213), .Y(n475) );
CLKMX2X2TS U4753 ( .A(n8724), .B(n12135), .S0(n1215), .Y(n468) );
CLKMX2X2TS U4754 ( .A(n8737), .B(n12132), .S0(n1215), .Y(n467) );
CLKMX2X2TS U4755 ( .A(n9148), .B(n12131), .S0(n1215), .Y(n464) );
AO21X2TS U4756 ( .A0(n2100), .A1(n7471), .B0(n1031), .Y(n7131) );
XNOR2X4TS U4757 ( .A(n1220), .B(n1284), .Y(n7447) );
XNOR2X4TS U4758 ( .A(n5567), .B(n1228), .Y(n4106) );
XOR2X4TS U4759 ( .A(n1031), .B(n11562), .Y(n3348) );
NAND2X6TS U4760 ( .A(DP_OP_168J26_122_4811_n8191), .B(n3417), .Y(n3395) );
ADDFHX4TS U4761 ( .A(n6305), .B(n6304), .CI(n6303), .CO(n6314), .S(n6333) );
ADDFHX4TS U4762 ( .A(n5644), .B(n5643), .CI(n5642), .CO(n5891), .S(n5669) );
NOR2BX2TS U4763 ( .AN(n6714), .B(n838), .Y(n5644) );
XNOR2X2TS U4764 ( .A(n7439), .B(n760), .Y(n7244) );
NOR2X6TS U4765 ( .A(n9305), .B(n8351), .Y(n3109) );
XNOR2X4TS U4766 ( .A(DP_OP_168J26_122_4811_n6641), .B(n1884), .Y(n5159) );
INVX16TS U4767 ( .A(n1591), .Y(n1454) );
ADDFHX4TS U4768 ( .A(n6956), .B(n6955), .CI(n6954), .CO(n6990), .S(n6994) );
OAI22X2TS U4769 ( .A0(n6704), .A1(n1953), .B0(n6669), .B1(n8612), .Y(n6955)
);
OA22X4TS U4770 ( .A0(n5309), .A1(n4859), .B0(n1988), .B1(n5142), .Y(n1230)
);
BUFX6TS U4771 ( .A(n2897), .Y(n1231) );
BUFX20TS U4772 ( .A(n8622), .Y(n1233) );
INVX6TS U4773 ( .A(n1801), .Y(add_x_19_n755) );
XOR2X4TS U4774 ( .A(n6988), .B(n1234), .Y(n7007) );
XOR2X4TS U4775 ( .A(n6987), .B(n6986), .Y(n1234) );
NAND2X2TS U4776 ( .A(n8799), .B(n8798), .Y(n8800) );
OAI22X4TS U4777 ( .A0(n2087), .A1(n3661), .B0(n1924), .B1(n5283), .Y(n3959)
);
OAI22X4TS U4778 ( .A0(n2088), .A1(n3662), .B0(n1925), .B1(n3661), .Y(n3741)
);
OAI22X4TS U4779 ( .A0(n1814), .A1(n4443), .B0(n2059), .B1(n4445), .Y(n4473)
);
NAND2X2TS U4780 ( .A(n4421), .B(n4420), .Y(n3193) );
NAND2X8TS U4781 ( .A(n3776), .B(n1422), .Y(n2241) );
OAI22X4TS U4782 ( .A0(n8519), .A1(n1908), .B0(n8517), .B1(n2052), .Y(n8591)
);
OAI2BB1X4TS U4783 ( .A0N(n6942), .A1N(n1235), .B0(n2997), .Y(n6995) );
OR2X4TS U4784 ( .A(n6943), .B(n6944), .Y(n1235) );
NOR2X4TS U4785 ( .A(n2711), .B(n2574), .Y(n10161) );
MXI2X4TS U4786 ( .A(n9691), .B(n11949), .S0(n11131), .Y(n670) );
OAI22X4TS U4787 ( .A0(n1914), .A1(n3396), .B0(n2059), .B1(n3405), .Y(n3444)
);
ADDFHX4TS U4788 ( .A(n4606), .B(n4605), .CI(n4607), .CO(n4681), .S(n4615) );
ADDFHX4TS U4789 ( .A(n6210), .B(n6209), .CI(n6211), .CO(n6247), .S(n6251) );
BUFX16TS U4790 ( .A(n5472), .Y(n2831) );
XNOR2X4TS U4791 ( .A(n7277), .B(n790), .Y(n3674) );
XNOR2X4TS U4792 ( .A(DP_OP_168J26_122_4811_n6776), .B(n1669), .Y(n5577) );
NOR2X4TS U4793 ( .A(n8667), .B(n8666), .Y(n2559) );
XNOR2X4TS U4794 ( .A(n1238), .B(n1241), .Y(n3650) );
XOR2X4TS U4795 ( .A(n4002), .B(n4001), .Y(n1244) );
INVX12TS U4796 ( .A(n1244), .Y(n4003) );
OAI22X2TS U4797 ( .A0(n4344), .A1(n2098), .B0(n2446), .B1(n3924), .Y(n4007)
);
OAI21X4TS U4798 ( .A0(n4282), .A1(n4283), .B0(n4281), .Y(n3243) );
OAI22X2TS U4799 ( .A0(n3677), .A1(n3821), .B0(n5304), .B1(n3694), .Y(n3806)
);
XOR2X2TS U4800 ( .A(n5408), .B(n5409), .Y(n3088) );
OAI22X2TS U4801 ( .A0(n4094), .A1(n8908), .B0(n4097), .B1(n9755), .Y(n4371)
);
NOR2BX2TS U4802 ( .AN(n6849), .B(n8908), .Y(n8538) );
XNOR2X4TS U4803 ( .A(n3449), .B(n2464), .Y(n5662) );
NOR2X6TS U4804 ( .A(n3022), .B(n2499), .Y(n10132) );
XNOR2X4TS U4805 ( .A(n1233), .B(n1245), .Y(n8671) );
XOR2X4TS U4806 ( .A(n8680), .B(n8679), .Y(n1245) );
CLKINVX12TS U4807 ( .A(n2417), .Y(n1536) );
OAI22X2TS U4808 ( .A0(DP_OP_168J26_122_4811_n5162), .A1(n12046), .B0(n2550),
.B1(n3202), .Y(n7371) );
OAI22X4TS U4809 ( .A0(n3032), .A1(n5533), .B0(n3031), .B1(n3030), .Y(n5915)
);
NOR2X4TS U4810 ( .A(n5700), .B(n5699), .Y(n3032) );
NAND2X6TS U4811 ( .A(n2476), .B(n1556), .Y(n2497) );
BUFX12TS U4812 ( .A(DP_OP_168J26_122_4811_n8187), .Y(n2448) );
NOR2X4TS U4813 ( .A(n3320), .B(n768), .Y(n6121) );
INVX16TS U4814 ( .A(n6714), .Y(n2780) );
ADDFHX4TS U4815 ( .A(n3736), .B(n3737), .CI(n3735), .CO(n3749), .S(n3722) );
XNOR2X4TS U4816 ( .A(n1249), .B(n9825), .Y(n9953) );
XNOR2X4TS U4817 ( .A(n1250), .B(n4853), .Y(n4895) );
XNOR2X4TS U4818 ( .A(n4854), .B(n4852), .Y(n1250) );
AND2X8TS U4819 ( .A(n10722), .B(n10724), .Y(n1251) );
OAI22X4TS U4820 ( .A0(n5149), .A1(n2095), .B0(n5173), .B1(n5343), .Y(n5150)
);
OAI22X4TS U4821 ( .A0(n2096), .A1(n5173), .B0(n5212), .B1(n1889), .Y(n5215)
);
CLKINVX12TS U4822 ( .A(DP_OP_168J26_122_4811_n8451), .Y(n1252) );
INVX16TS U4823 ( .A(n1252), .Y(n1253) );
NOR2X6TS U4824 ( .A(n6749), .B(n6773), .Y(n10246) );
NAND2X2TS U4825 ( .A(n6773), .B(n6749), .Y(n10247) );
OAI22X4TS U4826 ( .A0(n6174), .A1(n3528), .B0(n2450), .B1(n1804), .Y(n3540)
);
MXI2X4TS U4827 ( .A(n3329), .B(n11928), .S0(n10299), .Y(n592) );
NAND2X6TS U4828 ( .A(n2299), .B(n10118), .Y(n7960) );
OAI22X2TS U4829 ( .A0(n7477), .A1(n4459), .B0(n7474), .B1(n4794), .Y(n4785)
);
CLKINVX6TS U4830 ( .A(n8547), .Y(n8595) );
XNOR2X4TS U4831 ( .A(n1838), .B(n3085), .Y(n3074) );
OAI22X4TS U4832 ( .A0(n5950), .A1(n5651), .B0(n2043), .B1(n5864), .Y(n5880)
);
NAND2X4TS U4833 ( .A(n2540), .B(n6384), .Y(n10111) );
CLKINVX12TS U4834 ( .A(DP_OP_168J26_122_4811_n8474), .Y(n3047) );
NOR2BX2TS U4835 ( .AN(n6714), .B(n6176), .Y(n6107) );
AND2X6TS U4836 ( .A(n5982), .B(n1768), .Y(n2925) );
INVX8TS U4837 ( .A(n6373), .Y(n8451) );
ADDFHX4TS U4838 ( .A(n6246), .B(n6245), .CI(n6244), .CO(n6267), .S(n6263) );
ADDHX4TS U4839 ( .A(n6225), .B(n6224), .CO(n6249), .S(n6245) );
ADDFHX4TS U4840 ( .A(n4201), .B(n4202), .CI(n4200), .CO(n6311), .S(n6329) );
OAI22X4TS U4841 ( .A0(n5559), .A1(n1814), .B0(n3321), .B1(n2212), .Y(n5629)
);
XNOR2X4TS U4842 ( .A(n1271), .B(n763), .Y(n6008) );
INVX12TS U4843 ( .A(n1875), .Y(n1876) );
XOR2X4TS U4844 ( .A(n8539), .B(n4070), .Y(n5536) );
NAND2X4TS U4845 ( .A(n6717), .B(n6718), .Y(n10034) );
XNOR2X4TS U4846 ( .A(n7255), .B(n11767), .Y(n3692) );
INVX4TS U4847 ( .A(n7275), .Y(n7255) );
INVX6TS U4848 ( .A(n1761), .Y(n9897) );
INVX12TS U4849 ( .A(n5747), .Y(n5819) );
NAND2X2TS U4850 ( .A(n2281), .B(n4217), .Y(n1524) );
OAI2BB1X4TS U4851 ( .A0N(n6788), .A1N(n6787), .B0(n3159), .Y(n6778) );
NOR2X8TS U4852 ( .A(n6875), .B(n6874), .Y(n9491) );
INVX8TS U4853 ( .A(n6392), .Y(n4651) );
ADDFHX2TS U4854 ( .A(n3413), .B(n1229), .CI(n3412), .CO(n3427), .S(n3430) );
XNOR2X4TS U4855 ( .A(DP_OP_168J26_122_4811_n6794), .B(n1810), .Y(n4460) );
MXI2X4TS U4856 ( .A(n10254), .B(n11914), .S0(n10299), .Y(n590) );
XNOR2X4TS U4857 ( .A(n1263), .B(n5355), .Y(n2719) );
XOR2X4TS U4858 ( .A(n5356), .B(n5357), .Y(n1263) );
BUFX6TS U4859 ( .A(n5127), .Y(n2579) );
NOR2X2TS U4860 ( .A(n8228), .B(n8229), .Y(n9565) );
XOR2X4TS U4861 ( .A(n6445), .B(n1016), .Y(n2765) );
ADDFHX4TS U4862 ( .A(n5518), .B(n5519), .CI(n5517), .CO(n5522), .S(n5696) );
XOR2X4TS U4863 ( .A(DP_OP_168J26_122_4811_n8517), .B(n770), .Y(n3617) );
XNOR2X4TS U4864 ( .A(n8921), .B(n8896), .Y(n8564) );
OAI22X4TS U4865 ( .A0(n8015), .A1(n4545), .B0(n8013), .B1(n4594), .Y(n4606)
);
INVX8TS U4866 ( .A(n3601), .Y(n3559) );
ADDFHX4TS U4867 ( .A(n4758), .B(n4757), .CI(n4759), .CO(n4764), .S(n9937) );
XOR2X4TS U4868 ( .A(n1265), .B(n1266), .Y(n5914) );
XOR2X4TS U4869 ( .A(n5903), .B(n1710), .Y(n1266) );
ADDFHX4TS U4870 ( .A(n7201), .B(n7595), .CI(n2932), .CO(n7334), .S(n7210) );
XNOR2X4TS U4871 ( .A(n7275), .B(n2653), .Y(n7086) );
OAI22X2TS U4872 ( .A0(n2447), .A1(n4914), .B0(n1901), .B1(n4907), .Y(n4937)
);
BUFX16TS U4873 ( .A(n8587), .Y(n2610) );
ADDFHX4TS U4874 ( .A(n6447), .B(n6448), .CI(n6446), .CO(n6444), .S(n6551) );
CLKXOR2X4TS U4875 ( .A(n6429), .B(n2252), .Y(n6448) );
OAI22X2TS U4876 ( .A0(n6430), .A1(n2577), .B0(n6431), .B1(n8938), .Y(n6447)
);
OAI22X4TS U4877 ( .A0(n6644), .A1(n2552), .B0(n1268), .B1(n1269), .Y(n6664)
);
NAND2X4TS U4878 ( .A(n7939), .B(n11368), .Y(n9066) );
OAI21X2TS U4879 ( .A0(n2084), .A1(n10825), .B0(n10824), .Y(n10826) );
OAI22X2TS U4880 ( .A0(n8509), .A1(n1908), .B0(n8519), .B1(n2052), .Y(n8648)
);
ADDFHX4TS U4881 ( .A(n8974), .B(n8973), .CI(n8975), .S(n1272) );
ADDFHX4TS U4882 ( .A(n8916), .B(n8915), .CI(n8914), .CO(n8903), .S(n8973) );
ADDFHX2TS U4883 ( .A(n9840), .B(n9838), .CI(n9839), .CO(n9803), .S(n9858) );
NAND2X4TS U4884 ( .A(n1410), .B(n2931), .Y(n2970) );
NAND2X6TS U4885 ( .A(n959), .B(n2301), .Y(n10119) );
NAND2X6TS U4886 ( .A(n955), .B(n1669), .Y(n3621) );
XOR2X4TS U4887 ( .A(n6295), .B(n1274), .Y(n2303) );
ADDFHX4TS U4888 ( .A(n7074), .B(n7075), .CI(n7073), .CO(n7107), .S(n7076) );
XNOR2X4TS U4889 ( .A(n3449), .B(n1913), .Y(n5606) );
XNOR2X4TS U4890 ( .A(n1276), .B(n8656), .Y(n8708) );
XNOR2X4TS U4891 ( .A(n8657), .B(n8658), .Y(n1276) );
OAI22X4TS U4892 ( .A0(n5302), .A1(n4919), .B0(DP_OP_168J26_122_4811_n6618),
.B1(n4881), .Y(n4917) );
XNOR2X4TS U4893 ( .A(n2068), .B(DP_OP_168J26_122_4811_n8480), .Y(n4881) );
ADDFHX4TS U4894 ( .A(n6816), .B(n6815), .CI(n6814), .CO(n6869), .S(n6857) );
MXI2X4TS U4895 ( .A(n10286), .B(n11970), .S0(n11153), .Y(n611) );
OAI2BB1X2TS U4896 ( .A0N(n5217), .A1N(n5218), .B0(n3100), .Y(n5292) );
XNOR2X4TS U4897 ( .A(n8232), .B(n1277), .Y(n7179) );
XOR2X4TS U4898 ( .A(n7159), .B(n7588), .Y(n1277) );
ADDFHX4TS U4899 ( .A(n6869), .B(n6868), .CI(n6867), .CO(n6800), .S(n6870) );
XNOR2X2TS U4900 ( .A(n5278), .B(n1809), .Y(n5037) );
OR2X8TS U4901 ( .A(n1283), .B(n2774), .Y(n2772) );
XNOR2X4TS U4902 ( .A(n2022), .B(n2265), .Y(n6808) );
NAND2X8TS U4903 ( .A(n9983), .B(n9984), .Y(n9985) );
NOR2X4TS U4904 ( .A(n2387), .B(n788), .Y(n9579) );
NAND2X6TS U4905 ( .A(DP_OP_168J26_122_4811_n3245), .B(n3634), .Y(n3936) );
ADDFHX4TS U4906 ( .A(n4776), .B(n4775), .CI(n4774), .CO(n9097), .S(n4768) );
OAI22X4TS U4907 ( .A0(n4731), .A1(n2293), .B0(n4777), .B1(n1893), .Y(n4776)
);
OAI22X2TS U4908 ( .A0(n7171), .A1(n9457), .B0(n7192), .B1(n2050), .Y(n7206)
);
OAI22X2TS U4909 ( .A0(n3880), .A1(n6078), .B0(n6075), .B1(n2261), .Y(n6084)
);
NAND2X6TS U4910 ( .A(n1113), .B(n1511), .Y(n1280) );
NAND2X4TS U4911 ( .A(n2323), .B(n1405), .Y(n6002) );
ADDFHX4TS U4912 ( .A(n6514), .B(n6513), .CI(n6512), .CO(n6521), .S(n6519) );
NAND2X8TS U4913 ( .A(n2560), .B(n3127), .Y(n8362) );
OAI21X4TS U4914 ( .A0(DP_OP_168J26_122_4811_n8527), .A1(
DP_OP_168J26_122_4811_n8500), .B0(n1286), .Y(n3783) );
MXI2X4TS U4915 ( .A(n9715), .B(n11907), .S0(n11167), .Y(n675) );
INVX16TS U4916 ( .A(n2854), .Y(n1807) );
OAI22X2TS U4917 ( .A0(n6223), .A1(n6222), .B0(n11754), .B1(n6221), .Y(n6246)
);
NAND2X6TS U4918 ( .A(Sgf_operation_ODD1_Q_right[37]), .B(
Sgf_operation_ODD1_S_B[10]), .Y(add_x_19_n718) );
XOR2X4TS U4919 ( .A(n3997), .B(n4000), .Y(n3998) );
OAI22X4TS U4920 ( .A0(n1914), .A1(n3418), .B0(n2059), .B1(n3396), .Y(n3410)
);
ADDFHX4TS U4921 ( .A(n4436), .B(n4437), .CI(n4435), .CO(n4505), .S(n4507) );
OAI22X4TS U4922 ( .A0(n1814), .A1(n3405), .B0(n2060), .B1(n4443), .Y(n4437)
);
NOR2X6TS U4923 ( .A(n8371), .B(n3168), .Y(n2804) );
OAI21X4TS U4924 ( .A0(n6826), .A1(n6827), .B0(n6825), .Y(n3060) );
INVX8TS U4925 ( .A(n1290), .Y(n4000) );
NOR2X2TS U4926 ( .A(n1392), .B(n9588), .Y(add_x_19_n738) );
OAI21X4TS U4927 ( .A0(n2576), .A1(n9629), .B0(n3222), .Y(n3225) );
XNOR2X4TS U4928 ( .A(n3225), .B(n9490), .Y(n1392) );
OAI22X2TS U4929 ( .A0(n2222), .A1(n4581), .B0(n8009), .B1(n4597), .Y(n4602)
);
INVX12TS U4930 ( .A(n1398), .Y(n1896) );
INVX6TS U4931 ( .A(n1690), .Y(n1295) );
NAND2X4TS U4932 ( .A(n3017), .B(n3015), .Y(n3012) );
NAND3X6TS U4933 ( .A(n1404), .B(n3014), .C(n3016), .Y(n3013) );
INVX6TS U4934 ( .A(n11766), .Y(n7011) );
ADDFHX2TS U4935 ( .A(n6845), .B(n6844), .CI(n6843), .CO(n6838), .S(n6851) );
OR2X6TS U4936 ( .A(n11477), .B(n3564), .Y(n3148) );
OAI22X2TS U4937 ( .A0(n4141), .A1(n1222), .B0(n3321), .B1(n3895), .Y(n4107)
);
CLKINVX12TS U4938 ( .A(n11490), .Y(n3417) );
NOR2BX2TS U4939 ( .AN(n1859), .B(n7031), .Y(n4372) );
NAND2X2TS U4940 ( .A(n2984), .B(n6688), .Y(n2170) );
OAI22X2TS U4941 ( .A0(n2110), .A1(n5013), .B0(n5058), .B1(n5012), .Y(n5107)
);
NAND2X4TS U4942 ( .A(n5515), .B(n8616), .Y(n2715) );
OAI22X2TS U4943 ( .A0(n6165), .A1(n11754), .B0(n2184), .B1(n2029), .Y(n6169)
);
INVX2TS U4944 ( .A(n3139), .Y(n3137) );
OAI22X2TS U4945 ( .A0(n7260), .A1(n5306), .B0(n2048), .B1(n1529), .Y(n7269)
);
INVX2TS U4946 ( .A(n9658), .Y(n7399) );
OAI22X2TS U4947 ( .A0(n8541), .A1(n8948), .B0(n8442), .B1(n1886), .Y(n8562)
);
ADDFHX2TS U4948 ( .A(n7047), .B(n7046), .CI(n7045), .CO(n7081), .S(n7236) );
BUFX8TS U4949 ( .A(n5200), .Y(n2273) );
INVX2TS U4950 ( .A(n5216), .Y(n1794) );
INVX8TS U4951 ( .A(n7667), .Y(n7788) );
ADDFHX2TS U4952 ( .A(n6121), .B(n6120), .CI(n6119), .CO(n6041), .S(n6130) );
ADDFHX2TS U4953 ( .A(n7357), .B(n7356), .CI(n7355), .CO(n7373), .S(n7343) );
INVX2TS U4954 ( .A(n2805), .Y(n9290) );
INVX2TS U4955 ( .A(n8205), .Y(n2145) );
INVX2TS U4956 ( .A(n6852), .Y(n3064) );
NOR2X6TS U4957 ( .A(n8431), .B(n8435), .Y(n8376) );
NAND2X6TS U4958 ( .A(n2162), .B(n2729), .Y(n2728) );
OAI22X2TS U4959 ( .A0(n8617), .A1(n2099), .B0(n6885), .B1(n8570), .Y(n8673)
);
OAI21X2TS U4960 ( .A0(n2492), .A1(n6798), .B0(n6797), .Y(n3251) );
INVX4TS U4961 ( .A(n5477), .Y(n9934) );
NOR2X4TS U4962 ( .A(n10717), .B(n11833), .Y(n8792) );
INVX12TS U4963 ( .A(n1356), .Y(n10717) );
INVX4TS U4964 ( .A(n1356), .Y(n11247) );
NAND2X6TS U4965 ( .A(n11477), .B(n3564), .Y(n3150) );
INVX6TS U4966 ( .A(n8616), .Y(n2717) );
INVX2TS U4967 ( .A(n1027), .Y(n7292) );
INVX6TS U4968 ( .A(n3620), .Y(n4073) );
CLKINVX6TS U4969 ( .A(DP_OP_168J26_122_4811_n8513), .Y(n2609) );
NAND2X2TS U4970 ( .A(n2788), .B(n7275), .Y(n5147) );
INVX2TS U4971 ( .A(n6760), .Y(n6790) );
NAND2X2TS U4972 ( .A(n2780), .B(n2445), .Y(n6182) );
INVX2TS U4973 ( .A(n3522), .Y(n3009) );
OAI22X2TS U4974 ( .A0(n2077), .A1(n2380), .B0(n1624), .B1(n6156), .Y(n4449)
);
ADDFHX2TS U4975 ( .A(n3672), .B(n3701), .CI(n3700), .CO(n3721), .S(n3707) );
OAI22X2TS U4976 ( .A0(n7997), .A1(n3714), .B0(n3673), .B1(
DP_OP_168J26_122_4811_n6609), .Y(n3700) );
INVX6TS U4977 ( .A(n1882), .Y(n7444) );
OAI22X2TS U4978 ( .A0(n8025), .A1(n5224), .B0(n5304), .B1(n5255), .Y(n5267)
);
NAND2X4TS U4979 ( .A(n7771), .B(n7621), .Y(n7666) );
INVX2TS U4980 ( .A(n6817), .Y(n1734) );
OAI22X2TS U4981 ( .A0(n5950), .A1(n5566), .B0(n3307), .B1(n5651), .Y(n5673)
);
OAI22X2TS U4982 ( .A0(n2159), .A1(n3501), .B0(n974), .B1(n3472), .Y(n3488)
);
OAI22X2TS U4983 ( .A0(n4580), .A1(n2066), .B0(n1880), .B1(n4598), .Y(n4612)
);
OAI22X2TS U4984 ( .A0(n7492), .A1(n4460), .B0(n7491), .B1(
DP_OP_168J26_122_4811_n7949), .Y(n4798) );
OAI22X2TS U4985 ( .A0(n8022), .A1(n3674), .B0(n8020), .B1(n3649), .Y(n3704)
);
INVX2TS U4986 ( .A(n3732), .Y(n3680) );
NOR2BX2TS U4987 ( .AN(n1859), .B(n6883), .Y(n6911) );
OAI22X2TS U4988 ( .A0(n6451), .A1(n1969), .B0(n1933), .B1(n2236), .Y(n6454)
);
NOR2X2TS U4989 ( .A(n3096), .B(n3597), .Y(n3095) );
OAI22X2TS U4990 ( .A0(n7224), .A1(n1973), .B0(n7329), .B1(n2339), .Y(n7336)
);
INVX2TS U4991 ( .A(n7768), .Y(n7784) );
NAND2X4TS U4992 ( .A(n1135), .B(n1176), .Y(n7782) );
CLKINVX6TS U4993 ( .A(n2922), .Y(n2729) );
NAND2X4TS U4994 ( .A(n9639), .B(n8341), .Y(n9566) );
OAI22X2TS U4995 ( .A0(n1815), .A1(n5796), .B0(n3307), .B1(n5765), .Y(n5804)
);
OAI22X2TS U4996 ( .A0(n1822), .A1(n7354), .B0(n1951), .B1(n7368), .Y(n7370)
);
INVX2TS U4997 ( .A(n2964), .Y(n2962) );
NAND2X4TS U4998 ( .A(n3195), .B(n3194), .Y(n8029) );
NAND2X2TS U4999 ( .A(n8038), .B(n8037), .Y(n3194) );
INVX2TS U5000 ( .A(n6876), .Y(n3144) );
INVX4TS U5001 ( .A(n6441), .Y(n2794) );
NAND2X2TS U5002 ( .A(n5208), .B(n3034), .Y(n2846) );
NAND2X4TS U5003 ( .A(n5468), .B(n1510), .Y(n1509) );
INVX2TS U5004 ( .A(n9770), .Y(n2461) );
OAI22X2TS U5005 ( .A0(n8442), .A1(n2054), .B0(n5535), .B1(n8583), .Y(n8475)
);
NAND2X2TS U5006 ( .A(n5905), .B(n1550), .Y(n1698) );
OAI22X2TS U5007 ( .A0(n5040), .A1(n793), .B0(n2095), .B1(n5036), .Y(n5042)
);
INVX2TS U5008 ( .A(n9566), .Y(n9568) );
NOR2X2TS U5009 ( .A(n11047), .B(n11046), .Y(n11052) );
OAI22X2TS U5010 ( .A0(n4644), .A1(n2056), .B0(n4636), .B1(n2588), .Y(n4690)
);
INVX2TS U5011 ( .A(n9407), .Y(n9432) );
INVX2TS U5012 ( .A(n2698), .Y(n2923) );
INVX2TS U5013 ( .A(n10767), .Y(n5131) );
INVX2TS U5014 ( .A(n8871), .Y(n7806) );
NAND2X4TS U5015 ( .A(n2487), .B(n2385), .Y(n10740) );
INVX2TS U5016 ( .A(n7756), .Y(n1613) );
NOR2X4TS U5017 ( .A(n7797), .B(n11373), .Y(n8861) );
OAI21X2TS U5018 ( .A0(n9170), .A1(n7710), .B0(n7709), .Y(n9154) );
NOR2X2TS U5019 ( .A(n9182), .B(n9178), .Y(n7708) );
OAI21X2TS U5020 ( .A0(n7594), .A1(n9643), .B0(n7593), .Y(n8340) );
INVX2TS U5021 ( .A(n9502), .Y(n7591) );
INVX2TS U5022 ( .A(n9511), .Y(n7592) );
OAI21X2TS U5023 ( .A0(n4271), .A1(n4272), .B0(n4270), .Y(n2395) );
NOR2X2TS U5024 ( .A(n2877), .B(n8765), .Y(n2876) );
NOR2X1TS U5025 ( .A(n10090), .B(n10084), .Y(n2877) );
INVX2TS U5026 ( .A(n9287), .Y(n9289) );
INVX2TS U5027 ( .A(n9291), .Y(n3066) );
OAI22X2TS U5028 ( .A0(n3767), .A1(n1983), .B0(n1944), .B1(n3204), .Y(n4762)
);
INVX2TS U5029 ( .A(n5700), .Y(n3031) );
INVX2TS U5030 ( .A(n11100), .Y(n10553) );
INVX2TS U5031 ( .A(n9654), .Y(n7540) );
NOR2X2TS U5032 ( .A(n10602), .B(n10577), .Y(n10525) );
INVX2TS U5033 ( .A(n9935), .Y(n2263) );
INVX2TS U5034 ( .A(n10652), .Y(n7741) );
INVX2TS U5035 ( .A(n10649), .Y(n10651) );
INVX4TS U5036 ( .A(n8738), .Y(n9152) );
INVX2TS U5037 ( .A(n10076), .Y(n2906) );
NAND2X4TS U5038 ( .A(n7426), .B(n7425), .Y(n10100) );
INVX2TS U5039 ( .A(n9476), .Y(n9463) );
INVX2TS U5040 ( .A(n9298), .Y(n2326) );
NAND2X2TS U5041 ( .A(n9648), .B(n8422), .Y(n8424) );
AOI21X2TS U5042 ( .A0(n10065), .A1(n10064), .B0(n10063), .Y(n10066) );
NOR2X2TS U5043 ( .A(n11798), .B(FS_Module_state_reg[2]), .Y(n3330) );
INVX2TS U5044 ( .A(n11253), .Y(n10456) );
XOR2X1TS U5045 ( .A(n654), .B(n9733), .Y(n11549) );
INVX2TS U5046 ( .A(DP_OP_168J26_122_4811_n588), .Y(
DP_OP_168J26_122_4811_n586) );
XOR2X1TS U5047 ( .A(n668), .B(n695), .Y(n11496) );
AOI22X1TS U5048 ( .A0(n11249), .A1(Add_result[22]), .B0(n11246), .B1(n11270),
.Y(n12366) );
AOI2BB2X2TS U5049 ( .B0(n10861), .B1(n10880), .A0N(n10760), .A1N(n11847),
.Y(n12279) );
AOI2BB2X2TS U5050 ( .B0(n10947), .B1(n10974), .A0N(n10760), .A1N(n11852),
.Y(n12299) );
INVX6TS U5051 ( .A(n1021), .Y(n10976) );
NAND2X2TS U5052 ( .A(n12219), .B(n10877), .Y(n12256) );
BUFX8TS U5053 ( .A(DP_OP_168J26_122_4811_n8545), .Y(n2176) );
OR2X6TS U5054 ( .A(n2210), .B(n6142), .Y(n1628) );
OAI22X2TS U5055 ( .A0(n2048), .A1(n3821), .B0(n3828), .B1(n1820), .Y(n3830)
);
CLKINVX6TS U5056 ( .A(DP_OP_168J26_122_4811_n3605), .Y(n1560) );
NOR2X4TS U5057 ( .A(n3375), .B(n3620), .Y(n3377) );
INVX2TS U5058 ( .A(n3603), .Y(n3579) );
NOR3X4TS U5059 ( .A(n1490), .B(n3757), .C(n3580), .Y(n2955) );
INVX2TS U5060 ( .A(n2984), .Y(n2982) );
INVX8TS U5061 ( .A(n3017), .Y(n3014) );
INVX2TS U5062 ( .A(n5188), .Y(n3082) );
OAI22X2TS U5063 ( .A0(n6223), .A1(n4136), .B0(n1939), .B1(n1869), .Y(n4120)
);
OAI22X2TS U5064 ( .A0(n2379), .A1(n3531), .B0(n1897), .B1(n3499), .Y(n3543)
);
ADDFHX2TS U5065 ( .A(n2397), .B(n1913), .CI(n7487), .CO(n7515), .S(n7495) );
OAI22X2TS U5066 ( .A0(n2159), .A1(n3415), .B0(n2081), .B1(n3421), .Y(n3408)
);
INVX2TS U5067 ( .A(n2269), .Y(n4477) );
OAI22X2TS U5068 ( .A0(n5331), .A1(n3685), .B0(n1898), .B1(n3683), .Y(n3689)
);
NAND2X2TS U5069 ( .A(n3940), .B(n4073), .Y(n3942) );
INVX4TS U5070 ( .A(n2659), .Y(n3938) );
NAND2X4TS U5071 ( .A(n3754), .B(n3755), .Y(n1502) );
NAND2X2TS U5072 ( .A(n1394), .B(n3586), .Y(n3588) );
AOI21X2TS U5073 ( .A0(n3603), .A1(n3586), .B0(n3585), .Y(n3587) );
INVX2TS U5074 ( .A(n2178), .Y(n3590) );
NAND2X4TS U5075 ( .A(n2980), .B(n6965), .Y(n3283) );
CMPR22X2TS U5076 ( .A(n5210), .B(n5209), .CO(n5290), .S(n5240) );
INVX12TS U5077 ( .A(n4982), .Y(n2788) );
INVX4TS U5078 ( .A(n8767), .Y(n7339) );
INVX2TS U5079 ( .A(n7866), .Y(n7853) );
INVX2TS U5080 ( .A(n6793), .Y(n6828) );
OAI22X2TS U5081 ( .A0(n2103), .A1(n6177), .B0(n6176), .B1(n6175), .Y(n6213)
);
INVX8TS U5082 ( .A(n1286), .Y(n1324) );
NAND2X2TS U5083 ( .A(DP_OP_168J26_122_4811_n6641), .B(n2776), .Y(n7999) );
ADDFHX2TS U5084 ( .A(n7036), .B(n7232), .CI(n7231), .CO(n7045), .S(n7247) );
OAI22X2TS U5085 ( .A0(n1454), .A1(n2073), .B0(n1896), .B1(n11688), .Y(n7231)
);
NAND2X4TS U5086 ( .A(n3010), .B(n3008), .Y(n3539) );
INVX2TS U5087 ( .A(n8206), .Y(n2146) );
ADDFHX2TS U5088 ( .A(n3427), .B(n3426), .CI(n3425), .CO(n4491), .S(n3452) );
INVX4TS U5089 ( .A(n6739), .Y(n6794) );
INVX2TS U5090 ( .A(n6746), .Y(n3303) );
OAI22X2TS U5091 ( .A0(n2107), .A1(n3697), .B0(n1865), .B1(n3696), .Y(n3709)
);
INVX2TS U5092 ( .A(n1028), .Y(n4487) );
OAI22X2TS U5093 ( .A0(n8082), .A1(n8579), .B0(n8081), .B1(n2056), .Y(n8098)
);
NAND2X6TS U5094 ( .A(n3211), .B(n6540), .Y(n3210) );
INVX2TS U5095 ( .A(n6541), .Y(n3212) );
OR2X4TS U5096 ( .A(n6589), .B(n6590), .Y(n3092) );
NAND2BX2TS U5097 ( .AN(n3273), .B(n6673), .Y(n3272) );
OAI22X1TS U5098 ( .A0(n6554), .A1(n1953), .B0(n1534), .B1(n6921), .Y(n6549)
);
ADDFHX2TS U5099 ( .A(n4654), .B(n4653), .CI(n4652), .CO(n9089), .S(n4646) );
OAI22X2TS U5100 ( .A0(n2889), .A1(n2113), .B0(n4683), .B1(n1960), .Y(n4652)
);
NAND2X4TS U5101 ( .A(n2425), .B(n2896), .Y(n5410) );
INVX2TS U5102 ( .A(n5378), .Y(n1733) );
INVX2TS U5103 ( .A(n9801), .Y(n1513) );
INVX2TS U5104 ( .A(DP_OP_168J26_122_4811_n8498), .Y(n4066) );
OAI22X2TS U5105 ( .A0(n7329), .A1(n2165), .B0(n4095), .B1(n7380), .Y(n7376)
);
OAI21X2TS U5106 ( .A0(n7044), .A1(n1602), .B0(n7043), .Y(n1600) );
INVX2TS U5107 ( .A(n7900), .Y(n7894) );
INVX8TS U5108 ( .A(n2307), .Y(n7660) );
NAND2X6TS U5109 ( .A(n7641), .B(n7646), .Y(n7868) );
INVX2TS U5110 ( .A(n10668), .Y(n7745) );
OAI22X2TS U5111 ( .A0(n5751), .A1(n6154), .B0(n5719), .B1(n5572), .Y(n5772)
);
NOR2X2TS U5112 ( .A(n1918), .B(n1405), .Y(n6187) );
INVX6TS U5113 ( .A(n11783), .Y(n1858) );
OAI22X2TS U5114 ( .A0(n4360), .A1(n8948), .B0(n4359), .B1(n8583), .Y(n9776)
);
INVX12TS U5115 ( .A(n2028), .Y(n2029) );
NOR2X4TS U5116 ( .A(n8213), .B(n8218), .Y(n8221) );
OAI21X2TS U5117 ( .A0(n3509), .A1(n3510), .B0(n3508), .Y(n2372) );
NAND2X4TS U5118 ( .A(n2863), .B(n2914), .Y(n2862) );
OAI21X2TS U5119 ( .A0(n4627), .A1(n4628), .B0(n4626), .Y(n3266) );
OAI22X2TS U5120 ( .A0(n7305), .A1(n1973), .B0(n7229), .B1(n2339), .Y(n7308)
);
ADDFHX2TS U5121 ( .A(n6428), .B(n6426), .CI(n6427), .CO(n6501), .S(n6441) );
XOR2X2TS U5122 ( .A(n6621), .B(n6620), .Y(n6622) );
OAI22X2TS U5123 ( .A0(n8937), .A1(n2067), .B0(n1892), .B1(n6433), .Y(n8917)
);
OAI22X2TS U5124 ( .A0(n8947), .A1(n2259), .B0(n8946), .B1(n2056), .Y(n9001)
);
NAND2X4TS U5125 ( .A(n3240), .B(n3239), .Y(n5367) );
NAND2X2TS U5126 ( .A(n1045), .B(n1043), .Y(n1755) );
OAI22X2TS U5127 ( .A0(n8569), .A1(n1961), .B0(n2098), .B1(n8570), .Y(n9783)
);
INVX2TS U5128 ( .A(n5902), .Y(n1710) );
OAI22X2TS U5129 ( .A0(n5551), .A1(n6885), .B0(n2099), .B1(n5550), .Y(n5689)
);
XOR2X2TS U5130 ( .A(n6673), .B(n6674), .Y(n3274) );
INVX6TS U5131 ( .A(n2084), .Y(n9590) );
NOR2X6TS U5132 ( .A(n7941), .B(n11357), .Y(n9609) );
INVX2TS U5133 ( .A(n10822), .Y(n10823) );
INVX2TS U5134 ( .A(n10811), .Y(n10812) );
INVX2TS U5135 ( .A(n10427), .Y(n10398) );
NOR2X4TS U5136 ( .A(n10512), .B(n10511), .Y(n10593) );
INVX2TS U5137 ( .A(n8389), .Y(n8390) );
INVX2TS U5138 ( .A(n10601), .Y(n10573) );
INVX2TS U5139 ( .A(n10585), .Y(n10609) );
INVX4TS U5140 ( .A(n10572), .Y(n10610) );
NOR2X2TS U5141 ( .A(n10455), .B(n10437), .Y(n11087) );
INVX2TS U5142 ( .A(n10588), .Y(n10592) );
INVX2TS U5143 ( .A(n10062), .Y(n8193) );
NAND2X4TS U5144 ( .A(n9639), .B(n9644), .Y(n9506) );
INVX2TS U5145 ( .A(n9416), .Y(n9417) );
NAND2X4TS U5146 ( .A(n10985), .B(n10983), .Y(n10989) );
OAI21X2TS U5147 ( .A0(n7788), .A1(n7767), .B0(n7668), .Y(n7770) );
INVX2TS U5148 ( .A(n7781), .Y(n7767) );
NOR2X4TS U5149 ( .A(n10225), .B(n10226), .Y(n6139) );
INVX12TS U5150 ( .A(n1321), .Y(n7958) );
INVX2TS U5151 ( .A(n10115), .Y(n1322) );
NAND2BX2TS U5152 ( .AN(n2964), .B(n7137), .Y(n2960) );
INVX2TS U5153 ( .A(n6524), .Y(n1678) );
INVX2TS U5154 ( .A(n8452), .Y(n2712) );
NAND2X4TS U5155 ( .A(n1507), .B(n9833), .Y(n1506) );
INVX4TS U5156 ( .A(n5468), .Y(n1507) );
NAND2X4TS U5157 ( .A(n3075), .B(n9770), .Y(n2562) );
INVX2TS U5158 ( .A(n2600), .Y(n3075) );
INVX2TS U5159 ( .A(n10565), .Y(n10540) );
INVX2TS U5160 ( .A(n10566), .Y(n10533) );
INVX2TS U5161 ( .A(n12211), .Y(n11225) );
INVX2TS U5162 ( .A(n10475), .Y(n11032) );
INVX2TS U5163 ( .A(n9567), .Y(n2317) );
INVX2TS U5164 ( .A(n9370), .Y(n7430) );
INVX2TS U5165 ( .A(n11019), .Y(n5094) );
INVX2TS U5166 ( .A(n3063), .Y(n8359) );
INVX2TS U5167 ( .A(n1624), .Y(n1625) );
NAND2X6TS U5168 ( .A(n8429), .B(n8430), .Y(n10006) );
INVX2TS U5169 ( .A(n9506), .Y(n9508) );
INVX2TS U5170 ( .A(n9507), .Y(n2340) );
INVX2TS U5171 ( .A(n11010), .Y(n11012) );
INVX6TS U5172 ( .A(n2490), .Y(n2732) );
NAND2X4TS U5173 ( .A(n3154), .B(n10776), .Y(n10790) );
INVX2TS U5174 ( .A(n10777), .Y(n3155) );
INVX2TS U5175 ( .A(n7815), .Y(n7816) );
INVX2TS U5176 ( .A(n8879), .Y(n7800) );
INVX2TS U5177 ( .A(n9141), .Y(n8740) );
INVX2TS U5178 ( .A(n9154), .Y(n9166) );
NAND2X6TS U5179 ( .A(n2499), .B(n3022), .Y(n10150) );
INVX2TS U5180 ( .A(n10213), .Y(n10221) );
INVX2TS U5181 ( .A(n10091), .Y(n1470) );
NAND2X2TS U5182 ( .A(n9564), .B(n3115), .Y(n3114) );
NAND2X4TS U5183 ( .A(n2742), .B(n4337), .Y(n2741) );
NAND2X4TS U5184 ( .A(n2744), .B(n4336), .Y(n2743) );
INVX2TS U5185 ( .A(n11102), .Y(n10555) );
INVX2TS U5186 ( .A(n11016), .Y(n3293) );
OAI21X2TS U5187 ( .A0(n2016), .A1(n9351), .B0(n9350), .Y(n9352) );
CLKINVX6TS U5188 ( .A(DP_OP_168J26_122_4811_n553), .Y(
DP_OP_168J26_122_4811_n551) );
INVX2TS U5189 ( .A(Data_MY[35]), .Y(n10253) );
INVX2TS U5190 ( .A(n11289), .Y(n10460) );
INVX2TS U5191 ( .A(n11271), .Y(n11040) );
INVX2TS U5192 ( .A(n11273), .Y(n10463) );
INVX2TS U5193 ( .A(n9648), .Y(n7541) );
BUFX3TS U5194 ( .A(n12241), .Y(n12229) );
AOI21X2TS U5195 ( .A0(n9637), .A1(n9635), .B0(n2916), .Y(n1293) );
NAND2X4TS U5196 ( .A(n1547), .B(n7576), .Y(add_x_19_n734) );
INVX2TS U5197 ( .A(Data_MY[31]), .Y(n10267) );
INVX2TS U5198 ( .A(n10010), .Y(DP_OP_168J26_122_4811_n288) );
NAND2X2TS U5199 ( .A(n1834), .B(n10881), .Y(n12278) );
AOI2BB2X2TS U5200 ( .B0(n10861), .B1(n10884), .A0N(n2007), .A1N(n11846), .Y(
n12275) );
NAND2X2TS U5201 ( .A(n3238), .B(n1015), .Y(DP_OP_168J26_122_4811_n638) );
INVX2TS U5202 ( .A(n11261), .Y(n11084) );
INVX2TS U5203 ( .A(n11257), .Y(n11049) );
NAND2X2TS U5204 ( .A(n1821), .B(n10885), .Y(n12326) );
NAND2X1TS U5205 ( .A(n1015), .B(n10034), .Y(DP_OP_168J26_122_4811_n135) );
NAND2X2TS U5206 ( .A(n1821), .B(n10975), .Y(n12310) );
INVX2TS U5207 ( .A(n10006), .Y(DP_OP_168J26_122_4811_n575) );
ADDFHX2TS U5208 ( .A(n10052), .B(n10051), .CI(n10050), .CO(
DP_OP_168J26_122_4811_n1165), .S(DP_OP_168J26_122_4811_n1166) );
XOR2X1TS U5209 ( .A(n2173), .B(n2514), .Y(DP_OP_168J26_122_4811_n1356) );
INVX6TS U5210 ( .A(n9634), .Y(add_x_19_n770) );
BUFX8TS U5211 ( .A(n10008), .Y(n2351) );
NAND3X2TS U5212 ( .A(n10704), .B(n10703), .C(n10702), .Y(n358) );
BUFX3TS U5213 ( .A(n9664), .Y(n11449) );
NAND2X2TS U5214 ( .A(n1836), .B(n498), .Y(n12352) );
INVX2TS U5215 ( .A(n10075), .Y(n9044) );
NAND2X2TS U5216 ( .A(n10099), .B(n10098), .Y(DP_OP_168J26_122_4811_n137) );
INVX2TS U5217 ( .A(n10161), .Y(n10163) );
INVX2TS U5218 ( .A(n10182), .Y(DP_OP_168J26_122_4811_n160) );
INVX2TS U5219 ( .A(n10262), .Y(n10264) );
BUFX3TS U5220 ( .A(n12241), .Y(n12230) );
CLKBUFX3TS U5221 ( .A(n12222), .Y(n11980) );
BUFX3TS U5222 ( .A(n11975), .Y(n11726) );
CLKBUFX3TS U5223 ( .A(n12394), .Y(n11445) );
INVX2TS U5224 ( .A(n10082), .Y(n3271) );
CLKBUFX3TS U5225 ( .A(n11979), .Y(n11452) );
INVX2TS U5226 ( .A(n9037), .Y(n8774) );
CLKBUFX3TS U5227 ( .A(n11975), .Y(n11456) );
CLKBUFX3TS U5228 ( .A(n9663), .Y(n11454) );
CLKBUFX3TS U5229 ( .A(n11979), .Y(n11451) );
CLKBUFX2TS U5230 ( .A(n9664), .Y(n11448) );
XOR2X1TS U5231 ( .A(n1825), .B(n10113), .Y(Sgf_operation_ODD1_Q_left[32]) );
CLKBUFX3TS U5232 ( .A(n9664), .Y(n11446) );
INVX2TS U5233 ( .A(n8377), .Y(n10068) );
INVX2TS U5234 ( .A(Data_MX[4]), .Y(n9677) );
INVX2TS U5235 ( .A(Data_MX[31]), .Y(n9699) );
INVX2TS U5236 ( .A(Data_MX[14]), .Y(n9701) );
MXI2X4TS U5237 ( .A(n10301), .B(n11943), .S0(n10310), .Y(n616) );
INVX2TS U5238 ( .A(Data_MX[28]), .Y(n9705) );
INVX2TS U5239 ( .A(Data_MX[29]), .Y(n9715) );
INVX2TS U5240 ( .A(Data_MY[38]), .Y(n10271) );
INVX2TS U5241 ( .A(Data_MY[36]), .Y(n10251) );
INVX2TS U5242 ( .A(Data_MY[32]), .Y(n3326) );
BUFX3TS U5243 ( .A(n11988), .Y(n11711) );
INVX2TS U5244 ( .A(Data_MY[4]), .Y(n10268) );
XOR2X1TS U5245 ( .A(n662), .B(n9726), .Y(n11515) );
BUFX3TS U5246 ( .A(n11451), .Y(n11724) );
INVX2TS U5247 ( .A(Data_MY[16]), .Y(n10260) );
BUFX3TS U5248 ( .A(n11694), .Y(n11700) );
CLKBUFX2TS U5249 ( .A(n11979), .Y(n10319) );
CLKBUFX3TS U5250 ( .A(n10320), .Y(n11718) );
INVX2TS U5251 ( .A(n8775), .Y(n1677) );
BUFX3TS U5252 ( .A(n12241), .Y(n11707) );
BUFX3TS U5253 ( .A(n11993), .Y(n11703) );
BUFX3TS U5254 ( .A(n1976), .Y(n11708) );
BUFX3TS U5255 ( .A(n11713), .Y(n11706) );
BUFX3TS U5256 ( .A(n11998), .Y(n12000) );
BUFX3TS U5257 ( .A(n11713), .Y(n11710) );
CLKBUFX2TS U5258 ( .A(n11452), .Y(n11720) );
CLKBUFX2TS U5259 ( .A(n11451), .Y(n11721) );
CLKBUFX3TS U5260 ( .A(n11452), .Y(n11722) );
CLKBUFX3TS U5261 ( .A(n11452), .Y(n11723) );
NAND2X2TS U5262 ( .A(n1821), .B(n489), .Y(n10785) );
NAND2X2TS U5263 ( .A(n10882), .B(n499), .Y(n12349) );
NAND2X2TS U5264 ( .A(n1835), .B(n10883), .Y(n12282) );
AOI22X1TS U5265 ( .A0(n11249), .A1(Add_result[19]), .B0(n11248), .B1(n11247),
.Y(n12376) );
CLKINVX3TS U5266 ( .A(n1826), .Y(n1830) );
AOI22X1TS U5267 ( .A0(n11276), .A1(Add_result[25]), .B0(n11258), .B1(n11270),
.Y(n12357) );
AOI22X1TS U5268 ( .A0(n11285), .A1(Add_result[44]), .B0(n11289), .B1(n11281),
.Y(n12284) );
AOI22X1TS U5269 ( .A0(n11276), .A1(Add_result[24]), .B0(n11256), .B1(n11270),
.Y(n12360) );
INVX3TS U5270 ( .A(n2005), .Y(n1956) );
AOI2BB2X2TS U5271 ( .B0(n10871), .B1(n10874), .A0N(n10946), .A1N(n11861),
.Y(n12335) );
AOI2BB2X2TS U5272 ( .B0(n10947), .B1(n10971), .A0N(n10946), .A1N(n11857),
.Y(n12319) );
AOI2BB2X2TS U5273 ( .B0(n10861), .B1(n10878), .A0N(n2007), .A1N(n11869), .Y(
n12266) );
AOI2BB2X2TS U5274 ( .B0(n10947), .B1(n1000), .A0N(n2007), .A1N(n11851), .Y(
n12295) );
AOI2BB2X2TS U5275 ( .B0(n10947), .B1(n10972), .A0N(n2007), .A1N(n11853), .Y(
n12303) );
CLKBUFX3TS U5276 ( .A(n11972), .Y(n12001) );
AOI22X1TS U5277 ( .A0(n10673), .A1(Add_result[40]), .B0(n11261), .B1(n11281),
.Y(n12300) );
AOI2BB2X2TS U5278 ( .B0(n10871), .B1(n10873), .A0N(n10870), .A1N(n11864),
.Y(n12347) );
AOI2BB2X2TS U5279 ( .B0(n10947), .B1(n10879), .A0N(n10946), .A1N(n11850),
.Y(n12291) );
AOI22X1TS U5280 ( .A0(n11285), .A1(Add_result[52]), .B0(n11284), .B1(n12216),
.Y(n12255) );
CLKINVX3TS U5281 ( .A(n2005), .Y(n1855) );
BUFX3TS U5282 ( .A(n12242), .Y(n11988) );
BUFX3TS U5283 ( .A(n1975), .Y(n12236) );
INVX2TS U5284 ( .A(Data_MX[15]), .Y(n9669) );
AOI2BB2X2TS U5285 ( .B0(n10861), .B1(n10810), .A0N(n10946), .A1N(n11842),
.Y(n12258) );
INVX2TS U5286 ( .A(Data_MY[5]), .Y(n3327) );
INVX2TS U5287 ( .A(Data_MY[11]), .Y(n10272) );
INVX2TS U5288 ( .A(Data_MX[49]), .Y(n9703) );
INVX2TS U5289 ( .A(Data_MY[8]), .Y(n10254) );
INVX2TS U5290 ( .A(Data_MY[17]), .Y(n10261) );
INVX2TS U5291 ( .A(Data_MX[8]), .Y(n9727) );
BUFX3TS U5292 ( .A(n11994), .Y(n12233) );
CLKINVX3TS U5293 ( .A(n2005), .Y(n2006) );
BUFX3TS U5294 ( .A(n1855), .Y(n12241) );
INVX2TS U5295 ( .A(n11277), .Y(n10444) );
BUFX3TS U5296 ( .A(n11993), .Y(n11998) );
BUFX3TS U5297 ( .A(n11994), .Y(n1891) );
CLKINVX3TS U5298 ( .A(n1826), .Y(n1828) );
CLKBUFX3TS U5299 ( .A(n12394), .Y(n12225) );
NAND2X2TS U5300 ( .A(n2138), .B(n10884), .Y(n12269) );
NAND2X2TS U5301 ( .A(FS_Module_state_reg[1]), .B(FSM_add_overflow_flag), .Y(
n3331) );
CLKBUFX3TS U5302 ( .A(n12227), .Y(n11985) );
NAND2X2TS U5303 ( .A(n12219), .B(n10881), .Y(n12277) );
NAND2X2TS U5304 ( .A(n10976), .B(n10975), .Y(n12309) );
BUFX3TS U5305 ( .A(n11986), .Y(n12234) );
BUFX3TS U5306 ( .A(n12222), .Y(n12223) );
BUFX3TS U5307 ( .A(n11996), .Y(n11997) );
BUFX3TS U5308 ( .A(n11998), .Y(n12232) );
BUFX3TS U5309 ( .A(n12231), .Y(n11993) );
BUFX3TS U5310 ( .A(n12231), .Y(n11994) );
INVX2TS U5311 ( .A(n11244), .Y(n10490) );
INVX2TS U5312 ( .A(n11246), .Y(n10500) );
INVX2TS U5313 ( .A(Data_MX[22]), .Y(n10270) );
BUFX3TS U5314 ( .A(n1891), .Y(n12240) );
BUFX3TS U5315 ( .A(n12242), .Y(n11987) );
BUFX3TS U5316 ( .A(n12242), .Y(n11986) );
BUFX3TS U5317 ( .A(n12228), .Y(n11973) );
OAI22X2TS U5318 ( .A0(n1516), .A1(n5157), .B0(n5176), .B1(n1959), .Y(n5164)
);
INVX12TS U5319 ( .A(n3175), .Y(n4095) );
XOR2X4TS U5320 ( .A(n2400), .B(n1658), .Y(n1283) );
XOR2X4TS U5321 ( .A(n3386), .B(n3387), .Y(n1287) );
XNOR2X4TS U5322 ( .A(n2045), .B(n1008), .Y(n5223) );
XNOR2X2TS U5323 ( .A(n2590), .B(n1008), .Y(n5006) );
INVX3TS U5324 ( .A(n1008), .Y(n3299) );
XNOR2X2TS U5325 ( .A(n2079), .B(n1008), .Y(n4970) );
INVX6TS U5326 ( .A(n2825), .Y(n1288) );
OAI22X4TS U5327 ( .A0(n2900), .A1(n5343), .B0(n2096), .B1(n5277), .Y(n5314)
);
XOR2X4TS U5328 ( .A(n1240), .B(DP_OP_168J26_122_4811_n8501), .Y(n1290) );
OAI2BB1X2TS U5329 ( .A0N(n6827), .A1N(n6826), .B0(n3060), .Y(n6858) );
INVX6TS U5330 ( .A(n6772), .Y(n6880) );
ADDFHX4TS U5331 ( .A(n7062), .B(n7258), .CI(n7061), .CO(n7064), .S(n7267) );
MXI2X4TS U5332 ( .A(n10253), .B(n12142), .S0(n10310), .Y(n617) );
OR2X4TS U5333 ( .A(n8110), .B(n867), .Y(n8402) );
OAI2BB1X4TS U5334 ( .A0N(n4896), .A1N(n4897), .B0(n2266), .Y(n1639) );
XNOR2X4TS U5335 ( .A(n1294), .B(n1295), .Y(n3659) );
NAND2X4TS U5336 ( .A(n9284), .B(n8364), .Y(n8365) );
ADDFHX4TS U5337 ( .A(n4521), .B(n4519), .CI(n4520), .CO(n4587), .S(n4522) );
NAND2X4TS U5338 ( .A(n2194), .B(n7621), .Y(n2191) );
NAND2X4TS U5339 ( .A(n7621), .B(n2193), .Y(n2192) );
BUFX6TS U5340 ( .A(n2844), .Y(n3099) );
OAI22X2TS U5341 ( .A0(n2066), .A1(n3842), .B0(n3793), .B1(n1880), .Y(n3848)
);
BUFX4TS U5342 ( .A(n9129), .Y(n1326) );
MXI2X4TS U5343 ( .A(n10276), .B(n11919), .S0(n11131), .Y(n11804) );
CLKINVX6TS U5344 ( .A(n8354), .Y(n9284) );
BUFX12TS U5345 ( .A(n5508), .Y(n2577) );
NAND2X6TS U5346 ( .A(n5508), .B(n3254), .Y(n6434) );
MXI2X4TS U5347 ( .A(n9728), .B(n11953), .S0(n9731), .Y(n9729) );
INVX6TS U5348 ( .A(n2721), .Y(n1463) );
NAND2X6TS U5349 ( .A(n1407), .B(n2721), .Y(n2766) );
NAND2X4TS U5350 ( .A(n2721), .B(n1458), .Y(n1457) );
OAI22X4TS U5351 ( .A0(n6638), .A1(n1945), .B0(n6637), .B1(n8574), .Y(n6689)
);
XOR2X4TS U5352 ( .A(n5960), .B(n1391), .Y(n3525) );
ADDFHX4TS U5353 ( .A(n4034), .B(n4033), .CI(n4032), .CO(n4040), .S(n4234) );
CLKINVX6TS U5354 ( .A(n6539), .Y(n6575) );
XNOR2X4TS U5355 ( .A(n1006), .B(n1312), .Y(n6047) );
NAND2X8TS U5356 ( .A(n1298), .B(n1297), .Y(n4118) );
NAND2BX2TS U5357 ( .AN(n8351), .B(n8352), .Y(n8353) );
INVX8TS U5358 ( .A(n7587), .Y(n7159) );
NAND2BX4TS U5359 ( .AN(n4254), .B(n2775), .Y(n2258) );
ADDFHX4TS U5360 ( .A(n3402), .B(n3403), .CI(n3401), .CO(n4509), .S(n3439) );
NAND2X8TS U5361 ( .A(n2748), .B(n2631), .Y(n9808) );
ADDFHX4TS U5362 ( .A(n7323), .B(n7321), .CI(n7322), .CO(n7419), .S(n7324) );
BUFX20TS U5363 ( .A(n2410), .Y(n8619) );
OAI22X2TS U5364 ( .A0(n7260), .A1(n1900), .B0(n5306), .B1(n7281), .Y(n7285)
);
OR2X6TS U5365 ( .A(n2996), .B(n6644), .Y(n10632) );
INVX12TS U5366 ( .A(n2757), .Y(n3880) );
CLKINVX12TS U5367 ( .A(DP_OP_168J26_122_4811_n8447), .Y(n1301) );
INVX12TS U5368 ( .A(n1301), .Y(n1302) );
INVX16TS U5369 ( .A(n1301), .Y(n1303) );
INVX12TS U5370 ( .A(n2817), .Y(n3267) );
NAND2X2TS U5371 ( .A(n5467), .B(n2835), .Y(n2833) );
NAND2X8TS U5372 ( .A(n2271), .B(n1002), .Y(n2143) );
ADDFHX4TS U5373 ( .A(n6208), .B(n6206), .CI(n6207), .CO(n6252), .S(n6229) );
BUFX16TS U5374 ( .A(n3390), .Y(n2077) );
INVX12TS U5375 ( .A(n1229), .Y(n3451) );
MXI2X4TS U5376 ( .A(n10288), .B(n11959), .S0(n10310), .Y(n615) );
XOR2X4TS U5377 ( .A(n1763), .B(n5848), .Y(n1304) );
XOR2X4TS U5378 ( .A(n11528), .B(n6160), .Y(n6096) );
OAI21X2TS U5379 ( .A0(n10246), .A1(n10263), .B0(n10247), .Y(n6114) );
ADDFHX4TS U5380 ( .A(n6533), .B(n6532), .CI(n6531), .CO(n6518), .S(n6732) );
OAI22X2TS U5381 ( .A0(n1534), .A1(n8614), .B0(n6467), .B1(n8612), .Y(n6532)
);
BUFX20TS U5382 ( .A(n6435), .Y(n2408) );
ADDFHX4TS U5383 ( .A(n6034), .B(n6033), .CI(n6032), .CO(n6026), .S(n6118) );
BUFX20TS U5384 ( .A(n1260), .Y(n7275) );
NAND2X6TS U5385 ( .A(n5849), .B(n2574), .Y(n2898) );
ADDFHX2TS U5386 ( .A(n5616), .B(n5615), .CI(n5614), .CO(n5652), .S(n5703) );
OAI22X4TS U5387 ( .A0(n823), .A1(n6044), .B0(n11757), .B1(n6146), .Y(n6168)
);
OAI22X2TS U5388 ( .A0(n2071), .A1(n5176), .B0(n1959), .B1(n5221), .Y(n5213)
);
NAND2X4TS U5389 ( .A(n1224), .B(n5380), .Y(n1747) );
BUFX20TS U5390 ( .A(DP_OP_168J26_122_4811_n8486), .Y(n7279) );
OR2X6TS U5391 ( .A(n3675), .B(n1925), .Y(n1309) );
NAND2X8TS U5392 ( .A(n1308), .B(n1309), .Y(n3718) );
ADDFHX4TS U5393 ( .A(n8259), .B(n8257), .CI(n8258), .CO(n1310) );
CLKINVX12TS U5394 ( .A(DP_OP_168J26_122_4811_n8449), .Y(n1311) );
INVX16TS U5395 ( .A(n1311), .Y(n1312) );
OAI22X4TS U5396 ( .A0(n5677), .A1(n5676), .B0(n1479), .B1(n7473), .Y(n5854)
);
BUFX4TS U5397 ( .A(n6392), .Y(n2375) );
NOR2X4TS U5398 ( .A(n6393), .B(n2375), .Y(n7524) );
OR2X8TS U5399 ( .A(n3525), .B(n1815), .Y(n1314) );
NAND2X8TS U5400 ( .A(n1313), .B(n1314), .Y(n3534) );
BUFX8TS U5401 ( .A(n4820), .Y(n2520) );
XNOR2X4TS U5402 ( .A(n1315), .B(n5996), .Y(n8269) );
XNOR2X4TS U5403 ( .A(n5997), .B(n5995), .Y(n1315) );
NOR2BX4TS U5404 ( .AN(n1902), .B(n1941), .Y(n5063) );
BUFX16TS U5405 ( .A(n4484), .Y(n8533) );
XNOR2X4TS U5406 ( .A(n2045), .B(n1729), .Y(n2841) );
INVX12TS U5407 ( .A(n3047), .Y(n1729) );
ADDFHX4TS U5408 ( .A(n2933), .B(n7194), .CI(n7193), .CO(n7331), .S(n7205) );
ADDFHX4TS U5409 ( .A(n7132), .B(n7131), .CI(n7130), .CO(n7198), .S(n7134) );
NAND2X4TS U5410 ( .A(n2597), .B(n1662), .Y(n10171) );
MXI2X4TS U5411 ( .A(n10295), .B(n11929), .S0(n11153), .Y(n11806) );
INVX16TS U5412 ( .A(n1647), .Y(n2292) );
XOR2X4TS U5413 ( .A(n8403), .B(n1317), .Y(Sgf_operation_ODD1_Q_left[41]) );
OAI22X4TS U5414 ( .A0(n1853), .A1(n6152), .B0(n2063), .B1(n5962), .Y(n6219)
);
OAI22X4TS U5415 ( .A0(n1083), .A1(n6140), .B0(n974), .B1(n5956), .Y(n6209)
);
ADDFHX4TS U5416 ( .A(n6054), .B(n6053), .CI(n6052), .CO(n6196), .S(n6049) );
OAI22X4TS U5417 ( .A0(n6154), .A1(n6017), .B0(n3320), .B1(n6047), .Y(n6053)
);
MXI2X4TS U5418 ( .A(n10252), .B(n12249), .S0(n10299), .Y(n591) );
INVX4TS U5419 ( .A(n6761), .Y(n6813) );
NAND2X2TS U5420 ( .A(n2751), .B(n9769), .Y(n3004) );
NAND2X2TS U5421 ( .A(n9884), .B(n9885), .Y(n2631) );
NAND2X6TS U5422 ( .A(n3005), .B(n3004), .Y(n9765) );
XNOR2X4TS U5423 ( .A(n1319), .B(n8477), .Y(n8656) );
XOR2X4TS U5424 ( .A(n8667), .B(n8666), .Y(n1319) );
OAI22X1TS U5425 ( .A0(n6803), .A1(n4067), .B0(n6802), .B1(n1953), .Y(n6866)
);
NAND2X4TS U5426 ( .A(n4068), .B(n4067), .Y(n6528) );
XNOR2X2TS U5427 ( .A(n1312), .B(n1807), .Y(n6095) );
NAND2X2TS U5428 ( .A(n836), .B(n1791), .Y(n1788) );
NOR2X2TS U5429 ( .A(n7612), .B(n11641), .Y(n7614) );
ADDHX4TS U5430 ( .A(n6083), .B(n6084), .CO(n6759), .S(n6782) );
OAI22X4TS U5431 ( .A0(n2100), .A1(n4441), .B0(n7471), .B1(n4458), .Y(n4463)
);
NOR2X4TS U5432 ( .A(n3363), .B(DP_OP_168J26_122_4811_n3228), .Y(n3364) );
OAI22X2TS U5433 ( .A0(n7486), .A1(n2564), .B0(n2030), .B1(n1243), .Y(n7195)
);
OAI22X4TS U5434 ( .A0(n8979), .A1(n1987), .B0(n8899), .B1(n2051), .Y(n8959)
);
NAND2X4TS U5435 ( .A(n5451), .B(n5450), .Y(n1541) );
XOR2X4TS U5436 ( .A(n1682), .B(DP_OP_168J26_122_4811_n8535), .Y(n3597) );
NAND2X8TS U5437 ( .A(n10119), .B(n1322), .Y(n1321) );
XNOR2X4TS U5438 ( .A(n1035), .B(n2643), .Y(n3423) );
XOR2X4TS U5439 ( .A(n1323), .B(n6825), .Y(n6859) );
XOR2X4TS U5440 ( .A(n6826), .B(n6827), .Y(n1323) );
INVX4TS U5441 ( .A(n8032), .Y(n8104) );
OAI22X4TS U5442 ( .A0(n3416), .A1(n2100), .B0(n3398), .B1(n5677), .Y(n3433)
);
XOR2X4TS U5443 ( .A(n1289), .B(n11765), .Y(n4225) );
OAI22X2TS U5444 ( .A0(n8578), .A1(n8577), .B0(n1020), .B1(n8576), .Y(n8634)
);
ADDFHX4TS U5445 ( .A(n4335), .B(n4334), .CI(n4333), .CO(n4394), .S(n4338) );
OAI22X4TS U5446 ( .A0(n2102), .A1(n6038), .B0(n1948), .B1(n6037), .Y(n6092)
);
ADDFHX4TS U5447 ( .A(n6107), .B(n6106), .CI(n6105), .CO(n6132), .S(n6108) );
OAI22X2TS U5448 ( .A0(n6223), .A1(n6095), .B0(n11754), .B1(n6099), .Y(n6105)
);
XNOR2X4TS U5449 ( .A(n11528), .B(DP_OP_168J26_122_4811_n8500), .Y(n3996) );
BUFX20TS U5450 ( .A(n4684), .Y(n8577) );
XOR2X4TS U5451 ( .A(n11770), .B(n944), .Y(n1385) );
NAND2X1TS U5452 ( .A(n1017), .B(n8371), .Y(n8373) );
OAI21X1TS U5453 ( .A0(n8370), .A1(n8372), .B0(n8371), .Y(n8419) );
ADDFHX4TS U5454 ( .A(n7435), .B(n7437), .CI(n7436), .CO(n7498), .S(n7459) );
OAI21X2TS U5455 ( .A0(n11741), .A1(DP_OP_168J26_122_4811_n3602), .B0(
DP_OP_168J26_122_4811_n3603), .Y(n4002) );
XOR2X4TS U5456 ( .A(n1329), .B(n1756), .Y(n8479) );
XOR2X4TS U5457 ( .A(n8484), .B(n8486), .Y(n1329) );
ADDFHX4TS U5458 ( .A(n4524), .B(n4523), .CI(n4522), .CO(n4586), .S(n4745) );
XNOR2X4TS U5459 ( .A(n1220), .B(n1913), .Y(n3407) );
NAND2BX2TS U5460 ( .AN(n6378), .B(n4393), .Y(n3169) );
ADDFHX4TS U5461 ( .A(n6770), .B(n6771), .CI(n6769), .CO(n6897), .S(n6777) );
OAI22X4TS U5462 ( .A0(n6766), .A1(n1932), .B0(n6765), .B1(n1985), .Y(n6770)
);
BUFX20TS U5463 ( .A(DP_OP_168J26_122_4811_n8166), .Y(n7438) );
ADDFHX2TS U5464 ( .A(n4696), .B(n4698), .CI(n4697), .CO(n4706), .S(n9919) );
XNOR2X4TS U5465 ( .A(n914), .B(n8552), .Y(n3629) );
INVX8TS U5466 ( .A(n3583), .Y(n8551) );
ADDFHX4TS U5467 ( .A(n9004), .B(n9003), .CI(n9002), .CO(n9080), .S(n9104) );
ADDFHX4TS U5468 ( .A(n4781), .B(n4780), .CI(n4779), .CO(n7434), .S(n4799) );
INVX16TS U5469 ( .A(n2544), .Y(n5849) );
XNOR2X4TS U5470 ( .A(n3252), .B(n6797), .Y(n1752) );
NAND2X4TS U5471 ( .A(n1680), .B(n8553), .Y(n10139) );
INVX8TS U5472 ( .A(n8553), .Y(n8599) );
OAI22X2TS U5473 ( .A0(n8576), .A1(n2019), .B0(n8535), .B1(n1020), .Y(n8557)
);
INVX6TS U5474 ( .A(n9844), .Y(n1555) );
OAI21X4TS U5475 ( .A0(DP_OP_168J26_122_4811_n654), .A1(n9319), .B0(n10040),
.Y(DP_OP_168J26_122_4811_n643) );
OR2X4TS U5476 ( .A(n6414), .B(n6421), .Y(n10184) );
NAND2X4TS U5477 ( .A(n6421), .B(n6414), .Y(n9763) );
AOI21X2TS U5478 ( .A0(n10185), .A1(n10184), .B0(n10183), .Y(n10189) );
NAND2X4TS U5479 ( .A(n10187), .B(n10184), .Y(n6279) );
INVX12TS U5480 ( .A(n2012), .Y(n2013) );
OAI22X4TS U5481 ( .A0(n1857), .A1(n883), .B0(n879), .B1(n2013), .Y(n3732) );
OAI22X4TS U5482 ( .A0(DP_OP_168J26_122_4811_n6594), .A1(n11785), .B0(n2013),
.B1(n11768), .Y(n4534) );
OAI22X4TS U5483 ( .A0(n1857), .A1(n11764), .B0(n956), .B1(n2013), .Y(n8027)
);
OAI2BB1X1TS U5484 ( .A0N(n8907), .A1N(n785), .B0(n1927), .Y(n8944) );
NAND2X4TS U5485 ( .A(n3366), .B(n3352), .Y(n3620) );
OAI22X2TS U5486 ( .A0(n8089), .A1(n2545), .B0(n8088), .B1(n2054), .Y(n8158)
);
ADDFHX4TS U5487 ( .A(n8074), .B(n8073), .CI(n8072), .CO(n8163), .S(n8135) );
ADDFHX4TS U5488 ( .A(n6890), .B(n6889), .CI(n6888), .CO(n6900), .S(n6903) );
OAI22X2TS U5489 ( .A0(n4703), .A1(n1965), .B0(n4802), .B1(n8516), .Y(n4807)
);
NAND2X2TS U5490 ( .A(n6276), .B(n2161), .Y(n10186) );
AOI21X2TS U5491 ( .A0(n10187), .A1(n10183), .B0(n6277), .Y(n6278) );
OR2X6TS U5492 ( .A(n3423), .B(n2043), .Y(n1336) );
NAND2X4TS U5493 ( .A(n9737), .B(n751), .Y(n10316) );
ADDFHX4TS U5494 ( .A(n5557), .B(n5558), .CI(n5556), .CO(n5668), .S(n5581) );
OAI22X4TS U5495 ( .A0(n5589), .A1(n2090), .B0(n5554), .B1(n1227), .Y(n5557)
);
ADDFHX4TS U5496 ( .A(n5599), .B(n5600), .CI(n5598), .CO(n5657), .S(n5731) );
OAI22X2TS U5497 ( .A0(n8061), .A1(n1973), .B0(n7305), .B1(n2036), .Y(n8079)
);
NAND2X2TS U5498 ( .A(n2612), .B(n9887), .Y(n2883) );
OAI22X4TS U5499 ( .A0(n4345), .A1(n6885), .B0(n2099), .B1(n8569), .Y(n9786)
);
NOR2X4TS U5500 ( .A(n8554), .B(n8553), .Y(n10138) );
OAI22X4TS U5501 ( .A0(n4262), .A1(n2113), .B0(n4256), .B1(n2575), .Y(n4331)
);
ADDFHX4TS U5502 ( .A(n4100), .B(n4099), .CI(n4098), .CO(n4089), .S(n4213) );
ADDFHX4TS U5503 ( .A(n5666), .B(n4126), .CI(n4125), .CO(n4110), .S(n4193) );
NAND2X8TS U5504 ( .A(n2529), .B(n2528), .Y(n11762) );
OAI22X4TS U5505 ( .A0(n6180), .A1(n7445), .B0(n1918), .B1(n6179), .Y(n6184)
);
ADDFHX4TS U5506 ( .A(n6187), .B(n6185), .CI(n6186), .CO(n6192), .S(n6166) );
XOR2X4TS U5507 ( .A(n1292), .B(n2403), .Y(n2206) );
ADDFHX2TS U5508 ( .A(n6546), .B(n6547), .CI(n6545), .CO(n6540), .S(n6584) );
BUFX12TS U5509 ( .A(n5938), .Y(n6775) );
INVX16TS U5510 ( .A(n7243), .Y(n1810) );
BUFX20TS U5511 ( .A(n3640), .Y(n2473) );
OAI22X2TS U5512 ( .A0(n8559), .A1(n6883), .B0(n8476), .B1(n1983), .Y(n8663)
);
ADDFHX4TS U5513 ( .A(n5673), .B(n5672), .CI(n5671), .CO(n5852), .S(n5640) );
OAI22X2TS U5514 ( .A0(n7446), .A1(n1815), .B0(n2043), .B1(n1035), .Y(n7469)
);
OAI22X2TS U5515 ( .A0(n7229), .A1(n2165), .B0(n7162), .B1(n2339), .Y(n7187)
);
NAND2X4TS U5516 ( .A(n2707), .B(n2706), .Y(n1339) );
CLKINVX12TS U5517 ( .A(n8715), .Y(n2707) );
ADDFHX4TS U5518 ( .A(n3711), .B(n3712), .CI(n3710), .CO(n3813), .S(n3805) );
OAI22X4TS U5519 ( .A0(n7181), .A1(n1895), .B0(n7012), .B1(n8577), .Y(n7188)
);
XNOR2X4TS U5520 ( .A(n1059), .B(n1966), .Y(n7012) );
OAI22X2TS U5521 ( .A0(n6847), .A1(n8612), .B0(n6846), .B1(n1953), .Y(n6850)
);
NOR2X4TS U5522 ( .A(n1708), .B(n1307), .Y(n10115) );
NAND2X6TS U5523 ( .A(n2610), .B(n1708), .Y(n2952) );
INVX2TS U5524 ( .A(n6792), .Y(n6829) );
NOR2X4TS U5525 ( .A(n6792), .B(n6761), .Y(n10313) );
OAI22X2TS U5526 ( .A0(n6479), .A1(n2098), .B0(n6478), .B1(n2446), .Y(n6489)
);
ADDFHX4TS U5527 ( .A(n6577), .B(n6576), .CI(n6575), .CO(n6573), .S(n6616) );
ADDFHX4TS U5528 ( .A(n5754), .B(n5755), .CI(n5756), .CO(n5726), .S(n5810) );
NAND2X8TS U5529 ( .A(n3217), .B(n3216), .Y(n5773) );
OAI22X1TS U5530 ( .A0(n6409), .A1(n785), .B0(n6535), .B1(n8907), .Y(n6547)
);
XOR2X4TS U5531 ( .A(n9852), .B(n1675), .Y(n1341) );
INVX12TS U5532 ( .A(n1707), .Y(n1708) );
OR2X6TS U5533 ( .A(n6742), .B(n6740), .Y(n10283) );
ADDFHX4TS U5534 ( .A(n6112), .B(n6113), .CI(n6111), .CO(n6745), .S(n6742) );
BUFX20TS U5535 ( .A(n2446), .Y(n8616) );
OAI22X4TS U5536 ( .A0(n5345), .A1(n1809), .B0(n5034), .B1(n793), .Y(n11184)
);
ADDFHX4TS U5537 ( .A(n5964), .B(n5966), .CI(n5965), .CO(n5958), .S(n6260) );
OAI22X4TS U5538 ( .A0(n6438), .A1(n2098), .B0(n6456), .B1(n1961), .Y(n6443)
);
BUFX20TS U5539 ( .A(n5783), .Y(n2446) );
ADDFHX4TS U5540 ( .A(n3446), .B(n3447), .CI(n3445), .CO(n4499), .S(n3453) );
INVX16TS U5541 ( .A(n1930), .Y(n1931) );
XNOR2X2TS U5542 ( .A(DP_OP_168J26_122_4811_n6794), .B(n1817), .Y(n3469) );
XNOR2X2TS U5543 ( .A(DP_OP_168J26_122_4811_n6794), .B(n1694), .Y(n3422) );
INVX6TS U5544 ( .A(n9261), .Y(DP_OP_168J26_122_4811_n654) );
ADDFHX4TS U5545 ( .A(n6021), .B(n6020), .CI(n6019), .CO(n6050), .S(n6031) );
XNOR2X4TS U5546 ( .A(n5686), .B(n5688), .Y(n2548) );
ADDFHX4TS U5547 ( .A(n6702), .B(n6701), .CI(n6703), .CO(n6696), .S(n6943) );
OAI22X4TS U5548 ( .A0(n730), .A1(n5552), .B0(n7471), .B1(n5568), .Y(n5610)
);
BUFX16TS U5549 ( .A(n1624), .Y(n2571) );
INVX6TS U5550 ( .A(n1711), .Y(n1741) );
INVX4TS U5551 ( .A(n1669), .Y(n1670) );
BUFX12TS U5552 ( .A(n1669), .Y(n2397) );
AND2X2TS U5553 ( .A(n2064), .B(n10899), .Y(n1342) );
INVX8TS U5554 ( .A(n1416), .Y(n1984) );
INVX12TS U5555 ( .A(n1984), .Y(n1985) );
INVX6TS U5556 ( .A(n8542), .Y(n2032) );
INVX4TS U5557 ( .A(DP_OP_168J26_122_4811_n6618), .Y(n5180) );
INVX2TS U5558 ( .A(n3757), .Y(n3570) );
INVX8TS U5559 ( .A(n1868), .Y(n1869) );
AND2X2TS U5560 ( .A(n10088), .B(n9041), .Y(n1345) );
BUFX8TS U5561 ( .A(n2296), .Y(n6883) );
INVX8TS U5562 ( .A(n1730), .Y(n3202) );
OR2X8TS U5563 ( .A(n2466), .B(n2280), .Y(n1347) );
BUFX12TS U5564 ( .A(n5493), .Y(n8508) );
XNOR2X4TS U5565 ( .A(n8672), .B(n3185), .Y(n1348) );
BUFX12TS U5566 ( .A(n2446), .Y(n1961) );
INVX4TS U5567 ( .A(n9563), .Y(n8756) );
BUFX8TS U5568 ( .A(n6562), .Y(n8548) );
INVX2TS U5569 ( .A(n9561), .Y(n3196) );
INVX8TS U5570 ( .A(n8897), .Y(n1903) );
MXI2X4TS U5571 ( .A(n9686), .B(n11924), .S0(n9718), .Y(n1355) );
AND2X8TS U5572 ( .A(n8791), .B(FS_Module_state_reg[1]), .Y(n1356) );
OR2X8TS U5573 ( .A(n3332), .B(n8787), .Y(n1357) );
AND2X2TS U5574 ( .A(n10953), .B(n11383), .Y(n1360) );
NAND2X6TS U5575 ( .A(n6715), .B(n6716), .Y(n10040) );
INVX2TS U5576 ( .A(n7870), .Y(n7856) );
INVX2TS U5577 ( .A(n8722), .Y(n9210) );
INVX2TS U5578 ( .A(n7665), .Y(n7679) );
INVX2TS U5579 ( .A(n3569), .Y(n3759) );
BUFX12TS U5580 ( .A(n6079), .Y(n6086) );
CLKXOR2X2TS U5581 ( .A(n8373), .B(n8372), .Y(n1363) );
INVX4TS U5582 ( .A(n5254), .Y(n7024) );
BUFX4TS U5583 ( .A(n4060), .Y(n2588) );
OAI21X1TS U5584 ( .A0(n9579), .A1(n8421), .B0(n9580), .Y(n1365) );
NAND2X2TS U5585 ( .A(n8226), .B(n8227), .Y(n9560) );
MXI2X2TS U5586 ( .A(n11832), .B(n11796), .S0(FSM_selector_A), .Y(n3333) );
AO21X4TS U5587 ( .A0(n9652), .A1(n9651), .B0(n9650), .Y(n1366) );
OR2X4TS U5588 ( .A(n3317), .B(n2930), .Y(n3753) );
BUFX8TS U5589 ( .A(n6403), .Y(n8629) );
OR2X4TS U5590 ( .A(n8032), .B(n2262), .Y(n1367) );
OR2X4TS U5591 ( .A(n6876), .B(n6887), .Y(n10239) );
BUFX8TS U5592 ( .A(n2571), .Y(n7489) );
AND2X2TS U5593 ( .A(n1370), .B(n9285), .Y(n1372) );
AND2X2TS U5594 ( .A(n10059), .B(n10061), .Y(n1374) );
AND2X2TS U5595 ( .A(n8437), .B(n8436), .Y(n1375) );
AND2X2TS U5596 ( .A(n3574), .B(n3573), .Y(n1376) );
AND2X2TS U5597 ( .A(n11745), .B(n3779), .Y(n1377) );
AND2X2TS U5598 ( .A(n9071), .B(n10908), .Y(n1379) );
INVX2TS U5599 ( .A(n6509), .Y(n1768) );
AND2X2TS U5600 ( .A(n10956), .B(n10916), .Y(n1382) );
AND2X2TS U5601 ( .A(n2970), .B(n3563), .Y(n1383) );
NOR2X6TS U5602 ( .A(n6983), .B(n998), .Y(n9305) );
OR2X8TS U5603 ( .A(n10008), .B(n10007), .Y(n1390) );
NAND2X6TS U5604 ( .A(n1525), .B(n1524), .Y(n4254) );
OAI21X1TS U5605 ( .A0(n8732), .A1(n8729), .B0(n8733), .Y(n1393) );
NOR2X4TS U5606 ( .A(n3757), .B(n1489), .Y(n1394) );
INVX4TS U5607 ( .A(n7568), .Y(n9046) );
XNOR2X2TS U5608 ( .A(n8540), .B(n8513), .Y(n1396) );
INVX4TS U5609 ( .A(n9780), .Y(n1728) );
XNOR2X2TS U5610 ( .A(n1890), .B(n1644), .Y(n5277) );
INVX2TS U5611 ( .A(n7761), .Y(n7762) );
OAI21X1TS U5612 ( .A0(n9421), .A1(n9420), .B0(n9419), .Y(n1399) );
AND2X4TS U5613 ( .A(n2608), .B(n6439), .Y(n1400) );
AND2X2TS U5614 ( .A(n3759), .B(DP_OP_168J26_122_4811_n3445), .Y(n1401) );
AND2X8TS U5615 ( .A(n1549), .B(n1362), .Y(n1402) );
AND2X2TS U5616 ( .A(n5885), .B(n1481), .Y(n1403) );
INVX12TS U5617 ( .A(n1583), .Y(n2484) );
OR2X4TS U5618 ( .A(n8227), .B(n8226), .Y(n9561) );
OR2X2TS U5619 ( .A(n1809), .B(n1324), .Y(n1412) );
INVX6TS U5620 ( .A(n8223), .Y(n10065) );
BUFX8TS U5621 ( .A(DP_OP_168J26_122_4811_n6614), .Y(n1988) );
OAI22X2TS U5622 ( .A0(n7476), .A1(n7477), .B0(n7475), .B1(n7474), .Y(n1414)
);
NAND2X4TS U5623 ( .A(n6403), .B(n3787), .Y(n1416) );
INVX8TS U5624 ( .A(n1456), .Y(n2544) );
OR2X2TS U5625 ( .A(n2710), .B(n5220), .Y(n1417) );
OR2X4TS U5626 ( .A(n1900), .B(n8023), .Y(n1418) );
BUFX8TS U5627 ( .A(DP_OP_168J26_122_4811_n6616), .Y(n1990) );
AND2X2TS U5628 ( .A(n9861), .B(n9862), .Y(n1424) );
INVX2TS U5629 ( .A(n7772), .Y(n2199) );
AND2X2TS U5630 ( .A(n9338), .B(n9337), .Y(n1425) );
INVX8TS U5631 ( .A(n1370), .Y(n8416) );
BUFX8TS U5632 ( .A(n4351), .Y(n9456) );
AND2X4TS U5633 ( .A(n2875), .B(n2873), .Y(n1430) );
AND2X8TS U5634 ( .A(n11173), .B(FS_Module_state_reg[3]), .Y(n1431) );
INVX2TS U5635 ( .A(n8338), .Y(n9572) );
INVX2TS U5636 ( .A(n10072), .Y(n9035) );
INVX2TS U5637 ( .A(n10056), .Y(n8759) );
INVX2TS U5638 ( .A(n9034), .Y(n9299) );
XNOR2X4TS U5639 ( .A(n672), .B(n671), .Y(n1432) );
MXI2X2TS U5640 ( .A(n11826), .B(n12388), .S0(FSM_selector_A), .Y(n1434) );
MXI2X2TS U5641 ( .A(n11829), .B(n12385), .S0(FSM_selector_A), .Y(n1435) );
INVX2TS U5642 ( .A(n9565), .Y(n3115) );
AND2X2TS U5643 ( .A(n3115), .B(n10089), .Y(n1437) );
AND2X2TS U5644 ( .A(n9299), .B(n9298), .Y(n1438) );
AND2X2TS U5645 ( .A(n8760), .B(n8757), .Y(n1439) );
MXI2X2TS U5646 ( .A(n11828), .B(n12386), .S0(FSM_selector_A), .Y(n1440) );
INVX4TS U5647 ( .A(n6921), .Y(n2459) );
MXI2X4TS U5648 ( .A(n9725), .B(n11793), .S0(n9724), .Y(n1441) );
MXI2X4TS U5649 ( .A(n9698), .B(n11925), .S0(n11167), .Y(n1446) );
INVX4TS U5650 ( .A(n2653), .Y(n1776) );
AND2X2TS U5651 ( .A(n8774), .B(n9036), .Y(n1448) );
INVX8TS U5652 ( .A(n12218), .Y(n3290) );
BUFX3TS U5653 ( .A(n11987), .Y(n11713) );
CLKBUFX3TS U5654 ( .A(n11715), .Y(n10320) );
BUFX3TS U5655 ( .A(n2006), .Y(n11704) );
CLKINVX3TS U5656 ( .A(n1826), .Y(n1829) );
CLKINVX3TS U5657 ( .A(n2005), .Y(n1957) );
CLKINVX3TS U5658 ( .A(n2005), .Y(n1976) );
INVX2TS U5659 ( .A(n2005), .Y(n1867) );
INVX2TS U5660 ( .A(n2005), .Y(n1974) );
BUFX3TS U5661 ( .A(n11994), .Y(n11996) );
INVX2TS U5662 ( .A(n2005), .Y(n1975) );
INVX2TS U5663 ( .A(n11992), .Y(n2005) );
CLKBUFX2TS U5664 ( .A(n11972), .Y(n11129) );
INVX2TS U5665 ( .A(n1826), .Y(n1854) );
CLKBUFX3TS U5666 ( .A(n10320), .Y(n11719) );
CLKBUFX3TS U5667 ( .A(n11977), .Y(n11455) );
CLKBUFX2TS U5668 ( .A(n10320), .Y(n2008) );
CLKBUFX3TS U5669 ( .A(n10320), .Y(n11717) );
OAI22X2TS U5670 ( .A0(n6803), .A1(n1953), .B0(n8612), .B1(n1598), .Y(n6797)
);
XNOR2X2TS U5671 ( .A(n2021), .B(n1954), .Y(n6803) );
XNOR2X2TS U5672 ( .A(n3167), .B(n9633), .Y(Sgf_operation_ODD1_S_B[6]) );
NAND2X8TS U5673 ( .A(n2691), .B(n1464), .Y(n3069) );
NAND3X8TS U5674 ( .A(n2694), .B(n2692), .C(n2693), .Y(n1464) );
NOR2X8TS U5675 ( .A(n5849), .B(n5848), .Y(n9264) );
XOR2X4TS U5676 ( .A(n1467), .B(n5466), .Y(n1456) );
NAND3X8TS U5677 ( .A(n1461), .B(n1459), .C(n1457), .Y(n1547) );
AOI2BB2X4TS U5678 ( .B0(n7428), .B1(n5478), .A0N(n8182), .A1N(n1460), .Y(
n1459) );
OAI21X4TS U5679 ( .A0(n1466), .A1(n2872), .B0(n1397), .Y(n2768) );
XOR2X4TS U5680 ( .A(n5467), .B(n2835), .Y(n1467) );
INVX16TS U5681 ( .A(n2702), .Y(n10092) );
XOR2X4TS U5682 ( .A(n1469), .B(n10097), .Y(Sgf_operation_ODD1_Q_right[45])
);
OA21X4TS U5683 ( .A0(n10093), .A1(n1468), .B0(n1350), .Y(n1469) );
XOR2X4TS U5684 ( .A(n1471), .B(n6350), .Y(n6372) );
XOR2X4TS U5685 ( .A(n1484), .B(n6366), .Y(n1483) );
NAND2X4TS U5686 ( .A(n6352), .B(n6351), .Y(n1472) );
OAI21X4TS U5687 ( .A0(n6351), .A1(n6352), .B0(n6350), .Y(n1473) );
OAI21X4TS U5688 ( .A0(n8701), .A1(n8700), .B0(n8699), .Y(n1475) );
XOR2X4TS U5689 ( .A(n9276), .B(n9277), .Y(n1779) );
XOR2X4TS U5690 ( .A(n1784), .B(n2544), .Y(n1478) );
XOR2X4TS U5691 ( .A(n8487), .B(n6374), .Y(n1784) );
XOR2X4TS U5692 ( .A(n1763), .B(n5848), .Y(n8486) );
OAI22X4TS U5693 ( .A0(n5568), .A1(n730), .B0(n1916), .B1(n1479), .Y(n5672)
);
XNOR2X4TS U5694 ( .A(n2403), .B(DP_OP_168J26_122_4811_n8448), .Y(n1479) );
XNOR2X4TS U5695 ( .A(n5721), .B(n2341), .Y(n5862) );
XNOR2X4TS U5696 ( .A(n1454), .B(n1813), .Y(n5588) );
XNOR2X4TS U5697 ( .A(n1454), .B(n3451), .Y(n5650) );
XOR2X4TS U5698 ( .A(n1480), .B(n7349), .Y(n7448) );
XOR2X4TS U5699 ( .A(n1481), .B(n5885), .Y(n5856) );
OAI22X4TS U5700 ( .A0(n5667), .A1(n1364), .B0(n1243), .B1(n7486), .Y(n1481)
);
OAI2BB1X4TS U5701 ( .A0N(n6366), .A1N(n6365), .B0(n1482), .Y(n6357) );
OAI21X4TS U5702 ( .A0(n6365), .A1(n6366), .B0(n1484), .Y(n1482) );
XOR2X4TS U5703 ( .A(n1483), .B(n6365), .Y(n6367) );
OAI21X4TS U5704 ( .A0(n7959), .A1(n6379), .B0(n1485), .Y(n6380) );
AOI21X4TS U5705 ( .A0(n7960), .A1(n1487), .B0(n1486), .Y(n1485) );
NAND2X8TS U5706 ( .A(n7958), .B(n1487), .Y(n6379) );
AOI21X4TS U5707 ( .A0(n6375), .A1(n10133), .B0(n1488), .Y(n7959) );
NAND2X8TS U5708 ( .A(n2711), .B(n2574), .Y(n10162) );
XOR2X4TS U5709 ( .A(n6376), .B(n9801), .Y(n1635) );
XNOR2X4TS U5710 ( .A(n9906), .B(n9907), .Y(n2421) );
NOR2X8TS U5711 ( .A(n3580), .B(n2178), .Y(n3602) );
OR2X8TS U5712 ( .A(n3637), .B(n11756), .Y(n3757) );
NOR2X8TS U5713 ( .A(n7272), .B(DP_OP_168J26_122_4811_n8467), .Y(n2178) );
NAND3X8TS U5714 ( .A(n1495), .B(n1494), .C(n1493), .Y(n9479) );
OR2X8TS U5715 ( .A(n2246), .B(n3381), .Y(n1494) );
XOR2X4TS U5716 ( .A(n1492), .B(n1871), .Y(n8588) );
NAND2X8TS U5717 ( .A(n1499), .B(n1498), .Y(n3603) );
OA21X4TS U5718 ( .A0(n3572), .A1(DP_OP_168J26_122_4811_n3445), .B0(n3573),
.Y(n1498) );
NAND2X8TS U5719 ( .A(n3756), .B(n3378), .Y(n1499) );
NOR2X8TS U5720 ( .A(n3572), .B(n3569), .Y(n3378) );
NAND2X8TS U5721 ( .A(n2183), .B(n3630), .Y(n3756) );
INVX16TS U5722 ( .A(n1500), .Y(n2573) );
XNOR2X4TS U5723 ( .A(n1501), .B(n12030), .Y(n1500) );
OAI22X4TS U5724 ( .A0(n1533), .A1(n2114), .B0(n795), .B1(n1504), .Y(n4573)
);
BUFX12TS U5725 ( .A(n5468), .Y(n1505) );
OAI21X4TS U5726 ( .A0(n1280), .A1(n1318), .B0(n1679), .Y(n2799) );
NAND2X8TS U5727 ( .A(n1508), .B(n1506), .Y(n1679) );
INVX2TS U5728 ( .A(n9833), .Y(n1510) );
BUFX20TS U5729 ( .A(n5328), .Y(n1516) );
OAI22X4TS U5730 ( .A0(n5157), .A1(n1959), .B0(n4828), .B1(n2071), .Y(n5155)
);
XNOR2X4TS U5731 ( .A(n1240), .B(n1632), .Y(n1517) );
XOR2X4TS U5732 ( .A(n11582), .B(n1623), .Y(n5157) );
OAI2BB1X4TS U5733 ( .A0N(n1521), .A1N(n9923), .B0(n1519), .Y(n9941) );
OAI21X4TS U5734 ( .A0(n9923), .A1(n1521), .B0(n9924), .Y(n1519) );
XOR2X4TS U5735 ( .A(n1520), .B(n9924), .Y(n9927) );
XOR2X4TS U5736 ( .A(n9923), .B(n1521), .Y(n1520) );
OAI21X4TS U5737 ( .A0(n5368), .A1(n5367), .B0(n5366), .Y(n1522) );
XOR2X4TS U5738 ( .A(n2400), .B(n1658), .Y(n2775) );
OAI21X4TS U5739 ( .A0(n2281), .A1(n4217), .B0(n2268), .Y(n1525) );
OAI22X4TS U5740 ( .A0(n4839), .A1(n1898), .B0(n2110), .B1(n1526), .Y(n4851)
);
OAI22X4TS U5741 ( .A0(n4888), .A1(n5331), .B0(n5058), .B1(n1526), .Y(n4894)
);
XOR2X4TS U5742 ( .A(n5235), .B(n1726), .Y(n1526) );
INVX6TS U5743 ( .A(DP_OP_168J26_122_4811_n606), .Y(n1527) );
NAND2X8TS U5744 ( .A(n1527), .B(n1528), .Y(DP_OP_168J26_122_4811_n131) );
NOR2X8TS U5745 ( .A(n8309), .B(n8310), .Y(DP_OP_168J26_122_4811_n606) );
XOR2X4TS U5746 ( .A(n2653), .B(n1518), .Y(n1529) );
OAI22X4TS U5747 ( .A0(n1530), .A1(n974), .B0(n6003), .B1(
DP_OP_168J26_122_4811_n8003), .Y(n4440) );
AOI2BB2X4TS U5748 ( .B0(n1349), .B1(n1872), .A0N(n1530), .A1N(n6003), .Y(
n2269) );
XOR2X4TS U5749 ( .A(n952), .B(n2666), .Y(n1530) );
NOR2X8TS U5750 ( .A(n8307), .B(n8308), .Y(n10023) );
XNOR2X4TS U5751 ( .A(n2045), .B(n7279), .Y(n1532) );
XOR2X4TS U5752 ( .A(n2632), .B(n2032), .Y(n1534) );
XOR2X4TS U5753 ( .A(n4233), .B(n1536), .Y(n2310) );
NAND2X8TS U5754 ( .A(n1540), .B(n1537), .Y(n2417) );
XNOR2X4TS U5755 ( .A(DP_OP_168J26_122_4811_n6641), .B(
DP_OP_168J26_122_4811_n8480), .Y(n2904) );
OAI21X4TS U5756 ( .A0(n5433), .A1(n5431), .B0(n5432), .Y(n3126) );
OAI21X4TS U5757 ( .A0(n5450), .A1(n5451), .B0(n5449), .Y(n1542) );
OAI21X4TS U5758 ( .A0(n5350), .A1(n5351), .B0(n5349), .Y(n3028) );
OAI22X4TS U5759 ( .A0(n3820), .A1(n8013), .B0(n1543), .B1(n1980), .Y(n3831)
);
XNOR2X4TS U5760 ( .A(n3078), .B(n866), .Y(n1543) );
XOR2X4TS U5761 ( .A(n883), .B(n7275), .Y(n2871) );
OAI21X4TS U5762 ( .A0(n5374), .A1(n2897), .B0(n5373), .Y(n2425) );
OAI22X4TS U5763 ( .A0(n5316), .A1(n981), .B0(n5317), .B1(n8007), .Y(n2897)
);
XOR2X4TS U5764 ( .A(n11764), .B(n1289), .Y(n5317) );
XOR2X4TS U5765 ( .A(n1289), .B(n956), .Y(n5316) );
OAI2BB1X4TS U5766 ( .A0N(n9916), .A1N(n9915), .B0(n1545), .Y(n9926) );
OAI21X4TS U5767 ( .A0(n9915), .A1(n9916), .B0(n9914), .Y(n1545) );
XOR2X4TS U5768 ( .A(n1546), .B(n9915), .Y(n10015) );
XOR2X4TS U5769 ( .A(n9914), .B(n9916), .Y(n1546) );
OR2X8TS U5770 ( .A(n1547), .B(n7576), .Y(add_x_19_n830) );
OAI22X4TS U5771 ( .A0(n2112), .A1(n1548), .B0(n4702), .B1(n1960), .Y(n4759)
);
NAND2X1TS U5772 ( .A(n11739), .B(DP_OP_168J26_122_4811_n3603), .Y(n4062) );
NOR2X8TS U5773 ( .A(n3351), .B(DP_OP_168J26_122_4811_n3519), .Y(n3352) );
NOR2X8TS U5774 ( .A(DP_OP_168J26_122_4811_n8456), .B(
DP_OP_168J26_122_4811_n8481), .Y(n3351) );
XOR2X4TS U5775 ( .A(n5905), .B(n1550), .Y(n1695) );
NAND2X8TS U5776 ( .A(n5904), .B(n1550), .Y(n1696) );
OAI22X4TS U5777 ( .A0(n5832), .A1(n2108), .B0(n5831), .B1(n1962), .Y(n1550)
);
OAI21X4TS U5778 ( .A0(n9906), .A1(n9907), .B0(n9905), .Y(n2420) );
NAND2X4TS U5779 ( .A(n9825), .B(n1348), .Y(n1556) );
XOR2X4TS U5780 ( .A(n1558), .B(n4003), .Y(n1557) );
INVX12TS U5781 ( .A(n1585), .Y(n8627) );
XNOR2X4TS U5782 ( .A(n8627), .B(n2034), .Y(n8642) );
NOR2X8TS U5783 ( .A(n1560), .B(DP_OP_168J26_122_4811_n3602), .Y(n1559) );
NOR2X8TS U5784 ( .A(DP_OP_168J26_122_4811_n3595), .B(
DP_OP_168J26_122_4811_n3603), .Y(n1563) );
OAI2BB1X4TS U5785 ( .A0N(n1564), .A1N(n1572), .B0(n1566), .Y(n6973) );
XOR2X4TS U5786 ( .A(n1573), .B(n6908), .Y(n1572) );
BUFX20TS U5787 ( .A(n8444), .Y(n1565) );
XOR2X4TS U5788 ( .A(n1572), .B(n1569), .Y(n6933) );
OAI22X4TS U5789 ( .A0(n6905), .A1(n2109), .B0(n6923), .B1(n1955), .Y(n1570)
);
OAI22X4TS U5790 ( .A0(n6920), .A1(n8612), .B0(n8614), .B1(n6907), .Y(n1571)
);
XOR2X4TS U5791 ( .A(n6877), .B(n6876), .Y(n1573) );
NAND2X8TS U5792 ( .A(n1575), .B(n1574), .Y(n1848) );
NAND2BX4TS U5793 ( .AN(n2288), .B(n9946), .Y(n1574) );
NAND2BX4TS U5794 ( .AN(n9946), .B(n2288), .Y(n1576) );
XNOR2X2TS U5795 ( .A(n2288), .B(n9946), .Y(n1577) );
XNOR2X4TS U5796 ( .A(n1579), .B(n4406), .Y(n4409) );
XNOR2X4TS U5797 ( .A(n4407), .B(n1580), .Y(n1579) );
OAI22X4TS U5798 ( .A0(n4297), .A1(n2259), .B0(n4294), .B1(n8945), .Y(n1580)
);
XOR2X4TS U5799 ( .A(n9926), .B(n1068), .Y(n2250) );
INVX16TS U5800 ( .A(n1581), .Y(n1582) );
INVX12TS U5801 ( .A(n2484), .Y(n1581) );
OAI21X4TS U5802 ( .A0(n2658), .A1(n4077), .B0(n4076), .Y(n1584) );
XOR2X4TS U5803 ( .A(n1584), .B(n4079), .Y(n1583) );
OAI22X4TS U5804 ( .A0(n4705), .A1(n2293), .B0(n1893), .B1(n4731), .Y(n4728)
);
XOR2X4TS U5805 ( .A(n1585), .B(n8896), .Y(n4731) );
OAI21X4TS U5806 ( .A0(n2777), .A1(n4280), .B0(n4279), .Y(n1587) );
XNOR2X4TS U5807 ( .A(n1586), .B(n3746), .Y(n2777) );
XNOR2X4TS U5808 ( .A(n3745), .B(n3744), .Y(n1586) );
OAI2BB1X4TS U5809 ( .A0N(n4280), .A1N(n2777), .B0(n1587), .Y(n3964) );
NAND2X8TS U5810 ( .A(n3304), .B(n3305), .Y(DP_OP_168J26_122_4811_n626) );
OAI2BB1X4TS U5811 ( .A0N(n5112), .A1N(n5113), .B0(n1589), .Y(n5108) );
OAI21X4TS U5812 ( .A0(n5113), .A1(n5112), .B0(n5111), .Y(n1589) );
NOR2X4TS U5813 ( .A(n11639), .B(n11640), .Y(n7750) );
XNOR2X4TS U5814 ( .A(n2338), .B(n8887), .Y(n4364) );
XNOR2X4TS U5815 ( .A(n1454), .B(n743), .Y(n4794) );
XOR2X4TS U5816 ( .A(n1480), .B(n1715), .Y(n3431) );
OAI2BB1X4TS U5817 ( .A0N(n5894), .A1N(n5893), .B0(n1592), .Y(n6362) );
OAI21X4TS U5818 ( .A0(n5893), .A1(n5894), .B0(n5892), .Y(n1592) );
XOR2X4TS U5819 ( .A(n1593), .B(n5892), .Y(n5847) );
XOR2X4TS U5820 ( .A(n5894), .B(n5893), .Y(n1593) );
OAI21X4TS U5821 ( .A0(n5458), .A1(n1596), .B0(n5459), .Y(n1594) );
XNOR2X4TS U5822 ( .A(n1595), .B(n905), .Y(n5464) );
XOR2X4TS U5823 ( .A(n2349), .B(n1954), .Y(n1599) );
XNOR2X4TS U5824 ( .A(n8921), .B(n3322), .Y(n8064) );
XNOR2X4TS U5825 ( .A(n2632), .B(n1929), .Y(n5633) );
OAI2BB1X4TS U5826 ( .A0N(n7044), .A1N(n1602), .B0(n1600), .Y(n7078) );
XOR2X4TS U5827 ( .A(n1601), .B(n7043), .Y(n7237) );
XOR2X4TS U5828 ( .A(n7044), .B(n1602), .Y(n1601) );
OAI22X4TS U5829 ( .A0(n7041), .A1(n729), .B0(n7037), .B1(n5677), .Y(n1602)
);
XOR2X4TS U5830 ( .A(n4764), .B(n4763), .Y(n2294) );
XOR2X4TS U5831 ( .A(n3966), .B(n3965), .Y(n2286) );
XOR2X4TS U5832 ( .A(n1603), .B(n7049), .Y(n8230) );
XOR2X4TS U5833 ( .A(n7050), .B(n7051), .Y(n1603) );
BUFX12TS U5834 ( .A(n2815), .Y(n1604) );
BUFX6TS U5835 ( .A(n8592), .Y(n1605) );
OAI22X4TS U5836 ( .A0(n1001), .A1(n1604), .B0(n1605), .B1(n3022), .Y(n8698)
);
XOR2X4TS U5837 ( .A(n2677), .B(n1405), .Y(n5949) );
OAI22X4TS U5838 ( .A0(n795), .A1(n7060), .B0(n2114), .B1(n7022), .Y(n7057)
);
XOR2X4TS U5839 ( .A(n1608), .B(n2931), .Y(n7022) );
INVX12TS U5840 ( .A(Op_MY[23]), .Y(n2931) );
OAI22X4TS U5841 ( .A0(n3663), .A1(n1865), .B0(n3696), .B1(n5340), .Y(n2801)
);
OAI22X4TS U5842 ( .A0(n3698), .A1(n1934), .B0(n3670), .B1(n1990), .Y(n3702)
);
XOR2X4TS U5843 ( .A(n1610), .B(n989), .Y(n9395) );
OAI21X4TS U5844 ( .A0(n9394), .A1(n2202), .B0(n9393), .Y(n1610) );
INVX12TS U5845 ( .A(n7829), .Y(n2200) );
NAND2X4TS U5846 ( .A(n8880), .B(n8865), .Y(n7802) );
XOR2X4TS U5847 ( .A(n1289), .B(DP_OP_168J26_122_4811_n6171), .Y(n3713) );
XOR2X4TS U5848 ( .A(n1612), .B(n7760), .Y(n7797) );
AOI21X4TS U5849 ( .A0(n7667), .A1(n1614), .B0(n1613), .Y(n1612) );
XNOR2X2TS U5850 ( .A(n1831), .B(n2430), .Y(n5056) );
XNOR2X2TS U5851 ( .A(n1831), .B(n1870), .Y(n5005) );
OAI22X4TS U5852 ( .A0(n7445), .A1(n6155), .B0(n1918), .B1(n5955), .Y(n6210)
);
OAI21X4TS U5853 ( .A0(n7092), .A1(n2929), .B0(n7091), .Y(n2928) );
INVX4TS U5854 ( .A(n6725), .Y(n1616) );
ADDFHX4TS U5855 ( .A(n6455), .B(n6454), .CI(n6453), .CO(n6520), .S(n6725) );
OAI22X4TS U5856 ( .A0(n2089), .A1(n1811), .B0(n11528), .B1(n1227), .Y(n4125)
);
ADDFHX4TS U5857 ( .A(n5312), .B(n5311), .CI(n5310), .CO(n5416), .S(n5336) );
XOR2X4TS U5858 ( .A(n11527), .B(n7438), .Y(n5684) );
NAND2X6TS U5859 ( .A(n2663), .B(n2805), .Y(n2667) );
XNOR2X4TS U5860 ( .A(n2068), .B(n2409), .Y(n5181) );
XNOR2X4TS U5861 ( .A(n7277), .B(n5235), .Y(n4026) );
XNOR2X4TS U5862 ( .A(n5251), .B(n944), .Y(n5252) );
OAI22X2TS U5863 ( .A0(n4732), .A1(n1986), .B0(n4804), .B1(n2051), .Y(n4775)
);
XNOR2X4TS U5864 ( .A(n4003), .B(n2265), .Y(n6744) );
XOR2X4TS U5865 ( .A(n926), .B(n1813), .Y(n5679) );
XOR2X4TS U5866 ( .A(n3945), .B(n2217), .Y(n1620) );
AO22X4TS U5867 ( .A0(n2028), .A1(n1868), .B0(n1937), .B1(n1869), .Y(n3897)
);
NAND2X4TS U5868 ( .A(n5791), .B(n5790), .Y(n3216) );
NOR2BX2TS U5869 ( .AN(n6849), .B(n4061), .Y(n5943) );
ADDFHX2TS U5870 ( .A(n4398), .B(n4397), .CI(n4396), .S(n1621) );
XNOR2X4TS U5871 ( .A(n1634), .B(n2672), .Y(n1622) );
OAI22X2TS U5872 ( .A0(n8447), .A1(n1968), .B0(n8621), .B1(n1932), .Y(n8639)
);
XNOR2X4TS U5873 ( .A(n1819), .B(n2410), .Y(n8447) );
NAND2X4TS U5874 ( .A(DP_OP_168J26_122_4811_n8460), .B(n1711), .Y(n4078) );
OAI2BB2X4TS U5875 ( .B0(n2114), .B1(n4592), .A0N(n1626), .A1N(n860), .Y(
n4607) );
INVX2TS U5876 ( .A(n8028), .Y(n4677) );
ADDFHX4TS U5877 ( .A(n4678), .B(n4677), .CI(n4679), .CO(n8117), .S(n4662) );
NAND2X8TS U5878 ( .A(n1630), .B(n1631), .Y(n5062) );
ADDFHX4TS U5879 ( .A(n4148), .B(n4147), .CI(n4146), .CO(n4157), .S(n4203) );
BUFX20TS U5880 ( .A(n2647), .Y(n8641) );
ADDFHX2TS U5881 ( .A(n8608), .B(n8607), .CI(n8606), .CO(n8637), .S(n8605) );
XNOR2X4TS U5882 ( .A(n2398), .B(n1633), .Y(n2628) );
OAI2BB2X2TS U5883 ( .B0(n8908), .B1(n4097), .A0N(n1378), .A1N(n3176), .Y(
n4347) );
CMPR22X2TS U5884 ( .A(n4348), .B(n4347), .CO(n4370), .S(n8523) );
ADDFHX4TS U5885 ( .A(n9779), .B(n9778), .CI(n9777), .CO(n4381), .S(n9817) );
XNOR2X4TS U5886 ( .A(n1634), .B(n2672), .Y(n3414) );
ADDFHX4TS U5887 ( .A(n7553), .B(n7552), .CI(n7551), .CO(n7577), .S(n7542) );
OAI22X4TS U5888 ( .A0(n795), .A1(n7019), .B0(n2114), .B1(n7087), .Y(n7121)
);
NAND2BX4TS U5889 ( .AN(n5982), .B(n6509), .Y(n2924) );
XNOR2X4TS U5890 ( .A(n11485), .B(n3881), .Y(n3530) );
ADDFHX4TS U5891 ( .A(n7283), .B(n7282), .CI(n7284), .CO(n7989), .S(n8037) );
ADDFHX4TS U5892 ( .A(n5937), .B(n5936), .CI(n5935), .CO(n5975), .S(n8255) );
OAI22X2TS U5893 ( .A0(n5926), .A1(n8938), .B0(n5693), .B1(n1940), .Y(n5936)
);
XNOR2X2TS U5894 ( .A(n8444), .B(n2408), .Y(n5926) );
OAI22X4TS U5895 ( .A0(n5306), .A1(n5255), .B0(n5304), .B1(n5305), .Y(n5347)
);
NOR2X6TS U5896 ( .A(n8451), .B(n8452), .Y(n2713) );
ADDFHX4TS U5897 ( .A(n6733), .B(n6732), .CI(n6731), .CO(n8300), .S(n8295) );
ADDFHX4TS U5898 ( .A(n5709), .B(n5708), .CI(n5707), .CO(n5715), .S(n5762) );
BUFX12TS U5899 ( .A(n8354), .Y(n2530) );
AOI2BB2X2TS U5900 ( .B0(n10871), .B1(n10876), .A0N(n2007), .A1N(n11863), .Y(
n12343) );
INVX16TS U5901 ( .A(n9399), .Y(n10935) );
XOR2X4TS U5902 ( .A(n2546), .B(n1635), .Y(n9830) );
OAI21X4TS U5903 ( .A0(n1609), .A1(n9386), .B0(n9385), .Y(n9387) );
ADDFHX4TS U5904 ( .A(n6316), .B(n6315), .CI(n1403), .CO(n6349), .S(n6345) );
XNOR2X4TS U5905 ( .A(n2456), .B(n8897), .Y(n8514) );
BUFX20TS U5906 ( .A(n8443), .Y(n2456) );
ADDFHX4TS U5907 ( .A(n8494), .B(n8493), .CI(n8492), .CO(n8600), .S(n8496) );
NAND2X4TS U5908 ( .A(n1299), .B(n2248), .Y(n9321) );
XOR2X4TS U5909 ( .A(n1890), .B(n1637), .Y(n4831) );
ADDFHX4TS U5910 ( .A(n4865), .B(n4864), .CI(n4863), .CO(n4874), .S(n4902) );
AOI21X4TS U5911 ( .A0(n9231), .A1(n9230), .B0(n9229), .Y(n9236) );
NOR2X1TS U5912 ( .A(n9224), .B(n9227), .Y(n9230) );
NAND2X2TS U5913 ( .A(n2596), .B(n4324), .Y(n2861) );
XOR2X4TS U5914 ( .A(n1638), .B(n5199), .Y(n5202) );
XOR2X4TS U5915 ( .A(n5201), .B(n5200), .Y(n1638) );
OR2X4TS U5916 ( .A(n8996), .B(n7529), .Y(n9053) );
NAND2X4TS U5917 ( .A(n8996), .B(n7529), .Y(n9052) );
XNOR2X4TS U5918 ( .A(n2079), .B(DP_OP_168J26_122_4811_n8480), .Y(n4830) );
OAI22X4TS U5919 ( .A0(n4240), .A1(n5345), .B0(n3854), .B1(n1889), .Y(n4218)
);
ADDFHX4TS U5920 ( .A(n6028), .B(n6026), .CI(n6027), .CO(n6064), .S(n6029) );
XNOR2X4TS U5921 ( .A(n3451), .B(n2445), .Y(n5706) );
ADDFHX4TS U5922 ( .A(n4690), .B(n4689), .CI(n4688), .CO(n4763), .S(n9916) );
AND2X4TS U5923 ( .A(n5369), .B(n2652), .Y(n4232) );
ADDFHX4TS U5924 ( .A(n3465), .B(n3466), .CI(n3464), .CO(n3478), .S(n3505) );
ADDFHX2TS U5925 ( .A(n9449), .B(n9450), .CI(n9451), .CO(n9472), .S(n9467) );
OAI22X4TS U5926 ( .A0(n3880), .A1(n5752), .B0(n5626), .B1(n6142), .Y(n5723)
);
ADDFHX4TS U5927 ( .A(n5725), .B(n5724), .CI(n5723), .CO(n5727), .S(n5770) );
NAND2X2TS U5928 ( .A(n3866), .B(n3865), .Y(n1783) );
NAND3X6TS U5929 ( .A(n1783), .B(n1781), .C(n1782), .Y(n4285) );
XOR2X4TS U5930 ( .A(n6373), .B(n8452), .Y(n1763) );
XNOR2X2TS U5931 ( .A(n2349), .B(n6775), .Y(n6639) );
NAND2X2TS U5932 ( .A(n10119), .B(n10118), .Y(n10120) );
OAI22X4TS U5933 ( .A0(n6431), .A1(n2577), .B0(n6437), .B1(n6434), .Y(n6537)
);
ADDFHX2TS U5934 ( .A(n7363), .B(n7364), .CI(n7362), .CO(n7404), .S(n7381) );
XOR2X4TS U5935 ( .A(n1640), .B(n5974), .Y(n8263) );
XOR2X4TS U5936 ( .A(n5975), .B(n5973), .Y(n1640) );
NOR2X4TS U5937 ( .A(n10714), .B(n10732), .Y(n10722) );
ADDHX4TS U5938 ( .A(n5015), .B(n5014), .CO(n5106), .S(n5028) );
ADDFHX4TS U5939 ( .A(n6508), .B(n6507), .CI(n6506), .CO(n8260), .S(n8274) );
ADDFHX2TS U5940 ( .A(n4472), .B(n4473), .CI(n4474), .CO(n4480), .S(n4496) );
ADDFHX2TS U5941 ( .A(n7102), .B(n7103), .CI(n7101), .CO(n7116), .S(n7119) );
OAI22X1TS U5942 ( .A0(n2379), .A1(n7448), .B0(n1897), .B1(n7476), .Y(n7467)
);
OAI22X2TS U5943 ( .A0(n11688), .A1(n2073), .B0(n5722), .B1(n7474), .Y(n5759)
);
NAND2X4TS U5944 ( .A(n6798), .B(n1752), .Y(n1643) );
XNOR2X4TS U5945 ( .A(n1492), .B(n8513), .Y(n8067) );
ADDFHX4TS U5946 ( .A(n7059), .B(n7058), .CI(n11752), .CO(n7028), .S(n7266)
);
NAND3X6TS U5947 ( .A(n2192), .B(n2198), .C(n2191), .Y(n2190) );
OAI21X4TS U5948 ( .A0(n7916), .A1(n7892), .B0(n7891), .Y(n7893) );
BUFX8TS U5949 ( .A(n5984), .Y(n2611) );
ADDFHX4TS U5950 ( .A(n8028), .B(n8027), .CI(n8026), .CO(n8116), .S(n8118) );
ADDFHX4TS U5951 ( .A(n8250), .B(n8248), .CI(n8249), .CO(n8265), .S(n8276) );
XNOR2X2TS U5952 ( .A(n8627), .B(n8510), .Y(n8082) );
ADDFHX2TS U5953 ( .A(n8102), .B(n8101), .CI(n8100), .CO(n8096), .S(n8962) );
NOR2X1TS U5954 ( .A(n8086), .B(n1920), .Y(n8102) );
ADDFHX2TS U5955 ( .A(n4727), .B(n4726), .CI(n4725), .CO(n8987), .S(n4771) );
OAI22X4TS U5956 ( .A0(n4687), .A1(n1894), .B0(n4686), .B1(n8935), .Y(n4725)
);
NOR2X4TS U5957 ( .A(n3348), .B(DP_OP_168J26_122_4811_n3229), .Y(n3349) );
NAND2X6TS U5958 ( .A(n3049), .B(n6874), .Y(n3161) );
OAI22X4TS U5959 ( .A0(n5753), .A1(n6087), .B0(n5590), .B1(n1938), .Y(n5755)
);
NAND2X2TS U5960 ( .A(n7521), .B(n7522), .Y(n1845) );
NAND2X4TS U5961 ( .A(n4395), .B(n4394), .Y(n3244) );
ADDFHX2TS U5962 ( .A(n4012), .B(n4011), .CI(n4010), .CO(n4391), .S(n4275) );
OAI22X4TS U5963 ( .A0(n1083), .A1(n5555), .B0(n974), .B1(n5605), .Y(n5558)
);
OAI22X2TS U5964 ( .A0(n7228), .A1(n2545), .B0(n7161), .B1(n2055), .Y(n7178)
);
NOR2BX4TS U5965 ( .AN(n2448), .B(n7489), .Y(n5888) );
XOR2X4TS U5966 ( .A(n1651), .B(n9808), .Y(n3124) );
ADDFHX4TS U5967 ( .A(n3990), .B(n1327), .CI(n3989), .CO(n10047), .S(n4422)
);
OAI22X2TS U5968 ( .A0(n5257), .A1(n2027), .B0(n1989), .B1(n5308), .Y(n5346)
);
ADDFHX4TS U5969 ( .A(n5269), .B(n5268), .CI(n5267), .CO(n5296), .S(n5258) );
INVX8TS U5970 ( .A(n8488), .Y(n8602) );
ADDFHX4TS U5971 ( .A(n6159), .B(n6158), .CI(n6157), .CO(n6230), .S(n6199) );
OAI22X2TS U5972 ( .A0(n4622), .A1(n9755), .B0(n4813), .B1(n2036), .Y(n4653)
);
XNOR2X4TS U5973 ( .A(n6055), .B(n1817), .Y(n5661) );
OR2X2TS U5974 ( .A(n6631), .B(n2108), .Y(n1654) );
OR2X2TS U5975 ( .A(n6587), .B(n1955), .Y(n1655) );
NAND2X4TS U5976 ( .A(n1654), .B(n1655), .Y(n6618) );
OAI21X4TS U5977 ( .A0(n9580), .A1(n8425), .B0(n8426), .Y(n7583) );
ADDFHX4TS U5978 ( .A(n8119), .B(n8118), .CI(n8117), .CO(n8129), .S(n8199) );
XNOR2X4TS U5979 ( .A(n1881), .B(n6156), .Y(n5680) );
NAND2X2TS U5980 ( .A(n4286), .B(n4285), .Y(n2431) );
XOR2X4TS U5981 ( .A(n1656), .B(n9827), .Y(n9870) );
XOR2X4TS U5982 ( .A(n958), .B(n9828), .Y(n1656) );
NAND2X4TS U5983 ( .A(n7339), .B(n7340), .Y(n2966) );
NOR2X4TS U5984 ( .A(n7339), .B(n7340), .Y(n2967) );
INVX6TS U5985 ( .A(n7595), .Y(n7340) );
XNOR2X4TS U5986 ( .A(n1657), .B(n5440), .Y(n5456) );
XNOR2X4TS U5987 ( .A(n5442), .B(n5441), .Y(n1657) );
OAI22X4TS U5988 ( .A0(n8628), .A1(n2109), .B0(n8588), .B1(n1962), .Y(n9796)
);
XNOR2X4TS U5989 ( .A(n1659), .B(n1258), .Y(n4127) );
ADDFHX4TS U5990 ( .A(n5969), .B(n5968), .CI(n5967), .CO(n6243), .S(n6259) );
OAI21X4TS U5991 ( .A0(n1326), .A1(n9130), .B0(n2628), .Y(n2627) );
OAI22X2TS U5992 ( .A0(n4598), .A1(n5318), .B0(n1880), .B1(n4669), .Y(n4664)
);
XNOR2X4TS U5993 ( .A(n2634), .B(n2406), .Y(n5236) );
OAI21X4TS U5994 ( .A0(n5389), .A1(n5388), .B0(n5387), .Y(n2660) );
OAI22X2TS U5995 ( .A0(n5565), .A1(n2102), .B0(n6040), .B1(n5604), .Y(n5574)
);
XNOR2X4TS U5996 ( .A(n1660), .B(n6903), .Y(n6935) );
XNOR2X4TS U5997 ( .A(n6904), .B(n6902), .Y(n1660) );
XNOR2X2TS U5998 ( .A(n7273), .B(Op_MY[25]), .Y(n7023) );
OAI22X4TS U5999 ( .A0(n5950), .A1(n5949), .B0(n822), .B1(n5948), .Y(n6225)
);
OAI22X4TS U6000 ( .A0(n1981), .A1(n5322), .B0(n8013), .B1(n4230), .Y(n5394)
);
AO21X2TS U6001 ( .A0(n1607), .A1(n2114), .B0(n7139), .Y(n7218) );
OAI22X2TS U6002 ( .A0(n1857), .A1(n879), .B0(DP_OP_168J26_122_4811_n6608),
.B1(n11785), .Y(n3731) );
NAND2X8TS U6003 ( .A(n3006), .B(n9768), .Y(n3005) );
AND2X4TS U6004 ( .A(n4962), .B(n2786), .Y(n4959) );
NAND2BX4TS U6005 ( .AN(n5485), .B(n4764), .Y(n2878) );
XNOR2X4TS U6006 ( .A(n7275), .B(n2409), .Y(n3962) );
ADDFHX2TS U6007 ( .A(n3451), .B(n2341), .CI(n3450), .CO(n4501), .S(n3426) );
OAI2BB1X2TS U6008 ( .A0N(n4853), .A1N(n4852), .B0(n2810), .Y(n5198) );
OAI22X4TS U6009 ( .A0(n8069), .A1(n1895), .B0(n8068), .B1(n8577), .Y(n8073)
);
XNOR2X4TS U6010 ( .A(n1819), .B(n1967), .Y(n8069) );
OAI2BB2X4TS U6011 ( .B0(n2046), .B1(n4668), .A0N(n1663), .A1N(n1664), .Y(
n4665) );
OAI22X4TS U6012 ( .A0(n7445), .A1(n4142), .B0(n1918), .B1(n3899), .Y(n4111)
);
OAI22X2TS U6013 ( .A0(n4514), .A1(n1894), .B0(n4513), .B1(n2019), .Y(n4713)
);
XOR2X2TS U6014 ( .A(n3598), .B(n3095), .Y(n3599) );
NAND2X4TS U6015 ( .A(n3598), .B(n3102), .Y(n3259) );
XOR2X4TS U6016 ( .A(n3840), .B(n3841), .Y(n2798) );
ADDFHX4TS U6017 ( .A(n5807), .B(n5806), .CI(n5808), .CO(n5809), .S(n6241) );
OAI22X2TS U6018 ( .A0(n8978), .A1(n8977), .B0(n8976), .B1(n2581), .Y(n9010)
);
XOR2X4TS U6019 ( .A(n5174), .B(n3085), .Y(n3084) );
NAND2X4TS U6020 ( .A(n2489), .B(n9326), .Y(n1665) );
NAND2X6TS U6021 ( .A(n2952), .B(n777), .Y(n2951) );
ADDFHX4TS U6022 ( .A(n7451), .B(n1670), .CI(n7450), .CO(n7494), .S(n7457) );
ADDFHX2TS U6023 ( .A(n6490), .B(n6489), .CI(n6488), .CO(n8246), .S(n6516) );
NOR2X4TS U6024 ( .A(n8770), .B(n8769), .Y(n9034) );
ADDFHX4TS U6025 ( .A(n9843), .B(n9841), .CI(n9842), .CO(n9846), .S(n9845) );
OAI22X4TS U6026 ( .A0(n2090), .A1(n4187), .B0(n1227), .B1(n1811), .Y(n4198)
);
OAI22X4TS U6027 ( .A0(n2090), .A1(n5682), .B0(n4187), .B1(n6142), .Y(n5886)
);
ADDFHX4TS U6028 ( .A(n4198), .B(n4199), .CI(n4197), .CO(n4191), .S(n6330) );
ADDFHX4TS U6029 ( .A(n6916), .B(n6915), .CI(n3147), .CO(n6963), .S(n6960) );
NAND2BX2TS U6030 ( .AN(n6884), .B(n6636), .Y(n6634) );
OR2X4TS U6031 ( .A(n9458), .B(n1361), .Y(n9477) );
CLKINVX6TS U6032 ( .A(n9042), .Y(n9458) );
BUFX20TS U6033 ( .A(DP_OP_168J26_122_4811_n5162), .Y(n2434) );
OAI21X2TS U6034 ( .A0(n4953), .A1(n4954), .B0(n4955), .Y(n2419) );
ADDFHX4TS U6035 ( .A(n4917), .B(n4916), .CI(n4915), .CO(n4904), .S(n4954) );
ADDFHX4TS U6036 ( .A(n4960), .B(n4961), .CI(n4959), .CO(n4953), .S(n5109) );
NAND2X2TS U6037 ( .A(n8229), .B(n877), .Y(n10089) );
XOR2X4TS U6038 ( .A(n1019), .B(n1558), .Y(n8531) );
OAI22X2TS U6039 ( .A0(n4072), .A1(n9456), .B0(n4257), .B1(n2331), .Y(n4085)
);
XNOR2X4TS U6040 ( .A(n1220), .B(n1816), .Y(n4458) );
XNOR2X4TS U6041 ( .A(DP_OP_168J26_122_4811_n6776), .B(n951), .Y(n3397) );
ADDFHX4TS U6042 ( .A(n4177), .B(n4178), .CI(n4176), .CO(n4184), .S(n6313) );
ADDFHX4TS U6043 ( .A(n9101), .B(n9099), .CI(n9100), .CO(n9094), .S(n9118) );
OAI22X2TS U6044 ( .A0(n4778), .A1(n1886), .B0(n2055), .B1(n8951), .Y(n8997)
);
OAI22X4TS U6045 ( .A0(n3460), .A1(n2100), .B0(n3416), .B1(n7471), .Y(n3462)
);
OAI22X2TS U6046 ( .A0(n730), .A1(n3482), .B0(n1916), .B1(n3460), .Y(n3502)
);
ADDFHX4TS U6047 ( .A(n3541), .B(n3542), .CI(n3540), .CO(n3551), .S(n3889) );
ADDFHX4TS U6048 ( .A(n4783), .B(n4784), .CI(n4782), .CO(n7456), .S(n4789) );
ADDFHX4TS U6049 ( .A(n5698), .B(n5697), .CI(n5696), .CO(n5837), .S(n5973) );
OAI22X4TS U6050 ( .A0(n7169), .A1(n1895), .B0(n7223), .B1(n8935), .Y(n7208)
);
OAI22X2TS U6051 ( .A0(n5570), .A1(n823), .B0(n2450), .B1(n5649), .Y(n5645)
);
ADDFHX4TS U6052 ( .A(n4046), .B(n4045), .CI(n4044), .CO(n4037), .S(n4248) );
XNOR2X4TS U6053 ( .A(n2626), .B(n1668), .Y(n9910) );
OAI22X2TS U6054 ( .A0(n5661), .A1(n2102), .B0(n6040), .B1(n5860), .Y(n5858)
);
ADDFHX4TS U6055 ( .A(n5858), .B(n5857), .CI(n5856), .CO(n6321), .S(n5878) );
NOR2X1TS U6056 ( .A(n8551), .B(n1970), .Y(n7193) );
ADDFHX4TS U6057 ( .A(n4850), .B(n4851), .CI(n4849), .CO(n4852), .S(n4901) );
XOR2X4TS U6058 ( .A(n1673), .B(n3124), .Y(DP_OP_168J26_122_4811_n1222) );
XNOR2X2TS U6059 ( .A(n2079), .B(DP_OP_168J26_122_4811_n6559), .Y(n3803) );
XNOR2X2TS U6060 ( .A(n1861), .B(DP_OP_168J26_122_4811_n6559), .Y(n8014) );
INVX6TS U6061 ( .A(n9853), .Y(n1674) );
ADDFHX4TS U6062 ( .A(n3682), .B(n3681), .CI(n3680), .CO(n3733), .S(n3723) );
OAI22X2TS U6063 ( .A0(n6223), .A1(n6099), .B0(n11754), .B1(n6098), .Y(n6122)
);
OAI22X2TS U6064 ( .A0(n4513), .A1(n1894), .B0(n4687), .B1(n2019), .Y(n4512)
);
ADDFHX4TS U6065 ( .A(n3871), .B(n3872), .CI(n3870), .CO(n4310), .S(n4336) );
OAI22X4TS U6066 ( .A0(n3792), .A1(n2067), .B0(n3931), .B1(n1893), .Y(n3871)
);
XNOR2X2TS U6067 ( .A(n4003), .B(n4059), .Y(n5544) );
OAI22X4TS U6068 ( .A0(n3669), .A1(n1923), .B0(n1822), .B1(n3045), .Y(n3656)
);
XNOR2X4TS U6069 ( .A(n2931), .B(n1324), .Y(n2900) );
OAI22X2TS U6070 ( .A0(n8015), .A1(n7023), .B0(n2568), .B1(n7018), .Y(n7030)
);
NAND2X2TS U6071 ( .A(n7522), .B(n889), .Y(n1844) );
XNOR2X4TS U6072 ( .A(n4897), .B(n4896), .Y(n2156) );
NOR2X8TS U6073 ( .A(n2561), .B(n1233), .Y(n9320) );
ADDFHX2TS U6074 ( .A(n4700), .B(n4701), .CI(n4699), .CO(n4649), .S(n4722) );
CLKINVX6TS U6075 ( .A(n8251), .Y(n1735) );
OAI22X4TS U6076 ( .A0(n5924), .A1(n1908), .B0(n5532), .B1(n1862), .Y(n5921)
);
OAI22X2TS U6077 ( .A0(n4368), .A1(n9456), .B0(n4349), .B1(n8931), .Y(n8522)
);
OAI22X2TS U6078 ( .A0(n5815), .A1(n2108), .B0(n5832), .B1(n8641), .Y(n5824)
);
ADDFHX4TS U6079 ( .A(n5934), .B(n5933), .CI(n5932), .CO(n5822), .S(n8256) );
NAND2BX4TS U6080 ( .AN(n8776), .B(n1677), .Y(DP_OP_168J26_122_4811_n768) );
ADDFHX2TS U6081 ( .A(n6213), .B(n6214), .CI(n6212), .CO(n6250), .S(n6216) );
ADDFHX4TS U6082 ( .A(n6218), .B(n6219), .CI(n6220), .CO(n6261), .S(n6264) );
XNOR2X4TS U6083 ( .A(n2470), .B(n1678), .Y(n8292) );
INVX6TS U6084 ( .A(n10035), .Y(DP_OP_168J26_122_4811_n743) );
OAI22X2TS U6085 ( .A0(n8015), .A1(n3820), .B0(n8013), .B1(n3693), .Y(n3797)
);
ADDFHX4TS U6086 ( .A(n5953), .B(n5952), .CI(n5951), .CO(n5959), .S(n6248) );
OAI22X4TS U6087 ( .A0(n7486), .A1(n7443), .B0(n1364), .B1(n7485), .Y(n7465)
);
ADDFHX4TS U6088 ( .A(n7453), .B(n7454), .CI(n7452), .CO(n7493), .S(n7460) );
XNOR2X2TS U6089 ( .A(n6884), .B(n6636), .Y(n6637) );
OAI22X2TS U6090 ( .A0(n3397), .A1(n5571), .B0(n2063), .B1(n954), .Y(n3443)
);
OAI22X2TS U6091 ( .A0(n4580), .A1(n1880), .B0(n975), .B1(n4528), .Y(n4560)
);
OAI22X4TS U6092 ( .A0(n1910), .A1(n4432), .B0(n1364), .B1(n4431), .Y(n4470)
);
INVX8TS U6093 ( .A(n1681), .Y(n4055) );
ADDFHX4TS U6094 ( .A(n7155), .B(n7154), .CI(n7153), .CO(n7180), .S(n7289) );
OAI22X2TS U6095 ( .A0(n6423), .A1(n6919), .B0(n5988), .B1(n1852), .Y(n6508)
);
OAI22X2TS U6096 ( .A0(n2447), .A1(n4975), .B0(n1901), .B1(n4977), .Y(n4988)
);
ADDFHX2TS U6097 ( .A(n5691), .B(n5690), .CI(n5689), .CO(n8456), .S(n5738) );
OAI21X4TS U6098 ( .A0(n1691), .A1(n8854), .B0(n8855), .Y(n7808) );
OAI22X4TS U6099 ( .A0(n1941), .A1(n5181), .B0(n4860), .B1(n5302), .Y(n5140)
);
ADDFHX4TS U6100 ( .A(n4566), .B(n4565), .CI(n4564), .CO(n4583), .S(n4547) );
ADDFHX4TS U6101 ( .A(n4551), .B(n4552), .CI(n4550), .CO(n4572), .S(n4564) );
OAI22X2TS U6102 ( .A0(DP_OP_168J26_122_4811_n6594), .A1(n11768), .B0(n2013),
.B1(n11782), .Y(n4533) );
OAI22X4TS U6103 ( .A0(n2110), .A1(n4229), .B0(n1898), .B1(n4042), .Y(n4245)
);
XNOR2X4TS U6104 ( .A(n5251), .B(n7272), .Y(n4229) );
XNOR2X4TS U6105 ( .A(DP_OP_168J26_122_4811_n6641), .B(n1034), .Y(n5158) );
NAND2X4TS U6106 ( .A(n7626), .B(n2190), .Y(n2189) );
NAND2X2TS U6107 ( .A(n10954), .B(n10795), .Y(n10797) );
INVX8TS U6108 ( .A(n6181), .Y(n1882) );
OAI22X4TS U6109 ( .A0(n1910), .A1(n3487), .B0(n2030), .B1(n3459), .Y(n3503)
);
ADDHX4TS U6110 ( .A(n6641), .B(n6640), .CO(n6607), .S(n6671) );
OAI22X2TS U6111 ( .A0(DP_OP_168J26_122_4811_n5162), .A1(n3319), .B0(n765),
.B1(n12029), .Y(n7214) );
OAI22X2TS U6112 ( .A0(DP_OP_168J26_122_4811_n5162), .A1(n11765), .B0(n2550),
.B1(n1741), .Y(n7991) );
OAI22X2TS U6113 ( .A0(DP_OP_168J26_122_4811_n5162), .A1(n11781), .B0(n2550),
.B1(DP_OP_168J26_122_4811_n6172), .Y(n7062) );
NAND2X4TS U6114 ( .A(n5473), .B(n2746), .Y(n2744) );
XNOR2X2TS U6115 ( .A(n1831), .B(n1034), .Y(n4977) );
XNOR2X2TS U6116 ( .A(n5251), .B(DP_OP_168J26_122_4811_n8479), .Y(n5012) );
ADDFHX4TS U6117 ( .A(n7460), .B(n7459), .CI(n7458), .CO(n7481), .S(n7461) );
BUFX20TS U6118 ( .A(n914), .Y(n2364) );
OAI21X4TS U6119 ( .A0(n2201), .A1(n9400), .B0(n9399), .Y(n9404) );
NAND2X8TS U6120 ( .A(n1699), .B(n4898), .Y(n2637) );
ADDFHX4TS U6121 ( .A(n4169), .B(n4168), .CI(n4167), .CO(n4147), .S(n6310) );
INVX4TS U6122 ( .A(n6468), .Y(n6531) );
OAI22X2TS U6123 ( .A0(n5007), .A1(n5302), .B0(DP_OP_168J26_122_4811_n6618),
.B1(n5006), .Y(n5051) );
NAND2X2TS U6124 ( .A(n1044), .B(n1045), .Y(n1754) );
ADDFHX4TS U6125 ( .A(n3897), .B(n3898), .CI(n3896), .CO(n3885), .S(n4153) );
NAND2X4TS U6126 ( .A(n1005), .B(n3703), .Y(n2700) );
ADDFHX4TS U6127 ( .A(n6412), .B(n6410), .CI(n6411), .CO(n6493), .S(n6541) );
AOI21X4TS U6128 ( .A0(n8402), .A1(n8392), .B0(n7531), .Y(n7532) );
XNOR2X4TS U6129 ( .A(Op_MY[23]), .B(n2483), .Y(n2870) );
OAI22X2TS U6130 ( .A0(n4005), .A1(n2113), .B0(n3928), .B1(n1960), .Y(n3870)
);
XNOR2X4TS U6131 ( .A(n2348), .B(n8548), .Y(n3928) );
ADDFHX4TS U6132 ( .A(n3436), .B(n3437), .CI(n3438), .CO(n3454), .S(n3476) );
CLKBUFX2TS U6133 ( .A(n8189), .Y(n2651) );
XNOR2X4TS U6134 ( .A(n2203), .B(n1144), .Y(n1692) );
OAI22X4TS U6135 ( .A0(n8580), .A1(n967), .B0(n8582), .B1(n8581), .Y(n8633)
);
ADDFHX4TS U6136 ( .A(n3480), .B(n1687), .CI(n3479), .CO(n3483), .S(n3521) );
OAI21X2TS U6137 ( .A0(n3521), .A1(n3522), .B0(n3520), .Y(n3010) );
OAI22X2TS U6138 ( .A0(n6069), .A1(n6145), .B0(n2450), .B1(n2521), .Y(n3479)
);
XOR2X4TS U6139 ( .A(n5904), .B(n1695), .Y(n5913) );
NAND3X8TS U6140 ( .A(n1697), .B(n1696), .C(n1698), .Y(n5910) );
OAI22X4TS U6141 ( .A0(n5830), .A1(n6919), .B0(n1852), .B1(n5896), .Y(n5905)
);
INVX16TS U6142 ( .A(n1689), .Y(n5254) );
ADDFHX4TS U6143 ( .A(n5908), .B(n5907), .CI(n5906), .CO(n8487), .S(n5909) );
NOR2X4TS U6144 ( .A(n3606), .B(n3558), .Y(n3561) );
OR2X8TS U6145 ( .A(n4899), .B(n4900), .Y(n1699) );
OR2X8TS U6146 ( .A(n4286), .B(n4285), .Y(n1700) );
AOI2BB2X2TS U6147 ( .B0(n10871), .B1(n10875), .A0N(n10870), .A1N(n11865),
.Y(n12350) );
NOR2X4TS U6148 ( .A(n9420), .B(n9425), .Y(n7934) );
ADDFHX4TS U6149 ( .A(n8984), .B(n8983), .CI(n8982), .CO(n8974), .S(n9109) );
ADDFHX4TS U6150 ( .A(n5797), .B(n5798), .CI(n5799), .CO(n5811), .S(n5957) );
ADDFHX4TS U6151 ( .A(n8647), .B(n8645), .CI(n8646), .CO(n8682), .S(n8651) );
OAI22X2TS U6152 ( .A0(n8462), .A1(n8938), .B0(n8507), .B1(n1940), .Y(n8647)
);
ADDFHX4TS U6153 ( .A(n8506), .B(n8505), .CI(n8504), .CO(n8650), .S(n8645) );
ADDFHX4TS U6154 ( .A(n4109), .B(n4108), .CI(n4107), .CO(n4154), .S(n4183) );
ADDFHX4TS U6155 ( .A(n4246), .B(n4245), .CI(n4244), .CO(n4249), .S(n5399) );
ADDFHX4TS U6156 ( .A(n5868), .B(n5869), .CI(n5870), .CO(n6317), .S(n6327) );
ADDFHX4TS U6157 ( .A(n5548), .B(n5547), .CI(n5546), .CO(n5635), .S(n5826) );
ADDFHX2TS U6158 ( .A(n6301), .B(n6300), .CI(n6302), .CO(n6334), .S(n6320) );
OAI22X4TS U6159 ( .A0(n2018), .A1(n4114), .B0(n2038), .B1(n3883), .Y(n4119)
);
ADDFHX4TS U6160 ( .A(n5854), .B(n5853), .CI(n5855), .CO(n6322), .S(n5851) );
INVX8TS U6161 ( .A(n2719), .Y(n2844) );
INVX4TS U6162 ( .A(n5447), .Y(n1771) );
OAI22X4TS U6163 ( .A0(n2090), .A1(n5626), .B0(n5625), .B1(n1227), .Y(n5711)
);
XNOR2X4TS U6164 ( .A(n1812), .B(n1694), .Y(n5625) );
XNOR2X4TS U6165 ( .A(n8892), .B(n1904), .Y(n4362) );
BUFX16TS U6166 ( .A(n1286), .Y(n1890) );
OAI22X4TS U6167 ( .A0(n2073), .A1(n5621), .B0(n1897), .B1(n5588), .Y(n5612)
);
XNOR2X2TS U6168 ( .A(n2014), .B(n820), .Y(n4580) );
ADDFHX4TS U6169 ( .A(n5525), .B(n5523), .CI(n5524), .CO(n5509), .S(n5700) );
ADDFHX4TS U6170 ( .A(n5385), .B(n5384), .CI(n5386), .CO(n5404), .S(n5422) );
OAI22X4TS U6171 ( .A0(n5828), .A1(n1968), .B0(n5898), .B1(n8629), .Y(n5902)
);
XNOR2X4TS U6172 ( .A(n8550), .B(n2410), .Y(n5898) );
ADDFHX4TS U6173 ( .A(n6470), .B(n6471), .CI(n6469), .CO(n6487), .S(n6513) );
OAI22X4TS U6174 ( .A0(n3876), .A1(n6003), .B0(n3536), .B1(n973), .Y(n3910)
);
XOR2X4TS U6175 ( .A(n1289), .B(n1741), .Y(n4023) );
XNOR2X4TS U6176 ( .A(n1712), .B(n9967), .Y(DP_OP_168J26_122_4811_n984) );
ADDFHX4TS U6177 ( .A(n4987), .B(n4986), .CI(n4985), .CO(n5021), .S(n4997) );
OAI22X4TS U6178 ( .A0(n5302), .A1(n2993), .B0(n4979), .B1(n1941), .Y(n4986)
);
XOR2X2TS U6179 ( .A(n1831), .B(n945), .Y(n5176) );
ADDHX4TS U6180 ( .A(n5777), .B(n5776), .CO(n5529), .S(n5931) );
ADDFHX4TS U6181 ( .A(n8689), .B(n8687), .CI(n8688), .CO(n8690), .S(n8695) );
ADDFHX2TS U6182 ( .A(n8660), .B(n8661), .CI(n8659), .CO(n8685), .S(n8689) );
OAI22X2TS U6183 ( .A0(n1866), .A1(n5606), .B0(n2063), .B1(n5662), .Y(n5658)
);
NAND2X2TS U6184 ( .A(n10773), .B(n10772), .Y(n10774) );
NAND2X4TS U6185 ( .A(n6286), .B(n935), .Y(n10167) );
ADDFHX4TS U6186 ( .A(n6496), .B(n6495), .CI(n6494), .CO(n8254), .S(n8259) );
ADDFHX4TS U6187 ( .A(n6501), .B(n6500), .CI(n6502), .CO(n8257), .S(n6505) );
NAND2X4TS U6188 ( .A(n3042), .B(n5475), .Y(n9630) );
OAI21X4TS U6189 ( .A0(n9609), .A1(n9602), .B0(n9610), .Y(n7942) );
NOR2X4TS U6190 ( .A(n10955), .B(n9593), .Y(n9310) );
ADDFHX4TS U6191 ( .A(n5151), .B(n5152), .CI(n5150), .CO(n5239), .S(n5192) );
ADDFHX4TS U6192 ( .A(n5398), .B(n5397), .CI(n5396), .CO(n5375), .S(n5425) );
OAI22X4TS U6193 ( .A0(n5300), .A1(n2087), .B0(n1924), .B1(n4224), .Y(n5398)
);
INVX16TS U6194 ( .A(n5253), .Y(n1884) );
ADDFHX4TS U6195 ( .A(n5299), .B(n5298), .CI(n5297), .CO(n5418), .S(n5295) );
OAI22X4TS U6196 ( .A0(n6802), .A1(n8612), .B0(n6824), .B1(n8614), .Y(n6817)
);
BUFX20TS U6197 ( .A(n5794), .Y(n6223) );
OAI22X2TS U6198 ( .A0(n2029), .A1(n5573), .B0(n1938), .B1(n5569), .Y(n5556)
);
NAND2X6TS U6199 ( .A(n2954), .B(n9857), .Y(n2953) );
OAI22X4TS U6200 ( .A0(n2222), .A1(n8008), .B0(n8009), .B1(n7271), .Y(n7990)
);
ADDFHX4TS U6201 ( .A(n5838), .B(n5836), .CI(n5837), .CO(n5916), .S(n5912) );
OAI22X2TS U6202 ( .A0(n3662), .A1(n1925), .B0(n5302), .B1(n3675), .Y(n3705)
);
OAI22X2TS U6203 ( .A0(n2088), .A1(n4978), .B0(n1941), .B1(n4965), .Y(n5027)
);
OAI22X2TS U6204 ( .A0(n4956), .A1(n2088), .B0(n1941), .B1(n4919), .Y(n4960)
);
OAI22X4TS U6205 ( .A0(n4355), .A1(n5488), .B0(n8931), .B1(n4354), .Y(n8464)
);
XNOR2X1TS U6206 ( .A(n7277), .B(DP_OP_168J26_122_4811_n8486), .Y(n1719) );
OAI22X2TS U6207 ( .A0(n5579), .A1(n2073), .B0(n1896), .B1(n5650), .Y(n5671)
);
ADDFHX4TS U6208 ( .A(n9819), .B(n9820), .CI(n9821), .CO(n9841), .S(n9823) );
OAI2BB2X4TS U6209 ( .B0(n3679), .B1(n981), .A0N(n1721), .A1N(n1722), .Y(
n3691) );
OAI22X4TS U6210 ( .A0(n2185), .A1(n8020), .B0(n4837), .B1(n5309), .Y(n4864)
);
OAI22X4TS U6211 ( .A0(n3800), .A1(n2071), .B0(n1958), .B1(n11582), .Y(n3795)
);
ADDFHX4TS U6212 ( .A(n3977), .B(n3978), .CI(n3979), .CO(n4565), .S(n3954) );
ADDFHX4TS U6213 ( .A(n5824), .B(n5823), .CI(n5822), .CO(n5786), .S(n5995) );
XOR2X4TS U6214 ( .A(n11499), .B(n2380), .Y(n5719) );
XNOR2X4TS U6215 ( .A(n2298), .B(n1724), .Y(n1723) );
INVX16TS U6216 ( .A(n1723), .Y(n3591) );
OAI22X4TS U6217 ( .A0(n3854), .A1(n2096), .B0(n1324), .B1(n1889), .Y(n4033)
);
BUFX12TS U6218 ( .A(n3677), .Y(n1820) );
XNOR2X4TS U6219 ( .A(n2634), .B(n5254), .Y(n3828) );
BUFX12TS U6220 ( .A(DP_OP_168J26_122_4811_n6614), .Y(n8020) );
XOR2X4TS U6221 ( .A(n5062), .B(n5063), .Y(n1742) );
INVX8TS U6222 ( .A(n1725), .Y(n1726) );
AO21X4TS U6223 ( .A0(n1959), .A1(n1516), .B0(n11582), .Y(n3686) );
INVX6TS U6224 ( .A(n10984), .Y(n2695) );
INVX8TS U6225 ( .A(n10979), .Y(n10982) );
XNOR2X4TS U6226 ( .A(n3202), .B(n11581), .Y(n3675) );
XOR2X4TS U6227 ( .A(n5446), .B(n2836), .Y(n2835) );
ADDFHX4TS U6228 ( .A(n5445), .B(n5444), .CI(n5443), .CO(n1727), .S(n1731) );
ADDFHX4TS U6229 ( .A(n5282), .B(n5280), .CI(n5281), .CO(n5337), .S(n5262) );
XOR2X4TS U6230 ( .A(n1732), .B(n5918), .Y(n8286) );
XOR2X4TS U6231 ( .A(n5920), .B(n5919), .Y(n1732) );
NOR2X2TS U6232 ( .A(n11619), .B(n11620), .Y(n7764) );
NOR2X8TS U6233 ( .A(n3099), .B(n789), .Y(n11001) );
XNOR2X4TS U6234 ( .A(n2045), .B(n2625), .Y(n4019) );
OAI22X4TS U6235 ( .A0(n2447), .A1(n11582), .B0(n5038), .B1(n1959), .Y(n6780)
);
OAI22X4TS U6236 ( .A0(n5309), .A1(n3829), .B0(n8020), .B1(n3815), .Y(n3847)
);
ADDFHX4TS U6237 ( .A(n8600), .B(n8601), .CI(n8602), .CO(n8707), .S(n8703) );
OAI22X4TS U6238 ( .A0(n1914), .A1(n5578), .B0(n3321), .B1(n5679), .Y(n5643)
);
ADDFHX4TS U6239 ( .A(n3799), .B(n3798), .CI(n3797), .CO(n3810), .S(n3836) );
OAI22X2TS U6240 ( .A0(n4838), .A1(n975), .B0(n979), .B1(n4856), .Y(n4863) );
OAI22X4TS U6241 ( .A0(n1822), .A1(n7015), .B0(n1950), .B1(n7017), .Y(n7026)
);
AO21X4TS U6242 ( .A0(n1951), .A1(n1822), .B0(n11683), .Y(n9459) );
ADDFHX4TS U6243 ( .A(n5827), .B(n5825), .CI(n5826), .CO(n5690), .S(n5903) );
OAI22X2TS U6244 ( .A0(n3694), .A1(n3677), .B0(n3678), .B1(n5304), .Y(n3716)
);
XOR2X4TS U6245 ( .A(n5380), .B(n5378), .Y(n1746) );
OAI22X4TS U6246 ( .A0(n5345), .A1(n4832), .B0(n4831), .B1(n5343), .Y(n4844)
);
XNOR2X4TS U6247 ( .A(n5270), .B(n5237), .Y(n5324) );
XNOR2X4TS U6248 ( .A(n1729), .B(n1832), .Y(n3046) );
NAND2BX4TS U6249 ( .AN(n1733), .B(n1224), .Y(n1748) );
XOR2X4TS U6250 ( .A(n6819), .B(n1734), .Y(n3174) );
NAND2X2TS U6251 ( .A(n3833), .B(n1615), .Y(n1766) );
ADDFHX4TS U6252 ( .A(n4946), .B(n4945), .CI(n4944), .CO(n4955), .S(n5096) );
INVX6TS U6253 ( .A(n10791), .Y(n5132) );
OAI22X4TS U6254 ( .A0(n4229), .A1(n1899), .B0(n5331), .B1(n5329), .Y(n5395)
);
XNOR2X4TS U6255 ( .A(n5251), .B(DP_OP_168J26_122_4811_n6559), .Y(n5329) );
XOR2X2TS U6256 ( .A(n1832), .B(n956), .Y(n4914) );
OR2X4TS U6257 ( .A(n2451), .B(n759), .Y(n11112) );
BUFX6TS U6258 ( .A(n5982), .Y(n2490) );
OAI21X4TS U6259 ( .A0(n11305), .A1(n11301), .B0(n11302), .Y(n11058) );
NAND2X4TS U6260 ( .A(n4000), .B(n3999), .Y(n3158) );
XOR2X4TS U6261 ( .A(n6783), .B(n6759), .Y(n2853) );
OAI22X4TS U6262 ( .A0(n6918), .A1(n1985), .B0(n6699), .B1(n1933), .Y(n6967)
);
BUFX6TS U6263 ( .A(n6613), .Y(n2479) );
ADDFHX2TS U6264 ( .A(n5383), .B(n5382), .CI(n5381), .CO(n5401), .S(n5423) );
CLKINVX12TS U6265 ( .A(n5695), .Y(n5974) );
ADDFHX2TS U6266 ( .A(n6444), .B(n6443), .CI(n6442), .CO(n1738) );
ADDFHX4TS U6267 ( .A(n6444), .B(n6443), .CI(n6442), .CO(n6440), .S(n6727) );
XNOR2X4TS U6268 ( .A(n3072), .B(n1388), .Y(n1739) );
INVX8TS U6269 ( .A(n2208), .Y(n5984) );
NOR2X4TS U6270 ( .A(n3224), .B(n3223), .Y(n3222) );
NAND2X6TS U6271 ( .A(n7004), .B(n7005), .Y(n8180) );
XNOR2X4TS U6272 ( .A(n1740), .B(n1325), .Y(n5454) );
XOR2X4TS U6273 ( .A(n5450), .B(n5451), .Y(n1740) );
XOR2X4TS U6274 ( .A(n1832), .B(n1741), .Y(n4834) );
INVX2TS U6275 ( .A(n2989), .Y(n10099) );
NOR2X6TS U6276 ( .A(n2237), .B(n2989), .Y(n2654) );
ADDFHX4TS U6277 ( .A(n5395), .B(n5394), .CI(n5393), .CO(n5403), .S(n5426) );
NAND2X4TS U6278 ( .A(n6953), .B(n6951), .Y(n3261) );
NAND2X8TS U6279 ( .A(n5362), .B(n9262), .Y(n2692) );
NAND2X2TS U6280 ( .A(n5062), .B(n5063), .Y(n1745) );
NAND3X6TS U6281 ( .A(n1744), .B(n1743), .C(n1745), .Y(n5088) );
XOR2X4TS U6282 ( .A(n1224), .B(n1746), .Y(n5419) );
NAND2X2TS U6283 ( .A(n5378), .B(n5380), .Y(n1749) );
NAND3X6TS U6284 ( .A(n1747), .B(n1748), .C(n1749), .Y(n5424) );
OAI22X4TS U6285 ( .A0(n2111), .A1(n5330), .B0(n5329), .B1(
DP_OP_168J26_122_4811_n6619), .Y(n5378) );
INVX6TS U6286 ( .A(n6439), .Y(n6442) );
NAND2X4TS U6287 ( .A(n1636), .B(n5695), .Y(n10984) );
OR2X4TS U6288 ( .A(n6743), .B(n6746), .Y(n1750) );
INVX6TS U6289 ( .A(n9632), .Y(n3049) );
INVX2TS U6290 ( .A(n6768), .Y(n6898) );
NAND3X6TS U6291 ( .A(n1754), .B(n1753), .C(n1755), .Y(n4052) );
MXI2X4TS U6292 ( .A(n9716), .B(n11946), .S0(n11153), .Y(n3314) );
XOR2X4TS U6293 ( .A(n4844), .B(n4845), .Y(n1757) );
XOR2X4TS U6294 ( .A(n4843), .B(n1757), .Y(n4884) );
NAND2X2TS U6295 ( .A(n4845), .B(n4844), .Y(n1758) );
NAND2X8TS U6296 ( .A(n2732), .B(n2640), .Y(n10792) );
MXI2X4TS U6297 ( .A(n10267), .B(n12147), .S0(n11153), .Y(n613) );
INVX8TS U6298 ( .A(n8415), .Y(n3227) );
OAI2BB1X4TS U6299 ( .A0N(n949), .A1N(n8311), .B0(n2344), .Y(n8754) );
INVX6TS U6300 ( .A(n10779), .Y(n10788) );
XNOR2X4TS U6301 ( .A(n1762), .B(n9793), .Y(n1761) );
XNOR2X4TS U6302 ( .A(n9863), .B(n9864), .Y(n1762) );
NOR2X4TS U6303 ( .A(n11059), .B(n11308), .Y(n5071) );
NAND2BX4TS U6304 ( .AN(n5984), .B(n2727), .Y(n1775) );
ADDFHX4TS U6305 ( .A(n5153), .B(n5154), .CI(n5155), .CO(n5191), .S(n5145) );
OAI21X2TS U6306 ( .A0(n4853), .A1(n4852), .B0(n4854), .Y(n2810) );
NAND2X4TS U6307 ( .A(n6692), .B(n2290), .Y(n10624) );
INVX3TS U6308 ( .A(n759), .Y(n3145) );
NAND2X4TS U6309 ( .A(n3145), .B(n3144), .Y(n3143) );
NAND2X4TS U6310 ( .A(n10625), .B(n11112), .Y(n5092) );
ADDFHX4TS U6311 ( .A(n5821), .B(n5820), .CI(n5819), .CO(n5787), .S(n5996) );
NAND2X2TS U6312 ( .A(n2393), .B(n2177), .Y(n10779) );
OAI22X4TS U6313 ( .A0(n3802), .A1(n1899), .B0(n2870), .B1(n5331), .Y(n3833)
);
INVX4TS U6314 ( .A(n9305), .Y(n3208) );
XNOR2X4TS U6315 ( .A(n5982), .B(n1768), .Y(n2727) );
ADDFHX4TS U6316 ( .A(n6962), .B(n6961), .CI(n6960), .CO(n6970), .S(n6972) );
OAI21X4TS U6317 ( .A0(n5467), .A1(n2835), .B0(n5466), .Y(n2834) );
INVX8TS U6318 ( .A(n2837), .Y(n5695) );
OAI21X4TS U6319 ( .A0(n5441), .A1(n5442), .B0(n5440), .Y(n2267) );
BUFX8TS U6320 ( .A(n9793), .Y(n2560) );
ADDFHX4TS U6321 ( .A(n6806), .B(n6805), .CI(n6804), .CO(n6798), .S(n6865) );
XOR2X4TS U6322 ( .A(n4000), .B(n3999), .Y(n1770) );
OAI2BB1X4TS U6323 ( .A0N(n1772), .A1N(n1771), .B0(n5446), .Y(n2840) );
NAND2BX4TS U6324 ( .AN(n9864), .B(n9793), .Y(n3221) );
NAND2X8TS U6325 ( .A(n1774), .B(n1775), .Y(n8273) );
XOR2X4TS U6326 ( .A(n1776), .B(n5278), .Y(n3800) );
XNOR2X4TS U6327 ( .A(n3127), .B(n1778), .Y(n1777) );
XNOR2X4TS U6328 ( .A(n9862), .B(n9861), .Y(n1778) );
XOR2X4TS U6329 ( .A(n1779), .B(n9278), .Y(n8498) );
XOR2X1TS U6330 ( .A(n2515), .B(n9904), .Y(n2514) );
NAND2X4TS U6331 ( .A(n9275), .B(n9274), .Y(n2827) );
OAI21X4TS U6332 ( .A0(n5453), .A1(n1676), .B0(n2153), .Y(n2956) );
ADDFHX4TS U6333 ( .A(n5192), .B(n5191), .CI(n5190), .CO(n5243), .S(n5193) );
OAI2BB1X2TS U6334 ( .A0N(n3276), .A1N(n2767), .B0(n8194), .Y(n2857) );
XOR2X4TS U6335 ( .A(n1832), .B(n12030), .Y(n3850) );
XNOR2X4TS U6336 ( .A(n1785), .B(n1676), .Y(n1780) );
ADDFHX4TS U6337 ( .A(n6707), .B(n6706), .CI(n6705), .CO(n6956), .S(n6949) );
NAND2X4TS U6338 ( .A(n906), .B(n3864), .Y(n1781) );
NAND2X4TS U6339 ( .A(n3865), .B(n3864), .Y(n1782) );
XOR2X4TS U6340 ( .A(n1784), .B(n5849), .Y(n8485) );
XNOR2X4TS U6341 ( .A(n5452), .B(n1727), .Y(n1785) );
ADDFHX2TS U6342 ( .A(n6779), .B(n6778), .CI(n6777), .CO(n6927), .S(n6801) );
OAI22X4TS U6343 ( .A0(n4958), .A1(n2447), .B0(n4914), .B1(n1958), .Y(n4944)
);
ADDFHX4TS U6344 ( .A(n5102), .B(n5104), .CI(n5103), .CO(n5110), .S(n5118) );
XOR2X4TS U6345 ( .A(n2771), .B(n5126), .Y(n1800) );
NAND2X2TS U6346 ( .A(n836), .B(n5902), .Y(n1789) );
NAND2X2TS U6347 ( .A(n6772), .B(n6768), .Y(n11060) );
NAND3X8TS U6348 ( .A(n2919), .B(n5362), .C(n9263), .Y(n2694) );
AOI21X4TS U6349 ( .A0(n10945), .A1(n9392), .B0(n9391), .Y(n9393) );
AND2X8TS U6350 ( .A(n2847), .B(n2846), .Y(n1791) );
NAND2X2TS U6351 ( .A(n5355), .B(n5357), .Y(n3103) );
BUFX4TS U6352 ( .A(n2919), .Y(n2676) );
INVX4TS U6353 ( .A(n2393), .Y(n6523) );
ADDFHX4TS U6354 ( .A(n5248), .B(n5250), .CI(n5249), .CO(n5350), .S(n5259) );
XNOR2X4TS U6355 ( .A(n1795), .B(n1794), .Y(n5226) );
XOR2X4TS U6356 ( .A(n5217), .B(n5218), .Y(n1795) );
ADDFHX4TS U6357 ( .A(n6811), .B(n6810), .CI(n6809), .CO(n6816), .S(n6826) );
INVX8TS U6358 ( .A(n3157), .Y(n6403) );
OAI22X4TS U6359 ( .A0(n6917), .A1(n1932), .B0(n6893), .B1(n1985), .Y(n6913)
);
ADDFHX4TS U6360 ( .A(n5258), .B(n5259), .CI(n5260), .CO(n5353), .S(n5291) );
BUFX4TS U6361 ( .A(n3252), .Y(n2492) );
NAND2X8TS U6362 ( .A(n1798), .B(n1799), .Y(n10731) );
OA21X4TS U6363 ( .A0(n10636), .A1(n10638), .B0(n10639), .Y(n1799) );
NAND2X4TS U6364 ( .A(n10790), .B(n10789), .Y(n3153) );
NAND2X4TS U6365 ( .A(n9623), .B(n9625), .Y(add_x_19_n747) );
NAND2X2TS U6366 ( .A(n9625), .B(n9624), .Y(add_x_19_n67) );
NAND2X6TS U6367 ( .A(n3295), .B(n11016), .Y(n3098) );
INVX4TS U6368 ( .A(n3295), .Y(n3294) );
ADDFHX4TS U6369 ( .A(n6521), .B(n6522), .CI(n6523), .CO(n8272), .S(n6524) );
INVX2TS U6370 ( .A(n1254), .Y(n8368) );
BUFX6TS U6371 ( .A(n9886), .Y(n2612) );
AND2X8TS U6372 ( .A(n9283), .B(n9282), .Y(n1801) );
OAI22X4TS U6373 ( .A0(n2447), .A1(n5005), .B0(n4975), .B1(n1959), .Y(n5002)
);
ADDFHX4TS U6374 ( .A(n5027), .B(n5026), .CI(n5025), .CO(n5111), .S(n5115) );
OR2X4TS U6375 ( .A(n1958), .B(n4027), .Y(n1803) );
CLKINVX12TS U6376 ( .A(DP_OP_168J26_122_4811_n8249), .Y(n2854) );
INVX16TS U6377 ( .A(n2854), .Y(n1808) );
CLKINVX12TS U6378 ( .A(DP_OP_168J26_122_4811_n8250), .Y(n6141) );
INVX16TS U6379 ( .A(n8551), .Y(n1819) );
BUFX20TS U6380 ( .A(n4485), .Y(n8948) );
BUFX6TS U6381 ( .A(n8948), .Y(n2054) );
INVX16TS U6382 ( .A(n10114), .Y(n1824) );
INVX16TS U6383 ( .A(n10114), .Y(n1825) );
ADDFHX4TS U6384 ( .A(n4049), .B(n4048), .CI(n4047), .CO(n4051), .S(n4247) );
OAI22X4TS U6385 ( .A0(n5146), .A1(n1964), .B0(n7993), .B1(n5223), .Y(n5210)
);
INVX16TS U6386 ( .A(n6562), .Y(n6561) );
ADDFHX4TS U6387 ( .A(n3705), .B(n3704), .CI(n3706), .CO(n3746), .S(n3751) );
OAI22X4TS U6388 ( .A0(n1866), .A1(n5620), .B0(n5577), .B1(n5572), .Y(n5597)
);
ADDFHX2TS U6389 ( .A(n4103), .B(n4102), .CI(n4101), .CO(n4383), .S(n9782) );
OAI22X4TS U6390 ( .A0(n5512), .A1(n1940), .B0(n5693), .B1(n8938), .Y(n5745)
);
XNOR2X4TS U6391 ( .A(n8443), .B(n2408), .Y(n5512) );
XNOR2X4TS U6392 ( .A(n1028), .B(n2408), .Y(n5693) );
ADDFHX4TS U6393 ( .A(n8538), .B(n8537), .CI(n8536), .CO(n8521), .S(n8556) );
NOR2X8TS U6394 ( .A(n2661), .B(n2495), .Y(n8181) );
ADDFHX2TS U6395 ( .A(n4085), .B(n4086), .CI(n4084), .CO(n4288), .S(n4385) );
BUFX4TS U6396 ( .A(n9273), .Y(n2454) );
ADDFHX4TS U6397 ( .A(n5017), .B(n5018), .CI(n5016), .CO(n5112), .S(n5105) );
BUFX12TS U6398 ( .A(n1086), .Y(n2159) );
ADDFHX4TS U6399 ( .A(n6228), .B(n6226), .CI(n6227), .CO(n6244), .S(n6231) );
OAI22X4TS U6400 ( .A0(n2089), .A1(n6163), .B0(n6143), .B1(n6142), .Y(n6226)
);
XOR2X4TS U6401 ( .A(n1840), .B(n4658), .Y(n4815) );
XOR2X4TS U6402 ( .A(n4659), .B(n4660), .Y(n1840) );
ADDFHX4TS U6403 ( .A(n3532), .B(n3534), .CI(n3533), .CO(n3520), .S(n3901) );
ADDFHX4TS U6404 ( .A(n5718), .B(n5717), .CI(n5716), .CO(n5618), .S(n5791) );
ADDFHX4TS U6405 ( .A(n5619), .B(n5618), .CI(n5617), .CO(n5702), .S(n5748) );
ADDFHX4TS U6406 ( .A(n9785), .B(n9784), .CI(n9783), .CO(n9862), .S(n9820) );
ADDFHX4TS U6407 ( .A(n9786), .B(n9787), .CI(n9788), .CO(n9833), .S(n9861) );
XOR2X4TS U6408 ( .A(n3344), .B(n3343), .Y(n1841) );
INVX12TS U6409 ( .A(n1841), .Y(n3345) );
OAI22X4TS U6410 ( .A0(n6765), .A1(n1932), .B0(n1985), .B1(n6756), .Y(n6788)
);
XNOR2X2TS U6411 ( .A(n6633), .B(n2410), .Y(n6756) );
OAI22X4TS U6412 ( .A0(n2025), .A1(n4966), .B0(n4942), .B1(n1990), .Y(n5100)
);
OR2X4TS U6413 ( .A(n2770), .B(n2769), .Y(n10723) );
XNOR2X4TS U6414 ( .A(n2020), .B(n8513), .Y(n5549) );
OAI22X4TS U6415 ( .A0(n4365), .A1(n1020), .B0(n4259), .B1(n2019), .Y(n4319)
);
ADDFHX4TS U6416 ( .A(n5930), .B(n5931), .CI(n5929), .CO(n5934), .S(n6482) );
INVX12TS U6417 ( .A(n6385), .Y(n4312) );
ADDFX2TS U6418 ( .A(n3949), .B(n3948), .CI(n3947), .CO(n4755), .S(n4399) );
XNOR2X4TS U6419 ( .A(n2456), .B(n2453), .Y(n3791) );
NAND2X8TS U6420 ( .A(n2529), .B(n2528), .Y(n1843) );
XNOR2X4TS U6421 ( .A(n7279), .B(n5270), .Y(n4239) );
ADDFHX4TS U6422 ( .A(n7094), .B(n7095), .CI(n7093), .CO(n7123), .S(n7127) );
ADDFHX4TS U6423 ( .A(n3832), .B(n3831), .CI(n3830), .CO(n3840), .S(n4036) );
ADDFHX4TS U6424 ( .A(n5986), .B(n5987), .CI(n5985), .CO(n5997), .S(n8261) );
ADDFHX2TS U6425 ( .A(n2643), .B(n2669), .CI(n7098), .CO(n7105), .S(n7109) );
ADDFHX4TS U6426 ( .A(n8924), .B(n8925), .CI(n8926), .CO(n8969), .S(n8964) );
NAND2X8TS U6427 ( .A(n3392), .B(DP_OP_168J26_122_4811_n8218), .Y(n3393) );
ADDFHX4TS U6428 ( .A(n5171), .B(n5172), .CI(n5170), .CO(n5218), .S(n5160) );
ADDFHX2TS U6429 ( .A(n8944), .B(n8943), .CI(n8942), .CO(n8984), .S(n9005) );
OAI22X4TS U6430 ( .A0(n8910), .A1(n1973), .B0(n8909), .B1(n2036), .Y(n8942)
);
CLKBUFX2TS U6431 ( .A(n11007), .Y(n2533) );
OAI21X4TS U6432 ( .A0(n3938), .A1(DP_OP_168J26_122_4811_n3486), .B0(n2274),
.Y(n3939) );
ADDFHX2TS U6433 ( .A(n3910), .B(n3911), .CI(n3909), .CO(n3900), .S(n4122) );
ADDFHX4TS U6434 ( .A(n5392), .B(n5391), .CI(n5390), .CO(n5427), .S(n5417) );
ADDFHX4TS U6435 ( .A(n4381), .B(n4380), .CI(n4382), .CO(n4393), .S(n9802) );
ADDFHX4TS U6436 ( .A(n4376), .B(n4375), .CI(n4374), .CO(n4384), .S(n4380) );
ADDFHX2TS U6437 ( .A(n4292), .B(n4291), .CI(n4290), .CO(n4410), .S(n4287) );
XNOR2X2TS U6438 ( .A(n6892), .B(n4488), .Y(n4369) );
NAND2X4TS U6439 ( .A(n10519), .B(n1435), .Y(n10607) );
AOI21X4TS U6440 ( .A0(n3603), .A1(n3602), .B0(n739), .Y(n3604) );
OAI22X4TS U6441 ( .A0(n8899), .A1(n1986), .B0(n8138), .B1(n2051), .Y(n8915)
);
OAI22X2TS U6442 ( .A0(n1936), .A1(n4875), .B0(n1989), .B1(n4837), .Y(n4889)
);
XOR2X4TS U6443 ( .A(n945), .B(n1286), .Y(n4861) );
OAI22X4TS U6444 ( .A0(n2077), .A1(n1931), .B0(n7489), .B1(n1876), .Y(n4133)
);
ADDFHX4TS U6445 ( .A(n3308), .B(n4462), .CI(n4461), .CO(n4796), .S(n4467) );
ADDFHX2TS U6446 ( .A(n5628), .B(n5629), .CI(n5630), .CO(n5582), .S(n5713) );
ADDFHX4TS U6447 ( .A(n5980), .B(n5981), .CI(n5979), .CO(n5976), .S(n8271) );
ADDFHX4TS U6448 ( .A(n9835), .B(n9836), .CI(n9834), .CO(n9801), .S(n9860) );
INVX8TS U6449 ( .A(n7529), .Y(n9083) );
ADDFHX4TS U6450 ( .A(n7030), .B(n7029), .CI(n7028), .CO(n7051), .S(n7066) );
INVX8TS U6451 ( .A(n8240), .Y(n2932) );
ADDFHX2TS U6452 ( .A(n4604), .B(n4603), .CI(n4602), .CO(n4682), .S(n4611) );
OAI22X4TS U6453 ( .A0(n5221), .A1(n2071), .B0(n1958), .B1(n5279), .Y(n5249)
);
ADDFHX4TS U6454 ( .A(n5804), .B(n5805), .CI(n5803), .CO(n5947), .S(n6242) );
OAI22X4TS U6455 ( .A0(n7054), .A1(n2411), .B0(n1950), .B1(n7015), .Y(n7058)
);
ADDFHX4TS U6456 ( .A(n8095), .B(n8094), .CI(n8093), .CO(n8156), .S(n8108) );
NAND2X6TS U6457 ( .A(n10027), .B(n10029), .Y(n2680) );
ADDFHX4TS U6458 ( .A(n8665), .B(n8664), .CI(n8663), .CO(n8687), .S(n8666) );
NAND2X2TS U6459 ( .A(n889), .B(n7521), .Y(n1846) );
OAI22X4TS U6460 ( .A0(n2100), .A1(n7470), .B0(n7234), .B1(n5677), .Y(n7523)
);
XNOR2X2TS U6461 ( .A(n1705), .B(Op_MY[21]), .Y(n4556) );
ADDFHX4TS U6462 ( .A(n3889), .B(n3887), .CI(n3888), .CO(n4266), .S(n4158) );
ADDFHX4TS U6463 ( .A(n1303), .B(n1876), .CI(n3523), .CO(n3522), .S(n3886) );
OAI22X4TS U6464 ( .A0(n2399), .A1(n1686), .B0(n7489), .B1(n1850), .Y(n3523)
);
ADDFHX4TS U6465 ( .A(n4719), .B(n4718), .CI(n4717), .CO(n4736), .S(n4739) );
ADDFHX4TS U6466 ( .A(n4807), .B(n4805), .CI(n4806), .CO(n9103), .S(n4738) );
ADDFHX4TS U6467 ( .A(n3827), .B(n3825), .CI(n3826), .CO(n3869), .S(n3864) );
OAI22X4TS U6468 ( .A0(n2221), .A1(n3817), .B0(n5320), .B1(n3715), .Y(n3822)
);
ADDFHX4TS U6469 ( .A(n3823), .B(n3824), .CI(n3822), .CO(n3812), .S(n3839) );
ADDFHX4TS U6470 ( .A(n8959), .B(n8960), .CI(n8958), .CO(n8970), .S(n9105) );
ADDFHX4TS U6471 ( .A(n8918), .B(n8919), .CI(n8917), .CO(n8966), .S(n8960) );
ADDFHX2TS U6472 ( .A(n4534), .B(n4533), .CI(n4532), .CO(n4558), .S(n4566) );
OAI22X4TS U6473 ( .A0(n3850), .A1(n2071), .B0(n3800), .B1(n1959), .Y(n3835)
);
OAI22X4TS U6474 ( .A0(n3976), .A1(n5320), .B0(n1806), .B1(n3186), .Y(n3958)
);
INVX16TS U6475 ( .A(n2943), .Y(n3758) );
ADDFHX2TS U6476 ( .A(n4017), .B(n4018), .CI(n4016), .CO(n3855), .S(n4238) );
ADDFHX4TS U6477 ( .A(n9773), .B(n9772), .CI(n9771), .CO(n9791), .S(n9850) );
ADDFHX2TS U6478 ( .A(n6594), .B(n6595), .CI(n6593), .CO(n6597), .S(n6646) );
XNOR2X2TS U6479 ( .A(n1582), .B(n8542), .Y(n6554) );
OAI22X2TS U6480 ( .A0(n4258), .A1(n8931), .B0(n4257), .B1(n9456), .Y(n4320)
);
XNOR2X4TS U6481 ( .A(n2328), .B(n750), .Y(n5307) );
BUFX20TS U6482 ( .A(n7277), .Y(n2328) );
INVX6TS U6483 ( .A(n8226), .Y(n3119) );
NAND2X4TS U6484 ( .A(n2651), .B(n1709), .Y(n8799) );
OAI22X4TS U6485 ( .A0(n5286), .A1(n1806), .B0(n8009), .B1(n5321), .Y(n5342)
);
CMPR22X2TS U6486 ( .A(n5342), .B(n5341), .CO(n5414), .S(n5310) );
ADDFHX4TS U6487 ( .A(n8134), .B(n8133), .CI(n8132), .CO(n8106), .S(n8967) );
ADDFHX4TS U6488 ( .A(n8042), .B(n8043), .CI(n8044), .CO(n8128), .S(n8124) );
INVX4TS U6489 ( .A(n8227), .Y(n8093) );
ADDFHX4TS U6490 ( .A(n4575), .B(n4574), .CI(n4573), .CO(n4601), .S(n4568) );
OAI22X4TS U6491 ( .A0(n2221), .A1(n4539), .B0(n5320), .B1(n4581), .Y(n4574)
);
ADDFHX4TS U6492 ( .A(n4531), .B(n4530), .CI(n4529), .CO(n4559), .S(n4562) );
ADDFHX4TS U6493 ( .A(n8886), .B(n8885), .CI(n8884), .CO(n8968), .S(n8972) );
ADDFHX4TS U6494 ( .A(n3847), .B(n3846), .CI(n3845), .CO(n3841), .S(n4039) );
XNOR2X4TS U6495 ( .A(n2657), .B(n4488), .Y(n4355) );
CLKINVX12TS U6496 ( .A(n5571), .Y(n6006) );
OAI22X2TS U6497 ( .A0(n1866), .A1(n6047), .B0(n3320), .B1(n6151), .Y(n6186)
);
OAI22X4TS U6498 ( .A0(n1853), .A1(n6153), .B0(n3320), .B1(n6152), .Y(n6208)
);
OAI22X2TS U6499 ( .A0(n1853), .A1(n3471), .B0(n2062), .B1(
DP_OP_168J26_122_4811_n8030), .Y(n3464) );
INVX16TS U6500 ( .A(n3282), .Y(n1859) );
XNOR2X4TS U6501 ( .A(n8540), .B(n8533), .Y(n4373) );
XNOR2X2TS U6502 ( .A(n8540), .B(n4488), .Y(n4257) );
INVX6TS U6503 ( .A(n1856), .Y(n1857) );
XNOR2X4TS U6504 ( .A(n8534), .B(n8619), .Y(n6917) );
XNOR2X4TS U6505 ( .A(n8540), .B(n1946), .Y(n6699) );
XNOR2X4TS U6506 ( .A(n4003), .B(n8619), .Y(n6893) );
XNOR2X4TS U6507 ( .A(n1028), .B(n8619), .Y(n6630) );
BUFX16TS U6508 ( .A(n2410), .Y(n1946) );
XNOR2X2TS U6509 ( .A(n2328), .B(n1008), .Y(n4875) );
CLKINVX12TS U6510 ( .A(n6849), .Y(n3282) );
NOR2BX4TS U6511 ( .AN(n6849), .B(n2504), .Y(n6688) );
XNOR2X4TS U6512 ( .A(n7242), .B(n1312), .Y(n5621) );
XNOR2X4TS U6513 ( .A(n5174), .B(n5235), .Y(n5271) );
XNOR2X4TS U6514 ( .A(n2590), .B(n5235), .Y(n4860) );
XNOR2X4TS U6515 ( .A(n5235), .B(n5273), .Y(n3676) );
OAI22X2TS U6516 ( .A0(n5924), .A1(n8516), .B0(n5940), .B1(n8518), .Y(n5994)
);
OAI22X2TS U6517 ( .A0(n3950), .A1(n1965), .B0(n4637), .B1(n1862), .Y(n4754)
);
INVX6TS U6518 ( .A(n1863), .Y(n1864) );
NOR2BX4TS U6519 ( .AN(n2591), .B(n1943), .Y(n5077) );
NAND2BX4TS U6520 ( .AN(n2591), .B(n2455), .Y(n4824) );
NAND2BX4TS U6521 ( .AN(n2591), .B(n754), .Y(n4025) );
NAND2BX1TS U6522 ( .AN(n4982), .B(n5278), .Y(n5038) );
OAI22X4TS U6523 ( .A0(n5662), .A1(n1866), .B0(n2062), .B1(n5884), .Y(n5857)
);
OAI22X4TS U6524 ( .A0(n1985), .A1(n2950), .B0(n8629), .B1(n6758), .Y(n6763)
);
NAND2BX2TS U6525 ( .AN(n3290), .B(n10873), .Y(n12341) );
NAND2BX2TS U6526 ( .AN(n3290), .B(n10883), .Y(n12281) );
XNOR2X4TS U6527 ( .A(n1808), .B(n2503), .Y(n5685) );
INVX8TS U6528 ( .A(n11785), .Y(n1870) );
BUFX20TS U6529 ( .A(DP_OP_168J26_122_4811_n8477), .Y(n2625) );
BUFX20TS U6530 ( .A(DP_OP_168J26_122_4811_n6782), .Y(n2666) );
XNOR2X4TS U6531 ( .A(n8911), .B(n2410), .Y(n5828) );
XNOR2X4TS U6532 ( .A(n2376), .B(n8542), .Y(n6424) );
XNOR2X4TS U6533 ( .A(n2403), .B(n6156), .Y(n3416) );
OAI22X2TS U6534 ( .A0(n2222), .A1(n1838), .B0(n2046), .B1(n5287), .Y(n5341)
);
NAND2X2TS U6535 ( .A(n2066), .B(n1880), .Y(n2776) );
XNOR2X4TS U6536 ( .A(n1881), .B(n7349), .Y(n4448) );
CLKINVX12TS U6537 ( .A(DP_OP_168J26_122_4811_n8478), .Y(n5253) );
XNOR2X4TS U6538 ( .A(n5251), .B(n1885), .Y(n5013) );
XNOR2X4TS U6539 ( .A(n7275), .B(n1884), .Y(n3844) );
XNOR2X4TS U6540 ( .A(n2093), .B(n1885), .Y(n3715) );
OAI22X4TS U6541 ( .A0(n8585), .A1(n1886), .B0(n4359), .B1(n2054), .Y(n8529)
);
OAI22X4TS U6542 ( .A0(n1915), .A1(n5678), .B0(n2060), .B1(n4190), .Y(n5868)
);
OAI22X4TS U6543 ( .A0(n1914), .A1(n5679), .B0(n782), .B1(n5678), .Y(n5853)
);
BUFX8TS U6544 ( .A(n1256), .Y(n2341) );
INVX8TS U6545 ( .A(n12029), .Y(n1887) );
XNOR2X4TS U6546 ( .A(n1861), .B(n7272), .Y(n8012) );
XNOR2X4TS U6547 ( .A(n2455), .B(n7272), .Y(n4671) );
XNOR2X4TS U6548 ( .A(n2045), .B(n1887), .Y(n7256) );
OAI22X4TS U6549 ( .A0(n8081), .A1(n8579), .B0(n7304), .B1(n8945), .Y(n8080)
);
OAI22X2TS U6550 ( .A0(n4777), .A1(n2293), .B0(n8939), .B1(n1892), .Y(n8998)
);
BUFX20TS U6551 ( .A(n8933), .Y(n1895) );
NAND2X4TS U6552 ( .A(n1895), .B(n8935), .Y(n2813) );
OAI22X4TS U6553 ( .A0(n8936), .A1(n8935), .B0(n8934), .B1(n1894), .Y(n8994)
);
OAI22X4TS U6554 ( .A0(n8936), .A1(n1894), .B0(n8912), .B1(n8935), .Y(n8983)
);
INVX12TS U6555 ( .A(n1389), .Y(n1899) );
NOR2BX4TS U6556 ( .AN(n1809), .B(n741), .Y(n4220) );
XNOR2X2TS U6557 ( .A(n2045), .B(n4982), .Y(n5146) );
XOR2X4TS U6558 ( .A(n11740), .B(n4982), .Y(n4920) );
INVX4TS U6559 ( .A(n1903), .Y(n1905) );
OAI22X2TS U6560 ( .A0(n4363), .A1(n1862), .B0(n4364), .B1(n1908), .Y(n9774)
);
XNOR2X2TS U6561 ( .A(n8534), .B(n8510), .Y(n5545) );
CLKINVX12TS U6562 ( .A(n4455), .Y(n5665) );
OAI22X4TS U6563 ( .A0(n3400), .A1(n1911), .B0(n838), .B1(n3406), .Y(n3402)
);
OAI22X4TS U6564 ( .A0(n1911), .A1(n4189), .B0(n4165), .B1(n838), .Y(n4201)
);
OAI22X4TS U6565 ( .A0(n5663), .A1(n1911), .B0(n838), .B1(n4189), .Y(n5869)
);
OAI22X4TS U6566 ( .A0(n7492), .A1(n3423), .B0(n7491), .B1(n3422), .Y(n3446)
);
XNOR2X4TS U6567 ( .A(n7242), .B(n7488), .Y(n3499) );
XNOR2X4TS U6568 ( .A(n6093), .B(n7488), .Y(n6163) );
XNOR2X4TS U6569 ( .A(n2070), .B(n7488), .Y(n5624) );
INVX12TS U6570 ( .A(n1025), .Y(n1915) );
OAI22X4TS U6571 ( .A0(n7486), .A1(n7069), .B0(n838), .B1(n7097), .Y(n7103)
);
CLKINVX12TS U6572 ( .A(DP_OP_168J26_122_4811_n8220), .Y(n1917) );
OAI22X2TS U6573 ( .A0(n6178), .A1(n6175), .B0(n1948), .B1(n5954), .Y(n6211)
);
OAI22X2TS U6574 ( .A0(n2102), .A1(n5954), .B0(n6176), .B1(n5802), .Y(n5967)
);
OAI22X2TS U6575 ( .A0(n2089), .A1(n6025), .B0(n6022), .B1(n2261), .Y(n6043)
);
XNOR2X2TS U6576 ( .A(n1818), .B(n3322), .Y(n7162) );
INVX12TS U6577 ( .A(n1922), .Y(n1923) );
NOR2BX4TS U6578 ( .AN(n1902), .B(n1923), .Y(n5372) );
OAI22X4TS U6579 ( .A0(n2411), .A1(n4029), .B0(n1923), .B1(n4028), .Y(n4241)
);
OAI22X4TS U6580 ( .A0(n1822), .A1(n3816), .B0(n1923), .B1(n3714), .Y(n3823)
);
XNOR2X2TS U6581 ( .A(n8540), .B(n1926), .Y(n8445) );
XNOR2X2TS U6582 ( .A(n8511), .B(n6562), .Y(n6476) );
OAI22X2TS U6583 ( .A0(n6922), .A1(n6921), .B0(n6920), .B1(n8614), .Y(n6946)
);
BUFX20TS U6584 ( .A(n4984), .Y(n1934) );
AO21X4TS U6585 ( .A0(n9457), .A1(n2050), .B0(n1038), .Y(n9478) );
OAI22X4TS U6586 ( .A0(n3815), .A1(n8022), .B0(n3695), .B1(n8020), .Y(n3711)
);
OAI22X4TS U6587 ( .A0(n8022), .A1(n8019), .B0(n8020), .B1(n7278), .Y(n8018)
);
INVX16TS U6588 ( .A(n1937), .Y(n1938) );
OAI22X4TS U6589 ( .A0(n6437), .A1(n2577), .B0(n6434), .B1(n6436), .Y(n6556)
);
OAI22X2TS U6590 ( .A0(n6415), .A1(n2577), .B0(n6430), .B1(n8938), .Y(n6412)
);
OAI22X2TS U6591 ( .A0(n5692), .A1(n8574), .B0(n5527), .B1(n1945), .Y(n5734)
);
OAI22X2TS U6592 ( .A0(n6178), .A1(n6161), .B0(n6040), .B1(n6039), .Y(n6091)
);
INVX6TS U6593 ( .A(n6906), .Y(n6832) );
XNOR2X4TS U6594 ( .A(n1909), .B(n6906), .Y(n6802) );
NOR2BX2TS U6595 ( .AN(n6849), .B(n2647), .Y(n6841) );
OAI22X4TS U6596 ( .A0(n4683), .A1(n2112), .B0(n1960), .B1(n6561), .Y(n8989)
);
OAI22X2TS U6597 ( .A0(n8463), .A1(n2113), .B0(n8515), .B1(n1960), .Y(n8646)
);
OAI22X2TS U6598 ( .A0(n8549), .A1(n1960), .B0(n8515), .B1(n2113), .Y(n8659)
);
OAI22X4TS U6599 ( .A0(n8061), .A1(n2339), .B0(n1973), .B1(n8060), .Y(n8071)
);
OAI22X1TS U6600 ( .A0(n8895), .A1(n1973), .B0(n8064), .B1(n2339), .Y(n8139)
);
INVX16TS U6601 ( .A(n1963), .Y(n1964) );
BUFX12TS U6602 ( .A(n4356), .Y(n8977) );
XNOR2X4TS U6603 ( .A(n3640), .B(n1967), .Y(n8934) );
OAI22X4TS U6604 ( .A0(n4082), .A1(n8935), .B0(n4259), .B1(n1020), .Y(n4323)
);
BUFX3TS U6605 ( .A(n11998), .Y(n11995) );
INVX16TS U6606 ( .A(n7011), .Y(n1970) );
INVX16TS U6607 ( .A(n2362), .Y(n3176) );
BUFX12TS U6608 ( .A(n1725), .Y(n2483) );
OAI22X2TS U6609 ( .A0(n1980), .A1(n4667), .B0(n2568), .B1(n8014), .Y(n8044)
);
OAI22X2TS U6610 ( .A0(n1980), .A1(n4594), .B0(n2157), .B1(n4667), .Y(n4679)
);
OAI22X2TS U6611 ( .A0(n8015), .A1(n5274), .B0(n2157), .B1(n5323), .Y(n5297)
);
OAI22X4TS U6612 ( .A0(n1981), .A1(n8012), .B0(n2568), .B1(n7274), .Y(n8001)
);
OAI22X2TS U6613 ( .A0(n8574), .A1(n6635), .B0(n2296), .B1(n6634), .Y(n6690)
);
OAI22X4TS U6614 ( .A0(n6580), .A1(n8574), .B0(n6543), .B1(n6883), .Y(n6582)
);
NAND2X8TS U6615 ( .A(n4087), .B(n3643), .Y(n3644) );
OAI22X2TS U6616 ( .A0(n8022), .A1(n7278), .B0(n8020), .B1(n1706), .Y(n7287)
);
CLKBUFX3TS U6617 ( .A(n12226), .Y(n12222) );
BUFX3TS U6618 ( .A(n11973), .Y(n12239) );
BUFX3TS U6619 ( .A(n11696), .Y(n11709) );
BUFX3TS U6620 ( .A(n11995), .Y(n11701) );
BUFX3TS U6621 ( .A(n12229), .Y(n11699) );
MXI2X4TS U6622 ( .A(n10260), .B(n12247), .S0(n10326), .Y(n598) );
MXI2X4TS U6623 ( .A(n9727), .B(n11922), .S0(n10293), .Y(n654) );
INVX2TS U6624 ( .A(n1994), .Y(n1995) );
XOR2X1TS U6625 ( .A(n656), .B(n9729), .Y(n11514) );
INVX2TS U6626 ( .A(n1996), .Y(n1997) );
INVX2TS U6627 ( .A(n1998), .Y(n1999) );
NOR4X1TS U6628 ( .A(P_Sgf[14]), .B(P_Sgf[15]), .C(P_Sgf[13]), .D(P_Sgf[12]),
.Y(n9242) );
INVX2TS U6629 ( .A(n6752), .Y(n2002) );
CLKINVX6TS U6630 ( .A(n2002), .Y(n2003) );
OAI22X4TS U6631 ( .A0(ack_FSM), .A1(n10329), .B0(n12228), .B1(beg_FSM), .Y(
n12383) );
CLKBUFX3TS U6632 ( .A(n12222), .Y(n11978) );
INVX2TS U6633 ( .A(n11245), .Y(n11043) );
MXI2X4TS U6634 ( .A(n10327), .B(n11954), .S0(n10326), .Y(n601) );
MXI2X4TS U6635 ( .A(n9670), .B(n11960), .S0(n10293), .Y(n646) );
MXI2X4TS U6636 ( .A(n9675), .B(n11923), .S0(n10293), .Y(n652) );
MXI2X4TS U6637 ( .A(n10292), .B(n11902), .S0(n10293), .Y(n648) );
BUFX3TS U6638 ( .A(n12242), .Y(n12238) );
CLKBUFX3TS U6639 ( .A(n9663), .Y(n11453) );
CLKBUFX2TS U6640 ( .A(n12226), .Y(n11983) );
CLKBUFX3TS U6641 ( .A(n11982), .Y(n9664) );
CLKBUFX2TS U6642 ( .A(n12221), .Y(n11976) );
CLKBUFX3TS U6643 ( .A(n9664), .Y(n11447) );
CLKBUFX3TS U6644 ( .A(n11982), .Y(n11714) );
BUFX3TS U6645 ( .A(n11129), .Y(n11999) );
CLKBUFX3TS U6646 ( .A(n11981), .Y(n11450) );
CLKBUFX3TS U6647 ( .A(n11981), .Y(n11716) );
CLKBUFX3TS U6648 ( .A(n12222), .Y(n11977) );
CLKBUFX3TS U6649 ( .A(n12225), .Y(n11979) );
BUFX3TS U6650 ( .A(n11984), .Y(n12224) );
BUFX3TS U6651 ( .A(n11974), .Y(n12237) );
CLKBUFX2TS U6652 ( .A(n11129), .Y(n2009) );
CLKBUFX2TS U6653 ( .A(n10318), .Y(n2010) );
BUFX3TS U6654 ( .A(n11987), .Y(n11712) );
BUFX3TS U6655 ( .A(n1867), .Y(n11694) );
BUFX3TS U6656 ( .A(n11129), .Y(n11696) );
CLKBUFX3TS U6657 ( .A(n11997), .Y(n10318) );
NAND2X2TS U6658 ( .A(n10088), .B(n10073), .Y(n9301) );
NAND2X2TS U6659 ( .A(n10088), .B(n8718), .Y(n9559) );
XOR2X4TS U6660 ( .A(n2014), .B(DP_OP_168J26_122_4811_n6172), .Y(n3793) );
XNOR2X4TS U6661 ( .A(n2014), .B(n2653), .Y(n8006) );
XOR2X4TS U6662 ( .A(n2014), .B(n2527), .Y(n3666) );
OAI22X2TS U6663 ( .A0(n823), .A1(n6173), .B0(n11757), .B1(n6172), .Y(n6214)
);
OAI22X4TS U6664 ( .A0(n6066), .A1(n2018), .B0(n2450), .B1(n6102), .Y(n6104)
);
OAI22X4TS U6665 ( .A0(n8535), .A1(n2019), .B0(n8466), .B1(n1020), .Y(n8505)
);
INVX16TS U6666 ( .A(n8441), .Y(n2021) );
XNOR2X4TS U6667 ( .A(n2021), .B(n1946), .Y(n6918) );
XNOR2X4TS U6668 ( .A(n2021), .B(n1024), .Y(n4004) );
INVX16TS U6669 ( .A(n4070), .Y(n2022) );
XNOR2X2TS U6670 ( .A(n2657), .B(n6402), .Y(n6765) );
XNOR2X4TS U6671 ( .A(n2022), .B(n6435), .Y(n6437) );
INVX8TS U6672 ( .A(n2023), .Y(n2025) );
OAI22X2TS U6673 ( .A0(n4883), .A1(n2024), .B0(n5325), .B1(n4836), .Y(n4893)
);
OAI22X2TS U6674 ( .A0(n5309), .A1(n5142), .B0(n1988), .B1(n5166), .Y(n5170)
);
OAI22X2TS U6675 ( .A0(n6223), .A1(n6098), .B0(n11754), .B1(n6035), .Y(n6127)
);
OAI22X2TS U6676 ( .A0(n6223), .A1(n6221), .B0(n1939), .B1(n5795), .Y(n5965)
);
OAI22X2TS U6677 ( .A0(n2029), .A1(n6014), .B0(n11754), .B1(n6058), .Y(n6062)
);
AO21X4TS U6678 ( .A0(n4455), .A1(n786), .B0(n1243), .Y(n7352) );
OAI22X4TS U6679 ( .A0(n7038), .A1(n7486), .B0(n2030), .B1(n7069), .Y(n7074)
);
OAI22X2TS U6680 ( .A0(n5535), .A1(n2055), .B0(n5537), .B1(n8583), .Y(n5636)
);
XNOR2X4TS U6681 ( .A(n2465), .B(n8542), .Y(n6602) );
XNOR2X4TS U6682 ( .A(n1819), .B(n2034), .Y(n5831) );
BUFX8TS U6683 ( .A(n4095), .Y(n8908) );
OAI22X4TS U6684 ( .A0(n6069), .A1(n4196), .B0(n2038), .B1(n4173), .Y(n6305)
);
OAI22X4TS U6685 ( .A0(n5757), .A1(n2018), .B0(n2450), .B1(n5594), .Y(n5754)
);
XNOR2X4TS U6686 ( .A(n8894), .B(n8548), .Y(n5542) );
XNOR2X2TS U6687 ( .A(n1582), .B(n8548), .Y(n8463) );
XNOR2X4TS U6688 ( .A(n1805), .B(n1817), .Y(n5564) );
XNOR2X4TS U6689 ( .A(n8889), .B(n8896), .Y(n3792) );
BUFX6TS U6690 ( .A(n5507), .Y(n8896) );
NAND2X2TS U6691 ( .A(n10957), .B(n1360), .Y(n10958) );
NAND2X2TS U6692 ( .A(n10957), .B(n10811), .Y(n9389) );
INVX16TS U6693 ( .A(n9344), .Y(n10957) );
INVX16TS U6694 ( .A(n4064), .Y(n2041) );
AO21X4TS U6695 ( .A0(n5950), .A1(n7491), .B0(n928), .Y(n7521) );
OAI22X2TS U6696 ( .A0(n1815), .A1(n4446), .B0(n7491), .B1(n4460), .Y(n4451)
);
XNOR2X4TS U6697 ( .A(n6884), .B(n6435), .Y(n6436) );
NOR2BX4TS U6698 ( .AN(n1902), .B(n8009), .Y(n5247) );
XNOR2X4TS U6699 ( .A(n1861), .B(n2634), .Y(n3693) );
NOR2X1TS U6700 ( .A(n10400), .B(n11328), .Y(n10402) );
NOR2X1TS U6701 ( .A(n10392), .B(n2049), .Y(n10394) );
NOR2X1TS U6702 ( .A(n11048), .B(n11328), .Y(n11050) );
NOR2X1TS U6703 ( .A(n10409), .B(n2049), .Y(n10411) );
NOR2X1TS U6704 ( .A(n10404), .B(n11328), .Y(n10406) );
NOR2X1TS U6705 ( .A(n10387), .B(n11328), .Y(n10389) );
NOR2X1TS U6706 ( .A(n10420), .B(n11328), .Y(n10422) );
NOR2X1TS U6707 ( .A(n10415), .B(n2049), .Y(n10417) );
OAI22X2TS U6708 ( .A0(n8932), .A1(n2331), .B0(n8930), .B1(n2050), .Y(n8995)
);
OAI22X4TS U6709 ( .A0(n8065), .A1(n9457), .B0(n8062), .B1(n2050), .Y(n8070)
);
INVX12TS U6710 ( .A(n2449), .Y(n4351) );
OAI22X2TS U6711 ( .A0(n8138), .A1(n1987), .B0(n8067), .B1(n2051), .Y(n8133)
);
BUFX20TS U6712 ( .A(n2581), .Y(n2052) );
OAI22X2TS U6713 ( .A0(n3929), .A1(n8977), .B0(n3950), .B1(n8516), .Y(n3987)
);
OAI22X2TS U6714 ( .A0(n8888), .A1(n1965), .B0(n8137), .B1(n2052), .Y(n8916)
);
OAI22X2TS U6715 ( .A0(n8088), .A1(n2545), .B0(n7228), .B1(n2055), .Y(n7309)
);
OAI22X4TS U6716 ( .A0(n7161), .A1(n2545), .B0(n7160), .B1(n2054), .Y(n7164)
);
OAI22X2TS U6717 ( .A0(n4778), .A1(n2054), .B0(n4723), .B1(n1886), .Y(n4773)
);
OAI22X2TS U6718 ( .A0(n8949), .A1(n2545), .B0(n8890), .B1(n2054), .Y(n8956)
);
OAI22X2TS U6719 ( .A0(n4516), .A1(n1886), .B0(n4515), .B1(n2054), .Y(n4712)
);
AO21X4TS U6720 ( .A0(n2588), .A1(n8945), .B0(n5500), .Y(n7112) );
OAI22X4TS U6721 ( .A0(n4644), .A1(n2588), .B0(n4724), .B1(n8945), .Y(n4700)
);
XNOR2X4TS U6722 ( .A(n2338), .B(n8920), .Y(n8932) );
XNOR2X4TS U6723 ( .A(n2465), .B(n8920), .Y(n4812) );
XNOR2X4TS U6724 ( .A(n2376), .B(n8920), .Y(n8142) );
INVX2TS U6725 ( .A(n4488), .Y(n4353) );
XNOR2X4TS U6726 ( .A(n2465), .B(n8887), .Y(n8517) );
OAI22X4TS U6727 ( .A0(n1914), .A1(n4454), .B0(n4793), .B1(n2060), .Y(n4784)
);
OAI22X4TS U6728 ( .A0(n1222), .A1(n4445), .B0(n2060), .B1(n4454), .Y(n4453)
);
OAI22X2TS U6729 ( .A0(n1915), .A1(n7478), .B0(n2059), .B1(n7244), .Y(n7512)
);
OAI22X2TS U6730 ( .A0(n1222), .A1(n4793), .B0(n2059), .B1(n7440), .Y(n7452)
);
INVX4TS U6731 ( .A(n2061), .Y(n2062) );
NAND2X4TS U6732 ( .A(n10956), .B(n10962), .Y(n10964) );
NAND2X2TS U6733 ( .A(n10956), .B(n9363), .Y(n9365) );
INVX12TS U6734 ( .A(n7937), .Y(n9399) );
AO21X4TS U6735 ( .A0(n2067), .A1(n2577), .B0(n6433), .Y(n8141) );
XNOR2X4TS U6736 ( .A(n2590), .B(n7369), .Y(n3662) );
XNOR2X4TS U6737 ( .A(n2068), .B(n2653), .Y(n3661) );
OAI21X2TS U6738 ( .A0(n1824), .A1(n8345), .B0(n8344), .Y(n8350) );
OAI22X2TS U6739 ( .A0(n4028), .A1(n2411), .B0(n1923), .B1(n2842), .Y(n4016)
);
BUFX20TS U6740 ( .A(n7627), .Y(n2072) );
OAI21X2TS U6741 ( .A0(n7916), .A1(n7877), .B0(n7876), .Y(n7878) );
OAI21X2TS U6742 ( .A0(n7916), .A1(n7841), .B0(n7840), .Y(n7842) );
OAI21X2TS U6743 ( .A0(n2072), .A1(n7883), .B0(n7882), .Y(n7884) );
OAI21X2TS U6744 ( .A0(n2072), .A1(n7880), .B0(n7879), .Y(n7881) );
OAI21X2TS U6745 ( .A0(n2072), .A1(n7887), .B0(n7886), .Y(n7888) );
OAI21X2TS U6746 ( .A0(n2072), .A1(n7834), .B0(n7833), .Y(n7835) );
OAI21X2TS U6747 ( .A0(n2072), .A1(n7851), .B0(n7850), .Y(n7852) );
NOR2X4TS U6748 ( .A(n2076), .B(n10843), .Y(n10845) );
NOR2X4TS U6749 ( .A(n2076), .B(n10890), .Y(n10892) );
NOR2X4TS U6750 ( .A(n2075), .B(n10914), .Y(n10916) );
NOR2X4TS U6751 ( .A(n2076), .B(n10932), .Y(n10934) );
OAI22X2TS U6752 ( .A0(n2077), .A1(n7349), .B0(n7489), .B1(n11777), .Y(n7129)
);
NOR2X2TS U6753 ( .A(n3390), .B(n951), .Y(n7348) );
OAI22X2TS U6754 ( .A0(n1883), .A1(n7438), .B0(n2077), .B1(n2503), .Y(n7098)
);
CLKINVX12TS U6755 ( .A(n2078), .Y(n2860) );
NOR2X2TS U6756 ( .A(n2082), .B(n1405), .Y(n6011) );
OAI22X2TS U6757 ( .A0(n1084), .A1(n5801), .B0(n2081), .B1(n5766), .Y(n5803)
);
BUFX12TS U6758 ( .A(n10960), .Y(n2083) );
OAI21X2TS U6759 ( .A0(n2083), .A1(n10906), .B0(n10905), .Y(n10907) );
OAI21X2TS U6760 ( .A0(n2084), .A1(n10890), .B0(n10889), .Y(n10891) );
OAI21X2TS U6761 ( .A0(n2084), .A1(n10914), .B0(n10913), .Y(n10915) );
OAI21X2TS U6762 ( .A0(n2083), .A1(n10932), .B0(n10931), .Y(n10933) );
OAI21X2TS U6763 ( .A0(n2084), .A1(n10897), .B0(n10896), .Y(n10898) );
BUFX16TS U6764 ( .A(n7918), .Y(n2086) );
NAND2X2TS U6765 ( .A(n2085), .B(n10930), .Y(n10932) );
NAND2X2TS U6766 ( .A(n2086), .B(n10888), .Y(n10890) );
NAND2X2TS U6767 ( .A(n2085), .B(n10912), .Y(n10914) );
XNOR2X4TS U6768 ( .A(n2092), .B(n790), .Y(n7280) );
OAI22X2TS U6769 ( .A0(n6438), .A1(n1961), .B0(n6553), .B1(n2097), .Y(n6546)
);
OAI22X2TS U6770 ( .A0(n730), .A1(n4166), .B0(n7471), .B1(n4106), .Y(n4176)
);
BUFX16TS U6771 ( .A(n3391), .Y(n2102) );
AO21X2TS U6772 ( .A0(n2103), .A1(n6040), .B0(n6161), .Y(n3401) );
OAI22X4TS U6773 ( .A0(n2103), .A1(n3529), .B0(n1948), .B1(n3497), .Y(n3545)
);
OAI22X2TS U6774 ( .A0(n6179), .A1(n2104), .B0(n1919), .B1(n6155), .Y(n6207)
);
OAI22X2TS U6775 ( .A0(n6744), .A1(n2647), .B0(n6785), .B1(n8643), .Y(n6805)
);
INVX2TS U6776 ( .A(n8643), .Y(n3059) );
OAI22X4TS U6777 ( .A0(n6924), .A1(n8643), .B0(n6700), .B1(n2647), .Y(n6966)
);
OAI22X2TS U6778 ( .A0(n1964), .A1(n7256), .B0(n7993), .B1(n7060), .Y(n7268)
);
OAI22X4TS U6779 ( .A0(n7276), .A1(n728), .B0(n7993), .B1(n7256), .Y(n7284)
);
OAI22X4TS U6780 ( .A0(n7992), .A1(n1964), .B0(n7993), .B1(n7276), .Y(n8000)
);
OAI21X1TS U6781 ( .A0(n9298), .A1(n9037), .B0(n9036), .Y(n9038) );
INVX2TS U6782 ( .A(Op_MY[54]), .Y(n2116) );
CLKBUFX2TS U6783 ( .A(Add_result[42]), .Y(n2121) );
CLKBUFX2TS U6784 ( .A(Add_result[45]), .Y(n2122) );
CLKBUFX2TS U6785 ( .A(Add_result[50]), .Y(n2123) );
NAND2X2TS U6786 ( .A(n11067), .B(n11069), .Y(n10616) );
INVX2TS U6787 ( .A(n2124), .Y(n2125) );
OAI22X1TS U6788 ( .A0(n7291), .A1(n1020), .B0(n7181), .B1(n2019), .Y(n7312)
);
XNOR2X4TS U6789 ( .A(n8898), .B(n1967), .Y(n7181) );
INVX2TS U6790 ( .A(n2126), .Y(n2127) );
INVX12TS U6791 ( .A(n2242), .Y(n8444) );
OAI22X1TS U6792 ( .A0(n2110), .A1(n4991), .B0(n1898), .B1(n5013), .Y(n5024)
);
XNOR2X2TS U6793 ( .A(n5270), .B(n7369), .Y(n4579) );
INVX2TS U6794 ( .A(n2129), .Y(n2130) );
XNOR2X4TS U6795 ( .A(n11598), .B(n11599), .Y(n7716) );
NAND2X2TS U6796 ( .A(n3314), .B(n583), .Y(n11493) );
MXI2X4TS U6797 ( .A(n9717), .B(n11897), .S0(n10299), .Y(n583) );
NOR2BX4TS U6798 ( .AN(n2591), .B(n1713), .Y(n4827) );
AOI21X2TS U6799 ( .A0(n9193), .A1(n7706), .B0(n7705), .Y(n9170) );
OAI21X2TS U6800 ( .A0(n11410), .A1(n9196), .B0(n1127), .Y(n7705) );
OAI21X1TS U6801 ( .A0(n7900), .A1(n11600), .B0(n11601), .Y(n7901) );
AOI21X4TS U6802 ( .A0(n1156), .A1(n1136), .B0(n11629), .Y(n7900) );
OAI21X1TS U6803 ( .A0(n9571), .A1(n8346), .B0(n8347), .Y(n7599) );
OAI22X2TS U6804 ( .A0(n6905), .A1(n1955), .B0(n2003), .B1(n2109), .Y(n6902)
);
XNOR2X2TS U6805 ( .A(n6529), .B(n2021), .Y(n6905) );
NAND4BX2TS U6806 ( .AN(n12213), .B(n11809), .C(n11945), .D(n12145), .Y(
n11226) );
NAND2X4TS U6807 ( .A(n9627), .B(n9626), .Y(n9634) );
NAND2X2TS U6808 ( .A(n11267), .B(n11265), .Y(n11092) );
NAND2X1TS U6809 ( .A(n7910), .B(n7902), .Y(n7904) );
NAND2X4TS U6810 ( .A(n2917), .B(n9342), .Y(n9636) );
XNOR2X4TS U6811 ( .A(n7401), .B(n951), .Y(n9657) );
AND2X2TS U6812 ( .A(n2399), .B(n7489), .Y(n7401) );
MXI2X4TS U6813 ( .A(n10309), .B(n11965), .S0(n10326), .Y(n596) );
MXI2X4TS U6814 ( .A(n10307), .B(n11961), .S0(n10326), .Y(n594) );
MXI2X4TS U6815 ( .A(n10311), .B(n11963), .S0(n10310), .Y(n624) );
INVX2TS U6816 ( .A(n660), .Y(n10278) );
MXI2X4TS U6817 ( .A(n9689), .B(n11816), .S0(n11131), .Y(n666) );
MXI2X4TS U6818 ( .A(n9687), .B(n11969), .S0(n9718), .Y(n683) );
MXI2X4TS U6819 ( .A(n9668), .B(n11900), .S0(n9731), .Y(n662) );
NAND2X2TS U6820 ( .A(n10535), .B(n10534), .Y(n10582) );
NOR2X2TS U6821 ( .A(n10535), .B(n10534), .Y(n10558) );
NAND3X2TS U6822 ( .A(n10720), .B(n10719), .C(n10718), .Y(n359) );
NAND2X2TS U6823 ( .A(n11271), .B(n11268), .Y(n10413) );
NOR2X2TS U6824 ( .A(n11107), .B(n10554), .Y(n11102) );
OAI22X2TS U6825 ( .A0(n7162), .A1(n2165), .B0(n7170), .B1(n2036), .Y(n7163)
);
INVX2TS U6826 ( .A(n2134), .Y(n2135) );
NOR2X8TS U6827 ( .A(n9369), .B(FSM_selector_C), .Y(n10681) );
INVX2TS U6828 ( .A(n2136), .Y(n2137) );
NAND2X2TS U6829 ( .A(n2138), .B(n10973), .Y(n12321) );
NAND2X2TS U6830 ( .A(n2138), .B(n10885), .Y(n12325) );
ADDFHX2TS U6831 ( .A(n6911), .B(n6910), .CI(n6909), .CO(n6962), .S(n6901) );
OAI2BB1X4TS U6832 ( .A0N(n8271), .A1N(n8270), .B0(n2809), .Y(n8266) );
ADDFHX4TS U6833 ( .A(n5727), .B(n5728), .CI(n5726), .CO(n5749), .S(n5789) );
OAI2BB1X4TS U6834 ( .A0N(n3477), .A1N(n3478), .B0(n2139), .Y(n3456) );
XOR2X4TS U6835 ( .A(n3476), .B(n3477), .Y(n2140) );
OAI22X4TS U6836 ( .A0(n2024), .A1(n4836), .B0(n5325), .B1(n4835), .Y(n4865)
);
OAI22X4TS U6837 ( .A0(n4140), .A1(n6003), .B0(n2080), .B1(n4139), .Y(n4181)
);
XOR2X4TS U6838 ( .A(n3118), .B(n2141), .Y(n9976) );
INVX4TS U6839 ( .A(n9030), .Y(n2141) );
OAI22X4TS U6840 ( .A0(n2206), .A1(n2100), .B0(n3482), .B1(n7471), .Y(n3533)
);
OAI22X4TS U6841 ( .A0(n1806), .A1(n7053), .B0(n5320), .B1(n7014), .Y(n7059)
);
OAI22X4TS U6842 ( .A0(n6056), .A1(n2103), .B0(n1948), .B1(n6162), .Y(n6190)
);
XNOR2X4TS U6843 ( .A(n1816), .B(DP_OP_168J26_122_4811_n6776), .Y(n5883) );
OAI22X2TS U6844 ( .A0(n5925), .A1(n2575), .B0(n6476), .B1(n2113), .Y(n5993)
);
XNOR2X4TS U6845 ( .A(n5237), .B(n2094), .Y(n4597) );
XOR2X4TS U6846 ( .A(n2143), .B(n1372), .Y(n9283) );
NAND2X8TS U6847 ( .A(n2921), .B(n2920), .Y(n2144) );
OAI2BB1X4TS U6848 ( .A0N(n2146), .A1N(n2145), .B0(n8204), .Y(n2973) );
ADDFHX4TS U6849 ( .A(n3905), .B(n3904), .CI(n3903), .CO(n3884), .S(n4124) );
OAI22X2TS U6850 ( .A0(n1980), .A1(n3963), .B0(n2157), .B1(n4540), .Y(n4535)
);
OAI22X2TS U6851 ( .A0(n4911), .A1(n11758), .B0(n2096), .B1(n4957), .Y(n4938)
);
OAI22X2TS U6852 ( .A0(n7486), .A1(n7485), .B0(n786), .B1(n7484), .Y(n7516)
);
ADDFHX4TS U6853 ( .A(n3463), .B(n3462), .CI(n3461), .CO(n3428), .S(n3506) );
OAI22X2TS U6854 ( .A0(n4621), .A1(n2331), .B0(n4812), .B1(n5488), .Y(n4654)
);
OAI22X2TS U6855 ( .A0(n4369), .A1(n2050), .B0(n4368), .B1(n8931), .Y(n8568)
);
NAND2X8TS U6856 ( .A(n2428), .B(n2149), .Y(n6371) );
NOR2X4TS U6857 ( .A(n7716), .B(n11402), .Y(n9135) );
INVX12TS U6858 ( .A(n2213), .Y(n4061) );
OAI22X4TS U6859 ( .A0(n1853), .A1(n4127), .B0(n4104), .B1(n2062), .Y(n4178)
);
XNOR2X4TS U6860 ( .A(n954), .B(n2643), .Y(n4104) );
ADDFHX4TS U6861 ( .A(n7112), .B(n7111), .CI(n7110), .CO(n7194), .S(n7152) );
AOI21X4TS U6862 ( .A0(n1465), .A1(n1345), .B0(n2753), .Y(n2905) );
OAI2BB1X4TS U6863 ( .A0N(n1318), .A1N(n1280), .B0(n2799), .Y(n9789) );
INVX8TS U6864 ( .A(n6612), .Y(n6659) );
OAI22X4TS U6865 ( .A0(n5304), .A1(n5303), .B0(n5305), .B1(n8025), .Y(n5391)
);
BUFX3TS U6866 ( .A(n5452), .Y(n2153) );
OAI22X4TS U6867 ( .A0(n2159), .A1(n6001), .B0(n973), .B1(n6059), .Y(n6046)
);
OAI22X4TS U6868 ( .A0(n7280), .A1(n7997), .B0(n1951), .B1(n7257), .Y(n7283)
);
OA22X4TS U6869 ( .A0(n2077), .A1(DP_OP_168J26_122_4811_n7818), .B0(n1624),
.B1(n7233), .Y(n2154) );
OAI22X4TS U6870 ( .A0(n2087), .A1(n3819), .B0(n3133), .B1(n1925), .Y(n3799)
);
XNOR2X4TS U6871 ( .A(n11581), .B(n945), .Y(n5300) );
OAI22X4TS U6872 ( .A0(n7486), .A1(n7096), .B0(n786), .B1(n2564), .Y(n7132)
);
OAI22X4TS U6873 ( .A0(n3399), .A1(n2073), .B0(n3404), .B1(n1897), .Y(n3403)
);
OAI2BB1X4TS U6874 ( .A0N(n6263), .A1N(n6264), .B0(n2155), .Y(n6269) );
XNOR2X4TS U6875 ( .A(n2156), .B(n4895), .Y(n4898) );
OAI22X2TS U6876 ( .A0(n3535), .A1(n1853), .B0(n2063), .B1(n3500), .Y(n3548)
);
XNOR2X4TS U6877 ( .A(n2068), .B(n1885), .Y(n4956) );
XOR2X4TS U6878 ( .A(n2014), .B(n11781), .Y(n3842) );
INVX6TS U6879 ( .A(n8238), .Y(n7157) );
NAND2X4TS U6880 ( .A(n1836), .B(n496), .Y(n12358) );
NOR2X8TS U6881 ( .A(n2158), .B(n3248), .Y(n7429) );
NOR2X8TS U6882 ( .A(n3108), .B(n9491), .Y(n2158) );
XNOR2X4TS U6883 ( .A(n6093), .B(n6156), .Y(n6048) );
AOI2BB2X4TS U6884 ( .B0(n10947), .B1(n10970), .A0N(n10860), .A1N(n11854),
.Y(n12307) );
XNOR2X4TS U6885 ( .A(n5175), .B(n5270), .Y(n3699) );
OAI22X4TS U6886 ( .A0(n1083), .A1(n6149), .B0(n2080), .B1(n6147), .Y(n6158)
);
NAND2X2TS U6887 ( .A(n7771), .B(n1281), .Y(n7775) );
XNOR2X4TS U6888 ( .A(n1813), .B(n1006), .Y(n6151) );
OAI22X4TS U6889 ( .A0(n8579), .A1(n5501), .B0(n8581), .B1(n5502), .Y(n5776)
);
XNOR2X4TS U6890 ( .A(n8510), .B(n2657), .Y(n5502) );
AOI2BB2X2TS U6891 ( .B0(n10674), .B1(n483), .A0N(n10860), .A1N(n11878), .Y(
n10712) );
OAI22X2TS U6892 ( .A0(DP_OP_168J26_122_4811_n5162), .A1(n945), .B0(n1718),
.B1(n765), .Y(n7090) );
OAI22X2TS U6893 ( .A0(n1981), .A1(n5168), .B0(n2568), .B1(n5211), .Y(n5232)
);
INVX8TS U6894 ( .A(n1030), .Y(n7862) );
OAI21X2TS U6895 ( .A0(n7916), .A1(n7846), .B0(n7845), .Y(n7847) );
OR2X4TS U6896 ( .A(n11605), .B(n11604), .Y(n2307) );
AND2X8TS U6897 ( .A(n6429), .B(n2252), .Y(n6461) );
INVX2TS U6898 ( .A(n8844), .Y(n7805) );
NAND2X8TS U6899 ( .A(n1739), .B(n2160), .Y(n9625) );
ADDFHX4TS U6900 ( .A(n3717), .B(n3718), .CI(n3716), .CO(n3719), .S(n3811) );
ADDFHX4TS U6901 ( .A(n3813), .B(n3812), .CI(n3811), .CO(n3863), .S(n3866) );
XNOR2X4TS U6902 ( .A(n1887), .B(n5270), .Y(n3670) );
XNOR2X4TS U6903 ( .A(n5270), .B(n2409), .Y(n5326) );
OAI22X4TS U6904 ( .A0(n5326), .A1(n2024), .B0(n5324), .B1(n1990), .Y(n5380)
);
OAI22X2TS U6905 ( .A0(n6172), .A1(n6174), .B0(n11757), .B1(n5963), .Y(n6218)
);
XNOR2X4TS U6906 ( .A(n2455), .B(n5175), .Y(n4554) );
ADDFHX2TS U6907 ( .A(n7408), .B(n7407), .CI(n7406), .CO(n9451), .S(n7403) );
OAI22X2TS U6908 ( .A0(n1934), .A1(n3849), .B0(n1991), .B1(n3804), .Y(n3856)
);
XNOR2X2TS U6909 ( .A(n6835), .B(n1971), .Y(n4097) );
INVX2TS U6910 ( .A(n7605), .Y(n7398) );
XOR2X4TS U6911 ( .A(n2578), .B(n1338), .Y(n6258) );
NOR2X8TS U6912 ( .A(n2494), .B(n6285), .Y(n10175) );
OAI22X4TS U6913 ( .A0(n1815), .A1(DP_OP_168J26_122_4811_n7949), .B0(n2043),
.B1(n7446), .Y(n7437) );
OAI21X1TS U6914 ( .A0(n10549), .A1(n10568), .B0(n10548), .Y(n10550) );
CLKXOR2X2TS U6915 ( .A(n11107), .B(n1384), .Y(n10544) );
OAI22X2TS U6916 ( .A0(n1866), .A1(n11674), .B0(n2062), .B1(n6005), .Y(n6023)
);
ADDFHX4TS U6917 ( .A(n7168), .B(n7166), .CI(n7167), .CO(n7190), .S(n7176) );
XOR2X4TS U6918 ( .A(n6965), .B(n6964), .Y(n3285) );
OAI22X4TS U6919 ( .A0(n1806), .A1(n8010), .B0(n8009), .B1(n8008), .Y(n8049)
);
OAI22X4TS U6920 ( .A0(n5300), .A1(n1925), .B0(n5301), .B1(n2087), .Y(n5392)
);
OAI2BB1X4TS U6921 ( .A0N(n2910), .A1N(n4818), .B0(n2167), .Y(n9874) );
OAI21X4TS U6922 ( .A0(n2910), .A1(n4818), .B0(n4817), .Y(n2167) );
OAI22X2TS U6923 ( .A0(n8981), .A1(n1986), .B0(n8979), .B1(n2051), .Y(n9009)
);
XOR2X4TS U6924 ( .A(n2168), .B(n881), .Y(n4324) );
XOR2X4TS U6925 ( .A(n2777), .B(n4280), .Y(n2168) );
ADDFHX2TS U6926 ( .A(n7089), .B(n7090), .CI(n7088), .CO(n7142), .S(n7125) );
NAND2X8TS U6927 ( .A(n2944), .B(n2169), .Y(n2943) );
OAI2BB1X4TS U6928 ( .A0N(n2981), .A1N(n2982), .B0(n6687), .Y(n2171) );
OAI22X2TS U6929 ( .A0(n2025), .A1(n4980), .B0(n5325), .B1(n4966), .Y(n5025)
);
XNOR2X4TS U6930 ( .A(n2172), .B(n6881), .Y(n6952) );
XOR2X4TS U6931 ( .A(n6882), .B(n6709), .Y(n2172) );
OAI22X2TS U6932 ( .A0(n1936), .A1(n4557), .B0(n1989), .B1(n4556), .Y(n4576)
);
XOR2X4TS U6933 ( .A(n1876), .B(n2521), .Y(n2209) );
ADDFHX4TS U6934 ( .A(n4151), .B(n4150), .CI(n4149), .CO(n4160), .S(n4156) );
CLKBUFX2TS U6935 ( .A(n9903), .Y(n2173) );
ADDFHX4TS U6936 ( .A(n4440), .B(n4439), .CI(n4438), .CO(n4504), .S(n4508) );
OAI21X4TS U6937 ( .A0(DP_OP_168J26_122_4811_n3475), .A1(n4078), .B0(n3943),
.Y(n3372) );
OAI22X2TS U6938 ( .A0(n5544), .A1(n8581), .B0(n5498), .B1(n8579), .Y(n5518)
);
BUFX20TS U6939 ( .A(DP_OP_168J26_122_4811_n8177), .Y(n2380) );
XNOR2X4TS U6940 ( .A(n8911), .B(n8896), .Y(n4346) );
ADDFHX4TS U6941 ( .A(n6794), .B(n6795), .CI(n6796), .CO(n6806), .S(n6818) );
NAND2X2TS U6942 ( .A(n11738), .B(DP_OP_168J26_122_4811_n3596), .Y(n4001) );
ADDFHX4TS U6943 ( .A(n4722), .B(n4721), .CI(n4720), .CO(n4767), .S(n9925) );
OAI21X4TS U6944 ( .A0(n10224), .A1(n10226), .B0(n10227), .Y(n6138) );
NOR2BX2TS U6945 ( .AN(n5666), .B(n2450), .Y(n6074) );
ADDFHX4TS U6946 ( .A(n6074), .B(n6073), .CI(n6072), .CO(n6740), .S(n6738) );
XNOR2X4TS U6947 ( .A(n1819), .B(n8897), .Y(n4732) );
ADDFHX4TS U6948 ( .A(n5775), .B(n5773), .CI(n5774), .CO(n5834), .S(n5816) );
XNOR2X4TS U6949 ( .A(n1831), .B(n7272), .Y(n5327) );
OAI22X4TS U6950 ( .A0(n3527), .A1(n7445), .B0(n1918), .B1(n3486), .Y(n3542)
);
OAI21X4TS U6951 ( .A0(n5206), .A1(n1639), .B0(n5205), .Y(n2747) );
INVX4TS U6952 ( .A(n6398), .Y(n4648) );
INVX6TS U6953 ( .A(n6534), .Y(n6574) );
XNOR2X4TS U6954 ( .A(n7270), .B(DP_OP_168J26_122_4811_n8482), .Y(n3976) );
ADDFHX4TS U6955 ( .A(n6914), .B(n6913), .CI(n6912), .CO(n6961), .S(n6899) );
ADDFHX4TS U6956 ( .A(n4880), .B(n4879), .CI(n4878), .CO(n4886), .S(n4905) );
XNOR2X4TS U6957 ( .A(n2069), .B(n7272), .Y(n3851) );
OAI22X4TS U6958 ( .A0(n2104), .A1(n3486), .B0(n1921), .B1(n3470), .Y(n3490)
);
ADDFHX4TS U6959 ( .A(n3489), .B(n3490), .CI(n3488), .CO(n3509), .S(n3550) );
OAI21X4TS U6960 ( .A0(n3584), .A1(n2178), .B0(n3589), .Y(n3601) );
CLKINVX6TS U6961 ( .A(n9985), .Y(DP_OP_168J26_122_4811_n333) );
INVX16TS U6962 ( .A(n2181), .Y(n2182) );
OAI22X4TS U6963 ( .A0(n6058), .A1(n2029), .B0(n11754), .B1(n2184), .Y(n6189)
);
XOR2X4TS U6964 ( .A(n731), .B(n11527), .Y(n2184) );
XOR2X4TS U6965 ( .A(n3047), .B(n7277), .Y(n2185) );
OAI2BB1X4TS U6966 ( .A0N(n5997), .A1N(n1340), .B0(n2186), .Y(n8243) );
OAI21X4TS U6967 ( .A0(n1340), .A1(n5997), .B0(n5996), .Y(n2186) );
AOI21X4TS U6968 ( .A0(n7625), .A1(n7669), .B0(n2188), .Y(n2187) );
NOR2X8TS U6969 ( .A(n2196), .B(n2195), .Y(n7627) );
AND3X8TS U6970 ( .A(n2197), .B(n7667), .C(n7626), .Y(n2195) );
BUFX20TS U6971 ( .A(n2200), .Y(n2202) );
NAND2BX4TS U6972 ( .AN(n10943), .B(n2204), .Y(n2203) );
OAI21X4TS U6973 ( .A0(n2205), .A1(n2065), .B0(n10944), .Y(n2204) );
CLKINVX6TS U6974 ( .A(n7609), .Y(n7610) );
OAI21X4TS U6975 ( .A0(n5791), .A1(n5790), .B0(n5789), .Y(n3217) );
OAI22X4TS U6976 ( .A0(n2206), .A1(n1916), .B0(n2100), .B1(n3879), .Y(n3904)
);
OAI21X4TS U6977 ( .A0(n6295), .A1(n6296), .B0(n6294), .Y(n2613) );
XNOR2X4TS U6978 ( .A(n1805), .B(n1913), .Y(n5757) );
XNOR2X4TS U6979 ( .A(n760), .B(n6145), .Y(n3883) );
XNOR2X4TS U6980 ( .A(n952), .B(n2207), .Y(n3528) );
XOR2X4TS U6981 ( .A(n2643), .B(n2207), .Y(n5649) );
XOR2X4TS U6982 ( .A(n2669), .B(n2207), .Y(n5648) );
OAI22X4TS U6983 ( .A0(n6100), .A1(n6174), .B0(n2450), .B1(n2209), .Y(n6123)
);
OAI22X4TS U6984 ( .A0(n3107), .A1(n11757), .B0(n6174), .B1(n2209), .Y(n6120)
);
NOR2X8TS U6985 ( .A(n10026), .B(n10028), .Y(n9587) );
NOR2X8TS U6986 ( .A(n7320), .B(n7319), .Y(n10028) );
OAI22X4TS U6987 ( .A0(n5752), .A1(n1227), .B0(n2089), .B1(n2210), .Y(n5798)
);
XOR2X4TS U6988 ( .A(n1816), .B(n6141), .Y(n2210) );
INVX16TS U6989 ( .A(n2211), .Y(n8540) );
XNOR2X4TS U6990 ( .A(n3778), .B(n3777), .Y(n2211) );
NOR2X8TS U6991 ( .A(n3203), .B(DP_OP_168J26_122_4811_n3579), .Y(n3778) );
OAI22X4TS U6992 ( .A0(n5578), .A1(n2060), .B0(n1222), .B1(n2212), .Y(n5602)
);
XNOR2X4TS U6993 ( .A(n976), .B(n1931), .Y(n2212) );
NAND2X8TS U6994 ( .A(n4061), .B(n2214), .Y(n4060) );
XOR2X4TS U6995 ( .A(n2215), .B(n3946), .Y(n2214) );
OAI2BB1X4TS U6996 ( .A0N(n3734), .A1N(n2220), .B0(n2218), .Y(n3968) );
OAI21X4TS U6997 ( .A0(n3734), .A1(n2220), .B0(n3733), .Y(n2218) );
XOR2X4TS U6998 ( .A(n2219), .B(n3734), .Y(n3727) );
XOR2X4TS U6999 ( .A(n3733), .B(n2220), .Y(n2219) );
OAI22X4TS U7000 ( .A0(n3186), .A1(n2046), .B0(n2222), .B1(n3077), .Y(n3730)
);
XOR2X4TS U7001 ( .A(n2094), .B(n3078), .Y(n3077) );
NAND2X8TS U7002 ( .A(n3658), .B(DP_OP_168J26_122_4811_n6610), .Y(n2424) );
XOR2X4TS U7003 ( .A(n9526), .B(n9525), .Y(n2225) );
XOR2X4TS U7004 ( .A(n10753), .B(n10752), .Y(n2227) );
XOR2X4TS U7005 ( .A(n2231), .B(n11341), .Y(n2230) );
OAI21X4TS U7006 ( .A0(n2230), .A1(n1216), .B0(n12204), .Y(n10970) );
OAI21X4TS U7007 ( .A0(n2201), .A1(n10928), .B0(n10927), .Y(n2231) );
XOR2X4TS U7008 ( .A(n7788), .B(n2232), .Y(n7795) );
OAI22X4TS U7009 ( .A0(n4261), .A1(n8643), .B0(n8641), .B1(n1871), .Y(n4375)
);
XNOR2X4TS U7010 ( .A(n913), .B(n8626), .Y(n4261) );
XOR2X4TS U7011 ( .A(n2234), .B(n8294), .Y(n8303) );
XOR2X4TS U7012 ( .A(n8293), .B(n2682), .Y(n2234) );
XNOR2X4TS U7013 ( .A(n2235), .B(n6440), .Y(n2682) );
XNOR2X4TS U7014 ( .A(n6425), .B(n2794), .Y(n2235) );
INVX2TS U7015 ( .A(DP_OP_168J26_122_4811_n376), .Y(
DP_OP_168J26_122_4811_n374) );
NAND2X8TS U7016 ( .A(DP_OP_168J26_122_4811_n1006), .B(
DP_OP_168J26_122_4811_n1029), .Y(DP_OP_168J26_122_4811_n376) );
OAI22X4TS U7017 ( .A0(n6475), .A1(n1932), .B0(n1969), .B1(n2236), .Y(n6511)
);
XNOR2X2TS U7018 ( .A(n8892), .B(n8619), .Y(n2236) );
INVX16TS U7019 ( .A(n2239), .Y(n2549) );
XNOR2X4TS U7020 ( .A(n2238), .B(n1954), .Y(n6704) );
XOR2X4TS U7021 ( .A(n3371), .B(n3370), .Y(n2239) );
INVX16TS U7022 ( .A(n3376), .Y(n2658) );
NAND2X8TS U7023 ( .A(n2241), .B(n2240), .Y(n3376) );
AOI21X4TS U7024 ( .A0(DP_OP_168J26_122_4811_n3579), .A1(n2245), .B0(n2244),
.Y(n2240) );
XNOR2X4TS U7025 ( .A(n8887), .B(n1565), .Y(n5513) );
XNOR2X4TS U7026 ( .A(n2243), .B(n1377), .Y(n2242) );
OAI21X4TS U7027 ( .A0(n3778), .A1(DP_OP_168J26_122_4811_n3571), .B0(
DP_OP_168J26_122_4811_n3572), .Y(n2243) );
NAND2X8TS U7028 ( .A(DP_OP_168J26_122_4811_n8453), .B(
DP_OP_168J26_122_4811_n8478), .Y(n3779) );
NOR2X8TS U7029 ( .A(DP_OP_168J26_122_4811_n3560), .B(
DP_OP_168J26_122_4811_n3571), .Y(n2245) );
NOR3X8TS U7030 ( .A(n2247), .B(n3628), .C(n2890), .Y(n2246) );
NAND2BX2TS U7031 ( .AN(n6884), .B(n8539), .Y(n5495) );
OAI22X2TS U7032 ( .A0(n2379), .A1(n5650), .B0(n1897), .B1(n5862), .Y(n5881)
);
XOR2X4TS U7033 ( .A(n2249), .B(n1142), .Y(n10830) );
OAI2BB1X4TS U7034 ( .A0N(n2618), .A1N(n10829), .B0(n10828), .Y(n2249) );
ADDFHX4TS U7035 ( .A(n6660), .B(n6659), .CI(n6658), .CO(n6624), .S(n6695) );
NAND2X2TS U7036 ( .A(n2086), .B(n10823), .Y(n10825) );
XOR2X4TS U7037 ( .A(n2570), .B(n6433), .Y(n8939) );
ADDFHX4TS U7038 ( .A(n3688), .B(n3687), .CI(n3686), .CO(n3720), .S(n3826) );
XOR2X4TS U7039 ( .A(n2899), .B(n2250), .Y(n2288) );
ADDFHX4TS U7040 ( .A(n6484), .B(n6482), .CI(n6483), .CO(n8248), .S(n8245) );
OAI22X4TS U7041 ( .A0(n1876), .A1(n7490), .B0(n1883), .B1(n1686), .Y(n2359)
);
BUFX20TS U7042 ( .A(n6402), .Y(n2410) );
NAND2X2TS U7043 ( .A(n6620), .B(n6621), .Y(n6603) );
OAI22X4TS U7044 ( .A0(n4346), .A1(n2293), .B0(n4341), .B1(n1893), .Y(n4388)
);
OAI22X4TS U7045 ( .A0(n6407), .A1(n8518), .B0(n6408), .B1(n2581), .Y(n2252)
);
OAI22X2TS U7046 ( .A0(n1980), .A1(n4230), .B0(n2157), .B1(n4020), .Y(n4221)
);
OAI22X2TS U7047 ( .A0(n2434), .A1(n12029), .B0(n765), .B1(n1645), .Y(n7213)
);
XNOR2X4TS U7048 ( .A(n8270), .B(n8271), .Y(n2593) );
OAI22X4TS U7049 ( .A0(n4554), .A1(n1820), .B0(n4593), .B1(n1900), .Y(n4610)
);
OAI22X4TS U7050 ( .A0(n3693), .A1(n1981), .B0(n3676), .B1(n2568), .Y(n3717)
);
INVX8TS U7051 ( .A(n8986), .Y(n9085) );
INVX6TS U7052 ( .A(n2255), .Y(n3043) );
OAI21X4TS U7053 ( .A0(n5217), .A1(n5218), .B0(n5216), .Y(n3100) );
OAI22X2TS U7054 ( .A0(n942), .A1(n1934), .B0(n5325), .B1(n3698), .Y(n3708)
);
OAI22X4TS U7055 ( .A0(n2504), .A1(n6564), .B0(n8907), .B1(n6563), .Y(n6640)
);
OAI22X2TS U7056 ( .A0(n5950), .A1(n5623), .B0(n5622), .B1(n2150), .Y(n5707)
);
XNOR2X4TS U7057 ( .A(n1715), .B(n1807), .Y(n5753) );
OAI22X2TS U7058 ( .A0(n2027), .A1(n4026), .B0(n1988), .B1(n3829), .Y(n4044)
);
OAI22X4TS U7059 ( .A0(n1820), .A1(n4226), .B0(n2048), .B1(n4041), .Y(n4246)
);
OAI22X2TS U7060 ( .A0(n2025), .A1(n4910), .B0(n1990), .B1(n4883), .Y(n4915)
);
OAI22X4TS U7061 ( .A0(n1222), .A1(n7440), .B0(n2060), .B1(n7480), .Y(n7466)
);
OAI22X4TS U7062 ( .A0(n3801), .A1(n2422), .B0(n3692), .B1(n2114), .Y(n3798)
);
ADDHX4TS U7063 ( .A(n5760), .B(n5759), .CO(n5771), .S(n5806) );
ADDFHX4TS U7064 ( .A(n4332), .B(n4331), .CI(n4330), .CO(n4339), .S(n9832) );
XOR2X4TS U7065 ( .A(n7488), .B(n1391), .Y(n3878) );
OAI22X4TS U7066 ( .A0(n2222), .A1(n3715), .B0(n2046), .B1(n3074), .Y(n3690)
);
XOR2X4TS U7067 ( .A(n11525), .B(n7438), .Y(n4446) );
XNOR2X2TS U7068 ( .A(n8620), .B(n2410), .Y(n8631) );
OAI22X4TS U7069 ( .A0(n2434), .A1(n1741), .B0(n2550), .B1(n11781), .Y(n7258)
);
OAI22X4TS U7070 ( .A0(n6174), .A1(n6016), .B0(n11757), .B1(n6044), .Y(n6054)
);
OAI22X2TS U7071 ( .A0(n2104), .A1(n5706), .B0(n1919), .B1(n5627), .Y(n5710)
);
XOR2X4TS U7072 ( .A(n2390), .B(n2590), .Y(n2993) );
XOR2X2TS U7073 ( .A(n2014), .B(n1645), .Y(n4528) );
ADDFHX4TS U7074 ( .A(n4709), .B(n4710), .CI(n6392), .CO(n4737), .S(n4741) );
NOR2X2TS U7075 ( .A(n10955), .B(n10853), .Y(n10855) );
ADDFHX4TS U7076 ( .A(n3430), .B(n3429), .CI(n3428), .CO(n3457), .S(n3494) );
OAI22X4TS U7077 ( .A0(n3880), .A1(n6094), .B0(n6097), .B1(n6142), .Y(n6106)
);
ADDFHX4TS U7078 ( .A(n6927), .B(n2132), .CI(n6925), .CO(n6932), .S(n6934) );
OAI22X4TS U7079 ( .A0(n1222), .A1(n3895), .B0(n3530), .B1(n3321), .Y(n3907)
);
ADDFHX4TS U7080 ( .A(n3908), .B(n3907), .CI(n3906), .CO(n3902), .S(n4123) );
NOR2X1TS U7081 ( .A(n4487), .B(n1907), .Y(n4735) );
ADDFX2TS U7082 ( .A(n4713), .B(n4712), .CI(n4711), .CO(n4719), .S(n9922) );
OAI22X4TS U7083 ( .A0(n1853), .A1(n3500), .B0(n2063), .B1(n3471), .Y(n3489)
);
OAI22X2TS U7084 ( .A0(n2018), .A1(n5649), .B0(n2450), .B1(n5648), .Y(n5882)
);
OAI22X4TS U7085 ( .A0(DP_OP_168J26_122_4811_n6594), .A1(n11783), .B0(n11769),
.B1(n2013), .Y(n3672) );
XNOR2X2TS U7086 ( .A(n8894), .B(n2031), .Y(n5939) );
OAI22X2TS U7087 ( .A0(n2128), .A1(n1823), .B0(n1396), .B1(n1986), .Y(n5899)
);
XNOR2X4TS U7088 ( .A(n2453), .B(n1019), .Y(n4517) );
OAI2BB1X4TS U7089 ( .A0N(n5441), .A1N(n5442), .B0(n2267), .Y(n5462) );
BUFX3TS U7090 ( .A(n5789), .Y(n2287) );
BUFX20TS U7091 ( .A(n2292), .Y(n2422) );
OAI22X4TS U7092 ( .A0(n2073), .A1(n5705), .B0(n1897), .B1(n5621), .Y(n5708)
);
OAI21X4TS U7093 ( .A0(n872), .A1(n5729), .B0(n5731), .Y(n2264) );
OAI22X4TS U7094 ( .A0(n4457), .A1(n2105), .B0(n1921), .B1(n2445), .Y(n4787)
);
OAI22X4TS U7095 ( .A0(n2090), .A1(n5625), .B0(n5589), .B1(n1227), .Y(n5611)
);
ADDFHX2TS U7096 ( .A(n11737), .B(n7517), .CI(n7518), .CO(n7547), .S(n7514)
);
OAI22X4TS U7097 ( .A0(n838), .A1(n4792), .B0(n4456), .B1(n1910), .Y(n4783)
);
XNOR2X4TS U7098 ( .A(n1019), .B(n2408), .Y(n5631) );
XNOR2X4TS U7099 ( .A(n2570), .B(n1967), .Y(n7223) );
NOR2X2TS U7100 ( .A(n4685), .B(n1907), .Y(n4726) );
XNOR2X2TS U7101 ( .A(n5256), .B(n944), .Y(n3654) );
OAI21X4TS U7102 ( .A0(n4896), .A1(n4897), .B0(n4895), .Y(n2266) );
XNOR2X4TS U7103 ( .A(n8894), .B(n1904), .Y(n4361) );
NOR2BX2TS U7104 ( .AN(n1809), .B(n5304), .Y(n4880) );
INVX2TS U7105 ( .A(n7590), .Y(n7110) );
XNOR2X2TS U7106 ( .A(n2069), .B(n1711), .Y(n5179) );
OAI22X4TS U7107 ( .A0(n2088), .A1(n5181), .B0(n5179), .B1(n1941), .Y(n5185)
);
XNOR2X4TS U7108 ( .A(n2570), .B(n2037), .Y(n7304) );
OAI22X4TS U7109 ( .A0(n8559), .A1(n1983), .B0(n8558), .B1(n1945), .Y(n8610)
);
ADDFHX4TS U7110 ( .A(n8611), .B(n8610), .CI(n8609), .CO(n8597), .S(n8636) );
ADDFHX4TS U7111 ( .A(n4848), .B(n4846), .CI(n4847), .CO(n5187), .S(n4853) );
NOR2X6TS U7112 ( .A(n11356), .B(n7945), .Y(n9313) );
CLKINVX12TS U7113 ( .A(n11478), .Y(n5572) );
OAI22X1TS U7114 ( .A0(n4298), .A1(n2056), .B0(n4260), .B1(n2259), .Y(n4322)
);
OAI22X4TS U7115 ( .A0(n3804), .A1(n4984), .B0(n3699), .B1(n5325), .Y(n3794)
);
XNOR2X2TS U7116 ( .A(n8511), .B(n8887), .Y(n5506) );
OAI22X4TS U7117 ( .A0(n2447), .A1(n4834), .B0(n1959), .B1(n4833), .Y(n4843)
);
OAI22X4TS U7118 ( .A0(n1820), .A1(n3668), .B0(n1900), .B1(n3960), .Y(n3979)
);
XNOR2X2TS U7119 ( .A(n3345), .B(n1927), .Y(n5514) );
XNOR2X2TS U7120 ( .A(n2484), .B(n8896), .Y(n8520) );
OR2X8TS U7121 ( .A(n3923), .B(n2446), .Y(n2718) );
OAI2BB1X4TS U7122 ( .A0N(n5975), .A1N(n5974), .B0(n2270), .Y(n5978) );
OAI21X4TS U7123 ( .A0(n5974), .A1(n5975), .B0(n5973), .Y(n2270) );
ADDFHX4TS U7124 ( .A(n5145), .B(n5144), .CI(n5143), .CO(n5199), .S(n5206) );
OAI2BB1X4TS U7125 ( .A0N(n1018), .A1N(n2272), .B0(n5207), .Y(n2847) );
BUFX20TS U7126 ( .A(n8889), .Y(n2936) );
ADDFHX4TS U7127 ( .A(n6252), .B(n6251), .CI(n6250), .CO(n6265), .S(n6273) );
OAI22X2TS U7128 ( .A0(n4724), .A1(n2588), .B0(n4803), .B1(n2056), .Y(n4772)
);
XOR2X4TS U7129 ( .A(n9366), .B(n1453), .Y(n9367) );
OAI22X4TS U7130 ( .A0(n5178), .A1(n1899), .B0(n5331), .B1(n4829), .Y(n5153)
);
XNOR2X4TS U7131 ( .A(n5237), .B(n1979), .Y(n4829) );
NAND2X2TS U7132 ( .A(n7820), .B(n11363), .Y(n8782) );
OAI22X2TS U7133 ( .A0(n8015), .A1(n3665), .B0(n2157), .B1(n3664), .Y(n3739)
);
OAI21X4TS U7134 ( .A0(n3278), .A1(n8372), .B0(n3054), .Y(n2663) );
OAI22X4TS U7135 ( .A0(n4361), .A1(n1986), .B0(n4088), .B1(n1823), .Y(n4376)
);
XNOR2X4TS U7136 ( .A(n1037), .B(n2058), .Y(n3929) );
OAI22X4TS U7137 ( .A0(n1980), .A1(n3664), .B0(n2157), .B1(n3963), .Y(n3971)
);
XNOR2X2TS U7138 ( .A(n1882), .B(n2503), .Y(n3424) );
XNOR2X2TS U7139 ( .A(n1565), .B(n8552), .Y(n6599) );
XNOR2X4TS U7140 ( .A(n8550), .B(n8896), .Y(n4341) );
NOR2X8TS U7141 ( .A(n2276), .B(n2670), .Y(n3275) );
XNOR2X4TS U7142 ( .A(n2277), .B(n8428), .Y(Sgf_operation_ODD1_Q_left[44]) );
OAI22X4TS U7143 ( .A0(n3880), .A1(n6075), .B0(n6070), .B1(n1226), .Y(n6073)
);
XNOR2X4TS U7144 ( .A(n2238), .B(n1927), .Y(n5785) );
OAI21X4TS U7145 ( .A0(n8391), .A1(n7533), .B0(n7532), .Y(n7534) );
OAI22X2TS U7146 ( .A0(n2105), .A1(n5955), .B0(n1919), .B1(n5792), .Y(n5951)
);
OAI2BB1X4TS U7147 ( .A0N(n4660), .A1N(n4659), .B0(n2279), .Y(n8196) );
OAI22X2TS U7148 ( .A0(n730), .A1(n7447), .B0(n1916), .B1(n7472), .Y(n7468)
);
INVX2TS U7149 ( .A(n7596), .Y(n7201) );
ADDFHX2TS U7150 ( .A(n2503), .B(n743), .CI(n7129), .CO(n7200), .S(n7130) );
XNOR2X4TS U7151 ( .A(n1812), .B(n1669), .Y(n6164) );
OAI22X2TS U7152 ( .A0(n6565), .A1(n2109), .B0(n6530), .B1(n1955), .Y(n6548)
);
NOR2X2TS U7153 ( .A(n4811), .B(n1907), .Y(n8954) );
ADDFHX2TS U7154 ( .A(n1850), .B(n1686), .CI(n3420), .CO(n3436), .S(n3484) );
ADDFHX4TS U7155 ( .A(n5412), .B(n5411), .CI(n5410), .CO(n5430), .S(n5445) );
XNOR2X4TS U7156 ( .A(n1909), .B(n1927), .Y(n6535) );
XOR2X4TS U7157 ( .A(n8040), .B(n8041), .Y(n2355) );
XOR2X4TS U7158 ( .A(n2553), .B(n6644), .Y(n6954) );
XNOR2X2TS U7159 ( .A(n2570), .B(n2057), .Y(n7379) );
OAI22X4TS U7160 ( .A0(n2077), .A1(n1850), .B0(n7489), .B1(n3451), .Y(n3480)
);
ADDFHX4TS U7161 ( .A(n4222), .B(n4223), .CI(n4221), .CO(n4237), .S(n5376) );
OAI22X4TS U7162 ( .A0(n4367), .A1(n2259), .B0(n4366), .B1(n8581), .Y(n9778)
);
OAI22X4TS U7163 ( .A0(n1969), .A1(n2949), .B0(n4343), .B1(n8629), .Y(n9787)
);
XOR2X4TS U7164 ( .A(n8627), .B(n2950), .Y(n2949) );
AND2X8TS U7165 ( .A(n5534), .B(n2282), .Y(n8467) );
OAI22X4TS U7166 ( .A0(n8933), .A1(n5490), .B0(n5491), .B1(n4684), .Y(n2282)
);
XNOR2X4TS U7167 ( .A(n1861), .B(DP_OP_168J26_122_4811_n8473), .Y(n5168) );
BUFX6TS U7168 ( .A(n6636), .Y(n2283) );
ADDFHX4TS U7169 ( .A(n6654), .B(n6652), .CI(n6653), .CO(n6625), .S(n6697) );
BUFX3TS U7170 ( .A(n6610), .Y(n2284) );
ADDFHX4TS U7171 ( .A(n6051), .B(n6050), .CI(n6049), .CO(n6204), .S(n6063) );
OAI2BB1X4TS U7172 ( .A0N(n3966), .A1N(n3965), .B0(n2285), .Y(n4752) );
OAI21X4TS U7173 ( .A0(n3966), .A1(n3965), .B0(n3964), .Y(n2285) );
XOR2X4TS U7174 ( .A(n2286), .B(n1683), .Y(n3764) );
OAI22X2TS U7175 ( .A0(n2110), .A1(n5178), .B0(n1898), .B1(n5177), .Y(n5186)
);
XNOR2X4TS U7176 ( .A(n7270), .B(n5235), .Y(n4539) );
OAI22X4TS U7177 ( .A0(n5271), .A1(n2024), .B0(n5325), .B1(n5326), .Y(n5299)
);
XNOR2X2TS U7178 ( .A(n2068), .B(n7279), .Y(n5234) );
BUFX6TS U7179 ( .A(n9918), .Y(n2289) );
OAI22X4TS U7180 ( .A0(n4825), .A1(n8015), .B0(n2157), .B1(n5141), .Y(n5183)
);
NAND2X4TS U7181 ( .A(n9902), .B(n2755), .Y(n2304) );
BUFX20TS U7182 ( .A(n3591), .Y(n2363) );
AOI2BB2X4TS U7183 ( .B0(n10803), .B1(n492), .A0N(n10860), .A1N(n11870), .Y(
n12375) );
AOI2BB2X4TS U7184 ( .B0(n10803), .B1(n494), .A0N(n2007), .A1N(n11839), .Y(
n12368) );
AOI2BB2X4TS U7185 ( .B0(n10803), .B1(n495), .A0N(n10860), .A1N(n11838), .Y(
n12365) );
AOI2BB2X4TS U7186 ( .B0(n10803), .B1(n493), .A0N(n2007), .A1N(n11840), .Y(
n12371) );
ADDFHX2TS U7187 ( .A(n4400), .B(n4399), .CI(n4401), .CO(n9913), .S(n3932) );
OAI22X4TS U7188 ( .A0(n1086), .A1(n3421), .B0(n974), .B1(
DP_OP_168J26_122_4811_n8003), .Y(n3447) );
ADDFHX4TS U7189 ( .A(n5247), .B(n5246), .CI(n5245), .CO(n5351), .S(n5289) );
XNOR2X4TS U7190 ( .A(n1831), .B(DP_OP_168J26_122_4811_n6559), .Y(n5279) );
NAND2X2TS U7191 ( .A(n9535), .B(n9529), .Y(n9538) );
XNOR2X4TS U7192 ( .A(n2465), .B(n1966), .Y(n4513) );
OAI22X4TS U7193 ( .A0(n4974), .A1(n1899), .B0(n5055), .B1(n2111), .Y(n5076)
);
XOR2X4TS U7194 ( .A(n2390), .B(n2483), .Y(n5055) );
OAI21X4TS U7195 ( .A0(n2072), .A1(n7630), .B0(n7629), .Y(n7632) );
AOI2BB1X4TS U7196 ( .A0N(DP_OP_168J26_122_4811_n8535), .A1N(n1682), .B0(
n11584), .Y(n3260) );
OAI22X2TS U7197 ( .A0(n2577), .A1(n6432), .B0(n6434), .B1(n6433), .Y(n6557)
);
XNOR2X4TS U7198 ( .A(n8443), .B(n2283), .Y(n6473) );
XNOR2X4TS U7199 ( .A(n2557), .B(n2294), .Y(n9939) );
XNOR2X4TS U7200 ( .A(n1715), .B(DP_OP_168J26_122_4811_n6794), .Y(n3481) );
XNOR2X4TS U7201 ( .A(n1220), .B(n1669), .Y(n3398) );
OAI21X4TS U7202 ( .A0(n9274), .A1(n9275), .B0(n9273), .Y(n2295) );
NOR2BX2TS U7203 ( .AN(n2448), .B(n5677), .Y(n5613) );
INVX12TS U7204 ( .A(n2856), .Y(n3127) );
BUFX6TS U7205 ( .A(n5503), .Y(n2296) );
AO21X2TS U7206 ( .A0(n1980), .A1(n2568), .B0(n866), .Y(n7091) );
OAI22X4TS U7207 ( .A0(n1516), .A1(n5327), .B0(n1958), .B1(n2927), .Y(n5379)
);
XOR2X4TS U7208 ( .A(n2297), .B(n6677), .Y(n6679) );
XOR2X4TS U7209 ( .A(n6675), .B(n6676), .Y(n2297) );
OAI22X4TS U7210 ( .A0(n1806), .A1(n3853), .B0(n3818), .B1(n8009), .Y(n4017)
);
XNOR2X2TS U7211 ( .A(n1019), .B(n8508), .Y(n8509) );
XNOR2X4TS U7212 ( .A(n2455), .B(n2591), .Y(n4823) );
OAI22X2TS U7213 ( .A0(n8517), .A1(n1908), .B0(n4364), .B1(n1862), .Y(n8525)
);
XOR2X4TS U7214 ( .A(n2632), .B(n8087), .Y(n4363) );
OAI22X2TS U7215 ( .A0(n8573), .A1(n1982), .B0(n4263), .B1(n1945), .Y(n9834)
);
XOR2X4TS U7216 ( .A(n3245), .B(n2831), .Y(n3242) );
ADDFHX4TS U7217 ( .A(n8678), .B(n8676), .CI(n8677), .CO(n9854), .S(n8679) );
OAI22X2TS U7218 ( .A0(n8585), .A1(n2055), .B0(n8584), .B1(n8583), .Y(n8632)
);
XNOR2X4TS U7219 ( .A(n2303), .B(n948), .Y(n2302) );
XOR2X4TS U7220 ( .A(n2306), .B(n2885), .Y(n9868) );
OAI21X4TS U7221 ( .A0(n2755), .A1(n9902), .B0(n9901), .Y(n2305) );
XOR2X4TS U7222 ( .A(n9886), .B(n9887), .Y(n2306) );
OAI22X4TS U7223 ( .A0(n1910), .A1(n3526), .B0(n838), .B1(n3487), .Y(n3541)
);
XOR2X4TS U7224 ( .A(n2652), .B(n5369), .Y(n5412) );
ADDFHX2TS U7225 ( .A(n8560), .B(n8562), .CI(n8561), .CO(n8609), .S(n8606) );
NOR2BX2TS U7226 ( .AN(n1809), .B(n1991), .Y(n4987) );
XNOR2X4TS U7227 ( .A(n2338), .B(n8626), .Y(n6466) );
OA21X4TS U7228 ( .A0(n9287), .A1(n9285), .B0(n9288), .Y(n2313) );
ADDFHX4TS U7229 ( .A(n4111), .B(n4112), .CI(n4110), .CO(n4152), .S(n4182) );
OAI21X4TS U7230 ( .A0(n3621), .A1(DP_OP_168J26_122_4811_n3497), .B0(
DP_OP_168J26_122_4811_n3498), .Y(n4074) );
XNOR2X4TS U7231 ( .A(n8807), .B(n1166), .Y(n2309) );
AOI21X4TS U7232 ( .A0(n7913), .A1(n7909), .B0(n7912), .Y(n7914) );
OAI22X2TS U7233 ( .A0(n8951), .A1(n1886), .B0(n8949), .B1(n2053), .Y(n9000)
);
OAI22X2TS U7234 ( .A0(n8939), .A1(n2293), .B0(n8937), .B1(n1893), .Y(n8993)
);
NAND2X2TS U7235 ( .A(n2086), .B(n10920), .Y(n8802) );
NAND2X6TS U7236 ( .A(n2812), .B(n8656), .Y(n2811) );
ADDFHX2TS U7237 ( .A(n6898), .B(n6897), .CI(n6896), .CO(n6930), .S(n6925) );
OAI22X2TS U7238 ( .A0(n4366), .A1(n2259), .B0(n4260), .B1(n2056), .Y(n4318)
);
XNOR2X2TS U7239 ( .A(n6884), .B(n6775), .Y(n6776) );
XNOR2X4TS U7240 ( .A(n3616), .B(n3611), .Y(n3615) );
OR2X8TS U7241 ( .A(n6655), .B(n1010), .Y(n10235) );
OAI22X4TS U7242 ( .A0(n5537), .A1(n8948), .B0(n8950), .B1(n5536), .Y(n5547)
);
XNOR2X2TS U7243 ( .A(n8620), .B(n2033), .Y(n5896) );
XNOR2X4TS U7244 ( .A(n8889), .B(n2034), .Y(n5832) );
OAI21X2TS U7245 ( .A0(n10960), .A1(n10959), .B0(n10958), .Y(n10961) );
XNOR2X4TS U7246 ( .A(n2310), .B(n4232), .Y(n5402) );
XNOR2X4TS U7247 ( .A(n2311), .B(n8116), .Y(n8130) );
XOR2X4TS U7248 ( .A(n3138), .B(n3139), .Y(n2311) );
NOR2X2TS U7249 ( .A(n10822), .B(n9359), .Y(n10953) );
OAI2BB1X4TS U7250 ( .A0N(n5474), .A1N(n2179), .B0(n2313), .Y(n2670) );
XNOR2X4TS U7251 ( .A(n2022), .B(n8513), .Y(n5782) );
XNOR2X2TS U7252 ( .A(n8898), .B(n2034), .Y(n8644) );
OAI22X4TS U7253 ( .A0(n2399), .A1(n743), .B0(n7489), .B1(n7349), .Y(n7100)
);
INVX6TS U7254 ( .A(n6578), .Y(n6629) );
XOR2X4TS U7255 ( .A(n2314), .B(n5111), .Y(n5122) );
XNOR2X4TS U7256 ( .A(n3097), .B(n5112), .Y(n2314) );
XOR2X4TS U7257 ( .A(n2315), .B(n8587), .Y(n9822) );
BUFX20TS U7258 ( .A(n1516), .Y(n2447) );
XNOR2X4TS U7259 ( .A(n2316), .B(n3918), .Y(n4357) );
XOR2X4TS U7260 ( .A(n3916), .B(n3919), .Y(n2316) );
ADDFHX4TS U7261 ( .A(n5069), .B(n5068), .CI(n5067), .CO(n6746), .S(n6741) );
OAI22X2TS U7262 ( .A0(n8446), .A1(n2109), .B0(n8644), .B1(n1962), .Y(n8640)
);
AOI21X4TS U7263 ( .A0(n9654), .A1(n9568), .B0(n2317), .Y(n9569) );
BUFX20TS U7264 ( .A(n8620), .Y(n2348) );
AOI21X4TS U7265 ( .A0(n9154), .A1(n7714), .B0(n7713), .Y(n8738) );
OAI22X4TS U7266 ( .A0(n1084), .A1(n3472), .B0(n973), .B1(n3415), .Y(n3463)
);
OAI21X1TS U7267 ( .A0(n10960), .A1(n10797), .B0(n10796), .Y(n10798) );
ADDFHX4TS U7268 ( .A(n4340), .B(n4339), .CI(n4338), .CO(n4418), .S(n9807) );
ADDFHX4TS U7269 ( .A(n3546), .B(n3547), .CI(n3548), .CO(n3553), .S(n3887) );
ADDFHX4TS U7270 ( .A(n4163), .B(n4162), .CI(n4161), .CO(n4270), .S(n4267) );
ADDFHX4TS U7271 ( .A(n6383), .B(n4326), .CI(n4325), .CO(n4416), .S(n4419) );
ADDFHX2TS U7272 ( .A(n11780), .B(n4133), .CI(n4132), .CO(n4151), .S(n4148)
);
ADDFHX4TS U7273 ( .A(n6314), .B(n6313), .CI(n6312), .CO(n4207), .S(n6341) );
OAI21X4TS U7274 ( .A0(n8223), .A1(n8222), .B0(n3181), .Y(n2324) );
INVX6TS U7275 ( .A(n5476), .Y(n9931) );
OAI2BB1X4TS U7276 ( .A0N(n2502), .A1N(n5476), .B0(n9930), .Y(n2500) );
ADDFHX2TS U7277 ( .A(n8525), .B(n8524), .CI(n8526), .CO(n9839), .S(n9815) );
XOR2X4TS U7278 ( .A(n2330), .B(n6540), .Y(n6721) );
XNOR2X4TS U7279 ( .A(n6405), .B(n6541), .Y(n2330) );
OAI22X2TS U7280 ( .A0(n6409), .A1(n8907), .B0(n6417), .B1(n2504), .Y(n6410)
);
OAI22X4TS U7281 ( .A0(n2870), .A1(n1899), .B0(n5331), .B1(n4042), .Y(n4046)
);
INVX4TS U7282 ( .A(n6887), .Y(n6909) );
OAI22X2TS U7283 ( .A0(n1857), .A1(n11736), .B0(DP_OP_168J26_122_4811_n6608),
.B1(n883), .Y(n3701) );
ADDFHX4TS U7284 ( .A(n4243), .B(n4241), .CI(n4242), .CO(n4235), .S(n5400) );
OAI22X4TS U7285 ( .A0(n2339), .A1(n4096), .B0(n7031), .B1(n9755), .Y(n4348)
);
OAI2BB1X4TS U7286 ( .A0N(n1930), .A1N(n1302), .B0(n2359), .Y(n2333) );
OAI22X2TS U7287 ( .A0(n5802), .A1(n2103), .B0(n1948), .B1(n5758), .Y(n5807)
);
OAI21X4TS U7288 ( .A0(n3637), .A1(n3758), .B0(n2633), .Y(n3632) );
XOR2X2TS U7289 ( .A(n2482), .B(n4561), .Y(n4623) );
XNOR2X4TS U7290 ( .A(n2376), .B(n1905), .Y(n3760) );
OAI22X2TS U7291 ( .A0(n6657), .A1(n2108), .B0(n6631), .B1(n1955), .Y(n6673)
);
XNOR2X4TS U7292 ( .A(n1565), .B(n2283), .Y(n6450) );
ADDFHX4TS U7293 ( .A(n1285), .B(n7072), .CI(n7071), .CO(n7108), .S(n7077) );
OAI21X4TS U7294 ( .A0(n5984), .A1(n2925), .B0(n2924), .Y(n8262) );
NAND2BX2TS U7295 ( .AN(n6633), .B(n8533), .Y(n5489) );
OAI2BB1X4TS U7296 ( .A0N(n7352), .A1N(n7351), .B0(n2335), .Y(n7606) );
OAI21X2TS U7297 ( .A0(n7351), .A1(n7352), .B0(n7350), .Y(n2335) );
XNOR2X4TS U7298 ( .A(n7351), .B(n2336), .Y(n7597) );
XOR2X4TS U7299 ( .A(n7352), .B(n2337), .Y(n2336) );
ADDFHX4TS U7300 ( .A(n9005), .B(n9007), .CI(n9006), .CO(n8990), .S(n9079) );
XNOR2X2TS U7301 ( .A(n1812), .B(n916), .Y(n6022) );
XNOR2X2TS U7302 ( .A(n2017), .B(n1882), .Y(n3448) );
OAI2BB1X4TS U7303 ( .A0N(n5688), .A1N(n5687), .B0(n2547), .Y(n5874) );
OAI22X2TS U7304 ( .A0(n8099), .A1(n2545), .B0(n8089), .B1(n8948), .Y(n8072)
);
OAI22X4TS U7305 ( .A0(n7492), .A1(n4135), .B0(n3307), .B1(n4134), .Y(n4169)
);
OAI22X4TS U7306 ( .A0(n1911), .A1(n4165), .B0(n838), .B1(n4105), .Y(n4177)
);
XNOR2X4TS U7307 ( .A(n2936), .B(n1967), .Y(n8112) );
XNOR2X2TS U7308 ( .A(n886), .B(n2283), .Y(n5692) );
OAI22X4TS U7309 ( .A0(n5306), .A1(n4041), .B0(n3828), .B1(n5304), .Y(n4045)
);
XNOR2X4TS U7310 ( .A(n1979), .B(n7279), .Y(n5178) );
OAI22X2TS U7311 ( .A0(n8565), .A1(n1893), .B0(n8564), .B1(n2067), .Y(n9785)
);
ADDFHX2TS U7312 ( .A(n6126), .B(n6127), .CI(n6125), .CO(n6117), .S(n6128) );
OAI22X4TS U7313 ( .A0(n2222), .A1(n4668), .B0(n8009), .B1(n8010), .Y(n8043)
);
NAND2X2TS U7314 ( .A(n6876), .B(n6887), .Y(n9743) );
OAI22X4TS U7315 ( .A0(n2222), .A1(n5319), .B0(n2046), .B1(n4227), .Y(n5385)
);
XOR2X4TS U7316 ( .A(n3246), .B(DP_OP_168J26_122_4811_n3609), .Y(n6835) );
OAI22X2TS U7317 ( .A0(n5549), .A1(n8980), .B0(n1396), .B1(n1823), .Y(n5825)
);
OAI22X4TS U7318 ( .A0(n1083), .A1(n5674), .B0(n2080), .B1(n4194), .Y(n5873)
);
BUFX6TS U7319 ( .A(n4095), .Y(n2339) );
XOR2X4TS U7320 ( .A(n4509), .B(n4508), .Y(n2567) );
OAI22X4TS U7321 ( .A0(n1814), .A1(n7042), .B0(n2060), .B1(n976), .Y(n7044)
);
ADDFHX4TS U7322 ( .A(n5049), .B(n5048), .CI(n5047), .CO(n6757), .S(n6739) );
OAI22X2TS U7323 ( .A0(n3422), .A1(n7492), .B0(n2043), .B1(n4444), .Y(n4438)
);
INVX2TS U7324 ( .A(n7581), .Y(n7185) );
OAI22X2TS U7325 ( .A0(n1878), .A1(n7040), .B0(n786), .B1(n7038), .Y(n7047)
);
ADDFHX4TS U7326 ( .A(n5415), .B(n5413), .CI(n5414), .CO(n5444), .S(n5442) );
OAI21X4TS U7327 ( .A0(n8311), .A1(n949), .B0(n1759), .Y(n2344) );
OAI22X2TS U7328 ( .A0(n6477), .A1(n2504), .B0(n6417), .B1(n8907), .Y(n6426)
);
OAI22X2TS U7329 ( .A0(n6174), .A1(n3883), .B0(n2038), .B1(n3528), .Y(n3903)
);
OAI22X4TS U7330 ( .A0(n6165), .A1(n6223), .B0(n6222), .B1(n11754), .Y(n6206)
);
XOR2X4TS U7331 ( .A(n2345), .B(n7092), .Y(n7124) );
XNOR2X2TS U7332 ( .A(n1909), .B(n2408), .Y(n6415) );
XOR2X4TS U7333 ( .A(n2357), .B(n7063), .Y(n7264) );
BUFX6TS U7334 ( .A(n10133), .Y(n2346) );
XNOR2X2TS U7335 ( .A(n5721), .B(n1253), .Y(n5579) );
AO21X4TS U7336 ( .A0(n8643), .A1(n8641), .B0(n1871), .Y(n4303) );
OAI21X4TS U7337 ( .A0(DP_OP_168J26_122_4811_n8543), .A1(
DP_OP_168J26_122_4811_n8516), .B0(n1690), .Y(n3613) );
AOI21X4TS U7338 ( .A0(n8760), .A1(n8759), .B0(n8758), .Y(n8761) );
OAI21X4TS U7339 ( .A0(n4236), .A1(n4237), .B0(n4238), .Y(n2649) );
OAI22X4TS U7340 ( .A0(n3536), .A1(n6003), .B0(n973), .B1(n3501), .Y(n3547)
);
XNOR2X4TS U7341 ( .A(n2473), .B(n8887), .Y(n4316) );
OAI22X4TS U7342 ( .A0(n4316), .A1(n2052), .B0(n4363), .B1(n8977), .Y(n4102)
);
OAI22X2TS U7343 ( .A0(n2095), .A1(n4995), .B0(n4994), .B1(n11758), .Y(n5022)
);
OAI22X2TS U7344 ( .A0(n8890), .A1(n2545), .B0(n8111), .B1(n2053), .Y(n8924)
);
OAI22X4TS U7345 ( .A0(n1866), .A1(n4104), .B0(n2062), .B1(
DP_OP_168J26_122_4811_n8034), .Y(n4112) );
XNOR2X2TS U7346 ( .A(n2483), .B(DP_OP_168J26_122_4811_n8484), .Y(n4839) );
OAI22X2TS U7347 ( .A0(n2855), .A1(n1865), .B0(n5338), .B1(n2106), .Y(n5396)
);
XNOR2X4TS U7348 ( .A(n932), .B(n945), .Y(n3804) );
ADDFHX4TS U7349 ( .A(n8045), .B(n8047), .CI(n8046), .CO(n8052), .S(n8127) );
ADDFHX4TS U7350 ( .A(n7218), .B(n7219), .CI(n7217), .CO(n7342), .S(n7221) );
OAI21X4TS U7351 ( .A0(n2352), .A1(n1415), .B0(DP_OP_168J26_122_4811_n3258),
.Y(n3915) );
NOR2X8TS U7352 ( .A(DP_OP_168J26_122_4811_n8539), .B(n1333), .Y(n2352) );
OAI2BB1X4TS U7353 ( .A0N(n8041), .A1N(n8040), .B0(n2354), .Y(n8034) );
OAI21X4TS U7354 ( .A0(n8041), .A1(n8040), .B0(n8039), .Y(n2354) );
XOR2X4TS U7355 ( .A(n2355), .B(n8039), .Y(n8144) );
OAI22X2TS U7356 ( .A0(n2088), .A1(n5234), .B0(n1925), .B1(n5284), .Y(n5282)
);
XNOR2X4TS U7357 ( .A(n1492), .B(n2058), .Y(n8888) );
OAI22X2TS U7358 ( .A0(n5331), .A1(n4974), .B0(n5058), .B1(n4973), .Y(n5004)
);
CMPR22X2TS U7359 ( .A(n4138), .B(n4137), .CO(n4167), .S(n4197) );
XOR2X4TS U7360 ( .A(n7065), .B(n7064), .Y(n2357) );
OAI2BB1X4TS U7361 ( .A0N(n8071), .A1N(n3119), .B0(n2360), .Y(n8164) );
OAI21X4TS U7362 ( .A0(n3119), .A1(n8071), .B0(n8070), .Y(n2360) );
ADDHX4TS U7363 ( .A(n6764), .B(n6763), .CO(n6771), .S(n6787) );
ADDFX2TS U7364 ( .A(n4694), .B(n4695), .CI(n4693), .CO(n4707), .S(n4691) );
OAI22X4TS U7365 ( .A0(n8907), .A1(n6561), .B0(n2504), .B1(n6560), .Y(n6641)
);
OAI22X2TS U7366 ( .A0(n7023), .A1(n2568), .B0(n1981), .B1(n7052), .Y(n7056)
);
XNOR2X4TS U7367 ( .A(n2093), .B(n2409), .Y(n4581) );
XOR2X4TS U7368 ( .A(n2373), .B(n3510), .Y(n3873) );
XOR2X4TS U7369 ( .A(n5256), .B(n883), .Y(n4859) );
XOR2X4TS U7370 ( .A(n2984), .B(n6688), .Y(n2983) );
AOI21X4TS U7371 ( .A0(n9696), .A1(n9695), .B0(n6088), .Y(n10280) );
NAND2X8TS U7372 ( .A(n2589), .B(n3559), .Y(n2361) );
NAND2X8TS U7373 ( .A(n4095), .B(n3775), .Y(n2362) );
ADDFHX4TS U7374 ( .A(n5080), .B(n5079), .CI(n5078), .CO(n5085), .S(n5087) );
ADDFHX4TS U7375 ( .A(n5066), .B(n5065), .CI(n5064), .CO(n6772), .S(n6743) );
OAI22X4TS U7376 ( .A0(n6087), .A1(n4164), .B0(n4136), .B1(n1939), .Y(n4168)
);
XNOR2X4TS U7377 ( .A(n8443), .B(n1926), .Y(n8582) );
OAI22X2TS U7378 ( .A0(n8976), .A1(n1965), .B0(n8888), .B1(n1862), .Y(n8957)
);
OAI22X2TS U7379 ( .A0(n2110), .A1(n4973), .B0(n1899), .B1(n4991), .Y(n4989)
);
OAI22X4TS U7380 ( .A0(n1915), .A1(n4174), .B0(n4141), .B1(n782), .Y(n4180)
);
OAI2BB1X4TS U7381 ( .A0N(n3810), .A1N(n3809), .B0(n2365), .Y(n3868) );
OAI21X4TS U7382 ( .A0(n3809), .A1(n3810), .B0(n3808), .Y(n2365) );
XOR2X4TS U7383 ( .A(n3809), .B(n3810), .Y(n2366) );
INVX12TS U7384 ( .A(n3232), .Y(n8921) );
INVX4TS U7385 ( .A(n8110), .Y(n8925) );
XOR2X4TS U7386 ( .A(n2374), .B(n8311), .Y(n8320) );
XOR2X4TS U7387 ( .A(n8312), .B(n8313), .Y(n2374) );
XNOR2X4TS U7388 ( .A(n7270), .B(n878), .Y(n3818) );
OAI2BB1X4TS U7389 ( .A0N(n9030), .A1N(n9031), .B0(n3117), .Y(n9979) );
XOR2X4TS U7390 ( .A(n2940), .B(n8136), .Y(n9030) );
INVX2TS U7391 ( .A(n9657), .Y(n7400) );
BUFX20TS U7392 ( .A(n1881), .Y(n2445) );
OAI22X2TS U7393 ( .A0(n2105), .A1(n3424), .B0(n1921), .B1(n3448), .Y(n3445)
);
OAI22X2TS U7394 ( .A0(n5632), .A1(n2293), .B0(n5631), .B1(n1940), .Y(n5844)
);
NAND2X2TS U7395 ( .A(n7813), .B(n11377), .Y(n10750) );
ADDFHX2TS U7396 ( .A(n6947), .B(n6946), .CI(n6945), .CO(n6976), .S(n6971) );
XNOR2X2TS U7397 ( .A(n1028), .B(n1954), .Y(n6920) );
OAI22X2TS U7398 ( .A0(n8572), .A1(n2575), .B0(n8549), .B1(n2112), .Y(n8675)
);
INVX2TS U7399 ( .A(n6742), .Y(n6753) );
NOR2BX2TS U7400 ( .AN(n1019), .B(n1907), .Y(n8943) );
NOR2X2TS U7401 ( .A(n7679), .B(n7683), .Y(n7671) );
BUFX20TS U7402 ( .A(DP_OP_168J26_122_4811_n6579), .Y(n4982) );
INVX2TS U7403 ( .A(n7606), .Y(n7367) );
XOR2X4TS U7404 ( .A(n2378), .B(n4924), .Y(n4926) );
XOR2X4TS U7405 ( .A(n4923), .B(n4925), .Y(n2378) );
OAI22X2TS U7406 ( .A0(n6416), .A1(n8938), .B0(n5944), .B1(n1940), .Y(n6418)
);
XNOR2X4TS U7407 ( .A(n3052), .B(n3050), .Y(n3252) );
XNOR2X4TS U7408 ( .A(n8511), .B(n1255), .Y(n4359) );
OAI22X2TS U7409 ( .A0(n2029), .A1(n6076), .B0(n6086), .B1(n6071), .Y(n6072)
);
OAI22X2TS U7410 ( .A0(n1820), .A1(n4555), .B0(n1900), .B1(n4554), .Y(n4577)
);
XNOR2X2TS U7411 ( .A(n1882), .B(n7488), .Y(n4185) );
ADDFHX4TS U7412 ( .A(n4172), .B(n4171), .CI(n4170), .CO(n4131), .S(n6309) );
XOR2X4TS U7413 ( .A(n8550), .B(n6561), .Y(n8571) );
ADDFHX2TS U7414 ( .A(n9799), .B(n9798), .CI(n9797), .CO(n9863), .S(n9819) );
XNOR2X4TS U7415 ( .A(n2381), .B(n9768), .Y(n2534) );
XOR2X4TS U7416 ( .A(n2751), .B(n9769), .Y(n2381) );
OAI22X2TS U7417 ( .A0(n4256), .A1(n2112), .B0(n4005), .B1(n2575), .Y(n4308)
);
XOR2X4TS U7418 ( .A(n2384), .B(n1764), .Y(n8749) );
XOR2X4TS U7419 ( .A(n8281), .B(n8283), .Y(n2384) );
ADDFHX2TS U7420 ( .A(n9913), .B(n9912), .CI(n9911), .CO(n10016), .S(n10013)
);
XNOR2X2TS U7421 ( .A(n8511), .B(n2453), .Y(n3790) );
NAND2X8TS U7422 ( .A(n11762), .B(n1390), .Y(DP_OP_168J26_122_4811_n572) );
XNOR2X4TS U7423 ( .A(n2380), .B(n6145), .Y(n6172) );
CLKBUFX2TS U7424 ( .A(n2920), .Y(n2385) );
BUFX3TS U7425 ( .A(n8192), .Y(n2386) );
ACHCINX4TS U7426 ( .CIN(n6698), .A(n6967), .B(n6966), .CO(n6944) );
OAI22X2TS U7427 ( .A0(n3791), .A1(n9456), .B0(n3790), .B1(n2331), .Y(n3947)
);
XNOR2X4TS U7428 ( .A(n1037), .B(n2033), .Y(n6423) );
OAI22X2TS U7429 ( .A0(n8015), .A1(n4540), .B0(n2157), .B1(n4545), .Y(n4544)
);
XNOR2X4TS U7430 ( .A(n3432), .B(n1850), .Y(n6056) );
ADDFHX2TS U7431 ( .A(n5597), .B(n5596), .CI(n5595), .CO(n5600), .S(n5617) );
XNOR2X4TS U7432 ( .A(n2349), .B(n2283), .Y(n6543) );
OAI22X4TS U7433 ( .A0(n3893), .A1(n6178), .B0(n3529), .B1(n6040), .Y(n3908)
);
XOR2X4TS U7434 ( .A(n2389), .B(n5432), .Y(n5437) );
XOR2X4TS U7435 ( .A(n5431), .B(n5433), .Y(n2389) );
OAI22X4TS U7436 ( .A0(n8015), .A1(n5211), .B0(n8013), .B1(n5274), .Y(n5246)
);
OAI22X2TS U7437 ( .A0(n2095), .A1(n4994), .B0(n4964), .B1(n11758), .Y(n5016)
);
XNOR2X4TS U7438 ( .A(n5276), .B(n7369), .Y(n4240) );
NAND2X4TS U7439 ( .A(n6242), .B(n6243), .Y(n2391) );
OAI21X4TS U7440 ( .A0(n6243), .A1(n6242), .B0(n6241), .Y(n2392) );
ADDFHX4TS U7441 ( .A(n3655), .B(n3656), .CI(n3657), .CO(n3952), .S(n3744) );
XOR2X4TS U7442 ( .A(n4898), .B(n2638), .Y(n2393) );
ADDFHX4TS U7443 ( .A(n4905), .B(n4904), .CI(n4906), .CO(n4925), .S(n4949) );
OAI2BB1X4TS U7444 ( .A0N(n2394), .A1N(n6541), .B0(n3210), .Y(n6568) );
OAI22X4TS U7445 ( .A0(n5309), .A1(n4231), .B0(n1989), .B1(n4026), .Y(n4243)
);
OAI22X4TS U7446 ( .A0(n2111), .A1(n5222), .B0(n1898), .B1(n5252), .Y(n5248)
);
OAI21X4TS U7447 ( .A0(n5033), .A1(n5031), .B0(n5032), .Y(n3131) );
NAND2X8TS U7448 ( .A(n6101), .B(DP_OP_168J26_122_4811_n8198), .Y(n6069) );
XOR2X4TS U7449 ( .A(n2452), .B(n8699), .Y(n9272) );
OAI22X2TS U7450 ( .A0(n5939), .A1(n2099), .B0(n5784), .B1(n2446), .Y(n5933)
);
XNOR2X4TS U7451 ( .A(n7449), .B(n1805), .Y(n5593) );
OAI22X4TS U7452 ( .A0(n5306), .A1(n5148), .B0(n5304), .B1(n5169), .Y(n5151)
);
OAI22X2TS U7453 ( .A0(n8514), .A1(n1987), .B0(n8532), .B1(n1823), .Y(n8660)
);
ADDHX4TS U7454 ( .A(n6458), .B(n6457), .CO(n5941), .S(n6471) );
NAND2X2TS U7455 ( .A(n10208), .B(n10210), .Y(n6237) );
NOR2X8TS U7456 ( .A(n6863), .B(n6862), .Y(n3168) );
OAI21X4TS U7457 ( .A0(n6729), .A1(n6730), .B0(n6728), .Y(n2396) );
AOI2BB2X4TS U7458 ( .B0(n10871), .B1(n496), .A0N(n10760), .A1N(n11837), .Y(
n12362) );
OAI22X2TS U7459 ( .A0(n2102), .A1(n6008), .B0(n6176), .B1(n6007), .Y(n6010)
);
XNOR2X4TS U7460 ( .A(n2455), .B(n1884), .Y(n5305) );
XNOR2X2TS U7461 ( .A(n1019), .B(n1972), .Y(n4813) );
NAND2X4TS U7462 ( .A(n7724), .B(n1132), .Y(n8729) );
CLKINVX12TS U7463 ( .A(n11487), .Y(n6079) );
ADDFHX4TS U7464 ( .A(n3433), .B(n3434), .CI(n3435), .CO(n3441), .S(n3477) );
OAI22X2TS U7465 ( .A0(n1806), .A1(n7215), .B0(n2046), .B1(n1838), .Y(n7357)
);
XOR2X4TS U7466 ( .A(n9016), .B(n9015), .Y(n2398) );
OAI22X4TS U7467 ( .A0(n5318), .A1(n3793), .B0(n979), .B1(n3713), .Y(n3824)
);
OAI22X2TS U7468 ( .A0(n4360), .A1(n8583), .B0(n4092), .B1(n8948), .Y(n4103)
);
NOR2BX2TS U7469 ( .AN(n6884), .B(n9456), .Y(n8469) );
NAND2X4TS U7470 ( .A(n3917), .B(n3313), .Y(n3918) );
ADDFHX2TS U7471 ( .A(n5315), .B(n5314), .CI(n5313), .CO(n5421), .S(n5294) );
XOR2X4TS U7472 ( .A(n4014), .B(n4015), .Y(n2400) );
ADDFHX2TS U7473 ( .A(n4770), .B(n4769), .CI(n4768), .CO(n9116), .S(n4766) );
AOI21X4TS U7474 ( .A0(n10154), .A1(n6291), .B0(n6290), .Y(n6292) );
OAI22X2TS U7475 ( .A0(n5622), .A1(n1815), .B0(n822), .B1(n5563), .Y(n5628)
);
OAI22X2TS U7476 ( .A0(n4637), .A1(n1965), .B0(n4704), .B1(n2052), .Y(n4688)
);
OAI22X4TS U7477 ( .A0(n2411), .A1(n7257), .B0(n1951), .B1(n7054), .Y(n7061)
);
XOR2X2TS U7478 ( .A(n3388), .B(DP_OP_168J26_122_4811_n3223), .Y(n3389) );
OA21X4TS U7479 ( .A0(n7651), .A1(n7837), .B0(n11774), .Y(n7652) );
OAI21X4TS U7480 ( .A0(n2072), .A1(n7653), .B0(n7652), .Y(n7655) );
ADDFHX4TS U7481 ( .A(n9767), .B(n9766), .CI(n9765), .CO(
DP_OP_168J26_122_4811_n1193), .S(n4425) );
BUFX20TS U7482 ( .A(n8894), .Y(n2465) );
BUFX20TS U7483 ( .A(n8898), .Y(n2505) );
XOR2X4TS U7484 ( .A(n2402), .B(n2988), .Y(n6683) );
XOR2X4TS U7485 ( .A(n6662), .B(n6661), .Y(n2402) );
OAI22X2TS U7486 ( .A0(n5542), .A1(n2112), .B0(n8463), .B1(n1960), .Y(n8449)
);
XNOR2X2TS U7487 ( .A(n2328), .B(n1717), .Y(n3981) );
OAI22X4TS U7488 ( .A0(n2379), .A1(n4430), .B0(n7474), .B1(n4429), .Y(n4471)
);
OAI22X2TS U7489 ( .A0(n4802), .A1(n1965), .B0(n8978), .B1(n2052), .Y(n9004)
);
OAI22X4TS U7490 ( .A0(n4106), .A1(n7473), .B0(n3879), .B1(n5677), .Y(n4117)
);
ADDFHX4TS U7491 ( .A(n4117), .B(n4116), .CI(n4118), .CO(n4150), .S(n4130) );
XOR2X4TS U7492 ( .A(n2404), .B(n4270), .Y(n4327) );
XOR2X4TS U7493 ( .A(n4271), .B(n4272), .Y(n2404) );
ADDFHX4TS U7494 ( .A(n4040), .B(n4039), .CI(n4038), .CO(n4252), .S(n5368) );
OAI2BB1X4TS U7495 ( .A0N(n2405), .A1N(n2719), .B0(n3067), .Y(n8454) );
ADDFHX4TS U7496 ( .A(n5290), .B(n5289), .CI(n5288), .CO(n5335), .S(n5293) );
BUFX20TS U7497 ( .A(n3319), .Y(n2527) );
OAI22X2TS U7498 ( .A0(n2102), .A1(n4175), .B0(n6040), .B1(n4115), .Y(n4170)
);
OAI22X2TS U7499 ( .A0(n2029), .A1(n6071), .B0(n1939), .B1(n6095), .Y(n6112)
);
INVX2TS U7500 ( .A(n10282), .Y(n6089) );
AOI21X4TS U7501 ( .A0(n10283), .A1(n10281), .B0(n6089), .Y(n6090) );
AND2X8TS U7502 ( .A(n3070), .B(n10723), .Y(n2920) );
OAI22X4TS U7503 ( .A0(n4882), .A1(n5318), .B0(n4838), .B1(n980), .Y(n4879)
);
XNOR2X2TS U7504 ( .A(n2348), .B(n2034), .Y(n8446) );
NOR2X1TS U7505 ( .A(n10591), .B(n10593), .Y(n10514) );
AOI21X4TS U7506 ( .A0(n10514), .A1(n10588), .B0(n10513), .Y(n10572) );
AOI21X4TS U7507 ( .A0(n10610), .A1(n10609), .B0(n10608), .Y(n10615) );
MXI2X2TS U7508 ( .A(n11831), .B(n1433), .S0(FSM_selector_A), .Y(n10509) );
OAI22X2TS U7509 ( .A0(n4839), .A1(n2110), .B0(n5058), .B1(n4829), .Y(n4846)
);
OAI2BB1X4TS U7510 ( .A0N(n2407), .A1N(n1738), .B0(n2792), .Y(n6503) );
XNOR2X4TS U7511 ( .A(n7439), .B(n1694), .Y(n4793) );
OAI22X4TS U7512 ( .A0(n2105), .A1(n4447), .B0(n1921), .B1(n4457), .Y(n4452)
);
ADDFHX4TS U7513 ( .A(n8929), .B(n8927), .CI(n8928), .CO(n8965), .S(n8992) );
ADDFHX2TS U7514 ( .A(n5745), .B(n5746), .CI(n5744), .CO(n5838), .S(n5820) );
XNOR2X2TS U7515 ( .A(n2020), .B(n6435), .Y(n6416) );
OAI22X2TS U7516 ( .A0(n5212), .A1(n2095), .B0(n5277), .B1(n1889), .Y(n5245)
);
OAI22X4TS U7517 ( .A0(n8579), .A1(n5500), .B0(n8945), .B1(n5499), .Y(n5777)
);
OAI22X4TS U7518 ( .A0(n4342), .A1(n1969), .B0(n4083), .B1(n1933), .Y(n4009)
);
OAI2BB1X4TS U7519 ( .A0N(n3745), .A1N(n3746), .B0(n2882), .Y(n3985) );
INVX2TS U7520 ( .A(n8652), .Y(n2601) );
XNOR2X2TS U7521 ( .A(n8511), .B(n6636), .Y(n6449) );
XNOR2X2TS U7522 ( .A(n1861), .B(n2409), .Y(n3665) );
INVX6TS U7523 ( .A(n6283), .Y(n5985) );
OAI22X2TS U7524 ( .A0(n5306), .A1(n5303), .B0(n2048), .B1(n4226), .Y(n5386)
);
OAI2BB1X4TS U7525 ( .A0N(n8497), .A1N(n8496), .B0(n2412), .Y(n8702) );
XOR2X4TS U7526 ( .A(n2413), .B(n8495), .Y(n8483) );
XOR2X4TS U7527 ( .A(n8496), .B(n8497), .Y(n2413) );
XNOR2X2TS U7528 ( .A(n2021), .B(n1926), .Y(n5492) );
INVX6TS U7529 ( .A(n8192), .Y(n9088) );
XNOR2X4TS U7530 ( .A(n2414), .B(n9896), .Y(n2515) );
XOR2X4TS U7531 ( .A(n1777), .B(n9897), .Y(n2414) );
NOR2X4TS U7532 ( .A(n7815), .B(n11359), .Y(n9552) );
OAI21X2TS U7533 ( .A0(n8332), .A1(n8326), .B0(n8333), .Y(n6390) );
AO21X2TS U7534 ( .A0(n6003), .A1(n2081), .B0(n1223), .Y(n4782) );
XOR2X4TS U7535 ( .A(n10820), .B(n990), .Y(n10821) );
XOR2X4TS U7536 ( .A(n10838), .B(n1148), .Y(n10839) );
XNOR2X4TS U7537 ( .A(n2415), .B(n3242), .Y(n9883) );
XOR2X4TS U7538 ( .A(n4420), .B(n4421), .Y(n2415) );
ADDFHX2TS U7539 ( .A(n8954), .B(n8953), .CI(n8952), .CO(n8999), .S(n9082) );
OAI22X4TS U7540 ( .A0(n1911), .A1(n4105), .B0(n1364), .B1(n3894), .Y(n4108)
);
OAI22X2TS U7541 ( .A0(n4579), .A1(n1990), .B0(n1934), .B1(n4553), .Y(n4578)
);
CMPR22X2TS U7542 ( .A(n6183), .B(n6184), .CO(n6212), .S(n6193) );
ADDFHX4TS U7543 ( .A(n5887), .B(n5888), .CI(n5886), .CO(n6318), .S(n6315) );
AO22X4TS U7544 ( .A0(n4232), .A1(n2416), .B0(n4233), .B1(n2417), .Y(n4236)
);
NOR2X8TS U7545 ( .A(n7429), .B(n6941), .Y(n2630) );
OAI2BB1X4TS U7546 ( .A0N(n4954), .A1N(n4953), .B0(n2419), .Y(n4947) );
OAI22X2TS U7547 ( .A0(n6460), .A1(n2052), .B0(n6459), .B1(n8518), .Y(n6470)
);
ADDHX4TS U7548 ( .A(n5042), .B(n5041), .CO(n6737), .S(n6781) );
OAI22X2TS U7549 ( .A0(n8472), .A1(n1908), .B0(n8509), .B1(n8516), .Y(n8665)
);
OAI22X4TS U7550 ( .A0(n3683), .A1(n2110), .B0(n1899), .B1(n1726), .Y(n3737)
);
XNOR2X4TS U7551 ( .A(n7277), .B(n2409), .Y(n3829) );
XNOR2X4TS U7552 ( .A(n2549), .B(n2283), .Y(n6472) );
OAI21X4TS U7553 ( .A0(n1005), .A1(n3703), .B0(n2801), .Y(n2701) );
OAI2BB1X4TS U7554 ( .A0N(n9907), .A1N(n9906), .B0(n2420), .Y(n9869) );
XNOR2X4TS U7555 ( .A(n2421), .B(n9905), .Y(n9908) );
NAND2X2TS U7556 ( .A(n7427), .B(n8184), .Y(n7428) );
ADDFHX4TS U7557 ( .A(n5372), .B(n5371), .CI(n5370), .CO(n5411), .S(n5413) );
OAI22X2TS U7558 ( .A0(n8476), .A1(n1945), .B0(n5633), .B1(n1983), .Y(n8459)
);
OAI2BB1X4TS U7559 ( .A0N(n5426), .A1N(n753), .B0(n2423), .Y(n5451) );
OAI21X4TS U7560 ( .A0(n5426), .A1(n753), .B0(n5425), .Y(n2423) );
INVX4TS U7561 ( .A(n4392), .Y(n2656) );
OAI21X4TS U7562 ( .A0(n9329), .A1(n9332), .B0(n9330), .Y(n8360) );
ADDFHX4TS U7563 ( .A(n8108), .B(n8107), .CI(n8106), .CO(n9975), .S(n9023) );
OAI22X4TS U7564 ( .A0(n4024), .A1(n7997), .B0(n4029), .B1(n1923), .Y(n2652)
);
XNOR2X2TS U7565 ( .A(n2093), .B(n7369), .Y(n7138) );
XOR2X4TS U7566 ( .A(n2429), .B(n5874), .Y(n5845) );
XOR2X4TS U7567 ( .A(n5876), .B(n5875), .Y(n2429) );
OAI22X4TS U7568 ( .A0(n2995), .A1(n2569), .B0(n2994), .B1(n1010), .Y(n6672)
);
OAI22X4TS U7569 ( .A0(n3458), .A1(n2073), .B0(n1897), .B1(n3431), .Y(n3466)
);
NAND2X8TS U7570 ( .A(n2829), .B(n2431), .Y(n2596) );
NOR2X4TS U7571 ( .A(n7559), .B(n8332), .Y(n6391) );
XOR2X4TS U7572 ( .A(n2432), .B(n3521), .Y(n3892) );
XOR2X4TS U7573 ( .A(n3520), .B(n3522), .Y(n2432) );
ADDFHX4TS U7574 ( .A(n5083), .B(n5082), .CI(n5081), .CO(n5073), .S(n5084) );
XOR2X4TS U7575 ( .A(n2433), .B(n3944), .Y(n3232) );
AO21X4TS U7576 ( .A0(n3880), .A1(n1227), .B0(n11528), .Y(n4116) );
OAI22X2TS U7577 ( .A0(n2103), .A1(n5860), .B0(n1948), .B1(n5859), .Y(n6302)
);
OR2X2TS U7578 ( .A(n6686), .B(n6667), .Y(n10231) );
INVX2TS U7579 ( .A(n11178), .Y(n5035) );
XNOR2X2TS U7580 ( .A(n2021), .B(n6562), .Y(n6409) );
OAI2BB1X4TS U7581 ( .A0N(n4931), .A1N(n4930), .B0(n2435), .Y(n4923) );
OAI21X4TS U7582 ( .A0(n4930), .A1(n4931), .B0(n4929), .Y(n2435) );
XOR2X4TS U7583 ( .A(n4930), .B(n2436), .Y(n4952) );
XOR2X4TS U7584 ( .A(n4929), .B(n4931), .Y(n2436) );
OAI22X4TS U7585 ( .A0(n5779), .A1(n8530), .B0(n5782), .B1(n8980), .Y(n5942)
);
OAI22X2TS U7586 ( .A0(n1910), .A1(n3894), .B0(n1364), .B1(n3526), .Y(n3896)
);
OAI22X2TS U7587 ( .A0(n5494), .A1(n2108), .B0(n8446), .B1(n1962), .Y(n8492)
);
XNOR2X4TS U7588 ( .A(n5262), .B(n5263), .Y(n3156) );
XNOR2X4TS U7589 ( .A(n8550), .B(n2034), .Y(n5815) );
OAI2BB1X2TS U7590 ( .A0N(n4736), .A1N(n1334), .B0(n2437), .Y(n9873) );
OAI21X2TS U7591 ( .A0(n4736), .A1(n1334), .B0(n4738), .Y(n2437) );
XOR2X4TS U7592 ( .A(n2438), .B(n4736), .Y(n4765) );
XOR2X4TS U7593 ( .A(n4737), .B(n4738), .Y(n2438) );
XOR2X4TS U7594 ( .A(n5366), .B(n2439), .Y(n5436) );
XOR2X4TS U7595 ( .A(n5367), .B(n5368), .Y(n2439) );
XOR2X4TS U7596 ( .A(n7908), .B(n11542), .Y(n2442) );
OAI2BB1X4TS U7597 ( .A0N(n8179), .A1N(n8178), .B0(n2443), .Y(n9486) );
OAI21X4TS U7598 ( .A0(n8178), .A1(n8179), .B0(n8177), .Y(n2443) );
XOR2X4TS U7599 ( .A(n920), .B(n2444), .Y(n10001) );
XOR2X4TS U7600 ( .A(n8178), .B(n8179), .Y(n2444) );
OAI22X2TS U7601 ( .A0(n2090), .A1(n6096), .B0(n6025), .B1(n2261), .Y(n6119)
);
NAND2X2TS U7602 ( .A(n10880), .B(n10976), .Y(n12273) );
INVX2TS U7603 ( .A(n6621), .Y(n2645) );
OAI22X4TS U7604 ( .A0(n6459), .A1(n8516), .B0(n6408), .B1(n8518), .Y(n6462)
);
XNOR2X2TS U7605 ( .A(n4003), .B(n6775), .Y(n6691) );
XNOR2X4TS U7606 ( .A(n8539), .B(n2041), .Y(n5537) );
OAI22X2TS U7607 ( .A0(n4517), .A1(n2331), .B0(n4621), .B1(n9456), .Y(n4734)
);
NAND2X4TS U7608 ( .A(n10353), .B(n10352), .Y(n10385) );
OAI22X2TS U7609 ( .A0(n6666), .A1(n1961), .B0(n6691), .B1(n2097), .Y(n6707)
);
NOR2X1TS U7610 ( .A(n9196), .B(n11419), .Y(n7706) );
OAI22X2TS U7611 ( .A0(n4723), .A1(n2055), .B0(n4515), .B1(n1886), .Y(n4510)
);
OAI22X2TS U7612 ( .A0(n5514), .A1(n2113), .B0(n5543), .B1(n2575), .Y(n5520)
);
OAI22X4TS U7613 ( .A0(n2422), .A1(n7994), .B0(n2114), .B1(n7992), .Y(n8047)
);
NOR2X8TS U7614 ( .A(n2600), .B(n1514), .Y(n7964) );
OAI22X4TS U7615 ( .A0(n6643), .A1(n1944), .B0(n6642), .B1(n8574), .Y(n6670)
);
CLKINVX6TS U7616 ( .A(n6667), .Y(n6706) );
ADDFHX4TS U7617 ( .A(n8597), .B(n8599), .CI(n8598), .CO(n9824), .S(n8696) );
XNOR2X4TS U7618 ( .A(n3361), .B(n3362), .Y(n2449) );
XNOR2X2TS U7619 ( .A(n6055), .B(n5666), .Y(n6038) );
OAI22X4TS U7620 ( .A0(n1814), .A1(n926), .B0(n2059), .B1(n5562), .Y(n5586)
);
OAI21X4TS U7621 ( .A0(n1272), .A1(n9016), .B0(n9014), .Y(n3134) );
CLKINVX12TS U7622 ( .A(n2781), .Y(n2778) );
XNOR2X2TS U7623 ( .A(n2045), .B(n2634), .Y(n3684) );
AOI2BB2X4TS U7624 ( .B0(n10861), .B1(n11057), .A0N(n10870), .A1N(n11844),
.Y(n9396) );
XNOR2X4TS U7625 ( .A(n2465), .B(n3322), .Y(n8909) );
OAI22X4TS U7626 ( .A0(n8909), .A1(n9755), .B0(n8895), .B1(n2036), .Y(n8918)
);
XNOR2X4TS U7627 ( .A(n7865), .B(n11546), .Y(n7929) );
AOI21X4TS U7628 ( .A0(n8394), .A1(n8393), .B0(n8392), .Y(n8395) );
OAI21X1TS U7629 ( .A0(n7859), .A1(n7858), .B0(n7857), .Y(n7860) );
XOR2X4TS U7630 ( .A(n8700), .B(n8701), .Y(n2452) );
AO21X2TS U7631 ( .A0(n3648), .A1(n1943), .B0(n11770), .Y(n4608) );
XNOR2X2TS U7632 ( .A(n1979), .B(n1717), .Y(n5330) );
CMPR22X2TS U7633 ( .A(n4909), .B(n4908), .CO(n4906), .S(n4936) );
XOR2X4TS U7634 ( .A(n4618), .B(n4619), .Y(n2554) );
OAI22X2TS U7635 ( .A0(n4528), .A1(n1880), .B0(n975), .B1(n3982), .Y(n4550)
);
AOI21X2TS U7636 ( .A0(n10065), .A1(n8376), .B0(n8193), .Y(n8194) );
OAI21X4TS U7637 ( .A0(n8435), .A1(n8799), .B0(n8436), .Y(n8220) );
OAI22X2TS U7638 ( .A0(n4185), .A1(n2105), .B0(n1921), .B1(n4142), .Y(n4179)
);
OAI22X2TS U7639 ( .A0(n4188), .A1(n2104), .B0(n1919), .B1(n4185), .Y(n6319)
);
ADDFHX4TS U7640 ( .A(n8901), .B(n8903), .CI(n8902), .CO(n9029), .S(n9018) );
ADDFHX2TS U7641 ( .A(n8141), .B(n8140), .CI(n8139), .CO(n8149), .S(n8914) );
OAI22X2TS U7642 ( .A0(n5898), .A1(n1969), .B0(n5897), .B1(n8629), .Y(n5907)
);
NOR2X8TS U7643 ( .A(n9407), .B(n7936), .Y(n7885) );
OAI22X4TS U7644 ( .A0(n2097), .A1(n2976), .B0(n6886), .B1(n1961), .Y(n6910)
);
OAI22X4TS U7645 ( .A0(n6559), .A1(n2504), .B0(n6564), .B1(n8907), .Y(n6608)
);
XNOR2X2TS U7646 ( .A(n8620), .B(n8896), .Y(n4692) );
NAND2X2TS U7647 ( .A(n2086), .B(n10841), .Y(n10843) );
NOR2X2TS U7648 ( .A(n10886), .B(n7920), .Y(n7921) );
ADDFHX2TS U7649 ( .A(n9757), .B(n1436), .CI(n9756), .CO(n10198), .S(n9749)
);
ADDFHX2TS U7650 ( .A(n5348), .B(n5347), .CI(n5346), .CO(n5441), .S(n5349) );
ADDFHX4TS U7651 ( .A(n9079), .B(n9080), .CI(n9078), .CO(n9093), .S(n9122) );
ADDFHX4TS U7652 ( .A(n2380), .B(n1860), .CI(n4795), .CO(n7435), .S(n4797) );
CMPR22X2TS U7653 ( .A(n4841), .B(n4842), .CO(n4870), .S(n4849) );
AOI2BB2X4TS U7654 ( .B0(n10871), .B1(n497), .A0N(n2007), .A1N(n11868), .Y(
n12359) );
NAND2BX4TS U7655 ( .AN(n1777), .B(n9897), .Y(n2886) );
XNOR2X2TS U7656 ( .A(n1890), .B(DP_OP_168J26_122_4811_n8486), .Y(n4887) );
XNOR2X4TS U7657 ( .A(n2338), .B(n1929), .Y(n5634) );
OAI21X4TS U7658 ( .A0(n11632), .A1(n11633), .B0(n11634), .Y(n7697) );
OAI21X2TS U7659 ( .A0(n9232), .A1(n9226), .B0(n9233), .Y(n7736) );
ADDFHX4TS U7660 ( .A(n5772), .B(n5771), .CI(n5770), .CO(n5790), .S(n5945) );
XNOR2X4TS U7661 ( .A(n2457), .B(n2454), .Y(n9966) );
XNOR2X4TS U7662 ( .A(n9274), .B(n9275), .Y(n2457) );
OAI22X2TS U7663 ( .A0(n4671), .A1(n8025), .B0(n1900), .B1(n8024), .Y(n8113)
);
OA21X4TS U7664 ( .A0(n7424), .A1(n3141), .B0(n10100), .Y(n3140) );
ADDFHX4TS U7665 ( .A(n8625), .B(n8624), .CI(n8623), .CO(n8680), .S(n8635) );
OAI2BB2X4TS U7666 ( .B0(n8439), .B1(n6919), .A0N(n2460), .A1N(n2459), .Y(
n8608) );
ADDFHX4TS U7667 ( .A(n9796), .B(n9795), .CI(n9794), .CO(n9864), .S(n9856) );
OAI22X4TS U7668 ( .A0(n7490), .A1(n1913), .B0(n1624), .B1(n2464), .Y(n7451)
);
XNOR2X2TS U7669 ( .A(n1881), .B(n2397), .Y(n4188) );
NOR2X8TS U7670 ( .A(n4420), .B(n4421), .Y(n3191) );
NOR2BX4TS U7671 ( .AN(n6884), .B(n6403), .Y(n6783) );
OAI2BB1X4TS U7672 ( .A0N(n10019), .A1N(n10018), .B0(n2462), .Y(n10020) );
OAI21X4TS U7673 ( .A0(n10019), .A1(n10018), .B0(n10017), .Y(n2462) );
INVX8TS U7674 ( .A(n5480), .Y(n9923) );
OAI22X4TS U7675 ( .A0(n8025), .A1(n1518), .B0(n2048), .B1(n4824), .Y(n4841)
);
XNOR2X4TS U7676 ( .A(n2501), .B(n9931), .Y(n10042) );
NOR2X8TS U7677 ( .A(n7868), .B(n7874), .Y(n7910) );
XNOR2X4TS U7678 ( .A(n2632), .B(n1966), .Y(n4686) );
ADDFHX4TS U7679 ( .A(n6574), .B(n6573), .CI(n2770), .CO(n6731), .S(n6730) );
XNOR2X2TS U7680 ( .A(n4003), .B(n8539), .Y(n5535) );
CLKINVX6TS U7681 ( .A(n9998), .Y(DP_OP_168J26_122_4811_n318) );
OAI22X4TS U7682 ( .A0(n5560), .A1(n1914), .B0(n3321), .B1(n5559), .Y(n5587)
);
OAI22X2TS U7683 ( .A0(n6558), .A1(n2504), .B0(n6559), .B1(n8907), .Y(n6589)
);
XNOR2X4TS U7684 ( .A(n11581), .B(n2527), .Y(n4043) );
NAND2BX2TS U7685 ( .AN(n2591), .B(n2406), .Y(n4983) );
XNOR2X4TS U7686 ( .A(n5960), .B(n7439), .Y(n3396) );
OAI22X4TS U7687 ( .A0(n3046), .A1(n1516), .B0(n5057), .B1(n1901), .Y(n5061)
);
NAND2X2TS U7688 ( .A(n1394), .B(n3561), .Y(n3562) );
XNOR2X4TS U7689 ( .A(n1909), .B(n1255), .Y(n8442) );
ADDFHX2TS U7690 ( .A(n4577), .B(n4576), .CI(n4578), .CO(n4600), .S(n4571) );
OAI22X2TS U7691 ( .A0(n1934), .A1(n4579), .B0(n5325), .B1(n4596), .Y(n4613)
);
OAI22X4TS U7692 ( .A0(n1815), .A1(n5765), .B0(n5623), .B1(n3307), .Y(n5724)
);
OAI22X2TS U7693 ( .A0(n6657), .A1(n1955), .B0(n6700), .B1(n2109), .Y(n6701)
);
OAI22X2TS U7694 ( .A0(n3684), .A1(n2115), .B0(n1964), .B1(n2915), .Y(n3735)
);
OAI22X4TS U7695 ( .A0(n1964), .A1(n4228), .B0(n2115), .B1(n4019), .Y(n4222)
);
ADDFHX4TS U7696 ( .A(n4903), .B(n4902), .CI(n4901), .CO(n4896), .S(n4928) );
XNOR2X4TS U7697 ( .A(n2020), .B(n2453), .Y(n4258) );
ADDFHX2TS U7698 ( .A(n4212), .B(n4213), .CI(n4214), .CO(n4101), .S(n9788) );
OAI22X4TS U7699 ( .A0(n3404), .A1(n2073), .B0(n7474), .B1(n4430), .Y(n4439)
);
ADDFHX2TS U7700 ( .A(n5140), .B(n5138), .CI(n5139), .CO(n5161), .S(n5134) );
NAND2X8TS U7701 ( .A(n3267), .B(n2903), .Y(n2787) );
BUFX6TS U7702 ( .A(DP_OP_168J26_122_4811_n6613), .Y(n5304) );
XNOR2X4TS U7703 ( .A(n2363), .B(n1967), .Y(n8068) );
XOR2X4TS U7704 ( .A(n2570), .B(n6561), .Y(n2889) );
ADDFHX2TS U7705 ( .A(n6061), .B(n6062), .CI(n6060), .CO(n6194), .S(n6065) );
XOR2X4TS U7706 ( .A(n2941), .B(n8135), .Y(n2940) );
OAI21X4TS U7707 ( .A0(n10165), .A1(n7963), .B0(n7962), .Y(n7966) );
OAI21X4TS U7708 ( .A0(n7658), .A1(n7660), .B0(n7661), .Y(n7647) );
XNOR2X2TS U7709 ( .A(n1019), .B(n8619), .Y(n6451) );
XNOR2X4TS U7710 ( .A(n3591), .B(n2058), .Y(n4704) );
AOI21X2TS U7711 ( .A0(n7913), .A1(n7895), .B0(n7894), .Y(n7896) );
OAI21X4TS U7712 ( .A0(n7916), .A1(n7897), .B0(n7896), .Y(n7898) );
XNOR2X2TS U7713 ( .A(n5278), .B(n2634), .Y(n4958) );
OAI22X2TS U7714 ( .A0(n1607), .A1(n7139), .B0(n2114), .B1(n5147), .Y(n5209)
);
ADDFHX2TS U7715 ( .A(n7214), .B(n7213), .CI(n7212), .CO(n7344), .S(n7217) );
XNOR2X4TS U7716 ( .A(n5561), .B(n2397), .Y(n3467) );
OAI22X2TS U7717 ( .A0(n4295), .A1(n1895), .B0(n4514), .B1(n2019), .Y(n4698)
);
NAND2X4TS U7718 ( .A(n6525), .B(n6526), .Y(n2471) );
NAND2X2TS U7719 ( .A(DP_OP_168J26_122_4811_n8543), .B(
DP_OP_168J26_122_4811_n8516), .Y(n3612) );
XNOR2X2TS U7720 ( .A(n2445), .B(n2341), .Y(n5627) );
CLKBUFX2TS U7721 ( .A(n8238), .Y(n2474) );
BUFX4TS U7722 ( .A(n8662), .Y(n2499) );
OAI21X4TS U7723 ( .A0(n9825), .A1(n1348), .B0(n9826), .Y(n2476) );
CLKINVX12TS U7724 ( .A(n11486), .Y(n6101) );
ADDFHX4TS U7725 ( .A(n4310), .B(n4312), .CI(n4311), .CO(n10043), .S(n4415)
);
ADDFHX4TS U7726 ( .A(n4416), .B(n4415), .CI(n4414), .CO(n10011), .S(n4396)
);
OAI21X4TS U7727 ( .A0(n6361), .A1(n6360), .B0(n6359), .Y(n2664) );
OAI2BB1X4TS U7728 ( .A0N(n9277), .A1N(n9278), .B0(n2480), .Y(n9965) );
OAI21X4TS U7729 ( .A0(n9278), .A1(n9277), .B0(n9276), .Y(n2480) );
OAI2BB1X4TS U7730 ( .A0N(n4563), .A1N(n4562), .B0(n2481), .Y(n4584) );
OAI21X4TS U7731 ( .A0(n4562), .A1(n4563), .B0(n4561), .Y(n2481) );
XOR2X4TS U7732 ( .A(n4562), .B(n4563), .Y(n2482) );
XNOR2X4TS U7733 ( .A(n886), .B(n2251), .Y(n4080) );
OAI22X2TS U7734 ( .A0(n7306), .A1(n1935), .B0(n7182), .B1(n9456), .Y(n7311)
);
OAI22X4TS U7735 ( .A0(n5306), .A1(n3960), .B0(n2048), .B1(n4555), .Y(n4531)
);
ADDFHX2TS U7736 ( .A(n4643), .B(n4642), .CI(n4641), .CO(n4701), .S(n4757) );
XOR2X4TS U7737 ( .A(n1006), .B(n1229), .Y(n6152) );
INVX6TS U7738 ( .A(n6422), .Y(n6498) );
ADDFHX4TS U7739 ( .A(n8105), .B(n8104), .CI(n8103), .CO(n8107), .S(n8961) );
XNOR2X4TS U7740 ( .A(n1019), .B(n2283), .Y(n5928) );
OAI22X2TS U7741 ( .A0(n5928), .A1(n1983), .B0(n5692), .B1(n6883), .Y(n5937)
);
OAI22X2TS U7742 ( .A0(n1822), .A1(n7995), .B0(n1950), .B1(n7280), .Y(n8017)
);
ADDFHX4TS U7743 ( .A(n6199), .B(n6198), .CI(n6197), .CO(n6233), .S(n6200) );
ADDFHX4TS U7744 ( .A(n6648), .B(n6647), .CI(n6646), .CO(n6724), .S(n6675) );
OAI22X2TS U7745 ( .A0(n2089), .A1(n6164), .B0(n6163), .B1(n6142), .Y(n6170)
);
OAI22X2TS U7746 ( .A0(n2102), .A1(n5859), .B0(n1948), .B1(n4175), .Y(n6303)
);
OAI22X2TS U7747 ( .A0(n7477), .A1(n4429), .B0(n7474), .B1(n4459), .Y(n4465)
);
OAI22X4TS U7748 ( .A0(n8543), .A1(n8614), .B0(n2032), .B1(n1852), .Y(n8524)
);
ADDFHX2TS U7749 ( .A(n6755), .B(n6754), .CI(n6753), .CO(n6779), .S(n6804) );
OAI22X4TS U7750 ( .A0(n8615), .A1(n6919), .B0(n8613), .B1(n6921), .Y(n8625)
);
XNOR2X4TS U7751 ( .A(n1812), .B(n1813), .Y(n6070) );
OAI2BB1X4TS U7752 ( .A0N(n6979), .A1N(n6978), .B0(n2485), .Y(n6984) );
OAI21X2TS U7753 ( .A0(n6978), .A1(n6979), .B0(n6977), .Y(n2485) );
XNOR2X4TS U7754 ( .A(n6979), .B(n6978), .Y(n2486) );
CLKBUFX2TS U7755 ( .A(n2921), .Y(n2487) );
NAND2X8TS U7756 ( .A(n2524), .B(n2892), .Y(n2489) );
XOR2X4TS U7757 ( .A(n2517), .B(n1653), .Y(n6271) );
OAI22X4TS U7758 ( .A0(n7445), .A1(n2445), .B0(n1921), .B1(n6181), .Y(n7450)
);
OAI22X2TS U7759 ( .A0(n8514), .A1(n1823), .B0(n1993), .B1(n1986), .Y(n8561)
);
NAND2BX4TS U7760 ( .AN(n1809), .B(n7273), .Y(n4826) );
OAI22X2TS U7761 ( .A0(n5785), .A1(n2112), .B0(n5514), .B1(n2575), .Y(n5698)
);
XNOR2X4TS U7762 ( .A(DP_OP_168J26_122_4811_n3228), .B(n11753), .Y(n3362) );
XNOR2X2TS U7763 ( .A(n8540), .B(n6562), .Y(n6417) );
XOR2X4TS U7764 ( .A(n6161), .B(n11735), .Y(n3568) );
OAI22X4TS U7765 ( .A0(n975), .A1(n4913), .B0(n979), .B1(n4882), .Y(n4916) );
ADDFHX4TS U7766 ( .A(n8568), .B(n8566), .CI(n8567), .CO(n9777), .S(n9784) );
XNOR2X4TS U7767 ( .A(n1284), .B(n6093), .Y(n5626) );
XNOR2X4TS U7768 ( .A(n2600), .B(n9770), .Y(n3076) );
ADDFHX4TS U7769 ( .A(n4649), .B(n4651), .CI(n4650), .CO(n9091), .S(n4742) );
AOI21X4TS U7770 ( .A0(n7556), .A1(n6391), .B0(n6390), .Y(n7538) );
OAI21X4TS U7771 ( .A0(n10111), .A1(n9056), .B0(n9057), .Y(n7556) );
XNOR2X4TS U7772 ( .A(n1220), .B(n2380), .Y(n3460) );
OAI22X2TS U7773 ( .A0(n1936), .A1(n3649), .B0(n1989), .B1(n3654), .Y(n3657)
);
OAI22X2TS U7774 ( .A0(n5897), .A1(n1968), .B0(n8447), .B1(n1933), .Y(n8493)
);
ADDFHX4TS U7775 ( .A(n3958), .B(n3959), .CI(n3957), .CO(n4563), .S(n3951) );
OAI22X4TS U7776 ( .A0(n730), .A1(n7037), .B0(n7070), .B1(n7471), .Y(n7075)
);
OAI22X2TS U7777 ( .A0(n795), .A1(n3684), .B0(n3660), .B1(n2114), .Y(n3742)
);
OAI22X4TS U7778 ( .A0(n5340), .A1(n3228), .B0(n4538), .B1(n1865), .Y(n4536)
);
AOI21X4TS U7779 ( .A0(n7702), .A1(n7690), .B0(n7689), .Y(n7751) );
OAI22X2TS U7780 ( .A0(n861), .A1(n4592), .B0(n2115), .B1(n4670), .Y(n4673)
);
NOR2X8TS U7781 ( .A(n7659), .B(n7660), .Y(n7641) );
NAND2X2TS U7782 ( .A(n1835), .B(n10873), .Y(n12342) );
XNOR2X4TS U7783 ( .A(n9076), .B(n9075), .Y(n9077) );
AOI21X2TS U7784 ( .A0(n9418), .A1(n7934), .B0(n7933), .Y(n7935) );
NAND2X2TS U7785 ( .A(n6378), .B(n2535), .Y(n7975) );
OAI22X2TS U7786 ( .A0(n2104), .A1(n5627), .B0(n5608), .B1(n1919), .Y(n5595)
);
OAI22X4TS U7787 ( .A0(n4676), .A1(n7997), .B0(n1923), .B1(n7996), .Y(n8026)
);
XNOR2X4TS U7788 ( .A(n6145), .B(n5666), .Y(n6066) );
OAI21X4TS U7789 ( .A0(n10749), .A1(n10746), .B0(n10750), .Y(n9548) );
OAI21X4TS U7790 ( .A0(n7693), .A1(n1159), .B0(n1174), .Y(n7689) );
XOR2X4TS U7791 ( .A(n9930), .B(n2502), .Y(n2501) );
ADDFHX4TS U7792 ( .A(n6860), .B(n6861), .CI(n6859), .CO(n6862), .S(n6855) );
OAI2BB1X4TS U7793 ( .A0N(n10079), .A1N(n9035), .B0(n2754), .Y(n2753) );
OAI21X4TS U7794 ( .A0(n8185), .A1(n8184), .B0(n8183), .Y(n8186) );
OAI22X4TS U7795 ( .A0(n3697), .A1(n1943), .B0(n3803), .B1(n5340), .Y(n3807)
);
XNOR2X2TS U7796 ( .A(n2456), .B(n1954), .Y(n6922) );
NAND2X8TS U7797 ( .A(n9261), .B(n7010), .Y(n3304) );
XNOR2X4TS U7798 ( .A(n2092), .B(n2634), .Y(n4546) );
OAI2BB1X4TS U7799 ( .A0N(n9969), .A1N(n9968), .B0(n2506), .Y(n9033) );
OAI21X4TS U7800 ( .A0(n9969), .A1(n9968), .B0(n9967), .Y(n2506) );
OAI22X4TS U7801 ( .A0(n975), .A1(n4920), .B0(n3094), .B1(n981), .Y(n4962) );
XNOR2X2TS U7802 ( .A(n1890), .B(n5175), .Y(n5149) );
XOR2X4TS U7803 ( .A(n2507), .B(n8768), .Y(n7338) );
XOR2X4TS U7804 ( .A(n8767), .B(n7340), .Y(n2507) );
XOR2X4TS U7805 ( .A(n2508), .B(DP_OP_168J26_122_4811_n3232), .Y(n3636) );
OAI22X4TS U7806 ( .A0(n7997), .A1(n4595), .B0(n1951), .B1(n4676), .Y(n4678)
);
OAI2BB1X4TS U7807 ( .A0N(n9900), .A1N(n9899), .B0(n2509), .Y(n9903) );
OAI21X4TS U7808 ( .A0(n9899), .A1(n9900), .B0(n9898), .Y(n2509) );
XNOR2X4TS U7809 ( .A(n2510), .B(n1769), .Y(n9957) );
XNOR2X4TS U7810 ( .A(n9898), .B(n9900), .Y(n2510) );
OAI22X4TS U7811 ( .A0(n4349), .A1(n2050), .B0(n4355), .B1(n8931), .Y(n8537)
);
OAI22X4TS U7812 ( .A0(n5782), .A1(n8530), .B0(n8980), .B1(n5781), .Y(n6457)
);
OR2X8TS U7813 ( .A(n3242), .B(n3191), .Y(n2750) );
ADDFHX2TS U7814 ( .A(n4320), .B(n4319), .CI(n4318), .CO(n4334), .S(n4330) );
OAI21X4TS U7815 ( .A0(n3605), .A1(n3758), .B0(n3604), .Y(n3608) );
XNOR2X4TS U7816 ( .A(n1819), .B(n2037), .Y(n8947) );
NOR2X8TS U7817 ( .A(n3127), .B(n2761), .Y(n2512) );
NAND2X2TS U7818 ( .A(n1011), .B(n1000), .Y(n12289) );
OAI22X2TS U7819 ( .A0(n2111), .A1(n5252), .B0(n5330), .B1(n1899), .Y(n5348)
);
AOI21X2TS U7820 ( .A0(n7913), .A1(n11773), .B0(n11606), .Y(n7886) );
ADDFHX2TS U7821 ( .A(n5659), .B(n5660), .CI(n5658), .CO(n5879), .S(n5653) );
ADDFHX2TS U7822 ( .A(n5603), .B(n5602), .CI(n5601), .CO(n5654), .S(n5598) );
ADDFHX4TS U7823 ( .A(n5654), .B(n5653), .CI(n5652), .CO(n5892), .S(n5656) );
OAI22X4TS U7824 ( .A0(n4794), .A1(n2379), .B0(n7474), .B1(n7448), .Y(n7436)
);
OAI2BB1X4TS U7825 ( .A0N(n9904), .A1N(n2515), .B0(n2513), .Y(n9909) );
OAI21X4TS U7826 ( .A0(n2515), .A1(n9904), .B0(n9903), .Y(n2513) );
XOR2X4TS U7827 ( .A(n6263), .B(n6264), .Y(n2517) );
OAI22X2TS U7828 ( .A0(n7477), .A1(n5862), .B0(n1896), .B1(n5861), .Y(n6301)
);
OAI2BB1X4TS U7829 ( .A0N(n4821), .A1N(n2520), .B0(n2519), .Y(
DP_OP_168J26_122_4811_n1079) );
OAI21X4TS U7830 ( .A0(n2520), .A1(n4821), .B0(n2650), .Y(n2519) );
ADDFHX4TS U7831 ( .A(n4506), .B(n4504), .CI(n4505), .CO(n4481), .S(n4520) );
OAI22X2TS U7832 ( .A0(n3407), .A1(n1916), .B0(n2100), .B1(n3398), .Y(n3442)
);
ADDFHX4TS U7833 ( .A(n9922), .B(n9921), .CI(n9920), .CO(n4740), .S(n9928) );
ADDFHX4TS U7834 ( .A(n9919), .B(n9917), .CI(n2289), .CO(n9929), .S(n10044)
);
OAI22X4TS U7835 ( .A0(n5536), .A1(n8948), .B0(n8950), .B1(n5497), .Y(n5538)
);
ADDHX4TS U7836 ( .A(n5539), .B(n5538), .CO(n5546), .S(n5519) );
ADDFHX4TS U7837 ( .A(n4756), .B(n4755), .CI(n4754), .CO(n9938), .S(n9935) );
ADDFHX4TS U7838 ( .A(n4183), .B(n4184), .CI(n4182), .CO(n4145), .S(n4206) );
NAND3X8TS U7839 ( .A(n2787), .B(n11011), .C(n9337), .Y(n2524) );
XOR2X4TS U7840 ( .A(n2584), .B(n6728), .Y(n6736) );
NAND4X2TS U7841 ( .A(n9241), .B(n9240), .C(n9239), .D(n9238), .Y(n9252) );
OAI21X1TS U7842 ( .A0(n9166), .A1(n9156), .B0(n9155), .Y(n9161) );
OAI22X2TS U7843 ( .A0(n7138), .A1(n2221), .B0(n5320), .B1(n7215), .Y(n7219)
);
ADDFHX4TS U7844 ( .A(n7510), .B(n7509), .CI(n7508), .CO(n7543), .S(n7502) );
NAND2X2TS U7845 ( .A(n11749), .B(DP_OP_168J26_122_4811_n3590), .Y(n3769) );
ADDFHX2TS U7846 ( .A(n4385), .B(n4384), .CI(n4383), .CO(n4276), .S(n4392) );
ADDFHX2TS U7847 ( .A(n4091), .B(n4090), .CI(n4089), .CO(n4086), .S(n4374) );
XNOR2X4TS U7848 ( .A(n8534), .B(n1024), .Y(n4065) );
ADDFHX2TS U7849 ( .A(n4613), .B(n4612), .CI(n4611), .CO(n4656), .S(n4599) );
AOI21X2TS U7850 ( .A0(n11652), .A1(n11653), .B0(n11654), .Y(n7869) );
OAI22X2TS U7851 ( .A0(n3448), .A1(n2105), .B0(n1921), .B1(n4448), .Y(n4503)
);
OAI21X4TS U7852 ( .A0(n7916), .A1(n7915), .B0(n7914), .Y(n7917) );
OAI22X2TS U7853 ( .A0(n2103), .A1(n5704), .B0(n1948), .B1(n5624), .Y(n5712)
);
ADDFHX4TS U7854 ( .A(n4156), .B(n4157), .CI(n4155), .CO(n4269), .S(n4209) );
XOR2X4TS U7855 ( .A(n5699), .B(n5700), .Y(n3033) );
OAI22X4TS U7856 ( .A0(n1980), .A1(n5323), .B0(n5322), .B1(n8013), .Y(n5373)
);
XNOR2X2TS U7857 ( .A(n8443), .B(n8626), .Y(n6657) );
BUFX12TS U7858 ( .A(n10027), .Y(n2536) );
NAND2X4TS U7859 ( .A(n2797), .B(n9589), .Y(add_x_19_n703) );
XOR2X4TS U7860 ( .A(n2800), .B(n1427), .Y(n2797) );
ADDFHX4TS U7861 ( .A(n7312), .B(n7311), .CI(n7310), .CO(n7302), .S(n8150) );
OAI22X4TS U7862 ( .A0(n5793), .A1(n3320), .B0(n6154), .B1(n5962), .Y(n5966)
);
XNOR2X4TS U7863 ( .A(n1292), .B(n11499), .Y(n5793) );
OAI2BB1X4TS U7864 ( .A0N(n1394), .A1N(n2902), .B0(n3579), .Y(n3582) );
OAI22X4TS U7865 ( .A0(n2077), .A1(n2341), .B0(n4450), .B1(n1624), .Y(n3413)
);
XOR2X4TS U7866 ( .A(n2527), .B(n2092), .Y(n7017) );
CLKINVX12TS U7867 ( .A(n11007), .Y(n2903) );
OAI2BB1X4TS U7868 ( .A0N(n10283), .A1N(n2541), .B0(n6090), .Y(n10245) );
NOR2BX4TS U7869 ( .AN(n10303), .B(n10280), .Y(n2541) );
OAI22X2TS U7870 ( .A0(n2096), .A1(n5054), .B0(n5053), .B1(n11758), .Y(n5080)
);
NAND2X2TS U7871 ( .A(n7958), .B(n10124), .Y(n7963) );
ADDFHX2TS U7872 ( .A(n5186), .B(n5185), .CI(n5184), .CO(n5216), .S(n5195) );
XNOR2X2TS U7873 ( .A(n5273), .B(n1711), .Y(n3664) );
OAI22X2TS U7874 ( .A0(n2105), .A1(n3470), .B0(n1918), .B1(n3419), .Y(n3485)
);
OAI22X2TS U7875 ( .A0(n4448), .A1(n7445), .B0(n1918), .B1(n4447), .Y(n4476)
);
XNOR2X2TS U7876 ( .A(n2021), .B(n8539), .Y(n8541) );
XNOR2X2TS U7877 ( .A(n3345), .B(n2251), .Y(n4081) );
XNOR2X4TS U7878 ( .A(n5561), .B(n6714), .Y(n5560) );
OAI21X4TS U7879 ( .A0(n5687), .A1(n5688), .B0(n5686), .Y(n2547) );
XNOR2X4TS U7880 ( .A(n2548), .B(n5687), .Y(n5742) );
NAND2X2TS U7881 ( .A(n6289), .B(n1332), .Y(n10157) );
OAI21X4TS U7882 ( .A0(n2658), .A1(n3620), .B0(n807), .Y(n3354) );
INVX4TS U7883 ( .A(n10234), .Y(n6137) );
OAI22X2TS U7884 ( .A0(n3880), .A1(n6018), .B0(n6048), .B1(n1227), .Y(n6052)
);
NAND2BX4TS U7885 ( .AN(n5666), .B(n976), .Y(n5562) );
INVX2TS U7886 ( .A(n7214), .Y(n7136) );
AOI2BB1X4TS U7887 ( .A0N(n2989), .A1N(n8180), .B0(n2991), .Y(n2990) );
XNOR2X4TS U7888 ( .A(n6670), .B(n6671), .Y(n2553) );
XOR2X4TS U7889 ( .A(n2554), .B(n4617), .Y(n4638) );
BUFX12TS U7890 ( .A(n5533), .Y(n2556) );
OAI21X4TS U7891 ( .A0(n2559), .A1(n8477), .B0(n2558), .Y(n8694) );
NAND2X8TS U7892 ( .A(n9334), .B(n2892), .Y(n8354) );
AO21X4TS U7893 ( .A0(n2111), .A1(n1899), .B0(n1726), .Y(n3655) );
NAND2X8TS U7894 ( .A(n2563), .B(n2562), .Y(n4421) );
INVX2TS U7895 ( .A(n8773), .Y(n7393) );
OAI22X2TS U7896 ( .A0(n2090), .A1(n6022), .B0(n6018), .B1(n6142), .Y(n6009)
);
XOR2X4TS U7897 ( .A(n2893), .B(n4247), .Y(n5408) );
NAND2X2TS U7898 ( .A(n6291), .B(n10155), .Y(n6293) );
NOR2X6TS U7899 ( .A(n7821), .B(n11355), .Y(n9532) );
NAND2X8TS U7900 ( .A(n2992), .B(n2990), .Y(n9261) );
OAI22X4TS U7901 ( .A0(n8980), .A1(n1558), .B0(n2356), .B1(n5780), .Y(n6458)
);
OAI22X2TS U7902 ( .A0(n5541), .A1(n2052), .B0(n5506), .B1(n1908), .Y(n5900)
);
ADDFHX4TS U7903 ( .A(n8491), .B(n8490), .CI(n8489), .CO(n8601), .S(n8497) );
XOR2X4TS U7904 ( .A(n2567), .B(n4507), .Y(n4489) );
NOR2BX2TS U7905 ( .AN(n1902), .B(n1898), .Y(n5049) );
ADDFHX4TS U7906 ( .A(n9860), .B(n9859), .CI(n9858), .CO(n9847), .S(n9893) );
XNOR2X2TS U7907 ( .A(n8420), .B(n8419), .Y(n9282) );
NAND2X4TS U7908 ( .A(n9623), .B(add_x_19_n755), .Y(add_x_19_n68) );
XOR2X4TS U7909 ( .A(n2959), .B(n7165), .Y(n7172) );
XNOR2X4TS U7910 ( .A(n1812), .B(n2448), .Y(n6082) );
ADDFHX2TS U7911 ( .A(n6169), .B(n6170), .CI(n6171), .CO(n6217), .S(n6198) );
INVX4TS U7912 ( .A(n10631), .Y(n5093) );
AOI21X4TS U7913 ( .A0(n1801), .A1(n9625), .B0(n9586), .Y(add_x_19_n748) );
OAI21X4TS U7914 ( .A0(n6166), .A1(n6168), .B0(n6167), .Y(n3110) );
OAI2BB1X4TS U7915 ( .A0N(n6676), .A1N(n6677), .B0(n2639), .Y(n6734) );
OAI21X4TS U7916 ( .A0(n2988), .A1(n6662), .B0(n6661), .Y(n2987) );
ADDFHX4TS U7917 ( .A(n5215), .B(n5214), .CI(n5213), .CO(n5288), .S(n5217) );
OAI22X4TS U7918 ( .A0(n3247), .A1(n1865), .B0(n3213), .B1(n5340), .Y(n4891)
);
XNOR2X4TS U7919 ( .A(n2078), .B(DP_OP_168J26_122_4811_n8479), .Y(n3247) );
OAI21X4TS U7920 ( .A0(n7789), .A1(n7782), .B0(n7790), .Y(n7669) );
OAI21X1TS U7921 ( .A0(n7680), .A1(n7683), .B0(n7684), .Y(n7670) );
OR2X8TS U7922 ( .A(n1160), .B(n7925), .Y(n8820) );
OAI2BB1X4TS U7923 ( .A0N(n2617), .A1N(n1380), .B0(n10936), .Y(n10937) );
OAI22X2TS U7924 ( .A0(n1915), .A1(n3498), .B0(n3467), .B1(n3321), .Y(n3493)
);
OAI22X2TS U7925 ( .A0(n4343), .A1(n1968), .B0(n4342), .B1(n1933), .Y(n4387)
);
OAI21X2TS U7926 ( .A0(n7926), .A1(n8829), .B0(n8819), .Y(n7927) );
ADDFHX2TS U7927 ( .A(n9818), .B(n9817), .CI(n9816), .CO(n9853), .S(n9842) );
NAND2X8TS U7928 ( .A(n1347), .B(n1400), .Y(n2698) );
ADDFX2TS U7929 ( .A(n4303), .B(n4302), .CI(n4301), .CO(n4304), .S(n4309) );
ADDFHX4TS U7930 ( .A(n8906), .B(n8905), .CI(n8904), .CO(n8902), .S(n8975) );
OAI22X2TS U7931 ( .A0(n2027), .A1(n4876), .B0(n1988), .B1(n4875), .Y(n4909)
);
OAI22X2TS U7932 ( .A0(n5593), .A1(n2038), .B0(n6174), .B1(n5594), .Y(n5716)
);
XNOR2X2TS U7933 ( .A(n8443), .B(n2031), .Y(n6438) );
XOR2X4TS U7934 ( .A(DP_OP_168J26_122_4811_n8500), .B(
DP_OP_168J26_122_4811_n8527), .Y(n3995) );
INVX2TS U7935 ( .A(n6688), .Y(n2981) );
OAI21X4TS U7936 ( .A0(n9742), .A1(n6136), .B0(n6135), .Y(n9739) );
AOI21X4TS U7937 ( .A0(n10245), .A1(n6115), .B0(n6114), .Y(n9742) );
NOR2X6TS U7938 ( .A(n9283), .B(n9282), .Y(add_x_19_n754) );
NAND2X6TS U7939 ( .A(n2824), .B(n2825), .Y(n2812) );
OAI21X4TS U7940 ( .A0(n8038), .A1(n8037), .B0(n8036), .Y(n3195) );
NAND2X2TS U7941 ( .A(n6555), .B(n2493), .Y(n10216) );
OAI22X4TS U7942 ( .A0(n6223), .A1(n6077), .B0(n1939), .B1(n6076), .Y(n6083)
);
NAND2X2TS U7943 ( .A(n6612), .B(n6611), .Y(n10227) );
XNOR2X4TS U7944 ( .A(n2328), .B(n7369), .Y(n8019) );
XOR2X4TS U7945 ( .A(n2604), .B(n8470), .Y(n8657) );
XOR2X4TS U7946 ( .A(n6243), .B(n6242), .Y(n2578) );
OAI22X2TS U7947 ( .A0(n5684), .A1(n6087), .B0(n1938), .B1(n4195), .Y(n5872)
);
XOR2X4TS U7948 ( .A(n2580), .B(n1401), .Y(n3241) );
AOI21X4TS U7949 ( .A0(n2902), .A1(n3570), .B0(n3756), .Y(n2580) );
OAI22X2TS U7950 ( .A0(n4341), .A1(n2293), .B0(n3792), .B1(n1893), .Y(n4008)
);
ADDFHX4TS U7951 ( .A(n4542), .B(n4543), .CI(n4544), .CO(n4616), .S(n4567) );
XNOR2X4TS U7952 ( .A(n9637), .B(n2582), .Y(Sgf_operation_Result_28_) );
OAI22X2TS U7953 ( .A0(n1866), .A1(n5793), .B0(n3320), .B1(n5751), .Y(n5799)
);
OAI22X4TS U7954 ( .A0(n2077), .A1(n2397), .B0(n1883), .B1(n7488), .Y(n4795)
);
XNOR2X4TS U7955 ( .A(n2238), .B(n2408), .Y(n5632) );
AOI21X2TS U7956 ( .A0(DP_OP_168J26_122_4811_n3536), .A1(n3369), .B0(n11751),
.Y(n3341) );
OAI21X4TS U7957 ( .A0(n10175), .A1(n10171), .B0(n10176), .Y(n10154) );
XNOR2X4TS U7958 ( .A(n1819), .B(n2031), .Y(n8617) );
NAND2X4TS U7959 ( .A(n9812), .B(n9811), .Y(n3122) );
BUFX20TS U7960 ( .A(n8921), .Y(n2632) );
INVX4TS U7961 ( .A(n9982), .Y(DP_OP_168J26_122_4811_n348) );
INVX4TS U7962 ( .A(n5206), .Y(n2730) );
OAI22X4TS U7963 ( .A0(n6087), .A1(n4195), .B0(n1939), .B1(n4164), .Y(n4202)
);
ADDFHX4TS U7964 ( .A(n5422), .B(n5424), .CI(n5423), .CO(n5428), .S(n5458) );
XNOR2X4TS U7965 ( .A(n2593), .B(n8269), .Y(n8751) );
OAI2BB1X4TS U7966 ( .A0N(n9960), .A1N(n9959), .B0(n2594), .Y(
DP_OP_168J26_122_4811_n1029) );
OAI21X4TS U7967 ( .A0(n9959), .A1(n9960), .B0(n9958), .Y(n2594) );
XOR2X4TS U7968 ( .A(n2595), .B(n9958), .Y(DP_OP_168J26_122_4811_n1030) );
OAI21X4TS U7969 ( .A0(n6677), .A1(n6676), .B0(n6675), .Y(n2639) );
XNOR2X2TS U7970 ( .A(n8444), .B(n6562), .Y(n6477) );
XOR2X4TS U7971 ( .A(n4055), .B(n4054), .Y(n3071) );
OAI22X2TS U7972 ( .A0(n2089), .A1(n6070), .B0(n6094), .B1(n6142), .Y(n6113)
);
NAND2X2TS U7973 ( .A(n1842), .B(n907), .Y(n9057) );
OAI22X2TS U7974 ( .A0(n861), .A1(n3660), .B0(n3962), .B1(n2115), .Y(n3957)
);
ADDFHX4TS U7975 ( .A(n6822), .B(n6821), .CI(n6820), .CO(n6819), .S(n6861) );
INVX2TS U7976 ( .A(n9737), .Y(n6830) );
NAND2BX4TS U7977 ( .AN(n5666), .B(n1812), .Y(n6080) );
NAND2X2TS U7978 ( .A(DP_OP_168J26_122_4811_n8535), .B(n1682), .Y(n3577) );
ADDFHX4TS U7979 ( .A(n6626), .B(n6625), .CI(n6624), .CO(n6650), .S(n6711) );
ADDFHX4TS U7980 ( .A(n6493), .B(n6492), .CI(n6491), .CO(n6515), .S(n6567) );
XOR2X4TS U7981 ( .A(n9505), .B(n9504), .Y(add_x_19_n121) );
OAI22X4TS U7982 ( .A0(n8470), .A1(n2603), .B0(n2602), .B1(n2601), .Y(n8653)
);
INVX2TS U7983 ( .A(n8651), .Y(n2602) );
NOR2X2TS U7984 ( .A(n8652), .B(n8651), .Y(n2603) );
XNOR2X4TS U7985 ( .A(n8651), .B(n8652), .Y(n2604) );
OAI22X2TS U7986 ( .A0(n5345), .A1(n5040), .B0(n5044), .B1(n11758), .Y(n5047)
);
OAI22X2TS U7987 ( .A0(n4812), .A1(n2331), .B0(n8932), .B1(n5488), .Y(n8953)
);
XNOR2X4TS U7988 ( .A(n1832), .B(n1858), .Y(n5039) );
XNOR2X2TS U7989 ( .A(n7444), .B(n1333), .Y(n3920) );
NOR2X4TS U7990 ( .A(n3920), .B(n3919), .Y(n3921) );
OAI21X4TS U7991 ( .A0(n2607), .A1(n3758), .B0(n3571), .Y(n2938) );
NAND2BX4TS U7992 ( .AN(n3569), .B(n3570), .Y(n2607) );
BUFX12TS U7993 ( .A(n6405), .Y(n2608) );
ADDFHX2TS U7994 ( .A(n6418), .B(n6419), .CI(n6420), .CO(n6495), .S(n6500) );
INVX2TS U7995 ( .A(n6605), .Y(n6626) );
ADDFHX4TS U7996 ( .A(n4934), .B(n4933), .CI(n4932), .CO(n4931), .S(n4969) );
ADDFHX4TS U7997 ( .A(n5788), .B(n5786), .CI(n5787), .CO(n5839), .S(n8244) );
OAI2BB1X4TS U7998 ( .A0N(n6296), .A1N(n6295), .B0(n2613), .Y(n9781) );
OAI2BB1X4TS U7999 ( .A0N(n4236), .A1N(n4237), .B0(n2649), .Y(n4217) );
INVX4TS U8000 ( .A(n1233), .Y(n3024) );
BUFX20TS U8001 ( .A(Op_MY[26]), .Y(n2653) );
OAI21X4TS U8002 ( .A0(n3342), .A1(n2658), .B0(n3341), .Y(n3344) );
OAI22X4TS U8003 ( .A0(n861), .A1(n7087), .B0(n2114), .B1(n7086), .Y(n7092)
);
ADDFHX2TS U8004 ( .A(n5947), .B(n5946), .CI(n5945), .CO(n5812), .S(n6240) );
ADDFHX4TS U8005 ( .A(n3691), .B(n3690), .CI(n3689), .CO(n3724), .S(n3825) );
OAI21X4TS U8006 ( .A0(n1825), .A1(n9051), .B0(n9050), .Y(n9055) );
NOR2BX4TS U8007 ( .AN(n1902), .B(n2115), .Y(n5152) );
XNOR2X2TS U8008 ( .A(n2549), .B(n2453), .Y(n4518) );
OAI21X4TS U8009 ( .A0(n2202), .A1(n9073), .B0(n9072), .Y(n9076) );
XNOR2X4TS U8010 ( .A(n7704), .B(n11577), .Y(n7717) );
OAI21X2TS U8011 ( .A0(n8743), .A1(n9144), .B0(n8744), .Y(n7719) );
OAI2BB1X4TS U8012 ( .A0N(n2617), .A1N(n1382), .B0(n10917), .Y(n10918) );
OAI2BB1X4TS U8013 ( .A0N(n2618), .A1N(n1379), .B0(n10909), .Y(n10910) );
OAI2BB1X4TS U8014 ( .A0N(n2617), .A1N(n1342), .B0(n10900), .Y(n10901) );
OAI2BB1X4TS U8015 ( .A0N(n2618), .A1N(n1381), .B0(n10893), .Y(n10894) );
OAI21X4TS U8016 ( .A0(n7916), .A1(n7904), .B0(n7903), .Y(n7905) );
AOI2BB2X2TS U8017 ( .B0(n10947), .B1(n10973), .A0N(n10860), .A1N(n11859),
.Y(n12327) );
NOR2X8TS U8018 ( .A(n8355), .B(n1254), .Y(n8415) );
OAI2BB1X4TS U8019 ( .A0N(n4618), .A1N(n4619), .B0(n2619), .Y(n4814) );
OAI21X4TS U8020 ( .A0(n4618), .A1(n4619), .B0(n4617), .Y(n2619) );
NOR2X8TS U8021 ( .A(n9593), .B(n9313), .Y(n7918) );
NAND2X2TS U8022 ( .A(n2064), .B(n9618), .Y(n9620) );
XNOR2X4TS U8023 ( .A(n7353), .B(n1008), .Y(n4029) );
OAI2BB1X4TS U8024 ( .A0N(n9935), .A1N(n9934), .B0(n2620), .Y(n10046) );
XOR2X4TS U8025 ( .A(n9934), .B(n2621), .Y(n10048) );
XOR2X4TS U8026 ( .A(n9933), .B(n9935), .Y(n2621) );
XNOR2X4TS U8027 ( .A(n3017), .B(n5137), .Y(n3011) );
XNOR2X4TS U8028 ( .A(n8550), .B(n2037), .Y(n4724) );
OAI2BB1X4TS U8029 ( .A0N(n6231), .A1N(n6230), .B0(n2623), .Y(n6262) );
OAI21X4TS U8030 ( .A0(n6230), .A1(n6231), .B0(n6229), .Y(n2623) );
XNOR2X4TS U8031 ( .A(n2624), .B(n6230), .Y(n6234) );
XNOR2X4TS U8032 ( .A(n6231), .B(n6229), .Y(n2624) );
BUFX20TS U8033 ( .A(DP_OP_168J26_122_4811_n8482), .Y(n2634) );
XOR2X4TS U8034 ( .A(n9514), .B(n9513), .Y(add_x_19_n130) );
ADDFHX4TS U8035 ( .A(n4264), .B(n4266), .CI(n4265), .CO(n3912), .S(n4329) );
OAI21X4TS U8036 ( .A0(n10215), .A1(n10220), .B0(n10216), .Y(n10207) );
NOR2X4TS U8037 ( .A(n2463), .B(n7582), .Y(n8425) );
AOI21X4TS U8038 ( .A0(n9638), .A1(n9644), .B0(n9496), .Y(n9507) );
XOR2X4TS U8039 ( .A(n2755), .B(n9902), .Y(n2626) );
OAI22X4TS U8040 ( .A0(n3213), .A1(n1943), .B0(n4912), .B1(n2106), .Y(n4933)
);
XNOR2X4TS U8041 ( .A(n2078), .B(n1885), .Y(n3213) );
OAI21X4TS U8042 ( .A0(n2612), .A1(n9887), .B0(n2885), .Y(n2884) );
ADDFHX4TS U8043 ( .A(n9804), .B(n9802), .CI(n9803), .CO(n9806), .S(n9829) );
OAI22X4TS U8044 ( .A0(n8531), .A1(n8980), .B0(n4362), .B1(n1823), .Y(n8528)
);
NOR4X4TS U8045 ( .A(n472), .B(n469), .C(n470), .D(n471), .Y(n9247) );
OAI22X2TS U8046 ( .A0(n2102), .A1(n5604), .B0(n5661), .B1(n1948), .Y(n5660)
);
OAI22X2TS U8047 ( .A0(n3432), .A1(n6178), .B0(n6040), .B1(n6161), .Y(n3412)
);
XNOR2X2TS U8048 ( .A(n6633), .B(n4488), .Y(n4354) );
OAI21X1TS U8049 ( .A0(n9228), .A1(n9227), .B0(n9226), .Y(n9229) );
OAI21X2TS U8050 ( .A0(n7727), .A1(n11586), .B0(n11587), .Y(n7728) );
XNOR2X4TS U8051 ( .A(n7728), .B(n11570), .Y(n7732) );
XOR2X4TS U8052 ( .A(n2642), .B(n8592), .Y(n8693) );
NAND2X2TS U8053 ( .A(n10059), .B(n10069), .Y(n8380) );
OAI2BB1X4TS U8054 ( .A0N(n9130), .A1N(n1326), .B0(n2627), .Y(n9967) );
XOR2X4TS U8055 ( .A(n2629), .B(n2628), .Y(n9961) );
XOR2X4TS U8056 ( .A(n9130), .B(n9129), .Y(n2629) );
NOR2X8TS U8057 ( .A(n2974), .B(n2630), .Y(n2975) );
NOR2X8TS U8058 ( .A(n8592), .B(n2815), .Y(n2817) );
XOR2X4TS U8059 ( .A(n11779), .B(n11516), .Y(n3785) );
ADDFHX4TS U8060 ( .A(n6569), .B(n6567), .CI(n6568), .CO(n6572), .S(n8298) );
NOR2X8TS U8061 ( .A(n8389), .B(n7533), .Y(n7535) );
AOI21X4TS U8062 ( .A0(n8869), .A1(n7809), .B0(n7808), .Y(n7810) );
NAND3X4TS U8063 ( .A(n10978), .B(n11242), .C(n11333), .Y(n419) );
NOR2X4TS U8064 ( .A(n7693), .B(n1138), .Y(n7690) );
INVX2TS U8065 ( .A(n8864), .Y(n7799) );
XNOR2X4TS U8066 ( .A(n2936), .B(n1946), .Y(n5897) );
XOR2X4TS U8067 ( .A(n2635), .B(n8036), .Y(n8145) );
NAND2X8TS U8068 ( .A(n2637), .B(n2636), .Y(n5982) );
NAND2X2TS U8069 ( .A(n4899), .B(n4900), .Y(n2636) );
XOR2X4TS U8070 ( .A(n4899), .B(n4900), .Y(n2638) );
OAI22X2TS U8071 ( .A0(n2102), .A1(n6037), .B0(n6176), .B1(n6036), .Y(n6126)
);
OAI22X4TS U8072 ( .A0(n2447), .A1(n5056), .B0(n1959), .B1(n5005), .Y(n5083)
);
NAND2X4TS U8073 ( .A(DP_OP_168J26_122_4811_n613), .B(n10005), .Y(
DP_OP_168J26_122_4811_n591) );
OAI22X4TS U8074 ( .A0(DP_OP_168J26_122_4811_n6617), .A1(n4912), .B0(n4943),
.B1(n5340), .Y(n4946) );
OAI22X4TS U8075 ( .A0(n2447), .A1(n5037), .B0(n5039), .B1(n1958), .Y(n5041)
);
XOR2X4TS U8076 ( .A(n2641), .B(n6727), .Y(n8297) );
OAI22X2TS U8077 ( .A0(n6645), .A1(n1953), .B0(n6602), .B1(n1852), .Y(n6621)
);
ADDFHX4TS U8078 ( .A(n6591), .B(n6592), .CI(n2686), .CO(n6596), .S(n6647) );
XOR2X4TS U8079 ( .A(n2818), .B(n8668), .Y(n2642) );
ADDFHX4TS U8080 ( .A(n8458), .B(n8457), .CI(n8456), .CO(n8658), .S(n8455) );
NOR2X2TS U8081 ( .A(DP_OP_168J26_122_4811_n8544), .B(
DP_OP_168J26_122_4811_n8517), .Y(n3611) );
ADDFHX4TS U8082 ( .A(n8635), .B(n8636), .CI(n8637), .CO(n8670), .S(n8705) );
BUFX20TS U8083 ( .A(n3358), .Y(n8443) );
OAI22X4TS U8084 ( .A0(n2107), .A1(n1385), .B0(n1865), .B1(n3852), .Y(n4048)
);
NAND2X2TS U8085 ( .A(n9334), .B(n9338), .Y(n9324) );
INVX4TS U8086 ( .A(n9636), .Y(n2916) );
NAND2BX4TS U8087 ( .AN(n2644), .B(n6604), .Y(n6651) );
OAI21X4TS U8088 ( .A0(n2646), .A1(n2645), .B0(n6603), .Y(n2644) );
BUFX3TS U8089 ( .A(n4819), .Y(n2650) );
XOR2X4TS U8090 ( .A(n3083), .B(n5187), .Y(n5143) );
AOI2BB2X4TS U8091 ( .B0(n2965), .B1(n1922), .A0N(n2411), .A1N(n7083), .Y(
n2964) );
ADDFHX4TS U8092 ( .A(n6548), .B(n6550), .CI(n6549), .CO(n6733), .S(n6583) );
XOR2X4TS U8093 ( .A(n2655), .B(n5460), .Y(n5463) );
XOR2X4TS U8094 ( .A(n1731), .B(n5462), .Y(n2655) );
XNOR2X2TS U8095 ( .A(DP_OP_168J26_122_4811_n3238), .B(
DP_OP_168J26_122_4811_n3212), .Y(n3784) );
ADDFHX4TS U8096 ( .A(n3902), .B(n3901), .CI(n3900), .CO(n3890), .S(n4162) );
XOR2X4TS U8097 ( .A(n3172), .B(n2656), .Y(n9805) );
OAI22X2TS U8098 ( .A0(n4442), .A1(n730), .B0(n1916), .B1(n4441), .Y(n4474)
);
XNOR2X4TS U8099 ( .A(n8443), .B(n1972), .Y(n4635) );
OAI21X4TS U8100 ( .A0(n8840), .A1(n7811), .B0(n7810), .Y(n7979) );
AOI21X4TS U8101 ( .A0(n9206), .A1(n7749), .B0(n7748), .Y(n8840) );
AOI21X4TS U8102 ( .A0(n9739), .A1(n6139), .B0(n6138), .Y(n10206) );
AOI21X4TS U8103 ( .A0(n8340), .A1(n7600), .B0(n7599), .Y(n7601) );
OAI22X2TS U8104 ( .A0(n2100), .A1(n1220), .B0(n1916), .B1(n1031), .Y(n7099)
);
AOI21X2TS U8105 ( .A0(n9654), .A1(n9653), .B0(n1366), .Y(n9655) );
OAI21X1TS U8106 ( .A0(n9157), .A1(n9155), .B0(n9158), .Y(n7713) );
NOR2X1TS U8107 ( .A(n9157), .B(n9156), .Y(n7714) );
NAND2X6TS U8108 ( .A(n8323), .B(n8324), .Y(n9987) );
OAI2BB1X4TS U8109 ( .A0N(n5389), .A1N(n5388), .B0(n2660), .Y(n5406) );
OAI22X2TS U8110 ( .A0(n2104), .A1(n5764), .B0(n5706), .B1(n1919), .Y(n5767)
);
ADDFHX2TS U8111 ( .A(n5901), .B(n5900), .CI(n5899), .CO(n8489), .S(n5906) );
AOI21X4TS U8112 ( .A0(n10625), .A1(n10623), .B0(n5090), .Y(n5091) );
XOR2X4TS U8113 ( .A(n2662), .B(n1425), .Y(n3295) );
OAI21X4TS U8114 ( .A0(n11009), .A1(n9336), .B0(n9335), .Y(n2662) );
XNOR2X2TS U8115 ( .A(n8443), .B(n8887), .Y(n5541) );
OAI22X4TS U8116 ( .A0(n1910), .A1(n3459), .B0(n2030), .B1(n3414), .Y(n3474)
);
CMPR22X2TS U8117 ( .A(n6092), .B(n6091), .CO(n6125), .S(n6133) );
XOR2X4TS U8118 ( .A(n2280), .B(n3021), .Y(n6569) );
XNOR2X4TS U8119 ( .A(n928), .B(n1702), .Y(n3641) );
NAND2BX4TS U8120 ( .AN(n2448), .B(n3432), .Y(n6039) );
OAI2BB1X4TS U8121 ( .A0N(n6360), .A1N(n6361), .B0(n2664), .Y(n6353) );
XOR2X4TS U8122 ( .A(n2665), .B(n6359), .Y(n6369) );
XOR2X4TS U8123 ( .A(n6361), .B(n6360), .Y(n2665) );
NAND2X8TS U8124 ( .A(n2667), .B(n9291), .Y(n3167) );
XOR2X4TS U8125 ( .A(n2668), .B(n2322), .Y(n9890) );
XOR2X4TS U8126 ( .A(n9888), .B(n9889), .Y(n2668) );
OR2X4TS U8127 ( .A(n1286), .B(DP_OP_168J26_122_4811_n8499), .Y(n3991) );
BUFX20TS U8128 ( .A(n2767), .Y(n2721) );
XOR2X4TS U8129 ( .A(n2860), .B(n1887), .Y(n3697) );
OAI22X4TS U8130 ( .A0(n8023), .A1(n5306), .B0(n7281), .B1(n1900), .Y(n8016)
);
XNOR2X4TS U8131 ( .A(n11766), .B(n1629), .Y(n3774) );
NAND2X4TS U8132 ( .A(n1394), .B(n3602), .Y(n3605) );
OAI22X4TS U8133 ( .A0(n2671), .A1(n2106), .B0(n4970), .B1(n1864), .Y(n3265)
);
XOR2X4TS U8134 ( .A(n2860), .B(n1809), .Y(n2671) );
XNOR2X4TS U8135 ( .A(n8894), .B(n2037), .Y(n4298) );
NAND2X2TS U8136 ( .A(n4073), .B(n11732), .Y(n3624) );
XOR2X4TS U8137 ( .A(n2911), .B(n5032), .Y(n2996) );
ADDFHX4TS U8138 ( .A(n5520), .B(n5521), .CI(n5522), .CO(n5510), .S(n5836) );
XOR2X4TS U8139 ( .A(n3218), .B(n2287), .Y(n5991) );
XNOR2X4TS U8140 ( .A(n5174), .B(n1885), .Y(n4835) );
OA21X4TS U8141 ( .A0(n8351), .A1(n9306), .B0(n8352), .Y(n2858) );
NAND2BX4TS U8142 ( .AN(n5666), .B(n1804), .Y(n6067) );
OAI22X4TS U8143 ( .A0(n2855), .A1(n5340), .B0(n1385), .B1(n1864), .Y(n4223)
);
ADDFHX4TS U8144 ( .A(n4989), .B(n4990), .CI(n4988), .CO(n5020), .S(n5001) );
OAI22X4TS U8145 ( .A0(n4992), .A1(n5340), .B0(n4963), .B1(n1943), .Y(n5017)
);
XNOR2X4TS U8146 ( .A(n2079), .B(n1729), .Y(n4992) );
AOI21X2TS U8147 ( .A0(n9040), .A1(n9039), .B0(n9038), .Y(n10076) );
XOR2X4TS U8148 ( .A(n2674), .B(n4820), .Y(DP_OP_168J26_122_4811_n1080) );
XOR2X4TS U8149 ( .A(n4819), .B(n4821), .Y(n2674) );
XOR2X4TS U8150 ( .A(n2675), .B(n8317), .Y(n8752) );
XOR2X4TS U8151 ( .A(n8319), .B(n8318), .Y(n2675) );
ADDFHX4TS U8152 ( .A(n4889), .B(n4891), .CI(n4890), .CO(n4885), .S(n4930) );
XNOR2X4TS U8153 ( .A(n8911), .B(n1926), .Y(n4644) );
ADDFX2TS U8154 ( .A(n4729), .B(n4728), .CI(n4730), .CO(n4769), .S(n4721) );
XNOR2X4TS U8155 ( .A(n8620), .B(n2058), .Y(n4703) );
OAI22X4TS U8156 ( .A0(n5285), .A1(n2106), .B0(n5339), .B1(n1864), .Y(n5311)
);
XOR2X4TS U8157 ( .A(n2860), .B(n7279), .Y(n5339) );
NAND2X8TS U8158 ( .A(n3163), .B(n3109), .Y(n2859) );
NAND2X4TS U8159 ( .A(n3208), .B(n3163), .Y(n3207) );
OAI21X4TS U8160 ( .A0(n10023), .A1(n10033), .B0(n10024), .Y(
DP_OP_168J26_122_4811_n614) );
NAND2X8TS U8161 ( .A(n7320), .B(n7319), .Y(n10029) );
XOR2X4TS U8162 ( .A(n2705), .B(n3383), .Y(n3387) );
OAI21X4TS U8163 ( .A0(n8232), .A1(n2685), .B0(n2684), .Y(n7150) );
NAND2BX4TS U8164 ( .AN(n7159), .B(n7156), .Y(n2684) );
OAI2BB1X4TS U8165 ( .A0N(n5130), .A1N(n5129), .B0(n2688), .Y(n6445) );
OAI21X4TS U8166 ( .A0(n5130), .A1(n5129), .B0(n5128), .Y(n2688) );
XNOR2X4TS U8167 ( .A(n2689), .B(n5128), .Y(n2686) );
XOR2X4TS U8168 ( .A(n5129), .B(n5130), .Y(n2689) );
XOR2X4TS U8169 ( .A(n1606), .B(n7270), .Y(n7085) );
NOR2X8TS U8170 ( .A(n10777), .B(n2922), .Y(n2690) );
NAND2X8TS U8171 ( .A(n3069), .B(n3275), .Y(n2767) );
OAI21X4TS U8172 ( .A0(n10990), .A1(n10992), .B0(n10993), .Y(n9262) );
AOI21X4TS U8173 ( .A0(n10982), .A1(n10985), .B0(n2695), .Y(n10990) );
NAND2X4TS U8174 ( .A(n5819), .B(n2837), .Y(n10985) );
NOR2X4TS U8175 ( .A(n4859), .B(n8020), .Y(n2697) );
NOR2X8TS U8176 ( .A(n2697), .B(n2696), .Y(n3040) );
XOR2X4TS U8177 ( .A(n2699), .B(n1439), .Y(Sgf_operation_ODD1_Q_right[48]) );
XNOR2X4TS U8178 ( .A(n2703), .B(n10058), .Y(Sgf_operation_ODD1_Q_right[47])
);
OAI21X4TS U8179 ( .A0(n1468), .A1(n2806), .B0(n2704), .Y(n2703) );
AOI21X4TS U8180 ( .A0(n10092), .A1(n2808), .B0(n10055), .Y(n2704) );
XNOR2X4TS U8181 ( .A(n1262), .B(DP_OP_168J26_122_4811_n8504), .Y(n2705) );
OAI2BB1X4TS U8182 ( .A0N(n1417), .A1N(n5219), .B0(n2708), .Y(n5260) );
XOR2X4TS U8183 ( .A(n5219), .B(n2709), .Y(n5229) );
XOR2X4TS U8184 ( .A(n2710), .B(n5220), .Y(n2709) );
OAI22X4TS U8185 ( .A0(n5177), .A1(n5331), .B0(n1898), .B1(n5222), .Y(n2710)
);
OAI22X4TS U8186 ( .A0(n5848), .A1(n2713), .B0(n2712), .B1(n6373), .Y(n8603)
);
OAI22X2TS U8187 ( .A0(n8617), .A1(n2446), .B0(n8618), .B1(n2098), .Y(n8624)
);
OAI21X4TS U8188 ( .A0(n5515), .A1(n1022), .B0(n2716), .Y(n6895) );
NAND2BX4TS U8189 ( .AN(n6774), .B(n2717), .Y(n2716) );
OAI22X4TS U8190 ( .A0(n5516), .A1(n2099), .B0(n5550), .B1(n1961), .Y(n5523)
);
OAI22X4TS U8191 ( .A0(n8618), .A1(n1961), .B0(n2097), .B1(n8440), .Y(n8607)
);
OAI22X4TS U8192 ( .A0(n5551), .A1(n2098), .B0(n6885), .B1(n8440), .Y(n8490)
);
OAI21X4TS U8193 ( .A0(n2099), .A1(n3924), .B0(n2718), .Y(n4057) );
OAI22X4TS U8194 ( .A0(n4344), .A1(n2446), .B0(n2098), .B1(n4345), .Y(n4386)
);
XOR2X4TS U8195 ( .A(n3068), .B(n2844), .Y(n5841) );
OAI21X4TS U8196 ( .A0(n9487), .A1(n9630), .B0(n9488), .Y(n8188) );
NAND2X8TS U8197 ( .A(n2720), .B(n2861), .Y(n3042) );
NOR2X8TS U8198 ( .A(n5476), .B(n5477), .Y(n9487) );
XNOR2X4TS U8199 ( .A(n932), .B(n2527), .Y(n3698) );
AOI21X4TS U8200 ( .A0(n10092), .A1(n10073), .B0(n10079), .Y(n2723) );
XNOR2X4TS U8201 ( .A(n2722), .B(n9304), .Y(Sgf_operation_ODD1_Q_right[49])
);
OAI21X4TS U8202 ( .A0(n1468), .A1(n9301), .B0(n2723), .Y(n2722) );
OAI22X4TS U8203 ( .A0(n5325), .A1(n4910), .B0(n4942), .B1(n2025), .Y(n4939)
);
XOR2X4TS U8204 ( .A(n2406), .B(n11736), .Y(n4942) );
XOR2X4TS U8205 ( .A(n2406), .B(n883), .Y(n4910) );
OAI2BB1X4TS U8206 ( .A0N(n4925), .A1N(n4923), .B0(n2724), .Y(n4899) );
OAI21X4TS U8207 ( .A0(n4923), .A1(n4925), .B0(n4924), .Y(n2724) );
NOR2X8TS U8208 ( .A(n8324), .B(n8323), .Y(n9986) );
OAI2BB1X4TS U8209 ( .A0N(n2555), .A1N(n1736), .B0(n2726), .Y(n8750) );
OAI21X4TS U8210 ( .A0(n2555), .A1(n1736), .B0(n8317), .Y(n2726) );
OAI22X4TS U8211 ( .A0(n5983), .A1(n1962), .B0(n6481), .B1(n2109), .Y(n6509)
);
XNOR2X4TS U8212 ( .A(n8911), .B(n2034), .Y(n5983) );
NOR2X8TS U8213 ( .A(n9264), .B(n11001), .Y(n5362) );
XOR2X4TS U8214 ( .A(n1639), .B(n2730), .Y(n2731) );
XOR2X4TS U8215 ( .A(n879), .B(n5256), .Y(n5142) );
OAI21X4TS U8216 ( .A0(n9951), .A1(n1848), .B0(n9950), .Y(n3180) );
NAND2X8TS U8217 ( .A(n2738), .B(n2737), .Y(n4390) );
OAI2BB1X4TS U8218 ( .A0N(n2740), .A1N(n2739), .B0(n4053), .Y(n2738) );
XOR2X4TS U8219 ( .A(n5473), .B(n2745), .Y(n4417) );
XOR2X4TS U8220 ( .A(n2746), .B(n4336), .Y(n2745) );
OAI2BB1X4TS U8221 ( .A0N(n5206), .A1N(n1639), .B0(n2747), .Y(n5735) );
XOR2X4TS U8222 ( .A(n2749), .B(n9883), .Y(n9892) );
XOR2X4TS U8223 ( .A(n9885), .B(n9884), .Y(n2749) );
OAI22X4TS U8224 ( .A0(n8011), .A1(n4227), .B0(n2046), .B1(n3853), .Y(n4219)
);
XOR2X4TS U8225 ( .A(n883), .B(n2094), .Y(n3853) );
XOR2X4TS U8226 ( .A(n2390), .B(n2093), .Y(n4227) );
OAI22X4TS U8227 ( .A0(n4591), .A1(n2027), .B0(n1989), .B1(n4675), .Y(n4674)
);
XOR2X4TS U8228 ( .A(n5256), .B(n1606), .Y(n4675) );
XOR2X4TS U8229 ( .A(n5278), .B(n883), .Y(n5057) );
XOR2X4TS U8230 ( .A(n2752), .B(n5087), .Y(n6768) );
XOR2X4TS U8231 ( .A(n5088), .B(n5089), .Y(n2752) );
AOI21X4TS U8232 ( .A0(n10092), .A1(n9041), .B0(n2906), .Y(n2754) );
XNOR2X4TS U8233 ( .A(n2756), .B(n4626), .Y(n4751) );
XNOR2X4TS U8234 ( .A(n4627), .B(n4628), .Y(n2756) );
OAI22X4TS U8235 ( .A0(n2107), .A1(n3663), .B0(n1865), .B1(n3728), .Y(n3740)
);
XNOR2X4TS U8236 ( .A(n2078), .B(n1730), .Y(n3728) );
AND2X8TS U8237 ( .A(n1226), .B(DP_OP_168J26_122_4811_n8200), .Y(n2757) );
NAND2X8TS U8238 ( .A(n8182), .B(n8187), .Y(n8797) );
INVX16TS U8239 ( .A(n2758), .Y(n10088) );
NOR2X8TS U8240 ( .A(n8185), .B(n8181), .Y(n8187) );
NOR2X8TS U8241 ( .A(n1300), .B(n2557), .Y(n8185) );
NOR2X8TS U8242 ( .A(n9629), .B(n9487), .Y(n8182) );
OAI22X4TS U8243 ( .A0(n1898), .A1(n3685), .B0(n2111), .B1(n3802), .Y(n3796)
);
XOR2X4TS U8244 ( .A(n2483), .B(n3202), .Y(n3802) );
NAND2BX4TS U8245 ( .AN(n2687), .B(n6552), .Y(n2763) );
XOR2X4TS U8246 ( .A(n2765), .B(n6551), .Y(n6598) );
NOR2X8TS U8247 ( .A(n6718), .B(n6717), .Y(n6678) );
XOR2X4TS U8248 ( .A(n4954), .B(n4955), .Y(n2783) );
OAI2BB1X4TS U8249 ( .A0N(n2766), .A1N(n1430), .B0(n2768), .Y(
Sgf_operation_ODD1_Q_right[46]) );
XOR2X4TS U8250 ( .A(n2785), .B(n5127), .Y(n2771) );
NAND2X8TS U8251 ( .A(n2773), .B(n2772), .Y(n4274) );
OAI22X4TS U8252 ( .A0(n2066), .A1(n8005), .B0(n4922), .B1(n1880), .Y(n2786)
);
OAI22X4TS U8253 ( .A0(n887), .A1(DP_OP_168J26_122_4811_n6615), .B0(n975),
.B1(n3679), .Y(n3703) );
OAI22X4TS U8254 ( .A0(n8006), .A1(n1880), .B0(n5318), .B1(n4669), .Y(n8115)
);
OAI22X4TS U8255 ( .A0(n3666), .A1(n1880), .B0(n975), .B1(n887), .Y(n3738) );
NOR2X8TS U8256 ( .A(n7009), .B(n7008), .Y(n2781) );
OAI2BB1X4TS U8257 ( .A0N(n6726), .A1N(n6725), .B0(n2782), .Y(n8294) );
OAI21X4TS U8258 ( .A0(n6725), .A1(n6726), .B0(n6727), .Y(n2782) );
XOR2X4TS U8259 ( .A(n2783), .B(n4953), .Y(n2785) );
OAI2BB1X4TS U8260 ( .A0N(n2579), .A1N(n2785), .B0(n2784), .Y(n6439) );
OAI21X4TS U8261 ( .A0(n2579), .A1(n2785), .B0(n5126), .Y(n2784) );
XOR2X4TS U8262 ( .A(n2786), .B(n4962), .Y(n5113) );
OAI21X4TS U8263 ( .A0(n4225), .A1(n975), .B0(n2789), .Y(n4233) );
XOR2X4TS U8264 ( .A(n2014), .B(n883), .Y(n4838) );
OAI21X4TS U8265 ( .A0(n11009), .A1(n8365), .B0(n2795), .Y(n3201) );
AOI21X4TS U8266 ( .A0(n1665), .A1(n8364), .B0(n8363), .Y(n2795) );
XOR2X4TS U8267 ( .A(n6698), .B(n2796), .Y(n6968) );
NOR2X4TS U8268 ( .A(n9589), .B(n2797), .Y(add_x_19_n702) );
XOR2X4TS U8269 ( .A(n2798), .B(n3839), .Y(n4013) );
AOI21X1TS U8270 ( .A0(n10039), .A1(n2800), .B0(n10038), .Y(
DP_OP_168J26_122_4811_n662) );
INVX6TS U8271 ( .A(n2802), .Y(n4069) );
XOR2X4TS U8272 ( .A(n1286), .B(DP_OP_168J26_122_4811_n8499), .Y(n2802) );
XNOR2X4TS U8273 ( .A(n2015), .B(n2430), .Y(n5052) );
XNOR2X4TS U8274 ( .A(n2015), .B(n1870), .Y(n5054) );
XNOR2X4TS U8275 ( .A(n2015), .B(n1034), .Y(n4971) );
XNOR2X4TS U8276 ( .A(n1858), .B(n2015), .Y(n5034) );
XNOR2X4TS U8277 ( .A(n2634), .B(n2015), .Y(n4994) );
XOR2X4TS U8278 ( .A(n1324), .B(n1885), .Y(n5053) );
XOR2X4TS U8279 ( .A(n1221), .B(n5276), .Y(n4995) );
XOR2X4TS U8280 ( .A(n3078), .B(n5276), .Y(n4972) );
NAND2X2TS U8281 ( .A(n2808), .B(n10088), .Y(n2806) );
OAI21X4TS U8282 ( .A0(n8270), .A1(n8271), .B0(n8269), .Y(n2809) );
XOR2X4TS U8283 ( .A(n2860), .B(n2653), .Y(n4538) );
XOR2X4TS U8284 ( .A(n2860), .B(n7369), .Y(n3228) );
OAI22X4TS U8285 ( .A0(n8933), .A1(n2814), .B0(n8577), .B1(n5489), .Y(n5534)
);
XNOR2X4TS U8286 ( .A(n2566), .B(n2079), .Y(n2855) );
AOI21X4TS U8287 ( .A0(n1665), .A1(n9286), .B0(n2820), .Y(n2819) );
OAI2BB1X4TS U8288 ( .A0N(n5261), .A1N(n5262), .B0(n2822), .Y(n5352) );
OAI21X4TS U8289 ( .A0(n5261), .A1(n5262), .B0(n5263), .Y(n2822) );
NAND2X4TS U8290 ( .A(n1288), .B(n8658), .Y(n2823) );
XNOR2X4TS U8291 ( .A(n2409), .B(n2079), .Y(n5238) );
XOR2X4TS U8292 ( .A(n2826), .B(n8800), .Y(Sgf_operation_ODD1_Q_right[37]) );
AOI21X4TS U8293 ( .A0(n2721), .A1(n1009), .B0(n10065), .Y(n2826) );
XOR2X4TS U8294 ( .A(n1606), .B(n1831), .Y(n2828) );
OAI21X4TS U8295 ( .A0(n1468), .A1(n1013), .B0(n8717), .Y(n8721) );
XOR2X4TS U8296 ( .A(n2830), .B(n4284), .Y(n4389) );
XOR2X4TS U8297 ( .A(n4286), .B(n4285), .Y(n2830) );
OAI21X4TS U8298 ( .A0(n2832), .A1(n5472), .B0(n3244), .Y(n4414) );
XOR2X4TS U8299 ( .A(n2913), .B(n2255), .Y(n5472) );
XOR2X4TS U8300 ( .A(n5447), .B(n5448), .Y(n2836) );
XOR2X4TS U8301 ( .A(n2390), .B(n7273), .Y(n5211) );
XOR2X4TS U8302 ( .A(n7024), .B(n1729), .Y(n5148) );
XOR2X4TS U8303 ( .A(n2838), .B(n5207), .Y(n2837) );
XOR2X4TS U8304 ( .A(n2839), .B(n1438), .Y(Sgf_operation_ODD1_Q_right[50]) );
OAI21X4TS U8305 ( .A0(n1468), .A1(n9297), .B0(n9296), .Y(n2839) );
OAI2BB1X4TS U8306 ( .A0N(n5447), .A1N(n947), .B0(n2840), .Y(n5460) );
OAI22X4TS U8307 ( .A0(n5272), .A1(n1964), .B0(n7993), .B1(n2841), .Y(n5298)
);
OAI22X4TS U8308 ( .A0(n3816), .A1(n1951), .B0(n1822), .B1(n2842), .Y(n3846)
);
XOR2X4TS U8309 ( .A(n2390), .B(n7353), .Y(n2842) );
XOR2X4TS U8310 ( .A(n2843), .B(n1437), .Y(Sgf_operation_ODD1_Q_right[44]) );
OAI22X4TS U8311 ( .A0(n5166), .A1(n5309), .B0(n1988), .B1(n2845), .Y(n5220)
);
OAI22X4TS U8312 ( .A0(n5257), .A1(n8020), .B0(n5309), .B1(n2845), .Y(n5269)
);
XNOR2X4TS U8313 ( .A(n1884), .B(n7277), .Y(n2845) );
XOR2X4TS U8314 ( .A(n2328), .B(n11782), .Y(n5257) );
XOR2X4TS U8315 ( .A(n3085), .B(n1608), .Y(n3801) );
OAI22X4TS U8316 ( .A0(n5590), .A1(n6087), .B0(n1938), .B1(n2848), .Y(n5718)
);
OAI22X4TS U8317 ( .A0(n5573), .A1(n1939), .B0(n2029), .B1(n2848), .Y(n5596)
);
XOR2X4TS U8318 ( .A(n1807), .B(n1258), .Y(n2848) );
NAND2X8TS U8319 ( .A(n6873), .B(n6872), .Y(n9632) );
OAI2BB1X4TS U8320 ( .A0N(n6784), .A1N(n2852), .B0(n2851), .Y(n6786) );
OAI21X4TS U8321 ( .A0(n6784), .A1(n2852), .B0(n6783), .Y(n2851) );
XNOR2X4TS U8322 ( .A(n2853), .B(n6784), .Y(n6815) );
XNOR2X4TS U8323 ( .A(n2672), .B(n1869), .Y(n6058) );
XNOR2X4TS U8324 ( .A(n1860), .B(n1808), .Y(n6165) );
XOR2X4TS U8325 ( .A(n2448), .B(n11779), .Y(n6077) );
XOR2X4TS U8326 ( .A(n2328), .B(n3078), .Y(n5308) );
NAND2X4TS U8327 ( .A(n2175), .B(n2610), .Y(n9326) );
XOR2X4TS U8328 ( .A(n1465), .B(n1373), .Y(Sgf_operation_ODD1_Q_right[33]) );
XOR2X4TS U8329 ( .A(n2857), .B(n1374), .Y(n9589) );
XOR2X4TS U8330 ( .A(n2864), .B(n1448), .Y(Sgf_operation_ODD1_Q_right[51]) );
AOI21X4TS U8331 ( .A0(n10092), .A1(n2869), .B0(n2868), .Y(n2867) );
OAI21X4TS U8332 ( .A0(n10054), .A1(n8239), .B0(n10056), .Y(n2868) );
OAI21X4TS U8333 ( .A0(n10094), .A1(n10089), .B0(n10095), .Y(n8765) );
OAI21X4TS U8334 ( .A0(n3746), .A1(n3745), .B0(n3744), .Y(n2882) );
OAI2BB1X4TS U8335 ( .A0N(n1761), .A1N(n1777), .B0(n9896), .Y(n2887) );
OAI21X4TS U8336 ( .A0(n1468), .A1(n8434), .B0(n8433), .Y(n8438) );
XOR2X4TS U8337 ( .A(n4249), .B(n4248), .Y(n2893) );
XOR2X4TS U8338 ( .A(n2894), .B(n3271), .Y(Sgf_operation_ODD1_Q_right[53]) );
OAI21X4TS U8339 ( .A0(n10081), .A1(n1463), .B0(n10080), .Y(n2894) );
XOR2X4TS U8340 ( .A(n2895), .B(n5349), .Y(n5354) );
OAI22X4TS U8341 ( .A0(n2900), .A1(n5345), .B0(n5344), .B1(n5343), .Y(n5370)
);
XOR2X4TS U8342 ( .A(n8898), .B(n6433), .Y(n4705) );
XOR2X4TS U8343 ( .A(n2905), .B(n9045), .Y(Sgf_operation_ODD1_Q_right[52]) );
OAI2BB1X4TS U8344 ( .A0N(n9926), .A1N(n9925), .B0(n2907), .Y(n9949) );
XOR2X4TS U8345 ( .A(n2909), .B(n4817), .Y(n9947) );
NAND2X4TS U8346 ( .A(n6644), .B(n2996), .Y(n10631) );
XOR2X4TS U8347 ( .A(n5033), .B(n5031), .Y(n2911) );
OAI22X4TS U8348 ( .A0(n2096), .A1(n4972), .B0(n4995), .B1(n11758), .Y(n4985)
);
OAI21X4TS U8349 ( .A0(n4015), .A1(n4014), .B0(n4013), .Y(n2912) );
XOR2X4TS U8350 ( .A(n2596), .B(n2914), .Y(n2913) );
OAI22X4TS U8351 ( .A0(n3692), .A1(n1607), .B0(n2115), .B1(n2915), .Y(n3687)
);
XOR2X4TS U8352 ( .A(n1608), .B(n1221), .Y(n2915) );
OAI22X4TS U8353 ( .A0(n2111), .A1(n4941), .B0(n5058), .B1(n4918), .Y(n4961)
);
XOR2X4TS U8354 ( .A(n1979), .B(n3078), .Y(n4941) );
AOI21X4TS U8355 ( .A0(n9637), .A1(n9635), .B0(n2916), .Y(add_x_19_n774) );
OR2X8TS U8356 ( .A(n2917), .B(n9342), .Y(n9635) );
XNOR2X4TS U8357 ( .A(n2918), .B(n9328), .Y(n2917) );
OAI21X4TS U8358 ( .A0(n11009), .A1(n9324), .B0(n9323), .Y(n2918) );
NAND2X8TS U8359 ( .A(n10792), .B(n10789), .Y(n2922) );
NOR2X1TS U8360 ( .A(n2923), .B(n5131), .Y(n10776) );
XNOR2X4TS U8361 ( .A(n2078), .B(n882), .Y(n4963) );
ACHCINX4TS U8362 ( .CIN(n6542), .A(n6582), .B(n6581), .CO(n6585) );
XOR2X4TS U8363 ( .A(n6542), .B(n2926), .Y(n6614) );
XNOR2X4TS U8364 ( .A(n6581), .B(n6582), .Y(n2926) );
XOR2X4TS U8365 ( .A(n1831), .B(n1645), .Y(n2927) );
XNOR2X4TS U8366 ( .A(n2068), .B(n750), .Y(n4840) );
OAI2BB1X4TS U8367 ( .A0N(n7092), .A1N(n2929), .B0(n2928), .Y(n7141) );
NOR2X8TS U8368 ( .A(n3196), .B(n8214), .Y(n9563) );
XNOR2X4TS U8369 ( .A(n2935), .B(n6166), .Y(n6205) );
XNOR2X4TS U8370 ( .A(n6167), .B(n6168), .Y(n2935) );
INVX16TS U8371 ( .A(n2937), .Y(n8889) );
XNOR2X4TS U8372 ( .A(n2938), .B(n1376), .Y(n2937) );
NAND2X4TS U8373 ( .A(n11778), .B(n9985), .Y(DP_OP_168J26_122_4811_n106) );
OAI2BB1X4TS U8374 ( .A0N(n8136), .A1N(n837), .B0(n2939), .Y(n9974) );
XOR2X4TS U8375 ( .A(n8226), .B(n2942), .Y(n2941) );
XNOR2X4TS U8376 ( .A(n8071), .B(n8070), .Y(n2942) );
NOR2X8TS U8377 ( .A(n2946), .B(n2945), .Y(n3138) );
NOR2BX4TS U8378 ( .AN(n1413), .B(n8019), .Y(n2945) );
OAI22X4TS U8379 ( .A0(n1969), .A1(n8630), .B0(n2949), .B1(n8629), .Y(n9795)
);
OAI2BB1X4TS U8380 ( .A0N(n5453), .A1N(n1676), .B0(n2956), .Y(n5438) );
OAI2BB1X4TS U8381 ( .A0N(n7164), .A1N(n7165), .B0(n2958), .Y(n7191) );
OAI21X4TS U8382 ( .A0(n7165), .A1(n7164), .B0(n7163), .Y(n2958) );
XOR2X4TS U8383 ( .A(n7163), .B(n7164), .Y(n2959) );
OAI21X4TS U8384 ( .A0(n7137), .A1(n2962), .B0(n7136), .Y(n2961) );
XNOR2X4TS U8385 ( .A(n2963), .B(n7136), .Y(n7146) );
XOR2X4TS U8386 ( .A(n2092), .B(n2931), .Y(n7140) );
XNOR2X4TS U8387 ( .A(n2233), .B(n1928), .Y(n4632) );
OAI2BB1X4TS U8388 ( .A0N(n8205), .A1N(n8206), .B0(n2973), .Y(n8207) );
OAI22X4TS U8389 ( .A0(n6776), .A1(n2097), .B0(n6885), .B1(n2976), .Y(n6894)
);
XNOR2X4TS U8390 ( .A(n3566), .B(DP_OP_168J26_122_4811_n3223), .Y(n5938) );
OAI21X4TS U8391 ( .A0(DP_OP_168J26_122_4811_n8504), .A1(n1262), .B0(n2483),
.Y(n2978) );
XOR2X4TS U8392 ( .A(n2983), .B(n6687), .Y(n6964) );
OAI22X4TS U8393 ( .A0(n6883), .A1(n6642), .B0(n6638), .B1(n8574), .Y(n2984)
);
AND2X8TS U8394 ( .A(n5503), .B(n3286), .Y(n2979) );
XNOR2X4TS U8395 ( .A(n3565), .B(n3567), .Y(n2985) );
XOR2X4TS U8396 ( .A(DP_OP_168J26_122_4811_n8506), .B(
DP_OP_168J26_122_4811_n8533), .Y(n3567) );
OAI2BB1X4TS U8397 ( .A0N(n6662), .A1N(n2988), .B0(n2987), .Y(n6676) );
NAND2X4TS U8398 ( .A(n7006), .B(n7007), .Y(n10098) );
NOR2X8TS U8399 ( .A(n7006), .B(n7007), .Y(n2989) );
OAI22X4TS U8400 ( .A0(n2999), .A1(n5302), .B0(n1924), .B1(n2993), .Y(n5003)
);
NOR2BX4TS U8401 ( .AN(n1010), .B(n6693), .Y(n2995) );
NAND2X2TS U8402 ( .A(n6944), .B(n6943), .Y(n2997) );
XOR2X4TS U8403 ( .A(n2998), .B(n6942), .Y(n7000) );
XOR2X4TS U8404 ( .A(n6944), .B(n6943), .Y(n2998) );
OAI22X2TS U8405 ( .A0(n5006), .A1(n2088), .B0(n1941), .B1(n2999), .Y(n5082)
);
XOR2X4TS U8406 ( .A(n2590), .B(n11769), .Y(n2999) );
OAI2BB1X4TS U8407 ( .A0N(n6882), .A1N(n3001), .B0(n3000), .Y(n6948) );
OAI21X4TS U8408 ( .A0(n6882), .A1(n3001), .B0(n6881), .Y(n3000) );
INVX12TS U8409 ( .A(n2290), .Y(n3001) );
XOR2X4TS U8410 ( .A(n3076), .B(n3003), .Y(n9851) );
XNOR2X4TS U8411 ( .A(n3011), .B(n3015), .Y(n5135) );
OAI2BB1X4TS U8412 ( .A0N(n3013), .A1N(n5137), .B0(n3012), .Y(n5162) );
XNOR2X4TS U8413 ( .A(n2634), .B(n2078), .Y(n5156) );
XNOR2X4TS U8414 ( .A(n2079), .B(n750), .Y(n4857) );
NAND2X8TS U8415 ( .A(n3018), .B(n993), .Y(n3017) );
XOR2X4TS U8416 ( .A(n3297), .B(n5254), .Y(n4858) );
NAND2X4TS U8417 ( .A(n8374), .B(n1363), .Y(n9292) );
INVX2TS U8418 ( .A(n9302), .Y(n9039) );
XNOR2X4TS U8419 ( .A(n2590), .B(n882), .Y(n4979) );
NAND2X1TS U8420 ( .A(n6875), .B(n6874), .Y(n9492) );
ADDFHX4TS U8421 ( .A(n6517), .B(n6516), .CI(n6515), .CO(n8279), .S(n6526) );
ADDFHX4TS U8422 ( .A(n9083), .B(n9082), .CI(n9081), .CO(n9113), .S(n9102) );
ADDFHX4TS U8423 ( .A(n4616), .B(n4615), .CI(n4614), .CO(n4655), .S(n4588) );
ADDFHX4TS U8424 ( .A(n5843), .B(n5844), .CI(n5842), .CO(n8452), .S(n5737) );
OAI22X4TS U8425 ( .A0(n8643), .A1(n1871), .B0(n8641), .B1(n6791), .Y(n6821)
);
OAI21X4TS U8426 ( .A0(DP_OP_168J26_122_4811_n8537), .A1(
DP_OP_168J26_122_4811_n8510), .B0(n931), .Y(n3576) );
OAI21X4TS U8427 ( .A0(n10622), .A1(n5092), .B0(n5091), .Y(n10629) );
ADDFHX4TS U8428 ( .A(n3738), .B(n3740), .CI(n3739), .CO(n3955), .S(n3748) );
NAND2X4TS U8429 ( .A(n3262), .B(n3261), .Y(n6974) );
NOR2X4TS U8430 ( .A(n9811), .B(n9812), .Y(n3123) );
ADDFHX4TS U8431 ( .A(n9781), .B(n9782), .CI(n9780), .CO(n9792), .S(n9852) );
ADDFHX4TS U8432 ( .A(n5241), .B(n5239), .CI(n5240), .CO(n5261), .S(n5244) );
OAI22X4TS U8433 ( .A0(n1820), .A1(n4823), .B0(n5304), .B1(n4855), .Y(n4842)
);
INVX8TS U8434 ( .A(n8215), .Y(n8905) );
OAI21X4TS U8435 ( .A0(n6404), .A1(n3020), .B0(n3019), .Y(n6522) );
NAND2BX4TS U8436 ( .AN(n8680), .B(n1233), .Y(n3026) );
XOR2X4TS U8437 ( .A(n5276), .B(n3202), .Y(n5344) );
XNOR2X4TS U8438 ( .A(n3033), .B(n5533), .Y(n5977) );
XNOR2X4TS U8439 ( .A(n2091), .B(n882), .Y(n3816) );
XOR2X4TS U8440 ( .A(n7024), .B(n882), .Y(n5169) );
NAND2X4TS U8441 ( .A(n5201), .B(n2273), .Y(n3035) );
OAI21X4TS U8442 ( .A0(n5201), .A1(n2273), .B0(n5199), .Y(n3036) );
OAI22X4TS U8443 ( .A0(n4831), .A1(n2142), .B0(n1889), .B1(n4861), .Y(n3041)
);
AOI21X4TS U8444 ( .A0(n10092), .A1(n9563), .B0(n9564), .Y(n3044) );
OAI22X4TS U8445 ( .A0(n3673), .A1(n7997), .B0(n1950), .B1(n3045), .Y(n3681)
);
XNOR2X4TS U8446 ( .A(n1885), .B(n2091), .Y(n3045) );
XOR2X4TS U8447 ( .A(n2092), .B(n3085), .Y(n3669) );
OAI21X4TS U8448 ( .A0(n6953), .A1(n6951), .B0(n6952), .Y(n3262) );
OAI22X4TS U8449 ( .A0(n3253), .A1(n2071), .B0(n1901), .B1(n3046), .Y(n5068)
);
OAI2BB1X4TS U8450 ( .A0N(n5089), .A1N(n5088), .B0(n3048), .Y(n6891) );
OAI21X4TS U8451 ( .A0(n5088), .A1(n5089), .B0(n5087), .Y(n3048) );
OAI22X4TS U8452 ( .A0(n3669), .A1(n2411), .B0(n1923), .B1(n3961), .Y(n3978)
);
XOR2X4TS U8453 ( .A(n1832), .B(n859), .Y(n3253) );
XOR2X4TS U8454 ( .A(n3051), .B(n6750), .Y(n3050) );
XOR2X4TS U8455 ( .A(n6743), .B(n6747), .Y(n3052) );
OAI21X4TS U8456 ( .A0(n2003), .A1(n2647), .B0(n3053), .Y(n6747) );
XOR2X4TS U8457 ( .A(n3297), .B(n7270), .Y(n5319) );
OAI21X1TS U8458 ( .A0(n3278), .A1(n8372), .B0(n3054), .Y(n3061) );
NAND2BX4TS U8459 ( .AN(n6807), .B(n3059), .Y(n3058) );
XNOR2X4TS U8460 ( .A(n7277), .B(DP_OP_168J26_122_4811_n8473), .Y(n4837) );
XOR2X4TS U8461 ( .A(n11767), .B(n2147), .Y(n4226) );
NOR2BX4TS U8462 ( .AN(n8360), .B(n3063), .Y(n3062) );
NOR2BX4TS U8463 ( .AN(n3064), .B(n6853), .Y(n3063) );
NOR2X4TS U8464 ( .A(n9629), .B(n3069), .Y(n3224) );
XOR2X4TS U8465 ( .A(n5278), .B(n800), .Y(n4976) );
XOR2X4TS U8466 ( .A(n3071), .B(n4053), .Y(n4273) );
XOR2X4TS U8467 ( .A(n3072), .B(n1388), .Y(n9585) );
AND2X8TS U8468 ( .A(n9286), .B(n9284), .Y(n3073) );
OAI22X4TS U8469 ( .A0(n3077), .A1(n2046), .B0(n8011), .B1(n3074), .Y(n3736)
);
NAND2BX4TS U8470 ( .AN(n3081), .B(n5188), .Y(n3079) );
OAI2BB1X4TS U8471 ( .A0N(n3082), .A1N(n3081), .B0(n5187), .Y(n3080) );
XOR2X4TS U8472 ( .A(n5189), .B(n5188), .Y(n3083) );
OAI22X4TS U8473 ( .A0(n3086), .A1(n5325), .B0(n2024), .B1(n3084), .Y(n5154)
);
OAI22X4TS U8474 ( .A0(n4835), .A1(n2025), .B0(n1991), .B1(n3084), .Y(n4848)
);
OAI22X4TS U8475 ( .A0(n3132), .A1(n1991), .B0(n2024), .B1(n3086), .Y(n5172)
);
INVX4TS U8476 ( .A(n3091), .Y(n3090) );
XOR2X4TS U8477 ( .A(n3088), .B(n3090), .Y(n5439) );
OAI2BB1X4TS U8478 ( .A0N(n3090), .A1N(n5409), .B0(n3089), .Y(n5405) );
OAI2BB1X4TS U8479 ( .A0N(n3087), .A1N(n3091), .B0(n5408), .Y(n3089) );
XNOR2X4TS U8480 ( .A(n2092), .B(DP_OP_168J26_122_4811_n8473), .Y(n4028) );
NAND2X8TS U8481 ( .A(n1015), .B(n10041), .Y(DP_OP_168J26_122_4811_n637) );
AO22X4TS U8482 ( .A0(n6588), .A1(n3092), .B0(n6589), .B1(n6590), .Y(n6592)
);
XOR2X4TS U8483 ( .A(n6589), .B(n6590), .Y(n3093) );
XNOR2X4TS U8484 ( .A(DP_OP_168J26_122_4811_n6641), .B(n1008), .Y(n3094) );
XNOR2X4TS U8485 ( .A(n840), .B(n931), .Y(n3598) );
XOR2X4TS U8486 ( .A(n1682), .B(DP_OP_168J26_122_4811_n8507), .Y(n3096) );
XOR2X4TS U8487 ( .A(n11783), .B(n7273), .Y(n5141) );
XOR2X4TS U8488 ( .A(n3102), .B(n3101), .Y(n5504) );
NAND2BX4TS U8489 ( .AN(n3260), .B(n3577), .Y(n3102) );
NAND2X8TS U8490 ( .A(n3103), .B(n3104), .Y(n5848) );
OAI21X4TS U8491 ( .A0(n5357), .A1(n5355), .B0(n5356), .Y(n3104) );
OAI22X4TS U8492 ( .A0(n8025), .A1(n3678), .B0(n2048), .B1(n3671), .Y(n3682)
);
XOR2X4TS U8493 ( .A(n7279), .B(n1518), .Y(n3671) );
XOR2X4TS U8494 ( .A(n1518), .B(n5237), .Y(n3678) );
OAI22X4TS U8495 ( .A0(n5223), .A1(n1607), .B0(n5272), .B1(n7993), .Y(n5268)
);
XNOR2X4TS U8496 ( .A(n3106), .B(n6260), .Y(n6270) );
XNOR2X4TS U8497 ( .A(n6261), .B(n6259), .Y(n3106) );
OAI22X4TS U8498 ( .A0(n6013), .A1(n11757), .B0(n3107), .B1(n2018), .Y(n6034)
);
XOR2X4TS U8499 ( .A(n1805), .B(n1687), .Y(n3107) );
OAI2BB1X4TS U8500 ( .A0N(n6168), .A1N(n6166), .B0(n3110), .Y(n6197) );
XOR2X4TS U8501 ( .A(n2406), .B(n11783), .Y(n4980) );
XOR2X4TS U8502 ( .A(n2860), .B(n1711), .Y(n5285) );
AOI21X4TS U8503 ( .A0(n3112), .A1(n3238), .B0(n3111), .Y(n3305) );
INVX2TS U8504 ( .A(n10031), .Y(n3111) );
XNOR2X4TS U8505 ( .A(n2569), .B(n3113), .Y(n6957) );
XOR2X4TS U8506 ( .A(n6693), .B(n6694), .Y(n3113) );
XNOR2X4TS U8507 ( .A(n1688), .B(Op_MY[23]), .Y(n8023) );
OAI21X4TS U8508 ( .A0(n9030), .A1(n9031), .B0(n9029), .Y(n3117) );
XNOR2X4TS U8509 ( .A(n9031), .B(n9029), .Y(n3118) );
XNOR2X4TS U8510 ( .A(DP_OP_168J26_122_4811_n6641), .B(n826), .Y(n4913) );
OAI21X4TS U8511 ( .A0(n3124), .A1(n3123), .B0(n3122), .Y(
DP_OP_168J26_122_4811_n1221) );
XNOR2X4TS U8512 ( .A(n2570), .B(n2031), .Y(n3923) );
OAI22X4TS U8513 ( .A0(n4855), .A1(n1820), .B0(n2048), .B1(n4858), .Y(n4867)
);
OAI21X4TS U8514 ( .A0(n8282), .A1(n8283), .B0(n8281), .Y(n3125) );
OAI2BB1X4TS U8515 ( .A0N(n5433), .A1N(n5431), .B0(n3126), .Y(n5435) );
OAI22X4TS U8516 ( .A0(n1936), .A1(n4675), .B0(n1988), .B1(n8021), .Y(n8119)
);
OAI22X4TS U8517 ( .A0(n4976), .A1(n2071), .B0(n1901), .B1(n3128), .Y(n5026)
);
OAI22X4TS U8518 ( .A0(n4958), .A1(DP_OP_168J26_122_4811_n6620), .B0(n2447),
.B1(n3128), .Y(n5102) );
XOR2X4TS U8519 ( .A(n1832), .B(n3129), .Y(n3128) );
NOR2X8TS U8520 ( .A(DP_OP_168J26_122_4811_n637), .B(n2779), .Y(n7010) );
XOR2X4TS U8521 ( .A(n1221), .B(n1861), .Y(n3820) );
XNOR2X4TS U8522 ( .A(DP_OP_168J26_122_4811_n6641), .B(
DP_OP_168J26_122_4811_n6569), .Y(n5275) );
OAI22X4TS U8523 ( .A0(n5236), .A1(n1990), .B0(n2025), .B1(n3132), .Y(n5214)
);
XOR2X4TS U8524 ( .A(n5174), .B(n3129), .Y(n3132) );
XOR2X4TS U8525 ( .A(n12046), .B(n2069), .Y(n3133) );
XNOR2X4TS U8526 ( .A(n2078), .B(n826), .Y(n4993) );
OAI2BB1X4TS U8527 ( .A0N(n1272), .A1N(n9016), .B0(n3134), .Y(n9020) );
NOR2X8TS U8528 ( .A(n7425), .B(n7426), .Y(n3141) );
OAI22X4TS U8529 ( .A0(n7354), .A1(n1951), .B0(n1822), .B1(n7216), .Y(n7356)
);
XOR2X4TS U8530 ( .A(n754), .B(n3202), .Y(n7216) );
OR2X8TS U8531 ( .A(n6940), .B(n6939), .Y(n9373) );
NAND2X8TS U8532 ( .A(n3146), .B(n3143), .Y(n6953) );
NOR2X8TS U8533 ( .A(n6566), .B(n2526), .Y(n10732) );
XNOR2X4TS U8534 ( .A(DP_OP_168J26_122_4811_n8507), .B(
DP_OP_168J26_122_4811_n8534), .Y(n3594) );
NAND2X8TS U8535 ( .A(n3149), .B(n3148), .Y(n3593) );
NAND2X8TS U8536 ( .A(n3150), .B(n1278), .Y(n3149) );
OAI22X4TS U8537 ( .A0(n8628), .A1(n1962), .B0(n8642), .B1(n2108), .Y(n8678)
);
XNOR2X4TS U8538 ( .A(n2573), .B(n2034), .Y(n8628) );
XNOR2X4TS U8539 ( .A(n3151), .B(n10793), .Y(n10794) );
XNOR2X4TS U8540 ( .A(n3156), .B(n5261), .Y(n5265) );
XNOR2X4TS U8541 ( .A(n3158), .B(n3784), .Y(n3157) );
OAI21X4TS U8542 ( .A0(n6787), .A1(n6788), .B0(n6786), .Y(n3159) );
XNOR2X4TS U8543 ( .A(n3160), .B(n6787), .Y(n6868) );
XNOR2X4TS U8544 ( .A(n6788), .B(n6786), .Y(n3160) );
OAI2BB1X4TS U8545 ( .A0N(n9937), .A1N(n9938), .B0(n3164), .Y(n9940) );
XNOR2X4TS U8546 ( .A(n9938), .B(n3165), .Y(n10045) );
XNOR2X4TS U8547 ( .A(n9936), .B(n9937), .Y(n3165) );
XNOR2X4TS U8548 ( .A(n3166), .B(n3771), .Y(n3789) );
NAND2X4TS U8549 ( .A(n6862), .B(n6863), .Y(n8417) );
OAI21X4TS U8550 ( .A0(n3171), .A1(n4393), .B0(n4392), .Y(n3170) );
XOR2X4TS U8551 ( .A(n6378), .B(n4393), .Y(n3172) );
XNOR2X4TS U8552 ( .A(n3174), .B(n6818), .Y(n6856) );
INVX16TS U8553 ( .A(n3176), .Y(n9755) );
XNOR2X4TS U8554 ( .A(n3773), .B(n11786), .Y(n3175) );
OAI2BB1X4TS U8555 ( .A0N(n7051), .A1N(n7050), .B0(n3177), .Y(n8233) );
OAI21X4TS U8556 ( .A0(n7050), .A1(n7051), .B0(n7049), .Y(n3177) );
INVX6TS U8557 ( .A(DP_OP_168J26_122_4811_n201), .Y(
DP_OP_168J26_122_4811_n203) );
OAI22X4TS U8558 ( .A0(n7022), .A1(n2422), .B0(n2115), .B1(n7019), .Y(n7027)
);
OAI22X4TS U8559 ( .A0(n1822), .A1(n7140), .B0(n1951), .B1(n7216), .Y(n7212)
);
OAI2BB1X4TS U8560 ( .A0N(n9951), .A1N(n1848), .B0(n3180), .Y(
DP_OP_168J26_122_4811_n1105) );
AOI21X4TS U8561 ( .A0(n8221), .A1(n8220), .B0(n8219), .Y(n3181) );
XNOR2X4TS U8562 ( .A(n2364), .B(n2033), .Y(n8543) );
OAI22X4TS U8563 ( .A0(n7016), .A1(n2221), .B0(n5320), .B1(n7085), .Y(n7095)
);
OAI22X4TS U8564 ( .A0(n7138), .A1(n2046), .B0(n2221), .B1(n3184), .Y(n7137)
);
ACHCINX4TS U8565 ( .CIN(n8672), .A(n9855), .B(n9854), .CO(n9895) );
XOR2X4TS U8566 ( .A(n1221), .B(n7270), .Y(n3186) );
NAND2BX4TS U8567 ( .AN(n8756), .B(n8236), .Y(n10053) );
AOI21X4TS U8568 ( .A0(n8765), .A1(n8764), .B0(n8763), .Y(n3199) );
XNOR2X4TS U8569 ( .A(n3201), .B(n8369), .Y(n8374) );
XOR2X4TS U8570 ( .A(n1831), .B(n3202), .Y(n4027) );
OAI22X4TS U8571 ( .A0(n3204), .A1(n1983), .B0(n1945), .B1(n4632), .Y(n4758)
);
XNOR2X4TS U8572 ( .A(n1492), .B(n1928), .Y(n3204) );
OAI22X4TS U8573 ( .A0(n4006), .A1(n1982), .B0(n3768), .B1(n1944), .Y(n3872)
);
XNOR2X4TS U8574 ( .A(n3215), .B(n1672), .Y(n8289) );
XNOR2X4TS U8575 ( .A(n1239), .B(n8244), .Y(n3215) );
NAND2BX4TS U8576 ( .AN(n9793), .B(n9864), .Y(n3219) );
OAI22X4TS U8577 ( .A0(n4993), .A1(n1943), .B0(n2106), .B1(n4970), .Y(n4990)
);
NOR2X8TS U8578 ( .A(n3227), .B(n2530), .Y(n3226) );
OAI22X4TS U8579 ( .A0(n3728), .A1(n2107), .B0(n1864), .B1(n3228), .Y(n3975)
);
AOI21X4TS U8580 ( .A0(n4075), .A1(n3229), .B0(n2659), .Y(n4076) );
NAND2X8TS U8581 ( .A(n3231), .B(n3230), .Y(n3937) );
OAI21X4TS U8582 ( .A0(n2673), .A1(n6988), .B0(n6986), .Y(n3235) );
XOR2X4TS U8583 ( .A(n8438), .B(n1375), .Y(Sgf_operation_ODD1_Q_right[38]) );
OAI2BB1X4TS U8584 ( .A0N(n4282), .A1N(n4283), .B0(n3243), .Y(n3765) );
NOR2X8TS U8585 ( .A(DP_OP_168J26_122_4811_n606), .B(n9986), .Y(n10005) );
OAI22X4TS U8586 ( .A0(n2106), .A1(n3247), .B0(n1864), .B1(n4830), .Y(n4845)
);
OAI22X4TS U8587 ( .A0(n2106), .A1(n4538), .B0(n1864), .B1(n11770), .Y(n4575)
);
NAND2BX4TS U8588 ( .AN(n3250), .B(n6798), .Y(n3249) );
OAI22X4TS U8589 ( .A0(n5039), .A1(n1516), .B0(n1901), .B1(n3253), .Y(n5048)
);
XOR2X4TS U8590 ( .A(n3313), .B(n3255), .Y(n3254) );
XOR2X4TS U8591 ( .A(n840), .B(DP_OP_168J26_122_4811_n8510), .Y(n3256) );
XNOR2X4TS U8592 ( .A(n3257), .B(n3259), .Y(n5508) );
XOR2X4TS U8593 ( .A(n3578), .B(n3258), .Y(n3257) );
OAI22X4TS U8594 ( .A0(n2107), .A1(n11770), .B0(n3264), .B1(n1943), .Y(n3263)
);
OAI2BB1X4TS U8595 ( .A0N(n4627), .A1N(n4628), .B0(n3266), .Y(n4749) );
XNOR2X4TS U8596 ( .A(n3269), .B(n5487), .Y(Sgf_operation_ODD1_Q_right[36])
);
OAI21X4TS U8597 ( .A0(n5483), .A1(n1468), .B0(n5482), .Y(n3269) );
NOR2X8TS U8598 ( .A(n8416), .B(n9287), .Y(n5474) );
OAI2BB1X4TS U8599 ( .A0N(n2518), .A1N(n1531), .B0(n3270), .Y(n8547) );
OAI21X4TS U8600 ( .A0(n2518), .A1(n1531), .B0(n1780), .Y(n3270) );
XOR2X4TS U8601 ( .A(n3274), .B(n6672), .Y(n6989) );
OAI2BB1X4TS U8602 ( .A0N(n3279), .A1N(n6748), .B0(n3280), .Y(n6904) );
OAI21X4TS U8603 ( .A0(n2980), .A1(n6965), .B0(n6963), .Y(n3284) );
XOR2X4TS U8604 ( .A(n3285), .B(n6963), .Y(n6969) );
XNOR2X4TS U8605 ( .A(n3287), .B(n3594), .Y(n3286) );
NAND2X8TS U8606 ( .A(n3291), .B(n3290), .Y(n3289) );
OAI22X4TS U8607 ( .A0(n2106), .A1(n5156), .B0(n1864), .B1(n5167), .Y(n5165)
);
XOR2X4TS U8608 ( .A(n5235), .B(n11770), .Y(n5167) );
OAI22X4TS U8609 ( .A0(n5055), .A1(n1898), .B0(n2111), .B1(n3296), .Y(n5079)
);
XOR2X4TS U8610 ( .A(n1979), .B(n11769), .Y(n3296) );
OAI22X4TS U8611 ( .A0(n5045), .A1(n5331), .B0(n5058), .B1(n3298), .Y(n5060)
);
XOR2X4TS U8612 ( .A(n2483), .B(n3299), .Y(n3298) );
OAI2BB1X4TS U8613 ( .A0N(n6904), .A1N(n6903), .B0(n3300), .Y(n6928) );
OAI21X4TS U8614 ( .A0(n6904), .A1(n6903), .B0(n6902), .Y(n3300) );
ADDFHX2TS U8615 ( .A(n9484), .B(n9483), .CI(n9482), .CO(n9748), .S(n9471) );
ADDFHX2TS U8616 ( .A(n7106), .B(n7105), .CI(n7104), .CO(n7133), .S(n7115) );
NAND3X2TS U8617 ( .A(n10745), .B(n10744), .C(n10743), .Y(n366) );
XNOR2X4TS U8618 ( .A(n9520), .B(n9519), .Y(n9521) );
OAI21X4TS U8619 ( .A0(n10508), .A1(n10507), .B0(n10506), .Y(n10588) );
NAND3X2TS U8620 ( .A(n10757), .B(n10756), .C(n10755), .Y(n365) );
OAI21X2TS U8621 ( .A0(n10611), .A1(n10607), .B0(n10612), .Y(n10600) );
XOR2X4TS U8622 ( .A(n10581), .B(n10580), .Y(n11026) );
AOI21X2TS U8623 ( .A0(n10610), .A1(n10576), .B0(n10575), .Y(n10581) );
OAI21X2TS U8624 ( .A0(n10593), .A1(n10590), .B0(n10594), .Y(n10513) );
NOR2X4TS U8625 ( .A(n10523), .B(n1434), .Y(n10577) );
ADDFHX2TS U8626 ( .A(n8079), .B(n8080), .CI(n8078), .CO(n8152), .S(n8155) );
XNOR2X4TS U8627 ( .A(n9556), .B(n9555), .Y(n9557) );
ADDFHX4TS U8628 ( .A(n6322), .B(n6321), .CI(n6320), .CO(n6347), .S(n6351) );
OAI22X2TS U8629 ( .A0(n5680), .A1(n2105), .B0(n4188), .B1(n1918), .Y(n5870)
);
ADDFHX4TS U8630 ( .A(n6329), .B(n6330), .CI(n6331), .CO(n6323), .S(n6360) );
XOR2X4TS U8631 ( .A(n9646), .B(n9645), .Y(n3311) );
XNOR2X4TS U8632 ( .A(n9543), .B(n9542), .Y(n9544) );
ADDFHX4TS U8633 ( .A(n9867), .B(n9866), .CI(n9865), .CO(n9896), .S(n9900) );
XNOR2X4TS U8634 ( .A(n10610), .B(n10586), .Y(n11024) );
ADDFHX4TS U8635 ( .A(n9815), .B(n9814), .CI(n9813), .CO(n9843), .S(n9866) );
ADDFHX2TS U8636 ( .A(n8546), .B(n8545), .CI(n8544), .CO(n9813), .S(n8596) );
XNOR2X4TS U8637 ( .A(n2473), .B(n2034), .Y(n6481) );
XNOR2X4TS U8638 ( .A(n2022), .B(n8508), .Y(n6408) );
ADDFHX2TS U8639 ( .A(n6487), .B(n6486), .CI(n6485), .CO(n8247), .S(n6517) );
ADDFHX4TS U8640 ( .A(n4483), .B(n4481), .CI(n4482), .CO(n4810), .S(n4525) );
ADDFHX4TS U8641 ( .A(n4468), .B(n4467), .CI(n4466), .CO(n4779), .S(n4482) );
NAND2X4TS U8642 ( .A(n7535), .B(n7568), .Y(n7537) );
ADDFHX4TS U8643 ( .A(n4935), .B(n4936), .CI(n4937), .CO(n4948), .S(n4968) );
ADDFHX4TS U8644 ( .A(n8256), .B(n8255), .CI(n8254), .CO(n8264), .S(n8316) );
ADDFHX4TS U8645 ( .A(n4874), .B(n4873), .CI(n4872), .CO(n5196), .S(n4900) );
XOR2X4TS U8646 ( .A(n9376), .B(n9375), .Y(Sgf_operation_ODD1_S_B[9]) );
ADDFHX4TS U8647 ( .A(n8253), .B(n8252), .CI(n8251), .CO(n5979), .S(n8275) );
ADDFHX4TS U8648 ( .A(n10049), .B(n10047), .CI(n10048), .CO(n10050), .S(
n10017) );
ADDFHX2TS U8649 ( .A(n9475), .B(n9474), .CI(n9473), .CO(n9750), .S(n9482) );
XOR2X4TS U8650 ( .A(n10557), .B(n10556), .Y(n11017) );
AOI21X2TS U8651 ( .A0(n11106), .A1(n10553), .B0(n10552), .Y(n10557) );
XNOR2X4TS U8652 ( .A(n10160), .B(n10159), .Y(Sgf_operation_ODD1_Q_left[23])
);
NAND3X2TS U8653 ( .A(n10713), .B(n10712), .C(n10711), .Y(n362) );
ADDFHX4TS U8654 ( .A(n7303), .B(n7302), .CI(n7301), .CO(n7298), .S(n8170) );
MXI2X4TS U8655 ( .A(n10258), .B(n11904), .S0(n11131), .Y(n671) );
OAI21X2TS U8656 ( .A0(n7969), .A1(n7964), .B0(n7968), .Y(n7970) );
ADDFHX4TS U8657 ( .A(n7315), .B(n7314), .CI(n7313), .CO(n8179), .S(n8168) );
AOI21X2TS U8658 ( .A0(n10223), .A1(n10208), .B0(n10207), .Y(n10212) );
ADDFHX2TS U8659 ( .A(n9478), .B(n9477), .CI(n10082), .CO(n9751), .S(n9475)
);
XNOR2X4TS U8660 ( .A(n8911), .B(n8548), .Y(n8572) );
NAND2X4TS U8661 ( .A(n10002), .B(n10001), .Y(n10010) );
OAI21X1TS U8662 ( .A0(n8851), .A1(n8850), .B0(n1691), .Y(n8852) );
ADDFHX4TS U8663 ( .A(n7205), .B(n7204), .CI(n7203), .CO(n7325), .S(n7227) );
XNOR2X4TS U8664 ( .A(n10153), .B(n10152), .Y(Sgf_operation_ODD1_Q_left[26])
);
XNOR2X4TS U8665 ( .A(n6093), .B(n1715), .Y(n5961) );
OAI21X2TS U8666 ( .A0(n9533), .A1(n9532), .B0(n9531), .Y(n9534) );
ADDFHX4TS U8667 ( .A(n7159), .B(n7157), .CI(n7158), .CO(n7209), .S(n7165) );
ADDFX2TS U8668 ( .A(n9461), .B(n9460), .CI(n9459), .CO(n9476), .S(n9042) );
XNOR2X4TS U8669 ( .A(n1812), .B(n5960), .Y(n6143) );
AOI21X2TS U8670 ( .A0(n10693), .A1(n8878), .B0(n8877), .Y(n8882) );
XOR2X4TS U8671 ( .A(n10748), .B(n10709), .Y(n10710) );
OAI21X4TS U8672 ( .A0(n10748), .A1(n9523), .B0(n9522), .Y(n9526) );
OAI21X4TS U8673 ( .A0(n10748), .A1(n9516), .B0(n2377), .Y(n9520) );
AOI21X4TS U8674 ( .A0(n10125), .A1(n10129), .B0(n2300), .Y(n10116) );
OAI21X2TS U8675 ( .A0(n2539), .A1(n10225), .B0(n10224), .Y(n10230) );
NAND2X4TS U8676 ( .A(n9444), .B(n1214), .Y(n9445) );
OAI21X4TS U8677 ( .A0(n10560), .A1(n10582), .B0(n10561), .Y(n10565) );
NAND2X4TS U8678 ( .A(n9414), .B(n1214), .Y(n9415) );
NAND2X4TS U8679 ( .A(n9430), .B(n1214), .Y(n9431) );
NAND2X4TS U8680 ( .A(n9405), .B(n1214), .Y(n9406) );
INVX2TS U8681 ( .A(n10302), .Y(n10281) );
AOI21X2TS U8682 ( .A0(n10693), .A1(n8843), .B0(n8842), .Y(n8847) );
OAI2BB1X4TS U8683 ( .A0N(n1197), .A1N(n10775), .B0(n12191), .Y(n10802) );
XOR2X4TS U8684 ( .A(n2200), .B(n10774), .Y(n10775) );
NAND2X4TS U8685 ( .A(n6632), .B(n6655), .Y(n10234) );
XNOR2X4TS U8686 ( .A(n10142), .B(n10141), .Y(Sgf_operation_ODD1_Q_left[27])
);
AOI21X2TS U8687 ( .A0(n10223), .A1(n10221), .B0(n10214), .Y(n10219) );
BUFX20TS U8688 ( .A(n7539), .Y(n9654) );
OAI21X4TS U8689 ( .A0(n7538), .A1(n7537), .B0(n7536), .Y(n7539) );
OAI21X4TS U8690 ( .A0(n9135), .A1(n9149), .B0(n9136), .Y(n9141) );
NAND2X4TS U8691 ( .A(n7715), .B(n11409), .Y(n9149) );
ADDFHX4TS U8692 ( .A(n4527), .B(n4526), .CI(n4525), .CO(n4808), .S(n4585) );
ADDFHX2TS U8693 ( .A(n6190), .B(n6189), .CI(n6188), .CO(n6191), .S(n6195) );
AND2X8TS U8694 ( .A(n7610), .B(n11693), .Y(n7759) );
OAI22X2TS U8695 ( .A0(n7012), .A1(n1895), .B0(n7169), .B1(n4684), .Y(n7168)
);
NAND2X4TS U8696 ( .A(n10968), .B(n10977), .Y(n418) );
NAND2X6TS U8697 ( .A(n10967), .B(n11128), .Y(n10977) );
NAND3X2TS U8698 ( .A(n10763), .B(n10762), .C(n10761), .Y(n363) );
AOI2BB2X2TS U8699 ( .B0(n10674), .B1(n484), .A0N(n10946), .A1N(n10759), .Y(
n10762) );
ADDFHX2TS U8700 ( .A(n7383), .B(n7382), .CI(n7381), .CO(n7390), .S(n7358) );
ADDFHX4TS U8701 ( .A(n7338), .B(n7337), .CI(n7336), .CO(n7359), .S(n7321) );
OAI22X2TS U8702 ( .A0(n7223), .A1(n1895), .B0(n7327), .B1(n8577), .Y(n7337)
);
OAI22X2TS U8703 ( .A0(n7328), .A1(n1935), .B0(n7379), .B1(n2050), .Y(n7377)
);
ADDFHX2TS U8704 ( .A(n7207), .B(n7208), .CI(n7206), .CO(n7323), .S(n7189) );
XNOR2X4TS U8705 ( .A(n976), .B(n1810), .Y(n7478) );
XNOR2X4TS U8706 ( .A(n2364), .B(n8548), .Y(n4683) );
XNOR2X4TS U8707 ( .A(n2233), .B(n1905), .Y(n8066) );
XNOR2X4TS U8708 ( .A(n2364), .B(n1967), .Y(n7327) );
XNOR2X4TS U8709 ( .A(n7242), .B(n2440), .Y(n3404) );
OAI21X2TS U8710 ( .A0(n8851), .A1(n8841), .B0(n8871), .Y(n8842) );
OAI21X4TS U8711 ( .A0(n10572), .A1(n10527), .B0(n10526), .Y(n11106) );
NAND2X2TS U8712 ( .A(n10601), .B(n10525), .Y(n10527) );
INVX6TS U8713 ( .A(n7597), .Y(n7346) );
ADDFHX4TS U8714 ( .A(n7174), .B(n7173), .CI(n7172), .CO(n7226), .S(n7300) );
ADDFHX4TS U8715 ( .A(n7178), .B(n7180), .CI(n7179), .CO(n7173), .S(n7303) );
NOR2X6TS U8716 ( .A(n7944), .B(n11352), .Y(n9593) );
ADDFHX2TS U8717 ( .A(n7122), .B(n7121), .CI(n7120), .CO(n7149), .S(n7126) );
ADDFHX2TS U8718 ( .A(n9455), .B(n9454), .CI(n9453), .CO(n9483), .S(n9469) );
ADDFHX2TS U8719 ( .A(n9466), .B(n9465), .CI(n9464), .CO(n9474), .S(n9454) );
XNOR2X4TS U8720 ( .A(n9069), .B(n9068), .Y(n9070) );
NOR2X8TS U8721 ( .A(n7757), .B(n7759), .Y(n7771) );
XNOR2X4TS U8722 ( .A(n10147), .B(n10146), .Y(Sgf_operation_ODD1_Q_left[25])
);
OAI21X4TS U8723 ( .A0(n10165), .A1(n10161), .B0(n10162), .Y(n10147) );
ADDFHX4TS U8724 ( .A(n5293), .B(n5291), .CI(n5292), .CO(n5332), .S(n5360) );
ADDFHX2TS U8725 ( .A(n7605), .B(n7367), .CI(n7366), .CO(n7407), .S(n7362) );
ADDFHX2TS U8726 ( .A(n7188), .B(n7187), .CI(n7186), .CO(n7177), .S(n7301) );
XNOR2X4TS U8727 ( .A(n2573), .B(n2058), .Y(n8976) );
XNOR2X4TS U8728 ( .A(n2182), .B(n2251), .Y(n7228) );
XNOR2X4TS U8729 ( .A(n2182), .B(n1966), .Y(n7169) );
XNOR2X4TS U8730 ( .A(n2936), .B(n2031), .Y(n8618) );
AOI21X4TS U8731 ( .A0(n10792), .A1(n10788), .B0(n5132), .Y(n5133) );
OAI21X2TS U8732 ( .A0(n7644), .A1(n7643), .B0(n7642), .Y(n7645) );
AOI21X2TS U8733 ( .A0(n1167), .A1(n1125), .B0(n11597), .Y(n7838) );
ADDFHX4TS U8734 ( .A(n7185), .B(n7184), .CI(n7183), .CO(n7250), .S(n7310) );
ADDFHX4TS U8735 ( .A(n5891), .B(n5890), .CI(n5889), .CO(n6344), .S(n5893) );
XOR2X4TS U8736 ( .A(n10987), .B(n10986), .Y(n10988) );
AOI21X4TS U8737 ( .A0(n10242), .A1(n10238), .B0(n6134), .Y(n6135) );
INVX4TS U8738 ( .A(n9743), .Y(n10238) );
XOR2X4TS U8739 ( .A(n10996), .B(n10995), .Y(n10997) );
ADDFHX4TS U8740 ( .A(n8482), .B(n8483), .CI(n8481), .CO(n9278), .S(n8503) );
ADDFHX4TS U8741 ( .A(n3554), .B(n3553), .CI(n3552), .CO(n3875), .S(n4264) );
ADDFHX2TS U8742 ( .A(n3504), .B(n3503), .CI(n3502), .CO(n3507), .S(n3552) );
OAI22X2TS U8743 ( .A0(n3481), .A1(n1815), .B0(n2043), .B1(n3469), .Y(n3491)
);
ADDFHX4TS U8744 ( .A(n9092), .B(n9091), .CI(n9090), .CO(n9120), .S(n9871) );
OAI21X4TS U8745 ( .A0(n2016), .A1(n10964), .B0(n10963), .Y(n10965) );
ADDFHX4TS U8746 ( .A(n6328), .B(n6327), .CI(n6326), .CO(n6361), .S(n6350) );
ADDFHX4TS U8747 ( .A(n8125), .B(n8124), .CI(n8123), .CO(n8203), .S(n8205) );
OAI21X4TS U8748 ( .A0(n3624), .A1(n2658), .B0(n3623), .Y(n3626) );
ADDFHX4TS U8749 ( .A(n5703), .B(n5702), .CI(n5701), .CO(n5655), .S(n5835) );
ADDFHX4TS U8750 ( .A(n5404), .B(n5403), .CI(n5402), .CO(n5388), .S(n5449) );
AOI21X4TS U8751 ( .A0(n10195), .A1(n10191), .B0(n6274), .Y(n9761) );
OAI21X2TS U8752 ( .A0(n10193), .A1(n9762), .B0(n9761), .Y(n10185) );
AOI21X4TS U8753 ( .A0(n10207), .A1(n10210), .B0(n6235), .Y(n6236) );
ADDFHX4TS U8754 ( .A(n9084), .B(n9086), .CI(n9085), .CO(n9108), .S(n9112) );
ADDFHX2TS U8755 ( .A(n8988), .B(n8989), .CI(n8987), .CO(n9084), .S(n9087) );
ADDFHX4TS U8756 ( .A(n9879), .B(n9878), .CI(n9877), .CO(n9958), .S(n9880) );
ADDFHX4TS U8757 ( .A(n9122), .B(n9121), .CI(n9120), .CO(n9960), .S(n9877) );
ADDFHX4TS U8758 ( .A(n5972), .B(n5971), .CI(n5970), .CO(n5990), .S(n6238) );
ADDFHX4TS U8759 ( .A(n5811), .B(n5810), .CI(n5809), .CO(n5814), .S(n5970) );
ADDFHX4TS U8760 ( .A(n5852), .B(n5851), .CI(n5850), .CO(n6352), .S(n5875) );
XOR2X4TS U8761 ( .A(n10697), .B(n10696), .Y(n10698) );
AOI21X4TS U8762 ( .A0(n10693), .A1(n1368), .B0(n10692), .Y(n10697) );
XOR2X4TS U8763 ( .A(n2658), .B(n3780), .Y(n3781) );
ADDFHX4TS U8764 ( .A(n3886), .B(n3885), .CI(n3884), .CO(n3891), .S(n4159) );
NAND2X4TS U8765 ( .A(n8870), .B(n7809), .Y(n7811) );
ADDFHX4TS U8766 ( .A(n8655), .B(n8654), .CI(n8653), .CO(n8669), .S(n9275) );
INVX4TS U8767 ( .A(n11039), .Y(n10419) );
ADDFHX4TS U8768 ( .A(n4131), .B(n4130), .CI(n4129), .CO(n4144), .S(n4204) );
ADDFHX4TS U8769 ( .A(n9975), .B(n9974), .CI(n9973), .CO(n9993), .S(n9990) );
ADDFHX4TS U8770 ( .A(n8163), .B(n8164), .CI(n8162), .CO(n8165), .S(n9973) );
OAI22X4TS U8771 ( .A0(n7235), .A1(n1878), .B0(n2030), .B1(n7040), .Y(n7241)
);
OAI22X4TS U8772 ( .A0(n7486), .A1(n7484), .B0(n2030), .B1(n7235), .Y(n7522)
);
ADDFHX4TS U8773 ( .A(n8963), .B(n8962), .CI(n8961), .CO(n9024), .S(n9028) );
NAND2X4TS U8774 ( .A(n2516), .B(n6534), .Y(n10209) );
NAND2X2TS U8775 ( .A(n1390), .B(DP_OP_168J26_122_4811_n588), .Y(
DP_OP_168J26_122_4811_n129) );
XOR2X4TS U8776 ( .A(n11009), .B(n10999), .Y(n11000) );
AOI21X4TS U8777 ( .A0(n10107), .A1(n10123), .B0(n10106), .Y(
DP_OP_168J26_122_4811_n173) );
ADDFHX4TS U8778 ( .A(n5879), .B(n5878), .CI(n5877), .CO(n6364), .S(n5876) );
ADDFHX4TS U8779 ( .A(n5670), .B(n5669), .CI(n5668), .CO(n5877), .S(n5688) );
XNOR2X4TS U8780 ( .A(n2233), .B(n2058), .Y(n8137) );
ADDFHX4TS U8781 ( .A(n4124), .B(n4123), .CI(n4122), .CO(n4161), .S(n4143) );
NAND2X4TS U8782 ( .A(n5848), .B(n5849), .Y(n9265) );
ADDFHX4TS U8783 ( .A(n3749), .B(n3748), .CI(n3747), .CO(n3967), .S(n4280) );
ADDFHX2TS U8784 ( .A(n10022), .B(n10021), .CI(n10020), .CO(
DP_OP_168J26_122_4811_n1163), .S(DP_OP_168J26_122_4811_n1164) );
ADDFHX2TS U8785 ( .A(n1816), .B(n2440), .CI(n7039), .CO(n7073), .S(n7046) );
ADDFHX4TS U8786 ( .A(n5641), .B(n5639), .CI(n5640), .CO(n5894), .S(n5686) );
XNOR2X4TS U8787 ( .A(n2573), .B(n2033), .Y(n8615) );
ADDFHX4TS U8788 ( .A(n4661), .B(n4662), .CI(n4663), .CO(n8206), .S(n4660) );
AOI21X4TS U8789 ( .A0(n9048), .A1(n7535), .B0(n7534), .Y(n7536) );
OAI21X2TS U8790 ( .A0(n11022), .A1(n10630), .B0(n11019), .Y(n10634) );
ADDFHX4TS U8791 ( .A(n6334), .B(n6333), .CI(n6332), .CO(n6343), .S(n6359) );
ADDFHX4TS U8792 ( .A(n6311), .B(n6310), .CI(n6309), .CO(n4208), .S(n6342) );
NOR2X4TS U8793 ( .A(n7803), .B(n11378), .Y(n8841) );
ADDFHX4TS U8794 ( .A(n8605), .B(n8604), .CI(n8603), .CO(n8706), .S(n8710) );
ADDFHX4TS U8795 ( .A(n7152), .B(n7151), .CI(n7150), .CO(n7204), .S(n7174) );
NAND2X4TS U8796 ( .A(DP_OP_168J26_122_4811_n776), .B(n3209), .Y(
DP_OP_168J26_122_4811_n133) );
XNOR2X4TS U8797 ( .A(n8550), .B(n1928), .Y(n8558) );
XNOR2X4TS U8798 ( .A(DP_OP_168J26_122_4811_n6794), .B(n7233), .Y(n4444) );
ADDFHX4TS U8799 ( .A(n4413), .B(n4412), .CI(n4411), .CO(n10012), .S(n4397)
);
ADDFHX4TS U8800 ( .A(n8702), .B(n8703), .CI(n8704), .CO(n9281), .S(n9276) );
XNOR2X4TS U8801 ( .A(n2570), .B(n2251), .Y(n7161) );
ADDFHX4TS U8802 ( .A(n4193), .B(n4192), .CI(n4191), .CO(n4205), .S(n6324) );
ADDFHX4TS U8803 ( .A(n7068), .B(n7067), .CI(n7066), .CO(n7049), .S(n7252) );
NAND2X4TS U8804 ( .A(n1505), .B(n2546), .Y(n8367) );
ADDFHX2TS U8805 ( .A(n4773), .B(n4772), .CI(n4771), .CO(n9098), .S(n4770) );
ADDFHX4TS U8806 ( .A(n3454), .B(n3453), .CI(n3452), .CO(n4493), .S(n3512) );
ADDFHX4TS U8807 ( .A(n3934), .B(n3932), .CI(n3933), .CO(n10049), .S(n4424)
);
ADDFHX2TS U8808 ( .A(n4491), .B(n4490), .CI(n4489), .CO(n4747), .S(n4716) );
ADDFHX2TS U8809 ( .A(n3441), .B(n3439), .CI(n3440), .CO(n4490), .S(n3455) );
ADDFHX4TS U8810 ( .A(n8970), .B(n8971), .CI(n8972), .CO(n9019), .S(n9016) );
NAND2X4TS U8811 ( .A(n11460), .B(n9628), .Y(add_x_19_n762) );
XOR2X4TS U8812 ( .A(n9308), .B(n9307), .Y(Sgf_operation_ODD1_S_B[10]) );
NAND2X4TS U8813 ( .A(n3208), .B(n9306), .Y(n9307) );
NAND2X4TS U8814 ( .A(n10032), .B(n10031), .Y(DP_OP_168J26_122_4811_n134) );
ADDFHX4TS U8815 ( .A(n8966), .B(n8965), .CI(n8964), .CO(n9027), .S(n9013) );
ADDFHX4TS U8816 ( .A(n9469), .B(n9468), .CI(n9467), .CO(n9470), .S(n9447) );
ADDFHX4TS U8817 ( .A(n9125), .B(n9124), .CI(n9123), .CO(n9963), .S(n9126) );
OAI21X4TS U8818 ( .A0(n1825), .A1(n9570), .B0(n9569), .Y(n9574) );
ADDFHX4TS U8819 ( .A(n9944), .B(n9942), .CI(n9943), .CO(n9951), .S(n9945) );
ADDFHX4TS U8820 ( .A(n9281), .B(n9280), .CI(n9279), .CO(n9271), .S(n9964) );
ADDFHX4TS U8821 ( .A(n8710), .B(n8709), .CI(n8708), .CO(n9279), .S(n8500) );
ADDFHX2TS U8822 ( .A(n5867), .B(n5866), .CI(n5865), .CO(n6328), .S(n5850) );
MXI2X4TS U8823 ( .A(n9708), .B(n12246), .S0(n9718), .Y(n686) );
OAI22X2TS U8824 ( .A0(n2107), .A1(n3852), .B0(n1864), .B1(n3803), .Y(n3857)
);
ADDFHX4TS U8825 ( .A(n4207), .B(n4208), .CI(n4206), .CO(n6299), .S(n6335) );
NAND2X4TS U8826 ( .A(n10073), .B(n9303), .Y(n9293) );
XOR2X4TS U8827 ( .A(n9662), .B(n9661), .Y(n3324) );
ADDFHX2TS U8828 ( .A(n8957), .B(n8956), .CI(n8955), .CO(n8971), .S(n9106) );
AOI21X4TS U8829 ( .A0(n10632), .A1(n5094), .B0(n5093), .Y(n10636) );
NAND2X8TS U8830 ( .A(n9053), .B(n8412), .Y(n8389) );
ADDFHX4TS U8831 ( .A(n6572), .B(n6571), .CI(n6570), .CO(n8322), .S(n8290) );
ADDFHX4TS U8832 ( .A(n9116), .B(n9115), .CI(n9114), .CO(n9879), .S(n9875) );
ADDFHX4TS U8833 ( .A(n8152), .B(n8151), .CI(n8150), .CO(n8169), .S(n8173) );
ADDFHX2TS U8834 ( .A(n7309), .B(n7308), .CI(n7307), .CO(n7315), .S(n8151) );
OAI21X4TS U8835 ( .A0(n11009), .A1(n2530), .B0(n994), .Y(n8357) );
NAND2X6TS U8836 ( .A(n2490), .B(n2611), .Y(n10791) );
ADDFHX4TS U8837 ( .A(n7386), .B(n7385), .CI(n7384), .CO(n7387), .S(n7417) );
ADDFHX4TS U8838 ( .A(n7360), .B(n7359), .CI(n7358), .CO(n7389), .S(n7384) );
ADDFHX4TS U8839 ( .A(n9807), .B(n9806), .CI(n9805), .CO(n9884), .S(n9827) );
NAND2X4TS U8840 ( .A(n2474), .B(n940), .Y(n10056) );
ADDFHX4TS U8841 ( .A(n9113), .B(n9112), .CI(n9111), .CO(n9123), .S(n9121) );
ADDFHX4TS U8842 ( .A(n7251), .B(n7250), .CI(n7249), .CO(n7175), .S(n7314) );
ADDFHX4TS U8843 ( .A(n7290), .B(n7289), .CI(n7288), .CO(n7249), .S(n8160) );
ADDFHX4TS U8844 ( .A(n7035), .B(n7034), .CI(n7033), .CO(n7166), .S(n7251) );
ADDFHX4TS U8845 ( .A(n4278), .B(n4276), .CI(n4277), .CO(n4398), .S(n9790) );
AOI21X2TS U8846 ( .A0(n10730), .A1(n2353), .B0(n10729), .Y(n10735) );
ADDFHX2TS U8847 ( .A(n7347), .B(n7346), .CI(n7345), .CO(n7363), .S(n7335) );
INVX4TS U8848 ( .A(n1390), .Y(DP_OP_168J26_122_4811_n579) );
BUFX20TS U8849 ( .A(n3355), .Y(n8892) );
XNOR2X4TS U8850 ( .A(n8336), .B(n8335), .Y(Sgf_operation_ODD1_Q_left[35]) );
XNOR2X4TS U8851 ( .A(n2936), .B(n2037), .Y(n4803) );
ADDFHX4TS U8852 ( .A(n3838), .B(n3836), .CI(n3837), .CO(n4012), .S(n4014) );
ADDFHX2TS U8853 ( .A(n3710), .B(n1324), .CI(n3848), .CO(n3838), .S(n4038) );
INVX8TS U8854 ( .A(add_x_19_n754), .Y(n9623) );
ADDFHX4TS U8855 ( .A(n7397), .B(n7396), .CI(n7395), .CO(n9043), .S(n8772) );
INVX2TS U8856 ( .A(n9461), .Y(n7396) );
NAND2X6TS U8857 ( .A(n2495), .B(n2661), .Y(n8184) );
AOI21X4TS U8858 ( .A0(n8236), .A1(n9564), .B0(n8235), .Y(n10054) );
AOI21X2TS U8859 ( .A0(n7785), .A1(n7671), .B0(n7670), .Y(n7672) );
ADDFHX4TS U8860 ( .A(n8969), .B(n8968), .CI(n8967), .CO(n9031), .S(n9026) );
ADDFHX4TS U8861 ( .A(n4572), .B(n4571), .CI(n4570), .CO(n4619), .S(n4630) );
XNOR2X4TS U8862 ( .A(n10131), .B(n10130), .Y(Sgf_operation_ODD1_Q_left[28])
);
OAI21X4TS U8863 ( .A0(n10165), .A1(n10127), .B0(n10126), .Y(n10131) );
ADDFHX2TS U8864 ( .A(n7507), .B(n7506), .CI(n7505), .CO(n7544), .S(n7504) );
ADDFHX2TS U8865 ( .A(n7469), .B(n7468), .CI(n7467), .CO(n7506), .S(n7496) );
ADDFHX4TS U8866 ( .A(n8695), .B(n8694), .CI(n8693), .CO(n8700), .S(n9273) );
OAI21X4TS U8867 ( .A0(n7618), .A1(n7688), .B0(n7617), .Y(n7667) );
AOI21X4TS U8868 ( .A0(n7697), .A1(n7614), .B0(n7613), .Y(n7688) );
INVX6TS U8869 ( .A(Sgf_operation_ODD1_Q_left[30]), .Y(add_x_19_n322) );
ADDFHX4TS U8870 ( .A(n8692), .B(n8691), .CI(n8690), .CO(n9825), .S(n8701) );
XNOR2X4TS U8871 ( .A(n2041), .B(n1954), .Y(n6836) );
XNOR2X4TS U8872 ( .A(n2041), .B(n2408), .Y(n6431) );
XNOR2X4TS U8873 ( .A(n2041), .B(n8619), .Y(n6766) );
XNOR2X4TS U8874 ( .A(n2041), .B(n6636), .Y(n6642) );
XNOR2X4TS U8875 ( .A(n6823), .B(n8533), .Y(n8466) );
XNOR2X4TS U8876 ( .A(n6823), .B(n8513), .Y(n5779) );
XNOR2X4TS U8877 ( .A(n2041), .B(n8508), .Y(n6459) );
XNOR2X4TS U8878 ( .A(n6823), .B(n4488), .Y(n4349) );
XNOR2X4TS U8879 ( .A(n6823), .B(n1024), .Y(n4094) );
ADDFHX4TS U8880 ( .A(n4037), .B(n4036), .CI(n4035), .CO(n4015), .S(n4215) );
AOI21X2TS U8881 ( .A0(n9628), .A1(add_x_19_n770), .B0(n8375), .Y(
add_x_19_n763) );
AOI21X2TS U8882 ( .A0(n10669), .A1(n10662), .B0(n7745), .Y(n7746) );
NAND2X4TS U8883 ( .A(n2556), .B(n5829), .Y(n10993) );
OAI21X4TS U8884 ( .A0(n1825), .A1(n7558), .B0(n7557), .Y(n7561) );
OAI21X4TS U8885 ( .A0(n7563), .A1(n1825), .B0(n7562), .Y(n7567) );
ADDFHX2TS U8886 ( .A(n4306), .B(n4304), .CI(n4305), .CO(n4408), .S(n4326) );
XNOR2X4TS U8887 ( .A(n10121), .B(n10120), .Y(Sgf_operation_ODD1_Q_left[29])
);
XNOR2X4TS U8888 ( .A(n3582), .B(n3581), .Y(n3583) );
ADDFHX2TS U8889 ( .A(n8448), .B(n8449), .CI(n8450), .CO(n8638), .S(n8458) );
NOR2X6TS U8890 ( .A(n11428), .B(n11429), .Y(n9178) );
ADDFHX4TS U8891 ( .A(n7413), .B(n7412), .CI(n7411), .CO(n9446), .S(n7388) );
ADDFHX2TS U8892 ( .A(n7392), .B(n7391), .CI(n7390), .CO(n9448), .S(n7411) );
OAI22X2TS U8893 ( .A0(n2434), .A1(n1645), .B0(n2550), .B1(n12046), .Y(n7372)
);
XNOR2X4TS U8894 ( .A(n2182), .B(n8897), .Y(n8138) );
ADDFHX4TS U8895 ( .A(n9095), .B(n9094), .CI(n9093), .CO(n9130), .S(n9128) );
ADDFHX4TS U8896 ( .A(n8991), .B(n8992), .CI(n8990), .CO(n9012), .S(n9095) );
XNOR2X4TS U8897 ( .A(n1059), .B(n1905), .Y(n8899) );
XNOR2X4TS U8898 ( .A(n2364), .B(n1946), .Y(n4083) );
ADDFHX4TS U8899 ( .A(n8161), .B(n8160), .CI(n8159), .CO(n7313), .S(n8166) );
ADDFHX4TS U8900 ( .A(n3539), .B(n3538), .CI(n3537), .CO(n3557), .S(n3913) );
ADDFHX4TS U8901 ( .A(n3551), .B(n3550), .CI(n3549), .CO(n3537), .S(n4265) );
MXI2X4TS U8902 ( .A(n9710), .B(n11813), .S0(n9724), .Y(n690) );
AOI21X2TS U8903 ( .A0(n7761), .A1(n1281), .B0(n2199), .Y(n7774) );
NOR2X4TS U8904 ( .A(n8337), .B(n7602), .Y(n9647) );
OAI21X2TS U8905 ( .A0(n7602), .A1(n8339), .B0(n7601), .Y(n9652) );
NOR2X4TS U8906 ( .A(n2651), .B(n1709), .Y(n8431) );
ADDFHX4TS U8907 ( .A(n8974), .B(n8973), .CI(n8975), .CO(n9017), .S(n9015) );
XNOR2X4TS U8908 ( .A(n2632), .B(n8920), .Y(n8930) );
OAI21X2TS U8909 ( .A0(n1824), .A1(n8400), .B0(n8399), .Y(n8403) );
ADDFHX4TS U8910 ( .A(n6520), .B(n6518), .CI(n6519), .CO(n6525), .S(n8293) );
OAI21X4TS U8911 ( .A0(n10165), .A1(n10137), .B0(n10136), .Y(n10142) );
OAI21X4TS U8912 ( .A0(n10165), .A1(n10149), .B0(n10134), .Y(n10153) );
ADDFHX4TS U8913 ( .A(n10044), .B(n10043), .CI(n10042), .CO(n10052), .S(
n10019) );
ADDFHX4TS U8914 ( .A(n5657), .B(n5656), .CI(n5655), .CO(n5846), .S(n5740) );
NOR2X8TS U8915 ( .A(n11010), .B(n11008), .Y(n9334) );
ADDFHX4TS U8916 ( .A(n9848), .B(n9847), .CI(n9846), .CO(n9887), .S(n9906) );
ADDFHX4TS U8917 ( .A(n8259), .B(n8257), .CI(n8258), .CO(n8315), .S(n8278) );
ADDFHX4TS U8918 ( .A(n6499), .B(n6498), .CI(n6497), .CO(n8258), .S(n6504) );
NOR2X8TS U8919 ( .A(n10989), .B(n10992), .Y(n9263) );
AOI21X4TS U8920 ( .A0(n7785), .A1(n7665), .B0(n7669), .Y(n7681) );
ADDFHX4TS U8921 ( .A(n11655), .B(n11656), .CI(n11657), .CO(n7623), .S(n7622)
);
ADDFHX4TS U8922 ( .A(n4422), .B(n4423), .CI(n4424), .CO(n10018), .S(n9768)
);
XNOR2X4TS U8923 ( .A(n2484), .B(n2037), .Y(n4297) );
XNOR2X4TS U8924 ( .A(n2349), .B(n1255), .Y(n8584) );
XNOR2X4TS U8925 ( .A(n3597), .B(n3592), .Y(n3596) );
NOR2X4TS U8926 ( .A(DP_OP_168J26_122_4811_n8534), .B(
DP_OP_168J26_122_4811_n8507), .Y(n3592) );
ADDFHX4TS U8927 ( .A(n8261), .B(n8262), .CI(n8260), .CO(n8270), .S(n8314) );
XNOR2X4TS U8928 ( .A(n7242), .B(n951), .Y(n7475) );
ADDFHX2TS U8929 ( .A(n3971), .B(n3972), .CI(n3970), .CO(n4549), .S(n3953) );
MXI2X4TS U8930 ( .A(n10325), .B(n11916), .S0(n10326), .Y(n602) );
XNOR2X4TS U8931 ( .A(n2182), .B(n8896), .Y(n4777) );
XNOR2X4TS U8932 ( .A(n2505), .B(n1905), .Y(n8979) );
XNOR2X4TS U8933 ( .A(n8898), .B(n8548), .Y(n4402) );
ADDFHX4TS U8934 ( .A(n6665), .B(n6664), .CI(n6663), .CO(n6661), .S(n6991) );
XNOR2X4TS U8935 ( .A(n5174), .B(Op_MY[26]), .Y(n4596) );
ADDFHX4TS U8936 ( .A(n9824), .B(n9823), .CI(n9822), .CO(n9844), .S(n9899) );
XNOR2X4TS U8937 ( .A(n8511), .B(n1972), .Y(n4634) );
ADDFHX4TS U8938 ( .A(n3891), .B(n3890), .CI(n3892), .CO(n3914), .S(n4271) );
NAND2X4TS U8939 ( .A(n2494), .B(n6285), .Y(n10176) );
OAI21X2TS U8940 ( .A0(n2083), .A1(n7949), .B0(n7948), .Y(n7950) );
ADDFHX4TS U8941 ( .A(n9941), .B(n9940), .CI(n9939), .CO(n4817), .S(n9942) );
ADDFHX4TS U8942 ( .A(n4418), .B(n4419), .CI(n4417), .CO(n9769), .S(n9885) );
MXI2X4TS U8943 ( .A(n10312), .B(n12248), .S0(n10326), .Y(n597) );
ADDFHX4TS U8944 ( .A(n6651), .B(n6650), .CI(n6649), .CO(n6722), .S(n6681) );
NAND2X4TS U8945 ( .A(n10235), .B(n10231), .Y(n10225) );
ADDFHX4TS U8946 ( .A(n8056), .B(n8055), .CI(n8054), .CO(n8039), .S(n8120) );
ADDFHX4TS U8947 ( .A(n4648), .B(n4646), .CI(n4647), .CO(n9092), .S(n4744) );
ADDFHX4TS U8948 ( .A(n6349), .B(n6348), .CI(n6347), .CO(n6355), .S(n6365) );
ADDFHX4TS U8949 ( .A(n6319), .B(n6318), .CI(n6317), .CO(n6325), .S(n6348) );
ADDFHX4TS U8950 ( .A(n9119), .B(n9118), .CI(n9117), .CO(n9127), .S(n9878) );
ADDFHX4TS U8951 ( .A(n8596), .B(n8594), .CI(n8595), .CO(n9865), .S(n8697) );
AOI21X4TS U8952 ( .A0(n10092), .A1(n3306), .B0(n1386), .Y(n10080) );
ADDFHX4TS U8953 ( .A(n5580), .B(n5581), .CI(n5582), .CO(n5687), .S(n5730) );
XNOR2X4TS U8954 ( .A(n1306), .B(n1850), .Y(n4166) );
XNOR2X4TS U8955 ( .A(n9387), .B(n1161), .Y(n9388) );
NOR2X4TS U8956 ( .A(n7525), .B(n7537), .Y(n7526) );
XNOR2X4TS U8957 ( .A(n1220), .B(n7449), .Y(n4441) );
XNOR2X4TS U8958 ( .A(n7439), .B(n1284), .Y(n4454) );
NAND2X2TS U8959 ( .A(n9074), .B(n9602), .Y(n9075) );
OAI21X1TS U8960 ( .A0(n9604), .A1(n9603), .B0(n9602), .Y(n9605) );
XNOR2X4TS U8961 ( .A(n2573), .B(n1927), .Y(n4702) );
ADDFHX4TS U8962 ( .A(n5917), .B(n5916), .CI(n5915), .CO(n8482), .S(n5918) );
OR2X8TS U8963 ( .A(n10105), .B(n10104), .Y(n10123) );
ADDFHX4TS U8964 ( .A(n6971), .B(n6972), .CI(n6973), .CO(n6978), .S(n6980) );
NAND2X4TS U8965 ( .A(n2583), .B(n2523), .Y(n10194) );
ADDFHX4TS U8966 ( .A(n6133), .B(n6132), .CI(n6131), .CO(n6887), .S(n6749) );
OAI21X4TS U8967 ( .A0(n7722), .A1(n8738), .B0(n7721), .Y(n8725) );
XNOR2X4TS U8968 ( .A(n2376), .B(n2031), .Y(n5551) );
BUFX20TS U8969 ( .A(n3633), .Y(n8911) );
OAI22X2TS U8970 ( .A0(n2107), .A1(n4963), .B0(n1943), .B1(n4943), .Y(n5099)
);
XNOR2X4TS U8971 ( .A(n1037), .B(n2031), .Y(n8440) );
OAI21X2TS U8972 ( .A0(n10574), .A1(n10602), .B0(n10603), .Y(n10575) );
INVX2TS U8973 ( .A(n10600), .Y(n10574) );
XNOR2X4TS U8974 ( .A(n9268), .B(n9267), .Y(n9269) );
ADDFHX4TS U8975 ( .A(n9895), .B(n9893), .CI(n9894), .CO(n9902), .S(n9904) );
XNOR2X4TS U8976 ( .A(n11014), .B(n11013), .Y(n11015) );
ADDFHX4TS U8977 ( .A(n7457), .B(n7456), .CI(n7455), .CO(n7482), .S(n7463) );
MXI2X4TS U8978 ( .A(n9674), .B(n11810), .S0(n9718), .Y(n680) );
ADDFHX4TS U8979 ( .A(n6976), .B(n6975), .CI(n6974), .CO(n6999), .S(n6977) );
ADDFHX4TS U8980 ( .A(n6950), .B(n6949), .CI(n6948), .CO(n6942), .S(n6975) );
XNOR2X4TS U8981 ( .A(n2363), .B(n2037), .Y(n8946) );
XNOR2X4TS U8982 ( .A(n8620), .B(n8552), .Y(n8569) );
ADDFHX2TS U8983 ( .A(n4181), .B(n4180), .CI(n4179), .CO(n4146), .S(n6312) );
ADDFHX4TS U8984 ( .A(n5814), .B(n5813), .CI(n5812), .CO(n5817), .S(n5989) );
ADDFHX4TS U8985 ( .A(n5763), .B(n5762), .CI(n5761), .CO(n5775), .S(n5813) );
ADDFHX2TS U8986 ( .A(n8147), .B(n8148), .CI(n8149), .CO(n8136), .S(n8901) );
NAND2X4TS U8987 ( .A(n5476), .B(n5477), .Y(n9488) );
AOI21X4TS U8988 ( .A0(n1202), .A1(n1128), .B0(n11613), .Y(n7611) );
OAI22X2TS U8989 ( .A0(n5895), .A1(n6919), .B0(n8439), .B1(n1852), .Y(n8494)
);
XNOR2X4TS U8990 ( .A(n8627), .B(n2033), .Y(n8439) );
XNOR2X4TS U8991 ( .A(n2505), .B(n2033), .Y(n5895) );
AOI21X4TS U8992 ( .A0(n10653), .A1(n7742), .B0(n7741), .Y(n10661) );
XNOR2X4TS U8993 ( .A(n1220), .B(n7233), .Y(n7470) );
ADDFHX4TS U8994 ( .A(n5912), .B(n5914), .CI(n5913), .CO(n5919), .S(n8242) );
XNOR2X4TS U8995 ( .A(n5273), .B(n3381), .Y(n7018) );
INVX8TS U8996 ( .A(n11955), .Y(n3381) );
ADDFHX4TS U8997 ( .A(n6991), .B(n6990), .CI(n6989), .CO(n6682), .S(n7003) );
XNOR2X4TS U8998 ( .A(n1608), .B(n7369), .Y(n7087) );
ADDFHX4TS U8999 ( .A(n5923), .B(n5921), .CI(n5922), .CO(n5733), .S(n8250) );
ADDFHX4TS U9000 ( .A(n5531), .B(n5530), .CI(n5529), .CO(n5517), .S(n5922) );
MXI2X2TS U9001 ( .A(n10306), .B(n11964), .S0(n10310), .Y(n621) );
ADDFHX4TS U9002 ( .A(n7494), .B(n7495), .CI(n7493), .CO(n7509), .S(n7483) );
NAND2X2TS U9003 ( .A(Sgf_normalized_result[10]), .B(
Sgf_normalized_result[11]), .Y(n10361) );
INVX6TS U9004 ( .A(n8224), .Y(n8134) );
ADDFHX4TS U9005 ( .A(n6997), .B(n6996), .CI(n6995), .CO(n6987), .S(n7001) );
ADDFHX4TS U9006 ( .A(n6697), .B(n6696), .CI(n6695), .CO(n6684), .S(n6996) );
ADDFHX4TS U9007 ( .A(n4154), .B(n4153), .CI(n4152), .CO(n4163), .S(n4155) );
NAND2X6TS U9008 ( .A(n2572), .B(n2477), .Y(n9746) );
ADDFHX2TS U9009 ( .A(n12112), .B(n7100), .CI(n7099), .CO(n7135), .S(n7104)
);
XNOR2X4TS U9010 ( .A(n10790), .B(n10780), .Y(n10781) );
INVX2TS U9011 ( .A(n7703), .Y(n7749) );
ADDFHX4TS U9012 ( .A(n6505), .B(n6504), .CI(n6503), .CO(n8313), .S(n6571) );
ADDFHX4TS U9013 ( .A(n9871), .B(n9872), .CI(n9873), .CO(n9882), .S(n4821) );
ADDFHX4TS U9014 ( .A(n3725), .B(n3726), .CI(n3727), .CO(n3966), .S(n4283) );
ADDFHX4TS U9015 ( .A(n7498), .B(n7497), .CI(n7496), .CO(n7508), .S(n7501) );
ADDFHX4TS U9016 ( .A(n4998), .B(n4997), .CI(n4996), .CO(n5031), .S(n4999) );
XNOR2X4TS U9017 ( .A(n3357), .B(n3356), .Y(n3358) );
XNOR2X4TS U9018 ( .A(n8721), .B(n8720), .Y(Sgf_operation_ODD1_Q_right[42])
);
ADDFHX4TS U9019 ( .A(n8455), .B(n8454), .CI(n8453), .CO(n8709), .S(n8481) );
ADDFHX4TS U9020 ( .A(n6994), .B(n6993), .CI(n6992), .CO(n7002), .S(n6998) );
ADDFHX4TS U9021 ( .A(n6968), .B(n6970), .CI(n6969), .CO(n6992), .S(n6979) );
MXI2X4TS U9022 ( .A(n10279), .B(n11917), .S0(n11171), .Y(n626) );
NOR2X8TS U9023 ( .A(n3227), .B(n8416), .Y(n9286) );
OAI21X2TS U9024 ( .A0(n7870), .A1(n1134), .B0(n7869), .Y(n7871) );
AOI21X4TS U9025 ( .A0(n1180), .A1(n11642), .B0(n11643), .Y(n7870) );
OAI21X4TS U9026 ( .A0(n10206), .A1(n6237), .B0(n6236), .Y(n9745) );
XNOR2X4TS U9027 ( .A(n2455), .B(n944), .Y(n4555) );
ADDFHX4TS U9028 ( .A(n4427), .B(n4426), .CI(n4425), .CO(
DP_OP_168J26_122_4811_n1191), .S(DP_OP_168J26_122_4811_n1192) );
ADDFHX4TS U9029 ( .A(n4494), .B(n4493), .CI(n4492), .CO(n4746), .S(n4714) );
ADDFHX4TS U9030 ( .A(n4500), .B(n4499), .CI(n4498), .CO(n4523), .S(n4494) );
XOR2X4TS U9031 ( .A(n11005), .B(n11004), .Y(n11006) );
OAI21X2TS U9032 ( .A0(n11005), .A1(n11001), .B0(n11002), .Y(n9268) );
AOI21X4TS U9033 ( .A0(n7928), .A1(n8826), .B0(n7927), .Y(n9408) );
ADDFHX2TS U9034 ( .A(n8683), .B(n8682), .CI(n8681), .CO(n8692), .S(n8654) );
MXI2X4TS U9035 ( .A(n10270), .B(n11899), .S0(n11131), .Y(n668) );
NOR2X4TS U9036 ( .A(n6379), .B(n7957), .Y(n6381) );
NAND2X4TS U9037 ( .A(n6375), .B(n10148), .Y(n7957) );
ADDFHX2TS U9038 ( .A(n4497), .B(n4496), .CI(n4495), .CO(n4527), .S(n4524) );
ADDFHX4TS U9039 ( .A(n3875), .B(n3874), .CI(n3873), .CO(n3555), .S(n4379) );
ADDFHX4TS U9040 ( .A(n3506), .B(n3505), .CI(n3507), .CO(n3519), .S(n3874) );
BUFX20TS U9041 ( .A(n3627), .Y(n8894) );
OAI22X4TS U9042 ( .A0(n4139), .A1(n6003), .B0(n2080), .B1(n3876), .Y(n4132)
);
BUFX20TS U9043 ( .A(n6150), .Y(n6003) );
XNOR2X4TS U9044 ( .A(n2093), .B(n2653), .Y(n7215) );
XNOR2X4TS U9045 ( .A(n5561), .B(n1817), .Y(n4443) );
XNOR2X4TS U9046 ( .A(n7441), .B(n7439), .Y(n4445) );
ADDFHX4TS U9047 ( .A(n8280), .B(n8279), .CI(n8278), .CO(n8317), .S(n8321) );
ADDFHX4TS U9048 ( .A(n8276), .B(n8275), .CI(n8277), .CO(n8283), .S(n8318) );
XNOR2X4TS U9049 ( .A(n7242), .B(n6156), .Y(n3882) );
ADDFHX4TS U9050 ( .A(n9110), .B(n9109), .CI(n9108), .CO(n9014), .S(n9124) );
ADDFHX4TS U9051 ( .A(n10016), .B(n10015), .CI(n10014), .CO(n9946), .S(n10021) );
ADDFHX4TS U9052 ( .A(n9929), .B(n9928), .CI(n9927), .CO(n9944), .S(n10014)
);
ADDFHX4TS U9053 ( .A(n4549), .B(n4548), .CI(n4547), .CO(n4631), .S(n4627) );
XNOR2X4TS U9054 ( .A(n2456), .B(n1966), .Y(n4082) );
XNOR2X4TS U9055 ( .A(n1811), .B(n1810), .Y(n5683) );
ADDFHX4TS U9056 ( .A(n9013), .B(n9012), .CI(n9011), .CO(n9022), .S(n9129) );
INVX4TS U9057 ( .A(n8913), .Y(n8982) );
CMPR22X2TS U9058 ( .A(n5183), .B(n5182), .CO(n5184), .S(n5189) );
XOR2X4TS U9059 ( .A(n3921), .B(DP_OP_168J26_122_4811_n3219), .Y(n3922) );
XNOR2X4TS U9060 ( .A(n2632), .B(n8626), .Y(n6480) );
XNOR2X4TS U9061 ( .A(n2074), .B(n7233), .Y(n7040) );
NAND2BX4TS U9062 ( .AN(n5666), .B(n2564), .Y(n5667) );
XNOR2X4TS U9063 ( .A(n2074), .B(n2669), .Y(n7235) );
XNOR2X4TS U9064 ( .A(n2074), .B(n2440), .Y(n7485) );
XNOR2X4TS U9065 ( .A(n2074), .B(n1816), .Y(n7443) );
OAI22X2TS U9066 ( .A0(n5634), .A1(n1983), .B0(n5633), .B1(n1944), .Y(n5843)
);
NOR2X8TS U9067 ( .A(n7839), .B(n7837), .Y(n7867) );
NOR2X6TS U9068 ( .A(n1169), .B(n11596), .Y(n7789) );
ADDFHX4TS U9069 ( .A(n8475), .B(n8474), .CI(n8473), .CO(n8664), .S(n8491) );
ADDFHX4TS U9070 ( .A(n7125), .B(n7123), .CI(n7124), .CO(n7144), .S(n7148) );
ADDFHX4TS U9071 ( .A(n8173), .B(n8172), .CI(n8171), .CO(n8174), .S(n9991) );
ADDFHX4TS U9072 ( .A(n5909), .B(n5910), .CI(n5911), .CO(n8484), .S(n5920) );
ADDFHX4TS U9073 ( .A(n4949), .B(n4948), .CI(n4947), .CO(n4927), .S(n4950) );
XNOR2X4TS U9074 ( .A(n2044), .B(n8510), .Y(n5501) );
ADDFHX2TS U9075 ( .A(n8113), .B(n8115), .CI(n8114), .CO(n8131), .S(n8123) );
ADDFHX2TS U9076 ( .A(n4625), .B(n4624), .CI(n4623), .CO(n4750), .S(n4753) );
ADDFHX4TS U9077 ( .A(n8696), .B(n8697), .CI(n8698), .CO(n9898), .S(n8699) );
XNOR2X4TS U9078 ( .A(n10071), .B(n10070), .Y(Sgf_operation_ODD1_Q_right[40])
);
OAI21X4TS U9079 ( .A0(n10067), .A1(n1463), .B0(n10066), .Y(n10071) );
XOR2X4TS U9080 ( .A(n1271), .B(n2380), .Y(n5802) );
XNOR2X4TS U9081 ( .A(n754), .B(n7369), .Y(n7354) );
BUFX20TS U9082 ( .A(Op_MY[25]), .Y(n7369) );
OAI22X2TS U9083 ( .A0(n8614), .A1(n6832), .B0(n6831), .B1(n8612), .Y(n6844)
);
AO21X4TS U9084 ( .A0(n6528), .A1(n8612), .B0(n6832), .Y(n4100) );
ADDFHX4TS U9085 ( .A(n3863), .B(n3861), .CI(n3862), .CO(n4281), .S(n4286) );
ADDFHX4TS U9086 ( .A(n3724), .B(n3723), .CI(n3722), .CO(n3725), .S(n3861) );
ADDFHX4TS U9087 ( .A(n5750), .B(n5749), .CI(n5748), .CO(n5729), .S(n5818) );
ADDFHX4TS U9088 ( .A(n8300), .B(n8298), .CI(n8299), .CO(n8291), .S(n8301) );
ADDFHX4TS U9089 ( .A(n11621), .B(n11622), .CI(n11623), .CO(n7628), .S(n7624)
);
ADDFHX4TS U9090 ( .A(n6629), .B(n6628), .CI(n6627), .CO(n6615), .S(n6662) );
ADDFHX4TS U9091 ( .A(n9851), .B(n9850), .CI(n9849), .CO(n9889), .S(n9886) );
OAI21X4TS U9092 ( .A0(n7489), .A1(n2448), .B0(n2399), .Y(n4138) );
OAI22X4TS U9093 ( .A0(n7490), .A1(n6156), .B0(n1624), .B1(n2397), .Y(n4462)
);
OAI22X2TS U9094 ( .A0(n2399), .A1(n824), .B0(n1817), .B1(n7489), .Y(n7518)
);
OAI22X4TS U9095 ( .A0(n2440), .A1(n2399), .B0(n1883), .B1(n2643), .Y(n7232)
);
MXI2X4TS U9096 ( .A(n10294), .B(n11898), .S0(n10293), .Y(n647) );
ADDFHX4TS U9097 ( .A(n8035), .B(n8034), .CI(n8033), .CO(n8227), .S(n8225) );
ADDFHX4TS U9098 ( .A(n8031), .B(n8030), .CI(n8029), .CO(n8057), .S(n8033) );
XNOR2X4TS U9099 ( .A(n1818), .B(n8548), .Y(n4256) );
ADDFHX4TS U9100 ( .A(n5399), .B(n5400), .CI(n5401), .CO(n5409), .S(n5450) );
AOI21X4TS U9101 ( .A0(n8404), .A1(n8412), .B0(n7530), .Y(n8391) );
XNOR2X4TS U9102 ( .A(n7439), .B(n7233), .Y(n7440) );
ADDFHX4TS U9103 ( .A(n4742), .B(n4743), .CI(n4744), .CO(n9872), .S(n4818) );
OAI21X2TS U9104 ( .A0(n2084), .A1(n9616), .B0(n9615), .Y(n9617) );
ADDFHX2TS U9105 ( .A(n3443), .B(n3444), .CI(n3442), .CO(n4500), .S(n3440) );
NAND2X4TS U9106 ( .A(n11692), .B(n7620), .Y(n7758) );
ADDFHX4TS U9107 ( .A(n11689), .B(n11690), .CI(n11691), .CO(n7620) );
XNOR2X4TS U9108 ( .A(n2456), .B(n1927), .Y(n5925) );
XNOR2X4TS U9109 ( .A(n8898), .B(n8552), .Y(n4345) );
MXI2X4TS U9110 ( .A(n10298), .B(n11926), .S0(n10326), .Y(n600) );
ADDFHX4TS U9111 ( .A(n3752), .B(n3751), .CI(n3750), .CO(n4279), .S(n3867) );
XNOR2X4TS U9112 ( .A(n5960), .B(n6145), .Y(n5594) );
ADDFHX2TS U9113 ( .A(n3857), .B(n3856), .CI(n3855), .CO(n3859), .S(n4050) );
NOR2X8TS U9114 ( .A(n7923), .B(n1164), .Y(n8808) );
OAI22X2TS U9115 ( .A0(n7490), .A1(n4450), .B0(n1624), .B1(n2672), .Y(n3450)
);
OAI21X2TS U9116 ( .A0(n2083), .A1(n9382), .B0(n9381), .Y(n9383) );
NOR2X8TS U9117 ( .A(n7930), .B(n1162), .Y(n9439) );
XNOR2X4TS U9118 ( .A(n2348), .B(n1967), .Y(n7291) );
XNOR2X4TS U9119 ( .A(n5561), .B(n1715), .Y(n3405) );
ADDFHX4TS U9120 ( .A(n8274), .B(n8273), .CI(n8272), .CO(n8319), .S(n8312) );
ADDFHX4TS U9121 ( .A(n5337), .B(n5336), .CI(n5335), .CO(n5457), .S(n5333) );
ADDFHX2TS U9122 ( .A(n3975), .B(n3974), .CI(n3973), .CO(n4548), .S(n3969) );
ADDFHX4TS U9123 ( .A(n6936), .B(n6935), .CI(n6934), .CO(n6937), .S(n6875) );
ADDFHX4TS U9124 ( .A(n5296), .B(n5295), .CI(n5294), .CO(n5448), .S(n5334) );
NOR2X4TS U9125 ( .A(n6279), .B(n9762), .Y(n6281) );
OAI21X4TS U9126 ( .A0(n10336), .A1(n10333), .B0(n10334), .Y(n11298) );
ADDFHX4TS U9127 ( .A(n6337), .B(n6336), .CI(n6335), .CO(n6298), .S(n6338) );
ADDFHX4TS U9128 ( .A(n4205), .B(n4204), .CI(n4203), .CO(n4211), .S(n6336) );
XNOR2X4TS U9129 ( .A(n7442), .B(DP_OP_168J26_122_4811_n8448), .Y(n4189) );
OAI21X4TS U9130 ( .A0(n1825), .A1(n7572), .B0(n7571), .Y(n7575) );
OAI21X2TS U9131 ( .A0(n9425), .A1(n9419), .B0(n9426), .Y(n7933) );
ADDFHX2TS U9132 ( .A(n5715), .B(n5714), .CI(n5713), .CO(n5701), .S(n5774) );
OAI21X2TS U9133 ( .A0(n11022), .A1(n10637), .B0(n10636), .Y(n10642) );
ADDFHX4TS U9134 ( .A(n4398), .B(n4397), .CI(n4396), .CO(n9767), .S(n9809) );
ADDFHX4TS U9135 ( .A(n7128), .B(n7127), .CI(n7126), .CO(n7147), .S(n7050) );
ADDFHX4TS U9136 ( .A(n5377), .B(n5375), .CI(n5376), .CO(n5389), .S(n5429) );
ADDFHX4TS U9137 ( .A(n8670), .B(n8671), .CI(n8669), .CO(n9954), .S(n8712) );
ADDFHX4TS U9138 ( .A(n8200), .B(n8199), .CI(n8198), .CO(n8209), .S(n8204) );
ADDFHX4TS U9139 ( .A(n5417), .B(n5418), .CI(n5416), .CO(n5443), .S(n5447) );
AOI21X4TS U9140 ( .A0(n9371), .A1(n9372), .B0(n9370), .Y(n9376) );
ADDFHX4TS U9141 ( .A(n5196), .B(n5197), .CI(n5198), .CO(n5203), .S(n5205) );
ADDFHX4TS U9142 ( .A(n5136), .B(n5135), .CI(n5134), .CO(n5201), .S(n5197) );
ADDFHX4TS U9143 ( .A(n9829), .B(n9831), .CI(n9830), .CO(n9828), .S(n9907) );
OAI22X4TS U9144 ( .A0(n5498), .A1(n8581), .B0(n5502), .B1(n8579), .Y(n5530)
);
ADDFHX4TS U9145 ( .A(n4145), .B(n4144), .CI(n4143), .CO(n6296), .S(n4210) );
OAI21X4TS U9146 ( .A0(n8876), .A1(n7802), .B0(n7801), .Y(n8869) );
INVX4TS U9147 ( .A(n6397), .Y(n4806) );
XNOR2X4TS U9148 ( .A(n7279), .B(n2093), .Y(n4668) );
XNOR2X4TS U9149 ( .A(n1882), .B(n1312), .Y(n5955) );
ADDFHX4TS U9150 ( .A(n4886), .B(n4885), .CI(n4884), .CO(n4897), .S(n4924) );
ADDFHX4TS U9151 ( .A(n7222), .B(n7221), .CI(n7220), .CO(n8768), .S(n8240) );
ADDFHX4TS U9152 ( .A(n6064), .B(n6065), .CI(n6063), .CO(n6611), .S(n6655) );
NAND2X4TS U9153 ( .A(n6605), .B(n6578), .Y(n10220) );
XOR2X4TS U9154 ( .A(n2527), .B(n1890), .Y(n5173) );
OAI21X2TS U9155 ( .A0(n6279), .A1(n9761), .B0(n6278), .Y(n6280) );
XNOR2X4TS U9156 ( .A(n5561), .B(n7488), .Y(n3418) );
XNOR2X4TS U9157 ( .A(n2445), .B(n2464), .Y(n4142) );
ADDFHX4TS U9158 ( .A(n5959), .B(n5957), .CI(n5958), .CO(n5972), .S(n6254) );
XNOR2X4TS U9159 ( .A(n1869), .B(n2643), .Y(n5573) );
XNOR2X4TS U9160 ( .A(n2323), .B(n1860), .Y(n5605) );
XNOR2X4TS U9161 ( .A(n2323), .B(n1253), .Y(n5956) );
XNOR2X4TS U9162 ( .A(n2323), .B(n1876), .Y(n6147) );
XNOR2X4TS U9163 ( .A(n2323), .B(n1813), .Y(n6140) );
ADDHX4TS U9164 ( .A(n6789), .B(n6790), .CO(n6784), .S(n6822) );
NAND2X4TS U9165 ( .A(n8325), .B(n6391), .Y(n7525) );
NOR2X6TS U9166 ( .A(n10110), .B(n9056), .Y(n8325) );
ADDFHX4TS U9167 ( .A(n6130), .B(n6129), .CI(n6128), .CO(n6708), .S(n6876) );
MXI2X4TS U9168 ( .A(n9705), .B(n11809), .S0(n11167), .Y(n674) );
ADDFHX2TS U9169 ( .A(n1292), .B(n4434), .CI(n4433), .CO(n4506), .S(n4502) );
ADDFHX4TS U9170 ( .A(n6930), .B(n6929), .CI(n6928), .CO(n6981), .S(n6931) );
ADDFHX4TS U9171 ( .A(n6901), .B(n6899), .CI(n6900), .CO(n6951), .S(n6929) );
CMPR22X2TS U9172 ( .A(n5060), .B(n5059), .CO(n5065), .S(n5067) );
NOR2X4TS U9173 ( .A(n3785), .B(DP_OP_168J26_122_4811_n3238), .Y(n3786) );
ADDFHX4TS U9174 ( .A(n9981), .B(n9980), .CI(n9979), .CO(n9992), .S(n9988) );
ADDFHX4TS U9175 ( .A(n8155), .B(n8154), .CI(n8153), .CO(n8172), .S(n9981) );
ADDFHX4TS U9176 ( .A(n6109), .B(n6108), .CI(n6110), .CO(n6773), .S(n6767) );
ADDFHX4TS U9177 ( .A(n8707), .B(n8705), .CI(n8706), .CO(n8713), .S(n9280) );
ADDFHX4TS U9178 ( .A(n6585), .B(n6584), .CI(n6583), .CO(n6720), .S(n6728) );
OAI22X2TS U9179 ( .A0(n4255), .A1(n1982), .B0(n4006), .B1(n1944), .Y(n4307)
);
NOR2X4TS U9180 ( .A(n6745), .B(n6767), .Y(n10262) );
NAND2X4TS U9181 ( .A(n6767), .B(n6745), .Y(n10263) );
XNOR2X4TS U9182 ( .A(n1882), .B(DP_OP_168J26_122_4811_n8448), .Y(n6155) );
OR2X8TS U9183 ( .A(n7798), .B(n1189), .Y(n8865) );
XNOR2X4TS U9184 ( .A(n7966), .B(n7965), .Y(Sgf_operation_ODD1_Q_left[30]) );
OAI21X2TS U9185 ( .A0(n9539), .A1(n9531), .B0(n9540), .Y(n7823) );
NOR2X6TS U9186 ( .A(n7822), .B(n11360), .Y(n9539) );
XNOR2X4TS U9187 ( .A(n2041), .B(n8510), .Y(n5498) );
OAI21X4TS U9188 ( .A0(n7528), .A1(n7564), .B0(n7527), .Y(n9048) );
MXI2X4TS U9189 ( .A(n10308), .B(n12141), .S0(n10310), .Y(n623) );
XNOR2X4TS U9190 ( .A(n7442), .B(n1860), .Y(n3406) );
NAND2X8TS U9191 ( .A(n7619), .B(n1177), .Y(n7756) );
XOR2X4TS U9192 ( .A(n2072), .B(n7657), .Y(n7814) );
OAI22X2TS U9193 ( .A0(n4263), .A1(n1982), .B0(n4255), .B1(n6883), .Y(n4332)
);
XNOR2X4TS U9194 ( .A(n8620), .B(n1929), .Y(n4255) );
NOR2X8TS U9195 ( .A(DP_OP_168J26_122_4811_n8465), .B(
DP_OP_168J26_122_4811_n8490), .Y(n3572) );
ADDFHX4TS U9196 ( .A(n4052), .B(n4051), .CI(n4050), .CO(n4251), .S(n5366) );
OAI22X4TS U9197 ( .A0(n3880), .A1(n6082), .B0(n6081), .B1(n2261), .Y(n9736)
);
XNOR2X4TS U9198 ( .A(n1812), .B(n1302), .Y(n6081) );
XNOR2X4TS U9199 ( .A(n7664), .B(n7663), .Y(n7815) );
OAI21X4TS U9200 ( .A0(n7916), .A1(n7659), .B0(n7658), .Y(n7664) );
ADDFHX4TS U9201 ( .A(n7146), .B(n7145), .CI(n7144), .CO(n8241), .S(n8237) );
ADDFHX4TS U9202 ( .A(n5334), .B(n5333), .CI(n5332), .CO(n5467), .S(n5355) );
ADDFHX4TS U9203 ( .A(n8203), .B(n8202), .CI(n8201), .CO(n8210), .S(n8208) );
ADDFHX4TS U9204 ( .A(n8131), .B(n8130), .CI(n8129), .CO(n8212), .S(n8201) );
ADDFHX4TS U9205 ( .A(n8128), .B(n8127), .CI(n8126), .CO(n8122), .S(n8202) );
ADDFHX4TS U9206 ( .A(n6858), .B(n6857), .CI(n6856), .CO(n6864), .S(n6863) );
ADDFHX4TS U9207 ( .A(n5086), .B(n5085), .CI(n5084), .CO(n6692), .S(n6877) );
ADDFHX4TS U9208 ( .A(n4601), .B(n4600), .CI(n4599), .CO(n4659), .S(n4618) );
NOR2X4TS U9209 ( .A(n1332), .B(n6289), .Y(n10156) );
ADDFHX4TS U9210 ( .A(n4801), .B(n4800), .CI(n4799), .CO(n7432), .S(n4809) );
ADDFHX4TS U9211 ( .A(n4480), .B(n4479), .CI(n4478), .CO(n4801), .S(n4526) );
XNOR2X4TS U9212 ( .A(n7793), .B(n7792), .Y(n7807) );
ADDFHX4TS U9213 ( .A(n6249), .B(n6248), .CI(n6247), .CO(n6255), .S(n6266) );
XNOR2X4TS U9214 ( .A(n1223), .B(n11687), .Y(n3415) );
XNOR2X4TS U9215 ( .A(n3345), .B(n1926), .Y(n4366) );
ADDFHX2TS U9216 ( .A(n6011), .B(n6010), .CI(n6009), .CO(n6051), .S(n6027) );
XNOR2X4TS U9217 ( .A(n8443), .B(n2251), .Y(n4360) );
OR2X8TS U9218 ( .A(n10103), .B(n10102), .Y(n10109) );
OAI21X4TS U9219 ( .A0(n7730), .A1(n11589), .B0(n7698), .Y(n7729) );
XNOR2X4TS U9220 ( .A(n2676), .B(n10980), .Y(n10981) );
AOI21X4TS U9221 ( .A0(n2676), .A1(n9263), .B0(n9262), .Y(n11005) );
NAND2X8TS U9222 ( .A(DP_OP_168J26_122_4811_n8199), .B(n6079), .Y(n5794) );
NOR2X8TS U9223 ( .A(DP_OP_168J26_122_4811_n3552), .B(
DP_OP_168J26_122_4811_n3541), .Y(n3366) );
ADDFHX4TS U9224 ( .A(n5227), .B(n5226), .CI(n5225), .CO(n5359), .S(n5207) );
XNOR2X4TS U9225 ( .A(n2573), .B(n2410), .Y(n4343) );
XNOR2X4TS U9226 ( .A(n1805), .B(n916), .Y(n6173) );
ADDFHX2TS U9227 ( .A(n4940), .B(n4939), .CI(n4938), .CO(n4935), .S(n5098) );
OAI22X4TS U9228 ( .A0(n2089), .A1(n6081), .B0(n6078), .B1(n2261), .Y(n6792)
);
XNOR2X4TS U9229 ( .A(n6093), .B(n1931), .Y(n6078) );
NAND2X4TS U9230 ( .A(n10025), .B(n10024), .Y(DP_OP_168J26_122_4811_n132) );
INVX4TS U9231 ( .A(n10023), .Y(n10025) );
XNOR2X4TS U9232 ( .A(n7242), .B(n7233), .Y(n4459) );
AOI21X4TS U9233 ( .A0(n4075), .A1(n11732), .B0(n3622), .Y(n3623) );
ADDFHX4TS U9234 ( .A(n5406), .B(n5407), .CI(n5405), .CO(n5365), .S(n5434) );
XNOR2X4TS U9235 ( .A(n1454), .B(n1931), .Y(n5705) );
XNOR2X4TS U9236 ( .A(n1882), .B(n1813), .Y(n5792) );
ADDFHX4TS U9237 ( .A(n7116), .B(n7114), .CI(n7115), .CO(n7590), .S(n7587) );
NOR2X4TS U9238 ( .A(n9046), .B(n8405), .Y(n8408) );
ADDFHX4TS U9239 ( .A(n6118), .B(n6117), .CI(n6116), .CO(n6667), .S(n6710) );
ADDFHX4TS U9240 ( .A(n6043), .B(n6042), .CI(n6041), .CO(n6030), .S(n6116) );
ADDFHX4TS U9241 ( .A(n4160), .B(n4159), .CI(n4158), .CO(n4272), .S(n4268) );
ADDFHX4TS U9242 ( .A(n5841), .B(n5840), .CI(n5839), .CO(n8480), .S(n5999) );
ADDFHX4TS U9243 ( .A(n5738), .B(n1246), .CI(n5739), .CO(n8453), .S(n5840) );
XNOR2X4TS U9244 ( .A(n2397), .B(n7242), .Y(n3531) );
XNOR2X4TS U9245 ( .A(n1582), .B(n3322), .Y(n8895) );
ADDFHX4TS U9246 ( .A(n3985), .B(n3983), .CI(n3984), .CO(n4626), .S(n3766) );
ADDFHX4TS U9247 ( .A(n5162), .B(n5160), .CI(n5161), .CO(n5242), .S(n5200) );
XNOR2X4TS U9248 ( .A(n2022), .B(n6636), .Y(n6638) );
BUFX20TS U9249 ( .A(n5526), .Y(n6636) );
XOR2X4TS U9250 ( .A(n1262), .B(n1278), .Y(n3646) );
ADDFHX4TS U9251 ( .A(n7326), .B(n7325), .CI(n7324), .CO(n7418), .S(n7415) );
OAI22X2TS U9252 ( .A0(n730), .A1(n7070), .B0(n1916), .B1(n1306), .Y(n7102)
);
XOR2X4TS U9253 ( .A(n11688), .B(n2592), .Y(n7476) );
XOR2X4TS U9254 ( .A(n11500), .B(n801), .Y(n7097) );
XNOR2X4TS U9255 ( .A(n1881), .B(n2592), .Y(n4447) );
XNOR2X4TS U9256 ( .A(DP_OP_168J26_122_4811_n6776), .B(n7233), .Y(n3535) );
ADDFHX4TS U9257 ( .A(n4656), .B(n4655), .CI(n4657), .CO(n8197), .S(n4658) );
ADDFHX4TS U9258 ( .A(n6355), .B(n6354), .CI(n6353), .CO(n6339), .S(n6356) );
ADDFHX4TS U9259 ( .A(n6325), .B(n6324), .CI(n6323), .CO(n6337), .S(n6354) );
XNOR2X4TS U9260 ( .A(n5721), .B(n1302), .Y(n5720) );
ADDFHX2TS U9261 ( .A(n5873), .B(n5872), .CI(n5871), .CO(n6331), .S(n6326) );
ADDFHX4TS U9262 ( .A(n8295), .B(n8296), .CI(n8297), .CO(n8302), .S(n8304) );
ADDFHX2TS U9263 ( .A(n6122), .B(n6123), .CI(n6124), .CO(n6129), .S(n6131) );
NAND2X6TS U9264 ( .A(DP_OP_168J26_122_4811_n8194), .B(
DP_OP_168J26_122_4811_n8220), .Y(n3411) );
OR2X8TS U9265 ( .A(n2523), .B(n2583), .Y(n10195) );
INVX4TS U9266 ( .A(n8861), .Y(n8880) );
ADDFHX4TS U9267 ( .A(n6234), .B(n6233), .CI(n6232), .CO(n6527), .S(n6555) );
ADDFHX4TS U9268 ( .A(n6217), .B(n6216), .CI(n6215), .CO(n6272), .S(n6232) );
ADDFHX4TS U9269 ( .A(n5457), .B(n5456), .CI(n5455), .CO(n5465), .S(n5466) );
ADDFHX4TS U9270 ( .A(n5353), .B(n5354), .CI(n5352), .CO(n5455), .S(n5357) );
OAI21X2TS U9271 ( .A0(n8406), .A1(n8396), .B0(n8395), .Y(n8397) );
ADDFHX4TS U9272 ( .A(n4766), .B(n4767), .CI(n4765), .CO(n9876), .S(n9948) );
ADDFHX4TS U9273 ( .A(n8170), .B(n8169), .CI(n8168), .CO(n8177), .S(n8175) );
NOR2X4TS U9274 ( .A(n2540), .B(n6384), .Y(n10110) );
ADDFHX4TS U9275 ( .A(n9022), .B(n9020), .CI(n9021), .CO(n9971), .S(n9968) );
ADDFHX4TS U9276 ( .A(n9028), .B(n9027), .CI(n9026), .CO(n9977), .S(n9021) );
ADDFHX4TS U9277 ( .A(n6205), .B(n6204), .CI(n6203), .CO(n6578), .S(n6612) );
ADDFHX4TS U9278 ( .A(n6196), .B(n6195), .CI(n6194), .CO(n6201), .S(n6203) );
XNOR2X4TS U9279 ( .A(n1805), .B(n2503), .Y(n4196) );
NOR2X4TS U9280 ( .A(n8470), .B(n8477), .Y(n11008) );
OR2X6TS U9281 ( .A(n2516), .B(n6534), .Y(n10210) );
ADDFHX4TS U9282 ( .A(n6273), .B(n6272), .CI(n6271), .CO(n6452), .S(n6534) );
XNOR2X4TS U9283 ( .A(n3354), .B(n3353), .Y(n3355) );
ADDFHX4TS U9284 ( .A(n5445), .B(n5444), .CI(n5443), .CO(n5453), .S(n5461) );
OAI22X4TS U9285 ( .A0(n6087), .A1(n11779), .B0(n1938), .B1(n6085), .Y(n6760)
);
NOR2X2TS U9286 ( .A(n8743), .B(n9143), .Y(n7720) );
XNOR2X4TS U9287 ( .A(n2455), .B(n1008), .Y(n4855) );
XNOR2X4TS U9288 ( .A(n7270), .B(n1008), .Y(n5321) );
ADDFHX2TS U9289 ( .A(n5077), .B(n5076), .CI(n5075), .CO(n5009), .S(n5086) );
OAI21X2TS U9290 ( .A0(n8218), .A1(n10061), .B0(n8217), .Y(n8219) );
XOR2X2TS U9291 ( .A(n1129), .B(n11638), .Y(n7715) );
NAND2BX2TS U9292 ( .AN(n2448), .B(n1006), .Y(n6005) );
XNOR2X4TS U9293 ( .A(n1006), .B(n1253), .Y(n6153) );
XNOR2X4TS U9294 ( .A(n1006), .B(n6156), .Y(n5620) );
XNOR2X4TS U9295 ( .A(n1006), .B(n6160), .Y(n5962) );
XNOR2X4TS U9296 ( .A(n7852), .B(n11538), .Y(n7925) );
ADDFHX4TS U9297 ( .A(n8265), .B(n8264), .CI(n8263), .CO(n8268), .S(n8281) );
XNOR2X4TS U9298 ( .A(n1812), .B(n2440), .Y(n5752) );
ADDFHX4TS U9299 ( .A(n5430), .B(n5429), .CI(n5428), .CO(n5433), .S(n5452) );
ADDFHX4TS U9300 ( .A(n3513), .B(n3512), .CI(n3511), .CO(n4715), .S(n3514) );
ADDFHX4TS U9301 ( .A(n3457), .B(n3456), .CI(n3455), .CO(n4492), .S(n3511) );
ADDFHX4TS U9302 ( .A(n3496), .B(n3495), .CI(n3494), .CO(n3513), .S(n3556) );
XNOR2X4TS U9303 ( .A(n3432), .B(n1303), .Y(n6037) );
XNOR2X4TS U9304 ( .A(n1492), .B(n1946), .Y(n4342) );
OAI21X4TS U9305 ( .A0(n2658), .A1(n3367), .B0(n3318), .Y(n3371) );
XNOR2X4TS U9306 ( .A(n2092), .B(n1717), .Y(n7015) );
XNOR2X4TS U9307 ( .A(n2570), .B(n2033), .Y(n8613) );
XNOR2X4TS U9308 ( .A(n5256), .B(Op_MY[26]), .Y(n7278) );
ADDFHX4TS U9309 ( .A(n6364), .B(n6363), .CI(n6362), .CO(n6368), .S(n6370) );
ADDFHX4TS U9310 ( .A(n6346), .B(n6345), .CI(n6344), .CO(n6366), .S(n6363) );
ADDFHX4TS U9311 ( .A(n5116), .B(n5115), .CI(n5114), .CO(n5121), .S(n5123) );
ADDHX1TS U9312 ( .A(n6104), .B(n6103), .CO(n6109), .S(n6111) );
OAI21X4TS U9313 ( .A0(n9213), .A1(n9211), .B0(n9214), .Y(n9225) );
NAND2X2TS U9314 ( .A(n7732), .B(n11390), .Y(n9211) );
XNOR2X4TS U9315 ( .A(n2328), .B(n2566), .Y(n3649) );
XNOR2X4TS U9316 ( .A(n2483), .B(n2566), .Y(n5222) );
XNOR2X4TS U9317 ( .A(n2590), .B(DP_OP_168J26_122_4811_n6562), .Y(n5301) );
XNOR2X4TS U9318 ( .A(n5254), .B(n2566), .Y(n3960) );
XNOR2X4TS U9319 ( .A(n7273), .B(n2566), .Y(n4545) );
XNOR2X4TS U9320 ( .A(n2094), .B(n2566), .Y(n8008) );
XNOR2X4TS U9321 ( .A(n2092), .B(n2566), .Y(n7257) );
ADDFHX2TS U9322 ( .A(n7520), .B(n1414), .CI(n7519), .CO(n7546), .S(n7505) );
AOI21X4TS U9323 ( .A0(n10235), .A1(n10232), .B0(n6137), .Y(n10224) );
XNOR2X4TS U9324 ( .A(n954), .B(n1715), .Y(n5884) );
ADDFHX4TS U9325 ( .A(n7300), .B(n7298), .CI(n7299), .CO(n7316), .S(n8178) );
ADDFHX4TS U9326 ( .A(n7177), .B(n7176), .CI(n7175), .CO(n7318), .S(n7299) );
ADDFHX4TS U9327 ( .A(n5266), .B(n5264), .CI(n5265), .CO(n5356), .S(n5358) );
ADDFHX4TS U9328 ( .A(n5244), .B(n5243), .CI(n5242), .CO(n5264), .S(n5208) );
ADDFHX4TS U9329 ( .A(n7463), .B(n7462), .CI(n7461), .CO(n7499), .S(n7433) );
ADDFHX4TS U9330 ( .A(n4790), .B(n4789), .CI(n4788), .CO(n7462), .S(n4800) );
MXI2X2TS U9331 ( .A(n10328), .B(n11948), .S0(n11167), .Y(n604) );
NAND2X4TS U9332 ( .A(n10057), .B(n8760), .Y(n8762) );
XNOR2X4TS U9333 ( .A(n2632), .B(n1946), .Y(n5927) );
XNOR2X4TS U9334 ( .A(n2238), .B(n2251), .Y(n4092) );
ADDFHX2TS U9335 ( .A(n5882), .B(n5880), .CI(n5881), .CO(n6346), .S(n5889) );
XNOR2X4TS U9336 ( .A(n2238), .B(n8897), .Y(n8532) );
XNOR2X4TS U9337 ( .A(n3632), .B(n3631), .Y(n3633) );
NAND2X6TS U9338 ( .A(n8825), .B(n7928), .Y(n9407) );
ADDFHX4TS U9339 ( .A(n7483), .B(n7482), .CI(n7481), .CO(n7503), .S(n7500) );
OAI22X4TS U9340 ( .A0(n8466), .A1(n8577), .B0(n5491), .B1(n8933), .Y(n8468)
);
XNOR2X4TS U9341 ( .A(n2022), .B(n8533), .Y(n5491) );
XNOR2X4TS U9342 ( .A(n8889), .B(n1928), .Y(n8575) );
XNOR2X4TS U9343 ( .A(n1284), .B(n7242), .Y(n4430) );
ADDFHX4TS U9344 ( .A(n6299), .B(n6298), .CI(n6297), .CO(n9816), .S(n8586) );
AOI21X2TS U9345 ( .A0(n7592), .A1(n9503), .B0(n7591), .Y(n7593) );
XNOR2X2TS U9346 ( .A(n1979), .B(n2625), .Y(n4991) );
XOR2X4TS U9347 ( .A(n11740), .B(n2625), .Y(n4862) );
XNOR2X4TS U9348 ( .A(n2068), .B(n2625), .Y(n4965) );
XNOR2X4TS U9349 ( .A(n5174), .B(n2625), .Y(n4836) );
XNOR2X4TS U9350 ( .A(n5256), .B(n2625), .Y(n5166) );
XNOR2X4TS U9351 ( .A(n2455), .B(n2625), .Y(n5255) );
XNOR2X4TS U9352 ( .A(n7270), .B(n2625), .Y(n3817) );
XNOR2X4TS U9353 ( .A(n7353), .B(DP_OP_168J26_122_4811_n8477), .Y(n3673) );
NAND2X4TS U9354 ( .A(n2526), .B(n6566), .Y(n10733) );
ADDFHX4TS U9355 ( .A(n8004), .B(n8003), .CI(n8002), .CO(n8030), .S(n8040) );
ADDFHX2TS U9356 ( .A(n8001), .B(n8000), .CI(n7999), .CO(n8002), .S(n8051) );
CMPR22X2TS U9357 ( .A(n5050), .B(n5051), .CO(n5081), .S(n5089) );
XNOR2X4TS U9358 ( .A(n1006), .B(DP_OP_168J26_122_4811_n8448), .Y(n6017) );
XNOR2X4TS U9359 ( .A(n7655), .B(n7654), .Y(n7822) );
XNOR2X4TS U9360 ( .A(n2094), .B(n7272), .Y(n7014) );
BUFX20TS U9361 ( .A(n4059), .Y(n8510) );
XNOR2X4TS U9362 ( .A(n3626), .B(n3625), .Y(n3627) );
NAND2X4TS U9363 ( .A(n6667), .B(n6686), .Y(n9740) );
ADDFHX4TS U9364 ( .A(n6031), .B(n6030), .CI(n6029), .CO(n6632), .S(n6686) );
XNOR2X4TS U9365 ( .A(n1006), .B(n1303), .Y(n6012) );
OAI21X4TS U9366 ( .A0(n7916), .A1(n7907), .B0(n7906), .Y(n7908) );
XNOR2X4TS U9367 ( .A(n8444), .B(n2251), .Y(n8585) );
XNOR2X4TS U9368 ( .A(n4003), .B(n1024), .Y(n4071) );
ADDFHX4TS U9369 ( .A(n7081), .B(n7080), .CI(n7079), .CO(n7586), .S(n7581) );
ADDFHX4TS U9370 ( .A(n7238), .B(n7237), .CI(n7236), .CO(n7079), .S(n7294) );
XNOR2X4TS U9371 ( .A(n1805), .B(n1253), .Y(n6013) );
XOR2X4TS U9372 ( .A(n11528), .B(n731), .Y(n6018) );
XNOR2X4TS U9373 ( .A(n2445), .B(n1303), .Y(n6179) );
XNOR2X4TS U9374 ( .A(n7888), .B(n11545), .Y(n7940) );
NAND2X2TS U9375 ( .A(n10242), .B(n10239), .Y(n6136) );
ADDFHX4TS U9376 ( .A(n6270), .B(n6269), .CI(n6268), .CO(n6464), .S(n6468) );
XNOR2X4TS U9377 ( .A(n2022), .B(n6562), .Y(n6564) );
BUFX20TS U9378 ( .A(n5504), .Y(n6562) );
OR2X8TS U9379 ( .A(n7743), .B(n1154), .Y(n10664) );
XOR2X4TS U9380 ( .A(n7696), .B(n7695), .Y(n7743) );
OAI21X4TS U9381 ( .A0(n8781), .A1(n9517), .B0(n8782), .Y(n9530) );
XOR2X4TS U9382 ( .A(n2068), .B(n1645), .Y(n3819) );
NOR2X4TS U9383 ( .A(n6286), .B(n6287), .Y(n10166) );
ADDFHX4TS U9384 ( .A(n5742), .B(n5741), .CI(n5740), .CO(n6288), .S(n6287) );
XNOR2X4TS U9385 ( .A(n7353), .B(n5237), .Y(n7996) );
XNOR2X4TS U9386 ( .A(n2505), .B(n1946), .Y(n8630) );
ADDFHX4TS U9387 ( .A(n7227), .B(n7226), .CI(n7225), .CO(n7414), .S(n7317) );
ADDFHX4TS U9388 ( .A(n8122), .B(n8121), .CI(n8120), .CO(n8143), .S(n8211) );
ADDFHX4TS U9389 ( .A(n8053), .B(n8052), .CI(n8051), .CO(n8041), .S(n8121) );
XNOR2X4TS U9390 ( .A(n8921), .B(n2037), .Y(n4294) );
XNOR2X4TS U9391 ( .A(n7842), .B(n11537), .Y(n7923) );
XNOR2X4TS U9392 ( .A(n7835), .B(n11536), .Y(n7922) );
XNOR2X4TS U9393 ( .A(n7442), .B(n7488), .Y(n4431) );
ADDFHX4TS U9394 ( .A(n7135), .B(n7134), .CI(n7133), .CO(n7596), .S(n7589) );
XNOR2X4TS U9395 ( .A(n7847), .B(n11548), .Y(n7924) );
XNOR2X4TS U9396 ( .A(n7649), .B(n7648), .Y(n7821) );
OAI21X4TS U9397 ( .A0(n7916), .A1(n7868), .B0(n7651), .Y(n7649) );
XNOR2X4TS U9398 ( .A(n951), .B(n5561), .Y(n7042) );
ADDFHX2TS U9399 ( .A(n7240), .B(n7241), .CI(n7239), .CO(n7238), .S(n7550) );
XNOR2X4TS U9400 ( .A(n8921), .B(n1905), .Y(n4299) );
NAND2X4TS U9401 ( .A(n1178), .B(n1145), .Y(n7643) );
ADDFHX4TS U9402 ( .A(n4969), .B(n4968), .CI(n4967), .CO(n4951), .S(n5126) );
ADDFHX4TS U9403 ( .A(n5098), .B(n5097), .CI(n5096), .CO(n4967), .S(n5130) );
ADDFHX4TS U9404 ( .A(n5021), .B(n5020), .CI(n5019), .CO(n5124), .S(n5032) );
ADDFHX2TS U9405 ( .A(n5022), .B(n5023), .CI(n5024), .CO(n5116), .S(n5019) );
AOI21X4TS U9406 ( .A0(n11298), .A1(n11297), .B0(n5043), .Y(n11305) );
ADDFHX4TS U9407 ( .A(n6340), .B(n6339), .CI(n6338), .CO(n8563), .S(n8554) );
ADDFHX4TS U9408 ( .A(n9791), .B(n9790), .CI(n9789), .CO(n9810), .S(n9888) );
ADDFHX4TS U9409 ( .A(n5990), .B(n5991), .CI(n5989), .CO(n6282), .S(n6276) );
XNOR2X4TS U9410 ( .A(n978), .B(n1024), .Y(n8910) );
ADDFHX4TS U9411 ( .A(n5835), .B(n5834), .CI(n5833), .CO(n6286), .S(n6285) );
ADDFHX4TS U9412 ( .A(n9978), .B(n9977), .CI(n9976), .CO(n9989), .S(n9970) );
ADDFHX4TS U9413 ( .A(n9025), .B(n9024), .CI(n9023), .CO(n9980), .S(n9978) );
ADDFHX4TS U9414 ( .A(n5119), .B(n5117), .CI(n5118), .CO(n5129), .S(n5120) );
ADDFHX4TS U9415 ( .A(n5107), .B(n5106), .CI(n5105), .CO(n5117), .S(n5125) );
OAI22X2TS U9416 ( .A0(n7490), .A1(n2643), .B0(n7489), .B1(
DP_OP_168J26_122_4811_n7818), .Y(n7039) );
BUFX20TS U9417 ( .A(n6069), .Y(n6174) );
XNOR2X4TS U9418 ( .A(n2070), .B(n1813), .Y(n6007) );
XOR2X4TS U9419 ( .A(n7751), .B(n7692), .Y(n7744) );
ADDFHX4TS U9420 ( .A(n8268), .B(n8267), .CI(n8266), .CO(n8285), .S(n8287) );
ADDFHX4TS U9421 ( .A(n5978), .B(n5977), .CI(n5976), .CO(n6000), .S(n8267) );
XNOR2X4TS U9422 ( .A(n7881), .B(n11541), .Y(n7931) );
NOR2X4TS U9423 ( .A(n10060), .B(n8380), .Y(n8382) );
ADDFHX4TS U9424 ( .A(n7200), .B(n7199), .CI(n7198), .CO(n7598), .S(n7595) );
MXI2X4TS U9425 ( .A(n10297), .B(n12134), .S0(n11171), .Y(n627) );
ADDFHX4TS U9426 ( .A(n7344), .B(n7343), .CI(n7342), .CO(n8770), .S(n8767) );
OAI22X4TS U9427 ( .A0(n2089), .A1(n6141), .B0(n6080), .B1(n1227), .Y(n9737)
);
BUFX20TS U9428 ( .A(n5507), .Y(n6435) );
XNOR2X4TS U9429 ( .A(n3917), .B(n3313), .Y(n5507) );
XNOR2X4TS U9430 ( .A(n6145), .B(n1303), .Y(n6102) );
XOR2X4TS U9431 ( .A(n6161), .B(n1860), .Y(n5758) );
ADDFHX4TS U9432 ( .A(n4211), .B(n4209), .CI(n4210), .CO(n6295), .S(n6297) );
ADDFHX4TS U9433 ( .A(n4269), .B(n4268), .CI(n4267), .CO(n4328), .S(n6294) );
ADDFHX4TS U9434 ( .A(n6258), .B(n6257), .CI(n6256), .CO(n6421), .S(n6413) );
ADDFHX4TS U9435 ( .A(n6255), .B(n6254), .CI(n6253), .CO(n6239), .S(n6256) );
ADDFHX4TS U9436 ( .A(n6267), .B(n6266), .CI(n6265), .CO(n6257), .S(n6268) );
XNOR2X4TS U9437 ( .A(n2092), .B(n7279), .Y(n7995) );
XNOR2X4TS U9438 ( .A(n1807), .B(n1817), .Y(n5590) );
XNOR2X4TS U9439 ( .A(n3591), .B(n8548), .Y(n4005) );
ADDFHX2TS U9440 ( .A(n5711), .B(n5712), .CI(n5710), .CO(n5714), .S(n5761) );
ADDFHX4TS U9441 ( .A(n5074), .B(n5073), .CI(n5072), .CO(n6668), .S(n6709) );
XNOR2X4TS U9442 ( .A(n2074), .B(n1228), .Y(n3526) );
XNOR2X4TS U9443 ( .A(n2464), .B(n1807), .Y(n5795) );
XNOR2X4TS U9444 ( .A(n1565), .B(n2453), .Y(n4072) );
ADDFHX4TS U9445 ( .A(n4252), .B(n4251), .CI(n4250), .CO(n4053), .S(n5364) );
XNOR2X4TS U9446 ( .A(n7780), .B(n7779), .Y(n7803) );
OAI21X2TS U9447 ( .A0(n2072), .A1(n7864), .B0(n7863), .Y(n7865) );
XNOR2X4TS U9448 ( .A(n2549), .B(n1926), .Y(n4367) );
ADDFHX4TS U9449 ( .A(n7295), .B(n7294), .CI(n7293), .CO(n7582), .S(n7580) );
ADDFHX4TS U9450 ( .A(n7550), .B(n7549), .CI(n7548), .CO(n7293), .S(n7578) );
XNOR2X4TS U9451 ( .A(n1029), .B(n1292), .Y(n4141) );
OAI21X2TS U9452 ( .A0(n8406), .A1(n8405), .B0(n9052), .Y(n8407) );
ADDFHX4TS U9453 ( .A(n9448), .B(n9446), .CI(n9447), .CO(n10103), .S(n7425)
);
XNOR2X4TS U9454 ( .A(n2505), .B(n2283), .Y(n4006) );
XNOR2X4TS U9455 ( .A(n2069), .B(n2430), .Y(n4978) );
XNOR2X2TS U9456 ( .A(n5254), .B(n878), .Y(n5224) );
XNOR2X4TS U9457 ( .A(n7273), .B(n2430), .Y(n5323) );
XNOR2X4TS U9458 ( .A(n1979), .B(n2430), .Y(n4973) );
XNOR2X4TS U9459 ( .A(n2091), .B(n2430), .Y(n3714) );
XNOR2X4TS U9460 ( .A(n1881), .B(n1816), .Y(n3527) );
OAI21X2TS U9461 ( .A0(n9552), .A1(n9546), .B0(n9553), .Y(n7817) );
XNOR2X4TS U9462 ( .A(n4069), .B(n11502), .Y(n6601) );
ADDFHX4TS U9463 ( .A(n5436), .B(n5435), .CI(n5434), .CO(n9793), .S(n8587) );
XNOR2X4TS U9464 ( .A(n3936), .B(n11755), .Y(n4358) );
CMPR22X2TS U9465 ( .A(n6024), .B(n6023), .CO(n6028), .S(n6042) );
XOR2X4TS U9466 ( .A(n7727), .B(n11571), .Y(n7725) );
ADDFHX4TS U9467 ( .A(n8059), .B(n8057), .CI(n8058), .CO(n8229), .S(n8226) );
ADDFHX4TS U9468 ( .A(n7119), .B(n7118), .CI(n7117), .CO(n7588), .S(n7585) );
ADDFHX4TS U9469 ( .A(n7077), .B(n7078), .CI(n7076), .CO(n7117), .S(n7080) );
ADDFHX4TS U9470 ( .A(n7109), .B(n7108), .CI(n7107), .CO(n7114), .S(n7118) );
XNOR2X4TS U9471 ( .A(n3591), .B(n1929), .Y(n4263) );
XNOR2X4TS U9472 ( .A(n3776), .B(n3769), .Y(n6892) );
ADDFHX4TS U9473 ( .A(n4928), .B(n4927), .CI(n4926), .CO(n6422), .S(n6425) );
XNOR2X4TS U9474 ( .A(n7439), .B(n916), .Y(n3895) );
BUFX20TS U9475 ( .A(n3644), .Y(n8980) );
XNOR2X4TS U9476 ( .A(n3608), .B(n3607), .Y(n3609) );
ADDFHX2TS U9477 ( .A(n3709), .B(n3708), .CI(n3707), .CO(n3750), .S(n3808) );
XNOR2X4TS U9478 ( .A(n6055), .B(n1810), .Y(n3529) );
NOR2X8TS U9479 ( .A(n7594), .B(n9642), .Y(n8341) );
ADDFHX4TS U9480 ( .A(n9128), .B(n9127), .CI(n9126), .CO(n9962), .S(n9959) );
NOR2X2TS U9481 ( .A(n6781), .B(n6780), .Y(n10333) );
ADDFHX4TS U9482 ( .A(n8145), .B(n8143), .CI(n8144), .CO(n8224), .S(n8215) );
XNOR2X4TS U9483 ( .A(n1196), .B(n11579), .Y(n7718) );
ADDFHX4TS U9484 ( .A(n6240), .B(n6239), .CI(n6238), .CO(n6275), .S(n6414) );
XOR2X4TS U9485 ( .A(n7723), .B(n11576), .Y(n7724) );
XNOR2X4TS U9486 ( .A(n2409), .B(n2091), .Y(n4676) );
XNOR2X4TS U9487 ( .A(n7770), .B(n7769), .Y(n7804) );
ADDFHX4TS U9488 ( .A(n4315), .B(n4314), .CI(n4313), .CO(n6386), .S(n6384) );
ADDFHX4TS U9489 ( .A(n3914), .B(n3913), .CI(n3912), .CO(n4314), .S(n4377) );
ADDFHX4TS U9490 ( .A(n3557), .B(n3556), .CI(n3555), .CO(n3515), .S(n4313) );
ADDFHX4TS U9491 ( .A(n7375), .B(n7374), .CI(n7373), .CO(n8773), .S(n8769) );
ADDFHX2TS U9492 ( .A(n3807), .B(n3806), .CI(n3805), .CO(n3809), .S(n3858) );
ADDFHX4TS U9493 ( .A(n8500), .B(n8499), .CI(n8498), .CO(
DP_OP_168J26_122_4811_n1487), .S(n8776) );
ADDFHX4TS U9494 ( .A(n9949), .B(n9948), .CI(n9947), .CO(n4820), .S(n9950) );
XNOR2X4TS U9495 ( .A(n7242), .B(n1694), .Y(n4429) );
NAND2X6TS U9496 ( .A(n4351), .B(n3365), .Y(n4350) );
XNOR2X4TS U9497 ( .A(n3451), .B(DP_OP_168J26_122_4811_n8245), .Y(n5801) );
ADDFHX4TS U9498 ( .A(n3969), .B(n3968), .CI(n3967), .CO(n4628), .S(n3965) );
BUFX20TS U9499 ( .A(n7627), .Y(n7916) );
ADDFHX4TS U9500 ( .A(n9909), .B(n9910), .CI(n9908), .CO(
DP_OP_168J26_122_4811_n1319), .S(DP_OP_168J26_122_4811_n1320) );
XNOR2X4TS U9501 ( .A(n5561), .B(n1228), .Y(n4190) );
XNOR2X4TS U9502 ( .A(n1312), .B(n7442), .Y(n4165) );
OAI22X4TS U9503 ( .A0(n2096), .A1(n5034), .B0(n5036), .B1(n793), .Y(n6793)
);
OAI21X2TS U9504 ( .A0(n9313), .A1(n9594), .B0(n9314), .Y(n7946) );
ADDFHX4TS U9505 ( .A(n5109), .B(n5110), .CI(n5108), .CO(n5127), .S(n5128) );
ADDFHX4TS U9506 ( .A(n5464), .B(n5465), .CI(n5463), .CO(n8592), .S(n8477) );
XNOR2X4TS U9507 ( .A(n1812), .B(n2592), .Y(n5682) );
XNOR2X4TS U9508 ( .A(n8911), .B(n1967), .Y(n8936) );
AOI21X4TS U9509 ( .A0(n10174), .A1(n10155), .B0(n10154), .Y(n10170) );
CLKINVX12TS U9510 ( .A(DP_OP_168J26_122_4811_n8177), .Y(n3881) );
XNOR2X4TS U9511 ( .A(n9060), .B(n9059), .Y(Sgf_operation_ODD1_Q_left[33]) );
OR2X8TS U9512 ( .A(n10000), .B(n9999), .Y(n11776) );
XNOR2X4TS U9513 ( .A(n7766), .B(n7765), .Y(n7798) );
OAI21X4TS U9514 ( .A0(n7788), .A1(n7763), .B0(n7762), .Y(n7766) );
NOR2X8TS U9515 ( .A(n7524), .B(n7528), .Y(n7568) );
OAI21X2TS U9516 ( .A0(n10083), .A1(n8234), .B0(n10086), .Y(n8235) );
NOR2X8TS U9517 ( .A(n5829), .B(n2556), .Y(n10992) );
ADDFHX4TS U9518 ( .A(n5360), .B(n5359), .CI(n5358), .CO(n5638), .S(n5533) );
XNOR2X4TS U9519 ( .A(n2070), .B(n2669), .Y(n4175) );
XOR2X4TS U9520 ( .A(n11674), .B(n2017), .Y(n3500) );
ADDFHX4TS U9521 ( .A(n4952), .B(n4951), .CI(n4950), .CO(n6404), .S(n6405) );
MXI2X2TS U9522 ( .A(n10330), .B(n11817), .S0(n11171), .Y(n633) );
OAI21X4TS U9523 ( .A0(n10748), .A1(n9551), .B0(n9550), .Y(n9556) );
NAND2X4TS U9524 ( .A(n1708), .B(n1307), .Y(n10128) );
NAND2X4TS U9525 ( .A(n6984), .B(n6985), .Y(n8352) );
XNOR2X4TS U9526 ( .A(n9055), .B(n9054), .Y(Sgf_operation_ODD1_Q_left[38]) );
ADDFHX4TS U9527 ( .A(n6202), .B(n6201), .CI(n6200), .CO(n6539), .S(n6605) );
XOR2X4TS U9528 ( .A(n11525), .B(n2380), .Y(n5863) );
XNOR2X4TS U9529 ( .A(n7442), .B(n1302), .Y(n5663) );
ADDFHX4TS U9530 ( .A(n7389), .B(n7387), .CI(n7388), .CO(n7426), .S(n7422) );
NOR2X4TS U9531 ( .A(n6387), .B(n2289), .Y(n7559) );
ADDFHX4TS U9532 ( .A(n4716), .B(n4715), .CI(n4714), .CO(n6388), .S(n9918) );
ADDFHX4TS U9533 ( .A(n4275), .B(n4274), .CI(n4273), .CO(n5470), .S(n5469) );
NOR2X4TS U9534 ( .A(n7812), .B(n11370), .Y(n10747) );
XNOR2X4TS U9535 ( .A(n754), .B(n2653), .Y(n7368) );
XNOR2X4TS U9536 ( .A(n7233), .B(n2070), .Y(n4115) );
XOR2X4TS U9537 ( .A(n2017), .B(n2521), .Y(n4173) );
XNOR2X4TS U9538 ( .A(n6093), .B(DP_OP_168J26_122_4811_n8163), .Y(n4187) );
ADDFHX4TS U9539 ( .A(n9966), .B(n9965), .CI(n9964), .CO(
DP_OP_168J26_122_4811_n1455), .S(DP_OP_168J26_122_4811_n1456) );
ADDFHX4TS U9540 ( .A(n7544), .B(n7543), .CI(n7542), .CO(n8032), .S(n8109) );
XNOR2X4TS U9541 ( .A(n1816), .B(n7242), .Y(n3399) );
XNOR2X4TS U9542 ( .A(n7442), .B(n1813), .Y(n4105) );
ADDFHX4TS U9543 ( .A(n9272), .B(n9271), .CI(n9270), .CO(
DP_OP_168J26_122_4811_n1421), .S(DP_OP_168J26_122_4811_n1422) );
ADDFHX4TS U9544 ( .A(n8713), .B(n8712), .CI(n8711), .CO(n9956), .S(n9270) );
NAND2X4TS U9545 ( .A(n2600), .B(n1514), .Y(n7968) );
XOR2X4TS U9546 ( .A(n11624), .B(n11625), .Y(n7712) );
OAI22X4TS U9547 ( .A0(n1857), .A1(n1221), .B0(n2013), .B1(n11764), .Y(n8028)
);
INVX8TS U9548 ( .A(n10004), .Y(DP_OP_168J26_122_4811_n776) );
NOR2X8TS U9549 ( .A(DP_OP_168J26_122_4811_n8464), .B(
DP_OP_168J26_122_4811_n8489), .Y(n3569) );
OAI21X4TS U9550 ( .A0(n10732), .A1(n10728), .B0(n10733), .Y(n10721) );
ADDFHX4TS U9551 ( .A(n4631), .B(n4630), .CI(n4629), .CO(n4639), .S(n4748) );
ADDFHX4TS U9552 ( .A(n4583), .B(n4584), .CI(n4582), .CO(n4617), .S(n4629) );
ADDFHX2TS U9553 ( .A(n5233), .B(n5232), .CI(n5231), .CO(n5263), .S(n5228) );
ADDFHX4TS U9554 ( .A(n7318), .B(n7317), .CI(n7316), .CO(n7320), .S(n9485) );
XNOR2X4TS U9555 ( .A(n7878), .B(n11547), .Y(n7930) );
XNOR2X4TS U9556 ( .A(n2666), .B(n7349), .Y(n3421) );
XOR2X4TS U9557 ( .A(n2666), .B(n1670), .Y(n5675) );
XNOR2X4TS U9558 ( .A(n2666), .B(n1817), .Y(n4139) );
XNOR2X4TS U9559 ( .A(n2666), .B(n7441), .Y(n3876) );
XNOR2X4TS U9560 ( .A(n2666), .B(n7488), .Y(n5674) );
XNOR2X4TS U9561 ( .A(n2666), .B(n1284), .Y(n3536) );
XNOR2X4TS U9562 ( .A(n7233), .B(n2666), .Y(n3472) );
XNOR2X4TS U9563 ( .A(n2666), .B(n2669), .Y(n3501) );
XNOR2X4TS U9564 ( .A(n3594), .B(n3593), .Y(n5526) );
XNOR2X4TS U9565 ( .A(n2074), .B(n1253), .Y(n3894) );
BUFX20TS U9566 ( .A(n4060), .Y(n8579) );
XNOR2X4TS U9567 ( .A(n2363), .B(n2410), .Y(n8621) );
ADDFHX4TS U9568 ( .A(n7416), .B(n7415), .CI(n7414), .CO(n7421), .S(n7319) );
NOR2BX4TS U9569 ( .AN(n1809), .B(n1901), .Y(n6762) );
ADDFHX4TS U9570 ( .A(n5001), .B(n5000), .CI(n4999), .CO(n6644), .S(n6698) );
ADDFHX4TS U9571 ( .A(n5847), .B(n5846), .CI(n5845), .CO(n6373), .S(n6289) );
XNOR2X4TS U9572 ( .A(n5278), .B(n5175), .Y(n5221) );
INVX12TS U9573 ( .A(n1718), .Y(n5175) );
ADDFHX4TS U9574 ( .A(n7504), .B(n7503), .CI(n7502), .CO(n8110), .S(n8923) );
XNOR2X4TS U9575 ( .A(DP_OP_168J26_122_4811_n6776), .B(n1810), .Y(n3471) );
XNOR2X4TS U9576 ( .A(n2677), .B(n2672), .Y(n5864) );
XNOR2X4TS U9577 ( .A(n2677), .B(n1303), .Y(n5948) );
XNOR2X4TS U9578 ( .A(n2677), .B(DP_OP_168J26_122_4811_n8448), .Y(n5796) );
XNOR2X4TS U9579 ( .A(n1312), .B(n927), .Y(n5765) );
XNOR2X4TS U9580 ( .A(n2677), .B(n6156), .Y(n4135) );
ADDFHX4TS U9581 ( .A(n6724), .B(n6723), .CI(n6722), .CO(n8305), .S(n6735) );
ADDFHX4TS U9582 ( .A(n6598), .B(n6596), .CI(n6597), .CO(n6719), .S(n6723) );
XNOR2X4TS U9583 ( .A(n7439), .B(n1302), .Y(n5559) );
NOR2X4TS U9584 ( .A(n7866), .B(n1134), .Y(n7873) );
XOR2X4TS U9585 ( .A(n1223), .B(n2380), .Y(n5555) );
OR2X8TS U9586 ( .A(n6716), .B(n6715), .Y(n10041) );
XNOR2X4TS U9587 ( .A(n11500), .B(n952), .Y(n7096) );
ADDFHX4TS U9588 ( .A(n7579), .B(n7578), .CI(n7577), .CO(n7986), .S(n8100) );
ADDFHX4TS U9589 ( .A(n5439), .B(n5438), .CI(n5437), .CO(n8672), .S(n8622) );
XNOR2X4TS U9590 ( .A(n7255), .B(n1839), .Y(n7276) );
ADDFHX4TS U9591 ( .A(n5204), .B(n5203), .CI(n5202), .CO(n5747), .S(n5736) );
XNOR2X4TS U9592 ( .A(n1808), .B(n1237), .Y(n4195) );
XNOR2X4TS U9593 ( .A(n1303), .B(n1306), .Y(n5568) );
ADDFHX4TS U9594 ( .A(n3766), .B(n3765), .CI(n3764), .CO(n5476), .S(n5475) );
XOR2X4TS U9595 ( .A(n7700), .B(n7699), .Y(n9207) );
AOI21X2TS U9596 ( .A0(n7729), .A1(n11573), .B0(n1128), .Y(n7700) );
ADDFHX4TS U9597 ( .A(n9870), .B(n9869), .CI(n9868), .CO(
DP_OP_168J26_122_4811_n1285), .S(DP_OP_168J26_122_4811_n1286) );
ADDFHX4TS U9598 ( .A(n7254), .B(n7252), .CI(n7253), .CO(n8231), .S(n8228) );
ADDFHX4TS U9599 ( .A(n5125), .B(n5124), .CI(n5123), .CO(n6579), .S(n6613) );
XNOR2X4TS U9600 ( .A(DP_OP_168J26_122_4811_n6794), .B(n1669), .Y(n4134) );
ADDFHX4TS U9601 ( .A(n8503), .B(n8502), .CI(n8501), .CO(n8775), .S(n9997) );
BUFX20TS U9602 ( .A(DP_OP_168J26_122_4811_n8242), .Y(n5721) );
ADDFHX4TS U9603 ( .A(n4391), .B(n4390), .CI(n4389), .CO(n5473), .S(n5471) );
ADDFHX4TS U9604 ( .A(n7434), .B(n7433), .CI(n7432), .CO(n8941), .S(n8996) );
ADDFHX4TS U9605 ( .A(n7501), .B(n7500), .CI(n7499), .CO(n8928), .S(n8940) );
OAI22X2TS U9606 ( .A0(n2077), .A1(n2448), .B0(n1883), .B1(n1303), .Y(n4137)
);
OR2X8TS U9607 ( .A(n10001), .B(n10002), .Y(n11734) );
ADDFHX4TS U9608 ( .A(n4379), .B(n4378), .CI(n4377), .CO(n6383), .S(n6378) );
ADDFHX4TS U9609 ( .A(n4329), .B(n4328), .CI(n4327), .CO(n6377), .S(n6376) );
XNOR2X4TS U9610 ( .A(n2473), .B(n8548), .Y(n8549) );
NOR2X4TS U9611 ( .A(n2597), .B(n1662), .Y(n9759) );
ADDFHX4TS U9612 ( .A(n5818), .B(n5817), .CI(n5816), .CO(n6284), .S(n6283) );
ADDFHX4TS U9613 ( .A(n8322), .B(n8321), .CI(n8320), .CO(n8323), .S(n8309) );
XNOR2X4TS U9614 ( .A(n5561), .B(n1312), .Y(n5578) );
XNOR2X4TS U9615 ( .A(n6093), .B(n7233), .Y(n5589) );
BUFX20TS U9616 ( .A(Op_MY[47]), .Y(n7233) );
NAND2X8TS U9617 ( .A(DP_OP_168J26_122_4811_n6587), .B(
DP_OP_168J26_122_4811_n6615), .Y(n4022) );
XNOR2X4TS U9618 ( .A(n11525), .B(n952), .Y(n7446) );
XNOR2X4TS U9619 ( .A(n1811), .B(n7438), .Y(n5554) );
XNOR2X4TS U9620 ( .A(n1027), .B(n8548), .Y(n8515) );
XNOR2X4TS U9621 ( .A(n1582), .B(n1966), .Y(n4687) );
OAI21X4TS U9622 ( .A0(n9408), .A1(n7936), .B0(n7935), .Y(n7937) );
ADDFHX4TS U9623 ( .A(n8306), .B(n8305), .CI(n8304), .CO(n9132), .S(n7009) );
ADDFHX4TS U9624 ( .A(n4750), .B(n4748), .CI(n4749), .CO(n5485), .S(n5479) );
XNOR2X4TS U9625 ( .A(n6145), .B(n1810), .Y(n4114) );
NOR2X8TS U9626 ( .A(n11614), .B(n11615), .Y(n7752) );
NOR2X4TS U9627 ( .A(n10771), .B(n8808), .Y(n8825) );
ADDFHX4TS U9628 ( .A(n4587), .B(n4586), .CI(n4585), .CO(n6398), .S(n6393) );
NOR2X4TS U9629 ( .A(n1671), .B(n8985), .Y(n8213) );
ADDFHX4TS U9630 ( .A(n8209), .B(n8208), .CI(n8207), .CO(n8900), .S(n8985) );
XNOR2X4TS U9631 ( .A(n7273), .B(n1885), .Y(n4230) );
ADDFHX4TS U9632 ( .A(n8212), .B(n8210), .CI(n8211), .CO(n8216), .S(n8913) );
NOR2X4TS U9633 ( .A(n9532), .B(n9539), .Y(n7824) );
ADDFHX4TS U9634 ( .A(n8176), .B(n8174), .CI(n8175), .CO(n10002), .S(n9999)
);
XNOR2X2TS U9635 ( .A(n1818), .B(n2058), .Y(n4637) );
ADDFHX4TS U9636 ( .A(n8286), .B(n8285), .CI(n8284), .CO(n9996), .S(n8715) );
OAI21X4TS U9637 ( .A0(n7839), .A1(n11591), .B0(n7838), .Y(n7872) );
ADDFHX2TS U9638 ( .A(n7055), .B(n7056), .CI(n7057), .CO(n7068), .S(n7063) );
ADDFHX4TS U9639 ( .A(n4816), .B(n4814), .CI(n4815), .CO(n8191), .S(n8190) );
ADDFHX4TS U9640 ( .A(n9972), .B(n9971), .CI(n9970), .CO(n9984), .S(n9032) );
ADDFHX4TS U9641 ( .A(n7419), .B(n7418), .CI(n7417), .CO(n7423), .S(n7420) );
BUFX20TS U9642 ( .A(n3524), .Y(n7492) );
XNOR2X4TS U9643 ( .A(n11580), .B(n945), .Y(n7054) );
XNOR2X4TS U9644 ( .A(n3946), .B(n3935), .Y(n4059) );
NOR2X4TS U9645 ( .A(n10477), .B(n10476), .Y(n11323) );
NAND2X8TS U9646 ( .A(DP_OP_168J26_122_4811_n8196), .B(n5572), .Y(n5571) );
OAI21X2TS U9647 ( .A0(n1825), .A1(n9656), .B0(n9655), .Y(n9662) );
XNOR2X4TS U9648 ( .A(n11683), .B(n1645), .Y(n7083) );
ADDFHX4TS U9649 ( .A(n9957), .B(n9956), .CI(n9955), .CO(
DP_OP_168J26_122_4811_n1387), .S(DP_OP_168J26_122_4811_n1388) );
ADDFHX4TS U9650 ( .A(n9954), .B(n9953), .CI(n9952), .CO(
DP_OP_168J26_122_4811_n1389), .S(n9955) );
ADDFHX4TS U9651 ( .A(n9876), .B(n9875), .CI(n9874), .CO(n9881), .S(n4819) );
OAI21X4TS U9652 ( .A0(n9439), .A1(n9433), .B0(n9440), .Y(n9418) );
CMPR22X2TS U9653 ( .A(n5610), .B(n5609), .CO(n5670), .S(n5615) );
ADDFHX4TS U9654 ( .A(n4640), .B(n4639), .CI(n4638), .CO(n8189), .S(n5484) );
ADDFHX4TS U9655 ( .A(n8292), .B(n8291), .CI(n8290), .CO(n8310), .S(n8308) );
ADDFHX4TS U9656 ( .A(n4753), .B(n4752), .CI(n4751), .CO(n5480), .S(n5477) );
OAI21X4TS U9657 ( .A0(n8808), .A1(n10772), .B0(n8809), .Y(n8826) );
ADDFHX4TS U9658 ( .A(n8197), .B(n8195), .CI(n8196), .CO(n8986), .S(n8192) );
BUFX20TS U9659 ( .A(n4350), .Y(n9457) );
ADDFHX4TS U9660 ( .A(n6358), .B(n6357), .CI(n6356), .CO(n8553), .S(n8593) );
XNOR2X4TS U9661 ( .A(n3915), .B(DP_OP_168J26_122_4811_n3219), .Y(n5493) );
ADDFHX4TS U9662 ( .A(n9963), .B(n9962), .CI(n9961), .CO(
DP_OP_168J26_122_4811_n1005), .S(DP_OP_168J26_122_4811_n1006) );
XNOR2X4TS U9663 ( .A(n7755), .B(n7754), .Y(n7794) );
OAI21X2TS U9664 ( .A0(n7751), .A1(n7750), .B0(n11556), .Y(n7755) );
XNOR2X4TS U9665 ( .A(n1306), .B(n2672), .Y(n3482) );
OAI21X4TS U9666 ( .A0(n9264), .A1(n11002), .B0(n9265), .Y(n5361) );
ADDFHX4TS U9667 ( .A(n4810), .B(n4809), .CI(n4808), .CO(n7529), .S(n6397) );
NOR2X4TS U9668 ( .A(n9524), .B(n9552), .Y(n7818) );
NOR2X4TS U9669 ( .A(n9213), .B(n8722), .Y(n9223) );
NOR2X2TS U9670 ( .A(n7733), .B(n11389), .Y(n9213) );
XOR2X4TS U9671 ( .A(n11500), .B(n7438), .Y(n7038) );
XNOR2X4TS U9672 ( .A(n2092), .B(n7272), .Y(n7084) );
BUFX20TS U9673 ( .A(Op_MY[21]), .Y(n7272) );
XNOR2X4TS U9674 ( .A(n2403), .B(n760), .Y(n7037) );
XNOR2X4TS U9675 ( .A(n2397), .B(n2074), .Y(n4432) );
NOR2X4TS U9676 ( .A(n6386), .B(n6385), .Y(n9056) );
ADDFHX4TS U9677 ( .A(n3516), .B(n3515), .CI(n3514), .CO(n6387), .S(n6385) );
ADDFHX4TS U9678 ( .A(n8289), .B(n8288), .CI(n8287), .CO(n8714), .S(n8430) );
XNOR2X4TS U9679 ( .A(n7678), .B(n7677), .Y(n7813) );
ADDFHX4TS U9680 ( .A(n7003), .B(n7002), .CI(n7001), .CO(n7006), .S(n7005) );
ADDFHX4TS U9681 ( .A(n9993), .B(n9992), .CI(n9991), .CO(n10000), .S(n9994)
);
XNOR2X4TS U9682 ( .A(n7917), .B(n11540), .Y(n7945) );
XNOR2X4TS U9683 ( .A(n5270), .B(n2566), .Y(n3849) );
NOR2X4TS U9684 ( .A(n10060), .B(n8213), .Y(n10064) );
ADDFHX4TS U9685 ( .A(n6681), .B(n6680), .CI(n6679), .CO(n6717), .S(n6716) );
NAND2X8TS U9686 ( .A(DP_OP_168J26_122_4811_n6586), .B(
DP_OP_168J26_122_4811_n6614), .Y(n3814) );
BUFX20TS U9687 ( .A(n2150), .Y(n7491) );
ADDFHX4TS U9688 ( .A(n9990), .B(n9988), .CI(n9989), .CO(n9995), .S(n9983) );
ADDFHX4TS U9689 ( .A(n5122), .B(n5121), .CI(n5120), .CO(n6542), .S(n6600) );
AND2X8TS U9690 ( .A(n4093), .B(DP_OP_168J26_122_4811_n3609), .Y(n6633) );
AND2X8TS U9691 ( .A(n11740), .B(n7444), .Y(n3916) );
OR2X8TS U9692 ( .A(n6938), .B(n6937), .Y(n9371) );
NAND2X8TS U9693 ( .A(n1624), .B(n1275), .Y(n3390) );
BUFX20TS U9694 ( .A(n3393), .Y(n7477) );
XNOR2X4TS U9695 ( .A(n7353), .B(n5235), .Y(n4595) );
ADDFHX4TS U9696 ( .A(n7000), .B(n6999), .CI(n6998), .CO(n7004), .S(n6985) );
ADDFHX4TS U9697 ( .A(n6372), .B(n6371), .CI(n6370), .CO(n8471), .S(n6374) );
ADDFHX4TS U9698 ( .A(n6801), .B(n6800), .CI(n6799), .CO(n6874), .S(n6873) );
NOR2X4TS U9699 ( .A(n10522), .B(n10521), .Y(n10602) );
BUFX20TS U9700 ( .A(n1705), .Y(n7277) );
AOI21X4TS U9701 ( .A0(n10092), .A1(n9295), .B0(n9294), .Y(n9296) );
AOI21X2TS U9702 ( .A0(n9654), .A1(n8422), .B0(n1365), .Y(n8423) );
NAND2X8TS U9703 ( .A(n3599), .B(n5505), .Y(n3600) );
XOR2X4TS U9704 ( .A(n3994), .B(n3993), .Y(n6465) );
XNOR2X4TS U9705 ( .A(n9574), .B(n9573), .Y(Sgf_operation_ODD1_Q_left[48]) );
XNOR2X4TS U9706 ( .A(n9583), .B(n9582), .Y(Sgf_operation_ODD1_Q_left[43]) );
NOR2X4TS U9707 ( .A(n7032), .B(n1970), .Y(n7034) );
NAND2X8TS U9708 ( .A(DP_OP_168J26_122_4811_n8189), .B(n4428), .Y(n4455) );
ADDFHX4TS U9709 ( .A(n8751), .B(n8750), .CI(n8749), .CO(n8429), .S(n10008)
);
XNOR2X4TS U9710 ( .A(n7442), .B(DP_OP_168J26_122_4811_n8461), .Y(n4792) );
XNOR2X4TS U9711 ( .A(n7277), .B(n5237), .Y(n3815) );
XOR2X4TS U9712 ( .A(n3615), .B(n3614), .Y(n4485) );
XOR2X4TS U9713 ( .A(n4062), .B(n11741), .Y(n4063) );
ADDFHX4TS U9714 ( .A(n4747), .B(n4746), .CI(n4745), .CO(n6392), .S(n6389) );
XNOR2X4TS U9715 ( .A(n2363), .B(n3322), .Y(n7170) );
XOR2X4TS U9716 ( .A(n3636), .B(n3635), .Y(n4087) );
XNOR2X4TS U9717 ( .A(n7731), .B(n11569), .Y(n7734) );
NAND2X8TS U9718 ( .A(n3659), .B(DP_OP_168J26_122_4811_n6613), .Y(n3677) );
XNOR2X2TS U9719 ( .A(n8627), .B(n2057), .Y(n7192) );
NOR2X4TS U9720 ( .A(n9046), .B(n8396), .Y(n8398) );
NAND2X2TS U9721 ( .A(n8390), .B(n8393), .Y(n8396) );
NOR2X4TS U9722 ( .A(n7292), .B(n1920), .Y(n8084) );
NOR2X8TS U9723 ( .A(n8835), .B(n9439), .Y(n9416) );
XNOR2X4TS U9724 ( .A(n7884), .B(n11535), .Y(n7932) );
NOR2X8TS U9725 ( .A(n8777), .B(n8781), .Y(n9527) );
NOR2X6TS U9726 ( .A(n11354), .B(n7820), .Y(n8781) );
AOI21X4TS U9727 ( .A0(n11647), .A1(n11648), .B0(n11649), .Y(n7698) );
XOR2X4TS U9728 ( .A(n3596), .B(n3595), .Y(n5505) );
XNOR2X4TS U9729 ( .A(n9372), .B(n7431), .Y(n7576) );
ADDFHX4TS U9730 ( .A(n8303), .B(n8302), .CI(n8301), .CO(n8307), .S(n9131) );
AOI21X4TS U9731 ( .A0(n10695), .A1(n10692), .B0(n7796), .Y(n8876) );
BUFX20TS U9732 ( .A(n3814), .Y(n5309) );
NOR2X4TS U9733 ( .A(n8232), .B(n2426), .Y(n8234) );
ADDFHX4TS U9734 ( .A(n7149), .B(n7147), .CI(n7148), .CO(n8238), .S(n8232) );
NOR2X8TS U9735 ( .A(n740), .B(n8488), .Y(n10143) );
ADDFHX4TS U9736 ( .A(n6369), .B(n6368), .CI(n6367), .CO(n8662), .S(n8488) );
ADDFHX4TS U9737 ( .A(n8753), .B(n8754), .CI(n8752), .CO(n10007), .S(n8324)
);
ADDFHX4TS U9738 ( .A(n6933), .B(n6932), .CI(n6931), .CO(n6939), .S(n6938) );
ADDFHX4TS U9739 ( .A(n6982), .B(n6981), .CI(n6980), .CO(n6983), .S(n6940) );
NAND2X4TS U9740 ( .A(n2289), .B(n6387), .Y(n8326) );
NOR2X8TS U9741 ( .A(n9061), .B(n9065), .Y(n9599) );
XNOR2X4TS U9742 ( .A(n3788), .B(DP_OP_168J26_122_4811_n3224), .Y(n6402) );
INVX2TS U9743 ( .A(n1367), .Y(n9575) );
INVX2TS U9744 ( .A(n9740), .Y(n10232) );
AND2X2TS U9745 ( .A(n10073), .B(n10078), .Y(n3306) );
INVX2TS U9746 ( .A(n9462), .Y(n9753) );
XNOR2X4TS U9747 ( .A(DP_OP_168J26_122_4811_n8538), .B(
DP_OP_168J26_122_4811_n8511), .Y(n3313) );
INVX2TS U9748 ( .A(n7557), .Y(n8329) );
CLKBUFX3TS U9749 ( .A(n12221), .Y(n12226) );
INVX2TS U9750 ( .A(n9321), .Y(n9335) );
MXI2X1TS U9751 ( .A(n10598), .B(exp_oper_result[0]), .S0(n11068), .Y(n3323)
);
BUFX3TS U9752 ( .A(n11129), .Y(n11989) );
BUFX3TS U9753 ( .A(n11129), .Y(n11990) );
INVX2TS U9754 ( .A(n7836), .Y(n7830) );
INVX2TS U9755 ( .A(n7669), .Y(n7680) );
AOI21X1TS U9756 ( .A0(n7862), .A1(n7861), .B0(n7860), .Y(n7863) );
INVX2TS U9757 ( .A(n7640), .Y(n7634) );
INVX2TS U9758 ( .A(n9603), .Y(n9074) );
INVX2TS U9759 ( .A(Data_MX[41]), .Y(n9713) );
INVX2TS U9760 ( .A(Data_MX[30]), .Y(n9698) );
INVX4TS U9761 ( .A(n10385), .Y(n11318) );
INVX2TS U9762 ( .A(n7974), .Y(n7976) );
INVX2TS U9763 ( .A(n10166), .Y(n10168) );
INVX2TS U9764 ( .A(n9763), .Y(n10183) );
INVX2TS U9765 ( .A(n10215), .Y(n10217) );
INVX2TS U9766 ( .A(n9759), .Y(n10173) );
INVX2TS U9767 ( .A(n7964), .Y(n7967) );
INVX2TS U9768 ( .A(n10156), .Y(n10158) );
INVX2TS U9769 ( .A(n9579), .Y(n9581) );
INVX2TS U9770 ( .A(n10110), .Y(n10112) );
INVX2TS U9771 ( .A(n8332), .Y(n8334) );
INVX2TS U9772 ( .A(Data_MX[36]), .Y(n9681) );
INVX2TS U9773 ( .A(Data_MY[46]), .Y(n9684) );
INVX2TS U9774 ( .A(Data_MX[33]), .Y(n9685) );
INVX2TS U9775 ( .A(Data_MY[48]), .Y(n10324) );
INVX2TS U9776 ( .A(Data_MY[26]), .Y(n11164) );
INVX2TS U9777 ( .A(Data_MY[59]), .Y(n11161) );
INVX2TS U9778 ( .A(Data_MX[56]), .Y(n11138) );
XOR2X1TS U9779 ( .A(n670), .B(n9666), .Y(n11484) );
INVX2TS U9780 ( .A(n10256), .Y(n11565) );
NAND2X2TS U9781 ( .A(n2138), .B(n10875), .Y(n12345) );
AOI2BB1X4TS U9782 ( .A0N(n12055), .A1N(n12054), .B0(n12053), .Y(n11099) );
NOR2X8TS U9783 ( .A(n3325), .B(n10950), .Y(n10344) );
NAND2X8TS U9784 ( .A(n10344), .B(n11798), .Y(n9688) );
MXI2X4TS U9785 ( .A(n3326), .B(n11951), .S0(n11153), .Y(n614) );
INVX2TS U9786 ( .A(Data_MY[37]), .Y(n3328) );
MXI2X2TS U9787 ( .A(n3328), .B(n11950), .S0(n10310), .Y(n619) );
INVX2TS U9788 ( .A(Data_MY[10]), .Y(n3329) );
NOR2X4TS U9789 ( .A(n9255), .B(n3331), .Y(n3332) );
NOR2X8TS U9790 ( .A(n8790), .B(n11099), .Y(n8787) );
INVX2TS U9791 ( .A(n10507), .Y(n3334) );
NAND2X1TS U9792 ( .A(n3334), .B(n10506), .Y(n3337) );
XNOR2X1TS U9793 ( .A(n3337), .B(n10505), .Y(n10598) );
NAND2X4TS U9794 ( .A(n11887), .B(FS_Module_state_reg[1]), .Y(n9256) );
AND2X8TS U9795 ( .A(n12217), .B(n11242), .Y(n11126) );
INVX2TS U9796 ( .A(Data_MX[55]), .Y(n3338) );
MXI2X1TS U9797 ( .A(n3338), .B(n11829), .S0(n11148), .Y(n3339) );
INVX2TS U9798 ( .A(n3339), .Y(n11336) );
MXI2X4TS U9799 ( .A(n3340), .B(n11896), .S0(n9724), .Y(n9726) );
NAND2X1TS U9800 ( .A(n3366), .B(n3369), .Y(n3342) );
OAI22X1TS U9801 ( .A0(n3791), .A1(n2331), .B0(n4518), .B1(n9456), .Y(n4697)
);
AND2X2TS U9802 ( .A(n3754), .B(n3381), .Y(n3382) );
AND2X2TS U9803 ( .A(DP_OP_168J26_122_4811_n8467), .B(Op_MY[21]), .Y(n3379)
);
XOR2X4TS U9804 ( .A(n3387), .B(n3386), .Y(n5783) );
BUFX8TS U9805 ( .A(DP_OP_168J26_122_4811_n8223), .Y(n6040) );
XOR2X4TS U9806 ( .A(n1702), .B(n1703), .Y(n3392) );
CLKINVX12TS U9807 ( .A(n11505), .Y(n4428) );
BUFX8TS U9808 ( .A(DP_OP_168J26_122_4811_n8216), .Y(n7471) );
OAI21X2TS U9809 ( .A0(n3559), .A1(n3606), .B0(n1344), .Y(n3560) );
XOR2X4TS U9810 ( .A(DP_OP_168J26_122_4811_n8537), .B(
DP_OP_168J26_122_4811_n8510), .Y(n3578) );
NAND2X1TS U9811 ( .A(n3586), .B(n3584), .Y(n3581) );
NOR2X2TS U9812 ( .A(n3617), .B(n3616), .Y(n3618) );
OAI22X1TS U9813 ( .A0(n4080), .A1(n1886), .B0(n4405), .B1(n2055), .Y(n3763)
);
NAND2X1TS U9814 ( .A(n11555), .B(n3630), .Y(n3631) );
OAI22X1TS U9815 ( .A0(n3760), .A1(n2051), .B0(n4300), .B1(n1987), .Y(n3761)
);
OAI22X1TS U9816 ( .A0(n3654), .A1(n1936), .B0(n1988), .B1(n3981), .Y(n3970)
);
OAI22X1TS U9817 ( .A0(n3768), .A1(n1982), .B0(n3767), .B1(n6883), .Y(n4401)
);
NAND2X1TS U9818 ( .A(n11747), .B(DP_OP_168J26_122_4811_n3572), .Y(n3777) );
NOR2XLTS U9819 ( .A(n7031), .B(n3789), .Y(n3948) );
ADDFHX4TS U9820 ( .A(n3869), .B(n3868), .CI(n3867), .CO(n4282), .S(n4284) );
OAI22X1TS U9821 ( .A0(n3928), .A1(n2112), .B0(n4402), .B1(n2575), .Y(n3988)
);
OAI22X1TS U9822 ( .A0(n3931), .A1(n2293), .B0(n3930), .B1(n1893), .Y(n3986)
);
NOR2X2TS U9823 ( .A(n3937), .B(DP_OP_168J26_122_4811_n3486), .Y(n3940) );
XNOR2X4TS U9824 ( .A(n3995), .B(n3992), .Y(n3994) );
NAND2X2TS U9825 ( .A(n4069), .B(n11502), .Y(n3993) );
OAI22X2TS U9826 ( .A0(n4065), .A1(n8908), .B0(n4071), .B1(n9755), .Y(n4090)
);
XNOR2X4TS U9827 ( .A(n793), .B(n2261), .Y(n4067) );
OAI22X1TS U9828 ( .A0(n4083), .A1(n1969), .B0(n8629), .B1(n2950), .Y(n4290)
);
NAND2BX1TS U9829 ( .AN(n6633), .B(n1971), .Y(n4096) );
OAI22X1TS U9830 ( .A0(n6174), .A1(n5648), .B0(n2038), .B1(n4196), .Y(n5871)
);
OAI22X1TS U9831 ( .A0(n4300), .A1(n2051), .B0(n4299), .B1(n1987), .Y(n4305)
);
CMPR32X2TS U9832 ( .A(n4308), .B(n4309), .C(n4307), .CO(n4325), .S(n9773) );
OAI22X1TS U9833 ( .A0(n4346), .A1(n1892), .B0(n8565), .B1(n2067), .Y(n9840)
);
NAND2BX1TS U9834 ( .AN(n6633), .B(n4488), .Y(n4352) );
ADDFHX2TS U9835 ( .A(n4372), .B(n4371), .CI(n4370), .CO(n4214), .S(n8567) );
OAI22X1TS U9836 ( .A0(n1910), .A1(n4431), .B0(n2030), .B1(n4456), .Y(n4464)
);
CMPR32X2TS U9837 ( .A(n4450), .B(n2672), .C(n4449), .CO(n4468), .S(n4475) );
OAI22X1TS U9838 ( .A0(n4518), .A1(n2331), .B0(n4517), .B1(n5488), .Y(n4711)
);
OAI22X1TS U9839 ( .A0(n4692), .A1(n2293), .B0(n4705), .B1(n1893), .Y(n4708)
);
OAI22X1TS U9840 ( .A0(n4804), .A1(n1987), .B0(n8981), .B1(n2051), .Y(n9002)
);
OAI22X2TS U9841 ( .A0(n4887), .A1(n2095), .B0(n4832), .B1(n5343), .Y(n4878)
);
OAI22X1TS U9842 ( .A0(n2095), .A1(n4861), .B0(n5149), .B1(n1889), .Y(n5139)
);
XNOR2X1TS U9843 ( .A(n2328), .B(n4982), .Y(n4876) );
OAI22X1TS U9844 ( .A0(n8022), .A1(n1706), .B0(n1989), .B1(n4877), .Y(n4908)
);
OAI22X1TS U9845 ( .A0(n2096), .A1(n4964), .B0(n4957), .B1(n11758), .Y(n5103)
);
AOI21X4TS U9846 ( .A0(n11058), .A1(n5071), .B0(n5070), .Y(n10622) );
OAI22X1TS U9847 ( .A0(n1820), .A1(n5169), .B0(n2048), .B1(n5224), .Y(n5231)
);
ADDFHX4TS U9848 ( .A(n5195), .B(n5194), .CI(n5193), .CO(n5225), .S(n5204) );
XNOR2X1TS U9849 ( .A(n6633), .B(n4484), .Y(n5490) );
XNOR2X1TS U9850 ( .A(n8444), .B(n8897), .Y(n5540) );
OAI22X1TS U9851 ( .A0(n5513), .A1(n1862), .B0(n5532), .B1(n1908), .Y(n5744)
);
OAI22X1TS U9852 ( .A0(n5543), .A1(n2112), .B0(n5542), .B1(n2575), .Y(n5691)
);
OAI22X1TS U9853 ( .A0(n1084), .A1(n5591), .B0(n974), .B1(n5555), .Y(n5630)
);
OAI22X1TS U9854 ( .A0(n2379), .A1(n5588), .B0(n1897), .B1(n5579), .Y(n5601)
);
OAI22X1TS U9855 ( .A0(n6087), .A1(n5685), .B0(n1939), .B1(n5684), .Y(n5865)
);
ADDFHX4TS U9856 ( .A(n5734), .B(n5733), .CI(n5732), .CO(n5699), .S(n5980) );
OAI22X1TS U9857 ( .A0(n6174), .A1(n5800), .B0(n11757), .B1(n5757), .Y(n5808)
);
OAI22X1TS U9858 ( .A0(n5925), .A1(n2113), .B0(n2575), .B1(n5785), .Y(n5932)
);
OAI22X1TS U9859 ( .A0(n5926), .A1(n1940), .B0(n5944), .B1(n2067), .Y(n5992)
);
OAI22X1TS U9860 ( .A0(n6472), .A1(n1982), .B0(n5928), .B1(n6883), .Y(n6483)
);
OAI22X1TS U9861 ( .A0(n6478), .A1(n2099), .B0(n5939), .B1(n6885), .Y(n6496)
);
OAI22X1TS U9862 ( .A0(n5940), .A1(n8516), .B0(n6460), .B1(n8518), .Y(n6420)
);
OAI22X1TS U9863 ( .A0(n2090), .A1(n6143), .B0(n5961), .B1(n6142), .Y(n6220)
);
ADDFHX4TS U9864 ( .A(n6000), .B(n5998), .CI(n5999), .CO(n8502), .S(n8284) );
BUFX20TS U9865 ( .A(DP_OP_168J26_122_4811_n8187), .Y(n6714) );
NOR2X6TS U9866 ( .A(n6611), .B(n1330), .Y(n10226) );
OAI22X1TS U9867 ( .A0(n823), .A1(n6102), .B0(n2450), .B1(n6100), .Y(n6110)
);
NOR2X2TS U9868 ( .A(n10246), .B(n10262), .Y(n6115) );
OAI22X1TS U9869 ( .A0(n1853), .A1(n6151), .B0(n2062), .B1(n6153), .Y(n6157)
);
NOR2X6TS U9870 ( .A(n2493), .B(n6555), .Y(n10215) );
AOI21X4TS U9871 ( .A0(n9745), .A1(n6281), .B0(n6280), .Y(n9758) );
NOR2X4TS U9872 ( .A(n10156), .B(n10166), .Y(n6291) );
NOR2X4TS U9873 ( .A(n10175), .B(n9759), .Y(n10155) );
OAI21X2TS U9874 ( .A0(n10156), .A1(n10167), .B0(n10157), .Y(n6290) );
OAI21X4TS U9875 ( .A0(n9758), .A1(n6293), .B0(n6292), .Y(n7956) );
NOR2X4TS U9876 ( .A(n10138), .B(n10132), .Y(n6375) );
AOI21X4TS U9877 ( .A0(n7956), .A1(n6381), .B0(n6380), .Y(n6382) );
NAND2X1TS U9878 ( .A(n9047), .B(n7565), .Y(n6396) );
AOI21X1TS U9879 ( .A0(n9049), .A1(n7565), .B0(n6394), .Y(n6395) );
OAI21X2TS U9880 ( .A0(n1824), .A1(n6396), .B0(n6395), .Y(n6401) );
INVX2TS U9881 ( .A(n7528), .Y(n6399) );
XNOR2X4TS U9882 ( .A(n6401), .B(n6400), .Y(Sgf_operation_ODD1_Q_left[37]) );
OAI22X4TS U9883 ( .A0(n8977), .A1(n8087), .B0(n2052), .B1(n6406), .Y(n6429)
);
OAI22X1TS U9884 ( .A0(n6450), .A1(n1945), .B0(n8574), .B1(n6543), .Y(n6545)
);
OAI22X1TS U9885 ( .A0(n6424), .A1(n1852), .B0(n6467), .B1(n6919), .Y(n6491)
);
OAI22X1TS U9886 ( .A0(n6424), .A1(n6919), .B0(n6423), .B1(n1852), .Y(n6497)
);
OAI22X1TS U9887 ( .A0(n6450), .A1(n1982), .B0(n6883), .B1(n6449), .Y(n6455)
);
OAI22X1TS U9888 ( .A0(n6473), .A1(n1983), .B0(n6472), .B1(n1944), .Y(n6486)
);
OAI22X1TS U9889 ( .A0(n6477), .A1(n8907), .B0(n6476), .B1(n785), .Y(n6490)
);
OAI22X1TS U9890 ( .A0(n6481), .A1(n8641), .B0(n6480), .B1(n8643), .Y(n6488)
);
XNOR2X1TS U9891 ( .A(n4003), .B(n5504), .Y(n6558) );
OAI22X1TS U9892 ( .A0(n6535), .A1(n2504), .B0(n6558), .B1(n8907), .Y(n6577)
);
ADDFHX2TS U9893 ( .A(n6538), .B(n6537), .CI(n6536), .CO(n6446), .S(n6576) );
OAI22X1TS U9894 ( .A0(n6599), .A1(n2099), .B0(n6553), .B1(n1961), .Y(n6595)
);
XNOR2X1TS U9895 ( .A(n3345), .B(n6529), .Y(n6587) );
OAI22X1TS U9896 ( .A0(n6587), .A1(n2108), .B0(n6565), .B1(n1955), .Y(n6591)
);
XNOR2X1TS U9897 ( .A(n8534), .B(n6636), .Y(n6606) );
OAI22X1TS U9898 ( .A0(n6580), .A1(n1944), .B0(n6606), .B1(n1982), .Y(n6627)
);
OAI22X1TS U9899 ( .A0(n6586), .A1(n1932), .B0(n6630), .B1(n1416), .Y(n6619)
);
NAND2X1TS U9900 ( .A(n6620), .B(n6623), .Y(n6604) );
OAI22X1TS U9901 ( .A0(n6606), .A1(n1945), .B0(n6643), .B1(n8574), .Y(n6654)
);
ADDFHX4TS U9902 ( .A(n6614), .B(n6616), .CI(n6615), .CO(n6729), .S(n6649) );
XOR2X4TS U9903 ( .A(n6622), .B(n6623), .Y(n6712) );
XNOR2X1TS U9904 ( .A(n2020), .B(n6775), .Y(n6656) );
OAI22X1TS U9905 ( .A0(n6656), .A1(n2097), .B0(n6639), .B1(n6885), .Y(n6665)
);
XNOR2X1TS U9906 ( .A(n1954), .B(n3345), .Y(n6669) );
OAI22X1TS U9907 ( .A0(n6669), .A1(n8614), .B0(n6645), .B1(n1852), .Y(n6663)
);
XNOR2X1TS U9908 ( .A(n8534), .B(n6775), .Y(n6666) );
ADDFHX4TS U9909 ( .A(n6684), .B(n6682), .CI(n6683), .CO(n6680), .S(n6988) );
OAI22X1TS U9910 ( .A0(n6685), .A1(n1932), .B0(n6699), .B1(n1968), .Y(n6959)
);
OAI22X1TS U9911 ( .A0(n6922), .A1(n1953), .B0(n6704), .B1(n1852), .Y(n6950)
);
ADDFHX4TS U9912 ( .A(n6713), .B(n6712), .CI(n6711), .CO(n6677), .S(n6986) );
ADDFHX4TS U9913 ( .A(n6736), .B(n6734), .CI(n6735), .CO(n7008), .S(n6718) );
XNOR2X1TS U9914 ( .A(n8534), .B(n6529), .Y(n6752) );
OAI22X1TS U9915 ( .A0(n6785), .A1(n2647), .B0(n6808), .B1(n8643), .Y(n6814)
);
OAI22X1TS U9916 ( .A0(n6824), .A1(n8612), .B0(n6836), .B1(n1953), .Y(n6860)
);
CMPR32X2TS U9917 ( .A(n9737), .B(n6833), .C(n6834), .CO(n6840), .S(n6843) );
NOR2X2TS U9918 ( .A(n6851), .B(n6850), .Y(n9329) );
NOR2BX1TS U9919 ( .AN(n2591), .B(n793), .Y(n11183) );
NOR2BX1TS U9920 ( .AN(n6884), .B(n8612), .Y(n9339) );
ADDFHX4TS U9921 ( .A(n6880), .B(n6879), .CI(n6878), .CO(n6908), .S(n6896) );
CMPR22X2TS U9922 ( .A(n6895), .B(n6894), .CO(n6912), .S(n6878) );
OAI22X1TS U9923 ( .A0(n6918), .A1(n1933), .B0(n6917), .B1(n1985), .Y(n6947)
);
OAI22X1TS U9924 ( .A0(n6924), .A1(n1955), .B0(n6923), .B1(n2109), .Y(n6945)
);
NAND2X4TS U9925 ( .A(n6939), .B(n2164), .Y(n9374) );
ADDFHX4TS U9926 ( .A(n6959), .B(n6958), .CI(n6957), .CO(n6997), .S(n6993) );
XNOR2X1TS U9927 ( .A(n8620), .B(n2057), .Y(n7013) );
OAI22X1TS U9928 ( .A0(n7182), .A1(n1935), .B0(n7013), .B1(n9456), .Y(n7186)
);
OAI22X1TS U9929 ( .A0(n7013), .A1(n9457), .B0(n7171), .B1(n2050), .Y(n7167)
);
OAI22X1TS U9930 ( .A0(n1814), .A1(n7244), .B0(n2060), .B1(n7042), .Y(n7239)
);
NOR2X2TS U9931 ( .A(n7048), .B(n1907), .Y(n7184) );
OAI22X1TS U9932 ( .A0(n7304), .A1(n2588), .B0(n7082), .B1(n2056), .Y(n7288)
);
OAI22X1TS U9933 ( .A0(n2422), .A1(n7086), .B0(n2115), .B1(n7139), .Y(n7143)
);
OAI22X1TS U9934 ( .A0(n2434), .A1(n1718), .B0(n2550), .B1(n2527), .Y(n7089)
);
OAI22X1TS U9935 ( .A0(n2411), .A1(n7084), .B0(n1950), .B1(n7083), .Y(n7088)
);
OAI22X1TS U9936 ( .A0(n7160), .A1(n2545), .B0(n2054), .B1(n5496), .Y(n7211)
);
OAI22X1TS U9937 ( .A0(n7192), .A1(n9457), .B0(n7328), .B1(n5488), .Y(n7332)
);
CLKINVX1TS U9938 ( .A(n2363), .Y(n7202) );
NOR2X2TS U9939 ( .A(n7202), .B(n1920), .Y(n7333) );
OAI22X1TS U9940 ( .A0(n8062), .A1(n1935), .B0(n7306), .B1(n5488), .Y(n8078)
);
INVX2TS U9941 ( .A(n2505), .Y(n7361) );
OAI22X1TS U9942 ( .A0(n7379), .A1(n1935), .B0(n7409), .B1(n4351), .Y(n7392)
);
OAI22X1TS U9943 ( .A0(n7380), .A1(n2165), .B0(n7410), .B1(n2036), .Y(n7391)
);
CMPR32X2TS U9944 ( .A(n7398), .B(n7399), .C(n7400), .CO(n9465), .S(n7408) );
OAI22X1TS U9945 ( .A0(n2434), .A1(n12030), .B0(n765), .B1(n11955), .Y(n9460)
);
INVX2TS U9946 ( .A(n1059), .Y(n7402) );
OAI22X1TS U9947 ( .A0(n7409), .A1(n1935), .B0(n5488), .B1(n1038), .Y(n9450)
);
OAI22X1TS U9948 ( .A0(n7410), .A1(n2165), .B0(n9452), .B1(n4095), .Y(n9449)
);
INVX6TS U9949 ( .A(n2458), .Y(n9372) );
OAI22X1TS U9950 ( .A0(n1914), .A1(n7480), .B0(n2060), .B1(n7478), .Y(n7519)
);
NAND2X1TS U9951 ( .A(n8110), .B(n867), .Y(n8401) );
XNOR2X4TS U9952 ( .A(n7555), .B(n7554), .Y(Sgf_operation_ODD1_Q_left[42]) );
XNOR2X4TS U9953 ( .A(n7561), .B(n7560), .Y(Sgf_operation_ODD1_Q_left[34]) );
XNOR2X4TS U9954 ( .A(n7567), .B(n7566), .Y(Sgf_operation_ODD1_Q_left[36]) );
NAND2X1TS U9955 ( .A(n9047), .B(n7570), .Y(n7572) );
AOI21X2TS U9956 ( .A0(n1033), .A1(n7570), .B0(n7569), .Y(n7571) );
XNOR2X4TS U9957 ( .A(n7575), .B(n7574), .Y(Sgf_operation_ODD1_Q_left[40]) );
OR2X2TS U9958 ( .A(n7588), .B(n7587), .Y(n9512) );
NAND2X1TS U9959 ( .A(n9648), .B(n9647), .Y(n7604) );
AOI21X4TS U9960 ( .A0(n7584), .A1(n9576), .B0(n7583), .Y(n8339) );
NAND2X1TS U9961 ( .A(n7588), .B(n7587), .Y(n9511) );
OR2X2TS U9962 ( .A(n7606), .B(n7605), .Y(n9651) );
XNOR2X4TS U9963 ( .A(n7608), .B(n7607), .Y(Sgf_operation_ODD1_Q_left[50]) );
NOR2X6TS U9964 ( .A(n7674), .B(n7683), .Y(n7625) );
ADDFHX4TS U9965 ( .A(n11689), .B(n11690), .CI(n11691), .CO(n7609), .S(n7619)
);
NOR2X8TS U9966 ( .A(n11661), .B(n11662), .Y(n7693) );
NAND2X2TS U9967 ( .A(n7616), .B(n7690), .Y(n7618) );
NAND2X2TS U9968 ( .A(n7622), .B(n1170), .Y(n7684) );
CLKINVX1TS U9969 ( .A(n7647), .Y(n7629) );
XNOR2X4TS U9970 ( .A(n7632), .B(n7631), .Y(n7819) );
NAND2X1TS U9971 ( .A(n7641), .B(n7634), .Y(n7636) );
AOI21X1TS U9972 ( .A0(n7647), .A1(n7634), .B0(n7633), .Y(n7635) );
OAI21X2TS U9973 ( .A0(n2072), .A1(n7636), .B0(n7635), .Y(n7639) );
XNOR2X4TS U9974 ( .A(n7639), .B(n7638), .Y(n7820) );
NAND2X1TS U9975 ( .A(n7855), .B(n7650), .Y(n7653) );
OR2X8TS U9976 ( .A(n11659), .B(n11660), .Y(n7836) );
CLKINVX6TS U9977 ( .A(n7666), .Y(n7781) );
NAND2X1TS U9978 ( .A(n7671), .B(n7781), .Y(n7673) );
NAND2X1TS U9979 ( .A(n7781), .B(n7665), .Y(n7682) );
XNOR2X4TS U9980 ( .A(n7687), .B(n7686), .Y(n7812) );
NOR2X2TS U9981 ( .A(n7826), .B(n9516), .Y(n7828) );
NAND2X1TS U9982 ( .A(n11663), .B(n11664), .Y(n7701) );
NAND2BX1TS U9983 ( .AN(n7747), .B(n10660), .Y(n7703) );
NAND2X1TS U9984 ( .A(n7708), .B(n9175), .Y(n7710) );
AOI21X1TS U9985 ( .A0(n7708), .A1(n9177), .B0(n7707), .Y(n7709) );
NAND2X1TS U9986 ( .A(n11461), .B(n11458), .Y(n9156) );
AOI21X1TS U9987 ( .A0(n11461), .A1(n7711), .B0(n11459), .Y(n9155) );
NAND2X1TS U9988 ( .A(n7718), .B(n11403), .Y(n8744) );
NAND2X1TS U9989 ( .A(n9223), .B(n7737), .Y(n7739) );
NAND2X1TS U9990 ( .A(n7733), .B(n11395), .Y(n9214) );
OAI21X4TS U9991 ( .A0(n9212), .A1(n7739), .B0(n7738), .Y(n9206) );
AND2X2TS U9992 ( .A(n9207), .B(n1153), .Y(n7742) );
NAND2X1TS U9993 ( .A(n7784), .B(n7782), .Y(n7769) );
NAND2X1TS U9994 ( .A(n7781), .B(n7784), .Y(n7787) );
INVX2TS U9995 ( .A(n7782), .Y(n7783) );
OAI21X2TS U9996 ( .A0(n7788), .A1(n7787), .B0(n7786), .Y(n7793) );
INVX2TS U9997 ( .A(n7789), .Y(n7791) );
NOR2X6TS U9998 ( .A(n8850), .B(n8854), .Y(n7809) );
AOI21X4TS U9999 ( .A0(n7818), .A1(n9548), .B0(n7817), .Y(n9515) );
OA21X4TS U10000 ( .A0(n9515), .A1(n7826), .B0(n7825), .Y(n7827) );
OAI2BB1X4TS U10001 ( .A0N(n7828), .A1N(n7979), .B0(n7827), .Y(n7829) );
NOR2X1TS U10002 ( .A(n7837), .B(n7830), .Y(n7832) );
NAND2X1TS U10003 ( .A(n7855), .B(n7832), .Y(n7834) );
AOI21X1TS U10004 ( .A0(n7862), .A1(n7832), .B0(n7831), .Y(n7833) );
NAND2X1TS U10005 ( .A(n7855), .B(n7867), .Y(n7841) );
AOI21X1TS U10006 ( .A0(n7862), .A1(n7867), .B0(n7872), .Y(n7840) );
NOR2X1TS U10007 ( .A(n7854), .B(n1181), .Y(n7844) );
NAND2X1TS U10008 ( .A(n7855), .B(n7844), .Y(n7846) );
AOI21X1TS U10009 ( .A0(n7862), .A1(n7844), .B0(n7843), .Y(n7845) );
NAND2X1TS U10010 ( .A(n7855), .B(n7849), .Y(n7851) );
AOI21X1TS U10011 ( .A0(n7862), .A1(n7849), .B0(n7848), .Y(n7850) );
NAND2X1TS U10012 ( .A(n7855), .B(n7861), .Y(n7864) );
NAND2X1TS U10013 ( .A(n7910), .B(n11773), .Y(n7887) );
NAND2X1TS U10014 ( .A(n7910), .B(n7890), .Y(n7892) );
XNOR2X4TS U10015 ( .A(n7893), .B(n11539), .Y(n7941) );
NAND2X1TS U10016 ( .A(n7910), .B(n7895), .Y(n7897) );
XNOR2X4TS U10017 ( .A(n7898), .B(n11544), .Y(n7938) );
XNOR2X4TS U10018 ( .A(n7905), .B(n11543), .Y(n7939) );
NAND2X1TS U10019 ( .A(n11438), .B(n11439), .Y(n7920) );
XNOR2X4TS U10020 ( .A(n7954), .B(n11347), .Y(n7955) );
OAI2BB1X4TS U10021 ( .A0N(n1209), .A1N(n7955), .B0(n12178), .Y(n10879) );
NAND2X1TS U10022 ( .A(n7971), .B(n10124), .Y(n7973) );
XOR2X4TS U10023 ( .A(n7978), .B(n7977), .Y(add_x_19_n313) );
CLKINVX6TS U10024 ( .A(n9516), .Y(n9529) );
NAND2X1TS U10025 ( .A(n9527), .B(n9529), .Y(n7981) );
OAI22X1TS U10026 ( .A0(n8146), .A1(n8579), .B0(n8082), .B1(n2056), .Y(n8132)
);
OAI22X1TS U10027 ( .A0(n8111), .A1(n2545), .B0(n8099), .B1(n2055), .Y(n8963)
);
OAI22X1TS U10028 ( .A0(n8891), .A1(n2588), .B0(n8146), .B1(n2056), .Y(n8904)
);
AOI21X4TS U10029 ( .A0(n8188), .A1(n8187), .B0(n8186), .Y(n8223) );
INVX2TS U10030 ( .A(n8213), .Y(n10059) );
NAND2X1TS U10031 ( .A(n8241), .B(n8240), .Y(n8757) );
ADDFHX4TS U10032 ( .A(n8316), .B(n8315), .CI(n8314), .CO(n8282), .S(n8753)
);
NAND2X1TS U10033 ( .A(n8325), .B(n8328), .Y(n8331) );
AOI21X1TS U10034 ( .A0(n8329), .A1(n8328), .B0(n8327), .Y(n8330) );
OAI21X4TS U10035 ( .A0(n8331), .A1(n1825), .B0(n8330), .Y(n8336) );
CLKINVX6TS U10036 ( .A(n8337), .Y(n9639) );
AOI21X4TS U10037 ( .A0(n9638), .A1(n8341), .B0(n8340), .Y(n9567) );
XNOR2X4TS U10038 ( .A(n8350), .B(n8349), .Y(Sgf_operation_ODD1_Q_left[49])
);
INVX4TS U10039 ( .A(n8355), .Y(n8364) );
NAND2X1TS U10040 ( .A(n8364), .B(n8362), .Y(n8356) );
XNOR2X4TS U10041 ( .A(n8357), .B(n8356), .Y(n9627) );
CLKINVX1TS U10042 ( .A(n8362), .Y(n8363) );
INVX2TS U10043 ( .A(n9292), .Y(n8375) );
AOI21X1TS U10044 ( .A0(n10069), .A1(n8378), .B0(n8377), .Y(n8379) );
OAI21X2TS U10045 ( .A0(n10062), .A1(n8380), .B0(n8379), .Y(n8381) );
XNOR2X4TS U10046 ( .A(n8388), .B(n8387), .Y(Sgf_operation_ODD1_Q_right[41])
);
AOI21X1TS U10047 ( .A0(n9049), .A1(n8398), .B0(n8397), .Y(n8399) );
NAND2X1TS U10048 ( .A(n9047), .B(n8408), .Y(n8410) );
XNOR2X4TS U10049 ( .A(n8414), .B(n8413), .Y(Sgf_operation_ODD1_Q_left[39])
);
NAND2X1TS U10050 ( .A(n8418), .B(n8417), .Y(n8420) );
NAND2X1TS U10051 ( .A(n1009), .B(n8798), .Y(n8434) );
CLKINVX1TS U10052 ( .A(n8799), .Y(n8432) );
ADDFHX4TS U10053 ( .A(n8469), .B(n8468), .CI(n8467), .CO(n8504), .S(n8474)
);
ADDFHX4TS U10054 ( .A(n8480), .B(n8478), .CI(n8479), .CO(n8499), .S(n8501)
);
OAI22X1TS U10055 ( .A0(n8532), .A1(n1987), .B0(n1823), .B1(n8531), .Y(n8546)
);
OAI22X1TS U10056 ( .A0(n8621), .A1(n1968), .B0(n8631), .B1(n1933), .Y(n8623)
);
INVX2TS U10057 ( .A(Sgf_operation_ODD1_Q_left[34]), .Y(add_x_19_n278) );
INVX2TS U10058 ( .A(Sgf_operation_ODD1_Q_left[36]), .Y(add_x_19_n252) );
NAND2X1TS U10059 ( .A(n9210), .B(n9211), .Y(n8723) );
XNOR2X1TS U10060 ( .A(n9231), .B(n8723), .Y(n8724) );
INVX2TS U10061 ( .A(n8730), .Y(n8726) );
NAND2X1TS U10062 ( .A(n8726), .B(n8729), .Y(n8727) );
XOR2X1TS U10063 ( .A(n8731), .B(n8727), .Y(n8728) );
INVX2TS U10064 ( .A(n8732), .Y(n8734) );
NAND2X1TS U10065 ( .A(n8734), .B(n8733), .Y(n8735) );
AOI21X1TS U10066 ( .A0(n9152), .A1(n8742), .B0(n8741), .Y(n8747) );
INVX2TS U10067 ( .A(n8743), .Y(n8745) );
NAND2X1TS U10068 ( .A(n8745), .B(n8744), .Y(n8746) );
XOR2X1TS U10069 ( .A(n8747), .B(n8746), .Y(n8748) );
NAND2X1TS U10070 ( .A(n8768), .B(n8767), .Y(n9302) );
NAND2X1TS U10071 ( .A(n9529), .B(n9518), .Y(n8780) );
OAI21X4TS U10072 ( .A0(n9255), .A1(n11803), .B0(n8788), .Y(n8789) );
NAND2X4TS U10073 ( .A(n9255), .B(n8790), .Y(n8791) );
AOI22X1TS U10074 ( .A0(n11249), .A1(Add_result[16]), .B0(
Sgf_normalized_result[15]), .B1(n11247), .Y(n8796) );
AOI2BB2X4TS U10075 ( .B0(n10803), .B1(n489), .A0N(n10860), .A1N(n11873), .Y(
n8795) );
NAND3X2TS U10076 ( .A(n8796), .B(n8795), .C(n8794), .Y(n368) );
BUFX8TS U10077 ( .A(n10681), .Y(n10947) );
OAI21X2TS U10078 ( .A0(n2083), .A1(n8802), .B0(n8801), .Y(n8803) );
AOI2BB2X2TS U10079 ( .B0(n10947), .B1(n10969), .A0N(n10860), .A1N(n11855),
.Y(n12311) );
INVX2TS U10080 ( .A(n8808), .Y(n8810) );
OAI2BB1X4TS U10081 ( .A0N(n1214), .A1N(n8814), .B0(n8813), .Y(n492) );
NAND2X1TS U10082 ( .A(n8825), .B(n8830), .Y(n8818) );
INVX2TS U10083 ( .A(n8829), .Y(n8816) );
OAI2BB1X4TS U10084 ( .A0N(n1214), .A1N(n8824), .B0(n8823), .Y(n494) );
INVX2TS U10085 ( .A(n8825), .Y(n8828) );
INVX2TS U10086 ( .A(n8826), .Y(n8827) );
OAI2BB1X4TS U10087 ( .A0N(n12168), .A1N(n8834), .B0(n8833), .Y(n493) );
OAI2BB1X4TS U10088 ( .A0N(n1214), .A1N(n8839), .B0(n8838), .Y(n495) );
NAND2X1TS U10089 ( .A(n8845), .B(n8844), .Y(n8846) );
INVX2TS U10090 ( .A(n8854), .Y(n8856) );
NAND2X1TS U10091 ( .A(n8856), .B(n8855), .Y(n8857) );
OAI22X1TS U10092 ( .A0(n8946), .A1(n2588), .B0(n8891), .B1(n2056), .Y(n8955)
);
CMPR32X2TS U10093 ( .A(n8995), .B(n8994), .C(n8993), .CO(n8991), .S(n9101)
);
NAND2X1TS U10094 ( .A(n9047), .B(n7568), .Y(n9051) );
NAND2X1TS U10095 ( .A(n9058), .B(n9057), .Y(n9059) );
NAND2X1TS U10096 ( .A(n9071), .B(n9402), .Y(n9064) );
INVX2TS U10097 ( .A(n9401), .Y(n9062) );
INVX2TS U10098 ( .A(n9065), .Y(n9067) );
OAI2BB1X4TS U10099 ( .A0N(n1209), .A1N(n9070), .B0(n12187), .Y(n10875) );
NAND2X1TS U10100 ( .A(n10956), .B(n9599), .Y(n9073) );
OAI2BB1X4TS U10101 ( .A0N(n1197), .A1N(n9077), .B0(n12176), .Y(n10873) );
INVX2TS U10102 ( .A(n9133), .Y(n9150) );
INVX2TS U10103 ( .A(n9149), .Y(n9134) );
AOI21X1TS U10104 ( .A0(n9152), .A1(n9150), .B0(n9134), .Y(n9139) );
INVX2TS U10105 ( .A(n9135), .Y(n9137) );
NAND2X1TS U10106 ( .A(n9137), .B(n9136), .Y(n9138) );
XOR2X1TS U10107 ( .A(n9139), .B(n9138), .Y(n9140) );
AOI21X1TS U10108 ( .A0(n9152), .A1(n9142), .B0(n9141), .Y(n9147) );
INVX2TS U10109 ( .A(n9143), .Y(n9145) );
NAND2X1TS U10110 ( .A(n9145), .B(n9144), .Y(n9146) );
XOR2X1TS U10111 ( .A(n9147), .B(n9146), .Y(n9148) );
NAND2X1TS U10112 ( .A(n9150), .B(n9149), .Y(n9151) );
XNOR2X1TS U10113 ( .A(n9152), .B(n9151), .Y(n9153) );
INVX2TS U10114 ( .A(n9157), .Y(n9159) );
NAND2X1TS U10115 ( .A(n9159), .B(n9158), .Y(n9160) );
XOR2X1TS U10116 ( .A(n9166), .B(n9163), .Y(n9164) );
NAND2X1TS U10117 ( .A(n11461), .B(n11423), .Y(n9167) );
XNOR2X1TS U10118 ( .A(n9168), .B(n9167), .Y(n9169) );
AOI21X1TS U10119 ( .A0(n9191), .A1(n9175), .B0(n9177), .Y(n9173) );
INVX2TS U10120 ( .A(n9178), .Y(n9171) );
XOR2X1TS U10121 ( .A(n9173), .B(n9172), .Y(n9174) );
INVX2TS U10122 ( .A(n9175), .Y(n9176) );
NOR2X1TS U10123 ( .A(n9176), .B(n9178), .Y(n9181) );
AOI21X1TS U10124 ( .A0(n9191), .A1(n9181), .B0(n9180), .Y(n9185) );
INVX2TS U10125 ( .A(n9182), .Y(n9183) );
NAND2X1TS U10126 ( .A(n9183), .B(n11416), .Y(n9184) );
XOR2X1TS U10127 ( .A(n9185), .B(n9184), .Y(n9186) );
XOR2X1TS U10128 ( .A(n9188), .B(n9187), .Y(n9189) );
INVX2TS U10129 ( .A(n9193), .Y(n9201) );
OAI21X1TS U10130 ( .A0(n9201), .A1(n11406), .B0(n11407), .Y(n9194) );
XNOR2X1TS U10131 ( .A(n9194), .B(n11397), .Y(n9195) );
INVX2TS U10132 ( .A(n9196), .Y(n9197) );
XNOR2X1TS U10133 ( .A(n9199), .B(n9198), .Y(n9200) );
XOR2X1TS U10134 ( .A(n9201), .B(n11398), .Y(n9202) );
AOI21X1TS U10135 ( .A0(n3316), .A1(n11417), .B0(n11418), .Y(n9203) );
XOR2X1TS U10136 ( .A(n9203), .B(n11399), .Y(n9204) );
XNOR2X1TS U10137 ( .A(n3316), .B(n11411), .Y(n9205) );
XOR2X1TS U10138 ( .A(n10667), .B(n9208), .Y(n9209) );
NAND2X1TS U10139 ( .A(n9215), .B(n9214), .Y(n9216) );
XOR2X1TS U10140 ( .A(n9217), .B(n9216), .Y(n9218) );
INVX2TS U10141 ( .A(n9227), .Y(n9219) );
NAND2X1TS U10142 ( .A(n9219), .B(n9226), .Y(n9220) );
INVX2TS U10143 ( .A(n9232), .Y(n9234) );
NAND2X1TS U10144 ( .A(n9234), .B(n9233), .Y(n9235) );
XNOR2X1TS U10145 ( .A(Op_MX[63]), .B(Op_MY[63]), .Y(n11134) );
CLKMX2X2TS U10146 ( .A(round_mode[0]), .B(round_mode[1]), .S0(n11134), .Y(
n9254) );
NOR4X1TS U10147 ( .A(n456), .B(n455), .C(n453), .D(n454), .Y(n9239) );
NOR4X1TS U10148 ( .A(n452), .B(n451), .C(n450), .D(n449), .Y(n9238) );
NOR4X1TS U10149 ( .A(n11834), .B(P_Sgf[25]), .C(P_Sgf[26]), .D(P_Sgf[24]),
.Y(n9243) );
NOR4X2TS U10150 ( .A(n468), .B(n11822), .C(n467), .D(n465), .Y(n9246) );
NOR2X1TS U10151 ( .A(n11798), .B(n11887), .Y(n10323) );
NOR2XLTS U10152 ( .A(n10323), .B(FS_Module_state_reg[1]), .Y(n9257) );
MXI2X1TS U10153 ( .A(n9258), .B(n9257), .S0(n11099), .Y(n9259) );
MX2X4TS U10154 ( .A(n9269), .B(n2130), .S0(n1977), .Y(n445) );
XNOR2X4TS U10155 ( .A(n9317), .B(n9316), .Y(n9318) );
OAI2BB1X4TS U10156 ( .A0N(n1217), .A1N(n9318), .B0(n12184), .Y(n10874) );
AOI21X2TS U10157 ( .A0(n9321), .A1(n9338), .B0(n9322), .Y(n9323) );
CLKINVX1TS U10158 ( .A(n9334), .Y(n9336) );
AFHCONX2TS U10159 ( .A(n9341), .B(n9340), .CI(n9339), .CON(n9332), .S(n11016) );
BUFX8TS U10160 ( .A(n10681), .Y(n10861) );
NAND2X1TS U10161 ( .A(n9071), .B(n9349), .Y(n9351) );
OAI2BB1X4TS U10162 ( .A0N(n1209), .A1N(n9353), .B0(n12177), .Y(n10883) );
AOI2BB2X2TS U10163 ( .B0(n10861), .B1(n10883), .A0N(n10870), .A1N(n11849),
.Y(n12287) );
NAND2X4TS U10164 ( .A(n1833), .B(n493), .Y(n12367) );
NAND2X4TS U10165 ( .A(n1835), .B(n492), .Y(n12370) );
NAND2X4TS U10166 ( .A(n1821), .B(n494), .Y(n12364) );
NAND2X1TS U10167 ( .A(n11436), .B(n11437), .Y(n9354) );
NAND2X4TS U10168 ( .A(n10811), .B(n11386), .Y(n10822) );
NAND2X1TS U10169 ( .A(n11434), .B(n11435), .Y(n9359) );
NOR2X2TS U10170 ( .A(n10955), .B(n9361), .Y(n9363) );
OAI21X2TS U10171 ( .A0(n2084), .A1(n9361), .B0(n9360), .Y(n9362) );
AOI21X2TS U10172 ( .A0(n2065), .A1(n9363), .B0(n9362), .Y(n9364) );
NAND2X1TS U10173 ( .A(n9373), .B(n9374), .Y(n9375) );
BUFX8TS U10174 ( .A(n11254), .Y(n11285) );
AOI22X1TS U10175 ( .A0(n11285), .A1(Add_result[48]), .B0(
Sgf_normalized_result[47]), .B1(n11281), .Y(n9398) );
NOR2X1TS U10176 ( .A(n10840), .B(n9378), .Y(n9380) );
NAND2X1TS U10177 ( .A(n10957), .B(n9380), .Y(n9381) );
OAI2BB1X4TS U10178 ( .A0N(n1195), .A1N(n9388), .B0(n12197), .Y(n10808) );
NAND2X2TS U10179 ( .A(n1821), .B(n10808), .Y(n9397) );
OAI21X2TS U10180 ( .A0(n10960), .A1(n9390), .B0(n9389), .Y(n9391) );
OAI2BB1X4TS U10181 ( .A0N(n12196), .A1N(n9395), .B0(n12195), .Y(n11057) );
XNOR2X4TS U10182 ( .A(n9404), .B(n9403), .Y(n9405) );
OAI2BB1X4TS U10183 ( .A0N(n1208), .A1N(n12206), .B0(n9406), .Y(n499) );
NAND2X4TS U10184 ( .A(n1834), .B(n495), .Y(n12361) );
NAND2X1TS U10185 ( .A(n9416), .B(n9432), .Y(n9410) );
INVX2TS U10186 ( .A(n9420), .Y(n9411) );
XNOR2X4TS U10187 ( .A(n9413), .B(n9412), .Y(n9414) );
OAI2BB1X4TS U10188 ( .A0N(n1213), .A1N(n12208), .B0(n9415), .Y(n497) );
NAND2X4TS U10189 ( .A(n1836), .B(n497), .Y(n12355) );
NAND2X1TS U10190 ( .A(n9422), .B(n9432), .Y(n9424) );
AOI21X1TS U10191 ( .A0(n9436), .A1(n9422), .B0(n1399), .Y(n9423) );
XNOR2X4TS U10192 ( .A(n9429), .B(n9428), .Y(n9430) );
OAI2BB1X4TS U10193 ( .A0N(n1208), .A1N(n12171), .B0(n9431), .Y(n498) );
NAND2X1TS U10194 ( .A(n9432), .B(n9435), .Y(n9438) );
INVX2TS U10195 ( .A(n9433), .Y(n9434) );
INVX2TS U10196 ( .A(n9439), .Y(n9441) );
XNOR2X4TS U10197 ( .A(n9443), .B(n9442), .Y(n9444) );
OAI2BB1X4TS U10198 ( .A0N(n1192), .A1N(n12172), .B0(n9445), .Y(n496) );
OAI22X1TS U10199 ( .A0(n9452), .A1(n2165), .B0(n9481), .B1(n2339), .Y(n9484)
);
NOR2XLTS U10200 ( .A(n2181), .B(n1920), .Y(n9473) );
OAI22X1TS U10201 ( .A0(n9481), .A1(n2165), .B0(n4095), .B1(n7031), .Y(n9756)
);
INVX2TS U10202 ( .A(n9487), .Y(n9489) );
OAI21X2TS U10203 ( .A0(n1824), .A1(n9501), .B0(n9500), .Y(n9505) );
NAND2X1TS U10204 ( .A(n9648), .B(n9508), .Y(n9510) );
NAND2X1TS U10205 ( .A(n9512), .B(n9511), .Y(n9513) );
INVX2TS U10206 ( .A(n9545), .Y(n9523) );
NAND2X1TS U10207 ( .A(n9549), .B(n9545), .Y(n9551) );
AOI21X1TS U10208 ( .A0(n9549), .A1(n9548), .B0(n9547), .Y(n9550) );
NAND2X1TS U10209 ( .A(n9648), .B(n9568), .Y(n9570) );
NAND2X2TS U10210 ( .A(n9581), .B(n9580), .Y(n9582) );
NAND2X1TS U10211 ( .A(n10863), .B(n2064), .Y(n9592) );
XNOR2X4TS U10212 ( .A(n9597), .B(n9596), .Y(n9598) );
OAI2BB1X4TS U10213 ( .A0N(n1197), .A1N(n9598), .B0(n12185), .Y(n10872) );
XNOR2X4TS U10214 ( .A(n9613), .B(n9612), .Y(n9614) );
OAI2BB1X4TS U10215 ( .A0N(n1209), .A1N(n9614), .B0(n12186), .Y(n10876) );
XNOR2X4TS U10216 ( .A(n9621), .B(n1121), .Y(n9622) );
OAI2BB1X4TS U10217 ( .A0N(n1217), .A1N(n9622), .B0(n12181), .Y(n10948) );
AOI2BB2X2TS U10218 ( .B0(n10871), .B1(n499), .A0N(n2007), .A1N(n11866), .Y(
n12353) );
AOI2BB2X2TS U10219 ( .B0(n10871), .B1(n498), .A0N(n10760), .A1N(n11867), .Y(
n12356) );
INVX2TS U10220 ( .A(rst), .Y(n12394) );
CLKBUFX2TS U10221 ( .A(n12394), .Y(n11444) );
CLKBUFX3TS U10222 ( .A(n12394), .Y(n12221) );
CLKBUFX3TS U10223 ( .A(n12226), .Y(n11982) );
INVX2TS U10224 ( .A(n9629), .Y(n9631) );
NAND2X1TS U10225 ( .A(n9648), .B(n9639), .Y(n9641) );
AND2X2TS U10226 ( .A(n9647), .B(n9651), .Y(n9653) );
NAND2X1TS U10227 ( .A(n9648), .B(n9653), .Y(n9656) );
OR2X2TS U10228 ( .A(n9658), .B(n9657), .Y(n9660) );
NAND2X1TS U10229 ( .A(n9658), .B(n9657), .Y(n9659) );
NAND2X1TS U10230 ( .A(n9660), .B(n9659), .Y(n9661) );
BUFX3TS U10231 ( .A(n12221), .Y(n11975) );
CLKBUFX2TS U10232 ( .A(n11981), .Y(n11715) );
MXI2X4TS U10233 ( .A(n9665), .B(n11930), .S0(n10293), .Y(n9666) );
INVX2TS U10234 ( .A(n9666), .Y(n11462) );
MXI2X4TS U10235 ( .A(n9667), .B(n11895), .S0(n9724), .Y(n696) );
XOR2X1TS U10236 ( .A(n11462), .B(n696), .Y(n11727) );
INVX2TS U10237 ( .A(Data_MX[16]), .Y(n9668) );
MXI2X4TS U10238 ( .A(n9669), .B(n11795), .S0(n9731), .Y(n661) );
XNOR2X1TS U10239 ( .A(n662), .B(n661), .Y(n11585) );
INVX2TS U10240 ( .A(Data_MX[0]), .Y(n9670) );
INVX2TS U10241 ( .A(n11337), .Y(n9671) );
MXI2X4TS U10242 ( .A(n9672), .B(n9671), .S0(n11167), .Y(n673) );
INVX2TS U10243 ( .A(Data_MX[7]), .Y(n9673) );
INVX2TS U10244 ( .A(Data_MX[34]), .Y(n9674) );
XNOR2X1TS U10245 ( .A(n653), .B(n680), .Y(n11498) );
INVX2TS U10246 ( .A(Data_MX[6]), .Y(n9675) );
INVX2TS U10247 ( .A(Data_MX[5]), .Y(n9676) );
INVX2TS U10248 ( .A(Data_MX[3]), .Y(n9678) );
MXI2X4TS U10249 ( .A(n9678), .B(n983), .S0(n10293), .Y(n649) );
XNOR2X1TS U10250 ( .A(n650), .B(n649), .Y(n11464) );
INVX2TS U10251 ( .A(Data_MX[18]), .Y(n9679) );
MXI2X4TS U10252 ( .A(n9679), .B(n12136), .S0(n9731), .Y(n664) );
INVX2TS U10253 ( .A(Data_MX[17]), .Y(n9680) );
XNOR2X1TS U10254 ( .A(n664), .B(n12143), .Y(n11520) );
INVX2TS U10255 ( .A(Op_MY[46]), .Y(n9683) );
MXI2X4TS U10256 ( .A(n9684), .B(n9683), .S0(n11171), .Y(n628) );
XNOR2X1TS U10257 ( .A(n9682), .B(n628), .Y(n11675) );
MXI2X4TS U10258 ( .A(n9685), .B(n11815), .S0(n9718), .Y(n679) );
INVX2TS U10259 ( .A(Data_MX[32]), .Y(n9686) );
XNOR2X1TS U10260 ( .A(n679), .B(n1355), .Y(n11468) );
INVX2TS U10261 ( .A(Data_MX[37]), .Y(n9687) );
INVX2TS U10262 ( .A(Data_MX[20]), .Y(n9689) );
INVX2TS U10263 ( .A(Data_MX[19]), .Y(n9690) );
INVX2TS U10264 ( .A(Data_MX[24]), .Y(n9691) );
INVX2TS U10265 ( .A(Data_MX[23]), .Y(n9692) );
XNOR2X1TS U10266 ( .A(n670), .B(n9693), .Y(n11666) );
NAND2X1TS U10267 ( .A(n9695), .B(n9694), .Y(n9697) );
XNOR2X1TS U10268 ( .A(n9697), .B(n9696), .Y(Sgf_operation_ODD1_Q_left[3]) );
XNOR2X1TS U10269 ( .A(n9700), .B(n1446), .Y(n11517) );
XOR2X1TS U10270 ( .A(n660), .B(n661), .Y(n11474) );
MXI2X4TS U10271 ( .A(n9702), .B(n11894), .S0(n9724), .Y(n694) );
MXI2X4TS U10272 ( .A(n9703), .B(n11912), .S0(n9724), .Y(n695) );
INVX2TS U10273 ( .A(n695), .Y(n9704) );
XNOR2X1TS U10274 ( .A(n9704), .B(n694), .Y(n11563) );
INVX2TS U10275 ( .A(n674), .Y(n9706) );
XNOR2X1TS U10276 ( .A(n673), .B(n9706), .Y(n11521) );
INVX2TS U10277 ( .A(Data_MX[39]), .Y(n9707) );
MXI2X4TS U10278 ( .A(n9707), .B(n11905), .S0(n9718), .Y(n685) );
INVX2TS U10279 ( .A(Data_MX[40]), .Y(n9708) );
XOR2X1TS U10280 ( .A(n685), .B(n686), .Y(n11512) );
XOR2X1TS U10281 ( .A(n679), .B(n680), .Y(n11533) );
INVX2TS U10282 ( .A(Data_MX[45]), .Y(n9709) );
MXI2X4TS U10283 ( .A(n9709), .B(n11903), .S0(n9724), .Y(n691) );
INVX2TS U10284 ( .A(Data_MX[44]), .Y(n9710) );
XOR2X1TS U10285 ( .A(n691), .B(n690), .Y(n11681) );
INVX2TS U10286 ( .A(Data_MX[35]), .Y(n9711) );
MXI2X2TS U10287 ( .A(n9711), .B(n11931), .S0(n9718), .Y(n681) );
XOR2X1TS U10288 ( .A(n681), .B(n680), .Y(n11665) );
INVX2TS U10289 ( .A(Data_MX[47]), .Y(n9712) );
MXI2X4TS U10290 ( .A(n9712), .B(n12150), .S0(n9724), .Y(n693) );
XOR2X1TS U10291 ( .A(n693), .B(n694), .Y(n11506) );
MXI2X4TS U10292 ( .A(n9714), .B(n12245), .S0(n9724), .Y(n688) );
XOR2X1TS U10293 ( .A(n12139), .B(n688), .Y(n11501) );
XOR2X1TS U10294 ( .A(n675), .B(n674), .Y(n11518) );
XOR2X1TS U10295 ( .A(n695), .B(n696), .Y(n11685) );
XOR2X1TS U10296 ( .A(n12143), .B(n690), .Y(n11503) );
XOR2X1TS U10297 ( .A(n12139), .B(n686), .Y(n11507) );
INVX2TS U10298 ( .A(Data_MY[28]), .Y(n9716) );
INVX2TS U10299 ( .A(Data_MY[1]), .Y(n9717) );
MXI2X4TS U10300 ( .A(n9719), .B(n11945), .S0(n9718), .Y(n684) );
MXI2X4TS U10301 ( .A(n9720), .B(n12113), .S0(n11171), .Y(n632) );
XNOR2X1TS U10302 ( .A(n684), .B(n632), .Y(n11686) );
XNOR2X1TS U10303 ( .A(n661), .B(n688), .Y(n11479) );
XOR2X1TS U10304 ( .A(n664), .B(n665), .Y(n11524) );
INVX2TS U10305 ( .A(Data_MX[12]), .Y(n9721) );
INVX2TS U10306 ( .A(Data_MX[13]), .Y(n9722) );
XOR2X1TS U10307 ( .A(n658), .B(n12137), .Y(n11668) );
XOR2X1TS U10308 ( .A(n675), .B(n1446), .Y(n11494) );
XNOR2X1TS U10309 ( .A(n688), .B(n632), .Y(n11678) );
XNOR2X1TS U10310 ( .A(n9682), .B(n632), .Y(n11677) );
INVX2TS U10311 ( .A(Data_MX[46]), .Y(n9725) );
XOR2X1TS U10312 ( .A(n691), .B(n1441), .Y(n11508) );
XOR2X1TS U10313 ( .A(n681), .B(n9682), .Y(n11511) );
XNOR2X1TS U10314 ( .A(n9726), .B(n688), .Y(n11671) );
XNOR2X1TS U10315 ( .A(n685), .B(n684), .Y(n11463) );
XNOR2X1TS U10316 ( .A(n654), .B(n653), .Y(n11472) );
XNOR2X1TS U10317 ( .A(n9693), .B(n696), .Y(n11489) );
XNOR2X1TS U10318 ( .A(n693), .B(n1441), .Y(n11480) );
INVX2TS U10319 ( .A(Data_MX[11]), .Y(n9728) );
XNOR2X1TS U10320 ( .A(n658), .B(n9729), .Y(n11482) );
INVX2TS U10321 ( .A(Data_MX[10]), .Y(n9730) );
MXI2X4TS U10322 ( .A(n9730), .B(n11901), .S0(n9731), .Y(n656) );
INVX2TS U10323 ( .A(Data_MX[9]), .Y(n9732) );
XNOR2X1TS U10324 ( .A(n656), .B(n9733), .Y(n11481) );
CLKBUFX2TS U10325 ( .A(n12395), .Y(n11992) );
BUFX3TS U10326 ( .A(n1828), .Y(n12231) );
CLKBUFX2TS U10327 ( .A(n11993), .Y(n11702) );
CLKBUFX2TS U10328 ( .A(n11975), .Y(n11725) );
CLKBUFX2TS U10329 ( .A(n1855), .Y(n11705) );
CLKBUFX2TS U10330 ( .A(n11997), .Y(n11698) );
BUFX3TS U10331 ( .A(n12243), .Y(n12242) );
OR2X2TS U10332 ( .A(n9737), .B(n751), .Y(n9738) );
AND2X2TS U10333 ( .A(n9738), .B(n10316), .Y(Sgf_operation_ODD1_Q_left[1]) );
NAND2X1TS U10334 ( .A(n10231), .B(n9740), .Y(n9741) );
XOR2X1TS U10335 ( .A(n2539), .B(n9741), .Y(Sgf_operation_ODD1_Q_left[10]) );
INVX2TS U10336 ( .A(n9742), .Y(n10240) );
NAND2X1TS U10337 ( .A(n10239), .B(n9743), .Y(n9744) );
XNOR2X1TS U10338 ( .A(n10240), .B(n9744), .Y(Sgf_operation_ODD1_Q_left[8])
);
NAND2X1TS U10339 ( .A(n10190), .B(n9746), .Y(n9747) );
XOR2X1TS U10340 ( .A(n10193), .B(n9747), .Y(Sgf_operation_ODD1_Q_left[16])
);
CMPR32X2TS U10341 ( .A(n9753), .B(n9752), .C(n9751), .CO(n10200), .S(n9757)
);
AO21X2TS U10342 ( .A0(n2165), .A1(n2339), .B0(n7031), .Y(n10201) );
XNOR2X1TS U10343 ( .A(n10202), .B(n10201), .Y(n10199) );
NAND2X1TS U10344 ( .A(n10173), .B(n10171), .Y(n9760) );
XNOR2X1TS U10345 ( .A(n10174), .B(n9760), .Y(Sgf_operation_ODD1_Q_left[20])
);
NAND2X1TS U10346 ( .A(n10184), .B(n9763), .Y(n9764) );
XNOR2X1TS U10347 ( .A(n10185), .B(n9764), .Y(Sgf_operation_ODD1_Q_left[18])
);
NAND2X1TS U10348 ( .A(n1009), .B(n10064), .Y(n10067) );
NAND2X1TS U10349 ( .A(n10088), .B(n3306), .Y(n10081) );
NAND2X1TS U10350 ( .A(n10088), .B(n10091), .Y(n10093) );
NAND2X1TS U10351 ( .A(n10112), .B(n10111), .Y(n10113) );
NAND2X1TS U10352 ( .A(n10148), .B(n10151), .Y(n10137) );
AOI21X1TS U10353 ( .A0(n10151), .A1(n2346), .B0(n10135), .Y(n10136) );
NAND2X1TS U10354 ( .A(n10145), .B(n10144), .Y(n10146) );
CLKINVX1TS U10355 ( .A(n10148), .Y(n10149) );
OAI21X4TS U10356 ( .A0(n10170), .A1(n10166), .B0(n10167), .Y(n10160) );
NAND2X1TS U10357 ( .A(n10163), .B(n10162), .Y(n10164) );
NAND2X1TS U10358 ( .A(n10168), .B(n10167), .Y(n10169) );
INVX2TS U10359 ( .A(n10190), .Y(n10192) );
NAND2X1TS U10360 ( .A(n10195), .B(n10194), .Y(n10196) );
INVX2TS U10361 ( .A(n10220), .Y(n10214) );
AOI21X1TS U10362 ( .A0(n10240), .A1(n10239), .B0(n10238), .Y(n10244) );
CLKXOR2X2TS U10363 ( .A(n10244), .B(n10243), .Y(Sgf_operation_ODD1_Q_left[9]) );
INVX2TS U10364 ( .A(n10245), .Y(n10266) );
INVX2TS U10365 ( .A(n10246), .Y(n10248) );
XNOR2X1TS U10366 ( .A(n10250), .B(n10249), .Y(Sgf_operation_ODD1_Q_left[7])
);
MXI2X4TS U10367 ( .A(n10251), .B(n12148), .S0(n10310), .Y(n618) );
INVX2TS U10368 ( .A(n591), .Y(n10255) );
OAI21X1TS U10369 ( .A0(n11491), .A1(n11552), .B0(n11565), .Y(n11564) );
INVX2TS U10370 ( .A(Data_MX[26]), .Y(n10257) );
MXI2X4TS U10371 ( .A(n10257), .B(n11794), .S0(n11131), .Y(n672) );
INVX2TS U10372 ( .A(Data_MX[25]), .Y(n10258) );
INVX2TS U10373 ( .A(n598), .Y(n11627) );
MXI2X4TS U10374 ( .A(n10261), .B(n11927), .S0(n10326), .Y(n599) );
INVX2TS U10375 ( .A(n599), .Y(n11628) );
OAI22X1TS U10376 ( .A0(n11575), .A1(n11627), .B0(n11628), .B1(n1432), .Y(
n11626) );
NAND2X1TS U10377 ( .A(n10264), .B(n10263), .Y(n10265) );
XOR2X1TS U10378 ( .A(n10266), .B(n10265), .Y(Sgf_operation_ODD1_Q_left[6])
);
MXI2X4TS U10379 ( .A(n10268), .B(n11909), .S0(n10299), .Y(n586) );
MXI2X4TS U10380 ( .A(n10271), .B(n11812), .S0(n10310), .Y(n620) );
MXI2X4TS U10381 ( .A(n10272), .B(n11913), .S0(n10326), .Y(n593) );
INVX2TS U10382 ( .A(Data_MY[27]), .Y(n10274) );
INVX2TS U10383 ( .A(Data_MY[0]), .Y(n10275) );
INVX2TS U10384 ( .A(Data_MX[21]), .Y(n10276) );
NOR2BX1TS U10385 ( .AN(n10277), .B(n1446), .Y(n11488) );
NAND2BX1TS U10386 ( .AN(n10278), .B(n12139), .Y(n11682) );
INVX2TS U10387 ( .A(Data_MY[44]), .Y(n10279) );
OR2X2TS U10388 ( .A(n626), .B(n599), .Y(n11567) );
INVX2TS U10389 ( .A(n10280), .Y(n10304) );
AOI21X1TS U10390 ( .A0(n10304), .A1(n10303), .B0(n10281), .Y(n10285) );
NAND2X1TS U10391 ( .A(n10283), .B(n10282), .Y(n10284) );
INVX2TS U10392 ( .A(Data_MY[29]), .Y(n10286) );
INVX2TS U10393 ( .A(Data_MY[2]), .Y(n10287) );
MXI2X4TS U10394 ( .A(n10287), .B(n11958), .S0(n10299), .Y(n584) );
NAND2X1TS U10395 ( .A(n611), .B(n584), .Y(n11473) );
INVX2TS U10396 ( .A(Data_MY[33]), .Y(n10288) );
INVX2TS U10397 ( .A(Data_MY[6]), .Y(n10289) );
NAND2X1TS U10398 ( .A(n615), .B(n588), .Y(n11684) );
INVX2TS U10399 ( .A(Data_MY[40]), .Y(n10290) );
INVX2TS U10400 ( .A(Data_MY[13]), .Y(n10291) );
MXI2X4TS U10401 ( .A(n10291), .B(n11966), .S0(n10326), .Y(n595) );
NAND2X1TS U10402 ( .A(n622), .B(n595), .Y(n11559) );
INVX2TS U10403 ( .A(Data_MX[2]), .Y(n10292) );
INVX2TS U10404 ( .A(Data_MX[1]), .Y(n10294) );
INVX2TS U10405 ( .A(Data_MY[30]), .Y(n10295) );
INVX2TS U10406 ( .A(Data_MY[3]), .Y(n10296) );
NAND2X1TS U10407 ( .A(n11806), .B(n585), .Y(n11680) );
INVX2TS U10408 ( .A(Data_MY[45]), .Y(n10297) );
INVX2TS U10409 ( .A(Data_MY[18]), .Y(n10298) );
NAND2X1TS U10410 ( .A(n627), .B(n600), .Y(n11558) );
INVX2TS U10411 ( .A(Data_MY[7]), .Y(n10300) );
INVX2TS U10412 ( .A(Data_MY[34]), .Y(n10301) );
NOR2X1TS U10413 ( .A(n589), .B(n616), .Y(n11534) );
NAND2X1TS U10414 ( .A(n10303), .B(n10302), .Y(n10305) );
XNOR2X1TS U10415 ( .A(n10305), .B(n10304), .Y(Sgf_operation_ODD1_Q_left[4])
);
XNOR2X1TS U10416 ( .A(n668), .B(n11804), .Y(n11465) );
INVX2TS U10417 ( .A(Data_MY[39]), .Y(n10306) );
INVX2TS U10418 ( .A(Data_MY[12]), .Y(n10307) );
INVX2TS U10419 ( .A(Data_MY[41]), .Y(n10308) );
INVX2TS U10420 ( .A(Data_MY[14]), .Y(n10309) );
INVX2TS U10421 ( .A(Data_MY[42]), .Y(n10311) );
INVX2TS U10422 ( .A(Data_MY[15]), .Y(n10312) );
NOR2X1TS U10423 ( .A(n624), .B(n597), .Y(n11557) );
INVX2TS U10424 ( .A(n10313), .Y(n10315) );
NAND2X1TS U10425 ( .A(n10315), .B(n10314), .Y(n10317) );
CLKBUFX2TS U10426 ( .A(n11996), .Y(n11697) );
CLKBUFX2TS U10427 ( .A(n11704), .Y(n11695) );
BUFX3TS U10428 ( .A(n12228), .Y(n11972) );
CLKBUFX3TS U10429 ( .A(n12394), .Y(n12227) );
CLKBUFX2TS U10430 ( .A(n1867), .Y(n12235) );
CLKBUFX2TS U10431 ( .A(n12228), .Y(n11974) );
MXI2X2TS U10432 ( .A(n10324), .B(n12133), .S0(n11171), .Y(n630) );
INVX2TS U10433 ( .A(Data_MY[20]), .Y(n10325) );
INVX2TS U10434 ( .A(Data_MY[19]), .Y(n10327) );
INVX2TS U10435 ( .A(Data_MY[22]), .Y(n10328) );
INVX2TS U10436 ( .A(Data_MY[51]), .Y(n10330) );
AOI21X1TS U10437 ( .A0(n10530), .A1(zero_flag), .B0(n1356), .Y(n10331) );
NAND2X1TS U10438 ( .A(n10332), .B(n10331), .Y(n714) );
INVX2TS U10439 ( .A(n10333), .Y(n10335) );
NAND2X1TS U10440 ( .A(n10335), .B(n10334), .Y(n10337) );
XOR2X1TS U10441 ( .A(n10337), .B(n10336), .Y(n10338) );
CLKMX2X2TS U10442 ( .A(n10338), .B(P_Sgf[3]), .S0(n12218), .Y(n424) );
AO22X1TS U10443 ( .A0(n11287), .A1(Sgf_normalized_result[14]), .B0(
final_result_ieee[14]), .B1(n11288), .Y(n337) );
AO22X1TS U10444 ( .A0(n11292), .A1(Sgf_normalized_result[10]), .B0(
final_result_ieee[10]), .B1(n11288), .Y(n341) );
AO22X1TS U10445 ( .A0(n11287), .A1(Sgf_normalized_result[13]), .B0(
final_result_ieee[13]), .B1(n11288), .Y(n338) );
AO22X1TS U10446 ( .A0(n11292), .A1(Sgf_normalized_result[9]), .B0(
final_result_ieee[9]), .B1(n11288), .Y(n342) );
AO22X1TS U10447 ( .A0(n11292), .A1(Sgf_normalized_result[11]), .B0(
final_result_ieee[11]), .B1(n11288), .Y(n340) );
AO22X1TS U10448 ( .A0(n11287), .A1(n11255), .B0(final_result_ieee[22]), .B1(
n11286), .Y(n329) );
AO22X1TS U10449 ( .A0(n10341), .A1(n11256), .B0(final_result_ieee[23]), .B1(
n11286), .Y(n328) );
AO22X1TS U10450 ( .A0(n11292), .A1(Sgf_normalized_result[12]), .B0(
final_result_ieee[12]), .B1(n11288), .Y(n339) );
AO22X1TS U10451 ( .A0(n10341), .A1(n11258), .B0(final_result_ieee[24]), .B1(
n11286), .Y(n327) );
AO22X1TS U10452 ( .A0(n11292), .A1(Sgf_normalized_result[7]), .B0(
final_result_ieee[7]), .B1(n11288), .Y(n344) );
AO22X1TS U10453 ( .A0(n11292), .A1(Sgf_normalized_result[8]), .B0(
final_result_ieee[8]), .B1(n11288), .Y(n343) );
AO22X1TS U10454 ( .A0(n11287), .A1(Sgf_normalized_result[15]), .B0(
final_result_ieee[15]), .B1(n11286), .Y(n336) );
AO22X1TS U10455 ( .A0(n11292), .A1(Sgf_normalized_result[3]), .B0(
final_result_ieee[3]), .B1(n11295), .Y(n348) );
AO22X1TS U10456 ( .A0(n11294), .A1(n11279), .B0(final_result_ieee[45]), .B1(
n11293), .Y(n306) );
NAND3X1TS U10457 ( .A(n12004), .B(n12003), .C(n12002), .Y(n11284) );
AO22X1TS U10458 ( .A0(n11294), .A1(n11284), .B0(final_result_ieee[51]), .B1(
n11293), .Y(n300) );
AO22X1TS U10459 ( .A0(n11294), .A1(n11278), .B0(final_result_ieee[48]), .B1(
n11293), .Y(n303) );
AO22X1TS U10460 ( .A0(n11250), .A1(Sgf_normalized_result[1]), .B0(
final_result_ieee[1]), .B1(n11295), .Y(n350) );
AO22X1TS U10461 ( .A0(n11250), .A1(Sgf_normalized_result[0]), .B0(
final_result_ieee[0]), .B1(n11293), .Y(n351) );
XNOR2X1TS U10462 ( .A(n10343), .B(n11940), .Y(n10345) );
BUFX8TS U10463 ( .A(n10949), .Y(n11319) );
CLKMX2X2TS U10464 ( .A(n10345), .B(Add_result[8]), .S0(n11319), .Y(n571) );
NAND2X1TS U10465 ( .A(n10346), .B(Sgf_normalized_result[8]), .Y(n10347) );
XNOR2X1TS U10466 ( .A(n10348), .B(n11938), .Y(n10349) );
CLKMX2X2TS U10467 ( .A(n10349), .B(Add_result[9]), .S0(n11319), .Y(n570) );
NAND2X1TS U10468 ( .A(n11318), .B(n10354), .Y(n10355) );
XOR2X1TS U10469 ( .A(n10355), .B(n11934), .Y(n10356) );
CLKMX2X2TS U10470 ( .A(n10356), .B(Add_result[13]), .S0(n11319), .Y(n566) );
NAND2X1TS U10471 ( .A(n11318), .B(n10357), .Y(n10358) );
XOR2X1TS U10472 ( .A(n10358), .B(n11885), .Y(n10359) );
CLKMX2X2TS U10473 ( .A(n10359), .B(Add_result[12]), .S0(n11319), .Y(n567) );
NAND2X1TS U10474 ( .A(n11318), .B(n10384), .Y(n10362) );
XOR2X1TS U10475 ( .A(n10362), .B(n11836), .Y(n10363) );
CLKMX2X2TS U10476 ( .A(n10363), .B(Add_result[14]), .S0(n11319), .Y(n565) );
INVX2TS U10477 ( .A(n10384), .Y(n10372) );
NAND2X2TS U10478 ( .A(Sgf_normalized_result[14]), .B(
Sgf_normalized_result[15]), .Y(n10382) );
NAND2X1TS U10479 ( .A(n10364), .B(n11318), .Y(n10365) );
XOR2X1TS U10480 ( .A(n10365), .B(n11937), .Y(n10366) );
CLKMX2X2TS U10481 ( .A(n10366), .B(Add_result[16]), .S0(n11319), .Y(n563) );
NOR2X1TS U10482 ( .A(n10372), .B(n11836), .Y(n10367) );
NAND2X1TS U10483 ( .A(n10367), .B(n11318), .Y(n10368) );
XOR2X1TS U10484 ( .A(n10368), .B(n11935), .Y(n10369) );
CLKMX2X2TS U10485 ( .A(n10369), .B(Add_result[15]), .S0(n11319), .Y(n564) );
NAND2X1TS U10486 ( .A(n10370), .B(Sgf_normalized_result[16]), .Y(n10371) );
NOR2X1TS U10487 ( .A(n10372), .B(n10371), .Y(n10373) );
NAND2X1TS U10488 ( .A(n10373), .B(n11318), .Y(n10374) );
XOR2X1TS U10489 ( .A(n10374), .B(n11933), .Y(n10375) );
CLKMX2X2TS U10490 ( .A(n10375), .B(Add_result[17]), .S0(n11329), .Y(n562) );
NOR2X1TS U10491 ( .A(n10398), .B(n10425), .Y(n10380) );
NAND2X1TS U10492 ( .A(n10380), .B(n10419), .Y(n10387) );
INVX2TS U10493 ( .A(n11269), .Y(n10388) );
XNOR2X1TS U10494 ( .A(n10389), .B(n10388), .Y(n10390) );
CLKMX2X2TS U10495 ( .A(n10390), .B(Add_result[32]), .S0(n11071), .Y(n547) );
NOR2X1TS U10496 ( .A(n10398), .B(n10421), .Y(n10391) );
NAND2X1TS U10497 ( .A(n10391), .B(n10419), .Y(n10392) );
INVX2TS U10498 ( .A(n11272), .Y(n10393) );
XNOR2X1TS U10499 ( .A(n10394), .B(n10393), .Y(n10395) );
CLKMX2X2TS U10500 ( .A(n10395), .B(Add_result[31]), .S0(n11071), .Y(n548) );
NAND2X1TS U10501 ( .A(n10396), .B(n11269), .Y(n10397) );
NOR2X1TS U10502 ( .A(n10398), .B(n10397), .Y(n10399) );
NAND2X1TS U10503 ( .A(n10399), .B(n10419), .Y(n10400) );
INVX2TS U10504 ( .A(n11260), .Y(n10401) );
XNOR2X1TS U10505 ( .A(n10402), .B(n10401), .Y(n10403) );
CLKMX2X2TS U10506 ( .A(n10403), .B(Add_result[33]), .S0(n11071), .Y(n546) );
INVX2TS U10507 ( .A(n11268), .Y(n10405) );
XNOR2X1TS U10508 ( .A(n10406), .B(n10405), .Y(n10407) );
NAND2X1TS U10509 ( .A(n10419), .B(n10408), .Y(n10409) );
INVX2TS U10510 ( .A(n11259), .Y(n10410) );
XNOR2X1TS U10511 ( .A(n10411), .B(n10410), .Y(n10412) );
CLKMX2X2TS U10512 ( .A(n10412), .B(Add_result[29]), .S0(n11071), .Y(n550) );
NAND2X1TS U10513 ( .A(n10419), .B(n10414), .Y(n10415) );
XNOR2X1TS U10514 ( .A(n10417), .B(n10416), .Y(n10418) );
NAND2X1TS U10515 ( .A(n10419), .B(n10427), .Y(n10420) );
XNOR2X1TS U10516 ( .A(n10422), .B(n10421), .Y(n10423) );
CLKMX2X2TS U10517 ( .A(n10423), .B(Add_result[30]), .S0(n11071), .Y(n549) );
INVX2TS U10518 ( .A(n11262), .Y(n10433) );
XNOR2X1TS U10519 ( .A(n10434), .B(n10433), .Y(n10435) );
NOR2X1TS U10520 ( .A(n11075), .B(n11079), .Y(n10439) );
NAND2X1TS U10521 ( .A(n11077), .B(n10439), .Y(n10440) );
INVX2TS U10522 ( .A(n11279), .Y(n10441) );
XNOR2X1TS U10523 ( .A(n10442), .B(n10441), .Y(n10443) );
CLKMX2X2TS U10524 ( .A(n10443), .B(Add_result[45]), .S0(n11097), .Y(n534) );
XNOR2X1TS U10525 ( .A(n10445), .B(n10444), .Y(n10446) );
CLKMX2X2TS U10526 ( .A(n10446), .B(Add_result[42]), .S0(n11097), .Y(n537) );
NAND2X1TS U10527 ( .A(n10448), .B(n11278), .Y(n10449) );
NAND2X1TS U10528 ( .A(n10450), .B(n11077), .Y(n10451) );
XNOR2X1TS U10529 ( .A(n10453), .B(n10452), .Y(n10454) );
CLKMX2X2TS U10530 ( .A(n10454), .B(n1992), .S0(n11037), .Y(n530) );
XNOR2X1TS U10531 ( .A(n10457), .B(n10456), .Y(n10458) );
CLKMX2X2TS U10532 ( .A(n10458), .B(Add_result[38]), .S0(n11097), .Y(n541) );
NAND2X1TS U10533 ( .A(n11077), .B(n11277), .Y(n10459) );
XNOR2X1TS U10534 ( .A(n10461), .B(n10460), .Y(n10462) );
CLKMX2X2TS U10535 ( .A(n10462), .B(Add_result[43]), .S0(n11097), .Y(n536) );
XNOR2X1TS U10536 ( .A(n10464), .B(n10463), .Y(n10465) );
CLKMX2X2TS U10537 ( .A(n10465), .B(Add_result[36]), .S0(n11097), .Y(n543) );
INVX2TS U10538 ( .A(n11265), .Y(n10467) );
XNOR2X1TS U10539 ( .A(n10468), .B(n10467), .Y(n10469) );
CLKMX2X2TS U10540 ( .A(n10469), .B(Add_result[35]), .S0(n11071), .Y(n544) );
NAND2X1TS U10541 ( .A(n11077), .B(n10475), .Y(n10470) );
XNOR2X1TS U10542 ( .A(n10471), .B(n10481), .Y(n10472) );
CLKMX2X2TS U10543 ( .A(n10472), .B(Add_result[46]), .S0(n11037), .Y(n533) );
NAND2X1TS U10544 ( .A(n10475), .B(n10474), .Y(n10476) );
NAND2X1TS U10545 ( .A(n11323), .B(n11280), .Y(n10478) );
INVX2TS U10546 ( .A(n11284), .Y(n11116) );
XNOR2X1TS U10547 ( .A(n10479), .B(n11116), .Y(n10480) );
CLKMX2X2TS U10548 ( .A(n10480), .B(Add_result[51]), .S0(n11037), .Y(n528) );
NAND2X1TS U10549 ( .A(n10482), .B(n11077), .Y(n10483) );
XNOR2X1TS U10550 ( .A(n10484), .B(n11890), .Y(n10485) );
CLKMX2X2TS U10551 ( .A(n10485), .B(Add_result[47]), .S0(n11037), .Y(n532) );
NAND2X1TS U10552 ( .A(n10493), .B(n11255), .Y(n10486) );
INVX2TS U10553 ( .A(n11256), .Y(n10487) );
XNOR2X1TS U10554 ( .A(n10488), .B(n10487), .Y(n10489) );
CLKMX2X2TS U10555 ( .A(n10489), .B(n2120), .S0(n11329), .Y(n556) );
XNOR2X1TS U10556 ( .A(n10491), .B(n10490), .Y(n10492) );
CLKMX2X2TS U10557 ( .A(n10492), .B(n2119), .S0(n11329), .Y(n559) );
INVX2TS U10558 ( .A(n10493), .Y(n11047) );
INVX2TS U10559 ( .A(n11255), .Y(n10494) );
XNOR2X1TS U10560 ( .A(n10495), .B(n10494), .Y(n10496) );
CLKMX2X2TS U10561 ( .A(n10496), .B(Add_result[22]), .S0(n11329), .Y(n557) );
INVX2TS U10562 ( .A(n10497), .Y(n10498) );
XNOR2X1TS U10563 ( .A(n10501), .B(n10500), .Y(n10502) );
CLKMX2X2TS U10564 ( .A(n10502), .B(n2118), .S0(n11329), .Y(n558) );
AOI21X1TS U10565 ( .A0(n10600), .A1(n10525), .B0(n10524), .Y(n10526) );
AOI21X1TS U10566 ( .A0(n11106), .A1(n10542), .B0(n10541), .Y(n10547) );
INVX2TS U10567 ( .A(n10549), .Y(n10545) );
NAND2X1TS U10568 ( .A(n10545), .B(n10548), .Y(n10546) );
NAND2X1TS U10569 ( .A(n10566), .B(n10551), .Y(n11100) );
NAND2X1TS U10570 ( .A(n10555), .B(n11101), .Y(n10556) );
INVX2TS U10571 ( .A(n10582), .Y(n10559) );
AOI21X1TS U10572 ( .A0(n11106), .A1(n10583), .B0(n10559), .Y(n10564) );
INVX2TS U10573 ( .A(n10560), .Y(n10562) );
NAND2X1TS U10574 ( .A(n10562), .B(n10561), .Y(n10563) );
AOI21X1TS U10575 ( .A0(n11106), .A1(n10566), .B0(n10565), .Y(n10571) );
INVX2TS U10576 ( .A(n10567), .Y(n10569) );
NAND2X1TS U10577 ( .A(n10569), .B(n10568), .Y(n10570) );
INVX2TS U10578 ( .A(n10577), .Y(n10579) );
NAND2X1TS U10579 ( .A(n10579), .B(n10578), .Y(n10580) );
NAND2X1TS U10580 ( .A(n10583), .B(n10582), .Y(n10584) );
XNOR2X4TS U10581 ( .A(n11106), .B(n10584), .Y(n11027) );
NAND2X1TS U10582 ( .A(n10609), .B(n10607), .Y(n10586) );
NAND2X1TS U10583 ( .A(n10587), .B(n10590), .Y(n10589) );
XOR2X1TS U10584 ( .A(n10589), .B(n10592), .Y(n11123) );
OAI21X2TS U10585 ( .A0(n10592), .A1(n10591), .B0(n10590), .Y(n10597) );
INVX2TS U10586 ( .A(n10593), .Y(n10595) );
NAND2X1TS U10587 ( .A(n10595), .B(n10594), .Y(n10596) );
NAND3X1TS U10588 ( .A(n11026), .B(n11027), .C(n10599), .Y(n10617) );
AOI21X1TS U10589 ( .A0(n10610), .A1(n10601), .B0(n10600), .Y(n10606) );
NAND2X1TS U10590 ( .A(n10604), .B(n10603), .Y(n10605) );
INVX2TS U10591 ( .A(n10611), .Y(n10613) );
NAND2X1TS U10592 ( .A(n10613), .B(n10612), .Y(n10614) );
XOR2X1TS U10593 ( .A(n10615), .B(n10614), .Y(n11069) );
AOI21X1TS U10594 ( .A0(n11114), .A1(n11112), .B0(n10623), .Y(n10627) );
NAND2X1TS U10595 ( .A(n10625), .B(n10624), .Y(n10626) );
XOR2X1TS U10596 ( .A(n10627), .B(n10626), .Y(n10628) );
CLKMX2X2TS U10597 ( .A(n10628), .B(P_Sgf[9]), .S0(n1977), .Y(n430) );
CLKINVX1TS U10598 ( .A(n10629), .Y(n11022) );
INVX2TS U10599 ( .A(n11020), .Y(n10630) );
NAND2X1TS U10600 ( .A(n10632), .B(n10631), .Y(n10633) );
NAND2X1TS U10601 ( .A(n10640), .B(n10639), .Y(n10641) );
INVX2TS U10602 ( .A(n10660), .Y(n10644) );
NAND2X1TS U10603 ( .A(n10653), .B(n10652), .Y(n10654) );
AOI22X1TS U10604 ( .A0(n10673), .A1(Add_result[1]), .B0(
Sgf_normalized_result[0]), .B1(n11270), .Y(n10659) );
AOI2BB2X1TS U10605 ( .B0(n10674), .B1(n474), .A0N(n10682), .A1N(n12384), .Y(
n10658) );
NAND2X1TS U10606 ( .A(n1834), .B(n473), .Y(n10657) );
NAND3X1TS U10607 ( .A(n10659), .B(n10658), .C(n10657), .Y(n353) );
NAND2X1TS U10608 ( .A(n10664), .B(n10660), .Y(n10666) );
AOI21X1TS U10609 ( .A0(n10664), .A1(n10663), .B0(n10662), .Y(n10665) );
NAND2X1TS U10610 ( .A(n10669), .B(n10668), .Y(n10670) );
AOI22X1TS U10611 ( .A0(n10673), .A1(Add_result[2]), .B0(
Sgf_normalized_result[1]), .B1(n10717), .Y(n10677) );
AOI2BB2X1TS U10612 ( .B0(n10674), .B1(n475), .A0N(n10682), .A1N(n12378), .Y(
n10676) );
NAND2X1TS U10613 ( .A(n10882), .B(n474), .Y(n10675) );
NAND3X1TS U10614 ( .A(n10677), .B(n10676), .C(n10675), .Y(n354) );
NAND2X1TS U10615 ( .A(n1368), .B(n10678), .Y(n10679) );
AOI22X1TS U10616 ( .A0(n10758), .A1(Add_result[3]), .B0(
Sgf_normalized_result[2]), .B1(n10717), .Y(n10685) );
AOI2BB2X1TS U10617 ( .B0(n10674), .B1(n476), .A0N(n10682), .A1N(n12377), .Y(
n10684) );
NAND2X1TS U10618 ( .A(n1833), .B(n475), .Y(n10683) );
NAND3X1TS U10619 ( .A(n10685), .B(n10684), .C(n10683), .Y(n355) );
AOI22X1TS U10620 ( .A0(n10758), .A1(Add_result[9]), .B0(
Sgf_normalized_result[8]), .B1(n10717), .Y(n10688) );
AOI2BB2X2TS U10621 ( .B0(n10681), .B1(n482), .A0N(n10946), .A1N(n11879), .Y(
n10687) );
NAND2X1TS U10622 ( .A(n1833), .B(n481), .Y(n10686) );
AOI22X1TS U10623 ( .A0(n10758), .A1(Add_result[8]), .B0(
Sgf_normalized_result[7]), .B1(n10717), .Y(n10691) );
AOI2BB2X2TS U10624 ( .B0(n10681), .B1(n481), .A0N(n10860), .A1N(n11880), .Y(
n10690) );
AOI22X1TS U10625 ( .A0(n10758), .A1(Add_result[4]), .B0(
Sgf_normalized_result[3]), .B1(n10717), .Y(n10701) );
NAND2X1TS U10626 ( .A(n10882), .B(n476), .Y(n10699) );
AOI22X1TS U10627 ( .A0(n10758), .A1(Add_result[6]), .B0(n2135), .B1(n10717),
.Y(n10704) );
AOI2BB2X2TS U10628 ( .B0(n10681), .B1(n479), .A0N(n10860), .A1N(n11882), .Y(
n10703) );
AOI22X1TS U10629 ( .A0(n10758), .A1(Add_result[5]), .B0(n2137), .B1(n10717),
.Y(n10707) );
AOI2BB2X2TS U10630 ( .B0(n10681), .B1(n478), .A0N(n10870), .A1N(n11883), .Y(
n10706) );
NAND2X1TS U10631 ( .A(n1836), .B(n477), .Y(n10705) );
NAND3X1TS U10632 ( .A(n10707), .B(n10706), .C(n10705), .Y(n357) );
INVX2TS U10633 ( .A(n10747), .Y(n10708) );
AOI22X1TS U10634 ( .A0(n10758), .A1(Add_result[10]), .B0(
Sgf_normalized_result[9]), .B1(n11247), .Y(n10713) );
NAND2X1TS U10635 ( .A(n10730), .B(n10728), .Y(n10715) );
XNOR2X1TS U10636 ( .A(n2353), .B(n10715), .Y(n10716) );
CLKMX2X2TS U10637 ( .A(n10716), .B(P_Sgf[13]), .S0(n11312), .Y(n434) );
AOI2BB2X2TS U10638 ( .B0(n10681), .B1(n480), .A0N(n10760), .A1N(n11881), .Y(
n10719) );
AOI21X1TS U10639 ( .A0(n2353), .A1(n10722), .B0(n10721), .Y(n10726) );
NAND2X1TS U10640 ( .A(n10724), .B(n10723), .Y(n10725) );
NAND2X1TS U10641 ( .A(n1796), .B(n10733), .Y(n10734) );
NAND2X1TS U10642 ( .A(n10737), .B(n11820), .Y(n10738) );
CLKMX2X2TS U10643 ( .A(n10742), .B(P_Sgf[16]), .S0(n1977), .Y(n437) );
AOI22X1TS U10644 ( .A0(n11249), .A1(Add_result[14]), .B0(
Sgf_normalized_result[13]), .B1(n11247), .Y(n10745) );
AOI2BB2X2TS U10645 ( .B0(n10803), .B1(n487), .A0N(n10870), .A1N(n11875), .Y(
n10744) );
INVX2TS U10646 ( .A(n10749), .Y(n10751) );
AOI22X1TS U10647 ( .A0(n10758), .A1(Add_result[12]), .B0(
Sgf_normalized_result[11]), .B1(n11247), .Y(n10754) );
AOI22X1TS U10648 ( .A0(n11249), .A1(Add_result[13]), .B0(
Sgf_normalized_result[12]), .B1(n11247), .Y(n10757) );
AOI2BB2X2TS U10649 ( .B0(n10803), .B1(n486), .A0N(n10946), .A1N(n11876), .Y(
n10756) );
AOI22X1TS U10650 ( .A0(n10758), .A1(Add_result[11]), .B0(
Sgf_normalized_result[10]), .B1(n11247), .Y(n10763) );
NAND2X1TS U10651 ( .A(n1347), .B(n10767), .Y(n10768) );
NAND2X1TS U10652 ( .A(n10789), .B(n10779), .Y(n10780) );
AOI22X1TS U10653 ( .A0(n11249), .A1(Add_result[15]), .B0(
Sgf_normalized_result[14]), .B1(n11247), .Y(n10784) );
AOI22X1TS U10654 ( .A0(n11249), .A1(Add_result[17]), .B0(
Sgf_normalized_result[16]), .B1(n11247), .Y(n10787) );
NAND2X1TS U10655 ( .A(n10792), .B(n10791), .Y(n10793) );
AOI2BB2X1TS U10656 ( .B0(n10861), .B1(n10808), .A0N(n10946), .A1N(n11845),
.Y(n12271) );
AOI22X1TS U10657 ( .A0(n11249), .A1(Add_result[18]), .B0(
Sgf_normalized_result[17]), .B1(n11247), .Y(n10807) );
AOI2BB2X1TS U10658 ( .B0(n10803), .B1(n10802), .A0N(n10682), .A1N(n11871),
.Y(n10806) );
NAND2X1TS U10659 ( .A(n10957), .B(n10813), .Y(n10814) );
OAI21X2TS U10660 ( .A0(n2016), .A1(n10819), .B0(n10818), .Y(n10820) );
OAI2BB1X4TS U10661 ( .A0N(n1209), .A1N(n10821), .B0(n12194), .Y(n10878) );
NAND2X1TS U10662 ( .A(n10957), .B(n10823), .Y(n10824) );
OAI2BB1X4TS U10663 ( .A0N(n1131), .A1N(n10830), .B0(n12193), .Y(n10877) );
NAND2X1TS U10664 ( .A(n10957), .B(n10831), .Y(n10832) );
OAI2BB1X4TS U10665 ( .A0N(n1195), .A1N(n10839), .B0(n12200), .Y(n10880) );
XNOR2X4TS U10666 ( .A(n10848), .B(n11343), .Y(n10849) );
OAI2BB1X4TS U10667 ( .A0N(n1198), .A1N(n10849), .B0(n12199), .Y(n10884) );
OAI2BB1X4TS U10668 ( .A0N(n1198), .A1N(n10859), .B0(n12201), .Y(n10881) );
NAND2X1TS U10669 ( .A(n10956), .B(n10865), .Y(n10867) );
OAI2BB1X4TS U10670 ( .A0N(n9590), .A1N(n2085), .B0(n9344), .Y(n10864) );
XNOR2X4TS U10671 ( .A(n10868), .B(n11349), .Y(n10869) );
OAI2BB1X4TS U10672 ( .A0N(n1217), .A1N(n10869), .B0(n12183), .Y(n10885) );
INVX2TS U10673 ( .A(n10903), .Y(n10888) );
NAND2X1TS U10674 ( .A(n10940), .B(n10888), .Y(n10889) );
XNOR2X4TS U10675 ( .A(n10894), .B(n1146), .Y(n10895) );
OAI2BB1X4TS U10676 ( .A0N(n1217), .A1N(n10895), .B0(n12203), .Y(n10972) );
XNOR2X4TS U10677 ( .A(n10901), .B(n11348), .Y(n10902) );
OAI2BB1X4TS U10678 ( .A0N(n1217), .A1N(n10902), .B0(n12182), .Y(n10973) );
NAND2X1TS U10679 ( .A(n10940), .B(n10904), .Y(n10905) );
XNOR2X4TS U10680 ( .A(n10910), .B(n11342), .Y(n10911) );
OAI2BB1X4TS U10681 ( .A0N(n1195), .A1N(n10911), .B0(n12202), .Y(n10974) );
INVX2TS U10682 ( .A(n10929), .Y(n10912) );
XNOR2X4TS U10683 ( .A(n10918), .B(n1133), .Y(n10919) );
OAI2BB1X4TS U10684 ( .A0N(n1217), .A1N(n10919), .B0(n12180), .Y(n10971) );
INVX2TS U10685 ( .A(n10920), .Y(n10921) );
NAND2X1TS U10686 ( .A(n2064), .B(n10926), .Y(n10928) );
NAND2X1TS U10687 ( .A(n10940), .B(n10922), .Y(n10923) );
XNOR2X4TS U10688 ( .A(n10937), .B(n11340), .Y(n10938) );
OAI2BB1X4TS U10689 ( .A0N(n1217), .A1N(n10938), .B0(n12205), .Y(n10975) );
NAND2X1TS U10690 ( .A(n10940), .B(n10939), .Y(n10941) );
BUFX8TS U10691 ( .A(n10949), .Y(n11333) );
NAND3X1TS U10692 ( .A(n11333), .B(n11242), .C(n1874), .Y(n10968) );
INVX2TS U10693 ( .A(n11174), .Y(n10967) );
XNOR2X4TS U10694 ( .A(n10965), .B(n11350), .Y(n10966) );
OAI2BB1X4TS U10695 ( .A0N(n1217), .A1N(n10966), .B0(n12175), .Y(n11128) );
NAND2X1TS U10696 ( .A(n10983), .B(n10979), .Y(n10980) );
NAND2X1TS U10697 ( .A(n10985), .B(n10984), .Y(n10986) );
NAND2X1TS U10698 ( .A(n10994), .B(n10993), .Y(n10995) );
NAND2X1TS U10699 ( .A(n11003), .B(n11002), .Y(n11004) );
AO22X1TS U10700 ( .A0(n11287), .A1(Sgf_normalized_result[16]), .B0(
final_result_ieee[16]), .B1(n11286), .Y(n335) );
NAND2X1TS U10701 ( .A(n11020), .B(n11019), .Y(n11021) );
XOR2X1TS U10702 ( .A(n11022), .B(n11021), .Y(n11023) );
CLKMX2X2TS U10703 ( .A(n11024), .B(exp_oper_result[3]), .S0(n11068), .Y(n414) );
CLKMX2X2TS U10704 ( .A(n11025), .B(exp_oper_result[2]), .S0(n11068), .Y(n415) );
CLKMX2X2TS U10705 ( .A(n11026), .B(exp_oper_result[6]), .S0(n11068), .Y(n411) );
CLKMX2X2TS U10706 ( .A(n11027), .B(exp_oper_result[7]), .S0(n11068), .Y(n410) );
XNOR2X1TS U10707 ( .A(n11029), .B(n11117), .Y(n11030) );
CLKMX2X2TS U10708 ( .A(n11030), .B(Add_result[50]), .S0(n11037), .Y(n529) );
NOR2X1TS U10709 ( .A(n11032), .B(n11031), .Y(n11033) );
NAND2X1TS U10710 ( .A(n11033), .B(n11077), .Y(n11034) );
INVX2TS U10711 ( .A(n11278), .Y(n11035) );
XNOR2X1TS U10712 ( .A(n11036), .B(n11035), .Y(n11038) );
CLKMX2X2TS U10713 ( .A(n12103), .B(n12102), .S0(n12101), .Y(n580) );
XNOR2X1TS U10714 ( .A(n11041), .B(n11040), .Y(n11042) );
XNOR2X1TS U10715 ( .A(n11044), .B(n11043), .Y(n11045) );
CLKMX2X2TS U10716 ( .A(n11045), .B(Add_result[19]), .S0(n11329), .Y(n560) );
NAND2X1TS U10717 ( .A(n11052), .B(n11258), .Y(n11048) );
XNOR2X1TS U10718 ( .A(n11050), .B(n11049), .Y(n11051) );
INVX2TS U10719 ( .A(n11052), .Y(n11053) );
INVX2TS U10720 ( .A(n11258), .Y(n11054) );
XNOR2X1TS U10721 ( .A(n11055), .B(n11054), .Y(n11056) );
CLKINVX1TS U10722 ( .A(n11058), .Y(n11311) );
INVX2TS U10723 ( .A(n11059), .Y(n11061) );
NAND2X1TS U10724 ( .A(n11061), .B(n11060), .Y(n11062) );
XNOR2X1TS U10725 ( .A(n11063), .B(n11062), .Y(n11064) );
CLKMX2X2TS U10726 ( .A(n11064), .B(P_Sgf[7]), .S0(n11312), .Y(n428) );
XNOR2X1TS U10727 ( .A(n11065), .B(n11939), .Y(n11066) );
XOR2X1TS U10728 ( .A(n11118), .B(n11070), .Y(n11072) );
NAND2X1TS U10729 ( .A(n11318), .B(Sgf_normalized_result[10]), .Y(n11073) );
XOR2X1TS U10730 ( .A(n11073), .B(n11936), .Y(n11074) );
CLKMX2X2TS U10731 ( .A(n11074), .B(Add_result[11]), .S0(n11329), .Y(n568) );
INVX2TS U10732 ( .A(n11075), .Y(n11076) );
NAND2X1TS U10733 ( .A(n11077), .B(n11076), .Y(n11078) );
XNOR2X1TS U10734 ( .A(n11080), .B(n11079), .Y(n11081) );
CLKMX2X2TS U10735 ( .A(n11081), .B(Add_result[44]), .S0(n11097), .Y(n535) );
XNOR2X1TS U10736 ( .A(n11085), .B(n11084), .Y(n11086) );
NAND2X1TS U10737 ( .A(n11087), .B(n11262), .Y(n11088) );
XNOR2X1TS U10738 ( .A(n11090), .B(n11089), .Y(n11091) );
XNOR2X1TS U10739 ( .A(n11096), .B(n11095), .Y(n11098) );
CLKMX2X2TS U10740 ( .A(n11098), .B(Add_result[37]), .S0(n11097), .Y(n542) );
OAI22X1TS U10741 ( .A0(n11174), .A1(n11128), .B0(n11099), .B1(
FS_Module_state_reg[2]), .Y(n12381) );
AOI21X1TS U10742 ( .A0(n11106), .A1(n11105), .B0(n11104), .Y(n11109) );
INVX2TS U10743 ( .A(n11107), .Y(n11108) );
NAND2X1TS U10744 ( .A(n11112), .B(n11111), .Y(n11113) );
XNOR2X1TS U10745 ( .A(n11114), .B(n11113), .Y(n11115) );
NAND2X1TS U10746 ( .A(n11323), .B(n11321), .Y(n11119) );
INVX2TS U10747 ( .A(n580), .Y(n11120) );
XNOR2X1TS U10748 ( .A(n11121), .B(n11120), .Y(n11122) );
MXI2X1TS U10749 ( .A(n11124), .B(n1433), .S0(n11126), .Y(n416) );
INVX2TS U10750 ( .A(Data_MX[63]), .Y(n11130) );
MXI2X1TS U10751 ( .A(n11130), .B(n11893), .S0(n11131), .Y(n645) );
MXI2X1TS U10752 ( .A(n11892), .B(n12384), .S0(n11333), .Y(n579) );
MXI2X1TS U10753 ( .A(n11891), .B(n12378), .S0(n11333), .Y(n578) );
INVX2TS U10754 ( .A(Data_MY[63]), .Y(n11133) );
INVX2TS U10755 ( .A(Op_MY[63]), .Y(n11132) );
MXI2X1TS U10756 ( .A(n11133), .B(n11132), .S0(n11131), .Y(n715) );
MXI2X1TS U10757 ( .A(n11137), .B(n11971), .S0(n11293), .Y(n287) );
MXI2X1TS U10758 ( .A(n11138), .B(n11828), .S0(n11148), .Y(n702) );
INVX2TS U10759 ( .A(Data_MX[53]), .Y(n11140) );
BUFX8TS U10760 ( .A(n11139), .Y(n11169) );
MXI2X1TS U10761 ( .A(n11140), .B(n11831), .S0(n11169), .Y(n699) );
INVX2TS U10762 ( .A(Data_MX[54]), .Y(n11141) );
MXI2X1TS U10763 ( .A(n11141), .B(n11830), .S0(n11169), .Y(n700) );
INVX2TS U10764 ( .A(Data_MX[52]), .Y(n11142) );
MXI2X1TS U10765 ( .A(n11142), .B(n11832), .S0(n11169), .Y(n698) );
INVX2TS U10766 ( .A(Data_MX[58]), .Y(n11143) );
MXI2X1TS U10767 ( .A(n11143), .B(n11826), .S0(n11148), .Y(n704) );
INVX2TS U10768 ( .A(Data_MX[59]), .Y(n11144) );
MXI2X1TS U10769 ( .A(n11144), .B(n11825), .S0(n11148), .Y(n705) );
INVX2TS U10770 ( .A(Data_MX[57]), .Y(n11145) );
MXI2X1TS U10771 ( .A(n11145), .B(n11827), .S0(n11148), .Y(n703) );
INVX2TS U10772 ( .A(Data_MX[62]), .Y(n11146) );
MXI2X1TS U10773 ( .A(n11146), .B(n11823), .S0(n11148), .Y(n708) );
INVX2TS U10774 ( .A(Data_MX[60]), .Y(n11147) );
MXI2X1TS U10775 ( .A(n11147), .B(n11824), .S0(n11148), .Y(n706) );
INVX2TS U10776 ( .A(Data_MX[61]), .Y(n11149) );
MXI2X1TS U10777 ( .A(n11149), .B(n12149), .S0(n11148), .Y(n707) );
INVX2TS U10778 ( .A(Data_MY[53]), .Y(n11150) );
MXI2X1TS U10779 ( .A(n11150), .B(n11819), .S0(n11153), .Y(n635) );
INVX2TS U10780 ( .A(Data_MY[54]), .Y(n11151) );
MXI2X1TS U10781 ( .A(n11151), .B(n11818), .S0(n11153), .Y(n636) );
INVX2TS U10782 ( .A(Data_MY[55]), .Y(n11152) );
MXI2X1TS U10783 ( .A(n11152), .B(n11797), .S0(n11153), .Y(n637) );
INVX2TS U10784 ( .A(Data_MY[52]), .Y(n11154) );
MXI2X1TS U10785 ( .A(n11154), .B(n11956), .S0(n11153), .Y(n634) );
INVX2TS U10786 ( .A(Data_MY[62]), .Y(n11155) );
MXI2X1TS U10787 ( .A(n11155), .B(n11799), .S0(n11169), .Y(n644) );
INVX2TS U10788 ( .A(Data_MY[60]), .Y(n11156) );
MXI2X1TS U10789 ( .A(n11156), .B(n11801), .S0(n11169), .Y(n642) );
INVX2TS U10790 ( .A(Data_MY[58]), .Y(n11157) );
MXI2X1TS U10791 ( .A(n11157), .B(n11789), .S0(n11169), .Y(n640) );
INVX2TS U10792 ( .A(Data_MY[43]), .Y(n11158) );
MXI2X1TS U10793 ( .A(n11158), .B(n7036), .S0(n11171), .Y(n625) );
INVX2TS U10794 ( .A(Data_MY[61]), .Y(n11159) );
MXI2X1TS U10795 ( .A(n11159), .B(n11800), .S0(n11169), .Y(n643) );
INVX2TS U10796 ( .A(Data_MY[57]), .Y(n11160) );
MXI2X1TS U10797 ( .A(n11160), .B(n11790), .S0(n11169), .Y(n639) );
MXI2X1TS U10798 ( .A(n11161), .B(n11792), .S0(n11169), .Y(n641) );
INVX2TS U10799 ( .A(Data_MY[21]), .Y(n11162) );
MXI2X1TS U10800 ( .A(n11162), .B(n12029), .S0(n11167), .Y(n603) );
INVX2TS U10801 ( .A(Data_MY[25]), .Y(n11163) );
MXI2X1TS U10802 ( .A(n11163), .B(n12030), .S0(n11167), .Y(n607) );
MXI2X1TS U10803 ( .A(n11164), .B(n11955), .S0(n11167), .Y(n608) );
INVX2TS U10804 ( .A(Data_MY[23]), .Y(n11165) );
MXI2X1TS U10805 ( .A(n11165), .B(n12046), .S0(n11167), .Y(n605) );
INVX2TS U10806 ( .A(Data_MY[47]), .Y(n11166) );
MXI2X1TS U10807 ( .A(n11166), .B(n12112), .S0(n11171), .Y(n629) );
INVX2TS U10808 ( .A(Data_MY[24]), .Y(n11168) );
MXI2X1TS U10809 ( .A(n11168), .B(n2930), .S0(n11167), .Y(n606) );
INVX2TS U10810 ( .A(Data_MY[56]), .Y(n11170) );
MXI2X1TS U10811 ( .A(n11170), .B(n11791), .S0(n11169), .Y(n638) );
INVX2TS U10812 ( .A(Data_MY[49]), .Y(n11172) );
MXI2X1TS U10813 ( .A(n11172), .B(n7243), .S0(n11171), .Y(n631) );
NAND4X1TS U10814 ( .A(n11177), .B(n11176), .C(n11175), .D(n11174), .Y(n711)
);
NAND2X1TS U10815 ( .A(n11179), .B(n11178), .Y(n11181) );
XNOR2X1TS U10816 ( .A(n11181), .B(n11180), .Y(n11182) );
CLKMX2X2TS U10817 ( .A(n11182), .B(P_Sgf[2]), .S0(n12218), .Y(n423) );
CLKMX2X2TS U10818 ( .A(n11183), .B(P_Sgf[0]), .S0(n1011), .Y(n421) );
OR2X2TS U10819 ( .A(n11185), .B(n11184), .Y(n11187) );
AND2X2TS U10820 ( .A(n11187), .B(n11186), .Y(n11188) );
CLKMX2X2TS U10821 ( .A(n11188), .B(n1999), .S0(n1011), .Y(n11888) );
MXI2X1TS U10822 ( .A(Sgf_normalized_result[2]), .B(n12377), .S0(n11333), .Y(
n577) );
NAND4BBX1TS U10823 ( .AN(Op_MY[40]), .BN(Op_MY[44]), .C(n7036), .D(n11946),
.Y(n11189) );
INVX2TS U10824 ( .A(n11189), .Y(n11193) );
INVX2TS U10825 ( .A(n11190), .Y(n11192) );
AND4X1TS U10826 ( .A(n12133), .B(n7197), .C(n12134), .D(n11950), .Y(n11191)
);
NAND4X1TS U10827 ( .A(n11194), .B(n11193), .C(n11192), .D(n11191), .Y(n11199) );
NOR4X1TS U10828 ( .A(Op_MY[53]), .B(Op_MY[56]), .C(Op_MY[55]), .D(Op_MY[57]),
.Y(n11197) );
NOR4X1TS U10829 ( .A(Op_MY[58]), .B(Op_MY[60]), .C(Op_MY[59]), .D(Op_MY[61]),
.Y(n11196) );
NOR4X1TS U10830 ( .A(Op_MY[27]), .B(Op_MY[42]), .C(Op_MY[39]), .D(Op_MY[62]),
.Y(n11195) );
NAND4X1TS U10831 ( .A(n11197), .B(n11196), .C(n11195), .D(n1449), .Y(n11198)
);
NOR4X1TS U10832 ( .A(Op_MY[1]), .B(Op_MY[2]), .C(Op_MY[5]), .D(Op_MY[6]),
.Y(n11205) );
INVX2TS U10833 ( .A(n11200), .Y(n11204) );
NAND4BBX1TS U10834 ( .AN(Op_MY[18]), .BN(Op_MY[20]), .C(n11966), .D(n12046),
.Y(n11201) );
INVX2TS U10835 ( .A(n11201), .Y(n11203) );
AND4X2TS U10836 ( .A(n2930), .B(n12029), .C(n12030), .D(n11948), .Y(n11202)
);
NAND4X1TS U10837 ( .A(n11205), .B(n11204), .C(n11203), .D(n11202), .Y(n11212) );
AND4X1TS U10838 ( .A(n12112), .B(n12113), .C(n11951), .D(n11817), .Y(n11210)
);
NOR4X1TS U10839 ( .A(Op_MY[8]), .B(Op_MY[12]), .C(Op_MY[3]), .D(Op_MY[11]),
.Y(n11209) );
NAND4BBX1TS U10840 ( .AN(Op_MY[17]), .BN(Op_MY[7]), .C(n2125), .D(n11954),
.Y(n11206) );
INVX2TS U10841 ( .A(n11206), .Y(n11208) );
NOR4X1TS U10842 ( .A(Op_MY[33]), .B(Op_MY[0]), .C(Op_MY[4]), .D(Op_MY[46]),
.Y(n11207) );
NAND4X1TS U10843 ( .A(n11210), .B(n11209), .C(n11208), .D(n11207), .Y(n11211) );
NAND4BBX1TS U10844 ( .AN(n12146), .BN(n12209), .C(n11810), .D(n11944), .Y(
n11213) );
INVX2TS U10845 ( .A(n11213), .Y(n11218) );
NOR4BX1TS U10846 ( .AN(n11947), .B(Op_MX[39]), .C(Op_MX[29]), .D(Op_MX[31]),
.Y(n11216) );
AND4X1TS U10847 ( .A(n12151), .B(n11815), .C(n12150), .D(n11931), .Y(n11215)
);
NAND4X1TS U10848 ( .A(n11218), .B(n11217), .C(n11216), .D(n11215), .Y(n11224) );
NOR4X1TS U10849 ( .A(Op_MX[6]), .B(Op_MX[8]), .C(Op_MX[12]), .D(Op_MX[14]),
.Y(n11222) );
NOR4X1TS U10850 ( .A(Op_MX[16]), .B(Op_MX[2]), .C(Op_MX[10]), .D(Op_MX[22]),
.Y(n11221) );
NOR4X1TS U10851 ( .A(Op_MX[45]), .B(Op_MX[4]), .C(Op_MX[0]), .D(Op_MX[49]),
.Y(n11219) );
NAND4X1TS U10852 ( .A(n11222), .B(n11221), .C(n11220), .D(n11219), .Y(n11223) );
AND4X1TS U10853 ( .A(n11788), .B(n11811), .C(n11795), .D(n983), .Y(n11230)
);
NOR4BBX1TS U10854 ( .AN(n11225), .BN(n12244), .C(n12214), .D(n12212), .Y(
n11229) );
NOR4X1TS U10855 ( .A(n11814), .B(n12138), .C(n12215), .D(n11952), .Y(n11228)
);
INVX2TS U10856 ( .A(n11226), .Y(n11227) );
NAND4X1TS U10857 ( .A(n11230), .B(n11229), .C(n11228), .D(n11227), .Y(n11237) );
NOR4X1TS U10858 ( .A(Op_MX[56]), .B(Op_MX[53]), .C(n11231), .D(Op_MX[58]),
.Y(n11235) );
NOR4X1TS U10859 ( .A(Op_MX[57]), .B(Op_MX[60]), .C(Op_MX[59]), .D(Op_MX[62]),
.Y(n11234) );
NOR3X1TS U10860 ( .A(Op_MX[25]), .B(Op_MX[52]), .C(Op_MX[54]), .Y(n11232) );
NAND4X1TS U10861 ( .A(n11235), .B(n11234), .C(n11233), .D(n11232), .Y(n11236) );
AOI22X1TS U10862 ( .A0(n11241), .A1(n11240), .B0(n11239), .B1(n11238), .Y(
n11243) );
MXI2X1TS U10863 ( .A(n11243), .B(n11807), .S0(n11242), .Y(n581) );
AOI22X1TS U10864 ( .A0(n11249), .A1(n2118), .B0(n11244), .B1(n11270), .Y(
n12369) );
AOI22X1TS U10865 ( .A0(n11249), .A1(n2119), .B0(n11245), .B1(n11270), .Y(
n12372) );
AOI2BB2X1TS U10866 ( .B0(n11294), .B1(n11796), .A0N(n11251), .A1N(
final_result_ieee[52]), .Y(n299) );
AOI2BB2X1TS U10867 ( .B0(n11252), .B1(n1433), .A0N(n11251), .A1N(
final_result_ieee[53]), .Y(n298) );
AOI2BB2X1TS U10868 ( .B0(n11252), .B1(n3315), .A0N(n11251), .A1N(
final_result_ieee[54]), .Y(n297) );
AOI2BB2X1TS U10869 ( .B0(n11252), .B1(n12387), .A0N(n11251), .A1N(
final_result_ieee[57]), .Y(n294) );
AOI2BB2X1TS U10870 ( .B0(n11252), .B1(n12392), .A0N(n1431), .A1N(
final_result_ieee[62]), .Y(n289) );
AOI2BB2X1TS U10871 ( .B0(n11252), .B1(n12391), .A0N(n1431), .A1N(
final_result_ieee[61]), .Y(n290) );
AOI2BB2X1TS U10872 ( .B0(n11252), .B1(n12386), .A0N(n11251), .A1N(
final_result_ieee[56]), .Y(n295) );
AOI2BB2X1TS U10873 ( .B0(n11252), .B1(n12385), .A0N(n11251), .A1N(
final_result_ieee[55]), .Y(n296) );
AOI2BB2X1TS U10874 ( .B0(n11252), .B1(n12388), .A0N(n11251), .A1N(
final_result_ieee[58]), .Y(n293) );
AOI2BB2X1TS U10875 ( .B0(n11252), .B1(n12390), .A0N(n1431), .A1N(
final_result_ieee[60]), .Y(n291) );
AOI22X1TS U10876 ( .A0(n11254), .A1(Add_result[39]), .B0(n11253), .B1(n11281), .Y(n12304) );
BUFX8TS U10877 ( .A(n11254), .Y(n11276) );
AOI22X1TS U10878 ( .A0(n11276), .A1(n2120), .B0(n11255), .B1(n11270), .Y(
n12363) );
AOI22X1TS U10879 ( .A0(n11276), .A1(Add_result[26]), .B0(n11257), .B1(n11270), .Y(n12354) );
AOI22X1TS U10880 ( .A0(n11276), .A1(Add_result[30]), .B0(n11259), .B1(n11274), .Y(n12340) );
AOI22X1TS U10881 ( .A0(n10673), .A1(Add_result[34]), .B0(n11260), .B1(n11274), .Y(n12324) );
AOI22X1TS U10882 ( .A0(n10673), .A1(Add_result[41]), .B0(n11262), .B1(n11281), .Y(n12296) );
AOI22X1TS U10883 ( .A0(n11276), .A1(Add_result[29]), .B0(n11263), .B1(n11274), .Y(n12344) );
AOI22X1TS U10884 ( .A0(n10673), .A1(Add_result[38]), .B0(n11264), .B1(n11274), .Y(n12308) );
AOI22X1TS U10885 ( .A0(n10673), .A1(Add_result[36]), .B0(n11265), .B1(n11274), .Y(n12316) );
AOI22X1TS U10886 ( .A0(n11254), .A1(n2121), .B0(n11266), .B1(n11281), .Y(
n12292) );
AOI22X1TS U10887 ( .A0(n11254), .A1(Add_result[35]), .B0(n11267), .B1(n11274), .Y(n12320) );
AOI22X1TS U10888 ( .A0(n11276), .A1(Add_result[28]), .B0(n11268), .B1(n11270), .Y(n12348) );
AOI22X1TS U10889 ( .A0(n11254), .A1(Add_result[33]), .B0(n11269), .B1(n11274), .Y(n12328) );
AOI22X1TS U10890 ( .A0(n11276), .A1(Add_result[27]), .B0(n11271), .B1(n11270), .Y(n12351) );
AOI22X1TS U10891 ( .A0(n11276), .A1(Add_result[32]), .B0(n11272), .B1(n11274), .Y(n12332) );
AOI22X1TS U10892 ( .A0(n11254), .A1(Add_result[37]), .B0(n11273), .B1(n11274), .Y(n12312) );
AOI22X1TS U10893 ( .A0(n11276), .A1(Add_result[31]), .B0(n11275), .B1(n11274), .Y(n12336) );
AOI22X1TS U10894 ( .A0(n11285), .A1(Add_result[43]), .B0(n11277), .B1(n11281), .Y(n12288) );
AOI22X1TS U10895 ( .A0(n11285), .A1(n1992), .B0(n11278), .B1(n12216), .Y(
n12267) );
AOI22X1TS U10896 ( .A0(n11285), .A1(n2122), .B0(n11291), .B1(n11281), .Y(
n12280) );
AOI22X1TS U10897 ( .A0(n11285), .A1(Add_result[46]), .B0(n11279), .B1(n11281), .Y(n12276) );
AOI22X1TS U10898 ( .A0(n11285), .A1(Add_result[47]), .B0(n11282), .B1(n11281), .Y(n12272) );
AO22X1TS U10899 ( .A0(n11292), .A1(Sgf_normalized_result[6]), .B0(
final_result_ieee[6]), .B1(n11288), .Y(n345) );
AO22X1TS U10900 ( .A0(n11292), .A1(n2135), .B0(final_result_ieee[5]), .B1(
n11288), .Y(n346) );
AO22X1TS U10901 ( .A0(n11292), .A1(n2137), .B0(final_result_ieee[4]), .B1(
n11295), .Y(n347) );
AO22X1TS U10902 ( .A0(n11250), .A1(Sgf_normalized_result[2]), .B0(
final_result_ieee[2]), .B1(n11295), .Y(n349) );
NAND2X1TS U10903 ( .A(n11297), .B(n11296), .Y(n11299) );
XNOR2X1TS U10904 ( .A(n11299), .B(n11298), .Y(n11300) );
INVX2TS U10905 ( .A(n11301), .Y(n11303) );
NAND2X1TS U10906 ( .A(n11303), .B(n11302), .Y(n11304) );
XOR2X1TS U10907 ( .A(n11304), .B(n11305), .Y(n11306) );
CLKMX2X2TS U10908 ( .A(n11306), .B(P_Sgf[5]), .S0(n1978), .Y(n426) );
XNOR2X1TS U10909 ( .A(n11932), .B(Sgf_normalized_result[2]), .Y(n11307) );
CLKMX2X2TS U10910 ( .A(n11307), .B(Add_result[3]), .S0(n11333), .Y(n576) );
NAND2X1TS U10911 ( .A(n1750), .B(n11309), .Y(n11310) );
XOR2X1TS U10912 ( .A(n11311), .B(n11310), .Y(n11313) );
CLKMX2X2TS U10913 ( .A(n11313), .B(P_Sgf[6]), .S0(n1978), .Y(n427) );
XOR2X1TS U10914 ( .A(n11314), .B(n11889), .Y(n11315) );
CLKMX2X2TS U10915 ( .A(n11315), .B(Add_result[6]), .S0(n11319), .Y(n573) );
XNOR2X1TS U10916 ( .A(n11331), .B(n2137), .Y(n11317) );
CLKMX2X2TS U10917 ( .A(n11317), .B(Add_result[4]), .S0(n11333), .Y(n575) );
XNOR2X1TS U10918 ( .A(n11318), .B(n11941), .Y(n11320) );
CLKMX2X2TS U10919 ( .A(n11320), .B(Add_result[10]), .S0(n11319), .Y(n569) );
NAND2X1TS U10920 ( .A(n11323), .B(n11322), .Y(n11325) );
XOR2X1TS U10921 ( .A(n11328), .B(n11327), .Y(n11330) );
CLKMX2X2TS U10922 ( .A(n11330), .B(Add_result[18]), .S0(n11329), .Y(n561) );
NOR2XLTS U10923 ( .A(n11331), .B(Sgf_normalized_result[4]), .Y(n11332) );
XOR2X1TS U10924 ( .A(n11332), .B(n2135), .Y(n11334) );
CLKMX2X2TS U10925 ( .A(n11334), .B(Add_result[5]), .S0(n11333), .Y(n574) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_clk1.tcl_KOA_1STAGE_syn.sdf");
endmodule
|
/******************************************************************************
* File Name : data.v
* Version : 0.1
* Date : 2008 02 27
* Description: data source module
* Dependencies:
*
*
* Company: Beijing Soul
*
* BUG:
*
*****************************************************************************/
module data(/*AUTOARG*/
// Outputs
clk, rst, src_empty, ce, fo_full, m_last, fi, fi_cnt,
// Inputs
m_src_getn, m_endn
);
parameter LZF_WIDTH = 20;
parameter LZF_SIZE = 512;
parameter LZF_FILE = "../../../../files/01";
//parameter LZF_FILE = "../../../../files/texbook.pdf";
parameter LZF_DEBUG = 1;
parameter LZF_DELAY = 20;
parameter LZF_FIFO_AW = 5;
/* output parts */
output clk, rst, src_empty, ce, fo_full, m_last;
output [63:0] fi;
output [LZF_WIDTH-1:0] fi_cnt;
wire m_last;
reg clk = 1'b1;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg ce;
reg [LZF_WIDTH-1:0] fi_cnt;
reg fo_full;
reg rst;
reg src_empty;
// End of automatics
input m_src_getn, m_endn;
reg src_clr, src_we;
wire src_FIFO_full, src_FIFO_empty,
src_FIFO_emptyN, src_FIFO_fullN;
reg [63:0] src_din;
wire [63:0] fi;
wire [LZF_FIFO_AW-1:0] src_waddr, src_raddr;
wire src_rallow, src_wallow;
reg src_last;
fifo_control #(.ADDR_LENGTH(LZF_FIFO_AW))
src_FIFO (.rclock_in(clk),
.wclock_in(clk),
.renable_in(!m_src_getn),
.wenable_in(src_we),
.reset_in(rst),
.clear_in(rst),
.almost_empty_out(src_FIFO_emptyN),
.almost_full_out(src_FIFO_fullN),
.empty_out(src_FIFO_empty),
.waddr_out(src_waddr),
.raddr_out(src_raddr),
.rallow_out(src_rallow),
.wallow_out(src_wallow),
.full_out(src_FIFO_full));
tpram #(.aw(LZF_FIFO_AW), .dw(65))
src_mem (.clk_a(clk),
.rst_a(rst),
.ce_a(1'b1),
.we_a(src_wallow),
.addr_a(src_waddr),
.di_a({src_last, src_din}),
.do_a(),
.oe_a(1'b1),
.clk_b(clk),
.rst_b(rst),
.ce_b(1'b1),
.we_b(1'b0),
.oe_b(1'b1),
.addr_b(src_raddr),
.do_b({m_last, fi}),
.di_b(0));
always @(/*AS*/src_FIFO_empty or src_FIFO_emptyN)
if (src_FIFO_emptyN == 0 && src_FIFO_empty == 0)
src_empty = 0;
else
src_empty = 1;
reg [63:0] mem[65535:0];
reg [7:0] char;
integer i, f, j, k;
initial begin
ce = 0;
rst = 0;
src_clr = 0;
src_din = 0;
src_we = 0;
j = 0;
if (0 == $value$plusargs("size=%d", fi_cnt))
fi_cnt = LZF_SIZE;
$write("size is %h\n", fi_cnt);
fo_full = 0;
src_last = 0;
/* read the memory */
f = $fopen(LZF_FILE, "r");
for (i = 0; i < fi_cnt ; i = i + 8) begin
src_din[07:00] = $fgetc(f);
src_din[15:08] = $fgetc(f);
src_din[23:16] = $fgetc(f);
src_din[31:24] = $fgetc(f);
src_din[39:32] = $fgetc(f);
src_din[47:40] = $fgetc(f);
src_din[55:48] = $fgetc(f);
src_din[63:56] = $fgetc(f);
mem[j] = src_din;
j = j + 1;
end
/* reset */
@(negedge clk);
rst = 1;
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
rst = 0;
@(negedge clk);
ce = 1;
for (i = 0; i < j; f = f + 1/*loop*/) begin
if (src_empty && src_we == 0) begin
for (k = 0; k < LZF_DELAY; k = k + 1) begin
@(negedge clk);
end
src_we = 1;
end else if (src_FIFO_fullN) begin
src_we = 0;
end
src_din = mem[i];
if (src_we) begin
if (LZF_DEBUG) $write("%h:%h, %h\n", i, src_din, j);
i = i + 1;
end
@(negedge clk);
end
src_we = 0;
@(negedge clk);
src_last = 1'b1;
src_we = 1'b1;
@(negedge clk);
wait (!m_endn)
$finish;
end
always #7.5 clk = !clk;
endmodule // data
// Local Variables:
// verilog-library-directories:("." "../../common/")
// verilog-library-files:("")
// verilog-library-extensions:(".v" ".h")
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP_BEHAVIORAL_V
/**
* busdrivernovlp: Bus driver, enable gates pulldown only (pmoshvt
* devices).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__busdrivernovlp (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP_BEHAVIORAL_V |
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "mul4x4.v"
module alu(
input [WIDTH-1 : 0] a,
input [WIDTH-1 : 0] b,
input mul_enable,
input sub_enable,
input shift_enable,
input [2 : 0] shift_pos,
output [WIDTH-1 : 0] result,
output carry_out);
parameter WIDTH = 8;
wire [WIDTH-1 : 0] adder_res;
wire adder_carry;
wire [7 : 0] shift_res;
wire shift_carry;
wire [7: 0] mul_res;
assign result = (mul_enable) ? mul_res :
(shift_enable) ? shift_res :
(adder_res);
assign carry_out = (shift_enable) ? shift_carry :
adder_carry;
fadder #(.WIDTH(WIDTH)) ripple_adder(
.a(a),
.b(b),
.sub_enable(sub_enable),
.carry_in(sub_enable),
.res(adder_res),
.carry_out(adder_carry));
shl8 left_shift(
.a(a),
.shift(shift_pos),
.res(shift_res),
.carry(shift_carry));
mul4x4 multiply(a[3:0], a[7:4], mul_res);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////
// File name : SATA_TOP.v
// Note : This is the top module of SATA2 Host Controller
// Test/Verification Environment
// Dependencies : Nil
//////////////////////////////////////////////////////////////////////////////
module SATA_TOP#(
parameter integer CHIPSCOPE = 0
)
(
input TILE0_REFCLK_PAD_P_IN, // Input differential clock pin P 150MHZ
input TILE0_REFCLK_PAD_N_IN, // Input differential clock pin N 150MHZ
input GTPRESET_IN, // Reset input for GTP initialization
output TILE0_PLLLKDET_OUT, // GTP PLL Lock detected output
output TXP0_OUT, // SATA Connector TX P pin
output TXN0_OUT, // SATA Connector TX N pin
input RXP0_IN, // SATA Connector RX P pin
input RXN0_IN, // SATA Connector RX N pin
output DCMLOCKED_OUT, // PHY Layer DCM locked
output LINKUP, // SATA PHY initialisation completed LINK UP
output GEN2, // 1 when a SATA2 device detected, 0 when SATA1 device detected
output PHY_CLK_OUT, // PHY layer clock out
output CLK_OUT, // LINK and Transport Layer clock out CLK_OUT = PHY_CLK_OUT / 2
input HOST_READ_EN, // Read enable from host / user logic for Shadow register and PIO data
input HOST_WRITE_EN, // Write enable from host / user logic for Shadow register and PIO data
input [4:0] HOST_ADDR_REG, // Address bus for Shadow register
input [31:0] HOST_DATA_IN, // Data in bus for Shadow register and PIO data
output [31:0] HOST_DATA_OUT, // Data out bus for Shadow register and PIO data
output RESET_OUT, // Reset out for User logic this is from GTP reset out
output WRITE_HOLD_U, // Write HOLD signal for PIO and DMA write
output READ_HOLD_U, // Read HOLD signal for PIO and DMA read
input PIO_CLK_IN, // Clock in for PIO read / write
input DMA_CLK_IN, // Clock in for DMA read / write
input DMA_RQST, // DMA request. This should be 1 for DMA operation and 0 for PIO operation
output [31:0] DMA_RX_DATA_OUT, // DMA read data out bus
input DMA_RX_REN, // DMA read enable
input [31:0] DMA_TX_DATA_IN, // DMA write data in bus
input DMA_TX_WEN, // DMA write enable
input CE, // Chip enable
output IPF, // Interrupt pending flag
output DMA_TERMINATED, // This signal becomes 1 when a DMA terminate primitive get from Device (SSD)
output R_ERR, // set 1 when R_ERR Primitive received from disk
output ILLEGAL_STATE, // set 1 when illegal_state transition detected
input RX_FIFO_RESET, // reset signal for Receive data fifo
input TX_FIFO_RESET // reset signal for Transmit data fifo
);
wire [15:0] phy_rx_data_out;
wire [1:0] phy_rx_charisk_out;
wire [15:0] link_tx_data_out;
wire link_tx_charisk_out;
wire linkup_int;
wire phy_clk;
wire logic_reset;
wire [1:0] align_count;
wire clk;
//wire for link layer
wire [31:0] trnsp_tx_data_out;
wire [31:0] link_rx_data_out;
wire pmreq_p_t;
wire pmreq_s_t;
wire pm_en;
wire lreset;
wire data_rdy_t;
wire phy_detect_t;
wire illegal_state_t;
wire escapecf_t;
wire frame_end_t;
wire decerr;
wire tx_termn_t_o;
wire rx_fifo_rdy;
wire rx_fail_t;
wire crc_err_t;
wire valid_crc_t;
wire fis_err;
wire good_status_t;
wire unrecgnzd_fis_t;
//wire tx_termn_t_i;
wire r_ok_t;
wire r_err_t;
wire sof_t;
wire eof_t;
wire tx_rdy_ack_t;
wire data_out_vld_t;
wire r_ok_sent_t;
//for transport layer
wire dma_init;
wire dma_end;
wire stop_dma;
wire rx_fifo_empty;
wire hold_L;
wire cmd_done;
wire dma_tx_fifo_full;
wire dma_rx_fifo_empty;
wire data_in_rd_en_t;
wire x_rdy_sent_t;
wire tx_rdy_t;
assign PHY_CLK_OUT = phy_clk;
assign CLK_OUT = clk;
assign RESET_OUT = logic_reset;
assign R_ERR = r_err_t;
assign ILLEGAL_STATE = illegal_state_t;
sata_phy #(
.CHIPSCOPE (CHIPSCOPE)
)
PHY(
.TILE0_REFCLK_PAD_P_IN (TILE0_REFCLK_PAD_P_IN),
.TILE0_REFCLK_PAD_N_IN (TILE0_REFCLK_PAD_N_IN),
.GTPRESET_IN (GTPRESET_IN),
.TILE0_PLLLKDET_OUT (TILE0_PLLLKDET_OUT),
.TXP0_OUT (TXP0_OUT),
.TXN0_OUT (TXN0_OUT),
.RXP0_IN (RXP0_IN),
.RXN0_IN (RXN0_IN),
.DCMLOCKED_OUT (DCMLOCKED_OUT),
.LINKUP (linkup_int),
.logic_clk (phy_clk),
.GEN2 (GEN2),
.tx_data_in (link_tx_data_out),
.tx_charisk_in (link_tx_charisk_out),
.rx_data_out (phy_rx_data_out),
.rx_charisk_out (phy_rx_charisk_out),
.logic_reset (logic_reset),
.align_count (align_count),
.div2_logic_clock (clk)
);
assign LINKUP = linkup_int;
sata_link #(
.CHIPSCOPE (CHIPSCOPE)
)
LINK(
.CLK (clk),
.RESET (logic_reset),
.LINKUP (linkup_int),
.PHY_CLK (phy_clk),
.TX_DATA_OUT (link_tx_data_out),
.TX_CHARISK_OUT (link_tx_charisk_out),
.RX_DATA_IN (phy_rx_data_out),
.RX_CHARISK_IN (phy_rx_charisk_out),
.ALIGN_COUNT (align_count),
.TX_DATA_IN_DW (trnsp_tx_data_out),
.RX_DATA_OUT_DW (link_rx_data_out),
.PMREQ_P_T (1'b0), //pmreq_p_t),
.PMREQ_S_T (1'b0), //pmreq_s_t),
.PM_EN (1'b0),
.LRESET (1'b0), //lreset),
.DATA_RDY_T (data_rdy_t),
.PHY_DETECT_T (phy_detect_t),
.ILLEGAL_STATE_T (illegal_state_t),
.ESCAPECF_T (escapecf_t),
.FRAME_END_T (frame_end_t),
.DECERR (0),
.TX_TERMN_T_O (tx_termn_t_o),
.RX_FIFO_RDY (rx_fifo_rdy),
.RX_FAIL_T (rx_fail_t),
.CRC_ERR_T (crc_err_t),
.VALID_CRC_T (valid_crc_t),
.FIS_ERR (fis_err),
.GOOD_STATUS_T (good_status_t),
.UNRECGNZD_FIS_T (unrecgnzd_fis_t),
.TX_TERMN_T_I (1'b0), //(tx_termn_t_i),
.R_OK_T (r_ok_t),
.R_ERR_T (r_err_t),
.SOF_T (sof_t),
.EOF_T (eof_t),
.TX_RDY_ACK_T (tx_rdy_ack_t),
.DATA_OUT_VLD_T (data_out_vld_t),
.TX_RDY_T (tx_rdy_t),
.R_OK_SENT_T (r_ok_sent_t),
.DATA_IN_RD_EN_T (data_in_rd_en_t),
.X_RDY_SENT_T (x_rdy_sent_t),
.DMA_TERMINATED (DMA_TERMINATED)
);
sata_transport TRANSPORT (
.clk (clk),
.reset (logic_reset),
.DMA_RQST (DMA_RQST),
.data_in (HOST_DATA_IN), //output interface
.addr_reg (HOST_ADDR_REG), //output interface
.data_link_in (link_rx_data_out),
.LINK_DMA_ABORT (tx_termn_t_o),
.link_fis_recved_frm_dev (sof_t),
.phy_detect (phy_detect_t),
.H_write (HOST_WRITE_EN), //output interface
.H_read (HOST_READ_EN), //output interface
.link_txr_rdy (tx_rdy_ack_t),
.r_ok (r_ok_t),
.r_error (r_err_t),
.illegal_state (illegal_state_t),
.end_status (eof_t),
.data_link_out (trnsp_tx_data_out),
.FRAME_END_T (frame_end_t),
.hold_L (hold_L),
.WRITE_HOLD_U (WRITE_HOLD_U),
.READ_HOLD_U (READ_HOLD_U),
.txr_rdy (tx_rdy_t),
.data_out (HOST_DATA_OUT),
.EscapeCF_T (escapecf_t),
.UNRECGNZD_FIS_T (unrecgnzd_fis_t),
.IPF (IPF),
.FIS_ERR (fis_err),
.Good_status_T (good_status_t),
.RX_FIFO_RDY (rx_fifo_rdy),
.cmd_done (cmd_done),
.DMA_TX_DATA_IN (DMA_TX_DATA_IN),
.DMA_TX_WEN (DMA_TX_WEN),
.DMA_RX_DATA_OUT (DMA_RX_DATA_OUT),
.DMA_RX_REN (DMA_RX_REN),
.VALID_CRC_T (valid_crc_t),
.data_out_vld_T (data_out_vld_t),
.CRC_ERR_T (crc_err_t),
.DMA_INIT (1'b 0),
.DMA_END (dma_end),
.DATA_RDY_T (data_rdy_t),
.data_link_rd_en_t (data_in_rd_en_t),
.PIO_CLK_IN (PIO_CLK_IN),
.DMA_CLK_IN (DMA_CLK_IN),
.CE (CE),
.RX_FIFO_RESET (RX_FIFO_RESET),
.TX_FIFO_RESET (TX_FIFO_RESET)
);
endmodule
|
/*
* Wishbone Compatible BIOS ROM core using megafunction ROM
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
// The following is to get rid of the warning about not initializing the ROM
// altera message_off 10030
module bootrom (
input clk,
input rst,
// Wishbone slave interface
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [19:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input wb_stb_i,
input wb_cyc_i,
input [ 1:0] wb_sel_i,
output wb_ack_o
);
// Net declarations
reg [15:0] rom[0:8191]; // Instantiate the ROM
wire [ 12:0] rom_addr;
wire stb;
// Combinatorial logic
assign rom_addr = wb_adr_i[13:1];
assign stb = wb_stb_i & wb_cyc_i;
assign wb_ack_o = stb;
assign wb_dat_o = rom[rom_addr];
initial $readmemh("bootrom.dat", rom);
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 16:54:44 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire N4, N5, N8, N9, N11, N14, N15, N16, N18, EIGHTLENGTH_approx_cout,
DP_OP_9J21_122_982_n147, DP_OP_9J21_122_982_n146, n3, n4, n5, n6, n7,
n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21,
n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35,
n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49,
n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63,
n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77,
n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91,
n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104,
n105, n106, n107, n108, n109, n110, n111, n112, n113, n114, n115,
n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126,
n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137,
n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148,
n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159,
n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170,
n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181,
n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192,
n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, n203,
n204, n205, n206, n207, n208, n209, n210, n211, n212, n213, n214,
n215, n216, n217, n218, n219;
wire [15:0] EIGHTLENGTH_lower_in2_signed;
ACA_I_N16_Q8 EIGHTLENGTH_ApproxAdd ( .in1(in1[15:0]), .in2(
EIGHTLENGTH_lower_in2_signed), .res({EIGHTLENGTH_approx_cout,
res[15:0]}) );
AO22XLTS U20 ( .A0(n211), .A1(N18), .B0(n103), .B1(in2[15]), .Y(
EIGHTLENGTH_lower_in2_signed[15]) );
AO22XLTS U21 ( .A0(n211), .A1(n214), .B0(n213), .B1(in2[14]), .Y(
EIGHTLENGTH_lower_in2_signed[14]) );
AO22XLTS U22 ( .A0(n211), .A1(N16), .B0(n213), .B1(in2[13]), .Y(
EIGHTLENGTH_lower_in2_signed[13]) );
AO22XLTS U23 ( .A0(n211), .A1(N15), .B0(n213), .B1(in2[12]), .Y(
EIGHTLENGTH_lower_in2_signed[12]) );
AO22XLTS U24 ( .A0(n212), .A1(N14), .B0(n213), .B1(in2[11]), .Y(
EIGHTLENGTH_lower_in2_signed[11]) );
AO22XLTS U25 ( .A0(n212), .A1(n215), .B0(n213), .B1(in2[10]), .Y(
EIGHTLENGTH_lower_in2_signed[10]) );
AO22XLTS U26 ( .A0(n212), .A1(n216), .B0(n213), .B1(in2[9]), .Y(
EIGHTLENGTH_lower_in2_signed[9]) );
AO22XLTS U27 ( .A0(n212), .A1(N11), .B0(n213), .B1(in2[8]), .Y(
EIGHTLENGTH_lower_in2_signed[8]) );
AO22XLTS U28 ( .A0(n212), .A1(n217), .B0(n103), .B1(in2[7]), .Y(
EIGHTLENGTH_lower_in2_signed[7]) );
AO22XLTS U29 ( .A0(n212), .A1(N9), .B0(n103), .B1(in2[6]), .Y(
EIGHTLENGTH_lower_in2_signed[6]) );
AO22XLTS U30 ( .A0(n212), .A1(N8), .B0(n103), .B1(in2[5]), .Y(
EIGHTLENGTH_lower_in2_signed[5]) );
AO22XLTS U31 ( .A0(n212), .A1(n218), .B0(n103), .B1(in2[4]), .Y(
EIGHTLENGTH_lower_in2_signed[4]) );
AO22XLTS U32 ( .A0(n212), .A1(n219), .B0(n213), .B1(in2[3]), .Y(
EIGHTLENGTH_lower_in2_signed[3]) );
AO22XLTS U33 ( .A0(n212), .A1(N5), .B0(n213), .B1(in2[2]), .Y(
EIGHTLENGTH_lower_in2_signed[2]) );
AO22XLTS U34 ( .A0(add_sub), .A1(N4), .B0(n103), .B1(in2[1]), .Y(
EIGHTLENGTH_lower_in2_signed[1]) );
AO22XLTS U35 ( .A0(add_sub), .A1(in2[0]), .B0(n103), .B1(in2[0]), .Y(
EIGHTLENGTH_lower_in2_signed[0]) );
NAND2X1TS U36 ( .A(n137), .B(n136), .Y(n138) );
MX2X1TS U37 ( .A(in2[31]), .B(n65), .S0(n76), .Y(n102) );
INVX4TS U38 ( .A(n120), .Y(n132) );
INVX2TS U39 ( .A(n119), .Y(n129) );
NAND2X1TS U40 ( .A(n96), .B(in1[30]), .Y(n136) );
OR2X2TS U41 ( .A(n59), .B(in1[24]), .Y(n179) );
NAND2X1TS U42 ( .A(n26), .B(in1[18]), .Y(n147) );
NAND2X1TS U43 ( .A(in1[16]), .B(EIGHTLENGTH_approx_cout), .Y(
DP_OP_9J21_122_982_n147) );
NAND2BX2TS U44 ( .AN(in2[29]), .B(n68), .Y(n66) );
INVX4TS U45 ( .A(n103), .Y(n211) );
NOR2X2TS U46 ( .A(n80), .B(n70), .Y(n71) );
XNOR2X1TS U47 ( .A(n80), .B(in2[24]), .Y(n57) );
XNOR2X2TS U48 ( .A(n40), .B(in2[23]), .Y(n41) );
XNOR2X2TS U49 ( .A(n60), .B(in2[25]), .Y(n61) );
CLKINVX2TS U50 ( .A(n80), .Y(n74) );
INVX4TS U51 ( .A(add_sub), .Y(n103) );
NOR2X2TS U52 ( .A(in2[25]), .B(in2[24]), .Y(n73) );
NOR2X1TS U53 ( .A(in2[23]), .B(in2[22]), .Y(n53) );
INVX2TS U54 ( .A(n182), .Y(n11) );
NOR2X2TS U55 ( .A(n39), .B(in2[20]), .Y(n35) );
CLKMX2X2TS U56 ( .A(in2[25]), .B(n61), .S0(n211), .Y(n62) );
CLKMX2X4TS U57 ( .A(in2[29]), .B(n69), .S0(n211), .Y(n93) );
BUFX3TS U58 ( .A(n103), .Y(n213) );
OR2X1TS U59 ( .A(n26), .B(in1[18]), .Y(n151) );
INVX2TS U60 ( .A(n111), .Y(n174) );
OR2X2TS U61 ( .A(n47), .B(in1[23]), .Y(n3) );
OAI21X1TS U62 ( .A0(n194), .A1(n114), .B0(n198), .Y(n115) );
XNOR2X1TS U63 ( .A(n64), .B(in2[31]), .Y(n65) );
XNOR2X2TS U64 ( .A(n39), .B(in2[20]), .Y(n33) );
NOR3BX2TS U65 ( .AN(n54), .B(n39), .C(in2[22]), .Y(n40) );
INVX8TS U66 ( .A(n213), .Y(n76) );
XOR2X1TS U67 ( .A(n174), .B(n113), .Y(res[20]) );
XOR2X1TS U68 ( .A(n156), .B(n155), .Y(res[19]) );
NAND2X2TS U69 ( .A(n102), .B(in1[31]), .Y(n104) );
NOR2X1TS U70 ( .A(n193), .B(n114), .Y(n116) );
OR2X2TS U71 ( .A(n102), .B(in1[31]), .Y(n105) );
MX2X2TS U72 ( .A(in2[22]), .B(n4), .S0(n76), .Y(n46) );
NAND2X2TS U73 ( .A(n47), .B(in1[23]), .Y(n175) );
OR2X6TS U74 ( .A(n93), .B(in1[29]), .Y(n126) );
MX2X2TS U75 ( .A(in2[21]), .B(n36), .S0(n76), .Y(n43) );
MX2X2TS U76 ( .A(in2[19]), .B(n16), .S0(n76), .Y(n27) );
MX2X4TS U77 ( .A(in2[28]), .B(n72), .S0(n211), .Y(n92) );
MX2X4TS U78 ( .A(in2[27]), .B(n82), .S0(n211), .Y(n87) );
NAND2X2TS U79 ( .A(n24), .B(in1[17]), .Y(n143) );
XNOR2X2TS U80 ( .A(n15), .B(in2[19]), .Y(n16) );
MX2X2TS U81 ( .A(in2[17]), .B(n23), .S0(n76), .Y(n24) );
XNOR2X2TS U82 ( .A(n14), .B(in2[18]), .Y(n12) );
AND2X2TS U83 ( .A(n32), .B(n31), .Y(n55) );
XOR2X2TS U84 ( .A(n38), .B(in2[22]), .Y(n4) );
AOI21X2TS U85 ( .A0(n197), .A1(n119), .B0(n120), .Y(n110) );
XNOR2X1TS U86 ( .A(n5), .B(n63), .Y(res[25]) );
AO21X2TS U87 ( .A0(n197), .A1(n179), .B0(n85), .Y(n5) );
XNOR2X1TS U88 ( .A(n6), .B(n200), .Y(res[26]) );
AO21X2TS U89 ( .A0(n197), .A1(n196), .B0(n195), .Y(n6) );
XNOR2X1TS U90 ( .A(n7), .B(n118), .Y(res[27]) );
AO21X2TS U91 ( .A0(n197), .A1(n116), .B0(n115), .Y(n7) );
OR2X4TS U92 ( .A(n62), .B(in1[25]), .Y(n8) );
XOR2X1TS U93 ( .A(n110), .B(n109), .Y(res[28]) );
NAND2X4TS U94 ( .A(n56), .B(n32), .Y(n14) );
INVX8TS U95 ( .A(n100), .Y(n197) );
NAND2X4TS U96 ( .A(n8), .B(n179), .Y(n193) );
XOR2X2TS U97 ( .A(n128), .B(n127), .Y(res[29]) );
OR2X4TS U98 ( .A(in2[5]), .B(in2[4]), .Y(n182) );
OAI21X4TS U99 ( .A0(n30), .A1(n148), .B0(n29), .Y(n111) );
NAND2X2TS U100 ( .A(n151), .B(n154), .Y(n30) );
NOR3X4TS U101 ( .A(n80), .B(in2[28]), .C(n70), .Y(n68) );
MX2X4TS U102 ( .A(in2[30]), .B(n67), .S0(n211), .Y(n96) );
MX2X4TS U103 ( .A(in2[23]), .B(n41), .S0(n211), .Y(n47) );
NOR3X1TS U104 ( .A(n21), .B(n20), .C(in2[16]), .Y(n22) );
AOI21X2TS U105 ( .A0(n154), .A1(n150), .B0(n28), .Y(n29) );
NAND2X4TS U106 ( .A(n199), .B(n9), .Y(n91) );
NOR2X1TS U107 ( .A(in1[16]), .B(EIGHTLENGTH_approx_cout), .Y(
DP_OP_9J21_122_982_n146) );
OR2X2TS U108 ( .A(n24), .B(in1[17]), .Y(n144) );
OR2X2TS U109 ( .A(n27), .B(in1[19]), .Y(n154) );
INVX2TS U110 ( .A(n157), .Y(n45) );
INVX2TS U111 ( .A(n159), .Y(n44) );
OR2X2TS U112 ( .A(n46), .B(in1[22]), .Y(n170) );
NOR2X4TS U113 ( .A(n91), .B(n193), .Y(n119) );
OAI21X1TS U114 ( .A0(n132), .A1(n122), .B0(n121), .Y(n123) );
INVX2TS U115 ( .A(n39), .Y(n37) );
NAND2X4TS U116 ( .A(n126), .B(n108), .Y(n131) );
XOR2X1TS U117 ( .A(n66), .B(in2[30]), .Y(n67) );
AOI21X2TS U118 ( .A0(n126), .A1(n95), .B0(n94), .Y(n130) );
XOR2X1TS U119 ( .A(n56), .B(in2[16]), .Y(n17) );
NOR2X2TS U120 ( .A(n96), .B(in1[30]), .Y(n135) );
NAND2X1TS U121 ( .A(n144), .B(n143), .Y(n145) );
NAND2X1TS U122 ( .A(n160), .B(n159), .Y(n161) );
NAND2X1TS U123 ( .A(n163), .B(n170), .Y(n164) );
NAND2X1TS U124 ( .A(n3), .B(n175), .Y(n176) );
NAND2X1TS U125 ( .A(n179), .B(n178), .Y(n180) );
NAND2X1TS U126 ( .A(n108), .B(n121), .Y(n109) );
NAND2X1TS U127 ( .A(n126), .B(n125), .Y(n127) );
NOR2X1TS U128 ( .A(n129), .B(n122), .Y(n124) );
OR2X4TS U129 ( .A(n87), .B(in1[27]), .Y(n9) );
NOR2X2TS U130 ( .A(n80), .B(n79), .Y(n81) );
NAND2X4TS U131 ( .A(n170), .B(n3), .Y(n50) );
AOI21X4TS U132 ( .A0(n146), .A1(n144), .B0(n25), .Y(n148) );
NAND2X2TS U133 ( .A(n37), .B(n54), .Y(n38) );
MXI2X4TS U134 ( .A(n58), .B(n57), .S0(n76), .Y(n59) );
OR4X8TS U135 ( .A(n10), .B(in2[15]), .C(in2[14]), .D(n190), .Y(n21) );
NAND4BX4TS U136 ( .AN(n184), .B(n11), .C(n185), .D(n183), .Y(n20) );
INVX4TS U137 ( .A(n122), .Y(n108) );
XOR2X2TS U138 ( .A(n139), .B(n138), .Y(res[30]) );
MXI2X4TS U139 ( .A(n13), .B(n12), .S0(n76), .Y(n26) );
NAND4X8TS U140 ( .A(n56), .B(n55), .C(n54), .D(n53), .Y(n80) );
AOI21X2TS U141 ( .A0(n98), .A1(n120), .B0(n97), .Y(n99) );
OAI21X2TS U142 ( .A0(n130), .A1(n135), .B0(n136), .Y(n97) );
XOR2X4TS U143 ( .A(n75), .B(n78), .Y(n77) );
NAND2X2TS U144 ( .A(n74), .B(n73), .Y(n75) );
NAND2X8TS U145 ( .A(n56), .B(n55), .Y(n39) );
AOI21X4TS U146 ( .A0(n8), .A1(n85), .B0(n84), .Y(n194) );
AOI21X4TS U147 ( .A0(n160), .A1(n45), .B0(n44), .Y(n168) );
NOR2X4TS U148 ( .A(n135), .B(n131), .Y(n98) );
NOR2XLTS U149 ( .A(in2[14]), .B(n209), .Y(n210) );
NAND2X1TS U150 ( .A(n140), .B(DP_OP_9J21_122_982_n147), .Y(n141) );
NAND2X1TS U151 ( .A(n9), .B(n117), .Y(n118) );
INVX2TS U152 ( .A(in2[18]), .Y(n13) );
OR4X8TS U153 ( .A(in2[13]), .B(in2[12]), .C(in2[3]), .D(in2[2]), .Y(n10) );
OR2X4TS U154 ( .A(in2[1]), .B(in2[0]), .Y(n190) );
OR2X2TS U155 ( .A(in2[8]), .B(in2[9]), .Y(n184) );
NOR2X2TS U156 ( .A(in2[11]), .B(in2[10]), .Y(n185) );
NOR2X2TS U157 ( .A(in2[7]), .B(in2[6]), .Y(n183) );
NOR2X8TS U158 ( .A(n21), .B(n20), .Y(n56) );
NOR2X2TS U159 ( .A(in2[17]), .B(in2[16]), .Y(n32) );
NOR2X4TS U160 ( .A(n14), .B(in2[18]), .Y(n15) );
INVX2TS U161 ( .A(in2[16]), .Y(n18) );
MXI2X2TS U162 ( .A(n18), .B(n17), .S0(n76), .Y(n142) );
INVX2TS U163 ( .A(n142), .Y(n19) );
OAI21X2TS U164 ( .A0(n19), .A1(DP_OP_9J21_122_982_n146), .B0(
DP_OP_9J21_122_982_n147), .Y(n146) );
XNOR2X1TS U165 ( .A(n22), .B(in2[17]), .Y(n23) );
INVX2TS U166 ( .A(n143), .Y(n25) );
INVX2TS U167 ( .A(n147), .Y(n150) );
NAND2X2TS U168 ( .A(n27), .B(in1[19]), .Y(n153) );
INVX2TS U169 ( .A(n153), .Y(n28) );
INVX2TS U170 ( .A(in2[20]), .Y(n34) );
NOR2X1TS U171 ( .A(in2[19]), .B(in2[18]), .Y(n31) );
MXI2X2TS U172 ( .A(n34), .B(n33), .S0(n76), .Y(n42) );
NOR2X2TS U173 ( .A(n42), .B(in1[20]), .Y(n158) );
INVX2TS U174 ( .A(n158), .Y(n112) );
XNOR2X1TS U175 ( .A(n35), .B(in2[21]), .Y(n36) );
OR2X4TS U176 ( .A(n43), .B(in1[21]), .Y(n160) );
NAND2X2TS U177 ( .A(n112), .B(n160), .Y(n166) );
NOR2X2TS U178 ( .A(in2[21]), .B(in2[20]), .Y(n54) );
NOR2X2TS U179 ( .A(n166), .B(n50), .Y(n52) );
NAND2X2TS U180 ( .A(n42), .B(in1[20]), .Y(n157) );
NAND2X2TS U181 ( .A(n43), .B(in1[21]), .Y(n159) );
NAND2X2TS U182 ( .A(n46), .B(in1[22]), .Y(n163) );
INVX2TS U183 ( .A(n163), .Y(n169) );
INVX2TS U184 ( .A(n175), .Y(n48) );
AOI21X4TS U185 ( .A0(n3), .A1(n169), .B0(n48), .Y(n49) );
OAI21X4TS U186 ( .A0(n168), .A1(n50), .B0(n49), .Y(n51) );
AOI21X4TS U187 ( .A0(n111), .A1(n52), .B0(n51), .Y(n100) );
INVX2TS U188 ( .A(in2[24]), .Y(n58) );
NAND2X2TS U189 ( .A(n59), .B(in1[24]), .Y(n178) );
INVX2TS U190 ( .A(n178), .Y(n85) );
NOR2X4TS U191 ( .A(n80), .B(in2[24]), .Y(n60) );
NAND2X2TS U192 ( .A(n62), .B(in1[25]), .Y(n83) );
NAND2X1TS U193 ( .A(n8), .B(n83), .Y(n63) );
INVX2TS U194 ( .A(in2[26]), .Y(n78) );
NAND2X1TS U195 ( .A(n73), .B(n78), .Y(n79) );
OR2X2TS U196 ( .A(n79), .B(in2[27]), .Y(n70) );
NOR2X1TS U197 ( .A(n66), .B(in2[30]), .Y(n64) );
XNOR2X1TS U198 ( .A(n68), .B(in2[29]), .Y(n69) );
XNOR2X1TS U199 ( .A(n71), .B(in2[28]), .Y(n72) );
NOR2X2TS U200 ( .A(n92), .B(in1[28]), .Y(n122) );
MXI2X4TS U201 ( .A(n78), .B(n77), .S0(n76), .Y(n86) );
NOR2X2TS U202 ( .A(n86), .B(in1[26]), .Y(n114) );
INVX2TS U203 ( .A(n114), .Y(n199) );
XNOR2X1TS U204 ( .A(n81), .B(in2[27]), .Y(n82) );
NAND2X1TS U205 ( .A(n98), .B(n119), .Y(n101) );
INVX2TS U206 ( .A(n83), .Y(n84) );
NAND2X2TS U207 ( .A(n86), .B(in1[26]), .Y(n198) );
INVX2TS U208 ( .A(n198), .Y(n89) );
NAND2X2TS U209 ( .A(n87), .B(in1[27]), .Y(n117) );
INVX2TS U210 ( .A(n117), .Y(n88) );
AOI21X2TS U211 ( .A0(n9), .A1(n89), .B0(n88), .Y(n90) );
OAI21X4TS U212 ( .A0(n194), .A1(n91), .B0(n90), .Y(n120) );
NAND2X2TS U213 ( .A(n92), .B(in1[28]), .Y(n121) );
INVX2TS U214 ( .A(n121), .Y(n95) );
NAND2X2TS U215 ( .A(n93), .B(in1[29]), .Y(n125) );
INVX2TS U216 ( .A(n125), .Y(n94) );
OAI21X2TS U217 ( .A0(n101), .A1(n100), .B0(n99), .Y(n107) );
OAI2BB1X2TS U218 ( .A0N(n105), .A1N(n107), .B0(n104), .Y(res[32]) );
INVX2TS U219 ( .A(n103), .Y(n212) );
NAND2X2TS U220 ( .A(n105), .B(n104), .Y(n106) );
XNOR2X1TS U221 ( .A(n107), .B(n106), .Y(res[31]) );
NAND2X1TS U222 ( .A(n112), .B(n157), .Y(n113) );
AOI21X2TS U223 ( .A0(n197), .A1(n124), .B0(n123), .Y(n128) );
NOR2X1TS U224 ( .A(n129), .B(n131), .Y(n134) );
OAI21X1TS U225 ( .A0(n132), .A1(n131), .B0(n130), .Y(n133) );
AOI21X2TS U226 ( .A0(n197), .A1(n134), .B0(n133), .Y(n139) );
INVX2TS U227 ( .A(n135), .Y(n137) );
INVX2TS U228 ( .A(DP_OP_9J21_122_982_n146), .Y(n140) );
XNOR2X1TS U229 ( .A(n142), .B(n141), .Y(res[16]) );
XNOR2X1TS U230 ( .A(n146), .B(n145), .Y(res[17]) );
NAND2X1TS U231 ( .A(n151), .B(n147), .Y(n149) );
INVX2TS U232 ( .A(n148), .Y(n152) );
XNOR2X1TS U233 ( .A(n149), .B(n152), .Y(res[18]) );
AOI21X1TS U234 ( .A0(n152), .A1(n151), .B0(n150), .Y(n156) );
NAND2X1TS U235 ( .A(n154), .B(n153), .Y(n155) );
OAI21X1TS U236 ( .A0(n174), .A1(n158), .B0(n157), .Y(n162) );
XNOR2X1TS U237 ( .A(n162), .B(n161), .Y(res[21]) );
OAI21X1TS U238 ( .A0(n174), .A1(n166), .B0(n168), .Y(n165) );
XNOR2X1TS U239 ( .A(n165), .B(n164), .Y(res[22]) );
INVX2TS U240 ( .A(n166), .Y(n167) );
NAND2X1TS U241 ( .A(n167), .B(n170), .Y(n173) );
INVX2TS U242 ( .A(n168), .Y(n171) );
AOI21X1TS U243 ( .A0(n171), .A1(n170), .B0(n169), .Y(n172) );
OAI21X1TS U244 ( .A0(n174), .A1(n173), .B0(n172), .Y(n177) );
XNOR2X1TS U245 ( .A(n177), .B(n176), .Y(res[23]) );
XNOR2X1TS U246 ( .A(n197), .B(n180), .Y(res[24]) );
NOR2X1TS U247 ( .A(in2[2]), .B(n190), .Y(n201) );
INVX2TS U248 ( .A(in2[3]), .Y(n181) );
NAND2X1TS U249 ( .A(n201), .B(n181), .Y(n202) );
NOR2X2TS U250 ( .A(n182), .B(n202), .Y(n204) );
NAND2X1TS U251 ( .A(n183), .B(n204), .Y(n205) );
NOR2X2TS U252 ( .A(n205), .B(n184), .Y(n207) );
NAND2X1TS U253 ( .A(n185), .B(n207), .Y(n187) );
NOR2X1TS U254 ( .A(in2[12]), .B(n187), .Y(n208) );
INVX2TS U255 ( .A(in2[13]), .Y(n186) );
NAND2X1TS U256 ( .A(n208), .B(n186), .Y(n209) );
XOR2XLTS U257 ( .A(in2[14]), .B(n209), .Y(n214) );
XOR2XLTS U258 ( .A(in2[12]), .B(n187), .Y(N15) );
XOR2XLTS U259 ( .A(in2[8]), .B(n205), .Y(N11) );
INVX2TS U260 ( .A(in2[10]), .Y(n188) );
NAND2X1TS U261 ( .A(n207), .B(n188), .Y(n189) );
XOR2XLTS U262 ( .A(in2[11]), .B(n189), .Y(N14) );
XOR2XLTS U263 ( .A(in2[2]), .B(n190), .Y(N5) );
INVX2TS U264 ( .A(in2[6]), .Y(n191) );
NAND2X1TS U265 ( .A(n204), .B(n191), .Y(n192) );
XOR2XLTS U266 ( .A(in2[7]), .B(n192), .Y(n217) );
XOR2XLTS U267 ( .A(in2[1]), .B(in2[0]), .Y(N4) );
XOR2XLTS U268 ( .A(in2[4]), .B(n202), .Y(n218) );
INVX2TS U269 ( .A(n193), .Y(n196) );
INVX2TS U270 ( .A(n194), .Y(n195) );
NAND2X1TS U271 ( .A(n199), .B(n198), .Y(n200) );
XNOR2X1TS U272 ( .A(in2[3]), .B(n201), .Y(n219) );
NOR2XLTS U273 ( .A(in2[4]), .B(n202), .Y(n203) );
XNOR2X1TS U274 ( .A(in2[5]), .B(n203), .Y(N8) );
XNOR2X1TS U275 ( .A(in2[6]), .B(n204), .Y(N9) );
NOR2XLTS U276 ( .A(in2[8]), .B(n205), .Y(n206) );
XNOR2X1TS U277 ( .A(in2[9]), .B(n206), .Y(n216) );
XNOR2X1TS U278 ( .A(in2[10]), .B(n207), .Y(n215) );
XNOR2X1TS U279 ( .A(in2[13]), .B(n208), .Y(N16) );
XNOR2X1TS U280 ( .A(in2[15]), .B(n210), .Y(N18) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_ACAIN16Q8_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_PP_BLACKBOX_V
/**
* lpflow_inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_inputiso0p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S50_SYMBOL_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S50_SYMBOL_V
/**
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
* gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkdlybuf4s50 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S50_SYMBOL_V
|
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 14-2-2016
Based on information posted by Nemesis on:
http://gendev.spritesmind.net/forum/viewtopic.php?t=386&postdays=0&postorder=asc&start=167
Based on jt51_phasegen.v, from JT51
*/
/*
tab size 4
*/
module jt12_pg(
input clk,
input clk_en /* synthesis direct_enable */,
input rst,
// Channel frequency
input [10:0] fnum_I,
input [ 2:0] block_I,
// Operator multiplying
input [ 3:0] mul_II,
// Operator detuning
input [ 2:0] dt1_I, // same as JT51's DT1
// phase modulation from LFO
input [ 6:0] lfo_mod,
input [ 2:0] pms_I,
// phase operation
input pg_rst_II,
input pg_stop, // not implemented
output reg [ 4:0] keycode_II,
output [ 9:0] phase_VIII
);
parameter num_ch=6;
wire [4:0] keycode_I;
wire signed [5:0] detune_mod_I;
reg signed [5:0] detune_mod_II;
wire [16:0] phinc_I;
reg [16:0] phinc_II;
wire [19:0] phase_drop, phase_in;
wire [ 9:0] phase_II;
always @(posedge clk) if(clk_en) begin
keycode_II <= keycode_I;
detune_mod_II <= detune_mod_I;
phinc_II <= phinc_I;
end
jt12_pg_comb u_comb(
.block ( block_I ),
.fnum ( fnum_I ),
// Phase Modulation
.lfo_mod ( lfo_mod[6:2] ),
.pms ( pms_I ),
// Detune
.detune ( dt1_I ),
.keycode ( keycode_I ),
.detune_out ( detune_mod_I ),
// Phase increment
.phinc_out ( phinc_I ),
// Phase add
.mul ( mul_II ),
.phase_in ( phase_drop ),
.pg_rst ( pg_rst_II ),
.detune_in ( detune_mod_II ),
.phinc_in ( phinc_II ),
.phase_out ( phase_in ),
.phase_op ( phase_II )
);
jt12_sh_rst #( .width(20), .stages(4*num_ch) ) u_phsh(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( phase_in ),
.drop ( phase_drop)
);
jt12_sh_rst #( .width(10), .stages(6) ) u_pad(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( phase_II ),
.drop ( phase_VIII)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVP_BLACKBOX_V
`define SKY130_FD_SC_LS__EINVP_BLACKBOX_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__einvp (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVP_BLACKBOX_V
|
/* Concrete parameterizations of argmin for testing.
*
* Copyright (c) 2016, Stephen Longfield, stephenlongfield.com
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`include "argmin_10.v"
module argmin_test(
input clk,
input rst,
input wire [10*32-1:0] inp,
output wire [31:0] outp,
output wire [3:0] outp_addr
);
argmin_10#(.WIDTH(32)) am(clk, rst, inp, outp, outp_addr);
endmodule
|
`default_nettype none
module scheduler2_gr
#(
parameter ENTRY_ID = 6'h00
)(
//System
input wire iCLOCK,
input wire inRESET,
//Remove
input wire iFREE_RESTART,
//Commit_Vector
input wire [63:0] iCOMMIT_VECTOR,
//Regist
input wire iREGIST_0_VALID,
input wire [5:0] iREGIST_0_DESTINATION_REGNAME,
input wire [4:0] iREGIST_0_LOGIC_DESTINATION,
input wire [5:0] iREGIST_0_COMMIT_TAG,
input wire iREGIST_1_VALID,
input wire [5:0] iREGIST_1_DESTINATION_REGNAME,
input wire [4:0] iREGIST_1_LOGIC_DESTINATION,
input wire [5:0] iREGIST_1_COMMIT_TAG,
//EXEEND
input wire iEXEND_ADDER_VALID,
input wire [5:0] iEXEND_ADDER_COMMIT_TAG,
input wire [5:0] iEXEND_ADDER_REGNAME,
input wire [31:0] iEXEND_ADDER_DATA,
input wire iEXEND_MULDIV_VALID,
input wire [5:0] iEXEND_MULDIV_COMMIT_TAG,
input wire [5:0] iEXEND_MULDIV_REGNAME,
input wire [31:0] iEXEND_MULDIV_DATA,
input wire iEXEND_LDST_VALID,
input wire [5:0] iEXEND_LDST_COMMIT_TAG,
input wire [5:0] iEXEND_LDST_REGNAME,
input wire [31:0] iEXEND_LDST_DATA,
//Free List Valid
input wire iFREELIST_REGIST_VALID,
//INFO
output wire oINFO_FREELIST_REQ,
output wire oINFO_DATA_VALID,
output wire [31:0] oINFO_DATA
);
localparam PL_MAIN_STT_RESET = 2'h0;
localparam PL_MAIN_STT_INIT = 2'h1;
localparam PL_MAIN_STT_FREELIST = 2'h2;
localparam PL_MAIN_STT_RESERVE = 2'h3;
reg [1:0] b_main_state;
//Cuurent Entry
reg b_entry_valid;
reg [5:0] b_entry_commit_tag;
reg [4:0] b_entry_logic_dest;
reg b_entry_exe_end;
reg [31:0] b_entry_exe_data;
reg b_entry_exe_commit;
//Next Entry
reg b_next_entry_valid;
reg [5:0] b_next_entry_commit_tag;
reg b_next_entry_exe_end;
reg b_next_exe_commit;
wire init_physical_register = ENTRY_ID < 32;
wire pipe0_cuur_entry_register_condition = iREGIST_0_VALID && (iREGIST_0_DESTINATION_REGNAME == ENTRY_ID);// && (b_main_state == PL_MAIN_STT_RESERVE);
wire pipe1_cuur_entry_register_condition = iREGIST_1_VALID && (iREGIST_1_DESTINATION_REGNAME == ENTRY_ID);// && (b_main_state == PL_MAIN_STT_RESERVE);
wire pipe0_next_entry_register_condition = iREGIST_0_VALID && b_entry_valid && (iREGIST_0_LOGIC_DESTINATION == b_entry_logic_dest);
wire pipe1_next_entry_register_condition = (iREGIST_1_VALID && b_entry_valid && (iREGIST_1_LOGIC_DESTINATION == b_entry_logic_dest)) ||
(pipe0_cuur_entry_register_condition && iREGIST_1_VALID && (iREGIST_0_LOGIC_DESTINATION == iREGIST_1_LOGIC_DESTINATION));
wire freelist_req_condition = (b_main_state == PL_MAIN_STT_FREELIST);
wire cuur_commit_reset = freelist_req_condition;
wire cuur_entry_reset = freelist_req_condition || (iFREE_RESTART && (b_main_state == PL_MAIN_STT_RESERVE) && !b_entry_exe_commit);
wire cuur_exe_end_reset = freelist_req_condition || (iFREE_RESTART && (b_main_state == PL_MAIN_STT_RESERVE) && !b_entry_exe_commit);
wire next_commit_reset = freelist_req_condition;
wire next_entry_reset = freelist_req_condition || (iFREE_RESTART && (b_main_state == PL_MAIN_STT_RESERVE || b_main_state == PL_MAIN_STT_INIT) && !b_next_exe_commit);
wire next_exe_end_reset = freelist_req_condition || (iFREE_RESTART && (b_main_state == PL_MAIN_STT_RESERVE || b_main_state == PL_MAIN_STT_INIT) && !b_next_exe_commit);
//init_physical_register && (b_main_state == PL_MAIN_STT_INIT);
/*****************************************************
Main State
*****************************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_main_state <= PL_MAIN_STT_RESET;
end
else begin
case(b_main_state)
PL_MAIN_STT_RESET:
begin
if(init_physical_register)begin
b_main_state <= PL_MAIN_STT_INIT;
end
else begin
b_main_state <= PL_MAIN_STT_FREELIST;
end
end
PL_MAIN_STT_INIT:
begin
if(b_next_entry_exe_end && b_next_exe_commit)begin
b_main_state <= PL_MAIN_STT_FREELIST;
end
end
PL_MAIN_STT_FREELIST:
begin
if(iFREELIST_REGIST_VALID && !iFREE_RESTART)begin
b_main_state <= PL_MAIN_STT_RESERVE;
end
end
PL_MAIN_STT_RESERVE:
begin
if((/*b_entry_valid && b_entry_exe_end && b_entry_exe_data && b_next_entry_valid && b_next_entry_exe_end && b_next_exe_commit*/b_entry_exe_commit && b_next_exe_commit) ||
(iFREE_RESTART && !b_entry_exe_commit))
begin
b_main_state <= PL_MAIN_STT_FREELIST;
end
end
endcase
end
end
/*****************************************************
Current Entry
*****************************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_entry_valid <= 1'b0;
b_entry_commit_tag <= 6'h0;
b_entry_logic_dest <= 5'h0;
end
else if(cuur_entry_reset)begin
b_entry_valid <= 1'b0;
b_entry_commit_tag <= 6'h0;
b_entry_logic_dest <= 5'h0;
end
else begin
if(init_physical_register && b_main_state == PL_MAIN_STT_INIT)begin
b_entry_valid <= 1'b1;
b_entry_commit_tag <= 6'h0;
b_entry_logic_dest <= ENTRY_ID;
end
else if(pipe0_cuur_entry_register_condition)begin
b_entry_valid <= 1'b1;
b_entry_commit_tag <= iREGIST_0_COMMIT_TAG;
b_entry_logic_dest <= iREGIST_0_LOGIC_DESTINATION;
end
else if(pipe1_cuur_entry_register_condition)begin
b_entry_valid <= 1'b1;
b_entry_commit_tag <= iREGIST_1_COMMIT_TAG;
b_entry_logic_dest <= iREGIST_1_LOGIC_DESTINATION;
end
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_entry_exe_end <= 1'b0;
b_entry_exe_data <= 32'h0;
end
else if(cuur_exe_end_reset)begin
b_entry_exe_end <= 1'b0;
b_entry_exe_data <= 32'h0;
end
else begin
if(!b_entry_exe_end && b_entry_valid)begin
if(init_physical_register && b_main_state == PL_MAIN_STT_INIT)begin
b_entry_exe_end <= 1'b1;
b_entry_exe_data <= 32'h0;
end
else if(iEXEND_ADDER_VALID && b_entry_commit_tag == iEXEND_ADDER_COMMIT_TAG)begin
b_entry_exe_end <= 1'b1;
b_entry_exe_data <= iEXEND_ADDER_DATA;
end
else if(iEXEND_MULDIV_VALID && b_entry_commit_tag == iEXEND_MULDIV_COMMIT_TAG)begin
b_entry_exe_end <= 1'b1;
b_entry_exe_data <= iEXEND_MULDIV_DATA;
end
else if(iEXEND_LDST_VALID && b_entry_commit_tag == iEXEND_LDST_COMMIT_TAG)begin
b_entry_exe_end <= 1'b1;
b_entry_exe_data <= iEXEND_LDST_DATA;
end
end
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_entry_exe_commit <= 1'b0;
end
else if(cuur_commit_reset)begin
b_entry_exe_commit <= 1'b0;
end
else begin
if(b_entry_valid && b_entry_exe_end && !b_entry_exe_commit)begin
b_entry_exe_commit <= iCOMMIT_VECTOR[b_entry_commit_tag];
end
end
end
/*****************************************************
Next Entry
*****************************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_next_entry_valid <= 1'b0;
b_next_entry_commit_tag <= 6'h0;
end
else if(next_entry_reset)begin
b_next_entry_valid <= 1'b0;
b_next_entry_commit_tag <= 6'h0;
end
else begin
if(pipe0_next_entry_register_condition)begin
b_next_entry_valid <= 1'b1;
b_next_entry_commit_tag <= iREGIST_0_COMMIT_TAG;
end
else if(pipe1_next_entry_register_condition)begin
b_next_entry_valid <= 1'b1;
b_next_entry_commit_tag <= iREGIST_1_COMMIT_TAG;
end
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_next_entry_exe_end <= 1'b0;
end
else if(next_exe_end_reset)begin
b_next_entry_exe_end <= 1'b0;
end
else begin
if(b_next_entry_valid && iEXEND_ADDER_VALID && b_next_entry_commit_tag == iEXEND_ADDER_COMMIT_TAG)begin
b_next_entry_exe_end <= 1'b1;
end
else if(b_next_entry_valid && iEXEND_MULDIV_VALID && b_next_entry_commit_tag == iEXEND_MULDIV_COMMIT_TAG)begin
b_next_entry_exe_end <= 1'b1;
end
else if(b_next_entry_valid && iEXEND_LDST_VALID && b_next_entry_commit_tag == iEXEND_LDST_COMMIT_TAG)begin
b_next_entry_exe_end <= 1'b1;
end
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_next_exe_commit <= 1'b0;
end
else if(next_commit_reset)begin
b_next_exe_commit <= 1'b0;
end
else begin
if(b_next_entry_valid && b_next_entry_exe_end && !b_next_exe_commit)begin
b_next_exe_commit <= iCOMMIT_VECTOR[b_next_entry_commit_tag];
end
end
end
//Module Output
assign oINFO_FREELIST_REQ = (b_main_state == PL_MAIN_STT_FREELIST) && !iFREE_RESTART;
assign oINFO_DATA_VALID = b_entry_exe_end && !b_next_entry_exe_end;
assign oINFO_DATA = b_entry_exe_data;
endmodule
`default_nettype wire
|
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 3.4
// \ \ Application : 7 Series FPGAs Transceivers Wizard
// / / Filename : srio_gen2_0_multi_gt.v
// /___/ /\
// \ \ / \
// \___\/\___\
//
//
// Module srio_gen2_0_multi_gt (a Multi GT Wrapper)
// Generated by Xilinx 7 Series FPGAs Transceivers Wizard
//
//
// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
`default_nettype wire
`timescale 1ns / 1ps
`define DLY #1
//***************************** Entity Declaration ****************************
(* DowngradeIPIdentifiedWarnings="yes" *)
(* CORE_GENERATION_INFO = "srio_gen2_0_multi_gt,gtwizard_v3_4,{protocol_file=srio_gen2_multi_lane}" *) module srio_gen2_0_multi_gt #
(
// Simulation attributes
parameter WRAPPER_SIM_GTRESET_SPEEDUP = "FALSE", // Set to "TRUE" to speed up sim reset
parameter RX_DFE_KL_CFG2_IN = 32'h301148AC,
parameter PMA_RSV_IN = 32'h00018480
)
(
//_________________________________________________________________________
//_________________________________________________________________________
//GT0 (X0Y0)
//____________________________CHANNEL PORTS________________________________
//------------------------------- CPLL Ports -------------------------------
output gt0_cpllfbclklost_out,
output gt0_cplllock_out,
input gt0_cplllockdetclk_in,
output gt0_cpllrefclklost_out,
input gt0_cpllreset_in,
//------------------------ Channel - Clocking Ports ------------------------
input gt0_gtrefclk0_in,
//-------------------------- Channel - DRP Ports --------------------------
input [8:0] gt0_drpaddr_in,
input gt0_drpclk_in,
input [15:0] gt0_drpdi_in,
output [15:0] gt0_drpdo_out,
input gt0_drpen_in,
output gt0_drprdy_out,
input gt0_drpwe_in,
//------------------------- Digital Monitor Ports --------------------------
output [7:0] gt0_dmonitorout_out,
//----------------------------- Loopback Ports -----------------------------
input [2:0] gt0_loopback_in,
//------------------- RX Initialization and Reset Ports --------------------
input gt0_eyescanreset_in,
input gt0_rxuserrdy_in,
//------------------------ RX Margin Analysis Ports ------------------------
output gt0_eyescandataerror_out,
input gt0_eyescantrigger_in,
//----------------------- Receive Ports - CDR Ports ------------------------
input gt0_rxcdrhold_in,
//----------------- Receive Ports - Clock Correction Ports -----------------
output [1:0] gt0_rxclkcorcnt_out,
//---------------- Receive Ports - FPGA RX Interface Ports -----------------
input gt0_rxusrclk_in,
input gt0_rxusrclk2_in,
//---------------- Receive Ports - FPGA RX interface Ports -----------------
output [31:0] gt0_rxdata_out,
//----------------- Receive Ports - Pattern Checker Ports ------------------
output gt0_rxprbserr_out,
input [2:0] gt0_rxprbssel_in,
//----------------- Receive Ports - Pattern Checker ports ------------------
input gt0_rxprbscntreset_in,
//---------------- Receive Ports - RX 8B/10B Decoder Ports -----------------
output [3:0] gt0_rxdisperr_out,
output [3:0] gt0_rxnotintable_out,
//------------------------- Receive Ports - RX AFE -------------------------
input gt0_gtxrxp_in,
//---------------------- Receive Ports - RX AFE Ports ----------------------
input gt0_gtxrxn_in,
//----------------- Receive Ports - RX Buffer Bypass Ports -----------------
input gt0_rxbufreset_in,
output [2:0] gt0_rxbufstatus_out,
//------------ Receive Ports - RX Byte and Word Alignment Ports ------------
output gt0_rxbyteisaligned_out,
output gt0_rxbyterealign_out,
output gt0_rxcommadet_out,
input gt0_rxmcommaalignen_in,
input gt0_rxpcommaalignen_in,
//---------------- Receive Ports - RX Channel Bonding Ports ----------------
output gt0_rxchanbondseq_out,
input gt0_rxchbonden_in,
input [2:0] gt0_rxchbondlevel_in,
input gt0_rxchbondmaster_in,
output [4:0] gt0_rxchbondo_out,
input gt0_rxchbondslave_in,
//--------------- Receive Ports - RX Channel Bonding Ports ----------------
output gt0_rxchanisaligned_out,
output gt0_rxchanrealign_out,
//------------------- Receive Ports - RX Equalizer Ports -------------------
input gt0_rxdfeagchold_in,
input gt0_rxdfelfhold_in,
input gt0_rxdfelpmreset_in,
output [6:0] gt0_rxmonitorout_out,
input [1:0] gt0_rxmonitorsel_in,
//------------- Receive Ports - RX Fabric Output Control Ports -------------
output gt0_rxoutclk_out,
//----------- Receive Ports - RX Initialization and Reset Ports ------------
input gt0_gtrxreset_in,
input gt0_rxpcsreset_in,
input gt0_rxpmareset_in,
//---------------- Receive Ports - RX Margin Analysis ports ----------------
input gt0_rxlpmen_in,
//--------------- Receive Ports - RX Polarity Control Ports ----------------
input gt0_rxpolarity_in,
//----------------- Receive Ports - RX8B/10B Decoder Ports -----------------
output [3:0] gt0_rxchariscomma_out,
output [3:0] gt0_rxcharisk_out,
//---------------- Receive Ports - Rx Channel Bonding Ports ----------------
input [4:0] gt0_rxchbondi_in,
//------------ Receive Ports -RX Initialization and Reset Ports ------------
output gt0_rxresetdone_out,
//---------------------- TX Configurable Driver Ports ----------------------
input [4:0] gt0_txpostcursor_in,
input [4:0] gt0_txprecursor_in,
//------------------- TX Initialization and Reset Ports --------------------
input gt0_gttxreset_in,
input gt0_txuserrdy_in,
//---------------- Transmit Ports - FPGA TX Interface Ports ----------------
input gt0_txusrclk_in,
input gt0_txusrclk2_in,
//---------------- Transmit Ports - Pattern Generator Ports ----------------
input gt0_txprbsforceerr_in,
//-------------------- Transmit Ports - TX Buffer Ports --------------------
output [1:0] gt0_txbufstatus_out,
//------------- Transmit Ports - TX Configurable Driver Ports --------------
input [3:0] gt0_txdiffctrl_in,
input gt0_txinhibit_in,
//---------------- Transmit Ports - TX Data Path interface -----------------
input [31:0] gt0_txdata_in,
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
output gt0_gtxtxn_out,
output gt0_gtxtxp_out,
//--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
output gt0_txoutclk_out,
output gt0_txoutclkfabric_out,
output gt0_txoutclkpcs_out,
//------------------- Transmit Ports - TX Gearbox Ports --------------------
input [3:0] gt0_txcharisk_in,
//----------- Transmit Ports - TX Initialization and Reset Ports -----------
input gt0_txpcsreset_in,
input gt0_txpmareset_in,
output gt0_txresetdone_out,
//--------------- Transmit Ports - TX Polarity Control Ports ---------------
input gt0_txpolarity_in,
//---------------- Transmit Ports - pattern Generator Ports ----------------
input [2:0] gt0_txprbssel_in,
//_________________________________________________________________________
//_________________________________________________________________________
//GT1 (X0Y1)
//____________________________CHANNEL PORTS________________________________
//------------------------------- CPLL Ports -------------------------------
output gt1_cpllfbclklost_out,
output gt1_cplllock_out,
input gt1_cplllockdetclk_in,
output gt1_cpllrefclklost_out,
input gt1_cpllreset_in,
//------------------------ Channel - Clocking Ports ------------------------
input gt1_gtrefclk0_in,
//-------------------------- Channel - DRP Ports --------------------------
input [8:0] gt1_drpaddr_in,
input gt1_drpclk_in,
input [15:0] gt1_drpdi_in,
output [15:0] gt1_drpdo_out,
input gt1_drpen_in,
output gt1_drprdy_out,
input gt1_drpwe_in,
//------------------------- Digital Monitor Ports --------------------------
output [7:0] gt1_dmonitorout_out,
//----------------------------- Loopback Ports -----------------------------
input [2:0] gt1_loopback_in,
//------------------- RX Initialization and Reset Ports --------------------
input gt1_eyescanreset_in,
input gt1_rxuserrdy_in,
//------------------------ RX Margin Analysis Ports ------------------------
output gt1_eyescandataerror_out,
input gt1_eyescantrigger_in,
//----------------------- Receive Ports - CDR Ports ------------------------
input gt1_rxcdrhold_in,
//----------------- Receive Ports - Clock Correction Ports -----------------
output [1:0] gt1_rxclkcorcnt_out,
//---------------- Receive Ports - FPGA RX Interface Ports -----------------
input gt1_rxusrclk_in,
input gt1_rxusrclk2_in,
//---------------- Receive Ports - FPGA RX interface Ports -----------------
output [31:0] gt1_rxdata_out,
//----------------- Receive Ports - Pattern Checker Ports ------------------
output gt1_rxprbserr_out,
input [2:0] gt1_rxprbssel_in,
//----------------- Receive Ports - Pattern Checker ports ------------------
input gt1_rxprbscntreset_in,
//---------------- Receive Ports - RX 8B/10B Decoder Ports -----------------
output [3:0] gt1_rxdisperr_out,
output [3:0] gt1_rxnotintable_out,
//------------------------- Receive Ports - RX AFE -------------------------
input gt1_gtxrxp_in,
//---------------------- Receive Ports - RX AFE Ports ----------------------
input gt1_gtxrxn_in,
//----------------- Receive Ports - RX Buffer Bypass Ports -----------------
input gt1_rxbufreset_in,
output [2:0] gt1_rxbufstatus_out,
//------------ Receive Ports - RX Byte and Word Alignment Ports ------------
output gt1_rxbyteisaligned_out,
output gt1_rxbyterealign_out,
output gt1_rxcommadet_out,
input gt1_rxmcommaalignen_in,
input gt1_rxpcommaalignen_in,
//---------------- Receive Ports - RX Channel Bonding Ports ----------------
output gt1_rxchanbondseq_out,
input gt1_rxchbonden_in,
input [2:0] gt1_rxchbondlevel_in,
input gt1_rxchbondmaster_in,
output [4:0] gt1_rxchbondo_out,
input gt1_rxchbondslave_in,
//--------------- Receive Ports - RX Channel Bonding Ports ----------------
output gt1_rxchanisaligned_out,
output gt1_rxchanrealign_out,
//------------------- Receive Ports - RX Equalizer Ports -------------------
input gt1_rxdfeagchold_in,
input gt1_rxdfelfhold_in,
input gt1_rxdfelpmreset_in,
output [6:0] gt1_rxmonitorout_out,
input [1:0] gt1_rxmonitorsel_in,
//------------- Receive Ports - RX Fabric Output Control Ports -------------
output gt1_rxoutclk_out,
//----------- Receive Ports - RX Initialization and Reset Ports ------------
input gt1_gtrxreset_in,
input gt1_rxpcsreset_in,
input gt1_rxpmareset_in,
//---------------- Receive Ports - RX Margin Analysis ports ----------------
input gt1_rxlpmen_in,
//--------------- Receive Ports - RX Polarity Control Ports ----------------
input gt1_rxpolarity_in,
//----------------- Receive Ports - RX8B/10B Decoder Ports -----------------
output [3:0] gt1_rxchariscomma_out,
output [3:0] gt1_rxcharisk_out,
//---------------- Receive Ports - Rx Channel Bonding Ports ----------------
input [4:0] gt1_rxchbondi_in,
//------------ Receive Ports -RX Initialization and Reset Ports ------------
output gt1_rxresetdone_out,
//---------------------- TX Configurable Driver Ports ----------------------
input [4:0] gt1_txpostcursor_in,
input [4:0] gt1_txprecursor_in,
//------------------- TX Initialization and Reset Ports --------------------
input gt1_gttxreset_in,
input gt1_txuserrdy_in,
//---------------- Transmit Ports - FPGA TX Interface Ports ----------------
input gt1_txusrclk_in,
input gt1_txusrclk2_in,
//---------------- Transmit Ports - Pattern Generator Ports ----------------
input gt1_txprbsforceerr_in,
//-------------------- Transmit Ports - TX Buffer Ports --------------------
output [1:0] gt1_txbufstatus_out,
//------------- Transmit Ports - TX Configurable Driver Ports --------------
input [3:0] gt1_txdiffctrl_in,
input gt1_txinhibit_in,
//---------------- Transmit Ports - TX Data Path interface -----------------
input [31:0] gt1_txdata_in,
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
output gt1_gtxtxn_out,
output gt1_gtxtxp_out,
//--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
output gt1_txoutclk_out,
output gt1_txoutclkfabric_out,
output gt1_txoutclkpcs_out,
//------------------- Transmit Ports - TX Gearbox Ports --------------------
input [3:0] gt1_txcharisk_in,
//----------- Transmit Ports - TX Initialization and Reset Ports -----------
input gt1_txpcsreset_in,
input gt1_txpmareset_in,
output gt1_txresetdone_out,
//--------------- Transmit Ports - TX Polarity Control Ports ---------------
input gt1_txpolarity_in,
//---------------- Transmit Ports - pattern Generator Ports ----------------
input [2:0] gt1_txprbssel_in,
//____________________________COMMON PORTS________________________________
input gt0_qplloutclk_in,
input gt0_qplloutrefclk_in
);
//***************************** Parameter Declarations ************************
localparam QPLL_FBDIV_TOP = 40;
localparam QPLL_FBDIV_IN = (QPLL_FBDIV_TOP == 16) ? 10'b0000100000 :
(QPLL_FBDIV_TOP == 20) ? 10'b0000110000 :
(QPLL_FBDIV_TOP == 32) ? 10'b0001100000 :
(QPLL_FBDIV_TOP == 40) ? 10'b0010000000 :
(QPLL_FBDIV_TOP == 64) ? 10'b0011100000 :
(QPLL_FBDIV_TOP == 66) ? 10'b0101000000 :
(QPLL_FBDIV_TOP == 80) ? 10'b0100100000 :
(QPLL_FBDIV_TOP == 100) ? 10'b0101110000 : 10'b0000000000;
localparam QPLL_FBDIV_RATIO = (QPLL_FBDIV_TOP == 16) ? 1'b1 :
(QPLL_FBDIV_TOP == 20) ? 1'b1 :
(QPLL_FBDIV_TOP == 32) ? 1'b1 :
(QPLL_FBDIV_TOP == 40) ? 1'b1 :
(QPLL_FBDIV_TOP == 64) ? 1'b1 :
(QPLL_FBDIV_TOP == 66) ? 1'b0 :
(QPLL_FBDIV_TOP == 80) ? 1'b1 :
(QPLL_FBDIV_TOP == 100) ? 1'b1 : 1'b1;
//***************************** Wire Declarations *****************************
// ground and vcc signals
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [63:0] tied_to_vcc_vec_i;
wire gt0_qpllclk_i;
wire gt0_qpllrefclk_i;
wire gt1_qpllclk_i;
wire gt1_qpllrefclk_i;
//********************************* Main Body of Code**************************
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
assign gt0_qpllclk_i = gt0_qplloutclk_in;
assign gt0_qpllrefclk_i = gt0_qplloutrefclk_in;
assign gt1_qpllclk_i = gt0_qplloutclk_in;
assign gt1_qpllrefclk_i = gt0_qplloutrefclk_in;
//------------------------- GT Instances -------------------------------
//_________________________________________________________________________
//_________________________________________________________________________
//GT0 (X0Y0)
//_________________________________________________________________________
srio_gen2_0_GT #
(
// Simulation attributes
.GT_SIM_GTRESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP),
.RX_DFE_KL_CFG2_IN (RX_DFE_KL_CFG2_IN),
.PCS_RSVD_ATTR_IN (48'h000000000000),
.PMA_RSV_IN (PMA_RSV_IN)
)
gt0_srio_gen2_0_i
(
//------------------------------- CPLL Ports -------------------------------
.cpllfbclklost_out (gt0_cpllfbclklost_out),
.cplllock_out (gt0_cplllock_out),
.cplllockdetclk_in (gt0_cplllockdetclk_in),
.cpllrefclklost_out (gt0_cpllrefclklost_out),
.cpllreset_in (gt0_cpllreset_in),
//------------------------ Channel - Clocking Ports ------------------------
.gtrefclk0_in (gt0_gtrefclk0_in),
//-------------------------- Channel - DRP Ports --------------------------
.drpaddr_in (gt0_drpaddr_in),
.drpclk_in (gt0_drpclk_in),
.drpdi_in (gt0_drpdi_in),
.drpdo_out (gt0_drpdo_out),
.drpen_in (gt0_drpen_in),
.drprdy_out (gt0_drprdy_out),
.drpwe_in (gt0_drpwe_in),
//----------------------------- Clocking Ports -----------------------------
.qpllclk_in (gt0_qpllclk_i),
.qpllrefclk_in (gt0_qpllrefclk_i),
//------------------------- Digital Monitor Ports --------------------------
.dmonitorout_out (gt0_dmonitorout_out),
//----------------------------- Loopback Ports -----------------------------
.loopback_in (gt0_loopback_in),
//------------------- RX Initialization and Reset Ports --------------------
.eyescanreset_in (gt0_eyescanreset_in),
.rxuserrdy_in (gt0_rxuserrdy_in),
//------------------------ RX Margin Analysis Ports ------------------------
.eyescandataerror_out (gt0_eyescandataerror_out),
.eyescantrigger_in (gt0_eyescantrigger_in),
//----------------------- Receive Ports - CDR Ports ------------------------
.rxcdrhold_in (gt0_rxcdrhold_in),
//----------------- Receive Ports - Clock Correction Ports -----------------
.rxclkcorcnt_out (gt0_rxclkcorcnt_out),
//---------------- Receive Ports - FPGA RX Interface Ports -----------------
.rxusrclk_in (gt0_rxusrclk_in),
.rxusrclk2_in (gt0_rxusrclk2_in),
//---------------- Receive Ports - FPGA RX interface Ports -----------------
.rxdata_out (gt0_rxdata_out),
//----------------- Receive Ports - Pattern Checker Ports ------------------
.rxprbserr_out (gt0_rxprbserr_out),
.rxprbssel_in (gt0_rxprbssel_in),
//----------------- Receive Ports - Pattern Checker ports ------------------
.rxprbscntreset_in (gt0_rxprbscntreset_in),
//---------------- Receive Ports - RX 8B/10B Decoder Ports -----------------
.rxdisperr_out (gt0_rxdisperr_out),
.rxnotintable_out (gt0_rxnotintable_out),
//------------------------- Receive Ports - RX AFE -------------------------
.gtxrxp_in (gt0_gtxrxp_in),
//---------------------- Receive Ports - RX AFE Ports ----------------------
.gtxrxn_in (gt0_gtxrxn_in),
//----------------- Receive Ports - RX Buffer Bypass Ports -----------------
.rxbufreset_in (gt0_rxbufreset_in),
.rxbufstatus_out (gt0_rxbufstatus_out),
//------------ Receive Ports - RX Byte and Word Alignment Ports ------------
.rxbyteisaligned_out (gt0_rxbyteisaligned_out),
.rxbyterealign_out (gt0_rxbyterealign_out),
.rxcommadet_out (gt0_rxcommadet_out),
.rxmcommaalignen_in (gt0_rxmcommaalignen_in),
.rxpcommaalignen_in (gt0_rxpcommaalignen_in),
//---------------- Receive Ports - RX Channel Bonding Ports ----------------
.rxchanbondseq_out (gt0_rxchanbondseq_out),
.rxchbonden_in (gt0_rxchbonden_in),
.rxchbondlevel_in (gt0_rxchbondlevel_in),
.rxchbondmaster_in (gt0_rxchbondmaster_in),
.rxchbondo_out (gt0_rxchbondo_out),
.rxchbondslave_in (gt0_rxchbondslave_in),
//--------------- Receive Ports - RX Channel Bonding Ports ----------------
.rxchanisaligned_out (gt0_rxchanisaligned_out),
.rxchanrealign_out (gt0_rxchanrealign_out),
//------------------- Receive Ports - RX Equalizer Ports -------------------
.rxdfeagchold_in (gt0_rxdfeagchold_in),
.rxdfelfhold_in (gt0_rxdfelfhold_in),
.rxdfelpmreset_in (gt0_rxdfelpmreset_in),
.rxmonitorout_out (gt0_rxmonitorout_out),
.rxmonitorsel_in (gt0_rxmonitorsel_in),
//------------- Receive Ports - RX Fabric Output Control Ports -------------
.rxoutclk_out (gt0_rxoutclk_out),
//----------- Receive Ports - RX Initialization and Reset Ports ------------
.gtrxreset_in (gt0_gtrxreset_in),
.rxpcsreset_in (gt0_rxpcsreset_in),
.rxpmareset_in (gt0_rxpmareset_in),
//---------------- Receive Ports - RX Margin Analysis ports ----------------
.rxlpmen_in (gt0_rxlpmen_in),
//--------------- Receive Ports - RX Polarity Control Ports ----------------
.rxpolarity_in (gt0_rxpolarity_in),
//----------------- Receive Ports - RX8B/10B Decoder Ports -----------------
.rxchariscomma_out (gt0_rxchariscomma_out),
.rxcharisk_out (gt0_rxcharisk_out),
//---------------- Receive Ports - Rx Channel Bonding Ports ----------------
.rxchbondi_in (gt0_rxchbondi_in),
//------------ Receive Ports -RX Initialization and Reset Ports ------------
.rxresetdone_out (gt0_rxresetdone_out),
//---------------------- TX Configurable Driver Ports ----------------------
.txpostcursor_in (gt0_txpostcursor_in),
.txprecursor_in (gt0_txprecursor_in),
//------------------- TX Initialization and Reset Ports --------------------
.gttxreset_in (gt0_gttxreset_in),
.txuserrdy_in (gt0_txuserrdy_in),
//---------------- Transmit Ports - FPGA TX Interface Ports ----------------
.txusrclk_in (gt0_txusrclk_in),
.txusrclk2_in (gt0_txusrclk2_in),
//---------------- Transmit Ports - Pattern Generator Ports ----------------
.txprbsforceerr_in (gt0_txprbsforceerr_in),
//-------------------- Transmit Ports - TX Buffer Ports --------------------
.txbufstatus_out (gt0_txbufstatus_out),
//------------- Transmit Ports - TX Configurable Driver Ports --------------
.txdiffctrl_in (gt0_txdiffctrl_in),
.txinhibit_in (gt0_txinhibit_in),
//---------------- Transmit Ports - TX Data Path interface -----------------
.txdata_in (gt0_txdata_in),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.gtxtxn_out (gt0_gtxtxn_out),
.gtxtxp_out (gt0_gtxtxp_out),
//--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
.txoutclk_out (gt0_txoutclk_out),
.txoutclkfabric_out (gt0_txoutclkfabric_out),
.txoutclkpcs_out (gt0_txoutclkpcs_out),
//------------------- Transmit Ports - TX Gearbox Ports --------------------
.txcharisk_in (gt0_txcharisk_in),
//----------- Transmit Ports - TX Initialization and Reset Ports -----------
.txpcsreset_in (gt0_txpcsreset_in),
.txpmareset_in (gt0_txpmareset_in),
.txresetdone_out (gt0_txresetdone_out),
//--------------- Transmit Ports - TX Polarity Control Ports ---------------
.txpolarity_in (gt0_txpolarity_in),
//---------------- Transmit Ports - pattern Generator Ports ----------------
.txprbssel_in (gt0_txprbssel_in)
);
//_________________________________________________________________________
//_________________________________________________________________________
//GT1 (X0Y1)
//_________________________________________________________________________
srio_gen2_0_GT #
(
// Simulation attributes
.GT_SIM_GTRESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP),
.RX_DFE_KL_CFG2_IN (RX_DFE_KL_CFG2_IN),
.PCS_RSVD_ATTR_IN (48'h000000000000),
.PMA_RSV_IN (PMA_RSV_IN)
)
gt1_srio_gen2_0_i
(
//------------------------------- CPLL Ports -------------------------------
.cpllfbclklost_out (gt1_cpllfbclklost_out),
.cplllock_out (gt1_cplllock_out),
.cplllockdetclk_in (gt1_cplllockdetclk_in),
.cpllrefclklost_out (gt1_cpllrefclklost_out),
.cpllreset_in (gt1_cpllreset_in),
//------------------------ Channel - Clocking Ports ------------------------
.gtrefclk0_in (gt1_gtrefclk0_in),
//-------------------------- Channel - DRP Ports --------------------------
.drpaddr_in (gt1_drpaddr_in),
.drpclk_in (gt1_drpclk_in),
.drpdi_in (gt1_drpdi_in),
.drpdo_out (gt1_drpdo_out),
.drpen_in (gt1_drpen_in),
.drprdy_out (gt1_drprdy_out),
.drpwe_in (gt1_drpwe_in),
//----------------------------- Clocking Ports -----------------------------
.qpllclk_in (gt1_qpllclk_i),
.qpllrefclk_in (gt1_qpllrefclk_i),
//------------------------- Digital Monitor Ports --------------------------
.dmonitorout_out (gt1_dmonitorout_out),
//----------------------------- Loopback Ports -----------------------------
.loopback_in (gt1_loopback_in),
//------------------- RX Initialization and Reset Ports --------------------
.eyescanreset_in (gt1_eyescanreset_in),
.rxuserrdy_in (gt1_rxuserrdy_in),
//------------------------ RX Margin Analysis Ports ------------------------
.eyescandataerror_out (gt1_eyescandataerror_out),
.eyescantrigger_in (gt1_eyescantrigger_in),
//----------------------- Receive Ports - CDR Ports ------------------------
.rxcdrhold_in (gt1_rxcdrhold_in),
//----------------- Receive Ports - Clock Correction Ports -----------------
.rxclkcorcnt_out (gt1_rxclkcorcnt_out),
//---------------- Receive Ports - FPGA RX Interface Ports -----------------
.rxusrclk_in (gt1_rxusrclk_in),
.rxusrclk2_in (gt1_rxusrclk2_in),
//---------------- Receive Ports - FPGA RX interface Ports -----------------
.rxdata_out (gt1_rxdata_out),
//----------------- Receive Ports - Pattern Checker Ports ------------------
.rxprbserr_out (gt1_rxprbserr_out),
.rxprbssel_in (gt1_rxprbssel_in),
//----------------- Receive Ports - Pattern Checker ports ------------------
.rxprbscntreset_in (gt1_rxprbscntreset_in),
//---------------- Receive Ports - RX 8B/10B Decoder Ports -----------------
.rxdisperr_out (gt1_rxdisperr_out),
.rxnotintable_out (gt1_rxnotintable_out),
//------------------------- Receive Ports - RX AFE -------------------------
.gtxrxp_in (gt1_gtxrxp_in),
//---------------------- Receive Ports - RX AFE Ports ----------------------
.gtxrxn_in (gt1_gtxrxn_in),
//----------------- Receive Ports - RX Buffer Bypass Ports -----------------
.rxbufreset_in (gt1_rxbufreset_in),
.rxbufstatus_out (gt1_rxbufstatus_out),
//------------ Receive Ports - RX Byte and Word Alignment Ports ------------
.rxbyteisaligned_out (gt1_rxbyteisaligned_out),
.rxbyterealign_out (gt1_rxbyterealign_out),
.rxcommadet_out (gt1_rxcommadet_out),
.rxmcommaalignen_in (gt1_rxmcommaalignen_in),
.rxpcommaalignen_in (gt1_rxpcommaalignen_in),
//---------------- Receive Ports - RX Channel Bonding Ports ----------------
.rxchanbondseq_out (gt1_rxchanbondseq_out),
.rxchbonden_in (gt1_rxchbonden_in),
.rxchbondlevel_in (gt1_rxchbondlevel_in),
.rxchbondmaster_in (gt1_rxchbondmaster_in),
.rxchbondo_out (gt1_rxchbondo_out),
.rxchbondslave_in (gt1_rxchbondslave_in),
//--------------- Receive Ports - RX Channel Bonding Ports ----------------
.rxchanisaligned_out (gt1_rxchanisaligned_out),
.rxchanrealign_out (gt1_rxchanrealign_out),
//------------------- Receive Ports - RX Equalizer Ports -------------------
.rxdfeagchold_in (gt1_rxdfeagchold_in),
.rxdfelfhold_in (gt1_rxdfelfhold_in),
.rxdfelpmreset_in (gt1_rxdfelpmreset_in),
.rxmonitorout_out (gt1_rxmonitorout_out),
.rxmonitorsel_in (gt1_rxmonitorsel_in),
//------------- Receive Ports - RX Fabric Output Control Ports -------------
.rxoutclk_out (gt1_rxoutclk_out),
//----------- Receive Ports - RX Initialization and Reset Ports ------------
.gtrxreset_in (gt1_gtrxreset_in),
.rxpcsreset_in (gt1_rxpcsreset_in),
.rxpmareset_in (gt1_rxpmareset_in),
//---------------- Receive Ports - RX Margin Analysis ports ----------------
.rxlpmen_in (gt1_rxlpmen_in),
//--------------- Receive Ports - RX Polarity Control Ports ----------------
.rxpolarity_in (gt1_rxpolarity_in),
//----------------- Receive Ports - RX8B/10B Decoder Ports -----------------
.rxchariscomma_out (gt1_rxchariscomma_out),
.rxcharisk_out (gt1_rxcharisk_out),
//---------------- Receive Ports - Rx Channel Bonding Ports ----------------
.rxchbondi_in (gt1_rxchbondi_in),
//------------ Receive Ports -RX Initialization and Reset Ports ------------
.rxresetdone_out (gt1_rxresetdone_out),
//---------------------- TX Configurable Driver Ports ----------------------
.txpostcursor_in (gt1_txpostcursor_in),
.txprecursor_in (gt1_txprecursor_in),
//------------------- TX Initialization and Reset Ports --------------------
.gttxreset_in (gt1_gttxreset_in),
.txuserrdy_in (gt1_txuserrdy_in),
//---------------- Transmit Ports - FPGA TX Interface Ports ----------------
.txusrclk_in (gt1_txusrclk_in),
.txusrclk2_in (gt1_txusrclk2_in),
//---------------- Transmit Ports - Pattern Generator Ports ----------------
.txprbsforceerr_in (gt1_txprbsforceerr_in),
//-------------------- Transmit Ports - TX Buffer Ports --------------------
.txbufstatus_out (gt1_txbufstatus_out),
//------------- Transmit Ports - TX Configurable Driver Ports --------------
.txdiffctrl_in (gt1_txdiffctrl_in),
.txinhibit_in (gt1_txinhibit_in),
//---------------- Transmit Ports - TX Data Path interface -----------------
.txdata_in (gt1_txdata_in),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.gtxtxn_out (gt1_gtxtxn_out),
.gtxtxp_out (gt1_gtxtxp_out),
//--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
.txoutclk_out (gt1_txoutclk_out),
.txoutclkfabric_out (gt1_txoutclkfabric_out),
.txoutclkpcs_out (gt1_txoutclkpcs_out),
//------------------- Transmit Ports - TX Gearbox Ports --------------------
.txcharisk_in (gt1_txcharisk_in),
//----------- Transmit Ports - TX Initialization and Reset Ports -----------
.txpcsreset_in (gt1_txpcsreset_in),
.txpmareset_in (gt1_txpmareset_in),
.txresetdone_out (gt1_txresetdone_out),
//--------------- Transmit Ports - TX Polarity Control Ports ---------------
.txpolarity_in (gt1_txpolarity_in),
//---------------- Transmit Ports - pattern Generator Ports ----------------
.txprbssel_in (gt1_txprbssel_in)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2_BEHAVIORAL_V
`define SKY130_FD_SC_LS__NAND2_BEHAVIORAL_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nand2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2_BEHAVIORAL_V |
module test_out (
input clk,
input rst,
input enable,
output reg busy,
output reg error,
input ready,
output reg activate,
input [23:0] size,
input [31:0] data,
output reg strobe,
output reg [23:0] total_count
);
reg [31:0] test_value;
reg [23:0] count;
always @ (posedge clk) begin
if (rst) begin
activate <= 0;
count <= 0;
test_value <= 32'h0;
error <= 0;
busy <= 0;
total_count <= 0;
strobe <= 0;
end
else begin
busy <= 0;
strobe <= 0;
//The user is not asking to check anything
if (!enable) begin
//activate <= 0;
//count <= 0;
test_value <= 32'h0;
error <= 0;
total_count <= 0;
end
//Looking for total count
//busy <= 1;
if (ready && !activate) begin
count <= 0;
activate <= 1;
end
else if (activate) begin
busy <= 1;
if (count < size) begin
strobe <= 1;
total_count <= total_count + 1;
count <= count + 1;
if ((data != test_value) && enable) begin
error <= 1;
end
end
else begin
activate <= 0;
end
end
if (strobe) begin
test_value <= test_value + 1;
end
end
end
endmodule
|
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
// On Mon Nov 5 13:19:54 EST 2012
//
//
// Ports:
// Name I/O size props
// RDY_ledDrive O 1 const
// led O 5
// CLK I 1 clock
// RST_N I 1 reset
// ledDrive_i I 5 reg
// EN_ledDrive I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkLedN210(CLK,
RST_N,
ledDrive_i,
EN_ledDrive,
RDY_ledDrive,
led);
input CLK;
input RST_N;
// action method ledDrive
input [4 : 0] ledDrive_i;
input EN_ledDrive;
output RDY_ledDrive;
// value method led
output [4 : 0] led;
// signals for module outputs
wire [4 : 0] led;
wire RDY_ledDrive;
// register doInit
reg doInit;
wire doInit$D_IN, doInit$EN;
// register freeCnt
reg [31 : 0] freeCnt;
wire [31 : 0] freeCnt$D_IN;
wire freeCnt$EN;
// register ledReg
reg [4 : 0] ledReg;
wire [4 : 0] ledReg$D_IN;
wire ledReg$EN;
// remaining internal signals
reg [4 : 0] CASE_freeCnt_BITS_25_TO_23_3_0_IF_freeCnt_BIT__ETC__q1;
wire [4 : 0] x__h621, x__h622;
// action method ledDrive
assign RDY_ledDrive = 1'd1 ;
// value method led
assign led =
doInit ?
CASE_freeCnt_BITS_25_TO_23_3_0_IF_freeCnt_BIT__ETC__q1 :
~x__h621 ;
// register doInit
assign doInit$D_IN = 1'd0 ;
assign doInit$EN = freeCnt > 32'h08000000 ;
// register freeCnt
assign freeCnt$D_IN = freeCnt + 32'd1 ;
assign freeCnt$EN = 1'd1 ;
// register ledReg
assign ledReg$D_IN = ledDrive_i ;
assign ledReg$EN = EN_ledDrive ;
// remaining internal signals
assign x__h621 = x__h622 | ledReg ;
assign x__h622 = freeCnt[23] ? 5'h01 : 5'h0 ;
always@(freeCnt)
begin
case (freeCnt[25:23])
3'd0, 3'd1, 3'd2, 3'd6, 3'd7:
CASE_freeCnt_BITS_25_TO_23_3_0_IF_freeCnt_BIT__ETC__q1 =
freeCnt[21] ? 5'd3 : 5'd31;
3'd3: CASE_freeCnt_BITS_25_TO_23_3_0_IF_freeCnt_BIT__ETC__q1 = 5'd27;
3'd4: CASE_freeCnt_BITS_25_TO_23_3_0_IF_freeCnt_BIT__ETC__q1 = 5'd19;
3'd5: CASE_freeCnt_BITS_25_TO_23_3_0_IF_freeCnt_BIT__ETC__q1 = 5'd3;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
doInit <= `BSV_ASSIGNMENT_DELAY 1'd1;
freeCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
ledReg <= `BSV_ASSIGNMENT_DELAY 5'd0;
end
else
begin
if (doInit$EN) doInit <= `BSV_ASSIGNMENT_DELAY doInit$D_IN;
if (freeCnt$EN) freeCnt <= `BSV_ASSIGNMENT_DELAY freeCnt$D_IN;
if (ledReg$EN) ledReg <= `BSV_ASSIGNMENT_DELAY ledReg$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
doInit = 1'h0;
freeCnt = 32'hAAAAAAAA;
ledReg = 5'h0A;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkLedN210
|
/**************************************************************\
*
* WS2812 LED controll module
*
* Parameters:
* CYCLES_SHORT clk cycles for the 400 ns duration
* CYCLES_LONG clk cycles for the 800 ns duration
* CYCLES_RET clk cycles for the wait time after
* clocking the bits out
*
* inputs:
* clk clock signal
* resetn reset signal (low active)
* bitstream_available in idle state trigger clocking
* out the bitstream supplied
* bitstream the bitstream to be clocked out
*
* outputs:
* bitstream_read bitstream has been read and may be updated
* ws2811_data the actual output to control the ws2811 LEDs
* debug_info
*
\**************************************************************/
module ws2812b_out_module (
input clk,
input resetn,
input bitstream_available,
input [23:0] bitstream,
output reg bitstream_read,
output reg ws2812b_data,
output reg [3:0] debug_info
);
parameter CYCLES_SHORT = 3; // ~0,44 us @ 9 MHz
parameter CYCLES_LONG = 5; // ~0,66 us @ 9 MHz
parameter CYCLES_RET = 450; // 50,0 us @ 9 MHz
localparam CYCLES_WIDTH = $clog2(CYCLES_RET > CYCLES_LONG ? CYCLES_RET
: CYCLES_LONG);
// keep an eye on the length of bitnum
reg [4:0] bitnum = 0; // 0 .. 23
reg [CYCLES_WIDTH-1:0] counter = 0; // 0 .. CYCLES_RET
reg [23:0] bitstream_int; // internal copy of the txed LED data
reg [0:0] idle = 0;
always @(posedge clk) begin
if (!resetn) begin
// reset state
counter <= 0;
bitstream_read <= 0;
bitnum <= 0;
end else begin
bitstream_read <= 0; // default value
if (counter != 0) begin
// wait state: consume the desired time
counter <= counter - 1;
end else begin
if (!bitnum && !ws2812b_data) begin
if (bitstream_available) begin
// communicate to "caller"
bitstream_read <= 1; // state bitstream to be read for this cycle
bitstream_int <= bitstream; // get internal copy of bitstream
// start output
ws2812b_data <= 1;
bitnum <= 24;
counter <= bitstream[23] ? CYCLES_LONG : CYCLES_SHORT;
idle <= 0;
end else begin
// no new bitstream available -> trigger output of ws2812b LEDs
ws2812b_data <= 0;
counter <= CYCLES_RET; // cheaper logic
// counter <= idle ? 0 : CYCLES_RET; // immidiate reaction to bitstream available
idle <= 1;
end
end else if (bitnum) begin
// output the remainder of bitstream
if (!ws2812b_data) begin
ws2812b_data <= 1;
counter <= bitstream_int[23] ? CYCLES_LONG : CYCLES_SHORT;
end else begin
ws2812b_data <= 0;
counter <= (bitstream_int[23]) ? CYCLES_SHORT : CYCLES_LONG;
bitstream_int <= {bitstream_int[22:0], bitstream_int[23]};
bitnum <= bitnum - 1;
end
end
end
end
end
// assign debug_info = {bitstream_read, bitstream_available, resetn, clk};
assign debug_info = {ws2812b_data, bitstream_read, bitstream_available, clk};
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: HORIE Tetsuya
//
// Create Date: 2015/11/26 07:34:43
// Design Name:
// Module Name: TD4
// Project Name: TD4-GateLevel
// Target Devices: Nexys4 DDR
// Tool Versions:
// Description:
//
// Dependencies: Clocks.v
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
// Copyright © 2015 HORIE Tetsuya.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//////////////////////////////////////////////////////////////////////////////////
/**
* TD4のトップレベル・モジュールです。
*
* @param CLK100MHZ クロック信号
* @param CPU_RESETn リセット信号(負論理)
* @param LED LED
*/
module TD4(input CLK100MHZ,
input CPU_RESETn,
output [1:0] LED);
/*
* リセット信号関係
*/
wire reset; // リセット信号
not(reset, CPU_RESETn); // 入力は負論理で扱いにくいので、正論理に変換
/*
* クロック信号関係
*/
wire clk1Hz; // 1Hzのクロック信号線
wire clk10Hz; // 10Hzのクロック信号線
Clocks clks(CLK100MHZ, reset, clk1Hz, clk10Hz);
assign LED[0] = clk1Hz;
assign LED[1] = clk10Hz;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXTP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__EDFXTP_PP_SYMBOL_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__edfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXTP_PP_SYMBOL_V
|
// megafunction wizard: %ALTMULT_COMPLEX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altmult_complex
// ============================================================
// File Name: complex_mult.v
// Megafunction Name(s):
// altmult_complex
//
// Simulation Library Files(s):
// altera_lnsim
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altmult_complex CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" IMPLEMENTATION_STYLE="AUTO" PIPELINE=3 REPRESENTATION_A="SIGNED" REPRESENTATION_B="SIGNED" WIDTH_A=32 WIDTH_B=10 WIDTH_RESULT=42 aclr clock dataa_imag dataa_real datab_imag datab_real result_imag result_real
//VERSION_BEGIN 13.1 cbx_alt_ded_mult_y 2013:10:23:18:05:48:SJ cbx_altera_mult_add 2013:10:23:18:05:48:SJ cbx_altera_mult_add_rtl 2013:10:23:18:05:48:SJ cbx_altmult_add 2013:10:23:18:05:48:SJ cbx_altmult_complex 2013:10:23:18:05:48:SJ cbx_arriav 2013:10:23:18:05:48:SJ cbx_cycloneii 2013:10:23:18:05:48:SJ cbx_lpm_add_sub 2013:10:23:18:05:48:SJ cbx_lpm_compare 2013:10:23:18:05:48:SJ cbx_lpm_mult 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_padd 2013:10:23:18:05:48:SJ cbx_parallel_add 2013:10:23:18:05:48:SJ cbx_stratix 2013:10:23:18:05:48:SJ cbx_stratixii 2013:10:23:18:05:48:SJ cbx_stratixv 2013:10:23:18:05:48:SJ cbx_util_mgl 2013:10:23:18:05:48:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altmult_add CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" INPUT_ACLR_A0="ACLR0" INPUT_ACLR_A1="ACLR0" INPUT_ACLR_B0="ACLR0" INPUT_ACLR_B1="ACLR0" INPUT_REGISTER_A0="CLOCK0" INPUT_REGISTER_A1="CLOCK0" INPUT_REGISTER_B0="CLOCK0" INPUT_REGISTER_B1="CLOCK0" MULTIPLIER1_DIRECTION="SUB" MULTIPLIER_ACLR0="ACLR0" MULTIPLIER_ACLR1="ACLR0" MULTIPLIER_REGISTER0="CLOCK0" MULTIPLIER_REGISTER1="CLOCK0" NUMBER_OF_MULTIPLIERS=2 OUTPUT_ACLR="ACLR0" OUTPUT_REGISTER="CLOCK0" port_addnsub1="PORT_UNUSED" port_signa="PORT_UNUSED" port_signb="PORT_UNUSED" REPRESENTATION_A="SIGNED" REPRESENTATION_B="SIGNED" WIDTH_A=32 WIDTH_B=10 WIDTH_C=22 WIDTH_RESULT=42 aclr0 clock0 dataa datab ena0 result
//VERSION_BEGIN 13.1 cbx_alt_ded_mult_y 2013:10:23:18:05:48:SJ cbx_altera_mult_add 2013:10:23:18:05:48:SJ cbx_altera_mult_add_rtl 2013:10:23:18:05:48:SJ cbx_altmult_add 2013:10:23:18:05:48:SJ cbx_cycloneii 2013:10:23:18:05:48:SJ cbx_lpm_add_sub 2013:10:23:18:05:48:SJ cbx_lpm_mult 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_padd 2013:10:23:18:05:48:SJ cbx_parallel_add 2013:10:23:18:05:48:SJ cbx_stratix 2013:10:23:18:05:48:SJ cbx_stratixii 2013:10:23:18:05:48:SJ cbx_util_mgl 2013:10:23:18:05:48:SJ VERSION_END
//altera_mult_add ACCUM_DIRECTION="ADD" ACCUM_SLOAD_ACLR="ACLR0" ACCUM_SLOAD_PIPELINE_ACLR="ACLR0" ACCUM_SLOAD_PIPELINE_REGISTER="CLOCK0" ACCUM_SLOAD_REGISTER="CLOCK0" ACCUMULATOR="NO" ADDER1_ROUNDING="NO" ADDER3_ROUNDING="NO" ADDNSUB1_ROUND_ACLR="ACLR0" ADDNSUB1_ROUND_PIPELINE_ACLR="ACLR0" ADDNSUB1_ROUND_PIPELINE_REGISTER="CLOCK0" ADDNSUB1_ROUND_REGISTER="CLOCK0" ADDNSUB3_ROUND_ACLR="ACLR0" ADDNSUB3_ROUND_PIPELINE_ACLR="ACLR0" ADDNSUB3_ROUND_PIPELINE_REGISTER="CLOCK0" ADDNSUB3_ROUND_REGISTER="CLOCK0" ADDNSUB_MULTIPLIER_ACLR1="ACLR0" ADDNSUB_MULTIPLIER_ACLR3="ACLR0" ADDNSUB_MULTIPLIER_PIPELINE_ACLR1="ACLR0" ADDNSUB_MULTIPLIER_PIPELINE_ACLR3="ACLR0" ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER3="CLOCK0" CBX_AUTO_BLACKBOX="ALL" CHAINOUT_ACLR="ACLR0" CHAINOUT_ADDER="NO" CHAINOUT_REGISTER="CLOCK0" CHAINOUT_ROUND_ACLR="ACLR0" CHAINOUT_ROUND_OUTPUT_ACLR="ACLR0" CHAINOUT_ROUND_OUTPUT_REGISTER="CLOCK0" CHAINOUT_ROUND_PIPELINE_ACLR="ACLR0" CHAINOUT_ROUND_PIPELINE_REGISTER="CLOCK0" CHAINOUT_ROUND_REGISTER="CLOCK0" CHAINOUT_ROUNDING="NO" CHAINOUT_SATURATE_ACLR="ACLR0" CHAINOUT_SATURATE_OUTPUT_ACLR="ACLR0" CHAINOUT_SATURATE_OUTPUT_REGISTER="CLOCK0" CHAINOUT_SATURATE_PIPELINE_ACLR="ACLR0" CHAINOUT_SATURATE_PIPELINE_REGISTER="CLOCK0" CHAINOUT_SATURATE_REGISTER="CLOCK0" CHAINOUT_SATURATION="NO" COEF0_0=0 COEF0_1=0 COEF0_2=0 COEF0_3=0 COEF0_4=0 COEF0_5=0 COEF0_6=0 COEF0_7=0 COEF1_0=0 COEF1_1=0 COEF1_2=0 COEF1_3=0 COEF1_4=0 COEF1_5=0 COEF1_6=0 COEF1_7=0 COEF2_0=0 COEF2_1=0 COEF2_2=0 COEF2_3=0 COEF2_4=0 COEF2_5=0 COEF2_6=0 COEF2_7=0 COEF3_0=0 COEF3_1=0 COEF3_2=0 COEF3_3=0 COEF3_4=0 COEF3_5=0 COEF3_6=0 COEF3_7=0 COEFSEL0_ACLR="ACLR0" COEFSEL0_REGISTER="CLOCK0" COEFSEL1_ACLR="ACLR0" COEFSEL1_REGISTER="CLOCK0" COEFSEL2_ACLR="ACLR0" COEFSEL2_REGISTER="CLOCK0" COEFSEL3_ACLR="ACLR0" COEFSEL3_REGISTER="CLOCK0" DEDICATED_MULTIPLIER_CIRCUITRY="AUTO" DEVICE_FAMILY="Cyclone V" DOUBLE_ACCUM="NO" DSP_BLOCK_BALANCING="Auto" EXTRA_LATENCY=0 INPUT_ACLR_A0="ACLR0" INPUT_ACLR_A1="ACLR0" INPUT_ACLR_A2="ACLR0" INPUT_ACLR_A3="ACLR0" INPUT_ACLR_B0="ACLR0" INPUT_ACLR_B1="ACLR0" INPUT_ACLR_B2="ACLR0" INPUT_ACLR_B3="ACLR0" INPUT_ACLR_C0="ACLR0" INPUT_ACLR_C1="ACLR0" INPUT_ACLR_C2="ACLR0" INPUT_ACLR_C3="ACLR0" INPUT_REGISTER_A0="CLOCK0" INPUT_REGISTER_A1="CLOCK0" INPUT_REGISTER_A2="CLOCK0" INPUT_REGISTER_A3="CLOCK0" INPUT_REGISTER_B0="CLOCK0" INPUT_REGISTER_B1="CLOCK0" INPUT_REGISTER_B2="CLOCK0" INPUT_REGISTER_B3="CLOCK0" INPUT_REGISTER_C0="CLOCK0" INPUT_REGISTER_C1="CLOCK0" INPUT_REGISTER_C2="CLOCK0" INPUT_REGISTER_C3="CLOCK0" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_A1="DATAA" INPUT_SOURCE_A2="DATAA" INPUT_SOURCE_A3="DATAA" INPUT_SOURCE_B0="DATAB" INPUT_SOURCE_B1="DATAB" INPUT_SOURCE_B2="DATAB" INPUT_SOURCE_B3="DATAB" LOADCONST_CONTROL_ACLR="ACLR0" LOADCONST_CONTROL_REGISTER="CLOCK0" LOADCONST_VALUE=64 MULT01_ROUND_ACLR="ACLR0" MULT01_ROUND_REGISTER="CLOCK0" MULT01_SATURATION_ACLR="ACLR1" MULT01_SATURATION_REGISTER="CLOCK0" MULT23_ROUND_ACLR="ACLR0" MULT23_ROUND_REGISTER="CLOCK0" MULT23_SATURATION_ACLR="ACLR0" MULT23_SATURATION_REGISTER="CLOCK0" MULTIPLIER01_ROUNDING="NO" MULTIPLIER01_SATURATION="NO" MULTIPLIER1_DIRECTION="SUB" MULTIPLIER23_ROUNDING="NO" MULTIPLIER23_SATURATION="NO" MULTIPLIER3_DIRECTION="ADD" MULTIPLIER_ACLR0="ACLR0" MULTIPLIER_ACLR1="ACLR0" MULTIPLIER_ACLR2="ACLR0" MULTIPLIER_ACLR3="ACLR0" MULTIPLIER_REGISTER0="CLOCK0" MULTIPLIER_REGISTER1="CLOCK0" MULTIPLIER_REGISTER2="CLOCK0" MULTIPLIER_REGISTER3="CLOCK0" NUMBER_OF_MULTIPLIERS=2 OUTPUT_ACLR="ACLR0" OUTPUT_REGISTER="CLOCK0" OUTPUT_ROUND_ACLR="ACLR0" OUTPUT_ROUND_PIPELINE_ACLR="ACLR0" OUTPUT_ROUND_PIPELINE_REGISTER="CLOCK0" OUTPUT_ROUND_REGISTER="CLOCK0" OUTPUT_ROUND_TYPE="NEAREST_INTEGER" OUTPUT_ROUNDING="NO" OUTPUT_SATURATE_ACLR="ACLR0" OUTPUT_SATURATE_PIPELINE_ACLR="ACLR0" OUTPUT_SATURATE_PIPELINE_REGISTER="CLOCK0" OUTPUT_SATURATE_REGISTER="CLOCK0" OUTPUT_SATURATE_TYPE="ASYMMETRIC" OUTPUT_SATURATION="NO" port_addnsub1="PORT_UNUSED" port_addnsub3="PORT_UNUSED" PORT_CHAINOUT_SAT_IS_OVERFLOW="PORT_UNUSED" PORT_OUTPUT_IS_OVERFLOW="PORT_UNUSED" port_signa="PORT_UNUSED" port_signb="PORT_UNUSED" PREADDER_DIRECTION_0="ADD" PREADDER_DIRECTION_1="ADD" PREADDER_DIRECTION_2="ADD" PREADDER_DIRECTION_3="ADD" PREADDER_MODE="SIMPLE" REPRESENTATION_A="SIGNED" REPRESENTATION_B="SIGNED" ROTATE_ACLR="ACLR0" ROTATE_OUTPUT_ACLR="ACLR0" ROTATE_OUTPUT_REGISTER="CLOCK0" ROTATE_PIPELINE_ACLR="ACLR0" ROTATE_PIPELINE_REGISTER="CLOCK0" ROTATE_REGISTER="CLOCK0" SCANOUTA_ACLR="ACLR0" SCANOUTA_REGISTER="UNREGISTERED" SELECTED_DEVICE_FAMILY="Cyclone V" SHIFT_MODE="NO" SHIFT_RIGHT_ACLR="ACLR0" SHIFT_RIGHT_OUTPUT_ACLR="ACLR0" SHIFT_RIGHT_OUTPUT_REGISTER="CLOCK0" SHIFT_RIGHT_PIPELINE_ACLR="ACLR0" SHIFT_RIGHT_PIPELINE_REGISTER="CLOCK0" SHIFT_RIGHT_REGISTER="CLOCK0" SIGNED_ACLR_A="ACLR0" SIGNED_ACLR_B="ACLR0" SIGNED_PIPELINE_ACLR_A="ACLR0" SIGNED_PIPELINE_ACLR_B="ACLR0" SIGNED_PIPELINE_REGISTER_A="CLOCK0" SIGNED_PIPELINE_REGISTER_B="CLOCK0" SIGNED_REGISTER_A="CLOCK0" SIGNED_REGISTER_B="CLOCK0" SYSTOLIC_ACLR1="ACLR0" SYSTOLIC_ACLR3="ACLR0" SYSTOLIC_DELAY1="UNREGISTERED" SYSTOLIC_DELAY3="UNREGISTERED" WIDTH_A=32 WIDTH_B=10 WIDTH_C=22 WIDTH_CHAININ=1 WIDTH_COEF=18 WIDTH_MSB=17 WIDTH_RESULT=42 WIDTH_SATURATE_SIGN=1 ZERO_CHAINOUT_OUTPUT_ACLR="ACLR0" ZERO_CHAINOUT_OUTPUT_REGISTER="CLOCK0" ZERO_LOOPBACK_ACLR="ACLR0" ZERO_LOOPBACK_OUTPUT_ACLR="ACLR0" ZERO_LOOPBACK_OUTPUT_REGISTER="CLOCK0" ZERO_LOOPBACK_PIPELINE_ACLR="ACLR0" ZERO_LOOPBACK_PIPELINE_REGISTER="CLOCK0" ZERO_LOOPBACK_REGISTER="CLOCK0" aclr0 clock0 dataa datab ena0 ena1 ena2 ena3 result
//VERSION_BEGIN 13.1 cbx_altera_mult_add 2013:10:23:18:05:48:SJ cbx_altera_mult_add_rtl 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//synthesis_resources = altera_mult_add_rtl 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module complex_mult_altera_mult_add_6f4g
(
aclr0,
clock0,
dataa,
datab,
ena0,
ena1,
ena2,
ena3,
result) ;
input aclr0;
input clock0;
input [63:0] dataa;
input [19:0] datab;
input ena0;
input ena1;
input ena2;
input ena3;
output [41:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr0;
tri1 clock0;
tri0 [63:0] dataa;
tri0 [19:0] datab;
tri1 ena0;
tri1 ena1;
tri1 ena2;
tri1 ena3;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [41:0] wire_altera_mult_add_rtl2_result;
altera_mult_add_rtl altera_mult_add_rtl2
(
.aclr0(aclr0),
.chainout_sat_overflow(),
.clock0(clock0),
.dataa(dataa),
.datab(datab),
.ena0(ena0),
.ena1(ena1),
.ena2(ena2),
.ena3(ena3),
.mult0_is_saturated(),
.mult1_is_saturated(),
.mult2_is_saturated(),
.mult3_is_saturated(),
.overflow(),
.result(wire_altera_mult_add_rtl2_result),
.scanouta(),
.scanoutb(),
.accum_sload(1'b0),
.aclr1(1'b0),
.aclr2(1'b0),
.aclr3(1'b0),
.addnsub1(1'b1),
.addnsub1_round(1'b0),
.addnsub3(1'b1),
.addnsub3_round(1'b0),
.chainin({1{1'b0}}),
.chainout_round(1'b0),
.chainout_saturate(1'b0),
.clock1(1'b1),
.clock2(1'b1),
.clock3(1'b1),
.coefsel0({3{1'b0}}),
.coefsel1({3{1'b0}}),
.coefsel2({3{1'b0}}),
.coefsel3({3{1'b0}}),
.datac({44{1'b0}}),
.mult01_round(1'b0),
.mult01_saturation(1'b0),
.mult23_round(1'b0),
.mult23_saturation(1'b0),
.output_round(1'b0),
.output_saturate(1'b0),
.rotate(1'b0),
.scanina({32{1'b0}}),
.scaninb({10{1'b0}}),
.shift_right(1'b0),
.signa(1'b0),
.signb(1'b0),
.sload_accum(1'b0),
.sourcea({2{1'b0}}),
.sourceb({2{1'b0}}),
.zero_chainout(1'b0),
.zero_loopback(1'b0)
);
defparam
altera_mult_add_rtl2.accum_direction = "ADD",
altera_mult_add_rtl2.accum_sload_aclr = "ACLR0",
altera_mult_add_rtl2.accum_sload_latency_aclr = "NONE",
altera_mult_add_rtl2.accum_sload_latency_clock = "UNREGISTERED",
altera_mult_add_rtl2.accum_sload_register = "CLOCK0",
altera_mult_add_rtl2.accumulator = "NO",
altera_mult_add_rtl2.adder1_rounding = "NO",
altera_mult_add_rtl2.adder3_rounding = "NO",
altera_mult_add_rtl2.addnsub1_round_aclr = "ACLR0",
altera_mult_add_rtl2.addnsub1_round_pipeline_aclr = "ACLR0",
altera_mult_add_rtl2.addnsub1_round_pipeline_register = "CLOCK0",
altera_mult_add_rtl2.addnsub1_round_register = "CLOCK0",
altera_mult_add_rtl2.addnsub3_round_aclr = "ACLR0",
altera_mult_add_rtl2.addnsub3_round_pipeline_aclr = "ACLR0",
altera_mult_add_rtl2.addnsub3_round_pipeline_register = "CLOCK0",
altera_mult_add_rtl2.addnsub3_round_register = "CLOCK0",
altera_mult_add_rtl2.addnsub_multiplier_aclr1 = "ACLR0",
altera_mult_add_rtl2.addnsub_multiplier_aclr3 = "ACLR0",
altera_mult_add_rtl2.addnsub_multiplier_latency_aclr1 = "NONE",
altera_mult_add_rtl2.addnsub_multiplier_latency_aclr3 = "NONE",
altera_mult_add_rtl2.addnsub_multiplier_latency_clock1 = "UNREGISTERED",
altera_mult_add_rtl2.addnsub_multiplier_latency_clock3 = "UNREGISTERED",
altera_mult_add_rtl2.addnsub_multiplier_register1 = "CLOCK0",
altera_mult_add_rtl2.addnsub_multiplier_register3 = "CLOCK0",
altera_mult_add_rtl2.chainout_aclr = "ACLR0",
altera_mult_add_rtl2.chainout_adder = "NO",
altera_mult_add_rtl2.chainout_register = "CLOCK0",
altera_mult_add_rtl2.chainout_round_aclr = "ACLR0",
altera_mult_add_rtl2.chainout_round_output_aclr = "ACLR0",
altera_mult_add_rtl2.chainout_round_output_register = "CLOCK0",
altera_mult_add_rtl2.chainout_round_pipeline_aclr = "ACLR0",
altera_mult_add_rtl2.chainout_round_pipeline_register = "CLOCK0",
altera_mult_add_rtl2.chainout_round_register = "CLOCK0",
altera_mult_add_rtl2.chainout_rounding = "NO",
altera_mult_add_rtl2.chainout_saturate_aclr = "ACLR0",
altera_mult_add_rtl2.chainout_saturate_output_aclr = "ACLR0",
altera_mult_add_rtl2.chainout_saturate_output_register = "CLOCK0",
altera_mult_add_rtl2.chainout_saturate_pipeline_aclr = "ACLR0",
altera_mult_add_rtl2.chainout_saturate_pipeline_register = "CLOCK0",
altera_mult_add_rtl2.chainout_saturate_register = "CLOCK0",
altera_mult_add_rtl2.chainout_saturation = "NO",
altera_mult_add_rtl2.coef0_0 = 0,
altera_mult_add_rtl2.coef0_1 = 0,
altera_mult_add_rtl2.coef0_2 = 0,
altera_mult_add_rtl2.coef0_3 = 0,
altera_mult_add_rtl2.coef0_4 = 0,
altera_mult_add_rtl2.coef0_5 = 0,
altera_mult_add_rtl2.coef0_6 = 0,
altera_mult_add_rtl2.coef0_7 = 0,
altera_mult_add_rtl2.coef1_0 = 0,
altera_mult_add_rtl2.coef1_1 = 0,
altera_mult_add_rtl2.coef1_2 = 0,
altera_mult_add_rtl2.coef1_3 = 0,
altera_mult_add_rtl2.coef1_4 = 0,
altera_mult_add_rtl2.coef1_5 = 0,
altera_mult_add_rtl2.coef1_6 = 0,
altera_mult_add_rtl2.coef1_7 = 0,
altera_mult_add_rtl2.coef2_0 = 0,
altera_mult_add_rtl2.coef2_1 = 0,
altera_mult_add_rtl2.coef2_2 = 0,
altera_mult_add_rtl2.coef2_3 = 0,
altera_mult_add_rtl2.coef2_4 = 0,
altera_mult_add_rtl2.coef2_5 = 0,
altera_mult_add_rtl2.coef2_6 = 0,
altera_mult_add_rtl2.coef2_7 = 0,
altera_mult_add_rtl2.coef3_0 = 0,
altera_mult_add_rtl2.coef3_1 = 0,
altera_mult_add_rtl2.coef3_2 = 0,
altera_mult_add_rtl2.coef3_3 = 0,
altera_mult_add_rtl2.coef3_4 = 0,
altera_mult_add_rtl2.coef3_5 = 0,
altera_mult_add_rtl2.coef3_6 = 0,
altera_mult_add_rtl2.coef3_7 = 0,
altera_mult_add_rtl2.coefsel0_aclr = "ACLR0",
altera_mult_add_rtl2.coefsel0_latency_aclr = "NONE",
altera_mult_add_rtl2.coefsel0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl2.coefsel0_register = "CLOCK0",
altera_mult_add_rtl2.coefsel1_aclr = "ACLR0",
altera_mult_add_rtl2.coefsel1_latency_aclr = "NONE",
altera_mult_add_rtl2.coefsel1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl2.coefsel1_register = "CLOCK0",
altera_mult_add_rtl2.coefsel2_aclr = "ACLR0",
altera_mult_add_rtl2.coefsel2_latency_aclr = "NONE",
altera_mult_add_rtl2.coefsel2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl2.coefsel2_register = "CLOCK0",
altera_mult_add_rtl2.coefsel3_aclr = "ACLR0",
altera_mult_add_rtl2.coefsel3_latency_aclr = "NONE",
altera_mult_add_rtl2.coefsel3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl2.coefsel3_register = "CLOCK0",
altera_mult_add_rtl2.dedicated_multiplier_circuitry = "AUTO",
altera_mult_add_rtl2.double_accum = "NO",
altera_mult_add_rtl2.dsp_block_balancing = "Auto",
altera_mult_add_rtl2.extra_latency = 0,
altera_mult_add_rtl2.input_a0_latency_aclr = "NONE",
altera_mult_add_rtl2.input_a0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl2.input_a1_latency_aclr = "NONE",
altera_mult_add_rtl2.input_a1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl2.input_a2_latency_aclr = "NONE",
altera_mult_add_rtl2.input_a2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl2.input_a3_latency_aclr = "NONE",
altera_mult_add_rtl2.input_a3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl2.input_aclr_a0 = "ACLR0",
altera_mult_add_rtl2.input_aclr_a1 = "ACLR0",
altera_mult_add_rtl2.input_aclr_a2 = "ACLR0",
altera_mult_add_rtl2.input_aclr_a3 = "ACLR0",
altera_mult_add_rtl2.input_aclr_b0 = "ACLR0",
altera_mult_add_rtl2.input_aclr_b1 = "ACLR0",
altera_mult_add_rtl2.input_aclr_b2 = "ACLR0",
altera_mult_add_rtl2.input_aclr_b3 = "ACLR0",
altera_mult_add_rtl2.input_aclr_c0 = "ACLR0",
altera_mult_add_rtl2.input_aclr_c1 = "ACLR0",
altera_mult_add_rtl2.input_aclr_c2 = "ACLR0",
altera_mult_add_rtl2.input_aclr_c3 = "ACLR0",
altera_mult_add_rtl2.input_b0_latency_aclr = "NONE",
altera_mult_add_rtl2.input_b0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl2.input_b1_latency_aclr = "NONE",
altera_mult_add_rtl2.input_b1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl2.input_b2_latency_aclr = "NONE",
altera_mult_add_rtl2.input_b2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl2.input_b3_latency_aclr = "NONE",
altera_mult_add_rtl2.input_b3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl2.input_c0_latency_aclr = "NONE",
altera_mult_add_rtl2.input_c0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl2.input_c1_latency_aclr = "NONE",
altera_mult_add_rtl2.input_c1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl2.input_c2_latency_aclr = "NONE",
altera_mult_add_rtl2.input_c2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl2.input_c3_latency_aclr = "NONE",
altera_mult_add_rtl2.input_c3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl2.input_register_a0 = "CLOCK0",
altera_mult_add_rtl2.input_register_a1 = "CLOCK0",
altera_mult_add_rtl2.input_register_a2 = "CLOCK0",
altera_mult_add_rtl2.input_register_a3 = "CLOCK0",
altera_mult_add_rtl2.input_register_b0 = "CLOCK0",
altera_mult_add_rtl2.input_register_b1 = "CLOCK0",
altera_mult_add_rtl2.input_register_b2 = "CLOCK0",
altera_mult_add_rtl2.input_register_b3 = "CLOCK0",
altera_mult_add_rtl2.input_register_c0 = "CLOCK0",
altera_mult_add_rtl2.input_register_c1 = "CLOCK0",
altera_mult_add_rtl2.input_register_c2 = "CLOCK0",
altera_mult_add_rtl2.input_register_c3 = "CLOCK0",
altera_mult_add_rtl2.input_source_a0 = "DATAA",
altera_mult_add_rtl2.input_source_a1 = "DATAA",
altera_mult_add_rtl2.input_source_a2 = "DATAA",
altera_mult_add_rtl2.input_source_a3 = "DATAA",
altera_mult_add_rtl2.input_source_b0 = "DATAB",
altera_mult_add_rtl2.input_source_b1 = "DATAB",
altera_mult_add_rtl2.input_source_b2 = "DATAB",
altera_mult_add_rtl2.input_source_b3 = "DATAB",
altera_mult_add_rtl2.latency = 0,
altera_mult_add_rtl2.loadconst_control_aclr = "ACLR0",
altera_mult_add_rtl2.loadconst_control_register = "CLOCK0",
altera_mult_add_rtl2.loadconst_value = 64,
altera_mult_add_rtl2.mult01_round_aclr = "ACLR0",
altera_mult_add_rtl2.mult01_round_register = "CLOCK0",
altera_mult_add_rtl2.mult01_saturation_aclr = "ACLR1",
altera_mult_add_rtl2.mult01_saturation_register = "CLOCK0",
altera_mult_add_rtl2.mult23_round_aclr = "ACLR0",
altera_mult_add_rtl2.mult23_round_register = "CLOCK0",
altera_mult_add_rtl2.mult23_saturation_aclr = "ACLR0",
altera_mult_add_rtl2.mult23_saturation_register = "CLOCK0",
altera_mult_add_rtl2.multiplier01_rounding = "NO",
altera_mult_add_rtl2.multiplier01_saturation = "NO",
altera_mult_add_rtl2.multiplier1_direction = "SUB",
altera_mult_add_rtl2.multiplier23_rounding = "NO",
altera_mult_add_rtl2.multiplier23_saturation = "NO",
altera_mult_add_rtl2.multiplier3_direction = "ADD",
altera_mult_add_rtl2.multiplier_aclr0 = "ACLR0",
altera_mult_add_rtl2.multiplier_aclr1 = "ACLR0",
altera_mult_add_rtl2.multiplier_aclr2 = "ACLR0",
altera_mult_add_rtl2.multiplier_aclr3 = "ACLR0",
altera_mult_add_rtl2.multiplier_register0 = "CLOCK0",
altera_mult_add_rtl2.multiplier_register1 = "CLOCK0",
altera_mult_add_rtl2.multiplier_register2 = "CLOCK0",
altera_mult_add_rtl2.multiplier_register3 = "CLOCK0",
altera_mult_add_rtl2.number_of_multipliers = 2,
altera_mult_add_rtl2.output_aclr = "ACLR0",
altera_mult_add_rtl2.output_register = "CLOCK0",
altera_mult_add_rtl2.output_round_aclr = "ACLR0",
altera_mult_add_rtl2.output_round_pipeline_aclr = "ACLR0",
altera_mult_add_rtl2.output_round_pipeline_register = "CLOCK0",
altera_mult_add_rtl2.output_round_register = "CLOCK0",
altera_mult_add_rtl2.output_round_type = "NEAREST_INTEGER",
altera_mult_add_rtl2.output_rounding = "NO",
altera_mult_add_rtl2.output_saturate_aclr = "ACLR0",
altera_mult_add_rtl2.output_saturate_pipeline_aclr = "ACLR0",
altera_mult_add_rtl2.output_saturate_pipeline_register = "CLOCK0",
altera_mult_add_rtl2.output_saturate_register = "CLOCK0",
altera_mult_add_rtl2.output_saturate_type = "ASYMMETRIC",
altera_mult_add_rtl2.output_saturation = "NO",
altera_mult_add_rtl2.port_addnsub1 = "PORT_UNUSED",
altera_mult_add_rtl2.port_addnsub3 = "PORT_UNUSED",
altera_mult_add_rtl2.port_chainout_sat_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl2.port_output_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl2.port_signa = "PORT_UNUSED",
altera_mult_add_rtl2.port_signb = "PORT_UNUSED",
altera_mult_add_rtl2.preadder_direction_0 = "ADD",
altera_mult_add_rtl2.preadder_direction_1 = "ADD",
altera_mult_add_rtl2.preadder_direction_2 = "ADD",
altera_mult_add_rtl2.preadder_direction_3 = "ADD",
altera_mult_add_rtl2.preadder_mode = "SIMPLE",
altera_mult_add_rtl2.representation_a = "SIGNED",
altera_mult_add_rtl2.representation_b = "SIGNED",
altera_mult_add_rtl2.rotate_aclr = "ACLR0",
altera_mult_add_rtl2.rotate_output_aclr = "ACLR0",
altera_mult_add_rtl2.rotate_output_register = "CLOCK0",
altera_mult_add_rtl2.rotate_pipeline_aclr = "ACLR0",
altera_mult_add_rtl2.rotate_pipeline_register = "CLOCK0",
altera_mult_add_rtl2.rotate_register = "CLOCK0",
altera_mult_add_rtl2.scanouta_aclr = "ACLR0",
altera_mult_add_rtl2.scanouta_register = "UNREGISTERED",
altera_mult_add_rtl2.selected_device_family = "Cyclone V",
altera_mult_add_rtl2.shift_mode = "NO",
altera_mult_add_rtl2.shift_right_aclr = "ACLR0",
altera_mult_add_rtl2.shift_right_output_aclr = "ACLR0",
altera_mult_add_rtl2.shift_right_output_register = "CLOCK0",
altera_mult_add_rtl2.shift_right_pipeline_aclr = "ACLR0",
altera_mult_add_rtl2.shift_right_pipeline_register = "CLOCK0",
altera_mult_add_rtl2.shift_right_register = "CLOCK0",
altera_mult_add_rtl2.signed_aclr_a = "ACLR0",
altera_mult_add_rtl2.signed_aclr_b = "ACLR0",
altera_mult_add_rtl2.signed_latency_aclr_a = "NONE",
altera_mult_add_rtl2.signed_latency_aclr_b = "NONE",
altera_mult_add_rtl2.signed_latency_clock_a = "UNREGISTERED",
altera_mult_add_rtl2.signed_latency_clock_b = "UNREGISTERED",
altera_mult_add_rtl2.signed_register_a = "CLOCK0",
altera_mult_add_rtl2.signed_register_b = "CLOCK0",
altera_mult_add_rtl2.systolic_aclr1 = "ACLR0",
altera_mult_add_rtl2.systolic_aclr3 = "ACLR0",
altera_mult_add_rtl2.systolic_delay1 = "UNREGISTERED",
altera_mult_add_rtl2.systolic_delay3 = "UNREGISTERED",
altera_mult_add_rtl2.use_sload_accum_port = "NO",
altera_mult_add_rtl2.width_a = 32,
altera_mult_add_rtl2.width_b = 10,
altera_mult_add_rtl2.width_c = 22,
altera_mult_add_rtl2.width_chainin = 1,
altera_mult_add_rtl2.width_coef = 18,
altera_mult_add_rtl2.width_msb = 17,
altera_mult_add_rtl2.width_result = 42,
altera_mult_add_rtl2.width_saturate_sign = 1,
altera_mult_add_rtl2.zero_chainout_output_aclr = "ACLR0",
altera_mult_add_rtl2.zero_chainout_output_register = "CLOCK0",
altera_mult_add_rtl2.zero_loopback_aclr = "ACLR0",
altera_mult_add_rtl2.zero_loopback_output_aclr = "ACLR0",
altera_mult_add_rtl2.zero_loopback_output_register = "CLOCK0",
altera_mult_add_rtl2.zero_loopback_pipeline_aclr = "ACLR0",
altera_mult_add_rtl2.zero_loopback_pipeline_register = "CLOCK0",
altera_mult_add_rtl2.zero_loopback_register = "CLOCK0",
altera_mult_add_rtl2.lpm_type = "altera_mult_add_rtl";
assign
result = wire_altera_mult_add_rtl2_result;
endmodule //complex_mult_altera_mult_add_6f4g
//synthesis_resources = altera_mult_add_rtl 1 dsp_mac 2 reg 42
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module complex_mult_mult_add_frt1
(
aclr0,
clock0,
dataa,
datab,
ena0,
result) ;
input aclr0;
input clock0;
input [63:0] dataa;
input [19:0] datab;
input ena0;
output [41:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr0;
tri1 clock0;
tri0 [63:0] dataa;
tri0 [19:0] datab;
tri1 ena0;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [41:0] wire_altera_mult_add1_result;
wire ena1;
wire ena2;
wire ena3;
complex_mult_altera_mult_add_6f4g altera_mult_add1
(
.aclr0(aclr0),
.clock0(clock0),
.dataa(dataa),
.datab(datab),
.ena0(ena0),
.ena1(ena1),
.ena2(ena2),
.ena3(ena3),
.result(wire_altera_mult_add1_result));
assign
ena1 = 1'b1,
ena2 = 1'b1,
ena3 = 1'b1,
result = wire_altera_mult_add1_result;
endmodule //complex_mult_mult_add_frt1
//altmult_add CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" INPUT_ACLR_A0="ACLR0" INPUT_ACLR_A1="ACLR0" INPUT_ACLR_B0="ACLR0" INPUT_ACLR_B1="ACLR0" INPUT_REGISTER_A0="CLOCK0" INPUT_REGISTER_A1="CLOCK0" INPUT_REGISTER_B0="CLOCK0" INPUT_REGISTER_B1="CLOCK0" MULTIPLIER1_DIRECTION="ADD" MULTIPLIER_ACLR0="ACLR0" MULTIPLIER_ACLR1="ACLR0" MULTIPLIER_REGISTER0="CLOCK0" MULTIPLIER_REGISTER1="CLOCK0" NUMBER_OF_MULTIPLIERS=2 OUTPUT_ACLR="ACLR0" OUTPUT_REGISTER="CLOCK0" port_addnsub1="PORT_UNUSED" port_signa="PORT_UNUSED" port_signb="PORT_UNUSED" REPRESENTATION_A="SIGNED" REPRESENTATION_B="SIGNED" WIDTH_A=32 WIDTH_B=10 WIDTH_C=22 WIDTH_RESULT=42 aclr0 clock0 dataa datab ena0 result
//VERSION_BEGIN 13.1 cbx_alt_ded_mult_y 2013:10:23:18:05:48:SJ cbx_altera_mult_add 2013:10:23:18:05:48:SJ cbx_altera_mult_add_rtl 2013:10:23:18:05:48:SJ cbx_altmult_add 2013:10:23:18:05:48:SJ cbx_cycloneii 2013:10:23:18:05:48:SJ cbx_lpm_add_sub 2013:10:23:18:05:48:SJ cbx_lpm_mult 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_padd 2013:10:23:18:05:48:SJ cbx_parallel_add 2013:10:23:18:05:48:SJ cbx_stratix 2013:10:23:18:05:48:SJ cbx_stratixii 2013:10:23:18:05:48:SJ cbx_util_mgl 2013:10:23:18:05:48:SJ VERSION_END
//altera_mult_add ACCUM_DIRECTION="ADD" ACCUM_SLOAD_ACLR="ACLR0" ACCUM_SLOAD_PIPELINE_ACLR="ACLR0" ACCUM_SLOAD_PIPELINE_REGISTER="CLOCK0" ACCUM_SLOAD_REGISTER="CLOCK0" ACCUMULATOR="NO" ADDER1_ROUNDING="NO" ADDER3_ROUNDING="NO" ADDNSUB1_ROUND_ACLR="ACLR0" ADDNSUB1_ROUND_PIPELINE_ACLR="ACLR0" ADDNSUB1_ROUND_PIPELINE_REGISTER="CLOCK0" ADDNSUB1_ROUND_REGISTER="CLOCK0" ADDNSUB3_ROUND_ACLR="ACLR0" ADDNSUB3_ROUND_PIPELINE_ACLR="ACLR0" ADDNSUB3_ROUND_PIPELINE_REGISTER="CLOCK0" ADDNSUB3_ROUND_REGISTER="CLOCK0" ADDNSUB_MULTIPLIER_ACLR1="ACLR0" ADDNSUB_MULTIPLIER_ACLR3="ACLR0" ADDNSUB_MULTIPLIER_PIPELINE_ACLR1="ACLR0" ADDNSUB_MULTIPLIER_PIPELINE_ACLR3="ACLR0" ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER3="CLOCK0" CBX_AUTO_BLACKBOX="ALL" CHAINOUT_ACLR="ACLR0" CHAINOUT_ADDER="NO" CHAINOUT_REGISTER="CLOCK0" CHAINOUT_ROUND_ACLR="ACLR0" CHAINOUT_ROUND_OUTPUT_ACLR="ACLR0" CHAINOUT_ROUND_OUTPUT_REGISTER="CLOCK0" CHAINOUT_ROUND_PIPELINE_ACLR="ACLR0" CHAINOUT_ROUND_PIPELINE_REGISTER="CLOCK0" CHAINOUT_ROUND_REGISTER="CLOCK0" CHAINOUT_ROUNDING="NO" CHAINOUT_SATURATE_ACLR="ACLR0" CHAINOUT_SATURATE_OUTPUT_ACLR="ACLR0" CHAINOUT_SATURATE_OUTPUT_REGISTER="CLOCK0" CHAINOUT_SATURATE_PIPELINE_ACLR="ACLR0" CHAINOUT_SATURATE_PIPELINE_REGISTER="CLOCK0" CHAINOUT_SATURATE_REGISTER="CLOCK0" CHAINOUT_SATURATION="NO" COEF0_0=0 COEF0_1=0 COEF0_2=0 COEF0_3=0 COEF0_4=0 COEF0_5=0 COEF0_6=0 COEF0_7=0 COEF1_0=0 COEF1_1=0 COEF1_2=0 COEF1_3=0 COEF1_4=0 COEF1_5=0 COEF1_6=0 COEF1_7=0 COEF2_0=0 COEF2_1=0 COEF2_2=0 COEF2_3=0 COEF2_4=0 COEF2_5=0 COEF2_6=0 COEF2_7=0 COEF3_0=0 COEF3_1=0 COEF3_2=0 COEF3_3=0 COEF3_4=0 COEF3_5=0 COEF3_6=0 COEF3_7=0 COEFSEL0_ACLR="ACLR0" COEFSEL0_REGISTER="CLOCK0" COEFSEL1_ACLR="ACLR0" COEFSEL1_REGISTER="CLOCK0" COEFSEL2_ACLR="ACLR0" COEFSEL2_REGISTER="CLOCK0" COEFSEL3_ACLR="ACLR0" COEFSEL3_REGISTER="CLOCK0" DEDICATED_MULTIPLIER_CIRCUITRY="AUTO" DEVICE_FAMILY="Cyclone V" DOUBLE_ACCUM="NO" DSP_BLOCK_BALANCING="Auto" EXTRA_LATENCY=0 INPUT_ACLR_A0="ACLR0" INPUT_ACLR_A1="ACLR0" INPUT_ACLR_A2="ACLR0" INPUT_ACLR_A3="ACLR0" INPUT_ACLR_B0="ACLR0" INPUT_ACLR_B1="ACLR0" INPUT_ACLR_B2="ACLR0" INPUT_ACLR_B3="ACLR0" INPUT_ACLR_C0="ACLR0" INPUT_ACLR_C1="ACLR0" INPUT_ACLR_C2="ACLR0" INPUT_ACLR_C3="ACLR0" INPUT_REGISTER_A0="CLOCK0" INPUT_REGISTER_A1="CLOCK0" INPUT_REGISTER_A2="CLOCK0" INPUT_REGISTER_A3="CLOCK0" INPUT_REGISTER_B0="CLOCK0" INPUT_REGISTER_B1="CLOCK0" INPUT_REGISTER_B2="CLOCK0" INPUT_REGISTER_B3="CLOCK0" INPUT_REGISTER_C0="CLOCK0" INPUT_REGISTER_C1="CLOCK0" INPUT_REGISTER_C2="CLOCK0" INPUT_REGISTER_C3="CLOCK0" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_A1="DATAA" INPUT_SOURCE_A2="DATAA" INPUT_SOURCE_A3="DATAA" INPUT_SOURCE_B0="DATAB" INPUT_SOURCE_B1="DATAB" INPUT_SOURCE_B2="DATAB" INPUT_SOURCE_B3="DATAB" LOADCONST_CONTROL_ACLR="ACLR0" LOADCONST_CONTROL_REGISTER="CLOCK0" LOADCONST_VALUE=64 MULT01_ROUND_ACLR="ACLR0" MULT01_ROUND_REGISTER="CLOCK0" MULT01_SATURATION_ACLR="ACLR1" MULT01_SATURATION_REGISTER="CLOCK0" MULT23_ROUND_ACLR="ACLR0" MULT23_ROUND_REGISTER="CLOCK0" MULT23_SATURATION_ACLR="ACLR0" MULT23_SATURATION_REGISTER="CLOCK0" MULTIPLIER01_ROUNDING="NO" MULTIPLIER01_SATURATION="NO" MULTIPLIER1_DIRECTION="ADD" MULTIPLIER23_ROUNDING="NO" MULTIPLIER23_SATURATION="NO" MULTIPLIER3_DIRECTION="ADD" MULTIPLIER_ACLR0="ACLR0" MULTIPLIER_ACLR1="ACLR0" MULTIPLIER_ACLR2="ACLR0" MULTIPLIER_ACLR3="ACLR0" MULTIPLIER_REGISTER0="CLOCK0" MULTIPLIER_REGISTER1="CLOCK0" MULTIPLIER_REGISTER2="CLOCK0" MULTIPLIER_REGISTER3="CLOCK0" NUMBER_OF_MULTIPLIERS=2 OUTPUT_ACLR="ACLR0" OUTPUT_REGISTER="CLOCK0" OUTPUT_ROUND_ACLR="ACLR0" OUTPUT_ROUND_PIPELINE_ACLR="ACLR0" OUTPUT_ROUND_PIPELINE_REGISTER="CLOCK0" OUTPUT_ROUND_REGISTER="CLOCK0" OUTPUT_ROUND_TYPE="NEAREST_INTEGER" OUTPUT_ROUNDING="NO" OUTPUT_SATURATE_ACLR="ACLR0" OUTPUT_SATURATE_PIPELINE_ACLR="ACLR0" OUTPUT_SATURATE_PIPELINE_REGISTER="CLOCK0" OUTPUT_SATURATE_REGISTER="CLOCK0" OUTPUT_SATURATE_TYPE="ASYMMETRIC" OUTPUT_SATURATION="NO" port_addnsub1="PORT_UNUSED" port_addnsub3="PORT_UNUSED" PORT_CHAINOUT_SAT_IS_OVERFLOW="PORT_UNUSED" PORT_OUTPUT_IS_OVERFLOW="PORT_UNUSED" port_signa="PORT_UNUSED" port_signb="PORT_UNUSED" PREADDER_DIRECTION_0="ADD" PREADDER_DIRECTION_1="ADD" PREADDER_DIRECTION_2="ADD" PREADDER_DIRECTION_3="ADD" PREADDER_MODE="SIMPLE" REPRESENTATION_A="SIGNED" REPRESENTATION_B="SIGNED" ROTATE_ACLR="ACLR0" ROTATE_OUTPUT_ACLR="ACLR0" ROTATE_OUTPUT_REGISTER="CLOCK0" ROTATE_PIPELINE_ACLR="ACLR0" ROTATE_PIPELINE_REGISTER="CLOCK0" ROTATE_REGISTER="CLOCK0" SCANOUTA_ACLR="ACLR0" SCANOUTA_REGISTER="UNREGISTERED" SELECTED_DEVICE_FAMILY="Cyclone V" SHIFT_MODE="NO" SHIFT_RIGHT_ACLR="ACLR0" SHIFT_RIGHT_OUTPUT_ACLR="ACLR0" SHIFT_RIGHT_OUTPUT_REGISTER="CLOCK0" SHIFT_RIGHT_PIPELINE_ACLR="ACLR0" SHIFT_RIGHT_PIPELINE_REGISTER="CLOCK0" SHIFT_RIGHT_REGISTER="CLOCK0" SIGNED_ACLR_A="ACLR0" SIGNED_ACLR_B="ACLR0" SIGNED_PIPELINE_ACLR_A="ACLR0" SIGNED_PIPELINE_ACLR_B="ACLR0" SIGNED_PIPELINE_REGISTER_A="CLOCK0" SIGNED_PIPELINE_REGISTER_B="CLOCK0" SIGNED_REGISTER_A="CLOCK0" SIGNED_REGISTER_B="CLOCK0" SYSTOLIC_ACLR1="ACLR0" SYSTOLIC_ACLR3="ACLR0" SYSTOLIC_DELAY1="UNREGISTERED" SYSTOLIC_DELAY3="UNREGISTERED" WIDTH_A=32 WIDTH_B=10 WIDTH_C=22 WIDTH_CHAININ=1 WIDTH_COEF=18 WIDTH_MSB=17 WIDTH_RESULT=42 WIDTH_SATURATE_SIGN=1 ZERO_CHAINOUT_OUTPUT_ACLR="ACLR0" ZERO_CHAINOUT_OUTPUT_REGISTER="CLOCK0" ZERO_LOOPBACK_ACLR="ACLR0" ZERO_LOOPBACK_OUTPUT_ACLR="ACLR0" ZERO_LOOPBACK_OUTPUT_REGISTER="CLOCK0" ZERO_LOOPBACK_PIPELINE_ACLR="ACLR0" ZERO_LOOPBACK_PIPELINE_REGISTER="CLOCK0" ZERO_LOOPBACK_REGISTER="CLOCK0" aclr0 clock0 dataa datab ena0 ena1 ena2 ena3 result
//VERSION_BEGIN 13.1 cbx_altera_mult_add 2013:10:23:18:05:48:SJ cbx_altera_mult_add_rtl 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//synthesis_resources = altera_mult_add_rtl 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module complex_mult_altera_mult_add_5e4g
(
aclr0,
clock0,
dataa,
datab,
ena0,
ena1,
ena2,
ena3,
result) ;
input aclr0;
input clock0;
input [63:0] dataa;
input [19:0] datab;
input ena0;
input ena1;
input ena2;
input ena3;
output [41:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr0;
tri1 clock0;
tri0 [63:0] dataa;
tri0 [19:0] datab;
tri1 ena0;
tri1 ena1;
tri1 ena2;
tri1 ena3;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [41:0] wire_altera_mult_add_rtl4_result;
altera_mult_add_rtl altera_mult_add_rtl4
(
.aclr0(aclr0),
.chainout_sat_overflow(),
.clock0(clock0),
.dataa(dataa),
.datab(datab),
.ena0(ena0),
.ena1(ena1),
.ena2(ena2),
.ena3(ena3),
.mult0_is_saturated(),
.mult1_is_saturated(),
.mult2_is_saturated(),
.mult3_is_saturated(),
.overflow(),
.result(wire_altera_mult_add_rtl4_result),
.scanouta(),
.scanoutb(),
.accum_sload(1'b0),
.aclr1(1'b0),
.aclr2(1'b0),
.aclr3(1'b0),
.addnsub1(1'b1),
.addnsub1_round(1'b0),
.addnsub3(1'b1),
.addnsub3_round(1'b0),
.chainin({1{1'b0}}),
.chainout_round(1'b0),
.chainout_saturate(1'b0),
.clock1(1'b1),
.clock2(1'b1),
.clock3(1'b1),
.coefsel0({3{1'b0}}),
.coefsel1({3{1'b0}}),
.coefsel2({3{1'b0}}),
.coefsel3({3{1'b0}}),
.datac({44{1'b0}}),
.mult01_round(1'b0),
.mult01_saturation(1'b0),
.mult23_round(1'b0),
.mult23_saturation(1'b0),
.output_round(1'b0),
.output_saturate(1'b0),
.rotate(1'b0),
.scanina({32{1'b0}}),
.scaninb({10{1'b0}}),
.shift_right(1'b0),
.signa(1'b0),
.signb(1'b0),
.sload_accum(1'b0),
.sourcea({2{1'b0}}),
.sourceb({2{1'b0}}),
.zero_chainout(1'b0),
.zero_loopback(1'b0)
);
defparam
altera_mult_add_rtl4.accum_direction = "ADD",
altera_mult_add_rtl4.accum_sload_aclr = "ACLR0",
altera_mult_add_rtl4.accum_sload_latency_aclr = "NONE",
altera_mult_add_rtl4.accum_sload_latency_clock = "UNREGISTERED",
altera_mult_add_rtl4.accum_sload_register = "CLOCK0",
altera_mult_add_rtl4.accumulator = "NO",
altera_mult_add_rtl4.adder1_rounding = "NO",
altera_mult_add_rtl4.adder3_rounding = "NO",
altera_mult_add_rtl4.addnsub1_round_aclr = "ACLR0",
altera_mult_add_rtl4.addnsub1_round_pipeline_aclr = "ACLR0",
altera_mult_add_rtl4.addnsub1_round_pipeline_register = "CLOCK0",
altera_mult_add_rtl4.addnsub1_round_register = "CLOCK0",
altera_mult_add_rtl4.addnsub3_round_aclr = "ACLR0",
altera_mult_add_rtl4.addnsub3_round_pipeline_aclr = "ACLR0",
altera_mult_add_rtl4.addnsub3_round_pipeline_register = "CLOCK0",
altera_mult_add_rtl4.addnsub3_round_register = "CLOCK0",
altera_mult_add_rtl4.addnsub_multiplier_aclr1 = "ACLR0",
altera_mult_add_rtl4.addnsub_multiplier_aclr3 = "ACLR0",
altera_mult_add_rtl4.addnsub_multiplier_latency_aclr1 = "NONE",
altera_mult_add_rtl4.addnsub_multiplier_latency_aclr3 = "NONE",
altera_mult_add_rtl4.addnsub_multiplier_latency_clock1 = "UNREGISTERED",
altera_mult_add_rtl4.addnsub_multiplier_latency_clock3 = "UNREGISTERED",
altera_mult_add_rtl4.addnsub_multiplier_register1 = "CLOCK0",
altera_mult_add_rtl4.addnsub_multiplier_register3 = "CLOCK0",
altera_mult_add_rtl4.chainout_aclr = "ACLR0",
altera_mult_add_rtl4.chainout_adder = "NO",
altera_mult_add_rtl4.chainout_register = "CLOCK0",
altera_mult_add_rtl4.chainout_round_aclr = "ACLR0",
altera_mult_add_rtl4.chainout_round_output_aclr = "ACLR0",
altera_mult_add_rtl4.chainout_round_output_register = "CLOCK0",
altera_mult_add_rtl4.chainout_round_pipeline_aclr = "ACLR0",
altera_mult_add_rtl4.chainout_round_pipeline_register = "CLOCK0",
altera_mult_add_rtl4.chainout_round_register = "CLOCK0",
altera_mult_add_rtl4.chainout_rounding = "NO",
altera_mult_add_rtl4.chainout_saturate_aclr = "ACLR0",
altera_mult_add_rtl4.chainout_saturate_output_aclr = "ACLR0",
altera_mult_add_rtl4.chainout_saturate_output_register = "CLOCK0",
altera_mult_add_rtl4.chainout_saturate_pipeline_aclr = "ACLR0",
altera_mult_add_rtl4.chainout_saturate_pipeline_register = "CLOCK0",
altera_mult_add_rtl4.chainout_saturate_register = "CLOCK0",
altera_mult_add_rtl4.chainout_saturation = "NO",
altera_mult_add_rtl4.coef0_0 = 0,
altera_mult_add_rtl4.coef0_1 = 0,
altera_mult_add_rtl4.coef0_2 = 0,
altera_mult_add_rtl4.coef0_3 = 0,
altera_mult_add_rtl4.coef0_4 = 0,
altera_mult_add_rtl4.coef0_5 = 0,
altera_mult_add_rtl4.coef0_6 = 0,
altera_mult_add_rtl4.coef0_7 = 0,
altera_mult_add_rtl4.coef1_0 = 0,
altera_mult_add_rtl4.coef1_1 = 0,
altera_mult_add_rtl4.coef1_2 = 0,
altera_mult_add_rtl4.coef1_3 = 0,
altera_mult_add_rtl4.coef1_4 = 0,
altera_mult_add_rtl4.coef1_5 = 0,
altera_mult_add_rtl4.coef1_6 = 0,
altera_mult_add_rtl4.coef1_7 = 0,
altera_mult_add_rtl4.coef2_0 = 0,
altera_mult_add_rtl4.coef2_1 = 0,
altera_mult_add_rtl4.coef2_2 = 0,
altera_mult_add_rtl4.coef2_3 = 0,
altera_mult_add_rtl4.coef2_4 = 0,
altera_mult_add_rtl4.coef2_5 = 0,
altera_mult_add_rtl4.coef2_6 = 0,
altera_mult_add_rtl4.coef2_7 = 0,
altera_mult_add_rtl4.coef3_0 = 0,
altera_mult_add_rtl4.coef3_1 = 0,
altera_mult_add_rtl4.coef3_2 = 0,
altera_mult_add_rtl4.coef3_3 = 0,
altera_mult_add_rtl4.coef3_4 = 0,
altera_mult_add_rtl4.coef3_5 = 0,
altera_mult_add_rtl4.coef3_6 = 0,
altera_mult_add_rtl4.coef3_7 = 0,
altera_mult_add_rtl4.coefsel0_aclr = "ACLR0",
altera_mult_add_rtl4.coefsel0_latency_aclr = "NONE",
altera_mult_add_rtl4.coefsel0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl4.coefsel0_register = "CLOCK0",
altera_mult_add_rtl4.coefsel1_aclr = "ACLR0",
altera_mult_add_rtl4.coefsel1_latency_aclr = "NONE",
altera_mult_add_rtl4.coefsel1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl4.coefsel1_register = "CLOCK0",
altera_mult_add_rtl4.coefsel2_aclr = "ACLR0",
altera_mult_add_rtl4.coefsel2_latency_aclr = "NONE",
altera_mult_add_rtl4.coefsel2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl4.coefsel2_register = "CLOCK0",
altera_mult_add_rtl4.coefsel3_aclr = "ACLR0",
altera_mult_add_rtl4.coefsel3_latency_aclr = "NONE",
altera_mult_add_rtl4.coefsel3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl4.coefsel3_register = "CLOCK0",
altera_mult_add_rtl4.dedicated_multiplier_circuitry = "AUTO",
altera_mult_add_rtl4.double_accum = "NO",
altera_mult_add_rtl4.dsp_block_balancing = "Auto",
altera_mult_add_rtl4.extra_latency = 0,
altera_mult_add_rtl4.input_a0_latency_aclr = "NONE",
altera_mult_add_rtl4.input_a0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl4.input_a1_latency_aclr = "NONE",
altera_mult_add_rtl4.input_a1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl4.input_a2_latency_aclr = "NONE",
altera_mult_add_rtl4.input_a2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl4.input_a3_latency_aclr = "NONE",
altera_mult_add_rtl4.input_a3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl4.input_aclr_a0 = "ACLR0",
altera_mult_add_rtl4.input_aclr_a1 = "ACLR0",
altera_mult_add_rtl4.input_aclr_a2 = "ACLR0",
altera_mult_add_rtl4.input_aclr_a3 = "ACLR0",
altera_mult_add_rtl4.input_aclr_b0 = "ACLR0",
altera_mult_add_rtl4.input_aclr_b1 = "ACLR0",
altera_mult_add_rtl4.input_aclr_b2 = "ACLR0",
altera_mult_add_rtl4.input_aclr_b3 = "ACLR0",
altera_mult_add_rtl4.input_aclr_c0 = "ACLR0",
altera_mult_add_rtl4.input_aclr_c1 = "ACLR0",
altera_mult_add_rtl4.input_aclr_c2 = "ACLR0",
altera_mult_add_rtl4.input_aclr_c3 = "ACLR0",
altera_mult_add_rtl4.input_b0_latency_aclr = "NONE",
altera_mult_add_rtl4.input_b0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl4.input_b1_latency_aclr = "NONE",
altera_mult_add_rtl4.input_b1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl4.input_b2_latency_aclr = "NONE",
altera_mult_add_rtl4.input_b2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl4.input_b3_latency_aclr = "NONE",
altera_mult_add_rtl4.input_b3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl4.input_c0_latency_aclr = "NONE",
altera_mult_add_rtl4.input_c0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl4.input_c1_latency_aclr = "NONE",
altera_mult_add_rtl4.input_c1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl4.input_c2_latency_aclr = "NONE",
altera_mult_add_rtl4.input_c2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl4.input_c3_latency_aclr = "NONE",
altera_mult_add_rtl4.input_c3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl4.input_register_a0 = "CLOCK0",
altera_mult_add_rtl4.input_register_a1 = "CLOCK0",
altera_mult_add_rtl4.input_register_a2 = "CLOCK0",
altera_mult_add_rtl4.input_register_a3 = "CLOCK0",
altera_mult_add_rtl4.input_register_b0 = "CLOCK0",
altera_mult_add_rtl4.input_register_b1 = "CLOCK0",
altera_mult_add_rtl4.input_register_b2 = "CLOCK0",
altera_mult_add_rtl4.input_register_b3 = "CLOCK0",
altera_mult_add_rtl4.input_register_c0 = "CLOCK0",
altera_mult_add_rtl4.input_register_c1 = "CLOCK0",
altera_mult_add_rtl4.input_register_c2 = "CLOCK0",
altera_mult_add_rtl4.input_register_c3 = "CLOCK0",
altera_mult_add_rtl4.input_source_a0 = "DATAA",
altera_mult_add_rtl4.input_source_a1 = "DATAA",
altera_mult_add_rtl4.input_source_a2 = "DATAA",
altera_mult_add_rtl4.input_source_a3 = "DATAA",
altera_mult_add_rtl4.input_source_b0 = "DATAB",
altera_mult_add_rtl4.input_source_b1 = "DATAB",
altera_mult_add_rtl4.input_source_b2 = "DATAB",
altera_mult_add_rtl4.input_source_b3 = "DATAB",
altera_mult_add_rtl4.latency = 0,
altera_mult_add_rtl4.loadconst_control_aclr = "ACLR0",
altera_mult_add_rtl4.loadconst_control_register = "CLOCK0",
altera_mult_add_rtl4.loadconst_value = 64,
altera_mult_add_rtl4.mult01_round_aclr = "ACLR0",
altera_mult_add_rtl4.mult01_round_register = "CLOCK0",
altera_mult_add_rtl4.mult01_saturation_aclr = "ACLR1",
altera_mult_add_rtl4.mult01_saturation_register = "CLOCK0",
altera_mult_add_rtl4.mult23_round_aclr = "ACLR0",
altera_mult_add_rtl4.mult23_round_register = "CLOCK0",
altera_mult_add_rtl4.mult23_saturation_aclr = "ACLR0",
altera_mult_add_rtl4.mult23_saturation_register = "CLOCK0",
altera_mult_add_rtl4.multiplier01_rounding = "NO",
altera_mult_add_rtl4.multiplier01_saturation = "NO",
altera_mult_add_rtl4.multiplier1_direction = "ADD",
altera_mult_add_rtl4.multiplier23_rounding = "NO",
altera_mult_add_rtl4.multiplier23_saturation = "NO",
altera_mult_add_rtl4.multiplier3_direction = "ADD",
altera_mult_add_rtl4.multiplier_aclr0 = "ACLR0",
altera_mult_add_rtl4.multiplier_aclr1 = "ACLR0",
altera_mult_add_rtl4.multiplier_aclr2 = "ACLR0",
altera_mult_add_rtl4.multiplier_aclr3 = "ACLR0",
altera_mult_add_rtl4.multiplier_register0 = "CLOCK0",
altera_mult_add_rtl4.multiplier_register1 = "CLOCK0",
altera_mult_add_rtl4.multiplier_register2 = "CLOCK0",
altera_mult_add_rtl4.multiplier_register3 = "CLOCK0",
altera_mult_add_rtl4.number_of_multipliers = 2,
altera_mult_add_rtl4.output_aclr = "ACLR0",
altera_mult_add_rtl4.output_register = "CLOCK0",
altera_mult_add_rtl4.output_round_aclr = "ACLR0",
altera_mult_add_rtl4.output_round_pipeline_aclr = "ACLR0",
altera_mult_add_rtl4.output_round_pipeline_register = "CLOCK0",
altera_mult_add_rtl4.output_round_register = "CLOCK0",
altera_mult_add_rtl4.output_round_type = "NEAREST_INTEGER",
altera_mult_add_rtl4.output_rounding = "NO",
altera_mult_add_rtl4.output_saturate_aclr = "ACLR0",
altera_mult_add_rtl4.output_saturate_pipeline_aclr = "ACLR0",
altera_mult_add_rtl4.output_saturate_pipeline_register = "CLOCK0",
altera_mult_add_rtl4.output_saturate_register = "CLOCK0",
altera_mult_add_rtl4.output_saturate_type = "ASYMMETRIC",
altera_mult_add_rtl4.output_saturation = "NO",
altera_mult_add_rtl4.port_addnsub1 = "PORT_UNUSED",
altera_mult_add_rtl4.port_addnsub3 = "PORT_UNUSED",
altera_mult_add_rtl4.port_chainout_sat_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl4.port_output_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl4.port_signa = "PORT_UNUSED",
altera_mult_add_rtl4.port_signb = "PORT_UNUSED",
altera_mult_add_rtl4.preadder_direction_0 = "ADD",
altera_mult_add_rtl4.preadder_direction_1 = "ADD",
altera_mult_add_rtl4.preadder_direction_2 = "ADD",
altera_mult_add_rtl4.preadder_direction_3 = "ADD",
altera_mult_add_rtl4.preadder_mode = "SIMPLE",
altera_mult_add_rtl4.representation_a = "SIGNED",
altera_mult_add_rtl4.representation_b = "SIGNED",
altera_mult_add_rtl4.rotate_aclr = "ACLR0",
altera_mult_add_rtl4.rotate_output_aclr = "ACLR0",
altera_mult_add_rtl4.rotate_output_register = "CLOCK0",
altera_mult_add_rtl4.rotate_pipeline_aclr = "ACLR0",
altera_mult_add_rtl4.rotate_pipeline_register = "CLOCK0",
altera_mult_add_rtl4.rotate_register = "CLOCK0",
altera_mult_add_rtl4.scanouta_aclr = "ACLR0",
altera_mult_add_rtl4.scanouta_register = "UNREGISTERED",
altera_mult_add_rtl4.selected_device_family = "Cyclone V",
altera_mult_add_rtl4.shift_mode = "NO",
altera_mult_add_rtl4.shift_right_aclr = "ACLR0",
altera_mult_add_rtl4.shift_right_output_aclr = "ACLR0",
altera_mult_add_rtl4.shift_right_output_register = "CLOCK0",
altera_mult_add_rtl4.shift_right_pipeline_aclr = "ACLR0",
altera_mult_add_rtl4.shift_right_pipeline_register = "CLOCK0",
altera_mult_add_rtl4.shift_right_register = "CLOCK0",
altera_mult_add_rtl4.signed_aclr_a = "ACLR0",
altera_mult_add_rtl4.signed_aclr_b = "ACLR0",
altera_mult_add_rtl4.signed_latency_aclr_a = "NONE",
altera_mult_add_rtl4.signed_latency_aclr_b = "NONE",
altera_mult_add_rtl4.signed_latency_clock_a = "UNREGISTERED",
altera_mult_add_rtl4.signed_latency_clock_b = "UNREGISTERED",
altera_mult_add_rtl4.signed_register_a = "CLOCK0",
altera_mult_add_rtl4.signed_register_b = "CLOCK0",
altera_mult_add_rtl4.systolic_aclr1 = "ACLR0",
altera_mult_add_rtl4.systolic_aclr3 = "ACLR0",
altera_mult_add_rtl4.systolic_delay1 = "UNREGISTERED",
altera_mult_add_rtl4.systolic_delay3 = "UNREGISTERED",
altera_mult_add_rtl4.use_sload_accum_port = "NO",
altera_mult_add_rtl4.width_a = 32,
altera_mult_add_rtl4.width_b = 10,
altera_mult_add_rtl4.width_c = 22,
altera_mult_add_rtl4.width_chainin = 1,
altera_mult_add_rtl4.width_coef = 18,
altera_mult_add_rtl4.width_msb = 17,
altera_mult_add_rtl4.width_result = 42,
altera_mult_add_rtl4.width_saturate_sign = 1,
altera_mult_add_rtl4.zero_chainout_output_aclr = "ACLR0",
altera_mult_add_rtl4.zero_chainout_output_register = "CLOCK0",
altera_mult_add_rtl4.zero_loopback_aclr = "ACLR0",
altera_mult_add_rtl4.zero_loopback_output_aclr = "ACLR0",
altera_mult_add_rtl4.zero_loopback_output_register = "CLOCK0",
altera_mult_add_rtl4.zero_loopback_pipeline_aclr = "ACLR0",
altera_mult_add_rtl4.zero_loopback_pipeline_register = "CLOCK0",
altera_mult_add_rtl4.zero_loopback_register = "CLOCK0",
altera_mult_add_rtl4.lpm_type = "altera_mult_add_rtl";
assign
result = wire_altera_mult_add_rtl4_result;
endmodule //complex_mult_altera_mult_add_5e4g
//synthesis_resources = altera_mult_add_rtl 1 dsp_mac 2 reg 42
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module complex_mult_mult_add_eqt1
(
aclr0,
clock0,
dataa,
datab,
ena0,
result) ;
input aclr0;
input clock0;
input [63:0] dataa;
input [19:0] datab;
input ena0;
output [41:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr0;
tri1 clock0;
tri0 [63:0] dataa;
tri0 [19:0] datab;
tri1 ena0;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [41:0] wire_altera_mult_add3_result;
wire ena1;
wire ena2;
wire ena3;
complex_mult_altera_mult_add_5e4g altera_mult_add3
(
.aclr0(aclr0),
.clock0(clock0),
.dataa(dataa),
.datab(datab),
.ena0(ena0),
.ena1(ena1),
.ena2(ena2),
.ena3(ena3),
.result(wire_altera_mult_add3_result));
assign
ena1 = 1'b1,
ena2 = 1'b1,
ena3 = 1'b1,
result = wire_altera_mult_add3_result;
endmodule //complex_mult_mult_add_eqt1
//synthesis_resources = altera_mult_add_rtl 2 dsp_mac 4 reg 84
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module complex_mult_altmult_complex_ifp
(
aclr,
clock,
dataa_imag,
dataa_real,
datab_imag,
datab_real,
result_imag,
result_real) ;
input aclr;
input clock;
input [31:0] dataa_imag;
input [31:0] dataa_real;
input [9:0] datab_imag;
input [9:0] datab_real;
output [41:0] result_imag;
output [41:0] result_real;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [41:0] wire_mult_add1_result;
wire [41:0] wire_mult_add2_result;
wire ena;
wire [63:0] mult_add1_inputa;
wire [19:0] mult_add1_inputb;
wire [19:0] mult_add2_inputb;
complex_mult_mult_add_frt1 mult_add1
(
.aclr0(aclr),
.clock0(clock),
.dataa(mult_add1_inputa),
.datab(mult_add1_inputb),
.ena0(ena),
.result(wire_mult_add1_result));
complex_mult_mult_add_eqt1 mult_add2
(
.aclr0(aclr),
.clock0(clock),
.dataa(mult_add1_inputa),
.datab(mult_add2_inputb),
.ena0(ena),
.result(wire_mult_add2_result));
assign
ena = 1'b1,
mult_add1_inputa = {dataa_imag[31:0], dataa_real[31:0]},
mult_add1_inputb = {datab_imag[9:0], datab_real[9:0]},
mult_add2_inputb = {datab_real[9:0], datab_imag[9:0]},
result_imag = wire_mult_add2_result,
result_real = wire_mult_add1_result;
endmodule //complex_mult_altmult_complex_ifp
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module complex_mult (
aclr,
clock,
dataa_imag,
dataa_real,
datab_imag,
datab_real,
result_imag,
result_real);
input aclr;
input clock;
input [31:0] dataa_imag;
input [31:0] dataa_real;
input [9:0] datab_imag;
input [9:0] datab_real;
output [41:0] result_imag;
output [41:0] result_real;
wire [41:0] sub_wire0;
wire [41:0] sub_wire1;
wire [41:0] result_imag = sub_wire0[41:0];
wire [41:0] result_real = sub_wire1[41:0];
complex_mult_altmult_complex_ifp complex_mult_altmult_complex_ifp_component (
.aclr (aclr),
.clock (clock),
.dataa_imag (dataa_imag),
.dataa_real (dataa_real),
.datab_imag (datab_imag),
.datab_real (datab_real),
.result_imag (sub_wire0),
.result_real (sub_wire1));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: IMPLEMENTATION_STYLE STRING "AUTO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "3"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "SIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "SIGNED"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "42"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa_imag 0 0 32 0 INPUT NODEFVAL "dataa_imag[31..0]"
// Retrieval info: USED_PORT: dataa_real 0 0 32 0 INPUT NODEFVAL "dataa_real[31..0]"
// Retrieval info: USED_PORT: datab_imag 0 0 10 0 INPUT NODEFVAL "datab_imag[9..0]"
// Retrieval info: USED_PORT: datab_real 0 0 10 0 INPUT NODEFVAL "datab_real[9..0]"
// Retrieval info: USED_PORT: result_imag 0 0 42 0 OUTPUT NODEFVAL "result_imag[41..0]"
// Retrieval info: USED_PORT: result_real 0 0 42 0 OUTPUT NODEFVAL "result_real[41..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa_imag 0 0 32 0 dataa_imag 0 0 32 0
// Retrieval info: CONNECT: @dataa_real 0 0 32 0 dataa_real 0 0 32 0
// Retrieval info: CONNECT: @datab_imag 0 0 10 0 datab_imag 0 0 10 0
// Retrieval info: CONNECT: @datab_real 0 0 10 0 datab_real 0 0 10 0
// Retrieval info: CONNECT: result_imag 0 0 42 0 @result_imag 0 0 42 0
// Retrieval info: CONNECT: result_real 0 0 42 0 @result_real 0 0 42 0
// Retrieval info: GEN_FILE: TYPE_NORMAL complex_mult.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL complex_mult.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL complex_mult.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL complex_mult.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL complex_mult_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL complex_mult_bb.v FALSE
// Retrieval info: LIB_FILE: altera_lnsim
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="filesystem_encrypt,hls_ip_2017_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xczu9eg-ffvb1156-1-i-es1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.750000,HLS_SYN_LAT=78850,HLS_SYN_TPT=none,HLS_SYN_MEM=116,HLS_SYN_DSP=0,HLS_SYN_FF=7073,HLS_SYN_LUT=17302}" *)
module filesystem_encrypt (
ap_clk,
ap_rst_n,
ap_start,
ap_done,
ap_idle,
ap_ready,
m_axi_buffer_V_AWVALID,
m_axi_buffer_V_AWREADY,
m_axi_buffer_V_AWADDR,
m_axi_buffer_V_AWID,
m_axi_buffer_V_AWLEN,
m_axi_buffer_V_AWSIZE,
m_axi_buffer_V_AWBURST,
m_axi_buffer_V_AWLOCK,
m_axi_buffer_V_AWCACHE,
m_axi_buffer_V_AWPROT,
m_axi_buffer_V_AWQOS,
m_axi_buffer_V_AWREGION,
m_axi_buffer_V_AWUSER,
m_axi_buffer_V_WVALID,
m_axi_buffer_V_WREADY,
m_axi_buffer_V_WDATA,
m_axi_buffer_V_WSTRB,
m_axi_buffer_V_WLAST,
m_axi_buffer_V_WID,
m_axi_buffer_V_WUSER,
m_axi_buffer_V_ARVALID,
m_axi_buffer_V_ARREADY,
m_axi_buffer_V_ARADDR,
m_axi_buffer_V_ARID,
m_axi_buffer_V_ARLEN,
m_axi_buffer_V_ARSIZE,
m_axi_buffer_V_ARBURST,
m_axi_buffer_V_ARLOCK,
m_axi_buffer_V_ARCACHE,
m_axi_buffer_V_ARPROT,
m_axi_buffer_V_ARQOS,
m_axi_buffer_V_ARREGION,
m_axi_buffer_V_ARUSER,
m_axi_buffer_V_RVALID,
m_axi_buffer_V_RREADY,
m_axi_buffer_V_RDATA,
m_axi_buffer_V_RLAST,
m_axi_buffer_V_RID,
m_axi_buffer_V_RUSER,
m_axi_buffer_V_RRESP,
m_axi_buffer_V_BVALID,
m_axi_buffer_V_BREADY,
m_axi_buffer_V_BRESP,
m_axi_buffer_V_BID,
m_axi_buffer_V_BUSER,
key_V,
s_axi_AXILiteS_AWVALID,
s_axi_AXILiteS_AWREADY,
s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_WVALID,
s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB,
s_axi_AXILiteS_ARVALID,
s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_ARADDR,
s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY,
s_axi_AXILiteS_RDATA,
s_axi_AXILiteS_RRESP,
s_axi_AXILiteS_BVALID,
s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_BRESP
);
parameter ap_ST_fsm_state1 = 79'd1;
parameter ap_ST_fsm_pp0_stage0 = 79'd2;
parameter ap_ST_fsm_pp0_stage1 = 79'd4;
parameter ap_ST_fsm_pp0_stage2 = 79'd8;
parameter ap_ST_fsm_pp0_stage3 = 79'd16;
parameter ap_ST_fsm_pp0_stage4 = 79'd32;
parameter ap_ST_fsm_pp0_stage5 = 79'd64;
parameter ap_ST_fsm_pp0_stage6 = 79'd128;
parameter ap_ST_fsm_pp0_stage7 = 79'd256;
parameter ap_ST_fsm_pp0_stage8 = 79'd512;
parameter ap_ST_fsm_pp0_stage9 = 79'd1024;
parameter ap_ST_fsm_pp0_stage10 = 79'd2048;
parameter ap_ST_fsm_pp0_stage11 = 79'd4096;
parameter ap_ST_fsm_pp0_stage12 = 79'd8192;
parameter ap_ST_fsm_pp0_stage13 = 79'd16384;
parameter ap_ST_fsm_pp0_stage14 = 79'd32768;
parameter ap_ST_fsm_pp0_stage15 = 79'd65536;
parameter ap_ST_fsm_pp0_stage16 = 79'd131072;
parameter ap_ST_fsm_pp0_stage17 = 79'd262144;
parameter ap_ST_fsm_pp0_stage18 = 79'd524288;
parameter ap_ST_fsm_pp0_stage19 = 79'd1048576;
parameter ap_ST_fsm_pp0_stage20 = 79'd2097152;
parameter ap_ST_fsm_pp0_stage21 = 79'd4194304;
parameter ap_ST_fsm_pp0_stage22 = 79'd8388608;
parameter ap_ST_fsm_pp0_stage23 = 79'd16777216;
parameter ap_ST_fsm_pp0_stage24 = 79'd33554432;
parameter ap_ST_fsm_pp0_stage25 = 79'd67108864;
parameter ap_ST_fsm_pp0_stage26 = 79'd134217728;
parameter ap_ST_fsm_pp0_stage27 = 79'd268435456;
parameter ap_ST_fsm_pp0_stage28 = 79'd536870912;
parameter ap_ST_fsm_pp0_stage29 = 79'd1073741824;
parameter ap_ST_fsm_pp0_stage30 = 79'd2147483648;
parameter ap_ST_fsm_pp0_stage31 = 79'd4294967296;
parameter ap_ST_fsm_pp0_stage32 = 79'd8589934592;
parameter ap_ST_fsm_pp0_stage33 = 79'd17179869184;
parameter ap_ST_fsm_pp0_stage34 = 79'd34359738368;
parameter ap_ST_fsm_pp0_stage35 = 79'd68719476736;
parameter ap_ST_fsm_pp0_stage36 = 79'd137438953472;
parameter ap_ST_fsm_pp0_stage37 = 79'd274877906944;
parameter ap_ST_fsm_pp0_stage38 = 79'd549755813888;
parameter ap_ST_fsm_pp0_stage39 = 79'd1099511627776;
parameter ap_ST_fsm_pp0_stage40 = 79'd2199023255552;
parameter ap_ST_fsm_pp0_stage41 = 79'd4398046511104;
parameter ap_ST_fsm_pp0_stage42 = 79'd8796093022208;
parameter ap_ST_fsm_pp0_stage43 = 79'd17592186044416;
parameter ap_ST_fsm_pp0_stage44 = 79'd35184372088832;
parameter ap_ST_fsm_pp0_stage45 = 79'd70368744177664;
parameter ap_ST_fsm_pp0_stage46 = 79'd140737488355328;
parameter ap_ST_fsm_pp0_stage47 = 79'd281474976710656;
parameter ap_ST_fsm_pp0_stage48 = 79'd562949953421312;
parameter ap_ST_fsm_pp0_stage49 = 79'd1125899906842624;
parameter ap_ST_fsm_pp0_stage50 = 79'd2251799813685248;
parameter ap_ST_fsm_pp0_stage51 = 79'd4503599627370496;
parameter ap_ST_fsm_pp0_stage52 = 79'd9007199254740992;
parameter ap_ST_fsm_pp0_stage53 = 79'd18014398509481984;
parameter ap_ST_fsm_pp0_stage54 = 79'd36028797018963968;
parameter ap_ST_fsm_pp0_stage55 = 79'd72057594037927936;
parameter ap_ST_fsm_pp0_stage56 = 79'd144115188075855872;
parameter ap_ST_fsm_pp0_stage57 = 79'd288230376151711744;
parameter ap_ST_fsm_pp0_stage58 = 79'd576460752303423488;
parameter ap_ST_fsm_pp0_stage59 = 79'd1152921504606846976;
parameter ap_ST_fsm_pp0_stage60 = 79'd2305843009213693952;
parameter ap_ST_fsm_pp0_stage61 = 79'd4611686018427387904;
parameter ap_ST_fsm_pp0_stage62 = 79'd9223372036854775808;
parameter ap_ST_fsm_pp0_stage63 = 79'd18446744073709551616;
parameter ap_ST_fsm_pp0_stage64 = 79'd36893488147419103232;
parameter ap_ST_fsm_pp0_stage65 = 79'd73786976294838206464;
parameter ap_ST_fsm_pp0_stage66 = 79'd147573952589676412928;
parameter ap_ST_fsm_pp0_stage67 = 79'd295147905179352825856;
parameter ap_ST_fsm_pp0_stage68 = 79'd590295810358705651712;
parameter ap_ST_fsm_pp0_stage69 = 79'd1180591620717411303424;
parameter ap_ST_fsm_pp0_stage70 = 79'd2361183241434822606848;
parameter ap_ST_fsm_pp0_stage71 = 79'd4722366482869645213696;
parameter ap_ST_fsm_pp0_stage72 = 79'd9444732965739290427392;
parameter ap_ST_fsm_pp0_stage73 = 79'd18889465931478580854784;
parameter ap_ST_fsm_pp0_stage74 = 79'd37778931862957161709568;
parameter ap_ST_fsm_pp0_stage75 = 79'd75557863725914323419136;
parameter ap_ST_fsm_pp0_stage76 = 79'd151115727451828646838272;
parameter ap_ST_fsm_state80 = 79'd302231454903657293676544;
parameter C_S_AXI_AXILITES_DATA_WIDTH = 32;
parameter C_S_AXI_AXILITES_ADDR_WIDTH = 6;
parameter C_S_AXI_DATA_WIDTH = 32;
parameter C_M_AXI_BUFFER_V_ID_WIDTH = 1;
parameter C_M_AXI_BUFFER_V_ADDR_WIDTH = 32;
parameter C_M_AXI_BUFFER_V_DATA_WIDTH = 128;
parameter C_M_AXI_BUFFER_V_AWUSER_WIDTH = 1;
parameter C_M_AXI_BUFFER_V_ARUSER_WIDTH = 1;
parameter C_M_AXI_BUFFER_V_WUSER_WIDTH = 1;
parameter C_M_AXI_BUFFER_V_RUSER_WIDTH = 1;
parameter C_M_AXI_BUFFER_V_BUSER_WIDTH = 1;
parameter C_M_AXI_BUFFER_V_TARGET_ADDR = 0;
parameter C_M_AXI_BUFFER_V_USER_VALUE = 0;
parameter C_M_AXI_BUFFER_V_PROT_VALUE = 0;
parameter C_M_AXI_BUFFER_V_CACHE_VALUE = 3;
parameter C_M_AXI_DATA_WIDTH = 32;
parameter C_S_AXI_AXILITES_WSTRB_WIDTH = (32 / 8);
parameter C_S_AXI_WSTRB_WIDTH = (32 / 8);
parameter C_M_AXI_BUFFER_V_WSTRB_WIDTH = (128 / 8);
parameter C_M_AXI_WSTRB_WIDTH = (32 / 8);
input ap_clk;
input ap_rst_n;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output m_axi_buffer_V_AWVALID;
input m_axi_buffer_V_AWREADY;
output [C_M_AXI_BUFFER_V_ADDR_WIDTH - 1:0] m_axi_buffer_V_AWADDR;
output [C_M_AXI_BUFFER_V_ID_WIDTH - 1:0] m_axi_buffer_V_AWID;
output [7:0] m_axi_buffer_V_AWLEN;
output [2:0] m_axi_buffer_V_AWSIZE;
output [1:0] m_axi_buffer_V_AWBURST;
output [1:0] m_axi_buffer_V_AWLOCK;
output [3:0] m_axi_buffer_V_AWCACHE;
output [2:0] m_axi_buffer_V_AWPROT;
output [3:0] m_axi_buffer_V_AWQOS;
output [3:0] m_axi_buffer_V_AWREGION;
output [C_M_AXI_BUFFER_V_AWUSER_WIDTH - 1:0] m_axi_buffer_V_AWUSER;
output m_axi_buffer_V_WVALID;
input m_axi_buffer_V_WREADY;
output [C_M_AXI_BUFFER_V_DATA_WIDTH - 1:0] m_axi_buffer_V_WDATA;
output [C_M_AXI_BUFFER_V_WSTRB_WIDTH - 1:0] m_axi_buffer_V_WSTRB;
output m_axi_buffer_V_WLAST;
output [C_M_AXI_BUFFER_V_ID_WIDTH - 1:0] m_axi_buffer_V_WID;
output [C_M_AXI_BUFFER_V_WUSER_WIDTH - 1:0] m_axi_buffer_V_WUSER;
output m_axi_buffer_V_ARVALID;
input m_axi_buffer_V_ARREADY;
output [C_M_AXI_BUFFER_V_ADDR_WIDTH - 1:0] m_axi_buffer_V_ARADDR;
output [C_M_AXI_BUFFER_V_ID_WIDTH - 1:0] m_axi_buffer_V_ARID;
output [7:0] m_axi_buffer_V_ARLEN;
output [2:0] m_axi_buffer_V_ARSIZE;
output [1:0] m_axi_buffer_V_ARBURST;
output [1:0] m_axi_buffer_V_ARLOCK;
output [3:0] m_axi_buffer_V_ARCACHE;
output [2:0] m_axi_buffer_V_ARPROT;
output [3:0] m_axi_buffer_V_ARQOS;
output [3:0] m_axi_buffer_V_ARREGION;
output [C_M_AXI_BUFFER_V_ARUSER_WIDTH - 1:0] m_axi_buffer_V_ARUSER;
input m_axi_buffer_V_RVALID;
output m_axi_buffer_V_RREADY;
input [C_M_AXI_BUFFER_V_DATA_WIDTH - 1:0] m_axi_buffer_V_RDATA;
input m_axi_buffer_V_RLAST;
input [C_M_AXI_BUFFER_V_ID_WIDTH - 1:0] m_axi_buffer_V_RID;
input [C_M_AXI_BUFFER_V_RUSER_WIDTH - 1:0] m_axi_buffer_V_RUSER;
input [1:0] m_axi_buffer_V_RRESP;
input m_axi_buffer_V_BVALID;
output m_axi_buffer_V_BREADY;
input [1:0] m_axi_buffer_V_BRESP;
input [C_M_AXI_BUFFER_V_ID_WIDTH - 1:0] m_axi_buffer_V_BID;
input [C_M_AXI_BUFFER_V_BUSER_WIDTH - 1:0] m_axi_buffer_V_BUSER;
input [127:0] key_V;
input s_axi_AXILiteS_AWVALID;
output s_axi_AXILiteS_AWREADY;
input [C_S_AXI_AXILITES_ADDR_WIDTH - 1:0] s_axi_AXILiteS_AWADDR;
input s_axi_AXILiteS_WVALID;
output s_axi_AXILiteS_WREADY;
input [C_S_AXI_AXILITES_DATA_WIDTH - 1:0] s_axi_AXILiteS_WDATA;
input [C_S_AXI_AXILITES_WSTRB_WIDTH - 1:0] s_axi_AXILiteS_WSTRB;
input s_axi_AXILiteS_ARVALID;
output s_axi_AXILiteS_ARREADY;
input [C_S_AXI_AXILITES_ADDR_WIDTH - 1:0] s_axi_AXILiteS_ARADDR;
output s_axi_AXILiteS_RVALID;
input s_axi_AXILiteS_RREADY;
output [C_S_AXI_AXILITES_DATA_WIDTH - 1:0] s_axi_AXILiteS_RDATA;
output [1:0] s_axi_AXILiteS_RRESP;
output s_axi_AXILiteS_BVALID;
input s_axi_AXILiteS_BREADY;
output [1:0] s_axi_AXILiteS_BRESP;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg ap_rst_n_inv;
(* fsm_encoding = "none" *) reg [78:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
wire [127:0] iv_V;
wire [31:0] length_r;
reg [31:0] length_r_preg;
wire length_r_ap_vld;
reg [31:0] length_r_in_sig;
reg length_r_ap_vld_preg;
reg length_r_ap_vld_in_sig;
reg buffer_V_blk_n_AR;
wire ap_CS_fsm_pp0_stage1;
reg ap_enable_reg_pp0_iter0;
wire ap_block_pp0_stage1_flag00000000;
reg [0:0] tmp_reg_1932;
reg buffer_V_blk_n_R;
wire ap_CS_fsm_pp0_stage8;
wire ap_block_pp0_stage8_flag00000000;
wire ap_CS_fsm_pp0_stage9;
wire ap_block_pp0_stage9_flag00000000;
wire ap_CS_fsm_pp0_stage10;
wire ap_block_pp0_stage10_flag00000000;
wire ap_CS_fsm_pp0_stage11;
wire ap_block_pp0_stage11_flag00000000;
wire ap_CS_fsm_pp0_stage12;
wire ap_block_pp0_stage12_flag00000000;
wire ap_CS_fsm_pp0_stage13;
wire ap_block_pp0_stage13_flag00000000;
wire ap_CS_fsm_pp0_stage14;
wire ap_block_pp0_stage14_flag00000000;
wire ap_CS_fsm_pp0_stage15;
wire ap_block_pp0_stage15_flag00000000;
wire ap_CS_fsm_pp0_stage16;
wire ap_block_pp0_stage16_flag00000000;
wire ap_CS_fsm_pp0_stage17;
wire ap_block_pp0_stage17_flag00000000;
wire ap_CS_fsm_pp0_stage18;
wire ap_block_pp0_stage18_flag00000000;
wire ap_CS_fsm_pp0_stage19;
wire ap_block_pp0_stage19_flag00000000;
wire ap_CS_fsm_pp0_stage20;
wire ap_block_pp0_stage20_flag00000000;
wire ap_CS_fsm_pp0_stage21;
wire ap_block_pp0_stage21_flag00000000;
wire ap_CS_fsm_pp0_stage22;
wire ap_block_pp0_stage22_flag00000000;
wire ap_CS_fsm_pp0_stage23;
wire ap_block_pp0_stage23_flag00000000;
wire ap_CS_fsm_pp0_stage24;
wire ap_block_pp0_stage24_flag00000000;
wire ap_CS_fsm_pp0_stage25;
wire ap_block_pp0_stage25_flag00000000;
wire ap_CS_fsm_pp0_stage26;
wire ap_block_pp0_stage26_flag00000000;
wire ap_CS_fsm_pp0_stage27;
wire ap_block_pp0_stage27_flag00000000;
wire ap_CS_fsm_pp0_stage28;
wire ap_block_pp0_stage28_flag00000000;
wire ap_CS_fsm_pp0_stage29;
wire ap_block_pp0_stage29_flag00000000;
wire ap_CS_fsm_pp0_stage30;
wire ap_block_pp0_stage30_flag00000000;
wire ap_CS_fsm_pp0_stage31;
wire ap_block_pp0_stage31_flag00000000;
wire ap_CS_fsm_pp0_stage32;
wire ap_block_pp0_stage32_flag00000000;
wire ap_CS_fsm_pp0_stage33;
wire ap_block_pp0_stage33_flag00000000;
wire ap_CS_fsm_pp0_stage34;
wire ap_block_pp0_stage34_flag00000000;
wire ap_CS_fsm_pp0_stage35;
wire ap_block_pp0_stage35_flag00000000;
wire ap_CS_fsm_pp0_stage36;
wire ap_block_pp0_stage36_flag00000000;
wire ap_CS_fsm_pp0_stage37;
wire ap_block_pp0_stage37_flag00000000;
wire ap_CS_fsm_pp0_stage38;
wire ap_block_pp0_stage38_flag00000000;
wire ap_CS_fsm_pp0_stage39;
wire ap_block_pp0_stage39_flag00000000;
reg buffer_V_blk_n_AW;
wire ap_CS_fsm_pp0_stage40;
wire ap_block_pp0_stage40_flag00000000;
reg buffer_V_blk_n_W;
wire ap_CS_fsm_pp0_stage41;
wire ap_block_pp0_stage41_flag00000000;
wire ap_CS_fsm_pp0_stage42;
wire ap_block_pp0_stage42_flag00000000;
wire ap_CS_fsm_pp0_stage43;
wire ap_block_pp0_stage43_flag00000000;
wire ap_CS_fsm_pp0_stage44;
wire ap_block_pp0_stage44_flag00000000;
wire ap_CS_fsm_pp0_stage45;
wire ap_block_pp0_stage45_flag00000000;
wire ap_CS_fsm_pp0_stage46;
wire ap_block_pp0_stage46_flag00000000;
wire ap_CS_fsm_pp0_stage47;
wire ap_block_pp0_stage47_flag00000000;
wire ap_CS_fsm_pp0_stage48;
wire ap_block_pp0_stage48_flag00000000;
wire ap_CS_fsm_pp0_stage49;
wire ap_block_pp0_stage49_flag00000000;
wire ap_CS_fsm_pp0_stage50;
wire ap_block_pp0_stage50_flag00000000;
wire ap_CS_fsm_pp0_stage51;
wire ap_block_pp0_stage51_flag00000000;
wire ap_CS_fsm_pp0_stage52;
wire ap_block_pp0_stage52_flag00000000;
wire ap_CS_fsm_pp0_stage53;
wire ap_block_pp0_stage53_flag00000000;
wire ap_CS_fsm_pp0_stage54;
wire ap_block_pp0_stage54_flag00000000;
wire ap_CS_fsm_pp0_stage55;
wire ap_block_pp0_stage55_flag00000000;
wire ap_CS_fsm_pp0_stage56;
wire ap_block_pp0_stage56_flag00000000;
wire ap_CS_fsm_pp0_stage57;
wire ap_block_pp0_stage57_flag00000000;
wire ap_CS_fsm_pp0_stage58;
wire ap_block_pp0_stage58_flag00000000;
wire ap_CS_fsm_pp0_stage59;
wire ap_block_pp0_stage59_flag00000000;
wire ap_CS_fsm_pp0_stage60;
wire ap_block_pp0_stage60_flag00000000;
wire ap_CS_fsm_pp0_stage61;
wire ap_block_pp0_stage61_flag00000000;
wire ap_CS_fsm_pp0_stage62;
wire ap_block_pp0_stage62_flag00000000;
wire ap_CS_fsm_pp0_stage63;
wire ap_block_pp0_stage63_flag00000000;
wire ap_CS_fsm_pp0_stage64;
wire ap_block_pp0_stage64_flag00000000;
wire ap_CS_fsm_pp0_stage65;
wire ap_block_pp0_stage65_flag00000000;
wire ap_CS_fsm_pp0_stage66;
wire ap_block_pp0_stage66_flag00000000;
wire ap_CS_fsm_pp0_stage67;
wire ap_block_pp0_stage67_flag00000000;
wire ap_CS_fsm_pp0_stage68;
wire ap_block_pp0_stage68_flag00000000;
wire ap_CS_fsm_pp0_stage69;
wire ap_block_pp0_stage69_flag00000000;
wire ap_CS_fsm_pp0_stage70;
wire ap_block_pp0_stage70_flag00000000;
wire ap_CS_fsm_pp0_stage71;
wire ap_block_pp0_stage71_flag00000000;
wire ap_CS_fsm_pp0_stage72;
wire ap_block_pp0_stage72_flag00000000;
reg buffer_V_blk_n_B;
wire ap_CS_fsm_pp0_stage0;
reg ap_enable_reg_pp0_iter1;
wire ap_block_pp0_stage0_flag00000000;
reg length_r_blk_n;
reg buffer_V_AWVALID;
wire buffer_V_AWREADY;
reg buffer_V_WVALID;
wire buffer_V_WREADY;
reg [127:0] buffer_V_WDATA;
reg buffer_V_ARVALID;
wire buffer_V_ARREADY;
wire [31:0] buffer_V_ARADDR;
wire buffer_V_RVALID;
reg buffer_V_RREADY;
wire [127:0] buffer_V_RDATA;
wire buffer_V_RLAST;
wire [0:0] buffer_V_RID;
wire [0:0] buffer_V_RUSER;
wire [1:0] buffer_V_RRESP;
wire buffer_V_BVALID;
reg buffer_V_BREADY;
wire [1:0] buffer_V_BRESP;
wire [0:0] buffer_V_BID;
wire [0:0] buffer_V_BUSER;
reg [15:0] i_op_assign_reg_732;
reg [127:0] reg_752;
reg ap_block_state10_pp0_stage8_iter0;
reg ap_block_pp0_stage8_flag00011001;
reg ap_block_state13_pp0_stage11_iter0;
reg ap_block_pp0_stage11_flag00011001;
reg ap_block_state16_pp0_stage14_iter0;
reg ap_block_pp0_stage14_flag00011001;
reg ap_block_state19_pp0_stage17_iter0;
reg ap_block_pp0_stage17_flag00011001;
reg ap_block_state22_pp0_stage20_iter0;
reg ap_block_pp0_stage20_flag00011001;
reg ap_block_state25_pp0_stage23_iter0;
reg ap_block_pp0_stage23_flag00011001;
reg ap_block_state28_pp0_stage26_iter0;
reg ap_block_pp0_stage26_flag00011001;
reg ap_block_state31_pp0_stage29_iter0;
reg ap_block_pp0_stage29_flag00011001;
reg ap_block_state34_pp0_stage32_iter0;
reg ap_block_pp0_stage32_flag00011001;
reg ap_block_state37_pp0_stage35_iter0;
reg ap_block_pp0_stage35_flag00011001;
reg ap_block_state40_pp0_stage38_iter0;
reg ap_block_pp0_stage38_flag00011001;
reg [127:0] reg_756;
reg ap_block_state11_pp0_stage9_iter0;
reg ap_block_pp0_stage9_flag00011001;
reg ap_block_state14_pp0_stage12_iter0;
reg ap_block_pp0_stage12_flag00011001;
reg ap_block_state17_pp0_stage15_iter0;
reg ap_block_pp0_stage15_flag00011001;
reg ap_block_state20_pp0_stage18_iter0;
reg ap_block_pp0_stage18_flag00011001;
reg ap_block_state23_pp0_stage21_iter0;
reg ap_block_pp0_stage21_flag00011001;
reg ap_block_state26_pp0_stage24_iter0;
reg ap_block_pp0_stage24_flag00011001;
reg ap_block_state29_pp0_stage27_iter0;
reg ap_block_pp0_stage27_flag00011001;
reg ap_block_state32_pp0_stage30_iter0;
reg ap_block_pp0_stage30_flag00011001;
reg ap_block_state35_pp0_stage33_iter0;
reg ap_block_pp0_stage33_flag00011001;
reg ap_block_state38_pp0_stage36_iter0;
reg ap_block_pp0_stage36_flag00011001;
reg ap_block_state41_pp0_stage39_iter0;
reg ap_block_pp0_stage39_flag00011001;
reg [127:0] reg_760;
reg ap_block_state12_pp0_stage10_iter0;
reg ap_block_pp0_stage10_flag00011001;
reg ap_block_state15_pp0_stage13_iter0;
reg ap_block_pp0_stage13_flag00011001;
reg ap_block_state18_pp0_stage16_iter0;
reg ap_block_pp0_stage16_flag00011001;
reg ap_block_state21_pp0_stage19_iter0;
reg ap_block_pp0_stage19_flag00011001;
reg ap_block_state24_pp0_stage22_iter0;
reg ap_block_pp0_stage22_flag00011001;
reg ap_block_state27_pp0_stage25_iter0;
reg ap_block_pp0_stage25_flag00011001;
reg ap_block_state30_pp0_stage28_iter0;
reg ap_block_pp0_stage28_flag00011001;
reg ap_block_state33_pp0_stage31_iter0;
reg ap_block_pp0_stage31_flag00011001;
reg ap_block_state36_pp0_stage34_iter0;
reg ap_block_pp0_stage34_flag00011001;
reg ap_block_state39_pp0_stage37_iter0;
reg ap_block_pp0_stage37_flag00011001;
wire [127:0] buffer_temp_out_V_q1;
reg [127:0] reg_764;
wire [127:0] buffer_temp_out_V_q0;
wire ap_block_state43_pp0_stage41_iter0;
reg ap_sig_ioackin_buffer_V_WREADY;
reg ap_block_state43_io;
reg ap_block_pp0_stage41_flag00011001;
reg [127:0] reg_770;
wire ap_block_state44_pp0_stage42_iter0;
reg ap_block_state44_io;
reg ap_block_pp0_stage42_flag00011001;
reg [127:0] reg_775;
wire ap_block_state45_pp0_stage43_iter0;
reg ap_block_state45_io;
reg ap_block_pp0_stage43_flag00011001;
reg [127:0] reg_780;
wire ap_block_state46_pp0_stage44_iter0;
reg ap_block_state46_io;
reg ap_block_pp0_stage44_flag00011001;
reg ap_block_state1;
wire [0:0] tmp_fu_809_p3;
wire ap_block_state2_pp0_stage0_iter0;
reg ap_block_state79_pp0_stage0_iter1;
reg ap_block_pp0_stage0_flag00011001;
wire [0:0] tmp_66_fu_821_p2;
reg [0:0] tmp_66_reg_1936;
wire [14:0] tmp_98_fu_826_p1;
reg [14:0] tmp_98_reg_1940;
wire ap_block_state3_pp0_stage1_iter0;
reg ap_sig_ioackin_buffer_V_ARREADY;
reg ap_block_state3_io;
reg ap_block_pp0_stage1_flag00011001;
wire [63:0] tmp_1_fu_830_p1;
reg [63:0] tmp_1_reg_1974;
reg [31:0] buffer_V_addr_reg_1979;
wire [14:0] tmp_4_fu_841_p2;
reg [14:0] tmp_4_reg_1985;
wire [0:0] tmp_5_1_fu_861_p2;
reg [0:0] tmp_5_1_reg_1991;
wire [14:0] tmp_6_fu_866_p2;
reg [14:0] tmp_6_reg_1995;
wire ap_CS_fsm_pp0_stage2;
wire ap_block_state4_pp0_stage2_iter0;
wire ap_block_pp0_stage2_flag00011001;
wire [0:0] tmp_5_2_fu_884_p2;
reg [0:0] tmp_5_2_reg_2001;
wire [14:0] tmp_8_fu_889_p2;
reg [14:0] tmp_8_reg_2005;
wire ap_CS_fsm_pp0_stage3;
wire ap_block_state5_pp0_stage3_iter0;
wire ap_block_pp0_stage3_flag00011001;
wire [0:0] tmp_5_3_fu_907_p2;
reg [0:0] tmp_5_3_reg_2011;
wire [14:0] tmp_s_fu_912_p2;
reg [14:0] tmp_s_reg_2015;
wire ap_CS_fsm_pp0_stage4;
wire ap_block_state6_pp0_stage4_iter0;
wire ap_block_pp0_stage4_flag00011001;
wire [0:0] tmp_5_4_fu_930_p2;
reg [0:0] tmp_5_4_reg_2021;
wire [14:0] tmp_11_fu_935_p2;
reg [14:0] tmp_11_reg_2025;
wire ap_CS_fsm_pp0_stage5;
wire ap_block_state7_pp0_stage5_iter0;
wire ap_block_pp0_stage5_flag00011001;
wire [0:0] tmp_5_5_fu_953_p2;
reg [0:0] tmp_5_5_reg_2031;
wire [14:0] tmp_13_fu_958_p2;
reg [14:0] tmp_13_reg_2035;
wire ap_CS_fsm_pp0_stage6;
wire ap_block_state8_pp0_stage6_iter0;
wire ap_block_pp0_stage6_flag00011001;
wire [0:0] tmp_5_6_fu_976_p2;
reg [0:0] tmp_5_6_reg_2041;
wire [14:0] tmp_15_fu_981_p2;
reg [14:0] tmp_15_reg_2045;
wire ap_CS_fsm_pp0_stage7;
wire ap_block_state9_pp0_stage7_iter0;
wire ap_block_pp0_stage7_flag00011001;
wire [0:0] tmp_5_7_fu_999_p2;
reg [0:0] tmp_5_7_reg_2051;
wire [14:0] tmp_17_fu_1004_p2;
reg [14:0] tmp_17_reg_2055;
wire [0:0] tmp_5_8_fu_1022_p2;
reg [0:0] tmp_5_8_reg_2061;
wire [14:0] tmp_19_fu_1027_p2;
reg [14:0] tmp_19_reg_2065;
wire [0:0] tmp_5_9_fu_1045_p2;
reg [0:0] tmp_5_9_reg_2071;
wire [14:0] tmp_21_fu_1050_p2;
reg [14:0] tmp_21_reg_2075;
wire [0:0] tmp_5_s_fu_1068_p2;
reg [0:0] tmp_5_s_reg_2081;
wire [14:0] tmp_23_fu_1073_p2;
reg [14:0] tmp_23_reg_2085;
wire [14:0] tmp_25_fu_1082_p2;
reg [14:0] tmp_25_reg_2091;
wire [14:0] tmp_27_fu_1091_p2;
reg [14:0] tmp_27_reg_2097;
wire [14:0] tmp_29_fu_1100_p2;
reg [14:0] tmp_29_reg_2103;
wire [14:0] tmp_31_fu_1109_p2;
reg [14:0] tmp_31_reg_2109;
wire [14:0] tmp_33_fu_1118_p2;
reg [14:0] tmp_33_reg_2115;
wire [14:0] tmp_35_fu_1127_p2;
reg [14:0] tmp_35_reg_2121;
wire [14:0] tmp_37_fu_1136_p2;
reg [14:0] tmp_37_reg_2127;
wire [14:0] tmp_39_fu_1145_p2;
reg [14:0] tmp_39_reg_2133;
wire [14:0] tmp_41_fu_1154_p2;
reg [14:0] tmp_41_reg_2139;
wire [14:0] tmp_43_fu_1163_p2;
reg [14:0] tmp_43_reg_2145;
wire [14:0] tmp_45_fu_1172_p2;
reg [14:0] tmp_45_reg_2151;
wire [14:0] tmp_47_fu_1181_p2;
reg [14:0] tmp_47_reg_2157;
wire [14:0] tmp_49_fu_1190_p2;
reg [14:0] tmp_49_reg_2163;
wire [14:0] tmp_51_fu_1199_p2;
reg [14:0] tmp_51_reg_2169;
wire [14:0] tmp_53_fu_1208_p2;
reg [14:0] tmp_53_reg_2175;
wire [14:0] tmp_55_fu_1217_p2;
reg [14:0] tmp_55_reg_2181;
wire [14:0] tmp_57_fu_1226_p2;
reg [14:0] tmp_57_reg_2187;
wire [14:0] tmp_59_fu_1235_p2;
reg [14:0] tmp_59_reg_2193;
wire [14:0] tmp_61_fu_1244_p2;
reg [14:0] tmp_61_reg_2199;
wire [14:0] tmp_63_fu_1253_p2;
reg [14:0] tmp_63_reg_2205;
wire [0:0] tmp_5_10_fu_1271_p2;
reg [0:0] tmp_5_10_reg_2211;
wire [0:0] tmp_5_11_fu_1276_p2;
reg [0:0] tmp_5_11_reg_2215;
wire [0:0] tmp_5_12_fu_1281_p2;
reg [0:0] tmp_5_12_reg_2219;
wire [0:0] tmp_5_13_fu_1286_p2;
reg [0:0] tmp_5_13_reg_2223;
wire [0:0] tmp_5_14_fu_1291_p2;
reg [0:0] tmp_5_14_reg_2227;
wire [0:0] tmp_5_15_fu_1296_p2;
reg [0:0] tmp_5_15_reg_2231;
wire [0:0] tmp_5_16_fu_1301_p2;
reg [0:0] tmp_5_16_reg_2235;
wire [0:0] tmp_5_17_fu_1306_p2;
reg [0:0] tmp_5_17_reg_2239;
wire [0:0] tmp_5_18_fu_1311_p2;
reg [0:0] tmp_5_18_reg_2243;
wire [0:0] tmp_5_19_fu_1316_p2;
reg [0:0] tmp_5_19_reg_2247;
wire [0:0] tmp_5_20_fu_1321_p2;
reg [0:0] tmp_5_20_reg_2251;
wire [0:0] tmp_5_21_fu_1326_p2;
reg [0:0] tmp_5_21_reg_2255;
wire [0:0] tmp_5_22_fu_1331_p2;
reg [0:0] tmp_5_22_reg_2259;
wire [0:0] tmp_5_23_fu_1336_p2;
reg [0:0] tmp_5_23_reg_2263;
wire [0:0] tmp_5_24_fu_1341_p2;
reg [0:0] tmp_5_24_reg_2267;
wire [0:0] tmp_5_25_fu_1346_p2;
reg [0:0] tmp_5_25_reg_2271;
wire [0:0] tmp_5_26_fu_1351_p2;
reg [0:0] tmp_5_26_reg_2275;
wire [0:0] tmp_5_27_fu_1356_p2;
reg [0:0] tmp_5_27_reg_2279;
wire [0:0] tmp_5_28_fu_1361_p2;
reg [0:0] tmp_5_28_reg_2283;
wire [0:0] tmp_5_29_fu_1366_p2;
reg [0:0] tmp_5_29_reg_2287;
wire [0:0] tmp_5_30_fu_1371_p2;
reg [0:0] tmp_5_30_reg_2291;
wire [15:0] i_fu_1389_p2;
reg [15:0] i_reg_2295;
reg [127:0] buffer_temp_out_V_lo_4_reg_2300;
reg [127:0] buffer_temp_out_V_lo_5_reg_2305;
reg [127:0] buffer_temp_out_V_lo_6_reg_2310;
reg [127:0] buffer_temp_out_V_lo_7_reg_2315;
reg [127:0] buffer_temp_out_V_lo_8_reg_2320;
reg [127:0] buffer_temp_out_V_lo_9_reg_2325;
reg [127:0] buffer_temp_out_V_lo_10_reg_2330;
reg [127:0] buffer_temp_out_V_lo_11_reg_2335;
reg [127:0] buffer_temp_out_V_lo_12_reg_2340;
reg [127:0] buffer_temp_out_V_lo_13_reg_2345;
reg [127:0] buffer_temp_out_V_lo_14_reg_2350;
reg [127:0] buffer_temp_out_V_lo_15_reg_2355;
reg [127:0] buffer_temp_out_V_lo_16_reg_2360;
reg [127:0] buffer_temp_out_V_lo_17_reg_2365;
reg [127:0] buffer_temp_out_V_lo_18_reg_2370;
reg [127:0] buffer_temp_out_V_lo_19_reg_2375;
reg [127:0] buffer_temp_out_V_lo_20_reg_2380;
reg [127:0] buffer_temp_out_V_lo_21_reg_2385;
reg [127:0] buffer_temp_out_V_lo_22_reg_2390;
reg [127:0] buffer_temp_out_V_lo_23_reg_2395;
reg [127:0] buffer_temp_out_V_lo_24_reg_2400;
reg [127:0] buffer_temp_out_V_lo_25_reg_2405;
reg [127:0] buffer_temp_out_V_lo_26_reg_2410;
reg [127:0] buffer_temp_out_V_lo_27_reg_2415;
wire ap_block_state42_pp0_stage40_iter0;
reg ap_sig_ioackin_buffer_V_AWREADY;
reg ap_block_state42_io;
reg ap_block_pp0_stage40_flag00011001;
reg ap_block_pp0_stage0_flag00011011;
reg ap_condition_pp0_exit_iter0_state2;
wire ap_block_state78_pp0_stage76_iter0;
wire ap_block_pp0_stage76_flag00011011;
wire ap_CS_fsm_pp0_stage76;
reg [4:0] buffer_temp_out_V_address0;
reg buffer_temp_out_V_ce0;
reg buffer_temp_out_V_we0;
reg [127:0] buffer_temp_out_V_d0;
reg [4:0] buffer_temp_out_V_address1;
reg buffer_temp_out_V_ce1;
reg buffer_temp_out_V_we1;
reg [127:0] buffer_temp_out_V_d1;
wire grp_aestest_fu_744_ap_start;
wire grp_aestest_fu_744_ap_done;
wire grp_aestest_fu_744_ap_idle;
wire grp_aestest_fu_744_ap_ready;
reg grp_aestest_fu_744_ap_ce;
reg [127:0] grp_aestest_fu_744_inptext_V_read;
wire [127:0] grp_aestest_fu_744_ap_return;
reg ap_predicate_op143_call_state3;
reg ap_predicate_op307_call_state13;
reg ap_predicate_op152_call_state4;
reg ap_predicate_op370_call_state14;
reg ap_predicate_op162_call_state5;
reg ap_predicate_op392_call_state15;
reg ap_predicate_op173_call_state6;
reg ap_predicate_op414_call_state16;
reg ap_predicate_op185_call_state7;
reg ap_predicate_op436_call_state17;
reg ap_predicate_op198_call_state8;
reg ap_predicate_op458_call_state18;
reg ap_predicate_op212_call_state9;
reg ap_predicate_op480_call_state19;
reg ap_predicate_op227_call_state10;
reg ap_predicate_op502_call_state20;
reg ap_predicate_op243_call_state11;
reg ap_predicate_op524_call_state21;
reg ap_predicate_op260_call_state12;
reg ap_predicate_op546_call_state22;
reg ap_predicate_op324_call_state13;
reg ap_predicate_op568_call_state23;
reg ap_predicate_op387_call_state14;
reg ap_predicate_op590_call_state24;
reg ap_predicate_op409_call_state15;
reg ap_predicate_op612_call_state25;
reg ap_predicate_op431_call_state16;
reg ap_predicate_op634_call_state26;
reg ap_predicate_op453_call_state17;
reg ap_predicate_op656_call_state27;
reg ap_predicate_op475_call_state18;
reg ap_predicate_op678_call_state28;
reg ap_predicate_op497_call_state19;
reg ap_predicate_op700_call_state29;
reg ap_predicate_op519_call_state20;
reg ap_predicate_op722_call_state30;
reg ap_predicate_op541_call_state21;
reg ap_predicate_op744_call_state31;
reg ap_predicate_op563_call_state22;
reg ap_predicate_op766_call_state32;
reg ap_predicate_op585_call_state23;
reg ap_predicate_op788_call_state33;
reg ap_predicate_op607_call_state24;
reg ap_predicate_op810_call_state34;
reg ap_predicate_op629_call_state25;
reg ap_predicate_op832_call_state35;
reg ap_predicate_op651_call_state26;
reg ap_predicate_op851_call_state36;
reg ap_predicate_op673_call_state27;
reg ap_predicate_op869_call_state37;
reg ap_predicate_op695_call_state28;
reg ap_predicate_op886_call_state38;
reg ap_predicate_op717_call_state29;
reg ap_predicate_op902_call_state39;
reg ap_predicate_op739_call_state30;
reg ap_predicate_op917_call_state40;
reg ap_predicate_op761_call_state31;
reg ap_predicate_op931_call_state41;
reg ap_predicate_op783_call_state32;
reg ap_predicate_op943_call_state42;
reg ap_predicate_op805_call_state33;
reg ap_predicate_op955_call_state43;
reg ap_predicate_op827_call_state34;
reg ap_predicate_op969_call_state44;
reg [15:0] i_op_assign_phi_fu_736_p4;
reg ap_reg_grp_aestest_fu_744_ap_start;
reg ap_predicate_op143_call_state3_state2;
reg ap_predicate_op152_call_state4_state3;
reg ap_predicate_op162_call_state5_state4;
reg ap_predicate_op173_call_state6_state5;
reg ap_predicate_op185_call_state7_state6;
reg ap_predicate_op198_call_state8_state7;
reg ap_predicate_op212_call_state9_state8;
reg ap_predicate_op227_call_state10_state9;
reg ap_predicate_op243_call_state11_state10;
reg ap_predicate_op260_call_state12_state11;
reg ap_predicate_op324_call_state13_state12;
reg ap_predicate_op387_call_state14_state13;
reg ap_predicate_op409_call_state15_state14;
reg ap_predicate_op431_call_state16_state15;
reg ap_predicate_op453_call_state17_state16;
reg ap_predicate_op475_call_state18_state17;
reg ap_predicate_op497_call_state19_state18;
reg ap_predicate_op519_call_state20_state19;
reg ap_predicate_op541_call_state21_state20;
reg ap_predicate_op563_call_state22_state21;
reg ap_predicate_op585_call_state23_state22;
reg ap_predicate_op607_call_state24_state23;
reg ap_predicate_op629_call_state25_state24;
reg ap_predicate_op651_call_state26_state25;
reg ap_predicate_op673_call_state27_state26;
reg ap_predicate_op695_call_state28_state27;
reg ap_predicate_op717_call_state29_state28;
reg ap_predicate_op739_call_state30_state29;
reg ap_predicate_op761_call_state31_state30;
reg ap_predicate_op783_call_state32_state31;
reg ap_predicate_op805_call_state33_state32;
reg ap_predicate_op827_call_state34_state33;
wire [127:0] counter_V_fu_855_p2;
wire [127:0] counter_V_0_1_fu_878_p2;
wire ap_block_pp0_stage2_flag00000000;
wire [127:0] counter_V_0_2_fu_901_p2;
wire ap_block_pp0_stage3_flag00000000;
wire [127:0] counter_V_0_3_fu_924_p2;
wire ap_block_pp0_stage4_flag00000000;
wire [127:0] counter_V_0_4_fu_947_p2;
wire ap_block_pp0_stage5_flag00000000;
wire [127:0] counter_V_0_5_fu_970_p2;
wire ap_block_pp0_stage6_flag00000000;
wire [127:0] counter_V_0_6_fu_993_p2;
wire ap_block_pp0_stage7_flag00000000;
wire [127:0] counter_V_0_7_fu_1016_p2;
wire [127:0] counter_V_0_8_fu_1039_p2;
wire [127:0] counter_V_0_9_fu_1062_p2;
wire [127:0] counter_V_0_s_fu_1265_p2;
wire [127:0] counter_V_0_10_fu_1383_p2;
wire [127:0] counter_V_0_11_fu_1402_p2;
wire [127:0] counter_V_0_12_fu_1415_p2;
wire [127:0] counter_V_0_13_fu_1428_p2;
wire [127:0] counter_V_0_14_fu_1441_p2;
wire [127:0] counter_V_0_15_fu_1454_p2;
wire [127:0] counter_V_0_16_fu_1467_p2;
wire [127:0] counter_V_0_17_fu_1480_p2;
wire [127:0] counter_V_0_18_fu_1493_p2;
wire [127:0] counter_V_0_19_fu_1506_p2;
wire [127:0] counter_V_0_20_fu_1519_p2;
wire [127:0] counter_V_0_21_fu_1532_p2;
wire [127:0] counter_V_0_22_fu_1545_p2;
wire [127:0] counter_V_0_23_fu_1558_p2;
wire [127:0] counter_V_0_24_fu_1571_p2;
wire [127:0] counter_V_0_25_fu_1584_p2;
wire [127:0] counter_V_0_26_fu_1597_p2;
wire [127:0] counter_V_0_27_fu_1610_p2;
wire [127:0] counter_V_0_28_fu_1623_p2;
wire [127:0] counter_V_0_29_fu_1636_p2;
wire [127:0] counter_V_0_30_fu_1649_p2;
wire [63:0] tmp_5_fu_1376_p1;
wire [63:0] tmp_7_fu_1395_p1;
wire [63:0] tmp_9_fu_1408_p1;
wire [63:0] tmp_10_fu_1421_p1;
wire [63:0] tmp_12_fu_1434_p1;
wire [63:0] tmp_14_fu_1447_p1;
wire [63:0] tmp_16_fu_1460_p1;
wire [63:0] tmp_18_fu_1473_p1;
wire [63:0] tmp_20_fu_1486_p1;
wire [63:0] tmp_22_fu_1499_p1;
wire [63:0] tmp_24_fu_1512_p1;
wire [63:0] tmp_26_fu_1525_p1;
wire [63:0] tmp_28_fu_1538_p1;
wire [63:0] tmp_30_fu_1551_p1;
wire [63:0] tmp_32_fu_1564_p1;
wire [63:0] tmp_34_fu_1577_p1;
wire [63:0] tmp_36_fu_1590_p1;
wire [63:0] tmp_38_fu_1603_p1;
wire [63:0] tmp_40_fu_1616_p1;
wire [63:0] tmp_42_fu_1629_p1;
wire [63:0] tmp_44_fu_1642_p1;
wire [63:0] tmp_46_fu_1655_p1;
wire [63:0] tmp_48_fu_1659_p1;
wire [63:0] tmp_50_fu_1663_p1;
wire [63:0] tmp_52_fu_1667_p1;
wire [63:0] tmp_54_fu_1671_p1;
wire [63:0] tmp_56_fu_1675_p1;
wire [63:0] tmp_58_fu_1679_p1;
wire [63:0] tmp_60_fu_1683_p1;
wire [63:0] tmp_62_fu_1687_p1;
wire [63:0] tmp_64_fu_1691_p1;
reg ap_reg_ioackin_buffer_V_ARREADY;
wire ap_block_pp0_stage1_flag00001001;
reg ap_reg_ioackin_buffer_V_AWREADY;
wire ap_block_pp0_stage40_flag00001001;
reg ap_reg_ioackin_buffer_V_WREADY;
wire ap_block_pp0_stage41_flag00001001;
wire ap_block_pp0_stage42_flag00001001;
wire ap_block_pp0_stage43_flag00001001;
wire ap_block_pp0_stage44_flag00001001;
wire ap_block_state47_pp0_stage45_iter0;
wire ap_block_pp0_stage45_flag00001001;
reg ap_block_state47_io;
reg ap_block_pp0_stage45_flag00011001;
wire ap_block_state48_pp0_stage46_iter0;
wire ap_block_pp0_stage46_flag00001001;
reg ap_block_state48_io;
reg ap_block_pp0_stage46_flag00011001;
wire ap_block_state49_pp0_stage47_iter0;
wire ap_block_pp0_stage47_flag00001001;
reg ap_block_state49_io;
reg ap_block_pp0_stage47_flag00011001;
wire ap_block_state50_pp0_stage48_iter0;
wire ap_block_pp0_stage48_flag00001001;
reg ap_block_state50_io;
reg ap_block_pp0_stage48_flag00011001;
wire ap_block_state51_pp0_stage49_iter0;
wire ap_block_pp0_stage49_flag00001001;
reg ap_block_state51_io;
reg ap_block_pp0_stage49_flag00011001;
wire ap_block_state52_pp0_stage50_iter0;
wire ap_block_pp0_stage50_flag00001001;
reg ap_block_state52_io;
reg ap_block_pp0_stage50_flag00011001;
wire ap_block_state53_pp0_stage51_iter0;
wire ap_block_pp0_stage51_flag00001001;
reg ap_block_state53_io;
reg ap_block_pp0_stage51_flag00011001;
wire ap_block_state54_pp0_stage52_iter0;
wire ap_block_pp0_stage52_flag00001001;
reg ap_block_state54_io;
reg ap_block_pp0_stage52_flag00011001;
wire ap_block_state55_pp0_stage53_iter0;
wire ap_block_pp0_stage53_flag00001001;
reg ap_block_state55_io;
reg ap_block_pp0_stage53_flag00011001;
wire ap_block_state56_pp0_stage54_iter0;
wire ap_block_pp0_stage54_flag00001001;
reg ap_block_state56_io;
reg ap_block_pp0_stage54_flag00011001;
wire ap_block_state57_pp0_stage55_iter0;
wire ap_block_pp0_stage55_flag00001001;
reg ap_block_state57_io;
reg ap_block_pp0_stage55_flag00011001;
wire ap_block_state58_pp0_stage56_iter0;
wire ap_block_pp0_stage56_flag00001001;
reg ap_block_state58_io;
reg ap_block_pp0_stage56_flag00011001;
wire ap_block_state59_pp0_stage57_iter0;
wire ap_block_pp0_stage57_flag00001001;
reg ap_block_state59_io;
reg ap_block_pp0_stage57_flag00011001;
wire ap_block_state60_pp0_stage58_iter0;
wire ap_block_pp0_stage58_flag00001001;
reg ap_block_state60_io;
reg ap_block_pp0_stage58_flag00011001;
wire ap_block_state61_pp0_stage59_iter0;
wire ap_block_pp0_stage59_flag00001001;
reg ap_block_state61_io;
reg ap_block_pp0_stage59_flag00011001;
wire ap_block_state62_pp0_stage60_iter0;
wire ap_block_pp0_stage60_flag00001001;
reg ap_block_state62_io;
reg ap_block_pp0_stage60_flag00011001;
wire ap_block_state63_pp0_stage61_iter0;
wire ap_block_pp0_stage61_flag00001001;
reg ap_block_state63_io;
reg ap_block_pp0_stage61_flag00011001;
wire ap_block_state64_pp0_stage62_iter0;
wire ap_block_pp0_stage62_flag00001001;
reg ap_block_state64_io;
reg ap_block_pp0_stage62_flag00011001;
wire ap_block_state65_pp0_stage63_iter0;
wire ap_block_pp0_stage63_flag00001001;
reg ap_block_state65_io;
reg ap_block_pp0_stage63_flag00011001;
wire ap_block_state66_pp0_stage64_iter0;
wire ap_block_pp0_stage64_flag00001001;
reg ap_block_state66_io;
reg ap_block_pp0_stage64_flag00011001;
wire ap_block_state67_pp0_stage65_iter0;
wire ap_block_pp0_stage65_flag00001001;
reg ap_block_state67_io;
reg ap_block_pp0_stage65_flag00011001;
wire ap_block_state68_pp0_stage66_iter0;
wire ap_block_pp0_stage66_flag00001001;
reg ap_block_state68_io;
reg ap_block_pp0_stage66_flag00011001;
wire ap_block_state69_pp0_stage67_iter0;
wire ap_block_pp0_stage67_flag00001001;
reg ap_block_state69_io;
reg ap_block_pp0_stage67_flag00011001;
wire ap_block_state70_pp0_stage68_iter0;
wire ap_block_pp0_stage68_flag00001001;
reg ap_block_state70_io;
reg ap_block_pp0_stage68_flag00011001;
wire ap_block_state71_pp0_stage69_iter0;
wire ap_block_pp0_stage69_flag00001001;
reg ap_block_state71_io;
reg ap_block_pp0_stage69_flag00011001;
wire ap_block_state72_pp0_stage70_iter0;
wire ap_block_pp0_stage70_flag00001001;
reg ap_block_state72_io;
reg ap_block_pp0_stage70_flag00011001;
wire ap_block_state73_pp0_stage71_iter0;
wire ap_block_pp0_stage71_flag00001001;
reg ap_block_state73_io;
reg ap_block_pp0_stage71_flag00011001;
wire ap_block_state74_pp0_stage72_iter0;
wire ap_block_pp0_stage72_flag00001001;
reg ap_block_state74_io;
reg ap_block_pp0_stage72_flag00011001;
wire [127:0] grp_fu_786_p2;
wire [127:0] grp_fu_794_p2;
wire [127:0] grp_fu_802_p2;
wire [31:0] i_op_assign_cast1_fu_817_p1;
wire [127:0] tmp_2_fu_851_p1;
wire [31:0] tmp_4_cast_fu_847_p1;
wire [127:0] tmp_8_cast_6_fu_875_p1;
wire [31:0] tmp_6_cast_fu_871_p1;
wire [127:0] tmp_8_1_cast_fu_898_p1;
wire [31:0] tmp_8_cast_fu_894_p1;
wire [127:0] tmp_8_2_cast_fu_921_p1;
wire [31:0] tmp_cast_fu_917_p1;
wire [127:0] tmp_8_3_cast_fu_944_p1;
wire [31:0] tmp_11_cast_fu_940_p1;
wire [127:0] tmp_8_4_cast_fu_967_p1;
wire [31:0] tmp_13_cast_fu_963_p1;
wire [127:0] tmp_8_5_cast_fu_990_p1;
wire [31:0] tmp_15_cast_fu_986_p1;
wire [127:0] tmp_8_6_cast_fu_1013_p1;
wire [31:0] tmp_17_cast_fu_1009_p1;
wire [127:0] tmp_8_7_cast_fu_1036_p1;
wire [31:0] tmp_19_cast_fu_1032_p1;
wire [127:0] tmp_8_8_cast_fu_1059_p1;
wire [31:0] tmp_21_cast_fu_1055_p1;
wire [127:0] tmp_8_9_cast_fu_1262_p1;
wire [31:0] tmp_23_cast_fu_1078_p1;
wire [31:0] tmp_25_cast_fu_1087_p1;
wire [31:0] tmp_27_cast_fu_1096_p1;
wire [31:0] tmp_29_cast_fu_1105_p1;
wire [31:0] tmp_31_cast_fu_1114_p1;
wire [31:0] tmp_33_cast_fu_1123_p1;
wire [31:0] tmp_35_cast_fu_1132_p1;
wire [31:0] tmp_37_cast_fu_1141_p1;
wire [31:0] tmp_39_cast_fu_1150_p1;
wire [31:0] tmp_41_cast_fu_1159_p1;
wire [31:0] tmp_43_cast_fu_1168_p1;
wire [31:0] tmp_45_cast_fu_1177_p1;
wire [31:0] tmp_47_cast_fu_1186_p1;
wire [31:0] tmp_49_cast_fu_1195_p1;
wire [31:0] tmp_51_cast_fu_1204_p1;
wire [31:0] tmp_53_cast_fu_1213_p1;
wire [31:0] tmp_55_cast_fu_1222_p1;
wire [31:0] tmp_57_cast_fu_1231_p1;
wire [31:0] tmp_59_cast_fu_1240_p1;
wire [31:0] tmp_61_cast_fu_1249_p1;
wire [31:0] tmp_63_cast_fu_1258_p1;
wire [127:0] tmp_8_10_cast_fu_1380_p1;
wire [127:0] tmp_8_11_cast_fu_1399_p1;
wire [127:0] tmp_8_12_cast_fu_1412_p1;
wire [127:0] tmp_8_13_cast_fu_1425_p1;
wire [127:0] tmp_8_14_cast_fu_1438_p1;
wire [127:0] tmp_8_15_cast_fu_1451_p1;
wire [127:0] tmp_8_16_cast_fu_1464_p1;
wire [127:0] tmp_8_17_cast_fu_1477_p1;
wire [127:0] tmp_8_18_cast_fu_1490_p1;
wire [127:0] tmp_8_19_cast_fu_1503_p1;
wire [127:0] tmp_8_20_cast_fu_1516_p1;
wire [127:0] tmp_8_21_cast_fu_1529_p1;
wire [127:0] tmp_8_22_cast_fu_1542_p1;
wire [127:0] tmp_8_23_cast_fu_1555_p1;
wire [127:0] tmp_8_24_cast_fu_1568_p1;
wire [127:0] tmp_8_25_cast_fu_1581_p1;
wire [127:0] tmp_8_26_cast_fu_1594_p1;
wire [127:0] tmp_8_27_cast_fu_1607_p1;
wire [127:0] tmp_8_28_cast_fu_1620_p1;
wire [127:0] tmp_8_29_cast_fu_1633_p1;
wire [127:0] tmp_8_30_cast_fu_1646_p1;
wire ap_CS_fsm_state80;
reg [78:0] ap_NS_fsm;
reg ap_block_pp0_stage1_flag00011011;
wire ap_block_pp0_stage2_flag00011011;
wire ap_block_pp0_stage3_flag00011011;
wire ap_block_pp0_stage4_flag00011011;
wire ap_block_pp0_stage5_flag00011011;
wire ap_block_pp0_stage6_flag00011011;
wire ap_block_pp0_stage7_flag00011011;
reg ap_block_pp0_stage8_flag00011011;
reg ap_block_pp0_stage9_flag00011011;
reg ap_block_pp0_stage10_flag00011011;
reg ap_block_pp0_stage11_flag00011011;
reg ap_block_pp0_stage12_flag00011011;
reg ap_block_pp0_stage13_flag00011011;
reg ap_block_pp0_stage14_flag00011011;
reg ap_block_pp0_stage15_flag00011011;
reg ap_block_pp0_stage16_flag00011011;
reg ap_block_pp0_stage17_flag00011011;
reg ap_block_pp0_stage18_flag00011011;
reg ap_block_pp0_stage19_flag00011011;
reg ap_block_pp0_stage20_flag00011011;
reg ap_block_pp0_stage21_flag00011011;
reg ap_block_pp0_stage22_flag00011011;
reg ap_block_pp0_stage23_flag00011011;
reg ap_block_pp0_stage24_flag00011011;
reg ap_block_pp0_stage25_flag00011011;
reg ap_block_pp0_stage26_flag00011011;
reg ap_block_pp0_stage27_flag00011011;
reg ap_block_pp0_stage28_flag00011011;
reg ap_block_pp0_stage29_flag00011011;
reg ap_block_pp0_stage30_flag00011011;
reg ap_block_pp0_stage31_flag00011011;
reg ap_block_pp0_stage32_flag00011011;
reg ap_block_pp0_stage33_flag00011011;
reg ap_block_pp0_stage34_flag00011011;
reg ap_block_pp0_stage35_flag00011011;
reg ap_block_pp0_stage36_flag00011011;
reg ap_block_pp0_stage37_flag00011011;
reg ap_block_pp0_stage38_flag00011011;
reg ap_block_pp0_stage39_flag00011011;
reg ap_block_pp0_stage40_flag00011011;
reg ap_block_pp0_stage41_flag00011011;
reg ap_block_pp0_stage42_flag00011011;
reg ap_block_pp0_stage43_flag00011011;
reg ap_block_pp0_stage44_flag00011011;
reg ap_block_pp0_stage45_flag00011011;
reg ap_block_pp0_stage46_flag00011011;
reg ap_block_pp0_stage47_flag00011011;
reg ap_block_pp0_stage48_flag00011011;
reg ap_block_pp0_stage49_flag00011011;
reg ap_block_pp0_stage50_flag00011011;
reg ap_block_pp0_stage51_flag00011011;
reg ap_block_pp0_stage52_flag00011011;
reg ap_block_pp0_stage53_flag00011011;
reg ap_block_pp0_stage54_flag00011011;
reg ap_block_pp0_stage55_flag00011011;
reg ap_block_pp0_stage56_flag00011011;
reg ap_block_pp0_stage57_flag00011011;
reg ap_block_pp0_stage58_flag00011011;
reg ap_block_pp0_stage59_flag00011011;
reg ap_block_pp0_stage60_flag00011011;
reg ap_block_pp0_stage61_flag00011011;
reg ap_block_pp0_stage62_flag00011011;
reg ap_block_pp0_stage63_flag00011011;
reg ap_block_pp0_stage64_flag00011011;
reg ap_block_pp0_stage65_flag00011011;
reg ap_block_pp0_stage66_flag00011011;
reg ap_block_pp0_stage67_flag00011011;
reg ap_block_pp0_stage68_flag00011011;
reg ap_block_pp0_stage69_flag00011011;
reg ap_block_pp0_stage70_flag00011011;
reg ap_block_pp0_stage71_flag00011011;
reg ap_block_pp0_stage72_flag00011011;
wire ap_block_state75_pp0_stage73_iter0;
wire ap_block_pp0_stage73_flag00011011;
wire ap_block_pp0_stage73_flag00011001;
wire ap_block_state76_pp0_stage74_iter0;
wire ap_block_pp0_stage74_flag00011011;
wire ap_block_pp0_stage74_flag00011001;
wire ap_block_state77_pp0_stage75_iter0;
wire ap_block_pp0_stage75_flag00011011;
wire ap_block_pp0_stage75_flag00011001;
wire ap_block_pp0_stage76_flag00011001;
reg ap_idle_pp0;
wire ap_enable_pp0;
reg ap_condition_7926;
reg ap_condition_7931;
reg ap_condition_7969;
reg ap_condition_7973;
reg ap_condition_7977;
reg ap_condition_7981;
reg ap_condition_7985;
reg ap_condition_7989;
reg ap_condition_7993;
reg ap_condition_7997;
reg ap_condition_8001;
reg ap_condition_8005;
reg ap_condition_8008;
reg ap_condition_8011;
reg ap_condition_8014;
reg ap_condition_8017;
reg ap_condition_8020;
reg ap_condition_8023;
reg ap_condition_8026;
reg ap_condition_8029;
reg ap_condition_8032;
reg ap_condition_8035;
reg ap_condition_8038;
reg ap_condition_8041;
reg ap_condition_8044;
reg ap_condition_8047;
reg ap_condition_8050;
reg ap_condition_8053;
reg ap_condition_8056;
reg ap_condition_8059;
reg ap_condition_8062;
reg ap_condition_8065;
reg ap_condition_8068;
reg ap_condition_8071;
// power-on initialization
initial begin
#0 ap_CS_fsm = 79'd1;
#0 length_r_preg = 32'd0;
#0 length_r_ap_vld_preg = 1'b0;
#0 ap_enable_reg_pp0_iter0 = 1'b0;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_reg_grp_aestest_fu_744_ap_start = 1'b0;
#0 ap_reg_ioackin_buffer_V_ARREADY = 1'b0;
#0 ap_reg_ioackin_buffer_V_AWREADY = 1'b0;
#0 ap_reg_ioackin_buffer_V_WREADY = 1'b0;
end
filesystem_encrypt_AXILiteS_s_axi #(
.C_S_AXI_ADDR_WIDTH( C_S_AXI_AXILITES_ADDR_WIDTH ),
.C_S_AXI_DATA_WIDTH( C_S_AXI_AXILITES_DATA_WIDTH ))
filesystem_encrypt_AXILiteS_s_axi_U(
.AWVALID(s_axi_AXILiteS_AWVALID),
.AWREADY(s_axi_AXILiteS_AWREADY),
.AWADDR(s_axi_AXILiteS_AWADDR),
.WVALID(s_axi_AXILiteS_WVALID),
.WREADY(s_axi_AXILiteS_WREADY),
.WDATA(s_axi_AXILiteS_WDATA),
.WSTRB(s_axi_AXILiteS_WSTRB),
.ARVALID(s_axi_AXILiteS_ARVALID),
.ARREADY(s_axi_AXILiteS_ARREADY),
.ARADDR(s_axi_AXILiteS_ARADDR),
.RVALID(s_axi_AXILiteS_RVALID),
.RREADY(s_axi_AXILiteS_RREADY),
.RDATA(s_axi_AXILiteS_RDATA),
.RRESP(s_axi_AXILiteS_RRESP),
.BVALID(s_axi_AXILiteS_BVALID),
.BREADY(s_axi_AXILiteS_BREADY),
.BRESP(s_axi_AXILiteS_BRESP),
.ACLK(ap_clk),
.ARESET(ap_rst_n_inv),
.ACLK_EN(1'b1),
.iv_V(iv_V),
.length_r(length_r),
.length_r_ap_vld(length_r_ap_vld)
);
filesystem_encrypt_buffer_V_m_axi #(
.USER_DW( 128 ),
.USER_AW( 32 ),
.USER_MAXREQS( 5 ),
.NUM_READ_OUTSTANDING( 16 ),
.NUM_WRITE_OUTSTANDING( 16 ),
.MAX_READ_BURST_LENGTH( 16 ),
.MAX_WRITE_BURST_LENGTH( 16 ),
.C_M_AXI_ID_WIDTH( C_M_AXI_BUFFER_V_ID_WIDTH ),
.C_M_AXI_ADDR_WIDTH( C_M_AXI_BUFFER_V_ADDR_WIDTH ),
.C_M_AXI_DATA_WIDTH( C_M_AXI_BUFFER_V_DATA_WIDTH ),
.C_M_AXI_AWUSER_WIDTH( C_M_AXI_BUFFER_V_AWUSER_WIDTH ),
.C_M_AXI_ARUSER_WIDTH( C_M_AXI_BUFFER_V_ARUSER_WIDTH ),
.C_M_AXI_WUSER_WIDTH( C_M_AXI_BUFFER_V_WUSER_WIDTH ),
.C_M_AXI_RUSER_WIDTH( C_M_AXI_BUFFER_V_RUSER_WIDTH ),
.C_M_AXI_BUSER_WIDTH( C_M_AXI_BUFFER_V_BUSER_WIDTH ),
.C_TARGET_ADDR( C_M_AXI_BUFFER_V_TARGET_ADDR ),
.C_USER_VALUE( C_M_AXI_BUFFER_V_USER_VALUE ),
.C_PROT_VALUE( C_M_AXI_BUFFER_V_PROT_VALUE ),
.C_CACHE_VALUE( C_M_AXI_BUFFER_V_CACHE_VALUE ))
filesystem_encrypt_buffer_V_m_axi_U(
.AWVALID(m_axi_buffer_V_AWVALID),
.AWREADY(m_axi_buffer_V_AWREADY),
.AWADDR(m_axi_buffer_V_AWADDR),
.AWID(m_axi_buffer_V_AWID),
.AWLEN(m_axi_buffer_V_AWLEN),
.AWSIZE(m_axi_buffer_V_AWSIZE),
.AWBURST(m_axi_buffer_V_AWBURST),
.AWLOCK(m_axi_buffer_V_AWLOCK),
.AWCACHE(m_axi_buffer_V_AWCACHE),
.AWPROT(m_axi_buffer_V_AWPROT),
.AWQOS(m_axi_buffer_V_AWQOS),
.AWREGION(m_axi_buffer_V_AWREGION),
.AWUSER(m_axi_buffer_V_AWUSER),
.WVALID(m_axi_buffer_V_WVALID),
.WREADY(m_axi_buffer_V_WREADY),
.WDATA(m_axi_buffer_V_WDATA),
.WSTRB(m_axi_buffer_V_WSTRB),
.WLAST(m_axi_buffer_V_WLAST),
.WID(m_axi_buffer_V_WID),
.WUSER(m_axi_buffer_V_WUSER),
.ARVALID(m_axi_buffer_V_ARVALID),
.ARREADY(m_axi_buffer_V_ARREADY),
.ARADDR(m_axi_buffer_V_ARADDR),
.ARID(m_axi_buffer_V_ARID),
.ARLEN(m_axi_buffer_V_ARLEN),
.ARSIZE(m_axi_buffer_V_ARSIZE),
.ARBURST(m_axi_buffer_V_ARBURST),
.ARLOCK(m_axi_buffer_V_ARLOCK),
.ARCACHE(m_axi_buffer_V_ARCACHE),
.ARPROT(m_axi_buffer_V_ARPROT),
.ARQOS(m_axi_buffer_V_ARQOS),
.ARREGION(m_axi_buffer_V_ARREGION),
.ARUSER(m_axi_buffer_V_ARUSER),
.RVALID(m_axi_buffer_V_RVALID),
.RREADY(m_axi_buffer_V_RREADY),
.RDATA(m_axi_buffer_V_RDATA),
.RLAST(m_axi_buffer_V_RLAST),
.RID(m_axi_buffer_V_RID),
.RUSER(m_axi_buffer_V_RUSER),
.RRESP(m_axi_buffer_V_RRESP),
.BVALID(m_axi_buffer_V_BVALID),
.BREADY(m_axi_buffer_V_BREADY),
.BRESP(m_axi_buffer_V_BRESP),
.BID(m_axi_buffer_V_BID),
.BUSER(m_axi_buffer_V_BUSER),
.ACLK(ap_clk),
.ARESET(ap_rst_n_inv),
.ACLK_EN(1'b1),
.I_ARVALID(buffer_V_ARVALID),
.I_ARREADY(buffer_V_ARREADY),
.I_ARADDR(buffer_V_ARADDR),
.I_ARID(1'd0),
.I_ARLEN(32'd32),
.I_ARSIZE(3'd0),
.I_ARLOCK(2'd0),
.I_ARCACHE(4'd0),
.I_ARQOS(4'd0),
.I_ARPROT(3'd0),
.I_ARUSER(1'd0),
.I_ARBURST(2'd0),
.I_ARREGION(4'd0),
.I_RVALID(buffer_V_RVALID),
.I_RREADY(buffer_V_RREADY),
.I_RDATA(buffer_V_RDATA),
.I_RID(buffer_V_RID),
.I_RUSER(buffer_V_RUSER),
.I_RRESP(buffer_V_RRESP),
.I_RLAST(buffer_V_RLAST),
.I_AWVALID(buffer_V_AWVALID),
.I_AWREADY(buffer_V_AWREADY),
.I_AWADDR(buffer_V_addr_reg_1979),
.I_AWID(1'd0),
.I_AWLEN(32'd32),
.I_AWSIZE(3'd0),
.I_AWLOCK(2'd0),
.I_AWCACHE(4'd0),
.I_AWQOS(4'd0),
.I_AWPROT(3'd0),
.I_AWUSER(1'd0),
.I_AWBURST(2'd0),
.I_AWREGION(4'd0),
.I_WVALID(buffer_V_WVALID),
.I_WREADY(buffer_V_WREADY),
.I_WDATA(buffer_V_WDATA),
.I_WID(1'd0),
.I_WUSER(1'd0),
.I_WLAST(1'b0),
.I_WSTRB(16'd65535),
.I_BVALID(buffer_V_BVALID),
.I_BREADY(buffer_V_BREADY),
.I_BRESP(buffer_V_BRESP),
.I_BID(buffer_V_BID),
.I_BUSER(buffer_V_BUSER)
);
filesystem_encrypbkb #(
.DataWidth( 128 ),
.AddressRange( 32 ),
.AddressWidth( 5 ))
buffer_temp_out_V_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.address0(buffer_temp_out_V_address0),
.ce0(buffer_temp_out_V_ce0),
.we0(buffer_temp_out_V_we0),
.d0(buffer_temp_out_V_d0),
.q0(buffer_temp_out_V_q0),
.address1(buffer_temp_out_V_address1),
.ce1(buffer_temp_out_V_ce1),
.we1(buffer_temp_out_V_we1),
.d1(buffer_temp_out_V_d1),
.q1(buffer_temp_out_V_q1)
);
aestest grp_aestest_fu_744(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.ap_start(grp_aestest_fu_744_ap_start),
.ap_done(grp_aestest_fu_744_ap_done),
.ap_idle(grp_aestest_fu_744_ap_idle),
.ap_ready(grp_aestest_fu_744_ap_ready),
.ap_ce(grp_aestest_fu_744_ap_ce),
.inptext_V_read(grp_aestest_fu_744_inptext_V_read),
.key_V_read(key_V),
.ap_return(grp_aestest_fu_744_ap_return)
);
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011011 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (1'b0 == length_r_ap_vld_in_sig)))) begin
ap_enable_reg_pp0_iter0 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end else begin
if (((1'b1 == ap_condition_pp0_exit_iter0_state2) & (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011011 == 1'b0)) | ((ap_block_pp0_stage76_flag00011011 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage76))))) begin
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 ^ 1'b1);
end else if ((((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011011 == 1'b0)) | ((ap_block_pp0_stage76_flag00011011 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage76)))) begin
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end else if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (1'b0 == length_r_ap_vld_in_sig)))) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_reg_grp_aestest_fu_744_ap_start <= 1'b0;
end else begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op143_call_state3_state2)) | ((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op152_call_state4_state3)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op162_call_state5_state4)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op173_call_state6_state5)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op185_call_state7_state6)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_block_pp0_stage5_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op198_call_state8_state7)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_block_pp0_stage6_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op212_call_state9_state8)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op227_call_state10_state9)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage8) & (ap_block_pp0_stage8_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op243_call_state11_state10)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op260_call_state12_state11)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op324_call_state13_state12)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op387_call_state14_state13)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op409_call_state15_state14)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op431_call_state16_state15)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op453_call_state17_state16)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op475_call_state18_state17)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage16) & (ap_block_pp0_stage16_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op497_call_state19_state18)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage17) & (ap_block_pp0_stage17_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op519_call_state20_state19)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage18) & (ap_block_pp0_stage18_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op541_call_state21_state20)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage19) & (ap_block_pp0_stage19_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op563_call_state22_state21)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage20) & (ap_block_pp0_stage20_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op585_call_state23_state22)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage21) & (ap_block_pp0_stage21_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op607_call_state24_state23)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage22) & (ap_block_pp0_stage22_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op629_call_state25_state24)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage23) & (ap_block_pp0_stage23_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op651_call_state26_state25)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage24) & (ap_block_pp0_stage24_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op673_call_state27_state26)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage25) & (ap_block_pp0_stage25_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op695_call_state28_state27)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage26) & (ap_block_pp0_stage26_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op717_call_state29_state28)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage27) & (ap_block_pp0_stage27_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op739_call_state30_state29)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage28) & (ap_block_pp0_stage28_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op761_call_state31_state30)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage29) & (ap_block_pp0_stage29_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op783_call_state32_state31)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage30) & (ap_block_pp0_stage30_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op805_call_state33_state32)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage31) & (ap_block_pp0_stage31_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op827_call_state34_state33)))) begin
ap_reg_grp_aestest_fu_744_ap_start <= 1'b1;
end else if ((1'b1 == grp_aestest_fu_744_ap_ready)) begin
ap_reg_grp_aestest_fu_744_ap_start <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ioackin_buffer_V_ARREADY <= 1'b0;
end else begin
if ((ap_condition_7926 == 1'b1)) begin
if ((ap_block_pp0_stage1_flag00011001 == 1'b0)) begin
ap_reg_ioackin_buffer_V_ARREADY <= 1'b0;
end else if (((1'b1 == buffer_V_ARREADY) & (ap_block_pp0_stage1_flag00001001 == 1'b0))) begin
ap_reg_ioackin_buffer_V_ARREADY <= 1'b1;
end
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ioackin_buffer_V_AWREADY <= 1'b0;
end else begin
if ((ap_condition_7931 == 1'b1)) begin
if ((ap_block_pp0_stage40_flag00011001 == 1'b0)) begin
ap_reg_ioackin_buffer_V_AWREADY <= 1'b0;
end else if (((1'b1 == buffer_V_AWREADY) & (ap_block_pp0_stage40_flag00001001 == 1'b0))) begin
ap_reg_ioackin_buffer_V_AWREADY <= 1'b1;
end
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ioackin_buffer_V_WREADY <= 1'b0;
end else begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage41) & (ap_block_pp0_stage41_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage42) & (ap_block_pp0_stage42_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage43) & (ap_block_pp0_stage43_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage44) & (ap_block_pp0_stage44_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage45) & (ap_block_pp0_stage45_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage46) & (ap_block_pp0_stage46_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage47) & (ap_block_pp0_stage47_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage48) & (ap_block_pp0_stage48_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage49) & (ap_block_pp0_stage49_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage50) & (ap_block_pp0_stage50_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage51) & (ap_block_pp0_stage51_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage52) & (ap_block_pp0_stage52_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage53) & (ap_block_pp0_stage53_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage54) & (ap_block_pp0_stage54_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage55) & (ap_block_pp0_stage55_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage56) & (ap_block_pp0_stage56_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage57) & (ap_block_pp0_stage57_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage58) & (ap_block_pp0_stage58_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage59) & (ap_block_pp0_stage59_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage60) & (ap_block_pp0_stage60_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage61) & (ap_block_pp0_stage61_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage62) & (ap_block_pp0_stage62_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage63) & (ap_block_pp0_stage63_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage64) & (ap_block_pp0_stage64_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage65) & (ap_block_pp0_stage65_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage66) & (ap_block_pp0_stage66_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage67) & (ap_block_pp0_stage67_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage68) & (ap_block_pp0_stage68_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage69) & (ap_block_pp0_stage69_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage70) & (ap_block_pp0_stage70_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage71) & (ap_block_pp0_stage71_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage72) & (ap_block_pp0_stage72_flag00011001 == 1'b0)))) begin
ap_reg_ioackin_buffer_V_WREADY <= 1'b0;
end else if ((((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage41) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage41_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage42) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage42_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage43) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage43_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage44) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage44_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage45) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage45_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage46) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage46_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage47) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage47_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage48) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage48_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage49) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage49_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage50) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage50_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage51) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage51_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage52) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage52_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage53) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage53_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage54) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage54_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage55) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage55_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage56) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage56_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage57) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage57_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage58) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage58_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage59) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage59_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage60) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage60_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage61) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage61_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage62) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage62_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage63) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage63_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage64) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage64_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage65) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage65_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage66) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage66_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage67) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage67_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage68) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage68_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage69) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage69_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage70) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage70_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage71) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage71_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage72) & (1'b1 == buffer_V_WREADY) & (ap_block_pp0_stage72_flag00001001 == 1'b0)))) begin
ap_reg_ioackin_buffer_V_WREADY <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
length_r_ap_vld_preg <= 1'b0;
end else begin
if ((1'b1 == ap_CS_fsm_state80)) begin
length_r_ap_vld_preg <= 1'b0;
end else if (((1'b1 == length_r_ap_vld) & ~((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1)))) begin
length_r_ap_vld_preg <= length_r_ap_vld;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
length_r_preg <= 32'd0;
end else begin
if (((1'b1 == length_r_ap_vld) & ~((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1)))) begin
length_r_preg <= length_r;
end
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
i_op_assign_reg_732 <= i_reg_2295;
end else if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (1'b0 == length_r_ap_vld_in_sig)))) begin
i_op_assign_reg_732 <= 16'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0))) begin
if (((1'b1 == ap_CS_fsm_pp0_stage41) & (ap_block_pp0_stage41_flag00011001 == 1'b0))) begin
reg_764 <= buffer_temp_out_V_q0;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00011001 == 1'b0))) begin
reg_764 <= buffer_temp_out_V_q1;
end
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0))) begin
if (((1'b1 == ap_CS_fsm_pp0_stage44) & (ap_block_pp0_stage44_flag00011001 == 1'b0))) begin
reg_780 <= buffer_temp_out_V_q1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage16) & (ap_block_pp0_stage16_flag00011001 == 1'b0))) begin
reg_780 <= buffer_temp_out_V_q0;
end
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (tmp_reg_1932 == 1'd0) & (ap_block_pp0_stage1_flag00011001 == 1'b0))) begin
buffer_V_addr_reg_1979[15 : 0] <= tmp_1_fu_830_p1[15 : 0];
tmp_1_reg_1974[15 : 0] <= tmp_1_fu_830_p1[15 : 0];
tmp_4_reg_1985[14 : 1] <= tmp_4_fu_841_p2[14 : 1];
tmp_98_reg_1940 <= tmp_98_fu_826_p1;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage23) & (ap_block_pp0_stage23_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_10_reg_2330 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage24) & (ap_block_pp0_stage24_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_11_reg_2335 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage25) & (ap_block_pp0_stage25_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_12_reg_2340 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage26) & (ap_block_pp0_stage26_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_13_reg_2345 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage27) & (ap_block_pp0_stage27_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_14_reg_2350 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage28) & (ap_block_pp0_stage28_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_15_reg_2355 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage29) & (ap_block_pp0_stage29_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_16_reg_2360 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage30) & (ap_block_pp0_stage30_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_17_reg_2365 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage31) & (ap_block_pp0_stage31_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_18_reg_2370 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage32) & (ap_block_pp0_stage32_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_19_reg_2375 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage33) & (ap_block_pp0_stage33_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_20_reg_2380 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage34) & (ap_block_pp0_stage34_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_21_reg_2385 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage35) & (ap_block_pp0_stage35_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_22_reg_2390 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage36) & (ap_block_pp0_stage36_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_23_reg_2395 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage37) & (ap_block_pp0_stage37_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_24_reg_2400 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage38) & (ap_block_pp0_stage38_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_25_reg_2405 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage39) & (ap_block_pp0_stage39_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_26_reg_2410 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage40) & (ap_block_pp0_stage40_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_27_reg_2415 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage17) & (ap_block_pp0_stage17_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_4_reg_2300 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage18) & (ap_block_pp0_stage18_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_5_reg_2305 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage19) & (ap_block_pp0_stage19_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_6_reg_2310 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage20) & (ap_block_pp0_stage20_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_7_reg_2315 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage21) & (ap_block_pp0_stage21_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_8_reg_2320 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage22) & (ap_block_pp0_stage22_flag00011001 == 1'b0))) begin
buffer_temp_out_V_lo_9_reg_2325 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00011001 == 1'b0))) begin
i_reg_2295 <= i_fu_1389_p2;
end
end
always @ (posedge ap_clk) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage8) & (ap_block_pp0_stage8_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage17) & (ap_block_pp0_stage17_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage20) & (ap_block_pp0_stage20_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage23) & (ap_block_pp0_stage23_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage26) & (ap_block_pp0_stage26_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage29) & (ap_block_pp0_stage29_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage32) & (ap_block_pp0_stage32_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage35) & (ap_block_pp0_stage35_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage38) & (ap_block_pp0_stage38_flag00011001 == 1'b0)))) begin
reg_752 <= buffer_V_RDATA;
end
end
always @ (posedge ap_clk) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage18) & (ap_block_pp0_stage18_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage21) & (ap_block_pp0_stage21_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage24) & (ap_block_pp0_stage24_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage27) & (ap_block_pp0_stage27_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage30) & (ap_block_pp0_stage30_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage33) & (ap_block_pp0_stage33_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage36) & (ap_block_pp0_stage36_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage39) & (ap_block_pp0_stage39_flag00011001 == 1'b0)))) begin
reg_756 <= buffer_V_RDATA;
end
end
always @ (posedge ap_clk) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage16) & (ap_block_pp0_stage16_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage19) & (ap_block_pp0_stage19_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage22) & (ap_block_pp0_stage22_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage25) & (ap_block_pp0_stage25_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage28) & (ap_block_pp0_stage28_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage31) & (ap_block_pp0_stage31_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage34) & (ap_block_pp0_stage34_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage37) & (ap_block_pp0_stage37_flag00011001 == 1'b0)))) begin
reg_760 <= buffer_V_RDATA;
end
end
always @ (posedge ap_clk) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage42) & (ap_block_pp0_stage42_flag00011001 == 1'b0)))) begin
reg_770 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage43) & (ap_block_pp0_stage43_flag00011001 == 1'b0)))) begin
reg_775 <= buffer_temp_out_V_q0;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_block_pp0_stage5_flag00011001 == 1'b0))) begin
tmp_11_reg_2025[1] <= tmp_11_fu_935_p2[1];
tmp_11_reg_2025[14 : 3] <= tmp_11_fu_935_p2[14 : 3];
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_block_pp0_stage6_flag00011001 == 1'b0))) begin
tmp_13_reg_2035[0] <= tmp_13_fu_958_p2[0];
tmp_13_reg_2035[14 : 3] <= tmp_13_fu_958_p2[14 : 3];
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00011001 == 1'b0))) begin
tmp_15_reg_2045[14 : 3] <= tmp_15_fu_981_p2[14 : 3];
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage8) & (ap_block_pp0_stage8_flag00011001 == 1'b0))) begin
tmp_17_reg_2055[2 : 0] <= tmp_17_fu_1004_p2[2 : 0];
tmp_17_reg_2055[14 : 4] <= tmp_17_fu_1004_p2[14 : 4];
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00011001 == 1'b0))) begin
tmp_19_reg_2065[2 : 1] <= tmp_19_fu_1027_p2[2 : 1];
tmp_19_reg_2065[14 : 4] <= tmp_19_fu_1027_p2[14 : 4];
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00011001 == 1'b0))) begin
tmp_21_reg_2075[0] <= tmp_21_fu_1050_p2[0];
tmp_21_reg_2075[2] <= tmp_21_fu_1050_p2[2];
tmp_21_reg_2075[14 : 4] <= tmp_21_fu_1050_p2[14 : 4];
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0))) begin
tmp_23_reg_2085[2] <= tmp_23_fu_1073_p2[2];
tmp_23_reg_2085[14 : 4] <= tmp_23_fu_1073_p2[14 : 4];
tmp_25_reg_2091[1 : 0] <= tmp_25_fu_1082_p2[1 : 0];
tmp_25_reg_2091[14 : 4] <= tmp_25_fu_1082_p2[14 : 4];
tmp_27_reg_2097[1] <= tmp_27_fu_1091_p2[1];
tmp_27_reg_2097[14 : 4] <= tmp_27_fu_1091_p2[14 : 4];
tmp_29_reg_2103[0] <= tmp_29_fu_1100_p2[0];
tmp_29_reg_2103[14 : 4] <= tmp_29_fu_1100_p2[14 : 4];
tmp_31_reg_2109[14 : 4] <= tmp_31_fu_1109_p2[14 : 4];
tmp_33_reg_2115[3 : 0] <= tmp_33_fu_1118_p2[3 : 0];
tmp_33_reg_2115[14 : 5] <= tmp_33_fu_1118_p2[14 : 5];
tmp_35_reg_2121[3 : 1] <= tmp_35_fu_1127_p2[3 : 1];
tmp_35_reg_2121[14 : 5] <= tmp_35_fu_1127_p2[14 : 5];
tmp_37_reg_2127[0] <= tmp_37_fu_1136_p2[0];
tmp_37_reg_2127[3 : 2] <= tmp_37_fu_1136_p2[3 : 2];
tmp_37_reg_2127[14 : 5] <= tmp_37_fu_1136_p2[14 : 5];
tmp_39_reg_2133[3 : 2] <= tmp_39_fu_1145_p2[3 : 2];
tmp_39_reg_2133[14 : 5] <= tmp_39_fu_1145_p2[14 : 5];
tmp_41_reg_2139[1 : 0] <= tmp_41_fu_1154_p2[1 : 0];
tmp_41_reg_2139[3] <= tmp_41_fu_1154_p2[3];
tmp_41_reg_2139[14 : 5] <= tmp_41_fu_1154_p2[14 : 5];
tmp_43_reg_2145[1] <= tmp_43_fu_1163_p2[1];
tmp_43_reg_2145[3] <= tmp_43_fu_1163_p2[3];
tmp_43_reg_2145[14 : 5] <= tmp_43_fu_1163_p2[14 : 5];
tmp_45_reg_2151[0] <= tmp_45_fu_1172_p2[0];
tmp_45_reg_2151[3] <= tmp_45_fu_1172_p2[3];
tmp_45_reg_2151[14 : 5] <= tmp_45_fu_1172_p2[14 : 5];
tmp_47_reg_2157[3] <= tmp_47_fu_1181_p2[3];
tmp_47_reg_2157[14 : 5] <= tmp_47_fu_1181_p2[14 : 5];
tmp_49_reg_2163[2 : 0] <= tmp_49_fu_1190_p2[2 : 0];
tmp_49_reg_2163[14 : 5] <= tmp_49_fu_1190_p2[14 : 5];
tmp_51_reg_2169[2 : 1] <= tmp_51_fu_1199_p2[2 : 1];
tmp_51_reg_2169[14 : 5] <= tmp_51_fu_1199_p2[14 : 5];
tmp_53_reg_2175[0] <= tmp_53_fu_1208_p2[0];
tmp_53_reg_2175[2] <= tmp_53_fu_1208_p2[2];
tmp_53_reg_2175[14 : 5] <= tmp_53_fu_1208_p2[14 : 5];
tmp_55_reg_2181[2] <= tmp_55_fu_1217_p2[2];
tmp_55_reg_2181[14 : 5] <= tmp_55_fu_1217_p2[14 : 5];
tmp_57_reg_2187[1 : 0] <= tmp_57_fu_1226_p2[1 : 0];
tmp_57_reg_2187[14 : 5] <= tmp_57_fu_1226_p2[14 : 5];
tmp_59_reg_2193[1] <= tmp_59_fu_1235_p2[1];
tmp_59_reg_2193[14 : 5] <= tmp_59_fu_1235_p2[14 : 5];
tmp_61_reg_2199[0] <= tmp_61_fu_1244_p2[0];
tmp_61_reg_2199[14 : 5] <= tmp_61_fu_1244_p2[14 : 5];
tmp_63_reg_2205[14 : 5] <= tmp_63_fu_1253_p2[14 : 5];
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081))) begin
tmp_5_10_reg_2211 <= tmp_5_10_fu_1271_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2))) begin
tmp_5_11_reg_2215 <= tmp_5_11_fu_1276_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2) & (1'd1 == tmp_5_11_fu_1276_p2))) begin
tmp_5_12_reg_2219 <= tmp_5_12_fu_1281_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2) & (1'd1 == tmp_5_11_fu_1276_p2) & (1'd1 == tmp_5_12_fu_1281_p2))) begin
tmp_5_13_reg_2223 <= tmp_5_13_fu_1286_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2) & (1'd1 == tmp_5_11_fu_1276_p2) & (1'd1 == tmp_5_12_fu_1281_p2) & (1'd1 == tmp_5_13_fu_1286_p2))) begin
tmp_5_14_reg_2227 <= tmp_5_14_fu_1291_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2) & (1'd1 == tmp_5_11_fu_1276_p2) & (1'd1 == tmp_5_12_fu_1281_p2) & (1'd1 == tmp_5_13_fu_1286_p2) & (1'd1 == tmp_5_14_fu_1291_p2))) begin
tmp_5_15_reg_2231 <= tmp_5_15_fu_1296_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2) & (1'd1 == tmp_5_11_fu_1276_p2) & (1'd1 == tmp_5_12_fu_1281_p2) & (1'd1 == tmp_5_13_fu_1286_p2) & (1'd1 == tmp_5_14_fu_1291_p2) & (1'd1 == tmp_5_15_fu_1296_p2))) begin
tmp_5_16_reg_2235 <= tmp_5_16_fu_1301_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2) & (1'd1 == tmp_5_11_fu_1276_p2) & (1'd1 == tmp_5_12_fu_1281_p2) & (1'd1 == tmp_5_13_fu_1286_p2) & (1'd1 == tmp_5_14_fu_1291_p2) & (1'd1 == tmp_5_15_fu_1296_p2) & (1'd1 == tmp_5_16_fu_1301_p2))) begin
tmp_5_17_reg_2239 <= tmp_5_17_fu_1306_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2) & (1'd1 == tmp_5_11_fu_1276_p2) & (1'd1 == tmp_5_12_fu_1281_p2) & (1'd1 == tmp_5_13_fu_1286_p2) & (1'd1 == tmp_5_14_fu_1291_p2) & (1'd1 == tmp_5_15_fu_1296_p2) & (1'd1 == tmp_5_16_fu_1301_p2) & (1'd1 == tmp_5_17_fu_1306_p2))) begin
tmp_5_18_reg_2243 <= tmp_5_18_fu_1311_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2) & (1'd1 == tmp_5_11_fu_1276_p2) & (1'd1 == tmp_5_12_fu_1281_p2) & (1'd1 == tmp_5_13_fu_1286_p2) & (1'd1 == tmp_5_14_fu_1291_p2) & (1'd1 == tmp_5_15_fu_1296_p2) & (1'd1 == tmp_5_16_fu_1301_p2) & (1'd1 == tmp_5_17_fu_1306_p2) & (1'd1 == tmp_5_18_fu_1311_p2))) begin
tmp_5_19_reg_2247 <= tmp_5_19_fu_1316_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (tmp_reg_1932 == 1'd0) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1))) begin
tmp_5_1_reg_1991 <= tmp_5_1_fu_861_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2) & (1'd1 == tmp_5_11_fu_1276_p2) & (1'd1 == tmp_5_12_fu_1281_p2) & (1'd1 == tmp_5_13_fu_1286_p2) & (1'd1 == tmp_5_14_fu_1291_p2) & (1'd1 == tmp_5_15_fu_1296_p2) & (1'd1 == tmp_5_16_fu_1301_p2) & (1'd1 == tmp_5_17_fu_1306_p2) & (1'd1 == tmp_5_18_fu_1311_p2) & (1'd1 == tmp_5_19_fu_1316_p2))) begin
tmp_5_20_reg_2251 <= tmp_5_20_fu_1321_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2) & (1'd1 == tmp_5_11_fu_1276_p2) & (1'd1 == tmp_5_12_fu_1281_p2) & (1'd1 == tmp_5_13_fu_1286_p2) & (1'd1 == tmp_5_14_fu_1291_p2) & (1'd1 == tmp_5_15_fu_1296_p2) & (1'd1 == tmp_5_16_fu_1301_p2) & (1'd1 == tmp_5_17_fu_1306_p2) & (1'd1 == tmp_5_18_fu_1311_p2) & (1'd1 == tmp_5_19_fu_1316_p2) & (1'd1 == tmp_5_20_fu_1321_p2))) begin
tmp_5_21_reg_2255 <= tmp_5_21_fu_1326_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2) & (1'd1 == tmp_5_11_fu_1276_p2) & (1'd1 == tmp_5_12_fu_1281_p2) & (1'd1 == tmp_5_13_fu_1286_p2) & (1'd1 == tmp_5_14_fu_1291_p2) & (1'd1 == tmp_5_15_fu_1296_p2) & (1'd1 == tmp_5_16_fu_1301_p2) & (1'd1 == tmp_5_17_fu_1306_p2) & (1'd1 == tmp_5_18_fu_1311_p2) & (1'd1 == tmp_5_19_fu_1316_p2) & (1'd1 == tmp_5_20_fu_1321_p2) & (1'd1 == tmp_5_21_fu_1326_p2))) begin
tmp_5_22_reg_2259 <= tmp_5_22_fu_1331_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2) & (1'd1 == tmp_5_11_fu_1276_p2) & (1'd1 == tmp_5_12_fu_1281_p2) & (1'd1 == tmp_5_13_fu_1286_p2) & (1'd1 == tmp_5_14_fu_1291_p2) & (1'd1 == tmp_5_15_fu_1296_p2) & (1'd1 == tmp_5_16_fu_1301_p2) & (1'd1 == tmp_5_17_fu_1306_p2) & (1'd1 == tmp_5_18_fu_1311_p2) & (1'd1 == tmp_5_19_fu_1316_p2) & (1'd1 == tmp_5_20_fu_1321_p2) & (1'd1 == tmp_5_21_fu_1326_p2) & (1'd1 == tmp_5_22_fu_1331_p2))) begin
tmp_5_23_reg_2263 <= tmp_5_23_fu_1336_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2) & (1'd1 == tmp_5_11_fu_1276_p2) & (1'd1 == tmp_5_12_fu_1281_p2) & (1'd1 == tmp_5_13_fu_1286_p2) & (1'd1 == tmp_5_14_fu_1291_p2) & (1'd1 == tmp_5_15_fu_1296_p2) & (1'd1 == tmp_5_16_fu_1301_p2) & (1'd1 == tmp_5_17_fu_1306_p2) & (1'd1 == tmp_5_18_fu_1311_p2) & (1'd1 == tmp_5_19_fu_1316_p2) & (1'd1 == tmp_5_20_fu_1321_p2) & (1'd1 == tmp_5_21_fu_1326_p2) & (1'd1 == tmp_5_22_fu_1331_p2) & (1'd1 == tmp_5_23_fu_1336_p2))) begin
tmp_5_24_reg_2267 <= tmp_5_24_fu_1341_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2) & (1'd1 == tmp_5_11_fu_1276_p2) & (1'd1 == tmp_5_12_fu_1281_p2) & (1'd1 == tmp_5_13_fu_1286_p2) & (1'd1 == tmp_5_14_fu_1291_p2) & (1'd1 == tmp_5_15_fu_1296_p2) & (1'd1 == tmp_5_16_fu_1301_p2) & (1'd1 == tmp_5_17_fu_1306_p2) & (1'd1 == tmp_5_18_fu_1311_p2) & (1'd1 == tmp_5_19_fu_1316_p2) & (1'd1 == tmp_5_20_fu_1321_p2) & (1'd1 == tmp_5_21_fu_1326_p2) & (1'd1 == tmp_5_22_fu_1331_p2) & (1'd1 == tmp_5_23_fu_1336_p2) & (1'd1 == tmp_5_24_fu_1341_p2))) begin
tmp_5_25_reg_2271 <= tmp_5_25_fu_1346_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2) & (1'd1 == tmp_5_11_fu_1276_p2) & (1'd1 == tmp_5_12_fu_1281_p2) & (1'd1 == tmp_5_13_fu_1286_p2) & (1'd1 == tmp_5_14_fu_1291_p2) & (1'd1 == tmp_5_15_fu_1296_p2) & (1'd1 == tmp_5_16_fu_1301_p2) & (1'd1 == tmp_5_17_fu_1306_p2) & (1'd1 == tmp_5_18_fu_1311_p2) & (1'd1 == tmp_5_19_fu_1316_p2) & (1'd1 == tmp_5_20_fu_1321_p2) & (1'd1 == tmp_5_21_fu_1326_p2) & (1'd1 == tmp_5_22_fu_1331_p2) & (1'd1 == tmp_5_23_fu_1336_p2) & (1'd1 == tmp_5_24_fu_1341_p2) & (1'd1 == tmp_5_25_fu_1346_p2))) begin
tmp_5_26_reg_2275 <= tmp_5_26_fu_1351_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2) & (1'd1 == tmp_5_11_fu_1276_p2) & (1'd1 == tmp_5_12_fu_1281_p2) & (1'd1 == tmp_5_13_fu_1286_p2) & (1'd1 == tmp_5_14_fu_1291_p2) & (1'd1 == tmp_5_15_fu_1296_p2) & (1'd1 == tmp_5_16_fu_1301_p2) & (1'd1 == tmp_5_17_fu_1306_p2) & (1'd1 == tmp_5_18_fu_1311_p2) & (1'd1 == tmp_5_19_fu_1316_p2) & (1'd1 == tmp_5_20_fu_1321_p2) & (1'd1 == tmp_5_21_fu_1326_p2) & (1'd1 == tmp_5_22_fu_1331_p2) & (1'd1 == tmp_5_23_fu_1336_p2) & (1'd1 == tmp_5_24_fu_1341_p2) & (1'd1 == tmp_5_25_fu_1346_p2) & (1'd1 == tmp_5_26_fu_1351_p2))) begin
tmp_5_27_reg_2279 <= tmp_5_27_fu_1356_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2) & (1'd1 == tmp_5_11_fu_1276_p2) & (1'd1 == tmp_5_12_fu_1281_p2) & (1'd1 == tmp_5_13_fu_1286_p2) & (1'd1 == tmp_5_14_fu_1291_p2) & (1'd1 == tmp_5_15_fu_1296_p2) & (1'd1 == tmp_5_16_fu_1301_p2) & (1'd1 == tmp_5_17_fu_1306_p2) & (1'd1 == tmp_5_18_fu_1311_p2) & (1'd1 == tmp_5_19_fu_1316_p2) & (1'd1 == tmp_5_20_fu_1321_p2) & (1'd1 == tmp_5_21_fu_1326_p2) & (1'd1 == tmp_5_22_fu_1331_p2) & (1'd1 == tmp_5_23_fu_1336_p2) & (1'd1 == tmp_5_24_fu_1341_p2) & (1'd1 == tmp_5_25_fu_1346_p2) & (1'd1 == tmp_5_26_fu_1351_p2) & (1'd1 == tmp_5_27_fu_1356_p2))) begin
tmp_5_28_reg_2283 <= tmp_5_28_fu_1361_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2) & (1'd1 == tmp_5_11_fu_1276_p2) & (1'd1 == tmp_5_12_fu_1281_p2) & (1'd1 == tmp_5_13_fu_1286_p2) & (1'd1 == tmp_5_14_fu_1291_p2) & (1'd1 == tmp_5_15_fu_1296_p2) & (1'd1 == tmp_5_16_fu_1301_p2) & (1'd1 == tmp_5_17_fu_1306_p2) & (1'd1 == tmp_5_18_fu_1311_p2) & (1'd1 == tmp_5_19_fu_1316_p2) & (1'd1 == tmp_5_20_fu_1321_p2) & (1'd1 == tmp_5_21_fu_1326_p2) & (1'd1 == tmp_5_22_fu_1331_p2) & (1'd1 == tmp_5_23_fu_1336_p2) & (1'd1 == tmp_5_24_fu_1341_p2) & (1'd1 == tmp_5_25_fu_1346_p2) & (1'd1 == tmp_5_26_fu_1351_p2) & (1'd1 == tmp_5_27_fu_1356_p2) & (1'd1 == tmp_5_28_fu_1361_p2))) begin
tmp_5_29_reg_2287 <= tmp_5_29_fu_1366_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (tmp_5_1_reg_1991 == 1'd1))) begin
tmp_5_2_reg_2001 <= tmp_5_2_fu_884_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2) & (1'd1 == tmp_5_11_fu_1276_p2) & (1'd1 == tmp_5_12_fu_1281_p2) & (1'd1 == tmp_5_13_fu_1286_p2) & (1'd1 == tmp_5_14_fu_1291_p2) & (1'd1 == tmp_5_15_fu_1296_p2) & (1'd1 == tmp_5_16_fu_1301_p2) & (1'd1 == tmp_5_17_fu_1306_p2) & (1'd1 == tmp_5_18_fu_1311_p2) & (1'd1 == tmp_5_19_fu_1316_p2) & (1'd1 == tmp_5_20_fu_1321_p2) & (1'd1 == tmp_5_21_fu_1326_p2) & (1'd1 == tmp_5_22_fu_1331_p2) & (1'd1 == tmp_5_23_fu_1336_p2) & (1'd1 == tmp_5_24_fu_1341_p2) & (1'd1 == tmp_5_25_fu_1346_p2) & (1'd1 == tmp_5_26_fu_1351_p2) & (1'd1 == tmp_5_27_fu_1356_p2) & (1'd1 == tmp_5_28_fu_1361_p2) & (1'd1 == tmp_5_29_fu_1366_p2))) begin
tmp_5_30_reg_2291 <= tmp_5_30_fu_1371_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00011001 == 1'b0) & (1'd1 == tmp_5_2_reg_2001))) begin
tmp_5_3_reg_2011 <= tmp_5_3_fu_907_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00011001 == 1'b0) & (1'd1 == tmp_5_3_reg_2011))) begin
tmp_5_4_reg_2021 <= tmp_5_4_fu_930_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_block_pp0_stage5_flag00011001 == 1'b0) & (1'd1 == tmp_5_4_reg_2021))) begin
tmp_5_5_reg_2031 <= tmp_5_5_fu_953_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_block_pp0_stage6_flag00011001 == 1'b0) & (1'd1 == tmp_5_5_reg_2031))) begin
tmp_5_6_reg_2041 <= tmp_5_6_fu_976_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00011001 == 1'b0) & (1'd1 == tmp_5_6_reg_2041))) begin
tmp_5_7_reg_2051 <= tmp_5_7_fu_999_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage8) & (ap_block_pp0_stage8_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051))) begin
tmp_5_8_reg_2061 <= tmp_5_8_fu_1022_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061))) begin
tmp_5_9_reg_2071 <= tmp_5_9_fu_1045_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00011001 == 1'b0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071))) begin
tmp_5_s_reg_2081 <= tmp_5_s_fu_1068_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'd0 == tmp_fu_809_p3))) begin
tmp_66_reg_1936 <= tmp_66_fu_821_p2;
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
tmp_6_reg_1995[0] <= tmp_6_fu_866_p2[0];
tmp_6_reg_1995[14 : 2] <= tmp_6_fu_866_p2[14 : 2];
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00011001 == 1'b0))) begin
tmp_8_reg_2005[14 : 2] <= tmp_8_fu_889_p2[14 : 2];
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
tmp_reg_1932 <= i_op_assign_phi_fu_736_p4[32'd15];
end
end
always @ (posedge ap_clk) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00011001 == 1'b0))) begin
tmp_s_reg_2015[1 : 0] <= tmp_s_fu_912_p2[1 : 0];
tmp_s_reg_2015[14 : 3] <= tmp_s_fu_912_p2[14 : 3];
end
end
always @ (*) begin
if ((tmp_fu_809_p3 == 1'd1)) begin
ap_condition_pp0_exit_iter0_state2 = 1'b1;
end else begin
ap_condition_pp0_exit_iter0_state2 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state80)) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1))) begin
ap_idle_pp0 = 1'b1;
end else begin
ap_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state80)) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if ((1'b0 == ap_reg_ioackin_buffer_V_ARREADY)) begin
ap_sig_ioackin_buffer_V_ARREADY = buffer_V_ARREADY;
end else begin
ap_sig_ioackin_buffer_V_ARREADY = 1'b1;
end
end
always @ (*) begin
if ((1'b0 == ap_reg_ioackin_buffer_V_AWREADY)) begin
ap_sig_ioackin_buffer_V_AWREADY = buffer_V_AWREADY;
end else begin
ap_sig_ioackin_buffer_V_AWREADY = 1'b1;
end
end
always @ (*) begin
if ((1'b0 == ap_reg_ioackin_buffer_V_WREADY)) begin
ap_sig_ioackin_buffer_V_WREADY = buffer_V_WREADY;
end else begin
ap_sig_ioackin_buffer_V_WREADY = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (ap_block_pp0_stage1_flag00001001 == 1'b0) & (1'b0 == ap_reg_ioackin_buffer_V_ARREADY))) begin
buffer_V_ARVALID = 1'b1;
end else begin
buffer_V_ARVALID = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage40) & (ap_block_pp0_stage40_flag00001001 == 1'b0) & (1'b0 == ap_reg_ioackin_buffer_V_AWREADY))) begin
buffer_V_AWVALID = 1'b1;
end else begin
buffer_V_AWVALID = 1'b0;
end
end
always @ (*) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
buffer_V_BREADY = 1'b1;
end else begin
buffer_V_BREADY = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage8) & (ap_block_pp0_stage8_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage17) & (ap_block_pp0_stage17_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage20) & (ap_block_pp0_stage20_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage23) & (ap_block_pp0_stage23_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage26) & (ap_block_pp0_stage26_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage29) & (ap_block_pp0_stage29_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage32) & (ap_block_pp0_stage32_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage35) & (ap_block_pp0_stage35_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage38) & (ap_block_pp0_stage38_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage18) & (ap_block_pp0_stage18_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage21) & (ap_block_pp0_stage21_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage24) & (ap_block_pp0_stage24_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage27) & (ap_block_pp0_stage27_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage30) & (ap_block_pp0_stage30_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage33) & (ap_block_pp0_stage33_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage36) & (ap_block_pp0_stage36_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage39) & (ap_block_pp0_stage39_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage16) & (ap_block_pp0_stage16_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage19) & (ap_block_pp0_stage19_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage22) & (ap_block_pp0_stage22_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage25) & (ap_block_pp0_stage25_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage28) & (ap_block_pp0_stage28_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage31) & (ap_block_pp0_stage31_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage34) & (ap_block_pp0_stage34_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage37) & (ap_block_pp0_stage37_flag00011001 == 1'b0)))) begin
buffer_V_RREADY = 1'b1;
end else begin
buffer_V_RREADY = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage68) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage68_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_27_reg_2415;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage67) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage67_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_26_reg_2410;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage66) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage66_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_25_reg_2405;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage65) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage65_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_24_reg_2400;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage64) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage64_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_23_reg_2395;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage63) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage63_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_22_reg_2390;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage62) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage62_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_21_reg_2385;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage61) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage61_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_20_reg_2380;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage60) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage60_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_19_reg_2375;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage59) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage59_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_18_reg_2370;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage58) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage58_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_17_reg_2365;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage57) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage57_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_16_reg_2360;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage56) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage56_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_15_reg_2355;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage55) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage55_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_14_reg_2350;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage54) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage54_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_13_reg_2345;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage53) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage53_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_12_reg_2340;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage52) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage52_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_11_reg_2335;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage51) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage51_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_10_reg_2330;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage50) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage50_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_9_reg_2325;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage49) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage49_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_8_reg_2320;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage48) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage48_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_7_reg_2315;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage47) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage47_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_6_reg_2310;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage46) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage46_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_5_reg_2305;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage45) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage45_flag00001001 == 1'b0))) begin
buffer_V_WDATA = buffer_temp_out_V_lo_4_reg_2300;
end else if ((((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage44) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage44_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage72) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage72_flag00001001 == 1'b0)))) begin
buffer_V_WDATA = reg_780;
end else if ((((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage43) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage43_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage71) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage71_flag00001001 == 1'b0)))) begin
buffer_V_WDATA = reg_775;
end else if ((((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage42) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage42_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage70) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage70_flag00001001 == 1'b0)))) begin
buffer_V_WDATA = reg_770;
end else if ((((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage41) & (ap_block_pp0_stage41_flag00001001 == 1'b0) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage69) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage69_flag00001001 == 1'b0)))) begin
buffer_V_WDATA = reg_764;
end else begin
buffer_V_WDATA = 'bx;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage41) & (ap_block_pp0_stage41_flag00001001 == 1'b0) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage42) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage42_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage43) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage43_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage44) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage44_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage45) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage45_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage46) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage46_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage47) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage47_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage48) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage48_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage49) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage49_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage50) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage50_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage51) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage51_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage52) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage52_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage53) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage53_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage54) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage54_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage55) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage55_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage56) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage56_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage57) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage57_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage58) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage58_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage59) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage59_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage60) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage60_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage61) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage61_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage62) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage62_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage63) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage63_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage64) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage64_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage65) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage65_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage66) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage66_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage67) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage67_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage68) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage68_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage69) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage69_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage70) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage70_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage71) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage71_flag00001001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage72) & (1'b0 == ap_reg_ioackin_buffer_V_WREADY) & (ap_block_pp0_stage72_flag00001001 == 1'b0)))) begin
buffer_V_WVALID = 1'b1;
end else begin
buffer_V_WVALID = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage1_flag00000000 == 1'b0) & (tmp_reg_1932 == 1'd0))) begin
buffer_V_blk_n_AR = m_axi_buffer_V_ARREADY;
end else begin
buffer_V_blk_n_AR = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage40) & (ap_block_pp0_stage40_flag00000000 == 1'b0))) begin
buffer_V_blk_n_AW = m_axi_buffer_V_AWREADY;
end else begin
buffer_V_blk_n_AW = 1'b1;
end
end
always @ (*) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
buffer_V_blk_n_B = m_axi_buffer_V_BVALID;
end else begin
buffer_V_blk_n_B = 1'b1;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage8) & (ap_block_pp0_stage8_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage16) & (ap_block_pp0_stage16_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage17) & (ap_block_pp0_stage17_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage18) & (ap_block_pp0_stage18_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage19) & (ap_block_pp0_stage19_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage20) & (ap_block_pp0_stage20_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage21) & (ap_block_pp0_stage21_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage22) & (ap_block_pp0_stage22_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage23) & (ap_block_pp0_stage23_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage24) & (ap_block_pp0_stage24_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage25) & (ap_block_pp0_stage25_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage26) & (ap_block_pp0_stage26_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage27) & (ap_block_pp0_stage27_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage28) & (ap_block_pp0_stage28_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage29) & (ap_block_pp0_stage29_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage30) & (ap_block_pp0_stage30_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage31) & (ap_block_pp0_stage31_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage32) & (ap_block_pp0_stage32_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage33) & (ap_block_pp0_stage33_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage34) & (ap_block_pp0_stage34_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage35) & (ap_block_pp0_stage35_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage36) & (ap_block_pp0_stage36_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage37) & (ap_block_pp0_stage37_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage38) & (ap_block_pp0_stage38_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage39) & (ap_block_pp0_stage39_flag00000000 == 1'b0)))) begin
buffer_V_blk_n_R = m_axi_buffer_V_RVALID;
end else begin
buffer_V_blk_n_R = 1'b1;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage41) & (ap_block_pp0_stage41_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage42) & (ap_block_pp0_stage42_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage43) & (ap_block_pp0_stage43_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage44) & (ap_block_pp0_stage44_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage45) & (ap_block_pp0_stage45_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage46) & (ap_block_pp0_stage46_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage47) & (ap_block_pp0_stage47_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage48) & (ap_block_pp0_stage48_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage49) & (ap_block_pp0_stage49_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage50) & (ap_block_pp0_stage50_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage51) & (ap_block_pp0_stage51_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage52) & (ap_block_pp0_stage52_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage53) & (ap_block_pp0_stage53_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage54) & (ap_block_pp0_stage54_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage55) & (ap_block_pp0_stage55_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage56) & (ap_block_pp0_stage56_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage57) & (ap_block_pp0_stage57_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage58) & (ap_block_pp0_stage58_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage59) & (ap_block_pp0_stage59_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage60) & (ap_block_pp0_stage60_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage61) & (ap_block_pp0_stage61_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage62) & (ap_block_pp0_stage62_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage63) & (ap_block_pp0_stage63_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage64) & (ap_block_pp0_stage64_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage65) & (ap_block_pp0_stage65_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage66) & (ap_block_pp0_stage66_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage67) & (ap_block_pp0_stage67_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage68) & (ap_block_pp0_stage68_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage69) & (ap_block_pp0_stage69_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage70) & (ap_block_pp0_stage70_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage71) & (ap_block_pp0_stage71_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage72) & (ap_block_pp0_stage72_flag00000000 == 1'b0)))) begin
buffer_V_blk_n_W = m_axi_buffer_V_WREADY;
end else begin
buffer_V_blk_n_W = 1'b1;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter0)) begin
if (((1'b1 == ap_CS_fsm_pp0_stage42) & (ap_block_pp0_stage42_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd30;
end else if (((1'b1 == ap_CS_fsm_pp0_stage41) & (ap_block_pp0_stage41_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd29;
end else if (((1'b1 == ap_CS_fsm_pp0_stage40) & (ap_block_pp0_stage40_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd28;
end else if (((1'b1 == ap_CS_fsm_pp0_stage39) & (ap_block_pp0_stage39_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd27;
end else if (((1'b1 == ap_CS_fsm_pp0_stage38) & (ap_block_pp0_stage38_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd26;
end else if (((1'b1 == ap_CS_fsm_pp0_stage37) & (ap_block_pp0_stage37_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd25;
end else if (((1'b1 == ap_CS_fsm_pp0_stage36) & (ap_block_pp0_stage36_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd24;
end else if (((1'b1 == ap_CS_fsm_pp0_stage35) & (ap_block_pp0_stage35_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd23;
end else if (((1'b1 == ap_CS_fsm_pp0_stage34) & (ap_block_pp0_stage34_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd22;
end else if (((1'b1 == ap_CS_fsm_pp0_stage33) & (ap_block_pp0_stage33_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd21;
end else if (((1'b1 == ap_CS_fsm_pp0_stage32) & (ap_block_pp0_stage32_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd20;
end else if (((1'b1 == ap_CS_fsm_pp0_stage31) & (ap_block_pp0_stage31_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd19;
end else if (((1'b1 == ap_CS_fsm_pp0_stage30) & (ap_block_pp0_stage30_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd18;
end else if (((1'b1 == ap_CS_fsm_pp0_stage29) & (ap_block_pp0_stage29_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd17;
end else if (((1'b1 == ap_CS_fsm_pp0_stage28) & (ap_block_pp0_stage28_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd16;
end else if (((1'b1 == ap_CS_fsm_pp0_stage27) & (ap_block_pp0_stage27_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd15;
end else if (((1'b1 == ap_CS_fsm_pp0_stage26) & (ap_block_pp0_stage26_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd14;
end else if (((1'b1 == ap_CS_fsm_pp0_stage25) & (ap_block_pp0_stage25_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd13;
end else if (((1'b1 == ap_CS_fsm_pp0_stage24) & (ap_block_pp0_stage24_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd12;
end else if (((1'b1 == ap_CS_fsm_pp0_stage23) & (ap_block_pp0_stage23_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd11;
end else if (((1'b1 == ap_CS_fsm_pp0_stage22) & (ap_block_pp0_stage22_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd10;
end else if (((1'b1 == ap_CS_fsm_pp0_stage21) & (ap_block_pp0_stage21_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd9;
end else if (((1'b1 == ap_CS_fsm_pp0_stage20) & (ap_block_pp0_stage20_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd8;
end else if (((1'b1 == ap_CS_fsm_pp0_stage19) & (ap_block_pp0_stage19_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd7;
end else if (((1'b1 == ap_CS_fsm_pp0_stage18) & (ap_block_pp0_stage18_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd6;
end else if (((1'b1 == ap_CS_fsm_pp0_stage17) & (ap_block_pp0_stage17_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd5;
end else if (((1'b1 == ap_CS_fsm_pp0_stage16) & (ap_block_pp0_stage16_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd4;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd3;
end else if (((1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd2;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = 64'd1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = tmp_5_fu_1376_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address0 = tmp_1_reg_1974;
end else begin
buffer_temp_out_V_address0 = 'bx;
end
end else begin
buffer_temp_out_V_address0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter0)) begin
if (((1'b1 == ap_CS_fsm_pp0_stage43) & (ap_block_pp0_stage43_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = 64'd31;
end else if (((1'b1 == ap_CS_fsm_pp0_stage42) & (ap_block_pp0_stage42_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_64_fu_1691_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage41) & (ap_block_pp0_stage41_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_62_fu_1687_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage40) & (ap_block_pp0_stage40_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_60_fu_1683_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage39) & (ap_block_pp0_stage39_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_58_fu_1679_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage38) & (ap_block_pp0_stage38_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_56_fu_1675_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage37) & (ap_block_pp0_stage37_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_54_fu_1671_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage36) & (ap_block_pp0_stage36_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_52_fu_1667_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage35) & (ap_block_pp0_stage35_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_50_fu_1663_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage34) & (ap_block_pp0_stage34_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_48_fu_1659_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage33) & (ap_block_pp0_stage33_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_46_fu_1655_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage32) & (ap_block_pp0_stage32_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_44_fu_1642_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage31) & (ap_block_pp0_stage31_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_42_fu_1629_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage30) & (ap_block_pp0_stage30_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_40_fu_1616_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage29) & (ap_block_pp0_stage29_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_38_fu_1603_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage28) & (ap_block_pp0_stage28_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_36_fu_1590_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage27) & (ap_block_pp0_stage27_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_34_fu_1577_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage26) & (ap_block_pp0_stage26_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_32_fu_1564_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage25) & (ap_block_pp0_stage25_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_30_fu_1551_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage24) & (ap_block_pp0_stage24_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_28_fu_1538_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage23) & (ap_block_pp0_stage23_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_26_fu_1525_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage22) & (ap_block_pp0_stage22_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_24_fu_1512_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage21) & (ap_block_pp0_stage21_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_22_fu_1499_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage20) & (ap_block_pp0_stage20_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_20_fu_1486_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage19) & (ap_block_pp0_stage19_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_18_fu_1473_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage18) & (ap_block_pp0_stage18_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_16_fu_1460_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage17) & (ap_block_pp0_stage17_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_14_fu_1447_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage16) & (ap_block_pp0_stage16_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_12_fu_1434_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_10_fu_1421_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_9_fu_1408_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = tmp_7_fu_1395_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
buffer_temp_out_V_address1 = 64'd0;
end else begin
buffer_temp_out_V_address1 = 'bx;
end
end else begin
buffer_temp_out_V_address1 = 'bx;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage17) & (ap_block_pp0_stage17_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage20) & (ap_block_pp0_stage20_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage23) & (ap_block_pp0_stage23_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage26) & (ap_block_pp0_stage26_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage29) & (ap_block_pp0_stage29_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage32) & (ap_block_pp0_stage32_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage35) & (ap_block_pp0_stage35_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage38) & (ap_block_pp0_stage38_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage18) & (ap_block_pp0_stage18_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage21) & (ap_block_pp0_stage21_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage24) & (ap_block_pp0_stage24_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage27) & (ap_block_pp0_stage27_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage30) & (ap_block_pp0_stage30_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage33) & (ap_block_pp0_stage33_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage36) & (ap_block_pp0_stage36_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage39) & (ap_block_pp0_stage39_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage16) & (ap_block_pp0_stage16_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage19) & (ap_block_pp0_stage19_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage22) & (ap_block_pp0_stage22_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage25) & (ap_block_pp0_stage25_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage28) & (ap_block_pp0_stage28_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage31) & (ap_block_pp0_stage31_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage34) & (ap_block_pp0_stage34_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage37) & (ap_block_pp0_stage37_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage41) & (ap_block_pp0_stage41_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage42) & (ap_block_pp0_stage42_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage40) & (ap_block_pp0_stage40_flag00011001 == 1'b0)))) begin
buffer_temp_out_V_ce0 = 1'b1;
end else begin
buffer_temp_out_V_ce0 = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage17) & (ap_block_pp0_stage17_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage20) & (ap_block_pp0_stage20_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage23) & (ap_block_pp0_stage23_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage26) & (ap_block_pp0_stage26_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage29) & (ap_block_pp0_stage29_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage32) & (ap_block_pp0_stage32_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage35) & (ap_block_pp0_stage35_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage38) & (ap_block_pp0_stage38_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage18) & (ap_block_pp0_stage18_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage21) & (ap_block_pp0_stage21_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage24) & (ap_block_pp0_stage24_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage27) & (ap_block_pp0_stage27_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage30) & (ap_block_pp0_stage30_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage33) & (ap_block_pp0_stage33_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage36) & (ap_block_pp0_stage36_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage39) & (ap_block_pp0_stage39_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage16) & (ap_block_pp0_stage16_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage19) & (ap_block_pp0_stage19_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage22) & (ap_block_pp0_stage22_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage25) & (ap_block_pp0_stage25_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage28) & (ap_block_pp0_stage28_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage31) & (ap_block_pp0_stage31_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage34) & (ap_block_pp0_stage34_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage37) & (ap_block_pp0_stage37_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage41) & (ap_block_pp0_stage41_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage42) & (ap_block_pp0_stage42_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage43) & (ap_block_pp0_stage43_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage40) & (ap_block_pp0_stage40_flag00011001 == 1'b0)))) begin
buffer_temp_out_V_ce1 = 1'b1;
end else begin
buffer_temp_out_V_ce1 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter0)) begin
if (((1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
buffer_temp_out_V_d0 = grp_fu_794_p2;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
buffer_temp_out_V_d0 = grp_fu_786_p2;
end else begin
buffer_temp_out_V_d0 = 'bx;
end
end else begin
buffer_temp_out_V_d0 = 'bx;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage18) & (ap_block_pp0_stage18_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage21) & (ap_block_pp0_stage21_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage24) & (ap_block_pp0_stage24_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage27) & (ap_block_pp0_stage27_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage30) & (ap_block_pp0_stage30_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage33) & (ap_block_pp0_stage33_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage36) & (ap_block_pp0_stage36_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage39) & (ap_block_pp0_stage39_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage42) & (ap_block_pp0_stage42_flag00000000 == 1'b0)))) begin
buffer_temp_out_V_d1 = grp_fu_794_p2;
end else if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage17) & (ap_block_pp0_stage17_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage20) & (ap_block_pp0_stage20_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage23) & (ap_block_pp0_stage23_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage26) & (ap_block_pp0_stage26_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage29) & (ap_block_pp0_stage29_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage32) & (ap_block_pp0_stage32_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage35) & (ap_block_pp0_stage35_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage38) & (ap_block_pp0_stage38_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage41) & (ap_block_pp0_stage41_flag00000000 == 1'b0)))) begin
buffer_temp_out_V_d1 = grp_fu_786_p2;
end else if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage16) & (ap_block_pp0_stage16_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage19) & (ap_block_pp0_stage19_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage22) & (ap_block_pp0_stage22_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage25) & (ap_block_pp0_stage25_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage28) & (ap_block_pp0_stage28_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage31) & (ap_block_pp0_stage31_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage34) & (ap_block_pp0_stage34_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage37) & (ap_block_pp0_stage37_flag00000000 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage40) & (ap_block_pp0_stage40_flag00000000 == 1'b0)))) begin
buffer_temp_out_V_d1 = grp_fu_802_p2;
end else begin
buffer_temp_out_V_d1 = 'bx;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op307_call_state13)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op370_call_state14)))) begin
buffer_temp_out_V_we0 = 1'b1;
end else begin
buffer_temp_out_V_we0 = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op392_call_state15)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op414_call_state16)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op436_call_state17)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage16) & (ap_block_pp0_stage16_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op458_call_state18)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage17) & (ap_block_pp0_stage17_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op480_call_state19)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage18) & (ap_block_pp0_stage18_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op502_call_state20)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage19) & (ap_block_pp0_stage19_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op524_call_state21)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage20) & (ap_block_pp0_stage20_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op546_call_state22)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage21) & (ap_block_pp0_stage21_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op568_call_state23)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage22) & (ap_block_pp0_stage22_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op590_call_state24)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage23) & (ap_block_pp0_stage23_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op612_call_state25)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage24) & (ap_block_pp0_stage24_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op634_call_state26)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage25) & (ap_block_pp0_stage25_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op656_call_state27)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage26) & (ap_block_pp0_stage26_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op678_call_state28)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage27) & (ap_block_pp0_stage27_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op700_call_state29)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage28) & (ap_block_pp0_stage28_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op722_call_state30)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage29) & (ap_block_pp0_stage29_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op744_call_state31)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage30) & (ap_block_pp0_stage30_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op766_call_state32)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage31) & (ap_block_pp0_stage31_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op788_call_state33)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage32) & (ap_block_pp0_stage32_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op810_call_state34)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage33) & (ap_block_pp0_stage33_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op832_call_state35)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage34) & (ap_block_pp0_stage34_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op851_call_state36)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage35) & (ap_block_pp0_stage35_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op869_call_state37)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage36) & (ap_block_pp0_stage36_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op886_call_state38)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage37) & (ap_block_pp0_stage37_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op902_call_state39)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage38) & (ap_block_pp0_stage38_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op917_call_state40)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage39) & (ap_block_pp0_stage39_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op931_call_state41)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage40) & (ap_block_pp0_stage40_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op943_call_state42)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage41) & (ap_block_pp0_stage41_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op955_call_state43)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage42) & (ap_block_pp0_stage42_flag00011001 == 1'b0) & (1'b1 == ap_predicate_op969_call_state44)))) begin
buffer_temp_out_V_we1 = 1'b1;
end else begin
buffer_temp_out_V_we1 = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_block_pp0_stage5_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_block_pp0_stage6_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage8) & (ap_block_pp0_stage8_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage16) & (ap_block_pp0_stage16_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage17) & (ap_block_pp0_stage17_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage18) & (ap_block_pp0_stage18_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage19) & (ap_block_pp0_stage19_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage20) & (ap_block_pp0_stage20_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage21) & (ap_block_pp0_stage21_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage22) & (ap_block_pp0_stage22_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage23) & (ap_block_pp0_stage23_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage24) & (ap_block_pp0_stage24_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage25) & (ap_block_pp0_stage25_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage26) & (ap_block_pp0_stage26_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage27) & (ap_block_pp0_stage27_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage28) & (ap_block_pp0_stage28_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage29) & (ap_block_pp0_stage29_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage30) & (ap_block_pp0_stage30_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage31) & (ap_block_pp0_stage31_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage32) & (ap_block_pp0_stage32_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage33) & (ap_block_pp0_stage33_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage34) & (ap_block_pp0_stage34_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage35) & (ap_block_pp0_stage35_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage36) & (ap_block_pp0_stage36_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage37) & (ap_block_pp0_stage37_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage38) & (ap_block_pp0_stage38_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage39) & (ap_block_pp0_stage39_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage40) & (ap_block_pp0_stage40_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage41) & (ap_block_pp0_stage41_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage42) & (ap_block_pp0_stage42_flag00011001 == 1'b0)))) begin
grp_aestest_fu_744_ap_ce = 1'b1;
end else begin
grp_aestest_fu_744_ap_ce = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter0)) begin
if ((ap_condition_8071 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_30_fu_1649_p2;
end else if ((ap_condition_8068 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_29_fu_1636_p2;
end else if ((ap_condition_8065 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_28_fu_1623_p2;
end else if ((ap_condition_8062 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_27_fu_1610_p2;
end else if ((ap_condition_8059 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_26_fu_1597_p2;
end else if ((ap_condition_8056 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_25_fu_1584_p2;
end else if ((ap_condition_8053 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_24_fu_1571_p2;
end else if ((ap_condition_8050 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_23_fu_1558_p2;
end else if ((ap_condition_8047 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_22_fu_1545_p2;
end else if ((ap_condition_8044 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_21_fu_1532_p2;
end else if ((ap_condition_8041 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_20_fu_1519_p2;
end else if ((ap_condition_8038 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_19_fu_1506_p2;
end else if ((ap_condition_8035 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_18_fu_1493_p2;
end else if ((ap_condition_8032 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_17_fu_1480_p2;
end else if ((ap_condition_8029 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_16_fu_1467_p2;
end else if ((ap_condition_8026 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_15_fu_1454_p2;
end else if ((ap_condition_8023 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_14_fu_1441_p2;
end else if ((ap_condition_8020 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_13_fu_1428_p2;
end else if ((ap_condition_8017 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_12_fu_1415_p2;
end else if ((ap_condition_8014 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_11_fu_1402_p2;
end else if ((ap_condition_8011 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_10_fu_1383_p2;
end else if ((ap_condition_8008 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_s_fu_1265_p2;
end else if ((ap_condition_8005 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_9_fu_1062_p2;
end else if ((ap_condition_8001 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_8_fu_1039_p2;
end else if ((ap_condition_7997 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_7_fu_1016_p2;
end else if ((ap_condition_7993 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_6_fu_993_p2;
end else if ((ap_condition_7989 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_5_fu_970_p2;
end else if ((ap_condition_7985 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_4_fu_947_p2;
end else if ((ap_condition_7981 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_3_fu_924_p2;
end else if ((ap_condition_7977 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_2_fu_901_p2;
end else if ((ap_condition_7973 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_0_1_fu_878_p2;
end else if ((ap_condition_7969 == 1'b1)) begin
grp_aestest_fu_744_inptext_V_read = counter_V_fu_855_p2;
end else begin
grp_aestest_fu_744_inptext_V_read = 'bx;
end
end else begin
grp_aestest_fu_744_inptext_V_read = 'bx;
end
end
always @ (*) begin
if (((tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
i_op_assign_phi_fu_736_p4 = i_reg_2295;
end else begin
i_op_assign_phi_fu_736_p4 = i_op_assign_reg_732;
end
end
always @ (*) begin
if ((1'b1 == length_r_ap_vld)) begin
length_r_ap_vld_in_sig = length_r_ap_vld;
end else begin
length_r_ap_vld_in_sig = length_r_ap_vld_preg;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
length_r_blk_n = length_r_ap_vld;
end else begin
length_r_blk_n = 1'b1;
end
end
always @ (*) begin
if ((1'b1 == length_r_ap_vld)) begin
length_r_in_sig = length_r;
end else begin
length_r_in_sig = length_r_preg;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (1'b0 == length_r_ap_vld_in_sig)))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_pp0_stage0 : begin
if (((ap_block_pp0_stage0_flag00011011 == 1'b0) & ~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage0_flag00011011 == 1'b0) & (tmp_fu_809_p3 == 1'd1)))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage0_flag00011011 == 1'b0) & (tmp_fu_809_p3 == 1'd1))) begin
ap_NS_fsm = ap_ST_fsm_state80;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_pp0_stage1 : begin
if ((ap_block_pp0_stage1_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage2;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage1;
end
end
ap_ST_fsm_pp0_stage2 : begin
if ((ap_block_pp0_stage2_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage3;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage2;
end
end
ap_ST_fsm_pp0_stage3 : begin
if ((ap_block_pp0_stage3_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage4;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage3;
end
end
ap_ST_fsm_pp0_stage4 : begin
if ((ap_block_pp0_stage4_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage5;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage4;
end
end
ap_ST_fsm_pp0_stage5 : begin
if ((ap_block_pp0_stage5_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage6;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage5;
end
end
ap_ST_fsm_pp0_stage6 : begin
if ((ap_block_pp0_stage6_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage7;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage6;
end
end
ap_ST_fsm_pp0_stage7 : begin
if ((ap_block_pp0_stage7_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage8;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage7;
end
end
ap_ST_fsm_pp0_stage8 : begin
if ((ap_block_pp0_stage8_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage9;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage8;
end
end
ap_ST_fsm_pp0_stage9 : begin
if ((ap_block_pp0_stage9_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage10;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage9;
end
end
ap_ST_fsm_pp0_stage10 : begin
if ((ap_block_pp0_stage10_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage11;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage10;
end
end
ap_ST_fsm_pp0_stage11 : begin
if ((ap_block_pp0_stage11_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage12;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage11;
end
end
ap_ST_fsm_pp0_stage12 : begin
if ((ap_block_pp0_stage12_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage13;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage12;
end
end
ap_ST_fsm_pp0_stage13 : begin
if ((ap_block_pp0_stage13_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage14;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage13;
end
end
ap_ST_fsm_pp0_stage14 : begin
if ((ap_block_pp0_stage14_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage15;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage14;
end
end
ap_ST_fsm_pp0_stage15 : begin
if ((ap_block_pp0_stage15_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage16;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage15;
end
end
ap_ST_fsm_pp0_stage16 : begin
if ((ap_block_pp0_stage16_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage17;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage16;
end
end
ap_ST_fsm_pp0_stage17 : begin
if ((ap_block_pp0_stage17_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage18;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage17;
end
end
ap_ST_fsm_pp0_stage18 : begin
if ((ap_block_pp0_stage18_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage19;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage18;
end
end
ap_ST_fsm_pp0_stage19 : begin
if ((ap_block_pp0_stage19_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage20;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage19;
end
end
ap_ST_fsm_pp0_stage20 : begin
if ((ap_block_pp0_stage20_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage21;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage20;
end
end
ap_ST_fsm_pp0_stage21 : begin
if ((ap_block_pp0_stage21_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage22;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage21;
end
end
ap_ST_fsm_pp0_stage22 : begin
if ((ap_block_pp0_stage22_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage23;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage22;
end
end
ap_ST_fsm_pp0_stage23 : begin
if ((ap_block_pp0_stage23_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage24;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage23;
end
end
ap_ST_fsm_pp0_stage24 : begin
if ((ap_block_pp0_stage24_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage25;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage24;
end
end
ap_ST_fsm_pp0_stage25 : begin
if ((ap_block_pp0_stage25_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage26;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage25;
end
end
ap_ST_fsm_pp0_stage26 : begin
if ((ap_block_pp0_stage26_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage27;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage26;
end
end
ap_ST_fsm_pp0_stage27 : begin
if ((ap_block_pp0_stage27_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage28;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage27;
end
end
ap_ST_fsm_pp0_stage28 : begin
if ((ap_block_pp0_stage28_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage29;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage28;
end
end
ap_ST_fsm_pp0_stage29 : begin
if ((ap_block_pp0_stage29_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage30;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage29;
end
end
ap_ST_fsm_pp0_stage30 : begin
if ((ap_block_pp0_stage30_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage31;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage30;
end
end
ap_ST_fsm_pp0_stage31 : begin
if ((ap_block_pp0_stage31_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage32;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage31;
end
end
ap_ST_fsm_pp0_stage32 : begin
if ((ap_block_pp0_stage32_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage33;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage32;
end
end
ap_ST_fsm_pp0_stage33 : begin
if ((ap_block_pp0_stage33_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage34;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage33;
end
end
ap_ST_fsm_pp0_stage34 : begin
if ((ap_block_pp0_stage34_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage35;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage34;
end
end
ap_ST_fsm_pp0_stage35 : begin
if ((ap_block_pp0_stage35_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage36;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage35;
end
end
ap_ST_fsm_pp0_stage36 : begin
if ((ap_block_pp0_stage36_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage37;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage36;
end
end
ap_ST_fsm_pp0_stage37 : begin
if ((ap_block_pp0_stage37_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage38;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage37;
end
end
ap_ST_fsm_pp0_stage38 : begin
if ((ap_block_pp0_stage38_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage39;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage38;
end
end
ap_ST_fsm_pp0_stage39 : begin
if ((ap_block_pp0_stage39_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage40;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage39;
end
end
ap_ST_fsm_pp0_stage40 : begin
if ((ap_block_pp0_stage40_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage41;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage40;
end
end
ap_ST_fsm_pp0_stage41 : begin
if ((ap_block_pp0_stage41_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage42;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage41;
end
end
ap_ST_fsm_pp0_stage42 : begin
if ((ap_block_pp0_stage42_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage43;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage42;
end
end
ap_ST_fsm_pp0_stage43 : begin
if ((ap_block_pp0_stage43_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage44;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage43;
end
end
ap_ST_fsm_pp0_stage44 : begin
if ((ap_block_pp0_stage44_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage45;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage44;
end
end
ap_ST_fsm_pp0_stage45 : begin
if ((ap_block_pp0_stage45_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage46;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage45;
end
end
ap_ST_fsm_pp0_stage46 : begin
if ((ap_block_pp0_stage46_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage47;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage46;
end
end
ap_ST_fsm_pp0_stage47 : begin
if ((ap_block_pp0_stage47_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage48;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage47;
end
end
ap_ST_fsm_pp0_stage48 : begin
if ((ap_block_pp0_stage48_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage49;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage48;
end
end
ap_ST_fsm_pp0_stage49 : begin
if ((ap_block_pp0_stage49_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage50;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage49;
end
end
ap_ST_fsm_pp0_stage50 : begin
if ((ap_block_pp0_stage50_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage51;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage50;
end
end
ap_ST_fsm_pp0_stage51 : begin
if ((ap_block_pp0_stage51_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage52;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage51;
end
end
ap_ST_fsm_pp0_stage52 : begin
if ((ap_block_pp0_stage52_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage53;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage52;
end
end
ap_ST_fsm_pp0_stage53 : begin
if ((ap_block_pp0_stage53_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage54;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage53;
end
end
ap_ST_fsm_pp0_stage54 : begin
if ((ap_block_pp0_stage54_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage55;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage54;
end
end
ap_ST_fsm_pp0_stage55 : begin
if ((ap_block_pp0_stage55_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage56;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage55;
end
end
ap_ST_fsm_pp0_stage56 : begin
if ((ap_block_pp0_stage56_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage57;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage56;
end
end
ap_ST_fsm_pp0_stage57 : begin
if ((ap_block_pp0_stage57_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage58;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage57;
end
end
ap_ST_fsm_pp0_stage58 : begin
if ((ap_block_pp0_stage58_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage59;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage58;
end
end
ap_ST_fsm_pp0_stage59 : begin
if ((ap_block_pp0_stage59_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage60;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage59;
end
end
ap_ST_fsm_pp0_stage60 : begin
if ((ap_block_pp0_stage60_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage61;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage60;
end
end
ap_ST_fsm_pp0_stage61 : begin
if ((ap_block_pp0_stage61_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage62;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage61;
end
end
ap_ST_fsm_pp0_stage62 : begin
if ((ap_block_pp0_stage62_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage63;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage62;
end
end
ap_ST_fsm_pp0_stage63 : begin
if ((ap_block_pp0_stage63_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage64;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage63;
end
end
ap_ST_fsm_pp0_stage64 : begin
if ((ap_block_pp0_stage64_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage65;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage64;
end
end
ap_ST_fsm_pp0_stage65 : begin
if ((ap_block_pp0_stage65_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage66;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage65;
end
end
ap_ST_fsm_pp0_stage66 : begin
if ((ap_block_pp0_stage66_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage67;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage66;
end
end
ap_ST_fsm_pp0_stage67 : begin
if ((ap_block_pp0_stage67_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage68;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage67;
end
end
ap_ST_fsm_pp0_stage68 : begin
if ((ap_block_pp0_stage68_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage69;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage68;
end
end
ap_ST_fsm_pp0_stage69 : begin
if ((ap_block_pp0_stage69_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage70;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage69;
end
end
ap_ST_fsm_pp0_stage70 : begin
if ((ap_block_pp0_stage70_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage71;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage70;
end
end
ap_ST_fsm_pp0_stage71 : begin
if ((ap_block_pp0_stage71_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage72;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage71;
end
end
ap_ST_fsm_pp0_stage72 : begin
if ((ap_block_pp0_stage72_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage73;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage72;
end
end
ap_ST_fsm_pp0_stage73 : begin
if ((ap_block_pp0_stage73_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage74;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage73;
end
end
ap_ST_fsm_pp0_stage74 : begin
if ((ap_block_pp0_stage74_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage75;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage74;
end
end
ap_ST_fsm_pp0_stage75 : begin
if ((ap_block_pp0_stage75_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage76;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage75;
end
end
ap_ST_fsm_pp0_stage76 : begin
if ((ap_block_pp0_stage76_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage76;
end
end
ap_ST_fsm_state80 : begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_pp0_stage10 = ap_CS_fsm[32'd11];
assign ap_CS_fsm_pp0_stage11 = ap_CS_fsm[32'd12];
assign ap_CS_fsm_pp0_stage12 = ap_CS_fsm[32'd13];
assign ap_CS_fsm_pp0_stage13 = ap_CS_fsm[32'd14];
assign ap_CS_fsm_pp0_stage14 = ap_CS_fsm[32'd15];
assign ap_CS_fsm_pp0_stage15 = ap_CS_fsm[32'd16];
assign ap_CS_fsm_pp0_stage16 = ap_CS_fsm[32'd17];
assign ap_CS_fsm_pp0_stage17 = ap_CS_fsm[32'd18];
assign ap_CS_fsm_pp0_stage18 = ap_CS_fsm[32'd19];
assign ap_CS_fsm_pp0_stage19 = ap_CS_fsm[32'd20];
assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3];
assign ap_CS_fsm_pp0_stage20 = ap_CS_fsm[32'd21];
assign ap_CS_fsm_pp0_stage21 = ap_CS_fsm[32'd22];
assign ap_CS_fsm_pp0_stage22 = ap_CS_fsm[32'd23];
assign ap_CS_fsm_pp0_stage23 = ap_CS_fsm[32'd24];
assign ap_CS_fsm_pp0_stage24 = ap_CS_fsm[32'd25];
assign ap_CS_fsm_pp0_stage25 = ap_CS_fsm[32'd26];
assign ap_CS_fsm_pp0_stage26 = ap_CS_fsm[32'd27];
assign ap_CS_fsm_pp0_stage27 = ap_CS_fsm[32'd28];
assign ap_CS_fsm_pp0_stage28 = ap_CS_fsm[32'd29];
assign ap_CS_fsm_pp0_stage29 = ap_CS_fsm[32'd30];
assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4];
assign ap_CS_fsm_pp0_stage30 = ap_CS_fsm[32'd31];
assign ap_CS_fsm_pp0_stage31 = ap_CS_fsm[32'd32];
assign ap_CS_fsm_pp0_stage32 = ap_CS_fsm[32'd33];
assign ap_CS_fsm_pp0_stage33 = ap_CS_fsm[32'd34];
assign ap_CS_fsm_pp0_stage34 = ap_CS_fsm[32'd35];
assign ap_CS_fsm_pp0_stage35 = ap_CS_fsm[32'd36];
assign ap_CS_fsm_pp0_stage36 = ap_CS_fsm[32'd37];
assign ap_CS_fsm_pp0_stage37 = ap_CS_fsm[32'd38];
assign ap_CS_fsm_pp0_stage38 = ap_CS_fsm[32'd39];
assign ap_CS_fsm_pp0_stage39 = ap_CS_fsm[32'd40];
assign ap_CS_fsm_pp0_stage4 = ap_CS_fsm[32'd5];
assign ap_CS_fsm_pp0_stage40 = ap_CS_fsm[32'd41];
assign ap_CS_fsm_pp0_stage41 = ap_CS_fsm[32'd42];
assign ap_CS_fsm_pp0_stage42 = ap_CS_fsm[32'd43];
assign ap_CS_fsm_pp0_stage43 = ap_CS_fsm[32'd44];
assign ap_CS_fsm_pp0_stage44 = ap_CS_fsm[32'd45];
assign ap_CS_fsm_pp0_stage45 = ap_CS_fsm[32'd46];
assign ap_CS_fsm_pp0_stage46 = ap_CS_fsm[32'd47];
assign ap_CS_fsm_pp0_stage47 = ap_CS_fsm[32'd48];
assign ap_CS_fsm_pp0_stage48 = ap_CS_fsm[32'd49];
assign ap_CS_fsm_pp0_stage49 = ap_CS_fsm[32'd50];
assign ap_CS_fsm_pp0_stage5 = ap_CS_fsm[32'd6];
assign ap_CS_fsm_pp0_stage50 = ap_CS_fsm[32'd51];
assign ap_CS_fsm_pp0_stage51 = ap_CS_fsm[32'd52];
assign ap_CS_fsm_pp0_stage52 = ap_CS_fsm[32'd53];
assign ap_CS_fsm_pp0_stage53 = ap_CS_fsm[32'd54];
assign ap_CS_fsm_pp0_stage54 = ap_CS_fsm[32'd55];
assign ap_CS_fsm_pp0_stage55 = ap_CS_fsm[32'd56];
assign ap_CS_fsm_pp0_stage56 = ap_CS_fsm[32'd57];
assign ap_CS_fsm_pp0_stage57 = ap_CS_fsm[32'd58];
assign ap_CS_fsm_pp0_stage58 = ap_CS_fsm[32'd59];
assign ap_CS_fsm_pp0_stage59 = ap_CS_fsm[32'd60];
assign ap_CS_fsm_pp0_stage6 = ap_CS_fsm[32'd7];
assign ap_CS_fsm_pp0_stage60 = ap_CS_fsm[32'd61];
assign ap_CS_fsm_pp0_stage61 = ap_CS_fsm[32'd62];
assign ap_CS_fsm_pp0_stage62 = ap_CS_fsm[32'd63];
assign ap_CS_fsm_pp0_stage63 = ap_CS_fsm[32'd64];
assign ap_CS_fsm_pp0_stage64 = ap_CS_fsm[32'd65];
assign ap_CS_fsm_pp0_stage65 = ap_CS_fsm[32'd66];
assign ap_CS_fsm_pp0_stage66 = ap_CS_fsm[32'd67];
assign ap_CS_fsm_pp0_stage67 = ap_CS_fsm[32'd68];
assign ap_CS_fsm_pp0_stage68 = ap_CS_fsm[32'd69];
assign ap_CS_fsm_pp0_stage69 = ap_CS_fsm[32'd70];
assign ap_CS_fsm_pp0_stage7 = ap_CS_fsm[32'd8];
assign ap_CS_fsm_pp0_stage70 = ap_CS_fsm[32'd71];
assign ap_CS_fsm_pp0_stage71 = ap_CS_fsm[32'd72];
assign ap_CS_fsm_pp0_stage72 = ap_CS_fsm[32'd73];
assign ap_CS_fsm_pp0_stage76 = ap_CS_fsm[32'd77];
assign ap_CS_fsm_pp0_stage8 = ap_CS_fsm[32'd9];
assign ap_CS_fsm_pp0_stage9 = ap_CS_fsm[32'd10];
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state80 = ap_CS_fsm[32'd78];
assign ap_block_pp0_stage0_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage0_flag00011001 = ((tmp_reg_1932 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b0 == buffer_V_BVALID));
end
always @ (*) begin
ap_block_pp0_stage0_flag00011011 = ((tmp_reg_1932 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b0 == buffer_V_BVALID));
end
assign ap_block_pp0_stage10_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage10_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage10_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage11_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage11_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage11_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage12_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage12_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage12_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage13_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage13_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage13_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage14_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage14_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage14_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage15_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage15_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage15_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage16_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage16_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage16_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage17_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage17_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage17_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage18_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage18_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage18_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage19_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage19_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage19_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage1_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage1_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage1_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state3_io));
end
always @ (*) begin
ap_block_pp0_stage1_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state3_io));
end
assign ap_block_pp0_stage20_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage20_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage20_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage21_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage21_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage21_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage22_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage22_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage22_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage23_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage23_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage23_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage24_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage24_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage24_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage25_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage25_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage25_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage26_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage26_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage26_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage27_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage27_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage27_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage28_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage28_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage28_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage29_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage29_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage29_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage2_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage2_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage2_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage30_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage30_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage30_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage31_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage31_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage31_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage32_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage32_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage32_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage33_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage33_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage33_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage34_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage34_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage34_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage35_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage35_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage35_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage36_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage36_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage36_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage37_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage37_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage37_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage38_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage38_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage38_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage39_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage39_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage39_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage3_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage3_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage3_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage40_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage40_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage40_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state42_io));
end
always @ (*) begin
ap_block_pp0_stage40_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state42_io));
end
assign ap_block_pp0_stage41_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage41_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage41_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state43_io));
end
always @ (*) begin
ap_block_pp0_stage41_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state43_io));
end
assign ap_block_pp0_stage42_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage42_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage42_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state44_io));
end
always @ (*) begin
ap_block_pp0_stage42_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state44_io));
end
assign ap_block_pp0_stage43_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage43_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage43_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state45_io));
end
always @ (*) begin
ap_block_pp0_stage43_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state45_io));
end
assign ap_block_pp0_stage44_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage44_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage44_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state46_io));
end
always @ (*) begin
ap_block_pp0_stage44_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state46_io));
end
assign ap_block_pp0_stage45_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage45_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage45_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state47_io));
end
always @ (*) begin
ap_block_pp0_stage45_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state47_io));
end
assign ap_block_pp0_stage46_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage46_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage46_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state48_io));
end
always @ (*) begin
ap_block_pp0_stage46_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state48_io));
end
assign ap_block_pp0_stage47_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage47_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage47_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state49_io));
end
always @ (*) begin
ap_block_pp0_stage47_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state49_io));
end
assign ap_block_pp0_stage48_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage48_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage48_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state50_io));
end
always @ (*) begin
ap_block_pp0_stage48_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state50_io));
end
assign ap_block_pp0_stage49_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage49_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage49_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state51_io));
end
always @ (*) begin
ap_block_pp0_stage49_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state51_io));
end
assign ap_block_pp0_stage4_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage4_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage4_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage50_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage50_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage50_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state52_io));
end
always @ (*) begin
ap_block_pp0_stage50_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state52_io));
end
assign ap_block_pp0_stage51_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage51_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage51_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state53_io));
end
always @ (*) begin
ap_block_pp0_stage51_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state53_io));
end
assign ap_block_pp0_stage52_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage52_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage52_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state54_io));
end
always @ (*) begin
ap_block_pp0_stage52_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state54_io));
end
assign ap_block_pp0_stage53_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage53_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage53_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state55_io));
end
always @ (*) begin
ap_block_pp0_stage53_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state55_io));
end
assign ap_block_pp0_stage54_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage54_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage54_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state56_io));
end
always @ (*) begin
ap_block_pp0_stage54_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state56_io));
end
assign ap_block_pp0_stage55_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage55_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage55_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state57_io));
end
always @ (*) begin
ap_block_pp0_stage55_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state57_io));
end
assign ap_block_pp0_stage56_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage56_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage56_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state58_io));
end
always @ (*) begin
ap_block_pp0_stage56_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state58_io));
end
assign ap_block_pp0_stage57_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage57_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage57_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state59_io));
end
always @ (*) begin
ap_block_pp0_stage57_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state59_io));
end
assign ap_block_pp0_stage58_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage58_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage58_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state60_io));
end
always @ (*) begin
ap_block_pp0_stage58_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state60_io));
end
assign ap_block_pp0_stage59_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage59_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage59_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state61_io));
end
always @ (*) begin
ap_block_pp0_stage59_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state61_io));
end
assign ap_block_pp0_stage5_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage5_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage5_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage60_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage60_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage60_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state62_io));
end
always @ (*) begin
ap_block_pp0_stage60_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state62_io));
end
assign ap_block_pp0_stage61_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage61_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage61_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state63_io));
end
always @ (*) begin
ap_block_pp0_stage61_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state63_io));
end
assign ap_block_pp0_stage62_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage62_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage62_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state64_io));
end
always @ (*) begin
ap_block_pp0_stage62_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state64_io));
end
assign ap_block_pp0_stage63_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage63_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage63_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state65_io));
end
always @ (*) begin
ap_block_pp0_stage63_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state65_io));
end
assign ap_block_pp0_stage64_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage64_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage64_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state66_io));
end
always @ (*) begin
ap_block_pp0_stage64_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state66_io));
end
assign ap_block_pp0_stage65_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage65_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage65_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state67_io));
end
always @ (*) begin
ap_block_pp0_stage65_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state67_io));
end
assign ap_block_pp0_stage66_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage66_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage66_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state68_io));
end
always @ (*) begin
ap_block_pp0_stage66_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state68_io));
end
assign ap_block_pp0_stage67_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage67_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage67_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state69_io));
end
always @ (*) begin
ap_block_pp0_stage67_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state69_io));
end
assign ap_block_pp0_stage68_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage68_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage68_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state70_io));
end
always @ (*) begin
ap_block_pp0_stage68_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state70_io));
end
assign ap_block_pp0_stage69_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage69_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage69_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state71_io));
end
always @ (*) begin
ap_block_pp0_stage69_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state71_io));
end
assign ap_block_pp0_stage6_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage6_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage6_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage70_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage70_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage70_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state72_io));
end
always @ (*) begin
ap_block_pp0_stage70_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state72_io));
end
assign ap_block_pp0_stage71_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage71_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage71_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state73_io));
end
always @ (*) begin
ap_block_pp0_stage71_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state73_io));
end
assign ap_block_pp0_stage72_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage72_flag00001001 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage72_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state74_io));
end
always @ (*) begin
ap_block_pp0_stage72_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_block_state74_io));
end
assign ap_block_pp0_stage73_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage73_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage74_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage74_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage75_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage75_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage76_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage76_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage7_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage7_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage7_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage8_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage8_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage8_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_pp0_stage9_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage9_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_pp0_stage9_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state1 = ((1'b0 == ap_start) | (1'b0 == length_r_ap_vld_in_sig));
end
always @ (*) begin
ap_block_state10_pp0_stage8_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state11_pp0_stage9_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state12_pp0_stage10_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state13_pp0_stage11_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state14_pp0_stage12_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state15_pp0_stage13_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state16_pp0_stage14_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state17_pp0_stage15_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state18_pp0_stage16_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state19_pp0_stage17_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state20_pp0_stage18_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state21_pp0_stage19_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state22_pp0_stage20_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state23_pp0_stage21_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state24_pp0_stage22_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state25_pp0_stage23_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state26_pp0_stage24_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state27_pp0_stage25_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state28_pp0_stage26_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state29_pp0_stage27_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state30_pp0_stage28_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state31_pp0_stage29_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state32_pp0_stage30_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state33_pp0_stage31_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state34_pp0_stage32_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state35_pp0_stage33_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state36_pp0_stage34_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state37_pp0_stage35_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state38_pp0_stage36_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state39_pp0_stage37_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state3_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_ARREADY));
end
assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state40_pp0_stage38_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state41_pp0_stage39_iter0 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_RVALID));
end
always @ (*) begin
ap_block_state42_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_AWREADY));
end
assign ap_block_state42_pp0_stage40_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state43_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state43_pp0_stage41_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state44_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state44_pp0_stage42_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state45_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state45_pp0_stage43_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state46_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state46_pp0_stage44_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state47_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state47_pp0_stage45_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state48_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state48_pp0_stage46_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state49_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state49_pp0_stage47_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state50_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state50_pp0_stage48_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state51_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state51_pp0_stage49_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state52_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state52_pp0_stage50_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state53_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state53_pp0_stage51_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state54_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state54_pp0_stage52_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state55_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state55_pp0_stage53_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state56_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state56_pp0_stage54_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state57_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state57_pp0_stage55_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state58_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state58_pp0_stage56_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state59_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state59_pp0_stage57_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state60_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state60_pp0_stage58_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state61_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state61_pp0_stage59_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state62_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state62_pp0_stage60_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state63_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state63_pp0_stage61_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state64_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state64_pp0_stage62_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state65_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state65_pp0_stage63_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state66_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state66_pp0_stage64_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state67_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state67_pp0_stage65_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state68_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state68_pp0_stage66_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state69_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state69_pp0_stage67_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state6_pp0_stage4_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state70_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state70_pp0_stage68_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state71_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state71_pp0_stage69_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state72_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state72_pp0_stage70_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state73_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state73_pp0_stage71_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state74_io = ((tmp_reg_1932 == 1'd0) & (1'b0 == ap_sig_ioackin_buffer_V_WREADY));
end
assign ap_block_state74_pp0_stage72_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state75_pp0_stage73_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state76_pp0_stage74_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state77_pp0_stage75_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state78_pp0_stage76_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state79_pp0_stage0_iter1 = ((tmp_reg_1932 == 1'd0) & (1'b0 == buffer_V_BVALID));
end
assign ap_block_state7_pp0_stage5_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state8_pp0_stage6_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state9_pp0_stage7_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_condition_7926 = ((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0));
end
always @ (*) begin
ap_condition_7931 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_1932 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage40));
end
always @ (*) begin
ap_condition_7969 = ((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op143_call_state3));
end
always @ (*) begin
ap_condition_7973 = ((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_predicate_op152_call_state4) & (ap_block_pp0_stage2_flag00000000 == 1'b0));
end
always @ (*) begin
ap_condition_7977 = ((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_predicate_op162_call_state5) & (ap_block_pp0_stage3_flag00000000 == 1'b0));
end
always @ (*) begin
ap_condition_7981 = ((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_predicate_op173_call_state6) & (ap_block_pp0_stage4_flag00000000 == 1'b0));
end
always @ (*) begin
ap_condition_7985 = ((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_predicate_op185_call_state7) & (ap_block_pp0_stage5_flag00000000 == 1'b0));
end
always @ (*) begin
ap_condition_7989 = ((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_predicate_op198_call_state8) & (ap_block_pp0_stage6_flag00000000 == 1'b0));
end
always @ (*) begin
ap_condition_7993 = ((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_predicate_op212_call_state9) & (ap_block_pp0_stage7_flag00000000 == 1'b0));
end
always @ (*) begin
ap_condition_7997 = ((1'b1 == ap_CS_fsm_pp0_stage8) & (ap_block_pp0_stage8_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op227_call_state10));
end
always @ (*) begin
ap_condition_8001 = ((1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op243_call_state11));
end
always @ (*) begin
ap_condition_8005 = ((1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op260_call_state12));
end
always @ (*) begin
ap_condition_8008 = ((1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op324_call_state13));
end
always @ (*) begin
ap_condition_8011 = ((1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op387_call_state14));
end
always @ (*) begin
ap_condition_8014 = ((1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op409_call_state15));
end
always @ (*) begin
ap_condition_8017 = ((1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op431_call_state16));
end
always @ (*) begin
ap_condition_8020 = ((1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op453_call_state17));
end
always @ (*) begin
ap_condition_8023 = ((1'b1 == ap_CS_fsm_pp0_stage16) & (ap_block_pp0_stage16_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op475_call_state18));
end
always @ (*) begin
ap_condition_8026 = ((1'b1 == ap_CS_fsm_pp0_stage17) & (ap_block_pp0_stage17_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op497_call_state19));
end
always @ (*) begin
ap_condition_8029 = ((1'b1 == ap_CS_fsm_pp0_stage18) & (ap_block_pp0_stage18_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op519_call_state20));
end
always @ (*) begin
ap_condition_8032 = ((1'b1 == ap_CS_fsm_pp0_stage19) & (ap_block_pp0_stage19_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op541_call_state21));
end
always @ (*) begin
ap_condition_8035 = ((1'b1 == ap_CS_fsm_pp0_stage20) & (ap_block_pp0_stage20_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op563_call_state22));
end
always @ (*) begin
ap_condition_8038 = ((1'b1 == ap_CS_fsm_pp0_stage21) & (ap_block_pp0_stage21_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op585_call_state23));
end
always @ (*) begin
ap_condition_8041 = ((1'b1 == ap_CS_fsm_pp0_stage22) & (ap_block_pp0_stage22_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op607_call_state24));
end
always @ (*) begin
ap_condition_8044 = ((1'b1 == ap_CS_fsm_pp0_stage23) & (ap_block_pp0_stage23_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op629_call_state25));
end
always @ (*) begin
ap_condition_8047 = ((1'b1 == ap_CS_fsm_pp0_stage24) & (ap_block_pp0_stage24_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op651_call_state26));
end
always @ (*) begin
ap_condition_8050 = ((1'b1 == ap_CS_fsm_pp0_stage25) & (ap_block_pp0_stage25_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op673_call_state27));
end
always @ (*) begin
ap_condition_8053 = ((1'b1 == ap_CS_fsm_pp0_stage26) & (ap_block_pp0_stage26_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op695_call_state28));
end
always @ (*) begin
ap_condition_8056 = ((1'b1 == ap_CS_fsm_pp0_stage27) & (ap_block_pp0_stage27_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op717_call_state29));
end
always @ (*) begin
ap_condition_8059 = ((1'b1 == ap_CS_fsm_pp0_stage28) & (ap_block_pp0_stage28_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op739_call_state30));
end
always @ (*) begin
ap_condition_8062 = ((1'b1 == ap_CS_fsm_pp0_stage29) & (ap_block_pp0_stage29_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op761_call_state31));
end
always @ (*) begin
ap_condition_8065 = ((1'b1 == ap_CS_fsm_pp0_stage30) & (ap_block_pp0_stage30_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op783_call_state32));
end
always @ (*) begin
ap_condition_8068 = ((1'b1 == ap_CS_fsm_pp0_stage31) & (ap_block_pp0_stage31_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op805_call_state33));
end
always @ (*) begin
ap_condition_8071 = ((1'b1 == ap_CS_fsm_pp0_stage32) & (ap_block_pp0_stage32_flag00000000 == 1'b0) & (1'b1 == ap_predicate_op827_call_state34));
end
assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
always @ (*) begin
ap_predicate_op143_call_state3 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1));
end
always @ (*) begin
ap_predicate_op143_call_state3_state2 = ((1'd0 == tmp_fu_809_p3) & (tmp_66_fu_821_p2 == 1'd1));
end
always @ (*) begin
ap_predicate_op152_call_state4 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1));
end
always @ (*) begin
ap_predicate_op152_call_state4_state3 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_fu_861_p2 == 1'd1));
end
always @ (*) begin
ap_predicate_op162_call_state5 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001));
end
always @ (*) begin
ap_predicate_op162_call_state5_state4 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_fu_884_p2));
end
always @ (*) begin
ap_predicate_op173_call_state6 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011));
end
always @ (*) begin
ap_predicate_op173_call_state6_state5 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_fu_907_p2));
end
always @ (*) begin
ap_predicate_op185_call_state7 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021));
end
always @ (*) begin
ap_predicate_op185_call_state7_state6 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_fu_930_p2));
end
always @ (*) begin
ap_predicate_op198_call_state8 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031));
end
always @ (*) begin
ap_predicate_op198_call_state8_state7 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_fu_953_p2));
end
always @ (*) begin
ap_predicate_op212_call_state9 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041));
end
always @ (*) begin
ap_predicate_op212_call_state9_state8 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_fu_976_p2));
end
always @ (*) begin
ap_predicate_op227_call_state10 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051));
end
always @ (*) begin
ap_predicate_op227_call_state10_state9 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_fu_999_p2));
end
always @ (*) begin
ap_predicate_op243_call_state11 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061));
end
always @ (*) begin
ap_predicate_op243_call_state11_state10 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_fu_1022_p2));
end
always @ (*) begin
ap_predicate_op260_call_state12 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071));
end
always @ (*) begin
ap_predicate_op260_call_state12_state11 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_fu_1045_p2));
end
always @ (*) begin
ap_predicate_op307_call_state13 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1));
end
always @ (*) begin
ap_predicate_op324_call_state13 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081));
end
always @ (*) begin
ap_predicate_op324_call_state13_state12 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_fu_1068_p2));
end
always @ (*) begin
ap_predicate_op370_call_state14 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1));
end
always @ (*) begin
ap_predicate_op387_call_state14 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211));
end
always @ (*) begin
ap_predicate_op387_call_state14_state13 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_fu_1271_p2));
end
always @ (*) begin
ap_predicate_op392_call_state15 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001));
end
always @ (*) begin
ap_predicate_op409_call_state15 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215));
end
always @ (*) begin
ap_predicate_op409_call_state15_state14 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215));
end
always @ (*) begin
ap_predicate_op414_call_state16 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011));
end
always @ (*) begin
ap_predicate_op431_call_state16 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219));
end
always @ (*) begin
ap_predicate_op431_call_state16_state15 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219));
end
always @ (*) begin
ap_predicate_op436_call_state17 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021));
end
always @ (*) begin
ap_predicate_op453_call_state17 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223));
end
always @ (*) begin
ap_predicate_op453_call_state17_state16 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223));
end
always @ (*) begin
ap_predicate_op458_call_state18 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031));
end
always @ (*) begin
ap_predicate_op475_call_state18 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227));
end
always @ (*) begin
ap_predicate_op475_call_state18_state17 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227));
end
always @ (*) begin
ap_predicate_op480_call_state19 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041));
end
always @ (*) begin
ap_predicate_op497_call_state19 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231));
end
always @ (*) begin
ap_predicate_op497_call_state19_state18 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231));
end
always @ (*) begin
ap_predicate_op502_call_state20 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051));
end
always @ (*) begin
ap_predicate_op519_call_state20 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235));
end
always @ (*) begin
ap_predicate_op519_call_state20_state19 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235));
end
always @ (*) begin
ap_predicate_op524_call_state21 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061));
end
always @ (*) begin
ap_predicate_op541_call_state21 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239));
end
always @ (*) begin
ap_predicate_op541_call_state21_state20 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239));
end
always @ (*) begin
ap_predicate_op546_call_state22 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071));
end
always @ (*) begin
ap_predicate_op563_call_state22 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243));
end
always @ (*) begin
ap_predicate_op563_call_state22_state21 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243));
end
always @ (*) begin
ap_predicate_op568_call_state23 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081));
end
always @ (*) begin
ap_predicate_op585_call_state23 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247));
end
always @ (*) begin
ap_predicate_op585_call_state23_state22 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247));
end
always @ (*) begin
ap_predicate_op590_call_state24 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211));
end
always @ (*) begin
ap_predicate_op607_call_state24 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251));
end
always @ (*) begin
ap_predicate_op607_call_state24_state23 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251));
end
always @ (*) begin
ap_predicate_op612_call_state25 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215));
end
always @ (*) begin
ap_predicate_op629_call_state25 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255));
end
always @ (*) begin
ap_predicate_op629_call_state25_state24 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255));
end
always @ (*) begin
ap_predicate_op634_call_state26 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219));
end
always @ (*) begin
ap_predicate_op651_call_state26 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259));
end
always @ (*) begin
ap_predicate_op651_call_state26_state25 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259));
end
always @ (*) begin
ap_predicate_op656_call_state27 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223));
end
always @ (*) begin
ap_predicate_op673_call_state27 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263));
end
always @ (*) begin
ap_predicate_op673_call_state27_state26 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263));
end
always @ (*) begin
ap_predicate_op678_call_state28 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227));
end
always @ (*) begin
ap_predicate_op695_call_state28 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267));
end
always @ (*) begin
ap_predicate_op695_call_state28_state27 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267));
end
always @ (*) begin
ap_predicate_op700_call_state29 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231));
end
always @ (*) begin
ap_predicate_op717_call_state29 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267) & (1'd1 == tmp_5_25_reg_2271));
end
always @ (*) begin
ap_predicate_op717_call_state29_state28 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267) & (1'd1 == tmp_5_25_reg_2271));
end
always @ (*) begin
ap_predicate_op722_call_state30 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235));
end
always @ (*) begin
ap_predicate_op739_call_state30 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267) & (1'd1 == tmp_5_25_reg_2271) & (1'd1 == tmp_5_26_reg_2275));
end
always @ (*) begin
ap_predicate_op739_call_state30_state29 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267) & (1'd1 == tmp_5_25_reg_2271) & (1'd1 == tmp_5_26_reg_2275));
end
always @ (*) begin
ap_predicate_op744_call_state31 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239));
end
always @ (*) begin
ap_predicate_op761_call_state31 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267) & (1'd1 == tmp_5_25_reg_2271) & (1'd1 == tmp_5_26_reg_2275) & (1'd1 == tmp_5_27_reg_2279));
end
always @ (*) begin
ap_predicate_op761_call_state31_state30 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267) & (1'd1 == tmp_5_25_reg_2271) & (1'd1 == tmp_5_26_reg_2275) & (1'd1 == tmp_5_27_reg_2279));
end
always @ (*) begin
ap_predicate_op766_call_state32 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243));
end
always @ (*) begin
ap_predicate_op783_call_state32 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267) & (1'd1 == tmp_5_25_reg_2271) & (1'd1 == tmp_5_26_reg_2275) & (1'd1 == tmp_5_27_reg_2279) & (1'd1 == tmp_5_28_reg_2283));
end
always @ (*) begin
ap_predicate_op783_call_state32_state31 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267) & (1'd1 == tmp_5_25_reg_2271) & (1'd1 == tmp_5_26_reg_2275) & (1'd1 == tmp_5_27_reg_2279) & (1'd1 == tmp_5_28_reg_2283));
end
always @ (*) begin
ap_predicate_op788_call_state33 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247));
end
always @ (*) begin
ap_predicate_op805_call_state33 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267) & (1'd1 == tmp_5_25_reg_2271) & (1'd1 == tmp_5_26_reg_2275) & (1'd1 == tmp_5_27_reg_2279) & (1'd1 == tmp_5_28_reg_2283) & (1'd1 == tmp_5_29_reg_2287));
end
always @ (*) begin
ap_predicate_op805_call_state33_state32 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267) & (1'd1 == tmp_5_25_reg_2271) & (1'd1 == tmp_5_26_reg_2275) & (1'd1 == tmp_5_27_reg_2279) & (1'd1 == tmp_5_28_reg_2283) & (1'd1 == tmp_5_29_reg_2287));
end
always @ (*) begin
ap_predicate_op810_call_state34 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251));
end
always @ (*) begin
ap_predicate_op827_call_state34 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267) & (1'd1 == tmp_5_25_reg_2271) & (1'd1 == tmp_5_26_reg_2275) & (1'd1 == tmp_5_27_reg_2279) & (1'd1 == tmp_5_28_reg_2283) & (1'd1 == tmp_5_29_reg_2287) & (1'd1 == tmp_5_30_reg_2291));
end
always @ (*) begin
ap_predicate_op827_call_state34_state33 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267) & (1'd1 == tmp_5_25_reg_2271) & (1'd1 == tmp_5_26_reg_2275) & (1'd1 == tmp_5_27_reg_2279) & (1'd1 == tmp_5_28_reg_2283) & (1'd1 == tmp_5_29_reg_2287) & (1'd1 == tmp_5_30_reg_2291));
end
always @ (*) begin
ap_predicate_op832_call_state35 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255));
end
always @ (*) begin
ap_predicate_op851_call_state36 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259));
end
always @ (*) begin
ap_predicate_op869_call_state37 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263));
end
always @ (*) begin
ap_predicate_op886_call_state38 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267));
end
always @ (*) begin
ap_predicate_op902_call_state39 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267) & (1'd1 == tmp_5_25_reg_2271));
end
always @ (*) begin
ap_predicate_op917_call_state40 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267) & (1'd1 == tmp_5_25_reg_2271) & (1'd1 == tmp_5_26_reg_2275));
end
always @ (*) begin
ap_predicate_op931_call_state41 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267) & (1'd1 == tmp_5_25_reg_2271) & (1'd1 == tmp_5_26_reg_2275) & (1'd1 == tmp_5_27_reg_2279));
end
always @ (*) begin
ap_predicate_op943_call_state42 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267) & (1'd1 == tmp_5_25_reg_2271) & (1'd1 == tmp_5_26_reg_2275) & (1'd1 == tmp_5_27_reg_2279) & (1'd1 == tmp_5_28_reg_2283));
end
always @ (*) begin
ap_predicate_op955_call_state43 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267) & (1'd1 == tmp_5_25_reg_2271) & (1'd1 == tmp_5_26_reg_2275) & (1'd1 == tmp_5_27_reg_2279) & (1'd1 == tmp_5_28_reg_2283) & (1'd1 == tmp_5_29_reg_2287));
end
always @ (*) begin
ap_predicate_op969_call_state44 = ((tmp_reg_1932 == 1'd0) & (tmp_66_reg_1936 == 1'd1) & (tmp_5_1_reg_1991 == 1'd1) & (1'd1 == tmp_5_2_reg_2001) & (1'd1 == tmp_5_3_reg_2011) & (1'd1 == tmp_5_4_reg_2021) & (1'd1 == tmp_5_5_reg_2031) & (1'd1 == tmp_5_6_reg_2041) & (1'd1 == tmp_5_7_reg_2051) & (1'd1 == tmp_5_8_reg_2061) & (1'd1 == tmp_5_9_reg_2071) & (1'd1 == tmp_5_s_reg_2081) & (1'd1 == tmp_5_10_reg_2211) & (1'd1 == tmp_5_11_reg_2215) & (1'd1 == tmp_5_12_reg_2219) & (1'd1 == tmp_5_13_reg_2223) & (1'd1 == tmp_5_14_reg_2227) & (1'd1 == tmp_5_15_reg_2231) & (1'd1 == tmp_5_16_reg_2235) & (1'd1 == tmp_5_17_reg_2239) & (1'd1 == tmp_5_18_reg_2243) & (1'd1 == tmp_5_19_reg_2247) & (1'd1 == tmp_5_20_reg_2251) & (1'd1 == tmp_5_21_reg_2255) & (1'd1 == tmp_5_22_reg_2259) & (1'd1 == tmp_5_23_reg_2263) & (1'd1 == tmp_5_24_reg_2267) & (1'd1 == tmp_5_25_reg_2271) & (1'd1 == tmp_5_26_reg_2275) & (1'd1 == tmp_5_27_reg_2279) & (1'd1 == tmp_5_28_reg_2283) & (1'd1 == tmp_5_29_reg_2287) & (1'd1 == tmp_5_30_reg_2291));
end
always @ (*) begin
ap_rst_n_inv = ~ap_rst_n;
end
assign buffer_V_ARADDR = tmp_1_fu_830_p1;
assign counter_V_0_10_fu_1383_p2 = (tmp_8_10_cast_fu_1380_p1 + iv_V);
assign counter_V_0_11_fu_1402_p2 = (tmp_8_11_cast_fu_1399_p1 + iv_V);
assign counter_V_0_12_fu_1415_p2 = (tmp_8_12_cast_fu_1412_p1 + iv_V);
assign counter_V_0_13_fu_1428_p2 = (tmp_8_13_cast_fu_1425_p1 + iv_V);
assign counter_V_0_14_fu_1441_p2 = (tmp_8_14_cast_fu_1438_p1 + iv_V);
assign counter_V_0_15_fu_1454_p2 = (tmp_8_15_cast_fu_1451_p1 + iv_V);
assign counter_V_0_16_fu_1467_p2 = (tmp_8_16_cast_fu_1464_p1 + iv_V);
assign counter_V_0_17_fu_1480_p2 = (tmp_8_17_cast_fu_1477_p1 + iv_V);
assign counter_V_0_18_fu_1493_p2 = (tmp_8_18_cast_fu_1490_p1 + iv_V);
assign counter_V_0_19_fu_1506_p2 = (tmp_8_19_cast_fu_1503_p1 + iv_V);
assign counter_V_0_1_fu_878_p2 = (tmp_8_cast_6_fu_875_p1 + iv_V);
assign counter_V_0_20_fu_1519_p2 = (tmp_8_20_cast_fu_1516_p1 + iv_V);
assign counter_V_0_21_fu_1532_p2 = (tmp_8_21_cast_fu_1529_p1 + iv_V);
assign counter_V_0_22_fu_1545_p2 = (tmp_8_22_cast_fu_1542_p1 + iv_V);
assign counter_V_0_23_fu_1558_p2 = (tmp_8_23_cast_fu_1555_p1 + iv_V);
assign counter_V_0_24_fu_1571_p2 = (tmp_8_24_cast_fu_1568_p1 + iv_V);
assign counter_V_0_25_fu_1584_p2 = (tmp_8_25_cast_fu_1581_p1 + iv_V);
assign counter_V_0_26_fu_1597_p2 = (tmp_8_26_cast_fu_1594_p1 + iv_V);
assign counter_V_0_27_fu_1610_p2 = (tmp_8_27_cast_fu_1607_p1 + iv_V);
assign counter_V_0_28_fu_1623_p2 = (tmp_8_28_cast_fu_1620_p1 + iv_V);
assign counter_V_0_29_fu_1636_p2 = (tmp_8_29_cast_fu_1633_p1 + iv_V);
assign counter_V_0_2_fu_901_p2 = (tmp_8_1_cast_fu_898_p1 + iv_V);
assign counter_V_0_30_fu_1649_p2 = (tmp_8_30_cast_fu_1646_p1 + iv_V);
assign counter_V_0_3_fu_924_p2 = (tmp_8_2_cast_fu_921_p1 + iv_V);
assign counter_V_0_4_fu_947_p2 = (tmp_8_3_cast_fu_944_p1 + iv_V);
assign counter_V_0_5_fu_970_p2 = (tmp_8_4_cast_fu_967_p1 + iv_V);
assign counter_V_0_6_fu_993_p2 = (tmp_8_5_cast_fu_990_p1 + iv_V);
assign counter_V_0_7_fu_1016_p2 = (tmp_8_6_cast_fu_1013_p1 + iv_V);
assign counter_V_0_8_fu_1039_p2 = (tmp_8_7_cast_fu_1036_p1 + iv_V);
assign counter_V_0_9_fu_1062_p2 = (tmp_8_8_cast_fu_1059_p1 + iv_V);
assign counter_V_0_s_fu_1265_p2 = (tmp_8_9_cast_fu_1262_p1 + iv_V);
assign counter_V_fu_855_p2 = (tmp_2_fu_851_p1 + iv_V);
assign grp_aestest_fu_744_ap_start = ap_reg_grp_aestest_fu_744_ap_start;
assign grp_fu_786_p2 = (reg_752 ^ grp_aestest_fu_744_ap_return);
assign grp_fu_794_p2 = (reg_756 ^ grp_aestest_fu_744_ap_return);
assign grp_fu_802_p2 = (reg_760 ^ grp_aestest_fu_744_ap_return);
assign i_fu_1389_p2 = (i_op_assign_reg_732 + 16'd32);
assign i_op_assign_cast1_fu_817_p1 = i_op_assign_phi_fu_736_p4;
assign tmp_10_fu_1421_p1 = tmp_s_reg_2015;
assign tmp_11_cast_fu_940_p1 = tmp_11_fu_935_p2;
assign tmp_11_fu_935_p2 = (tmp_98_reg_1940 | 15'd5);
assign tmp_12_fu_1434_p1 = tmp_11_reg_2025;
assign tmp_13_cast_fu_963_p1 = tmp_13_fu_958_p2;
assign tmp_13_fu_958_p2 = (tmp_98_reg_1940 | 15'd6);
assign tmp_14_fu_1447_p1 = tmp_13_reg_2035;
assign tmp_15_cast_fu_986_p1 = tmp_15_fu_981_p2;
assign tmp_15_fu_981_p2 = (tmp_98_reg_1940 | 15'd7);
assign tmp_16_fu_1460_p1 = tmp_15_reg_2045;
assign tmp_17_cast_fu_1009_p1 = tmp_17_fu_1004_p2;
assign tmp_17_fu_1004_p2 = (tmp_98_reg_1940 | 15'd8);
assign tmp_18_fu_1473_p1 = tmp_17_reg_2055;
assign tmp_19_cast_fu_1032_p1 = tmp_19_fu_1027_p2;
assign tmp_19_fu_1027_p2 = (tmp_98_reg_1940 | 15'd9);
assign tmp_1_fu_830_p1 = i_op_assign_reg_732;
assign tmp_20_fu_1486_p1 = tmp_19_reg_2065;
assign tmp_21_cast_fu_1055_p1 = tmp_21_fu_1050_p2;
assign tmp_21_fu_1050_p2 = (tmp_98_reg_1940 | 15'd10);
assign tmp_22_fu_1499_p1 = tmp_21_reg_2075;
assign tmp_23_cast_fu_1078_p1 = tmp_23_fu_1073_p2;
assign tmp_23_fu_1073_p2 = (tmp_98_reg_1940 | 15'd11);
assign tmp_24_fu_1512_p1 = tmp_23_reg_2085;
assign tmp_25_cast_fu_1087_p1 = tmp_25_fu_1082_p2;
assign tmp_25_fu_1082_p2 = (tmp_98_reg_1940 | 15'd12);
assign tmp_26_fu_1525_p1 = tmp_25_reg_2091;
assign tmp_27_cast_fu_1096_p1 = tmp_27_fu_1091_p2;
assign tmp_27_fu_1091_p2 = (tmp_98_reg_1940 | 15'd13);
assign tmp_28_fu_1538_p1 = tmp_27_reg_2097;
assign tmp_29_cast_fu_1105_p1 = tmp_29_fu_1100_p2;
assign tmp_29_fu_1100_p2 = (tmp_98_reg_1940 | 15'd14);
assign tmp_2_fu_851_p1 = i_op_assign_reg_732;
assign tmp_30_fu_1551_p1 = tmp_29_reg_2103;
assign tmp_31_cast_fu_1114_p1 = tmp_31_fu_1109_p2;
assign tmp_31_fu_1109_p2 = (tmp_98_reg_1940 | 15'd15);
assign tmp_32_fu_1564_p1 = tmp_31_reg_2109;
assign tmp_33_cast_fu_1123_p1 = tmp_33_fu_1118_p2;
assign tmp_33_fu_1118_p2 = (tmp_98_reg_1940 | 15'd16);
assign tmp_34_fu_1577_p1 = tmp_33_reg_2115;
assign tmp_35_cast_fu_1132_p1 = tmp_35_fu_1127_p2;
assign tmp_35_fu_1127_p2 = (tmp_98_reg_1940 | 15'd17);
assign tmp_36_fu_1590_p1 = tmp_35_reg_2121;
assign tmp_37_cast_fu_1141_p1 = tmp_37_fu_1136_p2;
assign tmp_37_fu_1136_p2 = (tmp_98_reg_1940 | 15'd18);
assign tmp_38_fu_1603_p1 = tmp_37_reg_2127;
assign tmp_39_cast_fu_1150_p1 = tmp_39_fu_1145_p2;
assign tmp_39_fu_1145_p2 = (tmp_98_reg_1940 | 15'd19);
assign tmp_40_fu_1616_p1 = tmp_39_reg_2133;
assign tmp_41_cast_fu_1159_p1 = tmp_41_fu_1154_p2;
assign tmp_41_fu_1154_p2 = (tmp_98_reg_1940 | 15'd20);
assign tmp_42_fu_1629_p1 = tmp_41_reg_2139;
assign tmp_43_cast_fu_1168_p1 = tmp_43_fu_1163_p2;
assign tmp_43_fu_1163_p2 = (tmp_98_reg_1940 | 15'd21);
assign tmp_44_fu_1642_p1 = tmp_43_reg_2145;
assign tmp_45_cast_fu_1177_p1 = tmp_45_fu_1172_p2;
assign tmp_45_fu_1172_p2 = (tmp_98_reg_1940 | 15'd22);
assign tmp_46_fu_1655_p1 = tmp_45_reg_2151;
assign tmp_47_cast_fu_1186_p1 = tmp_47_fu_1181_p2;
assign tmp_47_fu_1181_p2 = (tmp_98_reg_1940 | 15'd23);
assign tmp_48_fu_1659_p1 = tmp_47_reg_2157;
assign tmp_49_cast_fu_1195_p1 = tmp_49_fu_1190_p2;
assign tmp_49_fu_1190_p2 = (tmp_98_reg_1940 | 15'd24);
assign tmp_4_cast_fu_847_p1 = tmp_4_fu_841_p2;
assign tmp_4_fu_841_p2 = (tmp_98_fu_826_p1 | 15'd1);
assign tmp_50_fu_1663_p1 = tmp_49_reg_2163;
assign tmp_51_cast_fu_1204_p1 = tmp_51_fu_1199_p2;
assign tmp_51_fu_1199_p2 = (tmp_98_reg_1940 | 15'd25);
assign tmp_52_fu_1667_p1 = tmp_51_reg_2169;
assign tmp_53_cast_fu_1213_p1 = tmp_53_fu_1208_p2;
assign tmp_53_fu_1208_p2 = (tmp_98_reg_1940 | 15'd26);
assign tmp_54_fu_1671_p1 = tmp_53_reg_2175;
assign tmp_55_cast_fu_1222_p1 = tmp_55_fu_1217_p2;
assign tmp_55_fu_1217_p2 = (tmp_98_reg_1940 | 15'd27);
assign tmp_56_fu_1675_p1 = tmp_55_reg_2181;
assign tmp_57_cast_fu_1231_p1 = tmp_57_fu_1226_p2;
assign tmp_57_fu_1226_p2 = (tmp_98_reg_1940 | 15'd28);
assign tmp_58_fu_1679_p1 = tmp_57_reg_2187;
assign tmp_59_cast_fu_1240_p1 = tmp_59_fu_1235_p2;
assign tmp_59_fu_1235_p2 = (tmp_98_reg_1940 | 15'd29);
assign tmp_5_10_fu_1271_p2 = ((tmp_23_cast_fu_1078_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_11_fu_1276_p2 = ((tmp_25_cast_fu_1087_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_12_fu_1281_p2 = ((tmp_27_cast_fu_1096_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_13_fu_1286_p2 = ((tmp_29_cast_fu_1105_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_14_fu_1291_p2 = ((tmp_31_cast_fu_1114_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_15_fu_1296_p2 = ((tmp_33_cast_fu_1123_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_16_fu_1301_p2 = ((tmp_35_cast_fu_1132_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_17_fu_1306_p2 = ((tmp_37_cast_fu_1141_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_18_fu_1311_p2 = ((tmp_39_cast_fu_1150_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_19_fu_1316_p2 = ((tmp_41_cast_fu_1159_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_1_fu_861_p2 = ((tmp_4_cast_fu_847_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_20_fu_1321_p2 = ((tmp_43_cast_fu_1168_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_21_fu_1326_p2 = ((tmp_45_cast_fu_1177_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_22_fu_1331_p2 = ((tmp_47_cast_fu_1186_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_23_fu_1336_p2 = ((tmp_49_cast_fu_1195_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_24_fu_1341_p2 = ((tmp_51_cast_fu_1204_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_25_fu_1346_p2 = ((tmp_53_cast_fu_1213_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_26_fu_1351_p2 = ((tmp_55_cast_fu_1222_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_27_fu_1356_p2 = ((tmp_57_cast_fu_1231_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_28_fu_1361_p2 = ((tmp_59_cast_fu_1240_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_29_fu_1366_p2 = ((tmp_61_cast_fu_1249_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_2_fu_884_p2 = ((tmp_6_cast_fu_871_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_30_fu_1371_p2 = ((tmp_63_cast_fu_1258_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_3_fu_907_p2 = ((tmp_8_cast_fu_894_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_4_fu_930_p2 = ((tmp_cast_fu_917_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_5_fu_953_p2 = ((tmp_11_cast_fu_940_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_6_fu_976_p2 = ((tmp_13_cast_fu_963_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_7_fu_999_p2 = ((tmp_15_cast_fu_986_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_8_fu_1022_p2 = ((tmp_17_cast_fu_1009_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_9_fu_1045_p2 = ((tmp_19_cast_fu_1032_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_5_fu_1376_p1 = tmp_4_reg_1985;
assign tmp_5_s_fu_1068_p2 = ((tmp_21_cast_fu_1055_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_60_fu_1683_p1 = tmp_59_reg_2193;
assign tmp_61_cast_fu_1249_p1 = tmp_61_fu_1244_p2;
assign tmp_61_fu_1244_p2 = (tmp_98_reg_1940 | 15'd30);
assign tmp_62_fu_1687_p1 = tmp_61_reg_2199;
assign tmp_63_cast_fu_1258_p1 = tmp_63_fu_1253_p2;
assign tmp_63_fu_1253_p2 = (tmp_98_reg_1940 | 15'd31);
assign tmp_64_fu_1691_p1 = tmp_63_reg_2205;
assign tmp_66_fu_821_p2 = ((i_op_assign_cast1_fu_817_p1 < length_r_in_sig) ? 1'b1 : 1'b0);
assign tmp_6_cast_fu_871_p1 = tmp_6_fu_866_p2;
assign tmp_6_fu_866_p2 = (tmp_98_reg_1940 | 15'd2);
assign tmp_7_fu_1395_p1 = tmp_6_reg_1995;
assign tmp_8_10_cast_fu_1380_p1 = tmp_23_reg_2085;
assign tmp_8_11_cast_fu_1399_p1 = tmp_25_reg_2091;
assign tmp_8_12_cast_fu_1412_p1 = tmp_27_reg_2097;
assign tmp_8_13_cast_fu_1425_p1 = tmp_29_reg_2103;
assign tmp_8_14_cast_fu_1438_p1 = tmp_31_reg_2109;
assign tmp_8_15_cast_fu_1451_p1 = tmp_33_reg_2115;
assign tmp_8_16_cast_fu_1464_p1 = tmp_35_reg_2121;
assign tmp_8_17_cast_fu_1477_p1 = tmp_37_reg_2127;
assign tmp_8_18_cast_fu_1490_p1 = tmp_39_reg_2133;
assign tmp_8_19_cast_fu_1503_p1 = tmp_41_reg_2139;
assign tmp_8_1_cast_fu_898_p1 = tmp_6_reg_1995;
assign tmp_8_20_cast_fu_1516_p1 = tmp_43_reg_2145;
assign tmp_8_21_cast_fu_1529_p1 = tmp_45_reg_2151;
assign tmp_8_22_cast_fu_1542_p1 = tmp_47_reg_2157;
assign tmp_8_23_cast_fu_1555_p1 = tmp_49_reg_2163;
assign tmp_8_24_cast_fu_1568_p1 = tmp_51_reg_2169;
assign tmp_8_25_cast_fu_1581_p1 = tmp_53_reg_2175;
assign tmp_8_26_cast_fu_1594_p1 = tmp_55_reg_2181;
assign tmp_8_27_cast_fu_1607_p1 = tmp_57_reg_2187;
assign tmp_8_28_cast_fu_1620_p1 = tmp_59_reg_2193;
assign tmp_8_29_cast_fu_1633_p1 = tmp_61_reg_2199;
assign tmp_8_2_cast_fu_921_p1 = tmp_8_reg_2005;
assign tmp_8_30_cast_fu_1646_p1 = tmp_63_reg_2205;
assign tmp_8_3_cast_fu_944_p1 = tmp_s_reg_2015;
assign tmp_8_4_cast_fu_967_p1 = tmp_11_reg_2025;
assign tmp_8_5_cast_fu_990_p1 = tmp_13_reg_2035;
assign tmp_8_6_cast_fu_1013_p1 = tmp_15_reg_2045;
assign tmp_8_7_cast_fu_1036_p1 = tmp_17_reg_2055;
assign tmp_8_8_cast_fu_1059_p1 = tmp_19_reg_2065;
assign tmp_8_9_cast_fu_1262_p1 = tmp_21_reg_2075;
assign tmp_8_cast_6_fu_875_p1 = tmp_4_reg_1985;
assign tmp_8_cast_fu_894_p1 = tmp_8_fu_889_p2;
assign tmp_8_fu_889_p2 = (tmp_98_reg_1940 | 15'd3);
assign tmp_98_fu_826_p1 = i_op_assign_reg_732[14:0];
assign tmp_9_fu_1408_p1 = tmp_8_reg_2005;
assign tmp_cast_fu_917_p1 = tmp_s_fu_912_p2;
assign tmp_fu_809_p3 = i_op_assign_phi_fu_736_p4[32'd15];
assign tmp_s_fu_912_p2 = (tmp_98_reg_1940 | 15'd4);
always @ (posedge ap_clk) begin
tmp_1_reg_1974[63:16] <= 48'b000000000000000000000000000000000000000000000000;
buffer_V_addr_reg_1979[31:16] <= 16'b0000000000000000;
tmp_4_reg_1985[0] <= 1'b1;
tmp_6_reg_1995[1] <= 1'b1;
tmp_8_reg_2005[1:0] <= 2'b11;
tmp_s_reg_2015[2] <= 1'b1;
tmp_11_reg_2025[0] <= 1'b1;
tmp_11_reg_2025[2] <= 1'b1;
tmp_13_reg_2035[2:1] <= 2'b11;
tmp_15_reg_2045[2:0] <= 3'b111;
tmp_17_reg_2055[3] <= 1'b1;
tmp_19_reg_2065[0] <= 1'b1;
tmp_19_reg_2065[3] <= 1'b1;
tmp_21_reg_2075[1] <= 1'b1;
tmp_21_reg_2075[3] <= 1'b1;
tmp_23_reg_2085[1:0] <= 2'b11;
tmp_23_reg_2085[3] <= 1'b1;
tmp_25_reg_2091[3:2] <= 2'b11;
tmp_27_reg_2097[0] <= 1'b1;
tmp_27_reg_2097[3:2] <= 2'b11;
tmp_29_reg_2103[3:1] <= 3'b111;
tmp_31_reg_2109[3:0] <= 4'b1111;
tmp_33_reg_2115[4] <= 1'b1;
tmp_35_reg_2121[0] <= 1'b1;
tmp_35_reg_2121[4] <= 1'b1;
tmp_37_reg_2127[1] <= 1'b1;
tmp_37_reg_2127[4] <= 1'b1;
tmp_39_reg_2133[1:0] <= 2'b11;
tmp_39_reg_2133[4] <= 1'b1;
tmp_41_reg_2139[2] <= 1'b1;
tmp_41_reg_2139[4] <= 1'b1;
tmp_43_reg_2145[0] <= 1'b1;
tmp_43_reg_2145[2:2] <= 1'b1;
tmp_43_reg_2145[4] <= 1'b1;
tmp_45_reg_2151[2:1] <= 2'b11;
tmp_45_reg_2151[4] <= 1'b1;
tmp_47_reg_2157[2:0] <= 3'b111;
tmp_47_reg_2157[4] <= 1'b1;
tmp_49_reg_2163[4:3] <= 2'b11;
tmp_51_reg_2169[0] <= 1'b1;
tmp_51_reg_2169[4:3] <= 2'b11;
tmp_53_reg_2175[1] <= 1'b1;
tmp_53_reg_2175[4:3] <= 2'b11;
tmp_55_reg_2181[1:0] <= 2'b11;
tmp_55_reg_2181[4:3] <= 2'b11;
tmp_57_reg_2187[4:2] <= 3'b111;
tmp_59_reg_2193[0] <= 1'b1;
tmp_59_reg_2193[4:2] <= 3'b111;
tmp_61_reg_2199[4:1] <= 4'b1111;
tmp_63_reg_2205[4:0] <= 5'b11111;
end
endmodule //filesystem_encrypt
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <[email protected]>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
/*
* Helper module for synchronizing bit signals from one clock domain to another.
* It uses the standard approach of 2 FF in series.
* Note, that while the module allows to synchronize multiple bits at once it is
* only able to synchronize multi-bit signals where at max one bit changes per
* clock cycle (e.g. a gray counter).
*/
module sync_bits
(
input [NUM_BITS-1:0] in,
input out_resetn,
input out_clk,
output [NUM_BITS-1:0] out
);
// Number of bits to synchronize
parameter NUM_BITS = 1;
// Whether input and output clocks are asynchronous, if 0 the synchronizer will
// be bypassed and the output signal equals the input signal.
parameter CLK_ASYNC = 1;
reg [NUM_BITS-1:0] out_m1 = 'h0;
reg [NUM_BITS-1:0] out_m2 = 'h0;
always @(posedge out_clk)
begin
if (out_resetn == 1'b0) begin
out_m1 <= 'b0;
out_m2 <= 'b0;
end else begin
out_m1 <= in;
out_m2 <= out_m1;
end
end
assign out = CLK_ASYNC ? out_m2 : in;
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_a_e
//
// Generated
// by: wig
// on: Mon Jun 26 06:35:31 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_a_e.v,v 1.3 2006/06/26 07:42:19 wig Exp $
// $Date: 2006/06/26 07:42:19 $
// $Log: inst_a_e.v,v $
// Revision 1.3 2006/06/26 07:42:19 wig
// Updated io, generic and mde_tests testcases
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_a_e
//
// No user `defines in this module
module inst_a_e
//
// Generated Module inst_a
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_1
inst_1_e #(
.FOO(16)
) inst_1 (
);
// End of Generated Instance Port Map for inst_1
// Generated Instance Port Map for inst_10
inst_10_e #(
.FOO(32)
) inst_10 (
);
// End of Generated Instance Port Map for inst_10
// Generated Instance Port Map for inst_2
inst_2_e #(
.FOO(16)
) inst_2 (
);
// End of Generated Instance Port Map for inst_2
// Generated Instance Port Map for inst_3
inst_3_e #(
.FOO(16)
) inst_3 (
);
// End of Generated Instance Port Map for inst_3
// Generated Instance Port Map for inst_4
inst_4_e #(
.FOO(16)
) inst_4 (
);
// End of Generated Instance Port Map for inst_4
// Generated Instance Port Map for inst_5
inst_5_e inst_5 (
);
// End of Generated Instance Port Map for inst_5
// Generated Instance Port Map for inst_6
inst_6_e inst_6 (
);
// End of Generated Instance Port Map for inst_6
// Generated Instance Port Map for inst_7
inst_7_e #(
.FOO(32)
) inst_7 (
);
// End of Generated Instance Port Map for inst_7
// Generated Instance Port Map for inst_8
inst_8_e #(
.FOO(32)
) inst_8 (
);
// End of Generated Instance Port Map for inst_8
// Generated Instance Port Map for inst_9
inst_9_e #(
.FOO(32)
) inst_9 (
);
// End of Generated Instance Port Map for inst_9
// Generated Instance Port Map for inst_aa
inst_aa_e #(
.NO_DEFAULT("nodefault"),
.NO_NAME("noname"),
.WIDTH(15)
) inst_aa (
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
inst_ab_e #(
.WIDTH(31)
) inst_ab (
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
inst_ac_e inst_ac (
);
// End of Generated Instance Port Map for inst_ac
// Generated Instance Port Map for inst_ad
inst_ad_e inst_ad (
);
// End of Generated Instance Port Map for inst_ad
// Generated Instance Port Map for inst_ae
inst_ae_e inst_ae (
);
// End of Generated Instance Port Map for inst_ae
// Generated Instance Port Map for inst_m1
inst_m_e #(
.FOO(15)
) inst_m1 (
);
// End of Generated Instance Port Map for inst_m1
// Generated Instance Port Map for inst_m10
inst_m_e #(
.FOO(30)
) inst_m10 (
);
// End of Generated Instance Port Map for inst_m10
// Generated Instance Port Map for inst_m2
inst_m_e #(
.FOO(15)
) inst_m2 (
);
// End of Generated Instance Port Map for inst_m2
// Generated Instance Port Map for inst_m3
inst_m_e #(
.FOO(15)
) inst_m3 (
);
// End of Generated Instance Port Map for inst_m3
// Generated Instance Port Map for inst_m4
inst_m_e #(
.FOO(15)
) inst_m4 (
);
// End of Generated Instance Port Map for inst_m4
// Generated Instance Port Map for inst_m5
inst_m_e #(
.FOO(15)
) inst_m5 (
);
// End of Generated Instance Port Map for inst_m5
// Generated Instance Port Map for inst_m6
inst_m_e #(
.FOO(30)
) inst_m6 (
);
// End of Generated Instance Port Map for inst_m6
// Generated Instance Port Map for inst_m7
inst_m_e #(
.FOO(30)
) inst_m7 (
);
// End of Generated Instance Port Map for inst_m7
// Generated Instance Port Map for inst_m8
inst_m_e #(
.FOO(30)
) inst_m8 (
);
// End of Generated Instance Port Map for inst_m8
// Generated Instance Port Map for inst_m9
inst_m_e #(
.FOO(30)
) inst_m9 (
);
// End of Generated Instance Port Map for inst_m9
endmodule
//
// End of Generated Module rtl of inst_a_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUFINV_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__BUFINV_PP_SYMBOL_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__bufinv (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUFINV_PP_SYMBOL_V
|
module ram_test (
input clk,
input rst,
output reg [22:0] addr,
output reg rw,
output reg [31:0] data_in,
input [31:0] data_out,
input busy,
output reg in_valid,
input out_valid,
output [7:0] leds
);
localparam STATE_SIZE = 2;
localparam WRITE = 0,
READ = 1,
IDLE = 2;
reg [STATE_SIZE-1:0] state_d, state_q = WRITE;
reg [4:0] led_d, led_q;
reg [22:0] addr_d, addr_q;
reg [6:0] error_d, error_q;
reg [31:0] seed_d, seed_q;
assign leds = {led_q[4], error_q};
reg pn_rst, pn_next;
wire [31:0] pn;
pn_gen pn_gen (
.clk(clk),
.rst(pn_rst),
.next(pn_next),
.seed(seed_q),
.num(pn)
);
always @* begin
addr_d = addr_q;
led_d = led_q;
state_d = state_q;
error_d = error_q;
addr = 23'd0;
rw = 1'b0;
data_in = 32'h00;
in_valid = 1'b0;
pn_rst = 1'b0 | rst;
pn_next = 1'b0;
seed_d = seed_q;
case (state_q)
WRITE: begin
led_d[4] = 1'b0;
if (!busy) begin
pn_next = 1'b1;
addr_d = addr_q + 1'b1;
addr = addr_q;
rw = 1'b1;
data_in = pn;
in_valid = 1'b1;
if (addr_q == {23{1'b1}}) begin
addr_d = 8'b0;
state_d = READ;
pn_rst = 1'b1;
end
end
end
READ: begin
led_d[4] = 1'b1;
if (!busy) begin
addr_d = addr_q + 1'b1;
addr = addr_q;
in_valid = 1'b1;
if (addr_q == {23{1'b1}}-25'd10)
seed_d = seed_q + 1'b1;
if (addr_q == {23{1'b1}}) begin
addr_d = 8'b0;
state_d = WRITE;
pn_rst = 1'b1;
end
end
if (out_valid) begin
pn_next = 1'b1;
led_d[0] = pn[7:0] != data_out[7:0];
led_d[1] = pn[15:8] != data_out[15:8];
led_d[2] = pn[23:16] != data_out[23:16];
led_d[3] = pn[31:24] != data_out[31:24];
if (data_out != pn && error_q < {7{1'b1}})
error_d = error_q + 1'b1;
end
end
IDLE: begin
led_d[4] = 1'b0;
end
default: state_d = WRITE;
endcase
end
always @(posedge clk) begin
if (rst) begin
state_q <= WRITE;
addr_q <= 8'd0;
error_q <= 7'b0;
seed_q <= 32'd0;
led_q <= 5'b0;
end else begin
state_q <= state_d;
addr_q <= addr_d;
error_q <= error_d;
seed_q <= seed_d;
led_q <= led_d;
end
end
endmodule
|
(** * IndProp: Inductively Defined Propositions *)
Require Export Logic.
(* ################################################################# *)
(* * Inductively Defined Propositions *)
(** * 帰納的に定義された命題 *)
(* In the [Logic] chapter, we looked at several ways of writing
propositions, including conjunction, disjunction, and quantifiers.
In this chapter, we bring a new tool into the mix: _inductive
definitions_.
Recall that we have seen two ways of stating that a number [n] is
even: We can say (1) [evenb n = true], or (2) [exists k, n =
double k]. Yet another possibility is to say that [n] is even if
we can establish its evenness from the following rules:
- Rule [ev_0]: The number [0] is even.
- Rule [ev_SS]: If [n] is even, then [S (S n)] is even. *)
(** [Logic]の章において、命題を書く幾つかの方法を見ました。論理積や論理和や数量子などです。 この章においては、新しいツールを導入して、_帰納的な定義_として統合します。
ある数が偶数であることを述べる二つの方法があったことを思いだしてください: (1) [evenb n = true]であることと (2)[exists k, n = double k]とです。 [n]が偶数であると述べるもっと他の方法があります。そのためには以下の規則に従います。
- 規則 [ev_0]: 0は偶数である。
- 規則 [ev_SS]: もし[n]が偶数であれば、[S (S n)]も偶数である。 *)
(* To illustrate how this definition of evenness works, let's
imagine using it to show that [4] is even. By rule [ev_SS], it
suffices to show that [2] is even. This, in turn, is again
guaranteed by rule [ev_SS], as long as we can show that [0] is
even. But this last fact follows directly from the [ev_0] rule. *)
(** この偶数性についての定義がどう働くかを説明するために、[4]が偶数であることをこの規則を用いて示してみましょう。まずは、[ev_SS]です。それには、[2]が偶数であることを示すことが十分(条件？)です。次にここで、[ev_SS]を用いて[0]が偶数であることを示せる限り、保証しなければなりません。しかし、最後の事実はl[ev_0]から直接に導かれます。*)
(* We will see many definitions like this one during the rest
of the course. For purposes of informal discussions, it is
helpful to have a lightweight notation that makes them easy to
read and write. _Inference rules_ are one such notation: *)
(** このような多くの定義をこのコースの残りを通して見て行きます。また、これらの読み書きを簡単にする手軽な記法があると非形式的な議論のために役にたちます。推論規則の一つは次のように書きます。*)
(**
------------ (ev_0)
ev 0
ev n
-------------- (ev_SS)
ev (S (S n))
*)
(* Each of the textual rules above is reformatted here as an
inference rule; the intended reading is that, if the _premises_
above the line all hold, then the _conclusion_ below the line
follows. For example, the rule [ev_SS] says that, if [n]
satisfies [ev], then [S (S n)] also does. If a rule has no
premises above the line, then its conclusion holds
unconditionally.
We can represent a proof using these rules by combining rule
applications into a _proof tree_. Here's how we might transcribe
the above proof that [4] is even: *)
(** 上記規則のそれぞれは、「もしラインの上にある根拠がすべて有効であるならば、ラインの下の結論が導かれる。」という推論規則として体裁を与えられています。たとえば、規則[ev_SS]は、[n]が[ev]を満たすならば、[S (S n)]もそうであるという意味です。ラインの上に前提を持たない場合は、無条件にその結論が導かれます。
規則と規則の適用を使って、証明を証明木として表すことが出来ます。上記の[4]が偶数であることを示す証明をどうやって書き換えるかを以下に示します。*)
(**
------ (ev_0)
ev 0
------ (ev_SS)
ev 2
------ (ev_SS)
ev 4
*)
(* Why call this a "tree" (rather than a "stack", for example)?
Because, in general, inference rules can have multiple premises.
We will see examples of this below. *)
(** なぜこれを"木"と言うのか？(むしろ"棚(stack)"と呼ぶべきなんじゃ？)
もちろん、一般的には、推論の規則は複数の前提を持つことが出来ます。この例を後で示します。*)
(* Putting all of this together, we can translate the definition of
evenness into a formal Coq definition using an [Inductive]
declaration, where each constructor corresponds to an inference
rule: *)
(** これらを全部まとめると、偶数性の定義を形式的なCoqの定義に、[Inductive]宣言を使って書き直すことが出来ます。その定義の中の各コンスラクタが先程の推論規則に対応しています。*)
Inductive ev : nat -> Prop :=
| ev_0 : ev 0
| ev_SS : forall n : nat, ev n -> ev (S (S n)).
(*r This definition is different in one crucial respect from
previous uses of [Inductive]: its result is not a [Type], but
rather a function from [nat] to [Prop] -- that is, a property of
numbers. Note that we've already seen other inductive definitions
that result in functions, such as [list], whose type is [Type ->
Type]. What is new here is that, because the [nat] argument of
[ev] appears _unnamed_, to the _right_ of the colon, it is allowed
to take different values in the types of different constructors:
[0] in the type of [ev_0] and [S (S n)] in the type of [ev_SS].
In contrast, the definition of [list] names the [X] parameter
_globally_, to the _left_ of the colon, forcing the result of
[nil] and [cons] to be the same ([list X]). Had we tried to bring
[nat] to the left in defining [ev], we would have seen an error: *)
(* この定義は重要な面で、これまでの[Inductive]の使い方とは異なっています: その結果が[Type]でなく、むしろ、[nat]から[Prop]への関数 -- すなわち、数の属性であることです。[Type -> Type]という型をもつ[list]型のような、結果が関数であるような他の帰納的な定義を見て来たことに注意してください。
ここで学ぶ新しいことは、[ev]の引数である[nat]に、_名前がなく_、また[nat]が(:=の直前の)コロンの右側にあるために、コンストラクタが異った値を取ることが許されています。[ev_0]の型のなかにある[0]や、[ev_SS]の型の中にある[S (S n)]のようにです。
逆に、[list]という定義は、グローバルに、コロンの左側で、[X]という名前をパラメータにつけていて、、[nil]や[cons]の結果が、同じ[List X]という型を持つように強制しています。[ev」の定義において、[nat]をコロンの左側に持ってきたとすると、エラーになるのが分かるでしょう。*)
Fail Inductive wrong_ev (n : nat) : Prop :=
| wrong_ev_0 : wrong_ev 0
| wrong_ev_SS : forall n, wrong_ev n -> wrong_ev (S (S n)).
(* ===> Error: A parameter of an inductive type n is not
allowed to be used as a bound variable in the type
of its constructor. *)
(** ===> エラー: 帰納的な型の中にあるパラメータ n は、そのコンスラクタの型の束縛変数のように使うことが許されていません。*)
(* ("Parameter" here is Coq jargon for an argument on the left of the
colon in an [Inductive] definition; "index" is used to refer to
arguments on the right of the colon.) *)
(** ("パラメータ"というのは、Coqにおいて、[Inductive]定義のコロンの左側にある引数のことを表す専門用語です。"index"はコロンの右側にある引数に言及するさいに使われます。)*)
(* We can think of the definition of [ev] as defining a Coq property
[ev : nat -> Prop], together with theorems [ev_0 : ev 0] and
[ev_SS : forall n, ev n -> ev (S (S n))]. Such "constructor
theorems" have the same status as proven theorems. In particular,
we can use Coq's [apply] tactic with the rule names to prove [ev]
for particular numbers... *)
(** Coqが属性を定義するように、[ev]の定義[ev : nat -> Prop]について、定理:[ev_0 : ev 0]と
l[ev_SS: forall n, ev n -> ev (S (S n))]と一緒に考えてみましょう。そのような、"構造化定理"？は証明された定理と同じ状態です。特に、Coqの[apply]タクティックに規則名を渡して、を特定の数が[ev]であることを証明するために使えます。*)
Theorem ev_4 : ev 4.
Proof. apply ev_SS. apply ev_SS. apply ev_0. Qed.
(* ... or we can use function application syntax: *)
(** ... あるいは、関数適用の記法で使うことも出来ます。*)
Theorem ev_4' : ev 4.
Proof. apply (ev_SS 2 (ev_SS 0 ev_0)). Qed.
(* We can also prove theorems that have hypotheses involving [ev]. *)
(** [ev]を含む仮定を持つ定理の証明をすることも出来ます。*)
Theorem ev_plus4 : forall n, ev n -> ev (4 + n).
Proof.
intros n. simpl. intros Hn.
apply ev_SS. apply ev_SS. apply Hn.
Qed.
(* More generally, we can show that any number multiplied by 2 is even: *)
(** もっと一般的に、あらゆる数に2が掛けられると偶数になることを示しましょう: *)
(* **** Exercise: 1 star (ev_double) *)
(** **** 練習問題: ★ (ev_double) *)
Theorem ev_double : forall n,
ev (double n).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(** * Using Evidence in Proofs *)
(** * 証明中に根拠を使用すること *)
(* Besides _constructing_ evidence that numbers are even, we can also
_reason about_ such evidence.
Introducing [ev] with an [Inductive] declaration tells Coq not
only that the constructors [ev_0] and [ev_SS] are valid ways to
build evidence that some number is even, but also that these two
constructors are the _only_ ways to build evidence that numbers
are even (in the sense of [ev]). *)
(** ある数が偶数であるという根拠を構築する際に、そのような根拠について推論することも出来ます。
[Inductive]宣言を持つ[ev]を導入することは、Coqにおいて、コンストラクタ[ev_0]と[ev_SS]が、ある数が偶数であるという根拠を構築する正しい方法であるというだけでなく、これら二つのコンスラクタはあらゆる数が偶数であるという根拠になる唯一の方法なのです。([ev]という意味において) *)
(* In other words, if someone gives us evidence [E] for the assertion
[ev n], then we know that [E] must have one of two shapes:
- [E] is [ev_0] (and [n] is [O]), or
- [E] is [ev_SS n' E'] (and [n] is [S (S n')], where [E'] is
evidence for [ev n']). *)
(** 言い換えると、[ev n]という言明に対して、根拠[E]が与えられたら、[E]は、二つのうちどちらかの形をしていなければならないことは、分かっていると思います。
- [E] は、[ev_0]である(そして、[n]は[O]である。あるいは、
- [E] は、[ev_SS n ' E']である'(そして、[n]は[S (S n)]である。そこで、[E']は[ev n']の根拠である.
*)
(** This suggests that it should be possible to analyze a hypothesis
of the form [ev n] much as we do inductively defined data
structures; in particular, it should be possible to argue by
_induction_ and _case analysis_ on such evidence. Let's look at a
few examples to see what this means in practice. *)
(** このことは、帰納的に定義されたデータと同じように、[ev n]という形をした仮説を解析することを可能にします。とくに、根拠に対する、帰納や、場合分けによって、根拠を示すことが出来るようになります。これが実際に何を意味すかを少し練習問題をやることで見てみましょう。*)
(* ================================================================= *)
(* ** Inversion on Evidence *)
(** ** 根拠に対するInversion *)
(* Suppose we are proving some fact involving a number [n], and we
are given [ev n] as a hypothesis. We already know how to perform
case analysis on [n] using the [inversion] tactic, generating
separate subgoals for the case where [n = O] and the case where [n
= S n'] for some [n']. But for some proofs we may instead want to
analyze the evidence that [ev n] _directly_.
By the definition of [ev], there are two cases to consider:
- If the evidence is of the form [ev_0], we know that [n = 0].
- Otherwise, the evidence must have the form [ev_SS n' E'], where
[n = S (S n')] and [E'] is evidence for [ev n']. *)
(** 自然数[n]を含むある事実を証明していると仮定して、仮説として[ev n]が与えられているとします。
我々はすでに、[inversion]タクティックを使った[n]についてのケース分析のやりかたを既に知っています。
そのケース分析では、[n = O]の場合と、[n = S n']の場合の二つのサブゴールを生成します。
しかし、別の証明では、[ev n]である根拠を直接解析したい場合があります。
[ev]の定義によって、二つの場合が考えられます。
- もし根拠が、[ev_0]由来のものである場合、[n = 0]であることが分かります。
- そうでない場合、根拠は、必ず[ev_SS n' E']という形をしており、そこでは[n = S (S n')]かつ、[E']が[ev n']である根拠になります。 *)
(* Subtracting two from an even number yields another even number.
We can easily prove this claim with the techniques that we've
already seen, provided that we phrase it in the right way. If we
state it in terms of [evenb], for instance, we can proceed by a
simple case analysis on [n]: *)
(** ある偶数から、2引くことは、別の偶数を導出します。この主張をこれまでに見た正しい方法で、もっと易しく証明出来ます。もし、[evenb]を使って述べた場合、例えば、[n]について場合分けで証明を進めることが出来ます。 *)
Theorem evenb_minus2: forall n,
evenb n = true -> evenb (pred (pred n)) = true.
Proof.
intros [ | [ | n' ] ].
- (* n = 0 *) reflexivity.
- (* n = 1; contradiction *) intros H. inversion H.
- (* n = n' + 2 *) simpl. intros H. apply H.
Qed.
(** We can perform this kind of reasoning in Coq, again using
the [inversion] tactic. Besides allowing us to reason about
equalities involving constructors, [inversion] provides a
case-analysis principle for inductively defined propositions.
When used in this way, its syntax is similar to [destruct]: We
pass it a list of identifiers separated by [|] characters to name
the arguments to each of the possible constructors. *)
(** この種の推論を[inversion]タクティックを使うことでCoqで行なうことが出来ます。
それに加えコンストラクタを含む等価性についての推論を行なうことも出来ます。
[inversion]は帰納的に定義された命題のためのケース分析の原理を提供してくれます。
上記のように使用された場合、[inversion]のシンタックスは[destruct]に似ます:
それぞれのありうるコンストラクタの引数として、 [|]の文字によって、分離して定義された識別子のリストを渡します。
(* We can state the same claim in terms of [ev], but this quickly
leads us to an obstacle: Since [ev] is defined inductively --
rather than as a function -- Coq doesn't know how to simplify a
goal involving [ev n] after case analysis on [n]. As a
consequence, the same proof strategy fails: *)
(** 同じ主張を、[ev]を使って述べることも出来ますが、障害にぶちあたります: [ev]は帰納的に定義されている-- 、むしろ関数として定義されている -- ので、Coqは、[n]に関数場合分けをしたとき、[ev n]を含むゴールをどうやって簡約してよいか分からないからです。結果として、同じ戦略では失敗します。*)
Theorem ev_minus2 : forall n,
ev n -> ev (pred (pred n)).
Proof.
intros n E.
inversion E as [| n' E'].
- (* E = ev_0 *) simpl. apply ev_0.
- (* E = ev_SS n' E' *) simpl. apply E'. Qed.
(* In words, here is how the inversion reasoning works in this proof:
- If the evidence is of the form [ev_0], we know that [n = 0].
Therefore, it suffices to show that [ev (pred (pred 0))] holds.
By the definition of [pred], this is equivalent to showing that
[ev 0] holds, which directly follows from [ev_0].
- Otherwise, the evidence must have the form [ev_SS n' E'], where
[n = S (S n')] and [E'] is evidence for [ev n']. We must then
show that [ev (pred (pred (S (S n'))))] holds, which, after
simplification, follows directly from [E']. *)
(** この証明のなかで、inversionがどのように動くかを言葉で書くと、
- 証拠が、[ev_0]という形をしている場合、[n = 0]であると分かります。それゆえ、[ev (pred (pred 0))]が成り立つことを示すこが出来れば十分です。
[pred]の定義によれば、これは、[ev 0]と等しいので、成り立つことが[ev_0]から直接導かれます。
- そうでない場合、証拠は、[ev_SS n' E']という形をしており、[n = S (S n')]で[E']は、[ev n']の根拠になります。それから、[ev (pred (pred (S (S n'))))]が成り立つことを示さなければなりませんが、簡約を行なうと、それは[E']から直接導かれます。*)
(* This particular proof also works if we replace [inversion] by
[destruct]: *)
(** 特にこの証明は、[inversion]を[destruct]に置換えたかのような動作をします。*)
Theorem ev_minus2' : forall n,
ev n -> ev (pred (pred n)).
Proof.
intros n E.
destruct E as [| n' E'].
- (* E = ev_0 *) simpl. apply ev_0.
- (* E = ev_SS n' E' *) simpl. apply E'. Qed.
(** The difference between the two forms is that [inversion] is more
convenient when used on a hypothesis that consists of an inductive
property applied to a complex expression (as opposed to a single
variable). Here's is a concrete example. Suppose that we wanted
to prove the following variation of [ev_minus2]: *)
(** ふたつの違いは、[inversion]の方が、(単一変数でないような)複雑な式に適用された帰納的な属性からなる仮説に使用する場合、少し便利であることです。ここに完全な例があります。
次の[ev_minus2]のバリエーションを証明したいとします:*)
Theorem evSS_ev : forall n,
ev (S (S n)) -> ev n.
(* Intuitively, we know that evidence for the hypothesis cannot
consist just of the [ev_0] constructor, since [O] and [S] are
different constructors of the type [nat]; hence, [ev_SS] is the
only case that applies. Unfortunately, [destruct] is not smart
enough to realize this, and it still generates two subgoals. Even
worse, in doing so, it keeps the final goal unchanged, failing to
provide any useful information for completing the proof. *)
(** 帰納的に、仮説の根拠が、[ev_0]コンスオラクタから生成されることはありえないことを知っています。なぜなら、[O]と[S]は異なるnatのコンストラクタであるからです。それゆえに、適用出来るケースは[ev_SS]だけです。残念なことに、[destruct]はこれを実現出来るほど賢くありませんし、サブゴールは二つ作成されたままです。さらに悪いことに、そうなっても最終のゴールは変らないまま、証明を終了させるための有用な情報はなんら得られません。*)
Proof.
intros n E.
destruct E as [| n' E'].
- (* E = ev_0. *)
(* We must prove that [n] is even from no assumptions! *)
(* [n]が偶数であることを証明しなくてはなりませんが、何の仮定もありません! *)
Abort.
(* What happened, exactly? Calling [destruct] has the effect of
replacing all occurrences of the property argument by the values
that correspond to each constructor. This is enough in the case
of [ev_minus2'] because that argument, [n], is mentioned directly
in the final goal. However, it doesn't help in the case of
[evSS_ev] since the term that gets replaced ([S (S n)]) is not
mentioned anywhere. *)
(** 正確には、何が起ったのでしょうか？[destruct]の呼び出しは、それぞれのコンストラクタに対応する値によって、属性の引数の出現すべてを置き換える効果があります。
これは、[ev_minus2']の場合では、引数[n]が最終のゴールに直接名前が出ているために、十分だったのです。しかし、[evSS_ev]の場合は、[S (S n)]を起きかえられる項がどこにもありません。*)
(* The [inversion] tactic, on the other hand, can detect (1) that the
first case does not apply, and (2) that the [n'] that appears on
the [ev_SS] case must be the same as [n]. This allows us to
complete the proof: *)
(** 一方、[inversion]タクティックは、(1)最初のケースは適用出来ないことを検知出来ます。そして(2)ev_SSのケースに現われる[n']は[n]と同じであるに違いないことを検知します。 これで、証明を終らせることが出来ます。*)
Theorem evSS_ev : forall n,
ev (S (S n)) -> ev n.
Proof.
intros n E.
inversion E as [| n' E'].
(* We are in the [E = ev_SS n' E'] case now. *)
(* [E = ev_SS n' E'] の場合にいます。E = ev_0の場合が成立するために、ev S (S n)が ev 0でなければなりませんが、
S (S n) が 0 になるようなnは存在しないので、とっととサブゴールから取り除かれます。*)
apply E'.
Qed.
(* By using [inversion], we can also apply the principle of explosion
to "obviously contradictory" hypotheses involving inductive
properties. For example: *)
(** [inversion]を使うことによって、帰納的な属性を含む"明らかに矛盾した"仮定に対する爆発原理を適用することも出来ます。例えば*)
Theorem one_not_even : ~ ev 1.
Proof.
intros H. inversion H. Qed.
(* **** Exercise: 1 star (inversion_practice) *)
(** **** 練習問題: ★ (inversion_practice) *)
(* Prove the following results using [inversion]. *)
(** 次の結果を[inversion]を用いて証明しなさい。*)
Theorem SSSSev__even : forall n,
ev (S (S (S (S n)))) -> ev n.
Proof.
(* FILL IN HERE *) Admitted.
Theorem even5_nonsense :
ev 5 -> 2 + 2 = 9.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* The way we've used [inversion] here may seem a bit
mysterious at first. Until now, we've only used [inversion] on
equality propositions, to utilize injectivity of constructors or
to discriminate between different constructors. But we see here
that [inversion] can also be applied to analyzing evidence for
inductively defined propositions.
Here's how [inversion] works in general. Suppose the name [I]
refers to an assumption [P] in the current context, where [P] has
been defined by an [Inductive] declaration. Then, for each of the
constructors of [P], [inversion I] generates a subgoal in which
[I] has been replaced by the exact, specific conditions under
which this constructor could have been used to prove [P]. Some of
these subgoals will be self-contradictory; [inversion] throws
these away. The ones that are left represent the cases that must
be proved to establish the original goal. For those, [inversion]
adds all equations into the proof context that must hold of the
arguments given to [P] (e.g., [S (S n') = n] in the proof of
[evSS_ev]). *)
(** このような [inversion] の使い方は最初はちょっと謎めいて思えるかもしれません。これまでは、 [inversion] は等号に関する命題に対して使い、コンストラクタから元のデータを取り出すためか、別のコンストラクタを区別するためににしか使っていませんでした。しかし、ここでは [inversion] が 帰納的に定義された命題に対する根拠を分析するためにも使えることを紹介しました。
ここで、[inversion] が一般にはどのように動作するかを説明します。 [I] が現在のコンテキストにおいて帰納的に宣言された仮定 [P] を参照しているとします。ここで、[inversion I] は、[P]のコンストラクタごとにサブゴールを生成します。 各サブゴールにおいて、 コンストラクタが [P] を証明するのに必要な条件によって [I] が置き換えられます。サブゴールのうちいくつかは矛盾が存在するので、 [inversion] はそれらを除外します。残っているのは、元のゴールが成り立つことを示すのに必要なサブゴールです。[inversion]は[P]に与えられた引数の全ての等式をコンテキストに加えます。(例、evSS_evの中の[S (S n') = n]のように。) *)
(* The [ev_double] exercise above shows that our new notion of
evenness is implied by the two earlier ones (since, by
[even_bool_prop] in chapter [Logic], we already know that
those are equivalent to each other). To show that all three
coincide, we just need the following lemma: *)
(** 上記の[ev_double]練習問題で偶数性の新しい記法が最初の二つによって含意されることを示しました。([Logicの章にあった[even_bool_prop]によって、これでお互いが等価であることが分かりました。)これらが三つがコインの裏表であることを示すために、次の補題が必要になります。*)
Lemma ev_even_firsttry : forall n,
ev n -> exists k, n = double k.
Proof.
(* WORKED IN CLASS *)
(* We could try to proceed by case analysis or induction on [n]. But
since [ev] is mentioned in a premise, this strategy would probably
lead to a dead end, as in the previous section. Thus, it seems
better to first try inversion on the evidence for [ev]. Indeed,
the first case can be solved trivially. *)
(** ここで、[n]に関する場合わけや、帰納法を使って証明を進めたくなるかもしれません。しかし、[ev]が前提として与えられているため、この戦略は前の問題と同じく行き詰まります。それゆえ、根拠である[ev]に対する帰納法を試すのがよい方法に思われます。たしかに、最初の場合は、簡単に解けます。*)
intros n E. inversion E as [| n' E'].
- (* E = ev_0 *)
exists 0. reflexivity.
- (* E = ev_SS n' E' *) simpl.
(* Unfortunately, the second case is harder. We need to show [exists
k, S (S n') = double k], but the only available assumption is
[E'], which states that [ev n'] holds. Since this isn't directly
useful, it seems that we are stuck and that performing case
analysis on [E] was a waste of time.
If we look more closely at our second goal, however, we can see
that something interesting happened: By performing case analysis
on [E], we were able to reduce the original result to an similar
one that involves a _different_ piece of evidence for [ev]: [E'].
More formally, we can finish our proof by showing that
exists k', n' = double k',
which is the same as the original statement, but with [n'] instead
of [n]. Indeed, it is not difficult to convince Coq that this
intermediate result suffices. *)
(** 残念なことに、二つ目の場合はより難しくなります。示す必要があるのは、[exists k, S (S n')]ですが、利用出来る仮定はただ[E']のみで、それは[ev n']であると述べています。これはそのままでは役に立ちませんので、[E]についてのケース分析を行なうことは時間の無駄のようです。
二番目のゴールがより厳密に見ることが出来れば、何かもっと面白いことが起こるのが見えたかもしれません。[E]についてのケース分析をすることで、[ev]の根拠の異なる断片を含む元の結果を減らすことが出来ます。一般的に言えば、以下を示すことで、証明を終わらせることが出来ます。
exists k', n' = double k',
これは最初の文と同じに見えるかもしれませんが、[n']が,[n]の代わりに使われています。確かに、Coqに中間結果が十分であると納得させることは難しくありません。 *)
assert (I : (exists k', n' = double k') ->
(exists k, S (S n') = double k)).
{ intros [k' Hk']. rewrite Hk'. exists (S k'). reflexivity. }
apply I. (* reduce the original goal to the new one *)
Admitted.
(* ================================================================= *)
(* ** Induction on Evidence *)
(** ** 根拠に対する帰納法 *)
(* If this looks familiar, it is no coincidence: We've encountered
similar problems in the [Induction] chapter, when trying to use
case analysis to prove results that required induction. And once
again the solution is... induction!
The behavior of [induction] on evidence is the same as its
behavior on data: It causes Coq to generate one subgoal for each
constructor that could have used to build that evidence, while
providing an induction hypotheses for each recursive occurrence of
the property in question. *)
(* Let's try our current lemma again: *)
(** 以前にも見たような気がするかもしれませんが、気のせいではありません。[Induction]の章で、似たような問題に遭遇しています。そのときは、必要とされる帰納の結果を証明するために、場合わけを用いました。そう、その時に用いた解決方法は、帰納です！
根拠に対する[induction]の振舞はデータに対する帰納法と同じようなものです。Coqに根拠を生成するそれぞれのコンストラクタに対応するサブゴールを生成させて、それぞれの再帰的な属性の出現に対して帰納仮説を与えて行きます。*)
(** もう一度、今の補題をやってみましょう: *)
Lemma ev_even : forall n,
ev n -> exists k, n = double k.
Proof.
intros n E.
induction E as [|n' E' IH].
- (* E = ev_0 *)
exists 0. reflexivity.
- (* E = ev_SS n' E'
with IH : exists k', n' = double k' *)
destruct IH as [k' Hk'].
rewrite Hk'. exists (S k'). reflexivity.
Qed.
(* Here, we can see that Coq produced an [IH] that corresponds to
[E'], the single recursive occurrence of [ev] in its own
definition. Since [E'] mentions [n'], the induction hypothesis
talks about [n'], as opposed to [n] or some other number. *)
(** ここで、Coqが[E']に応答する[IH]を導入しているのが分かります。再帰的な[ev]の出現はその定義のなかで一回きりです。[E']は、[n']に言及しているので、帰納仮説は[n]や他の番号ではなく[n']についてのものです。*)
(* The equivalence between the second and third definitions of
evenness now follows. *)
(** 二番目と三番目の偶数の定義の等価性については以下で示します *)
Theorem ev_even_iff : forall n,
ev n <-> exists k, n = double k.
Proof.
intros n. split.
- (* -> *) apply ev_even.
- (* <- *) intros [k Hk]. rewrite Hk. apply ev_double.
Qed.
(* As we will see in later chapters, induction on evidence is a
recurring technique across many areas, and in particular when
formalizing the semantics of programming languages, where many
properties of interest are defined inductively. *)
(** 後の章で見るように、根拠に対する帰納法は、 様々な分野で横断的に使用可能なテクニックです。
とりわけプログラミング言語の意味論を形式化するのに役立ちます。 そこでは多くの興味深い属性が帰納的に定義されています。*)
(* The following exercises provide simple examples of this
technique, to help you familiarize yourself with it. *)
(** 次の練習問題はこのテクニックの簡単な例です。この方法に慣れるのに役立つでしょう。*)
(* **** Exercise: 2 stars (ev_sum) *)
(** **** 練習問題: ★★ (ev_sum) *)
Theorem ev_sum : forall n m, ev n -> ev m -> ev (n + m).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 4 stars, advanced, optional (ev_alternate) *)
(** **** 練習問題: ★★★★ advanced, optional (ev_alternate) *)
(* In general, there may be multiple ways of defining a
property inductively. For example, here's a (slightly contrived)
alternative definition for [ev]: *)
(** 一般的に、帰納的に属性を定義する方法は、複数の方法がありえます。例えば、ここに(ちょっと不自然ですが) [ev]の代わりになる定義があります。*)
Inductive ev' : nat -> Prop :=
| ev'_0 : ev' 0
| ev'_2 : ev' 2
| ev'_sum : forall n m, ev' n -> ev' m -> ev' (n + m).
(* Prove that this definition is logically equivalent to the old
one. (You may want to look at the previous theorem when you get
to the induction step.) *)
(** この定義が論理的に以前の定義と等価なことを証明しなさい。(帰納法のステップに到達したとき、以前の定理を見たくなるかもしれません
)*)
Theorem ev'_ev : forall n, ev' n <-> ev n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 3 stars, advanced, recommended (ev_ev__ev) *)
(** **** 練習問題: ★★★ advanced recommended (ev_ev__ev) *)
(* Finding the appropriate thing to do induction on is a
bit tricky here: *)
(** 何に対して帰納法を行えばいいかを探しなさい。(ちょっとトリッキーですが) *)
Theorem ev_ev__ev : forall n m,
ev (n+m) -> ev n -> ev m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 3 stars, optional (ev_plus_plus) *)
(** **** 練習問題: ★★★ advanced recommended (ev_ev__ev) *)
(* This exercise just requires applying existing lemmas. No
induction or even case analysis is needed, though some of the
rewriting may be tedious. *)
(** 既存の補題を適用する必要のある練習問題です。 帰納法も場合分けも不要ですが、書き換えのうちいくつかはちょっと大変です。*)
Theorem ev_plus_plus : forall n m p,
ev (n+m) -> ev (n+p) -> ev (m+p).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(* * Inductive Relations *)
(** * 帰納的関係 *)
(* A proposition parameterized by a number (such as [ev])
can be thought of as a _property_ -- i.e., it defines
a subset of [nat], namely those numbers for which the proposition
is provable. In the same way, a two-argument proposition can be
thought of as a _relation_ -- i.e., it defines a set of pairs for
which the proposition is provable. *)
(** 数値をパラメータとして持つ命題(例えば、[ev]など)は属性 _property_と 見なすこともできます。つまり、それに属する値についてその命題が証明可能である ような nat の部分集合の定義と見ることができるということです。 同様に、引数（パラメータ）を二つ持つ命題は、その二つの「関係」を表していると考えられます。つまり、その命題について証明可能な値のペアの集合の定義、 というわけです。 *)
Module Playground.
(* One useful example is the "less than or equal to" relation on
numbers. *)
(** よく使われるものの例として「等しいかまたは小さい」 という関係があります。 *)
(* The following definition should be fairly intuitive. It
says that there are two ways to give evidence that one number is
less than or equal to another: either observe that they are the
same number, or give evidence that the first is less than or equal
to the predecessor of the second. *)
(** この定義はかなり直観的なものになります。これは、ある数値がもう一つの 数値より小さいかまたは等し>い、ということを示すには二つの方法があることを 示しています。一つはそれらが同じ数であるかどうかを確>認すること。もう 一つは最初の数が。二つ目の数の一つ前の数より小さいかまたは等しい、ということの根拠を得ることです。 *)
Inductive le : nat -> nat -> Prop :=
| le_n : forall n, le n n
| le_S : forall n m, (le n m) -> (le n (S m)).
Notation "m <= n" := (le m n).
(** Proofs of facts about [<=] using the constructors [le_n] and
[le_S] follow the same patterns as proofs about properties, like
[ev] above. We can [apply] the constructors to prove [<=]
goals (e.g., to show that [3<=3] or [3<=6]), and we can use
tactics like [inversion] to extract information from [<=]
hypotheses in the context (e.g., to prove that [(2 <= 1) ->
2+2=5].) *
(** コンストラクタ [le_n] と [le_S] を使った [<=] にからむ証明は、前章の [eq] がそうであったように、属性についての証明のいくつかのパターンに倣っています。[<=] の形をしたゴール（例えば [3<=3] や [3<=6] など）に、そのコンストラクタをapply することができますし、inversion のようなタクティックを使って（[(2 <= 1) -> 2+2=5] の証明をしようとする際のように） コンテキストに [<=] を含む仮定から情報を抽出することもできます。*)
(** Here are some sanity checks on the definition. (Notice that,
although these are the same kind of simple "unit tests" as we gave
for the testing functions we wrote in the first few lectures, we
must construct their proofs explicitly -- [simpl] and
[reflexivity] don't do the job, because the proofs aren't just a
matter of simplifying computations.) *)
(** ここで、定義が正しくなされているのかのチェックをしてみましょう。（注意して 欲しいのは、ここでやることが、最初のレクチャーで書いてもらった、ある種のシンプルな「ユニットテスト」のようなものですが、今回のものは以前のものとちょっと違います。今回のものには、[simpl] や [reflexivity] はほとんど役に立ちません。簡約だけで証明できるようなものではないからです。*)
Theorem test_le1 :
3 <= 3.
Proof.
(* WORKED IN CLASS *)
apply le_n. Qed.
Theorem test_le2 :
3 <= 6.
Proof.
(* WORKED IN CLASS *)
apply le_S. apply le_S. apply le_S. apply le_n. Qed.
Theorem test_le3 :
(2 <= 1) -> 2 + 2 = 5.
Proof.
(* WORKED IN CLASS *)
intros H. inversion H. inversion H2. Qed.
(* The "strictly less than" relation [n < m] can now be defined
in terms of [le]. *)
(** "より小さい"という関係 [n < m]は、[le]を使って定義出来ます。
End Playground.
Definition lt (n m:nat) := le (S n) m.
Notation "m < n" := (lt m n).
(* Here are a few more simple relations on numbers: *)
(** 数についての簡単な関係をいくつか示します。*)
Inductive square_of : nat -> nat -> Prop :=
| sq : forall n:nat, square_of n (n * n).
Inductive next_nat : nat -> nat -> Prop :=
| nn : forall n:nat, next_nat n (S n).
Inductive next_even : nat -> nat -> Prop :=
| ne_1 : forall n, ev (S n) -> next_even n (S n)
| ne_2 : forall n, ev (S (S n)) -> next_even n (S (S n)).
(* **** Exercise: 2 stars, optional (total_relation) *)
(** **** 練習問題: ★★, recommended (total_relation) *)
(* Define an inductive binary relation [total_relation] that holds
between every pair of natural numbers. *)
(** 二つの自然数の全てのペア同士の間に成り立つ帰納的な関係 [total_relation] を
定義しなさい。 *)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 2 stars, optional (empty_relation) *)
(** **** 練習問題: ★★ (empty_relation) *)
(* Define an inductive binary relation [empty_relation] (on numbers)
that never holds. *)
(** 自然数の間では決して成り立たない関係 [empty_relation] を帰納的に定義しなさい。 *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (le_exercises) *)
(** **** 練習問題: ★★★, optional (le_exercises) *)
(* Here are a number of facts about the [<=] and [<] relations that
we are going to need later in the course. The proofs make good
practice exercises. *)
(** 後のコースで必要になる[<=] や [<] といった関係についての事実を示しておきます。その証明自体がとてもよい練習問題になります。*)
Lemma le_trans : forall m n o, m <= n -> n <= o -> m <= o.
Proof.
(* FILL IN HERE *) Admitted.
Theorem O_le_n : forall n,
0 <= n.
Proof.
(* FILL IN HERE *) Admitted.
Theorem n_le_m__Sn_le_Sm : forall n m,
n <= m -> S n <= S m.
Proof.
(* FILL IN HERE *) Admitted.
Theorem Sn_le_Sm__n_le_m : forall n m,
S n <= S m -> n <= m.
Proof.
(* FILL IN HERE *) Admitted.
Theorem le_plus_l : forall a b,
a <= a + b.
Proof.
(* FILL IN HERE *) Admitted.
Theorem plus_lt : forall n1 n2 m,
n1 + n2 < m ->
n1 < m /\ n2 < m.
Proof.
unfold lt.
(* FILL IN HERE *) Admitted.
Theorem lt_S : forall n m,
n < m ->
n < S m.
Proof.
(* FILL IN HERE *) Admitted.
Theorem leb_complete : forall n m,
leb n m = true -> n <= m.
Proof.
(* FILL IN HERE *) Admitted.
(* Hint: The next one may be easiest to prove by induction on [m]. *)
(** ヒント: [m]による帰納法の方が簡単に証明出来ます。 *)
Theorem leb_correct : forall n m,
n <= m ->
leb n m = true.
Proof.
(* FILL IN HERE *) Admitted.
(* Hint: This theorem can easily be proved without using [induction]. *)
(** ヒント: この定理は[induction]を使わない方が簡単に証明出来ます。 *)
Theorem leb_true_trans : forall n m o,
leb n m = true -> leb m o = true -> leb n o = true.
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 2 stars, optional (leb_iff) *)
Theorem leb_iff : forall n m,
leb n m = true <-> n <= m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Module R.
(* **** Exercise: 3 stars, recommended (R_provability2) *)
(** **** 練習問題 ★★★, recommended (R_provability2) *)
(** We can define three-place relations, four-place relations,
etc., in just the same way as binary relations. For example,
consider the following three-place relation on numbers: *)
(** 次は三つや四つの値の間に成り立つ関係を同じように定義してみましょう。
例えば、次のような数値の三項関係が考えられます。 *)
Inductive R : nat -> nat -> nat -> Prop :=
| c1 : R 0 0 0
| c2 : forall m n o, R m n o -> R (S m) n (S o)
| c3 : forall m n o, R m n o -> R m (S n) (S o)
| c4 : forall m n o, R (S m) (S n) (S (S o)) -> R m n o
| c5 : forall m n o, R m n o -> R n m o.
(** - Which of the following propositions are provable?
- [R 1 1 2]
- [R 2 2 6]
- If we dropped constructor [c5] from the definition of [R],
would the set of provable propositions change? Briefly (1
sentence) explain your answer.
- If we dropped constructor [c4] from the definition of [R],
would the set of provable propositions change? Briefly (1
sentence) explain your answer.*)
(** - 次の命題のうち、この関係を満たすと証明できると言えるのはどれでしょうか。
- [R 1 1 2]
- [R 2 2 6]
- この関係 [R] の定義からコンストラクタ [c5] を取り除くと、証明可能な命題の範囲はどのように変わるでしょうか？端的に（１文で）説明しなさい。
- この関係 [R] の定義からコンストラクタ [c4] を取り除くと、証明可能な命題の範囲はどのように変わるでしょうか？端的に（１文で）説明しなさい。
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars, optional (R_fact) *)
(** **** 練習問題 ★★★, optional (R_fact) *)
(* The relation [R] above actually encodes a familiar function.
Figure out which function; then state and prove this equivalence
in Coq? *)
(** 上記の関係[R]は実際に、もっと分かりやすい関数をエンコードしたものです。どの関数か挙げなさい。Coqにおけるその関数と関係について述べて、証明しなさい*)
Definition fR : nat -> nat -> nat
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Theorem R_equiv_fR : forall m n o, R m n o <-> fR m n = o.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End R.
(** **** Exercise: 4 stars, advanced (subsequence) *)
(** A list is a _subsequence_ of another list if all of the elements
in the first list occur in the same order in the second list,
possibly with some extra elements in between. For example,
[1;2;3]
is a subsequence of each of the lists
[1;2;3]
[1;1;1;2;2;3]
[1;2;7;3]
[5;6;1;9;9;2;7;3;8]
but it is _not_ a subsequence of any of the lists
[1;2]
[1;3]
[5;6;2;1;7;3;8].
- Define an inductive proposition [subseq] on [list nat] that
captures what it means to be a subsequence. (Hint: You'll need
three cases.)
- Prove [subseq_refl] that subsequence is reflexive, that is,
any list is a subsequence of itself.
- Prove [subseq_app] that for any lists [l1], [l2], and [l3],
if [l1] is a subsequence of [l2], then [l1] is also a subsequence
of [l2 ++ l3].
- (Optional, harder) Prove [subseq_trans] that subsequence is
transitive -- that is, if [l1] is a subsequence of [l2] and [l2]
is a subsequence of [l3], then [l1] is a subsequence of [l3].
Hint: choose your induction carefully! *)
(**あるリストが、別のリストのサブシーケンス（ _subsequence_ ）であるとは、
最初のリストの要素が全て二つ目のリストに同じ順序で現れるということです。
ただし、その間に何か別の要素が入ってもかまいません。例えば、
[1,2,3]
は、次のいずれのリストのサブシーケンスでもあります。
[1,2,3]
[1,1,1,2,2,3]
[1,2,7,3]
[5,6,1,9,9,2,7,3,8]
しかし、次のいずれのリストのサブシーケンスでもありません。
[1,2]
[1,3]
[5,6,2,1,7,3,8]
- [list nat] 上に、そのリストがサブシーケンスであることを意味するような命題 [subseq] を定義しなさい。（ヒント：三つのケースが必要になります）
-サブシーケンスである、という関係が「反射的」であることを証明しなさい。つまり、どのようなリストも、それ自身のサブシーケンスであるということです。
- 任意のリスト [l1]、 [l2]、 [l3] について、もし [l1] が [l2] のサブシーケンスならば、 [l1] は [l2 ++ l3] のサブシーケンスでもある、ということを証明しなさい。
-（これは少し難しいですので、任意とします）サブシーケンスという関係は推移的である、つまり、 [l1] が [l2] のサブシーケンスであり、 [l2] が [l3] のサブシーケンスであるなら、 [l1] は [l3] のサブシーケンスである、というような関係であることを証明しなさい。（ヒント：何について帰納法を適用するか、よくよく注意して下さい!）*)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 2 stars, optionalM (R_provability2) *)
(** **** 練習問題 ★★, optionalM (R_provability2) *)
(* Suppose we give Coq the following definition:
Inductive R : nat -> list nat -> Prop :=
| c1 : R 0 []
| c2 : forall n l, R n l -> R (S n) (n :: l)
| c3 : forall n l, R (S n) l -> R n l.
Which of the following propositions are provable?
- [R 2 [1;0]]
- [R 1 [1;2;1;0]]
- [R 6 [3;2;1;0]] *)
(** Coq に次のような定義を与えたとします：
Inductive R : nat -> list nat -> Prop :=
| c1 : R 0 []
| c2 : forall n l, R n l -> R (S n) (n :: l)
| c3 : forall n l, R (S n) l -> R n l.
次のうち、証明可能なのはどの命題でしょうか？
- [R 2 [1;0]]
- [R 1 [1;2;1;0]]
- [R 6 [3;2;1;0]] *)
(** [] *)
(* ################################################################# *)
(* * Case Study: Regular Expressions *)
(** * ケーススタディ: 正規表現 *)
(* The [ev] property provides a simple example for illustrating
inductive definitions and the basic techniques for reasoning about
them, but it is not terribly exciting -- after all, it is
equivalent to the two non-inductive of evenness that we had
already seen, and does not seem to offer any concrete benefit over
them. To give a better sense of the power of inductive
definitions, we now show how to use them to model a classic
concept in computer science: _regular expressions_. *)
(** [ev]属性は、帰納的な定義とそれを使う推論の簡単な例を提供します。しかしそれほど興奮するものでもありません。-- 結局、それまでに見た二つの非帰納的な定義と等価ですし、それらを越えるどんな具体的なメリットもありません。帰納的定義のパワーをもっと感じるために、コンピュータサイエンスの古典的概念 -- 正規表現 -- を帰納的定義を使って、どのようにモデル化するかを見てみましょう。
(* Regular expressions are a simple language for describing strings,
defined as follows: *)
(** 正規表現は、以下のように帰納的な型によって定義された文字列を記述するための単純な言語です:*)
Inductive reg_exp (T : Type) : Type :=
| EmptySet : reg_exp T
| EmptyStr : reg_exp T
| Char : T -> reg_exp T
| App : reg_exp T -> reg_exp T -> reg_exp T
| Union : reg_exp T -> reg_exp T -> reg_exp T
| Star : reg_exp T -> reg_exp T.
Arguments EmptySet {T}.
Arguments EmptyStr {T}.
Arguments Char {T} _.
Arguments App {T} _ _.
Arguments Union {T} _ _.
Arguments Star {T} _.
(** Note that this definition is _polymorphic_: Regular
expressions in [reg_exp T] describe strings with characters drawn
from [T] -- that is, lists of elements of [T].
(We depart slightly from standard practice in that we do not
require the type [T] to be finite. This results in a somewhat
different theory of regular expressions, but the difference is not
significant for our purposes.) *)
(** この定義が多相的なものであることに気がついたでしょうか: [req_exp T]中の正規表現は文字列を[T]から採られる文字によって記述します。すなわち、[T]の要素のリストです。(有限の型[T]を必要としない標準的な練習から開始します。その結果正規表現といくらか異なるものになりますが、この違いは、我々の目的からすれば、重要なものではありません) *)
(* We connect regular expressions and strings via the following
rules, which define when a regular expression _matches_ some
string:
- The expression [EmptySet] does not match any string.
- The expression [EmptyStr] matches the empty string [[]].
- The expression [Char x] matches the one-character string [[x]].
- If [re1] matches [s1], and [re2] matches [s2], then [App re1
re2] matches [s1 ++ s2].
- If at least one of [re1] and [re2] matches [s], then [Union re1
re2] matches [s].
- Finally, if we can write some string [s] as the concatenation of
a sequence of strings [s = s_1 ++ ... ++ s_k], and the
expression [re] matches each one of the strings [s_i], then
[Star re] matches [s].
As a special case, the sequence of strings may be empty, so
[Star re] always matches the empty string [[]] no matter what
[re] is.
We can easily translate this informal definition into an
[Inductive] one as follows: *)
(** 正規表現と文字列を以下の規則で結び付けます。そのルールは正規表現が文字列にいつマッチするかを定義します:
- [EmptySet]式はどんな文字列にもマッチしません。
- [EmptyStr]式は、空の文字列[[]]にマッチします。
- [Char x]式は、一文字からなる文字列[[x]]にマッチします。
- もし [re1]が文字列[s1]にマッチして、[re2]が文字列[s2]にマッチするならば、{App re1 re2]は、[s1 ++ s2]にマッチします。
- もし、[re1]と[re2]の少くともどちらかが文字列[s]にマッチするならば、[Union re1 re2]は[s]にマッチします。
- 最後に、もし文字列[s]を[s = s_1 ++ ... ++ s_k]のように、文字列の並びの結合として書くことが出来て、正規表現[re]がそれぞれの文字列[s_i]にマッチするならば、[Star re]は[s]にマッチします。(特別な場合として、文字列の並びが空である場合、[Star re]は常に、[re]が何であるかに関係なく、空の文字列[[]]にマッチします。
この非形式的定義を[Inductive]を使用したものに翻訳するのは簡単です: *)
Inductive exp_match {T} : list T -> reg_exp T -> Prop :=
| MEmpty : exp_match [] EmptyStr
| MChar : forall x, exp_match [x] (Char x)
| MApp : forall s1 re1 s2 re2,
exp_match s1 re1 ->
exp_match s2 re2 ->
exp_match (s1 ++ s2) (App re1 re2)
| MUnionL : forall s1 re1 re2,
exp_match s1 re1 ->
exp_match s1 (Union re1 re2)
| MUnionR : forall re1 s2 re2,
exp_match s2 re2 ->
exp_match s2 (Union re1 re2)
| MStar0 : forall re, exp_match [] (Star re)
| MStarApp : forall s1 s2 re,
exp_match s1 re ->
exp_match s2 (Star re) ->
exp_match (s1 ++ s2) (Star re).
(* Again, for readability, we can also display this definition using
inference-rule notation. At the same time, let's introduce a more
readable infix notation. *)
(** もう一度、読み易いように、この定義を推論規則の記法を使って書き直してみましょう。それど同時に、もっと読み易い記法を導入してみることにしましょう。*)
Notation "s =~ re" := (exp_match s re) (at level 80).
(**
---------------- (MEmpty)
[] =~ EmptyStr
--------------- (MChar)
[x] =~ Char x
s1 =~ re1 s2 =~ re2
------------------------- (MApp)
s1 ++ s2 =~ App re1 re2
s1 =~ re1
--------------------- (MUnionL)
s1 =~ Union re1 re2
s2 =~ re2
--------------------- (MUnionR)
s2 =~ Union re1 re2
--------------- (MStar0)
[] =~ Star re
s1 =~ re s2 =~ Star re
--------------------------- (MStarApp)
s1 ++ s2 =~ Star re
*)
(* Notice that these rules are not _quite_ the same as the informal
ones that we gave at the beginning of the section. First, we
don't need to include a rule explicitly stating that no string
matches [EmptySet]; we just don't happen to include any rule that
would have the effect of some string matching [EmptySet]. (Indeed,
the syntax of inductive definitions doesn't even _allow_ us to
give such a "negative rule.")
Second, the informal rules for [Union] and [Star] correspond
to two constructors each: [MUnionL] / [MUnionR], and [MStar0] /
[MStarApp]. The result is logically equivalent to the original
rules but more convenient to use in Coq, since the recursive
occurrences of [exp_match] are given as direct arguments to the
constructors, making it easier to perform induction on evidence.
(The [exp_match_ex1] and [exp_match_ex2] exercises below ask you
to prove that the constructors given in the inductive declaration
and the ones that would arise from a more literal transcription of
the informal rules are indeed equivalent.)
Let's illustrate these rules with a few examples. *)
(** これらの規則は、このセクションの最初に見た非形式的なものと全く同じものではないことに気をつけてください。まず[EmptySet]にどんな文字列もマッチしないことを述べる規則を含める必要はありません: [EmptySet]にマッチする文字列の効果を持つどんなルールを含めることは決して出来ないからです。
(実際、再帰的定義のシンタックスは、そのような否定的な規則を含めることが許されていません。*)
次に、[Union]や[Star]の二つの非形式的な規則は、それぞれ二つのコンストラクタに対応します:[MUnionL] / [MUnionR]、[MStar0] / [MStartApp]とにです。その結果、論理的に元の規則に等しくはなるだけでなく、Coqにとっても都合のよいものになります: 再帰的な[exp_match]を直接コンスラクタの引数として与えることが出来るようになるからです。それは、根拠についての帰納法の適用をより簡単にしてくれます。(下記の[exp_match_ex1]と[exp_match_ex2]の練習問題で、再帰的に宣言されたコンストラクタと、非形式的な規則をもっと文字通りに変換したものが論理的に等しいことを証明して下さい。
これらの規則を幾つかの例で説明してみましょう。*)
Example reg_exp_ex1 : [1] =~ Char 1.
Proof.
apply MChar.
Qed.
Example reg_exp_ex2 : [1; 2] =~ App (Char 1) (Char 2).
Proof.
apply (MApp [1] _ [2]).
- apply MChar.
- apply MChar.
Qed.
(* (Notice how the last example applies [MApp] to the strings [[1]]
and [[2]] directly. Since the goal mentions [[1; 2]] instead of
[[1] ++ [2]], Coq wouldn't be able to figure out how to split the
string on its own.)
Using [inversion], we can also show that certain strings do _not_
match a regular expression: *)
(** (最後の例において、[MApp]が[[1]]と[[2]]の文字列に直接どのように適用されているか注意しましょう。
ゴールに[[1]++[2]]ではなく、[[1; 2]]が設定されているので、Coqそれ自身は、その文字列をどのように分割したらよいかを見つけ出すことが出来ません。)
[inversion]を使うことで、ある特定の文字列が正規表現にマッチしないことを示すことが出来ます。*)
Example reg_exp_ex3 : ~ ([1; 2] =~ Char 1).
Proof.
intros H. inversion H.
Qed.
(* We can define helper functions to help write down regular
expressions. The [reg_exp_of_list] function constructs a regular
expression that matches exactly the list that it receives as an
argument: *)
(** 正規表現を書き下すヘルパ関数を定義することが出来ます。[req_exp_of_list]関数は、引数として受け取ったリストに確実にマッチする正規表現を構築します。*)
Fixpoint reg_exp_of_list {T} (l : list T) :=
match l with
| [] => EmptyStr
| x :: l' => App (Char x) (reg_exp_of_list l')
end.
Example reg_exp_ex4 : [1; 2; 3] =~ reg_exp_of_list [1; 2; 3].
Proof.
simpl. apply (MApp [1]).
{ apply MChar. }
apply (MApp [2]).
{ apply MChar. }
apply (MApp [3]).
{ apply MChar. }
apply MEmpty.
Qed.
(* We can also prove general facts about [exp_match]. For instance,
the following lemma shows that every string [s] that matches [re]
also matches [Star re]. *)
(** [exp_match]に関する一般的な事実を証明することも出来ます。例えば、次の補題は、[re]にマッチする全ての文字列(群)が、[Star re]にもマッチすることを示します。*)
Lemma MStar1 :
forall T s (re : reg_exp T) ,
s =~ re ->
s =~ Star re.
Proof.
intros T s re H.
rewrite <- (app_nil_r _ s).
apply (MStarApp s [] re).
- apply H.
- apply MStar0.
Qed.
(* (Note the use of [app_nil_r] to change the goal of the theorem to
exactly the same shape expected by [MStarApp].) *)
(** (定理のゴールを[MStarApp]で期待される形と全く同じに変更する[app_nil_r]の使用に注目してください。*)
(* **** Exercise: 3 stars (exp_match_ex1) *)
(** **** 練習問題: ★★★ stars (exp_match_ex1) *)
(* The following lemmas show that the informal matching rules given
at the beginning of the chapter can be obtained from the formal
inductive definition. *)
(** 次の補題は、この節の最初に提示された非形式的なマッチング規則が形式的な帰納的定義からも得られることを示しています。*)
Lemma empty_is_empty : forall T (s : list T),
~ (s =~ EmptySet).
Proof.
(* FILL IN HERE *) Admitted.
Lemma MUnion' : forall T (s : list T) (re1 re2 : reg_exp T),
s =~ re1 \/ s =~ re2 ->
s =~ Union re1 re2.
Proof.
(* FILL IN HERE *) Admitted.
(* The next lemma is stated in terms of the [fold] function from the
[Poly] chapter: If [ss : list (list T)] represents a sequence of
strings [s1, ..., sn], then [fold app ss []] is the result of
concatenating them all together. *)
(** 次の補題を[Poly]の章の[fold]関数を使って説明すると:[ss : list (list T)]が、文字列[s1,..., sn]を表現しているとすると、[fold app ss []]は、それら全てを結合した結果です。*)
Lemma MStar' : forall T (ss : list (list T)) (re : reg_exp T),
(forall s, In s ss -> s =~ re) ->
fold app ss [] =~ Star re.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars (reg_exp_of_list) *)
(** **** 練習問題: ★★★★ stars (reg_exp_of_list) *)
(* Prove that [reg_exp_of_list] satisfies the following
specification: *)
(** [reg_exp_of_list]が次の仕様を満すことを証明しなさい。*)
Lemma reg_exp_of_list_spec : forall T (s1 s2 : list T),
s1 =~ reg_exp_of_list s2 <-> s1 = s2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* Since the definition of [exp_match] has a recursive
structure, we might expect that proofs involving regular
expressions will often require induction on evidence. For
example, suppose that we wanted to prove the following intuitive
result: If a regular expression [re] matches some string [s], then
all elements of [s] must occur somewhere in [re]. To state this
theorem, we first define a function [re_chars] that lists all
characters that occur in a regular expression: *)
(** [exp_match]の定義は再帰的構造をしてため、正規表現を含む証明はしばしば根拠に対する帰納法を必要とすると感じてしまうかもしれません。例えば、次の直感的な結果を証明したいと思ったとしましょう:もし、正規表現[re]がある文字列[s]にマッチする場合、[s]の全ての要素は、[re]のどこかに出現しなければならない。
この定理を述べるために、まず、正規表現中の全ての文字を列挙する[re_chars]関数を定義します。*)
Fixpoint re_chars {T} (re : reg_exp T) : list T :=
match re with
| EmptySet => []
| EmptyStr => []
| Char x => [x]
| App re1 re2 => re_chars re1 ++ re_chars re2
| Union re1 re2 => re_chars re1 ++ re_chars re2
| Star re => re_chars re
end.
(* We can then phrase our theorem as follows: *)
(** それから次のように定理を表現します: *)
Theorem in_re_match : forall T (s : list T) (re : reg_exp T) (x : T),
s =~ re ->
In x s ->
In x (re_chars re).
Proof.
intros T s re x Hmatch Hin.
induction Hmatch
as [
|x'
|s1 re1 s2 re2 Hmatch1 IH1 Hmatch2 IH2
|s1 re1 re2 Hmatch IH|re1 s2 re2 Hmatch IH
|re|s1 s2 re Hmatch1 IH1 Hmatch2 IH2].
(* WORKED IN CLASS *)
- (* MEmpty *)
apply Hin.
- (* MChar *)
apply Hin.
- simpl. rewrite in_app_iff in *.
destruct Hin as [Hin | Hin].
+ (* In x s1 *)
left. apply (IH1 Hin).
+ (* In x s2 *)
right. apply (IH2 Hin).
- (* MUnionL *)
simpl. rewrite in_app_iff.
left. apply (IH Hin).
- (* MUnionR *)
simpl. rewrite in_app_iff.
right. apply (IH Hin).
- (* MStar0 *)
destruct Hin.
(* Something interesting happens in the [MStarApp] case. We obtain
_two_ induction hypotheses: One that applies when [x] occurs in
[s1] (which matches [re]), and a second one that applies when [x]
occurs in [s2] (which matches [Star re]). This is a good
illustration of why we need induction on evidence for [exp_match],
as opposed to [re]: The latter would only provide an induction
hypothesis for strings that match [re], which would not allow us
to reason about the case [In x s2]. *)
(** 何か興味深いことが、[MStarApp]のケースで起こりました。ここで、_二つ_の帰納法の仮定が得られました: 一つは、([re]にマッチする)[s1]上に[x]が現われるときに適用され、もう一つは、([Star re]にマッチする)[s2]上に[x]が現れるときに適用されるものです。これは、なぜ[exp_match]の根拠に対する帰納法が、[re]とは対照的に必要となるのかについてのよい説明になっています: 後で、[re]にマッチする文字列のための帰納法の仮定が提供され、[In x s2]のケースについての推論が可能になります。*)
- (* MStarApp *)
simpl. rewrite in_app_iff in Hin.
destruct Hin as [Hin | Hin].
+ (* In x s1 *)
apply (IH1 Hin).
+ (* In x s2 *)
apply (IH2 Hin).
Qed.
(* **** Exercise: 4 stars (re_not_empty) *)
(** **** 練習問題: ★★★★ stars (re_not_empty) *)
(* Write a recursive function [re_not_empty] that tests whether a
regular expression matches some string. Prove that your function
is correct. *)
(** 正規表現がある文字列にマッチするかどうかをテストする帰納的な関数[re_not_empty]を書いて、あなたの関数が正しいことを証明しなさい。*)
Fixpoint re_not_empty {T : Type} (re : reg_exp T) : bool
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Lemma re_not_empty_correct : forall T (re : reg_exp T),
(exists s, s =~ re) <-> re_not_empty re = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(* ** The [remember] Tactic *)
(** ** [remember] タクティック *)
(* One potentially confusing feature of the [induction] tactic is
that it happily lets you try to set up an induction over a term
that isn't sufficiently general. The effect of this is to lose
information (much as [destruct] can do), and leave you unable to
complete the proof. Here's an example: *)
(** [induction]タクティックの混乱しやすいかもしれない特徴として、十分に一般的でない項に対して帰納法を行なうことが出来てしまうことです。このことの影響は([destruct]でよくやるように)情報を失なってしまって、証明を完了出来なくなってしまうことです。次の例では: *)
Lemma star_app: forall T (s1 s2 : list T) (re : reg_exp T),
s1 =~ Star re ->
s2 =~ Star re ->
s1 ++ s2 =~ Star re.
Proof.
intros T s1 s2 re H1.
(* Just doing an [inversion] on [H1] won't get us very far in the
recursive cases. (Try it!). So we need induction. Here is a naive
first attempt: *)
(** [H1]に対して、[inversion]を行なっても、再帰的なケースの中でどこへも行けません。(やってみましょう！)。そのため、帰納法が必要になります。ここで素朴な方法をまず試してみましょう: *)
induction H1
as [|x'|s1 re1 s2' re2 Hmatch1 IH1 Hmatch2 IH2
|s1 re1 re2 Hmatch IH|re1 s2' re2 Hmatch IH
|re''|s1 s2' re'' Hmatch1 IH1 Hmatch2 IH2].
(* But now, although we get seven cases (as we would expect from the
definition of [exp_match]), we have lost a very important bit of
information from [H1]: the fact that [s1] matched something of the
form [Star re]. This means that we have to give proofs for _all_
seven constructors of this definition, even though all but two of
them ([MStar0] and [MStarApp]) are contradictory. We can still
get the proof to go through for a few constructors, such as
[MEmpty]... *)
(** しかしここで、7つのケース([exp_match]の定義から期待されるように)があるにも拘らず、[H1]からの僅かな、しかし非常に重要な情報が失われてしまっているのです: [s1]が[Star re]の形式にマッチしたという事実です。
このことは、この定義の7つのコンストラクタ全てに対する証明を与えなければならないことを意味しています。[MStar0]と[MStarApp]の二つを除いて矛盾しているにも拘らず、です。少数のコンスラクタのために、証明を続けることは出来ます。[MEmpty]のように... *)
- (* MEmpty *)
simpl. intros H. apply H.
(* ... but most cases get stuck. For [MChar], for instance, we
must show that *)
(** ... しかしほとんどの場合は詰ってしまいます。たとえば、[MChar]では、 *)
s2 =~ Char x' -> x' :: s2 =~ Char x',
(* which is clearly impossible. *)
(** はっきりと不可能です。*)
- (* MChar. 詰った... *)
Abort.
(** The problem is that [induction] over a Prop hypothesis only works
properly with hypotheses that are completely general, i.e., ones
in which all the arguments are variables, as opposed to more
complex expressions, such as [Star re].
(In this respect, [induction] on evidence behaves more like
[destruct] than like [inversion].)
We can solve this problem by generalizing over the problematic
expressions with an explicit equality: *)
(** この問題は、命題の仮説に対する[induction]は、完全に一般化された仮説上でしか上手く動かないことです、
言い換えると、もっと複雑な表現とちがって、全ての引数が変数であるような仮定、 たとえば、[Star re]のようなものです。
このような場合において、命題上の[induction]は、[inversion]というよりは、[destruct]に近い振舞いを[induction]は行ないます。
問題のある表現に対して明示的な等価性をもって一般化してやることで、この問題を解くことが出来ます: *) *)
Lemma star_app: forall T (s1 s2 : list T) (re re' : reg_exp T),
s1 =~ re' ->
re' = Star re ->
s2 =~ Star re ->
s1 ++ s2 =~ Star re.
(** We can now proceed by performing induction over evidence directly,
because the argument to the first hypothesis is sufficiently
general, which means that we can discharge most cases by inverting
the [re' = Star re] equality in the context.
This idiom is so common that Coq provides a tactic to
automatically generate such equations for us, avoiding thus the
need for changing the statements of our theorems. *)
(** 直接に、根拠に対する帰納法を進めて来ました。最初の仮説に対する引数は十分に一般的だったからです。
つまり、コンテキストの中の[re' = Star re]という等式を反転することでほとんどの場合を排除することが出来ます。
このイディオムはそのような等式を生み出すためにタクティックを用いる非常に一般的な方法です。
そのため、我々の定理の文を変更しなくてもよくなります。*)
(* Invoking the tactic [remember e as x] causes Coq to (1) replace
all occurrences of the expression [e] by the variable [x], and (2)
add an equation [x = e] to the context. Here's how we can use it
to show the above result: *)
(** [remember e as x]タクティックを呼び出すことで、Coqに(1) 式[e]変数[x]に置き換えさせることが出来、そして(2) [x=e]という等式をコンテキストに付け加えさせます。上記の結果を示すためにそれをどう使うのか見てみましょう。*)
Abort.
Lemma star_app: forall T (s1 s2 : list T) (re : reg_exp T),
s1 =~ Star re ->
s2 =~ Star re ->
s1 ++ s2 =~ Star re.
Proof.
intros T s1 s2 re H1.
remember (Star re) as re'.
(* We now have [Heqre' : re' = Star re]. *)
(** こうすることで、[Heqre' : re' = Star re]を使えます。*)
generalize dependent s2.
induction H1
as [|x'|s1 re1 s2' re2 Hmatch1 IH1 Hmatch2 IH2
|s1 re1 re2 Hmatch IH|re1 s2' re2 Hmatch IH
|re''|s1 s2' re'' Hmatch1 IH1 Hmatch2 IH2].
(* The [Heqre'] is contradictory in most cases, which allows us to
conclude immediately. *)
(** [Heqre']は大半のケースで矛盾しているので、直接結論を導くことが出来ます。*)
- (* MEmpty *) inversion Heqre'.
- (* MChar *) inversion Heqre'.
- (* MApp *) inversion Heqre'.
- (* MUnionL *) inversion Heqre'.
- (* MUnionR *) inversion Heqre'.
(* The interesting cases are those that correspond to [Star]. Note
that the induction hypothesis [IH2] on the [MStarApp] case
mentions an additional premise [Star re'' = Star re'], which
results from the equality generated by [remember]. *)
(** 興味深いケースは[Star]に対応するものです。
帰納法の仮説[IH2]が追加された前提[Star re'' = Start re']を意図したものであることに気をつけてください。
その前提は、[remember]によって生成された等式に起因します。*)
- (* MStar0 *)
inversion Heqre'. intros s H. apply H.
- (* MStarApp *)
inversion Heqre'. rewrite H0 in IH2, Hmatch1.
intros s2 H1. rewrite <- app_assoc.
apply MStarApp.
+ apply Hmatch1.
+ apply IH2.
* reflexivity.
* apply H1.
Qed.
(* **** Exercise: 4 stars (exp_match_ex2) *)
(** **** 練習問題: ★★★★ stars (exp_match_ex2) *)
(* The [MStar''] lemma below (combined with its converse, the
[MStar'] exercise above), shows that our definition of [exp_match]
for [Star] is equivalent to the informal one given previously. *)
(** 下の補題[MStar''](逆の補題である上記の補題[MStar']と結合？してます)は、我々の、[Star]のための[exp_match]の定義が上記で非形式的に与えられたものと同値であることを示しています。*)
Lemma MStar'' : forall T (s : list T) (re : reg_exp T),
s =~ Star re ->
exists ss : list (list T),
s = fold app ss []
/\ forall s', In s' ss -> s' =~ re.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 5 stars, advanced (pumping) *)
(** **** 練習問題: ★★★★★, advanced (pumping) *)
(* One of the first really interesting theorems in the theory of
regular expressions is the so-called _pumping lemma_, which
states, informally, that any sufficiently long string [s] matching
a regular expression [re] can be "pumped" by repeating some middle
section of [s] an arbitrary number of times to produce a new
string also matching [re].
To begin, we need to define "sufficiently long." Since we are
working in a constructive logic, we actually need to be able to
calculate, for each regular expression [re], the minimum length
for strings [s] to guarantee "pumpability." *)
(** 正規表現の定理の中で第一に興味深い定理の一つは、「正規表現の反復補題」と呼ばれるものです。
その補題は、非形式的には、次のようなものです。
正規表現[re]にマッチする十分に長い文字列[s]は、
[s]のどこかの中間部分の任意回の繰り返して膨らませることで、
[re]にマッチする新しい文字列を生み出すことが出来ます。
まず、「十分に長い」とは何かを定義する必要があります。
我々は構成的論理の中にいるので、"pumpability"を保証する最小の長さに対応するどの正規表現[re]でも、
現実に計算可能である必要があります。 *)
Module Pumping.
Fixpoint pumping_constant {T} (re : reg_exp T) : nat :=
match re with
| EmptySet => 0
| EmptyStr => 1
| Char _ => 2
| App re1 re2 =>
pumping_constant re1 + pumping_constant re2
| Union re1 re2 =>
pumping_constant re1 + pumping_constant re2
| Star _ => 1
end.
(* Next, it is useful to define an auxiliary function that repeats a
string (appends it to itself) some number of times. *)
(** 次に、指定された回数、指定された文字列それ自身を繰替えして生成する補助関数があると便利です。*)
Fixpoint napp {T} (n : nat) (l : list T) : list T :=
match n with
| 0 => []
| S n' => l ++ napp n' l
end.
Lemma napp_plus: forall T (n m : nat) (l : list T),
napp (n + m) l = napp n l ++ napp m l.
Proof.
intros T n m l.
induction n as [|n IHn].
- reflexivity.
- simpl. rewrite IHn, app_assoc. reflexivity.
Qed.
(* Now, the pumping lemma itself says that, if [s =~ re] and if the
length of [s] is at least the pumping constant of [re], then [s]
can be split into three substrings [s1 ++ s2 ++ s3] in such a way
that [s2] can be repeated any number of times and the result, when
combined with [s1] and [s3] will still match [re]. Since [s2] is
also guaranteed not to be the empty string, this gives us
a (constructive!) way to generate strings matching [re] that are
as long as we like. *)
(** ここで反復補題がどういうものであるか説明します。もし[s =~ re]であり、
[s]の長さが[re]のpumping constant以上である場合、[s]は三つの部分文字列に分割が可能であり、
[s1 ++ s2 ++ s3] 分割したうちの[s2]を[s1]と[s3]の間で、任意回繰り返した文字列も、
[re]にマッチするというものです。
[s2]は空の文字列でないことが保証されているので、
このことは[re]にマッチする文字列をあなたの望む長さで得る方法を(構成的に!)提供してくれます。 *)
Lemma pumping : forall T (re : reg_exp T) s,
s =~ re ->
pumping_constant re <= length s ->
exists s1 s2 s3,
s = s1 ++ s2 ++ s3 /\
s2 <> [] /\
forall m, s1 ++ napp m s2 ++ s3 =~ re.
(* To streamline the proof (which you are to fill in), the [omega]
tactic, which is enabled by the following [Require], is helpful in
several places for automatically completing tedious low-level
arguments involving equalities or inequalities over natural
numbers. We'll return to [omega] in a later chapter, but feel
free to experiment with it now if you like. The first case of the
induction gives an example of how it is used. *)
(** あなたがこれから埋める証明を簡素化するために、[omega]タクティックが、(次の[Require]によって使えるようになるのですが)いくつかの場所では、自然数の等式と等式の否定を含む低レベルの論証を自動的に完了させるのに役立つでしょう。後の章で再び[omega]を使うことになるでしょうが、気兼ねすることなく使ってください。帰納法の最初のケースにおいて、それがどのように使われるかの例を見ましょう。*)
Require Import Coq.omega.Omega.
Proof.
intros T re s Hmatch.
induction Hmatch
as [ | x | s1 re1 s2 re2 Hmatch1 IH1 Hmatch2 IH2
| s1 re1 re2 Hmatch IH | re1 s2 re2 Hmatch IH
| re | s1 s2 re Hmatch1 IH1 Hmatch2 IH2 ].
- (* MEmpty *)
simpl. omega.
(* FILL IN HERE *) Admitted.
End Pumping.
(* [] *)
(* ################################################################# *)
(* * Case Study: Improving Reflection *)
(* We've seen in the [Logic] chapter that we often need to
relate boolean computations to statements in [Prop]. But
performing this conversion in the way we did it there can result
in tedious proof scripts. Consider the proof of the following
theorem: *)
(** [Logic]の章において、[Prop]による命題をブール値の計算に関連付ける必要がよくありました。
しかし、我々がそこで行なったように変換することは、つまらないスクリプトを書く結果に終わります。
次の定理の証明について考えてみましょう: *)
Theorem filter_not_empty_In : forall n l,
filter (beq_nat n) l <> [] ->
In n l.
Proof.
intros n l. induction l as [|m l' IHl'].
- (* l = [] *)
simpl. intros H. apply H. reflexivity.
- (* l = m :: l' *)
simpl. destruct (beq_nat n m) eqn:H.
+ (* beq_nat n m = true *)
intros _. rewrite beq_nat_true_iff in H. rewrite H.
left. reflexivity.
+ (* beq_nat n m = false *)
intros H'. right. apply IHl'. apply H'.
Qed.
(** In the first branch after [destruct], we explicitly apply
the [beq_nat_true_iff] lemma to the equation generated by
destructing [beq_nat n m], to convert the assumption [beq_nat n m
= true] into the assumption [n = m]; then we had to [rewrite]
using this assumption to complete the case.
We can streamline this by defining an inductive proposition that
yields a better case-analysis principle for [beq_nat n m].
Instead of generating an equation such as [beq_nat n m = true],
which is generally not directly useful, this principle gives us
right away the assumption we really need: [n = m].
We'll actually define something a bit more general, which can be
used with arbitrary properties (and not just equalities): *)
(** [destruct]の後の最初の分岐において、明示的に顕示的に[beq_nat_true_iff]の補題を[beq_nat n m]を場合分けすることで生成される等式[n = m]に変換するために適用しています;
このケースを完了させるこの仮定を使用するために、[rewrite]を使う必要があるでしょう。
この証明をもっと簡単にすることが出来ます。[beq_nat n m]に対するもっとよい場合分けの原理を導出する 再帰的な命題を定義することでです。
直接にはあまり使い道のない[beq_nat n m = true]に対応する等式を生成する代わりに、この原理は、我々が必要とする仮定[n = m]をすぐさま与えてくれます。
すこしだけ一般化して定義することで、任意の命題(等式だけに限らない)に対して用いることが出来るようになります。*)
Module FirstTry.
Inductive reflect : Prop -> bool -> Prop :=
| ReflectT : forall (P:Prop), P -> reflect P true
| ReflectF : forall (P:Prop), ~ P -> reflect P false.
(* Before explaining this, let's rearrange it a little: Since the
types of both [ReflectT] and [ReflectF] begin with
[forall (P:Prop)], we can make the definition a bit more readable
and easier to work with by making [P] a parameter of the whole
Inductive declaration. *)
(** これを説明する前に、すこしだけ変更してみましょう:
[ReflectT]と[ReflectF]の両方の型が[forall (P:Prop)で始まっています。
再帰的な宣言全体のパラメータ[P]が掛るようにすることで、
この定義をもっと読み易く動かすのが簡単にすることが出来ます。*)
End FirstTry.
Inductive reflect (P : Prop) : bool -> Prop :=
| ReflectT : P -> reflect P true
| ReflectF : ~ P -> reflect P false.
(** The [reflect] property takes two arguments: a proposition
[P] and a boolean [b]. Intuitively, it states that the property
[P] is _reflected_ in (i.e., equivalent to) the boolean [b]: [P]
holds if and only if [b = true]. To see this, notice that, by
definition, the only way we can produce evidence that [reflect P
true] holds is by showing that [P] is true and using the
[ReflectT] constructor. If we invert this statement, this means
that it should be possible to extract evidence for [P] from a
End FirstTry.
Inductive reflect (P : Prop) : bool -> Prop :=
| ReflectT : P -> reflect P true
| ReflectF : ~ P -> reflect P false.
(* The [reflect] property takes two arguments: a proposition
[P] and a boolean [b]. Intuitively, it states that the property
[P] is _reflected_ in (i.e., equivalent to) the boolean [b]: [P]
holds if and only if [b = true]. To see this, notice that, by
definition, the only way we can produce evidence that [reflect P
true] holds is by showing that [P] is true and using the
[ReflectT] constructor. If we invert this statement, this means
that it should be possible to extract evidence for [P] from a
proof of [reflect P true]. Conversely, the only way to show
[reflect P false] is by combining evidence for [~ P] with the
[ReflectF] constructor.
It is easy to formalize this intuition and show that the two
statements are indeed equivalent: *)
(** [reflect]という属性は二つの引数を取ります: 命題[P]とブール値[b]です。直感的にそれは、属性[P]はブール値[b]を反映(たとえば、等しいとか)している: [P]が[b=true]であり、そのときに限り成り立つ。ということを述べています。このことを確かめるために、定義によって、[reflect P true]が成り立つ根拠を生成することの出来る唯一の方法は、[P]がtrueであることを示して、[ReflectT]コンスラクタを使うことです。逆にいうと、これは、[P]の根拠を抽出することが、[reflect P true]の証明することで出来るべきであるという意味です。反対に、[reflect P false]を示す唯一の方法は、[~ P]の根拠を[ReflectF]コンストラクタと結合することです。*)
Theorem iff_reflect : forall P b, (P <-> b = true) -> reflect P b.
Proof.
(* WORKED IN CLASS *)
intros P b H. destruct b.
- apply ReflectT. rewrite H. reflexivity.
- apply ReflectF. rewrite H. intros H'. inversion H'.
Qed.
(* **** Exercise: 2 stars, recommended (reflect_iff) *)
(** **** 練習問題: ★★, recommended (reflect_iff) *)
Theorem reflect_iff : forall P b, reflect P b -> (P <-> b = true).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* The advantage of [reflect] over the normal "if and only if"
connective is that, by destructing a hypothesis or lemma of the
form [reflect P b], we can perform case analysis on [b] while at
the same time generating appropriate hypothesis in the two
branches ([P] in the first subgoal and [~ P] in the second). *)
(** 通常の"もし~でありかつそのときに限り"のiff結合子を上回る[reflect]の利点は、
仮説や、[reflect P b]という形の補題を場合分けすることで、
[b]についてのケース分析を進めることが出来、二つの分岐において同時に、
適切な仮説を生成することが出来る点です。
(最初のサブゴールにおいては、[P]が、二番目には、[~P] が) *)
(* To use [reflect] to produce a better proof of
[filter_not_empty_In], we begin by recasting the
[beq_nat_iff_true] lemma into a more convenient form in terms of
[reflect]: *)
[filter_not_empty_In]のもっとよい証明を行なうために、[reflect]を使ってみましょう。
まず[beq_nat_iff_true]の補題をもっと[reflect]で使い易い形に変形することから始めましょう。*)
Lemma beq_natP : forall n m, reflect (n = m) (beq_nat n m).
Proof.
intros n m.
apply iff_reflect. rewrite beq_nat_true_iff. reflexivity.
Qed.
(* The new proof of [filter_not_empty_In] now goes as follows.
Notice how the calls to [destruct] and [apply] are combined into a
single call to [destruct]. *)
(** [filter_not_empty_In]の新しい証明は次に示すものです。
[destruct]と[apply]の呼出しが一つの[destruct]の呼出しに統一されるかについて、注目してみてください。*)
(* (To see this clearly, look at the two proofs of
[filter_not_empty_In] with Coq and observe the differences in
proof state at the beginning of the first case of the
[destruct].) *)
(** (このことをはっきりと理解するために、[filter_not_emptyIn]nの二つの証明をCoqで動かしながら良く見て、[destruct]による最初の分岐の開始において、証明がどのように違うかをよく観察してみてください。*)
Theorem filter_not_empty_In' : forall n l,
filter (beq_nat n) l <> [] ->
In n l.
Proof.
intros n l. induction l as [|m l' IHl'].
- (* l = [] *)
simpl. intros H. apply H. reflexivity.
- (* l = m :: l' *)
simpl. destruct (beq_natP n m) as [H | H].
+ (* n = m *)
intros _. rewrite H. left. reflexivity.
+ (* n <> m *)
intros H'. right. apply IHl'. apply H'.
Qed.
(* **** Exercise: 3 stars, recommended (beq_natP_practice) *)
(** **** 練習問題: ★★★, recommended (beq_natP_practice) *)
(* Use [beq_natP] as above to prove the following: *)
(** [beq_natP]を上記のように使って次の証明をしなさい。 *)
Fixpoint count n l :=
match l with
| [] => 0
| m :: l' => (if beq_nat n m then 1 else 0) + count n l'
end.
Theorem beq_natP_practice : forall n l,
count n l = 0 -> ~(In n l).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** This technique gives us only a small gain in convenience for
the proofs we've seen here, but using [reflect] consistently often
leads to noticeably shorter and clearer scripts as proofs get
larger. We'll see many more examples in later chapters.
The use of the [reflect] property was popularized by _SSReflect_,
a Coq library that has been used to formalize important results in
mathematics, including as the 4-color theorem and the
Feit-Thompson theorem. The name SSReflect stands for _small-scale
reflection_, i.e., the pervasive use of reflection to simplify
small proof steps with boolean computations. *)
(** このテクニックは、この証明では特に、僅かな前進しか与えてくれないことは間違いありませんが、[reflect]を使用することは、しばしば確実に証明を短く簡潔にしてくれます。あとの章で[reflect]が現われる例を見ることになるでしょう。
[reflect]属性の使用は、SSReflectによってポピュラーなものになりました。SSReflectは、4色問題定理やFeit-Thompson定理を含む数学の重要な結果を形式化するために使われてきたCoqのライブラリです。SSReflectとは、(small scale reflection)の略です: 小さな証明のステップをブール値の計算に単純化するreflectionの多用です。*)
(* ################################################################# *)
(* * Additional Exercises *)
(** * 追加の練習問題 *)
(* **** Exercise: 3 stars, recommended (nostutter) *)
(** **** 練習問題: ★★★ , recommended (nostutter) *)
(* Formulating inductive definitions of properties is an important
skill you'll need in this course. Try to solve this exercise
without any help at all.
We say that a list "stutters" if it repeats the same element
consecutively. The property "[nostutter mylist]" means that
[mylist] does not stutter. Formulate an inductive definition for
[nostutter]. (This is different from the [NoDup] property in the
exercise above; the sequence [1;4;1] repeats but does not
stutter.) *)
(** 述語の帰納的な定義を定式化できるようになるというのは、これから先の学習に必要なスキルになってきま
す。
同じ数値が連続して現れるリストを "stutters" （どもったリスト）と呼ぶことにします。述語 "[nostutter mylist]" は、 [mylist] が「どもったリスト」でないことを意味しています。[nostutter] の帰納的な定義を記
述しなさい。（これは以前の練習問題に出てきた [no_repeats] という述語とは異なるものです。リスト [1,4,1] は repeats ではありますが stutter ではありません。）
*)
Inductive nostutter {X:Type} : list X -> Prop :=
(* FILL IN HERE *)
.
(* Make sure each of these tests succeeds, but feel free to change
the suggested proof (in comments) if the given one doesn't work
reflect_ifofor you. Your definition might be different from ours and still
f. intro.
repeat match goal with
h: nostutter _ |- _ => inversion h; clear h; subst
end.
contradiction H1; auto. Qed.
be correct, in which case the examples might need a different
proof. (You'll notice that the suggested proofs use a number of
tactics we haven't talked about, to make them more robust to
different possible ways of defining [nostutter]. You can probably
just uncomment and use them as-is, but you can also prove each
example with more basic tactics.) *)
(** できた定義が、以下のテストを通過することを確認してください。通過できないものがあったら、定義を修
正してもかまいません。あなたの書いた定義が、正しくはあるけれど私の用意した模範解答と異なっているかも
しれません。その場合、このテストを通過するために別の証明を用意する必要があります。
以下の Example にコメントとして提示された証明には、色々な種類の[nostutter] の定義に対応できるように>
するため、まだ説明していないタクティックがいくつか使用されています。 まずこれらのコメントをはずした>
だけの状態で確認できればいいのですが、もしそうしたいなら、これらの証明をもっと基本的なタクティックで
書き換えて証明してもかまいません。
*)
Example test_nostutter_1: nostutter [3;1;4;1;5;6].
(* FILL IN HERE *) Admitted.
(*
Proof. repeat constructor; apply beq_nat_false_iff; auto.
Qed.
*)
Example test_nostutter_2: nostutter (@nil nat).
(* FILL IN HERE *) Admitted.
(*
Proof. repeat constructor; apply beq_nat_false_iff; auto.
Qed.
*)
Example test_nostutter_3: nostutter [5].
(* FILL IN HERE *) Admitted.
(*
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
*)
Example test_nostutter_4: not (nostutter [3;1;1;4]).
(* FILL IN HERE *) Admitted.
(*
Proof. intro.
repeat match goal with
h: nostutter _ |- _ => inversion h; clear h; subst
end.
contradiction H1; auto. Qed.
*)
(** [] *)
(* **** Exercise: 4 stars, advanced (filter_challenge) *)
(** **** 練習問題: ★★★★, advanced (filter_challenge) *)
(** Let's prove that our definition of [filter] from the [Poly]
chapter matches an abstract specification. Here is the
specification, written out informally in English:
A list [l] is an "in-order merge" of [l1] and [l2] if it contains
all the same elements as [l1] and [l2], in the same order as [l1]
and [l2], but possibly interleaved. For example,
[1;4;6;2;3]
is an in-order merge of
[1;6;2]
and
[4;3].
Now, suppose we have a set [X], a function [test: X->bool], and a
list [l] of type [list X]. Suppose further that [l] is an
in-order merge of two lists, [l1] and [l2], such that every item
in [l1] satisfies [test] and no item in [l2] satisfies test. Then
[filter test l = l1].
Translate this specification into a Coq theorem and prove
it. (You'll need to begin by defining what it means for one list
to be a merge of two others. Do this with an inductive relation,
not a [Fixpoint].) *)
(** [Poly]の章から我々の[filter]の定義が理論上の仕様を満たしていることを証明しましょう。
ここで言う仕様とは日本語で非形式的に書くと以下のものになります。
集合 [X] と関数 [test: X->bool]、リスト[l] とその型 [list X] を想定する。
さらに、[l] が二つのリスト [l1] と [l2] が順序を維持したままマージされたもので、
リスト [l1] の要素はすべて [test] を満たし、 [l2] の要素はすべて満たさないとすると、
[filter test l = l1] が成り立つ。
リスト [l] が [l1] と [l2] を順序を維持したままマージしたものである、とは、
それが [l1] と [l2] の要素をすべて含んでいて、しかも 互いに入り組んではいても
[l1] 、 [l2] の要素が同じ順序になっている、ということです。例えば、
[1,4,6,2,3]
は、以下の二つを順序を維持したままマージしたものです。
[1,6,2]
と、
[4,3]
課題は、この仕様をCoq の定理の形に書き直し、それを証明することです。
（ヒント：まず、一つのリストが二つのリストをマージしたものとなっている、
ということを示す定義を書く必要がありますが、これは帰納的な関係であって、
[Fixpoint] で書くようなものではありません。）
*)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 5 stars, advanced, optional (filter_challenge_2) *)
(** **** 練習問題: ★★★★★, advanced, optional (filter_challenge_2) *)
(* A different way to characterize the behavior of [filter] goes like
this: Among all subsequences of [l] with the property that [test]
evaluates to [true] on all their members, [filter test l] is the
longest. Formalize this claim and prove it. *)
(** [filter] の振る舞いに関する特性を別の切り口で表すとこうなります。
「[test] の結果が [true] なる要素だけでできた、リスト [l] のすべての部分リストの中で、
[filter test l] が最も長いリストである。」これを形式的に記述し、それを証明しなさい。 *)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 4 stars, optional (palindromes) *)
(** **** 練習問題 ★★★★ recommended (palindromes) *)
(** A palindrome is a sequence that reads the same backwards as
forwards.
- Define an inductive proposition [pal] on [list X] that
captures what it means to be a palindrome. (Hint: You'll need
three cases. Your definition should be based on the structure
of the list; just having a single constructor like
c : forall l, l = rev l -> pal l
may seem obvious, but will not work very well.)
- Prove ([pal_app_rev]) that
forall l, pal (l ++ rev l).
- Prove ([pal_rev] that)
forall l, pal l -> l = rev l.
*)
(** palindrome（回文）は、最初から読んでも逆から読んでも同じになるような シーケンスです。
- [list X] でパラメータ化され、それが palindrome であることを示すような帰納的命題 [pal] を定義し
なさい。（ヒント：これには三つのケースが必要です。この定義は、リストの構造に基いたものとなるはずです
。まず一つのコンストラクタ、
c : forall l, l = rev l -> pal l
は明らかですが、これはあまりうまくいきません。)
- 以下を証明しなさい。
forall l, pal (l ++ rev l).
- 以下を証明しなさい。
forall l, pal l -> l = rev l.
*)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 5 stars, optional (palindrome_converse) *)
(** **** 練習問題 ★★★★★, optional (palindrome_converse) *)
(* Again, the converse direction is significantly more difficult, due
to the lack of evidence. Using your definition of [pal] from the
previous exercise, prove that
forall l, l = rev l -> pal l.
*)
(** もう一度言いますが、逆方向は大変難しいです。根拠が足りないせいです。あなたの[pal]の定義を用いて下記を証明しなさい。
forall l, l = rev l -> pal l.
*)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 4 stars, advanced, optional (NoDup) *)
(** **** 練習問題 ★★★★, advanced, optional (NoDup) *)
(* Recall the definition of the [In] property from the [Logic]
chapter, which asserts that a value [x] appears at least once in a
list [l]: *)
(** [Logic]の章で行なった[In]という属性の定義を思い出してください。[x]がリスト[l]に少なくとも一度表われることを
表明します。*)
(* Fixpoint In (A : Type) (x : A) (l : list A) : Prop :=
match l with
| [] => False
| x' :: l' => x' = x \/ In A x l'
end *)
(* Your first task is to use [In] to define a proposition [disjoint X
l1 l2], which should be provable exactly when [l1] and [l2] are
lists (with elements of type X) that have no elements in
common. *)
(** 最初の課題は、[In]を使って、[disjoint X l1 l2]という命題を定義することです。
その命題は、(Xという型の要素を持つ)[l1]と[l2]が共通の要素を持たないときに、証明されます。*)
(* FILL IN HERE *)
(* Next, use [In] to define an inductive proposition [NoDup X
l], which should be provable exactly when [l] is a list (with
elements of type [X]) where every member is different from every
other. For example, [NoDup nat [1;2;3;4]] and [NoDup
bool []] should be provable, while [NoDup nat [1;2;1]] and
[NoDup bool [true;true]] should not be. *)
(** 次に、[In]を使って、[NoDup X l]という帰納命題を定義しなさい。その命題は、[l]がそのどのメンバも他のメンバと異なっているときにのみ
証明される命題です。
.例えば、[NoDump nat [1;2;3;4]]と[NoDup bool []]は証明可能ですが、[NoDup not [1;2;1]]や[NoDup bool [true;true]]
は証明不可能です。*)
(* FILL IN HERE *)
(* Finally, state and prove one or more interesting theorems relating
[disjoint], [NoDup] and [++] (list append). *)
(** 最後に、[disjoint]と[NoDup]と[++](リストの結合)に関係した面白い定理を述べて証明しなさい *)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 4 stars, advanced, optional (pigeonhole principle) *)
(** **** 練習問題: ★★★★, advanced (pigeonhole principle) *)
(* The _pigeonhole principle_ states a basic fact about counting: if
we distribute more than [n] items into [n] pigeonholes, some
pigeonhole must contain at least two items. As often happens, this
apparently trivial fact about numbers requires non-trivial
machinery to prove, but we now have enough... *)
(** 「鳩の巣定理（ "pigeonhole principle" ）」は、「数えあげる」ということについての基本的な事実を
提示しています。「もし [n] 個の鳩の巣に[n] 個より多い数のものを入れようとするなら、どのような入れ方>
をしてもいくつかの鳩の巣には必ず一つ以上のものが入ることになる。」というもので、この、数値に関する見
るからに自明な事実を証明するにも、なかなか自明とは言えない手段が必要になります。我々は既にそれを知っ
ているのですが... *)
(* First prove an easy useful lemma. *)
(** まず簡単ですが有用な補題を証明してください。 *)
Lemma in_split : forall (X:Type) (x:X) (l:list X),
In x l ->
exists l1 l2, l = l1 ++ x :: l2.
Proof.
(* FILL IN HERE *) Admitted.
(* Now define a property [repeats] such that [repeats X l] asserts
that [l] contains at least one repeated element (of type [X]). *)
(** [次に属性[repeats]を定義してください。[repeats X l]のように使用して、lが少なくとも一度以上繰替えされる([X]型の)要素として現われることを主張するものです。*)
Inductive repeats {X:Type} : list X -> Prop :=
(* FILL IN HERE *)
.
(* Now, here's a way to formalize the pigeonhole principle. Suppose
list [l2] represents a list of pigeonhole labels, and list [l1]
represents the labels assigned to a list of items. If there are
more items than labels, at least two items must have the same
label -- i.e., list [l1] must contain repeats.
This proof is much easier if you use the [excluded_middle]
hypothesis to show that [In] is decidable, i.e., [forall x l, (In x
l) \/ ~ (In x l)]. However, it is also possible to make the proof
go through _without_ assuming that [In] is decidable; if you
manage to do this, you will not need the [excluded_middle]
hypothesis. *)
(** この「鳩の巣定理」を定式化する方法を一つ挙げておきましょう。リスト [l2] が鳩の巣に貼られたラベルの一覧を、リスト [l1] はそのラベルの、アイテムへの割り当ての一覧を表しているとします。もしラベルよりも沢山のアイテムがあったならば、少なくとも二つのアイテムに同じラベルが貼られていることになります。--つまりリスト[l1]は繰り返しを含んでなければなりません。
この証明はもし[In]が決定可能であるということ、つまり [forall x l, (In x l) \/ ~ (In x l) ] を示すために[exclude_middle]排中律を仮説としてが使えればもっと簡単になります。
しかし、[In]が決定可能であることを仮定しないで証明をすることも可能です: これを何とかやってやろうと思うなら、[excluded_middle]の仮定は必要なくなります。 *)
おそらくこの証明には「排中律（ [excluded_middle] ）」が必要になるでしょう。 *)
Theorem pigeonhole_principle: forall (X:Type) (l1 l2:list X),
excluded_middle ->
(forall x, In x l1 -> In x l2) ->
length l2 < length l1 ->
repeats l1.
Proof.
intros X l1. induction l1 as [|x l1' IHl1'].
(* FILL IN HERE *) Admitted.
(** [] *)
(** $Date: 2016-12-17 23:53:20 -0500 (Sat, 17 Dec 2016) $ *)
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* XGMII 10GBASE-R encoder
*/
module xgmii_baser_enc_64 #
(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2
)
(
input wire clk,
input wire rst,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_txd,
input wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* 10GBASE-R encoded interface
*/
output wire [DATA_WIDTH-1:0] encoded_tx_data,
output wire [HDR_WIDTH-1:0] encoded_tx_hdr,
/*
* Status
*/
output wire tx_bad_block
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
localparam [7:0]
XGMII_IDLE = 8'h07,
XGMII_LPI = 8'h06,
XGMII_START = 8'hfb,
XGMII_TERM = 8'hfd,
XGMII_ERROR = 8'hfe,
XGMII_SEQ_OS = 8'h9c,
XGMII_RES_0 = 8'h1c,
XGMII_RES_1 = 8'h3c,
XGMII_RES_2 = 8'h7c,
XGMII_RES_3 = 8'hbc,
XGMII_RES_4 = 8'hdc,
XGMII_RES_5 = 8'hf7,
XGMII_SIG_OS = 8'h5c;
localparam [6:0]
CTRL_IDLE = 7'h00,
CTRL_LPI = 7'h06,
CTRL_ERROR = 7'h1e,
CTRL_RES_0 = 7'h2d,
CTRL_RES_1 = 7'h33,
CTRL_RES_2 = 7'h4b,
CTRL_RES_3 = 7'h55,
CTRL_RES_4 = 7'h66,
CTRL_RES_5 = 7'h78;
localparam [3:0]
O_SEQ_OS = 4'h0,
O_SIG_OS = 4'hf;
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
localparam [7:0]
BLOCK_TYPE_CTRL = 8'h1e, // C7 C6 C5 C4 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_4 = 8'h2d, // D7 D6 D5 O4 C3 C2 C1 C0 BT
BLOCK_TYPE_START_4 = 8'h33, // D7 D6 D5 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_START = 8'h66, // D7 D6 D5 O0 D3 D2 D1 BT
BLOCK_TYPE_OS_04 = 8'h55, // D7 D6 D5 O4 O0 D3 D2 D1 BT
BLOCK_TYPE_START_0 = 8'h78, // D7 D6 D5 D4 D3 D2 D1 BT
BLOCK_TYPE_OS_0 = 8'h4b, // C7 C6 C5 C4 O0 D3 D2 D1 BT
BLOCK_TYPE_TERM_0 = 8'h87, // C7 C6 C5 C4 C3 C2 C1 BT
BLOCK_TYPE_TERM_1 = 8'h99, // C7 C6 C5 C4 C3 C2 D0 BT
BLOCK_TYPE_TERM_2 = 8'haa, // C7 C6 C5 C4 C3 D1 D0 BT
BLOCK_TYPE_TERM_3 = 8'hb4, // C7 C6 C5 C4 D2 D1 D0 BT
BLOCK_TYPE_TERM_4 = 8'hcc, // C7 C6 C5 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_5 = 8'hd2, // C7 C6 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_6 = 8'he1, // C7 D5 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_7 = 8'hff; // D6 D5 D4 D3 D2 D1 D0 BT
reg [DATA_WIDTH*7/8-1:0] encoded_ctrl;
reg [CTRL_WIDTH-1:0] encode_err;
reg [DATA_WIDTH-1:0] encoded_tx_data_reg = {DATA_WIDTH{1'b0}}, encoded_tx_data_next;
reg [HDR_WIDTH-1:0] encoded_tx_hdr_reg = {HDR_WIDTH{1'b0}}, encoded_tx_hdr_next;
reg tx_bad_block_reg = 1'b0, tx_bad_block_next;
assign encoded_tx_data = encoded_tx_data_reg;
assign encoded_tx_hdr = encoded_tx_hdr_reg;
assign tx_bad_block = tx_bad_block_reg;
integer i;
always @* begin
tx_bad_block_next = 1'b0;
for (i = 0; i < CTRL_WIDTH; i = i + 1) begin
if (xgmii_txc[i]) begin
// control
case (xgmii_txd[8*i +: 8])
XGMII_IDLE: begin
encoded_ctrl[7*i +: 7] = CTRL_IDLE;
encode_err[i] = 1'b0;
end
XGMII_LPI: begin
encoded_ctrl[7*i +: 7] = CTRL_LPI;
encode_err[i] = 1'b0;
end
XGMII_ERROR: begin
encoded_ctrl[7*i +: 7] = CTRL_ERROR;
encode_err[i] = 1'b0;
end
XGMII_RES_0: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_0;
encode_err[i] = 1'b0;
end
XGMII_RES_1: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_1;
encode_err[i] = 1'b0;
end
XGMII_RES_2: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_2;
encode_err[i] = 1'b0;
end
XGMII_RES_3: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_3;
encode_err[i] = 1'b0;
end
XGMII_RES_4: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_4;
encode_err[i] = 1'b0;
end
XGMII_RES_5: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_5;
encode_err[i] = 1'b0;
end
default: begin
encoded_ctrl[7*i +: 7] = CTRL_ERROR;
encode_err[i] = 1'b1;
end
endcase
end else begin
// data (always invalid as control)
encoded_ctrl[7*i +: 7] = CTRL_ERROR;
encode_err[i] = 1'b1;
end
end
if (xgmii_txc == 8'h00) begin
encoded_tx_data_next = xgmii_txd;
encoded_tx_hdr_next = SYNC_DATA;
tx_bad_block_next = 1'b0;
end else begin
if (xgmii_txc == 8'h1f && xgmii_txd[39:32] == XGMII_SEQ_OS) begin
// ordered set in lane 4
encoded_tx_data_next = {xgmii_txd[63:40], O_SEQ_OS, encoded_ctrl[27:0], BLOCK_TYPE_OS_4};
tx_bad_block_next = encode_err[3:0] != 0;
end else if (xgmii_txc == 8'h1f && xgmii_txd[39:32] == XGMII_START) begin
// start in lane 4
encoded_tx_data_next = {xgmii_txd[63:40], 4'd0, encoded_ctrl[27:0], BLOCK_TYPE_START_4};
tx_bad_block_next = encode_err[3:0] != 0;
end else if (xgmii_txc == 8'h11 && xgmii_txd[7:0] == XGMII_SEQ_OS && xgmii_txd[39:32] == XGMII_START) begin
// ordered set in lane 0, start in lane 4
encoded_tx_data_next = {xgmii_txd[63:40], 4'd0, O_SEQ_OS, xgmii_txd[31:8], BLOCK_TYPE_OS_START};
tx_bad_block_next = 1'b0;
end else if (xgmii_txc == 8'h11 && xgmii_txd[7:0] == XGMII_SEQ_OS && xgmii_txd[39:32] == XGMII_SEQ_OS) begin
// ordered set in lane 0 and lane 4
encoded_tx_data_next = {xgmii_txd[63:40], O_SEQ_OS, O_SEQ_OS, xgmii_txd[31:8], BLOCK_TYPE_OS_04};
tx_bad_block_next = 1'b0;
end else if (xgmii_txc == 8'h01 && xgmii_txd[7:0] == XGMII_START) begin
// start in lane 0
encoded_tx_data_next = {xgmii_txd[63:8], BLOCK_TYPE_START_0};
tx_bad_block_next = 1'b0;
end else if (xgmii_txc == 8'hf1 && xgmii_txd[7:0] == XGMII_SEQ_OS) begin
// ordered set in lane 0
encoded_tx_data_next = {encoded_ctrl[55:28], O_SEQ_OS, xgmii_txd[31:8], BLOCK_TYPE_OS_0};
tx_bad_block_next = encode_err[7:4] != 0;
end else if (xgmii_txc == 8'hff && xgmii_txd[7:0] == XGMII_TERM) begin
// terminate in lane 0
encoded_tx_data_next = {encoded_ctrl[55:7], 7'd0, BLOCK_TYPE_TERM_0};
tx_bad_block_next = encode_err[7:1] != 0;
end else if (xgmii_txc == 8'hfe && xgmii_txd[15:8] == XGMII_TERM) begin
// terminate in lane 1
encoded_tx_data_next = {encoded_ctrl[55:14], 6'd0, xgmii_txd[7:0], BLOCK_TYPE_TERM_1};
tx_bad_block_next = encode_err[7:2] != 0;
end else if (xgmii_txc == 8'hfc && xgmii_txd[23:16] == XGMII_TERM) begin
// terminate in lane 2
encoded_tx_data_next = {encoded_ctrl[55:21], 5'd0, xgmii_txd[15:0], BLOCK_TYPE_TERM_2};
tx_bad_block_next = encode_err[7:3] != 0;
end else if (xgmii_txc == 8'hf8 && xgmii_txd[31:24] == XGMII_TERM) begin
// terminate in lane 3
encoded_tx_data_next = {encoded_ctrl[55:28], 4'd0, xgmii_txd[23:0], BLOCK_TYPE_TERM_3};
tx_bad_block_next = encode_err[7:4] != 0;
end else if (xgmii_txc == 8'hf0 && xgmii_txd[39:32] == XGMII_TERM) begin
// terminate in lane 4
encoded_tx_data_next = {encoded_ctrl[55:35], 3'd0, xgmii_txd[31:0], BLOCK_TYPE_TERM_4};
tx_bad_block_next = encode_err[7:5] != 0;
end else if (xgmii_txc == 8'he0 && xgmii_txd[47:40] == XGMII_TERM) begin
// terminate in lane 5
encoded_tx_data_next = {encoded_ctrl[55:42], 2'd0, xgmii_txd[39:0], BLOCK_TYPE_TERM_5};
tx_bad_block_next = encode_err[7:6] != 0;
end else if (xgmii_txc == 8'hc0 && xgmii_txd[55:48] == XGMII_TERM) begin
// terminate in lane 6
encoded_tx_data_next = {encoded_ctrl[55:49], 1'd0, xgmii_txd[47:0], BLOCK_TYPE_TERM_6};
tx_bad_block_next = encode_err[7] != 0;
end else if (xgmii_txc == 8'h80 && xgmii_txd[63:56] == XGMII_TERM) begin
// terminate in lane 7
encoded_tx_data_next = {xgmii_txd[55:0], BLOCK_TYPE_TERM_7};
tx_bad_block_next = 1'b0;
end else if (xgmii_txc == 8'hff) begin
// all control
encoded_tx_data_next = {encoded_ctrl, BLOCK_TYPE_CTRL};
tx_bad_block_next = encode_err != 0;
end else begin
// no corresponding block format
encoded_tx_data_next = {{8{CTRL_ERROR}}, BLOCK_TYPE_CTRL};
tx_bad_block_next = 1'b1;
end
encoded_tx_hdr_next = SYNC_CTRL;
end
end
always @(posedge clk) begin
encoded_tx_data_reg <= encoded_tx_data_next;
encoded_tx_hdr_reg <= encoded_tx_hdr_next;
tx_bad_block_reg <= tx_bad_block_next;
end
endmodule
`resetall
|
// megafunction wizard: %LPM_MULT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: mult16_12.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module mult16_12 (
clock,
dataa,
datab,
result);
input clock;
input [15:0] dataa;
input [15:0] datab;
output [31:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "16"
// Retrieval info: PRIVATE: WidthB NUMERIC "16"
// Retrieval info: PRIVATE: WidthP NUMERIC "32"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: optimize NUMERIC "1"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=9"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "32"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16_12.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16_12.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16_12.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16_12.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16_12_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16_12_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16_12_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16_12_wave*.jpg FALSE
// Retrieval info: LIB_FILE: lpm
|
// File gh_fifo_async16_sr.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
// vhd2vl is Free (libre) Software:
// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
// Verilog for correctness, ideally with a formal verification tool.
//
// You are welcome to redistribute vhd2vl under certain conditions.
// See the license (GPLv2) file included with the source for details.
// The result of translation follows. Its copyright status should be
// considered unchanged from the original VHDL.
//-------------------------------------------------------------------
// Filename: gh_fifo_async16_sr.vhd
//
//
// Description:
// an Asynchronous FIFO
//
// Copyright (c) 2006 by George Huber
// an OpenCores.org Project
// free to use, but see documentation for conditions
//
// Revision History:
// Revision Date Author Comment
// -------- ---------- --------- -----------
// 1.0 12/17/06 h lefevre Initial revision
//
//------------------------------------------------------
// no timescale needed
module gh_fifo_async16_sr(
clk_WR,
clk_RD,
rst,
srst,
WR,
RD,
D,
Q,
empty,
full
);
parameter [31:0] data_width=8;
// size of data bus
input clk_WR;
// write clock
input clk_RD;
// read clock
input rst;
// resets counters
input srst;
// resets counters (sync with clk_WR)
input WR;
// write control
input RD;
// read control
input [data_width - 1:0] D;
output [data_width - 1:0] Q;
output empty;
output full;
wire clk_WR;
wire clk_RD;
wire rst;
wire srst;
wire WR;
wire RD;
wire [data_width - 1:0] D;
wire [data_width - 1:0] Q;
wire empty;
wire full;
reg [data_width - 1:0] ram_mem[15:0];
wire iempty;
wire ifull;
wire add_WR_CE;
reg [4:0] add_WR; // 4 bits are used to address MEM
reg [4:0] add_WR_GC; // 5 bits are used to compare
wire [4:0] n_add_WR; // for empty, full flags
reg [4:0] add_WR_RS; // synced to read clk
wire add_RD_CE;
reg [4:0] add_RD;
reg [4:0] add_RD_GC;
reg [4:0] add_RD_GCwc;
wire [4:0] n_add_RD;
reg [4:0] add_RD_WS; // synced to write clk
reg srst_w;
reg isrst_w;
reg srst_r;
reg isrst_r;
//------------------------------------------
//----- memory -----------------------------
//------------------------------------------
always @(posedge clk_WR) begin
if(((WR == 1'b 1) && (ifull == 1'b 0))) begin
ram_mem[(add_WR[3:0])] <= D;
end
end
assign Q = ram_mem[(add_RD[3:0])];
//---------------------------------------
//--- Write address counter -------------
//---------------------------------------
assign add_WR_CE = (ifull == 1'b 1) ? 1'b 0 : (WR == 1'b 0) ? 1'b 0 : 1'b 1;
assign n_add_WR = add_WR + 4'h 1;
always @(posedge clk_WR or posedge rst) begin
if((rst == 1'b 1)) begin
add_WR <= {5{1'b0}};
add_RD_WS <= 5'b 11000;
add_WR_GC <= {5{1'b0}};
end else begin
add_RD_WS <= add_RD_GCwc;
if((srst_w == 1'b 1)) begin
add_WR <= {5{1'b0}};
add_WR_GC <= {5{1'b0}};
end
else if((add_WR_CE == 1'b 1)) begin
add_WR <= n_add_WR;
add_WR_GC[0] <= n_add_WR[0] ^ n_add_WR[1];
add_WR_GC[1] <= n_add_WR[1] ^ n_add_WR[2];
add_WR_GC[2] <= n_add_WR[2] ^ n_add_WR[3];
add_WR_GC[3] <= n_add_WR[3] ^ n_add_WR[4];
add_WR_GC[4] <= n_add_WR[4];
end
else begin
add_WR <= add_WR;
add_WR_GC <= add_WR_GC;
end
end
end
assign full = ifull;
assign ifull = (iempty == 1'b 1) ? 1'b 0 : (add_RD_WS != add_WR_GC) ? 1'b 0 : 1'b 1;
//---------------------------------------
//--- Read address counter --------------
//---------------------------------------
assign add_RD_CE = (iempty == 1'b 1) ? 1'b 0 : (RD == 1'b 0) ? 1'b 0 : 1'b 1;
assign n_add_RD = add_RD + 4'h 1;
always @(posedge clk_RD or posedge rst) begin
if((rst == 1'b 1)) begin
add_RD <= {5{1'b0}};
add_WR_RS <= {5{1'b0}};
add_RD_GC <= {5{1'b0}};
add_RD_GCwc <= 5'b 11000;
end else begin
add_WR_RS <= add_WR_GC;
if((srst_r == 1'b 1)) begin
add_RD <= {5{1'b0}};
add_RD_GC <= {5{1'b0}};
add_RD_GCwc <= 5'b 11000;
end
else if((add_RD_CE == 1'b 1)) begin
add_RD <= n_add_RD;
add_RD_GC[0] <= n_add_RD[0] ^ n_add_RD[1];
add_RD_GC[1] <= n_add_RD[1] ^ n_add_RD[2];
add_RD_GC[2] <= n_add_RD[2] ^ n_add_RD[3];
add_RD_GC[3] <= n_add_RD[3] ^ n_add_RD[4];
add_RD_GC[4] <= n_add_RD[4];
add_RD_GCwc[0] <= n_add_RD[0] ^ n_add_RD[1];
add_RD_GCwc[1] <= n_add_RD[1] ^ n_add_RD[2];
add_RD_GCwc[2] <= n_add_RD[2] ^ n_add_RD[3];
add_RD_GCwc[3] <= n_add_RD[3] ^ (( ~n_add_RD[4]));
add_RD_GCwc[4] <= ( ~n_add_RD[4]);
end
else begin
add_RD <= add_RD;
add_RD_GC <= add_RD_GC;
add_RD_GCwc <= add_RD_GCwc;
end
end
end
assign empty = iempty;
assign iempty = (add_WR_RS == add_RD_GC) ? 1'b 1 : 1'b 0;
//--------------------------------
//- sync rest stuff --------------
//- srst is sync with clk_WR -----
//- srst_r is sync with clk_RD ---
//--------------------------------
always @(posedge clk_WR or posedge rst) begin
if((rst == 1'b 1)) begin
srst_w <= 1'b 0;
isrst_r <= 1'b 0;
end else begin
isrst_r <= srst_r;
if((srst == 1'b 1)) begin
srst_w <= 1'b 1;
end
else if((isrst_r == 1'b 1)) begin
srst_w <= 1'b 0;
end
end
end
always @(posedge clk_RD or posedge rst) begin
if((rst == 1'b 1)) begin
srst_r <= 1'b 0;
isrst_w <= 1'b 0;
end else begin
isrst_w <= srst_w;
if((isrst_w == 1'b 1)) begin
srst_r <= 1'b 1;
end
else begin
srst_r <= 1'b 0;
end
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 10:19:56 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux2x1_10_0_0/RAT_Mux2x1_10_0_0_stub.v
// Design : RAT_Mux2x1_10_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "Mux2x1_10,Vivado 2016.4" *)
module RAT_Mux2x1_10_0_0(A, B, SEL, X)
/* synthesis syn_black_box black_box_pad_pin="A[9:0],B[9:0],SEL,X[9:0]" */;
input [9:0]A;
input [9:0]B;
input SEL;
output [9:0]X;
endmodule
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the user's design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// 503-286-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: [email protected]
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_load_store_unit.v
// Title : Load and store unit
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : Instead of disallowing an instruction cache miss on a data cache
// : miss, both can now occur at the same time. If both occur at same
// : time, then restart address is the address of instruction that
// : caused data cache miss.
// Version : 3.2
// : EBRs use SYNC resets instead of ASYNC resets.
// Version : 3.3
// : Support for new non-cacheable Data Memory that is accessible by
// : the data port and has a one cycle access latency.
// Version : 3.4
// : No change
// Version : 3.5
// : Bug fix: Inline memory is correctly generated if it is not a
// : power-of-two
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_load_store_unit (
// ----- Inputs -------
clk_i,
rst_i,
// From pipeline
stall_a,
stall_x,
stall_m,
kill_m,
exception_m,
store_operand_x,
load_store_address_x,
load_store_address_m,
load_store_address_w,
`ifdef CFG_MMU_ENABLED
load_d,
store_d,
`endif
load_x,
store_x,
load_q_x,
store_q_x,
load_q_m,
store_q_m,
sign_extend_x,
size_x,
`ifdef CFG_DCACHE_ENABLED
dflush,
`endif
`ifdef CFG_IROM_ENABLED
irom_data_m,
`endif
`ifdef CFG_MMU_ENABLED
dtlb_enable,
tlbpaddr,
tlbvaddr,
dtlb_update,
dtlb_flush,
dtlb_invalidate,
`endif
// From Wishbone
d_dat_i,
d_ack_i,
d_err_i,
d_rty_i,
// ----- Outputs -------
// To pipeline
`ifdef CFG_DCACHE_ENABLED
dcache_refill_request,
dcache_restart_request,
dcache_stall_request,
dcache_refilling,
`endif
`ifdef CFG_IROM_ENABLED
irom_store_data_m,
irom_address_xm,
irom_we_xm,
irom_stall_request_x,
`endif
load_data_w,
stall_wb_load,
`ifdef CFG_MMU_ENABLED
dtlb_stall_request,
dtlb_miss_vfn,
dtlb_miss_x,
dtlb_fault_x,
`endif
// To Wishbone
d_dat_o,
d_adr_o,
d_cyc_o,
d_sel_o,
d_stb_o,
d_we_o,
d_cti_o,
d_lock_o,
d_bte_o
);
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
parameter associativity = 1; // Associativity of the cache (Number of ways)
parameter sets = 512; // Number of sets
parameter bytes_per_line = 16; // Number of bytes per cache line
parameter base_address = 0; // Base address of cachable memory
parameter limit = 0; // Limit (highest address) of cachable memory
// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
localparam addr_offset_width = bytes_per_line == 4 ? 1 : `CLOG2(bytes_per_line)-2;
localparam addr_offset_lsb = 2;
localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input stall_a; // A stage stall
input stall_x; // X stage stall
input stall_m; // M stage stall
input kill_m; // Kill instruction in M stage
input exception_m; // An exception occured in the M stage
input [`LM32_WORD_RNG] store_operand_x; // Data read from register to store
input [`LM32_WORD_RNG] load_store_address_x; // X stage load/store address
input [`LM32_WORD_RNG] load_store_address_m; // M stage load/store address
input [1:0] load_store_address_w; // W stage load/store address (only least two significant bits are needed)
`ifdef CFG_MMU_ENABLED
input load_d; // Load instruction in D stage
input store_d; // Store instruction in D stage
`endif
input load_x; // Load instruction in X stage
input store_x; // Store instruction in X stage
input load_q_x; // Load instruction in X stage
input store_q_x; // Store instruction in X stage
input load_q_m; // Load instruction in M stage
input store_q_m; // Store instruction in M stage
input sign_extend_x; // Whether load instruction in X stage should sign extend or zero extend
input [`LM32_SIZE_RNG] size_x; // Size of load or store (byte, hword, word)
`ifdef CFG_DCACHE_ENABLED
input dflush; // Flush the data cache
`endif
`ifdef CFG_IROM_ENABLED
input [`LM32_WORD_RNG] irom_data_m; // Data from Instruction-ROM
`endif
`ifdef CFG_MMU_ENABLED
input dtlb_enable; // Data TLB enable
input [`LM32_WORD_RNG] tlbpaddr; // TLBPADDR CSR
input [`LM32_WORD_RNG] tlbvaddr; // TLBVADDR CSR
input dtlb_update; // Data TLB update
input dtlb_flush; // Data TLB flush
input dtlb_invalidate; // Data TLB invalidate
`endif
input [`LM32_WORD_RNG] d_dat_i; // Data Wishbone interface read data
input d_ack_i; // Data Wishbone interface acknowledgement
input d_err_i; // Data Wishbone interface error
input d_rty_i; // Data Wishbone interface retry
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
`ifdef CFG_DCACHE_ENABLED
output dcache_refill_request; // Request to refill data cache
wire dcache_refill_request;
output dcache_restart_request; // Request to restart the instruction that caused a data cache miss
wire dcache_restart_request;
output dcache_stall_request; // Data cache stall request
wire dcache_stall_request;
output dcache_refilling;
wire dcache_refilling;
`endif
`ifdef CFG_IROM_ENABLED
output [`LM32_WORD_RNG] irom_store_data_m; // Store data to Instruction ROM
wire [`LM32_WORD_RNG] irom_store_data_m;
output [`LM32_WORD_RNG] irom_address_xm; // Load/store address to Instruction ROM
wire [`LM32_WORD_RNG] irom_address_xm;
output irom_we_xm; // Write-enable of 2nd port of Instruction ROM
wire irom_we_xm;
output irom_stall_request_x; // Stall instruction in D stage
wire irom_stall_request_x;
`endif
output [`LM32_WORD_RNG] load_data_w; // Result of a load instruction
reg [`LM32_WORD_RNG] load_data_w;
output stall_wb_load; // Request to stall pipeline due to a load from the Wishbone interface
reg stall_wb_load;
`ifdef CFG_MMU_ENABLED
output dtlb_stall_request; // Data TLB stall request
wire dtlb_stall_request;
output [`LM32_WORD_RNG] dtlb_miss_vfn; // Virtual frame number of missed load or store address
wire [`LM32_WORD_RNG] dtlb_miss_vfn;
output dtlb_miss_x; // Indicates if a data TLB miss has occured
wire dtlb_miss_x;
output dtlb_fault_x; // Indicates if a data TLB fault has occured in X stage
wire dtlb_fault_x;
`endif
output [`LM32_WORD_RNG] d_dat_o; // Data Wishbone interface write data
reg [`LM32_WORD_RNG] d_dat_o;
output [`LM32_WORD_RNG] d_adr_o; // Data Wishbone interface address
reg [`LM32_WORD_RNG] d_adr_o;
output d_cyc_o; // Data Wishbone interface cycle
reg d_cyc_o;
output [`LM32_BYTE_SELECT_RNG] d_sel_o; // Data Wishbone interface byte select
reg [`LM32_BYTE_SELECT_RNG] d_sel_o;
output d_stb_o; // Data Wishbone interface strobe
reg d_stb_o;
output d_we_o; // Data Wishbone interface write enable
reg d_we_o;
output [`LM32_CTYPE_RNG] d_cti_o; // Data Wishbone interface cycle type
reg [`LM32_CTYPE_RNG] d_cti_o;
output d_lock_o; // Date Wishbone interface lock bus
reg d_lock_o;
output [`LM32_BTYPE_RNG] d_bte_o; // Data Wishbone interface burst type
wire [`LM32_BTYPE_RNG] d_bte_o;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
// Microcode pipeline registers - See inputs for description
reg [`LM32_SIZE_RNG] size_m;
reg [`LM32_SIZE_RNG] size_w;
reg sign_extend_m;
reg sign_extend_w;
reg [`LM32_WORD_RNG] store_data_x;
reg [`LM32_WORD_RNG] store_data_m;
reg [`LM32_BYTE_SELECT_RNG] byte_enable_x;
reg [`LM32_BYTE_SELECT_RNG] byte_enable_m;
wire [`LM32_WORD_RNG] data_m;
reg [`LM32_WORD_RNG] data_w;
`ifdef CFG_DCACHE_ENABLED
wire dcache_select_x; // Select data cache to load from / store to
reg dcache_select_m;
wire [`LM32_WORD_RNG] dcache_data_m; // Data read from cache
wire [`LM32_WORD_RNG] dcache_refill_address; // Address to refill data cache from
reg dcache_refill_ready; // Indicates the next word of refill data is ready
wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type
wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type
wire last_word; // Indicates if this is the last word in the cache line
wire [`LM32_WORD_RNG] first_address; // First cache refill address
`endif
`ifdef CFG_DRAM_ENABLED
wire dram_select_x; // Select data RAM to load from / store to
reg dram_select_m;
reg dram_bypass_en; // RAW in data RAM; read latched (bypass) value rather than value from memory
reg [`LM32_WORD_RNG] dram_bypass_data; // Latched value of store'd data to data RAM
wire [`LM32_WORD_RNG] dram_data_out; // Data read from data RAM
wire [`LM32_WORD_RNG] dram_data_m; // Data read from data RAM: bypass value or value from memory
wire [`LM32_WORD_RNG] dram_store_data_m; // Data to write to RAM
`endif
wire wb_select_x; // Select Wishbone to load from / store to
`ifdef CFG_IROM_ENABLED
wire irom_select_x; // Select instruction ROM to load from / store to
reg irom_select_m;
`endif
reg wb_select_m;
reg [`LM32_WORD_RNG] wb_data_m; // Data read from Wishbone
reg wb_load_complete; // Indicates when a Wishbone load is complete
`ifdef CFG_MMU_ENABLED
wire [`LM32_WORD_RNG] physical_load_store_address_m; // X stage physical load/store address
wire cache_inhibit_x; // Indicates if data cache should be bypassed
`endif
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
`ifdef CFG_DRAM_ENABLED
`define LM32_DRAM_WIDTH `CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)
`define LM32_DRAM_RNG (`LM32_DRAM_WIDTH-1+2):2
// Data RAM
lm32_ram #(
.data_width (`LM32_WORD_WIDTH),
.address_width (`LM32_DRAM_WIDTH),
.init_file (`CFG_DRAM_INIT_FILE)
) ram (
// ----- Inputs -------
.read_clk (clk_i),
.write_clk (clk_i),
.reset (rst_i),
.enable_read (!stall_x),
.read_address (load_store_address_x[`LM32_DRAM_RNG]),
.enable_write (!stall_m),
.write_address (load_store_address_m[`LM32_DRAM_RNG]),
.write_data (dram_store_data_m),
.write_enable (store_q_m & dram_select_m),
// ----- Outputs -------
.read_data (dram_data_out)
);
/*----------------------------------------------------------------------
EBRs cannot perform reads from location 'written to' on the same clock
edge. Therefore bypass logic is required to latch the store'd value
and use it for the load (instead of value from memory).
----------------------------------------------------------------------*/
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
if (rst_i == `TRUE)
begin
dram_bypass_en <= `FALSE;
dram_bypass_data <= 0;
end
else
begin
if (stall_x == `FALSE)
dram_bypass_data <= dram_store_data_m;
if ( (stall_m == `FALSE)
&& (stall_x == `FALSE)
&& (store_q_m == `TRUE)
&& ( (load_x == `TRUE)
|| (store_x == `TRUE)
)
&& (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2])
)
dram_bypass_en <= `TRUE;
else
if ( (dram_bypass_en == `TRUE)
&& (stall_x == `FALSE)
)
dram_bypass_en <= `FALSE;
end
assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out;
`endif
`ifdef CFG_DCACHE_ENABLED
// Data cache
lm32_dcache #(
.associativity (associativity),
.sets (sets),
.bytes_per_line (bytes_per_line),
.base_address (base_address),
.limit (limit)
) dcache (
// ----- Inputs -----
.clk_i (clk_i),
.rst_i (rst_i),
.stall_a (stall_a),
.stall_x (stall_x),
.stall_m (stall_m),
.address_x (load_store_address_x),
`ifdef CFG_MMU_ENABLED
/* VIPT cache, address_m is (only) used for tag */
.address_m (physical_load_store_address_m),
`else
.address_m (load_store_address_m),
`endif
.load_q_m (load_q_m & dcache_select_m),
.store_q_m (store_q_m & dcache_select_m),
.store_data (store_data_m),
.store_byte_select (byte_enable_m & {4{dcache_select_m}}),
.refill_ready (dcache_refill_ready),
.refill_data (wb_data_m),
.dflush (dflush),
`ifdef CFG_MMU_ENABLED
.dtlb_miss_x (dtlb_miss_x),
`endif
// ----- Outputs -----
.stall_request (dcache_stall_request),
.restart_request (dcache_restart_request),
.refill_request (dcache_refill_request),
.refill_address (dcache_refill_address),
.refilling (dcache_refilling),
.load_data (dcache_data_m)
);
`endif
`ifdef CFG_MMU_ENABLED
// Data TLB
lm32_dtlb dtlb (
// ----- Inputs -----
.clk_i (clk_i),
.rst_i (rst_i),
.enable (dtlb_enable),
.stall_x (stall_x),
.stall_m (stall_m),
.address_x (load_store_address_x),
.address_m (load_store_address_m),
.load_d (load_d),
.store_d (store_d),
.load_q_x (load_q_x),
.store_q_x (store_q_x),
.tlbpaddr (tlbpaddr),
.tlbvaddr (tlbvaddr),
.update (dtlb_update),
.flush (dtlb_flush),
.invalidate (dtlb_invalidate),
// ----- Outputs -----
.physical_load_store_address_m (physical_load_store_address_m),
.stall_request (dtlb_stall_request),
.miss_vfn (dtlb_miss_vfn),
.miss_x (dtlb_miss_x),
.fault_x (dtlb_fault_x),
.cache_inhibit_x (cache_inhibit_x)
);
`endif
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
// Select where data should be loaded from / stored to
`ifdef CFG_DRAM_ENABLED
assign dram_select_x = (load_store_address_x >= `CFG_DRAM_BASE_ADDRESS)
&& (load_store_address_x <= `CFG_DRAM_LIMIT);
`endif
`ifdef CFG_IROM_ENABLED
assign irom_select_x = (load_store_address_x >= `CFG_IROM_BASE_ADDRESS)
&& (load_store_address_x <= `CFG_IROM_LIMIT);
`endif
`ifdef CFG_DCACHE_ENABLED
assign dcache_select_x = (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS)
&& (load_store_address_x <= `CFG_DCACHE_LIMIT)
`ifdef CFG_DRAM_ENABLED
&& (dram_select_x == `FALSE)
`endif
`ifdef CFG_IROM_ENABLED
&& (irom_select_x == `FALSE)
`endif
`ifdef CFG_MMU_ENABLED
&& (cache_inhibit_x == `FALSE)
`endif
;
`endif
assign wb_select_x = `TRUE
`ifdef CFG_DCACHE_ENABLED
&& !dcache_select_x
`endif
`ifdef CFG_DRAM_ENABLED
&& !dram_select_x
`endif
`ifdef CFG_IROM_ENABLED
&& !irom_select_x
`endif
;
// Make sure data to store is in correct byte lane
always @(*)
begin
case (size_x)
`LM32_SIZE_BYTE: store_data_x = {4{store_operand_x[7:0]}};
`LM32_SIZE_HWORD: store_data_x = {2{store_operand_x[15:0]}};
`LM32_SIZE_WORD: store_data_x = store_operand_x;
default: store_data_x = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
// Generate byte enable accoring to size of load or store and address being accessed
always @(*)
begin
casez ({size_x, load_store_address_x[1:0]})
{`LM32_SIZE_BYTE, 2'b11}: byte_enable_x = 4'b0001;
{`LM32_SIZE_BYTE, 2'b10}: byte_enable_x = 4'b0010;
{`LM32_SIZE_BYTE, 2'b01}: byte_enable_x = 4'b0100;
{`LM32_SIZE_BYTE, 2'b00}: byte_enable_x = 4'b1000;
{`LM32_SIZE_HWORD, 2'b1?}: byte_enable_x = 4'b0011;
{`LM32_SIZE_HWORD, 2'b0?}: byte_enable_x = 4'b1100;
{`LM32_SIZE_WORD, 2'b??}: byte_enable_x = 4'b1111;
default: byte_enable_x = 4'bxxxx;
endcase
end
`ifdef CFG_DRAM_ENABLED
// Only replace selected bytes
assign dram_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : dram_data_m[`LM32_BYTE_0_RNG];
assign dram_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : dram_data_m[`LM32_BYTE_1_RNG];
assign dram_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : dram_data_m[`LM32_BYTE_2_RNG];
assign dram_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : dram_data_m[`LM32_BYTE_3_RNG];
`endif
`ifdef CFG_IROM_ENABLED
// Only replace selected bytes
assign irom_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : irom_data_m[`LM32_BYTE_0_RNG];
assign irom_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : irom_data_m[`LM32_BYTE_1_RNG];
assign irom_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : irom_data_m[`LM32_BYTE_2_RNG];
assign irom_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : irom_data_m[`LM32_BYTE_3_RNG];
`endif
`ifdef CFG_IROM_ENABLED
// Instead of implementing a byte-addressable instruction ROM (for store byte instruction),
// a load-and-store architecture is used wherein a 32-bit value is loaded, the requisite
// byte is replaced, and the whole 32-bit value is written back
assign irom_address_xm = ((irom_select_m == `TRUE) && (store_q_m == `TRUE))
? load_store_address_m
: load_store_address_x;
// All store instructions perform a write operation in the M stage
assign irom_we_xm = (irom_select_m == `TRUE)
&& (store_q_m == `TRUE);
// A single port in instruction ROM is available to load-store unit for doing loads/stores.
// Since every store requires a load (in X stage) and then a store (in M stage), we cannot
// allow load (or store) instructions sequentially after the store instructions to proceed
// until the store instruction has vacated M stage (i.e., completed the store operation)
assign irom_stall_request_x = (irom_select_x == `TRUE)
&& (store_q_x == `TRUE);
`endif
`ifdef CFG_DCACHE_ENABLED
`ifdef CFG_DRAM_ENABLED
`ifdef CFG_IROM_ENABLED
// WB + DC + DRAM + IROM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: dram_select_m == `TRUE
? dram_data_m
: irom_select_m == `TRUE
? irom_data_m
: dcache_data_m;
`else
// WB + DC + DRAM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: dram_select_m == `TRUE
? dram_data_m
: dcache_data_m;
`endif
`else
`ifdef CFG_IROM_ENABLED
// WB + DC + IROM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: irom_select_m == `TRUE
? irom_data_m
: dcache_data_m;
`else
// WB + DC
assign data_m = wb_select_m == `TRUE
? wb_data_m
: dcache_data_m;
`endif
`endif
`else
`ifdef CFG_DRAM_ENABLED
`ifdef CFG_IROM_ENABLED
// WB + DRAM + IROM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: dram_select_m == `TRUE
? dram_data_m
: irom_data_m;
`else
// WB + DRAM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: dram_data_m;
`endif
`else
`ifdef CFG_IROM_ENABLED
// WB + IROM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: irom_data_m;
`else
// WB
assign data_m = wb_data_m;
`endif
`endif
`endif
// Sub-word selection and sign/zero-extension for loads
always @(*)
begin
casez ({size_w, load_store_address_w[1:0]})
{`LM32_SIZE_BYTE, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
{`LM32_SIZE_BYTE, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
{`LM32_SIZE_BYTE, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
{`LM32_SIZE_BYTE, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
{`LM32_SIZE_HWORD, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
{`LM32_SIZE_HWORD, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
{`LM32_SIZE_WORD, 2'b??}: load_data_w = data_w;
default: load_data_w = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
// Unused/constant Wishbone signals
assign d_bte_o = `LM32_BTYPE_LINEAR;
`ifdef CFG_DCACHE_ENABLED
// Generate signal to indicate last word in cache line
generate
case (bytes_per_line)
4:
begin
assign first_cycle_type = `LM32_CTYPE_END;
assign next_cycle_type = `LM32_CTYPE_END;
assign last_word = `TRUE;
assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:2], 2'b00};
end
8:
begin
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
assign next_cycle_type = `LM32_CTYPE_END;
assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
end
default:
begin
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
assign next_cycle_type = d_adr_o[addr_offset_msb:addr_offset_lsb+1] == {addr_offset_width-1{1'b1}} ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
end
endcase
endgenerate
`endif
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
// Data Wishbone interface
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
d_cyc_o <= `FALSE;
d_stb_o <= `FALSE;
d_dat_o <= {`LM32_WORD_WIDTH{1'b0}};
d_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
d_we_o <= `FALSE;
d_cti_o <= `LM32_CTYPE_END;
d_lock_o <= `FALSE;
wb_data_m <= {`LM32_WORD_WIDTH{1'b0}};
wb_load_complete <= `FALSE;
stall_wb_load <= `FALSE;
`ifdef CFG_DCACHE_ENABLED
dcache_refill_ready <= `FALSE;
`endif
end
else
begin
`ifdef CFG_DCACHE_ENABLED
// Refill ready should only be asserted for a single cycle
dcache_refill_ready <= `FALSE;
`endif
// Is a Wishbone cycle already in progress?
if (d_cyc_o == `TRUE)
begin
// Is the cycle complete?
if ((d_ack_i == `TRUE) || (d_err_i == `TRUE))
begin
`ifdef CFG_DCACHE_ENABLED
if ((dcache_refilling == `TRUE) && (!last_word))
begin
// Fetch next word of cache line
d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
end
else
`endif
begin
// Refill/access complete
d_cyc_o <= `FALSE;
d_stb_o <= `FALSE;
d_lock_o <= `FALSE;
end
`ifdef CFG_DCACHE_ENABLED
d_cti_o <= next_cycle_type;
// If we are performing a refill, indicate to cache next word of data is ready
dcache_refill_ready <= dcache_refilling;
`endif
// Register data read from Wishbone interface
wb_data_m <= d_dat_i;
// Don't set when stores complete - otherwise we'll deadlock if load in m stage
wb_load_complete <= !d_we_o;
end
// synthesis translate_off
if (d_err_i == `TRUE)
$display ("Data bus error. Address: %x", d_adr_o);
// synthesis translate_on
end
else
begin
`ifdef CFG_DCACHE_ENABLED
if (dcache_refill_request == `TRUE)
begin
// Start cache refill
d_adr_o <= first_address;
d_cyc_o <= `TRUE;
d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}};
d_stb_o <= `TRUE;
d_we_o <= `FALSE;
d_cti_o <= first_cycle_type;
//d_lock_o <= `TRUE;
end
else
`endif
if ( (store_q_m == `TRUE)
&& (stall_m == `FALSE)
`ifdef CFG_DRAM_ENABLED
&& (dram_select_m == `FALSE)
`endif
`ifdef CFG_IROM_ENABLED
&& (irom_select_m == `FALSE)
`endif
)
begin
// Data cache is write through, so all stores go to memory
d_dat_o <= store_data_m;
d_adr_o <=
`ifdef CFG_MMU_ENABLED
(dtlb_enable) ? physical_load_store_address_m :
`endif
load_store_address_m;
d_cyc_o <= `TRUE;
d_sel_o <= byte_enable_m;
d_stb_o <= `TRUE;
d_we_o <= `TRUE;
d_cti_o <= `LM32_CTYPE_END;
end
else if ( (load_q_m == `TRUE)
&& (wb_select_m == `TRUE)
&& (wb_load_complete == `FALSE)
// stall_m will be TRUE, because stall_wb_load will be TRUE
)
begin
// Read requested address
stall_wb_load <= `FALSE;
d_adr_o <=
`ifdef CFG_MMU_ENABLED
(dtlb_enable) ? physical_load_store_address_m :
`endif
load_store_address_m;
d_cyc_o <= `TRUE;
d_sel_o <= byte_enable_m;
d_stb_o <= `TRUE;
d_we_o <= `FALSE;
d_cti_o <= `LM32_CTYPE_END;
end
end
// Clear load/store complete flag when instruction leaves M stage
if (stall_m == `FALSE)
wb_load_complete <= `FALSE;
// When a Wishbone load first enters the M stage, we need to stall it
if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE))
stall_wb_load <= `TRUE;
// Clear stall request if load instruction is killed
if ((kill_m == `TRUE) || (exception_m == `TRUE))
stall_wb_load <= `FALSE;
end
end
// Pipeline registers
// X/M stage pipeline registers
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
sign_extend_m <= `FALSE;
size_m <= 2'b00;
byte_enable_m <= `FALSE;
store_data_m <= {`LM32_WORD_WIDTH{1'b0}};
`ifdef CFG_DCACHE_ENABLED
dcache_select_m <= `FALSE;
`endif
`ifdef CFG_DRAM_ENABLED
dram_select_m <= `FALSE;
`endif
`ifdef CFG_IROM_ENABLED
irom_select_m <= `FALSE;
`endif
wb_select_m <= `FALSE;
end
else
begin
if (stall_m == `FALSE)
begin
sign_extend_m <= sign_extend_x;
size_m <= size_x;
byte_enable_m <= byte_enable_x;
store_data_m <= store_data_x;
`ifdef CFG_DCACHE_ENABLED
dcache_select_m <= dcache_select_x;
`endif
`ifdef CFG_DRAM_ENABLED
dram_select_m <= dram_select_x;
`endif
`ifdef CFG_IROM_ENABLED
irom_select_m <= irom_select_x;
`endif
wb_select_m <= wb_select_x;
end
end
end
// M/W stage pipeline registers
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
size_w <= 2'b00;
data_w <= {`LM32_WORD_WIDTH{1'b0}};
sign_extend_w <= `FALSE;
end
else
begin
size_w <= size_m;
data_w <= data_m;
sign_extend_w <= sign_extend_m;
end
end
/////////////////////////////////////////////////////
// Behavioural Logic
/////////////////////////////////////////////////////
// synthesis translate_off
// Check for non-aligned loads or stores
always @(posedge clk_i)
begin
if (((load_q_m == `TRUE) || (store_q_m == `TRUE)) && (stall_m == `FALSE))
begin
if ((size_m === `LM32_SIZE_HWORD) && (load_store_address_m[0] !== 1'b0))
$display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
if ((size_m === `LM32_SIZE_WORD) && (load_store_address_m[1:0] !== 2'b00))
$display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
end
end
// synthesis translate_on
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:47:32 11/06/2013
// Design Name:
// Module Name: i2s_out
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// Recibe un clock de 50Mhz
//////////////////////////////////////////////////////////////////////////////////
module i2s_out(input clock, input reset, input[15:0] left_data,
input[15:0] right_data, output mclk, output lrck, output sclk, output reg sdin);
reg [3:0] data_pos;
initial
begin
data_pos <= 4'b0;
end
/** mclk es igual al clock . 50Mhz */
assign mclk = clock;
/** mclk/lrck = 64 entonces lrck se hace de 781250Hz */
lrck_divider lrck_gen(
.clock(clock),
.reset(reset),
.clock_out(lrck)
);
/** sclk/lrck = 32 y mclk/sclk = 2. Entonces sclk = 25Mhz*/
sclk_divider sclk_gen(
.clock(clock),
.reset(reset),
.clock_out(sclk)
);
/**
* flanco positivo de lrck = canal derecho
* flanco negativo de lrck = canal izquierdo
* los datos se mandan con sclk
**/
always @ (negedge sclk)
begin
if(lrck)
begin
if(data_pos == 4'b0)
begin
sdin <= left_data[data_pos];
end
else
begin
sdin <= right_data[data_pos];
end
end
else
begin
if(data_pos == 4'b0)
begin
sdin <= right_data[data_pos];
end
else
begin
sdin <= left_data[data_pos];
end
end
/** Siempre hay que cambiar la posicion */
data_pos <= data_pos - 1;
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: sa1_mult.v
// /___/ /\ Timestamp: Fri Oct 26 01:08:37 2018
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog D:/prj/sd2snes/verilog/sd2snes_sa1/ipcore_dir/tmp/_cg/sa1_mult.ngc D:/prj/sd2snes/verilog/sd2snes_sa1/ipcore_dir/tmp/_cg/sa1_mult.v
// Device : 3s400pq208-4
// Input file : D:/prj/sd2snes/verilog/sd2snes_sa1/ipcore_dir/tmp/_cg/sa1_mult.ngc
// Output file : D:/prj/sd2snes/verilog/sd2snes_sa1/ipcore_dir/tmp/_cg/sa1_mult.v
// # of Modules : 1
// Design Name : sa1_mult
// Xilinx : E:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module sa1_mult (
clk, p, a, b
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
output [31 : 0] p;
input [15 : 0] a;
input [15 : 0] b;
// synthesis translate_off
wire \blk00000001/sig00000041 ;
wire \blk00000001/sig00000040 ;
wire \blk00000001/sig0000003f ;
wire \blk00000001/sig0000003e ;
wire \blk00000001/sig0000003d ;
wire \blk00000001/sig0000003c ;
wire \blk00000001/sig0000003b ;
wire \blk00000001/sig0000003a ;
wire \blk00000001/sig00000039 ;
wire \blk00000001/sig00000038 ;
wire \blk00000001/sig00000037 ;
wire \blk00000001/sig00000036 ;
wire \blk00000001/sig00000035 ;
wire \blk00000001/sig00000034 ;
wire \blk00000001/sig00000033 ;
wire \blk00000001/sig00000032 ;
wire \blk00000001/sig00000031 ;
wire \blk00000001/sig00000030 ;
wire \blk00000001/sig0000002f ;
wire \blk00000001/sig0000002e ;
wire \blk00000001/sig0000002d ;
wire \blk00000001/sig0000002c ;
wire \blk00000001/sig0000002b ;
wire \blk00000001/sig0000002a ;
wire \blk00000001/sig00000029 ;
wire \blk00000001/sig00000028 ;
wire \blk00000001/sig00000027 ;
wire \blk00000001/sig00000026 ;
wire \blk00000001/sig00000025 ;
wire \blk00000001/sig00000024 ;
wire \blk00000001/sig00000023 ;
wire \blk00000001/sig00000022 ;
wire \NLW_blk00000001/blk00000022_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000022_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000022_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000022_P<31>_UNCONNECTED ;
MULT18X18 \blk00000001/blk00000022 (
.A({a[15], a[15], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
.B({b[15], b[15], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
.P({\blk00000001/sig0000003a , \NLW_blk00000001/blk00000022_P<34>_UNCONNECTED , \NLW_blk00000001/blk00000022_P<33>_UNCONNECTED ,
\NLW_blk00000001/blk00000022_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000022_P<31>_UNCONNECTED , \blk00000001/sig00000039 , \blk00000001/sig00000037
, \blk00000001/sig00000036 , \blk00000001/sig00000035 , \blk00000001/sig00000034 , \blk00000001/sig00000033 , \blk00000001/sig00000032 ,
\blk00000001/sig00000031 , \blk00000001/sig00000030 , \blk00000001/sig0000002f , \blk00000001/sig0000002e , \blk00000001/sig0000002c ,
\blk00000001/sig0000002b , \blk00000001/sig0000002a , \blk00000001/sig00000029 , \blk00000001/sig00000028 , \blk00000001/sig00000027 ,
\blk00000001/sig00000026 , \blk00000001/sig00000025 , \blk00000001/sig00000024 , \blk00000001/sig00000023 , \blk00000001/sig00000041 ,
\blk00000001/sig00000040 , \blk00000001/sig0000003f , \blk00000001/sig0000003e , \blk00000001/sig0000003d , \blk00000001/sig0000003c ,
\blk00000001/sig0000003b , \blk00000001/sig00000038 , \blk00000001/sig0000002d , \blk00000001/sig00000022 })
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000021 (
.C(clk),
.D(\blk00000001/sig0000003a ),
.Q(p[31])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000020 (
.C(clk),
.D(\blk00000001/sig00000039 ),
.Q(p[30])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001f (
.C(clk),
.D(\blk00000001/sig00000037 ),
.Q(p[29])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001e (
.C(clk),
.D(\blk00000001/sig00000036 ),
.Q(p[28])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001d (
.C(clk),
.D(\blk00000001/sig00000035 ),
.Q(p[27])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001c (
.C(clk),
.D(\blk00000001/sig00000034 ),
.Q(p[26])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001b (
.C(clk),
.D(\blk00000001/sig00000033 ),
.Q(p[25])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001a (
.C(clk),
.D(\blk00000001/sig00000032 ),
.Q(p[24])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000019 (
.C(clk),
.D(\blk00000001/sig00000031 ),
.Q(p[23])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000018 (
.C(clk),
.D(\blk00000001/sig00000030 ),
.Q(p[22])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000017 (
.C(clk),
.D(\blk00000001/sig0000002f ),
.Q(p[21])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000016 (
.C(clk),
.D(\blk00000001/sig0000002e ),
.Q(p[20])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000015 (
.C(clk),
.D(\blk00000001/sig0000002c ),
.Q(p[19])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000014 (
.C(clk),
.D(\blk00000001/sig0000002b ),
.Q(p[18])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000013 (
.C(clk),
.D(\blk00000001/sig0000002a ),
.Q(p[17])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000012 (
.C(clk),
.D(\blk00000001/sig00000029 ),
.Q(p[16])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000011 (
.C(clk),
.D(\blk00000001/sig00000028 ),
.Q(p[15])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000010 (
.C(clk),
.D(\blk00000001/sig00000027 ),
.Q(p[14])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000f (
.C(clk),
.D(\blk00000001/sig00000026 ),
.Q(p[13])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000e (
.C(clk),
.D(\blk00000001/sig00000025 ),
.Q(p[12])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000d (
.C(clk),
.D(\blk00000001/sig00000024 ),
.Q(p[11])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000c (
.C(clk),
.D(\blk00000001/sig00000023 ),
.Q(p[10])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000b (
.C(clk),
.D(\blk00000001/sig00000041 ),
.Q(p[9])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000a (
.C(clk),
.D(\blk00000001/sig00000040 ),
.Q(p[8])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000009 (
.C(clk),
.D(\blk00000001/sig0000003f ),
.Q(p[7])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000008 (
.C(clk),
.D(\blk00000001/sig0000003e ),
.Q(p[6])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000007 (
.C(clk),
.D(\blk00000001/sig0000003d ),
.Q(p[5])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000006 (
.C(clk),
.D(\blk00000001/sig0000003c ),
.Q(p[4])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000005 (
.C(clk),
.D(\blk00000001/sig0000003b ),
.Q(p[3])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000004 (
.C(clk),
.D(\blk00000001/sig00000038 ),
.Q(p[2])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000003 (
.C(clk),
.D(\blk00000001/sig0000002d ),
.Q(p[1])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000002 (
.C(clk),
.D(\blk00000001/sig00000022 ),
.Q(p[0])
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_PP_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire ci ;
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM , A, B, ci );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , pwrgood_pp0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , pwrgood_pp1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22AI_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__O22AI_BEHAVIORAL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__o22ai (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22AI_BEHAVIORAL_V |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module sp_best3 (
ap_clk,
ap_rst,
rank_ex_0_V_read,
rank_ex_1_V_read,
rank_ex_2_V_read,
rank_ex_3_V_read,
rank_ex_4_V_read,
rank_ex_5_V_read,
rank_ex_6_V_read,
rank_ex_7_V_read,
rank_ex_8_V_read,
rank_ex_9_V_read,
rank_ex_10_V_read,
rank_ex_11_V_read,
rank_ex_12_V_read,
rank_ex_13_V_read,
rank_ex_14_V_read,
rank_ex_15_V_read,
rank_ex_16_V_read,
rank_ex_17_V_read,
rank_ex_18_V_read,
rank_ex_19_V_read,
rank_ex_20_V_read,
rank_ex_21_V_read,
rank_ex_22_V_read,
rank_ex_23_V_read,
rank_ex_24_V_read,
rank_ex_25_V_read,
rank_ex_26_V_read,
rank_ex_27_V_read,
rank_ex_28_V_read,
rank_ex_29_V_read,
rank_ex_30_V_read,
rank_ex_31_V_read,
rank_ex_32_V_read,
rank_ex_33_V_read,
rank_ex_34_V_read,
rank_ex_35_V_read,
rank_ex_36_V_read,
rank_ex_37_V_read,
rank_ex_38_V_read,
rank_ex_39_V_read,
rank_ex_40_V_read,
rank_ex_41_V_read,
rank_ex_42_V_read,
rank_ex_43_V_read,
rank_ex_44_V_read,
rank_ex_45_V_read,
rank_ex_46_V_read,
rank_ex_47_V_read,
rank_ex_48_V_read,
rank_ex_49_V_read,
rank_ex_50_V_read,
rank_ex_51_V_read,
rank_ex_52_V_read,
rank_ex_53_V_read,
rank_ex_54_V_read,
rank_ex_55_V_read,
rank_ex_56_V_read,
rank_ex_57_V_read,
rank_ex_58_V_read,
rank_ex_59_V_read,
rank_ex_60_V_read,
rank_ex_61_V_read,
rank_ex_62_V_read,
rank_ex_63_V_read,
rank_ex_64_V_read,
rank_ex_65_V_read,
rank_ex_66_V_read,
rank_ex_67_V_read,
rank_ex_68_V_read,
rank_ex_69_V_read,
rank_ex_70_V_read,
rank_ex_71_V_read,
rank_ex_72_V_read,
rank_ex_73_V_read,
rank_ex_74_V_read,
rank_ex_75_V_read,
rank_ex_76_V_read,
rank_ex_77_V_read,
rank_ex_78_V_read,
rank_ex_79_V_read,
rank_ex_80_V_read,
rank_ex_81_V_read,
rank_ex_82_V_read,
rank_ex_83_V_read,
rank_ex_84_V_read,
rank_ex_85_V_read,
rank_ex_86_V_read,
rank_ex_87_V_read,
rank_ex_88_V_read,
rank_ex_89_V_read,
rank_ex_90_V_read,
rank_ex_91_V_read,
rank_ex_92_V_read,
rank_ex_93_V_read,
rank_ex_94_V_read,
rank_ex_95_V_read,
rank_ex_96_V_read,
rank_ex_97_V_read,
rank_ex_98_V_read,
rank_ex_99_V_read,
rank_ex_100_V_read,
rank_ex_101_V_read,
rank_ex_102_V_read,
rank_ex_103_V_read,
rank_ex_104_V_read,
rank_ex_105_V_read,
rank_ex_106_V_read,
rank_ex_107_V_read,
rank_ex_108_V_read,
rank_ex_109_V_read,
rank_ex_110_V_read,
rank_ex_111_V_read,
rank_ex_112_V_read,
rank_ex_113_V_read,
rank_ex_114_V_read,
rank_ex_115_V_read,
rank_ex_116_V_read,
rank_ex_117_V_read,
rank_ex_118_V_read,
rank_ex_119_V_read,
rank_ex_120_V_read,
rank_ex_121_V_read,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3,
ap_return_4,
ap_return_5
);
parameter ap_const_lv3_0 = 3'b000;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv3_1 = 3'b1;
parameter ap_const_lv2_1 = 2'b1;
parameter ap_const_lv3_2 = 3'b10;
parameter ap_const_lv2_2 = 2'b10;
parameter ap_const_lv3_3 = 3'b11;
parameter ap_const_lv2_3 = 2'b11;
parameter ap_const_lv3_7 = 3'b111;
parameter ap_const_lv3_4 = 3'b100;
parameter ap_const_lv3_5 = 3'b101;
parameter ap_const_lv3_6 = 3'b110;
parameter ap_const_lv4_4 = 4'b100;
parameter ap_const_lv4_5 = 4'b101;
parameter ap_const_lv4_6 = 4'b110;
parameter ap_const_lv4_7 = 4'b111;
parameter ap_const_lv4_F = 4'b1111;
parameter ap_const_lv4_B = 4'b1011;
parameter ap_const_lv4_8 = 4'b1000;
parameter ap_const_lv4_9 = 4'b1001;
parameter ap_const_lv4_A = 4'b1010;
parameter ap_const_lv5_8 = 5'b1000;
parameter ap_const_lv5_9 = 5'b1001;
parameter ap_const_lv5_A = 5'b1010;
parameter ap_const_lv5_B = 5'b1011;
parameter ap_const_lv5_1F = 5'b11111;
parameter ap_const_lv5_C = 5'b1100;
parameter ap_const_lv5_D = 5'b1101;
parameter ap_const_lv5_E = 5'b1110;
parameter ap_const_lv5_F = 5'b1111;
parameter ap_const_lv5_13 = 5'b10011;
parameter ap_const_lv5_10 = 5'b10000;
parameter ap_const_lv5_11 = 5'b10001;
parameter ap_const_lv5_12 = 5'b10010;
parameter ap_const_lv6_0 = 6'b000000;
parameter ap_const_lv5_0 = 5'b00000;
parameter ap_const_lv6_1 = 6'b1;
parameter ap_const_lv5_1 = 5'b1;
parameter ap_const_lv6_2 = 6'b10;
parameter ap_const_lv5_2 = 5'b10;
parameter ap_const_lv6_3 = 6'b11;
parameter ap_const_lv5_3 = 5'b11;
parameter ap_const_lv6_4 = 6'b100;
parameter ap_const_lv5_4 = 5'b100;
parameter ap_const_lv6_5 = 6'b101;
parameter ap_const_lv5_5 = 5'b101;
parameter ap_const_lv6_6 = 6'b110;
parameter ap_const_lv5_6 = 5'b110;
parameter ap_const_lv6_7 = 6'b111;
parameter ap_const_lv5_7 = 5'b111;
parameter ap_const_lv6_8 = 6'b1000;
parameter ap_const_lv6_9 = 6'b1001;
parameter ap_const_lv6_A = 6'b1010;
parameter ap_const_lv6_B = 6'b1011;
parameter ap_const_lv6_C = 6'b1100;
parameter ap_const_lv6_D = 6'b1101;
parameter ap_const_lv6_E = 6'b1110;
parameter ap_const_lv6_F = 6'b1111;
parameter ap_const_lv6_10 = 6'b10000;
parameter ap_const_lv6_11 = 6'b10001;
parameter ap_const_lv6_12 = 6'b10010;
parameter ap_const_lv6_13 = 6'b10011;
parameter ap_const_lv6_14 = 6'b10100;
parameter ap_const_lv5_14 = 5'b10100;
parameter ap_const_lv6_15 = 6'b10101;
parameter ap_const_lv5_15 = 5'b10101;
parameter ap_const_lv6_16 = 6'b10110;
parameter ap_const_lv5_16 = 5'b10110;
parameter ap_const_lv6_17 = 6'b10111;
parameter ap_const_lv5_17 = 5'b10111;
parameter ap_const_lv6_18 = 6'b11000;
parameter ap_const_lv5_18 = 5'b11000;
parameter ap_const_lv6_19 = 6'b11001;
parameter ap_const_lv5_19 = 5'b11001;
parameter ap_const_lv6_1A = 6'b11010;
parameter ap_const_lv5_1A = 5'b11010;
parameter ap_const_lv6_1B = 6'b11011;
parameter ap_const_lv5_1B = 5'b11011;
parameter ap_const_lv6_1C = 6'b11100;
parameter ap_const_lv5_1C = 5'b11100;
parameter ap_const_lv6_1D = 6'b11101;
parameter ap_const_lv5_1D = 5'b11101;
parameter ap_const_lv6_1E = 6'b11110;
parameter ap_const_lv5_1E = 5'b11110;
parameter ap_const_lv6_1F = 6'b11111;
parameter ap_const_lv6_3F = 6'b111111;
parameter ap_const_lv6_23 = 6'b100011;
parameter ap_const_lv6_20 = 6'b100000;
parameter ap_const_lv6_21 = 6'b100001;
parameter ap_const_lv6_22 = 6'b100010;
parameter ap_const_lv6_24 = 6'b100100;
parameter ap_const_lv6_25 = 6'b100101;
parameter ap_const_lv6_26 = 6'b100110;
parameter ap_const_lv6_27 = 6'b100111;
parameter ap_const_lv6_28 = 6'b101000;
parameter ap_const_lv6_29 = 6'b101001;
parameter ap_const_lv6_2A = 6'b101010;
parameter ap_const_lv6_2B = 6'b101011;
parameter ap_const_lv6_2C = 6'b101100;
parameter ap_const_lv6_2D = 6'b101101;
parameter ap_const_lv6_2E = 6'b101110;
parameter ap_const_lv6_2F = 6'b101111;
parameter ap_const_lv6_30 = 6'b110000;
parameter ap_const_lv6_31 = 6'b110001;
parameter ap_const_lv6_32 = 6'b110010;
parameter ap_const_lv6_33 = 6'b110011;
parameter ap_const_lv6_34 = 6'b110100;
parameter ap_const_lv6_35 = 6'b110101;
parameter ap_const_lv6_36 = 6'b110110;
parameter ap_const_lv6_37 = 6'b110111;
parameter ap_const_lv6_38 = 6'b111000;
parameter ap_const_lv6_39 = 6'b111001;
parameter ap_const_lv6_3A = 6'b111010;
parameter ap_const_lv6_3B = 6'b111011;
parameter ap_const_lv6_3C = 6'b111100;
parameter ap_const_lv6_3D = 6'b111101;
parameter ap_const_lv6_3E = 6'b111110;
parameter ap_const_lv7_2 = 7'b10;
parameter ap_const_lv7_4 = 7'b100;
parameter ap_const_lv7_6 = 7'b110;
parameter ap_const_lv7_8 = 7'b1000;
parameter ap_const_lv7_A = 7'b1010;
parameter ap_const_lv7_C = 7'b1100;
parameter ap_const_lv7_E = 7'b1110;
parameter ap_const_lv7_10 = 7'b10000;
parameter ap_const_lv7_12 = 7'b10010;
parameter ap_const_lv7_14 = 7'b10100;
parameter ap_const_lv7_16 = 7'b10110;
parameter ap_const_lv7_18 = 7'b11000;
parameter ap_const_lv7_1A = 7'b11010;
parameter ap_const_lv7_1C = 7'b11100;
parameter ap_const_lv7_1E = 7'b11110;
parameter ap_const_lv7_20 = 7'b100000;
parameter ap_const_lv7_22 = 7'b100010;
parameter ap_const_lv7_24 = 7'b100100;
parameter ap_const_lv7_26 = 7'b100110;
parameter ap_const_lv7_28 = 7'b101000;
parameter ap_const_lv7_2A = 7'b101010;
parameter ap_const_lv7_2C = 7'b101100;
parameter ap_const_lv7_2E = 7'b101110;
parameter ap_const_lv7_30 = 7'b110000;
parameter ap_const_lv7_32 = 7'b110010;
parameter ap_const_lv7_34 = 7'b110100;
parameter ap_const_lv7_36 = 7'b110110;
parameter ap_const_lv7_38 = 7'b111000;
parameter ap_const_lv7_3A = 7'b111010;
parameter ap_const_lv7_3C = 7'b111100;
parameter ap_const_lv7_3E = 7'b111110;
parameter ap_const_lv7_40 = 7'b1000000;
parameter ap_const_lv7_42 = 7'b1000010;
parameter ap_const_lv7_44 = 7'b1000100;
parameter ap_const_lv7_46 = 7'b1000110;
parameter ap_const_lv7_48 = 7'b1001000;
parameter ap_const_lv7_4A = 7'b1001010;
parameter ap_const_lv7_4C = 7'b1001100;
parameter ap_const_lv7_4E = 7'b1001110;
parameter ap_const_lv7_50 = 7'b1010000;
parameter ap_const_lv7_52 = 7'b1010010;
parameter ap_const_lv7_54 = 7'b1010100;
parameter ap_const_lv7_56 = 7'b1010110;
parameter ap_const_lv7_58 = 7'b1011000;
parameter ap_const_lv7_5A = 7'b1011010;
parameter ap_const_lv7_5C = 7'b1011100;
parameter ap_const_lv7_5E = 7'b1011110;
parameter ap_const_lv7_60 = 7'b1100000;
parameter ap_const_lv7_62 = 7'b1100010;
parameter ap_const_lv7_64 = 7'b1100100;
parameter ap_const_lv7_66 = 7'b1100110;
parameter ap_const_lv7_68 = 7'b1101000;
parameter ap_const_lv7_6A = 7'b1101010;
parameter ap_const_lv7_6C = 7'b1101100;
parameter ap_const_lv7_6E = 7'b1101110;
parameter ap_const_lv7_70 = 7'b1110000;
parameter ap_const_lv7_72 = 7'b1110010;
parameter ap_const_lv7_74 = 7'b1110100;
parameter ap_const_lv7_76 = 7'b1110110;
parameter ap_const_lv7_0 = 7'b0000000;
parameter ap_const_lv7_1 = 7'b1;
parameter ap_const_lv7_7F = 7'b1111111;
input ap_clk;
input ap_rst;
input [5:0] rank_ex_0_V_read;
input [5:0] rank_ex_1_V_read;
input [5:0] rank_ex_2_V_read;
input [5:0] rank_ex_3_V_read;
input [5:0] rank_ex_4_V_read;
input [5:0] rank_ex_5_V_read;
input [5:0] rank_ex_6_V_read;
input [5:0] rank_ex_7_V_read;
input [5:0] rank_ex_8_V_read;
input [5:0] rank_ex_9_V_read;
input [5:0] rank_ex_10_V_read;
input [5:0] rank_ex_11_V_read;
input [5:0] rank_ex_12_V_read;
input [5:0] rank_ex_13_V_read;
input [5:0] rank_ex_14_V_read;
input [5:0] rank_ex_15_V_read;
input [5:0] rank_ex_16_V_read;
input [5:0] rank_ex_17_V_read;
input [5:0] rank_ex_18_V_read;
input [5:0] rank_ex_19_V_read;
input [5:0] rank_ex_20_V_read;
input [5:0] rank_ex_21_V_read;
input [5:0] rank_ex_22_V_read;
input [5:0] rank_ex_23_V_read;
input [5:0] rank_ex_24_V_read;
input [5:0] rank_ex_25_V_read;
input [5:0] rank_ex_26_V_read;
input [5:0] rank_ex_27_V_read;
input [5:0] rank_ex_28_V_read;
input [5:0] rank_ex_29_V_read;
input [5:0] rank_ex_30_V_read;
input [5:0] rank_ex_31_V_read;
input [5:0] rank_ex_32_V_read;
input [5:0] rank_ex_33_V_read;
input [5:0] rank_ex_34_V_read;
input [5:0] rank_ex_35_V_read;
input [5:0] rank_ex_36_V_read;
input [5:0] rank_ex_37_V_read;
input [5:0] rank_ex_38_V_read;
input [5:0] rank_ex_39_V_read;
input [5:0] rank_ex_40_V_read;
input [5:0] rank_ex_41_V_read;
input [5:0] rank_ex_42_V_read;
input [5:0] rank_ex_43_V_read;
input [5:0] rank_ex_44_V_read;
input [5:0] rank_ex_45_V_read;
input [5:0] rank_ex_46_V_read;
input [5:0] rank_ex_47_V_read;
input [5:0] rank_ex_48_V_read;
input [5:0] rank_ex_49_V_read;
input [5:0] rank_ex_50_V_read;
input [5:0] rank_ex_51_V_read;
input [5:0] rank_ex_52_V_read;
input [5:0] rank_ex_53_V_read;
input [5:0] rank_ex_54_V_read;
input [5:0] rank_ex_55_V_read;
input [5:0] rank_ex_56_V_read;
input [5:0] rank_ex_57_V_read;
input [5:0] rank_ex_58_V_read;
input [5:0] rank_ex_59_V_read;
input [5:0] rank_ex_60_V_read;
input [5:0] rank_ex_61_V_read;
input [5:0] rank_ex_62_V_read;
input [5:0] rank_ex_63_V_read;
input [5:0] rank_ex_64_V_read;
input [5:0] rank_ex_65_V_read;
input [5:0] rank_ex_66_V_read;
input [5:0] rank_ex_67_V_read;
input [5:0] rank_ex_68_V_read;
input [5:0] rank_ex_69_V_read;
input [5:0] rank_ex_70_V_read;
input [5:0] rank_ex_71_V_read;
input [5:0] rank_ex_72_V_read;
input [5:0] rank_ex_73_V_read;
input [5:0] rank_ex_74_V_read;
input [5:0] rank_ex_75_V_read;
input [5:0] rank_ex_76_V_read;
input [5:0] rank_ex_77_V_read;
input [5:0] rank_ex_78_V_read;
input [5:0] rank_ex_79_V_read;
input [5:0] rank_ex_80_V_read;
input [5:0] rank_ex_81_V_read;
input [5:0] rank_ex_82_V_read;
input [5:0] rank_ex_83_V_read;
input [5:0] rank_ex_84_V_read;
input [5:0] rank_ex_85_V_read;
input [5:0] rank_ex_86_V_read;
input [5:0] rank_ex_87_V_read;
input [5:0] rank_ex_88_V_read;
input [5:0] rank_ex_89_V_read;
input [5:0] rank_ex_90_V_read;
input [5:0] rank_ex_91_V_read;
input [5:0] rank_ex_92_V_read;
input [5:0] rank_ex_93_V_read;
input [5:0] rank_ex_94_V_read;
input [5:0] rank_ex_95_V_read;
input [5:0] rank_ex_96_V_read;
input [5:0] rank_ex_97_V_read;
input [5:0] rank_ex_98_V_read;
input [5:0] rank_ex_99_V_read;
input [5:0] rank_ex_100_V_read;
input [5:0] rank_ex_101_V_read;
input [5:0] rank_ex_102_V_read;
input [5:0] rank_ex_103_V_read;
input [5:0] rank_ex_104_V_read;
input [5:0] rank_ex_105_V_read;
input [5:0] rank_ex_106_V_read;
input [5:0] rank_ex_107_V_read;
input [5:0] rank_ex_108_V_read;
input [5:0] rank_ex_109_V_read;
input [5:0] rank_ex_110_V_read;
input [5:0] rank_ex_111_V_read;
input [5:0] rank_ex_112_V_read;
input [5:0] rank_ex_113_V_read;
input [5:0] rank_ex_114_V_read;
input [5:0] rank_ex_115_V_read;
input [5:0] rank_ex_116_V_read;
input [5:0] rank_ex_117_V_read;
input [5:0] rank_ex_118_V_read;
input [5:0] rank_ex_119_V_read;
input [5:0] rank_ex_120_V_read;
input [5:0] rank_ex_121_V_read;
output [5:0] ap_return_0;
output [5:0] ap_return_1;
output [5:0] ap_return_2;
output [6:0] ap_return_3;
output [6:0] ap_return_4;
output [6:0] ap_return_5;
reg [5:0] rank_ex_120_V_read_1_reg_19603;
reg [5:0] rank_ex_118_V_read_1_reg_19609;
reg [5:0] rank_ex_116_V_read_1_reg_19615;
reg [5:0] rank_ex_114_V_read_1_reg_19621;
reg [5:0] rank_ex_112_V_read_1_reg_19627;
reg [5:0] rank_ex_110_V_read_1_reg_19633;
reg [5:0] rank_ex_108_V_read_1_reg_19639;
reg [5:0] rank_ex_106_V_read_1_reg_19645;
reg [5:0] rank_ex_104_V_read_1_reg_19651;
reg [5:0] rank_ex_102_V_read_1_reg_19657;
reg [5:0] rank_ex_100_V_read_1_reg_19663;
reg [5:0] rank_ex_98_V_read_1_reg_19669;
reg [5:0] rank_ex_96_V_read_1_reg_19675;
reg [5:0] rank_ex_94_V_read_1_reg_19681;
reg [5:0] rank_ex_92_V_read_1_reg_19687;
reg [5:0] rank_ex_90_V_read_1_reg_19693;
reg [5:0] rank_ex_88_V_read_1_reg_19699;
reg [5:0] rank_ex_86_V_read_1_reg_19705;
reg [5:0] rank_ex_84_V_read_1_reg_19711;
reg [5:0] rank_ex_82_V_read_1_reg_19717;
reg [5:0] rank_ex_80_V_read_1_reg_19723;
reg [5:0] rank_ex_78_V_read_1_reg_19729;
reg [5:0] rank_ex_76_V_read_1_reg_19735;
reg [5:0] rank_ex_74_V_read_1_reg_19741;
reg [5:0] rank_ex_72_V_read_1_reg_19747;
reg [5:0] rank_ex_70_V_read_1_reg_19753;
reg [5:0] rank_ex_68_V_read_1_reg_19759;
reg [5:0] rank_ex_66_V_read_1_reg_19765;
reg [5:0] rank_ex_64_V_read_1_reg_19771;
reg [5:0] rank_ex_62_V_read_1_reg_19777;
reg [5:0] rank_ex_60_V_read_1_reg_19783;
reg [5:0] rank_ex_58_V_read_1_reg_19789;
reg [5:0] rank_ex_56_V_read_1_reg_19795;
reg [5:0] rank_ex_54_V_read_1_reg_19801;
reg [5:0] rank_ex_52_V_read_1_reg_19807;
reg [5:0] rank_ex_50_V_read_1_reg_19813;
reg [5:0] rank_ex_48_V_read_1_reg_19819;
reg [5:0] rank_ex_46_V_read_1_reg_19825;
reg [5:0] rank_ex_44_V_read_1_reg_19831;
reg [5:0] rank_ex_42_V_read_1_reg_19837;
reg [5:0] rank_ex_40_V_read_1_reg_19843;
reg [5:0] rank_ex_38_V_read_1_reg_19849;
reg [5:0] rank_ex_36_V_read_1_reg_19855;
reg [5:0] rank_ex_34_V_read_1_reg_19861;
reg [5:0] rank_ex_32_V_read_1_reg_19867;
reg [5:0] rank_ex_30_V_read_1_reg_19873;
reg [5:0] rank_ex_28_V_read_1_reg_19879;
reg [5:0] rank_ex_26_V_read_1_reg_19885;
reg [5:0] rank_ex_24_V_read_1_reg_19891;
reg [5:0] rank_ex_22_V_read_1_reg_19897;
reg [5:0] rank_ex_20_V_read_1_reg_19903;
reg [5:0] rank_ex_18_V_read_1_reg_19909;
reg [5:0] rank_ex_16_V_read_1_reg_19915;
reg [5:0] rank_ex_14_V_read_1_reg_19921;
reg [5:0] rank_ex_12_V_read_1_reg_19927;
reg [5:0] rank_ex_10_V_read_1_reg_19933;
reg [5:0] rank_ex_8_V_read_1_reg_19939;
reg [5:0] rank_ex_6_V_read_1_reg_19945;
reg [5:0] rank_ex_4_V_read_1_reg_19951;
reg [5:0] rank_ex_2_V_read_1_reg_19957;
reg [5:0] rank_ex_0_V_read_1_reg_19963;
reg [5:0] winner_0_V_write_assign_reg_19969;
reg [6:0] winid_0_V_write_assign_reg_19974;
reg [5:0] win_l0_0_V_reg_19979;
reg [5:0] win_l0_1_V_reg_20046;
reg [5:0] win_l0_2_V_reg_20113;
reg [5:0] win_l0_3_V_reg_20180;
reg [5:0] win_l0_4_V_reg_20247;
reg [5:0] win_l0_5_V_reg_20315;
reg [5:0] win_l0_6_V_reg_20383;
reg [5:0] win_l0_7_V_reg_20451;
reg [5:0] win_l0_8_V_reg_20519;
reg [5:0] win_l0_9_V_reg_20587;
reg [5:0] win_l0_10_V_reg_20655;
reg [5:0] win_l0_11_V_reg_20723;
reg [5:0] win_l0_12_V_reg_20791;
reg [5:0] win_l0_13_V_reg_20859;
reg [5:0] win_l0_14_V_reg_20927;
reg [5:0] win_l0_15_V_reg_20995;
reg [5:0] win_l0_16_V_reg_21063;
reg [5:0] win_l0_17_V_reg_21130;
reg [5:0] win_l0_18_V_reg_21197;
reg [5:0] win_l0_19_V_reg_21264;
reg [5:0] win_l0_20_V_reg_21331;
reg [5:0] win_l0_21_V_reg_21398;
reg [5:0] win_l0_22_V_reg_21465;
reg [5:0] win_l0_23_V_reg_21532;
reg [5:0] win_l0_24_V_reg_21599;
reg [5:0] win_l0_25_V_reg_21666;
reg [5:0] win_l0_26_V_reg_21733;
reg [5:0] win_l0_27_V_reg_21800;
reg [5:0] win_l0_28_V_reg_21867;
reg [5:0] win_l0_29_V_reg_21934;
reg [5:0] win_l0_30_V_reg_22001;
reg [5:0] win_l0_31_V_reg_22068;
reg [5:0] win_l0_32_V_reg_22135;
reg [5:0] win_l0_33_V_reg_22202;
reg [5:0] win_l0_34_V_reg_22269;
reg [5:0] win_l0_35_V_reg_22336;
reg [5:0] win_l0_36_V_reg_22403;
reg [5:0] win_l0_37_V_reg_22470;
reg [5:0] win_l0_38_V_reg_22537;
reg [5:0] win_l0_39_V_reg_22604;
reg [5:0] win_l0_40_V_reg_22671;
reg [5:0] win_l0_41_V_reg_22738;
reg [5:0] win_l0_42_V_reg_22805;
reg [5:0] win_l0_43_V_reg_22872;
reg [5:0] win_l0_44_V_reg_22939;
reg [5:0] win_l0_45_V_reg_23006;
reg [5:0] win_l0_46_V_reg_23073;
reg [5:0] win_l0_47_V_reg_23140;
reg [5:0] win_l0_48_V_reg_23207;
reg [5:0] win_l0_49_V_reg_23274;
reg [5:0] win_l0_50_V_reg_23341;
reg [5:0] win_l0_51_V_reg_23408;
reg [5:0] win_l0_52_V_reg_23475;
reg [5:0] win_l0_53_V_reg_23542;
reg [5:0] win_l0_54_V_reg_23609;
reg [5:0] win_l0_55_V_reg_23676;
reg [5:0] win_l0_56_V_reg_23743;
reg [5:0] win_l0_57_V_reg_23810;
reg [5:0] win_l0_58_V_reg_23877;
reg [5:0] win_l0_59_V_reg_23944;
reg [5:0] win_l0_60_V_reg_24011;
wire [5:0] win_l1_V_load_fu_15300_p3;
reg [5:0] win_l1_V_load_reg_24078;
wire [0:0] sel_tmp2057_demorgan_fu_16412_p2;
reg [0:0] sel_tmp2057_demorgan_reg_24343;
wire [0:0] sel_tmp49_fu_16438_p2;
reg [0:0] sel_tmp49_reg_24348;
wire [0:0] sel_tmp55_fu_16488_p2;
reg [0:0] sel_tmp55_reg_24353;
wire [5:0] win_l2_V_load_4_fu_16494_p3;
reg [5:0] win_l2_V_load_4_reg_24359;
wire [0:0] sel_tmp2101_demorgan_fu_16568_p2;
reg [0:0] sel_tmp2101_demorgan_reg_24369;
wire [0:0] sel_tmp58_fu_16594_p2;
reg [0:0] sel_tmp58_reg_24374;
wire [0:0] sel_tmp64_fu_16644_p2;
reg [0:0] sel_tmp64_reg_24379;
wire [5:0] win_l2_V_load_5_fu_16650_p3;
reg [5:0] win_l2_V_load_5_reg_24385;
wire [0:0] sel_tmp2145_demorgan_fu_16724_p2;
reg [0:0] sel_tmp2145_demorgan_reg_24395;
wire [0:0] sel_tmp67_fu_16750_p2;
reg [0:0] sel_tmp67_reg_24400;
wire [0:0] sel_tmp73_fu_16800_p2;
reg [0:0] sel_tmp73_reg_24405;
wire [5:0] temp_V_2_3_fu_16806_p3;
reg [5:0] temp_V_2_3_reg_24411;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_0;
wire [6:0] call_ret_sp_sort_fu_14608_ap_return_1;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_2;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_3;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_4;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_5;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_6;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_7;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_8;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_9;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_10;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_11;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_12;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_13;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_14;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_15;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_16;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_17;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_18;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_19;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_20;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_21;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_22;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_23;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_24;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_25;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_26;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_27;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_28;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_29;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_30;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_31;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_32;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_33;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_34;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_35;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_36;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_37;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_38;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_39;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_40;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_41;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_42;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_43;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_44;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_45;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_46;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_47;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_48;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_49;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_50;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_51;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_52;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_53;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_54;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_55;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_56;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_57;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_58;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_59;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_60;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_61;
wire [5:0] call_ret_sp_sort_fu_14608_ap_return_62;
wire [5:0] ap_reg_phiprechg_win_l1_V_load_1_reg_1354pp0_it0;
wire [0:0] tmp_294_4_fu_15554_p2;
wire [0:0] tmp_309_4_fu_15578_p2;
wire [0:0] tmp_318_4_fu_15602_p2;
wire [0:0] or_cond85_fu_15572_p2;
wire [0:0] or_cond86_fu_15596_p2;
wire [0:0] or_cond87_fu_15620_p2;
reg [5:0] win_l1_V_load_1_phi_fu_1357_p8;
wire [5:0] ap_reg_phiprechg_win_l1_V_load_4_1_reg_1367pp0_it0;
wire [0:0] tmp_294_5_fu_15626_p2;
wire [0:0] tmp_309_5_fu_15650_p2;
wire [0:0] tmp_318_5_fu_15674_p2;
wire [0:0] or_cond88_fu_15644_p2;
wire [0:0] or_cond89_fu_15668_p2;
wire [0:0] or_cond90_fu_15692_p2;
reg [5:0] win_l1_V_load_4_1_phi_fu_1370_p8;
wire [5:0] ap_reg_phiprechg_win_l1_V_load_5_1_reg_1380pp0_it0;
wire [0:0] tmp_294_6_fu_15698_p2;
wire [0:0] tmp_309_6_fu_15722_p2;
wire [0:0] tmp_318_6_fu_15746_p2;
wire [0:0] or_cond91_fu_15716_p2;
wire [0:0] or_cond92_fu_15740_p2;
wire [0:0] or_cond93_fu_15764_p2;
reg [5:0] win_l1_V_load_5_1_phi_fu_1383_p8;
wire [5:0] ap_reg_phiprechg_win_l1_V_load_6_1_reg_1393pp0_it0;
wire [0:0] tmp_294_7_fu_15770_p2;
wire [0:0] tmp_309_7_fu_15794_p2;
wire [0:0] tmp_318_7_fu_15818_p2;
wire [0:0] or_cond94_fu_15788_p2;
wire [0:0] or_cond95_fu_15812_p2;
wire [0:0] or_cond96_fu_15836_p2;
reg [5:0] win_l1_V_load_6_1_phi_fu_1396_p8;
wire [5:0] ap_reg_phiprechg_win_l1_V_load_2_reg_1406pp0_it0;
wire [0:0] tmp_294_8_fu_15842_p2;
wire [0:0] tmp_309_8_fu_15866_p2;
wire [0:0] tmp_318_8_fu_15890_p2;
wire [0:0] or_cond97_fu_15860_p2;
wire [0:0] or_cond98_fu_15884_p2;
wire [0:0] or_cond99_fu_15908_p2;
reg [5:0] win_l1_V_load_2_phi_fu_1409_p8;
wire [5:0] ap_reg_phiprechg_win_l1_V_load_4_2_reg_1419pp0_it0;
wire [0:0] tmp_294_9_fu_15914_p2;
wire [0:0] tmp_309_9_fu_15938_p2;
wire [0:0] tmp_318_9_fu_15962_p2;
wire [0:0] or_cond100_fu_15932_p2;
wire [0:0] or_cond101_fu_15956_p2;
wire [0:0] or_cond102_fu_15980_p2;
reg [5:0] win_l1_V_load_4_2_phi_fu_1422_p8;
wire [5:0] ap_reg_phiprechg_win_l1_V_load_5_2_reg_1432pp0_it0;
wire [0:0] tmp_294_s_fu_15986_p2;
wire [0:0] tmp_309_s_fu_16010_p2;
wire [0:0] tmp_318_s_fu_16034_p2;
wire [0:0] or_cond103_fu_16004_p2;
wire [0:0] or_cond104_fu_16028_p2;
wire [0:0] or_cond105_fu_16052_p2;
reg [5:0] win_l1_V_load_5_2_phi_fu_1435_p8;
wire [5:0] ap_reg_phiprechg_win_l1_V_load_6_2_reg_1445pp0_it0;
wire [0:0] tmp_294_10_fu_16058_p2;
wire [0:0] tmp_309_10_fu_16082_p2;
wire [0:0] tmp_318_10_fu_16106_p2;
wire [0:0] or_cond106_fu_16076_p2;
wire [0:0] or_cond107_fu_16100_p2;
wire [0:0] or_cond108_fu_16124_p2;
reg [5:0] win_l1_V_load_6_2_phi_fu_1448_p8;
wire [5:0] ap_reg_phiprechg_win_l1_V_load_3_reg_1458pp0_it0;
wire [0:0] tmp_294_11_fu_16130_p2;
wire [0:0] tmp_309_11_fu_16154_p2;
wire [0:0] tmp_318_11_fu_16178_p2;
wire [0:0] or_cond109_fu_16148_p2;
wire [0:0] or_cond110_fu_16172_p2;
wire [0:0] or_cond111_fu_16196_p2;
reg [5:0] win_l1_V_load_3_phi_fu_1461_p8;
wire [5:0] ap_reg_phiprechg_win_l1_V_load_4_3_reg_1471pp0_it0;
wire [0:0] tmp_294_12_fu_16202_p2;
wire [0:0] tmp_309_12_fu_16226_p2;
wire [0:0] tmp_318_12_fu_16250_p2;
wire [0:0] or_cond112_fu_16220_p2;
wire [0:0] or_cond113_fu_16244_p2;
wire [0:0] or_cond114_fu_16268_p2;
reg [5:0] win_l1_V_load_4_3_phi_fu_1474_p8;
wire [5:0] ap_reg_phiprechg_win_l1_V_load_5_3_reg_1484pp0_it0;
wire [0:0] tmp_294_13_fu_16274_p2;
wire [0:0] tmp_309_13_fu_16298_p2;
wire [0:0] tmp_318_13_fu_16322_p2;
wire [0:0] or_cond115_fu_16292_p2;
wire [0:0] or_cond116_fu_16316_p2;
wire [0:0] or_cond117_fu_16340_p2;
reg [5:0] win_l1_V_load_5_3_phi_fu_1487_p8;
wire [2:0] ap_reg_phiprechg_ranki_l1_0_V_reg_1497pp0_it0;
reg [2:0] ap_reg_phiprechg_ranki_l1_0_V_reg_1497pp0_it1;
wire [1:0] newSel13_fu_15330_p3;
wire [5:0] ap_reg_phiprechg_win_l1_V_load_4_reg_1522pp0_it0;
reg [5:0] ap_reg_phiprechg_win_l1_V_load_4_reg_1522pp0_it1;
wire [0:0] tmp_294_1_fu_15338_p2;
wire [0:0] tmp_309_1_fu_15362_p2;
wire [0:0] tmp_318_1_fu_15386_p2;
wire [0:0] or_cond61_fu_15356_p2;
wire [0:0] or_cond63_fu_15380_p2;
wire [0:0] or_cond65_fu_15404_p2;
wire [2:0] ap_reg_phiprechg_a_winid_V_s_reg_1535pp0_it0;
reg [2:0] ap_reg_phiprechg_a_winid_V_s_reg_1535pp0_it1;
wire [2:0] a_winid_V_s_phi_fu_1542_p8;
wire [3:0] ap_reg_phiprechg_ranki_l1_1_V_reg_1556pp0_it1;
reg [3:0] ranki_l1_1_V_phi_fu_1559_p10;
wire [5:0] ap_reg_phiprechg_win_l1_V_load_5_reg_1576pp0_it0;
reg [5:0] ap_reg_phiprechg_win_l1_V_load_5_reg_1576pp0_it1;
wire [0:0] tmp_294_2_fu_15410_p2;
wire [0:0] tmp_309_2_fu_15434_p2;
wire [0:0] tmp_318_2_fu_15458_p2;
wire [0:0] or_cond72_fu_15428_p2;
wire [0:0] or_cond75_fu_15452_p2;
wire [0:0] or_cond78_fu_15476_p2;
wire [3:0] ap_reg_phiprechg_a_winid_V_2_reg_1589pp0_it0;
reg [3:0] ap_reg_phiprechg_a_winid_V_2_reg_1589pp0_it1;
wire [3:0] a_winid_V_2_phi_fu_1596_p8;
wire [4:0] ap_reg_phiprechg_ranki_l1_2_V_reg_1610pp0_it1;
reg [4:0] ranki_l1_2_V_phi_fu_1613_p10;
wire [5:0] ap_reg_phiprechg_win_l1_V_load_6_reg_1630pp0_it0;
reg [5:0] ap_reg_phiprechg_win_l1_V_load_6_reg_1630pp0_it1;
wire [0:0] tmp_294_3_fu_15482_p2;
wire [0:0] tmp_309_3_fu_15506_p2;
wire [0:0] tmp_318_3_fu_15530_p2;
wire [0:0] or_cond79_fu_15500_p2;
wire [0:0] or_cond81_fu_15524_p2;
wire [0:0] or_cond83_fu_15548_p2;
wire [2:0] ap_reg_phiprechg_a_winid_V_3_reg_1643pp0_it0;
reg [2:0] ap_reg_phiprechg_a_winid_V_3_reg_1643pp0_it1;
wire [2:0] a_winid_V_3_phi_fu_1650_p8;
wire [4:0] ap_reg_phiprechg_ranki_l1_3_V_reg_1664pp0_it1;
reg [4:0] ranki_l1_3_V_phi_fu_1667_p10;
wire [4:0] ap_reg_phiprechg_a_winid_V_4_reg_1684pp0_it0;
reg [4:0] ap_reg_phiprechg_a_winid_V_4_reg_1684pp0_it1;
wire [4:0] a_winid_V_4_phi_fu_1691_p8;
wire [5:0] ap_reg_phiprechg_ranki_l1_4_V_reg_1705pp0_it1;
reg [5:0] ranki_l1_4_V_phi_fu_1708_p66;
wire [4:0] ap_reg_phiprechg_a_winid_V_5_reg_1809pp0_it0;
reg [4:0] ap_reg_phiprechg_a_winid_V_5_reg_1809pp0_it1;
wire [4:0] a_winid_V_5_phi_fu_1816_p8;
wire [5:0] ap_reg_phiprechg_ranki_l1_5_V_reg_1830pp0_it1;
reg [5:0] ranki_l1_5_V_phi_fu_1833_p66;
wire [3:0] ap_reg_phiprechg_a_winid_V_6_reg_1934pp0_it0;
reg [3:0] ap_reg_phiprechg_a_winid_V_6_reg_1934pp0_it1;
wire [5:0] ap_reg_phiprechg_ranki_l1_6_V_reg_1955pp0_it1;
wire signed [4:0] a_winid_V_6_cast_fu_16854_p1;
reg [5:0] ranki_l1_6_V_phi_fu_1958_p66;
wire [2:0] ap_reg_phiprechg_a_winid_V_7_reg_2059pp0_it0;
reg [2:0] ap_reg_phiprechg_a_winid_V_7_reg_2059pp0_it1;
wire [5:0] ap_reg_phiprechg_ranki_l1_7_V_reg_2080pp0_it1;
wire signed [4:0] a_winid_V_7_cast_fu_16862_p1;
reg [5:0] ranki_l1_7_V_phi_fu_2083_p66;
wire [5:0] ap_reg_phiprechg_a_winid_V_8_reg_2184pp0_it0;
reg [5:0] ap_reg_phiprechg_a_winid_V_8_reg_2184pp0_it1;
wire [5:0] a_winid_V_8_phi_fu_2191_p8;
wire [5:0] ap_reg_phiprechg_ranki_l1_8_V_reg_2205pp0_it1;
reg [5:0] ranki_l1_8_V_phi_fu_2208_p128;
wire [5:0] ap_reg_phiprechg_a_winid_V_9_reg_2402pp0_it0;
reg [5:0] ap_reg_phiprechg_a_winid_V_9_reg_2402pp0_it1;
wire [5:0] a_winid_V_9_phi_fu_2409_p8;
wire [5:0] ap_reg_phiprechg_ranki_l1_9_V_reg_2423pp0_it1;
reg [5:0] ranki_l1_9_V_phi_fu_2426_p128;
wire [5:0] ap_reg_phiprechg_a_winid_V_10_reg_2620pp0_it0;
reg [5:0] ap_reg_phiprechg_a_winid_V_10_reg_2620pp0_it1;
wire [5:0] a_winid_V_10_phi_fu_2627_p8;
wire [5:0] ap_reg_phiprechg_ranki_l1_10_V_reg_2641pp0_it1;
reg [5:0] ranki_l1_10_V_phi_fu_2644_p128;
wire [5:0] ap_reg_phiprechg_a_winid_V_11_reg_2838pp0_it0;
reg [5:0] ap_reg_phiprechg_a_winid_V_11_reg_2838pp0_it1;
wire [5:0] a_winid_V_11_phi_fu_2845_p8;
wire [5:0] ap_reg_phiprechg_ranki_l1_11_V_reg_2859pp0_it1;
reg [5:0] ranki_l1_11_V_phi_fu_2862_p128;
wire [4:0] ap_reg_phiprechg_a_winid_V_12_reg_3056pp0_it0;
reg [4:0] ap_reg_phiprechg_a_winid_V_12_reg_3056pp0_it1;
wire [5:0] ap_reg_phiprechg_ranki_l1_12_V_reg_3077pp0_it1;
wire signed [5:0] a_winid_V_12_cast_fu_16886_p1;
reg [5:0] ranki_l1_12_V_phi_fu_3080_p128;
wire [4:0] ap_reg_phiprechg_a_winid_V_13_reg_3274pp0_it0;
reg [4:0] ap_reg_phiprechg_a_winid_V_13_reg_3274pp0_it1;
wire [5:0] ap_reg_phiprechg_ranki_l1_13_V_reg_3295pp0_it1;
wire signed [5:0] a_winid_V_13_cast_fu_16894_p1;
reg [5:0] ranki_l1_13_V_phi_fu_3298_p128;
wire [3:0] ap_reg_phiprechg_a_winid_V_14_reg_3492pp0_it0;
reg [3:0] ap_reg_phiprechg_a_winid_V_14_reg_3492pp0_it1;
wire [5:0] ap_reg_phiprechg_ranki_l1_14_V_reg_3513pp0_it1;
wire signed [5:0] a_winid_V_14_cast_fu_16902_p1;
reg [5:0] ranki_l1_14_V_phi_fu_3516_p128;
wire [5:0] ap_reg_phiprechg_win_l2_V_load_reg_3710pp0_it1;
wire [0:0] tmp_217_fu_16910_p2;
wire [0:0] tmp_220_fu_16931_p2;
wire [0:0] tmp_223_fu_16954_p2;
wire [0:0] or_cond_85_fu_16925_p2;
wire [0:0] or_cond50_fu_16948_p2;
wire [0:0] or_cond51_fu_16971_p2;
reg [5:0] win_l2_V_load_phi_fu_3713_p8;
wire [1:0] ap_reg_phiprechg_a_winid_1_V_reg_3726pp0_it1;
reg [1:0] a_winid_1_V_phi_fu_3729_p8;
wire [5:0] ap_reg_phiprechg_sorter_a_V_load29_phi_reg_3743pp0_it1;
wire [6:0] tmp_2772_fu_17361_p2;
reg [5:0] sorter_a_V_load29_phi_phi_fu_3746_p122;
wire [6:0] p_086_0_i1_fu_17394_p3;
wire [6:0] ap_reg_phiprechg_winid_1_V_write_assign_reg_3870pp0_it1;
wire [0:0] tmp_23_fu_17367_p2;
reg [6:0] winid_1_V_write_assign_phi_fu_3873_p4;
wire [6:0] p_tmp_s_fu_17385_p3;
wire [5:0] ap_reg_phiprechg_win_l0_V_s_reg_3879pp0_it1;
wire [5:0] tmp_2771_fu_17357_p1;
reg [5:0] win_l0_V_s_phi_fu_3882_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_1_reg_4013pp0_it1;
reg [5:0] win_l0_V_1_phi_fu_4016_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_58_reg_4147pp0_it1;
reg [5:0] win_l0_V_58_phi_fu_4150_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_57_reg_4281pp0_it1;
reg [5:0] win_l0_V_57_phi_fu_4284_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_56_reg_4415pp0_it1;
reg [5:0] win_l0_V_56_phi_fu_4418_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_55_reg_4549pp0_it1;
reg [5:0] win_l0_V_55_phi_fu_4552_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_54_reg_4683pp0_it1;
reg [5:0] win_l0_V_54_phi_fu_4686_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_53_reg_4817pp0_it1;
reg [5:0] win_l0_V_53_phi_fu_4820_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_52_reg_4951pp0_it1;
reg [5:0] win_l0_V_52_phi_fu_4954_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_51_reg_5085pp0_it1;
reg [5:0] win_l0_V_51_phi_fu_5088_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_50_reg_5219pp0_it1;
reg [5:0] win_l0_V_50_phi_fu_5222_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_49_reg_5353pp0_it1;
reg [5:0] win_l0_V_49_phi_fu_5356_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_48_reg_5487pp0_it1;
reg [5:0] win_l0_V_48_phi_fu_5490_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_47_reg_5621pp0_it1;
reg [5:0] win_l0_V_47_phi_fu_5624_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_46_reg_5755pp0_it1;
reg [5:0] win_l0_V_46_phi_fu_5758_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_45_reg_5889pp0_it1;
reg [5:0] win_l0_V_45_phi_fu_5892_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_44_reg_6023pp0_it1;
reg [5:0] win_l0_V_44_phi_fu_6026_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_43_reg_6157pp0_it1;
reg [5:0] win_l0_V_43_phi_fu_6160_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_42_reg_6291pp0_it1;
reg [5:0] win_l0_V_42_phi_fu_6294_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_41_reg_6425pp0_it1;
reg [5:0] win_l0_V_41_phi_fu_6428_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_40_reg_6559pp0_it1;
reg [5:0] win_l0_V_40_phi_fu_6562_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_39_reg_6693pp0_it1;
reg [5:0] win_l0_V_39_phi_fu_6696_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_38_reg_6827pp0_it1;
reg [5:0] win_l0_V_38_phi_fu_6830_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_37_reg_6961pp0_it1;
reg [5:0] win_l0_V_37_phi_fu_6964_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_36_reg_7095pp0_it1;
reg [5:0] win_l0_V_36_phi_fu_7098_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_35_reg_7229pp0_it1;
reg [5:0] win_l0_V_35_phi_fu_7232_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_34_reg_7363pp0_it1;
reg [5:0] win_l0_V_34_phi_fu_7366_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_33_reg_7497pp0_it1;
reg [5:0] win_l0_V_33_phi_fu_7500_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_32_reg_7631pp0_it1;
reg [5:0] win_l0_V_32_phi_fu_7634_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_31_reg_7765pp0_it1;
reg [5:0] win_l0_V_31_phi_fu_7768_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_30_reg_7899pp0_it1;
reg [5:0] win_l0_V_30_phi_fu_7902_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_29_reg_8033pp0_it1;
reg [5:0] win_l0_V_29_phi_fu_8036_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_28_reg_8167pp0_it1;
reg [5:0] win_l0_V_28_phi_fu_8170_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_27_reg_8301pp0_it1;
reg [5:0] win_l0_V_27_phi_fu_8304_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_26_reg_8435pp0_it1;
reg [5:0] win_l0_V_26_phi_fu_8438_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_25_reg_8569pp0_it1;
reg [5:0] win_l0_V_25_phi_fu_8572_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_24_reg_8703pp0_it1;
reg [5:0] win_l0_V_24_phi_fu_8706_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_23_reg_8837pp0_it1;
reg [5:0] win_l0_V_23_phi_fu_8840_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_22_reg_8971pp0_it1;
reg [5:0] win_l0_V_22_phi_fu_8974_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_21_reg_9105pp0_it1;
reg [5:0] win_l0_V_21_phi_fu_9108_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_20_reg_9239pp0_it1;
reg [5:0] win_l0_V_20_phi_fu_9242_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_19_reg_9373pp0_it1;
reg [5:0] win_l0_V_19_phi_fu_9376_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_18_reg_9507pp0_it1;
reg [5:0] win_l0_V_18_phi_fu_9510_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_17_reg_9641pp0_it1;
reg [5:0] win_l0_V_17_phi_fu_9644_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_16_reg_9775pp0_it1;
reg [5:0] win_l0_V_16_phi_fu_9778_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_15_reg_9909pp0_it1;
reg [5:0] win_l0_V_15_phi_fu_9912_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_14_reg_10043pp0_it1;
reg [5:0] win_l0_V_14_phi_fu_10046_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_13_reg_10177pp0_it1;
reg [5:0] win_l0_V_13_phi_fu_10180_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_12_reg_10311pp0_it1;
reg [5:0] win_l0_V_12_phi_fu_10314_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_11_reg_10445pp0_it1;
reg [5:0] win_l0_V_11_phi_fu_10448_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_10_reg_10579pp0_it1;
reg [5:0] win_l0_V_10_phi_fu_10582_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_9_reg_10713pp0_it1;
reg [5:0] win_l0_V_9_phi_fu_10716_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_8_reg_10847pp0_it1;
reg [5:0] win_l0_V_8_phi_fu_10850_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_7_reg_10981pp0_it1;
reg [5:0] win_l0_V_7_phi_fu_10984_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_6_reg_11115pp0_it1;
reg [5:0] win_l0_V_6_phi_fu_11118_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_5_reg_11249pp0_it1;
reg [5:0] win_l0_V_5_phi_fu_11252_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_4_reg_11383pp0_it1;
reg [5:0] win_l0_V_4_phi_fu_11386_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_3_reg_11517pp0_it1;
reg [5:0] win_l0_V_3_phi_fu_11520_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_2_reg_11651pp0_it1;
reg [5:0] win_l0_V_2_phi_fu_11654_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_59_reg_11785pp0_it1;
reg [5:0] win_l0_V_59_phi_fu_11788_p128;
wire [5:0] ap_reg_phiprechg_win_l0_V_reg_11919pp0_it1;
reg [5:0] win_l0_V_phi_fu_11922_p128;
wire [5:0] ap_reg_phiprechg_win_l1_V_1_load_reg_12053pp0_it1;
wire [0:0] tmp_226_fu_17403_p2;
wire [0:0] tmp_229_fu_17427_p2;
wire [0:0] tmp_232_fu_17451_p2;
wire [0:0] or_cond118_fu_17421_p2;
wire [0:0] or_cond119_fu_17445_p2;
wire [0:0] or_cond120_fu_17469_p2;
reg [5:0] win_l1_V_1_load_phi_fu_12056_p8;
wire [1:0] ap_reg_phiprechg_a_winid_V_1_reg_12070pp0_it1;
reg [1:0] a_winid_V_1_phi_fu_12073_p8;
wire [2:0] ap_reg_phiprechg_ranki_l1_0_V_1_reg_12087pp0_it1;
reg [2:0] ranki_l1_0_V_1_phi_fu_12090_p10;
wire [5:0] ap_reg_phiprechg_win_l1_V_1_load_1_reg_12107pp0_it1;
wire [0:0] tmp_351_1_fu_17483_p2;
wire [0:0] tmp_366_1_fu_17507_p2;
wire [0:0] tmp_375_1_fu_17531_p2;
wire [0:0] or_cond121_fu_17501_p2;
wire [0:0] or_cond122_fu_17525_p2;
wire [0:0] or_cond123_fu_17549_p2;
reg [5:0] win_l1_V_1_load_1_phi_fu_12110_p8;
wire [2:0] ap_reg_phiprechg_a_winid_V_1_1_reg_12124pp0_it1;
reg [2:0] a_winid_V_1_1_phi_fu_12127_p8;
wire [3:0] ap_reg_phiprechg_ranki_l1_1_V_1_reg_12141pp0_it1;
reg [3:0] ranki_l1_1_V_1_phi_fu_12144_p10;
wire [5:0] ap_reg_phiprechg_win_l1_V_1_load_2_reg_12161pp0_it1;
wire [0:0] tmp_351_2_fu_17563_p2;
wire [0:0] tmp_366_2_fu_17587_p2;
wire [0:0] tmp_375_2_fu_17611_p2;
wire [0:0] or_cond124_fu_17581_p2;
wire [0:0] or_cond125_fu_17605_p2;
wire [0:0] or_cond126_fu_17629_p2;
reg [5:0] win_l1_V_1_load_2_phi_fu_12164_p8;
wire [3:0] ap_reg_phiprechg_a_winid_V_1_2_reg_12178pp0_it1;
reg [3:0] a_winid_V_1_2_phi_fu_12181_p8;
wire [4:0] ap_reg_phiprechg_ranki_l1_2_V_1_reg_12195pp0_it1;
reg [4:0] ranki_l1_2_V_1_phi_fu_12198_p10;
wire [5:0] ap_reg_phiprechg_win_l1_V_1_load_3_reg_12215pp0_it1;
wire [0:0] tmp_351_3_fu_17643_p2;
wire [0:0] tmp_366_3_fu_17667_p2;
wire [0:0] tmp_375_3_fu_17691_p2;
wire [0:0] or_cond127_fu_17661_p2;
wire [0:0] or_cond128_fu_17685_p2;
wire [0:0] or_cond129_fu_17709_p2;
reg [5:0] win_l1_V_1_load_3_phi_fu_12218_p8;
wire [2:0] ap_reg_phiprechg_a_winid_V_1_3_reg_12232pp0_it1;
reg [2:0] a_winid_V_1_3_phi_fu_12235_p8;
wire [4:0] ap_reg_phiprechg_ranki_l1_3_V_1_reg_12249pp0_it1;
reg [4:0] ranki_l1_3_V_1_phi_fu_12252_p10;
wire [5:0] ap_reg_phiprechg_win_l1_V_1_load_s_reg_12269pp0_it1;
wire [0:0] tmp_351_4_fu_17723_p2;
wire [0:0] tmp_366_4_fu_17747_p2;
wire [0:0] tmp_375_4_fu_17771_p2;
wire [0:0] or_cond130_fu_17741_p2;
wire [0:0] or_cond131_fu_17765_p2;
wire [0:0] or_cond132_fu_17789_p2;
reg [5:0] win_l1_V_1_load_s_phi_fu_12272_p8;
wire [4:0] ap_reg_phiprechg_a_winid_V_1_4_reg_12286pp0_it1;
reg [4:0] a_winid_V_1_4_phi_fu_12289_p8;
wire [5:0] ap_reg_phiprechg_ranki_l1_4_V_1_reg_12303pp0_it1;
reg [5:0] ranki_l1_4_V_1_phi_fu_12306_p66;
wire [5:0] ap_reg_phiprechg_win_l1_V_1_load_1_1_reg_12407pp0_it1;
wire [0:0] tmp_351_5_fu_17799_p2;
wire [0:0] tmp_366_5_fu_17823_p2;
wire [0:0] tmp_375_5_fu_17847_p2;
wire [0:0] or_cond133_fu_17817_p2;
wire [0:0] or_cond134_fu_17841_p2;
wire [0:0] or_cond135_fu_17865_p2;
reg [5:0] win_l1_V_1_load_1_1_phi_fu_12410_p8;
wire [4:0] ap_reg_phiprechg_a_winid_V_1_5_reg_12424pp0_it1;
reg [4:0] a_winid_V_1_5_phi_fu_12427_p8;
wire [5:0] ap_reg_phiprechg_ranki_l1_5_V_1_reg_12441pp0_it1;
reg [5:0] ranki_l1_5_V_1_phi_fu_12444_p66;
wire [5:0] ap_reg_phiprechg_win_l1_V_1_load_2_1_reg_12545pp0_it1;
wire [0:0] tmp_351_6_fu_17875_p2;
wire [0:0] tmp_366_6_fu_17899_p2;
wire [0:0] tmp_375_6_fu_17923_p2;
wire [0:0] or_cond136_fu_17893_p2;
wire [0:0] or_cond137_fu_17917_p2;
wire [0:0] or_cond138_fu_17941_p2;
reg [5:0] win_l1_V_1_load_2_1_phi_fu_12548_p8;
wire [3:0] ap_reg_phiprechg_a_winid_V_1_6_reg_12562pp0_it1;
reg [3:0] a_winid_V_1_6_phi_fu_12565_p8;
wire [5:0] ap_reg_phiprechg_ranki_l1_6_V_1_reg_12579pp0_it1;
wire signed [4:0] a_winid_V_1_6_cast_fu_17947_p1;
reg [5:0] ranki_l1_6_V_1_phi_fu_12582_p66;
wire [5:0] ap_reg_phiprechg_win_l1_V_1_load_3_1_reg_12683pp0_it1;
wire [0:0] tmp_351_7_fu_17955_p2;
wire [0:0] tmp_366_7_fu_17979_p2;
wire [0:0] tmp_375_7_fu_18003_p2;
wire [0:0] or_cond139_fu_17973_p2;
wire [0:0] or_cond140_fu_17997_p2;
wire [0:0] or_cond141_fu_18021_p2;
reg [5:0] win_l1_V_1_load_3_1_phi_fu_12686_p8;
wire [2:0] ap_reg_phiprechg_a_winid_V_1_7_reg_12700pp0_it1;
reg [2:0] a_winid_V_1_7_phi_fu_12703_p8;
wire [5:0] ap_reg_phiprechg_ranki_l1_7_V_1_reg_12717pp0_it1;
wire signed [4:0] a_winid_V_1_7_cast_fu_18027_p1;
reg [5:0] ranki_l1_7_V_1_phi_fu_12720_p66;
wire [5:0] ap_reg_phiprechg_win_l1_V_1_load_4_reg_12821pp0_it1;
wire [0:0] tmp_351_8_fu_18035_p2;
wire [0:0] tmp_366_8_fu_18059_p2;
wire [0:0] tmp_375_8_fu_18083_p2;
wire [0:0] or_cond142_fu_18053_p2;
wire [0:0] or_cond143_fu_18077_p2;
wire [0:0] or_cond144_fu_18101_p2;
reg [5:0] win_l1_V_1_load_4_phi_fu_12824_p8;
wire [5:0] ap_reg_phiprechg_a_winid_V_1_8_reg_12838pp0_it1;
reg [5:0] a_winid_V_1_8_phi_fu_12841_p8;
wire [5:0] ap_reg_phiprechg_ranki_l1_8_V_1_reg_12855pp0_it1;
reg [5:0] ranki_l1_8_V_1_phi_fu_12858_p128;
wire [5:0] ap_reg_phiprechg_win_l1_V_1_load_1_2_reg_13052pp0_it1;
wire [0:0] tmp_351_9_fu_18111_p2;
wire [0:0] tmp_366_9_fu_18135_p2;
wire [0:0] tmp_375_9_fu_18159_p2;
wire [0:0] or_cond145_fu_18129_p2;
wire [0:0] or_cond146_fu_18153_p2;
wire [0:0] or_cond147_fu_18177_p2;
reg [5:0] win_l1_V_1_load_1_2_phi_fu_13055_p8;
wire [5:0] ap_reg_phiprechg_a_winid_V_1_9_reg_13069pp0_it1;
reg [5:0] a_winid_V_1_9_phi_fu_13072_p8;
wire [5:0] ap_reg_phiprechg_ranki_l1_9_V_1_reg_13086pp0_it1;
reg [5:0] ranki_l1_9_V_1_phi_fu_13089_p128;
wire [5:0] ap_reg_phiprechg_win_l1_V_1_load_2_2_reg_13283pp0_it1;
wire [0:0] tmp_351_s_fu_18187_p2;
wire [0:0] tmp_366_s_fu_18211_p2;
wire [0:0] tmp_375_s_fu_18235_p2;
wire [0:0] or_cond148_fu_18205_p2;
wire [0:0] or_cond149_fu_18229_p2;
wire [0:0] or_cond150_fu_18253_p2;
reg [5:0] win_l1_V_1_load_2_2_phi_fu_13286_p8;
wire [5:0] ap_reg_phiprechg_a_winid_V_1_s_reg_13300pp0_it1;
reg [5:0] a_winid_V_1_s_phi_fu_13303_p8;
wire [5:0] ap_reg_phiprechg_ranki_l1_10_V_1_reg_13317pp0_it1;
reg [5:0] ranki_l1_10_V_1_phi_fu_13320_p128;
wire [5:0] ap_reg_phiprechg_win_l1_V_1_load_3_2_reg_13514pp0_it1;
wire [0:0] tmp_351_10_fu_18263_p2;
wire [0:0] tmp_366_10_fu_18287_p2;
wire [0:0] tmp_375_10_fu_18311_p2;
wire [0:0] or_cond151_fu_18281_p2;
wire [0:0] or_cond152_fu_18305_p2;
wire [0:0] or_cond153_fu_18329_p2;
reg [5:0] win_l1_V_1_load_3_2_phi_fu_13517_p8;
wire [5:0] ap_reg_phiprechg_a_winid_V_1_10_reg_13531pp0_it1;
reg [5:0] a_winid_V_1_10_phi_fu_13534_p8;
wire [5:0] ap_reg_phiprechg_ranki_l1_11_V_1_reg_13548pp0_it1;
reg [5:0] ranki_l1_11_V_1_phi_fu_13551_p128;
wire [5:0] ap_reg_phiprechg_win_l1_V_1_load_5_reg_13745pp0_it1;
wire [0:0] tmp_351_11_fu_18339_p2;
wire [0:0] tmp_366_11_fu_18363_p2;
wire [0:0] tmp_375_11_fu_18387_p2;
wire [0:0] or_cond154_fu_18357_p2;
wire [0:0] or_cond155_fu_18381_p2;
wire [0:0] or_cond156_fu_18405_p2;
reg [5:0] win_l1_V_1_load_5_phi_fu_13748_p8;
wire [4:0] ap_reg_phiprechg_a_winid_V_1_11_reg_13762pp0_it1;
reg [4:0] a_winid_V_1_11_phi_fu_13765_p8;
wire [5:0] ap_reg_phiprechg_ranki_l1_12_V_1_reg_13779pp0_it1;
wire signed [5:0] a_winid_V_1_11_cast_fu_18411_p1;
reg [5:0] ranki_l1_12_V_1_phi_fu_13782_p128;
wire [5:0] ap_reg_phiprechg_win_l1_V_1_load_1_3_reg_13976pp0_it1;
wire [0:0] tmp_351_12_fu_18419_p2;
wire [0:0] tmp_366_12_fu_18443_p2;
wire [0:0] tmp_375_12_fu_18467_p2;
wire [0:0] or_cond157_fu_18437_p2;
wire [0:0] or_cond158_fu_18461_p2;
wire [0:0] or_cond159_fu_18485_p2;
reg [5:0] win_l1_V_1_load_1_3_phi_fu_13979_p8;
wire [4:0] ap_reg_phiprechg_a_winid_V_1_12_reg_13993pp0_it1;
reg [4:0] a_winid_V_1_12_phi_fu_13996_p8;
wire [5:0] ap_reg_phiprechg_ranki_l1_13_V_1_reg_14010pp0_it1;
wire signed [5:0] a_winid_V_1_12_cast_fu_18491_p1;
reg [5:0] ranki_l1_13_V_1_phi_fu_14013_p128;
wire [5:0] ap_reg_phiprechg_win_l1_V_1_load_2_3_reg_14207pp0_it1;
wire [0:0] tmp_351_13_fu_18499_p2;
wire [0:0] tmp_366_13_fu_18523_p2;
wire [0:0] tmp_375_13_fu_18547_p2;
wire [0:0] or_cond160_fu_18517_p2;
wire [0:0] or_cond161_fu_18541_p2;
wire [0:0] or_cond162_fu_18565_p2;
reg [5:0] win_l1_V_1_load_2_3_phi_fu_14210_p8;
wire [3:0] ap_reg_phiprechg_a_winid_V_1_13_reg_14224pp0_it1;
reg [3:0] a_winid_V_1_13_phi_fu_14227_p8;
wire [5:0] ap_reg_phiprechg_ranki_l1_14_V_1_reg_14241pp0_it1;
wire signed [5:0] a_winid_V_1_13_cast_fu_18571_p1;
reg [5:0] ranki_l1_14_V_1_phi_fu_14244_p128;
wire [5:0] ap_reg_phiprechg_win_l2_V_1_load_reg_14438pp0_it1;
wire [0:0] tmp_235_fu_18579_p2;
wire [0:0] tmp_238_fu_18603_p2;
wire [0:0] tmp_241_fu_18627_p2;
wire [0:0] or_cond67_fu_18597_p2;
wire [0:0] or_cond68_fu_18621_p2;
wire [0:0] or_cond69_fu_18645_p2;
reg [5:0] win_l2_V_1_load_phi_fu_14441_p8;
wire [1:0] ap_reg_phiprechg_a_winid_1_V_1_reg_14455pp0_it1;
reg [1:0] a_winid_1_V_1_phi_fu_14458_p8;
wire [5:0] ap_reg_phiprechg_sorter_a_V_load_14_phi_reg_14472pp0_it1;
wire [6:0] tmp_2773_fu_19527_p2;
reg [5:0] sorter_a_V_load_14_phi_phi_fu_14475_p122;
wire [6:0] p_086_0_i_fu_19560_p3;
wire [6:0] ap_reg_phiprechg_winid_2_V_write_assign_reg_14599pp0_it1;
wire [0:0] tmp_37_fu_19533_p2;
reg [6:0] winid_2_V_write_assign_phi_fu_14602_p4;
wire [6:0] p_tmp_1_fu_19551_p3;
wire [0:0] tmp_209_fu_15158_p2;
wire [0:0] tmp_210_fu_15164_p2;
wire [0:0] tmp_212_fu_15182_p2;
wire [0:0] tmp_213_fu_15188_p2;
wire [0:0] tmp_208_fu_15152_p2;
wire [0:0] or_cond57_fu_15170_p2;
wire [0:0] sel_tmp2013_demorgan_fu_15218_p2;
wire [0:0] tmp_211_fu_15176_p2;
wire [0:0] or_cond60_fu_15194_p2;
wire [0:0] sel_tmp2017_demorgan_fu_15232_p2;
wire [0:0] sel_tmp39_fu_15238_p2;
wire [0:0] sel_tmp40_fu_15244_p2;
wire [5:0] sel_tmp_fu_15224_p3;
wire [0:0] tmp_216_fu_15212_p2;
wire [0:0] tmp_214_fu_15200_p2;
wire [0:0] tmp_fu_15258_p2;
wire [0:0] tmp_215_fu_15206_p2;
wire [0:0] sel_tmp2023_demorgan_fu_15264_p2;
wire [0:0] tmp15_fu_15282_p2;
wire [0:0] sel_tmp43_fu_15276_p2;
wire [0:0] sel_tmp45_fu_15288_p2;
wire [0:0] sel_tmp42_fu_15270_p2;
wire [0:0] sel_tmp46_fu_15294_p2;
wire [5:0] sel_tmp41_fu_15250_p3;
wire [0:0] or_cond_fu_15316_p2;
wire [1:0] newSel_fu_15308_p3;
wire [1:0] newSel141_cast_fu_15322_p3;
wire [0:0] tmp_295_1_fu_15344_p2;
wire [0:0] tmp_306_1_fu_15350_p2;
wire [0:0] tmp_312_1_fu_15368_p2;
wire [0:0] tmp_315_1_fu_15374_p2;
wire [0:0] tmp_321_1_fu_15392_p2;
wire [0:0] tmp_324_1_fu_15398_p2;
wire [0:0] tmp_295_2_fu_15416_p2;
wire [0:0] tmp_306_2_fu_15422_p2;
wire [0:0] tmp_312_2_fu_15440_p2;
wire [0:0] tmp_315_2_fu_15446_p2;
wire [0:0] tmp_321_2_fu_15464_p2;
wire [0:0] tmp_324_2_fu_15470_p2;
wire [0:0] tmp_295_3_fu_15488_p2;
wire [0:0] tmp_306_3_fu_15494_p2;
wire [0:0] tmp_312_3_fu_15512_p2;
wire [0:0] tmp_315_3_fu_15518_p2;
wire [0:0] tmp_321_3_fu_15536_p2;
wire [0:0] tmp_324_3_fu_15542_p2;
wire [0:0] tmp_295_4_fu_15560_p2;
wire [0:0] tmp_306_4_fu_15566_p2;
wire [0:0] tmp_312_4_fu_15584_p2;
wire [0:0] tmp_315_4_fu_15590_p2;
wire [0:0] tmp_321_4_fu_15608_p2;
wire [0:0] tmp_324_4_fu_15614_p2;
wire [0:0] tmp_295_5_fu_15632_p2;
wire [0:0] tmp_306_5_fu_15638_p2;
wire [0:0] tmp_312_5_fu_15656_p2;
wire [0:0] tmp_315_5_fu_15662_p2;
wire [0:0] tmp_321_5_fu_15680_p2;
wire [0:0] tmp_324_5_fu_15686_p2;
wire [0:0] tmp_295_6_fu_15704_p2;
wire [0:0] tmp_306_6_fu_15710_p2;
wire [0:0] tmp_312_6_fu_15728_p2;
wire [0:0] tmp_315_6_fu_15734_p2;
wire [0:0] tmp_321_6_fu_15752_p2;
wire [0:0] tmp_324_6_fu_15758_p2;
wire [0:0] tmp_295_7_fu_15776_p2;
wire [0:0] tmp_306_7_fu_15782_p2;
wire [0:0] tmp_312_7_fu_15800_p2;
wire [0:0] tmp_315_7_fu_15806_p2;
wire [0:0] tmp_321_7_fu_15824_p2;
wire [0:0] tmp_324_7_fu_15830_p2;
wire [0:0] tmp_295_8_fu_15848_p2;
wire [0:0] tmp_306_8_fu_15854_p2;
wire [0:0] tmp_312_8_fu_15872_p2;
wire [0:0] tmp_315_8_fu_15878_p2;
wire [0:0] tmp_321_8_fu_15896_p2;
wire [0:0] tmp_324_8_fu_15902_p2;
wire [0:0] tmp_295_9_fu_15920_p2;
wire [0:0] tmp_306_9_fu_15926_p2;
wire [0:0] tmp_312_9_fu_15944_p2;
wire [0:0] tmp_315_9_fu_15950_p2;
wire [0:0] tmp_321_9_fu_15968_p2;
wire [0:0] tmp_324_9_fu_15974_p2;
wire [0:0] tmp_295_s_fu_15992_p2;
wire [0:0] tmp_306_s_fu_15998_p2;
wire [0:0] tmp_312_s_fu_16016_p2;
wire [0:0] tmp_315_s_fu_16022_p2;
wire [0:0] tmp_321_s_fu_16040_p2;
wire [0:0] tmp_324_s_fu_16046_p2;
wire [0:0] tmp_295_10_fu_16064_p2;
wire [0:0] tmp_306_10_fu_16070_p2;
wire [0:0] tmp_312_10_fu_16088_p2;
wire [0:0] tmp_315_10_fu_16094_p2;
wire [0:0] tmp_321_10_fu_16112_p2;
wire [0:0] tmp_324_10_fu_16118_p2;
wire [0:0] tmp_295_11_fu_16136_p2;
wire [0:0] tmp_306_11_fu_16142_p2;
wire [0:0] tmp_312_11_fu_16160_p2;
wire [0:0] tmp_315_11_fu_16166_p2;
wire [0:0] tmp_321_11_fu_16184_p2;
wire [0:0] tmp_324_11_fu_16190_p2;
wire [0:0] tmp_295_12_fu_16208_p2;
wire [0:0] tmp_306_12_fu_16214_p2;
wire [0:0] tmp_312_12_fu_16232_p2;
wire [0:0] tmp_315_12_fu_16238_p2;
wire [0:0] tmp_321_12_fu_16256_p2;
wire [0:0] tmp_324_12_fu_16262_p2;
wire [0:0] tmp_295_13_fu_16280_p2;
wire [0:0] tmp_306_13_fu_16286_p2;
wire [0:0] tmp_312_13_fu_16304_p2;
wire [0:0] tmp_315_13_fu_16310_p2;
wire [0:0] tmp_321_13_fu_16328_p2;
wire [0:0] tmp_324_13_fu_16334_p2;
wire [0:0] tmp_308_1_fu_16352_p2;
wire [0:0] tmp_311_1_fu_16358_p2;
wire [0:0] tmp_317_1_fu_16376_p2;
wire [0:0] tmp_320_1_fu_16382_p2;
wire [0:0] tmp_305_1_fu_16346_p2;
wire [0:0] or_cond52_fu_16364_p2;
wire [0:0] tmp_314_1_fu_16370_p2;
wire [0:0] or_cond53_fu_16388_p2;
wire [0:0] sel_tmp2061_demorgan_fu_16426_p2;
wire [0:0] sel_tmp48_fu_16432_p2;
wire [5:0] sel_tmp47_fu_16418_p3;
wire [0:0] tmp_328_1_fu_16406_p2;
wire [0:0] tmp_323_1_fu_16394_p2;
wire [0:0] tmp16_fu_16452_p2;
wire [0:0] tmp_326_1_fu_16400_p2;
wire [0:0] sel_tmp2067_demorgan_fu_16458_p2;
wire [0:0] tmp17_fu_16476_p2;
wire [0:0] sel_tmp52_fu_16470_p2;
wire [0:0] sel_tmp54_fu_16482_p2;
wire [0:0] sel_tmp51_fu_16464_p2;
wire [5:0] sel_tmp50_fu_16444_p3;
wire [0:0] tmp_308_2_fu_16508_p2;
wire [0:0] tmp_311_2_fu_16514_p2;
wire [0:0] tmp_317_2_fu_16532_p2;
wire [0:0] tmp_320_2_fu_16538_p2;
wire [0:0] tmp_305_2_fu_16502_p2;
wire [0:0] or_cond55_fu_16520_p2;
wire [0:0] tmp_314_2_fu_16526_p2;
wire [0:0] or_cond56_fu_16544_p2;
wire [0:0] sel_tmp2105_demorgan_fu_16582_p2;
wire [0:0] sel_tmp57_fu_16588_p2;
wire [5:0] sel_tmp56_fu_16574_p3;
wire [0:0] tmp_328_2_fu_16562_p2;
wire [0:0] tmp_323_2_fu_16550_p2;
wire [0:0] tmp18_fu_16608_p2;
wire [0:0] tmp_326_2_fu_16556_p2;
wire [0:0] sel_tmp2111_demorgan_fu_16614_p2;
wire [0:0] tmp19_fu_16632_p2;
wire [0:0] sel_tmp61_fu_16626_p2;
wire [0:0] sel_tmp63_fu_16638_p2;
wire [0:0] sel_tmp60_fu_16620_p2;
wire [5:0] sel_tmp59_fu_16600_p3;
wire [0:0] tmp_308_3_fu_16664_p2;
wire [0:0] tmp_311_3_fu_16670_p2;
wire [0:0] tmp_317_3_fu_16688_p2;
wire [0:0] tmp_320_3_fu_16694_p2;
wire [0:0] tmp_305_3_fu_16658_p2;
wire [0:0] or_cond58_fu_16676_p2;
wire [0:0] tmp_314_3_fu_16682_p2;
wire [0:0] or_cond59_fu_16700_p2;
wire [0:0] sel_tmp2149_demorgan_fu_16738_p2;
wire [0:0] sel_tmp66_fu_16744_p2;
wire [5:0] sel_tmp65_fu_16730_p3;
wire [0:0] tmp_328_3_fu_16718_p2;
wire [0:0] tmp_323_3_fu_16706_p2;
wire [0:0] tmp20_fu_16764_p2;
wire [0:0] tmp_326_3_fu_16712_p2;
wire [0:0] sel_tmp2155_demorgan_fu_16770_p2;
wire [0:0] tmp21_fu_16788_p2;
wire [0:0] sel_tmp70_fu_16782_p2;
wire [0:0] sel_tmp72_fu_16794_p2;
wire [0:0] sel_tmp69_fu_16776_p2;
wire [5:0] sel_tmp68_fu_16756_p3;
wire signed [5:0] ranki_l1_0_V_0_cast2_fu_16814_p1;
wire signed [5:0] ranki_l1_1_V_cast_fu_16822_p1;
wire signed [5:0] ranki_l1_2_V_cast_fu_16830_p1;
wire signed [5:0] ranki_l1_3_V_cast_fu_16838_p1;
wire [0:0] tmp_218_fu_16915_p2;
wire [0:0] tmp_219_fu_16920_p2;
wire [0:0] tmp_221_fu_16936_p2;
wire [0:0] tmp_222_fu_16942_p2;
wire [0:0] tmp_224_fu_16959_p2;
wire [0:0] tmp_225_fu_16965_p2;
wire [6:0] ranki_l1_0_V_0_cast_fu_16818_p1;
wire [6:0] ranki_l1_1_V_0_cast_fu_16826_p1;
wire [6:0] ranki_l1_2_V_0_cast_fu_16834_p1;
wire [6:0] ranki_l1_3_V_0_cast_fu_16842_p1;
wire [6:0] ranki_l1_4_V_0_cast_fu_16846_p1;
wire [6:0] ranki_l1_5_V_0_cast_fu_16850_p1;
wire [6:0] ranki_l1_6_V_0_cast_fu_16858_p1;
wire [6:0] ranki_l1_7_V_0_cast_fu_16866_p1;
wire [6:0] ranki_l1_8_V_0_cast_fu_16870_p1;
wire [6:0] ranki_l1_9_V_0_cast_fu_16874_p1;
wire [6:0] ranki_l1_10_V_0_cast_fu_16878_p1;
wire [6:0] ranki_l1_11_V_0_cast_fu_16882_p1;
wire [6:0] ranki_l1_12_V_0_cast_fu_16890_p1;
wire [6:0] ranki_l1_13_V_0_cast_fu_16898_p1;
wire [6:0] ranki_l1_14_V_0_cast_fu_16906_p1;
wire [3:0] ranki_l2_0_V_fu_16981_p17;
wire [0:0] or_cond4_fu_17026_p2;
wire [2:0] newSel14_fu_17019_p3;
wire [2:0] newSel15_fu_17030_p3;
wire [2:0] newSel16_fu_17037_p3;
wire [3:0] ranki_l2_1_V_fu_17049_p17;
wire [0:0] or_cond5_fu_17094_p2;
wire [3:0] newSel17_fu_17087_p3;
wire [3:0] newSel18_fu_17098_p3;
wire [3:0] ranki_l2_2_V_fu_17113_p17;
wire [0:0] or_cond6_fu_17158_p2;
wire [2:0] newSel20_fu_17151_p3;
wire [2:0] newSel21_fu_17162_p3;
wire [2:0] newSel22_fu_17169_p3;
wire signed [3:0] ranki_l2_3_V_fu_17181_p17;
wire [0:0] tmp_14_fu_17224_p2;
wire [0:0] tmp_15_fu_17229_p2;
wire [0:0] tmp22_fu_17234_p2;
wire [0:0] tmp_s_fu_17219_p2;
wire [0:0] tmp_17_fu_17251_p2;
wire [0:0] tmp_18_fu_17255_p2;
wire [0:0] tmp23_fu_17259_p2;
wire [0:0] tmp_16_fu_17246_p2;
wire [0:0] tmp_20_fu_17276_p2;
wire [0:0] tmp_21_fu_17280_p2;
wire [0:0] tmp24_fu_17284_p2;
wire [0:0] tmp_19_fu_17271_p2;
wire [0:0] or_cond66_fu_17290_p2;
wire [0:0] or_cond62_fu_17240_p2;
wire [0:0] or_cond64_fu_17265_p2;
wire [0:0] sel_tmp75_fu_17314_p2;
wire [1:0] phitmp_fu_17302_p3;
wire [1:0] sel_tmp74_fu_17310_p1;
wire [5:0] temp_V_2_3_win_l2_V_load_5_fu_17296_p3;
wire [5:0] sel_tmp76_fu_17328_p3;
wire [6:0] ranki_l2_0_V_fu_16981_p18;
wire [6:0] ranki_l2_1_V_fu_17049_p18;
wire [6:0] ranki_l2_2_V_fu_17113_p18;
wire [6:0] ranki_l2_3_V_fu_17181_p18;
wire [1:0] winid0_V_fu_17343_p5;
wire [6:0] winid0_V_fu_17343_p6;
wire [5:0] win0_V_fu_17335_p3;
wire [0:0] tmp_24_fu_17373_p2;
wire [6:0] tmp_26_fu_17379_p2;
wire [0:0] tmp_227_fu_17409_p2;
wire [0:0] tmp_228_fu_17415_p2;
wire [0:0] tmp_230_fu_17433_p2;
wire [0:0] tmp_231_fu_17439_p2;
wire [0:0] tmp_233_fu_17457_p2;
wire [0:0] tmp_234_fu_17463_p2;
wire signed [5:0] ranki_l1_0_V_1_cast_fu_17475_p1;
wire [0:0] tmp_352_1_fu_17489_p2;
wire [0:0] tmp_363_1_fu_17495_p2;
wire [0:0] tmp_369_1_fu_17513_p2;
wire [0:0] tmp_372_1_fu_17519_p2;
wire [0:0] tmp_378_1_fu_17537_p2;
wire [0:0] tmp_381_1_fu_17543_p2;
wire signed [5:0] ranki_l1_1_V_1_cast_fu_17555_p1;
wire [0:0] tmp_352_2_fu_17569_p2;
wire [0:0] tmp_363_2_fu_17575_p2;
wire [0:0] tmp_369_2_fu_17593_p2;
wire [0:0] tmp_372_2_fu_17599_p2;
wire [0:0] tmp_378_2_fu_17617_p2;
wire [0:0] tmp_381_2_fu_17623_p2;
wire signed [5:0] ranki_l1_2_V_1_cast_fu_17635_p1;
wire [0:0] tmp_352_3_fu_17649_p2;
wire [0:0] tmp_363_3_fu_17655_p2;
wire [0:0] tmp_369_3_fu_17673_p2;
wire [0:0] tmp_372_3_fu_17679_p2;
wire [0:0] tmp_378_3_fu_17697_p2;
wire [0:0] tmp_381_3_fu_17703_p2;
wire signed [5:0] ranki_l1_3_V_1_cast_fu_17715_p1;
wire [0:0] tmp_352_4_fu_17729_p2;
wire [0:0] tmp_363_4_fu_17735_p2;
wire [0:0] tmp_369_4_fu_17753_p2;
wire [0:0] tmp_372_4_fu_17759_p2;
wire [0:0] tmp_378_4_fu_17777_p2;
wire [0:0] tmp_381_4_fu_17783_p2;
wire [0:0] tmp_352_5_fu_17805_p2;
wire [0:0] tmp_363_5_fu_17811_p2;
wire [0:0] tmp_369_5_fu_17829_p2;
wire [0:0] tmp_372_5_fu_17835_p2;
wire [0:0] tmp_378_5_fu_17853_p2;
wire [0:0] tmp_381_5_fu_17859_p2;
wire [0:0] tmp_352_6_fu_17881_p2;
wire [0:0] tmp_363_6_fu_17887_p2;
wire [0:0] tmp_369_6_fu_17905_p2;
wire [0:0] tmp_372_6_fu_17911_p2;
wire [0:0] tmp_378_6_fu_17929_p2;
wire [0:0] tmp_381_6_fu_17935_p2;
wire [0:0] tmp_352_7_fu_17961_p2;
wire [0:0] tmp_363_7_fu_17967_p2;
wire [0:0] tmp_369_7_fu_17985_p2;
wire [0:0] tmp_372_7_fu_17991_p2;
wire [0:0] tmp_378_7_fu_18009_p2;
wire [0:0] tmp_381_7_fu_18015_p2;
wire [0:0] tmp_352_8_fu_18041_p2;
wire [0:0] tmp_363_8_fu_18047_p2;
wire [0:0] tmp_369_8_fu_18065_p2;
wire [0:0] tmp_372_8_fu_18071_p2;
wire [0:0] tmp_378_8_fu_18089_p2;
wire [0:0] tmp_381_8_fu_18095_p2;
wire [0:0] tmp_352_9_fu_18117_p2;
wire [0:0] tmp_363_9_fu_18123_p2;
wire [0:0] tmp_369_9_fu_18141_p2;
wire [0:0] tmp_372_9_fu_18147_p2;
wire [0:0] tmp_378_9_fu_18165_p2;
wire [0:0] tmp_381_9_fu_18171_p2;
wire [0:0] tmp_352_s_fu_18193_p2;
wire [0:0] tmp_363_s_fu_18199_p2;
wire [0:0] tmp_369_s_fu_18217_p2;
wire [0:0] tmp_372_s_fu_18223_p2;
wire [0:0] tmp_378_s_fu_18241_p2;
wire [0:0] tmp_381_s_fu_18247_p2;
wire [0:0] tmp_352_10_fu_18269_p2;
wire [0:0] tmp_363_10_fu_18275_p2;
wire [0:0] tmp_369_10_fu_18293_p2;
wire [0:0] tmp_372_10_fu_18299_p2;
wire [0:0] tmp_378_10_fu_18317_p2;
wire [0:0] tmp_381_10_fu_18323_p2;
wire [0:0] tmp_352_11_fu_18345_p2;
wire [0:0] tmp_363_11_fu_18351_p2;
wire [0:0] tmp_369_11_fu_18369_p2;
wire [0:0] tmp_372_11_fu_18375_p2;
wire [0:0] tmp_378_11_fu_18393_p2;
wire [0:0] tmp_381_11_fu_18399_p2;
wire [0:0] tmp_352_12_fu_18425_p2;
wire [0:0] tmp_363_12_fu_18431_p2;
wire [0:0] tmp_369_12_fu_18449_p2;
wire [0:0] tmp_372_12_fu_18455_p2;
wire [0:0] tmp_378_12_fu_18473_p2;
wire [0:0] tmp_381_12_fu_18479_p2;
wire [0:0] tmp_352_13_fu_18505_p2;
wire [0:0] tmp_363_13_fu_18511_p2;
wire [0:0] tmp_369_13_fu_18529_p2;
wire [0:0] tmp_372_13_fu_18535_p2;
wire [0:0] tmp_378_13_fu_18553_p2;
wire [0:0] tmp_381_13_fu_18559_p2;
wire [0:0] tmp_236_fu_18585_p2;
wire [0:0] tmp_237_fu_18591_p2;
wire [0:0] tmp_239_fu_18609_p2;
wire [0:0] tmp_240_fu_18615_p2;
wire [0:0] tmp_242_fu_18633_p2;
wire [0:0] tmp_243_fu_18639_p2;
wire [6:0] ranki_l1_0_V_3_0_cast_fu_17479_p1;
wire [6:0] ranki_l1_1_V_3_0_cast_fu_17559_p1;
wire [6:0] ranki_l1_2_V_3_0_cast_fu_17639_p1;
wire [6:0] ranki_l1_3_V_3_0_cast_fu_17719_p1;
wire [6:0] ranki_l1_4_V_3_0_cast_fu_17795_p1;
wire [6:0] ranki_l1_5_V_3_0_cast_fu_17871_p1;
wire [6:0] ranki_l1_6_V_3_0_cast_fu_17951_p1;
wire [6:0] ranki_l1_7_V_3_0_cast_fu_18031_p1;
wire [6:0] ranki_l1_8_V_3_0_cast_fu_18107_p1;
wire [6:0] ranki_l1_9_V_3_0_cast_fu_18183_p1;
wire [6:0] ranki_l1_10_V_3_0_cast_fu_18259_p1;
wire [6:0] ranki_l1_11_V_3_0_cast_fu_18335_p1;
wire [6:0] ranki_l1_12_V_3_0_cast_fu_18415_p1;
wire [6:0] ranki_l1_13_V_3_0_cast_fu_18495_p1;
wire [6:0] ranki_l1_14_V_3_0_cast_fu_18575_p1;
wire [3:0] ranki_l2_0_V_1_fu_18655_p17;
wire [0:0] tmp_365_1_fu_18699_p2;
wire [0:0] tmp_368_1_fu_18705_p2;
wire [0:0] tmp_374_1_fu_18723_p2;
wire [0:0] tmp_377_1_fu_18729_p2;
wire [0:0] tmp_362_1_fu_18693_p2;
wire [0:0] or_cond70_fu_18711_p2;
wire [0:0] sel_tmp2197_demorgan_fu_18759_p2;
wire [0:0] tmp_371_1_fu_18717_p2;
wire [0:0] or_cond71_fu_18735_p2;
wire [0:0] sel_tmp2201_demorgan_fu_18773_p2;
wire [0:0] sel_tmp78_fu_18779_p2;
wire [0:0] sel_tmp79_fu_18785_p2;
wire [5:0] sel_tmp77_fu_18765_p3;
wire [0:0] tmp_385_1_fu_18753_p2;
wire [0:0] tmp_380_1_fu_18741_p2;
wire [0:0] tmp42_fu_18799_p2;
wire [0:0] tmp_383_1_fu_18747_p2;
wire [0:0] sel_tmp2207_demorgan_fu_18805_p2;
wire [0:0] tmp43_fu_18823_p2;
wire [0:0] sel_tmp82_fu_18817_p2;
wire [0:0] sel_tmp84_fu_18829_p2;
wire [0:0] sel_tmp81_fu_18811_p2;
wire [0:0] sel_tmp85_fu_18835_p2;
wire [5:0] sel_tmp80_fu_18791_p3;
wire [0:0] or_cond7_fu_18857_p2;
wire [2:0] newSel23_fu_18849_p3;
wire [2:0] newSel24_fu_18863_p3;
wire [2:0] newSel25_fu_18871_p3;
wire [3:0] ranki_l2_1_V_1_fu_18883_p17;
wire [0:0] tmp_365_2_fu_18927_p2;
wire [0:0] tmp_368_2_fu_18933_p2;
wire [0:0] tmp_374_2_fu_18951_p2;
wire [0:0] tmp_377_2_fu_18957_p2;
wire [0:0] tmp_362_2_fu_18921_p2;
wire [0:0] or_cond73_fu_18939_p2;
wire [0:0] sel_tmp2241_demorgan_fu_18987_p2;
wire [0:0] tmp_371_2_fu_18945_p2;
wire [0:0] or_cond74_fu_18963_p2;
wire [0:0] sel_tmp2245_demorgan_fu_19001_p2;
wire [0:0] sel_tmp87_fu_19007_p2;
wire [0:0] sel_tmp88_fu_19013_p2;
wire [5:0] sel_tmp86_fu_18993_p3;
wire [0:0] tmp_385_2_fu_18981_p2;
wire [0:0] tmp_380_2_fu_18969_p2;
wire [0:0] tmp44_fu_19027_p2;
wire [0:0] tmp_383_2_fu_18975_p2;
wire [0:0] sel_tmp2251_demorgan_fu_19033_p2;
wire [0:0] tmp45_fu_19051_p2;
wire [0:0] sel_tmp91_fu_19045_p2;
wire [0:0] sel_tmp93_fu_19057_p2;
wire [0:0] sel_tmp90_fu_19039_p2;
wire [0:0] sel_tmp94_fu_19063_p2;
wire [5:0] sel_tmp89_fu_19019_p3;
wire [0:0] or_cond8_fu_19085_p2;
wire [3:0] newSel26_fu_19077_p3;
wire [3:0] newSel27_fu_19091_p3;
wire [3:0] ranki_l2_2_V_1_fu_19107_p17;
wire [0:0] tmp_365_3_fu_19151_p2;
wire [0:0] tmp_368_3_fu_19157_p2;
wire [0:0] tmp_374_3_fu_19175_p2;
wire [0:0] tmp_377_3_fu_19181_p2;
wire [0:0] tmp_362_3_fu_19145_p2;
wire [0:0] or_cond76_fu_19163_p2;
wire [0:0] sel_tmp2285_demorgan_fu_19211_p2;
wire [0:0] tmp_371_3_fu_19169_p2;
wire [0:0] or_cond77_fu_19187_p2;
wire [0:0] sel_tmp2289_demorgan_fu_19225_p2;
wire [0:0] sel_tmp96_fu_19231_p2;
wire [0:0] sel_tmp97_fu_19237_p2;
wire [5:0] sel_tmp95_fu_19217_p3;
wire [0:0] tmp_385_3_fu_19205_p2;
wire [0:0] tmp_380_3_fu_19193_p2;
wire [0:0] tmp46_fu_19251_p2;
wire [0:0] tmp_383_3_fu_19199_p2;
wire [0:0] sel_tmp2295_demorgan_fu_19257_p2;
wire [0:0] tmp47_fu_19275_p2;
wire [0:0] sel_tmp100_fu_19269_p2;
wire [0:0] sel_tmp102_fu_19281_p2;
wire [0:0] sel_tmp99_fu_19263_p2;
wire [0:0] sel_tmp103_fu_19287_p2;
wire [5:0] sel_tmp98_fu_19243_p3;
wire [0:0] or_cond9_fu_19309_p2;
wire [2:0] newSel29_fu_19301_p3;
wire [2:0] newSel30_fu_19315_p3;
wire [2:0] newSel31_fu_19323_p3;
wire signed [3:0] ranki_l2_3_V_1_fu_19335_p17;
wire [5:0] win_l2_V_1_load_1_fu_18841_p3;
wire [5:0] win_l2_V_1_load_2_fu_19069_p3;
wire [5:0] temp_V_4_3_fu_19293_p3;
wire [0:0] tmp_28_fu_19379_p2;
wire [0:0] tmp_29_fu_19385_p2;
wire [0:0] tmp48_fu_19391_p2;
wire [0:0] tmp_27_fu_19373_p2;
wire [0:0] tmp_31_fu_19409_p2;
wire [0:0] tmp_32_fu_19415_p2;
wire [0:0] tmp49_fu_19421_p2;
wire [0:0] tmp_30_fu_19403_p2;
wire [0:0] tmp_34_fu_19439_p2;
wire [0:0] tmp_35_fu_19445_p2;
wire [0:0] tmp50_fu_19451_p2;
wire [0:0] tmp_33_fu_19433_p2;
wire [0:0] or_cond84_fu_19457_p2;
wire [0:0] or_cond80_fu_19397_p2;
wire [0:0] or_cond82_fu_19427_p2;
wire [0:0] sel_tmp105_fu_19483_p2;
wire [1:0] phitmp1_fu_19471_p3;
wire [1:0] sel_tmp104_fu_19479_p1;
wire [5:0] temp_V_4_3_win_l2_V_1_load_2_fu_19463_p3;
wire [5:0] sel_tmp106_fu_19497_p3;
wire [6:0] ranki_l2_0_V_1_fu_18655_p18;
wire [6:0] ranki_l2_1_V_1_fu_18883_p18;
wire [6:0] ranki_l2_2_V_1_fu_19107_p18;
wire [6:0] ranki_l2_3_V_1_fu_19335_p18;
wire [1:0] winid0_V_1_fu_19513_p5;
wire [6:0] winid0_V_1_fu_19513_p6;
wire [5:0] win0_V_1_fu_19505_p3;
wire [0:0] tmp_38_fu_19539_p2;
wire [6:0] tmp_40_fu_19545_p2;
sp_sort call_ret_sp_sort_fu_14608(
.sorter_0_a_V_read(rank_ex_0_V_read),
.sorter_1_a_V_read(rank_ex_1_V_read),
.sorter_2_a_V_read(rank_ex_2_V_read),
.sorter_3_a_V_read(rank_ex_3_V_read),
.sorter_4_a_V_read(rank_ex_4_V_read),
.sorter_5_a_V_read(rank_ex_5_V_read),
.sorter_6_a_V_read(rank_ex_6_V_read),
.sorter_7_a_V_read(rank_ex_7_V_read),
.sorter_8_a_V_read(rank_ex_8_V_read),
.sorter_9_a_V_read(rank_ex_9_V_read),
.sorter_10_a_V_read(rank_ex_10_V_read),
.sorter_11_a_V_read(rank_ex_11_V_read),
.sorter_12_a_V_read(rank_ex_12_V_read),
.sorter_13_a_V_read(rank_ex_13_V_read),
.sorter_14_a_V_read(rank_ex_14_V_read),
.sorter_15_a_V_read(rank_ex_15_V_read),
.sorter_16_a_V_read(rank_ex_16_V_read),
.sorter_17_a_V_read(rank_ex_17_V_read),
.sorter_18_a_V_read(rank_ex_18_V_read),
.sorter_19_a_V_read(rank_ex_19_V_read),
.sorter_20_a_V_read(rank_ex_20_V_read),
.sorter_21_a_V_read(rank_ex_21_V_read),
.sorter_22_a_V_read(rank_ex_22_V_read),
.sorter_23_a_V_read(rank_ex_23_V_read),
.sorter_24_a_V_read(rank_ex_24_V_read),
.sorter_25_a_V_read(rank_ex_25_V_read),
.sorter_26_a_V_read(rank_ex_26_V_read),
.sorter_27_a_V_read(rank_ex_27_V_read),
.sorter_28_a_V_read(rank_ex_28_V_read),
.sorter_29_a_V_read(rank_ex_29_V_read),
.sorter_30_a_V_read(rank_ex_30_V_read),
.sorter_31_a_V_read(rank_ex_31_V_read),
.sorter_32_a_V_read(rank_ex_32_V_read),
.sorter_33_a_V_read(rank_ex_33_V_read),
.sorter_34_a_V_read(rank_ex_34_V_read),
.sorter_35_a_V_read(rank_ex_35_V_read),
.sorter_36_a_V_read(rank_ex_36_V_read),
.sorter_37_a_V_read(rank_ex_37_V_read),
.sorter_38_a_V_read(rank_ex_38_V_read),
.sorter_39_a_V_read(rank_ex_39_V_read),
.sorter_40_a_V_read(rank_ex_40_V_read),
.sorter_41_a_V_read(rank_ex_41_V_read),
.sorter_42_a_V_read(rank_ex_42_V_read),
.sorter_43_a_V_read(rank_ex_43_V_read),
.sorter_44_a_V_read(rank_ex_44_V_read),
.sorter_45_a_V_read(rank_ex_45_V_read),
.sorter_46_a_V_read(rank_ex_46_V_read),
.sorter_47_a_V_read(rank_ex_47_V_read),
.sorter_48_a_V_read(rank_ex_48_V_read),
.sorter_49_a_V_read(rank_ex_49_V_read),
.sorter_50_a_V_read(rank_ex_50_V_read),
.sorter_51_a_V_read(rank_ex_51_V_read),
.sorter_52_a_V_read(rank_ex_52_V_read),
.sorter_53_a_V_read(rank_ex_53_V_read),
.sorter_54_a_V_read(rank_ex_54_V_read),
.sorter_55_a_V_read(rank_ex_55_V_read),
.sorter_56_a_V_read(rank_ex_56_V_read),
.sorter_57_a_V_read(rank_ex_57_V_read),
.sorter_58_a_V_read(rank_ex_58_V_read),
.sorter_59_a_V_read(rank_ex_59_V_read),
.sorter_60_a_V_read(rank_ex_60_V_read),
.sorter_61_a_V_read(rank_ex_61_V_read),
.sorter_62_a_V_read(rank_ex_62_V_read),
.sorter_63_a_V_read(rank_ex_63_V_read),
.sorter_64_a_V_read(rank_ex_64_V_read),
.sorter_65_a_V_read(rank_ex_65_V_read),
.sorter_66_a_V_read(rank_ex_66_V_read),
.sorter_67_a_V_read(rank_ex_67_V_read),
.sorter_68_a_V_read(rank_ex_68_V_read),
.sorter_69_a_V_read(rank_ex_69_V_read),
.sorter_70_a_V_read(rank_ex_70_V_read),
.sorter_71_a_V_read(rank_ex_71_V_read),
.sorter_72_a_V_read(rank_ex_72_V_read),
.sorter_73_a_V_read(rank_ex_73_V_read),
.sorter_74_a_V_read(rank_ex_74_V_read),
.sorter_75_a_V_read(rank_ex_75_V_read),
.sorter_76_a_V_read(rank_ex_76_V_read),
.sorter_77_a_V_read(rank_ex_77_V_read),
.sorter_78_a_V_read(rank_ex_78_V_read),
.sorter_79_a_V_read(rank_ex_79_V_read),
.sorter_80_a_V_read(rank_ex_80_V_read),
.sorter_81_a_V_read(rank_ex_81_V_read),
.sorter_82_a_V_read(rank_ex_82_V_read),
.sorter_83_a_V_read(rank_ex_83_V_read),
.sorter_84_a_V_read(rank_ex_84_V_read),
.sorter_85_a_V_read(rank_ex_85_V_read),
.sorter_86_a_V_read(rank_ex_86_V_read),
.sorter_87_a_V_read(rank_ex_87_V_read),
.sorter_88_a_V_read(rank_ex_88_V_read),
.sorter_89_a_V_read(rank_ex_89_V_read),
.sorter_90_a_V_read(rank_ex_90_V_read),
.sorter_91_a_V_read(rank_ex_91_V_read),
.sorter_92_a_V_read(rank_ex_92_V_read),
.sorter_93_a_V_read(rank_ex_93_V_read),
.sorter_94_a_V_read(rank_ex_94_V_read),
.sorter_95_a_V_read(rank_ex_95_V_read),
.sorter_96_a_V_read(rank_ex_96_V_read),
.sorter_97_a_V_read(rank_ex_97_V_read),
.sorter_98_a_V_read(rank_ex_98_V_read),
.sorter_99_a_V_read(rank_ex_99_V_read),
.sorter_100_a_V_read(rank_ex_100_V_read),
.sorter_101_a_V_read(rank_ex_101_V_read),
.sorter_102_a_V_read(rank_ex_102_V_read),
.sorter_103_a_V_read(rank_ex_103_V_read),
.sorter_104_a_V_read(rank_ex_104_V_read),
.sorter_105_a_V_read(rank_ex_105_V_read),
.sorter_106_a_V_read(rank_ex_106_V_read),
.sorter_107_a_V_read(rank_ex_107_V_read),
.sorter_108_a_V_read(rank_ex_108_V_read),
.sorter_109_a_V_read(rank_ex_109_V_read),
.sorter_110_a_V_read(rank_ex_110_V_read),
.sorter_111_a_V_read(rank_ex_111_V_read),
.sorter_112_a_V_read(rank_ex_112_V_read),
.sorter_113_a_V_read(rank_ex_113_V_read),
.sorter_114_a_V_read(rank_ex_114_V_read),
.sorter_115_a_V_read(rank_ex_115_V_read),
.sorter_116_a_V_read(rank_ex_116_V_read),
.sorter_117_a_V_read(rank_ex_117_V_read),
.sorter_118_a_V_read(rank_ex_118_V_read),
.sorter_119_a_V_read(rank_ex_119_V_read),
.sorter_120_a_V_read(rank_ex_120_V_read),
.sorter_121_a_V_read(rank_ex_121_V_read),
.ap_return_0(call_ret_sp_sort_fu_14608_ap_return_0),
.ap_return_1(call_ret_sp_sort_fu_14608_ap_return_1),
.ap_return_2(call_ret_sp_sort_fu_14608_ap_return_2),
.ap_return_3(call_ret_sp_sort_fu_14608_ap_return_3),
.ap_return_4(call_ret_sp_sort_fu_14608_ap_return_4),
.ap_return_5(call_ret_sp_sort_fu_14608_ap_return_5),
.ap_return_6(call_ret_sp_sort_fu_14608_ap_return_6),
.ap_return_7(call_ret_sp_sort_fu_14608_ap_return_7),
.ap_return_8(call_ret_sp_sort_fu_14608_ap_return_8),
.ap_return_9(call_ret_sp_sort_fu_14608_ap_return_9),
.ap_return_10(call_ret_sp_sort_fu_14608_ap_return_10),
.ap_return_11(call_ret_sp_sort_fu_14608_ap_return_11),
.ap_return_12(call_ret_sp_sort_fu_14608_ap_return_12),
.ap_return_13(call_ret_sp_sort_fu_14608_ap_return_13),
.ap_return_14(call_ret_sp_sort_fu_14608_ap_return_14),
.ap_return_15(call_ret_sp_sort_fu_14608_ap_return_15),
.ap_return_16(call_ret_sp_sort_fu_14608_ap_return_16),
.ap_return_17(call_ret_sp_sort_fu_14608_ap_return_17),
.ap_return_18(call_ret_sp_sort_fu_14608_ap_return_18),
.ap_return_19(call_ret_sp_sort_fu_14608_ap_return_19),
.ap_return_20(call_ret_sp_sort_fu_14608_ap_return_20),
.ap_return_21(call_ret_sp_sort_fu_14608_ap_return_21),
.ap_return_22(call_ret_sp_sort_fu_14608_ap_return_22),
.ap_return_23(call_ret_sp_sort_fu_14608_ap_return_23),
.ap_return_24(call_ret_sp_sort_fu_14608_ap_return_24),
.ap_return_25(call_ret_sp_sort_fu_14608_ap_return_25),
.ap_return_26(call_ret_sp_sort_fu_14608_ap_return_26),
.ap_return_27(call_ret_sp_sort_fu_14608_ap_return_27),
.ap_return_28(call_ret_sp_sort_fu_14608_ap_return_28),
.ap_return_29(call_ret_sp_sort_fu_14608_ap_return_29),
.ap_return_30(call_ret_sp_sort_fu_14608_ap_return_30),
.ap_return_31(call_ret_sp_sort_fu_14608_ap_return_31),
.ap_return_32(call_ret_sp_sort_fu_14608_ap_return_32),
.ap_return_33(call_ret_sp_sort_fu_14608_ap_return_33),
.ap_return_34(call_ret_sp_sort_fu_14608_ap_return_34),
.ap_return_35(call_ret_sp_sort_fu_14608_ap_return_35),
.ap_return_36(call_ret_sp_sort_fu_14608_ap_return_36),
.ap_return_37(call_ret_sp_sort_fu_14608_ap_return_37),
.ap_return_38(call_ret_sp_sort_fu_14608_ap_return_38),
.ap_return_39(call_ret_sp_sort_fu_14608_ap_return_39),
.ap_return_40(call_ret_sp_sort_fu_14608_ap_return_40),
.ap_return_41(call_ret_sp_sort_fu_14608_ap_return_41),
.ap_return_42(call_ret_sp_sort_fu_14608_ap_return_42),
.ap_return_43(call_ret_sp_sort_fu_14608_ap_return_43),
.ap_return_44(call_ret_sp_sort_fu_14608_ap_return_44),
.ap_return_45(call_ret_sp_sort_fu_14608_ap_return_45),
.ap_return_46(call_ret_sp_sort_fu_14608_ap_return_46),
.ap_return_47(call_ret_sp_sort_fu_14608_ap_return_47),
.ap_return_48(call_ret_sp_sort_fu_14608_ap_return_48),
.ap_return_49(call_ret_sp_sort_fu_14608_ap_return_49),
.ap_return_50(call_ret_sp_sort_fu_14608_ap_return_50),
.ap_return_51(call_ret_sp_sort_fu_14608_ap_return_51),
.ap_return_52(call_ret_sp_sort_fu_14608_ap_return_52),
.ap_return_53(call_ret_sp_sort_fu_14608_ap_return_53),
.ap_return_54(call_ret_sp_sort_fu_14608_ap_return_54),
.ap_return_55(call_ret_sp_sort_fu_14608_ap_return_55),
.ap_return_56(call_ret_sp_sort_fu_14608_ap_return_56),
.ap_return_57(call_ret_sp_sort_fu_14608_ap_return_57),
.ap_return_58(call_ret_sp_sort_fu_14608_ap_return_58),
.ap_return_59(call_ret_sp_sort_fu_14608_ap_return_59),
.ap_return_60(call_ret_sp_sort_fu_14608_ap_return_60),
.ap_return_61(call_ret_sp_sort_fu_14608_ap_return_61),
.ap_return_62(call_ret_sp_sort_fu_14608_ap_return_62)
);
sp_mux_16to1_sel4_7_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 7 ),
.din2_WIDTH( 7 ),
.din3_WIDTH( 7 ),
.din4_WIDTH( 7 ),
.din5_WIDTH( 7 ),
.din6_WIDTH( 7 ),
.din7_WIDTH( 7 ),
.din8_WIDTH( 7 ),
.din9_WIDTH( 7 ),
.din10_WIDTH( 7 ),
.din11_WIDTH( 7 ),
.din12_WIDTH( 7 ),
.din13_WIDTH( 7 ),
.din14_WIDTH( 7 ),
.din15_WIDTH( 7 ),
.din16_WIDTH( 7 ),
.din17_WIDTH( 4 ),
.dout_WIDTH( 7 ))
sp_mux_16to1_sel4_7_1_U2759(
.din1(ranki_l1_0_V_0_cast_fu_16818_p1),
.din2(ranki_l1_1_V_0_cast_fu_16826_p1),
.din3(ranki_l1_2_V_0_cast_fu_16834_p1),
.din4(ranki_l1_3_V_0_cast_fu_16842_p1),
.din5(ranki_l1_4_V_0_cast_fu_16846_p1),
.din6(ranki_l1_5_V_0_cast_fu_16850_p1),
.din7(ranki_l1_6_V_0_cast_fu_16858_p1),
.din8(ranki_l1_7_V_0_cast_fu_16866_p1),
.din9(ranki_l1_8_V_0_cast_fu_16870_p1),
.din10(ranki_l1_9_V_0_cast_fu_16874_p1),
.din11(ranki_l1_10_V_0_cast_fu_16878_p1),
.din12(ranki_l1_11_V_0_cast_fu_16882_p1),
.din13(ranki_l1_12_V_0_cast_fu_16890_p1),
.din14(ranki_l1_13_V_0_cast_fu_16898_p1),
.din15(ranki_l1_14_V_0_cast_fu_16906_p1),
.din16(ap_const_lv7_3C),
.din17(ranki_l2_0_V_fu_16981_p17),
.dout(ranki_l2_0_V_fu_16981_p18)
);
sp_mux_16to1_sel4_7_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 7 ),
.din2_WIDTH( 7 ),
.din3_WIDTH( 7 ),
.din4_WIDTH( 7 ),
.din5_WIDTH( 7 ),
.din6_WIDTH( 7 ),
.din7_WIDTH( 7 ),
.din8_WIDTH( 7 ),
.din9_WIDTH( 7 ),
.din10_WIDTH( 7 ),
.din11_WIDTH( 7 ),
.din12_WIDTH( 7 ),
.din13_WIDTH( 7 ),
.din14_WIDTH( 7 ),
.din15_WIDTH( 7 ),
.din16_WIDTH( 7 ),
.din17_WIDTH( 4 ),
.dout_WIDTH( 7 ))
sp_mux_16to1_sel4_7_1_U2760(
.din1(ranki_l1_0_V_0_cast_fu_16818_p1),
.din2(ranki_l1_1_V_0_cast_fu_16826_p1),
.din3(ranki_l1_2_V_0_cast_fu_16834_p1),
.din4(ranki_l1_3_V_0_cast_fu_16842_p1),
.din5(ranki_l1_4_V_0_cast_fu_16846_p1),
.din6(ranki_l1_5_V_0_cast_fu_16850_p1),
.din7(ranki_l1_6_V_0_cast_fu_16858_p1),
.din8(ranki_l1_7_V_0_cast_fu_16866_p1),
.din9(ranki_l1_8_V_0_cast_fu_16870_p1),
.din10(ranki_l1_9_V_0_cast_fu_16874_p1),
.din11(ranki_l1_10_V_0_cast_fu_16878_p1),
.din12(ranki_l1_11_V_0_cast_fu_16882_p1),
.din13(ranki_l1_12_V_0_cast_fu_16890_p1),
.din14(ranki_l1_13_V_0_cast_fu_16898_p1),
.din15(ranki_l1_14_V_0_cast_fu_16906_p1),
.din16(ap_const_lv7_3C),
.din17(ranki_l2_1_V_fu_17049_p17),
.dout(ranki_l2_1_V_fu_17049_p18)
);
sp_mux_16to1_sel4_7_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 7 ),
.din2_WIDTH( 7 ),
.din3_WIDTH( 7 ),
.din4_WIDTH( 7 ),
.din5_WIDTH( 7 ),
.din6_WIDTH( 7 ),
.din7_WIDTH( 7 ),
.din8_WIDTH( 7 ),
.din9_WIDTH( 7 ),
.din10_WIDTH( 7 ),
.din11_WIDTH( 7 ),
.din12_WIDTH( 7 ),
.din13_WIDTH( 7 ),
.din14_WIDTH( 7 ),
.din15_WIDTH( 7 ),
.din16_WIDTH( 7 ),
.din17_WIDTH( 4 ),
.dout_WIDTH( 7 ))
sp_mux_16to1_sel4_7_1_U2761(
.din1(ranki_l1_0_V_0_cast_fu_16818_p1),
.din2(ranki_l1_1_V_0_cast_fu_16826_p1),
.din3(ranki_l1_2_V_0_cast_fu_16834_p1),
.din4(ranki_l1_3_V_0_cast_fu_16842_p1),
.din5(ranki_l1_4_V_0_cast_fu_16846_p1),
.din6(ranki_l1_5_V_0_cast_fu_16850_p1),
.din7(ranki_l1_6_V_0_cast_fu_16858_p1),
.din8(ranki_l1_7_V_0_cast_fu_16866_p1),
.din9(ranki_l1_8_V_0_cast_fu_16870_p1),
.din10(ranki_l1_9_V_0_cast_fu_16874_p1),
.din11(ranki_l1_10_V_0_cast_fu_16878_p1),
.din12(ranki_l1_11_V_0_cast_fu_16882_p1),
.din13(ranki_l1_12_V_0_cast_fu_16890_p1),
.din14(ranki_l1_13_V_0_cast_fu_16898_p1),
.din15(ranki_l1_14_V_0_cast_fu_16906_p1),
.din16(ap_const_lv7_3C),
.din17(ranki_l2_2_V_fu_17113_p17),
.dout(ranki_l2_2_V_fu_17113_p18)
);
sp_mux_16to1_sel4_7_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 7 ),
.din2_WIDTH( 7 ),
.din3_WIDTH( 7 ),
.din4_WIDTH( 7 ),
.din5_WIDTH( 7 ),
.din6_WIDTH( 7 ),
.din7_WIDTH( 7 ),
.din8_WIDTH( 7 ),
.din9_WIDTH( 7 ),
.din10_WIDTH( 7 ),
.din11_WIDTH( 7 ),
.din12_WIDTH( 7 ),
.din13_WIDTH( 7 ),
.din14_WIDTH( 7 ),
.din15_WIDTH( 7 ),
.din16_WIDTH( 7 ),
.din17_WIDTH( 4 ),
.dout_WIDTH( 7 ))
sp_mux_16to1_sel4_7_1_U2762(
.din1(ranki_l1_0_V_0_cast_fu_16818_p1),
.din2(ranki_l1_1_V_0_cast_fu_16826_p1),
.din3(ranki_l1_2_V_0_cast_fu_16834_p1),
.din4(ranki_l1_3_V_0_cast_fu_16842_p1),
.din5(ranki_l1_4_V_0_cast_fu_16846_p1),
.din6(ranki_l1_5_V_0_cast_fu_16850_p1),
.din7(ranki_l1_6_V_0_cast_fu_16858_p1),
.din8(ranki_l1_7_V_0_cast_fu_16866_p1),
.din9(ranki_l1_8_V_0_cast_fu_16870_p1),
.din10(ranki_l1_9_V_0_cast_fu_16874_p1),
.din11(ranki_l1_10_V_0_cast_fu_16878_p1),
.din12(ranki_l1_11_V_0_cast_fu_16882_p1),
.din13(ranki_l1_12_V_0_cast_fu_16890_p1),
.din14(ranki_l1_13_V_0_cast_fu_16898_p1),
.din15(ranki_l1_14_V_0_cast_fu_16906_p1),
.din16(ap_const_lv7_3C),
.din17(ranki_l2_3_V_fu_17181_p17),
.dout(ranki_l2_3_V_fu_17181_p18)
);
sp_mux_4to1_sel2_7_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 7 ),
.din2_WIDTH( 7 ),
.din3_WIDTH( 7 ),
.din4_WIDTH( 7 ),
.din5_WIDTH( 2 ),
.dout_WIDTH( 7 ))
sp_mux_4to1_sel2_7_1_U2763(
.din1(ranki_l2_0_V_fu_16981_p18),
.din2(ranki_l2_1_V_fu_17049_p18),
.din3(ranki_l2_2_V_fu_17113_p18),
.din4(ranki_l2_3_V_fu_17181_p18),
.din5(winid0_V_fu_17343_p5),
.dout(winid0_V_fu_17343_p6)
);
sp_mux_16to1_sel4_7_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 7 ),
.din2_WIDTH( 7 ),
.din3_WIDTH( 7 ),
.din4_WIDTH( 7 ),
.din5_WIDTH( 7 ),
.din6_WIDTH( 7 ),
.din7_WIDTH( 7 ),
.din8_WIDTH( 7 ),
.din9_WIDTH( 7 ),
.din10_WIDTH( 7 ),
.din11_WIDTH( 7 ),
.din12_WIDTH( 7 ),
.din13_WIDTH( 7 ),
.din14_WIDTH( 7 ),
.din15_WIDTH( 7 ),
.din16_WIDTH( 7 ),
.din17_WIDTH( 4 ),
.dout_WIDTH( 7 ))
sp_mux_16to1_sel4_7_1_U2764(
.din1(ranki_l1_0_V_3_0_cast_fu_17479_p1),
.din2(ranki_l1_1_V_3_0_cast_fu_17559_p1),
.din3(ranki_l1_2_V_3_0_cast_fu_17639_p1),
.din4(ranki_l1_3_V_3_0_cast_fu_17719_p1),
.din5(ranki_l1_4_V_3_0_cast_fu_17795_p1),
.din6(ranki_l1_5_V_3_0_cast_fu_17871_p1),
.din7(ranki_l1_6_V_3_0_cast_fu_17951_p1),
.din8(ranki_l1_7_V_3_0_cast_fu_18031_p1),
.din9(ranki_l1_8_V_3_0_cast_fu_18107_p1),
.din10(ranki_l1_9_V_3_0_cast_fu_18183_p1),
.din11(ranki_l1_10_V_3_0_cast_fu_18259_p1),
.din12(ranki_l1_11_V_3_0_cast_fu_18335_p1),
.din13(ranki_l1_12_V_3_0_cast_fu_18415_p1),
.din14(ranki_l1_13_V_3_0_cast_fu_18495_p1),
.din15(ranki_l1_14_V_3_0_cast_fu_18575_p1),
.din16(ap_const_lv7_3C),
.din17(ranki_l2_0_V_1_fu_18655_p17),
.dout(ranki_l2_0_V_1_fu_18655_p18)
);
sp_mux_16to1_sel4_7_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 7 ),
.din2_WIDTH( 7 ),
.din3_WIDTH( 7 ),
.din4_WIDTH( 7 ),
.din5_WIDTH( 7 ),
.din6_WIDTH( 7 ),
.din7_WIDTH( 7 ),
.din8_WIDTH( 7 ),
.din9_WIDTH( 7 ),
.din10_WIDTH( 7 ),
.din11_WIDTH( 7 ),
.din12_WIDTH( 7 ),
.din13_WIDTH( 7 ),
.din14_WIDTH( 7 ),
.din15_WIDTH( 7 ),
.din16_WIDTH( 7 ),
.din17_WIDTH( 4 ),
.dout_WIDTH( 7 ))
sp_mux_16to1_sel4_7_1_U2765(
.din1(ranki_l1_0_V_3_0_cast_fu_17479_p1),
.din2(ranki_l1_1_V_3_0_cast_fu_17559_p1),
.din3(ranki_l1_2_V_3_0_cast_fu_17639_p1),
.din4(ranki_l1_3_V_3_0_cast_fu_17719_p1),
.din5(ranki_l1_4_V_3_0_cast_fu_17795_p1),
.din6(ranki_l1_5_V_3_0_cast_fu_17871_p1),
.din7(ranki_l1_6_V_3_0_cast_fu_17951_p1),
.din8(ranki_l1_7_V_3_0_cast_fu_18031_p1),
.din9(ranki_l1_8_V_3_0_cast_fu_18107_p1),
.din10(ranki_l1_9_V_3_0_cast_fu_18183_p1),
.din11(ranki_l1_10_V_3_0_cast_fu_18259_p1),
.din12(ranki_l1_11_V_3_0_cast_fu_18335_p1),
.din13(ranki_l1_12_V_3_0_cast_fu_18415_p1),
.din14(ranki_l1_13_V_3_0_cast_fu_18495_p1),
.din15(ranki_l1_14_V_3_0_cast_fu_18575_p1),
.din16(ap_const_lv7_3C),
.din17(ranki_l2_1_V_1_fu_18883_p17),
.dout(ranki_l2_1_V_1_fu_18883_p18)
);
sp_mux_16to1_sel4_7_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 7 ),
.din2_WIDTH( 7 ),
.din3_WIDTH( 7 ),
.din4_WIDTH( 7 ),
.din5_WIDTH( 7 ),
.din6_WIDTH( 7 ),
.din7_WIDTH( 7 ),
.din8_WIDTH( 7 ),
.din9_WIDTH( 7 ),
.din10_WIDTH( 7 ),
.din11_WIDTH( 7 ),
.din12_WIDTH( 7 ),
.din13_WIDTH( 7 ),
.din14_WIDTH( 7 ),
.din15_WIDTH( 7 ),
.din16_WIDTH( 7 ),
.din17_WIDTH( 4 ),
.dout_WIDTH( 7 ))
sp_mux_16to1_sel4_7_1_U2766(
.din1(ranki_l1_0_V_3_0_cast_fu_17479_p1),
.din2(ranki_l1_1_V_3_0_cast_fu_17559_p1),
.din3(ranki_l1_2_V_3_0_cast_fu_17639_p1),
.din4(ranki_l1_3_V_3_0_cast_fu_17719_p1),
.din5(ranki_l1_4_V_3_0_cast_fu_17795_p1),
.din6(ranki_l1_5_V_3_0_cast_fu_17871_p1),
.din7(ranki_l1_6_V_3_0_cast_fu_17951_p1),
.din8(ranki_l1_7_V_3_0_cast_fu_18031_p1),
.din9(ranki_l1_8_V_3_0_cast_fu_18107_p1),
.din10(ranki_l1_9_V_3_0_cast_fu_18183_p1),
.din11(ranki_l1_10_V_3_0_cast_fu_18259_p1),
.din12(ranki_l1_11_V_3_0_cast_fu_18335_p1),
.din13(ranki_l1_12_V_3_0_cast_fu_18415_p1),
.din14(ranki_l1_13_V_3_0_cast_fu_18495_p1),
.din15(ranki_l1_14_V_3_0_cast_fu_18575_p1),
.din16(ap_const_lv7_3C),
.din17(ranki_l2_2_V_1_fu_19107_p17),
.dout(ranki_l2_2_V_1_fu_19107_p18)
);
sp_mux_16to1_sel4_7_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 7 ),
.din2_WIDTH( 7 ),
.din3_WIDTH( 7 ),
.din4_WIDTH( 7 ),
.din5_WIDTH( 7 ),
.din6_WIDTH( 7 ),
.din7_WIDTH( 7 ),
.din8_WIDTH( 7 ),
.din9_WIDTH( 7 ),
.din10_WIDTH( 7 ),
.din11_WIDTH( 7 ),
.din12_WIDTH( 7 ),
.din13_WIDTH( 7 ),
.din14_WIDTH( 7 ),
.din15_WIDTH( 7 ),
.din16_WIDTH( 7 ),
.din17_WIDTH( 4 ),
.dout_WIDTH( 7 ))
sp_mux_16to1_sel4_7_1_U2767(
.din1(ranki_l1_0_V_3_0_cast_fu_17479_p1),
.din2(ranki_l1_1_V_3_0_cast_fu_17559_p1),
.din3(ranki_l1_2_V_3_0_cast_fu_17639_p1),
.din4(ranki_l1_3_V_3_0_cast_fu_17719_p1),
.din5(ranki_l1_4_V_3_0_cast_fu_17795_p1),
.din6(ranki_l1_5_V_3_0_cast_fu_17871_p1),
.din7(ranki_l1_6_V_3_0_cast_fu_17951_p1),
.din8(ranki_l1_7_V_3_0_cast_fu_18031_p1),
.din9(ranki_l1_8_V_3_0_cast_fu_18107_p1),
.din10(ranki_l1_9_V_3_0_cast_fu_18183_p1),
.din11(ranki_l1_10_V_3_0_cast_fu_18259_p1),
.din12(ranki_l1_11_V_3_0_cast_fu_18335_p1),
.din13(ranki_l1_12_V_3_0_cast_fu_18415_p1),
.din14(ranki_l1_13_V_3_0_cast_fu_18495_p1),
.din15(ranki_l1_14_V_3_0_cast_fu_18575_p1),
.din16(ap_const_lv7_3C),
.din17(ranki_l2_3_V_1_fu_19335_p17),
.dout(ranki_l2_3_V_1_fu_19335_p18)
);
sp_mux_4to1_sel2_7_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 7 ),
.din2_WIDTH( 7 ),
.din3_WIDTH( 7 ),
.din4_WIDTH( 7 ),
.din5_WIDTH( 2 ),
.dout_WIDTH( 7 ))
sp_mux_4to1_sel2_7_1_U2768(
.din1(ranki_l2_0_V_1_fu_18655_p18),
.din2(ranki_l2_1_V_1_fu_18883_p18),
.din3(ranki_l2_2_V_1_fu_19107_p18),
.din4(ranki_l2_3_V_1_fu_19335_p18),
.din5(winid0_V_1_fu_19513_p5),
.dout(winid0_V_1_fu_19513_p6)
);
always @ (posedge ap_clk) begin
if (((~(1'b0 == tmp_294_s_fu_15986_p2) & ~(1'b0 == tmp_309_s_fu_16010_p2) & (1'b0 == tmp_318_s_fu_16034_p2) & (1'b0 == or_cond105_fu_16052_p2)) | (~(1'b0 == tmp_309_s_fu_16010_p2) & (1'b0 == tmp_318_s_fu_16034_p2) & ~(1'b0 == or_cond103_fu_16004_p2) & (1'b0 == or_cond105_fu_16052_p2)) | (~(1'b0 == tmp_294_s_fu_15986_p2) & (1'b0 == tmp_318_s_fu_16034_p2) & ~(1'b0 == or_cond104_fu_16028_p2) & (1'b0 == or_cond105_fu_16052_p2)) | ((1'b0 == tmp_318_s_fu_16034_p2) & ~(1'b0 == or_cond103_fu_16004_p2) & ~(1'b0 == or_cond104_fu_16028_p2) & (1'b0 == or_cond105_fu_16052_p2)))) begin
ap_reg_phiprechg_a_winid_V_10_reg_2620pp0_it1 <= ap_const_lv6_2A;
end else if (((~(1'b0 == tmp_294_s_fu_15986_p2) & (1'b0 == tmp_309_s_fu_16010_p2) & (1'b0 == or_cond104_fu_16028_p2)) | ((1'b0 == tmp_309_s_fu_16010_p2) & ~(1'b0 == or_cond103_fu_16004_p2) & (1'b0 == or_cond104_fu_16028_p2)))) begin
ap_reg_phiprechg_a_winid_V_10_reg_2620pp0_it1 <= ap_const_lv6_29;
end else if (((1'b0 == tmp_294_s_fu_15986_p2) & (1'b0 == or_cond103_fu_16004_p2))) begin
ap_reg_phiprechg_a_winid_V_10_reg_2620pp0_it1 <= ap_const_lv6_28;
end else if (((~(1'b0 == tmp_294_s_fu_15986_p2) & ~(1'b0 == tmp_309_s_fu_16010_p2) & ~(1'b0 == tmp_318_s_fu_16034_p2)) | (~(1'b0 == tmp_309_s_fu_16010_p2) & ~(1'b0 == tmp_318_s_fu_16034_p2) & ~(1'b0 == or_cond103_fu_16004_p2)) | (~(1'b0 == tmp_294_s_fu_15986_p2) & ~(1'b0 == tmp_318_s_fu_16034_p2) & ~(1'b0 == or_cond104_fu_16028_p2)) | (~(1'b0 == tmp_294_s_fu_15986_p2) & ~(1'b0 == tmp_309_s_fu_16010_p2) & ~(1'b0 == or_cond105_fu_16052_p2)) | (~(1'b0 == tmp_318_s_fu_16034_p2) & ~(1'b0 == or_cond103_fu_16004_p2) & ~(1'b0 == or_cond104_fu_16028_p2)) | (~(1'b0 == tmp_309_s_fu_16010_p2) & ~(1'b0 == or_cond103_fu_16004_p2) & ~(1'b0 == or_cond105_fu_16052_p2)) | (~(1'b0 == tmp_294_s_fu_15986_p2) & ~(1'b0 == or_cond104_fu_16028_p2) & ~(1'b0 == or_cond105_fu_16052_p2)) | (~(1'b0 == or_cond103_fu_16004_p2) & ~(1'b0 == or_cond104_fu_16028_p2) & ~(1'b0 == or_cond105_fu_16052_p2)))) begin
ap_reg_phiprechg_a_winid_V_10_reg_2620pp0_it1 <= ap_const_lv6_2B;
end else if ((1'b1 == 1'b1)) begin
ap_reg_phiprechg_a_winid_V_10_reg_2620pp0_it1 <= ap_reg_phiprechg_a_winid_V_10_reg_2620pp0_it0;
end
end
always @ (posedge ap_clk) begin
if (((~(1'b0 == tmp_294_10_fu_16058_p2) & ~(1'b0 == tmp_309_10_fu_16082_p2) & (1'b0 == tmp_318_10_fu_16106_p2) & (1'b0 == or_cond108_fu_16124_p2)) | (~(1'b0 == tmp_309_10_fu_16082_p2) & (1'b0 == tmp_318_10_fu_16106_p2) & ~(1'b0 == or_cond106_fu_16076_p2) & (1'b0 == or_cond108_fu_16124_p2)) | (~(1'b0 == tmp_294_10_fu_16058_p2) & (1'b0 == tmp_318_10_fu_16106_p2) & ~(1'b0 == or_cond107_fu_16100_p2) & (1'b0 == or_cond108_fu_16124_p2)) | ((1'b0 == tmp_318_10_fu_16106_p2) & ~(1'b0 == or_cond106_fu_16076_p2) & ~(1'b0 == or_cond107_fu_16100_p2) & (1'b0 == or_cond108_fu_16124_p2)))) begin
ap_reg_phiprechg_a_winid_V_11_reg_2838pp0_it1 <= ap_const_lv6_2E;
end else if (((~(1'b0 == tmp_294_10_fu_16058_p2) & (1'b0 == tmp_309_10_fu_16082_p2) & (1'b0 == or_cond107_fu_16100_p2)) | ((1'b0 == tmp_309_10_fu_16082_p2) & ~(1'b0 == or_cond106_fu_16076_p2) & (1'b0 == or_cond107_fu_16100_p2)))) begin
ap_reg_phiprechg_a_winid_V_11_reg_2838pp0_it1 <= ap_const_lv6_2D;
end else if (((1'b0 == tmp_294_10_fu_16058_p2) & (1'b0 == or_cond106_fu_16076_p2))) begin
ap_reg_phiprechg_a_winid_V_11_reg_2838pp0_it1 <= ap_const_lv6_2C;
end else if (((~(1'b0 == tmp_294_10_fu_16058_p2) & ~(1'b0 == tmp_309_10_fu_16082_p2) & ~(1'b0 == tmp_318_10_fu_16106_p2)) | (~(1'b0 == tmp_309_10_fu_16082_p2) & ~(1'b0 == tmp_318_10_fu_16106_p2) & ~(1'b0 == or_cond106_fu_16076_p2)) | (~(1'b0 == tmp_294_10_fu_16058_p2) & ~(1'b0 == tmp_318_10_fu_16106_p2) & ~(1'b0 == or_cond107_fu_16100_p2)) | (~(1'b0 == tmp_294_10_fu_16058_p2) & ~(1'b0 == tmp_309_10_fu_16082_p2) & ~(1'b0 == or_cond108_fu_16124_p2)) | (~(1'b0 == tmp_318_10_fu_16106_p2) & ~(1'b0 == or_cond106_fu_16076_p2) & ~(1'b0 == or_cond107_fu_16100_p2)) | (~(1'b0 == tmp_309_10_fu_16082_p2) & ~(1'b0 == or_cond106_fu_16076_p2) & ~(1'b0 == or_cond108_fu_16124_p2)) | (~(1'b0 == tmp_294_10_fu_16058_p2) & ~(1'b0 == or_cond107_fu_16100_p2) & ~(1'b0 == or_cond108_fu_16124_p2)) | (~(1'b0 == or_cond106_fu_16076_p2) & ~(1'b0 == or_cond107_fu_16100_p2) & ~(1'b0 == or_cond108_fu_16124_p2)))) begin
ap_reg_phiprechg_a_winid_V_11_reg_2838pp0_it1 <= ap_const_lv6_2F;
end else if ((1'b1 == 1'b1)) begin
ap_reg_phiprechg_a_winid_V_11_reg_2838pp0_it1 <= ap_reg_phiprechg_a_winid_V_11_reg_2838pp0_it0;
end
end
always @ (posedge ap_clk) begin
if (((~(1'b0 == tmp_294_11_fu_16130_p2) & ~(1'b0 == tmp_309_11_fu_16154_p2) & (1'b0 == tmp_318_11_fu_16178_p2) & (1'b0 == or_cond111_fu_16196_p2)) | (~(1'b0 == tmp_309_11_fu_16154_p2) & (1'b0 == tmp_318_11_fu_16178_p2) & ~(1'b0 == or_cond109_fu_16148_p2) & (1'b0 == or_cond111_fu_16196_p2)) | (~(1'b0 == tmp_294_11_fu_16130_p2) & (1'b0 == tmp_318_11_fu_16178_p2) & ~(1'b0 == or_cond110_fu_16172_p2) & (1'b0 == or_cond111_fu_16196_p2)) | ((1'b0 == tmp_318_11_fu_16178_p2) & ~(1'b0 == or_cond109_fu_16148_p2) & ~(1'b0 == or_cond110_fu_16172_p2) & (1'b0 == or_cond111_fu_16196_p2)))) begin
ap_reg_phiprechg_a_winid_V_12_reg_3056pp0_it1 <= ap_const_lv5_12;
end else if (((~(1'b0 == tmp_294_11_fu_16130_p2) & (1'b0 == tmp_309_11_fu_16154_p2) & (1'b0 == or_cond110_fu_16172_p2)) | ((1'b0 == tmp_309_11_fu_16154_p2) & ~(1'b0 == or_cond109_fu_16148_p2) & (1'b0 == or_cond110_fu_16172_p2)))) begin
ap_reg_phiprechg_a_winid_V_12_reg_3056pp0_it1 <= ap_const_lv5_11;
end else if (((1'b0 == tmp_294_11_fu_16130_p2) & (1'b0 == or_cond109_fu_16148_p2))) begin
ap_reg_phiprechg_a_winid_V_12_reg_3056pp0_it1 <= ap_const_lv5_10;
end else if (((~(1'b0 == tmp_294_11_fu_16130_p2) & ~(1'b0 == tmp_309_11_fu_16154_p2) & ~(1'b0 == tmp_318_11_fu_16178_p2)) | (~(1'b0 == tmp_309_11_fu_16154_p2) & ~(1'b0 == tmp_318_11_fu_16178_p2) & ~(1'b0 == or_cond109_fu_16148_p2)) | (~(1'b0 == tmp_294_11_fu_16130_p2) & ~(1'b0 == tmp_318_11_fu_16178_p2) & ~(1'b0 == or_cond110_fu_16172_p2)) | (~(1'b0 == tmp_294_11_fu_16130_p2) & ~(1'b0 == tmp_309_11_fu_16154_p2) & ~(1'b0 == or_cond111_fu_16196_p2)) | (~(1'b0 == tmp_318_11_fu_16178_p2) & ~(1'b0 == or_cond109_fu_16148_p2) & ~(1'b0 == or_cond110_fu_16172_p2)) | (~(1'b0 == tmp_309_11_fu_16154_p2) & ~(1'b0 == or_cond109_fu_16148_p2) & ~(1'b0 == or_cond111_fu_16196_p2)) | (~(1'b0 == tmp_294_11_fu_16130_p2) & ~(1'b0 == or_cond110_fu_16172_p2) & ~(1'b0 == or_cond111_fu_16196_p2)) | (~(1'b0 == or_cond109_fu_16148_p2) & ~(1'b0 == or_cond110_fu_16172_p2) & ~(1'b0 == or_cond111_fu_16196_p2)))) begin
ap_reg_phiprechg_a_winid_V_12_reg_3056pp0_it1 <= ap_const_lv5_13;
end else if ((1'b1 == 1'b1)) begin
ap_reg_phiprechg_a_winid_V_12_reg_3056pp0_it1 <= ap_reg_phiprechg_a_winid_V_12_reg_3056pp0_it0;
end
end
always @ (posedge ap_clk) begin
if (((~(1'b0 == tmp_294_12_fu_16202_p2) & ~(1'b0 == tmp_309_12_fu_16226_p2) & (1'b0 == tmp_318_12_fu_16250_p2) & (1'b0 == or_cond114_fu_16268_p2)) | (~(1'b0 == tmp_309_12_fu_16226_p2) & (1'b0 == tmp_318_12_fu_16250_p2) & ~(1'b0 == or_cond112_fu_16220_p2) & (1'b0 == or_cond114_fu_16268_p2)) | (~(1'b0 == tmp_294_12_fu_16202_p2) & (1'b0 == tmp_318_12_fu_16250_p2) & ~(1'b0 == or_cond113_fu_16244_p2) & (1'b0 == or_cond114_fu_16268_p2)) | ((1'b0 == tmp_318_12_fu_16250_p2) & ~(1'b0 == or_cond112_fu_16220_p2) & ~(1'b0 == or_cond113_fu_16244_p2) & (1'b0 == or_cond114_fu_16268_p2)))) begin
ap_reg_phiprechg_a_winid_V_13_reg_3274pp0_it1 <= ap_const_lv5_16;
end else if (((~(1'b0 == tmp_294_12_fu_16202_p2) & (1'b0 == tmp_309_12_fu_16226_p2) & (1'b0 == or_cond113_fu_16244_p2)) | ((1'b0 == tmp_309_12_fu_16226_p2) & ~(1'b0 == or_cond112_fu_16220_p2) & (1'b0 == or_cond113_fu_16244_p2)))) begin
ap_reg_phiprechg_a_winid_V_13_reg_3274pp0_it1 <= ap_const_lv5_15;
end else if (((1'b0 == tmp_294_12_fu_16202_p2) & (1'b0 == or_cond112_fu_16220_p2))) begin
ap_reg_phiprechg_a_winid_V_13_reg_3274pp0_it1 <= ap_const_lv5_14;
end else if (((~(1'b0 == tmp_294_12_fu_16202_p2) & ~(1'b0 == tmp_309_12_fu_16226_p2) & ~(1'b0 == tmp_318_12_fu_16250_p2)) | (~(1'b0 == tmp_309_12_fu_16226_p2) & ~(1'b0 == tmp_318_12_fu_16250_p2) & ~(1'b0 == or_cond112_fu_16220_p2)) | (~(1'b0 == tmp_294_12_fu_16202_p2) & ~(1'b0 == tmp_318_12_fu_16250_p2) & ~(1'b0 == or_cond113_fu_16244_p2)) | (~(1'b0 == tmp_294_12_fu_16202_p2) & ~(1'b0 == tmp_309_12_fu_16226_p2) & ~(1'b0 == or_cond114_fu_16268_p2)) | (~(1'b0 == tmp_318_12_fu_16250_p2) & ~(1'b0 == or_cond112_fu_16220_p2) & ~(1'b0 == or_cond113_fu_16244_p2)) | (~(1'b0 == tmp_309_12_fu_16226_p2) & ~(1'b0 == or_cond112_fu_16220_p2) & ~(1'b0 == or_cond114_fu_16268_p2)) | (~(1'b0 == tmp_294_12_fu_16202_p2) & ~(1'b0 == or_cond113_fu_16244_p2) & ~(1'b0 == or_cond114_fu_16268_p2)) | (~(1'b0 == or_cond112_fu_16220_p2) & ~(1'b0 == or_cond113_fu_16244_p2) & ~(1'b0 == or_cond114_fu_16268_p2)))) begin
ap_reg_phiprechg_a_winid_V_13_reg_3274pp0_it1 <= ap_const_lv5_17;
end else if ((1'b1 == 1'b1)) begin
ap_reg_phiprechg_a_winid_V_13_reg_3274pp0_it1 <= ap_reg_phiprechg_a_winid_V_13_reg_3274pp0_it0;
end
end
always @ (posedge ap_clk) begin
if (((~(1'b0 == tmp_294_13_fu_16274_p2) & ~(1'b0 == tmp_309_13_fu_16298_p2) & (1'b0 == tmp_318_13_fu_16322_p2) & (1'b0 == or_cond117_fu_16340_p2)) | (~(1'b0 == tmp_309_13_fu_16298_p2) & (1'b0 == tmp_318_13_fu_16322_p2) & ~(1'b0 == or_cond115_fu_16292_p2) & (1'b0 == or_cond117_fu_16340_p2)) | (~(1'b0 == tmp_294_13_fu_16274_p2) & (1'b0 == tmp_318_13_fu_16322_p2) & ~(1'b0 == or_cond116_fu_16316_p2) & (1'b0 == or_cond117_fu_16340_p2)) | ((1'b0 == tmp_318_13_fu_16322_p2) & ~(1'b0 == or_cond115_fu_16292_p2) & ~(1'b0 == or_cond116_fu_16316_p2) & (1'b0 == or_cond117_fu_16340_p2)))) begin
ap_reg_phiprechg_a_winid_V_14_reg_3492pp0_it1 <= ap_const_lv4_A;
end else if (((~(1'b0 == tmp_294_13_fu_16274_p2) & (1'b0 == tmp_309_13_fu_16298_p2) & (1'b0 == or_cond116_fu_16316_p2)) | ((1'b0 == tmp_309_13_fu_16298_p2) & ~(1'b0 == or_cond115_fu_16292_p2) & (1'b0 == or_cond116_fu_16316_p2)))) begin
ap_reg_phiprechg_a_winid_V_14_reg_3492pp0_it1 <= ap_const_lv4_9;
end else if (((1'b0 == tmp_294_13_fu_16274_p2) & (1'b0 == or_cond115_fu_16292_p2))) begin
ap_reg_phiprechg_a_winid_V_14_reg_3492pp0_it1 <= ap_const_lv4_8;
end else if (((~(1'b0 == tmp_294_13_fu_16274_p2) & ~(1'b0 == tmp_309_13_fu_16298_p2) & ~(1'b0 == tmp_318_13_fu_16322_p2)) | (~(1'b0 == tmp_309_13_fu_16298_p2) & ~(1'b0 == tmp_318_13_fu_16322_p2) & ~(1'b0 == or_cond115_fu_16292_p2)) | (~(1'b0 == tmp_294_13_fu_16274_p2) & ~(1'b0 == tmp_318_13_fu_16322_p2) & ~(1'b0 == or_cond116_fu_16316_p2)) | (~(1'b0 == tmp_294_13_fu_16274_p2) & ~(1'b0 == tmp_309_13_fu_16298_p2) & ~(1'b0 == or_cond117_fu_16340_p2)) | (~(1'b0 == tmp_318_13_fu_16322_p2) & ~(1'b0 == or_cond115_fu_16292_p2) & ~(1'b0 == or_cond116_fu_16316_p2)) | (~(1'b0 == tmp_309_13_fu_16298_p2) & ~(1'b0 == or_cond115_fu_16292_p2) & ~(1'b0 == or_cond117_fu_16340_p2)) | (~(1'b0 == tmp_294_13_fu_16274_p2) & ~(1'b0 == or_cond116_fu_16316_p2) & ~(1'b0 == or_cond117_fu_16340_p2)) | (~(1'b0 == or_cond115_fu_16292_p2) & ~(1'b0 == or_cond116_fu_16316_p2) & ~(1'b0 == or_cond117_fu_16340_p2)))) begin
ap_reg_phiprechg_a_winid_V_14_reg_3492pp0_it1 <= ap_const_lv4_B;
end else if ((1'b1 == 1'b1)) begin
ap_reg_phiprechg_a_winid_V_14_reg_3492pp0_it1 <= ap_reg_phiprechg_a_winid_V_14_reg_3492pp0_it0;
end
end
always @ (posedge ap_clk) begin
if (((~(1'b0 == tmp_294_2_fu_15410_p2) & ~(1'b0 == tmp_309_2_fu_15434_p2) & (1'b0 == tmp_318_2_fu_15458_p2) & (1'b0 == or_cond78_fu_15476_p2)) | (~(1'b0 == tmp_309_2_fu_15434_p2) & (1'b0 == tmp_318_2_fu_15458_p2) & ~(1'b0 == or_cond72_fu_15428_p2) & (1'b0 == or_cond78_fu_15476_p2)) | (~(1'b0 == tmp_294_2_fu_15410_p2) & (1'b0 == tmp_318_2_fu_15458_p2) & ~(1'b0 == or_cond75_fu_15452_p2) & (1'b0 == or_cond78_fu_15476_p2)) | ((1'b0 == tmp_318_2_fu_15458_p2) & ~(1'b0 == or_cond72_fu_15428_p2) & ~(1'b0 == or_cond75_fu_15452_p2) & (1'b0 == or_cond78_fu_15476_p2)))) begin
ap_reg_phiprechg_a_winid_V_2_reg_1589pp0_it1 <= ap_const_lv4_A;
end else if (((~(1'b0 == tmp_294_2_fu_15410_p2) & (1'b0 == tmp_309_2_fu_15434_p2) & (1'b0 == or_cond75_fu_15452_p2)) | ((1'b0 == tmp_309_2_fu_15434_p2) & ~(1'b0 == or_cond72_fu_15428_p2) & (1'b0 == or_cond75_fu_15452_p2)))) begin
ap_reg_phiprechg_a_winid_V_2_reg_1589pp0_it1 <= ap_const_lv4_9;
end else if (((1'b0 == tmp_294_2_fu_15410_p2) & (1'b0 == or_cond72_fu_15428_p2))) begin
ap_reg_phiprechg_a_winid_V_2_reg_1589pp0_it1 <= ap_const_lv4_8;
end else if (((~(1'b0 == tmp_294_2_fu_15410_p2) & ~(1'b0 == tmp_309_2_fu_15434_p2) & ~(1'b0 == tmp_318_2_fu_15458_p2)) | (~(1'b0 == tmp_309_2_fu_15434_p2) & ~(1'b0 == tmp_318_2_fu_15458_p2) & ~(1'b0 == or_cond72_fu_15428_p2)) | (~(1'b0 == tmp_294_2_fu_15410_p2) & ~(1'b0 == tmp_318_2_fu_15458_p2) & ~(1'b0 == or_cond75_fu_15452_p2)) | (~(1'b0 == tmp_294_2_fu_15410_p2) & ~(1'b0 == tmp_309_2_fu_15434_p2) & ~(1'b0 == or_cond78_fu_15476_p2)) | (~(1'b0 == tmp_318_2_fu_15458_p2) & ~(1'b0 == or_cond72_fu_15428_p2) & ~(1'b0 == or_cond75_fu_15452_p2)) | (~(1'b0 == tmp_309_2_fu_15434_p2) & ~(1'b0 == or_cond72_fu_15428_p2) & ~(1'b0 == or_cond78_fu_15476_p2)) | (~(1'b0 == tmp_294_2_fu_15410_p2) & ~(1'b0 == or_cond75_fu_15452_p2) & ~(1'b0 == or_cond78_fu_15476_p2)) | (~(1'b0 == or_cond72_fu_15428_p2) & ~(1'b0 == or_cond75_fu_15452_p2) & ~(1'b0 == or_cond78_fu_15476_p2)))) begin
ap_reg_phiprechg_a_winid_V_2_reg_1589pp0_it1 <= ap_const_lv4_B;
end else if ((1'b1 == 1'b1)) begin
ap_reg_phiprechg_a_winid_V_2_reg_1589pp0_it1 <= ap_reg_phiprechg_a_winid_V_2_reg_1589pp0_it0;
end
end
always @ (posedge ap_clk) begin
if (((~(1'b0 == tmp_294_3_fu_15482_p2) & ~(1'b0 == tmp_309_3_fu_15506_p2) & (1'b0 == tmp_318_3_fu_15530_p2) & (1'b0 == or_cond83_fu_15548_p2)) | (~(1'b0 == tmp_309_3_fu_15506_p2) & (1'b0 == tmp_318_3_fu_15530_p2) & ~(1'b0 == or_cond79_fu_15500_p2) & (1'b0 == or_cond83_fu_15548_p2)) | (~(1'b0 == tmp_294_3_fu_15482_p2) & (1'b0 == tmp_318_3_fu_15530_p2) & ~(1'b0 == or_cond81_fu_15524_p2) & (1'b0 == or_cond83_fu_15548_p2)) | ((1'b0 == tmp_318_3_fu_15530_p2) & ~(1'b0 == or_cond79_fu_15500_p2) & ~(1'b0 == or_cond81_fu_15524_p2) & (1'b0 == or_cond83_fu_15548_p2)))) begin
ap_reg_phiprechg_a_winid_V_3_reg_1643pp0_it1 <= ap_const_lv3_6;
end else if (((~(1'b0 == tmp_294_3_fu_15482_p2) & (1'b0 == tmp_309_3_fu_15506_p2) & (1'b0 == or_cond81_fu_15524_p2)) | ((1'b0 == tmp_309_3_fu_15506_p2) & ~(1'b0 == or_cond79_fu_15500_p2) & (1'b0 == or_cond81_fu_15524_p2)))) begin
ap_reg_phiprechg_a_winid_V_3_reg_1643pp0_it1 <= ap_const_lv3_5;
end else if (((1'b0 == tmp_294_3_fu_15482_p2) & (1'b0 == or_cond79_fu_15500_p2))) begin
ap_reg_phiprechg_a_winid_V_3_reg_1643pp0_it1 <= ap_const_lv3_4;
end else if (((~(1'b0 == tmp_294_3_fu_15482_p2) & ~(1'b0 == tmp_309_3_fu_15506_p2) & ~(1'b0 == tmp_318_3_fu_15530_p2)) | (~(1'b0 == tmp_309_3_fu_15506_p2) & ~(1'b0 == tmp_318_3_fu_15530_p2) & ~(1'b0 == or_cond79_fu_15500_p2)) | (~(1'b0 == tmp_294_3_fu_15482_p2) & ~(1'b0 == tmp_318_3_fu_15530_p2) & ~(1'b0 == or_cond81_fu_15524_p2)) | (~(1'b0 == tmp_294_3_fu_15482_p2) & ~(1'b0 == tmp_309_3_fu_15506_p2) & ~(1'b0 == or_cond83_fu_15548_p2)) | (~(1'b0 == tmp_318_3_fu_15530_p2) & ~(1'b0 == or_cond79_fu_15500_p2) & ~(1'b0 == or_cond81_fu_15524_p2)) | (~(1'b0 == tmp_309_3_fu_15506_p2) & ~(1'b0 == or_cond79_fu_15500_p2) & ~(1'b0 == or_cond83_fu_15548_p2)) | (~(1'b0 == tmp_294_3_fu_15482_p2) & ~(1'b0 == or_cond81_fu_15524_p2) & ~(1'b0 == or_cond83_fu_15548_p2)) | (~(1'b0 == or_cond79_fu_15500_p2) & ~(1'b0 == or_cond81_fu_15524_p2) & ~(1'b0 == or_cond83_fu_15548_p2)))) begin
ap_reg_phiprechg_a_winid_V_3_reg_1643pp0_it1 <= ap_const_lv3_7;
end else if ((1'b1 == 1'b1)) begin
ap_reg_phiprechg_a_winid_V_3_reg_1643pp0_it1 <= ap_reg_phiprechg_a_winid_V_3_reg_1643pp0_it0;
end
end
always @ (posedge ap_clk) begin
if (((~(tmp_294_4_fu_15554_p2 == 1'b0) & ~(1'b0 == tmp_309_4_fu_15578_p2) & (1'b0 == tmp_318_4_fu_15602_p2) & (1'b0 == or_cond87_fu_15620_p2)) | (~(1'b0 == tmp_309_4_fu_15578_p2) & (1'b0 == tmp_318_4_fu_15602_p2) & ~(1'b0 == or_cond85_fu_15572_p2) & (1'b0 == or_cond87_fu_15620_p2)) | (~(tmp_294_4_fu_15554_p2 == 1'b0) & (1'b0 == tmp_318_4_fu_15602_p2) & ~(1'b0 == or_cond86_fu_15596_p2) & (1'b0 == or_cond87_fu_15620_p2)) | ((1'b0 == tmp_318_4_fu_15602_p2) & ~(1'b0 == or_cond85_fu_15572_p2) & ~(1'b0 == or_cond86_fu_15596_p2) & (1'b0 == or_cond87_fu_15620_p2)))) begin
ap_reg_phiprechg_a_winid_V_4_reg_1684pp0_it1 <= ap_const_lv5_12;
end else if (((~(tmp_294_4_fu_15554_p2 == 1'b0) & (1'b0 == tmp_309_4_fu_15578_p2) & (1'b0 == or_cond86_fu_15596_p2)) | ((1'b0 == tmp_309_4_fu_15578_p2) & ~(1'b0 == or_cond85_fu_15572_p2) & (1'b0 == or_cond86_fu_15596_p2)))) begin
ap_reg_phiprechg_a_winid_V_4_reg_1684pp0_it1 <= ap_const_lv5_11;
end else if (((tmp_294_4_fu_15554_p2 == 1'b0) & (1'b0 == or_cond85_fu_15572_p2))) begin
ap_reg_phiprechg_a_winid_V_4_reg_1684pp0_it1 <= ap_const_lv5_10;
end else if (((~(tmp_294_4_fu_15554_p2 == 1'b0) & ~(1'b0 == tmp_309_4_fu_15578_p2) & ~(1'b0 == tmp_318_4_fu_15602_p2)) | (~(1'b0 == tmp_309_4_fu_15578_p2) & ~(1'b0 == tmp_318_4_fu_15602_p2) & ~(1'b0 == or_cond85_fu_15572_p2)) | (~(tmp_294_4_fu_15554_p2 == 1'b0) & ~(1'b0 == tmp_318_4_fu_15602_p2) & ~(1'b0 == or_cond86_fu_15596_p2)) | (~(tmp_294_4_fu_15554_p2 == 1'b0) & ~(1'b0 == tmp_309_4_fu_15578_p2) & ~(1'b0 == or_cond87_fu_15620_p2)) | (~(1'b0 == tmp_318_4_fu_15602_p2) & ~(1'b0 == or_cond85_fu_15572_p2) & ~(1'b0 == or_cond86_fu_15596_p2)) | (~(1'b0 == tmp_309_4_fu_15578_p2) & ~(1'b0 == or_cond85_fu_15572_p2) & ~(1'b0 == or_cond87_fu_15620_p2)) | (~(tmp_294_4_fu_15554_p2 == 1'b0) & ~(1'b0 == or_cond86_fu_15596_p2) & ~(1'b0 == or_cond87_fu_15620_p2)) | (~(1'b0 == or_cond85_fu_15572_p2) & ~(1'b0 == or_cond86_fu_15596_p2) & ~(1'b0 == or_cond87_fu_15620_p2)))) begin
ap_reg_phiprechg_a_winid_V_4_reg_1684pp0_it1 <= ap_const_lv5_13;
end else if ((1'b1 == 1'b1)) begin
ap_reg_phiprechg_a_winid_V_4_reg_1684pp0_it1 <= ap_reg_phiprechg_a_winid_V_4_reg_1684pp0_it0;
end
end
always @ (posedge ap_clk) begin
if (((~(1'b0 == tmp_294_5_fu_15626_p2) & ~(1'b0 == tmp_309_5_fu_15650_p2) & (1'b0 == tmp_318_5_fu_15674_p2) & (1'b0 == or_cond90_fu_15692_p2)) | (~(1'b0 == tmp_309_5_fu_15650_p2) & (1'b0 == tmp_318_5_fu_15674_p2) & ~(1'b0 == or_cond88_fu_15644_p2) & (1'b0 == or_cond90_fu_15692_p2)) | (~(1'b0 == tmp_294_5_fu_15626_p2) & (1'b0 == tmp_318_5_fu_15674_p2) & ~(1'b0 == or_cond89_fu_15668_p2) & (1'b0 == or_cond90_fu_15692_p2)) | ((1'b0 == tmp_318_5_fu_15674_p2) & ~(1'b0 == or_cond88_fu_15644_p2) & ~(1'b0 == or_cond89_fu_15668_p2) & (1'b0 == or_cond90_fu_15692_p2)))) begin
ap_reg_phiprechg_a_winid_V_5_reg_1809pp0_it1 <= ap_const_lv5_16;
end else if (((~(1'b0 == tmp_294_5_fu_15626_p2) & (1'b0 == tmp_309_5_fu_15650_p2) & (1'b0 == or_cond89_fu_15668_p2)) | ((1'b0 == tmp_309_5_fu_15650_p2) & ~(1'b0 == or_cond88_fu_15644_p2) & (1'b0 == or_cond89_fu_15668_p2)))) begin
ap_reg_phiprechg_a_winid_V_5_reg_1809pp0_it1 <= ap_const_lv5_15;
end else if (((1'b0 == tmp_294_5_fu_15626_p2) & (1'b0 == or_cond88_fu_15644_p2))) begin
ap_reg_phiprechg_a_winid_V_5_reg_1809pp0_it1 <= ap_const_lv5_14;
end else if (((~(1'b0 == tmp_294_5_fu_15626_p2) & ~(1'b0 == tmp_309_5_fu_15650_p2) & ~(1'b0 == tmp_318_5_fu_15674_p2)) | (~(1'b0 == tmp_309_5_fu_15650_p2) & ~(1'b0 == tmp_318_5_fu_15674_p2) & ~(1'b0 == or_cond88_fu_15644_p2)) | (~(1'b0 == tmp_294_5_fu_15626_p2) & ~(1'b0 == tmp_318_5_fu_15674_p2) & ~(1'b0 == or_cond89_fu_15668_p2)) | (~(1'b0 == tmp_294_5_fu_15626_p2) & ~(1'b0 == tmp_309_5_fu_15650_p2) & ~(1'b0 == or_cond90_fu_15692_p2)) | (~(1'b0 == tmp_318_5_fu_15674_p2) & ~(1'b0 == or_cond88_fu_15644_p2) & ~(1'b0 == or_cond89_fu_15668_p2)) | (~(1'b0 == tmp_309_5_fu_15650_p2) & ~(1'b0 == or_cond88_fu_15644_p2) & ~(1'b0 == or_cond90_fu_15692_p2)) | (~(1'b0 == tmp_294_5_fu_15626_p2) & ~(1'b0 == or_cond89_fu_15668_p2) & ~(1'b0 == or_cond90_fu_15692_p2)) | (~(1'b0 == or_cond88_fu_15644_p2) & ~(1'b0 == or_cond89_fu_15668_p2) & ~(1'b0 == or_cond90_fu_15692_p2)))) begin
ap_reg_phiprechg_a_winid_V_5_reg_1809pp0_it1 <= ap_const_lv5_17;
end else if ((1'b1 == 1'b1)) begin
ap_reg_phiprechg_a_winid_V_5_reg_1809pp0_it1 <= ap_reg_phiprechg_a_winid_V_5_reg_1809pp0_it0;
end
end
always @ (posedge ap_clk) begin
if (((~(1'b0 == tmp_294_6_fu_15698_p2) & ~(1'b0 == tmp_309_6_fu_15722_p2) & (1'b0 == tmp_318_6_fu_15746_p2) & (1'b0 == or_cond93_fu_15764_p2)) | (~(1'b0 == tmp_309_6_fu_15722_p2) & (1'b0 == tmp_318_6_fu_15746_p2) & ~(1'b0 == or_cond91_fu_15716_p2) & (1'b0 == or_cond93_fu_15764_p2)) | (~(1'b0 == tmp_294_6_fu_15698_p2) & (1'b0 == tmp_318_6_fu_15746_p2) & ~(1'b0 == or_cond92_fu_15740_p2) & (1'b0 == or_cond93_fu_15764_p2)) | ((1'b0 == tmp_318_6_fu_15746_p2) & ~(1'b0 == or_cond91_fu_15716_p2) & ~(1'b0 == or_cond92_fu_15740_p2) & (1'b0 == or_cond93_fu_15764_p2)))) begin
ap_reg_phiprechg_a_winid_V_6_reg_1934pp0_it1 <= ap_const_lv4_A;
end else if (((~(1'b0 == tmp_294_6_fu_15698_p2) & (1'b0 == tmp_309_6_fu_15722_p2) & (1'b0 == or_cond92_fu_15740_p2)) | ((1'b0 == tmp_309_6_fu_15722_p2) & ~(1'b0 == or_cond91_fu_15716_p2) & (1'b0 == or_cond92_fu_15740_p2)))) begin
ap_reg_phiprechg_a_winid_V_6_reg_1934pp0_it1 <= ap_const_lv4_9;
end else if (((1'b0 == tmp_294_6_fu_15698_p2) & (1'b0 == or_cond91_fu_15716_p2))) begin
ap_reg_phiprechg_a_winid_V_6_reg_1934pp0_it1 <= ap_const_lv4_8;
end else if (((~(1'b0 == tmp_294_6_fu_15698_p2) & ~(1'b0 == tmp_309_6_fu_15722_p2) & ~(1'b0 == tmp_318_6_fu_15746_p2)) | (~(1'b0 == tmp_309_6_fu_15722_p2) & ~(1'b0 == tmp_318_6_fu_15746_p2) & ~(1'b0 == or_cond91_fu_15716_p2)) | (~(1'b0 == tmp_294_6_fu_15698_p2) & ~(1'b0 == tmp_318_6_fu_15746_p2) & ~(1'b0 == or_cond92_fu_15740_p2)) | (~(1'b0 == tmp_294_6_fu_15698_p2) & ~(1'b0 == tmp_309_6_fu_15722_p2) & ~(1'b0 == or_cond93_fu_15764_p2)) | (~(1'b0 == tmp_318_6_fu_15746_p2) & ~(1'b0 == or_cond91_fu_15716_p2) & ~(1'b0 == or_cond92_fu_15740_p2)) | (~(1'b0 == tmp_309_6_fu_15722_p2) & ~(1'b0 == or_cond91_fu_15716_p2) & ~(1'b0 == or_cond93_fu_15764_p2)) | (~(1'b0 == tmp_294_6_fu_15698_p2) & ~(1'b0 == or_cond92_fu_15740_p2) & ~(1'b0 == or_cond93_fu_15764_p2)) | (~(1'b0 == or_cond91_fu_15716_p2) & ~(1'b0 == or_cond92_fu_15740_p2) & ~(1'b0 == or_cond93_fu_15764_p2)))) begin
ap_reg_phiprechg_a_winid_V_6_reg_1934pp0_it1 <= ap_const_lv4_B;
end else if ((1'b1 == 1'b1)) begin
ap_reg_phiprechg_a_winid_V_6_reg_1934pp0_it1 <= ap_reg_phiprechg_a_winid_V_6_reg_1934pp0_it0;
end
end
always @ (posedge ap_clk) begin
if (((~(1'b0 == tmp_294_7_fu_15770_p2) & ~(1'b0 == tmp_309_7_fu_15794_p2) & (1'b0 == tmp_318_7_fu_15818_p2) & (1'b0 == or_cond96_fu_15836_p2)) | (~(1'b0 == tmp_309_7_fu_15794_p2) & (1'b0 == tmp_318_7_fu_15818_p2) & ~(1'b0 == or_cond94_fu_15788_p2) & (1'b0 == or_cond96_fu_15836_p2)) | (~(1'b0 == tmp_294_7_fu_15770_p2) & (1'b0 == tmp_318_7_fu_15818_p2) & ~(1'b0 == or_cond95_fu_15812_p2) & (1'b0 == or_cond96_fu_15836_p2)) | ((1'b0 == tmp_318_7_fu_15818_p2) & ~(1'b0 == or_cond94_fu_15788_p2) & ~(1'b0 == or_cond95_fu_15812_p2) & (1'b0 == or_cond96_fu_15836_p2)))) begin
ap_reg_phiprechg_a_winid_V_7_reg_2059pp0_it1 <= ap_const_lv3_6;
end else if (((~(1'b0 == tmp_294_7_fu_15770_p2) & (1'b0 == tmp_309_7_fu_15794_p2) & (1'b0 == or_cond95_fu_15812_p2)) | ((1'b0 == tmp_309_7_fu_15794_p2) & ~(1'b0 == or_cond94_fu_15788_p2) & (1'b0 == or_cond95_fu_15812_p2)))) begin
ap_reg_phiprechg_a_winid_V_7_reg_2059pp0_it1 <= ap_const_lv3_5;
end else if (((1'b0 == tmp_294_7_fu_15770_p2) & (1'b0 == or_cond94_fu_15788_p2))) begin
ap_reg_phiprechg_a_winid_V_7_reg_2059pp0_it1 <= ap_const_lv3_4;
end else if (((~(1'b0 == tmp_294_7_fu_15770_p2) & ~(1'b0 == tmp_309_7_fu_15794_p2) & ~(1'b0 == tmp_318_7_fu_15818_p2)) | (~(1'b0 == tmp_309_7_fu_15794_p2) & ~(1'b0 == tmp_318_7_fu_15818_p2) & ~(1'b0 == or_cond94_fu_15788_p2)) | (~(1'b0 == tmp_294_7_fu_15770_p2) & ~(1'b0 == tmp_318_7_fu_15818_p2) & ~(1'b0 == or_cond95_fu_15812_p2)) | (~(1'b0 == tmp_294_7_fu_15770_p2) & ~(1'b0 == tmp_309_7_fu_15794_p2) & ~(1'b0 == or_cond96_fu_15836_p2)) | (~(1'b0 == tmp_318_7_fu_15818_p2) & ~(1'b0 == or_cond94_fu_15788_p2) & ~(1'b0 == or_cond95_fu_15812_p2)) | (~(1'b0 == tmp_309_7_fu_15794_p2) & ~(1'b0 == or_cond94_fu_15788_p2) & ~(1'b0 == or_cond96_fu_15836_p2)) | (~(1'b0 == tmp_294_7_fu_15770_p2) & ~(1'b0 == or_cond95_fu_15812_p2) & ~(1'b0 == or_cond96_fu_15836_p2)) | (~(1'b0 == or_cond94_fu_15788_p2) & ~(1'b0 == or_cond95_fu_15812_p2) & ~(1'b0 == or_cond96_fu_15836_p2)))) begin
ap_reg_phiprechg_a_winid_V_7_reg_2059pp0_it1 <= ap_const_lv3_7;
end else if ((1'b1 == 1'b1)) begin
ap_reg_phiprechg_a_winid_V_7_reg_2059pp0_it1 <= ap_reg_phiprechg_a_winid_V_7_reg_2059pp0_it0;
end
end
always @ (posedge ap_clk) begin
if (((~(1'b0 == tmp_294_8_fu_15842_p2) & ~(1'b0 == tmp_309_8_fu_15866_p2) & (1'b0 == tmp_318_8_fu_15890_p2) & (1'b0 == or_cond99_fu_15908_p2)) | (~(1'b0 == tmp_309_8_fu_15866_p2) & (1'b0 == tmp_318_8_fu_15890_p2) & ~(1'b0 == or_cond97_fu_15860_p2) & (1'b0 == or_cond99_fu_15908_p2)) | (~(1'b0 == tmp_294_8_fu_15842_p2) & (1'b0 == tmp_318_8_fu_15890_p2) & ~(1'b0 == or_cond98_fu_15884_p2) & (1'b0 == or_cond99_fu_15908_p2)) | ((1'b0 == tmp_318_8_fu_15890_p2) & ~(1'b0 == or_cond97_fu_15860_p2) & ~(1'b0 == or_cond98_fu_15884_p2) & (1'b0 == or_cond99_fu_15908_p2)))) begin
ap_reg_phiprechg_a_winid_V_8_reg_2184pp0_it1 <= ap_const_lv6_22;
end else if (((~(1'b0 == tmp_294_8_fu_15842_p2) & (1'b0 == tmp_309_8_fu_15866_p2) & (1'b0 == or_cond98_fu_15884_p2)) | ((1'b0 == tmp_309_8_fu_15866_p2) & ~(1'b0 == or_cond97_fu_15860_p2) & (1'b0 == or_cond98_fu_15884_p2)))) begin
ap_reg_phiprechg_a_winid_V_8_reg_2184pp0_it1 <= ap_const_lv6_21;
end else if (((1'b0 == tmp_294_8_fu_15842_p2) & (1'b0 == or_cond97_fu_15860_p2))) begin
ap_reg_phiprechg_a_winid_V_8_reg_2184pp0_it1 <= ap_const_lv6_20;
end else if (((~(1'b0 == tmp_294_8_fu_15842_p2) & ~(1'b0 == tmp_309_8_fu_15866_p2) & ~(1'b0 == tmp_318_8_fu_15890_p2)) | (~(1'b0 == tmp_309_8_fu_15866_p2) & ~(1'b0 == tmp_318_8_fu_15890_p2) & ~(1'b0 == or_cond97_fu_15860_p2)) | (~(1'b0 == tmp_294_8_fu_15842_p2) & ~(1'b0 == tmp_318_8_fu_15890_p2) & ~(1'b0 == or_cond98_fu_15884_p2)) | (~(1'b0 == tmp_294_8_fu_15842_p2) & ~(1'b0 == tmp_309_8_fu_15866_p2) & ~(1'b0 == or_cond99_fu_15908_p2)) | (~(1'b0 == tmp_318_8_fu_15890_p2) & ~(1'b0 == or_cond97_fu_15860_p2) & ~(1'b0 == or_cond98_fu_15884_p2)) | (~(1'b0 == tmp_309_8_fu_15866_p2) & ~(1'b0 == or_cond97_fu_15860_p2) & ~(1'b0 == or_cond99_fu_15908_p2)) | (~(1'b0 == tmp_294_8_fu_15842_p2) & ~(1'b0 == or_cond98_fu_15884_p2) & ~(1'b0 == or_cond99_fu_15908_p2)) | (~(1'b0 == or_cond97_fu_15860_p2) & ~(1'b0 == or_cond98_fu_15884_p2) & ~(1'b0 == or_cond99_fu_15908_p2)))) begin
ap_reg_phiprechg_a_winid_V_8_reg_2184pp0_it1 <= ap_const_lv6_23;
end else if ((1'b1 == 1'b1)) begin
ap_reg_phiprechg_a_winid_V_8_reg_2184pp0_it1 <= ap_reg_phiprechg_a_winid_V_8_reg_2184pp0_it0;
end
end
always @ (posedge ap_clk) begin
if (((~(1'b0 == tmp_294_9_fu_15914_p2) & ~(1'b0 == tmp_309_9_fu_15938_p2) & (1'b0 == tmp_318_9_fu_15962_p2) & (1'b0 == or_cond102_fu_15980_p2)) | (~(1'b0 == tmp_309_9_fu_15938_p2) & (1'b0 == tmp_318_9_fu_15962_p2) & ~(1'b0 == or_cond100_fu_15932_p2) & (1'b0 == or_cond102_fu_15980_p2)) | (~(1'b0 == tmp_294_9_fu_15914_p2) & (1'b0 == tmp_318_9_fu_15962_p2) & ~(1'b0 == or_cond101_fu_15956_p2) & (1'b0 == or_cond102_fu_15980_p2)) | ((1'b0 == tmp_318_9_fu_15962_p2) & ~(1'b0 == or_cond100_fu_15932_p2) & ~(1'b0 == or_cond101_fu_15956_p2) & (1'b0 == or_cond102_fu_15980_p2)))) begin
ap_reg_phiprechg_a_winid_V_9_reg_2402pp0_it1 <= ap_const_lv6_26;
end else if (((~(1'b0 == tmp_294_9_fu_15914_p2) & (1'b0 == tmp_309_9_fu_15938_p2) & (1'b0 == or_cond101_fu_15956_p2)) | ((1'b0 == tmp_309_9_fu_15938_p2) & ~(1'b0 == or_cond100_fu_15932_p2) & (1'b0 == or_cond101_fu_15956_p2)))) begin
ap_reg_phiprechg_a_winid_V_9_reg_2402pp0_it1 <= ap_const_lv6_25;
end else if (((1'b0 == tmp_294_9_fu_15914_p2) & (1'b0 == or_cond100_fu_15932_p2))) begin
ap_reg_phiprechg_a_winid_V_9_reg_2402pp0_it1 <= ap_const_lv6_24;
end else if (((~(1'b0 == tmp_294_9_fu_15914_p2) & ~(1'b0 == tmp_309_9_fu_15938_p2) & ~(1'b0 == tmp_318_9_fu_15962_p2)) | (~(1'b0 == tmp_309_9_fu_15938_p2) & ~(1'b0 == tmp_318_9_fu_15962_p2) & ~(1'b0 == or_cond100_fu_15932_p2)) | (~(1'b0 == tmp_294_9_fu_15914_p2) & ~(1'b0 == tmp_318_9_fu_15962_p2) & ~(1'b0 == or_cond101_fu_15956_p2)) | (~(1'b0 == tmp_294_9_fu_15914_p2) & ~(1'b0 == tmp_309_9_fu_15938_p2) & ~(1'b0 == or_cond102_fu_15980_p2)) | (~(1'b0 == tmp_318_9_fu_15962_p2) & ~(1'b0 == or_cond100_fu_15932_p2) & ~(1'b0 == or_cond101_fu_15956_p2)) | (~(1'b0 == tmp_309_9_fu_15938_p2) & ~(1'b0 == or_cond100_fu_15932_p2) & ~(1'b0 == or_cond102_fu_15980_p2)) | (~(1'b0 == tmp_294_9_fu_15914_p2) & ~(1'b0 == or_cond101_fu_15956_p2) & ~(1'b0 == or_cond102_fu_15980_p2)) | (~(1'b0 == or_cond100_fu_15932_p2) & ~(1'b0 == or_cond101_fu_15956_p2) & ~(1'b0 == or_cond102_fu_15980_p2)))) begin
ap_reg_phiprechg_a_winid_V_9_reg_2402pp0_it1 <= ap_const_lv6_27;
end else if ((1'b1 == 1'b1)) begin
ap_reg_phiprechg_a_winid_V_9_reg_2402pp0_it1 <= ap_reg_phiprechg_a_winid_V_9_reg_2402pp0_it0;
end
end
always @ (posedge ap_clk) begin
if (((~(1'b0 == tmp_294_1_fu_15338_p2) & ~(1'b0 == tmp_309_1_fu_15362_p2) & (1'b0 == tmp_318_1_fu_15386_p2) & (1'b0 == or_cond65_fu_15404_p2)) | (~(1'b0 == tmp_309_1_fu_15362_p2) & (1'b0 == tmp_318_1_fu_15386_p2) & ~(1'b0 == or_cond61_fu_15356_p2) & (1'b0 == or_cond65_fu_15404_p2)) | (~(1'b0 == tmp_294_1_fu_15338_p2) & (1'b0 == tmp_318_1_fu_15386_p2) & ~(1'b0 == or_cond63_fu_15380_p2) & (1'b0 == or_cond65_fu_15404_p2)) | ((1'b0 == tmp_318_1_fu_15386_p2) & ~(1'b0 == or_cond61_fu_15356_p2) & ~(1'b0 == or_cond63_fu_15380_p2) & (1'b0 == or_cond65_fu_15404_p2)))) begin
ap_reg_phiprechg_a_winid_V_s_reg_1535pp0_it1 <= ap_const_lv3_6;
end else if (((~(1'b0 == tmp_294_1_fu_15338_p2) & (1'b0 == tmp_309_1_fu_15362_p2) & (1'b0 == or_cond63_fu_15380_p2)) | ((1'b0 == tmp_309_1_fu_15362_p2) & ~(1'b0 == or_cond61_fu_15356_p2) & (1'b0 == or_cond63_fu_15380_p2)))) begin
ap_reg_phiprechg_a_winid_V_s_reg_1535pp0_it1 <= ap_const_lv3_5;
end else if (((1'b0 == tmp_294_1_fu_15338_p2) & (1'b0 == or_cond61_fu_15356_p2))) begin
ap_reg_phiprechg_a_winid_V_s_reg_1535pp0_it1 <= ap_const_lv3_4;
end else if (((~(1'b0 == tmp_294_1_fu_15338_p2) & ~(1'b0 == tmp_309_1_fu_15362_p2) & ~(1'b0 == tmp_318_1_fu_15386_p2)) | (~(1'b0 == tmp_309_1_fu_15362_p2) & ~(1'b0 == tmp_318_1_fu_15386_p2) & ~(1'b0 == or_cond61_fu_15356_p2)) | (~(1'b0 == tmp_294_1_fu_15338_p2) & ~(1'b0 == tmp_318_1_fu_15386_p2) & ~(1'b0 == or_cond63_fu_15380_p2)) | (~(1'b0 == tmp_294_1_fu_15338_p2) & ~(1'b0 == tmp_309_1_fu_15362_p2) & ~(1'b0 == or_cond65_fu_15404_p2)) | (~(1'b0 == tmp_318_1_fu_15386_p2) & ~(1'b0 == or_cond61_fu_15356_p2) & ~(1'b0 == or_cond63_fu_15380_p2)) | (~(1'b0 == tmp_309_1_fu_15362_p2) & ~(1'b0 == or_cond61_fu_15356_p2) & ~(1'b0 == or_cond65_fu_15404_p2)) | (~(1'b0 == tmp_294_1_fu_15338_p2) & ~(1'b0 == or_cond63_fu_15380_p2) & ~(1'b0 == or_cond65_fu_15404_p2)) | (~(1'b0 == or_cond61_fu_15356_p2) & ~(1'b0 == or_cond63_fu_15380_p2) & ~(1'b0 == or_cond65_fu_15404_p2)))) begin
ap_reg_phiprechg_a_winid_V_s_reg_1535pp0_it1 <= ap_const_lv3_7;
end else if ((1'b1 == 1'b1)) begin
ap_reg_phiprechg_a_winid_V_s_reg_1535pp0_it1 <= ap_reg_phiprechg_a_winid_V_s_reg_1535pp0_it0;
end
end
always @ (posedge ap_clk) begin
if (~(1'b1 == 1'b1)) begin
ap_reg_phiprechg_ranki_l1_0_V_reg_1497pp0_it1 <= ap_const_lv3_7;
end else if ((newSel13_fu_15330_p3 == ap_const_lv2_3)) begin
ap_reg_phiprechg_ranki_l1_0_V_reg_1497pp0_it1 <= ap_const_lv3_3;
end else if ((newSel13_fu_15330_p3 == ap_const_lv2_2)) begin
ap_reg_phiprechg_ranki_l1_0_V_reg_1497pp0_it1 <= ap_const_lv3_2;
end else if ((newSel13_fu_15330_p3 == ap_const_lv2_1)) begin
ap_reg_phiprechg_ranki_l1_0_V_reg_1497pp0_it1 <= ap_const_lv3_1;
end else if ((newSel13_fu_15330_p3 == ap_const_lv2_0)) begin
ap_reg_phiprechg_ranki_l1_0_V_reg_1497pp0_it1 <= ap_const_lv3_0;
end else if ((1'b1 == 1'b1)) begin
ap_reg_phiprechg_ranki_l1_0_V_reg_1497pp0_it1 <= ap_reg_phiprechg_ranki_l1_0_V_reg_1497pp0_it0;
end
end
always @ (posedge ap_clk) begin
if (((~(1'b0 == tmp_294_1_fu_15338_p2) & ~(1'b0 == tmp_309_1_fu_15362_p2) & (1'b0 == tmp_318_1_fu_15386_p2) & (1'b0 == or_cond65_fu_15404_p2)) | (~(1'b0 == tmp_309_1_fu_15362_p2) & (1'b0 == tmp_318_1_fu_15386_p2) & ~(1'b0 == or_cond61_fu_15356_p2) & (1'b0 == or_cond65_fu_15404_p2)) | (~(1'b0 == tmp_294_1_fu_15338_p2) & (1'b0 == tmp_318_1_fu_15386_p2) & ~(1'b0 == or_cond63_fu_15380_p2) & (1'b0 == or_cond65_fu_15404_p2)) | ((1'b0 == tmp_318_1_fu_15386_p2) & ~(1'b0 == or_cond61_fu_15356_p2) & ~(1'b0 == or_cond63_fu_15380_p2) & (1'b0 == or_cond65_fu_15404_p2)))) begin
ap_reg_phiprechg_win_l1_V_load_4_reg_1522pp0_it1 <= call_ret_sp_sort_fu_14608_ap_return_8;
end else if (((~(1'b0 == tmp_294_1_fu_15338_p2) & (1'b0 == tmp_309_1_fu_15362_p2) & (1'b0 == or_cond63_fu_15380_p2)) | ((1'b0 == tmp_309_1_fu_15362_p2) & ~(1'b0 == or_cond61_fu_15356_p2) & (1'b0 == or_cond63_fu_15380_p2)))) begin
ap_reg_phiprechg_win_l1_V_load_4_reg_1522pp0_it1 <= call_ret_sp_sort_fu_14608_ap_return_7;
end else if (((1'b0 == tmp_294_1_fu_15338_p2) & (1'b0 == or_cond61_fu_15356_p2))) begin
ap_reg_phiprechg_win_l1_V_load_4_reg_1522pp0_it1 <= call_ret_sp_sort_fu_14608_ap_return_6;
end else if (((~(1'b0 == tmp_294_1_fu_15338_p2) & ~(1'b0 == tmp_309_1_fu_15362_p2) & ~(1'b0 == tmp_318_1_fu_15386_p2)) | (~(1'b0 == tmp_309_1_fu_15362_p2) & ~(1'b0 == tmp_318_1_fu_15386_p2) & ~(1'b0 == or_cond61_fu_15356_p2)) | (~(1'b0 == tmp_294_1_fu_15338_p2) & ~(1'b0 == tmp_318_1_fu_15386_p2) & ~(1'b0 == or_cond63_fu_15380_p2)) | (~(1'b0 == tmp_294_1_fu_15338_p2) & ~(1'b0 == tmp_309_1_fu_15362_p2) & ~(1'b0 == or_cond65_fu_15404_p2)) | (~(1'b0 == tmp_318_1_fu_15386_p2) & ~(1'b0 == or_cond61_fu_15356_p2) & ~(1'b0 == or_cond63_fu_15380_p2)) | (~(1'b0 == tmp_309_1_fu_15362_p2) & ~(1'b0 == or_cond61_fu_15356_p2) & ~(1'b0 == or_cond65_fu_15404_p2)) | (~(1'b0 == tmp_294_1_fu_15338_p2) & ~(1'b0 == or_cond63_fu_15380_p2) & ~(1'b0 == or_cond65_fu_15404_p2)) | (~(1'b0 == or_cond61_fu_15356_p2) & ~(1'b0 == or_cond63_fu_15380_p2) & ~(1'b0 == or_cond65_fu_15404_p2)))) begin
ap_reg_phiprechg_win_l1_V_load_4_reg_1522pp0_it1 <= call_ret_sp_sort_fu_14608_ap_return_9;
end else if ((1'b1 == 1'b1)) begin
ap_reg_phiprechg_win_l1_V_load_4_reg_1522pp0_it1 <= ap_reg_phiprechg_win_l1_V_load_4_reg_1522pp0_it0;
end
end
always @ (posedge ap_clk) begin
if (((~(1'b0 == tmp_294_2_fu_15410_p2) & ~(1'b0 == tmp_309_2_fu_15434_p2) & (1'b0 == tmp_318_2_fu_15458_p2) & (1'b0 == or_cond78_fu_15476_p2)) | (~(1'b0 == tmp_309_2_fu_15434_p2) & (1'b0 == tmp_318_2_fu_15458_p2) & ~(1'b0 == or_cond72_fu_15428_p2) & (1'b0 == or_cond78_fu_15476_p2)) | (~(1'b0 == tmp_294_2_fu_15410_p2) & (1'b0 == tmp_318_2_fu_15458_p2) & ~(1'b0 == or_cond75_fu_15452_p2) & (1'b0 == or_cond78_fu_15476_p2)) | ((1'b0 == tmp_318_2_fu_15458_p2) & ~(1'b0 == or_cond72_fu_15428_p2) & ~(1'b0 == or_cond75_fu_15452_p2) & (1'b0 == or_cond78_fu_15476_p2)))) begin
ap_reg_phiprechg_win_l1_V_load_5_reg_1576pp0_it1 <= call_ret_sp_sort_fu_14608_ap_return_12;
end else if (((~(1'b0 == tmp_294_2_fu_15410_p2) & (1'b0 == tmp_309_2_fu_15434_p2) & (1'b0 == or_cond75_fu_15452_p2)) | ((1'b0 == tmp_309_2_fu_15434_p2) & ~(1'b0 == or_cond72_fu_15428_p2) & (1'b0 == or_cond75_fu_15452_p2)))) begin
ap_reg_phiprechg_win_l1_V_load_5_reg_1576pp0_it1 <= call_ret_sp_sort_fu_14608_ap_return_11;
end else if (((1'b0 == tmp_294_2_fu_15410_p2) & (1'b0 == or_cond72_fu_15428_p2))) begin
ap_reg_phiprechg_win_l1_V_load_5_reg_1576pp0_it1 <= call_ret_sp_sort_fu_14608_ap_return_10;
end else if (((~(1'b0 == tmp_294_2_fu_15410_p2) & ~(1'b0 == tmp_309_2_fu_15434_p2) & ~(1'b0 == tmp_318_2_fu_15458_p2)) | (~(1'b0 == tmp_309_2_fu_15434_p2) & ~(1'b0 == tmp_318_2_fu_15458_p2) & ~(1'b0 == or_cond72_fu_15428_p2)) | (~(1'b0 == tmp_294_2_fu_15410_p2) & ~(1'b0 == tmp_318_2_fu_15458_p2) & ~(1'b0 == or_cond75_fu_15452_p2)) | (~(1'b0 == tmp_294_2_fu_15410_p2) & ~(1'b0 == tmp_309_2_fu_15434_p2) & ~(1'b0 == or_cond78_fu_15476_p2)) | (~(1'b0 == tmp_318_2_fu_15458_p2) & ~(1'b0 == or_cond72_fu_15428_p2) & ~(1'b0 == or_cond75_fu_15452_p2)) | (~(1'b0 == tmp_309_2_fu_15434_p2) & ~(1'b0 == or_cond72_fu_15428_p2) & ~(1'b0 == or_cond78_fu_15476_p2)) | (~(1'b0 == tmp_294_2_fu_15410_p2) & ~(1'b0 == or_cond75_fu_15452_p2) & ~(1'b0 == or_cond78_fu_15476_p2)) | (~(1'b0 == or_cond72_fu_15428_p2) & ~(1'b0 == or_cond75_fu_15452_p2) & ~(1'b0 == or_cond78_fu_15476_p2)))) begin
ap_reg_phiprechg_win_l1_V_load_5_reg_1576pp0_it1 <= call_ret_sp_sort_fu_14608_ap_return_13;
end else if ((1'b1 == 1'b1)) begin
ap_reg_phiprechg_win_l1_V_load_5_reg_1576pp0_it1 <= ap_reg_phiprechg_win_l1_V_load_5_reg_1576pp0_it0;
end
end
always @ (posedge ap_clk) begin
if (((~(1'b0 == tmp_294_3_fu_15482_p2) & ~(1'b0 == tmp_309_3_fu_15506_p2) & (1'b0 == tmp_318_3_fu_15530_p2) & (1'b0 == or_cond83_fu_15548_p2)) | (~(1'b0 == tmp_309_3_fu_15506_p2) & (1'b0 == tmp_318_3_fu_15530_p2) & ~(1'b0 == or_cond79_fu_15500_p2) & (1'b0 == or_cond83_fu_15548_p2)) | (~(1'b0 == tmp_294_3_fu_15482_p2) & (1'b0 == tmp_318_3_fu_15530_p2) & ~(1'b0 == or_cond81_fu_15524_p2) & (1'b0 == or_cond83_fu_15548_p2)) | ((1'b0 == tmp_318_3_fu_15530_p2) & ~(1'b0 == or_cond79_fu_15500_p2) & ~(1'b0 == or_cond81_fu_15524_p2) & (1'b0 == or_cond83_fu_15548_p2)))) begin
ap_reg_phiprechg_win_l1_V_load_6_reg_1630pp0_it1 <= call_ret_sp_sort_fu_14608_ap_return_16;
end else if (((~(1'b0 == tmp_294_3_fu_15482_p2) & (1'b0 == tmp_309_3_fu_15506_p2) & (1'b0 == or_cond81_fu_15524_p2)) | ((1'b0 == tmp_309_3_fu_15506_p2) & ~(1'b0 == or_cond79_fu_15500_p2) & (1'b0 == or_cond81_fu_15524_p2)))) begin
ap_reg_phiprechg_win_l1_V_load_6_reg_1630pp0_it1 <= call_ret_sp_sort_fu_14608_ap_return_15;
end else if (((1'b0 == tmp_294_3_fu_15482_p2) & (1'b0 == or_cond79_fu_15500_p2))) begin
ap_reg_phiprechg_win_l1_V_load_6_reg_1630pp0_it1 <= call_ret_sp_sort_fu_14608_ap_return_14;
end else if (((~(1'b0 == tmp_294_3_fu_15482_p2) & ~(1'b0 == tmp_309_3_fu_15506_p2) & ~(1'b0 == tmp_318_3_fu_15530_p2)) | (~(1'b0 == tmp_309_3_fu_15506_p2) & ~(1'b0 == tmp_318_3_fu_15530_p2) & ~(1'b0 == or_cond79_fu_15500_p2)) | (~(1'b0 == tmp_294_3_fu_15482_p2) & ~(1'b0 == tmp_318_3_fu_15530_p2) & ~(1'b0 == or_cond81_fu_15524_p2)) | (~(1'b0 == tmp_294_3_fu_15482_p2) & ~(1'b0 == tmp_309_3_fu_15506_p2) & ~(1'b0 == or_cond83_fu_15548_p2)) | (~(1'b0 == tmp_318_3_fu_15530_p2) & ~(1'b0 == or_cond79_fu_15500_p2) & ~(1'b0 == or_cond81_fu_15524_p2)) | (~(1'b0 == tmp_309_3_fu_15506_p2) & ~(1'b0 == or_cond79_fu_15500_p2) & ~(1'b0 == or_cond83_fu_15548_p2)) | (~(1'b0 == tmp_294_3_fu_15482_p2) & ~(1'b0 == or_cond81_fu_15524_p2) & ~(1'b0 == or_cond83_fu_15548_p2)) | (~(1'b0 == or_cond79_fu_15500_p2) & ~(1'b0 == or_cond81_fu_15524_p2) & ~(1'b0 == or_cond83_fu_15548_p2)))) begin
ap_reg_phiprechg_win_l1_V_load_6_reg_1630pp0_it1 <= call_ret_sp_sort_fu_14608_ap_return_17;
end else if ((1'b1 == 1'b1)) begin
ap_reg_phiprechg_win_l1_V_load_6_reg_1630pp0_it1 <= ap_reg_phiprechg_win_l1_V_load_6_reg_1630pp0_it0;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == 1'b1)) begin
rank_ex_0_V_read_1_reg_19963 <= rank_ex_0_V_read;
rank_ex_100_V_read_1_reg_19663 <= rank_ex_100_V_read;
rank_ex_102_V_read_1_reg_19657 <= rank_ex_102_V_read;
rank_ex_104_V_read_1_reg_19651 <= rank_ex_104_V_read;
rank_ex_106_V_read_1_reg_19645 <= rank_ex_106_V_read;
rank_ex_108_V_read_1_reg_19639 <= rank_ex_108_V_read;
rank_ex_10_V_read_1_reg_19933 <= rank_ex_10_V_read;
rank_ex_110_V_read_1_reg_19633 <= rank_ex_110_V_read;
rank_ex_112_V_read_1_reg_19627 <= rank_ex_112_V_read;
rank_ex_114_V_read_1_reg_19621 <= rank_ex_114_V_read;
rank_ex_116_V_read_1_reg_19615 <= rank_ex_116_V_read;
rank_ex_118_V_read_1_reg_19609 <= rank_ex_118_V_read;
rank_ex_120_V_read_1_reg_19603 <= rank_ex_120_V_read;
rank_ex_12_V_read_1_reg_19927 <= rank_ex_12_V_read;
rank_ex_14_V_read_1_reg_19921 <= rank_ex_14_V_read;
rank_ex_16_V_read_1_reg_19915 <= rank_ex_16_V_read;
rank_ex_18_V_read_1_reg_19909 <= rank_ex_18_V_read;
rank_ex_20_V_read_1_reg_19903 <= rank_ex_20_V_read;
rank_ex_22_V_read_1_reg_19897 <= rank_ex_22_V_read;
rank_ex_24_V_read_1_reg_19891 <= rank_ex_24_V_read;
rank_ex_26_V_read_1_reg_19885 <= rank_ex_26_V_read;
rank_ex_28_V_read_1_reg_19879 <= rank_ex_28_V_read;
rank_ex_2_V_read_1_reg_19957 <= rank_ex_2_V_read;
rank_ex_30_V_read_1_reg_19873 <= rank_ex_30_V_read;
rank_ex_32_V_read_1_reg_19867 <= rank_ex_32_V_read;
rank_ex_34_V_read_1_reg_19861 <= rank_ex_34_V_read;
rank_ex_36_V_read_1_reg_19855 <= rank_ex_36_V_read;
rank_ex_38_V_read_1_reg_19849 <= rank_ex_38_V_read;
rank_ex_40_V_read_1_reg_19843 <= rank_ex_40_V_read;
rank_ex_42_V_read_1_reg_19837 <= rank_ex_42_V_read;
rank_ex_44_V_read_1_reg_19831 <= rank_ex_44_V_read;
rank_ex_46_V_read_1_reg_19825 <= rank_ex_46_V_read;
rank_ex_48_V_read_1_reg_19819 <= rank_ex_48_V_read;
rank_ex_4_V_read_1_reg_19951 <= rank_ex_4_V_read;
rank_ex_50_V_read_1_reg_19813 <= rank_ex_50_V_read;
rank_ex_52_V_read_1_reg_19807 <= rank_ex_52_V_read;
rank_ex_54_V_read_1_reg_19801 <= rank_ex_54_V_read;
rank_ex_56_V_read_1_reg_19795 <= rank_ex_56_V_read;
rank_ex_58_V_read_1_reg_19789 <= rank_ex_58_V_read;
rank_ex_60_V_read_1_reg_19783 <= rank_ex_60_V_read;
rank_ex_62_V_read_1_reg_19777 <= rank_ex_62_V_read;
rank_ex_64_V_read_1_reg_19771 <= rank_ex_64_V_read;
rank_ex_66_V_read_1_reg_19765 <= rank_ex_66_V_read;
rank_ex_68_V_read_1_reg_19759 <= rank_ex_68_V_read;
rank_ex_6_V_read_1_reg_19945 <= rank_ex_6_V_read;
rank_ex_70_V_read_1_reg_19753 <= rank_ex_70_V_read;
rank_ex_72_V_read_1_reg_19747 <= rank_ex_72_V_read;
rank_ex_74_V_read_1_reg_19741 <= rank_ex_74_V_read;
rank_ex_76_V_read_1_reg_19735 <= rank_ex_76_V_read;
rank_ex_78_V_read_1_reg_19729 <= rank_ex_78_V_read;
rank_ex_80_V_read_1_reg_19723 <= rank_ex_80_V_read;
rank_ex_82_V_read_1_reg_19717 <= rank_ex_82_V_read;
rank_ex_84_V_read_1_reg_19711 <= rank_ex_84_V_read;
rank_ex_86_V_read_1_reg_19705 <= rank_ex_86_V_read;
rank_ex_88_V_read_1_reg_19699 <= rank_ex_88_V_read;
rank_ex_8_V_read_1_reg_19939 <= rank_ex_8_V_read;
rank_ex_90_V_read_1_reg_19693 <= rank_ex_90_V_read;
rank_ex_92_V_read_1_reg_19687 <= rank_ex_92_V_read;
rank_ex_94_V_read_1_reg_19681 <= rank_ex_94_V_read;
rank_ex_96_V_read_1_reg_19675 <= rank_ex_96_V_read;
rank_ex_98_V_read_1_reg_19669 <= rank_ex_98_V_read;
sel_tmp2057_demorgan_reg_24343 <= sel_tmp2057_demorgan_fu_16412_p2;
sel_tmp2101_demorgan_reg_24369 <= sel_tmp2101_demorgan_fu_16568_p2;
sel_tmp2145_demorgan_reg_24395 <= sel_tmp2145_demorgan_fu_16724_p2;
sel_tmp49_reg_24348 <= sel_tmp49_fu_16438_p2;
sel_tmp55_reg_24353 <= sel_tmp55_fu_16488_p2;
sel_tmp58_reg_24374 <= sel_tmp58_fu_16594_p2;
sel_tmp64_reg_24379 <= sel_tmp64_fu_16644_p2;
sel_tmp67_reg_24400 <= sel_tmp67_fu_16750_p2;
sel_tmp73_reg_24405 <= sel_tmp73_fu_16800_p2;
temp_V_2_3_reg_24411 <= temp_V_2_3_fu_16806_p3;
win_l0_0_V_reg_19979 <= call_ret_sp_sort_fu_14608_ap_return_2;
win_l0_10_V_reg_20655 <= call_ret_sp_sort_fu_14608_ap_return_12;
win_l0_11_V_reg_20723 <= call_ret_sp_sort_fu_14608_ap_return_13;
win_l0_12_V_reg_20791 <= call_ret_sp_sort_fu_14608_ap_return_14;
win_l0_13_V_reg_20859 <= call_ret_sp_sort_fu_14608_ap_return_15;
win_l0_14_V_reg_20927 <= call_ret_sp_sort_fu_14608_ap_return_16;
win_l0_15_V_reg_20995 <= call_ret_sp_sort_fu_14608_ap_return_17;
win_l0_16_V_reg_21063 <= call_ret_sp_sort_fu_14608_ap_return_18;
win_l0_17_V_reg_21130 <= call_ret_sp_sort_fu_14608_ap_return_19;
win_l0_18_V_reg_21197 <= call_ret_sp_sort_fu_14608_ap_return_20;
win_l0_19_V_reg_21264 <= call_ret_sp_sort_fu_14608_ap_return_21;
win_l0_1_V_reg_20046 <= call_ret_sp_sort_fu_14608_ap_return_3;
win_l0_20_V_reg_21331 <= call_ret_sp_sort_fu_14608_ap_return_22;
win_l0_21_V_reg_21398 <= call_ret_sp_sort_fu_14608_ap_return_23;
win_l0_22_V_reg_21465 <= call_ret_sp_sort_fu_14608_ap_return_24;
win_l0_23_V_reg_21532 <= call_ret_sp_sort_fu_14608_ap_return_25;
win_l0_24_V_reg_21599 <= call_ret_sp_sort_fu_14608_ap_return_26;
win_l0_25_V_reg_21666 <= call_ret_sp_sort_fu_14608_ap_return_27;
win_l0_26_V_reg_21733 <= call_ret_sp_sort_fu_14608_ap_return_28;
win_l0_27_V_reg_21800 <= call_ret_sp_sort_fu_14608_ap_return_29;
win_l0_28_V_reg_21867 <= call_ret_sp_sort_fu_14608_ap_return_30;
win_l0_29_V_reg_21934 <= call_ret_sp_sort_fu_14608_ap_return_31;
win_l0_2_V_reg_20113 <= call_ret_sp_sort_fu_14608_ap_return_4;
win_l0_30_V_reg_22001 <= call_ret_sp_sort_fu_14608_ap_return_32;
win_l0_31_V_reg_22068 <= call_ret_sp_sort_fu_14608_ap_return_33;
win_l0_32_V_reg_22135 <= call_ret_sp_sort_fu_14608_ap_return_34;
win_l0_33_V_reg_22202 <= call_ret_sp_sort_fu_14608_ap_return_35;
win_l0_34_V_reg_22269 <= call_ret_sp_sort_fu_14608_ap_return_36;
win_l0_35_V_reg_22336 <= call_ret_sp_sort_fu_14608_ap_return_37;
win_l0_36_V_reg_22403 <= call_ret_sp_sort_fu_14608_ap_return_38;
win_l0_37_V_reg_22470 <= call_ret_sp_sort_fu_14608_ap_return_39;
win_l0_38_V_reg_22537 <= call_ret_sp_sort_fu_14608_ap_return_40;
win_l0_39_V_reg_22604 <= call_ret_sp_sort_fu_14608_ap_return_41;
win_l0_3_V_reg_20180 <= call_ret_sp_sort_fu_14608_ap_return_5;
win_l0_40_V_reg_22671 <= call_ret_sp_sort_fu_14608_ap_return_42;
win_l0_41_V_reg_22738 <= call_ret_sp_sort_fu_14608_ap_return_43;
win_l0_42_V_reg_22805 <= call_ret_sp_sort_fu_14608_ap_return_44;
win_l0_43_V_reg_22872 <= call_ret_sp_sort_fu_14608_ap_return_45;
win_l0_44_V_reg_22939 <= call_ret_sp_sort_fu_14608_ap_return_46;
win_l0_45_V_reg_23006 <= call_ret_sp_sort_fu_14608_ap_return_47;
win_l0_46_V_reg_23073 <= call_ret_sp_sort_fu_14608_ap_return_48;
win_l0_47_V_reg_23140 <= call_ret_sp_sort_fu_14608_ap_return_49;
win_l0_48_V_reg_23207 <= call_ret_sp_sort_fu_14608_ap_return_50;
win_l0_49_V_reg_23274 <= call_ret_sp_sort_fu_14608_ap_return_51;
win_l0_4_V_reg_20247 <= call_ret_sp_sort_fu_14608_ap_return_6;
win_l0_50_V_reg_23341 <= call_ret_sp_sort_fu_14608_ap_return_52;
win_l0_51_V_reg_23408 <= call_ret_sp_sort_fu_14608_ap_return_53;
win_l0_52_V_reg_23475 <= call_ret_sp_sort_fu_14608_ap_return_54;
win_l0_53_V_reg_23542 <= call_ret_sp_sort_fu_14608_ap_return_55;
win_l0_54_V_reg_23609 <= call_ret_sp_sort_fu_14608_ap_return_56;
win_l0_55_V_reg_23676 <= call_ret_sp_sort_fu_14608_ap_return_57;
win_l0_56_V_reg_23743 <= call_ret_sp_sort_fu_14608_ap_return_58;
win_l0_57_V_reg_23810 <= call_ret_sp_sort_fu_14608_ap_return_59;
win_l0_58_V_reg_23877 <= call_ret_sp_sort_fu_14608_ap_return_60;
win_l0_59_V_reg_23944 <= call_ret_sp_sort_fu_14608_ap_return_61;
win_l0_5_V_reg_20315 <= call_ret_sp_sort_fu_14608_ap_return_7;
win_l0_60_V_reg_24011 <= call_ret_sp_sort_fu_14608_ap_return_62;
win_l0_6_V_reg_20383 <= call_ret_sp_sort_fu_14608_ap_return_8;
win_l0_7_V_reg_20451 <= call_ret_sp_sort_fu_14608_ap_return_9;
win_l0_8_V_reg_20519 <= call_ret_sp_sort_fu_14608_ap_return_10;
win_l0_9_V_reg_20587 <= call_ret_sp_sort_fu_14608_ap_return_11;
win_l1_V_load_reg_24078 <= win_l1_V_load_fu_15300_p3;
win_l2_V_load_4_reg_24359 <= win_l2_V_load_4_fu_16494_p3;
win_l2_V_load_5_reg_24385 <= win_l2_V_load_5_fu_16650_p3;
winid_0_V_write_assign_reg_19974 <= call_ret_sp_sort_fu_14608_ap_return_1;
winner_0_V_write_assign_reg_19969 <= call_ret_sp_sort_fu_14608_ap_return_0;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_235_fu_18579_p2) & ~(1'b0 == tmp_238_fu_18603_p2) & (1'b0 == tmp_241_fu_18627_p2) & (1'b0 == or_cond69_fu_18645_p2)) | (~(1'b0 == tmp_238_fu_18603_p2) & (1'b0 == tmp_241_fu_18627_p2) & ~(1'b0 == or_cond67_fu_18597_p2) & (1'b0 == or_cond69_fu_18645_p2)) | (~(1'b0 == tmp_235_fu_18579_p2) & (1'b0 == tmp_241_fu_18627_p2) & ~(1'b0 == or_cond68_fu_18621_p2) & (1'b0 == or_cond69_fu_18645_p2)) | ((1'b0 == tmp_241_fu_18627_p2) & ~(1'b0 == or_cond67_fu_18597_p2) & ~(1'b0 == or_cond68_fu_18621_p2) & (1'b0 == or_cond69_fu_18645_p2)))) begin
a_winid_1_V_1_phi_fu_14458_p8 = ap_const_lv2_2;
end else if (((~(1'b0 == tmp_235_fu_18579_p2) & (1'b0 == tmp_238_fu_18603_p2) & (1'b0 == or_cond68_fu_18621_p2)) | ((1'b0 == tmp_238_fu_18603_p2) & ~(1'b0 == or_cond67_fu_18597_p2) & (1'b0 == or_cond68_fu_18621_p2)))) begin
a_winid_1_V_1_phi_fu_14458_p8 = ap_const_lv2_1;
end else if (((1'b0 == tmp_235_fu_18579_p2) & (1'b0 == or_cond67_fu_18597_p2))) begin
a_winid_1_V_1_phi_fu_14458_p8 = ap_const_lv2_0;
end else if (((~(1'b0 == tmp_235_fu_18579_p2) & ~(1'b0 == tmp_238_fu_18603_p2) & ~(1'b0 == tmp_241_fu_18627_p2)) | (~(1'b0 == tmp_238_fu_18603_p2) & ~(1'b0 == tmp_241_fu_18627_p2) & ~(1'b0 == or_cond67_fu_18597_p2)) | (~(1'b0 == tmp_235_fu_18579_p2) & ~(1'b0 == tmp_241_fu_18627_p2) & ~(1'b0 == or_cond68_fu_18621_p2)) | (~(1'b0 == tmp_235_fu_18579_p2) & ~(1'b0 == tmp_238_fu_18603_p2) & ~(1'b0 == or_cond69_fu_18645_p2)) | (~(1'b0 == tmp_241_fu_18627_p2) & ~(1'b0 == or_cond67_fu_18597_p2) & ~(1'b0 == or_cond68_fu_18621_p2)) | (~(1'b0 == tmp_238_fu_18603_p2) & ~(1'b0 == or_cond67_fu_18597_p2) & ~(1'b0 == or_cond69_fu_18645_p2)) | (~(1'b0 == tmp_235_fu_18579_p2) & ~(1'b0 == or_cond68_fu_18621_p2) & ~(1'b0 == or_cond69_fu_18645_p2)) | (~(1'b0 == or_cond67_fu_18597_p2) & ~(1'b0 == or_cond68_fu_18621_p2) & ~(1'b0 == or_cond69_fu_18645_p2)))) begin
a_winid_1_V_1_phi_fu_14458_p8 = ap_const_lv2_3;
end else begin
a_winid_1_V_1_phi_fu_14458_p8 = ap_reg_phiprechg_a_winid_1_V_1_reg_14455pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_217_fu_16910_p2) & ~(1'b0 == tmp_220_fu_16931_p2) & (1'b0 == tmp_223_fu_16954_p2) & (1'b0 == or_cond51_fu_16971_p2)) | (~(1'b0 == tmp_220_fu_16931_p2) & (1'b0 == tmp_223_fu_16954_p2) & ~(1'b0 == or_cond_85_fu_16925_p2) & (1'b0 == or_cond51_fu_16971_p2)) | (~(1'b0 == tmp_217_fu_16910_p2) & (1'b0 == tmp_223_fu_16954_p2) & ~(1'b0 == or_cond50_fu_16948_p2) & (1'b0 == or_cond51_fu_16971_p2)) | ((1'b0 == tmp_223_fu_16954_p2) & ~(1'b0 == or_cond_85_fu_16925_p2) & ~(1'b0 == or_cond50_fu_16948_p2) & (1'b0 == or_cond51_fu_16971_p2)))) begin
a_winid_1_V_phi_fu_3729_p8 = ap_const_lv2_2;
end else if (((~(1'b0 == tmp_217_fu_16910_p2) & (1'b0 == tmp_220_fu_16931_p2) & (1'b0 == or_cond50_fu_16948_p2)) | ((1'b0 == tmp_220_fu_16931_p2) & ~(1'b0 == or_cond_85_fu_16925_p2) & (1'b0 == or_cond50_fu_16948_p2)))) begin
a_winid_1_V_phi_fu_3729_p8 = ap_const_lv2_1;
end else if (((1'b0 == tmp_217_fu_16910_p2) & (1'b0 == or_cond_85_fu_16925_p2))) begin
a_winid_1_V_phi_fu_3729_p8 = ap_const_lv2_0;
end else if (((~(1'b0 == tmp_217_fu_16910_p2) & ~(1'b0 == tmp_220_fu_16931_p2) & ~(1'b0 == tmp_223_fu_16954_p2)) | (~(1'b0 == tmp_220_fu_16931_p2) & ~(1'b0 == tmp_223_fu_16954_p2) & ~(1'b0 == or_cond_85_fu_16925_p2)) | (~(1'b0 == tmp_217_fu_16910_p2) & ~(1'b0 == tmp_223_fu_16954_p2) & ~(1'b0 == or_cond50_fu_16948_p2)) | (~(1'b0 == tmp_217_fu_16910_p2) & ~(1'b0 == tmp_220_fu_16931_p2) & ~(1'b0 == or_cond51_fu_16971_p2)) | (~(1'b0 == tmp_223_fu_16954_p2) & ~(1'b0 == or_cond_85_fu_16925_p2) & ~(1'b0 == or_cond50_fu_16948_p2)) | (~(1'b0 == tmp_220_fu_16931_p2) & ~(1'b0 == or_cond_85_fu_16925_p2) & ~(1'b0 == or_cond51_fu_16971_p2)) | (~(1'b0 == tmp_217_fu_16910_p2) & ~(1'b0 == or_cond50_fu_16948_p2) & ~(1'b0 == or_cond51_fu_16971_p2)) | (~(1'b0 == or_cond_85_fu_16925_p2) & ~(1'b0 == or_cond50_fu_16948_p2) & ~(1'b0 == or_cond51_fu_16971_p2)))) begin
a_winid_1_V_phi_fu_3729_p8 = ap_const_lv2_3;
end else begin
a_winid_1_V_phi_fu_3729_p8 = ap_reg_phiprechg_a_winid_1_V_reg_3726pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_10_fu_18263_p2) & ~(1'b0 == tmp_366_10_fu_18287_p2) & (1'b0 == tmp_375_10_fu_18311_p2) & (1'b0 == or_cond153_fu_18329_p2)) | (~(1'b0 == tmp_366_10_fu_18287_p2) & (1'b0 == tmp_375_10_fu_18311_p2) & ~(1'b0 == or_cond151_fu_18281_p2) & (1'b0 == or_cond153_fu_18329_p2)) | (~(1'b0 == tmp_351_10_fu_18263_p2) & (1'b0 == tmp_375_10_fu_18311_p2) & ~(1'b0 == or_cond152_fu_18305_p2) & (1'b0 == or_cond153_fu_18329_p2)) | ((1'b0 == tmp_375_10_fu_18311_p2) & ~(1'b0 == or_cond151_fu_18281_p2) & ~(1'b0 == or_cond152_fu_18305_p2) & (1'b0 == or_cond153_fu_18329_p2)))) begin
a_winid_V_1_10_phi_fu_13534_p8 = ap_const_lv6_2E;
end else if (((~(1'b0 == tmp_351_10_fu_18263_p2) & (1'b0 == tmp_366_10_fu_18287_p2) & (1'b0 == or_cond152_fu_18305_p2)) | ((1'b0 == tmp_366_10_fu_18287_p2) & ~(1'b0 == or_cond151_fu_18281_p2) & (1'b0 == or_cond152_fu_18305_p2)))) begin
a_winid_V_1_10_phi_fu_13534_p8 = ap_const_lv6_2D;
end else if (((1'b0 == tmp_351_10_fu_18263_p2) & (1'b0 == or_cond151_fu_18281_p2))) begin
a_winid_V_1_10_phi_fu_13534_p8 = ap_const_lv6_2C;
end else if (((~(1'b0 == tmp_351_10_fu_18263_p2) & ~(1'b0 == tmp_366_10_fu_18287_p2) & ~(1'b0 == tmp_375_10_fu_18311_p2)) | (~(1'b0 == tmp_366_10_fu_18287_p2) & ~(1'b0 == tmp_375_10_fu_18311_p2) & ~(1'b0 == or_cond151_fu_18281_p2)) | (~(1'b0 == tmp_351_10_fu_18263_p2) & ~(1'b0 == tmp_375_10_fu_18311_p2) & ~(1'b0 == or_cond152_fu_18305_p2)) | (~(1'b0 == tmp_351_10_fu_18263_p2) & ~(1'b0 == tmp_366_10_fu_18287_p2) & ~(1'b0 == or_cond153_fu_18329_p2)) | (~(1'b0 == tmp_375_10_fu_18311_p2) & ~(1'b0 == or_cond151_fu_18281_p2) & ~(1'b0 == or_cond152_fu_18305_p2)) | (~(1'b0 == tmp_366_10_fu_18287_p2) & ~(1'b0 == or_cond151_fu_18281_p2) & ~(1'b0 == or_cond153_fu_18329_p2)) | (~(1'b0 == tmp_351_10_fu_18263_p2) & ~(1'b0 == or_cond152_fu_18305_p2) & ~(1'b0 == or_cond153_fu_18329_p2)) | (~(1'b0 == or_cond151_fu_18281_p2) & ~(1'b0 == or_cond152_fu_18305_p2) & ~(1'b0 == or_cond153_fu_18329_p2)))) begin
a_winid_V_1_10_phi_fu_13534_p8 = ap_const_lv6_2F;
end else begin
a_winid_V_1_10_phi_fu_13534_p8 = ap_reg_phiprechg_a_winid_V_1_10_reg_13531pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_11_fu_18339_p2) & ~(1'b0 == tmp_366_11_fu_18363_p2) & (1'b0 == tmp_375_11_fu_18387_p2) & (1'b0 == or_cond156_fu_18405_p2)) | (~(1'b0 == tmp_366_11_fu_18363_p2) & (1'b0 == tmp_375_11_fu_18387_p2) & ~(1'b0 == or_cond154_fu_18357_p2) & (1'b0 == or_cond156_fu_18405_p2)) | (~(1'b0 == tmp_351_11_fu_18339_p2) & (1'b0 == tmp_375_11_fu_18387_p2) & ~(1'b0 == or_cond155_fu_18381_p2) & (1'b0 == or_cond156_fu_18405_p2)) | ((1'b0 == tmp_375_11_fu_18387_p2) & ~(1'b0 == or_cond154_fu_18357_p2) & ~(1'b0 == or_cond155_fu_18381_p2) & (1'b0 == or_cond156_fu_18405_p2)))) begin
a_winid_V_1_11_phi_fu_13765_p8 = ap_const_lv5_12;
end else if (((~(1'b0 == tmp_351_11_fu_18339_p2) & (1'b0 == tmp_366_11_fu_18363_p2) & (1'b0 == or_cond155_fu_18381_p2)) | ((1'b0 == tmp_366_11_fu_18363_p2) & ~(1'b0 == or_cond154_fu_18357_p2) & (1'b0 == or_cond155_fu_18381_p2)))) begin
a_winid_V_1_11_phi_fu_13765_p8 = ap_const_lv5_11;
end else if (((1'b0 == tmp_351_11_fu_18339_p2) & (1'b0 == or_cond154_fu_18357_p2))) begin
a_winid_V_1_11_phi_fu_13765_p8 = ap_const_lv5_10;
end else if (((~(1'b0 == tmp_351_11_fu_18339_p2) & ~(1'b0 == tmp_366_11_fu_18363_p2) & ~(1'b0 == tmp_375_11_fu_18387_p2)) | (~(1'b0 == tmp_366_11_fu_18363_p2) & ~(1'b0 == tmp_375_11_fu_18387_p2) & ~(1'b0 == or_cond154_fu_18357_p2)) | (~(1'b0 == tmp_351_11_fu_18339_p2) & ~(1'b0 == tmp_375_11_fu_18387_p2) & ~(1'b0 == or_cond155_fu_18381_p2)) | (~(1'b0 == tmp_351_11_fu_18339_p2) & ~(1'b0 == tmp_366_11_fu_18363_p2) & ~(1'b0 == or_cond156_fu_18405_p2)) | (~(1'b0 == tmp_375_11_fu_18387_p2) & ~(1'b0 == or_cond154_fu_18357_p2) & ~(1'b0 == or_cond155_fu_18381_p2)) | (~(1'b0 == tmp_366_11_fu_18363_p2) & ~(1'b0 == or_cond154_fu_18357_p2) & ~(1'b0 == or_cond156_fu_18405_p2)) | (~(1'b0 == tmp_351_11_fu_18339_p2) & ~(1'b0 == or_cond155_fu_18381_p2) & ~(1'b0 == or_cond156_fu_18405_p2)) | (~(1'b0 == or_cond154_fu_18357_p2) & ~(1'b0 == or_cond155_fu_18381_p2) & ~(1'b0 == or_cond156_fu_18405_p2)))) begin
a_winid_V_1_11_phi_fu_13765_p8 = ap_const_lv5_13;
end else begin
a_winid_V_1_11_phi_fu_13765_p8 = ap_reg_phiprechg_a_winid_V_1_11_reg_13762pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_12_fu_18419_p2) & ~(1'b0 == tmp_366_12_fu_18443_p2) & (1'b0 == tmp_375_12_fu_18467_p2) & (1'b0 == or_cond159_fu_18485_p2)) | (~(1'b0 == tmp_366_12_fu_18443_p2) & (1'b0 == tmp_375_12_fu_18467_p2) & ~(1'b0 == or_cond157_fu_18437_p2) & (1'b0 == or_cond159_fu_18485_p2)) | (~(1'b0 == tmp_351_12_fu_18419_p2) & (1'b0 == tmp_375_12_fu_18467_p2) & ~(1'b0 == or_cond158_fu_18461_p2) & (1'b0 == or_cond159_fu_18485_p2)) | ((1'b0 == tmp_375_12_fu_18467_p2) & ~(1'b0 == or_cond157_fu_18437_p2) & ~(1'b0 == or_cond158_fu_18461_p2) & (1'b0 == or_cond159_fu_18485_p2)))) begin
a_winid_V_1_12_phi_fu_13996_p8 = ap_const_lv5_16;
end else if (((~(1'b0 == tmp_351_12_fu_18419_p2) & (1'b0 == tmp_366_12_fu_18443_p2) & (1'b0 == or_cond158_fu_18461_p2)) | ((1'b0 == tmp_366_12_fu_18443_p2) & ~(1'b0 == or_cond157_fu_18437_p2) & (1'b0 == or_cond158_fu_18461_p2)))) begin
a_winid_V_1_12_phi_fu_13996_p8 = ap_const_lv5_15;
end else if (((1'b0 == tmp_351_12_fu_18419_p2) & (1'b0 == or_cond157_fu_18437_p2))) begin
a_winid_V_1_12_phi_fu_13996_p8 = ap_const_lv5_14;
end else if (((~(1'b0 == tmp_351_12_fu_18419_p2) & ~(1'b0 == tmp_366_12_fu_18443_p2) & ~(1'b0 == tmp_375_12_fu_18467_p2)) | (~(1'b0 == tmp_366_12_fu_18443_p2) & ~(1'b0 == tmp_375_12_fu_18467_p2) & ~(1'b0 == or_cond157_fu_18437_p2)) | (~(1'b0 == tmp_351_12_fu_18419_p2) & ~(1'b0 == tmp_375_12_fu_18467_p2) & ~(1'b0 == or_cond158_fu_18461_p2)) | (~(1'b0 == tmp_351_12_fu_18419_p2) & ~(1'b0 == tmp_366_12_fu_18443_p2) & ~(1'b0 == or_cond159_fu_18485_p2)) | (~(1'b0 == tmp_375_12_fu_18467_p2) & ~(1'b0 == or_cond157_fu_18437_p2) & ~(1'b0 == or_cond158_fu_18461_p2)) | (~(1'b0 == tmp_366_12_fu_18443_p2) & ~(1'b0 == or_cond157_fu_18437_p2) & ~(1'b0 == or_cond159_fu_18485_p2)) | (~(1'b0 == tmp_351_12_fu_18419_p2) & ~(1'b0 == or_cond158_fu_18461_p2) & ~(1'b0 == or_cond159_fu_18485_p2)) | (~(1'b0 == or_cond157_fu_18437_p2) & ~(1'b0 == or_cond158_fu_18461_p2) & ~(1'b0 == or_cond159_fu_18485_p2)))) begin
a_winid_V_1_12_phi_fu_13996_p8 = ap_const_lv5_17;
end else begin
a_winid_V_1_12_phi_fu_13996_p8 = ap_reg_phiprechg_a_winid_V_1_12_reg_13993pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_13_fu_18499_p2) & ~(1'b0 == tmp_366_13_fu_18523_p2) & (1'b0 == tmp_375_13_fu_18547_p2) & (1'b0 == or_cond162_fu_18565_p2)) | (~(1'b0 == tmp_366_13_fu_18523_p2) & (1'b0 == tmp_375_13_fu_18547_p2) & ~(1'b0 == or_cond160_fu_18517_p2) & (1'b0 == or_cond162_fu_18565_p2)) | (~(1'b0 == tmp_351_13_fu_18499_p2) & (1'b0 == tmp_375_13_fu_18547_p2) & ~(1'b0 == or_cond161_fu_18541_p2) & (1'b0 == or_cond162_fu_18565_p2)) | ((1'b0 == tmp_375_13_fu_18547_p2) & ~(1'b0 == or_cond160_fu_18517_p2) & ~(1'b0 == or_cond161_fu_18541_p2) & (1'b0 == or_cond162_fu_18565_p2)))) begin
a_winid_V_1_13_phi_fu_14227_p8 = ap_const_lv4_A;
end else if (((~(1'b0 == tmp_351_13_fu_18499_p2) & (1'b0 == tmp_366_13_fu_18523_p2) & (1'b0 == or_cond161_fu_18541_p2)) | ((1'b0 == tmp_366_13_fu_18523_p2) & ~(1'b0 == or_cond160_fu_18517_p2) & (1'b0 == or_cond161_fu_18541_p2)))) begin
a_winid_V_1_13_phi_fu_14227_p8 = ap_const_lv4_9;
end else if (((1'b0 == tmp_351_13_fu_18499_p2) & (1'b0 == or_cond160_fu_18517_p2))) begin
a_winid_V_1_13_phi_fu_14227_p8 = ap_const_lv4_8;
end else if (((~(1'b0 == tmp_351_13_fu_18499_p2) & ~(1'b0 == tmp_366_13_fu_18523_p2) & ~(1'b0 == tmp_375_13_fu_18547_p2)) | (~(1'b0 == tmp_366_13_fu_18523_p2) & ~(1'b0 == tmp_375_13_fu_18547_p2) & ~(1'b0 == or_cond160_fu_18517_p2)) | (~(1'b0 == tmp_351_13_fu_18499_p2) & ~(1'b0 == tmp_375_13_fu_18547_p2) & ~(1'b0 == or_cond161_fu_18541_p2)) | (~(1'b0 == tmp_351_13_fu_18499_p2) & ~(1'b0 == tmp_366_13_fu_18523_p2) & ~(1'b0 == or_cond162_fu_18565_p2)) | (~(1'b0 == tmp_375_13_fu_18547_p2) & ~(1'b0 == or_cond160_fu_18517_p2) & ~(1'b0 == or_cond161_fu_18541_p2)) | (~(1'b0 == tmp_366_13_fu_18523_p2) & ~(1'b0 == or_cond160_fu_18517_p2) & ~(1'b0 == or_cond162_fu_18565_p2)) | (~(1'b0 == tmp_351_13_fu_18499_p2) & ~(1'b0 == or_cond161_fu_18541_p2) & ~(1'b0 == or_cond162_fu_18565_p2)) | (~(1'b0 == or_cond160_fu_18517_p2) & ~(1'b0 == or_cond161_fu_18541_p2) & ~(1'b0 == or_cond162_fu_18565_p2)))) begin
a_winid_V_1_13_phi_fu_14227_p8 = ap_const_lv4_B;
end else begin
a_winid_V_1_13_phi_fu_14227_p8 = ap_reg_phiprechg_a_winid_V_1_13_reg_14224pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_1_fu_17483_p2) & ~(1'b0 == tmp_366_1_fu_17507_p2) & (1'b0 == tmp_375_1_fu_17531_p2) & (1'b0 == or_cond123_fu_17549_p2)) | (~(1'b0 == tmp_366_1_fu_17507_p2) & (1'b0 == tmp_375_1_fu_17531_p2) & ~(1'b0 == or_cond121_fu_17501_p2) & (1'b0 == or_cond123_fu_17549_p2)) | (~(1'b0 == tmp_351_1_fu_17483_p2) & (1'b0 == tmp_375_1_fu_17531_p2) & ~(1'b0 == or_cond122_fu_17525_p2) & (1'b0 == or_cond123_fu_17549_p2)) | ((1'b0 == tmp_375_1_fu_17531_p2) & ~(1'b0 == or_cond121_fu_17501_p2) & ~(1'b0 == or_cond122_fu_17525_p2) & (1'b0 == or_cond123_fu_17549_p2)))) begin
a_winid_V_1_1_phi_fu_12127_p8 = ap_const_lv3_6;
end else if (((~(1'b0 == tmp_351_1_fu_17483_p2) & (1'b0 == tmp_366_1_fu_17507_p2) & (1'b0 == or_cond122_fu_17525_p2)) | ((1'b0 == tmp_366_1_fu_17507_p2) & ~(1'b0 == or_cond121_fu_17501_p2) & (1'b0 == or_cond122_fu_17525_p2)))) begin
a_winid_V_1_1_phi_fu_12127_p8 = ap_const_lv3_5;
end else if (((1'b0 == tmp_351_1_fu_17483_p2) & (1'b0 == or_cond121_fu_17501_p2))) begin
a_winid_V_1_1_phi_fu_12127_p8 = ap_const_lv3_4;
end else if (((~(1'b0 == tmp_351_1_fu_17483_p2) & ~(1'b0 == tmp_366_1_fu_17507_p2) & ~(1'b0 == tmp_375_1_fu_17531_p2)) | (~(1'b0 == tmp_366_1_fu_17507_p2) & ~(1'b0 == tmp_375_1_fu_17531_p2) & ~(1'b0 == or_cond121_fu_17501_p2)) | (~(1'b0 == tmp_351_1_fu_17483_p2) & ~(1'b0 == tmp_375_1_fu_17531_p2) & ~(1'b0 == or_cond122_fu_17525_p2)) | (~(1'b0 == tmp_351_1_fu_17483_p2) & ~(1'b0 == tmp_366_1_fu_17507_p2) & ~(1'b0 == or_cond123_fu_17549_p2)) | (~(1'b0 == tmp_375_1_fu_17531_p2) & ~(1'b0 == or_cond121_fu_17501_p2) & ~(1'b0 == or_cond122_fu_17525_p2)) | (~(1'b0 == tmp_366_1_fu_17507_p2) & ~(1'b0 == or_cond121_fu_17501_p2) & ~(1'b0 == or_cond123_fu_17549_p2)) | (~(1'b0 == tmp_351_1_fu_17483_p2) & ~(1'b0 == or_cond122_fu_17525_p2) & ~(1'b0 == or_cond123_fu_17549_p2)) | (~(1'b0 == or_cond121_fu_17501_p2) & ~(1'b0 == or_cond122_fu_17525_p2) & ~(1'b0 == or_cond123_fu_17549_p2)))) begin
a_winid_V_1_1_phi_fu_12127_p8 = ap_const_lv3_7;
end else begin
a_winid_V_1_1_phi_fu_12127_p8 = ap_reg_phiprechg_a_winid_V_1_1_reg_12124pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_2_fu_17563_p2) & ~(1'b0 == tmp_366_2_fu_17587_p2) & (1'b0 == tmp_375_2_fu_17611_p2) & (1'b0 == or_cond126_fu_17629_p2)) | (~(1'b0 == tmp_366_2_fu_17587_p2) & (1'b0 == tmp_375_2_fu_17611_p2) & ~(1'b0 == or_cond124_fu_17581_p2) & (1'b0 == or_cond126_fu_17629_p2)) | (~(1'b0 == tmp_351_2_fu_17563_p2) & (1'b0 == tmp_375_2_fu_17611_p2) & ~(1'b0 == or_cond125_fu_17605_p2) & (1'b0 == or_cond126_fu_17629_p2)) | ((1'b0 == tmp_375_2_fu_17611_p2) & ~(1'b0 == or_cond124_fu_17581_p2) & ~(1'b0 == or_cond125_fu_17605_p2) & (1'b0 == or_cond126_fu_17629_p2)))) begin
a_winid_V_1_2_phi_fu_12181_p8 = ap_const_lv4_A;
end else if (((~(1'b0 == tmp_351_2_fu_17563_p2) & (1'b0 == tmp_366_2_fu_17587_p2) & (1'b0 == or_cond125_fu_17605_p2)) | ((1'b0 == tmp_366_2_fu_17587_p2) & ~(1'b0 == or_cond124_fu_17581_p2) & (1'b0 == or_cond125_fu_17605_p2)))) begin
a_winid_V_1_2_phi_fu_12181_p8 = ap_const_lv4_9;
end else if (((1'b0 == tmp_351_2_fu_17563_p2) & (1'b0 == or_cond124_fu_17581_p2))) begin
a_winid_V_1_2_phi_fu_12181_p8 = ap_const_lv4_8;
end else if (((~(1'b0 == tmp_351_2_fu_17563_p2) & ~(1'b0 == tmp_366_2_fu_17587_p2) & ~(1'b0 == tmp_375_2_fu_17611_p2)) | (~(1'b0 == tmp_366_2_fu_17587_p2) & ~(1'b0 == tmp_375_2_fu_17611_p2) & ~(1'b0 == or_cond124_fu_17581_p2)) | (~(1'b0 == tmp_351_2_fu_17563_p2) & ~(1'b0 == tmp_375_2_fu_17611_p2) & ~(1'b0 == or_cond125_fu_17605_p2)) | (~(1'b0 == tmp_351_2_fu_17563_p2) & ~(1'b0 == tmp_366_2_fu_17587_p2) & ~(1'b0 == or_cond126_fu_17629_p2)) | (~(1'b0 == tmp_375_2_fu_17611_p2) & ~(1'b0 == or_cond124_fu_17581_p2) & ~(1'b0 == or_cond125_fu_17605_p2)) | (~(1'b0 == tmp_366_2_fu_17587_p2) & ~(1'b0 == or_cond124_fu_17581_p2) & ~(1'b0 == or_cond126_fu_17629_p2)) | (~(1'b0 == tmp_351_2_fu_17563_p2) & ~(1'b0 == or_cond125_fu_17605_p2) & ~(1'b0 == or_cond126_fu_17629_p2)) | (~(1'b0 == or_cond124_fu_17581_p2) & ~(1'b0 == or_cond125_fu_17605_p2) & ~(1'b0 == or_cond126_fu_17629_p2)))) begin
a_winid_V_1_2_phi_fu_12181_p8 = ap_const_lv4_B;
end else begin
a_winid_V_1_2_phi_fu_12181_p8 = ap_reg_phiprechg_a_winid_V_1_2_reg_12178pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_3_fu_17643_p2) & ~(1'b0 == tmp_366_3_fu_17667_p2) & (1'b0 == tmp_375_3_fu_17691_p2) & (1'b0 == or_cond129_fu_17709_p2)) | (~(1'b0 == tmp_366_3_fu_17667_p2) & (1'b0 == tmp_375_3_fu_17691_p2) & ~(1'b0 == or_cond127_fu_17661_p2) & (1'b0 == or_cond129_fu_17709_p2)) | (~(1'b0 == tmp_351_3_fu_17643_p2) & (1'b0 == tmp_375_3_fu_17691_p2) & ~(1'b0 == or_cond128_fu_17685_p2) & (1'b0 == or_cond129_fu_17709_p2)) | ((1'b0 == tmp_375_3_fu_17691_p2) & ~(1'b0 == or_cond127_fu_17661_p2) & ~(1'b0 == or_cond128_fu_17685_p2) & (1'b0 == or_cond129_fu_17709_p2)))) begin
a_winid_V_1_3_phi_fu_12235_p8 = ap_const_lv3_6;
end else if (((~(1'b0 == tmp_351_3_fu_17643_p2) & (1'b0 == tmp_366_3_fu_17667_p2) & (1'b0 == or_cond128_fu_17685_p2)) | ((1'b0 == tmp_366_3_fu_17667_p2) & ~(1'b0 == or_cond127_fu_17661_p2) & (1'b0 == or_cond128_fu_17685_p2)))) begin
a_winid_V_1_3_phi_fu_12235_p8 = ap_const_lv3_5;
end else if (((1'b0 == tmp_351_3_fu_17643_p2) & (1'b0 == or_cond127_fu_17661_p2))) begin
a_winid_V_1_3_phi_fu_12235_p8 = ap_const_lv3_4;
end else if (((~(1'b0 == tmp_351_3_fu_17643_p2) & ~(1'b0 == tmp_366_3_fu_17667_p2) & ~(1'b0 == tmp_375_3_fu_17691_p2)) | (~(1'b0 == tmp_366_3_fu_17667_p2) & ~(1'b0 == tmp_375_3_fu_17691_p2) & ~(1'b0 == or_cond127_fu_17661_p2)) | (~(1'b0 == tmp_351_3_fu_17643_p2) & ~(1'b0 == tmp_375_3_fu_17691_p2) & ~(1'b0 == or_cond128_fu_17685_p2)) | (~(1'b0 == tmp_351_3_fu_17643_p2) & ~(1'b0 == tmp_366_3_fu_17667_p2) & ~(1'b0 == or_cond129_fu_17709_p2)) | (~(1'b0 == tmp_375_3_fu_17691_p2) & ~(1'b0 == or_cond127_fu_17661_p2) & ~(1'b0 == or_cond128_fu_17685_p2)) | (~(1'b0 == tmp_366_3_fu_17667_p2) & ~(1'b0 == or_cond127_fu_17661_p2) & ~(1'b0 == or_cond129_fu_17709_p2)) | (~(1'b0 == tmp_351_3_fu_17643_p2) & ~(1'b0 == or_cond128_fu_17685_p2) & ~(1'b0 == or_cond129_fu_17709_p2)) | (~(1'b0 == or_cond127_fu_17661_p2) & ~(1'b0 == or_cond128_fu_17685_p2) & ~(1'b0 == or_cond129_fu_17709_p2)))) begin
a_winid_V_1_3_phi_fu_12235_p8 = ap_const_lv3_7;
end else begin
a_winid_V_1_3_phi_fu_12235_p8 = ap_reg_phiprechg_a_winid_V_1_3_reg_12232pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_4_fu_17723_p2) & ~(1'b0 == tmp_366_4_fu_17747_p2) & (1'b0 == tmp_375_4_fu_17771_p2) & (1'b0 == or_cond132_fu_17789_p2)) | (~(1'b0 == tmp_366_4_fu_17747_p2) & (1'b0 == tmp_375_4_fu_17771_p2) & ~(1'b0 == or_cond130_fu_17741_p2) & (1'b0 == or_cond132_fu_17789_p2)) | (~(1'b0 == tmp_351_4_fu_17723_p2) & (1'b0 == tmp_375_4_fu_17771_p2) & ~(1'b0 == or_cond131_fu_17765_p2) & (1'b0 == or_cond132_fu_17789_p2)) | ((1'b0 == tmp_375_4_fu_17771_p2) & ~(1'b0 == or_cond130_fu_17741_p2) & ~(1'b0 == or_cond131_fu_17765_p2) & (1'b0 == or_cond132_fu_17789_p2)))) begin
a_winid_V_1_4_phi_fu_12289_p8 = ap_const_lv5_12;
end else if (((~(1'b0 == tmp_351_4_fu_17723_p2) & (1'b0 == tmp_366_4_fu_17747_p2) & (1'b0 == or_cond131_fu_17765_p2)) | ((1'b0 == tmp_366_4_fu_17747_p2) & ~(1'b0 == or_cond130_fu_17741_p2) & (1'b0 == or_cond131_fu_17765_p2)))) begin
a_winid_V_1_4_phi_fu_12289_p8 = ap_const_lv5_11;
end else if (((1'b0 == tmp_351_4_fu_17723_p2) & (1'b0 == or_cond130_fu_17741_p2))) begin
a_winid_V_1_4_phi_fu_12289_p8 = ap_const_lv5_10;
end else if (((~(1'b0 == tmp_351_4_fu_17723_p2) & ~(1'b0 == tmp_366_4_fu_17747_p2) & ~(1'b0 == tmp_375_4_fu_17771_p2)) | (~(1'b0 == tmp_366_4_fu_17747_p2) & ~(1'b0 == tmp_375_4_fu_17771_p2) & ~(1'b0 == or_cond130_fu_17741_p2)) | (~(1'b0 == tmp_351_4_fu_17723_p2) & ~(1'b0 == tmp_375_4_fu_17771_p2) & ~(1'b0 == or_cond131_fu_17765_p2)) | (~(1'b0 == tmp_351_4_fu_17723_p2) & ~(1'b0 == tmp_366_4_fu_17747_p2) & ~(1'b0 == or_cond132_fu_17789_p2)) | (~(1'b0 == tmp_375_4_fu_17771_p2) & ~(1'b0 == or_cond130_fu_17741_p2) & ~(1'b0 == or_cond131_fu_17765_p2)) | (~(1'b0 == tmp_366_4_fu_17747_p2) & ~(1'b0 == or_cond130_fu_17741_p2) & ~(1'b0 == or_cond132_fu_17789_p2)) | (~(1'b0 == tmp_351_4_fu_17723_p2) & ~(1'b0 == or_cond131_fu_17765_p2) & ~(1'b0 == or_cond132_fu_17789_p2)) | (~(1'b0 == or_cond130_fu_17741_p2) & ~(1'b0 == or_cond131_fu_17765_p2) & ~(1'b0 == or_cond132_fu_17789_p2)))) begin
a_winid_V_1_4_phi_fu_12289_p8 = ap_const_lv5_13;
end else begin
a_winid_V_1_4_phi_fu_12289_p8 = ap_reg_phiprechg_a_winid_V_1_4_reg_12286pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_5_fu_17799_p2) & ~(1'b0 == tmp_366_5_fu_17823_p2) & (1'b0 == tmp_375_5_fu_17847_p2) & (1'b0 == or_cond135_fu_17865_p2)) | (~(1'b0 == tmp_366_5_fu_17823_p2) & (1'b0 == tmp_375_5_fu_17847_p2) & ~(1'b0 == or_cond133_fu_17817_p2) & (1'b0 == or_cond135_fu_17865_p2)) | (~(1'b0 == tmp_351_5_fu_17799_p2) & (1'b0 == tmp_375_5_fu_17847_p2) & ~(1'b0 == or_cond134_fu_17841_p2) & (1'b0 == or_cond135_fu_17865_p2)) | ((1'b0 == tmp_375_5_fu_17847_p2) & ~(1'b0 == or_cond133_fu_17817_p2) & ~(1'b0 == or_cond134_fu_17841_p2) & (1'b0 == or_cond135_fu_17865_p2)))) begin
a_winid_V_1_5_phi_fu_12427_p8 = ap_const_lv5_16;
end else if (((~(1'b0 == tmp_351_5_fu_17799_p2) & (1'b0 == tmp_366_5_fu_17823_p2) & (1'b0 == or_cond134_fu_17841_p2)) | ((1'b0 == tmp_366_5_fu_17823_p2) & ~(1'b0 == or_cond133_fu_17817_p2) & (1'b0 == or_cond134_fu_17841_p2)))) begin
a_winid_V_1_5_phi_fu_12427_p8 = ap_const_lv5_15;
end else if (((1'b0 == tmp_351_5_fu_17799_p2) & (1'b0 == or_cond133_fu_17817_p2))) begin
a_winid_V_1_5_phi_fu_12427_p8 = ap_const_lv5_14;
end else if (((~(1'b0 == tmp_351_5_fu_17799_p2) & ~(1'b0 == tmp_366_5_fu_17823_p2) & ~(1'b0 == tmp_375_5_fu_17847_p2)) | (~(1'b0 == tmp_366_5_fu_17823_p2) & ~(1'b0 == tmp_375_5_fu_17847_p2) & ~(1'b0 == or_cond133_fu_17817_p2)) | (~(1'b0 == tmp_351_5_fu_17799_p2) & ~(1'b0 == tmp_375_5_fu_17847_p2) & ~(1'b0 == or_cond134_fu_17841_p2)) | (~(1'b0 == tmp_351_5_fu_17799_p2) & ~(1'b0 == tmp_366_5_fu_17823_p2) & ~(1'b0 == or_cond135_fu_17865_p2)) | (~(1'b0 == tmp_375_5_fu_17847_p2) & ~(1'b0 == or_cond133_fu_17817_p2) & ~(1'b0 == or_cond134_fu_17841_p2)) | (~(1'b0 == tmp_366_5_fu_17823_p2) & ~(1'b0 == or_cond133_fu_17817_p2) & ~(1'b0 == or_cond135_fu_17865_p2)) | (~(1'b0 == tmp_351_5_fu_17799_p2) & ~(1'b0 == or_cond134_fu_17841_p2) & ~(1'b0 == or_cond135_fu_17865_p2)) | (~(1'b0 == or_cond133_fu_17817_p2) & ~(1'b0 == or_cond134_fu_17841_p2) & ~(1'b0 == or_cond135_fu_17865_p2)))) begin
a_winid_V_1_5_phi_fu_12427_p8 = ap_const_lv5_17;
end else begin
a_winid_V_1_5_phi_fu_12427_p8 = ap_reg_phiprechg_a_winid_V_1_5_reg_12424pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_6_fu_17875_p2) & ~(1'b0 == tmp_366_6_fu_17899_p2) & (1'b0 == tmp_375_6_fu_17923_p2) & (1'b0 == or_cond138_fu_17941_p2)) | (~(1'b0 == tmp_366_6_fu_17899_p2) & (1'b0 == tmp_375_6_fu_17923_p2) & ~(1'b0 == or_cond136_fu_17893_p2) & (1'b0 == or_cond138_fu_17941_p2)) | (~(1'b0 == tmp_351_6_fu_17875_p2) & (1'b0 == tmp_375_6_fu_17923_p2) & ~(1'b0 == or_cond137_fu_17917_p2) & (1'b0 == or_cond138_fu_17941_p2)) | ((1'b0 == tmp_375_6_fu_17923_p2) & ~(1'b0 == or_cond136_fu_17893_p2) & ~(1'b0 == or_cond137_fu_17917_p2) & (1'b0 == or_cond138_fu_17941_p2)))) begin
a_winid_V_1_6_phi_fu_12565_p8 = ap_const_lv4_A;
end else if (((~(1'b0 == tmp_351_6_fu_17875_p2) & (1'b0 == tmp_366_6_fu_17899_p2) & (1'b0 == or_cond137_fu_17917_p2)) | ((1'b0 == tmp_366_6_fu_17899_p2) & ~(1'b0 == or_cond136_fu_17893_p2) & (1'b0 == or_cond137_fu_17917_p2)))) begin
a_winid_V_1_6_phi_fu_12565_p8 = ap_const_lv4_9;
end else if (((1'b0 == tmp_351_6_fu_17875_p2) & (1'b0 == or_cond136_fu_17893_p2))) begin
a_winid_V_1_6_phi_fu_12565_p8 = ap_const_lv4_8;
end else if (((~(1'b0 == tmp_351_6_fu_17875_p2) & ~(1'b0 == tmp_366_6_fu_17899_p2) & ~(1'b0 == tmp_375_6_fu_17923_p2)) | (~(1'b0 == tmp_366_6_fu_17899_p2) & ~(1'b0 == tmp_375_6_fu_17923_p2) & ~(1'b0 == or_cond136_fu_17893_p2)) | (~(1'b0 == tmp_351_6_fu_17875_p2) & ~(1'b0 == tmp_375_6_fu_17923_p2) & ~(1'b0 == or_cond137_fu_17917_p2)) | (~(1'b0 == tmp_351_6_fu_17875_p2) & ~(1'b0 == tmp_366_6_fu_17899_p2) & ~(1'b0 == or_cond138_fu_17941_p2)) | (~(1'b0 == tmp_375_6_fu_17923_p2) & ~(1'b0 == or_cond136_fu_17893_p2) & ~(1'b0 == or_cond137_fu_17917_p2)) | (~(1'b0 == tmp_366_6_fu_17899_p2) & ~(1'b0 == or_cond136_fu_17893_p2) & ~(1'b0 == or_cond138_fu_17941_p2)) | (~(1'b0 == tmp_351_6_fu_17875_p2) & ~(1'b0 == or_cond137_fu_17917_p2) & ~(1'b0 == or_cond138_fu_17941_p2)) | (~(1'b0 == or_cond136_fu_17893_p2) & ~(1'b0 == or_cond137_fu_17917_p2) & ~(1'b0 == or_cond138_fu_17941_p2)))) begin
a_winid_V_1_6_phi_fu_12565_p8 = ap_const_lv4_B;
end else begin
a_winid_V_1_6_phi_fu_12565_p8 = ap_reg_phiprechg_a_winid_V_1_6_reg_12562pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_7_fu_17955_p2) & ~(1'b0 == tmp_366_7_fu_17979_p2) & (1'b0 == tmp_375_7_fu_18003_p2) & (1'b0 == or_cond141_fu_18021_p2)) | (~(1'b0 == tmp_366_7_fu_17979_p2) & (1'b0 == tmp_375_7_fu_18003_p2) & ~(1'b0 == or_cond139_fu_17973_p2) & (1'b0 == or_cond141_fu_18021_p2)) | (~(1'b0 == tmp_351_7_fu_17955_p2) & (1'b0 == tmp_375_7_fu_18003_p2) & ~(1'b0 == or_cond140_fu_17997_p2) & (1'b0 == or_cond141_fu_18021_p2)) | ((1'b0 == tmp_375_7_fu_18003_p2) & ~(1'b0 == or_cond139_fu_17973_p2) & ~(1'b0 == or_cond140_fu_17997_p2) & (1'b0 == or_cond141_fu_18021_p2)))) begin
a_winid_V_1_7_phi_fu_12703_p8 = ap_const_lv3_6;
end else if (((~(1'b0 == tmp_351_7_fu_17955_p2) & (1'b0 == tmp_366_7_fu_17979_p2) & (1'b0 == or_cond140_fu_17997_p2)) | ((1'b0 == tmp_366_7_fu_17979_p2) & ~(1'b0 == or_cond139_fu_17973_p2) & (1'b0 == or_cond140_fu_17997_p2)))) begin
a_winid_V_1_7_phi_fu_12703_p8 = ap_const_lv3_5;
end else if (((1'b0 == tmp_351_7_fu_17955_p2) & (1'b0 == or_cond139_fu_17973_p2))) begin
a_winid_V_1_7_phi_fu_12703_p8 = ap_const_lv3_4;
end else if (((~(1'b0 == tmp_351_7_fu_17955_p2) & ~(1'b0 == tmp_366_7_fu_17979_p2) & ~(1'b0 == tmp_375_7_fu_18003_p2)) | (~(1'b0 == tmp_366_7_fu_17979_p2) & ~(1'b0 == tmp_375_7_fu_18003_p2) & ~(1'b0 == or_cond139_fu_17973_p2)) | (~(1'b0 == tmp_351_7_fu_17955_p2) & ~(1'b0 == tmp_375_7_fu_18003_p2) & ~(1'b0 == or_cond140_fu_17997_p2)) | (~(1'b0 == tmp_351_7_fu_17955_p2) & ~(1'b0 == tmp_366_7_fu_17979_p2) & ~(1'b0 == or_cond141_fu_18021_p2)) | (~(1'b0 == tmp_375_7_fu_18003_p2) & ~(1'b0 == or_cond139_fu_17973_p2) & ~(1'b0 == or_cond140_fu_17997_p2)) | (~(1'b0 == tmp_366_7_fu_17979_p2) & ~(1'b0 == or_cond139_fu_17973_p2) & ~(1'b0 == or_cond141_fu_18021_p2)) | (~(1'b0 == tmp_351_7_fu_17955_p2) & ~(1'b0 == or_cond140_fu_17997_p2) & ~(1'b0 == or_cond141_fu_18021_p2)) | (~(1'b0 == or_cond139_fu_17973_p2) & ~(1'b0 == or_cond140_fu_17997_p2) & ~(1'b0 == or_cond141_fu_18021_p2)))) begin
a_winid_V_1_7_phi_fu_12703_p8 = ap_const_lv3_7;
end else begin
a_winid_V_1_7_phi_fu_12703_p8 = ap_reg_phiprechg_a_winid_V_1_7_reg_12700pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_8_fu_18035_p2) & ~(1'b0 == tmp_366_8_fu_18059_p2) & (1'b0 == tmp_375_8_fu_18083_p2) & (1'b0 == or_cond144_fu_18101_p2)) | (~(1'b0 == tmp_366_8_fu_18059_p2) & (1'b0 == tmp_375_8_fu_18083_p2) & ~(1'b0 == or_cond142_fu_18053_p2) & (1'b0 == or_cond144_fu_18101_p2)) | (~(1'b0 == tmp_351_8_fu_18035_p2) & (1'b0 == tmp_375_8_fu_18083_p2) & ~(1'b0 == or_cond143_fu_18077_p2) & (1'b0 == or_cond144_fu_18101_p2)) | ((1'b0 == tmp_375_8_fu_18083_p2) & ~(1'b0 == or_cond142_fu_18053_p2) & ~(1'b0 == or_cond143_fu_18077_p2) & (1'b0 == or_cond144_fu_18101_p2)))) begin
a_winid_V_1_8_phi_fu_12841_p8 = ap_const_lv6_22;
end else if (((~(1'b0 == tmp_351_8_fu_18035_p2) & (1'b0 == tmp_366_8_fu_18059_p2) & (1'b0 == or_cond143_fu_18077_p2)) | ((1'b0 == tmp_366_8_fu_18059_p2) & ~(1'b0 == or_cond142_fu_18053_p2) & (1'b0 == or_cond143_fu_18077_p2)))) begin
a_winid_V_1_8_phi_fu_12841_p8 = ap_const_lv6_21;
end else if (((1'b0 == tmp_351_8_fu_18035_p2) & (1'b0 == or_cond142_fu_18053_p2))) begin
a_winid_V_1_8_phi_fu_12841_p8 = ap_const_lv6_20;
end else if (((~(1'b0 == tmp_351_8_fu_18035_p2) & ~(1'b0 == tmp_366_8_fu_18059_p2) & ~(1'b0 == tmp_375_8_fu_18083_p2)) | (~(1'b0 == tmp_366_8_fu_18059_p2) & ~(1'b0 == tmp_375_8_fu_18083_p2) & ~(1'b0 == or_cond142_fu_18053_p2)) | (~(1'b0 == tmp_351_8_fu_18035_p2) & ~(1'b0 == tmp_375_8_fu_18083_p2) & ~(1'b0 == or_cond143_fu_18077_p2)) | (~(1'b0 == tmp_351_8_fu_18035_p2) & ~(1'b0 == tmp_366_8_fu_18059_p2) & ~(1'b0 == or_cond144_fu_18101_p2)) | (~(1'b0 == tmp_375_8_fu_18083_p2) & ~(1'b0 == or_cond142_fu_18053_p2) & ~(1'b0 == or_cond143_fu_18077_p2)) | (~(1'b0 == tmp_366_8_fu_18059_p2) & ~(1'b0 == or_cond142_fu_18053_p2) & ~(1'b0 == or_cond144_fu_18101_p2)) | (~(1'b0 == tmp_351_8_fu_18035_p2) & ~(1'b0 == or_cond143_fu_18077_p2) & ~(1'b0 == or_cond144_fu_18101_p2)) | (~(1'b0 == or_cond142_fu_18053_p2) & ~(1'b0 == or_cond143_fu_18077_p2) & ~(1'b0 == or_cond144_fu_18101_p2)))) begin
a_winid_V_1_8_phi_fu_12841_p8 = ap_const_lv6_23;
end else begin
a_winid_V_1_8_phi_fu_12841_p8 = ap_reg_phiprechg_a_winid_V_1_8_reg_12838pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_9_fu_18111_p2) & ~(1'b0 == tmp_366_9_fu_18135_p2) & (1'b0 == tmp_375_9_fu_18159_p2) & (1'b0 == or_cond147_fu_18177_p2)) | (~(1'b0 == tmp_366_9_fu_18135_p2) & (1'b0 == tmp_375_9_fu_18159_p2) & ~(1'b0 == or_cond145_fu_18129_p2) & (1'b0 == or_cond147_fu_18177_p2)) | (~(1'b0 == tmp_351_9_fu_18111_p2) & (1'b0 == tmp_375_9_fu_18159_p2) & ~(1'b0 == or_cond146_fu_18153_p2) & (1'b0 == or_cond147_fu_18177_p2)) | ((1'b0 == tmp_375_9_fu_18159_p2) & ~(1'b0 == or_cond145_fu_18129_p2) & ~(1'b0 == or_cond146_fu_18153_p2) & (1'b0 == or_cond147_fu_18177_p2)))) begin
a_winid_V_1_9_phi_fu_13072_p8 = ap_const_lv6_26;
end else if (((~(1'b0 == tmp_351_9_fu_18111_p2) & (1'b0 == tmp_366_9_fu_18135_p2) & (1'b0 == or_cond146_fu_18153_p2)) | ((1'b0 == tmp_366_9_fu_18135_p2) & ~(1'b0 == or_cond145_fu_18129_p2) & (1'b0 == or_cond146_fu_18153_p2)))) begin
a_winid_V_1_9_phi_fu_13072_p8 = ap_const_lv6_25;
end else if (((1'b0 == tmp_351_9_fu_18111_p2) & (1'b0 == or_cond145_fu_18129_p2))) begin
a_winid_V_1_9_phi_fu_13072_p8 = ap_const_lv6_24;
end else if (((~(1'b0 == tmp_351_9_fu_18111_p2) & ~(1'b0 == tmp_366_9_fu_18135_p2) & ~(1'b0 == tmp_375_9_fu_18159_p2)) | (~(1'b0 == tmp_366_9_fu_18135_p2) & ~(1'b0 == tmp_375_9_fu_18159_p2) & ~(1'b0 == or_cond145_fu_18129_p2)) | (~(1'b0 == tmp_351_9_fu_18111_p2) & ~(1'b0 == tmp_375_9_fu_18159_p2) & ~(1'b0 == or_cond146_fu_18153_p2)) | (~(1'b0 == tmp_351_9_fu_18111_p2) & ~(1'b0 == tmp_366_9_fu_18135_p2) & ~(1'b0 == or_cond147_fu_18177_p2)) | (~(1'b0 == tmp_375_9_fu_18159_p2) & ~(1'b0 == or_cond145_fu_18129_p2) & ~(1'b0 == or_cond146_fu_18153_p2)) | (~(1'b0 == tmp_366_9_fu_18135_p2) & ~(1'b0 == or_cond145_fu_18129_p2) & ~(1'b0 == or_cond147_fu_18177_p2)) | (~(1'b0 == tmp_351_9_fu_18111_p2) & ~(1'b0 == or_cond146_fu_18153_p2) & ~(1'b0 == or_cond147_fu_18177_p2)) | (~(1'b0 == or_cond145_fu_18129_p2) & ~(1'b0 == or_cond146_fu_18153_p2) & ~(1'b0 == or_cond147_fu_18177_p2)))) begin
a_winid_V_1_9_phi_fu_13072_p8 = ap_const_lv6_27;
end else begin
a_winid_V_1_9_phi_fu_13072_p8 = ap_reg_phiprechg_a_winid_V_1_9_reg_13069pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_226_fu_17403_p2) & ~(1'b0 == tmp_229_fu_17427_p2) & (1'b0 == tmp_232_fu_17451_p2) & (1'b0 == or_cond120_fu_17469_p2)) | (~(1'b0 == tmp_229_fu_17427_p2) & (1'b0 == tmp_232_fu_17451_p2) & ~(1'b0 == or_cond118_fu_17421_p2) & (1'b0 == or_cond120_fu_17469_p2)) | (~(1'b0 == tmp_226_fu_17403_p2) & (1'b0 == tmp_232_fu_17451_p2) & ~(1'b0 == or_cond119_fu_17445_p2) & (1'b0 == or_cond120_fu_17469_p2)) | ((1'b0 == tmp_232_fu_17451_p2) & ~(1'b0 == or_cond118_fu_17421_p2) & ~(1'b0 == or_cond119_fu_17445_p2) & (1'b0 == or_cond120_fu_17469_p2)))) begin
a_winid_V_1_phi_fu_12073_p8 = ap_const_lv2_2;
end else if (((~(1'b0 == tmp_226_fu_17403_p2) & (1'b0 == tmp_229_fu_17427_p2) & (1'b0 == or_cond119_fu_17445_p2)) | ((1'b0 == tmp_229_fu_17427_p2) & ~(1'b0 == or_cond118_fu_17421_p2) & (1'b0 == or_cond119_fu_17445_p2)))) begin
a_winid_V_1_phi_fu_12073_p8 = ap_const_lv2_1;
end else if (((1'b0 == tmp_226_fu_17403_p2) & (1'b0 == or_cond118_fu_17421_p2))) begin
a_winid_V_1_phi_fu_12073_p8 = ap_const_lv2_0;
end else if (((~(1'b0 == tmp_226_fu_17403_p2) & ~(1'b0 == tmp_229_fu_17427_p2) & ~(1'b0 == tmp_232_fu_17451_p2)) | (~(1'b0 == tmp_229_fu_17427_p2) & ~(1'b0 == tmp_232_fu_17451_p2) & ~(1'b0 == or_cond118_fu_17421_p2)) | (~(1'b0 == tmp_226_fu_17403_p2) & ~(1'b0 == tmp_232_fu_17451_p2) & ~(1'b0 == or_cond119_fu_17445_p2)) | (~(1'b0 == tmp_226_fu_17403_p2) & ~(1'b0 == tmp_229_fu_17427_p2) & ~(1'b0 == or_cond120_fu_17469_p2)) | (~(1'b0 == tmp_232_fu_17451_p2) & ~(1'b0 == or_cond118_fu_17421_p2) & ~(1'b0 == or_cond119_fu_17445_p2)) | (~(1'b0 == tmp_229_fu_17427_p2) & ~(1'b0 == or_cond118_fu_17421_p2) & ~(1'b0 == or_cond120_fu_17469_p2)) | (~(1'b0 == tmp_226_fu_17403_p2) & ~(1'b0 == or_cond119_fu_17445_p2) & ~(1'b0 == or_cond120_fu_17469_p2)) | (~(1'b0 == or_cond118_fu_17421_p2) & ~(1'b0 == or_cond119_fu_17445_p2) & ~(1'b0 == or_cond120_fu_17469_p2)))) begin
a_winid_V_1_phi_fu_12073_p8 = ap_const_lv2_3;
end else begin
a_winid_V_1_phi_fu_12073_p8 = ap_reg_phiprechg_a_winid_V_1_reg_12070pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_s_fu_18187_p2) & ~(1'b0 == tmp_366_s_fu_18211_p2) & (1'b0 == tmp_375_s_fu_18235_p2) & (1'b0 == or_cond150_fu_18253_p2)) | (~(1'b0 == tmp_366_s_fu_18211_p2) & (1'b0 == tmp_375_s_fu_18235_p2) & ~(1'b0 == or_cond148_fu_18205_p2) & (1'b0 == or_cond150_fu_18253_p2)) | (~(1'b0 == tmp_351_s_fu_18187_p2) & (1'b0 == tmp_375_s_fu_18235_p2) & ~(1'b0 == or_cond149_fu_18229_p2) & (1'b0 == or_cond150_fu_18253_p2)) | ((1'b0 == tmp_375_s_fu_18235_p2) & ~(1'b0 == or_cond148_fu_18205_p2) & ~(1'b0 == or_cond149_fu_18229_p2) & (1'b0 == or_cond150_fu_18253_p2)))) begin
a_winid_V_1_s_phi_fu_13303_p8 = ap_const_lv6_2A;
end else if (((~(1'b0 == tmp_351_s_fu_18187_p2) & (1'b0 == tmp_366_s_fu_18211_p2) & (1'b0 == or_cond149_fu_18229_p2)) | ((1'b0 == tmp_366_s_fu_18211_p2) & ~(1'b0 == or_cond148_fu_18205_p2) & (1'b0 == or_cond149_fu_18229_p2)))) begin
a_winid_V_1_s_phi_fu_13303_p8 = ap_const_lv6_29;
end else if (((1'b0 == tmp_351_s_fu_18187_p2) & (1'b0 == or_cond148_fu_18205_p2))) begin
a_winid_V_1_s_phi_fu_13303_p8 = ap_const_lv6_28;
end else if (((~(1'b0 == tmp_351_s_fu_18187_p2) & ~(1'b0 == tmp_366_s_fu_18211_p2) & ~(1'b0 == tmp_375_s_fu_18235_p2)) | (~(1'b0 == tmp_366_s_fu_18211_p2) & ~(1'b0 == tmp_375_s_fu_18235_p2) & ~(1'b0 == or_cond148_fu_18205_p2)) | (~(1'b0 == tmp_351_s_fu_18187_p2) & ~(1'b0 == tmp_375_s_fu_18235_p2) & ~(1'b0 == or_cond149_fu_18229_p2)) | (~(1'b0 == tmp_351_s_fu_18187_p2) & ~(1'b0 == tmp_366_s_fu_18211_p2) & ~(1'b0 == or_cond150_fu_18253_p2)) | (~(1'b0 == tmp_375_s_fu_18235_p2) & ~(1'b0 == or_cond148_fu_18205_p2) & ~(1'b0 == or_cond149_fu_18229_p2)) | (~(1'b0 == tmp_366_s_fu_18211_p2) & ~(1'b0 == or_cond148_fu_18205_p2) & ~(1'b0 == or_cond150_fu_18253_p2)) | (~(1'b0 == tmp_351_s_fu_18187_p2) & ~(1'b0 == or_cond149_fu_18229_p2) & ~(1'b0 == or_cond150_fu_18253_p2)) | (~(1'b0 == or_cond148_fu_18205_p2) & ~(1'b0 == or_cond149_fu_18229_p2) & ~(1'b0 == or_cond150_fu_18253_p2)))) begin
a_winid_V_1_s_phi_fu_13303_p8 = ap_const_lv6_2B;
end else begin
a_winid_V_1_s_phi_fu_13303_p8 = ap_reg_phiprechg_a_winid_V_1_s_reg_13300pp0_it1;
end
end
always @ (*) begin
if (~(1'b1 == 1'b1)) begin
ranki_l1_0_V_1_phi_fu_12090_p10 = ap_const_lv3_7;
end else if ((ap_const_lv2_3 == a_winid_V_1_phi_fu_12073_p8)) begin
ranki_l1_0_V_1_phi_fu_12090_p10 = ap_const_lv3_3;
end else if ((ap_const_lv2_2 == a_winid_V_1_phi_fu_12073_p8)) begin
ranki_l1_0_V_1_phi_fu_12090_p10 = ap_const_lv3_2;
end else if ((ap_const_lv2_1 == a_winid_V_1_phi_fu_12073_p8)) begin
ranki_l1_0_V_1_phi_fu_12090_p10 = ap_const_lv3_1;
end else if ((ap_const_lv2_0 == a_winid_V_1_phi_fu_12073_p8)) begin
ranki_l1_0_V_1_phi_fu_12090_p10 = ap_const_lv3_0;
end else begin
ranki_l1_0_V_1_phi_fu_12090_p10 = ap_reg_phiprechg_ranki_l1_0_V_1_reg_12087pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_3F == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_3F;
end else if ((ap_const_lv6_3E == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_3E;
end else if ((ap_const_lv6_3D == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_3D;
end else if ((ap_const_lv6_3C == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_3C;
end else if ((ap_const_lv6_3B == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_3B;
end else if ((ap_const_lv6_3A == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_3A;
end else if ((ap_const_lv6_39 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_39;
end else if ((ap_const_lv6_38 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_38;
end else if ((ap_const_lv6_37 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_37;
end else if ((ap_const_lv6_36 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_36;
end else if ((ap_const_lv6_35 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_35;
end else if ((ap_const_lv6_34 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_34;
end else if ((ap_const_lv6_33 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_33;
end else if ((ap_const_lv6_32 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_32;
end else if ((ap_const_lv6_31 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_31;
end else if ((ap_const_lv6_30 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_30;
end else if ((ap_const_lv6_2F == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_2F;
end else if ((ap_const_lv6_2E == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_2E;
end else if ((ap_const_lv6_2D == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_2D;
end else if ((ap_const_lv6_2C == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_2C;
end else if ((ap_const_lv6_2B == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_2B;
end else if ((ap_const_lv6_2A == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_2A;
end else if ((ap_const_lv6_29 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_29;
end else if ((ap_const_lv6_28 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_28;
end else if ((ap_const_lv6_27 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_27;
end else if ((ap_const_lv6_26 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_26;
end else if ((ap_const_lv6_25 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_25;
end else if ((ap_const_lv6_24 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_24;
end else if ((ap_const_lv6_23 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_23;
end else if ((ap_const_lv6_22 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_22;
end else if ((ap_const_lv6_21 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_21;
end else if ((ap_const_lv6_20 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_20;
end else if ((ap_const_lv6_1F == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_1F;
end else if ((ap_const_lv6_1E == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_1E;
end else if ((ap_const_lv6_1D == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_1D;
end else if ((ap_const_lv6_1C == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_1C;
end else if ((ap_const_lv6_1B == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_1B;
end else if ((ap_const_lv6_1A == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_1A;
end else if ((ap_const_lv6_19 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_19;
end else if ((ap_const_lv6_18 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_18;
end else if ((ap_const_lv6_17 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_17;
end else if ((ap_const_lv6_16 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_16;
end else if ((ap_const_lv6_15 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_15;
end else if ((ap_const_lv6_14 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_14;
end else if ((ap_const_lv6_13 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_13;
end else if ((ap_const_lv6_12 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_12;
end else if ((ap_const_lv6_11 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_11;
end else if ((ap_const_lv6_10 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_10;
end else if ((ap_const_lv6_F == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_F;
end else if ((ap_const_lv6_E == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_E;
end else if ((ap_const_lv6_D == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_D;
end else if ((ap_const_lv6_C == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_C;
end else if ((ap_const_lv6_B == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_B;
end else if ((ap_const_lv6_A == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_A;
end else if ((ap_const_lv6_9 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_9;
end else if ((ap_const_lv6_8 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_8;
end else if ((ap_const_lv6_7 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_7;
end else if ((ap_const_lv6_6 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_6;
end else if ((ap_const_lv6_5 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_5;
end else if ((ap_const_lv6_4 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_4;
end else if ((ap_const_lv6_3 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_3;
end else if ((ap_const_lv6_2 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_2;
end else if ((ap_const_lv6_1 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_1;
end else if ((ap_const_lv6_0 == a_winid_V_1_s_phi_fu_13303_p8)) begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_const_lv6_0;
end else begin
ranki_l1_10_V_1_phi_fu_13320_p128 = ap_reg_phiprechg_ranki_l1_10_V_1_reg_13317pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_3F == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_3F;
end else if ((ap_const_lv6_3E == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_3E;
end else if ((ap_const_lv6_3D == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_3D;
end else if ((ap_const_lv6_3C == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_3C;
end else if ((ap_const_lv6_3B == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_3B;
end else if ((ap_const_lv6_3A == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_3A;
end else if ((ap_const_lv6_39 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_39;
end else if ((ap_const_lv6_38 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_38;
end else if ((ap_const_lv6_37 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_37;
end else if ((ap_const_lv6_36 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_36;
end else if ((ap_const_lv6_35 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_35;
end else if ((ap_const_lv6_34 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_34;
end else if ((ap_const_lv6_33 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_33;
end else if ((ap_const_lv6_32 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_32;
end else if ((ap_const_lv6_31 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_31;
end else if ((ap_const_lv6_30 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_30;
end else if ((ap_const_lv6_2F == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_2F;
end else if ((ap_const_lv6_2E == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_2E;
end else if ((ap_const_lv6_2D == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_2D;
end else if ((ap_const_lv6_2C == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_2C;
end else if ((ap_const_lv6_2B == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_2B;
end else if ((ap_const_lv6_2A == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_2A;
end else if ((ap_const_lv6_29 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_29;
end else if ((ap_const_lv6_28 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_28;
end else if ((ap_const_lv6_27 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_27;
end else if ((ap_const_lv6_26 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_26;
end else if ((ap_const_lv6_25 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_25;
end else if ((ap_const_lv6_24 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_24;
end else if ((ap_const_lv6_23 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_23;
end else if ((ap_const_lv6_22 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_22;
end else if ((ap_const_lv6_21 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_21;
end else if ((ap_const_lv6_20 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_20;
end else if ((ap_const_lv6_1F == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_1F;
end else if ((ap_const_lv6_1E == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_1E;
end else if ((ap_const_lv6_1D == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_1D;
end else if ((ap_const_lv6_1C == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_1C;
end else if ((ap_const_lv6_1B == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_1B;
end else if ((ap_const_lv6_1A == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_1A;
end else if ((ap_const_lv6_19 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_19;
end else if ((ap_const_lv6_18 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_18;
end else if ((ap_const_lv6_17 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_17;
end else if ((ap_const_lv6_16 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_16;
end else if ((ap_const_lv6_15 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_15;
end else if ((ap_const_lv6_14 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_14;
end else if ((ap_const_lv6_13 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_13;
end else if ((ap_const_lv6_12 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_12;
end else if ((ap_const_lv6_11 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_11;
end else if ((ap_const_lv6_10 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_10;
end else if ((ap_const_lv6_F == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_F;
end else if ((ap_const_lv6_E == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_E;
end else if ((ap_const_lv6_D == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_D;
end else if ((ap_const_lv6_C == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_C;
end else if ((ap_const_lv6_B == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_B;
end else if ((ap_const_lv6_A == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_A;
end else if ((ap_const_lv6_9 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_9;
end else if ((ap_const_lv6_8 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_8;
end else if ((ap_const_lv6_7 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_7;
end else if ((ap_const_lv6_6 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_6;
end else if ((ap_const_lv6_5 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_5;
end else if ((ap_const_lv6_4 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_4;
end else if ((ap_const_lv6_3 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_3;
end else if ((ap_const_lv6_2 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_2;
end else if ((ap_const_lv6_1 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_1;
end else if ((ap_const_lv6_0 == a_winid_V_10_phi_fu_2627_p8)) begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_const_lv6_0;
end else begin
ranki_l1_10_V_phi_fu_2644_p128 = ap_reg_phiprechg_ranki_l1_10_V_reg_2641pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_3F == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_3F;
end else if ((ap_const_lv6_3E == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_3E;
end else if ((ap_const_lv6_3D == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_3D;
end else if ((ap_const_lv6_3C == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_3C;
end else if ((ap_const_lv6_3B == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_3B;
end else if ((ap_const_lv6_3A == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_3A;
end else if ((ap_const_lv6_39 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_39;
end else if ((ap_const_lv6_38 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_38;
end else if ((ap_const_lv6_37 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_37;
end else if ((ap_const_lv6_36 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_36;
end else if ((ap_const_lv6_35 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_35;
end else if ((ap_const_lv6_34 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_34;
end else if ((ap_const_lv6_33 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_33;
end else if ((ap_const_lv6_32 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_32;
end else if ((ap_const_lv6_31 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_31;
end else if ((ap_const_lv6_30 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_30;
end else if ((ap_const_lv6_2F == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_2F;
end else if ((ap_const_lv6_2E == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_2E;
end else if ((ap_const_lv6_2D == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_2D;
end else if ((ap_const_lv6_2C == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_2C;
end else if ((ap_const_lv6_2B == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_2B;
end else if ((ap_const_lv6_2A == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_2A;
end else if ((ap_const_lv6_29 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_29;
end else if ((ap_const_lv6_28 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_28;
end else if ((ap_const_lv6_27 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_27;
end else if ((ap_const_lv6_26 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_26;
end else if ((ap_const_lv6_25 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_25;
end else if ((ap_const_lv6_24 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_24;
end else if ((ap_const_lv6_23 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_23;
end else if ((ap_const_lv6_22 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_22;
end else if ((ap_const_lv6_21 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_21;
end else if ((ap_const_lv6_20 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_20;
end else if ((ap_const_lv6_1F == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_1F;
end else if ((ap_const_lv6_1E == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_1E;
end else if ((ap_const_lv6_1D == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_1D;
end else if ((ap_const_lv6_1C == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_1C;
end else if ((ap_const_lv6_1B == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_1B;
end else if ((ap_const_lv6_1A == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_1A;
end else if ((ap_const_lv6_19 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_19;
end else if ((ap_const_lv6_18 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_18;
end else if ((ap_const_lv6_17 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_17;
end else if ((ap_const_lv6_16 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_16;
end else if ((ap_const_lv6_15 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_15;
end else if ((ap_const_lv6_14 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_14;
end else if ((ap_const_lv6_13 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_13;
end else if ((ap_const_lv6_12 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_12;
end else if ((ap_const_lv6_11 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_11;
end else if ((ap_const_lv6_10 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_10;
end else if ((ap_const_lv6_F == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_F;
end else if ((ap_const_lv6_E == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_E;
end else if ((ap_const_lv6_D == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_D;
end else if ((ap_const_lv6_C == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_C;
end else if ((ap_const_lv6_B == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_B;
end else if ((ap_const_lv6_A == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_A;
end else if ((ap_const_lv6_9 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_9;
end else if ((ap_const_lv6_8 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_8;
end else if ((ap_const_lv6_7 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_7;
end else if ((ap_const_lv6_6 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_6;
end else if ((ap_const_lv6_5 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_5;
end else if ((ap_const_lv6_4 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_4;
end else if ((ap_const_lv6_3 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_3;
end else if ((ap_const_lv6_2 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_2;
end else if ((ap_const_lv6_1 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_1;
end else if ((ap_const_lv6_0 == a_winid_V_1_10_phi_fu_13534_p8)) begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_const_lv6_0;
end else begin
ranki_l1_11_V_1_phi_fu_13551_p128 = ap_reg_phiprechg_ranki_l1_11_V_1_reg_13548pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_3F == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_3F;
end else if ((ap_const_lv6_3E == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_3E;
end else if ((ap_const_lv6_3D == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_3D;
end else if ((ap_const_lv6_3C == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_3C;
end else if ((ap_const_lv6_3B == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_3B;
end else if ((ap_const_lv6_3A == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_3A;
end else if ((ap_const_lv6_39 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_39;
end else if ((ap_const_lv6_38 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_38;
end else if ((ap_const_lv6_37 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_37;
end else if ((ap_const_lv6_36 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_36;
end else if ((ap_const_lv6_35 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_35;
end else if ((ap_const_lv6_34 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_34;
end else if ((ap_const_lv6_33 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_33;
end else if ((ap_const_lv6_32 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_32;
end else if ((ap_const_lv6_31 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_31;
end else if ((ap_const_lv6_30 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_30;
end else if ((ap_const_lv6_2F == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_2F;
end else if ((ap_const_lv6_2E == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_2E;
end else if ((ap_const_lv6_2D == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_2D;
end else if ((ap_const_lv6_2C == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_2C;
end else if ((ap_const_lv6_2B == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_2B;
end else if ((ap_const_lv6_2A == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_2A;
end else if ((ap_const_lv6_29 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_29;
end else if ((ap_const_lv6_28 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_28;
end else if ((ap_const_lv6_27 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_27;
end else if ((ap_const_lv6_26 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_26;
end else if ((ap_const_lv6_25 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_25;
end else if ((ap_const_lv6_24 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_24;
end else if ((ap_const_lv6_23 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_23;
end else if ((ap_const_lv6_22 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_22;
end else if ((ap_const_lv6_21 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_21;
end else if ((ap_const_lv6_20 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_20;
end else if ((ap_const_lv6_1F == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_1F;
end else if ((ap_const_lv6_1E == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_1E;
end else if ((ap_const_lv6_1D == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_1D;
end else if ((ap_const_lv6_1C == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_1C;
end else if ((ap_const_lv6_1B == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_1B;
end else if ((ap_const_lv6_1A == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_1A;
end else if ((ap_const_lv6_19 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_19;
end else if ((ap_const_lv6_18 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_18;
end else if ((ap_const_lv6_17 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_17;
end else if ((ap_const_lv6_16 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_16;
end else if ((ap_const_lv6_15 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_15;
end else if ((ap_const_lv6_14 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_14;
end else if ((ap_const_lv6_13 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_13;
end else if ((ap_const_lv6_12 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_12;
end else if ((ap_const_lv6_11 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_11;
end else if ((ap_const_lv6_10 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_10;
end else if ((ap_const_lv6_F == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_F;
end else if ((ap_const_lv6_E == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_E;
end else if ((ap_const_lv6_D == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_D;
end else if ((ap_const_lv6_C == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_C;
end else if ((ap_const_lv6_B == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_B;
end else if ((ap_const_lv6_A == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_A;
end else if ((ap_const_lv6_9 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_9;
end else if ((ap_const_lv6_8 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_8;
end else if ((ap_const_lv6_7 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_7;
end else if ((ap_const_lv6_6 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_6;
end else if ((ap_const_lv6_5 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_5;
end else if ((ap_const_lv6_4 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_4;
end else if ((ap_const_lv6_3 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_3;
end else if ((ap_const_lv6_2 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_2;
end else if ((ap_const_lv6_1 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_1;
end else if ((ap_const_lv6_0 == a_winid_V_11_phi_fu_2845_p8)) begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_const_lv6_0;
end else begin
ranki_l1_11_V_phi_fu_2862_p128 = ap_reg_phiprechg_ranki_l1_11_V_reg_2859pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_3F == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_3F;
end else if ((ap_const_lv6_3E == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_3E;
end else if ((ap_const_lv6_3D == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_3D;
end else if ((ap_const_lv6_3C == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_3C;
end else if ((ap_const_lv6_3B == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_3B;
end else if ((ap_const_lv6_3A == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_3A;
end else if ((ap_const_lv6_39 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_39;
end else if ((ap_const_lv6_38 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_38;
end else if ((ap_const_lv6_37 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_37;
end else if ((ap_const_lv6_36 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_36;
end else if ((ap_const_lv6_35 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_35;
end else if ((ap_const_lv6_34 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_34;
end else if ((ap_const_lv6_33 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_33;
end else if ((ap_const_lv6_32 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_32;
end else if ((ap_const_lv6_31 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_31;
end else if ((ap_const_lv6_30 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_30;
end else if ((ap_const_lv6_2F == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_2F;
end else if ((ap_const_lv6_2E == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_2E;
end else if ((ap_const_lv6_2D == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_2D;
end else if ((ap_const_lv6_2C == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_2C;
end else if ((ap_const_lv6_2B == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_2B;
end else if ((ap_const_lv6_2A == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_2A;
end else if ((ap_const_lv6_29 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_29;
end else if ((ap_const_lv6_28 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_28;
end else if ((ap_const_lv6_27 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_27;
end else if ((ap_const_lv6_26 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_26;
end else if ((ap_const_lv6_25 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_25;
end else if ((ap_const_lv6_24 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_24;
end else if ((ap_const_lv6_23 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_23;
end else if ((ap_const_lv6_22 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_22;
end else if ((ap_const_lv6_21 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_21;
end else if ((ap_const_lv6_20 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_20;
end else if ((ap_const_lv6_1F == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_1F;
end else if ((ap_const_lv6_1E == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_1E;
end else if ((ap_const_lv6_1D == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_1D;
end else if ((ap_const_lv6_1C == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_1C;
end else if ((ap_const_lv6_1B == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_1B;
end else if ((ap_const_lv6_1A == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_1A;
end else if ((ap_const_lv6_19 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_19;
end else if ((ap_const_lv6_18 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_18;
end else if ((ap_const_lv6_17 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_17;
end else if ((ap_const_lv6_16 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_16;
end else if ((ap_const_lv6_15 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_15;
end else if ((ap_const_lv6_14 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_14;
end else if ((ap_const_lv6_13 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_13;
end else if ((ap_const_lv6_12 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_12;
end else if ((ap_const_lv6_11 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_11;
end else if ((ap_const_lv6_10 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_10;
end else if ((ap_const_lv6_F == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_F;
end else if ((ap_const_lv6_E == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_E;
end else if ((ap_const_lv6_D == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_D;
end else if ((ap_const_lv6_C == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_C;
end else if ((ap_const_lv6_B == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_B;
end else if ((ap_const_lv6_A == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_A;
end else if ((ap_const_lv6_9 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_9;
end else if ((ap_const_lv6_8 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_8;
end else if ((ap_const_lv6_7 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_7;
end else if ((ap_const_lv6_6 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_6;
end else if ((ap_const_lv6_5 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_5;
end else if ((ap_const_lv6_4 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_4;
end else if ((ap_const_lv6_3 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_3;
end else if ((ap_const_lv6_2 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_2;
end else if ((ap_const_lv6_1 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_1;
end else if ((ap_const_lv6_0 == a_winid_V_1_11_cast_fu_18411_p1)) begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_const_lv6_0;
end else begin
ranki_l1_12_V_1_phi_fu_13782_p128 = ap_reg_phiprechg_ranki_l1_12_V_1_reg_13779pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_3F == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_3F;
end else if ((ap_const_lv6_3E == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_3E;
end else if ((ap_const_lv6_3D == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_3D;
end else if ((ap_const_lv6_3C == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_3C;
end else if ((ap_const_lv6_3B == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_3B;
end else if ((ap_const_lv6_3A == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_3A;
end else if ((ap_const_lv6_39 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_39;
end else if ((ap_const_lv6_38 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_38;
end else if ((ap_const_lv6_37 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_37;
end else if ((ap_const_lv6_36 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_36;
end else if ((ap_const_lv6_35 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_35;
end else if ((ap_const_lv6_34 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_34;
end else if ((ap_const_lv6_33 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_33;
end else if ((ap_const_lv6_32 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_32;
end else if ((ap_const_lv6_31 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_31;
end else if ((ap_const_lv6_30 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_30;
end else if ((ap_const_lv6_2F == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_2F;
end else if ((ap_const_lv6_2E == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_2E;
end else if ((ap_const_lv6_2D == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_2D;
end else if ((ap_const_lv6_2C == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_2C;
end else if ((ap_const_lv6_2B == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_2B;
end else if ((ap_const_lv6_2A == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_2A;
end else if ((ap_const_lv6_29 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_29;
end else if ((ap_const_lv6_28 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_28;
end else if ((ap_const_lv6_27 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_27;
end else if ((ap_const_lv6_26 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_26;
end else if ((ap_const_lv6_25 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_25;
end else if ((ap_const_lv6_24 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_24;
end else if ((ap_const_lv6_23 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_23;
end else if ((ap_const_lv6_22 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_22;
end else if ((ap_const_lv6_21 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_21;
end else if ((ap_const_lv6_20 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_20;
end else if ((ap_const_lv6_1F == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_1F;
end else if ((ap_const_lv6_1E == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_1E;
end else if ((ap_const_lv6_1D == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_1D;
end else if ((ap_const_lv6_1C == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_1C;
end else if ((ap_const_lv6_1B == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_1B;
end else if ((ap_const_lv6_1A == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_1A;
end else if ((ap_const_lv6_19 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_19;
end else if ((ap_const_lv6_18 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_18;
end else if ((ap_const_lv6_17 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_17;
end else if ((ap_const_lv6_16 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_16;
end else if ((ap_const_lv6_15 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_15;
end else if ((ap_const_lv6_14 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_14;
end else if ((ap_const_lv6_13 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_13;
end else if ((ap_const_lv6_12 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_12;
end else if ((ap_const_lv6_11 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_11;
end else if ((ap_const_lv6_10 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_10;
end else if ((ap_const_lv6_F == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_F;
end else if ((ap_const_lv6_E == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_E;
end else if ((ap_const_lv6_D == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_D;
end else if ((ap_const_lv6_C == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_C;
end else if ((ap_const_lv6_B == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_B;
end else if ((ap_const_lv6_A == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_A;
end else if ((ap_const_lv6_9 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_9;
end else if ((ap_const_lv6_8 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_8;
end else if ((ap_const_lv6_7 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_7;
end else if ((ap_const_lv6_6 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_6;
end else if ((ap_const_lv6_5 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_5;
end else if ((ap_const_lv6_4 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_4;
end else if ((ap_const_lv6_3 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_3;
end else if ((ap_const_lv6_2 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_2;
end else if ((ap_const_lv6_1 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_1;
end else if ((ap_const_lv6_0 == a_winid_V_12_cast_fu_16886_p1)) begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_const_lv6_0;
end else begin
ranki_l1_12_V_phi_fu_3080_p128 = ap_reg_phiprechg_ranki_l1_12_V_reg_3077pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_3F == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_3F;
end else if ((ap_const_lv6_3E == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_3E;
end else if ((ap_const_lv6_3D == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_3D;
end else if ((ap_const_lv6_3C == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_3C;
end else if ((ap_const_lv6_3B == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_3B;
end else if ((ap_const_lv6_3A == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_3A;
end else if ((ap_const_lv6_39 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_39;
end else if ((ap_const_lv6_38 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_38;
end else if ((ap_const_lv6_37 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_37;
end else if ((ap_const_lv6_36 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_36;
end else if ((ap_const_lv6_35 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_35;
end else if ((ap_const_lv6_34 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_34;
end else if ((ap_const_lv6_33 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_33;
end else if ((ap_const_lv6_32 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_32;
end else if ((ap_const_lv6_31 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_31;
end else if ((ap_const_lv6_30 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_30;
end else if ((ap_const_lv6_2F == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_2F;
end else if ((ap_const_lv6_2E == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_2E;
end else if ((ap_const_lv6_2D == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_2D;
end else if ((ap_const_lv6_2C == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_2C;
end else if ((ap_const_lv6_2B == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_2B;
end else if ((ap_const_lv6_2A == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_2A;
end else if ((ap_const_lv6_29 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_29;
end else if ((ap_const_lv6_28 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_28;
end else if ((ap_const_lv6_27 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_27;
end else if ((ap_const_lv6_26 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_26;
end else if ((ap_const_lv6_25 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_25;
end else if ((ap_const_lv6_24 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_24;
end else if ((ap_const_lv6_23 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_23;
end else if ((ap_const_lv6_22 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_22;
end else if ((ap_const_lv6_21 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_21;
end else if ((ap_const_lv6_20 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_20;
end else if ((ap_const_lv6_1F == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_1F;
end else if ((ap_const_lv6_1E == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_1E;
end else if ((ap_const_lv6_1D == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_1D;
end else if ((ap_const_lv6_1C == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_1C;
end else if ((ap_const_lv6_1B == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_1B;
end else if ((ap_const_lv6_1A == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_1A;
end else if ((ap_const_lv6_19 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_19;
end else if ((ap_const_lv6_18 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_18;
end else if ((ap_const_lv6_17 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_17;
end else if ((ap_const_lv6_16 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_16;
end else if ((ap_const_lv6_15 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_15;
end else if ((ap_const_lv6_14 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_14;
end else if ((ap_const_lv6_13 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_13;
end else if ((ap_const_lv6_12 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_12;
end else if ((ap_const_lv6_11 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_11;
end else if ((ap_const_lv6_10 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_10;
end else if ((ap_const_lv6_F == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_F;
end else if ((ap_const_lv6_E == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_E;
end else if ((ap_const_lv6_D == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_D;
end else if ((ap_const_lv6_C == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_C;
end else if ((ap_const_lv6_B == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_B;
end else if ((ap_const_lv6_A == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_A;
end else if ((ap_const_lv6_9 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_9;
end else if ((ap_const_lv6_8 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_8;
end else if ((ap_const_lv6_7 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_7;
end else if ((ap_const_lv6_6 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_6;
end else if ((ap_const_lv6_5 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_5;
end else if ((ap_const_lv6_4 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_4;
end else if ((ap_const_lv6_3 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_3;
end else if ((ap_const_lv6_2 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_2;
end else if ((ap_const_lv6_1 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_1;
end else if ((ap_const_lv6_0 == a_winid_V_1_12_cast_fu_18491_p1)) begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_const_lv6_0;
end else begin
ranki_l1_13_V_1_phi_fu_14013_p128 = ap_reg_phiprechg_ranki_l1_13_V_1_reg_14010pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_3F == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_3F;
end else if ((ap_const_lv6_3E == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_3E;
end else if ((ap_const_lv6_3D == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_3D;
end else if ((ap_const_lv6_3C == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_3C;
end else if ((ap_const_lv6_3B == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_3B;
end else if ((ap_const_lv6_3A == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_3A;
end else if ((ap_const_lv6_39 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_39;
end else if ((ap_const_lv6_38 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_38;
end else if ((ap_const_lv6_37 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_37;
end else if ((ap_const_lv6_36 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_36;
end else if ((ap_const_lv6_35 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_35;
end else if ((ap_const_lv6_34 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_34;
end else if ((ap_const_lv6_33 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_33;
end else if ((ap_const_lv6_32 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_32;
end else if ((ap_const_lv6_31 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_31;
end else if ((ap_const_lv6_30 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_30;
end else if ((ap_const_lv6_2F == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_2F;
end else if ((ap_const_lv6_2E == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_2E;
end else if ((ap_const_lv6_2D == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_2D;
end else if ((ap_const_lv6_2C == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_2C;
end else if ((ap_const_lv6_2B == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_2B;
end else if ((ap_const_lv6_2A == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_2A;
end else if ((ap_const_lv6_29 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_29;
end else if ((ap_const_lv6_28 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_28;
end else if ((ap_const_lv6_27 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_27;
end else if ((ap_const_lv6_26 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_26;
end else if ((ap_const_lv6_25 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_25;
end else if ((ap_const_lv6_24 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_24;
end else if ((ap_const_lv6_23 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_23;
end else if ((ap_const_lv6_22 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_22;
end else if ((ap_const_lv6_21 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_21;
end else if ((ap_const_lv6_20 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_20;
end else if ((ap_const_lv6_1F == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_1F;
end else if ((ap_const_lv6_1E == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_1E;
end else if ((ap_const_lv6_1D == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_1D;
end else if ((ap_const_lv6_1C == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_1C;
end else if ((ap_const_lv6_1B == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_1B;
end else if ((ap_const_lv6_1A == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_1A;
end else if ((ap_const_lv6_19 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_19;
end else if ((ap_const_lv6_18 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_18;
end else if ((ap_const_lv6_17 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_17;
end else if ((ap_const_lv6_16 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_16;
end else if ((ap_const_lv6_15 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_15;
end else if ((ap_const_lv6_14 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_14;
end else if ((ap_const_lv6_13 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_13;
end else if ((ap_const_lv6_12 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_12;
end else if ((ap_const_lv6_11 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_11;
end else if ((ap_const_lv6_10 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_10;
end else if ((ap_const_lv6_F == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_F;
end else if ((ap_const_lv6_E == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_E;
end else if ((ap_const_lv6_D == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_D;
end else if ((ap_const_lv6_C == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_C;
end else if ((ap_const_lv6_B == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_B;
end else if ((ap_const_lv6_A == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_A;
end else if ((ap_const_lv6_9 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_9;
end else if ((ap_const_lv6_8 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_8;
end else if ((ap_const_lv6_7 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_7;
end else if ((ap_const_lv6_6 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_6;
end else if ((ap_const_lv6_5 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_5;
end else if ((ap_const_lv6_4 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_4;
end else if ((ap_const_lv6_3 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_3;
end else if ((ap_const_lv6_2 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_2;
end else if ((ap_const_lv6_1 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_1;
end else if ((ap_const_lv6_0 == a_winid_V_13_cast_fu_16894_p1)) begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_const_lv6_0;
end else begin
ranki_l1_13_V_phi_fu_3298_p128 = ap_reg_phiprechg_ranki_l1_13_V_reg_3295pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_3F == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_3F;
end else if ((ap_const_lv6_3E == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_3E;
end else if ((ap_const_lv6_3D == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_3D;
end else if ((ap_const_lv6_3C == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_3C;
end else if ((ap_const_lv6_3B == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_3B;
end else if ((ap_const_lv6_3A == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_3A;
end else if ((ap_const_lv6_39 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_39;
end else if ((ap_const_lv6_38 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_38;
end else if ((ap_const_lv6_37 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_37;
end else if ((ap_const_lv6_36 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_36;
end else if ((ap_const_lv6_35 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_35;
end else if ((ap_const_lv6_34 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_34;
end else if ((ap_const_lv6_33 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_33;
end else if ((ap_const_lv6_32 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_32;
end else if ((ap_const_lv6_31 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_31;
end else if ((ap_const_lv6_30 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_30;
end else if ((ap_const_lv6_2F == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_2F;
end else if ((ap_const_lv6_2E == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_2E;
end else if ((ap_const_lv6_2D == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_2D;
end else if ((ap_const_lv6_2C == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_2C;
end else if ((ap_const_lv6_2B == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_2B;
end else if ((ap_const_lv6_2A == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_2A;
end else if ((ap_const_lv6_29 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_29;
end else if ((ap_const_lv6_28 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_28;
end else if ((ap_const_lv6_27 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_27;
end else if ((ap_const_lv6_26 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_26;
end else if ((ap_const_lv6_25 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_25;
end else if ((ap_const_lv6_24 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_24;
end else if ((ap_const_lv6_23 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_23;
end else if ((ap_const_lv6_22 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_22;
end else if ((ap_const_lv6_21 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_21;
end else if ((ap_const_lv6_20 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_20;
end else if ((ap_const_lv6_1F == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_1F;
end else if ((ap_const_lv6_1E == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_1E;
end else if ((ap_const_lv6_1D == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_1D;
end else if ((ap_const_lv6_1C == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_1C;
end else if ((ap_const_lv6_1B == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_1B;
end else if ((ap_const_lv6_1A == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_1A;
end else if ((ap_const_lv6_19 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_19;
end else if ((ap_const_lv6_18 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_18;
end else if ((ap_const_lv6_17 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_17;
end else if ((ap_const_lv6_16 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_16;
end else if ((ap_const_lv6_15 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_15;
end else if ((ap_const_lv6_14 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_14;
end else if ((ap_const_lv6_13 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_13;
end else if ((ap_const_lv6_12 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_12;
end else if ((ap_const_lv6_11 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_11;
end else if ((ap_const_lv6_10 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_10;
end else if ((ap_const_lv6_F == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_F;
end else if ((ap_const_lv6_E == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_E;
end else if ((ap_const_lv6_D == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_D;
end else if ((ap_const_lv6_C == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_C;
end else if ((ap_const_lv6_B == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_B;
end else if ((ap_const_lv6_A == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_A;
end else if ((ap_const_lv6_9 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_9;
end else if ((ap_const_lv6_8 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_8;
end else if ((ap_const_lv6_7 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_7;
end else if ((ap_const_lv6_6 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_6;
end else if ((ap_const_lv6_5 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_5;
end else if ((ap_const_lv6_4 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_4;
end else if ((ap_const_lv6_3 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_3;
end else if ((ap_const_lv6_2 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_2;
end else if ((ap_const_lv6_1 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_1;
end else if ((ap_const_lv6_0 == a_winid_V_1_13_cast_fu_18571_p1)) begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_const_lv6_0;
end else begin
ranki_l1_14_V_1_phi_fu_14244_p128 = ap_reg_phiprechg_ranki_l1_14_V_1_reg_14241pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_3F == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_3F;
end else if ((ap_const_lv6_3E == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_3E;
end else if ((ap_const_lv6_3D == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_3D;
end else if ((ap_const_lv6_3C == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_3C;
end else if ((ap_const_lv6_3B == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_3B;
end else if ((ap_const_lv6_3A == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_3A;
end else if ((ap_const_lv6_39 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_39;
end else if ((ap_const_lv6_38 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_38;
end else if ((ap_const_lv6_37 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_37;
end else if ((ap_const_lv6_36 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_36;
end else if ((ap_const_lv6_35 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_35;
end else if ((ap_const_lv6_34 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_34;
end else if ((ap_const_lv6_33 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_33;
end else if ((ap_const_lv6_32 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_32;
end else if ((ap_const_lv6_31 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_31;
end else if ((ap_const_lv6_30 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_30;
end else if ((ap_const_lv6_2F == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_2F;
end else if ((ap_const_lv6_2E == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_2E;
end else if ((ap_const_lv6_2D == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_2D;
end else if ((ap_const_lv6_2C == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_2C;
end else if ((ap_const_lv6_2B == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_2B;
end else if ((ap_const_lv6_2A == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_2A;
end else if ((ap_const_lv6_29 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_29;
end else if ((ap_const_lv6_28 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_28;
end else if ((ap_const_lv6_27 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_27;
end else if ((ap_const_lv6_26 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_26;
end else if ((ap_const_lv6_25 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_25;
end else if ((ap_const_lv6_24 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_24;
end else if ((ap_const_lv6_23 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_23;
end else if ((ap_const_lv6_22 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_22;
end else if ((ap_const_lv6_21 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_21;
end else if ((ap_const_lv6_20 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_20;
end else if ((ap_const_lv6_1F == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_1F;
end else if ((ap_const_lv6_1E == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_1E;
end else if ((ap_const_lv6_1D == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_1D;
end else if ((ap_const_lv6_1C == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_1C;
end else if ((ap_const_lv6_1B == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_1B;
end else if ((ap_const_lv6_1A == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_1A;
end else if ((ap_const_lv6_19 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_19;
end else if ((ap_const_lv6_18 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_18;
end else if ((ap_const_lv6_17 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_17;
end else if ((ap_const_lv6_16 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_16;
end else if ((ap_const_lv6_15 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_15;
end else if ((ap_const_lv6_14 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_14;
end else if ((ap_const_lv6_13 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_13;
end else if ((ap_const_lv6_12 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_12;
end else if ((ap_const_lv6_11 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_11;
end else if ((ap_const_lv6_10 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_10;
end else if ((ap_const_lv6_F == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_F;
end else if ((ap_const_lv6_E == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_E;
end else if ((ap_const_lv6_D == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_D;
end else if ((ap_const_lv6_C == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_C;
end else if ((ap_const_lv6_B == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_B;
end else if ((ap_const_lv6_A == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_A;
end else if ((ap_const_lv6_9 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_9;
end else if ((ap_const_lv6_8 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_8;
end else if ((ap_const_lv6_7 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_7;
end else if ((ap_const_lv6_6 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_6;
end else if ((ap_const_lv6_5 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_5;
end else if ((ap_const_lv6_4 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_4;
end else if ((ap_const_lv6_3 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_3;
end else if ((ap_const_lv6_2 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_2;
end else if ((ap_const_lv6_1 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_1;
end else if ((ap_const_lv6_0 == a_winid_V_14_cast_fu_16902_p1)) begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_const_lv6_0;
end else begin
ranki_l1_14_V_phi_fu_3516_p128 = ap_reg_phiprechg_ranki_l1_14_V_reg_3513pp0_it1;
end
end
always @ (*) begin
if ((~(ap_const_lv3_4 == a_winid_V_1_1_phi_fu_12127_p8) & ~(ap_const_lv3_5 == a_winid_V_1_1_phi_fu_12127_p8) & ~(ap_const_lv3_6 == a_winid_V_1_1_phi_fu_12127_p8) & ~(ap_const_lv3_7 == a_winid_V_1_1_phi_fu_12127_p8))) begin
ranki_l1_1_V_1_phi_fu_12144_p10 = ap_const_lv4_F;
end else if ((ap_const_lv3_7 == a_winid_V_1_1_phi_fu_12127_p8)) begin
ranki_l1_1_V_1_phi_fu_12144_p10 = ap_const_lv4_7;
end else if ((ap_const_lv3_6 == a_winid_V_1_1_phi_fu_12127_p8)) begin
ranki_l1_1_V_1_phi_fu_12144_p10 = ap_const_lv4_6;
end else if ((ap_const_lv3_5 == a_winid_V_1_1_phi_fu_12127_p8)) begin
ranki_l1_1_V_1_phi_fu_12144_p10 = ap_const_lv4_5;
end else if ((ap_const_lv3_4 == a_winid_V_1_1_phi_fu_12127_p8)) begin
ranki_l1_1_V_1_phi_fu_12144_p10 = ap_const_lv4_4;
end else begin
ranki_l1_1_V_1_phi_fu_12144_p10 = ap_reg_phiprechg_ranki_l1_1_V_1_reg_12141pp0_it1;
end
end
always @ (*) begin
if ((~(a_winid_V_s_phi_fu_1542_p8 == ap_const_lv3_4) & ~(a_winid_V_s_phi_fu_1542_p8 == ap_const_lv3_5) & ~(a_winid_V_s_phi_fu_1542_p8 == ap_const_lv3_6) & ~(ap_const_lv3_7 == a_winid_V_s_phi_fu_1542_p8))) begin
ranki_l1_1_V_phi_fu_1559_p10 = ap_const_lv4_F;
end else if ((ap_const_lv3_7 == a_winid_V_s_phi_fu_1542_p8)) begin
ranki_l1_1_V_phi_fu_1559_p10 = ap_const_lv4_7;
end else if ((a_winid_V_s_phi_fu_1542_p8 == ap_const_lv3_6)) begin
ranki_l1_1_V_phi_fu_1559_p10 = ap_const_lv4_6;
end else if ((a_winid_V_s_phi_fu_1542_p8 == ap_const_lv3_5)) begin
ranki_l1_1_V_phi_fu_1559_p10 = ap_const_lv4_5;
end else if ((a_winid_V_s_phi_fu_1542_p8 == ap_const_lv3_4)) begin
ranki_l1_1_V_phi_fu_1559_p10 = ap_const_lv4_4;
end else begin
ranki_l1_1_V_phi_fu_1559_p10 = ap_reg_phiprechg_ranki_l1_1_V_reg_1556pp0_it1;
end
end
always @ (*) begin
if ((~(ap_const_lv4_8 == a_winid_V_1_2_phi_fu_12181_p8) & ~(ap_const_lv4_9 == a_winid_V_1_2_phi_fu_12181_p8) & ~(ap_const_lv4_A == a_winid_V_1_2_phi_fu_12181_p8) & ~(ap_const_lv4_B == a_winid_V_1_2_phi_fu_12181_p8))) begin
ranki_l1_2_V_1_phi_fu_12198_p10 = ap_const_lv5_1F;
end else if ((ap_const_lv4_B == a_winid_V_1_2_phi_fu_12181_p8)) begin
ranki_l1_2_V_1_phi_fu_12198_p10 = ap_const_lv5_B;
end else if ((ap_const_lv4_A == a_winid_V_1_2_phi_fu_12181_p8)) begin
ranki_l1_2_V_1_phi_fu_12198_p10 = ap_const_lv5_A;
end else if ((ap_const_lv4_9 == a_winid_V_1_2_phi_fu_12181_p8)) begin
ranki_l1_2_V_1_phi_fu_12198_p10 = ap_const_lv5_9;
end else if ((ap_const_lv4_8 == a_winid_V_1_2_phi_fu_12181_p8)) begin
ranki_l1_2_V_1_phi_fu_12198_p10 = ap_const_lv5_8;
end else begin
ranki_l1_2_V_1_phi_fu_12198_p10 = ap_reg_phiprechg_ranki_l1_2_V_1_reg_12195pp0_it1;
end
end
always @ (*) begin
if ((~(a_winid_V_2_phi_fu_1596_p8 == ap_const_lv4_8) & ~(a_winid_V_2_phi_fu_1596_p8 == ap_const_lv4_9) & ~(a_winid_V_2_phi_fu_1596_p8 == ap_const_lv4_A) & ~(ap_const_lv4_B == a_winid_V_2_phi_fu_1596_p8))) begin
ranki_l1_2_V_phi_fu_1613_p10 = ap_const_lv5_1F;
end else if ((ap_const_lv4_B == a_winid_V_2_phi_fu_1596_p8)) begin
ranki_l1_2_V_phi_fu_1613_p10 = ap_const_lv5_B;
end else if ((a_winid_V_2_phi_fu_1596_p8 == ap_const_lv4_A)) begin
ranki_l1_2_V_phi_fu_1613_p10 = ap_const_lv5_A;
end else if ((a_winid_V_2_phi_fu_1596_p8 == ap_const_lv4_9)) begin
ranki_l1_2_V_phi_fu_1613_p10 = ap_const_lv5_9;
end else if ((a_winid_V_2_phi_fu_1596_p8 == ap_const_lv4_8)) begin
ranki_l1_2_V_phi_fu_1613_p10 = ap_const_lv5_8;
end else begin
ranki_l1_2_V_phi_fu_1613_p10 = ap_reg_phiprechg_ranki_l1_2_V_reg_1610pp0_it1;
end
end
always @ (*) begin
if ((~(ap_const_lv3_4 == a_winid_V_1_3_phi_fu_12235_p8) & ~(ap_const_lv3_5 == a_winid_V_1_3_phi_fu_12235_p8) & ~(ap_const_lv3_6 == a_winid_V_1_3_phi_fu_12235_p8) & ~(ap_const_lv3_7 == a_winid_V_1_3_phi_fu_12235_p8))) begin
ranki_l1_3_V_1_phi_fu_12252_p10 = ap_const_lv5_1F;
end else if ((ap_const_lv3_7 == a_winid_V_1_3_phi_fu_12235_p8)) begin
ranki_l1_3_V_1_phi_fu_12252_p10 = ap_const_lv5_F;
end else if ((ap_const_lv3_6 == a_winid_V_1_3_phi_fu_12235_p8)) begin
ranki_l1_3_V_1_phi_fu_12252_p10 = ap_const_lv5_E;
end else if ((ap_const_lv3_5 == a_winid_V_1_3_phi_fu_12235_p8)) begin
ranki_l1_3_V_1_phi_fu_12252_p10 = ap_const_lv5_D;
end else if ((ap_const_lv3_4 == a_winid_V_1_3_phi_fu_12235_p8)) begin
ranki_l1_3_V_1_phi_fu_12252_p10 = ap_const_lv5_C;
end else begin
ranki_l1_3_V_1_phi_fu_12252_p10 = ap_reg_phiprechg_ranki_l1_3_V_1_reg_12249pp0_it1;
end
end
always @ (*) begin
if ((~(ap_const_lv3_4 == a_winid_V_3_phi_fu_1650_p8) & ~(ap_const_lv3_5 == a_winid_V_3_phi_fu_1650_p8) & ~(ap_const_lv3_6 == a_winid_V_3_phi_fu_1650_p8) & ~(ap_const_lv3_7 == a_winid_V_3_phi_fu_1650_p8))) begin
ranki_l1_3_V_phi_fu_1667_p10 = ap_const_lv5_1F;
end else if ((ap_const_lv3_7 == a_winid_V_3_phi_fu_1650_p8)) begin
ranki_l1_3_V_phi_fu_1667_p10 = ap_const_lv5_F;
end else if ((ap_const_lv3_6 == a_winid_V_3_phi_fu_1650_p8)) begin
ranki_l1_3_V_phi_fu_1667_p10 = ap_const_lv5_E;
end else if ((ap_const_lv3_5 == a_winid_V_3_phi_fu_1650_p8)) begin
ranki_l1_3_V_phi_fu_1667_p10 = ap_const_lv5_D;
end else if ((ap_const_lv3_4 == a_winid_V_3_phi_fu_1650_p8)) begin
ranki_l1_3_V_phi_fu_1667_p10 = ap_const_lv5_C;
end else begin
ranki_l1_3_V_phi_fu_1667_p10 = ap_reg_phiprechg_ranki_l1_3_V_reg_1664pp0_it1;
end
end
always @ (*) begin
if (~(1'b1 == 1'b1)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_3F;
end else if ((ap_const_lv5_1F == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_1F;
end else if ((ap_const_lv5_1E == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_1E;
end else if ((ap_const_lv5_1D == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_1D;
end else if ((ap_const_lv5_1C == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_1C;
end else if ((ap_const_lv5_1B == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_1B;
end else if ((ap_const_lv5_1A == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_1A;
end else if ((ap_const_lv5_19 == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_19;
end else if ((ap_const_lv5_18 == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_18;
end else if ((ap_const_lv5_17 == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_17;
end else if ((ap_const_lv5_16 == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_16;
end else if ((ap_const_lv5_15 == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_15;
end else if ((ap_const_lv5_14 == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_14;
end else if ((ap_const_lv5_13 == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_13;
end else if ((ap_const_lv5_12 == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_12;
end else if ((ap_const_lv5_11 == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_11;
end else if ((ap_const_lv5_10 == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_10;
end else if ((ap_const_lv5_F == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_F;
end else if ((ap_const_lv5_E == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_E;
end else if ((ap_const_lv5_D == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_D;
end else if ((ap_const_lv5_C == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_C;
end else if ((ap_const_lv5_B == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_B;
end else if ((ap_const_lv5_A == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_A;
end else if ((ap_const_lv5_9 == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_9;
end else if ((ap_const_lv5_8 == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_8;
end else if ((ap_const_lv5_7 == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_7;
end else if ((ap_const_lv5_6 == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_6;
end else if ((ap_const_lv5_5 == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_5;
end else if ((ap_const_lv5_4 == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_4;
end else if ((ap_const_lv5_3 == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_3;
end else if ((ap_const_lv5_2 == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_2;
end else if ((ap_const_lv5_1 == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_1;
end else if ((ap_const_lv5_0 == a_winid_V_1_4_phi_fu_12289_p8)) begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_const_lv6_0;
end else begin
ranki_l1_4_V_1_phi_fu_12306_p66 = ap_reg_phiprechg_ranki_l1_4_V_1_reg_12303pp0_it1;
end
end
always @ (*) begin
if (~(1'b1 == 1'b1)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_3F;
end else if ((ap_const_lv5_1F == a_winid_V_4_phi_fu_1691_p8)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_1F;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_1E)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_1E;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_1D)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_1D;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_1C)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_1C;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_1B)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_1B;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_1A)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_1A;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_19)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_19;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_18)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_18;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_17)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_17;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_16)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_16;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_15)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_15;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_14)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_14;
end else if ((ap_const_lv5_13 == a_winid_V_4_phi_fu_1691_p8)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_13;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_12)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_12;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_11)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_11;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_10)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_10;
end else if ((ap_const_lv5_F == a_winid_V_4_phi_fu_1691_p8)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_F;
end else if ((ap_const_lv5_E == a_winid_V_4_phi_fu_1691_p8)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_E;
end else if ((ap_const_lv5_D == a_winid_V_4_phi_fu_1691_p8)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_D;
end else if ((ap_const_lv5_C == a_winid_V_4_phi_fu_1691_p8)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_C;
end else if ((ap_const_lv5_B == a_winid_V_4_phi_fu_1691_p8)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_B;
end else if ((ap_const_lv5_A == a_winid_V_4_phi_fu_1691_p8)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_A;
end else if ((ap_const_lv5_9 == a_winid_V_4_phi_fu_1691_p8)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_9;
end else if ((ap_const_lv5_8 == a_winid_V_4_phi_fu_1691_p8)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_8;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_7)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_7;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_6)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_6;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_5)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_5;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_4)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_4;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_3)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_3;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_2)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_2;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_1)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_1;
end else if ((a_winid_V_4_phi_fu_1691_p8 == ap_const_lv5_0)) begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_const_lv6_0;
end else begin
ranki_l1_4_V_phi_fu_1708_p66 = ap_reg_phiprechg_ranki_l1_4_V_reg_1705pp0_it1;
end
end
always @ (*) begin
if (~(1'b1 == 1'b1)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_3F;
end else if ((ap_const_lv5_1F == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_1F;
end else if ((ap_const_lv5_1E == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_1E;
end else if ((ap_const_lv5_1D == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_1D;
end else if ((ap_const_lv5_1C == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_1C;
end else if ((ap_const_lv5_1B == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_1B;
end else if ((ap_const_lv5_1A == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_1A;
end else if ((ap_const_lv5_19 == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_19;
end else if ((ap_const_lv5_18 == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_18;
end else if ((ap_const_lv5_17 == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_17;
end else if ((ap_const_lv5_16 == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_16;
end else if ((ap_const_lv5_15 == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_15;
end else if ((ap_const_lv5_14 == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_14;
end else if ((ap_const_lv5_13 == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_13;
end else if ((ap_const_lv5_12 == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_12;
end else if ((ap_const_lv5_11 == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_11;
end else if ((ap_const_lv5_10 == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_10;
end else if ((ap_const_lv5_F == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_F;
end else if ((ap_const_lv5_E == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_E;
end else if ((ap_const_lv5_D == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_D;
end else if ((ap_const_lv5_C == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_C;
end else if ((ap_const_lv5_B == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_B;
end else if ((ap_const_lv5_A == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_A;
end else if ((ap_const_lv5_9 == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_9;
end else if ((ap_const_lv5_8 == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_8;
end else if ((ap_const_lv5_7 == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_7;
end else if ((ap_const_lv5_6 == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_6;
end else if ((ap_const_lv5_5 == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_5;
end else if ((ap_const_lv5_4 == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_4;
end else if ((ap_const_lv5_3 == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_3;
end else if ((ap_const_lv5_2 == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_2;
end else if ((ap_const_lv5_1 == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_1;
end else if ((ap_const_lv5_0 == a_winid_V_1_5_phi_fu_12427_p8)) begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_const_lv6_0;
end else begin
ranki_l1_5_V_1_phi_fu_12444_p66 = ap_reg_phiprechg_ranki_l1_5_V_1_reg_12441pp0_it1;
end
end
always @ (*) begin
if (~(1'b1 == 1'b1)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_3F;
end else if ((ap_const_lv5_1F == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_1F;
end else if ((ap_const_lv5_1E == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_1E;
end else if ((ap_const_lv5_1D == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_1D;
end else if ((ap_const_lv5_1C == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_1C;
end else if ((ap_const_lv5_1B == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_1B;
end else if ((ap_const_lv5_1A == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_1A;
end else if ((ap_const_lv5_19 == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_19;
end else if ((ap_const_lv5_18 == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_18;
end else if ((ap_const_lv5_17 == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_17;
end else if ((ap_const_lv5_16 == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_16;
end else if ((ap_const_lv5_15 == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_15;
end else if ((ap_const_lv5_14 == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_14;
end else if ((ap_const_lv5_13 == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_13;
end else if ((ap_const_lv5_12 == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_12;
end else if ((ap_const_lv5_11 == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_11;
end else if ((ap_const_lv5_10 == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_10;
end else if ((ap_const_lv5_F == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_F;
end else if ((ap_const_lv5_E == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_E;
end else if ((ap_const_lv5_D == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_D;
end else if ((ap_const_lv5_C == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_C;
end else if ((ap_const_lv5_B == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_B;
end else if ((ap_const_lv5_A == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_A;
end else if ((ap_const_lv5_9 == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_9;
end else if ((ap_const_lv5_8 == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_8;
end else if ((ap_const_lv5_7 == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_7;
end else if ((ap_const_lv5_6 == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_6;
end else if ((ap_const_lv5_5 == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_5;
end else if ((ap_const_lv5_4 == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_4;
end else if ((ap_const_lv5_3 == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_3;
end else if ((ap_const_lv5_2 == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_2;
end else if ((ap_const_lv5_1 == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_1;
end else if ((ap_const_lv5_0 == a_winid_V_5_phi_fu_1816_p8)) begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_const_lv6_0;
end else begin
ranki_l1_5_V_phi_fu_1833_p66 = ap_reg_phiprechg_ranki_l1_5_V_reg_1830pp0_it1;
end
end
always @ (*) begin
if (~(1'b1 == 1'b1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_3F;
end else if ((ap_const_lv5_1F == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_1F;
end else if ((ap_const_lv5_1E == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_1E;
end else if ((ap_const_lv5_1D == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_1D;
end else if ((ap_const_lv5_1C == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_1C;
end else if ((ap_const_lv5_1B == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_1B;
end else if ((ap_const_lv5_1A == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_1A;
end else if ((ap_const_lv5_19 == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_19;
end else if ((ap_const_lv5_18 == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_18;
end else if ((ap_const_lv5_17 == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_17;
end else if ((ap_const_lv5_16 == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_16;
end else if ((ap_const_lv5_15 == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_15;
end else if ((ap_const_lv5_14 == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_14;
end else if ((ap_const_lv5_13 == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_13;
end else if ((ap_const_lv5_12 == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_12;
end else if ((ap_const_lv5_11 == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_11;
end else if ((ap_const_lv5_10 == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_10;
end else if ((ap_const_lv5_F == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_F;
end else if ((ap_const_lv5_E == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_E;
end else if ((ap_const_lv5_D == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_D;
end else if ((ap_const_lv5_C == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_C;
end else if ((ap_const_lv5_B == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_B;
end else if ((ap_const_lv5_A == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_A;
end else if ((ap_const_lv5_9 == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_9;
end else if ((ap_const_lv5_8 == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_8;
end else if ((ap_const_lv5_7 == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_7;
end else if ((ap_const_lv5_6 == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_6;
end else if ((ap_const_lv5_5 == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_5;
end else if ((ap_const_lv5_4 == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_4;
end else if ((ap_const_lv5_3 == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_3;
end else if ((ap_const_lv5_2 == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_2;
end else if ((ap_const_lv5_1 == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_1;
end else if ((ap_const_lv5_0 == a_winid_V_1_6_cast_fu_17947_p1)) begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_const_lv6_0;
end else begin
ranki_l1_6_V_1_phi_fu_12582_p66 = ap_reg_phiprechg_ranki_l1_6_V_1_reg_12579pp0_it1;
end
end
always @ (*) begin
if (~(1'b1 == 1'b1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_3F;
end else if ((ap_const_lv5_1F == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_1F;
end else if ((ap_const_lv5_1E == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_1E;
end else if ((ap_const_lv5_1D == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_1D;
end else if ((ap_const_lv5_1C == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_1C;
end else if ((ap_const_lv5_1B == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_1B;
end else if ((ap_const_lv5_1A == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_1A;
end else if ((ap_const_lv5_19 == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_19;
end else if ((ap_const_lv5_18 == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_18;
end else if ((ap_const_lv5_17 == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_17;
end else if ((ap_const_lv5_16 == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_16;
end else if ((ap_const_lv5_15 == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_15;
end else if ((ap_const_lv5_14 == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_14;
end else if ((ap_const_lv5_13 == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_13;
end else if ((ap_const_lv5_12 == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_12;
end else if ((ap_const_lv5_11 == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_11;
end else if ((ap_const_lv5_10 == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_10;
end else if ((ap_const_lv5_F == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_F;
end else if ((ap_const_lv5_E == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_E;
end else if ((ap_const_lv5_D == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_D;
end else if ((ap_const_lv5_C == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_C;
end else if ((ap_const_lv5_B == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_B;
end else if ((ap_const_lv5_A == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_A;
end else if ((ap_const_lv5_9 == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_9;
end else if ((ap_const_lv5_8 == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_8;
end else if ((ap_const_lv5_7 == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_7;
end else if ((ap_const_lv5_6 == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_6;
end else if ((ap_const_lv5_5 == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_5;
end else if ((ap_const_lv5_4 == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_4;
end else if ((ap_const_lv5_3 == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_3;
end else if ((ap_const_lv5_2 == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_2;
end else if ((ap_const_lv5_1 == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_1;
end else if ((ap_const_lv5_0 == a_winid_V_6_cast_fu_16854_p1)) begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_const_lv6_0;
end else begin
ranki_l1_6_V_phi_fu_1958_p66 = ap_reg_phiprechg_ranki_l1_6_V_reg_1955pp0_it1;
end
end
always @ (*) begin
if (~(1'b1 == 1'b1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_3F;
end else if ((ap_const_lv5_1F == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_1F;
end else if ((ap_const_lv5_1E == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_1E;
end else if ((ap_const_lv5_1D == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_1D;
end else if ((ap_const_lv5_1C == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_1C;
end else if ((ap_const_lv5_1B == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_1B;
end else if ((ap_const_lv5_1A == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_1A;
end else if ((ap_const_lv5_19 == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_19;
end else if ((ap_const_lv5_18 == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_18;
end else if ((ap_const_lv5_17 == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_17;
end else if ((ap_const_lv5_16 == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_16;
end else if ((ap_const_lv5_15 == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_15;
end else if ((ap_const_lv5_14 == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_14;
end else if ((ap_const_lv5_13 == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_13;
end else if ((ap_const_lv5_12 == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_12;
end else if ((ap_const_lv5_11 == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_11;
end else if ((ap_const_lv5_10 == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_10;
end else if ((ap_const_lv5_F == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_F;
end else if ((ap_const_lv5_E == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_E;
end else if ((ap_const_lv5_D == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_D;
end else if ((ap_const_lv5_C == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_C;
end else if ((ap_const_lv5_B == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_B;
end else if ((ap_const_lv5_A == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_A;
end else if ((ap_const_lv5_9 == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_9;
end else if ((ap_const_lv5_8 == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_8;
end else if ((ap_const_lv5_7 == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_7;
end else if ((ap_const_lv5_6 == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_6;
end else if ((ap_const_lv5_5 == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_5;
end else if ((ap_const_lv5_4 == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_4;
end else if ((ap_const_lv5_3 == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_3;
end else if ((ap_const_lv5_2 == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_2;
end else if ((ap_const_lv5_1 == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_1;
end else if ((ap_const_lv5_0 == a_winid_V_1_7_cast_fu_18027_p1)) begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_const_lv6_0;
end else begin
ranki_l1_7_V_1_phi_fu_12720_p66 = ap_reg_phiprechg_ranki_l1_7_V_1_reg_12717pp0_it1;
end
end
always @ (*) begin
if (~(1'b1 == 1'b1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_3F;
end else if ((ap_const_lv5_1F == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_1F;
end else if ((ap_const_lv5_1E == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_1E;
end else if ((ap_const_lv5_1D == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_1D;
end else if ((ap_const_lv5_1C == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_1C;
end else if ((ap_const_lv5_1B == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_1B;
end else if ((ap_const_lv5_1A == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_1A;
end else if ((ap_const_lv5_19 == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_19;
end else if ((ap_const_lv5_18 == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_18;
end else if ((ap_const_lv5_17 == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_17;
end else if ((ap_const_lv5_16 == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_16;
end else if ((ap_const_lv5_15 == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_15;
end else if ((ap_const_lv5_14 == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_14;
end else if ((ap_const_lv5_13 == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_13;
end else if ((ap_const_lv5_12 == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_12;
end else if ((ap_const_lv5_11 == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_11;
end else if ((ap_const_lv5_10 == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_10;
end else if ((ap_const_lv5_F == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_F;
end else if ((ap_const_lv5_E == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_E;
end else if ((ap_const_lv5_D == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_D;
end else if ((ap_const_lv5_C == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_C;
end else if ((ap_const_lv5_B == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_B;
end else if ((ap_const_lv5_A == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_A;
end else if ((ap_const_lv5_9 == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_9;
end else if ((ap_const_lv5_8 == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_8;
end else if ((ap_const_lv5_7 == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_7;
end else if ((ap_const_lv5_6 == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_6;
end else if ((ap_const_lv5_5 == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_5;
end else if ((ap_const_lv5_4 == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_4;
end else if ((ap_const_lv5_3 == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_3;
end else if ((ap_const_lv5_2 == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_2;
end else if ((ap_const_lv5_1 == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_1;
end else if ((ap_const_lv5_0 == a_winid_V_7_cast_fu_16862_p1)) begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_const_lv6_0;
end else begin
ranki_l1_7_V_phi_fu_2083_p66 = ap_reg_phiprechg_ranki_l1_7_V_reg_2080pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_3F == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_3F;
end else if ((ap_const_lv6_3E == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_3E;
end else if ((ap_const_lv6_3D == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_3D;
end else if ((ap_const_lv6_3C == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_3C;
end else if ((ap_const_lv6_3B == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_3B;
end else if ((ap_const_lv6_3A == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_3A;
end else if ((ap_const_lv6_39 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_39;
end else if ((ap_const_lv6_38 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_38;
end else if ((ap_const_lv6_37 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_37;
end else if ((ap_const_lv6_36 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_36;
end else if ((ap_const_lv6_35 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_35;
end else if ((ap_const_lv6_34 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_34;
end else if ((ap_const_lv6_33 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_33;
end else if ((ap_const_lv6_32 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_32;
end else if ((ap_const_lv6_31 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_31;
end else if ((ap_const_lv6_30 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_30;
end else if ((ap_const_lv6_2F == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_2F;
end else if ((ap_const_lv6_2E == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_2E;
end else if ((ap_const_lv6_2D == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_2D;
end else if ((ap_const_lv6_2C == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_2C;
end else if ((ap_const_lv6_2B == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_2B;
end else if ((ap_const_lv6_2A == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_2A;
end else if ((ap_const_lv6_29 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_29;
end else if ((ap_const_lv6_28 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_28;
end else if ((ap_const_lv6_27 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_27;
end else if ((ap_const_lv6_26 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_26;
end else if ((ap_const_lv6_25 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_25;
end else if ((ap_const_lv6_24 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_24;
end else if ((ap_const_lv6_23 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_23;
end else if ((ap_const_lv6_22 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_22;
end else if ((ap_const_lv6_21 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_21;
end else if ((ap_const_lv6_20 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_20;
end else if ((ap_const_lv6_1F == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_1F;
end else if ((ap_const_lv6_1E == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_1E;
end else if ((ap_const_lv6_1D == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_1D;
end else if ((ap_const_lv6_1C == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_1C;
end else if ((ap_const_lv6_1B == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_1B;
end else if ((ap_const_lv6_1A == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_1A;
end else if ((ap_const_lv6_19 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_19;
end else if ((ap_const_lv6_18 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_18;
end else if ((ap_const_lv6_17 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_17;
end else if ((ap_const_lv6_16 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_16;
end else if ((ap_const_lv6_15 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_15;
end else if ((ap_const_lv6_14 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_14;
end else if ((ap_const_lv6_13 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_13;
end else if ((ap_const_lv6_12 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_12;
end else if ((ap_const_lv6_11 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_11;
end else if ((ap_const_lv6_10 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_10;
end else if ((ap_const_lv6_F == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_F;
end else if ((ap_const_lv6_E == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_E;
end else if ((ap_const_lv6_D == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_D;
end else if ((ap_const_lv6_C == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_C;
end else if ((ap_const_lv6_B == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_B;
end else if ((ap_const_lv6_A == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_A;
end else if ((ap_const_lv6_9 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_9;
end else if ((ap_const_lv6_8 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_8;
end else if ((ap_const_lv6_7 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_7;
end else if ((ap_const_lv6_6 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_6;
end else if ((ap_const_lv6_5 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_5;
end else if ((ap_const_lv6_4 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_4;
end else if ((ap_const_lv6_3 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_3;
end else if ((ap_const_lv6_2 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_2;
end else if ((ap_const_lv6_1 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_1;
end else if ((ap_const_lv6_0 == a_winid_V_1_8_phi_fu_12841_p8)) begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_const_lv6_0;
end else begin
ranki_l1_8_V_1_phi_fu_12858_p128 = ap_reg_phiprechg_ranki_l1_8_V_1_reg_12855pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_3F == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_3F;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_3E)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_3E;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_3D)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_3D;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_3C)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_3C;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_3B)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_3B;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_3A)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_3A;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_39)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_39;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_38)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_38;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_37)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_37;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_36)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_36;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_35)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_35;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_34)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_34;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_33)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_33;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_32)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_32;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_31)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_31;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_30)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_30;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_2F)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_2F;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_2E)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_2E;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_2D)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_2D;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_2C)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_2C;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_2B)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_2B;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_2A)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_2A;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_29)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_29;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_28)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_28;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_27)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_27;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_26)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_26;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_25)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_25;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_24)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_24;
end else if ((ap_const_lv6_23 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_23;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_22)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_22;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_21)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_21;
end else if ((a_winid_V_8_phi_fu_2191_p8 == ap_const_lv6_20)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_20;
end else if ((ap_const_lv6_1F == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_1F;
end else if ((ap_const_lv6_1E == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_1E;
end else if ((ap_const_lv6_1D == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_1D;
end else if ((ap_const_lv6_1C == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_1C;
end else if ((ap_const_lv6_1B == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_1B;
end else if ((ap_const_lv6_1A == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_1A;
end else if ((ap_const_lv6_19 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_19;
end else if ((ap_const_lv6_18 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_18;
end else if ((ap_const_lv6_17 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_17;
end else if ((ap_const_lv6_16 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_16;
end else if ((ap_const_lv6_15 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_15;
end else if ((ap_const_lv6_14 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_14;
end else if ((ap_const_lv6_13 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_13;
end else if ((ap_const_lv6_12 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_12;
end else if ((ap_const_lv6_11 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_11;
end else if ((ap_const_lv6_10 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_10;
end else if ((ap_const_lv6_F == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_F;
end else if ((ap_const_lv6_E == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_E;
end else if ((ap_const_lv6_D == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_D;
end else if ((ap_const_lv6_C == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_C;
end else if ((ap_const_lv6_B == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_B;
end else if ((ap_const_lv6_A == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_A;
end else if ((ap_const_lv6_9 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_9;
end else if ((ap_const_lv6_8 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_8;
end else if ((ap_const_lv6_7 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_7;
end else if ((ap_const_lv6_6 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_6;
end else if ((ap_const_lv6_5 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_5;
end else if ((ap_const_lv6_4 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_4;
end else if ((ap_const_lv6_3 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_3;
end else if ((ap_const_lv6_2 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_2;
end else if ((ap_const_lv6_1 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_1;
end else if ((ap_const_lv6_0 == a_winid_V_8_phi_fu_2191_p8)) begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_const_lv6_0;
end else begin
ranki_l1_8_V_phi_fu_2208_p128 = ap_reg_phiprechg_ranki_l1_8_V_reg_2205pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_3F == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_3F;
end else if ((ap_const_lv6_3E == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_3E;
end else if ((ap_const_lv6_3D == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_3D;
end else if ((ap_const_lv6_3C == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_3C;
end else if ((ap_const_lv6_3B == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_3B;
end else if ((ap_const_lv6_3A == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_3A;
end else if ((ap_const_lv6_39 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_39;
end else if ((ap_const_lv6_38 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_38;
end else if ((ap_const_lv6_37 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_37;
end else if ((ap_const_lv6_36 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_36;
end else if ((ap_const_lv6_35 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_35;
end else if ((ap_const_lv6_34 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_34;
end else if ((ap_const_lv6_33 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_33;
end else if ((ap_const_lv6_32 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_32;
end else if ((ap_const_lv6_31 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_31;
end else if ((ap_const_lv6_30 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_30;
end else if ((ap_const_lv6_2F == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_2F;
end else if ((ap_const_lv6_2E == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_2E;
end else if ((ap_const_lv6_2D == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_2D;
end else if ((ap_const_lv6_2C == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_2C;
end else if ((ap_const_lv6_2B == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_2B;
end else if ((ap_const_lv6_2A == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_2A;
end else if ((ap_const_lv6_29 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_29;
end else if ((ap_const_lv6_28 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_28;
end else if ((ap_const_lv6_27 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_27;
end else if ((ap_const_lv6_26 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_26;
end else if ((ap_const_lv6_25 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_25;
end else if ((ap_const_lv6_24 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_24;
end else if ((ap_const_lv6_23 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_23;
end else if ((ap_const_lv6_22 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_22;
end else if ((ap_const_lv6_21 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_21;
end else if ((ap_const_lv6_20 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_20;
end else if ((ap_const_lv6_1F == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_1F;
end else if ((ap_const_lv6_1E == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_1E;
end else if ((ap_const_lv6_1D == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_1D;
end else if ((ap_const_lv6_1C == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_1C;
end else if ((ap_const_lv6_1B == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_1B;
end else if ((ap_const_lv6_1A == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_1A;
end else if ((ap_const_lv6_19 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_19;
end else if ((ap_const_lv6_18 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_18;
end else if ((ap_const_lv6_17 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_17;
end else if ((ap_const_lv6_16 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_16;
end else if ((ap_const_lv6_15 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_15;
end else if ((ap_const_lv6_14 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_14;
end else if ((ap_const_lv6_13 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_13;
end else if ((ap_const_lv6_12 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_12;
end else if ((ap_const_lv6_11 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_11;
end else if ((ap_const_lv6_10 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_10;
end else if ((ap_const_lv6_F == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_F;
end else if ((ap_const_lv6_E == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_E;
end else if ((ap_const_lv6_D == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_D;
end else if ((ap_const_lv6_C == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_C;
end else if ((ap_const_lv6_B == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_B;
end else if ((ap_const_lv6_A == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_A;
end else if ((ap_const_lv6_9 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_9;
end else if ((ap_const_lv6_8 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_8;
end else if ((ap_const_lv6_7 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_7;
end else if ((ap_const_lv6_6 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_6;
end else if ((ap_const_lv6_5 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_5;
end else if ((ap_const_lv6_4 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_4;
end else if ((ap_const_lv6_3 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_3;
end else if ((ap_const_lv6_2 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_2;
end else if ((ap_const_lv6_1 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_1;
end else if ((ap_const_lv6_0 == a_winid_V_1_9_phi_fu_13072_p8)) begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_const_lv6_0;
end else begin
ranki_l1_9_V_1_phi_fu_13089_p128 = ap_reg_phiprechg_ranki_l1_9_V_1_reg_13086pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_3F == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_3F;
end else if ((ap_const_lv6_3E == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_3E;
end else if ((ap_const_lv6_3D == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_3D;
end else if ((ap_const_lv6_3C == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_3C;
end else if ((ap_const_lv6_3B == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_3B;
end else if ((ap_const_lv6_3A == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_3A;
end else if ((ap_const_lv6_39 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_39;
end else if ((ap_const_lv6_38 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_38;
end else if ((ap_const_lv6_37 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_37;
end else if ((ap_const_lv6_36 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_36;
end else if ((ap_const_lv6_35 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_35;
end else if ((ap_const_lv6_34 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_34;
end else if ((ap_const_lv6_33 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_33;
end else if ((ap_const_lv6_32 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_32;
end else if ((ap_const_lv6_31 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_31;
end else if ((ap_const_lv6_30 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_30;
end else if ((ap_const_lv6_2F == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_2F;
end else if ((ap_const_lv6_2E == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_2E;
end else if ((ap_const_lv6_2D == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_2D;
end else if ((ap_const_lv6_2C == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_2C;
end else if ((ap_const_lv6_2B == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_2B;
end else if ((ap_const_lv6_2A == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_2A;
end else if ((ap_const_lv6_29 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_29;
end else if ((ap_const_lv6_28 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_28;
end else if ((ap_const_lv6_27 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_27;
end else if ((ap_const_lv6_26 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_26;
end else if ((ap_const_lv6_25 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_25;
end else if ((ap_const_lv6_24 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_24;
end else if ((ap_const_lv6_23 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_23;
end else if ((ap_const_lv6_22 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_22;
end else if ((ap_const_lv6_21 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_21;
end else if ((ap_const_lv6_20 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_20;
end else if ((ap_const_lv6_1F == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_1F;
end else if ((ap_const_lv6_1E == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_1E;
end else if ((ap_const_lv6_1D == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_1D;
end else if ((ap_const_lv6_1C == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_1C;
end else if ((ap_const_lv6_1B == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_1B;
end else if ((ap_const_lv6_1A == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_1A;
end else if ((ap_const_lv6_19 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_19;
end else if ((ap_const_lv6_18 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_18;
end else if ((ap_const_lv6_17 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_17;
end else if ((ap_const_lv6_16 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_16;
end else if ((ap_const_lv6_15 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_15;
end else if ((ap_const_lv6_14 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_14;
end else if ((ap_const_lv6_13 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_13;
end else if ((ap_const_lv6_12 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_12;
end else if ((ap_const_lv6_11 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_11;
end else if ((ap_const_lv6_10 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_10;
end else if ((ap_const_lv6_F == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_F;
end else if ((ap_const_lv6_E == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_E;
end else if ((ap_const_lv6_D == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_D;
end else if ((ap_const_lv6_C == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_C;
end else if ((ap_const_lv6_B == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_B;
end else if ((ap_const_lv6_A == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_A;
end else if ((ap_const_lv6_9 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_9;
end else if ((ap_const_lv6_8 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_8;
end else if ((ap_const_lv6_7 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_7;
end else if ((ap_const_lv6_6 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_6;
end else if ((ap_const_lv6_5 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_5;
end else if ((ap_const_lv6_4 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_4;
end else if ((ap_const_lv6_3 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_3;
end else if ((ap_const_lv6_2 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_2;
end else if ((ap_const_lv6_1 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_1;
end else if ((ap_const_lv6_0 == a_winid_V_9_phi_fu_2409_p8)) begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_const_lv6_0;
end else begin
ranki_l1_9_V_phi_fu_2426_p128 = ap_reg_phiprechg_ranki_l1_9_V_reg_2423pp0_it1;
end
end
always @ (*) begin
if ((tmp_2772_fu_17361_p2 == ap_const_lv7_0)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_0_V_read_1_reg_19963;
end else if ((~(tmp_2772_fu_17361_p2 == ap_const_lv7_0) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_2) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_4) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_6) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_8) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_A) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_C) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_E) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_10) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_12) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_14) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_16) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_18) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_1A) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_1C) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_1E) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_20) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_22) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_24) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_26) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_28) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_2A) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_2C) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_2E) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_30) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_32) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_34) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_36) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_38) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_3A) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_3C) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_3E) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_40) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_42) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_44) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_46) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_48) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_4A) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_4C) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_4E) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_50) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_52) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_54) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_56) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_58) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_5A) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_5C) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_5E) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_60) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_62) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_64) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_66) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_68) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_6A) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_6C) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_6E) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_70) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_72) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_74) & ~(tmp_2772_fu_17361_p2 == ap_const_lv7_76))) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_120_V_read_1_reg_19603;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_76)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_118_V_read_1_reg_19609;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_74)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_116_V_read_1_reg_19615;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_72)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_114_V_read_1_reg_19621;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_70)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_112_V_read_1_reg_19627;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_6E)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_110_V_read_1_reg_19633;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_6C)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_108_V_read_1_reg_19639;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_6A)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_106_V_read_1_reg_19645;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_68)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_104_V_read_1_reg_19651;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_66)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_102_V_read_1_reg_19657;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_64)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_100_V_read_1_reg_19663;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_62)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_98_V_read_1_reg_19669;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_60)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_96_V_read_1_reg_19675;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_5E)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_94_V_read_1_reg_19681;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_5C)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_92_V_read_1_reg_19687;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_5A)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_90_V_read_1_reg_19693;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_58)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_88_V_read_1_reg_19699;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_56)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_86_V_read_1_reg_19705;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_54)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_84_V_read_1_reg_19711;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_52)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_82_V_read_1_reg_19717;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_50)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_80_V_read_1_reg_19723;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_4E)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_78_V_read_1_reg_19729;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_4C)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_76_V_read_1_reg_19735;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_4A)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_74_V_read_1_reg_19741;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_48)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_72_V_read_1_reg_19747;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_46)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_70_V_read_1_reg_19753;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_44)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_68_V_read_1_reg_19759;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_42)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_66_V_read_1_reg_19765;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_40)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_64_V_read_1_reg_19771;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_3E)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_62_V_read_1_reg_19777;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_3C)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_60_V_read_1_reg_19783;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_3A)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_58_V_read_1_reg_19789;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_38)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_56_V_read_1_reg_19795;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_36)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_54_V_read_1_reg_19801;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_34)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_52_V_read_1_reg_19807;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_32)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_50_V_read_1_reg_19813;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_30)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_48_V_read_1_reg_19819;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_2E)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_46_V_read_1_reg_19825;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_2C)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_44_V_read_1_reg_19831;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_2A)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_42_V_read_1_reg_19837;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_28)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_40_V_read_1_reg_19843;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_26)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_38_V_read_1_reg_19849;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_24)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_36_V_read_1_reg_19855;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_22)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_34_V_read_1_reg_19861;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_20)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_32_V_read_1_reg_19867;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_1E)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_30_V_read_1_reg_19873;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_1C)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_28_V_read_1_reg_19879;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_1A)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_26_V_read_1_reg_19885;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_18)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_24_V_read_1_reg_19891;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_16)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_22_V_read_1_reg_19897;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_14)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_20_V_read_1_reg_19903;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_12)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_18_V_read_1_reg_19909;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_10)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_16_V_read_1_reg_19915;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_E)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_14_V_read_1_reg_19921;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_C)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_12_V_read_1_reg_19927;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_A)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_10_V_read_1_reg_19933;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_8)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_8_V_read_1_reg_19939;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_6)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_6_V_read_1_reg_19945;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_4)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_4_V_read_1_reg_19951;
end else if ((tmp_2772_fu_17361_p2 == ap_const_lv7_2)) begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = rank_ex_2_V_read_1_reg_19957;
end else begin
sorter_a_V_load29_phi_phi_fu_3746_p122 = ap_reg_phiprechg_sorter_a_V_load29_phi_reg_3743pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv7_0 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_0_V_read_1_reg_19963;
end else if ((~(ap_const_lv7_0 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_2 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_4 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_6 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_8 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_A == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_C == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_E == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_10 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_12 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_14 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_16 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_18 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_1A == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_1C == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_1E == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_20 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_22 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_24 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_26 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_28 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_2A == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_2C == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_2E == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_30 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_32 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_34 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_36 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_38 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_3A == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_3C == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_3E == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_40 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_42 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_44 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_46 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_48 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_4A == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_4C == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_4E == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_50 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_52 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_54 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_56 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_58 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_5A == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_5C == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_5E == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_60 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_62 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_64 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_66 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_68 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_6A == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_6C == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_6E == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_70 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_72 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_74 == tmp_2773_fu_19527_p2) & ~(ap_const_lv7_76 == tmp_2773_fu_19527_p2))) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_120_V_read_1_reg_19603;
end else if ((ap_const_lv7_76 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_118_V_read_1_reg_19609;
end else if ((ap_const_lv7_74 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_116_V_read_1_reg_19615;
end else if ((ap_const_lv7_72 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_114_V_read_1_reg_19621;
end else if ((ap_const_lv7_70 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_112_V_read_1_reg_19627;
end else if ((ap_const_lv7_6E == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_110_V_read_1_reg_19633;
end else if ((ap_const_lv7_6C == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_108_V_read_1_reg_19639;
end else if ((ap_const_lv7_6A == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_106_V_read_1_reg_19645;
end else if ((ap_const_lv7_68 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_104_V_read_1_reg_19651;
end else if ((ap_const_lv7_66 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_102_V_read_1_reg_19657;
end else if ((ap_const_lv7_64 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_100_V_read_1_reg_19663;
end else if ((ap_const_lv7_62 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_98_V_read_1_reg_19669;
end else if ((ap_const_lv7_60 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_96_V_read_1_reg_19675;
end else if ((ap_const_lv7_5E == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_94_V_read_1_reg_19681;
end else if ((ap_const_lv7_5C == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_92_V_read_1_reg_19687;
end else if ((ap_const_lv7_5A == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_90_V_read_1_reg_19693;
end else if ((ap_const_lv7_58 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_88_V_read_1_reg_19699;
end else if ((ap_const_lv7_56 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_86_V_read_1_reg_19705;
end else if ((ap_const_lv7_54 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_84_V_read_1_reg_19711;
end else if ((ap_const_lv7_52 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_82_V_read_1_reg_19717;
end else if ((ap_const_lv7_50 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_80_V_read_1_reg_19723;
end else if ((ap_const_lv7_4E == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_78_V_read_1_reg_19729;
end else if ((ap_const_lv7_4C == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_76_V_read_1_reg_19735;
end else if ((ap_const_lv7_4A == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_74_V_read_1_reg_19741;
end else if ((ap_const_lv7_48 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_72_V_read_1_reg_19747;
end else if ((ap_const_lv7_46 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_70_V_read_1_reg_19753;
end else if ((ap_const_lv7_44 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_68_V_read_1_reg_19759;
end else if ((ap_const_lv7_42 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_66_V_read_1_reg_19765;
end else if ((ap_const_lv7_40 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_64_V_read_1_reg_19771;
end else if ((ap_const_lv7_3E == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_62_V_read_1_reg_19777;
end else if ((ap_const_lv7_3C == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_60_V_read_1_reg_19783;
end else if ((ap_const_lv7_3A == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_58_V_read_1_reg_19789;
end else if ((ap_const_lv7_38 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_56_V_read_1_reg_19795;
end else if ((ap_const_lv7_36 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_54_V_read_1_reg_19801;
end else if ((ap_const_lv7_34 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_52_V_read_1_reg_19807;
end else if ((ap_const_lv7_32 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_50_V_read_1_reg_19813;
end else if ((ap_const_lv7_30 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_48_V_read_1_reg_19819;
end else if ((ap_const_lv7_2E == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_46_V_read_1_reg_19825;
end else if ((ap_const_lv7_2C == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_44_V_read_1_reg_19831;
end else if ((ap_const_lv7_2A == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_42_V_read_1_reg_19837;
end else if ((ap_const_lv7_28 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_40_V_read_1_reg_19843;
end else if ((ap_const_lv7_26 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_38_V_read_1_reg_19849;
end else if ((ap_const_lv7_24 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_36_V_read_1_reg_19855;
end else if ((ap_const_lv7_22 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_34_V_read_1_reg_19861;
end else if ((ap_const_lv7_20 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_32_V_read_1_reg_19867;
end else if ((ap_const_lv7_1E == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_30_V_read_1_reg_19873;
end else if ((ap_const_lv7_1C == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_28_V_read_1_reg_19879;
end else if ((ap_const_lv7_1A == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_26_V_read_1_reg_19885;
end else if ((ap_const_lv7_18 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_24_V_read_1_reg_19891;
end else if ((ap_const_lv7_16 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_22_V_read_1_reg_19897;
end else if ((ap_const_lv7_14 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_20_V_read_1_reg_19903;
end else if ((ap_const_lv7_12 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_18_V_read_1_reg_19909;
end else if ((ap_const_lv7_10 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_16_V_read_1_reg_19915;
end else if ((ap_const_lv7_E == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_14_V_read_1_reg_19921;
end else if ((ap_const_lv7_C == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_12_V_read_1_reg_19927;
end else if ((ap_const_lv7_A == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_10_V_read_1_reg_19933;
end else if ((ap_const_lv7_8 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_8_V_read_1_reg_19939;
end else if ((ap_const_lv7_6 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_6_V_read_1_reg_19945;
end else if ((ap_const_lv7_4 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_4_V_read_1_reg_19951;
end else if ((ap_const_lv7_2 == tmp_2773_fu_19527_p2)) begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = rank_ex_2_V_read_1_reg_19957;
end else begin
sorter_a_V_load_14_phi_phi_fu_14475_p122 = ap_reg_phiprechg_sorter_a_V_load_14_phi_reg_14472pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_A == tmp_2771_fu_17357_p1)) begin
win_l0_V_10_phi_fu_10582_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_10_phi_fu_10582_p128 = win_l0_10_V_reg_20655;
end else begin
win_l0_V_10_phi_fu_10582_p128 = ap_reg_phiprechg_win_l0_V_10_reg_10579pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_B == tmp_2771_fu_17357_p1)) begin
win_l0_V_11_phi_fu_10448_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_11_phi_fu_10448_p128 = win_l0_11_V_reg_20723;
end else begin
win_l0_V_11_phi_fu_10448_p128 = ap_reg_phiprechg_win_l0_V_11_reg_10445pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_C == tmp_2771_fu_17357_p1)) begin
win_l0_V_12_phi_fu_10314_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_12_phi_fu_10314_p128 = win_l0_12_V_reg_20791;
end else begin
win_l0_V_12_phi_fu_10314_p128 = ap_reg_phiprechg_win_l0_V_12_reg_10311pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_D == tmp_2771_fu_17357_p1)) begin
win_l0_V_13_phi_fu_10180_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_13_phi_fu_10180_p128 = win_l0_13_V_reg_20859;
end else begin
win_l0_V_13_phi_fu_10180_p128 = ap_reg_phiprechg_win_l0_V_13_reg_10177pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_E == tmp_2771_fu_17357_p1)) begin
win_l0_V_14_phi_fu_10046_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_14_phi_fu_10046_p128 = win_l0_14_V_reg_20927;
end else begin
win_l0_V_14_phi_fu_10046_p128 = ap_reg_phiprechg_win_l0_V_14_reg_10043pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_F == tmp_2771_fu_17357_p1)) begin
win_l0_V_15_phi_fu_9912_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_15_phi_fu_9912_p128 = win_l0_15_V_reg_20995;
end else begin
win_l0_V_15_phi_fu_9912_p128 = ap_reg_phiprechg_win_l0_V_15_reg_9909pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_10 == tmp_2771_fu_17357_p1)) begin
win_l0_V_16_phi_fu_9778_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_16_phi_fu_9778_p128 = win_l0_16_V_reg_21063;
end else begin
win_l0_V_16_phi_fu_9778_p128 = ap_reg_phiprechg_win_l0_V_16_reg_9775pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_11 == tmp_2771_fu_17357_p1)) begin
win_l0_V_17_phi_fu_9644_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_17_phi_fu_9644_p128 = win_l0_17_V_reg_21130;
end else begin
win_l0_V_17_phi_fu_9644_p128 = ap_reg_phiprechg_win_l0_V_17_reg_9641pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_12 == tmp_2771_fu_17357_p1)) begin
win_l0_V_18_phi_fu_9510_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_18_phi_fu_9510_p128 = win_l0_18_V_reg_21197;
end else begin
win_l0_V_18_phi_fu_9510_p128 = ap_reg_phiprechg_win_l0_V_18_reg_9507pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_13 == tmp_2771_fu_17357_p1)) begin
win_l0_V_19_phi_fu_9376_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_19_phi_fu_9376_p128 = win_l0_19_V_reg_21264;
end else begin
win_l0_V_19_phi_fu_9376_p128 = ap_reg_phiprechg_win_l0_V_19_reg_9373pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_3B == tmp_2771_fu_17357_p1)) begin
win_l0_V_1_phi_fu_4016_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_1_phi_fu_4016_p128 = win_l0_59_V_reg_23944;
end else begin
win_l0_V_1_phi_fu_4016_p128 = ap_reg_phiprechg_win_l0_V_1_reg_4013pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_14 == tmp_2771_fu_17357_p1)) begin
win_l0_V_20_phi_fu_9242_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_20_phi_fu_9242_p128 = win_l0_20_V_reg_21331;
end else begin
win_l0_V_20_phi_fu_9242_p128 = ap_reg_phiprechg_win_l0_V_20_reg_9239pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_15 == tmp_2771_fu_17357_p1)) begin
win_l0_V_21_phi_fu_9108_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_21_phi_fu_9108_p128 = win_l0_21_V_reg_21398;
end else begin
win_l0_V_21_phi_fu_9108_p128 = ap_reg_phiprechg_win_l0_V_21_reg_9105pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_16 == tmp_2771_fu_17357_p1)) begin
win_l0_V_22_phi_fu_8974_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_22_phi_fu_8974_p128 = win_l0_22_V_reg_21465;
end else begin
win_l0_V_22_phi_fu_8974_p128 = ap_reg_phiprechg_win_l0_V_22_reg_8971pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_17 == tmp_2771_fu_17357_p1)) begin
win_l0_V_23_phi_fu_8840_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_23_phi_fu_8840_p128 = win_l0_23_V_reg_21532;
end else begin
win_l0_V_23_phi_fu_8840_p128 = ap_reg_phiprechg_win_l0_V_23_reg_8837pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_18 == tmp_2771_fu_17357_p1)) begin
win_l0_V_24_phi_fu_8706_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_24_phi_fu_8706_p128 = win_l0_24_V_reg_21599;
end else begin
win_l0_V_24_phi_fu_8706_p128 = ap_reg_phiprechg_win_l0_V_24_reg_8703pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_19 == tmp_2771_fu_17357_p1)) begin
win_l0_V_25_phi_fu_8572_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_25_phi_fu_8572_p128 = win_l0_25_V_reg_21666;
end else begin
win_l0_V_25_phi_fu_8572_p128 = ap_reg_phiprechg_win_l0_V_25_reg_8569pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_1A == tmp_2771_fu_17357_p1)) begin
win_l0_V_26_phi_fu_8438_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_26_phi_fu_8438_p128 = win_l0_26_V_reg_21733;
end else begin
win_l0_V_26_phi_fu_8438_p128 = ap_reg_phiprechg_win_l0_V_26_reg_8435pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_1B == tmp_2771_fu_17357_p1)) begin
win_l0_V_27_phi_fu_8304_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_27_phi_fu_8304_p128 = win_l0_27_V_reg_21800;
end else begin
win_l0_V_27_phi_fu_8304_p128 = ap_reg_phiprechg_win_l0_V_27_reg_8301pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_1C == tmp_2771_fu_17357_p1)) begin
win_l0_V_28_phi_fu_8170_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_28_phi_fu_8170_p128 = win_l0_28_V_reg_21867;
end else begin
win_l0_V_28_phi_fu_8170_p128 = ap_reg_phiprechg_win_l0_V_28_reg_8167pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_1D == tmp_2771_fu_17357_p1)) begin
win_l0_V_29_phi_fu_8036_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_29_phi_fu_8036_p128 = win_l0_29_V_reg_21934;
end else begin
win_l0_V_29_phi_fu_8036_p128 = ap_reg_phiprechg_win_l0_V_29_reg_8033pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_2 == tmp_2771_fu_17357_p1)) begin
win_l0_V_2_phi_fu_11654_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_2_phi_fu_11654_p128 = win_l0_2_V_reg_20113;
end else begin
win_l0_V_2_phi_fu_11654_p128 = ap_reg_phiprechg_win_l0_V_2_reg_11651pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_1E == tmp_2771_fu_17357_p1)) begin
win_l0_V_30_phi_fu_7902_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_30_phi_fu_7902_p128 = win_l0_30_V_reg_22001;
end else begin
win_l0_V_30_phi_fu_7902_p128 = ap_reg_phiprechg_win_l0_V_30_reg_7899pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_1F == tmp_2771_fu_17357_p1)) begin
win_l0_V_31_phi_fu_7768_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_31_phi_fu_7768_p128 = win_l0_31_V_reg_22068;
end else begin
win_l0_V_31_phi_fu_7768_p128 = ap_reg_phiprechg_win_l0_V_31_reg_7765pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_20 == tmp_2771_fu_17357_p1)) begin
win_l0_V_32_phi_fu_7634_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_32_phi_fu_7634_p128 = win_l0_32_V_reg_22135;
end else begin
win_l0_V_32_phi_fu_7634_p128 = ap_reg_phiprechg_win_l0_V_32_reg_7631pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_21 == tmp_2771_fu_17357_p1)) begin
win_l0_V_33_phi_fu_7500_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_33_phi_fu_7500_p128 = win_l0_33_V_reg_22202;
end else begin
win_l0_V_33_phi_fu_7500_p128 = ap_reg_phiprechg_win_l0_V_33_reg_7497pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_22 == tmp_2771_fu_17357_p1)) begin
win_l0_V_34_phi_fu_7366_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_34_phi_fu_7366_p128 = win_l0_34_V_reg_22269;
end else begin
win_l0_V_34_phi_fu_7366_p128 = ap_reg_phiprechg_win_l0_V_34_reg_7363pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_23 == tmp_2771_fu_17357_p1)) begin
win_l0_V_35_phi_fu_7232_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_35_phi_fu_7232_p128 = win_l0_35_V_reg_22336;
end else begin
win_l0_V_35_phi_fu_7232_p128 = ap_reg_phiprechg_win_l0_V_35_reg_7229pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_24 == tmp_2771_fu_17357_p1)) begin
win_l0_V_36_phi_fu_7098_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_36_phi_fu_7098_p128 = win_l0_36_V_reg_22403;
end else begin
win_l0_V_36_phi_fu_7098_p128 = ap_reg_phiprechg_win_l0_V_36_reg_7095pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_25 == tmp_2771_fu_17357_p1)) begin
win_l0_V_37_phi_fu_6964_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_37_phi_fu_6964_p128 = win_l0_37_V_reg_22470;
end else begin
win_l0_V_37_phi_fu_6964_p128 = ap_reg_phiprechg_win_l0_V_37_reg_6961pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_26 == tmp_2771_fu_17357_p1)) begin
win_l0_V_38_phi_fu_6830_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_38_phi_fu_6830_p128 = win_l0_38_V_reg_22537;
end else begin
win_l0_V_38_phi_fu_6830_p128 = ap_reg_phiprechg_win_l0_V_38_reg_6827pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_27 == tmp_2771_fu_17357_p1)) begin
win_l0_V_39_phi_fu_6696_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_39_phi_fu_6696_p128 = win_l0_39_V_reg_22604;
end else begin
win_l0_V_39_phi_fu_6696_p128 = ap_reg_phiprechg_win_l0_V_39_reg_6693pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_3 == tmp_2771_fu_17357_p1)) begin
win_l0_V_3_phi_fu_11520_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_3_phi_fu_11520_p128 = win_l0_3_V_reg_20180;
end else begin
win_l0_V_3_phi_fu_11520_p128 = ap_reg_phiprechg_win_l0_V_3_reg_11517pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_28 == tmp_2771_fu_17357_p1)) begin
win_l0_V_40_phi_fu_6562_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_40_phi_fu_6562_p128 = win_l0_40_V_reg_22671;
end else begin
win_l0_V_40_phi_fu_6562_p128 = ap_reg_phiprechg_win_l0_V_40_reg_6559pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_29 == tmp_2771_fu_17357_p1)) begin
win_l0_V_41_phi_fu_6428_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_41_phi_fu_6428_p128 = win_l0_41_V_reg_22738;
end else begin
win_l0_V_41_phi_fu_6428_p128 = ap_reg_phiprechg_win_l0_V_41_reg_6425pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_2A == tmp_2771_fu_17357_p1)) begin
win_l0_V_42_phi_fu_6294_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_42_phi_fu_6294_p128 = win_l0_42_V_reg_22805;
end else begin
win_l0_V_42_phi_fu_6294_p128 = ap_reg_phiprechg_win_l0_V_42_reg_6291pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_2B == tmp_2771_fu_17357_p1)) begin
win_l0_V_43_phi_fu_6160_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_43_phi_fu_6160_p128 = win_l0_43_V_reg_22872;
end else begin
win_l0_V_43_phi_fu_6160_p128 = ap_reg_phiprechg_win_l0_V_43_reg_6157pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_2C == tmp_2771_fu_17357_p1)) begin
win_l0_V_44_phi_fu_6026_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_44_phi_fu_6026_p128 = win_l0_44_V_reg_22939;
end else begin
win_l0_V_44_phi_fu_6026_p128 = ap_reg_phiprechg_win_l0_V_44_reg_6023pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_2D == tmp_2771_fu_17357_p1)) begin
win_l0_V_45_phi_fu_5892_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_45_phi_fu_5892_p128 = win_l0_45_V_reg_23006;
end else begin
win_l0_V_45_phi_fu_5892_p128 = ap_reg_phiprechg_win_l0_V_45_reg_5889pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_2E == tmp_2771_fu_17357_p1)) begin
win_l0_V_46_phi_fu_5758_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_46_phi_fu_5758_p128 = win_l0_46_V_reg_23073;
end else begin
win_l0_V_46_phi_fu_5758_p128 = ap_reg_phiprechg_win_l0_V_46_reg_5755pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_2F == tmp_2771_fu_17357_p1)) begin
win_l0_V_47_phi_fu_5624_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_47_phi_fu_5624_p128 = win_l0_47_V_reg_23140;
end else begin
win_l0_V_47_phi_fu_5624_p128 = ap_reg_phiprechg_win_l0_V_47_reg_5621pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_30 == tmp_2771_fu_17357_p1)) begin
win_l0_V_48_phi_fu_5490_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_48_phi_fu_5490_p128 = win_l0_48_V_reg_23207;
end else begin
win_l0_V_48_phi_fu_5490_p128 = ap_reg_phiprechg_win_l0_V_48_reg_5487pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_31 == tmp_2771_fu_17357_p1)) begin
win_l0_V_49_phi_fu_5356_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_49_phi_fu_5356_p128 = win_l0_49_V_reg_23274;
end else begin
win_l0_V_49_phi_fu_5356_p128 = ap_reg_phiprechg_win_l0_V_49_reg_5353pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_4 == tmp_2771_fu_17357_p1)) begin
win_l0_V_4_phi_fu_11386_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_4_phi_fu_11386_p128 = win_l0_4_V_reg_20247;
end else begin
win_l0_V_4_phi_fu_11386_p128 = ap_reg_phiprechg_win_l0_V_4_reg_11383pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_32 == tmp_2771_fu_17357_p1)) begin
win_l0_V_50_phi_fu_5222_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_50_phi_fu_5222_p128 = win_l0_50_V_reg_23341;
end else begin
win_l0_V_50_phi_fu_5222_p128 = ap_reg_phiprechg_win_l0_V_50_reg_5219pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_33 == tmp_2771_fu_17357_p1)) begin
win_l0_V_51_phi_fu_5088_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_51_phi_fu_5088_p128 = win_l0_51_V_reg_23408;
end else begin
win_l0_V_51_phi_fu_5088_p128 = ap_reg_phiprechg_win_l0_V_51_reg_5085pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_34 == tmp_2771_fu_17357_p1)) begin
win_l0_V_52_phi_fu_4954_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_52_phi_fu_4954_p128 = win_l0_52_V_reg_23475;
end else begin
win_l0_V_52_phi_fu_4954_p128 = ap_reg_phiprechg_win_l0_V_52_reg_4951pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_35 == tmp_2771_fu_17357_p1)) begin
win_l0_V_53_phi_fu_4820_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_53_phi_fu_4820_p128 = win_l0_53_V_reg_23542;
end else begin
win_l0_V_53_phi_fu_4820_p128 = ap_reg_phiprechg_win_l0_V_53_reg_4817pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_36 == tmp_2771_fu_17357_p1)) begin
win_l0_V_54_phi_fu_4686_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_54_phi_fu_4686_p128 = win_l0_54_V_reg_23609;
end else begin
win_l0_V_54_phi_fu_4686_p128 = ap_reg_phiprechg_win_l0_V_54_reg_4683pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_37 == tmp_2771_fu_17357_p1)) begin
win_l0_V_55_phi_fu_4552_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_55_phi_fu_4552_p128 = win_l0_55_V_reg_23676;
end else begin
win_l0_V_55_phi_fu_4552_p128 = ap_reg_phiprechg_win_l0_V_55_reg_4549pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_38 == tmp_2771_fu_17357_p1)) begin
win_l0_V_56_phi_fu_4418_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_56_phi_fu_4418_p128 = win_l0_56_V_reg_23743;
end else begin
win_l0_V_56_phi_fu_4418_p128 = ap_reg_phiprechg_win_l0_V_56_reg_4415pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_39 == tmp_2771_fu_17357_p1)) begin
win_l0_V_57_phi_fu_4284_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_57_phi_fu_4284_p128 = win_l0_57_V_reg_23810;
end else begin
win_l0_V_57_phi_fu_4284_p128 = ap_reg_phiprechg_win_l0_V_57_reg_4281pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_3A == tmp_2771_fu_17357_p1)) begin
win_l0_V_58_phi_fu_4150_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_58_phi_fu_4150_p128 = win_l0_58_V_reg_23877;
end else begin
win_l0_V_58_phi_fu_4150_p128 = ap_reg_phiprechg_win_l0_V_58_reg_4147pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_1 == tmp_2771_fu_17357_p1)) begin
win_l0_V_59_phi_fu_11788_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_59_phi_fu_11788_p128 = win_l0_1_V_reg_20046;
end else begin
win_l0_V_59_phi_fu_11788_p128 = ap_reg_phiprechg_win_l0_V_59_reg_11785pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_5 == tmp_2771_fu_17357_p1)) begin
win_l0_V_5_phi_fu_11252_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_5_phi_fu_11252_p128 = win_l0_5_V_reg_20315;
end else begin
win_l0_V_5_phi_fu_11252_p128 = ap_reg_phiprechg_win_l0_V_5_reg_11249pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_6 == tmp_2771_fu_17357_p1)) begin
win_l0_V_6_phi_fu_11118_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_6_phi_fu_11118_p128 = win_l0_6_V_reg_20383;
end else begin
win_l0_V_6_phi_fu_11118_p128 = ap_reg_phiprechg_win_l0_V_6_reg_11115pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_7 == tmp_2771_fu_17357_p1)) begin
win_l0_V_7_phi_fu_10984_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_7_phi_fu_10984_p128 = win_l0_7_V_reg_20451;
end else begin
win_l0_V_7_phi_fu_10984_p128 = ap_reg_phiprechg_win_l0_V_7_reg_10981pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_8 == tmp_2771_fu_17357_p1)) begin
win_l0_V_8_phi_fu_10850_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_8_phi_fu_10850_p128 = win_l0_8_V_reg_20519;
end else begin
win_l0_V_8_phi_fu_10850_p128 = ap_reg_phiprechg_win_l0_V_8_reg_10847pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_9 == tmp_2771_fu_17357_p1)) begin
win_l0_V_9_phi_fu_10716_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_9_phi_fu_10716_p128 = win_l0_9_V_reg_20587;
end else begin
win_l0_V_9_phi_fu_10716_p128 = ap_reg_phiprechg_win_l0_V_9_reg_10713pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_0 == tmp_2771_fu_17357_p1)) begin
win_l0_V_phi_fu_11922_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3C == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1))) begin
win_l0_V_phi_fu_11922_p128 = win_l0_0_V_reg_19979;
end else begin
win_l0_V_phi_fu_11922_p128 = ap_reg_phiprechg_win_l0_V_reg_11919pp0_it1;
end
end
always @ (*) begin
if ((ap_const_lv6_3C == tmp_2771_fu_17357_p1)) begin
win_l0_V_s_phi_fu_3882_p128 = ap_const_lv6_0;
end else if (((ap_const_lv6_3F == tmp_2771_fu_17357_p1) | (ap_const_lv6_3E == tmp_2771_fu_17357_p1) | (ap_const_lv6_3D == tmp_2771_fu_17357_p1) | (ap_const_lv6_3B == tmp_2771_fu_17357_p1) | (ap_const_lv6_3A == tmp_2771_fu_17357_p1) | (ap_const_lv6_39 == tmp_2771_fu_17357_p1) | (ap_const_lv6_38 == tmp_2771_fu_17357_p1) | (ap_const_lv6_37 == tmp_2771_fu_17357_p1) | (ap_const_lv6_36 == tmp_2771_fu_17357_p1) | (ap_const_lv6_35 == tmp_2771_fu_17357_p1) | (ap_const_lv6_34 == tmp_2771_fu_17357_p1) | (ap_const_lv6_33 == tmp_2771_fu_17357_p1) | (ap_const_lv6_32 == tmp_2771_fu_17357_p1) | (ap_const_lv6_31 == tmp_2771_fu_17357_p1) | (ap_const_lv6_30 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2F == tmp_2771_fu_17357_p1) | (ap_const_lv6_2E == tmp_2771_fu_17357_p1) | (ap_const_lv6_2D == tmp_2771_fu_17357_p1) | (ap_const_lv6_2C == tmp_2771_fu_17357_p1) | (ap_const_lv6_2B == tmp_2771_fu_17357_p1) | (ap_const_lv6_2A == tmp_2771_fu_17357_p1) | (ap_const_lv6_29 == tmp_2771_fu_17357_p1) | (ap_const_lv6_28 == tmp_2771_fu_17357_p1) | (ap_const_lv6_27 == tmp_2771_fu_17357_p1) | (ap_const_lv6_26 == tmp_2771_fu_17357_p1) | (ap_const_lv6_25 == tmp_2771_fu_17357_p1) | (ap_const_lv6_24 == tmp_2771_fu_17357_p1) | (ap_const_lv6_23 == tmp_2771_fu_17357_p1) | (ap_const_lv6_22 == tmp_2771_fu_17357_p1) | (ap_const_lv6_21 == tmp_2771_fu_17357_p1) | (ap_const_lv6_20 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1F == tmp_2771_fu_17357_p1) | (ap_const_lv6_1E == tmp_2771_fu_17357_p1) | (ap_const_lv6_1D == tmp_2771_fu_17357_p1) | (ap_const_lv6_1C == tmp_2771_fu_17357_p1) | (ap_const_lv6_1B == tmp_2771_fu_17357_p1) | (ap_const_lv6_1A == tmp_2771_fu_17357_p1) | (ap_const_lv6_19 == tmp_2771_fu_17357_p1) | (ap_const_lv6_18 == tmp_2771_fu_17357_p1) | (ap_const_lv6_17 == tmp_2771_fu_17357_p1) | (ap_const_lv6_16 == tmp_2771_fu_17357_p1) | (ap_const_lv6_15 == tmp_2771_fu_17357_p1) | (ap_const_lv6_14 == tmp_2771_fu_17357_p1) | (ap_const_lv6_13 == tmp_2771_fu_17357_p1) | (ap_const_lv6_12 == tmp_2771_fu_17357_p1) | (ap_const_lv6_11 == tmp_2771_fu_17357_p1) | (ap_const_lv6_10 == tmp_2771_fu_17357_p1) | (ap_const_lv6_F == tmp_2771_fu_17357_p1) | (ap_const_lv6_E == tmp_2771_fu_17357_p1) | (ap_const_lv6_D == tmp_2771_fu_17357_p1) | (ap_const_lv6_C == tmp_2771_fu_17357_p1) | (ap_const_lv6_B == tmp_2771_fu_17357_p1) | (ap_const_lv6_A == tmp_2771_fu_17357_p1) | (ap_const_lv6_9 == tmp_2771_fu_17357_p1) | (ap_const_lv6_8 == tmp_2771_fu_17357_p1) | (ap_const_lv6_7 == tmp_2771_fu_17357_p1) | (ap_const_lv6_6 == tmp_2771_fu_17357_p1) | (ap_const_lv6_5 == tmp_2771_fu_17357_p1) | (ap_const_lv6_4 == tmp_2771_fu_17357_p1) | (ap_const_lv6_3 == tmp_2771_fu_17357_p1) | (ap_const_lv6_2 == tmp_2771_fu_17357_p1) | (ap_const_lv6_1 == tmp_2771_fu_17357_p1) | (ap_const_lv6_0 == tmp_2771_fu_17357_p1))) begin
win_l0_V_s_phi_fu_3882_p128 = win_l0_60_V_reg_24011;
end else begin
win_l0_V_s_phi_fu_3882_p128 = ap_reg_phiprechg_win_l0_V_s_reg_3879pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_5_fu_17799_p2) & ~(1'b0 == tmp_366_5_fu_17823_p2) & (1'b0 == tmp_375_5_fu_17847_p2) & (1'b0 == or_cond135_fu_17865_p2)) | (~(1'b0 == tmp_366_5_fu_17823_p2) & (1'b0 == tmp_375_5_fu_17847_p2) & ~(1'b0 == or_cond133_fu_17817_p2) & (1'b0 == or_cond135_fu_17865_p2)) | (~(1'b0 == tmp_351_5_fu_17799_p2) & (1'b0 == tmp_375_5_fu_17847_p2) & ~(1'b0 == or_cond134_fu_17841_p2) & (1'b0 == or_cond135_fu_17865_p2)) | ((1'b0 == tmp_375_5_fu_17847_p2) & ~(1'b0 == or_cond133_fu_17817_p2) & ~(1'b0 == or_cond134_fu_17841_p2) & (1'b0 == or_cond135_fu_17865_p2)))) begin
win_l1_V_1_load_1_1_phi_fu_12410_p8 = win_l0_V_22_phi_fu_8974_p128;
end else if (((~(1'b0 == tmp_351_5_fu_17799_p2) & (1'b0 == tmp_366_5_fu_17823_p2) & (1'b0 == or_cond134_fu_17841_p2)) | ((1'b0 == tmp_366_5_fu_17823_p2) & ~(1'b0 == or_cond133_fu_17817_p2) & (1'b0 == or_cond134_fu_17841_p2)))) begin
win_l1_V_1_load_1_1_phi_fu_12410_p8 = win_l0_V_21_phi_fu_9108_p128;
end else if (((1'b0 == tmp_351_5_fu_17799_p2) & (1'b0 == or_cond133_fu_17817_p2))) begin
win_l1_V_1_load_1_1_phi_fu_12410_p8 = win_l0_V_20_phi_fu_9242_p128;
end else if (((~(1'b0 == tmp_351_5_fu_17799_p2) & ~(1'b0 == tmp_366_5_fu_17823_p2) & ~(1'b0 == tmp_375_5_fu_17847_p2)) | (~(1'b0 == tmp_366_5_fu_17823_p2) & ~(1'b0 == tmp_375_5_fu_17847_p2) & ~(1'b0 == or_cond133_fu_17817_p2)) | (~(1'b0 == tmp_351_5_fu_17799_p2) & ~(1'b0 == tmp_375_5_fu_17847_p2) & ~(1'b0 == or_cond134_fu_17841_p2)) | (~(1'b0 == tmp_351_5_fu_17799_p2) & ~(1'b0 == tmp_366_5_fu_17823_p2) & ~(1'b0 == or_cond135_fu_17865_p2)) | (~(1'b0 == tmp_375_5_fu_17847_p2) & ~(1'b0 == or_cond133_fu_17817_p2) & ~(1'b0 == or_cond134_fu_17841_p2)) | (~(1'b0 == tmp_366_5_fu_17823_p2) & ~(1'b0 == or_cond133_fu_17817_p2) & ~(1'b0 == or_cond135_fu_17865_p2)) | (~(1'b0 == tmp_351_5_fu_17799_p2) & ~(1'b0 == or_cond134_fu_17841_p2) & ~(1'b0 == or_cond135_fu_17865_p2)) | (~(1'b0 == or_cond133_fu_17817_p2) & ~(1'b0 == or_cond134_fu_17841_p2) & ~(1'b0 == or_cond135_fu_17865_p2)))) begin
win_l1_V_1_load_1_1_phi_fu_12410_p8 = win_l0_V_23_phi_fu_8840_p128;
end else begin
win_l1_V_1_load_1_1_phi_fu_12410_p8 = ap_reg_phiprechg_win_l1_V_1_load_1_1_reg_12407pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_9_fu_18111_p2) & ~(1'b0 == tmp_366_9_fu_18135_p2) & (1'b0 == tmp_375_9_fu_18159_p2) & (1'b0 == or_cond147_fu_18177_p2)) | (~(1'b0 == tmp_366_9_fu_18135_p2) & (1'b0 == tmp_375_9_fu_18159_p2) & ~(1'b0 == or_cond145_fu_18129_p2) & (1'b0 == or_cond147_fu_18177_p2)) | (~(1'b0 == tmp_351_9_fu_18111_p2) & (1'b0 == tmp_375_9_fu_18159_p2) & ~(1'b0 == or_cond146_fu_18153_p2) & (1'b0 == or_cond147_fu_18177_p2)) | ((1'b0 == tmp_375_9_fu_18159_p2) & ~(1'b0 == or_cond145_fu_18129_p2) & ~(1'b0 == or_cond146_fu_18153_p2) & (1'b0 == or_cond147_fu_18177_p2)))) begin
win_l1_V_1_load_1_2_phi_fu_13055_p8 = win_l0_V_38_phi_fu_6830_p128;
end else if (((~(1'b0 == tmp_351_9_fu_18111_p2) & (1'b0 == tmp_366_9_fu_18135_p2) & (1'b0 == or_cond146_fu_18153_p2)) | ((1'b0 == tmp_366_9_fu_18135_p2) & ~(1'b0 == or_cond145_fu_18129_p2) & (1'b0 == or_cond146_fu_18153_p2)))) begin
win_l1_V_1_load_1_2_phi_fu_13055_p8 = win_l0_V_37_phi_fu_6964_p128;
end else if (((1'b0 == tmp_351_9_fu_18111_p2) & (1'b0 == or_cond145_fu_18129_p2))) begin
win_l1_V_1_load_1_2_phi_fu_13055_p8 = win_l0_V_36_phi_fu_7098_p128;
end else if (((~(1'b0 == tmp_351_9_fu_18111_p2) & ~(1'b0 == tmp_366_9_fu_18135_p2) & ~(1'b0 == tmp_375_9_fu_18159_p2)) | (~(1'b0 == tmp_366_9_fu_18135_p2) & ~(1'b0 == tmp_375_9_fu_18159_p2) & ~(1'b0 == or_cond145_fu_18129_p2)) | (~(1'b0 == tmp_351_9_fu_18111_p2) & ~(1'b0 == tmp_375_9_fu_18159_p2) & ~(1'b0 == or_cond146_fu_18153_p2)) | (~(1'b0 == tmp_351_9_fu_18111_p2) & ~(1'b0 == tmp_366_9_fu_18135_p2) & ~(1'b0 == or_cond147_fu_18177_p2)) | (~(1'b0 == tmp_375_9_fu_18159_p2) & ~(1'b0 == or_cond145_fu_18129_p2) & ~(1'b0 == or_cond146_fu_18153_p2)) | (~(1'b0 == tmp_366_9_fu_18135_p2) & ~(1'b0 == or_cond145_fu_18129_p2) & ~(1'b0 == or_cond147_fu_18177_p2)) | (~(1'b0 == tmp_351_9_fu_18111_p2) & ~(1'b0 == or_cond146_fu_18153_p2) & ~(1'b0 == or_cond147_fu_18177_p2)) | (~(1'b0 == or_cond145_fu_18129_p2) & ~(1'b0 == or_cond146_fu_18153_p2) & ~(1'b0 == or_cond147_fu_18177_p2)))) begin
win_l1_V_1_load_1_2_phi_fu_13055_p8 = win_l0_V_39_phi_fu_6696_p128;
end else begin
win_l1_V_1_load_1_2_phi_fu_13055_p8 = ap_reg_phiprechg_win_l1_V_1_load_1_2_reg_13052pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_12_fu_18419_p2) & ~(1'b0 == tmp_366_12_fu_18443_p2) & (1'b0 == tmp_375_12_fu_18467_p2) & (1'b0 == or_cond159_fu_18485_p2)) | (~(1'b0 == tmp_366_12_fu_18443_p2) & (1'b0 == tmp_375_12_fu_18467_p2) & ~(1'b0 == or_cond157_fu_18437_p2) & (1'b0 == or_cond159_fu_18485_p2)) | (~(1'b0 == tmp_351_12_fu_18419_p2) & (1'b0 == tmp_375_12_fu_18467_p2) & ~(1'b0 == or_cond158_fu_18461_p2) & (1'b0 == or_cond159_fu_18485_p2)) | ((1'b0 == tmp_375_12_fu_18467_p2) & ~(1'b0 == or_cond157_fu_18437_p2) & ~(1'b0 == or_cond158_fu_18461_p2) & (1'b0 == or_cond159_fu_18485_p2)))) begin
win_l1_V_1_load_1_3_phi_fu_13979_p8 = win_l0_V_54_phi_fu_4686_p128;
end else if (((~(1'b0 == tmp_351_12_fu_18419_p2) & (1'b0 == tmp_366_12_fu_18443_p2) & (1'b0 == or_cond158_fu_18461_p2)) | ((1'b0 == tmp_366_12_fu_18443_p2) & ~(1'b0 == or_cond157_fu_18437_p2) & (1'b0 == or_cond158_fu_18461_p2)))) begin
win_l1_V_1_load_1_3_phi_fu_13979_p8 = win_l0_V_53_phi_fu_4820_p128;
end else if (((1'b0 == tmp_351_12_fu_18419_p2) & (1'b0 == or_cond157_fu_18437_p2))) begin
win_l1_V_1_load_1_3_phi_fu_13979_p8 = win_l0_V_52_phi_fu_4954_p128;
end else if (((~(1'b0 == tmp_351_12_fu_18419_p2) & ~(1'b0 == tmp_366_12_fu_18443_p2) & ~(1'b0 == tmp_375_12_fu_18467_p2)) | (~(1'b0 == tmp_366_12_fu_18443_p2) & ~(1'b0 == tmp_375_12_fu_18467_p2) & ~(1'b0 == or_cond157_fu_18437_p2)) | (~(1'b0 == tmp_351_12_fu_18419_p2) & ~(1'b0 == tmp_375_12_fu_18467_p2) & ~(1'b0 == or_cond158_fu_18461_p2)) | (~(1'b0 == tmp_351_12_fu_18419_p2) & ~(1'b0 == tmp_366_12_fu_18443_p2) & ~(1'b0 == or_cond159_fu_18485_p2)) | (~(1'b0 == tmp_375_12_fu_18467_p2) & ~(1'b0 == or_cond157_fu_18437_p2) & ~(1'b0 == or_cond158_fu_18461_p2)) | (~(1'b0 == tmp_366_12_fu_18443_p2) & ~(1'b0 == or_cond157_fu_18437_p2) & ~(1'b0 == or_cond159_fu_18485_p2)) | (~(1'b0 == tmp_351_12_fu_18419_p2) & ~(1'b0 == or_cond158_fu_18461_p2) & ~(1'b0 == or_cond159_fu_18485_p2)) | (~(1'b0 == or_cond157_fu_18437_p2) & ~(1'b0 == or_cond158_fu_18461_p2) & ~(1'b0 == or_cond159_fu_18485_p2)))) begin
win_l1_V_1_load_1_3_phi_fu_13979_p8 = win_l0_V_55_phi_fu_4552_p128;
end else begin
win_l1_V_1_load_1_3_phi_fu_13979_p8 = ap_reg_phiprechg_win_l1_V_1_load_1_3_reg_13976pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_1_fu_17483_p2) & ~(1'b0 == tmp_366_1_fu_17507_p2) & (1'b0 == tmp_375_1_fu_17531_p2) & (1'b0 == or_cond123_fu_17549_p2)) | (~(1'b0 == tmp_366_1_fu_17507_p2) & (1'b0 == tmp_375_1_fu_17531_p2) & ~(1'b0 == or_cond121_fu_17501_p2) & (1'b0 == or_cond123_fu_17549_p2)) | (~(1'b0 == tmp_351_1_fu_17483_p2) & (1'b0 == tmp_375_1_fu_17531_p2) & ~(1'b0 == or_cond122_fu_17525_p2) & (1'b0 == or_cond123_fu_17549_p2)) | ((1'b0 == tmp_375_1_fu_17531_p2) & ~(1'b0 == or_cond121_fu_17501_p2) & ~(1'b0 == or_cond122_fu_17525_p2) & (1'b0 == or_cond123_fu_17549_p2)))) begin
win_l1_V_1_load_1_phi_fu_12110_p8 = win_l0_V_6_phi_fu_11118_p128;
end else if (((~(1'b0 == tmp_351_1_fu_17483_p2) & (1'b0 == tmp_366_1_fu_17507_p2) & (1'b0 == or_cond122_fu_17525_p2)) | ((1'b0 == tmp_366_1_fu_17507_p2) & ~(1'b0 == or_cond121_fu_17501_p2) & (1'b0 == or_cond122_fu_17525_p2)))) begin
win_l1_V_1_load_1_phi_fu_12110_p8 = win_l0_V_5_phi_fu_11252_p128;
end else if (((1'b0 == tmp_351_1_fu_17483_p2) & (1'b0 == or_cond121_fu_17501_p2))) begin
win_l1_V_1_load_1_phi_fu_12110_p8 = win_l0_V_4_phi_fu_11386_p128;
end else if (((~(1'b0 == tmp_351_1_fu_17483_p2) & ~(1'b0 == tmp_366_1_fu_17507_p2) & ~(1'b0 == tmp_375_1_fu_17531_p2)) | (~(1'b0 == tmp_366_1_fu_17507_p2) & ~(1'b0 == tmp_375_1_fu_17531_p2) & ~(1'b0 == or_cond121_fu_17501_p2)) | (~(1'b0 == tmp_351_1_fu_17483_p2) & ~(1'b0 == tmp_375_1_fu_17531_p2) & ~(1'b0 == or_cond122_fu_17525_p2)) | (~(1'b0 == tmp_351_1_fu_17483_p2) & ~(1'b0 == tmp_366_1_fu_17507_p2) & ~(1'b0 == or_cond123_fu_17549_p2)) | (~(1'b0 == tmp_375_1_fu_17531_p2) & ~(1'b0 == or_cond121_fu_17501_p2) & ~(1'b0 == or_cond122_fu_17525_p2)) | (~(1'b0 == tmp_366_1_fu_17507_p2) & ~(1'b0 == or_cond121_fu_17501_p2) & ~(1'b0 == or_cond123_fu_17549_p2)) | (~(1'b0 == tmp_351_1_fu_17483_p2) & ~(1'b0 == or_cond122_fu_17525_p2) & ~(1'b0 == or_cond123_fu_17549_p2)) | (~(1'b0 == or_cond121_fu_17501_p2) & ~(1'b0 == or_cond122_fu_17525_p2) & ~(1'b0 == or_cond123_fu_17549_p2)))) begin
win_l1_V_1_load_1_phi_fu_12110_p8 = win_l0_V_7_phi_fu_10984_p128;
end else begin
win_l1_V_1_load_1_phi_fu_12110_p8 = ap_reg_phiprechg_win_l1_V_1_load_1_reg_12107pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_6_fu_17875_p2) & ~(1'b0 == tmp_366_6_fu_17899_p2) & (1'b0 == tmp_375_6_fu_17923_p2) & (1'b0 == or_cond138_fu_17941_p2)) | (~(1'b0 == tmp_366_6_fu_17899_p2) & (1'b0 == tmp_375_6_fu_17923_p2) & ~(1'b0 == or_cond136_fu_17893_p2) & (1'b0 == or_cond138_fu_17941_p2)) | (~(1'b0 == tmp_351_6_fu_17875_p2) & (1'b0 == tmp_375_6_fu_17923_p2) & ~(1'b0 == or_cond137_fu_17917_p2) & (1'b0 == or_cond138_fu_17941_p2)) | ((1'b0 == tmp_375_6_fu_17923_p2) & ~(1'b0 == or_cond136_fu_17893_p2) & ~(1'b0 == or_cond137_fu_17917_p2) & (1'b0 == or_cond138_fu_17941_p2)))) begin
win_l1_V_1_load_2_1_phi_fu_12548_p8 = win_l0_V_26_phi_fu_8438_p128;
end else if (((~(1'b0 == tmp_351_6_fu_17875_p2) & (1'b0 == tmp_366_6_fu_17899_p2) & (1'b0 == or_cond137_fu_17917_p2)) | ((1'b0 == tmp_366_6_fu_17899_p2) & ~(1'b0 == or_cond136_fu_17893_p2) & (1'b0 == or_cond137_fu_17917_p2)))) begin
win_l1_V_1_load_2_1_phi_fu_12548_p8 = win_l0_V_25_phi_fu_8572_p128;
end else if (((1'b0 == tmp_351_6_fu_17875_p2) & (1'b0 == or_cond136_fu_17893_p2))) begin
win_l1_V_1_load_2_1_phi_fu_12548_p8 = win_l0_V_24_phi_fu_8706_p128;
end else if (((~(1'b0 == tmp_351_6_fu_17875_p2) & ~(1'b0 == tmp_366_6_fu_17899_p2) & ~(1'b0 == tmp_375_6_fu_17923_p2)) | (~(1'b0 == tmp_366_6_fu_17899_p2) & ~(1'b0 == tmp_375_6_fu_17923_p2) & ~(1'b0 == or_cond136_fu_17893_p2)) | (~(1'b0 == tmp_351_6_fu_17875_p2) & ~(1'b0 == tmp_375_6_fu_17923_p2) & ~(1'b0 == or_cond137_fu_17917_p2)) | (~(1'b0 == tmp_351_6_fu_17875_p2) & ~(1'b0 == tmp_366_6_fu_17899_p2) & ~(1'b0 == or_cond138_fu_17941_p2)) | (~(1'b0 == tmp_375_6_fu_17923_p2) & ~(1'b0 == or_cond136_fu_17893_p2) & ~(1'b0 == or_cond137_fu_17917_p2)) | (~(1'b0 == tmp_366_6_fu_17899_p2) & ~(1'b0 == or_cond136_fu_17893_p2) & ~(1'b0 == or_cond138_fu_17941_p2)) | (~(1'b0 == tmp_351_6_fu_17875_p2) & ~(1'b0 == or_cond137_fu_17917_p2) & ~(1'b0 == or_cond138_fu_17941_p2)) | (~(1'b0 == or_cond136_fu_17893_p2) & ~(1'b0 == or_cond137_fu_17917_p2) & ~(1'b0 == or_cond138_fu_17941_p2)))) begin
win_l1_V_1_load_2_1_phi_fu_12548_p8 = win_l0_V_27_phi_fu_8304_p128;
end else begin
win_l1_V_1_load_2_1_phi_fu_12548_p8 = ap_reg_phiprechg_win_l1_V_1_load_2_1_reg_12545pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_s_fu_18187_p2) & ~(1'b0 == tmp_366_s_fu_18211_p2) & (1'b0 == tmp_375_s_fu_18235_p2) & (1'b0 == or_cond150_fu_18253_p2)) | (~(1'b0 == tmp_366_s_fu_18211_p2) & (1'b0 == tmp_375_s_fu_18235_p2) & ~(1'b0 == or_cond148_fu_18205_p2) & (1'b0 == or_cond150_fu_18253_p2)) | (~(1'b0 == tmp_351_s_fu_18187_p2) & (1'b0 == tmp_375_s_fu_18235_p2) & ~(1'b0 == or_cond149_fu_18229_p2) & (1'b0 == or_cond150_fu_18253_p2)) | ((1'b0 == tmp_375_s_fu_18235_p2) & ~(1'b0 == or_cond148_fu_18205_p2) & ~(1'b0 == or_cond149_fu_18229_p2) & (1'b0 == or_cond150_fu_18253_p2)))) begin
win_l1_V_1_load_2_2_phi_fu_13286_p8 = win_l0_V_42_phi_fu_6294_p128;
end else if (((~(1'b0 == tmp_351_s_fu_18187_p2) & (1'b0 == tmp_366_s_fu_18211_p2) & (1'b0 == or_cond149_fu_18229_p2)) | ((1'b0 == tmp_366_s_fu_18211_p2) & ~(1'b0 == or_cond148_fu_18205_p2) & (1'b0 == or_cond149_fu_18229_p2)))) begin
win_l1_V_1_load_2_2_phi_fu_13286_p8 = win_l0_V_41_phi_fu_6428_p128;
end else if (((1'b0 == tmp_351_s_fu_18187_p2) & (1'b0 == or_cond148_fu_18205_p2))) begin
win_l1_V_1_load_2_2_phi_fu_13286_p8 = win_l0_V_40_phi_fu_6562_p128;
end else if (((~(1'b0 == tmp_351_s_fu_18187_p2) & ~(1'b0 == tmp_366_s_fu_18211_p2) & ~(1'b0 == tmp_375_s_fu_18235_p2)) | (~(1'b0 == tmp_366_s_fu_18211_p2) & ~(1'b0 == tmp_375_s_fu_18235_p2) & ~(1'b0 == or_cond148_fu_18205_p2)) | (~(1'b0 == tmp_351_s_fu_18187_p2) & ~(1'b0 == tmp_375_s_fu_18235_p2) & ~(1'b0 == or_cond149_fu_18229_p2)) | (~(1'b0 == tmp_351_s_fu_18187_p2) & ~(1'b0 == tmp_366_s_fu_18211_p2) & ~(1'b0 == or_cond150_fu_18253_p2)) | (~(1'b0 == tmp_375_s_fu_18235_p2) & ~(1'b0 == or_cond148_fu_18205_p2) & ~(1'b0 == or_cond149_fu_18229_p2)) | (~(1'b0 == tmp_366_s_fu_18211_p2) & ~(1'b0 == or_cond148_fu_18205_p2) & ~(1'b0 == or_cond150_fu_18253_p2)) | (~(1'b0 == tmp_351_s_fu_18187_p2) & ~(1'b0 == or_cond149_fu_18229_p2) & ~(1'b0 == or_cond150_fu_18253_p2)) | (~(1'b0 == or_cond148_fu_18205_p2) & ~(1'b0 == or_cond149_fu_18229_p2) & ~(1'b0 == or_cond150_fu_18253_p2)))) begin
win_l1_V_1_load_2_2_phi_fu_13286_p8 = win_l0_V_43_phi_fu_6160_p128;
end else begin
win_l1_V_1_load_2_2_phi_fu_13286_p8 = ap_reg_phiprechg_win_l1_V_1_load_2_2_reg_13283pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_13_fu_18499_p2) & ~(1'b0 == tmp_366_13_fu_18523_p2) & (1'b0 == tmp_375_13_fu_18547_p2) & (1'b0 == or_cond162_fu_18565_p2)) | (~(1'b0 == tmp_366_13_fu_18523_p2) & (1'b0 == tmp_375_13_fu_18547_p2) & ~(1'b0 == or_cond160_fu_18517_p2) & (1'b0 == or_cond162_fu_18565_p2)) | (~(1'b0 == tmp_351_13_fu_18499_p2) & (1'b0 == tmp_375_13_fu_18547_p2) & ~(1'b0 == or_cond161_fu_18541_p2) & (1'b0 == or_cond162_fu_18565_p2)) | ((1'b0 == tmp_375_13_fu_18547_p2) & ~(1'b0 == or_cond160_fu_18517_p2) & ~(1'b0 == or_cond161_fu_18541_p2) & (1'b0 == or_cond162_fu_18565_p2)))) begin
win_l1_V_1_load_2_3_phi_fu_14210_p8 = win_l0_V_58_phi_fu_4150_p128;
end else if (((~(1'b0 == tmp_351_13_fu_18499_p2) & (1'b0 == tmp_366_13_fu_18523_p2) & (1'b0 == or_cond161_fu_18541_p2)) | ((1'b0 == tmp_366_13_fu_18523_p2) & ~(1'b0 == or_cond160_fu_18517_p2) & (1'b0 == or_cond161_fu_18541_p2)))) begin
win_l1_V_1_load_2_3_phi_fu_14210_p8 = win_l0_V_57_phi_fu_4284_p128;
end else if (((1'b0 == tmp_351_13_fu_18499_p2) & (1'b0 == or_cond160_fu_18517_p2))) begin
win_l1_V_1_load_2_3_phi_fu_14210_p8 = win_l0_V_56_phi_fu_4418_p128;
end else if (((~(1'b0 == tmp_351_13_fu_18499_p2) & ~(1'b0 == tmp_366_13_fu_18523_p2) & ~(1'b0 == tmp_375_13_fu_18547_p2)) | (~(1'b0 == tmp_366_13_fu_18523_p2) & ~(1'b0 == tmp_375_13_fu_18547_p2) & ~(1'b0 == or_cond160_fu_18517_p2)) | (~(1'b0 == tmp_351_13_fu_18499_p2) & ~(1'b0 == tmp_375_13_fu_18547_p2) & ~(1'b0 == or_cond161_fu_18541_p2)) | (~(1'b0 == tmp_351_13_fu_18499_p2) & ~(1'b0 == tmp_366_13_fu_18523_p2) & ~(1'b0 == or_cond162_fu_18565_p2)) | (~(1'b0 == tmp_375_13_fu_18547_p2) & ~(1'b0 == or_cond160_fu_18517_p2) & ~(1'b0 == or_cond161_fu_18541_p2)) | (~(1'b0 == tmp_366_13_fu_18523_p2) & ~(1'b0 == or_cond160_fu_18517_p2) & ~(1'b0 == or_cond162_fu_18565_p2)) | (~(1'b0 == tmp_351_13_fu_18499_p2) & ~(1'b0 == or_cond161_fu_18541_p2) & ~(1'b0 == or_cond162_fu_18565_p2)) | (~(1'b0 == or_cond160_fu_18517_p2) & ~(1'b0 == or_cond161_fu_18541_p2) & ~(1'b0 == or_cond162_fu_18565_p2)))) begin
win_l1_V_1_load_2_3_phi_fu_14210_p8 = win_l0_V_1_phi_fu_4016_p128;
end else begin
win_l1_V_1_load_2_3_phi_fu_14210_p8 = ap_reg_phiprechg_win_l1_V_1_load_2_3_reg_14207pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_2_fu_17563_p2) & ~(1'b0 == tmp_366_2_fu_17587_p2) & (1'b0 == tmp_375_2_fu_17611_p2) & (1'b0 == or_cond126_fu_17629_p2)) | (~(1'b0 == tmp_366_2_fu_17587_p2) & (1'b0 == tmp_375_2_fu_17611_p2) & ~(1'b0 == or_cond124_fu_17581_p2) & (1'b0 == or_cond126_fu_17629_p2)) | (~(1'b0 == tmp_351_2_fu_17563_p2) & (1'b0 == tmp_375_2_fu_17611_p2) & ~(1'b0 == or_cond125_fu_17605_p2) & (1'b0 == or_cond126_fu_17629_p2)) | ((1'b0 == tmp_375_2_fu_17611_p2) & ~(1'b0 == or_cond124_fu_17581_p2) & ~(1'b0 == or_cond125_fu_17605_p2) & (1'b0 == or_cond126_fu_17629_p2)))) begin
win_l1_V_1_load_2_phi_fu_12164_p8 = win_l0_V_10_phi_fu_10582_p128;
end else if (((~(1'b0 == tmp_351_2_fu_17563_p2) & (1'b0 == tmp_366_2_fu_17587_p2) & (1'b0 == or_cond125_fu_17605_p2)) | ((1'b0 == tmp_366_2_fu_17587_p2) & ~(1'b0 == or_cond124_fu_17581_p2) & (1'b0 == or_cond125_fu_17605_p2)))) begin
win_l1_V_1_load_2_phi_fu_12164_p8 = win_l0_V_9_phi_fu_10716_p128;
end else if (((1'b0 == tmp_351_2_fu_17563_p2) & (1'b0 == or_cond124_fu_17581_p2))) begin
win_l1_V_1_load_2_phi_fu_12164_p8 = win_l0_V_8_phi_fu_10850_p128;
end else if (((~(1'b0 == tmp_351_2_fu_17563_p2) & ~(1'b0 == tmp_366_2_fu_17587_p2) & ~(1'b0 == tmp_375_2_fu_17611_p2)) | (~(1'b0 == tmp_366_2_fu_17587_p2) & ~(1'b0 == tmp_375_2_fu_17611_p2) & ~(1'b0 == or_cond124_fu_17581_p2)) | (~(1'b0 == tmp_351_2_fu_17563_p2) & ~(1'b0 == tmp_375_2_fu_17611_p2) & ~(1'b0 == or_cond125_fu_17605_p2)) | (~(1'b0 == tmp_351_2_fu_17563_p2) & ~(1'b0 == tmp_366_2_fu_17587_p2) & ~(1'b0 == or_cond126_fu_17629_p2)) | (~(1'b0 == tmp_375_2_fu_17611_p2) & ~(1'b0 == or_cond124_fu_17581_p2) & ~(1'b0 == or_cond125_fu_17605_p2)) | (~(1'b0 == tmp_366_2_fu_17587_p2) & ~(1'b0 == or_cond124_fu_17581_p2) & ~(1'b0 == or_cond126_fu_17629_p2)) | (~(1'b0 == tmp_351_2_fu_17563_p2) & ~(1'b0 == or_cond125_fu_17605_p2) & ~(1'b0 == or_cond126_fu_17629_p2)) | (~(1'b0 == or_cond124_fu_17581_p2) & ~(1'b0 == or_cond125_fu_17605_p2) & ~(1'b0 == or_cond126_fu_17629_p2)))) begin
win_l1_V_1_load_2_phi_fu_12164_p8 = win_l0_V_11_phi_fu_10448_p128;
end else begin
win_l1_V_1_load_2_phi_fu_12164_p8 = ap_reg_phiprechg_win_l1_V_1_load_2_reg_12161pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_7_fu_17955_p2) & ~(1'b0 == tmp_366_7_fu_17979_p2) & (1'b0 == tmp_375_7_fu_18003_p2) & (1'b0 == or_cond141_fu_18021_p2)) | (~(1'b0 == tmp_366_7_fu_17979_p2) & (1'b0 == tmp_375_7_fu_18003_p2) & ~(1'b0 == or_cond139_fu_17973_p2) & (1'b0 == or_cond141_fu_18021_p2)) | (~(1'b0 == tmp_351_7_fu_17955_p2) & (1'b0 == tmp_375_7_fu_18003_p2) & ~(1'b0 == or_cond140_fu_17997_p2) & (1'b0 == or_cond141_fu_18021_p2)) | ((1'b0 == tmp_375_7_fu_18003_p2) & ~(1'b0 == or_cond139_fu_17973_p2) & ~(1'b0 == or_cond140_fu_17997_p2) & (1'b0 == or_cond141_fu_18021_p2)))) begin
win_l1_V_1_load_3_1_phi_fu_12686_p8 = win_l0_V_30_phi_fu_7902_p128;
end else if (((~(1'b0 == tmp_351_7_fu_17955_p2) & (1'b0 == tmp_366_7_fu_17979_p2) & (1'b0 == or_cond140_fu_17997_p2)) | ((1'b0 == tmp_366_7_fu_17979_p2) & ~(1'b0 == or_cond139_fu_17973_p2) & (1'b0 == or_cond140_fu_17997_p2)))) begin
win_l1_V_1_load_3_1_phi_fu_12686_p8 = win_l0_V_29_phi_fu_8036_p128;
end else if (((1'b0 == tmp_351_7_fu_17955_p2) & (1'b0 == or_cond139_fu_17973_p2))) begin
win_l1_V_1_load_3_1_phi_fu_12686_p8 = win_l0_V_28_phi_fu_8170_p128;
end else if (((~(1'b0 == tmp_351_7_fu_17955_p2) & ~(1'b0 == tmp_366_7_fu_17979_p2) & ~(1'b0 == tmp_375_7_fu_18003_p2)) | (~(1'b0 == tmp_366_7_fu_17979_p2) & ~(1'b0 == tmp_375_7_fu_18003_p2) & ~(1'b0 == or_cond139_fu_17973_p2)) | (~(1'b0 == tmp_351_7_fu_17955_p2) & ~(1'b0 == tmp_375_7_fu_18003_p2) & ~(1'b0 == or_cond140_fu_17997_p2)) | (~(1'b0 == tmp_351_7_fu_17955_p2) & ~(1'b0 == tmp_366_7_fu_17979_p2) & ~(1'b0 == or_cond141_fu_18021_p2)) | (~(1'b0 == tmp_375_7_fu_18003_p2) & ~(1'b0 == or_cond139_fu_17973_p2) & ~(1'b0 == or_cond140_fu_17997_p2)) | (~(1'b0 == tmp_366_7_fu_17979_p2) & ~(1'b0 == or_cond139_fu_17973_p2) & ~(1'b0 == or_cond141_fu_18021_p2)) | (~(1'b0 == tmp_351_7_fu_17955_p2) & ~(1'b0 == or_cond140_fu_17997_p2) & ~(1'b0 == or_cond141_fu_18021_p2)) | (~(1'b0 == or_cond139_fu_17973_p2) & ~(1'b0 == or_cond140_fu_17997_p2) & ~(1'b0 == or_cond141_fu_18021_p2)))) begin
win_l1_V_1_load_3_1_phi_fu_12686_p8 = win_l0_V_31_phi_fu_7768_p128;
end else begin
win_l1_V_1_load_3_1_phi_fu_12686_p8 = ap_reg_phiprechg_win_l1_V_1_load_3_1_reg_12683pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_10_fu_18263_p2) & ~(1'b0 == tmp_366_10_fu_18287_p2) & (1'b0 == tmp_375_10_fu_18311_p2) & (1'b0 == or_cond153_fu_18329_p2)) | (~(1'b0 == tmp_366_10_fu_18287_p2) & (1'b0 == tmp_375_10_fu_18311_p2) & ~(1'b0 == or_cond151_fu_18281_p2) & (1'b0 == or_cond153_fu_18329_p2)) | (~(1'b0 == tmp_351_10_fu_18263_p2) & (1'b0 == tmp_375_10_fu_18311_p2) & ~(1'b0 == or_cond152_fu_18305_p2) & (1'b0 == or_cond153_fu_18329_p2)) | ((1'b0 == tmp_375_10_fu_18311_p2) & ~(1'b0 == or_cond151_fu_18281_p2) & ~(1'b0 == or_cond152_fu_18305_p2) & (1'b0 == or_cond153_fu_18329_p2)))) begin
win_l1_V_1_load_3_2_phi_fu_13517_p8 = win_l0_V_46_phi_fu_5758_p128;
end else if (((~(1'b0 == tmp_351_10_fu_18263_p2) & (1'b0 == tmp_366_10_fu_18287_p2) & (1'b0 == or_cond152_fu_18305_p2)) | ((1'b0 == tmp_366_10_fu_18287_p2) & ~(1'b0 == or_cond151_fu_18281_p2) & (1'b0 == or_cond152_fu_18305_p2)))) begin
win_l1_V_1_load_3_2_phi_fu_13517_p8 = win_l0_V_45_phi_fu_5892_p128;
end else if (((1'b0 == tmp_351_10_fu_18263_p2) & (1'b0 == or_cond151_fu_18281_p2))) begin
win_l1_V_1_load_3_2_phi_fu_13517_p8 = win_l0_V_44_phi_fu_6026_p128;
end else if (((~(1'b0 == tmp_351_10_fu_18263_p2) & ~(1'b0 == tmp_366_10_fu_18287_p2) & ~(1'b0 == tmp_375_10_fu_18311_p2)) | (~(1'b0 == tmp_366_10_fu_18287_p2) & ~(1'b0 == tmp_375_10_fu_18311_p2) & ~(1'b0 == or_cond151_fu_18281_p2)) | (~(1'b0 == tmp_351_10_fu_18263_p2) & ~(1'b0 == tmp_375_10_fu_18311_p2) & ~(1'b0 == or_cond152_fu_18305_p2)) | (~(1'b0 == tmp_351_10_fu_18263_p2) & ~(1'b0 == tmp_366_10_fu_18287_p2) & ~(1'b0 == or_cond153_fu_18329_p2)) | (~(1'b0 == tmp_375_10_fu_18311_p2) & ~(1'b0 == or_cond151_fu_18281_p2) & ~(1'b0 == or_cond152_fu_18305_p2)) | (~(1'b0 == tmp_366_10_fu_18287_p2) & ~(1'b0 == or_cond151_fu_18281_p2) & ~(1'b0 == or_cond153_fu_18329_p2)) | (~(1'b0 == tmp_351_10_fu_18263_p2) & ~(1'b0 == or_cond152_fu_18305_p2) & ~(1'b0 == or_cond153_fu_18329_p2)) | (~(1'b0 == or_cond151_fu_18281_p2) & ~(1'b0 == or_cond152_fu_18305_p2) & ~(1'b0 == or_cond153_fu_18329_p2)))) begin
win_l1_V_1_load_3_2_phi_fu_13517_p8 = win_l0_V_47_phi_fu_5624_p128;
end else begin
win_l1_V_1_load_3_2_phi_fu_13517_p8 = ap_reg_phiprechg_win_l1_V_1_load_3_2_reg_13514pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_3_fu_17643_p2) & ~(1'b0 == tmp_366_3_fu_17667_p2) & (1'b0 == tmp_375_3_fu_17691_p2) & (1'b0 == or_cond129_fu_17709_p2)) | (~(1'b0 == tmp_366_3_fu_17667_p2) & (1'b0 == tmp_375_3_fu_17691_p2) & ~(1'b0 == or_cond127_fu_17661_p2) & (1'b0 == or_cond129_fu_17709_p2)) | (~(1'b0 == tmp_351_3_fu_17643_p2) & (1'b0 == tmp_375_3_fu_17691_p2) & ~(1'b0 == or_cond128_fu_17685_p2) & (1'b0 == or_cond129_fu_17709_p2)) | ((1'b0 == tmp_375_3_fu_17691_p2) & ~(1'b0 == or_cond127_fu_17661_p2) & ~(1'b0 == or_cond128_fu_17685_p2) & (1'b0 == or_cond129_fu_17709_p2)))) begin
win_l1_V_1_load_3_phi_fu_12218_p8 = win_l0_V_14_phi_fu_10046_p128;
end else if (((~(1'b0 == tmp_351_3_fu_17643_p2) & (1'b0 == tmp_366_3_fu_17667_p2) & (1'b0 == or_cond128_fu_17685_p2)) | ((1'b0 == tmp_366_3_fu_17667_p2) & ~(1'b0 == or_cond127_fu_17661_p2) & (1'b0 == or_cond128_fu_17685_p2)))) begin
win_l1_V_1_load_3_phi_fu_12218_p8 = win_l0_V_13_phi_fu_10180_p128;
end else if (((1'b0 == tmp_351_3_fu_17643_p2) & (1'b0 == or_cond127_fu_17661_p2))) begin
win_l1_V_1_load_3_phi_fu_12218_p8 = win_l0_V_12_phi_fu_10314_p128;
end else if (((~(1'b0 == tmp_351_3_fu_17643_p2) & ~(1'b0 == tmp_366_3_fu_17667_p2) & ~(1'b0 == tmp_375_3_fu_17691_p2)) | (~(1'b0 == tmp_366_3_fu_17667_p2) & ~(1'b0 == tmp_375_3_fu_17691_p2) & ~(1'b0 == or_cond127_fu_17661_p2)) | (~(1'b0 == tmp_351_3_fu_17643_p2) & ~(1'b0 == tmp_375_3_fu_17691_p2) & ~(1'b0 == or_cond128_fu_17685_p2)) | (~(1'b0 == tmp_351_3_fu_17643_p2) & ~(1'b0 == tmp_366_3_fu_17667_p2) & ~(1'b0 == or_cond129_fu_17709_p2)) | (~(1'b0 == tmp_375_3_fu_17691_p2) & ~(1'b0 == or_cond127_fu_17661_p2) & ~(1'b0 == or_cond128_fu_17685_p2)) | (~(1'b0 == tmp_366_3_fu_17667_p2) & ~(1'b0 == or_cond127_fu_17661_p2) & ~(1'b0 == or_cond129_fu_17709_p2)) | (~(1'b0 == tmp_351_3_fu_17643_p2) & ~(1'b0 == or_cond128_fu_17685_p2) & ~(1'b0 == or_cond129_fu_17709_p2)) | (~(1'b0 == or_cond127_fu_17661_p2) & ~(1'b0 == or_cond128_fu_17685_p2) & ~(1'b0 == or_cond129_fu_17709_p2)))) begin
win_l1_V_1_load_3_phi_fu_12218_p8 = win_l0_V_15_phi_fu_9912_p128;
end else begin
win_l1_V_1_load_3_phi_fu_12218_p8 = ap_reg_phiprechg_win_l1_V_1_load_3_reg_12215pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_8_fu_18035_p2) & ~(1'b0 == tmp_366_8_fu_18059_p2) & (1'b0 == tmp_375_8_fu_18083_p2) & (1'b0 == or_cond144_fu_18101_p2)) | (~(1'b0 == tmp_366_8_fu_18059_p2) & (1'b0 == tmp_375_8_fu_18083_p2) & ~(1'b0 == or_cond142_fu_18053_p2) & (1'b0 == or_cond144_fu_18101_p2)) | (~(1'b0 == tmp_351_8_fu_18035_p2) & (1'b0 == tmp_375_8_fu_18083_p2) & ~(1'b0 == or_cond143_fu_18077_p2) & (1'b0 == or_cond144_fu_18101_p2)) | ((1'b0 == tmp_375_8_fu_18083_p2) & ~(1'b0 == or_cond142_fu_18053_p2) & ~(1'b0 == or_cond143_fu_18077_p2) & (1'b0 == or_cond144_fu_18101_p2)))) begin
win_l1_V_1_load_4_phi_fu_12824_p8 = win_l0_V_34_phi_fu_7366_p128;
end else if (((~(1'b0 == tmp_351_8_fu_18035_p2) & (1'b0 == tmp_366_8_fu_18059_p2) & (1'b0 == or_cond143_fu_18077_p2)) | ((1'b0 == tmp_366_8_fu_18059_p2) & ~(1'b0 == or_cond142_fu_18053_p2) & (1'b0 == or_cond143_fu_18077_p2)))) begin
win_l1_V_1_load_4_phi_fu_12824_p8 = win_l0_V_33_phi_fu_7500_p128;
end else if (((1'b0 == tmp_351_8_fu_18035_p2) & (1'b0 == or_cond142_fu_18053_p2))) begin
win_l1_V_1_load_4_phi_fu_12824_p8 = win_l0_V_32_phi_fu_7634_p128;
end else if (((~(1'b0 == tmp_351_8_fu_18035_p2) & ~(1'b0 == tmp_366_8_fu_18059_p2) & ~(1'b0 == tmp_375_8_fu_18083_p2)) | (~(1'b0 == tmp_366_8_fu_18059_p2) & ~(1'b0 == tmp_375_8_fu_18083_p2) & ~(1'b0 == or_cond142_fu_18053_p2)) | (~(1'b0 == tmp_351_8_fu_18035_p2) & ~(1'b0 == tmp_375_8_fu_18083_p2) & ~(1'b0 == or_cond143_fu_18077_p2)) | (~(1'b0 == tmp_351_8_fu_18035_p2) & ~(1'b0 == tmp_366_8_fu_18059_p2) & ~(1'b0 == or_cond144_fu_18101_p2)) | (~(1'b0 == tmp_375_8_fu_18083_p2) & ~(1'b0 == or_cond142_fu_18053_p2) & ~(1'b0 == or_cond143_fu_18077_p2)) | (~(1'b0 == tmp_366_8_fu_18059_p2) & ~(1'b0 == or_cond142_fu_18053_p2) & ~(1'b0 == or_cond144_fu_18101_p2)) | (~(1'b0 == tmp_351_8_fu_18035_p2) & ~(1'b0 == or_cond143_fu_18077_p2) & ~(1'b0 == or_cond144_fu_18101_p2)) | (~(1'b0 == or_cond142_fu_18053_p2) & ~(1'b0 == or_cond143_fu_18077_p2) & ~(1'b0 == or_cond144_fu_18101_p2)))) begin
win_l1_V_1_load_4_phi_fu_12824_p8 = win_l0_V_35_phi_fu_7232_p128;
end else begin
win_l1_V_1_load_4_phi_fu_12824_p8 = ap_reg_phiprechg_win_l1_V_1_load_4_reg_12821pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_11_fu_18339_p2) & ~(1'b0 == tmp_366_11_fu_18363_p2) & (1'b0 == tmp_375_11_fu_18387_p2) & (1'b0 == or_cond156_fu_18405_p2)) | (~(1'b0 == tmp_366_11_fu_18363_p2) & (1'b0 == tmp_375_11_fu_18387_p2) & ~(1'b0 == or_cond154_fu_18357_p2) & (1'b0 == or_cond156_fu_18405_p2)) | (~(1'b0 == tmp_351_11_fu_18339_p2) & (1'b0 == tmp_375_11_fu_18387_p2) & ~(1'b0 == or_cond155_fu_18381_p2) & (1'b0 == or_cond156_fu_18405_p2)) | ((1'b0 == tmp_375_11_fu_18387_p2) & ~(1'b0 == or_cond154_fu_18357_p2) & ~(1'b0 == or_cond155_fu_18381_p2) & (1'b0 == or_cond156_fu_18405_p2)))) begin
win_l1_V_1_load_5_phi_fu_13748_p8 = win_l0_V_50_phi_fu_5222_p128;
end else if (((~(1'b0 == tmp_351_11_fu_18339_p2) & (1'b0 == tmp_366_11_fu_18363_p2) & (1'b0 == or_cond155_fu_18381_p2)) | ((1'b0 == tmp_366_11_fu_18363_p2) & ~(1'b0 == or_cond154_fu_18357_p2) & (1'b0 == or_cond155_fu_18381_p2)))) begin
win_l1_V_1_load_5_phi_fu_13748_p8 = win_l0_V_49_phi_fu_5356_p128;
end else if (((1'b0 == tmp_351_11_fu_18339_p2) & (1'b0 == or_cond154_fu_18357_p2))) begin
win_l1_V_1_load_5_phi_fu_13748_p8 = win_l0_V_48_phi_fu_5490_p128;
end else if (((~(1'b0 == tmp_351_11_fu_18339_p2) & ~(1'b0 == tmp_366_11_fu_18363_p2) & ~(1'b0 == tmp_375_11_fu_18387_p2)) | (~(1'b0 == tmp_366_11_fu_18363_p2) & ~(1'b0 == tmp_375_11_fu_18387_p2) & ~(1'b0 == or_cond154_fu_18357_p2)) | (~(1'b0 == tmp_351_11_fu_18339_p2) & ~(1'b0 == tmp_375_11_fu_18387_p2) & ~(1'b0 == or_cond155_fu_18381_p2)) | (~(1'b0 == tmp_351_11_fu_18339_p2) & ~(1'b0 == tmp_366_11_fu_18363_p2) & ~(1'b0 == or_cond156_fu_18405_p2)) | (~(1'b0 == tmp_375_11_fu_18387_p2) & ~(1'b0 == or_cond154_fu_18357_p2) & ~(1'b0 == or_cond155_fu_18381_p2)) | (~(1'b0 == tmp_366_11_fu_18363_p2) & ~(1'b0 == or_cond154_fu_18357_p2) & ~(1'b0 == or_cond156_fu_18405_p2)) | (~(1'b0 == tmp_351_11_fu_18339_p2) & ~(1'b0 == or_cond155_fu_18381_p2) & ~(1'b0 == or_cond156_fu_18405_p2)) | (~(1'b0 == or_cond154_fu_18357_p2) & ~(1'b0 == or_cond155_fu_18381_p2) & ~(1'b0 == or_cond156_fu_18405_p2)))) begin
win_l1_V_1_load_5_phi_fu_13748_p8 = win_l0_V_51_phi_fu_5088_p128;
end else begin
win_l1_V_1_load_5_phi_fu_13748_p8 = ap_reg_phiprechg_win_l1_V_1_load_5_reg_13745pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_226_fu_17403_p2) & ~(1'b0 == tmp_229_fu_17427_p2) & (1'b0 == tmp_232_fu_17451_p2) & (1'b0 == or_cond120_fu_17469_p2)) | (~(1'b0 == tmp_229_fu_17427_p2) & (1'b0 == tmp_232_fu_17451_p2) & ~(1'b0 == or_cond118_fu_17421_p2) & (1'b0 == or_cond120_fu_17469_p2)) | (~(1'b0 == tmp_226_fu_17403_p2) & (1'b0 == tmp_232_fu_17451_p2) & ~(1'b0 == or_cond119_fu_17445_p2) & (1'b0 == or_cond120_fu_17469_p2)) | ((1'b0 == tmp_232_fu_17451_p2) & ~(1'b0 == or_cond118_fu_17421_p2) & ~(1'b0 == or_cond119_fu_17445_p2) & (1'b0 == or_cond120_fu_17469_p2)))) begin
win_l1_V_1_load_phi_fu_12056_p8 = win_l0_V_2_phi_fu_11654_p128;
end else if (((~(1'b0 == tmp_226_fu_17403_p2) & (1'b0 == tmp_229_fu_17427_p2) & (1'b0 == or_cond119_fu_17445_p2)) | ((1'b0 == tmp_229_fu_17427_p2) & ~(1'b0 == or_cond118_fu_17421_p2) & (1'b0 == or_cond119_fu_17445_p2)))) begin
win_l1_V_1_load_phi_fu_12056_p8 = win_l0_V_59_phi_fu_11788_p128;
end else if (((1'b0 == tmp_226_fu_17403_p2) & (1'b0 == or_cond118_fu_17421_p2))) begin
win_l1_V_1_load_phi_fu_12056_p8 = win_l0_V_phi_fu_11922_p128;
end else if (((~(1'b0 == tmp_226_fu_17403_p2) & ~(1'b0 == tmp_229_fu_17427_p2) & ~(1'b0 == tmp_232_fu_17451_p2)) | (~(1'b0 == tmp_229_fu_17427_p2) & ~(1'b0 == tmp_232_fu_17451_p2) & ~(1'b0 == or_cond118_fu_17421_p2)) | (~(1'b0 == tmp_226_fu_17403_p2) & ~(1'b0 == tmp_232_fu_17451_p2) & ~(1'b0 == or_cond119_fu_17445_p2)) | (~(1'b0 == tmp_226_fu_17403_p2) & ~(1'b0 == tmp_229_fu_17427_p2) & ~(1'b0 == or_cond120_fu_17469_p2)) | (~(1'b0 == tmp_232_fu_17451_p2) & ~(1'b0 == or_cond118_fu_17421_p2) & ~(1'b0 == or_cond119_fu_17445_p2)) | (~(1'b0 == tmp_229_fu_17427_p2) & ~(1'b0 == or_cond118_fu_17421_p2) & ~(1'b0 == or_cond120_fu_17469_p2)) | (~(1'b0 == tmp_226_fu_17403_p2) & ~(1'b0 == or_cond119_fu_17445_p2) & ~(1'b0 == or_cond120_fu_17469_p2)) | (~(1'b0 == or_cond118_fu_17421_p2) & ~(1'b0 == or_cond119_fu_17445_p2) & ~(1'b0 == or_cond120_fu_17469_p2)))) begin
win_l1_V_1_load_phi_fu_12056_p8 = win_l0_V_3_phi_fu_11520_p128;
end else begin
win_l1_V_1_load_phi_fu_12056_p8 = ap_reg_phiprechg_win_l1_V_1_load_reg_12053pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_351_4_fu_17723_p2) & ~(1'b0 == tmp_366_4_fu_17747_p2) & (1'b0 == tmp_375_4_fu_17771_p2) & (1'b0 == or_cond132_fu_17789_p2)) | (~(1'b0 == tmp_366_4_fu_17747_p2) & (1'b0 == tmp_375_4_fu_17771_p2) & ~(1'b0 == or_cond130_fu_17741_p2) & (1'b0 == or_cond132_fu_17789_p2)) | (~(1'b0 == tmp_351_4_fu_17723_p2) & (1'b0 == tmp_375_4_fu_17771_p2) & ~(1'b0 == or_cond131_fu_17765_p2) & (1'b0 == or_cond132_fu_17789_p2)) | ((1'b0 == tmp_375_4_fu_17771_p2) & ~(1'b0 == or_cond130_fu_17741_p2) & ~(1'b0 == or_cond131_fu_17765_p2) & (1'b0 == or_cond132_fu_17789_p2)))) begin
win_l1_V_1_load_s_phi_fu_12272_p8 = win_l0_V_18_phi_fu_9510_p128;
end else if (((~(1'b0 == tmp_351_4_fu_17723_p2) & (1'b0 == tmp_366_4_fu_17747_p2) & (1'b0 == or_cond131_fu_17765_p2)) | ((1'b0 == tmp_366_4_fu_17747_p2) & ~(1'b0 == or_cond130_fu_17741_p2) & (1'b0 == or_cond131_fu_17765_p2)))) begin
win_l1_V_1_load_s_phi_fu_12272_p8 = win_l0_V_17_phi_fu_9644_p128;
end else if (((1'b0 == tmp_351_4_fu_17723_p2) & (1'b0 == or_cond130_fu_17741_p2))) begin
win_l1_V_1_load_s_phi_fu_12272_p8 = win_l0_V_16_phi_fu_9778_p128;
end else if (((~(1'b0 == tmp_351_4_fu_17723_p2) & ~(1'b0 == tmp_366_4_fu_17747_p2) & ~(1'b0 == tmp_375_4_fu_17771_p2)) | (~(1'b0 == tmp_366_4_fu_17747_p2) & ~(1'b0 == tmp_375_4_fu_17771_p2) & ~(1'b0 == or_cond130_fu_17741_p2)) | (~(1'b0 == tmp_351_4_fu_17723_p2) & ~(1'b0 == tmp_375_4_fu_17771_p2) & ~(1'b0 == or_cond131_fu_17765_p2)) | (~(1'b0 == tmp_351_4_fu_17723_p2) & ~(1'b0 == tmp_366_4_fu_17747_p2) & ~(1'b0 == or_cond132_fu_17789_p2)) | (~(1'b0 == tmp_375_4_fu_17771_p2) & ~(1'b0 == or_cond130_fu_17741_p2) & ~(1'b0 == or_cond131_fu_17765_p2)) | (~(1'b0 == tmp_366_4_fu_17747_p2) & ~(1'b0 == or_cond130_fu_17741_p2) & ~(1'b0 == or_cond132_fu_17789_p2)) | (~(1'b0 == tmp_351_4_fu_17723_p2) & ~(1'b0 == or_cond131_fu_17765_p2) & ~(1'b0 == or_cond132_fu_17789_p2)) | (~(1'b0 == or_cond130_fu_17741_p2) & ~(1'b0 == or_cond131_fu_17765_p2) & ~(1'b0 == or_cond132_fu_17789_p2)))) begin
win_l1_V_1_load_s_phi_fu_12272_p8 = win_l0_V_19_phi_fu_9376_p128;
end else begin
win_l1_V_1_load_s_phi_fu_12272_p8 = ap_reg_phiprechg_win_l1_V_1_load_s_reg_12269pp0_it1;
end
end
always @ (*) begin
if (((~(tmp_294_4_fu_15554_p2 == 1'b0) & ~(1'b0 == tmp_309_4_fu_15578_p2) & (1'b0 == tmp_318_4_fu_15602_p2) & (1'b0 == or_cond87_fu_15620_p2)) | (~(1'b0 == tmp_309_4_fu_15578_p2) & (1'b0 == tmp_318_4_fu_15602_p2) & ~(1'b0 == or_cond85_fu_15572_p2) & (1'b0 == or_cond87_fu_15620_p2)) | (~(tmp_294_4_fu_15554_p2 == 1'b0) & (1'b0 == tmp_318_4_fu_15602_p2) & ~(1'b0 == or_cond86_fu_15596_p2) & (1'b0 == or_cond87_fu_15620_p2)) | ((1'b0 == tmp_318_4_fu_15602_p2) & ~(1'b0 == or_cond85_fu_15572_p2) & ~(1'b0 == or_cond86_fu_15596_p2) & (1'b0 == or_cond87_fu_15620_p2)))) begin
win_l1_V_load_1_phi_fu_1357_p8 = call_ret_sp_sort_fu_14608_ap_return_20;
end else if (((~(tmp_294_4_fu_15554_p2 == 1'b0) & (1'b0 == tmp_309_4_fu_15578_p2) & (1'b0 == or_cond86_fu_15596_p2)) | ((1'b0 == tmp_309_4_fu_15578_p2) & ~(1'b0 == or_cond85_fu_15572_p2) & (1'b0 == or_cond86_fu_15596_p2)))) begin
win_l1_V_load_1_phi_fu_1357_p8 = call_ret_sp_sort_fu_14608_ap_return_19;
end else if (((tmp_294_4_fu_15554_p2 == 1'b0) & (1'b0 == or_cond85_fu_15572_p2))) begin
win_l1_V_load_1_phi_fu_1357_p8 = call_ret_sp_sort_fu_14608_ap_return_18;
end else if (((~(tmp_294_4_fu_15554_p2 == 1'b0) & ~(1'b0 == tmp_309_4_fu_15578_p2) & ~(1'b0 == tmp_318_4_fu_15602_p2)) | (~(1'b0 == tmp_309_4_fu_15578_p2) & ~(1'b0 == tmp_318_4_fu_15602_p2) & ~(1'b0 == or_cond85_fu_15572_p2)) | (~(tmp_294_4_fu_15554_p2 == 1'b0) & ~(1'b0 == tmp_318_4_fu_15602_p2) & ~(1'b0 == or_cond86_fu_15596_p2)) | (~(tmp_294_4_fu_15554_p2 == 1'b0) & ~(1'b0 == tmp_309_4_fu_15578_p2) & ~(1'b0 == or_cond87_fu_15620_p2)) | (~(1'b0 == tmp_318_4_fu_15602_p2) & ~(1'b0 == or_cond85_fu_15572_p2) & ~(1'b0 == or_cond86_fu_15596_p2)) | (~(1'b0 == tmp_309_4_fu_15578_p2) & ~(1'b0 == or_cond85_fu_15572_p2) & ~(1'b0 == or_cond87_fu_15620_p2)) | (~(tmp_294_4_fu_15554_p2 == 1'b0) & ~(1'b0 == or_cond86_fu_15596_p2) & ~(1'b0 == or_cond87_fu_15620_p2)) | (~(1'b0 == or_cond85_fu_15572_p2) & ~(1'b0 == or_cond86_fu_15596_p2) & ~(1'b0 == or_cond87_fu_15620_p2)))) begin
win_l1_V_load_1_phi_fu_1357_p8 = call_ret_sp_sort_fu_14608_ap_return_21;
end else begin
win_l1_V_load_1_phi_fu_1357_p8 = ap_reg_phiprechg_win_l1_V_load_1_reg_1354pp0_it0;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_294_8_fu_15842_p2) & ~(1'b0 == tmp_309_8_fu_15866_p2) & (1'b0 == tmp_318_8_fu_15890_p2) & (1'b0 == or_cond99_fu_15908_p2)) | (~(1'b0 == tmp_309_8_fu_15866_p2) & (1'b0 == tmp_318_8_fu_15890_p2) & ~(1'b0 == or_cond97_fu_15860_p2) & (1'b0 == or_cond99_fu_15908_p2)) | (~(1'b0 == tmp_294_8_fu_15842_p2) & (1'b0 == tmp_318_8_fu_15890_p2) & ~(1'b0 == or_cond98_fu_15884_p2) & (1'b0 == or_cond99_fu_15908_p2)) | ((1'b0 == tmp_318_8_fu_15890_p2) & ~(1'b0 == or_cond97_fu_15860_p2) & ~(1'b0 == or_cond98_fu_15884_p2) & (1'b0 == or_cond99_fu_15908_p2)))) begin
win_l1_V_load_2_phi_fu_1409_p8 = call_ret_sp_sort_fu_14608_ap_return_36;
end else if (((~(1'b0 == tmp_294_8_fu_15842_p2) & (1'b0 == tmp_309_8_fu_15866_p2) & (1'b0 == or_cond98_fu_15884_p2)) | ((1'b0 == tmp_309_8_fu_15866_p2) & ~(1'b0 == or_cond97_fu_15860_p2) & (1'b0 == or_cond98_fu_15884_p2)))) begin
win_l1_V_load_2_phi_fu_1409_p8 = call_ret_sp_sort_fu_14608_ap_return_35;
end else if (((1'b0 == tmp_294_8_fu_15842_p2) & (1'b0 == or_cond97_fu_15860_p2))) begin
win_l1_V_load_2_phi_fu_1409_p8 = call_ret_sp_sort_fu_14608_ap_return_34;
end else if (((~(1'b0 == tmp_294_8_fu_15842_p2) & ~(1'b0 == tmp_309_8_fu_15866_p2) & ~(1'b0 == tmp_318_8_fu_15890_p2)) | (~(1'b0 == tmp_309_8_fu_15866_p2) & ~(1'b0 == tmp_318_8_fu_15890_p2) & ~(1'b0 == or_cond97_fu_15860_p2)) | (~(1'b0 == tmp_294_8_fu_15842_p2) & ~(1'b0 == tmp_318_8_fu_15890_p2) & ~(1'b0 == or_cond98_fu_15884_p2)) | (~(1'b0 == tmp_294_8_fu_15842_p2) & ~(1'b0 == tmp_309_8_fu_15866_p2) & ~(1'b0 == or_cond99_fu_15908_p2)) | (~(1'b0 == tmp_318_8_fu_15890_p2) & ~(1'b0 == or_cond97_fu_15860_p2) & ~(1'b0 == or_cond98_fu_15884_p2)) | (~(1'b0 == tmp_309_8_fu_15866_p2) & ~(1'b0 == or_cond97_fu_15860_p2) & ~(1'b0 == or_cond99_fu_15908_p2)) | (~(1'b0 == tmp_294_8_fu_15842_p2) & ~(1'b0 == or_cond98_fu_15884_p2) & ~(1'b0 == or_cond99_fu_15908_p2)) | (~(1'b0 == or_cond97_fu_15860_p2) & ~(1'b0 == or_cond98_fu_15884_p2) & ~(1'b0 == or_cond99_fu_15908_p2)))) begin
win_l1_V_load_2_phi_fu_1409_p8 = call_ret_sp_sort_fu_14608_ap_return_37;
end else begin
win_l1_V_load_2_phi_fu_1409_p8 = ap_reg_phiprechg_win_l1_V_load_2_reg_1406pp0_it0;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_294_11_fu_16130_p2) & ~(1'b0 == tmp_309_11_fu_16154_p2) & (1'b0 == tmp_318_11_fu_16178_p2) & (1'b0 == or_cond111_fu_16196_p2)) | (~(1'b0 == tmp_309_11_fu_16154_p2) & (1'b0 == tmp_318_11_fu_16178_p2) & ~(1'b0 == or_cond109_fu_16148_p2) & (1'b0 == or_cond111_fu_16196_p2)) | (~(1'b0 == tmp_294_11_fu_16130_p2) & (1'b0 == tmp_318_11_fu_16178_p2) & ~(1'b0 == or_cond110_fu_16172_p2) & (1'b0 == or_cond111_fu_16196_p2)) | ((1'b0 == tmp_318_11_fu_16178_p2) & ~(1'b0 == or_cond109_fu_16148_p2) & ~(1'b0 == or_cond110_fu_16172_p2) & (1'b0 == or_cond111_fu_16196_p2)))) begin
win_l1_V_load_3_phi_fu_1461_p8 = call_ret_sp_sort_fu_14608_ap_return_52;
end else if (((~(1'b0 == tmp_294_11_fu_16130_p2) & (1'b0 == tmp_309_11_fu_16154_p2) & (1'b0 == or_cond110_fu_16172_p2)) | ((1'b0 == tmp_309_11_fu_16154_p2) & ~(1'b0 == or_cond109_fu_16148_p2) & (1'b0 == or_cond110_fu_16172_p2)))) begin
win_l1_V_load_3_phi_fu_1461_p8 = call_ret_sp_sort_fu_14608_ap_return_51;
end else if (((1'b0 == tmp_294_11_fu_16130_p2) & (1'b0 == or_cond109_fu_16148_p2))) begin
win_l1_V_load_3_phi_fu_1461_p8 = call_ret_sp_sort_fu_14608_ap_return_50;
end else if (((~(1'b0 == tmp_294_11_fu_16130_p2) & ~(1'b0 == tmp_309_11_fu_16154_p2) & ~(1'b0 == tmp_318_11_fu_16178_p2)) | (~(1'b0 == tmp_309_11_fu_16154_p2) & ~(1'b0 == tmp_318_11_fu_16178_p2) & ~(1'b0 == or_cond109_fu_16148_p2)) | (~(1'b0 == tmp_294_11_fu_16130_p2) & ~(1'b0 == tmp_318_11_fu_16178_p2) & ~(1'b0 == or_cond110_fu_16172_p2)) | (~(1'b0 == tmp_294_11_fu_16130_p2) & ~(1'b0 == tmp_309_11_fu_16154_p2) & ~(1'b0 == or_cond111_fu_16196_p2)) | (~(1'b0 == tmp_318_11_fu_16178_p2) & ~(1'b0 == or_cond109_fu_16148_p2) & ~(1'b0 == or_cond110_fu_16172_p2)) | (~(1'b0 == tmp_309_11_fu_16154_p2) & ~(1'b0 == or_cond109_fu_16148_p2) & ~(1'b0 == or_cond111_fu_16196_p2)) | (~(1'b0 == tmp_294_11_fu_16130_p2) & ~(1'b0 == or_cond110_fu_16172_p2) & ~(1'b0 == or_cond111_fu_16196_p2)) | (~(1'b0 == or_cond109_fu_16148_p2) & ~(1'b0 == or_cond110_fu_16172_p2) & ~(1'b0 == or_cond111_fu_16196_p2)))) begin
win_l1_V_load_3_phi_fu_1461_p8 = call_ret_sp_sort_fu_14608_ap_return_53;
end else begin
win_l1_V_load_3_phi_fu_1461_p8 = ap_reg_phiprechg_win_l1_V_load_3_reg_1458pp0_it0;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_294_5_fu_15626_p2) & ~(1'b0 == tmp_309_5_fu_15650_p2) & (1'b0 == tmp_318_5_fu_15674_p2) & (1'b0 == or_cond90_fu_15692_p2)) | (~(1'b0 == tmp_309_5_fu_15650_p2) & (1'b0 == tmp_318_5_fu_15674_p2) & ~(1'b0 == or_cond88_fu_15644_p2) & (1'b0 == or_cond90_fu_15692_p2)) | (~(1'b0 == tmp_294_5_fu_15626_p2) & (1'b0 == tmp_318_5_fu_15674_p2) & ~(1'b0 == or_cond89_fu_15668_p2) & (1'b0 == or_cond90_fu_15692_p2)) | ((1'b0 == tmp_318_5_fu_15674_p2) & ~(1'b0 == or_cond88_fu_15644_p2) & ~(1'b0 == or_cond89_fu_15668_p2) & (1'b0 == or_cond90_fu_15692_p2)))) begin
win_l1_V_load_4_1_phi_fu_1370_p8 = call_ret_sp_sort_fu_14608_ap_return_24;
end else if (((~(1'b0 == tmp_294_5_fu_15626_p2) & (1'b0 == tmp_309_5_fu_15650_p2) & (1'b0 == or_cond89_fu_15668_p2)) | ((1'b0 == tmp_309_5_fu_15650_p2) & ~(1'b0 == or_cond88_fu_15644_p2) & (1'b0 == or_cond89_fu_15668_p2)))) begin
win_l1_V_load_4_1_phi_fu_1370_p8 = call_ret_sp_sort_fu_14608_ap_return_23;
end else if (((1'b0 == tmp_294_5_fu_15626_p2) & (1'b0 == or_cond88_fu_15644_p2))) begin
win_l1_V_load_4_1_phi_fu_1370_p8 = call_ret_sp_sort_fu_14608_ap_return_22;
end else if (((~(1'b0 == tmp_294_5_fu_15626_p2) & ~(1'b0 == tmp_309_5_fu_15650_p2) & ~(1'b0 == tmp_318_5_fu_15674_p2)) | (~(1'b0 == tmp_309_5_fu_15650_p2) & ~(1'b0 == tmp_318_5_fu_15674_p2) & ~(1'b0 == or_cond88_fu_15644_p2)) | (~(1'b0 == tmp_294_5_fu_15626_p2) & ~(1'b0 == tmp_318_5_fu_15674_p2) & ~(1'b0 == or_cond89_fu_15668_p2)) | (~(1'b0 == tmp_294_5_fu_15626_p2) & ~(1'b0 == tmp_309_5_fu_15650_p2) & ~(1'b0 == or_cond90_fu_15692_p2)) | (~(1'b0 == tmp_318_5_fu_15674_p2) & ~(1'b0 == or_cond88_fu_15644_p2) & ~(1'b0 == or_cond89_fu_15668_p2)) | (~(1'b0 == tmp_309_5_fu_15650_p2) & ~(1'b0 == or_cond88_fu_15644_p2) & ~(1'b0 == or_cond90_fu_15692_p2)) | (~(1'b0 == tmp_294_5_fu_15626_p2) & ~(1'b0 == or_cond89_fu_15668_p2) & ~(1'b0 == or_cond90_fu_15692_p2)) | (~(1'b0 == or_cond88_fu_15644_p2) & ~(1'b0 == or_cond89_fu_15668_p2) & ~(1'b0 == or_cond90_fu_15692_p2)))) begin
win_l1_V_load_4_1_phi_fu_1370_p8 = call_ret_sp_sort_fu_14608_ap_return_25;
end else begin
win_l1_V_load_4_1_phi_fu_1370_p8 = ap_reg_phiprechg_win_l1_V_load_4_1_reg_1367pp0_it0;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_294_9_fu_15914_p2) & ~(1'b0 == tmp_309_9_fu_15938_p2) & (1'b0 == tmp_318_9_fu_15962_p2) & (1'b0 == or_cond102_fu_15980_p2)) | (~(1'b0 == tmp_309_9_fu_15938_p2) & (1'b0 == tmp_318_9_fu_15962_p2) & ~(1'b0 == or_cond100_fu_15932_p2) & (1'b0 == or_cond102_fu_15980_p2)) | (~(1'b0 == tmp_294_9_fu_15914_p2) & (1'b0 == tmp_318_9_fu_15962_p2) & ~(1'b0 == or_cond101_fu_15956_p2) & (1'b0 == or_cond102_fu_15980_p2)) | ((1'b0 == tmp_318_9_fu_15962_p2) & ~(1'b0 == or_cond100_fu_15932_p2) & ~(1'b0 == or_cond101_fu_15956_p2) & (1'b0 == or_cond102_fu_15980_p2)))) begin
win_l1_V_load_4_2_phi_fu_1422_p8 = call_ret_sp_sort_fu_14608_ap_return_40;
end else if (((~(1'b0 == tmp_294_9_fu_15914_p2) & (1'b0 == tmp_309_9_fu_15938_p2) & (1'b0 == or_cond101_fu_15956_p2)) | ((1'b0 == tmp_309_9_fu_15938_p2) & ~(1'b0 == or_cond100_fu_15932_p2) & (1'b0 == or_cond101_fu_15956_p2)))) begin
win_l1_V_load_4_2_phi_fu_1422_p8 = call_ret_sp_sort_fu_14608_ap_return_39;
end else if (((1'b0 == tmp_294_9_fu_15914_p2) & (1'b0 == or_cond100_fu_15932_p2))) begin
win_l1_V_load_4_2_phi_fu_1422_p8 = call_ret_sp_sort_fu_14608_ap_return_38;
end else if (((~(1'b0 == tmp_294_9_fu_15914_p2) & ~(1'b0 == tmp_309_9_fu_15938_p2) & ~(1'b0 == tmp_318_9_fu_15962_p2)) | (~(1'b0 == tmp_309_9_fu_15938_p2) & ~(1'b0 == tmp_318_9_fu_15962_p2) & ~(1'b0 == or_cond100_fu_15932_p2)) | (~(1'b0 == tmp_294_9_fu_15914_p2) & ~(1'b0 == tmp_318_9_fu_15962_p2) & ~(1'b0 == or_cond101_fu_15956_p2)) | (~(1'b0 == tmp_294_9_fu_15914_p2) & ~(1'b0 == tmp_309_9_fu_15938_p2) & ~(1'b0 == or_cond102_fu_15980_p2)) | (~(1'b0 == tmp_318_9_fu_15962_p2) & ~(1'b0 == or_cond100_fu_15932_p2) & ~(1'b0 == or_cond101_fu_15956_p2)) | (~(1'b0 == tmp_309_9_fu_15938_p2) & ~(1'b0 == or_cond100_fu_15932_p2) & ~(1'b0 == or_cond102_fu_15980_p2)) | (~(1'b0 == tmp_294_9_fu_15914_p2) & ~(1'b0 == or_cond101_fu_15956_p2) & ~(1'b0 == or_cond102_fu_15980_p2)) | (~(1'b0 == or_cond100_fu_15932_p2) & ~(1'b0 == or_cond101_fu_15956_p2) & ~(1'b0 == or_cond102_fu_15980_p2)))) begin
win_l1_V_load_4_2_phi_fu_1422_p8 = call_ret_sp_sort_fu_14608_ap_return_41;
end else begin
win_l1_V_load_4_2_phi_fu_1422_p8 = ap_reg_phiprechg_win_l1_V_load_4_2_reg_1419pp0_it0;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_294_12_fu_16202_p2) & ~(1'b0 == tmp_309_12_fu_16226_p2) & (1'b0 == tmp_318_12_fu_16250_p2) & (1'b0 == or_cond114_fu_16268_p2)) | (~(1'b0 == tmp_309_12_fu_16226_p2) & (1'b0 == tmp_318_12_fu_16250_p2) & ~(1'b0 == or_cond112_fu_16220_p2) & (1'b0 == or_cond114_fu_16268_p2)) | (~(1'b0 == tmp_294_12_fu_16202_p2) & (1'b0 == tmp_318_12_fu_16250_p2) & ~(1'b0 == or_cond113_fu_16244_p2) & (1'b0 == or_cond114_fu_16268_p2)) | ((1'b0 == tmp_318_12_fu_16250_p2) & ~(1'b0 == or_cond112_fu_16220_p2) & ~(1'b0 == or_cond113_fu_16244_p2) & (1'b0 == or_cond114_fu_16268_p2)))) begin
win_l1_V_load_4_3_phi_fu_1474_p8 = call_ret_sp_sort_fu_14608_ap_return_56;
end else if (((~(1'b0 == tmp_294_12_fu_16202_p2) & (1'b0 == tmp_309_12_fu_16226_p2) & (1'b0 == or_cond113_fu_16244_p2)) | ((1'b0 == tmp_309_12_fu_16226_p2) & ~(1'b0 == or_cond112_fu_16220_p2) & (1'b0 == or_cond113_fu_16244_p2)))) begin
win_l1_V_load_4_3_phi_fu_1474_p8 = call_ret_sp_sort_fu_14608_ap_return_55;
end else if (((1'b0 == tmp_294_12_fu_16202_p2) & (1'b0 == or_cond112_fu_16220_p2))) begin
win_l1_V_load_4_3_phi_fu_1474_p8 = call_ret_sp_sort_fu_14608_ap_return_54;
end else if (((~(1'b0 == tmp_294_12_fu_16202_p2) & ~(1'b0 == tmp_309_12_fu_16226_p2) & ~(1'b0 == tmp_318_12_fu_16250_p2)) | (~(1'b0 == tmp_309_12_fu_16226_p2) & ~(1'b0 == tmp_318_12_fu_16250_p2) & ~(1'b0 == or_cond112_fu_16220_p2)) | (~(1'b0 == tmp_294_12_fu_16202_p2) & ~(1'b0 == tmp_318_12_fu_16250_p2) & ~(1'b0 == or_cond113_fu_16244_p2)) | (~(1'b0 == tmp_294_12_fu_16202_p2) & ~(1'b0 == tmp_309_12_fu_16226_p2) & ~(1'b0 == or_cond114_fu_16268_p2)) | (~(1'b0 == tmp_318_12_fu_16250_p2) & ~(1'b0 == or_cond112_fu_16220_p2) & ~(1'b0 == or_cond113_fu_16244_p2)) | (~(1'b0 == tmp_309_12_fu_16226_p2) & ~(1'b0 == or_cond112_fu_16220_p2) & ~(1'b0 == or_cond114_fu_16268_p2)) | (~(1'b0 == tmp_294_12_fu_16202_p2) & ~(1'b0 == or_cond113_fu_16244_p2) & ~(1'b0 == or_cond114_fu_16268_p2)) | (~(1'b0 == or_cond112_fu_16220_p2) & ~(1'b0 == or_cond113_fu_16244_p2) & ~(1'b0 == or_cond114_fu_16268_p2)))) begin
win_l1_V_load_4_3_phi_fu_1474_p8 = call_ret_sp_sort_fu_14608_ap_return_57;
end else begin
win_l1_V_load_4_3_phi_fu_1474_p8 = ap_reg_phiprechg_win_l1_V_load_4_3_reg_1471pp0_it0;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_294_6_fu_15698_p2) & ~(1'b0 == tmp_309_6_fu_15722_p2) & (1'b0 == tmp_318_6_fu_15746_p2) & (1'b0 == or_cond93_fu_15764_p2)) | (~(1'b0 == tmp_309_6_fu_15722_p2) & (1'b0 == tmp_318_6_fu_15746_p2) & ~(1'b0 == or_cond91_fu_15716_p2) & (1'b0 == or_cond93_fu_15764_p2)) | (~(1'b0 == tmp_294_6_fu_15698_p2) & (1'b0 == tmp_318_6_fu_15746_p2) & ~(1'b0 == or_cond92_fu_15740_p2) & (1'b0 == or_cond93_fu_15764_p2)) | ((1'b0 == tmp_318_6_fu_15746_p2) & ~(1'b0 == or_cond91_fu_15716_p2) & ~(1'b0 == or_cond92_fu_15740_p2) & (1'b0 == or_cond93_fu_15764_p2)))) begin
win_l1_V_load_5_1_phi_fu_1383_p8 = call_ret_sp_sort_fu_14608_ap_return_28;
end else if (((~(1'b0 == tmp_294_6_fu_15698_p2) & (1'b0 == tmp_309_6_fu_15722_p2) & (1'b0 == or_cond92_fu_15740_p2)) | ((1'b0 == tmp_309_6_fu_15722_p2) & ~(1'b0 == or_cond91_fu_15716_p2) & (1'b0 == or_cond92_fu_15740_p2)))) begin
win_l1_V_load_5_1_phi_fu_1383_p8 = call_ret_sp_sort_fu_14608_ap_return_27;
end else if (((1'b0 == tmp_294_6_fu_15698_p2) & (1'b0 == or_cond91_fu_15716_p2))) begin
win_l1_V_load_5_1_phi_fu_1383_p8 = call_ret_sp_sort_fu_14608_ap_return_26;
end else if (((~(1'b0 == tmp_294_6_fu_15698_p2) & ~(1'b0 == tmp_309_6_fu_15722_p2) & ~(1'b0 == tmp_318_6_fu_15746_p2)) | (~(1'b0 == tmp_309_6_fu_15722_p2) & ~(1'b0 == tmp_318_6_fu_15746_p2) & ~(1'b0 == or_cond91_fu_15716_p2)) | (~(1'b0 == tmp_294_6_fu_15698_p2) & ~(1'b0 == tmp_318_6_fu_15746_p2) & ~(1'b0 == or_cond92_fu_15740_p2)) | (~(1'b0 == tmp_294_6_fu_15698_p2) & ~(1'b0 == tmp_309_6_fu_15722_p2) & ~(1'b0 == or_cond93_fu_15764_p2)) | (~(1'b0 == tmp_318_6_fu_15746_p2) & ~(1'b0 == or_cond91_fu_15716_p2) & ~(1'b0 == or_cond92_fu_15740_p2)) | (~(1'b0 == tmp_309_6_fu_15722_p2) & ~(1'b0 == or_cond91_fu_15716_p2) & ~(1'b0 == or_cond93_fu_15764_p2)) | (~(1'b0 == tmp_294_6_fu_15698_p2) & ~(1'b0 == or_cond92_fu_15740_p2) & ~(1'b0 == or_cond93_fu_15764_p2)) | (~(1'b0 == or_cond91_fu_15716_p2) & ~(1'b0 == or_cond92_fu_15740_p2) & ~(1'b0 == or_cond93_fu_15764_p2)))) begin
win_l1_V_load_5_1_phi_fu_1383_p8 = call_ret_sp_sort_fu_14608_ap_return_29;
end else begin
win_l1_V_load_5_1_phi_fu_1383_p8 = ap_reg_phiprechg_win_l1_V_load_5_1_reg_1380pp0_it0;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_294_s_fu_15986_p2) & ~(1'b0 == tmp_309_s_fu_16010_p2) & (1'b0 == tmp_318_s_fu_16034_p2) & (1'b0 == or_cond105_fu_16052_p2)) | (~(1'b0 == tmp_309_s_fu_16010_p2) & (1'b0 == tmp_318_s_fu_16034_p2) & ~(1'b0 == or_cond103_fu_16004_p2) & (1'b0 == or_cond105_fu_16052_p2)) | (~(1'b0 == tmp_294_s_fu_15986_p2) & (1'b0 == tmp_318_s_fu_16034_p2) & ~(1'b0 == or_cond104_fu_16028_p2) & (1'b0 == or_cond105_fu_16052_p2)) | ((1'b0 == tmp_318_s_fu_16034_p2) & ~(1'b0 == or_cond103_fu_16004_p2) & ~(1'b0 == or_cond104_fu_16028_p2) & (1'b0 == or_cond105_fu_16052_p2)))) begin
win_l1_V_load_5_2_phi_fu_1435_p8 = call_ret_sp_sort_fu_14608_ap_return_44;
end else if (((~(1'b0 == tmp_294_s_fu_15986_p2) & (1'b0 == tmp_309_s_fu_16010_p2) & (1'b0 == or_cond104_fu_16028_p2)) | ((1'b0 == tmp_309_s_fu_16010_p2) & ~(1'b0 == or_cond103_fu_16004_p2) & (1'b0 == or_cond104_fu_16028_p2)))) begin
win_l1_V_load_5_2_phi_fu_1435_p8 = call_ret_sp_sort_fu_14608_ap_return_43;
end else if (((1'b0 == tmp_294_s_fu_15986_p2) & (1'b0 == or_cond103_fu_16004_p2))) begin
win_l1_V_load_5_2_phi_fu_1435_p8 = call_ret_sp_sort_fu_14608_ap_return_42;
end else if (((~(1'b0 == tmp_294_s_fu_15986_p2) & ~(1'b0 == tmp_309_s_fu_16010_p2) & ~(1'b0 == tmp_318_s_fu_16034_p2)) | (~(1'b0 == tmp_309_s_fu_16010_p2) & ~(1'b0 == tmp_318_s_fu_16034_p2) & ~(1'b0 == or_cond103_fu_16004_p2)) | (~(1'b0 == tmp_294_s_fu_15986_p2) & ~(1'b0 == tmp_318_s_fu_16034_p2) & ~(1'b0 == or_cond104_fu_16028_p2)) | (~(1'b0 == tmp_294_s_fu_15986_p2) & ~(1'b0 == tmp_309_s_fu_16010_p2) & ~(1'b0 == or_cond105_fu_16052_p2)) | (~(1'b0 == tmp_318_s_fu_16034_p2) & ~(1'b0 == or_cond103_fu_16004_p2) & ~(1'b0 == or_cond104_fu_16028_p2)) | (~(1'b0 == tmp_309_s_fu_16010_p2) & ~(1'b0 == or_cond103_fu_16004_p2) & ~(1'b0 == or_cond105_fu_16052_p2)) | (~(1'b0 == tmp_294_s_fu_15986_p2) & ~(1'b0 == or_cond104_fu_16028_p2) & ~(1'b0 == or_cond105_fu_16052_p2)) | (~(1'b0 == or_cond103_fu_16004_p2) & ~(1'b0 == or_cond104_fu_16028_p2) & ~(1'b0 == or_cond105_fu_16052_p2)))) begin
win_l1_V_load_5_2_phi_fu_1435_p8 = call_ret_sp_sort_fu_14608_ap_return_45;
end else begin
win_l1_V_load_5_2_phi_fu_1435_p8 = ap_reg_phiprechg_win_l1_V_load_5_2_reg_1432pp0_it0;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_294_13_fu_16274_p2) & ~(1'b0 == tmp_309_13_fu_16298_p2) & (1'b0 == tmp_318_13_fu_16322_p2) & (1'b0 == or_cond117_fu_16340_p2)) | (~(1'b0 == tmp_309_13_fu_16298_p2) & (1'b0 == tmp_318_13_fu_16322_p2) & ~(1'b0 == or_cond115_fu_16292_p2) & (1'b0 == or_cond117_fu_16340_p2)) | (~(1'b0 == tmp_294_13_fu_16274_p2) & (1'b0 == tmp_318_13_fu_16322_p2) & ~(1'b0 == or_cond116_fu_16316_p2) & (1'b0 == or_cond117_fu_16340_p2)) | ((1'b0 == tmp_318_13_fu_16322_p2) & ~(1'b0 == or_cond115_fu_16292_p2) & ~(1'b0 == or_cond116_fu_16316_p2) & (1'b0 == or_cond117_fu_16340_p2)))) begin
win_l1_V_load_5_3_phi_fu_1487_p8 = call_ret_sp_sort_fu_14608_ap_return_60;
end else if (((~(1'b0 == tmp_294_13_fu_16274_p2) & (1'b0 == tmp_309_13_fu_16298_p2) & (1'b0 == or_cond116_fu_16316_p2)) | ((1'b0 == tmp_309_13_fu_16298_p2) & ~(1'b0 == or_cond115_fu_16292_p2) & (1'b0 == or_cond116_fu_16316_p2)))) begin
win_l1_V_load_5_3_phi_fu_1487_p8 = call_ret_sp_sort_fu_14608_ap_return_59;
end else if (((1'b0 == tmp_294_13_fu_16274_p2) & (1'b0 == or_cond115_fu_16292_p2))) begin
win_l1_V_load_5_3_phi_fu_1487_p8 = call_ret_sp_sort_fu_14608_ap_return_58;
end else if (((~(1'b0 == tmp_294_13_fu_16274_p2) & ~(1'b0 == tmp_309_13_fu_16298_p2) & ~(1'b0 == tmp_318_13_fu_16322_p2)) | (~(1'b0 == tmp_309_13_fu_16298_p2) & ~(1'b0 == tmp_318_13_fu_16322_p2) & ~(1'b0 == or_cond115_fu_16292_p2)) | (~(1'b0 == tmp_294_13_fu_16274_p2) & ~(1'b0 == tmp_318_13_fu_16322_p2) & ~(1'b0 == or_cond116_fu_16316_p2)) | (~(1'b0 == tmp_294_13_fu_16274_p2) & ~(1'b0 == tmp_309_13_fu_16298_p2) & ~(1'b0 == or_cond117_fu_16340_p2)) | (~(1'b0 == tmp_318_13_fu_16322_p2) & ~(1'b0 == or_cond115_fu_16292_p2) & ~(1'b0 == or_cond116_fu_16316_p2)) | (~(1'b0 == tmp_309_13_fu_16298_p2) & ~(1'b0 == or_cond115_fu_16292_p2) & ~(1'b0 == or_cond117_fu_16340_p2)) | (~(1'b0 == tmp_294_13_fu_16274_p2) & ~(1'b0 == or_cond116_fu_16316_p2) & ~(1'b0 == or_cond117_fu_16340_p2)) | (~(1'b0 == or_cond115_fu_16292_p2) & ~(1'b0 == or_cond116_fu_16316_p2) & ~(1'b0 == or_cond117_fu_16340_p2)))) begin
win_l1_V_load_5_3_phi_fu_1487_p8 = call_ret_sp_sort_fu_14608_ap_return_61;
end else begin
win_l1_V_load_5_3_phi_fu_1487_p8 = ap_reg_phiprechg_win_l1_V_load_5_3_reg_1484pp0_it0;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_294_7_fu_15770_p2) & ~(1'b0 == tmp_309_7_fu_15794_p2) & (1'b0 == tmp_318_7_fu_15818_p2) & (1'b0 == or_cond96_fu_15836_p2)) | (~(1'b0 == tmp_309_7_fu_15794_p2) & (1'b0 == tmp_318_7_fu_15818_p2) & ~(1'b0 == or_cond94_fu_15788_p2) & (1'b0 == or_cond96_fu_15836_p2)) | (~(1'b0 == tmp_294_7_fu_15770_p2) & (1'b0 == tmp_318_7_fu_15818_p2) & ~(1'b0 == or_cond95_fu_15812_p2) & (1'b0 == or_cond96_fu_15836_p2)) | ((1'b0 == tmp_318_7_fu_15818_p2) & ~(1'b0 == or_cond94_fu_15788_p2) & ~(1'b0 == or_cond95_fu_15812_p2) & (1'b0 == or_cond96_fu_15836_p2)))) begin
win_l1_V_load_6_1_phi_fu_1396_p8 = call_ret_sp_sort_fu_14608_ap_return_32;
end else if (((~(1'b0 == tmp_294_7_fu_15770_p2) & (1'b0 == tmp_309_7_fu_15794_p2) & (1'b0 == or_cond95_fu_15812_p2)) | ((1'b0 == tmp_309_7_fu_15794_p2) & ~(1'b0 == or_cond94_fu_15788_p2) & (1'b0 == or_cond95_fu_15812_p2)))) begin
win_l1_V_load_6_1_phi_fu_1396_p8 = call_ret_sp_sort_fu_14608_ap_return_31;
end else if (((1'b0 == tmp_294_7_fu_15770_p2) & (1'b0 == or_cond94_fu_15788_p2))) begin
win_l1_V_load_6_1_phi_fu_1396_p8 = call_ret_sp_sort_fu_14608_ap_return_30;
end else if (((~(1'b0 == tmp_294_7_fu_15770_p2) & ~(1'b0 == tmp_309_7_fu_15794_p2) & ~(1'b0 == tmp_318_7_fu_15818_p2)) | (~(1'b0 == tmp_309_7_fu_15794_p2) & ~(1'b0 == tmp_318_7_fu_15818_p2) & ~(1'b0 == or_cond94_fu_15788_p2)) | (~(1'b0 == tmp_294_7_fu_15770_p2) & ~(1'b0 == tmp_318_7_fu_15818_p2) & ~(1'b0 == or_cond95_fu_15812_p2)) | (~(1'b0 == tmp_294_7_fu_15770_p2) & ~(1'b0 == tmp_309_7_fu_15794_p2) & ~(1'b0 == or_cond96_fu_15836_p2)) | (~(1'b0 == tmp_318_7_fu_15818_p2) & ~(1'b0 == or_cond94_fu_15788_p2) & ~(1'b0 == or_cond95_fu_15812_p2)) | (~(1'b0 == tmp_309_7_fu_15794_p2) & ~(1'b0 == or_cond94_fu_15788_p2) & ~(1'b0 == or_cond96_fu_15836_p2)) | (~(1'b0 == tmp_294_7_fu_15770_p2) & ~(1'b0 == or_cond95_fu_15812_p2) & ~(1'b0 == or_cond96_fu_15836_p2)) | (~(1'b0 == or_cond94_fu_15788_p2) & ~(1'b0 == or_cond95_fu_15812_p2) & ~(1'b0 == or_cond96_fu_15836_p2)))) begin
win_l1_V_load_6_1_phi_fu_1396_p8 = call_ret_sp_sort_fu_14608_ap_return_33;
end else begin
win_l1_V_load_6_1_phi_fu_1396_p8 = ap_reg_phiprechg_win_l1_V_load_6_1_reg_1393pp0_it0;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_294_10_fu_16058_p2) & ~(1'b0 == tmp_309_10_fu_16082_p2) & (1'b0 == tmp_318_10_fu_16106_p2) & (1'b0 == or_cond108_fu_16124_p2)) | (~(1'b0 == tmp_309_10_fu_16082_p2) & (1'b0 == tmp_318_10_fu_16106_p2) & ~(1'b0 == or_cond106_fu_16076_p2) & (1'b0 == or_cond108_fu_16124_p2)) | (~(1'b0 == tmp_294_10_fu_16058_p2) & (1'b0 == tmp_318_10_fu_16106_p2) & ~(1'b0 == or_cond107_fu_16100_p2) & (1'b0 == or_cond108_fu_16124_p2)) | ((1'b0 == tmp_318_10_fu_16106_p2) & ~(1'b0 == or_cond106_fu_16076_p2) & ~(1'b0 == or_cond107_fu_16100_p2) & (1'b0 == or_cond108_fu_16124_p2)))) begin
win_l1_V_load_6_2_phi_fu_1448_p8 = call_ret_sp_sort_fu_14608_ap_return_48;
end else if (((~(1'b0 == tmp_294_10_fu_16058_p2) & (1'b0 == tmp_309_10_fu_16082_p2) & (1'b0 == or_cond107_fu_16100_p2)) | ((1'b0 == tmp_309_10_fu_16082_p2) & ~(1'b0 == or_cond106_fu_16076_p2) & (1'b0 == or_cond107_fu_16100_p2)))) begin
win_l1_V_load_6_2_phi_fu_1448_p8 = call_ret_sp_sort_fu_14608_ap_return_47;
end else if (((1'b0 == tmp_294_10_fu_16058_p2) & (1'b0 == or_cond106_fu_16076_p2))) begin
win_l1_V_load_6_2_phi_fu_1448_p8 = call_ret_sp_sort_fu_14608_ap_return_46;
end else if (((~(1'b0 == tmp_294_10_fu_16058_p2) & ~(1'b0 == tmp_309_10_fu_16082_p2) & ~(1'b0 == tmp_318_10_fu_16106_p2)) | (~(1'b0 == tmp_309_10_fu_16082_p2) & ~(1'b0 == tmp_318_10_fu_16106_p2) & ~(1'b0 == or_cond106_fu_16076_p2)) | (~(1'b0 == tmp_294_10_fu_16058_p2) & ~(1'b0 == tmp_318_10_fu_16106_p2) & ~(1'b0 == or_cond107_fu_16100_p2)) | (~(1'b0 == tmp_294_10_fu_16058_p2) & ~(1'b0 == tmp_309_10_fu_16082_p2) & ~(1'b0 == or_cond108_fu_16124_p2)) | (~(1'b0 == tmp_318_10_fu_16106_p2) & ~(1'b0 == or_cond106_fu_16076_p2) & ~(1'b0 == or_cond107_fu_16100_p2)) | (~(1'b0 == tmp_309_10_fu_16082_p2) & ~(1'b0 == or_cond106_fu_16076_p2) & ~(1'b0 == or_cond108_fu_16124_p2)) | (~(1'b0 == tmp_294_10_fu_16058_p2) & ~(1'b0 == or_cond107_fu_16100_p2) & ~(1'b0 == or_cond108_fu_16124_p2)) | (~(1'b0 == or_cond106_fu_16076_p2) & ~(1'b0 == or_cond107_fu_16100_p2) & ~(1'b0 == or_cond108_fu_16124_p2)))) begin
win_l1_V_load_6_2_phi_fu_1448_p8 = call_ret_sp_sort_fu_14608_ap_return_49;
end else begin
win_l1_V_load_6_2_phi_fu_1448_p8 = ap_reg_phiprechg_win_l1_V_load_6_2_reg_1445pp0_it0;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_235_fu_18579_p2) & ~(1'b0 == tmp_238_fu_18603_p2) & (1'b0 == tmp_241_fu_18627_p2) & (1'b0 == or_cond69_fu_18645_p2)) | (~(1'b0 == tmp_238_fu_18603_p2) & (1'b0 == tmp_241_fu_18627_p2) & ~(1'b0 == or_cond67_fu_18597_p2) & (1'b0 == or_cond69_fu_18645_p2)) | (~(1'b0 == tmp_235_fu_18579_p2) & (1'b0 == tmp_241_fu_18627_p2) & ~(1'b0 == or_cond68_fu_18621_p2) & (1'b0 == or_cond69_fu_18645_p2)) | ((1'b0 == tmp_241_fu_18627_p2) & ~(1'b0 == or_cond67_fu_18597_p2) & ~(1'b0 == or_cond68_fu_18621_p2) & (1'b0 == or_cond69_fu_18645_p2)))) begin
win_l2_V_1_load_phi_fu_14441_p8 = win_l1_V_1_load_2_phi_fu_12164_p8;
end else if (((~(1'b0 == tmp_235_fu_18579_p2) & (1'b0 == tmp_238_fu_18603_p2) & (1'b0 == or_cond68_fu_18621_p2)) | ((1'b0 == tmp_238_fu_18603_p2) & ~(1'b0 == or_cond67_fu_18597_p2) & (1'b0 == or_cond68_fu_18621_p2)))) begin
win_l2_V_1_load_phi_fu_14441_p8 = win_l1_V_1_load_1_phi_fu_12110_p8;
end else if (((1'b0 == tmp_235_fu_18579_p2) & (1'b0 == or_cond67_fu_18597_p2))) begin
win_l2_V_1_load_phi_fu_14441_p8 = win_l1_V_1_load_phi_fu_12056_p8;
end else if (((~(1'b0 == tmp_235_fu_18579_p2) & ~(1'b0 == tmp_238_fu_18603_p2) & ~(1'b0 == tmp_241_fu_18627_p2)) | (~(1'b0 == tmp_238_fu_18603_p2) & ~(1'b0 == tmp_241_fu_18627_p2) & ~(1'b0 == or_cond67_fu_18597_p2)) | (~(1'b0 == tmp_235_fu_18579_p2) & ~(1'b0 == tmp_241_fu_18627_p2) & ~(1'b0 == or_cond68_fu_18621_p2)) | (~(1'b0 == tmp_235_fu_18579_p2) & ~(1'b0 == tmp_238_fu_18603_p2) & ~(1'b0 == or_cond69_fu_18645_p2)) | (~(1'b0 == tmp_241_fu_18627_p2) & ~(1'b0 == or_cond67_fu_18597_p2) & ~(1'b0 == or_cond68_fu_18621_p2)) | (~(1'b0 == tmp_238_fu_18603_p2) & ~(1'b0 == or_cond67_fu_18597_p2) & ~(1'b0 == or_cond69_fu_18645_p2)) | (~(1'b0 == tmp_235_fu_18579_p2) & ~(1'b0 == or_cond68_fu_18621_p2) & ~(1'b0 == or_cond69_fu_18645_p2)) | (~(1'b0 == or_cond67_fu_18597_p2) & ~(1'b0 == or_cond68_fu_18621_p2) & ~(1'b0 == or_cond69_fu_18645_p2)))) begin
win_l2_V_1_load_phi_fu_14441_p8 = win_l1_V_1_load_3_phi_fu_12218_p8;
end else begin
win_l2_V_1_load_phi_fu_14441_p8 = ap_reg_phiprechg_win_l2_V_1_load_reg_14438pp0_it1;
end
end
always @ (*) begin
if (((~(1'b0 == tmp_217_fu_16910_p2) & ~(1'b0 == tmp_220_fu_16931_p2) & (1'b0 == tmp_223_fu_16954_p2) & (1'b0 == or_cond51_fu_16971_p2)) | (~(1'b0 == tmp_220_fu_16931_p2) & (1'b0 == tmp_223_fu_16954_p2) & ~(1'b0 == or_cond_85_fu_16925_p2) & (1'b0 == or_cond51_fu_16971_p2)) | (~(1'b0 == tmp_217_fu_16910_p2) & (1'b0 == tmp_223_fu_16954_p2) & ~(1'b0 == or_cond50_fu_16948_p2) & (1'b0 == or_cond51_fu_16971_p2)) | ((1'b0 == tmp_223_fu_16954_p2) & ~(1'b0 == or_cond_85_fu_16925_p2) & ~(1'b0 == or_cond50_fu_16948_p2) & (1'b0 == or_cond51_fu_16971_p2)))) begin
win_l2_V_load_phi_fu_3713_p8 = ap_reg_phiprechg_win_l1_V_load_5_reg_1576pp0_it1;
end else if (((~(1'b0 == tmp_217_fu_16910_p2) & (1'b0 == tmp_220_fu_16931_p2) & (1'b0 == or_cond50_fu_16948_p2)) | ((1'b0 == tmp_220_fu_16931_p2) & ~(1'b0 == or_cond_85_fu_16925_p2) & (1'b0 == or_cond50_fu_16948_p2)))) begin
win_l2_V_load_phi_fu_3713_p8 = ap_reg_phiprechg_win_l1_V_load_4_reg_1522pp0_it1;
end else if (((1'b0 == tmp_217_fu_16910_p2) & (1'b0 == or_cond_85_fu_16925_p2))) begin
win_l2_V_load_phi_fu_3713_p8 = win_l1_V_load_reg_24078;
end else if (((~(1'b0 == tmp_217_fu_16910_p2) & ~(1'b0 == tmp_220_fu_16931_p2) & ~(1'b0 == tmp_223_fu_16954_p2)) | (~(1'b0 == tmp_220_fu_16931_p2) & ~(1'b0 == tmp_223_fu_16954_p2) & ~(1'b0 == or_cond_85_fu_16925_p2)) | (~(1'b0 == tmp_217_fu_16910_p2) & ~(1'b0 == tmp_223_fu_16954_p2) & ~(1'b0 == or_cond50_fu_16948_p2)) | (~(1'b0 == tmp_217_fu_16910_p2) & ~(1'b0 == tmp_220_fu_16931_p2) & ~(1'b0 == or_cond51_fu_16971_p2)) | (~(1'b0 == tmp_223_fu_16954_p2) & ~(1'b0 == or_cond_85_fu_16925_p2) & ~(1'b0 == or_cond50_fu_16948_p2)) | (~(1'b0 == tmp_220_fu_16931_p2) & ~(1'b0 == or_cond_85_fu_16925_p2) & ~(1'b0 == or_cond51_fu_16971_p2)) | (~(1'b0 == tmp_217_fu_16910_p2) & ~(1'b0 == or_cond50_fu_16948_p2) & ~(1'b0 == or_cond51_fu_16971_p2)) | (~(1'b0 == or_cond_85_fu_16925_p2) & ~(1'b0 == or_cond50_fu_16948_p2) & ~(1'b0 == or_cond51_fu_16971_p2)))) begin
win_l2_V_load_phi_fu_3713_p8 = ap_reg_phiprechg_win_l1_V_load_6_reg_1630pp0_it1;
end else begin
win_l2_V_load_phi_fu_3713_p8 = ap_reg_phiprechg_win_l2_V_load_reg_3710pp0_it1;
end
end
always @ (*) begin
if ((1'b0 == tmp_23_fu_17367_p2)) begin
winid_1_V_write_assign_phi_fu_3873_p4 = p_tmp_s_fu_17385_p3;
end else if (~(1'b0 == tmp_23_fu_17367_p2)) begin
winid_1_V_write_assign_phi_fu_3873_p4 = p_086_0_i1_fu_17394_p3;
end else begin
winid_1_V_write_assign_phi_fu_3873_p4 = ap_reg_phiprechg_winid_1_V_write_assign_reg_3870pp0_it1;
end
end
always @ (*) begin
if ((1'b0 == tmp_37_fu_19533_p2)) begin
winid_2_V_write_assign_phi_fu_14602_p4 = p_tmp_1_fu_19551_p3;
end else if (~(1'b0 == tmp_37_fu_19533_p2)) begin
winid_2_V_write_assign_phi_fu_14602_p4 = p_086_0_i_fu_19560_p3;
end else begin
winid_2_V_write_assign_phi_fu_14602_p4 = ap_reg_phiprechg_winid_2_V_write_assign_reg_14599pp0_it1;
end
end
assign a_winid_V_10_phi_fu_2627_p8 = ap_reg_phiprechg_a_winid_V_10_reg_2620pp0_it1;
assign a_winid_V_11_phi_fu_2845_p8 = ap_reg_phiprechg_a_winid_V_11_reg_2838pp0_it1;
assign a_winid_V_12_cast_fu_16886_p1 = $signed(ap_reg_phiprechg_a_winid_V_12_reg_3056pp0_it1);
assign a_winid_V_13_cast_fu_16894_p1 = $signed(ap_reg_phiprechg_a_winid_V_13_reg_3274pp0_it1);
assign a_winid_V_14_cast_fu_16902_p1 = $signed(ap_reg_phiprechg_a_winid_V_14_reg_3492pp0_it1);
assign a_winid_V_1_11_cast_fu_18411_p1 = $signed(a_winid_V_1_11_phi_fu_13765_p8);
assign a_winid_V_1_12_cast_fu_18491_p1 = $signed(a_winid_V_1_12_phi_fu_13996_p8);
assign a_winid_V_1_13_cast_fu_18571_p1 = $signed(a_winid_V_1_13_phi_fu_14227_p8);
assign a_winid_V_1_6_cast_fu_17947_p1 = $signed(a_winid_V_1_6_phi_fu_12565_p8);
assign a_winid_V_1_7_cast_fu_18027_p1 = $signed(a_winid_V_1_7_phi_fu_12703_p8);
assign a_winid_V_2_phi_fu_1596_p8 = ap_reg_phiprechg_a_winid_V_2_reg_1589pp0_it1;
assign a_winid_V_3_phi_fu_1650_p8 = ap_reg_phiprechg_a_winid_V_3_reg_1643pp0_it1;
assign a_winid_V_4_phi_fu_1691_p8 = ap_reg_phiprechg_a_winid_V_4_reg_1684pp0_it1;
assign a_winid_V_5_phi_fu_1816_p8 = ap_reg_phiprechg_a_winid_V_5_reg_1809pp0_it1;
assign a_winid_V_6_cast_fu_16854_p1 = $signed(ap_reg_phiprechg_a_winid_V_6_reg_1934pp0_it1);
assign a_winid_V_7_cast_fu_16862_p1 = $signed(ap_reg_phiprechg_a_winid_V_7_reg_2059pp0_it1);
assign a_winid_V_8_phi_fu_2191_p8 = ap_reg_phiprechg_a_winid_V_8_reg_2184pp0_it1;
assign a_winid_V_9_phi_fu_2409_p8 = ap_reg_phiprechg_a_winid_V_9_reg_2402pp0_it1;
assign a_winid_V_s_phi_fu_1542_p8 = ap_reg_phiprechg_a_winid_V_s_reg_1535pp0_it1;
assign ap_reg_phiprechg_a_winid_1_V_1_reg_14455pp0_it1 = 'bx;
assign ap_reg_phiprechg_a_winid_1_V_reg_3726pp0_it1 = 'bx;
assign ap_reg_phiprechg_a_winid_V_10_reg_2620pp0_it0 = 'bx;
assign ap_reg_phiprechg_a_winid_V_11_reg_2838pp0_it0 = 'bx;
assign ap_reg_phiprechg_a_winid_V_12_reg_3056pp0_it0 = 'bx;
assign ap_reg_phiprechg_a_winid_V_13_reg_3274pp0_it0 = 'bx;
assign ap_reg_phiprechg_a_winid_V_14_reg_3492pp0_it0 = 'bx;
assign ap_reg_phiprechg_a_winid_V_1_10_reg_13531pp0_it1 = 'bx;
assign ap_reg_phiprechg_a_winid_V_1_11_reg_13762pp0_it1 = 'bx;
assign ap_reg_phiprechg_a_winid_V_1_12_reg_13993pp0_it1 = 'bx;
assign ap_reg_phiprechg_a_winid_V_1_13_reg_14224pp0_it1 = 'bx;
assign ap_reg_phiprechg_a_winid_V_1_1_reg_12124pp0_it1 = 'bx;
assign ap_reg_phiprechg_a_winid_V_1_2_reg_12178pp0_it1 = 'bx;
assign ap_reg_phiprechg_a_winid_V_1_3_reg_12232pp0_it1 = 'bx;
assign ap_reg_phiprechg_a_winid_V_1_4_reg_12286pp0_it1 = 'bx;
assign ap_reg_phiprechg_a_winid_V_1_5_reg_12424pp0_it1 = 'bx;
assign ap_reg_phiprechg_a_winid_V_1_6_reg_12562pp0_it1 = 'bx;
assign ap_reg_phiprechg_a_winid_V_1_7_reg_12700pp0_it1 = 'bx;
assign ap_reg_phiprechg_a_winid_V_1_8_reg_12838pp0_it1 = 'bx;
assign ap_reg_phiprechg_a_winid_V_1_9_reg_13069pp0_it1 = 'bx;
assign ap_reg_phiprechg_a_winid_V_1_reg_12070pp0_it1 = 'bx;
assign ap_reg_phiprechg_a_winid_V_1_s_reg_13300pp0_it1 = 'bx;
assign ap_reg_phiprechg_a_winid_V_2_reg_1589pp0_it0 = 'bx;
assign ap_reg_phiprechg_a_winid_V_3_reg_1643pp0_it0 = 'bx;
assign ap_reg_phiprechg_a_winid_V_4_reg_1684pp0_it0 = 'bx;
assign ap_reg_phiprechg_a_winid_V_5_reg_1809pp0_it0 = 'bx;
assign ap_reg_phiprechg_a_winid_V_6_reg_1934pp0_it0 = 'bx;
assign ap_reg_phiprechg_a_winid_V_7_reg_2059pp0_it0 = 'bx;
assign ap_reg_phiprechg_a_winid_V_8_reg_2184pp0_it0 = 'bx;
assign ap_reg_phiprechg_a_winid_V_9_reg_2402pp0_it0 = 'bx;
assign ap_reg_phiprechg_a_winid_V_s_reg_1535pp0_it0 = 'bx;
assign ap_reg_phiprechg_ranki_l1_0_V_1_reg_12087pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_0_V_reg_1497pp0_it0 = 'bx;
assign ap_reg_phiprechg_ranki_l1_10_V_1_reg_13317pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_10_V_reg_2641pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_11_V_1_reg_13548pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_11_V_reg_2859pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_12_V_1_reg_13779pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_12_V_reg_3077pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_13_V_1_reg_14010pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_13_V_reg_3295pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_14_V_1_reg_14241pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_14_V_reg_3513pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_1_V_1_reg_12141pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_1_V_reg_1556pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_2_V_1_reg_12195pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_2_V_reg_1610pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_3_V_1_reg_12249pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_3_V_reg_1664pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_4_V_1_reg_12303pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_4_V_reg_1705pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_5_V_1_reg_12441pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_5_V_reg_1830pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_6_V_1_reg_12579pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_6_V_reg_1955pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_7_V_1_reg_12717pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_7_V_reg_2080pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_8_V_1_reg_12855pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_8_V_reg_2205pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_9_V_1_reg_13086pp0_it1 = 'bx;
assign ap_reg_phiprechg_ranki_l1_9_V_reg_2423pp0_it1 = 'bx;
assign ap_reg_phiprechg_sorter_a_V_load29_phi_reg_3743pp0_it1 = 'bx;
assign ap_reg_phiprechg_sorter_a_V_load_14_phi_reg_14472pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_10_reg_10579pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_11_reg_10445pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_12_reg_10311pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_13_reg_10177pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_14_reg_10043pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_15_reg_9909pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_16_reg_9775pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_17_reg_9641pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_18_reg_9507pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_19_reg_9373pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_1_reg_4013pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_20_reg_9239pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_21_reg_9105pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_22_reg_8971pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_23_reg_8837pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_24_reg_8703pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_25_reg_8569pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_26_reg_8435pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_27_reg_8301pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_28_reg_8167pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_29_reg_8033pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_2_reg_11651pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_30_reg_7899pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_31_reg_7765pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_32_reg_7631pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_33_reg_7497pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_34_reg_7363pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_35_reg_7229pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_36_reg_7095pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_37_reg_6961pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_38_reg_6827pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_39_reg_6693pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_3_reg_11517pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_40_reg_6559pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_41_reg_6425pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_42_reg_6291pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_43_reg_6157pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_44_reg_6023pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_45_reg_5889pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_46_reg_5755pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_47_reg_5621pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_48_reg_5487pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_49_reg_5353pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_4_reg_11383pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_50_reg_5219pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_51_reg_5085pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_52_reg_4951pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_53_reg_4817pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_54_reg_4683pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_55_reg_4549pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_56_reg_4415pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_57_reg_4281pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_58_reg_4147pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_59_reg_11785pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_5_reg_11249pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_6_reg_11115pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_7_reg_10981pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_8_reg_10847pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_9_reg_10713pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_reg_11919pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l0_V_s_reg_3879pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l1_V_1_load_1_1_reg_12407pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l1_V_1_load_1_2_reg_13052pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l1_V_1_load_1_3_reg_13976pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l1_V_1_load_1_reg_12107pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l1_V_1_load_2_1_reg_12545pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l1_V_1_load_2_2_reg_13283pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l1_V_1_load_2_3_reg_14207pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l1_V_1_load_2_reg_12161pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l1_V_1_load_3_1_reg_12683pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l1_V_1_load_3_2_reg_13514pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l1_V_1_load_3_reg_12215pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l1_V_1_load_4_reg_12821pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l1_V_1_load_5_reg_13745pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l1_V_1_load_reg_12053pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l1_V_1_load_s_reg_12269pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l1_V_load_1_reg_1354pp0_it0 = 'bx;
assign ap_reg_phiprechg_win_l1_V_load_2_reg_1406pp0_it0 = 'bx;
assign ap_reg_phiprechg_win_l1_V_load_3_reg_1458pp0_it0 = 'bx;
assign ap_reg_phiprechg_win_l1_V_load_4_1_reg_1367pp0_it0 = 'bx;
assign ap_reg_phiprechg_win_l1_V_load_4_2_reg_1419pp0_it0 = 'bx;
assign ap_reg_phiprechg_win_l1_V_load_4_3_reg_1471pp0_it0 = 'bx;
assign ap_reg_phiprechg_win_l1_V_load_4_reg_1522pp0_it0 = 'bx;
assign ap_reg_phiprechg_win_l1_V_load_5_1_reg_1380pp0_it0 = 'bx;
assign ap_reg_phiprechg_win_l1_V_load_5_2_reg_1432pp0_it0 = 'bx;
assign ap_reg_phiprechg_win_l1_V_load_5_3_reg_1484pp0_it0 = 'bx;
assign ap_reg_phiprechg_win_l1_V_load_5_reg_1576pp0_it0 = 'bx;
assign ap_reg_phiprechg_win_l1_V_load_6_1_reg_1393pp0_it0 = 'bx;
assign ap_reg_phiprechg_win_l1_V_load_6_2_reg_1445pp0_it0 = 'bx;
assign ap_reg_phiprechg_win_l1_V_load_6_reg_1630pp0_it0 = 'bx;
assign ap_reg_phiprechg_win_l2_V_1_load_reg_14438pp0_it1 = 'bx;
assign ap_reg_phiprechg_win_l2_V_load_reg_3710pp0_it1 = 'bx;
assign ap_reg_phiprechg_winid_1_V_write_assign_reg_3870pp0_it1 = 'bx;
assign ap_reg_phiprechg_winid_2_V_write_assign_reg_14599pp0_it1 = 'bx;
assign ap_return_0 = winner_0_V_write_assign_reg_19969;
assign ap_return_1 = win0_V_fu_17335_p3;
assign ap_return_2 = win0_V_1_fu_19505_p3;
assign ap_return_3 = winid_0_V_write_assign_reg_19974;
assign ap_return_4 = winid_1_V_write_assign_phi_fu_3873_p4;
assign ap_return_5 = winid_2_V_write_assign_phi_fu_14602_p4;
assign newSel13_fu_15330_p3 = ((or_cond_fu_15316_p2[0:0] === 1'b1) ? newSel_fu_15308_p3 : newSel141_cast_fu_15322_p3);
assign newSel141_cast_fu_15322_p3 = ((sel_tmp2013_demorgan_fu_15218_p2[0:0] === 1'b1) ? ap_const_lv2_3 : ap_const_lv2_0);
assign newSel14_fu_17019_p3 = ((sel_tmp55_reg_24353[0:0] === 1'b1) ? ap_const_lv3_6 : ap_const_lv3_5);
assign newSel15_fu_17030_p3 = ((sel_tmp2057_demorgan_reg_24343[0:0] === 1'b1) ? ap_const_lv3_7 : ap_const_lv3_4);
assign newSel16_fu_17037_p3 = ((or_cond4_fu_17026_p2[0:0] === 1'b1) ? newSel14_fu_17019_p3 : newSel15_fu_17030_p3);
assign newSel17_fu_17087_p3 = ((sel_tmp64_reg_24379[0:0] === 1'b1) ? ap_const_lv4_A : ap_const_lv4_9);
assign newSel18_fu_17098_p3 = ((sel_tmp2101_demorgan_reg_24369[0:0] === 1'b1) ? ap_const_lv4_B : ap_const_lv4_8);
assign newSel20_fu_17151_p3 = ((sel_tmp73_reg_24405[0:0] === 1'b1) ? ap_const_lv3_6 : ap_const_lv3_5);
assign newSel21_fu_17162_p3 = ((sel_tmp2145_demorgan_reg_24395[0:0] === 1'b1) ? ap_const_lv3_7 : ap_const_lv3_4);
assign newSel22_fu_17169_p3 = ((or_cond6_fu_17158_p2[0:0] === 1'b1) ? newSel20_fu_17151_p3 : newSel21_fu_17162_p3);
assign newSel23_fu_18849_p3 = ((sel_tmp85_fu_18835_p2[0:0] === 1'b1) ? ap_const_lv3_6 : ap_const_lv3_5);
assign newSel24_fu_18863_p3 = ((sel_tmp2197_demorgan_fu_18759_p2[0:0] === 1'b1) ? ap_const_lv3_7 : ap_const_lv3_4);
assign newSel25_fu_18871_p3 = ((or_cond7_fu_18857_p2[0:0] === 1'b1) ? newSel23_fu_18849_p3 : newSel24_fu_18863_p3);
assign newSel26_fu_19077_p3 = ((sel_tmp94_fu_19063_p2[0:0] === 1'b1) ? ap_const_lv4_A : ap_const_lv4_9);
assign newSel27_fu_19091_p3 = ((sel_tmp2241_demorgan_fu_18987_p2[0:0] === 1'b1) ? ap_const_lv4_B : ap_const_lv4_8);
assign newSel29_fu_19301_p3 = ((sel_tmp103_fu_19287_p2[0:0] === 1'b1) ? ap_const_lv3_6 : ap_const_lv3_5);
assign newSel30_fu_19315_p3 = ((sel_tmp2285_demorgan_fu_19211_p2[0:0] === 1'b1) ? ap_const_lv3_7 : ap_const_lv3_4);
assign newSel31_fu_19323_p3 = ((or_cond9_fu_19309_p2[0:0] === 1'b1) ? newSel29_fu_19301_p3 : newSel30_fu_19315_p3);
assign newSel_fu_15308_p3 = ((sel_tmp46_fu_15294_p2[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_1);
assign or_cond100_fu_15932_p2 = (tmp_295_9_fu_15920_p2 | tmp_306_9_fu_15926_p2);
assign or_cond101_fu_15956_p2 = (tmp_312_9_fu_15944_p2 | tmp_315_9_fu_15950_p2);
assign or_cond102_fu_15980_p2 = (tmp_321_9_fu_15968_p2 | tmp_324_9_fu_15974_p2);
assign or_cond103_fu_16004_p2 = (tmp_295_s_fu_15992_p2 | tmp_306_s_fu_15998_p2);
assign or_cond104_fu_16028_p2 = (tmp_312_s_fu_16016_p2 | tmp_315_s_fu_16022_p2);
assign or_cond105_fu_16052_p2 = (tmp_321_s_fu_16040_p2 | tmp_324_s_fu_16046_p2);
assign or_cond106_fu_16076_p2 = (tmp_295_10_fu_16064_p2 | tmp_306_10_fu_16070_p2);
assign or_cond107_fu_16100_p2 = (tmp_312_10_fu_16088_p2 | tmp_315_10_fu_16094_p2);
assign or_cond108_fu_16124_p2 = (tmp_321_10_fu_16112_p2 | tmp_324_10_fu_16118_p2);
assign or_cond109_fu_16148_p2 = (tmp_295_11_fu_16136_p2 | tmp_306_11_fu_16142_p2);
assign or_cond110_fu_16172_p2 = (tmp_312_11_fu_16160_p2 | tmp_315_11_fu_16166_p2);
assign or_cond111_fu_16196_p2 = (tmp_321_11_fu_16184_p2 | tmp_324_11_fu_16190_p2);
assign or_cond112_fu_16220_p2 = (tmp_295_12_fu_16208_p2 | tmp_306_12_fu_16214_p2);
assign or_cond113_fu_16244_p2 = (tmp_312_12_fu_16232_p2 | tmp_315_12_fu_16238_p2);
assign or_cond114_fu_16268_p2 = (tmp_321_12_fu_16256_p2 | tmp_324_12_fu_16262_p2);
assign or_cond115_fu_16292_p2 = (tmp_295_13_fu_16280_p2 | tmp_306_13_fu_16286_p2);
assign or_cond116_fu_16316_p2 = (tmp_312_13_fu_16304_p2 | tmp_315_13_fu_16310_p2);
assign or_cond117_fu_16340_p2 = (tmp_321_13_fu_16328_p2 | tmp_324_13_fu_16334_p2);
assign or_cond118_fu_17421_p2 = (tmp_227_fu_17409_p2 | tmp_228_fu_17415_p2);
assign or_cond119_fu_17445_p2 = (tmp_230_fu_17433_p2 | tmp_231_fu_17439_p2);
assign or_cond120_fu_17469_p2 = (tmp_233_fu_17457_p2 | tmp_234_fu_17463_p2);
assign or_cond121_fu_17501_p2 = (tmp_352_1_fu_17489_p2 | tmp_363_1_fu_17495_p2);
assign or_cond122_fu_17525_p2 = (tmp_369_1_fu_17513_p2 | tmp_372_1_fu_17519_p2);
assign or_cond123_fu_17549_p2 = (tmp_378_1_fu_17537_p2 | tmp_381_1_fu_17543_p2);
assign or_cond124_fu_17581_p2 = (tmp_352_2_fu_17569_p2 | tmp_363_2_fu_17575_p2);
assign or_cond125_fu_17605_p2 = (tmp_369_2_fu_17593_p2 | tmp_372_2_fu_17599_p2);
assign or_cond126_fu_17629_p2 = (tmp_378_2_fu_17617_p2 | tmp_381_2_fu_17623_p2);
assign or_cond127_fu_17661_p2 = (tmp_352_3_fu_17649_p2 | tmp_363_3_fu_17655_p2);
assign or_cond128_fu_17685_p2 = (tmp_369_3_fu_17673_p2 | tmp_372_3_fu_17679_p2);
assign or_cond129_fu_17709_p2 = (tmp_378_3_fu_17697_p2 | tmp_381_3_fu_17703_p2);
assign or_cond130_fu_17741_p2 = (tmp_352_4_fu_17729_p2 | tmp_363_4_fu_17735_p2);
assign or_cond131_fu_17765_p2 = (tmp_369_4_fu_17753_p2 | tmp_372_4_fu_17759_p2);
assign or_cond132_fu_17789_p2 = (tmp_378_4_fu_17777_p2 | tmp_381_4_fu_17783_p2);
assign or_cond133_fu_17817_p2 = (tmp_352_5_fu_17805_p2 | tmp_363_5_fu_17811_p2);
assign or_cond134_fu_17841_p2 = (tmp_369_5_fu_17829_p2 | tmp_372_5_fu_17835_p2);
assign or_cond135_fu_17865_p2 = (tmp_378_5_fu_17853_p2 | tmp_381_5_fu_17859_p2);
assign or_cond136_fu_17893_p2 = (tmp_352_6_fu_17881_p2 | tmp_363_6_fu_17887_p2);
assign or_cond137_fu_17917_p2 = (tmp_369_6_fu_17905_p2 | tmp_372_6_fu_17911_p2);
assign or_cond138_fu_17941_p2 = (tmp_378_6_fu_17929_p2 | tmp_381_6_fu_17935_p2);
assign or_cond139_fu_17973_p2 = (tmp_352_7_fu_17961_p2 | tmp_363_7_fu_17967_p2);
assign or_cond140_fu_17997_p2 = (tmp_369_7_fu_17985_p2 | tmp_372_7_fu_17991_p2);
assign or_cond141_fu_18021_p2 = (tmp_378_7_fu_18009_p2 | tmp_381_7_fu_18015_p2);
assign or_cond142_fu_18053_p2 = (tmp_352_8_fu_18041_p2 | tmp_363_8_fu_18047_p2);
assign or_cond143_fu_18077_p2 = (tmp_369_8_fu_18065_p2 | tmp_372_8_fu_18071_p2);
assign or_cond144_fu_18101_p2 = (tmp_378_8_fu_18089_p2 | tmp_381_8_fu_18095_p2);
assign or_cond145_fu_18129_p2 = (tmp_352_9_fu_18117_p2 | tmp_363_9_fu_18123_p2);
assign or_cond146_fu_18153_p2 = (tmp_369_9_fu_18141_p2 | tmp_372_9_fu_18147_p2);
assign or_cond147_fu_18177_p2 = (tmp_378_9_fu_18165_p2 | tmp_381_9_fu_18171_p2);
assign or_cond148_fu_18205_p2 = (tmp_352_s_fu_18193_p2 | tmp_363_s_fu_18199_p2);
assign or_cond149_fu_18229_p2 = (tmp_369_s_fu_18217_p2 | tmp_372_s_fu_18223_p2);
assign or_cond150_fu_18253_p2 = (tmp_378_s_fu_18241_p2 | tmp_381_s_fu_18247_p2);
assign or_cond151_fu_18281_p2 = (tmp_352_10_fu_18269_p2 | tmp_363_10_fu_18275_p2);
assign or_cond152_fu_18305_p2 = (tmp_369_10_fu_18293_p2 | tmp_372_10_fu_18299_p2);
assign or_cond153_fu_18329_p2 = (tmp_378_10_fu_18317_p2 | tmp_381_10_fu_18323_p2);
assign or_cond154_fu_18357_p2 = (tmp_352_11_fu_18345_p2 | tmp_363_11_fu_18351_p2);
assign or_cond155_fu_18381_p2 = (tmp_369_11_fu_18369_p2 | tmp_372_11_fu_18375_p2);
assign or_cond156_fu_18405_p2 = (tmp_378_11_fu_18393_p2 | tmp_381_11_fu_18399_p2);
assign or_cond157_fu_18437_p2 = (tmp_352_12_fu_18425_p2 | tmp_363_12_fu_18431_p2);
assign or_cond158_fu_18461_p2 = (tmp_369_12_fu_18449_p2 | tmp_372_12_fu_18455_p2);
assign or_cond159_fu_18485_p2 = (tmp_378_12_fu_18473_p2 | tmp_381_12_fu_18479_p2);
assign or_cond160_fu_18517_p2 = (tmp_352_13_fu_18505_p2 | tmp_363_13_fu_18511_p2);
assign or_cond161_fu_18541_p2 = (tmp_369_13_fu_18529_p2 | tmp_372_13_fu_18535_p2);
assign or_cond162_fu_18565_p2 = (tmp_378_13_fu_18553_p2 | tmp_381_13_fu_18559_p2);
assign or_cond4_fu_17026_p2 = (sel_tmp55_reg_24353 | sel_tmp49_reg_24348);
assign or_cond50_fu_16948_p2 = (tmp_221_fu_16936_p2 | tmp_222_fu_16942_p2);
assign or_cond51_fu_16971_p2 = (tmp_224_fu_16959_p2 | tmp_225_fu_16965_p2);
assign or_cond52_fu_16364_p2 = (tmp_308_1_fu_16352_p2 | tmp_311_1_fu_16358_p2);
assign or_cond53_fu_16388_p2 = (tmp_317_1_fu_16376_p2 | tmp_320_1_fu_16382_p2);
assign or_cond55_fu_16520_p2 = (tmp_308_2_fu_16508_p2 | tmp_311_2_fu_16514_p2);
assign or_cond56_fu_16544_p2 = (tmp_317_2_fu_16532_p2 | tmp_320_2_fu_16538_p2);
assign or_cond57_fu_15170_p2 = (tmp_209_fu_15158_p2 | tmp_210_fu_15164_p2);
assign or_cond58_fu_16676_p2 = (tmp_308_3_fu_16664_p2 | tmp_311_3_fu_16670_p2);
assign or_cond59_fu_16700_p2 = (tmp_317_3_fu_16688_p2 | tmp_320_3_fu_16694_p2);
assign or_cond5_fu_17094_p2 = (sel_tmp64_reg_24379 | sel_tmp58_reg_24374);
assign or_cond60_fu_15194_p2 = (tmp_212_fu_15182_p2 | tmp_213_fu_15188_p2);
assign or_cond61_fu_15356_p2 = (tmp_295_1_fu_15344_p2 | tmp_306_1_fu_15350_p2);
assign or_cond62_fu_17240_p2 = (tmp22_fu_17234_p2 | tmp_s_fu_17219_p2);
assign or_cond63_fu_15380_p2 = (tmp_312_1_fu_15368_p2 | tmp_315_1_fu_15374_p2);
assign or_cond64_fu_17265_p2 = (tmp23_fu_17259_p2 | tmp_16_fu_17246_p2);
assign or_cond65_fu_15404_p2 = (tmp_321_1_fu_15392_p2 | tmp_324_1_fu_15398_p2);
assign or_cond66_fu_17290_p2 = (tmp24_fu_17284_p2 | tmp_19_fu_17271_p2);
assign or_cond67_fu_18597_p2 = (tmp_236_fu_18585_p2 | tmp_237_fu_18591_p2);
assign or_cond68_fu_18621_p2 = (tmp_239_fu_18609_p2 | tmp_240_fu_18615_p2);
assign or_cond69_fu_18645_p2 = (tmp_242_fu_18633_p2 | tmp_243_fu_18639_p2);
assign or_cond6_fu_17158_p2 = (sel_tmp73_reg_24405 | sel_tmp67_reg_24400);
assign or_cond70_fu_18711_p2 = (tmp_365_1_fu_18699_p2 | tmp_368_1_fu_18705_p2);
assign or_cond71_fu_18735_p2 = (tmp_374_1_fu_18723_p2 | tmp_377_1_fu_18729_p2);
assign or_cond72_fu_15428_p2 = (tmp_295_2_fu_15416_p2 | tmp_306_2_fu_15422_p2);
assign or_cond73_fu_18939_p2 = (tmp_365_2_fu_18927_p2 | tmp_368_2_fu_18933_p2);
assign or_cond74_fu_18963_p2 = (tmp_374_2_fu_18951_p2 | tmp_377_2_fu_18957_p2);
assign or_cond75_fu_15452_p2 = (tmp_312_2_fu_15440_p2 | tmp_315_2_fu_15446_p2);
assign or_cond76_fu_19163_p2 = (tmp_365_3_fu_19151_p2 | tmp_368_3_fu_19157_p2);
assign or_cond77_fu_19187_p2 = (tmp_374_3_fu_19175_p2 | tmp_377_3_fu_19181_p2);
assign or_cond78_fu_15476_p2 = (tmp_321_2_fu_15464_p2 | tmp_324_2_fu_15470_p2);
assign or_cond79_fu_15500_p2 = (tmp_295_3_fu_15488_p2 | tmp_306_3_fu_15494_p2);
assign or_cond7_fu_18857_p2 = (sel_tmp85_fu_18835_p2 | sel_tmp79_fu_18785_p2);
assign or_cond80_fu_19397_p2 = (tmp48_fu_19391_p2 | tmp_27_fu_19373_p2);
assign or_cond81_fu_15524_p2 = (tmp_312_3_fu_15512_p2 | tmp_315_3_fu_15518_p2);
assign or_cond82_fu_19427_p2 = (tmp49_fu_19421_p2 | tmp_30_fu_19403_p2);
assign or_cond83_fu_15548_p2 = (tmp_321_3_fu_15536_p2 | tmp_324_3_fu_15542_p2);
assign or_cond84_fu_19457_p2 = (tmp50_fu_19451_p2 | tmp_33_fu_19433_p2);
assign or_cond85_fu_15572_p2 = (tmp_295_4_fu_15560_p2 | tmp_306_4_fu_15566_p2);
assign or_cond86_fu_15596_p2 = (tmp_312_4_fu_15584_p2 | tmp_315_4_fu_15590_p2);
assign or_cond87_fu_15620_p2 = (tmp_321_4_fu_15608_p2 | tmp_324_4_fu_15614_p2);
assign or_cond88_fu_15644_p2 = (tmp_295_5_fu_15632_p2 | tmp_306_5_fu_15638_p2);
assign or_cond89_fu_15668_p2 = (tmp_312_5_fu_15656_p2 | tmp_315_5_fu_15662_p2);
assign or_cond8_fu_19085_p2 = (sel_tmp94_fu_19063_p2 | sel_tmp88_fu_19013_p2);
assign or_cond90_fu_15692_p2 = (tmp_321_5_fu_15680_p2 | tmp_324_5_fu_15686_p2);
assign or_cond91_fu_15716_p2 = (tmp_295_6_fu_15704_p2 | tmp_306_6_fu_15710_p2);
assign or_cond92_fu_15740_p2 = (tmp_312_6_fu_15728_p2 | tmp_315_6_fu_15734_p2);
assign or_cond93_fu_15764_p2 = (tmp_321_6_fu_15752_p2 | tmp_324_6_fu_15758_p2);
assign or_cond94_fu_15788_p2 = (tmp_295_7_fu_15776_p2 | tmp_306_7_fu_15782_p2);
assign or_cond95_fu_15812_p2 = (tmp_312_7_fu_15800_p2 | tmp_315_7_fu_15806_p2);
assign or_cond96_fu_15836_p2 = (tmp_321_7_fu_15824_p2 | tmp_324_7_fu_15830_p2);
assign or_cond97_fu_15860_p2 = (tmp_295_8_fu_15848_p2 | tmp_306_8_fu_15854_p2);
assign or_cond98_fu_15884_p2 = (tmp_312_8_fu_15872_p2 | tmp_315_8_fu_15878_p2);
assign or_cond99_fu_15908_p2 = (tmp_321_8_fu_15896_p2 | tmp_324_8_fu_15902_p2);
assign or_cond9_fu_19309_p2 = (sel_tmp103_fu_19287_p2 | sel_tmp97_fu_19237_p2);
assign or_cond_85_fu_16925_p2 = (tmp_218_fu_16915_p2 | tmp_219_fu_16920_p2);
assign or_cond_fu_15316_p2 = (sel_tmp46_fu_15294_p2 | sel_tmp40_fu_15244_p2);
assign p_086_0_i1_fu_17394_p3 = ((tmp_24_fu_17373_p2[0:0] === 1'b1) ? ap_const_lv7_7F : tmp_2772_fu_17361_p2);
assign p_086_0_i_fu_19560_p3 = ((tmp_38_fu_19539_p2[0:0] === 1'b1) ? ap_const_lv7_7F : tmp_2773_fu_19527_p2);
assign p_tmp_1_fu_19551_p3 = ((tmp_38_fu_19539_p2[0:0] === 1'b1) ? ap_const_lv7_7F : tmp_40_fu_19545_p2);
assign p_tmp_s_fu_17385_p3 = ((tmp_24_fu_17373_p2[0:0] === 1'b1) ? ap_const_lv7_7F : tmp_26_fu_17379_p2);
assign phitmp1_fu_19471_p3 = ((or_cond84_fu_19457_p2[0:0] === 1'b1) ? ap_const_lv2_3 : ap_const_lv2_2);
assign phitmp_fu_17302_p3 = ((or_cond66_fu_17290_p2[0:0] === 1'b1) ? ap_const_lv2_3 : ap_const_lv2_2);
assign ranki_l1_0_V_0_cast2_fu_16814_p1 = $signed(ap_reg_phiprechg_ranki_l1_0_V_reg_1497pp0_it1);
assign ranki_l1_0_V_0_cast_fu_16818_p1 = $unsigned(ranki_l1_0_V_0_cast2_fu_16814_p1);
assign ranki_l1_0_V_1_cast_fu_17475_p1 = $signed(ranki_l1_0_V_1_phi_fu_12090_p10);
assign ranki_l1_0_V_3_0_cast_fu_17479_p1 = $unsigned(ranki_l1_0_V_1_cast_fu_17475_p1);
assign ranki_l1_10_V_0_cast_fu_16878_p1 = ranki_l1_10_V_phi_fu_2644_p128;
assign ranki_l1_10_V_3_0_cast_fu_18259_p1 = ranki_l1_10_V_1_phi_fu_13320_p128;
assign ranki_l1_11_V_0_cast_fu_16882_p1 = ranki_l1_11_V_phi_fu_2862_p128;
assign ranki_l1_11_V_3_0_cast_fu_18335_p1 = ranki_l1_11_V_1_phi_fu_13551_p128;
assign ranki_l1_12_V_0_cast_fu_16890_p1 = ranki_l1_12_V_phi_fu_3080_p128;
assign ranki_l1_12_V_3_0_cast_fu_18415_p1 = ranki_l1_12_V_1_phi_fu_13782_p128;
assign ranki_l1_13_V_0_cast_fu_16898_p1 = ranki_l1_13_V_phi_fu_3298_p128;
assign ranki_l1_13_V_3_0_cast_fu_18495_p1 = ranki_l1_13_V_1_phi_fu_14013_p128;
assign ranki_l1_14_V_0_cast_fu_16906_p1 = ranki_l1_14_V_phi_fu_3516_p128;
assign ranki_l1_14_V_3_0_cast_fu_18575_p1 = ranki_l1_14_V_1_phi_fu_14244_p128;
assign ranki_l1_1_V_0_cast_fu_16826_p1 = $unsigned(ranki_l1_1_V_cast_fu_16822_p1);
assign ranki_l1_1_V_1_cast_fu_17555_p1 = $signed(ranki_l1_1_V_1_phi_fu_12144_p10);
assign ranki_l1_1_V_3_0_cast_fu_17559_p1 = $unsigned(ranki_l1_1_V_1_cast_fu_17555_p1);
assign ranki_l1_1_V_cast_fu_16822_p1 = $signed(ranki_l1_1_V_phi_fu_1559_p10);
assign ranki_l1_2_V_0_cast_fu_16834_p1 = $unsigned(ranki_l1_2_V_cast_fu_16830_p1);
assign ranki_l1_2_V_1_cast_fu_17635_p1 = $signed(ranki_l1_2_V_1_phi_fu_12198_p10);
assign ranki_l1_2_V_3_0_cast_fu_17639_p1 = $unsigned(ranki_l1_2_V_1_cast_fu_17635_p1);
assign ranki_l1_2_V_cast_fu_16830_p1 = $signed(ranki_l1_2_V_phi_fu_1613_p10);
assign ranki_l1_3_V_0_cast_fu_16842_p1 = $unsigned(ranki_l1_3_V_cast_fu_16838_p1);
assign ranki_l1_3_V_1_cast_fu_17715_p1 = $signed(ranki_l1_3_V_1_phi_fu_12252_p10);
assign ranki_l1_3_V_3_0_cast_fu_17719_p1 = $unsigned(ranki_l1_3_V_1_cast_fu_17715_p1);
assign ranki_l1_3_V_cast_fu_16838_p1 = $signed(ranki_l1_3_V_phi_fu_1667_p10);
assign ranki_l1_4_V_0_cast_fu_16846_p1 = ranki_l1_4_V_phi_fu_1708_p66;
assign ranki_l1_4_V_3_0_cast_fu_17795_p1 = ranki_l1_4_V_1_phi_fu_12306_p66;
assign ranki_l1_5_V_0_cast_fu_16850_p1 = ranki_l1_5_V_phi_fu_1833_p66;
assign ranki_l1_5_V_3_0_cast_fu_17871_p1 = ranki_l1_5_V_1_phi_fu_12444_p66;
assign ranki_l1_6_V_0_cast_fu_16858_p1 = ranki_l1_6_V_phi_fu_1958_p66;
assign ranki_l1_6_V_3_0_cast_fu_17951_p1 = ranki_l1_6_V_1_phi_fu_12582_p66;
assign ranki_l1_7_V_0_cast_fu_16866_p1 = ranki_l1_7_V_phi_fu_2083_p66;
assign ranki_l1_7_V_3_0_cast_fu_18031_p1 = ranki_l1_7_V_1_phi_fu_12720_p66;
assign ranki_l1_8_V_0_cast_fu_16870_p1 = ranki_l1_8_V_phi_fu_2208_p128;
assign ranki_l1_8_V_3_0_cast_fu_18107_p1 = ranki_l1_8_V_1_phi_fu_12858_p128;
assign ranki_l1_9_V_0_cast_fu_16874_p1 = ranki_l1_9_V_phi_fu_2426_p128;
assign ranki_l1_9_V_3_0_cast_fu_18183_p1 = ranki_l1_9_V_1_phi_fu_13089_p128;
assign ranki_l2_0_V_1_fu_18655_p17 = a_winid_1_V_1_phi_fu_14458_p8;
assign ranki_l2_0_V_fu_16981_p17 = a_winid_1_V_phi_fu_3729_p8;
assign ranki_l2_1_V_1_fu_18883_p17 = newSel25_fu_18871_p3;
assign ranki_l2_1_V_fu_17049_p17 = newSel16_fu_17037_p3;
assign ranki_l2_2_V_1_fu_19107_p17 = ((or_cond8_fu_19085_p2[0:0] === 1'b1) ? newSel26_fu_19077_p3 : newSel27_fu_19091_p3);
assign ranki_l2_2_V_fu_17113_p17 = ((or_cond5_fu_17094_p2[0:0] === 1'b1) ? newSel17_fu_17087_p3 : newSel18_fu_17098_p3);
assign ranki_l2_3_V_1_fu_19335_p17 = $signed(newSel31_fu_19323_p3);
assign ranki_l2_3_V_fu_17181_p17 = $signed(newSel22_fu_17169_p3);
assign sel_tmp100_fu_19269_p2 = (tmp_362_3_fu_19145_p2 & or_cond77_fu_19187_p2);
assign sel_tmp102_fu_19281_p2 = (tmp47_fu_19275_p2 | sel_tmp100_fu_19269_p2);
assign sel_tmp103_fu_19287_p2 = (sel_tmp102_fu_19281_p2 & sel_tmp99_fu_19263_p2);
assign sel_tmp104_fu_19479_p1 = or_cond80_fu_19397_p2;
assign sel_tmp105_fu_19483_p2 = (or_cond80_fu_19397_p2 & or_cond82_fu_19427_p2);
assign sel_tmp106_fu_19497_p3 = ((or_cond80_fu_19397_p2[0:0] === 1'b1) ? win_l2_V_1_load_1_fu_18841_p3 : win_l2_V_1_load_phi_fu_14441_p8);
assign sel_tmp2013_demorgan_fu_15218_p2 = (tmp_208_fu_15152_p2 | or_cond57_fu_15170_p2);
assign sel_tmp2017_demorgan_fu_15232_p2 = (tmp_211_fu_15176_p2 | or_cond60_fu_15194_p2);
assign sel_tmp2023_demorgan_fu_15264_p2 = (tmp_fu_15258_p2 | tmp_215_fu_15206_p2);
assign sel_tmp2057_demorgan_fu_16412_p2 = (tmp_305_1_fu_16346_p2 | or_cond52_fu_16364_p2);
assign sel_tmp2061_demorgan_fu_16426_p2 = (tmp_314_1_fu_16370_p2 | or_cond53_fu_16388_p2);
assign sel_tmp2067_demorgan_fu_16458_p2 = (tmp16_fu_16452_p2 | tmp_326_1_fu_16400_p2);
assign sel_tmp2101_demorgan_fu_16568_p2 = (tmp_305_2_fu_16502_p2 | or_cond55_fu_16520_p2);
assign sel_tmp2105_demorgan_fu_16582_p2 = (tmp_314_2_fu_16526_p2 | or_cond56_fu_16544_p2);
assign sel_tmp2111_demorgan_fu_16614_p2 = (tmp18_fu_16608_p2 | tmp_326_2_fu_16556_p2);
assign sel_tmp2145_demorgan_fu_16724_p2 = (tmp_305_3_fu_16658_p2 | or_cond58_fu_16676_p2);
assign sel_tmp2149_demorgan_fu_16738_p2 = (tmp_314_3_fu_16682_p2 | or_cond59_fu_16700_p2);
assign sel_tmp2155_demorgan_fu_16770_p2 = (tmp20_fu_16764_p2 | tmp_326_3_fu_16712_p2);
assign sel_tmp2197_demorgan_fu_18759_p2 = (tmp_362_1_fu_18693_p2 | or_cond70_fu_18711_p2);
assign sel_tmp2201_demorgan_fu_18773_p2 = (tmp_371_1_fu_18717_p2 | or_cond71_fu_18735_p2);
assign sel_tmp2207_demorgan_fu_18805_p2 = (tmp42_fu_18799_p2 | tmp_383_1_fu_18747_p2);
assign sel_tmp2241_demorgan_fu_18987_p2 = (tmp_362_2_fu_18921_p2 | or_cond73_fu_18939_p2);
assign sel_tmp2245_demorgan_fu_19001_p2 = (tmp_371_2_fu_18945_p2 | or_cond74_fu_18963_p2);
assign sel_tmp2251_demorgan_fu_19033_p2 = (tmp44_fu_19027_p2 | tmp_383_2_fu_18975_p2);
assign sel_tmp2285_demorgan_fu_19211_p2 = (tmp_362_3_fu_19145_p2 | or_cond76_fu_19163_p2);
assign sel_tmp2289_demorgan_fu_19225_p2 = (tmp_371_3_fu_19169_p2 | or_cond77_fu_19187_p2);
assign sel_tmp2295_demorgan_fu_19257_p2 = (tmp46_fu_19251_p2 | tmp_383_3_fu_19199_p2);
assign sel_tmp39_fu_15238_p2 = (sel_tmp2017_demorgan_fu_15232_p2 ^ 1'b1);
assign sel_tmp40_fu_15244_p2 = (sel_tmp2013_demorgan_fu_15218_p2 & sel_tmp39_fu_15238_p2);
assign sel_tmp41_fu_15250_p3 = ((sel_tmp40_fu_15244_p2[0:0] === 1'b1) ? call_ret_sp_sort_fu_14608_ap_return_3 : sel_tmp_fu_15224_p3);
assign sel_tmp42_fu_15270_p2 = (sel_tmp2023_demorgan_fu_15264_p2 ^ 1'b1);
assign sel_tmp43_fu_15276_p2 = (tmp_208_fu_15152_p2 & or_cond60_fu_15194_p2);
assign sel_tmp45_fu_15288_p2 = (tmp15_fu_15282_p2 | sel_tmp43_fu_15276_p2);
assign sel_tmp46_fu_15294_p2 = (sel_tmp45_fu_15288_p2 & sel_tmp42_fu_15270_p2);
assign sel_tmp47_fu_16418_p3 = ((sel_tmp2057_demorgan_fu_16412_p2[0:0] === 1'b1) ? win_l1_V_load_6_1_phi_fu_1396_p8 : win_l1_V_load_1_phi_fu_1357_p8);
assign sel_tmp48_fu_16432_p2 = (sel_tmp2061_demorgan_fu_16426_p2 ^ 1'b1);
assign sel_tmp49_fu_16438_p2 = (sel_tmp2057_demorgan_fu_16412_p2 & sel_tmp48_fu_16432_p2);
assign sel_tmp50_fu_16444_p3 = ((sel_tmp49_fu_16438_p2[0:0] === 1'b1) ? win_l1_V_load_4_1_phi_fu_1370_p8 : sel_tmp47_fu_16418_p3);
assign sel_tmp51_fu_16464_p2 = (sel_tmp2067_demorgan_fu_16458_p2 ^ 1'b1);
assign sel_tmp52_fu_16470_p2 = (tmp_305_1_fu_16346_p2 & or_cond53_fu_16388_p2);
assign sel_tmp54_fu_16482_p2 = (tmp17_fu_16476_p2 | sel_tmp52_fu_16470_p2);
assign sel_tmp55_fu_16488_p2 = (sel_tmp54_fu_16482_p2 & sel_tmp51_fu_16464_p2);
assign sel_tmp56_fu_16574_p3 = ((sel_tmp2101_demorgan_fu_16568_p2[0:0] === 1'b1) ? win_l1_V_load_6_2_phi_fu_1448_p8 : win_l1_V_load_2_phi_fu_1409_p8);
assign sel_tmp57_fu_16588_p2 = (sel_tmp2105_demorgan_fu_16582_p2 ^ 1'b1);
assign sel_tmp58_fu_16594_p2 = (sel_tmp2101_demorgan_fu_16568_p2 & sel_tmp57_fu_16588_p2);
assign sel_tmp59_fu_16600_p3 = ((sel_tmp58_fu_16594_p2[0:0] === 1'b1) ? win_l1_V_load_4_2_phi_fu_1422_p8 : sel_tmp56_fu_16574_p3);
assign sel_tmp60_fu_16620_p2 = (sel_tmp2111_demorgan_fu_16614_p2 ^ 1'b1);
assign sel_tmp61_fu_16626_p2 = (tmp_305_2_fu_16502_p2 & or_cond56_fu_16544_p2);
assign sel_tmp63_fu_16638_p2 = (tmp19_fu_16632_p2 | sel_tmp61_fu_16626_p2);
assign sel_tmp64_fu_16644_p2 = (sel_tmp63_fu_16638_p2 & sel_tmp60_fu_16620_p2);
assign sel_tmp65_fu_16730_p3 = ((sel_tmp2145_demorgan_fu_16724_p2[0:0] === 1'b1) ? call_ret_sp_sort_fu_14608_ap_return_62 : win_l1_V_load_3_phi_fu_1461_p8);
assign sel_tmp66_fu_16744_p2 = (sel_tmp2149_demorgan_fu_16738_p2 ^ 1'b1);
assign sel_tmp67_fu_16750_p2 = (sel_tmp2145_demorgan_fu_16724_p2 & sel_tmp66_fu_16744_p2);
assign sel_tmp68_fu_16756_p3 = ((sel_tmp67_fu_16750_p2[0:0] === 1'b1) ? win_l1_V_load_4_3_phi_fu_1474_p8 : sel_tmp65_fu_16730_p3);
assign sel_tmp69_fu_16776_p2 = (sel_tmp2155_demorgan_fu_16770_p2 ^ 1'b1);
assign sel_tmp70_fu_16782_p2 = (tmp_305_3_fu_16658_p2 & or_cond59_fu_16700_p2);
assign sel_tmp72_fu_16794_p2 = (tmp21_fu_16788_p2 | sel_tmp70_fu_16782_p2);
assign sel_tmp73_fu_16800_p2 = (sel_tmp72_fu_16794_p2 & sel_tmp69_fu_16776_p2);
assign sel_tmp74_fu_17310_p1 = or_cond62_fu_17240_p2;
assign sel_tmp75_fu_17314_p2 = (or_cond62_fu_17240_p2 & or_cond64_fu_17265_p2);
assign sel_tmp76_fu_17328_p3 = ((or_cond62_fu_17240_p2[0:0] === 1'b1) ? win_l2_V_load_4_reg_24359 : win_l2_V_load_phi_fu_3713_p8);
assign sel_tmp77_fu_18765_p3 = ((sel_tmp2197_demorgan_fu_18759_p2[0:0] === 1'b1) ? win_l1_V_1_load_3_1_phi_fu_12686_p8 : win_l1_V_1_load_s_phi_fu_12272_p8);
assign sel_tmp78_fu_18779_p2 = (sel_tmp2201_demorgan_fu_18773_p2 ^ 1'b1);
assign sel_tmp79_fu_18785_p2 = (sel_tmp2197_demorgan_fu_18759_p2 & sel_tmp78_fu_18779_p2);
assign sel_tmp80_fu_18791_p3 = ((sel_tmp79_fu_18785_p2[0:0] === 1'b1) ? win_l1_V_1_load_1_1_phi_fu_12410_p8 : sel_tmp77_fu_18765_p3);
assign sel_tmp81_fu_18811_p2 = (sel_tmp2207_demorgan_fu_18805_p2 ^ 1'b1);
assign sel_tmp82_fu_18817_p2 = (tmp_362_1_fu_18693_p2 & or_cond71_fu_18735_p2);
assign sel_tmp84_fu_18829_p2 = (tmp43_fu_18823_p2 | sel_tmp82_fu_18817_p2);
assign sel_tmp85_fu_18835_p2 = (sel_tmp84_fu_18829_p2 & sel_tmp81_fu_18811_p2);
assign sel_tmp86_fu_18993_p3 = ((sel_tmp2241_demorgan_fu_18987_p2[0:0] === 1'b1) ? win_l1_V_1_load_3_2_phi_fu_13517_p8 : win_l1_V_1_load_4_phi_fu_12824_p8);
assign sel_tmp87_fu_19007_p2 = (sel_tmp2245_demorgan_fu_19001_p2 ^ 1'b1);
assign sel_tmp88_fu_19013_p2 = (sel_tmp2241_demorgan_fu_18987_p2 & sel_tmp87_fu_19007_p2);
assign sel_tmp89_fu_19019_p3 = ((sel_tmp88_fu_19013_p2[0:0] === 1'b1) ? win_l1_V_1_load_1_2_phi_fu_13055_p8 : sel_tmp86_fu_18993_p3);
assign sel_tmp90_fu_19039_p2 = (sel_tmp2251_demorgan_fu_19033_p2 ^ 1'b1);
assign sel_tmp91_fu_19045_p2 = (tmp_362_2_fu_18921_p2 & or_cond74_fu_18963_p2);
assign sel_tmp93_fu_19057_p2 = (tmp45_fu_19051_p2 | sel_tmp91_fu_19045_p2);
assign sel_tmp94_fu_19063_p2 = (sel_tmp93_fu_19057_p2 & sel_tmp90_fu_19039_p2);
assign sel_tmp95_fu_19217_p3 = ((sel_tmp2285_demorgan_fu_19211_p2[0:0] === 1'b1) ? win_l0_V_s_phi_fu_3882_p128 : win_l1_V_1_load_5_phi_fu_13748_p8);
assign sel_tmp96_fu_19231_p2 = (sel_tmp2289_demorgan_fu_19225_p2 ^ 1'b1);
assign sel_tmp97_fu_19237_p2 = (sel_tmp2285_demorgan_fu_19211_p2 & sel_tmp96_fu_19231_p2);
assign sel_tmp98_fu_19243_p3 = ((sel_tmp97_fu_19237_p2[0:0] === 1'b1) ? win_l1_V_1_load_1_3_phi_fu_13979_p8 : sel_tmp95_fu_19217_p3);
assign sel_tmp99_fu_19263_p2 = (sel_tmp2295_demorgan_fu_19257_p2 ^ 1'b1);
assign sel_tmp_fu_15224_p3 = ((sel_tmp2013_demorgan_fu_15218_p2[0:0] === 1'b1) ? call_ret_sp_sort_fu_14608_ap_return_5 : call_ret_sp_sort_fu_14608_ap_return_2);
assign temp_V_2_3_fu_16806_p3 = ((sel_tmp73_fu_16800_p2[0:0] === 1'b1) ? win_l1_V_load_5_3_phi_fu_1487_p8 : sel_tmp68_fu_16756_p3);
assign temp_V_2_3_win_l2_V_load_5_fu_17296_p3 = ((or_cond66_fu_17290_p2[0:0] === 1'b1) ? temp_V_2_3_reg_24411 : win_l2_V_load_5_reg_24385);
assign temp_V_4_3_fu_19293_p3 = ((sel_tmp103_fu_19287_p2[0:0] === 1'b1) ? win_l1_V_1_load_2_3_phi_fu_14210_p8 : sel_tmp98_fu_19243_p3);
assign temp_V_4_3_win_l2_V_1_load_2_fu_19463_p3 = ((or_cond84_fu_19457_p2[0:0] === 1'b1) ? temp_V_4_3_fu_19293_p3 : win_l2_V_1_load_2_fu_19069_p3);
assign tmp15_fu_15282_p2 = (or_cond57_fu_15170_p2 & sel_tmp2017_demorgan_fu_15232_p2);
assign tmp16_fu_16452_p2 = (tmp_328_1_fu_16406_p2 | tmp_323_1_fu_16394_p2);
assign tmp17_fu_16476_p2 = (or_cond52_fu_16364_p2 & sel_tmp2061_demorgan_fu_16426_p2);
assign tmp18_fu_16608_p2 = (tmp_328_2_fu_16562_p2 | tmp_323_2_fu_16550_p2);
assign tmp19_fu_16632_p2 = (or_cond55_fu_16520_p2 & sel_tmp2105_demorgan_fu_16582_p2);
assign tmp20_fu_16764_p2 = (tmp_328_3_fu_16718_p2 | tmp_323_3_fu_16706_p2);
assign tmp21_fu_16788_p2 = (or_cond58_fu_16676_p2 & sel_tmp2149_demorgan_fu_16738_p2);
assign tmp22_fu_17234_p2 = (tmp_14_fu_17224_p2 | tmp_15_fu_17229_p2);
assign tmp23_fu_17259_p2 = (tmp_17_fu_17251_p2 | tmp_18_fu_17255_p2);
assign tmp24_fu_17284_p2 = (tmp_20_fu_17276_p2 | tmp_21_fu_17280_p2);
assign tmp42_fu_18799_p2 = (tmp_385_1_fu_18753_p2 | tmp_380_1_fu_18741_p2);
assign tmp43_fu_18823_p2 = (or_cond70_fu_18711_p2 & sel_tmp2201_demorgan_fu_18773_p2);
assign tmp44_fu_19027_p2 = (tmp_385_2_fu_18981_p2 | tmp_380_2_fu_18969_p2);
assign tmp45_fu_19051_p2 = (or_cond73_fu_18939_p2 & sel_tmp2245_demorgan_fu_19001_p2);
assign tmp46_fu_19251_p2 = (tmp_385_3_fu_19205_p2 | tmp_380_3_fu_19193_p2);
assign tmp47_fu_19275_p2 = (or_cond76_fu_19163_p2 & sel_tmp2289_demorgan_fu_19225_p2);
assign tmp48_fu_19391_p2 = (tmp_28_fu_19379_p2 | tmp_29_fu_19385_p2);
assign tmp49_fu_19421_p2 = (tmp_31_fu_19409_p2 | tmp_32_fu_19415_p2);
assign tmp50_fu_19451_p2 = (tmp_34_fu_19439_p2 | tmp_35_fu_19445_p2);
assign tmp_14_fu_17224_p2 = ((win_l2_V_load_phi_fu_3713_p8 < win_l2_V_load_5_reg_24385) ? 1'b1 : 1'b0);
assign tmp_15_fu_17229_p2 = ((win_l2_V_load_phi_fu_3713_p8 < temp_V_2_3_reg_24411) ? 1'b1 : 1'b0);
assign tmp_16_fu_17246_p2 = ((win_l2_V_load_4_reg_24359 < win_l2_V_load_phi_fu_3713_p8) ? 1'b1 : 1'b0);
assign tmp_17_fu_17251_p2 = ((win_l2_V_load_4_reg_24359 < win_l2_V_load_5_reg_24385) ? 1'b1 : 1'b0);
assign tmp_18_fu_17255_p2 = ((win_l2_V_load_4_reg_24359 < temp_V_2_3_reg_24411) ? 1'b1 : 1'b0);
assign tmp_19_fu_17271_p2 = ((win_l2_V_load_5_reg_24385 < win_l2_V_load_phi_fu_3713_p8) ? 1'b1 : 1'b0);
assign tmp_208_fu_15152_p2 = ((call_ret_sp_sort_fu_14608_ap_return_3 > call_ret_sp_sort_fu_14608_ap_return_2) ? 1'b1 : 1'b0);
assign tmp_209_fu_15158_p2 = ((call_ret_sp_sort_fu_14608_ap_return_2 < call_ret_sp_sort_fu_14608_ap_return_4) ? 1'b1 : 1'b0);
assign tmp_20_fu_17276_p2 = ((win_l2_V_load_5_reg_24385 < win_l2_V_load_4_reg_24359) ? 1'b1 : 1'b0);
assign tmp_210_fu_15164_p2 = ((call_ret_sp_sort_fu_14608_ap_return_2 < call_ret_sp_sort_fu_14608_ap_return_5) ? 1'b1 : 1'b0);
assign tmp_211_fu_15176_p2 = ((call_ret_sp_sort_fu_14608_ap_return_3 < call_ret_sp_sort_fu_14608_ap_return_2) ? 1'b1 : 1'b0);
assign tmp_212_fu_15182_p2 = ((call_ret_sp_sort_fu_14608_ap_return_3 < call_ret_sp_sort_fu_14608_ap_return_4) ? 1'b1 : 1'b0);
assign tmp_213_fu_15188_p2 = ((call_ret_sp_sort_fu_14608_ap_return_3 < call_ret_sp_sort_fu_14608_ap_return_5) ? 1'b1 : 1'b0);
assign tmp_214_fu_15200_p2 = ((call_ret_sp_sort_fu_14608_ap_return_4 < call_ret_sp_sort_fu_14608_ap_return_2) ? 1'b1 : 1'b0);
assign tmp_215_fu_15206_p2 = ((call_ret_sp_sort_fu_14608_ap_return_4 < call_ret_sp_sort_fu_14608_ap_return_3) ? 1'b1 : 1'b0);
assign tmp_216_fu_15212_p2 = ((call_ret_sp_sort_fu_14608_ap_return_4 < call_ret_sp_sort_fu_14608_ap_return_5) ? 1'b1 : 1'b0);
assign tmp_217_fu_16910_p2 = ((win_l1_V_load_reg_24078 < ap_reg_phiprechg_win_l1_V_load_4_reg_1522pp0_it1) ? 1'b1 : 1'b0);
assign tmp_218_fu_16915_p2 = ((win_l1_V_load_reg_24078 < ap_reg_phiprechg_win_l1_V_load_5_reg_1576pp0_it1) ? 1'b1 : 1'b0);
assign tmp_219_fu_16920_p2 = ((win_l1_V_load_reg_24078 < ap_reg_phiprechg_win_l1_V_load_6_reg_1630pp0_it1) ? 1'b1 : 1'b0);
assign tmp_21_fu_17280_p2 = ((win_l2_V_load_5_reg_24385 < temp_V_2_3_reg_24411) ? 1'b1 : 1'b0);
assign tmp_220_fu_16931_p2 = ((ap_reg_phiprechg_win_l1_V_load_4_reg_1522pp0_it1 < win_l1_V_load_reg_24078) ? 1'b1 : 1'b0);
assign tmp_221_fu_16936_p2 = ((ap_reg_phiprechg_win_l1_V_load_4_reg_1522pp0_it1 < ap_reg_phiprechg_win_l1_V_load_5_reg_1576pp0_it1) ? 1'b1 : 1'b0);
assign tmp_222_fu_16942_p2 = ((ap_reg_phiprechg_win_l1_V_load_4_reg_1522pp0_it1 < ap_reg_phiprechg_win_l1_V_load_6_reg_1630pp0_it1) ? 1'b1 : 1'b0);
assign tmp_223_fu_16954_p2 = ((ap_reg_phiprechg_win_l1_V_load_5_reg_1576pp0_it1 < win_l1_V_load_reg_24078) ? 1'b1 : 1'b0);
assign tmp_224_fu_16959_p2 = ((ap_reg_phiprechg_win_l1_V_load_5_reg_1576pp0_it1 < ap_reg_phiprechg_win_l1_V_load_4_reg_1522pp0_it1) ? 1'b1 : 1'b0);
assign tmp_225_fu_16965_p2 = ((ap_reg_phiprechg_win_l1_V_load_5_reg_1576pp0_it1 < ap_reg_phiprechg_win_l1_V_load_6_reg_1630pp0_it1) ? 1'b1 : 1'b0);
assign tmp_226_fu_17403_p2 = ((win_l0_V_phi_fu_11922_p128 < win_l0_V_59_phi_fu_11788_p128) ? 1'b1 : 1'b0);
assign tmp_227_fu_17409_p2 = ((win_l0_V_phi_fu_11922_p128 < win_l0_V_2_phi_fu_11654_p128) ? 1'b1 : 1'b0);
assign tmp_228_fu_17415_p2 = ((win_l0_V_phi_fu_11922_p128 < win_l0_V_3_phi_fu_11520_p128) ? 1'b1 : 1'b0);
assign tmp_229_fu_17427_p2 = ((win_l0_V_59_phi_fu_11788_p128 < win_l0_V_phi_fu_11922_p128) ? 1'b1 : 1'b0);
assign tmp_230_fu_17433_p2 = ((win_l0_V_59_phi_fu_11788_p128 < win_l0_V_2_phi_fu_11654_p128) ? 1'b1 : 1'b0);
assign tmp_231_fu_17439_p2 = ((win_l0_V_59_phi_fu_11788_p128 < win_l0_V_3_phi_fu_11520_p128) ? 1'b1 : 1'b0);
assign tmp_232_fu_17451_p2 = ((win_l0_V_2_phi_fu_11654_p128 < win_l0_V_phi_fu_11922_p128) ? 1'b1 : 1'b0);
assign tmp_233_fu_17457_p2 = ((win_l0_V_2_phi_fu_11654_p128 < win_l0_V_59_phi_fu_11788_p128) ? 1'b1 : 1'b0);
assign tmp_234_fu_17463_p2 = ((win_l0_V_2_phi_fu_11654_p128 < win_l0_V_3_phi_fu_11520_p128) ? 1'b1 : 1'b0);
assign tmp_235_fu_18579_p2 = ((win_l1_V_1_load_phi_fu_12056_p8 < win_l1_V_1_load_1_phi_fu_12110_p8) ? 1'b1 : 1'b0);
assign tmp_236_fu_18585_p2 = ((win_l1_V_1_load_phi_fu_12056_p8 < win_l1_V_1_load_2_phi_fu_12164_p8) ? 1'b1 : 1'b0);
assign tmp_237_fu_18591_p2 = ((win_l1_V_1_load_phi_fu_12056_p8 < win_l1_V_1_load_3_phi_fu_12218_p8) ? 1'b1 : 1'b0);
assign tmp_238_fu_18603_p2 = ((win_l1_V_1_load_1_phi_fu_12110_p8 < win_l1_V_1_load_phi_fu_12056_p8) ? 1'b1 : 1'b0);
assign tmp_239_fu_18609_p2 = ((win_l1_V_1_load_1_phi_fu_12110_p8 < win_l1_V_1_load_2_phi_fu_12164_p8) ? 1'b1 : 1'b0);
assign tmp_23_fu_17367_p2 = ((win0_V_fu_17335_p3 == sorter_a_V_load29_phi_phi_fu_3746_p122) ? 1'b1 : 1'b0);
assign tmp_240_fu_18615_p2 = ((win_l1_V_1_load_1_phi_fu_12110_p8 < win_l1_V_1_load_3_phi_fu_12218_p8) ? 1'b1 : 1'b0);
assign tmp_241_fu_18627_p2 = ((win_l1_V_1_load_2_phi_fu_12164_p8 < win_l1_V_1_load_phi_fu_12056_p8) ? 1'b1 : 1'b0);
assign tmp_242_fu_18633_p2 = ((win_l1_V_1_load_2_phi_fu_12164_p8 < win_l1_V_1_load_1_phi_fu_12110_p8) ? 1'b1 : 1'b0);
assign tmp_243_fu_18639_p2 = ((win_l1_V_1_load_2_phi_fu_12164_p8 < win_l1_V_1_load_3_phi_fu_12218_p8) ? 1'b1 : 1'b0);
assign tmp_24_fu_17373_p2 = ((winid0_V_fu_17343_p6 == ap_const_lv7_0) ? 1'b1 : 1'b0);
assign tmp_26_fu_17379_p2 = (tmp_2772_fu_17361_p2 | ap_const_lv7_1);
assign tmp_2771_fu_17357_p1 = winid0_V_fu_17343_p6[5:0];
assign tmp_2772_fu_17361_p2 = winid0_V_fu_17343_p6 << ap_const_lv7_1;
assign tmp_2773_fu_19527_p2 = winid0_V_1_fu_19513_p6 << ap_const_lv7_1;
assign tmp_27_fu_19373_p2 = ((win_l2_V_1_load_phi_fu_14441_p8 < win_l2_V_1_load_1_fu_18841_p3) ? 1'b1 : 1'b0);
assign tmp_28_fu_19379_p2 = ((win_l2_V_1_load_phi_fu_14441_p8 < win_l2_V_1_load_2_fu_19069_p3) ? 1'b1 : 1'b0);
assign tmp_294_10_fu_16058_p2 = ((call_ret_sp_sort_fu_14608_ap_return_46 < call_ret_sp_sort_fu_14608_ap_return_47) ? 1'b1 : 1'b0);
assign tmp_294_11_fu_16130_p2 = ((call_ret_sp_sort_fu_14608_ap_return_50 < call_ret_sp_sort_fu_14608_ap_return_51) ? 1'b1 : 1'b0);
assign tmp_294_12_fu_16202_p2 = ((call_ret_sp_sort_fu_14608_ap_return_54 < call_ret_sp_sort_fu_14608_ap_return_55) ? 1'b1 : 1'b0);
assign tmp_294_13_fu_16274_p2 = ((call_ret_sp_sort_fu_14608_ap_return_58 < call_ret_sp_sort_fu_14608_ap_return_59) ? 1'b1 : 1'b0);
assign tmp_294_1_fu_15338_p2 = ((call_ret_sp_sort_fu_14608_ap_return_6 < call_ret_sp_sort_fu_14608_ap_return_7) ? 1'b1 : 1'b0);
assign tmp_294_2_fu_15410_p2 = ((call_ret_sp_sort_fu_14608_ap_return_10 < call_ret_sp_sort_fu_14608_ap_return_11) ? 1'b1 : 1'b0);
assign tmp_294_3_fu_15482_p2 = ((call_ret_sp_sort_fu_14608_ap_return_14 < call_ret_sp_sort_fu_14608_ap_return_15) ? 1'b1 : 1'b0);
assign tmp_294_4_fu_15554_p2 = ((call_ret_sp_sort_fu_14608_ap_return_18 < call_ret_sp_sort_fu_14608_ap_return_19) ? 1'b1 : 1'b0);
assign tmp_294_5_fu_15626_p2 = ((call_ret_sp_sort_fu_14608_ap_return_22 < call_ret_sp_sort_fu_14608_ap_return_23) ? 1'b1 : 1'b0);
assign tmp_294_6_fu_15698_p2 = ((call_ret_sp_sort_fu_14608_ap_return_26 < call_ret_sp_sort_fu_14608_ap_return_27) ? 1'b1 : 1'b0);
assign tmp_294_7_fu_15770_p2 = ((call_ret_sp_sort_fu_14608_ap_return_30 < call_ret_sp_sort_fu_14608_ap_return_31) ? 1'b1 : 1'b0);
assign tmp_294_8_fu_15842_p2 = ((call_ret_sp_sort_fu_14608_ap_return_34 < call_ret_sp_sort_fu_14608_ap_return_35) ? 1'b1 : 1'b0);
assign tmp_294_9_fu_15914_p2 = ((call_ret_sp_sort_fu_14608_ap_return_38 < call_ret_sp_sort_fu_14608_ap_return_39) ? 1'b1 : 1'b0);
assign tmp_294_s_fu_15986_p2 = ((call_ret_sp_sort_fu_14608_ap_return_42 < call_ret_sp_sort_fu_14608_ap_return_43) ? 1'b1 : 1'b0);
assign tmp_295_10_fu_16064_p2 = ((call_ret_sp_sort_fu_14608_ap_return_46 < call_ret_sp_sort_fu_14608_ap_return_48) ? 1'b1 : 1'b0);
assign tmp_295_11_fu_16136_p2 = ((call_ret_sp_sort_fu_14608_ap_return_50 < call_ret_sp_sort_fu_14608_ap_return_52) ? 1'b1 : 1'b0);
assign tmp_295_12_fu_16208_p2 = ((call_ret_sp_sort_fu_14608_ap_return_54 < call_ret_sp_sort_fu_14608_ap_return_56) ? 1'b1 : 1'b0);
assign tmp_295_13_fu_16280_p2 = ((call_ret_sp_sort_fu_14608_ap_return_58 < call_ret_sp_sort_fu_14608_ap_return_60) ? 1'b1 : 1'b0);
assign tmp_295_1_fu_15344_p2 = ((call_ret_sp_sort_fu_14608_ap_return_6 < call_ret_sp_sort_fu_14608_ap_return_8) ? 1'b1 : 1'b0);
assign tmp_295_2_fu_15416_p2 = ((call_ret_sp_sort_fu_14608_ap_return_10 < call_ret_sp_sort_fu_14608_ap_return_12) ? 1'b1 : 1'b0);
assign tmp_295_3_fu_15488_p2 = ((call_ret_sp_sort_fu_14608_ap_return_14 < call_ret_sp_sort_fu_14608_ap_return_16) ? 1'b1 : 1'b0);
assign tmp_295_4_fu_15560_p2 = ((call_ret_sp_sort_fu_14608_ap_return_18 < call_ret_sp_sort_fu_14608_ap_return_20) ? 1'b1 : 1'b0);
assign tmp_295_5_fu_15632_p2 = ((call_ret_sp_sort_fu_14608_ap_return_22 < call_ret_sp_sort_fu_14608_ap_return_24) ? 1'b1 : 1'b0);
assign tmp_295_6_fu_15704_p2 = ((call_ret_sp_sort_fu_14608_ap_return_26 < call_ret_sp_sort_fu_14608_ap_return_28) ? 1'b1 : 1'b0);
assign tmp_295_7_fu_15776_p2 = ((call_ret_sp_sort_fu_14608_ap_return_30 < call_ret_sp_sort_fu_14608_ap_return_32) ? 1'b1 : 1'b0);
assign tmp_295_8_fu_15848_p2 = ((call_ret_sp_sort_fu_14608_ap_return_34 < call_ret_sp_sort_fu_14608_ap_return_36) ? 1'b1 : 1'b0);
assign tmp_295_9_fu_15920_p2 = ((call_ret_sp_sort_fu_14608_ap_return_38 < call_ret_sp_sort_fu_14608_ap_return_40) ? 1'b1 : 1'b0);
assign tmp_295_s_fu_15992_p2 = ((call_ret_sp_sort_fu_14608_ap_return_42 < call_ret_sp_sort_fu_14608_ap_return_44) ? 1'b1 : 1'b0);
assign tmp_29_fu_19385_p2 = ((win_l2_V_1_load_phi_fu_14441_p8 < temp_V_4_3_fu_19293_p3) ? 1'b1 : 1'b0);
assign tmp_305_1_fu_16346_p2 = ((win_l1_V_load_4_1_phi_fu_1370_p8 > win_l1_V_load_1_phi_fu_1357_p8) ? 1'b1 : 1'b0);
assign tmp_305_2_fu_16502_p2 = ((win_l1_V_load_4_2_phi_fu_1422_p8 > win_l1_V_load_2_phi_fu_1409_p8) ? 1'b1 : 1'b0);
assign tmp_305_3_fu_16658_p2 = ((win_l1_V_load_4_3_phi_fu_1474_p8 > win_l1_V_load_3_phi_fu_1461_p8) ? 1'b1 : 1'b0);
assign tmp_306_10_fu_16070_p2 = ((call_ret_sp_sort_fu_14608_ap_return_46 < call_ret_sp_sort_fu_14608_ap_return_49) ? 1'b1 : 1'b0);
assign tmp_306_11_fu_16142_p2 = ((call_ret_sp_sort_fu_14608_ap_return_50 < call_ret_sp_sort_fu_14608_ap_return_53) ? 1'b1 : 1'b0);
assign tmp_306_12_fu_16214_p2 = ((call_ret_sp_sort_fu_14608_ap_return_54 < call_ret_sp_sort_fu_14608_ap_return_57) ? 1'b1 : 1'b0);
assign tmp_306_13_fu_16286_p2 = ((call_ret_sp_sort_fu_14608_ap_return_58 < call_ret_sp_sort_fu_14608_ap_return_61) ? 1'b1 : 1'b0);
assign tmp_306_1_fu_15350_p2 = ((call_ret_sp_sort_fu_14608_ap_return_6 < call_ret_sp_sort_fu_14608_ap_return_9) ? 1'b1 : 1'b0);
assign tmp_306_2_fu_15422_p2 = ((call_ret_sp_sort_fu_14608_ap_return_10 < call_ret_sp_sort_fu_14608_ap_return_13) ? 1'b1 : 1'b0);
assign tmp_306_3_fu_15494_p2 = ((call_ret_sp_sort_fu_14608_ap_return_14 < call_ret_sp_sort_fu_14608_ap_return_17) ? 1'b1 : 1'b0);
assign tmp_306_4_fu_15566_p2 = ((call_ret_sp_sort_fu_14608_ap_return_18 < call_ret_sp_sort_fu_14608_ap_return_21) ? 1'b1 : 1'b0);
assign tmp_306_5_fu_15638_p2 = ((call_ret_sp_sort_fu_14608_ap_return_22 < call_ret_sp_sort_fu_14608_ap_return_25) ? 1'b1 : 1'b0);
assign tmp_306_6_fu_15710_p2 = ((call_ret_sp_sort_fu_14608_ap_return_26 < call_ret_sp_sort_fu_14608_ap_return_29) ? 1'b1 : 1'b0);
assign tmp_306_7_fu_15782_p2 = ((call_ret_sp_sort_fu_14608_ap_return_30 < call_ret_sp_sort_fu_14608_ap_return_33) ? 1'b1 : 1'b0);
assign tmp_306_8_fu_15854_p2 = ((call_ret_sp_sort_fu_14608_ap_return_34 < call_ret_sp_sort_fu_14608_ap_return_37) ? 1'b1 : 1'b0);
assign tmp_306_9_fu_15926_p2 = ((call_ret_sp_sort_fu_14608_ap_return_38 < call_ret_sp_sort_fu_14608_ap_return_41) ? 1'b1 : 1'b0);
assign tmp_306_s_fu_15998_p2 = ((call_ret_sp_sort_fu_14608_ap_return_42 < call_ret_sp_sort_fu_14608_ap_return_45) ? 1'b1 : 1'b0);
assign tmp_308_1_fu_16352_p2 = ((win_l1_V_load_1_phi_fu_1357_p8 < win_l1_V_load_5_1_phi_fu_1383_p8) ? 1'b1 : 1'b0);
assign tmp_308_2_fu_16508_p2 = ((win_l1_V_load_2_phi_fu_1409_p8 < win_l1_V_load_5_2_phi_fu_1435_p8) ? 1'b1 : 1'b0);
assign tmp_308_3_fu_16664_p2 = ((win_l1_V_load_3_phi_fu_1461_p8 < win_l1_V_load_5_3_phi_fu_1487_p8) ? 1'b1 : 1'b0);
assign tmp_309_10_fu_16082_p2 = ((call_ret_sp_sort_fu_14608_ap_return_47 < call_ret_sp_sort_fu_14608_ap_return_46) ? 1'b1 : 1'b0);
assign tmp_309_11_fu_16154_p2 = ((call_ret_sp_sort_fu_14608_ap_return_51 < call_ret_sp_sort_fu_14608_ap_return_50) ? 1'b1 : 1'b0);
assign tmp_309_12_fu_16226_p2 = ((call_ret_sp_sort_fu_14608_ap_return_55 < call_ret_sp_sort_fu_14608_ap_return_54) ? 1'b1 : 1'b0);
assign tmp_309_13_fu_16298_p2 = ((call_ret_sp_sort_fu_14608_ap_return_59 < call_ret_sp_sort_fu_14608_ap_return_58) ? 1'b1 : 1'b0);
assign tmp_309_1_fu_15362_p2 = ((call_ret_sp_sort_fu_14608_ap_return_7 < call_ret_sp_sort_fu_14608_ap_return_6) ? 1'b1 : 1'b0);
assign tmp_309_2_fu_15434_p2 = ((call_ret_sp_sort_fu_14608_ap_return_11 < call_ret_sp_sort_fu_14608_ap_return_10) ? 1'b1 : 1'b0);
assign tmp_309_3_fu_15506_p2 = ((call_ret_sp_sort_fu_14608_ap_return_15 < call_ret_sp_sort_fu_14608_ap_return_14) ? 1'b1 : 1'b0);
assign tmp_309_4_fu_15578_p2 = ((call_ret_sp_sort_fu_14608_ap_return_19 < call_ret_sp_sort_fu_14608_ap_return_18) ? 1'b1 : 1'b0);
assign tmp_309_5_fu_15650_p2 = ((call_ret_sp_sort_fu_14608_ap_return_23 < call_ret_sp_sort_fu_14608_ap_return_22) ? 1'b1 : 1'b0);
assign tmp_309_6_fu_15722_p2 = ((call_ret_sp_sort_fu_14608_ap_return_27 < call_ret_sp_sort_fu_14608_ap_return_26) ? 1'b1 : 1'b0);
assign tmp_309_7_fu_15794_p2 = ((call_ret_sp_sort_fu_14608_ap_return_31 < call_ret_sp_sort_fu_14608_ap_return_30) ? 1'b1 : 1'b0);
assign tmp_309_8_fu_15866_p2 = ((call_ret_sp_sort_fu_14608_ap_return_35 < call_ret_sp_sort_fu_14608_ap_return_34) ? 1'b1 : 1'b0);
assign tmp_309_9_fu_15938_p2 = ((call_ret_sp_sort_fu_14608_ap_return_39 < call_ret_sp_sort_fu_14608_ap_return_38) ? 1'b1 : 1'b0);
assign tmp_309_s_fu_16010_p2 = ((call_ret_sp_sort_fu_14608_ap_return_43 < call_ret_sp_sort_fu_14608_ap_return_42) ? 1'b1 : 1'b0);
assign tmp_30_fu_19403_p2 = ((win_l2_V_1_load_1_fu_18841_p3 < win_l2_V_1_load_phi_fu_14441_p8) ? 1'b1 : 1'b0);
assign tmp_311_1_fu_16358_p2 = ((win_l1_V_load_1_phi_fu_1357_p8 < win_l1_V_load_6_1_phi_fu_1396_p8) ? 1'b1 : 1'b0);
assign tmp_311_2_fu_16514_p2 = ((win_l1_V_load_2_phi_fu_1409_p8 < win_l1_V_load_6_2_phi_fu_1448_p8) ? 1'b1 : 1'b0);
assign tmp_311_3_fu_16670_p2 = ((win_l1_V_load_3_phi_fu_1461_p8 < call_ret_sp_sort_fu_14608_ap_return_62) ? 1'b1 : 1'b0);
assign tmp_312_10_fu_16088_p2 = ((call_ret_sp_sort_fu_14608_ap_return_47 < call_ret_sp_sort_fu_14608_ap_return_48) ? 1'b1 : 1'b0);
assign tmp_312_11_fu_16160_p2 = ((call_ret_sp_sort_fu_14608_ap_return_51 < call_ret_sp_sort_fu_14608_ap_return_52) ? 1'b1 : 1'b0);
assign tmp_312_12_fu_16232_p2 = ((call_ret_sp_sort_fu_14608_ap_return_55 < call_ret_sp_sort_fu_14608_ap_return_56) ? 1'b1 : 1'b0);
assign tmp_312_13_fu_16304_p2 = ((call_ret_sp_sort_fu_14608_ap_return_59 < call_ret_sp_sort_fu_14608_ap_return_60) ? 1'b1 : 1'b0);
assign tmp_312_1_fu_15368_p2 = ((call_ret_sp_sort_fu_14608_ap_return_7 < call_ret_sp_sort_fu_14608_ap_return_8) ? 1'b1 : 1'b0);
assign tmp_312_2_fu_15440_p2 = ((call_ret_sp_sort_fu_14608_ap_return_11 < call_ret_sp_sort_fu_14608_ap_return_12) ? 1'b1 : 1'b0);
assign tmp_312_3_fu_15512_p2 = ((call_ret_sp_sort_fu_14608_ap_return_15 < call_ret_sp_sort_fu_14608_ap_return_16) ? 1'b1 : 1'b0);
assign tmp_312_4_fu_15584_p2 = ((call_ret_sp_sort_fu_14608_ap_return_19 < call_ret_sp_sort_fu_14608_ap_return_20) ? 1'b1 : 1'b0);
assign tmp_312_5_fu_15656_p2 = ((call_ret_sp_sort_fu_14608_ap_return_23 < call_ret_sp_sort_fu_14608_ap_return_24) ? 1'b1 : 1'b0);
assign tmp_312_6_fu_15728_p2 = ((call_ret_sp_sort_fu_14608_ap_return_27 < call_ret_sp_sort_fu_14608_ap_return_28) ? 1'b1 : 1'b0);
assign tmp_312_7_fu_15800_p2 = ((call_ret_sp_sort_fu_14608_ap_return_31 < call_ret_sp_sort_fu_14608_ap_return_32) ? 1'b1 : 1'b0);
assign tmp_312_8_fu_15872_p2 = ((call_ret_sp_sort_fu_14608_ap_return_35 < call_ret_sp_sort_fu_14608_ap_return_36) ? 1'b1 : 1'b0);
assign tmp_312_9_fu_15944_p2 = ((call_ret_sp_sort_fu_14608_ap_return_39 < call_ret_sp_sort_fu_14608_ap_return_40) ? 1'b1 : 1'b0);
assign tmp_312_s_fu_16016_p2 = ((call_ret_sp_sort_fu_14608_ap_return_43 < call_ret_sp_sort_fu_14608_ap_return_44) ? 1'b1 : 1'b0);
assign tmp_314_1_fu_16370_p2 = ((win_l1_V_load_4_1_phi_fu_1370_p8 < win_l1_V_load_1_phi_fu_1357_p8) ? 1'b1 : 1'b0);
assign tmp_314_2_fu_16526_p2 = ((win_l1_V_load_4_2_phi_fu_1422_p8 < win_l1_V_load_2_phi_fu_1409_p8) ? 1'b1 : 1'b0);
assign tmp_314_3_fu_16682_p2 = ((win_l1_V_load_4_3_phi_fu_1474_p8 < win_l1_V_load_3_phi_fu_1461_p8) ? 1'b1 : 1'b0);
assign tmp_315_10_fu_16094_p2 = ((call_ret_sp_sort_fu_14608_ap_return_47 < call_ret_sp_sort_fu_14608_ap_return_49) ? 1'b1 : 1'b0);
assign tmp_315_11_fu_16166_p2 = ((call_ret_sp_sort_fu_14608_ap_return_51 < call_ret_sp_sort_fu_14608_ap_return_53) ? 1'b1 : 1'b0);
assign tmp_315_12_fu_16238_p2 = ((call_ret_sp_sort_fu_14608_ap_return_55 < call_ret_sp_sort_fu_14608_ap_return_57) ? 1'b1 : 1'b0);
assign tmp_315_13_fu_16310_p2 = ((call_ret_sp_sort_fu_14608_ap_return_59 < call_ret_sp_sort_fu_14608_ap_return_61) ? 1'b1 : 1'b0);
assign tmp_315_1_fu_15374_p2 = ((call_ret_sp_sort_fu_14608_ap_return_7 < call_ret_sp_sort_fu_14608_ap_return_9) ? 1'b1 : 1'b0);
assign tmp_315_2_fu_15446_p2 = ((call_ret_sp_sort_fu_14608_ap_return_11 < call_ret_sp_sort_fu_14608_ap_return_13) ? 1'b1 : 1'b0);
assign tmp_315_3_fu_15518_p2 = ((call_ret_sp_sort_fu_14608_ap_return_15 < call_ret_sp_sort_fu_14608_ap_return_17) ? 1'b1 : 1'b0);
assign tmp_315_4_fu_15590_p2 = ((call_ret_sp_sort_fu_14608_ap_return_19 < call_ret_sp_sort_fu_14608_ap_return_21) ? 1'b1 : 1'b0);
assign tmp_315_5_fu_15662_p2 = ((call_ret_sp_sort_fu_14608_ap_return_23 < call_ret_sp_sort_fu_14608_ap_return_25) ? 1'b1 : 1'b0);
assign tmp_315_6_fu_15734_p2 = ((call_ret_sp_sort_fu_14608_ap_return_27 < call_ret_sp_sort_fu_14608_ap_return_29) ? 1'b1 : 1'b0);
assign tmp_315_7_fu_15806_p2 = ((call_ret_sp_sort_fu_14608_ap_return_31 < call_ret_sp_sort_fu_14608_ap_return_33) ? 1'b1 : 1'b0);
assign tmp_315_8_fu_15878_p2 = ((call_ret_sp_sort_fu_14608_ap_return_35 < call_ret_sp_sort_fu_14608_ap_return_37) ? 1'b1 : 1'b0);
assign tmp_315_9_fu_15950_p2 = ((call_ret_sp_sort_fu_14608_ap_return_39 < call_ret_sp_sort_fu_14608_ap_return_41) ? 1'b1 : 1'b0);
assign tmp_315_s_fu_16022_p2 = ((call_ret_sp_sort_fu_14608_ap_return_43 < call_ret_sp_sort_fu_14608_ap_return_45) ? 1'b1 : 1'b0);
assign tmp_317_1_fu_16376_p2 = ((win_l1_V_load_4_1_phi_fu_1370_p8 < win_l1_V_load_5_1_phi_fu_1383_p8) ? 1'b1 : 1'b0);
assign tmp_317_2_fu_16532_p2 = ((win_l1_V_load_4_2_phi_fu_1422_p8 < win_l1_V_load_5_2_phi_fu_1435_p8) ? 1'b1 : 1'b0);
assign tmp_317_3_fu_16688_p2 = ((win_l1_V_load_4_3_phi_fu_1474_p8 < win_l1_V_load_5_3_phi_fu_1487_p8) ? 1'b1 : 1'b0);
assign tmp_318_10_fu_16106_p2 = ((call_ret_sp_sort_fu_14608_ap_return_48 < call_ret_sp_sort_fu_14608_ap_return_46) ? 1'b1 : 1'b0);
assign tmp_318_11_fu_16178_p2 = ((call_ret_sp_sort_fu_14608_ap_return_52 < call_ret_sp_sort_fu_14608_ap_return_50) ? 1'b1 : 1'b0);
assign tmp_318_12_fu_16250_p2 = ((call_ret_sp_sort_fu_14608_ap_return_56 < call_ret_sp_sort_fu_14608_ap_return_54) ? 1'b1 : 1'b0);
assign tmp_318_13_fu_16322_p2 = ((call_ret_sp_sort_fu_14608_ap_return_60 < call_ret_sp_sort_fu_14608_ap_return_58) ? 1'b1 : 1'b0);
assign tmp_318_1_fu_15386_p2 = ((call_ret_sp_sort_fu_14608_ap_return_8 < call_ret_sp_sort_fu_14608_ap_return_6) ? 1'b1 : 1'b0);
assign tmp_318_2_fu_15458_p2 = ((call_ret_sp_sort_fu_14608_ap_return_12 < call_ret_sp_sort_fu_14608_ap_return_10) ? 1'b1 : 1'b0);
assign tmp_318_3_fu_15530_p2 = ((call_ret_sp_sort_fu_14608_ap_return_16 < call_ret_sp_sort_fu_14608_ap_return_14) ? 1'b1 : 1'b0);
assign tmp_318_4_fu_15602_p2 = ((call_ret_sp_sort_fu_14608_ap_return_20 < call_ret_sp_sort_fu_14608_ap_return_18) ? 1'b1 : 1'b0);
assign tmp_318_5_fu_15674_p2 = ((call_ret_sp_sort_fu_14608_ap_return_24 < call_ret_sp_sort_fu_14608_ap_return_22) ? 1'b1 : 1'b0);
assign tmp_318_6_fu_15746_p2 = ((call_ret_sp_sort_fu_14608_ap_return_28 < call_ret_sp_sort_fu_14608_ap_return_26) ? 1'b1 : 1'b0);
assign tmp_318_7_fu_15818_p2 = ((call_ret_sp_sort_fu_14608_ap_return_32 < call_ret_sp_sort_fu_14608_ap_return_30) ? 1'b1 : 1'b0);
assign tmp_318_8_fu_15890_p2 = ((call_ret_sp_sort_fu_14608_ap_return_36 < call_ret_sp_sort_fu_14608_ap_return_34) ? 1'b1 : 1'b0);
assign tmp_318_9_fu_15962_p2 = ((call_ret_sp_sort_fu_14608_ap_return_40 < call_ret_sp_sort_fu_14608_ap_return_38) ? 1'b1 : 1'b0);
assign tmp_318_s_fu_16034_p2 = ((call_ret_sp_sort_fu_14608_ap_return_44 < call_ret_sp_sort_fu_14608_ap_return_42) ? 1'b1 : 1'b0);
assign tmp_31_fu_19409_p2 = ((win_l2_V_1_load_1_fu_18841_p3 < win_l2_V_1_load_2_fu_19069_p3) ? 1'b1 : 1'b0);
assign tmp_320_1_fu_16382_p2 = ((win_l1_V_load_4_1_phi_fu_1370_p8 < win_l1_V_load_6_1_phi_fu_1396_p8) ? 1'b1 : 1'b0);
assign tmp_320_2_fu_16538_p2 = ((win_l1_V_load_4_2_phi_fu_1422_p8 < win_l1_V_load_6_2_phi_fu_1448_p8) ? 1'b1 : 1'b0);
assign tmp_320_3_fu_16694_p2 = ((win_l1_V_load_4_3_phi_fu_1474_p8 < call_ret_sp_sort_fu_14608_ap_return_62) ? 1'b1 : 1'b0);
assign tmp_321_10_fu_16112_p2 = ((call_ret_sp_sort_fu_14608_ap_return_48 < call_ret_sp_sort_fu_14608_ap_return_47) ? 1'b1 : 1'b0);
assign tmp_321_11_fu_16184_p2 = ((call_ret_sp_sort_fu_14608_ap_return_52 < call_ret_sp_sort_fu_14608_ap_return_51) ? 1'b1 : 1'b0);
assign tmp_321_12_fu_16256_p2 = ((call_ret_sp_sort_fu_14608_ap_return_56 < call_ret_sp_sort_fu_14608_ap_return_55) ? 1'b1 : 1'b0);
assign tmp_321_13_fu_16328_p2 = ((call_ret_sp_sort_fu_14608_ap_return_60 < call_ret_sp_sort_fu_14608_ap_return_59) ? 1'b1 : 1'b0);
assign tmp_321_1_fu_15392_p2 = ((call_ret_sp_sort_fu_14608_ap_return_8 < call_ret_sp_sort_fu_14608_ap_return_7) ? 1'b1 : 1'b0);
assign tmp_321_2_fu_15464_p2 = ((call_ret_sp_sort_fu_14608_ap_return_12 < call_ret_sp_sort_fu_14608_ap_return_11) ? 1'b1 : 1'b0);
assign tmp_321_3_fu_15536_p2 = ((call_ret_sp_sort_fu_14608_ap_return_16 < call_ret_sp_sort_fu_14608_ap_return_15) ? 1'b1 : 1'b0);
assign tmp_321_4_fu_15608_p2 = ((call_ret_sp_sort_fu_14608_ap_return_20 < call_ret_sp_sort_fu_14608_ap_return_19) ? 1'b1 : 1'b0);
assign tmp_321_5_fu_15680_p2 = ((call_ret_sp_sort_fu_14608_ap_return_24 < call_ret_sp_sort_fu_14608_ap_return_23) ? 1'b1 : 1'b0);
assign tmp_321_6_fu_15752_p2 = ((call_ret_sp_sort_fu_14608_ap_return_28 < call_ret_sp_sort_fu_14608_ap_return_27) ? 1'b1 : 1'b0);
assign tmp_321_7_fu_15824_p2 = ((call_ret_sp_sort_fu_14608_ap_return_32 < call_ret_sp_sort_fu_14608_ap_return_31) ? 1'b1 : 1'b0);
assign tmp_321_8_fu_15896_p2 = ((call_ret_sp_sort_fu_14608_ap_return_36 < call_ret_sp_sort_fu_14608_ap_return_35) ? 1'b1 : 1'b0);
assign tmp_321_9_fu_15968_p2 = ((call_ret_sp_sort_fu_14608_ap_return_40 < call_ret_sp_sort_fu_14608_ap_return_39) ? 1'b1 : 1'b0);
assign tmp_321_s_fu_16040_p2 = ((call_ret_sp_sort_fu_14608_ap_return_44 < call_ret_sp_sort_fu_14608_ap_return_43) ? 1'b1 : 1'b0);
assign tmp_323_1_fu_16394_p2 = ((win_l1_V_load_5_1_phi_fu_1383_p8 < win_l1_V_load_1_phi_fu_1357_p8) ? 1'b1 : 1'b0);
assign tmp_323_2_fu_16550_p2 = ((win_l1_V_load_5_2_phi_fu_1435_p8 < win_l1_V_load_2_phi_fu_1409_p8) ? 1'b1 : 1'b0);
assign tmp_323_3_fu_16706_p2 = ((win_l1_V_load_5_3_phi_fu_1487_p8 < win_l1_V_load_3_phi_fu_1461_p8) ? 1'b1 : 1'b0);
assign tmp_324_10_fu_16118_p2 = ((call_ret_sp_sort_fu_14608_ap_return_48 < call_ret_sp_sort_fu_14608_ap_return_49) ? 1'b1 : 1'b0);
assign tmp_324_11_fu_16190_p2 = ((call_ret_sp_sort_fu_14608_ap_return_52 < call_ret_sp_sort_fu_14608_ap_return_53) ? 1'b1 : 1'b0);
assign tmp_324_12_fu_16262_p2 = ((call_ret_sp_sort_fu_14608_ap_return_56 < call_ret_sp_sort_fu_14608_ap_return_57) ? 1'b1 : 1'b0);
assign tmp_324_13_fu_16334_p2 = ((call_ret_sp_sort_fu_14608_ap_return_60 < call_ret_sp_sort_fu_14608_ap_return_61) ? 1'b1 : 1'b0);
assign tmp_324_1_fu_15398_p2 = ((call_ret_sp_sort_fu_14608_ap_return_8 < call_ret_sp_sort_fu_14608_ap_return_9) ? 1'b1 : 1'b0);
assign tmp_324_2_fu_15470_p2 = ((call_ret_sp_sort_fu_14608_ap_return_12 < call_ret_sp_sort_fu_14608_ap_return_13) ? 1'b1 : 1'b0);
assign tmp_324_3_fu_15542_p2 = ((call_ret_sp_sort_fu_14608_ap_return_16 < call_ret_sp_sort_fu_14608_ap_return_17) ? 1'b1 : 1'b0);
assign tmp_324_4_fu_15614_p2 = ((call_ret_sp_sort_fu_14608_ap_return_20 < call_ret_sp_sort_fu_14608_ap_return_21) ? 1'b1 : 1'b0);
assign tmp_324_5_fu_15686_p2 = ((call_ret_sp_sort_fu_14608_ap_return_24 < call_ret_sp_sort_fu_14608_ap_return_25) ? 1'b1 : 1'b0);
assign tmp_324_6_fu_15758_p2 = ((call_ret_sp_sort_fu_14608_ap_return_28 < call_ret_sp_sort_fu_14608_ap_return_29) ? 1'b1 : 1'b0);
assign tmp_324_7_fu_15830_p2 = ((call_ret_sp_sort_fu_14608_ap_return_32 < call_ret_sp_sort_fu_14608_ap_return_33) ? 1'b1 : 1'b0);
assign tmp_324_8_fu_15902_p2 = ((call_ret_sp_sort_fu_14608_ap_return_36 < call_ret_sp_sort_fu_14608_ap_return_37) ? 1'b1 : 1'b0);
assign tmp_324_9_fu_15974_p2 = ((call_ret_sp_sort_fu_14608_ap_return_40 < call_ret_sp_sort_fu_14608_ap_return_41) ? 1'b1 : 1'b0);
assign tmp_324_s_fu_16046_p2 = ((call_ret_sp_sort_fu_14608_ap_return_44 < call_ret_sp_sort_fu_14608_ap_return_45) ? 1'b1 : 1'b0);
assign tmp_326_1_fu_16400_p2 = ((win_l1_V_load_5_1_phi_fu_1383_p8 < win_l1_V_load_4_1_phi_fu_1370_p8) ? 1'b1 : 1'b0);
assign tmp_326_2_fu_16556_p2 = ((win_l1_V_load_5_2_phi_fu_1435_p8 < win_l1_V_load_4_2_phi_fu_1422_p8) ? 1'b1 : 1'b0);
assign tmp_326_3_fu_16712_p2 = ((win_l1_V_load_5_3_phi_fu_1487_p8 < win_l1_V_load_4_3_phi_fu_1474_p8) ? 1'b1 : 1'b0);
assign tmp_328_1_fu_16406_p2 = ((win_l1_V_load_5_1_phi_fu_1383_p8 < win_l1_V_load_6_1_phi_fu_1396_p8) ? 1'b1 : 1'b0);
assign tmp_328_2_fu_16562_p2 = ((win_l1_V_load_5_2_phi_fu_1435_p8 < win_l1_V_load_6_2_phi_fu_1448_p8) ? 1'b1 : 1'b0);
assign tmp_328_3_fu_16718_p2 = ((win_l1_V_load_5_3_phi_fu_1487_p8 < call_ret_sp_sort_fu_14608_ap_return_62) ? 1'b1 : 1'b0);
assign tmp_32_fu_19415_p2 = ((win_l2_V_1_load_1_fu_18841_p3 < temp_V_4_3_fu_19293_p3) ? 1'b1 : 1'b0);
assign tmp_33_fu_19433_p2 = ((win_l2_V_1_load_2_fu_19069_p3 < win_l2_V_1_load_phi_fu_14441_p8) ? 1'b1 : 1'b0);
assign tmp_34_fu_19439_p2 = ((win_l2_V_1_load_2_fu_19069_p3 < win_l2_V_1_load_1_fu_18841_p3) ? 1'b1 : 1'b0);
assign tmp_351_10_fu_18263_p2 = ((win_l0_V_44_phi_fu_6026_p128 < win_l0_V_45_phi_fu_5892_p128) ? 1'b1 : 1'b0);
assign tmp_351_11_fu_18339_p2 = ((win_l0_V_48_phi_fu_5490_p128 < win_l0_V_49_phi_fu_5356_p128) ? 1'b1 : 1'b0);
assign tmp_351_12_fu_18419_p2 = ((win_l0_V_52_phi_fu_4954_p128 < win_l0_V_53_phi_fu_4820_p128) ? 1'b1 : 1'b0);
assign tmp_351_13_fu_18499_p2 = ((win_l0_V_56_phi_fu_4418_p128 < win_l0_V_57_phi_fu_4284_p128) ? 1'b1 : 1'b0);
assign tmp_351_1_fu_17483_p2 = ((win_l0_V_4_phi_fu_11386_p128 < win_l0_V_5_phi_fu_11252_p128) ? 1'b1 : 1'b0);
assign tmp_351_2_fu_17563_p2 = ((win_l0_V_8_phi_fu_10850_p128 < win_l0_V_9_phi_fu_10716_p128) ? 1'b1 : 1'b0);
assign tmp_351_3_fu_17643_p2 = ((win_l0_V_12_phi_fu_10314_p128 < win_l0_V_13_phi_fu_10180_p128) ? 1'b1 : 1'b0);
assign tmp_351_4_fu_17723_p2 = ((win_l0_V_16_phi_fu_9778_p128 < win_l0_V_17_phi_fu_9644_p128) ? 1'b1 : 1'b0);
assign tmp_351_5_fu_17799_p2 = ((win_l0_V_20_phi_fu_9242_p128 < win_l0_V_21_phi_fu_9108_p128) ? 1'b1 : 1'b0);
assign tmp_351_6_fu_17875_p2 = ((win_l0_V_24_phi_fu_8706_p128 < win_l0_V_25_phi_fu_8572_p128) ? 1'b1 : 1'b0);
assign tmp_351_7_fu_17955_p2 = ((win_l0_V_28_phi_fu_8170_p128 < win_l0_V_29_phi_fu_8036_p128) ? 1'b1 : 1'b0);
assign tmp_351_8_fu_18035_p2 = ((win_l0_V_32_phi_fu_7634_p128 < win_l0_V_33_phi_fu_7500_p128) ? 1'b1 : 1'b0);
assign tmp_351_9_fu_18111_p2 = ((win_l0_V_36_phi_fu_7098_p128 < win_l0_V_37_phi_fu_6964_p128) ? 1'b1 : 1'b0);
assign tmp_351_s_fu_18187_p2 = ((win_l0_V_40_phi_fu_6562_p128 < win_l0_V_41_phi_fu_6428_p128) ? 1'b1 : 1'b0);
assign tmp_352_10_fu_18269_p2 = ((win_l0_V_44_phi_fu_6026_p128 < win_l0_V_46_phi_fu_5758_p128) ? 1'b1 : 1'b0);
assign tmp_352_11_fu_18345_p2 = ((win_l0_V_48_phi_fu_5490_p128 < win_l0_V_50_phi_fu_5222_p128) ? 1'b1 : 1'b0);
assign tmp_352_12_fu_18425_p2 = ((win_l0_V_52_phi_fu_4954_p128 < win_l0_V_54_phi_fu_4686_p128) ? 1'b1 : 1'b0);
assign tmp_352_13_fu_18505_p2 = ((win_l0_V_56_phi_fu_4418_p128 < win_l0_V_58_phi_fu_4150_p128) ? 1'b1 : 1'b0);
assign tmp_352_1_fu_17489_p2 = ((win_l0_V_4_phi_fu_11386_p128 < win_l0_V_6_phi_fu_11118_p128) ? 1'b1 : 1'b0);
assign tmp_352_2_fu_17569_p2 = ((win_l0_V_8_phi_fu_10850_p128 < win_l0_V_10_phi_fu_10582_p128) ? 1'b1 : 1'b0);
assign tmp_352_3_fu_17649_p2 = ((win_l0_V_12_phi_fu_10314_p128 < win_l0_V_14_phi_fu_10046_p128) ? 1'b1 : 1'b0);
assign tmp_352_4_fu_17729_p2 = ((win_l0_V_16_phi_fu_9778_p128 < win_l0_V_18_phi_fu_9510_p128) ? 1'b1 : 1'b0);
assign tmp_352_5_fu_17805_p2 = ((win_l0_V_20_phi_fu_9242_p128 < win_l0_V_22_phi_fu_8974_p128) ? 1'b1 : 1'b0);
assign tmp_352_6_fu_17881_p2 = ((win_l0_V_24_phi_fu_8706_p128 < win_l0_V_26_phi_fu_8438_p128) ? 1'b1 : 1'b0);
assign tmp_352_7_fu_17961_p2 = ((win_l0_V_28_phi_fu_8170_p128 < win_l0_V_30_phi_fu_7902_p128) ? 1'b1 : 1'b0);
assign tmp_352_8_fu_18041_p2 = ((win_l0_V_32_phi_fu_7634_p128 < win_l0_V_34_phi_fu_7366_p128) ? 1'b1 : 1'b0);
assign tmp_352_9_fu_18117_p2 = ((win_l0_V_36_phi_fu_7098_p128 < win_l0_V_38_phi_fu_6830_p128) ? 1'b1 : 1'b0);
assign tmp_352_s_fu_18193_p2 = ((win_l0_V_40_phi_fu_6562_p128 < win_l0_V_42_phi_fu_6294_p128) ? 1'b1 : 1'b0);
assign tmp_35_fu_19445_p2 = ((win_l2_V_1_load_2_fu_19069_p3 < temp_V_4_3_fu_19293_p3) ? 1'b1 : 1'b0);
assign tmp_362_1_fu_18693_p2 = ((win_l1_V_1_load_1_1_phi_fu_12410_p8 > win_l1_V_1_load_s_phi_fu_12272_p8) ? 1'b1 : 1'b0);
assign tmp_362_2_fu_18921_p2 = ((win_l1_V_1_load_1_2_phi_fu_13055_p8 > win_l1_V_1_load_4_phi_fu_12824_p8) ? 1'b1 : 1'b0);
assign tmp_362_3_fu_19145_p2 = ((win_l1_V_1_load_1_3_phi_fu_13979_p8 > win_l1_V_1_load_5_phi_fu_13748_p8) ? 1'b1 : 1'b0);
assign tmp_363_10_fu_18275_p2 = ((win_l0_V_44_phi_fu_6026_p128 < win_l0_V_47_phi_fu_5624_p128) ? 1'b1 : 1'b0);
assign tmp_363_11_fu_18351_p2 = ((win_l0_V_48_phi_fu_5490_p128 < win_l0_V_51_phi_fu_5088_p128) ? 1'b1 : 1'b0);
assign tmp_363_12_fu_18431_p2 = ((win_l0_V_52_phi_fu_4954_p128 < win_l0_V_55_phi_fu_4552_p128) ? 1'b1 : 1'b0);
assign tmp_363_13_fu_18511_p2 = ((win_l0_V_56_phi_fu_4418_p128 < win_l0_V_1_phi_fu_4016_p128) ? 1'b1 : 1'b0);
assign tmp_363_1_fu_17495_p2 = ((win_l0_V_4_phi_fu_11386_p128 < win_l0_V_7_phi_fu_10984_p128) ? 1'b1 : 1'b0);
assign tmp_363_2_fu_17575_p2 = ((win_l0_V_8_phi_fu_10850_p128 < win_l0_V_11_phi_fu_10448_p128) ? 1'b1 : 1'b0);
assign tmp_363_3_fu_17655_p2 = ((win_l0_V_12_phi_fu_10314_p128 < win_l0_V_15_phi_fu_9912_p128) ? 1'b1 : 1'b0);
assign tmp_363_4_fu_17735_p2 = ((win_l0_V_16_phi_fu_9778_p128 < win_l0_V_19_phi_fu_9376_p128) ? 1'b1 : 1'b0);
assign tmp_363_5_fu_17811_p2 = ((win_l0_V_20_phi_fu_9242_p128 < win_l0_V_23_phi_fu_8840_p128) ? 1'b1 : 1'b0);
assign tmp_363_6_fu_17887_p2 = ((win_l0_V_24_phi_fu_8706_p128 < win_l0_V_27_phi_fu_8304_p128) ? 1'b1 : 1'b0);
assign tmp_363_7_fu_17967_p2 = ((win_l0_V_28_phi_fu_8170_p128 < win_l0_V_31_phi_fu_7768_p128) ? 1'b1 : 1'b0);
assign tmp_363_8_fu_18047_p2 = ((win_l0_V_32_phi_fu_7634_p128 < win_l0_V_35_phi_fu_7232_p128) ? 1'b1 : 1'b0);
assign tmp_363_9_fu_18123_p2 = ((win_l0_V_36_phi_fu_7098_p128 < win_l0_V_39_phi_fu_6696_p128) ? 1'b1 : 1'b0);
assign tmp_363_s_fu_18199_p2 = ((win_l0_V_40_phi_fu_6562_p128 < win_l0_V_43_phi_fu_6160_p128) ? 1'b1 : 1'b0);
assign tmp_365_1_fu_18699_p2 = ((win_l1_V_1_load_s_phi_fu_12272_p8 < win_l1_V_1_load_2_1_phi_fu_12548_p8) ? 1'b1 : 1'b0);
assign tmp_365_2_fu_18927_p2 = ((win_l1_V_1_load_4_phi_fu_12824_p8 < win_l1_V_1_load_2_2_phi_fu_13286_p8) ? 1'b1 : 1'b0);
assign tmp_365_3_fu_19151_p2 = ((win_l1_V_1_load_5_phi_fu_13748_p8 < win_l1_V_1_load_2_3_phi_fu_14210_p8) ? 1'b1 : 1'b0);
assign tmp_366_10_fu_18287_p2 = ((win_l0_V_45_phi_fu_5892_p128 < win_l0_V_44_phi_fu_6026_p128) ? 1'b1 : 1'b0);
assign tmp_366_11_fu_18363_p2 = ((win_l0_V_49_phi_fu_5356_p128 < win_l0_V_48_phi_fu_5490_p128) ? 1'b1 : 1'b0);
assign tmp_366_12_fu_18443_p2 = ((win_l0_V_53_phi_fu_4820_p128 < win_l0_V_52_phi_fu_4954_p128) ? 1'b1 : 1'b0);
assign tmp_366_13_fu_18523_p2 = ((win_l0_V_57_phi_fu_4284_p128 < win_l0_V_56_phi_fu_4418_p128) ? 1'b1 : 1'b0);
assign tmp_366_1_fu_17507_p2 = ((win_l0_V_5_phi_fu_11252_p128 < win_l0_V_4_phi_fu_11386_p128) ? 1'b1 : 1'b0);
assign tmp_366_2_fu_17587_p2 = ((win_l0_V_9_phi_fu_10716_p128 < win_l0_V_8_phi_fu_10850_p128) ? 1'b1 : 1'b0);
assign tmp_366_3_fu_17667_p2 = ((win_l0_V_13_phi_fu_10180_p128 < win_l0_V_12_phi_fu_10314_p128) ? 1'b1 : 1'b0);
assign tmp_366_4_fu_17747_p2 = ((win_l0_V_17_phi_fu_9644_p128 < win_l0_V_16_phi_fu_9778_p128) ? 1'b1 : 1'b0);
assign tmp_366_5_fu_17823_p2 = ((win_l0_V_21_phi_fu_9108_p128 < win_l0_V_20_phi_fu_9242_p128) ? 1'b1 : 1'b0);
assign tmp_366_6_fu_17899_p2 = ((win_l0_V_25_phi_fu_8572_p128 < win_l0_V_24_phi_fu_8706_p128) ? 1'b1 : 1'b0);
assign tmp_366_7_fu_17979_p2 = ((win_l0_V_29_phi_fu_8036_p128 < win_l0_V_28_phi_fu_8170_p128) ? 1'b1 : 1'b0);
assign tmp_366_8_fu_18059_p2 = ((win_l0_V_33_phi_fu_7500_p128 < win_l0_V_32_phi_fu_7634_p128) ? 1'b1 : 1'b0);
assign tmp_366_9_fu_18135_p2 = ((win_l0_V_37_phi_fu_6964_p128 < win_l0_V_36_phi_fu_7098_p128) ? 1'b1 : 1'b0);
assign tmp_366_s_fu_18211_p2 = ((win_l0_V_41_phi_fu_6428_p128 < win_l0_V_40_phi_fu_6562_p128) ? 1'b1 : 1'b0);
assign tmp_368_1_fu_18705_p2 = ((win_l1_V_1_load_s_phi_fu_12272_p8 < win_l1_V_1_load_3_1_phi_fu_12686_p8) ? 1'b1 : 1'b0);
assign tmp_368_2_fu_18933_p2 = ((win_l1_V_1_load_4_phi_fu_12824_p8 < win_l1_V_1_load_3_2_phi_fu_13517_p8) ? 1'b1 : 1'b0);
assign tmp_368_3_fu_19157_p2 = ((win_l1_V_1_load_5_phi_fu_13748_p8 < win_l0_V_s_phi_fu_3882_p128) ? 1'b1 : 1'b0);
assign tmp_369_10_fu_18293_p2 = ((win_l0_V_45_phi_fu_5892_p128 < win_l0_V_46_phi_fu_5758_p128) ? 1'b1 : 1'b0);
assign tmp_369_11_fu_18369_p2 = ((win_l0_V_49_phi_fu_5356_p128 < win_l0_V_50_phi_fu_5222_p128) ? 1'b1 : 1'b0);
assign tmp_369_12_fu_18449_p2 = ((win_l0_V_53_phi_fu_4820_p128 < win_l0_V_54_phi_fu_4686_p128) ? 1'b1 : 1'b0);
assign tmp_369_13_fu_18529_p2 = ((win_l0_V_57_phi_fu_4284_p128 < win_l0_V_58_phi_fu_4150_p128) ? 1'b1 : 1'b0);
assign tmp_369_1_fu_17513_p2 = ((win_l0_V_5_phi_fu_11252_p128 < win_l0_V_6_phi_fu_11118_p128) ? 1'b1 : 1'b0);
assign tmp_369_2_fu_17593_p2 = ((win_l0_V_9_phi_fu_10716_p128 < win_l0_V_10_phi_fu_10582_p128) ? 1'b1 : 1'b0);
assign tmp_369_3_fu_17673_p2 = ((win_l0_V_13_phi_fu_10180_p128 < win_l0_V_14_phi_fu_10046_p128) ? 1'b1 : 1'b0);
assign tmp_369_4_fu_17753_p2 = ((win_l0_V_17_phi_fu_9644_p128 < win_l0_V_18_phi_fu_9510_p128) ? 1'b1 : 1'b0);
assign tmp_369_5_fu_17829_p2 = ((win_l0_V_21_phi_fu_9108_p128 < win_l0_V_22_phi_fu_8974_p128) ? 1'b1 : 1'b0);
assign tmp_369_6_fu_17905_p2 = ((win_l0_V_25_phi_fu_8572_p128 < win_l0_V_26_phi_fu_8438_p128) ? 1'b1 : 1'b0);
assign tmp_369_7_fu_17985_p2 = ((win_l0_V_29_phi_fu_8036_p128 < win_l0_V_30_phi_fu_7902_p128) ? 1'b1 : 1'b0);
assign tmp_369_8_fu_18065_p2 = ((win_l0_V_33_phi_fu_7500_p128 < win_l0_V_34_phi_fu_7366_p128) ? 1'b1 : 1'b0);
assign tmp_369_9_fu_18141_p2 = ((win_l0_V_37_phi_fu_6964_p128 < win_l0_V_38_phi_fu_6830_p128) ? 1'b1 : 1'b0);
assign tmp_369_s_fu_18217_p2 = ((win_l0_V_41_phi_fu_6428_p128 < win_l0_V_42_phi_fu_6294_p128) ? 1'b1 : 1'b0);
assign tmp_371_1_fu_18717_p2 = ((win_l1_V_1_load_1_1_phi_fu_12410_p8 < win_l1_V_1_load_s_phi_fu_12272_p8) ? 1'b1 : 1'b0);
assign tmp_371_2_fu_18945_p2 = ((win_l1_V_1_load_1_2_phi_fu_13055_p8 < win_l1_V_1_load_4_phi_fu_12824_p8) ? 1'b1 : 1'b0);
assign tmp_371_3_fu_19169_p2 = ((win_l1_V_1_load_1_3_phi_fu_13979_p8 < win_l1_V_1_load_5_phi_fu_13748_p8) ? 1'b1 : 1'b0);
assign tmp_372_10_fu_18299_p2 = ((win_l0_V_45_phi_fu_5892_p128 < win_l0_V_47_phi_fu_5624_p128) ? 1'b1 : 1'b0);
assign tmp_372_11_fu_18375_p2 = ((win_l0_V_49_phi_fu_5356_p128 < win_l0_V_51_phi_fu_5088_p128) ? 1'b1 : 1'b0);
assign tmp_372_12_fu_18455_p2 = ((win_l0_V_53_phi_fu_4820_p128 < win_l0_V_55_phi_fu_4552_p128) ? 1'b1 : 1'b0);
assign tmp_372_13_fu_18535_p2 = ((win_l0_V_57_phi_fu_4284_p128 < win_l0_V_1_phi_fu_4016_p128) ? 1'b1 : 1'b0);
assign tmp_372_1_fu_17519_p2 = ((win_l0_V_5_phi_fu_11252_p128 < win_l0_V_7_phi_fu_10984_p128) ? 1'b1 : 1'b0);
assign tmp_372_2_fu_17599_p2 = ((win_l0_V_9_phi_fu_10716_p128 < win_l0_V_11_phi_fu_10448_p128) ? 1'b1 : 1'b0);
assign tmp_372_3_fu_17679_p2 = ((win_l0_V_13_phi_fu_10180_p128 < win_l0_V_15_phi_fu_9912_p128) ? 1'b1 : 1'b0);
assign tmp_372_4_fu_17759_p2 = ((win_l0_V_17_phi_fu_9644_p128 < win_l0_V_19_phi_fu_9376_p128) ? 1'b1 : 1'b0);
assign tmp_372_5_fu_17835_p2 = ((win_l0_V_21_phi_fu_9108_p128 < win_l0_V_23_phi_fu_8840_p128) ? 1'b1 : 1'b0);
assign tmp_372_6_fu_17911_p2 = ((win_l0_V_25_phi_fu_8572_p128 < win_l0_V_27_phi_fu_8304_p128) ? 1'b1 : 1'b0);
assign tmp_372_7_fu_17991_p2 = ((win_l0_V_29_phi_fu_8036_p128 < win_l0_V_31_phi_fu_7768_p128) ? 1'b1 : 1'b0);
assign tmp_372_8_fu_18071_p2 = ((win_l0_V_33_phi_fu_7500_p128 < win_l0_V_35_phi_fu_7232_p128) ? 1'b1 : 1'b0);
assign tmp_372_9_fu_18147_p2 = ((win_l0_V_37_phi_fu_6964_p128 < win_l0_V_39_phi_fu_6696_p128) ? 1'b1 : 1'b0);
assign tmp_372_s_fu_18223_p2 = ((win_l0_V_41_phi_fu_6428_p128 < win_l0_V_43_phi_fu_6160_p128) ? 1'b1 : 1'b0);
assign tmp_374_1_fu_18723_p2 = ((win_l1_V_1_load_1_1_phi_fu_12410_p8 < win_l1_V_1_load_2_1_phi_fu_12548_p8) ? 1'b1 : 1'b0);
assign tmp_374_2_fu_18951_p2 = ((win_l1_V_1_load_1_2_phi_fu_13055_p8 < win_l1_V_1_load_2_2_phi_fu_13286_p8) ? 1'b1 : 1'b0);
assign tmp_374_3_fu_19175_p2 = ((win_l1_V_1_load_1_3_phi_fu_13979_p8 < win_l1_V_1_load_2_3_phi_fu_14210_p8) ? 1'b1 : 1'b0);
assign tmp_375_10_fu_18311_p2 = ((win_l0_V_46_phi_fu_5758_p128 < win_l0_V_44_phi_fu_6026_p128) ? 1'b1 : 1'b0);
assign tmp_375_11_fu_18387_p2 = ((win_l0_V_50_phi_fu_5222_p128 < win_l0_V_48_phi_fu_5490_p128) ? 1'b1 : 1'b0);
assign tmp_375_12_fu_18467_p2 = ((win_l0_V_54_phi_fu_4686_p128 < win_l0_V_52_phi_fu_4954_p128) ? 1'b1 : 1'b0);
assign tmp_375_13_fu_18547_p2 = ((win_l0_V_58_phi_fu_4150_p128 < win_l0_V_56_phi_fu_4418_p128) ? 1'b1 : 1'b0);
assign tmp_375_1_fu_17531_p2 = ((win_l0_V_6_phi_fu_11118_p128 < win_l0_V_4_phi_fu_11386_p128) ? 1'b1 : 1'b0);
assign tmp_375_2_fu_17611_p2 = ((win_l0_V_10_phi_fu_10582_p128 < win_l0_V_8_phi_fu_10850_p128) ? 1'b1 : 1'b0);
assign tmp_375_3_fu_17691_p2 = ((win_l0_V_14_phi_fu_10046_p128 < win_l0_V_12_phi_fu_10314_p128) ? 1'b1 : 1'b0);
assign tmp_375_4_fu_17771_p2 = ((win_l0_V_18_phi_fu_9510_p128 < win_l0_V_16_phi_fu_9778_p128) ? 1'b1 : 1'b0);
assign tmp_375_5_fu_17847_p2 = ((win_l0_V_22_phi_fu_8974_p128 < win_l0_V_20_phi_fu_9242_p128) ? 1'b1 : 1'b0);
assign tmp_375_6_fu_17923_p2 = ((win_l0_V_26_phi_fu_8438_p128 < win_l0_V_24_phi_fu_8706_p128) ? 1'b1 : 1'b0);
assign tmp_375_7_fu_18003_p2 = ((win_l0_V_30_phi_fu_7902_p128 < win_l0_V_28_phi_fu_8170_p128) ? 1'b1 : 1'b0);
assign tmp_375_8_fu_18083_p2 = ((win_l0_V_34_phi_fu_7366_p128 < win_l0_V_32_phi_fu_7634_p128) ? 1'b1 : 1'b0);
assign tmp_375_9_fu_18159_p2 = ((win_l0_V_38_phi_fu_6830_p128 < win_l0_V_36_phi_fu_7098_p128) ? 1'b1 : 1'b0);
assign tmp_375_s_fu_18235_p2 = ((win_l0_V_42_phi_fu_6294_p128 < win_l0_V_40_phi_fu_6562_p128) ? 1'b1 : 1'b0);
assign tmp_377_1_fu_18729_p2 = ((win_l1_V_1_load_1_1_phi_fu_12410_p8 < win_l1_V_1_load_3_1_phi_fu_12686_p8) ? 1'b1 : 1'b0);
assign tmp_377_2_fu_18957_p2 = ((win_l1_V_1_load_1_2_phi_fu_13055_p8 < win_l1_V_1_load_3_2_phi_fu_13517_p8) ? 1'b1 : 1'b0);
assign tmp_377_3_fu_19181_p2 = ((win_l1_V_1_load_1_3_phi_fu_13979_p8 < win_l0_V_s_phi_fu_3882_p128) ? 1'b1 : 1'b0);
assign tmp_378_10_fu_18317_p2 = ((win_l0_V_46_phi_fu_5758_p128 < win_l0_V_45_phi_fu_5892_p128) ? 1'b1 : 1'b0);
assign tmp_378_11_fu_18393_p2 = ((win_l0_V_50_phi_fu_5222_p128 < win_l0_V_49_phi_fu_5356_p128) ? 1'b1 : 1'b0);
assign tmp_378_12_fu_18473_p2 = ((win_l0_V_54_phi_fu_4686_p128 < win_l0_V_53_phi_fu_4820_p128) ? 1'b1 : 1'b0);
assign tmp_378_13_fu_18553_p2 = ((win_l0_V_58_phi_fu_4150_p128 < win_l0_V_57_phi_fu_4284_p128) ? 1'b1 : 1'b0);
assign tmp_378_1_fu_17537_p2 = ((win_l0_V_6_phi_fu_11118_p128 < win_l0_V_5_phi_fu_11252_p128) ? 1'b1 : 1'b0);
assign tmp_378_2_fu_17617_p2 = ((win_l0_V_10_phi_fu_10582_p128 < win_l0_V_9_phi_fu_10716_p128) ? 1'b1 : 1'b0);
assign tmp_378_3_fu_17697_p2 = ((win_l0_V_14_phi_fu_10046_p128 < win_l0_V_13_phi_fu_10180_p128) ? 1'b1 : 1'b0);
assign tmp_378_4_fu_17777_p2 = ((win_l0_V_18_phi_fu_9510_p128 < win_l0_V_17_phi_fu_9644_p128) ? 1'b1 : 1'b0);
assign tmp_378_5_fu_17853_p2 = ((win_l0_V_22_phi_fu_8974_p128 < win_l0_V_21_phi_fu_9108_p128) ? 1'b1 : 1'b0);
assign tmp_378_6_fu_17929_p2 = ((win_l0_V_26_phi_fu_8438_p128 < win_l0_V_25_phi_fu_8572_p128) ? 1'b1 : 1'b0);
assign tmp_378_7_fu_18009_p2 = ((win_l0_V_30_phi_fu_7902_p128 < win_l0_V_29_phi_fu_8036_p128) ? 1'b1 : 1'b0);
assign tmp_378_8_fu_18089_p2 = ((win_l0_V_34_phi_fu_7366_p128 < win_l0_V_33_phi_fu_7500_p128) ? 1'b1 : 1'b0);
assign tmp_378_9_fu_18165_p2 = ((win_l0_V_38_phi_fu_6830_p128 < win_l0_V_37_phi_fu_6964_p128) ? 1'b1 : 1'b0);
assign tmp_378_s_fu_18241_p2 = ((win_l0_V_42_phi_fu_6294_p128 < win_l0_V_41_phi_fu_6428_p128) ? 1'b1 : 1'b0);
assign tmp_37_fu_19533_p2 = ((win0_V_1_fu_19505_p3 == sorter_a_V_load_14_phi_phi_fu_14475_p122) ? 1'b1 : 1'b0);
assign tmp_380_1_fu_18741_p2 = ((win_l1_V_1_load_2_1_phi_fu_12548_p8 < win_l1_V_1_load_s_phi_fu_12272_p8) ? 1'b1 : 1'b0);
assign tmp_380_2_fu_18969_p2 = ((win_l1_V_1_load_2_2_phi_fu_13286_p8 < win_l1_V_1_load_4_phi_fu_12824_p8) ? 1'b1 : 1'b0);
assign tmp_380_3_fu_19193_p2 = ((win_l1_V_1_load_2_3_phi_fu_14210_p8 < win_l1_V_1_load_5_phi_fu_13748_p8) ? 1'b1 : 1'b0);
assign tmp_381_10_fu_18323_p2 = ((win_l0_V_46_phi_fu_5758_p128 < win_l0_V_47_phi_fu_5624_p128) ? 1'b1 : 1'b0);
assign tmp_381_11_fu_18399_p2 = ((win_l0_V_50_phi_fu_5222_p128 < win_l0_V_51_phi_fu_5088_p128) ? 1'b1 : 1'b0);
assign tmp_381_12_fu_18479_p2 = ((win_l0_V_54_phi_fu_4686_p128 < win_l0_V_55_phi_fu_4552_p128) ? 1'b1 : 1'b0);
assign tmp_381_13_fu_18559_p2 = ((win_l0_V_58_phi_fu_4150_p128 < win_l0_V_1_phi_fu_4016_p128) ? 1'b1 : 1'b0);
assign tmp_381_1_fu_17543_p2 = ((win_l0_V_6_phi_fu_11118_p128 < win_l0_V_7_phi_fu_10984_p128) ? 1'b1 : 1'b0);
assign tmp_381_2_fu_17623_p2 = ((win_l0_V_10_phi_fu_10582_p128 < win_l0_V_11_phi_fu_10448_p128) ? 1'b1 : 1'b0);
assign tmp_381_3_fu_17703_p2 = ((win_l0_V_14_phi_fu_10046_p128 < win_l0_V_15_phi_fu_9912_p128) ? 1'b1 : 1'b0);
assign tmp_381_4_fu_17783_p2 = ((win_l0_V_18_phi_fu_9510_p128 < win_l0_V_19_phi_fu_9376_p128) ? 1'b1 : 1'b0);
assign tmp_381_5_fu_17859_p2 = ((win_l0_V_22_phi_fu_8974_p128 < win_l0_V_23_phi_fu_8840_p128) ? 1'b1 : 1'b0);
assign tmp_381_6_fu_17935_p2 = ((win_l0_V_26_phi_fu_8438_p128 < win_l0_V_27_phi_fu_8304_p128) ? 1'b1 : 1'b0);
assign tmp_381_7_fu_18015_p2 = ((win_l0_V_30_phi_fu_7902_p128 < win_l0_V_31_phi_fu_7768_p128) ? 1'b1 : 1'b0);
assign tmp_381_8_fu_18095_p2 = ((win_l0_V_34_phi_fu_7366_p128 < win_l0_V_35_phi_fu_7232_p128) ? 1'b1 : 1'b0);
assign tmp_381_9_fu_18171_p2 = ((win_l0_V_38_phi_fu_6830_p128 < win_l0_V_39_phi_fu_6696_p128) ? 1'b1 : 1'b0);
assign tmp_381_s_fu_18247_p2 = ((win_l0_V_42_phi_fu_6294_p128 < win_l0_V_43_phi_fu_6160_p128) ? 1'b1 : 1'b0);
assign tmp_383_1_fu_18747_p2 = ((win_l1_V_1_load_2_1_phi_fu_12548_p8 < win_l1_V_1_load_1_1_phi_fu_12410_p8) ? 1'b1 : 1'b0);
assign tmp_383_2_fu_18975_p2 = ((win_l1_V_1_load_2_2_phi_fu_13286_p8 < win_l1_V_1_load_1_2_phi_fu_13055_p8) ? 1'b1 : 1'b0);
assign tmp_383_3_fu_19199_p2 = ((win_l1_V_1_load_2_3_phi_fu_14210_p8 < win_l1_V_1_load_1_3_phi_fu_13979_p8) ? 1'b1 : 1'b0);
assign tmp_385_1_fu_18753_p2 = ((win_l1_V_1_load_2_1_phi_fu_12548_p8 < win_l1_V_1_load_3_1_phi_fu_12686_p8) ? 1'b1 : 1'b0);
assign tmp_385_2_fu_18981_p2 = ((win_l1_V_1_load_2_2_phi_fu_13286_p8 < win_l1_V_1_load_3_2_phi_fu_13517_p8) ? 1'b1 : 1'b0);
assign tmp_385_3_fu_19205_p2 = ((win_l1_V_1_load_2_3_phi_fu_14210_p8 < win_l0_V_s_phi_fu_3882_p128) ? 1'b1 : 1'b0);
assign tmp_38_fu_19539_p2 = ((winid0_V_1_fu_19513_p6 == ap_const_lv7_0) ? 1'b1 : 1'b0);
assign tmp_40_fu_19545_p2 = (tmp_2773_fu_19527_p2 | ap_const_lv7_1);
assign tmp_fu_15258_p2 = (tmp_216_fu_15212_p2 | tmp_214_fu_15200_p2);
assign tmp_s_fu_17219_p2 = ((win_l2_V_load_phi_fu_3713_p8 < win_l2_V_load_4_reg_24359) ? 1'b1 : 1'b0);
assign win0_V_1_fu_19505_p3 = ((sel_tmp105_fu_19483_p2[0:0] === 1'b1) ? temp_V_4_3_win_l2_V_1_load_2_fu_19463_p3 : sel_tmp106_fu_19497_p3);
assign win0_V_fu_17335_p3 = ((sel_tmp75_fu_17314_p2[0:0] === 1'b1) ? temp_V_2_3_win_l2_V_load_5_fu_17296_p3 : sel_tmp76_fu_17328_p3);
assign win_l1_V_load_fu_15300_p3 = ((sel_tmp46_fu_15294_p2[0:0] === 1'b1) ? call_ret_sp_sort_fu_14608_ap_return_4 : sel_tmp41_fu_15250_p3);
assign win_l2_V_1_load_1_fu_18841_p3 = ((sel_tmp85_fu_18835_p2[0:0] === 1'b1) ? win_l1_V_1_load_2_1_phi_fu_12548_p8 : sel_tmp80_fu_18791_p3);
assign win_l2_V_1_load_2_fu_19069_p3 = ((sel_tmp94_fu_19063_p2[0:0] === 1'b1) ? win_l1_V_1_load_2_2_phi_fu_13286_p8 : sel_tmp89_fu_19019_p3);
assign win_l2_V_load_4_fu_16494_p3 = ((sel_tmp55_fu_16488_p2[0:0] === 1'b1) ? win_l1_V_load_5_1_phi_fu_1383_p8 : sel_tmp50_fu_16444_p3);
assign win_l2_V_load_5_fu_16650_p3 = ((sel_tmp64_fu_16644_p2[0:0] === 1'b1) ? win_l1_V_load_5_2_phi_fu_1435_p8 : sel_tmp59_fu_16600_p3);
assign winid0_V_1_fu_19513_p5 = ((sel_tmp105_fu_19483_p2[0:0] === 1'b1) ? phitmp1_fu_19471_p3 : sel_tmp104_fu_19479_p1);
assign winid0_V_fu_17343_p5 = ((sel_tmp75_fu_17314_p2[0:0] === 1'b1) ? phitmp_fu_17302_p3 : sel_tmp74_fu_17310_p1);
endmodule //sp_best3
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__SDFXTP_BEHAVIORAL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hvl__udp_dff_p_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hvl__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign cond1 = ( SCE_delayed === 1'b0 );
assign cond2 = ( SCE_delayed === 1'b1 );
assign cond3 = ( D_delayed !== SCD_delayed );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXTP_BEHAVIORAL_V |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
i2s_mclk,
i2s_bclk,
i2s_lrclk,
i2s_sdata_out,
i2s_sdata_in,
spdif,
iic_scl,
iic_sda,
iic_mux_scl,
iic_mux_sda,
hdmi_iic_rstn,
hdmi_iic_scl,
hdmi_iic_sda,
hdmi_rx_clk,
hdmi_tx_clk,
hdmi_rx_data,
hdmi_tx_data,
hdmiio_int,
otg_vbusoc);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [31:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
inout iic_scl;
inout iic_sda;
inout [ 1:0] iic_mux_scl;
inout [ 1:0] iic_mux_sda;
inout hdmi_iic_rstn;
inout hdmi_iic_scl;
inout hdmi_iic_sda;
inout hdmiio_int;
input otg_vbusoc;
// imageon ports
input hdmi_rx_clk;
output hdmi_tx_clk;
input [15:0] hdmi_rx_data;
output [15:0] hdmi_tx_data;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
wire hdmi_rx_clk;
wire hdmi_tx_clk;
wire hdmi_rx_clk_bufio;
wire [15:0] hdmi_rx_data;
reg [15:0] hdmi_rx_data_in;
reg [15:0] hdmi_tx_data;
always @(posedge hdmi_rx_clk_bufio) begin
hdmi_rx_data_in <= hdmi_rx_data;
hdmi_tx_data <= hdmi_rx_data_in;
end
// instantiations
BUFIO (
.I (hdmi_rx_clk),
.O (hdmi_rx_clk_bufio));
ODDR #(.INIT(1'b0)) i_clk_oddr (
.R (1'b0),
.S (1'b0),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.C (hdmi_rx_clk_bufio),
.Q (hdmi_tx_clk));
ad_iobuf #(.DATA_WIDTH(1)) i_gpio_hdmi (
.dio_t (gpio_t[32]),
.dio_i (gpio_o[32]),
.dio_o (gpio_i[32]),
.dio_p (hdmiio_int));
ad_iobuf #(.DATA_WIDTH(1)) i_gpio_hdmi_iic_rstn (
.dio_t (gpio_t[33]),
.dio_i (gpio_o[33]),
.dio_o (gpio_i[33]),
.dio_p (hdmi_iic_rstn));
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.iic_imageon_scl_io (hdmi_iic_scl),
.iic_imageon_sda_io (hdmi_iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_12 (1'b0),
.ps_intr_13 (1'b0),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************
|
(** * More Logic *)
Require Export "Prop".
(* ############################################################ *)
(** * Existential Quantification *)
(** Another critical logical connective is _existential
quantification_. We can express it with the following
definition: *)
Inductive ex (X:Type) (P : X->Prop) : Prop :=
ex_intro : forall (witness:X), P witness -> ex X P.
(** That is, [ex] is a family of propositions indexed by a type [X]
and a property [P] over [X]. In order to give evidence for the
assertion "there exists an [x] for which the property [P] holds"
we must actually name a _witness_ -- a specific value [x] -- and
then give evidence for [P x], i.e., evidence that [x] has the
property [P].
*)
(** *** *)
(** Coq's [Notation] facility can be used to introduce more
familiar notation for writing existentially quantified
propositions, exactly parallel to the built-in syntax for
universally quantified propositions. Instead of writing [ex nat
ev] to express the proposition that there exists some number that
is even, for example, we can write [exists x:nat, ev x]. (It is
not necessary to understand exactly how the [Notation] definition
works.) *)
Notation "'exists' x , p" := (ex _ (fun x => p))
(at level 200, x ident, right associativity) : type_scope.
Notation "'exists' x : X , p" := (ex _ (fun x:X => p))
(at level 200, x ident, right associativity) : type_scope.
(** *** *)
(** We can use the usual set of tactics for
manipulating existentials. For example, to prove an
existential, we can [apply] the constructor [ex_intro]. Since the
premise of [ex_intro] involves a variable ([witness]) that does
not appear in its conclusion, we need to explicitly give its value
when we use [apply]. *)
Example exists_example_1 : exists n, n + (n * n) = 6.
Proof.
apply ex_intro with (witness:=2).
reflexivity. Qed.
(** Note that we have to explicitly give the witness. *)
(** *** *)
(** Or, instead of writing [apply ex_intro with (witness:=e)] all the
time, we can use the convenient shorthand [exists e], which means
the same thing. *)
Example exists_example_1' : exists n, n + (n * n) = 6.
Proof.
exists 2.
reflexivity. Qed.
(** *** *)
(** Conversely, if we have an existential hypothesis in the
context, we can eliminate it with [inversion]. Note the use
of the [as...] pattern to name the variable that Coq
introduces to name the witness value and get evidence that
the hypothesis holds for the witness. (If we don't
explicitly choose one, Coq will just call it [witness], which
makes proofs confusing.) *)
Theorem exists_example_2 : forall n,
(exists m, n = 4 + m) ->
(exists o, n = 2 + o).
Proof.
intros n H.
inversion H as [m Hm].
exists (2 + m).
apply Hm. Qed.
(** Here is another example of how to work with existentials. *)
Lemma exists_example_3 :
exists (n:nat), even n /\ beautiful n.
Proof.
(* WORKED IN CLASS *)
exists 8.
split.
unfold even. simpl. reflexivity.
apply b_sum with (n:=3) (m:=5).
apply b_3. apply b_5.
Qed.
(** **** Exercise: 1 star, optional (english_exists) *)
(** In English, what does the proposition
ex nat (fun n => beautiful (S n))
]]
mean? *)
(* Exists a natural number n that n+1 is beautiful. *)
(*
*)
(** **** Exercise: 1 star (dist_not_exists) *)
(** Prove that "[P] holds for all [x]" implies "there is no [x] for
which [P] does not hold." *)
Theorem dist_not_exists : forall (X:Type) (P : X -> Prop),
(forall x, P x) -> ~ (exists x, ~ P x).
Proof.
unfold not.
intros.
inversion H0 as [x H1].
apply H1.
apply H.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (not_exists_dist) *)
(** (The other direction of this theorem requires the classical "law
of the excluded middle".) *)
Theorem not_exists_dist :
excluded_middle ->
forall (X:Type) (P : X -> Prop),
~ (exists x, ~ P x) -> (forall x, P x).
Proof.
unfold excluded_middle.
intros.
destruct (H (P x)).
apply H1.
unfold not in H0 at 1.
apply ex_falso_quodlibet.
apply H0.
exists x.
apply H1.
Qed.
(** [] *)
(** **** Exercise: 2 stars (dist_exists_or) *)
(** Prove that existential quantification distributes over
disjunction. *)
Theorem dist_exists_or : forall (X:Type) (P Q : X -> Prop),
(exists x, P x \/ Q x) <-> (exists x, P x) \/ (exists x, Q x).
Proof.
split.
Case "->".
intro H.
inversion H as [x H0].
inversion H0.
left. exists x. apply H1.
right. exists x. apply H1.
Case "<-".
intro H.
inversion H.
inversion H0 as [x H1].
exists x. left. apply H1.
inversion H0 as [x H1].
exists x. right. apply H1.
Qed.
(** [] *)
(* ###################################################### *)
(** * Evidence-carrying booleans. *)
(** So far we've seen two different forms of equality predicates:
[eq], which produces a [Prop], and
the type-specific forms, like [beq_nat], that produce [boolean]
values. The former are more convenient to reason about, but
we've relied on the latter to let us use equality tests
in _computations_. While it is straightforward to write lemmas
(e.g. [beq_nat_true] and [beq_nat_false]) that connect the two forms,
using these lemmas quickly gets tedious.
*)
(** *** *)
(**
It turns out that we can get the benefits of both forms at once
by using a construct called [sumbool]. *)
Inductive sumbool (A B : Prop) : Set :=
| left : A -> sumbool A B
| right : B -> sumbool A B.
Notation "{ A } + { B }" := (sumbool A B) : type_scope.
(** Think of [sumbool] as being like the [boolean] type, but instead
of its values being just [true] and [false], they carry _evidence_
of truth or falsity. This means that when we [destruct] them, we
are left with the relevant evidence as a hypothesis -- just as with [or].
(In fact, the definition of [sumbool] is almost the same as for [or].
The only difference is that values of [sumbool] are declared to be in
[Set] rather than in [Prop]; this is a technical distinction
that allows us to compute with them.) *)
(** *** *)
(** Here's how we can define a [sumbool] for equality on [nat]s *)
Theorem eq_nat_dec : forall n m : nat, {n = m} + {n <> m}.
Proof.
(* WORKED IN CLASS *)
intros n.
induction n as [|n'].
Case "n = 0".
intros m.
destruct m as [|m'].
SCase "m = 0".
left. reflexivity.
SCase "m = S m'".
right. intros contra. inversion contra.
Case "n = S n'".
intros m.
destruct m as [|m'].
SCase "m = 0".
right. intros contra. inversion contra.
SCase "m = S m'".
destruct IHn' with (m := m') as [eq | neq].
left. apply f_equal. apply eq.
right. intros Heq. inversion Heq as [Heq']. apply neq. apply Heq'.
Defined.
(** Read as a theorem, this says that equality on [nat]s is decidable:
that is, given two [nat] values, we can always produce either
evidence that they are equal or evidence that they are not.
Read computationally, [eq_nat_dec] takes two [nat] values and returns
a [sumbool] constructed with [left] if they are equal and [right]
if they are not; this result can be tested with a [match] or, better,
with an [if-then-else], just like a regular [boolean].
(Notice that we ended this proof with [Defined] rather than [Qed].
The only difference this makes is that the proof becomes _transparent_,
meaning that its definition is available when Coq tries to do reductions,
which is important for the computational interpretation.)
*)
(** *** *)
(**
Here's a simple example illustrating the advantages of the [sumbool] form. *)
Definition override' {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if eq_nat_dec k k' then x else f k'.
Theorem override_same' : forall (X:Type) x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override' f k1 x1) k2 = f k2.
Proof.
intros X x1 k1 k2 f. intros Hx1.
unfold override'.
destruct (eq_nat_dec k1 k2). (* observe what appears as a hypothesis *)
Case "k1 = k2".
rewrite <- e.
symmetry. apply Hx1.
Case "k1 <> k2".
reflexivity. Qed.
(** Compare this to the more laborious proof (in MoreCoq.v) for the
version of [override] defined using [beq_nat], where we had to
use the auxiliary lemma [beq_nat_true] to convert a fact about booleans
to a Prop. *)
(** **** Exercise: 1 star (override_shadow') *)
Theorem override_shadow' : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
(override' (override' f k1 x2) k1 x1) k2 = (override' f k1 x1) k2.
Proof.
intros.
unfold override'.
destruct (eq_nat_dec k1 k2).
reflexivity.
reflexivity.
Qed.
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (all_forallb) *)
(** Inductively define a property [all] of lists, parameterized by a
type [X] and a property [P : X -> Prop], such that [all X P l]
asserts that [P] is true for every element of the list [l]. *)
Inductive all (X : Type) (P : X -> Prop) : (list X -> Prop) :=
| all_nil : all X P []
| all_rest : forall x, forall l, P x -> all X P l -> all X P (x :: l).
(** Recall the function [forallb], from the exercise
[forall_exists_challenge] in chapter [Poly]: *)
Fixpoint forallb {X : Type} (test : X -> bool) (l : list X) : bool :=
match l with
| [] => true
| x :: l' => andb (test x) (forallb test l')
end.
(** Using the property [all], write down a specification for [forallb],
and prove that it satisfies the specification. Try to make your
specification as precise as possible.
Are there any important properties of the function [forallb] which
are not captured by your specification? *)
Lemma all__forallb :
forall (X : Type) (P : X -> Prop) (test : X -> bool),
(forall x, P x <-> test x = true) ->
(forall l, forallb test l = true <-> all X P l).
Proof.
intros.
split.
Case "->".
intro H0.
induction l as [| x' l'].
apply all_nil.
apply all_rest.
inversion H0. apply H. apply andb_true_elim1 in H2. apply H2.
inversion H0. apply andb_true_elim2 in H2. apply IHl'. apply H2.
Case "<-".
intro H0.
induction H0. reflexivity.
simpl.
apply andb_true_intro.
split.
apply H in H0. apply H0.
apply IHall.
Qed.
(** [] *)
(** **** Exercise: 4 stars, advanced (filter_challenge) *)
(** One of the main purposes of Coq is to prove that programs match
their specifications. To this end, let's prove that our
definition of [filter] matches a specification. Here is the
specification, written out informally in English.
Suppose we have a set [X], a function [test: X->bool], and a list
[l] of type [list X]. Suppose further that [l] is an "in-order
merge" of two lists, [l1] and [l2], such that every item in [l1]
satisfies [test] and no item in [l2] satisfies test. Then [filter
test l = l1].
A list [l] is an "in-order merge" of [l1] and [l2] if it contains
all the same elements as [l1] and [l2], in the same order as [l1]
and [l2], but possibly interleaved. For example,
[1,4,6,2,3]
is an in-order merge of
[1,6,2]
and
[4,3].
Your job is to translate this specification into a Coq theorem and
prove it. (Hint: You'll need to begin by defining what it means
for one list to be a merge of two others. Do this with an
inductive relation, not a [Fixpoint].) *)
Inductive in_order_merge {X : Type}
: list X -> list X -> list X -> Prop :=
| merge_nil: in_order_merge [] [] []
| merge_first: forall x a b c,
in_order_merge a b c -> in_order_merge (x::a) b (x::c)
| merge_second: forall x a b c,
in_order_merge a b c -> in_order_merge a (x::b) (x::c).
Theorem merge_filter :
forall (X : Type) (test : X -> bool) (l l1 l2 : list X),
in_order_merge l1 l2 l ->
forallb test l1 = true ->
forallb (fun x => negb (test x)) l2 = true ->
filter test l = l1.
Proof.
intros.
induction H.
Case "merge_nil".
reflexivity.
Case "merge_first".
simpl in *.
apply andb_prop in H0. inversion H0.
rewrite H2. apply f_equal. apply IHin_order_merge.
apply H3. apply H1.
Case "merge_second".
simpl in *.
apply andb_prop in H1. inversion H1.
destruct (test x) eqn:HX.
inversion H2.
apply IHin_order_merge.
apply H0. apply H3.
Qed.
(** [] *)
(** **** Exercise: 5 stars, advanced, optional (filter_challenge_2) *)
(** A different way to formally characterize the behavior of [filter]
goes like this: Among all subsequences of [l] with the property
that [test] evaluates to [true] on all their members, [filter test
l] is the longest. Express this claim formally and prove it. *)
(* subseq is defined on `nat` in Prop.v *)
Inductive Subseq {X : Type}
: list X -> list X -> Prop :=
| subseq_nil_any: forall l2, Subseq [] l2
| subseq_ignore1: forall x l1 l2,
Subseq l1 l2 -> Subseq l1 (x :: l2)
| subseq_match1: forall x l1 l2,
Subseq l1 l2 -> Subseq (x :: l1) (x :: l2).
Theorem filter_challenge_2:
forall (X: Type) (test: X -> bool) (l subl: list X),
forallb test subl = true ->
Subseq subl l ->
length subl <= length (filter test l).
Proof.
intros.
induction H0.
Case "nil".
simpl. apply O_le_n.
Case "ignore1".
simpl.
destruct (test x).
simpl. apply le_S. apply IHSubseq. apply H.
apply IHSubseq. apply H.
Case "match1".
simpl.
destruct (test x) eqn:HE.
SCase "test x = true".
simpl. apply n_le_m__Sn_le_Sm. apply IHSubseq.
simpl in H. apply andb_true_elim2 in H. apply H.
SCase "test x = false".
simpl in H. apply andb_true_elim1 in H.
rewrite H in HE.
inversion HE.
Qed.
(** [] *)
(** **** Exercise: 4 stars, advanced (no_repeats) *)
(** The following inductively defined proposition... *)
Inductive appears_in {X:Type} (a:X) : list X -> Prop :=
| ai_here : forall l, appears_in a (a::l)
| ai_later : forall b l, appears_in a l -> appears_in a (b::l).
(** ...gives us a precise way of saying that a value [a] appears at
least once as a member of a list [l].
Here's a pair of warm-ups about [appears_in].
*)
Lemma appears_in_app : forall (X:Type) (xs ys : list X) (x:X),
appears_in x (xs ++ ys) -> appears_in x xs \/ appears_in x ys.
Proof.
intros X xs.
induction xs as [|x xs'].
intros. simpl in H. right. apply H.
intros.
simpl in H.
inversion H. left. apply ai_here.
apply IHxs' in H1.
inversion H1.
left. apply ai_later. apply H3.
right. apply H3.
Qed.
Lemma app_appears_in : forall (X:Type) (xs ys : list X) (x:X),
appears_in x xs \/ appears_in x ys -> appears_in x (xs ++ ys).
Proof.
intros X xs.
induction xs as [|x xs'].
intros. simpl.
inversion H. inversion H0. apply H0.
intros. simpl.
inversion H.
inversion H0.
apply ai_here.
apply ai_later. apply IHxs'. left. apply H2.
apply ai_later. apply IHxs'. right. apply H0.
Qed.
(** Now use [appears_in] to define a proposition [disjoint X l1 l2],
which should be provable exactly when [l1] and [l2] are
lists (with elements of type X) that have no elements in common. *)
Inductive disjoint {X : Type} : list X -> list X -> Prop :=
| disjoint_fst_nil: forall a, disjoint a []
| disjoint_nil_snd: forall b, disjoint [] b
| disjoint_fst: forall x a b,
~ appears_in x b -> disjoint a b -> disjoint (x::a) b
| disjoint_snd: forall x a b,
~ appears_in x a -> disjoint a b -> disjoint a (x::b).
(** Next, use [appears_in] to define an inductive proposition
[no_repeats X l], which should be provable exactly when [l] is a
list (with elements of type [X]) where every member is different
from every other. For example, [no_repeats nat [1,2,3,4]] and
[no_repeats bool []] should be provable, while [no_repeats nat
[1,2,1]] and [no_repeats bool [true,true]] should not be. *)
Inductive no_repeats {X : Type} : list X -> Prop :=
| norep_nil: no_repeats []
| norep_cc: forall x l,
~ appears_in x l -> no_repeats l -> no_repeats (x::l).
(** Finally, state and prove one or more interesting theorems relating
[disjoint], [no_repeats] and [++] (list append). *)
Theorem dis_dis: forall (X : Type) (x : X) (l1 l2 : list X),
disjoint (x::l1) l2 -> disjoint l1 l2.
Proof.
intros.
generalize dependent l1.
induction l2.
intros.
apply disjoint_fst_nil.
intros.
inversion H.
apply H4. apply disjoint_snd. intro H5. apply H3.
apply ai_later. apply H5.
apply IHl2. apply H4.
Qed.
Theorem dis_neq: forall (X : Type) (x y : X) (l1 l2 : list X),
disjoint (x::l1) (y::l2) -> x <> y.
Proof.
intros.
inversion H.
intro E. apply H2. rewrite E. apply ai_here.
intro E. apply H3. rewrite E. apply ai_here.
Qed.
Theorem dis_nai: forall (X : Type) (x : X) (l1 l2 : list X),
disjoint (x::l1) l2 -> ~ appears_in x l2.
Proof.
intros.
generalize dependent l1.
induction l2 as [|y l2'].
Case "l2 = []".
intros. intro h. inversion h.
Case "l2 = y :: l2'".
intros. intro h.
inversion H.
apply H2. apply h.
inversion h.
apply dis_neq in H. apply H. apply H6.
apply IHl2' in H4. apply H4. apply H6.
Qed.
Lemma disjoint__norep: forall (X : Type) (l1 l2 : list X),
disjoint l1 l2 -> no_repeats l1 -> no_repeats l2
-> no_repeats (l1 ++ l2).
Proof.
intros X l1.
induction l1 as [|x1 l1'].
intros. simpl. apply H1.
intros.
simpl.
apply norep_cc.
intro A.
apply appears_in_app in A.
inversion A.
inversion H0. apply H5. apply H2.
destruct l2 as [| x2 l2']. inversion H2.
inversion H. apply H5. apply H2.
apply dis_nai in H.
apply H. apply H2.
apply IHl1'.
apply dis_dis in H. apply H.
inversion H0. apply H5. apply H1.
Qed.
(** [] *)
(** **** Exercise: 3 stars (nostutter) *)
(** Formulating inductive definitions of predicates is an important
skill you'll need in this course. Try to solve this exercise
without any help at all.
We say that a list of numbers "stutters" if it repeats the same
number consecutively. The predicate "[nostutter mylist]" means
that [mylist] does not stutter. Formulate an inductive definition
for [nostutter]. (This is different from the [no_repeats]
predicate in the exercise above; the sequence [1;4;1] repeats but
does not stutter.) *)
Inductive nostutter: list nat -> Prop :=
| ns_nil: nostutter []
| ns_sgl: forall x, nostutter [x]
| ns_more : forall x y l,
x <> y -> nostutter (y::l) -> nostutter (x::y::l).
(** Make sure each of these tests succeeds, but you are free
to change the proof if the given one doesn't work for you.
Your definition might be different from mine and still correct,
in which case the examples might need a different proof.
The suggested proofs for the examples (in comments) use a number
of tactics we haven't talked about, to try to make them robust
with respect to different possible ways of defining [nostutter].
You should be able to just uncomment and use them as-is, but if
you prefer you can also prove each example with more basic
tactics. *)
Example test_nostutter_1: nostutter [3;1;4;1;5;6].
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
Example test_nostutter_2: nostutter [].
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
Example test_nostutter_3: nostutter [5].
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
Example test_nostutter_4: not (nostutter [3;1;1;4]).
Proof. intro.
repeat match goal with
h: nostutter _ |- _ => inversion h; clear h; subst
end.
contradiction H1; auto. Qed.
(** [] *)
(** **** Exercise: 4 stars, advanced (pigeonhole principle) *)
(** The "pigeonhole principle" states a basic fact about counting:
if you distribute more than [n] items into [n] pigeonholes, some
pigeonhole must contain at least two items. As is often the case,
this apparently trivial fact about numbers requires non-trivial
machinery to prove, but we now have enough... *)
(** First a pair of useful lemmas (we already proved these for lists
of naturals, but not for arbitrary lists). *)
Lemma app_length : forall (X:Type) (l1 l2 : list X),
length (l1 ++ l2) = length l1 + length l2.
Proof.
intros X l1.
induction l1 as [|l1'].
intros. reflexivity.
intro l2.
destruct l2.
rewrite app_nil. simpl. rewrite plus_0_r. reflexivity.
simpl. apply f_equal. apply IHl1.
Qed.
Lemma appears_in_app_split : forall (X:Type) (x:X) (l:list X),
appears_in x l ->
exists l1, exists l2, l = l1 ++ (x::l2).
Proof.
intros.
induction l as [|x' l'].
inversion H.
inversion H.
exists []. exists l'. reflexivity.
apply IHl' in H1.
inversion H1 as [l1' H3].
inversion H3 as [l2' H4].
exists (x'::l1'). exists l2'. rewrite H4. reflexivity.
Qed.
(** Now define a predicate [repeats] (analogous to [no_repeats] in the
exercise above), such that [repeats X l] asserts that [l] contains
at least one repeated element (of type [X]). *)
Inductive repeats {X:Type} : list X -> Prop :=
| rep_here: forall x l, appears_in x l -> repeats (x::l)
| rep_later: forall x l, repeats l -> repeats (x::l).
(** Now here's a way to formalize the pigeonhole principle. List [l2]
represents a list of pigeonhole labels, and list [l1] represents
the labels assigned to a list of items: if there are more items
than labels, at least two items must have the same label. This
proof is much easier if you use the [excluded_middle] hypothesis
to show that [appears_in] is decidable, i.e. [forall x
l, (appears_in x l) \/ ~ (appears_in x l)]. However, it is also
possible to make the proof go through _without_ assuming that
[appears_in] is decidable; if you can manage to do this, you will
not need the [excluded_middle] hypothesis. *)
Theorem pigeonhole_principle: forall (X:Type) (l1 l2:list X),
excluded_middle ->
(forall x, appears_in x l1 -> appears_in x l2) ->
length l2 < length l1 ->
repeats l1.
Proof.
intros X l1. induction l1 as [|x l1'].
intros. inversion H1.
intros.
assert (HX: appears_in x l2). apply H0. apply ai_here.
destruct (H (appears_in x l1')).
(* if x appears in l1': *)
apply rep_here. apply H2.
(* x not in l1', continue on l1' and (l2 - {x}) *)
apply rep_later.
(* split l2 into l2h ++ x :: l2t *)
assert (HX2: appears_in x l2). apply HX.
apply appears_in_app_split in HX2.
inversion HX2 as [l2h H3].
inversion H3 as [l2t H5].
apply IHl1' with (l2:=l2h ++ l2t).
apply H.
intros.
destruct (H (x0 = x)).
(* if x0 = x *)
rewrite H6 in H4. apply ex_falso_quodlibet. apply H2. apply H4.
(* if x0 <> x, we dont't need x in l2 but just l2h ++ l2t *)
assert (HX0: appears_in x0 l2). apply H0. apply ai_later. apply H4.
rewrite H5 in HX0.
apply appears_in_app in HX0.
inversion HX0.
apply app_appears_in. left. apply H7.
apply app_appears_in. right.
inversion H7.
apply ex_falso_quodlibet. apply H6. apply H9. apply H9.
(* finally, the length restriction *)
rewrite H5 in H1.
rewrite app_length in H1.
simpl in H1.
rewrite <-plus_n_Sm in H1.
unfold lt in H1.
apply Sn_le_Sm__n_le_m in H1.
rewrite <-app_length in H1.
unfold lt.
apply H1.
Qed.
(** [] *)
(* TODO: without excluded_middle. Maybe there is a less powerful version of it with just [appears_in]. *)
(* FILL IN HERE *)
(* $Date: 2014-10-14 15:52:05 -0400 (Tue, 14 Oct 2014) $ *)
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_adapter_8_64;
// parameters
localparam INPUT_DATA_WIDTH = 8;
localparam INPUT_KEEP_WIDTH = (INPUT_DATA_WIDTH/8);
localparam OUTPUT_DATA_WIDTH = 64;
localparam OUTPUT_KEEP_WIDTH = (OUTPUT_DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [INPUT_DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [INPUT_KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [OUTPUT_DATA_WIDTH-1:0] output_axis_tdata;
wire [OUTPUT_KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
// dump file
$dumpfile("test_axis_adapter_8_64.lxt");
$dumpvars(0, test_axis_adapter_8_64);
end
axis_adapter #(
.INPUT_DATA_WIDTH(INPUT_DATA_WIDTH),
.INPUT_KEEP_WIDTH(INPUT_KEEP_WIDTH),
.OUTPUT_DATA_WIDTH(OUTPUT_DATA_WIDTH),
.OUTPUT_KEEP_WIDTH(OUTPUT_KEEP_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD2_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD2_BLACKBOX_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlygate4sd2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD2_BLACKBOX_V
|
/*****************************************************************************\
*
* interface to IS61WV6416BLL-10TLI 64kx16 bit SRAM
*
* instantiation side: 128kx8 bit
*
* the clk input is MUST NOT be faster than 100 MHz
* the inputs may be reset after 1 cycle
*
* transition chains:
* read
* done
* read request (higher priority then write request)
* set outputs to memory
* read reply, reset outputs
* done
*
* write
* done
* write request
* enable data output
* set outputs
* reset outputs
* done
*
\*****************************************************************************/
module RAM_IS61WV6416BLL (
// communication from/to instantiation
input [0:0] clk, // clock
input [0:0] n_reset, // global reset (low active)
// reading from memory
input [16:0] w_address, // Address Input
input [7:0] w_data, // Data bi-directional
input [0:0] w_request, // request Input
output reg [0:0] w_started, // started writing
output reg [0:0] w_done, // write done
// writing to memory
input [16:0] r_address, // Address Input
output reg [7:0] r_data, // Data bi-directional
input [0:0] r_request, // request Input
output reg [0:0] r_started, // started reading
output reg [0:0] r_done, // reply done
// communication to actual SRAM (harware)
output reg [15:0] hw_address, // Address Input
output reg [0:0] hw_n_cs, // Chip Select (low active)
output reg [0:0] hw_n_we, // Write Enable (low active)
output reg [0:0] hw_n_oe, // Output Enable (low active)
output reg [0:0] hw_n_ub, // upper byte selection (low active)
output reg [0:0] hw_n_lb, // lower byte selection (low active)
input [15:0] hw_data_in, // data input
output reg [15:0] hw_data_out, // data output
output reg [0:0] hw_data_oe // direction of iCE40 data pins
);
reg [0:0] counter = 0;
reg [0:0] r_request_int = 0;
reg [0:0] w_request_int = 0;
always @ (posedge clk) begin
if (!n_reset) begin
r_done <= 0;
w_done <= 0;
hw_n_we <= 1;
hw_n_oe <= 1;
hw_n_cs <= 1;
counter <= 0;
end else begin
if (counter) begin
counter <= counter-1;
end else begin
if (r_done || w_done) begin
// reset done signals after one cycle and
// request buffers at the same time
r_done <= 0;
w_done <= 0;
r_request_int <= 0;
w_request_int <= 0;
hw_n_cs <= 1;
hw_data_oe <= 1;
hw_data_oe <= 1;
end else if (r_request && hw_n_cs) begin
// read request is issued while no access is pending
r_request_int <= 1;
r_started <= 1;
hw_n_we <= 1; // todo: access write enable sequentially if required
hw_n_oe <= 0;
hw_n_cs <= 0;
hw_n_ub <= r_address[16];
hw_n_lb <= !r_address[16];
hw_address <= r_address[15:0];
counter <= 1;
end else if (r_request_int && !hw_n_cs) begin
// the pending read request should be answered by the SRAM
r_started <= 0;
hw_n_oe <= 1;
hw_n_cs <= 1;
r_data <= hw_n_ub ? hw_data_in[15:8] : hw_data_in[7:0];
r_done <= 1;
end else if (w_request && hw_n_cs && !hw_data_oe) begin
hw_data_oe <= 1;
end else if (w_request && hw_n_cs && hw_data_oe) begin
// write request is issued while no access is pending
w_request_int <= 1;
w_started <= 1;
hw_n_we <= 0; // TODO: access write enable sequentially if required
hw_n_oe <= 1;
hw_n_cs <= 0;
hw_data_oe <= 0;
hw_n_ub <= r_address[16];
hw_n_lb <= !r_address[16];
hw_address <= r_address[15:0];
hw_data_out <= {w_data, w_data};
counter <= 1;
end else if (w_request_int && !hw_n_cs) begin
// the pending write request should be answered by the SRAM
w_started <= 0;
hw_n_oe <= 1;
hw_n_cs <= 1;
w_done <= 1;
end else begin
// no request -> nothing to do
end
end
end
end
endmodule
|
/* Generated by Yosys 0.4+19 (git sha1 abf81d7, clang 3.4-1ubuntu3 -fPIC -Os) */
(* src = "../control/control.v:1" *)
module control(op, alu_op, regDst, aluSrc, memToReg, regWrite, memRead, memWrite, branch);
(* src = "../control/control.v:2" *)
input [5:0] op;
(* src = "../control/control.v:3" *)
output [1:0] alu_op;
(* src = "../control/control.v:4" *)
output regDst;
(* src = "../control/control.v:4" *)
output aluSrc;
(* src = "../control/control.v:4" *)
output memToReg;
(* src = "../control/control.v:4" *)
output regWrite;
(* src = "../control/control.v:5" *)
output memRead;
(* src = "../control/control.v:5" *)
output memWrite;
(* src = "../control/control.v:5" *)
output branch;
(* src = "../control/control.v:8" *)
wire int0;
(* src = "../control/control.v:8" *)
wire op0_bar;
(* src = "../control/control.v:8" *)
wire op1_bar;
(* src = "../control/control.v:8" *)
wire op2_bar;
(* src = "../control/control.v:8" *)
wire op3_bar;
(* src = "../control/control.v:8" *)
wire op4_bar;
(* src = "../control/control.v:8" *)
wire op5_bar;
(* src = "../control/control.v:17" *)
wire _00_;
(* src = "../control/control.v:17" *)
wire _01_;
(* src = "../control/control.v:17" *)
wire _02_;
(* src = "../control/control.v:17" *)
wire _03_;
(* src = "../control/control.v:18" *)
wire _04_;
(* src = "../control/control.v:18" *)
wire _05_;
(* src = "../control/control.v:20" *)
wire _06_;
(* src = "../control/control.v:20" *)
wire _07_;
(* src = "../control/control.v:20" *)
wire _08_;
(* src = "../control/control.v:20" *)
wire _09_;
(* src = "../control/control.v:22" *)
wire _10_;
(* src = "../control/control.v:22" *)
wire _11_;
(* src = "../control/control.v:22" *)
wire _12_;
(* src = "../control/control.v:25" *)
wire _13_;
(* src = "../control/control.v:25" *)
wire _14_;
assign op0_bar = ~op[0];
assign op1_bar = ~op[1];
assign op2_bar = ~op[2];
assign op3_bar = ~op[3];
assign op4_bar = ~op[4];
assign op5_bar = ~op[5];
assign _00_ = op5_bar & op4_bar;
assign _01_ = _00_ & op3_bar;
assign _02_ = _01_ & op[2];
assign _03_ = _02_ & op1_bar;
assign alu_op[0] = _03_ & op0_bar;
assign _04_ = _01_ & op2_bar;
assign _05_ = _04_ & op1_bar;
assign alu_op[1] = _05_ & op0_bar;
assign _06_ = op[5] & op4_bar;
assign _07_ = _06_ & op3_bar;
assign _08_ = _07_ & op2_bar;
assign _09_ = _08_ & op[1];
assign int0 = _09_ & op[0];
assign _10_ = _06_ & op[3];
assign _11_ = _10_ & op2_bar;
assign _12_ = _11_ & op[1];
assign memWrite = _12_ & op[0];
assign _13_ = _06_ & op2_bar;
assign _14_ = _13_ & op[1];
assign aluSrc = _14_ & op[0];
assign regWrite = int0 | alu_op[1];
assign regDst = alu_op[1];
assign memToReg = int0;
assign memRead = int0;
assign branch = alu_op[0];
endmodule
|
// ***************************************************************************
//
// UCLA CDSC Microbenchmark AFU
//
// Engineer: Peng Wei
// Create Date: Oct 13, 2015
// Module Name: micro_bench
// Description: top level wrapper for Microbenchmark AFU
// ***************************************************************************
//
// CSR Address Map -- Change v1.1
//------------------------------------------------------------------------------------------
// Address[15:0] Attribute Name Comments
// 'h1A00 WO CSR_AFU_DSM_BASEL Lower 32-bits of AFU DSM base address. The lower 6-bbits are 4x00 since the address is cache aligned.
// 'h1A04 WO CSR_AFU_DSM_BASEH Upper 32-bits of AFU DSM base address.
// 'h1A20: WO CSR_SRC_ADDR Start physical address for source buffer. All read requests are targetted to this region.
// 'h1A24: WO CSR_DST_ADDR Start physical address for destination buffer. All write requests are targetted to this region.
// 'h1A2c: WO CSR_CTL Controls test flow, start, stop, force completion
// 'h1A30: WO CSR_DATA_SIZE Input/Output data size
// 'h1A34: WO CSR_LOOP_NUM Loop number
//
//
// DSM Offeset Map -- Change v1.1
//------------------------------------------------------------------------------------------
// Byte Offset Attribute Name Comments
// 0x00 RO DSM_AFU_ID non-zero value to uniquely identify the AFU
// 0x40 RO DSM_STATUS test status and error register
//
//
// 1 Cacheline = 64B i.e 2^6 Bytes
// Let 2^N be the number of cachelines in the source & destination buffers. Then select CSR_SRC_ADDR & CSR_DEST_ADDR to be 2^(N+6) aligned.
//
// CSR_SRC_ADDR:
// [31:0] WO 2^(N+6)B aligned address points to the start of read buffer
//
// CSR_DST_ADDR:
// [31:0] WO 2^(N+6)B aligned address points to the start of write buffer
//
// CSR_CTL:
// [31:3] WO Rsvd
// [2] WO Force test completion. Writes test completion flag and other performance counters to csr_stat. It appears to be like a normal test completion.
// [1] WO Starts test execution.
// [0] WO Active low test Reset. All configuration parameters change to reset defaults.
//
// CSR_CFG:
// [29] WO cr_interrupt_testmode - used to test interrupt. Generates an interrupt at end of each test.
// [28] WO cr_interrupt_on_error - send an interrupt when error detected
// [27:20] WO cr_test_cfg -may be used to configure the behavior of each test mode
// [10:9] WO cr_rdsel -configure read request type. 0- RdLine_S, 1- RdLine_I, 2- RdLine_O, 3- Mixed mode
// [8] WO cr_delay_en -enable random delay insertion between requests
// [4:2] WO cr_mode -configures test mode
// [1] WO cr_cont - 1- test rollsover to start address after it reaches the CSR_NUM_LINES count. Such a test terminates only on an error.
// 0- test terminates, updated the status csr when CSR_NUM_LINES count is reached.
// [0] WO cr_wrthru_en -switch between write back to write through request type. 0- Wr Back, 1- WrThru
//
// DSM_STATUS:
// [511:256] RO Error dump from Test Mode
// [255:224] RO end overhead
// [223:192] RO start overhead
// [191:160] RO Number of writes
// [159:128] RO Number of reads
// [127:64] RO Number of clocks
// [63:32] RO test error register
// [31:0] RO test completion flag
//
// DSM_AFU_ID:
// [512:144] RO Zeros
// [143:128] RO Version
// [127:0] RO AFU ID
module micro_bench #(parameter TXHDR_WIDTH=61, RXHDR_WIDTH=18, DATA_WIDTH =512)
(
// ---------------------------global signals-------------------------------------------------
clk, // in std_logic; -- Core clock
reset_n, // in std_logic; -- Use SPARINGLY only for control
// ---------------------------IF signals between SPL and FPL --------------------------------
rb2cf_C0RxHdr, // [RXHDR_WIDTH-1:0] cci_intf: Rx header to SPL channel 0
rb2cf_C0RxData, // [DATA_WIDTH -1:0] cci_intf: Rx data response to SPL | no back pressure
rb2cf_C0RxWrValid, // cci_intf: Rx write response enable
rb2cf_C0RxRdValid, // cci_intf: Rx read response enable
rb2cf_C0RxCfgValid, // cci_intf: Rx config response enable
rb2cf_C0RxUMsgValid, // cci_intf: Rx UMsg valid
rb2cf_C0RxIntrValid, // cci_intf: Rx interrupt valid
rb2cf_C1RxHdr, // [RXHDR_WIDTH-1:0] cci_intf: Rx header to SPL channel 1
rb2cf_C1RxWrValid, // cci_intf: Rx write response valid
rb2cf_C1RxIntrValid, // cci_intf: Rx interrupt valid
cf2ci_C0TxHdr, // [TXHDR_WIDTH-1:0] cci_intf: Tx Header from SPL channel 0
cf2ci_C0TxRdValid, // cci_intf: Tx read request enable
cf2ci_C1TxHdr, // cci_intf: Tx Header from SPL channel 1
cf2ci_C1TxData, // cci_intf: Tx data from SPL
cf2ci_C1TxWrValid, // cci_intf: Tx write request enable
cf2ci_C1TxIntrValid, // cci_intf: Tx interrupt valid
ci2cf_C0TxAlmFull, // cci_intf: Tx memory channel 0 almost full
ci2cf_C1TxAlmFull, // cci_intf: TX memory channel 1 almost full
ci2cf_InitDn // Link initialization is complete
);
input clk; // in std_logic; -- Core clock
input reset_n; // in std_logic; -- Use SPARINGLY only for control
input [RXHDR_WIDTH-1:0] rb2cf_C0RxHdr; // [RXHDR_WIDTH-1:0]cci_intf: Rx header to SPL channel 0
input [DATA_WIDTH -1:0] rb2cf_C0RxData; // [DATA_WIDTH -1:0]cci_intf: data response to SPL | no back pressure
input rb2cf_C0RxWrValid; // cci_intf: write response enable
input rb2cf_C0RxRdValid; // cci_intf: read response enable
input rb2cf_C0RxCfgValid; // cci_intf: config response enable
input rb2cf_C0RxUMsgValid; // cci_intf: Rx UMsg valid
input rb2cf_C0RxIntrValid; // cci_intf: interrupt response enable
input [RXHDR_WIDTH-1:0] rb2cf_C1RxHdr; // [RXHDR_WIDTH-1:0]cci_intf: Rx header to SPL channel 1
input rb2cf_C1RxWrValid; // cci_intf: write response valid
input rb2cf_C1RxIntrValid; // cci_intf: interrupt response valid
output [TXHDR_WIDTH-1:0] cf2ci_C0TxHdr; // [TXHDR_WIDTH-1:0]cci_intf: Tx Header from SPL channel 0
output cf2ci_C0TxRdValid; // cci_intf: Tx read request enable
output [TXHDR_WIDTH-1:0] cf2ci_C1TxHdr; // cci_intf: Tx Header from SPL channel 1
output [DATA_WIDTH -1:0] cf2ci_C1TxData; // cci_intf: Tx data from SPL
output cf2ci_C1TxWrValid; // cci_intf: Tx write request enable
output cf2ci_C1TxIntrValid; // cci_intf: Tx interrupt valid
input ci2cf_C0TxAlmFull; // cci_intf: Tx memory channel 0 almost full
input ci2cf_C1TxAlmFull; // cci_intf: TX memory channel 1 almost full
input ci2cf_InitDn; // cci_intf: Link initialization is complete
assign cf2ci_C1TxIntrValid = 'b0;
//----------------------------------------------------------------------------------------------------------------------
// Microbenchmark AFU ID
// It is important to keep the least significant 4 bits NON-ZERO to be compliant with CCIDemo.cpp
//
localparam MICRO_BENCH = 128'h2015_1013_900d_beef_a000_b000_c000_d000;
localparam VERSION = 16'h0001;
//---------------------------------------------------------
// CCI-S Request Encodings ***** DO NOT MODIFY ******
//---------------------------------------------------------
localparam WrThru = 4'h1;
localparam WrLine = 4'h2;
localparam RdLine = 4'h4;
localparam WrFence = 4'h5;
//--------------------------------------------------------
// CCI-S Response Encodings ***** DO NOT MODIFY ******
//--------------------------------------------------------
localparam RSP_CSR = 4'h0;
localparam RSP_WRITE = 4'h1;
localparam RSP_READ = 4'h4;
//---------------------------------------------------------
// Default Values ****** May be MODIFIED *******
//---------------------------------------------------------
localparam DEF_SRC_ADDR = 32'h0400_0000; // Read data starting from here. Cache aligned Address
localparam DEF_DST_ADDR = 32'h0800_0000; // Copy data to here. Cache aligned Address
localparam DEF_DSM_BASE = 32'h04ff_ffff; // default status address
//---------------------------------------------------------
// CSR Address Map ***** DO NOT MODIFY *****
//---------------------------------------------------------
localparam CSR_AFU_DSM_BASEL = 16'h1a00; // WO - Lower 32-bits of AFU DSM base address. The lower 6-bbits are 4x00 since the address is cache aligned.
localparam CSR_AFU_DSM_BASEH = 16'h1a04; // WO - Upper 32-bits of AFU DSM base address.
localparam CSR_SRC_ADDR = 16'h1a20; // WO Reads are targetted to this region
localparam CSR_DST_ADDR = 16'h1a24; // WO Writes are targetted to this region
localparam CSR_CTL = 16'h1a2c; // WO Control CSR to start n stop the test
localparam CSR_DATA_SIZE = 16'h1a30; // WO Input/Output data size
localparam CSR_LOOP_NUM = 16'h1a34; // WO Loop number
//----------------------------------------------------------------------------------
// Device Status Memory (DSM) Address Map ***** DO NOT MODIFY *****
// Physical address = value at CSR_AFU_DSM_BASE + Byte offset
//----------------------------------------------------------------------------------
// Byte Offset Attribute Width Comments
localparam DSM_AFU_ID = 32'h0; // RO 32b non-zero value to uniquely identify the AFU
localparam DSM_STATUS = 32'h40; // RO 512b test status and error info
//----------------------------------------------------------------------------------------------------------------------
reg [DATA_WIDTH-1:0] cf2ci_C1TxData;
reg [TXHDR_WIDTH-1:0] cf2ci_C1TxHdr;
reg cf2ci_C1TxWrValid;
reg [TXHDR_WIDTH-1:0] cf2ci_C0TxHdr;
reg cf2ci_C0TxRdValid;
reg dsm_base_valid;
reg dsm_base_valid_q;
reg afuid_updtd;
reg task_completed;
reg task_completed_d;
reg [63:0] cr_dsm_base; // a00h, a04h - DSM base address
reg [31:0] cr_src_address; // a20h - source buffer address
reg [31:0] cr_dst_address; // a24h - destn buffer address
reg [31:0] cr_ctl = 0; // a2ch - control register to start and stop the test
reg [31:0] cr_data_size; // a30h - input/output data size (unit: byte)
reg [31:0] cr_loop_num; // a34h - specify how many times the kernel needs to be repeated
wire test_go = cr_ctl[1]; // When 0, it allows reconfiguration of test parameters.
//CCI Read Address Offset
reg [31:0] RdAddrOffset;
//CCI Read ID
reg [13:0] RdReqId;
//CCI Read Type
wire [3:0] rdreq_type = RdLine;
//CCI Read Date
reg [DATA_WIDTH-1:0] RdData;
//CCI Write Address Offset
reg [31:0] WrAddrOffset;
//CCI Write ID
reg [13:0] WrReqId;
//CCI Write Type
wire [3:0] wrreq_type = WrLine;
//CCI Write Date
reg [DATA_WIDTH-1:0] WrData;
wire [31:0] ds_afuid_address = dsm_offset2addr(DSM_AFU_ID,cr_dsm_base); // 0h - afu id is written to this address
wire [31:0] ds_stat_address = dsm_offset2addr(DSM_STATUS,cr_dsm_base); // 40h - test status is written to this address
wire re2xy_go = test_go & afuid_updtd & ci2cf_InitDn; // After initializing DSM, we can do actual tasks on AFU
reg WrHdr_valid; // 1: Valid Write Request
reg RdHdr_valid; // 1: Valid Read Request
//-------------------------
//CSR Register Handling
//-------------------------
always @(posedge clk)
begin
if(!reset_n)
begin
cr_dsm_base <= DEF_DSM_BASE;
cr_src_address <= DEF_SRC_ADDR;
cr_dst_address <= DEF_DST_ADDR;
cr_ctl <= 'b0;
cr_data_size <= 'h4000;
cr_loop_num <= 'b1;
dsm_base_valid <= 'b0;
end
else
begin
//control register can be written anytime after resetting
if(rb2cf_C0RxCfgValid)
case({rb2cf_C0RxHdr[13:0],2'b00}) /* synthesis parallel_case */
CSR_CTL : cr_ctl <= rb2cf_C0RxData[31:0];
endcase
if(~test_go) // Configuration Mode, following CSRs can only be updated in this mode
begin
if(rb2cf_C0RxCfgValid)
case({rb2cf_C0RxHdr[13:0],2'b00}) /* synthesis parallel_case */
CSR_SRC_ADDR: cr_src_address <= rb2cf_C0RxData[31:0];
CSR_DST_ADDR: cr_dst_address <= rb2cf_C0RxData[31:0];
CSR_AFU_DSM_BASEH: cr_dsm_base[63:32] <= rb2cf_C0RxData[31:0];
CSR_AFU_DSM_BASEL:begin
cr_dsm_base[31:0] <= rb2cf_C0RxData[31:0];
dsm_base_valid <= 'b1;
end
CSR_DATA_SIZE: cr_data_size <= rb2cf_C0RxData[31:0];
CSR_LOOP_NUM: cr_loop_num <= rb2cf_C0RxData[31:0];
endcase
end
end
end
//-------------------------
// Data Processing
//-------------------------
reg [31:0] cache_line_counter; // increment rate = 'd64
reg [31:0] cache_line_counter_d;
reg [31:0] integer_counter;
reg [31:0] integer_counter_d;
reg [DATA_WIDTH-1:0] final_result;
reg [DATA_WIDTH-1:0] final_result_d;
reg [2:0] cur_state;
reg [2:0] next_state;
localparam RESET = 'd0;
localparam IDLE = 'd1;
localparam WAIT = 'd2;
localparam CALC = 'd3;
localparam WRITE = 'd4;
localparam DONE = 'd5;
// Sequential Logic
always @ (posedge clk)
begin
if (!reset_n)
begin
cache_line_counter <= 'b0;
integer_counter <= 'b0;
final_result <= {(DATA_WIDTH/32){32'h900dbeef}};
cur_state <= RESET;
end
else
begin
cache_line_counter <= cache_line_counter_d;
integer_counter <= integer_counter_d;
final_result <= final_result_d;
cur_state <= next_state;
end
end
// Combinatorial Logic
always @ (*)
begin
next_state = cur_state;
case(cur_state) /* synthesis parallel_case */
RESET:
begin
if(re2xy_go) // ready to go
next_state = IDLE;
end
IDLE:
begin
if(!ci2cf_C0TxAlmFull) // read request sent
next_state = WAIT;
end
WAIT:
begin
if(rb2cf_C0RxRdValid) // read response received
next_state = CALC;
end
CALC:
begin
if(integer_counter == 'd16 && cache_line_counter == cr_data_size)
next_state = WRITE;
if(integer_counter == 'd16 && cache_line_counter != cr_data_size)
next_state = IDLE;
end
WRITE:
begin
if(!ci2cf_C1TxAlmFull) // write request sent
next_state = DONE;
end
endcase
end
always @ (*)
begin
cache_line_counter_d = cache_line_counter;
integer_counter_d = integer_counter;
final_result_d = final_result;
RdHdr_valid = 'b0;
RdAddrOffset = 'b0;
RdReqId = 'b0;
WrHdr_valid = 'b0;
WrAddrOffset = 'b0;
WrReqId = 'b0;
WrData = 'b0;
task_completed_d = 'b0;
case(cur_state) /* synthesis parallel_case */
IDLE:
begin
RdHdr_valid = 'b1;
RdAddrOffset = cache_line_counter;
RdReqId = 'b0; // fixed ID for sequential kernel
end
WAIT:
begin
if(rb2cf_C0RxRdValid) // read response received
begin
cache_line_counter_d = cache_line_counter + 'b1; // increment cache line counter
integer_counter_d = 'd16; // reset integer counter
end
end
CALC:
begin
if(integer_counter != 'd16)
begin
integer_counter_d = integer_counter + 'b1;
end
else
begin
final_result_d = final_result ^ RdData;
end
end
WRITE:
begin
WrHdr_valid = 'b1;
WrAddrOffset = 'b0;
WrReqId = 'b0;
WrData = final_result;
if(!ci2cf_C1TxAlmFull) // write request sent
task_completed_d = 'b1;
end
endcase
end
//-------------------------
// Handle CCI Tx Channels
//-------------------------
// Format Read Header
wire [31:0] RdAddr = cr_src_address ^ RdAddrOffset;
wire [TXHDR_WIDTH-1:0] RdHdr = {
5'h00, // [60:56] Byte Enable
rdreq_type, // [55:52] Request Type
6'h00, // [51:46] Rsvd
RdAddr, // [45:14] Address
RdReqId // [13:0] Meta data to track the SPL requests
};
// Format Write Header
wire [31:0] WrAddr = cr_dst_address ^ WrAddrOffset;
wire [TXHDR_WIDTH-1:0] WrHdr = {
5'h00, // [60:56] Byte Enable
wrreq_type, // [55:52] Request Type
6'h00, // [51:46] Rsvd
WrAddr, // [45:14] Address
WrReqId // [13:0] Meta data to track the SPL requests
};
// Sending Requests
always @(posedge clk)
begin
if(!reset_n)
begin
afuid_updtd <= 'b0;
cf2ci_C1TxHdr <= 'b0;
cf2ci_C1TxWrValid <= 'b0;
cf2ci_C1TxData <= 'b0;
cf2ci_C0TxHdr <= 'b0;
cf2ci_C0TxRdValid <= 'b0;
dsm_base_valid_q <= 'b0;
task_completed <= 'b0;
end
else
begin
//Tx Path
//--------------------------------------------------------------------------
cf2ci_C1TxHdr <= 'b0;
cf2ci_C1TxWrValid <= 'b0;
cf2ci_C1TxData <= 'b0;
cf2ci_C0TxHdr <= 'b0;
cf2ci_C0TxRdValid <= 'b0;
dsm_base_valid_q <= dsm_base_valid;
task_completed <= task_completed_d;
// Channel 1
if(ci2cf_C1TxAlmFull==0)
begin
//The first write request should be DSM initialization
if( ci2cf_InitDn && dsm_base_valid_q && !afuid_updtd )
begin
afuid_updtd <= 1;
cf2ci_C1TxHdr <= {
5'h0, // [60:56] Byte Enable
WrLine, // [55:52] Request Type
6'h00, // [51:46] Rsvd
ds_afuid_address, // [44:14] Address
14'h3ffe // [13:0] Meta data to track the SPL requests
};
cf2ci_C1TxWrValid <= 1;
cf2ci_C1TxData <= { 368'h0, // [512:144] Zeros
VERSION , // [143:128] Version #2
MICRO_BENCH // [127:0] AFU ID
};
end
else if (re2xy_go) //Executing real tasks
begin
if(task_completed == 'b1)
begin
cf2ci_C1TxWrValid <= 1'b1;
cf2ci_C1TxHdr <= {
5'h0,
WrLine,
6'h00,
ds_stat_address,
14'h3fff
};
cf2ci_C1TxData <= 'b1; // task completed
end
else if( WrHdr_valid ) // Write to Destination Workspace
begin
cf2ci_C1TxHdr <= WrHdr;
cf2ci_C1TxWrValid <= 1'b1;
cf2ci_C1TxData <= WrData;
end
end // re2xy_go
end // C1_TxAmlFull
// Channel 0
if( re2xy_go
&& RdHdr_valid && !ci2cf_C0TxAlmFull ) // Read from Source Workspace
begin //----------------------------------
cf2ci_C0TxHdr <= RdHdr;
cf2ci_C0TxRdValid <= 'b1;
end
/* synthesis translate_off */
if(cf2ci_C1TxWrValid)
$display("*Req Type: %x \t Addr: %x \n Data: %x", cf2ci_C1TxHdr[55:52], cf2ci_C1TxHdr[45:14], cf2ci_C1TxData);
if(cf2ci_C0TxRdValid)
$display("*Req Type: %x \t Addr: %x", cf2ci_C0TxHdr[55:52], cf2ci_C0TxHdr[45:14]);
/* synthesis translate_on */
end
end
//-------------------------
//Handle Responses
//-------------------------
//We have already handled Cfg Responses in the Configuration Mode
//We do not need to care about Write Responses
//Only Read Responses are considered
always @ (posedge clk)
begin
if (!reset_n)
begin
RdData <= 'b0;
end
else
begin
if (rb2cf_C0RxRdValid)
RdData <= rb2cf_C0RxData;
end
end
// Function: Returns physical address for a DSM register
function automatic [31:0] dsm_offset2addr;
input [9:0] offset_b;
input [63:0] base_b;
begin
dsm_offset2addr = base_b[37:6] + offset_b[9:6];
end
endfunction
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41AI_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O41AI_PP_BLACKBOX_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o41ai (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41AI_PP_BLACKBOX_V
|
// -*- verilog -*-
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
module qa_contents
#(
parameter WIDTH = 32,
parameter MWIDTH = 1
)
(
input wire clk,
input wire rst_n,
input wire [WIDTH-1:0] in_data,
input wire in_nd,
input wire [MWIDTH-1:0] in_m,
input wire [`MSG_WIDTH-1:0] in_msg,
input wire in_msg_nd,
output wire [WIDTH-1:0] out_data,
output reg out_nd,
output reg [MWIDTH-1:0] out_m,
output wire [`MSG_WIDTH-1:0] out_msg,
output wire out_msg_nd,
output reg error
);
wire [WIDTH/2-1:0] x;
wire [WIDTH/2-1:0] y;
wire [WIDTH/2-1:0] z;
assign x = in_data[WIDTH-1:WIDTH/2];
assign y = in_data[WIDTH/2-1:0];
assign out_data = {{WIDTH/2{1'b0}}, z};
always @ (posedge clk)
if (~rst_n)
error <= 1'b0;
else
begin
out_nd <= in_nd;
end
multiply #(WIDTH/2) multiply_0
(.clk(clk),
.rst_n(rst_n),
.x(x),
.y(y),
.z(z)
);
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLCLKP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__SDLCLKP_BEHAVIORAL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hvl__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
wire GCLK_b ;
reg notifier ;
wire awake ;
wire SCE_awake ;
wire GATE_awake ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK_delayed );
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK_b , m0n, CLK_delayed );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (GCLK , GCLK_b, VPWR, VGND );
assign awake = ( VPWR === 1'b1 );
assign SCE_awake = ( ( GATE_delayed === 1'b0 ) & awake );
assign GATE_awake = ( ( SCE_delayed === 1'b0 ) & awake );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLCLKP_BEHAVIORAL_V |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.