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//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's CPU ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ, ////
//// ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_cpu.v,v $
// Revision 1.2 2006-12-22 08:34:00 vak
// The design is successfully compiled using on-chip RAM.
//
// Revision 1.1 2006/12/21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.16 2005/01/07 09:28:37 andreje
// flag for l.cmov instruction added
//
// Revision 1.15 2004/05/09 19:49:04 lampret
// Added some l.cust5 custom instructions as example
//
// Revision 1.14 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.12.4.2 2004/02/11 01:40:11 lampret
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
//
// Revision 1.12.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.12 2002/09/07 05:42:02 lampret
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
//
// Revision 1.11 2002/08/28 01:44:25 lampret
// Removed some commented RTL. Fixed SR/ESR flag bug.
//
// Revision 1.10 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.9 2002/03/29 16:29:37 lampret
// Fixed some ports in instnatiations that were removed from the modules
//
// Revision 1.8 2002/03/29 15:16:54 lampret
// Some of the warnings fixed.
//
// Revision 1.7 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.6 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
// Revision 1.5 2002/01/28 01:15:59 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.4 2002/01/18 14:21:43 lampret
// Fixed 'the NPC single-step fix'.
//
// Revision 1.3 2002/01/18 07:56:00 lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.19 2001/11/30 18:59:47 simons
// *** empty log message ***
//
// Revision 1.18 2001/11/23 21:42:31 simons
// Program counter divided to PPC and NPC.
//
// Revision 1.17 2001/11/23 08:38:51 lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.16 2001/11/20 00:57:22 lampret
// Fixed width of du_except.
//
// Revision 1.15 2001/11/18 09:58:28 lampret
// Fixed some l.trap typos.
//
// Revision 1.14 2001/11/18 08:36:28 lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.13 2001/11/13 10:02:21 lampret
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
//
// Revision 1.12 2001/11/12 01:45:40 lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.11 2001/11/10 03:43:57 lampret
// Fixed exceptions.
//
// Revision 1.10 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.9 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.4 2001/08/17 08:01:19 lampret
// IC enable/disable.
//
// Revision 1.3 2001/08/13 03:36:20 lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_cpu(
// Clk & Rst
clk, rst,
// Insn interface
ic_en,
icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
immu_en,
// Debug unit
ex_insn, ex_freeze, id_pc, branch_op,
spr_dat_npc, rf_dataw,
du_stall, du_addr, du_dat_du, du_read, du_write, du_dsr, du_hwbkpt,
du_except, du_dat_cpu,
// Data interface
dc_en,
dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
dmmu_en,
// Interrupt & tick exceptions
sig_int, sig_tick,
// SPR interface
supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm,
spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
//
// I/O ports
//
//
// Clk & Rst
//
input clk;
input rst;
//
// Insn (IC) interface
//
output ic_en;
output [31:0] icpu_adr_o;
output icpu_cycstb_o;
output [3:0] icpu_sel_o;
output [3:0] icpu_tag_o;
input [31:0] icpu_dat_i;
input icpu_ack_i;
input icpu_rty_i;
input icpu_err_i;
input [31:0] icpu_adr_i;
input [3:0] icpu_tag_i;
//
// Insn (IMMU) interface
//
output immu_en;
//
// Debug interface
//
output [31:0] ex_insn;
output ex_freeze;
output [31:0] id_pc;
output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
input du_stall;
input [dw-1:0] du_addr;
input [dw-1:0] du_dat_du;
input du_read;
input du_write;
input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
input du_hwbkpt;
output [12:0] du_except;
output [dw-1:0] du_dat_cpu;
output [dw-1:0] rf_dataw;
//
// Data (DC) interface
//
output [31:0] dcpu_adr_o;
output dcpu_cycstb_o;
output dcpu_we_o;
output [3:0] dcpu_sel_o;
output [3:0] dcpu_tag_o;
output [31:0] dcpu_dat_o;
input [31:0] dcpu_dat_i;
input dcpu_ack_i;
input dcpu_rty_i;
input dcpu_err_i;
input [3:0] dcpu_tag_i;
output dc_en;
//
// Data (DMMU) interface
//
output dmmu_en;
//
// SPR interface
//
output supv;
input [dw-1:0] spr_dat_pic;
input [dw-1:0] spr_dat_tt;
input [dw-1:0] spr_dat_pm;
input [dw-1:0] spr_dat_dmmu;
input [dw-1:0] spr_dat_immu;
input [dw-1:0] spr_dat_du;
output [dw-1:0] spr_addr;
output [dw-1:0] spr_dat_cpu;
output [dw-1:0] spr_dat_npc;
output [31:0] spr_cs;
output spr_we;
//
// Interrupt exceptions
//
input sig_int;
input sig_tick;
//
// Internal wires
//
wire [31:0] if_insn;
wire [31:0] if_pc;
wire [31:2] lr_sav;
wire [aw-1:0] rf_addrw;
wire [aw-1:0] rf_addra;
wire [aw-1:0] rf_addrb;
wire rf_rda;
wire rf_rdb;
wire [dw-1:0] simm;
wire [dw-1:2] branch_addrofs;
wire [`OR1200_ALUOP_WIDTH-1:0] alu_op;
wire [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
wire [`OR1200_COMPOP_WIDTH-1:0] comp_op;
wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
wire [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
wire genpc_freeze;
wire if_freeze;
wire id_freeze;
wire ex_freeze;
wire wb_freeze;
wire [`OR1200_SEL_WIDTH-1:0] sel_a;
wire [`OR1200_SEL_WIDTH-1:0] sel_b;
wire [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
wire [dw-1:0] rf_dataw;
wire [dw-1:0] rf_dataa;
wire [dw-1:0] rf_datab;
wire [dw-1:0] muxed_b;
wire [dw-1:0] wb_forw;
wire wbforw_valid;
wire [dw-1:0] operand_a;
wire [dw-1:0] operand_b;
wire [dw-1:0] alu_dataout;
wire [dw-1:0] lsu_dataout;
wire [dw-1:0] sprs_dataout;
wire [31:0] lsu_addrofs;
wire [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
wire [`OR1200_EXCEPT_WIDTH-1:0] except_type;
wire [4:0] cust5_op;
wire [5:0] cust5_limm;
wire flushpipe;
wire extend_flush;
wire branch_taken;
wire flag;
wire flagforw;
wire flag_we;
wire carry;
wire cyforw;
wire cy_we;
wire lsu_stall;
wire epcr_we;
wire eear_we;
wire esr_we;
wire pc_we;
wire [31:0] epcr;
wire [31:0] eear;
wire [`OR1200_SR_WIDTH-1:0] esr;
wire sr_we;
wire [`OR1200_SR_WIDTH-1:0] to_sr;
wire [`OR1200_SR_WIDTH-1:0] sr;
wire except_start;
wire except_started;
wire [31:0] wb_insn;
wire [15:0] spr_addrimm;
wire sig_syscall;
wire sig_trap;
wire [31:0] spr_dat_cfgr;
wire [31:0] spr_dat_rf;
wire [31:0] spr_dat_npc;
wire [31:0] spr_dat_ppc;
wire [31:0] spr_dat_mac;
wire force_dslot_fetch;
wire no_more_dslot;
wire ex_void;
wire if_stall;
wire id_macrc_op;
wire ex_macrc_op;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
wire [31:0] mult_mac_result;
wire mac_stall;
wire [12:0] except_stop;
wire genpc_refetch;
wire rfe;
wire lsu_unstall;
wire except_align;
wire except_dtlbmiss;
wire except_dmmufault;
wire except_illegal;
wire except_itlbmiss;
wire except_immufault;
wire except_ibuserr;
wire except_dbuserr;
wire abort_ex;
//
// Send exceptions to Debug Unit
//
assign du_except = except_stop;
//
// Data cache enable
//
assign dc_en = sr[`OR1200_SR_DCE];
//
// Instruction cache enable
//
assign ic_en = sr[`OR1200_SR_ICE];
//
// DMMU enable
//
assign dmmu_en = sr[`OR1200_SR_DME];
//
// IMMU enable
//
assign immu_en = sr[`OR1200_SR_IME];
//
// SUPV bit
//
assign supv = sr[`OR1200_SR_SM];
//
// Instantiation of instruction fetch block
//
or1200_genpc or1200_genpc(
.clk(clk),
.rst(rst),
.icpu_adr_o(icpu_adr_o),
.icpu_cycstb_o(icpu_cycstb_o),
.icpu_sel_o(icpu_sel_o),
.icpu_tag_o(icpu_tag_o),
.icpu_rty_i(icpu_rty_i),
.icpu_adr_i(icpu_adr_i),
.branch_op(branch_op),
.except_type(except_type),
.except_start(except_start),
.except_prefix(sr[`OR1200_SR_EPH]),
.branch_addrofs(branch_addrofs),
.lr_restor(operand_b),
.flag(flag),
.taken(branch_taken),
.binsn_addr(lr_sav),
.epcr(epcr),
.spr_dat_i(spr_dat_cpu),
.spr_pc_we(pc_we),
.genpc_refetch(genpc_refetch),
.genpc_freeze(genpc_freeze),
.no_more_dslot(no_more_dslot)
);
//
// Instantiation of instruction fetch block
//
or1200_if or1200_if(
.clk(clk),
.rst(rst),
.icpu_dat_i(icpu_dat_i),
.icpu_ack_i(icpu_ack_i),
.icpu_err_i(icpu_err_i),
.icpu_adr_i(icpu_adr_i),
.icpu_tag_i(icpu_tag_i),
.if_freeze(if_freeze),
.if_insn(if_insn),
.if_pc(if_pc),
.flushpipe(flushpipe),
.if_stall(if_stall),
.no_more_dslot(no_more_dslot),
.genpc_refetch(genpc_refetch),
.rfe(rfe),
.except_itlbmiss(except_itlbmiss),
.except_immufault(except_immufault),
.except_ibuserr(except_ibuserr)
);
//
// Instantiation of instruction decode/control logic
//
or1200_ctrl or1200_ctrl(
.clk(clk),
.rst(rst),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
.wb_freeze(wb_freeze),
.flushpipe(flushpipe),
.if_insn(if_insn),
.ex_insn(ex_insn),
.branch_op(branch_op),
.branch_taken(branch_taken),
.rf_addra(rf_addra),
.rf_addrb(rf_addrb),
.rf_rda(rf_rda),
.rf_rdb(rf_rdb),
.alu_op(alu_op),
.mac_op(mac_op),
.shrot_op(shrot_op),
.comp_op(comp_op),
.rf_addrw(rf_addrw),
.rfwb_op(rfwb_op),
.wb_insn(wb_insn),
.simm(simm),
.branch_addrofs(branch_addrofs),
.lsu_addrofs(lsu_addrofs),
.sel_a(sel_a),
.sel_b(sel_b),
.lsu_op(lsu_op),
.cust5_op(cust5_op),
.cust5_limm(cust5_limm),
.multicycle(multicycle),
.spr_addrimm(spr_addrimm),
.wbforw_valid(wbforw_valid),
.sig_syscall(sig_syscall),
.sig_trap(sig_trap),
.force_dslot_fetch(force_dslot_fetch),
.no_more_dslot(no_more_dslot),
.ex_void(ex_void),
.id_macrc_op(id_macrc_op),
.ex_macrc_op(ex_macrc_op),
.rfe(rfe),
.du_hwbkpt(du_hwbkpt),
.except_illegal(except_illegal)
);
//
// Instantiation of register file
//
or1200_rf or1200_rf(
.clk(clk),
.rst(rst),
.supv(sr[`OR1200_SR_SM]),
.wb_freeze(wb_freeze),
.addrw(rf_addrw),
.dataw(rf_dataw),
.id_freeze(id_freeze),
.we(rfwb_op[0]),
.flushpipe(flushpipe),
.addra(rf_addra),
.rda(rf_rda),
.dataa(rf_dataa),
.addrb(rf_addrb),
.rdb(rf_rdb),
.datab(rf_datab),
.spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_rf)
);
//
// Instantiation of operand muxes
//
or1200_operandmuxes or1200_operandmuxes(
.clk(clk),
.rst(rst),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
.rf_dataa(rf_dataa),
.rf_datab(rf_datab),
.ex_forw(rf_dataw),
.wb_forw(wb_forw),
.simm(simm),
.sel_a(sel_a),
.sel_b(sel_b),
.operand_a(operand_a),
.operand_b(operand_b),
.muxed_b(muxed_b)
);
//
// Instantiation of CPU's ALU
//
or1200_alu or1200_alu(
.a(operand_a),
.b(operand_b),
.mult_mac_result(mult_mac_result),
.macrc_op(ex_macrc_op),
.alu_op(alu_op),
.shrot_op(shrot_op),
.comp_op(comp_op),
.cust5_op(cust5_op),
.cust5_limm(cust5_limm),
.result(alu_dataout),
.flagforw(flagforw),
.flag_we(flag_we),
.cyforw(cyforw),
.cy_we(cy_we),
.flag(flag),
.carry(carry)
);
//
// Instantiation of CPU's ALU
//
or1200_mult_mac or1200_mult_mac(
.clk(clk),
.rst(rst),
.ex_freeze(ex_freeze),
.id_macrc_op(id_macrc_op),
.macrc_op(ex_macrc_op),
.a(operand_a),
.b(operand_b),
.mac_op(mac_op),
.alu_op(alu_op),
.result(mult_mac_result),
.mac_stall_r(mac_stall),
.spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_mac)
);
//
// Instantiation of CPU's SPRS block
//
or1200_sprs or1200_sprs(
.clk(clk),
.rst(rst),
.addrbase(operand_a),
.addrofs(spr_addrimm),
.dat_i(operand_b),
.alu_op(alu_op),
.flagforw(flagforw),
.flag_we(flag_we),
.flag(flag),
.cyforw(cyforw),
.cy_we(cy_we),
.carry(carry),
.to_wbmux(sprs_dataout),
.du_addr(du_addr),
.du_dat_du(du_dat_du),
.du_read(du_read),
.du_write(du_write),
.du_dat_cpu(du_dat_cpu),
.spr_addr(spr_addr),
.spr_dat_pic(spr_dat_pic),
.spr_dat_tt(spr_dat_tt),
.spr_dat_pm(spr_dat_pm),
.spr_dat_cfgr(spr_dat_cfgr),
.spr_dat_rf(spr_dat_rf),
.spr_dat_npc(spr_dat_npc),
.spr_dat_ppc(spr_dat_ppc),
.spr_dat_mac(spr_dat_mac),
.spr_dat_dmmu(spr_dat_dmmu),
.spr_dat_immu(spr_dat_immu),
.spr_dat_du(spr_dat_du),
.spr_dat_o(spr_dat_cpu),
.spr_cs(spr_cs),
.spr_we(spr_we),
.epcr_we(epcr_we),
.eear_we(eear_we),
.esr_we(esr_we),
.pc_we(pc_we),
.epcr(epcr),
.eear(eear),
.esr(esr),
.except_started(except_started),
.sr_we(sr_we),
.to_sr(to_sr),
.sr(sr),
.branch_op(branch_op)
);
//
// Instantiation of load/store unit
//
or1200_lsu or1200_lsu(
.addrbase(operand_a),
.addrofs(lsu_addrofs),
.lsu_op(lsu_op),
.lsu_datain(operand_b),
.lsu_dataout(lsu_dataout),
.lsu_stall(lsu_stall),
.lsu_unstall(lsu_unstall),
.du_stall(du_stall),
.except_align(except_align),
.except_dtlbmiss(except_dtlbmiss),
.except_dmmufault(except_dmmufault),
.except_dbuserr(except_dbuserr),
.dcpu_adr_o(dcpu_adr_o),
.dcpu_cycstb_o(dcpu_cycstb_o),
.dcpu_we_o(dcpu_we_o),
.dcpu_sel_o(dcpu_sel_o),
.dcpu_tag_o(dcpu_tag_o),
.dcpu_dat_o(dcpu_dat_o),
.dcpu_dat_i(dcpu_dat_i),
.dcpu_ack_i(dcpu_ack_i),
.dcpu_rty_i(dcpu_rty_i),
.dcpu_err_i(dcpu_err_i),
.dcpu_tag_i(dcpu_tag_i)
);
//
// Instantiation of write-back muxes
//
or1200_wbmux or1200_wbmux(
.clk(clk),
.rst(rst),
.wb_freeze(wb_freeze),
.rfwb_op(rfwb_op),
.muxin_a(alu_dataout),
.muxin_b(lsu_dataout),
.muxin_c(sprs_dataout),
.muxin_d({lr_sav, 2'b0}),
.muxout(rf_dataw),
.muxreg(wb_forw),
.muxreg_valid(wbforw_valid)
);
//
// Instantiation of freeze logic
//
or1200_freeze or1200_freeze(
.clk(clk),
.rst(rst),
.multicycle(multicycle),
.flushpipe(flushpipe),
.extend_flush(extend_flush),
.lsu_stall(lsu_stall),
.if_stall(if_stall),
.lsu_unstall(lsu_unstall),
.force_dslot_fetch(force_dslot_fetch),
.abort_ex(abort_ex),
.du_stall(du_stall),
.mac_stall(mac_stall),
.genpc_freeze(genpc_freeze),
.if_freeze(if_freeze),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
.wb_freeze(wb_freeze),
.icpu_ack_i(icpu_ack_i),
.icpu_err_i(icpu_err_i)
);
//
// Instantiation of exception block
//
or1200_except or1200_except(
.clk(clk),
.rst(rst),
.sig_ibuserr(except_ibuserr),
.sig_dbuserr(except_dbuserr),
.sig_illegal(except_illegal),
.sig_align(except_align),
.sig_range(1'b0),
.sig_dtlbmiss(except_dtlbmiss),
.sig_dmmufault(except_dmmufault),
.sig_int(sig_int),
.sig_syscall(sig_syscall),
.sig_trap(sig_trap),
.sig_itlbmiss(except_itlbmiss),
.sig_immufault(except_immufault),
.sig_tick(sig_tick),
.branch_taken(branch_taken),
.icpu_ack_i(icpu_ack_i),
.icpu_err_i(icpu_err_i),
.dcpu_ack_i(dcpu_ack_i),
.dcpu_err_i(dcpu_err_i),
.genpc_freeze(genpc_freeze),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
.wb_freeze(wb_freeze),
.if_stall(if_stall),
.if_pc(if_pc),
.id_pc(id_pc),
.lr_sav(lr_sav),
.flushpipe(flushpipe),
.extend_flush(extend_flush),
.except_type(except_type),
.except_start(except_start),
.except_started(except_started),
.except_stop(except_stop),
.ex_void(ex_void),
.spr_dat_ppc(spr_dat_ppc),
.spr_dat_npc(spr_dat_npc),
.datain(operand_b),
.du_dsr(du_dsr),
.epcr_we(epcr_we),
.eear_we(eear_we),
.esr_we(esr_we),
.pc_we(pc_we),
.epcr(epcr),
.eear(eear),
.esr(esr),
.lsu_addr(dcpu_adr_o),
.sr_we(sr_we),
.to_sr(to_sr),
.sr(sr),
.abort_ex(abort_ex)
);
//
// Instantiation of configuration registers
//
or1200_cfgr or1200_cfgr(
.spr_addr(spr_addr),
.spr_dat_o(spr_dat_cfgr)
);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module start_for_CvtColokbM_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd5;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module start_for_CvtColokbM (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd5;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_CvtColokbM_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_start_for_CvtColokbM_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CONB_PP_SYMBOL_V
`define SKY130_FD_SC_MS__CONB_PP_SYMBOL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__conb (
//# {{data|Data Signals}}
output HI ,
output LO ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CONB_PP_SYMBOL_V
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
`define HOST_DATA_DELAY_FIXED
module sd_host_platform_spartan6 #(
parameter OUTPUT_DELAY = 0,
parameter INPUT_DELAY = 0
)(
input rst,
input clk,
output o_locked,
input i_read_wait,
output o_sd_clk,
input i_sd_data_dir,
input [7:0] i_sd_data_out,
output [7:0] o_sd_data_in,
input i_sd_cmd_dir,
input i_sd_cmd_out,
output o_sd_cmd_in,
//Configuration
input i_cfg_inc,
input i_cfg_en,
output o_phy_clk,
inout io_phy_cmd,
inout [3:0] io_phy_data
);
//local parameters
localparam USER_RESET_TIMEOUT = 4'hF;
//registes/wires
wire [7:0] sd_data_out;
wire pll_serdes_clk;
wire pll_sd_clk;
wire ddr_clk_delay;
wire ddr_clk;
wire sd_cmd_tristate_dly;
wire sd_cmd_out_delay;
wire sd_cmd_in_delay;
wire [3:0] pin_data_out;
wire [3:0] pin_data_in;
wire [3:0] pin_data_tristate;
wire [3:0] pin_data_out_delay;
wire [3:0] pin_data_in_predelay;
wire [3:0] pin_data_tristate_predelay;
wire serdes_strobe;
wire din_serdes_strobe_buf;
reg sd_clk;
//wire !o_sd_clk;
reg user_reset = 1;
reg [3:0] user_reset_count = 0;
wire sd_data_direction;
//submodules
//Generate the SERDES
//Clock will be used to drive both the output and the internal state machine
//Take the output of the delay buffer and send it through ODDR2
ODDR2 #(
.DDR_ALIGNMENT ("NONE" ),
.INIT (1'b0 ),
.SRTYPE ("SYNC" )
) oddr2_clk (
.D0 (1'b1 ),
.D1 (1'b0 ),
.C0 (o_sd_clk ),
.C1 (!o_sd_clk ),
.CE (1'b1 ),
.Q (o_phy_clk ),
.R (1'b0 ),
.S (1'b0 )
);
//Internal Clock Interface
//Control Line
IOBUF #(
.IOSTANDARD ("LVCMOS33" )
) cmd_iobuf (
.T (sd_cmd_tristate_dly ),
.O (sd_cmd_in_delay ),
.I (sd_cmd_out_delay ),
.IO (io_phy_cmd )
);
IODELAY2 #(
.DATA_RATE ("SDR" ),
.IDELAY_VALUE (INPUT_DELAY ),
.ODELAY_VALUE (OUTPUT_DELAY ),
.IDELAY_TYPE ("FIXED" ),
.COUNTER_WRAPAROUND ("STAY_AT_LIMIT" ),
.DELAY_SRC ("IO" ),
.SERDES_MODE ("NONE" ),
.SIM_TAPDELAY_VALUE (75 )
) cmd_delay (
.T (!i_sd_cmd_dir ),
.ODATAIN (i_sd_cmd_out ),
//.DATAOUT (o_sd_cmd_in ),
.DATAOUT2 (o_sd_cmd_in ),
//FPGA Fabric
//IOB
.TOUT (sd_cmd_tristate_dly ),
.IDATAIN (sd_cmd_in_delay ),
.DOUT (sd_cmd_out_delay ),
.IOCLK0 (o_sd_clk ),
//.IOCLK1 (!o_sd_clk ),
.CAL (1'b0 ),
.BUSY ( ),
.CLK (clk ),
.INC (i_cfg_inc ),
.CE (i_cfg_en ),
.RST (rst )
);
//DATA Lines
wire [3:0] sd_data_dir;
wire [3:0] sd_data_dir_predelay;
assign sd_data_dir = {sd_data_direction, sd_data_direction, sd_data_direction, sd_data_direction};
genvar pcnt;
generate
for (pcnt = 0; pcnt < 4; pcnt = pcnt + 1) begin: sgen
IOBUF #(
.IOSTANDARD ("LVCMOS33" )
) io_data_buffer (
.T (pin_data_tristate[pcnt] ),
.I (pin_data_out[pcnt] ),
.O (pin_data_in[pcnt] ),
.IO (io_phy_data[pcnt] )
);
IODELAY2 #(
.DATA_RATE ("DDR" ),
`ifdef HOST_DATA_DELAY_FIXED
.IDELAY_TYPE ("FIXED" ),
.IDELAY_VALUE (INPUT_DELAY ),
.ODELAY_VALUE (OUTPUT_DELAY ),
`else
.IDELAY_TYPE ("VARIABLE_FROM_ZERO" ),
.ODELAY_VALUE (0 ),
`endif
.COUNTER_WRAPAROUND ("STAY_AT_LIMIT" ),
.DELAY_SRC ("IO" ),
.SERDES_MODE ("NONE" ),
.SIM_TAPDELAY_VALUE (75 )
)sd_data_delay(
//IOSerdes
//.T (1'b0),
.T (sd_data_dir_predelay[pcnt] ),
.ODATAIN (pin_data_in_predelay[pcnt] ),
.DATAOUT (pin_data_out_delay[pcnt] ),
//To/From IO Buffer
.TOUT (pin_data_tristate[pcnt] ),
.IDATAIN (pin_data_in[pcnt] ),
.DOUT (pin_data_out[pcnt] ),
.BUSY ( ),
.CAL (1'b0 ),
.IOCLK0 (o_sd_clk ),
.IOCLK1 (!o_sd_clk ),
`ifdef HOST_DATA_DELAY_FIXED
.CLK (1'b0 ),
.INC (1'b0 ),
.CE (1'b0 ),
.RST (1'b0 )
`else
.CLK (clk ),
.INC (i_cfg_inc ),
.CE (i_cfg_en ),
.RST (rst )
`endif
);
ODDR2 #(
.DDR_ALIGNMENT ("C0" ),
.SRTYPE ("ASYNC" ),
.INIT (1 )
) data_dir_ddr (
.C0 (o_sd_clk ),
.C1 (!o_sd_clk ),
.CE (1'b1 ),
.S (1'b0 ),
.R (1'b0 ),
.D0 (sd_data_dir[pcnt] ),
.D1 (sd_data_dir[pcnt] ),
// .D0 (1'b0 ),
// .D1 (1'b0 ),
.Q (sd_data_dir_predelay[pcnt] )
);
IDDR2 #(
//.DDR_ALIGNMENT ("NONE" ),
.DDR_ALIGNMENT ("C0" ),
.INIT_Q0 (1 ),
.INIT_Q1 (1 ),
.SRTYPE ("ASYNC" )
//.SRTYPE ("SYNC" )
) data_in_ddr (
.C0 (o_sd_clk ),
.C1 (!o_sd_clk ),
.CE (1'b1 ),
.S (1'b0 ),
.R (1'b0 ),
.D (pin_data_out_delay[pcnt] ),
.Q0 (o_sd_data_in[pcnt] ),
.Q1 (o_sd_data_in[pcnt + 4] )
);
ODDR2 #(
// .DDR_ALIGNMENT ("NONE" ),
// .SRTYPE ("SYNC" ),
.DDR_ALIGNMENT ("C0" ),
.SRTYPE ("ASYNC" ),
.INIT (1 )
) data_out_ddr (
.C0 (o_sd_clk ),
.C1 (!o_sd_clk ),
.CE (1'b1 ),
.S (1'b0 ),
.R (1'b0 ),
.D0 (sd_data_out[pcnt + 4] ),
.D1 (sd_data_out[pcnt] ),
// .D0 (1'b0 ),
// .D1 (1'b0 ),
.Q (pin_data_in_predelay[pcnt] )
);
end
//`define ADJUSTABLE_DELAY
endgenerate
BUFG sd_clk_buffer_p(
.I (sd_clk ),
.O (o_sd_clk )
);
/*
BUFG sd_clk_buffer_n(
.I (!sd_clk ),
.O (!o_sd_clk )
);
*/
//asynchronous logic
assign sd_data_out = i_read_wait ? {1'b1, 1'b0, 1'b1, 1'b1, 1'b1, 1'b0, 1'b1, 1'b1}:
i_sd_data_out;
//assign sd_data_out = i_sd_data_out;
assign sd_data_direction = (!i_sd_data_dir && !i_read_wait);
//assign sd_data_direction = (!i_sd_data_dir);
assign o_locked = !user_reset;
//Synchronous Logic
reg [7:0] count;
always @ (posedge clk) begin
if (rst) begin
sd_clk <= 0;
count <= 0;
end
else begin
if (count < 4) begin
count <= count + 1;
end
else begin
sd_clk <= ~sd_clk;
count <= 0;
end
end
end
initial begin
user_reset_count <= 0;
end
always @ (posedge o_sd_clk or posedge rst) begin
if (rst) begin
user_reset <= 1;
user_reset_count <= 0;
end
else begin
if (user_reset_count < USER_RESET_TIMEOUT) begin
user_reset_count <= user_reset_count + 1;
end
else begin
user_reset <= 0;
end
end
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file spartan6_dmem.v when simulating
// the core, spartan6_dmem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module spartan6_dmem(
clka,
ena,
wea,
addra,
dina,
douta);
input clka;
input ena;
input [1 : 0] wea;
input [9 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V3_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan6"),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_WEA_WIDTH(2),
.C_WEB_WIDTH(2),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan6"))
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of spartan6_dmem is "black_box"
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1N_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__INPUTISO1N_PP_BLACKBOX_V
/**
* inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__inputiso1n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1N_PP_BLACKBOX_V
|
module processor(clock);
/* Instruction Register Detail
31:28 - Opcode
27:24 - CC
27 - Source Type (0 = reg || mem, 1 = imm)
26 - Destination Type (0 = reg, 1 = imm)
23:12 - Source address
23:12 - Shift/Rotate Count
11:0 - Destination Address
*/
input clock;
reg [31:0] memory [4095:0]; //12-bit address allows 4096 possible memory addresses
reg [11:0] register [4:0]; //16 registers (i.e. 5-bit address) that are each 12-bits wide (maximum width of immediate value)
reg [23:0] doubleWidth;
reg [11:0] sourceValue, result;
reg signed [11:0] count;
reg [4:0] psr;
reg carry;
integer i, j, programCounter;
initial begin
//Instantiate Memory
memory[3] = {4'd2, 1'b1, 3'd0, 12'd6, 12'd0}; //Store 6 into mem0
memory[4] = {4'd1, 1'b0, 3'd0, 12'd0, 12'd0}; //Load mem0 into reg0
memory[5] = {4'd9, 1'b0, 1'b0, 2'd0, 12'd0, 12'd0}; //Complement reg0
memory[6] = {4'd5, 1'b1, 1'b0, 2'd0, 12'd1, 12'd0}; //Add reg 0 + 1
memory[7] = {4'd2, 1'b0, 3'd0, 12'd0, 12'd1}; //Store reg0 into me1
memory[8] = {4'd10, 28'd0}; //Count 1s
memory[9] = {4'd11, 28'd0}; //Multiply mem0 by mem1 and store into mem2
memory[10] = {4'd8, 28'd0}; //HALT
//Clear all other memory
for (i = 0; i < 3; i = i + 1) begin
memory[i] = 32'd0;
end
for (i = 10; i < 4096; i = i + 1) begin
memory[i] = 32'd0;
end
//Clear registers
for (i = 0; i < 5; i = i + 1) begin
register[i] = 12'd0;
end
programCounter = 3; //Sets program counter to 3, which we will be using for beginning all programs
doubleWidth = 24'd0;
sourceValue = 12'd0;
result = 12'd0;
carry = 1'b0;
end
always @(posedge clock) begin
getSourceValue;
//Clear carry, result, count, and doubleWidth
carry = 1'b0;
result = 12'd0;
count = 12'd0;
doubleWidth = 24'd0;
case (memory[programCounter][31:28])
4'd0: begin //NOP
programCounter = programCounter + 1;
end
4'd1: begin //LOAD
result = sourceValue;
register[memory[programCounter][11:0]] = result; //LOAD loads value from source into a register
setPSR;
programCounter = programCounter + 1;
end
4'd2: begin //STORE
memory[memory[programCounter][11:0]] = sourceValue; //STORE stores value from source into memory
clearPSR;
programCounter = programCounter + 1;
end
4'd3: begin //BRANCH
case (memory[programCounter][27:24]) //Condition code
4'd0: begin //Always
programCounter = programCounter + 1;
end
4'd1: begin //Parity
if (psr[1] == 1'b1) programCounter = memory[programCounter][11:0];
else programCounter = programCounter + 1;
end
4'd2: begin //Even
if (psr[2] == 1'b1) programCounter = memory[programCounter][11:0];
else programCounter = programCounter + 1;
end
4'd3: begin //Carry
if (psr[0] == 1'b1) programCounter = memory[programCounter][11:0];
else programCounter = programCounter + 1;
end
4'd4: begin //Negative
if (psr[3] == 1'b1) programCounter = memory[programCounter][11:0];
else programCounter = programCounter + 1;
end
4'd5: begin //Zero
if (psr[4] == 1'b1) programCounter = memory[programCounter][11:0];
else programCounter = programCounter + 1;
end
4'd6: begin //No Carry
if (psr[0] == 1'b0) programCounter = memory[programCounter][11:0];
else programCounter = programCounter + 1;
end
4'd7: begin //Positive
if (psr[3] == 1'b0) programCounter = memory[programCounter][11:0];
else programCounter = programCounter + 1;
end
endcase
end
4'd4: begin //XOR
register[memory[programCounter][11:0]] = register[memory[programCounter][11:0]] ^ sourceValue;
setPSR;
programCounter = programCounter + 1;
end
4'd5: begin //ADD
{carry, register[memory[programCounter][11:0]]} = register[memory[programCounter][11:0]] + sourceValue;
setPSR;
programCounter = programCounter + 1;
end
4'd6: begin //ROTATE
doubleWidth = {register[memory[programCounter][11:0]], register[memory[programCounter][11:0]]};
if (count > 0) //Rotate right
register[memory[programCounter][11:0]] = doubleWidth[24 - sourceValue -: 12];
else //Rotate left
register[memory[programCounter][11:0]] = doubleWidth[12 + sourceValue -: 12];
setPSR;
programCounter = programCounter + 1;
end
4'd7: begin //SHIFT
if (count > 0) //Shift right
register[memory[programCounter][11:0]] = count >> sourceValue;
else //Shift left
register[memory[programCounter][11:0]] = count << sourceValue;
setPSR;
programCounter = programCounter + 1;
end
4'd8: begin
$finish; //HALT
end
4'd9: begin //Complement
register[memory[programCounter][11:0]] = ~sourceValue;
programCounter = programCounter + 1;
end
4'd10: begin //1s count (problem 4)
j = 0;
for (i = 0; i < 12; i = i + 1)
if (memory[0][i] == 1'b1) j = j + 1;
memory[1] = j;
programCounter = programCounter + 1;
end
4'd11: begin //Multiply (problem 5)
memory[2] = memory[0] * memory[1];
programCounter = programCounter + 1;
end
endcase
end
task clearPSR; begin
psr = 5'd0;
end
endtask
task setPSR; begin
//Carry bit
if (carry == 1'b1) psr[0] = 1'b1;
else psr[0] = 1'b0;
//Parity bit
j = 0;
for (i = 0; i < 12; i = i + 1) begin
if (result[i] == 1) j = j + 1;
end
if (count % 2 == 0) psr[1] = 1'b1;
else psr[1] = 1'b0;
//Even and Odd bit
if (result % 2 == 0) begin
psr[2] = 1'b1;
psr[4] = 1'b0;
end
else begin
psr[2] = 1'b0;
psr[4] = 1'b1;
end
//Negative bit
if (result[11] == 1'b1) psr[3] = 1'b1;
else psr[3] = 1'b0;
end
endtask
task getSourceValue; begin
case (memory[programCounter][31:28])
4'd1: begin //LOAD source can be memory or immediate
if (memory[programCounter][27] == 1'b0)
sourceValue = memory[memory[programCounter][23:12]];
else
sourceValue = memory[programCounter][23:12];
end
4'd2, //STORE
4'd4, //XOR
4'd5, //ADD
4'd9: //COMPLEMENT
begin //Source can be register or immediate
if (memory[programCounter][27] == 1'b0)
sourceValue = register[memory[programCounter][23:12]];
else
sourceValue = memory[programCounter][23:12];
end
4'd6, //ROTATE
4'd7: //SHIFT
begin
count = memory[programCounter][23:12];
if (count[11] == 1'b0) sourceValue = count;
else sourceValue = {1'b0, count[10:0]} - 12'd2048;
end
default:
sourceValue = 12'd1;
endcase
end
endtask
endmodule |
module smallfifo16x(input rst,
input clk_in,
input [15:0] fifo_in,
input fifo_en,
output fifo_full,
input clk_out,
output [15:0] fifo_out,
output fifo_empty,
input fifo_rd);
vga_fifo_dc#(.AWIDTH(4),.DWIDTH(16))
fifo0(.rclk (clk_out),
.wclk (clk_in),
.rclr (~rst),
.wclr (~rst),
.wreq (fifo_en),
.d (fifo_in),
.rreq (fifo_rd),
.q (fifo_out),
.empty (fifo_empty),
.full (fifo_full));
endmodule
module soundctl (input clk,
input rst,
output sound_clr_full,
input [15:0] sound_clr_sample,
input [15:0] sound_clr_rate,
input sound_clr_req,
output reg pwm_out
);
wire [15:0] fifo_out;
wire fifo_empty;
reg fifo_rd;
smallfifo16x fifo1(.rst(rst),
.clk_in(clk),
.fifo_in(sound_clr_sample),
.fifo_en(sound_clr_req),
.fifo_full(sound_clr_full),
.clk_out(clk),
.fifo_out(fifo_out),
.fifo_empty(fifo_empty),
.fifo_rd(fifo_rd));
reg [15:0] counter;
reg [8:0] sample;
always @(posedge clk)
if (~rst) begin
fifo_rd <= 0;
counter <= 0;
pwm_out <= 0;
sample <= 1024; // 50% duty cycle default level
end else begin
pwm_out <= (counter < sample)?1:0;
if (fifo_rd) begin
sample <= fifo_out;
fifo_rd <= 0;
end
else if (counter >= sound_clr_rate) begin
counter <= 0;
if (~fifo_empty) fifo_rd <= 1; else begin
fifo_rd <= 0;
sample <= 1024;
end
end else begin
fifo_rd <= 0;
counter <= counter + 1;
end
end
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_LevelGateway(
input clock,
input reset,
input io_interrupt,
output io_plic_valid,
input io_plic_ready,
input io_plic_complete
);
reg inFlight;
reg [31:0] GEN_2;
wire T_12;
wire GEN_0;
wire GEN_1;
wire T_16;
wire T_17;
assign io_plic_valid = T_17;
assign T_12 = io_interrupt & io_plic_ready;
assign GEN_0 = T_12 ? 1'h1 : inFlight;
assign GEN_1 = io_plic_complete ? 1'h0 : GEN_0;
assign T_16 = inFlight == 1'h0;
assign T_17 = io_interrupt & T_16;
always @(posedge clock or posedge reset) begin
if (reset) begin
inFlight <= 1'h0;
end else begin
if (io_plic_complete) begin
inFlight <= 1'h0;
end else begin
if (T_12) begin
inFlight <= 1'h1;
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXTP_4_V
`define SKY130_FD_SC_LS__DFXTP_4_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog wrapper for dfxtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfxtp_4 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfxtp_4 (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXTP_4_V
|
/*
-- ============================================================================
-- FILE NAME : chip_top.v
-- DESCRIPTION : gbvW
[
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** ÂÊwb_t@C **********/
`include "gpio.h"
/********** W
[ **********/
module chip_top (
/********** NbN & Zbg **********/
input wire clk_ref, // îêNbN
input wire reset_sw // O[oZbg
/********** UART **********/
`ifdef IMPLEMENT_UART // UARTÀ
, input wire uart_rx // UARTóMM
, output wire uart_tx // UARTMM
`endif
/********** ÄpüoÍ|[g **********/
`ifdef IMPLEMENT_GPIO // GPIOÀ
`ifdef GPIO_IN_CH // üÍ|[gÌÀ
, input wire [`GPIO_IN_CH-1:0] gpio_in // üÍ|[g
`endif
`ifdef GPIO_OUT_CH // oÍ|[gÌÀ
, output wire [`GPIO_OUT_CH-1:0] gpio_out // oÍ|[g
`endif
`ifdef GPIO_IO_CH // üoÍ|[gÌÀ
, inout wire [`GPIO_IO_CH-1:0] gpio_io // üoÍ|[g
`endif
`endif
);
/********** NbN & Zbg **********/
wire clk; // NbN
wire clk_; // ½]NbN
wire chip_reset; // `bvZbg
/********** NbNW
[ **********/
clk_gen clk_gen (
/********** NbN & Zbg **********/
.clk_ref (clk_ref), // îêNbN
.reset_sw (reset_sw), // O[oZbg
/********** ¶¬NbN **********/
.clk (clk), // NbN
.clk_ (clk_), // ½]NbN
/********** `bvZbg **********/
.chip_reset (chip_reset) // `bvZbg
);
/********** `bv **********/
chip chip (
/********** NbN & Zbg **********/
.clk (clk), // NbN
.clk_ (clk_), // ½]NbN
.reset (chip_reset) // Zbg
/********** UART **********/
`ifdef IMPLEMENT_UART
, .uart_rx (uart_rx) // UARTóMg`
, .uart_tx (uart_tx) // UARTMg`
`endif
/********** ÄpüoÍ|[g **********/
`ifdef IMPLEMENT_GPIO
`ifdef GPIO_IN_CH // üÍ|[gÌÀ
, .gpio_in (gpio_in) // üÍ|[g
`endif
`ifdef GPIO_OUT_CH // oÍ|[gÌÀ
, .gpio_out (gpio_out) // oÍ|[g
`endif
`ifdef GPIO_IO_CH // üoÍ|[gÌÀ
, .gpio_io (gpio_io) // üoÍ|[g
`endif
`endif
);
endmodule
|
module fpu_add ( inq_op, inq_rnd_mode, inq_id, inq_fcc, inq_in1,
inq_in1_50_0_neq_0, inq_in1_53_32_neq_0, inq_in1_exp_eq_0,
inq_in1_exp_neq_ffs, inq_in2, inq_in2_50_0_neq_0, inq_in2_53_32_neq_0,
inq_in2_exp_eq_0, inq_in2_exp_neq_ffs, inq_add, add_dest_rdy,
fadd_clken_l, arst_l, grst_l, rclk, add_pipe_active, a1stg_step,
a6stg_fadd_in, add_id_out_in, a6stg_fcmpop, add_exc_out, a6stg_dbl_dst,
a6stg_sng_dst, a6stg_long_dst, a6stg_int_dst, add_sign_out,
add_exp_out, add_frac_out, add_cc_out, add_fcc_out, se_add_exp,
se_add_frac, si, so );
input [7:0] inq_op;
input [1:0] inq_rnd_mode;
input [4:0] inq_id;
input [1:0] inq_fcc;
input [63:0] inq_in1;
input [63:0] inq_in2;
output [9:0] add_id_out_in;
output [4:0] add_exc_out;
output [10:0] add_exp_out;
output [63:0] add_frac_out;
output [1:0] add_cc_out;
output [1:0] add_fcc_out;
input inq_in1_50_0_neq_0, inq_in1_53_32_neq_0, inq_in1_exp_eq_0,
inq_in1_exp_neq_ffs, inq_in2_50_0_neq_0, inq_in2_53_32_neq_0,
inq_in2_exp_eq_0, inq_in2_exp_neq_ffs, inq_add, add_dest_rdy,
fadd_clken_l, arst_l, grst_l, rclk, se_add_exp, se_add_frac, si;
output add_pipe_active, a1stg_step, a6stg_fadd_in, a6stg_fcmpop,
a6stg_dbl_dst, a6stg_sng_dst, a6stg_long_dst, a6stg_int_dst,
add_sign_out, so;
wire a1stg_fsdtoix, a1stg_faddsubs, a1stg_fdtos, a3stg_fdtos_inv,
\a4stg_shl_cnt[5] , \fpu_add_ctl/n941 , \fpu_add_ctl/n940 ,
\fpu_add_ctl/n939 , \fpu_add_ctl/n938 , \fpu_add_ctl/n937 ,
\fpu_add_ctl/n936 , \fpu_add_ctl/n470 , \fpu_add_ctl/n49 ,
\fpu_add_ctl/n47 , \fpu_add_ctl/n338 , \fpu_add_ctl/n337 ,
\fpu_add_ctl/n336 , \fpu_add_ctl/n335 , \fpu_add_ctl/n334 ,
\fpu_add_ctl/n333 , \fpu_add_ctl/n332 , \fpu_add_ctl/n330 ,
\fpu_add_ctl/n329 , \fpu_add_ctl/n328 , \fpu_add_ctl/n327 ,
\fpu_add_ctl/n326 , \fpu_add_ctl/n325 , \fpu_add_ctl/n324 ,
\fpu_add_ctl/n323 , \fpu_add_ctl/n322 , \fpu_add_ctl/n321 ,
\fpu_add_ctl/n320 , \fpu_add_ctl/n319 , \fpu_add_ctl/n318 ,
\fpu_add_ctl/n317 , \fpu_add_ctl/n316 , \fpu_add_ctl/n315 ,
\fpu_add_ctl/n314 , \fpu_add_ctl/n313 , \fpu_add_ctl/n312 ,
\fpu_add_ctl/n311 , \fpu_add_ctl/n310 , \fpu_add_ctl/n309 ,
\fpu_add_ctl/n308 , \fpu_add_ctl/n307 , \fpu_add_ctl/n303 ,
\fpu_add_ctl/n752 , \fpu_add_ctl/n751 , \fpu_add_ctl/n750 ,
\fpu_add_ctl/n749 , \fpu_add_ctl/n748 , \fpu_add_ctl/n747 ,
\fpu_add_ctl/n746 , \fpu_add_ctl/n745 , \fpu_add_ctl/n744 ,
\fpu_add_ctl/n743 , \fpu_add_ctl/n742 , \fpu_add_ctl/n741 ,
\fpu_add_ctl/n740 , \fpu_add_ctl/n739 , \fpu_add_ctl/n738 ,
\fpu_add_ctl/n737 , \fpu_add_ctl/n736 , \fpu_add_ctl/n735 ,
\fpu_add_ctl/n734 , \fpu_add_ctl/n733 , \fpu_add_ctl/n732 ,
\fpu_add_ctl/n731 , \fpu_add_ctl/n730 , \fpu_add_ctl/n729 ,
\fpu_add_ctl/n728 , \fpu_add_ctl/n727 , \fpu_add_ctl/n726 ,
\fpu_add_ctl/n725 , \fpu_add_ctl/n724 , \fpu_add_ctl/n723 ,
\fpu_add_ctl/n722 , \fpu_add_ctl/n721 , \fpu_add_ctl/n720 ,
\fpu_add_ctl/n719 , \fpu_add_ctl/n718 , \fpu_add_ctl/n717 ,
\fpu_add_ctl/n716 , \fpu_add_ctl/n715 , \fpu_add_ctl/n714 ,
\fpu_add_ctl/n713 , \fpu_add_ctl/n712 , \fpu_add_ctl/n711 ,
\fpu_add_ctl/n710 , \fpu_add_ctl/n709 , \fpu_add_ctl/n708 ,
\fpu_add_ctl/n707 , \fpu_add_ctl/n706 , \fpu_add_ctl/n705 ,
\fpu_add_ctl/n704 , \fpu_add_ctl/n703 , \fpu_add_ctl/n702 ,
\fpu_add_ctl/n701 , \fpu_add_ctl/n700 , \fpu_add_ctl/n699 ,
\fpu_add_ctl/n698 , \fpu_add_ctl/n697 , \fpu_add_ctl/n696 ,
\fpu_add_ctl/n695 , \fpu_add_ctl/n694 , \fpu_add_ctl/n693 ,
\fpu_add_ctl/n692 , \fpu_add_ctl/n691 , \fpu_add_ctl/n690 ,
\fpu_add_ctl/n689 , \fpu_add_ctl/n688 , \fpu_add_ctl/n687 ,
\fpu_add_ctl/n686 , \fpu_add_ctl/n685 , \fpu_add_ctl/n684 ,
\fpu_add_ctl/n683 , \fpu_add_ctl/n682 , \fpu_add_ctl/n681 ,
\fpu_add_ctl/n680 , \fpu_add_ctl/n679 , \fpu_add_ctl/n678 ,
\fpu_add_ctl/n677 , \fpu_add_ctl/n676 , \fpu_add_ctl/n675 ,
\fpu_add_ctl/n674 , \fpu_add_ctl/n673 , \fpu_add_ctl/n672 ,
\fpu_add_ctl/n671 , \fpu_add_ctl/n670 , \fpu_add_ctl/n669 ,
\fpu_add_ctl/n668 , \fpu_add_ctl/n667 , \fpu_add_ctl/n666 ,
\fpu_add_ctl/n665 , \fpu_add_ctl/n664 , \fpu_add_ctl/n663 ,
\fpu_add_ctl/n662 , \fpu_add_ctl/n661 , \fpu_add_ctl/n660 ,
\fpu_add_ctl/n659 , \fpu_add_ctl/n658 , \fpu_add_ctl/n657 ,
\fpu_add_ctl/n656 , \fpu_add_ctl/n655 , \fpu_add_ctl/n654 ,
\fpu_add_ctl/n653 , \fpu_add_ctl/n652 , \fpu_add_ctl/n651 ,
\fpu_add_ctl/n650 , \fpu_add_ctl/n649 , \fpu_add_ctl/n648 ,
\fpu_add_ctl/n647 , \fpu_add_ctl/n646 , \fpu_add_ctl/n645 ,
\fpu_add_ctl/n644 , \fpu_add_ctl/n643 , \fpu_add_ctl/n642 ,
\fpu_add_ctl/n641 , \fpu_add_ctl/n640 , \fpu_add_ctl/n639 ,
\fpu_add_ctl/n638 , \fpu_add_ctl/n637 , \fpu_add_ctl/n636 ,
\fpu_add_ctl/n635 , \fpu_add_ctl/n634 , \fpu_add_ctl/n633 ,
\fpu_add_ctl/n632 , \fpu_add_ctl/n631 , \fpu_add_ctl/n630 ,
\fpu_add_ctl/n629 , \fpu_add_ctl/n628 , \fpu_add_ctl/n627 ,
\fpu_add_ctl/n626 , \fpu_add_ctl/n625 , \fpu_add_ctl/n624 ,
\fpu_add_ctl/n623 , \fpu_add_ctl/n622 , \fpu_add_ctl/n621 ,
\fpu_add_ctl/n620 , \fpu_add_ctl/n619 , \fpu_add_ctl/n618 ,
\fpu_add_ctl/n617 , \fpu_add_ctl/n616 , \fpu_add_ctl/n615 ,
\fpu_add_ctl/n614 , \fpu_add_ctl/n613 , \fpu_add_ctl/n612 ,
\fpu_add_ctl/n611 , \fpu_add_ctl/n610 , \fpu_add_ctl/n609 ,
\fpu_add_ctl/n608 , \fpu_add_ctl/n607 , \fpu_add_ctl/n606 ,
\fpu_add_ctl/n605 , \fpu_add_ctl/n604 , \fpu_add_ctl/n603 ,
\fpu_add_ctl/n602 , \fpu_add_ctl/n601 , \fpu_add_ctl/n600 ,
\fpu_add_ctl/n599 , \fpu_add_ctl/n598 , \fpu_add_ctl/n597 ,
\fpu_add_ctl/n596 , \fpu_add_ctl/n595 , \fpu_add_ctl/n594 ,
\fpu_add_ctl/n593 , \fpu_add_ctl/n592 , \fpu_add_ctl/n591 ,
\fpu_add_ctl/n590 , \fpu_add_ctl/n589 , \fpu_add_ctl/n588 ,
\fpu_add_ctl/n587 , \fpu_add_ctl/n586 , \fpu_add_ctl/n585 ,
\fpu_add_ctl/n584 , \fpu_add_ctl/n583 , \fpu_add_ctl/n582 ,
\fpu_add_ctl/n581 , \fpu_add_ctl/n580 , \fpu_add_ctl/n579 ,
\fpu_add_ctl/n578 , \fpu_add_ctl/n577 , \fpu_add_ctl/n576 ,
\fpu_add_ctl/n575 , \fpu_add_ctl/n574 , \fpu_add_ctl/n573 ,
\fpu_add_ctl/n572 , \fpu_add_ctl/n571 , \fpu_add_ctl/n570 ,
\fpu_add_ctl/n569 , \fpu_add_ctl/n568 , \fpu_add_ctl/n567 ,
\fpu_add_ctl/n566 , \fpu_add_ctl/n565 , \fpu_add_ctl/n564 ,
\fpu_add_ctl/n563 , \fpu_add_ctl/n562 , \fpu_add_ctl/n561 ,
\fpu_add_ctl/n560 , \fpu_add_ctl/n559 , \fpu_add_ctl/n558 ,
\fpu_add_ctl/n557 , \fpu_add_ctl/n556 , \fpu_add_ctl/n555 ,
\fpu_add_ctl/n554 , \fpu_add_ctl/n553 , \fpu_add_ctl/n552 ,
\fpu_add_ctl/n551 , \fpu_add_ctl/n550 , \fpu_add_ctl/n549 ,
\fpu_add_ctl/n548 , \fpu_add_ctl/n547 , \fpu_add_ctl/n546 ,
\fpu_add_ctl/n545 , \fpu_add_ctl/n544 , \fpu_add_ctl/n543 ,
\fpu_add_ctl/n542 , \fpu_add_ctl/n541 , \fpu_add_ctl/n540 ,
\fpu_add_ctl/n441 , \fpu_add_ctl/n426 , \fpu_add_ctl/n425 ,
\fpu_add_ctl/n416 , \fpu_add_ctl/n269 , \fpu_add_ctl/n255 ,
\fpu_add_ctl/n252 , \fpu_add_ctl/n210 , \fpu_add_ctl/n207 ,
\fpu_add_ctl/n205 , \fpu_add_ctl/n203 , \fpu_add_ctl/n202 ,
\fpu_add_ctl/n200 , \fpu_add_ctl/n196 , \fpu_add_ctl/n183 ,
\fpu_add_ctl/n182 , \fpu_add_ctl/n177 , \fpu_add_ctl/n150 ,
\fpu_add_ctl/n147 , \fpu_add_ctl/n144 , \fpu_add_ctl/n143 ,
\fpu_add_ctl/n142 , \fpu_add_ctl/n141 , \fpu_add_ctl/n140 ,
\fpu_add_ctl/n139 , \fpu_add_ctl/n138 , \fpu_add_ctl/n133 ,
\fpu_add_ctl/n130 , \fpu_add_ctl/n129 , \fpu_add_ctl/n127 ,
\fpu_add_ctl/n125 , \fpu_add_ctl/n124 , \fpu_add_ctl/n123 ,
\fpu_add_ctl/n122 , \fpu_add_ctl/n121 , \fpu_add_ctl/n119 ,
\fpu_add_ctl/n118 , \fpu_add_ctl/n117 , \fpu_add_ctl/n116 ,
\fpu_add_ctl/n113 , \fpu_add_ctl/n110 , \fpu_add_ctl/n109 ,
\fpu_add_ctl/n102 , \fpu_add_ctl/n101 , \fpu_add_ctl/n97 ,
\fpu_add_ctl/n90 , \fpu_add_ctl/n89 , \fpu_add_ctl/n86 ,
\fpu_add_ctl/n85 , \fpu_add_ctl/n79 , \fpu_add_ctl/n78 ,
\fpu_add_ctl/n77 , \fpu_add_ctl/n66 , \fpu_add_ctl/n65 ,
\fpu_add_ctl/n41 , \fpu_add_ctl/n40 , \fpu_add_ctl/n39 ,
\fpu_add_ctl/n38 , \fpu_add_ctl/n37 , \fpu_add_ctl/n34 ,
\fpu_add_ctl/n32 , \fpu_add_ctl/n31 , \fpu_add_ctl/n16 ,
\fpu_add_ctl/n15 , \fpu_add_ctl/n14 , \fpu_add_ctl/n13 ,
\fpu_add_ctl/n9 , \fpu_add_ctl/n7 , \fpu_add_ctl/n5 ,
\fpu_add_ctl/n4 , \fpu_add_ctl/n3 , \fpu_add_ctl/n2 ,
\fpu_add_ctl/n1 , \fpu_add_ctl/i_add_pipe_active/N7 ,
\fpu_add_ctl/dffrl_add_ctl/N4 , \fpu_add_ctl/add_nx_out ,
\fpu_add_ctl/add_of_out_tmp2 , \fpu_add_ctl/a3stg_a2_expadd_11 ,
\fpu_add_ctl/a2stg_nan_in2 , \fpu_add_ctl/a2stg_in2_gt_in1_exp ,
\fpu_add_ctl/add_id_out[9] , \fpu_add_ctl/add_id_out[8] ,
\fpu_add_ctl/add_id_out[7] , \fpu_add_ctl/add_id_out[6] ,
\fpu_add_ctl/add_id_out[5] , \fpu_add_ctl/add_id_out[4] ,
\fpu_add_ctl/add_id_out[3] , \fpu_add_ctl/add_id_out[2] ,
\fpu_add_ctl/add_id_out[1] , \fpu_add_ctl/add_id_out[0] ,
\fpu_add_ctl/a3stg_id[2] , \fpu_add_ctl/a3stg_opdec_9_0[3] ,
\fpu_add_ctl/a2stg_id[2] , \fpu_add_ctl/add_ctl_rst_l ,
\fpu_add_exp_dp/n452 , \fpu_add_exp_dp/n451 , \fpu_add_exp_dp/n450 ,
\fpu_add_exp_dp/n448 , \fpu_add_exp_dp/n447 , \fpu_add_exp_dp/n446 ,
\fpu_add_exp_dp/n445 , \fpu_add_exp_dp/n444 , \fpu_add_exp_dp/n443 ,
\fpu_add_exp_dp/n442 , \fpu_add_exp_dp/n441 , \fpu_add_exp_dp/n440 ,
\fpu_add_exp_dp/n439 , \fpu_add_exp_dp/n438 , \fpu_add_exp_dp/n437 ,
\fpu_add_exp_dp/n436 , \fpu_add_exp_dp/n435 , \fpu_add_exp_dp/n434 ,
\fpu_add_exp_dp/n433 , \fpu_add_exp_dp/n432 , \fpu_add_exp_dp/n431 ,
\fpu_add_exp_dp/n47 , \fpu_add_exp_dp/n45 , \fpu_add_exp_dp/n722 ,
\fpu_add_exp_dp/n721 , \fpu_add_exp_dp/n720 , \fpu_add_exp_dp/n719 ,
\fpu_add_exp_dp/n718 , \fpu_add_exp_dp/n717 , \fpu_add_exp_dp/n716 ,
\fpu_add_exp_dp/n715 , \fpu_add_exp_dp/n714 , \fpu_add_exp_dp/n713 ,
\fpu_add_exp_dp/n712 , \fpu_add_exp_dp/n711 , \fpu_add_exp_dp/n710 ,
\fpu_add_exp_dp/n709 , \fpu_add_exp_dp/n708 , \fpu_add_exp_dp/n707 ,
\fpu_add_exp_dp/n706 , \fpu_add_exp_dp/n705 , \fpu_add_exp_dp/n704 ,
\fpu_add_exp_dp/n703 , \fpu_add_exp_dp/n702 , \fpu_add_exp_dp/n701 ,
\fpu_add_exp_dp/n700 , \fpu_add_exp_dp/n699 , \fpu_add_exp_dp/n698 ,
\fpu_add_exp_dp/n697 , \fpu_add_exp_dp/n696 , \fpu_add_exp_dp/n695 ,
\fpu_add_exp_dp/n694 , \fpu_add_exp_dp/n693 , \fpu_add_exp_dp/n692 ,
\fpu_add_exp_dp/n691 , \fpu_add_exp_dp/n690 , \fpu_add_exp_dp/n689 ,
\fpu_add_exp_dp/n688 , \fpu_add_exp_dp/n687 , \fpu_add_exp_dp/n686 ,
\fpu_add_exp_dp/n685 , \fpu_add_exp_dp/n684 , \fpu_add_exp_dp/n683 ,
\fpu_add_exp_dp/n682 , \fpu_add_exp_dp/n681 , \fpu_add_exp_dp/n680 ,
\fpu_add_exp_dp/n679 , \fpu_add_exp_dp/n678 , \fpu_add_exp_dp/n677 ,
\fpu_add_exp_dp/n676 , \fpu_add_exp_dp/n675 , \fpu_add_exp_dp/n674 ,
\fpu_add_exp_dp/n673 , \fpu_add_exp_dp/n672 , \fpu_add_exp_dp/n671 ,
\fpu_add_exp_dp/n670 , \fpu_add_exp_dp/n669 , \fpu_add_exp_dp/n668 ,
\fpu_add_exp_dp/n667 , \fpu_add_exp_dp/n666 , \fpu_add_exp_dp/n665 ,
\fpu_add_exp_dp/n664 , \fpu_add_exp_dp/n663 , \fpu_add_exp_dp/n662 ,
\fpu_add_exp_dp/n661 , \fpu_add_exp_dp/n660 , \fpu_add_exp_dp/n659 ,
\fpu_add_exp_dp/n658 , \fpu_add_exp_dp/n657 , \fpu_add_exp_dp/n656 ,
\fpu_add_exp_dp/n655 , \fpu_add_exp_dp/n654 , \fpu_add_exp_dp/n653 ,
\fpu_add_exp_dp/n652 , \fpu_add_exp_dp/n651 , \fpu_add_exp_dp/n650 ,
\fpu_add_exp_dp/n649 , \fpu_add_exp_dp/n648 , \fpu_add_exp_dp/n647 ,
\fpu_add_exp_dp/n646 , \fpu_add_exp_dp/n645 , \fpu_add_exp_dp/n644 ,
\fpu_add_exp_dp/n643 , \fpu_add_exp_dp/n642 , \fpu_add_exp_dp/n641 ,
\fpu_add_exp_dp/n640 , \fpu_add_exp_dp/n639 , \fpu_add_exp_dp/n638 ,
\fpu_add_exp_dp/n637 , \fpu_add_exp_dp/n636 , \fpu_add_exp_dp/n635 ,
\fpu_add_exp_dp/n634 , \fpu_add_exp_dp/n633 , \fpu_add_exp_dp/n632 ,
\fpu_add_exp_dp/n631 , \fpu_add_exp_dp/n630 , \fpu_add_exp_dp/n629 ,
\fpu_add_exp_dp/n628 , \fpu_add_exp_dp/n627 , \fpu_add_exp_dp/n626 ,
\fpu_add_exp_dp/n625 , \fpu_add_exp_dp/n624 , \fpu_add_exp_dp/n623 ,
\fpu_add_exp_dp/n622 , \fpu_add_exp_dp/n621 , \fpu_add_exp_dp/n620 ,
\fpu_add_exp_dp/n619 , \fpu_add_exp_dp/n618 , \fpu_add_exp_dp/n617 ,
\fpu_add_exp_dp/n616 , \fpu_add_exp_dp/n615 , \fpu_add_exp_dp/n614 ,
\fpu_add_exp_dp/n613 , \fpu_add_exp_dp/n612 , \fpu_add_exp_dp/n611 ,
\fpu_add_exp_dp/n610 , \fpu_add_exp_dp/n609 , \fpu_add_exp_dp/n608 ,
\fpu_add_exp_dp/n607 , \fpu_add_exp_dp/n606 , \fpu_add_exp_dp/n605 ,
\fpu_add_exp_dp/n604 , \fpu_add_exp_dp/n603 , \fpu_add_exp_dp/n602 ,
\fpu_add_exp_dp/n601 , \fpu_add_exp_dp/n600 , \fpu_add_exp_dp/n599 ,
\fpu_add_exp_dp/n598 , \fpu_add_exp_dp/n597 , \fpu_add_exp_dp/n596 ,
\fpu_add_exp_dp/n595 , \fpu_add_exp_dp/n594 , \fpu_add_exp_dp/n593 ,
\fpu_add_exp_dp/n592 , \fpu_add_exp_dp/n591 , \fpu_add_exp_dp/n589 ,
\fpu_add_exp_dp/n588 , \fpu_add_exp_dp/n587 , \fpu_add_exp_dp/n586 ,
\fpu_add_exp_dp/n585 , \fpu_add_exp_dp/n584 , \fpu_add_exp_dp/n583 ,
\fpu_add_exp_dp/n582 , \fpu_add_exp_dp/n581 , \fpu_add_exp_dp/n580 ,
\fpu_add_exp_dp/n579 , \fpu_add_exp_dp/n578 , \fpu_add_exp_dp/n577 ,
\fpu_add_exp_dp/n576 , \fpu_add_exp_dp/n575 , \fpu_add_exp_dp/n574 ,
\fpu_add_exp_dp/n573 , \fpu_add_exp_dp/n572 , \fpu_add_exp_dp/n571 ,
\fpu_add_exp_dp/n570 , \fpu_add_exp_dp/n569 , \fpu_add_exp_dp/n568 ,
\fpu_add_exp_dp/n567 , \fpu_add_exp_dp/n566 , \fpu_add_exp_dp/n565 ,
\fpu_add_exp_dp/n563 , \fpu_add_exp_dp/n562 , \fpu_add_exp_dp/n561 ,
\fpu_add_exp_dp/n560 , \fpu_add_exp_dp/n559 , \fpu_add_exp_dp/n558 ,
\fpu_add_exp_dp/n557 , \fpu_add_exp_dp/n556 , \fpu_add_exp_dp/n555 ,
\fpu_add_exp_dp/n554 , \fpu_add_exp_dp/n553 , \fpu_add_exp_dp/n552 ,
\fpu_add_exp_dp/n550 , \fpu_add_exp_dp/n549 , \fpu_add_exp_dp/n548 ,
\fpu_add_exp_dp/n547 , \fpu_add_exp_dp/n546 , \fpu_add_exp_dp/n545 ,
\fpu_add_exp_dp/n544 , \fpu_add_exp_dp/n543 , \fpu_add_exp_dp/n542 ,
\fpu_add_exp_dp/n541 , \fpu_add_exp_dp/n540 , \fpu_add_exp_dp/n539 ,
\fpu_add_exp_dp/n538 , \fpu_add_exp_dp/n537 , \fpu_add_exp_dp/n536 ,
\fpu_add_exp_dp/n535 , \fpu_add_exp_dp/n534 , \fpu_add_exp_dp/n533 ,
\fpu_add_exp_dp/n532 , \fpu_add_exp_dp/n531 , \fpu_add_exp_dp/n530 ,
\fpu_add_exp_dp/n529 , \fpu_add_exp_dp/n528 , \fpu_add_exp_dp/n527 ,
\fpu_add_exp_dp/n526 , \fpu_add_exp_dp/n525 , \fpu_add_exp_dp/n524 ,
\fpu_add_exp_dp/n523 , \fpu_add_exp_dp/n522 , \fpu_add_exp_dp/n521 ,
\fpu_add_exp_dp/n520 , \fpu_add_exp_dp/n519 , \fpu_add_exp_dp/n518 ,
\fpu_add_exp_dp/n517 , \fpu_add_exp_dp/n516 , \fpu_add_exp_dp/n515 ,
\fpu_add_exp_dp/n514 , \fpu_add_exp_dp/n513 , \fpu_add_exp_dp/n512 ,
\fpu_add_exp_dp/n511 , \fpu_add_exp_dp/n510 , \fpu_add_exp_dp/n509 ,
\fpu_add_exp_dp/n508 , \fpu_add_exp_dp/n507 , \fpu_add_exp_dp/n256 ,
\fpu_add_exp_dp/n253 , \fpu_add_exp_dp/n252 , \fpu_add_exp_dp/n251 ,
\fpu_add_exp_dp/n250 , \fpu_add_exp_dp/n249 , \fpu_add_exp_dp/n248 ,
\fpu_add_exp_dp/n247 , \fpu_add_exp_dp/n246 , \fpu_add_exp_dp/n245 ,
\fpu_add_exp_dp/n244 , \fpu_add_exp_dp/n243 , \fpu_add_exp_dp/n242 ,
\fpu_add_exp_dp/n241 , \fpu_add_exp_dp/n240 , \fpu_add_exp_dp/n239 ,
\fpu_add_exp_dp/n238 , \fpu_add_exp_dp/n237 , \fpu_add_exp_dp/n236 ,
\fpu_add_exp_dp/n235 , \fpu_add_exp_dp/n234 , \fpu_add_exp_dp/n233 ,
\fpu_add_exp_dp/n232 , \fpu_add_exp_dp/n231 , \fpu_add_exp_dp/n230 ,
\fpu_add_exp_dp/n229 , \fpu_add_exp_dp/n228 , \fpu_add_exp_dp/n225 ,
\fpu_add_exp_dp/n224 , \fpu_add_exp_dp/n222 , \fpu_add_exp_dp/n221 ,
\fpu_add_exp_dp/n220 , \fpu_add_exp_dp/n219 , \fpu_add_exp_dp/n218 ,
\fpu_add_exp_dp/n217 , \fpu_add_exp_dp/n216 , \fpu_add_exp_dp/n215 ,
\fpu_add_exp_dp/n214 , \fpu_add_exp_dp/n213 , \fpu_add_exp_dp/n212 ,
\fpu_add_exp_dp/n211 , \fpu_add_exp_dp/n210 , \fpu_add_exp_dp/n209 ,
\fpu_add_exp_dp/n208 , \fpu_add_exp_dp/n207 , \fpu_add_exp_dp/n206 ,
\fpu_add_exp_dp/n205 , \fpu_add_exp_dp/n204 , \fpu_add_exp_dp/n203 ,
\fpu_add_exp_dp/n202 , \fpu_add_exp_dp/n201 , \fpu_add_exp_dp/n200 ,
\fpu_add_exp_dp/n199 , \fpu_add_exp_dp/n198 , \fpu_add_exp_dp/n197 ,
\fpu_add_exp_dp/n196 , \fpu_add_exp_dp/n195 , \fpu_add_exp_dp/n194 ,
\fpu_add_exp_dp/n193 , \fpu_add_exp_dp/n192 , \fpu_add_exp_dp/n191 ,
\fpu_add_exp_dp/n190 , \fpu_add_exp_dp/n189 , \fpu_add_exp_dp/n188 ,
\fpu_add_exp_dp/n187 , \fpu_add_exp_dp/n186 , \fpu_add_exp_dp/n185 ,
\fpu_add_exp_dp/n184 , \fpu_add_exp_dp/n183 , \fpu_add_exp_dp/n182 ,
\fpu_add_exp_dp/n181 , \fpu_add_exp_dp/n180 , \fpu_add_exp_dp/n179 ,
\fpu_add_exp_dp/n178 , \fpu_add_exp_dp/n177 , \fpu_add_exp_dp/n176 ,
\fpu_add_exp_dp/n175 , \fpu_add_exp_dp/n174 , \fpu_add_exp_dp/n172 ,
\fpu_add_exp_dp/n171 , \fpu_add_exp_dp/n170 , \fpu_add_exp_dp/n150 ,
\fpu_add_exp_dp/n149 , \fpu_add_exp_dp/n147 , \fpu_add_exp_dp/n146 ,
\fpu_add_exp_dp/n145 , \fpu_add_exp_dp/n144 , \fpu_add_exp_dp/n143 ,
\fpu_add_exp_dp/n142 , \fpu_add_exp_dp/n141 , \fpu_add_exp_dp/n137 ,
\fpu_add_exp_dp/n136 , \fpu_add_exp_dp/n135 , \fpu_add_exp_dp/n134 ,
\fpu_add_exp_dp/n133 , \fpu_add_exp_dp/n132 , \fpu_add_exp_dp/n131 ,
\fpu_add_exp_dp/n130 , \fpu_add_exp_dp/n129 , \fpu_add_exp_dp/n128 ,
\fpu_add_exp_dp/n127 , \fpu_add_exp_dp/n126 , \fpu_add_exp_dp/n125 ,
\fpu_add_exp_dp/n124 , \fpu_add_exp_dp/n122 , \fpu_add_exp_dp/n121 ,
\fpu_add_exp_dp/n120 , \fpu_add_exp_dp/n119 , \fpu_add_exp_dp/n118 ,
\fpu_add_exp_dp/n117 , \fpu_add_exp_dp/n116 , \fpu_add_exp_dp/n115 ,
\fpu_add_exp_dp/n114 , \fpu_add_exp_dp/n113 , \fpu_add_exp_dp/n112 ,
\fpu_add_exp_dp/n111 , \fpu_add_exp_dp/n109 , \fpu_add_exp_dp/n108 ,
\fpu_add_exp_dp/n107 , \fpu_add_exp_dp/n106 , \fpu_add_exp_dp/n105 ,
\fpu_add_exp_dp/n104 , \fpu_add_exp_dp/n103 , \fpu_add_exp_dp/n102 ,
\fpu_add_exp_dp/n101 , \fpu_add_exp_dp/n100 , \fpu_add_exp_dp/n99 ,
\fpu_add_exp_dp/n98 , \fpu_add_exp_dp/n96 , \fpu_add_exp_dp/n95 ,
\fpu_add_exp_dp/n94 , \fpu_add_exp_dp/n93 , \fpu_add_exp_dp/n92 ,
\fpu_add_exp_dp/n91 , \fpu_add_exp_dp/n90 , \fpu_add_exp_dp/n89 ,
\fpu_add_exp_dp/n88 , \fpu_add_exp_dp/n87 , \fpu_add_exp_dp/n86 ,
\fpu_add_exp_dp/n85 , \fpu_add_exp_dp/n83 , \fpu_add_exp_dp/n82 ,
\fpu_add_exp_dp/n81 , \fpu_add_exp_dp/n80 , \fpu_add_exp_dp/n79 ,
\fpu_add_exp_dp/n78 , \fpu_add_exp_dp/n77 , \fpu_add_exp_dp/n76 ,
\fpu_add_exp_dp/n75 , \fpu_add_exp_dp/n74 , \fpu_add_exp_dp/n73 ,
\fpu_add_exp_dp/n72 , \fpu_add_exp_dp/n71 , \fpu_add_exp_dp/n70 ,
\fpu_add_exp_dp/n69 , \fpu_add_exp_dp/n68 , \fpu_add_exp_dp/n67 ,
\fpu_add_exp_dp/n66 , \fpu_add_exp_dp/n65 , \fpu_add_exp_dp/n64 ,
\fpu_add_exp_dp/n63 , \fpu_add_exp_dp/n62 , \fpu_add_exp_dp/n61 ,
\fpu_add_exp_dp/n60 , \fpu_add_exp_dp/n57 , \fpu_add_exp_dp/n50 ,
\fpu_add_exp_dp/n48 , \fpu_add_exp_dp/n46 , \fpu_add_exp_dp/n22 ,
\fpu_add_exp_dp/n21 , \fpu_add_exp_dp/n20 , \fpu_add_exp_dp/n19 ,
\fpu_add_exp_dp/n18 , \fpu_add_exp_dp/n17 , \fpu_add_exp_dp/n16 ,
\fpu_add_exp_dp/n15 , \fpu_add_exp_dp/n14 , \fpu_add_exp_dp/n13 ,
\fpu_add_exp_dp/n12 , \fpu_add_exp_dp/n11 , \fpu_add_exp_dp/n10 ,
\fpu_add_exp_dp/n9 , \fpu_add_exp_dp/n8 , \fpu_add_exp_dp/n7 ,
\fpu_add_exp_dp/n6 , \fpu_add_exp_dp/n5 , \fpu_add_exp_dp/n4 ,
\fpu_add_exp_dp/n3 , \fpu_add_exp_dp/n2 , \fpu_add_exp_dp/n1 ,
\fpu_add_exp_dp/i_a4stg_exp_pre4/N3 ,
\fpu_add_exp_dp/i_a4stg_exp_pre4/N4 ,
\fpu_add_exp_dp/i_a4stg_exp_pre4/N5 ,
\fpu_add_exp_dp/i_a4stg_exp_pre4/N6 ,
\fpu_add_exp_dp/i_a4stg_exp_pre4/N7 ,
\fpu_add_exp_dp/i_a4stg_exp_pre4/N8 ,
\fpu_add_exp_dp/i_a4stg_exp_pre4/N9 ,
\fpu_add_exp_dp/i_a4stg_exp_pre4/N10 ,
\fpu_add_exp_dp/i_a4stg_exp_pre4/N11 ,
\fpu_add_exp_dp/i_a4stg_exp_pre4/N12 ,
\fpu_add_exp_dp/i_a4stg_exp_pre4/N13 ,
\fpu_add_exp_dp/i_a4stg_exp_pre4/N14 ,
\fpu_add_exp_dp/i_a4stg_exp_pre2/N3 ,
\fpu_add_exp_dp/i_a4stg_exp_pre2/N4 ,
\fpu_add_exp_dp/i_a4stg_exp_pre2/N5 ,
\fpu_add_exp_dp/i_a4stg_exp_pre2/N6 ,
\fpu_add_exp_dp/i_a4stg_exp_pre2/N7 ,
\fpu_add_exp_dp/i_a4stg_exp_pre2/N8 ,
\fpu_add_exp_dp/i_a4stg_exp_pre2/N9 ,
\fpu_add_exp_dp/i_a4stg_exp_pre2/N10 ,
\fpu_add_exp_dp/i_a4stg_exp_pre2/N11 ,
\fpu_add_exp_dp/i_a4stg_exp_pre2/N12 ,
\fpu_add_exp_dp/i_a4stg_exp_pre2/N13 ,
\fpu_add_exp_dp/i_a4stg_exp_pre2/N14 ,
\fpu_add_exp_dp/i_a4stg_exp_pre3/N3 ,
\fpu_add_exp_dp/i_a4stg_exp_pre3/N4 ,
\fpu_add_exp_dp/i_a4stg_exp_pre3/N5 ,
\fpu_add_exp_dp/i_a4stg_exp_pre3/N6 ,
\fpu_add_exp_dp/i_a4stg_exp_pre3/N7 ,
\fpu_add_exp_dp/i_a4stg_exp_pre3/N8 ,
\fpu_add_exp_dp/i_a4stg_exp_pre3/N9 ,
\fpu_add_exp_dp/i_a4stg_exp_pre3/N10 ,
\fpu_add_exp_dp/i_a4stg_exp_pre3/N11 ,
\fpu_add_exp_dp/i_a4stg_exp_pre3/N12 ,
\fpu_add_exp_dp/i_a4stg_exp_pre3/N13 ,
\fpu_add_exp_dp/i_a4stg_exp_pre3/N14 ,
\fpu_add_exp_dp/i_a4stg_exp_pre1/N3 ,
\fpu_add_exp_dp/i_a4stg_exp_pre1/N4 ,
\fpu_add_exp_dp/i_a4stg_exp_pre1/N5 ,
\fpu_add_exp_dp/i_a4stg_exp_pre1/N6 ,
\fpu_add_exp_dp/i_a4stg_exp_pre1/N7 ,
\fpu_add_exp_dp/i_a4stg_exp_pre1/N8 ,
\fpu_add_exp_dp/i_a4stg_exp_pre1/N9 ,
\fpu_add_exp_dp/i_a4stg_exp_pre1/N10 ,
\fpu_add_exp_dp/i_a4stg_exp_pre1/N11 ,
\fpu_add_exp_dp/i_a4stg_exp_pre1/N12 ,
\fpu_add_exp_dp/i_a4stg_exp_pre1/N13 ,
\fpu_add_exp_dp/i_a4stg_exp_pre1/N14 ,
\fpu_add_exp_dp/ckbuf_add_exp_dp/N1 ,
\fpu_add_exp_dp/ckbuf_add_exp_dp/clken ,
\fpu_add_exp_dp/add_exp_out3[10] , \fpu_add_exp_dp/add_exp_out3[9] ,
\fpu_add_exp_dp/add_exp_out3[8] , \fpu_add_exp_dp/add_exp_out3[7] ,
\fpu_add_exp_dp/add_exp_out3[6] , \fpu_add_exp_dp/add_exp_out3[5] ,
\fpu_add_exp_dp/add_exp_out3[4] , \fpu_add_exp_dp/add_exp_out3[3] ,
\fpu_add_exp_dp/add_exp_out3[2] , \fpu_add_exp_dp/add_exp_out3[1] ,
\fpu_add_exp_dp/add_exp_out3[0] , \fpu_add_exp_dp/a4stg_exp2[11] ,
\fpu_add_exp_dp/a4stg_exp2[9] , \fpu_add_exp_dp/a4stg_exp2[8] ,
\fpu_add_exp_dp/a4stg_exp2[7] , \fpu_add_exp_dp/a4stg_exp2[4] ,
\fpu_add_exp_dp/a4stg_exp2[3] , \fpu_add_exp_dp/a4stg_exp2[2] ,
\fpu_add_exp_dp/a4stg_exp2[0] , \fpu_add_exp_dp/a4stg_exp_pre4[11] ,
\fpu_add_exp_dp/a4stg_exp_pre4[10] ,
\fpu_add_exp_dp/a4stg_exp_pre4[9] ,
\fpu_add_exp_dp/a4stg_exp_pre4[8] ,
\fpu_add_exp_dp/a4stg_exp_pre4[7] ,
\fpu_add_exp_dp/a4stg_exp_pre4[6] ,
\fpu_add_exp_dp/a4stg_exp_pre4[5] ,
\fpu_add_exp_dp/a4stg_exp_pre4[4] ,
\fpu_add_exp_dp/a4stg_exp_pre4[3] ,
\fpu_add_exp_dp/a4stg_exp_pre4[2] ,
\fpu_add_exp_dp/a4stg_exp_pre4[1] ,
\fpu_add_exp_dp/a4stg_exp_pre4[0] ,
\fpu_add_exp_dp/a4stg_exp_pre2[11] ,
\fpu_add_exp_dp/a4stg_exp_pre2[10] ,
\fpu_add_exp_dp/a4stg_exp_pre2[9] ,
\fpu_add_exp_dp/a4stg_exp_pre2[8] ,
\fpu_add_exp_dp/a4stg_exp_pre2[7] ,
\fpu_add_exp_dp/a4stg_exp_pre2[6] ,
\fpu_add_exp_dp/a4stg_exp_pre2[5] ,
\fpu_add_exp_dp/a4stg_exp_pre2[4] ,
\fpu_add_exp_dp/a4stg_exp_pre2[3] ,
\fpu_add_exp_dp/a4stg_exp_pre2[2] ,
\fpu_add_exp_dp/a4stg_exp_pre2[1] ,
\fpu_add_exp_dp/a4stg_exp_pre2[0] ,
\fpu_add_exp_dp/a4stg_exp_pre3[11] ,
\fpu_add_exp_dp/a4stg_exp_pre3[10] ,
\fpu_add_exp_dp/a4stg_exp_pre3[9] ,
\fpu_add_exp_dp/a4stg_exp_pre3[8] ,
\fpu_add_exp_dp/a4stg_exp_pre3[7] ,
\fpu_add_exp_dp/a4stg_exp_pre3[6] ,
\fpu_add_exp_dp/a4stg_exp_pre3[5] ,
\fpu_add_exp_dp/a4stg_exp_pre3[4] ,
\fpu_add_exp_dp/a4stg_exp_pre3[3] ,
\fpu_add_exp_dp/a4stg_exp_pre3[2] ,
\fpu_add_exp_dp/a4stg_exp_pre3[1] ,
\fpu_add_exp_dp/a4stg_exp_pre3[0] ,
\fpu_add_exp_dp/a4stg_exp_pre1[11] ,
\fpu_add_exp_dp/a4stg_exp_pre1[10] ,
\fpu_add_exp_dp/a4stg_exp_pre1[9] ,
\fpu_add_exp_dp/a4stg_exp_pre1[8] ,
\fpu_add_exp_dp/a4stg_exp_pre1[7] ,
\fpu_add_exp_dp/a4stg_exp_pre1[6] ,
\fpu_add_exp_dp/a4stg_exp_pre1[5] ,
\fpu_add_exp_dp/a4stg_exp_pre1[4] ,
\fpu_add_exp_dp/a4stg_exp_pre1[3] ,
\fpu_add_exp_dp/a4stg_exp_pre1[2] ,
\fpu_add_exp_dp/a4stg_exp_pre1[1] ,
\fpu_add_exp_dp/a4stg_exp_pre1[0] ,
\fpu_add_exp_dp/a1stg_expadd3_in2[10] ,
\fpu_add_exp_dp/a1stg_in2a[59] , \fpu_add_exp_dp/a1stg_in2a[58] ,
\fpu_add_exp_dp/a1stg_in2a[57] , \fpu_add_exp_dp/a1stg_in2a[56] ,
\fpu_add_exp_dp/a1stg_in2a[55] , \fpu_add_exp_dp/a1stg_in2a[54] ,
\fpu_add_exp_dp/a1stg_in2a[53] , \fpu_add_exp_dp/a1stg_in2a[52] ,
\fpu_add_frac_dp/n5644 , \fpu_add_frac_dp/n5643 ,
\fpu_add_frac_dp/n5642 , \fpu_add_frac_dp/n5641 ,
\fpu_add_frac_dp/n5640 , \fpu_add_frac_dp/n5635 ,
\fpu_add_frac_dp/n5634 , \fpu_add_frac_dp/n5633 ,
\fpu_add_frac_dp/n5632 , \fpu_add_frac_dp/n5631 ,
\fpu_add_frac_dp/n5630 , \fpu_add_frac_dp/n5629 ,
\fpu_add_frac_dp/n5627 , \fpu_add_frac_dp/n5626 ,
\fpu_add_frac_dp/n5625 , \fpu_add_frac_dp/n5624 ,
\fpu_add_frac_dp/n5623 , \fpu_add_frac_dp/n5622 ,
\fpu_add_frac_dp/n5621 , \fpu_add_frac_dp/n5620 ,
\fpu_add_frac_dp/n5619 , \fpu_add_frac_dp/n5618 ,
\fpu_add_frac_dp/n5617 , \fpu_add_frac_dp/n5616 ,
\fpu_add_frac_dp/n5614 , \fpu_add_frac_dp/n5613 ,
\fpu_add_frac_dp/n5612 , \fpu_add_frac_dp/n5611 ,
\fpu_add_frac_dp/n5610 , \fpu_add_frac_dp/n5609 ,
\fpu_add_frac_dp/n5608 , \fpu_add_frac_dp/n5605 ,
\fpu_add_frac_dp/n2189 , \fpu_add_frac_dp/n1574 ,
\fpu_add_frac_dp/n1573 , \fpu_add_frac_dp/n1572 ,
\fpu_add_frac_dp/n1571 , \fpu_add_frac_dp/n1570 ,
\fpu_add_frac_dp/n1569 , \fpu_add_frac_dp/n1568 ,
\fpu_add_frac_dp/n1567 , \fpu_add_frac_dp/n1566 ,
\fpu_add_frac_dp/n1565 , \fpu_add_frac_dp/n1564 ,
\fpu_add_frac_dp/n1563 , \fpu_add_frac_dp/n1562 ,
\fpu_add_frac_dp/n1561 , \fpu_add_frac_dp/n1560 ,
\fpu_add_frac_dp/n1559 , \fpu_add_frac_dp/n1558 ,
\fpu_add_frac_dp/n1557 , \fpu_add_frac_dp/n1556 ,
\fpu_add_frac_dp/n1555 , \fpu_add_frac_dp/n1554 ,
\fpu_add_frac_dp/n1553 , \fpu_add_frac_dp/n1552 ,
\fpu_add_frac_dp/n1551 , \fpu_add_frac_dp/n1550 ,
\fpu_add_frac_dp/n1549 , \fpu_add_frac_dp/n1548 ,
\fpu_add_frac_dp/n1547 , \fpu_add_frac_dp/n1546 ,
\fpu_add_frac_dp/n1545 , \fpu_add_frac_dp/n1544 ,
\fpu_add_frac_dp/n1543 , \fpu_add_frac_dp/n1542 ,
\fpu_add_frac_dp/n1541 , \fpu_add_frac_dp/n1540 ,
\fpu_add_frac_dp/n1539 , \fpu_add_frac_dp/n1538 ,
\fpu_add_frac_dp/n1537 , \fpu_add_frac_dp/n1536 ,
\fpu_add_frac_dp/n1535 , \fpu_add_frac_dp/n1534 ,
\fpu_add_frac_dp/n1533 , \fpu_add_frac_dp/n1532 ,
\fpu_add_frac_dp/n1531 , \fpu_add_frac_dp/n1530 ,
\fpu_add_frac_dp/n1529 , \fpu_add_frac_dp/n1528 ,
\fpu_add_frac_dp/n1527 , \fpu_add_frac_dp/n1526 ,
\fpu_add_frac_dp/n1525 , \fpu_add_frac_dp/n1524 ,
\fpu_add_frac_dp/n1523 , \fpu_add_frac_dp/n1522 ,
\fpu_add_frac_dp/n1521 , \fpu_add_frac_dp/n1520 ,
\fpu_add_frac_dp/n1519 , \fpu_add_frac_dp/n1518 ,
\fpu_add_frac_dp/n1517 , \fpu_add_frac_dp/n1516 ,
\fpu_add_frac_dp/n1515 , \fpu_add_frac_dp/n1509 ,
\fpu_add_frac_dp/n2544 , \fpu_add_frac_dp/n2543 ,
\fpu_add_frac_dp/n2540 , \fpu_add_frac_dp/n2539 ,
\fpu_add_frac_dp/n2538 , \fpu_add_frac_dp/n2537 ,
\fpu_add_frac_dp/n2536 , \fpu_add_frac_dp/n2535 ,
\fpu_add_frac_dp/n2534 , \fpu_add_frac_dp/n2533 ,
\fpu_add_frac_dp/n2532 , \fpu_add_frac_dp/n2531 ,
\fpu_add_frac_dp/n2530 , \fpu_add_frac_dp/n2529 ,
\fpu_add_frac_dp/n2528 , \fpu_add_frac_dp/n2527 ,
\fpu_add_frac_dp/n2526 , \fpu_add_frac_dp/n2525 ,
\fpu_add_frac_dp/n2524 , \fpu_add_frac_dp/n2523 ,
\fpu_add_frac_dp/n2522 , \fpu_add_frac_dp/n2521 ,
\fpu_add_frac_dp/n2520 , \fpu_add_frac_dp/n2519 ,
\fpu_add_frac_dp/n2518 , \fpu_add_frac_dp/n2517 ,
\fpu_add_frac_dp/n2516 , \fpu_add_frac_dp/n2515 ,
\fpu_add_frac_dp/n2514 , \fpu_add_frac_dp/n2513 ,
\fpu_add_frac_dp/n2512 , \fpu_add_frac_dp/n2511 ,
\fpu_add_frac_dp/n2510 , \fpu_add_frac_dp/n2509 ,
\fpu_add_frac_dp/n2508 , \fpu_add_frac_dp/n2507 ,
\fpu_add_frac_dp/n2506 , \fpu_add_frac_dp/n2505 ,
\fpu_add_frac_dp/n2504 , \fpu_add_frac_dp/n2503 ,
\fpu_add_frac_dp/n2502 , \fpu_add_frac_dp/n2501 ,
\fpu_add_frac_dp/n2500 , \fpu_add_frac_dp/n2499 ,
\fpu_add_frac_dp/n2498 , \fpu_add_frac_dp/n2497 ,
\fpu_add_frac_dp/n2496 , \fpu_add_frac_dp/n2495 ,
\fpu_add_frac_dp/n2494 , \fpu_add_frac_dp/n2493 ,
\fpu_add_frac_dp/n2492 , \fpu_add_frac_dp/n2491 ,
\fpu_add_frac_dp/n2490 , \fpu_add_frac_dp/n2489 ,
\fpu_add_frac_dp/n2488 , \fpu_add_frac_dp/n2487 ,
\fpu_add_frac_dp/n2486 , \fpu_add_frac_dp/n2485 ,
\fpu_add_frac_dp/n2484 , \fpu_add_frac_dp/n2483 ,
\fpu_add_frac_dp/n2482 , \fpu_add_frac_dp/n2481 ,
\fpu_add_frac_dp/n2480 , \fpu_add_frac_dp/n2479 ,
\fpu_add_frac_dp/n2478 , \fpu_add_frac_dp/n2477 ,
\fpu_add_frac_dp/n2476 , \fpu_add_frac_dp/n2475 ,
\fpu_add_frac_dp/n2474 , \fpu_add_frac_dp/n2473 ,
\fpu_add_frac_dp/n2472 , \fpu_add_frac_dp/n2471 ,
\fpu_add_frac_dp/n2470 , \fpu_add_frac_dp/n2469 ,
\fpu_add_frac_dp/n2468 , \fpu_add_frac_dp/n2467 ,
\fpu_add_frac_dp/n2466 , \fpu_add_frac_dp/n2465 ,
\fpu_add_frac_dp/n2462 , \fpu_add_frac_dp/n2460 ,
\fpu_add_frac_dp/n2459 , \fpu_add_frac_dp/n2458 ,
\fpu_add_frac_dp/n2457 , \fpu_add_frac_dp/n2455 ,
\fpu_add_frac_dp/n2454 , \fpu_add_frac_dp/n2453 ,
\fpu_add_frac_dp/n2452 , \fpu_add_frac_dp/n2449 ,
\fpu_add_frac_dp/n2448 , \fpu_add_frac_dp/n2447 ,
\fpu_add_frac_dp/n2446 , \fpu_add_frac_dp/n2445 ,
\fpu_add_frac_dp/n2444 , \fpu_add_frac_dp/n2442 ,
\fpu_add_frac_dp/n2441 , \fpu_add_frac_dp/n2440 ,
\fpu_add_frac_dp/n2439 , \fpu_add_frac_dp/n2438 ,
\fpu_add_frac_dp/n2437 , \fpu_add_frac_dp/n2436 ,
\fpu_add_frac_dp/n2435 , \fpu_add_frac_dp/n2434 ,
\fpu_add_frac_dp/n2433 , \fpu_add_frac_dp/n2432 ,
\fpu_add_frac_dp/n2431 , \fpu_add_frac_dp/n2430 ,
\fpu_add_frac_dp/n2429 , \fpu_add_frac_dp/n2428 ,
\fpu_add_frac_dp/n2427 , \fpu_add_frac_dp/n2426 ,
\fpu_add_frac_dp/n2425 , \fpu_add_frac_dp/n2424 ,
\fpu_add_frac_dp/n2423 , \fpu_add_frac_dp/n2422 ,
\fpu_add_frac_dp/n2421 , \fpu_add_frac_dp/n2420 ,
\fpu_add_frac_dp/n2419 , \fpu_add_frac_dp/n2418 ,
\fpu_add_frac_dp/n2417 , \fpu_add_frac_dp/n2416 ,
\fpu_add_frac_dp/n2415 , \fpu_add_frac_dp/n2414 ,
\fpu_add_frac_dp/n2413 , \fpu_add_frac_dp/n2412 ,
\fpu_add_frac_dp/n2411 , \fpu_add_frac_dp/n2410 ,
\fpu_add_frac_dp/n2409 , \fpu_add_frac_dp/n2408 ,
\fpu_add_frac_dp/n2407 , \fpu_add_frac_dp/n2406 ,
\fpu_add_frac_dp/n2405 , \fpu_add_frac_dp/n2404 ,
\fpu_add_frac_dp/n2403 , \fpu_add_frac_dp/n2402 ,
\fpu_add_frac_dp/n2401 , \fpu_add_frac_dp/n2400 ,
\fpu_add_frac_dp/n2399 , \fpu_add_frac_dp/n2398 ,
\fpu_add_frac_dp/n2397 , \fpu_add_frac_dp/n2396 ,
\fpu_add_frac_dp/n2395 , \fpu_add_frac_dp/n2394 ,
\fpu_add_frac_dp/n2393 , \fpu_add_frac_dp/n2392 ,
\fpu_add_frac_dp/n2391 , \fpu_add_frac_dp/n2390 ,
\fpu_add_frac_dp/n2389 , \fpu_add_frac_dp/n2388 ,
\fpu_add_frac_dp/n2387 , \fpu_add_frac_dp/n2386 ,
\fpu_add_frac_dp/n2385 , \fpu_add_frac_dp/n2384 ,
\fpu_add_frac_dp/n2382 , \fpu_add_frac_dp/n2381 ,
\fpu_add_frac_dp/n2380 , \fpu_add_frac_dp/n2379 ,
\fpu_add_frac_dp/n2378 , \fpu_add_frac_dp/n2377 ,
\fpu_add_frac_dp/n2376 , \fpu_add_frac_dp/n2375 ,
\fpu_add_frac_dp/n2374 , \fpu_add_frac_dp/n2373 ,
\fpu_add_frac_dp/n2372 , \fpu_add_frac_dp/n2370 ,
\fpu_add_frac_dp/n2369 , \fpu_add_frac_dp/n2368 ,
\fpu_add_frac_dp/n2367 , \fpu_add_frac_dp/n2366 ,
\fpu_add_frac_dp/n2365 , \fpu_add_frac_dp/n2364 ,
\fpu_add_frac_dp/n2363 , \fpu_add_frac_dp/n2362 ,
\fpu_add_frac_dp/n2361 , \fpu_add_frac_dp/n2360 ,
\fpu_add_frac_dp/n2359 , \fpu_add_frac_dp/n2358 ,
\fpu_add_frac_dp/n2357 , \fpu_add_frac_dp/n2356 ,
\fpu_add_frac_dp/n2355 , \fpu_add_frac_dp/n2354 ,
\fpu_add_frac_dp/n2353 , \fpu_add_frac_dp/n2352 ,
\fpu_add_frac_dp/n2351 , \fpu_add_frac_dp/n2350 ,
\fpu_add_frac_dp/n2349 , \fpu_add_frac_dp/n2348 ,
\fpu_add_frac_dp/n2347 , \fpu_add_frac_dp/n2346 ,
\fpu_add_frac_dp/n2345 , \fpu_add_frac_dp/n2344 ,
\fpu_add_frac_dp/n2343 , \fpu_add_frac_dp/n2342 ,
\fpu_add_frac_dp/n2341 , \fpu_add_frac_dp/n2340 ,
\fpu_add_frac_dp/n2339 , \fpu_add_frac_dp/n2338 ,
\fpu_add_frac_dp/n2337 , \fpu_add_frac_dp/n2336 ,
\fpu_add_frac_dp/n2335 , \fpu_add_frac_dp/n2334 ,
\fpu_add_frac_dp/n2333 , \fpu_add_frac_dp/n2332 ,
\fpu_add_frac_dp/n2331 , \fpu_add_frac_dp/n2330 ,
\fpu_add_frac_dp/n2325 , \fpu_add_frac_dp/n2322 ,
\fpu_add_frac_dp/n2320 , \fpu_add_frac_dp/n2317 ,
\fpu_add_frac_dp/n2316 , \fpu_add_frac_dp/n2314 ,
\fpu_add_frac_dp/n2313 , \fpu_add_frac_dp/n2310 ,
\fpu_add_frac_dp/n2309 , \fpu_add_frac_dp/n2308 ,
\fpu_add_frac_dp/n2307 , \fpu_add_frac_dp/n2306 ,
\fpu_add_frac_dp/n2305 , \fpu_add_frac_dp/n2304 ,
\fpu_add_frac_dp/n2303 , \fpu_add_frac_dp/n2302 ,
\fpu_add_frac_dp/n2301 , \fpu_add_frac_dp/n2300 ,
\fpu_add_frac_dp/n2299 , \fpu_add_frac_dp/n2298 ,
\fpu_add_frac_dp/n2297 , \fpu_add_frac_dp/n2296 ,
\fpu_add_frac_dp/n2295 , \fpu_add_frac_dp/n2294 ,
\fpu_add_frac_dp/n2293 , \fpu_add_frac_dp/n2292 ,
\fpu_add_frac_dp/n2291 , \fpu_add_frac_dp/n2290 ,
\fpu_add_frac_dp/n2289 , \fpu_add_frac_dp/n2288 ,
\fpu_add_frac_dp/n2287 , \fpu_add_frac_dp/n2285 ,
\fpu_add_frac_dp/n2282 , \fpu_add_frac_dp/n2281 ,
\fpu_add_frac_dp/n2280 , \fpu_add_frac_dp/n2279 ,
\fpu_add_frac_dp/n2278 , \fpu_add_frac_dp/n2277 ,
\fpu_add_frac_dp/n2276 , \fpu_add_frac_dp/n2275 ,
\fpu_add_frac_dp/n2274 , \fpu_add_frac_dp/n2273 ,
\fpu_add_frac_dp/n2272 , \fpu_add_frac_dp/n2271 ,
\fpu_add_frac_dp/n2270 , \fpu_add_frac_dp/n2269 ,
\fpu_add_frac_dp/n2262 , \fpu_add_frac_dp/n4285 ,
\fpu_add_frac_dp/n4284 , \fpu_add_frac_dp/n4283 ,
\fpu_add_frac_dp/n4282 , \fpu_add_frac_dp/n4281 ,
\fpu_add_frac_dp/n4280 , \fpu_add_frac_dp/n4279 ,
\fpu_add_frac_dp/n4278 , \fpu_add_frac_dp/n4277 ,
\fpu_add_frac_dp/n4276 , \fpu_add_frac_dp/n4275 ,
\fpu_add_frac_dp/n4274 , \fpu_add_frac_dp/n4273 ,
\fpu_add_frac_dp/n4272 , \fpu_add_frac_dp/n4271 ,
\fpu_add_frac_dp/n4270 , \fpu_add_frac_dp/n4269 ,
\fpu_add_frac_dp/n4268 , \fpu_add_frac_dp/n4267 ,
\fpu_add_frac_dp/n4266 , \fpu_add_frac_dp/n4265 ,
\fpu_add_frac_dp/n4264 , \fpu_add_frac_dp/n4263 ,
\fpu_add_frac_dp/n4262 , \fpu_add_frac_dp/n4261 ,
\fpu_add_frac_dp/n4260 , \fpu_add_frac_dp/n4259 ,
\fpu_add_frac_dp/n4258 , \fpu_add_frac_dp/n4257 ,
\fpu_add_frac_dp/n4256 , \fpu_add_frac_dp/n4255 ,
\fpu_add_frac_dp/n4254 , \fpu_add_frac_dp/n4253 ,
\fpu_add_frac_dp/n4252 , \fpu_add_frac_dp/n4251 ,
\fpu_add_frac_dp/n4250 , \fpu_add_frac_dp/n4249 ,
\fpu_add_frac_dp/n4248 , \fpu_add_frac_dp/n4247 ,
\fpu_add_frac_dp/n4246 , \fpu_add_frac_dp/n4245 ,
\fpu_add_frac_dp/n4244 , \fpu_add_frac_dp/n4243 ,
\fpu_add_frac_dp/n4242 , \fpu_add_frac_dp/n4241 ,
\fpu_add_frac_dp/n4240 , \fpu_add_frac_dp/n4239 ,
\fpu_add_frac_dp/n4238 , \fpu_add_frac_dp/n4237 ,
\fpu_add_frac_dp/n4236 , \fpu_add_frac_dp/n4235 ,
\fpu_add_frac_dp/n4234 , \fpu_add_frac_dp/n4233 ,
\fpu_add_frac_dp/n4232 , \fpu_add_frac_dp/n4231 ,
\fpu_add_frac_dp/n4230 , \fpu_add_frac_dp/n4229 ,
\fpu_add_frac_dp/n4228 , \fpu_add_frac_dp/n4227 ,
\fpu_add_frac_dp/n4226 , \fpu_add_frac_dp/n4225 ,
\fpu_add_frac_dp/n4224 , \fpu_add_frac_dp/n4223 ,
\fpu_add_frac_dp/n4222 , \fpu_add_frac_dp/n4221 ,
\fpu_add_frac_dp/n4220 , \fpu_add_frac_dp/n4219 ,
\fpu_add_frac_dp/n4218 , \fpu_add_frac_dp/n4217 ,
\fpu_add_frac_dp/n4216 , \fpu_add_frac_dp/n4215 ,
\fpu_add_frac_dp/n4214 , \fpu_add_frac_dp/n4213 ,
\fpu_add_frac_dp/n4212 , \fpu_add_frac_dp/n4211 ,
\fpu_add_frac_dp/n4210 , \fpu_add_frac_dp/n4209 ,
\fpu_add_frac_dp/n4208 , \fpu_add_frac_dp/n4207 ,
\fpu_add_frac_dp/n4206 , \fpu_add_frac_dp/n4205 ,
\fpu_add_frac_dp/n4204 , \fpu_add_frac_dp/n4203 ,
\fpu_add_frac_dp/n4202 , \fpu_add_frac_dp/n4201 ,
\fpu_add_frac_dp/n4200 , \fpu_add_frac_dp/n4199 ,
\fpu_add_frac_dp/n4198 , \fpu_add_frac_dp/n4197 ,
\fpu_add_frac_dp/n4196 , \fpu_add_frac_dp/n4195 ,
\fpu_add_frac_dp/n4194 , \fpu_add_frac_dp/n4193 ,
\fpu_add_frac_dp/n4192 , \fpu_add_frac_dp/n4191 ,
\fpu_add_frac_dp/n4190 , \fpu_add_frac_dp/n4189 ,
\fpu_add_frac_dp/n4188 , \fpu_add_frac_dp/n4187 ,
\fpu_add_frac_dp/n4186 , \fpu_add_frac_dp/n4185 ,
\fpu_add_frac_dp/n4184 , \fpu_add_frac_dp/n4183 ,
\fpu_add_frac_dp/n4182 , \fpu_add_frac_dp/n4181 ,
\fpu_add_frac_dp/n4180 , \fpu_add_frac_dp/n4179 ,
\fpu_add_frac_dp/n4178 , \fpu_add_frac_dp/n4177 ,
\fpu_add_frac_dp/n4176 , \fpu_add_frac_dp/n4175 ,
\fpu_add_frac_dp/n4174 , \fpu_add_frac_dp/n4173 ,
\fpu_add_frac_dp/n4172 , \fpu_add_frac_dp/n4171 ,
\fpu_add_frac_dp/n4170 , \fpu_add_frac_dp/n4169 ,
\fpu_add_frac_dp/n4168 , \fpu_add_frac_dp/n4167 ,
\fpu_add_frac_dp/n4166 , \fpu_add_frac_dp/n4165 ,
\fpu_add_frac_dp/n4164 , \fpu_add_frac_dp/n4163 ,
\fpu_add_frac_dp/n4162 , \fpu_add_frac_dp/n4161 ,
\fpu_add_frac_dp/n4160 , \fpu_add_frac_dp/n4159 ,
\fpu_add_frac_dp/n4158 , \fpu_add_frac_dp/n4157 ,
\fpu_add_frac_dp/n4156 , \fpu_add_frac_dp/n4155 ,
\fpu_add_frac_dp/n4154 , \fpu_add_frac_dp/n4153 ,
\fpu_add_frac_dp/n4152 , \fpu_add_frac_dp/n4151 ,
\fpu_add_frac_dp/n4150 , \fpu_add_frac_dp/n4149 ,
\fpu_add_frac_dp/n4148 , \fpu_add_frac_dp/n4147 ,
\fpu_add_frac_dp/n4146 , \fpu_add_frac_dp/n4145 ,
\fpu_add_frac_dp/n4144 , \fpu_add_frac_dp/n4143 ,
\fpu_add_frac_dp/n4142 , \fpu_add_frac_dp/n4141 ,
\fpu_add_frac_dp/n4140 , \fpu_add_frac_dp/n4139 ,
\fpu_add_frac_dp/n4138 , \fpu_add_frac_dp/n4137 ,
\fpu_add_frac_dp/n4136 , \fpu_add_frac_dp/n4135 ,
\fpu_add_frac_dp/n4134 , \fpu_add_frac_dp/n4133 ,
\fpu_add_frac_dp/n4132 , \fpu_add_frac_dp/n4131 ,
\fpu_add_frac_dp/n4130 , \fpu_add_frac_dp/n4129 ,
\fpu_add_frac_dp/n4128 , \fpu_add_frac_dp/n4127 ,
\fpu_add_frac_dp/n4126 , \fpu_add_frac_dp/n4125 ,
\fpu_add_frac_dp/n4124 , \fpu_add_frac_dp/n4123 ,
\fpu_add_frac_dp/n4122 , \fpu_add_frac_dp/n4121 ,
\fpu_add_frac_dp/n4120 , \fpu_add_frac_dp/n4119 ,
\fpu_add_frac_dp/n4118 , \fpu_add_frac_dp/n4117 ,
\fpu_add_frac_dp/n4116 , \fpu_add_frac_dp/n4115 ,
\fpu_add_frac_dp/n4114 , \fpu_add_frac_dp/n4113 ,
\fpu_add_frac_dp/n4112 , \fpu_add_frac_dp/n4111 ,
\fpu_add_frac_dp/n4110 , \fpu_add_frac_dp/n4109 ,
\fpu_add_frac_dp/n4108 , \fpu_add_frac_dp/n4107 ,
\fpu_add_frac_dp/n4106 , \fpu_add_frac_dp/n4105 ,
\fpu_add_frac_dp/n4104 , \fpu_add_frac_dp/n4103 ,
\fpu_add_frac_dp/n4102 , \fpu_add_frac_dp/n4101 ,
\fpu_add_frac_dp/n4100 , \fpu_add_frac_dp/n4099 ,
\fpu_add_frac_dp/n4098 , \fpu_add_frac_dp/n4097 ,
\fpu_add_frac_dp/n4096 , \fpu_add_frac_dp/n4095 ,
\fpu_add_frac_dp/n4094 , \fpu_add_frac_dp/n4093 ,
\fpu_add_frac_dp/n4092 , \fpu_add_frac_dp/n4091 ,
\fpu_add_frac_dp/n4090 , \fpu_add_frac_dp/n4089 ,
\fpu_add_frac_dp/n4088 , \fpu_add_frac_dp/n4087 ,
\fpu_add_frac_dp/n4086 , \fpu_add_frac_dp/n4085 ,
\fpu_add_frac_dp/n4084 , \fpu_add_frac_dp/n4083 ,
\fpu_add_frac_dp/n4082 , \fpu_add_frac_dp/n4081 ,
\fpu_add_frac_dp/n4080 , \fpu_add_frac_dp/n4079 ,
\fpu_add_frac_dp/n4078 , \fpu_add_frac_dp/n4077 ,
\fpu_add_frac_dp/n4076 , \fpu_add_frac_dp/n4075 ,
\fpu_add_frac_dp/n4074 , \fpu_add_frac_dp/n4073 ,
\fpu_add_frac_dp/n4072 , \fpu_add_frac_dp/n4071 ,
\fpu_add_frac_dp/n4070 , \fpu_add_frac_dp/n4069 ,
\fpu_add_frac_dp/n4068 , \fpu_add_frac_dp/n4067 ,
\fpu_add_frac_dp/n4066 , \fpu_add_frac_dp/n4065 ,
\fpu_add_frac_dp/n4064 , \fpu_add_frac_dp/n4063 ,
\fpu_add_frac_dp/n4062 , \fpu_add_frac_dp/n4061 ,
\fpu_add_frac_dp/n4060 , \fpu_add_frac_dp/n4059 ,
\fpu_add_frac_dp/n4058 , \fpu_add_frac_dp/n4057 ,
\fpu_add_frac_dp/n4056 , \fpu_add_frac_dp/n4055 ,
\fpu_add_frac_dp/n4054 , \fpu_add_frac_dp/n4053 ,
\fpu_add_frac_dp/n4052 , \fpu_add_frac_dp/n4051 ,
\fpu_add_frac_dp/n4050 , \fpu_add_frac_dp/n4049 ,
\fpu_add_frac_dp/n4048 , \fpu_add_frac_dp/n4047 ,
\fpu_add_frac_dp/n4046 , \fpu_add_frac_dp/n4045 ,
\fpu_add_frac_dp/n4044 , \fpu_add_frac_dp/n4043 ,
\fpu_add_frac_dp/n4042 , \fpu_add_frac_dp/n4041 ,
\fpu_add_frac_dp/n4040 , \fpu_add_frac_dp/n4039 ,
\fpu_add_frac_dp/n4038 , \fpu_add_frac_dp/n4037 ,
\fpu_add_frac_dp/n4036 , \fpu_add_frac_dp/n4035 ,
\fpu_add_frac_dp/n4034 , \fpu_add_frac_dp/n4033 ,
\fpu_add_frac_dp/n4032 , \fpu_add_frac_dp/n4031 ,
\fpu_add_frac_dp/n4030 , \fpu_add_frac_dp/n4029 ,
\fpu_add_frac_dp/n4028 , \fpu_add_frac_dp/n4027 ,
\fpu_add_frac_dp/n4026 , \fpu_add_frac_dp/n4025 ,
\fpu_add_frac_dp/n4024 , \fpu_add_frac_dp/n4023 ,
\fpu_add_frac_dp/n4022 , \fpu_add_frac_dp/n4021 ,
\fpu_add_frac_dp/n4020 , \fpu_add_frac_dp/n4019 ,
\fpu_add_frac_dp/n4018 , \fpu_add_frac_dp/n4017 ,
\fpu_add_frac_dp/n4016 , \fpu_add_frac_dp/n4015 ,
\fpu_add_frac_dp/n4014 , \fpu_add_frac_dp/n4013 ,
\fpu_add_frac_dp/n4012 , \fpu_add_frac_dp/n4011 ,
\fpu_add_frac_dp/n4010 , \fpu_add_frac_dp/n4009 ,
\fpu_add_frac_dp/n4008 , \fpu_add_frac_dp/n4007 ,
\fpu_add_frac_dp/n4006 , \fpu_add_frac_dp/n4005 ,
\fpu_add_frac_dp/n4004 , \fpu_add_frac_dp/n4003 ,
\fpu_add_frac_dp/n4002 , \fpu_add_frac_dp/n4001 ,
\fpu_add_frac_dp/n4000 , \fpu_add_frac_dp/n3999 ,
\fpu_add_frac_dp/n3998 , \fpu_add_frac_dp/n3997 ,
\fpu_add_frac_dp/n3996 , \fpu_add_frac_dp/n3995 ,
\fpu_add_frac_dp/n3994 , \fpu_add_frac_dp/n3993 ,
\fpu_add_frac_dp/n3992 , \fpu_add_frac_dp/n3991 ,
\fpu_add_frac_dp/n3990 , \fpu_add_frac_dp/n3989 ,
\fpu_add_frac_dp/n3988 , \fpu_add_frac_dp/n3987 ,
\fpu_add_frac_dp/n3986 , \fpu_add_frac_dp/n3985 ,
\fpu_add_frac_dp/n3984 , \fpu_add_frac_dp/n3983 ,
\fpu_add_frac_dp/n3982 , \fpu_add_frac_dp/n3981 ,
\fpu_add_frac_dp/n3980 , \fpu_add_frac_dp/n3979 ,
\fpu_add_frac_dp/n3978 , \fpu_add_frac_dp/n3977 ,
\fpu_add_frac_dp/n3976 , \fpu_add_frac_dp/n3975 ,
\fpu_add_frac_dp/n3974 , \fpu_add_frac_dp/n3973 ,
\fpu_add_frac_dp/n3972 , \fpu_add_frac_dp/n3971 ,
\fpu_add_frac_dp/n3970 , \fpu_add_frac_dp/n3969 ,
\fpu_add_frac_dp/n3968 , \fpu_add_frac_dp/n3967 ,
\fpu_add_frac_dp/n3966 , \fpu_add_frac_dp/n3965 ,
\fpu_add_frac_dp/n3964 , \fpu_add_frac_dp/n3963 ,
\fpu_add_frac_dp/n3962 , \fpu_add_frac_dp/n3961 ,
\fpu_add_frac_dp/n3960 , \fpu_add_frac_dp/n3959 ,
\fpu_add_frac_dp/n3958 , \fpu_add_frac_dp/n3957 ,
\fpu_add_frac_dp/n3956 , \fpu_add_frac_dp/n3955 ,
\fpu_add_frac_dp/n3954 , \fpu_add_frac_dp/n3953 ,
\fpu_add_frac_dp/n3952 , \fpu_add_frac_dp/n3951 ,
\fpu_add_frac_dp/n3950 , \fpu_add_frac_dp/n3949 ,
\fpu_add_frac_dp/n3948 , \fpu_add_frac_dp/n3947 ,
\fpu_add_frac_dp/n3946 , \fpu_add_frac_dp/n3945 ,
\fpu_add_frac_dp/n3944 , \fpu_add_frac_dp/n3943 ,
\fpu_add_frac_dp/n3942 , \fpu_add_frac_dp/n3941 ,
\fpu_add_frac_dp/n3940 , \fpu_add_frac_dp/n3939 ,
\fpu_add_frac_dp/n3938 , \fpu_add_frac_dp/n3937 ,
\fpu_add_frac_dp/n3936 , \fpu_add_frac_dp/n3935 ,
\fpu_add_frac_dp/n3934 , \fpu_add_frac_dp/n3933 ,
\fpu_add_frac_dp/n3932 , \fpu_add_frac_dp/n3931 ,
\fpu_add_frac_dp/n3930 , \fpu_add_frac_dp/n3929 ,
\fpu_add_frac_dp/n3928 , \fpu_add_frac_dp/n3927 ,
\fpu_add_frac_dp/n3926 , \fpu_add_frac_dp/n3925 ,
\fpu_add_frac_dp/n3924 , \fpu_add_frac_dp/n3923 ,
\fpu_add_frac_dp/n3922 , \fpu_add_frac_dp/n3921 ,
\fpu_add_frac_dp/n3920 , \fpu_add_frac_dp/n3919 ,
\fpu_add_frac_dp/n3918 , \fpu_add_frac_dp/n3917 ,
\fpu_add_frac_dp/n3916 , \fpu_add_frac_dp/n3915 ,
\fpu_add_frac_dp/n3914 , \fpu_add_frac_dp/n3913 ,
\fpu_add_frac_dp/n3912 , \fpu_add_frac_dp/n3911 ,
\fpu_add_frac_dp/n3910 , \fpu_add_frac_dp/n3909 ,
\fpu_add_frac_dp/n3908 , \fpu_add_frac_dp/n3907 ,
\fpu_add_frac_dp/n3906 , \fpu_add_frac_dp/n3905 ,
\fpu_add_frac_dp/n3904 , \fpu_add_frac_dp/n3903 ,
\fpu_add_frac_dp/n3902 , \fpu_add_frac_dp/n3901 ,
\fpu_add_frac_dp/n3900 , \fpu_add_frac_dp/n3899 ,
\fpu_add_frac_dp/n3898 , \fpu_add_frac_dp/n3897 ,
\fpu_add_frac_dp/n3896 , \fpu_add_frac_dp/n3895 ,
\fpu_add_frac_dp/n3894 , \fpu_add_frac_dp/n3893 ,
\fpu_add_frac_dp/n3892 , \fpu_add_frac_dp/n3891 ,
\fpu_add_frac_dp/n3890 , \fpu_add_frac_dp/n3889 ,
\fpu_add_frac_dp/n3888 , \fpu_add_frac_dp/n3887 ,
\fpu_add_frac_dp/n3886 , \fpu_add_frac_dp/n3885 ,
\fpu_add_frac_dp/n3884 , \fpu_add_frac_dp/n3883 ,
\fpu_add_frac_dp/n3882 , \fpu_add_frac_dp/n3881 ,
\fpu_add_frac_dp/n3880 , \fpu_add_frac_dp/n3879 ,
\fpu_add_frac_dp/n3878 , \fpu_add_frac_dp/n3877 ,
\fpu_add_frac_dp/n3876 , \fpu_add_frac_dp/n3875 ,
\fpu_add_frac_dp/n3874 , \fpu_add_frac_dp/n3873 ,
\fpu_add_frac_dp/n3872 , \fpu_add_frac_dp/n3871 ,
\fpu_add_frac_dp/n3870 , \fpu_add_frac_dp/n3869 ,
\fpu_add_frac_dp/n3868 , \fpu_add_frac_dp/n3867 ,
\fpu_add_frac_dp/n3866 , \fpu_add_frac_dp/n3865 ,
\fpu_add_frac_dp/n3864 , \fpu_add_frac_dp/n3863 ,
\fpu_add_frac_dp/n3862 , \fpu_add_frac_dp/n3861 ,
\fpu_add_frac_dp/n3860 , \fpu_add_frac_dp/n3859 ,
\fpu_add_frac_dp/n3858 , \fpu_add_frac_dp/n3857 ,
\fpu_add_frac_dp/n3856 , \fpu_add_frac_dp/n3855 ,
\fpu_add_frac_dp/n3854 , \fpu_add_frac_dp/n3853 ,
\fpu_add_frac_dp/n3852 , \fpu_add_frac_dp/n3851 ,
\fpu_add_frac_dp/n3850 , \fpu_add_frac_dp/n3849 ,
\fpu_add_frac_dp/n3848 , \fpu_add_frac_dp/n3847 ,
\fpu_add_frac_dp/n3846 , \fpu_add_frac_dp/n3845 ,
\fpu_add_frac_dp/n3844 , \fpu_add_frac_dp/n3843 ,
\fpu_add_frac_dp/n3842 , \fpu_add_frac_dp/n3841 ,
\fpu_add_frac_dp/n3840 , \fpu_add_frac_dp/n3839 ,
\fpu_add_frac_dp/n3838 , \fpu_add_frac_dp/n3837 ,
\fpu_add_frac_dp/n3836 , \fpu_add_frac_dp/n3835 ,
\fpu_add_frac_dp/n3834 , \fpu_add_frac_dp/n3833 ,
\fpu_add_frac_dp/n3832 , \fpu_add_frac_dp/n3831 ,
\fpu_add_frac_dp/n3830 , \fpu_add_frac_dp/n3829 ,
\fpu_add_frac_dp/n3828 , \fpu_add_frac_dp/n3827 ,
\fpu_add_frac_dp/n3826 , \fpu_add_frac_dp/n3825 ,
\fpu_add_frac_dp/n3824 , \fpu_add_frac_dp/n3823 ,
\fpu_add_frac_dp/n3822 , \fpu_add_frac_dp/n3821 ,
\fpu_add_frac_dp/n3820 , \fpu_add_frac_dp/n3819 ,
\fpu_add_frac_dp/n3818 , \fpu_add_frac_dp/n3817 ,
\fpu_add_frac_dp/n3816 , \fpu_add_frac_dp/n3815 ,
\fpu_add_frac_dp/n3814 , \fpu_add_frac_dp/n3813 ,
\fpu_add_frac_dp/n3812 , \fpu_add_frac_dp/n3811 ,
\fpu_add_frac_dp/n3810 , \fpu_add_frac_dp/n3809 ,
\fpu_add_frac_dp/n3808 , \fpu_add_frac_dp/n3807 ,
\fpu_add_frac_dp/n3806 , \fpu_add_frac_dp/n3805 ,
\fpu_add_frac_dp/n3804 , \fpu_add_frac_dp/n3803 ,
\fpu_add_frac_dp/n3802 , \fpu_add_frac_dp/n3801 ,
\fpu_add_frac_dp/n3800 , \fpu_add_frac_dp/n3799 ,
\fpu_add_frac_dp/n3798 , \fpu_add_frac_dp/n3797 ,
\fpu_add_frac_dp/n3796 , \fpu_add_frac_dp/n3795 ,
\fpu_add_frac_dp/n3794 , \fpu_add_frac_dp/n3792 ,
\fpu_add_frac_dp/n3791 , \fpu_add_frac_dp/n3790 ,
\fpu_add_frac_dp/n3789 , \fpu_add_frac_dp/n3788 ,
\fpu_add_frac_dp/n3787 , \fpu_add_frac_dp/n3786 ,
\fpu_add_frac_dp/n3785 , \fpu_add_frac_dp/n3784 ,
\fpu_add_frac_dp/n3783 , \fpu_add_frac_dp/n3782 ,
\fpu_add_frac_dp/n3781 , \fpu_add_frac_dp/n3780 ,
\fpu_add_frac_dp/n3779 , \fpu_add_frac_dp/n3778 ,
\fpu_add_frac_dp/n3777 , \fpu_add_frac_dp/n3776 ,
\fpu_add_frac_dp/n3775 , \fpu_add_frac_dp/n3774 ,
\fpu_add_frac_dp/n3773 , \fpu_add_frac_dp/n3772 ,
\fpu_add_frac_dp/n3771 , \fpu_add_frac_dp/n3770 ,
\fpu_add_frac_dp/n3769 , \fpu_add_frac_dp/n3768 ,
\fpu_add_frac_dp/n3767 , \fpu_add_frac_dp/n3766 ,
\fpu_add_frac_dp/n3765 , \fpu_add_frac_dp/n3764 ,
\fpu_add_frac_dp/n3763 , \fpu_add_frac_dp/n3762 ,
\fpu_add_frac_dp/n3761 , \fpu_add_frac_dp/n3760 ,
\fpu_add_frac_dp/n3759 , \fpu_add_frac_dp/n3758 ,
\fpu_add_frac_dp/n3757 , \fpu_add_frac_dp/n3756 ,
\fpu_add_frac_dp/n3755 , \fpu_add_frac_dp/n3754 ,
\fpu_add_frac_dp/n3753 , \fpu_add_frac_dp/n3752 ,
\fpu_add_frac_dp/n3751 , \fpu_add_frac_dp/n3750 ,
\fpu_add_frac_dp/n3749 , \fpu_add_frac_dp/n3748 ,
\fpu_add_frac_dp/n3747 , \fpu_add_frac_dp/n3746 ,
\fpu_add_frac_dp/n3745 , \fpu_add_frac_dp/n3744 ,
\fpu_add_frac_dp/n3743 , \fpu_add_frac_dp/n3742 ,
\fpu_add_frac_dp/n3741 , \fpu_add_frac_dp/n3740 ,
\fpu_add_frac_dp/n3739 , \fpu_add_frac_dp/n3738 ,
\fpu_add_frac_dp/n3737 , \fpu_add_frac_dp/n3736 ,
\fpu_add_frac_dp/n3735 , \fpu_add_frac_dp/n3734 ,
\fpu_add_frac_dp/n3733 , \fpu_add_frac_dp/n3732 ,
\fpu_add_frac_dp/n3731 , \fpu_add_frac_dp/n3730 ,
\fpu_add_frac_dp/n3729 , \fpu_add_frac_dp/n3728 ,
\fpu_add_frac_dp/n3727 , \fpu_add_frac_dp/n3726 ,
\fpu_add_frac_dp/n3725 , \fpu_add_frac_dp/n3724 ,
\fpu_add_frac_dp/n3723 , \fpu_add_frac_dp/n3722 ,
\fpu_add_frac_dp/n3721 , \fpu_add_frac_dp/n3720 ,
\fpu_add_frac_dp/n3719 , \fpu_add_frac_dp/n3718 ,
\fpu_add_frac_dp/n3717 , \fpu_add_frac_dp/n3716 ,
\fpu_add_frac_dp/n3715 , \fpu_add_frac_dp/n3714 ,
\fpu_add_frac_dp/n3713 , \fpu_add_frac_dp/n3712 ,
\fpu_add_frac_dp/n3711 , \fpu_add_frac_dp/n3710 ,
\fpu_add_frac_dp/n3709 , \fpu_add_frac_dp/n3708 ,
\fpu_add_frac_dp/n3707 , \fpu_add_frac_dp/n3706 ,
\fpu_add_frac_dp/n3705 , \fpu_add_frac_dp/n3704 ,
\fpu_add_frac_dp/n3703 , \fpu_add_frac_dp/n3702 ,
\fpu_add_frac_dp/n3701 , \fpu_add_frac_dp/n3700 ,
\fpu_add_frac_dp/n3699 , \fpu_add_frac_dp/n3698 ,
\fpu_add_frac_dp/n3697 , \fpu_add_frac_dp/n3696 ,
\fpu_add_frac_dp/n3695 , \fpu_add_frac_dp/n3694 ,
\fpu_add_frac_dp/n3693 , \fpu_add_frac_dp/n3692 ,
\fpu_add_frac_dp/n3691 , \fpu_add_frac_dp/n3690 ,
\fpu_add_frac_dp/n3689 , \fpu_add_frac_dp/n3688 ,
\fpu_add_frac_dp/n3687 , \fpu_add_frac_dp/n3686 ,
\fpu_add_frac_dp/n3685 , \fpu_add_frac_dp/n3684 ,
\fpu_add_frac_dp/n3683 , \fpu_add_frac_dp/n3682 ,
\fpu_add_frac_dp/n3681 , \fpu_add_frac_dp/n3680 ,
\fpu_add_frac_dp/n3679 , \fpu_add_frac_dp/n3678 ,
\fpu_add_frac_dp/n3677 , \fpu_add_frac_dp/n3676 ,
\fpu_add_frac_dp/n3675 , \fpu_add_frac_dp/n3674 ,
\fpu_add_frac_dp/n3673 , \fpu_add_frac_dp/n3672 ,
\fpu_add_frac_dp/n3671 , \fpu_add_frac_dp/n3670 ,
\fpu_add_frac_dp/n3669 , \fpu_add_frac_dp/n3668 ,
\fpu_add_frac_dp/n3667 , \fpu_add_frac_dp/n3666 ,
\fpu_add_frac_dp/n3665 , \fpu_add_frac_dp/n3664 ,
\fpu_add_frac_dp/n3663 , \fpu_add_frac_dp/n3662 ,
\fpu_add_frac_dp/n3661 , \fpu_add_frac_dp/n3660 ,
\fpu_add_frac_dp/n3659 , \fpu_add_frac_dp/n3658 ,
\fpu_add_frac_dp/n3657 , \fpu_add_frac_dp/n3656 ,
\fpu_add_frac_dp/n3655 , \fpu_add_frac_dp/n3654 ,
\fpu_add_frac_dp/n3653 , \fpu_add_frac_dp/n3652 ,
\fpu_add_frac_dp/n3651 , \fpu_add_frac_dp/n3650 ,
\fpu_add_frac_dp/n3649 , \fpu_add_frac_dp/n3648 ,
\fpu_add_frac_dp/n3647 , \fpu_add_frac_dp/n3646 ,
\fpu_add_frac_dp/n3645 , \fpu_add_frac_dp/n3644 ,
\fpu_add_frac_dp/n3643 , \fpu_add_frac_dp/n3642 ,
\fpu_add_frac_dp/n3641 , \fpu_add_frac_dp/n3640 ,
\fpu_add_frac_dp/n3639 , \fpu_add_frac_dp/n3638 ,
\fpu_add_frac_dp/n3637 , \fpu_add_frac_dp/n3636 ,
\fpu_add_frac_dp/n3635 , \fpu_add_frac_dp/n3634 ,
\fpu_add_frac_dp/n3633 , \fpu_add_frac_dp/n3632 ,
\fpu_add_frac_dp/n3631 , \fpu_add_frac_dp/n3630 ,
\fpu_add_frac_dp/n3629 , \fpu_add_frac_dp/n3628 ,
\fpu_add_frac_dp/n3627 , \fpu_add_frac_dp/n3626 ,
\fpu_add_frac_dp/n3625 , \fpu_add_frac_dp/n3624 ,
\fpu_add_frac_dp/n3623 , \fpu_add_frac_dp/n3622 ,
\fpu_add_frac_dp/n3621 , \fpu_add_frac_dp/n3620 ,
\fpu_add_frac_dp/n3619 , \fpu_add_frac_dp/n3618 ,
\fpu_add_frac_dp/n3617 , \fpu_add_frac_dp/n3616 ,
\fpu_add_frac_dp/n3615 , \fpu_add_frac_dp/n3614 ,
\fpu_add_frac_dp/n3613 , \fpu_add_frac_dp/n3612 ,
\fpu_add_frac_dp/n3611 , \fpu_add_frac_dp/n3610 ,
\fpu_add_frac_dp/n3609 , \fpu_add_frac_dp/n3608 ,
\fpu_add_frac_dp/n3607 , \fpu_add_frac_dp/n3606 ,
\fpu_add_frac_dp/n3605 , \fpu_add_frac_dp/n3604 ,
\fpu_add_frac_dp/n3603 , \fpu_add_frac_dp/n3602 ,
\fpu_add_frac_dp/n3601 , \fpu_add_frac_dp/n3600 ,
\fpu_add_frac_dp/n3599 , \fpu_add_frac_dp/n3598 ,
\fpu_add_frac_dp/n3597 , \fpu_add_frac_dp/n3596 ,
\fpu_add_frac_dp/n3595 , \fpu_add_frac_dp/n3594 ,
\fpu_add_frac_dp/n3593 , \fpu_add_frac_dp/n3592 ,
\fpu_add_frac_dp/n3591 , \fpu_add_frac_dp/n3590 ,
\fpu_add_frac_dp/n3589 , \fpu_add_frac_dp/n3588 ,
\fpu_add_frac_dp/n3587 , \fpu_add_frac_dp/n3586 ,
\fpu_add_frac_dp/n3585 , \fpu_add_frac_dp/n3584 ,
\fpu_add_frac_dp/n3583 , \fpu_add_frac_dp/n3582 ,
\fpu_add_frac_dp/n3581 , \fpu_add_frac_dp/n3580 ,
\fpu_add_frac_dp/n3579 , \fpu_add_frac_dp/n3578 ,
\fpu_add_frac_dp/n3577 , \fpu_add_frac_dp/n3576 ,
\fpu_add_frac_dp/n3575 , \fpu_add_frac_dp/n3574 ,
\fpu_add_frac_dp/n3573 , \fpu_add_frac_dp/n3572 ,
\fpu_add_frac_dp/n3571 , \fpu_add_frac_dp/n3570 ,
\fpu_add_frac_dp/n3569 , \fpu_add_frac_dp/n3568 ,
\fpu_add_frac_dp/n3567 , \fpu_add_frac_dp/n3566 ,
\fpu_add_frac_dp/n3565 , \fpu_add_frac_dp/n3564 ,
\fpu_add_frac_dp/n3563 , \fpu_add_frac_dp/n3562 ,
\fpu_add_frac_dp/n3561 , \fpu_add_frac_dp/n3560 ,
\fpu_add_frac_dp/n3559 , \fpu_add_frac_dp/n3558 ,
\fpu_add_frac_dp/n3557 , \fpu_add_frac_dp/n3556 ,
\fpu_add_frac_dp/n3555 , \fpu_add_frac_dp/n3554 ,
\fpu_add_frac_dp/n3553 , \fpu_add_frac_dp/n3552 ,
\fpu_add_frac_dp/n3551 , \fpu_add_frac_dp/n3550 ,
\fpu_add_frac_dp/n3549 , \fpu_add_frac_dp/n3548 ,
\fpu_add_frac_dp/n3547 , \fpu_add_frac_dp/n3546 ,
\fpu_add_frac_dp/n3545 , \fpu_add_frac_dp/n3544 ,
\fpu_add_frac_dp/n3543 , \fpu_add_frac_dp/n3542 ,
\fpu_add_frac_dp/n3541 , \fpu_add_frac_dp/n3540 ,
\fpu_add_frac_dp/n3539 , \fpu_add_frac_dp/n3538 ,
\fpu_add_frac_dp/n3537 , \fpu_add_frac_dp/n3536 ,
\fpu_add_frac_dp/n3535 , \fpu_add_frac_dp/n3534 ,
\fpu_add_frac_dp/n3533 , \fpu_add_frac_dp/n3532 ,
\fpu_add_frac_dp/n3531 , \fpu_add_frac_dp/n3530 ,
\fpu_add_frac_dp/n3529 , \fpu_add_frac_dp/n3528 ,
\fpu_add_frac_dp/n3527 , \fpu_add_frac_dp/n3526 ,
\fpu_add_frac_dp/n3525 , \fpu_add_frac_dp/n3524 ,
\fpu_add_frac_dp/n3523 , \fpu_add_frac_dp/n3522 ,
\fpu_add_frac_dp/n3521 , \fpu_add_frac_dp/n3520 ,
\fpu_add_frac_dp/n3519 , \fpu_add_frac_dp/n3518 ,
\fpu_add_frac_dp/n3517 , \fpu_add_frac_dp/n3516 ,
\fpu_add_frac_dp/n3515 , \fpu_add_frac_dp/n3514 ,
\fpu_add_frac_dp/n3513 , \fpu_add_frac_dp/n3512 ,
\fpu_add_frac_dp/n3511 , \fpu_add_frac_dp/n3510 ,
\fpu_add_frac_dp/n3509 , \fpu_add_frac_dp/n3508 ,
\fpu_add_frac_dp/n3507 , \fpu_add_frac_dp/n3506 ,
\fpu_add_frac_dp/n3505 , \fpu_add_frac_dp/n3504 ,
\fpu_add_frac_dp/n3503 , \fpu_add_frac_dp/n3502 ,
\fpu_add_frac_dp/n3501 , \fpu_add_frac_dp/n3500 ,
\fpu_add_frac_dp/n3499 , \fpu_add_frac_dp/n3498 ,
\fpu_add_frac_dp/n3497 , \fpu_add_frac_dp/n3496 ,
\fpu_add_frac_dp/n3495 , \fpu_add_frac_dp/n3494 ,
\fpu_add_frac_dp/n3493 , \fpu_add_frac_dp/n3492 ,
\fpu_add_frac_dp/n3491 , \fpu_add_frac_dp/n3490 ,
\fpu_add_frac_dp/n3489 , \fpu_add_frac_dp/n3488 ,
\fpu_add_frac_dp/n3487 , \fpu_add_frac_dp/n3486 ,
\fpu_add_frac_dp/n3485 , \fpu_add_frac_dp/n3484 ,
\fpu_add_frac_dp/n3483 , \fpu_add_frac_dp/n3482 ,
\fpu_add_frac_dp/n3481 , \fpu_add_frac_dp/n3480 ,
\fpu_add_frac_dp/n3479 , \fpu_add_frac_dp/n3478 ,
\fpu_add_frac_dp/n3477 , \fpu_add_frac_dp/n3476 ,
\fpu_add_frac_dp/n3475 , \fpu_add_frac_dp/n3474 ,
\fpu_add_frac_dp/n3473 , \fpu_add_frac_dp/n3472 ,
\fpu_add_frac_dp/n3471 , \fpu_add_frac_dp/n3470 ,
\fpu_add_frac_dp/n3469 , \fpu_add_frac_dp/n3468 ,
\fpu_add_frac_dp/n3467 , \fpu_add_frac_dp/n3466 ,
\fpu_add_frac_dp/n3465 , \fpu_add_frac_dp/n3464 ,
\fpu_add_frac_dp/n3463 , \fpu_add_frac_dp/n3462 ,
\fpu_add_frac_dp/n3461 , \fpu_add_frac_dp/n3460 ,
\fpu_add_frac_dp/n3459 , \fpu_add_frac_dp/n3458 ,
\fpu_add_frac_dp/n3457 , \fpu_add_frac_dp/n3456 ,
\fpu_add_frac_dp/n3455 , \fpu_add_frac_dp/n3454 ,
\fpu_add_frac_dp/n3453 , \fpu_add_frac_dp/n3452 ,
\fpu_add_frac_dp/n3451 , \fpu_add_frac_dp/n3450 ,
\fpu_add_frac_dp/n3449 , \fpu_add_frac_dp/n3448 ,
\fpu_add_frac_dp/n3447 , \fpu_add_frac_dp/n3446 ,
\fpu_add_frac_dp/n3445 , \fpu_add_frac_dp/n3444 ,
\fpu_add_frac_dp/n3443 , \fpu_add_frac_dp/n3442 ,
\fpu_add_frac_dp/n3441 , \fpu_add_frac_dp/n3440 ,
\fpu_add_frac_dp/n3439 , \fpu_add_frac_dp/n3438 ,
\fpu_add_frac_dp/n3437 , \fpu_add_frac_dp/n3436 ,
\fpu_add_frac_dp/n3435 , \fpu_add_frac_dp/n3434 ,
\fpu_add_frac_dp/n3433 , \fpu_add_frac_dp/n3432 ,
\fpu_add_frac_dp/n3431 , \fpu_add_frac_dp/n3430 ,
\fpu_add_frac_dp/n3429 , \fpu_add_frac_dp/n3428 ,
\fpu_add_frac_dp/n3427 , \fpu_add_frac_dp/n3426 ,
\fpu_add_frac_dp/n3425 , \fpu_add_frac_dp/n3424 ,
\fpu_add_frac_dp/n3423 , \fpu_add_frac_dp/n3422 ,
\fpu_add_frac_dp/n3421 , \fpu_add_frac_dp/n3420 ,
\fpu_add_frac_dp/n3419 , \fpu_add_frac_dp/n3418 ,
\fpu_add_frac_dp/n3417 , \fpu_add_frac_dp/n3416 ,
\fpu_add_frac_dp/n3415 , \fpu_add_frac_dp/n3414 ,
\fpu_add_frac_dp/n3413 , \fpu_add_frac_dp/n3412 ,
\fpu_add_frac_dp/n3411 , \fpu_add_frac_dp/n3410 ,
\fpu_add_frac_dp/n3409 , \fpu_add_frac_dp/n3408 ,
\fpu_add_frac_dp/n3407 , \fpu_add_frac_dp/n3406 ,
\fpu_add_frac_dp/n3405 , \fpu_add_frac_dp/n3404 ,
\fpu_add_frac_dp/n3403 , \fpu_add_frac_dp/n3402 ,
\fpu_add_frac_dp/n3401 , \fpu_add_frac_dp/n3400 ,
\fpu_add_frac_dp/n3399 , \fpu_add_frac_dp/n3398 ,
\fpu_add_frac_dp/n3397 , \fpu_add_frac_dp/n3396 ,
\fpu_add_frac_dp/n3395 , \fpu_add_frac_dp/n3394 ,
\fpu_add_frac_dp/n3393 , \fpu_add_frac_dp/n3392 ,
\fpu_add_frac_dp/n3391 , \fpu_add_frac_dp/n3390 ,
\fpu_add_frac_dp/n3389 , \fpu_add_frac_dp/n3388 ,
\fpu_add_frac_dp/n3387 , \fpu_add_frac_dp/n3386 ,
\fpu_add_frac_dp/n3385 , \fpu_add_frac_dp/n3384 ,
\fpu_add_frac_dp/n3383 , \fpu_add_frac_dp/n3382 ,
\fpu_add_frac_dp/n3381 , \fpu_add_frac_dp/n3380 ,
\fpu_add_frac_dp/n3379 , \fpu_add_frac_dp/n3378 ,
\fpu_add_frac_dp/n3377 , \fpu_add_frac_dp/n3376 ,
\fpu_add_frac_dp/n3375 , \fpu_add_frac_dp/n1391 ,
\fpu_add_frac_dp/n1384 , \fpu_add_frac_dp/n1382 ,
\fpu_add_frac_dp/n1355 , \fpu_add_frac_dp/n1354 ,
\fpu_add_frac_dp/n1352 , \fpu_add_frac_dp/n1335 ,
\fpu_add_frac_dp/n1333 , \fpu_add_frac_dp/n1332 ,
\fpu_add_frac_dp/n1315 , \fpu_add_frac_dp/n1314 ,
\fpu_add_frac_dp/n1215 , \fpu_add_frac_dp/n1213 ,
\fpu_add_frac_dp/n1123 , \fpu_add_frac_dp/n1122 ,
\fpu_add_frac_dp/n1119 , \fpu_add_frac_dp/n1115 ,
\fpu_add_frac_dp/n1109 , \fpu_add_frac_dp/n1107 ,
\fpu_add_frac_dp/n1106 , \fpu_add_frac_dp/n1105 ,
\fpu_add_frac_dp/n1104 , \fpu_add_frac_dp/n1103 ,
\fpu_add_frac_dp/n1096 , \fpu_add_frac_dp/n1095 ,
\fpu_add_frac_dp/n1094 , \fpu_add_frac_dp/n1093 ,
\fpu_add_frac_dp/n1090 , \fpu_add_frac_dp/n1089 ,
\fpu_add_frac_dp/n1088 , \fpu_add_frac_dp/n1087 ,
\fpu_add_frac_dp/n1086 , \fpu_add_frac_dp/n1085 ,
\fpu_add_frac_dp/n1084 , \fpu_add_frac_dp/n1083 ,
\fpu_add_frac_dp/n1082 , \fpu_add_frac_dp/n1070 ,
\fpu_add_frac_dp/n1067 , \fpu_add_frac_dp/n1056 ,
\fpu_add_frac_dp/n1050 , \fpu_add_frac_dp/n1048 ,
\fpu_add_frac_dp/n1045 , \fpu_add_frac_dp/n1044 ,
\fpu_add_frac_dp/n1007 , \fpu_add_frac_dp/n1006 ,
\fpu_add_frac_dp/n1005 , \fpu_add_frac_dp/n1004 ,
\fpu_add_frac_dp/n1003 , \fpu_add_frac_dp/n1002 ,
\fpu_add_frac_dp/n1001 , \fpu_add_frac_dp/n998 ,
\fpu_add_frac_dp/n965 , \fpu_add_frac_dp/n945 ,
\fpu_add_frac_dp/n943 , \fpu_add_frac_dp/n942 ,
\fpu_add_frac_dp/n940 , \fpu_add_frac_dp/n937 ,
\fpu_add_frac_dp/n935 , \fpu_add_frac_dp/n934 ,
\fpu_add_frac_dp/n933 , \fpu_add_frac_dp/n932 ,
\fpu_add_frac_dp/n931 , \fpu_add_frac_dp/n930 ,
\fpu_add_frac_dp/n929 , \fpu_add_frac_dp/n928 ,
\fpu_add_frac_dp/n927 , \fpu_add_frac_dp/n922 ,
\fpu_add_frac_dp/n921 , \fpu_add_frac_dp/n920 ,
\fpu_add_frac_dp/n919 , \fpu_add_frac_dp/n918 ,
\fpu_add_frac_dp/n917 , \fpu_add_frac_dp/n913 ,
\fpu_add_frac_dp/n912 , \fpu_add_frac_dp/n911 ,
\fpu_add_frac_dp/n908 , \fpu_add_frac_dp/n907 ,
\fpu_add_frac_dp/n905 , \fpu_add_frac_dp/n904 ,
\fpu_add_frac_dp/n903 , \fpu_add_frac_dp/n901 ,
\fpu_add_frac_dp/n900 , \fpu_add_frac_dp/n898 ,
\fpu_add_frac_dp/n895 , \fpu_add_frac_dp/n851 ,
\fpu_add_frac_dp/n848 , \fpu_add_frac_dp/n847 ,
\fpu_add_frac_dp/n846 , \fpu_add_frac_dp/n845 ,
\fpu_add_frac_dp/n844 , \fpu_add_frac_dp/n843 ,
\fpu_add_frac_dp/n841 , \fpu_add_frac_dp/n839 ,
\fpu_add_frac_dp/n834 , \fpu_add_frac_dp/n833 ,
\fpu_add_frac_dp/n824 , \fpu_add_frac_dp/n823 ,
\fpu_add_frac_dp/n822 , \fpu_add_frac_dp/n817 ,
\fpu_add_frac_dp/n816 , \fpu_add_frac_dp/n815 ,
\fpu_add_frac_dp/n814 , \fpu_add_frac_dp/n781 ,
\fpu_add_frac_dp/n780 , \fpu_add_frac_dp/n779 ,
\fpu_add_frac_dp/n778 , \fpu_add_frac_dp/n777 ,
\fpu_add_frac_dp/n774 , \fpu_add_frac_dp/n773 ,
\fpu_add_frac_dp/n772 , \fpu_add_frac_dp/n771 ,
\fpu_add_frac_dp/n770 , \fpu_add_frac_dp/n769 ,
\fpu_add_frac_dp/n768 , \fpu_add_frac_dp/n767 ,
\fpu_add_frac_dp/n766 , \fpu_add_frac_dp/n763 ,
\fpu_add_frac_dp/n762 , \fpu_add_frac_dp/n761 ,
\fpu_add_frac_dp/n760 , \fpu_add_frac_dp/n759 ,
\fpu_add_frac_dp/n758 , \fpu_add_frac_dp/n757 ,
\fpu_add_frac_dp/n756 , \fpu_add_frac_dp/n755 ,
\fpu_add_frac_dp/n752 , \fpu_add_frac_dp/n751 ,
\fpu_add_frac_dp/n750 , \fpu_add_frac_dp/n749 ,
\fpu_add_frac_dp/n747 , \fpu_add_frac_dp/n745 ,
\fpu_add_frac_dp/n744 , \fpu_add_frac_dp/n743 ,
\fpu_add_frac_dp/n741 , \fpu_add_frac_dp/n736 ,
\fpu_add_frac_dp/n735 , \fpu_add_frac_dp/n734 ,
\fpu_add_frac_dp/n733 , \fpu_add_frac_dp/n732 ,
\fpu_add_frac_dp/n731 , \fpu_add_frac_dp/n730 ,
\fpu_add_frac_dp/n729 , \fpu_add_frac_dp/n728 ,
\fpu_add_frac_dp/n727 , \fpu_add_frac_dp/n726 ,
\fpu_add_frac_dp/n725 , \fpu_add_frac_dp/n724 ,
\fpu_add_frac_dp/n723 , \fpu_add_frac_dp/n722 ,
\fpu_add_frac_dp/n721 , \fpu_add_frac_dp/n720 ,
\fpu_add_frac_dp/n719 , \fpu_add_frac_dp/n718 ,
\fpu_add_frac_dp/n717 , \fpu_add_frac_dp/n716 ,
\fpu_add_frac_dp/n715 , \fpu_add_frac_dp/n714 ,
\fpu_add_frac_dp/n713 , \fpu_add_frac_dp/n712 ,
\fpu_add_frac_dp/n711 , \fpu_add_frac_dp/n710 ,
\fpu_add_frac_dp/n709 , \fpu_add_frac_dp/n708 ,
\fpu_add_frac_dp/n707 , \fpu_add_frac_dp/n706 ,
\fpu_add_frac_dp/n705 , \fpu_add_frac_dp/n704 ,
\fpu_add_frac_dp/n703 , \fpu_add_frac_dp/n702 ,
\fpu_add_frac_dp/n701 , \fpu_add_frac_dp/n700 ,
\fpu_add_frac_dp/n699 , \fpu_add_frac_dp/n698 ,
\fpu_add_frac_dp/n697 , \fpu_add_frac_dp/n696 ,
\fpu_add_frac_dp/n695 , \fpu_add_frac_dp/n694 ,
\fpu_add_frac_dp/n693 , \fpu_add_frac_dp/n692 ,
\fpu_add_frac_dp/n691 , \fpu_add_frac_dp/n690 ,
\fpu_add_frac_dp/n689 , \fpu_add_frac_dp/n688 ,
\fpu_add_frac_dp/n687 , \fpu_add_frac_dp/n686 ,
\fpu_add_frac_dp/n685 , \fpu_add_frac_dp/n684 ,
\fpu_add_frac_dp/n683 , \fpu_add_frac_dp/n682 ,
\fpu_add_frac_dp/n681 , \fpu_add_frac_dp/n680 ,
\fpu_add_frac_dp/n679 , \fpu_add_frac_dp/n678 ,
\fpu_add_frac_dp/n677 , \fpu_add_frac_dp/n676 ,
\fpu_add_frac_dp/n675 , \fpu_add_frac_dp/n674 ,
\fpu_add_frac_dp/n673 , \fpu_add_frac_dp/n670 ,
\fpu_add_frac_dp/n668 , \fpu_add_frac_dp/n666 ,
\fpu_add_frac_dp/n664 , \fpu_add_frac_dp/n662 ,
\fpu_add_frac_dp/n660 , \fpu_add_frac_dp/n659 ,
\fpu_add_frac_dp/n658 , \fpu_add_frac_dp/n654 ,
\fpu_add_frac_dp/n652 , \fpu_add_frac_dp/n650 ,
\fpu_add_frac_dp/n649 , \fpu_add_frac_dp/n648 ,
\fpu_add_frac_dp/n647 , \fpu_add_frac_dp/n646 ,
\fpu_add_frac_dp/n645 , \fpu_add_frac_dp/n644 ,
\fpu_add_frac_dp/n643 , \fpu_add_frac_dp/n642 ,
\fpu_add_frac_dp/n641 , \fpu_add_frac_dp/n640 ,
\fpu_add_frac_dp/n639 , \fpu_add_frac_dp/n638 ,
\fpu_add_frac_dp/n637 , \fpu_add_frac_dp/n636 ,
\fpu_add_frac_dp/n635 , \fpu_add_frac_dp/n634 ,
\fpu_add_frac_dp/n633 , \fpu_add_frac_dp/n632 ,
\fpu_add_frac_dp/n631 , \fpu_add_frac_dp/n630 ,
\fpu_add_frac_dp/n629 , \fpu_add_frac_dp/n628 ,
\fpu_add_frac_dp/n627 , \fpu_add_frac_dp/n626 ,
\fpu_add_frac_dp/n625 , \fpu_add_frac_dp/n624 ,
\fpu_add_frac_dp/n623 , \fpu_add_frac_dp/n622 ,
\fpu_add_frac_dp/n621 , \fpu_add_frac_dp/n620 ,
\fpu_add_frac_dp/n619 , \fpu_add_frac_dp/n618 ,
\fpu_add_frac_dp/n617 , \fpu_add_frac_dp/n616 ,
\fpu_add_frac_dp/n615 , \fpu_add_frac_dp/n614 ,
\fpu_add_frac_dp/n613 , \fpu_add_frac_dp/n612 ,
\fpu_add_frac_dp/n611 , \fpu_add_frac_dp/n610 ,
\fpu_add_frac_dp/n609 , \fpu_add_frac_dp/n608 ,
\fpu_add_frac_dp/n607 , \fpu_add_frac_dp/n606 ,
\fpu_add_frac_dp/n605 , \fpu_add_frac_dp/n604 ,
\fpu_add_frac_dp/n603 , \fpu_add_frac_dp/n602 ,
\fpu_add_frac_dp/n601 , \fpu_add_frac_dp/n600 ,
\fpu_add_frac_dp/n599 , \fpu_add_frac_dp/n598 ,
\fpu_add_frac_dp/n596 , \fpu_add_frac_dp/n594 ,
\fpu_add_frac_dp/n593 , \fpu_add_frac_dp/n592 ,
\fpu_add_frac_dp/n589 , \fpu_add_frac_dp/n586 ,
\fpu_add_frac_dp/n584 , \fpu_add_frac_dp/n583 ,
\fpu_add_frac_dp/n582 , \fpu_add_frac_dp/n580 ,
\fpu_add_frac_dp/n579 , \fpu_add_frac_dp/n577 ,
\fpu_add_frac_dp/n576 , \fpu_add_frac_dp/n575 ,
\fpu_add_frac_dp/n574 , \fpu_add_frac_dp/n573 ,
\fpu_add_frac_dp/n572 , \fpu_add_frac_dp/n571 ,
\fpu_add_frac_dp/n570 , \fpu_add_frac_dp/n569 ,
\fpu_add_frac_dp/n568 , \fpu_add_frac_dp/n567 ,
\fpu_add_frac_dp/n566 , \fpu_add_frac_dp/n565 ,
\fpu_add_frac_dp/n564 , \fpu_add_frac_dp/n563 ,
\fpu_add_frac_dp/n562 , \fpu_add_frac_dp/n561 ,
\fpu_add_frac_dp/n560 , \fpu_add_frac_dp/n559 ,
\fpu_add_frac_dp/n558 , \fpu_add_frac_dp/n557 ,
\fpu_add_frac_dp/n556 , \fpu_add_frac_dp/n555 ,
\fpu_add_frac_dp/n554 , \fpu_add_frac_dp/n553 ,
\fpu_add_frac_dp/n552 , \fpu_add_frac_dp/n551 ,
\fpu_add_frac_dp/n550 , \fpu_add_frac_dp/n549 ,
\fpu_add_frac_dp/n548 , \fpu_add_frac_dp/n547 ,
\fpu_add_frac_dp/n546 , \fpu_add_frac_dp/n545 ,
\fpu_add_frac_dp/n544 , \fpu_add_frac_dp/n543 ,
\fpu_add_frac_dp/n542 , \fpu_add_frac_dp/n541 ,
\fpu_add_frac_dp/n540 , \fpu_add_frac_dp/n539 ,
\fpu_add_frac_dp/n538 , \fpu_add_frac_dp/n537 ,
\fpu_add_frac_dp/n536 , \fpu_add_frac_dp/n535 ,
\fpu_add_frac_dp/n534 , \fpu_add_frac_dp/n533 ,
\fpu_add_frac_dp/n532 , \fpu_add_frac_dp/n531 ,
\fpu_add_frac_dp/n530 , \fpu_add_frac_dp/n529 ,
\fpu_add_frac_dp/n528 , \fpu_add_frac_dp/n527 ,
\fpu_add_frac_dp/n526 , \fpu_add_frac_dp/n525 ,
\fpu_add_frac_dp/n524 , \fpu_add_frac_dp/n523 ,
\fpu_add_frac_dp/n522 , \fpu_add_frac_dp/n521 ,
\fpu_add_frac_dp/n520 , \fpu_add_frac_dp/n519 ,
\fpu_add_frac_dp/n518 , \fpu_add_frac_dp/n517 ,
\fpu_add_frac_dp/n516 , \fpu_add_frac_dp/n515 ,
\fpu_add_frac_dp/n514 , \fpu_add_frac_dp/n513 ,
\fpu_add_frac_dp/n512 , \fpu_add_frac_dp/n511 ,
\fpu_add_frac_dp/n510 , \fpu_add_frac_dp/n509 ,
\fpu_add_frac_dp/n508 , \fpu_add_frac_dp/n507 ,
\fpu_add_frac_dp/n506 , \fpu_add_frac_dp/n505 ,
\fpu_add_frac_dp/n504 , \fpu_add_frac_dp/n503 ,
\fpu_add_frac_dp/n502 , \fpu_add_frac_dp/n501 ,
\fpu_add_frac_dp/n500 , \fpu_add_frac_dp/n498 ,
\fpu_add_frac_dp/n496 , \fpu_add_frac_dp/n494 ,
\fpu_add_frac_dp/n492 , \fpu_add_frac_dp/n490 ,
\fpu_add_frac_dp/n488 , \fpu_add_frac_dp/n486 ,
\fpu_add_frac_dp/n484 , \fpu_add_frac_dp/n482 ,
\fpu_add_frac_dp/n480 , \fpu_add_frac_dp/n478 ,
\fpu_add_frac_dp/n476 , \fpu_add_frac_dp/n474 ,
\fpu_add_frac_dp/n472 , \fpu_add_frac_dp/n470 ,
\fpu_add_frac_dp/n468 , \fpu_add_frac_dp/n466 ,
\fpu_add_frac_dp/n464 , \fpu_add_frac_dp/n462 ,
\fpu_add_frac_dp/n460 , \fpu_add_frac_dp/n458 ,
\fpu_add_frac_dp/n456 , \fpu_add_frac_dp/n454 ,
\fpu_add_frac_dp/n452 , \fpu_add_frac_dp/n450 ,
\fpu_add_frac_dp/n448 , \fpu_add_frac_dp/n446 ,
\fpu_add_frac_dp/n444 , \fpu_add_frac_dp/n442 ,
\fpu_add_frac_dp/n440 , \fpu_add_frac_dp/n438 ,
\fpu_add_frac_dp/n436 , \fpu_add_frac_dp/n434 ,
\fpu_add_frac_dp/n432 , \fpu_add_frac_dp/n430 ,
\fpu_add_frac_dp/n428 , \fpu_add_frac_dp/n426 ,
\fpu_add_frac_dp/n424 , \fpu_add_frac_dp/n422 ,
\fpu_add_frac_dp/n420 , \fpu_add_frac_dp/n418 ,
\fpu_add_frac_dp/n416 , \fpu_add_frac_dp/n414 ,
\fpu_add_frac_dp/n412 , \fpu_add_frac_dp/n410 ,
\fpu_add_frac_dp/n408 , \fpu_add_frac_dp/n406 ,
\fpu_add_frac_dp/n404 , \fpu_add_frac_dp/n402 ,
\fpu_add_frac_dp/n400 , \fpu_add_frac_dp/n398 ,
\fpu_add_frac_dp/n396 , \fpu_add_frac_dp/n394 ,
\fpu_add_frac_dp/n392 , \fpu_add_frac_dp/n390 ,
\fpu_add_frac_dp/n388 , \fpu_add_frac_dp/n386 ,
\fpu_add_frac_dp/n384 , \fpu_add_frac_dp/n382 ,
\fpu_add_frac_dp/n380 , \fpu_add_frac_dp/n378 ,
\fpu_add_frac_dp/n377 , \fpu_add_frac_dp/n376 ,
\fpu_add_frac_dp/n375 , \fpu_add_frac_dp/n374 ,
\fpu_add_frac_dp/n373 , \fpu_add_frac_dp/n372 ,
\fpu_add_frac_dp/n371 , \fpu_add_frac_dp/n370 ,
\fpu_add_frac_dp/n369 , \fpu_add_frac_dp/n368 ,
\fpu_add_frac_dp/n367 , \fpu_add_frac_dp/n366 ,
\fpu_add_frac_dp/n365 , \fpu_add_frac_dp/n364 ,
\fpu_add_frac_dp/n363 , \fpu_add_frac_dp/n362 ,
\fpu_add_frac_dp/n361 , \fpu_add_frac_dp/n360 ,
\fpu_add_frac_dp/n359 , \fpu_add_frac_dp/n358 ,
\fpu_add_frac_dp/n357 , \fpu_add_frac_dp/n356 ,
\fpu_add_frac_dp/n355 , \fpu_add_frac_dp/n354 ,
\fpu_add_frac_dp/n353 , \fpu_add_frac_dp/n352 ,
\fpu_add_frac_dp/n351 , \fpu_add_frac_dp/n350 ,
\fpu_add_frac_dp/n349 , \fpu_add_frac_dp/n348 ,
\fpu_add_frac_dp/n347 , \fpu_add_frac_dp/n346 ,
\fpu_add_frac_dp/n345 , \fpu_add_frac_dp/n344 ,
\fpu_add_frac_dp/n343 , \fpu_add_frac_dp/n342 ,
\fpu_add_frac_dp/n341 , \fpu_add_frac_dp/n340 ,
\fpu_add_frac_dp/n339 , \fpu_add_frac_dp/n338 ,
\fpu_add_frac_dp/n337 , \fpu_add_frac_dp/n336 ,
\fpu_add_frac_dp/n335 , \fpu_add_frac_dp/n334 ,
\fpu_add_frac_dp/n333 , \fpu_add_frac_dp/n332 ,
\fpu_add_frac_dp/n331 , \fpu_add_frac_dp/n330 ,
\fpu_add_frac_dp/n329 , \fpu_add_frac_dp/n328 ,
\fpu_add_frac_dp/n327 , \fpu_add_frac_dp/n326 ,
\fpu_add_frac_dp/n325 , \fpu_add_frac_dp/n324 ,
\fpu_add_frac_dp/n323 , \fpu_add_frac_dp/n322 ,
\fpu_add_frac_dp/n321 , \fpu_add_frac_dp/n320 ,
\fpu_add_frac_dp/n319 , \fpu_add_frac_dp/n318 ,
\fpu_add_frac_dp/n317 , \fpu_add_frac_dp/n316 ,
\fpu_add_frac_dp/n315 , \fpu_add_frac_dp/n313 ,
\fpu_add_frac_dp/n311 , \fpu_add_frac_dp/n309 ,
\fpu_add_frac_dp/n307 , \fpu_add_frac_dp/n305 ,
\fpu_add_frac_dp/n303 , \fpu_add_frac_dp/n301 ,
\fpu_add_frac_dp/n299 , \fpu_add_frac_dp/n297 ,
\fpu_add_frac_dp/n295 , \fpu_add_frac_dp/n293 ,
\fpu_add_frac_dp/n291 , \fpu_add_frac_dp/n289 ,
\fpu_add_frac_dp/n287 , \fpu_add_frac_dp/n285 ,
\fpu_add_frac_dp/n283 , \fpu_add_frac_dp/n282 ,
\fpu_add_frac_dp/n281 , \fpu_add_frac_dp/n280 ,
\fpu_add_frac_dp/n279 , \fpu_add_frac_dp/n278 ,
\fpu_add_frac_dp/n277 , \fpu_add_frac_dp/n276 ,
\fpu_add_frac_dp/n275 , \fpu_add_frac_dp/n274 ,
\fpu_add_frac_dp/n273 , \fpu_add_frac_dp/n272 ,
\fpu_add_frac_dp/n271 , \fpu_add_frac_dp/n270 ,
\fpu_add_frac_dp/n269 , \fpu_add_frac_dp/n268 ,
\fpu_add_frac_dp/n267 , \fpu_add_frac_dp/n266 ,
\fpu_add_frac_dp/n265 , \fpu_add_frac_dp/n264 ,
\fpu_add_frac_dp/n263 , \fpu_add_frac_dp/n262 ,
\fpu_add_frac_dp/n261 , \fpu_add_frac_dp/n260 ,
\fpu_add_frac_dp/n259 , \fpu_add_frac_dp/n258 ,
\fpu_add_frac_dp/n257 , \fpu_add_frac_dp/n256 ,
\fpu_add_frac_dp/n255 , \fpu_add_frac_dp/n254 ,
\fpu_add_frac_dp/n253 , \fpu_add_frac_dp/n252 ,
\fpu_add_frac_dp/n251 , \fpu_add_frac_dp/n250 ,
\fpu_add_frac_dp/n249 , \fpu_add_frac_dp/n248 ,
\fpu_add_frac_dp/n247 , \fpu_add_frac_dp/n246 ,
\fpu_add_frac_dp/n245 , \fpu_add_frac_dp/n244 ,
\fpu_add_frac_dp/n243 , \fpu_add_frac_dp/n242 ,
\fpu_add_frac_dp/n241 , \fpu_add_frac_dp/n240 ,
\fpu_add_frac_dp/n239 , \fpu_add_frac_dp/n238 ,
\fpu_add_frac_dp/n237 , \fpu_add_frac_dp/n236 ,
\fpu_add_frac_dp/n235 , \fpu_add_frac_dp/n234 ,
\fpu_add_frac_dp/n233 , \fpu_add_frac_dp/n232 ,
\fpu_add_frac_dp/n231 , \fpu_add_frac_dp/n230 ,
\fpu_add_frac_dp/n229 , \fpu_add_frac_dp/n228 ,
\fpu_add_frac_dp/n227 , \fpu_add_frac_dp/n226 ,
\fpu_add_frac_dp/n225 , \fpu_add_frac_dp/n224 ,
\fpu_add_frac_dp/n223 , \fpu_add_frac_dp/n222 ,
\fpu_add_frac_dp/n221 , \fpu_add_frac_dp/n220 ,
\fpu_add_frac_dp/n219 , \fpu_add_frac_dp/n218 ,
\fpu_add_frac_dp/n217 , \fpu_add_frac_dp/n216 ,
\fpu_add_frac_dp/n215 , \fpu_add_frac_dp/n214 ,
\fpu_add_frac_dp/n213 , \fpu_add_frac_dp/n212 ,
\fpu_add_frac_dp/n211 , \fpu_add_frac_dp/n210 ,
\fpu_add_frac_dp/n209 , \fpu_add_frac_dp/n208 ,
\fpu_add_frac_dp/n207 , \fpu_add_frac_dp/n206 ,
\fpu_add_frac_dp/n205 , \fpu_add_frac_dp/n204 ,
\fpu_add_frac_dp/n203 , \fpu_add_frac_dp/n202 ,
\fpu_add_frac_dp/n201 , \fpu_add_frac_dp/n200 ,
\fpu_add_frac_dp/n199 , \fpu_add_frac_dp/n198 ,
\fpu_add_frac_dp/n197 , \fpu_add_frac_dp/n196 ,
\fpu_add_frac_dp/n195 , \fpu_add_frac_dp/n194 ,
\fpu_add_frac_dp/n193 , \fpu_add_frac_dp/n192 ,
\fpu_add_frac_dp/n191 , \fpu_add_frac_dp/n190 ,
\fpu_add_frac_dp/n189 , \fpu_add_frac_dp/n188 ,
\fpu_add_frac_dp/n187 , \fpu_add_frac_dp/n134 ,
\fpu_add_frac_dp/n132 , \fpu_add_frac_dp/n129 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N3 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N8 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N9 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N13 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N14 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N15 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N16 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N17 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N18 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N19 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N20 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N21 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N22 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N23 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N24 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N25 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N26 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N27 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N28 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N29 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N30 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N31 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N32 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N33 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N34 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N35 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N36 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N37 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N38 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N39 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N40 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N41 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N42 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N43 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N44 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N45 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N46 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N47 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N48 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N49 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N50 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N51 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N52 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N53 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N54 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N55 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N56 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N57 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N58 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N59 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N60 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N61 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N62 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N63 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N64 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N65 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N66 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N4 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N5 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N6 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N7 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N8 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N9 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N10 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N11 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N12 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N13 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N14 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N15 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N16 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N17 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N18 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N19 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N20 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N21 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N22 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N23 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N24 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N25 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N26 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N27 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N28 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N29 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N30 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N31 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N32 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N33 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N34 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N35 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N36 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N37 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N38 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N39 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N40 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N41 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N42 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N43 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N44 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N45 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N46 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N47 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N48 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N49 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N50 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N51 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N52 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N53 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N54 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N55 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N56 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N57 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N58 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N59 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N60 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N61 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N62 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N63 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N64 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N65 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N66 ,
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ,
\fpu_add_frac_dp/i_a3stg_frac2/N3 ,
\fpu_add_frac_dp/i_a3stg_frac2/N4 ,
\fpu_add_frac_dp/i_a3stg_frac2/N5 ,
\fpu_add_frac_dp/i_a3stg_frac2/N6 ,
\fpu_add_frac_dp/i_a3stg_frac2/N7 ,
\fpu_add_frac_dp/i_a3stg_frac2/N8 ,
\fpu_add_frac_dp/i_a3stg_frac2/N9 ,
\fpu_add_frac_dp/i_a3stg_frac2/N10 ,
\fpu_add_frac_dp/i_a3stg_frac2/N11 ,
\fpu_add_frac_dp/i_a3stg_frac2/N12 ,
\fpu_add_frac_dp/i_a3stg_frac2/N13 ,
\fpu_add_frac_dp/i_a3stg_frac2/N14 ,
\fpu_add_frac_dp/i_a3stg_frac2/N15 ,
\fpu_add_frac_dp/i_a3stg_frac2/N16 ,
\fpu_add_frac_dp/i_a3stg_frac2/N17 ,
\fpu_add_frac_dp/i_a3stg_frac2/N18 ,
\fpu_add_frac_dp/i_a3stg_frac2/N19 ,
\fpu_add_frac_dp/i_a3stg_frac2/N20 ,
\fpu_add_frac_dp/i_a3stg_frac2/N21 ,
\fpu_add_frac_dp/i_a3stg_frac2/N22 ,
\fpu_add_frac_dp/i_a3stg_frac2/N23 ,
\fpu_add_frac_dp/i_a3stg_frac2/N24 ,
\fpu_add_frac_dp/i_a3stg_frac2/N25 ,
\fpu_add_frac_dp/i_a3stg_frac2/N26 ,
\fpu_add_frac_dp/i_a3stg_frac2/N27 ,
\fpu_add_frac_dp/i_a3stg_frac2/N28 ,
\fpu_add_frac_dp/i_a3stg_frac2/N29 ,
\fpu_add_frac_dp/i_a3stg_frac2/N30 ,
\fpu_add_frac_dp/i_a3stg_frac2/N31 ,
\fpu_add_frac_dp/i_a3stg_frac2/N32 ,
\fpu_add_frac_dp/i_a3stg_frac2/N33 ,
\fpu_add_frac_dp/i_a3stg_frac2/N34 ,
\fpu_add_frac_dp/i_a3stg_frac2/N35 ,
\fpu_add_frac_dp/i_a3stg_frac2/N36 ,
\fpu_add_frac_dp/i_a3stg_frac2/N37 ,
\fpu_add_frac_dp/i_a3stg_frac2/N38 ,
\fpu_add_frac_dp/i_a3stg_frac2/N39 ,
\fpu_add_frac_dp/i_a3stg_frac2/N40 ,
\fpu_add_frac_dp/i_a3stg_frac2/N41 ,
\fpu_add_frac_dp/i_a3stg_frac2/N42 ,
\fpu_add_frac_dp/i_a3stg_frac2/N43 ,
\fpu_add_frac_dp/i_a3stg_frac2/N44 ,
\fpu_add_frac_dp/i_a3stg_frac2/N45 ,
\fpu_add_frac_dp/i_a3stg_frac2/N46 ,
\fpu_add_frac_dp/i_a3stg_frac2/N47 ,
\fpu_add_frac_dp/i_a3stg_frac2/N48 ,
\fpu_add_frac_dp/i_a3stg_frac2/N49 ,
\fpu_add_frac_dp/i_a3stg_frac2/N50 ,
\fpu_add_frac_dp/i_a3stg_frac2/N51 ,
\fpu_add_frac_dp/i_a3stg_frac2/N52 ,
\fpu_add_frac_dp/i_a3stg_frac2/N53 ,
\fpu_add_frac_dp/i_a3stg_frac2/N54 ,
\fpu_add_frac_dp/i_a3stg_frac2/N55 ,
\fpu_add_frac_dp/i_a3stg_frac2/N56 ,
\fpu_add_frac_dp/i_a3stg_frac2/N57 ,
\fpu_add_frac_dp/i_a3stg_frac2/N58 ,
\fpu_add_frac_dp/i_a3stg_frac2/N59 ,
\fpu_add_frac_dp/i_a3stg_frac2/N60 ,
\fpu_add_frac_dp/i_a3stg_frac2/N61 ,
\fpu_add_frac_dp/i_a3stg_frac2/N62 ,
\fpu_add_frac_dp/i_a3stg_frac2/N63 ,
\fpu_add_frac_dp/i_a3stg_frac2/N64 ,
\fpu_add_frac_dp/i_a3stg_frac2/N65 ,
\fpu_add_frac_dp/i_a3stg_frac2/N66 ,
\fpu_add_frac_dp/ckbuf_add_frac_dp/N1 ,
\fpu_add_frac_dp/ckbuf_add_frac_dp/clken ,
\fpu_add_frac_dp/a5stg_in_of ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[63] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[62] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[61] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[60] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[59] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[58] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[57] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[56] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[55] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[54] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[53] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[52] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[51] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[50] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[49] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[48] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[47] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[46] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[45] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[44] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[43] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[42] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[41] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[40] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[39] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[38] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[37] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[36] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[35] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[34] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[33] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[32] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[31] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[30] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[29] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[28] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[27] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[26] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[25] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[24] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[23] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[22] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[21] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[20] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[19] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[18] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[17] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[16] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[15] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[14] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[13] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[12] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[11] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[10] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[9] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[8] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[7] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[6] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[5] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[4] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[3] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[2] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[1] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[63] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[62] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[61] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[60] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[59] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[58] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[57] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[56] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[55] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[54] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[53] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[52] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[51] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[50] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[49] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[48] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[47] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[46] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[45] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[44] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[43] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[42] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[41] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[40] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[39] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[38] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[37] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[36] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[35] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[34] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[33] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[32] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[31] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[30] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[29] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[28] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[27] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[26] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[25] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[24] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[23] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[22] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[21] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[20] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[19] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[18] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[17] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[16] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[15] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[14] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[13] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[12] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[11] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[10] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[9] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[8] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[7] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[6] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[5] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[4] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[3] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[2] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[1] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[63] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[62] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[61] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[60] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[59] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[58] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[57] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[56] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[55] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[54] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[53] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[52] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[51] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[50] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[49] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[48] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[47] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[46] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[45] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[44] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[43] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[42] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[41] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[40] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[39] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[38] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[37] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[36] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[35] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[34] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[33] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[32] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[31] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[30] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[29] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[28] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[27] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[26] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[25] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[24] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[23] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[22] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[21] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[20] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[19] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[18] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[17] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[16] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[15] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[14] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[13] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[12] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[11] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[10] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[9] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[8] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[7] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[6] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[5] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[4] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[3] ,
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[2] ,
\fpu_add_frac_dp/a4stg_shl_cnt_dec54_1[1] ,
\fpu_add_frac_dp/a3stg_fracadd[0] , \fpu_add_frac_dp/a3stg_frac2[63] ,
\fpu_add_frac_dp/a2stg_shr_cnt[5] ,
\fpu_add_frac_dp/a2stg_shr_cnt_4[3] ,
\fpu_add_frac_dp/a2stg_frac2a[58] , \fpu_add_frac_dp/a1stg_in2[3] ,
n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58,
n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72,
n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86,
n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100,
n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122,
n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144,
n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155,
n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166,
n167, n168, n169, n170, n171, n172, n173, n174, n175, n176, n177,
n178, n179, n180, n181, n182, n183, n184, n185, n186, n187, n188,
n189, n190, n191, n192, n193, n194, n195, n196, n197, n198, n199,
n200, n201, n202, n203, n204, n205, n206, n207, n208, n209, n210,
n211, n212, n213, n214, n215, n216, n217, n218, n219, n220, n221,
n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, n232,
n233, n234, n235, n236, n237, n238, n239, n240, n241, n242, n243,
n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, n254,
n255, n256, n257, n258, n259, n260, n261, n262, n263, n264, n265,
n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, n276,
n277, n278, n279, n280, n281, n282, n283, n284, n285, n286, n287,
n288, n289, n290, n291, n292, n293, n294, n295, n296, n297, n298,
n299, n300, n301, n302, n303, n304, n305, n306, n307, n308, n309,
n310, n311, n312, n313, n314, n315, n316, n317, n318, n319, n320,
n321, n322, n323, n324, n325, n326, n327, n328, n329, n330, n331,
n332, n333, n334, n335, n336, n337, n338, n339, n340, n341, n342,
n343, n344, n345, n346, n347, n348, n349, n350, n351, n352, n353,
n354, n355, n356, n357, n358, n359, n360, n361, n362, n363, n364,
n365, n366, n367, n368, n369, n370, n371, n372, n373, n374, n375,
n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, n386,
n387, n388, n389, n390, n391, n392, n393, n394, n395, n396, n397,
n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408,
n409, n410, n411, n412, n413, n414, n415, n416, n417, n418, n419,
n420, n421, n422, n423, n424, n425, n426, n427, n428, n429, n430,
n431, n432, n433, n434, n435, n436, n437, n438, n439, n440, n441,
n442, n443, n444, n445, n446, n447, n448, n449, n450, n451, n452,
n453, n454, n455, n456, n457, n458, n459, n460, n461, n462, n463,
n464, n465, n466, n467, n468, n469, n470, n471, n472, n473, n474,
n475, n476, n477, n478, n479, n480, n481, n482, n483, n484, n485,
n486, n487, n488, n489, n490, n491, n492, n493, n494, n495, n496,
n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507,
n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518,
n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, n529,
n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540,
n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, n551,
n552, n553, n554, n555, n556, n557, n558, n559, n560, n561, n562,
n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, n573,
n574, n575, n576, n577, n578, n579, n580, n581, n582, n583, n584,
n585, n586, n587, n588, n589, n590, n591, n592, n593, n594, n595,
n596, n597, n598, n599, n600, n601, n602, n603, n604, n605, n606,
n607, n608, n609, n610, n611, n612, n613, n614, n615, n616, n617,
n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, n628,
n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639,
n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650,
n651, n652, n653, n654, n655, n656, n657, n658, n659, n660, n661,
n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672,
n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, n683,
n684, n685, n686, n687, n688, n689, n690, n691, n692, n693, n694,
n695, n696, n697, n698, n699, n700, n701, n702, n703, n704, n705,
n706, n707, n708, n709, n710, n711, n712, n713, n714, n715, n716,
n717, n718, n719, n720, n721, n722, n723, n724, n725, n726, n727,
n728, n729, n730, n731, n732, n733, n734, n735, n736, n737, n738,
n739, n740, n741, n742, n743, n744, n745, n746, n747, n748, n749,
n750, n751, n752, n753, n754, n755, n756, n757, n758, n759, n760,
n761, n762, n763, n764, n765, n766, n767, n768, n769, n770, n771,
n772, n773, n774, n775, n776, n777, n778, n779, n780, n781, n782,
n783, n784, n785, n786, n787, n788, n789, n790, n791, n792, n793,
n794, n795, n796, n797, n798, n799, n800, n801, n802, n803, n804,
n805, n806, n807, n808, n809, n810, n811, n812, n813, n814, n815,
n816, n817, n818, n819, n820, n821, n822, n823, n824, n825, n826,
n827, n828, n829, n830, n831, n832, n833, n834, n835, n836, n837,
n838, n839, n840, n841, n842, n843, n844, n845, n846, n847, n848,
n849, n850, n851, n852, n853, n854, n855, n856, n857, n858, n859,
n860, n861, n862, n863, n864, n865, n866, n867, n868, n869, n870,
n871, n872, n873, n874, n875, n876, n877, n878, n879, n880, n881,
n882, n883, n884, n885, n886, n887, n888, n889, n890, n891, n892,
n893, n894, n895, n896, n897, n898, n899, n900, n901, n902, n903,
n904, n905, n906, n907, n908, n909, n910, n911, n912, n913, n914,
n915, n916, n917, n918, n919, n920, n921, n922, n923, n924, n925,
n926, n927, n928, n929, n930, n931, n932, n933, n934, n935, n936,
n937, n938, n939, n940, n941, n942, n943, n944, n945, n946, n947,
n948, n949, n950, n951, n952, n953, n954, n955, n956, n957, n958,
n959, n960, n961, n962, n963, n964, n965, n966, n967, n968, n969,
n970, n971, n972, n973, n974, n975, n976, n977, n978, n979, n980,
n981, n982, n983, n984, n985, n986, n987, n988, n989, n990, n991,
n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001, n1002,
n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012,
n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022,
n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032,
n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042,
n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052,
n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062,
n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072,
n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082,
n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092,
n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102,
n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112,
n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122,
n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132,
n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142,
n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152,
n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162,
n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172,
n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182,
n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192,
n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202,
n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212,
n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222,
n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232,
n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242,
n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252,
n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262,
n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272,
n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282,
n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292,
n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302,
n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312,
n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322,
n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332,
n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342,
n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352,
n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362,
n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372,
n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382,
n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392,
n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402,
n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412,
n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422,
n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432,
n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442,
n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452,
n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462,
n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472,
n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482,
n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492,
n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502,
n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512,
n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522,
n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532,
n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542,
n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552,
n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562,
n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572,
n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582,
n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592,
n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602,
n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612,
n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622,
n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632,
n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642,
n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652,
n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662,
n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672,
n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682,
n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692,
n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702,
n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712,
n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722,
n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732,
n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742,
n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752,
n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772,
n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782,
n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822,
n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832,
n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842,
n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852,
n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862,
n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872,
n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882,
n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892,
n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902,
n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912,
n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922,
n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932,
n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942,
n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952,
n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962,
n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972,
n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982,
n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992,
n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002,
n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012,
n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022,
n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032,
n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042,
n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052,
n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062,
n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072,
n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082,
n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092,
n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102,
n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112,
n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122,
n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132,
n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142,
n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152,
n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162,
n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172,
n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182,
n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192,
n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202,
n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212,
n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222,
n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232,
n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242,
n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252,
n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262,
n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272,
n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282,
n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292,
n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302,
n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312,
n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322,
n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332,
n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342,
n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352,
n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362,
n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372,
n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382,
n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392,
n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402,
n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412,
n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422,
n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432,
n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442,
n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452,
n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462,
n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472,
n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482,
n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492,
n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502,
n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512,
n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522,
n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532,
n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542,
n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552,
n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562,
n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572,
n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582,
n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592,
n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602,
n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612,
n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622,
n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632,
n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642,
n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652,
n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662,
n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672,
n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682,
n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692,
n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702,
n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712,
n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722,
n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732,
n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742,
n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752,
n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762,
n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772,
n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782,
n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792,
n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802,
n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812,
n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822,
n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832,
n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842,
n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852,
n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862,
n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872,
n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882,
n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892,
n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902,
n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912,
n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922,
n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932,
n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942,
n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952,
n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962,
n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972,
n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982,
n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992,
n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002,
n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012,
n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022,
n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032,
n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042,
n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052,
n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062,
n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072,
n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082,
n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092,
n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102,
n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112,
n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122,
n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132,
n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142,
n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152,
n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162,
n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172,
n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182,
n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192,
n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202,
n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212,
n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222,
n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232,
n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242,
n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252,
n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262,
n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272,
n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282,
n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292,
n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302,
n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312,
n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322,
n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332,
n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342,
n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352,
n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362,
n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372,
n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382,
n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392,
n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402,
n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412,
n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422,
n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432,
n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442,
n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452,
n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462,
n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472,
n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482,
n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492,
n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502,
n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512,
n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522,
n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532,
n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542,
n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552,
n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562,
n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572,
n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582,
n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592,
n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602,
n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612,
n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622,
n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632,
n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642,
n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652,
n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662,
n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672,
n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682,
n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692,
n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702,
n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712,
n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722,
n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732,
n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742,
n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752,
n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762,
n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772,
n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782,
n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792,
n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802,
n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812,
n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822,
n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832,
n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842,
n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852,
n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862,
n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872,
n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882,
n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892,
n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902,
n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912,
n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922,
n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932,
n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942,
n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952,
n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962,
n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972,
n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982,
n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992,
n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002,
n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012,
n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022,
n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032,
n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042,
n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052,
n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062,
n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072,
n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082,
n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092,
n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102,
n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112,
n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122,
n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132,
n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142,
n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152,
n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161, n4162,
n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172,
n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182,
n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192,
n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202,
n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212,
n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222,
n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231, n4232,
n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242,
n4243, n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4251, n4252,
n4253, n4254, n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262,
n4263, n4264, n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272,
n4273, n4274, n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282,
n4283, n4284, n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292,
n4293, n4294, n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302,
n4303, n4304, n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312,
n4313, n4314, n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322,
n4323, n4324, n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332,
n4333, n4334, n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342,
n4343, n4344, n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352,
n4353, n4354, n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362,
n4363, n4364, n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372,
n4373, n4374, n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382,
n4383, n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392,
n4393, n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402,
n4403, n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412,
n4413, n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422,
n4423, n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432,
n4433, n4434, n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442,
n4443, n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452,
n4453, n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462,
n4463, n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472,
n4473, n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482,
n4483, n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492,
n4493, n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502,
n4503, n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512,
n4513, n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522,
n4523, n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532,
n4533, n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541, n4542,
n4543, n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552,
n4553, n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561, n4562,
n4563, n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572,
n4573, n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581, n4582,
n4583, n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591, n4592,
n4593, n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601, n4602,
n4603, n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611, n4612,
n4613, n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622,
n4623, n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631, n4632,
n4633, n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641, n4642,
n4643, n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651, n4652,
n4653, n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662,
n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671, n4672,
n4673, n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681, n4682,
n4683, n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691, n4692,
n4693, n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701, n4702,
n4703, n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711, n4712,
n4713, n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721, n4722,
n4723, n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732,
n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741, n4742,
n4743, n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751, n4752,
n4753, n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761, n4762,
n4763, n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772,
n4773, n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781, n4782,
n4783, n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791, n4792,
n4793, n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801, n4802,
n4803, n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811, n4812,
n4813, n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821, n4822,
n4823, n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831, n4832,
n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841, n4842,
n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851, n4852,
n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861, n4862,
n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871, n4872,
n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881, n4882,
n4883, n4884, n4885, n4886, n4887, n4888;
assign so = 1'b0;
assign add_exc_out[1] = 1'b0;
DFFX1 \fpu_add_ctl/i_a2stg_fracadd_frac2/q_reg[0] ( .D(\fpu_add_ctl/n540 ),
.CLK(rclk), .Q(n155), .QN(\fpu_add_ctl/n1 ) );
DFFX1 \fpu_add_ctl/i_add_nx_out/q_reg[0] ( .D(\fpu_add_ctl/n541 ), .CLK(
rclk), .Q(\fpu_add_ctl/add_nx_out ), .QN(\fpu_add_ctl/n2 ) );
DFFX1 \fpu_add_ctl/i_add_uf_out/q_reg[0] ( .D(\fpu_add_ctl/n542 ), .CLK(
rclk), .Q(add_exc_out[2]), .QN(\fpu_add_ctl/n3 ) );
DFFX1 \fpu_add_ctl/i_add_of_out_tmp2/q_reg[0] ( .D(\fpu_add_ctl/n543 ),
.CLK(rclk), .Q(\fpu_add_ctl/add_of_out_tmp2 ), .QN(\fpu_add_ctl/n4 )
);
DFFX1 \fpu_add_ctl/i_add_of_out_tmp1/q_reg[0] ( .D(\fpu_add_ctl/n544 ),
.CLK(rclk), .Q(n1234), .QN(\fpu_add_ctl/n5 ) );
DFFX1 \fpu_add_ctl/i_add_nv_out/q_reg[0] ( .D(\fpu_add_ctl/n545 ), .CLK(
rclk), .Q(add_exc_out[4]) );
DFFX1 \fpu_add_ctl/i_a4stg_nx/q_reg[0] ( .D(\fpu_add_ctl/n546 ), .CLK(rclk),
.Q(n1245), .QN(\fpu_add_ctl/n7 ) );
DFFX1 \fpu_add_ctl/i_a4stg_nx2/q_reg[0] ( .D(\fpu_add_ctl/n547 ), .CLK(rclk), .Q(n513) );
DFFX1 \fpu_add_ctl/i_a4stg_of_mask/q_reg[0] ( .D(\fpu_add_ctl/n548 ), .CLK(
rclk), .Q(n452), .QN(\fpu_add_ctl/n9 ) );
DFFX1 \fpu_add_ctl/i_a4stg_of_mask2/q_reg[0] ( .D(\fpu_add_ctl/n549 ),
.CLK(rclk), .Q(n905) );
DFFX1 \fpu_add_ctl/i_a4stg_nv/q_reg[0] ( .D(\fpu_add_ctl/n550 ), .CLK(rclk),
.Q(n1074) );
DFFX1 \fpu_add_ctl/i_a4stg_nv2/q_reg[0] ( .D(\fpu_add_ctl/n551 ), .CLK(rclk), .Q(n512) );
DFFX1 \fpu_add_ctl/i_a3stg_nx_tmp3/q_reg[0] ( .D(\fpu_add_ctl/n552 ), .CLK(
rclk), .Q(n1265), .QN(\fpu_add_ctl/n13 ) );
DFFX1 \fpu_add_ctl/i_a3stg_nx_tmp2/q_reg[0] ( .D(\fpu_add_ctl/n553 ), .CLK(
rclk), .Q(n1272), .QN(\fpu_add_ctl/n14 ) );
DFFX1 \fpu_add_ctl/i_a3stg_nx_tmp1/q_reg[0] ( .D(\fpu_add_ctl/n554 ), .CLK(
rclk), .Q(n1249), .QN(\fpu_add_ctl/n15 ) );
DFFX1 \fpu_add_ctl/i_a3stg_a2_expadd_11/q_reg[0] ( .D(\fpu_add_ctl/n555 ),
.CLK(rclk), .Q(\fpu_add_ctl/a3stg_a2_expadd_11 ), .QN(
\fpu_add_ctl/n16 ) );
DFFX1 \fpu_add_ctl/i_a3stg_of_mask/q_reg[0] ( .D(\fpu_add_ctl/n556 ), .CLK(
rclk), .Q(n137) );
DFFX1 \fpu_add_ctl/i_a3stg_nv/q_reg[0] ( .D(\fpu_add_ctl/n557 ), .CLK(rclk),
.Q(n140) );
DFFX1 \fpu_add_ctl/i_a2stg_of_mask/q_reg[0] ( .D(\fpu_add_ctl/n558 ), .CLK(
rclk), .Q(n1077) );
DFFX1 \fpu_add_ctl/i_a2stg_nv/q_reg[0] ( .D(\fpu_add_ctl/n559 ), .CLK(rclk),
.Q(n903) );
DFFX1 \fpu_add_ctl/i_add_cc_out/q_reg[1] ( .D(\fpu_add_ctl/n560 ), .CLK(
rclk), .Q(add_cc_out[1]) );
DFFX1 \fpu_add_ctl/i_add_cc_out/q_reg[0] ( .D(\fpu_add_ctl/n561 ), .CLK(
rclk), .Q(add_cc_out[0]) );
DFFX1 \fpu_add_ctl/i_add_sign_out/q_reg[0] ( .D(\fpu_add_ctl/n562 ), .CLK(
rclk), .Q(add_sign_out) );
DFFX1 \fpu_add_ctl/i_a4stg_cc/q_reg[1] ( .D(\fpu_add_ctl/n563 ), .CLK(rclk),
.Q(n557) );
DFFX1 \fpu_add_ctl/i_a4stg_cc/q_reg[0] ( .D(\fpu_add_ctl/n564 ), .CLK(rclk),
.Q(n556) );
DFFX1 \fpu_add_ctl/i_a4stg_sign/q_reg[0] ( .D(\fpu_add_ctl/n565 ), .CLK(
rclk), .Q(n444), .QN(\fpu_add_ctl/n337 ) );
DFFX1 \fpu_add_ctl/i_a4stg_sign2/q_reg[0] ( .D(\fpu_add_ctl/n566 ), .CLK(
rclk), .Q(n884) );
DFFX1 \fpu_add_ctl/i_a3stg_cc/q_reg[1] ( .D(\fpu_add_ctl/n567 ), .CLK(rclk),
.Q(n1083) );
DFFX1 \fpu_add_ctl/i_a3stg_cc/q_reg[0] ( .D(\fpu_add_ctl/n568 ), .CLK(rclk),
.Q(n1082) );
DFFX1 \fpu_add_ctl/i_a3stg_sign/q_reg[0] ( .D(\fpu_add_ctl/n569 ), .CLK(
rclk), .Q(n149) );
DFFX1 \fpu_add_ctl/i_a2stg_2inf_in/q_reg[0] ( .D(\fpu_add_ctl/n570 ), .CLK(
rclk), .Q(n957), .QN(\fpu_add_ctl/n31 ) );
DFFX1 \fpu_add_ctl/i_a2stg_2zero_in/q_reg[0] ( .D(\fpu_add_ctl/n571 ),
.CLK(rclk), .Q(n1217), .QN(\fpu_add_ctl/n32 ) );
DFFX1 \fpu_add_ctl/i_a2stg_qnan_in1/q_reg[0] ( .D(\fpu_add_ctl/n572 ),
.CLK(rclk), .Q(n1068) );
DFFX1 \fpu_add_ctl/i_a2stg_snan_in1/q_reg[0] ( .D(\fpu_add_ctl/n573 ),
.CLK(rclk), .Q(n422), .QN(\fpu_add_ctl/n311 ) );
DFFX1 \fpu_add_ctl/i_a2stg_qnan_in2/q_reg[0] ( .D(\fpu_add_ctl/n574 ),
.CLK(rclk), .Q(n1213), .QN(\fpu_add_ctl/n34 ) );
DFFX1 \fpu_add_ctl/i_a2stg_snan_in2/q_reg[0] ( .D(\fpu_add_ctl/n575 ),
.CLK(rclk), .Q(n1173), .QN(\fpu_add_ctl/n310 ) );
DFFX1 \fpu_add_ctl/i_a2stg_nan_in2/q_reg[0] ( .D(\fpu_add_ctl/n576 ), .CLK(
rclk), .Q(\fpu_add_ctl/a2stg_nan_in2 ), .QN(\fpu_add_ctl/n338 ) );
DFFX1 \fpu_add_ctl/i_a2stg_nan_in/q_reg[0] ( .D(\fpu_add_ctl/n577 ), .CLK(
rclk), .Q(n851), .QN(\fpu_add_ctl/n37 ) );
DFFX1 \fpu_add_ctl/i_a2stg_in2_gt_in1_exp/q_reg[0] ( .D(\fpu_add_ctl/n578 ),
.CLK(rclk), .Q(\fpu_add_ctl/a2stg_in2_gt_in1_exp ), .QN(
\fpu_add_ctl/n38 ) );
DFFX1 \fpu_add_ctl/i_a2stg_in2_eq_in1_exp/q_reg[0] ( .D(\fpu_add_ctl/n579 ),
.CLK(rclk), .Q(n1004), .QN(\fpu_add_ctl/n335 ) );
DFFX1 \fpu_add_ctl/i_a2stg_in2_gt_in1_frac/q_reg[0] ( .D(\fpu_add_ctl/n580 ), .CLK(rclk), .Q(n1212), .QN(\fpu_add_ctl/n39 ) );
DFFX1 \fpu_add_ctl/i_a2stg_in2_neq_in1_frac/q_reg[0] ( .D(
\fpu_add_ctl/n581 ), .CLK(rclk), .Q(n1210), .QN(\fpu_add_ctl/n40 ) );
DFFX1 \fpu_add_ctl/i_a2stg_sub/q_reg[0] ( .D(\fpu_add_ctl/n582 ), .CLK(rclk), .Q(\fpu_add_ctl/n313 ), .QN(n754) );
DFFX1 \fpu_add_ctl/i_a2stg_sign2/q_reg[0] ( .D(\fpu_add_ctl/n583 ), .CLK(
rclk), .Q(n270), .QN(\fpu_add_ctl/n316 ) );
DFFX1 \fpu_add_ctl/i_a2stg_sign1/q_reg[0] ( .D(\fpu_add_ctl/n584 ), .CLK(
rclk), .Q(n433), .QN(\fpu_add_ctl/n41 ) );
DFFX1 \fpu_add_ctl/i_add_pipe_active/q_reg[0] ( .D(
\fpu_add_ctl/i_add_pipe_active/N7 ), .CLK(rclk), .Q(add_pipe_active)
);
DFFX1 \fpu_add_ctl/i_add_fcc_out/q_reg[1] ( .D(\fpu_add_ctl/n585 ), .CLK(
rclk), .Q(add_fcc_out[1]) );
DFFX1 \fpu_add_ctl/i_add_fcc_out/q_reg[0] ( .D(\fpu_add_ctl/n586 ), .CLK(
rclk), .Q(add_fcc_out[0]) );
DFFSSRX1 \fpu_add_ctl/i_add_id_out/q_reg[9] ( .D(\fpu_add_ctl/n470 ),
.RSTB(add_id_out_in[9]), .SETB(1'b1), .CLK(rclk), .Q(
\fpu_add_ctl/add_id_out[9] ) );
DFFSSRX1 \fpu_add_ctl/i_add_id_out/q_reg[8] ( .D(\fpu_add_ctl/n470 ),
.RSTB(add_id_out_in[8]), .SETB(1'b1), .CLK(rclk), .Q(
\fpu_add_ctl/add_id_out[8] ) );
DFFSSRX1 \fpu_add_ctl/i_add_id_out/q_reg[7] ( .D(\fpu_add_ctl/n470 ),
.RSTB(add_id_out_in[7]), .SETB(1'b1), .CLK(rclk), .Q(
\fpu_add_ctl/add_id_out[7] ) );
DFFSSRX1 \fpu_add_ctl/i_add_id_out/q_reg[6] ( .D(\fpu_add_ctl/n470 ),
.RSTB(add_id_out_in[6]), .SETB(1'b1), .CLK(rclk), .Q(
\fpu_add_ctl/add_id_out[6] ) );
DFFSSRX1 \fpu_add_ctl/i_add_id_out/q_reg[5] ( .D(\fpu_add_ctl/n470 ),
.RSTB(add_id_out_in[5]), .SETB(1'b1), .CLK(rclk), .Q(
\fpu_add_ctl/add_id_out[5] ) );
DFFSSRX1 \fpu_add_ctl/i_add_id_out/q_reg[4] ( .D(\fpu_add_ctl/n470 ),
.RSTB(add_id_out_in[4]), .SETB(1'b1), .CLK(rclk), .Q(
\fpu_add_ctl/add_id_out[4] ) );
DFFSSRX1 \fpu_add_ctl/i_add_id_out/q_reg[3] ( .D(\fpu_add_ctl/n470 ),
.RSTB(add_id_out_in[3]), .SETB(1'b1), .CLK(rclk), .Q(
\fpu_add_ctl/add_id_out[3] ) );
DFFSSRX1 \fpu_add_ctl/i_add_id_out/q_reg[2] ( .D(\fpu_add_ctl/n470 ),
.RSTB(add_id_out_in[2]), .SETB(1'b1), .CLK(rclk), .Q(
\fpu_add_ctl/add_id_out[2] ) );
DFFSSRX1 \fpu_add_ctl/i_add_id_out/q_reg[1] ( .D(\fpu_add_ctl/n470 ),
.RSTB(add_id_out_in[1]), .SETB(1'b1), .CLK(rclk), .Q(
\fpu_add_ctl/add_id_out[1] ) );
DFFSSRX1 \fpu_add_ctl/i_add_id_out/q_reg[0] ( .D(\fpu_add_ctl/n470 ),
.RSTB(add_id_out_in[0]), .SETB(1'b1), .CLK(rclk), .Q(
\fpu_add_ctl/add_id_out[0] ) );
DFFX1 \fpu_add_ctl/i_a4stg_opdec/q_reg[17] ( .D(\fpu_add_ctl/n606 ), .CLK(
rclk), .Q(n1242), .QN(\fpu_add_ctl/n65 ) );
DFFX1 \fpu_add_ctl/i_a5stg_opdec/q_reg[8] ( .D(\fpu_add_ctl/n612 ), .CLK(
rclk), .Q(n1157), .QN(\fpu_add_ctl/n66 ) );
DFFX1 \fpu_add_ctl/i_a6stg_opdec/q_reg[4] ( .D(\fpu_add_ctl/n607 ), .CLK(
rclk), .Q(a6stg_dbl_dst) );
DFFX1 \fpu_add_ctl/i_a5stg_opdec/q_reg[7] ( .D(\fpu_add_ctl/n613 ), .CLK(
rclk), .Q(n1073) );
DFFX1 \fpu_add_ctl/i_a6stg_opdec/q_reg[3] ( .D(\fpu_add_ctl/n608 ), .CLK(
rclk), .Q(a6stg_sng_dst) );
DFFX1 \fpu_add_ctl/i_a5stg_opdec/q_reg[6] ( .D(\fpu_add_ctl/n614 ), .CLK(
rclk), .Q(n1072) );
DFFX1 \fpu_add_ctl/i_a6stg_opdec/q_reg[2] ( .D(\fpu_add_ctl/n609 ), .CLK(
rclk), .Q(a6stg_long_dst) );
DFFX1 \fpu_add_ctl/i_a5stg_opdec/q_reg[5] ( .D(\fpu_add_ctl/n615 ), .CLK(
rclk), .Q(n1071) );
DFFX1 \fpu_add_ctl/i_a6stg_opdec/q_reg[1] ( .D(\fpu_add_ctl/n610 ), .CLK(
rclk), .Q(a6stg_int_dst) );
DFFX1 \fpu_add_ctl/i_a5stg_opdec/q_reg[4] ( .D(\fpu_add_ctl/n616 ), .CLK(
rclk), .Q(n1070) );
DFFX1 \fpu_add_ctl/i_a6stg_opdec/q_reg[0] ( .D(\fpu_add_ctl/n611 ), .CLK(
rclk), .Q(a6stg_fcmpop) );
DFFX1 \fpu_add_ctl/i_a5stg_opdec/q_reg[3] ( .D(\fpu_add_ctl/n617 ), .CLK(
rclk), .Q(n1069) );
DFFX1 \fpu_add_ctl/i_a5stg_opdec/q_reg[2] ( .D(\fpu_add_ctl/n618 ), .CLK(
rclk), .Q(n622), .QN(\fpu_add_ctl/n315 ) );
DFFX1 \fpu_add_ctl/i_a5stg_opdec/q_reg[1] ( .D(\fpu_add_ctl/n619 ), .CLK(
rclk), .Q(n552), .QN(\fpu_add_ctl/n77 ) );
DFFX1 \fpu_add_ctl/i_a5stg_opdec/q_reg[0] ( .D(\fpu_add_ctl/n620 ), .CLK(
rclk), .Q(n108), .QN(\fpu_add_ctl/n78 ) );
DFFX1 \fpu_add_ctl/i_a4stg_opdec/q_reg[16] ( .D(\fpu_add_ctl/n621 ), .CLK(
rclk), .Q(n339), .QN(\fpu_add_ctl/n79 ) );
DFFX1 \fpu_add_ctl/i_a4stg_opdec/q_reg[15] ( .D(\fpu_add_ctl/n622 ), .CLK(
rclk), .Q(n136) );
DFFX1 \fpu_add_ctl/i_a4stg_opdec/q_reg[14] ( .D(\fpu_add_ctl/n623 ), .CLK(
rclk), .Q(n135) );
DFFX1 \fpu_add_ctl/i_a4stg_opdec/q_reg[13] ( .D(\fpu_add_ctl/n624 ), .CLK(
rclk), .Q(n333) );
DFFX1 \fpu_add_ctl/i_a4stg_opdec/q_reg[12] ( .D(\fpu_add_ctl/n625 ), .CLK(
rclk), .Q(n134) );
DFFX1 \fpu_add_ctl/i_a4stg_opdec/q_reg[11] ( .D(\fpu_add_ctl/n626 ), .CLK(
rclk), .Q(n927), .QN(\fpu_add_ctl/n939 ) );
DFFX1 \fpu_add_ctl/i_a4stg_opdec/q_reg[10] ( .D(\fpu_add_ctl/n627 ), .CLK(
rclk), .Q(n490), .QN(\fpu_add_ctl/n334 ) );
DFFX1 \fpu_add_ctl/i_a4stg_opdec/q_reg[9] ( .D(\fpu_add_ctl/n628 ), .CLK(
rclk), .Q(n1246), .QN(\fpu_add_ctl/n85 ) );
DFFX1 \fpu_add_ctl/i_a4stg_opdec/q_reg[8] ( .D(\fpu_add_ctl/n629 ), .CLK(
rclk), .Q(n324), .QN(\fpu_add_ctl/n86 ) );
DFFX1 \fpu_add_ctl/i_a4stg_opdec/q_reg[7] ( .D(\fpu_add_ctl/n630 ), .CLK(
rclk), .Q(\fpu_add_ctl/n319 ), .QN(n642) );
DFFX1 \fpu_add_ctl/i_a4stg_opdec/q_reg[6] ( .D(\fpu_add_ctl/n631 ), .CLK(
rclk), .Q(n420), .QN(\fpu_add_ctl/n941 ) );
DFFX1 \fpu_add_ctl/i_a4stg_opdec/q_reg[5] ( .D(\fpu_add_ctl/n632 ), .CLK(
rclk), .Q(n148), .QN(\fpu_add_ctl/n323 ) );
DFFX1 \fpu_add_ctl/i_a4stg_opdec/q_reg[4] ( .D(\fpu_add_ctl/n633 ), .CLK(
rclk), .Q(n21), .QN(\fpu_add_ctl/n322 ) );
DFFX1 \fpu_add_ctl/i_a4stg_opdec/q_reg[3] ( .D(\fpu_add_ctl/n634 ), .CLK(
rclk), .Q(n55), .QN(\fpu_add_ctl/n89 ) );
DFFX1 \fpu_add_ctl/i_a4stg_opdec/q_reg[2] ( .D(\fpu_add_ctl/n635 ), .CLK(
rclk), .Q(n492), .QN(\fpu_add_ctl/n90 ) );
DFFX1 \fpu_add_ctl/i_a4stg_opdec/q_reg[1] ( .D(\fpu_add_ctl/n636 ), .CLK(
rclk), .Q(n1032) );
DFFX1 \fpu_add_ctl/i_a4stg_opdec/q_reg[0] ( .D(\fpu_add_ctl/n637 ), .CLK(
rclk), .Q(n1031) );
DFFX1 \fpu_add_ctl/i_a3stg_opdec/q_reg[18] ( .D(\fpu_add_ctl/n638 ), .CLK(
rclk), .Q(n576) );
DFFX1 \fpu_add_ctl/i_a3stg_opdec/q_reg[17] ( .D(\fpu_add_ctl/n639 ), .CLK(
rclk), .Q(\fpu_add_ctl/n325 ), .QN(\fpu_add_ctl/n255 ) );
DFFX1 \fpu_add_ctl/i_a3stg_opdec/q_reg[16] ( .D(\fpu_add_ctl/n640 ), .CLK(
rclk), .Q(n575) );
DFFX1 \fpu_add_ctl/i_a3stg_opdec/q_reg[15] ( .D(\fpu_add_ctl/n641 ), .CLK(
rclk), .Q(n574) );
DFFX1 \fpu_add_ctl/i_a3stg_opdec/q_reg[14] ( .D(\fpu_add_ctl/n642 ), .CLK(
rclk), .Q(n1030) );
DFFX1 \fpu_add_ctl/i_a3stg_opdec/q_reg[13] ( .D(\fpu_add_ctl/n643 ), .CLK(
rclk), .Q(n549), .QN(\fpu_add_ctl/n97 ) );
DFFX1 \fpu_add_ctl/i_a3stg_opdec/q_reg[11] ( .D(\fpu_add_ctl/n645 ), .CLK(
rclk), .Q(n1029) );
DFFX1 \fpu_add_ctl/i_a3stg_opdec/q_reg[10] ( .D(\fpu_add_ctl/n646 ), .CLK(
rclk), .Q(n336) );
DFFX1 \fpu_add_ctl/i_a3stg_opdec/q_reg[9] ( .D(\fpu_add_ctl/n647 ), .CLK(
rclk), .Q(n1028) );
DFFX1 \fpu_add_ctl/i_a4stg_rnd_mode/q_reg[0] ( .D(\fpu_add_ctl/n649 ),
.CLK(rclk), .Q(\fpu_add_ctl/n307 ), .QN(n1084) );
DFFX1 \fpu_add_ctl/i_a4stg_rnd_mode/q_reg[1] ( .D(\fpu_add_ctl/n648 ),
.CLK(rclk), .Q(n291), .QN(\fpu_add_ctl/n937 ) );
DFFX1 \fpu_add_ctl/i_a3stg_opdec/q_reg[8] ( .D(\fpu_add_ctl/n650 ), .CLK(
rclk), .Q(n455), .QN(\fpu_add_ctl/n101 ) );
DFFX1 \fpu_add_ctl/i_a3stg_opdec/q_reg[7] ( .D(\fpu_add_ctl/n651 ), .CLK(
rclk), .Q(n895), .QN(\fpu_add_ctl/n102 ) );
DFFX1 \fpu_add_ctl/i_a3stg_opdec/q_reg[6] ( .D(\fpu_add_ctl/n652 ), .CLK(
rclk), .Q(n1027) );
DFFX1 \fpu_add_ctl/i_a3stg_opdec/q_reg[5] ( .D(\fpu_add_ctl/n653 ), .CLK(
rclk), .Q(n1026) );
DFFX1 \fpu_add_ctl/i_a3stg_opdec/q_reg[4] ( .D(\fpu_add_ctl/n654 ), .CLK(
rclk), .Q(n1025) );
DFFX1 \fpu_add_ctl/i_a3stg_opdec/q_reg[3] ( .D(\fpu_add_ctl/n655 ), .CLK(
rclk), .Q(\fpu_add_ctl/a3stg_opdec_9_0[3] ), .QN(a3stg_fdtos_inv) );
DFFX1 \fpu_add_ctl/i_a3stg_opdec/q_reg[2] ( .D(\fpu_add_ctl/n656 ), .CLK(
rclk), .Q(n1024) );
DFFX1 \fpu_add_ctl/i_a3stg_opdec/q_reg[1] ( .D(\fpu_add_ctl/n657 ), .CLK(
rclk), .Q(n573) );
DFFX1 \fpu_add_ctl/i_a3stg_opdec/q_reg[0] ( .D(\fpu_add_ctl/n658 ), .CLK(
rclk), .Q(n572) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[20] ( .D(\fpu_add_ctl/n671 ), .CLK(
rclk), .Q(n547), .QN(\fpu_add_ctl/n109 ) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[21] ( .D(\fpu_add_ctl/n670 ), .CLK(
rclk), .Q(n1008), .QN(\fpu_add_ctl/n110 ) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[8] ( .D(\fpu_add_ctl/n682 ), .CLK(
rclk), .Q(n858) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[22] ( .D(\fpu_add_ctl/n669 ), .CLK(
rclk), .Q(n356) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[28] ( .D(\fpu_add_ctl/n661 ), .CLK(
rclk), .Q(n1201), .QN(\fpu_add_ctl/n113 ) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[30] ( .D(\fpu_add_ctl/n659 ), .CLK(
rclk), .Q(n1023) );
DFFX1 \fpu_add_ctl/i_a1stg_dblop/q_reg[0] ( .D(\fpu_add_ctl/n689 ), .CLK(
rclk), .Q(n295) );
DFFX1 \fpu_add_ctl/i_a1stg_sngop/q_reg[0] ( .D(\fpu_add_ctl/n601 ), .CLK(
rclk), .Q(n662), .QN(\fpu_add_ctl/n116 ) );
DFFX1 \fpu_add_ctl/i_a1stg_in2_exp_neq_ffs/q_reg[0] ( .D(\fpu_add_ctl/n600 ), .CLK(rclk), .Q(\fpu_add_ctl/n317 ), .QN(n338) );
DFFX1 \fpu_add_ctl/i_a1stg_in2_exp_eq_0/q_reg[0] ( .D(\fpu_add_ctl/n599 ),
.CLK(rclk), .Q(n1086), .QN(\fpu_add_ctl/n117 ) );
DFFX1 \fpu_add_ctl/i_a1stg_in2_53_32_neq_0/q_reg[0] ( .D(\fpu_add_ctl/n598 ), .CLK(rclk), .Q(n730), .QN(\fpu_add_ctl/n118 ) );
DFFX1 \fpu_add_ctl/i_a1stg_in2_50_0_neq_0/q_reg[0] ( .D(\fpu_add_ctl/n597 ),
.CLK(rclk), .Q(n731), .QN(\fpu_add_ctl/n119 ) );
DFFX1 \fpu_add_ctl/i_a1stg_in2_63/q_reg[0] ( .D(\fpu_add_ctl/n596 ), .CLK(
rclk), .Q(n649), .QN(\fpu_add_ctl/n940 ) );
DFFX1 \fpu_add_ctl/i_a1stg_in2_54/q_reg[0] ( .D(\fpu_add_ctl/n595 ), .CLK(
rclk), .Q(n847), .QN(\fpu_add_ctl/n333 ) );
DFFX1 \fpu_add_ctl/i_a1stg_in2_51/q_reg[0] ( .D(\fpu_add_ctl/n594 ), .CLK(
rclk), .Q(n460), .QN(\fpu_add_ctl/n121 ) );
DFFX1 \fpu_add_ctl/i_a1stg_in1_exp_neq_ffs/q_reg[0] ( .D(\fpu_add_ctl/n593 ), .CLK(rclk), .Q(n598), .QN(\fpu_add_ctl/n324 ) );
DFFX1 \fpu_add_ctl/i_a1stg_in1_exp_eq_0/q_reg[0] ( .D(\fpu_add_ctl/n592 ),
.CLK(rclk), .Q(n1085), .QN(\fpu_add_ctl/n122 ) );
DFFX1 \fpu_add_ctl/i_a1stg_in1_53_32_neq_0/q_reg[0] ( .D(\fpu_add_ctl/n591 ), .CLK(rclk), .Q(n743), .QN(\fpu_add_ctl/n123 ) );
DFFX1 \fpu_add_ctl/i_a1stg_in1_50_0_neq_0/q_reg[0] ( .D(\fpu_add_ctl/n590 ),
.CLK(rclk), .Q(n744), .QN(\fpu_add_ctl/n124 ) );
DFFX1 \fpu_add_ctl/i_a1stg_in1_63/q_reg[0] ( .D(\fpu_add_ctl/n589 ), .CLK(
rclk), .Q(n897), .QN(\fpu_add_ctl/n125 ) );
DFFX1 \fpu_add_ctl/i_a1stg_in1_54/q_reg[0] ( .D(\fpu_add_ctl/n588 ), .CLK(
rclk), .Q(n1120), .QN(\fpu_add_ctl/n332 ) );
DFFX1 \fpu_add_ctl/i_a1stg_in1_51/q_reg[0] ( .D(\fpu_add_ctl/n587 ), .CLK(
rclk), .Q(n1119), .QN(\fpu_add_ctl/n127 ) );
DFFSSRX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[3] ( .D(a1stg_fdtos), .RSTB(
\fpu_add_ctl/n47 ), .SETB(\fpu_add_ctl/n426 ), .CLK(rclk), .Q(n91),
.QN(\fpu_add_ctl/n336 ) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[6] ( .D(\fpu_add_ctl/n684 ), .CLK(
rclk), .Q(n571) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[13] ( .D(\fpu_add_ctl/n677 ), .CLK(
rclk), .Q(n128), .QN(\fpu_add_ctl/n129 ) );
DFFSSRX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[19] ( .D(a1stg_fsdtoix), .RSTB(
\fpu_add_ctl/n47 ), .SETB(\fpu_add_ctl/n416 ), .CLK(rclk), .Q(
\fpu_add_ctl/n329 ), .QN(\fpu_add_ctl/n252 ) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[26] ( .D(\fpu_add_ctl/n663 ), .CLK(
rclk), .Q(n506), .QN(\fpu_add_ctl/n130 ) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[29] ( .D(\fpu_add_ctl/n660 ), .CLK(
rclk), .Q(n651) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[14] ( .D(\fpu_add_ctl/n676 ), .CLK(
rclk), .Q(n1076) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[15] ( .D(\fpu_add_ctl/n675 ), .CLK(
rclk), .Q(n553), .QN(\fpu_add_ctl/n133 ) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[16] ( .D(\fpu_add_ctl/n674 ), .CLK(
rclk), .Q(n569) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[17] ( .D(\fpu_add_ctl/n673 ), .CLK(
rclk), .Q(n1022) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[4] ( .D(\fpu_add_ctl/n685 ), .CLK(
rclk), .Q(n570) );
DFFSSRX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[5] ( .D(\fpu_add_ctl/n47 ),
.RSTB(a1stg_faddsubs), .SETB(\fpu_add_ctl/n425 ), .CLK(rclk), .Q(n562)
);
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[27] ( .D(\fpu_add_ctl/n662 ), .CLK(
rclk), .Q(n1200), .QN(\fpu_add_ctl/n138 ) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[23] ( .D(\fpu_add_ctl/n668 ), .CLK(
rclk), .Q(n1187), .QN(\fpu_add_ctl/n139 ) );
DFFX1 \fpu_add_ctl/i_a3stg_faddsubopa/q_reg[0] ( .D(\fpu_add_ctl/n666 ),
.CLK(rclk), .Q(n1233), .QN(\fpu_add_ctl/n140 ) );
DFFX1 \fpu_add_ctl/i_a3stg_faddsubopa/q_reg[1] ( .D(\fpu_add_ctl/n665 ),
.CLK(rclk), .Q(n1218), .QN(\fpu_add_ctl/n141 ) );
DFFX1 \fpu_add_ctl/i_a3stg_opdec/q_reg[12] ( .D(\fpu_add_ctl/n644 ), .CLK(
rclk), .Q(n133), .QN(\fpu_add_ctl/n142 ) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[24] ( .D(\fpu_add_ctl/n667 ), .CLK(
rclk), .Q(n640), .QN(\fpu_add_ctl/n938 ) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[9] ( .D(\fpu_add_ctl/n681 ), .CLK(
rclk), .Q(n511), .QN(\fpu_add_ctl/n143 ) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[25] ( .D(\fpu_add_ctl/n664 ), .CLK(
rclk), .Q(n1214), .QN(\fpu_add_ctl/n144 ) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[1] ( .D(\fpu_add_ctl/n687 ), .CLK(
rclk), .Q(n1001) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[10] ( .D(\fpu_add_ctl/n680 ), .CLK(
rclk), .Q(n757) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[12] ( .D(\fpu_add_ctl/n678 ), .CLK(
rclk), .Q(n421), .QN(\fpu_add_ctl/n147 ) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[18] ( .D(\fpu_add_ctl/n672 ), .CLK(
rclk), .Q(n258) );
DFFX1 \fpu_add_ctl/i_a1stg_op/q_reg[7] ( .D(\fpu_add_ctl/n752 ), .CLK(rclk),
.Q(\fpu_add_ctl/n314 ), .QN(n172) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[2] ( .D(\fpu_add_ctl/n686 ), .CLK(
rclk), .Q(n560) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[11] ( .D(\fpu_add_ctl/n679 ), .CLK(
rclk), .Q(n718), .QN(\fpu_add_ctl/n150 ) );
DFFX1 \fpu_add_ctl/i_a1stg_op/q_reg[6] ( .D(\fpu_add_ctl/n751 ), .CLK(rclk),
.Q(\fpu_add_ctl/n312 ), .QN(n254) );
DFFX1 \fpu_add_ctl/i_a1stg_op/q_reg[5] ( .D(\fpu_add_ctl/n750 ), .CLK(rclk),
.Q(n84) );
DFFX1 \fpu_add_ctl/i_a1stg_op/q_reg[4] ( .D(\fpu_add_ctl/n749 ), .CLK(rclk),
.Q(n585), .QN(\fpu_add_ctl/n303 ) );
DFFX1 \fpu_add_ctl/i_a1stg_op/q_reg[3] ( .D(\fpu_add_ctl/n748 ), .CLK(rclk),
.Q(n595), .QN(\fpu_add_ctl/n321 ) );
DFFX1 \fpu_add_ctl/i_a1stg_op/q_reg[2] ( .D(\fpu_add_ctl/n747 ), .CLK(rclk),
.Q(n18), .QN(\fpu_add_ctl/n318 ) );
DFFX1 \fpu_add_ctl/i_a1stg_op/q_reg[1] ( .D(\fpu_add_ctl/n746 ), .CLK(rclk),
.Q(n829), .QN(\fpu_add_ctl/n936 ) );
DFFX1 \fpu_add_ctl/i_a1stg_op/q_reg[0] ( .D(\fpu_add_ctl/n745 ), .CLK(rclk),
.Q(\fpu_add_ctl/n320 ), .QN(n158) );
DFFX1 \fpu_add_ctl/i_a4stg_fcc/q_reg[1] ( .D(\fpu_add_ctl/n737 ), .CLK(rclk), .Q(n555) );
DFFX1 \fpu_add_ctl/i_a3stg_fcc/q_reg[1] ( .D(\fpu_add_ctl/n739 ), .CLK(rclk), .Q(n1013) );
DFFX1 \fpu_add_ctl/i_a2stg_fcc/q_reg[1] ( .D(\fpu_add_ctl/n741 ), .CLK(rclk), .Q(n564) );
DFFX1 \fpu_add_ctl/i_a1stg_fcc/q_reg[1] ( .D(\fpu_add_ctl/n744 ), .CLK(rclk), .Q(n1011) );
DFFX1 \fpu_add_ctl/i_a4stg_fcc/q_reg[0] ( .D(\fpu_add_ctl/n738 ), .CLK(rclk), .Q(n554) );
DFFX1 \fpu_add_ctl/i_a3stg_fcc/q_reg[0] ( .D(\fpu_add_ctl/n740 ), .CLK(rclk), .Q(n1012) );
DFFX1 \fpu_add_ctl/i_a2stg_fcc/q_reg[0] ( .D(\fpu_add_ctl/n742 ), .CLK(rclk), .Q(n563) );
DFFX1 \fpu_add_ctl/i_a1stg_fcc/q_reg[0] ( .D(\fpu_add_ctl/n743 ), .CLK(rclk), .Q(n1010) );
DFFX1 \fpu_add_ctl/i_a5stg_id/q_reg[6] ( .D(\fpu_add_ctl/n705 ), .CLK(rclk),
.Q(n888) );
DFFX1 \fpu_add_ctl/i_a4stg_id/q_reg[6] ( .D(\fpu_add_ctl/n715 ), .CLK(rclk),
.Q(n350) );
DFFX1 \fpu_add_ctl/i_a5stg_id/q_reg[7] ( .D(\fpu_add_ctl/n704 ), .CLK(rclk),
.Q(n887) );
DFFX1 \fpu_add_ctl/i_a4stg_id/q_reg[7] ( .D(\fpu_add_ctl/n714 ), .CLK(rclk),
.Q(n349) );
DFFX1 \fpu_add_ctl/i_a5stg_id/q_reg[8] ( .D(\fpu_add_ctl/n703 ), .CLK(rclk),
.Q(n886) );
DFFX1 \fpu_add_ctl/i_a4stg_id/q_reg[8] ( .D(\fpu_add_ctl/n713 ), .CLK(rclk),
.Q(n348) );
DFFX1 \fpu_add_ctl/i_a5stg_id/q_reg[9] ( .D(\fpu_add_ctl/n702 ), .CLK(rclk),
.Q(n885) );
DFFX1 \fpu_add_ctl/i_a4stg_id/q_reg[9] ( .D(\fpu_add_ctl/n712 ), .CLK(rclk),
.Q(n347) );
DFFX1 \fpu_add_ctl/i_a5stg_id/q_reg[2] ( .D(\fpu_add_ctl/n709 ), .CLK(rclk),
.Q(n892) );
DFFX1 \fpu_add_ctl/i_a4stg_id/q_reg[2] ( .D(\fpu_add_ctl/n719 ), .CLK(rclk),
.Q(n354) );
DFFX1 \fpu_add_ctl/i_a5stg_id/q_reg[3] ( .D(\fpu_add_ctl/n708 ), .CLK(rclk),
.Q(n891) );
DFFX1 \fpu_add_ctl/i_a4stg_id/q_reg[3] ( .D(\fpu_add_ctl/n718 ), .CLK(rclk),
.Q(n353) );
DFFX1 \fpu_add_ctl/i_a5stg_id/q_reg[4] ( .D(\fpu_add_ctl/n707 ), .CLK(rclk),
.Q(n890) );
DFFX1 \fpu_add_ctl/i_a4stg_id/q_reg[4] ( .D(\fpu_add_ctl/n717 ), .CLK(rclk),
.Q(n352) );
DFFX1 \fpu_add_ctl/i_a5stg_id/q_reg[5] ( .D(\fpu_add_ctl/n706 ), .CLK(rclk),
.Q(n889) );
DFFX1 \fpu_add_ctl/i_a4stg_id/q_reg[5] ( .D(\fpu_add_ctl/n716 ), .CLK(rclk),
.Q(n351) );
DFFX1 \fpu_add_ctl/i_a3stg_id/q_reg[4] ( .D(\fpu_add_ctl/n722 ), .CLK(rclk),
.Q(n89), .QN(\fpu_add_ctl/n177 ) );
DFFX1 \fpu_add_ctl/i_a2stg_id/q_reg[4] ( .D(\fpu_add_ctl/n727 ), .CLK(rclk),
.Q(n1017) );
DFFX1 \fpu_add_ctl/i_a1stg_id/q_reg[4] ( .D(\fpu_add_ctl/n736 ), .CLK(rclk),
.Q(n566) );
DFFX1 \fpu_add_ctl/i_a3stg_id/q_reg[3] ( .D(\fpu_add_ctl/n723 ), .CLK(rclk),
.Q(n269), .QN(\fpu_add_ctl/n308 ) );
DFFX1 \fpu_add_ctl/i_a2stg_id/q_reg[3] ( .D(\fpu_add_ctl/n728 ), .CLK(rclk),
.Q(n1016) );
DFFX1 \fpu_add_ctl/i_a1stg_id/q_reg[3] ( .D(\fpu_add_ctl/n735 ), .CLK(rclk),
.Q(n565) );
DFFX1 \fpu_add_ctl/i_a3stg_id/q_reg[2] ( .D(\fpu_add_ctl/n724 ), .CLK(rclk),
.Q(\fpu_add_ctl/a3stg_id[2] ), .QN(\fpu_add_ctl/n326 ) );
DFFX1 \fpu_add_ctl/i_a2stg_id/q_reg[2] ( .D(\fpu_add_ctl/n729 ), .CLK(rclk),
.Q(\fpu_add_ctl/a2stg_id[2] ), .QN(\fpu_add_ctl/n182 ) );
DFFX1 \fpu_add_ctl/i_a1stg_id/q_reg[2] ( .D(\fpu_add_ctl/n734 ), .CLK(rclk),
.Q(n1216), .QN(\fpu_add_ctl/n183 ) );
DFFX1 \fpu_add_ctl/i_a5stg_id/q_reg[1] ( .D(\fpu_add_ctl/n710 ), .CLK(rclk),
.Q(n893) );
DFFX1 \fpu_add_ctl/i_a4stg_id/q_reg[1] ( .D(\fpu_add_ctl/n720 ), .CLK(rclk),
.Q(n341) );
DFFX1 \fpu_add_ctl/i_a3stg_id/q_reg[1] ( .D(\fpu_add_ctl/n725 ), .CLK(rclk),
.Q(n1019) );
DFFX1 \fpu_add_ctl/i_a2stg_id/q_reg[1] ( .D(\fpu_add_ctl/n730 ), .CLK(rclk),
.Q(n568) );
DFFX1 \fpu_add_ctl/i_a1stg_id/q_reg[1] ( .D(\fpu_add_ctl/n733 ), .CLK(rclk),
.Q(n1015) );
DFFX1 \fpu_add_ctl/i_a5stg_id/q_reg[0] ( .D(\fpu_add_ctl/n711 ), .CLK(rclk),
.Q(n894) );
DFFX1 \fpu_add_ctl/i_a4stg_id/q_reg[0] ( .D(\fpu_add_ctl/n721 ), .CLK(rclk),
.Q(n342) );
DFFX1 \fpu_add_ctl/i_a3stg_id/q_reg[0] ( .D(\fpu_add_ctl/n726 ), .CLK(rclk),
.Q(n1018) );
DFFX1 \fpu_add_ctl/i_a2stg_id/q_reg[0] ( .D(\fpu_add_ctl/n731 ), .CLK(rclk),
.Q(n567) );
DFFX1 \fpu_add_ctl/i_a1stg_id/q_reg[0] ( .D(\fpu_add_ctl/n732 ), .CLK(rclk),
.Q(n1014) );
DFFX1 \fpu_add_ctl/i_a4stg_rnd_mode2/q_reg[1] ( .D(\fpu_add_ctl/n694 ),
.CLK(rclk), .Q(n883) );
DFFX1 \fpu_add_ctl/i_a3stg_rnd_mode/q_reg[1] ( .D(\fpu_add_ctl/n696 ),
.CLK(rclk), .Q(n147) );
DFFX1 \fpu_add_ctl/i_a2stg_rnd_mode/q_reg[1] ( .D(\fpu_add_ctl/n698 ),
.CLK(rclk), .Q(n504), .QN(\fpu_add_ctl/n196 ) );
DFFX1 \fpu_add_ctl/i_a1stg_rnd_mode/q_reg[1] ( .D(\fpu_add_ctl/n701 ),
.CLK(rclk), .Q(n1021) );
DFFX1 \fpu_add_ctl/i_a4stg_rnd_mode2/q_reg[0] ( .D(\fpu_add_ctl/n695 ),
.CLK(rclk), .Q(n882) );
DFFX1 \fpu_add_ctl/i_a3stg_rnd_mode/q_reg[0] ( .D(\fpu_add_ctl/n697 ),
.CLK(rclk), .Q(n146) );
DFFX1 \fpu_add_ctl/i_a2stg_rnd_mode/q_reg[0] ( .D(\fpu_add_ctl/n699 ),
.CLK(rclk), .Q(n505), .QN(\fpu_add_ctl/n200 ) );
DFFX1 \fpu_add_ctl/i_a1stg_rnd_mode/q_reg[0] ( .D(\fpu_add_ctl/n700 ),
.CLK(rclk), .Q(n1020) );
DFFX1 \fpu_add_ctl/i_a1stg_dblopa/q_reg[3] ( .D(\fpu_add_ctl/n693 ), .CLK(
rclk), .Q(n915), .QN(\fpu_add_ctl/n202 ) );
DFFX1 \fpu_add_ctl/i_a1stg_dblopa/q_reg[2] ( .D(\fpu_add_ctl/n692 ), .CLK(
rclk), .Q(n325), .QN(\fpu_add_ctl/n309 ) );
DFFX1 \fpu_add_ctl/i_a1stg_dblopa/q_reg[1] ( .D(\fpu_add_ctl/n691 ), .CLK(
rclk), .Q(n44), .QN(\fpu_add_ctl/n203 ) );
DFFX1 \fpu_add_ctl/i_a1stg_dblopa/q_reg[0] ( .D(\fpu_add_ctl/n690 ), .CLK(
rclk), .Q(n700), .QN(\fpu_add_ctl/n327 ) );
DFFX1 \fpu_add_ctl/i_a1stg_sngopa/q_reg[3] ( .D(\fpu_add_ctl/n605 ), .CLK(
rclk), .Q(n129) );
DFFX1 \fpu_add_ctl/i_a1stg_sngopa/q_reg[2] ( .D(\fpu_add_ctl/n604 ), .CLK(
rclk), .Q(n692), .QN(\fpu_add_ctl/n330 ) );
DFFX1 \fpu_add_ctl/i_a1stg_sngopa/q_reg[1] ( .D(\fpu_add_ctl/n603 ), .CLK(
rclk), .Q(n102), .QN(\fpu_add_ctl/n205 ) );
DFFX1 \fpu_add_ctl/i_a1stg_sngopa/q_reg[0] ( .D(\fpu_add_ctl/n602 ), .CLK(
rclk), .Q(n701), .QN(\fpu_add_ctl/n328 ) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[7] ( .D(\fpu_add_ctl/n683 ), .CLK(
rclk), .Q(n355) );
DFFX1 \fpu_add_ctl/i_a2stg_opdec/q_reg[0] ( .D(\fpu_add_ctl/n688 ), .CLK(
rclk), .Q(n849), .QN(\fpu_add_ctl/n207 ) );
DFFSSRX1 \fpu_add_ctl/i_a6stg_opdec/q_reg[5] ( .D(\fpu_add_ctl/n49 ),
.RSTB(\fpu_add_ctl/n441 ), .SETB(n586), .CLK(rclk), .QN(
\fpu_add_ctl/n269 ) );
DFFARX1 \fpu_add_ctl/dffrl_add_ctl/q_reg[0] ( .D(
\fpu_add_ctl/dffrl_add_ctl/N4 ), .CLK(rclk), .RSTB(arst_l), .Q(
\fpu_add_ctl/add_ctl_rst_l ), .QN(\fpu_add_ctl/n210 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out4/q_reg[10] ( .D(\fpu_add_exp_dp/n507 ),
.CLK(n1566), .Q(n1238), .QN(\fpu_add_exp_dp/n1 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out4/q_reg[9] ( .D(\fpu_add_exp_dp/n508 ),
.CLK(n1566), .Q(n1232), .QN(\fpu_add_exp_dp/n2 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out4/q_reg[8] ( .D(\fpu_add_exp_dp/n509 ),
.CLK(n1566), .Q(n1231), .QN(\fpu_add_exp_dp/n3 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out4/q_reg[7] ( .D(\fpu_add_exp_dp/n510 ),
.CLK(n1566), .Q(n1230), .QN(\fpu_add_exp_dp/n4 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out4/q_reg[6] ( .D(\fpu_add_exp_dp/n511 ),
.CLK(n1566), .Q(n1229), .QN(\fpu_add_exp_dp/n5 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out4/q_reg[5] ( .D(\fpu_add_exp_dp/n512 ),
.CLK(n1566), .Q(n1228), .QN(\fpu_add_exp_dp/n6 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out4/q_reg[4] ( .D(\fpu_add_exp_dp/n513 ),
.CLK(n1566), .Q(n1227), .QN(\fpu_add_exp_dp/n7 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out4/q_reg[3] ( .D(\fpu_add_exp_dp/n514 ),
.CLK(n1566), .Q(n1226), .QN(\fpu_add_exp_dp/n8 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out4/q_reg[2] ( .D(\fpu_add_exp_dp/n515 ),
.CLK(n1566), .Q(n1225), .QN(\fpu_add_exp_dp/n9 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out4/q_reg[1] ( .D(\fpu_add_exp_dp/n516 ),
.CLK(n1566), .Q(n1237), .QN(\fpu_add_exp_dp/n10 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out4/q_reg[0] ( .D(\fpu_add_exp_dp/n517 ),
.CLK(n1565), .Q(n1236), .QN(\fpu_add_exp_dp/n11 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out3/q_reg[10] ( .D(\fpu_add_exp_dp/n518 ),
.CLK(\fpu_add_exp_dp/n448 ), .Q(\fpu_add_exp_dp/add_exp_out3[10] ),
.QN(\fpu_add_exp_dp/n12 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out3/q_reg[9] ( .D(\fpu_add_exp_dp/n519 ),
.CLK(\fpu_add_exp_dp/n448 ), .Q(\fpu_add_exp_dp/add_exp_out3[9] ),
.QN(\fpu_add_exp_dp/n13 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out3/q_reg[8] ( .D(\fpu_add_exp_dp/n520 ),
.CLK(\fpu_add_exp_dp/n448 ), .Q(\fpu_add_exp_dp/add_exp_out3[8] ),
.QN(\fpu_add_exp_dp/n14 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out3/q_reg[7] ( .D(\fpu_add_exp_dp/n521 ),
.CLK(n1585), .Q(\fpu_add_exp_dp/add_exp_out3[7] ), .QN(
\fpu_add_exp_dp/n15 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out3/q_reg[6] ( .D(\fpu_add_exp_dp/n522 ),
.CLK(\fpu_add_exp_dp/n448 ), .Q(\fpu_add_exp_dp/add_exp_out3[6] ),
.QN(\fpu_add_exp_dp/n16 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out3/q_reg[5] ( .D(\fpu_add_exp_dp/n523 ),
.CLK(n1585), .Q(\fpu_add_exp_dp/add_exp_out3[5] ), .QN(
\fpu_add_exp_dp/n17 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out3/q_reg[4] ( .D(\fpu_add_exp_dp/n524 ),
.CLK(\fpu_add_exp_dp/n448 ), .Q(\fpu_add_exp_dp/add_exp_out3[4] ),
.QN(\fpu_add_exp_dp/n18 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out3/q_reg[3] ( .D(\fpu_add_exp_dp/n525 ),
.CLK(n1567), .Q(\fpu_add_exp_dp/add_exp_out3[3] ), .QN(
\fpu_add_exp_dp/n19 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out3/q_reg[2] ( .D(\fpu_add_exp_dp/n526 ),
.CLK(n1585), .Q(\fpu_add_exp_dp/add_exp_out3[2] ), .QN(
\fpu_add_exp_dp/n20 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out3/q_reg[1] ( .D(\fpu_add_exp_dp/n527 ),
.CLK(n1567), .Q(\fpu_add_exp_dp/add_exp_out3[1] ), .QN(
\fpu_add_exp_dp/n21 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out3/q_reg[0] ( .D(\fpu_add_exp_dp/n528 ),
.CLK(n1567), .Q(\fpu_add_exp_dp/add_exp_out3[0] ), .QN(
\fpu_add_exp_dp/n22 ) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out2/q_reg[10] ( .D(\fpu_add_exp_dp/n529 ),
.CLK(n1565), .Q(n443) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out2/q_reg[9] ( .D(\fpu_add_exp_dp/n530 ),
.CLK(n1565), .Q(n441) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out2/q_reg[8] ( .D(\fpu_add_exp_dp/n531 ),
.CLK(n1565), .Q(n442) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out2/q_reg[7] ( .D(\fpu_add_exp_dp/n532 ),
.CLK(n1565), .Q(n732) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out2/q_reg[6] ( .D(\fpu_add_exp_dp/n533 ),
.CLK(n1565), .Q(n733) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out2/q_reg[5] ( .D(\fpu_add_exp_dp/n534 ),
.CLK(n1565), .Q(n734) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out2/q_reg[4] ( .D(\fpu_add_exp_dp/n535 ),
.CLK(n1565), .Q(n735) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out2/q_reg[3] ( .D(\fpu_add_exp_dp/n536 ),
.CLK(n1565), .Q(n736) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out2/q_reg[2] ( .D(\fpu_add_exp_dp/n537 ),
.CLK(n1565), .Q(n737) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out2/q_reg[1] ( .D(\fpu_add_exp_dp/n538 ),
.CLK(n1565), .Q(n738) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out2/q_reg[0] ( .D(\fpu_add_exp_dp/n539 ),
.CLK(n1565), .Q(n764) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out1/q_reg[10] ( .D(\fpu_add_exp_dp/n540 ),
.CLK(n1567), .Q(n760) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out1/q_reg[9] ( .D(\fpu_add_exp_dp/n541 ),
.CLK(n1567), .Q(n758) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out1/q_reg[8] ( .D(\fpu_add_exp_dp/n542 ),
.CLK(n1567), .Q(n759) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out1/q_reg[7] ( .D(\fpu_add_exp_dp/n543 ),
.CLK(n1567), .Q(n434) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out1/q_reg[6] ( .D(\fpu_add_exp_dp/n544 ),
.CLK(n1567), .Q(n435) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out1/q_reg[5] ( .D(\fpu_add_exp_dp/n545 ),
.CLK(n1567), .Q(n436) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out1/q_reg[4] ( .D(\fpu_add_exp_dp/n546 ),
.CLK(n1567), .Q(n437) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out1/q_reg[3] ( .D(\fpu_add_exp_dp/n547 ),
.CLK(n1567), .Q(n438) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out1/q_reg[2] ( .D(\fpu_add_exp_dp/n548 ),
.CLK(n1567), .Q(n439) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out1/q_reg[1] ( .D(\fpu_add_exp_dp/n549 ),
.CLK(n1566), .Q(n440) );
DFFX1 \fpu_add_exp_dp/i_add_exp_out1/q_reg[0] ( .D(\fpu_add_exp_dp/n550 ),
.CLK(n1566), .Q(n454) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp2/q_reg[11] ( .D(\fpu_add_exp_dp/n552 ),
.CLK(n1572), .Q(\fpu_add_exp_dp/a4stg_exp2[11] ), .QN(
\fpu_add_exp_dp/n46 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp2/q_reg[10] ( .D(\fpu_add_exp_dp/n553 ),
.CLK(n1573), .Q(n663), .QN(\fpu_add_exp_dp/n451 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp2/q_reg[9] ( .D(\fpu_add_exp_dp/n554 ),
.CLK(n1572), .Q(\fpu_add_exp_dp/a4stg_exp2[9] ), .QN(
\fpu_add_exp_dp/n48 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp2/q_reg[8] ( .D(\fpu_add_exp_dp/n555 ),
.CLK(n1572), .Q(\fpu_add_exp_dp/a4stg_exp2[8] ), .QN(
\fpu_add_exp_dp/n450 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp2/q_reg[7] ( .D(\fpu_add_exp_dp/n556 ),
.CLK(n1572), .Q(\fpu_add_exp_dp/a4stg_exp2[7] ), .QN(
\fpu_add_exp_dp/n50 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp2/q_reg[6] ( .D(\fpu_add_exp_dp/n557 ),
.CLK(n1573), .Q(n666), .QN(\fpu_add_exp_dp/n452 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp2/q_reg[5] ( .D(\fpu_add_exp_dp/n558 ),
.CLK(n1572), .Q(n761), .QN(\fpu_add_exp_dp/n441 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp2/q_reg[4] ( .D(\fpu_add_exp_dp/n559 ),
.CLK(n1571), .Q(\fpu_add_exp_dp/a4stg_exp2[4] ), .QN(
\fpu_add_exp_dp/n440 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp2/q_reg[3] ( .D(\fpu_add_exp_dp/n560 ),
.CLK(n1571), .Q(\fpu_add_exp_dp/a4stg_exp2[3] ), .QN(
\fpu_add_exp_dp/n439 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp2/q_reg[2] ( .D(\fpu_add_exp_dp/n561 ),
.CLK(n1571), .Q(\fpu_add_exp_dp/a4stg_exp2[2] ), .QN(
\fpu_add_exp_dp/n438 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp2/q_reg[1] ( .D(\fpu_add_exp_dp/n562 ),
.CLK(n1572), .Q(n643), .QN(\fpu_add_exp_dp/n437 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp2/q_reg[0] ( .D(\fpu_add_exp_dp/n563 ),
.CLK(n1571), .Q(\fpu_add_exp_dp/a4stg_exp2[0] ), .QN(
\fpu_add_exp_dp/n57 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre2/q_reg[11] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre2/N14 ), .CLK(n1568), .Q(
\fpu_add_exp_dp/a4stg_exp_pre2[11] ), .QN(\fpu_add_exp_dp/n60 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre4/q_reg[11] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N14 ), .CLK(n1570), .Q(
\fpu_add_exp_dp/a4stg_exp_pre4[11] ), .QN(\fpu_add_exp_dp/n61 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre2/q_reg[10] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre2/N13 ), .CLK(n1568), .Q(
\fpu_add_exp_dp/a4stg_exp_pre2[10] ), .QN(\fpu_add_exp_dp/n62 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre4/q_reg[10] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N13 ), .CLK(n1570), .Q(
\fpu_add_exp_dp/a4stg_exp_pre4[10] ), .QN(\fpu_add_exp_dp/n63 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre2/q_reg[9] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre2/N12 ), .CLK(n1568), .Q(
\fpu_add_exp_dp/a4stg_exp_pre2[9] ), .QN(\fpu_add_exp_dp/n64 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre4/q_reg[9] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N12 ), .CLK(n1570), .Q(
\fpu_add_exp_dp/a4stg_exp_pre4[9] ), .QN(\fpu_add_exp_dp/n65 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre2/q_reg[8] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre2/N11 ), .CLK(n1568), .Q(
\fpu_add_exp_dp/a4stg_exp_pre2[8] ), .QN(\fpu_add_exp_dp/n66 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre4/q_reg[8] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N11 ), .CLK(n1570), .Q(
\fpu_add_exp_dp/a4stg_exp_pre4[8] ), .QN(\fpu_add_exp_dp/n67 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre2/q_reg[7] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre2/N10 ), .CLK(n1568), .Q(
\fpu_add_exp_dp/a4stg_exp_pre2[7] ), .QN(\fpu_add_exp_dp/n68 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre4/q_reg[7] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N10 ), .CLK(n1570), .Q(
\fpu_add_exp_dp/a4stg_exp_pre4[7] ), .QN(\fpu_add_exp_dp/n69 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre2/q_reg[6] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre2/N9 ), .CLK(\fpu_add_exp_dp/n448 ),
.Q(\fpu_add_exp_dp/a4stg_exp_pre2[6] ), .QN(\fpu_add_exp_dp/n70 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre4/q_reg[6] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N9 ), .CLK(n1569), .Q(
\fpu_add_exp_dp/a4stg_exp_pre4[6] ), .QN(\fpu_add_exp_dp/n71 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre2/q_reg[5] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre2/N8 ), .CLK(\fpu_add_exp_dp/n448 ),
.Q(\fpu_add_exp_dp/a4stg_exp_pre2[5] ), .QN(\fpu_add_exp_dp/n72 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre4/q_reg[5] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N8 ), .CLK(n1569), .Q(
\fpu_add_exp_dp/a4stg_exp_pre4[5] ), .QN(\fpu_add_exp_dp/n73 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre2/q_reg[4] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre2/N7 ), .CLK(\fpu_add_exp_dp/n448 ),
.Q(\fpu_add_exp_dp/a4stg_exp_pre2[4] ), .QN(\fpu_add_exp_dp/n74 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre4/q_reg[4] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N7 ), .CLK(n1569), .Q(
\fpu_add_exp_dp/a4stg_exp_pre4[4] ), .QN(\fpu_add_exp_dp/n75 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre2/q_reg[3] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre2/N6 ), .CLK(\fpu_add_exp_dp/n448 ),
.Q(\fpu_add_exp_dp/a4stg_exp_pre2[3] ), .QN(\fpu_add_exp_dp/n76 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre4/q_reg[3] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N6 ), .CLK(n1569), .Q(
\fpu_add_exp_dp/a4stg_exp_pre4[3] ), .QN(\fpu_add_exp_dp/n77 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre2/q_reg[2] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre2/N5 ), .CLK(n1568), .Q(
\fpu_add_exp_dp/a4stg_exp_pre2[2] ), .QN(\fpu_add_exp_dp/n78 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre4/q_reg[2] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N5 ), .CLK(n1570), .Q(
\fpu_add_exp_dp/a4stg_exp_pre4[2] ), .QN(\fpu_add_exp_dp/n79 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre2/q_reg[1] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre2/N4 ), .CLK(n1568), .Q(
\fpu_add_exp_dp/a4stg_exp_pre2[1] ), .QN(\fpu_add_exp_dp/n80 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre4/q_reg[1] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N4 ), .CLK(n1570), .Q(
\fpu_add_exp_dp/a4stg_exp_pre4[1] ), .QN(\fpu_add_exp_dp/n81 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre2/q_reg[0] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre2/N3 ), .CLK(n1568), .Q(
\fpu_add_exp_dp/a4stg_exp_pre2[0] ), .QN(\fpu_add_exp_dp/n82 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre4/q_reg[0] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N3 ), .CLK(n1570), .Q(
\fpu_add_exp_dp/a4stg_exp_pre4[0] ), .QN(\fpu_add_exp_dp/n83 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre3/q_reg[11] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N14 ), .CLK(n1569), .Q(
\fpu_add_exp_dp/a4stg_exp_pre3[11] ), .QN(\fpu_add_exp_dp/n85 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre3/q_reg[10] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N13 ), .CLK(n1569), .Q(
\fpu_add_exp_dp/a4stg_exp_pre3[10] ), .QN(\fpu_add_exp_dp/n86 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre3/q_reg[9] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N12 ), .CLK(n1569), .Q(
\fpu_add_exp_dp/a4stg_exp_pre3[9] ), .QN(\fpu_add_exp_dp/n87 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre3/q_reg[8] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N11 ), .CLK(n1569), .Q(
\fpu_add_exp_dp/a4stg_exp_pre3[8] ), .QN(\fpu_add_exp_dp/n88 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre3/q_reg[7] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N10 ), .CLK(n1569), .Q(
\fpu_add_exp_dp/a4stg_exp_pre3[7] ), .QN(\fpu_add_exp_dp/n89 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre3/q_reg[6] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N9 ), .CLK(n1568), .Q(
\fpu_add_exp_dp/a4stg_exp_pre3[6] ), .QN(\fpu_add_exp_dp/n90 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre3/q_reg[5] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N8 ), .CLK(n1568), .Q(
\fpu_add_exp_dp/a4stg_exp_pre3[5] ), .QN(\fpu_add_exp_dp/n91 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre3/q_reg[4] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N7 ), .CLK(n1568), .Q(
\fpu_add_exp_dp/a4stg_exp_pre3[4] ), .QN(\fpu_add_exp_dp/n92 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre3/q_reg[3] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N6 ), .CLK(n1568), .Q(
\fpu_add_exp_dp/a4stg_exp_pre3[3] ), .QN(\fpu_add_exp_dp/n93 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre3/q_reg[2] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N5 ), .CLK(n1569), .Q(
\fpu_add_exp_dp/a4stg_exp_pre3[2] ), .QN(\fpu_add_exp_dp/n94 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre3/q_reg[1] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N4 ), .CLK(n1569), .Q(
\fpu_add_exp_dp/a4stg_exp_pre3[1] ), .QN(\fpu_add_exp_dp/n95 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre3/q_reg[0] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N3 ), .CLK(n1569), .Q(
\fpu_add_exp_dp/a4stg_exp_pre3[0] ), .QN(\fpu_add_exp_dp/n96 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre1/q_reg[11] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N14 ), .CLK(n1571), .Q(
\fpu_add_exp_dp/a4stg_exp_pre1[11] ), .QN(\fpu_add_exp_dp/n98 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre1/q_reg[10] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N13 ), .CLK(n1571), .Q(
\fpu_add_exp_dp/a4stg_exp_pre1[10] ), .QN(\fpu_add_exp_dp/n99 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre1/q_reg[9] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N12 ), .CLK(n1571), .Q(
\fpu_add_exp_dp/a4stg_exp_pre1[9] ), .QN(\fpu_add_exp_dp/n100 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre1/q_reg[8] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N11 ), .CLK(n1571), .Q(
\fpu_add_exp_dp/a4stg_exp_pre1[8] ), .QN(\fpu_add_exp_dp/n101 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre1/q_reg[7] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N10 ), .CLK(n1571), .Q(
\fpu_add_exp_dp/a4stg_exp_pre1[7] ), .QN(\fpu_add_exp_dp/n102 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre1/q_reg[6] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N9 ), .CLK(n1570), .Q(
\fpu_add_exp_dp/a4stg_exp_pre1[6] ), .QN(\fpu_add_exp_dp/n103 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre1/q_reg[5] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N8 ), .CLK(n1570), .Q(
\fpu_add_exp_dp/a4stg_exp_pre1[5] ), .QN(\fpu_add_exp_dp/n104 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre1/q_reg[4] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N7 ), .CLK(n1570), .Q(
\fpu_add_exp_dp/a4stg_exp_pre1[4] ), .QN(\fpu_add_exp_dp/n105 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre1/q_reg[3] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N6 ), .CLK(n1570), .Q(
\fpu_add_exp_dp/a4stg_exp_pre1[3] ), .QN(\fpu_add_exp_dp/n106 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre1/q_reg[2] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N5 ), .CLK(n1571), .Q(
\fpu_add_exp_dp/a4stg_exp_pre1[2] ), .QN(\fpu_add_exp_dp/n107 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre1/q_reg[1] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N4 ), .CLK(n1571), .Q(
\fpu_add_exp_dp/a4stg_exp_pre1[1] ), .QN(\fpu_add_exp_dp/n108 ) );
DFFX1 \fpu_add_exp_dp/i_a4stg_exp_pre1/q_reg[0] ( .D(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N3 ), .CLK(n1571), .Q(
\fpu_add_exp_dp/a4stg_exp_pre1[0] ), .QN(\fpu_add_exp_dp/n109 ) );
DFFX1 \fpu_add_exp_dp/i_a3stg_exp/q_reg[11] ( .D(\fpu_add_exp_dp/n565 ),
.CLK(n1575), .Q(n728), .QN(\fpu_add_exp_dp/n447 ) );
DFFX1 \fpu_add_exp_dp/i_a3stg_exp/q_reg[10] ( .D(\fpu_add_exp_dp/n566 ),
.CLK(n1573), .Q(n181), .QN(\fpu_add_exp_dp/n446 ) );
DFFX1 \fpu_add_exp_dp/i_a3stg_exp/q_reg[9] ( .D(\fpu_add_exp_dp/n567 ),
.CLK(n1573), .Q(n17), .QN(\fpu_add_exp_dp/n443 ) );
DFFX1 \fpu_add_exp_dp/i_a3stg_exp/q_reg[8] ( .D(\fpu_add_exp_dp/n568 ),
.CLK(n1573), .Q(n71), .QN(\fpu_add_exp_dp/n445 ) );
DFFX1 \fpu_add_exp_dp/i_a3stg_exp/q_reg[7] ( .D(\fpu_add_exp_dp/n569 ),
.CLK(n1572), .Q(n256), .QN(\fpu_add_exp_dp/n442 ) );
DFFX1 \fpu_add_exp_dp/i_a3stg_exp/q_reg[6] ( .D(\fpu_add_exp_dp/n570 ),
.CLK(n1573), .Q(n160), .QN(\fpu_add_exp_dp/n435 ) );
DFFX1 \fpu_add_exp_dp/i_a3stg_exp/q_reg[5] ( .D(\fpu_add_exp_dp/n571 ),
.CLK(n1572), .Q(n69), .QN(\fpu_add_exp_dp/n433 ) );
DFFX1 \fpu_add_exp_dp/i_a3stg_exp/q_reg[4] ( .D(\fpu_add_exp_dp/n572 ),
.CLK(n1572), .Q(n67), .QN(\fpu_add_exp_dp/n432 ) );
DFFX1 \fpu_add_exp_dp/i_a3stg_exp/q_reg[3] ( .D(\fpu_add_exp_dp/n573 ),
.CLK(n1572), .Q(n178), .QN(\fpu_add_exp_dp/n434 ) );
DFFX1 \fpu_add_exp_dp/i_a3stg_exp/q_reg[2] ( .D(\fpu_add_exp_dp/n574 ),
.CLK(n1572), .Q(n159), .QN(\fpu_add_exp_dp/n431 ) );
DFFX1 \fpu_add_exp_dp/i_a3stg_exp/q_reg[1] ( .D(\fpu_add_exp_dp/n575 ),
.CLK(n1572), .Q(n72), .QN(\fpu_add_exp_dp/n436 ) );
DFFX1 \fpu_add_exp_dp/i_a3stg_exp/q_reg[0] ( .D(\fpu_add_exp_dp/n576 ),
.CLK(n1573), .Q(n583), .QN(\fpu_add_exp_dp/n444 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expadd2_in2/q_reg[12] ( .D(
\fpu_add_exp_dp/n577 ), .CLK(n1576), .Q(n694) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expadd2_in2/q_reg[11] ( .D(
\fpu_add_exp_dp/n578 ), .CLK(n1576), .Q(n629), .QN(
\fpu_add_exp_dp/n111 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expadd2_in2/q_reg[10] ( .D(
\fpu_add_exp_dp/n579 ), .CLK(n1576), .Q(n298), .QN(
\fpu_add_exp_dp/n112 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expadd2_in2/q_reg[9] ( .D(
\fpu_add_exp_dp/n580 ), .CLK(n1576), .Q(n300), .QN(
\fpu_add_exp_dp/n113 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expadd2_in2/q_reg[8] ( .D(
\fpu_add_exp_dp/n581 ), .CLK(n1576), .Q(n301), .QN(
\fpu_add_exp_dp/n114 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expadd2_in2/q_reg[7] ( .D(
\fpu_add_exp_dp/n582 ), .CLK(n1576), .Q(n308), .QN(
\fpu_add_exp_dp/n115 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expadd2_in2/q_reg[6] ( .D(
\fpu_add_exp_dp/n583 ), .CLK(n1576), .Q(n302), .QN(
\fpu_add_exp_dp/n116 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expadd2_in2/q_reg[5] ( .D(
\fpu_add_exp_dp/n584 ), .CLK(n1576), .Q(n299), .QN(
\fpu_add_exp_dp/n117 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expadd2_in2/q_reg[4] ( .D(
\fpu_add_exp_dp/n585 ), .CLK(n1576), .Q(n303), .QN(
\fpu_add_exp_dp/n118 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expadd2_in2/q_reg[3] ( .D(
\fpu_add_exp_dp/n586 ), .CLK(n1575), .Q(n304), .QN(
\fpu_add_exp_dp/n119 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expadd2_in2/q_reg[2] ( .D(
\fpu_add_exp_dp/n587 ), .CLK(n1575), .Q(n305), .QN(
\fpu_add_exp_dp/n120 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expadd2_in2/q_reg[1] ( .D(
\fpu_add_exp_dp/n588 ), .CLK(n1575), .Q(n297), .QN(
\fpu_add_exp_dp/n121 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expadd2_in2/q_reg[0] ( .D(
\fpu_add_exp_dp/n589 ), .CLK(n1575), .Q(n830), .QN(
\fpu_add_exp_dp/n122 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expa/q_reg[11] ( .D(\fpu_add_exp_dp/n591 ),
.CLK(n1575), .Q(n316), .QN(\fpu_add_exp_dp/n124 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expa/q_reg[10] ( .D(\fpu_add_exp_dp/n592 ),
.CLK(n1575), .Q(n680), .QN(\fpu_add_exp_dp/n125 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expa/q_reg[9] ( .D(\fpu_add_exp_dp/n593 ),
.CLK(n1575), .Q(n681), .QN(\fpu_add_exp_dp/n126 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expa/q_reg[8] ( .D(\fpu_add_exp_dp/n594 ),
.CLK(n1575), .Q(n682), .QN(\fpu_add_exp_dp/n127 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expa/q_reg[7] ( .D(\fpu_add_exp_dp/n595 ),
.CLK(n1575), .Q(n683), .QN(\fpu_add_exp_dp/n128 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expa/q_reg[6] ( .D(\fpu_add_exp_dp/n596 ),
.CLK(n1575), .Q(n661), .QN(\fpu_add_exp_dp/n129 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expa/q_reg[5] ( .D(\fpu_add_exp_dp/n597 ),
.CLK(n1575), .Q(n684), .QN(\fpu_add_exp_dp/n130 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expa/q_reg[4] ( .D(\fpu_add_exp_dp/n598 ),
.CLK(n1574), .Q(n685), .QN(\fpu_add_exp_dp/n131 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expa/q_reg[3] ( .D(\fpu_add_exp_dp/n599 ),
.CLK(n1574), .Q(n686), .QN(\fpu_add_exp_dp/n132 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expa/q_reg[2] ( .D(\fpu_add_exp_dp/n600 ),
.CLK(n1574), .Q(n687), .QN(\fpu_add_exp_dp/n133 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expa/q_reg[1] ( .D(\fpu_add_exp_dp/n601 ),
.CLK(n1574), .Q(n676), .QN(\fpu_add_exp_dp/n134 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_expa/q_reg[0] ( .D(\fpu_add_exp_dp/n602 ),
.CLK(n1574), .Q(n315), .QN(\fpu_add_exp_dp/n135 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_exp/q_reg[11] ( .D(\fpu_add_exp_dp/n603 ),
.CLK(n1574), .Q(n725), .QN(\fpu_add_exp_dp/n136 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_exp/q_reg[10] ( .D(\fpu_add_exp_dp/n604 ),
.CLK(n1574), .Q(n289), .QN(\fpu_add_exp_dp/n137 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_exp/q_reg[9] ( .D(\fpu_add_exp_dp/n605 ),
.CLK(n1574), .Q(n88) );
DFFX1 \fpu_add_exp_dp/i_a2stg_exp/q_reg[8] ( .D(\fpu_add_exp_dp/n606 ),
.CLK(n1574), .Q(n35) );
DFFX1 \fpu_add_exp_dp/i_a2stg_exp/q_reg[7] ( .D(\fpu_add_exp_dp/n607 ),
.CLK(n1574), .Q(n221) );
DFFX1 \fpu_add_exp_dp/i_a2stg_exp/q_reg[6] ( .D(\fpu_add_exp_dp/n608 ),
.CLK(n1574), .Q(n711), .QN(\fpu_add_exp_dp/n141 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_exp/q_reg[5] ( .D(\fpu_add_exp_dp/n609 ),
.CLK(n1574), .Q(n646), .QN(\fpu_add_exp_dp/n142 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_exp/q_reg[4] ( .D(\fpu_add_exp_dp/n610 ),
.CLK(n1573), .Q(n648), .QN(\fpu_add_exp_dp/n143 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_exp/q_reg[3] ( .D(\fpu_add_exp_dp/n611 ),
.CLK(n1573), .Q(n290), .QN(\fpu_add_exp_dp/n144 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_exp/q_reg[2] ( .D(\fpu_add_exp_dp/n612 ),
.CLK(n1573), .Q(n287), .QN(\fpu_add_exp_dp/n145 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_exp/q_reg[1] ( .D(\fpu_add_exp_dp/n613 ),
.CLK(n1573), .Q(n73), .QN(\fpu_add_exp_dp/n146 ) );
DFFX1 \fpu_add_exp_dp/i_a2stg_exp/q_reg[0] ( .D(\fpu_add_exp_dp/n614 ),
.CLK(n1573), .Q(n645), .QN(\fpu_add_exp_dp/n147 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in2/q_reg[10] ( .D(
\fpu_add_exp_dp/n615 ), .CLK(n1577), .Q(
\fpu_add_exp_dp/a1stg_expadd3_in2[10] ), .QN(\fpu_add_exp_dp/n47 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in2/q_reg[9] ( .D(
\fpu_add_exp_dp/n616 ), .CLK(n1577), .Q(n445), .QN(
\fpu_add_exp_dp/n149 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in2/q_reg[8] ( .D(
\fpu_add_exp_dp/n617 ), .CLK(n1577), .Q(n446), .QN(
\fpu_add_exp_dp/n150 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in2/q_reg[7] ( .D(
\fpu_add_exp_dp/n618 ), .CLK(n1585), .Q(n323) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in2/q_reg[6] ( .D(
\fpu_add_exp_dp/n619 ), .CLK(n1585), .Q(n322) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in2/q_reg[5] ( .D(
\fpu_add_exp_dp/n620 ), .CLK(n1585), .Q(n321) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in2/q_reg[4] ( .D(
\fpu_add_exp_dp/n621 ), .CLK(n1585), .Q(n320) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in2/q_reg[3] ( .D(
\fpu_add_exp_dp/n622 ), .CLK(n1585), .Q(n319) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in2/q_reg[2] ( .D(
\fpu_add_exp_dp/n623 ), .CLK(n1585), .Q(n309) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in2/q_reg[1] ( .D(
\fpu_add_exp_dp/n624 ), .CLK(n1585), .Q(n56) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in2/q_reg[0] ( .D(
\fpu_add_exp_dp/n625 ), .CLK(n1585), .Q(n491) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in1/q_reg[10] ( .D(
\fpu_add_exp_dp/n626 ), .CLK(n1585), .Q(n961), .QN(
\fpu_add_exp_dp/n45 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in1/q_reg[9] ( .D(
\fpu_add_exp_dp/n627 ), .CLK(n1584), .Q(n1000) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in1/q_reg[8] ( .D(
\fpu_add_exp_dp/n628 ), .CLK(n1584), .Q(n999) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in1/q_reg[7] ( .D(
\fpu_add_exp_dp/n629 ), .CLK(n1584), .Q(n998) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in1/q_reg[6] ( .D(
\fpu_add_exp_dp/n630 ), .CLK(n1584), .Q(n997) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in1/q_reg[5] ( .D(
\fpu_add_exp_dp/n631 ), .CLK(n1584), .Q(n996) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in1/q_reg[4] ( .D(
\fpu_add_exp_dp/n632 ), .CLK(n1584), .Q(n995) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in1/q_reg[3] ( .D(
\fpu_add_exp_dp/n633 ), .CLK(n1584), .Q(n994) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in1/q_reg[2] ( .D(
\fpu_add_exp_dp/n634 ), .CLK(n1584), .Q(n993) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in1/q_reg[1] ( .D(
\fpu_add_exp_dp/n635 ), .CLK(n1584), .Q(n138) );
DFFX1 \fpu_add_exp_dp/i_a1stg_expadd3_in1/q_reg[0] ( .D(
\fpu_add_exp_dp/n636 ), .CLK(n1584), .Q(n992) );
DFFX1 \fpu_add_exp_dp/i_a1stg_op_7/q_reg[3] ( .D(\fpu_add_exp_dp/n637 ),
.CLK(n1584), .Q(n1241), .QN(\fpu_add_exp_dp/n170 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_op_7/q_reg[2] ( .D(\fpu_add_exp_dp/n638 ),
.CLK(n1584), .Q(n1240), .QN(\fpu_add_exp_dp/n171 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_op_7/q_reg[1] ( .D(\fpu_add_exp_dp/n639 ),
.CLK(n1583), .Q(n1239), .QN(\fpu_add_exp_dp/n172 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_op_7/q_reg[0] ( .D(\fpu_add_exp_dp/n640 ),
.CLK(n1583), .Q(n13) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblopa/q_reg[10] ( .D(
\fpu_add_exp_dp/n641 ), .CLK(n1583), .Q(n1148), .QN(
\fpu_add_exp_dp/n174 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblopa/q_reg[9] ( .D(\fpu_add_exp_dp/n642 ), .CLK(n1583), .Q(n559), .QN(\fpu_add_exp_dp/n175 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblopa/q_reg[8] ( .D(\fpu_add_exp_dp/n643 ), .CLK(n1583), .Q(n1163), .QN(\fpu_add_exp_dp/n176 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblopa/q_reg[7] ( .D(\fpu_add_exp_dp/n644 ), .CLK(n1583), .Q(n1171), .QN(\fpu_add_exp_dp/n177 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblopa/q_reg[6] ( .D(\fpu_add_exp_dp/n645 ), .CLK(n1583), .Q(n1168), .QN(\fpu_add_exp_dp/n178 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblopa/q_reg[5] ( .D(\fpu_add_exp_dp/n646 ), .CLK(n1583), .Q(n1155), .QN(\fpu_add_exp_dp/n179 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblopa/q_reg[4] ( .D(\fpu_add_exp_dp/n647 ), .CLK(n1583), .Q(n1167), .QN(\fpu_add_exp_dp/n180 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblopa/q_reg[3] ( .D(\fpu_add_exp_dp/n648 ), .CLK(n1583), .Q(n1166), .QN(\fpu_add_exp_dp/n181 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblopa/q_reg[2] ( .D(\fpu_add_exp_dp/n649 ), .CLK(n1583), .Q(n1179), .QN(\fpu_add_exp_dp/n182 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblopa/q_reg[1] ( .D(\fpu_add_exp_dp/n650 ), .CLK(n1583), .Q(n558), .QN(\fpu_add_exp_dp/n183 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblopa/q_reg[0] ( .D(\fpu_add_exp_dp/n651 ), .CLK(n1582), .Q(n151), .QN(\fpu_add_exp_dp/n184 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblop/q_reg[10] ( .D(\fpu_add_exp_dp/n652 ), .CLK(n1582), .Q(n928), .QN(\fpu_add_exp_dp/n185 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblop/q_reg[9] ( .D(\fpu_add_exp_dp/n653 ),
.CLK(n1582), .Q(n1150), .QN(\fpu_add_exp_dp/n186 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblop/q_reg[8] ( .D(\fpu_add_exp_dp/n654 ),
.CLK(n1582), .Q(n1147), .QN(\fpu_add_exp_dp/n187 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblop/q_reg[7] ( .D(\fpu_add_exp_dp/n655 ),
.CLK(n1582), .Q(n545), .QN(\fpu_add_exp_dp/n188 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblop/q_reg[6] ( .D(\fpu_add_exp_dp/n656 ),
.CLK(n1582), .Q(n546), .QN(\fpu_add_exp_dp/n189 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblop/q_reg[5] ( .D(\fpu_add_exp_dp/n657 ),
.CLK(n1582), .Q(n516), .QN(\fpu_add_exp_dp/n190 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblop/q_reg[4] ( .D(\fpu_add_exp_dp/n658 ),
.CLK(n1582), .Q(n515), .QN(\fpu_add_exp_dp/n191 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblop/q_reg[3] ( .D(\fpu_add_exp_dp/n659 ),
.CLK(n1582), .Q(n514), .QN(\fpu_add_exp_dp/n192 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblop/q_reg[2] ( .D(\fpu_add_exp_dp/n660 ),
.CLK(n1582), .Q(n1165), .QN(\fpu_add_exp_dp/n193 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblop/q_reg[1] ( .D(\fpu_add_exp_dp/n661 ),
.CLK(n1582), .Q(n1154), .QN(\fpu_add_exp_dp/n194 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_dblop/q_reg[0] ( .D(\fpu_add_exp_dp/n662 ),
.CLK(n1582), .Q(n1164), .QN(\fpu_add_exp_dp/n195 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_sngopa/q_reg[7] ( .D(\fpu_add_exp_dp/n663 ), .CLK(n1581), .Q(n1178), .QN(\fpu_add_exp_dp/n196 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_sngopa/q_reg[6] ( .D(\fpu_add_exp_dp/n664 ), .CLK(n1581), .Q(n1177), .QN(\fpu_add_exp_dp/n197 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_sngopa/q_reg[5] ( .D(\fpu_add_exp_dp/n665 ), .CLK(n1581), .Q(n1170), .QN(\fpu_add_exp_dp/n198 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_sngopa/q_reg[4] ( .D(\fpu_add_exp_dp/n666 ), .CLK(n1581), .Q(n1176), .QN(\fpu_add_exp_dp/n199 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_sngopa/q_reg[3] ( .D(\fpu_add_exp_dp/n667 ), .CLK(n1581), .Q(n1175), .QN(\fpu_add_exp_dp/n200 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_sngopa/q_reg[2] ( .D(\fpu_add_exp_dp/n668 ), .CLK(n1581), .Q(n1174), .QN(\fpu_add_exp_dp/n201 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_sngopa/q_reg[1] ( .D(\fpu_add_exp_dp/n669 ), .CLK(n1581), .Q(n61), .QN(\fpu_add_exp_dp/n202 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_sngopa/q_reg[0] ( .D(\fpu_add_exp_dp/n670 ), .CLK(n1581), .Q(n510), .QN(\fpu_add_exp_dp/n203 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_sngop/q_reg[7] ( .D(\fpu_add_exp_dp/n671 ),
.CLK(n1581), .Q(n936), .QN(\fpu_add_exp_dp/n204 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_sngop/q_reg[6] ( .D(\fpu_add_exp_dp/n672 ),
.CLK(n1581), .Q(n937), .QN(\fpu_add_exp_dp/n205 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_sngop/q_reg[5] ( .D(\fpu_add_exp_dp/n673 ),
.CLK(n1581), .Q(n960), .QN(\fpu_add_exp_dp/n206 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_sngop/q_reg[4] ( .D(\fpu_add_exp_dp/n674 ),
.CLK(n1581), .Q(n959), .QN(\fpu_add_exp_dp/n207 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_sngop/q_reg[3] ( .D(\fpu_add_exp_dp/n675 ),
.CLK(n1580), .Q(n958), .QN(\fpu_add_exp_dp/n208 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_sngop/q_reg[2] ( .D(\fpu_add_exp_dp/n676 ),
.CLK(n1580), .Q(n1160), .QN(\fpu_add_exp_dp/n209 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_sngop/q_reg[1] ( .D(\fpu_add_exp_dp/n677 ),
.CLK(n1580), .Q(n1169), .QN(\fpu_add_exp_dp/n210 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_dp_sngop/q_reg[0] ( .D(\fpu_add_exp_dp/n678 ),
.CLK(n1580), .Q(n1159), .QN(\fpu_add_exp_dp/n211 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2a/q_reg[10] ( .D(\fpu_add_exp_dp/n679 ),
.CLK(n1580), .Q(n1181), .QN(\fpu_add_exp_dp/n212 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2a/q_reg[9] ( .D(\fpu_add_exp_dp/n680 ),
.CLK(n1580), .Q(n1075), .QN(\fpu_add_exp_dp/n213 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2a/q_reg[8] ( .D(\fpu_add_exp_dp/n681 ),
.CLK(n1580), .Q(n1180), .QN(\fpu_add_exp_dp/n214 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2a/q_reg[7] ( .D(\fpu_add_exp_dp/n682 ),
.CLK(n1577), .Q(\fpu_add_exp_dp/a1stg_in2a[59] ), .QN(
\fpu_add_exp_dp/n215 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2a/q_reg[6] ( .D(\fpu_add_exp_dp/n683 ),
.CLK(n1577), .Q(\fpu_add_exp_dp/a1stg_in2a[58] ), .QN(
\fpu_add_exp_dp/n216 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2a/q_reg[5] ( .D(\fpu_add_exp_dp/n684 ),
.CLK(n1577), .Q(\fpu_add_exp_dp/a1stg_in2a[57] ), .QN(
\fpu_add_exp_dp/n217 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2a/q_reg[4] ( .D(\fpu_add_exp_dp/n685 ),
.CLK(n1577), .Q(\fpu_add_exp_dp/a1stg_in2a[56] ), .QN(
\fpu_add_exp_dp/n218 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2a/q_reg[3] ( .D(\fpu_add_exp_dp/n686 ),
.CLK(n1577), .Q(\fpu_add_exp_dp/a1stg_in2a[55] ), .QN(
\fpu_add_exp_dp/n219 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2a/q_reg[2] ( .D(\fpu_add_exp_dp/n687 ),
.CLK(n1576), .Q(\fpu_add_exp_dp/a1stg_in2a[54] ), .QN(
\fpu_add_exp_dp/n220 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2a/q_reg[1] ( .D(\fpu_add_exp_dp/n688 ),
.CLK(n1576), .Q(\fpu_add_exp_dp/a1stg_in2a[53] ), .QN(
\fpu_add_exp_dp/n221 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2a/q_reg[0] ( .D(\fpu_add_exp_dp/n689 ),
.CLK(n1576), .Q(\fpu_add_exp_dp/a1stg_in2a[52] ), .QN(
\fpu_add_exp_dp/n222 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2/q_reg[10] ( .D(\fpu_add_exp_dp/n690 ),
.CLK(n1580), .Q(n105) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2/q_reg[9] ( .D(\fpu_add_exp_dp/n691 ),
.CLK(n1580), .Q(n127), .QN(\fpu_add_exp_dp/n224 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2/q_reg[8] ( .D(\fpu_add_exp_dp/n692 ),
.CLK(n1580), .Q(n126), .QN(\fpu_add_exp_dp/n225 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2/q_reg[7] ( .D(\fpu_add_exp_dp/n693 ),
.CLK(n1580), .Q(n41) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2/q_reg[6] ( .D(\fpu_add_exp_dp/n694 ),
.CLK(n1580), .Q(n42) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2/q_reg[5] ( .D(\fpu_add_exp_dp/n695 ),
.CLK(n1579), .Q(n49), .QN(\fpu_add_exp_dp/n228 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2/q_reg[4] ( .D(\fpu_add_exp_dp/n696 ),
.CLK(n1579), .Q(n110), .QN(\fpu_add_exp_dp/n229 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2/q_reg[3] ( .D(\fpu_add_exp_dp/n697 ),
.CLK(n1579), .Q(n109), .QN(\fpu_add_exp_dp/n230 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2/q_reg[2] ( .D(\fpu_add_exp_dp/n698 ),
.CLK(n1579), .Q(n1005), .QN(\fpu_add_exp_dp/n231 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2/q_reg[1] ( .D(\fpu_add_exp_dp/n699 ),
.CLK(n1579), .Q(n991), .QN(\fpu_add_exp_dp/n232 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in2/q_reg[0] ( .D(\fpu_add_exp_dp/n700 ),
.CLK(n1579), .Q(n990), .QN(\fpu_add_exp_dp/n233 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1a/q_reg[10] ( .D(\fpu_add_exp_dp/n701 ),
.CLK(n1579), .Q(n657), .QN(\fpu_add_exp_dp/n234 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1a/q_reg[9] ( .D(\fpu_add_exp_dp/n702 ),
.CLK(n1579), .Q(n656), .QN(\fpu_add_exp_dp/n235 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1a/q_reg[8] ( .D(\fpu_add_exp_dp/n703 ),
.CLK(n1579), .Q(n658), .QN(\fpu_add_exp_dp/n236 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1a/q_reg[7] ( .D(\fpu_add_exp_dp/n704 ),
.CLK(n1579), .Q(n669), .QN(\fpu_add_exp_dp/n237 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1a/q_reg[6] ( .D(\fpu_add_exp_dp/n705 ),
.CLK(n1579), .Q(n668), .QN(\fpu_add_exp_dp/n238 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1a/q_reg[5] ( .D(\fpu_add_exp_dp/n706 ),
.CLK(n1579), .Q(n675), .QN(\fpu_add_exp_dp/n239 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1a/q_reg[4] ( .D(\fpu_add_exp_dp/n707 ),
.CLK(n1578), .Q(n674), .QN(\fpu_add_exp_dp/n240 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1a/q_reg[3] ( .D(\fpu_add_exp_dp/n708 ),
.CLK(n1578), .Q(n672), .QN(\fpu_add_exp_dp/n241 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1a/q_reg[2] ( .D(\fpu_add_exp_dp/n709 ),
.CLK(n1578), .Q(n508), .QN(\fpu_add_exp_dp/n242 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1a/q_reg[1] ( .D(\fpu_add_exp_dp/n710 ),
.CLK(n1578), .Q(n507), .QN(\fpu_add_exp_dp/n243 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1a/q_reg[0] ( .D(\fpu_add_exp_dp/n711 ),
.CLK(n1578), .Q(n509), .QN(\fpu_add_exp_dp/n244 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1/q_reg[10] ( .D(\fpu_add_exp_dp/n712 ),
.CLK(n1578), .Q(n1156), .QN(\fpu_add_exp_dp/n245 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1/q_reg[9] ( .D(\fpu_add_exp_dp/n713 ),
.CLK(n1578), .Q(n1183), .QN(\fpu_add_exp_dp/n246 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1/q_reg[8] ( .D(\fpu_add_exp_dp/n714 ),
.CLK(n1578), .Q(n1182), .QN(\fpu_add_exp_dp/n247 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1/q_reg[7] ( .D(\fpu_add_exp_dp/n715 ),
.CLK(n1578), .Q(n1172), .QN(\fpu_add_exp_dp/n248 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1/q_reg[6] ( .D(\fpu_add_exp_dp/n716 ),
.CLK(n1578), .Q(n1162), .QN(\fpu_add_exp_dp/n249 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1/q_reg[5] ( .D(\fpu_add_exp_dp/n717 ),
.CLK(n1578), .Q(n1161), .QN(\fpu_add_exp_dp/n250 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1/q_reg[4] ( .D(\fpu_add_exp_dp/n718 ),
.CLK(n1578), .Q(n152), .QN(\fpu_add_exp_dp/n251 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1/q_reg[3] ( .D(\fpu_add_exp_dp/n719 ),
.CLK(n1577), .Q(n60), .QN(\fpu_add_exp_dp/n252 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1/q_reg[2] ( .D(\fpu_add_exp_dp/n720 ),
.CLK(n1577), .Q(n1223), .QN(\fpu_add_exp_dp/n253 ) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1/q_reg[1] ( .D(\fpu_add_exp_dp/n721 ),
.CLK(n1577), .Q(n1066) );
DFFX1 \fpu_add_exp_dp/i_a1stg_in1/q_reg[0] ( .D(\fpu_add_exp_dp/n722 ),
.CLK(n1577), .Q(n1033) );
LATCHX1 \fpu_add_exp_dp/ckbuf_add_exp_dp/clken_reg ( .CLK(
\fpu_add_frac_dp/n2189 ), .D(\fpu_add_exp_dp/ckbuf_add_exp_dp/N1 ),
.Q(\fpu_add_exp_dp/ckbuf_add_exp_dp/clken ), .QN(\fpu_add_exp_dp/n256 ) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[63] ( .D(\fpu_add_frac_dp/n3375 ),
.CLK(n1529), .Q(n467) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[62] ( .D(\fpu_add_frac_dp/n3376 ),
.CLK(n1529), .Q(n468) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[61] ( .D(\fpu_add_frac_dp/n3377 ),
.CLK(n1529), .Q(n963) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[60] ( .D(\fpu_add_frac_dp/n3378 ),
.CLK(n1528), .Q(n466) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[59] ( .D(\fpu_add_frac_dp/n3379 ),
.CLK(n1528), .Q(n933) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[58] ( .D(\fpu_add_frac_dp/n3380 ),
.CLK(n1529), .Q(n1034) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[57] ( .D(\fpu_add_frac_dp/n3381 ),
.CLK(n1528), .Q(n906) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[56] ( .D(\fpu_add_frac_dp/n3382 ),
.CLK(n1530), .Q(n1064) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[55] ( .D(\fpu_add_frac_dp/n3383 ),
.CLK(n1536), .Q(n918) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[54] ( .D(\fpu_add_frac_dp/n3384 ),
.CLK(n1536), .Q(n909) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[53] ( .D(\fpu_add_frac_dp/n3385 ),
.CLK(n1530), .Q(n910) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[52] ( .D(\fpu_add_frac_dp/n3386 ),
.CLK(n1531), .Q(n911) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[51] ( .D(\fpu_add_frac_dp/n3387 ),
.CLK(n1531), .Q(n912) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[50] ( .D(\fpu_add_frac_dp/n3388 ),
.CLK(n1531), .Q(n913) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[49] ( .D(\fpu_add_frac_dp/n3389 ),
.CLK(n1526), .Q(n469) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[48] ( .D(\fpu_add_frac_dp/n3390 ),
.CLK(n1525), .Q(n470) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[47] ( .D(\fpu_add_frac_dp/n3391 ),
.CLK(n1525), .Q(n471) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[46] ( .D(\fpu_add_frac_dp/n3392 ),
.CLK(n1525), .Q(n472) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[45] ( .D(\fpu_add_frac_dp/n3393 ),
.CLK(n1525), .Q(n473) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[44] ( .D(\fpu_add_frac_dp/n3394 ),
.CLK(n1524), .Q(n474) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[43] ( .D(\fpu_add_frac_dp/n3395 ),
.CLK(n1524), .Q(n475) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[42] ( .D(\fpu_add_frac_dp/n3396 ),
.CLK(n1524), .Q(n476) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[41] ( .D(\fpu_add_frac_dp/n3397 ),
.CLK(n1524), .Q(n477) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[40] ( .D(\fpu_add_frac_dp/n3398 ),
.CLK(n1524), .Q(n478) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[39] ( .D(\fpu_add_frac_dp/n3399 ),
.CLK(n1523), .Q(n479) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[38] ( .D(\fpu_add_frac_dp/n3400 ),
.CLK(n1523), .Q(n480) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[37] ( .D(\fpu_add_frac_dp/n3401 ),
.CLK(n1523), .Q(n481) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[36] ( .D(\fpu_add_frac_dp/n3402 ),
.CLK(n1523), .Q(n482) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[35] ( .D(\fpu_add_frac_dp/n3403 ),
.CLK(n1522), .Q(n483) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[34] ( .D(\fpu_add_frac_dp/n3404 ),
.CLK(n1522), .Q(n484) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[33] ( .D(\fpu_add_frac_dp/n3405 ),
.CLK(n1521), .Q(n485) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[32] ( .D(\fpu_add_frac_dp/n3406 ),
.CLK(n1521), .Q(n486) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[31] ( .D(\fpu_add_frac_dp/n3407 ),
.CLK(n1521), .Q(n487) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[30] ( .D(\fpu_add_frac_dp/n3408 ),
.CLK(n1521), .Q(n488) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[29] ( .D(\fpu_add_frac_dp/n3409 ),
.CLK(n1521), .Q(n489) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[28] ( .D(\fpu_add_frac_dp/n3410 ),
.CLK(n1520), .Q(n517) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[27] ( .D(\fpu_add_frac_dp/n3411 ),
.CLK(n1520), .Q(n518) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[26] ( .D(\fpu_add_frac_dp/n3412 ),
.CLK(n1520), .Q(n519) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[25] ( .D(\fpu_add_frac_dp/n3413 ),
.CLK(n1520), .Q(n520) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[24] ( .D(\fpu_add_frac_dp/n3414 ),
.CLK(n1537), .Q(n521) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[23] ( .D(\fpu_add_frac_dp/n3415 ),
.CLK(n1538), .Q(n522) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[22] ( .D(\fpu_add_frac_dp/n3416 ),
.CLK(n1538), .Q(n523) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[21] ( .D(\fpu_add_frac_dp/n3417 ),
.CLK(n1518), .Q(n524) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[20] ( .D(\fpu_add_frac_dp/n3418 ),
.CLK(n1519), .Q(n525) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[19] ( .D(\fpu_add_frac_dp/n3419 ),
.CLK(n1519), .Q(n526) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[18] ( .D(\fpu_add_frac_dp/n3420 ),
.CLK(n1519), .Q(n527) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[17] ( .D(\fpu_add_frac_dp/n3421 ),
.CLK(n1537), .Q(n528) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[16] ( .D(\fpu_add_frac_dp/n3422 ),
.CLK(n1537), .Q(n529) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[15] ( .D(\fpu_add_frac_dp/n3423 ),
.CLK(n1532), .Q(n530) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[14] ( .D(\fpu_add_frac_dp/n3424 ),
.CLK(n1535), .Q(n531) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[13] ( .D(\fpu_add_frac_dp/n3425 ),
.CLK(n1535), .Q(n532) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[12] ( .D(\fpu_add_frac_dp/n3426 ),
.CLK(n1536), .Q(n533) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[11] ( .D(\fpu_add_frac_dp/n3427 ),
.CLK(n1519), .Q(n534) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[10] ( .D(\fpu_add_frac_dp/n3428 ),
.CLK(n1519), .Q(n535) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[9] ( .D(\fpu_add_frac_dp/n3429 ),
.CLK(n1537), .Q(n1002) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[8] ( .D(\fpu_add_frac_dp/n3430 ),
.CLK(n1537), .Q(n1003) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[7] ( .D(\fpu_add_frac_dp/n3431 ),
.CLK(n1531), .Q(n919) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[6] ( .D(\fpu_add_frac_dp/n3432 ),
.CLK(n1535), .Q(n920) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[5] ( .D(\fpu_add_frac_dp/n3433 ),
.CLK(n1535), .Q(n921) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[4] ( .D(\fpu_add_frac_dp/n3434 ),
.CLK(n1536), .Q(n922) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[3] ( .D(\fpu_add_frac_dp/n3435 ),
.CLK(n1522), .Q(n923) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[2] ( .D(\fpu_add_frac_dp/n3436 ),
.CLK(n1522), .Q(n924) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[1] ( .D(\fpu_add_frac_dp/n3437 ),
.CLK(n1522), .Q(n551) );
DFFX1 \fpu_add_frac_dp/i_a5stg_shl/q_reg[0] ( .D(\fpu_add_frac_dp/n3438 ),
.CLK(n1522), .Q(n925) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[63] ( .D(
\fpu_add_frac_dp/n3439 ), .CLK(n1529), .Q(n859) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[62] ( .D(
\fpu_add_frac_dp/n3440 ), .CLK(n1529), .Q(n907) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[61] ( .D(
\fpu_add_frac_dp/n3441 ), .CLK(n1530), .Q(n493) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[60] ( .D(
\fpu_add_frac_dp/n3442 ), .CLK(n1533), .Q(n860) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[59] ( .D(
\fpu_add_frac_dp/n3443 ), .CLK(n1529), .Q(n494) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[58] ( .D(
\fpu_add_frac_dp/n3444 ), .CLK(n1529), .Q(n495) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[57] ( .D(
\fpu_add_frac_dp/n3445 ), .CLK(n1530), .Q(n496) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[56] ( .D(
\fpu_add_frac_dp/n3446 ), .CLK(n1530), .Q(n497) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[55] ( .D(
\fpu_add_frac_dp/n3447 ), .CLK(n1536), .Q(n498) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[54] ( .D(
\fpu_add_frac_dp/n3448 ), .CLK(n1536), .Q(n499) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[53] ( .D(
\fpu_add_frac_dp/n3449 ), .CLK(n1530), .Q(n500) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[52] ( .D(
\fpu_add_frac_dp/n3450 ), .CLK(n1531), .Q(n501) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[51] ( .D(
\fpu_add_frac_dp/n3451 ), .CLK(n1531), .Q(n502) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[50] ( .D(
\fpu_add_frac_dp/n3452 ), .CLK(n1531), .Q(n503) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[49] ( .D(
\fpu_add_frac_dp/n3453 ), .CLK(n1526), .Q(n861) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[48] ( .D(
\fpu_add_frac_dp/n3454 ), .CLK(n1525), .Q(n862) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[47] ( .D(
\fpu_add_frac_dp/n3455 ), .CLK(n1525), .Q(n863) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[46] ( .D(
\fpu_add_frac_dp/n3456 ), .CLK(n1525), .Q(n864) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[45] ( .D(
\fpu_add_frac_dp/n3457 ), .CLK(n1525), .Q(n865) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[44] ( .D(
\fpu_add_frac_dp/n3458 ), .CLK(n1525), .Q(n866) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[43] ( .D(
\fpu_add_frac_dp/n3459 ), .CLK(n1524), .Q(n867) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[42] ( .D(
\fpu_add_frac_dp/n3460 ), .CLK(n1524), .Q(n868) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[41] ( .D(
\fpu_add_frac_dp/n3461 ), .CLK(n1524), .Q(n869) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[40] ( .D(
\fpu_add_frac_dp/n3462 ), .CLK(n1524), .Q(n870) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[39] ( .D(
\fpu_add_frac_dp/n3463 ), .CLK(n1523), .Q(n871) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[38] ( .D(
\fpu_add_frac_dp/n3464 ), .CLK(n1523), .Q(n872) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[37] ( .D(
\fpu_add_frac_dp/n3465 ), .CLK(n1523), .Q(n873) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[36] ( .D(
\fpu_add_frac_dp/n3466 ), .CLK(n1523), .Q(n874) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[35] ( .D(
\fpu_add_frac_dp/n3467 ), .CLK(n1523), .Q(n875) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[34] ( .D(
\fpu_add_frac_dp/n3468 ), .CLK(n1522), .Q(n876) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[33] ( .D(
\fpu_add_frac_dp/n3469 ), .CLK(n1521), .Q(n877) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[32] ( .D(
\fpu_add_frac_dp/n3470 ), .CLK(n1521), .Q(n878) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[31] ( .D(
\fpu_add_frac_dp/n3471 ), .CLK(n1521), .Q(n879) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[30] ( .D(
\fpu_add_frac_dp/n3472 ), .CLK(n1521), .Q(n880) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[29] ( .D(
\fpu_add_frac_dp/n3473 ), .CLK(n1521), .Q(n881) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[28] ( .D(
\fpu_add_frac_dp/n3474 ), .CLK(n1520), .Q(n938) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[27] ( .D(
\fpu_add_frac_dp/n3475 ), .CLK(n1520), .Q(n939) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[26] ( .D(
\fpu_add_frac_dp/n3476 ), .CLK(n1520), .Q(n940) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[25] ( .D(
\fpu_add_frac_dp/n3477 ), .CLK(n1520), .Q(n941) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[24] ( .D(
\fpu_add_frac_dp/n3478 ), .CLK(n1537), .Q(n942) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[23] ( .D(
\fpu_add_frac_dp/n3479 ), .CLK(n1538), .Q(n943) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[22] ( .D(
\fpu_add_frac_dp/n3480 ), .CLK(n1523), .Q(n944) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[21] ( .D(
\fpu_add_frac_dp/n3481 ), .CLK(n1518), .Q(n945) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[20] ( .D(
\fpu_add_frac_dp/n3482 ), .CLK(n1519), .Q(n946) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[19] ( .D(
\fpu_add_frac_dp/n3483 ), .CLK(n1519), .Q(n947) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[18] ( .D(
\fpu_add_frac_dp/n3484 ), .CLK(n1519), .Q(n948) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[17] ( .D(
\fpu_add_frac_dp/n3485 ), .CLK(n1537), .Q(n949) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[16] ( .D(
\fpu_add_frac_dp/n3486 ), .CLK(n1537), .Q(n950) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[15] ( .D(
\fpu_add_frac_dp/n3487 ), .CLK(n1532), .Q(n951) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[14] ( .D(
\fpu_add_frac_dp/n3488 ), .CLK(n1535), .Q(n952) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[13] ( .D(
\fpu_add_frac_dp/n3489 ), .CLK(n1535), .Q(n953) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[12] ( .D(
\fpu_add_frac_dp/n3490 ), .CLK(n1536), .Q(n954) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[11] ( .D(
\fpu_add_frac_dp/n3491 ), .CLK(n1536), .Q(n955) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[10] ( .D(
\fpu_add_frac_dp/n3492 ), .CLK(n1519), .Q(n908) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[9] ( .D(
\fpu_add_frac_dp/n3493 ), .CLK(n1537), .Q(n536) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[8] ( .D(
\fpu_add_frac_dp/n3494 ), .CLK(n1537), .Q(n537) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[7] ( .D(
\fpu_add_frac_dp/n3495 ), .CLK(n1532), .Q(n538) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[6] ( .D(
\fpu_add_frac_dp/n3496 ), .CLK(n1535), .Q(n539) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[5] ( .D(
\fpu_add_frac_dp/n3497 ), .CLK(n1535), .Q(n540) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[4] ( .D(
\fpu_add_frac_dp/n3498 ), .CLK(n1536), .Q(n541) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[3] ( .D(
\fpu_add_frac_dp/n3499 ), .CLK(n1522), .Q(n542) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[2] ( .D(
\fpu_add_frac_dp/n3500 ), .CLK(n1522), .Q(n543) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[1] ( .D(
\fpu_add_frac_dp/n3501 ), .CLK(n1522), .Q(n978) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rnd_frac/q_reg[0] ( .D(
\fpu_add_frac_dp/n3502 ), .CLK(n1522), .Q(n544) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[57] ( .D(
\fpu_add_frac_dp/n3503 ), .CLK(n1528), .Q(n1248), .QN(
\fpu_add_frac_dp/n129 ) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[56] ( .D(
\fpu_add_frac_dp/n3504 ), .CLK(n1532), .Q(n579) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[55] ( .D(
\fpu_add_frac_dp/n3505 ), .CLK(n1532), .Q(n66), .QN(
\fpu_add_frac_dp/n5617 ) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[54] ( .D(
\fpu_add_frac_dp/n3506 ), .CLK(n1520), .Q(
\fpu_add_frac_dp/a5stg_in_of ), .QN(\fpu_add_frac_dp/n132 ) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[53] ( .D(
\fpu_add_frac_dp/n3507 ), .CLK(n1520), .Q(n65), .QN(
\fpu_add_frac_dp/n5616 ) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[52] ( .D(
\fpu_add_frac_dp/n3508 ), .CLK(n1555), .Q(n1186), .QN(
\fpu_add_frac_dp/n134 ) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[51] ( .D(
\fpu_add_frac_dp/n3509 ), .CLK(n1528), .Q(n1006) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[50] ( .D(
\fpu_add_frac_dp/n3510 ), .CLK(n1538), .Q(n1035) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[49] ( .D(
\fpu_add_frac_dp/n3511 ), .CLK(n1481), .Q(n1036) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[48] ( .D(
\fpu_add_frac_dp/n3512 ), .CLK(n1529), .Q(n1037) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[47] ( .D(
\fpu_add_frac_dp/n3513 ), .CLK(n1529), .Q(n1038) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[46] ( .D(
\fpu_add_frac_dp/n3514 ), .CLK(n1530), .Q(n1039) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[45] ( .D(
\fpu_add_frac_dp/n3515 ), .CLK(n1530), .Q(n1040) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[44] ( .D(
\fpu_add_frac_dp/n3516 ), .CLK(n1530), .Q(n1041) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[43] ( .D(
\fpu_add_frac_dp/n3517 ), .CLK(n1530), .Q(n964) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[42] ( .D(
\fpu_add_frac_dp/n3518 ), .CLK(n1530), .Q(n965) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[41] ( .D(
\fpu_add_frac_dp/n3519 ), .CLK(n1531), .Q(n966) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[40] ( .D(
\fpu_add_frac_dp/n3520 ), .CLK(n1531), .Q(n967) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[39] ( .D(
\fpu_add_frac_dp/n3521 ), .CLK(n1531), .Q(n968) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[38] ( .D(
\fpu_add_frac_dp/n3522 ), .CLK(n1534), .Q(n1042) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[37] ( .D(
\fpu_add_frac_dp/n3523 ), .CLK(n1534), .Q(n1043) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[36] ( .D(
\fpu_add_frac_dp/n3524 ), .CLK(n1534), .Q(n1044) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[35] ( .D(
\fpu_add_frac_dp/n3525 ), .CLK(n1534), .Q(n1045) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[34] ( .D(
\fpu_add_frac_dp/n3526 ), .CLK(n1534), .Q(n1046) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[33] ( .D(
\fpu_add_frac_dp/n3527 ), .CLK(n1534), .Q(n1047) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[32] ( .D(
\fpu_add_frac_dp/n3528 ), .CLK(n1534), .Q(n1048) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[31] ( .D(
\fpu_add_frac_dp/n3529 ), .CLK(n1534), .Q(n1049) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[30] ( .D(
\fpu_add_frac_dp/n3530 ), .CLK(n1534), .Q(n1050) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[29] ( .D(
\fpu_add_frac_dp/n3531 ), .CLK(n1534), .Q(n1051) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[28] ( .D(
\fpu_add_frac_dp/n3532 ), .CLK(n1534), .Q(n1052) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[27] ( .D(
\fpu_add_frac_dp/n3533 ), .CLK(n1534), .Q(n1053) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[26] ( .D(
\fpu_add_frac_dp/n3534 ), .CLK(n1533), .Q(n1054) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[25] ( .D(
\fpu_add_frac_dp/n3535 ), .CLK(n1534), .Q(n1055) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[24] ( .D(
\fpu_add_frac_dp/n3536 ), .CLK(n1533), .Q(n1056) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[23] ( .D(
\fpu_add_frac_dp/n3537 ), .CLK(n1533), .Q(n1057) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[22] ( .D(
\fpu_add_frac_dp/n3538 ), .CLK(n1533), .Q(n1058) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[21] ( .D(
\fpu_add_frac_dp/n3539 ), .CLK(n1533), .Q(n1059) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[20] ( .D(
\fpu_add_frac_dp/n3540 ), .CLK(n1533), .Q(n1060) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[19] ( .D(
\fpu_add_frac_dp/n3541 ), .CLK(n1533), .Q(n1061) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[18] ( .D(
\fpu_add_frac_dp/n3542 ), .CLK(n1533), .Q(n1062) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[17] ( .D(
\fpu_add_frac_dp/n3543 ), .CLK(n1533), .Q(n969) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[16] ( .D(
\fpu_add_frac_dp/n3544 ), .CLK(n1533), .Q(n970) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[15] ( .D(
\fpu_add_frac_dp/n3545 ), .CLK(n1533), .Q(n971) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[14] ( .D(
\fpu_add_frac_dp/n3546 ), .CLK(n1533), .Q(n972) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[13] ( .D(
\fpu_add_frac_dp/n3547 ), .CLK(n1533), .Q(n973) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[12] ( .D(
\fpu_add_frac_dp/n3548 ), .CLK(n1532), .Q(n974) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[11] ( .D(
\fpu_add_frac_dp/n3549 ), .CLK(n1532), .Q(n975) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[10] ( .D(
\fpu_add_frac_dp/n3550 ), .CLK(n1532), .Q(n976) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[9] ( .D(\fpu_add_frac_dp/n3551 ), .CLK(n1532), .Q(n977) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[8] ( .D(\fpu_add_frac_dp/n3552 ), .CLK(n1532), .Q(n979) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[7] ( .D(\fpu_add_frac_dp/n3553 ), .CLK(n1532), .Q(n980) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[6] ( .D(\fpu_add_frac_dp/n3554 ), .CLK(n1532), .Q(n981) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[5] ( .D(\fpu_add_frac_dp/n3555 ), .CLK(n1532), .Q(n982) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[4] ( .D(\fpu_add_frac_dp/n3556 ), .CLK(n1532), .Q(n983) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[3] ( .D(\fpu_add_frac_dp/n3557 ), .CLK(n1535), .Q(n984) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[2] ( .D(\fpu_add_frac_dp/n3558 ), .CLK(n1535), .Q(n985) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[1] ( .D(\fpu_add_frac_dp/n3559 ), .CLK(n1536), .Q(n986) );
DFFX1 \fpu_add_frac_dp/i_a5stg_rndadd/q_reg[0] ( .D(\fpu_add_frac_dp/n3560 ), .CLK(n1536), .Q(n987) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[63] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N66 ), .CLK(n1529), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[63] ), .QN(\fpu_add_frac_dp/n187 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[63] ( .D(
\fpu_add_frac_dp/n3561 ), .CLK(n1551), .Q(n846), .QN(
\fpu_add_frac_dp/n188 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[62] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N65 ), .CLK(n1529), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[62] ), .QN(\fpu_add_frac_dp/n189 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[62] ( .D(
\fpu_add_frac_dp/n3562 ), .CLK(n1551), .Q(n831), .QN(
\fpu_add_frac_dp/n190 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[61] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N64 ), .CLK(n1530), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[61] ), .QN(\fpu_add_frac_dp/n191 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[61] ( .D(
\fpu_add_frac_dp/n3563 ), .CLK(n1551), .Q(n832), .QN(
\fpu_add_frac_dp/n192 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[60] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N63 ), .CLK(n1528), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[60] ), .QN(\fpu_add_frac_dp/n193 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[60] ( .D(
\fpu_add_frac_dp/n3564 ), .CLK(n1550), .Q(n843), .QN(
\fpu_add_frac_dp/n194 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[59] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N62 ), .CLK(n1529), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[59] ), .QN(\fpu_add_frac_dp/n195 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[59] ( .D(
\fpu_add_frac_dp/n3565 ), .CLK(n1550), .Q(n840), .QN(
\fpu_add_frac_dp/n196 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[58] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N61 ), .CLK(n1529), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[58] ), .QN(\fpu_add_frac_dp/n197 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[58] ( .D(
\fpu_add_frac_dp/n3566 ), .CLK(n1550), .Q(n833), .QN(
\fpu_add_frac_dp/n198 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[57] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N60 ), .CLK(n1530), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[57] ), .QN(\fpu_add_frac_dp/n199 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[57] ( .D(
\fpu_add_frac_dp/n3567 ), .CLK(n1550), .Q(n834), .QN(
\fpu_add_frac_dp/n200 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[56] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N59 ), .CLK(n1530), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[56] ), .QN(\fpu_add_frac_dp/n201 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[56] ( .D(
\fpu_add_frac_dp/n3568 ), .CLK(n1550), .Q(n844), .QN(
\fpu_add_frac_dp/n202 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[55] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N58 ), .CLK(n1536), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[55] ), .QN(\fpu_add_frac_dp/n203 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[55] ( .D(
\fpu_add_frac_dp/n3569 ), .CLK(n1550), .Q(n841), .QN(
\fpu_add_frac_dp/n204 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[54] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N57 ), .CLK(n1537), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[54] ), .QN(\fpu_add_frac_dp/n205 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[54] ( .D(
\fpu_add_frac_dp/n3570 ), .CLK(n1550), .Q(n835), .QN(
\fpu_add_frac_dp/n206 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[53] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N56 ), .CLK(n1531), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[53] ), .QN(\fpu_add_frac_dp/n207 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[53] ( .D(
\fpu_add_frac_dp/n3571 ), .CLK(n1550), .Q(n836), .QN(
\fpu_add_frac_dp/n208 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[52] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N55 ), .CLK(n1531), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[52] ), .QN(\fpu_add_frac_dp/n209 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[52] ( .D(
\fpu_add_frac_dp/n3572 ), .CLK(n1550), .Q(n845), .QN(
\fpu_add_frac_dp/n210 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[51] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N54 ), .CLK(n1531), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[51] ), .QN(\fpu_add_frac_dp/n211 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[51] ( .D(
\fpu_add_frac_dp/n3573 ), .CLK(n1550), .Q(n842), .QN(
\fpu_add_frac_dp/n212 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[50] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N53 ), .CLK(n1531), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[50] ), .QN(\fpu_add_frac_dp/n213 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[50] ( .D(
\fpu_add_frac_dp/n3574 ), .CLK(n1550), .Q(n837), .QN(
\fpu_add_frac_dp/n214 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[49] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N52 ), .CLK(n1526), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[49] ), .QN(\fpu_add_frac_dp/n215 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[49] ( .D(
\fpu_add_frac_dp/n3575 ), .CLK(n1550), .Q(n838), .QN(
\fpu_add_frac_dp/n216 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[48] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N51 ), .CLK(n1525), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[48] ), .QN(\fpu_add_frac_dp/n217 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[48] ( .D(
\fpu_add_frac_dp/n3576 ), .CLK(n1550), .Q(n914), .QN(
\fpu_add_frac_dp/n218 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[47] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N50 ), .CLK(n1525), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[47] ), .QN(\fpu_add_frac_dp/n219 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[47] ( .D(
\fpu_add_frac_dp/n3577 ), .CLK(n1550), .Q(n451), .QN(
\fpu_add_frac_dp/n220 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[46] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N49 ), .CLK(n1525), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[46] ), .QN(\fpu_add_frac_dp/n221 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[46] ( .D(
\fpu_add_frac_dp/n3578 ), .CLK(n1549), .Q(n456), .QN(
\fpu_add_frac_dp/n222 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[45] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N48 ), .CLK(n1525), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[45] ), .QN(\fpu_add_frac_dp/n223 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[45] ( .D(
\fpu_add_frac_dp/n3579 ), .CLK(n1549), .Q(n457), .QN(
\fpu_add_frac_dp/n224 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[44] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N47 ), .CLK(n1525), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[44] ), .QN(\fpu_add_frac_dp/n225 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[44] ( .D(
\fpu_add_frac_dp/n3580 ), .CLK(n1549), .Q(n464), .QN(
\fpu_add_frac_dp/n226 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[43] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N46 ), .CLK(n1524), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[43] ), .QN(\fpu_add_frac_dp/n227 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[43] ( .D(
\fpu_add_frac_dp/n3581 ), .CLK(n1549), .Q(n461), .QN(
\fpu_add_frac_dp/n228 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[42] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N45 ), .CLK(n1524), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[42] ), .QN(\fpu_add_frac_dp/n229 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[42] ( .D(
\fpu_add_frac_dp/n3582 ), .CLK(n1549), .Q(n766), .QN(
\fpu_add_frac_dp/n230 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[41] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N44 ), .CLK(n1524), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[41] ), .QN(\fpu_add_frac_dp/n231 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[41] ( .D(
\fpu_add_frac_dp/n3583 ), .CLK(n1549), .Q(n462), .QN(
\fpu_add_frac_dp/n232 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[40] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N43 ), .CLK(n1524), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[40] ), .QN(\fpu_add_frac_dp/n233 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[40] ( .D(
\fpu_add_frac_dp/n3584 ), .CLK(n1549), .Q(n458), .QN(
\fpu_add_frac_dp/n234 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[39] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N42 ), .CLK(n1524), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[39] ), .QN(\fpu_add_frac_dp/n235 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[39] ( .D(
\fpu_add_frac_dp/n3585 ), .CLK(n1549), .Q(n459), .QN(
\fpu_add_frac_dp/n236 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[38] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N41 ), .CLK(n1523), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[38] ), .QN(\fpu_add_frac_dp/n237 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[38] ( .D(
\fpu_add_frac_dp/n3586 ), .CLK(n1549), .Q(n767), .QN(
\fpu_add_frac_dp/n238 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[37] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N40 ), .CLK(n1523), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[37] ), .QN(\fpu_add_frac_dp/n239 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[37] ( .D(
\fpu_add_frac_dp/n3587 ), .CLK(n1549), .Q(n765), .QN(
\fpu_add_frac_dp/n240 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[36] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N39 ), .CLK(n1523), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[36] ), .QN(\fpu_add_frac_dp/n241 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[36] ( .D(
\fpu_add_frac_dp/n3588 ), .CLK(n1549), .Q(n742), .QN(
\fpu_add_frac_dp/n242 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[35] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N38 ), .CLK(n1523), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[35] ), .QN(\fpu_add_frac_dp/n243 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[35] ( .D(
\fpu_add_frac_dp/n3589 ), .CLK(n1549), .Q(n741), .QN(
\fpu_add_frac_dp/n244 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[34] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N37 ), .CLK(n1522), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[34] ), .QN(\fpu_add_frac_dp/n245 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[34] ( .D(
\fpu_add_frac_dp/n3590 ), .CLK(n1549), .Q(n739), .QN(
\fpu_add_frac_dp/n246 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[33] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N36 ), .CLK(n1522), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[33] ), .QN(\fpu_add_frac_dp/n247 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[33] ( .D(
\fpu_add_frac_dp/n3591 ), .CLK(n1549), .Q(n740), .QN(
\fpu_add_frac_dp/n248 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[32] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N35 ), .CLK(n1521), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[32] ), .QN(\fpu_add_frac_dp/n249 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[32] ( .D(
\fpu_add_frac_dp/n3592 ), .CLK(n1548), .Q(n1090), .QN(
\fpu_add_frac_dp/n250 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[31] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N34 ), .CLK(n1521), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[31] ), .QN(\fpu_add_frac_dp/n251 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[31] ( .D(
\fpu_add_frac_dp/n3593 ), .CLK(n1548), .Q(n729), .QN(
\fpu_add_frac_dp/n252 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[30] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N33 ), .CLK(n1521), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[30] ), .QN(\fpu_add_frac_dp/n253 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[30] ( .D(
\fpu_add_frac_dp/n3594 ), .CLK(n1548), .Q(n726), .QN(
\fpu_add_frac_dp/n254 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[29] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N32 ), .CLK(n1521), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[29] ), .QN(\fpu_add_frac_dp/n255 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[29] ( .D(
\fpu_add_frac_dp/n3595 ), .CLK(n1548), .Q(n727), .QN(
\fpu_add_frac_dp/n256 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[28] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N31 ), .CLK(n1520), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[28] ), .QN(\fpu_add_frac_dp/n257 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[28] ( .D(
\fpu_add_frac_dp/n3596 ), .CLK(n1548), .Q(n751), .QN(
\fpu_add_frac_dp/n258 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[27] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N30 ), .CLK(n1520), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[27] ), .QN(\fpu_add_frac_dp/n259 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[27] ( .D(
\fpu_add_frac_dp/n3597 ), .CLK(n1548), .Q(n749), .QN(
\fpu_add_frac_dp/n260 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[26] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N29 ), .CLK(n1520), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[26] ), .QN(\fpu_add_frac_dp/n261 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[26] ( .D(
\fpu_add_frac_dp/n3598 ), .CLK(n1548), .Q(n448), .QN(
\fpu_add_frac_dp/n262 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[25] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N28 ), .CLK(n1520), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[25] ), .QN(\fpu_add_frac_dp/n263 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[25] ( .D(
\fpu_add_frac_dp/n3599 ), .CLK(n1548), .Q(n748), .QN(
\fpu_add_frac_dp/n264 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[24] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N27 ), .CLK(n1537), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[24] ), .QN(\fpu_add_frac_dp/n265 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[24] ( .D(
\fpu_add_frac_dp/n3600 ), .CLK(n1548), .Q(n752), .QN(
\fpu_add_frac_dp/n266 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[23] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N26 ), .CLK(n1538), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[23] ), .QN(\fpu_add_frac_dp/n267 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[23] ( .D(
\fpu_add_frac_dp/n3601 ), .CLK(n1548), .Q(n750), .QN(
\fpu_add_frac_dp/n268 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[22] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N25 ), .CLK(n1518), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[22] ), .QN(\fpu_add_frac_dp/n269 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[22] ( .D(
\fpu_add_frac_dp/n3602 ), .CLK(n1548), .Q(n449), .QN(
\fpu_add_frac_dp/n270 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[21] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N24 ), .CLK(n1519), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[21] ), .QN(\fpu_add_frac_dp/n271 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[21] ( .D(
\fpu_add_frac_dp/n3603 ), .CLK(n1548), .Q(n450), .QN(
\fpu_add_frac_dp/n272 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[20] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N23 ), .CLK(n1519), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[20] ), .QN(\fpu_add_frac_dp/n273 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[20] ( .D(
\fpu_add_frac_dp/n3604 ), .CLK(n1552), .Q(n432), .QN(
\fpu_add_frac_dp/n274 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[19] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N22 ), .CLK(n1519), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[19] ), .QN(\fpu_add_frac_dp/n275 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[19] ( .D(
\fpu_add_frac_dp/n3605 ), .CLK(n1528), .Q(n431), .QN(
\fpu_add_frac_dp/n276 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[18] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N21 ), .CLK(n1519), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[18] ), .QN(\fpu_add_frac_dp/n277 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[18] ( .D(
\fpu_add_frac_dp/n3606 ), .CLK(n1528), .Q(n429), .QN(
\fpu_add_frac_dp/n278 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[17] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N20 ), .CLK(n1537), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[17] ), .QN(\fpu_add_frac_dp/n279 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[17] ( .D(
\fpu_add_frac_dp/n3607 ), .CLK(n1528), .Q(n430), .QN(
\fpu_add_frac_dp/n280 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[16] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N19 ), .CLK(n1537), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[16] ), .QN(\fpu_add_frac_dp/n281 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[16] ( .D(
\fpu_add_frac_dp/n3608 ), .CLK(n1528), .Q(n756), .QN(
\fpu_add_frac_dp/n282 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[15] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N18 ), .CLK(n1534), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[15] ), .QN(\fpu_add_frac_dp/n283 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[15] ( .D(
\fpu_add_frac_dp/n3609 ), .CLK(n1528), .Q(n130), .QN(
\fpu_add_frac_dp/n2417 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[14] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N17 ), .CLK(n1535), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[14] ), .QN(\fpu_add_frac_dp/n285 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[14] ( .D(
\fpu_add_frac_dp/n3610 ), .CLK(n1528), .Q(n45), .QN(
\fpu_add_frac_dp/n2291 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[13] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N16 ), .CLK(n1535), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[13] ), .QN(\fpu_add_frac_dp/n287 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[13] ( .D(
\fpu_add_frac_dp/n3611 ), .CLK(n1528), .Q(n257), .QN(
\fpu_add_frac_dp/n2358 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[12] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N15 ), .CLK(n1536), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[12] ), .QN(\fpu_add_frac_dp/n289 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[12] ( .D(
\fpu_add_frac_dp/n3612 ), .CLK(n1528), .Q(n107), .QN(
\fpu_add_frac_dp/n2292 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[11] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N14 ), .CLK(n1536), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[11] ), .QN(\fpu_add_frac_dp/n291 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[11] ( .D(
\fpu_add_frac_dp/n3613 ), .CLK(n1527), .Q(n264), .QN(
\fpu_add_frac_dp/n2360 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[10] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N13 ), .CLK(n1519), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[10] ), .QN(\fpu_add_frac_dp/n293 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[10] ( .D(
\fpu_add_frac_dp/n3614 ), .CLK(n1527), .Q(n119), .QN(
\fpu_add_frac_dp/n2293 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[9] ( .D(
\fpu_add_frac_dp/n1566 ), .RSTB(\fpu_add_frac_dp/n1509 ), .SETB(
\fpu_add_frac_dp/n1005 ), .CLK(n1476), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[9] ), .QN(\fpu_add_frac_dp/n295 )
);
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[9] ( .D(
\fpu_add_frac_dp/n3615 ), .CLK(n1527), .Q(n285), .QN(
\fpu_add_frac_dp/n2410 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[8] ( .D(
\fpu_add_frac_dp/n1567 ), .RSTB(\fpu_add_frac_dp/n1509 ), .SETB(
\fpu_add_frac_dp/n1006 ), .CLK(n1476), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[8] ), .QN(\fpu_add_frac_dp/n297 )
);
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[8] ( .D(
\fpu_add_frac_dp/n3616 ), .CLK(n1527), .Q(n123), .QN(
\fpu_add_frac_dp/n2346 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[7] ( .D(
\fpu_add_frac_dp/n1568 ), .RSTB(\fpu_add_frac_dp/n1509 ), .SETB(
\fpu_add_frac_dp/n1007 ), .CLK(n1478), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[7] ), .QN(\fpu_add_frac_dp/n299 )
);
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[7] ( .D(
\fpu_add_frac_dp/n3617 ), .CLK(n1527), .Q(n286), .QN(
\fpu_add_frac_dp/n2413 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[6] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N9 ), .CLK(n1535), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[6] ), .QN(\fpu_add_frac_dp/n301 )
);
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[6] ( .D(
\fpu_add_frac_dp/n3618 ), .CLK(n1527), .Q(n124), .QN(
\fpu_add_frac_dp/n2349 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[5] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N8 ), .CLK(n1535), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[5] ), .QN(\fpu_add_frac_dp/n303 )
);
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[5] ( .D(
\fpu_add_frac_dp/n3619 ), .CLK(n1527), .Q(n51), .QN(
\fpu_add_frac_dp/n2294 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[4] ( .D(
\fpu_add_frac_dp/n1571 ), .RSTB(\fpu_add_frac_dp/n1509 ), .SETB(
\fpu_add_frac_dp/n1001 ), .CLK(n1478), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[4] ), .QN(\fpu_add_frac_dp/n305 )
);
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[4] ( .D(
\fpu_add_frac_dp/n3620 ), .CLK(n1527), .Q(n284), .QN(
\fpu_add_frac_dp/n2414 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[3] ( .D(
\fpu_add_frac_dp/n1572 ), .RSTB(\fpu_add_frac_dp/n1509 ), .SETB(
\fpu_add_frac_dp/n1002 ), .CLK(n1477), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[3] ), .QN(\fpu_add_frac_dp/n307 )
);
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[3] ( .D(
\fpu_add_frac_dp/n3621 ), .CLK(n1527), .Q(n50), .QN(
\fpu_add_frac_dp/n2347 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[2] ( .D(
\fpu_add_frac_dp/n1573 ), .RSTB(\fpu_add_frac_dp/n1509 ), .SETB(
\fpu_add_frac_dp/n1003 ), .CLK(n1477), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[2] ), .QN(\fpu_add_frac_dp/n309 )
);
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[2] ( .D(
\fpu_add_frac_dp/n3622 ), .CLK(n1527), .Q(n115), .QN(
\fpu_add_frac_dp/n2412 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[1] ( .D(
\fpu_add_frac_dp/n1574 ), .RSTB(\fpu_add_frac_dp/n1509 ), .SETB(
\fpu_add_frac_dp/n1004 ), .CLK(n1477), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre2[1] ), .QN(\fpu_add_frac_dp/n311 )
);
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[1] ( .D(
\fpu_add_frac_dp/n3623 ), .CLK(n1527), .Q(n48), .QN(
\fpu_add_frac_dp/n2348 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/q_reg[0] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N3 ), .CLK(n1522), .Q(n956),
.QN(\fpu_add_frac_dp/n313 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_shl_data/q_reg[0] ( .D(
\fpu_add_frac_dp/n3624 ), .CLK(n1527), .Q(n219), .QN(
\fpu_add_frac_dp/n2401 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[63] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N66 ), .CLK(n1541), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[63] ), .QN(\fpu_add_frac_dp/n315 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[62] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N65 ), .CLK(n1540), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[62] ), .QN(\fpu_add_frac_dp/n316 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[61] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N64 ), .CLK(n1540), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[61] ), .QN(\fpu_add_frac_dp/n317 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[60] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N63 ), .CLK(n1540), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[60] ), .QN(\fpu_add_frac_dp/n318 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[59] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N62 ), .CLK(n1540), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[59] ), .QN(\fpu_add_frac_dp/n319 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[58] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N61 ), .CLK(n1540), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[58] ), .QN(\fpu_add_frac_dp/n320 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[57] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N60 ), .CLK(n1540), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[57] ), .QN(\fpu_add_frac_dp/n321 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[56] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N59 ), .CLK(n1540), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[56] ), .QN(\fpu_add_frac_dp/n322 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[55] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N58 ), .CLK(n1540), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[55] ), .QN(\fpu_add_frac_dp/n323 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[54] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N57 ), .CLK(n1540), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[54] ), .QN(\fpu_add_frac_dp/n324 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[53] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N56 ), .CLK(n1540), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[53] ), .QN(\fpu_add_frac_dp/n325 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[52] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N55 ), .CLK(n1540), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[52] ), .QN(\fpu_add_frac_dp/n326 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[51] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N54 ), .CLK(n1539), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[51] ), .QN(\fpu_add_frac_dp/n327 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[50] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N53 ), .CLK(n1539), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[50] ), .QN(\fpu_add_frac_dp/n328 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[49] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N52 ), .CLK(n1539), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[49] ), .QN(\fpu_add_frac_dp/n329 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[48] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N51 ), .CLK(n1539), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[48] ), .QN(\fpu_add_frac_dp/n330 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[47] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N50 ), .CLK(n1539), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[47] ), .QN(\fpu_add_frac_dp/n331 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[46] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N49 ), .CLK(n1539), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[46] ), .QN(\fpu_add_frac_dp/n332 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[45] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N48 ), .CLK(n1539), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[45] ), .QN(\fpu_add_frac_dp/n333 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[44] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N47 ), .CLK(n1539), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[44] ), .QN(\fpu_add_frac_dp/n334 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[43] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N46 ), .CLK(n1539), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[43] ), .QN(\fpu_add_frac_dp/n335 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[42] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N45 ), .CLK(n1539), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[42] ), .QN(\fpu_add_frac_dp/n336 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[41] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N44 ), .CLK(n1539), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[41] ), .QN(\fpu_add_frac_dp/n337 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[40] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N43 ), .CLK(n1539), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[40] ), .QN(\fpu_add_frac_dp/n338 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[39] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N42 ), .CLK(n1539), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[39] ), .QN(\fpu_add_frac_dp/n339 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[38] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N41 ), .CLK(n1539), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[38] ), .QN(\fpu_add_frac_dp/n340 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[37] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N40 ), .CLK(n1538), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[37] ), .QN(\fpu_add_frac_dp/n341 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[36] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N39 ), .CLK(n1538), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[36] ), .QN(\fpu_add_frac_dp/n342 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[35] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N38 ), .CLK(n1538), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[35] ), .QN(\fpu_add_frac_dp/n343 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[34] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N37 ), .CLK(n1538), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[34] ), .QN(\fpu_add_frac_dp/n344 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[33] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N36 ), .CLK(n1538), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[33] ), .QN(\fpu_add_frac_dp/n345 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[32] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N35 ), .CLK(n1538), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[32] ), .QN(\fpu_add_frac_dp/n346 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[31] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N34 ), .CLK(n1538), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[31] ), .QN(\fpu_add_frac_dp/n347 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[30] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N33 ), .CLK(n1538), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[30] ), .QN(\fpu_add_frac_dp/n348 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[29] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N32 ), .CLK(n1538), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[29] ), .QN(\fpu_add_frac_dp/n349 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[28] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N31 ), .CLK(n1543), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[28] ), .QN(\fpu_add_frac_dp/n350 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[27] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N30 ), .CLK(n1557), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[27] ), .QN(\fpu_add_frac_dp/n351 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[26] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N29 ), .CLK(n1557), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[26] ), .QN(\fpu_add_frac_dp/n352 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[25] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N28 ), .CLK(n1557), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[25] ), .QN(\fpu_add_frac_dp/n353 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[24] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N27 ), .CLK(n1557), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[24] ), .QN(\fpu_add_frac_dp/n354 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[23] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N26 ), .CLK(n1557), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[23] ), .QN(\fpu_add_frac_dp/n355 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[22] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N25 ), .CLK(n1557), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[22] ), .QN(\fpu_add_frac_dp/n356 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[21] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N24 ), .CLK(n1557), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[21] ), .QN(\fpu_add_frac_dp/n357 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[20] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N23 ), .CLK(n1557), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[20] ), .QN(\fpu_add_frac_dp/n358 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[19] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N22 ), .CLK(n1557), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[19] ), .QN(\fpu_add_frac_dp/n359 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[18] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N21 ), .CLK(n1557), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[18] ), .QN(\fpu_add_frac_dp/n360 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[17] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N20 ), .CLK(n1557), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[17] ), .QN(\fpu_add_frac_dp/n361 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[16] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N19 ), .CLK(n1557), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[16] ), .QN(\fpu_add_frac_dp/n362 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[15] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N18 ), .CLK(n1556), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[15] ), .QN(\fpu_add_frac_dp/n363 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[14] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N17 ), .CLK(n1556), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[14] ), .QN(\fpu_add_frac_dp/n364 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[13] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N16 ), .CLK(n1556), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[13] ), .QN(\fpu_add_frac_dp/n365 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[12] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N15 ), .CLK(n1556), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[12] ), .QN(\fpu_add_frac_dp/n366 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[11] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N14 ), .CLK(n1556), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[11] ), .QN(\fpu_add_frac_dp/n367 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[10] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N13 ), .CLK(n1556), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[10] ), .QN(\fpu_add_frac_dp/n368 ) );
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[9] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N12 ), .CLK(n1556), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[9] ), .QN(\fpu_add_frac_dp/n369 )
);
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[8] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N11 ), .CLK(n1556), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[8] ), .QN(\fpu_add_frac_dp/n370 )
);
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[7] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N10 ), .CLK(n1556), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[7] ), .QN(\fpu_add_frac_dp/n371 )
);
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[6] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N9 ), .CLK(n1556), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[6] ), .QN(\fpu_add_frac_dp/n372 )
);
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[5] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N8 ), .CLK(n1556), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[5] ), .QN(\fpu_add_frac_dp/n373 )
);
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[4] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N7 ), .CLK(n1556), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[4] ), .QN(\fpu_add_frac_dp/n374 )
);
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[3] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N6 ), .CLK(n1556), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[3] ), .QN(\fpu_add_frac_dp/n375 )
);
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[2] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N5 ), .CLK(n1556), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[2] ), .QN(\fpu_add_frac_dp/n376 )
);
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/q_reg[1] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N4 ), .CLK(n1540), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre3[1] ), .QN(\fpu_add_frac_dp/n377 )
);
DFFX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[63] ( .D(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .CLK(n1540), .Q(
\fpu_add_frac_dp/a4stg_rnd_frac_pre1[63] ), .QN(\fpu_add_frac_dp/n378 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[62] ( .D(
\fpu_add_frac_dp/n1515 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1479),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[62] ), .QN(
\fpu_add_frac_dp/n380 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[61] ( .D(
\fpu_add_frac_dp/n1516 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1479),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[61] ), .QN(
\fpu_add_frac_dp/n382 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[60] ( .D(
\fpu_add_frac_dp/n1517 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1478),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[60] ), .QN(
\fpu_add_frac_dp/n384 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[59] ( .D(
\fpu_add_frac_dp/n1518 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1478),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[59] ), .QN(
\fpu_add_frac_dp/n386 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[58] ( .D(
\fpu_add_frac_dp/n1519 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1478),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[58] ), .QN(
\fpu_add_frac_dp/n388 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[57] ( .D(
\fpu_add_frac_dp/n1520 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1478),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[57] ), .QN(
\fpu_add_frac_dp/n390 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[56] ( .D(
\fpu_add_frac_dp/n1521 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1477),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[56] ), .QN(
\fpu_add_frac_dp/n392 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[55] ( .D(
\fpu_add_frac_dp/n1522 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1477),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[55] ), .QN(
\fpu_add_frac_dp/n394 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[54] ( .D(
\fpu_add_frac_dp/n1523 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1477),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[54] ), .QN(
\fpu_add_frac_dp/n396 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[53] ( .D(
\fpu_add_frac_dp/n1524 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1477),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[53] ), .QN(
\fpu_add_frac_dp/n398 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[52] ( .D(
\fpu_add_frac_dp/n1525 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1476),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[52] ), .QN(
\fpu_add_frac_dp/n400 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[51] ( .D(
\fpu_add_frac_dp/n1526 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1476),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[51] ), .QN(
\fpu_add_frac_dp/n402 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[50] ( .D(
\fpu_add_frac_dp/n1527 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1477),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[50] ), .QN(
\fpu_add_frac_dp/n404 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[49] ( .D(
\fpu_add_frac_dp/n1528 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1477),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[49] ), .QN(
\fpu_add_frac_dp/n406 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[48] ( .D(
\fpu_add_frac_dp/n1529 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1476),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[48] ), .QN(
\fpu_add_frac_dp/n408 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[47] ( .D(
\fpu_add_frac_dp/n1530 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1476),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[47] ), .QN(
\fpu_add_frac_dp/n410 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[46] ( .D(
\fpu_add_frac_dp/n1531 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1476),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[46] ), .QN(
\fpu_add_frac_dp/n412 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[45] ( .D(
\fpu_add_frac_dp/n1532 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1476),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[45] ), .QN(
\fpu_add_frac_dp/n414 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[44] ( .D(
\fpu_add_frac_dp/n1533 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1475),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[44] ), .QN(
\fpu_add_frac_dp/n416 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[43] ( .D(
\fpu_add_frac_dp/n1534 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1476),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[43] ), .QN(
\fpu_add_frac_dp/n418 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[42] ( .D(
\fpu_add_frac_dp/n1535 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1475),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[42] ), .QN(
\fpu_add_frac_dp/n420 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[41] ( .D(
\fpu_add_frac_dp/n1536 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1475),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[41] ), .QN(
\fpu_add_frac_dp/n422 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[40] ( .D(
\fpu_add_frac_dp/n1537 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1475),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[40] ), .QN(
\fpu_add_frac_dp/n424 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[39] ( .D(
\fpu_add_frac_dp/n1538 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1475),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[39] ), .QN(
\fpu_add_frac_dp/n426 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[38] ( .D(
\fpu_add_frac_dp/n1539 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1475),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[38] ), .QN(
\fpu_add_frac_dp/n428 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[37] ( .D(
\fpu_add_frac_dp/n1540 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1475),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[37] ), .QN(
\fpu_add_frac_dp/n430 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[36] ( .D(
\fpu_add_frac_dp/n1541 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1475),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[36] ), .QN(
\fpu_add_frac_dp/n432 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[35] ( .D(
\fpu_add_frac_dp/n1542 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1474),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[35] ), .QN(
\fpu_add_frac_dp/n434 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[34] ( .D(
\fpu_add_frac_dp/n1543 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1474),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[34] ), .QN(
\fpu_add_frac_dp/n436 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[33] ( .D(
\fpu_add_frac_dp/n1544 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1474),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[33] ), .QN(
\fpu_add_frac_dp/n438 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[32] ( .D(
\fpu_add_frac_dp/n1545 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1474),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[32] ), .QN(
\fpu_add_frac_dp/n440 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[31] ( .D(
\fpu_add_frac_dp/n1546 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1474),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[31] ), .QN(
\fpu_add_frac_dp/n442 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[30] ( .D(
\fpu_add_frac_dp/n1547 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1474),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[30] ), .QN(
\fpu_add_frac_dp/n444 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[29] ( .D(
\fpu_add_frac_dp/n1548 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1474),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[29] ), .QN(
\fpu_add_frac_dp/n446 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[28] ( .D(
\fpu_add_frac_dp/n1549 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1474),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[28] ), .QN(
\fpu_add_frac_dp/n448 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[27] ( .D(
\fpu_add_frac_dp/n1550 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1474),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[27] ), .QN(
\fpu_add_frac_dp/n450 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[26] ( .D(
\fpu_add_frac_dp/n1551 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1474),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[26] ), .QN(
\fpu_add_frac_dp/n452 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[25] ( .D(
\fpu_add_frac_dp/n1552 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1474),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[25] ), .QN(
\fpu_add_frac_dp/n454 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[24] ( .D(
\fpu_add_frac_dp/n1553 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1474),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[24] ), .QN(
\fpu_add_frac_dp/n456 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[23] ( .D(
\fpu_add_frac_dp/n1554 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1475),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[23] ), .QN(
\fpu_add_frac_dp/n458 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[22] ( .D(
\fpu_add_frac_dp/n1555 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1475),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[22] ), .QN(
\fpu_add_frac_dp/n460 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[21] ( .D(
\fpu_add_frac_dp/n1556 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1475),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[21] ), .QN(
\fpu_add_frac_dp/n462 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[20] ( .D(
\fpu_add_frac_dp/n1557 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1475),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[20] ), .QN(
\fpu_add_frac_dp/n464 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[19] ( .D(
\fpu_add_frac_dp/n1558 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1476),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[19] ), .QN(
\fpu_add_frac_dp/n466 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[18] ( .D(
\fpu_add_frac_dp/n1559 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1476),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[18] ), .QN(
\fpu_add_frac_dp/n468 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[17] ( .D(
\fpu_add_frac_dp/n1560 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1477),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[17] ), .QN(
\fpu_add_frac_dp/n470 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[16] ( .D(
\fpu_add_frac_dp/n1561 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1478),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[16] ), .QN(
\fpu_add_frac_dp/n472 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[15] ( .D(
\fpu_add_frac_dp/n1562 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1477),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[15] ), .QN(
\fpu_add_frac_dp/n474 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[14] ( .D(
\fpu_add_frac_dp/n1563 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1478),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[14] ), .QN(
\fpu_add_frac_dp/n476 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[13] ( .D(
\fpu_add_frac_dp/n1564 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1476),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[13] ), .QN(
\fpu_add_frac_dp/n478 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[12] ( .D(
\fpu_add_frac_dp/n1565 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1478),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[12] ), .QN(
\fpu_add_frac_dp/n480 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[11] ( .D(
\fpu_add_frac_dp/n1566 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1479),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[11] ), .QN(
\fpu_add_frac_dp/n482 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[10] ( .D(
\fpu_add_frac_dp/n1567 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1478),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[10] ), .QN(
\fpu_add_frac_dp/n484 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[9] ( .D(
\fpu_add_frac_dp/n1568 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1478),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[9] ), .QN(
\fpu_add_frac_dp/n486 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[8] ( .D(
\fpu_add_frac_dp/n1569 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1479),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[8] ), .QN(
\fpu_add_frac_dp/n488 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[7] ( .D(
\fpu_add_frac_dp/n1570 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1479),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[7] ), .QN(
\fpu_add_frac_dp/n490 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[6] ( .D(
\fpu_add_frac_dp/n1571 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1477),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[6] ), .QN(
\fpu_add_frac_dp/n492 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[5] ( .D(
\fpu_add_frac_dp/n1572 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1479),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[5] ), .QN(
\fpu_add_frac_dp/n494 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[4] ( .D(
\fpu_add_frac_dp/n1573 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1479),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[4] ), .QN(
\fpu_add_frac_dp/n496 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[3] ( .D(
\fpu_add_frac_dp/n1574 ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1479),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[3] ), .QN(
\fpu_add_frac_dp/n498 ) );
DFFSSRX1 \fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/q_reg[2] ( .D(
\fpu_add_frac_dp/a3stg_fracadd[0] ), .RSTB(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ), .SETB(1'b1), .CLK(n1478),
.Q(\fpu_add_frac_dp/a4stg_rnd_frac_pre1[2] ), .QN(
\fpu_add_frac_dp/n500 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[7] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N10 ), .CLK(n1545), .Q(n413), .QN(
\fpu_add_frac_dp/n501 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[8] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N11 ), .CLK(n1545), .Q(n412), .QN(
\fpu_add_frac_dp/n502 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[1] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N4 ), .CLK(n1543), .Q(n419), .QN(
\fpu_add_frac_dp/n503 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[2] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N5 ), .CLK(n1542), .Q(n418), .QN(
\fpu_add_frac_dp/n504 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[3] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N6 ), .CLK(n1541), .Q(n417), .QN(
\fpu_add_frac_dp/n505 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[4] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N7 ), .CLK(n1541), .Q(n416), .QN(
\fpu_add_frac_dp/n506 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[6] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N9 ), .CLK(n1541), .Q(n414), .QN(
\fpu_add_frac_dp/n507 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[5] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N8 ), .CLK(n1541), .Q(n415), .QN(
\fpu_add_frac_dp/n508 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[0] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N3 ), .CLK(n1544), .Q(n139), .QN(
\fpu_add_frac_dp/n509 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[4] ( .D(
\fpu_add_frac_dp/n3735 ), .CLK(n1481), .Q(n1264), .QN(
\fpu_add_frac_dp/n510 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[9] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N12 ), .CLK(n1545), .Q(n411), .QN(
\fpu_add_frac_dp/n511 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[10] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N13 ), .CLK(n1545), .Q(n410), .QN(
\fpu_add_frac_dp/n512 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[63] ( .D(
\fpu_add_frac_dp/n3738 ), .CLK(n1510), .Q(n1219), .QN(
\fpu_add_frac_dp/n513 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[11] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N14 ), .CLK(n1545), .Q(n409), .QN(
\fpu_add_frac_dp/n514 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[5] ( .D(
\fpu_add_frac_dp/n3734 ), .CLK(n1481), .Q(n1302), .QN(
\fpu_add_frac_dp/n515 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[12] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N15 ), .CLK(n1545), .Q(n408), .QN(
\fpu_add_frac_dp/n516 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[13] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N16 ), .CLK(n1545), .Q(n407), .QN(
\fpu_add_frac_dp/n517 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[14] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N17 ), .CLK(n1545), .Q(n406), .QN(
\fpu_add_frac_dp/n518 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[15] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N18 ), .CLK(n1545), .Q(n405), .QN(
\fpu_add_frac_dp/n519 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[16] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N19 ), .CLK(n1545), .Q(n404), .QN(
\fpu_add_frac_dp/n520 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[17] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N20 ), .CLK(n1545), .Q(n403), .QN(
\fpu_add_frac_dp/n521 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[18] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N21 ), .CLK(n1544), .Q(n402), .QN(
\fpu_add_frac_dp/n522 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[19] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N22 ), .CLK(n1544), .Q(n401), .QN(
\fpu_add_frac_dp/n523 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[20] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N23 ), .CLK(n1544), .Q(n400), .QN(
\fpu_add_frac_dp/n524 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[21] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N24 ), .CLK(n1544), .Q(n399), .QN(
\fpu_add_frac_dp/n525 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[22] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N25 ), .CLK(n1544), .Q(n398), .QN(
\fpu_add_frac_dp/n526 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[23] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N26 ), .CLK(n1544), .Q(n397), .QN(
\fpu_add_frac_dp/n527 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[62] ( .D(
\fpu_add_frac_dp/n3625 ), .CLK(n1512), .Q(n20), .QN(
\fpu_add_frac_dp/n528 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[24] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N27 ), .CLK(n1544), .Q(n396), .QN(
\fpu_add_frac_dp/n529 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[25] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N28 ), .CLK(n1544), .Q(n395), .QN(
\fpu_add_frac_dp/n530 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[26] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N29 ), .CLK(n1544), .Q(n394), .QN(
\fpu_add_frac_dp/n531 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[27] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N30 ), .CLK(n1544), .Q(n393), .QN(
\fpu_add_frac_dp/n532 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[28] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N31 ), .CLK(n1544), .Q(n392), .QN(
\fpu_add_frac_dp/n533 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[29] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N32 ), .CLK(n1544), .Q(n391), .QN(
\fpu_add_frac_dp/n534 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[30] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N33 ), .CLK(n1544), .Q(n390), .QN(
\fpu_add_frac_dp/n535 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[31] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N34 ), .CLK(n1543), .Q(n389), .QN(
\fpu_add_frac_dp/n536 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[32] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N35 ), .CLK(n1543), .Q(n388), .QN(
\fpu_add_frac_dp/n537 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[33] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N36 ), .CLK(n1543), .Q(n387), .QN(
\fpu_add_frac_dp/n538 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[34] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N37 ), .CLK(n1543), .Q(n386), .QN(
\fpu_add_frac_dp/n539 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[35] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N38 ), .CLK(n1543), .Q(n385), .QN(
\fpu_add_frac_dp/n540 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[36] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N39 ), .CLK(n1543), .Q(n384), .QN(
\fpu_add_frac_dp/n541 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[37] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N40 ), .CLK(n1543), .Q(n383), .QN(
\fpu_add_frac_dp/n542 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[38] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N41 ), .CLK(n1543), .Q(n382), .QN(
\fpu_add_frac_dp/n543 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[39] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N42 ), .CLK(n1543), .Q(n381), .QN(
\fpu_add_frac_dp/n544 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[61] ( .D(
\fpu_add_frac_dp/n3626 ), .CLK(n1512), .Q(n118), .QN(
\fpu_add_frac_dp/n545 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[40] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N43 ), .CLK(n1543), .Q(n380), .QN(
\fpu_add_frac_dp/n546 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[41] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N44 ), .CLK(n1543), .Q(n379), .QN(
\fpu_add_frac_dp/n547 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[42] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N45 ), .CLK(n1543), .Q(n378), .QN(
\fpu_add_frac_dp/n548 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[43] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N46 ), .CLK(n1542), .Q(n377), .QN(
\fpu_add_frac_dp/n549 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[44] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N47 ), .CLK(n1542), .Q(n376), .QN(
\fpu_add_frac_dp/n550 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[45] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N48 ), .CLK(n1542), .Q(n375), .QN(
\fpu_add_frac_dp/n551 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[46] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N49 ), .CLK(n1542), .Q(n374), .QN(
\fpu_add_frac_dp/n552 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[47] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N50 ), .CLK(n1542), .Q(n373), .QN(
\fpu_add_frac_dp/n553 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[48] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N51 ), .CLK(n1542), .Q(n372), .QN(
\fpu_add_frac_dp/n554 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[49] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N52 ), .CLK(n1542), .Q(n371), .QN(
\fpu_add_frac_dp/n555 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[50] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N53 ), .CLK(n1542), .Q(n370), .QN(
\fpu_add_frac_dp/n556 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[51] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N54 ), .CLK(n1542), .Q(n369), .QN(
\fpu_add_frac_dp/n557 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[52] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N55 ), .CLK(n1542), .Q(n368), .QN(
\fpu_add_frac_dp/n558 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[53] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N56 ), .CLK(n1542), .Q(n367), .QN(
\fpu_add_frac_dp/n559 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[54] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N57 ), .CLK(n1542), .Q(n366), .QN(
\fpu_add_frac_dp/n560 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[55] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N58 ), .CLK(n1542), .Q(n365), .QN(
\fpu_add_frac_dp/n561 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[56] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N59 ), .CLK(n1541), .Q(n364), .QN(
\fpu_add_frac_dp/n562 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[57] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N60 ), .CLK(n1541), .Q(n363), .QN(
\fpu_add_frac_dp/n563 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[58] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N61 ), .CLK(n1541), .Q(n362), .QN(
\fpu_add_frac_dp/n564 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[59] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N62 ), .CLK(n1541), .Q(n361), .QN(
\fpu_add_frac_dp/n565 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[60] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N63 ), .CLK(n1541), .Q(n360), .QN(
\fpu_add_frac_dp/n566 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[61] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N64 ), .CLK(n1541), .Q(n359), .QN(
\fpu_add_frac_dp/n567 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[62] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N65 ), .CLK(n1541), .Q(n753), .QN(
\fpu_add_frac_dp/n568 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac2/q_reg[63] ( .D(
\fpu_add_frac_dp/i_a3stg_frac2/N66 ), .CLK(n1541), .Q(
\fpu_add_frac_dp/a3stg_frac2[63] ), .QN(\fpu_add_frac_dp/n569 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[60] ( .D(
\fpu_add_frac_dp/n3627 ), .CLK(n1512), .Q(n1124), .QN(
\fpu_add_frac_dp/n570 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[59] ( .D(
\fpu_add_frac_dp/n3628 ), .CLK(n1512), .Q(n1222), .QN(
\fpu_add_frac_dp/n571 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[58] ( .D(
\fpu_add_frac_dp/n3629 ), .CLK(n1512), .Q(n5), .QN(
\fpu_add_frac_dp/n572 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[57] ( .D(
\fpu_add_frac_dp/n3630 ), .CLK(n1512), .Q(n47), .QN(
\fpu_add_frac_dp/n573 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[52] ( .D(
\fpu_add_frac_dp/n3631 ), .CLK(n1512), .Q(\fpu_add_frac_dp/n2382 ),
.QN(\fpu_add_frac_dp/n1391 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[51] ( .D(
\fpu_add_frac_dp/n3632 ), .CLK(n1512), .Q(
\fpu_add_frac_dp/a2stg_shr_cnt_4[3] ), .QN(\fpu_add_frac_dp/n574 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[50] ( .D(
\fpu_add_frac_dp/n3633 ), .CLK(n1512), .Q(n1126), .QN(
\fpu_add_frac_dp/n575 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[49] ( .D(
\fpu_add_frac_dp/n3634 ), .CLK(n1511), .Q(n1221), .QN(
\fpu_add_frac_dp/n576 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[48] ( .D(
\fpu_add_frac_dp/n3635 ), .CLK(n1511), .Q(n1220), .QN(
\fpu_add_frac_dp/n577 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[47] ( .D(
\fpu_add_frac_dp/n3636 ), .CLK(n1511), .Q(\fpu_add_frac_dp/n2322 ),
.QN(n580) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[46] ( .D(
\fpu_add_frac_dp/n3637 ), .CLK(n1511), .Q(\fpu_add_frac_dp/n2397 ),
.QN(\fpu_add_frac_dp/n1384 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[45] ( .D(
\fpu_add_frac_dp/n3638 ), .CLK(n1511), .Q(n581), .QN(
\fpu_add_frac_dp/n2375 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[44] ( .D(
\fpu_add_frac_dp/n3639 ), .CLK(n1511), .Q(\fpu_add_frac_dp/n2399 ),
.QN(\fpu_add_frac_dp/n1382 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[43] ( .D(
\fpu_add_frac_dp/n3640 ), .CLK(n1511), .Q(n1063) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[42] ( .D(
\fpu_add_frac_dp/n3641 ), .CLK(n1511), .Q(
\fpu_add_frac_dp/a2stg_shr_cnt[5] ), .QN(\fpu_add_frac_dp/n579 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[41] ( .D(
\fpu_add_frac_dp/n3642 ), .CLK(n1511), .Q(\fpu_add_frac_dp/n2306 ),
.QN(n624) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[40] ( .D(
\fpu_add_frac_dp/n3643 ), .CLK(n1511), .Q(n693), .QN(
\fpu_add_frac_dp/n2377 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[39] ( .D(
\fpu_add_frac_dp/n3644 ), .CLK(n1511), .Q(n755), .QN(
\fpu_add_frac_dp/n580 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[38] ( .D(
\fpu_add_frac_dp/n3645 ), .CLK(n1511), .Q(n255), .QN(
\fpu_add_frac_dp/n2308 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[37] ( .D(
\fpu_add_frac_dp/n3646 ), .CLK(n1511), .Q(n962), .QN(
\fpu_add_frac_dp/n2448 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[36] ( .D(
\fpu_add_frac_dp/n3647 ), .CLK(n1540), .Q(n296), .QN(
\fpu_add_frac_dp/n582 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[35] ( .D(
\fpu_add_frac_dp/n3648 ), .CLK(n1511), .Q(n746), .QN(
\fpu_add_frac_dp/n583 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[34] ( .D(
\fpu_add_frac_dp/n3649 ), .CLK(n1510), .Q(n653), .QN(
\fpu_add_frac_dp/n2370 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[33] ( .D(
\fpu_add_frac_dp/n3650 ), .CLK(n1510), .Q(n311), .QN(
\fpu_add_frac_dp/n2465 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[32] ( .D(
\fpu_add_frac_dp/n3651 ), .CLK(n1510), .Q(n1145), .QN(
\fpu_add_frac_dp/n584 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[31] ( .D(
\fpu_add_frac_dp/n3652 ), .CLK(n1510), .Q(n166), .QN(
\fpu_add_frac_dp/n5641 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[30] ( .D(
\fpu_add_frac_dp/n3653 ), .CLK(n1510), .Q(n641), .QN(
\fpu_add_frac_dp/n2385 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[29] ( .D(
\fpu_add_frac_dp/n3654 ), .CLK(n1527), .Q(n1144), .QN(
\fpu_add_frac_dp/n586 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[28] ( .D(
\fpu_add_frac_dp/n3655 ), .CLK(n1527), .Q(n596), .QN(
\fpu_add_frac_dp/n2271 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[27] ( .D(
\fpu_add_frac_dp/n3656 ), .CLK(n1526), .Q(\fpu_add_frac_dp/n2320 ),
.QN(\fpu_add_frac_dp/n5634 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[25] ( .D(
\fpu_add_frac_dp/n3657 ), .CLK(n1526), .Q(
\fpu_add_frac_dp/a4stg_shl_cnt_dec54_1[1] ), .QN(
\fpu_add_frac_dp/n589 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[24] ( .D(
\fpu_add_frac_dp/n3658 ), .CLK(n1526), .Q(n14), .QN(
\fpu_add_frac_dp/n5633 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[21] ( .D(
\fpu_add_frac_dp/n3659 ), .CLK(n1526), .Q(\fpu_add_frac_dp/n2325 ),
.QN(\fpu_add_frac_dp/n5635 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[18] ( .D(
\fpu_add_frac_dp/n3660 ), .CLK(n1526), .Q(n2), .QN(
\fpu_add_frac_dp/n592 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[17] ( .D(
\fpu_add_frac_dp/n3661 ), .CLK(n1526), .Q(\a4stg_shl_cnt[5] ), .QN(
\fpu_add_frac_dp/n593 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[16] ( .D(
\fpu_add_frac_dp/n3662 ), .CLK(n1526), .Q(n762), .QN(
\fpu_add_frac_dp/n594 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[15] ( .D(
\fpu_add_frac_dp/n3663 ), .CLK(n1526), .Q(n584), .QN(
\fpu_add_frac_dp/n2307 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[14] ( .D(
\fpu_add_frac_dp/n3664 ), .CLK(n1526), .Q(n63), .QN(
\fpu_add_frac_dp/n2471 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[13] ( .D(
\fpu_add_frac_dp/n3665 ), .CLK(n1526), .Q(n582), .QN(
\fpu_add_frac_dp/n2460 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[12] ( .D(
\fpu_add_frac_dp/n3666 ), .CLK(n1526), .Q(n154), .QN(
\fpu_add_frac_dp/n2449 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[8] ( .D(
\fpu_add_frac_dp/n3731 ), .CLK(n1545), .Q(n64), .QN(
\fpu_add_frac_dp/n5614 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[7] ( .D(
\fpu_add_frac_dp/n3732 ), .CLK(n1510), .Q(\fpu_add_frac_dp/n2369 ),
.QN(\fpu_add_frac_dp/n2287 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[6] ( .D(
\fpu_add_frac_dp/n3733 ), .CLK(n1551), .Q(n1121), .QN(
\fpu_add_frac_dp/n596 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[2] ( .D(
\fpu_add_frac_dp/n3736 ), .CLK(n1510), .Q(n926), .QN(
\fpu_add_frac_dp/n2478 ) );
DFFX1 \fpu_add_frac_dp/i_astg_xtra_regs/q_reg[0] ( .D(
\fpu_add_frac_dp/n3737 ), .CLK(n1541), .Q(n852), .QN(
\fpu_add_frac_dp/n598 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[53] ( .D(
\fpu_add_frac_dp/n3739 ), .CLK(n1510), .Q(n1235), .QN(
\fpu_add_frac_dp/n599 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[52] ( .D(
\fpu_add_frac_dp/n3740 ), .CLK(n1510), .Q(n1301), .QN(
\fpu_add_frac_dp/n600 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[51] ( .D(
\fpu_add_frac_dp/n3741 ), .CLK(n1510), .Q(n1300), .QN(
\fpu_add_frac_dp/n601 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[50] ( .D(
\fpu_add_frac_dp/n3742 ), .CLK(n1510), .Q(n1263), .QN(
\fpu_add_frac_dp/n602 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[49] ( .D(
\fpu_add_frac_dp/n3743 ), .CLK(n1510), .Q(n1270), .QN(
\fpu_add_frac_dp/n603 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[48] ( .D(
\fpu_add_frac_dp/n3744 ), .CLK(n1510), .Q(n1299), .QN(
\fpu_add_frac_dp/n604 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[47] ( .D(
\fpu_add_frac_dp/n3745 ), .CLK(n1509), .Q(n1298), .QN(
\fpu_add_frac_dp/n605 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[46] ( .D(
\fpu_add_frac_dp/n3746 ), .CLK(n1509), .Q(n1262), .QN(
\fpu_add_frac_dp/n606 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[45] ( .D(
\fpu_add_frac_dp/n3747 ), .CLK(n1509), .Q(n1244), .QN(
\fpu_add_frac_dp/n607 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[44] ( .D(
\fpu_add_frac_dp/n3748 ), .CLK(n1509), .Q(n1297), .QN(
\fpu_add_frac_dp/n608 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[43] ( .D(
\fpu_add_frac_dp/n3749 ), .CLK(n1509), .Q(n1296), .QN(
\fpu_add_frac_dp/n609 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[42] ( .D(
\fpu_add_frac_dp/n3750 ), .CLK(n1509), .Q(n1261), .QN(
\fpu_add_frac_dp/n610 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[41] ( .D(
\fpu_add_frac_dp/n3751 ), .CLK(n1509), .Q(n1224), .QN(
\fpu_add_frac_dp/n611 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[40] ( .D(
\fpu_add_frac_dp/n3752 ), .CLK(n1509), .Q(n1295), .QN(
\fpu_add_frac_dp/n612 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[39] ( .D(
\fpu_add_frac_dp/n3753 ), .CLK(n1509), .Q(n1294), .QN(
\fpu_add_frac_dp/n613 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[38] ( .D(
\fpu_add_frac_dp/n3754 ), .CLK(n1509), .Q(n1260), .QN(
\fpu_add_frac_dp/n614 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[37] ( .D(
\fpu_add_frac_dp/n3755 ), .CLK(n1509), .Q(n1293), .QN(
\fpu_add_frac_dp/n615 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[36] ( .D(
\fpu_add_frac_dp/n3756 ), .CLK(n1509), .Q(n1259), .QN(
\fpu_add_frac_dp/n616 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[35] ( .D(
\fpu_add_frac_dp/n3757 ), .CLK(n1509), .Q(n1292), .QN(
\fpu_add_frac_dp/n617 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[34] ( .D(
\fpu_add_frac_dp/n3758 ), .CLK(n1509), .Q(n1258), .QN(
\fpu_add_frac_dp/n618 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[33] ( .D(
\fpu_add_frac_dp/n3759 ), .CLK(n1508), .Q(n1291), .QN(
\fpu_add_frac_dp/n619 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[32] ( .D(
\fpu_add_frac_dp/n3760 ), .CLK(n1508), .Q(n1290), .QN(
\fpu_add_frac_dp/n620 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[31] ( .D(
\fpu_add_frac_dp/n3761 ), .CLK(n1508), .Q(n1289), .QN(
\fpu_add_frac_dp/n621 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[30] ( .D(
\fpu_add_frac_dp/n3762 ), .CLK(n1508), .Q(n1257), .QN(
\fpu_add_frac_dp/n622 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[29] ( .D(
\fpu_add_frac_dp/n3763 ), .CLK(n1508), .Q(n1288), .QN(
\fpu_add_frac_dp/n623 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[28] ( .D(
\fpu_add_frac_dp/n3764 ), .CLK(n1508), .Q(n1287), .QN(
\fpu_add_frac_dp/n624 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[27] ( .D(
\fpu_add_frac_dp/n3765 ), .CLK(n1508), .Q(n1256), .QN(
\fpu_add_frac_dp/n625 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[26] ( .D(
\fpu_add_frac_dp/n3766 ), .CLK(n1508), .Q(n1286), .QN(
\fpu_add_frac_dp/n626 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[25] ( .D(
\fpu_add_frac_dp/n3767 ), .CLK(n1508), .Q(n1255), .QN(
\fpu_add_frac_dp/n627 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[24] ( .D(
\fpu_add_frac_dp/n3768 ), .CLK(n1508), .Q(n1243), .QN(
\fpu_add_frac_dp/n628 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[23] ( .D(
\fpu_add_frac_dp/n3769 ), .CLK(n1508), .Q(n1285), .QN(
\fpu_add_frac_dp/n629 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[22] ( .D(
\fpu_add_frac_dp/n3770 ), .CLK(n1508), .Q(n1254), .QN(
\fpu_add_frac_dp/n630 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[21] ( .D(
\fpu_add_frac_dp/n3771 ), .CLK(n1508), .Q(n1269), .QN(
\fpu_add_frac_dp/n631 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[20] ( .D(
\fpu_add_frac_dp/n3772 ), .CLK(n1508), .Q(n1268), .QN(
\fpu_add_frac_dp/n632 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[19] ( .D(
\fpu_add_frac_dp/n3773 ), .CLK(n1507), .Q(n1284), .QN(
\fpu_add_frac_dp/n633 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[18] ( .D(
\fpu_add_frac_dp/n3774 ), .CLK(n1513), .Q(n1253), .QN(
\fpu_add_frac_dp/n634 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[17] ( .D(
\fpu_add_frac_dp/n3775 ), .CLK(n1487), .Q(n1267), .QN(
\fpu_add_frac_dp/n635 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[16] ( .D(
\fpu_add_frac_dp/n3776 ), .CLK(n1480), .Q(n1283), .QN(
\fpu_add_frac_dp/n636 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[15] ( .D(
\fpu_add_frac_dp/n3777 ), .CLK(n1487), .Q(n1282), .QN(
\fpu_add_frac_dp/n637 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[14] ( .D(
\fpu_add_frac_dp/n3778 ), .CLK(n1487), .Q(n1252), .QN(
\fpu_add_frac_dp/n638 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[13] ( .D(
\fpu_add_frac_dp/n3779 ), .CLK(n1487), .Q(n1281), .QN(
\fpu_add_frac_dp/n639 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[12] ( .D(
\fpu_add_frac_dp/n3780 ), .CLK(n1487), .Q(n1280), .QN(
\fpu_add_frac_dp/n640 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[11] ( .D(
\fpu_add_frac_dp/n3781 ), .CLK(n1486), .Q(n1279), .QN(
\fpu_add_frac_dp/n641 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[10] ( .D(
\fpu_add_frac_dp/n3782 ), .CLK(n1486), .Q(n1278), .QN(
\fpu_add_frac_dp/n642 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[9] ( .D(\fpu_add_frac_dp/n3783 ), .CLK(n1486), .Q(n1247), .QN(\fpu_add_frac_dp/n643 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[8] ( .D(\fpu_add_frac_dp/n3784 ), .CLK(n1486), .Q(n1266), .QN(\fpu_add_frac_dp/n644 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[7] ( .D(\fpu_add_frac_dp/n3785 ), .CLK(n1486), .Q(n1277), .QN(\fpu_add_frac_dp/n645 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[6] ( .D(\fpu_add_frac_dp/n3786 ), .CLK(n1486), .Q(n1251), .QN(\fpu_add_frac_dp/n646 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[5] ( .D(\fpu_add_frac_dp/n3787 ), .CLK(n1486), .Q(n1273), .QN(\fpu_add_frac_dp/n647 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[4] ( .D(\fpu_add_frac_dp/n3788 ), .CLK(n1486), .Q(n1276), .QN(\fpu_add_frac_dp/n648 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[3] ( .D(\fpu_add_frac_dp/n3789 ), .CLK(n1486), .Q(n1275), .QN(\fpu_add_frac_dp/n649 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[2] ( .D(\fpu_add_frac_dp/n3790 ), .CLK(n1486), .Q(n1250), .QN(\fpu_add_frac_dp/n650 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[1] ( .D(\fpu_add_frac_dp/n3791 ), .CLK(n1486), .Q(n1081) );
DFFX1 \fpu_add_frac_dp/i_a3stg_expdec/q_reg[0] ( .D(\fpu_add_frac_dp/n3792 ), .CLK(n1486), .Q(n1274), .QN(\fpu_add_frac_dp/n652 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[63] ( .D(
\fpu_add_frac_dp/n3667 ), .CLK(n1551), .Q(n87), .QN(
\fpu_add_frac_dp/n2440 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[62] ( .D(
\fpu_add_frac_dp/n3668 ), .CLK(n1551), .Q(n266), .QN(
\fpu_add_frac_dp/n5618 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[61] ( .D(
\fpu_add_frac_dp/n3669 ), .CLK(n1551), .Q(n94), .QN(
\fpu_add_frac_dp/n2288 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[60] ( .D(
\fpu_add_frac_dp/n3670 ), .CLK(n1551), .Q(\fpu_add_frac_dp/n2337 ),
.QN(n654) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[59] ( .D(
\fpu_add_frac_dp/n3671 ), .CLK(n1551), .Q(n82), .QN(
\fpu_add_frac_dp/n2394 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[58] ( .D(
\fpu_add_frac_dp/n3672 ), .CLK(n1551), .Q(n171), .QN(
\fpu_add_frac_dp/n654 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[57] ( .D(
\fpu_add_frac_dp/n3673 ), .CLK(n1551), .Q(\fpu_add_frac_dp/n2343 ),
.QN(\fpu_add_frac_dp/n1355 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[56] ( .D(
\fpu_add_frac_dp/n3674 ), .CLK(n1551), .Q(\fpu_add_frac_dp/n2407 ),
.QN(\fpu_add_frac_dp/n1354 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[55] ( .D(
\fpu_add_frac_dp/n3675 ), .CLK(n1551), .Q(\fpu_add_frac_dp/n2338 ),
.QN(\fpu_add_frac_dp/n1352 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[54] ( .D(
\fpu_add_frac_dp/n3676 ), .CLK(n1551), .Q(n265), .QN(
\fpu_add_frac_dp/n2290 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[53] ( .D(
\fpu_add_frac_dp/n3677 ), .CLK(n1552), .Q(n92), .QN(
\fpu_add_frac_dp/n2345 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[52] ( .D(
\fpu_add_frac_dp/n3678 ), .CLK(n1552), .Q(n313), .QN(
\fpu_add_frac_dp/n2416 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[51] ( .D(
\fpu_add_frac_dp/n3679 ), .CLK(n1552), .Q(n85), .QN(
\fpu_add_frac_dp/n2378 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[50] ( .D(
\fpu_add_frac_dp/n3680 ), .CLK(n1552), .Q(n22), .QN(
\fpu_add_frac_dp/n5631 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[49] ( .D(
\fpu_add_frac_dp/n3681 ), .CLK(n1552), .Q(n175), .QN(
\fpu_add_frac_dp/n2386 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[48] ( .D(
\fpu_add_frac_dp/n3682 ), .CLK(n1552), .Q(n104), .QN(
\fpu_add_frac_dp/n5630 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[47] ( .D(
\fpu_add_frac_dp/n3683 ), .CLK(n1552), .Q(n40), .QN(
\fpu_add_frac_dp/n2333 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[46] ( .D(
\fpu_add_frac_dp/n3684 ), .CLK(n1552), .Q(n667), .QN(
\fpu_add_frac_dp/n5632 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[45] ( .D(
\fpu_add_frac_dp/n3685 ), .CLK(n1552), .Q(n100), .QN(
\fpu_add_frac_dp/n2387 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[44] ( .D(
\fpu_add_frac_dp/n3686 ), .CLK(n1552), .Q(n665), .QN(
\fpu_add_frac_dp/n5609 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[43] ( .D(
\fpu_add_frac_dp/n3687 ), .CLK(n1552), .Q(n83), .QN(
\fpu_add_frac_dp/n2537 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[42] ( .D(
\fpu_add_frac_dp/n3688 ), .CLK(n1552), .Q(n38), .QN(
\fpu_add_frac_dp/n2481 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[41] ( .D(
\fpu_add_frac_dp/n3689 ), .CLK(n1552), .Q(n117), .QN(
\fpu_add_frac_dp/n2361 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[40] ( .D(
\fpu_add_frac_dp/n3690 ), .CLK(n1553), .Q(n673), .QN(
\fpu_add_frac_dp/n658 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[39] ( .D(
\fpu_add_frac_dp/n3691 ), .CLK(n1553), .Q(n19), .QN(
\fpu_add_frac_dp/n2404 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[38] ( .D(
\fpu_add_frac_dp/n3692 ), .CLK(n1553), .Q(n86), .QN(
\fpu_add_frac_dp/n2336 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[37] ( .D(
\fpu_add_frac_dp/n3693 ), .CLK(n1553), .Q(n177), .QN(
\fpu_add_frac_dp/n659 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[36] ( .D(
\fpu_add_frac_dp/n3694 ), .CLK(n1553), .Q(\fpu_add_frac_dp/n2332 ),
.QN(n716) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[35] ( .D(
\fpu_add_frac_dp/n3695 ), .CLK(n1553), .Q(\fpu_add_frac_dp/n2406 ),
.QN(\fpu_add_frac_dp/n1335 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[34] ( .D(
\fpu_add_frac_dp/n3696 ), .CLK(n1553), .Q(\fpu_add_frac_dp/n2289 ),
.QN(n1271) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[33] ( .D(
\fpu_add_frac_dp/n3697 ), .CLK(n1553), .Q(\fpu_add_frac_dp/n2342 ),
.QN(\fpu_add_frac_dp/n1333 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[32] ( .D(
\fpu_add_frac_dp/n3698 ), .CLK(n1553), .Q(\fpu_add_frac_dp/n2403 ),
.QN(\fpu_add_frac_dp/n1332 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[31] ( .D(
\fpu_add_frac_dp/n3699 ), .CLK(n1553), .Q(\fpu_add_frac_dp/n2335 ),
.QN(n839) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[30] ( .D(
\fpu_add_frac_dp/n3700 ), .CLK(n1553), .Q(n262), .QN(
\fpu_add_frac_dp/n2363 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[29] ( .D(
\fpu_add_frac_dp/n3701 ), .CLK(n1553), .Q(n101), .QN(
\fpu_add_frac_dp/n2496 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[28] ( .D(
\fpu_add_frac_dp/n3702 ), .CLK(n1553), .Q(n329), .QN(
\fpu_add_frac_dp/n660 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[27] ( .D(
\fpu_add_frac_dp/n3703 ), .CLK(n1553), .Q(\fpu_add_frac_dp/n2313 ),
.QN(n346) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[26] ( .D(
\fpu_add_frac_dp/n3704 ), .CLK(n1554), .Q(\fpu_add_frac_dp/n2402 ),
.QN(n710) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[25] ( .D(
\fpu_add_frac_dp/n3705 ), .CLK(n1554), .Q(n116), .QN(
\fpu_add_frac_dp/n2470 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[24] ( .D(
\fpu_add_frac_dp/n3706 ), .CLK(n1554), .Q(n331), .QN(
\fpu_add_frac_dp/n5619 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[23] ( .D(
\fpu_add_frac_dp/n3707 ), .CLK(n1554), .Q(n74), .QN(
\fpu_add_frac_dp/n2409 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[22] ( .D(
\fpu_add_frac_dp/n3708 ), .CLK(n1554), .Q(n594), .QN(
\fpu_add_frac_dp/n662 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[21] ( .D(
\fpu_add_frac_dp/n3709 ), .CLK(n1554), .Q(\fpu_add_frac_dp/n2405 ),
.QN(n1087) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[20] ( .D(
\fpu_add_frac_dp/n3710 ), .CLK(n1554), .Q(\fpu_add_frac_dp/n2339 ),
.QN(n447) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[19] ( .D(
\fpu_add_frac_dp/n3711 ), .CLK(n1554), .Q(n664), .QN(
\fpu_add_frac_dp/n2411 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[18] ( .D(
\fpu_add_frac_dp/n3712 ), .CLK(n1554), .Q(n111), .QN(
\fpu_add_frac_dp/n2344 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[17] ( .D(
\fpu_add_frac_dp/n3713 ), .CLK(n1554), .Q(n43), .QN(
\fpu_add_frac_dp/n2495 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[16] ( .D(
\fpu_add_frac_dp/n3714 ), .CLK(n1554), .Q(n328), .QN(
\fpu_add_frac_dp/n664 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[15] ( .D(
\fpu_add_frac_dp/n3715 ), .CLK(n1554), .Q(\fpu_add_frac_dp/n2400 ),
.QN(\fpu_add_frac_dp/n1315 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[14] ( .D(
\fpu_add_frac_dp/n3716 ), .CLK(n1554), .Q(\fpu_add_frac_dp/n2330 ),
.QN(\fpu_add_frac_dp/n1314 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[13] ( .D(
\fpu_add_frac_dp/n3717 ), .CLK(n1554), .Q(n597), .QN(
\fpu_add_frac_dp/n2437 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[12] ( .D(
\fpu_add_frac_dp/n3718 ), .CLK(n1555), .Q(n37) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[11] ( .D(
\fpu_add_frac_dp/n3719 ), .CLK(n1555), .Q(n691), .QN(
\fpu_add_frac_dp/n2519 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[10] ( .D(
\fpu_add_frac_dp/n3720 ), .CLK(n1555), .Q(n12), .QN(
\fpu_add_frac_dp/n5610 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[9] ( .D(
\fpu_add_frac_dp/n3721 ), .CLK(n1555), .Q(n34), .QN(
\fpu_add_frac_dp/n2494 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[8] ( .D(
\fpu_add_frac_dp/n3722 ), .CLK(n1555), .Q(n623), .QN(
\fpu_add_frac_dp/n666 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[7] ( .D(
\fpu_add_frac_dp/n3723 ), .CLK(n1555), .Q(n33), .QN(
\fpu_add_frac_dp/n2513 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[6] ( .D(
\fpu_add_frac_dp/n3724 ), .CLK(n1555), .Q(n173), .QN(
\fpu_add_frac_dp/n668 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[5] ( .D(
\fpu_add_frac_dp/n3725 ), .CLK(n1555), .Q(n626), .QN(
\fpu_add_frac_dp/n2520 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[4] ( .D(
\fpu_add_frac_dp/n3726 ), .CLK(n1555), .Q(n90) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[3] ( .D(
\fpu_add_frac_dp/n3727 ), .CLK(n1555), .Q(n671), .QN(
\fpu_add_frac_dp/n670 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[2] ( .D(
\fpu_add_frac_dp/n3728 ), .CLK(n1555), .Q(n282), .QN(
\fpu_add_frac_dp/n2447 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[1] ( .D(
\fpu_add_frac_dp/n3729 ), .CLK(n1555), .Q(n103), .QN(
\fpu_add_frac_dp/n5642 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_ld0_frac/q_reg[0] ( .D(
\fpu_add_frac_dp/n3730 ), .CLK(n1555), .Q(n652) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[62] ( .D(\fpu_add_frac_dp/n3794 ), .CLK(n1493), .Q(n453), .QN(\fpu_add_frac_dp/n673 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[61] ( .D(\fpu_add_frac_dp/n3795 ), .CLK(n1493), .Q(n768), .QN(\fpu_add_frac_dp/n674 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[60] ( .D(\fpu_add_frac_dp/n3796 ), .CLK(n1493), .Q(n769), .QN(\fpu_add_frac_dp/n675 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[59] ( .D(\fpu_add_frac_dp/n3797 ), .CLK(n1493), .Q(n770), .QN(\fpu_add_frac_dp/n676 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[58] ( .D(\fpu_add_frac_dp/n3798 ), .CLK(n1493), .Q(n771), .QN(\fpu_add_frac_dp/n677 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[57] ( .D(\fpu_add_frac_dp/n3799 ), .CLK(n1493), .Q(n772), .QN(\fpu_add_frac_dp/n678 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[56] ( .D(\fpu_add_frac_dp/n3800 ), .CLK(n1493), .Q(n773), .QN(\fpu_add_frac_dp/n679 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[55] ( .D(\fpu_add_frac_dp/n3801 ), .CLK(n1492), .Q(n774), .QN(\fpu_add_frac_dp/n680 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[54] ( .D(\fpu_add_frac_dp/n3802 ), .CLK(n1492), .Q(n775), .QN(\fpu_add_frac_dp/n681 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[53] ( .D(\fpu_add_frac_dp/n3803 ), .CLK(n1492), .Q(n776), .QN(\fpu_add_frac_dp/n682 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[52] ( .D(\fpu_add_frac_dp/n3804 ), .CLK(n1492), .Q(n777), .QN(\fpu_add_frac_dp/n683 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[51] ( .D(\fpu_add_frac_dp/n3805 ), .CLK(n1492), .Q(n778), .QN(\fpu_add_frac_dp/n684 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[50] ( .D(\fpu_add_frac_dp/n3806 ), .CLK(n1492), .Q(n779), .QN(\fpu_add_frac_dp/n685 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[49] ( .D(\fpu_add_frac_dp/n3807 ), .CLK(n1492), .Q(n780), .QN(\fpu_add_frac_dp/n686 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[48] ( .D(\fpu_add_frac_dp/n3808 ), .CLK(n1491), .Q(n781), .QN(\fpu_add_frac_dp/n687 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[47] ( .D(\fpu_add_frac_dp/n3809 ), .CLK(n1491), .Q(n782), .QN(\fpu_add_frac_dp/n688 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[46] ( .D(\fpu_add_frac_dp/n3810 ), .CLK(n1491), .Q(n783), .QN(\fpu_add_frac_dp/n689 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[45] ( .D(\fpu_add_frac_dp/n3811 ), .CLK(n1491), .Q(n784), .QN(\fpu_add_frac_dp/n690 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[44] ( .D(\fpu_add_frac_dp/n3812 ), .CLK(n1491), .Q(n785), .QN(\fpu_add_frac_dp/n691 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[43] ( .D(\fpu_add_frac_dp/n3813 ), .CLK(n1491), .Q(n786), .QN(\fpu_add_frac_dp/n692 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[42] ( .D(\fpu_add_frac_dp/n3814 ), .CLK(n1491), .Q(n787), .QN(\fpu_add_frac_dp/n693 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[41] ( .D(\fpu_add_frac_dp/n3815 ), .CLK(n1490), .Q(n788), .QN(\fpu_add_frac_dp/n694 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[40] ( .D(\fpu_add_frac_dp/n3816 ), .CLK(n1490), .Q(n789), .QN(\fpu_add_frac_dp/n695 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[39] ( .D(\fpu_add_frac_dp/n3817 ), .CLK(n1490), .Q(n790), .QN(\fpu_add_frac_dp/n696 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[38] ( .D(\fpu_add_frac_dp/n3818 ), .CLK(n1490), .Q(n791), .QN(\fpu_add_frac_dp/n697 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[37] ( .D(\fpu_add_frac_dp/n3819 ), .CLK(n1490), .Q(n792), .QN(\fpu_add_frac_dp/n698 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[36] ( .D(\fpu_add_frac_dp/n3820 ), .CLK(n1490), .Q(n793), .QN(\fpu_add_frac_dp/n699 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[35] ( .D(\fpu_add_frac_dp/n3821 ), .CLK(n1490), .Q(n794), .QN(\fpu_add_frac_dp/n700 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[34] ( .D(\fpu_add_frac_dp/n3822 ), .CLK(n1489), .Q(n795), .QN(\fpu_add_frac_dp/n701 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[33] ( .D(\fpu_add_frac_dp/n3823 ), .CLK(n1489), .Q(n796), .QN(\fpu_add_frac_dp/n702 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[32] ( .D(\fpu_add_frac_dp/n3824 ), .CLK(n1489), .Q(n797), .QN(\fpu_add_frac_dp/n703 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[31] ( .D(\fpu_add_frac_dp/n3825 ), .CLK(n1489), .Q(n798), .QN(\fpu_add_frac_dp/n704 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[30] ( .D(\fpu_add_frac_dp/n3826 ), .CLK(n1489), .Q(n799), .QN(\fpu_add_frac_dp/n705 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[29] ( .D(\fpu_add_frac_dp/n3827 ), .CLK(n1489), .Q(n800), .QN(\fpu_add_frac_dp/n706 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[28] ( .D(\fpu_add_frac_dp/n3828 ), .CLK(n1489), .Q(n801), .QN(\fpu_add_frac_dp/n707 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[27] ( .D(\fpu_add_frac_dp/n3829 ), .CLK(n1488), .Q(n802), .QN(\fpu_add_frac_dp/n708 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[26] ( .D(\fpu_add_frac_dp/n3830 ), .CLK(n1488), .Q(n803), .QN(\fpu_add_frac_dp/n709 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[25] ( .D(\fpu_add_frac_dp/n3831 ), .CLK(n1488), .Q(n804), .QN(\fpu_add_frac_dp/n710 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[24] ( .D(\fpu_add_frac_dp/n3832 ), .CLK(n1488), .Q(n805), .QN(\fpu_add_frac_dp/n711 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[23] ( .D(\fpu_add_frac_dp/n3833 ), .CLK(n1488), .Q(n806), .QN(\fpu_add_frac_dp/n712 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[22] ( .D(\fpu_add_frac_dp/n3834 ), .CLK(n1488), .Q(n807), .QN(\fpu_add_frac_dp/n713 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[21] ( .D(\fpu_add_frac_dp/n3835 ), .CLK(n1488), .Q(n808), .QN(\fpu_add_frac_dp/n714 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[20] ( .D(\fpu_add_frac_dp/n3836 ), .CLK(n1487), .Q(n809), .QN(\fpu_add_frac_dp/n715 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[19] ( .D(\fpu_add_frac_dp/n3837 ), .CLK(n1487), .Q(n810), .QN(\fpu_add_frac_dp/n716 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[18] ( .D(\fpu_add_frac_dp/n3838 ), .CLK(n1487), .Q(n811), .QN(\fpu_add_frac_dp/n717 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[17] ( .D(\fpu_add_frac_dp/n3839 ), .CLK(n1487), .Q(n812), .QN(\fpu_add_frac_dp/n718 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[16] ( .D(\fpu_add_frac_dp/n3840 ), .CLK(n1492), .Q(n813), .QN(\fpu_add_frac_dp/n719 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[15] ( .D(\fpu_add_frac_dp/n3841 ), .CLK(n1548), .Q(n814), .QN(\fpu_add_frac_dp/n720 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[14] ( .D(\fpu_add_frac_dp/n3842 ), .CLK(n1547), .Q(n815), .QN(\fpu_add_frac_dp/n721 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[13] ( .D(\fpu_add_frac_dp/n3843 ), .CLK(n1547), .Q(n816), .QN(\fpu_add_frac_dp/n722 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[12] ( .D(\fpu_add_frac_dp/n3844 ), .CLK(n1547), .Q(n817), .QN(\fpu_add_frac_dp/n723 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[11] ( .D(\fpu_add_frac_dp/n3845 ), .CLK(n1547), .Q(n818), .QN(\fpu_add_frac_dp/n724 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[10] ( .D(\fpu_add_frac_dp/n3846 ), .CLK(n1547), .Q(n819), .QN(\fpu_add_frac_dp/n725 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[9] ( .D(\fpu_add_frac_dp/n3847 ),
.CLK(n1547), .Q(n820), .QN(\fpu_add_frac_dp/n726 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[8] ( .D(\fpu_add_frac_dp/n3848 ),
.CLK(n1547), .Q(n821), .QN(\fpu_add_frac_dp/n727 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[7] ( .D(\fpu_add_frac_dp/n3849 ),
.CLK(n1546), .Q(n822), .QN(\fpu_add_frac_dp/n728 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[6] ( .D(\fpu_add_frac_dp/n3850 ),
.CLK(n1546), .Q(n823), .QN(\fpu_add_frac_dp/n729 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[5] ( .D(\fpu_add_frac_dp/n3851 ),
.CLK(n1546), .Q(n824), .QN(\fpu_add_frac_dp/n730 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[4] ( .D(\fpu_add_frac_dp/n3852 ),
.CLK(n1546), .Q(n825), .QN(\fpu_add_frac_dp/n731 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[3] ( .D(\fpu_add_frac_dp/n3853 ),
.CLK(n1546), .Q(n826), .QN(\fpu_add_frac_dp/n732 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[2] ( .D(\fpu_add_frac_dp/n3854 ),
.CLK(n1546), .Q(n827), .QN(\fpu_add_frac_dp/n733 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[1] ( .D(\fpu_add_frac_dp/n3855 ),
.CLK(n1546), .Q(n828), .QN(\fpu_add_frac_dp/n734 ) );
DFFX1 \fpu_add_frac_dp/i_a3stg_frac1/q_reg[0] ( .D(\fpu_add_frac_dp/n3856 ),
.CLK(n1545), .Q(n465), .QN(\fpu_add_frac_dp/n735 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[63] ( .D(
\fpu_add_frac_dp/n3857 ), .CLK(n1486), .Q(n15), .QN(
\fpu_add_frac_dp/n2262 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[62] ( .D(
\fpu_add_frac_dp/n3858 ), .CLK(n1486), .Q(n16), .QN(
\fpu_add_frac_dp/n2270 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[61] ( .D(
\fpu_add_frac_dp/n3859 ), .CLK(n1485), .Q(n3), .QN(
\fpu_add_frac_dp/n2282 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[60] ( .D(
\fpu_add_frac_dp/n3860 ), .CLK(n1485), .Q(n156), .QN(
\fpu_add_frac_dp/n2317 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[59] ( .D(
\fpu_add_frac_dp/n3861 ), .CLK(n1485), .Q(n68), .QN(
\fpu_add_frac_dp/n2269 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[58] ( .D(
\fpu_add_frac_dp/n3862 ), .CLK(n1485), .Q(
\fpu_add_frac_dp/a2stg_frac2a[58] ), .QN(\fpu_add_frac_dp/n2281 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[57] ( .D(
\fpu_add_frac_dp/n3863 ), .CLK(n1485), .Q(n157), .QN(
\fpu_add_frac_dp/n2314 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[56] ( .D(
\fpu_add_frac_dp/n3864 ), .CLK(n1485), .Q(n4), .QN(
\fpu_add_frac_dp/n2331 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[55] ( .D(
\fpu_add_frac_dp/n3865 ), .CLK(n1485), .Q(n98), .QN(
\fpu_add_frac_dp/n2430 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[54] ( .D(
\fpu_add_frac_dp/n3866 ), .CLK(n1485), .Q(n97), .QN(
\fpu_add_frac_dp/n2429 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[53] ( .D(
\fpu_add_frac_dp/n3867 ), .CLK(n1485), .Q(n613), .QN(
\fpu_add_frac_dp/n2428 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[52] ( .D(
\fpu_add_frac_dp/n3868 ), .CLK(n1485), .Q(n95), .QN(
\fpu_add_frac_dp/n2427 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[51] ( .D(
\fpu_add_frac_dp/n3869 ), .CLK(n1485), .Q(n632), .QN(
\fpu_add_frac_dp/n2341 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[50] ( .D(
\fpu_add_frac_dp/n3870 ), .CLK(n1485), .Q(n630), .QN(
\fpu_add_frac_dp/n2395 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[49] ( .D(
\fpu_add_frac_dp/n3871 ), .CLK(n1485), .Q(n631), .QN(
\fpu_add_frac_dp/n2426 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[48] ( .D(
\fpu_add_frac_dp/n3872 ), .CLK(n1485), .Q(n96), .QN(
\fpu_add_frac_dp/n2425 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[47] ( .D(
\fpu_add_frac_dp/n3873 ), .CLK(n1484), .Q(n217), .QN(
\fpu_add_frac_dp/n2518 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[46] ( .D(
\fpu_add_frac_dp/n3874 ), .CLK(n1484), .Q(n280), .QN(
\fpu_add_frac_dp/n2517 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[45] ( .D(
\fpu_add_frac_dp/n3875 ), .CLK(n1484), .Q(n281), .QN(
\fpu_add_frac_dp/n2516 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[44] ( .D(
\fpu_add_frac_dp/n3876 ), .CLK(n1484), .Q(n638), .QN(
\fpu_add_frac_dp/n2515 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[43] ( .D(
\fpu_add_frac_dp/n3877 ), .CLK(n1484), .Q(n174), .QN(
\fpu_add_frac_dp/n2480 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[42] ( .D(
\fpu_add_frac_dp/n3878 ), .CLK(n1484), .Q(n70), .QN(
\fpu_add_frac_dp/n2479 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[41] ( .D(
\fpu_add_frac_dp/n3879 ), .CLK(n1484), .Q(\fpu_add_frac_dp/n2380 ),
.QN(\fpu_add_frac_dp/n1215 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[40] ( .D(
\fpu_add_frac_dp/n3880 ), .CLK(n1484), .Q(n168), .QN(
\fpu_add_frac_dp/n2497 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[39] ( .D(
\fpu_add_frac_dp/n3881 ), .CLK(n1484), .Q(n271), .QN(
\fpu_add_frac_dp/n736 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[38] ( .D(
\fpu_add_frac_dp/n3882 ), .CLK(n1484), .Q(n23) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[37] ( .D(
\fpu_add_frac_dp/n3883 ), .CLK(n1484), .Q(n162) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[36] ( .D(
\fpu_add_frac_dp/n3884 ), .CLK(n1484), .Q(n6) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[35] ( .D(
\fpu_add_frac_dp/n3885 ), .CLK(n1484), .Q(n205), .QN(
\fpu_add_frac_dp/n2424 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[34] ( .D(
\fpu_add_frac_dp/n3886 ), .CLK(n1484), .Q(\fpu_add_frac_dp/n2393 ),
.QN(\fpu_add_frac_dp/n1213 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[33] ( .D(
\fpu_add_frac_dp/n3887 ), .CLK(n1483), .Q(n278), .QN(
\fpu_add_frac_dp/n741 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[32] ( .D(
\fpu_add_frac_dp/n3888 ), .CLK(n1483), .Q(n218) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[31] ( .D(
\fpu_add_frac_dp/n3889 ), .CLK(n1483), .Q(n696), .QN(
\fpu_add_frac_dp/n743 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[30] ( .D(
\fpu_add_frac_dp/n3890 ), .CLK(n1483), .Q(n678), .QN(
\fpu_add_frac_dp/n744 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[29] ( .D(
\fpu_add_frac_dp/n3891 ), .CLK(n1483), .Q(n679), .QN(
\fpu_add_frac_dp/n745 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[28] ( .D(
\fpu_add_frac_dp/n3892 ), .CLK(n1483), .Q(n106) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[27] ( .D(
\fpu_add_frac_dp/n3893 ), .CLK(n1483), .Q(n720), .QN(
\fpu_add_frac_dp/n747 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[26] ( .D(
\fpu_add_frac_dp/n3894 ), .CLK(n1483), .Q(n312) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[25] ( .D(
\fpu_add_frac_dp/n3895 ), .CLK(n1483), .Q(n932), .QN(
\fpu_add_frac_dp/n749 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[24] ( .D(
\fpu_add_frac_dp/n3896 ), .CLK(n1483), .Q(n929), .QN(
\fpu_add_frac_dp/n750 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[23] ( .D(
\fpu_add_frac_dp/n3897 ), .CLK(n1483), .Q(n931), .QN(
\fpu_add_frac_dp/n751 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[22] ( .D(
\fpu_add_frac_dp/n3898 ), .CLK(n1483), .Q(n934), .QN(
\fpu_add_frac_dp/n752 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[21] ( .D(
\fpu_add_frac_dp/n3899 ), .CLK(n1483), .Q(n131) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[20] ( .D(
\fpu_add_frac_dp/n3900 ), .CLK(n1483), .Q(n314) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[19] ( .D(
\fpu_add_frac_dp/n3901 ), .CLK(n1482), .Q(n717), .QN(
\fpu_add_frac_dp/n755 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[18] ( .D(
\fpu_add_frac_dp/n3902 ), .CLK(n1482), .Q(n1152), .QN(
\fpu_add_frac_dp/n756 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[17] ( .D(
\fpu_add_frac_dp/n3903 ), .CLK(n1482), .Q(n1151), .QN(
\fpu_add_frac_dp/n757 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[16] ( .D(
\fpu_add_frac_dp/n3904 ), .CLK(n1482), .Q(n930), .QN(
\fpu_add_frac_dp/n758 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[15] ( .D(
\fpu_add_frac_dp/n3905 ), .CLK(n1482), .Q(n935), .QN(
\fpu_add_frac_dp/n759 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[14] ( .D(
\fpu_add_frac_dp/n3906 ), .CLK(n1482), .Q(n425), .QN(
\fpu_add_frac_dp/n760 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[13] ( .D(
\fpu_add_frac_dp/n3907 ), .CLK(n1482), .Q(n721), .QN(
\fpu_add_frac_dp/n761 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[12] ( .D(
\fpu_add_frac_dp/n3908 ), .CLK(n1482), .Q(n150), .QN(
\fpu_add_frac_dp/n762 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[11] ( .D(
\fpu_add_frac_dp/n3909 ), .CLK(n1482), .Q(n627), .QN(
\fpu_add_frac_dp/n763 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[10] ( .D(
\fpu_add_frac_dp/n3910 ), .CLK(n1482), .Q(n161) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[9] ( .D(\fpu_add_frac_dp/n3911 ), .CLK(n1482), .Q(n75) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[8] ( .D(\fpu_add_frac_dp/n3912 ), .CLK(n1482), .Q(n659), .QN(\fpu_add_frac_dp/n766 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[7] ( .D(\fpu_add_frac_dp/n3913 ), .CLK(n1482), .Q(n901), .QN(\fpu_add_frac_dp/n767 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[6] ( .D(\fpu_add_frac_dp/n3914 ), .CLK(n1482), .Q(n655), .QN(\fpu_add_frac_dp/n768 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[5] ( .D(\fpu_add_frac_dp/n3915 ), .CLK(n1481), .Q(n898), .QN(\fpu_add_frac_dp/n769 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[4] ( .D(\fpu_add_frac_dp/n3916 ), .CLK(n1481), .Q(n660), .QN(\fpu_add_frac_dp/n770 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[3] ( .D(\fpu_add_frac_dp/n3917 ), .CLK(n1481), .Q(n899), .QN(\fpu_add_frac_dp/n771 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[2] ( .D(\fpu_add_frac_dp/n3918 ), .CLK(n1481), .Q(n690), .QN(\fpu_add_frac_dp/n772 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[1] ( .D(\fpu_add_frac_dp/n3919 ), .CLK(n1481), .Q(n902), .QN(\fpu_add_frac_dp/n773 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2a/q_reg[0] ( .D(\fpu_add_frac_dp/n3920 ), .CLK(n1481), .Q(n896), .QN(\fpu_add_frac_dp/n774 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[63] ( .D(\fpu_add_frac_dp/n3921 ), .CLK(n1481), .Q(n1101), .QN(\fpu_add_frac_dp/n2498 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[62] ( .D(\fpu_add_frac_dp/n3922 ), .CLK(n1481), .Q(n142), .QN(\fpu_add_frac_dp/n2502 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[61] ( .D(\fpu_add_frac_dp/n3923 ), .CLK(n1481), .Q(n706), .QN(\fpu_add_frac_dp/n2506 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[60] ( .D(\fpu_add_frac_dp/n3924 ), .CLK(n1480), .Q(\fpu_add_frac_dp/n2384 ), .QN(n1009) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[59] ( .D(\fpu_add_frac_dp/n3925 ), .CLK(n1480), .Q(\fpu_add_frac_dp/n2391 ), .QN(n153) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[58] ( .D(\fpu_add_frac_dp/n3926 ), .CLK(n1480), .Q(\fpu_add_frac_dp/n2390 ), .QN(n561) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[57] ( .D(\fpu_add_frac_dp/n3927 ), .CLK(n1480), .Q(\fpu_add_frac_dp/n2392 ), .QN(n62) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[56] ( .D(\fpu_add_frac_dp/n3928 ), .CLK(n1480), .Q(n343), .QN(\fpu_add_frac_dp/n2357 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[55] ( .D(\fpu_add_frac_dp/n3929 ), .CLK(n1480), .Q(n1118), .QN(\fpu_add_frac_dp/n2431 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[54] ( .D(\fpu_add_frac_dp/n3930 ), .CLK(n1480), .Q(n1103), .QN(\fpu_add_frac_dp/n2418 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[53] ( .D(\fpu_add_frac_dp/n3931 ), .CLK(n1480), .Q(n1100), .QN(\fpu_add_frac_dp/n2351 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[52] ( .D(\fpu_add_frac_dp/n3932 ), .CLK(n1481), .Q(n1110), .QN(\fpu_add_frac_dp/n2505 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[51] ( .D(\fpu_add_frac_dp/n3933 ), .CLK(n1480), .Q(n708), .QN(\fpu_add_frac_dp/n2501 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[50] ( .D(\fpu_add_frac_dp/n3934 ), .CLK(n1480), .Q(n345), .QN(\fpu_add_frac_dp/n2512 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[49] ( .D(\fpu_add_frac_dp/n3935 ), .CLK(n1481), .Q(n144), .QN(\fpu_add_frac_dp/n2509 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[48] ( .D(\fpu_add_frac_dp/n3936 ), .CLK(n1480), .Q(n59), .QN(\fpu_add_frac_dp/n2500 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[47] ( .D(\fpu_add_frac_dp/n3937 ), .CLK(n1479), .Q(n707), .QN(\fpu_add_frac_dp/n2303 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[46] ( .D(\fpu_add_frac_dp/n3938 ), .CLK(n1480), .Q(n344), .QN(\fpu_add_frac_dp/n2356 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[45] ( .D(\fpu_add_frac_dp/n3939 ), .CLK(n1479), .Q(n143), .QN(\fpu_add_frac_dp/n2508 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[44] ( .D(\fpu_add_frac_dp/n3940 ), .CLK(n1479), .Q(n58), .QN(\fpu_add_frac_dp/n2504 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[43] ( .D(\fpu_add_frac_dp/n3941 ), .CLK(n1480), .Q(n1117), .QN(\fpu_add_frac_dp/n2276 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[42] ( .D(\fpu_add_frac_dp/n3942 ), .CLK(n1479), .Q(n1102), .QN(\fpu_add_frac_dp/n2302 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[41] ( .D(\fpu_add_frac_dp/n3943 ), .CLK(n1479), .Q(n1099), .QN(\fpu_add_frac_dp/n2422 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[40] ( .D(\fpu_add_frac_dp/n3944 ), .CLK(n1496), .Q(n1109), .QN(\fpu_add_frac_dp/n2355 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[39] ( .D(\fpu_add_frac_dp/n3945 ), .CLK(n1496), .Q(n1116), .QN(\fpu_add_frac_dp/n2275 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[38] ( .D(\fpu_add_frac_dp/n3946 ), .CLK(n1496), .Q(n1098), .QN(\fpu_add_frac_dp/n2301 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[37] ( .D(\fpu_add_frac_dp/n3947 ), .CLK(n1496), .Q(n1097), .QN(\fpu_add_frac_dp/n2421 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[36] ( .D(\fpu_add_frac_dp/n3948 ), .CLK(n1496), .Q(n1108), .QN(\fpu_add_frac_dp/n2511 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[35] ( .D(\fpu_add_frac_dp/n3949 ), .CLK(n1496), .Q(n1115), .QN(\fpu_add_frac_dp/n2435 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[34] ( .D(\fpu_add_frac_dp/n3950 ), .CLK(n1496), .Q(n1096), .QN(\fpu_add_frac_dp/n2354 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[33] ( .D(\fpu_add_frac_dp/n3951 ), .CLK(n1496), .Q(n1095), .QN(\fpu_add_frac_dp/n2274 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[32] ( .D(\fpu_add_frac_dp/n3952 ), .CLK(n1496), .Q(n1107), .QN(\fpu_add_frac_dp/n2300 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[31] ( .D(\fpu_add_frac_dp/n3953 ), .CLK(n1496), .Q(n1114), .QN(\fpu_add_frac_dp/n2510 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[30] ( .D(\fpu_add_frac_dp/n3954 ), .CLK(n1496), .Q(n1094), .QN(\fpu_add_frac_dp/n2503 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[29] ( .D(\fpu_add_frac_dp/n3955 ), .CLK(n1496), .Q(n1106), .QN(\fpu_add_frac_dp/n2499 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[28] ( .D(\fpu_add_frac_dp/n3956 ), .CLK(n1496), .Q(n424), .QN(\fpu_add_frac_dp/n2507 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[27] ( .D(\fpu_add_frac_dp/n3957 ), .CLK(n1496), .Q(n723), .QN(\fpu_add_frac_dp/n2419 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[26] ( .D(\fpu_add_frac_dp/n3958 ), .CLK(n1495), .Q(n1113), .QN(\fpu_add_frac_dp/n2299 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[25] ( .D(\fpu_add_frac_dp/n3959 ), .CLK(n1495), .Q(n1093), .QN(\fpu_add_frac_dp/n2420 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[24] ( .D(\fpu_add_frac_dp/n3960 ), .CLK(n1495), .Q(n1105), .QN(\fpu_add_frac_dp/n2273 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[23] ( .D(\fpu_add_frac_dp/n3961 ), .CLK(n1495), .Q(n426), .QN(\fpu_add_frac_dp/n2352 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[22] ( .D(\fpu_add_frac_dp/n3962 ), .CLK(n1495), .Q(n724), .QN(\fpu_add_frac_dp/n2353 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[21] ( .D(\fpu_add_frac_dp/n3963 ), .CLK(n1495), .Q(n1112), .QN(\fpu_add_frac_dp/n2434 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[20] ( .D(\fpu_add_frac_dp/n3964 ), .CLK(n1495), .Q(n1092), .QN(\fpu_add_frac_dp/n2433 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[19] ( .D(\fpu_add_frac_dp/n3965 ), .CLK(n1495), .Q(n1104), .QN(\fpu_add_frac_dp/n2297 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[18] ( .D(\fpu_add_frac_dp/n3966 ), .CLK(n1495), .Q(n423), .QN(\fpu_add_frac_dp/n2272 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[17] ( .D(\fpu_add_frac_dp/n3967 ), .CLK(n1495), .Q(n722), .QN(\fpu_add_frac_dp/n2298 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[16] ( .D(\fpu_add_frac_dp/n3968 ), .CLK(n1495), .Q(n1123), .QN(\fpu_add_frac_dp/n2359 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[15] ( .D(\fpu_add_frac_dp/n3969 ), .CLK(n1495), .Q(n1125), .QN(\fpu_add_frac_dp/n2432 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[14] ( .D(\fpu_add_frac_dp/n3970 ), .CLK(n1495), .Q(n1122), .QN(\fpu_add_frac_dp/n2362 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[13] ( .D(\fpu_add_frac_dp/n3971 ), .CLK(n1495), .Q(n1091), .QN(\fpu_add_frac_dp/n2304 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[12] ( .D(\fpu_add_frac_dp/n3972 ), .CLK(n1494), .Q(\fpu_add_frac_dp/n2389 ), .QN(n904) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[11] ( .D(\fpu_add_frac_dp/n3973 ), .CLK(n1494), .Q(n1111), .QN(\fpu_add_frac_dp/n2277 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[10] ( .D(\fpu_add_frac_dp/n3974 ), .CLK(n1494), .Q(n1142), .QN(\fpu_add_frac_dp/n2531 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[9] ( .D(\fpu_add_frac_dp/n3975 ),
.CLK(n1494), .Q(n1141), .QN(\fpu_add_frac_dp/n2530 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[8] ( .D(\fpu_add_frac_dp/n3976 ),
.CLK(n1494), .Q(n1140), .QN(\fpu_add_frac_dp/n2529 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[7] ( .D(\fpu_add_frac_dp/n3977 ),
.CLK(n1494), .Q(n1139), .QN(\fpu_add_frac_dp/n2528 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[6] ( .D(\fpu_add_frac_dp/n3978 ),
.CLK(n1494), .Q(n1138), .QN(\fpu_add_frac_dp/n2527 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[5] ( .D(\fpu_add_frac_dp/n3979 ),
.CLK(n1494), .Q(n1149), .QN(\fpu_add_frac_dp/n2526 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[4] ( .D(\fpu_add_frac_dp/n3980 ),
.CLK(n1494), .Q(n1137), .QN(\fpu_add_frac_dp/n2525 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[3] ( .D(\fpu_add_frac_dp/n3981 ),
.CLK(n1494), .Q(n1136), .QN(\fpu_add_frac_dp/n2524 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[2] ( .D(\fpu_add_frac_dp/n3982 ),
.CLK(n1494), .Q(n1135), .QN(\fpu_add_frac_dp/n2523 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[1] ( .D(\fpu_add_frac_dp/n3983 ),
.CLK(n1494), .Q(n1134), .QN(\fpu_add_frac_dp/n2522 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac2/q_reg[0] ( .D(\fpu_add_frac_dp/n3984 ),
.CLK(n1494), .Q(n1196), .QN(\fpu_add_frac_dp/n2539 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[63] ( .D(\fpu_add_frac_dp/n3985 ), .CLK(n1494), .Q(n850), .QN(\fpu_add_frac_dp/n5640 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[62] ( .D(\fpu_add_frac_dp/n3986 ), .CLK(n1493), .Q(n226) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[61] ( .D(\fpu_add_frac_dp/n3987 ), .CLK(n1493), .Q(n195) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[60] ( .D(\fpu_add_frac_dp/n3988 ), .CLK(n1493), .Q(n317), .QN(\fpu_add_frac_dp/n777 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[59] ( .D(\fpu_add_frac_dp/n3989 ), .CLK(n1493), .Q(n293), .QN(\fpu_add_frac_dp/n778 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[58] ( .D(\fpu_add_frac_dp/n3990 ), .CLK(n1493), .Q(n334), .QN(\fpu_add_frac_dp/n779 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[57] ( .D(\fpu_add_frac_dp/n3991 ), .CLK(n1493), .Q(n332), .QN(\fpu_add_frac_dp/n780 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[56] ( .D(\fpu_add_frac_dp/n3992 ), .CLK(n1493), .Q(n294), .QN(\fpu_add_frac_dp/n781 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[55] ( .D(\fpu_add_frac_dp/n3993 ), .CLK(n1492), .Q(n196) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[54] ( .D(\fpu_add_frac_dp/n3994 ), .CLK(n1492), .Q(n227) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[53] ( .D(\fpu_add_frac_dp/n3995 ), .CLK(n1492), .Q(n228) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[52] ( .D(\fpu_add_frac_dp/n3996 ), .CLK(n1492), .Q(n229) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[51] ( .D(\fpu_add_frac_dp/n3997 ), .CLK(n1492), .Q(n230) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[50] ( .D(\fpu_add_frac_dp/n3998 ), .CLK(n1492), .Q(n231) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[49] ( .D(\fpu_add_frac_dp/n3999 ), .CLK(n1491), .Q(n232) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[48] ( .D(\fpu_add_frac_dp/n4000 ), .CLK(n1491), .Q(n233) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[47] ( .D(\fpu_add_frac_dp/n4001 ), .CLK(n1491), .Q(n197) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[46] ( .D(\fpu_add_frac_dp/n4002 ), .CLK(n1491), .Q(n198) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[45] ( .D(\fpu_add_frac_dp/n4003 ), .CLK(n1491), .Q(n234) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[44] ( .D(\fpu_add_frac_dp/n4004 ), .CLK(n1491), .Q(n235) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[43] ( .D(\fpu_add_frac_dp/n4005 ), .CLK(n1491), .Q(n236) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[42] ( .D(\fpu_add_frac_dp/n4006 ), .CLK(n1490), .Q(n199) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[41] ( .D(\fpu_add_frac_dp/n4007 ), .CLK(n1490), .Q(n237) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[40] ( .D(\fpu_add_frac_dp/n4008 ), .CLK(n1490), .Q(n259) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[39] ( .D(\fpu_add_frac_dp/n4009 ), .CLK(n1490), .Q(n200) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[38] ( .D(\fpu_add_frac_dp/n4010 ), .CLK(n1490), .Q(n238) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[37] ( .D(\fpu_add_frac_dp/n4011 ), .CLK(n1490), .Q(n201) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[36] ( .D(\fpu_add_frac_dp/n4012 ), .CLK(n1490), .Q(n239) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[35] ( .D(\fpu_add_frac_dp/n4013 ), .CLK(n1489), .Q(n202) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[34] ( .D(\fpu_add_frac_dp/n4014 ), .CLK(n1489), .Q(n240) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[33] ( .D(\fpu_add_frac_dp/n4015 ), .CLK(n1489), .Q(n241) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[32] ( .D(\fpu_add_frac_dp/n4016 ), .CLK(n1489), .Q(n242) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[31] ( .D(\fpu_add_frac_dp/n4017 ), .CLK(n1489), .Q(n243) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[30] ( .D(\fpu_add_frac_dp/n4018 ), .CLK(n1489), .Q(n203) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[29] ( .D(\fpu_add_frac_dp/n4019 ), .CLK(n1489), .Q(n244) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[28] ( .D(\fpu_add_frac_dp/n4020 ), .CLK(n1488), .Q(n245) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[27] ( .D(\fpu_add_frac_dp/n4021 ), .CLK(n1488), .Q(n204) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[26] ( .D(\fpu_add_frac_dp/n4022 ), .CLK(n1488), .Q(n246) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[25] ( .D(\fpu_add_frac_dp/n4023 ), .CLK(n1488), .Q(n247) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[24] ( .D(\fpu_add_frac_dp/n4024 ), .CLK(n1488), .Q(n248) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[23] ( .D(\fpu_add_frac_dp/n4025 ), .CLK(n1488), .Q(n318), .QN(\fpu_add_frac_dp/n814 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[22] ( .D(\fpu_add_frac_dp/n4026 ), .CLK(n1488), .Q(n279), .QN(\fpu_add_frac_dp/n815 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[21] ( .D(\fpu_add_frac_dp/n4027 ), .CLK(n1487), .Q(n267), .QN(\fpu_add_frac_dp/n816 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[20] ( .D(\fpu_add_frac_dp/n4028 ), .CLK(n1487), .Q(n263), .QN(\fpu_add_frac_dp/n817 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[19] ( .D(\fpu_add_frac_dp/n4029 ), .CLK(n1487), .Q(n249) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[18] ( .D(\fpu_add_frac_dp/n4030 ), .CLK(n1487), .Q(n250) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[17] ( .D(\fpu_add_frac_dp/n4031 ), .CLK(n1487), .Q(n251) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[16] ( .D(\fpu_add_frac_dp/n4032 ), .CLK(n1497), .Q(n179) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[15] ( .D(\fpu_add_frac_dp/n4033 ), .CLK(n1548), .Q(n268), .QN(\fpu_add_frac_dp/n822 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[14] ( .D(\fpu_add_frac_dp/n4034 ), .CLK(n1547), .Q(n180), .QN(\fpu_add_frac_dp/n823 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[13] ( .D(\fpu_add_frac_dp/n4035 ), .CLK(n1547), .Q(n327), .QN(\fpu_add_frac_dp/n824 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[12] ( .D(\fpu_add_frac_dp/n4036 ), .CLK(n1547), .Q(n252) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[11] ( .D(\fpu_add_frac_dp/n4037 ), .CLK(n1547), .Q(n253) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[10] ( .D(\fpu_add_frac_dp/n4038 ), .CLK(n1547), .Q(n260) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[9] ( .D(\fpu_add_frac_dp/n4039 ),
.CLK(n1547), .Q(n261) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[8] ( .D(\fpu_add_frac_dp/n4040 ),
.CLK(n1547), .Q(n224) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[7] ( .D(\fpu_add_frac_dp/n4041 ),
.CLK(n1546), .Q(n222) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[6] ( .D(\fpu_add_frac_dp/n4042 ),
.CLK(n1546), .Q(n225) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[5] ( .D(\fpu_add_frac_dp/n4043 ),
.CLK(n1546), .Q(n223) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[4] ( .D(\fpu_add_frac_dp/n4044 ),
.CLK(n1546), .Q(n288), .QN(\fpu_add_frac_dp/n833 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[3] ( .D(\fpu_add_frac_dp/n4045 ),
.CLK(n1546), .Q(n310), .QN(\fpu_add_frac_dp/n834 ) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[2] ( .D(\fpu_add_frac_dp/n4046 ),
.CLK(n1546), .Q(n220) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[1] ( .D(\fpu_add_frac_dp/n4047 ),
.CLK(n1546), .Q(n625) );
DFFX1 \fpu_add_frac_dp/i_a2stg_frac1/q_reg[0] ( .D(\fpu_add_frac_dp/n4048 ),
.CLK(n1545), .Q(n307), .QN(\fpu_add_frac_dp/n2477 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[54] ( .D(\fpu_add_frac_dp/n4049 ),
.CLK(n1518), .Q(n1130), .QN(\fpu_add_frac_dp/n2364 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[53] ( .D(\fpu_add_frac_dp/n4050 ),
.CLK(n1507), .Q(n650), .QN(\fpu_add_frac_dp/n2442 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[52] ( .D(\fpu_add_frac_dp/n4051 ),
.CLK(n1507), .Q(\fpu_add_frac_dp/n5644 ), .QN(n1304) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[51] ( .D(\fpu_add_frac_dp/n4052 ),
.CLK(n1507), .Q(\fpu_add_frac_dp/n2491 ), .QN(n1089) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[50] ( .D(\fpu_add_frac_dp/n4053 ),
.CLK(n1507), .Q(n427), .QN(\fpu_add_frac_dp/n2535 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[49] ( .D(\fpu_add_frac_dp/n4054 ),
.CLK(n1507), .Q(n1065), .QN(\fpu_add_frac_dp/n5625 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[48] ( .D(\fpu_add_frac_dp/n4055 ),
.CLK(n1507), .Q(n1211), .QN(\fpu_add_frac_dp/n5626 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[47] ( .D(\fpu_add_frac_dp/n4056 ),
.CLK(n1507), .Q(\fpu_add_frac_dp/n5624 ), .QN(\fpu_add_frac_dp/n1123 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[46] ( .D(\fpu_add_frac_dp/n4057 ),
.CLK(n1507), .Q(\fpu_add_frac_dp/n5611 ), .QN(\fpu_add_frac_dp/n1122 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[45] ( .D(\fpu_add_frac_dp/n4058 ),
.CLK(n1507), .Q(n1208), .QN(\fpu_add_frac_dp/n2538 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[44] ( .D(\fpu_add_frac_dp/n4059 ),
.CLK(n1507), .Q(\fpu_add_frac_dp/n5621 ), .QN(n578) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[43] ( .D(\fpu_add_frac_dp/n4060 ),
.CLK(n1507), .Q(n763), .QN(\fpu_add_frac_dp/n2543 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[42] ( .D(\fpu_add_frac_dp/n4061 ),
.CLK(n1507), .Q(n1199), .QN(\fpu_add_frac_dp/n839 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[41] ( .D(\fpu_add_frac_dp/n4062 ),
.CLK(n1507), .Q(\fpu_add_frac_dp/n5620 ), .QN(\fpu_add_frac_dp/n1119 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[40] ( .D(\fpu_add_frac_dp/n4063 ),
.CLK(n1506), .Q(n463), .QN(\fpu_add_frac_dp/n2438 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[39] ( .D(\fpu_add_frac_dp/n4064 ),
.CLK(n1506), .Q(n141) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[38] ( .D(\fpu_add_frac_dp/n4065 ),
.CLK(n1506), .Q(\fpu_add_frac_dp/n5613 ), .QN(n306) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[37] ( .D(\fpu_add_frac_dp/n4066 ),
.CLK(n1506), .Q(\fpu_add_frac_dp/n5612 ), .QN(n719) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[36] ( .D(\fpu_add_frac_dp/n4067 ),
.CLK(n1506), .Q(n1207), .QN(\fpu_add_frac_dp/n841 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[35] ( .D(\fpu_add_frac_dp/n4068 ),
.CLK(n1506), .Q(\fpu_add_frac_dp/n5623 ), .QN(\fpu_add_frac_dp/n1115 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[34] ( .D(\fpu_add_frac_dp/n4069 ),
.CLK(n1506), .Q(n916), .QN(\fpu_add_frac_dp/n2365 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[33] ( .D(\fpu_add_frac_dp/n4070 ),
.CLK(n1506), .Q(n326), .QN(\fpu_add_frac_dp/n2532 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[32] ( .D(\fpu_add_frac_dp/n4071 ),
.CLK(n1506), .Q(\fpu_add_frac_dp/n5622 ), .QN(n358) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[31] ( .D(\fpu_add_frac_dp/n4072 ),
.CLK(n1506), .Q(n1194), .QN(\fpu_add_frac_dp/n2441 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[30] ( .D(\fpu_add_frac_dp/n4073 ),
.CLK(n1506), .Q(n132), .QN(\fpu_add_frac_dp/n843 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[29] ( .D(\fpu_add_frac_dp/n4074 ),
.CLK(n1506), .Q(n1132), .QN(\fpu_add_frac_dp/n2514 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[28] ( .D(\fpu_add_frac_dp/n4075 ),
.CLK(n1506), .Q(\fpu_add_frac_dp/n5605 ), .QN(n428) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[27] ( .D(\fpu_add_frac_dp/n4076 ),
.CLK(n1506), .Q(\fpu_add_frac_dp/n5608 ), .QN(\fpu_add_frac_dp/n1109 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[26] ( .D(\fpu_add_frac_dp/n4077 ),
.CLK(n1505), .Q(\fpu_add_frac_dp/n2482 ), .QN(n1303) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[25] ( .D(\fpu_add_frac_dp/n4078 ),
.CLK(n1505), .Q(\fpu_add_frac_dp/n2486 ), .QN(\fpu_add_frac_dp/n1107 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[24] ( .D(\fpu_add_frac_dp/n4079 ),
.CLK(n1505), .Q(n1127), .QN(\fpu_add_frac_dp/n844 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[23] ( .D(\fpu_add_frac_dp/n4080 ),
.CLK(n1505), .Q(\fpu_add_frac_dp/n2458 ), .QN(\fpu_add_frac_dp/n1106 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[22] ( .D(\fpu_add_frac_dp/n4081 ),
.CLK(n1505), .Q(\fpu_add_frac_dp/n2492 ), .QN(\fpu_add_frac_dp/n1105 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[21] ( .D(\fpu_add_frac_dp/n4082 ),
.CLK(n1505), .Q(n335), .QN(\fpu_add_frac_dp/n845 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[20] ( .D(\fpu_add_frac_dp/n4083 ),
.CLK(n1505), .Q(\fpu_add_frac_dp/n2487 ), .QN(\fpu_add_frac_dp/n1104 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[19] ( .D(\fpu_add_frac_dp/n4084 ),
.CLK(n1505), .Q(\fpu_add_frac_dp/n2485 ), .QN(\fpu_add_frac_dp/n1103 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[18] ( .D(\fpu_add_frac_dp/n4085 ),
.CLK(n1505), .Q(n1192), .QN(\fpu_add_frac_dp/n846 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[17] ( .D(\fpu_add_frac_dp/n4086 ),
.CLK(n1505), .Q(n1131), .QN(\fpu_add_frac_dp/n2536 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[16] ( .D(\fpu_add_frac_dp/n4087 ),
.CLK(n1505), .Q(n1193), .QN(\fpu_add_frac_dp/n5629 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[15] ( .D(\fpu_add_frac_dp/n4088 ),
.CLK(n1505), .Q(n1203), .QN(\fpu_add_frac_dp/n847 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[14] ( .D(\fpu_add_frac_dp/n4089 ),
.CLK(n1505), .Q(n1007), .QN(\fpu_add_frac_dp/n5627 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[13] ( .D(\fpu_add_frac_dp/n4090 ),
.CLK(n1505), .Q(n330) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[12] ( .D(\fpu_add_frac_dp/n4091 ),
.CLK(n1504), .Q(n670), .QN(\fpu_add_frac_dp/n848 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[11] ( .D(\fpu_add_frac_dp/n4092 ),
.CLK(n1504), .Q(\fpu_add_frac_dp/n2457 ), .QN(n357) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[10] ( .D(\fpu_add_frac_dp/n4093 ),
.CLK(n1504), .Q(\fpu_add_frac_dp/n2483 ), .QN(n1088) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[9] ( .D(\fpu_add_frac_dp/n4094 ),
.CLK(n1504), .Q(n697), .QN(\fpu_add_frac_dp/n2374 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[8] ( .D(\fpu_add_frac_dp/n4095 ),
.CLK(n1504), .Q(\fpu_add_frac_dp/n2472 ), .QN(\fpu_add_frac_dp/n1096 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[7] ( .D(\fpu_add_frac_dp/n4096 ),
.CLK(n1504), .Q(\fpu_add_frac_dp/n2489 ), .QN(\fpu_add_frac_dp/n1095 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[6] ( .D(\fpu_add_frac_dp/n4097 ),
.CLK(n1504), .Q(\fpu_add_frac_dp/n2490 ), .QN(\fpu_add_frac_dp/n1094 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[5] ( .D(\fpu_add_frac_dp/n4098 ),
.CLK(n1504), .Q(\fpu_add_frac_dp/n2459 ), .QN(\fpu_add_frac_dp/n1093 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[4] ( .D(\fpu_add_frac_dp/n4099 ),
.CLK(n1504), .Q(n900), .QN(\fpu_add_frac_dp/n2366 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[3] ( .D(\fpu_add_frac_dp/n4100 ),
.CLK(n1504), .Q(n1205), .QN(\fpu_add_frac_dp/n2533 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[2] ( .D(\fpu_add_frac_dp/n4101 ),
.CLK(n1504), .Q(n337), .QN(\fpu_add_frac_dp/n2436 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[1] ( .D(\fpu_add_frac_dp/n4102 ),
.CLK(n1504), .Q(\fpu_add_frac_dp/n2455 ), .QN(\fpu_add_frac_dp/n1090 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2a/q_reg[0] ( .D(\fpu_add_frac_dp/n4103 ),
.CLK(n1504), .Q(n702), .QN(\fpu_add_frac_dp/n851 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[63] ( .D(\fpu_add_frac_dp/n4104 ),
.CLK(n1504), .Q(n1080) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[62] ( .D(\fpu_add_frac_dp/n4105 ),
.CLK(n1503), .Q(\fpu_add_frac_dp/n2469 ), .QN(\fpu_add_frac_dp/n1089 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[61] ( .D(\fpu_add_frac_dp/n4106 ),
.CLK(n1503), .Q(\fpu_add_frac_dp/n2468 ), .QN(\fpu_add_frac_dp/n1088 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[60] ( .D(\fpu_add_frac_dp/n4107 ),
.CLK(n1503), .Q(\fpu_add_frac_dp/n2475 ), .QN(\fpu_add_frac_dp/n1087 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[59] ( .D(\fpu_add_frac_dp/n4108 ),
.CLK(n1503), .Q(\fpu_add_frac_dp/n2467 ), .QN(\fpu_add_frac_dp/n1086 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[58] ( .D(\fpu_add_frac_dp/n4109 ),
.CLK(n1503), .Q(\fpu_add_frac_dp/n2474 ), .QN(\fpu_add_frac_dp/n1085 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[57] ( .D(\fpu_add_frac_dp/n4110 ),
.CLK(n1503), .Q(\fpu_add_frac_dp/n2466 ), .QN(\fpu_add_frac_dp/n1084 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[56] ( .D(\fpu_add_frac_dp/n4111 ),
.CLK(n1503), .Q(\fpu_add_frac_dp/n2473 ), .QN(\fpu_add_frac_dp/n1083 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[55] ( .D(\fpu_add_frac_dp/n4112 ),
.CLK(n1503), .Q(\fpu_add_frac_dp/n2446 ), .QN(\fpu_add_frac_dp/n1082 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[54] ( .D(\fpu_add_frac_dp/n4113 ),
.CLK(n1503), .Q(n593), .QN(\fpu_add_frac_dp/n2340 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[53] ( .D(\fpu_add_frac_dp/n4114 ),
.CLK(n1503), .Q(n592), .QN(\fpu_add_frac_dp/n2285 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[52] ( .D(\fpu_add_frac_dp/n4115 ),
.CLK(n1503), .Q(n591), .QN(\fpu_add_frac_dp/n2309 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[51] ( .D(\fpu_add_frac_dp/n4116 ),
.CLK(n1503), .Q(n169), .QN(\fpu_add_frac_dp/n2398 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[50] ( .D(\fpu_add_frac_dp/n4117 ),
.CLK(n1503), .Q(n165), .QN(\fpu_add_frac_dp/n2396 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[49] ( .D(\fpu_add_frac_dp/n4118 ),
.CLK(n1503), .Q(n78), .QN(\fpu_add_frac_dp/n2376 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[48] ( .D(\fpu_add_frac_dp/n4119 ),
.CLK(n1502), .Q(n589), .QN(\fpu_add_frac_dp/n2334 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[47] ( .D(\fpu_add_frac_dp/n4120 ),
.CLK(n1502), .Q(n588), .QN(\fpu_add_frac_dp/n2379 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[46] ( .D(\fpu_add_frac_dp/n4121 ),
.CLK(n1502), .Q(n587), .QN(\fpu_add_frac_dp/n2280 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[45] ( .D(\fpu_add_frac_dp/n4122 ),
.CLK(n1502), .Q(n164), .QN(\fpu_add_frac_dp/n2310 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[44] ( .D(\fpu_add_frac_dp/n4123 ),
.CLK(n1502), .Q(n163), .QN(\fpu_add_frac_dp/n2278 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[43] ( .D(\fpu_add_frac_dp/n4124 ),
.CLK(n1502), .Q(n29), .QN(\fpu_add_frac_dp/n2316 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[42] ( .D(\fpu_add_frac_dp/n4125 ),
.CLK(n1502), .Q(n28), .QN(\fpu_add_frac_dp/n2279 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[41] ( .D(\fpu_add_frac_dp/n4126 ),
.CLK(n1502), .Q(n27), .QN(\fpu_add_frac_dp/n2423 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[40] ( .D(\fpu_add_frac_dp/n4127 ),
.CLK(n1502), .Q(n167), .QN(\fpu_add_frac_dp/n2381 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[39] ( .D(\fpu_add_frac_dp/n4128 ),
.CLK(n1502), .Q(n77) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[38] ( .D(\fpu_add_frac_dp/n4129 ),
.CLK(n1502), .Q(n76) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[37] ( .D(\fpu_add_frac_dp/n4130 ),
.CLK(n1502), .Q(n26) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[36] ( .D(\fpu_add_frac_dp/n4131 ),
.CLK(n1502), .Q(n25), .QN(\fpu_add_frac_dp/n2388 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[35] ( .D(\fpu_add_frac_dp/n4132 ),
.CLK(n1501), .Q(n24) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[34] ( .D(\fpu_add_frac_dp/n4133 ),
.CLK(n1501), .Q(n9) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[33] ( .D(\fpu_add_frac_dp/n4134 ),
.CLK(n1501), .Q(n8) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[32] ( .D(\fpu_add_frac_dp/n4135 ),
.CLK(n1501), .Q(n7) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[31] ( .D(\fpu_add_frac_dp/n4136 ),
.CLK(n1501), .Q(n114) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[30] ( .D(\fpu_add_frac_dp/n4137 ),
.CLK(n1501), .Q(n113) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[29] ( .D(\fpu_add_frac_dp/n4138 ),
.CLK(n1501), .Q(n112) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[28] ( .D(\fpu_add_frac_dp/n4139 ),
.CLK(n1501), .Q(n639) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[27] ( .D(\fpu_add_frac_dp/n4140 ),
.CLK(n1501), .Q(n277) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[26] ( .D(\fpu_add_frac_dp/n4141 ),
.CLK(n1501), .Q(n637) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[25] ( .D(\fpu_add_frac_dp/n4142 ),
.CLK(n1501), .Q(n276) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[24] ( .D(\fpu_add_frac_dp/n4143 ),
.CLK(n1501), .Q(n636) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[23] ( .D(\fpu_add_frac_dp/n4144 ),
.CLK(n1501), .Q(n275) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[22] ( .D(\fpu_add_frac_dp/n4145 ),
.CLK(n1501), .Q(n635) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[21] ( .D(\fpu_add_frac_dp/n4146 ),
.CLK(n1500), .Q(n274) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[20] ( .D(\fpu_add_frac_dp/n4147 ),
.CLK(n1500), .Q(n634) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[19] ( .D(\fpu_add_frac_dp/n4148 ),
.CLK(n1500), .Q(n273) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[18] ( .D(\fpu_add_frac_dp/n4149 ),
.CLK(n1500), .Q(n633) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[17] ( .D(\fpu_add_frac_dp/n4150 ),
.CLK(n1500), .Q(n272) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[16] ( .D(\fpu_add_frac_dp/n4151 ),
.CLK(n1500), .Q(n122) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[15] ( .D(\fpu_add_frac_dp/n4152 ),
.CLK(n1500), .Q(n53) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[14] ( .D(\fpu_add_frac_dp/n4153 ),
.CLK(n1500), .Q(n121) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[13] ( .D(\fpu_add_frac_dp/n4154 ),
.CLK(n1500), .Q(n52) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[12] ( .D(\fpu_add_frac_dp/n4155 ),
.CLK(n1500), .Q(n120) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[11] ( .D(\fpu_add_frac_dp/n4156 ),
.CLK(n1500), .Q(n39) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[10] ( .D(\fpu_add_frac_dp/n4157 ),
.CLK(n1500), .Q(n81) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[9] ( .D(\fpu_add_frac_dp/n4158 ),
.CLK(n1500), .Q(n32) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[8] ( .D(\fpu_add_frac_dp/n4159 ),
.CLK(n1500), .Q(n80) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[7] ( .D(\fpu_add_frac_dp/n4160 ),
.CLK(n1499), .Q(n31) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[6] ( .D(\fpu_add_frac_dp/n4161 ),
.CLK(n1499), .Q(n79) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[5] ( .D(\fpu_add_frac_dp/n4162 ),
.CLK(n1499), .Q(n30) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[4] ( .D(\fpu_add_frac_dp/n4163 ),
.CLK(n1499), .Q(n11) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[3] ( .D(\fpu_add_frac_dp/n4164 ),
.CLK(n1499), .Q(\fpu_add_frac_dp/a1stg_in2[3] ), .QN(
\fpu_add_frac_dp/n895 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[2] ( .D(\fpu_add_frac_dp/n4165 ),
.CLK(n1499), .Q(n10) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[1] ( .D(\fpu_add_frac_dp/n4166 ),
.CLK(n1499), .Q(n170) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in2/q_reg[0] ( .D(\fpu_add_frac_dp/n4167 ),
.CLK(n1499), .Q(n36), .QN(\fpu_add_frac_dp/n898 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[54] ( .D(\fpu_add_frac_dp/n4168 ),
.CLK(n1499), .Q(n283) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[53] ( .D(\fpu_add_frac_dp/n4169 ),
.CLK(n1499), .Q(n747), .QN(\fpu_add_frac_dp/n900 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[52] ( .D(\fpu_add_frac_dp/n4170 ),
.CLK(n1499), .Q(n548), .QN(\fpu_add_frac_dp/n5643 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[51] ( .D(\fpu_add_frac_dp/n4171 ),
.CLK(n1499), .Q(n340), .QN(\fpu_add_frac_dp/n901 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[50] ( .D(\fpu_add_frac_dp/n4172 ),
.CLK(n1499), .Q(\fpu_add_frac_dp/n2350 ), .QN(n1158) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[49] ( .D(\fpu_add_frac_dp/n4173 ),
.CLK(n1499), .Q(n917), .QN(\fpu_add_frac_dp/n2415 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[48] ( .D(\fpu_add_frac_dp/n4174 ),
.CLK(n1498), .Q(\fpu_add_frac_dp/n2476 ), .QN(\fpu_add_frac_dp/n1070 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[47] ( .D(\fpu_add_frac_dp/n4175 ),
.CLK(n1498), .Q(n1202), .QN(\fpu_add_frac_dp/n903 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[46] ( .D(\fpu_add_frac_dp/n4176 ),
.CLK(n1498), .Q(n1198), .QN(\fpu_add_frac_dp/n904 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[45] ( .D(\fpu_add_frac_dp/n4177 ),
.CLK(n1498), .Q(n677), .QN(\fpu_add_frac_dp/n2373 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[44] ( .D(\fpu_add_frac_dp/n4178 ),
.CLK(n1498), .Q(n57), .QN(\fpu_add_frac_dp/n905 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[43] ( .D(\fpu_add_frac_dp/n4179 ),
.CLK(n1498), .Q(n848), .QN(\fpu_add_frac_dp/n2540 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[42] ( .D(\fpu_add_frac_dp/n4180 ),
.CLK(n1498), .Q(\fpu_add_frac_dp/n2462 ), .QN(\fpu_add_frac_dp/n1067 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[41] ( .D(\fpu_add_frac_dp/n4181 ),
.CLK(n1498), .Q(n1129), .QN(\fpu_add_frac_dp/n907 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[40] ( .D(\fpu_add_frac_dp/n4182 ),
.CLK(n1498), .Q(n709), .QN(\fpu_add_frac_dp/n908 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[39] ( .D(\fpu_add_frac_dp/n4183 ),
.CLK(n1498), .Q(\fpu_add_frac_dp/n2452 ), .QN(n1079) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[38] ( .D(\fpu_add_frac_dp/n4184 ),
.CLK(n1498), .Q(n46) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[37] ( .D(\fpu_add_frac_dp/n4185 ),
.CLK(n1498), .Q(n125) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[36] ( .D(\fpu_add_frac_dp/n4186 ),
.CLK(n1498), .Q(n292), .QN(\fpu_add_frac_dp/n2408 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[35] ( .D(\fpu_add_frac_dp/n4187 ),
.CLK(n1498), .Q(n1215), .QN(\fpu_add_frac_dp/n911 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[34] ( .D(\fpu_add_frac_dp/n4188 ),
.CLK(n1497), .Q(n857), .QN(\fpu_add_frac_dp/n912 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[33] ( .D(\fpu_add_frac_dp/n4189 ),
.CLK(n1497), .Q(\fpu_add_frac_dp/n2295 ), .QN(n1067) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[32] ( .D(\fpu_add_frac_dp/n4190 ),
.CLK(n1497), .Q(n855), .QN(\fpu_add_frac_dp/n913 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[31] ( .D(\fpu_add_frac_dp/n4191 ),
.CLK(n1497), .Q(n704) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[30] ( .D(\fpu_add_frac_dp/n4192 ),
.CLK(n1497), .Q(\fpu_add_frac_dp/n2445 ), .QN(n989) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[29] ( .D(\fpu_add_frac_dp/n4193 ),
.CLK(n1497), .Q(n856), .QN(\fpu_add_frac_dp/n2367 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[28] ( .D(\fpu_add_frac_dp/n4194 ),
.CLK(n1497), .Q(n54) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[27] ( .D(\fpu_add_frac_dp/n4195 ),
.CLK(n1497), .Q(n647) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[26] ( .D(\fpu_add_frac_dp/n4196 ),
.CLK(n1497), .Q(n550), .QN(\fpu_add_frac_dp/n917 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[25] ( .D(\fpu_add_frac_dp/n4197 ),
.CLK(n1497), .Q(n1209), .QN(\fpu_add_frac_dp/n918 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[24] ( .D(\fpu_add_frac_dp/n4198 ),
.CLK(n1497), .Q(\fpu_add_frac_dp/n2488 ), .QN(\fpu_add_frac_dp/n1056 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[23] ( .D(\fpu_add_frac_dp/n4199 ),
.CLK(n1497), .Q(n1206), .QN(\fpu_add_frac_dp/n919 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[22] ( .D(\fpu_add_frac_dp/n4200 ),
.CLK(n1497), .Q(n1204), .QN(\fpu_add_frac_dp/n920 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[21] ( .D(\fpu_add_frac_dp/n4201 ),
.CLK(n1502), .Q(\fpu_add_frac_dp/n2444 ), .QN(n1078) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[20] ( .D(\fpu_add_frac_dp/n4202 ),
.CLK(n1518), .Q(n1143), .QN(\fpu_add_frac_dp/n921 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[19] ( .D(\fpu_add_frac_dp/n4203 ),
.CLK(n1518), .Q(n1197), .QN(\fpu_add_frac_dp/n922 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[18] ( .D(\fpu_add_frac_dp/n4204 ),
.CLK(n1518), .Q(n1153), .QN(\fpu_add_frac_dp/n2439 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[17] ( .D(\fpu_add_frac_dp/n4205 ),
.CLK(n1518), .Q(n853), .QN(\fpu_add_frac_dp/n2372 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[16] ( .D(\fpu_add_frac_dp/n4206 ),
.CLK(n1518), .Q(n703), .QN(\fpu_add_frac_dp/n2305 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[15] ( .D(\fpu_add_frac_dp/n4207 ),
.CLK(n1518), .Q(\fpu_add_frac_dp/n2453 ), .QN(\fpu_add_frac_dp/n1050 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[14] ( .D(\fpu_add_frac_dp/n4208 ),
.CLK(n1518), .Q(n988), .QN(\fpu_add_frac_dp/n2454 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[13] ( .D(\fpu_add_frac_dp/n4209 ),
.CLK(n1518), .Q(n1184), .QN(\fpu_add_frac_dp/n2368 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[12] ( .D(\fpu_add_frac_dp/n4210 ),
.CLK(n1518), .Q(\fpu_add_frac_dp/n2484 ), .QN(\fpu_add_frac_dp/n1048 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[11] ( .D(\fpu_add_frac_dp/n4211 ),
.CLK(n1518), .Q(n854), .QN(\fpu_add_frac_dp/n927 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[10] ( .D(\fpu_add_frac_dp/n4212 ),
.CLK(n1517), .Q(n145), .QN(\fpu_add_frac_dp/n928 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[9] ( .D(\fpu_add_frac_dp/n4213 ),
.CLK(n1517), .Q(n577), .QN(\fpu_add_frac_dp/n2544 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[8] ( .D(\fpu_add_frac_dp/n4214 ),
.CLK(n1517), .Q(n1146), .QN(\fpu_add_frac_dp/n929 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[7] ( .D(\fpu_add_frac_dp/n4215 ),
.CLK(n1517), .Q(n1195), .QN(\fpu_add_frac_dp/n930 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[6] ( .D(\fpu_add_frac_dp/n4216 ),
.CLK(n1517), .Q(n1133), .QN(\fpu_add_frac_dp/n931 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[5] ( .D(\fpu_add_frac_dp/n4217 ),
.CLK(n1517), .Q(n1128), .QN(\fpu_add_frac_dp/n932 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[4] ( .D(\fpu_add_frac_dp/n4218 ),
.CLK(n1517), .Q(n695), .QN(\fpu_add_frac_dp/n933 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[3] ( .D(\fpu_add_frac_dp/n4219 ),
.CLK(n1517), .Q(\fpu_add_frac_dp/n2296 ), .QN(\fpu_add_frac_dp/n1045 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[2] ( .D(\fpu_add_frac_dp/n4220 ),
.CLK(n1517), .Q(n745), .QN(\fpu_add_frac_dp/n934 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[1] ( .D(\fpu_add_frac_dp/n4221 ),
.CLK(n1517), .Q(n1185), .QN(\fpu_add_frac_dp/n935 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1a/q_reg[0] ( .D(\fpu_add_frac_dp/n4222 ),
.CLK(n1517), .Q(\fpu_add_frac_dp/n2493 ), .QN(\fpu_add_frac_dp/n1044 )
);
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[62] ( .D(\fpu_add_frac_dp/n4223 ),
.CLK(n1517), .Q(n715) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[61] ( .D(\fpu_add_frac_dp/n4224 ),
.CLK(n1517), .Q(n1191), .QN(\fpu_add_frac_dp/n937 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[60] ( .D(\fpu_add_frac_dp/n4225 ),
.CLK(n1517), .Q(n712) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[59] ( .D(\fpu_add_frac_dp/n4226 ),
.CLK(n1516), .Q(n713) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[58] ( .D(\fpu_add_frac_dp/n4227 ),
.CLK(n1516), .Q(n1190), .QN(\fpu_add_frac_dp/n940 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[57] ( .D(\fpu_add_frac_dp/n4228 ),
.CLK(n1516), .Q(n714) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[56] ( .D(\fpu_add_frac_dp/n4229 ),
.CLK(n1516), .Q(n1189), .QN(\fpu_add_frac_dp/n942 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[55] ( .D(\fpu_add_frac_dp/n4230 ),
.CLK(n1516), .Q(n1188), .QN(\fpu_add_frac_dp/n943 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[54] ( .D(\fpu_add_frac_dp/n4231 ),
.CLK(n1516), .Q(n705), .QN(\fpu_add_frac_dp/n2534 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[53] ( .D(\fpu_add_frac_dp/n4232 ),
.CLK(n1516), .Q(n689), .QN(\fpu_add_frac_dp/n945 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[52] ( .D(\fpu_add_frac_dp/n4233 ),
.CLK(n1516), .Q(n688), .QN(\fpu_add_frac_dp/n2521 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[51] ( .D(\fpu_add_frac_dp/n4234 ),
.CLK(n1516), .Q(n206) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[50] ( .D(\fpu_add_frac_dp/n4235 ),
.CLK(n1516), .Q(n216) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[49] ( .D(\fpu_add_frac_dp/n4236 ),
.CLK(n1516), .Q(n215) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[48] ( .D(\fpu_add_frac_dp/n4237 ),
.CLK(n1516), .Q(n621) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[47] ( .D(\fpu_add_frac_dp/n4238 ),
.CLK(n1516), .Q(n620) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[46] ( .D(\fpu_add_frac_dp/n4239 ),
.CLK(n1516), .Q(n619) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[45] ( .D(\fpu_add_frac_dp/n4240 ),
.CLK(n1515), .Q(n214) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[44] ( .D(\fpu_add_frac_dp/n4241 ),
.CLK(n1515), .Q(n213) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[43] ( .D(\fpu_add_frac_dp/n4242 ),
.CLK(n1515), .Q(n212) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[42] ( .D(\fpu_add_frac_dp/n4243 ),
.CLK(n1515), .Q(n618) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[41] ( .D(\fpu_add_frac_dp/n4244 ),
.CLK(n1515), .Q(n617) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[40] ( .D(\fpu_add_frac_dp/n4245 ),
.CLK(n1515), .Q(n616) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[39] ( .D(\fpu_add_frac_dp/n4246 ),
.CLK(n1515), .Q(n211) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[38] ( .D(\fpu_add_frac_dp/n4247 ),
.CLK(n1515), .Q(n210) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[37] ( .D(\fpu_add_frac_dp/n4248 ),
.CLK(n1515), .Q(n209) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[36] ( .D(\fpu_add_frac_dp/n4249 ),
.CLK(n1515), .Q(n615) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[35] ( .D(\fpu_add_frac_dp/n4250 ),
.CLK(n1515), .Q(n614) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[34] ( .D(\fpu_add_frac_dp/n4251 ),
.CLK(n1515), .Q(n99) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[33] ( .D(\fpu_add_frac_dp/n4252 ),
.CLK(n1515), .Q(n208) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[32] ( .D(\fpu_add_frac_dp/n4253 ),
.CLK(n1515), .Q(n176), .QN(\fpu_add_frac_dp/n965 ) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[31] ( .D(\fpu_add_frac_dp/n4254 ),
.CLK(n1514), .Q(n699) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[30] ( .D(\fpu_add_frac_dp/n4255 ),
.CLK(n1514), .Q(n698) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[29] ( .D(\fpu_add_frac_dp/n4256 ),
.CLK(n1514), .Q(n644) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[28] ( .D(\fpu_add_frac_dp/n4257 ),
.CLK(n1514), .Q(n207) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[27] ( .D(\fpu_add_frac_dp/n4258 ),
.CLK(n1514), .Q(n611) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[26] ( .D(\fpu_add_frac_dp/n4259 ),
.CLK(n1514), .Q(n194) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[25] ( .D(\fpu_add_frac_dp/n4260 ),
.CLK(n1514), .Q(n610) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[24] ( .D(\fpu_add_frac_dp/n4261 ),
.CLK(n1514), .Q(n193) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[23] ( .D(\fpu_add_frac_dp/n4262 ),
.CLK(n1514), .Q(n609) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[22] ( .D(\fpu_add_frac_dp/n4263 ),
.CLK(n1514), .Q(n192) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[21] ( .D(\fpu_add_frac_dp/n4264 ),
.CLK(n1514), .Q(n608) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[20] ( .D(\fpu_add_frac_dp/n4265 ),
.CLK(n1514), .Q(n191) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[19] ( .D(\fpu_add_frac_dp/n4266 ),
.CLK(n1514), .Q(n607) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[18] ( .D(\fpu_add_frac_dp/n4267 ),
.CLK(n1514), .Q(n190) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[17] ( .D(\fpu_add_frac_dp/n4268 ),
.CLK(n1513), .Q(n606) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[16] ( .D(\fpu_add_frac_dp/n4269 ),
.CLK(n1513), .Q(n189) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[15] ( .D(\fpu_add_frac_dp/n4270 ),
.CLK(n1513), .Q(n605) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[14] ( .D(\fpu_add_frac_dp/n4271 ),
.CLK(n1513), .Q(n188) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[13] ( .D(\fpu_add_frac_dp/n4272 ),
.CLK(n1513), .Q(n604) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[12] ( .D(\fpu_add_frac_dp/n4273 ),
.CLK(n1513), .Q(n187) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[11] ( .D(\fpu_add_frac_dp/n4274 ),
.CLK(n1513), .Q(n603) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[10] ( .D(\fpu_add_frac_dp/n4275 ),
.CLK(n1513), .Q(n186) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[9] ( .D(\fpu_add_frac_dp/n4276 ),
.CLK(n1513), .Q(n602) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[8] ( .D(\fpu_add_frac_dp/n4277 ),
.CLK(n1513), .Q(n185) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[7] ( .D(\fpu_add_frac_dp/n4278 ),
.CLK(n1513), .Q(n601) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[6] ( .D(\fpu_add_frac_dp/n4279 ),
.CLK(n1513), .Q(n184) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[5] ( .D(\fpu_add_frac_dp/n4280 ),
.CLK(n1513), .Q(n600) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[4] ( .D(\fpu_add_frac_dp/n4281 ),
.CLK(n1512), .Q(n183) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[3] ( .D(\fpu_add_frac_dp/n4282 ),
.CLK(n1512), .Q(n599) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[2] ( .D(\fpu_add_frac_dp/n4283 ),
.CLK(n1512), .Q(n182) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[1] ( .D(\fpu_add_frac_dp/n4284 ),
.CLK(n1512), .Q(n93) );
DFFX1 \fpu_add_frac_dp/i_a1stg_in1/q_reg[0] ( .D(\fpu_add_frac_dp/n4285 ),
.CLK(n1512), .Q(n612) );
LATCHX1 \fpu_add_frac_dp/ckbuf_add_frac_dp/clken_reg ( .CLK(
\fpu_add_frac_dp/n2189 ), .D(\fpu_add_frac_dp/ckbuf_add_frac_dp/N1 ),
.Q(\fpu_add_frac_dp/ckbuf_add_frac_dp/clken ), .QN(
\fpu_add_frac_dp/n998 ) );
OR2X1 U2 ( .IN1(n4114), .IN2(\fpu_add_ctl/n210 ), .Q(n586) );
OR2X1 U3 ( .IN1(n2590), .IN2(n1745), .Q(n590) );
OR2X1 U4 ( .IN1(\fpu_add_frac_dp/n132 ), .IN2(\fpu_add_frac_dp/n134 ), .Q(
n628) );
INVX0 U5 ( .INP(\fpu_add_frac_dp/n5617 ), .ZN(n1305) );
INVX0 U6 ( .INP(\fpu_add_frac_dp/n5617 ), .ZN(n1306) );
INVX0 U7 ( .INP(\fpu_add_frac_dp/n5617 ), .ZN(n1307) );
INVX0 U8 ( .INP(\fpu_add_frac_dp/n5616 ), .ZN(n1308) );
INVX0 U9 ( .INP(\fpu_add_frac_dp/n5616 ), .ZN(n1309) );
INVX0 U10 ( .INP(\fpu_add_frac_dp/n5616 ), .ZN(n1310) );
INVX0 U11 ( .INP(n3973), .ZN(n1311) );
INVX0 U12 ( .INP(n3973), .ZN(n1312) );
INVX0 U13 ( .INP(n3973), .ZN(n1313) );
INVX0 U14 ( .INP(n3973), .ZN(n1314) );
INVX0 U15 ( .INP(n628), .ZN(n1315) );
INVX0 U16 ( .INP(n628), .ZN(n1316) );
INVX0 U17 ( .INP(n628), .ZN(n1317) );
INVX0 U18 ( .INP(n628), .ZN(n1318) );
INVX0 U19 ( .INP(n590), .ZN(n1319) );
INVX0 U20 ( .INP(n590), .ZN(n1320) );
INVX0 U21 ( .INP(n590), .ZN(n1321) );
INVX0 U22 ( .INP(n590), .ZN(n1322) );
INVX0 U23 ( .INP(\fpu_add_ctl/n1 ), .ZN(n1323) );
INVX0 U24 ( .INP(\fpu_add_ctl/n1 ), .ZN(n1324) );
INVX0 U25 ( .INP(\fpu_add_ctl/n1 ), .ZN(n1325) );
INVX0 U26 ( .INP(\fpu_add_frac_dp/n5614 ), .ZN(n1326) );
INVX0 U27 ( .INP(\fpu_add_frac_dp/n5614 ), .ZN(n1327) );
INVX0 U28 ( .INP(\fpu_add_frac_dp/n5614 ), .ZN(n1328) );
INVX0 U29 ( .INP(n1933), .ZN(n1329) );
INVX0 U30 ( .INP(n1933), .ZN(n1330) );
INVX0 U31 ( .INP(n1933), .ZN(n1331) );
INVX0 U32 ( .INP(n1933), .ZN(n1332) );
INVX0 U33 ( .INP(n586), .ZN(n1333) );
INVX0 U34 ( .INP(n586), .ZN(n1334) );
INVX0 U35 ( .INP(n586), .ZN(n1335) );
INVX0 U36 ( .INP(n586), .ZN(n1336) );
INVX0 U37 ( .INP(n4057), .ZN(n1337) );
INVX0 U38 ( .INP(n4057), .ZN(n1338) );
INVX0 U39 ( .INP(n4057), .ZN(n1339) );
INVX0 U40 ( .INP(n4057), .ZN(n1340) );
INVX2 U41 ( .INP(n1811), .ZN(n1594) );
INVX2 U42 ( .INP(n1598), .ZN(n1597) );
NOR2X1 U43 ( .IN1(n584), .IN2(n1745), .QN(n2994) );
NOR2X1 U44 ( .IN1(n129), .IN2(n295), .QN(n1596) );
INVX2 U45 ( .INP(n3071), .ZN(n3065) );
NAND2X1 U46 ( .IN1(n3156), .IN2(n3157), .QN(\fpu_add_frac_dp/n1509 ) );
INVX0 U47 ( .INP(n1450), .ZN(n1440) );
INVX0 U48 ( .INP(n1450), .ZN(n1439) );
INVX0 U49 ( .INP(n1450), .ZN(n1436) );
INVX0 U50 ( .INP(n1450), .ZN(n1437) );
INVX0 U51 ( .INP(n1450), .ZN(n1438) );
INVX0 U52 ( .INP(n1450), .ZN(n1441) );
INVX0 U53 ( .INP(n1473), .ZN(n1462) );
INVX0 U54 ( .INP(n1450), .ZN(n1443) );
INVX0 U55 ( .INP(n1450), .ZN(n1444) );
INVX0 U56 ( .INP(n1450), .ZN(n1445) );
INVX0 U57 ( .INP(n1450), .ZN(n1448) );
INVX0 U58 ( .INP(n1450), .ZN(n1447) );
INVX0 U59 ( .INP(n1450), .ZN(n1446) );
INVX0 U60 ( .INP(n1450), .ZN(n1442) );
INVX0 U61 ( .INP(n1450), .ZN(n1435) );
INVX0 U62 ( .INP(n1473), .ZN(n1463) );
INVX0 U63 ( .INP(n1473), .ZN(n1464) );
INVX0 U64 ( .INP(n1473), .ZN(n1472) );
INVX0 U65 ( .INP(n1473), .ZN(n1465) );
INVX0 U66 ( .INP(n1473), .ZN(n1466) );
INVX0 U67 ( .INP(n1473), .ZN(n1467) );
INVX0 U68 ( .INP(n1473), .ZN(n1468) );
INVX0 U69 ( .INP(n1473), .ZN(n1469) );
INVX0 U70 ( .INP(n1473), .ZN(n1470) );
INVX0 U71 ( .INP(n1473), .ZN(n1471) );
INVX0 U72 ( .INP(n1431), .ZN(n1430) );
INVX0 U73 ( .INP(n1434), .ZN(n1389) );
INVX0 U74 ( .INP(n1432), .ZN(n1415) );
INVX0 U75 ( .INP(n1434), .ZN(n1395) );
INVX0 U76 ( .INP(n1434), .ZN(n1390) );
INVX0 U77 ( .INP(n1434), .ZN(n1394) );
INVX0 U78 ( .INP(n1434), .ZN(n1391) );
INVX0 U79 ( .INP(n1434), .ZN(n1392) );
INVX0 U80 ( .INP(n1434), .ZN(n1393) );
INVX0 U81 ( .INP(n1433), .ZN(n1396) );
INVX0 U82 ( .INP(n1433), .ZN(n1398) );
INVX0 U83 ( .INP(n1433), .ZN(n1403) );
INVX0 U84 ( .INP(n1433), .ZN(n1402) );
INVX0 U85 ( .INP(n1433), .ZN(n1399) );
INVX0 U86 ( .INP(n1433), .ZN(n1401) );
INVX0 U87 ( .INP(n1433), .ZN(n1400) );
INVX0 U88 ( .INP(n1433), .ZN(n1397) );
INVX0 U89 ( .INP(n1433), .ZN(n1405) );
INVX0 U90 ( .INP(n1433), .ZN(n1404) );
INVX0 U91 ( .INP(n1433), .ZN(n1406) );
INVX0 U92 ( .INP(n1432), .ZN(n1409) );
INVX0 U93 ( .INP(n1432), .ZN(n1408) );
INVX0 U94 ( .INP(n1433), .ZN(n1407) );
INVX0 U95 ( .INP(n1432), .ZN(n1410) );
INVX0 U96 ( .INP(n1432), .ZN(n1411) );
INVX0 U97 ( .INP(n1432), .ZN(n1412) );
INVX0 U98 ( .INP(n1432), .ZN(n1413) );
INVX0 U99 ( .INP(n1432), .ZN(n1414) );
INVX0 U100 ( .INP(n1432), .ZN(n1416) );
INVX0 U101 ( .INP(n1434), .ZN(n1388) );
INVX0 U102 ( .INP(n1434), .ZN(n1387) );
INVX0 U103 ( .INP(n1434), .ZN(n1386) );
INVX0 U104 ( .INP(n1434), .ZN(n1385) );
INVX0 U105 ( .INP(n1434), .ZN(n1384) );
INVX0 U106 ( .INP(n1432), .ZN(n1418) );
INVX0 U107 ( .INP(n1431), .ZN(n1420) );
INVX0 U108 ( .INP(n1431), .ZN(n1422) );
INVX0 U109 ( .INP(n1431), .ZN(n1423) );
INVX0 U110 ( .INP(n1431), .ZN(n1424) );
INVX0 U111 ( .INP(n1431), .ZN(n1425) );
INVX0 U112 ( .INP(n1431), .ZN(n1421) );
INVX0 U113 ( .INP(n1431), .ZN(n1426) );
INVX0 U114 ( .INP(n1431), .ZN(n1427) );
INVX0 U115 ( .INP(n1431), .ZN(n1428) );
INVX0 U116 ( .INP(n1431), .ZN(n1429) );
INVX0 U117 ( .INP(n1432), .ZN(n1419) );
INVX0 U118 ( .INP(n1432), .ZN(n1417) );
INVX0 U119 ( .INP(n2046), .ZN(n1379) );
INVX0 U120 ( .INP(n2046), .ZN(n1380) );
INVX0 U121 ( .INP(n2046), .ZN(n1381) );
INVX0 U122 ( .INP(n2046), .ZN(n1382) );
INVX0 U123 ( .INP(n1431), .ZN(n1383) );
INVX0 U124 ( .INP(n1450), .ZN(n1449) );
INVX0 U125 ( .INP(n1473), .ZN(n1461) );
INVX0 U126 ( .INP(n4000), .ZN(n1473) );
INVX0 U127 ( .INP(n3986), .ZN(n1451) );
INVX0 U128 ( .INP(n3986), .ZN(n1452) );
INVX0 U129 ( .INP(n3986), .ZN(n1453) );
INVX0 U130 ( .INP(n3986), .ZN(n1454) );
INVX0 U131 ( .INP(n3986), .ZN(n1455) );
INVX0 U132 ( .INP(n3986), .ZN(n1456) );
INVX0 U133 ( .INP(n3986), .ZN(n1457) );
INVX0 U134 ( .INP(n3986), .ZN(n1458) );
INVX0 U135 ( .INP(n3986), .ZN(n1459) );
INVX0 U136 ( .INP(n3986), .ZN(n1460) );
INVX0 U137 ( .INP(n1746), .ZN(n1450) );
INVX0 U138 ( .INP(n1379), .ZN(n1431) );
INVX0 U139 ( .INP(n1380), .ZN(n1432) );
INVX0 U140 ( .INP(n1381), .ZN(n1433) );
INVX0 U141 ( .INP(n1382), .ZN(n1434) );
INVX0 U142 ( .INP(n1357), .ZN(n1348) );
INVX0 U143 ( .INP(n1357), .ZN(n1347) );
INVX0 U144 ( .INP(n1357), .ZN(n1345) );
INVX0 U145 ( .INP(n1357), .ZN(n1344) );
INVX0 U146 ( .INP(n1357), .ZN(n1346) );
INVX0 U147 ( .INP(n1357), .ZN(n1349) );
INVX0 U148 ( .INP(n1357), .ZN(n1352) );
INVX0 U149 ( .INP(n1357), .ZN(n1351) );
INVX0 U150 ( .INP(n1357), .ZN(n1350) );
INVX0 U151 ( .INP(n1357), .ZN(n1353) );
INVX0 U152 ( .INP(n1357), .ZN(n1354) );
INVX0 U153 ( .INP(n1357), .ZN(n1356) );
INVX0 U154 ( .INP(n1357), .ZN(n1355) );
INVX0 U155 ( .INP(n1357), .ZN(n1343) );
INVX0 U156 ( .INP(n1377), .ZN(n1375) );
INVX0 U157 ( .INP(n1377), .ZN(n1374) );
INVX0 U158 ( .INP(n1377), .ZN(n1373) );
INVX0 U159 ( .INP(n1377), .ZN(n1372) );
INVX0 U160 ( .INP(n1377), .ZN(n1371) );
INVX0 U161 ( .INP(n1377), .ZN(n1370) );
INVX0 U162 ( .INP(n1377), .ZN(n1369) );
INVX0 U163 ( .INP(n1377), .ZN(n1368) );
INVX0 U164 ( .INP(n1377), .ZN(n1367) );
INVX0 U165 ( .INP(n1377), .ZN(n1366) );
INVX0 U166 ( .INP(n1378), .ZN(n1365) );
INVX0 U167 ( .INP(n1378), .ZN(n1364) );
INVX0 U168 ( .INP(n1378), .ZN(n1363) );
INVX0 U169 ( .INP(n1378), .ZN(n1362) );
INVX0 U170 ( .INP(n1378), .ZN(n1361) );
INVX0 U171 ( .INP(n1378), .ZN(n1360) );
INVX0 U172 ( .INP(n1378), .ZN(n1359) );
INVX0 U173 ( .INP(n1378), .ZN(n1358) );
INVX0 U174 ( .INP(n1561), .ZN(n1514) );
INVX0 U175 ( .INP(n1561), .ZN(n1515) );
INVX0 U176 ( .INP(n1561), .ZN(n1516) );
INVX0 U177 ( .INP(n1561), .ZN(n1517) );
INVX0 U178 ( .INP(n1562), .ZN(n1498) );
INVX0 U179 ( .INP(n1562), .ZN(n1499) );
INVX0 U180 ( .INP(n1562), .ZN(n1500) );
INVX0 U181 ( .INP(n1562), .ZN(n1501) );
INVX0 U182 ( .INP(n1562), .ZN(n1502) );
INVX0 U183 ( .INP(n1562), .ZN(n1503) );
INVX0 U184 ( .INP(n1562), .ZN(n1504) );
INVX0 U185 ( .INP(n1562), .ZN(n1505) );
INVX0 U186 ( .INP(n1562), .ZN(n1506) );
INVX0 U187 ( .INP(n1563), .ZN(n1497) );
INVX0 U188 ( .INP(n1563), .ZN(n1494) );
INVX0 U189 ( .INP(n1563), .ZN(n1495) );
INVX0 U190 ( .INP(n1563), .ZN(n1496) );
INVX0 U191 ( .INP(n1564), .ZN(n1482) );
INVX0 U192 ( .INP(n1564), .ZN(n1483) );
INVX0 U193 ( .INP(n1564), .ZN(n1484) );
INVX0 U194 ( .INP(n1564), .ZN(n1485) );
INVX0 U195 ( .INP(n1558), .ZN(n1546) );
INVX0 U196 ( .INP(n1558), .ZN(n1547) );
INVX0 U197 ( .INP(n1563), .ZN(n1488) );
INVX0 U198 ( .INP(n1563), .ZN(n1489) );
INVX0 U199 ( .INP(n1563), .ZN(n1490) );
INVX0 U200 ( .INP(n1563), .ZN(n1491) );
INVX0 U201 ( .INP(n1563), .ZN(n1492) );
INVX0 U202 ( .INP(n1563), .ZN(n1493) );
INVX0 U203 ( .INP(n1558), .ZN(n1554) );
INVX0 U204 ( .INP(n1558), .ZN(n1553) );
INVX0 U205 ( .INP(n1563), .ZN(n1486) );
INVX0 U206 ( .INP(n1564), .ZN(n1480) );
INVX0 U207 ( .INP(n1563), .ZN(n1487) );
INVX0 U208 ( .INP(n1561), .ZN(n1513) );
INVX0 U209 ( .INP(n1562), .ZN(n1507) );
INVX0 U210 ( .INP(n1562), .ZN(n1508) );
INVX0 U211 ( .INP(n1562), .ZN(n1509) );
INVX0 U212 ( .INP(n1561), .ZN(n1511) );
INVX0 U213 ( .INP(n1561), .ZN(n1512) );
INVX0 U214 ( .INP(n1561), .ZN(n1510) );
INVX0 U215 ( .INP(n1559), .ZN(n1544) );
INVX0 U216 ( .INP(n1559), .ZN(n1542) );
INVX0 U217 ( .INP(n1559), .ZN(n1545) );
INVX0 U218 ( .INP(n1558), .ZN(n1556) );
INVX0 U219 ( .INP(n1559), .ZN(n1543) );
INVX0 U220 ( .INP(n1559), .ZN(n1539) );
INVX0 U221 ( .INP(n1559), .ZN(n1540) );
INVX0 U222 ( .INP(n1559), .ZN(n1541) );
INVX0 U223 ( .INP(n1560), .ZN(n1527) );
INVX0 U224 ( .INP(n1558), .ZN(n1552) );
INVX0 U225 ( .INP(n1558), .ZN(n1548) );
INVX0 U226 ( .INP(n1558), .ZN(n1549) );
INVX0 U227 ( .INP(n1558), .ZN(n1550) );
INVX0 U228 ( .INP(n1558), .ZN(n1551) );
INVX0 U229 ( .INP(n1559), .ZN(n1534) );
INVX0 U230 ( .INP(n1564), .ZN(n1481) );
INVX0 U231 ( .INP(n1558), .ZN(n1555) );
INVX0 U232 ( .INP(n1560), .ZN(n1533) );
INVX0 U233 ( .INP(n1559), .ZN(n1535) );
INVX0 U234 ( .INP(n1560), .ZN(n1532) );
INVX0 U235 ( .INP(n1561), .ZN(n1519) );
INVX0 U236 ( .INP(n1561), .ZN(n1518) );
INVX0 U237 ( .INP(n1559), .ZN(n1538) );
INVX0 U238 ( .INP(n1559), .ZN(n1537) );
INVX0 U239 ( .INP(n1561), .ZN(n1520) );
INVX0 U240 ( .INP(n1561), .ZN(n1521) );
INVX0 U241 ( .INP(n1560), .ZN(n1522) );
INVX0 U242 ( .INP(n1560), .ZN(n1523) );
INVX0 U243 ( .INP(n1560), .ZN(n1524) );
INVX0 U244 ( .INP(n1560), .ZN(n1525) );
INVX0 U245 ( .INP(n1560), .ZN(n1526) );
INVX0 U246 ( .INP(n1560), .ZN(n1531) );
INVX0 U247 ( .INP(n1559), .ZN(n1536) );
INVX0 U248 ( .INP(n1560), .ZN(n1530) );
INVX0 U249 ( .INP(n1560), .ZN(n1528) );
INVX0 U250 ( .INP(n1560), .ZN(n1529) );
INVX0 U251 ( .INP(n1564), .ZN(n1479) );
INVX0 U252 ( .INP(n1564), .ZN(n1474) );
INVX0 U253 ( .INP(n1564), .ZN(n1475) );
INVX0 U254 ( .INP(n1564), .ZN(n1477) );
INVX0 U255 ( .INP(n1564), .ZN(n1478) );
INVX0 U256 ( .INP(n1564), .ZN(n1476) );
INVX0 U257 ( .INP(n1377), .ZN(n1376) );
INVX0 U258 ( .INP(n1586), .ZN(n1578) );
INVX0 U259 ( .INP(n1586), .ZN(n1579) );
INVX0 U260 ( .INP(n1586), .ZN(n1580) );
INVX0 U261 ( .INP(n1586), .ZN(n1581) );
INVX0 U262 ( .INP(n1586), .ZN(n1582) );
INVX0 U263 ( .INP(n1586), .ZN(n1583) );
INVX0 U264 ( .INP(n1586), .ZN(n1584) );
INVX0 U265 ( .INP(n1586), .ZN(n1577) );
INVX0 U266 ( .INP(n1586), .ZN(n1574) );
INVX0 U267 ( .INP(n1586), .ZN(n1576) );
INVX0 U268 ( .INP(n1586), .ZN(n1575) );
INVX0 U269 ( .INP(n1587), .ZN(n1569) );
INVX0 U270 ( .INP(n1587), .ZN(n1570) );
INVX0 U271 ( .INP(n1587), .ZN(n1568) );
INVX0 U272 ( .INP(n1587), .ZN(n1571) );
INVX0 U273 ( .INP(n1587), .ZN(n1573) );
INVX0 U274 ( .INP(n1587), .ZN(n1572) );
INVX0 U275 ( .INP(n1587), .ZN(n1567) );
INVX0 U276 ( .INP(n1587), .ZN(n1565) );
INVX0 U277 ( .INP(n1587), .ZN(n1566) );
INVX0 U278 ( .INP(n1558), .ZN(n1557) );
INVX0 U279 ( .INP(n1586), .ZN(n1585) );
INVX0 U280 ( .INP(n1588), .ZN(n1357) );
INVX0 U281 ( .INP(\fpu_add_exp_dp/n448 ), .ZN(n1586) );
INVX0 U282 ( .INP(\fpu_add_exp_dp/n448 ), .ZN(n1587) );
NBUFFX2 U283 ( .INP(n1342), .Z(n1563) );
NBUFFX2 U284 ( .INP(n1342), .Z(n1562) );
NBUFFX2 U285 ( .INP(n1342), .Z(n1564) );
NBUFFX2 U286 ( .INP(n1342), .Z(n1558) );
NBUFFX2 U287 ( .INP(n1342), .Z(n1561) );
NBUFFX2 U288 ( .INP(n1342), .Z(n1559) );
NBUFFX2 U289 ( .INP(n1342), .Z(n1560) );
NBUFFX2 U290 ( .INP(n1341), .Z(n1377) );
NBUFFX2 U291 ( .INP(n1341), .Z(n1378) );
OR2X1 U292 ( .IN1(n1343), .IN2(se_add_frac), .Q(n1341) );
OR2X1 U293 ( .IN1(\fpu_add_frac_dp/n998 ), .IN2(\fpu_add_frac_dp/n2189 ),
.Q(n1342) );
AO22X1 U294 ( .IN1(n1343), .IN2(n612), .IN3(inq_in1[0]), .IN4(n1376), .Q(
\fpu_add_frac_dp/n4285 ) );
AO22X1 U295 ( .IN1(n1349), .IN2(n93), .IN3(inq_in1[1]), .IN4(n1376), .Q(
\fpu_add_frac_dp/n4284 ) );
AO22X1 U296 ( .IN1(n1349), .IN2(n182), .IN3(inq_in1[2]), .IN4(n1376), .Q(
\fpu_add_frac_dp/n4283 ) );
AO22X1 U297 ( .IN1(n1349), .IN2(n599), .IN3(inq_in1[3]), .IN4(n1376), .Q(
\fpu_add_frac_dp/n4282 ) );
AO22X1 U298 ( .IN1(n1349), .IN2(n183), .IN3(inq_in1[4]), .IN4(n1376), .Q(
\fpu_add_frac_dp/n4281 ) );
AO22X1 U299 ( .IN1(n1349), .IN2(n600), .IN3(inq_in1[5]), .IN4(n1376), .Q(
\fpu_add_frac_dp/n4280 ) );
AO22X1 U300 ( .IN1(n1349), .IN2(n184), .IN3(inq_in1[6]), .IN4(n1376), .Q(
\fpu_add_frac_dp/n4279 ) );
AO22X1 U301 ( .IN1(n1349), .IN2(n601), .IN3(inq_in1[7]), .IN4(n1376), .Q(
\fpu_add_frac_dp/n4278 ) );
AO22X1 U302 ( .IN1(n1349), .IN2(n185), .IN3(inq_in1[8]), .IN4(n1376), .Q(
\fpu_add_frac_dp/n4277 ) );
AO22X1 U303 ( .IN1(n1349), .IN2(n602), .IN3(inq_in1[9]), .IN4(n1375), .Q(
\fpu_add_frac_dp/n4276 ) );
AO22X1 U304 ( .IN1(n1349), .IN2(n186), .IN3(inq_in1[10]), .IN4(n1375), .Q(
\fpu_add_frac_dp/n4275 ) );
AO22X1 U305 ( .IN1(n1349), .IN2(n603), .IN3(inq_in1[11]), .IN4(n1375), .Q(
\fpu_add_frac_dp/n4274 ) );
AO22X1 U306 ( .IN1(n1349), .IN2(n187), .IN3(inq_in1[12]), .IN4(n1375), .Q(
\fpu_add_frac_dp/n4273 ) );
AO22X1 U307 ( .IN1(n1348), .IN2(n604), .IN3(inq_in1[13]), .IN4(n1375), .Q(
\fpu_add_frac_dp/n4272 ) );
AO22X1 U308 ( .IN1(n1348), .IN2(n188), .IN3(inq_in1[14]), .IN4(n1375), .Q(
\fpu_add_frac_dp/n4271 ) );
AO22X1 U309 ( .IN1(n1348), .IN2(n605), .IN3(inq_in1[15]), .IN4(n1375), .Q(
\fpu_add_frac_dp/n4270 ) );
AO22X1 U310 ( .IN1(n1348), .IN2(n189), .IN3(inq_in1[16]), .IN4(n1375), .Q(
\fpu_add_frac_dp/n4269 ) );
AO22X1 U311 ( .IN1(n1348), .IN2(n606), .IN3(inq_in1[17]), .IN4(n1375), .Q(
\fpu_add_frac_dp/n4268 ) );
AO22X1 U312 ( .IN1(n1348), .IN2(n190), .IN3(inq_in1[18]), .IN4(n1375), .Q(
\fpu_add_frac_dp/n4267 ) );
AO22X1 U313 ( .IN1(n1348), .IN2(n607), .IN3(inq_in1[19]), .IN4(n1375), .Q(
\fpu_add_frac_dp/n4266 ) );
AO22X1 U314 ( .IN1(n1348), .IN2(n191), .IN3(inq_in1[20]), .IN4(n1375), .Q(
\fpu_add_frac_dp/n4265 ) );
AO22X1 U315 ( .IN1(n1348), .IN2(n608), .IN3(inq_in1[21]), .IN4(n1374), .Q(
\fpu_add_frac_dp/n4264 ) );
AO22X1 U316 ( .IN1(n1348), .IN2(n192), .IN3(inq_in1[22]), .IN4(n1374), .Q(
\fpu_add_frac_dp/n4263 ) );
AO22X1 U317 ( .IN1(n1348), .IN2(n609), .IN3(inq_in1[23]), .IN4(n1374), .Q(
\fpu_add_frac_dp/n4262 ) );
AO22X1 U318 ( .IN1(n1348), .IN2(n193), .IN3(inq_in1[24]), .IN4(n1374), .Q(
\fpu_add_frac_dp/n4261 ) );
AO22X1 U319 ( .IN1(n1348), .IN2(n610), .IN3(inq_in1[25]), .IN4(n1374), .Q(
\fpu_add_frac_dp/n4260 ) );
AO22X1 U320 ( .IN1(n1348), .IN2(n194), .IN3(inq_in1[26]), .IN4(n1374), .Q(
\fpu_add_frac_dp/n4259 ) );
AO22X1 U321 ( .IN1(n1348), .IN2(n611), .IN3(inq_in1[27]), .IN4(n1374), .Q(
\fpu_add_frac_dp/n4258 ) );
AO22X1 U322 ( .IN1(n1348), .IN2(n207), .IN3(inq_in1[28]), .IN4(n1374), .Q(
\fpu_add_frac_dp/n4257 ) );
AO22X1 U323 ( .IN1(n1348), .IN2(n644), .IN3(inq_in1[29]), .IN4(n1374), .Q(
\fpu_add_frac_dp/n4256 ) );
AO22X1 U324 ( .IN1(n1347), .IN2(n698), .IN3(inq_in1[30]), .IN4(n1374), .Q(
\fpu_add_frac_dp/n4255 ) );
AO22X1 U325 ( .IN1(n1347), .IN2(n699), .IN3(inq_in1[31]), .IN4(n1374), .Q(
\fpu_add_frac_dp/n4254 ) );
AO22X1 U326 ( .IN1(n1347), .IN2(n176), .IN3(inq_in1[32]), .IN4(n1374), .Q(
\fpu_add_frac_dp/n4253 ) );
AO22X1 U327 ( .IN1(n1347), .IN2(n208), .IN3(inq_in1[33]), .IN4(n1373), .Q(
\fpu_add_frac_dp/n4252 ) );
AO22X1 U328 ( .IN1(n1347), .IN2(n99), .IN3(inq_in1[34]), .IN4(n1373), .Q(
\fpu_add_frac_dp/n4251 ) );
AO22X1 U329 ( .IN1(n1347), .IN2(n614), .IN3(inq_in1[35]), .IN4(n1373), .Q(
\fpu_add_frac_dp/n4250 ) );
AO22X1 U330 ( .IN1(n1347), .IN2(n615), .IN3(inq_in1[36]), .IN4(n1373), .Q(
\fpu_add_frac_dp/n4249 ) );
AO22X1 U331 ( .IN1(n1347), .IN2(n209), .IN3(inq_in1[37]), .IN4(n1373), .Q(
\fpu_add_frac_dp/n4248 ) );
AO22X1 U332 ( .IN1(n1347), .IN2(n210), .IN3(inq_in1[38]), .IN4(n1373), .Q(
\fpu_add_frac_dp/n4247 ) );
AO22X1 U333 ( .IN1(n1347), .IN2(n211), .IN3(inq_in1[39]), .IN4(n1373), .Q(
\fpu_add_frac_dp/n4246 ) );
AO22X1 U334 ( .IN1(n1347), .IN2(n616), .IN3(inq_in1[40]), .IN4(n1373), .Q(
\fpu_add_frac_dp/n4245 ) );
AO22X1 U335 ( .IN1(n1347), .IN2(n617), .IN3(inq_in1[41]), .IN4(n1373), .Q(
\fpu_add_frac_dp/n4244 ) );
AO22X1 U336 ( .IN1(n1347), .IN2(n618), .IN3(inq_in1[42]), .IN4(n1373), .Q(
\fpu_add_frac_dp/n4243 ) );
AO22X1 U337 ( .IN1(n1347), .IN2(n212), .IN3(inq_in1[43]), .IN4(n1373), .Q(
\fpu_add_frac_dp/n4242 ) );
AO22X1 U338 ( .IN1(n1347), .IN2(n213), .IN3(inq_in1[44]), .IN4(n1373), .Q(
\fpu_add_frac_dp/n4241 ) );
AO22X1 U339 ( .IN1(n1347), .IN2(n214), .IN3(inq_in1[45]), .IN4(n1372), .Q(
\fpu_add_frac_dp/n4240 ) );
AO22X1 U340 ( .IN1(n1347), .IN2(n619), .IN3(inq_in1[46]), .IN4(n1372), .Q(
\fpu_add_frac_dp/n4239 ) );
AO22X1 U341 ( .IN1(n1346), .IN2(n620), .IN3(inq_in1[47]), .IN4(n1372), .Q(
\fpu_add_frac_dp/n4238 ) );
AO22X1 U342 ( .IN1(n1346), .IN2(n621), .IN3(inq_in1[48]), .IN4(n1372), .Q(
\fpu_add_frac_dp/n4237 ) );
AO22X1 U343 ( .IN1(n1346), .IN2(n215), .IN3(inq_in1[49]), .IN4(n1372), .Q(
\fpu_add_frac_dp/n4236 ) );
AO22X1 U344 ( .IN1(n1346), .IN2(n216), .IN3(inq_in1[50]), .IN4(n1372), .Q(
\fpu_add_frac_dp/n4235 ) );
AO22X1 U345 ( .IN1(n1346), .IN2(n206), .IN3(inq_in1[51]), .IN4(n1372), .Q(
\fpu_add_frac_dp/n4234 ) );
AO22X1 U346 ( .IN1(n1346), .IN2(n688), .IN3(inq_in1[52]), .IN4(n1372), .Q(
\fpu_add_frac_dp/n4233 ) );
AO22X1 U347 ( .IN1(n1346), .IN2(n689), .IN3(inq_in1[53]), .IN4(n1372), .Q(
\fpu_add_frac_dp/n4232 ) );
AO22X1 U348 ( .IN1(n1346), .IN2(n705), .IN3(inq_in1[54]), .IN4(n1372), .Q(
\fpu_add_frac_dp/n4231 ) );
AO22X1 U349 ( .IN1(n1346), .IN2(n1188), .IN3(inq_in1[55]), .IN4(n1372), .Q(
\fpu_add_frac_dp/n4230 ) );
AO22X1 U350 ( .IN1(n1346), .IN2(n1189), .IN3(inq_in1[56]), .IN4(n1372), .Q(
\fpu_add_frac_dp/n4229 ) );
AO22X1 U351 ( .IN1(n1346), .IN2(n714), .IN3(inq_in1[57]), .IN4(n1371), .Q(
\fpu_add_frac_dp/n4228 ) );
AO22X1 U352 ( .IN1(n1346), .IN2(n1190), .IN3(inq_in1[58]), .IN4(n1371), .Q(
\fpu_add_frac_dp/n4227 ) );
AO22X1 U353 ( .IN1(n1346), .IN2(n713), .IN3(inq_in1[59]), .IN4(n1371), .Q(
\fpu_add_frac_dp/n4226 ) );
AO22X1 U354 ( .IN1(n1346), .IN2(n712), .IN3(inq_in1[60]), .IN4(n1371), .Q(
\fpu_add_frac_dp/n4225 ) );
AO22X1 U355 ( .IN1(n1346), .IN2(n1191), .IN3(inq_in1[61]), .IN4(n1371), .Q(
\fpu_add_frac_dp/n4224 ) );
AO22X1 U356 ( .IN1(n1346), .IN2(n715), .IN3(inq_in1[62]), .IN4(n1371), .Q(
\fpu_add_frac_dp/n4223 ) );
AO22X1 U357 ( .IN1(\fpu_add_frac_dp/n2493 ), .IN2(n1356), .IN3(inq_in1[0]),
.IN4(n1371), .Q(\fpu_add_frac_dp/n4222 ) );
AO22X1 U358 ( .IN1(n1345), .IN2(n1185), .IN3(inq_in1[1]), .IN4(n1371), .Q(
\fpu_add_frac_dp/n4221 ) );
AO22X1 U359 ( .IN1(n1345), .IN2(n745), .IN3(inq_in1[2]), .IN4(n1371), .Q(
\fpu_add_frac_dp/n4220 ) );
AO22X1 U360 ( .IN1(\fpu_add_frac_dp/n2296 ), .IN2(n1356), .IN3(inq_in1[3]),
.IN4(n1371), .Q(\fpu_add_frac_dp/n4219 ) );
AO22X1 U361 ( .IN1(n1345), .IN2(n695), .IN3(inq_in1[4]), .IN4(n1371), .Q(
\fpu_add_frac_dp/n4218 ) );
AO22X1 U362 ( .IN1(n1345), .IN2(n1128), .IN3(inq_in1[5]), .IN4(n1371), .Q(
\fpu_add_frac_dp/n4217 ) );
AO22X1 U363 ( .IN1(n1345), .IN2(n1133), .IN3(inq_in1[6]), .IN4(n1370), .Q(
\fpu_add_frac_dp/n4216 ) );
AO22X1 U364 ( .IN1(n1345), .IN2(n1195), .IN3(inq_in1[7]), .IN4(n1370), .Q(
\fpu_add_frac_dp/n4215 ) );
AO22X1 U365 ( .IN1(n1345), .IN2(n1146), .IN3(inq_in1[8]), .IN4(n1370), .Q(
\fpu_add_frac_dp/n4214 ) );
AO22X1 U366 ( .IN1(n1345), .IN2(n577), .IN3(inq_in1[9]), .IN4(n1370), .Q(
\fpu_add_frac_dp/n4213 ) );
AO22X1 U367 ( .IN1(n1345), .IN2(n145), .IN3(inq_in1[10]), .IN4(n1370), .Q(
\fpu_add_frac_dp/n4212 ) );
AO22X1 U368 ( .IN1(n1345), .IN2(n854), .IN3(inq_in1[11]), .IN4(n1370), .Q(
\fpu_add_frac_dp/n4211 ) );
AO22X1 U369 ( .IN1(\fpu_add_frac_dp/n2484 ), .IN2(n1356), .IN3(inq_in1[12]),
.IN4(n1370), .Q(\fpu_add_frac_dp/n4210 ) );
AO22X1 U370 ( .IN1(n1345), .IN2(n1184), .IN3(inq_in1[13]), .IN4(n1370), .Q(
\fpu_add_frac_dp/n4209 ) );
AO22X1 U371 ( .IN1(n1345), .IN2(n988), .IN3(inq_in1[14]), .IN4(n1370), .Q(
\fpu_add_frac_dp/n4208 ) );
AO22X1 U372 ( .IN1(\fpu_add_frac_dp/n2453 ), .IN2(n1356), .IN3(inq_in1[15]),
.IN4(n1370), .Q(\fpu_add_frac_dp/n4207 ) );
AO22X1 U373 ( .IN1(n1345), .IN2(n703), .IN3(inq_in1[16]), .IN4(n1370), .Q(
\fpu_add_frac_dp/n4206 ) );
AO22X1 U374 ( .IN1(n1345), .IN2(n853), .IN3(inq_in1[17]), .IN4(n1370), .Q(
\fpu_add_frac_dp/n4205 ) );
AO22X1 U375 ( .IN1(n1345), .IN2(n1153), .IN3(inq_in1[18]), .IN4(n1369), .Q(
\fpu_add_frac_dp/n4204 ) );
AO22X1 U376 ( .IN1(n1345), .IN2(n1197), .IN3(inq_in1[19]), .IN4(n1369), .Q(
\fpu_add_frac_dp/n4203 ) );
AO22X1 U377 ( .IN1(n1345), .IN2(n1143), .IN3(inq_in1[20]), .IN4(n1369), .Q(
\fpu_add_frac_dp/n4202 ) );
AO22X1 U378 ( .IN1(\fpu_add_frac_dp/n2444 ), .IN2(n1356), .IN3(inq_in1[21]),
.IN4(n1369), .Q(\fpu_add_frac_dp/n4201 ) );
AO22X1 U379 ( .IN1(n1344), .IN2(n1204), .IN3(inq_in1[22]), .IN4(n1369), .Q(
\fpu_add_frac_dp/n4200 ) );
AO22X1 U380 ( .IN1(n1344), .IN2(n1206), .IN3(inq_in1[23]), .IN4(n1369), .Q(
\fpu_add_frac_dp/n4199 ) );
AO22X1 U381 ( .IN1(\fpu_add_frac_dp/n2488 ), .IN2(n1356), .IN3(inq_in1[24]),
.IN4(n1369), .Q(\fpu_add_frac_dp/n4198 ) );
AO22X1 U382 ( .IN1(n1344), .IN2(n1209), .IN3(inq_in1[25]), .IN4(n1369), .Q(
\fpu_add_frac_dp/n4197 ) );
AO22X1 U383 ( .IN1(n1344), .IN2(n550), .IN3(inq_in1[26]), .IN4(n1369), .Q(
\fpu_add_frac_dp/n4196 ) );
AO22X1 U384 ( .IN1(n1344), .IN2(n647), .IN3(inq_in1[27]), .IN4(n1369), .Q(
\fpu_add_frac_dp/n4195 ) );
AO22X1 U385 ( .IN1(n1344), .IN2(n54), .IN3(inq_in1[28]), .IN4(n1369), .Q(
\fpu_add_frac_dp/n4194 ) );
AO22X1 U386 ( .IN1(n1344), .IN2(n856), .IN3(inq_in1[29]), .IN4(n1369), .Q(
\fpu_add_frac_dp/n4193 ) );
AO22X1 U387 ( .IN1(\fpu_add_frac_dp/n2445 ), .IN2(n1356), .IN3(inq_in1[30]),
.IN4(n1368), .Q(\fpu_add_frac_dp/n4192 ) );
AO22X1 U388 ( .IN1(n1344), .IN2(n704), .IN3(inq_in1[31]), .IN4(n1368), .Q(
\fpu_add_frac_dp/n4191 ) );
AO22X1 U389 ( .IN1(n1344), .IN2(n855), .IN3(inq_in1[32]), .IN4(n1368), .Q(
\fpu_add_frac_dp/n4190 ) );
AO22X1 U390 ( .IN1(\fpu_add_frac_dp/n2295 ), .IN2(n1356), .IN3(inq_in1[33]),
.IN4(n1368), .Q(\fpu_add_frac_dp/n4189 ) );
AO22X1 U391 ( .IN1(n1344), .IN2(n857), .IN3(inq_in1[34]), .IN4(n1368), .Q(
\fpu_add_frac_dp/n4188 ) );
AO22X1 U392 ( .IN1(n1344), .IN2(n1215), .IN3(inq_in1[35]), .IN4(n1368), .Q(
\fpu_add_frac_dp/n4187 ) );
AO22X1 U393 ( .IN1(n1344), .IN2(n292), .IN3(inq_in1[36]), .IN4(n1368), .Q(
\fpu_add_frac_dp/n4186 ) );
AO22X1 U394 ( .IN1(n1344), .IN2(n125), .IN3(inq_in1[37]), .IN4(n1368), .Q(
\fpu_add_frac_dp/n4185 ) );
AO22X1 U395 ( .IN1(n1344), .IN2(n46), .IN3(inq_in1[38]), .IN4(n1368), .Q(
\fpu_add_frac_dp/n4184 ) );
AO22X1 U396 ( .IN1(\fpu_add_frac_dp/n2452 ), .IN2(n1356), .IN3(inq_in1[39]),
.IN4(n1368), .Q(\fpu_add_frac_dp/n4183 ) );
AO22X1 U397 ( .IN1(n1344), .IN2(n709), .IN3(inq_in1[40]), .IN4(n1368), .Q(
\fpu_add_frac_dp/n4182 ) );
AO22X1 U398 ( .IN1(n1344), .IN2(n1129), .IN3(inq_in1[41]), .IN4(n1368), .Q(
\fpu_add_frac_dp/n4181 ) );
AO22X1 U399 ( .IN1(\fpu_add_frac_dp/n2462 ), .IN2(n1356), .IN3(inq_in1[42]),
.IN4(n1367), .Q(\fpu_add_frac_dp/n4180 ) );
AO22X1 U400 ( .IN1(n1344), .IN2(n848), .IN3(inq_in1[43]), .IN4(n1367), .Q(
\fpu_add_frac_dp/n4179 ) );
AO22X1 U401 ( .IN1(n1343), .IN2(n57), .IN3(inq_in1[44]), .IN4(n1367), .Q(
\fpu_add_frac_dp/n4178 ) );
AO22X1 U402 ( .IN1(n1343), .IN2(n677), .IN3(inq_in1[45]), .IN4(n1367), .Q(
\fpu_add_frac_dp/n4177 ) );
AO22X1 U403 ( .IN1(n1343), .IN2(n1198), .IN3(inq_in1[46]), .IN4(n1367), .Q(
\fpu_add_frac_dp/n4176 ) );
AO22X1 U404 ( .IN1(n1343), .IN2(n1202), .IN3(inq_in1[47]), .IN4(n1367), .Q(
\fpu_add_frac_dp/n4175 ) );
AO22X1 U405 ( .IN1(\fpu_add_frac_dp/n2476 ), .IN2(n1588), .IN3(inq_in1[48]),
.IN4(n1367), .Q(\fpu_add_frac_dp/n4174 ) );
AO22X1 U406 ( .IN1(n1343), .IN2(n917), .IN3(inq_in1[49]), .IN4(n1367), .Q(
\fpu_add_frac_dp/n4173 ) );
AO22X1 U407 ( .IN1(\fpu_add_frac_dp/n2350 ), .IN2(n1354), .IN3(inq_in1[50]),
.IN4(n1367), .Q(\fpu_add_frac_dp/n4172 ) );
AO22X1 U408 ( .IN1(n1343), .IN2(n340), .IN3(inq_in1[51]), .IN4(n1367), .Q(
\fpu_add_frac_dp/n4171 ) );
AO22X1 U409 ( .IN1(n1343), .IN2(n548), .IN3(inq_in1[52]), .IN4(n1367), .Q(
\fpu_add_frac_dp/n4170 ) );
AO22X1 U410 ( .IN1(n1343), .IN2(n747), .IN3(inq_in1[53]), .IN4(n1367), .Q(
\fpu_add_frac_dp/n4169 ) );
AO22X1 U411 ( .IN1(n1343), .IN2(n283), .IN3(inq_in1[54]), .IN4(n1376), .Q(
\fpu_add_frac_dp/n4168 ) );
AO22X1 U412 ( .IN1(n1343), .IN2(n36), .IN3(inq_in2[0]), .IN4(n1376), .Q(
\fpu_add_frac_dp/n4167 ) );
AO22X1 U413 ( .IN1(n1349), .IN2(n170), .IN3(inq_in2[1]), .IN4(n1376), .Q(
\fpu_add_frac_dp/n4166 ) );
AO22X1 U414 ( .IN1(n1343), .IN2(n10), .IN3(inq_in2[2]), .IN4(n1365), .Q(
\fpu_add_frac_dp/n4165 ) );
AO22X1 U415 ( .IN1(n1343), .IN2(n1589), .IN3(inq_in2[3]), .IN4(n1364), .Q(
\fpu_add_frac_dp/n4164 ) );
AO22X1 U416 ( .IN1(n1343), .IN2(n11), .IN3(inq_in2[4]), .IN4(n1363), .Q(
\fpu_add_frac_dp/n4163 ) );
AO22X1 U417 ( .IN1(n1346), .IN2(n30), .IN3(inq_in2[5]), .IN4(n1362), .Q(
\fpu_add_frac_dp/n4162 ) );
AO22X1 U418 ( .IN1(n1349), .IN2(n79), .IN3(inq_in2[6]), .IN4(n1361), .Q(
\fpu_add_frac_dp/n4161 ) );
AO22X1 U419 ( .IN1(n1349), .IN2(n31), .IN3(inq_in2[7]), .IN4(n1360), .Q(
\fpu_add_frac_dp/n4160 ) );
AO22X1 U420 ( .IN1(n1349), .IN2(n80), .IN3(inq_in2[8]), .IN4(n1359), .Q(
\fpu_add_frac_dp/n4159 ) );
AO22X1 U421 ( .IN1(n1349), .IN2(n32), .IN3(inq_in2[9]), .IN4(n1358), .Q(
\fpu_add_frac_dp/n4158 ) );
AO22X1 U422 ( .IN1(n1350), .IN2(n81), .IN3(inq_in2[10]), .IN4(n1375), .Q(
\fpu_add_frac_dp/n4157 ) );
AO22X1 U423 ( .IN1(n1350), .IN2(n39), .IN3(inq_in2[11]), .IN4(n1366), .Q(
\fpu_add_frac_dp/n4156 ) );
AO22X1 U424 ( .IN1(n1350), .IN2(n120), .IN3(inq_in2[12]), .IN4(n1366), .Q(
\fpu_add_frac_dp/n4155 ) );
AO22X1 U425 ( .IN1(n1350), .IN2(n52), .IN3(inq_in2[13]), .IN4(n1366), .Q(
\fpu_add_frac_dp/n4154 ) );
AO22X1 U426 ( .IN1(n1350), .IN2(n121), .IN3(inq_in2[14]), .IN4(n1366), .Q(
\fpu_add_frac_dp/n4153 ) );
AO22X1 U427 ( .IN1(n1350), .IN2(n53), .IN3(inq_in2[15]), .IN4(n1366), .Q(
\fpu_add_frac_dp/n4152 ) );
AO22X1 U428 ( .IN1(n1350), .IN2(n122), .IN3(inq_in2[16]), .IN4(n1366), .Q(
\fpu_add_frac_dp/n4151 ) );
AO22X1 U429 ( .IN1(n1350), .IN2(n272), .IN3(inq_in2[17]), .IN4(n1366), .Q(
\fpu_add_frac_dp/n4150 ) );
AO22X1 U430 ( .IN1(n1350), .IN2(n633), .IN3(inq_in2[18]), .IN4(n1366), .Q(
\fpu_add_frac_dp/n4149 ) );
AO22X1 U431 ( .IN1(n1350), .IN2(n273), .IN3(inq_in2[19]), .IN4(n1366), .Q(
\fpu_add_frac_dp/n4148 ) );
AO22X1 U432 ( .IN1(n1350), .IN2(n634), .IN3(inq_in2[20]), .IN4(n1366), .Q(
\fpu_add_frac_dp/n4147 ) );
AO22X1 U433 ( .IN1(n1350), .IN2(n274), .IN3(inq_in2[21]), .IN4(n1366), .Q(
\fpu_add_frac_dp/n4146 ) );
AO22X1 U434 ( .IN1(n1350), .IN2(n635), .IN3(inq_in2[22]), .IN4(n1366), .Q(
\fpu_add_frac_dp/n4145 ) );
AO22X1 U435 ( .IN1(n1350), .IN2(n275), .IN3(inq_in2[23]), .IN4(n1365), .Q(
\fpu_add_frac_dp/n4144 ) );
AO22X1 U436 ( .IN1(n1351), .IN2(n636), .IN3(inq_in2[24]), .IN4(n1365), .Q(
\fpu_add_frac_dp/n4143 ) );
AO22X1 U437 ( .IN1(n1351), .IN2(n276), .IN3(inq_in2[25]), .IN4(n1365), .Q(
\fpu_add_frac_dp/n4142 ) );
AO22X1 U438 ( .IN1(n1350), .IN2(n637), .IN3(inq_in2[26]), .IN4(n1365), .Q(
\fpu_add_frac_dp/n4141 ) );
AO22X1 U439 ( .IN1(n1351), .IN2(n277), .IN3(inq_in2[27]), .IN4(n1365), .Q(
\fpu_add_frac_dp/n4140 ) );
AO22X1 U440 ( .IN1(n1351), .IN2(n639), .IN3(inq_in2[28]), .IN4(n1365), .Q(
\fpu_add_frac_dp/n4139 ) );
AO22X1 U441 ( .IN1(n1351), .IN2(n112), .IN3(inq_in2[29]), .IN4(n1365), .Q(
\fpu_add_frac_dp/n4138 ) );
AO22X1 U442 ( .IN1(n1351), .IN2(n113), .IN3(inq_in2[30]), .IN4(n1365), .Q(
\fpu_add_frac_dp/n4137 ) );
AO22X1 U443 ( .IN1(n1351), .IN2(n114), .IN3(inq_in2[31]), .IN4(n1365), .Q(
\fpu_add_frac_dp/n4136 ) );
AO22X1 U444 ( .IN1(n1351), .IN2(n7), .IN3(inq_in2[32]), .IN4(n1365), .Q(
\fpu_add_frac_dp/n4135 ) );
AO22X1 U445 ( .IN1(n1351), .IN2(n8), .IN3(inq_in2[33]), .IN4(n1365), .Q(
\fpu_add_frac_dp/n4134 ) );
AO22X1 U446 ( .IN1(n1351), .IN2(n9), .IN3(inq_in2[34]), .IN4(n1365), .Q(
\fpu_add_frac_dp/n4133 ) );
AO22X1 U447 ( .IN1(n1351), .IN2(n24), .IN3(inq_in2[35]), .IN4(n1364), .Q(
\fpu_add_frac_dp/n4132 ) );
AO22X1 U448 ( .IN1(n1351), .IN2(n25), .IN3(inq_in2[36]), .IN4(n1364), .Q(
\fpu_add_frac_dp/n4131 ) );
AO22X1 U449 ( .IN1(n1351), .IN2(n26), .IN3(inq_in2[37]), .IN4(n1364), .Q(
\fpu_add_frac_dp/n4130 ) );
AO22X1 U450 ( .IN1(n1352), .IN2(n76), .IN3(inq_in2[38]), .IN4(n1364), .Q(
\fpu_add_frac_dp/n4129 ) );
AO22X1 U451 ( .IN1(n1352), .IN2(n77), .IN3(inq_in2[39]), .IN4(n1364), .Q(
\fpu_add_frac_dp/n4128 ) );
AO22X1 U452 ( .IN1(n1351), .IN2(n167), .IN3(inq_in2[40]), .IN4(n1364), .Q(
\fpu_add_frac_dp/n4127 ) );
AO22X1 U453 ( .IN1(n1352), .IN2(n27), .IN3(inq_in2[41]), .IN4(n1364), .Q(
\fpu_add_frac_dp/n4126 ) );
AO22X1 U454 ( .IN1(n1352), .IN2(n28), .IN3(inq_in2[42]), .IN4(n1364), .Q(
\fpu_add_frac_dp/n4125 ) );
AO22X1 U455 ( .IN1(n1352), .IN2(n29), .IN3(inq_in2[43]), .IN4(n1364), .Q(
\fpu_add_frac_dp/n4124 ) );
AO22X1 U456 ( .IN1(n1352), .IN2(n163), .IN3(inq_in2[44]), .IN4(n1364), .Q(
\fpu_add_frac_dp/n4123 ) );
AO22X1 U457 ( .IN1(n1352), .IN2(n164), .IN3(inq_in2[45]), .IN4(n1364), .Q(
\fpu_add_frac_dp/n4122 ) );
AO22X1 U458 ( .IN1(n1352), .IN2(n587), .IN3(inq_in2[46]), .IN4(n1364), .Q(
\fpu_add_frac_dp/n4121 ) );
AO22X1 U459 ( .IN1(n1352), .IN2(n588), .IN3(inq_in2[47]), .IN4(n1363), .Q(
\fpu_add_frac_dp/n4120 ) );
AO22X1 U460 ( .IN1(n1352), .IN2(n589), .IN3(inq_in2[48]), .IN4(n1363), .Q(
\fpu_add_frac_dp/n4119 ) );
AO22X1 U461 ( .IN1(n1352), .IN2(n78), .IN3(inq_in2[49]), .IN4(n1363), .Q(
\fpu_add_frac_dp/n4118 ) );
AO22X1 U462 ( .IN1(n1352), .IN2(n165), .IN3(inq_in2[50]), .IN4(n1363), .Q(
\fpu_add_frac_dp/n4117 ) );
AO22X1 U463 ( .IN1(n1351), .IN2(n169), .IN3(inq_in2[51]), .IN4(n1363), .Q(
\fpu_add_frac_dp/n4116 ) );
AO22X1 U464 ( .IN1(n1353), .IN2(n591), .IN3(inq_in2[52]), .IN4(n1363), .Q(
\fpu_add_frac_dp/n4115 ) );
AO22X1 U465 ( .IN1(n1353), .IN2(n592), .IN3(inq_in2[53]), .IN4(n1363), .Q(
\fpu_add_frac_dp/n4114 ) );
AO22X1 U466 ( .IN1(n1353), .IN2(n593), .IN3(inq_in2[54]), .IN4(n1363), .Q(
\fpu_add_frac_dp/n4113 ) );
AO22X1 U467 ( .IN1(\fpu_add_frac_dp/n2446 ), .IN2(n1356), .IN3(inq_in2[55]),
.IN4(n1363), .Q(\fpu_add_frac_dp/n4112 ) );
AO22X1 U468 ( .IN1(\fpu_add_frac_dp/n2473 ), .IN2(n1356), .IN3(inq_in2[56]),
.IN4(n1363), .Q(\fpu_add_frac_dp/n4111 ) );
AO22X1 U469 ( .IN1(\fpu_add_frac_dp/n2466 ), .IN2(n1356), .IN3(inq_in2[57]),
.IN4(n1363), .Q(\fpu_add_frac_dp/n4110 ) );
AO22X1 U470 ( .IN1(\fpu_add_frac_dp/n2474 ), .IN2(n1356), .IN3(inq_in2[58]),
.IN4(n1363), .Q(\fpu_add_frac_dp/n4109 ) );
AO22X1 U471 ( .IN1(\fpu_add_frac_dp/n2467 ), .IN2(n1356), .IN3(inq_in2[59]),
.IN4(n1362), .Q(\fpu_add_frac_dp/n4108 ) );
AO22X1 U472 ( .IN1(\fpu_add_frac_dp/n2475 ), .IN2(n1356), .IN3(inq_in2[60]),
.IN4(n1362), .Q(\fpu_add_frac_dp/n4107 ) );
AO22X1 U473 ( .IN1(\fpu_add_frac_dp/n2468 ), .IN2(n1356), .IN3(inq_in2[61]),
.IN4(n1362), .Q(\fpu_add_frac_dp/n4106 ) );
AO22X1 U474 ( .IN1(\fpu_add_frac_dp/n2469 ), .IN2(n1355), .IN3(inq_in2[62]),
.IN4(n1362), .Q(\fpu_add_frac_dp/n4105 ) );
AO22X1 U475 ( .IN1(n1353), .IN2(n1080), .IN3(inq_in2[63]), .IN4(n1362), .Q(
\fpu_add_frac_dp/n4104 ) );
AO22X1 U476 ( .IN1(n1353), .IN2(n702), .IN3(inq_in2[0]), .IN4(n1362), .Q(
\fpu_add_frac_dp/n4103 ) );
AO22X1 U477 ( .IN1(\fpu_add_frac_dp/n2455 ), .IN2(n1355), .IN3(inq_in2[1]),
.IN4(n1362), .Q(\fpu_add_frac_dp/n4102 ) );
AO22X1 U478 ( .IN1(n1353), .IN2(n337), .IN3(inq_in2[2]), .IN4(n1362), .Q(
\fpu_add_frac_dp/n4101 ) );
AO22X1 U479 ( .IN1(n1353), .IN2(n1205), .IN3(inq_in2[3]), .IN4(n1362), .Q(
\fpu_add_frac_dp/n4100 ) );
AO22X1 U480 ( .IN1(n1352), .IN2(n900), .IN3(inq_in2[4]), .IN4(n1362), .Q(
\fpu_add_frac_dp/n4099 ) );
AO22X1 U481 ( .IN1(\fpu_add_frac_dp/n2459 ), .IN2(n1355), .IN3(inq_in2[5]),
.IN4(n1362), .Q(\fpu_add_frac_dp/n4098 ) );
AO22X1 U482 ( .IN1(\fpu_add_frac_dp/n2490 ), .IN2(n1355), .IN3(inq_in2[6]),
.IN4(n1362), .Q(\fpu_add_frac_dp/n4097 ) );
AO22X1 U483 ( .IN1(\fpu_add_frac_dp/n2489 ), .IN2(n1355), .IN3(inq_in2[7]),
.IN4(n1361), .Q(\fpu_add_frac_dp/n4096 ) );
AO22X1 U484 ( .IN1(\fpu_add_frac_dp/n2472 ), .IN2(n1355), .IN3(inq_in2[8]),
.IN4(n1361), .Q(\fpu_add_frac_dp/n4095 ) );
AO22X1 U485 ( .IN1(n1354), .IN2(n697), .IN3(inq_in2[9]), .IN4(n1361), .Q(
\fpu_add_frac_dp/n4094 ) );
AO22X1 U486 ( .IN1(\fpu_add_frac_dp/n2483 ), .IN2(n1355), .IN3(inq_in2[10]),
.IN4(n1361), .Q(\fpu_add_frac_dp/n4093 ) );
AO22X1 U487 ( .IN1(\fpu_add_frac_dp/n2457 ), .IN2(n1355), .IN3(inq_in2[11]),
.IN4(n1361), .Q(\fpu_add_frac_dp/n4092 ) );
AO22X1 U488 ( .IN1(n1354), .IN2(n670), .IN3(inq_in2[12]), .IN4(n1361), .Q(
\fpu_add_frac_dp/n4091 ) );
AO22X1 U489 ( .IN1(n1354), .IN2(n330), .IN3(inq_in2[13]), .IN4(n1361), .Q(
\fpu_add_frac_dp/n4090 ) );
AO22X1 U490 ( .IN1(n1353), .IN2(n1007), .IN3(inq_in2[14]), .IN4(n1361), .Q(
\fpu_add_frac_dp/n4089 ) );
AO22X1 U491 ( .IN1(n1353), .IN2(n1203), .IN3(inq_in2[15]), .IN4(n1361), .Q(
\fpu_add_frac_dp/n4088 ) );
AO22X1 U492 ( .IN1(n1354), .IN2(n1193), .IN3(inq_in2[16]), .IN4(n1361), .Q(
\fpu_add_frac_dp/n4087 ) );
AO22X1 U493 ( .IN1(n1353), .IN2(n1131), .IN3(inq_in2[17]), .IN4(n1361), .Q(
\fpu_add_frac_dp/n4086 ) );
AO22X1 U494 ( .IN1(n1354), .IN2(n1192), .IN3(inq_in2[18]), .IN4(n1361), .Q(
\fpu_add_frac_dp/n4085 ) );
AO22X1 U495 ( .IN1(\fpu_add_frac_dp/n2485 ), .IN2(n1355), .IN3(inq_in2[19]),
.IN4(n1360), .Q(\fpu_add_frac_dp/n4084 ) );
AO22X1 U496 ( .IN1(\fpu_add_frac_dp/n2487 ), .IN2(n1355), .IN3(inq_in2[20]),
.IN4(n1360), .Q(\fpu_add_frac_dp/n4083 ) );
AO22X1 U497 ( .IN1(n1354), .IN2(n335), .IN3(inq_in2[21]), .IN4(n1360), .Q(
\fpu_add_frac_dp/n4082 ) );
AO22X1 U498 ( .IN1(\fpu_add_frac_dp/n2492 ), .IN2(n1355), .IN3(inq_in2[22]),
.IN4(n1360), .Q(\fpu_add_frac_dp/n4081 ) );
AO22X1 U499 ( .IN1(\fpu_add_frac_dp/n2458 ), .IN2(n1355), .IN3(inq_in2[23]),
.IN4(n1360), .Q(\fpu_add_frac_dp/n4080 ) );
AO22X1 U500 ( .IN1(n1354), .IN2(n1127), .IN3(inq_in2[24]), .IN4(n1360), .Q(
\fpu_add_frac_dp/n4079 ) );
AO22X1 U501 ( .IN1(\fpu_add_frac_dp/n2486 ), .IN2(n1355), .IN3(inq_in2[25]),
.IN4(n1360), .Q(\fpu_add_frac_dp/n4078 ) );
AO22X1 U502 ( .IN1(\fpu_add_frac_dp/n2482 ), .IN2(n1355), .IN3(inq_in2[26]),
.IN4(n1360), .Q(\fpu_add_frac_dp/n4077 ) );
AO22X1 U503 ( .IN1(\fpu_add_frac_dp/n5608 ), .IN2(n1355), .IN3(inq_in2[27]),
.IN4(n1360), .Q(\fpu_add_frac_dp/n4076 ) );
AO22X1 U504 ( .IN1(\fpu_add_frac_dp/n5605 ), .IN2(n1354), .IN3(inq_in2[28]),
.IN4(n1360), .Q(\fpu_add_frac_dp/n4075 ) );
AO22X1 U505 ( .IN1(n1353), .IN2(n1132), .IN3(inq_in2[29]), .IN4(n1360), .Q(
\fpu_add_frac_dp/n4074 ) );
AO22X1 U506 ( .IN1(n1353), .IN2(n132), .IN3(inq_in2[30]), .IN4(n1360), .Q(
\fpu_add_frac_dp/n4073 ) );
AO22X1 U507 ( .IN1(n1353), .IN2(n1194), .IN3(inq_in2[31]), .IN4(n1359), .Q(
\fpu_add_frac_dp/n4072 ) );
AO22X1 U508 ( .IN1(\fpu_add_frac_dp/n5622 ), .IN2(n1354), .IN3(inq_in2[32]),
.IN4(n1359), .Q(\fpu_add_frac_dp/n4071 ) );
AO22X1 U509 ( .IN1(n1353), .IN2(n326), .IN3(inq_in2[33]), .IN4(n1359), .Q(
\fpu_add_frac_dp/n4070 ) );
AO22X1 U510 ( .IN1(n1353), .IN2(n916), .IN3(inq_in2[34]), .IN4(n1359), .Q(
\fpu_add_frac_dp/n4069 ) );
AO22X1 U511 ( .IN1(\fpu_add_frac_dp/n5623 ), .IN2(n1354), .IN3(inq_in2[35]),
.IN4(n1359), .Q(\fpu_add_frac_dp/n4068 ) );
AO22X1 U512 ( .IN1(n1352), .IN2(n1207), .IN3(inq_in2[36]), .IN4(n1359), .Q(
\fpu_add_frac_dp/n4067 ) );
AO22X1 U513 ( .IN1(\fpu_add_frac_dp/n5612 ), .IN2(n1354), .IN3(inq_in2[37]),
.IN4(n1359), .Q(\fpu_add_frac_dp/n4066 ) );
AO22X1 U514 ( .IN1(\fpu_add_frac_dp/n5613 ), .IN2(n1354), .IN3(inq_in2[38]),
.IN4(n1359), .Q(\fpu_add_frac_dp/n4065 ) );
AO22X1 U515 ( .IN1(n1352), .IN2(n141), .IN3(inq_in2[39]), .IN4(n1359), .Q(
\fpu_add_frac_dp/n4064 ) );
AO22X1 U516 ( .IN1(n1353), .IN2(n463), .IN3(inq_in2[40]), .IN4(n1359), .Q(
\fpu_add_frac_dp/n4063 ) );
AO22X1 U517 ( .IN1(\fpu_add_frac_dp/n5620 ), .IN2(n1355), .IN3(inq_in2[41]),
.IN4(n1359), .Q(\fpu_add_frac_dp/n4062 ) );
AO22X1 U518 ( .IN1(n1352), .IN2(n1199), .IN3(inq_in2[42]), .IN4(n1359), .Q(
\fpu_add_frac_dp/n4061 ) );
AO22X1 U519 ( .IN1(n1352), .IN2(n763), .IN3(inq_in2[43]), .IN4(n1358), .Q(
\fpu_add_frac_dp/n4060 ) );
AO22X1 U520 ( .IN1(\fpu_add_frac_dp/n5621 ), .IN2(n1354), .IN3(inq_in2[44]),
.IN4(n1358), .Q(\fpu_add_frac_dp/n4059 ) );
AO22X1 U521 ( .IN1(n1351), .IN2(n1208), .IN3(inq_in2[45]), .IN4(n1358), .Q(
\fpu_add_frac_dp/n4058 ) );
AO22X1 U522 ( .IN1(\fpu_add_frac_dp/n5611 ), .IN2(n1354), .IN3(inq_in2[46]),
.IN4(n1358), .Q(\fpu_add_frac_dp/n4057 ) );
AO22X1 U523 ( .IN1(\fpu_add_frac_dp/n5624 ), .IN2(n1355), .IN3(inq_in2[47]),
.IN4(n1358), .Q(\fpu_add_frac_dp/n4056 ) );
AO22X1 U524 ( .IN1(n1351), .IN2(n1211), .IN3(inq_in2[48]), .IN4(n1358), .Q(
\fpu_add_frac_dp/n4055 ) );
AO22X1 U525 ( .IN1(n1350), .IN2(n1065), .IN3(inq_in2[49]), .IN4(n1358), .Q(
\fpu_add_frac_dp/n4054 ) );
AO22X1 U526 ( .IN1(n1350), .IN2(n427), .IN3(inq_in2[50]), .IN4(n1358), .Q(
\fpu_add_frac_dp/n4053 ) );
AO22X1 U527 ( .IN1(\fpu_add_frac_dp/n2491 ), .IN2(n1354), .IN3(inq_in2[51]),
.IN4(n1358), .Q(\fpu_add_frac_dp/n4052 ) );
AO22X1 U528 ( .IN1(\fpu_add_frac_dp/n5644 ), .IN2(n1354), .IN3(inq_in2[52]),
.IN4(n1358), .Q(\fpu_add_frac_dp/n4051 ) );
AO22X1 U529 ( .IN1(n1353), .IN2(n650), .IN3(inq_in2[53]), .IN4(n1358), .Q(
\fpu_add_frac_dp/n4050 ) );
AO22X1 U530 ( .IN1(n1343), .IN2(n1130), .IN3(inq_in2[54]), .IN4(n1358), .Q(
\fpu_add_frac_dp/n4049 ) );
NOR2X0 U531 ( .IN1(a1stg_step), .IN2(se_add_frac), .QN(n1588) );
AO22X1 U532 ( .IN1(n1426), .IN2(n307), .IN3(n1590), .IN4(n36), .Q(
\fpu_add_frac_dp/n4048 ) );
AO22X1 U533 ( .IN1(n1422), .IN2(n625), .IN3(n1590), .IN4(n170), .Q(
\fpu_add_frac_dp/n4047 ) );
AO22X1 U534 ( .IN1(n1422), .IN2(n220), .IN3(n1590), .IN4(n10), .Q(
\fpu_add_frac_dp/n4046 ) );
AO22X1 U535 ( .IN1(n1422), .IN2(n310), .IN3(n1590), .IN4(n1589), .Q(
\fpu_add_frac_dp/n4045 ) );
AO22X1 U536 ( .IN1(n1422), .IN2(n288), .IN3(n1590), .IN4(n11), .Q(
\fpu_add_frac_dp/n4044 ) );
AO22X1 U537 ( .IN1(n1422), .IN2(n223), .IN3(n1590), .IN4(n30), .Q(
\fpu_add_frac_dp/n4043 ) );
AO22X1 U538 ( .IN1(n1422), .IN2(n225), .IN3(n1590), .IN4(n79), .Q(
\fpu_add_frac_dp/n4042 ) );
AO22X1 U539 ( .IN1(n1422), .IN2(n222), .IN3(n1590), .IN4(n31), .Q(
\fpu_add_frac_dp/n4041 ) );
AO22X1 U540 ( .IN1(n1422), .IN2(n224), .IN3(n1590), .IN4(n80), .Q(
\fpu_add_frac_dp/n4040 ) );
AO22X1 U541 ( .IN1(n1422), .IN2(n261), .IN3(n1590), .IN4(n32), .Q(
\fpu_add_frac_dp/n4039 ) );
AO22X1 U542 ( .IN1(n1422), .IN2(n260), .IN3(n1590), .IN4(n81), .Q(
\fpu_add_frac_dp/n4038 ) );
AO221X1 U543 ( .IN1(n1591), .IN2(n612), .IN3(n1389), .IN4(n253), .IN5(n1592),
.Q(\fpu_add_frac_dp/n4037 ) );
AO221X1 U544 ( .IN1(n1593), .IN2(n1594), .IN3(n1590), .IN4(n39), .IN5(n1595),
.Q(n1592) );
AND2X1 U545 ( .IN1(n1596), .IN2(n1597), .Q(n1590) );
NOR2X0 U546 ( .IN1(\fpu_add_frac_dp/n898 ), .IN2(n1598), .QN(n1593) );
AO221X1 U547 ( .IN1(n1597), .IN2(n1599), .IN3(n1390), .IN4(n252), .IN5(n1600), .Q(\fpu_add_frac_dp/n4036 ) );
AO221X1 U548 ( .IN1(n1601), .IN2(n612), .IN3(n1591), .IN4(n93), .IN5(n1595),
.Q(n1600) );
AO221X1 U549 ( .IN1(n1597), .IN2(n1602), .IN3(n1392), .IN4(n327), .IN5(n1603), .Q(\fpu_add_frac_dp/n4035 ) );
AO221X1 U550 ( .IN1(n1601), .IN2(n93), .IN3(n1591), .IN4(n182), .IN5(n1595),
.Q(n1603) );
AO221X1 U551 ( .IN1(n1597), .IN2(n1604), .IN3(n1392), .IN4(n180), .IN5(n1605), .Q(\fpu_add_frac_dp/n4034 ) );
AO221X1 U552 ( .IN1(n1601), .IN2(n182), .IN3(n1591), .IN4(n599), .IN5(n1595),
.Q(n1605) );
AO221X1 U553 ( .IN1(n1597), .IN2(n1606), .IN3(n1392), .IN4(n268), .IN5(n1607), .Q(\fpu_add_frac_dp/n4033 ) );
AO221X1 U554 ( .IN1(n1601), .IN2(n599), .IN3(n1591), .IN4(n183), .IN5(n1595),
.Q(n1607) );
AO221X1 U555 ( .IN1(n1597), .IN2(n1608), .IN3(n1393), .IN4(n179), .IN5(n1609), .Q(\fpu_add_frac_dp/n4032 ) );
AO221X1 U556 ( .IN1(n1601), .IN2(n183), .IN3(n1591), .IN4(n600), .IN5(n1595),
.Q(n1609) );
AO221X1 U557 ( .IN1(n1597), .IN2(n1610), .IN3(n1393), .IN4(n251), .IN5(n1611), .Q(\fpu_add_frac_dp/n4031 ) );
AO221X1 U558 ( .IN1(n1601), .IN2(n600), .IN3(n1591), .IN4(n184), .IN5(n1595),
.Q(n1611) );
AO221X1 U559 ( .IN1(n1597), .IN2(n1612), .IN3(n1393), .IN4(n250), .IN5(n1613), .Q(\fpu_add_frac_dp/n4030 ) );
AO221X1 U560 ( .IN1(n1601), .IN2(n184), .IN3(n1591), .IN4(n601), .IN5(n1595),
.Q(n1613) );
AO221X1 U561 ( .IN1(n1597), .IN2(n1614), .IN3(n1393), .IN4(n249), .IN5(n1615), .Q(\fpu_add_frac_dp/n4029 ) );
AO221X1 U562 ( .IN1(n1601), .IN2(n601), .IN3(n1591), .IN4(n185), .IN5(n1595),
.Q(n1615) );
AO221X1 U563 ( .IN1(n1597), .IN2(n1616), .IN3(n1393), .IN4(n263), .IN5(n1617), .Q(\fpu_add_frac_dp/n4028 ) );
AO221X1 U564 ( .IN1(n1601), .IN2(n185), .IN3(n1591), .IN4(n602), .IN5(n1595),
.Q(n1617) );
AO221X1 U565 ( .IN1(n1597), .IN2(n1618), .IN3(n1393), .IN4(n267), .IN5(n1619), .Q(\fpu_add_frac_dp/n4027 ) );
AO221X1 U566 ( .IN1(n1601), .IN2(n602), .IN3(n1591), .IN4(n186), .IN5(n1595),
.Q(n1619) );
AO221X1 U567 ( .IN1(n1597), .IN2(n1620), .IN3(n1393), .IN4(n279), .IN5(n1621), .Q(\fpu_add_frac_dp/n4026 ) );
AO221X1 U568 ( .IN1(n1601), .IN2(n186), .IN3(n1591), .IN4(n603), .IN5(n1595),
.Q(n1621) );
AO221X1 U569 ( .IN1(n1597), .IN2(n1622), .IN3(n1393), .IN4(n318), .IN5(n1623), .Q(\fpu_add_frac_dp/n4025 ) );
AO221X1 U570 ( .IN1(n1601), .IN2(n603), .IN3(n1591), .IN4(n187), .IN5(n1595),
.Q(n1623) );
AO221X1 U571 ( .IN1(n1597), .IN2(n1624), .IN3(n1393), .IN4(n248), .IN5(n1625), .Q(\fpu_add_frac_dp/n4024 ) );
AO221X1 U572 ( .IN1(n1601), .IN2(n187), .IN3(n1591), .IN4(n604), .IN5(n1595),
.Q(n1625) );
AO221X1 U573 ( .IN1(n1597), .IN2(n1626), .IN3(n1394), .IN4(n247), .IN5(n1627), .Q(\fpu_add_frac_dp/n4023 ) );
AO221X1 U574 ( .IN1(n1601), .IN2(n604), .IN3(n1591), .IN4(n188), .IN5(n1595),
.Q(n1627) );
AO221X1 U575 ( .IN1(n1597), .IN2(n1628), .IN3(n1395), .IN4(n246), .IN5(n1629), .Q(\fpu_add_frac_dp/n4022 ) );
AO221X1 U576 ( .IN1(n1601), .IN2(n188), .IN3(n1591), .IN4(n605), .IN5(n1595),
.Q(n1629) );
AO221X1 U577 ( .IN1(n1597), .IN2(n1630), .IN3(n1389), .IN4(n204), .IN5(n1631), .Q(\fpu_add_frac_dp/n4021 ) );
AO221X1 U578 ( .IN1(n1601), .IN2(n605), .IN3(n1591), .IN4(n189), .IN5(n1595),
.Q(n1631) );
AO221X1 U579 ( .IN1(n1597), .IN2(n1632), .IN3(n1394), .IN4(n245), .IN5(n1633), .Q(\fpu_add_frac_dp/n4020 ) );
AO221X1 U580 ( .IN1(n1601), .IN2(n189), .IN3(n1591), .IN4(n606), .IN5(n1595),
.Q(n1633) );
AO221X1 U581 ( .IN1(n1597), .IN2(n1634), .IN3(n1394), .IN4(n244), .IN5(n1635), .Q(\fpu_add_frac_dp/n4019 ) );
AO221X1 U582 ( .IN1(n1601), .IN2(n606), .IN3(n1591), .IN4(n190), .IN5(n1595),
.Q(n1635) );
AO221X1 U583 ( .IN1(n1597), .IN2(n1636), .IN3(n1394), .IN4(n203), .IN5(n1637), .Q(\fpu_add_frac_dp/n4018 ) );
AO221X1 U584 ( .IN1(n1601), .IN2(n190), .IN3(n1591), .IN4(n607), .IN5(n1595),
.Q(n1637) );
AO221X1 U585 ( .IN1(n1597), .IN2(n1638), .IN3(n1394), .IN4(n243), .IN5(n1639), .Q(\fpu_add_frac_dp/n4017 ) );
AO221X1 U586 ( .IN1(n1601), .IN2(n607), .IN3(n1591), .IN4(n191), .IN5(n1595),
.Q(n1639) );
AO221X1 U587 ( .IN1(n1597), .IN2(n1640), .IN3(n1394), .IN4(n242), .IN5(n1641), .Q(\fpu_add_frac_dp/n4016 ) );
AO221X1 U588 ( .IN1(n1601), .IN2(n191), .IN3(n1591), .IN4(n608), .IN5(n1595),
.Q(n1641) );
AO221X1 U589 ( .IN1(n1597), .IN2(n1642), .IN3(n1394), .IN4(n241), .IN5(n1643), .Q(\fpu_add_frac_dp/n4015 ) );
AO221X1 U590 ( .IN1(n1601), .IN2(n608), .IN3(n1591), .IN4(n192), .IN5(n1595),
.Q(n1643) );
AO221X1 U591 ( .IN1(n1597), .IN2(n1644), .IN3(n1394), .IN4(n240), .IN5(n1645), .Q(\fpu_add_frac_dp/n4014 ) );
AO221X1 U592 ( .IN1(n1601), .IN2(n192), .IN3(n1591), .IN4(n609), .IN5(n1595),
.Q(n1645) );
AO221X1 U593 ( .IN1(n1597), .IN2(n1646), .IN3(n1394), .IN4(n202), .IN5(n1647), .Q(\fpu_add_frac_dp/n4013 ) );
AO221X1 U594 ( .IN1(n1601), .IN2(n609), .IN3(n1591), .IN4(n193), .IN5(n1595),
.Q(n1647) );
AO221X1 U595 ( .IN1(n1597), .IN2(n1648), .IN3(n1395), .IN4(n239), .IN5(n1649), .Q(\fpu_add_frac_dp/n4012 ) );
AO221X1 U596 ( .IN1(n1601), .IN2(n193), .IN3(n1591), .IN4(n610), .IN5(n1595),
.Q(n1649) );
AO221X1 U597 ( .IN1(n1597), .IN2(n1650), .IN3(n1395), .IN4(n201), .IN5(n1651), .Q(\fpu_add_frac_dp/n4011 ) );
AO221X1 U598 ( .IN1(n1601), .IN2(n610), .IN3(n1591), .IN4(n194), .IN5(n1595),
.Q(n1651) );
AO221X1 U599 ( .IN1(n1597), .IN2(n1652), .IN3(n1395), .IN4(n238), .IN5(n1653), .Q(\fpu_add_frac_dp/n4010 ) );
AO221X1 U600 ( .IN1(n1601), .IN2(n194), .IN3(n1591), .IN4(n611), .IN5(n1595),
.Q(n1653) );
AO221X1 U601 ( .IN1(n1597), .IN2(n1654), .IN3(n1395), .IN4(n200), .IN5(n1655), .Q(\fpu_add_frac_dp/n4009 ) );
AO221X1 U602 ( .IN1(n1601), .IN2(n611), .IN3(n1591), .IN4(n207), .IN5(n1595),
.Q(n1655) );
AND4X1 U603 ( .IN1(n1656), .IN2(n1657), .IN3(n1658), .IN4(n1659), .Q(n1595)
);
NAND4X0 U604 ( .IN1(n1660), .IN2(n1661), .IN3(n1662), .IN4(n1663), .QN(
\fpu_add_frac_dp/n4008 ) );
AOI222X1 U605 ( .IN1(n259), .IN2(n1422), .IN3(n644), .IN4(n1591), .IN5(n1664), .IN6(n1597), .QN(n1663) );
NOR2X0 U606 ( .IN1(n1665), .IN2(n1666), .QN(n1591) );
NAND2X0 U607 ( .IN1(n1601), .IN2(n207), .QN(n1662) );
AND2X1 U608 ( .IN1(n1667), .IN2(n1668), .Q(n1601) );
NAND3X0 U609 ( .IN1(n1668), .IN2(n176), .IN3(n1669), .QN(n1660) );
AO221X1 U610 ( .IN1(n1597), .IN2(n1670), .IN3(n1395), .IN4(n237), .IN5(n1671), .Q(\fpu_add_frac_dp/n4007 ) );
AO21X1 U611 ( .IN1(n1668), .IN2(n1672), .IN3(n1673), .Q(n1671) );
AO221X1 U612 ( .IN1(n1597), .IN2(n1674), .IN3(n1394), .IN4(n199), .IN5(n1675), .Q(\fpu_add_frac_dp/n4006 ) );
AO21X1 U613 ( .IN1(n1668), .IN2(n1676), .IN3(n1673), .Q(n1675) );
AO221X1 U614 ( .IN1(n1597), .IN2(n1677), .IN3(n1395), .IN4(n236), .IN5(n1678), .Q(\fpu_add_frac_dp/n4005 ) );
AO21X1 U615 ( .IN1(n1668), .IN2(n1679), .IN3(n1673), .Q(n1678) );
AO221X1 U616 ( .IN1(n1597), .IN2(n1680), .IN3(n1395), .IN4(n235), .IN5(n1681), .Q(\fpu_add_frac_dp/n4004 ) );
AO21X1 U617 ( .IN1(n1668), .IN2(n1682), .IN3(n1673), .Q(n1681) );
AO221X1 U618 ( .IN1(n1597), .IN2(n1683), .IN3(n1395), .IN4(n234), .IN5(n1684), .Q(\fpu_add_frac_dp/n4003 ) );
AO21X1 U619 ( .IN1(n1668), .IN2(n1685), .IN3(n1673), .Q(n1684) );
AO221X1 U620 ( .IN1(n1597), .IN2(n1686), .IN3(n1395), .IN4(n198), .IN5(n1687), .Q(\fpu_add_frac_dp/n4002 ) );
AO21X1 U621 ( .IN1(n1668), .IN2(n1688), .IN3(n1673), .Q(n1687) );
AO221X1 U622 ( .IN1(n1597), .IN2(n1689), .IN3(n1396), .IN4(n197), .IN5(n1690), .Q(\fpu_add_frac_dp/n4001 ) );
AO21X1 U623 ( .IN1(n1668), .IN2(n1691), .IN3(n1673), .Q(n1690) );
AO221X1 U624 ( .IN1(n1597), .IN2(n1692), .IN3(n1396), .IN4(n233), .IN5(n1693), .Q(\fpu_add_frac_dp/n4000 ) );
AO21X1 U625 ( .IN1(n1668), .IN2(n1694), .IN3(n1673), .Q(n1693) );
AO221X1 U626 ( .IN1(n1597), .IN2(n1695), .IN3(n1395), .IN4(n232), .IN5(n1696), .Q(\fpu_add_frac_dp/n3999 ) );
AO21X1 U627 ( .IN1(n1668), .IN2(n1697), .IN3(n1673), .Q(n1696) );
AO221X1 U628 ( .IN1(n1597), .IN2(n1698), .IN3(n1396), .IN4(n231), .IN5(n1699), .Q(\fpu_add_frac_dp/n3998 ) );
AO21X1 U629 ( .IN1(n1668), .IN2(n1700), .IN3(n1673), .Q(n1699) );
AO221X1 U630 ( .IN1(n1597), .IN2(n1701), .IN3(n1394), .IN4(n230), .IN5(n1702), .Q(\fpu_add_frac_dp/n3997 ) );
AO21X1 U631 ( .IN1(n1668), .IN2(n1703), .IN3(n1673), .Q(n1702) );
AO221X1 U632 ( .IN1(n1597), .IN2(n1704), .IN3(n1396), .IN4(n229), .IN5(n1705), .Q(\fpu_add_frac_dp/n3996 ) );
AO21X1 U633 ( .IN1(n1668), .IN2(n1706), .IN3(n1673), .Q(n1705) );
AO221X1 U634 ( .IN1(n1597), .IN2(n1707), .IN3(n1394), .IN4(n228), .IN5(n1708), .Q(\fpu_add_frac_dp/n3995 ) );
AO21X1 U635 ( .IN1(n1668), .IN2(n1709), .IN3(n1673), .Q(n1708) );
AO221X1 U636 ( .IN1(n1597), .IN2(n1710), .IN3(n1396), .IN4(n227), .IN5(n1711), .Q(\fpu_add_frac_dp/n3994 ) );
AO21X1 U637 ( .IN1(n1668), .IN2(n1712), .IN3(n1673), .Q(n1711) );
AO221X1 U638 ( .IN1(n1597), .IN2(n1713), .IN3(n1394), .IN4(n196), .IN5(n1714), .Q(\fpu_add_frac_dp/n3993 ) );
AO21X1 U639 ( .IN1(n1668), .IN2(n1715), .IN3(n1673), .Q(n1714) );
AO221X1 U640 ( .IN1(n1597), .IN2(n1716), .IN3(n1396), .IN4(n294), .IN5(n1717), .Q(\fpu_add_frac_dp/n3992 ) );
AO21X1 U641 ( .IN1(n1668), .IN2(n1718), .IN3(n1673), .Q(n1717) );
AO221X1 U642 ( .IN1(n1597), .IN2(n1719), .IN3(n1395), .IN4(n332), .IN5(n1720), .Q(\fpu_add_frac_dp/n3991 ) );
AO21X1 U643 ( .IN1(n1668), .IN2(n1721), .IN3(n1673), .Q(n1720) );
AO221X1 U644 ( .IN1(n1597), .IN2(n1722), .IN3(n1396), .IN4(n334), .IN5(n1723), .Q(\fpu_add_frac_dp/n3990 ) );
AO21X1 U645 ( .IN1(n1668), .IN2(n1724), .IN3(n1673), .Q(n1723) );
AO221X1 U646 ( .IN1(n1597), .IN2(n1725), .IN3(n1395), .IN4(n293), .IN5(n1726), .Q(\fpu_add_frac_dp/n3989 ) );
AO21X1 U647 ( .IN1(n1668), .IN2(n1727), .IN3(n1673), .Q(n1726) );
AO221X1 U648 ( .IN1(n1597), .IN2(n1728), .IN3(n1396), .IN4(n317), .IN5(n1729), .Q(\fpu_add_frac_dp/n3988 ) );
AO21X1 U649 ( .IN1(n1668), .IN2(n1730), .IN3(n1673), .Q(n1729) );
AO221X1 U650 ( .IN1(n1597), .IN2(n1731), .IN3(n1395), .IN4(n195), .IN5(n1732), .Q(\fpu_add_frac_dp/n3987 ) );
AO21X1 U651 ( .IN1(n1668), .IN2(n1733), .IN3(n1673), .Q(n1732) );
AO221X1 U652 ( .IN1(n1597), .IN2(n1734), .IN3(n1396), .IN4(n226), .IN5(n1735), .Q(\fpu_add_frac_dp/n3986 ) );
AO221X1 U653 ( .IN1(n1736), .IN2(n1737), .IN3(n1668), .IN4(n1738), .IN5(
n1673), .Q(n1735) );
INVX0 U654 ( .INP(n1661), .ZN(n1673) );
NAND2X0 U655 ( .IN1(n1739), .IN2(n1659), .QN(n1661) );
INVX0 U656 ( .INP(n1740), .ZN(n1739) );
AND2X1 U657 ( .IN1(n1741), .IN2(n1659), .Q(n1736) );
NAND2X0 U658 ( .IN1(n1598), .IN2(n1666), .QN(n1659) );
AO222X1 U659 ( .IN1(n1597), .IN2(n1742), .IN3(n1668), .IN4(n1743), .IN5(
n1384), .IN6(n850), .Q(\fpu_add_frac_dp/n3985 ) );
INVX0 U660 ( .INP(n1666), .ZN(n1668) );
AO21X1 U661 ( .IN1(n1737), .IN2(n1744), .IN3(n1745), .Q(n1666) );
NAND3X0 U662 ( .IN1(n1435), .IN2(n1744), .IN3(n1737), .QN(n1598) );
AO221X1 U663 ( .IN1(n1747), .IN2(n1748), .IN3(n1749), .IN4(n1750), .IN5(
n1751), .Q(n1744) );
OR2X1 U664 ( .IN1(n1752), .IN2(n1753), .Q(n1747) );
AO22X1 U665 ( .IN1(n1419), .IN2(n1196), .IN3(n1754), .IN4(n36), .Q(
\fpu_add_frac_dp/n3984 ) );
AO22X1 U666 ( .IN1(n1419), .IN2(n1134), .IN3(n1754), .IN4(n170), .Q(
\fpu_add_frac_dp/n3983 ) );
AO22X1 U667 ( .IN1(n1419), .IN2(n1135), .IN3(n1754), .IN4(n10), .Q(
\fpu_add_frac_dp/n3982 ) );
AO22X1 U668 ( .IN1(n1419), .IN2(n1136), .IN3(n1754), .IN4(n1589), .Q(
\fpu_add_frac_dp/n3981 ) );
AO22X1 U669 ( .IN1(n1419), .IN2(n1137), .IN3(n1754), .IN4(n11), .Q(
\fpu_add_frac_dp/n3980 ) );
AO22X1 U670 ( .IN1(n1419), .IN2(n1149), .IN3(n1754), .IN4(n30), .Q(
\fpu_add_frac_dp/n3979 ) );
AO22X1 U671 ( .IN1(n1419), .IN2(n1138), .IN3(n1754), .IN4(n79), .Q(
\fpu_add_frac_dp/n3978 ) );
AO22X1 U672 ( .IN1(n1419), .IN2(n1139), .IN3(n1754), .IN4(n31), .Q(
\fpu_add_frac_dp/n3977 ) );
AO22X1 U673 ( .IN1(n1418), .IN2(n1140), .IN3(n1754), .IN4(n80), .Q(
\fpu_add_frac_dp/n3976 ) );
AO22X1 U674 ( .IN1(n1418), .IN2(n1141), .IN3(n1754), .IN4(n32), .Q(
\fpu_add_frac_dp/n3975 ) );
AO22X1 U675 ( .IN1(n1418), .IN2(n1142), .IN3(n1754), .IN4(n81), .Q(
\fpu_add_frac_dp/n3974 ) );
AO21X1 U676 ( .IN1(n1397), .IN2(n1111), .IN3(n1755), .Q(
\fpu_add_frac_dp/n3973 ) );
AO21X1 U677 ( .IN1(\fpu_add_frac_dp/n2389 ), .IN2(n1415), .IN3(n1756), .Q(
\fpu_add_frac_dp/n3972 ) );
AO21X1 U678 ( .IN1(n1398), .IN2(n1091), .IN3(n1757), .Q(
\fpu_add_frac_dp/n3971 ) );
AO21X1 U679 ( .IN1(n1398), .IN2(n1122), .IN3(n1758), .Q(
\fpu_add_frac_dp/n3970 ) );
AO21X1 U680 ( .IN1(n1398), .IN2(n1125), .IN3(n1759), .Q(
\fpu_add_frac_dp/n3969 ) );
AO21X1 U681 ( .IN1(n1398), .IN2(n1123), .IN3(n1760), .Q(
\fpu_add_frac_dp/n3968 ) );
AO21X1 U682 ( .IN1(n1398), .IN2(n722), .IN3(n1761), .Q(
\fpu_add_frac_dp/n3967 ) );
AO21X1 U683 ( .IN1(n1398), .IN2(n423), .IN3(n1762), .Q(
\fpu_add_frac_dp/n3966 ) );
AO21X1 U684 ( .IN1(n1398), .IN2(n1104), .IN3(n1763), .Q(
\fpu_add_frac_dp/n3965 ) );
AO21X1 U685 ( .IN1(n1398), .IN2(n1092), .IN3(n1764), .Q(
\fpu_add_frac_dp/n3964 ) );
AO21X1 U686 ( .IN1(n1398), .IN2(n1112), .IN3(n1765), .Q(
\fpu_add_frac_dp/n3963 ) );
AO21X1 U687 ( .IN1(n1398), .IN2(n724), .IN3(n1766), .Q(
\fpu_add_frac_dp/n3962 ) );
AO21X1 U688 ( .IN1(n1398), .IN2(n426), .IN3(n1767), .Q(
\fpu_add_frac_dp/n3961 ) );
AO21X1 U689 ( .IN1(n1398), .IN2(n1105), .IN3(n1768), .Q(
\fpu_add_frac_dp/n3960 ) );
AO21X1 U690 ( .IN1(n1398), .IN2(n1093), .IN3(n1769), .Q(
\fpu_add_frac_dp/n3959 ) );
AO21X1 U691 ( .IN1(n1398), .IN2(n1113), .IN3(n1770), .Q(
\fpu_add_frac_dp/n3958 ) );
AO21X1 U692 ( .IN1(n1399), .IN2(n723), .IN3(n1771), .Q(
\fpu_add_frac_dp/n3957 ) );
AO21X1 U693 ( .IN1(n1399), .IN2(n424), .IN3(n1772), .Q(
\fpu_add_frac_dp/n3956 ) );
AO21X1 U694 ( .IN1(n1399), .IN2(n1106), .IN3(n1773), .Q(
\fpu_add_frac_dp/n3955 ) );
AO21X1 U695 ( .IN1(n1399), .IN2(n1094), .IN3(n1774), .Q(
\fpu_add_frac_dp/n3954 ) );
AO21X1 U696 ( .IN1(n1399), .IN2(n1114), .IN3(n1775), .Q(
\fpu_add_frac_dp/n3953 ) );
AO21X1 U697 ( .IN1(n1399), .IN2(n1107), .IN3(n1776), .Q(
\fpu_add_frac_dp/n3952 ) );
AO21X1 U698 ( .IN1(n1399), .IN2(n1095), .IN3(n1777), .Q(
\fpu_add_frac_dp/n3951 ) );
AO21X1 U699 ( .IN1(n1399), .IN2(n1096), .IN3(n1778), .Q(
\fpu_add_frac_dp/n3950 ) );
AO21X1 U700 ( .IN1(n1399), .IN2(n1115), .IN3(n1779), .Q(
\fpu_add_frac_dp/n3949 ) );
AO21X1 U701 ( .IN1(n1399), .IN2(n1108), .IN3(n1780), .Q(
\fpu_add_frac_dp/n3948 ) );
AO21X1 U702 ( .IN1(n1399), .IN2(n1097), .IN3(n1781), .Q(
\fpu_add_frac_dp/n3947 ) );
AO21X1 U703 ( .IN1(n1399), .IN2(n1098), .IN3(n1782), .Q(
\fpu_add_frac_dp/n3946 ) );
AO21X1 U704 ( .IN1(n1399), .IN2(n1116), .IN3(n1783), .Q(
\fpu_add_frac_dp/n3945 ) );
AO21X1 U705 ( .IN1(n1400), .IN2(n1109), .IN3(n1784), .Q(
\fpu_add_frac_dp/n3944 ) );
AO21X1 U706 ( .IN1(n1400), .IN2(n1099), .IN3(n1785), .Q(
\fpu_add_frac_dp/n3943 ) );
AO21X1 U707 ( .IN1(n1400), .IN2(n1102), .IN3(n1786), .Q(
\fpu_add_frac_dp/n3942 ) );
AO21X1 U708 ( .IN1(n1400), .IN2(n1117), .IN3(n1787), .Q(
\fpu_add_frac_dp/n3941 ) );
AO21X1 U709 ( .IN1(n1400), .IN2(n58), .IN3(n1788), .Q(
\fpu_add_frac_dp/n3940 ) );
AO21X1 U710 ( .IN1(n1400), .IN2(n143), .IN3(n1789), .Q(
\fpu_add_frac_dp/n3939 ) );
AO21X1 U711 ( .IN1(n1400), .IN2(n344), .IN3(n1790), .Q(
\fpu_add_frac_dp/n3938 ) );
AO21X1 U712 ( .IN1(n1396), .IN2(n707), .IN3(n1791), .Q(
\fpu_add_frac_dp/n3937 ) );
AO21X1 U713 ( .IN1(n1404), .IN2(n59), .IN3(n1792), .Q(
\fpu_add_frac_dp/n3936 ) );
AO21X1 U714 ( .IN1(n1404), .IN2(n144), .IN3(n1793), .Q(
\fpu_add_frac_dp/n3935 ) );
AO21X1 U715 ( .IN1(n1404), .IN2(n345), .IN3(n1794), .Q(
\fpu_add_frac_dp/n3934 ) );
AO21X1 U716 ( .IN1(n1404), .IN2(n708), .IN3(n1795), .Q(
\fpu_add_frac_dp/n3933 ) );
AO21X1 U717 ( .IN1(n1404), .IN2(n1110), .IN3(n1796), .Q(
\fpu_add_frac_dp/n3932 ) );
AO21X1 U718 ( .IN1(n1403), .IN2(n1100), .IN3(n1797), .Q(
\fpu_add_frac_dp/n3931 ) );
AO21X1 U719 ( .IN1(n1403), .IN2(n1103), .IN3(n1798), .Q(
\fpu_add_frac_dp/n3930 ) );
AO21X1 U720 ( .IN1(n1403), .IN2(n1118), .IN3(n1799), .Q(
\fpu_add_frac_dp/n3929 ) );
AO21X1 U721 ( .IN1(n1403), .IN2(n343), .IN3(n1800), .Q(
\fpu_add_frac_dp/n3928 ) );
AO21X1 U722 ( .IN1(\fpu_add_frac_dp/n2392 ), .IN2(n1415), .IN3(n1801), .Q(
\fpu_add_frac_dp/n3927 ) );
AO21X1 U723 ( .IN1(\fpu_add_frac_dp/n2390 ), .IN2(n1415), .IN3(n1802), .Q(
\fpu_add_frac_dp/n3926 ) );
AO21X1 U724 ( .IN1(\fpu_add_frac_dp/n2391 ), .IN2(n1415), .IN3(n1803), .Q(
\fpu_add_frac_dp/n3925 ) );
AO21X1 U725 ( .IN1(\fpu_add_frac_dp/n2384 ), .IN2(n1415), .IN3(n1804), .Q(
\fpu_add_frac_dp/n3924 ) );
AO21X1 U726 ( .IN1(n1403), .IN2(n706), .IN3(n1805), .Q(
\fpu_add_frac_dp/n3923 ) );
AO21X1 U727 ( .IN1(n1403), .IN2(n142), .IN3(n1806), .Q(
\fpu_add_frac_dp/n3922 ) );
AO21X1 U728 ( .IN1(n1403), .IN2(n1101), .IN3(n1807), .Q(
\fpu_add_frac_dp/n3921 ) );
AO22X1 U729 ( .IN1(n1428), .IN2(n896), .IN3(n1754), .IN4(n36), .Q(
\fpu_add_frac_dp/n3920 ) );
AO22X1 U730 ( .IN1(n1430), .IN2(n902), .IN3(n1754), .IN4(n170), .Q(
\fpu_add_frac_dp/n3919 ) );
AO22X1 U731 ( .IN1(n1429), .IN2(n690), .IN3(n1754), .IN4(n10), .Q(
\fpu_add_frac_dp/n3918 ) );
AO22X1 U732 ( .IN1(n1430), .IN2(n899), .IN3(n1754), .IN4(n1589), .Q(
\fpu_add_frac_dp/n3917 ) );
AO22X1 U733 ( .IN1(n1429), .IN2(n660), .IN3(n1754), .IN4(n11), .Q(
\fpu_add_frac_dp/n3916 ) );
AO22X1 U734 ( .IN1(n1429), .IN2(n898), .IN3(n1754), .IN4(n30), .Q(
\fpu_add_frac_dp/n3915 ) );
AO22X1 U735 ( .IN1(n1428), .IN2(n655), .IN3(n1754), .IN4(n79), .Q(
\fpu_add_frac_dp/n3914 ) );
AO22X1 U736 ( .IN1(n1429), .IN2(n901), .IN3(n1754), .IN4(n31), .Q(
\fpu_add_frac_dp/n3913 ) );
AO22X1 U737 ( .IN1(n1429), .IN2(n659), .IN3(n1754), .IN4(n80), .Q(
\fpu_add_frac_dp/n3912 ) );
AO22X1 U738 ( .IN1(n1429), .IN2(n75), .IN3(n1754), .IN4(n32), .Q(
\fpu_add_frac_dp/n3911 ) );
AO22X1 U739 ( .IN1(n1429), .IN2(n161), .IN3(n1754), .IN4(n81), .Q(
\fpu_add_frac_dp/n3910 ) );
AO21X1 U740 ( .IN1(n1403), .IN2(n627), .IN3(n1755), .Q(
\fpu_add_frac_dp/n3909 ) );
AO222X1 U741 ( .IN1(n1754), .IN2(n39), .IN3(n1808), .IN4(n1809), .IN5(n1810),
.IN6(n612), .Q(n1755) );
NOR2X0 U742 ( .IN1(\fpu_add_frac_dp/n898 ), .IN2(n1811), .QN(n1808) );
AND2X1 U743 ( .IN1(n1809), .IN2(n1596), .Q(n1754) );
AO21X1 U744 ( .IN1(n1403), .IN2(n150), .IN3(n1756), .Q(
\fpu_add_frac_dp/n3908 ) );
AO222X1 U745 ( .IN1(n1810), .IN2(n93), .IN3(n1809), .IN4(n1599), .IN5(n1812),
.IN6(n612), .Q(n1756) );
AO222X1 U746 ( .IN1(n1813), .IN2(n36), .IN3(n1596), .IN4(n120), .IN5(n1594),
.IN6(n170), .Q(n1599) );
AO21X1 U747 ( .IN1(n1403), .IN2(n721), .IN3(n1757), .Q(
\fpu_add_frac_dp/n3907 ) );
AO222X1 U748 ( .IN1(n1810), .IN2(n182), .IN3(n1809), .IN4(n1602), .IN5(n1812), .IN6(n93), .Q(n1757) );
AO222X1 U749 ( .IN1(n1813), .IN2(n170), .IN3(n1596), .IN4(n52), .IN5(n1594),
.IN6(n10), .Q(n1602) );
AO21X1 U750 ( .IN1(n1403), .IN2(n425), .IN3(n1758), .Q(
\fpu_add_frac_dp/n3906 ) );
AO222X1 U751 ( .IN1(n1810), .IN2(n599), .IN3(n1809), .IN4(n1604), .IN5(n1812), .IN6(n182), .Q(n1758) );
AO222X1 U752 ( .IN1(n1813), .IN2(n10), .IN3(n1596), .IN4(n121), .IN5(n1594),
.IN6(n1589), .Q(n1604) );
AO21X1 U753 ( .IN1(n1403), .IN2(n935), .IN3(n1759), .Q(
\fpu_add_frac_dp/n3905 ) );
AO222X1 U754 ( .IN1(n1810), .IN2(n183), .IN3(n1809), .IN4(n1606), .IN5(n1812), .IN6(n599), .Q(n1759) );
AO222X1 U755 ( .IN1(n1813), .IN2(n1589), .IN3(n1596), .IN4(n53), .IN5(n1594),
.IN6(n11), .Q(n1606) );
INVX0 U756 ( .INP(\fpu_add_frac_dp/n895 ), .ZN(n1589) );
AO21X1 U757 ( .IN1(n1403), .IN2(n930), .IN3(n1760), .Q(
\fpu_add_frac_dp/n3904 ) );
AO222X1 U758 ( .IN1(n1810), .IN2(n600), .IN3(n1809), .IN4(n1608), .IN5(n1812), .IN6(n183), .Q(n1760) );
AO222X1 U759 ( .IN1(n1813), .IN2(n11), .IN3(n1596), .IN4(n122), .IN5(n1594),
.IN6(n30), .Q(n1608) );
AO21X1 U760 ( .IN1(n1403), .IN2(n1151), .IN3(n1761), .Q(
\fpu_add_frac_dp/n3903 ) );
AO222X1 U761 ( .IN1(n1810), .IN2(n184), .IN3(n1809), .IN4(n1610), .IN5(n1812), .IN6(n600), .Q(n1761) );
AO222X1 U762 ( .IN1(n1813), .IN2(n30), .IN3(n1596), .IN4(n272), .IN5(n1594),
.IN6(n79), .Q(n1610) );
AO21X1 U763 ( .IN1(n1402), .IN2(n1152), .IN3(n1762), .Q(
\fpu_add_frac_dp/n3902 ) );
AO222X1 U764 ( .IN1(n1810), .IN2(n601), .IN3(n1809), .IN4(n1612), .IN5(n1812), .IN6(n184), .Q(n1762) );
AO222X1 U765 ( .IN1(n1813), .IN2(n79), .IN3(n1596), .IN4(n633), .IN5(n1594),
.IN6(n31), .Q(n1612) );
AO21X1 U766 ( .IN1(n1402), .IN2(n717), .IN3(n1763), .Q(
\fpu_add_frac_dp/n3901 ) );
AO222X1 U767 ( .IN1(n1810), .IN2(n185), .IN3(n1809), .IN4(n1614), .IN5(n1812), .IN6(n601), .Q(n1763) );
AO222X1 U768 ( .IN1(n1813), .IN2(n31), .IN3(n1596), .IN4(n273), .IN5(n1594),
.IN6(n80), .Q(n1614) );
AO21X1 U769 ( .IN1(n1402), .IN2(n314), .IN3(n1764), .Q(
\fpu_add_frac_dp/n3900 ) );
AO222X1 U770 ( .IN1(n1810), .IN2(n602), .IN3(n1809), .IN4(n1616), .IN5(n1812), .IN6(n185), .Q(n1764) );
AO222X1 U771 ( .IN1(n1813), .IN2(n80), .IN3(n1596), .IN4(n634), .IN5(n1594),
.IN6(n32), .Q(n1616) );
AO21X1 U772 ( .IN1(n1402), .IN2(n131), .IN3(n1765), .Q(
\fpu_add_frac_dp/n3899 ) );
AO222X1 U773 ( .IN1(n1810), .IN2(n186), .IN3(n1809), .IN4(n1618), .IN5(n1812), .IN6(n602), .Q(n1765) );
AO222X1 U774 ( .IN1(n1813), .IN2(n32), .IN3(n1596), .IN4(n274), .IN5(n1594),
.IN6(n81), .Q(n1618) );
AO21X1 U775 ( .IN1(n1402), .IN2(n934), .IN3(n1766), .Q(
\fpu_add_frac_dp/n3898 ) );
AO222X1 U776 ( .IN1(n1810), .IN2(n603), .IN3(n1809), .IN4(n1620), .IN5(n1812), .IN6(n186), .Q(n1766) );
AO222X1 U777 ( .IN1(n1813), .IN2(n81), .IN3(n1596), .IN4(n635), .IN5(n1594),
.IN6(n39), .Q(n1620) );
AO21X1 U778 ( .IN1(n1402), .IN2(n931), .IN3(n1767), .Q(
\fpu_add_frac_dp/n3897 ) );
AO222X1 U779 ( .IN1(n1810), .IN2(n187), .IN3(n1809), .IN4(n1622), .IN5(n1812), .IN6(n603), .Q(n1767) );
AO222X1 U780 ( .IN1(n1813), .IN2(n39), .IN3(n1596), .IN4(n275), .IN5(n1594),
.IN6(n120), .Q(n1622) );
AO21X1 U781 ( .IN1(n1402), .IN2(n929), .IN3(n1768), .Q(
\fpu_add_frac_dp/n3896 ) );
AO222X1 U782 ( .IN1(n1810), .IN2(n604), .IN3(n1809), .IN4(n1624), .IN5(n1812), .IN6(n187), .Q(n1768) );
AO222X1 U783 ( .IN1(n1813), .IN2(n120), .IN3(n1596), .IN4(n636), .IN5(n1594),
.IN6(n52), .Q(n1624) );
AO21X1 U784 ( .IN1(n1402), .IN2(n932), .IN3(n1769), .Q(
\fpu_add_frac_dp/n3895 ) );
AO222X1 U785 ( .IN1(n1810), .IN2(n188), .IN3(n1809), .IN4(n1626), .IN5(n1812), .IN6(n604), .Q(n1769) );
AO222X1 U786 ( .IN1(n1813), .IN2(n52), .IN3(n1596), .IN4(n276), .IN5(n1594),
.IN6(n121), .Q(n1626) );
AO21X1 U787 ( .IN1(n1402), .IN2(n312), .IN3(n1770), .Q(
\fpu_add_frac_dp/n3894 ) );
AO222X1 U788 ( .IN1(n1810), .IN2(n605), .IN3(n1809), .IN4(n1628), .IN5(n1812), .IN6(n188), .Q(n1770) );
AO222X1 U789 ( .IN1(n1813), .IN2(n121), .IN3(n1596), .IN4(n637), .IN5(n1594),
.IN6(n53), .Q(n1628) );
AO21X1 U790 ( .IN1(n1402), .IN2(n720), .IN3(n1771), .Q(
\fpu_add_frac_dp/n3893 ) );
AO222X1 U791 ( .IN1(n1810), .IN2(n189), .IN3(n1809), .IN4(n1630), .IN5(n1812), .IN6(n605), .Q(n1771) );
AO222X1 U792 ( .IN1(n1813), .IN2(n53), .IN3(n1596), .IN4(n277), .IN5(n1594),
.IN6(n122), .Q(n1630) );
AO21X1 U793 ( .IN1(n1402), .IN2(n106), .IN3(n1772), .Q(
\fpu_add_frac_dp/n3892 ) );
AO222X1 U794 ( .IN1(n1810), .IN2(n606), .IN3(n1809), .IN4(n1632), .IN5(n1812), .IN6(n189), .Q(n1772) );
AO222X1 U795 ( .IN1(n1813), .IN2(n122), .IN3(n1596), .IN4(n639), .IN5(n1594),
.IN6(n272), .Q(n1632) );
AO21X1 U796 ( .IN1(n1402), .IN2(n679), .IN3(n1773), .Q(
\fpu_add_frac_dp/n3891 ) );
AO222X1 U797 ( .IN1(n1810), .IN2(n190), .IN3(n1809), .IN4(n1634), .IN5(n1812), .IN6(n606), .Q(n1773) );
AO222X1 U798 ( .IN1(n1813), .IN2(n272), .IN3(n1596), .IN4(n112), .IN5(n1594),
.IN6(n633), .Q(n1634) );
AO21X1 U799 ( .IN1(n1402), .IN2(n678), .IN3(n1774), .Q(
\fpu_add_frac_dp/n3890 ) );
AO222X1 U800 ( .IN1(n1810), .IN2(n607), .IN3(n1809), .IN4(n1636), .IN5(n1812), .IN6(n190), .Q(n1774) );
AO222X1 U801 ( .IN1(n1813), .IN2(n633), .IN3(n1596), .IN4(n113), .IN5(n1594),
.IN6(n273), .Q(n1636) );
AO21X1 U802 ( .IN1(n1402), .IN2(n696), .IN3(n1775), .Q(
\fpu_add_frac_dp/n3889 ) );
AO222X1 U803 ( .IN1(n1810), .IN2(n191), .IN3(n1809), .IN4(n1638), .IN5(n1812), .IN6(n607), .Q(n1775) );
AO222X1 U804 ( .IN1(n1813), .IN2(n273), .IN3(n1596), .IN4(n114), .IN5(n1594),
.IN6(n634), .Q(n1638) );
AO21X1 U805 ( .IN1(n1401), .IN2(n218), .IN3(n1776), .Q(
\fpu_add_frac_dp/n3888 ) );
AO222X1 U806 ( .IN1(n1810), .IN2(n608), .IN3(n1809), .IN4(n1640), .IN5(n1812), .IN6(n191), .Q(n1776) );
AO222X1 U807 ( .IN1(n1813), .IN2(n634), .IN3(n1596), .IN4(n7), .IN5(n1594),
.IN6(n274), .Q(n1640) );
AO21X1 U808 ( .IN1(n1399), .IN2(n278), .IN3(n1777), .Q(
\fpu_add_frac_dp/n3887 ) );
AO222X1 U809 ( .IN1(n1810), .IN2(n192), .IN3(n1809), .IN4(n1642), .IN5(n1812), .IN6(n608), .Q(n1777) );
AO222X1 U810 ( .IN1(n1813), .IN2(n274), .IN3(n1596), .IN4(n8), .IN5(n1594),
.IN6(n635), .Q(n1642) );
AO21X1 U811 ( .IN1(\fpu_add_frac_dp/n2393 ), .IN2(n1415), .IN3(n1778), .Q(
\fpu_add_frac_dp/n3886 ) );
AO222X1 U812 ( .IN1(n1810), .IN2(n609), .IN3(n1809), .IN4(n1644), .IN5(n1812), .IN6(n192), .Q(n1778) );
AO222X1 U813 ( .IN1(n1813), .IN2(n635), .IN3(n1596), .IN4(n9), .IN5(n1594),
.IN6(n275), .Q(n1644) );
AO21X1 U814 ( .IN1(n1401), .IN2(n205), .IN3(n1779), .Q(
\fpu_add_frac_dp/n3885 ) );
AO222X1 U815 ( .IN1(n1810), .IN2(n193), .IN3(n1809), .IN4(n1646), .IN5(n1812), .IN6(n609), .Q(n1779) );
AO222X1 U816 ( .IN1(n1813), .IN2(n275), .IN3(n1596), .IN4(n24), .IN5(n1594),
.IN6(n636), .Q(n1646) );
AO21X1 U817 ( .IN1(n1401), .IN2(n6), .IN3(n1780), .Q(\fpu_add_frac_dp/n3884 ) );
AO222X1 U818 ( .IN1(n1810), .IN2(n610), .IN3(n1809), .IN4(n1648), .IN5(n1812), .IN6(n193), .Q(n1780) );
AO222X1 U819 ( .IN1(n1813), .IN2(n636), .IN3(n1596), .IN4(n25), .IN5(n1594),
.IN6(n276), .Q(n1648) );
AO21X1 U820 ( .IN1(n1401), .IN2(n162), .IN3(n1781), .Q(
\fpu_add_frac_dp/n3883 ) );
AO222X1 U821 ( .IN1(n1810), .IN2(n194), .IN3(n1809), .IN4(n1650), .IN5(n1812), .IN6(n610), .Q(n1781) );
AO222X1 U822 ( .IN1(n1813), .IN2(n276), .IN3(n1596), .IN4(n26), .IN5(n1594),
.IN6(n637), .Q(n1650) );
AO21X1 U823 ( .IN1(n1401), .IN2(n23), .IN3(n1782), .Q(
\fpu_add_frac_dp/n3882 ) );
AO222X1 U824 ( .IN1(n1810), .IN2(n611), .IN3(n1809), .IN4(n1652), .IN5(n1812), .IN6(n194), .Q(n1782) );
AO222X1 U825 ( .IN1(n1813), .IN2(n637), .IN3(n1596), .IN4(n76), .IN5(n1594),
.IN6(n277), .Q(n1652) );
AO21X1 U826 ( .IN1(n1401), .IN2(n271), .IN3(n1783), .Q(
\fpu_add_frac_dp/n3881 ) );
AO222X1 U827 ( .IN1(n1810), .IN2(n207), .IN3(n1809), .IN4(n1654), .IN5(n1812), .IN6(n611), .Q(n1783) );
AO222X1 U828 ( .IN1(n1813), .IN2(n277), .IN3(n1596), .IN4(n77), .IN5(n1594),
.IN6(n639), .Q(n1654) );
AO21X1 U829 ( .IN1(n1401), .IN2(n168), .IN3(n1784), .Q(
\fpu_add_frac_dp/n3880 ) );
AO221X1 U830 ( .IN1(n1810), .IN2(n644), .IN3(n1812), .IN4(n207), .IN5(n1814),
.Q(n1784) );
AO22X1 U831 ( .IN1(n1809), .IN2(n1664), .IN3(n1815), .IN4(n1816), .Q(n1814)
);
NOR2X0 U832 ( .IN1(\fpu_add_frac_dp/n965 ), .IN2(n1817), .QN(n1815) );
AO221X1 U833 ( .IN1(n1818), .IN2(n7), .IN3(n1594), .IN4(n112), .IN5(n1819),
.Q(n1664) );
AO22X1 U834 ( .IN1(n1813), .IN2(n639), .IN3(n1596), .IN4(n167), .Q(n1819) );
AND2X1 U835 ( .IN1(n1816), .IN2(n1667), .Q(n1812) );
AND2X1 U836 ( .IN1(n1816), .IN2(n1820), .Q(n1810) );
AO21X1 U837 ( .IN1(\fpu_add_frac_dp/n2380 ), .IN2(n1415), .IN3(n1785), .Q(
\fpu_add_frac_dp/n3879 ) );
AO22X1 U838 ( .IN1(n1809), .IN2(n1670), .IN3(n1816), .IN4(n1672), .Q(n1785)
);
AO221X1 U839 ( .IN1(n1669), .IN2(n208), .IN3(n1820), .IN4(n698), .IN5(n1821),
.Q(n1672) );
AO22X1 U840 ( .IN1(n1667), .IN2(n644), .IN3(n1822), .IN4(n176), .Q(n1821) );
AO221X1 U841 ( .IN1(n1818), .IN2(n8), .IN3(n1594), .IN4(n113), .IN5(n1823),
.Q(n1670) );
AO222X1 U842 ( .IN1(n1824), .IN2(n7), .IN3(n1596), .IN4(n27), .IN5(n1813),
.IN6(n112), .Q(n1823) );
AO21X1 U843 ( .IN1(n1401), .IN2(n70), .IN3(n1786), .Q(
\fpu_add_frac_dp/n3878 ) );
AO22X1 U844 ( .IN1(n1809), .IN2(n1674), .IN3(n1816), .IN4(n1676), .Q(n1786)
);
AO221X1 U845 ( .IN1(n1669), .IN2(n99), .IN3(n1820), .IN4(n699), .IN5(n1825),
.Q(n1676) );
AO22X1 U846 ( .IN1(n1667), .IN2(n698), .IN3(n1822), .IN4(n208), .Q(n1825) );
AO221X1 U847 ( .IN1(n1818), .IN2(n9), .IN3(n1594), .IN4(n114), .IN5(n1826),
.Q(n1674) );
AO222X1 U848 ( .IN1(n1824), .IN2(n8), .IN3(n1596), .IN4(n28), .IN5(n1813),
.IN6(n113), .Q(n1826) );
AO21X1 U849 ( .IN1(n1401), .IN2(n174), .IN3(n1787), .Q(
\fpu_add_frac_dp/n3877 ) );
AO22X1 U850 ( .IN1(n1809), .IN2(n1677), .IN3(n1816), .IN4(n1679), .Q(n1787)
);
AO221X1 U851 ( .IN1(n1669), .IN2(n614), .IN3(n1820), .IN4(n176), .IN5(n1827),
.Q(n1679) );
AO22X1 U852 ( .IN1(n1667), .IN2(n699), .IN3(n1822), .IN4(n99), .Q(n1827) );
AO221X1 U853 ( .IN1(n1818), .IN2(n24), .IN3(n1594), .IN4(n7), .IN5(n1828),
.Q(n1677) );
AO222X1 U854 ( .IN1(n1824), .IN2(n9), .IN3(n1596), .IN4(n29), .IN5(n1813),
.IN6(n114), .Q(n1828) );
AO21X1 U855 ( .IN1(n1401), .IN2(n638), .IN3(n1788), .Q(
\fpu_add_frac_dp/n3876 ) );
AO22X1 U856 ( .IN1(n1809), .IN2(n1680), .IN3(n1816), .IN4(n1682), .Q(n1788)
);
AO221X1 U857 ( .IN1(n1669), .IN2(n615), .IN3(n1820), .IN4(n208), .IN5(n1829),
.Q(n1682) );
AO22X1 U858 ( .IN1(n1667), .IN2(n176), .IN3(n1822), .IN4(n614), .Q(n1829) );
AO221X1 U859 ( .IN1(n1818), .IN2(n25), .IN3(n1594), .IN4(n8), .IN5(n1830),
.Q(n1680) );
AO222X1 U860 ( .IN1(n1824), .IN2(n24), .IN3(n1596), .IN4(n163), .IN5(n1813),
.IN6(n7), .Q(n1830) );
AO21X1 U861 ( .IN1(n1401), .IN2(n281), .IN3(n1789), .Q(
\fpu_add_frac_dp/n3875 ) );
AO22X1 U862 ( .IN1(n1809), .IN2(n1683), .IN3(n1816), .IN4(n1685), .Q(n1789)
);
AO221X1 U863 ( .IN1(n1669), .IN2(n209), .IN3(n1820), .IN4(n99), .IN5(n1831),
.Q(n1685) );
AO22X1 U864 ( .IN1(n1667), .IN2(n208), .IN3(n1822), .IN4(n615), .Q(n1831) );
AO221X1 U865 ( .IN1(n1818), .IN2(n26), .IN3(n1594), .IN4(n9), .IN5(n1832),
.Q(n1683) );
AO222X1 U866 ( .IN1(n1824), .IN2(n25), .IN3(n1596), .IN4(n164), .IN5(n1813),
.IN6(n8), .Q(n1832) );
AO21X1 U867 ( .IN1(n1401), .IN2(n280), .IN3(n1790), .Q(
\fpu_add_frac_dp/n3874 ) );
AO22X1 U868 ( .IN1(n1809), .IN2(n1686), .IN3(n1816), .IN4(n1688), .Q(n1790)
);
AO221X1 U869 ( .IN1(n1669), .IN2(n210), .IN3(n1820), .IN4(n614), .IN5(n1833),
.Q(n1688) );
AO22X1 U870 ( .IN1(n1667), .IN2(n99), .IN3(n1822), .IN4(n209), .Q(n1833) );
AO221X1 U871 ( .IN1(n1818), .IN2(n76), .IN3(n1594), .IN4(n24), .IN5(n1834),
.Q(n1686) );
AO222X1 U872 ( .IN1(n1824), .IN2(n26), .IN3(n1596), .IN4(n587), .IN5(n1813),
.IN6(n9), .Q(n1834) );
AO21X1 U873 ( .IN1(n1401), .IN2(n217), .IN3(n1791), .Q(
\fpu_add_frac_dp/n3873 ) );
AO22X1 U874 ( .IN1(n1809), .IN2(n1689), .IN3(n1816), .IN4(n1691), .Q(n1791)
);
AO221X1 U875 ( .IN1(n1669), .IN2(n211), .IN3(n1820), .IN4(n615), .IN5(n1835),
.Q(n1691) );
AO22X1 U876 ( .IN1(n1667), .IN2(n614), .IN3(n1822), .IN4(n210), .Q(n1835) );
AO221X1 U877 ( .IN1(n1818), .IN2(n77), .IN3(n1594), .IN4(n25), .IN5(n1836),
.Q(n1689) );
AO222X1 U878 ( .IN1(n1824), .IN2(n76), .IN3(n1596), .IN4(n588), .IN5(n1813),
.IN6(n24), .Q(n1836) );
AO21X1 U879 ( .IN1(n1401), .IN2(n96), .IN3(n1792), .Q(
\fpu_add_frac_dp/n3872 ) );
AO22X1 U880 ( .IN1(n1809), .IN2(n1692), .IN3(n1816), .IN4(n1694), .Q(n1792)
);
AO221X1 U881 ( .IN1(n1669), .IN2(n616), .IN3(n1820), .IN4(n209), .IN5(n1837),
.Q(n1694) );
AO22X1 U882 ( .IN1(n1667), .IN2(n615), .IN3(n1822), .IN4(n211), .Q(n1837) );
AO221X1 U883 ( .IN1(n1818), .IN2(n167), .IN3(n1594), .IN4(n26), .IN5(n1838),
.Q(n1692) );
AO222X1 U884 ( .IN1(n1824), .IN2(n77), .IN3(n1596), .IN4(n589), .IN5(n1813),
.IN6(n25), .Q(n1838) );
AO21X1 U885 ( .IN1(n1400), .IN2(n631), .IN3(n1793), .Q(
\fpu_add_frac_dp/n3871 ) );
AO22X1 U886 ( .IN1(n1809), .IN2(n1695), .IN3(n1816), .IN4(n1697), .Q(n1793)
);
AO221X1 U887 ( .IN1(n1669), .IN2(n617), .IN3(n1820), .IN4(n210), .IN5(n1839),
.Q(n1697) );
AO22X1 U888 ( .IN1(n1667), .IN2(n209), .IN3(n1822), .IN4(n616), .Q(n1839) );
AO221X1 U889 ( .IN1(n1818), .IN2(n27), .IN3(n1594), .IN4(n76), .IN5(n1840),
.Q(n1695) );
AO222X1 U890 ( .IN1(n1824), .IN2(n167), .IN3(n1596), .IN4(n78), .IN5(n1813),
.IN6(n26), .Q(n1840) );
AO21X1 U891 ( .IN1(n1400), .IN2(n630), .IN3(n1794), .Q(
\fpu_add_frac_dp/n3870 ) );
AO22X1 U892 ( .IN1(n1809), .IN2(n1698), .IN3(n1816), .IN4(n1700), .Q(n1794)
);
AO221X1 U893 ( .IN1(n1669), .IN2(n618), .IN3(n1820), .IN4(n211), .IN5(n1841),
.Q(n1700) );
AO22X1 U894 ( .IN1(n1667), .IN2(n210), .IN3(n1822), .IN4(n617), .Q(n1841) );
AO221X1 U895 ( .IN1(n1818), .IN2(n28), .IN3(n1594), .IN4(n77), .IN5(n1842),
.Q(n1698) );
AO222X1 U896 ( .IN1(n1824), .IN2(n27), .IN3(n1596), .IN4(n165), .IN5(n1813),
.IN6(n76), .Q(n1842) );
AO21X1 U897 ( .IN1(n1400), .IN2(n632), .IN3(n1795), .Q(
\fpu_add_frac_dp/n3869 ) );
AO22X1 U898 ( .IN1(n1809), .IN2(n1701), .IN3(n1816), .IN4(n1703), .Q(n1795)
);
AO221X1 U899 ( .IN1(n1669), .IN2(n212), .IN3(n1820), .IN4(n616), .IN5(n1843),
.Q(n1703) );
AO22X1 U900 ( .IN1(n1667), .IN2(n211), .IN3(n1822), .IN4(n618), .Q(n1843) );
AO221X1 U901 ( .IN1(n1818), .IN2(n29), .IN3(n1594), .IN4(n167), .IN5(n1844),
.Q(n1701) );
AO222X1 U902 ( .IN1(n1824), .IN2(n28), .IN3(n1596), .IN4(n169), .IN5(n1813),
.IN6(n77), .Q(n1844) );
AO21X1 U903 ( .IN1(n1400), .IN2(n95), .IN3(n1796), .Q(
\fpu_add_frac_dp/n3868 ) );
AO22X1 U904 ( .IN1(n1809), .IN2(n1704), .IN3(n1816), .IN4(n1706), .Q(n1796)
);
AO221X1 U905 ( .IN1(n1669), .IN2(n213), .IN3(n1820), .IN4(n617), .IN5(n1845),
.Q(n1706) );
AO22X1 U906 ( .IN1(n1667), .IN2(n616), .IN3(n1822), .IN4(n212), .Q(n1845) );
AO221X1 U907 ( .IN1(n1818), .IN2(n163), .IN3(n1594), .IN4(n27), .IN5(n1846),
.Q(n1704) );
AO222X1 U908 ( .IN1(n1824), .IN2(n29), .IN3(n1596), .IN4(n591), .IN5(n1813),
.IN6(n167), .Q(n1846) );
AO21X1 U909 ( .IN1(n1400), .IN2(n613), .IN3(n1797), .Q(
\fpu_add_frac_dp/n3867 ) );
AO22X1 U910 ( .IN1(n1809), .IN2(n1707), .IN3(n1816), .IN4(n1709), .Q(n1797)
);
AO221X1 U911 ( .IN1(n1669), .IN2(n214), .IN3(n1820), .IN4(n618), .IN5(n1847),
.Q(n1709) );
AO22X1 U912 ( .IN1(n1667), .IN2(n617), .IN3(n1822), .IN4(n213), .Q(n1847) );
AO221X1 U913 ( .IN1(n1818), .IN2(n164), .IN3(n1594), .IN4(n28), .IN5(n1848),
.Q(n1707) );
AO222X1 U914 ( .IN1(n1824), .IN2(n163), .IN3(n1596), .IN4(n592), .IN5(n1813),
.IN6(n27), .Q(n1848) );
AO21X1 U915 ( .IN1(n1404), .IN2(n97), .IN3(n1798), .Q(
\fpu_add_frac_dp/n3866 ) );
AO22X1 U916 ( .IN1(n1809), .IN2(n1710), .IN3(n1816), .IN4(n1712), .Q(n1798)
);
AO221X1 U917 ( .IN1(n1669), .IN2(n619), .IN3(n1820), .IN4(n212), .IN5(n1849),
.Q(n1712) );
AO22X1 U918 ( .IN1(n1667), .IN2(n618), .IN3(n1822), .IN4(n214), .Q(n1849) );
AO221X1 U919 ( .IN1(n1818), .IN2(n587), .IN3(n1594), .IN4(n29), .IN5(n1850),
.Q(n1710) );
AO222X1 U920 ( .IN1(n1824), .IN2(n164), .IN3(n1596), .IN4(n593), .IN5(n1813),
.IN6(n28), .Q(n1850) );
AO21X1 U921 ( .IN1(n1400), .IN2(n98), .IN3(n1799), .Q(
\fpu_add_frac_dp/n3865 ) );
AO22X1 U922 ( .IN1(n1809), .IN2(n1713), .IN3(n1816), .IN4(n1715), .Q(n1799)
);
AO221X1 U923 ( .IN1(n1669), .IN2(n620), .IN3(n1820), .IN4(n213), .IN5(n1851),
.Q(n1715) );
AO22X1 U924 ( .IN1(n1667), .IN2(n212), .IN3(n1822), .IN4(n619), .Q(n1851) );
AO221X1 U925 ( .IN1(n1818), .IN2(n588), .IN3(n1594), .IN4(n163), .IN5(n1852),
.Q(n1713) );
AO222X1 U926 ( .IN1(n1824), .IN2(n587), .IN3(n1596), .IN4(
\fpu_add_frac_dp/n2446 ), .IN5(n1813), .IN6(n29), .Q(n1852) );
AO21X1 U927 ( .IN1(n1400), .IN2(n4), .IN3(n1800), .Q(\fpu_add_frac_dp/n3864 ) );
AO22X1 U928 ( .IN1(n1809), .IN2(n1716), .IN3(n1816), .IN4(n1718), .Q(n1800)
);
AO221X1 U929 ( .IN1(n1669), .IN2(n621), .IN3(n1820), .IN4(n214), .IN5(n1853),
.Q(n1718) );
AO22X1 U930 ( .IN1(n1667), .IN2(n213), .IN3(n1822), .IN4(n620), .Q(n1853) );
AO221X1 U931 ( .IN1(n1818), .IN2(n589), .IN3(n1594), .IN4(n164), .IN5(n1854),
.Q(n1716) );
AO222X1 U932 ( .IN1(n1824), .IN2(n588), .IN3(n1596), .IN4(
\fpu_add_frac_dp/n2473 ), .IN5(n1813), .IN6(n163), .Q(n1854) );
AO21X1 U933 ( .IN1(n1397), .IN2(n157), .IN3(n1801), .Q(
\fpu_add_frac_dp/n3863 ) );
AO22X1 U934 ( .IN1(n1809), .IN2(n1719), .IN3(n1816), .IN4(n1721), .Q(n1801)
);
AO221X1 U935 ( .IN1(n1669), .IN2(n215), .IN3(n1820), .IN4(n619), .IN5(n1855),
.Q(n1721) );
AO22X1 U936 ( .IN1(n1667), .IN2(n214), .IN3(n1822), .IN4(n621), .Q(n1855) );
AO221X1 U937 ( .IN1(n1818), .IN2(n78), .IN3(n1594), .IN4(n587), .IN5(n1856),
.Q(n1719) );
AO222X1 U938 ( .IN1(n1824), .IN2(n589), .IN3(n1596), .IN4(
\fpu_add_frac_dp/n2466 ), .IN5(n1813), .IN6(n164), .Q(n1856) );
AO21X1 U939 ( .IN1(n1397), .IN2(n1857), .IN3(n1802), .Q(
\fpu_add_frac_dp/n3862 ) );
AO22X1 U940 ( .IN1(n1809), .IN2(n1722), .IN3(n1816), .IN4(n1724), .Q(n1802)
);
AO221X1 U941 ( .IN1(n1669), .IN2(n216), .IN3(n1820), .IN4(n620), .IN5(n1858),
.Q(n1724) );
AO22X1 U942 ( .IN1(n1667), .IN2(n619), .IN3(n1822), .IN4(n215), .Q(n1858) );
AO221X1 U943 ( .IN1(n1818), .IN2(n165), .IN3(n1594), .IN4(n588), .IN5(n1859),
.Q(n1722) );
AO222X1 U944 ( .IN1(n1824), .IN2(n78), .IN3(n1596), .IN4(
\fpu_add_frac_dp/n2474 ), .IN5(n1813), .IN6(n587), .Q(n1859) );
AO21X1 U945 ( .IN1(n1397), .IN2(n68), .IN3(n1803), .Q(
\fpu_add_frac_dp/n3861 ) );
AO22X1 U946 ( .IN1(n1809), .IN2(n1725), .IN3(n1816), .IN4(n1727), .Q(n1803)
);
AO221X1 U947 ( .IN1(n1669), .IN2(n206), .IN3(n1820), .IN4(n621), .IN5(n1860),
.Q(n1727) );
AO22X1 U948 ( .IN1(n1667), .IN2(n620), .IN3(n1822), .IN4(n216), .Q(n1860) );
AO221X1 U949 ( .IN1(n1818), .IN2(n169), .IN3(n1594), .IN4(n589), .IN5(n1861),
.Q(n1725) );
AO222X1 U950 ( .IN1(n1824), .IN2(n165), .IN3(n1596), .IN4(
\fpu_add_frac_dp/n2467 ), .IN5(n1813), .IN6(n588), .Q(n1861) );
AO21X1 U951 ( .IN1(n1397), .IN2(n156), .IN3(n1804), .Q(
\fpu_add_frac_dp/n3860 ) );
AO22X1 U952 ( .IN1(n1809), .IN2(n1728), .IN3(n1816), .IN4(n1730), .Q(n1804)
);
AO221X1 U953 ( .IN1(n1669), .IN2(n688), .IN3(n1820), .IN4(n215), .IN5(n1862),
.Q(n1730) );
AO22X1 U954 ( .IN1(n1667), .IN2(n621), .IN3(n1822), .IN4(n206), .Q(n1862) );
AO221X1 U955 ( .IN1(n1818), .IN2(n591), .IN3(n1594), .IN4(n78), .IN5(n1863),
.Q(n1728) );
AO222X1 U956 ( .IN1(n1824), .IN2(n169), .IN3(n1596), .IN4(
\fpu_add_frac_dp/n2475 ), .IN5(n1813), .IN6(n589), .Q(n1863) );
AO21X1 U957 ( .IN1(n1397), .IN2(n3), .IN3(n1805), .Q(\fpu_add_frac_dp/n3859 ) );
AO22X1 U958 ( .IN1(n1809), .IN2(n1731), .IN3(n1816), .IN4(n1733), .Q(n1805)
);
AO221X1 U959 ( .IN1(n1669), .IN2(n689), .IN3(n1820), .IN4(n216), .IN5(n1864),
.Q(n1733) );
AO22X1 U960 ( .IN1(n1667), .IN2(n215), .IN3(n1822), .IN4(n688), .Q(n1864) );
AO221X1 U961 ( .IN1(n1818), .IN2(n592), .IN3(n1594), .IN4(n165), .IN5(n1865),
.Q(n1731) );
AO222X1 U962 ( .IN1(n1824), .IN2(n591), .IN3(n1596), .IN4(
\fpu_add_frac_dp/n2468 ), .IN5(n1813), .IN6(n78), .Q(n1865) );
AO21X1 U963 ( .IN1(n1397), .IN2(n16), .IN3(n1806), .Q(
\fpu_add_frac_dp/n3858 ) );
AO22X1 U964 ( .IN1(n1816), .IN2(n1738), .IN3(n1809), .IN4(n1866), .Q(n1806)
);
AO21X1 U965 ( .IN1(n1751), .IN2(n1867), .IN3(n1734), .Q(n1866) );
AO221X1 U966 ( .IN1(n1818), .IN2(n593), .IN3(n1594), .IN4(n169), .IN5(n1868),
.Q(n1734) );
AO222X1 U967 ( .IN1(n1824), .IN2(n592), .IN3(n1596), .IN4(
\fpu_add_frac_dp/n2469 ), .IN5(n1813), .IN6(n165), .Q(n1868) );
INVX0 U968 ( .INP(n1869), .ZN(n1818) );
AO221X1 U969 ( .IN1(n1669), .IN2(n705), .IN3(n1820), .IN4(n206), .IN5(n1870),
.Q(n1738) );
AO22X1 U970 ( .IN1(n1667), .IN2(n216), .IN3(n1822), .IN4(n689), .Q(n1870) );
INVX0 U971 ( .INP(n1665), .ZN(n1820) );
INVX0 U972 ( .INP(n1817), .ZN(n1669) );
AO21X1 U973 ( .IN1(n1397), .IN2(n15), .IN3(n1807), .Q(
\fpu_add_frac_dp/n3857 ) );
AO22X1 U974 ( .IN1(n1816), .IN2(n1743), .IN3(n1809), .IN4(n1742), .Q(n1807)
);
NAND4X0 U975 ( .IN1(n1869), .IN2(n1811), .IN3(n1871), .IN4(n1872), .QN(n1742) );
AOI22X1 U976 ( .IN1(n593), .IN2(n1824), .IN3(n169), .IN4(n1813), .QN(n1872)
);
NOR2X0 U977 ( .IN1(\fpu_add_ctl/n117 ), .IN2(\fpu_add_ctl/n327 ), .QN(n1813)
);
NOR2X0 U978 ( .IN1(\fpu_add_ctl/n117 ), .IN2(\fpu_add_ctl/n328 ), .QN(n1824)
);
NAND2X0 U979 ( .IN1(n1596), .IN2(n1080), .QN(n1871) );
NAND2X0 U980 ( .IN1(\fpu_add_ctl/n117 ), .IN2(n700), .QN(n1811) );
NAND2X0 U981 ( .IN1(\fpu_add_ctl/n117 ), .IN2(n701), .QN(n1869) );
AOI21X1 U982 ( .IN1(n1737), .IN2(n1873), .IN3(n1745), .QN(n1809) );
NAND2X0 U983 ( .IN1(n1874), .IN2(n1875), .QN(n1873) );
INVX0 U984 ( .INP(n1748), .ZN(n1875) );
NAND3X0 U985 ( .IN1(n1817), .IN2(n1665), .IN3(n1876), .QN(n1743) );
AOI22X1 U986 ( .IN1(n705), .IN2(n1822), .IN3(n206), .IN4(n1667), .QN(n1876)
);
NOR2X0 U987 ( .IN1(\fpu_add_ctl/n122 ), .IN2(\fpu_add_ctl/n327 ), .QN(n1667)
);
NOR2X0 U988 ( .IN1(\fpu_add_ctl/n122 ), .IN2(\fpu_add_ctl/n328 ), .QN(n1822)
);
NAND2X0 U989 ( .IN1(\fpu_add_ctl/n122 ), .IN2(n700), .QN(n1665) );
NAND2X0 U990 ( .IN1(\fpu_add_ctl/n122 ), .IN2(n701), .QN(n1817) );
AND3X1 U991 ( .IN1(n1449), .IN2(n1748), .IN3(n1874), .Q(n1816) );
NOR2X0 U992 ( .IN1(n1867), .IN2(n1877), .QN(n1874) );
AO222X1 U993 ( .IN1(\fpu_add_exp_dp/n45 ), .IN2(n1878), .IN3(
\fpu_add_exp_dp/n47 ), .IN4(n1879), .IN5(n1880), .IN6(n1881), .Q(n1748) );
NAND2X0 U994 ( .IN1(n961), .IN2(n1882), .QN(n1879) );
INVX0 U995 ( .INP(n1882), .ZN(n1878) );
AO22X1 U996 ( .IN1(n1883), .IN2(n445), .IN3(n1884), .IN4(n1000), .Q(n1882)
);
OR2X1 U997 ( .IN1(n445), .IN2(n1883), .Q(n1884) );
AO22X1 U998 ( .IN1(n1885), .IN2(n446), .IN3(n1886), .IN4(n999), .Q(n1883) );
OR2X1 U999 ( .IN1(n446), .IN2(n1885), .Q(n1886) );
AO22X1 U1000 ( .IN1(n1887), .IN2(n323), .IN3(n1888), .IN4(n998), .Q(n1885)
);
OR2X1 U1001 ( .IN1(n323), .IN2(n1887), .Q(n1888) );
AO22X1 U1002 ( .IN1(n1889), .IN2(n322), .IN3(n1890), .IN4(n997), .Q(n1887)
);
OR2X1 U1003 ( .IN1(n322), .IN2(n1889), .Q(n1890) );
AO22X1 U1004 ( .IN1(n1891), .IN2(n321), .IN3(n1892), .IN4(n996), .Q(n1889)
);
OR2X1 U1005 ( .IN1(n321), .IN2(n1891), .Q(n1892) );
AO22X1 U1006 ( .IN1(n1893), .IN2(n320), .IN3(n1894), .IN4(n995), .Q(n1891)
);
OR2X1 U1007 ( .IN1(n320), .IN2(n1893), .Q(n1894) );
AO22X1 U1008 ( .IN1(n1895), .IN2(n319), .IN3(n1896), .IN4(n994), .Q(n1893)
);
OR2X1 U1009 ( .IN1(n319), .IN2(n1895), .Q(n1896) );
AO22X1 U1010 ( .IN1(n1897), .IN2(n309), .IN3(n1898), .IN4(n993), .Q(n1895)
);
OR2X1 U1011 ( .IN1(n309), .IN2(n1897), .Q(n1898) );
AO21X1 U1012 ( .IN1(n56), .IN2(n138), .IN3(n1899), .Q(n1897) );
OA22X1 U1013 ( .IN1(n56), .IN2(n138), .IN3(n491), .IN4(n992), .Q(n1899) );
AO22X1 U1014 ( .IN1(n1443), .IN2(n625), .IN3(n1409), .IN4(n465), .Q(
\fpu_add_frac_dp/n3856 ) );
AO22X1 U1015 ( .IN1(n1443), .IN2(n220), .IN3(n1409), .IN4(n828), .Q(
\fpu_add_frac_dp/n3855 ) );
AO22X1 U1016 ( .IN1(n1443), .IN2(n310), .IN3(n1410), .IN4(n827), .Q(
\fpu_add_frac_dp/n3854 ) );
AO22X1 U1017 ( .IN1(n1443), .IN2(n288), .IN3(n1409), .IN4(n826), .Q(
\fpu_add_frac_dp/n3853 ) );
AO22X1 U1018 ( .IN1(n1443), .IN2(n223), .IN3(n1409), .IN4(n825), .Q(
\fpu_add_frac_dp/n3852 ) );
AO22X1 U1019 ( .IN1(n1443), .IN2(n225), .IN3(n1409), .IN4(n824), .Q(
\fpu_add_frac_dp/n3851 ) );
AO22X1 U1020 ( .IN1(n1443), .IN2(n222), .IN3(n1409), .IN4(n823), .Q(
\fpu_add_frac_dp/n3850 ) );
AO22X1 U1021 ( .IN1(n1443), .IN2(n224), .IN3(n1409), .IN4(n822), .Q(
\fpu_add_frac_dp/n3849 ) );
AO22X1 U1022 ( .IN1(n1443), .IN2(n261), .IN3(n1409), .IN4(n821), .Q(
\fpu_add_frac_dp/n3848 ) );
AO22X1 U1023 ( .IN1(n1443), .IN2(n260), .IN3(n1409), .IN4(n820), .Q(
\fpu_add_frac_dp/n3847 ) );
AO22X1 U1024 ( .IN1(n1443), .IN2(n253), .IN3(n1409), .IN4(n819), .Q(
\fpu_add_frac_dp/n3846 ) );
AO22X1 U1025 ( .IN1(n1443), .IN2(n252), .IN3(n1409), .IN4(n818), .Q(
\fpu_add_frac_dp/n3845 ) );
AO22X1 U1026 ( .IN1(n1443), .IN2(n327), .IN3(n1408), .IN4(n817), .Q(
\fpu_add_frac_dp/n3844 ) );
AO22X1 U1027 ( .IN1(n1443), .IN2(n180), .IN3(n1408), .IN4(n816), .Q(
\fpu_add_frac_dp/n3843 ) );
AO22X1 U1028 ( .IN1(n1443), .IN2(n268), .IN3(n1409), .IN4(n815), .Q(
\fpu_add_frac_dp/n3842 ) );
AO22X1 U1029 ( .IN1(n1444), .IN2(n179), .IN3(n1408), .IN4(n814), .Q(
\fpu_add_frac_dp/n3841 ) );
AO22X1 U1030 ( .IN1(n1443), .IN2(n251), .IN3(n1408), .IN4(n813), .Q(
\fpu_add_frac_dp/n3840 ) );
AO22X1 U1031 ( .IN1(n1444), .IN2(n250), .IN3(n1409), .IN4(n812), .Q(
\fpu_add_frac_dp/n3839 ) );
AO22X1 U1032 ( .IN1(n1444), .IN2(n249), .IN3(n1409), .IN4(n811), .Q(
\fpu_add_frac_dp/n3838 ) );
AO22X1 U1033 ( .IN1(n1444), .IN2(n263), .IN3(n1408), .IN4(n810), .Q(
\fpu_add_frac_dp/n3837 ) );
AO22X1 U1034 ( .IN1(n1444), .IN2(n267), .IN3(n1408), .IN4(n809), .Q(
\fpu_add_frac_dp/n3836 ) );
AO22X1 U1035 ( .IN1(n1444), .IN2(n279), .IN3(n1408), .IN4(n808), .Q(
\fpu_add_frac_dp/n3835 ) );
AO22X1 U1036 ( .IN1(n1444), .IN2(n318), .IN3(n1408), .IN4(n807), .Q(
\fpu_add_frac_dp/n3834 ) );
AO22X1 U1037 ( .IN1(n1444), .IN2(n248), .IN3(n1408), .IN4(n806), .Q(
\fpu_add_frac_dp/n3833 ) );
AO22X1 U1038 ( .IN1(n1444), .IN2(n247), .IN3(n1408), .IN4(n805), .Q(
\fpu_add_frac_dp/n3832 ) );
AO22X1 U1039 ( .IN1(n1444), .IN2(n246), .IN3(n1408), .IN4(n804), .Q(
\fpu_add_frac_dp/n3831 ) );
AO22X1 U1040 ( .IN1(n1444), .IN2(n204), .IN3(n1410), .IN4(n803), .Q(
\fpu_add_frac_dp/n3830 ) );
AO22X1 U1041 ( .IN1(n1444), .IN2(n245), .IN3(n1407), .IN4(n802), .Q(
\fpu_add_frac_dp/n3829 ) );
AO22X1 U1042 ( .IN1(n1444), .IN2(n244), .IN3(n1407), .IN4(n801), .Q(
\fpu_add_frac_dp/n3828 ) );
AO22X1 U1043 ( .IN1(n1446), .IN2(n203), .IN3(n1408), .IN4(n800), .Q(
\fpu_add_frac_dp/n3827 ) );
AO22X1 U1044 ( .IN1(n1444), .IN2(n243), .IN3(n1407), .IN4(n799), .Q(
\fpu_add_frac_dp/n3826 ) );
AO22X1 U1045 ( .IN1(n1444), .IN2(n242), .IN3(n1407), .IN4(n798), .Q(
\fpu_add_frac_dp/n3825 ) );
AO22X1 U1046 ( .IN1(n1444), .IN2(n241), .IN3(n1407), .IN4(n797), .Q(
\fpu_add_frac_dp/n3824 ) );
AO22X1 U1047 ( .IN1(n1444), .IN2(n240), .IN3(n1407), .IN4(n796), .Q(
\fpu_add_frac_dp/n3823 ) );
AO22X1 U1048 ( .IN1(n1446), .IN2(n202), .IN3(n1407), .IN4(n795), .Q(
\fpu_add_frac_dp/n3822 ) );
AO22X1 U1049 ( .IN1(n1444), .IN2(n239), .IN3(n1408), .IN4(n794), .Q(
\fpu_add_frac_dp/n3821 ) );
AO22X1 U1050 ( .IN1(n1445), .IN2(n201), .IN3(n1407), .IN4(n793), .Q(
\fpu_add_frac_dp/n3820 ) );
AO22X1 U1051 ( .IN1(n1445), .IN2(n238), .IN3(n1407), .IN4(n792), .Q(
\fpu_add_frac_dp/n3819 ) );
AO22X1 U1052 ( .IN1(n1445), .IN2(n200), .IN3(n1407), .IN4(n791), .Q(
\fpu_add_frac_dp/n3818 ) );
AO22X1 U1053 ( .IN1(n1445), .IN2(n259), .IN3(n1408), .IN4(n790), .Q(
\fpu_add_frac_dp/n3817 ) );
AO22X1 U1054 ( .IN1(n1445), .IN2(n237), .IN3(n1406), .IN4(n789), .Q(
\fpu_add_frac_dp/n3816 ) );
AO22X1 U1055 ( .IN1(n1445), .IN2(n199), .IN3(n1407), .IN4(n788), .Q(
\fpu_add_frac_dp/n3815 ) );
AO22X1 U1056 ( .IN1(n1445), .IN2(n236), .IN3(n1406), .IN4(n787), .Q(
\fpu_add_frac_dp/n3814 ) );
AO22X1 U1057 ( .IN1(n1445), .IN2(n235), .IN3(n1406), .IN4(n786), .Q(
\fpu_add_frac_dp/n3813 ) );
AO22X1 U1058 ( .IN1(n1445), .IN2(n234), .IN3(n1407), .IN4(n785), .Q(
\fpu_add_frac_dp/n3812 ) );
AO22X1 U1059 ( .IN1(n1445), .IN2(n198), .IN3(n1406), .IN4(n784), .Q(
\fpu_add_frac_dp/n3811 ) );
AO22X1 U1060 ( .IN1(n1445), .IN2(n197), .IN3(n1406), .IN4(n783), .Q(
\fpu_add_frac_dp/n3810 ) );
AO22X1 U1061 ( .IN1(n1445), .IN2(n233), .IN3(n1407), .IN4(n782), .Q(
\fpu_add_frac_dp/n3809 ) );
AO22X1 U1062 ( .IN1(n1445), .IN2(n232), .IN3(n1406), .IN4(n781), .Q(
\fpu_add_frac_dp/n3808 ) );
AO22X1 U1063 ( .IN1(n1445), .IN2(n231), .IN3(n1406), .IN4(n780), .Q(
\fpu_add_frac_dp/n3807 ) );
AO22X1 U1064 ( .IN1(n1445), .IN2(n230), .IN3(n1407), .IN4(n779), .Q(
\fpu_add_frac_dp/n3806 ) );
AO22X1 U1065 ( .IN1(n1445), .IN2(n229), .IN3(n1406), .IN4(n778), .Q(
\fpu_add_frac_dp/n3805 ) );
AO22X1 U1066 ( .IN1(n1445), .IN2(n228), .IN3(n1406), .IN4(n777), .Q(
\fpu_add_frac_dp/n3804 ) );
AO22X1 U1067 ( .IN1(n1445), .IN2(n227), .IN3(n1406), .IN4(n776), .Q(
\fpu_add_frac_dp/n3803 ) );
AO22X1 U1068 ( .IN1(n1446), .IN2(n196), .IN3(n1414), .IN4(n775), .Q(
\fpu_add_frac_dp/n3802 ) );
AO22X1 U1069 ( .IN1(n1446), .IN2(n294), .IN3(n1406), .IN4(n774), .Q(
\fpu_add_frac_dp/n3801 ) );
AO22X1 U1070 ( .IN1(n1446), .IN2(n332), .IN3(n1410), .IN4(n773), .Q(
\fpu_add_frac_dp/n3800 ) );
AO22X1 U1071 ( .IN1(n1446), .IN2(n334), .IN3(n1414), .IN4(n772), .Q(
\fpu_add_frac_dp/n3799 ) );
AO22X1 U1072 ( .IN1(n1446), .IN2(n293), .IN3(n1414), .IN4(n771), .Q(
\fpu_add_frac_dp/n3798 ) );
AO22X1 U1073 ( .IN1(n1446), .IN2(n317), .IN3(n1414), .IN4(n770), .Q(
\fpu_add_frac_dp/n3797 ) );
AO22X1 U1074 ( .IN1(n1446), .IN2(n195), .IN3(n1415), .IN4(n769), .Q(
\fpu_add_frac_dp/n3796 ) );
AO22X1 U1075 ( .IN1(n1446), .IN2(n226), .IN3(n1415), .IN4(n768), .Q(
\fpu_add_frac_dp/n3795 ) );
AO22X1 U1076 ( .IN1(n1446), .IN2(n850), .IN3(n1415), .IN4(n453), .Q(
\fpu_add_frac_dp/n3794 ) );
AO22X1 U1077 ( .IN1(n1416), .IN2(n1274), .IN3(n1900), .IN4(n1901), .Q(
\fpu_add_frac_dp/n3792 ) );
AO22X1 U1078 ( .IN1(n1426), .IN2(n1081), .IN3(n1902), .IN4(n1900), .Q(
\fpu_add_frac_dp/n3791 ) );
AO22X1 U1079 ( .IN1(n1422), .IN2(n1250), .IN3(n1903), .IN4(n1904), .Q(
\fpu_add_frac_dp/n3790 ) );
AO22X1 U1080 ( .IN1(n1422), .IN2(n1275), .IN3(n1903), .IN4(n1905), .Q(
\fpu_add_frac_dp/n3789 ) );
NOR2X0 U1081 ( .IN1(\fpu_add_exp_dp/n146 ), .IN2(n1906), .QN(n1903) );
AO22X1 U1082 ( .IN1(n1423), .IN2(n1276), .IN3(n1904), .IN4(n1900), .Q(
\fpu_add_frac_dp/n3788 ) );
AO22X1 U1083 ( .IN1(n1423), .IN2(n1273), .IN3(n1905), .IN4(n1900), .Q(
\fpu_add_frac_dp/n3787 ) );
NOR2X0 U1084 ( .IN1(n73), .IN2(n1906), .QN(n1900) );
NAND2X0 U1085 ( .IN1(n1907), .IN2(n1908), .QN(n1906) );
AO22X1 U1086 ( .IN1(n1423), .IN2(n1251), .IN3(n1909), .IN4(n1910), .Q(
\fpu_add_frac_dp/n3786 ) );
AO22X1 U1087 ( .IN1(n1423), .IN2(n1277), .IN3(n1911), .IN4(n1910), .Q(
\fpu_add_frac_dp/n3785 ) );
AO22X1 U1088 ( .IN1(n1423), .IN2(n1266), .IN3(n1912), .IN4(n1910), .Q(
\fpu_add_frac_dp/n3784 ) );
AO22X1 U1089 ( .IN1(n1423), .IN2(n1247), .IN3(n1913), .IN4(n1910), .Q(
\fpu_add_frac_dp/n3783 ) );
AO22X1 U1090 ( .IN1(n1423), .IN2(n1278), .IN3(n1914), .IN4(n1910), .Q(
\fpu_add_frac_dp/n3782 ) );
AO22X1 U1091 ( .IN1(n1423), .IN2(n1279), .IN3(n1915), .IN4(n1910), .Q(
\fpu_add_frac_dp/n3781 ) );
AO22X1 U1092 ( .IN1(n1423), .IN2(n1280), .IN3(n1916), .IN4(n1910), .Q(
\fpu_add_frac_dp/n3780 ) );
AO22X1 U1093 ( .IN1(n1423), .IN2(n1281), .IN3(n1917), .IN4(n1910), .Q(
\fpu_add_frac_dp/n3779 ) );
AO22X1 U1094 ( .IN1(n1423), .IN2(n1252), .IN3(n1909), .IN4(n1908), .Q(
\fpu_add_frac_dp/n3778 ) );
AO22X1 U1095 ( .IN1(n1423), .IN2(n1282), .IN3(n1911), .IN4(n1908), .Q(
\fpu_add_frac_dp/n3777 ) );
AO22X1 U1096 ( .IN1(n1423), .IN2(n1283), .IN3(n1912), .IN4(n1908), .Q(
\fpu_add_frac_dp/n3776 ) );
AO22X1 U1097 ( .IN1(n1423), .IN2(n1267), .IN3(n1913), .IN4(n1908), .Q(
\fpu_add_frac_dp/n3775 ) );
AO22X1 U1098 ( .IN1(n1423), .IN2(n1253), .IN3(n1914), .IN4(n1908), .Q(
\fpu_add_frac_dp/n3774 ) );
AO22X1 U1099 ( .IN1(n1424), .IN2(n1284), .IN3(n1915), .IN4(n1908), .Q(
\fpu_add_frac_dp/n3773 ) );
AO22X1 U1100 ( .IN1(n1424), .IN2(n1268), .IN3(n1916), .IN4(n1908), .Q(
\fpu_add_frac_dp/n3772 ) );
AO22X1 U1101 ( .IN1(n1424), .IN2(n1269), .IN3(n1917), .IN4(n1908), .Q(
\fpu_add_frac_dp/n3771 ) );
NOR2X0 U1102 ( .IN1(n290), .IN2(\fpu_add_exp_dp/n142 ), .QN(n1908) );
AO22X1 U1103 ( .IN1(n1424), .IN2(n1254), .IN3(n1918), .IN4(n1901), .Q(
\fpu_add_frac_dp/n3770 ) );
AO22X1 U1104 ( .IN1(n1424), .IN2(n1285), .IN3(n1918), .IN4(n1902), .Q(
\fpu_add_frac_dp/n3769 ) );
AO22X1 U1105 ( .IN1(n1424), .IN2(n1243), .IN3(n1919), .IN4(n1901), .Q(
\fpu_add_frac_dp/n3768 ) );
AO22X1 U1106 ( .IN1(n1424), .IN2(n1255), .IN3(n1919), .IN4(n1902), .Q(
\fpu_add_frac_dp/n3767 ) );
AO22X1 U1107 ( .IN1(n1424), .IN2(n1286), .IN3(n1918), .IN4(n1904), .Q(
\fpu_add_frac_dp/n3766 ) );
AO22X1 U1108 ( .IN1(n1424), .IN2(n1256), .IN3(n1918), .IN4(n1905), .Q(
\fpu_add_frac_dp/n3765 ) );
AND3X1 U1109 ( .IN1(n1907), .IN2(n73), .IN3(n1920), .Q(n1918) );
AO22X1 U1110 ( .IN1(n1424), .IN2(n1287), .IN3(n1919), .IN4(n1904), .Q(
\fpu_add_frac_dp/n3764 ) );
AO22X1 U1111 ( .IN1(n1424), .IN2(n1288), .IN3(n1919), .IN4(n1905), .Q(
\fpu_add_frac_dp/n3763 ) );
AND3X1 U1112 ( .IN1(\fpu_add_exp_dp/n146 ), .IN2(n1907), .IN3(n1920), .Q(
n1919) );
AO22X1 U1113 ( .IN1(n1424), .IN2(n1257), .IN3(n1921), .IN4(n1901), .Q(
\fpu_add_frac_dp/n3762 ) );
AO22X1 U1114 ( .IN1(n1424), .IN2(n1289), .IN3(n1921), .IN4(n1902), .Q(
\fpu_add_frac_dp/n3761 ) );
AO22X1 U1115 ( .IN1(n1424), .IN2(n1290), .IN3(n1922), .IN4(n1901), .Q(
\fpu_add_frac_dp/n3760 ) );
AO22X1 U1116 ( .IN1(n1424), .IN2(n1291), .IN3(n1922), .IN4(n1902), .Q(
\fpu_add_frac_dp/n3759 ) );
AO22X1 U1117 ( .IN1(n1425), .IN2(n1258), .IN3(n1921), .IN4(n1904), .Q(
\fpu_add_frac_dp/n3758 ) );
AO22X1 U1118 ( .IN1(n1425), .IN2(n1292), .IN3(n1921), .IN4(n1905), .Q(
\fpu_add_frac_dp/n3757 ) );
AND2X1 U1119 ( .IN1(n1923), .IN2(n73), .Q(n1921) );
AO22X1 U1120 ( .IN1(n1425), .IN2(n1259), .IN3(n1922), .IN4(n1904), .Q(
\fpu_add_frac_dp/n3756 ) );
AO22X1 U1121 ( .IN1(n1425), .IN2(n1293), .IN3(n1922), .IN4(n1905), .Q(
\fpu_add_frac_dp/n3755 ) );
AND2X1 U1122 ( .IN1(n1923), .IN2(\fpu_add_exp_dp/n146 ), .Q(n1922) );
AND2X1 U1123 ( .IN1(n1924), .IN2(n1907), .Q(n1923) );
AND2X1 U1124 ( .IN1(n1925), .IN2(n648), .Q(n1907) );
AO22X1 U1125 ( .IN1(n1425), .IN2(n1260), .IN3(n1920), .IN4(n1909), .Q(
\fpu_add_frac_dp/n3754 ) );
AO22X1 U1126 ( .IN1(n1425), .IN2(n1294), .IN3(n1920), .IN4(n1911), .Q(
\fpu_add_frac_dp/n3753 ) );
AO22X1 U1127 ( .IN1(n1425), .IN2(n1295), .IN3(n1920), .IN4(n1912), .Q(
\fpu_add_frac_dp/n3752 ) );
AO22X1 U1128 ( .IN1(n1425), .IN2(n1224), .IN3(n1920), .IN4(n1913), .Q(
\fpu_add_frac_dp/n3751 ) );
AO22X1 U1129 ( .IN1(n1425), .IN2(n1261), .IN3(n1920), .IN4(n1914), .Q(
\fpu_add_frac_dp/n3750 ) );
AO22X1 U1130 ( .IN1(n1425), .IN2(n1296), .IN3(n1920), .IN4(n1915), .Q(
\fpu_add_frac_dp/n3749 ) );
AO22X1 U1131 ( .IN1(n1425), .IN2(n1297), .IN3(n1920), .IN4(n1916), .Q(
\fpu_add_frac_dp/n3748 ) );
AO22X1 U1132 ( .IN1(n1425), .IN2(n1244), .IN3(n1920), .IN4(n1917), .Q(
\fpu_add_frac_dp/n3747 ) );
AO22X1 U1133 ( .IN1(n1425), .IN2(n1262), .IN3(n1924), .IN4(n1909), .Q(
\fpu_add_frac_dp/n3746 ) );
AND2X1 U1134 ( .IN1(n1926), .IN2(n1901), .Q(n1909) );
AO22X1 U1135 ( .IN1(n1425), .IN2(n1298), .IN3(n1924), .IN4(n1911), .Q(
\fpu_add_frac_dp/n3745 ) );
AND2X1 U1136 ( .IN1(n1926), .IN2(n1902), .Q(n1911) );
AO22X1 U1137 ( .IN1(n1425), .IN2(n1299), .IN3(n1924), .IN4(n1912), .Q(
\fpu_add_frac_dp/n3744 ) );
AND2X1 U1138 ( .IN1(n1927), .IN2(n1901), .Q(n1912) );
AO22X1 U1139 ( .IN1(n1426), .IN2(n1270), .IN3(n1924), .IN4(n1913), .Q(
\fpu_add_frac_dp/n3743 ) );
AND2X1 U1140 ( .IN1(n1927), .IN2(n1902), .Q(n1913) );
NOR2X0 U1141 ( .IN1(n645), .IN2(\fpu_add_exp_dp/n145 ), .QN(n1902) );
AO22X1 U1142 ( .IN1(n1426), .IN2(n1263), .IN3(n1924), .IN4(n1914), .Q(
\fpu_add_frac_dp/n3742 ) );
AND2X1 U1143 ( .IN1(n1926), .IN2(n1904), .Q(n1914) );
AO22X1 U1144 ( .IN1(n1426), .IN2(n1300), .IN3(n1924), .IN4(n1915), .Q(
\fpu_add_frac_dp/n3741 ) );
AND2X1 U1145 ( .IN1(n1926), .IN2(n1905), .Q(n1915) );
AND2X1 U1146 ( .IN1(n1928), .IN2(n73), .Q(n1926) );
AO22X1 U1147 ( .IN1(n1426), .IN2(n1301), .IN3(n1924), .IN4(n1916), .Q(
\fpu_add_frac_dp/n3740 ) );
AND2X1 U1148 ( .IN1(n1927), .IN2(n1904), .Q(n1916) );
NOR2X0 U1149 ( .IN1(n287), .IN2(\fpu_add_exp_dp/n147 ), .QN(n1904) );
AO22X1 U1150 ( .IN1(n1426), .IN2(n1235), .IN3(n1924), .IN4(n1917), .Q(
\fpu_add_frac_dp/n3739 ) );
AND2X1 U1151 ( .IN1(n1927), .IN2(n1905), .Q(n1917) );
NOR2X0 U1152 ( .IN1(n287), .IN2(n645), .QN(n1905) );
AND2X1 U1153 ( .IN1(n1928), .IN2(\fpu_add_exp_dp/n146 ), .Q(n1927) );
AND2X1 U1154 ( .IN1(\fpu_add_exp_dp/n143 ), .IN2(n1925), .Q(n1928) );
AND4X1 U1155 ( .IN1(\fpu_add_exp_dp/n137 ), .IN2(n1929), .IN3(n1449), .IN4(
n640), .Q(n1925) );
AO21X1 U1156 ( .IN1(n1396), .IN2(n1219), .IN3(n1930), .Q(
\fpu_add_frac_dp/n3738 ) );
AO22X1 U1157 ( .IN1(n1426), .IN2(n852), .IN3(n1931), .IN4(\fpu_add_ctl/n37 ),
.Q(\fpu_add_frac_dp/n3737 ) );
NOR2X0 U1158 ( .IN1(n1932), .IN2(n1933), .QN(n1931) );
NAND3X0 U1159 ( .IN1(n1934), .IN2(n1935), .IN3(n1936), .QN(
\fpu_add_frac_dp/n3736 ) );
NAND2X0 U1160 ( .IN1(n1430), .IN2(n926), .QN(n1936) );
AO22X1 U1161 ( .IN1(n1426), .IN2(n1264), .IN3(n1442), .IN4(n1937), .Q(
\fpu_add_frac_dp/n3735 ) );
NAND4X0 U1162 ( .IN1(n1938), .IN2(n1939), .IN3(n1940), .IN4(n1941), .QN(
n1937) );
NOR4X0 U1163 ( .IN1(n1942), .IN2(n1943), .IN3(n1944), .IN4(n1945), .QN(n1941) );
AO222X1 U1164 ( .IN1(\fpu_add_frac_dp/n2399 ), .IN2(n1946), .IN3(n1947),
.IN4(n746), .IN5(n1948), .IN6(n166), .Q(n1943) );
OR4X1 U1165 ( .IN1(n1949), .IN2(n1950), .IN3(n1951), .IN4(n1952), .Q(n1947)
);
NAND4X0 U1166 ( .IN1(n1953), .IN2(n1954), .IN3(n1955), .IN4(n1956), .QN(
n1942) );
NOR2X0 U1167 ( .IN1(n1957), .IN2(n1958), .QN(n1956) );
INVX0 U1168 ( .INP(n1959), .ZN(n1955) );
INVX0 U1169 ( .INP(n1960), .ZN(n1953) );
NOR4X0 U1170 ( .IN1(n1961), .IN2(n1962), .IN3(n1963), .IN4(n1964), .QN(n1940) );
OR3X1 U1171 ( .IN1(n1965), .IN2(n1966), .IN3(n1967), .Q(n1962) );
OR4X1 U1172 ( .IN1(n1968), .IN2(n1969), .IN3(n1970), .IN4(n1971), .Q(n1961)
);
OR2X1 U1173 ( .IN1(n1972), .IN2(n1973), .Q(n1970) );
NOR4X0 U1174 ( .IN1(n1974), .IN2(n1975), .IN3(n1976), .IN4(n1977), .QN(n1939) );
OR3X1 U1175 ( .IN1(n1978), .IN2(n1979), .IN3(n1980), .Q(n1975) );
OR4X1 U1176 ( .IN1(n1981), .IN2(n1982), .IN3(n1983), .IN4(n1984), .Q(n1974)
);
OR2X1 U1177 ( .IN1(n1985), .IN2(n1986), .Q(n1984) );
NOR4X0 U1178 ( .IN1(n1987), .IN2(n1988), .IN3(n1989), .IN4(n1990), .QN(n1938) );
OR3X1 U1179 ( .IN1(n1991), .IN2(n1992), .IN3(n1993), .Q(n1988) );
OR4X1 U1180 ( .IN1(n1994), .IN2(n1995), .IN3(n1996), .IN4(n1997), .Q(n1987)
);
INVX0 U1181 ( .INP(n1998), .ZN(n1994) );
AO22X1 U1182 ( .IN1(n1416), .IN2(n1302), .IN3(n1442), .IN4(n1999), .Q(
\fpu_add_frac_dp/n3734 ) );
NAND4X0 U1183 ( .IN1(n2000), .IN2(n2001), .IN3(n2002), .IN4(n2003), .QN(
n1999) );
OA222X1 U1184 ( .IN1(\fpu_add_frac_dp/n2308 ), .IN2(n2004), .IN3(n2005),
.IN4(n2006), .IN5(\fpu_add_frac_dp/n579 ), .IN6(n2007), .Q(n2003) );
INVX0 U1185 ( .INP(n2008), .ZN(n2007) );
OA22X1 U1186 ( .IN1(\fpu_add_frac_dp/n2377 ), .IN2(n2009), .IN3(
\fpu_add_frac_dp/n580 ), .IN4(n2010), .Q(n2002) );
NOR4X0 U1187 ( .IN1(n2011), .IN2(n2012), .IN3(n2013), .IN4(n2014), .QN(n2010) );
NOR2X0 U1188 ( .IN1(n2015), .IN2(n2016), .QN(n2013) );
AO222X1 U1189 ( .IN1(n2017), .IN2(n693), .IN3(n2018), .IN4(n2019), .IN5(
n2020), .IN6(n2021), .Q(n2011) );
NOR2X0 U1190 ( .IN1(\fpu_add_frac_dp/n2308 ), .IN2(n2022), .QN(n2018) );
NAND3X0 U1191 ( .IN1(n2023), .IN2(n2024), .IN3(n2025), .QN(n2017) );
AOI222X1 U1192 ( .IN1(n255), .IN2(n2026), .IN3(n2027), .IN4(n2021), .IN5(
n1989), .IN6(n2028), .QN(n2025) );
INVX0 U1193 ( .INP(n2029), .ZN(n2023) );
OA221X1 U1194 ( .IN1(n2030), .IN2(n2016), .IN3(\fpu_add_frac_dp/n2308 ),
.IN4(n2031), .IN5(n2032), .Q(n2009) );
AOI21X1 U1195 ( .IN1(n2021), .IN2(n2029), .IN3(n2033), .QN(n2032) );
NAND2X0 U1196 ( .IN1(\fpu_add_frac_dp/n2306 ), .IN2(n2034), .QN(n2001) );
NAND4X0 U1197 ( .IN1(n2035), .IN2(n2036), .IN3(n2037), .IN4(n2038), .QN(
n2034) );
OA22X1 U1198 ( .IN1(n2039), .IN2(n2016), .IN3(\fpu_add_frac_dp/n2308 ),
.IN4(n2040), .Q(n2037) );
INVX0 U1199 ( .INP(n2041), .ZN(n2036) );
INVX0 U1200 ( .INP(n2042), .ZN(n2035) );
NAND2X0 U1201 ( .IN1(n2028), .IN2(n2043), .QN(n2000) );
AO21X1 U1202 ( .IN1(n1397), .IN2(n1121), .IN3(n1319), .Q(
\fpu_add_frac_dp/n3733 ) );
AO22X1 U1203 ( .IN1(\fpu_add_frac_dp/n2369 ), .IN2(n1430), .IN3(n2044),
.IN4(n2045), .Q(\fpu_add_frac_dp/n3732 ) );
INVX0 U1204 ( .INP(n1934), .ZN(n2044) );
OAI221X1 U1205 ( .IN1(n1934), .IN2(n2045), .IN3(n2046), .IN4(
\fpu_add_frac_dp/n5614 ), .IN5(n1935), .QN(\fpu_add_frac_dp/n3731 ) );
NAND3X0 U1206 ( .IN1(n1435), .IN2(n649), .IN3(n2047), .QN(n1935) );
MUX21X1 U1207 ( .IN1(n2048), .IN2(n2049), .S(n2050), .Q(n2045) );
NAND3X0 U1208 ( .IN1(n2051), .IN2(n2052), .IN3(n2053), .QN(n2049) );
INVX0 U1209 ( .INP(n2054), .ZN(n2053) );
NAND2X0 U1210 ( .IN1(n2055), .IN2(n2056), .QN(n2048) );
XOR2X1 U1211 ( .IN1(n2057), .IN2(n2058), .Q(n2056) );
INVX0 U1212 ( .INP(n2059), .ZN(n2055) );
NAND3X0 U1213 ( .IN1(n1737), .IN2(n1435), .IN3(n1656), .QN(n1934) );
AO22X1 U1214 ( .IN1(n1417), .IN2(n652), .IN3(n2060), .IN4(n1440), .Q(
\fpu_add_frac_dp/n3730 ) );
XOR3X1 U1215 ( .IN1(\fpu_add_frac_dp/n2478 ), .IN2(\fpu_add_frac_dp/n2477 ),
.IN3(n2061), .Q(n2060) );
AO22X1 U1216 ( .IN1(n1417), .IN2(n103), .IN3(n2062), .IN4(n1440), .Q(
\fpu_add_frac_dp/n3729 ) );
XOR3X1 U1217 ( .IN1(n625), .IN2(n2063), .IN3(n2064), .Q(n2062) );
AO22X1 U1218 ( .IN1(n1417), .IN2(n282), .IN3(n2065), .IN4(n1440), .Q(
\fpu_add_frac_dp/n3728 ) );
XOR2X1 U1219 ( .IN1(n220), .IN2(n2066), .Q(n2065) );
NOR2X0 U1220 ( .IN1(n2067), .IN2(n2068), .QN(n2066) );
AO22X1 U1221 ( .IN1(n1417), .IN2(n671), .IN3(n1441), .IN4(n2069), .Q(
\fpu_add_frac_dp/n3727 ) );
XOR3X1 U1222 ( .IN1(n310), .IN2(n2070), .IN3(n2071), .Q(n2069) );
AO22X1 U1223 ( .IN1(n1417), .IN2(n90), .IN3(n1442), .IN4(n2072), .Q(
\fpu_add_frac_dp/n3726 ) );
XOR3X1 U1224 ( .IN1(n2073), .IN2(n288), .IN3(n2074), .Q(n2072) );
AO22X1 U1225 ( .IN1(n1417), .IN2(n626), .IN3(n2075), .IN4(n1440), .Q(
\fpu_add_frac_dp/n3725 ) );
XOR3X1 U1226 ( .IN1(n2076), .IN2(n223), .IN3(n2077), .Q(n2075) );
AO22X1 U1227 ( .IN1(n1417), .IN2(n173), .IN3(n1442), .IN4(n2078), .Q(
\fpu_add_frac_dp/n3724 ) );
XOR3X1 U1228 ( .IN1(n2079), .IN2(n225), .IN3(n2080), .Q(n2078) );
AO22X1 U1229 ( .IN1(n1417), .IN2(n33), .IN3(n2081), .IN4(n1440), .Q(
\fpu_add_frac_dp/n3723 ) );
XOR3X1 U1230 ( .IN1(n2082), .IN2(n222), .IN3(n2083), .Q(n2081) );
AO22X1 U1231 ( .IN1(n1418), .IN2(n623), .IN3(n1441), .IN4(n2084), .Q(
\fpu_add_frac_dp/n3722 ) );
XOR3X1 U1232 ( .IN1(n2085), .IN2(n224), .IN3(n2086), .Q(n2084) );
AO22X1 U1233 ( .IN1(n1418), .IN2(n34), .IN3(n2087), .IN4(n1440), .Q(
\fpu_add_frac_dp/n3721 ) );
XOR3X1 U1234 ( .IN1(n261), .IN2(n2088), .IN3(n2089), .Q(n2087) );
AO22X1 U1235 ( .IN1(n1417), .IN2(n12), .IN3(n2090), .IN4(n1439), .Q(
\fpu_add_frac_dp/n3720 ) );
XOR3X1 U1236 ( .IN1(n260), .IN2(n2091), .IN3(n2092), .Q(n2090) );
AO22X1 U1237 ( .IN1(n1417), .IN2(n691), .IN3(n2093), .IN4(n1440), .Q(
\fpu_add_frac_dp/n3719 ) );
XOR3X1 U1238 ( .IN1(n253), .IN2(n2094), .IN3(n2095), .Q(n2093) );
AO22X1 U1239 ( .IN1(n1417), .IN2(n37), .IN3(n2096), .IN4(n1440), .Q(
\fpu_add_frac_dp/n3718 ) );
XOR3X1 U1240 ( .IN1(n252), .IN2(n2097), .IN3(n2098), .Q(n2096) );
AO22X1 U1241 ( .IN1(n1417), .IN2(n597), .IN3(n1441), .IN4(n2099), .Q(
\fpu_add_frac_dp/n3717 ) );
AO22X1 U1242 ( .IN1(n2100), .IN2(n2101), .IN3(n2102), .IN4(n327), .Q(n2099)
);
NAND2X0 U1243 ( .IN1(n2103), .IN2(n2101), .QN(n2102) );
INVX0 U1244 ( .INP(n2104), .ZN(n2100) );
AO22X1 U1245 ( .IN1(\fpu_add_frac_dp/n2330 ), .IN2(n1430), .IN3(n2105),
.IN4(n1440), .Q(\fpu_add_frac_dp/n3716 ) );
XOR2X1 U1246 ( .IN1(n180), .IN2(n2106), .Q(n2105) );
AND2X1 U1247 ( .IN1(n2107), .IN2(n2108), .Q(n2106) );
AO22X1 U1248 ( .IN1(\fpu_add_frac_dp/n2400 ), .IN2(n1419), .IN3(n2109),
.IN4(n1440), .Q(\fpu_add_frac_dp/n3715 ) );
XOR2X1 U1249 ( .IN1(n268), .IN2(n2110), .Q(n2109) );
NOR2X0 U1250 ( .IN1(n2111), .IN2(n2112), .QN(n2110) );
INVX0 U1251 ( .INP(n2113), .ZN(n2111) );
AO22X1 U1252 ( .IN1(n1417), .IN2(n328), .IN3(n2114), .IN4(n1440), .Q(
\fpu_add_frac_dp/n3714 ) );
XOR2X1 U1253 ( .IN1(n179), .IN2(n2115), .Q(n2114) );
OA21X1 U1254 ( .IN1(n2116), .IN2(n2117), .IN3(n2118), .Q(n2115) );
AO22X1 U1255 ( .IN1(n1418), .IN2(n43), .IN3(n1441), .IN4(n2119), .Q(
\fpu_add_frac_dp/n3713 ) );
XOR3X1 U1256 ( .IN1(n251), .IN2(n2120), .IN3(n2121), .Q(n2119) );
AO22X1 U1257 ( .IN1(n1418), .IN2(n111), .IN3(n2122), .IN4(n1439), .Q(
\fpu_add_frac_dp/n3712 ) );
XOR3X1 U1258 ( .IN1(n250), .IN2(n2123), .IN3(n2124), .Q(n2122) );
AO22X1 U1259 ( .IN1(n1418), .IN2(n664), .IN3(n2125), .IN4(n1440), .Q(
\fpu_add_frac_dp/n3711 ) );
XOR3X1 U1260 ( .IN1(n249), .IN2(n2126), .IN3(n2127), .Q(n2125) );
AO22X1 U1261 ( .IN1(\fpu_add_frac_dp/n2339 ), .IN2(n1430), .IN3(n2128),
.IN4(n1440), .Q(\fpu_add_frac_dp/n3710 ) );
XOR2X1 U1262 ( .IN1(n263), .IN2(n2129), .Q(n2128) );
AND2X1 U1263 ( .IN1(n2130), .IN2(n2131), .Q(n2129) );
AO22X1 U1264 ( .IN1(\fpu_add_frac_dp/n2405 ), .IN2(n1430), .IN3(n2132),
.IN4(n1440), .Q(\fpu_add_frac_dp/n3709 ) );
XOR2X1 U1265 ( .IN1(n267), .IN2(n2133), .Q(n2132) );
NOR2X0 U1266 ( .IN1(n2134), .IN2(n2135), .QN(n2133) );
INVX0 U1267 ( .INP(n2136), .ZN(n2134) );
AO22X1 U1268 ( .IN1(n1418), .IN2(n594), .IN3(n1441), .IN4(n2137), .Q(
\fpu_add_frac_dp/n3708 ) );
XOR3X1 U1269 ( .IN1(n2138), .IN2(n279), .IN3(n2139), .Q(n2137) );
AO22X1 U1270 ( .IN1(n1418), .IN2(n74), .IN3(n2140), .IN4(n1438), .Q(
\fpu_add_frac_dp/n3707 ) );
XOR3X1 U1271 ( .IN1(\fpu_add_frac_dp/n814 ), .IN2(n2141), .IN3(n2142), .Q(
n2140) );
AO22X1 U1272 ( .IN1(n1418), .IN2(n331), .IN3(n2143), .IN4(n1439), .Q(
\fpu_add_frac_dp/n3706 ) );
XOR3X1 U1273 ( .IN1(n248), .IN2(n2144), .IN3(n2145), .Q(n2143) );
AO22X1 U1274 ( .IN1(n1418), .IN2(n116), .IN3(n2146), .IN4(n1440), .Q(
\fpu_add_frac_dp/n3705 ) );
XOR3X1 U1275 ( .IN1(n247), .IN2(n2147), .IN3(n2148), .Q(n2146) );
AO22X1 U1276 ( .IN1(\fpu_add_frac_dp/n2402 ), .IN2(n1430), .IN3(n2149),
.IN4(n1439), .Q(\fpu_add_frac_dp/n3704 ) );
XOR3X1 U1277 ( .IN1(n246), .IN2(n2150), .IN3(n2151), .Q(n2149) );
AO22X1 U1278 ( .IN1(\fpu_add_frac_dp/n2313 ), .IN2(n1430), .IN3(n2152),
.IN4(n1440), .Q(\fpu_add_frac_dp/n3703 ) );
XOR2X1 U1279 ( .IN1(n204), .IN2(n2153), .Q(n2152) );
NOR2X0 U1280 ( .IN1(n2154), .IN2(n2155), .QN(n2153) );
AO22X1 U1281 ( .IN1(n1418), .IN2(n329), .IN3(n1441), .IN4(n2156), .Q(
\fpu_add_frac_dp/n3702 ) );
XOR3X1 U1282 ( .IN1(n245), .IN2(n2157), .IN3(n2158), .Q(n2156) );
AO22X1 U1283 ( .IN1(n1418), .IN2(n101), .IN3(n2159), .IN4(n1440), .Q(
\fpu_add_frac_dp/n3701 ) );
XOR3X1 U1284 ( .IN1(n244), .IN2(n2160), .IN3(n2161), .Q(n2159) );
AO22X1 U1285 ( .IN1(n1418), .IN2(n262), .IN3(n2162), .IN4(n1439), .Q(
\fpu_add_frac_dp/n3700 ) );
XOR2X1 U1286 ( .IN1(n203), .IN2(n2163), .Q(n2162) );
NOR2X0 U1287 ( .IN1(n2164), .IN2(n2165), .QN(n2163) );
AO22X1 U1288 ( .IN1(\fpu_add_frac_dp/n2335 ), .IN2(n1430), .IN3(n1441),
.IN4(n2166), .Q(\fpu_add_frac_dp/n3699 ) );
XOR3X1 U1289 ( .IN1(n243), .IN2(n2167), .IN3(n2168), .Q(n2166) );
AO22X1 U1290 ( .IN1(\fpu_add_frac_dp/n2403 ), .IN2(n1430), .IN3(n2169),
.IN4(n1439), .Q(\fpu_add_frac_dp/n3698 ) );
XOR3X1 U1291 ( .IN1(n242), .IN2(n2170), .IN3(n2171), .Q(n2169) );
AO22X1 U1292 ( .IN1(\fpu_add_frac_dp/n2342 ), .IN2(n1418), .IN3(n2172),
.IN4(n1438), .Q(\fpu_add_frac_dp/n3697 ) );
XOR3X1 U1293 ( .IN1(n241), .IN2(n2173), .IN3(n2174), .Q(n2172) );
AO22X1 U1294 ( .IN1(\fpu_add_frac_dp/n2289 ), .IN2(n1430), .IN3(n2175),
.IN4(n1439), .Q(\fpu_add_frac_dp/n3696 ) );
XOR3X1 U1295 ( .IN1(n240), .IN2(n2176), .IN3(n2177), .Q(n2175) );
AO22X1 U1296 ( .IN1(\fpu_add_frac_dp/n2406 ), .IN2(n1417), .IN3(n2178),
.IN4(n1439), .Q(\fpu_add_frac_dp/n3695 ) );
XOR2X1 U1297 ( .IN1(n202), .IN2(n2179), .Q(n2178) );
NOR2X0 U1298 ( .IN1(n2180), .IN2(n2181), .QN(n2179) );
AO22X1 U1299 ( .IN1(\fpu_add_frac_dp/n2332 ), .IN2(n1430), .IN3(n1441),
.IN4(n2182), .Q(\fpu_add_frac_dp/n3694 ) );
XOR3X1 U1300 ( .IN1(n239), .IN2(n2183), .IN3(n2184), .Q(n2182) );
AO22X1 U1301 ( .IN1(n1419), .IN2(n177), .IN3(n2185), .IN4(n1439), .Q(
\fpu_add_frac_dp/n3693 ) );
XOR2X1 U1302 ( .IN1(n201), .IN2(n2186), .Q(n2185) );
NOR2X0 U1303 ( .IN1(n2187), .IN2(n2188), .QN(n2186) );
AO22X1 U1304 ( .IN1(n1419), .IN2(n86), .IN3(n1441), .IN4(n2189), .Q(
\fpu_add_frac_dp/n3692 ) );
XOR3X1 U1305 ( .IN1(n238), .IN2(n2190), .IN3(n2191), .Q(n2189) );
AO22X1 U1306 ( .IN1(n1419), .IN2(n19), .IN3(n2192), .IN4(n1439), .Q(
\fpu_add_frac_dp/n3691 ) );
XOR2X1 U1307 ( .IN1(n200), .IN2(n2193), .Q(n2192) );
NOR2X0 U1308 ( .IN1(n2194), .IN2(n2195), .QN(n2193) );
AO22X1 U1309 ( .IN1(n1419), .IN2(n673), .IN3(n1441), .IN4(n2196), .Q(
\fpu_add_frac_dp/n3690 ) );
XOR3X1 U1310 ( .IN1(n259), .IN2(n2197), .IN3(n2198), .Q(n2196) );
AO22X1 U1311 ( .IN1(n1419), .IN2(n117), .IN3(n2199), .IN4(n1439), .Q(
\fpu_add_frac_dp/n3689 ) );
XOR3X1 U1312 ( .IN1(n237), .IN2(n2200), .IN3(n2201), .Q(n2199) );
AO22X1 U1313 ( .IN1(n1419), .IN2(n38), .IN3(n2202), .IN4(n1439), .Q(
\fpu_add_frac_dp/n3688 ) );
XOR2X1 U1314 ( .IN1(n199), .IN2(n2203), .Q(n2202) );
NOR2X0 U1315 ( .IN1(n2204), .IN2(n2205), .QN(n2203) );
AO22X1 U1316 ( .IN1(n1420), .IN2(n83), .IN3(n1441), .IN4(n2206), .Q(
\fpu_add_frac_dp/n3687 ) );
XOR3X1 U1317 ( .IN1(n236), .IN2(n2207), .IN3(n2208), .Q(n2206) );
AO22X1 U1318 ( .IN1(n1420), .IN2(n665), .IN3(n2209), .IN4(n1439), .Q(
\fpu_add_frac_dp/n3686 ) );
XOR3X1 U1319 ( .IN1(n235), .IN2(n2210), .IN3(n2211), .Q(n2209) );
AO22X1 U1320 ( .IN1(n1420), .IN2(n100), .IN3(n2212), .IN4(n1439), .Q(
\fpu_add_frac_dp/n3685 ) );
XOR3X1 U1321 ( .IN1(n234), .IN2(n2213), .IN3(n2214), .Q(n2212) );
AO22X1 U1322 ( .IN1(n1420), .IN2(n667), .IN3(n2215), .IN4(n1439), .Q(
\fpu_add_frac_dp/n3684 ) );
XOR2X1 U1323 ( .IN1(n198), .IN2(n2216), .Q(n2215) );
NOR2X0 U1324 ( .IN1(n2217), .IN2(n2218), .QN(n2216) );
AO22X1 U1325 ( .IN1(n1420), .IN2(n40), .IN3(n2219), .IN4(n1439), .Q(
\fpu_add_frac_dp/n3683 ) );
XOR2X1 U1326 ( .IN1(n197), .IN2(n2220), .Q(n2219) );
NOR2X0 U1327 ( .IN1(n2221), .IN2(n2222), .QN(n2220) );
AO22X1 U1328 ( .IN1(n1420), .IN2(n104), .IN3(n1441), .IN4(n2223), .Q(
\fpu_add_frac_dp/n3682 ) );
XOR3X1 U1329 ( .IN1(n233), .IN2(n2224), .IN3(n2225), .Q(n2223) );
AO22X1 U1330 ( .IN1(n1420), .IN2(n175), .IN3(n2226), .IN4(n1439), .Q(
\fpu_add_frac_dp/n3681 ) );
XOR3X1 U1331 ( .IN1(n232), .IN2(n2227), .IN3(n2228), .Q(n2226) );
AO22X1 U1332 ( .IN1(n1420), .IN2(n22), .IN3(n2229), .IN4(n1438), .Q(
\fpu_add_frac_dp/n3680 ) );
XOR3X1 U1333 ( .IN1(n231), .IN2(n2230), .IN3(n2231), .Q(n2229) );
AO22X1 U1334 ( .IN1(n1420), .IN2(n85), .IN3(n2232), .IN4(n1438), .Q(
\fpu_add_frac_dp/n3679 ) );
XOR3X1 U1335 ( .IN1(n230), .IN2(n2233), .IN3(n2234), .Q(n2232) );
AO22X1 U1336 ( .IN1(n1420), .IN2(n313), .IN3(n2235), .IN4(n1438), .Q(
\fpu_add_frac_dp/n3678 ) );
XOR3X1 U1337 ( .IN1(n229), .IN2(n2236), .IN3(n2237), .Q(n2235) );
AO22X1 U1338 ( .IN1(n1420), .IN2(n92), .IN3(n2238), .IN4(n1438), .Q(
\fpu_add_frac_dp/n3677 ) );
XOR3X1 U1339 ( .IN1(n228), .IN2(n2239), .IN3(n2240), .Q(n2238) );
AO22X1 U1340 ( .IN1(n1420), .IN2(n265), .IN3(n2241), .IN4(n1438), .Q(
\fpu_add_frac_dp/n3676 ) );
XOR3X1 U1341 ( .IN1(n227), .IN2(n2242), .IN3(n2243), .Q(n2241) );
AO22X1 U1342 ( .IN1(\fpu_add_frac_dp/n2338 ), .IN2(n1430), .IN3(n2244),
.IN4(n1438), .Q(\fpu_add_frac_dp/n3675 ) );
XOR2X1 U1343 ( .IN1(n196), .IN2(n2245), .Q(n2244) );
NOR2X0 U1344 ( .IN1(n2246), .IN2(n2247), .QN(n2245) );
AO22X1 U1345 ( .IN1(\fpu_add_frac_dp/n2407 ), .IN2(n1430), .IN3(n1441),
.IN4(n2248), .Q(\fpu_add_frac_dp/n3674 ) );
XOR3X1 U1346 ( .IN1(n294), .IN2(n2249), .IN3(n2250), .Q(n2248) );
AO22X1 U1347 ( .IN1(\fpu_add_frac_dp/n2343 ), .IN2(n1430), .IN3(n2251),
.IN4(n1438), .Q(\fpu_add_frac_dp/n3673 ) );
XOR2X1 U1348 ( .IN1(n2252), .IN2(\fpu_add_frac_dp/n780 ), .Q(n2251) );
NAND2X0 U1349 ( .IN1(n2253), .IN2(n2254), .QN(n2252) );
INVX0 U1350 ( .INP(n2255), .ZN(n2253) );
AO22X1 U1351 ( .IN1(n1420), .IN2(n171), .IN3(n1441), .IN4(n2256), .Q(
\fpu_add_frac_dp/n3672 ) );
AO22X1 U1352 ( .IN1(n2257), .IN2(n334), .IN3(n2258), .IN4(n2259), .Q(n2256)
);
NAND2X0 U1353 ( .IN1(n2260), .IN2(n2261), .QN(n2259) );
XNOR2X1 U1354 ( .IN1(n2261), .IN2(n2260), .Q(n2257) );
AO22X1 U1355 ( .IN1(n1420), .IN2(n82), .IN3(n1441), .IN4(n2262), .Q(
\fpu_add_frac_dp/n3671 ) );
XOR3X1 U1356 ( .IN1(n293), .IN2(n2263), .IN3(n2264), .Q(n2262) );
AO22X1 U1357 ( .IN1(\fpu_add_frac_dp/n2337 ), .IN2(n1420), .IN3(n2265),
.IN4(n1438), .Q(\fpu_add_frac_dp/n3670 ) );
XOR3X1 U1358 ( .IN1(\fpu_add_frac_dp/n777 ), .IN2(n2266), .IN3(n2267), .Q(
n2265) );
AO22X1 U1359 ( .IN1(n1420), .IN2(n94), .IN3(n2268), .IN4(n1438), .Q(
\fpu_add_frac_dp/n3669 ) );
XOR2X1 U1360 ( .IN1(n195), .IN2(n2269), .Q(n2268) );
NOR2X0 U1361 ( .IN1(n2270), .IN2(n2271), .QN(n2269) );
AO22X1 U1362 ( .IN1(n1421), .IN2(n266), .IN3(n1441), .IN4(n2272), .Q(
\fpu_add_frac_dp/n3668 ) );
XOR3X1 U1363 ( .IN1(n226), .IN2(n2273), .IN3(n2274), .Q(n2272) );
AO22X1 U1364 ( .IN1(n1422), .IN2(n87), .IN3(n1441), .IN4(n2275), .Q(
\fpu_add_frac_dp/n3667 ) );
XOR3X1 U1365 ( .IN1(\fpu_add_frac_dp/n5640 ), .IN2(n2276), .IN3(n2277), .Q(
n2275) );
NOR2X0 U1366 ( .IN1(\fpu_add_frac_dp/n2369 ), .IN2(n2278), .QN(n2277) );
MUX21X1 U1367 ( .IN1(n1324), .IN2(n1328), .S(\fpu_add_frac_dp/n2498 ), .Q(
n2278) );
OA22X1 U1368 ( .IN1(n2279), .IN2(n226), .IN3(n2280), .IN4(n2281), .Q(n2276)
);
NOR2X0 U1369 ( .IN1(n2273), .IN2(n2274), .QN(n2279) );
INVX0 U1370 ( .INP(n2280), .ZN(n2274) );
OA21X1 U1371 ( .IN1(n195), .IN2(n2270), .IN3(n2282), .Q(n2280) );
INVX0 U1372 ( .INP(n2271), .ZN(n2282) );
NOR2X0 U1373 ( .IN1(n2283), .IN2(n2284), .QN(n2271) );
AND2X1 U1374 ( .IN1(n2283), .IN2(n2284), .Q(n2270) );
AO21X1 U1375 ( .IN1(\fpu_add_frac_dp/n2502 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2285), .Q(n2284) );
MUX21X1 U1376 ( .IN1(n1323), .IN2(n1327), .S(\fpu_add_frac_dp/n2506 ), .Q(
n2285) );
AO22X1 U1377 ( .IN1(n2267), .IN2(n2286), .IN3(n2287), .IN4(n317), .Q(n2283)
);
NAND2X0 U1378 ( .IN1(n2288), .IN2(n2266), .QN(n2287) );
INVX0 U1379 ( .INP(n2286), .ZN(n2266) );
AO21X1 U1380 ( .IN1(\fpu_add_frac_dp/n2506 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2289), .Q(n2286) );
MUX21X1 U1381 ( .IN1(n1327), .IN2(n1324), .S(\fpu_add_frac_dp/n2384 ), .Q(
n2289) );
INVX0 U1382 ( .INP(n2288), .ZN(n2267) );
OA22X1 U1383 ( .IN1(n2264), .IN2(n2263), .IN3(n2290), .IN4(
\fpu_add_frac_dp/n778 ), .Q(n2288) );
AND2X1 U1384 ( .IN1(n2263), .IN2(n2264), .Q(n2290) );
AOI21X1 U1385 ( .IN1(\fpu_add_frac_dp/n2369 ), .IN2(n1009), .IN3(n2291),
.QN(n2263) );
MUX21X1 U1386 ( .IN1(n64), .IN2(n1323), .S(\fpu_add_frac_dp/n2391 ), .Q(
n2291) );
AO21X1 U1387 ( .IN1(n2260), .IN2(n2261), .IN3(n2258), .Q(n2264) );
OA21X1 U1388 ( .IN1(n2261), .IN2(n2260), .IN3(\fpu_add_frac_dp/n779 ), .Q(
n2258) );
OAI21X1 U1389 ( .IN1(n332), .IN2(n2255), .IN3(n2254), .QN(n2261) );
NAND2X0 U1390 ( .IN1(n2292), .IN2(n2293), .QN(n2254) );
NOR2X0 U1391 ( .IN1(n2293), .IN2(n2292), .QN(n2255) );
AOI21X1 U1392 ( .IN1(\fpu_add_frac_dp/n2369 ), .IN2(n561), .IN3(n2294), .QN(
n2292) );
MUX21X1 U1393 ( .IN1(n1328), .IN2(n155), .S(\fpu_add_frac_dp/n2392 ), .Q(
n2294) );
AO22X1 U1394 ( .IN1(n2249), .IN2(n2250), .IN3(\fpu_add_frac_dp/n781 ), .IN4(
n2295), .Q(n2293) );
NAND2X0 U1395 ( .IN1(n2296), .IN2(n2297), .QN(n2295) );
INVX0 U1396 ( .INP(n2296), .ZN(n2250) );
OA21X1 U1397 ( .IN1(n196), .IN2(n2246), .IN3(n2298), .Q(n2296) );
INVX0 U1398 ( .INP(n2247), .ZN(n2298) );
NOR2X0 U1399 ( .IN1(n2299), .IN2(n2300), .QN(n2247) );
AND2X1 U1400 ( .IN1(n2299), .IN2(n2300), .Q(n2246) );
AO21X1 U1401 ( .IN1(\fpu_add_frac_dp/n2357 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2301), .Q(n2300) );
MUX21X1 U1402 ( .IN1(n155), .IN2(n64), .S(\fpu_add_frac_dp/n2431 ), .Q(n2301) );
AO22X1 U1403 ( .IN1(n2243), .IN2(n2242), .IN3(n2302), .IN4(n227), .Q(n2299)
);
OR2X1 U1404 ( .IN1(n2243), .IN2(n2242), .Q(n2302) );
AO21X1 U1405 ( .IN1(\fpu_add_frac_dp/n2431 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2303), .Q(n2242) );
MUX21X1 U1406 ( .IN1(n1325), .IN2(n1328), .S(\fpu_add_frac_dp/n2418 ), .Q(
n2303) );
AO22X1 U1407 ( .IN1(n2240), .IN2(n2239), .IN3(n2304), .IN4(n228), .Q(n2243)
);
OR2X1 U1408 ( .IN1(n2240), .IN2(n2239), .Q(n2304) );
AO21X1 U1409 ( .IN1(\fpu_add_frac_dp/n2418 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2305), .Q(n2239) );
MUX21X1 U1410 ( .IN1(n1324), .IN2(n1327), .S(\fpu_add_frac_dp/n2351 ), .Q(
n2305) );
AO22X1 U1411 ( .IN1(n2237), .IN2(n2236), .IN3(n2306), .IN4(n229), .Q(n2240)
);
OR2X1 U1412 ( .IN1(n2237), .IN2(n2236), .Q(n2306) );
AO21X1 U1413 ( .IN1(\fpu_add_frac_dp/n2351 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2307), .Q(n2236) );
MUX21X1 U1414 ( .IN1(n1323), .IN2(n64), .S(\fpu_add_frac_dp/n2505 ), .Q(
n2307) );
AO22X1 U1415 ( .IN1(n2234), .IN2(n2233), .IN3(n2308), .IN4(n230), .Q(n2237)
);
OR2X1 U1416 ( .IN1(n2234), .IN2(n2233), .Q(n2308) );
AO21X1 U1417 ( .IN1(\fpu_add_frac_dp/n2505 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2309), .Q(n2233) );
MUX21X1 U1418 ( .IN1(n155), .IN2(n1328), .S(\fpu_add_frac_dp/n2501 ), .Q(
n2309) );
AO22X1 U1419 ( .IN1(n2231), .IN2(n2230), .IN3(n2310), .IN4(n231), .Q(n2234)
);
OR2X1 U1420 ( .IN1(n2231), .IN2(n2230), .Q(n2310) );
AO21X1 U1421 ( .IN1(\fpu_add_frac_dp/n2501 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2311), .Q(n2230) );
MUX21X1 U1422 ( .IN1(n1325), .IN2(n1327), .S(\fpu_add_frac_dp/n2512 ), .Q(
n2311) );
AO22X1 U1423 ( .IN1(n2228), .IN2(n2227), .IN3(n2312), .IN4(n232), .Q(n2231)
);
OR2X1 U1424 ( .IN1(n2228), .IN2(n2227), .Q(n2312) );
AO21X1 U1425 ( .IN1(\fpu_add_frac_dp/n2512 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2313), .Q(n2227) );
MUX21X1 U1426 ( .IN1(n1324), .IN2(n64), .S(\fpu_add_frac_dp/n2509 ), .Q(
n2313) );
AO22X1 U1427 ( .IN1(n2314), .IN2(n2315), .IN3(n2316), .IN4(n233), .Q(n2228)
);
NAND2X0 U1428 ( .IN1(n2224), .IN2(n2225), .QN(n2316) );
INVX0 U1429 ( .INP(n2314), .ZN(n2225) );
INVX0 U1430 ( .INP(n2315), .ZN(n2224) );
AO21X1 U1431 ( .IN1(\fpu_add_frac_dp/n2509 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2317), .Q(n2315) );
MUX21X1 U1432 ( .IN1(n1323), .IN2(n1328), .S(\fpu_add_frac_dp/n2500 ), .Q(
n2317) );
OA21X1 U1433 ( .IN1(n197), .IN2(n2221), .IN3(n2318), .Q(n2314) );
INVX0 U1434 ( .INP(n2222), .ZN(n2318) );
NOR2X0 U1435 ( .IN1(n2319), .IN2(n2320), .QN(n2222) );
AND2X1 U1436 ( .IN1(n2320), .IN2(n2319), .Q(n2221) );
AO21X1 U1437 ( .IN1(\fpu_add_frac_dp/n2500 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2321), .Q(n2319) );
MUX21X1 U1438 ( .IN1(n155), .IN2(n1327), .S(\fpu_add_frac_dp/n2303 ), .Q(
n2321) );
OA21X1 U1439 ( .IN1(n198), .IN2(n2217), .IN3(n2322), .Q(n2320) );
INVX0 U1440 ( .INP(n2218), .ZN(n2322) );
NOR2X0 U1441 ( .IN1(n2323), .IN2(n2324), .QN(n2218) );
AND2X1 U1442 ( .IN1(n2323), .IN2(n2324), .Q(n2217) );
AO21X1 U1443 ( .IN1(\fpu_add_frac_dp/n2303 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2325), .Q(n2324) );
MUX21X1 U1444 ( .IN1(n1325), .IN2(n64), .S(\fpu_add_frac_dp/n2356 ), .Q(
n2325) );
AO22X1 U1445 ( .IN1(n2214), .IN2(n2213), .IN3(n2326), .IN4(n234), .Q(n2323)
);
OR2X1 U1446 ( .IN1(n2214), .IN2(n2213), .Q(n2326) );
AO21X1 U1447 ( .IN1(\fpu_add_frac_dp/n2356 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2327), .Q(n2213) );
MUX21X1 U1448 ( .IN1(n1324), .IN2(n1328), .S(\fpu_add_frac_dp/n2508 ), .Q(
n2327) );
AO22X1 U1449 ( .IN1(n2211), .IN2(n2210), .IN3(n2328), .IN4(n235), .Q(n2214)
);
OR2X1 U1450 ( .IN1(n2211), .IN2(n2210), .Q(n2328) );
AO21X1 U1451 ( .IN1(\fpu_add_frac_dp/n2508 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2329), .Q(n2210) );
MUX21X1 U1452 ( .IN1(n1323), .IN2(n1327), .S(\fpu_add_frac_dp/n2504 ), .Q(
n2329) );
AO22X1 U1453 ( .IN1(n2330), .IN2(n2331), .IN3(n2332), .IN4(n236), .Q(n2211)
);
NAND2X0 U1454 ( .IN1(n2207), .IN2(n2208), .QN(n2332) );
INVX0 U1455 ( .INP(n2330), .ZN(n2208) );
INVX0 U1456 ( .INP(n2331), .ZN(n2207) );
AO21X1 U1457 ( .IN1(\fpu_add_frac_dp/n2504 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2333), .Q(n2331) );
MUX21X1 U1458 ( .IN1(n155), .IN2(n64), .S(\fpu_add_frac_dp/n2276 ), .Q(n2333) );
OA21X1 U1459 ( .IN1(n199), .IN2(n2204), .IN3(n2334), .Q(n2330) );
INVX0 U1460 ( .INP(n2205), .ZN(n2334) );
NOR2X0 U1461 ( .IN1(n2335), .IN2(n2336), .QN(n2205) );
AND2X1 U1462 ( .IN1(n2335), .IN2(n2336), .Q(n2204) );
AO21X1 U1463 ( .IN1(\fpu_add_frac_dp/n2276 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2337), .Q(n2336) );
MUX21X1 U1464 ( .IN1(n1325), .IN2(n1328), .S(\fpu_add_frac_dp/n2302 ), .Q(
n2337) );
AO22X1 U1465 ( .IN1(n2201), .IN2(n2200), .IN3(n2338), .IN4(n237), .Q(n2335)
);
OR2X1 U1466 ( .IN1(n2201), .IN2(n2200), .Q(n2338) );
AO21X1 U1467 ( .IN1(\fpu_add_frac_dp/n2302 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2339), .Q(n2200) );
MUX21X1 U1468 ( .IN1(n1324), .IN2(n1327), .S(\fpu_add_frac_dp/n2422 ), .Q(
n2339) );
AO22X1 U1469 ( .IN1(n2340), .IN2(n2341), .IN3(n2342), .IN4(n259), .Q(n2201)
);
NAND2X0 U1470 ( .IN1(n2197), .IN2(n2198), .QN(n2342) );
INVX0 U1471 ( .INP(n2340), .ZN(n2198) );
INVX0 U1472 ( .INP(n2341), .ZN(n2197) );
AO21X1 U1473 ( .IN1(\fpu_add_frac_dp/n2422 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2343), .Q(n2341) );
MUX21X1 U1474 ( .IN1(n1323), .IN2(n64), .S(\fpu_add_frac_dp/n2355 ), .Q(
n2343) );
OA21X1 U1475 ( .IN1(n200), .IN2(n2194), .IN3(n2344), .Q(n2340) );
INVX0 U1476 ( .INP(n2195), .ZN(n2344) );
NOR2X0 U1477 ( .IN1(n2345), .IN2(n2346), .QN(n2195) );
AND2X1 U1478 ( .IN1(n2345), .IN2(n2346), .Q(n2194) );
AO21X1 U1479 ( .IN1(\fpu_add_frac_dp/n2355 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2347), .Q(n2346) );
MUX21X1 U1480 ( .IN1(n155), .IN2(n1328), .S(\fpu_add_frac_dp/n2275 ), .Q(
n2347) );
AO22X1 U1481 ( .IN1(n2348), .IN2(n2349), .IN3(n2350), .IN4(n238), .Q(n2345)
);
NAND2X0 U1482 ( .IN1(n2190), .IN2(n2191), .QN(n2350) );
INVX0 U1483 ( .INP(n2348), .ZN(n2191) );
INVX0 U1484 ( .INP(n2349), .ZN(n2190) );
AO21X1 U1485 ( .IN1(\fpu_add_frac_dp/n2275 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2351), .Q(n2349) );
MUX21X1 U1486 ( .IN1(n1325), .IN2(n1327), .S(\fpu_add_frac_dp/n2301 ), .Q(
n2351) );
OA21X1 U1487 ( .IN1(n201), .IN2(n2187), .IN3(n2352), .Q(n2348) );
INVX0 U1488 ( .INP(n2188), .ZN(n2352) );
NOR2X0 U1489 ( .IN1(n2353), .IN2(n2354), .QN(n2188) );
AND2X1 U1490 ( .IN1(n2353), .IN2(n2354), .Q(n2187) );
AO21X1 U1491 ( .IN1(\fpu_add_frac_dp/n2301 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2355), .Q(n2354) );
MUX21X1 U1492 ( .IN1(n1324), .IN2(n64), .S(\fpu_add_frac_dp/n2421 ), .Q(
n2355) );
AO22X1 U1493 ( .IN1(n2356), .IN2(n2357), .IN3(n2358), .IN4(n239), .Q(n2353)
);
NAND2X0 U1494 ( .IN1(n2183), .IN2(n2184), .QN(n2358) );
INVX0 U1495 ( .INP(n2356), .ZN(n2184) );
INVX0 U1496 ( .INP(n2357), .ZN(n2183) );
AO21X1 U1497 ( .IN1(\fpu_add_frac_dp/n2421 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2359), .Q(n2357) );
MUX21X1 U1498 ( .IN1(n1323), .IN2(n1328), .S(\fpu_add_frac_dp/n2511 ), .Q(
n2359) );
OA21X1 U1499 ( .IN1(n202), .IN2(n2180), .IN3(n2360), .Q(n2356) );
INVX0 U1500 ( .INP(n2181), .ZN(n2360) );
NOR2X0 U1501 ( .IN1(n2361), .IN2(n2362), .QN(n2181) );
AND2X1 U1502 ( .IN1(n2361), .IN2(n2362), .Q(n2180) );
AO21X1 U1503 ( .IN1(\fpu_add_frac_dp/n2511 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2363), .Q(n2362) );
MUX21X1 U1504 ( .IN1(n155), .IN2(n1327), .S(\fpu_add_frac_dp/n2435 ), .Q(
n2363) );
AO22X1 U1505 ( .IN1(n2177), .IN2(n2176), .IN3(n2364), .IN4(n240), .Q(n2361)
);
OR2X1 U1506 ( .IN1(n2177), .IN2(n2176), .Q(n2364) );
AO21X1 U1507 ( .IN1(\fpu_add_frac_dp/n2435 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2365), .Q(n2176) );
MUX21X1 U1508 ( .IN1(n1325), .IN2(n64), .S(\fpu_add_frac_dp/n2354 ), .Q(
n2365) );
AO22X1 U1509 ( .IN1(n2174), .IN2(n2173), .IN3(n2366), .IN4(n241), .Q(n2177)
);
OR2X1 U1510 ( .IN1(n2174), .IN2(n2173), .Q(n2366) );
AO21X1 U1511 ( .IN1(\fpu_add_frac_dp/n2354 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2367), .Q(n2173) );
MUX21X1 U1512 ( .IN1(n1324), .IN2(n1328), .S(\fpu_add_frac_dp/n2274 ), .Q(
n2367) );
AO22X1 U1513 ( .IN1(n2171), .IN2(n2170), .IN3(n2368), .IN4(n242), .Q(n2174)
);
OR2X1 U1514 ( .IN1(n2171), .IN2(n2170), .Q(n2368) );
AO21X1 U1515 ( .IN1(\fpu_add_frac_dp/n2274 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2369), .Q(n2170) );
MUX21X1 U1516 ( .IN1(n1323), .IN2(n1327), .S(\fpu_add_frac_dp/n2300 ), .Q(
n2369) );
AO22X1 U1517 ( .IN1(n2370), .IN2(n2371), .IN3(n2372), .IN4(n243), .Q(n2171)
);
NAND2X0 U1518 ( .IN1(n2167), .IN2(n2168), .QN(n2372) );
INVX0 U1519 ( .INP(n2370), .ZN(n2168) );
INVX0 U1520 ( .INP(n2371), .ZN(n2167) );
AO21X1 U1521 ( .IN1(\fpu_add_frac_dp/n2300 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2373), .Q(n2371) );
MUX21X1 U1522 ( .IN1(n155), .IN2(n64), .S(\fpu_add_frac_dp/n2510 ), .Q(n2373) );
OA21X1 U1523 ( .IN1(n203), .IN2(n2164), .IN3(n2374), .Q(n2370) );
INVX0 U1524 ( .INP(n2165), .ZN(n2374) );
NOR2X0 U1525 ( .IN1(n2375), .IN2(n2376), .QN(n2165) );
AND2X1 U1526 ( .IN1(n2375), .IN2(n2376), .Q(n2164) );
AO21X1 U1527 ( .IN1(\fpu_add_frac_dp/n2510 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2377), .Q(n2376) );
MUX21X1 U1528 ( .IN1(n1325), .IN2(n1328), .S(\fpu_add_frac_dp/n2503 ), .Q(
n2377) );
AO22X1 U1529 ( .IN1(n2161), .IN2(n2160), .IN3(n2378), .IN4(n244), .Q(n2375)
);
OR2X1 U1530 ( .IN1(n2161), .IN2(n2160), .Q(n2378) );
AO21X1 U1531 ( .IN1(\fpu_add_frac_dp/n2503 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2379), .Q(n2160) );
MUX21X1 U1532 ( .IN1(n1324), .IN2(n1327), .S(\fpu_add_frac_dp/n2499 ), .Q(
n2379) );
AO22X1 U1533 ( .IN1(n2380), .IN2(n2381), .IN3(n2382), .IN4(n245), .Q(n2161)
);
NAND2X0 U1534 ( .IN1(n2157), .IN2(n2158), .QN(n2382) );
INVX0 U1535 ( .INP(n2380), .ZN(n2158) );
INVX0 U1536 ( .INP(n2381), .ZN(n2157) );
AO21X1 U1537 ( .IN1(\fpu_add_frac_dp/n2499 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2383), .Q(n2381) );
MUX21X1 U1538 ( .IN1(n1323), .IN2(n64), .S(\fpu_add_frac_dp/n2507 ), .Q(
n2383) );
OA21X1 U1539 ( .IN1(n204), .IN2(n2154), .IN3(n2384), .Q(n2380) );
INVX0 U1540 ( .INP(n2155), .ZN(n2384) );
NOR2X0 U1541 ( .IN1(n2385), .IN2(n2386), .QN(n2155) );
AND2X1 U1542 ( .IN1(n2385), .IN2(n2386), .Q(n2154) );
AO21X1 U1543 ( .IN1(\fpu_add_frac_dp/n2507 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2387), .Q(n2386) );
MUX21X1 U1544 ( .IN1(n155), .IN2(n1328), .S(\fpu_add_frac_dp/n2419 ), .Q(
n2387) );
AO22X1 U1545 ( .IN1(n2151), .IN2(n2150), .IN3(n2388), .IN4(n246), .Q(n2385)
);
OR2X1 U1546 ( .IN1(n2151), .IN2(n2150), .Q(n2388) );
AO21X1 U1547 ( .IN1(\fpu_add_frac_dp/n2419 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2389), .Q(n2150) );
MUX21X1 U1548 ( .IN1(n1325), .IN2(n1327), .S(\fpu_add_frac_dp/n2299 ), .Q(
n2389) );
AO22X1 U1549 ( .IN1(n2148), .IN2(n2147), .IN3(n2390), .IN4(n247), .Q(n2151)
);
OR2X1 U1550 ( .IN1(n2148), .IN2(n2147), .Q(n2390) );
AO21X1 U1551 ( .IN1(\fpu_add_frac_dp/n2299 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2391), .Q(n2147) );
MUX21X1 U1552 ( .IN1(n1324), .IN2(n64), .S(\fpu_add_frac_dp/n2420 ), .Q(
n2391) );
AO22X1 U1553 ( .IN1(n2145), .IN2(n2144), .IN3(n2392), .IN4(n248), .Q(n2148)
);
OR2X1 U1554 ( .IN1(n2145), .IN2(n2144), .Q(n2392) );
AO21X1 U1555 ( .IN1(\fpu_add_frac_dp/n2420 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2393), .Q(n2144) );
MUX21X1 U1556 ( .IN1(n1323), .IN2(n1328), .S(\fpu_add_frac_dp/n2273 ), .Q(
n2393) );
AO22X1 U1557 ( .IN1(n2142), .IN2(n2394), .IN3(n2395), .IN4(n318), .Q(n2145)
);
NAND2X0 U1558 ( .IN1(n2396), .IN2(n2141), .QN(n2395) );
INVX0 U1559 ( .INP(n2394), .ZN(n2141) );
AO21X1 U1560 ( .IN1(\fpu_add_frac_dp/n2273 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2397), .Q(n2394) );
MUX21X1 U1561 ( .IN1(n155), .IN2(n1327), .S(\fpu_add_frac_dp/n2352 ), .Q(
n2397) );
INVX0 U1562 ( .INP(n2396), .ZN(n2142) );
OA22X1 U1563 ( .IN1(n2139), .IN2(n2138), .IN3(n2398), .IN4(
\fpu_add_frac_dp/n815 ), .Q(n2396) );
AND2X1 U1564 ( .IN1(n2138), .IN2(n2139), .Q(n2398) );
AOI21X1 U1565 ( .IN1(\fpu_add_frac_dp/n2352 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2399), .QN(n2138) );
MUX21X1 U1566 ( .IN1(n1325), .IN2(n64), .S(\fpu_add_frac_dp/n2353 ), .Q(
n2399) );
AO21X1 U1567 ( .IN1(\fpu_add_frac_dp/n816 ), .IN2(n2136), .IN3(n2135), .Q(
n2139) );
NOR2X0 U1568 ( .IN1(n2400), .IN2(n2401), .QN(n2135) );
AOI21X1 U1569 ( .IN1(\fpu_add_frac_dp/n817 ), .IN2(n2130), .IN3(n2402), .QN(
n2401) );
NAND3X0 U1570 ( .IN1(n2400), .IN2(n2131), .IN3(n2403), .QN(n2136) );
NAND2X0 U1571 ( .IN1(\fpu_add_frac_dp/n817 ), .IN2(n2130), .QN(n2403) );
NAND2X0 U1572 ( .IN1(n2404), .IN2(n2405), .QN(n2130) );
INVX0 U1573 ( .INP(n2402), .ZN(n2131) );
NOR2X0 U1574 ( .IN1(n2404), .IN2(n2405), .QN(n2402) );
AO21X1 U1575 ( .IN1(\fpu_add_frac_dp/n2434 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2406), .Q(n2405) );
MUX21X1 U1576 ( .IN1(n1324), .IN2(n1328), .S(\fpu_add_frac_dp/n2433 ), .Q(
n2406) );
AO22X1 U1577 ( .IN1(n2127), .IN2(n2126), .IN3(n2407), .IN4(n249), .Q(n2404)
);
OR2X1 U1578 ( .IN1(n2127), .IN2(n2126), .Q(n2407) );
AO21X1 U1579 ( .IN1(\fpu_add_frac_dp/n2433 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2408), .Q(n2126) );
MUX21X1 U1580 ( .IN1(n1323), .IN2(n1327), .S(\fpu_add_frac_dp/n2297 ), .Q(
n2408) );
AO22X1 U1581 ( .IN1(n2124), .IN2(n2123), .IN3(n2409), .IN4(n250), .Q(n2127)
);
OR2X1 U1582 ( .IN1(n2124), .IN2(n2123), .Q(n2409) );
AO21X1 U1583 ( .IN1(\fpu_add_frac_dp/n2297 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2410), .Q(n2123) );
MUX21X1 U1584 ( .IN1(n155), .IN2(n64), .S(\fpu_add_frac_dp/n2272 ), .Q(n2410) );
AO22X1 U1585 ( .IN1(n2121), .IN2(n2120), .IN3(n2411), .IN4(n251), .Q(n2124)
);
OR2X1 U1586 ( .IN1(n2120), .IN2(n2121), .Q(n2411) );
AO21X1 U1587 ( .IN1(\fpu_add_frac_dp/n2272 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2412), .Q(n2120) );
MUX21X1 U1588 ( .IN1(n1325), .IN2(n1328), .S(\fpu_add_frac_dp/n2298 ), .Q(
n2412) );
OA22X1 U1589 ( .IN1(n179), .IN2(n2413), .IN3(n2117), .IN4(n2116), .Q(n2121)
);
INVX0 U1590 ( .INP(n2118), .ZN(n2413) );
NAND2X0 U1591 ( .IN1(n2116), .IN2(n2117), .QN(n2118) );
AO21X1 U1592 ( .IN1(\fpu_add_frac_dp/n2298 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2414), .Q(n2117) );
MUX21X1 U1593 ( .IN1(n1324), .IN2(n1327), .S(\fpu_add_frac_dp/n2359 ), .Q(
n2414) );
AOI21X1 U1594 ( .IN1(\fpu_add_frac_dp/n822 ), .IN2(n2113), .IN3(n2112), .QN(
n2116) );
NOR2X0 U1595 ( .IN1(n2415), .IN2(n2416), .QN(n2112) );
OA21X1 U1596 ( .IN1(n180), .IN2(n2417), .IN3(n2108), .Q(n2416) );
NAND3X0 U1597 ( .IN1(n2415), .IN2(n2108), .IN3(n2418), .QN(n2113) );
NAND2X0 U1598 ( .IN1(\fpu_add_frac_dp/n823 ), .IN2(n2107), .QN(n2418) );
INVX0 U1599 ( .INP(n2417), .ZN(n2107) );
NOR2X0 U1600 ( .IN1(n2419), .IN2(n2420), .QN(n2417) );
NAND2X0 U1601 ( .IN1(n2420), .IN2(n2419), .QN(n2108) );
NAND2X0 U1602 ( .IN1(n2101), .IN2(n2104), .QN(n2419) );
NAND2X0 U1603 ( .IN1(\fpu_add_frac_dp/n824 ), .IN2(n2103), .QN(n2104) );
NAND2X0 U1604 ( .IN1(n2421), .IN2(n2422), .QN(n2103) );
OR2X1 U1605 ( .IN1(n2422), .IN2(n2421), .Q(n2101) );
AO21X1 U1606 ( .IN1(\fpu_add_frac_dp/n2362 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2423), .Q(n2421) );
MUX21X1 U1607 ( .IN1(n1323), .IN2(n64), .S(\fpu_add_frac_dp/n2304 ), .Q(
n2423) );
AO22X1 U1608 ( .IN1(n2098), .IN2(n2097), .IN3(n2424), .IN4(n252), .Q(n2422)
);
OR2X1 U1609 ( .IN1(n2098), .IN2(n2097), .Q(n2424) );
AO21X1 U1610 ( .IN1(\fpu_add_frac_dp/n2304 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2425), .Q(n2097) );
MUX21X1 U1611 ( .IN1(n1327), .IN2(n1325), .S(\fpu_add_frac_dp/n2389 ), .Q(
n2425) );
AO22X1 U1612 ( .IN1(n2095), .IN2(n2094), .IN3(n2426), .IN4(n253), .Q(n2098)
);
OR2X1 U1613 ( .IN1(n2095), .IN2(n2094), .Q(n2426) );
AO21X1 U1614 ( .IN1(\fpu_add_frac_dp/n2369 ), .IN2(n904), .IN3(n2427), .Q(
n2094) );
MUX21X1 U1615 ( .IN1(n155), .IN2(n1328), .S(\fpu_add_frac_dp/n2277 ), .Q(
n2427) );
AO22X1 U1616 ( .IN1(n2092), .IN2(n2091), .IN3(n2428), .IN4(n260), .Q(n2095)
);
OR2X1 U1617 ( .IN1(n2092), .IN2(n2091), .Q(n2428) );
AO21X1 U1618 ( .IN1(\fpu_add_frac_dp/n2277 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2429), .Q(n2091) );
MUX21X1 U1619 ( .IN1(n1325), .IN2(n1326), .S(\fpu_add_frac_dp/n2531 ), .Q(
n2429) );
AO22X1 U1620 ( .IN1(n2089), .IN2(n2088), .IN3(n2430), .IN4(n261), .Q(n2092)
);
OR2X1 U1621 ( .IN1(n2089), .IN2(n2088), .Q(n2430) );
AO21X1 U1622 ( .IN1(\fpu_add_frac_dp/n2531 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2431), .Q(n2088) );
MUX21X1 U1623 ( .IN1(n1324), .IN2(n1326), .S(\fpu_add_frac_dp/n2530 ), .Q(
n2431) );
AO22X1 U1624 ( .IN1(n2086), .IN2(n2085), .IN3(n2432), .IN4(n224), .Q(n2089)
);
OR2X1 U1625 ( .IN1(n2085), .IN2(n2086), .Q(n2432) );
AO21X1 U1626 ( .IN1(\fpu_add_frac_dp/n2530 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2433), .Q(n2085) );
MUX21X1 U1627 ( .IN1(n1323), .IN2(n1326), .S(\fpu_add_frac_dp/n2529 ), .Q(
n2433) );
OA22X1 U1628 ( .IN1(n2082), .IN2(n2083), .IN3(n222), .IN4(n2434), .Q(n2086)
);
AND2X1 U1629 ( .IN1(n2083), .IN2(n2082), .Q(n2434) );
AO22X1 U1630 ( .IN1(n2080), .IN2(n2079), .IN3(n2435), .IN4(n225), .Q(n2083)
);
OR2X1 U1631 ( .IN1(n2079), .IN2(n2080), .Q(n2435) );
AO21X1 U1632 ( .IN1(\fpu_add_frac_dp/n2528 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2436), .Q(n2079) );
MUX21X1 U1633 ( .IN1(n155), .IN2(n1326), .S(\fpu_add_frac_dp/n2527 ), .Q(
n2436) );
OA22X1 U1634 ( .IN1(n2076), .IN2(n2077), .IN3(n223), .IN4(n2437), .Q(n2080)
);
AND2X1 U1635 ( .IN1(n2077), .IN2(n2076), .Q(n2437) );
OAI22X1 U1636 ( .IN1(n2074), .IN2(n2073), .IN3(n2438), .IN4(
\fpu_add_frac_dp/n833 ), .QN(n2077) );
AND2X1 U1637 ( .IN1(n2073), .IN2(n2074), .Q(n2438) );
AOI21X1 U1638 ( .IN1(\fpu_add_frac_dp/n2526 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2439), .QN(n2073) );
MUX21X1 U1639 ( .IN1(n1325), .IN2(n1326), .S(\fpu_add_frac_dp/n2525 ), .Q(
n2439) );
AO22X1 U1640 ( .IN1(n2070), .IN2(n2071), .IN3(\fpu_add_frac_dp/n834 ), .IN4(
n2440), .Q(n2074) );
NAND2X0 U1641 ( .IN1(n2441), .IN2(n2442), .QN(n2440) );
INVX0 U1642 ( .INP(n2441), .ZN(n2071) );
OA21X1 U1643 ( .IN1(n220), .IN2(n2067), .IN3(n2443), .Q(n2441) );
INVX0 U1644 ( .INP(n2068), .ZN(n2443) );
NOR2X0 U1645 ( .IN1(n2444), .IN2(n2445), .QN(n2068) );
AND2X1 U1646 ( .IN1(n2444), .IN2(n2445), .Q(n2067) );
AO21X1 U1647 ( .IN1(\fpu_add_frac_dp/n2524 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2446), .Q(n2445) );
MUX21X1 U1648 ( .IN1(n1324), .IN2(n1326), .S(\fpu_add_frac_dp/n2523 ), .Q(
n2446) );
AO22X1 U1649 ( .IN1(n2064), .IN2(n2063), .IN3(n2447), .IN4(n625), .Q(n2444)
);
OR2X1 U1650 ( .IN1(n2064), .IN2(n2063), .Q(n2447) );
AO21X1 U1651 ( .IN1(\fpu_add_frac_dp/n2523 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2448), .Q(n2063) );
MUX21X1 U1652 ( .IN1(n1323), .IN2(n1326), .S(\fpu_add_frac_dp/n2522 ), .Q(
n2448) );
AO22X1 U1653 ( .IN1(n2061), .IN2(n307), .IN3(n2449), .IN4(n926), .Q(n2064)
);
OR2X1 U1654 ( .IN1(n2061), .IN2(n307), .Q(n2449) );
AO21X1 U1655 ( .IN1(\fpu_add_frac_dp/n2522 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2450), .Q(n2061) );
MUX21X1 U1656 ( .IN1(n155), .IN2(n1326), .S(\fpu_add_frac_dp/n2539 ), .Q(
n2450) );
INVX0 U1657 ( .INP(n2442), .ZN(n2070) );
AO21X1 U1658 ( .IN1(\fpu_add_frac_dp/n2525 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2451), .Q(n2442) );
MUX21X1 U1659 ( .IN1(n1325), .IN2(n1326), .S(\fpu_add_frac_dp/n2524 ), .Q(
n2451) );
AO21X1 U1660 ( .IN1(\fpu_add_frac_dp/n2527 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2452), .Q(n2076) );
MUX21X1 U1661 ( .IN1(n1324), .IN2(n1326), .S(\fpu_add_frac_dp/n2526 ), .Q(
n2452) );
AO21X1 U1662 ( .IN1(\fpu_add_frac_dp/n2529 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2453), .Q(n2082) );
MUX21X1 U1663 ( .IN1(n1323), .IN2(n1326), .S(\fpu_add_frac_dp/n2528 ), .Q(
n2453) );
AOI21X1 U1664 ( .IN1(\fpu_add_frac_dp/n2432 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2454), .QN(n2420) );
MUX21X1 U1665 ( .IN1(n155), .IN2(n1326), .S(\fpu_add_frac_dp/n2362 ), .Q(
n2454) );
AO21X1 U1666 ( .IN1(\fpu_add_frac_dp/n2359 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2455), .Q(n2415) );
MUX21X1 U1667 ( .IN1(n1325), .IN2(n1326), .S(\fpu_add_frac_dp/n2432 ), .Q(
n2455) );
AO21X1 U1668 ( .IN1(\fpu_add_frac_dp/n2353 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2456), .Q(n2400) );
MUX21X1 U1669 ( .IN1(n1323), .IN2(n1326), .S(\fpu_add_frac_dp/n2434 ), .Q(
n2456) );
INVX0 U1670 ( .INP(n2297), .ZN(n2249) );
AO21X1 U1671 ( .IN1(\fpu_add_frac_dp/n2369 ), .IN2(n62), .IN3(n2457), .Q(
n2297) );
MUX21X1 U1672 ( .IN1(n155), .IN2(n1326), .S(\fpu_add_frac_dp/n2357 ), .Q(
n2457) );
AOI21X1 U1673 ( .IN1(\fpu_add_frac_dp/n2369 ), .IN2(n153), .IN3(n2458), .QN(
n2260) );
MUX21X1 U1674 ( .IN1(n64), .IN2(n1324), .S(\fpu_add_frac_dp/n2390 ), .Q(
n2458) );
INVX0 U1675 ( .INP(n2281), .ZN(n2273) );
AO21X1 U1676 ( .IN1(\fpu_add_frac_dp/n2498 ), .IN2(\fpu_add_frac_dp/n2369 ),
.IN3(n2459), .Q(n2281) );
MUX21X1 U1677 ( .IN1(n1325), .IN2(n1326), .S(\fpu_add_frac_dp/n2502 ), .Q(
n2459) );
AO222X1 U1678 ( .IN1(n2460), .IN2(n583), .IN3(n1322), .IN4(n2461), .IN5(
n1388), .IN6(n154), .Q(\fpu_add_frac_dp/n3666 ) );
OAI222X1 U1679 ( .IN1(n2462), .IN2(n2463), .IN3(n2464), .IN4(n2465), .IN5(
n2466), .IN6(n2467), .QN(n2461) );
INVX0 U1680 ( .INP(n2468), .ZN(n2467) );
OA221X1 U1681 ( .IN1(n2469), .IN2(n40), .IN3(n2470), .IN4(n2471), .IN5(n2472), .Q(n2466) );
OA21X1 U1682 ( .IN1(n2473), .IN2(n2474), .IN3(n2475), .Q(n2472) );
NAND4X0 U1683 ( .IN1(n2476), .IN2(\fpu_add_frac_dp/n2537 ), .IN3(n2477),
.IN4(n2478), .QN(n2475) );
OA21X1 U1684 ( .IN1(\fpu_add_frac_dp/n2361 ), .IN2(n38), .IN3(n2479), .Q(
n2477) );
AO21X1 U1685 ( .IN1(\fpu_add_frac_dp/n2342 ), .IN2(n1271), .IN3(n2480), .Q(
n2474) );
AO21X1 U1686 ( .IN1(\fpu_add_frac_dp/n2336 ), .IN2(n177), .IN3(n19), .Q(
n2471) );
OA21X1 U1687 ( .IN1(\fpu_add_frac_dp/n5609 ), .IN2(n100), .IN3(
\fpu_add_frac_dp/n5632 ), .Q(n2469) );
NAND2X0 U1688 ( .IN1(n2481), .IN2(n2482), .QN(n2465) );
AO221X1 U1689 ( .IN1(n2483), .IN2(n2484), .IN3(n2485), .IN4(n2486), .IN5(
n2487), .Q(n2482) );
NOR4X0 U1690 ( .IN1(\fpu_add_frac_dp/n2313 ), .IN2(n2488), .IN3(n2489),
.IN4(n2490), .QN(n2487) );
OA21X1 U1691 ( .IN1(n2491), .IN2(n74), .IN3(n2492), .Q(n2489) );
OA21X1 U1692 ( .IN1(\fpu_add_frac_dp/n2405 ), .IN2(n447), .IN3(
\fpu_add_frac_dp/n662 ), .Q(n2491) );
NOR2X0 U1693 ( .IN1(\fpu_add_frac_dp/n2402 ), .IN2(\fpu_add_frac_dp/n2470 ),
.QN(n2488) );
NAND2X0 U1694 ( .IN1(\fpu_add_frac_dp/n2344 ), .IN2(n43), .QN(n2486) );
INVX0 U1695 ( .INP(n2493), .ZN(n2485) );
NAND2X0 U1696 ( .IN1(\fpu_add_frac_dp/n2363 ), .IN2(n101), .QN(n2484) );
NOR2X0 U1697 ( .IN1(\fpu_add_frac_dp/n2335 ), .IN2(n2494), .QN(n2483) );
OA221X1 U1698 ( .IN1(n2495), .IN2(n2496), .IN3(n33), .IN4(n2497), .IN5(n2498), .Q(n2464) );
OA21X1 U1699 ( .IN1(\fpu_add_frac_dp/n2400 ), .IN2(n2499), .IN3(n2500), .Q(
n2498) );
AOI21X1 U1700 ( .IN1(n37), .IN2(\fpu_add_frac_dp/n2437 ), .IN3(
\fpu_add_frac_dp/n2330 ), .QN(n2499) );
OAI21X1 U1701 ( .IN1(n2501), .IN2(n173), .IN3(n2502), .QN(n2497) );
OA21X1 U1702 ( .IN1(n2503), .IN2(n90), .IN3(\fpu_add_frac_dp/n2520 ), .Q(
n2501) );
OA21X1 U1703 ( .IN1(\fpu_add_frac_dp/n5642 ), .IN2(n282), .IN3(
\fpu_add_frac_dp/n670 ), .Q(n2503) );
OA21X1 U1704 ( .IN1(\fpu_add_frac_dp/n666 ), .IN2(n34), .IN3(
\fpu_add_frac_dp/n5610 ), .Q(n2495) );
OA221X1 U1705 ( .IN1(n2504), .IN2(n87), .IN3(n2505), .IN4(n2506), .IN5(n2507), .Q(n2463) );
OA21X1 U1706 ( .IN1(n2508), .IN2(n2509), .IN3(n2510), .Q(n2507) );
NAND4X0 U1707 ( .IN1(n2511), .IN2(\fpu_add_frac_dp/n2394 ), .IN3(n2512),
.IN4(n2513), .QN(n2510) );
NAND2X0 U1708 ( .IN1(\fpu_add_frac_dp/n2343 ), .IN2(\fpu_add_frac_dp/n654 ),
.QN(n2512) );
NOR2X0 U1709 ( .IN1(\fpu_add_frac_dp/n2386 ), .IN2(n22), .QN(n2508) );
OA21X1 U1710 ( .IN1(\fpu_add_frac_dp/n2416 ), .IN2(n92), .IN3(
\fpu_add_frac_dp/n2290 ), .Q(n2505) );
OA21X1 U1711 ( .IN1(n94), .IN2(n654), .IN3(\fpu_add_frac_dp/n5618 ), .Q(
n2504) );
AO222X1 U1712 ( .IN1(n2460), .IN2(n72), .IN3(n1321), .IN4(n2514), .IN5(n1388), .IN6(n582), .Q(\fpu_add_frac_dp/n3665 ) );
AO221X1 U1713 ( .IN1(n2515), .IN2(n2516), .IN3(n2468), .IN4(n2517), .IN5(
n2518), .Q(n2514) );
NAND2X0 U1714 ( .IN1(n2519), .IN2(n2520), .QN(n2518) );
NAND4X0 U1715 ( .IN1(n2521), .IN2(\fpu_add_frac_dp/n2363 ), .IN3(n2522),
.IN4(n839), .QN(n2520) );
NAND2X0 U1716 ( .IN1(n2494), .IN2(n2523), .QN(n2522) );
NAND3X0 U1717 ( .IN1(n346), .IN2(n710), .IN3(n2524), .QN(n2523) );
NAND2X0 U1718 ( .IN1(n2492), .IN2(n2525), .QN(n2524) );
NAND3X0 U1719 ( .IN1(\fpu_add_frac_dp/n2409 ), .IN2(n2526), .IN3(
\fpu_add_frac_dp/n662 ), .QN(n2525) );
NAND3X0 U1720 ( .IN1(n447), .IN2(n1087), .IN3(n2527), .QN(n2526) );
NAND2X0 U1721 ( .IN1(\fpu_add_frac_dp/n2344 ), .IN2(\fpu_add_frac_dp/n2411 ),
.QN(n2527) );
AO21X1 U1722 ( .IN1(n2528), .IN2(n2529), .IN3(n2462), .Q(n2519) );
NAND3X0 U1723 ( .IN1(n2530), .IN2(n2531), .IN3(\fpu_add_frac_dp/n2290 ),
.QN(n2529) );
NAND3X0 U1724 ( .IN1(\fpu_add_frac_dp/n2345 ), .IN2(n2532), .IN3(
\fpu_add_frac_dp/n2416 ), .QN(n2531) );
NAND2X0 U1725 ( .IN1(\fpu_add_frac_dp/n5631 ), .IN2(\fpu_add_frac_dp/n2378 ),
.QN(n2532) );
NAND3X0 U1726 ( .IN1(\fpu_add_frac_dp/n2440 ), .IN2(n2533), .IN3(
\fpu_add_frac_dp/n5618 ), .QN(n2528) );
NAND3X0 U1727 ( .IN1(n2534), .IN2(n654), .IN3(\fpu_add_frac_dp/n2288 ), .QN(
n2533) );
OR3X1 U1728 ( .IN1(n82), .IN2(n2535), .IN3(n171), .Q(n2534) );
AO222X1 U1729 ( .IN1(n2476), .IN2(n2536), .IN3(n2537), .IN4(n2538), .IN5(
n2539), .IN6(n2540), .Q(n2517) );
INVX0 U1730 ( .INP(n2470), .ZN(n2538) );
NAND3X0 U1731 ( .IN1(n2541), .IN2(n2542), .IN3(n2476), .QN(n2470) );
NAND3X0 U1732 ( .IN1(\fpu_add_frac_dp/n2336 ), .IN2(n716), .IN3(
\fpu_add_frac_dp/n659 ), .QN(n2542) );
NOR2X0 U1733 ( .IN1(n86), .IN2(n19), .QN(n2537) );
NAND2X0 U1734 ( .IN1(n2478), .IN2(n2543), .QN(n2536) );
NAND3X0 U1735 ( .IN1(\fpu_add_frac_dp/n2481 ), .IN2(n2479), .IN3(
\fpu_add_frac_dp/n2537 ), .QN(n2543) );
INVX0 U1736 ( .INP(n2544), .ZN(n2478) );
NAND3X0 U1737 ( .IN1(n2545), .IN2(n2546), .IN3(n2547), .QN(n2516) );
NAND3X0 U1738 ( .IN1(n2548), .IN2(n2549), .IN3(\fpu_add_frac_dp/n5610 ),
.QN(n2547) );
NAND3X0 U1739 ( .IN1(\fpu_add_frac_dp/n2494 ), .IN2(n2550), .IN3(
\fpu_add_frac_dp/n666 ), .QN(n2549) );
OR3X1 U1740 ( .IN1(n33), .IN2(n2551), .IN3(n173), .Q(n2550) );
INVX0 U1741 ( .INP(n2496), .ZN(n2548) );
OR3X1 U1742 ( .IN1(\fpu_add_frac_dp/n2330 ), .IN2(\fpu_add_frac_dp/n2400 ),
.IN3(n2552), .Q(n2545) );
AO222X1 U1743 ( .IN1(n2460), .IN2(n159), .IN3(n1319), .IN4(n2553), .IN5(
n1388), .IN6(n63), .Q(\fpu_add_frac_dp/n3664 ) );
NAND2X0 U1744 ( .IN1(n2554), .IN2(n2555), .QN(n2553) );
NAND3X0 U1745 ( .IN1(n2556), .IN2(n2557), .IN3(n2515), .QN(n2555) );
NAND2X0 U1746 ( .IN1(n2502), .IN2(n2558), .QN(n2557) );
NAND3X0 U1747 ( .IN1(\fpu_add_frac_dp/n2513 ), .IN2(n2551), .IN3(
\fpu_add_frac_dp/n668 ), .QN(n2558) );
MUX21X1 U1748 ( .IN1(n2559), .IN2(n2560), .S(n2481), .Q(n2554) );
NAND2X0 U1749 ( .IN1(n2561), .IN2(n2562), .QN(n2560) );
AO21X1 U1750 ( .IN1(n2563), .IN2(n2564), .IN3(n2565), .Q(n2562) );
OA22X1 U1751 ( .IN1(n2566), .IN2(n2567), .IN3(n2568), .IN4(n2569), .Q(n2559)
);
NOR4X0 U1752 ( .IN1(n2570), .IN2(n22), .IN3(n175), .IN4(n104), .QN(n2566) );
AO221X1 U1753 ( .IN1(n2571), .IN2(n2476), .IN3(n2539), .IN4(n716), .IN5(n85),
.Q(n2570) );
INVX0 U1754 ( .INP(n2473), .ZN(n2539) );
NOR2X0 U1755 ( .IN1(n2541), .IN2(n2544), .QN(n2571) );
AO222X1 U1756 ( .IN1(n2460), .IN2(n178), .IN3(n1322), .IN4(n2572), .IN5(
n1388), .IN6(n584), .Q(\fpu_add_frac_dp/n3663 ) );
NAND4X0 U1757 ( .IN1(n2573), .IN2(n2574), .IN3(n2575), .IN4(n2576), .QN(
n2572) );
NAND3X0 U1758 ( .IN1(n2561), .IN2(n2492), .IN3(n2521), .QN(n2576) );
NOR2X0 U1759 ( .IN1(n2577), .IN2(n2500), .QN(n2521) );
NAND3X0 U1760 ( .IN1(n2476), .IN2(n2541), .IN3(n2468), .QN(n2575) );
NAND3X0 U1761 ( .IN1(n2568), .IN2(n2578), .IN3(n2511), .QN(n2574) );
INVX0 U1762 ( .INP(n2569), .ZN(n2511) );
INVX0 U1763 ( .INP(n2513), .ZN(n2568) );
NAND2X0 U1764 ( .IN1(n2515), .IN2(n2502), .QN(n2573) );
AO222X1 U1765 ( .IN1(n2460), .IN2(n67), .IN3(n1321), .IN4(n2579), .IN5(n1388), .IN6(n762), .Q(\fpu_add_frac_dp/n3662 ) );
NAND3X0 U1766 ( .IN1(n2580), .IN2(n2581), .IN3(n2582), .QN(
\fpu_add_frac_dp/n3661 ) );
OR2X1 U1767 ( .IN1(n2046), .IN2(\fpu_add_frac_dp/n593 ), .Q(n2582) );
AO222X1 U1768 ( .IN1(n2583), .IN2(n67), .IN3(n2584), .IN4(n2579), .IN5(n1388), .IN6(n2), .Q(\fpu_add_frac_dp/n3660 ) );
AO222X1 U1769 ( .IN1(\fpu_add_exp_dp/n432 ), .IN2(n2583), .IN3(n2585), .IN4(
n2584), .IN5(n1379), .IN6(n2586), .Q(\fpu_add_frac_dp/n3659 ) );
INVX0 U1770 ( .INP(n2580), .ZN(n2584) );
NAND2X0 U1771 ( .IN1(n1320), .IN2(n2481), .QN(n2580) );
INVX0 U1772 ( .INP(n2577), .ZN(n2481) );
INVX0 U1773 ( .INP(n2581), .ZN(n2583) );
NAND2X0 U1774 ( .IN1(n2460), .IN2(n69), .QN(n2581) );
OAI22X1 U1775 ( .IN1(n2046), .IN2(\fpu_add_frac_dp/n5633 ), .IN3(n1745),
.IN4(n2587), .QN(\fpu_add_frac_dp/n3658 ) );
OAI22X1 U1776 ( .IN1(n2046), .IN2(\fpu_add_frac_dp/n589 ), .IN3(n1745),
.IN4(n2587), .QN(\fpu_add_frac_dp/n3657 ) );
MUX21X1 U1777 ( .IN1(n2588), .IN2(n2589), .S(n2590), .Q(n2587) );
NAND2X0 U1778 ( .IN1(\fpu_add_exp_dp/n433 ), .IN2(n67), .QN(n2589) );
NAND2X0 U1779 ( .IN1(n2579), .IN2(n2577), .QN(n2588) );
INVX0 U1780 ( .INP(n2585), .ZN(n2579) );
AO21X1 U1781 ( .IN1(n1397), .IN2(n2591), .IN3(n2592), .Q(
\fpu_add_frac_dp/n3656 ) );
AO21X1 U1782 ( .IN1(n1396), .IN2(n596), .IN3(n2592), .Q(
\fpu_add_frac_dp/n3655 ) );
AO21X1 U1783 ( .IN1(n1397), .IN2(n1144), .IN3(n2592), .Q(
\fpu_add_frac_dp/n3654 ) );
NAND2X0 U1784 ( .IN1(n2593), .IN2(n2594), .QN(n2592) );
NAND3X0 U1785 ( .IN1(n1320), .IN2(n2577), .IN3(n2585), .QN(n2594) );
NOR2X0 U1786 ( .IN1(n2468), .IN2(n2515), .QN(n2585) );
NOR2X0 U1787 ( .IN1(n2564), .IN2(n2577), .QN(n2515) );
INVX0 U1788 ( .INP(n2500), .ZN(n2564) );
NOR2X0 U1789 ( .IN1(n2493), .IN2(n2595), .QN(n2500) );
NOR2X0 U1790 ( .IN1(n2578), .IN2(n2596), .QN(n2468) );
NAND3X0 U1791 ( .IN1(\fpu_add_exp_dp/n432 ), .IN2(n2460), .IN3(
\fpu_add_exp_dp/n433 ), .QN(n2593) );
AO21X1 U1792 ( .IN1(n1396), .IN2(n641), .IN3(n2597), .Q(
\fpu_add_frac_dp/n3653 ) );
AO21X1 U1793 ( .IN1(n1397), .IN2(n166), .IN3(n2597), .Q(
\fpu_add_frac_dp/n3652 ) );
AO21X1 U1794 ( .IN1(n1396), .IN2(n1145), .IN3(n2598), .Q(
\fpu_add_frac_dp/n3651 ) );
AO21X1 U1795 ( .IN1(n1397), .IN2(n311), .IN3(n2598), .Q(
\fpu_add_frac_dp/n3650 ) );
AO21X1 U1796 ( .IN1(n1397), .IN2(n653), .IN3(n2599), .Q(
\fpu_add_frac_dp/n3649 ) );
AO21X1 U1797 ( .IN1(n1404), .IN2(n746), .IN3(n2599), .Q(
\fpu_add_frac_dp/n3648 ) );
AO22X1 U1798 ( .IN1(n1421), .IN2(n296), .IN3(n1442), .IN4(n2600), .Q(
\fpu_add_frac_dp/n3647 ) );
NAND2X0 U1799 ( .IN1(n2601), .IN2(n2602), .QN(n2600) );
AO21X1 U1800 ( .IN1(n1404), .IN2(n962), .IN3(n2597), .Q(
\fpu_add_frac_dp/n3646 ) );
AND2X1 U1801 ( .IN1(n1442), .IN2(n2603), .Q(n2597) );
AO221X1 U1802 ( .IN1(n2604), .IN2(n2605), .IN3(n2606), .IN4(n2058), .IN5(
n2607), .Q(n2603) );
AO21X1 U1803 ( .IN1(n2608), .IN2(n2609), .IN3(n2610), .Q(n2607) );
AO21X1 U1804 ( .IN1(n2057), .IN2(n2608), .IN3(a1stg_fsdtoix), .Q(n2606) );
NAND2X0 U1805 ( .IN1(n2052), .IN2(n2051), .QN(n2605) );
NAND2X0 U1806 ( .IN1(n2611), .IN2(n2612), .QN(n2051) );
AO21X1 U1807 ( .IN1(n1404), .IN2(n255), .IN3(n2598), .Q(
\fpu_add_frac_dp/n3645 ) );
AND2X1 U1808 ( .IN1(n1442), .IN2(n2613), .Q(n2598) );
AO221X1 U1809 ( .IN1(a1stg_fsdtoix), .IN2(n2614), .IN3(n2604), .IN4(n2615),
.IN5(n2616), .Q(n2613) );
AO21X1 U1810 ( .IN1(n2608), .IN2(n2617), .IN3(n2610), .Q(n2616) );
XOR3X1 U1811 ( .IN1(n2618), .IN2(n2619), .IN3(n2609), .Q(n2617) );
XOR3X1 U1812 ( .IN1(n2620), .IN2(n2621), .IN3(n2052), .Q(n2615) );
AO21X1 U1813 ( .IN1(n2619), .IN2(n2622), .IN3(n2623), .Q(n2614) );
AO21X1 U1814 ( .IN1(n1404), .IN2(n755), .IN3(n2599), .Q(
\fpu_add_frac_dp/n3644 ) );
AND2X1 U1815 ( .IN1(n1442), .IN2(n2624), .Q(n2599) );
AO221X1 U1816 ( .IN1(n2625), .IN2(n2604), .IN3(n2608), .IN4(n2626), .IN5(
n2627), .Q(n2624) );
AO21X1 U1817 ( .IN1(a1stg_fsdtoix), .IN2(n2628), .IN3(n2610), .Q(n2627) );
INVX0 U1818 ( .INP(n2629), .ZN(n2628) );
XOR3X1 U1819 ( .IN1(n2630), .IN2(n2631), .IN3(n2632), .Q(n2626) );
XOR3X1 U1820 ( .IN1(n2633), .IN2(n2634), .IN3(n2635), .Q(n2625) );
AO21X1 U1821 ( .IN1(n1404), .IN2(n693), .IN3(n2636), .Q(
\fpu_add_frac_dp/n3643 ) );
AO21X1 U1822 ( .IN1(\fpu_add_frac_dp/n2306 ), .IN2(n1415), .IN3(n2637), .Q(
\fpu_add_frac_dp/n3642 ) );
AO21X1 U1823 ( .IN1(n1404), .IN2(n2638), .IN3(n2639), .Q(
\fpu_add_frac_dp/n3641 ) );
AO21X1 U1824 ( .IN1(n1405), .IN2(n1063), .IN3(n2636), .Q(
\fpu_add_frac_dp/n3640 ) );
AO21X1 U1825 ( .IN1(\fpu_add_frac_dp/n2399 ), .IN2(n1415), .IN3(n2636), .Q(
\fpu_add_frac_dp/n3639 ) );
AO21X1 U1826 ( .IN1(n1405), .IN2(n581), .IN3(n2636), .Q(
\fpu_add_frac_dp/n3638 ) );
AO21X1 U1827 ( .IN1(\fpu_add_frac_dp/n2397 ), .IN2(n1416), .IN3(n2636), .Q(
\fpu_add_frac_dp/n3637 ) );
AO21X1 U1828 ( .IN1(\fpu_add_frac_dp/n2322 ), .IN2(n1415), .IN3(n2636), .Q(
\fpu_add_frac_dp/n3636 ) );
AND2X1 U1829 ( .IN1(n1443), .IN2(n2640), .Q(n2636) );
AO221X1 U1830 ( .IN1(a1stg_fsdtoix), .IN2(n2641), .IN3(n2608), .IN4(n2642),
.IN5(n2643), .Q(n2640) );
AO21X1 U1831 ( .IN1(n2644), .IN2(n2604), .IN3(n2610), .Q(n2643) );
XNOR3X1 U1832 ( .IN1(n2645), .IN2(n2646), .IN3(n2647), .Q(n2644) );
XOR3X1 U1833 ( .IN1(n2648), .IN2(n2649), .IN3(n2650), .Q(n2642) );
OR2X1 U1834 ( .IN1(n2651), .IN2(n2652), .Q(n2641) );
AO21X1 U1835 ( .IN1(n1405), .IN2(n1220), .IN3(n2637), .Q(
\fpu_add_frac_dp/n3635 ) );
AO21X1 U1836 ( .IN1(n1405), .IN2(n1221), .IN3(n2637), .Q(
\fpu_add_frac_dp/n3634 ) );
AO21X1 U1837 ( .IN1(n1405), .IN2(n1126), .IN3(n2637), .Q(
\fpu_add_frac_dp/n3633 ) );
AO21X1 U1838 ( .IN1(n1405), .IN2(n2653), .IN3(n2637), .Q(
\fpu_add_frac_dp/n3632 ) );
AO21X1 U1839 ( .IN1(\fpu_add_frac_dp/n2382 ), .IN2(n1416), .IN3(n2637), .Q(
\fpu_add_frac_dp/n3631 ) );
AND2X1 U1840 ( .IN1(n1442), .IN2(n2654), .Q(n2637) );
AO221X1 U1841 ( .IN1(a1stg_fsdtoix), .IN2(n2655), .IN3(n2608), .IN4(n2656),
.IN5(n2657), .Q(n2654) );
AO21X1 U1842 ( .IN1(n2658), .IN2(n2604), .IN3(n2610), .Q(n2657) );
XNOR3X1 U1843 ( .IN1(n2659), .IN2(n2660), .IN3(n2661), .Q(n2658) );
XOR3X1 U1844 ( .IN1(n2662), .IN2(n2663), .IN3(n2664), .Q(n2656) );
OR2X1 U1845 ( .IN1(n2665), .IN2(n2666), .Q(n2655) );
AO21X1 U1846 ( .IN1(n1405), .IN2(n47), .IN3(n2639), .Q(
\fpu_add_frac_dp/n3630 ) );
AO21X1 U1847 ( .IN1(n1405), .IN2(n5), .IN3(n2639), .Q(
\fpu_add_frac_dp/n3629 ) );
AO21X1 U1848 ( .IN1(n1405), .IN2(n1222), .IN3(n2639), .Q(
\fpu_add_frac_dp/n3628 ) );
AND2X1 U1849 ( .IN1(n1442), .IN2(n2667), .Q(n2639) );
AO21X1 U1850 ( .IN1(n1405), .IN2(n1124), .IN3(n1930), .Q(
\fpu_add_frac_dp/n3627 ) );
AO21X1 U1851 ( .IN1(n1405), .IN2(n118), .IN3(n1930), .Q(
\fpu_add_frac_dp/n3626 ) );
AO21X1 U1852 ( .IN1(n1406), .IN2(n20), .IN3(n1930), .Q(
\fpu_add_frac_dp/n3625 ) );
NOR2X0 U1853 ( .IN1(n2667), .IN2(n1745), .QN(n1930) );
AO221X1 U1854 ( .IN1(n2668), .IN2(n2669), .IN3(n2608), .IN4(n2670), .IN5(
n2671), .Q(n2667) );
AO21X1 U1855 ( .IN1(n2672), .IN2(n2604), .IN3(n2610), .Q(n2671) );
AO22X1 U1856 ( .IN1(n2608), .IN2(n2059), .IN3(n2604), .IN4(n2054), .Q(n2610)
);
NAND4X0 U1857 ( .IN1(n2673), .IN2(n2674), .IN3(n2675), .IN4(n2676), .QN(
n2054) );
NOR2X0 U1858 ( .IN1(n2677), .IN2(n2678), .QN(n2676) );
XNOR3X1 U1859 ( .IN1(n2679), .IN2(n2680), .IN3(n2681), .Q(n2678) );
XNOR3X1 U1860 ( .IN1(n2682), .IN2(n2683), .IN3(n2684), .Q(n2677) );
NAND3X0 U1861 ( .IN1(n2685), .IN2(n2686), .IN3(n2687), .QN(n2675) );
XOR3X1 U1862 ( .IN1(n2688), .IN2(n2689), .IN3(n2690), .Q(n2674) );
XOR3X1 U1863 ( .IN1(n2691), .IN2(n2692), .IN3(n2693), .Q(n2673) );
NAND4X0 U1864 ( .IN1(n2694), .IN2(n2695), .IN3(n2696), .IN4(n2697), .QN(
n2059) );
NOR2X0 U1865 ( .IN1(n2698), .IN2(n2699), .QN(n2697) );
XOR3X1 U1866 ( .IN1(n2700), .IN2(n2701), .IN3(n2702), .Q(n2699) );
OA22X1 U1867 ( .IN1(\fpu_add_exp_dp/n205 ), .IN2(\fpu_add_exp_dp/n235 ),
.IN3(\fpu_add_exp_dp/n189 ), .IN4(\fpu_add_exp_dp/n238 ), .Q(n2701) );
XOR3X1 U1868 ( .IN1(n2703), .IN2(n2704), .IN3(n2705), .Q(n2698) );
OA22X1 U1869 ( .IN1(\fpu_add_exp_dp/n204 ), .IN2(\fpu_add_exp_dp/n234 ),
.IN3(\fpu_add_exp_dp/n188 ), .IN4(\fpu_add_exp_dp/n237 ), .Q(n2704) );
XOR3X1 U1870 ( .IN1(n2706), .IN2(n2707), .IN3(n2708), .Q(n2696) );
NAND2X0 U1871 ( .IN1(n2709), .IN2(n2710), .QN(n2708) );
NOR2X0 U1872 ( .IN1(\fpu_add_exp_dp/n234 ), .IN2(\fpu_add_exp_dp/n185 ),
.QN(n2707) );
XOR3X1 U1873 ( .IN1(n2710), .IN2(n2711), .IN3(n2709), .Q(n2695) );
NOR2X0 U1874 ( .IN1(n2712), .IN2(n2713), .QN(n2709) );
NOR2X0 U1875 ( .IN1(\fpu_add_exp_dp/n186 ), .IN2(\fpu_add_exp_dp/n235 ),
.QN(n2711) );
XOR3X1 U1876 ( .IN1(n2713), .IN2(n2714), .IN3(n2712), .Q(n2694) );
NAND2X0 U1877 ( .IN1(n2703), .IN2(n2705), .QN(n2712) );
NOR2X0 U1878 ( .IN1(n2702), .IN2(n2700), .QN(n2705) );
AO22X1 U1879 ( .IN1(n2715), .IN2(n2716), .IN3(n2717), .IN4(n2718), .Q(n2702)
);
OR2X1 U1880 ( .IN1(n2716), .IN2(n2715), .Q(n2717) );
NOR2X0 U1881 ( .IN1(\fpu_add_exp_dp/n236 ), .IN2(\fpu_add_exp_dp/n187 ),
.QN(n2714) );
AND2X1 U1882 ( .IN1(n2050), .IN2(n2719), .Q(n2604) );
XNOR3X1 U1883 ( .IN1(n2720), .IN2(n2721), .IN3(n2722), .Q(n2672) );
XOR3X1 U1884 ( .IN1(n2718), .IN2(n2715), .IN3(n2716), .Q(n2670) );
AO22X1 U1885 ( .IN1(n2663), .IN2(n2664), .IN3(n2723), .IN4(n2662), .Q(n2716)
);
OR2X1 U1886 ( .IN1(n2664), .IN2(n2663), .Q(n2723) );
AO22X1 U1887 ( .IN1(n2648), .IN2(n2650), .IN3(n2724), .IN4(n2649), .Q(n2664)
);
OR2X1 U1888 ( .IN1(n2650), .IN2(n2648), .Q(n2724) );
AO22X1 U1889 ( .IN1(n2630), .IN2(n2632), .IN3(n2725), .IN4(n2631), .Q(n2650)
);
OR2X1 U1890 ( .IN1(n2632), .IN2(n2630), .Q(n2725) );
AO22X1 U1891 ( .IN1(n2618), .IN2(n2726), .IN3(n2727), .IN4(n2728), .Q(n2632)
);
INVX0 U1892 ( .INP(n2619), .ZN(n2728) );
OR2X1 U1893 ( .IN1(n2726), .IN2(n2618), .Q(n2727) );
INVX0 U1894 ( .INP(n2609), .ZN(n2726) );
NOR2X0 U1895 ( .IN1(n2058), .IN2(n2057), .QN(n2609) );
OA22X1 U1896 ( .IN1(\fpu_add_exp_dp/n211 ), .IN2(\fpu_add_exp_dp/n241 ),
.IN3(\fpu_add_exp_dp/n195 ), .IN4(\fpu_add_exp_dp/n244 ), .Q(n2057) );
INVX0 U1897 ( .INP(n2622), .ZN(n2058) );
OA22X1 U1898 ( .IN1(\fpu_add_exp_dp/n243 ), .IN2(\fpu_add_exp_dp/n194 ),
.IN3(\fpu_add_exp_dp/n240 ), .IN4(\fpu_add_exp_dp/n210 ), .Q(n2618) );
OA22X1 U1899 ( .IN1(\fpu_add_exp_dp/n242 ), .IN2(\fpu_add_exp_dp/n193 ),
.IN3(\fpu_add_exp_dp/n239 ), .IN4(\fpu_add_exp_dp/n209 ), .Q(n2630) );
OA22X1 U1900 ( .IN1(\fpu_add_exp_dp/n241 ), .IN2(\fpu_add_exp_dp/n192 ),
.IN3(\fpu_add_exp_dp/n238 ), .IN4(\fpu_add_exp_dp/n208 ), .Q(n2648) );
OA22X1 U1901 ( .IN1(\fpu_add_exp_dp/n240 ), .IN2(\fpu_add_exp_dp/n191 ),
.IN3(\fpu_add_exp_dp/n237 ), .IN4(\fpu_add_exp_dp/n207 ), .Q(n2663) );
OA22X1 U1902 ( .IN1(\fpu_add_exp_dp/n239 ), .IN2(\fpu_add_exp_dp/n190 ),
.IN3(\fpu_add_exp_dp/n236 ), .IN4(\fpu_add_exp_dp/n206 ), .Q(n2715) );
NOR2X0 U1903 ( .IN1(n1867), .IN2(n2050), .QN(n2608) );
OR2X1 U1904 ( .IN1(n2729), .IN2(n2730), .Q(n2669) );
AO222X1 U1905 ( .IN1(n1322), .IN2(n652), .IN3(n2460), .IN4(n103), .IN5(n1388), .IN6(n219), .Q(\fpu_add_frac_dp/n3624 ) );
AO222X1 U1906 ( .IN1(n1321), .IN2(n103), .IN3(n2460), .IN4(n282), .IN5(n1388), .IN6(n48), .Q(\fpu_add_frac_dp/n3623 ) );
AO222X1 U1907 ( .IN1(n1319), .IN2(n282), .IN3(n2460), .IN4(n671), .IN5(n1388), .IN6(n115), .Q(\fpu_add_frac_dp/n3622 ) );
AO222X1 U1908 ( .IN1(n1320), .IN2(n671), .IN3(n2460), .IN4(n90), .IN5(n1388),
.IN6(n50), .Q(\fpu_add_frac_dp/n3621 ) );
AO222X1 U1909 ( .IN1(n1322), .IN2(n90), .IN3(n2460), .IN4(n626), .IN5(n1388),
.IN6(n284), .Q(\fpu_add_frac_dp/n3620 ) );
AO222X1 U1910 ( .IN1(n1321), .IN2(n626), .IN3(n2460), .IN4(n173), .IN5(n1388), .IN6(n51), .Q(\fpu_add_frac_dp/n3619 ) );
AO222X1 U1911 ( .IN1(n1319), .IN2(n173), .IN3(n2460), .IN4(n33), .IN5(n1387),
.IN6(n124), .Q(\fpu_add_frac_dp/n3618 ) );
AO222X1 U1912 ( .IN1(n1320), .IN2(n33), .IN3(n2460), .IN4(n623), .IN5(n1387),
.IN6(n286), .Q(\fpu_add_frac_dp/n3617 ) );
AO222X1 U1913 ( .IN1(n1322), .IN2(n623), .IN3(n2460), .IN4(n34), .IN5(n1387),
.IN6(n123), .Q(\fpu_add_frac_dp/n3616 ) );
AO222X1 U1914 ( .IN1(n1321), .IN2(n34), .IN3(n2460), .IN4(n12), .IN5(n1387),
.IN6(n285), .Q(\fpu_add_frac_dp/n3615 ) );
AO222X1 U1915 ( .IN1(n1319), .IN2(n12), .IN3(n2460), .IN4(n691), .IN5(n1387),
.IN6(n119), .Q(\fpu_add_frac_dp/n3614 ) );
AO222X1 U1916 ( .IN1(n1320), .IN2(n691), .IN3(n2460), .IN4(n37), .IN5(n1387),
.IN6(n264), .Q(\fpu_add_frac_dp/n3613 ) );
AO222X1 U1917 ( .IN1(n1322), .IN2(n37), .IN3(n2460), .IN4(n597), .IN5(n1387),
.IN6(n107), .Q(\fpu_add_frac_dp/n3612 ) );
AO222X1 U1918 ( .IN1(n1321), .IN2(n597), .IN3(n2460), .IN4(
\fpu_add_frac_dp/n2330 ), .IN5(n1387), .IN6(n257), .Q(
\fpu_add_frac_dp/n3611 ) );
AO222X1 U1919 ( .IN1(n1319), .IN2(\fpu_add_frac_dp/n2330 ), .IN3(n2460),
.IN4(\fpu_add_frac_dp/n2400 ), .IN5(n1387), .IN6(n45), .Q(
\fpu_add_frac_dp/n3610 ) );
AO222X1 U1920 ( .IN1(n1320), .IN2(\fpu_add_frac_dp/n2400 ), .IN3(n2460),
.IN4(n328), .IN5(n1387), .IN6(n130), .Q(\fpu_add_frac_dp/n3609 ) );
AO222X1 U1921 ( .IN1(n1322), .IN2(n328), .IN3(n2460), .IN4(n43), .IN5(n1387),
.IN6(n756), .Q(\fpu_add_frac_dp/n3608 ) );
AO222X1 U1922 ( .IN1(n1321), .IN2(n43), .IN3(n2460), .IN4(n111), .IN5(n1387),
.IN6(n430), .Q(\fpu_add_frac_dp/n3607 ) );
AO222X1 U1923 ( .IN1(n1319), .IN2(n111), .IN3(n2460), .IN4(n664), .IN5(n1386), .IN6(n429), .Q(\fpu_add_frac_dp/n3606 ) );
AO222X1 U1924 ( .IN1(n1320), .IN2(n664), .IN3(n2460), .IN4(
\fpu_add_frac_dp/n2339 ), .IN5(n1386), .IN6(n431), .Q(
\fpu_add_frac_dp/n3605 ) );
AO222X1 U1925 ( .IN1(n1322), .IN2(\fpu_add_frac_dp/n2339 ), .IN3(n2460),
.IN4(\fpu_add_frac_dp/n2405 ), .IN5(n1386), .IN6(n432), .Q(
\fpu_add_frac_dp/n3604 ) );
AO222X1 U1926 ( .IN1(n1321), .IN2(\fpu_add_frac_dp/n2405 ), .IN3(n2460),
.IN4(n594), .IN5(n1386), .IN6(n450), .Q(\fpu_add_frac_dp/n3603 ) );
AO222X1 U1927 ( .IN1(n1319), .IN2(n594), .IN3(n2460), .IN4(n74), .IN5(n1386),
.IN6(n449), .Q(\fpu_add_frac_dp/n3602 ) );
AO222X1 U1928 ( .IN1(n1320), .IN2(n74), .IN3(n2460), .IN4(n331), .IN5(n1386),
.IN6(n750), .Q(\fpu_add_frac_dp/n3601 ) );
AO222X1 U1929 ( .IN1(n1322), .IN2(n331), .IN3(n2460), .IN4(n116), .IN5(n1386), .IN6(n752), .Q(\fpu_add_frac_dp/n3600 ) );
AO222X1 U1930 ( .IN1(n1321), .IN2(n116), .IN3(n2460), .IN4(
\fpu_add_frac_dp/n2402 ), .IN5(n1386), .IN6(n748), .Q(
\fpu_add_frac_dp/n3599 ) );
AO222X1 U1931 ( .IN1(n1319), .IN2(\fpu_add_frac_dp/n2402 ), .IN3(n2460),
.IN4(\fpu_add_frac_dp/n2313 ), .IN5(n1386), .IN6(n448), .Q(
\fpu_add_frac_dp/n3598 ) );
AO222X1 U1932 ( .IN1(n1320), .IN2(\fpu_add_frac_dp/n2313 ), .IN3(n2460),
.IN4(n329), .IN5(n1386), .IN6(n749), .Q(\fpu_add_frac_dp/n3597 ) );
AO222X1 U1933 ( .IN1(n1322), .IN2(n329), .IN3(n2460), .IN4(n101), .IN5(n1386), .IN6(n751), .Q(\fpu_add_frac_dp/n3596 ) );
AO222X1 U1934 ( .IN1(n1321), .IN2(n101), .IN3(n2460), .IN4(n262), .IN5(n1386), .IN6(n727), .Q(\fpu_add_frac_dp/n3595 ) );
AO222X1 U1935 ( .IN1(n1319), .IN2(n262), .IN3(n2460), .IN4(
\fpu_add_frac_dp/n2335 ), .IN5(n1385), .IN6(n726), .Q(
\fpu_add_frac_dp/n3594 ) );
AO222X1 U1936 ( .IN1(n1320), .IN2(\fpu_add_frac_dp/n2335 ), .IN3(n2460),
.IN4(\fpu_add_frac_dp/n2403 ), .IN5(n1385), .IN6(n729), .Q(
\fpu_add_frac_dp/n3593 ) );
AO222X1 U1937 ( .IN1(n1322), .IN2(\fpu_add_frac_dp/n2403 ), .IN3(n2460),
.IN4(\fpu_add_frac_dp/n2342 ), .IN5(n1385), .IN6(n1090), .Q(
\fpu_add_frac_dp/n3592 ) );
AO222X1 U1938 ( .IN1(n1321), .IN2(\fpu_add_frac_dp/n2342 ), .IN3(n2460),
.IN4(\fpu_add_frac_dp/n2289 ), .IN5(n1385), .IN6(n740), .Q(
\fpu_add_frac_dp/n3591 ) );
AO222X1 U1939 ( .IN1(n1319), .IN2(\fpu_add_frac_dp/n2289 ), .IN3(n2460),
.IN4(\fpu_add_frac_dp/n2406 ), .IN5(n1385), .IN6(n739), .Q(
\fpu_add_frac_dp/n3590 ) );
AO222X1 U1940 ( .IN1(n1320), .IN2(\fpu_add_frac_dp/n2406 ), .IN3(n2460),
.IN4(\fpu_add_frac_dp/n2332 ), .IN5(n1385), .IN6(n741), .Q(
\fpu_add_frac_dp/n3589 ) );
AO222X1 U1941 ( .IN1(n1322), .IN2(\fpu_add_frac_dp/n2332 ), .IN3(n2460),
.IN4(n177), .IN5(n1385), .IN6(n742), .Q(\fpu_add_frac_dp/n3588 ) );
AO222X1 U1942 ( .IN1(n1321), .IN2(n177), .IN3(n2460), .IN4(n86), .IN5(n1385),
.IN6(n765), .Q(\fpu_add_frac_dp/n3587 ) );
AO222X1 U1943 ( .IN1(n1319), .IN2(n86), .IN3(n2460), .IN4(n19), .IN5(n1385),
.IN6(n767), .Q(\fpu_add_frac_dp/n3586 ) );
AO222X1 U1944 ( .IN1(n1320), .IN2(n19), .IN3(n2460), .IN4(n673), .IN5(n1385),
.IN6(n459), .Q(\fpu_add_frac_dp/n3585 ) );
AO222X1 U1945 ( .IN1(n1322), .IN2(n673), .IN3(n2460), .IN4(n117), .IN5(n1385), .IN6(n458), .Q(\fpu_add_frac_dp/n3584 ) );
AO222X1 U1946 ( .IN1(n1321), .IN2(n117), .IN3(n2460), .IN4(n38), .IN5(n1385),
.IN6(n462), .Q(\fpu_add_frac_dp/n3583 ) );
AO222X1 U1947 ( .IN1(n1319), .IN2(n38), .IN3(n2460), .IN4(n83), .IN5(n1384),
.IN6(n766), .Q(\fpu_add_frac_dp/n3582 ) );
AO222X1 U1948 ( .IN1(n1320), .IN2(n83), .IN3(n2460), .IN4(n665), .IN5(n1384),
.IN6(n461), .Q(\fpu_add_frac_dp/n3581 ) );
AO222X1 U1949 ( .IN1(n1322), .IN2(n665), .IN3(n2460), .IN4(n100), .IN5(n1384), .IN6(n464), .Q(\fpu_add_frac_dp/n3580 ) );
AO222X1 U1950 ( .IN1(n1321), .IN2(n100), .IN3(n2460), .IN4(n667), .IN5(n1384), .IN6(n457), .Q(\fpu_add_frac_dp/n3579 ) );
AO222X1 U1951 ( .IN1(n1319), .IN2(n667), .IN3(n2460), .IN4(n40), .IN5(n1384),
.IN6(n456), .Q(\fpu_add_frac_dp/n3578 ) );
AO222X1 U1952 ( .IN1(n1320), .IN2(n40), .IN3(n2460), .IN4(n104), .IN5(n1384),
.IN6(n451), .Q(\fpu_add_frac_dp/n3577 ) );
AO222X1 U1953 ( .IN1(n1322), .IN2(n104), .IN3(n2460), .IN4(n175), .IN5(n1384), .IN6(n914), .Q(\fpu_add_frac_dp/n3576 ) );
AO222X1 U1954 ( .IN1(n1321), .IN2(n175), .IN3(n2460), .IN4(n22), .IN5(n1384),
.IN6(n838), .Q(\fpu_add_frac_dp/n3575 ) );
AO222X1 U1955 ( .IN1(n1319), .IN2(n22), .IN3(n2460), .IN4(n85), .IN5(n1384),
.IN6(n837), .Q(\fpu_add_frac_dp/n3574 ) );
AO222X1 U1956 ( .IN1(n1320), .IN2(n85), .IN3(n2460), .IN4(n313), .IN5(n1384),
.IN6(n842), .Q(\fpu_add_frac_dp/n3573 ) );
AO222X1 U1957 ( .IN1(n1322), .IN2(n313), .IN3(n2460), .IN4(n92), .IN5(n1383),
.IN6(n845), .Q(\fpu_add_frac_dp/n3572 ) );
AO222X1 U1958 ( .IN1(n1321), .IN2(n92), .IN3(n2460), .IN4(n265), .IN5(n1383),
.IN6(n836), .Q(\fpu_add_frac_dp/n3571 ) );
AO222X1 U1959 ( .IN1(n1319), .IN2(n265), .IN3(n2460), .IN4(
\fpu_add_frac_dp/n2338 ), .IN5(n1383), .IN6(n835), .Q(
\fpu_add_frac_dp/n3570 ) );
AO222X1 U1960 ( .IN1(n1320), .IN2(\fpu_add_frac_dp/n2338 ), .IN3(n2460),
.IN4(\fpu_add_frac_dp/n2407 ), .IN5(n1383), .IN6(n841), .Q(
\fpu_add_frac_dp/n3569 ) );
AO222X1 U1961 ( .IN1(n1322), .IN2(\fpu_add_frac_dp/n2407 ), .IN3(n2460),
.IN4(\fpu_add_frac_dp/n2343 ), .IN5(n1383), .IN6(n844), .Q(
\fpu_add_frac_dp/n3568 ) );
AO222X1 U1962 ( .IN1(n1321), .IN2(\fpu_add_frac_dp/n2343 ), .IN3(n2460),
.IN4(n171), .IN5(n1383), .IN6(n834), .Q(\fpu_add_frac_dp/n3567 ) );
AO222X1 U1963 ( .IN1(n1319), .IN2(n171), .IN3(n2460), .IN4(n82), .IN5(n1383),
.IN6(n833), .Q(\fpu_add_frac_dp/n3566 ) );
AO222X1 U1964 ( .IN1(n1320), .IN2(n82), .IN3(n2460), .IN4(
\fpu_add_frac_dp/n2337 ), .IN5(n1383), .IN6(n840), .Q(
\fpu_add_frac_dp/n3565 ) );
AO222X1 U1965 ( .IN1(n1322), .IN2(\fpu_add_frac_dp/n2337 ), .IN3(n2460),
.IN4(n94), .IN5(n1379), .IN6(n843), .Q(\fpu_add_frac_dp/n3564 ) );
AO222X1 U1966 ( .IN1(n1321), .IN2(n94), .IN3(n2460), .IN4(n266), .IN5(n1379),
.IN6(n832), .Q(\fpu_add_frac_dp/n3563 ) );
AO222X1 U1967 ( .IN1(n1319), .IN2(n266), .IN3(n2460), .IN4(n87), .IN5(n1379),
.IN6(n831), .Q(\fpu_add_frac_dp/n3562 ) );
AND2X1 U1968 ( .IN1(n1442), .IN2(n2590), .Q(n2460) );
AO22X1 U1969 ( .IN1(n1426), .IN2(n846), .IN3(n1320), .IN4(n87), .Q(
\fpu_add_frac_dp/n3561 ) );
NAND4X0 U1970 ( .IN1(\fpu_add_frac_dp/n599 ), .IN2(n2731), .IN3(n2732),
.IN4(n2733), .QN(n2590) );
OA221X1 U1971 ( .IN1(n2734), .IN2(n2506), .IN3(n2735), .IN4(n2578), .IN5(
n2736), .Q(n2733) );
OA22X1 U1972 ( .IN1(n2737), .IN2(n87), .IN3(n2738), .IN4(n2509), .Q(n2736)
);
INVX0 U1973 ( .INP(n2739), .ZN(n2509) );
OA21X1 U1974 ( .IN1(n2740), .IN2(n22), .IN3(\fpu_add_frac_dp/n612 ), .Q(
n2738) );
OA21X1 U1975 ( .IN1(\fpu_add_frac_dp/n614 ), .IN2(n175), .IN3(
\fpu_add_frac_dp/n613 ), .Q(n2740) );
OA21X1 U1976 ( .IN1(n2741), .IN2(n266), .IN3(\fpu_add_frac_dp/n600 ), .Q(
n2737) );
OA21X1 U1977 ( .IN1(\fpu_add_frac_dp/n602 ), .IN2(n94), .IN3(
\fpu_add_frac_dp/n601 ), .Q(n2741) );
OA221X1 U1978 ( .IN1(n2742), .IN2(n2743), .IN3(n2744), .IN4(n2473), .IN5(
n2745), .Q(n2735) );
OA21X1 U1979 ( .IN1(\fpu_add_frac_dp/n616 ), .IN2(n40), .IN3(
\fpu_add_frac_dp/n615 ), .Q(n2745) );
OA221X1 U1980 ( .IN1(\fpu_add_frac_dp/n628 ), .IN2(n2480), .IN3(n2746),
.IN4(n2747), .IN5(n2748), .Q(n2744) );
OA21X1 U1981 ( .IN1(\fpu_add_frac_dp/n627 ), .IN2(\fpu_add_frac_dp/n2332 ),
.IN3(\fpu_add_frac_dp/n626 ), .Q(n2748) );
OA21X1 U1982 ( .IN1(\fpu_add_frac_dp/n630 ), .IN2(\fpu_add_frac_dp/n2342 ),
.IN3(\fpu_add_frac_dp/n629 ), .Q(n2746) );
OA221X1 U1983 ( .IN1(n2749), .IN2(n2544), .IN3(n2750), .IN4(n2751), .IN5(
n2752), .Q(n2742) );
OA21X1 U1984 ( .IN1(\fpu_add_frac_dp/n618 ), .IN2(n100), .IN3(
\fpu_add_frac_dp/n617 ), .Q(n2752) );
INVX0 U1985 ( .INP(n2541), .ZN(n2751) );
OA21X1 U1986 ( .IN1(n2753), .IN2(n19), .IN3(\fpu_add_frac_dp/n623 ), .Q(
n2750) );
OA21X1 U1987 ( .IN1(\fpu_add_frac_dp/n625 ), .IN2(n86), .IN3(
\fpu_add_frac_dp/n624 ), .Q(n2753) );
OA21X1 U1988 ( .IN1(n2754), .IN2(n83), .IN3(\fpu_add_frac_dp/n619 ), .Q(
n2749) );
OA21X1 U1989 ( .IN1(n2755), .IN2(n38), .IN3(\fpu_add_frac_dp/n620 ), .Q(
n2754) );
OA21X1 U1990 ( .IN1(\fpu_add_frac_dp/n622 ), .IN2(n117), .IN3(
\fpu_add_frac_dp/n621 ), .Q(n2755) );
INVX0 U1991 ( .INP(n2530), .ZN(n2506) );
OA21X1 U1992 ( .IN1(n2756), .IN2(n265), .IN3(\fpu_add_frac_dp/n608 ), .Q(
n2734) );
OA21X1 U1993 ( .IN1(\fpu_add_frac_dp/n610 ), .IN2(n92), .IN3(
\fpu_add_frac_dp/n609 ), .Q(n2756) );
OA22X1 U1994 ( .IN1(n2757), .IN2(n2577), .IN3(n2758), .IN4(n2569), .Q(n2732)
);
OA221X1 U1995 ( .IN1(\fpu_add_frac_dp/n607 ), .IN2(n2513), .IN3(n2759),
.IN4(n82), .IN5(\fpu_add_frac_dp/n603 ), .Q(n2758) );
OA21X1 U1996 ( .IN1(n2760), .IN2(n171), .IN3(\fpu_add_frac_dp/n604 ), .Q(
n2759) );
OA21X1 U1997 ( .IN1(\fpu_add_frac_dp/n606 ), .IN2(\fpu_add_frac_dp/n2343 ),
.IN3(\fpu_add_frac_dp/n605 ), .Q(n2760) );
NAND2X0 U1998 ( .IN1(n2596), .IN2(n2462), .QN(n2577) );
INVX0 U1999 ( .INP(n2578), .ZN(n2462) );
NAND4X0 U2000 ( .IN1(\fpu_add_frac_dp/n5631 ), .IN2(\fpu_add_frac_dp/n5630 ),
.IN3(\fpu_add_frac_dp/n2386 ), .IN4(n2739), .QN(n2578) );
NOR2X0 U2001 ( .IN1(n85), .IN2(n2567), .QN(n2739) );
NOR4X0 U2002 ( .IN1(n2473), .IN2(n2747), .IN3(\fpu_add_frac_dp/n2342 ),
.IN4(\fpu_add_frac_dp/n2403 ), .QN(n2596) );
INVX0 U2003 ( .INP(n2540), .ZN(n2747) );
NOR2X0 U2004 ( .IN1(n2480), .IN2(\fpu_add_frac_dp/n2289 ), .QN(n2540) );
OR2X1 U2005 ( .IN1(\fpu_add_frac_dp/n2332 ), .IN2(\fpu_add_frac_dp/n2406 ),
.Q(n2480) );
NAND4X0 U2006 ( .IN1(n2476), .IN2(n2541), .IN3(\fpu_add_frac_dp/n2336 ),
.IN4(n2761), .QN(n2473) );
NOR2X0 U2007 ( .IN1(n19), .IN2(n177), .QN(n2761) );
NOR3X0 U2008 ( .IN1(n2479), .IN2(n2544), .IN3(n83), .QN(n2541) );
NAND2X0 U2009 ( .IN1(\fpu_add_frac_dp/n5609 ), .IN2(\fpu_add_frac_dp/n2387 ),
.QN(n2544) );
NAND3X0 U2010 ( .IN1(\fpu_add_frac_dp/n2481 ), .IN2(\fpu_add_frac_dp/n2361 ),
.IN3(\fpu_add_frac_dp/n658 ), .QN(n2479) );
INVX0 U2011 ( .INP(n2743), .ZN(n2476) );
NAND2X0 U2012 ( .IN1(\fpu_add_frac_dp/n5632 ), .IN2(\fpu_add_frac_dp/n2333 ),
.QN(n2743) );
OA221X1 U2013 ( .IN1(\fpu_add_frac_dp/n2335 ), .IN2(n2762), .IN3(n2763),
.IN4(n2493), .IN5(\fpu_add_frac_dp/n631 ), .Q(n2757) );
NAND4X0 U2014 ( .IN1(\fpu_add_frac_dp/n2411 ), .IN2(n2561), .IN3(n2492),
.IN4(n2563), .QN(n2493) );
NOR4X0 U2015 ( .IN1(n594), .IN2(n74), .IN3(\fpu_add_frac_dp/n2339 ), .IN4(
\fpu_add_frac_dp/n2405 ), .QN(n2563) );
INVX0 U2016 ( .INP(n2565), .ZN(n2492) );
INVX0 U2017 ( .INP(n2490), .ZN(n2561) );
NAND2X0 U2018 ( .IN1(n2494), .IN2(n839), .QN(n2490) );
INVX0 U2019 ( .INP(n2764), .ZN(n2494) );
OA221X1 U2020 ( .IN1(n2765), .IN2(n2595), .IN3(n2766), .IN4(n111), .IN5(
\fpu_add_frac_dp/n644 ), .Q(n2763) );
OA21X1 U2021 ( .IN1(\fpu_add_frac_dp/n646 ), .IN2(n43), .IN3(
\fpu_add_frac_dp/n645 ), .Q(n2766) );
NAND3X0 U2022 ( .IN1(\fpu_add_frac_dp/n2344 ), .IN2(\fpu_add_frac_dp/n2495 ),
.IN3(\fpu_add_frac_dp/n664 ), .QN(n2595) );
AND3X1 U2023 ( .IN1(\fpu_add_frac_dp/n647 ), .IN2(n2767), .IN3(n2768), .Q(
n2765) );
OA221X1 U2024 ( .IN1(\fpu_add_frac_dp/n2400 ), .IN2(n2769), .IN3(n2770),
.IN4(n2496), .IN5(n2771), .Q(n2768) );
OR3X1 U2025 ( .IN1(n103), .IN2(n2546), .IN3(n652), .Q(n2771) );
NAND4X0 U2026 ( .IN1(n2502), .IN2(n2551), .IN3(\fpu_add_frac_dp/n2447 ),
.IN4(n2772), .QN(n2546) );
AND3X1 U2027 ( .IN1(\fpu_add_frac_dp/n668 ), .IN2(\fpu_add_frac_dp/n2513 ),
.IN3(\fpu_add_frac_dp/n670 ), .Q(n2772) );
NOR2X0 U2028 ( .IN1(n90), .IN2(n626), .QN(n2551) );
NOR4X0 U2029 ( .IN1(n623), .IN2(n12), .IN3(n34), .IN4(n2496), .QN(n2502) );
NAND2X0 U2030 ( .IN1(\fpu_add_frac_dp/n2519 ), .IN2(n2556), .QN(n2496) );
OA21X1 U2031 ( .IN1(\fpu_add_ctl/n140 ), .IN2(n12), .IN3(
\fpu_add_frac_dp/n652 ), .Q(n2770) );
OA21X1 U2032 ( .IN1(\fpu_add_frac_dp/n2330 ), .IN2(n2773), .IN3(
\fpu_add_frac_dp/n648 ), .Q(n2769) );
OA21X1 U2033 ( .IN1(\fpu_add_frac_dp/n650 ), .IN2(n597), .IN3(
\fpu_add_frac_dp/n649 ), .Q(n2773) );
NAND2X0 U2034 ( .IN1(n2556), .IN2(n1081), .QN(n2767) );
NOR3X0 U2035 ( .IN1(\fpu_add_frac_dp/n2330 ), .IN2(\fpu_add_frac_dp/n2400 ),
.IN3(n2774), .QN(n2556) );
INVX0 U2036 ( .INP(n2552), .ZN(n2774) );
NOR2X0 U2037 ( .IN1(n37), .IN2(n597), .QN(n2552) );
OA221X1 U2038 ( .IN1(n2775), .IN2(n2764), .IN3(n2776), .IN4(n262), .IN5(
\fpu_add_frac_dp/n632 ), .Q(n2762) );
OA21X1 U2039 ( .IN1(\fpu_add_frac_dp/n634 ), .IN2(n101), .IN3(
\fpu_add_frac_dp/n633 ), .Q(n2776) );
NAND3X0 U2040 ( .IN1(\fpu_add_frac_dp/n2496 ), .IN2(\fpu_add_frac_dp/n2363 ),
.IN3(\fpu_add_frac_dp/n660 ), .QN(n2764) );
OA221X1 U2041 ( .IN1(n2777), .IN2(n2565), .IN3(\fpu_add_frac_dp/n2313 ),
.IN4(n2778), .IN5(\fpu_add_frac_dp/n635 ), .Q(n2775) );
OA21X1 U2042 ( .IN1(\fpu_add_frac_dp/n2402 ), .IN2(n2779), .IN3(
\fpu_add_frac_dp/n636 ), .Q(n2778) );
OA21X1 U2043 ( .IN1(\fpu_add_frac_dp/n638 ), .IN2(n116), .IN3(
\fpu_add_frac_dp/n637 ), .Q(n2779) );
NAND4X0 U2044 ( .IN1(\fpu_add_frac_dp/n5619 ), .IN2(\fpu_add_frac_dp/n2470 ),
.IN3(n346), .IN4(n710), .QN(n2565) );
OA21X1 U2045 ( .IN1(n2780), .IN2(n74), .IN3(\fpu_add_frac_dp/n639 ), .Q(
n2777) );
OA21X1 U2046 ( .IN1(n2781), .IN2(n594), .IN3(\fpu_add_frac_dp/n640 ), .Q(
n2780) );
OA21X1 U2047 ( .IN1(n2782), .IN2(\fpu_add_frac_dp/n2405 ), .IN3(
\fpu_add_frac_dp/n641 ), .Q(n2781) );
OA21X1 U2048 ( .IN1(\fpu_add_frac_dp/n2339 ), .IN2(\fpu_add_frac_dp/n643 ),
.IN3(\fpu_add_frac_dp/n642 ), .Q(n2782) );
OR2X1 U2049 ( .IN1(n2567), .IN2(\fpu_add_frac_dp/n611 ), .Q(n2731) );
NAND4X0 U2050 ( .IN1(\fpu_add_frac_dp/n2416 ), .IN2(\fpu_add_frac_dp/n2345 ),
.IN3(\fpu_add_frac_dp/n2290 ), .IN4(n2530), .QN(n2567) );
NOR3X0 U2051 ( .IN1(n2513), .IN2(\fpu_add_frac_dp/n2338 ), .IN3(n2569), .QN(
n2530) );
NAND4X0 U2052 ( .IN1(\fpu_add_frac_dp/n5618 ), .IN2(\fpu_add_frac_dp/n2440 ),
.IN3(\fpu_add_frac_dp/n2288 ), .IN4(n654), .QN(n2569) );
NAND3X0 U2053 ( .IN1(\fpu_add_frac_dp/n2394 ), .IN2(n2535), .IN3(
\fpu_add_frac_dp/n654 ), .QN(n2513) );
NOR2X0 U2054 ( .IN1(\fpu_add_frac_dp/n2407 ), .IN2(\fpu_add_frac_dp/n2343 ),
.QN(n2535) );
AO22X1 U2055 ( .IN1(n1426), .IN2(n987), .IN3(n2783), .IN4(n1438), .Q(
\fpu_add_frac_dp/n3560 ) );
NOR2X0 U2056 ( .IN1(n2784), .IN2(n2785), .QN(n2783) );
NOR3X0 U2057 ( .IN1(n2786), .IN2(n21), .IN3(n108), .QN(n2785) );
AO22X1 U2058 ( .IN1(n1426), .IN2(n986), .IN3(n2787), .IN4(n1438), .Q(
\fpu_add_frac_dp/n3559 ) );
XOR2X1 U2059 ( .IN1(n2788), .IN2(n2784), .Q(n2787) );
AO22X1 U2060 ( .IN1(n1426), .IN2(n985), .IN3(n2789), .IN4(n1438), .Q(
\fpu_add_frac_dp/n3558 ) );
NOR2X0 U2061 ( .IN1(n2790), .IN2(n2791), .QN(n2789) );
AOI21X1 U2062 ( .IN1(n2788), .IN2(n2784), .IN3(n2792), .QN(n2791) );
AO22X1 U2063 ( .IN1(n1426), .IN2(n984), .IN3(n2793), .IN4(n1438), .Q(
\fpu_add_frac_dp/n3557 ) );
XOR2X1 U2064 ( .IN1(n2790), .IN2(n2794), .Q(n2793) );
AO22X1 U2065 ( .IN1(n1426), .IN2(n983), .IN3(n2795), .IN4(n1436), .Q(
\fpu_add_frac_dp/n3556 ) );
NOR2X0 U2066 ( .IN1(n2796), .IN2(n2797), .QN(n2795) );
AOI21X1 U2067 ( .IN1(n2794), .IN2(n2790), .IN3(n2798), .QN(n2797) );
AO22X1 U2068 ( .IN1(n1427), .IN2(n982), .IN3(n2799), .IN4(n1438), .Q(
\fpu_add_frac_dp/n3555 ) );
XOR2X1 U2069 ( .IN1(n2800), .IN2(n2796), .Q(n2799) );
AO22X1 U2070 ( .IN1(n1427), .IN2(n981), .IN3(n2801), .IN4(n1435), .Q(
\fpu_add_frac_dp/n3554 ) );
NOR2X0 U2071 ( .IN1(n2802), .IN2(n2803), .QN(n2801) );
OA21X1 U2072 ( .IN1(n2804), .IN2(n2805), .IN3(n2806), .Q(n2803) );
AO22X1 U2073 ( .IN1(n1427), .IN2(n980), .IN3(n2807), .IN4(n1435), .Q(
\fpu_add_frac_dp/n3553 ) );
XOR2X1 U2074 ( .IN1(n2808), .IN2(n2809), .Q(n2807) );
AO22X1 U2075 ( .IN1(n1427), .IN2(n979), .IN3(n2810), .IN4(n1435), .Q(
\fpu_add_frac_dp/n3552 ) );
NOR2X0 U2076 ( .IN1(n2811), .IN2(n2812), .QN(n2810) );
OA21X1 U2077 ( .IN1(n2809), .IN2(n2808), .IN3(n2813), .Q(n2812) );
AO22X1 U2078 ( .IN1(n1427), .IN2(n977), .IN3(n2814), .IN4(n1435), .Q(
\fpu_add_frac_dp/n3551 ) );
XOR2X1 U2079 ( .IN1(n2815), .IN2(n2811), .Q(n2814) );
AO22X1 U2080 ( .IN1(n1427), .IN2(n976), .IN3(n2816), .IN4(n1435), .Q(
\fpu_add_frac_dp/n3550 ) );
NOR2X0 U2081 ( .IN1(n2817), .IN2(n2818), .QN(n2816) );
OA21X1 U2082 ( .IN1(n2819), .IN2(n2820), .IN3(n2821), .Q(n2818) );
AO22X1 U2083 ( .IN1(n1427), .IN2(n975), .IN3(n2822), .IN4(n1435), .Q(
\fpu_add_frac_dp/n3549 ) );
XOR2X1 U2084 ( .IN1(n2823), .IN2(n2824), .Q(n2822) );
AO22X1 U2085 ( .IN1(n1427), .IN2(n974), .IN3(n2825), .IN4(n1435), .Q(
\fpu_add_frac_dp/n3548 ) );
NOR2X0 U2086 ( .IN1(n2826), .IN2(n2827), .QN(n2825) );
OA21X1 U2087 ( .IN1(n2824), .IN2(n2823), .IN3(n2828), .Q(n2827) );
AO22X1 U2088 ( .IN1(n1427), .IN2(n973), .IN3(n2829), .IN4(n1435), .Q(
\fpu_add_frac_dp/n3547 ) );
XOR2X1 U2089 ( .IN1(n2830), .IN2(n2826), .Q(n2829) );
AO22X1 U2090 ( .IN1(n1427), .IN2(n972), .IN3(n2831), .IN4(n1435), .Q(
\fpu_add_frac_dp/n3546 ) );
NOR2X0 U2091 ( .IN1(n2832), .IN2(n2833), .QN(n2831) );
AOI21X1 U2092 ( .IN1(n2830), .IN2(n2826), .IN3(n2834), .QN(n2833) );
AO22X1 U2093 ( .IN1(n1427), .IN2(n971), .IN3(n2835), .IN4(n1436), .Q(
\fpu_add_frac_dp/n3545 ) );
XOR2X1 U2094 ( .IN1(n2832), .IN2(n2836), .Q(n2835) );
AO22X1 U2095 ( .IN1(n1428), .IN2(n970), .IN3(n2837), .IN4(n1435), .Q(
\fpu_add_frac_dp/n3544 ) );
NOR2X0 U2096 ( .IN1(n2838), .IN2(n2839), .QN(n2837) );
AOI21X1 U2097 ( .IN1(n2836), .IN2(n2832), .IN3(n2840), .QN(n2839) );
AO22X1 U2098 ( .IN1(n1427), .IN2(n969), .IN3(n2841), .IN4(n1436), .Q(
\fpu_add_frac_dp/n3543 ) );
XOR2X1 U2099 ( .IN1(n2842), .IN2(n2838), .Q(n2841) );
AO22X1 U2100 ( .IN1(n1428), .IN2(n1062), .IN3(n2843), .IN4(n1436), .Q(
\fpu_add_frac_dp/n3542 ) );
NOR2X0 U2101 ( .IN1(n2844), .IN2(n2845), .QN(n2843) );
AOI21X1 U2102 ( .IN1(n2842), .IN2(n2838), .IN3(n2846), .QN(n2845) );
AO22X1 U2103 ( .IN1(n1428), .IN2(n1061), .IN3(n2847), .IN4(n1436), .Q(
\fpu_add_frac_dp/n3541 ) );
XOR2X1 U2104 ( .IN1(n2844), .IN2(n2848), .Q(n2847) );
AO22X1 U2105 ( .IN1(n1428), .IN2(n1060), .IN3(n2849), .IN4(n1436), .Q(
\fpu_add_frac_dp/n3540 ) );
NOR2X0 U2106 ( .IN1(n2850), .IN2(n2851), .QN(n2849) );
AOI21X1 U2107 ( .IN1(n2848), .IN2(n2844), .IN3(n2852), .QN(n2851) );
AO22X1 U2108 ( .IN1(n1427), .IN2(n1059), .IN3(n2853), .IN4(n1436), .Q(
\fpu_add_frac_dp/n3539 ) );
XOR2X1 U2109 ( .IN1(n2854), .IN2(n2850), .Q(n2853) );
AO22X1 U2110 ( .IN1(n1427), .IN2(n1058), .IN3(n2855), .IN4(n1436), .Q(
\fpu_add_frac_dp/n3538 ) );
NOR2X0 U2111 ( .IN1(n2856), .IN2(n2857), .QN(n2855) );
AOI21X1 U2112 ( .IN1(n2854), .IN2(n2850), .IN3(n2858), .QN(n2857) );
AO22X1 U2113 ( .IN1(n1428), .IN2(n1057), .IN3(n2859), .IN4(n1436), .Q(
\fpu_add_frac_dp/n3537 ) );
XOR2X1 U2114 ( .IN1(n2860), .IN2(n2861), .Q(n2859) );
AO22X1 U2115 ( .IN1(n1428), .IN2(n1056), .IN3(n2862), .IN4(n1436), .Q(
\fpu_add_frac_dp/n3536 ) );
NOR2X0 U2116 ( .IN1(n2863), .IN2(n2864), .QN(n2862) );
OA21X1 U2117 ( .IN1(n2861), .IN2(n2860), .IN3(n2865), .Q(n2864) );
AO22X1 U2118 ( .IN1(n1428), .IN2(n1055), .IN3(n2866), .IN4(n1436), .Q(
\fpu_add_frac_dp/n3535 ) );
XOR2X1 U2119 ( .IN1(n2867), .IN2(n2863), .Q(n2866) );
AO22X1 U2120 ( .IN1(n1428), .IN2(n1054), .IN3(n2868), .IN4(n1436), .Q(
\fpu_add_frac_dp/n3534 ) );
NOR2X0 U2121 ( .IN1(n2869), .IN2(n2870), .QN(n2868) );
OA21X1 U2122 ( .IN1(n2871), .IN2(n2872), .IN3(n2873), .Q(n2870) );
AO22X1 U2123 ( .IN1(n1429), .IN2(n1053), .IN3(n2874), .IN4(n1436), .Q(
\fpu_add_frac_dp/n3533 ) );
XOR2X1 U2124 ( .IN1(n2875), .IN2(n2876), .Q(n2874) );
AO22X1 U2125 ( .IN1(n1427), .IN2(n1052), .IN3(n2877), .IN4(n1436), .Q(
\fpu_add_frac_dp/n3532 ) );
NOR2X0 U2126 ( .IN1(n2878), .IN2(n2879), .QN(n2877) );
OA21X1 U2127 ( .IN1(n2876), .IN2(n2875), .IN3(n2880), .Q(n2879) );
INVX0 U2128 ( .INP(n2881), .ZN(n2876) );
AO22X1 U2129 ( .IN1(n1429), .IN2(n1051), .IN3(n1442), .IN4(n2882), .Q(
\fpu_add_frac_dp/n3531 ) );
XOR3X1 U2130 ( .IN1(n2883), .IN2(n2884), .IN3(n2885), .Q(n2882) );
AO22X1 U2131 ( .IN1(n1428), .IN2(n1050), .IN3(n2886), .IN4(n1437), .Q(
\fpu_add_frac_dp/n3530 ) );
OA21X1 U2132 ( .IN1(n2887), .IN2(n2888), .IN3(n2889), .Q(n2886) );
AO22X1 U2133 ( .IN1(n1429), .IN2(n1049), .IN3(n2890), .IN4(n1436), .Q(
\fpu_add_frac_dp/n3529 ) );
XOR2X1 U2134 ( .IN1(n2891), .IN2(n2892), .Q(n2890) );
AO22X1 U2135 ( .IN1(n1428), .IN2(n1048), .IN3(n2893), .IN4(n1436), .Q(
\fpu_add_frac_dp/n3528 ) );
NOR2X0 U2136 ( .IN1(n2894), .IN2(n2895), .QN(n2893) );
AOI21X1 U2137 ( .IN1(n2891), .IN2(n2892), .IN3(n2896), .QN(n2895) );
AO22X1 U2138 ( .IN1(n1429), .IN2(n1047), .IN3(n2897), .IN4(n1436), .Q(
\fpu_add_frac_dp/n3527 ) );
XOR2X1 U2139 ( .IN1(n2894), .IN2(n2898), .Q(n2897) );
AO22X1 U2140 ( .IN1(n1428), .IN2(n1046), .IN3(n2899), .IN4(n1437), .Q(
\fpu_add_frac_dp/n3526 ) );
NOR2X0 U2141 ( .IN1(n2900), .IN2(n2901), .QN(n2899) );
AOI21X1 U2142 ( .IN1(n2898), .IN2(n2894), .IN3(n2902), .QN(n2901) );
AO22X1 U2143 ( .IN1(n1429), .IN2(n1045), .IN3(n2903), .IN4(n1437), .Q(
\fpu_add_frac_dp/n3525 ) );
XOR2X1 U2144 ( .IN1(n2904), .IN2(n2900), .Q(n2903) );
AO22X1 U2145 ( .IN1(n1428), .IN2(n1044), .IN3(n2905), .IN4(n1437), .Q(
\fpu_add_frac_dp/n3524 ) );
NOR2X0 U2146 ( .IN1(n2906), .IN2(n2907), .QN(n2905) );
AOI21X1 U2147 ( .IN1(n2904), .IN2(n2900), .IN3(n2908), .QN(n2907) );
AO22X1 U2148 ( .IN1(n1429), .IN2(n1043), .IN3(n2909), .IN4(n1437), .Q(
\fpu_add_frac_dp/n3523 ) );
XOR2X1 U2149 ( .IN1(n2906), .IN2(n2910), .Q(n2909) );
AO22X1 U2150 ( .IN1(n1429), .IN2(n1042), .IN3(n2911), .IN4(n1437), .Q(
\fpu_add_frac_dp/n3522 ) );
NOR2X0 U2151 ( .IN1(n2912), .IN2(n2913), .QN(n2911) );
AOI21X1 U2152 ( .IN1(n2910), .IN2(n2906), .IN3(n2914), .QN(n2913) );
AO22X1 U2153 ( .IN1(n1428), .IN2(n968), .IN3(n2915), .IN4(n1437), .Q(
\fpu_add_frac_dp/n3521 ) );
XOR2X1 U2154 ( .IN1(n2916), .IN2(n2912), .Q(n2915) );
AO22X1 U2155 ( .IN1(n1429), .IN2(n967), .IN3(n2917), .IN4(n1437), .Q(
\fpu_add_frac_dp/n3520 ) );
NOR2X0 U2156 ( .IN1(n2918), .IN2(n2919), .QN(n2917) );
AOI21X1 U2157 ( .IN1(n2916), .IN2(n2912), .IN3(n2920), .QN(n2919) );
AO22X1 U2158 ( .IN1(n1419), .IN2(n966), .IN3(n2921), .IN4(n1437), .Q(
\fpu_add_frac_dp/n3519 ) );
XOR2X1 U2159 ( .IN1(n2918), .IN2(n2922), .Q(n2921) );
AO22X1 U2160 ( .IN1(n1416), .IN2(n965), .IN3(n2923), .IN4(n1437), .Q(
\fpu_add_frac_dp/n3518 ) );
NOR2X0 U2161 ( .IN1(n2924), .IN2(n2925), .QN(n2923) );
AOI21X1 U2162 ( .IN1(n2922), .IN2(n2918), .IN3(n2926), .QN(n2925) );
AO22X1 U2163 ( .IN1(n1416), .IN2(n964), .IN3(n2927), .IN4(n1437), .Q(
\fpu_add_frac_dp/n3517 ) );
XOR2X1 U2164 ( .IN1(n2928), .IN2(n2924), .Q(n2927) );
AO22X1 U2165 ( .IN1(n1416), .IN2(n1041), .IN3(n2929), .IN4(n1437), .Q(
\fpu_add_frac_dp/n3516 ) );
NOR2X0 U2166 ( .IN1(n2930), .IN2(n2931), .QN(n2929) );
AOI21X1 U2167 ( .IN1(n2928), .IN2(n2924), .IN3(n2932), .QN(n2931) );
AO22X1 U2168 ( .IN1(n1416), .IN2(n1040), .IN3(n2933), .IN4(n1437), .Q(
\fpu_add_frac_dp/n3515 ) );
XOR2X1 U2169 ( .IN1(n2934), .IN2(n2935), .Q(n2933) );
AO22X1 U2170 ( .IN1(n1416), .IN2(n1039), .IN3(n2936), .IN4(n1437), .Q(
\fpu_add_frac_dp/n3514 ) );
NOR2X0 U2171 ( .IN1(n2937), .IN2(n2938), .QN(n2936) );
OA21X1 U2172 ( .IN1(n2935), .IN2(n2934), .IN3(n2939), .Q(n2938) );
INVX0 U2173 ( .INP(n2940), .ZN(n2935) );
AO22X1 U2174 ( .IN1(n1416), .IN2(n1038), .IN3(n2941), .IN4(n1437), .Q(
\fpu_add_frac_dp/n3513 ) );
XOR2X1 U2175 ( .IN1(n2942), .IN2(n2937), .Q(n2941) );
AO22X1 U2176 ( .IN1(n1416), .IN2(n1037), .IN3(n2943), .IN4(n1437), .Q(
\fpu_add_frac_dp/n3512 ) );
NOR2X0 U2177 ( .IN1(n2944), .IN2(n2945), .QN(n2943) );
AOI21X1 U2178 ( .IN1(n2942), .IN2(n2937), .IN3(n2946), .QN(n2945) );
AO22X1 U2179 ( .IN1(n1416), .IN2(n1036), .IN3(n2947), .IN4(n1437), .Q(
\fpu_add_frac_dp/n3511 ) );
XOR2X1 U2180 ( .IN1(n2944), .IN2(n2948), .Q(n2947) );
AO22X1 U2181 ( .IN1(n1416), .IN2(n1035), .IN3(n2949), .IN4(n1438), .Q(
\fpu_add_frac_dp/n3510 ) );
NOR2X0 U2182 ( .IN1(n2950), .IN2(n2951), .QN(n2949) );
AOI21X1 U2183 ( .IN1(n2948), .IN2(n2944), .IN3(n2952), .QN(n2951) );
AO21X1 U2184 ( .IN1(n1406), .IN2(n1006), .IN3(n2953), .Q(
\fpu_add_frac_dp/n3509 ) );
MUX21X1 U2185 ( .IN1(n2954), .IN2(n2955), .S(n2950), .Q(n2953) );
NOR2X0 U2186 ( .IN1(n1745), .IN2(n2956), .QN(n2955) );
AO22X1 U2187 ( .IN1(n1443), .IN2(n2957), .IN3(n1410), .IN4(n1186), .Q(
\fpu_add_frac_dp/n3508 ) );
AO22X1 U2188 ( .IN1(n1416), .IN2(n65), .IN3(n1442), .IN4(n2958), .Q(
\fpu_add_frac_dp/n3507 ) );
AO21X1 U2189 ( .IN1(n2959), .IN2(n2960), .IN3(n492), .Q(n2958) );
OAI22X1 U2190 ( .IN1(n1745), .IN2(n2959), .IN3(n2046), .IN4(
\fpu_add_frac_dp/n132 ), .QN(\fpu_add_frac_dp/n3506 ) );
AO22X1 U2191 ( .IN1(n1416), .IN2(n1305), .IN3(n1442), .IN4(n2961), .Q(
\fpu_add_frac_dp/n3505 ) );
NAND2X0 U2192 ( .IN1(\fpu_add_ctl/n85 ), .IN2(n2962), .QN(n2961) );
AO22X1 U2193 ( .IN1(n1448), .IN2(n2963), .IN3(n1410), .IN4(n579), .Q(
\fpu_add_frac_dp/n3504 ) );
AO22X1 U2194 ( .IN1(n1417), .IN2(n1248), .IN3(n2954), .IN4(n2950), .Q(
\fpu_add_frac_dp/n3503 ) );
AO22X1 U2195 ( .IN1(n1448), .IN2(n956), .IN3(n1410), .IN4(n544), .Q(
\fpu_add_frac_dp/n3502 ) );
AO22X1 U2196 ( .IN1(n1417), .IN2(n978), .IN3(n1442), .IN4(n2964), .Q(
\fpu_add_frac_dp/n3501 ) );
AO22X1 U2197 ( .IN1(n1449), .IN2(n2965), .IN3(n1410), .IN4(n543), .Q(
\fpu_add_frac_dp/n3500 ) );
AO22X1 U2198 ( .IN1(n1448), .IN2(n2966), .IN3(n1410), .IN4(n542), .Q(
\fpu_add_frac_dp/n3499 ) );
AO22X1 U2199 ( .IN1(n1449), .IN2(n2967), .IN3(n1410), .IN4(n541), .Q(
\fpu_add_frac_dp/n3498 ) );
AO22X1 U2200 ( .IN1(n1448), .IN2(n2968), .IN3(n1410), .IN4(n540), .Q(
\fpu_add_frac_dp/n3497 ) );
AO22X1 U2201 ( .IN1(n1448), .IN2(n2969), .IN3(n1410), .IN4(n539), .Q(
\fpu_add_frac_dp/n3496 ) );
AO22X1 U2202 ( .IN1(n1448), .IN2(n2970), .IN3(n1410), .IN4(n538), .Q(
\fpu_add_frac_dp/n3495 ) );
AO22X1 U2203 ( .IN1(n1448), .IN2(n2971), .IN3(n1410), .IN4(n537), .Q(
\fpu_add_frac_dp/n3494 ) );
AO22X1 U2204 ( .IN1(n1448), .IN2(n2972), .IN3(n1410), .IN4(n536), .Q(
\fpu_add_frac_dp/n3493 ) );
AO22X1 U2205 ( .IN1(n1448), .IN2(n2973), .IN3(n1411), .IN4(n908), .Q(
\fpu_add_frac_dp/n3492 ) );
AO22X1 U2206 ( .IN1(n1746), .IN2(n2786), .IN3(n1411), .IN4(n955), .Q(
\fpu_add_frac_dp/n3491 ) );
AO22X1 U2207 ( .IN1(n1448), .IN2(n2788), .IN3(n1411), .IN4(n954), .Q(
\fpu_add_frac_dp/n3490 ) );
AO22X1 U2208 ( .IN1(n1448), .IN2(n2792), .IN3(n1411), .IN4(n953), .Q(
\fpu_add_frac_dp/n3489 ) );
AO22X1 U2209 ( .IN1(n1448), .IN2(n2794), .IN3(n1411), .IN4(n952), .Q(
\fpu_add_frac_dp/n3488 ) );
AO22X1 U2210 ( .IN1(n1448), .IN2(n2798), .IN3(n1411), .IN4(n951), .Q(
\fpu_add_frac_dp/n3487 ) );
AO22X1 U2211 ( .IN1(n1448), .IN2(n2800), .IN3(n1411), .IN4(n950), .Q(
\fpu_add_frac_dp/n3486 ) );
AO22X1 U2212 ( .IN1(n1746), .IN2(n2974), .IN3(n1411), .IN4(n949), .Q(
\fpu_add_frac_dp/n3485 ) );
AO22X1 U2213 ( .IN1(n1448), .IN2(n2975), .IN3(n1411), .IN4(n948), .Q(
\fpu_add_frac_dp/n3484 ) );
AO22X1 U2214 ( .IN1(n1448), .IN2(n2976), .IN3(n1411), .IN4(n947), .Q(
\fpu_add_frac_dp/n3483 ) );
AO22X1 U2215 ( .IN1(n1448), .IN2(n2815), .IN3(n1411), .IN4(n946), .Q(
\fpu_add_frac_dp/n3482 ) );
AO22X1 U2216 ( .IN1(n1746), .IN2(n2977), .IN3(n1411), .IN4(n945), .Q(
\fpu_add_frac_dp/n3481 ) );
AO22X1 U2217 ( .IN1(n1448), .IN2(n2978), .IN3(n1411), .IN4(n944), .Q(
\fpu_add_frac_dp/n3480 ) );
AO22X1 U2218 ( .IN1(n1746), .IN2(n2979), .IN3(n1411), .IN4(n943), .Q(
\fpu_add_frac_dp/n3479 ) );
AO22X1 U2219 ( .IN1(n1746), .IN2(n2830), .IN3(n1412), .IN4(n942), .Q(
\fpu_add_frac_dp/n3478 ) );
AO22X1 U2220 ( .IN1(n1746), .IN2(n2834), .IN3(n1412), .IN4(n941), .Q(
\fpu_add_frac_dp/n3477 ) );
AO22X1 U2221 ( .IN1(n1746), .IN2(n2836), .IN3(n1412), .IN4(n940), .Q(
\fpu_add_frac_dp/n3476 ) );
AO22X1 U2222 ( .IN1(n1746), .IN2(n2840), .IN3(n1412), .IN4(n939), .Q(
\fpu_add_frac_dp/n3475 ) );
AO22X1 U2223 ( .IN1(n1746), .IN2(n2842), .IN3(n1412), .IN4(n938), .Q(
\fpu_add_frac_dp/n3474 ) );
AO22X1 U2224 ( .IN1(n1447), .IN2(n2846), .IN3(n1412), .IN4(n881), .Q(
\fpu_add_frac_dp/n3473 ) );
AO22X1 U2225 ( .IN1(n1449), .IN2(n2848), .IN3(n1412), .IN4(n880), .Q(
\fpu_add_frac_dp/n3472 ) );
AO22X1 U2226 ( .IN1(n1746), .IN2(n2852), .IN3(n1412), .IN4(n879), .Q(
\fpu_add_frac_dp/n3471 ) );
AO22X1 U2227 ( .IN1(n1449), .IN2(n2854), .IN3(n1412), .IN4(n878), .Q(
\fpu_add_frac_dp/n3470 ) );
AO22X1 U2228 ( .IN1(n1746), .IN2(n2858), .IN3(n1412), .IN4(n877), .Q(
\fpu_add_frac_dp/n3469 ) );
AO22X1 U2229 ( .IN1(n1449), .IN2(n2980), .IN3(n1412), .IN4(n876), .Q(
\fpu_add_frac_dp/n3468 ) );
AO22X1 U2230 ( .IN1(n1449), .IN2(n2981), .IN3(n1412), .IN4(n875), .Q(
\fpu_add_frac_dp/n3467 ) );
AO22X1 U2231 ( .IN1(n1746), .IN2(n2867), .IN3(n1412), .IN4(n874), .Q(
\fpu_add_frac_dp/n3466 ) );
AO22X1 U2232 ( .IN1(n1449), .IN2(n2982), .IN3(n1412), .IN4(n873), .Q(
\fpu_add_frac_dp/n3465 ) );
AO22X1 U2233 ( .IN1(n1447), .IN2(n2881), .IN3(n1413), .IN4(n872), .Q(
\fpu_add_frac_dp/n3464 ) );
AO22X1 U2234 ( .IN1(n1449), .IN2(n2983), .IN3(n1413), .IN4(n871), .Q(
\fpu_add_frac_dp/n3463 ) );
AO22X1 U2235 ( .IN1(n1447), .IN2(n2984), .IN3(n1413), .IN4(n870), .Q(
\fpu_add_frac_dp/n3462 ) );
AO22X1 U2236 ( .IN1(n1447), .IN2(n2888), .IN3(n1413), .IN4(n869), .Q(
\fpu_add_frac_dp/n3461 ) );
AO22X1 U2237 ( .IN1(n1447), .IN2(n2891), .IN3(n1413), .IN4(n868), .Q(
\fpu_add_frac_dp/n3460 ) );
AO22X1 U2238 ( .IN1(n1447), .IN2(n2896), .IN3(n1413), .IN4(n867), .Q(
\fpu_add_frac_dp/n3459 ) );
AO22X1 U2239 ( .IN1(n1447), .IN2(n2898), .IN3(n1413), .IN4(n866), .Q(
\fpu_add_frac_dp/n3458 ) );
AO22X1 U2240 ( .IN1(n1447), .IN2(n2902), .IN3(n1413), .IN4(n865), .Q(
\fpu_add_frac_dp/n3457 ) );
AO22X1 U2241 ( .IN1(n1447), .IN2(n2904), .IN3(n1413), .IN4(n864), .Q(
\fpu_add_frac_dp/n3456 ) );
AO22X1 U2242 ( .IN1(n1447), .IN2(n2908), .IN3(n1413), .IN4(n863), .Q(
\fpu_add_frac_dp/n3455 ) );
AO22X1 U2243 ( .IN1(n1447), .IN2(n2910), .IN3(n1413), .IN4(n862), .Q(
\fpu_add_frac_dp/n3454 ) );
AO22X1 U2244 ( .IN1(n1447), .IN2(n2914), .IN3(n1413), .IN4(n861), .Q(
\fpu_add_frac_dp/n3453 ) );
AO22X1 U2245 ( .IN1(n1447), .IN2(n2916), .IN3(n1413), .IN4(n503), .Q(
\fpu_add_frac_dp/n3452 ) );
AO22X1 U2246 ( .IN1(n1447), .IN2(n2920), .IN3(n1413), .IN4(n502), .Q(
\fpu_add_frac_dp/n3451 ) );
AO22X1 U2247 ( .IN1(n1446), .IN2(n2922), .IN3(n1414), .IN4(n501), .Q(
\fpu_add_frac_dp/n3450 ) );
AO22X1 U2248 ( .IN1(n1447), .IN2(n2926), .IN3(n1414), .IN4(n500), .Q(
\fpu_add_frac_dp/n3449 ) );
AO22X1 U2249 ( .IN1(n1447), .IN2(n2928), .IN3(n1414), .IN4(n499), .Q(
\fpu_add_frac_dp/n3448 ) );
AO22X1 U2250 ( .IN1(n1447), .IN2(n2932), .IN3(n1414), .IN4(n498), .Q(
\fpu_add_frac_dp/n3447 ) );
AO22X1 U2251 ( .IN1(n1446), .IN2(n2940), .IN3(n1414), .IN4(n497), .Q(
\fpu_add_frac_dp/n3446 ) );
AO22X1 U2252 ( .IN1(n1447), .IN2(n2985), .IN3(n1414), .IN4(n496), .Q(
\fpu_add_frac_dp/n3445 ) );
AO22X1 U2253 ( .IN1(n1446), .IN2(n2942), .IN3(n1414), .IN4(n495), .Q(
\fpu_add_frac_dp/n3444 ) );
AO22X1 U2254 ( .IN1(n1446), .IN2(n2946), .IN3(n1414), .IN4(n494), .Q(
\fpu_add_frac_dp/n3443 ) );
AO22X1 U2255 ( .IN1(n1446), .IN2(n2948), .IN3(n1414), .IN4(n860), .Q(
\fpu_add_frac_dp/n3442 ) );
AO22X1 U2256 ( .IN1(n1446), .IN2(n2952), .IN3(n1414), .IN4(n493), .Q(
\fpu_add_frac_dp/n3441 ) );
AO21X1 U2257 ( .IN1(n1405), .IN2(n907), .IN3(n2954), .Q(
\fpu_add_frac_dp/n3440 ) );
NOR2X0 U2258 ( .IN1(n1745), .IN2(n2986), .QN(n2954) );
AO22X1 U2259 ( .IN1(n1446), .IN2(n2987), .IN3(n1406), .IN4(n859), .Q(
\fpu_add_frac_dp/n3439 ) );
AO22X1 U2260 ( .IN1(n1421), .IN2(n925), .IN3(n2988), .IN4(n2989), .Q(
\fpu_add_frac_dp/n3438 ) );
AO22X1 U2261 ( .IN1(n1421), .IN2(n551), .IN3(n2990), .IN4(n2989), .Q(
\fpu_add_frac_dp/n3437 ) );
AO22X1 U2262 ( .IN1(n1421), .IN2(n924), .IN3(n2991), .IN4(n2989), .Q(
\fpu_add_frac_dp/n3436 ) );
AO22X1 U2263 ( .IN1(n1421), .IN2(n923), .IN3(n2992), .IN4(n2989), .Q(
\fpu_add_frac_dp/n3435 ) );
AO22X1 U2264 ( .IN1(n1421), .IN2(n922), .IN3(n2993), .IN4(n2994), .Q(
\fpu_add_frac_dp/n3434 ) );
AO22X1 U2265 ( .IN1(n1421), .IN2(n921), .IN3(n2995), .IN4(n2994), .Q(
\fpu_add_frac_dp/n3433 ) );
AO22X1 U2266 ( .IN1(n1421), .IN2(n920), .IN3(n2996), .IN4(n2994), .Q(
\fpu_add_frac_dp/n3432 ) );
AO22X1 U2267 ( .IN1(n1421), .IN2(n919), .IN3(n2997), .IN4(n2994), .Q(
\fpu_add_frac_dp/n3431 ) );
AO21X1 U2268 ( .IN1(n1405), .IN2(n1003), .IN3(n2998), .Q(
\fpu_add_frac_dp/n3430 ) );
AO21X1 U2269 ( .IN1(n1405), .IN2(n1002), .IN3(n2999), .Q(
\fpu_add_frac_dp/n3429 ) );
AO222X1 U2270 ( .IN1(n3000), .IN2(n2994), .IN3(n3001), .IN4(n2991), .IN5(
n1379), .IN6(n535), .Q(\fpu_add_frac_dp/n3428 ) );
AO222X1 U2271 ( .IN1(n3002), .IN2(n2994), .IN3(n3001), .IN4(n2992), .IN5(
n1379), .IN6(n534), .Q(\fpu_add_frac_dp/n3427 ) );
AO222X1 U2272 ( .IN1(n3003), .IN2(n2993), .IN3(n3004), .IN4(n2994), .IN5(
n1379), .IN6(n533), .Q(\fpu_add_frac_dp/n3426 ) );
AO222X1 U2273 ( .IN1(n3003), .IN2(n2995), .IN3(n3005), .IN4(n2994), .IN5(
n1379), .IN6(n532), .Q(\fpu_add_frac_dp/n3425 ) );
AO222X1 U2274 ( .IN1(n3003), .IN2(n2996), .IN3(n3006), .IN4(n2994), .IN5(
n1379), .IN6(n531), .Q(\fpu_add_frac_dp/n3424 ) );
AO222X1 U2275 ( .IN1(n3003), .IN2(n2997), .IN3(n3007), .IN4(n2994), .IN5(
n1379), .IN6(n530), .Q(\fpu_add_frac_dp/n3423 ) );
AO222X1 U2276 ( .IN1(n3008), .IN2(n3003), .IN3(n3009), .IN4(n2994), .IN5(
n1379), .IN6(n529), .Q(\fpu_add_frac_dp/n3422 ) );
AO222X1 U2277 ( .IN1(n3010), .IN2(n3003), .IN3(n3011), .IN4(n2994), .IN5(
n1379), .IN6(n528), .Q(\fpu_add_frac_dp/n3421 ) );
AO222X1 U2278 ( .IN1(n3000), .IN2(n3003), .IN3(n3012), .IN4(n2994), .IN5(
n1380), .IN6(n527), .Q(\fpu_add_frac_dp/n3420 ) );
AO222X1 U2279 ( .IN1(n3002), .IN2(n3003), .IN3(n3013), .IN4(n2994), .IN5(
n1380), .IN6(n526), .Q(\fpu_add_frac_dp/n3419 ) );
AO222X1 U2280 ( .IN1(n3004), .IN2(n3003), .IN3(n3014), .IN4(n2994), .IN5(
n1380), .IN6(n525), .Q(\fpu_add_frac_dp/n3418 ) );
AO222X1 U2281 ( .IN1(n3005), .IN2(n3003), .IN3(n2994), .IN4(n3015), .IN5(
n1380), .IN6(n524), .Q(\fpu_add_frac_dp/n3417 ) );
AO222X1 U2282 ( .IN1(n3006), .IN2(n3003), .IN3(n2994), .IN4(n3016), .IN5(
n1380), .IN6(n523), .Q(\fpu_add_frac_dp/n3416 ) );
AO222X1 U2283 ( .IN1(n3007), .IN2(n3003), .IN3(n2994), .IN4(n3017), .IN5(
n1380), .IN6(n522), .Q(\fpu_add_frac_dp/n3415 ) );
AO222X1 U2284 ( .IN1(n3009), .IN2(n3003), .IN3(n2994), .IN4(n3018), .IN5(
n1380), .IN6(n521), .Q(\fpu_add_frac_dp/n3414 ) );
AO222X1 U2285 ( .IN1(n3011), .IN2(n3003), .IN3(n2994), .IN4(n3019), .IN5(
n1380), .IN6(n520), .Q(\fpu_add_frac_dp/n3413 ) );
AO222X1 U2286 ( .IN1(n3012), .IN2(n3003), .IN3(n2994), .IN4(n3020), .IN5(
n1380), .IN6(n519), .Q(\fpu_add_frac_dp/n3412 ) );
AO222X1 U2287 ( .IN1(n3013), .IN2(n3003), .IN3(n2994), .IN4(n3021), .IN5(
n1380), .IN6(n518), .Q(\fpu_add_frac_dp/n3411 ) );
AO222X1 U2288 ( .IN1(n3014), .IN2(n3003), .IN3(n2994), .IN4(n3022), .IN5(
n1380), .IN6(n517), .Q(\fpu_add_frac_dp/n3410 ) );
AO222X1 U2289 ( .IN1(n3003), .IN2(n3015), .IN3(n2994), .IN4(n3023), .IN5(
n1380), .IN6(n489), .Q(\fpu_add_frac_dp/n3409 ) );
AO222X1 U2290 ( .IN1(n3003), .IN2(n3016), .IN3(n2994), .IN4(n3024), .IN5(
n1381), .IN6(n488), .Q(\fpu_add_frac_dp/n3408 ) );
AO222X1 U2291 ( .IN1(n3003), .IN2(n3017), .IN3(n2994), .IN4(n3025), .IN5(
n1381), .IN6(n487), .Q(\fpu_add_frac_dp/n3407 ) );
AO222X1 U2292 ( .IN1(n3003), .IN2(n3018), .IN3(n2994), .IN4(n3026), .IN5(
n1381), .IN6(n486), .Q(\fpu_add_frac_dp/n3406 ) );
AO222X1 U2293 ( .IN1(n3003), .IN2(n3019), .IN3(n2994), .IN4(n3027), .IN5(
n1381), .IN6(n485), .Q(\fpu_add_frac_dp/n3405 ) );
AO222X1 U2294 ( .IN1(n3003), .IN2(n3020), .IN3(n2994), .IN4(n3028), .IN5(
n1381), .IN6(n484), .Q(\fpu_add_frac_dp/n3404 ) );
AO222X1 U2295 ( .IN1(n3003), .IN2(n3021), .IN3(n2994), .IN4(n3029), .IN5(
n1381), .IN6(n483), .Q(\fpu_add_frac_dp/n3403 ) );
AO222X1 U2296 ( .IN1(n3003), .IN2(n3022), .IN3(n2994), .IN4(n3030), .IN5(
n1381), .IN6(n482), .Q(\fpu_add_frac_dp/n3402 ) );
AO222X1 U2297 ( .IN1(n3003), .IN2(n3023), .IN3(n2994), .IN4(n3031), .IN5(
n1381), .IN6(n481), .Q(\fpu_add_frac_dp/n3401 ) );
AO222X1 U2298 ( .IN1(n3003), .IN2(n3024), .IN3(n2994), .IN4(n3032), .IN5(
n1381), .IN6(n480), .Q(\fpu_add_frac_dp/n3400 ) );
AO222X1 U2299 ( .IN1(n3003), .IN2(n3025), .IN3(n2994), .IN4(n3033), .IN5(
n1381), .IN6(n479), .Q(\fpu_add_frac_dp/n3399 ) );
AO222X1 U2300 ( .IN1(n3003), .IN2(n3026), .IN3(n2994), .IN4(n3034), .IN5(
n1381), .IN6(n478), .Q(\fpu_add_frac_dp/n3398 ) );
AO222X1 U2301 ( .IN1(n3003), .IN2(n3027), .IN3(n2994), .IN4(n3035), .IN5(
n1381), .IN6(n477), .Q(\fpu_add_frac_dp/n3397 ) );
AO222X1 U2302 ( .IN1(n3003), .IN2(n3028), .IN3(n2994), .IN4(n3036), .IN5(
n1382), .IN6(n476), .Q(\fpu_add_frac_dp/n3396 ) );
AO222X1 U2303 ( .IN1(n3003), .IN2(n3029), .IN3(n2994), .IN4(n3037), .IN5(
n1382), .IN6(n475), .Q(\fpu_add_frac_dp/n3395 ) );
AO222X1 U2304 ( .IN1(n3003), .IN2(n3030), .IN3(n2994), .IN4(n3038), .IN5(
n1382), .IN6(n474), .Q(\fpu_add_frac_dp/n3394 ) );
AO222X1 U2305 ( .IN1(n3003), .IN2(n3031), .IN3(n2994), .IN4(n3039), .IN5(
n1382), .IN6(n473), .Q(\fpu_add_frac_dp/n3393 ) );
AO222X1 U2306 ( .IN1(n3003), .IN2(n3032), .IN3(n2994), .IN4(n3040), .IN5(
n1382), .IN6(n472), .Q(\fpu_add_frac_dp/n3392 ) );
AO222X1 U2307 ( .IN1(n3003), .IN2(n3033), .IN3(n2994), .IN4(n3041), .IN5(
n1382), .IN6(n471), .Q(\fpu_add_frac_dp/n3391 ) );
AO222X1 U2308 ( .IN1(n3003), .IN2(n3034), .IN3(n2994), .IN4(n3042), .IN5(
n1382), .IN6(n470), .Q(\fpu_add_frac_dp/n3390 ) );
AO222X1 U2309 ( .IN1(n3003), .IN2(n3035), .IN3(n2994), .IN4(n3043), .IN5(
n1382), .IN6(n469), .Q(\fpu_add_frac_dp/n3389 ) );
AO222X1 U2310 ( .IN1(n3003), .IN2(n3036), .IN3(n3044), .IN4(n2994), .IN5(
n1382), .IN6(n913), .Q(\fpu_add_frac_dp/n3388 ) );
AO222X1 U2311 ( .IN1(n3003), .IN2(n3037), .IN3(n3045), .IN4(n2994), .IN5(
n1382), .IN6(n912), .Q(\fpu_add_frac_dp/n3387 ) );
AO222X1 U2312 ( .IN1(n3003), .IN2(n3038), .IN3(n3046), .IN4(n2994), .IN5(
n1382), .IN6(n911), .Q(\fpu_add_frac_dp/n3386 ) );
AO222X1 U2313 ( .IN1(n3003), .IN2(n3039), .IN3(n2994), .IN4(n3047), .IN5(
n1382), .IN6(n910), .Q(\fpu_add_frac_dp/n3385 ) );
AO222X1 U2314 ( .IN1(n3003), .IN2(n3040), .IN3(n3048), .IN4(n2994), .IN5(
n1383), .IN6(n909), .Q(\fpu_add_frac_dp/n3384 ) );
AO222X1 U2315 ( .IN1(n3003), .IN2(n3041), .IN3(n3049), .IN4(n2994), .IN5(
n1383), .IN6(n918), .Q(\fpu_add_frac_dp/n3383 ) );
AO22X1 U2316 ( .IN1(n1421), .IN2(n1064), .IN3(n1442), .IN4(n3050), .Q(
\fpu_add_frac_dp/n3382 ) );
AO221X1 U2317 ( .IN1(n3003), .IN2(n3043), .IN3(n1393), .IN4(n906), .IN5(
n3051), .Q(\fpu_add_frac_dp/n3381 ) );
AO22X1 U2318 ( .IN1(n2989), .IN2(n3052), .IN3(n3053), .IN4(n3054), .Q(n3051)
);
AO21X1 U2319 ( .IN1(n1404), .IN2(n1034), .IN3(n3055), .Q(
\fpu_add_frac_dp/n3380 ) );
AO21X1 U2320 ( .IN1(n1404), .IN2(n933), .IN3(n3056), .Q(
\fpu_add_frac_dp/n3379 ) );
AO221X1 U2321 ( .IN1(n3046), .IN2(n3003), .IN3(n1393), .IN4(n466), .IN5(
n3057), .Q(\fpu_add_frac_dp/n3378 ) );
AO22X1 U2322 ( .IN1(n3053), .IN2(n3058), .IN3(n2989), .IN4(n3059), .Q(n3057)
);
INVX0 U2323 ( .INP(n3060), .ZN(n3059) );
AO22X1 U2324 ( .IN1(n1421), .IN2(n963), .IN3(n1442), .IN4(n3061), .Q(
\fpu_add_frac_dp/n3377 ) );
AO222X1 U2325 ( .IN1(n3048), .IN2(n3003), .IN3(n1435), .IN4(n3062), .IN5(
n1383), .IN6(n468), .Q(\fpu_add_frac_dp/n3376 ) );
AO222X1 U2326 ( .IN1(n3049), .IN2(n3003), .IN3(n1435), .IN4(n3063), .IN5(
n1383), .IN6(n467), .Q(\fpu_add_frac_dp/n3375 ) );
INVX0 U2327 ( .INP(n3064), .ZN(\fpu_add_frac_dp/n1574 ) );
AOI222X1 U2328 ( .IN1(\fpu_add_frac_dp/n1569 ), .IN2(n3065), .IN3(n2997),
.IN4(n3066), .IN5(n2970), .IN6(n1389), .QN(\fpu_add_frac_dp/n1007 ) );
AOI222X1 U2329 ( .IN1(n3065), .IN2(\fpu_add_frac_dp/n1568 ), .IN3(n2998),
.IN4(\fpu_add_ctl/n319 ), .IN5(n2971), .IN6(n1389), .QN(
\fpu_add_frac_dp/n1006 ) );
AO22X1 U2330 ( .IN1(n3008), .IN2(n2994), .IN3(n3001), .IN4(n2988), .Q(n2998)
);
INVX0 U2331 ( .INP(n3067), .ZN(\fpu_add_frac_dp/n1568 ) );
AOI222X1 U2332 ( .IN1(n3065), .IN2(\fpu_add_frac_dp/n1567 ), .IN3(n2999),
.IN4(\fpu_add_ctl/n319 ), .IN5(n2972), .IN6(n1389), .QN(
\fpu_add_frac_dp/n1005 ) );
AO22X1 U2333 ( .IN1(n3010), .IN2(n2994), .IN3(n3001), .IN4(n2990), .Q(n2999)
);
AND2X1 U2334 ( .IN1(n3003), .IN2(\fpu_add_frac_dp/n2471 ), .Q(n3001) );
INVX0 U2335 ( .INP(n3068), .ZN(\fpu_add_frac_dp/n1567 ) );
AOI222X1 U2336 ( .IN1(n3065), .IN2(\fpu_add_frac_dp/a3stg_fracadd[0] ),
.IN3(n2990), .IN4(n3069), .IN5(n2964), .IN6(n1389), .QN(
\fpu_add_frac_dp/n1004 ) );
INVX0 U2337 ( .INP(n3070), .ZN(n2990) );
OA222X1 U2338 ( .IN1(n3071), .IN2(n3064), .IN3(n3072), .IN4(n3073), .IN5(
n3074), .IN6(n2046), .Q(\fpu_add_frac_dp/n1003 ) );
AOI222X1 U2339 ( .IN1(n3065), .IN2(\fpu_add_frac_dp/n1573 ), .IN3(n2992),
.IN4(n3069), .IN5(n2966), .IN6(n1389), .QN(\fpu_add_frac_dp/n1002 ) );
INVX0 U2340 ( .INP(n3075), .ZN(\fpu_add_frac_dp/n1573 ) );
AOI222X1 U2341 ( .IN1(n3065), .IN2(\fpu_add_frac_dp/n1572 ), .IN3(n2993),
.IN4(n3066), .IN5(n2967), .IN6(n1389), .QN(\fpu_add_frac_dp/n1001 ) );
INVX0 U2342 ( .INP(n3076), .ZN(\fpu_add_frac_dp/n1572 ) );
NOR2X0 U2343 ( .IN1(n3077), .IN2(n3078), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N9 ) );
NOR2X0 U2344 ( .IN1(n3077), .IN2(n3079), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N8 ) );
NOR2X0 U2345 ( .IN1(n3077), .IN2(n3076), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N7 ) );
XNOR3X1 U2346 ( .IN1(\fpu_add_frac_dp/n732 ), .IN2(\fpu_add_frac_dp/n505 ),
.IN3(n3080), .Q(n3076) );
INVX0 U2347 ( .INP(n3081), .ZN(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N66 )
);
NOR2X0 U2348 ( .IN1(n3077), .IN2(n2602), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N65 ) );
NOR2X0 U2349 ( .IN1(n3077), .IN2(n3082), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N64 ) );
NOR2X0 U2350 ( .IN1(n3077), .IN2(n3083), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N63 ) );
NOR2X0 U2351 ( .IN1(n3077), .IN2(n3084), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N62 ) );
NOR2X0 U2352 ( .IN1(n3077), .IN2(n3085), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N61 ) );
NOR2X0 U2353 ( .IN1(n3077), .IN2(n3086), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N60 ) );
NOR2X0 U2354 ( .IN1(n3077), .IN2(n3075), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N6 ) );
XNOR3X1 U2355 ( .IN1(\fpu_add_frac_dp/n733 ), .IN2(\fpu_add_frac_dp/n504 ),
.IN3(n3087), .Q(n3075) );
NOR2X0 U2356 ( .IN1(n3077), .IN2(n3088), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N59 ) );
NOR2X0 U2357 ( .IN1(n3077), .IN2(n3089), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N58 ) );
NOR2X0 U2358 ( .IN1(n3077), .IN2(n3090), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N57 ) );
NOR2X0 U2359 ( .IN1(n3077), .IN2(n3091), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N56 ) );
NOR2X0 U2360 ( .IN1(n3077), .IN2(n3092), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N55 ) );
NOR2X0 U2361 ( .IN1(n3077), .IN2(n3093), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N54 ) );
NOR2X0 U2362 ( .IN1(n3077), .IN2(n3094), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N53 ) );
NOR2X0 U2363 ( .IN1(n3077), .IN2(n3095), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N52 ) );
NOR2X0 U2364 ( .IN1(n3077), .IN2(n3096), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N51 ) );
NOR2X0 U2365 ( .IN1(n3077), .IN2(n3097), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N50 ) );
NOR2X0 U2366 ( .IN1(n3077), .IN2(n3064), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N5 ) );
XNOR3X1 U2367 ( .IN1(\fpu_add_frac_dp/n734 ), .IN2(\fpu_add_frac_dp/n503 ),
.IN3(n3098), .Q(n3064) );
NOR2X0 U2368 ( .IN1(n3077), .IN2(n3099), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N49 ) );
NOR2X0 U2369 ( .IN1(n3077), .IN2(n3100), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N48 ) );
NOR2X0 U2370 ( .IN1(n3077), .IN2(n3101), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N47 ) );
NOR2X0 U2371 ( .IN1(n3077), .IN2(n3102), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N46 ) );
NOR2X0 U2372 ( .IN1(n3077), .IN2(n3103), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N45 ) );
NOR2X0 U2373 ( .IN1(n3077), .IN2(n3104), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N44 ) );
NOR2X0 U2374 ( .IN1(n3077), .IN2(n3105), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N43 ) );
NOR2X0 U2375 ( .IN1(n3077), .IN2(n3106), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N42 ) );
NOR2X0 U2376 ( .IN1(n3077), .IN2(n3107), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N41 ) );
NOR2X0 U2377 ( .IN1(n3077), .IN2(n3108), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N40 ) );
NOR2X0 U2378 ( .IN1(n3077), .IN2(n3109), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N4 ) );
INVX0 U2379 ( .INP(\fpu_add_frac_dp/a3stg_fracadd[0] ), .ZN(n3109) );
NOR2X0 U2380 ( .IN1(n3077), .IN2(n3110), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N39 ) );
NOR2X0 U2381 ( .IN1(n3077), .IN2(n3111), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N38 ) );
NOR2X0 U2382 ( .IN1(n3077), .IN2(n3112), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N37 ) );
NOR2X0 U2383 ( .IN1(n3077), .IN2(n3113), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N36 ) );
NOR2X0 U2384 ( .IN1(n3077), .IN2(n3114), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N35 ) );
NOR2X0 U2385 ( .IN1(n3077), .IN2(n3115), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N34 ) );
NOR2X0 U2386 ( .IN1(n3077), .IN2(n3116), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N33 ) );
NOR2X0 U2387 ( .IN1(n3077), .IN2(n3117), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N32 ) );
NOR2X0 U2388 ( .IN1(n3077), .IN2(n3118), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N31 ) );
NOR2X0 U2389 ( .IN1(n3077), .IN2(n3119), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N30 ) );
NOR2X0 U2390 ( .IN1(n3077), .IN2(n3120), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N29 ) );
NOR2X0 U2391 ( .IN1(n3077), .IN2(n3121), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N28 ) );
NOR2X0 U2392 ( .IN1(n3077), .IN2(n3122), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N27 ) );
NOR2X0 U2393 ( .IN1(n3077), .IN2(n3123), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N26 ) );
NOR2X0 U2394 ( .IN1(n3077), .IN2(n3124), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N25 ) );
NOR2X0 U2395 ( .IN1(n3077), .IN2(n3125), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N24 ) );
NOR2X0 U2396 ( .IN1(n3077), .IN2(n3126), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N23 ) );
NOR2X0 U2397 ( .IN1(n3077), .IN2(n3127), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N22 ) );
NOR2X0 U2398 ( .IN1(n3077), .IN2(n3128), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N21 ) );
NOR2X0 U2399 ( .IN1(n3077), .IN2(n3129), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N20 ) );
NOR2X0 U2400 ( .IN1(n3077), .IN2(n3130), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N19 ) );
NOR2X0 U2401 ( .IN1(n3077), .IN2(n3131), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N18 ) );
NOR2X0 U2402 ( .IN1(n3077), .IN2(n3132), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N17 ) );
NOR2X0 U2403 ( .IN1(n3077), .IN2(n3133), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N16 ) );
NOR2X0 U2404 ( .IN1(n3077), .IN2(n3134), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N15 ) );
NOR2X0 U2405 ( .IN1(n3077), .IN2(n3135), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N14 ) );
NOR2X0 U2406 ( .IN1(n3077), .IN2(n3136), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N13 ) );
NOR2X0 U2407 ( .IN1(n3077), .IN2(n3068), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N12 ) );
XNOR3X1 U2408 ( .IN1(\fpu_add_frac_dp/n727 ), .IN2(\fpu_add_frac_dp/n502 ),
.IN3(n3137), .Q(n3068) );
NOR2X0 U2409 ( .IN1(n3077), .IN2(n3067), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N11 ) );
XNOR3X1 U2410 ( .IN1(\fpu_add_frac_dp/n728 ), .IN2(\fpu_add_frac_dp/n501 ),
.IN3(n3138), .Q(n3067) );
NOR2X0 U2411 ( .IN1(n3077), .IN2(n3139), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre3/N10 ) );
AND2X1 U2412 ( .IN1(n3140), .IN2(n3081), .Q(n3077) );
NAND4X0 U2413 ( .IN1(n3141), .IN2(n3142), .IN3(n3143), .IN4(n3144), .QN(
n3081) );
NAND4X0 U2414 ( .IN1(n2601), .IN2(n583), .IN3(n3142), .IN4(n3145), .QN(n3140) );
NOR2X0 U2415 ( .IN1(n3146), .IN2(n2602), .QN(n3145) );
AO221X1 U2416 ( .IN1(\fpu_add_frac_dp/n1569 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(\fpu_add_frac_dp/n1570 ), .IN4(n3065), .IN5(n3147), .Q(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N9 ) );
AO22X1 U2417 ( .IN1(n1421), .IN2(n2969), .IN3(n3066), .IN4(n2996), .Q(n3147)
);
INVX0 U2418 ( .INP(n3139), .ZN(\fpu_add_frac_dp/n1569 ) );
XNOR3X1 U2419 ( .IN1(\fpu_add_frac_dp/n729 ), .IN2(\fpu_add_frac_dp/n507 ),
.IN3(n3148), .Q(n3139) );
AO221X1 U2420 ( .IN1(\fpu_add_frac_dp/n1570 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(\fpu_add_frac_dp/n1571 ), .IN4(n3065), .IN5(n3149), .Q(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N8 ) );
AO22X1 U2421 ( .IN1(n1421), .IN2(n2968), .IN3(n3066), .IN4(n2995), .Q(n3149)
);
INVX0 U2422 ( .INP(n3079), .ZN(\fpu_add_frac_dp/n1571 ) );
XNOR3X1 U2423 ( .IN1(\fpu_add_frac_dp/n731 ), .IN2(\fpu_add_frac_dp/n506 ),
.IN3(n3150), .Q(n3079) );
INVX0 U2424 ( .INP(n3078), .ZN(\fpu_add_frac_dp/n1570 ) );
XNOR3X1 U2425 ( .IN1(\fpu_add_frac_dp/n730 ), .IN2(\fpu_add_frac_dp/n508 ),
.IN3(n3151), .Q(n3078) );
NAND2X0 U2426 ( .IN1(n3152), .IN2(n3153), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N66 ) );
OA221X1 U2427 ( .IN1(n3154), .IN2(n3155), .IN3(n3143), .IN4(n3156), .IN5(
n3157), .Q(n3153) );
INVX0 U2428 ( .INP(n3063), .ZN(n3154) );
AO22X1 U2429 ( .IN1(n3158), .IN2(n3159), .IN3(n3160), .IN4(n3161), .Q(n3063)
);
OA22X1 U2430 ( .IN1(n3162), .IN2(n3163), .IN3(n3164), .IN4(n3165), .Q(n3161)
);
AO21X1 U2431 ( .IN1(n729), .IN2(n2586), .IN3(n3166), .Q(n3163) );
AO222X1 U2432 ( .IN1(n451), .IN2(n14), .IN3(n846), .IN4(n2591), .IN5(n130),
.IN6(n2), .Q(n3162) );
NOR2X0 U2433 ( .IN1(n3167), .IN2(n3168), .QN(n3160) );
OA21X1 U2434 ( .IN1(n3169), .IN2(n3170), .IN3(n582), .Q(n3167) );
OA222X1 U2435 ( .IN1(n3071), .IN2(n3171), .IN3(n3172), .IN4(n3173), .IN5(
n3174), .IN6(n2046), .Q(n3152) );
AO221X1 U2436 ( .IN1(n3141), .IN2(\fpu_add_frac_dp/n1509 ), .IN3(n3175),
.IN4(n3065), .IN5(n3176), .Q(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N65 ) );
AO222X1 U2437 ( .IN1(n3177), .IN2(n3048), .IN3(n3178), .IN4(n3062), .IN5(
n1384), .IN6(n2956), .Q(n3176) );
AO22X1 U2438 ( .IN1(n3158), .IN2(n3179), .IN3(n3180), .IN4(n3181), .Q(n3062)
);
OA22X1 U2439 ( .IN1(n3164), .IN2(n3182), .IN3(n3166), .IN4(n3165), .Q(n3181)
);
AO221X1 U2440 ( .IN1(n45), .IN2(n2), .IN3(n726), .IN4(n2586), .IN5(n3183),
.Q(n3165) );
AO22X1 U2441 ( .IN1(n456), .IN2(n14), .IN3(n831), .IN4(n2591), .Q(n3183) );
NOR2X0 U2442 ( .IN1(n3184), .IN2(n3168), .QN(n3180) );
AOI21X1 U2443 ( .IN1(n3185), .IN2(n3186), .IN3(\fpu_add_frac_dp/n2460 ),
.QN(n3184) );
AO221X1 U2444 ( .IN1(n1389), .IN2(n2952), .IN3(n3175), .IN4(
\fpu_add_frac_dp/n1509 ), .IN5(n3187), .Q(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N64 ) );
AO22X1 U2445 ( .IN1(\fpu_add_frac_dp/n1515 ), .IN2(n3065), .IN3(n3178),
.IN4(n3061), .Q(n3187) );
AO222X1 U2446 ( .IN1(n3158), .IN2(n3052), .IN3(n3188), .IN4(n3189), .IN5(
n3047), .IN6(n584), .Q(n3061) );
MUX21X1 U2447 ( .IN1(n3190), .IN2(n3191), .S(\fpu_add_frac_dp/n2460 ), .Q(
n3188) );
NOR2X0 U2448 ( .IN1(n3169), .IN2(n3170), .QN(n3191) );
NOR2X0 U2449 ( .IN1(n3182), .IN2(n154), .QN(n3170) );
AO221X1 U2450 ( .IN1(n257), .IN2(n2), .IN3(n727), .IN4(n2586), .IN5(n3192),
.Q(n3182) );
AO22X1 U2451 ( .IN1(n457), .IN2(n14), .IN3(n832), .IN4(n2591), .Q(n3192) );
AND2X1 U2452 ( .IN1(n3193), .IN2(n154), .Q(n3169) );
AND2X1 U2453 ( .IN1(n3194), .IN2(n3195), .Q(n3190) );
INVX0 U2454 ( .INP(n3196), .ZN(n3052) );
INVX0 U2455 ( .INP(n3082), .ZN(\fpu_add_frac_dp/n1515 ) );
AO221X1 U2456 ( .IN1(n3197), .IN2(n3046), .IN3(n1392), .IN4(n2948), .IN5(
n3198), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N63 ) );
OAI222X1 U2457 ( .IN1(n3199), .IN2(n3082), .IN3(n3200), .IN4(n3155), .IN5(
n3071), .IN6(n3083), .QN(n3198) );
OA22X1 U2458 ( .IN1(n3060), .IN2(n3168), .IN3(n3201), .IN4(n3202), .Q(n3200)
);
MUX21X1 U2459 ( .IN1(n3203), .IN2(n3204), .S(\fpu_add_frac_dp/n2460 ), .Q(
n3060) );
NAND2X0 U2460 ( .IN1(n3186), .IN2(n3185), .QN(n3204) );
NAND2X0 U2461 ( .IN1(n3205), .IN2(n154), .QN(n3185) );
NAND2X0 U2462 ( .IN1(n3193), .IN2(\fpu_add_frac_dp/n2449 ), .QN(n3186) );
AOI221X1 U2463 ( .IN1(n107), .IN2(n2), .IN3(n751), .IN4(n2586), .IN5(n3206),
.QN(n3193) );
AO22X1 U2464 ( .IN1(n464), .IN2(n14), .IN3(n843), .IN4(n2591), .Q(n3206) );
XNOR3X1 U2465 ( .IN1(\fpu_add_frac_dp/n675 ), .IN2(\fpu_add_frac_dp/n566 ),
.IN3(n3207), .Q(n3082) );
AO221X1 U2466 ( .IN1(\fpu_add_ctl/n319 ), .IN2(n3056), .IN3(
\fpu_add_frac_dp/n1516 ), .IN4(\fpu_add_frac_dp/n1509 ), .IN5(n3208),
.Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N62 ) );
AO22X1 U2467 ( .IN1(n1421), .IN2(n2946), .IN3(\fpu_add_frac_dp/n1517 ),
.IN4(n3065), .Q(n3208) );
INVX0 U2468 ( .INP(n3083), .ZN(\fpu_add_frac_dp/n1516 ) );
XNOR3X1 U2469 ( .IN1(\fpu_add_frac_dp/n676 ), .IN2(\fpu_add_frac_dp/n565 ),
.IN3(n3209), .Q(n3083) );
AO222X1 U2470 ( .IN1(n2989), .IN2(n3159), .IN3(n3210), .IN4(n3053), .IN5(
n3045), .IN6(n3003), .Q(n3056) );
MUX21X1 U2471 ( .IN1(n3211), .IN2(n3212), .S(\fpu_add_frac_dp/n2460 ), .Q(
n3210) );
AND2X1 U2472 ( .IN1(n3213), .IN2(n3214), .Q(n3212) );
INVX0 U2473 ( .INP(n3215), .ZN(n3159) );
MUX21X1 U2474 ( .IN1(n3216), .IN2(n3217), .S(\fpu_add_frac_dp/n2460 ), .Q(
n3215) );
NAND2X0 U2475 ( .IN1(n3195), .IN2(n3194), .QN(n3217) );
NAND2X0 U2476 ( .IN1(n3218), .IN2(n154), .QN(n3194) );
NAND2X0 U2477 ( .IN1(n3205), .IN2(\fpu_add_frac_dp/n2449 ), .QN(n3195) );
AOI221X1 U2478 ( .IN1(n264), .IN2(n2), .IN3(n749), .IN4(n2586), .IN5(n3219),
.QN(n3205) );
AO22X1 U2479 ( .IN1(n461), .IN2(n14), .IN3(n840), .IN4(n2591), .Q(n3219) );
AO221X1 U2480 ( .IN1(\fpu_add_ctl/n319 ), .IN2(n3055), .IN3(
\fpu_add_frac_dp/n1517 ), .IN4(\fpu_add_frac_dp/n1509 ), .IN5(n3220),
.Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N61 ) );
AO22X1 U2481 ( .IN1(n1422), .IN2(n2942), .IN3(\fpu_add_frac_dp/n1518 ),
.IN4(n3065), .Q(n3220) );
INVX0 U2482 ( .INP(n3085), .ZN(\fpu_add_frac_dp/n1518 ) );
INVX0 U2483 ( .INP(n3084), .ZN(\fpu_add_frac_dp/n1517 ) );
XNOR3X1 U2484 ( .IN1(\fpu_add_frac_dp/n677 ), .IN2(\fpu_add_frac_dp/n564 ),
.IN3(n3221), .Q(n3084) );
AO222X1 U2485 ( .IN1(n2989), .IN2(n3179), .IN3(n3222), .IN4(n3053), .IN5(
n3044), .IN6(n3003), .Q(n3055) );
NOR2X0 U2486 ( .IN1(n3202), .IN2(n1745), .QN(n3053) );
MUX21X1 U2487 ( .IN1(n3223), .IN2(n3224), .S(\fpu_add_frac_dp/n2460 ), .Q(
n3222) );
AND2X1 U2488 ( .IN1(n3225), .IN2(n3226), .Q(n3224) );
INVX0 U2489 ( .INP(n3227), .ZN(n3179) );
MUX21X1 U2490 ( .IN1(n3228), .IN2(n3203), .S(\fpu_add_frac_dp/n2460 ), .Q(
n3227) );
NAND2X0 U2491 ( .IN1(n3229), .IN2(n3230), .QN(n3203) );
NAND2X0 U2492 ( .IN1(n3231), .IN2(n154), .QN(n3230) );
NAND2X0 U2493 ( .IN1(n3218), .IN2(\fpu_add_frac_dp/n2449 ), .QN(n3229) );
AOI221X1 U2494 ( .IN1(n766), .IN2(n14), .IN3(n448), .IN4(n2586), .IN5(n3232),
.QN(n3218) );
AO22X1 U2495 ( .IN1(n119), .IN2(n2), .IN3(n833), .IN4(n2591), .Q(n3232) );
NAND2X0 U2496 ( .IN1(n3233), .IN2(n3234), .QN(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N60 ) );
OA222X1 U2497 ( .IN1(n3199), .IN2(n3085), .IN3(n3155), .IN4(n3235), .IN5(
n3196), .IN6(n3073), .Q(n3234) );
MUX21X1 U2498 ( .IN1(n3236), .IN2(n3216), .S(\fpu_add_frac_dp/n2460 ), .Q(
n3196) );
NAND2X0 U2499 ( .IN1(n3237), .IN2(n3238), .QN(n3216) );
NAND2X0 U2500 ( .IN1(n3239), .IN2(n154), .QN(n3238) );
NAND2X0 U2501 ( .IN1(n3231), .IN2(\fpu_add_frac_dp/n2449 ), .QN(n3237) );
AOI221X1 U2502 ( .IN1(n285), .IN2(n2), .IN3(n748), .IN4(n2586), .IN5(n3240),
.QN(n3231) );
AO22X1 U2503 ( .IN1(n462), .IN2(n14), .IN3(n834), .IN4(n2591), .Q(n3240) );
NAND2X0 U2504 ( .IN1(n3054), .IN2(n3158), .QN(n3235) );
XNOR3X1 U2505 ( .IN1(\fpu_add_frac_dp/n678 ), .IN2(\fpu_add_frac_dp/n563 ),
.IN3(n3241), .Q(n3085) );
INVX0 U2506 ( .INP(\fpu_add_frac_dp/n1509 ), .ZN(n3199) );
OA222X1 U2507 ( .IN1(n2939), .IN2(n2046), .IN3(n3071), .IN4(n3086), .IN5(
n3242), .IN6(n3173), .Q(n3233) );
INVX0 U2508 ( .INP(n2985), .ZN(n2939) );
AO221X1 U2509 ( .IN1(n3178), .IN2(n3050), .IN3(\fpu_add_frac_dp/n1519 ),
.IN4(\fpu_add_frac_dp/n1509 ), .IN5(n3243), .Q(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N59 ) );
AO22X1 U2510 ( .IN1(n1422), .IN2(n2940), .IN3(\fpu_add_frac_dp/n1520 ),
.IN4(n3065), .Q(n3243) );
INVX0 U2511 ( .INP(n3086), .ZN(\fpu_add_frac_dp/n1519 ) );
XNOR3X1 U2512 ( .IN1(\fpu_add_frac_dp/n679 ), .IN2(\fpu_add_frac_dp/n562 ),
.IN3(n3244), .Q(n3086) );
AO222X1 U2513 ( .IN1(n3189), .IN2(n3058), .IN3(n3245), .IN4(n3158), .IN5(
n3042), .IN6(n584), .Q(n3050) );
INVX0 U2514 ( .INP(n3202), .ZN(n3158) );
NAND2X0 U2515 ( .IN1(\fpu_add_frac_dp/n2307 ), .IN2(n63), .QN(n3202) );
MUX21X1 U2516 ( .IN1(n3246), .IN2(n3223), .S(\fpu_add_frac_dp/n2460 ), .Q(
n3245) );
INVX0 U2517 ( .INP(n3201), .ZN(n3058) );
MUX21X1 U2518 ( .IN1(n3247), .IN2(n3228), .S(\fpu_add_frac_dp/n2460 ), .Q(
n3201) );
NAND2X0 U2519 ( .IN1(n3248), .IN2(n3249), .QN(n3228) );
NAND2X0 U2520 ( .IN1(n3250), .IN2(n154), .QN(n3249) );
NAND2X0 U2521 ( .IN1(n3239), .IN2(\fpu_add_frac_dp/n2449 ), .QN(n3248) );
AOI221X1 U2522 ( .IN1(n123), .IN2(n2), .IN3(n752), .IN4(n2586), .IN5(n3251),
.QN(n3239) );
AO22X1 U2523 ( .IN1(n458), .IN2(n14), .IN3(n844), .IN4(n2591), .Q(n3251) );
INVX0 U2524 ( .INP(n3168), .ZN(n3189) );
INVX0 U2525 ( .INP(n3155), .ZN(n3178) );
AO221X1 U2526 ( .IN1(n3177), .IN2(n3041), .IN3(n1392), .IN4(n2932), .IN5(
n3252), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N58 ) );
AO222X1 U2527 ( .IN1(\fpu_add_frac_dp/n1520 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3049), .IN5(\fpu_add_frac_dp/n1521 ), .IN6(n3065),
.Q(n3252) );
INVX0 U2528 ( .INP(n3172), .ZN(n3049) );
AO221X1 U2529 ( .IN1(n3253), .IN2(n3254), .IN3(n3255), .IN4(n3256), .IN5(
n3257), .Q(n3172) );
AO22X1 U2530 ( .IN1(n3258), .IN2(n3259), .IN3(n3260), .IN4(n3236), .Q(n3257)
);
NAND2X0 U2531 ( .IN1(n3214), .IN2(n3213), .QN(n3236) );
NAND2X0 U2532 ( .IN1(n3261), .IN2(n154), .QN(n3213) );
NAND2X0 U2533 ( .IN1(n3250), .IN2(\fpu_add_frac_dp/n2449 ), .QN(n3214) );
AOI221X1 U2534 ( .IN1(n286), .IN2(n2), .IN3(n750), .IN4(n2586), .IN5(n3262),
.QN(n3250) );
AO22X1 U2535 ( .IN1(n459), .IN2(n14), .IN3(n841), .IN4(n2591), .Q(n3262) );
OR2X1 U2536 ( .IN1(n3263), .IN2(n3264), .Q(n3256) );
INVX0 U2537 ( .INP(n3088), .ZN(\fpu_add_frac_dp/n1520 ) );
XNOR3X1 U2538 ( .IN1(\fpu_add_frac_dp/n680 ), .IN2(\fpu_add_frac_dp/n561 ),
.IN3(n3265), .Q(n3088) );
AO221X1 U2539 ( .IN1(n3177), .IN2(n3040), .IN3(n1393), .IN4(n2928), .IN5(
n3266), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N57 ) );
AO222X1 U2540 ( .IN1(\fpu_add_frac_dp/n1521 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3048), .IN5(\fpu_add_frac_dp/n1522 ), .IN6(n3065),
.Q(n3266) );
AOI221X1 U2541 ( .IN1(n3253), .IN2(n3267), .IN3(n3255), .IN4(n3268), .IN5(
n3269), .QN(n3048) );
AO22X1 U2542 ( .IN1(n3258), .IN2(n3270), .IN3(n3260), .IN4(n3247), .Q(n3269)
);
NAND2X0 U2543 ( .IN1(n3226), .IN2(n3225), .QN(n3247) );
NAND2X0 U2544 ( .IN1(n3271), .IN2(n154), .QN(n3225) );
NAND2X0 U2545 ( .IN1(n3261), .IN2(\fpu_add_frac_dp/n2449 ), .QN(n3226) );
AOI221X1 U2546 ( .IN1(n767), .IN2(n14), .IN3(n449), .IN4(n2586), .IN5(n3272),
.QN(n3261) );
AO22X1 U2547 ( .IN1(n124), .IN2(n2), .IN3(n835), .IN4(n2591), .Q(n3272) );
INVX0 U2548 ( .INP(n3089), .ZN(\fpu_add_frac_dp/n1521 ) );
XNOR3X1 U2549 ( .IN1(\fpu_add_frac_dp/n681 ), .IN2(\fpu_add_frac_dp/n560 ),
.IN3(n3273), .Q(n3089) );
AO221X1 U2550 ( .IN1(n3197), .IN2(n3039), .IN3(n1392), .IN4(n2926), .IN5(
n3274), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N56 ) );
AO222X1 U2551 ( .IN1(\fpu_add_frac_dp/n1522 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3275), .IN4(n3047), .IN5(\fpu_add_frac_dp/n1523 ), .IN6(n3065),
.Q(n3274) );
MUX21X1 U2552 ( .IN1(n3054), .IN2(n3276), .S(n63), .Q(n3047) );
INVX0 U2553 ( .INP(n3277), .ZN(n3276) );
MUX21X1 U2554 ( .IN1(n3278), .IN2(n3211), .S(\fpu_add_frac_dp/n2460 ), .Q(
n3054) );
NOR2X0 U2555 ( .IN1(n3264), .IN2(n3263), .QN(n3211) );
AND2X1 U2556 ( .IN1(n3271), .IN2(\fpu_add_frac_dp/n2449 ), .Q(n3263) );
AOI221X1 U2557 ( .IN1(n765), .IN2(n14), .IN3(n450), .IN4(n2586), .IN5(n3279),
.QN(n3271) );
AO22X1 U2558 ( .IN1(n51), .IN2(n2), .IN3(n836), .IN4(n2591), .Q(n3279) );
NOR2X0 U2559 ( .IN1(n3280), .IN2(\fpu_add_frac_dp/n2449 ), .QN(n3264) );
INVX0 U2560 ( .INP(n3090), .ZN(\fpu_add_frac_dp/n1522 ) );
XNOR3X1 U2561 ( .IN1(\fpu_add_frac_dp/n682 ), .IN2(\fpu_add_frac_dp/n559 ),
.IN3(n3281), .Q(n3090) );
AO221X1 U2562 ( .IN1(n3177), .IN2(n3038), .IN3(n1392), .IN4(n2922), .IN5(
n3282), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N55 ) );
AO222X1 U2563 ( .IN1(\fpu_add_frac_dp/n1523 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3046), .IN5(\fpu_add_frac_dp/n1524 ), .IN6(n3065),
.Q(n3282) );
AOI222X1 U2564 ( .IN1(n3255), .IN2(n3270), .IN3(n63), .IN4(n3283), .IN5(
n3260), .IN6(n3268), .QN(n3046) );
INVX0 U2565 ( .INP(n3223), .ZN(n3268) );
MUX21X1 U2566 ( .IN1(n3284), .IN2(n3280), .S(\fpu_add_frac_dp/n2449 ), .Q(
n3223) );
AO221X1 U2567 ( .IN1(n742), .IN2(n14), .IN3(n432), .IN4(n2586), .IN5(n3285),
.Q(n3280) );
AO22X1 U2568 ( .IN1(n284), .IN2(n2), .IN3(n845), .IN4(n2591), .Q(n3285) );
INVX0 U2569 ( .INP(n3091), .ZN(\fpu_add_frac_dp/n1523 ) );
XNOR3X1 U2570 ( .IN1(\fpu_add_frac_dp/n683 ), .IN2(\fpu_add_frac_dp/n558 ),
.IN3(n3286), .Q(n3091) );
AO221X1 U2571 ( .IN1(n3177), .IN2(n3037), .IN3(n1392), .IN4(n2920), .IN5(
n3287), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N54 ) );
AO222X1 U2572 ( .IN1(\fpu_add_frac_dp/n1524 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3045), .IN5(\fpu_add_frac_dp/n1525 ), .IN6(n3065),
.Q(n3287) );
AOI222X1 U2573 ( .IN1(n3255), .IN2(n3254), .IN3(n63), .IN4(n3288), .IN5(
n3260), .IN6(n3259), .QN(n3045) );
INVX0 U2574 ( .INP(n3278), .ZN(n3259) );
MUX21X1 U2575 ( .IN1(n3289), .IN2(n3284), .S(\fpu_add_frac_dp/n2449 ), .Q(
n3278) );
AO221X1 U2576 ( .IN1(n741), .IN2(n14), .IN3(n431), .IN4(n2586), .IN5(n3290),
.Q(n3284) );
AO22X1 U2577 ( .IN1(n50), .IN2(n2), .IN3(n842), .IN4(n2591), .Q(n3290) );
INVX0 U2578 ( .INP(n3092), .ZN(\fpu_add_frac_dp/n1524 ) );
XNOR3X1 U2579 ( .IN1(\fpu_add_frac_dp/n684 ), .IN2(\fpu_add_frac_dp/n557 ),
.IN3(n3291), .Q(n3092) );
AO221X1 U2580 ( .IN1(n3177), .IN2(n3036), .IN3(n1393), .IN4(n2916), .IN5(
n3292), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N53 ) );
AO222X1 U2581 ( .IN1(\fpu_add_frac_dp/n1525 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3044), .IN5(\fpu_add_frac_dp/n1526 ), .IN6(n3065),
.Q(n3292) );
AOI222X1 U2582 ( .IN1(n3255), .IN2(n3267), .IN3(n63), .IN4(n3293), .IN5(
n3260), .IN6(n3270), .QN(n3044) );
INVX0 U2583 ( .INP(n3246), .ZN(n3270) );
MUX21X1 U2584 ( .IN1(n3294), .IN2(n3289), .S(\fpu_add_frac_dp/n2449 ), .Q(
n3246) );
AO221X1 U2585 ( .IN1(n739), .IN2(n14), .IN3(n429), .IN4(n2586), .IN5(n3295),
.Q(n3289) );
AO22X1 U2586 ( .IN1(n115), .IN2(n2), .IN3(n837), .IN4(n2591), .Q(n3295) );
INVX0 U2587 ( .INP(n3093), .ZN(\fpu_add_frac_dp/n1525 ) );
XNOR3X1 U2588 ( .IN1(\fpu_add_frac_dp/n685 ), .IN2(\fpu_add_frac_dp/n556 ),
.IN3(n3296), .Q(n3093) );
AO221X1 U2589 ( .IN1(n3177), .IN2(n3035), .IN3(n1392), .IN4(n2914), .IN5(
n3297), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N52 ) );
AO222X1 U2590 ( .IN1(\fpu_add_frac_dp/n1526 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3043), .IN5(\fpu_add_frac_dp/n1527 ), .IN6(n3065),
.Q(n3297) );
INVX0 U2591 ( .INP(n3242), .ZN(n3043) );
MUX21X1 U2592 ( .IN1(n3298), .IN2(n3277), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3242) );
AO222X1 U2593 ( .IN1(n3299), .IN2(n3300), .IN3(\fpu_add_frac_dp/n2460 ),
.IN4(n3254), .IN5(n3301), .IN6(n3302), .Q(n3277) );
INVX0 U2594 ( .INP(n3303), .ZN(n3254) );
MUX21X1 U2595 ( .IN1(n3304), .IN2(n3294), .S(\fpu_add_frac_dp/n2449 ), .Q(
n3303) );
AO221X1 U2596 ( .IN1(n740), .IN2(n14), .IN3(n430), .IN4(n2586), .IN5(n3305),
.Q(n3294) );
AO22X1 U2597 ( .IN1(n48), .IN2(n2), .IN3(n838), .IN4(n2591), .Q(n3305) );
NAND3X0 U2598 ( .IN1(n3306), .IN2(n3307), .IN3(n3308), .QN(n3304) );
INVX0 U2599 ( .INP(n3094), .ZN(\fpu_add_frac_dp/n1526 ) );
XNOR3X1 U2600 ( .IN1(\fpu_add_frac_dp/n686 ), .IN2(\fpu_add_frac_dp/n555 ),
.IN3(n3309), .Q(n3094) );
AO221X1 U2601 ( .IN1(n3177), .IN2(n3034), .IN3(n1393), .IN4(n2910), .IN5(
n3310), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N51 ) );
AO222X1 U2602 ( .IN1(\fpu_add_frac_dp/n1527 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3042), .IN5(\fpu_add_frac_dp/n1528 ), .IN6(n3065),
.Q(n3310) );
INVX0 U2603 ( .INP(n3311), .ZN(n3042) );
MUX21X1 U2604 ( .IN1(n3312), .IN2(n3283), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3311) );
AO222X1 U2605 ( .IN1(n3301), .IN2(n3300), .IN3(\fpu_add_frac_dp/n2460 ),
.IN4(n3267), .IN5(n3313), .IN6(n3302), .Q(n3283) );
MUX21X1 U2606 ( .IN1(n3314), .IN2(n3299), .S(n154), .Q(n3267) );
AND3X1 U2607 ( .IN1(n3306), .IN2(n3307), .IN3(n3308), .Q(n3314) );
OA22X1 U2608 ( .IN1(\fpu_add_frac_dp/n592 ), .IN2(\fpu_add_frac_dp/n2401 ),
.IN3(\fpu_add_frac_dp/n5633 ), .IN4(\fpu_add_frac_dp/n250 ), .Q(n3308)
);
NAND2X0 U2609 ( .IN1(n2591), .IN2(n914), .QN(n3307) );
INVX0 U2610 ( .INP(\fpu_add_frac_dp/n5634 ), .ZN(n2591) );
NAND2X0 U2611 ( .IN1(n2586), .IN2(n756), .QN(n3306) );
INVX0 U2612 ( .INP(\fpu_add_frac_dp/n5635 ), .ZN(n2586) );
INVX0 U2613 ( .INP(n3095), .ZN(\fpu_add_frac_dp/n1527 ) );
XNOR3X1 U2614 ( .IN1(\fpu_add_frac_dp/n687 ), .IN2(\fpu_add_frac_dp/n554 ),
.IN3(n3315), .Q(n3095) );
AO221X1 U2615 ( .IN1(n3177), .IN2(n3033), .IN3(n1392), .IN4(n2908), .IN5(
n3316), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N50 ) );
AO222X1 U2616 ( .IN1(\fpu_add_frac_dp/n1528 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3041), .IN5(\fpu_add_frac_dp/n1529 ), .IN6(n3065),
.Q(n3316) );
INVX0 U2617 ( .INP(n3317), .ZN(n3041) );
MUX21X1 U2618 ( .IN1(n3318), .IN2(n3288), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3317) );
AO221X1 U2619 ( .IN1(n3313), .IN2(n3300), .IN3(n3319), .IN4(n3302), .IN5(
n3320), .Q(n3288) );
AO22X1 U2620 ( .IN1(n3301), .IN2(n3321), .IN3(n3299), .IN4(n3322), .Q(n3320)
);
OA222X1 U2621 ( .IN1(\fpu_add_frac_dp/n5634 ), .IN2(\fpu_add_frac_dp/n220 ),
.IN3(\fpu_add_frac_dp/n5635 ), .IN4(\fpu_add_frac_dp/n2417 ), .IN5(
\fpu_add_frac_dp/n5633 ), .IN6(\fpu_add_frac_dp/n252 ), .Q(n3299) );
INVX0 U2622 ( .INP(n3096), .ZN(\fpu_add_frac_dp/n1528 ) );
XNOR3X1 U2623 ( .IN1(\fpu_add_frac_dp/n688 ), .IN2(\fpu_add_frac_dp/n553 ),
.IN3(n3323), .Q(n3096) );
AO221X1 U2624 ( .IN1(n3177), .IN2(n3032), .IN3(n1392), .IN4(n2904), .IN5(
n3324), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N49 ) );
AO222X1 U2625 ( .IN1(\fpu_add_frac_dp/n1529 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3040), .IN5(\fpu_add_frac_dp/n1530 ), .IN6(n3065),
.Q(n3324) );
INVX0 U2626 ( .INP(n3325), .ZN(n3040) );
MUX21X1 U2627 ( .IN1(n3326), .IN2(n3293), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3325) );
AO221X1 U2628 ( .IN1(n3319), .IN2(n3300), .IN3(n3327), .IN4(n3302), .IN5(
n3328), .Q(n3293) );
AO22X1 U2629 ( .IN1(n3313), .IN2(n3321), .IN3(n3301), .IN4(n3322), .Q(n3328)
);
OA222X1 U2630 ( .IN1(\fpu_add_frac_dp/n5634 ), .IN2(\fpu_add_frac_dp/n222 ),
.IN3(\fpu_add_frac_dp/n5635 ), .IN4(\fpu_add_frac_dp/n2291 ), .IN5(
\fpu_add_frac_dp/n5633 ), .IN6(\fpu_add_frac_dp/n254 ), .Q(n3301) );
INVX0 U2631 ( .INP(n3097), .ZN(\fpu_add_frac_dp/n1529 ) );
XNOR3X1 U2632 ( .IN1(\fpu_add_frac_dp/n689 ), .IN2(\fpu_add_frac_dp/n552 ),
.IN3(n3329), .Q(n3097) );
AO221X1 U2633 ( .IN1(n3177), .IN2(n3031), .IN3(n1391), .IN4(n2902), .IN5(
n3330), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N48 ) );
AO222X1 U2634 ( .IN1(\fpu_add_frac_dp/n1530 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3039), .IN5(\fpu_add_frac_dp/n1531 ), .IN6(n3065),
.Q(n3330) );
INVX0 U2635 ( .INP(n3331), .ZN(n3039) );
MUX21X1 U2636 ( .IN1(n3332), .IN2(n3298), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3331) );
AO221X1 U2637 ( .IN1(n3327), .IN2(n3300), .IN3(n3333), .IN4(n3302), .IN5(
n3334), .Q(n3298) );
AO22X1 U2638 ( .IN1(n3319), .IN2(n3321), .IN3(n3313), .IN4(n3322), .Q(n3334)
);
OA222X1 U2639 ( .IN1(\fpu_add_frac_dp/n5634 ), .IN2(\fpu_add_frac_dp/n224 ),
.IN3(\fpu_add_frac_dp/n5635 ), .IN4(\fpu_add_frac_dp/n2358 ), .IN5(
\fpu_add_frac_dp/n5633 ), .IN6(\fpu_add_frac_dp/n256 ), .Q(n3313) );
INVX0 U2640 ( .INP(n3099), .ZN(\fpu_add_frac_dp/n1530 ) );
XNOR3X1 U2641 ( .IN1(\fpu_add_frac_dp/n690 ), .IN2(\fpu_add_frac_dp/n551 ),
.IN3(n3335), .Q(n3099) );
AO221X1 U2642 ( .IN1(n3177), .IN2(n3030), .IN3(n1394), .IN4(n2898), .IN5(
n3336), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N47 ) );
AO222X1 U2643 ( .IN1(\fpu_add_frac_dp/n1531 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3038), .IN5(\fpu_add_frac_dp/n1532 ), .IN6(n3065),
.Q(n3336) );
INVX0 U2644 ( .INP(n3337), .ZN(n3038) );
MUX21X1 U2645 ( .IN1(n3338), .IN2(n3312), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3337) );
AO221X1 U2646 ( .IN1(n3333), .IN2(n3300), .IN3(n3339), .IN4(n3302), .IN5(
n3340), .Q(n3312) );
AO22X1 U2647 ( .IN1(n3327), .IN2(n3321), .IN3(n3319), .IN4(n3322), .Q(n3340)
);
OA222X1 U2648 ( .IN1(\fpu_add_frac_dp/n5634 ), .IN2(\fpu_add_frac_dp/n226 ),
.IN3(\fpu_add_frac_dp/n5635 ), .IN4(\fpu_add_frac_dp/n2292 ), .IN5(
\fpu_add_frac_dp/n5633 ), .IN6(\fpu_add_frac_dp/n258 ), .Q(n3319) );
INVX0 U2649 ( .INP(n3100), .ZN(\fpu_add_frac_dp/n1531 ) );
XNOR3X1 U2650 ( .IN1(\fpu_add_frac_dp/n691 ), .IN2(\fpu_add_frac_dp/n550 ),
.IN3(n3341), .Q(n3100) );
AO221X1 U2651 ( .IN1(n3177), .IN2(n3029), .IN3(n1391), .IN4(n2896), .IN5(
n3342), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N46 ) );
AO222X1 U2652 ( .IN1(\fpu_add_frac_dp/n1532 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3037), .IN5(\fpu_add_frac_dp/n1533 ), .IN6(n3065),
.Q(n3342) );
INVX0 U2653 ( .INP(n3343), .ZN(n3037) );
MUX21X1 U2654 ( .IN1(n3344), .IN2(n3318), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3343) );
AO221X1 U2655 ( .IN1(n3339), .IN2(n3300), .IN3(n3345), .IN4(n3302), .IN5(
n3346), .Q(n3318) );
AO22X1 U2656 ( .IN1(n3333), .IN2(n3321), .IN3(n3327), .IN4(n3322), .Q(n3346)
);
OA222X1 U2657 ( .IN1(\fpu_add_frac_dp/n5634 ), .IN2(\fpu_add_frac_dp/n228 ),
.IN3(\fpu_add_frac_dp/n5635 ), .IN4(\fpu_add_frac_dp/n2360 ), .IN5(
\fpu_add_frac_dp/n5633 ), .IN6(\fpu_add_frac_dp/n260 ), .Q(n3327) );
INVX0 U2658 ( .INP(n3101), .ZN(\fpu_add_frac_dp/n1532 ) );
XNOR3X1 U2659 ( .IN1(\fpu_add_frac_dp/n692 ), .IN2(\fpu_add_frac_dp/n549 ),
.IN3(n3347), .Q(n3101) );
AO221X1 U2660 ( .IN1(n3197), .IN2(n3028), .IN3(n1391), .IN4(n2891), .IN5(
n3348), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N45 ) );
AO222X1 U2661 ( .IN1(\fpu_add_frac_dp/n1533 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3275), .IN4(n3036), .IN5(\fpu_add_frac_dp/n1534 ), .IN6(n3065),
.Q(n3348) );
INVX0 U2662 ( .INP(n3349), .ZN(n3036) );
MUX21X1 U2663 ( .IN1(n3350), .IN2(n3326), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3349) );
AO221X1 U2664 ( .IN1(n3345), .IN2(n3300), .IN3(n3351), .IN4(n3302), .IN5(
n3352), .Q(n3326) );
AO22X1 U2665 ( .IN1(n3339), .IN2(n3321), .IN3(n3333), .IN4(n3322), .Q(n3352)
);
OA222X1 U2666 ( .IN1(\fpu_add_frac_dp/n5634 ), .IN2(\fpu_add_frac_dp/n230 ),
.IN3(\fpu_add_frac_dp/n5635 ), .IN4(\fpu_add_frac_dp/n2293 ), .IN5(
\fpu_add_frac_dp/n5633 ), .IN6(\fpu_add_frac_dp/n262 ), .Q(n3333) );
INVX0 U2667 ( .INP(n3102), .ZN(\fpu_add_frac_dp/n1533 ) );
XNOR3X1 U2668 ( .IN1(\fpu_add_frac_dp/n693 ), .IN2(\fpu_add_frac_dp/n548 ),
.IN3(n3353), .Q(n3102) );
AO221X1 U2669 ( .IN1(n3177), .IN2(n3027), .IN3(n1392), .IN4(n2888), .IN5(
n3354), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N44 ) );
AO222X1 U2670 ( .IN1(\fpu_add_frac_dp/n1534 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3035), .IN5(\fpu_add_frac_dp/n1535 ), .IN6(n3065),
.Q(n3354) );
INVX0 U2671 ( .INP(n3355), .ZN(n3035) );
MUX21X1 U2672 ( .IN1(n3356), .IN2(n3332), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3355) );
AO221X1 U2673 ( .IN1(n3351), .IN2(n3300), .IN3(n3357), .IN4(n3302), .IN5(
n3358), .Q(n3332) );
AO22X1 U2674 ( .IN1(n3345), .IN2(n3321), .IN3(n3339), .IN4(n3322), .Q(n3358)
);
OA222X1 U2675 ( .IN1(\fpu_add_frac_dp/n5634 ), .IN2(\fpu_add_frac_dp/n232 ),
.IN3(\fpu_add_frac_dp/n5635 ), .IN4(\fpu_add_frac_dp/n2410 ), .IN5(
\fpu_add_frac_dp/n5633 ), .IN6(\fpu_add_frac_dp/n264 ), .Q(n3339) );
INVX0 U2676 ( .INP(n3103), .ZN(\fpu_add_frac_dp/n1534 ) );
XNOR3X1 U2677 ( .IN1(\fpu_add_frac_dp/n694 ), .IN2(\fpu_add_frac_dp/n547 ),
.IN3(n3359), .Q(n3103) );
AO221X1 U2678 ( .IN1(n3177), .IN2(n3026), .IN3(n1391), .IN4(n2984), .IN5(
n3360), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N43 ) );
AO222X1 U2679 ( .IN1(\fpu_add_frac_dp/n1535 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3034), .IN5(\fpu_add_frac_dp/n1536 ), .IN6(n3065),
.Q(n3360) );
INVX0 U2680 ( .INP(n3361), .ZN(n3034) );
MUX21X1 U2681 ( .IN1(n3362), .IN2(n3338), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3361) );
AO221X1 U2682 ( .IN1(n3357), .IN2(n3300), .IN3(n3363), .IN4(n3302), .IN5(
n3364), .Q(n3338) );
AO22X1 U2683 ( .IN1(n3351), .IN2(n3321), .IN3(n3345), .IN4(n3322), .Q(n3364)
);
OA222X1 U2684 ( .IN1(\fpu_add_frac_dp/n5634 ), .IN2(\fpu_add_frac_dp/n234 ),
.IN3(\fpu_add_frac_dp/n5635 ), .IN4(\fpu_add_frac_dp/n2346 ), .IN5(
\fpu_add_frac_dp/n5633 ), .IN6(\fpu_add_frac_dp/n266 ), .Q(n3345) );
INVX0 U2685 ( .INP(n3104), .ZN(\fpu_add_frac_dp/n1535 ) );
XNOR3X1 U2686 ( .IN1(\fpu_add_frac_dp/n695 ), .IN2(\fpu_add_frac_dp/n546 ),
.IN3(n3365), .Q(n3104) );
AO221X1 U2687 ( .IN1(n3177), .IN2(n3025), .IN3(n1391), .IN4(n2983), .IN5(
n3366), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N42 ) );
AO222X1 U2688 ( .IN1(\fpu_add_frac_dp/n1536 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3033), .IN5(\fpu_add_frac_dp/n1537 ), .IN6(n3065),
.Q(n3366) );
INVX0 U2689 ( .INP(n3367), .ZN(n3033) );
MUX21X1 U2690 ( .IN1(n3368), .IN2(n3344), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3367) );
AO221X1 U2691 ( .IN1(n3363), .IN2(n3300), .IN3(n3369), .IN4(n3302), .IN5(
n3370), .Q(n3344) );
AO22X1 U2692 ( .IN1(n3357), .IN2(n3321), .IN3(n3351), .IN4(n3322), .Q(n3370)
);
OA222X1 U2693 ( .IN1(\fpu_add_frac_dp/n5634 ), .IN2(\fpu_add_frac_dp/n236 ),
.IN3(\fpu_add_frac_dp/n5635 ), .IN4(\fpu_add_frac_dp/n2413 ), .IN5(
\fpu_add_frac_dp/n5633 ), .IN6(\fpu_add_frac_dp/n268 ), .Q(n3351) );
INVX0 U2694 ( .INP(n3105), .ZN(\fpu_add_frac_dp/n1536 ) );
XNOR3X1 U2695 ( .IN1(\fpu_add_frac_dp/n696 ), .IN2(\fpu_add_frac_dp/n544 ),
.IN3(n3371), .Q(n3105) );
AO221X1 U2696 ( .IN1(n3177), .IN2(n3024), .IN3(n1391), .IN4(n2881), .IN5(
n3372), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N41 ) );
AO222X1 U2697 ( .IN1(\fpu_add_frac_dp/n1537 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3032), .IN5(\fpu_add_frac_dp/n1538 ), .IN6(n3065),
.Q(n3372) );
INVX0 U2698 ( .INP(n3373), .ZN(n3032) );
MUX21X1 U2699 ( .IN1(n3374), .IN2(n3350), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3373) );
AO221X1 U2700 ( .IN1(n3369), .IN2(n3300), .IN3(n3375), .IN4(n3302), .IN5(
n3376), .Q(n3350) );
AO22X1 U2701 ( .IN1(n3363), .IN2(n3321), .IN3(n3357), .IN4(n3322), .Q(n3376)
);
OA222X1 U2702 ( .IN1(\fpu_add_frac_dp/n5634 ), .IN2(\fpu_add_frac_dp/n238 ),
.IN3(\fpu_add_frac_dp/n5635 ), .IN4(\fpu_add_frac_dp/n2349 ), .IN5(
\fpu_add_frac_dp/n5633 ), .IN6(\fpu_add_frac_dp/n270 ), .Q(n3357) );
INVX0 U2703 ( .INP(n3106), .ZN(\fpu_add_frac_dp/n1537 ) );
XNOR3X1 U2704 ( .IN1(\fpu_add_frac_dp/n697 ), .IN2(\fpu_add_frac_dp/n543 ),
.IN3(n3377), .Q(n3106) );
AO221X1 U2705 ( .IN1(n3177), .IN2(n3023), .IN3(n1391), .IN4(n2982), .IN5(
n3378), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N40 ) );
AO222X1 U2706 ( .IN1(\fpu_add_frac_dp/n1538 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3031), .IN5(\fpu_add_frac_dp/n1539 ), .IN6(n3065),
.Q(n3378) );
INVX0 U2707 ( .INP(n3379), .ZN(n3031) );
MUX21X1 U2708 ( .IN1(n3380), .IN2(n3356), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3379) );
AO221X1 U2709 ( .IN1(n3375), .IN2(n3300), .IN3(n3381), .IN4(n3302), .IN5(
n3382), .Q(n3356) );
AO22X1 U2710 ( .IN1(n3369), .IN2(n3321), .IN3(n3363), .IN4(n3322), .Q(n3382)
);
OA222X1 U2711 ( .IN1(\fpu_add_frac_dp/n5634 ), .IN2(\fpu_add_frac_dp/n240 ),
.IN3(\fpu_add_frac_dp/n5635 ), .IN4(\fpu_add_frac_dp/n2294 ), .IN5(
\fpu_add_frac_dp/n5633 ), .IN6(\fpu_add_frac_dp/n272 ), .Q(n3363) );
INVX0 U2712 ( .INP(n3107), .ZN(\fpu_add_frac_dp/n1538 ) );
XNOR3X1 U2713 ( .IN1(\fpu_add_frac_dp/n698 ), .IN2(\fpu_add_frac_dp/n542 ),
.IN3(n3383), .Q(n3107) );
AO221X1 U2714 ( .IN1(n3177), .IN2(n3022), .IN3(n1391), .IN4(n2867), .IN5(
n3384), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N39 ) );
AO222X1 U2715 ( .IN1(\fpu_add_frac_dp/n1539 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3030), .IN5(\fpu_add_frac_dp/n1540 ), .IN6(n3065),
.Q(n3384) );
INVX0 U2716 ( .INP(n3385), .ZN(n3030) );
MUX21X1 U2717 ( .IN1(n3386), .IN2(n3362), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3385) );
AO221X1 U2718 ( .IN1(n3381), .IN2(n3300), .IN3(n3387), .IN4(n3302), .IN5(
n3388), .Q(n3362) );
AO22X1 U2719 ( .IN1(n3375), .IN2(n3321), .IN3(n3369), .IN4(n3322), .Q(n3388)
);
OA222X1 U2720 ( .IN1(\fpu_add_frac_dp/n5634 ), .IN2(\fpu_add_frac_dp/n242 ),
.IN3(\fpu_add_frac_dp/n5635 ), .IN4(\fpu_add_frac_dp/n2414 ), .IN5(
\fpu_add_frac_dp/n5633 ), .IN6(\fpu_add_frac_dp/n274 ), .Q(n3369) );
INVX0 U2721 ( .INP(n3108), .ZN(\fpu_add_frac_dp/n1539 ) );
XNOR3X1 U2722 ( .IN1(\fpu_add_frac_dp/n699 ), .IN2(\fpu_add_frac_dp/n541 ),
.IN3(n3389), .Q(n3108) );
AO221X1 U2723 ( .IN1(n3177), .IN2(n3021), .IN3(n1392), .IN4(n2981), .IN5(
n3390), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N38 ) );
AO222X1 U2724 ( .IN1(\fpu_add_frac_dp/n1540 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3029), .IN5(\fpu_add_frac_dp/n1541 ), .IN6(n3065),
.Q(n3390) );
INVX0 U2725 ( .INP(n3391), .ZN(n3029) );
MUX21X1 U2726 ( .IN1(n3392), .IN2(n3368), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3391) );
AO221X1 U2727 ( .IN1(n3387), .IN2(n3300), .IN3(n3393), .IN4(n3302), .IN5(
n3394), .Q(n3368) );
AO22X1 U2728 ( .IN1(n3381), .IN2(n3321), .IN3(n3375), .IN4(n3322), .Q(n3394)
);
OA222X1 U2729 ( .IN1(\fpu_add_frac_dp/n5634 ), .IN2(\fpu_add_frac_dp/n244 ),
.IN3(\fpu_add_frac_dp/n5635 ), .IN4(\fpu_add_frac_dp/n2347 ), .IN5(
\fpu_add_frac_dp/n5633 ), .IN6(\fpu_add_frac_dp/n276 ), .Q(n3375) );
INVX0 U2730 ( .INP(n3110), .ZN(\fpu_add_frac_dp/n1540 ) );
XNOR3X1 U2731 ( .IN1(\fpu_add_frac_dp/n700 ), .IN2(\fpu_add_frac_dp/n540 ),
.IN3(n3395), .Q(n3110) );
AO221X1 U2732 ( .IN1(n3177), .IN2(n3020), .IN3(n1391), .IN4(n2980), .IN5(
n3396), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N37 ) );
AO222X1 U2733 ( .IN1(\fpu_add_frac_dp/n1541 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3028), .IN5(\fpu_add_frac_dp/n1542 ), .IN6(n3065),
.Q(n3396) );
INVX0 U2734 ( .INP(n3397), .ZN(n3028) );
MUX21X1 U2735 ( .IN1(n3398), .IN2(n3374), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3397) );
AO221X1 U2736 ( .IN1(n3393), .IN2(n3300), .IN3(n3399), .IN4(n3302), .IN5(
n3400), .Q(n3374) );
AO22X1 U2737 ( .IN1(n3387), .IN2(n3321), .IN3(n3381), .IN4(n3322), .Q(n3400)
);
OA222X1 U2738 ( .IN1(\fpu_add_frac_dp/n5634 ), .IN2(\fpu_add_frac_dp/n246 ),
.IN3(\fpu_add_frac_dp/n5635 ), .IN4(\fpu_add_frac_dp/n2412 ), .IN5(
\fpu_add_frac_dp/n5633 ), .IN6(\fpu_add_frac_dp/n278 ), .Q(n3381) );
INVX0 U2739 ( .INP(n3111), .ZN(\fpu_add_frac_dp/n1541 ) );
XNOR3X1 U2740 ( .IN1(\fpu_add_frac_dp/n701 ), .IN2(\fpu_add_frac_dp/n539 ),
.IN3(n3401), .Q(n3111) );
AO221X1 U2741 ( .IN1(n3177), .IN2(n3019), .IN3(n1391), .IN4(n2858), .IN5(
n3402), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N36 ) );
AO222X1 U2742 ( .IN1(\fpu_add_frac_dp/n1542 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3027), .IN5(\fpu_add_frac_dp/n1543 ), .IN6(n3065),
.Q(n3402) );
INVX0 U2743 ( .INP(n3403), .ZN(n3027) );
MUX21X1 U2744 ( .IN1(n3404), .IN2(n3380), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3403) );
AO221X1 U2745 ( .IN1(n3399), .IN2(n3300), .IN3(n3405), .IN4(n3302), .IN5(
n3406), .Q(n3380) );
AO22X1 U2746 ( .IN1(n3393), .IN2(n3321), .IN3(n3387), .IN4(n3322), .Q(n3406)
);
OA222X1 U2747 ( .IN1(\fpu_add_frac_dp/n5634 ), .IN2(\fpu_add_frac_dp/n248 ),
.IN3(\fpu_add_frac_dp/n5635 ), .IN4(\fpu_add_frac_dp/n2348 ), .IN5(
\fpu_add_frac_dp/n5633 ), .IN6(\fpu_add_frac_dp/n280 ), .Q(n3387) );
INVX0 U2748 ( .INP(n3112), .ZN(\fpu_add_frac_dp/n1542 ) );
XNOR3X1 U2749 ( .IN1(\fpu_add_frac_dp/n702 ), .IN2(\fpu_add_frac_dp/n538 ),
.IN3(n3407), .Q(n3112) );
AO221X1 U2750 ( .IN1(n3177), .IN2(n3018), .IN3(n1391), .IN4(n2854), .IN5(
n3408), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N35 ) );
AO222X1 U2751 ( .IN1(\fpu_add_frac_dp/n1543 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3026), .IN5(\fpu_add_frac_dp/n1544 ), .IN6(n3065),
.Q(n3408) );
INVX0 U2752 ( .INP(n3409), .ZN(n3026) );
MUX21X1 U2753 ( .IN1(n3410), .IN2(n3386), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3409) );
AO221X1 U2754 ( .IN1(n3405), .IN2(n3300), .IN3(n3411), .IN4(n3302), .IN5(
n3412), .Q(n3386) );
AO22X1 U2755 ( .IN1(n3399), .IN2(n3321), .IN3(n3393), .IN4(n3322), .Q(n3412)
);
OA222X1 U2756 ( .IN1(\fpu_add_frac_dp/n5634 ), .IN2(\fpu_add_frac_dp/n250 ),
.IN3(\fpu_add_frac_dp/n5635 ), .IN4(\fpu_add_frac_dp/n2401 ), .IN5(
\fpu_add_frac_dp/n5633 ), .IN6(\fpu_add_frac_dp/n282 ), .Q(n3393) );
INVX0 U2757 ( .INP(n3113), .ZN(\fpu_add_frac_dp/n1543 ) );
XNOR3X1 U2758 ( .IN1(\fpu_add_frac_dp/n703 ), .IN2(\fpu_add_frac_dp/n537 ),
.IN3(n3413), .Q(n3113) );
AO221X1 U2759 ( .IN1(n3177), .IN2(n3017), .IN3(n1391), .IN4(n2852), .IN5(
n3414), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N34 ) );
AO222X1 U2760 ( .IN1(\fpu_add_frac_dp/n1544 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3025), .IN5(\fpu_add_frac_dp/n1545 ), .IN6(n3065),
.Q(n3414) );
INVX0 U2761 ( .INP(n3415), .ZN(n3025) );
MUX21X1 U2762 ( .IN1(n3416), .IN2(n3392), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3415) );
AO221X1 U2763 ( .IN1(n3411), .IN2(n3300), .IN3(n3417), .IN4(n3302), .IN5(
n3418), .Q(n3392) );
AO22X1 U2764 ( .IN1(n3405), .IN2(n3321), .IN3(n3399), .IN4(n3322), .Q(n3418)
);
OA22X1 U2765 ( .IN1(\fpu_add_frac_dp/n589 ), .IN2(\fpu_add_frac_dp/n2417 ),
.IN3(\fpu_add_frac_dp/n252 ), .IN4(\fpu_add_frac_dp/n2271 ), .Q(n3399)
);
INVX0 U2766 ( .INP(n3114), .ZN(\fpu_add_frac_dp/n1544 ) );
XNOR3X1 U2767 ( .IN1(\fpu_add_frac_dp/n704 ), .IN2(\fpu_add_frac_dp/n536 ),
.IN3(n3419), .Q(n3114) );
AO221X1 U2768 ( .IN1(n3177), .IN2(n3016), .IN3(n1390), .IN4(n2848), .IN5(
n3420), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N33 ) );
AO222X1 U2769 ( .IN1(\fpu_add_frac_dp/n1545 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3024), .IN5(\fpu_add_frac_dp/n1546 ), .IN6(n3065),
.Q(n3420) );
INVX0 U2770 ( .INP(n3421), .ZN(n3024) );
MUX21X1 U2771 ( .IN1(n3422), .IN2(n3398), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3421) );
AO221X1 U2772 ( .IN1(n3417), .IN2(n3300), .IN3(n3423), .IN4(n3302), .IN5(
n3424), .Q(n3398) );
AO22X1 U2773 ( .IN1(n3411), .IN2(n3321), .IN3(n3405), .IN4(n3322), .Q(n3424)
);
OA22X1 U2774 ( .IN1(\fpu_add_frac_dp/n589 ), .IN2(\fpu_add_frac_dp/n2291 ),
.IN3(\fpu_add_frac_dp/n254 ), .IN4(\fpu_add_frac_dp/n2271 ), .Q(n3405)
);
INVX0 U2775 ( .INP(n3115), .ZN(\fpu_add_frac_dp/n1545 ) );
XNOR3X1 U2776 ( .IN1(\fpu_add_frac_dp/n705 ), .IN2(\fpu_add_frac_dp/n535 ),
.IN3(n3425), .Q(n3115) );
AO221X1 U2777 ( .IN1(n3197), .IN2(n3015), .IN3(n1391), .IN4(n2846), .IN5(
n3426), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N32 ) );
AO222X1 U2778 ( .IN1(\fpu_add_frac_dp/n1546 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3275), .IN4(n3023), .IN5(\fpu_add_frac_dp/n1547 ), .IN6(n3065),
.Q(n3426) );
INVX0 U2779 ( .INP(n3427), .ZN(n3023) );
MUX21X1 U2780 ( .IN1(n3428), .IN2(n3404), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3427) );
AO221X1 U2781 ( .IN1(n3423), .IN2(n3300), .IN3(n3429), .IN4(n3302), .IN5(
n3430), .Q(n3404) );
AO22X1 U2782 ( .IN1(n3417), .IN2(n3321), .IN3(n3411), .IN4(n3322), .Q(n3430)
);
OA22X1 U2783 ( .IN1(\fpu_add_frac_dp/n589 ), .IN2(\fpu_add_frac_dp/n2358 ),
.IN3(\fpu_add_frac_dp/n256 ), .IN4(\fpu_add_frac_dp/n2271 ), .Q(n3411)
);
INVX0 U2784 ( .INP(n3116), .ZN(\fpu_add_frac_dp/n1546 ) );
XNOR3X1 U2785 ( .IN1(\fpu_add_frac_dp/n706 ), .IN2(\fpu_add_frac_dp/n534 ),
.IN3(n3431), .Q(n3116) );
AO221X1 U2786 ( .IN1(n3177), .IN2(n3014), .IN3(n1390), .IN4(n2842), .IN5(
n3432), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N31 ) );
AO222X1 U2787 ( .IN1(\fpu_add_frac_dp/n1547 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3022), .IN5(\fpu_add_frac_dp/n1548 ), .IN6(n3065),
.Q(n3432) );
INVX0 U2788 ( .INP(n3433), .ZN(n3022) );
MUX21X1 U2789 ( .IN1(n3434), .IN2(n3410), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3433) );
AO221X1 U2790 ( .IN1(n3429), .IN2(n3300), .IN3(n3435), .IN4(n3302), .IN5(
n3436), .Q(n3410) );
AO22X1 U2791 ( .IN1(n3423), .IN2(n3321), .IN3(n3417), .IN4(n3322), .Q(n3436)
);
OA22X1 U2792 ( .IN1(\fpu_add_frac_dp/n589 ), .IN2(\fpu_add_frac_dp/n2292 ),
.IN3(\fpu_add_frac_dp/n258 ), .IN4(\fpu_add_frac_dp/n2271 ), .Q(n3417)
);
INVX0 U2793 ( .INP(n3117), .ZN(\fpu_add_frac_dp/n1547 ) );
XNOR3X1 U2794 ( .IN1(\fpu_add_frac_dp/n707 ), .IN2(\fpu_add_frac_dp/n533 ),
.IN3(n3437), .Q(n3117) );
AO221X1 U2795 ( .IN1(n3197), .IN2(n3013), .IN3(n1390), .IN4(n2840), .IN5(
n3438), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N30 ) );
AO222X1 U2796 ( .IN1(\fpu_add_frac_dp/n1548 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3275), .IN4(n3021), .IN5(\fpu_add_frac_dp/n1549 ), .IN6(n3065),
.Q(n3438) );
INVX0 U2797 ( .INP(n3439), .ZN(n3021) );
MUX21X1 U2798 ( .IN1(n3440), .IN2(n3416), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3439) );
AO221X1 U2799 ( .IN1(n3435), .IN2(n3300), .IN3(n3441), .IN4(n3302), .IN5(
n3442), .Q(n3416) );
AO22X1 U2800 ( .IN1(n3429), .IN2(n3321), .IN3(n3423), .IN4(n3322), .Q(n3442)
);
OA22X1 U2801 ( .IN1(\fpu_add_frac_dp/n589 ), .IN2(\fpu_add_frac_dp/n2360 ),
.IN3(\fpu_add_frac_dp/n260 ), .IN4(\fpu_add_frac_dp/n2271 ), .Q(n3423)
);
INVX0 U2802 ( .INP(n3118), .ZN(\fpu_add_frac_dp/n1548 ) );
XNOR3X1 U2803 ( .IN1(\fpu_add_frac_dp/n708 ), .IN2(\fpu_add_frac_dp/n532 ),
.IN3(n3443), .Q(n3118) );
AO222X1 U2804 ( .IN1(n1415), .IN2(n956), .IN3(n3069), .IN4(n2988), .IN5(
\fpu_add_frac_dp/a3stg_fracadd[0] ), .IN6(\fpu_add_frac_dp/n1509 ),
.Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N3 ) );
INVX0 U2805 ( .INP(n3444), .ZN(n2988) );
INVX0 U2806 ( .INP(n3073), .ZN(n3069) );
NAND2X0 U2807 ( .IN1(\fpu_add_ctl/n319 ), .IN2(n2989), .QN(n3073) );
NOR2X0 U2808 ( .IN1(n3168), .IN2(n1745), .QN(n2989) );
NAND2X0 U2809 ( .IN1(\fpu_add_frac_dp/n2471 ), .IN2(\fpu_add_frac_dp/n2307 ),
.QN(n3168) );
AO221X1 U2810 ( .IN1(n3177), .IN2(n3012), .IN3(n1390), .IN4(n2836), .IN5(
n3445), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N29 ) );
AO222X1 U2811 ( .IN1(\fpu_add_frac_dp/n1549 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3020), .IN5(\fpu_add_frac_dp/n1550 ), .IN6(n3065),
.Q(n3445) );
INVX0 U2812 ( .INP(n3446), .ZN(n3020) );
MUX21X1 U2813 ( .IN1(n3447), .IN2(n3422), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3446) );
AO221X1 U2814 ( .IN1(n3441), .IN2(n3300), .IN3(n3448), .IN4(n3302), .IN5(
n3449), .Q(n3422) );
AO22X1 U2815 ( .IN1(n3435), .IN2(n3321), .IN3(n3429), .IN4(n3322), .Q(n3449)
);
OA22X1 U2816 ( .IN1(\fpu_add_frac_dp/n589 ), .IN2(\fpu_add_frac_dp/n2293 ),
.IN3(\fpu_add_frac_dp/n262 ), .IN4(\fpu_add_frac_dp/n2271 ), .Q(n3429)
);
INVX0 U2817 ( .INP(n3119), .ZN(\fpu_add_frac_dp/n1549 ) );
XNOR3X1 U2818 ( .IN1(\fpu_add_frac_dp/n709 ), .IN2(\fpu_add_frac_dp/n531 ),
.IN3(n3450), .Q(n3119) );
AO221X1 U2819 ( .IN1(n3177), .IN2(n3011), .IN3(n1390), .IN4(n2834), .IN5(
n3451), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N28 ) );
AO222X1 U2820 ( .IN1(\fpu_add_frac_dp/n1550 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3019), .IN5(\fpu_add_frac_dp/n1551 ), .IN6(n3065),
.Q(n3451) );
INVX0 U2821 ( .INP(n3452), .ZN(n3019) );
MUX21X1 U2822 ( .IN1(n3453), .IN2(n3428), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3452) );
AO221X1 U2823 ( .IN1(n3448), .IN2(n3300), .IN3(n3454), .IN4(n3302), .IN5(
n3455), .Q(n3428) );
AO22X1 U2824 ( .IN1(n3441), .IN2(n3321), .IN3(n3435), .IN4(n3322), .Q(n3455)
);
OA22X1 U2825 ( .IN1(\fpu_add_frac_dp/n589 ), .IN2(\fpu_add_frac_dp/n2410 ),
.IN3(\fpu_add_frac_dp/n264 ), .IN4(\fpu_add_frac_dp/n2271 ), .Q(n3435)
);
INVX0 U2826 ( .INP(n3120), .ZN(\fpu_add_frac_dp/n1550 ) );
XNOR3X1 U2827 ( .IN1(\fpu_add_frac_dp/n710 ), .IN2(\fpu_add_frac_dp/n530 ),
.IN3(n3456), .Q(n3120) );
AO221X1 U2828 ( .IN1(n3177), .IN2(n3009), .IN3(n1391), .IN4(n2830), .IN5(
n3457), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N27 ) );
AO222X1 U2829 ( .IN1(\fpu_add_frac_dp/n1551 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3018), .IN5(\fpu_add_frac_dp/n1552 ), .IN6(n3065),
.Q(n3457) );
INVX0 U2830 ( .INP(n3458), .ZN(n3018) );
MUX21X1 U2831 ( .IN1(n3459), .IN2(n3434), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3458) );
AO221X1 U2832 ( .IN1(n3454), .IN2(n3300), .IN3(n3460), .IN4(n3302), .IN5(
n3461), .Q(n3434) );
AO22X1 U2833 ( .IN1(n3448), .IN2(n3321), .IN3(n3441), .IN4(n3322), .Q(n3461)
);
OA22X1 U2834 ( .IN1(\fpu_add_frac_dp/n589 ), .IN2(\fpu_add_frac_dp/n2346 ),
.IN3(\fpu_add_frac_dp/n266 ), .IN4(\fpu_add_frac_dp/n2271 ), .Q(n3441)
);
INVX0 U2835 ( .INP(n3121), .ZN(\fpu_add_frac_dp/n1551 ) );
XNOR3X1 U2836 ( .IN1(\fpu_add_frac_dp/n711 ), .IN2(\fpu_add_frac_dp/n529 ),
.IN3(n3462), .Q(n3121) );
AO221X1 U2837 ( .IN1(n3177), .IN2(n3007), .IN3(n1390), .IN4(n2979), .IN5(
n3463), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N26 ) );
AO222X1 U2838 ( .IN1(\fpu_add_frac_dp/n1552 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3017), .IN5(\fpu_add_frac_dp/n1553 ), .IN6(n3065),
.Q(n3463) );
INVX0 U2839 ( .INP(n3464), .ZN(n3017) );
MUX21X1 U2840 ( .IN1(n3465), .IN2(n3440), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3464) );
AO221X1 U2841 ( .IN1(n3460), .IN2(n3300), .IN3(n3466), .IN4(n3302), .IN5(
n3467), .Q(n3440) );
AO22X1 U2842 ( .IN1(n3454), .IN2(n3321), .IN3(n3448), .IN4(n3322), .Q(n3467)
);
OA22X1 U2843 ( .IN1(\fpu_add_frac_dp/n589 ), .IN2(\fpu_add_frac_dp/n2413 ),
.IN3(\fpu_add_frac_dp/n268 ), .IN4(\fpu_add_frac_dp/n2271 ), .Q(n3448)
);
INVX0 U2844 ( .INP(n3122), .ZN(\fpu_add_frac_dp/n1552 ) );
XNOR3X1 U2845 ( .IN1(\fpu_add_frac_dp/n712 ), .IN2(\fpu_add_frac_dp/n527 ),
.IN3(n3468), .Q(n3122) );
AO221X1 U2846 ( .IN1(n3177), .IN2(n3006), .IN3(n1392), .IN4(n2978), .IN5(
n3469), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N25 ) );
AO222X1 U2847 ( .IN1(\fpu_add_frac_dp/n1553 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3016), .IN5(\fpu_add_frac_dp/n1554 ), .IN6(n3065),
.Q(n3469) );
INVX0 U2848 ( .INP(n3470), .ZN(n3016) );
MUX21X1 U2849 ( .IN1(n3471), .IN2(n3447), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3470) );
AO221X1 U2850 ( .IN1(n3466), .IN2(n3300), .IN3(n3472), .IN4(n3302), .IN5(
n3473), .Q(n3447) );
AO22X1 U2851 ( .IN1(n3460), .IN2(n3321), .IN3(n3454), .IN4(n3322), .Q(n3473)
);
OA22X1 U2852 ( .IN1(\fpu_add_frac_dp/n589 ), .IN2(\fpu_add_frac_dp/n2349 ),
.IN3(\fpu_add_frac_dp/n270 ), .IN4(\fpu_add_frac_dp/n2271 ), .Q(n3454)
);
INVX0 U2853 ( .INP(n3123), .ZN(\fpu_add_frac_dp/n1553 ) );
XNOR3X1 U2854 ( .IN1(\fpu_add_frac_dp/n713 ), .IN2(\fpu_add_frac_dp/n526 ),
.IN3(n3474), .Q(n3123) );
AO221X1 U2855 ( .IN1(n3177), .IN2(n3005), .IN3(n1390), .IN4(n2977), .IN5(
n3475), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N24 ) );
AO222X1 U2856 ( .IN1(\fpu_add_frac_dp/n1554 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3015), .IN5(\fpu_add_frac_dp/n1555 ), .IN6(n3065),
.Q(n3475) );
INVX0 U2857 ( .INP(n3476), .ZN(n3015) );
MUX21X1 U2858 ( .IN1(n3477), .IN2(n3453), .S(\fpu_add_frac_dp/n2471 ), .Q(
n3476) );
AO221X1 U2859 ( .IN1(n3302), .IN2(n3478), .IN3(n3472), .IN4(n3300), .IN5(
n3479), .Q(n3453) );
AO22X1 U2860 ( .IN1(n3466), .IN2(n3321), .IN3(n3460), .IN4(n3322), .Q(n3479)
);
OA22X1 U2861 ( .IN1(\fpu_add_frac_dp/n589 ), .IN2(\fpu_add_frac_dp/n2294 ),
.IN3(\fpu_add_frac_dp/n272 ), .IN4(\fpu_add_frac_dp/n2271 ), .Q(n3460)
);
INVX0 U2862 ( .INP(n3124), .ZN(\fpu_add_frac_dp/n1554 ) );
XNOR3X1 U2863 ( .IN1(\fpu_add_frac_dp/n714 ), .IN2(\fpu_add_frac_dp/n525 ),
.IN3(n3480), .Q(n3124) );
AO221X1 U2864 ( .IN1(n3197), .IN2(n3004), .IN3(n1390), .IN4(n2815), .IN5(
n3481), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N23 ) );
AO222X1 U2865 ( .IN1(\fpu_add_frac_dp/n1555 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3275), .IN4(n3014), .IN5(\fpu_add_frac_dp/n1556 ), .IN6(n3065),
.Q(n3481) );
AOI222X1 U2866 ( .IN1(n3253), .IN2(n3482), .IN3(\fpu_add_frac_dp/n2471 ),
.IN4(n3459), .IN5(n3483), .IN6(n3258), .QN(n3014) );
AO221X1 U2867 ( .IN1(n3466), .IN2(n3322), .IN3(n3302), .IN4(n3484), .IN5(
n3485), .Q(n3459) );
AO22X1 U2868 ( .IN1(n3472), .IN2(n3321), .IN3(n3300), .IN4(n3478), .Q(n3485)
);
OA22X1 U2869 ( .IN1(\fpu_add_frac_dp/n589 ), .IN2(\fpu_add_frac_dp/n2414 ),
.IN3(\fpu_add_frac_dp/n274 ), .IN4(\fpu_add_frac_dp/n2271 ), .Q(n3466)
);
INVX0 U2870 ( .INP(n3125), .ZN(\fpu_add_frac_dp/n1555 ) );
XNOR3X1 U2871 ( .IN1(\fpu_add_frac_dp/n715 ), .IN2(\fpu_add_frac_dp/n524 ),
.IN3(n3486), .Q(n3125) );
AO221X1 U2872 ( .IN1(n3177), .IN2(n3002), .IN3(n1390), .IN4(n2976), .IN5(
n3487), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N22 ) );
AO222X1 U2873 ( .IN1(\fpu_add_frac_dp/n1556 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3013), .IN5(\fpu_add_frac_dp/n1557 ), .IN6(n3065),
.Q(n3487) );
AOI222X1 U2874 ( .IN1(n3488), .IN2(n3253), .IN3(\fpu_add_frac_dp/n2471 ),
.IN4(n3465), .IN5(n3489), .IN6(n3258), .QN(n3013) );
AO221X1 U2875 ( .IN1(n3302), .IN2(n3490), .IN3(n3300), .IN4(n3484), .IN5(
n3491), .Q(n3465) );
AO22X1 U2876 ( .IN1(n3478), .IN2(n3321), .IN3(n3472), .IN4(n3322), .Q(n3491)
);
OA22X1 U2877 ( .IN1(\fpu_add_frac_dp/n589 ), .IN2(\fpu_add_frac_dp/n2347 ),
.IN3(\fpu_add_frac_dp/n276 ), .IN4(\fpu_add_frac_dp/n2271 ), .Q(n3472)
);
NOR2X0 U2878 ( .IN1(n154), .IN2(\fpu_add_frac_dp/n2460 ), .QN(n3300) );
NOR2X0 U2879 ( .IN1(\fpu_add_frac_dp/n2449 ), .IN2(\fpu_add_frac_dp/n2460 ),
.QN(n3302) );
INVX0 U2880 ( .INP(n3126), .ZN(\fpu_add_frac_dp/n1556 ) );
XNOR3X1 U2881 ( .IN1(\fpu_add_frac_dp/n716 ), .IN2(\fpu_add_frac_dp/n523 ),
.IN3(n3492), .Q(n3126) );
AO221X1 U2882 ( .IN1(n3177), .IN2(n3000), .IN3(n1390), .IN4(n2975), .IN5(
n3493), .Q(\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N21 ) );
AO222X1 U2883 ( .IN1(\fpu_add_frac_dp/n1557 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(n3066), .IN4(n3012), .IN5(\fpu_add_frac_dp/n1558 ), .IN6(n3065),
.Q(n3493) );
AOI222X1 U2884 ( .IN1(n3253), .IN2(n3494), .IN3(\fpu_add_frac_dp/n2471 ),
.IN4(n3471), .IN5(n3258), .IN6(n3482), .QN(n3012) );
AO222X1 U2885 ( .IN1(n3321), .IN2(n3484), .IN3(n3478), .IN4(n3322), .IN5(
n3483), .IN6(n582), .Q(n3471) );
OA22X1 U2886 ( .IN1(\fpu_add_frac_dp/n589 ), .IN2(\fpu_add_frac_dp/n2412 ),
.IN3(\fpu_add_frac_dp/n278 ), .IN4(\fpu_add_frac_dp/n2271 ), .Q(n3478)
);
INVX0 U2887 ( .INP(n3127), .ZN(\fpu_add_frac_dp/n1557 ) );
XNOR3X1 U2888 ( .IN1(\fpu_add_frac_dp/n717 ), .IN2(\fpu_add_frac_dp/n522 ),
.IN3(n3495), .Q(n3127) );
AO221X1 U2889 ( .IN1(\fpu_add_frac_dp/n1559 ), .IN2(n3065), .IN3(n1389),
.IN4(n2974), .IN5(n3496), .Q(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N20 ) );
AO222X1 U2890 ( .IN1(n3177), .IN2(n3010), .IN3(n3066), .IN4(n3011), .IN5(
\fpu_add_frac_dp/n1558 ), .IN6(\fpu_add_frac_dp/n1509 ), .Q(n3496) );
INVX0 U2891 ( .INP(n3128), .ZN(\fpu_add_frac_dp/n1558 ) );
XNOR3X1 U2892 ( .IN1(\fpu_add_frac_dp/n718 ), .IN2(\fpu_add_frac_dp/n521 ),
.IN3(n3497), .Q(n3128) );
AOI222X1 U2893 ( .IN1(n3498), .IN2(n3253), .IN3(\fpu_add_frac_dp/n2471 ),
.IN4(n3477), .IN5(n3488), .IN6(n3258), .QN(n3011) );
AO222X1 U2894 ( .IN1(n3490), .IN2(n3321), .IN3(n3484), .IN4(n3322), .IN5(
n3489), .IN6(n582), .Q(n3477) );
INVX0 U2895 ( .INP(n3166), .ZN(n3322) );
NAND2X0 U2896 ( .IN1(\fpu_add_frac_dp/n2460 ), .IN2(\fpu_add_frac_dp/n2449 ),
.QN(n3166) );
OA22X1 U2897 ( .IN1(\fpu_add_frac_dp/n589 ), .IN2(\fpu_add_frac_dp/n2348 ),
.IN3(\fpu_add_frac_dp/n280 ), .IN4(\fpu_add_frac_dp/n2271 ), .Q(n3484)
);
INVX0 U2898 ( .INP(n3164), .ZN(n3321) );
NAND2X0 U2899 ( .IN1(\fpu_add_frac_dp/n2460 ), .IN2(n154), .QN(n3164) );
AOI221X1 U2900 ( .IN1(n3253), .IN2(n3499), .IN3(n3500), .IN4(n3255), .IN5(
n3501), .QN(n3010) );
AO22X1 U2901 ( .IN1(n3258), .IN2(n3502), .IN3(n3503), .IN4(n3260), .Q(n3501)
);
AO221X1 U2902 ( .IN1(\fpu_add_frac_dp/n1560 ), .IN2(n3065), .IN3(n1390),
.IN4(n2800), .IN5(n3504), .Q(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N19 ) );
AO222X1 U2903 ( .IN1(n3177), .IN2(n3008), .IN3(n3066), .IN4(n3009), .IN5(
\fpu_add_frac_dp/n1559 ), .IN6(\fpu_add_frac_dp/n1509 ), .Q(n3504) );
INVX0 U2904 ( .INP(n3129), .ZN(\fpu_add_frac_dp/n1559 ) );
XNOR3X1 U2905 ( .IN1(\fpu_add_frac_dp/n719 ), .IN2(\fpu_add_frac_dp/n520 ),
.IN3(n3505), .Q(n3129) );
AOI221X1 U2906 ( .IN1(n3483), .IN2(n3260), .IN3(n3258), .IN4(n3494), .IN5(
n3506), .QN(n3009) );
AO22X1 U2907 ( .IN1(n3507), .IN2(n3253), .IN3(n3255), .IN4(n3482), .Q(n3506)
);
OA22X1 U2908 ( .IN1(n154), .IN2(n3490), .IN3(n3508), .IN4(
\fpu_add_frac_dp/n2417 ), .Q(n3483) );
OA22X1 U2909 ( .IN1(\fpu_add_frac_dp/n589 ), .IN2(\fpu_add_frac_dp/n2401 ),
.IN3(\fpu_add_frac_dp/n282 ), .IN4(\fpu_add_frac_dp/n2271 ), .Q(n3490)
);
AOI221X1 U2910 ( .IN1(n3253), .IN2(n3509), .IN3(n3510), .IN4(n3255), .IN5(
n3511), .QN(n3008) );
AO22X1 U2911 ( .IN1(n3512), .IN2(n3260), .IN3(n3258), .IN4(n3513), .Q(n3511)
);
AO221X1 U2912 ( .IN1(\fpu_add_frac_dp/n1561 ), .IN2(n3065), .IN3(n1389),
.IN4(n2798), .IN5(n3514), .Q(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N18 ) );
AO222X1 U2913 ( .IN1(n3177), .IN2(n2997), .IN3(n3066), .IN4(n3007), .IN5(
\fpu_add_frac_dp/n1560 ), .IN6(\fpu_add_frac_dp/n1509 ), .Q(n3514) );
INVX0 U2914 ( .INP(n3130), .ZN(\fpu_add_frac_dp/n1560 ) );
XNOR3X1 U2915 ( .IN1(\fpu_add_frac_dp/n720 ), .IN2(\fpu_add_frac_dp/n519 ),
.IN3(n3515), .Q(n3130) );
AOI221X1 U2916 ( .IN1(n3503), .IN2(n3253), .IN3(n3488), .IN4(n3255), .IN5(
n3516), .QN(n3007) );
AO22X1 U2917 ( .IN1(n3498), .IN2(n3258), .IN3(n3489), .IN4(n3260), .Q(n3516)
);
AOI22X1 U2918 ( .IN1(n3517), .IN2(n130), .IN3(n3518), .IN4(n45), .QN(n3489)
);
AOI222X1 U2919 ( .IN1(n3502), .IN2(n3255), .IN3(n3519), .IN4(n63), .IN5(
n3500), .IN6(n3260), .QN(n2997) );
AO221X1 U2920 ( .IN1(\fpu_add_frac_dp/n1562 ), .IN2(n3065), .IN3(n1390),
.IN4(n2794), .IN5(n3520), .Q(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N17 ) );
AO222X1 U2921 ( .IN1(n3197), .IN2(n2996), .IN3(n3275), .IN4(n3006), .IN5(
\fpu_add_frac_dp/n1561 ), .IN6(\fpu_add_frac_dp/n1509 ), .Q(n3520) );
INVX0 U2922 ( .INP(n3131), .ZN(\fpu_add_frac_dp/n1561 ) );
XNOR3X1 U2923 ( .IN1(\fpu_add_frac_dp/n721 ), .IN2(\fpu_add_frac_dp/n518 ),
.IN3(n3521), .Q(n3131) );
AOI221X1 U2924 ( .IN1(n3253), .IN2(n3512), .IN3(n3255), .IN4(n3494), .IN5(
n3522), .QN(n3006) );
AO22X1 U2925 ( .IN1(n3507), .IN2(n3258), .IN3(n3260), .IN4(n3482), .Q(n3522)
);
NAND2X0 U2926 ( .IN1(n3523), .IN2(n596), .QN(n3482) );
MUX21X1 U2927 ( .IN1(n257), .IN2(n45), .S(\fpu_add_frac_dp/n2449 ), .Q(n3523) );
AOI222X1 U2928 ( .IN1(n3255), .IN2(n3513), .IN3(n3072), .IN4(n63), .IN5(
n3510), .IN6(n3260), .QN(n2996) );
AO221X1 U2929 ( .IN1(\fpu_add_frac_dp/n1563 ), .IN2(n3065), .IN3(n1389),
.IN4(n2792), .IN5(n3524), .Q(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N16 ) );
AO222X1 U2930 ( .IN1(n3177), .IN2(n2995), .IN3(n3066), .IN4(n3005), .IN5(
\fpu_add_frac_dp/n1562 ), .IN6(\fpu_add_frac_dp/n1509 ), .Q(n3524) );
INVX0 U2931 ( .INP(n3132), .ZN(\fpu_add_frac_dp/n1562 ) );
XNOR3X1 U2932 ( .IN1(\fpu_add_frac_dp/n722 ), .IN2(\fpu_add_frac_dp/n517 ),
.IN3(n3525), .Q(n3132) );
AOI221X1 U2933 ( .IN1(n3253), .IN2(n3500), .IN3(n3498), .IN4(n3255), .IN5(
n3526), .QN(n3005) );
AO22X1 U2934 ( .IN1(n3503), .IN2(n3258), .IN3(n3488), .IN4(n3260), .Q(n3526)
);
AOI22X1 U2935 ( .IN1(n3517), .IN2(n257), .IN3(n3518), .IN4(n107), .QN(n3488)
);
INVX0 U2936 ( .INP(n3508), .ZN(n3518) );
NAND2X0 U2937 ( .IN1(n154), .IN2(n596), .QN(n3508) );
AOI222X1 U2938 ( .IN1(n3255), .IN2(n3499), .IN3(n63), .IN4(n3070), .IN5(
n3502), .IN6(n3260), .QN(n2995) );
NAND2X0 U2939 ( .IN1(\fpu_add_frac_dp/n2460 ), .IN2(n3527), .QN(n3070) );
INVX0 U2940 ( .INP(n3528), .ZN(n3499) );
AO221X1 U2941 ( .IN1(\fpu_add_frac_dp/n1564 ), .IN2(n3065), .IN3(n1390),
.IN4(n2788), .IN5(n3529), .Q(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N15 ) );
AO222X1 U2942 ( .IN1(n3177), .IN2(n2993), .IN3(n3066), .IN4(n3004), .IN5(
\fpu_add_frac_dp/n1563 ), .IN6(\fpu_add_frac_dp/n1509 ), .Q(n3529) );
INVX0 U2943 ( .INP(n3133), .ZN(\fpu_add_frac_dp/n1563 ) );
XNOR3X1 U2944 ( .IN1(\fpu_add_frac_dp/n723 ), .IN2(\fpu_add_frac_dp/n516 ),
.IN3(n3530), .Q(n3133) );
AOI221X1 U2945 ( .IN1(n3253), .IN2(n3510), .IN3(n3507), .IN4(n3255), .IN5(
n3531), .QN(n3004) );
AO22X1 U2946 ( .IN1(n3512), .IN2(n3258), .IN3(n3260), .IN4(n3494), .Q(n3531)
);
NAND2X0 U2947 ( .IN1(n3532), .IN2(n596), .QN(n3494) );
MUX21X1 U2948 ( .IN1(n264), .IN2(n107), .S(\fpu_add_frac_dp/n2449 ), .Q(
n3532) );
AND2X1 U2949 ( .IN1(\fpu_add_ctl/n319 ), .IN2(n2994), .Q(n3066) );
AOI222X1 U2950 ( .IN1(n3513), .IN2(n3260), .IN3(n63), .IN4(n3444), .IN5(
n3255), .IN6(n3509), .QN(n2993) );
INVX0 U2951 ( .INP(n3533), .ZN(n3509) );
NAND3X0 U2952 ( .IN1(n3534), .IN2(n219), .IN3(\fpu_add_frac_dp/n2460 ), .QN(
n3444) );
INVX0 U2953 ( .INP(n3173), .ZN(n3177) );
NAND2X0 U2954 ( .IN1(\fpu_add_ctl/n319 ), .IN2(n3003), .QN(n3173) );
NOR2X0 U2955 ( .IN1(n1745), .IN2(\fpu_add_frac_dp/n2307 ), .QN(n3003) );
AO221X1 U2956 ( .IN1(n1389), .IN2(n2786), .IN3(\fpu_add_frac_dp/n1565 ),
.IN4(n3065), .IN5(n3535), .Q(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N14 ) );
AO222X1 U2957 ( .IN1(n3275), .IN2(n3002), .IN3(n3536), .IN4(n3197), .IN5(
\fpu_add_frac_dp/n1564 ), .IN6(\fpu_add_frac_dp/n1509 ), .Q(n3535) );
INVX0 U2958 ( .INP(n3134), .ZN(\fpu_add_frac_dp/n1564 ) );
XNOR3X1 U2959 ( .IN1(\fpu_add_frac_dp/n724 ), .IN2(\fpu_add_frac_dp/n514 ),
.IN3(n3537), .Q(n3134) );
NOR2X0 U2960 ( .IN1(n63), .IN2(n3519), .QN(n3536) );
INVX0 U2961 ( .INP(n2992), .ZN(n3519) );
MUX21X1 U2962 ( .IN1(n3527), .IN2(n3528), .S(\fpu_add_frac_dp/n2460 ), .Q(
n2992) );
AO22X1 U2963 ( .IN1(n3538), .IN2(n115), .IN3(n3534), .IN4(n50), .Q(n3528) );
AO22X1 U2964 ( .IN1(n3538), .IN2(n219), .IN3(n3534), .IN4(n48), .Q(n3527) );
AOI221X1 U2965 ( .IN1(n3253), .IN2(n3502), .IN3(n3503), .IN4(n3255), .IN5(
n3539), .QN(n3002) );
AO22X1 U2966 ( .IN1(n3498), .IN2(n3260), .IN3(n3258), .IN4(n3500), .Q(n3539)
);
AOI22X1 U2967 ( .IN1(n3534), .IN2(n286), .IN3(n3538), .IN4(n124), .QN(n3500)
);
AOI22X1 U2968 ( .IN1(n3517), .IN2(n264), .IN3(n3538), .IN4(n119), .QN(n3498)
);
NOR2X0 U2969 ( .IN1(n154), .IN2(\fpu_add_frac_dp/n2271 ), .QN(n3517) );
AOI22X1 U2970 ( .IN1(n3534), .IN2(n285), .IN3(n3538), .IN4(n123), .QN(n3503)
);
AOI22X1 U2971 ( .IN1(n3538), .IN2(n284), .IN3(n3534), .IN4(n51), .QN(n3502)
);
AO221X1 U2972 ( .IN1(\fpu_add_frac_dp/n1565 ), .IN2(\fpu_add_frac_dp/n1509 ),
.IN3(\fpu_add_frac_dp/n1566 ), .IN4(n3065), .IN5(n3540), .Q(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre2/N13 ) );
AO222X1 U2973 ( .IN1(n1415), .IN2(n2973), .IN3(n3541), .IN4(n3197), .IN5(
n3275), .IN6(n3000), .Q(n3540) );
AOI221X1 U2974 ( .IN1(n3253), .IN2(n3513), .IN3(n3512), .IN4(n3255), .IN5(
n3542), .QN(n3000) );
AO22X1 U2975 ( .IN1(n3507), .IN2(n3260), .IN3(n3258), .IN4(n3510), .Q(n3542)
);
AOI22X1 U2976 ( .IN1(n3534), .IN2(n124), .IN3(n3538), .IN4(n51), .QN(n3510)
);
NOR2X0 U2977 ( .IN1(n582), .IN2(\fpu_add_frac_dp/n2471 ), .QN(n3258) );
NOR2X0 U2978 ( .IN1(n63), .IN2(n582), .QN(n3260) );
AOI22X1 U2979 ( .IN1(n3538), .IN2(n285), .IN3(n3534), .IN4(n119), .QN(n3507)
);
NOR2X0 U2980 ( .IN1(n63), .IN2(\fpu_add_frac_dp/n2460 ), .QN(n3255) );
AOI22X1 U2981 ( .IN1(n3538), .IN2(n286), .IN3(n3534), .IN4(n123), .QN(n3512)
);
AOI22X1 U2982 ( .IN1(n3534), .IN2(n284), .IN3(n3538), .IN4(n50), .QN(n3513)
);
NOR2X0 U2983 ( .IN1(\fpu_add_frac_dp/n2460 ), .IN2(\fpu_add_frac_dp/n2471 ),
.QN(n3253) );
NOR2X0 U2984 ( .IN1(n3155), .IN2(n584), .QN(n3275) );
NOR2X0 U2985 ( .IN1(n3155), .IN2(\fpu_add_frac_dp/n2307 ), .QN(n3197) );
NAND2X0 U2986 ( .IN1(\fpu_add_ctl/n319 ), .IN2(n1449), .QN(n3155) );
NOR2X0 U2987 ( .IN1(n63), .IN2(n3072), .QN(n3541) );
INVX0 U2988 ( .INP(n2991), .ZN(n3072) );
MUX21X1 U2989 ( .IN1(n3543), .IN2(n3533), .S(\fpu_add_frac_dp/n2460 ), .Q(
n2991) );
AO22X1 U2990 ( .IN1(n3534), .IN2(n115), .IN3(n3538), .IN4(n48), .Q(n3533) );
NOR2X0 U2991 ( .IN1(\fpu_add_frac_dp/n2449 ), .IN2(\fpu_add_frac_dp/n586 ),
.QN(n3538) );
AND2X1 U2992 ( .IN1(n219), .IN2(n3534), .Q(n3543) );
NOR2X0 U2993 ( .IN1(n154), .IN2(\fpu_add_frac_dp/n586 ), .QN(n3534) );
NAND2X0 U2994 ( .IN1(\fpu_add_ctl/a3stg_opdec_9_0[3] ), .IN2(n1449), .QN(
n3071) );
INVX0 U2995 ( .INP(n3136), .ZN(\fpu_add_frac_dp/n1566 ) );
XNOR3X1 U2996 ( .IN1(\fpu_add_frac_dp/n726 ), .IN2(\fpu_add_frac_dp/n511 ),
.IN3(n3544), .Q(n3136) );
NAND2X0 U2997 ( .IN1(n3142), .IN2(n3545), .QN(n3157) );
NAND2X0 U2998 ( .IN1(n1449), .IN2(n3546), .QN(n3156) );
AO21X1 U2999 ( .IN1(n3547), .IN2(n133), .IN3(n336), .Q(n3546) );
INVX0 U3000 ( .INP(n3135), .ZN(\fpu_add_frac_dp/n1565 ) );
XNOR3X1 U3001 ( .IN1(\fpu_add_frac_dp/n725 ), .IN2(\fpu_add_frac_dp/n512 ),
.IN3(n3548), .Q(n3135) );
AND4X1 U3002 ( .IN1(n3146), .IN2(n2601), .IN3(n3142), .IN4(n3175), .Q(
\fpu_add_frac_dp/i_a4stg_rnd_frac_pre1/N66 ) );
NOR2X0 U3003 ( .IN1(n1745), .IN2(\fpu_add_ctl/n141 ), .QN(n3142) );
MUX21X1 U3004 ( .IN1(n3549), .IN2(n1330), .S(n3550), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N9 ) );
OA221X1 U3005 ( .IN1(\fpu_add_frac_dp/n507 ), .IN2(n1312), .IN3(n3551),
.IN4(n3552), .IN5(n3553), .Q(n3550) );
OA21X1 U3006 ( .IN1(n3554), .IN2(n3555), .IN3(n3556), .Q(n3553) );
MUX21X1 U3007 ( .IN1(n3549), .IN2(n1331), .S(n3557), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N8 ) );
OA221X1 U3008 ( .IN1(\fpu_add_frac_dp/n508 ), .IN2(n1313), .IN3(n3558),
.IN4(n3555), .IN5(n3559), .Q(n3557) );
OA21X1 U3009 ( .IN1(n3554), .IN2(n3552), .IN3(n3556), .Q(n3559) );
AOI221X1 U3010 ( .IN1(n3560), .IN2(n3561), .IN3(n3562), .IN4(n3563), .IN5(
n3564), .QN(n3554) );
AO22X1 U3011 ( .IN1(n3565), .IN2(n3566), .IN3(n3567), .IN4(n3568), .Q(n3564)
);
MUX21X1 U3012 ( .IN1(n3549), .IN2(n1332), .S(n3569), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N7 ) );
OA221X1 U3013 ( .IN1(\fpu_add_frac_dp/n506 ), .IN2(n1314), .IN3(n3570),
.IN4(n3555), .IN5(n3571), .Q(n3569) );
OA21X1 U3014 ( .IN1(n3558), .IN2(n3552), .IN3(n3556), .Q(n3571) );
AOI221X1 U3015 ( .IN1(n3562), .IN2(n3572), .IN3(n3567), .IN4(n3573), .IN5(
n3574), .QN(n3558) );
AO22X1 U3016 ( .IN1(n3565), .IN2(n3575), .IN3(n3560), .IN4(n3576), .Q(n3574)
);
MUX21X1 U3017 ( .IN1(n3549), .IN2(n1330), .S(n3577), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N66 ) );
OA22X1 U3018 ( .IN1(n3578), .IN2(n3579), .IN3(\fpu_add_frac_dp/n569 ), .IN4(
n1312), .Q(n3577) );
MUX21X1 U3019 ( .IN1(n3549), .IN2(n1331), .S(n3580), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N65 ) );
OA221X1 U3020 ( .IN1(\fpu_add_frac_dp/n568 ), .IN2(n1311), .IN3(n3581),
.IN4(n3582), .IN5(n3583), .Q(n3580) );
OA21X1 U3021 ( .IN1(n3578), .IN2(n3584), .IN3(n3556), .Q(n3583) );
MUX21X1 U3022 ( .IN1(n3549), .IN2(n1332), .S(n3585), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N64 ) );
OA221X1 U3023 ( .IN1(\fpu_add_frac_dp/n567 ), .IN2(n1312), .IN3(n3586),
.IN4(n3582), .IN5(n3587), .Q(n3585) );
OA21X1 U3024 ( .IN1(n3581), .IN2(n3588), .IN3(n3556), .Q(n3587) );
AOI22X1 U3025 ( .IN1(n3589), .IN2(n166), .IN3(n3590), .IN4(n3591), .QN(n3581) );
NOR2X0 U3026 ( .IN1(\fpu_add_frac_dp/n2270 ), .IN2(n641), .QN(n3590) );
INVX0 U3027 ( .INP(n3578), .ZN(n3589) );
NAND2X0 U3028 ( .IN1(n3591), .IN2(n15), .QN(n3578) );
MUX21X1 U3029 ( .IN1(n3549), .IN2(n1330), .S(n3592), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N63 ) );
OA221X1 U3030 ( .IN1(\fpu_add_frac_dp/n566 ), .IN2(n1313), .IN3(n3593),
.IN4(n3579), .IN5(n3594), .Q(n3592) );
OA221X1 U3031 ( .IN1(n3586), .IN2(n3588), .IN3(n3582), .IN4(n3595), .IN5(
n3556), .Q(n3594) );
NAND2X0 U3032 ( .IN1(n3596), .IN2(n166), .QN(n3595) );
AOI22X1 U3033 ( .IN1(\fpu_add_frac_dp/n2385 ), .IN2(n3596), .IN3(n3597),
.IN4(n3591), .QN(n3586) );
NOR2X0 U3034 ( .IN1(\fpu_add_frac_dp/n5641 ), .IN2(\fpu_add_frac_dp/n2270 ),
.QN(n3597) );
MUX21X1 U3035 ( .IN1(n3549), .IN2(n1331), .S(n3598), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N62 ) );
OA221X1 U3036 ( .IN1(\fpu_add_frac_dp/n565 ), .IN2(n1314), .IN3(n3599),
.IN4(n3579), .IN5(n3600), .Q(n3598) );
OA221X1 U3037 ( .IN1(n3593), .IN2(n3601), .IN3(n3602), .IN4(n3603), .IN5(
n3556), .Q(n3600) );
INVX0 U3038 ( .INP(n3596), .ZN(n3602) );
AO22X1 U3039 ( .IN1(n3604), .IN2(n15), .IN3(n3591), .IN4(n3), .Q(n3596) );
MUX21X1 U3040 ( .IN1(n3549), .IN2(n1332), .S(n3605), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N61 ) );
OA221X1 U3041 ( .IN1(\fpu_add_frac_dp/n564 ), .IN2(n1311), .IN3(n3606),
.IN4(n3579), .IN5(n3607), .Q(n3605) );
OA221X1 U3042 ( .IN1(n3601), .IN2(n3599), .IN3(n3593), .IN4(n3603), .IN5(
n3556), .Q(n3607) );
AOI22X1 U3043 ( .IN1(n3604), .IN2(n16), .IN3(n3591), .IN4(n156), .QN(n3593)
);
MUX21X1 U3044 ( .IN1(n3549), .IN2(n1330), .S(n3608), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N60 ) );
OA221X1 U3045 ( .IN1(\fpu_add_frac_dp/n563 ), .IN2(n1312), .IN3(n3609),
.IN4(n3579), .IN5(n3610), .Q(n3608) );
OA221X1 U3046 ( .IN1(n3601), .IN2(n3606), .IN3(n3599), .IN4(n3603), .IN5(
n3556), .Q(n3610) );
AOI222X1 U3047 ( .IN1(n3604), .IN2(n3), .IN3(n3591), .IN4(n68), .IN5(n3611),
.IN6(n15), .QN(n3599) );
MUX21X1 U3048 ( .IN1(n3549), .IN2(n1331), .S(n3612), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N6 ) );
OA221X1 U3049 ( .IN1(\fpu_add_frac_dp/n505 ), .IN2(n1313), .IN3(n3613),
.IN4(n3555), .IN5(n3614), .Q(n3612) );
OA21X1 U3050 ( .IN1(n3570), .IN2(n3552), .IN3(n3556), .Q(n3614) );
AOI221X1 U3051 ( .IN1(n3560), .IN2(n3615), .IN3(n3567), .IN4(n3561), .IN5(
n3616), .QN(n3570) );
AO22X1 U3052 ( .IN1(n3562), .IN2(n3568), .IN3(n3565), .IN4(n3563), .Q(n3616)
);
MUX21X1 U3053 ( .IN1(n3549), .IN2(n1332), .S(n3617), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N59 ) );
OA221X1 U3054 ( .IN1(\fpu_add_frac_dp/n562 ), .IN2(n1314), .IN3(n3618),
.IN4(n3579), .IN5(n3619), .Q(n3617) );
OA221X1 U3055 ( .IN1(n3601), .IN2(n3609), .IN3(n3606), .IN4(n3603), .IN5(
n3556), .Q(n3619) );
AOI222X1 U3056 ( .IN1(n3604), .IN2(n156), .IN3(n3591), .IN4(n1857), .IN5(
n3611), .IN6(n16), .QN(n3606) );
MUX21X1 U3057 ( .IN1(n3549), .IN2(n1330), .S(n3620), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N58 ) );
OA221X1 U3058 ( .IN1(\fpu_add_frac_dp/n561 ), .IN2(n1311), .IN3(n3621),
.IN4(n3579), .IN5(n3622), .Q(n3620) );
OA221X1 U3059 ( .IN1(n3601), .IN2(n3618), .IN3(n3609), .IN4(n3603), .IN5(
n3556), .Q(n3622) );
AOI221X1 U3060 ( .IN1(n3591), .IN2(n157), .IN3(n3604), .IN4(n68), .IN5(n3623), .QN(n3609) );
AO22X1 U3061 ( .IN1(n3624), .IN2(n15), .IN3(n3611), .IN4(n3), .Q(n3623) );
MUX21X1 U3062 ( .IN1(n3549), .IN2(n1331), .S(n3625), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N57 ) );
OA221X1 U3063 ( .IN1(\fpu_add_frac_dp/n560 ), .IN2(n1312), .IN3(n3626),
.IN4(n3579), .IN5(n3627), .Q(n3625) );
OA221X1 U3064 ( .IN1(n3601), .IN2(n3621), .IN3(n3618), .IN4(n3603), .IN5(
n3556), .Q(n3627) );
AOI221X1 U3065 ( .IN1(n3591), .IN2(n4), .IN3(n3604), .IN4(n1857), .IN5(n3628), .QN(n3618) );
AO22X1 U3066 ( .IN1(n3624), .IN2(n16), .IN3(n3611), .IN4(n156), .Q(n3628) );
AND2X1 U3067 ( .IN1(n3629), .IN2(n3560), .Q(n3591) );
MUX21X1 U3068 ( .IN1(n3549), .IN2(n1332), .S(n3630), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N56 ) );
OA221X1 U3069 ( .IN1(\fpu_add_frac_dp/n559 ), .IN2(n1313), .IN3(n3631),
.IN4(n3579), .IN5(n3632), .Q(n3630) );
OA221X1 U3070 ( .IN1(n3601), .IN2(n3626), .IN3(n3621), .IN4(n3603), .IN5(
n3556), .Q(n3632) );
AOI221X1 U3071 ( .IN1(n3604), .IN2(n157), .IN3(n3611), .IN4(n68), .IN5(n3633), .QN(n3621) );
AO22X1 U3072 ( .IN1(n3560), .IN2(n3634), .IN3(n3624), .IN4(n3), .Q(n3633) );
MUX21X1 U3073 ( .IN1(n3549), .IN2(n1330), .S(n3635), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N55 ) );
OA221X1 U3074 ( .IN1(\fpu_add_frac_dp/n558 ), .IN2(n1314), .IN3(n3636),
.IN4(n3579), .IN5(n3637), .Q(n3635) );
OA221X1 U3075 ( .IN1(n3601), .IN2(n3631), .IN3(n3626), .IN4(n3603), .IN5(
n3556), .Q(n3637) );
AOI221X1 U3076 ( .IN1(n3604), .IN2(n4), .IN3(n3611), .IN4(n1857), .IN5(n3638), .QN(n3626) );
AO22X1 U3077 ( .IN1(n3560), .IN2(n3639), .IN3(n3624), .IN4(n156), .Q(n3638)
);
AND2X1 U3078 ( .IN1(n3629), .IN2(n3567), .Q(n3604) );
MUX21X1 U3079 ( .IN1(n3549), .IN2(n1331), .S(n3640), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N54 ) );
OA221X1 U3080 ( .IN1(\fpu_add_frac_dp/n557 ), .IN2(n1311), .IN3(n3641),
.IN4(n3579), .IN5(n3642), .Q(n3640) );
OA221X1 U3081 ( .IN1(n3601), .IN2(n3636), .IN3(n3631), .IN4(n3603), .IN5(
n3556), .Q(n3642) );
AOI221X1 U3082 ( .IN1(n3611), .IN2(n157), .IN3(n3624), .IN4(n68), .IN5(n3643), .QN(n3631) );
AO22X1 U3083 ( .IN1(n3560), .IN2(n3644), .IN3(n3567), .IN4(n3634), .Q(n3643)
);
MUX21X1 U3084 ( .IN1(n3549), .IN2(n1332), .S(n3645), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N53 ) );
OA221X1 U3085 ( .IN1(\fpu_add_frac_dp/n556 ), .IN2(n1312), .IN3(n3646),
.IN4(n3579), .IN5(n3647), .Q(n3645) );
OA221X1 U3086 ( .IN1(n3601), .IN2(n3641), .IN3(n3636), .IN4(n3603), .IN5(
n3556), .Q(n3647) );
AOI221X1 U3087 ( .IN1(n3611), .IN2(n4), .IN3(n3624), .IN4(n1857), .IN5(n3648), .QN(n3636) );
AO22X1 U3088 ( .IN1(n3560), .IN2(n3649), .IN3(n3567), .IN4(n3639), .Q(n3648)
);
AND2X1 U3089 ( .IN1(n3629), .IN2(n3562), .Q(n3611) );
MUX21X1 U3090 ( .IN1(n3549), .IN2(n1330), .S(n3650), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N52 ) );
OA221X1 U3091 ( .IN1(\fpu_add_frac_dp/n555 ), .IN2(n1313), .IN3(n3651),
.IN4(n3579), .IN5(n3652), .Q(n3650) );
OA221X1 U3092 ( .IN1(n3601), .IN2(n3646), .IN3(n3641), .IN4(n3603), .IN5(
n3556), .Q(n3652) );
AOI221X1 U3093 ( .IN1(n3624), .IN2(n157), .IN3(n3562), .IN4(n3634), .IN5(
n3653), .QN(n3641) );
AO22X1 U3094 ( .IN1(n3560), .IN2(n3654), .IN3(n3567), .IN4(n3644), .Q(n3653)
);
MUX21X1 U3095 ( .IN1(n3549), .IN2(n1331), .S(n3655), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N51 ) );
OA221X1 U3096 ( .IN1(\fpu_add_frac_dp/n554 ), .IN2(n1314), .IN3(n3656),
.IN4(n3579), .IN5(n3657), .Q(n3655) );
OA221X1 U3097 ( .IN1(n3601), .IN2(n3651), .IN3(n3646), .IN4(n3603), .IN5(
n3556), .Q(n3657) );
AOI221X1 U3098 ( .IN1(n3624), .IN2(n4), .IN3(n3562), .IN4(n3639), .IN5(n3658), .QN(n3646) );
AO22X1 U3099 ( .IN1(n3560), .IN2(n3659), .IN3(n3567), .IN4(n3649), .Q(n3658)
);
AND2X1 U3100 ( .IN1(n3629), .IN2(n3565), .Q(n3624) );
MUX21X1 U3101 ( .IN1(n3549), .IN2(n1332), .S(n3660), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N50 ) );
OA221X1 U3102 ( .IN1(\fpu_add_frac_dp/n553 ), .IN2(n1311), .IN3(n3661),
.IN4(n3579), .IN5(n3662), .Q(n3660) );
OA221X1 U3103 ( .IN1(n3601), .IN2(n3656), .IN3(n3651), .IN4(n3603), .IN5(
n3556), .Q(n3662) );
AOI221X1 U3104 ( .IN1(n3567), .IN2(n3654), .IN3(n3560), .IN4(n3663), .IN5(
n3664), .QN(n3651) );
AO22X1 U3105 ( .IN1(n3562), .IN2(n3644), .IN3(n3565), .IN4(n3634), .Q(n3664)
);
AO22X1 U3106 ( .IN1(n3665), .IN2(n15), .IN3(n3629), .IN4(n98), .Q(n3634) );
MUX21X1 U3107 ( .IN1(n3549), .IN2(n1330), .S(n3666), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N5 ) );
OA221X1 U3108 ( .IN1(\fpu_add_frac_dp/n504 ), .IN2(n1312), .IN3(n3667),
.IN4(n3555), .IN5(n3668), .Q(n3666) );
OA21X1 U3109 ( .IN1(n3613), .IN2(n3552), .IN3(n3556), .Q(n3668) );
AOI221X1 U3110 ( .IN1(n3560), .IN2(n3669), .IN3(n3567), .IN4(n3576), .IN5(
n3670), .QN(n3613) );
AO22X1 U3111 ( .IN1(n3565), .IN2(n3572), .IN3(n3562), .IN4(n3573), .Q(n3670)
);
MUX21X1 U3112 ( .IN1(n3549), .IN2(n1331), .S(n3671), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N49 ) );
OA221X1 U3113 ( .IN1(\fpu_add_frac_dp/n552 ), .IN2(n1313), .IN3(n3672),
.IN4(n3579), .IN5(n3673), .Q(n3671) );
OA221X1 U3114 ( .IN1(n3601), .IN2(n3661), .IN3(n3656), .IN4(n3603), .IN5(
n3556), .Q(n3673) );
AOI221X1 U3115 ( .IN1(n3567), .IN2(n3659), .IN3(n3560), .IN4(n3674), .IN5(
n3675), .QN(n3656) );
AO22X1 U3116 ( .IN1(n3562), .IN2(n3649), .IN3(n3565), .IN4(n3639), .Q(n3675)
);
AO22X1 U3117 ( .IN1(n3665), .IN2(n16), .IN3(n3629), .IN4(n97), .Q(n3639) );
MUX21X1 U3118 ( .IN1(n3549), .IN2(n1332), .S(n3676), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N48 ) );
OA221X1 U3119 ( .IN1(\fpu_add_frac_dp/n551 ), .IN2(n1314), .IN3(n3677),
.IN4(n3579), .IN5(n3678), .Q(n3676) );
OA221X1 U3120 ( .IN1(n3601), .IN2(n3672), .IN3(n3661), .IN4(n3603), .IN5(
n3556), .Q(n3678) );
AOI221X1 U3121 ( .IN1(n3567), .IN2(n3663), .IN3(n3560), .IN4(n3679), .IN5(
n3680), .QN(n3661) );
AO22X1 U3122 ( .IN1(n3562), .IN2(n3654), .IN3(n3565), .IN4(n3644), .Q(n3680)
);
AO22X1 U3123 ( .IN1(n3665), .IN2(n3), .IN3(n3629), .IN4(n613), .Q(n3644) );
MUX21X1 U3124 ( .IN1(n3549), .IN2(n1330), .S(n3681), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N47 ) );
OA221X1 U3125 ( .IN1(\fpu_add_frac_dp/n550 ), .IN2(n1311), .IN3(n3682),
.IN4(n3579), .IN5(n3683), .Q(n3681) );
OA221X1 U3126 ( .IN1(n3601), .IN2(n3677), .IN3(n3672), .IN4(n3603), .IN5(
n3556), .Q(n3683) );
AOI221X1 U3127 ( .IN1(n3567), .IN2(n3674), .IN3(n3560), .IN4(n3684), .IN5(
n3685), .QN(n3672) );
AO22X1 U3128 ( .IN1(n3562), .IN2(n3659), .IN3(n3565), .IN4(n3649), .Q(n3685)
);
AO22X1 U3129 ( .IN1(n3665), .IN2(n156), .IN3(n3629), .IN4(n95), .Q(n3649) );
MUX21X1 U3130 ( .IN1(n3549), .IN2(n1331), .S(n3686), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N46 ) );
OA221X1 U3131 ( .IN1(\fpu_add_frac_dp/n549 ), .IN2(n1312), .IN3(n3687),
.IN4(n3579), .IN5(n3688), .Q(n3686) );
OA221X1 U3132 ( .IN1(n3601), .IN2(n3682), .IN3(n3677), .IN4(n3603), .IN5(
n3556), .Q(n3688) );
AOI221X1 U3133 ( .IN1(n3567), .IN2(n3679), .IN3(n3560), .IN4(n3689), .IN5(
n3690), .QN(n3677) );
AO22X1 U3134 ( .IN1(n3562), .IN2(n3663), .IN3(n3565), .IN4(n3654), .Q(n3690)
);
AO22X1 U3135 ( .IN1(n3665), .IN2(n68), .IN3(n3629), .IN4(n632), .Q(n3654) );
MUX21X1 U3136 ( .IN1(n3549), .IN2(n1332), .S(n3691), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N45 ) );
OA221X1 U3137 ( .IN1(\fpu_add_frac_dp/n548 ), .IN2(n1313), .IN3(n3692),
.IN4(n3579), .IN5(n3693), .Q(n3691) );
OA221X1 U3138 ( .IN1(n3601), .IN2(n3687), .IN3(n3682), .IN4(n3603), .IN5(
n3556), .Q(n3693) );
AOI221X1 U3139 ( .IN1(n3567), .IN2(n3684), .IN3(n3560), .IN4(n3694), .IN5(
n3695), .QN(n3682) );
AO22X1 U3140 ( .IN1(n3562), .IN2(n3674), .IN3(n3565), .IN4(n3659), .Q(n3695)
);
AO22X1 U3141 ( .IN1(n3665), .IN2(n1857), .IN3(n3629), .IN4(n630), .Q(n3659)
);
MUX21X1 U3142 ( .IN1(n3549), .IN2(n1330), .S(n3696), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N44 ) );
OA221X1 U3143 ( .IN1(\fpu_add_frac_dp/n547 ), .IN2(n1314), .IN3(n3697),
.IN4(n3579), .IN5(n3698), .Q(n3696) );
OA221X1 U3144 ( .IN1(n3601), .IN2(n3692), .IN3(n3687), .IN4(n3603), .IN5(
n3556), .Q(n3698) );
AOI221X1 U3145 ( .IN1(n3567), .IN2(n3689), .IN3(n3560), .IN4(n3699), .IN5(
n3700), .QN(n3687) );
AO22X1 U3146 ( .IN1(n3562), .IN2(n3679), .IN3(n3565), .IN4(n3663), .Q(n3700)
);
AO22X1 U3147 ( .IN1(n3665), .IN2(n157), .IN3(n3629), .IN4(n631), .Q(n3663)
);
MUX21X1 U3148 ( .IN1(n3549), .IN2(n1331), .S(n3701), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N43 ) );
OA221X1 U3149 ( .IN1(\fpu_add_frac_dp/n546 ), .IN2(n1311), .IN3(n3702),
.IN4(n3579), .IN5(n3703), .Q(n3701) );
OA221X1 U3150 ( .IN1(n3601), .IN2(n3697), .IN3(n3692), .IN4(n3603), .IN5(
n3556), .Q(n3703) );
AOI221X1 U3151 ( .IN1(n3567), .IN2(n3694), .IN3(n3560), .IN4(n3704), .IN5(
n3705), .QN(n3692) );
AO22X1 U3152 ( .IN1(n3562), .IN2(n3684), .IN3(n3565), .IN4(n3674), .Q(n3705)
);
AO22X1 U3153 ( .IN1(n3665), .IN2(n4), .IN3(n3629), .IN4(n96), .Q(n3674) );
MUX21X1 U3154 ( .IN1(n3549), .IN2(n1332), .S(n3706), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N42 ) );
OA221X1 U3155 ( .IN1(\fpu_add_frac_dp/n544 ), .IN2(n1312), .IN3(n3707),
.IN4(n3579), .IN5(n3708), .Q(n3706) );
OA221X1 U3156 ( .IN1(n3601), .IN2(n3702), .IN3(n3697), .IN4(n3603), .IN5(
n3556), .Q(n3708) );
AOI221X1 U3157 ( .IN1(n3567), .IN2(n3699), .IN3(n3560), .IN4(n3709), .IN5(
n3710), .QN(n3697) );
AO22X1 U3158 ( .IN1(n3562), .IN2(n3689), .IN3(n3565), .IN4(n3679), .Q(n3710)
);
AO222X1 U3159 ( .IN1(n3629), .IN2(n217), .IN3(n3711), .IN4(n15), .IN5(n3665),
.IN6(n98), .Q(n3679) );
MUX21X1 U3160 ( .IN1(n3549), .IN2(n1330), .S(n3712), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N41 ) );
OA221X1 U3161 ( .IN1(\fpu_add_frac_dp/n543 ), .IN2(n1313), .IN3(n3713),
.IN4(n3579), .IN5(n3714), .Q(n3712) );
OA221X1 U3162 ( .IN1(n3601), .IN2(n3707), .IN3(n3702), .IN4(n3603), .IN5(
n3556), .Q(n3714) );
AOI221X1 U3163 ( .IN1(n3567), .IN2(n3704), .IN3(n3560), .IN4(n3715), .IN5(
n3716), .QN(n3702) );
AO22X1 U3164 ( .IN1(n3562), .IN2(n3694), .IN3(n3565), .IN4(n3684), .Q(n3716)
);
AO222X1 U3165 ( .IN1(n3629), .IN2(n280), .IN3(n3711), .IN4(n16), .IN5(n3665),
.IN6(n97), .Q(n3684) );
MUX21X1 U3166 ( .IN1(n3549), .IN2(n1331), .S(n3717), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N40 ) );
OA221X1 U3167 ( .IN1(\fpu_add_frac_dp/n542 ), .IN2(n1314), .IN3(n3718),
.IN4(n3579), .IN5(n3719), .Q(n3717) );
OA221X1 U3168 ( .IN1(n3601), .IN2(n3713), .IN3(n3707), .IN4(n3603), .IN5(
n3556), .Q(n3719) );
AOI221X1 U3169 ( .IN1(n3565), .IN2(n3689), .IN3(n3562), .IN4(n3699), .IN5(
n3720), .QN(n3707) );
AO22X1 U3170 ( .IN1(n3560), .IN2(n3721), .IN3(n3567), .IN4(n3709), .Q(n3720)
);
AO222X1 U3171 ( .IN1(n3629), .IN2(n281), .IN3(n3711), .IN4(n3), .IN5(n3665),
.IN6(n613), .Q(n3689) );
MUX21X1 U3172 ( .IN1(n3549), .IN2(n1332), .S(n3722), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N4 ) );
OA221X1 U3173 ( .IN1(\fpu_add_frac_dp/n503 ), .IN2(n1311), .IN3(n3723),
.IN4(n3555), .IN5(n3724), .Q(n3722) );
OA21X1 U3174 ( .IN1(n3667), .IN2(n3552), .IN3(n3556), .Q(n3724) );
AOI221X1 U3175 ( .IN1(n3560), .IN2(n3725), .IN3(n3567), .IN4(n3615), .IN5(
n3726), .QN(n3667) );
AO22X1 U3176 ( .IN1(n3565), .IN2(n3568), .IN3(n3562), .IN4(n3561), .Q(n3726)
);
MUX21X1 U3177 ( .IN1(n3549), .IN2(n1330), .S(n3727), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N39 ) );
OA221X1 U3178 ( .IN1(\fpu_add_frac_dp/n541 ), .IN2(n1312), .IN3(n3728),
.IN4(n3579), .IN5(n3729), .Q(n3727) );
OA221X1 U3179 ( .IN1(n3601), .IN2(n3718), .IN3(n3713), .IN4(n3603), .IN5(
n3556), .Q(n3729) );
AOI221X1 U3180 ( .IN1(n3565), .IN2(n3694), .IN3(n3562), .IN4(n3704), .IN5(
n3730), .QN(n3713) );
AO22X1 U3181 ( .IN1(n3560), .IN2(n3731), .IN3(n3567), .IN4(n3715), .Q(n3730)
);
AO222X1 U3182 ( .IN1(n3629), .IN2(n638), .IN3(n3711), .IN4(n156), .IN5(n3665), .IN6(n95), .Q(n3694) );
MUX21X1 U3183 ( .IN1(n3549), .IN2(n1331), .S(n3732), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N38 ) );
OA221X1 U3184 ( .IN1(\fpu_add_frac_dp/n540 ), .IN2(n1313), .IN3(n3733),
.IN4(n3579), .IN5(n3734), .Q(n3732) );
OA221X1 U3185 ( .IN1(n3601), .IN2(n3728), .IN3(n3718), .IN4(n3603), .IN5(
n3556), .Q(n3734) );
AOI221X1 U3186 ( .IN1(n3565), .IN2(n3699), .IN3(n3562), .IN4(n3709), .IN5(
n3735), .QN(n3718) );
AO22X1 U3187 ( .IN1(n3560), .IN2(n3736), .IN3(n3567), .IN4(n3721), .Q(n3735)
);
AO222X1 U3188 ( .IN1(n3629), .IN2(n174), .IN3(n3711), .IN4(n68), .IN5(n3665),
.IN6(n632), .Q(n3699) );
MUX21X1 U3189 ( .IN1(n3549), .IN2(n1332), .S(n3737), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N37 ) );
OA221X1 U3190 ( .IN1(\fpu_add_frac_dp/n539 ), .IN2(n1314), .IN3(n3738),
.IN4(n3579), .IN5(n3739), .Q(n3737) );
OA221X1 U3191 ( .IN1(n3601), .IN2(n3733), .IN3(n3728), .IN4(n3603), .IN5(
n3556), .Q(n3739) );
AOI221X1 U3192 ( .IN1(n3565), .IN2(n3704), .IN3(n3562), .IN4(n3715), .IN5(
n3740), .QN(n3728) );
AO22X1 U3193 ( .IN1(n3560), .IN2(n3741), .IN3(n3567), .IN4(n3731), .Q(n3740)
);
AO222X1 U3194 ( .IN1(n3629), .IN2(n70), .IN3(n3711), .IN4(n1857), .IN5(n3665), .IN6(n630), .Q(n3704) );
MUX21X1 U3195 ( .IN1(n3549), .IN2(n1330), .S(n3742), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N36 ) );
OA221X1 U3196 ( .IN1(\fpu_add_frac_dp/n538 ), .IN2(n1311), .IN3(n3743),
.IN4(n3579), .IN5(n3744), .Q(n3742) );
OA221X1 U3197 ( .IN1(n3601), .IN2(n3738), .IN3(n3733), .IN4(n3603), .IN5(
n3556), .Q(n3744) );
AOI221X1 U3198 ( .IN1(n3565), .IN2(n3709), .IN3(n3562), .IN4(n3721), .IN5(
n3745), .QN(n3733) );
AO22X1 U3199 ( .IN1(n3560), .IN2(n1952), .IN3(n3567), .IN4(n3736), .Q(n3745)
);
AO222X1 U3200 ( .IN1(n3629), .IN2(\fpu_add_frac_dp/n2380 ), .IN3(n3711),
.IN4(n157), .IN5(n3665), .IN6(n631), .Q(n3709) );
MUX21X1 U3201 ( .IN1(n3549), .IN2(n1331), .S(n3746), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N35 ) );
OA221X1 U3202 ( .IN1(\fpu_add_frac_dp/n537 ), .IN2(n1312), .IN3(n3738),
.IN4(n3603), .IN5(n3747), .Q(n3746) );
OA221X1 U3203 ( .IN1(n3748), .IN2(n3579), .IN3(n3601), .IN4(n3743), .IN5(
n3556), .Q(n3747) );
OA21X1 U3204 ( .IN1(n3582), .IN2(\fpu_add_frac_dp/n5641 ), .IN3(n3584), .Q(
n3601) );
OR2X1 U3205 ( .IN1(n3582), .IN2(n641), .Q(n3579) );
NAND2X0 U3206 ( .IN1(n3749), .IN2(n3750), .QN(n3582) );
AO21X1 U3207 ( .IN1(n3751), .IN2(n1313), .IN3(n3752), .Q(n3750) );
AO22X1 U3208 ( .IN1(n3753), .IN2(n553), .IN3(n3754), .IN4(n1022), .Q(n3751)
);
AOI221X1 U3209 ( .IN1(n3565), .IN2(n3715), .IN3(n3562), .IN4(n3731), .IN5(
n3755), .QN(n3738) );
AO22X1 U3210 ( .IN1(n3560), .IN2(n1950), .IN3(n3567), .IN4(n3741), .Q(n3755)
);
AO222X1 U3211 ( .IN1(n3629), .IN2(n168), .IN3(n3711), .IN4(n4), .IN5(n3665),
.IN6(n96), .Q(n3715) );
AND2X1 U3212 ( .IN1(n3756), .IN2(n1063), .Q(n3665) );
AND2X1 U3213 ( .IN1(n3757), .IN2(n580), .Q(n3711) );
AND2X1 U3214 ( .IN1(n3756), .IN2(n580), .Q(n3629) );
MUX21X1 U3215 ( .IN1(n3549), .IN2(n1332), .S(n3758), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N34 ) );
OA221X1 U3216 ( .IN1(\fpu_add_frac_dp/n536 ), .IN2(n1313), .IN3(n3759),
.IN4(n3555), .IN5(n3760), .Q(n3758) );
OA221X1 U3217 ( .IN1(n3748), .IN2(n3761), .IN3(n3743), .IN4(n3603), .IN5(
n3556), .Q(n3760) );
AOI221X1 U3218 ( .IN1(n3567), .IN2(n1952), .IN3(n3560), .IN4(n1951), .IN5(
n3762), .QN(n3743) );
AO22X1 U3219 ( .IN1(n3562), .IN2(n3736), .IN3(n3565), .IN4(n3721), .Q(n3762)
);
AO222X1 U3220 ( .IN1(n3763), .IN2(n217), .IN3(n3764), .IN4(n15), .IN5(n3765),
.IN6(n580), .Q(n3721) );
MUX21X1 U3221 ( .IN1(n3549), .IN2(n1330), .S(n3766), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N33 ) );
OA221X1 U3222 ( .IN1(\fpu_add_frac_dp/n535 ), .IN2(n1314), .IN3(n1954),
.IN4(n3555), .IN5(n3767), .Q(n3766) );
OA221X1 U3223 ( .IN1(n3759), .IN2(n3761), .IN3(n3748), .IN4(n3603), .IN5(
n3556), .Q(n3767) );
INVX0 U3224 ( .INP(n1948), .ZN(n3748) );
AO221X1 U3225 ( .IN1(n3567), .IN2(n1950), .IN3(n3560), .IN4(n1949), .IN5(
n3768), .Q(n1948) );
AO22X1 U3226 ( .IN1(n3562), .IN2(n3741), .IN3(n3565), .IN4(n3731), .Q(n3768)
);
AO222X1 U3227 ( .IN1(n3763), .IN2(n280), .IN3(n3764), .IN4(n16), .IN5(n3769),
.IN6(n580), .Q(n3731) );
MUX21X1 U3228 ( .IN1(n3549), .IN2(n1331), .S(n3770), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N32 ) );
OA221X1 U3229 ( .IN1(\fpu_add_frac_dp/n534 ), .IN2(n1311), .IN3(n3771),
.IN4(n3555), .IN5(n3772), .Q(n3770) );
OA221X1 U3230 ( .IN1(n1954), .IN2(n3761), .IN3(n3759), .IN4(n3603), .IN5(
n3556), .Q(n3772) );
INVX0 U3231 ( .INP(n1945), .ZN(n3759) );
AO221X1 U3232 ( .IN1(n3567), .IN2(n1951), .IN3(n3560), .IN4(n1963), .IN5(
n3773), .Q(n1945) );
AO22X1 U3233 ( .IN1(n3562), .IN2(n1952), .IN3(n3565), .IN4(n3736), .Q(n3773)
);
AO222X1 U3234 ( .IN1(n3763), .IN2(n281), .IN3(n3764), .IN4(n3), .IN5(n3774),
.IN6(n580), .Q(n3736) );
MUX21X1 U3235 ( .IN1(n3549), .IN2(n1332), .S(n3775), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N31 ) );
OA221X1 U3236 ( .IN1(\fpu_add_frac_dp/n533 ), .IN2(n1312), .IN3(n3776),
.IN4(n3555), .IN5(n3777), .Q(n3775) );
OA221X1 U3237 ( .IN1(n3761), .IN2(n3771), .IN3(n1954), .IN4(n3603), .IN5(
n3556), .Q(n3777) );
AOI221X1 U3238 ( .IN1(n3567), .IN2(n1949), .IN3(n3560), .IN4(n1964), .IN5(
n3778), .QN(n1954) );
AO22X1 U3239 ( .IN1(n3562), .IN2(n1950), .IN3(n3565), .IN4(n3741), .Q(n3778)
);
AO222X1 U3240 ( .IN1(n3763), .IN2(n638), .IN3(n3764), .IN4(n156), .IN5(n3779), .IN6(n580), .Q(n3741) );
MUX21X1 U3241 ( .IN1(n3549), .IN2(n1330), .S(n3780), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N30 ) );
OA221X1 U3242 ( .IN1(\fpu_add_frac_dp/n532 ), .IN2(n1313), .IN3(n3781),
.IN4(n3555), .IN5(n3782), .Q(n3780) );
OA221X1 U3243 ( .IN1(n3761), .IN2(n3776), .IN3(n3771), .IN4(n3603), .IN5(
n3556), .Q(n3782) );
AOI221X1 U3244 ( .IN1(n3567), .IN2(n1963), .IN3(n3560), .IN4(n1972), .IN5(
n3783), .QN(n3771) );
AO22X1 U3245 ( .IN1(n3562), .IN2(n1951), .IN3(n3565), .IN4(n1952), .Q(n3783)
);
AO222X1 U3246 ( .IN1(n3763), .IN2(n174), .IN3(n3764), .IN4(n68), .IN5(n1946),
.IN6(n580), .Q(n1952) );
MUX21X1 U3247 ( .IN1(n3549), .IN2(n1331), .S(n3784), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N3 ) );
OA221X1 U3248 ( .IN1(\fpu_add_frac_dp/n509 ), .IN2(n1314), .IN3(n3723),
.IN4(n3552), .IN5(n3785), .Q(n3784) );
OA21X1 U3249 ( .IN1(n3786), .IN2(n3555), .IN3(n3556), .Q(n3785) );
AOI221X1 U3250 ( .IN1(n3561), .IN2(n3565), .IN3(n3615), .IN4(n3562), .IN5(
n3787), .QN(n3786) );
AO22X1 U3251 ( .IN1(n3788), .IN2(n3560), .IN3(n3725), .IN4(n3567), .Q(n3787)
);
AO22X1 U3252 ( .IN1(\fpu_add_frac_dp/n2397 ), .IN2(n1976), .IN3(n1960),
.IN4(n580), .Q(n3725) );
AO222X1 U3253 ( .IN1(n3789), .IN2(n690), .IN3(n3790), .IN4(n2653), .IN5(
n3791), .IN6(\fpu_add_frac_dp/n2393 ), .Q(n1960) );
AO22X1 U3254 ( .IN1(n580), .IN2(n1959), .IN3(n1977), .IN4(
\fpu_add_frac_dp/n2397 ), .Q(n3788) );
AO222X1 U3255 ( .IN1(n3789), .IN2(n896), .IN3(n3792), .IN4(n2653), .IN5(
n3791), .IN6(n218), .Q(n1959) );
AO22X1 U3256 ( .IN1(\fpu_add_frac_dp/n2397 ), .IN2(n2027), .IN3(n1957),
.IN4(n580), .Q(n3615) );
AO222X1 U3257 ( .IN1(n3789), .IN2(n660), .IN3(n3793), .IN4(n2653), .IN5(
n3791), .IN6(n6), .Q(n1957) );
AO22X1 U3258 ( .IN1(\fpu_add_frac_dp/n2397 ), .IN2(n1989), .IN3(n1958),
.IN4(n580), .Q(n3561) );
AO222X1 U3259 ( .IN1(n3789), .IN2(n655), .IN3(n3794), .IN4(n2653), .IN5(
n3791), .IN6(n23), .Q(n1958) );
AOI221X1 U3260 ( .IN1(n3560), .IN2(n3795), .IN3(n3567), .IN4(n3669), .IN5(
n3796), .QN(n3723) );
AO22X1 U3261 ( .IN1(n3565), .IN2(n3573), .IN3(n3562), .IN4(n3576), .Q(n3796)
);
AO22X1 U3262 ( .IN1(\fpu_add_frac_dp/n2397 ), .IN2(n2026), .IN3(n1966),
.IN4(n580), .Q(n3576) );
AO222X1 U3263 ( .IN1(n3789), .IN2(n898), .IN3(n3797), .IN4(n2653), .IN5(
n3791), .IN6(n162), .Q(n1966) );
AO22X1 U3264 ( .IN1(\fpu_add_frac_dp/n2397 ), .IN2(n1990), .IN3(n1967),
.IN4(n580), .Q(n3669) );
AO222X1 U3265 ( .IN1(n3789), .IN2(n899), .IN3(n3798), .IN4(n2653), .IN5(
n3791), .IN6(n205), .Q(n1967) );
AO22X1 U3266 ( .IN1(\fpu_add_frac_dp/n2397 ), .IN2(n1996), .IN3(n1965),
.IN4(n580), .Q(n3795) );
AO222X1 U3267 ( .IN1(n3789), .IN2(n902), .IN3(n3799), .IN4(n2653), .IN5(
n3791), .IN6(n278), .Q(n1965) );
MUX21X1 U3268 ( .IN1(n3549), .IN2(n1332), .S(n3800), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N29 ) );
OA221X1 U3269 ( .IN1(\fpu_add_frac_dp/n531 ), .IN2(n1311), .IN3(n3801),
.IN4(n3555), .IN5(n3802), .Q(n3800) );
OA221X1 U3270 ( .IN1(n3761), .IN2(n3781), .IN3(n3776), .IN4(n3603), .IN5(
n3556), .Q(n3802) );
AOI221X1 U3271 ( .IN1(n3567), .IN2(n1964), .IN3(n3560), .IN4(n1973), .IN5(
n3803), .QN(n3776) );
AO22X1 U3272 ( .IN1(n3562), .IN2(n1949), .IN3(n3565), .IN4(n1950), .Q(n3803)
);
AO222X1 U3273 ( .IN1(n3763), .IN2(n70), .IN3(n3764), .IN4(n1857), .IN5(n3804), .IN6(n580), .Q(n1950) );
MUX21X1 U3274 ( .IN1(n3549), .IN2(n1330), .S(n3805), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N28 ) );
OA221X1 U3275 ( .IN1(\fpu_add_frac_dp/n530 ), .IN2(n1312), .IN3(n3806),
.IN4(n3555), .IN5(n3807), .Q(n3805) );
OA221X1 U3276 ( .IN1(n3761), .IN2(n3801), .IN3(n3781), .IN4(n3603), .IN5(
n3556), .Q(n3807) );
AOI221X1 U3277 ( .IN1(n3567), .IN2(n1972), .IN3(n3560), .IN4(n3808), .IN5(
n3809), .QN(n3781) );
AO22X1 U3278 ( .IN1(n3562), .IN2(n1963), .IN3(n3565), .IN4(n1951), .Q(n3809)
);
AO222X1 U3279 ( .IN1(n3763), .IN2(\fpu_add_frac_dp/n2380 ), .IN3(n3764),
.IN4(n157), .IN5(n3810), .IN6(n580), .Q(n1951) );
MUX21X1 U3280 ( .IN1(n3549), .IN2(n1331), .S(n3811), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N27 ) );
OA221X1 U3281 ( .IN1(\fpu_add_frac_dp/n529 ), .IN2(n1313), .IN3(n3812),
.IN4(n3555), .IN5(n3813), .Q(n3811) );
OA221X1 U3282 ( .IN1(n3761), .IN2(n3806), .IN3(n3801), .IN4(n3603), .IN5(
n3556), .Q(n3813) );
AOI221X1 U3283 ( .IN1(n3567), .IN2(n1973), .IN3(n3560), .IN4(n1971), .IN5(
n3814), .QN(n3801) );
AO22X1 U3284 ( .IN1(n3562), .IN2(n1964), .IN3(n3565), .IN4(n1949), .Q(n3814)
);
AO222X1 U3285 ( .IN1(n3763), .IN2(n168), .IN3(n3764), .IN4(n4), .IN5(n3815),
.IN6(n580), .Q(n1949) );
AND2X1 U3286 ( .IN1(n3757), .IN2(\fpu_add_frac_dp/n2399 ), .Q(n3764) );
NOR2X0 U3287 ( .IN1(\fpu_add_frac_dp/n570 ), .IN2(\fpu_add_frac_dp/n577 ),
.QN(n3757) );
AND2X1 U3288 ( .IN1(n3756), .IN2(\fpu_add_frac_dp/n2399 ), .Q(n3763) );
NOR2X0 U3289 ( .IN1(\fpu_add_frac_dp/n2382 ), .IN2(\fpu_add_frac_dp/n570 ),
.QN(n3756) );
MUX21X1 U3290 ( .IN1(n3549), .IN2(n1332), .S(n3816), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N26 ) );
OA221X1 U3291 ( .IN1(\fpu_add_frac_dp/n527 ), .IN2(n1314), .IN3(n3817),
.IN4(n3555), .IN5(n3818), .Q(n3816) );
OA221X1 U3292 ( .IN1(n3761), .IN2(n3812), .IN3(n3806), .IN4(n3603), .IN5(
n3556), .Q(n3818) );
AOI221X1 U3293 ( .IN1(n3567), .IN2(n3808), .IN3(n3560), .IN4(n1969), .IN5(
n3819), .QN(n3806) );
AO22X1 U3294 ( .IN1(n3562), .IN2(n1972), .IN3(n3565), .IN4(n1963), .Q(n3819)
);
AO22X1 U3295 ( .IN1(n1982), .IN2(n580), .IN3(\fpu_add_frac_dp/n2399 ), .IN4(
n3765), .Q(n1963) );
AO22X1 U3296 ( .IN1(n3820), .IN2(n98), .IN3(n3821), .IN4(n271), .Q(n3765) );
MUX21X1 U3297 ( .IN1(n3549), .IN2(n1329), .S(n3822), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N25 ) );
OA221X1 U3298 ( .IN1(\fpu_add_frac_dp/n526 ), .IN2(n1311), .IN3(n3823),
.IN4(n3555), .IN5(n3824), .Q(n3822) );
OA221X1 U3299 ( .IN1(n3761), .IN2(n3817), .IN3(n3812), .IN4(n3603), .IN5(
n3556), .Q(n3824) );
AOI221X1 U3300 ( .IN1(n3567), .IN2(n1971), .IN3(n3560), .IN4(n1968), .IN5(
n3825), .QN(n3812) );
AO22X1 U3301 ( .IN1(n3562), .IN2(n1973), .IN3(n3565), .IN4(n1964), .Q(n3825)
);
AO22X1 U3302 ( .IN1(n1981), .IN2(n580), .IN3(\fpu_add_frac_dp/n2399 ), .IN4(
n3769), .Q(n1964) );
AO22X1 U3303 ( .IN1(n3820), .IN2(n97), .IN3(n3821), .IN4(n23), .Q(n3769) );
MUX21X1 U3304 ( .IN1(n3549), .IN2(n1329), .S(n3826), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N24 ) );
OA221X1 U3305 ( .IN1(\fpu_add_frac_dp/n525 ), .IN2(n1312), .IN3(n3827),
.IN4(n3555), .IN5(n3828), .Q(n3826) );
OA221X1 U3306 ( .IN1(n3761), .IN2(n3823), .IN3(n3817), .IN4(n3603), .IN5(
n3556), .Q(n3828) );
AOI221X1 U3307 ( .IN1(n3567), .IN2(n1969), .IN3(n3560), .IN4(n3829), .IN5(
n3830), .QN(n3817) );
AO22X1 U3308 ( .IN1(n3562), .IN2(n3808), .IN3(n3565), .IN4(n1972), .Q(n3830)
);
AO22X1 U3309 ( .IN1(n1983), .IN2(n580), .IN3(\fpu_add_frac_dp/n2399 ), .IN4(
n3774), .Q(n1972) );
AO22X1 U3310 ( .IN1(n3820), .IN2(n613), .IN3(n3821), .IN4(n162), .Q(n3774)
);
MUX21X1 U3311 ( .IN1(n3549), .IN2(n1329), .S(n3831), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N23 ) );
OA221X1 U3312 ( .IN1(\fpu_add_frac_dp/n524 ), .IN2(n1313), .IN3(n3832),
.IN4(n3555), .IN5(n3833), .Q(n3831) );
OA221X1 U3313 ( .IN1(n3761), .IN2(n3827), .IN3(n3823), .IN4(n3603), .IN5(
n3556), .Q(n3833) );
AOI221X1 U3314 ( .IN1(n3567), .IN2(n1968), .IN3(n3560), .IN4(n3834), .IN5(
n3835), .QN(n3823) );
AO22X1 U3315 ( .IN1(n3562), .IN2(n1971), .IN3(n3565), .IN4(n1973), .Q(n3835)
);
AO22X1 U3316 ( .IN1(n1985), .IN2(n580), .IN3(\fpu_add_frac_dp/n2399 ), .IN4(
n3779), .Q(n1973) );
AO22X1 U3317 ( .IN1(n3820), .IN2(n95), .IN3(n3821), .IN4(n6), .Q(n3779) );
MUX21X1 U3318 ( .IN1(n3549), .IN2(n1329), .S(n3836), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N22 ) );
OA221X1 U3319 ( .IN1(\fpu_add_frac_dp/n523 ), .IN2(n1314), .IN3(n3837),
.IN4(n3555), .IN5(n3838), .Q(n3836) );
OA221X1 U3320 ( .IN1(n3761), .IN2(n3832), .IN3(n3827), .IN4(n3603), .IN5(
n3556), .Q(n3838) );
AOI221X1 U3321 ( .IN1(n3567), .IN2(n3829), .IN3(n3560), .IN4(n3839), .IN5(
n3840), .QN(n3827) );
AO22X1 U3322 ( .IN1(n3562), .IN2(n1969), .IN3(n3565), .IN4(n3808), .Q(n3840)
);
AO22X1 U3323 ( .IN1(n1986), .IN2(n580), .IN3(\fpu_add_frac_dp/n2399 ), .IN4(
n1946), .Q(n3808) );
AO22X1 U3324 ( .IN1(n3820), .IN2(n632), .IN3(n3821), .IN4(n205), .Q(n1946)
);
MUX21X1 U3325 ( .IN1(n3549), .IN2(n1329), .S(n3841), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N21 ) );
OA221X1 U3326 ( .IN1(\fpu_add_frac_dp/n522 ), .IN2(n1311), .IN3(n3842),
.IN4(n3555), .IN5(n3843), .Q(n3841) );
OA221X1 U3327 ( .IN1(n3761), .IN2(n3837), .IN3(n3832), .IN4(n3603), .IN5(
n3556), .Q(n3843) );
AOI221X1 U3328 ( .IN1(n3567), .IN2(n3834), .IN3(n3560), .IN4(n3844), .IN5(
n3845), .QN(n3832) );
AO22X1 U3329 ( .IN1(n3562), .IN2(n1968), .IN3(n3565), .IN4(n1971), .Q(n3845)
);
AO22X1 U3330 ( .IN1(n1979), .IN2(n580), .IN3(\fpu_add_frac_dp/n2399 ), .IN4(
n3804), .Q(n1971) );
AO22X1 U3331 ( .IN1(n3820), .IN2(n630), .IN3(n3821), .IN4(
\fpu_add_frac_dp/n2393 ), .Q(n3804) );
MUX21X1 U3332 ( .IN1(n3549), .IN2(n1329), .S(n3846), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N20 ) );
OA221X1 U3333 ( .IN1(\fpu_add_frac_dp/n521 ), .IN2(n1312), .IN3(n3847),
.IN4(n3555), .IN5(n3848), .Q(n3846) );
OA221X1 U3334 ( .IN1(n3761), .IN2(n3842), .IN3(n3837), .IN4(n3603), .IN5(
n3556), .Q(n3848) );
AOI221X1 U3335 ( .IN1(n3567), .IN2(n3839), .IN3(n3560), .IN4(n3849), .IN5(
n3850), .QN(n3837) );
AO22X1 U3336 ( .IN1(n3562), .IN2(n3829), .IN3(n3565), .IN4(n1969), .Q(n3850)
);
AO22X1 U3337 ( .IN1(n1978), .IN2(n580), .IN3(\fpu_add_frac_dp/n2399 ), .IN4(
n3810), .Q(n1969) );
AO22X1 U3338 ( .IN1(n3820), .IN2(n631), .IN3(n3821), .IN4(n278), .Q(n3810)
);
MUX21X1 U3339 ( .IN1(n3549), .IN2(n1329), .S(n3851), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N19 ) );
OA221X1 U3340 ( .IN1(\fpu_add_frac_dp/n520 ), .IN2(n1313), .IN3(n3852),
.IN4(n3555), .IN5(n3853), .Q(n3851) );
OA221X1 U3341 ( .IN1(n3761), .IN2(n3847), .IN3(n3842), .IN4(n3603), .IN5(
n3556), .Q(n3853) );
AOI221X1 U3342 ( .IN1(n3567), .IN2(n3844), .IN3(n3560), .IN4(n3854), .IN5(
n3855), .QN(n3842) );
AO22X1 U3343 ( .IN1(n3562), .IN2(n3834), .IN3(n3565), .IN4(n1968), .Q(n3855)
);
AO22X1 U3344 ( .IN1(n1980), .IN2(n580), .IN3(\fpu_add_frac_dp/n2399 ), .IN4(
n3815), .Q(n1968) );
AO22X1 U3345 ( .IN1(n3820), .IN2(n96), .IN3(n3821), .IN4(n218), .Q(n3815) );
MUX21X1 U3346 ( .IN1(n3549), .IN2(n1329), .S(n3856), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N18 ) );
OA221X1 U3347 ( .IN1(\fpu_add_frac_dp/n519 ), .IN2(n1314), .IN3(n3857),
.IN4(n3555), .IN5(n3858), .Q(n3856) );
OA221X1 U3348 ( .IN1(n3761), .IN2(n3852), .IN3(n3847), .IN4(n3603), .IN5(
n3556), .Q(n3858) );
AOI221X1 U3349 ( .IN1(n3567), .IN2(n3849), .IN3(n3560), .IN4(n3859), .IN5(
n3860), .QN(n3847) );
AO22X1 U3350 ( .IN1(n3562), .IN2(n3839), .IN3(n3565), .IN4(n3829), .Q(n3860)
);
AO22X1 U3351 ( .IN1(n1991), .IN2(n580), .IN3(n1982), .IN4(n581), .Q(n3829)
);
AO222X1 U3352 ( .IN1(n3821), .IN2(n696), .IN3(n3861), .IN4(n15), .IN5(n3820),
.IN6(n217), .Q(n1982) );
MUX21X1 U3353 ( .IN1(n3549), .IN2(n1329), .S(n3862), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N17 ) );
OA221X1 U3354 ( .IN1(\fpu_add_frac_dp/n518 ), .IN2(n1311), .IN3(n3863),
.IN4(n3555), .IN5(n3864), .Q(n3862) );
OA221X1 U3355 ( .IN1(n3761), .IN2(n3857), .IN3(n3852), .IN4(n3603), .IN5(
n3556), .Q(n3864) );
AOI221X1 U3356 ( .IN1(n3567), .IN2(n3854), .IN3(n3560), .IN4(n3865), .IN5(
n3866), .QN(n3852) );
AO22X1 U3357 ( .IN1(n3562), .IN2(n3844), .IN3(n3565), .IN4(n3834), .Q(n3866)
);
AO22X1 U3358 ( .IN1(n1993), .IN2(n580), .IN3(n1981), .IN4(n581), .Q(n3834)
);
AO222X1 U3359 ( .IN1(n3821), .IN2(n678), .IN3(n3861), .IN4(n16), .IN5(n3820),
.IN6(n280), .Q(n1981) );
MUX21X1 U3360 ( .IN1(n3549), .IN2(n1329), .S(n3867), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N16 ) );
OA221X1 U3361 ( .IN1(\fpu_add_frac_dp/n517 ), .IN2(n1312), .IN3(n3868),
.IN4(n3555), .IN5(n3869), .Q(n3867) );
OA221X1 U3362 ( .IN1(n3761), .IN2(n3863), .IN3(n3857), .IN4(n3603), .IN5(
n3556), .Q(n3869) );
AOI221X1 U3363 ( .IN1(n3567), .IN2(n3859), .IN3(n3560), .IN4(n3870), .IN5(
n3871), .QN(n3857) );
AO22X1 U3364 ( .IN1(n3562), .IN2(n3849), .IN3(n3565), .IN4(n3839), .Q(n3871)
);
AO22X1 U3365 ( .IN1(n1997), .IN2(n580), .IN3(n1983), .IN4(n581), .Q(n3839)
);
AO222X1 U3366 ( .IN1(n3821), .IN2(n679), .IN3(n3861), .IN4(n3), .IN5(n3820),
.IN6(n281), .Q(n1983) );
MUX21X1 U3367 ( .IN1(n3549), .IN2(n1329), .S(n3872), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N15 ) );
OA221X1 U3368 ( .IN1(\fpu_add_frac_dp/n516 ), .IN2(n1313), .IN3(n3873),
.IN4(n3555), .IN5(n3874), .Q(n3872) );
OA221X1 U3369 ( .IN1(n3761), .IN2(n3868), .IN3(n3863), .IN4(n3603), .IN5(
n3556), .Q(n3874) );
AOI221X1 U3370 ( .IN1(n3567), .IN2(n3865), .IN3(n3560), .IN4(n3875), .IN5(
n3876), .QN(n3863) );
AO22X1 U3371 ( .IN1(n3562), .IN2(n3854), .IN3(n3565), .IN4(n3844), .Q(n3876)
);
AO22X1 U3372 ( .IN1(n1992), .IN2(n580), .IN3(n1985), .IN4(n581), .Q(n3844)
);
AO222X1 U3373 ( .IN1(n3821), .IN2(n106), .IN3(n3861), .IN4(n156), .IN5(n3820), .IN6(n638), .Q(n1985) );
NOR2X0 U3374 ( .IN1(\fpu_add_frac_dp/n2382 ), .IN2(\fpu_add_frac_dp/n573 ),
.QN(n3861) );
NOR2X0 U3375 ( .IN1(\fpu_add_frac_dp/n2382 ), .IN2(\fpu_add_frac_dp/n545 ),
.QN(n3821) );
MUX21X1 U3376 ( .IN1(n3549), .IN2(n1329), .S(n3877), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N14 ) );
OA221X1 U3377 ( .IN1(\fpu_add_frac_dp/n514 ), .IN2(n1314), .IN3(n3878),
.IN4(n3555), .IN5(n3879), .Q(n3877) );
OA221X1 U3378 ( .IN1(n3761), .IN2(n3873), .IN3(n3868), .IN4(n3603), .IN5(
n3556), .Q(n3879) );
AOI221X1 U3379 ( .IN1(n3567), .IN2(n3870), .IN3(n3560), .IN4(n3880), .IN5(
n3881), .QN(n3868) );
AO22X1 U3380 ( .IN1(n3562), .IN2(n3859), .IN3(n3565), .IN4(n3849), .Q(n3881)
);
AO22X1 U3381 ( .IN1(n3882), .IN2(n580), .IN3(n1986), .IN4(n581), .Q(n3849)
);
AO22X1 U3382 ( .IN1(n3883), .IN2(n3884), .IN3(n3820), .IN4(n174), .Q(n1986)
);
INVX0 U3383 ( .INP(n3885), .ZN(n3883) );
MUX21X1 U3384 ( .IN1(n3549), .IN2(n1329), .S(n3886), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N13 ) );
OA221X1 U3385 ( .IN1(\fpu_add_frac_dp/n512 ), .IN2(n1311), .IN3(n3887),
.IN4(n3555), .IN5(n3888), .Q(n3886) );
OA221X1 U3386 ( .IN1(n3761), .IN2(n3878), .IN3(n3873), .IN4(n3603), .IN5(
n3556), .Q(n3888) );
AOI221X1 U3387 ( .IN1(n3560), .IN2(n3566), .IN3(n3567), .IN4(n3875), .IN5(
n3889), .QN(n3873) );
AO22X1 U3388 ( .IN1(n3562), .IN2(n3865), .IN3(n3565), .IN4(n3854), .Q(n3889)
);
AO22X1 U3389 ( .IN1(n3890), .IN2(n580), .IN3(n1979), .IN4(n581), .Q(n3854)
);
AO22X1 U3390 ( .IN1(n3891), .IN2(n3884), .IN3(n3820), .IN4(n70), .Q(n1979)
);
MUX21X1 U3391 ( .IN1(n3549), .IN2(n1329), .S(n3892), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N12 ) );
OA221X1 U3392 ( .IN1(\fpu_add_frac_dp/n511 ), .IN2(n1312), .IN3(n3893),
.IN4(n3555), .IN5(n3894), .Q(n3892) );
OA221X1 U3393 ( .IN1(n3761), .IN2(n3887), .IN3(n3878), .IN4(n3603), .IN5(
n3556), .Q(n3894) );
AOI221X1 U3394 ( .IN1(n3560), .IN2(n3575), .IN3(n3567), .IN4(n3880), .IN5(
n3895), .QN(n3878) );
AO22X1 U3395 ( .IN1(n3562), .IN2(n3870), .IN3(n3565), .IN4(n3859), .Q(n3895)
);
AO22X1 U3396 ( .IN1(n3896), .IN2(n580), .IN3(n1978), .IN4(n581), .Q(n3859)
);
AO22X1 U3397 ( .IN1(n3897), .IN2(n3884), .IN3(n3820), .IN4(
\fpu_add_frac_dp/n2380 ), .Q(n1978) );
MUX21X1 U3398 ( .IN1(n3549), .IN2(n1329), .S(n3898), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N11 ) );
OA221X1 U3399 ( .IN1(\fpu_add_frac_dp/n502 ), .IN2(n1313), .IN3(n3899),
.IN4(n3555), .IN5(n3900), .Q(n3898) );
OA221X1 U3400 ( .IN1(n3887), .IN2(n3603), .IN3(n3761), .IN4(n3893), .IN5(
n3556), .Q(n3900) );
AOI221X1 U3401 ( .IN1(n3562), .IN2(n3880), .IN3(n3560), .IN4(n3572), .IN5(
n3901), .QN(n3893) );
AO22X1 U3402 ( .IN1(n3567), .IN2(n3575), .IN3(n3565), .IN4(n3870), .Q(n3901)
);
AND2X1 U3403 ( .IN1(n3552), .IN2(n3584), .Q(n3761) );
NAND2X0 U3404 ( .IN1(n3902), .IN2(\fpu_add_frac_dp/n2385 ), .QN(n3584) );
NAND2X0 U3405 ( .IN1(n3902), .IN2(n166), .QN(n3603) );
INVX0 U3406 ( .INP(n3588), .ZN(n3902) );
AOI221X1 U3407 ( .IN1(n3565), .IN2(n3865), .IN3(n3560), .IN4(n3563), .IN5(
n3903), .QN(n3887) );
AO22X1 U3408 ( .IN1(n3562), .IN2(n3875), .IN3(n3567), .IN4(n3566), .Q(n3903)
);
AO22X1 U3409 ( .IN1(n3904), .IN2(n580), .IN3(n1980), .IN4(n581), .Q(n3865)
);
AO22X1 U3410 ( .IN1(n3905), .IN2(n3884), .IN3(n3820), .IN4(n168), .Q(n1980)
);
NOR2X0 U3411 ( .IN1(\fpu_add_frac_dp/n570 ), .IN2(\fpu_add_frac_dp/n576 ),
.QN(n3820) );
MUX21X1 U3412 ( .IN1(n3549), .IN2(n1329), .S(n3906), .Q(
\fpu_add_frac_dp/i_a3stg_frac2/N10 ) );
OA221X1 U3413 ( .IN1(\fpu_add_frac_dp/n501 ), .IN2(n1314), .IN3(n3551),
.IN4(n3555), .IN5(n3907), .Q(n3906) );
OA221X1 U3414 ( .IN1(n3908), .IN2(n3588), .IN3(n3899), .IN4(n3552), .IN5(
n3556), .Q(n3907) );
NAND3X0 U3415 ( .IN1(n3909), .IN2(n1311), .IN3(\fpu_add_ctl/n329 ), .QN(
n3556) );
INVX0 U3416 ( .INP(n3749), .ZN(n3909) );
NAND3X0 U3417 ( .IN1(n3749), .IN2(n166), .IN3(n3752), .QN(n3552) );
AOI221X1 U3418 ( .IN1(n3567), .IN2(n3563), .IN3(n3560), .IN4(n3568), .IN5(
n3910), .QN(n3899) );
AO22X1 U3419 ( .IN1(n3565), .IN2(n3875), .IN3(n3562), .IN4(n3566), .Q(n3910)
);
AO22X1 U3420 ( .IN1(\fpu_add_frac_dp/n2397 ), .IN2(n3904), .IN3(n1977),
.IN4(n580), .Q(n3568) );
AO222X1 U3421 ( .IN1(n3789), .IN2(n659), .IN3(n3905), .IN4(n2653), .IN5(
n3791), .IN6(n168), .Q(n1977) );
AO22X1 U3422 ( .IN1(\fpu_add_frac_dp/n2397 ), .IN2(n3890), .IN3(n1976),
.IN4(n580), .Q(n3563) );
AO222X1 U3423 ( .IN1(n3789), .IN2(n161), .IN3(n3891), .IN4(n2653), .IN5(
n3791), .IN6(n70), .Q(n1976) );
NAND2X0 U3424 ( .IN1(n1311), .IN2(n356), .QN(n3588) );
NOR4X0 U3425 ( .IN1(n3911), .IN2(n3912), .IN3(n2029), .IN4(n2041), .QN(n3908) );
NAND4X0 U3426 ( .IN1(n3913), .IN2(n3914), .IN3(n3915), .IN4(n2004), .QN(
n2041) );
OA21X1 U3427 ( .IN1(\fpu_add_frac_dp/n579 ), .IN2(n3916), .IN3(n3917), .Q(
n3915) );
NOR4X0 U3428 ( .IN1(n23), .IN2(n3918), .IN3(n162), .IN4(n6), .QN(n3916) );
NAND2X0 U3429 ( .IN1(\fpu_add_frac_dp/n2497 ), .IN2(\fpu_add_frac_dp/n2424 ),
.QN(n3918) );
AO221X1 U3430 ( .IN1(\fpu_add_frac_dp/n2306 ), .IN2(n3905), .IN3(n168),
.IN4(n2638), .IN5(n659), .Q(n2029) );
AO22X1 U3431 ( .IN1(n118), .IN2(n929), .IN3(n4), .IN4(n47), .Q(n3905) );
AO21X1 U3432 ( .IN1(n2008), .IN2(n2638), .IN3(n2033), .Q(n3912) );
NAND4X0 U3433 ( .IN1(n2038), .IN2(n2015), .IN3(n2005), .IN4(n3919), .QN(
n2033) );
NOR3X0 U3434 ( .IN1(n2020), .IN2(n3920), .IN3(n2014), .QN(n3919) );
MUX21X1 U3435 ( .IN1(n3921), .IN2(n3922), .S(\fpu_add_frac_dp/n2306 ), .Q(
n2014) );
NAND3X0 U3436 ( .IN1(n3923), .IN2(n2040), .IN3(n2039), .QN(n3922) );
NAND4X0 U3437 ( .IN1(n3914), .IN2(\fpu_add_frac_dp/n771 ), .IN3(n2004),
.IN4(n3924), .QN(n3921) );
NAND2X0 U3438 ( .IN1(n205), .IN2(n2638), .QN(n3924) );
OA21X1 U3439 ( .IN1(\fpu_add_frac_dp/n741 ), .IN2(\fpu_add_frac_dp/n579 ),
.IN3(\fpu_add_frac_dp/n773 ), .Q(n2004) );
INVX0 U3440 ( .INP(n2043), .ZN(n3914) );
AO21X1 U3441 ( .IN1(\fpu_add_frac_dp/n2393 ), .IN2(n2638), .IN3(n690), .Q(
n2043) );
OA21X1 U3442 ( .IN1(n3925), .IN2(n3926), .IN3(n2019), .Q(n3920) );
NAND3X0 U3443 ( .IN1(n3927), .IN2(n624), .IN3(\fpu_add_frac_dp/n769 ), .QN(
n2019) );
NAND2X0 U3444 ( .IN1(n2638), .IN2(n162), .QN(n3927) );
INVX0 U3445 ( .INP(n2022), .ZN(n3925) );
NOR2X0 U3446 ( .IN1(n3797), .IN2(n624), .QN(n2022) );
AO221X1 U3447 ( .IN1(\fpu_add_frac_dp/n2306 ), .IN2(n3793), .IN3(n2638),
.IN4(n6), .IN5(n660), .Q(n2020) );
INVX0 U3448 ( .INP(n2012), .ZN(n2005) );
NAND3X0 U3449 ( .IN1(n3928), .IN2(n3917), .IN3(\fpu_add_frac_dp/n774 ), .QN(
n2012) );
NAND2X0 U3450 ( .IN1(n218), .IN2(n2638), .QN(n3917) );
NAND2X0 U3451 ( .IN1(\fpu_add_frac_dp/n2306 ), .IN2(n3792), .QN(n3928) );
AOI221X1 U3452 ( .IN1(\fpu_add_frac_dp/n2306 ), .IN2(n3794), .IN3(n2638),
.IN4(n23), .IN5(n655), .QN(n2015) );
OA21X1 U3453 ( .IN1(\fpu_add_frac_dp/n579 ), .IN2(\fpu_add_frac_dp/n736 ),
.IN3(\fpu_add_frac_dp/n767 ), .Q(n2038) );
NAND4X0 U3454 ( .IN1(n3929), .IN2(n3930), .IN3(n3931), .IN4(n3932), .QN(
n2008) );
NOR4X0 U3455 ( .IN1(n3933), .IN2(n627), .IN3(n75), .IN4(n161), .QN(n3932) );
NAND4X0 U3456 ( .IN1(\fpu_add_frac_dp/n773 ), .IN2(\fpu_add_frac_dp/n772 ),
.IN3(\fpu_add_frac_dp/n767 ), .IN4(n3934), .QN(n3933) );
NAND2X0 U3457 ( .IN1(\fpu_add_frac_dp/n2306 ), .IN2(n3935), .QN(n3934) );
OR3X1 U3458 ( .IN1(n70), .IN2(\fpu_add_frac_dp/n2380 ), .IN3(n174), .Q(n3935) );
NOR4X0 U3459 ( .IN1(n3936), .IN2(n312), .IN3(n106), .IN4(n720), .QN(n3931)
);
NAND4X0 U3460 ( .IN1(\fpu_add_frac_dp/n745 ), .IN2(\fpu_add_frac_dp/n744 ),
.IN3(\fpu_add_frac_dp/n743 ), .IN4(n3913), .QN(n3936) );
AND4X1 U3461 ( .IN1(\fpu_add_frac_dp/n771 ), .IN2(\fpu_add_frac_dp/n769 ),
.IN3(\fpu_add_frac_dp/n766 ), .IN4(n3937), .Q(n3913) );
AND3X1 U3462 ( .IN1(\fpu_add_frac_dp/n768 ), .IN2(\fpu_add_frac_dp/n774 ),
.IN3(\fpu_add_frac_dp/n770 ), .Q(n3937) );
NOR4X0 U3463 ( .IN1(n3938), .IN2(n717), .IN3(n131), .IN4(n314), .QN(n3930)
);
NAND4X0 U3464 ( .IN1(\fpu_add_frac_dp/n752 ), .IN2(\fpu_add_frac_dp/n751 ),
.IN3(\fpu_add_frac_dp/n750 ), .IN4(\fpu_add_frac_dp/n749 ), .QN(n3938)
);
NOR4X0 U3465 ( .IN1(n3939), .IN2(n150), .IN3(n425), .IN4(n721), .QN(n3929)
);
NAND4X0 U3466 ( .IN1(\fpu_add_frac_dp/n759 ), .IN2(\fpu_add_frac_dp/n758 ),
.IN3(\fpu_add_frac_dp/n757 ), .IN4(\fpu_add_frac_dp/n756 ), .QN(n3939)
);
AO221X1 U3467 ( .IN1(n3940), .IN2(n2021), .IN3(n3941), .IN4(n755), .IN5(
n3942), .Q(n3911) );
AO22X1 U3468 ( .IN1(\fpu_add_frac_dp/n2306 ), .IN2(n2042), .IN3(n3943),
.IN4(n693), .Q(n3942) );
NAND4X0 U3469 ( .IN1(n1998), .IN2(n3944), .IN3(n2024), .IN4(n3945), .QN(
n3943) );
OA221X1 U3470 ( .IN1(\fpu_add_frac_dp/n2308 ), .IN2(n3946), .IN3(
\fpu_add_frac_dp/n580 ), .IN4(n3947), .IN5(n3948), .Q(n3945) );
OA22X1 U3471 ( .IN1(n3949), .IN2(n2016), .IN3(n3950), .IN4(n2006), .Q(n3948)
);
INVX0 U3472 ( .INP(n2021), .ZN(n2006) );
INVX0 U3473 ( .INP(n1944), .ZN(n3947) );
NAND3X0 U3474 ( .IN1(n3949), .IN2(n3946), .IN3(n3950), .QN(n1944) );
INVX0 U3475 ( .INP(n3896), .ZN(n3950) );
INVX0 U3476 ( .INP(n3882), .ZN(n3949) );
INVX0 U3477 ( .INP(n3890), .ZN(n3946) );
AO22X1 U3478 ( .IN1(n3951), .IN2(\fpu_add_frac_dp/n2393 ), .IN3(n3790),
.IN4(n3884), .Q(n3890) );
INVX0 U3479 ( .INP(n2039), .ZN(n3790) );
OA22X1 U3480 ( .IN1(\fpu_add_frac_dp/n756 ), .IN2(\fpu_add_frac_dp/n528 ),
.IN3(\fpu_add_frac_dp/n572 ), .IN4(\fpu_add_frac_dp/n2395 ), .Q(n2039)
);
INVX0 U3481 ( .INP(n1989), .ZN(n3944) );
NOR4X0 U3482 ( .IN1(n3952), .IN2(n2026), .IN3(n2027), .IN4(n3904), .QN(n1998) );
AO22X1 U3483 ( .IN1(n3951), .IN2(n218), .IN3(n3792), .IN4(n3884), .Q(n3904)
);
AO22X1 U3484 ( .IN1(n20), .IN2(n930), .IN3(n96), .IN4(n5), .Q(n3792) );
NAND4X0 U3485 ( .IN1(n3953), .IN2(n3954), .IN3(n3955), .IN4(n3956), .QN(
n2042) );
NOR4X0 U3486 ( .IN1(n75), .IN2(n161), .IN3(n627), .IN4(n3957), .QN(n3956) );
NAND3X0 U3487 ( .IN1(n3958), .IN2(n2024), .IN3(n3959), .QN(n3941) );
AOI222X1 U3488 ( .IN1(n2021), .IN2(n3880), .IN3(n3870), .IN4(n2028), .IN5(
n255), .IN6(n3875), .QN(n3959) );
AO22X1 U3489 ( .IN1(n1989), .IN2(n580), .IN3(n1993), .IN4(n581), .Q(n3875)
);
AO22X1 U3490 ( .IN1(n3951), .IN2(n23), .IN3(n3794), .IN4(n3884), .Q(n1993)
);
AO22X1 U3491 ( .IN1(n20), .IN2(n934), .IN3(n97), .IN4(n5), .Q(n3794) );
AO222X1 U3492 ( .IN1(n3960), .IN2(n3884), .IN3(n3961), .IN4(n16), .IN5(n3951), .IN6(n678), .Q(n1989) );
INVX0 U3493 ( .INP(n3953), .ZN(n3960) );
OA22X1 U3494 ( .IN1(\fpu_add_frac_dp/n760 ), .IN2(\fpu_add_frac_dp/n528 ),
.IN3(\fpu_add_frac_dp/n572 ), .IN4(\fpu_add_frac_dp/n2517 ), .Q(n3953)
);
INVX0 U3495 ( .INP(n2016), .ZN(n2028) );
AO22X1 U3496 ( .IN1(n3952), .IN2(n580), .IN3(n1991), .IN4(n581), .Q(n3870)
);
AO22X1 U3497 ( .IN1(n3951), .IN2(n271), .IN3(n3926), .IN4(n3884), .Q(n1991)
);
AND3X1 U3498 ( .IN1(n2031), .IN2(n3962), .IN3(n2030), .Q(n2024) );
INVX0 U3499 ( .INP(n3566), .ZN(n3958) );
AO22X1 U3500 ( .IN1(n1992), .IN2(n581), .IN3(n2027), .IN4(n580), .Q(n3566)
);
AO222X1 U3501 ( .IN1(n3963), .IN2(n3884), .IN3(n3961), .IN4(n156), .IN5(
n3951), .IN6(n106), .Q(n2027) );
INVX0 U3502 ( .INP(n3954), .ZN(n3963) );
OA22X1 U3503 ( .IN1(\fpu_add_frac_dp/n762 ), .IN2(\fpu_add_frac_dp/n528 ),
.IN3(\fpu_add_frac_dp/n572 ), .IN4(\fpu_add_frac_dp/n2515 ), .Q(n3954)
);
AO22X1 U3504 ( .IN1(n3951), .IN2(n6), .IN3(n3793), .IN4(n3884), .Q(n1992) );
AO22X1 U3505 ( .IN1(n314), .IN2(n20), .IN3(n5), .IN4(n95), .Q(n3793) );
NAND2X0 U3506 ( .IN1(\fpu_add_frac_dp/n2448 ), .IN2(\fpu_add_frac_dp/n2308 ),
.QN(n2021) );
OAI221X1 U3507 ( .IN1(n2016), .IN2(n3962), .IN3(n2030), .IN4(
\fpu_add_frac_dp/n2308 ), .IN5(n2031), .QN(n3940) );
AOI221X1 U3508 ( .IN1(\fpu_add_frac_dp/n2380 ), .IN2(n2638), .IN3(
\fpu_add_frac_dp/n2306 ), .IN4(n3897), .IN5(n75), .QN(n2031) );
AOI221X1 U3509 ( .IN1(n2638), .IN2(n70), .IN3(\fpu_add_frac_dp/n2306 ),
.IN4(n3891), .IN5(n161), .QN(n2030) );
AO22X1 U3510 ( .IN1(n118), .IN2(n312), .IN3(n1857), .IN4(n47), .Q(n3891) );
INVX0 U3511 ( .INP(\fpu_add_frac_dp/n2281 ), .ZN(n1857) );
INVX0 U3512 ( .INP(\fpu_add_frac_dp/n579 ), .ZN(n2638) );
OA221X1 U3513 ( .IN1(n624), .IN2(n3885), .IN3(\fpu_add_frac_dp/n2480 ),
.IN4(\fpu_add_frac_dp/n579 ), .IN5(\fpu_add_frac_dp/n763 ), .Q(n3962)
);
NAND2X0 U3514 ( .IN1(n962), .IN2(n255), .QN(n2016) );
NAND3X0 U3515 ( .IN1(n3749), .IN2(n3752), .IN3(\fpu_add_frac_dp/n2385 ),
.QN(n3555) );
AND2X1 U3516 ( .IN1(n3964), .IN2(n1314), .Q(n3752) );
AO22X1 U3517 ( .IN1(n3753), .IN2(n1076), .IN3(n3754), .IN4(n569), .Q(n3964)
);
XOR2X1 U3518 ( .IN1(n694), .IN2(n3965), .Q(n3749) );
OA22X1 U3519 ( .IN1(n3966), .IN2(n316), .IN3(n629), .IN4(n3967), .Q(n3965)
);
NOR2X0 U3520 ( .IN1(n3968), .IN2(\fpu_add_exp_dp/n111 ), .QN(n3966) );
AOI221X1 U3521 ( .IN1(n3567), .IN2(n3572), .IN3(n3560), .IN4(n3573), .IN5(
n3969), .QN(n3551) );
AO22X1 U3522 ( .IN1(n3565), .IN2(n3880), .IN3(n3562), .IN4(n3575), .Q(n3969)
);
AO22X1 U3523 ( .IN1(n3882), .IN2(n581), .IN3(n1990), .IN4(n580), .Q(n3575)
);
OAI22X1 U3524 ( .IN1(\fpu_add_frac_dp/n575 ), .IN2(n3885), .IN3(
\fpu_add_frac_dp/n2382 ), .IN4(n3970), .QN(n1990) );
OA22X1 U3525 ( .IN1(\fpu_add_frac_dp/n572 ), .IN2(\fpu_add_frac_dp/n2480 ),
.IN3(\fpu_add_frac_dp/n763 ), .IN4(\fpu_add_frac_dp/n528 ), .Q(n3970)
);
OA22X1 U3526 ( .IN1(\fpu_add_frac_dp/n747 ), .IN2(\fpu_add_frac_dp/n545 ),
.IN3(\fpu_add_frac_dp/n573 ), .IN4(\fpu_add_frac_dp/n2269 ), .Q(n3885)
);
AO22X1 U3527 ( .IN1(n3951), .IN2(n205), .IN3(n3798), .IN4(n3884), .Q(n3882)
);
INVX0 U3528 ( .INP(n3923), .ZN(n3798) );
OA22X1 U3529 ( .IN1(\fpu_add_frac_dp/n528 ), .IN2(\fpu_add_frac_dp/n755 ),
.IN3(\fpu_add_frac_dp/n2341 ), .IN4(\fpu_add_frac_dp/n572 ), .Q(n3923)
);
NOR2X0 U3530 ( .IN1(n311), .IN2(\fpu_add_frac_dp/n583 ), .QN(n3562) );
AO22X1 U3531 ( .IN1(n1997), .IN2(n581), .IN3(n2026), .IN4(n580), .Q(n3880)
);
AO222X1 U3532 ( .IN1(n3971), .IN2(n3884), .IN3(n3961), .IN4(n3), .IN5(n3951),
.IN6(n679), .Q(n2026) );
INVX0 U3533 ( .INP(n3955), .ZN(n3971) );
OA22X1 U3534 ( .IN1(\fpu_add_frac_dp/n761 ), .IN2(\fpu_add_frac_dp/n528 ),
.IN3(\fpu_add_frac_dp/n572 ), .IN4(\fpu_add_frac_dp/n2516 ), .Q(n3955)
);
AO22X1 U3535 ( .IN1(n3951), .IN2(n162), .IN3(n3797), .IN4(n3884), .Q(n1997)
);
AO22X1 U3536 ( .IN1(n20), .IN2(n131), .IN3(n613), .IN4(n5), .Q(n3797) );
NOR2X0 U3537 ( .IN1(\fpu_add_frac_dp/n583 ), .IN2(\fpu_add_frac_dp/n584 ),
.QN(n3565) );
AO22X1 U3538 ( .IN1(\fpu_add_frac_dp/n2397 ), .IN2(n3952), .IN3(n1995),
.IN4(n580), .Q(n3573) );
AO222X1 U3539 ( .IN1(n3789), .IN2(n901), .IN3(n3926), .IN4(n2653), .IN5(
n3791), .IN6(n271), .Q(n1995) );
AO22X1 U3540 ( .IN1(n20), .IN2(n931), .IN3(n98), .IN4(n5), .Q(n3926) );
AO222X1 U3541 ( .IN1(n3951), .IN2(n696), .IN3(n3961), .IN4(n15), .IN5(n3957),
.IN6(n3884), .Q(n3952) );
AO22X1 U3542 ( .IN1(n20), .IN2(n935), .IN3(n217), .IN4(n5), .Q(n3957) );
NOR2X0 U3543 ( .IN1(\fpu_add_frac_dp/n573 ), .IN2(\fpu_add_frac_dp/n575 ),
.QN(n3961) );
NOR2X0 U3544 ( .IN1(n653), .IN2(n311), .QN(n3560) );
AO22X1 U3545 ( .IN1(\fpu_add_frac_dp/n2397 ), .IN2(n3896), .IN3(n1996),
.IN4(n580), .Q(n3572) );
AO222X1 U3546 ( .IN1(n3789), .IN2(n75), .IN3(n3897), .IN4(n2653), .IN5(n3791), .IN6(\fpu_add_frac_dp/n2380 ), .Q(n1996) );
NOR2X0 U3547 ( .IN1(\fpu_add_frac_dp/n2382 ), .IN2(\fpu_add_frac_dp/n571 ),
.QN(n3791) );
INVX0 U3548 ( .INP(\fpu_add_frac_dp/n574 ), .ZN(n2653) );
AO22X1 U3549 ( .IN1(n118), .IN2(n932), .IN3(n157), .IN4(n47), .Q(n3897) );
NOR2X0 U3550 ( .IN1(\fpu_add_frac_dp/n2382 ), .IN2(\fpu_add_frac_dp/n513 ),
.QN(n3789) );
AO22X1 U3551 ( .IN1(n3951), .IN2(n278), .IN3(n3799), .IN4(n3884), .Q(n3896)
);
INVX0 U3552 ( .INP(\fpu_add_frac_dp/n2382 ), .ZN(n3884) );
INVX0 U3553 ( .INP(n2040), .ZN(n3799) );
OA22X1 U3554 ( .IN1(\fpu_add_frac_dp/n757 ), .IN2(\fpu_add_frac_dp/n528 ),
.IN3(\fpu_add_frac_dp/n572 ), .IN4(\fpu_add_frac_dp/n2426 ), .Q(n2040)
);
NOR2X0 U3555 ( .IN1(\fpu_add_frac_dp/n545 ), .IN2(\fpu_add_frac_dp/n575 ),
.QN(n3951) );
NOR2X0 U3556 ( .IN1(n653), .IN2(\fpu_add_frac_dp/n584 ), .QN(n3567) );
NAND2X0 U3557 ( .IN1(\fpu_add_ctl/n313 ), .IN2(n1449), .QN(n1933) );
INVX0 U3558 ( .INP(n1745), .ZN(n1746) );
NAND2X0 U3559 ( .IN1(n3972), .IN2(n1311), .QN(n1745) );
AO21X1 U3560 ( .IN1(n754), .IN2(n3972), .IN3(n1389), .Q(n3549) );
NAND2X0 U3561 ( .IN1(n3973), .IN2(n3972), .QN(n2046) );
NAND2X0 U3562 ( .IN1(fadd_clken_l), .IN2(n3972), .QN(
\fpu_add_frac_dp/ckbuf_add_frac_dp/N1 ) );
INVX0 U3563 ( .INP(se_add_frac), .ZN(n3972) );
XOR3X1 U3564 ( .IN1(\fpu_add_frac_dp/n735 ), .IN2(\fpu_add_frac_dp/n598 ),
.IN3(n139), .Q(\fpu_add_frac_dp/a3stg_fracadd[0] ) );
AO21X1 U3565 ( .IN1(n1455), .IN2(n1033), .IN3(n3974), .Q(
\fpu_add_exp_dp/n722 ) );
AO21X1 U3566 ( .IN1(n1451), .IN2(n1066), .IN3(n3975), .Q(
\fpu_add_exp_dp/n721 ) );
AO21X1 U3567 ( .IN1(n1451), .IN2(n1223), .IN3(n3976), .Q(
\fpu_add_exp_dp/n720 ) );
AO21X1 U3568 ( .IN1(n1451), .IN2(n60), .IN3(n3977), .Q(\fpu_add_exp_dp/n719 ) );
AO21X1 U3569 ( .IN1(n1451), .IN2(n152), .IN3(n3978), .Q(
\fpu_add_exp_dp/n718 ) );
AO21X1 U3570 ( .IN1(n1451), .IN2(n1161), .IN3(n3979), .Q(
\fpu_add_exp_dp/n717 ) );
AO21X1 U3571 ( .IN1(n1451), .IN2(n1162), .IN3(n3980), .Q(
\fpu_add_exp_dp/n716 ) );
AO21X1 U3572 ( .IN1(n1451), .IN2(n1172), .IN3(n3981), .Q(
\fpu_add_exp_dp/n715 ) );
AO21X1 U3573 ( .IN1(n1451), .IN2(n1182), .IN3(n3982), .Q(
\fpu_add_exp_dp/n714 ) );
AO21X1 U3574 ( .IN1(n1452), .IN2(n1183), .IN3(n3983), .Q(
\fpu_add_exp_dp/n713 ) );
AO21X1 U3575 ( .IN1(n1451), .IN2(n1156), .IN3(n3984), .Q(
\fpu_add_exp_dp/n712 ) );
AO21X1 U3576 ( .IN1(n1452), .IN2(n509), .IN3(n3974), .Q(
\fpu_add_exp_dp/n711 ) );
AO21X1 U3577 ( .IN1(n1451), .IN2(n507), .IN3(n3975), .Q(
\fpu_add_exp_dp/n710 ) );
AO21X1 U3578 ( .IN1(n1452), .IN2(n508), .IN3(n3976), .Q(
\fpu_add_exp_dp/n709 ) );
AO21X1 U3579 ( .IN1(n1452), .IN2(n672), .IN3(n3977), .Q(
\fpu_add_exp_dp/n708 ) );
AO21X1 U3580 ( .IN1(n1452), .IN2(n674), .IN3(n3978), .Q(
\fpu_add_exp_dp/n707 ) );
AO21X1 U3581 ( .IN1(n1452), .IN2(n675), .IN3(n3979), .Q(
\fpu_add_exp_dp/n706 ) );
AO21X1 U3582 ( .IN1(n1452), .IN2(n668), .IN3(n3980), .Q(
\fpu_add_exp_dp/n705 ) );
AO21X1 U3583 ( .IN1(n1452), .IN2(n669), .IN3(n3981), .Q(
\fpu_add_exp_dp/n704 ) );
AO21X1 U3584 ( .IN1(n1452), .IN2(n658), .IN3(n3982), .Q(
\fpu_add_exp_dp/n703 ) );
AO21X1 U3585 ( .IN1(n1452), .IN2(n656), .IN3(n3983), .Q(
\fpu_add_exp_dp/n702 ) );
AO21X1 U3586 ( .IN1(n1452), .IN2(n657), .IN3(n3984), .Q(
\fpu_add_exp_dp/n701 ) );
AO22X1 U3587 ( .IN1(n1460), .IN2(n990), .IN3(n3985), .IN4(inq_in2[52]), .Q(
\fpu_add_exp_dp/n700 ) );
AO22X1 U3588 ( .IN1(n1460), .IN2(n991), .IN3(n3985), .IN4(inq_in2[53]), .Q(
\fpu_add_exp_dp/n699 ) );
AO22X1 U3589 ( .IN1(n1460), .IN2(n1005), .IN3(n3985), .IN4(inq_in2[54]), .Q(
\fpu_add_exp_dp/n698 ) );
AO22X1 U3590 ( .IN1(n1460), .IN2(n109), .IN3(n3985), .IN4(inq_in2[55]), .Q(
\fpu_add_exp_dp/n697 ) );
AO22X1 U3591 ( .IN1(n1460), .IN2(n110), .IN3(n3985), .IN4(inq_in2[56]), .Q(
\fpu_add_exp_dp/n696 ) );
AO22X1 U3592 ( .IN1(n1460), .IN2(n49), .IN3(n3985), .IN4(inq_in2[57]), .Q(
\fpu_add_exp_dp/n695 ) );
AO22X1 U3593 ( .IN1(n1460), .IN2(n42), .IN3(n3985), .IN4(inq_in2[58]), .Q(
\fpu_add_exp_dp/n694 ) );
AO22X1 U3594 ( .IN1(n1459), .IN2(n41), .IN3(n3985), .IN4(inq_in2[59]), .Q(
\fpu_add_exp_dp/n693 ) );
AO22X1 U3595 ( .IN1(n1460), .IN2(n126), .IN3(n3985), .IN4(inq_in2[60]), .Q(
\fpu_add_exp_dp/n692 ) );
AO22X1 U3596 ( .IN1(n1460), .IN2(n127), .IN3(n3985), .IN4(inq_in2[61]), .Q(
\fpu_add_exp_dp/n691 ) );
AO22X1 U3597 ( .IN1(n1460), .IN2(n105), .IN3(n3985), .IN4(inq_in2[62]), .Q(
\fpu_add_exp_dp/n690 ) );
OAI22X1 U3598 ( .IN1(n3986), .IN2(\fpu_add_exp_dp/n222 ), .IN3(n3987), .IN4(
n3988), .QN(\fpu_add_exp_dp/n689 ) );
OAI22X1 U3599 ( .IN1(n3986), .IN2(\fpu_add_exp_dp/n221 ), .IN3(n3987), .IN4(
n3989), .QN(\fpu_add_exp_dp/n688 ) );
OAI22X1 U3600 ( .IN1(n3986), .IN2(\fpu_add_exp_dp/n220 ), .IN3(n3987), .IN4(
n3990), .QN(\fpu_add_exp_dp/n687 ) );
OAI22X1 U3601 ( .IN1(n3986), .IN2(\fpu_add_exp_dp/n219 ), .IN3(n3987), .IN4(
n3991), .QN(\fpu_add_exp_dp/n686 ) );
OAI22X1 U3602 ( .IN1(n3986), .IN2(\fpu_add_exp_dp/n218 ), .IN3(n3987), .IN4(
n3992), .QN(\fpu_add_exp_dp/n685 ) );
OAI22X1 U3603 ( .IN1(n3986), .IN2(\fpu_add_exp_dp/n217 ), .IN3(n3987), .IN4(
n3993), .QN(\fpu_add_exp_dp/n684 ) );
OAI22X1 U3604 ( .IN1(n3986), .IN2(\fpu_add_exp_dp/n216 ), .IN3(n3987), .IN4(
n3994), .QN(\fpu_add_exp_dp/n683 ) );
OAI22X1 U3605 ( .IN1(n3986), .IN2(\fpu_add_exp_dp/n215 ), .IN3(n3987), .IN4(
n3995), .QN(\fpu_add_exp_dp/n682 ) );
AO22X1 U3606 ( .IN1(n1459), .IN2(n1180), .IN3(n3985), .IN4(inq_in2[60]), .Q(
\fpu_add_exp_dp/n681 ) );
AO22X1 U3607 ( .IN1(n1460), .IN2(n1075), .IN3(n3985), .IN4(inq_in2[61]), .Q(
\fpu_add_exp_dp/n680 ) );
AO22X1 U3608 ( .IN1(n1459), .IN2(n1181), .IN3(n3985), .IN4(inq_in2[62]), .Q(
\fpu_add_exp_dp/n679 ) );
AO21X1 U3609 ( .IN1(n1452), .IN2(n1159), .IN3(n3996), .Q(
\fpu_add_exp_dp/n678 ) );
AO21X1 U3610 ( .IN1(n1452), .IN2(n1169), .IN3(n3996), .Q(
\fpu_add_exp_dp/n677 ) );
AO21X1 U3611 ( .IN1(n1453), .IN2(n1160), .IN3(n3996), .Q(
\fpu_add_exp_dp/n676 ) );
AO21X1 U3612 ( .IN1(n1453), .IN2(n958), .IN3(n3996), .Q(
\fpu_add_exp_dp/n675 ) );
AO21X1 U3613 ( .IN1(n1453), .IN2(n959), .IN3(n3996), .Q(
\fpu_add_exp_dp/n674 ) );
AO21X1 U3614 ( .IN1(n1453), .IN2(n960), .IN3(n3996), .Q(
\fpu_add_exp_dp/n673 ) );
AO21X1 U3615 ( .IN1(n1453), .IN2(n937), .IN3(n3996), .Q(
\fpu_add_exp_dp/n672 ) );
AO21X1 U3616 ( .IN1(n1453), .IN2(n936), .IN3(n3996), .Q(
\fpu_add_exp_dp/n671 ) );
AO21X1 U3617 ( .IN1(n1453), .IN2(n510), .IN3(n3996), .Q(
\fpu_add_exp_dp/n670 ) );
AO21X1 U3618 ( .IN1(n1453), .IN2(n61), .IN3(n3996), .Q(\fpu_add_exp_dp/n669 ) );
AO21X1 U3619 ( .IN1(n1453), .IN2(n1174), .IN3(n3996), .Q(
\fpu_add_exp_dp/n668 ) );
AO21X1 U3620 ( .IN1(n1453), .IN2(n1175), .IN3(n3996), .Q(
\fpu_add_exp_dp/n667 ) );
AO21X1 U3621 ( .IN1(n1454), .IN2(n1176), .IN3(n3996), .Q(
\fpu_add_exp_dp/n666 ) );
AO21X1 U3622 ( .IN1(n1453), .IN2(n1170), .IN3(n3996), .Q(
\fpu_add_exp_dp/n665 ) );
AO21X1 U3623 ( .IN1(n1453), .IN2(n1177), .IN3(n3996), .Q(
\fpu_add_exp_dp/n664 ) );
AO21X1 U3624 ( .IN1(n1454), .IN2(n1178), .IN3(n3996), .Q(
\fpu_add_exp_dp/n663 ) );
AND2X1 U3625 ( .IN1(inq_op[0]), .IN2(n3985), .Q(n3996) );
AO21X1 U3626 ( .IN1(n1453), .IN2(n1164), .IN3(n3997), .Q(
\fpu_add_exp_dp/n662 ) );
AO21X1 U3627 ( .IN1(n1454), .IN2(n1154), .IN3(n3997), .Q(
\fpu_add_exp_dp/n661 ) );
AO21X1 U3628 ( .IN1(n1454), .IN2(n1165), .IN3(n3997), .Q(
\fpu_add_exp_dp/n660 ) );
AO21X1 U3629 ( .IN1(n1454), .IN2(n514), .IN3(n3997), .Q(
\fpu_add_exp_dp/n659 ) );
AO21X1 U3630 ( .IN1(n1454), .IN2(n515), .IN3(n3997), .Q(
\fpu_add_exp_dp/n658 ) );
AO21X1 U3631 ( .IN1(n1454), .IN2(n516), .IN3(n3997), .Q(
\fpu_add_exp_dp/n657 ) );
AO21X1 U3632 ( .IN1(n1454), .IN2(n546), .IN3(n3997), .Q(
\fpu_add_exp_dp/n656 ) );
AO21X1 U3633 ( .IN1(n1454), .IN2(n545), .IN3(n3997), .Q(
\fpu_add_exp_dp/n655 ) );
AO21X1 U3634 ( .IN1(n1454), .IN2(n1147), .IN3(n3997), .Q(
\fpu_add_exp_dp/n654 ) );
AO21X1 U3635 ( .IN1(n1454), .IN2(n1150), .IN3(n3997), .Q(
\fpu_add_exp_dp/n653 ) );
AO21X1 U3636 ( .IN1(n1454), .IN2(n928), .IN3(n3997), .Q(
\fpu_add_exp_dp/n652 ) );
AO21X1 U3637 ( .IN1(n1454), .IN2(n151), .IN3(n3997), .Q(
\fpu_add_exp_dp/n651 ) );
AO21X1 U3638 ( .IN1(n1455), .IN2(n558), .IN3(n3997), .Q(
\fpu_add_exp_dp/n650 ) );
AO21X1 U3639 ( .IN1(n1455), .IN2(n1179), .IN3(n3997), .Q(
\fpu_add_exp_dp/n649 ) );
AO21X1 U3640 ( .IN1(n1455), .IN2(n1166), .IN3(n3997), .Q(
\fpu_add_exp_dp/n648 ) );
AO21X1 U3641 ( .IN1(n1455), .IN2(n1167), .IN3(n3997), .Q(
\fpu_add_exp_dp/n647 ) );
AO21X1 U3642 ( .IN1(n1455), .IN2(n1155), .IN3(n3997), .Q(
\fpu_add_exp_dp/n646 ) );
AO21X1 U3643 ( .IN1(n1455), .IN2(n1168), .IN3(n3997), .Q(
\fpu_add_exp_dp/n645 ) );
AO21X1 U3644 ( .IN1(n1455), .IN2(n1171), .IN3(n3997), .Q(
\fpu_add_exp_dp/n644 ) );
AO21X1 U3645 ( .IN1(n1455), .IN2(n1163), .IN3(n3997), .Q(
\fpu_add_exp_dp/n643 ) );
AO21X1 U3646 ( .IN1(n1455), .IN2(n559), .IN3(n3997), .Q(
\fpu_add_exp_dp/n642 ) );
AO21X1 U3647 ( .IN1(n1455), .IN2(n1148), .IN3(n3997), .Q(
\fpu_add_exp_dp/n641 ) );
AND2X1 U3648 ( .IN1(inq_op[1]), .IN2(n3985), .Q(n3997) );
AO21X1 U3649 ( .IN1(n1455), .IN2(n13), .IN3(n3998), .Q(\fpu_add_exp_dp/n640 ) );
AO21X1 U3650 ( .IN1(n1455), .IN2(n1239), .IN3(n3998), .Q(
\fpu_add_exp_dp/n639 ) );
AO21X1 U3651 ( .IN1(n1456), .IN2(n1240), .IN3(n3998), .Q(
\fpu_add_exp_dp/n638 ) );
AO21X1 U3652 ( .IN1(n1456), .IN2(n1241), .IN3(n3998), .Q(
\fpu_add_exp_dp/n637 ) );
AND2X1 U3653 ( .IN1(inq_op[7]), .IN2(n3985), .Q(n3998) );
AO21X1 U3654 ( .IN1(n1456), .IN2(n992), .IN3(n3974), .Q(
\fpu_add_exp_dp/n636 ) );
AND2X1 U3655 ( .IN1(n3985), .IN2(inq_in1[52]), .Q(n3974) );
AO21X1 U3656 ( .IN1(n1456), .IN2(n138), .IN3(n3975), .Q(
\fpu_add_exp_dp/n635 ) );
AND2X1 U3657 ( .IN1(n3985), .IN2(inq_in1[53]), .Q(n3975) );
AO21X1 U3658 ( .IN1(n1456), .IN2(n993), .IN3(n3976), .Q(
\fpu_add_exp_dp/n634 ) );
AND2X1 U3659 ( .IN1(n3985), .IN2(inq_in1[54]), .Q(n3976) );
AO21X1 U3660 ( .IN1(n1456), .IN2(n994), .IN3(n3977), .Q(
\fpu_add_exp_dp/n633 ) );
AND2X1 U3661 ( .IN1(n3985), .IN2(inq_in1[55]), .Q(n3977) );
AO21X1 U3662 ( .IN1(n1456), .IN2(n995), .IN3(n3978), .Q(
\fpu_add_exp_dp/n632 ) );
AND2X1 U3663 ( .IN1(n3985), .IN2(inq_in1[56]), .Q(n3978) );
AO21X1 U3664 ( .IN1(n1456), .IN2(n996), .IN3(n3979), .Q(
\fpu_add_exp_dp/n631 ) );
AND2X1 U3665 ( .IN1(n3985), .IN2(inq_in1[57]), .Q(n3979) );
AO21X1 U3666 ( .IN1(n1456), .IN2(n997), .IN3(n3980), .Q(
\fpu_add_exp_dp/n630 ) );
AND2X1 U3667 ( .IN1(n3985), .IN2(inq_in1[58]), .Q(n3980) );
AO21X1 U3668 ( .IN1(n1456), .IN2(n998), .IN3(n3981), .Q(
\fpu_add_exp_dp/n629 ) );
AND2X1 U3669 ( .IN1(n3985), .IN2(inq_in1[59]), .Q(n3981) );
AO21X1 U3670 ( .IN1(n1456), .IN2(n999), .IN3(n3982), .Q(
\fpu_add_exp_dp/n628 ) );
AND2X1 U3671 ( .IN1(n3985), .IN2(inq_in1[60]), .Q(n3982) );
AO21X1 U3672 ( .IN1(n1456), .IN2(n1000), .IN3(n3983), .Q(
\fpu_add_exp_dp/n627 ) );
AND2X1 U3673 ( .IN1(n3985), .IN2(inq_in1[61]), .Q(n3983) );
AO21X1 U3674 ( .IN1(n1456), .IN2(n961), .IN3(n3984), .Q(
\fpu_add_exp_dp/n626 ) );
AND2X1 U3675 ( .IN1(n3985), .IN2(inq_in1[62]), .Q(n3984) );
AO221X1 U3676 ( .IN1(n3985), .IN2(n3988), .IN3(n1451), .IN4(n491), .IN5(
n3999), .Q(\fpu_add_exp_dp/n625 ) );
INVX0 U3677 ( .INP(inq_in2[52]), .ZN(n3988) );
AO221X1 U3678 ( .IN1(n3985), .IN2(n3989), .IN3(n1451), .IN4(n56), .IN5(n3999), .Q(\fpu_add_exp_dp/n624 ) );
INVX0 U3679 ( .INP(inq_in2[53]), .ZN(n3989) );
AO221X1 U3680 ( .IN1(n3985), .IN2(n3990), .IN3(n1451), .IN4(n309), .IN5(
n3999), .Q(\fpu_add_exp_dp/n623 ) );
NOR2X0 U3681 ( .IN1(n3987), .IN2(inq_op[1]), .QN(n3999) );
INVX0 U3682 ( .INP(inq_in2[54]), .ZN(n3990) );
AO22X1 U3683 ( .IN1(n1459), .IN2(n319), .IN3(n3985), .IN4(n3991), .Q(
\fpu_add_exp_dp/n622 ) );
INVX0 U3684 ( .INP(inq_in2[55]), .ZN(n3991) );
AO22X1 U3685 ( .IN1(n1460), .IN2(n320), .IN3(n3985), .IN4(n3992), .Q(
\fpu_add_exp_dp/n621 ) );
INVX0 U3686 ( .INP(inq_in2[56]), .ZN(n3992) );
AO22X1 U3687 ( .IN1(n1459), .IN2(n321), .IN3(n3985), .IN4(n3993), .Q(
\fpu_add_exp_dp/n620 ) );
INVX0 U3688 ( .INP(inq_in2[57]), .ZN(n3993) );
AO22X1 U3689 ( .IN1(n1460), .IN2(n322), .IN3(n3985), .IN4(n3994), .Q(
\fpu_add_exp_dp/n619 ) );
INVX0 U3690 ( .INP(inq_in2[58]), .ZN(n3994) );
AO22X1 U3691 ( .IN1(n1459), .IN2(n323), .IN3(n3985), .IN4(n3995), .Q(
\fpu_add_exp_dp/n618 ) );
INVX0 U3692 ( .INP(inq_in2[59]), .ZN(n3995) );
INVX0 U3693 ( .INP(n3987), .ZN(n3985) );
OAI22X1 U3694 ( .IN1(n3986), .IN2(\fpu_add_exp_dp/n150 ), .IN3(n3987), .IN4(
inq_in2[60]), .QN(\fpu_add_exp_dp/n617 ) );
OAI22X1 U3695 ( .IN1(n3986), .IN2(\fpu_add_exp_dp/n149 ), .IN3(n3987), .IN4(
inq_in2[61]), .QN(\fpu_add_exp_dp/n616 ) );
OAI22X1 U3696 ( .IN1(n3986), .IN2(\fpu_add_exp_dp/n47 ), .IN3(n3987), .IN4(
inq_in2[62]), .QN(\fpu_add_exp_dp/n615 ) );
NAND2X0 U3697 ( .IN1(a1stg_step), .IN2(\fpu_add_ctl/n470 ), .QN(n3987) );
AO21X1 U3698 ( .IN1(n1467), .IN2(n645), .IN3(n4001), .Q(
\fpu_add_exp_dp/n614 ) );
AO21X1 U3699 ( .IN1(n1465), .IN2(n73), .IN3(n4002), .Q(\fpu_add_exp_dp/n613 ) );
AO21X1 U3700 ( .IN1(n1464), .IN2(n287), .IN3(n4003), .Q(
\fpu_add_exp_dp/n612 ) );
AO21X1 U3701 ( .IN1(n1464), .IN2(n290), .IN3(n4004), .Q(
\fpu_add_exp_dp/n611 ) );
AO21X1 U3702 ( .IN1(n1465), .IN2(n648), .IN3(n4005), .Q(
\fpu_add_exp_dp/n610 ) );
AO21X1 U3703 ( .IN1(n1464), .IN2(n646), .IN3(n4006), .Q(
\fpu_add_exp_dp/n609 ) );
AO21X1 U3704 ( .IN1(n1467), .IN2(n711), .IN3(n4007), .Q(
\fpu_add_exp_dp/n608 ) );
AO21X1 U3705 ( .IN1(n1466), .IN2(n221), .IN3(n4008), .Q(
\fpu_add_exp_dp/n607 ) );
AO21X1 U3706 ( .IN1(n1464), .IN2(n35), .IN3(n4009), .Q(\fpu_add_exp_dp/n606 ) );
AO21X1 U3707 ( .IN1(n1464), .IN2(n88), .IN3(n4010), .Q(\fpu_add_exp_dp/n605 ) );
AO21X1 U3708 ( .IN1(n1467), .IN2(n289), .IN3(n4011), .Q(
\fpu_add_exp_dp/n604 ) );
AO21X1 U3709 ( .IN1(n1464), .IN2(n725), .IN3(n4012), .Q(
\fpu_add_exp_dp/n603 ) );
AO21X1 U3710 ( .IN1(n1464), .IN2(n315), .IN3(n4001), .Q(
\fpu_add_exp_dp/n602 ) );
AO22X1 U3711 ( .IN1(n4013), .IN2(n2622), .IN3(n1339), .IN4(n4014), .Q(n4001)
);
AO221X1 U3712 ( .IN1(n4015), .IN2(n672), .IN3(n4016), .IN4(n109), .IN5(n4017), .Q(n4014) );
AO22X1 U3713 ( .IN1(n4018), .IN2(n990), .IN3(n4019), .IN4(n509), .Q(n4017)
);
AO21X1 U3714 ( .IN1(n1466), .IN2(n676), .IN3(n4002), .Q(
\fpu_add_exp_dp/n601 ) );
AO22X1 U3715 ( .IN1(n1338), .IN2(n4020), .IN3(n4013), .IN4(n4021), .Q(n4002)
);
XOR2X1 U3716 ( .IN1(n2622), .IN2(n2619), .Q(n4021) );
AO221X1 U3717 ( .IN1(n4015), .IN2(n674), .IN3(n4016), .IN4(n110), .IN5(n4022), .Q(n4020) );
AO22X1 U3718 ( .IN1(n4018), .IN2(n991), .IN3(n4019), .IN4(n507), .Q(n4022)
);
AO21X1 U3719 ( .IN1(n1467), .IN2(n687), .IN3(n4003), .Q(
\fpu_add_exp_dp/n600 ) );
AO22X1 U3720 ( .IN1(n2629), .IN2(n4013), .IN3(n1340), .IN4(n4023), .Q(n4003)
);
AO221X1 U3721 ( .IN1(n4015), .IN2(n675), .IN3(n4016), .IN4(n49), .IN5(n4024),
.Q(n4023) );
AO22X1 U3722 ( .IN1(n4018), .IN2(n1005), .IN3(n4019), .IN4(n508), .Q(n4024)
);
OA21X1 U3723 ( .IN1(n2631), .IN2(n2623), .IN3(n4025), .Q(n2629) );
AO21X1 U3724 ( .IN1(n1464), .IN2(n686), .IN3(n4004), .Q(
\fpu_add_exp_dp/n599 ) );
AO22X1 U3725 ( .IN1(n1340), .IN2(n4026), .IN3(n4027), .IN4(n4013), .Q(n4004)
);
NOR2X0 U3726 ( .IN1(n2651), .IN2(n2652), .QN(n4027) );
NOR2X0 U3727 ( .IN1(n2649), .IN2(n4028), .QN(n2652) );
AO221X1 U3728 ( .IN1(n4019), .IN2(n672), .IN3(n4018), .IN4(n109), .IN5(n4029), .Q(n4026) );
AO22X1 U3729 ( .IN1(n4016), .IN2(n42), .IN3(n4015), .IN4(n668), .Q(n4029) );
AO21X1 U3730 ( .IN1(n1466), .IN2(n685), .IN3(n4005), .Q(
\fpu_add_exp_dp/n598 ) );
AO22X1 U3731 ( .IN1(n1337), .IN2(n4030), .IN3(n4031), .IN4(n4013), .Q(n4005)
);
NOR2X0 U3732 ( .IN1(n2665), .IN2(n2666), .QN(n4031) );
NOR2X0 U3733 ( .IN1(n2662), .IN2(n2651), .QN(n2666) );
AO221X1 U3734 ( .IN1(n4019), .IN2(n674), .IN3(n4018), .IN4(n110), .IN5(n4032), .Q(n4030) );
AO22X1 U3735 ( .IN1(n4016), .IN2(n41), .IN3(n4015), .IN4(n669), .Q(n4032) );
AO21X1 U3736 ( .IN1(n1464), .IN2(n684), .IN3(n4006), .Q(
\fpu_add_exp_dp/n597 ) );
AO22X1 U3737 ( .IN1(n1339), .IN2(n4033), .IN3(n4034), .IN4(n4013), .Q(n4006)
);
NOR2X0 U3738 ( .IN1(n2729), .IN2(n2730), .QN(n4034) );
NOR2X0 U3739 ( .IN1(n2718), .IN2(n2665), .QN(n2730) );
INVX0 U3740 ( .INP(n4035), .ZN(n2665) );
INVX0 U3741 ( .INP(n4036), .ZN(n2718) );
AO221X1 U3742 ( .IN1(n4019), .IN2(n675), .IN3(n4018), .IN4(n49), .IN5(n4037),
.Q(n4033) );
AO22X1 U3743 ( .IN1(n4016), .IN2(n126), .IN3(n4015), .IN4(n658), .Q(n4037)
);
AO21X1 U3744 ( .IN1(n1466), .IN2(n661), .IN3(n4007), .Q(
\fpu_add_exp_dp/n596 ) );
AO22X1 U3745 ( .IN1(n1338), .IN2(n4038), .IN3(n4039), .IN4(n4013), .Q(n4007)
);
OA21X1 U3746 ( .IN1(n2729), .IN2(n2700), .IN3(n4040), .Q(n4039) );
AO221X1 U3747 ( .IN1(n4019), .IN2(n668), .IN3(n4018), .IN4(n42), .IN5(n4041),
.Q(n4038) );
AO22X1 U3748 ( .IN1(n4016), .IN2(n127), .IN3(n4015), .IN4(n656), .Q(n4041)
);
AO21X1 U3749 ( .IN1(n1466), .IN2(n683), .IN3(n4008), .Q(
\fpu_add_exp_dp/n595 ) );
AO22X1 U3750 ( .IN1(n1340), .IN2(n4042), .IN3(n4043), .IN4(n4013), .Q(n4008)
);
AOI21X1 U3751 ( .IN1(n4040), .IN2(n2703), .IN3(n4044), .QN(n4043) );
AO221X1 U3752 ( .IN1(n4019), .IN2(n669), .IN3(n4018), .IN4(n41), .IN5(n4045),
.Q(n4042) );
AO22X1 U3753 ( .IN1(n4016), .IN2(n105), .IN3(n4015), .IN4(n657), .Q(n4045)
);
NOR2X0 U3754 ( .IN1(n4046), .IN2(n4047), .QN(n4015) );
AO21X1 U3755 ( .IN1(a1stg_faddsubs), .IN2(n4047), .IN3(n4048), .Q(n4016) );
AO21X1 U3756 ( .IN1(n1464), .IN2(n682), .IN3(n4009), .Q(
\fpu_add_exp_dp/n594 ) );
AO222X1 U3757 ( .IN1(n4049), .IN2(n126), .IN3(n4050), .IN4(n4013), .IN5(
n4051), .IN6(n658), .Q(n4009) );
OA21X1 U3758 ( .IN1(n2713), .IN2(n4044), .IN3(n4052), .Q(n4050) );
AO21X1 U3759 ( .IN1(n1465), .IN2(n681), .IN3(n4010), .Q(
\fpu_add_exp_dp/n593 ) );
AO222X1 U3760 ( .IN1(n4049), .IN2(n127), .IN3(n4053), .IN4(n4013), .IN5(
n4051), .IN6(n656), .Q(n4010) );
AOI21X1 U3761 ( .IN1(n2710), .IN2(n4052), .IN3(n4054), .QN(n4053) );
AO21X1 U3762 ( .IN1(n1465), .IN2(n680), .IN3(n4011), .Q(
\fpu_add_exp_dp/n592 ) );
AO222X1 U3763 ( .IN1(n4049), .IN2(n105), .IN3(n4013), .IN4(n4055), .IN5(
n4051), .IN6(n657), .Q(n4011) );
AND2X1 U3764 ( .IN1(n1340), .IN2(n4019), .Q(n4051) );
NOR2X0 U3765 ( .IN1(n4047), .IN2(n4056), .QN(n4019) );
XOR2X1 U3766 ( .IN1(n2706), .IN2(n4054), .Q(n4055) );
AND2X1 U3767 ( .IN1(n1337), .IN2(n4018), .Q(n4049) );
AO21X1 U3768 ( .IN1(n1658), .IN2(n4047), .IN3(a1stg_fdtos), .Q(n4018) );
INVX0 U3769 ( .INP(n2050), .ZN(n4047) );
AO21X1 U3770 ( .IN1(n1465), .IN2(n316), .IN3(n4012), .Q(
\fpu_add_exp_dp/n591 ) );
AND3X1 U3771 ( .IN1(n4013), .IN2(n2706), .IN3(n4054), .Q(n4012) );
NOR2X0 U3772 ( .IN1(n4052), .IN2(n2710), .QN(n4054) );
NAND2X0 U3773 ( .IN1(n559), .IN2(n1075), .QN(n2710) );
NAND2X0 U3774 ( .IN1(n4044), .IN2(n2713), .QN(n4052) );
NOR2X0 U3775 ( .IN1(\fpu_add_exp_dp/n176 ), .IN2(\fpu_add_exp_dp/n214 ),
.QN(n2713) );
NOR2X0 U3776 ( .IN1(n4040), .IN2(n2703), .QN(n4044) );
OA22X1 U3777 ( .IN1(\fpu_add_exp_dp/n215 ), .IN2(\fpu_add_exp_dp/n177 ),
.IN3(\fpu_add_exp_dp/n212 ), .IN4(\fpu_add_exp_dp/n196 ), .Q(n2703) );
NAND2X0 U3778 ( .IN1(n2729), .IN2(n2700), .QN(n4040) );
OAI22X1 U3779 ( .IN1(\fpu_add_exp_dp/n197 ), .IN2(\fpu_add_exp_dp/n213 ),
.IN3(\fpu_add_exp_dp/n178 ), .IN4(\fpu_add_exp_dp/n216 ), .QN(n2700)
);
NOR2X0 U3780 ( .IN1(n4035), .IN2(n4036), .QN(n2729) );
OA22X1 U3781 ( .IN1(\fpu_add_exp_dp/n217 ), .IN2(\fpu_add_exp_dp/n179 ),
.IN3(\fpu_add_exp_dp/n214 ), .IN4(\fpu_add_exp_dp/n198 ), .Q(n4036) );
NAND2X0 U3782 ( .IN1(n2651), .IN2(n2662), .QN(n4035) );
OAI22X1 U3783 ( .IN1(\fpu_add_exp_dp/n199 ), .IN2(\fpu_add_exp_dp/n215 ),
.IN3(\fpu_add_exp_dp/n180 ), .IN4(\fpu_add_exp_dp/n218 ), .QN(n2662)
);
AND2X1 U3784 ( .IN1(n4028), .IN2(n2649), .Q(n2651) );
OAI22X1 U3785 ( .IN1(\fpu_add_exp_dp/n200 ), .IN2(\fpu_add_exp_dp/n216 ),
.IN3(\fpu_add_exp_dp/n181 ), .IN4(\fpu_add_exp_dp/n219 ), .QN(n2649)
);
INVX0 U3786 ( .INP(n4025), .ZN(n4028) );
NAND2X0 U3787 ( .IN1(n2623), .IN2(n2631), .QN(n4025) );
OAI22X1 U3788 ( .IN1(\fpu_add_exp_dp/n220 ), .IN2(\fpu_add_exp_dp/n182 ),
.IN3(\fpu_add_exp_dp/n217 ), .IN4(\fpu_add_exp_dp/n201 ), .QN(n2631)
);
NOR2X0 U3789 ( .IN1(n2619), .IN2(n2622), .QN(n2623) );
OA22X1 U3790 ( .IN1(\fpu_add_exp_dp/n222 ), .IN2(\fpu_add_exp_dp/n184 ),
.IN3(\fpu_add_exp_dp/n219 ), .IN4(\fpu_add_exp_dp/n203 ), .Q(n2622) );
OA22X1 U3791 ( .IN1(\fpu_add_exp_dp/n202 ), .IN2(\fpu_add_exp_dp/n218 ),
.IN3(\fpu_add_exp_dp/n183 ), .IN4(\fpu_add_exp_dp/n221 ), .Q(n2619) );
NOR2X0 U3792 ( .IN1(\fpu_add_exp_dp/n174 ), .IN2(\fpu_add_exp_dp/n212 ),
.QN(n2706) );
NOR2X0 U3793 ( .IN1(n4057), .IN2(n4058), .QN(n4013) );
AO21X1 U3794 ( .IN1(n1466), .IN2(n830), .IN3(n4059), .Q(
\fpu_add_exp_dp/n589 ) );
AO21X1 U3795 ( .IN1(n1465), .IN2(n297), .IN3(n4059), .Q(
\fpu_add_exp_dp/n588 ) );
AO21X1 U3796 ( .IN1(n1465), .IN2(n305), .IN3(n4059), .Q(
\fpu_add_exp_dp/n587 ) );
AO21X1 U3797 ( .IN1(n1466), .IN2(n304), .IN3(n4059), .Q(
\fpu_add_exp_dp/n586 ) );
AO21X1 U3798 ( .IN1(n1465), .IN2(n303), .IN3(n4059), .Q(
\fpu_add_exp_dp/n585 ) );
AO221X1 U3799 ( .IN1(n1462), .IN2(n299), .IN3(n4060), .IN4(n1340), .IN5(
n4061), .Q(\fpu_add_exp_dp/n584 ) );
AO21X1 U3800 ( .IN1(n1466), .IN2(n302), .IN3(n4062), .Q(
\fpu_add_exp_dp/n583 ) );
AO22X1 U3801 ( .IN1(n1472), .IN2(n308), .IN3(n1338), .IN4(n4063), .Q(
\fpu_add_exp_dp/n582 ) );
NAND2X0 U3802 ( .IN1(n4064), .IN2(n4065), .QN(n4063) );
AO21X1 U3803 ( .IN1(n1465), .IN2(n301), .IN3(n4066), .Q(
\fpu_add_exp_dp/n581 ) );
AO21X1 U3804 ( .IN1(n1465), .IN2(n300), .IN3(n4066), .Q(
\fpu_add_exp_dp/n580 ) );
OA21X1 U3805 ( .IN1(n4067), .IN2(n4048), .IN3(n1338), .Q(n4066) );
AO221X1 U3806 ( .IN1(n1462), .IN2(n298), .IN3(n4068), .IN4(n1340), .IN5(
n4061), .Q(\fpu_add_exp_dp/n579 ) );
AO21X1 U3807 ( .IN1(n4069), .IN2(n1340), .IN3(n4059), .Q(n4061) );
AO21X1 U3808 ( .IN1(n1465), .IN2(n629), .IN3(n4062), .Q(
\fpu_add_exp_dp/n578 ) );
AO21X1 U3809 ( .IN1(n1465), .IN2(n694), .IN3(n4062), .Q(
\fpu_add_exp_dp/n577 ) );
AO21X1 U3810 ( .IN1(n1338), .IN2(n4067), .IN3(n4059), .Q(n4062) );
NOR2X0 U3811 ( .IN1(n4070), .IN2(n4057), .QN(n4059) );
OR3X1 U3812 ( .IN1(n4068), .IN2(n4069), .IN3(n4071), .Q(n4067) );
INVX0 U3813 ( .INP(n4064), .ZN(n4071) );
NOR2X0 U3814 ( .IN1(n4060), .IN2(n4072), .QN(n4064) );
AO221X1 U3815 ( .IN1(n4073), .IN2(n4074), .IN3(n4075), .IN4(n315), .IN5(
n4076), .Q(\fpu_add_exp_dp/n576 ) );
AO21X1 U3816 ( .IN1(n1466), .IN2(n583), .IN3(n4077), .Q(n4076) );
AO221X1 U3817 ( .IN1(n4075), .IN2(n676), .IN3(n1462), .IN4(n72), .IN5(n4078),
.Q(\fpu_add_exp_dp/n575 ) );
AO21X1 U3818 ( .IN1(n4079), .IN2(n4073), .IN3(n4080), .Q(n4078) );
INVX0 U3819 ( .INP(n4081), .ZN(n4079) );
AO221X1 U3820 ( .IN1(n4075), .IN2(n687), .IN3(n1463), .IN4(n159), .IN5(n4082), .Q(\fpu_add_exp_dp/n574 ) );
AO21X1 U3821 ( .IN1(n4083), .IN2(n4073), .IN3(n4080), .Q(n4082) );
AO221X1 U3822 ( .IN1(n4075), .IN2(n686), .IN3(n1462), .IN4(n178), .IN5(n4084), .Q(\fpu_add_exp_dp/n573 ) );
AO21X1 U3823 ( .IN1(n4085), .IN2(n4073), .IN3(n4080), .Q(n4084) );
AO221X1 U3824 ( .IN1(n4075), .IN2(n685), .IN3(n1463), .IN4(n67), .IN5(n4086),
.Q(\fpu_add_exp_dp/n572 ) );
AO21X1 U3825 ( .IN1(n4087), .IN2(n4073), .IN3(n4080), .Q(n4086) );
AND2X1 U3826 ( .IN1(n1339), .IN2(n4088), .Q(n4080) );
OR3X1 U3827 ( .IN1(n421), .IN2(n4089), .IN3(n718), .Q(n4088) );
AO221X1 U3828 ( .IN1(n4075), .IN2(n684), .IN3(n1463), .IN4(n69), .IN5(n4090),
.Q(\fpu_add_exp_dp/n571 ) );
AO22X1 U3829 ( .IN1(n4091), .IN2(n4073), .IN3(n1337), .IN4(n4089), .Q(n4090)
);
NAND2X0 U3830 ( .IN1(\fpu_add_ctl/n207 ), .IN2(n4092), .QN(n4089) );
AO221X1 U3831 ( .IN1(n4093), .IN2(n4073), .IN3(n4075), .IN4(n661), .IN5(
n4094), .Q(\fpu_add_exp_dp/n570 ) );
AO21X1 U3832 ( .IN1(n1465), .IN2(n160), .IN3(n4077), .Q(n4094) );
NAND2X0 U3833 ( .IN1(n4095), .IN2(n4096), .QN(n4077) );
NAND3X0 U3834 ( .IN1(n1339), .IN2(n91), .IN3(n4097), .QN(n4096) );
AO221X1 U3835 ( .IN1(n4075), .IN2(n683), .IN3(n1462), .IN4(n256), .IN5(n4098), .Q(\fpu_add_exp_dp/n569 ) );
AO22X1 U3836 ( .IN1(n4099), .IN2(n4073), .IN3(n1339), .IN4(n4100), .Q(n4098)
);
NAND2X0 U3837 ( .IN1(\fpu_add_ctl/n147 ), .IN2(n4092), .QN(n4100) );
AOI221X1 U3838 ( .IN1(n4097), .IN2(n91), .IN3(n4101), .IN4(n258), .IN5(n757),
.QN(n4092) );
INVX0 U3839 ( .INP(n4102), .ZN(n4097) );
AO221X1 U3840 ( .IN1(n4075), .IN2(n682), .IN3(n1463), .IN4(n71), .IN5(n4103),
.Q(\fpu_add_exp_dp/n568 ) );
AO21X1 U3841 ( .IN1(n4104), .IN2(n4073), .IN3(n4105), .Q(n4103) );
AO221X1 U3842 ( .IN1(n4075), .IN2(n681), .IN3(n1463), .IN4(n17), .IN5(n4106),
.Q(\fpu_add_exp_dp/n567 ) );
AO21X1 U3843 ( .IN1(n4107), .IN2(n4073), .IN3(n4105), .Q(n4106) );
AO221X1 U3844 ( .IN1(n4075), .IN2(n680), .IN3(n1462), .IN4(n181), .IN5(n4108), .Q(\fpu_add_exp_dp/n566 ) );
AO221X1 U3845 ( .IN1(n1338), .IN2(n4109), .IN3(n4110), .IN4(n4073), .IN5(
n4105), .Q(n4108) );
INVX0 U3846 ( .INP(n4095), .ZN(n4105) );
NAND3X0 U3847 ( .IN1(n1338), .IN2(n258), .IN3(n4101), .QN(n4095) );
AND3X1 U3848 ( .IN1(n4111), .IN2(n4112), .IN3(n1340), .Q(n4073) );
AO21X1 U3849 ( .IN1(n4102), .IN2(n91), .IN3(n258), .Q(n4112) );
NAND4X0 U3850 ( .IN1(n4101), .IN2(n289), .IN3(n88), .IN4(n35), .QN(n4102) );
AND4X1 U3851 ( .IN1(n1901), .IN2(n221), .IN3(n1910), .IN4(n4113), .Q(n4101)
);
NOR3X0 U3852 ( .IN1(\fpu_add_exp_dp/n141 ), .IN2(\fpu_add_exp_dp/n146 ),
.IN3(\fpu_add_exp_dp/n143 ), .QN(n4113) );
NOR2X0 U3853 ( .IN1(\fpu_add_exp_dp/n142 ), .IN2(\fpu_add_exp_dp/n144 ),
.QN(n1910) );
NAND2X0 U3854 ( .IN1(\fpu_add_ctl/n150 ), .IN2(\fpu_add_ctl/n207 ), .QN(
n4109) );
AO22X1 U3855 ( .IN1(n4000), .IN2(n728), .IN3(n4075), .IN4(n316), .Q(
\fpu_add_exp_dp/n565 ) );
OAI22X1 U3856 ( .IN1(n4057), .IN2(\fpu_add_exp_dp/n444 ), .IN3(n4114), .IN4(
\fpu_add_exp_dp/n57 ), .QN(\fpu_add_exp_dp/n563 ) );
AO22X1 U3857 ( .IN1(n1337), .IN2(n72), .IN3(n1469), .IN4(n643), .Q(
\fpu_add_exp_dp/n562 ) );
OAI22X1 U3858 ( .IN1(n4057), .IN2(\fpu_add_exp_dp/n431 ), .IN3(n4114), .IN4(
\fpu_add_exp_dp/n438 ), .QN(\fpu_add_exp_dp/n561 ) );
OAI22X1 U3859 ( .IN1(n4057), .IN2(\fpu_add_exp_dp/n434 ), .IN3(n4114), .IN4(
\fpu_add_exp_dp/n439 ), .QN(\fpu_add_exp_dp/n560 ) );
OAI22X1 U3860 ( .IN1(n4057), .IN2(\fpu_add_exp_dp/n432 ), .IN3(n4114), .IN4(
\fpu_add_exp_dp/n440 ), .QN(\fpu_add_exp_dp/n559 ) );
AO22X1 U3861 ( .IN1(n1339), .IN2(n69), .IN3(n1470), .IN4(n761), .Q(
\fpu_add_exp_dp/n558 ) );
AO22X1 U3862 ( .IN1(n1338), .IN2(n160), .IN3(n1469), .IN4(n666), .Q(
\fpu_add_exp_dp/n557 ) );
OAI22X1 U3863 ( .IN1(n4057), .IN2(\fpu_add_exp_dp/n442 ), .IN3(n4114), .IN4(
\fpu_add_exp_dp/n50 ), .QN(\fpu_add_exp_dp/n556 ) );
OAI22X1 U3864 ( .IN1(n4057), .IN2(\fpu_add_exp_dp/n445 ), .IN3(n4114), .IN4(
\fpu_add_exp_dp/n450 ), .QN(\fpu_add_exp_dp/n555 ) );
OAI22X1 U3865 ( .IN1(n4057), .IN2(\fpu_add_exp_dp/n443 ), .IN3(n4114), .IN4(
\fpu_add_exp_dp/n48 ), .QN(\fpu_add_exp_dp/n554 ) );
AO22X1 U3866 ( .IN1(n1340), .IN2(n181), .IN3(n1470), .IN4(n663), .Q(
\fpu_add_exp_dp/n553 ) );
OAI22X1 U3867 ( .IN1(n4057), .IN2(\fpu_add_exp_dp/n447 ), .IN3(n4114), .IN4(
\fpu_add_exp_dp/n46 ), .QN(\fpu_add_exp_dp/n552 ) );
AO21X1 U3868 ( .IN1(n1465), .IN2(n454), .IN3(n4115), .Q(
\fpu_add_exp_dp/n550 ) );
OA222X1 U3869 ( .IN1(n2959), .IN2(n2957), .IN3(n4116), .IN4(n4117), .IN5(
n4118), .IN6(n4119), .Q(n4115) );
AND2X1 U3870 ( .IN1(n2962), .IN2(n1339), .Q(n4116) );
XOR2X1 U3871 ( .IN1(\fpu_add_ctl/n307 ), .IN2(n4120), .Q(n2957) );
NOR2X0 U3872 ( .IN1(\fpu_add_ctl/n337 ), .IN2(\fpu_add_ctl/n937 ), .QN(n4120) );
AO221X1 U3873 ( .IN1(n4121), .IN2(n4122), .IN3(n1463), .IN4(n440), .IN5(
n4123), .Q(\fpu_add_exp_dp/n549 ) );
NAND2X0 U3874 ( .IN1(n4124), .IN2(n4125), .QN(n4123) );
NAND3X0 U3875 ( .IN1(n4126), .IN2(n4127), .IN3(n4128), .QN(n4124) );
NAND2X0 U3876 ( .IN1(n4129), .IN2(n4130), .QN(n4127) );
AO221X1 U3877 ( .IN1(n4122), .IN2(n4131), .IN3(n1462), .IN4(n439), .IN5(
n4132), .Q(\fpu_add_exp_dp/n548 ) );
NAND2X0 U3878 ( .IN1(n4133), .IN2(n4125), .QN(n4132) );
NAND3X0 U3879 ( .IN1(n4126), .IN2(n4134), .IN3(n4135), .QN(n4133) );
INVX0 U3880 ( .INP(n4136), .ZN(n4135) );
NAND2X0 U3881 ( .IN1(n4137), .IN2(n4129), .QN(n4134) );
INVX0 U3882 ( .INP(n4137), .ZN(n4131) );
AO221X1 U3883 ( .IN1(n4122), .IN2(n4138), .IN3(n1463), .IN4(n438), .IN5(
n4139), .Q(\fpu_add_exp_dp/n547 ) );
NAND2X0 U3884 ( .IN1(n4140), .IN2(n4125), .QN(n4139) );
NAND3X0 U3885 ( .IN1(n4126), .IN2(n4141), .IN3(n4142), .QN(n4140) );
NAND2X0 U3886 ( .IN1(n4143), .IN2(n4129), .QN(n4141) );
INVX0 U3887 ( .INP(n4143), .ZN(n4138) );
AO221X1 U3888 ( .IN1(n4122), .IN2(n4144), .IN3(n1462), .IN4(n437), .IN5(
n4145), .Q(\fpu_add_exp_dp/n546 ) );
NAND2X0 U3889 ( .IN1(n4146), .IN2(n4125), .QN(n4145) );
NAND3X0 U3890 ( .IN1(n4126), .IN2(n4147), .IN3(n4148), .QN(n4146) );
NAND2X0 U3891 ( .IN1(n4149), .IN2(n4129), .QN(n4147) );
INVX0 U3892 ( .INP(n4149), .ZN(n4144) );
AO221X1 U3893 ( .IN1(n4122), .IN2(n4150), .IN3(n1462), .IN4(n436), .IN5(
n4151), .Q(\fpu_add_exp_dp/n545 ) );
NAND2X0 U3894 ( .IN1(n4152), .IN2(n4125), .QN(n4151) );
NAND3X0 U3895 ( .IN1(n4126), .IN2(n4153), .IN3(n4154), .QN(n4152) );
NAND2X0 U3896 ( .IN1(n4155), .IN2(n4129), .QN(n4153) );
AO221X1 U3897 ( .IN1(n4156), .IN2(n4122), .IN3(n1462), .IN4(n435), .IN5(
n4157), .Q(\fpu_add_exp_dp/n544 ) );
NAND2X0 U3898 ( .IN1(n4158), .IN2(n4125), .QN(n4157) );
NAND3X0 U3899 ( .IN1(n4126), .IN2(n4159), .IN3(n4160), .QN(n4158) );
NAND2X0 U3900 ( .IN1(n4129), .IN2(n4161), .QN(n4159) );
INVX0 U3901 ( .INP(n4161), .ZN(n4156) );
AO221X1 U3902 ( .IN1(n4162), .IN2(n4122), .IN3(n1463), .IN4(n434), .IN5(
n4163), .Q(\fpu_add_exp_dp/n543 ) );
NAND2X0 U3903 ( .IN1(n4164), .IN2(n4125), .QN(n4163) );
NAND2X0 U3904 ( .IN1(n4122), .IN2(n4119), .QN(n4125) );
NAND3X0 U3905 ( .IN1(n4126), .IN2(n4165), .IN3(n4166), .QN(n4164) );
NAND2X0 U3906 ( .IN1(n4129), .IN2(n4167), .QN(n4165) );
INVX0 U3907 ( .INP(n4119), .ZN(n4129) );
AND2X1 U3908 ( .IN1(n4126), .IN2(n2962), .Q(n4122) );
AO21X1 U3909 ( .IN1(n1467), .IN2(n759), .IN3(n4168), .Q(
\fpu_add_exp_dp/n542 ) );
OA221X1 U3910 ( .IN1(n2962), .IN2(n4169), .IN3(n4170), .IN4(n4119), .IN5(
n4171), .Q(n4168) );
INVX0 U3911 ( .INP(n4172), .ZN(n4169) );
AO21X1 U3912 ( .IN1(n1466), .IN2(n758), .IN3(n4173), .Q(
\fpu_add_exp_dp/n541 ) );
OA221X1 U3913 ( .IN1(n2962), .IN2(n4174), .IN3(n4175), .IN4(n4119), .IN5(
n4171), .Q(n4173) );
AO21X1 U3914 ( .IN1(n1466), .IN2(n760), .IN3(n4176), .Q(
\fpu_add_exp_dp/n540 ) );
OA221X1 U3915 ( .IN1(n2962), .IN2(n4177), .IN3(n4178), .IN4(n4119), .IN5(
n4171), .Q(n4176) );
AO21X1 U3916 ( .IN1(\fpu_add_ctl/n65 ), .IN2(n1338), .IN3(n4126), .Q(n4171)
);
AND2X1 U3917 ( .IN1(n1338), .IN2(n2959), .Q(n4126) );
AO21X1 U3918 ( .IN1(\fpu_add_ctl/n90 ), .IN2(n4179), .IN3(
\fpu_add_frac_dp/n596 ), .Q(n4119) );
NAND2X0 U3919 ( .IN1(n2959), .IN2(n2960), .QN(n4179) );
INVX0 U3920 ( .INP(n4180), .ZN(n4178) );
OA22X1 U3921 ( .IN1(n4181), .IN2(\fpu_add_ctl/n315 ), .IN3(n4182), .IN4(
n4183), .Q(n2962) );
AO221X1 U3922 ( .IN1(n1462), .IN2(n764), .IN3(n1339), .IN4(n4184), .IN5(
n4185), .Q(\fpu_add_exp_dp/n539 ) );
AO221X1 U3923 ( .IN1(n4186), .IN2(n1337), .IN3(n1463), .IN4(n738), .IN5(
n4187), .Q(\fpu_add_exp_dp/n538 ) );
AO21X1 U3924 ( .IN1(n4117), .IN2(n4128), .IN3(n4185), .Q(n4187) );
INVX0 U3925 ( .INP(n4188), .ZN(n4117) );
AO221X1 U3926 ( .IN1(n1337), .IN2(n4189), .IN3(n1463), .IN4(n737), .IN5(
n4185), .Q(\fpu_add_exp_dp/n537 ) );
OAI21X1 U3927 ( .IN1(n4136), .IN2(n4186), .IN3(n4190), .QN(n4189) );
AO221X1 U3928 ( .IN1(n1340), .IN2(n4191), .IN3(n1463), .IN4(n736), .IN5(
n4185), .Q(\fpu_add_exp_dp/n536 ) );
AO21X1 U3929 ( .IN1(n4142), .IN2(n4190), .IN3(n4192), .Q(n4191) );
AO221X1 U3930 ( .IN1(n1339), .IN2(n4193), .IN3(n1463), .IN4(n735), .IN5(
n4185), .Q(\fpu_add_exp_dp/n535 ) );
OAI21X1 U3931 ( .IN1(n4194), .IN2(n4192), .IN3(n4195), .QN(n4193) );
AO221X1 U3932 ( .IN1(n1338), .IN2(n4196), .IN3(n1464), .IN4(n734), .IN5(
n4185), .Q(\fpu_add_exp_dp/n534 ) );
AO21X1 U3933 ( .IN1(n4154), .IN2(n4195), .IN3(n4197), .Q(n4196) );
AO221X1 U3934 ( .IN1(n1337), .IN2(n4198), .IN3(n1463), .IN4(n733), .IN5(
n4185), .Q(\fpu_add_exp_dp/n533 ) );
OAI21X1 U3935 ( .IN1(n4199), .IN2(n4197), .IN3(n4200), .QN(n4198) );
AO221X1 U3936 ( .IN1(n1340), .IN2(n4201), .IN3(n1464), .IN4(n732), .IN5(
n4185), .Q(\fpu_add_exp_dp/n532 ) );
AO21X1 U3937 ( .IN1(n4166), .IN2(n4200), .IN3(n4202), .Q(n4201) );
AO221X1 U3938 ( .IN1(n1339), .IN2(n4203), .IN3(n1464), .IN4(n442), .IN5(
n4185), .Q(\fpu_add_exp_dp/n531 ) );
OAI21X1 U3939 ( .IN1(n4172), .IN2(n4202), .IN3(n4204), .QN(n4203) );
AO221X1 U3940 ( .IN1(n1338), .IN2(n4205), .IN3(n1463), .IN4(n441), .IN5(
n4185), .Q(\fpu_add_exp_dp/n530 ) );
AO21X1 U3941 ( .IN1(n4174), .IN2(n4204), .IN3(n4206), .Q(n4205) );
AO221X1 U3942 ( .IN1(n1337), .IN2(n4207), .IN3(n1464), .IN4(n443), .IN5(
n4185), .Q(\fpu_add_exp_dp/n529 ) );
AND2X1 U3943 ( .IN1(n1340), .IN2(n4208), .Q(n4185) );
NAND3X0 U3944 ( .IN1(n2963), .IN2(n2956), .IN3(n2950), .QN(n4208) );
AO22X1 U3945 ( .IN1(n4209), .IN2(n4182), .IN3(n4181), .IN4(n622), .Q(n2963)
);
AO22X1 U3946 ( .IN1(n4210), .IN2(n108), .IN3(n4211), .IN4(n552), .Q(n4181)
);
INVX0 U3947 ( .INP(n4183), .ZN(n4209) );
XOR2X1 U3948 ( .IN1(n4177), .IN2(n4206), .Q(n4207) );
NOR2X0 U3949 ( .IN1(n4204), .IN2(n4174), .QN(n4206) );
INVX0 U3950 ( .INP(n4212), .ZN(n4174) );
NAND2X0 U3951 ( .IN1(n4202), .IN2(n4172), .QN(n4204) );
NOR2X0 U3952 ( .IN1(n4200), .IN2(n4166), .QN(n4202) );
NAND2X0 U3953 ( .IN1(n4197), .IN2(n4199), .QN(n4200) );
NOR2X0 U3954 ( .IN1(n4195), .IN2(n4154), .QN(n4197) );
NAND2X0 U3955 ( .IN1(n4192), .IN2(n4194), .QN(n4195) );
NOR2X0 U3956 ( .IN1(n4190), .IN2(n4142), .QN(n4192) );
NAND2X0 U3957 ( .IN1(n4186), .IN2(n4136), .QN(n4190) );
NOR2X0 U3958 ( .IN1(n4213), .IN2(n4128), .QN(n4186) );
INVX0 U3959 ( .INP(n4214), .ZN(n4128) );
INVX0 U3960 ( .INP(n4215), .ZN(n4177) );
NAND3X0 U3961 ( .IN1(n4188), .IN2(n4216), .IN3(n4217), .QN(
\fpu_add_exp_dp/n528 ) );
OR2X1 U3962 ( .IN1(n4114), .IN2(\fpu_add_exp_dp/n22 ), .Q(n4217) );
NAND2X0 U3963 ( .IN1(n4213), .IN2(n1337), .QN(n4188) );
OAI221X1 U3964 ( .IN1(n4114), .IN2(\fpu_add_exp_dp/n21 ), .IN3(n4214), .IN4(
n4057), .IN5(n4216), .QN(\fpu_add_exp_dp/n527 ) );
OAI221X1 U3965 ( .IN1(n4114), .IN2(\fpu_add_exp_dp/n20 ), .IN3(n4136), .IN4(
n4057), .IN5(n4216), .QN(\fpu_add_exp_dp/n526 ) );
OAI221X1 U3966 ( .IN1(n4114), .IN2(\fpu_add_exp_dp/n19 ), .IN3(n4218), .IN4(
n4057), .IN5(n4216), .QN(\fpu_add_exp_dp/n525 ) );
OAI221X1 U3967 ( .IN1(n4114), .IN2(\fpu_add_exp_dp/n18 ), .IN3(n4194), .IN4(
n4057), .IN5(n4216), .QN(\fpu_add_exp_dp/n524 ) );
OAI221X1 U3968 ( .IN1(n4114), .IN2(\fpu_add_exp_dp/n17 ), .IN3(n4219), .IN4(
n4057), .IN5(n4216), .QN(\fpu_add_exp_dp/n523 ) );
OAI221X1 U3969 ( .IN1(n4114), .IN2(\fpu_add_exp_dp/n16 ), .IN3(n4199), .IN4(
n4057), .IN5(n4216), .QN(\fpu_add_exp_dp/n522 ) );
OAI221X1 U3970 ( .IN1(n4114), .IN2(\fpu_add_exp_dp/n15 ), .IN3(n4220), .IN4(
n4057), .IN5(n4216), .QN(\fpu_add_exp_dp/n521 ) );
OAI221X1 U3971 ( .IN1(n4114), .IN2(\fpu_add_exp_dp/n14 ), .IN3(n4057), .IN4(
n4172), .IN5(n4216), .QN(\fpu_add_exp_dp/n520 ) );
OAI221X1 U3972 ( .IN1(n4114), .IN2(\fpu_add_exp_dp/n13 ), .IN3(n4057), .IN4(
n4212), .IN5(n4216), .QN(\fpu_add_exp_dp/n519 ) );
OAI221X1 U3973 ( .IN1(n4114), .IN2(\fpu_add_exp_dp/n12 ), .IN3(n4057), .IN4(
n4215), .IN5(n4216), .QN(\fpu_add_exp_dp/n518 ) );
NAND3X0 U3974 ( .IN1(n1337), .IN2(n4183), .IN3(\fpu_add_ctl/n315 ), .QN(
n4216) );
NAND2X0 U3975 ( .IN1(n2959), .IN2(n4221), .QN(n4183) );
AO21X1 U3976 ( .IN1(n296), .IN2(n927), .IN3(n55), .Q(n4221) );
AO21X1 U3977 ( .IN1(n1466), .IN2(n1236), .IN3(n4222), .Q(
\fpu_add_exp_dp/n517 ) );
AO21X1 U3978 ( .IN1(n1467), .IN2(n1237), .IN3(n4222), .Q(
\fpu_add_exp_dp/n516 ) );
AO21X1 U3979 ( .IN1(n1466), .IN2(n1225), .IN3(n4222), .Q(
\fpu_add_exp_dp/n515 ) );
AO21X1 U3980 ( .IN1(n1466), .IN2(n1226), .IN3(n4222), .Q(
\fpu_add_exp_dp/n514 ) );
AO21X1 U3981 ( .IN1(n1467), .IN2(n1227), .IN3(n4222), .Q(
\fpu_add_exp_dp/n513 ) );
AO21X1 U3982 ( .IN1(n1467), .IN2(n1228), .IN3(n4222), .Q(
\fpu_add_exp_dp/n512 ) );
AO21X1 U3983 ( .IN1(n1467), .IN2(n1229), .IN3(n4222), .Q(
\fpu_add_exp_dp/n511 ) );
AO21X1 U3984 ( .IN1(n1467), .IN2(n1230), .IN3(n4222), .Q(
\fpu_add_exp_dp/n510 ) );
AO21X1 U3985 ( .IN1(n1467), .IN2(n1231), .IN3(n4222), .Q(
\fpu_add_exp_dp/n509 ) );
AO21X1 U3986 ( .IN1(n1467), .IN2(n1232), .IN3(n4222), .Q(
\fpu_add_exp_dp/n508 ) );
AO21X1 U3987 ( .IN1(n1467), .IN2(n1238), .IN3(n4222), .Q(
\fpu_add_exp_dp/n507 ) );
AND3X1 U3988 ( .IN1(n2950), .IN2(n2956), .IN3(n1339), .Q(n4222) );
AND3X1 U3989 ( .IN1(n2952), .IN2(n2948), .IN3(n2944), .Q(n2950) );
AND3X1 U3990 ( .IN1(n2946), .IN2(n2942), .IN3(n2937), .Q(n2944) );
AND3X1 U3991 ( .IN1(n2985), .IN2(n2940), .IN3(n2930), .Q(n2937) );
INVX0 U3992 ( .INP(n2934), .ZN(n2930) );
NAND3X0 U3993 ( .IN1(n2932), .IN2(n2928), .IN3(n2924), .QN(n2934) );
AND3X1 U3994 ( .IN1(n2926), .IN2(n2922), .IN3(n2918), .Q(n2924) );
AND3X1 U3995 ( .IN1(n2920), .IN2(n2916), .IN3(n2912), .Q(n2918) );
AND3X1 U3996 ( .IN1(n2914), .IN2(n2910), .IN3(n2906), .Q(n2912) );
AND3X1 U3997 ( .IN1(n2908), .IN2(n2904), .IN3(n2900), .Q(n2906) );
AND3X1 U3998 ( .IN1(n2902), .IN2(n2898), .IN3(n2894), .Q(n2900) );
AND3X1 U3999 ( .IN1(n2896), .IN2(n2891), .IN3(n2892), .Q(n2894) );
INVX0 U4000 ( .INP(n2889), .ZN(n2892) );
NAND2X0 U4001 ( .IN1(n2887), .IN2(n2888), .QN(n2889) );
AO22X1 U4002 ( .IN1(n2878), .IN2(n2984), .IN3(n4223), .IN4(n2884), .Q(n2887)
);
NAND2X0 U4003 ( .IN1(n2885), .IN2(n2883), .QN(n4223) );
INVX0 U4004 ( .INP(n2984), .ZN(n2885) );
INVX0 U4005 ( .INP(n2883), .ZN(n2878) );
NAND3X0 U4006 ( .IN1(n2983), .IN2(n2881), .IN3(n2869), .QN(n2883) );
INVX0 U4007 ( .INP(n2875), .ZN(n2869) );
NAND3X0 U4008 ( .IN1(n2982), .IN2(n2867), .IN3(n2863), .QN(n2875) );
INVX0 U4009 ( .INP(n2872), .ZN(n2863) );
NAND3X0 U4010 ( .IN1(n2981), .IN2(n2980), .IN3(n2856), .QN(n2872) );
INVX0 U4011 ( .INP(n2860), .ZN(n2856) );
NAND3X0 U4012 ( .IN1(n2858), .IN2(n2854), .IN3(n2850), .QN(n2860) );
AND3X1 U4013 ( .IN1(n2852), .IN2(n2848), .IN3(n2844), .Q(n2850) );
AND3X1 U4014 ( .IN1(n2846), .IN2(n2842), .IN3(n2838), .Q(n2844) );
AND3X1 U4015 ( .IN1(n2840), .IN2(n2836), .IN3(n2832), .Q(n2838) );
AND3X1 U4016 ( .IN1(n2834), .IN2(n2830), .IN3(n2826), .Q(n2832) );
AND3X1 U4017 ( .IN1(n2979), .IN2(n2978), .IN3(n2817), .Q(n2826) );
INVX0 U4018 ( .INP(n2823), .ZN(n2817) );
NAND3X0 U4019 ( .IN1(n2977), .IN2(n2815), .IN3(n2811), .QN(n2823) );
INVX0 U4020 ( .INP(n2820), .ZN(n2811) );
NAND3X0 U4021 ( .IN1(n2976), .IN2(n2975), .IN3(n2802), .QN(n2820) );
INVX0 U4022 ( .INP(n2808), .ZN(n2802) );
NAND3X0 U4023 ( .IN1(n2974), .IN2(n2800), .IN3(n2796), .QN(n2808) );
INVX0 U4024 ( .INP(n2805), .ZN(n2796) );
NAND3X0 U4025 ( .IN1(n2798), .IN2(n2794), .IN3(n2790), .QN(n2805) );
AND3X1 U4026 ( .IN1(n2792), .IN2(n2788), .IN3(n2784), .Q(n2790) );
OA21X1 U4027 ( .IN1(n108), .IN2(n21), .IN3(n2786), .Q(n2784) );
NOR2X0 U4028 ( .IN1(\fpu_add_exp_dp/n256 ), .IN2(\fpu_add_frac_dp/n2189 ),
.QN(\fpu_add_exp_dp/n448 ) );
INVX0 U4029 ( .INP(rclk), .ZN(\fpu_add_frac_dp/n2189 ) );
NOR2X0 U4030 ( .IN1(\fpu_add_exp_dp/n435 ), .IN2(n4224), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N9 ) );
NOR2X0 U4031 ( .IN1(\fpu_add_exp_dp/n433 ), .IN2(n4224), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N8 ) );
NOR2X0 U4032 ( .IN1(\fpu_add_exp_dp/n432 ), .IN2(n4224), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N7 ) );
NOR2X0 U4033 ( .IN1(\fpu_add_exp_dp/n434 ), .IN2(n4224), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N6 ) );
NOR2X0 U4034 ( .IN1(\fpu_add_exp_dp/n431 ), .IN2(n4224), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N5 ) );
NOR2X0 U4035 ( .IN1(\fpu_add_exp_dp/n436 ), .IN2(n4224), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N4 ) );
NOR2X0 U4036 ( .IN1(\fpu_add_exp_dp/n444 ), .IN2(n4224), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N3 ) );
NOR2X0 U4037 ( .IN1(\fpu_add_exp_dp/n447 ), .IN2(n4224), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N14 ) );
NOR2X0 U4038 ( .IN1(\fpu_add_exp_dp/n446 ), .IN2(n4224), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N13 ) );
NOR2X0 U4039 ( .IN1(\fpu_add_exp_dp/n443 ), .IN2(n4224), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N12 ) );
NOR2X0 U4040 ( .IN1(\fpu_add_exp_dp/n445 ), .IN2(n4224), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N11 ) );
NOR2X0 U4041 ( .IN1(\fpu_add_exp_dp/n442 ), .IN2(n4224), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre4/N10 ) );
NAND3X0 U4042 ( .IN1(n3143), .IN2(n4225), .IN3(n4226), .QN(n4224) );
NAND2X0 U4043 ( .IN1(n3171), .IN2(n3144), .QN(n4225) );
INVX0 U4044 ( .INP(n3545), .ZN(n3143) );
NOR2X0 U4045 ( .IN1(n4227), .IN2(n4228), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N9 ) );
AOI21X1 U4046 ( .IN1(n160), .IN2(n4229), .IN3(n4230), .QN(n4227) );
NOR2X0 U4047 ( .IN1(n4231), .IN2(n4228), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N8 ) );
OA21X1 U4048 ( .IN1(\fpu_add_exp_dp/n433 ), .IN2(n4232), .IN3(n4229), .Q(
n4231) );
NOR2X0 U4049 ( .IN1(n4233), .IN2(n4228), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N7 ) );
AOI21X1 U4050 ( .IN1(n67), .IN2(n4234), .IN3(n4232), .QN(n4233) );
NOR2X0 U4051 ( .IN1(n4235), .IN2(n4228), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N6 ) );
OA21X1 U4052 ( .IN1(\fpu_add_exp_dp/n434 ), .IN2(n4236), .IN3(n4234), .Q(
n4235) );
NOR2X0 U4053 ( .IN1(n4237), .IN2(n4228), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N5 ) );
AOI21X1 U4054 ( .IN1(n159), .IN2(n4238), .IN3(n4236), .QN(n4237) );
NOR2X0 U4055 ( .IN1(n4239), .IN2(n4228), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N4 ) );
OA21X1 U4056 ( .IN1(\fpu_add_exp_dp/n444 ), .IN2(\fpu_add_exp_dp/n436 ),
.IN3(n4238), .Q(n4239) );
NOR2X0 U4057 ( .IN1(n583), .IN2(n4228), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N3 ) );
NOR2X0 U4058 ( .IN1(\fpu_add_exp_dp/n447 ), .IN2(n4228), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N14 ) );
NOR3X0 U4059 ( .IN1(n4228), .IN2(\fpu_add_exp_dp/n446 ), .IN3(n4240), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N13 ) );
NOR2X0 U4060 ( .IN1(n4241), .IN2(n4228), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N12 ) );
AOI21X1 U4061 ( .IN1(n17), .IN2(n4242), .IN3(n4240), .QN(n4241) );
NOR2X0 U4062 ( .IN1(n4242), .IN2(n17), .QN(n4240) );
INVX0 U4063 ( .INP(n4243), .ZN(n4242) );
NOR2X0 U4064 ( .IN1(n4244), .IN2(n4228), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N11 ) );
AOI21X1 U4065 ( .IN1(n71), .IN2(n4245), .IN3(n4243), .QN(n4244) );
NOR2X0 U4066 ( .IN1(n4245), .IN2(n71), .QN(n4243) );
NOR2X0 U4067 ( .IN1(n4246), .IN2(n4228), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre3/N10 ) );
NAND4X0 U4068 ( .IN1(n3175), .IN2(n4226), .IN3(n2601), .IN4(n3144), .QN(
n4228) );
INVX0 U4069 ( .INP(n3547), .ZN(n3144) );
NOR2X0 U4070 ( .IN1(n583), .IN2(n3146), .QN(n3547) );
NAND4X0 U4071 ( .IN1(\fpu_add_exp_dp/n435 ), .IN2(\fpu_add_exp_dp/n434 ),
.IN3(n4247), .IN4(n4248), .QN(n3146) );
NOR4X0 U4072 ( .IN1(n17), .IN2(n4249), .IN3(n71), .IN4(n181), .QN(n4248) );
NAND2X0 U4073 ( .IN1(\fpu_add_exp_dp/n442 ), .IN2(\fpu_add_exp_dp/n436 ),
.QN(n4249) );
AND3X1 U4074 ( .IN1(\fpu_add_exp_dp/n433 ), .IN2(\fpu_add_exp_dp/n432 ),
.IN3(\fpu_add_exp_dp/n431 ), .Q(n4247) );
NOR2X0 U4075 ( .IN1(n3545), .IN2(n3141), .QN(n2601) );
INVX0 U4076 ( .INP(n3171), .ZN(n3141) );
XNOR3X1 U4077 ( .IN1(\fpu_add_frac_dp/n673 ), .IN2(\fpu_add_frac_dp/n568 ),
.IN3(n4250), .Q(n3171) );
INVX0 U4078 ( .INP(n2602), .ZN(n3175) );
XNOR3X1 U4079 ( .IN1(\fpu_add_frac_dp/n674 ), .IN2(\fpu_add_frac_dp/n567 ),
.IN3(n4251), .Q(n2602) );
OA21X1 U4080 ( .IN1(\fpu_add_exp_dp/n442 ), .IN2(n4230), .IN3(n4245), .Q(
n4246) );
NAND2X0 U4081 ( .IN1(n4230), .IN2(\fpu_add_exp_dp/n442 ), .QN(n4245) );
NOR2X0 U4082 ( .IN1(n4229), .IN2(n160), .QN(n4230) );
NAND2X0 U4083 ( .IN1(n4232), .IN2(\fpu_add_exp_dp/n433 ), .QN(n4229) );
NOR2X0 U4084 ( .IN1(n4234), .IN2(n67), .QN(n4232) );
NAND2X0 U4085 ( .IN1(n4236), .IN2(\fpu_add_exp_dp/n434 ), .QN(n4234) );
NOR2X0 U4086 ( .IN1(n4238), .IN2(n159), .QN(n4236) );
AO222X1 U4087 ( .IN1(n4252), .IN2(n160), .IN3(n4253), .IN4(n4161), .IN5(
n1461), .IN6(n4199), .Q(\fpu_add_exp_dp/i_a4stg_exp_pre2/N9 ) );
AO21X1 U4088 ( .IN1(n4254), .IN2(n666), .IN3(n4255), .Q(n4161) );
AO222X1 U4089 ( .IN1(n4252), .IN2(n69), .IN3(n4253), .IN4(n4155), .IN5(n1461), .IN6(n4219), .Q(\fpu_add_exp_dp/i_a4stg_exp_pre2/N8 ) );
INVX0 U4090 ( .INP(n4150), .ZN(n4155) );
XNOR3X1 U4091 ( .IN1(\fpu_add_frac_dp/n593 ), .IN2(\fpu_add_exp_dp/n441 ),
.IN3(n4256), .Q(n4150) );
AO222X1 U4092 ( .IN1(n4252), .IN2(n67), .IN3(n4253), .IN4(n4149), .IN5(n1462), .IN6(n4194), .Q(\fpu_add_exp_dp/i_a4stg_exp_pre2/N7 ) );
XOR3X1 U4093 ( .IN1(\fpu_add_frac_dp/n594 ), .IN2(\fpu_add_exp_dp/n440 ),
.IN3(n4257), .Q(n4149) );
AO222X1 U4094 ( .IN1(n4252), .IN2(n178), .IN3(n4253), .IN4(n4143), .IN5(
n1462), .IN6(n4218), .Q(\fpu_add_exp_dp/i_a4stg_exp_pre2/N6 ) );
XOR3X1 U4095 ( .IN1(\fpu_add_frac_dp/n2307 ), .IN2(\fpu_add_exp_dp/n439 ),
.IN3(n4258), .Q(n4143) );
AO222X1 U4096 ( .IN1(n4252), .IN2(n159), .IN3(n4253), .IN4(n4137), .IN5(
n1461), .IN6(n4136), .Q(\fpu_add_exp_dp/i_a4stg_exp_pre2/N5 ) );
XOR3X1 U4097 ( .IN1(\fpu_add_frac_dp/n2471 ), .IN2(\fpu_add_exp_dp/n438 ),
.IN3(n4259), .Q(n4137) );
AO222X1 U4098 ( .IN1(n4252), .IN2(n72), .IN3(n4253), .IN4(n4130), .IN5(n1462), .IN6(n4214), .Q(\fpu_add_exp_dp/i_a4stg_exp_pre2/N4 ) );
INVX0 U4099 ( .INP(n4121), .ZN(n4130) );
XOR3X1 U4100 ( .IN1(n4260), .IN2(\fpu_add_frac_dp/n2460 ), .IN3(n643), .Q(
n4121) );
AO222X1 U4101 ( .IN1(n4252), .IN2(n583), .IN3(n4253), .IN4(n4261), .IN5(
n1461), .IN6(n4184), .Q(\fpu_add_exp_dp/i_a4stg_exp_pre2/N3 ) );
INVX0 U4102 ( .INP(n4118), .ZN(n4261) );
OA21X1 U4103 ( .IN1(n154), .IN2(\fpu_add_exp_dp/n57 ), .IN3(n4262), .Q(n4118) );
AO222X1 U4104 ( .IN1(n4252), .IN2(n728), .IN3(n4263), .IN4(n4253), .IN5(
n1461), .IN6(n4264), .Q(\fpu_add_exp_dp/i_a4stg_exp_pre2/N14 ) );
XNOR2X1 U4105 ( .IN1(\fpu_add_exp_dp/n46 ), .IN2(n4265), .Q(n4263) );
AO222X1 U4106 ( .IN1(n4252), .IN2(n181), .IN3(n4253), .IN4(n4180), .IN5(
n1461), .IN6(n4215), .Q(\fpu_add_exp_dp/i_a4stg_exp_pre2/N13 ) );
AO21X1 U4107 ( .IN1(n663), .IN2(n4266), .IN3(n4265), .Q(n4180) );
NOR2X0 U4108 ( .IN1(n663), .IN2(n4266), .QN(n4265) );
AO222X1 U4109 ( .IN1(n4252), .IN2(n17), .IN3(n4253), .IN4(n4267), .IN5(n1461), .IN6(n4212), .Q(\fpu_add_exp_dp/i_a4stg_exp_pre2/N12 ) );
INVX0 U4110 ( .INP(n4175), .ZN(n4267) );
OA21X1 U4111 ( .IN1(\fpu_add_exp_dp/n48 ), .IN2(n4268), .IN3(n4266), .Q(
n4175) );
NAND2X0 U4112 ( .IN1(\fpu_add_exp_dp/n48 ), .IN2(n4268), .QN(n4266) );
INVX0 U4113 ( .INP(n4269), .ZN(n4268) );
AO222X1 U4114 ( .IN1(n4252), .IN2(n71), .IN3(n4253), .IN4(n4270), .IN5(n1461), .IN6(n4172), .Q(\fpu_add_exp_dp/i_a4stg_exp_pre2/N11 ) );
INVX0 U4115 ( .INP(n4170), .ZN(n4270) );
OA21X1 U4116 ( .IN1(\fpu_add_exp_dp/n450 ), .IN2(n4271), .IN3(n4269), .Q(
n4170) );
NAND2X0 U4117 ( .IN1(\fpu_add_exp_dp/n450 ), .IN2(n4271), .QN(n4269) );
INVX0 U4118 ( .INP(n4272), .ZN(n4271) );
AO222X1 U4119 ( .IN1(n4253), .IN2(n4167), .IN3(n4252), .IN4(n256), .IN5(
n1461), .IN6(n4220), .Q(\fpu_add_exp_dp/i_a4stg_exp_pre2/N10 ) );
AND2X1 U4120 ( .IN1(n1337), .IN2(\fpu_add_ctl/a3stg_opdec_9_0[3] ), .Q(n4252) );
INVX0 U4121 ( .INP(n4162), .ZN(n4167) );
OA21X1 U4122 ( .IN1(n4255), .IN2(\fpu_add_exp_dp/n50 ), .IN3(n4272), .Q(
n4162) );
NAND2X0 U4123 ( .IN1(\fpu_add_exp_dp/n50 ), .IN2(n4255), .QN(n4272) );
NOR2X0 U4124 ( .IN1(n666), .IN2(n4254), .QN(n4255) );
AO22X1 U4125 ( .IN1(n4273), .IN2(n761), .IN3(\fpu_add_frac_dp/n593 ), .IN4(
n4274), .Q(n4254) );
NAND2X0 U4126 ( .IN1(\fpu_add_exp_dp/n441 ), .IN2(n4256), .QN(n4274) );
INVX0 U4127 ( .INP(n4256), .ZN(n4273) );
AO22X1 U4128 ( .IN1(\fpu_add_exp_dp/n440 ), .IN2(n4257), .IN3(n4275), .IN4(
n762), .Q(n4256) );
OR2X1 U4129 ( .IN1(n4257), .IN2(\fpu_add_exp_dp/n440 ), .Q(n4275) );
AO22X1 U4130 ( .IN1(\fpu_add_exp_dp/n439 ), .IN2(n4258), .IN3(n4276), .IN4(
n584), .Q(n4257) );
OR2X1 U4131 ( .IN1(n4258), .IN2(\fpu_add_exp_dp/n439 ), .Q(n4276) );
AO22X1 U4132 ( .IN1(\fpu_add_exp_dp/n438 ), .IN2(n4259), .IN3(n4277), .IN4(
n63), .Q(n4258) );
OR2X1 U4133 ( .IN1(n4259), .IN2(\fpu_add_exp_dp/n438 ), .Q(n4277) );
AO22X1 U4134 ( .IN1(n4260), .IN2(\fpu_add_exp_dp/n437 ), .IN3(n4278), .IN4(
n582), .Q(n4259) );
NAND2X0 U4135 ( .IN1(n643), .IN2(n4262), .QN(n4278) );
INVX0 U4136 ( .INP(n4262), .ZN(n4260) );
NAND2X0 U4137 ( .IN1(\fpu_add_exp_dp/n57 ), .IN2(n154), .QN(n4262) );
NOR3X0 U4138 ( .IN1(n642), .IN2(\fpu_add_frac_dp/n596 ), .IN3(n4057), .QN(
n4253) );
NOR3X0 U4139 ( .IN1(n4279), .IN2(n4280), .IN3(n4281), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N9 ) );
OA21X1 U4140 ( .IN1(\fpu_add_exp_dp/n433 ), .IN2(n4282), .IN3(
\fpu_add_exp_dp/n435 ), .Q(n4281) );
NOR2X0 U4141 ( .IN1(n4279), .IN2(n4283), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N8 ) );
XOR2X1 U4142 ( .IN1(n69), .IN2(n4282), .Q(n4283) );
NOR3X0 U4143 ( .IN1(n4279), .IN2(n4284), .IN3(n4285), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N7 ) );
OA21X1 U4144 ( .IN1(\fpu_add_exp_dp/n434 ), .IN2(n4286), .IN3(
\fpu_add_exp_dp/n432 ), .Q(n4285) );
NOR2X0 U4145 ( .IN1(n4279), .IN2(n4287), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N6 ) );
XOR2X1 U4146 ( .IN1(\fpu_add_exp_dp/n434 ), .IN2(n4288), .Q(n4287) );
NOR3X0 U4147 ( .IN1(n4279), .IN2(n4288), .IN3(n4289), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N5 ) );
OA21X1 U4148 ( .IN1(\fpu_add_exp_dp/n444 ), .IN2(\fpu_add_exp_dp/n436 ),
.IN3(\fpu_add_exp_dp/n431 ), .Q(n4289) );
OA21X1 U4149 ( .IN1(n4290), .IN2(\fpu_add_exp_dp/i_a4stg_exp_pre1/N3 ),
.IN3(n4238), .Q(\fpu_add_exp_dp/i_a4stg_exp_pre1/N4 ) );
NAND2X0 U4150 ( .IN1(\fpu_add_exp_dp/n444 ), .IN2(\fpu_add_exp_dp/n436 ),
.QN(n4238) );
NOR2X0 U4151 ( .IN1(n72), .IN2(n4279), .QN(n4290) );
NOR2X0 U4152 ( .IN1(n4279), .IN2(n583), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N3 ) );
NOR2X0 U4153 ( .IN1(n4279), .IN2(n4291), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N14 ) );
XOR2X1 U4154 ( .IN1(\fpu_add_exp_dp/n447 ), .IN2(n4292), .Q(n4291) );
NOR3X0 U4155 ( .IN1(n4279), .IN2(n4292), .IN3(n4293), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N13 ) );
OA21X1 U4156 ( .IN1(\fpu_add_exp_dp/n443 ), .IN2(n4294), .IN3(
\fpu_add_exp_dp/n446 ), .Q(n4293) );
NOR3X0 U4157 ( .IN1(\fpu_add_exp_dp/n443 ), .IN2(\fpu_add_exp_dp/n446 ),
.IN3(n4294), .QN(n4292) );
NOR2X0 U4158 ( .IN1(n4279), .IN2(n4295), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N12 ) );
XOR2X1 U4159 ( .IN1(n17), .IN2(n4294), .Q(n4295) );
NOR3X0 U4160 ( .IN1(n4279), .IN2(n4296), .IN3(n4297), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N11 ) );
OA21X1 U4161 ( .IN1(\fpu_add_exp_dp/n442 ), .IN2(n4298), .IN3(
\fpu_add_exp_dp/n445 ), .Q(n4297) );
INVX0 U4162 ( .INP(n4294), .ZN(n4296) );
NAND3X0 U4163 ( .IN1(n256), .IN2(n71), .IN3(n4280), .QN(n4294) );
NOR2X0 U4164 ( .IN1(n4279), .IN2(n4299), .QN(
\fpu_add_exp_dp/i_a4stg_exp_pre1/N10 ) );
XOR2X1 U4165 ( .IN1(\fpu_add_exp_dp/n442 ), .IN2(n4280), .Q(n4299) );
INVX0 U4166 ( .INP(n4298), .ZN(n4280) );
NAND3X0 U4167 ( .IN1(n69), .IN2(n160), .IN3(n4284), .QN(n4298) );
INVX0 U4168 ( .INP(n4282), .ZN(n4284) );
NAND3X0 U4169 ( .IN1(n67), .IN2(n178), .IN3(n4288), .QN(n4282) );
INVX0 U4170 ( .INP(n4286), .ZN(n4288) );
NAND3X0 U4171 ( .IN1(n72), .IN2(n583), .IN3(n159), .QN(n4286) );
NAND2X0 U4172 ( .IN1(n4226), .IN2(n3545), .QN(n4279) );
XNOR2X1 U4173 ( .IN1(\fpu_add_frac_dp/n569 ), .IN2(n4300), .Q(n3545) );
OA22X1 U4174 ( .IN1(n4301), .IN2(n453), .IN3(n753), .IN4(n4250), .Q(n4300)
);
AND2X1 U4175 ( .IN1(n4250), .IN2(n753), .Q(n4301) );
AO22X1 U4176 ( .IN1(n4251), .IN2(n359), .IN3(n4302), .IN4(n768), .Q(n4250)
);
OR2X1 U4177 ( .IN1(n359), .IN2(n4251), .Q(n4302) );
AO22X1 U4178 ( .IN1(n3207), .IN2(n360), .IN3(n4303), .IN4(n769), .Q(n4251)
);
OR2X1 U4179 ( .IN1(n360), .IN2(n3207), .Q(n4303) );
AO22X1 U4180 ( .IN1(n3209), .IN2(n361), .IN3(n4304), .IN4(n770), .Q(n3207)
);
OR2X1 U4181 ( .IN1(n361), .IN2(n3209), .Q(n4304) );
AO22X1 U4182 ( .IN1(n3221), .IN2(n362), .IN3(n4305), .IN4(n771), .Q(n3209)
);
OR2X1 U4183 ( .IN1(n362), .IN2(n3221), .Q(n4305) );
AO22X1 U4184 ( .IN1(n3241), .IN2(n363), .IN3(n4306), .IN4(n772), .Q(n3221)
);
OR2X1 U4185 ( .IN1(n363), .IN2(n3241), .Q(n4306) );
AO22X1 U4186 ( .IN1(n3244), .IN2(n364), .IN3(n4307), .IN4(n773), .Q(n3241)
);
OR2X1 U4187 ( .IN1(n364), .IN2(n3244), .Q(n4307) );
AO22X1 U4188 ( .IN1(n3265), .IN2(n365), .IN3(n4308), .IN4(n774), .Q(n3244)
);
OR2X1 U4189 ( .IN1(n365), .IN2(n3265), .Q(n4308) );
AO22X1 U4190 ( .IN1(n3273), .IN2(n366), .IN3(n4309), .IN4(n775), .Q(n3265)
);
OR2X1 U4191 ( .IN1(n366), .IN2(n3273), .Q(n4309) );
AO22X1 U4192 ( .IN1(n3281), .IN2(n367), .IN3(n4310), .IN4(n776), .Q(n3273)
);
OR2X1 U4193 ( .IN1(n367), .IN2(n3281), .Q(n4310) );
AO22X1 U4194 ( .IN1(n3286), .IN2(n368), .IN3(n4311), .IN4(n777), .Q(n3281)
);
OR2X1 U4195 ( .IN1(n368), .IN2(n3286), .Q(n4311) );
AO22X1 U4196 ( .IN1(n3291), .IN2(n369), .IN3(n4312), .IN4(n778), .Q(n3286)
);
OR2X1 U4197 ( .IN1(n369), .IN2(n3291), .Q(n4312) );
AO22X1 U4198 ( .IN1(n3296), .IN2(n370), .IN3(n4313), .IN4(n779), .Q(n3291)
);
OR2X1 U4199 ( .IN1(n370), .IN2(n3296), .Q(n4313) );
AO22X1 U4200 ( .IN1(n3309), .IN2(n371), .IN3(n4314), .IN4(n780), .Q(n3296)
);
OR2X1 U4201 ( .IN1(n371), .IN2(n3309), .Q(n4314) );
AO22X1 U4202 ( .IN1(n3315), .IN2(n372), .IN3(n4315), .IN4(n781), .Q(n3309)
);
OR2X1 U4203 ( .IN1(n372), .IN2(n3315), .Q(n4315) );
AO22X1 U4204 ( .IN1(n3323), .IN2(n373), .IN3(n4316), .IN4(n782), .Q(n3315)
);
OR2X1 U4205 ( .IN1(n373), .IN2(n3323), .Q(n4316) );
AO22X1 U4206 ( .IN1(n3329), .IN2(n374), .IN3(n4317), .IN4(n783), .Q(n3323)
);
OR2X1 U4207 ( .IN1(n374), .IN2(n3329), .Q(n4317) );
AO22X1 U4208 ( .IN1(n3335), .IN2(n375), .IN3(n4318), .IN4(n784), .Q(n3329)
);
OR2X1 U4209 ( .IN1(n375), .IN2(n3335), .Q(n4318) );
AO22X1 U4210 ( .IN1(n3341), .IN2(n376), .IN3(n4319), .IN4(n785), .Q(n3335)
);
OR2X1 U4211 ( .IN1(n376), .IN2(n3341), .Q(n4319) );
AO22X1 U4212 ( .IN1(n3347), .IN2(n377), .IN3(n4320), .IN4(n786), .Q(n3341)
);
OR2X1 U4213 ( .IN1(n377), .IN2(n3347), .Q(n4320) );
AO22X1 U4214 ( .IN1(n3353), .IN2(n378), .IN3(n4321), .IN4(n787), .Q(n3347)
);
OR2X1 U4215 ( .IN1(n378), .IN2(n3353), .Q(n4321) );
AO22X1 U4216 ( .IN1(n3359), .IN2(n379), .IN3(n4322), .IN4(n788), .Q(n3353)
);
OR2X1 U4217 ( .IN1(n379), .IN2(n3359), .Q(n4322) );
AO22X1 U4218 ( .IN1(n3365), .IN2(n380), .IN3(n4323), .IN4(n789), .Q(n3359)
);
OR2X1 U4219 ( .IN1(n380), .IN2(n3365), .Q(n4323) );
AO22X1 U4220 ( .IN1(n3371), .IN2(n381), .IN3(n4324), .IN4(n790), .Q(n3365)
);
OR2X1 U4221 ( .IN1(n381), .IN2(n3371), .Q(n4324) );
AO22X1 U4222 ( .IN1(n3377), .IN2(n382), .IN3(n4325), .IN4(n791), .Q(n3371)
);
OR2X1 U4223 ( .IN1(n382), .IN2(n3377), .Q(n4325) );
AO22X1 U4224 ( .IN1(n3383), .IN2(n383), .IN3(n4326), .IN4(n792), .Q(n3377)
);
OR2X1 U4225 ( .IN1(n383), .IN2(n3383), .Q(n4326) );
AO22X1 U4226 ( .IN1(n3389), .IN2(n384), .IN3(n4327), .IN4(n793), .Q(n3383)
);
OR2X1 U4227 ( .IN1(n384), .IN2(n3389), .Q(n4327) );
AO22X1 U4228 ( .IN1(n3395), .IN2(n385), .IN3(n4328), .IN4(n794), .Q(n3389)
);
OR2X1 U4229 ( .IN1(n385), .IN2(n3395), .Q(n4328) );
AO22X1 U4230 ( .IN1(n3401), .IN2(n386), .IN3(n4329), .IN4(n795), .Q(n3395)
);
OR2X1 U4231 ( .IN1(n386), .IN2(n3401), .Q(n4329) );
AO22X1 U4232 ( .IN1(n3407), .IN2(n387), .IN3(n4330), .IN4(n796), .Q(n3401)
);
OR2X1 U4233 ( .IN1(n387), .IN2(n3407), .Q(n4330) );
AO22X1 U4234 ( .IN1(n3413), .IN2(n388), .IN3(n4331), .IN4(n797), .Q(n3407)
);
OR2X1 U4235 ( .IN1(n388), .IN2(n3413), .Q(n4331) );
AO22X1 U4236 ( .IN1(n3419), .IN2(n389), .IN3(n4332), .IN4(n798), .Q(n3413)
);
OR2X1 U4237 ( .IN1(n389), .IN2(n3419), .Q(n4332) );
AO22X1 U4238 ( .IN1(n3425), .IN2(n390), .IN3(n4333), .IN4(n799), .Q(n3419)
);
OR2X1 U4239 ( .IN1(n390), .IN2(n3425), .Q(n4333) );
AO22X1 U4240 ( .IN1(n3431), .IN2(n391), .IN3(n4334), .IN4(n800), .Q(n3425)
);
OR2X1 U4241 ( .IN1(n391), .IN2(n3431), .Q(n4334) );
AO22X1 U4242 ( .IN1(n3437), .IN2(n392), .IN3(n4335), .IN4(n801), .Q(n3431)
);
OR2X1 U4243 ( .IN1(n392), .IN2(n3437), .Q(n4335) );
AO22X1 U4244 ( .IN1(n3443), .IN2(n393), .IN3(n4336), .IN4(n802), .Q(n3437)
);
OR2X1 U4245 ( .IN1(n393), .IN2(n3443), .Q(n4336) );
AO22X1 U4246 ( .IN1(n3450), .IN2(n394), .IN3(n4337), .IN4(n803), .Q(n3443)
);
OR2X1 U4247 ( .IN1(n394), .IN2(n3450), .Q(n4337) );
AO22X1 U4248 ( .IN1(n3456), .IN2(n395), .IN3(n4338), .IN4(n804), .Q(n3450)
);
OR2X1 U4249 ( .IN1(n395), .IN2(n3456), .Q(n4338) );
AO22X1 U4250 ( .IN1(n3462), .IN2(n396), .IN3(n4339), .IN4(n805), .Q(n3456)
);
OR2X1 U4251 ( .IN1(n396), .IN2(n3462), .Q(n4339) );
AO22X1 U4252 ( .IN1(n3468), .IN2(n397), .IN3(n4340), .IN4(n806), .Q(n3462)
);
OR2X1 U4253 ( .IN1(n397), .IN2(n3468), .Q(n4340) );
AO22X1 U4254 ( .IN1(n3474), .IN2(n398), .IN3(n4341), .IN4(n807), .Q(n3468)
);
OR2X1 U4255 ( .IN1(n398), .IN2(n3474), .Q(n4341) );
AO22X1 U4256 ( .IN1(n3480), .IN2(n399), .IN3(n4342), .IN4(n808), .Q(n3474)
);
OR2X1 U4257 ( .IN1(n399), .IN2(n3480), .Q(n4342) );
AO22X1 U4258 ( .IN1(n3486), .IN2(n400), .IN3(n4343), .IN4(n809), .Q(n3480)
);
OR2X1 U4259 ( .IN1(n400), .IN2(n3486), .Q(n4343) );
AO22X1 U4260 ( .IN1(n3492), .IN2(n401), .IN3(n4344), .IN4(n810), .Q(n3486)
);
OR2X1 U4261 ( .IN1(n401), .IN2(n3492), .Q(n4344) );
AO22X1 U4262 ( .IN1(n3495), .IN2(n402), .IN3(n4345), .IN4(n811), .Q(n3492)
);
OR2X1 U4263 ( .IN1(n402), .IN2(n3495), .Q(n4345) );
AO22X1 U4264 ( .IN1(n3497), .IN2(n403), .IN3(n4346), .IN4(n812), .Q(n3495)
);
OR2X1 U4265 ( .IN1(n403), .IN2(n3497), .Q(n4346) );
AO22X1 U4266 ( .IN1(n3505), .IN2(n404), .IN3(n4347), .IN4(n813), .Q(n3497)
);
OR2X1 U4267 ( .IN1(n404), .IN2(n3505), .Q(n4347) );
AO22X1 U4268 ( .IN1(n3515), .IN2(n405), .IN3(n4348), .IN4(n814), .Q(n3505)
);
OR2X1 U4269 ( .IN1(n405), .IN2(n3515), .Q(n4348) );
AO22X1 U4270 ( .IN1(n3521), .IN2(n406), .IN3(n4349), .IN4(n815), .Q(n3515)
);
OR2X1 U4271 ( .IN1(n406), .IN2(n3521), .Q(n4349) );
AO22X1 U4272 ( .IN1(n3525), .IN2(n407), .IN3(n4350), .IN4(n816), .Q(n3521)
);
OR2X1 U4273 ( .IN1(n407), .IN2(n3525), .Q(n4350) );
AO22X1 U4274 ( .IN1(n3530), .IN2(n408), .IN3(n4351), .IN4(n817), .Q(n3525)
);
OR2X1 U4275 ( .IN1(n408), .IN2(n3530), .Q(n4351) );
AO22X1 U4276 ( .IN1(n3537), .IN2(n409), .IN3(n4352), .IN4(n818), .Q(n3530)
);
OR2X1 U4277 ( .IN1(n409), .IN2(n3537), .Q(n4352) );
AO22X1 U4278 ( .IN1(n3548), .IN2(n410), .IN3(n4353), .IN4(n819), .Q(n3537)
);
OR2X1 U4279 ( .IN1(n410), .IN2(n3548), .Q(n4353) );
AO22X1 U4280 ( .IN1(n3544), .IN2(n411), .IN3(n4354), .IN4(n820), .Q(n3548)
);
OR2X1 U4281 ( .IN1(n411), .IN2(n3544), .Q(n4354) );
AO22X1 U4282 ( .IN1(n3137), .IN2(n412), .IN3(n4355), .IN4(n821), .Q(n3544)
);
OR2X1 U4283 ( .IN1(n412), .IN2(n3137), .Q(n4355) );
AO22X1 U4284 ( .IN1(n3138), .IN2(n413), .IN3(n4356), .IN4(n822), .Q(n3137)
);
OR2X1 U4285 ( .IN1(n413), .IN2(n3138), .Q(n4356) );
AO22X1 U4286 ( .IN1(n3148), .IN2(n414), .IN3(n4357), .IN4(n823), .Q(n3138)
);
OR2X1 U4287 ( .IN1(n414), .IN2(n3148), .Q(n4357) );
AO22X1 U4288 ( .IN1(n3151), .IN2(n415), .IN3(n4358), .IN4(n824), .Q(n3148)
);
OR2X1 U4289 ( .IN1(n415), .IN2(n3151), .Q(n4358) );
AO22X1 U4290 ( .IN1(n3150), .IN2(n416), .IN3(n4359), .IN4(n825), .Q(n3151)
);
OR2X1 U4291 ( .IN1(n416), .IN2(n3150), .Q(n4359) );
AO22X1 U4292 ( .IN1(n3080), .IN2(n417), .IN3(n4360), .IN4(n826), .Q(n3150)
);
OR2X1 U4293 ( .IN1(n417), .IN2(n3080), .Q(n4360) );
AO22X1 U4294 ( .IN1(n3087), .IN2(n418), .IN3(n4361), .IN4(n827), .Q(n3080)
);
OR2X1 U4295 ( .IN1(n418), .IN2(n3087), .Q(n4361) );
AO22X1 U4296 ( .IN1(n3098), .IN2(n419), .IN3(n4362), .IN4(n828), .Q(n3087)
);
OR2X1 U4297 ( .IN1(n419), .IN2(n3098), .Q(n4362) );
AO22X1 U4298 ( .IN1(n139), .IN2(n852), .IN3(n4363), .IN4(n465), .Q(n3098) );
NAND2X0 U4299 ( .IN1(\fpu_add_frac_dp/n598 ), .IN2(\fpu_add_frac_dp/n509 ),
.QN(n4363) );
NOR2X0 U4300 ( .IN1(n4057), .IN2(\fpu_add_ctl/n142 ), .QN(n4226) );
NAND2X0 U4301 ( .IN1(fadd_clken_l), .IN2(\fpu_add_ctl/n470 ), .QN(
\fpu_add_exp_dp/ckbuf_add_exp_dp/N1 ) );
AO22X1 U4302 ( .IN1(n4364), .IN2(inq_op[7]), .IN3(n4365), .IN4(
\fpu_add_ctl/n314 ), .Q(\fpu_add_ctl/n752 ) );
AO22X1 U4303 ( .IN1(inq_op[6]), .IN2(n4364), .IN3(n4365), .IN4(
\fpu_add_ctl/n312 ), .Q(\fpu_add_ctl/n751 ) );
AO22X1 U4304 ( .IN1(inq_op[5]), .IN2(n4364), .IN3(n4365), .IN4(n84), .Q(
\fpu_add_ctl/n750 ) );
AO22X1 U4305 ( .IN1(inq_op[4]), .IN2(n4364), .IN3(n4365), .IN4(n585), .Q(
\fpu_add_ctl/n749 ) );
AO22X1 U4306 ( .IN1(inq_op[3]), .IN2(n4364), .IN3(n4365), .IN4(n595), .Q(
\fpu_add_ctl/n748 ) );
AO22X1 U4307 ( .IN1(inq_op[2]), .IN2(n4364), .IN3(n4365), .IN4(n18), .Q(
\fpu_add_ctl/n747 ) );
AO22X1 U4308 ( .IN1(n4364), .IN2(inq_op[1]), .IN3(n4365), .IN4(n829), .Q(
\fpu_add_ctl/n746 ) );
AO22X1 U4309 ( .IN1(n4364), .IN2(inq_op[0]), .IN3(n4365), .IN4(
\fpu_add_ctl/n320 ), .Q(\fpu_add_ctl/n745 ) );
NOR2X0 U4310 ( .IN1(n3986), .IN2(\fpu_add_ctl/n210 ), .QN(n4365) );
AND2X1 U4311 ( .IN1(inq_add), .IN2(\fpu_add_ctl/n47 ), .Q(n4364) );
AO22X1 U4312 ( .IN1(inq_fcc[1]), .IN2(n4366), .IN3(n1458), .IN4(n1011), .Q(
\fpu_add_ctl/n744 ) );
AO22X1 U4313 ( .IN1(inq_fcc[0]), .IN2(n4366), .IN3(n1457), .IN4(n1010), .Q(
\fpu_add_ctl/n743 ) );
AO22X1 U4314 ( .IN1(n1337), .IN2(n1010), .IN3(n1468), .IN4(n563), .Q(
\fpu_add_ctl/n742 ) );
AO22X1 U4315 ( .IN1(n1339), .IN2(n1011), .IN3(n1468), .IN4(n564), .Q(
\fpu_add_ctl/n741 ) );
AO22X1 U4316 ( .IN1(n1338), .IN2(n563), .IN3(n1468), .IN4(n1012), .Q(
\fpu_add_ctl/n740 ) );
AO22X1 U4317 ( .IN1(n1340), .IN2(n564), .IN3(n1468), .IN4(n1013), .Q(
\fpu_add_ctl/n739 ) );
AO22X1 U4318 ( .IN1(n1337), .IN2(n1012), .IN3(n1468), .IN4(n554), .Q(
\fpu_add_ctl/n738 ) );
AO22X1 U4319 ( .IN1(n1339), .IN2(n1013), .IN3(n1468), .IN4(n555), .Q(
\fpu_add_ctl/n737 ) );
AO22X1 U4320 ( .IN1(inq_id[4]), .IN2(n4366), .IN3(n1458), .IN4(n566), .Q(
\fpu_add_ctl/n736 ) );
AO22X1 U4321 ( .IN1(inq_id[3]), .IN2(n4366), .IN3(n1457), .IN4(n565), .Q(
\fpu_add_ctl/n735 ) );
AO22X1 U4322 ( .IN1(inq_id[2]), .IN2(n4366), .IN3(n1458), .IN4(n1216), .Q(
\fpu_add_ctl/n734 ) );
AO22X1 U4323 ( .IN1(inq_id[1]), .IN2(n4366), .IN3(n1457), .IN4(n1015), .Q(
\fpu_add_ctl/n733 ) );
AO22X1 U4324 ( .IN1(inq_id[0]), .IN2(n4366), .IN3(n1458), .IN4(n1014), .Q(
\fpu_add_ctl/n732 ) );
AO22X1 U4325 ( .IN1(n1338), .IN2(n1014), .IN3(n1468), .IN4(n567), .Q(
\fpu_add_ctl/n731 ) );
AO22X1 U4326 ( .IN1(n1340), .IN2(n1015), .IN3(n1468), .IN4(n568), .Q(
\fpu_add_ctl/n730 ) );
OAI22X1 U4327 ( .IN1(n4057), .IN2(\fpu_add_ctl/n183 ), .IN3(n4114), .IN4(
\fpu_add_ctl/n182 ), .QN(\fpu_add_ctl/n729 ) );
AO22X1 U4328 ( .IN1(n1337), .IN2(n565), .IN3(n1468), .IN4(n1016), .Q(
\fpu_add_ctl/n728 ) );
AO22X1 U4329 ( .IN1(n1339), .IN2(n566), .IN3(n1468), .IN4(n1017), .Q(
\fpu_add_ctl/n727 ) );
AO22X1 U4330 ( .IN1(n1338), .IN2(n567), .IN3(n1468), .IN4(n1018), .Q(
\fpu_add_ctl/n726 ) );
AO22X1 U4331 ( .IN1(n1340), .IN2(n568), .IN3(n1468), .IN4(n1019), .Q(
\fpu_add_ctl/n725 ) );
OAI22X1 U4332 ( .IN1(n4057), .IN2(\fpu_add_ctl/n182 ), .IN3(n4114), .IN4(
\fpu_add_ctl/n326 ), .QN(\fpu_add_ctl/n724 ) );
AO22X1 U4333 ( .IN1(n1337), .IN2(n1016), .IN3(n1468), .IN4(n269), .Q(
\fpu_add_ctl/n723 ) );
AO22X1 U4334 ( .IN1(n1339), .IN2(n1017), .IN3(n1469), .IN4(n89), .Q(
\fpu_add_ctl/n722 ) );
AO22X1 U4335 ( .IN1(n1338), .IN2(n1018), .IN3(n1469), .IN4(n342), .Q(
\fpu_add_ctl/n721 ) );
AO22X1 U4336 ( .IN1(n1340), .IN2(n1019), .IN3(n1469), .IN4(n341), .Q(
\fpu_add_ctl/n720 ) );
AO22X1 U4337 ( .IN1(n1472), .IN2(n354), .IN3(n4367), .IN4(\fpu_add_ctl/n308 ), .Q(\fpu_add_ctl/n719 ) );
NOR2X0 U4338 ( .IN1(n4368), .IN2(n89), .QN(n4367) );
AO22X1 U4339 ( .IN1(n1472), .IN2(n353), .IN3(n4369), .IN4(n4370), .Q(
\fpu_add_ctl/n718 ) );
NOR2X0 U4340 ( .IN1(n89), .IN2(n269), .QN(n4369) );
AO22X1 U4341 ( .IN1(n1472), .IN2(n352), .IN3(n4371), .IN4(\fpu_add_ctl/n177 ), .Q(\fpu_add_ctl/n717 ) );
NOR2X0 U4342 ( .IN1(\fpu_add_ctl/n308 ), .IN2(n4368), .QN(n4371) );
AO22X1 U4343 ( .IN1(n1472), .IN2(n351), .IN3(n4372), .IN4(n4370), .Q(
\fpu_add_ctl/n716 ) );
NOR2X0 U4344 ( .IN1(\fpu_add_ctl/n308 ), .IN2(n89), .QN(n4372) );
AO22X1 U4345 ( .IN1(n1472), .IN2(n350), .IN3(n4373), .IN4(\fpu_add_ctl/n308 ), .Q(\fpu_add_ctl/n715 ) );
NOR2X0 U4346 ( .IN1(\fpu_add_ctl/n177 ), .IN2(n4368), .QN(n4373) );
AO22X1 U4347 ( .IN1(n1472), .IN2(n349), .IN3(n4374), .IN4(n4370), .Q(
\fpu_add_ctl/n714 ) );
NOR2X0 U4348 ( .IN1(\fpu_add_ctl/n177 ), .IN2(n269), .QN(n4374) );
AO22X1 U4349 ( .IN1(n4000), .IN2(n348), .IN3(n4375), .IN4(n4376), .Q(
\fpu_add_ctl/n713 ) );
INVX0 U4350 ( .INP(n4368), .ZN(n4376) );
NAND2X0 U4351 ( .IN1(\fpu_add_ctl/n326 ), .IN2(n1337), .QN(n4368) );
AO22X1 U4352 ( .IN1(n1472), .IN2(n347), .IN3(n4375), .IN4(n4370), .Q(
\fpu_add_ctl/n712 ) );
NOR2X0 U4353 ( .IN1(n4057), .IN2(\fpu_add_ctl/n326 ), .QN(n4370) );
NOR2X0 U4354 ( .IN1(\fpu_add_ctl/n308 ), .IN2(\fpu_add_ctl/n177 ), .QN(n4375) );
AO22X1 U4355 ( .IN1(n1337), .IN2(n342), .IN3(n1469), .IN4(n894), .Q(
\fpu_add_ctl/n711 ) );
AO22X1 U4356 ( .IN1(n1339), .IN2(n341), .IN3(n1469), .IN4(n893), .Q(
\fpu_add_ctl/n710 ) );
AO22X1 U4357 ( .IN1(n1338), .IN2(n354), .IN3(n1469), .IN4(n892), .Q(
\fpu_add_ctl/n709 ) );
AO22X1 U4358 ( .IN1(n1340), .IN2(n353), .IN3(n1469), .IN4(n891), .Q(
\fpu_add_ctl/n708 ) );
AO22X1 U4359 ( .IN1(n1337), .IN2(n352), .IN3(n1469), .IN4(n890), .Q(
\fpu_add_ctl/n707 ) );
AO22X1 U4360 ( .IN1(n1339), .IN2(n351), .IN3(n1469), .IN4(n889), .Q(
\fpu_add_ctl/n706 ) );
AO22X1 U4361 ( .IN1(n1338), .IN2(n350), .IN3(n1469), .IN4(n888), .Q(
\fpu_add_ctl/n705 ) );
AO22X1 U4362 ( .IN1(n1340), .IN2(n349), .IN3(n1469), .IN4(n887), .Q(
\fpu_add_ctl/n704 ) );
AO22X1 U4363 ( .IN1(n1337), .IN2(n348), .IN3(n1470), .IN4(n886), .Q(
\fpu_add_ctl/n703 ) );
AO22X1 U4364 ( .IN1(n1339), .IN2(n347), .IN3(n1470), .IN4(n885), .Q(
\fpu_add_ctl/n702 ) );
AO22X1 U4365 ( .IN1(inq_rnd_mode[1]), .IN2(n4366), .IN3(n1458), .IN4(n1021),
.Q(\fpu_add_ctl/n701 ) );
AO22X1 U4366 ( .IN1(inq_rnd_mode[0]), .IN2(n4366), .IN3(n1458), .IN4(n1020),
.Q(\fpu_add_ctl/n700 ) );
AO22X1 U4367 ( .IN1(n1338), .IN2(n1020), .IN3(n1470), .IN4(n505), .Q(
\fpu_add_ctl/n699 ) );
AO22X1 U4368 ( .IN1(n1340), .IN2(n1021), .IN3(n1470), .IN4(n504), .Q(
\fpu_add_ctl/n698 ) );
AO22X1 U4369 ( .IN1(n1337), .IN2(n505), .IN3(n1470), .IN4(n146), .Q(
\fpu_add_ctl/n697 ) );
AO22X1 U4370 ( .IN1(n1339), .IN2(n504), .IN3(n1470), .IN4(n147), .Q(
\fpu_add_ctl/n696 ) );
AO22X1 U4371 ( .IN1(n1338), .IN2(n146), .IN3(n1470), .IN4(n882), .Q(
\fpu_add_ctl/n695 ) );
AO22X1 U4372 ( .IN1(n1340), .IN2(n147), .IN3(n1470), .IN4(n883), .Q(
\fpu_add_ctl/n694 ) );
AO21X1 U4373 ( .IN1(n1457), .IN2(n915), .IN3(n4377), .Q(\fpu_add_ctl/n693 )
);
AO21X1 U4374 ( .IN1(n1457), .IN2(n325), .IN3(n4377), .Q(\fpu_add_ctl/n692 )
);
AO21X1 U4375 ( .IN1(n1457), .IN2(n44), .IN3(n4377), .Q(\fpu_add_ctl/n691 )
);
AO21X1 U4376 ( .IN1(n1457), .IN2(n700), .IN3(n4377), .Q(\fpu_add_ctl/n690 )
);
AO21X1 U4377 ( .IN1(n1457), .IN2(n295), .IN3(n4377), .Q(\fpu_add_ctl/n689 )
);
AND2X1 U4378 ( .IN1(n4366), .IN2(inq_op[1]), .Q(n4377) );
AO21X1 U4379 ( .IN1(n1333), .IN2(n849), .IN3(n4378), .Q(\fpu_add_ctl/n688 )
);
AO21X1 U4380 ( .IN1(n1334), .IN2(n1001), .IN3(n4379), .Q(\fpu_add_ctl/n687 )
);
AO21X1 U4381 ( .IN1(n1335), .IN2(n560), .IN3(n4380), .Q(\fpu_add_ctl/n686 )
);
AO22X1 U4382 ( .IN1(n1333), .IN2(n570), .IN3(\fpu_add_ctl/n47 ), .IN4(n1658),
.Q(\fpu_add_ctl/n685 ) );
INVX0 U4383 ( .INP(n4056), .ZN(n1658) );
AO22X1 U4384 ( .IN1(n1335), .IN2(n571), .IN3(\fpu_add_ctl/n47 ), .IN4(n4381),
.Q(\fpu_add_ctl/n684 ) );
NAND2X0 U4385 ( .IN1(n4070), .IN2(n4046), .QN(n4381) );
NAND3X0 U4386 ( .IN1(n4382), .IN2(n4383), .IN3(n4384), .QN(
\fpu_add_ctl/n683 ) );
NAND2X0 U4387 ( .IN1(n1335), .IN2(n355), .QN(n4384) );
INVX0 U4388 ( .INP(n4378), .ZN(n4383) );
NOR2X0 U4389 ( .IN1(n4385), .IN2(\fpu_add_ctl/n312 ), .QN(n4378) );
AO221X1 U4390 ( .IN1(\fpu_add_ctl/n47 ), .IN2(n2719), .IN3(n1336), .IN4(n858), .IN5(n4380), .Q(\fpu_add_ctl/n682 ) );
AO22X1 U4391 ( .IN1(n1336), .IN2(n511), .IN3(n4386), .IN4(\fpu_add_ctl/n47 ),
.Q(\fpu_add_ctl/n681 ) );
AO22X1 U4392 ( .IN1(n1334), .IN2(n757), .IN3(n4379), .IN4(n254), .Q(
\fpu_add_ctl/n680 ) );
AO22X1 U4393 ( .IN1(n1333), .IN2(n718), .IN3(n4380), .IN4(n158), .Q(
\fpu_add_ctl/n679 ) );
INVX0 U4394 ( .INP(n4387), .ZN(n4380) );
AO22X1 U4395 ( .IN1(n1335), .IN2(n421), .IN3(n4379), .IN4(\fpu_add_ctl/n312 ), .Q(\fpu_add_ctl/n678 ) );
INVX0 U4396 ( .INP(n4382), .ZN(n4379) );
AO22X1 U4397 ( .IN1(n1336), .IN2(n128), .IN3(\fpu_add_ctl/n47 ), .IN4(n4388),
.Q(\fpu_add_ctl/n677 ) );
NAND2X0 U4398 ( .IN1(n4070), .IN2(n4058), .QN(n4388) );
INVX0 U4399 ( .INP(a1stg_fsdtoix), .ZN(n4058) );
AO22X1 U4400 ( .IN1(n1334), .IN2(n1076), .IN3(n4072), .IN4(\fpu_add_ctl/n47 ), .Q(\fpu_add_ctl/n676 ) );
NOR2X0 U4401 ( .IN1(n4389), .IN2(n4390), .QN(n4072) );
AO22X1 U4402 ( .IN1(n1333), .IN2(n553), .IN3(\fpu_add_ctl/n47 ), .IN4(n4060),
.Q(\fpu_add_ctl/n675 ) );
NOR2X0 U4403 ( .IN1(n4391), .IN2(n4390), .QN(n4060) );
AO22X1 U4404 ( .IN1(n1335), .IN2(n569), .IN3(\fpu_add_ctl/n47 ), .IN4(n4068),
.Q(\fpu_add_ctl/n674 ) );
NOR2X0 U4405 ( .IN1(n4392), .IN2(n4389), .QN(n4068) );
AO22X1 U4406 ( .IN1(n1336), .IN2(n1022), .IN3(\fpu_add_ctl/n47 ), .IN4(n4069), .Q(\fpu_add_ctl/n673 ) );
NOR2X0 U4407 ( .IN1(n4391), .IN2(n4392), .QN(n4069) );
AO22X1 U4408 ( .IN1(n1334), .IN2(n258), .IN3(n4048), .IN4(\fpu_add_ctl/n47 ),
.Q(\fpu_add_ctl/n672 ) );
AO22X1 U4409 ( .IN1(n1333), .IN2(n547), .IN3(n4393), .IN4(\fpu_add_ctl/n47 ),
.Q(\fpu_add_ctl/n671 ) );
NOR2X0 U4410 ( .IN1(n4394), .IN2(n4392), .QN(n4393) );
AO22X1 U4411 ( .IN1(n1335), .IN2(n1008), .IN3(n4395), .IN4(\fpu_add_ctl/n47 ), .Q(\fpu_add_ctl/n670 ) );
NOR2X0 U4412 ( .IN1(n4394), .IN2(n4390), .QN(n4395) );
AO22X1 U4413 ( .IN1(n1336), .IN2(n356), .IN3(\fpu_add_ctl/n47 ), .IN4(n2719),
.Q(\fpu_add_ctl/n669 ) );
AO22X1 U4414 ( .IN1(n1334), .IN2(n1187), .IN3(\fpu_add_ctl/n47 ), .IN4(n4396), .Q(\fpu_add_ctl/n668 ) );
AO22X1 U4415 ( .IN1(n1333), .IN2(n640), .IN3(\fpu_add_ctl/n47 ), .IN4(n1737),
.Q(\fpu_add_ctl/n667 ) );
AO21X1 U4416 ( .IN1(n1336), .IN2(n1233), .IN3(n4397), .Q(\fpu_add_ctl/n666 )
);
AO21X1 U4417 ( .IN1(n1333), .IN2(n1218), .IN3(n4397), .Q(\fpu_add_ctl/n665 )
);
OAI21X1 U4418 ( .IN1(\fpu_add_ctl/n144 ), .IN2(n586), .IN3(n4398), .QN(
\fpu_add_ctl/n664 ) );
NAND4X0 U4419 ( .IN1(n4399), .IN2(\fpu_add_ctl/n318 ), .IN3(n4400), .IN4(
n585), .QN(n4398) );
AO22X1 U4420 ( .IN1(n1335), .IN2(n506), .IN3(\fpu_add_ctl/n47 ), .IN4(n2668),
.Q(\fpu_add_ctl/n663 ) );
NAND3X0 U4421 ( .IN1(n4401), .IN2(n4382), .IN3(n4402), .QN(
\fpu_add_ctl/n662 ) );
OA22X1 U4422 ( .IN1(n4046), .IN2(n4403), .IN3(\fpu_add_ctl/n138 ), .IN4(n586), .Q(n4402) );
NAND4X0 U4423 ( .IN1(n4404), .IN2(\fpu_add_ctl/n47 ), .IN3(n4405), .IN4(n158), .QN(n4382) );
NAND4X0 U4424 ( .IN1(n4399), .IN2(\fpu_add_ctl/n303 ), .IN3(n18), .IN4(n158),
.QN(n4401) );
AND3X1 U4425 ( .IN1(n4406), .IN2(\fpu_add_ctl/n314 ), .IN3(\fpu_add_ctl/n47 ), .Q(n4399) );
NAND3X0 U4426 ( .IN1(n4387), .IN2(n4385), .IN3(n4407), .QN(
\fpu_add_ctl/n661 ) );
OA22X1 U4427 ( .IN1(n4056), .IN2(n4403), .IN3(\fpu_add_ctl/n113 ), .IN4(n586), .Q(n4407) );
NAND2X0 U4428 ( .IN1(n4408), .IN2(n4409), .QN(n4056) );
NAND4X0 U4429 ( .IN1(\fpu_add_ctl/n47 ), .IN2(n4410), .IN3(n4405), .IN4(n158), .QN(n4385) );
NAND4X0 U4430 ( .IN1(\fpu_add_ctl/n47 ), .IN2(n4410), .IN3(n4405), .IN4(
\fpu_add_ctl/n312 ), .QN(n4387) );
AO22X1 U4431 ( .IN1(n1336), .IN2(n651), .IN3(\fpu_add_ctl/n47 ), .IN4(n4411),
.Q(\fpu_add_ctl/n660 ) );
AO22X1 U4432 ( .IN1(n1334), .IN2(n1023), .IN3(\fpu_add_ctl/n47 ), .IN4(n295),
.Q(\fpu_add_ctl/n659 ) );
AO22X1 U4433 ( .IN1(n1333), .IN2(n572), .IN3(\fpu_add_ctl/n49 ), .IN4(n849),
.Q(\fpu_add_ctl/n658 ) );
AO22X1 U4434 ( .IN1(n1335), .IN2(n573), .IN3(\fpu_add_ctl/n49 ), .IN4(n1001),
.Q(\fpu_add_ctl/n657 ) );
AO22X1 U4435 ( .IN1(n1336), .IN2(n1024), .IN3(\fpu_add_ctl/n49 ), .IN4(n560),
.Q(\fpu_add_ctl/n656 ) );
AO22X1 U4436 ( .IN1(\fpu_add_ctl/a3stg_opdec_9_0[3] ), .IN2(n1336), .IN3(
\fpu_add_ctl/n49 ), .IN4(n91), .Q(\fpu_add_ctl/n655 ) );
AO22X1 U4437 ( .IN1(n1334), .IN2(n1025), .IN3(\fpu_add_ctl/n49 ), .IN4(n570),
.Q(\fpu_add_ctl/n654 ) );
AO22X1 U4438 ( .IN1(n1333), .IN2(n1026), .IN3(\fpu_add_ctl/n49 ), .IN4(n562),
.Q(\fpu_add_ctl/n653 ) );
AO22X1 U4439 ( .IN1(n1335), .IN2(n1027), .IN3(\fpu_add_ctl/n49 ), .IN4(n571),
.Q(\fpu_add_ctl/n652 ) );
AO22X1 U4440 ( .IN1(n1336), .IN2(n895), .IN3(\fpu_add_ctl/n49 ), .IN4(n355),
.Q(\fpu_add_ctl/n651 ) );
AO22X1 U4441 ( .IN1(n1334), .IN2(n455), .IN3(\fpu_add_ctl/n49 ), .IN4(n858),
.Q(\fpu_add_ctl/n650 ) );
AO222X1 U4442 ( .IN1(n4412), .IN2(n146), .IN3(n4413), .IN4(n882), .IN5(n1461), .IN6(\fpu_add_ctl/n307 ), .Q(\fpu_add_ctl/n649 ) );
AO222X1 U4443 ( .IN1(n4412), .IN2(n147), .IN3(n4413), .IN4(n883), .IN5(n1461), .IN6(n291), .Q(\fpu_add_ctl/n648 ) );
AO22X1 U4444 ( .IN1(n1333), .IN2(n1028), .IN3(\fpu_add_ctl/n49 ), .IN4(n511),
.Q(\fpu_add_ctl/n647 ) );
AO22X1 U4445 ( .IN1(n1335), .IN2(n336), .IN3(\fpu_add_ctl/n49 ), .IN4(
\fpu_add_ctl/n329 ), .Q(\fpu_add_ctl/n646 ) );
AO22X1 U4446 ( .IN1(n1336), .IN2(n1029), .IN3(\fpu_add_ctl/n49 ), .IN4(n356),
.Q(\fpu_add_ctl/n645 ) );
AO21X1 U4447 ( .IN1(n1333), .IN2(n133), .IN3(n4397), .Q(\fpu_add_ctl/n644 )
);
AND2X1 U4448 ( .IN1(\fpu_add_ctl/n49 ), .IN2(n640), .Q(n4397) );
AO22X1 U4449 ( .IN1(n1334), .IN2(n549), .IN3(\fpu_add_ctl/n49 ), .IN4(n1214),
.Q(\fpu_add_ctl/n643 ) );
AO22X1 U4450 ( .IN1(n1333), .IN2(n1030), .IN3(\fpu_add_ctl/n49 ), .IN4(n506),
.Q(\fpu_add_ctl/n642 ) );
AO22X1 U4451 ( .IN1(n1335), .IN2(n574), .IN3(\fpu_add_ctl/n49 ), .IN4(n1200),
.Q(\fpu_add_ctl/n641 ) );
AO22X1 U4452 ( .IN1(n1336), .IN2(n575), .IN3(\fpu_add_ctl/n49 ), .IN4(n1201),
.Q(\fpu_add_ctl/n640 ) );
AO22X1 U4453 ( .IN1(\fpu_add_ctl/n325 ), .IN2(n1334), .IN3(\fpu_add_ctl/n49 ), .IN4(n651), .Q(\fpu_add_ctl/n639 ) );
AO22X1 U4454 ( .IN1(n1334), .IN2(n576), .IN3(\fpu_add_ctl/n49 ), .IN4(n1023),
.Q(\fpu_add_ctl/n638 ) );
AO22X1 U4455 ( .IN1(n1333), .IN2(n1031), .IN3(\fpu_add_ctl/n49 ), .IN4(n572),
.Q(\fpu_add_ctl/n637 ) );
AO22X1 U4456 ( .IN1(n1335), .IN2(n1032), .IN3(\fpu_add_ctl/n49 ), .IN4(n573),
.Q(\fpu_add_ctl/n636 ) );
AO22X1 U4457 ( .IN1(n1336), .IN2(n492), .IN3(\fpu_add_ctl/n49 ), .IN4(n1024),
.Q(\fpu_add_ctl/n635 ) );
AO22X1 U4458 ( .IN1(n1334), .IN2(n55), .IN3(\fpu_add_ctl/n49 ), .IN4(
\fpu_add_ctl/a3stg_opdec_9_0[3] ), .Q(\fpu_add_ctl/n634 ) );
AO22X1 U4459 ( .IN1(n1333), .IN2(n21), .IN3(\fpu_add_ctl/n49 ), .IN4(n1025),
.Q(\fpu_add_ctl/n633 ) );
AO22X1 U4460 ( .IN1(n1335), .IN2(n148), .IN3(\fpu_add_ctl/n49 ), .IN4(n1026),
.Q(\fpu_add_ctl/n632 ) );
AO22X1 U4461 ( .IN1(n1336), .IN2(n420), .IN3(\fpu_add_ctl/n49 ), .IN4(n1027),
.Q(\fpu_add_ctl/n631 ) );
AO22X1 U4462 ( .IN1(\fpu_add_ctl/n319 ), .IN2(n1333), .IN3(\fpu_add_ctl/n49 ), .IN4(n895), .Q(\fpu_add_ctl/n630 ) );
AO22X1 U4463 ( .IN1(n1334), .IN2(n324), .IN3(\fpu_add_ctl/n49 ), .IN4(n1028),
.Q(\fpu_add_ctl/n629 ) );
AO22X1 U4464 ( .IN1(n1333), .IN2(n1246), .IN3(\fpu_add_ctl/n49 ), .IN4(n336),
.Q(\fpu_add_ctl/n628 ) );
AO22X1 U4465 ( .IN1(n1335), .IN2(n490), .IN3(\fpu_add_ctl/n49 ), .IN4(n1029),
.Q(\fpu_add_ctl/n627 ) );
AO22X1 U4466 ( .IN1(n1336), .IN2(n927), .IN3(\fpu_add_ctl/n49 ), .IN4(n133),
.Q(\fpu_add_ctl/n626 ) );
AO22X1 U4467 ( .IN1(n1334), .IN2(n134), .IN3(\fpu_add_ctl/n49 ), .IN4(n549),
.Q(\fpu_add_ctl/n625 ) );
AO22X1 U4468 ( .IN1(n1333), .IN2(n333), .IN3(\fpu_add_ctl/n49 ), .IN4(n1030),
.Q(\fpu_add_ctl/n624 ) );
AO22X1 U4469 ( .IN1(n1335), .IN2(n135), .IN3(\fpu_add_ctl/n49 ), .IN4(n574),
.Q(\fpu_add_ctl/n623 ) );
AO22X1 U4470 ( .IN1(n1336), .IN2(n136), .IN3(\fpu_add_ctl/n49 ), .IN4(n575),
.Q(\fpu_add_ctl/n622 ) );
AO22X1 U4471 ( .IN1(n1334), .IN2(n339), .IN3(\fpu_add_ctl/n325 ), .IN4(
\fpu_add_ctl/n49 ), .Q(\fpu_add_ctl/n621 ) );
AO22X1 U4472 ( .IN1(n1333), .IN2(n108), .IN3(\fpu_add_ctl/n49 ), .IN4(n1031),
.Q(\fpu_add_ctl/n620 ) );
AO22X1 U4473 ( .IN1(n1335), .IN2(n552), .IN3(\fpu_add_ctl/n49 ), .IN4(n1032),
.Q(\fpu_add_ctl/n619 ) );
AO22X1 U4474 ( .IN1(n1336), .IN2(n622), .IN3(\fpu_add_ctl/n49 ), .IN4(
\fpu_add_ctl/n319 ), .Q(\fpu_add_ctl/n618 ) );
AO22X1 U4475 ( .IN1(n1334), .IN2(n1069), .IN3(\fpu_add_ctl/n49 ), .IN4(n324),
.Q(\fpu_add_ctl/n617 ) );
AO22X1 U4476 ( .IN1(n1333), .IN2(n1070), .IN3(\fpu_add_ctl/n49 ), .IN4(n134),
.Q(\fpu_add_ctl/n616 ) );
AO22X1 U4477 ( .IN1(n1335), .IN2(n1071), .IN3(\fpu_add_ctl/n49 ), .IN4(n333),
.Q(\fpu_add_ctl/n615 ) );
AO22X1 U4478 ( .IN1(n1336), .IN2(n1072), .IN3(\fpu_add_ctl/n49 ), .IN4(n135),
.Q(\fpu_add_ctl/n614 ) );
AO22X1 U4479 ( .IN1(n1334), .IN2(n1073), .IN3(\fpu_add_ctl/n49 ), .IN4(n136),
.Q(\fpu_add_ctl/n613 ) );
AO22X1 U4480 ( .IN1(n1335), .IN2(n1157), .IN3(\fpu_add_ctl/n49 ), .IN4(n339),
.Q(\fpu_add_ctl/n612 ) );
AO222X1 U4481 ( .IN1(n4414), .IN2(n1069), .IN3(n4415), .IN4(n324), .IN5(
n1334), .IN6(a6stg_fcmpop), .Q(\fpu_add_ctl/n611 ) );
AO222X1 U4482 ( .IN1(n4414), .IN2(n1070), .IN3(n4415), .IN4(n134), .IN5(
n1333), .IN6(a6stg_int_dst), .Q(\fpu_add_ctl/n610 ) );
AO222X1 U4483 ( .IN1(n4414), .IN2(n1071), .IN3(n4415), .IN4(n333), .IN5(
n1336), .IN6(a6stg_long_dst), .Q(\fpu_add_ctl/n609 ) );
AO222X1 U4484 ( .IN1(n4414), .IN2(n1072), .IN3(n4415), .IN4(n135), .IN5(
n1335), .IN6(a6stg_sng_dst), .Q(\fpu_add_ctl/n608 ) );
AO222X1 U4485 ( .IN1(n4414), .IN2(n1073), .IN3(n4415), .IN4(n136), .IN5(
n1334), .IN6(a6stg_dbl_dst), .Q(\fpu_add_ctl/n607 ) );
AND3X1 U4486 ( .IN1(\fpu_add_ctl/n315 ), .IN2(n642), .IN3(\fpu_add_ctl/n49 ),
.Q(n4415) );
AND2X1 U4487 ( .IN1(\fpu_add_ctl/n49 ), .IN2(n622), .Q(n4414) );
AO22X1 U4488 ( .IN1(n1336), .IN2(n1242), .IN3(\fpu_add_ctl/n49 ), .IN4(n576),
.Q(\fpu_add_ctl/n606 ) );
AO21X1 U4489 ( .IN1(n1457), .IN2(n129), .IN3(n4416), .Q(\fpu_add_ctl/n605 )
);
AO21X1 U4490 ( .IN1(n1457), .IN2(n692), .IN3(n4416), .Q(\fpu_add_ctl/n604 )
);
AO21X1 U4491 ( .IN1(n1457), .IN2(n102), .IN3(n4416), .Q(\fpu_add_ctl/n603 )
);
AO21X1 U4492 ( .IN1(n1457), .IN2(n701), .IN3(n4416), .Q(\fpu_add_ctl/n602 )
);
AO21X1 U4493 ( .IN1(n1457), .IN2(n662), .IN3(n4416), .Q(\fpu_add_ctl/n601 )
);
AND2X1 U4494 ( .IN1(n4366), .IN2(inq_op[0]), .Q(n4416) );
AO22X1 U4495 ( .IN1(inq_in2_exp_neq_ffs), .IN2(n4366), .IN3(n1459), .IN4(
\fpu_add_ctl/n317 ), .Q(\fpu_add_ctl/n600 ) );
AO22X1 U4496 ( .IN1(inq_in2_exp_eq_0), .IN2(n4366), .IN3(n1458), .IN4(n1086),
.Q(\fpu_add_ctl/n599 ) );
AO22X1 U4497 ( .IN1(inq_in2_53_32_neq_0), .IN2(n4366), .IN3(n1459), .IN4(
n730), .Q(\fpu_add_ctl/n598 ) );
AO22X1 U4498 ( .IN1(inq_in2_50_0_neq_0), .IN2(n4366), .IN3(n1458), .IN4(n731), .Q(\fpu_add_ctl/n597 ) );
AO22X1 U4499 ( .IN1(n4366), .IN2(inq_in2[63]), .IN3(n1459), .IN4(n649), .Q(
\fpu_add_ctl/n596 ) );
AO22X1 U4500 ( .IN1(n4366), .IN2(inq_in2[54]), .IN3(n1458), .IN4(n847), .Q(
\fpu_add_ctl/n595 ) );
AO22X1 U4501 ( .IN1(n4366), .IN2(inq_in2[51]), .IN3(n1459), .IN4(n460), .Q(
\fpu_add_ctl/n594 ) );
AO22X1 U4502 ( .IN1(inq_in1_exp_neq_ffs), .IN2(n4366), .IN3(n1458), .IN4(
n598), .Q(\fpu_add_ctl/n593 ) );
AO22X1 U4503 ( .IN1(inq_in1_exp_eq_0), .IN2(n4366), .IN3(n1459), .IN4(n1085),
.Q(\fpu_add_ctl/n592 ) );
AO22X1 U4504 ( .IN1(inq_in1_53_32_neq_0), .IN2(n4366), .IN3(n1458), .IN4(
n743), .Q(\fpu_add_ctl/n591 ) );
AO22X1 U4505 ( .IN1(inq_in1_50_0_neq_0), .IN2(n4366), .IN3(n1459), .IN4(n744), .Q(\fpu_add_ctl/n590 ) );
AO22X1 U4506 ( .IN1(inq_in1[63]), .IN2(n4366), .IN3(n1458), .IN4(n897), .Q(
\fpu_add_ctl/n589 ) );
AO22X1 U4507 ( .IN1(n4366), .IN2(inq_in1[54]), .IN3(n1459), .IN4(n1120), .Q(
\fpu_add_ctl/n588 ) );
AO22X1 U4508 ( .IN1(n4366), .IN2(inq_in1[51]), .IN3(n1458), .IN4(n1119), .Q(
\fpu_add_ctl/n587 ) );
NAND2X0 U4509 ( .IN1(n4417), .IN2(\fpu_add_ctl/n470 ), .QN(n3986) );
AND2X1 U4510 ( .IN1(n1338), .IN2(n4418), .Q(n4366) );
AO22X1 U4511 ( .IN1(n1472), .IN2(add_fcc_out[0]), .IN3(n4419), .IN4(n554),
.Q(\fpu_add_ctl/n586 ) );
AO22X1 U4512 ( .IN1(n4000), .IN2(add_fcc_out[1]), .IN3(n4419), .IN4(n555),
.Q(\fpu_add_ctl/n585 ) );
AO22X1 U4513 ( .IN1(n1337), .IN2(n897), .IN3(n1471), .IN4(n433), .Q(
\fpu_add_ctl/n584 ) );
AO22X1 U4514 ( .IN1(n1339), .IN2(n649), .IN3(n1471), .IN4(n270), .Q(
\fpu_add_ctl/n583 ) );
AO22X1 U4515 ( .IN1(n1338), .IN2(n1656), .IN3(n1470), .IN4(
\fpu_add_ctl/n313 ), .Q(\fpu_add_ctl/n582 ) );
AO22X1 U4516 ( .IN1(n1340), .IN2(n4420), .IN3(n1470), .IN4(n1210), .Q(
\fpu_add_ctl/n581 ) );
NAND4X0 U4517 ( .IN1(n4421), .IN2(n4422), .IN3(n4423), .IN4(n4424), .QN(
n4420) );
NOR4X0 U4518 ( .IN1(n4425), .IN2(n4426), .IN3(n4427), .IN4(n4428), .QN(n4424) );
XOR2X1 U4519 ( .IN1(\fpu_add_frac_dp/n2493 ), .IN2(n702), .Q(n4427) );
NOR2X0 U4520 ( .IN1(n4429), .IN2(n4430), .QN(n4423) );
AO22X1 U4521 ( .IN1(n1337), .IN2(n1881), .IN3(n1469), .IN4(n1212), .Q(
\fpu_add_ctl/n580 ) );
OAI21X1 U4522 ( .IN1(n4425), .IN2(n4431), .IN3(n4432), .QN(n1881) );
NAND4X0 U4523 ( .IN1(n4433), .IN2(n4434), .IN3(n4435), .IN4(n662), .QN(n4432) );
OR3X1 U4524 ( .IN1(n4436), .IN2(\fpu_add_frac_dp/n900 ), .IN3(n650), .Q(
n4434) );
NAND2X0 U4525 ( .IN1(\fpu_add_frac_dp/n2364 ), .IN2(n283), .QN(n4433) );
MUX21X1 U4526 ( .IN1(n4437), .IN2(n4438), .S(n4421), .Q(n4431) );
AND4X1 U4527 ( .IN1(n4439), .IN2(n4440), .IN3(n4441), .IN4(n4442), .Q(n4421)
);
NOR4X0 U4528 ( .IN1(n4443), .IN2(n4444), .IN3(n4445), .IN4(n4446), .QN(n4442) );
INVX0 U4529 ( .INP(n4447), .ZN(n4444) );
OR3X1 U4530 ( .IN1(n4448), .IN2(n4449), .IN3(n4450), .Q(n4443) );
OA221X1 U4531 ( .IN1(n428), .IN2(n54), .IN3(n989), .IN4(n132), .IN5(n4451),
.Q(n4441) );
OA21X1 U4532 ( .IN1(n1067), .IN2(n326), .IN3(n4452), .Q(n4451) );
NOR2X0 U4533 ( .IN1(n4453), .IN2(n4454), .QN(n4439) );
XOR2X1 U4534 ( .IN1(n647), .IN2(\fpu_add_frac_dp/n5608 ), .Q(n4453) );
MUX21X1 U4535 ( .IN1(n4455), .IN2(n4456), .S(n4422), .Q(n4438) );
AND4X1 U4536 ( .IN1(n4457), .IN2(n4458), .IN3(n4459), .IN4(n4460), .Q(n4422)
);
NOR4X0 U4537 ( .IN1(n4461), .IN2(n4462), .IN3(n4463), .IN4(n4464), .QN(n4460) );
XOR2X1 U4538 ( .IN1(\fpu_add_frac_dp/n846 ), .IN2(\fpu_add_frac_dp/n2439 ),
.Q(n4464) );
INVX0 U4539 ( .INP(n4465), .ZN(n4461) );
AOI221X1 U4540 ( .IN1(\fpu_add_frac_dp/n2487 ), .IN2(\fpu_add_frac_dp/n921 ),
.IN3(\fpu_add_frac_dp/n2444 ), .IN4(\fpu_add_frac_dp/n845 ), .IN5(
n4466), .QN(n4459) );
MUX21X1 U4541 ( .IN1(n4467), .IN2(n4468), .S(n4430), .Q(n4456) );
NAND4X0 U4542 ( .IN1(n4469), .IN2(n4470), .IN3(n4471), .IN4(n4472), .QN(
n4430) );
NAND2X0 U4543 ( .IN1(\fpu_add_frac_dp/n928 ), .IN2(\fpu_add_frac_dp/n2483 ),
.QN(n4472) );
INVX0 U4544 ( .INP(n4473), .ZN(n4471) );
XOR2X1 U4545 ( .IN1(n697), .IN2(\fpu_add_frac_dp/n2544 ), .Q(n4469) );
OA221X1 U4546 ( .IN1(n4474), .IN2(n4475), .IN3(n4476), .IN4(n4477), .IN5(
n4478), .Q(n4468) );
OA22X1 U4547 ( .IN1(n4479), .IN2(n4480), .IN3(\fpu_add_frac_dp/n2536 ),
.IN4(n853), .Q(n4478) );
NOR2X0 U4548 ( .IN1(n4481), .IN2(n4482), .QN(n4476) );
NOR3X0 U4549 ( .IN1(n4483), .IN2(\fpu_add_frac_dp/n848 ), .IN3(
\fpu_add_frac_dp/n2484 ), .QN(n4481) );
INVX0 U4550 ( .INP(n4470), .ZN(n4475) );
NOR4X0 U4551 ( .IN1(n4477), .IN2(n4482), .IN3(n4484), .IN4(n4483), .QN(n4470) );
NOR2X0 U4552 ( .IN1(n330), .IN2(\fpu_add_frac_dp/n2368 ), .QN(n4483) );
XOR2X1 U4553 ( .IN1(n670), .IN2(\fpu_add_frac_dp/n2484 ), .Q(n4484) );
AO22X1 U4554 ( .IN1(\fpu_add_frac_dp/n2454 ), .IN2(n1007), .IN3(
\fpu_add_frac_dp/n2368 ), .IN4(n330), .Q(n4482) );
NAND3X0 U4555 ( .IN1(n4485), .IN2(n4479), .IN3(n4486), .QN(n4477) );
AOI22X1 U4556 ( .IN1(\fpu_add_frac_dp/n2453 ), .IN2(\fpu_add_frac_dp/n847 ),
.IN3(n988), .IN4(\fpu_add_frac_dp/n5627 ), .QN(n4486) );
OA22X1 U4557 ( .IN1(\fpu_add_frac_dp/n2453 ), .IN2(\fpu_add_frac_dp/n847 ),
.IN3(n703), .IN4(\fpu_add_frac_dp/n5629 ), .Q(n4479) );
INVX0 U4558 ( .INP(n4480), .ZN(n4485) );
AO21X1 U4559 ( .IN1(\fpu_add_frac_dp/n5629 ), .IN2(n703), .IN3(n4487), .Q(
n4480) );
XOR2X1 U4560 ( .IN1(\fpu_add_frac_dp/n2536 ), .IN2(\fpu_add_frac_dp/n2372 ),
.Q(n4487) );
OA22X1 U4561 ( .IN1(n4488), .IN2(n4473), .IN3(n357), .IN4(n854), .Q(n4474)
);
AO21X1 U4562 ( .IN1(n1088), .IN2(n145), .IN3(n4489), .Q(n4473) );
XOR2X1 U4563 ( .IN1(n357), .IN2(\fpu_add_frac_dp/n927 ), .Q(n4489) );
OA21X1 U4564 ( .IN1(n1088), .IN2(n145), .IN3(n577), .Q(n4488) );
NOR4X0 U4565 ( .IN1(n4490), .IN2(n4491), .IN3(n4492), .IN4(n4493), .QN(n4467) );
AND2X1 U4566 ( .IN1(\fpu_add_frac_dp/n2472 ), .IN2(\fpu_add_frac_dp/n929 ),
.Q(n4493) );
OA221X1 U4567 ( .IN1(\fpu_add_frac_dp/n932 ), .IN2(\fpu_add_frac_dp/n2459 ),
.IN3(n4494), .IN4(n4495), .IN5(n4496), .Q(n4492) );
AOI21X1 U4568 ( .IN1(n695), .IN2(\fpu_add_frac_dp/n2366 ), .IN3(n4497), .QN(
n4495) );
OA21X1 U4569 ( .IN1(n4498), .IN2(n4499), .IN3(n4500), .Q(n4491) );
INVX0 U4570 ( .INP(n4501), .ZN(n4499) );
AND2X1 U4571 ( .IN1(\fpu_add_frac_dp/n2490 ), .IN2(\fpu_add_frac_dp/n931 ),
.Q(n4498) );
OA221X1 U4572 ( .IN1(n4502), .IN2(n4428), .IN3(n4503), .IN4(n4504), .IN5(
n4505), .Q(n4490) );
INVX0 U4573 ( .INP(n4429), .ZN(n4505) );
NAND4X0 U4574 ( .IN1(n4496), .IN2(n4506), .IN3(n4497), .IN4(n4507), .QN(
n4429) );
OA221X1 U4575 ( .IN1(\fpu_add_frac_dp/n934 ), .IN2(n337), .IN3(
\fpu_add_frac_dp/n933 ), .IN4(n900), .IN5(n4508), .Q(n4507) );
AOI21X1 U4576 ( .IN1(\fpu_add_frac_dp/n2296 ), .IN2(\fpu_add_frac_dp/n2533 ),
.IN3(n4494), .QN(n4508) );
AND2X1 U4577 ( .IN1(\fpu_add_frac_dp/n932 ), .IN2(\fpu_add_frac_dp/n2459 ),
.Q(n4494) );
OA22X1 U4578 ( .IN1(n695), .IN2(\fpu_add_frac_dp/n2366 ), .IN3(
\fpu_add_frac_dp/n2533 ), .IN4(\fpu_add_frac_dp/n2296 ), .Q(n4497) );
OR2X1 U4579 ( .IN1(\fpu_add_frac_dp/n2459 ), .IN2(\fpu_add_frac_dp/n932 ),
.Q(n4506) );
AND4X1 U4580 ( .IN1(n4500), .IN2(n4509), .IN3(n4510), .IN4(n4501), .Q(n4496)
);
NAND2X0 U4581 ( .IN1(\fpu_add_frac_dp/n930 ), .IN2(\fpu_add_frac_dp/n2489 ),
.QN(n4501) );
NAND2X0 U4582 ( .IN1(\fpu_add_frac_dp/n929 ), .IN2(\fpu_add_frac_dp/n2472 ),
.QN(n4510) );
XOR2X1 U4583 ( .IN1(\fpu_add_frac_dp/n931 ), .IN2(\fpu_add_frac_dp/n2490 ),
.Q(n4509) );
OA22X1 U4584 ( .IN1(\fpu_add_frac_dp/n2489 ), .IN2(\fpu_add_frac_dp/n930 ),
.IN3(\fpu_add_frac_dp/n2472 ), .IN4(\fpu_add_frac_dp/n929 ), .Q(n4500)
);
INVX0 U4585 ( .INP(n4426), .ZN(n4504) );
NOR2X0 U4586 ( .IN1(\fpu_add_frac_dp/n2455 ), .IN2(\fpu_add_frac_dp/n935 ),
.QN(n4426) );
NOR2X0 U4587 ( .IN1(\fpu_add_frac_dp/n2436 ), .IN2(n745), .QN(n4503) );
AO22X1 U4588 ( .IN1(\fpu_add_frac_dp/n935 ), .IN2(\fpu_add_frac_dp/n2455 ),
.IN3(\fpu_add_frac_dp/n934 ), .IN4(n337), .Q(n4428) );
NOR2X0 U4589 ( .IN1(\fpu_add_frac_dp/n2493 ), .IN2(\fpu_add_frac_dp/n851 ),
.QN(n4502) );
OA21X1 U4590 ( .IN1(n1303), .IN2(n550), .IN3(n4511), .Q(n4455) );
NAND3X0 U4591 ( .IN1(n4512), .IN2(n4513), .IN3(n4458), .QN(n4511) );
OA21X1 U4592 ( .IN1(\fpu_add_frac_dp/n2486 ), .IN2(\fpu_add_frac_dp/n918 ),
.IN3(n4514), .Q(n4458) );
XOR2X1 U4593 ( .IN1(\fpu_add_frac_dp/n2482 ), .IN2(\fpu_add_frac_dp/n917 ),
.Q(n4514) );
NAND3X0 U4594 ( .IN1(n4515), .IN2(n4516), .IN3(n4517), .QN(n4513) );
INVX0 U4595 ( .INP(n4462), .ZN(n4517) );
NAND2X0 U4596 ( .IN1(n4518), .IN2(n4519), .QN(n4462) );
XOR2X1 U4597 ( .IN1(\fpu_add_frac_dp/n844 ), .IN2(\fpu_add_frac_dp/n2488 ),
.Q(n4518) );
OAI21X1 U4598 ( .IN1(n4520), .IN2(n4463), .IN3(n4457), .QN(n4515) );
OA221X1 U4599 ( .IN1(\fpu_add_frac_dp/n2458 ), .IN2(\fpu_add_frac_dp/n919 ),
.IN3(\fpu_add_frac_dp/n2492 ), .IN4(\fpu_add_frac_dp/n920 ), .IN5(
n4516), .Q(n4457) );
NAND2X0 U4600 ( .IN1(\fpu_add_frac_dp/n919 ), .IN2(\fpu_add_frac_dp/n2458 ),
.QN(n4516) );
AO22X1 U4601 ( .IN1(\fpu_add_frac_dp/n920 ), .IN2(\fpu_add_frac_dp/n2492 ),
.IN3(n335), .IN4(n1078), .Q(n4463) );
OA22X1 U4602 ( .IN1(n4521), .IN2(n4522), .IN3(n1078), .IN4(n335), .Q(n4520)
);
AND2X1 U4603 ( .IN1(\fpu_add_frac_dp/n2487 ), .IN2(\fpu_add_frac_dp/n921 ),
.Q(n4522) );
OA21X1 U4604 ( .IN1(\fpu_add_frac_dp/n2439 ), .IN2(n4466), .IN3(n4465), .Q(
n4521) );
OA22X1 U4605 ( .IN1(\fpu_add_frac_dp/n2487 ), .IN2(\fpu_add_frac_dp/n921 ),
.IN3(\fpu_add_frac_dp/n2485 ), .IN4(\fpu_add_frac_dp/n922 ), .Q(n4465)
);
AND2X1 U4606 ( .IN1(\fpu_add_frac_dp/n922 ), .IN2(\fpu_add_frac_dp/n2485 ),
.Q(n4466) );
NAND3X0 U4607 ( .IN1(\fpu_add_frac_dp/n2488 ), .IN2(n4519), .IN3(
\fpu_add_frac_dp/n844 ), .QN(n4512) );
NAND2X0 U4608 ( .IN1(\fpu_add_frac_dp/n918 ), .IN2(\fpu_add_frac_dp/n2486 ),
.QN(n4519) );
OA221X1 U4609 ( .IN1(n1089), .IN2(n340), .IN3(n4448), .IN4(n4523), .IN5(
n4524), .Q(n4437) );
NAND3X0 U4610 ( .IN1(n1158), .IN2(n427), .IN3(n4525), .QN(n4524) );
MUX21X1 U4611 ( .IN1(n4526), .IN2(n4527), .S(n4450), .Q(n4523) );
NAND4X0 U4612 ( .IN1(n4528), .IN2(n4529), .IN3(n4530), .IN4(n4531), .QN(
n4450) );
NOR2X0 U4613 ( .IN1(n4532), .IN2(n4533), .QN(n4530) );
XOR2X1 U4614 ( .IN1(n677), .IN2(\fpu_add_frac_dp/n2538 ), .Q(n4528) );
AO22X1 U4615 ( .IN1(n4533), .IN2(n4534), .IN3(n4535), .IN4(n4531), .Q(n4527)
);
OA21X1 U4616 ( .IN1(\fpu_add_frac_dp/n5626 ), .IN2(\fpu_add_frac_dp/n2476 ),
.IN3(n4534), .Q(n4531) );
OA21X1 U4617 ( .IN1(n4536), .IN2(n4537), .IN3(n4538), .Q(n4535) );
INVX0 U4618 ( .INP(n4529), .ZN(n4537) );
OA221X1 U4619 ( .IN1(\fpu_add_frac_dp/n904 ), .IN2(\fpu_add_frac_dp/n5611 ),
.IN3(\fpu_add_frac_dp/n903 ), .IN4(\fpu_add_frac_dp/n5624 ), .IN5(
n4538), .Q(n4529) );
NAND2X0 U4620 ( .IN1(\fpu_add_frac_dp/n903 ), .IN2(\fpu_add_frac_dp/n5624 ),
.QN(n4538) );
NOR2X0 U4621 ( .IN1(\fpu_add_frac_dp/n2373 ), .IN2(n4532), .QN(n4536) );
AND2X1 U4622 ( .IN1(\fpu_add_frac_dp/n904 ), .IN2(\fpu_add_frac_dp/n5611 ),
.Q(n4532) );
NAND2X0 U4623 ( .IN1(\fpu_add_frac_dp/n2415 ), .IN2(n1065), .QN(n4534) );
AO22X1 U4624 ( .IN1(\fpu_add_frac_dp/n5626 ), .IN2(\fpu_add_frac_dp/n2476 ),
.IN3(\fpu_add_frac_dp/n5625 ), .IN4(n917), .Q(n4533) );
MUX21X1 U4625 ( .IN1(n4539), .IN2(n4540), .S(n4445), .Q(n4526) );
NAND3X0 U4626 ( .IN1(n4541), .IN2(n4542), .IN3(n4543), .QN(n4445) );
OA22X1 U4627 ( .IN1(n719), .IN2(n125), .IN3(n306), .IN4(n46), .Q(n4543) );
INVX0 U4628 ( .INP(n4544), .ZN(n4542) );
XOR2X1 U4629 ( .IN1(n292), .IN2(\fpu_add_frac_dp/n841 ), .Q(n4541) );
AND3X1 U4630 ( .IN1(n4545), .IN2(n4546), .IN3(n4547), .Q(n4540) );
OA22X1 U4631 ( .IN1(n4548), .IN2(n4544), .IN3(n578), .IN4(n57), .Q(n4547) );
AO221X1 U4632 ( .IN1(n125), .IN2(n719), .IN3(n46), .IN4(n306), .IN5(n4549),
.Q(n4544) );
OA21X1 U4633 ( .IN1(n719), .IN2(n125), .IN3(n292), .Q(n4548) );
OR3X1 U4634 ( .IN1(n4550), .IN2(n4551), .IN3(n4552), .Q(n4546) );
AND2X1 U4635 ( .IN1(n4553), .IN2(n4554), .Q(n4552) );
NAND3X0 U4636 ( .IN1(n4555), .IN2(n4556), .IN3(n4557), .QN(n4554) );
AO22X1 U4637 ( .IN1(\fpu_add_frac_dp/n907 ), .IN2(\fpu_add_frac_dp/n5620 ),
.IN3(n4558), .IN4(n4559), .Q(n4557) );
INVX0 U4638 ( .INP(n4560), .ZN(n4559) );
NAND2X0 U4639 ( .IN1(\fpu_add_frac_dp/n2438 ), .IN2(n709), .QN(n4558) );
OR3X1 U4640 ( .IN1(n4549), .IN2(n306), .IN3(n46), .Q(n4545) );
NAND4X0 U4641 ( .IN1(n4561), .IN2(n4553), .IN3(n4562), .IN4(n4563), .QN(
n4549) );
NOR4X0 U4642 ( .IN1(n4564), .IN2(n4560), .IN3(n4551), .IN4(n4565), .QN(n4563) );
INVX0 U4643 ( .INP(n4555), .ZN(n4565) );
NAND2X0 U4644 ( .IN1(\fpu_add_frac_dp/n839 ), .IN2(\fpu_add_frac_dp/n2462 ),
.QN(n4555) );
NOR2X0 U4645 ( .IN1(\fpu_add_frac_dp/n905 ), .IN2(\fpu_add_frac_dp/n5621 ),
.QN(n4551) );
NOR2X0 U4646 ( .IN1(\fpu_add_frac_dp/n907 ), .IN2(\fpu_add_frac_dp/n5620 ),
.QN(n4560) );
AO21X1 U4647 ( .IN1(\fpu_add_frac_dp/n2438 ), .IN2(n709), .IN3(n4550), .Q(
n4564) );
NOR2X0 U4648 ( .IN1(n763), .IN2(\fpu_add_frac_dp/n2540 ), .QN(n4550) );
OA22X1 U4649 ( .IN1(n1079), .IN2(n141), .IN3(n578), .IN4(n57), .Q(n4562) );
OA22X1 U4650 ( .IN1(n848), .IN2(\fpu_add_frac_dp/n2543 ), .IN3(
\fpu_add_frac_dp/n2462 ), .IN4(\fpu_add_frac_dp/n839 ), .Q(n4553) );
INVX0 U4651 ( .INP(n4556), .ZN(n4561) );
AO222X1 U4652 ( .IN1(n1079), .IN2(n141), .IN3(\fpu_add_frac_dp/n908 ), .IN4(
n463), .IN5(\fpu_add_frac_dp/n907 ), .IN6(\fpu_add_frac_dp/n5620 ),
.Q(n4556) );
OA21X1 U4653 ( .IN1(n4566), .IN2(n4454), .IN3(n4452), .Q(n4539) );
NAND2X0 U4654 ( .IN1(\fpu_add_frac_dp/n911 ), .IN2(\fpu_add_frac_dp/n5623 ),
.QN(n4452) );
OAI22X1 U4655 ( .IN1(\fpu_add_frac_dp/n5623 ), .IN2(\fpu_add_frac_dp/n911 ),
.IN3(n916), .IN4(\fpu_add_frac_dp/n912 ), .QN(n4454) );
OA21X1 U4656 ( .IN1(n4567), .IN2(n4568), .IN3(n4447), .Q(n4566) );
OA22X1 U4657 ( .IN1(n857), .IN2(\fpu_add_frac_dp/n2365 ), .IN3(
\fpu_add_frac_dp/n2295 ), .IN4(\fpu_add_frac_dp/n2532 ), .Q(n4447) );
NOR2X0 U4658 ( .IN1(n1067), .IN2(n326), .QN(n4568) );
OA22X1 U4659 ( .IN1(n4569), .IN2(n4446), .IN3(n358), .IN4(n855), .Q(n4567)
);
AO21X1 U4660 ( .IN1(\fpu_add_frac_dp/n2441 ), .IN2(n704), .IN3(n4570), .Q(
n4446) );
XOR2X1 U4661 ( .IN1(n358), .IN2(\fpu_add_frac_dp/n913 ), .Q(n4570) );
OA21X1 U4662 ( .IN1(n4571), .IN2(n4572), .IN3(n4440), .Q(n4569) );
OA22X1 U4663 ( .IN1(\fpu_add_frac_dp/n2445 ), .IN2(\fpu_add_frac_dp/n843 ),
.IN3(n704), .IN4(\fpu_add_frac_dp/n2441 ), .Q(n4440) );
NOR2X0 U4664 ( .IN1(n989), .IN2(n132), .QN(n4572) );
OA22X1 U4665 ( .IN1(n4573), .IN2(n4449), .IN3(\fpu_add_frac_dp/n2514 ),
.IN4(n856), .Q(n4571) );
AO21X1 U4666 ( .IN1(n428), .IN2(n54), .IN3(n4574), .Q(n4449) );
XOR2X1 U4667 ( .IN1(\fpu_add_frac_dp/n2514 ), .IN2(\fpu_add_frac_dp/n2367 ),
.Q(n4574) );
OA21X1 U4668 ( .IN1(n428), .IN2(n54), .IN3(n647), .Q(n4573) );
NAND3X0 U4669 ( .IN1(n4575), .IN2(n4525), .IN3(n4576), .QN(n4448) );
XOR2X1 U4670 ( .IN1(\fpu_add_frac_dp/n2535 ), .IN2(\fpu_add_frac_dp/n2350 ),
.Q(n4576) );
NAND2X0 U4671 ( .IN1(n340), .IN2(n1089), .QN(n4525) );
NAND2X0 U4672 ( .IN1(\fpu_add_frac_dp/n901 ), .IN2(\fpu_add_frac_dp/n2491 ),
.QN(n4575) );
AND2X1 U4673 ( .IN1(n4577), .IN2(n662), .Q(n4425) );
AO221X1 U4674 ( .IN1(\fpu_add_frac_dp/n2364 ), .IN2(n283), .IN3(
\fpu_add_frac_dp/n2442 ), .IN4(n747), .IN5(n4578), .Q(n4577) );
AO21X1 U4675 ( .IN1(n548), .IN2(n1304), .IN3(n4435), .Q(n4578) );
AO221X1 U4676 ( .IN1(\fpu_add_frac_dp/n900 ), .IN2(n650), .IN3(
\fpu_add_frac_dp/n5643 ), .IN4(\fpu_add_frac_dp/n5644 ), .IN5(n4436),
.Q(n4435) );
NOR2X0 U4677 ( .IN1(n283), .IN2(\fpu_add_frac_dp/n2364 ), .QN(n4436) );
AO22X1 U4678 ( .IN1(n1339), .IN2(n1880), .IN3(n1470), .IN4(n1004), .Q(
\fpu_add_ctl/n579 ) );
AND4X1 U4679 ( .IN1(n4579), .IN2(n4580), .IN3(n4581), .IN4(n4582), .Q(n1880)
);
NOR4X0 U4680 ( .IN1(n4583), .IN2(n4584), .IN3(n4585), .IN4(n4586), .QN(n4582) );
XOR2X1 U4681 ( .IN1(\fpu_add_frac_dp/n2475 ), .IN2(n712), .Q(n4586) );
XOR2X1 U4682 ( .IN1(\fpu_add_frac_dp/n2467 ), .IN2(n713), .Q(n4585) );
XOR2X1 U4683 ( .IN1(\fpu_add_frac_dp/n2466 ), .IN2(n714), .Q(n4584) );
XOR2X1 U4684 ( .IN1(\fpu_add_frac_dp/n2469 ), .IN2(n715), .Q(n4583) );
AND3X1 U4685 ( .IN1(n4587), .IN2(n4588), .IN3(n4589), .Q(n4581) );
XOR2X1 U4686 ( .IN1(\fpu_add_frac_dp/n940 ), .IN2(\fpu_add_frac_dp/n2474 ),
.Q(n4589) );
NAND2X0 U4687 ( .IN1(\fpu_add_ctl/n116 ), .IN2(n4590), .QN(n4588) );
NAND3X0 U4688 ( .IN1(n4591), .IN2(n4592), .IN3(n4593), .QN(n4590) );
XOR2X1 U4689 ( .IN1(n591), .IN2(\fpu_add_frac_dp/n2521 ), .Q(n4593) );
XOR2X1 U4690 ( .IN1(n593), .IN2(\fpu_add_frac_dp/n2534 ), .Q(n4592) );
XOR2X1 U4691 ( .IN1(n592), .IN2(\fpu_add_frac_dp/n945 ), .Q(n4591) );
XOR2X1 U4692 ( .IN1(\fpu_add_frac_dp/n942 ), .IN2(\fpu_add_frac_dp/n2473 ),
.Q(n4587) );
XOR2X1 U4693 ( .IN1(\fpu_add_frac_dp/n937 ), .IN2(\fpu_add_frac_dp/n2468 ),
.Q(n4580) );
XOR2X1 U4694 ( .IN1(\fpu_add_frac_dp/n943 ), .IN2(\fpu_add_frac_dp/n2446 ),
.Q(n4579) );
OAI22X1 U4695 ( .IN1(n4057), .IN2(n2050), .IN3(n4114), .IN4(
\fpu_add_ctl/n38 ), .QN(\fpu_add_ctl/n578 ) );
OA22X1 U4696 ( .IN1(n2685), .IN2(n2687), .IN3(n2686), .IN4(n4594), .Q(n2050)
);
AND2X1 U4697 ( .IN1(n2687), .IN2(n2685), .Q(n4594) );
NAND2X0 U4698 ( .IN1(n928), .IN2(n105), .QN(n2686) );
NOR2X0 U4699 ( .IN1(\fpu_add_exp_dp/n245 ), .IN2(\fpu_add_exp_dp/n174 ),
.QN(n2687) );
AOI22X1 U4700 ( .IN1(n2680), .IN2(n2681), .IN3(n2679), .IN4(n4595), .QN(
n2685) );
OR2X1 U4701 ( .IN1(n2681), .IN2(n2680), .Q(n4595) );
OA21X1 U4702 ( .IN1(\fpu_add_exp_dp/n246 ), .IN2(\fpu_add_exp_dp/n175 ),
.IN3(\fpu_add_exp_dp/n170 ), .Q(n2679) );
AO22X1 U4703 ( .IN1(n2682), .IN2(n2684), .IN3(n2683), .IN4(n4596), .Q(n2681)
);
OR2X1 U4704 ( .IN1(n2684), .IN2(n2682), .Q(n4596) );
OA21X1 U4705 ( .IN1(\fpu_add_exp_dp/n247 ), .IN2(\fpu_add_exp_dp/n176 ),
.IN3(\fpu_add_exp_dp/n171 ), .Q(n2683) );
AO22X1 U4706 ( .IN1(n2688), .IN2(n2690), .IN3(n4597), .IN4(n2689), .Q(n2684)
);
AO22X1 U4707 ( .IN1(n936), .IN2(n105), .IN3(n545), .IN4(n41), .Q(n2689) );
OR2X1 U4708 ( .IN1(n2690), .IN2(n2688), .Q(n4597) );
AO22X1 U4709 ( .IN1(n2692), .IN2(n2693), .IN3(n2691), .IN4(n4598), .Q(n2690)
);
OR2X1 U4710 ( .IN1(n2693), .IN2(n2692), .Q(n4598) );
OA22X1 U4711 ( .IN1(\fpu_add_exp_dp/n249 ), .IN2(\fpu_add_exp_dp/n178 ),
.IN3(\fpu_add_exp_dp/n246 ), .IN4(\fpu_add_exp_dp/n197 ), .Q(n2691) );
AO22X1 U4712 ( .IN1(n2720), .IN2(n2722), .IN3(n2721), .IN4(n4599), .Q(n2693)
);
OR2X1 U4713 ( .IN1(n2722), .IN2(n2720), .Q(n4599) );
OA22X1 U4714 ( .IN1(\fpu_add_exp_dp/n250 ), .IN2(\fpu_add_exp_dp/n179 ),
.IN3(\fpu_add_exp_dp/n247 ), .IN4(\fpu_add_exp_dp/n198 ), .Q(n2721) );
AO22X1 U4715 ( .IN1(n2659), .IN2(n2661), .IN3(n2660), .IN4(n4600), .Q(n2722)
);
OR2X1 U4716 ( .IN1(n2661), .IN2(n2659), .Q(n4600) );
OA22X1 U4717 ( .IN1(\fpu_add_exp_dp/n251 ), .IN2(\fpu_add_exp_dp/n180 ),
.IN3(\fpu_add_exp_dp/n248 ), .IN4(\fpu_add_exp_dp/n199 ), .Q(n2660) );
AO22X1 U4718 ( .IN1(n2645), .IN2(n2647), .IN3(n2646), .IN4(n4601), .Q(n2661)
);
OR2X1 U4719 ( .IN1(n2647), .IN2(n2645), .Q(n4601) );
OA22X1 U4720 ( .IN1(\fpu_add_exp_dp/n252 ), .IN2(\fpu_add_exp_dp/n181 ),
.IN3(\fpu_add_exp_dp/n249 ), .IN4(\fpu_add_exp_dp/n200 ), .Q(n2646) );
AO22X1 U4721 ( .IN1(n4602), .IN2(n2635), .IN3(n2634), .IN4(n4603), .Q(n2647)
);
NAND2X0 U4722 ( .IN1(n4604), .IN2(n2633), .QN(n4603) );
OA22X1 U4723 ( .IN1(\fpu_add_exp_dp/n253 ), .IN2(\fpu_add_exp_dp/n182 ),
.IN3(\fpu_add_exp_dp/n250 ), .IN4(\fpu_add_exp_dp/n201 ), .Q(n2634) );
INVX0 U4724 ( .INP(n4604), .ZN(n2635) );
OA22X1 U4725 ( .IN1(n2052), .IN2(n2621), .IN3(n2620), .IN4(n4605), .Q(n4604)
);
AND2X1 U4726 ( .IN1(n2621), .IN2(n2052), .Q(n4605) );
AO22X1 U4727 ( .IN1(n1066), .IN2(n558), .IN3(n152), .IN4(n61), .Q(n2620) );
OA22X1 U4728 ( .IN1(\fpu_add_exp_dp/n232 ), .IN2(\fpu_add_exp_dp/n194 ),
.IN3(\fpu_add_exp_dp/n229 ), .IN4(\fpu_add_exp_dp/n210 ), .Q(n2621) );
OR2X1 U4729 ( .IN1(n2612), .IN2(n2611), .Q(n2052) );
OA22X1 U4730 ( .IN1(\fpu_add_exp_dp/n233 ), .IN2(\fpu_add_exp_dp/n195 ),
.IN3(\fpu_add_exp_dp/n230 ), .IN4(\fpu_add_exp_dp/n211 ), .Q(n2611) );
AO221X1 U4731 ( .IN1(n151), .IN2(n1033), .IN3(n510), .IN4(n60), .IN5(n13),
.Q(n2612) );
INVX0 U4732 ( .INP(n2633), .ZN(n4602) );
OA22X1 U4733 ( .IN1(\fpu_add_exp_dp/n209 ), .IN2(\fpu_add_exp_dp/n228 ),
.IN3(\fpu_add_exp_dp/n193 ), .IN4(\fpu_add_exp_dp/n231 ), .Q(n2633) );
AO22X1 U4734 ( .IN1(n958), .IN2(n42), .IN3(n514), .IN4(n109), .Q(n2645) );
AO22X1 U4735 ( .IN1(n959), .IN2(n41), .IN3(n515), .IN4(n110), .Q(n2659) );
AO22X1 U4736 ( .IN1(n960), .IN2(n126), .IN3(n516), .IN4(n49), .Q(n2720) );
AO22X1 U4737 ( .IN1(n937), .IN2(n127), .IN3(n546), .IN4(n42), .Q(n2692) );
OA221X1 U4738 ( .IN1(\fpu_add_exp_dp/n248 ), .IN2(\fpu_add_exp_dp/n177 ),
.IN3(\fpu_add_exp_dp/n245 ), .IN4(\fpu_add_exp_dp/n196 ), .IN5(
\fpu_add_exp_dp/n172 ), .Q(n2688) );
NOR2X0 U4739 ( .IN1(\fpu_add_exp_dp/n187 ), .IN2(\fpu_add_exp_dp/n225 ),
.QN(n2682) );
NOR2X0 U4740 ( .IN1(\fpu_add_exp_dp/n186 ), .IN2(\fpu_add_exp_dp/n224 ),
.QN(n2680) );
AO22X1 U4741 ( .IN1(n1472), .IN2(n851), .IN3(n1340), .IN4(n1741), .Q(
\fpu_add_ctl/n577 ) );
OAI22X1 U4742 ( .IN1(n4057), .IN2(n1752), .IN3(n4114), .IN4(
\fpu_add_ctl/n338 ), .QN(\fpu_add_ctl/n576 ) );
AO22X1 U4743 ( .IN1(n1338), .IN2(n1751), .IN3(n1470), .IN4(n1173), .Q(
\fpu_add_ctl/n575 ) );
AO22X1 U4744 ( .IN1(n1340), .IN2(n1749), .IN3(n1471), .IN4(n1213), .Q(
\fpu_add_ctl/n574 ) );
AND2X1 U4745 ( .IN1(n4606), .IN2(n338), .Q(n1749) );
AO22X1 U4746 ( .IN1(n102), .IN2(n847), .IN3(n460), .IN4(n44), .Q(n4606) );
AO22X1 U4747 ( .IN1(n4607), .IN2(n1339), .IN3(n1471), .IN4(n422), .Q(
\fpu_add_ctl/n573 ) );
AO22X1 U4748 ( .IN1(n4000), .IN2(n1068), .IN3(n4608), .IN4(n1340), .Q(
\fpu_add_ctl/n572 ) );
NOR2X0 U4749 ( .IN1(n4609), .IN2(n598), .QN(n4608) );
OA22X1 U4750 ( .IN1(\fpu_add_ctl/n203 ), .IN2(\fpu_add_ctl/n127 ), .IN3(
\fpu_add_ctl/n332 ), .IN4(\fpu_add_ctl/n205 ), .Q(n4609) );
AO21X1 U4751 ( .IN1(n1467), .IN2(n1217), .IN3(n4610), .Q(\fpu_add_ctl/n571 )
);
NOR4X0 U4752 ( .IN1(n4611), .IN2(n4612), .IN3(\fpu_add_ctl/n122 ), .IN4(
\fpu_add_ctl/n117 ), .QN(n4610) );
OA21X1 U4753 ( .IN1(n4613), .IN2(n4614), .IN3(\fpu_add_ctl/n202 ), .Q(n4612)
);
OR3X1 U4754 ( .IN1(n4615), .IN2(n4616), .IN3(n4057), .Q(n4611) );
AO22X1 U4755 ( .IN1(n1337), .IN2(n1657), .IN3(n1471), .IN4(n957), .Q(
\fpu_add_ctl/n570 ) );
AO22X1 U4756 ( .IN1(n4000), .IN2(n149), .IN3(n4617), .IN4(n4618), .Q(
\fpu_add_ctl/n569 ) );
NAND4X0 U4757 ( .IN1(n4619), .IN2(n640), .IN3(n4620), .IN4(n4621), .QN(n4618) );
OA22X1 U4758 ( .IN1(\fpu_add_ctl/n316 ), .IN2(n4622), .IN3(\fpu_add_ctl/n41 ), .IN4(n4623), .Q(n4621) );
AOI22X1 U4759 ( .IN1(n422), .IN2(\fpu_add_ctl/n310 ), .IN3(n1068), .IN4(
\fpu_add_ctl/n338 ), .QN(n4623) );
OA21X1 U4760 ( .IN1(\fpu_add_ctl/n34 ), .IN2(n422), .IN3(\fpu_add_ctl/n310 ),
.Q(n4622) );
NAND4X0 U4761 ( .IN1(n4624), .IN2(\fpu_add_ctl/n37 ), .IN3(\fpu_add_ctl/n31 ), .IN4(n4625), .QN(n4620) );
NOR3X0 U4762 ( .IN1(n4626), .IN2(\fpu_add_ctl/n200 ), .IN3(
\fpu_add_ctl/n196 ), .QN(n4625) );
NOR2X0 U4763 ( .IN1(n4627), .IN2(n433), .QN(n4626) );
NAND4X0 U4764 ( .IN1(\fpu_add_ctl/n37 ), .IN2(n4628), .IN3(n4629), .IN4(
n4630), .QN(n4619) );
AO21X1 U4765 ( .IN1(n4631), .IN2(n4632), .IN3(n4627), .Q(n4630) );
XOR2X1 U4766 ( .IN1(\fpu_add_ctl/n139 ), .IN2(\fpu_add_ctl/n316 ), .Q(n4627)
);
OAI21X1 U4767 ( .IN1(n4624), .IN2(n4631), .IN3(\fpu_add_ctl/n41 ), .QN(n4629) );
NAND2X0 U4768 ( .IN1(\fpu_add_ctl/n313 ), .IN2(n957), .QN(n4628) );
AO21X1 U4769 ( .IN1(n1337), .IN2(n270), .IN3(n4075), .Q(n4617) );
NOR2X0 U4770 ( .IN1(n4057), .IN2(\fpu_add_ctl/n938 ), .QN(n4075) );
NAND3X0 U4771 ( .IN1(n4633), .IN2(n4634), .IN3(n4635), .QN(
\fpu_add_ctl/n568 ) );
MUX21X1 U4772 ( .IN1(n4636), .IN2(n4637), .S(\fpu_add_ctl/n316 ), .Q(n4635)
);
NAND2X0 U4773 ( .IN1(n4000), .IN2(n1082), .QN(n4633) );
NAND3X0 U4774 ( .IN1(n4638), .IN2(n4634), .IN3(n4639), .QN(
\fpu_add_ctl/n567 ) );
MUX21X1 U4775 ( .IN1(n4637), .IN2(n4636), .S(\fpu_add_ctl/n316 ), .Q(n4639)
);
NAND4X0 U4776 ( .IN1(n4640), .IN2(n4631), .IN3(n4632), .IN4(n754), .QN(n4636) );
NAND2X0 U4777 ( .IN1(n4641), .IN2(n4640), .QN(n4637) );
MUX21X1 U4778 ( .IN1(n4642), .IN2(\fpu_add_ctl/n32 ), .S(\fpu_add_ctl/n313 ),
.Q(n4641) );
NOR2X0 U4779 ( .IN1(n4624), .IN2(n4631), .QN(n4642) );
OA21X1 U4780 ( .IN1(\fpu_add_ctl/n39 ), .IN2(\fpu_add_ctl/n335 ), .IN3(
\fpu_add_ctl/n38 ), .Q(n4631) );
INVX0 U4781 ( .INP(n4632), .ZN(n4624) );
NAND2X0 U4782 ( .IN1(\fpu_add_ctl/n40 ), .IN2(n1004), .QN(n4632) );
NAND2X0 U4783 ( .IN1(n4640), .IN2(n851), .QN(n4634) );
NOR2X0 U4784 ( .IN1(n4057), .IN2(\fpu_add_ctl/n143 ), .QN(n4640) );
NAND2X0 U4785 ( .IN1(n4000), .IN2(n1083), .QN(n4638) );
AO22X1 U4786 ( .IN1(n1339), .IN2(n149), .IN3(n1471), .IN4(n884), .Q(
\fpu_add_ctl/n566 ) );
AO222X1 U4787 ( .IN1(n4412), .IN2(n149), .IN3(n4413), .IN4(n884), .IN5(n1461), .IN6(n444), .Q(\fpu_add_ctl/n565 ) );
NOR2X0 U4788 ( .IN1(n455), .IN2(n4057), .QN(n4413) );
NOR2X0 U4789 ( .IN1(n4057), .IN2(\fpu_add_ctl/n101 ), .QN(n4412) );
AO22X1 U4790 ( .IN1(n1338), .IN2(n1082), .IN3(n1471), .IN4(n556), .Q(
\fpu_add_ctl/n564 ) );
AO22X1 U4791 ( .IN1(n1340), .IN2(n1083), .IN3(n1471), .IN4(n557), .Q(
\fpu_add_ctl/n563 ) );
AO22X1 U4792 ( .IN1(n1337), .IN2(n444), .IN3(n1471), .IN4(add_sign_out), .Q(
\fpu_add_ctl/n562 ) );
AO22X1 U4793 ( .IN1(n1472), .IN2(add_cc_out[0]), .IN3(n4419), .IN4(n556),
.Q(\fpu_add_ctl/n561 ) );
AO22X1 U4794 ( .IN1(n4000), .IN2(add_cc_out[1]), .IN3(n4419), .IN4(n557),
.Q(\fpu_add_ctl/n560 ) );
NOR2X0 U4795 ( .IN1(n4057), .IN2(\fpu_add_ctl/n86 ), .QN(n4419) );
AO22X1 U4796 ( .IN1(n1339), .IN2(n4643), .IN3(n1471), .IN4(n903), .Q(
\fpu_add_ctl/n559 ) );
AO221X1 U4797 ( .IN1(n1751), .IN2(n4644), .IN3(n4607), .IN4(n4645), .IN5(
n4646), .Q(n4643) );
NAND2X0 U4798 ( .IN1(n4647), .IN2(n1740), .QN(n4646) );
NAND3X0 U4799 ( .IN1(n1657), .IN2(n1737), .IN3(n1656), .QN(n1740) );
INVX0 U4800 ( .INP(n4648), .ZN(n1656) );
NOR4X0 U4801 ( .IN1(n4649), .IN2(n598), .IN3(\fpu_add_ctl/n317 ), .IN4(n4650), .QN(n1657) );
OA22X1 U4802 ( .IN1(\fpu_add_ctl/n330 ), .IN2(n4613), .IN3(
\fpu_add_ctl/n309 ), .IN4(n4616), .Q(n4650) );
OA22X1 U4803 ( .IN1(\fpu_add_ctl/n330 ), .IN2(n4614), .IN3(
\fpu_add_ctl/n309 ), .IN4(n4615), .Q(n4649) );
NAND3X0 U4804 ( .IN1(n1741), .IN2(n18), .IN3(n4386), .QN(n4647) );
INVX0 U4805 ( .INP(n1750), .ZN(n4607) );
AO21X1 U4806 ( .IN1(n4651), .IN2(n4652), .IN3(n598), .Q(n1750) );
NAND3X0 U4807 ( .IN1(n743), .IN2(n102), .IN3(\fpu_add_ctl/n332 ), .QN(n4652)
);
NAND3X0 U4808 ( .IN1(n744), .IN2(n44), .IN3(\fpu_add_ctl/n127 ), .QN(n4651)
);
OR3X1 U4809 ( .IN1(n4048), .IN2(a1stg_fdtos), .IN3(n4645), .Q(n4644) );
AO21X1 U4810 ( .IN1(n4386), .IN2(\fpu_add_ctl/n318 ), .IN3(n1737), .Q(n4645)
);
AND4X1 U4811 ( .IN1(n4406), .IN2(n4400), .IN3(n585), .IN4(n172), .Q(n4386)
);
AOI21X1 U4812 ( .IN1(n4653), .IN2(n4654), .IN3(\fpu_add_ctl/n317 ), .QN(
n1751) );
NAND3X0 U4813 ( .IN1(n730), .IN2(n102), .IN3(\fpu_add_ctl/n333 ), .QN(n4654)
);
NAND3X0 U4814 ( .IN1(n731), .IN2(n44), .IN3(\fpu_add_ctl/n121 ), .QN(n4653)
);
AO22X1 U4815 ( .IN1(n4000), .IN2(n1077), .IN3(n1338), .IN4(n4655), .Q(
\fpu_add_ctl/n558 ) );
NAND2X0 U4816 ( .IN1(n1877), .IN2(n2719), .QN(n4655) );
NAND2X0 U4817 ( .IN1(n4656), .IN2(n1867), .QN(n2719) );
OA22X1 U4818 ( .IN1(n338), .IN2(\fpu_add_ctl/n324 ), .IN3(n915), .IN4(n129),
.Q(n1877) );
AO22X1 U4819 ( .IN1(n4000), .IN2(n140), .IN3(n1337), .IN4(n4657), .Q(
\fpu_add_ctl/n557 ) );
AO21X1 U4820 ( .IN1(n1932), .IN2(n4658), .IN3(n903), .Q(n4657) );
NAND4X0 U4821 ( .IN1(n4659), .IN2(n4660), .IN3(n4661), .IN4(n4662), .QN(
n4658) );
NOR4X0 U4822 ( .IN1(n4663), .IN2(n4087), .IN3(n4083), .IN4(n4085), .QN(n4662) );
XOR3X1 U4823 ( .IN1(\fpu_add_exp_dp/n132 ), .IN2(\fpu_add_exp_dp/n119 ),
.IN3(n4664), .Q(n4085) );
XOR3X1 U4824 ( .IN1(\fpu_add_exp_dp/n133 ), .IN2(\fpu_add_exp_dp/n120 ),
.IN3(n4665), .Q(n4083) );
XOR3X1 U4825 ( .IN1(\fpu_add_exp_dp/n131 ), .IN2(\fpu_add_exp_dp/n118 ),
.IN3(n4666), .Q(n4087) );
NAND4X0 U4826 ( .IN1(n4081), .IN2(n4667), .IN3(n4668), .IN4(n270), .QN(n4663) );
OR2X1 U4827 ( .IN1(n4669), .IN2(\fpu_add_ctl/n130 ), .Q(n4668) );
INVX0 U4828 ( .INP(n4074), .ZN(n4667) );
XOR3X1 U4829 ( .IN1(\fpu_add_exp_dp/n135 ), .IN2(\fpu_add_exp_dp/n122 ),
.IN3(n128), .Q(n4074) );
XNOR3X1 U4830 ( .IN1(\fpu_add_exp_dp/n134 ), .IN2(\fpu_add_exp_dp/n121 ),
.IN3(n4670), .Q(n4081) );
NOR4X0 U4831 ( .IN1(n4091), .IN2(n4093), .IN3(n4099), .IN4(n4104), .QN(n4661) );
XOR3X1 U4832 ( .IN1(\fpu_add_exp_dp/n127 ), .IN2(\fpu_add_exp_dp/n114 ),
.IN3(n4671), .Q(n4104) );
XOR3X1 U4833 ( .IN1(\fpu_add_exp_dp/n128 ), .IN2(\fpu_add_exp_dp/n115 ),
.IN3(n4672), .Q(n4099) );
XOR3X1 U4834 ( .IN1(\fpu_add_exp_dp/n129 ), .IN2(\fpu_add_exp_dp/n116 ),
.IN3(n4673), .Q(n4093) );
XOR3X1 U4835 ( .IN1(\fpu_add_exp_dp/n130 ), .IN2(\fpu_add_exp_dp/n117 ),
.IN3(n4674), .Q(n4091) );
NOR2X0 U4836 ( .IN1(n4107), .IN2(n4110), .QN(n4659) );
XOR3X1 U4837 ( .IN1(\fpu_add_exp_dp/n125 ), .IN2(\fpu_add_exp_dp/n112 ),
.IN3(n4675), .Q(n4110) );
XOR3X1 U4838 ( .IN1(\fpu_add_exp_dp/n126 ), .IN2(\fpu_add_exp_dp/n113 ),
.IN3(n4676), .Q(n4107) );
AND2X1 U4839 ( .IN1(\fpu_add_ctl/n329 ), .IN2(n4111), .Q(n1932) );
AO22X1 U4840 ( .IN1(n1338), .IN2(n1077), .IN3(n1471), .IN4(n137), .Q(
\fpu_add_ctl/n556 ) );
OAI22X1 U4841 ( .IN1(n4111), .IN2(n4057), .IN3(n4114), .IN4(
\fpu_add_ctl/n16 ), .QN(\fpu_add_ctl/n555 ) );
XNOR3X1 U4842 ( .IN1(\fpu_add_exp_dp/n124 ), .IN2(n629), .IN3(n3968), .Q(
n4111) );
INVX0 U4843 ( .INP(n3967), .ZN(n3968) );
AO22X1 U4844 ( .IN1(n4675), .IN2(n298), .IN3(n4677), .IN4(n680), .Q(n3967)
);
OR2X1 U4845 ( .IN1(n298), .IN2(n4675), .Q(n4677) );
AO22X1 U4846 ( .IN1(n4676), .IN2(n300), .IN3(n4678), .IN4(n681), .Q(n4675)
);
OR2X1 U4847 ( .IN1(n300), .IN2(n4676), .Q(n4678) );
AO22X1 U4848 ( .IN1(n4671), .IN2(n301), .IN3(n4679), .IN4(n682), .Q(n4676)
);
OR2X1 U4849 ( .IN1(n301), .IN2(n4671), .Q(n4679) );
AO22X1 U4850 ( .IN1(n4672), .IN2(n308), .IN3(n4680), .IN4(n683), .Q(n4671)
);
OR2X1 U4851 ( .IN1(n308), .IN2(n4672), .Q(n4680) );
AO22X1 U4852 ( .IN1(n4673), .IN2(n302), .IN3(n4681), .IN4(n661), .Q(n4672)
);
OR2X1 U4853 ( .IN1(n302), .IN2(n4673), .Q(n4681) );
AO22X1 U4854 ( .IN1(n4674), .IN2(n299), .IN3(n4682), .IN4(n684), .Q(n4673)
);
OR2X1 U4855 ( .IN1(n299), .IN2(n4674), .Q(n4682) );
AO22X1 U4856 ( .IN1(n4666), .IN2(n303), .IN3(n4683), .IN4(n685), .Q(n4674)
);
OR2X1 U4857 ( .IN1(n303), .IN2(n4666), .Q(n4683) );
AO22X1 U4858 ( .IN1(n4664), .IN2(n304), .IN3(n4684), .IN4(n686), .Q(n4666)
);
OR2X1 U4859 ( .IN1(n304), .IN2(n4664), .Q(n4684) );
AO22X1 U4860 ( .IN1(n4665), .IN2(n305), .IN3(n4685), .IN4(n687), .Q(n4664)
);
OR2X1 U4861 ( .IN1(n305), .IN2(n4665), .Q(n4685) );
AO22X1 U4862 ( .IN1(n4670), .IN2(n297), .IN3(n4686), .IN4(n676), .Q(n4665)
);
OR2X1 U4863 ( .IN1(n297), .IN2(n4670), .Q(n4686) );
AO22X1 U4864 ( .IN1(n128), .IN2(n830), .IN3(n4687), .IN4(n315), .Q(n4670) );
NAND2X0 U4865 ( .IN1(\fpu_add_exp_dp/n122 ), .IN2(\fpu_add_ctl/n129 ), .QN(
n4687) );
AO22X1 U4866 ( .IN1(n4000), .IN2(n1249), .IN3(n1339), .IN4(n4688), .Q(
\fpu_add_ctl/n554 ) );
AO22X1 U4867 ( .IN1(n3753), .IN2(n1008), .IN3(n3754), .IN4(n547), .Q(n4688)
);
AO22X1 U4868 ( .IN1(n4000), .IN2(n1272), .IN3(n4689), .IN4(n1339), .Q(
\fpu_add_ctl/n553 ) );
OA21X1 U4869 ( .IN1(n4690), .IN2(n4691), .IN3(n4692), .Q(n4689) );
OAI22X1 U4870 ( .IN1(n3753), .IN2(\fpu_add_ctl/n110 ), .IN3(n3754), .IN4(
\fpu_add_ctl/n109 ), .QN(n4692) );
OR4X1 U4871 ( .IN1(n3753), .IN2(n221), .IN3(n35), .IN4(n88), .Q(n3754) );
NAND2X0 U4872 ( .IN1(\fpu_add_exp_dp/n136 ), .IN2(\fpu_add_exp_dp/n137 ),
.QN(n3753) );
NAND4X0 U4873 ( .IN1(n4669), .IN2(n4660), .IN3(\fpu_add_frac_dp/n2498 ),
.IN4(n1924), .QN(n4691) );
NOR2X0 U4874 ( .IN1(n646), .IN2(n290), .QN(n1924) );
INVX0 U4875 ( .INP(n4693), .ZN(n4660) );
NAND4X0 U4876 ( .IN1(\fpu_add_exp_dp/n143 ), .IN2(\fpu_add_exp_dp/n145 ),
.IN3(\fpu_add_exp_dp/n146 ), .IN4(n1929), .QN(n4690) );
AO22X1 U4877 ( .IN1(n4000), .IN2(n1265), .IN3(n4694), .IN4(n4695), .Q(
\fpu_add_ctl/n552 ) );
NOR4X0 U4878 ( .IN1(n4696), .IN2(n4669), .IN3(\fpu_add_ctl/n316 ), .IN4(
\fpu_add_ctl/n133 ), .QN(n4695) );
NOR4X0 U4879 ( .IN1(n4697), .IN2(n4698), .IN3(n4699), .IN4(n4700), .QN(n4669) );
NAND4X0 U4880 ( .IN1(\fpu_add_frac_dp/n2434 ), .IN2(\fpu_add_frac_dp/n2433 ),
.IN3(n4701), .IN4(\fpu_add_frac_dp/n2297 ), .QN(n4700) );
NOR2X0 U4881 ( .IN1(n722), .IN2(n423), .QN(n4701) );
NAND4X0 U4882 ( .IN1(\fpu_add_frac_dp/n2277 ), .IN2(n904), .IN3(
\fpu_add_frac_dp/n2304 ), .IN4(n4702), .QN(n4699) );
AND3X1 U4883 ( .IN1(\fpu_add_frac_dp/n2432 ), .IN2(\fpu_add_frac_dp/n2362 ),
.IN3(\fpu_add_frac_dp/n2359 ), .Q(n4702) );
NAND4X0 U4884 ( .IN1(\fpu_add_frac_dp/n2510 ), .IN2(\fpu_add_frac_dp/n2503 ),
.IN3(n4703), .IN4(\fpu_add_frac_dp/n2499 ), .QN(n4698) );
NOR2X0 U4885 ( .IN1(n723), .IN2(n424), .QN(n4703) );
NAND4X0 U4886 ( .IN1(\fpu_add_frac_dp/n2299 ), .IN2(\fpu_add_frac_dp/n2420 ),
.IN3(n4704), .IN4(\fpu_add_frac_dp/n2273 ), .QN(n4697) );
NOR2X0 U4887 ( .IN1(n724), .IN2(n426), .QN(n4704) );
NAND3X0 U4888 ( .IN1(n648), .IN2(n73), .IN3(n289), .QN(n4696) );
NOR4X0 U4889 ( .IN1(n4705), .IN2(n4693), .IN3(n725), .IN4(n4057), .QN(n4694)
);
NAND4X0 U4890 ( .IN1(n4706), .IN2(n4707), .IN3(n4708), .IN4(n4709), .QN(
n4693) );
NOR4X0 U4891 ( .IN1(n4710), .IN2(n4711), .IN3(n4712), .IN4(n4713), .QN(n4709) );
NAND4X0 U4892 ( .IN1(\fpu_add_frac_dp/n2276 ), .IN2(\fpu_add_frac_dp/n2302 ),
.IN3(\fpu_add_frac_dp/n2422 ), .IN4(\fpu_add_frac_dp/n2355 ), .QN(
n4713) );
NAND4X0 U4893 ( .IN1(\fpu_add_frac_dp/n2275 ), .IN2(\fpu_add_frac_dp/n2301 ),
.IN3(\fpu_add_frac_dp/n2421 ), .IN4(\fpu_add_frac_dp/n2511 ), .QN(
n4712) );
NAND4X0 U4894 ( .IN1(\fpu_add_frac_dp/n2435 ), .IN2(\fpu_add_frac_dp/n2354 ),
.IN3(\fpu_add_frac_dp/n2274 ), .IN4(\fpu_add_frac_dp/n2300 ), .QN(
n4711) );
NAND4X0 U4895 ( .IN1(n1009), .IN2(n561), .IN3(n153), .IN4(n62), .QN(n4710)
);
NOR4X0 U4896 ( .IN1(n4714), .IN2(n142), .IN3(n343), .IN4(n706), .QN(n4708)
);
NAND4X0 U4897 ( .IN1(\fpu_add_frac_dp/n2431 ), .IN2(\fpu_add_frac_dp/n2418 ),
.IN3(\fpu_add_frac_dp/n2351 ), .IN4(\fpu_add_frac_dp/n2505 ), .QN(
n4714) );
NOR4X0 U4898 ( .IN1(n58), .IN2(n143), .IN3(n344), .IN4(n707), .QN(n4707) );
NOR4X0 U4899 ( .IN1(n59), .IN2(n144), .IN3(n345), .IN4(n708), .QN(n4706) );
NAND3X0 U4900 ( .IN1(n1901), .IN2(n1929), .IN3(n1920), .QN(n4705) );
NOR2X0 U4901 ( .IN1(n646), .IN2(\fpu_add_exp_dp/n144 ), .QN(n1920) );
NOR4X0 U4902 ( .IN1(n711), .IN2(n221), .IN3(n35), .IN4(n88), .QN(n1929) );
NOR2X0 U4903 ( .IN1(\fpu_add_exp_dp/n147 ), .IN2(\fpu_add_exp_dp/n145 ),
.QN(n1901) );
AO22X1 U4904 ( .IN1(n1340), .IN2(n140), .IN3(n1471), .IN4(n512), .Q(
\fpu_add_ctl/n551 ) );
AO222X1 U4905 ( .IN1(n1472), .IN2(n1074), .IN3(n4715), .IN4(n140), .IN5(
n4716), .IN6(n512), .Q(\fpu_add_ctl/n550 ) );
AO22X1 U4906 ( .IN1(n1337), .IN2(n137), .IN3(n1471), .IN4(n905), .Q(
\fpu_add_ctl/n549 ) );
AO222X1 U4907 ( .IN1(n1472), .IN2(n452), .IN3(n4715), .IN4(n137), .IN5(n4716), .IN6(n905), .Q(\fpu_add_ctl/n548 ) );
AO22X1 U4908 ( .IN1(n1339), .IN2(n4717), .IN3(n1471), .IN4(n513), .Q(
\fpu_add_ctl/n547 ) );
AO222X1 U4909 ( .IN1(n1472), .IN2(n1245), .IN3(n4715), .IN4(n4717), .IN5(
n4716), .IN6(n513), .Q(\fpu_add_ctl/n546 ) );
AOI21X1 U4910 ( .IN1(\fpu_add_ctl/n102 ), .IN2(\fpu_add_ctl/n325 ), .IN3(
n4057), .QN(n4716) );
OAI21X1 U4911 ( .IN1(\fpu_add_ctl/n16 ), .IN2(n4718), .IN3(\fpu_add_ctl/n13 ), .QN(n4717) );
OA21X1 U4912 ( .IN1(\fpu_add_ctl/n15 ), .IN2(n4719), .IN3(\fpu_add_ctl/n14 ),
.Q(n4718) );
OA21X1 U4913 ( .IN1(\fpu_add_frac_dp/n510 ), .IN2(\fpu_add_ctl/n97 ), .IN3(
\fpu_add_frac_dp/n515 ), .Q(n4719) );
AND3X1 U4914 ( .IN1(\fpu_add_ctl/n325 ), .IN2(n1340), .IN3(
\fpu_add_ctl/n102 ), .Q(n4715) );
AO22X1 U4915 ( .IN1(n1338), .IN2(n1074), .IN3(n1472), .IN4(add_exc_out[4]),
.Q(\fpu_add_ctl/n545 ) );
AO21X1 U4916 ( .IN1(n1468), .IN2(n1234), .IN3(n4720), .Q(\fpu_add_ctl/n544 )
);
NOR4X0 U4917 ( .IN1(n4721), .IN2(n4722), .IN3(n4723), .IN4(n4057), .QN(n4720) );
OA22X1 U4918 ( .IN1(\fpu_add_frac_dp/n582 ), .IN2(n4724), .IN3(
\fpu_add_ctl/n941 ), .IN4(\fpu_add_ctl/n89 ), .Q(n4722) );
INVX0 U4919 ( .INP(n4182), .ZN(n4721) );
AO22X1 U4920 ( .IN1(n4210), .IN2(n21), .IN3(n4725), .IN4(n4211), .Q(n4182)
);
AO21X1 U4921 ( .IN1(n4726), .IN2(n4727), .IN3(n4728), .Q(n4211) );
NOR4X0 U4922 ( .IN1(\fpu_add_ctl/n307 ), .IN2(n2880), .IN3(n4729), .IN4(n291), .QN(n4728) );
NOR2X0 U4923 ( .IN1(n2984), .IN2(n4730), .QN(n4729) );
INVX0 U4924 ( .INP(n2983), .ZN(n2880) );
AO21X1 U4925 ( .IN1(n55), .IN2(n452), .IN3(n148), .Q(n4725) );
AO22X1 U4926 ( .IN1(n4726), .IN2(n4731), .IN3(n4732), .IN4(n2973), .Q(n4210)
);
NAND2X0 U4927 ( .IN1(n4733), .IN2(n4734), .QN(n4732) );
NAND3X0 U4928 ( .IN1(n4735), .IN2(n1084), .IN3(\fpu_add_ctl/n937 ), .QN(
n4734) );
INVX0 U4929 ( .INP(n4733), .ZN(n4726) );
NAND2X0 U4930 ( .IN1(n4736), .IN2(n291), .QN(n4733) );
XOR2X1 U4931 ( .IN1(\fpu_add_ctl/n337 ), .IN2(\fpu_add_ctl/n307 ), .Q(n4736)
);
OAI22X1 U4932 ( .IN1(n4057), .IN2(n2959), .IN3(n4114), .IN4(\fpu_add_ctl/n4 ), .QN(\fpu_add_ctl/n543 ) );
OA21X1 U4933 ( .IN1(\fpu_add_ctl/n9 ), .IN2(n4737), .IN3(n4738), .Q(n2959)
);
OR3X1 U4934 ( .IN1(n4213), .IN2(n4724), .IN3(n4723), .Q(n4738) );
NAND4X0 U4935 ( .IN1(n4214), .IN2(n4136), .IN3(n4739), .IN4(n4740), .QN(
n4723) );
NOR4X0 U4936 ( .IN1(\fpu_add_ctl/n9 ), .IN2(n4154), .IN3(n4160), .IN4(n4148),
.QN(n4740) );
INVX0 U4937 ( .INP(n4194), .ZN(n4148) );
INVX0 U4938 ( .INP(n4219), .ZN(n4154) );
NOR2X0 U4939 ( .IN1(n4166), .IN2(n4142), .QN(n4739) );
INVX0 U4940 ( .INP(n4218), .ZN(n4142) );
AND2X1 U4941 ( .IN1(\fpu_add_ctl/n941 ), .IN2(n4741), .Q(n4724) );
NAND4X0 U4942 ( .IN1(n4215), .IN2(n4172), .IN3(n4212), .IN4(n21), .QN(n4741)
);
INVX0 U4943 ( .INP(n4184), .ZN(n4213) );
OA22X1 U4944 ( .IN1(n4742), .IN2(n4743), .IN3(\fpu_add_ctl/n941 ), .IN4(
n4744), .Q(n4737) );
NOR2X0 U4945 ( .IN1(n21), .IN2(n420), .QN(n4743) );
INVX0 U4946 ( .INP(n4264), .ZN(n4742) );
NAND4X0 U4947 ( .IN1(\fpu_add_exp_dp/n98 ), .IN2(\fpu_add_exp_dp/n85 ),
.IN3(\fpu_add_exp_dp/n61 ), .IN4(\fpu_add_exp_dp/n60 ), .QN(n4264) );
OAI22X1 U4948 ( .IN1(\fpu_add_ctl/n3 ), .IN2(n4114), .IN3(n4745), .IN4(n4057), .QN(\fpu_add_ctl/n542 ) );
OA21X1 U4949 ( .IN1(n4746), .IN2(n4747), .IN3(n4748), .Q(n4745) );
NAND4X0 U4950 ( .IN1(\fpu_add_frac_dp/n596 ), .IN2(\fpu_add_ctl/n89 ), .IN3(
n2960), .IN4(n4749), .QN(n4748) );
NAND4X0 U4951 ( .IN1(n4750), .IN2(n4751), .IN3(n4752), .IN4(n4753), .QN(
n4749) );
NOR4X0 U4952 ( .IN1(n4754), .IN2(n4755), .IN3(n4756), .IN4(n4757), .QN(n4753) );
NAND4X0 U4953 ( .IN1(\fpu_add_frac_dp/n210 ), .IN2(\fpu_add_frac_dp/n208 ),
.IN3(\fpu_add_frac_dp/n206 ), .IN4(\fpu_add_frac_dp/n204 ), .QN(n4757)
);
NAND4X0 U4954 ( .IN1(\fpu_add_frac_dp/n202 ), .IN2(\fpu_add_frac_dp/n200 ),
.IN3(\fpu_add_frac_dp/n198 ), .IN4(\fpu_add_frac_dp/n196 ), .QN(n4756)
);
NAND4X0 U4955 ( .IN1(\fpu_add_frac_dp/n194 ), .IN2(\fpu_add_frac_dp/n192 ),
.IN3(\fpu_add_frac_dp/n190 ), .IN4(\fpu_add_frac_dp/n188 ), .QN(n4755)
);
NAND4X0 U4956 ( .IN1(\fpu_add_frac_dp/n2358 ), .IN2(\fpu_add_frac_dp/n2291 ),
.IN3(\fpu_add_frac_dp/n2360 ), .IN4(\fpu_add_frac_dp/n2292 ), .QN(
n4754) );
NOR4X0 U4957 ( .IN1(n4758), .IN2(n4759), .IN3(n4760), .IN4(n4761), .QN(n4752) );
NAND4X0 U4958 ( .IN1(\fpu_add_frac_dp/n2347 ), .IN2(\fpu_add_frac_dp/n2346 ),
.IN3(\fpu_add_frac_dp/n234 ), .IN4(\fpu_add_frac_dp/n232 ), .QN(n4761)
);
NAND4X0 U4959 ( .IN1(\fpu_add_frac_dp/n230 ), .IN2(\fpu_add_frac_dp/n2294 ),
.IN3(\fpu_add_frac_dp/n2293 ), .IN4(\fpu_add_frac_dp/n228 ), .QN(n4760) );
NAND4X0 U4960 ( .IN1(\fpu_add_frac_dp/n226 ), .IN2(\fpu_add_frac_dp/n224 ),
.IN3(\fpu_add_frac_dp/n222 ), .IN4(\fpu_add_frac_dp/n220 ), .QN(n4759)
);
NAND4X0 U4961 ( .IN1(\fpu_add_frac_dp/n218 ), .IN2(\fpu_add_frac_dp/n216 ),
.IN3(\fpu_add_frac_dp/n214 ), .IN4(\fpu_add_frac_dp/n212 ), .QN(n4758)
);
NOR4X0 U4962 ( .IN1(n4762), .IN2(n4763), .IN3(n4764), .IN4(n4765), .QN(n4751) );
NAND4X0 U4963 ( .IN1(\fpu_add_frac_dp/n250 ), .IN2(\fpu_add_frac_dp/n248 ),
.IN3(\fpu_add_frac_dp/n246 ), .IN4(\fpu_add_frac_dp/n244 ), .QN(n4765)
);
NAND4X0 U4964 ( .IN1(\fpu_add_frac_dp/n242 ), .IN2(\fpu_add_frac_dp/n2417 ),
.IN3(\fpu_add_frac_dp/n2414 ), .IN4(\fpu_add_frac_dp/n2413 ), .QN(
n4764) );
NAND4X0 U4965 ( .IN1(\fpu_add_frac_dp/n2412 ), .IN2(\fpu_add_frac_dp/n2410 ),
.IN3(\fpu_add_frac_dp/n2401 ), .IN4(\fpu_add_frac_dp/n240 ), .QN(n4763) );
NAND4X0 U4966 ( .IN1(\fpu_add_frac_dp/n238 ), .IN2(\fpu_add_frac_dp/n236 ),
.IN3(\fpu_add_frac_dp/n2349 ), .IN4(\fpu_add_frac_dp/n2348 ), .QN(
n4762) );
NOR4X0 U4967 ( .IN1(n4766), .IN2(n4767), .IN3(n4768), .IN4(n4769), .QN(n4750) );
NAND4X0 U4968 ( .IN1(\fpu_add_frac_dp/n282 ), .IN2(\fpu_add_frac_dp/n280 ),
.IN3(\fpu_add_frac_dp/n278 ), .IN4(\fpu_add_frac_dp/n276 ), .QN(n4769)
);
NAND4X0 U4969 ( .IN1(\fpu_add_frac_dp/n274 ), .IN2(\fpu_add_frac_dp/n272 ),
.IN3(\fpu_add_frac_dp/n270 ), .IN4(\fpu_add_frac_dp/n268 ), .QN(n4768)
);
NAND4X0 U4970 ( .IN1(\fpu_add_frac_dp/n266 ), .IN2(\fpu_add_frac_dp/n264 ),
.IN3(\fpu_add_frac_dp/n262 ), .IN4(\fpu_add_frac_dp/n260 ), .QN(n4767)
);
NAND4X0 U4971 ( .IN1(\fpu_add_frac_dp/n258 ), .IN2(\fpu_add_frac_dp/n256 ),
.IN3(\fpu_add_frac_dp/n254 ), .IN4(\fpu_add_frac_dp/n252 ), .QN(n4766)
);
NOR2X0 U4972 ( .IN1(n296), .IN2(\fpu_add_ctl/n939 ), .QN(n2960) );
NAND4X0 U4973 ( .IN1(n4166), .IN2(n4160), .IN3(n4744), .IN4(n4770), .QN(
n4747) );
NOR3X0 U4974 ( .IN1(n4219), .IN2(n4218), .IN3(n4194), .QN(n4770) );
NAND4X0 U4975 ( .IN1(\fpu_add_exp_dp/n92 ), .IN2(\fpu_add_exp_dp/n75 ),
.IN3(\fpu_add_exp_dp/n74 ), .IN4(\fpu_add_exp_dp/n105 ), .QN(n4194) );
NAND4X0 U4976 ( .IN1(\fpu_add_exp_dp/n93 ), .IN2(\fpu_add_exp_dp/n77 ),
.IN3(\fpu_add_exp_dp/n76 ), .IN4(\fpu_add_exp_dp/n106 ), .QN(n4218) );
NAND4X0 U4977 ( .IN1(\fpu_add_exp_dp/n91 ), .IN2(\fpu_add_exp_dp/n73 ),
.IN3(\fpu_add_exp_dp/n72 ), .IN4(\fpu_add_exp_dp/n104 ), .QN(n4219) );
NOR3X0 U4978 ( .IN1(n4172), .IN2(n4215), .IN3(n4212), .QN(n4744) );
NAND4X0 U4979 ( .IN1(\fpu_add_exp_dp/n87 ), .IN2(\fpu_add_exp_dp/n65 ),
.IN3(\fpu_add_exp_dp/n64 ), .IN4(\fpu_add_exp_dp/n100 ), .QN(n4212) );
NAND4X0 U4980 ( .IN1(\fpu_add_exp_dp/n99 ), .IN2(\fpu_add_exp_dp/n86 ),
.IN3(\fpu_add_exp_dp/n63 ), .IN4(\fpu_add_exp_dp/n62 ), .QN(n4215) );
NAND4X0 U4981 ( .IN1(\fpu_add_exp_dp/n88 ), .IN2(\fpu_add_exp_dp/n67 ),
.IN3(\fpu_add_exp_dp/n66 ), .IN4(\fpu_add_exp_dp/n101 ), .QN(n4172) );
INVX0 U4982 ( .INP(n4199), .ZN(n4160) );
NAND4X0 U4983 ( .IN1(\fpu_add_exp_dp/n90 ), .IN2(\fpu_add_exp_dp/n71 ),
.IN3(\fpu_add_exp_dp/n70 ), .IN4(\fpu_add_exp_dp/n103 ), .QN(n4199) );
INVX0 U4984 ( .INP(n4220), .ZN(n4166) );
NAND4X0 U4985 ( .IN1(\fpu_add_exp_dp/n89 ), .IN2(\fpu_add_exp_dp/n69 ),
.IN3(\fpu_add_exp_dp/n68 ), .IN4(\fpu_add_exp_dp/n102 ), .QN(n4220) );
NAND4X0 U4986 ( .IN1(n4771), .IN2(n490), .IN3(n4772), .IN4(n4773), .QN(n4746) );
NOR3X0 U4987 ( .IN1(n4136), .IN2(n4184), .IN3(n4214), .QN(n4773) );
NAND4X0 U4988 ( .IN1(\fpu_add_exp_dp/n95 ), .IN2(\fpu_add_exp_dp/n81 ),
.IN3(\fpu_add_exp_dp/n80 ), .IN4(\fpu_add_exp_dp/n108 ), .QN(n4214) );
NAND4X0 U4989 ( .IN1(\fpu_add_exp_dp/n96 ), .IN2(\fpu_add_exp_dp/n83 ),
.IN3(\fpu_add_exp_dp/n82 ), .IN4(\fpu_add_exp_dp/n109 ), .QN(n4184) );
NAND4X0 U4990 ( .IN1(\fpu_add_exp_dp/n94 ), .IN2(\fpu_add_exp_dp/n79 ),
.IN3(\fpu_add_exp_dp/n78 ), .IN4(\fpu_add_exp_dp/n107 ), .QN(n4136) );
NAND2X0 U4991 ( .IN1(\fpu_add_ctl/n89 ), .IN2(\fpu_add_frac_dp/n582 ), .QN(
n4772) );
NAND4X0 U4992 ( .IN1(n4774), .IN2(n4775), .IN3(n4776), .IN4(n4777), .QN(
n4771) );
NOR4X0 U4993 ( .IN1(n4778), .IN2(n2904), .IN3(n2898), .IN4(n2902), .QN(n4777) );
NAND3X0 U4994 ( .IN1(\fpu_add_frac_dp/n333 ), .IN2(\fpu_add_frac_dp/n223 ),
.IN3(\fpu_add_frac_dp/n414 ), .QN(n2902) );
NAND3X0 U4995 ( .IN1(\fpu_add_frac_dp/n334 ), .IN2(\fpu_add_frac_dp/n225 ),
.IN3(\fpu_add_frac_dp/n416 ), .QN(n2898) );
NAND3X0 U4996 ( .IN1(\fpu_add_frac_dp/n332 ), .IN2(\fpu_add_frac_dp/n221 ),
.IN3(\fpu_add_frac_dp/n412 ), .QN(n2904) );
OR4X1 U4997 ( .IN1(n2896), .IN2(n2891), .IN3(n2888), .IN4(n2984), .Q(n4778)
);
NAND3X0 U4998 ( .IN1(\fpu_add_frac_dp/n338 ), .IN2(\fpu_add_frac_dp/n233 ),
.IN3(\fpu_add_frac_dp/n424 ), .QN(n2984) );
NAND3X0 U4999 ( .IN1(\fpu_add_frac_dp/n337 ), .IN2(\fpu_add_frac_dp/n231 ),
.IN3(\fpu_add_frac_dp/n422 ), .QN(n2888) );
NAND3X0 U5000 ( .IN1(\fpu_add_frac_dp/n336 ), .IN2(\fpu_add_frac_dp/n229 ),
.IN3(\fpu_add_frac_dp/n420 ), .QN(n2891) );
NAND3X0 U5001 ( .IN1(\fpu_add_frac_dp/n335 ), .IN2(\fpu_add_frac_dp/n227 ),
.IN3(\fpu_add_frac_dp/n418 ), .QN(n2896) );
NOR4X0 U5002 ( .IN1(n4779), .IN2(n2914), .IN3(n2908), .IN4(n2910), .QN(n4776) );
NAND3X0 U5003 ( .IN1(\fpu_add_frac_dp/n330 ), .IN2(\fpu_add_frac_dp/n217 ),
.IN3(\fpu_add_frac_dp/n408 ), .QN(n2910) );
NAND3X0 U5004 ( .IN1(\fpu_add_frac_dp/n331 ), .IN2(\fpu_add_frac_dp/n219 ),
.IN3(\fpu_add_frac_dp/n410 ), .QN(n2908) );
NAND3X0 U5005 ( .IN1(\fpu_add_frac_dp/n329 ), .IN2(\fpu_add_frac_dp/n215 ),
.IN3(\fpu_add_frac_dp/n406 ), .QN(n2914) );
OR3X1 U5006 ( .IN1(n2920), .IN2(n2916), .IN3(n2922), .Q(n4779) );
NAND3X0 U5007 ( .IN1(\fpu_add_frac_dp/n326 ), .IN2(\fpu_add_frac_dp/n209 ),
.IN3(\fpu_add_frac_dp/n400 ), .QN(n2922) );
NAND3X0 U5008 ( .IN1(\fpu_add_frac_dp/n328 ), .IN2(\fpu_add_frac_dp/n213 ),
.IN3(\fpu_add_frac_dp/n404 ), .QN(n2916) );
NAND3X0 U5009 ( .IN1(\fpu_add_frac_dp/n327 ), .IN2(\fpu_add_frac_dp/n211 ),
.IN3(\fpu_add_frac_dp/n402 ), .QN(n2920) );
NOR4X0 U5010 ( .IN1(n4780), .IN2(n2932), .IN3(n2926), .IN4(n2928), .QN(n4775) );
NAND3X0 U5011 ( .IN1(\fpu_add_frac_dp/n324 ), .IN2(\fpu_add_frac_dp/n205 ),
.IN3(\fpu_add_frac_dp/n396 ), .QN(n2928) );
NAND3X0 U5012 ( .IN1(\fpu_add_frac_dp/n325 ), .IN2(\fpu_add_frac_dp/n207 ),
.IN3(\fpu_add_frac_dp/n398 ), .QN(n2926) );
NAND3X0 U5013 ( .IN1(\fpu_add_frac_dp/n323 ), .IN2(\fpu_add_frac_dp/n203 ),
.IN3(\fpu_add_frac_dp/n394 ), .QN(n2932) );
OR3X1 U5014 ( .IN1(n2985), .IN2(n2940), .IN3(n2942), .Q(n4780) );
NAND3X0 U5015 ( .IN1(\fpu_add_frac_dp/n320 ), .IN2(\fpu_add_frac_dp/n197 ),
.IN3(\fpu_add_frac_dp/n388 ), .QN(n2942) );
NAND3X0 U5016 ( .IN1(\fpu_add_frac_dp/n322 ), .IN2(\fpu_add_frac_dp/n201 ),
.IN3(\fpu_add_frac_dp/n392 ), .QN(n2940) );
NAND3X0 U5017 ( .IN1(\fpu_add_frac_dp/n321 ), .IN2(\fpu_add_frac_dp/n199 ),
.IN3(\fpu_add_frac_dp/n390 ), .QN(n2985) );
NOR4X0 U5018 ( .IN1(n4781), .IN2(n2952), .IN3(n2946), .IN4(n2948), .QN(n4774) );
NAND3X0 U5019 ( .IN1(\fpu_add_frac_dp/n318 ), .IN2(\fpu_add_frac_dp/n193 ),
.IN3(\fpu_add_frac_dp/n384 ), .QN(n2948) );
NAND3X0 U5020 ( .IN1(\fpu_add_frac_dp/n319 ), .IN2(\fpu_add_frac_dp/n195 ),
.IN3(\fpu_add_frac_dp/n386 ), .QN(n2946) );
NAND3X0 U5021 ( .IN1(\fpu_add_frac_dp/n317 ), .IN2(\fpu_add_frac_dp/n191 ),
.IN3(\fpu_add_frac_dp/n382 ), .QN(n2952) );
NAND3X0 U5022 ( .IN1(n3174), .IN2(n2986), .IN3(n4782), .QN(n4781) );
INVX0 U5023 ( .INP(n2956), .ZN(n2986) );
NAND3X0 U5024 ( .IN1(\fpu_add_frac_dp/n316 ), .IN2(\fpu_add_frac_dp/n189 ),
.IN3(\fpu_add_frac_dp/n380 ), .QN(n2956) );
INVX0 U5025 ( .INP(n2987), .ZN(n3174) );
NAND3X0 U5026 ( .IN1(\fpu_add_frac_dp/n315 ), .IN2(\fpu_add_frac_dp/n187 ),
.IN3(\fpu_add_frac_dp/n378 ), .QN(n2987) );
OAI22X1 U5027 ( .IN1(\fpu_add_ctl/n2 ), .IN2(n4114), .IN3(n4783), .IN4(n4057), .QN(\fpu_add_ctl/n541 ) );
OA21X1 U5028 ( .IN1(\fpu_add_ctl/n9 ), .IN2(n4784), .IN3(\fpu_add_ctl/n7 ),
.Q(n4783) );
OA21X1 U5029 ( .IN1(n4785), .IN2(n4786), .IN3(n4787), .Q(n4784) );
NAND3X0 U5030 ( .IN1(n4727), .IN2(n2884), .IN3(n4788), .QN(n4787) );
NAND2X0 U5031 ( .IN1(\fpu_add_frac_dp/n582 ), .IN2(n148), .QN(n4788) );
NAND2X0 U5032 ( .IN1(\fpu_add_ctl/n941 ), .IN2(\fpu_add_ctl/n77 ), .QN(n2884) );
INVX0 U5033 ( .INP(n4782), .ZN(n4727) );
NOR2X0 U5034 ( .IN1(n4730), .IN2(n2983), .QN(n4782) );
NAND3X0 U5035 ( .IN1(\fpu_add_frac_dp/n339 ), .IN2(\fpu_add_frac_dp/n235 ),
.IN3(\fpu_add_frac_dp/n426 ), .QN(n2983) );
NAND4X0 U5036 ( .IN1(n4789), .IN2(n4790), .IN3(n4791), .IN4(n4792), .QN(
n4730) );
NOR2X0 U5037 ( .IN1(n4793), .IN2(n4794), .QN(n4792) );
NAND4X0 U5038 ( .IN1(n2813), .IN2(n2809), .IN3(n2806), .IN4(n2804), .QN(
n4794) );
INVX0 U5039 ( .INP(n2800), .ZN(n2804) );
NAND3X0 U5040 ( .IN1(\fpu_add_frac_dp/n362 ), .IN2(\fpu_add_frac_dp/n281 ),
.IN3(\fpu_add_frac_dp/n472 ), .QN(n2800) );
INVX0 U5041 ( .INP(n2974), .ZN(n2806) );
NAND3X0 U5042 ( .IN1(\fpu_add_frac_dp/n361 ), .IN2(\fpu_add_frac_dp/n279 ),
.IN3(\fpu_add_frac_dp/n470 ), .QN(n2974) );
INVX0 U5043 ( .INP(n2975), .ZN(n2809) );
NAND3X0 U5044 ( .IN1(\fpu_add_frac_dp/n360 ), .IN2(\fpu_add_frac_dp/n277 ),
.IN3(\fpu_add_frac_dp/n468 ), .QN(n2975) );
INVX0 U5045 ( .INP(n2976), .ZN(n2813) );
NAND3X0 U5046 ( .IN1(\fpu_add_frac_dp/n359 ), .IN2(\fpu_add_frac_dp/n275 ),
.IN3(\fpu_add_frac_dp/n466 ), .QN(n2976) );
OR4X1 U5047 ( .IN1(n2798), .IN2(n2794), .IN3(n2792), .IN4(n2788), .Q(n4793)
);
NAND3X0 U5048 ( .IN1(\fpu_add_frac_dp/n366 ), .IN2(\fpu_add_frac_dp/n289 ),
.IN3(\fpu_add_frac_dp/n480 ), .QN(n2788) );
NAND3X0 U5049 ( .IN1(\fpu_add_frac_dp/n365 ), .IN2(\fpu_add_frac_dp/n287 ),
.IN3(\fpu_add_frac_dp/n478 ), .QN(n2792) );
NAND3X0 U5050 ( .IN1(\fpu_add_frac_dp/n364 ), .IN2(\fpu_add_frac_dp/n285 ),
.IN3(\fpu_add_frac_dp/n476 ), .QN(n2794) );
NAND3X0 U5051 ( .IN1(\fpu_add_frac_dp/n363 ), .IN2(\fpu_add_frac_dp/n283 ),
.IN3(\fpu_add_frac_dp/n474 ), .QN(n2798) );
NOR4X0 U5052 ( .IN1(n4795), .IN2(n2836), .IN3(n2830), .IN4(n2834), .QN(n4791) );
NAND3X0 U5053 ( .IN1(\fpu_add_frac_dp/n353 ), .IN2(\fpu_add_frac_dp/n263 ),
.IN3(\fpu_add_frac_dp/n454 ), .QN(n2834) );
NAND3X0 U5054 ( .IN1(\fpu_add_frac_dp/n354 ), .IN2(\fpu_add_frac_dp/n265 ),
.IN3(\fpu_add_frac_dp/n456 ), .QN(n2830) );
NAND3X0 U5055 ( .IN1(\fpu_add_frac_dp/n352 ), .IN2(\fpu_add_frac_dp/n261 ),
.IN3(\fpu_add_frac_dp/n452 ), .QN(n2836) );
NAND4X0 U5056 ( .IN1(n2828), .IN2(n2824), .IN3(n2821), .IN4(n2819), .QN(
n4795) );
INVX0 U5057 ( .INP(n2815), .ZN(n2819) );
NAND3X0 U5058 ( .IN1(\fpu_add_frac_dp/n358 ), .IN2(\fpu_add_frac_dp/n273 ),
.IN3(\fpu_add_frac_dp/n464 ), .QN(n2815) );
INVX0 U5059 ( .INP(n2977), .ZN(n2821) );
NAND3X0 U5060 ( .IN1(\fpu_add_frac_dp/n357 ), .IN2(\fpu_add_frac_dp/n271 ),
.IN3(\fpu_add_frac_dp/n462 ), .QN(n2977) );
INVX0 U5061 ( .INP(n2978), .ZN(n2824) );
NAND3X0 U5062 ( .IN1(\fpu_add_frac_dp/n356 ), .IN2(\fpu_add_frac_dp/n269 ),
.IN3(\fpu_add_frac_dp/n460 ), .QN(n2978) );
INVX0 U5063 ( .INP(n2979), .ZN(n2828) );
NAND3X0 U5064 ( .IN1(\fpu_add_frac_dp/n355 ), .IN2(\fpu_add_frac_dp/n267 ),
.IN3(\fpu_add_frac_dp/n458 ), .QN(n2979) );
NOR4X0 U5065 ( .IN1(n4796), .IN2(n2858), .IN3(n2852), .IN4(n2854), .QN(n4790) );
NAND3X0 U5066 ( .IN1(\fpu_add_frac_dp/n346 ), .IN2(\fpu_add_frac_dp/n249 ),
.IN3(\fpu_add_frac_dp/n440 ), .QN(n2854) );
NAND3X0 U5067 ( .IN1(\fpu_add_frac_dp/n347 ), .IN2(\fpu_add_frac_dp/n251 ),
.IN3(\fpu_add_frac_dp/n442 ), .QN(n2852) );
NAND3X0 U5068 ( .IN1(\fpu_add_frac_dp/n345 ), .IN2(\fpu_add_frac_dp/n247 ),
.IN3(\fpu_add_frac_dp/n438 ), .QN(n2858) );
OR4X1 U5069 ( .IN1(n2848), .IN2(n2846), .IN3(n2842), .IN4(n2840), .Q(n4796)
);
NAND3X0 U5070 ( .IN1(\fpu_add_frac_dp/n351 ), .IN2(\fpu_add_frac_dp/n259 ),
.IN3(\fpu_add_frac_dp/n450 ), .QN(n2840) );
NAND3X0 U5071 ( .IN1(\fpu_add_frac_dp/n350 ), .IN2(\fpu_add_frac_dp/n257 ),
.IN3(\fpu_add_frac_dp/n448 ), .QN(n2842) );
NAND3X0 U5072 ( .IN1(\fpu_add_frac_dp/n349 ), .IN2(\fpu_add_frac_dp/n255 ),
.IN3(\fpu_add_frac_dp/n446 ), .QN(n2846) );
NAND3X0 U5073 ( .IN1(\fpu_add_frac_dp/n348 ), .IN2(\fpu_add_frac_dp/n253 ),
.IN3(\fpu_add_frac_dp/n444 ), .QN(n2848) );
NOR4X0 U5074 ( .IN1(n4797), .IN2(n2973), .IN3(n2881), .IN4(n4735), .QN(n4789) );
OR2X1 U5075 ( .IN1(n4731), .IN2(n2786), .Q(n4735) );
NAND3X0 U5076 ( .IN1(\fpu_add_frac_dp/n367 ), .IN2(\fpu_add_frac_dp/n291 ),
.IN3(\fpu_add_frac_dp/n482 ), .QN(n2786) );
NAND3X0 U5077 ( .IN1(\fpu_add_frac_dp/n340 ), .IN2(\fpu_add_frac_dp/n237 ),
.IN3(\fpu_add_frac_dp/n428 ), .QN(n2881) );
NAND4X0 U5078 ( .IN1(n2873), .IN2(n2871), .IN3(n2865), .IN4(n2861), .QN(
n4797) );
INVX0 U5079 ( .INP(n2980), .ZN(n2861) );
NAND3X0 U5080 ( .IN1(\fpu_add_frac_dp/n344 ), .IN2(\fpu_add_frac_dp/n245 ),
.IN3(\fpu_add_frac_dp/n436 ), .QN(n2980) );
INVX0 U5081 ( .INP(n2981), .ZN(n2865) );
NAND3X0 U5082 ( .IN1(\fpu_add_frac_dp/n343 ), .IN2(\fpu_add_frac_dp/n243 ),
.IN3(\fpu_add_frac_dp/n434 ), .QN(n2981) );
INVX0 U5083 ( .INP(n2867), .ZN(n2871) );
NAND3X0 U5084 ( .IN1(\fpu_add_frac_dp/n342 ), .IN2(\fpu_add_frac_dp/n241 ),
.IN3(\fpu_add_frac_dp/n432 ), .QN(n2867) );
INVX0 U5085 ( .INP(n2982), .ZN(n2873) );
NAND3X0 U5086 ( .IN1(\fpu_add_frac_dp/n341 ), .IN2(\fpu_add_frac_dp/n239 ),
.IN3(\fpu_add_frac_dp/n430 ), .QN(n2982) );
MUX21X1 U5087 ( .IN1(\fpu_add_frac_dp/n582 ), .IN2(\fpu_add_ctl/n78 ), .S(
\fpu_add_ctl/n322 ), .Q(n4786) );
NOR2X0 U5088 ( .IN1(n4731), .IN2(n2973), .QN(n4785) );
NAND3X0 U5089 ( .IN1(\fpu_add_frac_dp/n368 ), .IN2(\fpu_add_frac_dp/n293 ),
.IN3(\fpu_add_frac_dp/n484 ), .QN(n2973) );
NAND4X0 U5090 ( .IN1(\fpu_add_frac_dp/n313 ), .IN2(n3074), .IN3(n4798),
.IN4(n4799), .QN(n4731) );
NOR4X0 U5091 ( .IN1(n4800), .IN2(n2967), .IN3(n2964), .IN4(n2966), .QN(n4799) );
NAND3X0 U5092 ( .IN1(\fpu_add_frac_dp/n375 ), .IN2(\fpu_add_frac_dp/n307 ),
.IN3(\fpu_add_frac_dp/n498 ), .QN(n2966) );
NAND2X0 U5093 ( .IN1(\fpu_add_frac_dp/n377 ), .IN2(\fpu_add_frac_dp/n311 ),
.QN(n2964) );
NAND3X0 U5094 ( .IN1(\fpu_add_frac_dp/n374 ), .IN2(\fpu_add_frac_dp/n305 ),
.IN3(\fpu_add_frac_dp/n496 ), .QN(n2967) );
OR2X1 U5095 ( .IN1(n2969), .IN2(n2968), .Q(n4800) );
NAND3X0 U5096 ( .IN1(\fpu_add_frac_dp/n373 ), .IN2(\fpu_add_frac_dp/n303 ),
.IN3(\fpu_add_frac_dp/n494 ), .QN(n2968) );
NAND3X0 U5097 ( .IN1(\fpu_add_frac_dp/n372 ), .IN2(\fpu_add_frac_dp/n301 ),
.IN3(\fpu_add_frac_dp/n492 ), .QN(n2969) );
NOR3X0 U5098 ( .IN1(n2972), .IN2(n2971), .IN3(n2970), .QN(n4798) );
NAND3X0 U5099 ( .IN1(\fpu_add_frac_dp/n371 ), .IN2(\fpu_add_frac_dp/n299 ),
.IN3(\fpu_add_frac_dp/n490 ), .QN(n2970) );
NAND3X0 U5100 ( .IN1(\fpu_add_frac_dp/n370 ), .IN2(\fpu_add_frac_dp/n297 ),
.IN3(\fpu_add_frac_dp/n488 ), .QN(n2971) );
NAND3X0 U5101 ( .IN1(\fpu_add_frac_dp/n369 ), .IN2(\fpu_add_frac_dp/n295 ),
.IN3(\fpu_add_frac_dp/n486 ), .QN(n2972) );
INVX0 U5102 ( .INP(n2965), .ZN(n3074) );
NAND3X0 U5103 ( .IN1(\fpu_add_frac_dp/n376 ), .IN2(\fpu_add_frac_dp/n309 ),
.IN3(\fpu_add_frac_dp/n500 ), .QN(n2965) );
AO22X1 U5104 ( .IN1(n4000), .IN2(n1325), .IN3(n1340), .IN4(n4801), .Q(
\fpu_add_ctl/n540 ) );
AO221X1 U5105 ( .IN1(n1737), .IN2(n4648), .IN3(n2047), .IN4(
\fpu_add_ctl/n940 ), .IN5(n4048), .Q(n4801) );
INVX0 U5106 ( .INP(n4065), .ZN(n4048) );
NAND4X0 U5107 ( .IN1(n4410), .IN2(n4802), .IN3(n4803), .IN4(
\fpu_add_ctl/n312 ), .QN(n4065) );
INVX0 U5108 ( .INP(n4804), .ZN(n2047) );
NAND3X0 U5109 ( .IN1(n4805), .IN2(n4070), .IN3(n4806), .QN(n4648) );
XOR3X1 U5110 ( .IN1(\fpu_add_ctl/n125 ), .IN2(\fpu_add_ctl/n940 ), .IN3(
n4396), .Q(n4806) );
NOR2X0 U5111 ( .IN1(n1867), .IN2(\fpu_add_ctl/n318 ), .QN(n4396) );
NAND2X0 U5112 ( .IN1(n1737), .IN2(n1741), .QN(n4805) );
NAND2X0 U5113 ( .IN1(n1752), .IN2(n1753), .QN(n1741) );
NAND2X0 U5114 ( .IN1(\fpu_add_ctl/n324 ), .IN2(n4807), .QN(n1753) );
AO22X1 U5115 ( .IN1(n692), .IN2(n4613), .IN3(n325), .IN4(n4616), .Q(n4807)
);
NAND2X0 U5116 ( .IN1(\fpu_add_ctl/n127 ), .IN2(\fpu_add_ctl/n124 ), .QN(
n4616) );
NAND2X0 U5117 ( .IN1(\fpu_add_ctl/n332 ), .IN2(\fpu_add_ctl/n123 ), .QN(
n4613) );
NAND2X0 U5118 ( .IN1(n338), .IN2(n4808), .QN(n1752) );
AO22X1 U5119 ( .IN1(n692), .IN2(n4614), .IN3(n325), .IN4(n4615), .Q(n4808)
);
NAND2X0 U5120 ( .IN1(\fpu_add_ctl/n119 ), .IN2(\fpu_add_ctl/n121 ), .QN(
n4615) );
NAND2X0 U5121 ( .IN1(\fpu_add_ctl/n118 ), .IN2(\fpu_add_ctl/n333 ), .QN(
n4614) );
INVX0 U5122 ( .INP(n1867), .ZN(n1737) );
NAND2X0 U5123 ( .IN1(n4409), .IN2(n4400), .QN(n1867) );
INVX0 U5124 ( .INP(n4114), .ZN(n4000) );
INVX0 U5125 ( .INP(n4403), .ZN(\fpu_add_ctl/n47 ) );
NAND2X0 U5126 ( .IN1(\fpu_add_ctl/n49 ), .IN2(n4418), .QN(n4403) );
NOR2X0 U5127 ( .IN1(n4057), .IN2(\fpu_add_ctl/n210 ), .QN(\fpu_add_ctl/n49 )
);
NAND2X0 U5128 ( .IN1(\fpu_add_ctl/n470 ), .IN2(n1312), .QN(n4057) );
INVX0 U5129 ( .INP(n4809), .ZN(\fpu_add_ctl/n441 ) );
NAND2X0 U5130 ( .IN1(n1336), .IN2(n91), .QN(\fpu_add_ctl/n426 ) );
NAND2X0 U5131 ( .IN1(n1334), .IN2(n562), .QN(\fpu_add_ctl/n425 ) );
NAND2X0 U5132 ( .IN1(\fpu_add_ctl/n329 ), .IN2(n1335), .QN(
\fpu_add_ctl/n416 ) );
NAND2X0 U5133 ( .IN1(n3973), .IN2(\fpu_add_ctl/n470 ), .QN(n4114) );
NOR3X0 U5134 ( .IN1(n4810), .IN2(se_add_exp), .IN3(\fpu_add_ctl/n210 ), .QN(
\fpu_add_ctl/i_add_pipe_active/N7 ) );
NOR4X0 U5135 ( .IN1(n4811), .IN2(n651), .IN3(\fpu_add_ctl/n325 ), .IN4(n4411), .QN(n4810) );
NAND4X0 U5136 ( .IN1(n4812), .IN2(n4813), .IN3(n4814), .IN4(n4804), .QN(
n4411) );
NAND3X0 U5137 ( .IN1(n4815), .IN2(n158), .IN3(n4405), .QN(n4804) );
OR2X1 U5138 ( .IN1(n4404), .IN2(n4410), .Q(n4815) );
NOR2X0 U5139 ( .IN1(n595), .IN2(\fpu_add_ctl/n318 ), .QN(n4404) );
NOR2X0 U5140 ( .IN1(n4816), .IN2(n2668), .QN(n4814) );
NOR2X0 U5141 ( .IN1(n4389), .IN2(n4817), .QN(n2668) );
NAND3X0 U5142 ( .IN1(n4818), .IN2(n4400), .IN3(n4406), .QN(n4813) );
INVX0 U5143 ( .INP(n4817), .ZN(n4400) );
AO21X1 U5144 ( .IN1(\fpu_add_ctl/n318 ), .IN2(n585), .IN3(n172), .Q(n4818)
);
NAND3X0 U5145 ( .IN1(n4405), .IN2(\fpu_add_ctl/n312 ), .IN3(n4410), .QN(
n4812) );
NOR2X0 U5146 ( .IN1(n18), .IN2(\fpu_add_ctl/n321 ), .QN(n4410) );
AND2X1 U5147 ( .IN1(n4803), .IN2(\fpu_add_ctl/n936 ), .Q(n4405) );
NOR3X0 U5148 ( .IN1(n84), .IN2(n172), .IN3(n585), .QN(n4803) );
NAND3X0 U5149 ( .IN1(\fpu_add_ctl/n66 ), .IN2(\fpu_add_ctl/n269 ), .IN3(
\fpu_add_ctl/n79 ), .QN(n4811) );
AND2X1 U5150 ( .IN1(grst_l), .IN2(\fpu_add_ctl/n470 ), .Q(
\fpu_add_ctl/dffrl_add_ctl/N4 ) );
INVX0 U5151 ( .INP(se_add_exp), .ZN(\fpu_add_ctl/n470 ) );
AO222X1 U5152 ( .IN1(n4819), .IN2(n347), .IN3(n4820), .IN4(n885), .IN5(n3973), .IN6(\fpu_add_ctl/add_id_out[9] ), .Q(add_id_out_in[9]) );
AO222X1 U5153 ( .IN1(n4819), .IN2(n348), .IN3(n4820), .IN4(n886), .IN5(n3973), .IN6(\fpu_add_ctl/add_id_out[8] ), .Q(add_id_out_in[8]) );
AO222X1 U5154 ( .IN1(n4819), .IN2(n349), .IN3(n4820), .IN4(n887), .IN5(n3973), .IN6(\fpu_add_ctl/add_id_out[7] ), .Q(add_id_out_in[7]) );
AO222X1 U5155 ( .IN1(n4819), .IN2(n350), .IN3(n4820), .IN4(n888), .IN5(n3973), .IN6(\fpu_add_ctl/add_id_out[6] ), .Q(add_id_out_in[6]) );
AO222X1 U5156 ( .IN1(n4819), .IN2(n351), .IN3(n4820), .IN4(n889), .IN5(n3973), .IN6(\fpu_add_ctl/add_id_out[5] ), .Q(add_id_out_in[5]) );
AO222X1 U5157 ( .IN1(n4819), .IN2(n352), .IN3(n4820), .IN4(n890), .IN5(n3973), .IN6(\fpu_add_ctl/add_id_out[4] ), .Q(add_id_out_in[4]) );
AO222X1 U5158 ( .IN1(n4819), .IN2(n353), .IN3(n4820), .IN4(n891), .IN5(n3973), .IN6(\fpu_add_ctl/add_id_out[3] ), .Q(add_id_out_in[3]) );
AO222X1 U5159 ( .IN1(n4819), .IN2(n354), .IN3(n4820), .IN4(n892), .IN5(n3973), .IN6(\fpu_add_ctl/add_id_out[2] ), .Q(add_id_out_in[2]) );
AO222X1 U5160 ( .IN1(n4819), .IN2(n341), .IN3(n4820), .IN4(n893), .IN5(n3973), .IN6(\fpu_add_ctl/add_id_out[1] ), .Q(add_id_out_in[1]) );
AO222X1 U5161 ( .IN1(n4819), .IN2(n342), .IN3(n4820), .IN4(n894), .IN5(n3973), .IN6(\fpu_add_ctl/add_id_out[0] ), .Q(add_id_out_in[0]) );
NOR2X0 U5162 ( .IN1(n3973), .IN2(\fpu_add_ctl/n315 ), .QN(n4820) );
NOR2X0 U5163 ( .IN1(n622), .IN2(n3973), .QN(n4819) );
AO221X1 U5164 ( .IN1(n536), .IN2(n1306), .IN3(n1002), .IN4(n1308), .IN5(
n1315), .Q(add_frac_out[9]) );
AO221X1 U5165 ( .IN1(n537), .IN2(n1305), .IN3(n1003), .IN4(n65), .IN5(n1315),
.Q(add_frac_out[8]) );
AO221X1 U5166 ( .IN1(n538), .IN2(n1307), .IN3(n1310), .IN4(n919), .IN5(n1315), .Q(add_frac_out[7]) );
AO221X1 U5167 ( .IN1(n539), .IN2(n66), .IN3(n1309), .IN4(n920), .IN5(n1315),
.Q(add_frac_out[6]) );
AO221X1 U5168 ( .IN1(n467), .IN2(n1308), .IN3(n1307), .IN4(n859), .IN5(n1315), .Q(add_frac_out[63]) );
AO221X1 U5169 ( .IN1(n468), .IN2(n1310), .IN3(n66), .IN4(n907), .IN5(n4821),
.Q(add_frac_out[62]) );
AO21X1 U5170 ( .IN1(n1006), .IN2(n579), .IN3(n1316), .Q(n4821) );
AO221X1 U5171 ( .IN1(n963), .IN2(n65), .IN3(n1306), .IN4(n493), .IN5(n4822),
.Q(add_frac_out[61]) );
AO21X1 U5172 ( .IN1(n1035), .IN2(n579), .IN3(n1317), .Q(n4822) );
AO221X1 U5173 ( .IN1(n466), .IN2(n1309), .IN3(n1305), .IN4(n860), .IN5(n4823), .Q(add_frac_out[60]) );
AO21X1 U5174 ( .IN1(n1036), .IN2(n579), .IN3(n1318), .Q(n4823) );
AO221X1 U5175 ( .IN1(n540), .IN2(n1306), .IN3(n1308), .IN4(n921), .IN5(n1315), .Q(add_frac_out[5]) );
AO221X1 U5176 ( .IN1(n933), .IN2(n1308), .IN3(n1307), .IN4(n494), .IN5(n4824), .Q(add_frac_out[59]) );
AO21X1 U5177 ( .IN1(n1037), .IN2(n579), .IN3(n1316), .Q(n4824) );
AO221X1 U5178 ( .IN1(n1309), .IN2(n1034), .IN3(n66), .IN4(n495), .IN5(n4825),
.Q(add_frac_out[58]) );
AO21X1 U5179 ( .IN1(n1038), .IN2(n579), .IN3(n1317), .Q(n4825) );
AO221X1 U5180 ( .IN1(n65), .IN2(n906), .IN3(n1306), .IN4(n496), .IN5(n4826),
.Q(add_frac_out[57]) );
AO21X1 U5181 ( .IN1(n1039), .IN2(n579), .IN3(n1318), .Q(n4826) );
AO221X1 U5182 ( .IN1(n1310), .IN2(n1064), .IN3(n1305), .IN4(n497), .IN5(
n4827), .Q(add_frac_out[56]) );
AO21X1 U5183 ( .IN1(n1040), .IN2(n579), .IN3(n1316), .Q(n4827) );
AO221X1 U5184 ( .IN1(n1309), .IN2(n918), .IN3(n1307), .IN4(n498), .IN5(n4828), .Q(add_frac_out[55]) );
AO21X1 U5185 ( .IN1(n1041), .IN2(n579), .IN3(n1317), .Q(n4828) );
AO221X1 U5186 ( .IN1(n964), .IN2(n579), .IN3(n66), .IN4(n499), .IN5(n4829),
.Q(add_frac_out[54]) );
AO21X1 U5187 ( .IN1(n909), .IN2(n1309), .IN3(n1318), .Q(n4829) );
AO221X1 U5188 ( .IN1(n965), .IN2(n579), .IN3(n1306), .IN4(n500), .IN5(n4830),
.Q(add_frac_out[53]) );
AO21X1 U5189 ( .IN1(n910), .IN2(n1308), .IN3(n1316), .Q(n4830) );
AO221X1 U5190 ( .IN1(n966), .IN2(n579), .IN3(n1305), .IN4(n501), .IN5(n4831),
.Q(add_frac_out[52]) );
AO21X1 U5191 ( .IN1(n911), .IN2(n1310), .IN3(n1317), .Q(n4831) );
AO221X1 U5192 ( .IN1(n967), .IN2(n579), .IN3(n1307), .IN4(n502), .IN5(n4832),
.Q(add_frac_out[51]) );
AO21X1 U5193 ( .IN1(n912), .IN2(n65), .IN3(n1318), .Q(n4832) );
AO221X1 U5194 ( .IN1(n968), .IN2(n579), .IN3(n66), .IN4(n503), .IN5(n4833),
.Q(add_frac_out[50]) );
AO21X1 U5195 ( .IN1(n913), .IN2(n1309), .IN3(n1316), .Q(n4833) );
AO221X1 U5196 ( .IN1(n541), .IN2(n1305), .IN3(n65), .IN4(n922), .IN5(n1315),
.Q(add_frac_out[4]) );
AO221X1 U5197 ( .IN1(n469), .IN2(n1310), .IN3(n1306), .IN4(n861), .IN5(n4834), .Q(add_frac_out[49]) );
AO21X1 U5198 ( .IN1(n1042), .IN2(n579), .IN3(n1317), .Q(n4834) );
AO221X1 U5199 ( .IN1(n470), .IN2(n65), .IN3(n1305), .IN4(n862), .IN5(n4835),
.Q(add_frac_out[48]) );
AO21X1 U5200 ( .IN1(n1043), .IN2(n579), .IN3(n1318), .Q(n4835) );
AO221X1 U5201 ( .IN1(n471), .IN2(n1309), .IN3(n1307), .IN4(n863), .IN5(n4836), .Q(add_frac_out[47]) );
AO21X1 U5202 ( .IN1(n1044), .IN2(n579), .IN3(n1316), .Q(n4836) );
AO221X1 U5203 ( .IN1(n472), .IN2(n1308), .IN3(n66), .IN4(n864), .IN5(n4837),
.Q(add_frac_out[46]) );
AO21X1 U5204 ( .IN1(n1045), .IN2(n579), .IN3(n1317), .Q(n4837) );
AO221X1 U5205 ( .IN1(n473), .IN2(n1310), .IN3(n1306), .IN4(n865), .IN5(n4838), .Q(add_frac_out[45]) );
AO21X1 U5206 ( .IN1(n1046), .IN2(n579), .IN3(n1318), .Q(n4838) );
AO221X1 U5207 ( .IN1(n474), .IN2(n65), .IN3(n1305), .IN4(n866), .IN5(n4839),
.Q(add_frac_out[44]) );
AO21X1 U5208 ( .IN1(n1047), .IN2(n579), .IN3(n1316), .Q(n4839) );
AO221X1 U5209 ( .IN1(n475), .IN2(n1309), .IN3(n1307), .IN4(n867), .IN5(n4840), .Q(add_frac_out[43]) );
AO21X1 U5210 ( .IN1(n1048), .IN2(n579), .IN3(n1317), .Q(n4840) );
AO221X1 U5211 ( .IN1(n476), .IN2(n1308), .IN3(n66), .IN4(n868), .IN5(n4841),
.Q(add_frac_out[42]) );
AO21X1 U5212 ( .IN1(n1049), .IN2(n579), .IN3(n1318), .Q(n4841) );
AO221X1 U5213 ( .IN1(n477), .IN2(n1310), .IN3(n1306), .IN4(n869), .IN5(n4842), .Q(add_frac_out[41]) );
AO21X1 U5214 ( .IN1(n1050), .IN2(n579), .IN3(n1316), .Q(n4842) );
AO221X1 U5215 ( .IN1(n478), .IN2(n65), .IN3(n1305), .IN4(n870), .IN5(n4843),
.Q(add_frac_out[40]) );
AO21X1 U5216 ( .IN1(n1051), .IN2(n579), .IN3(n1317), .Q(n4843) );
AO221X1 U5217 ( .IN1(n542), .IN2(n1307), .IN3(n1310), .IN4(n923), .IN5(n1315), .Q(add_frac_out[3]) );
AO221X1 U5218 ( .IN1(n479), .IN2(n1309), .IN3(n1307), .IN4(n871), .IN5(n4844), .Q(add_frac_out[39]) );
AO21X1 U5219 ( .IN1(n1052), .IN2(n579), .IN3(n1318), .Q(n4844) );
AO221X1 U5220 ( .IN1(n480), .IN2(n1308), .IN3(n66), .IN4(n872), .IN5(n4845),
.Q(add_frac_out[38]) );
AO21X1 U5221 ( .IN1(n1053), .IN2(n579), .IN3(n1316), .Q(n4845) );
AO221X1 U5222 ( .IN1(n481), .IN2(n1310), .IN3(n1306), .IN4(n873), .IN5(n4846), .Q(add_frac_out[37]) );
AO21X1 U5223 ( .IN1(n1054), .IN2(n579), .IN3(n1317), .Q(n4846) );
AO221X1 U5224 ( .IN1(n482), .IN2(n65), .IN3(n1305), .IN4(n874), .IN5(n4847),
.Q(add_frac_out[36]) );
AO21X1 U5225 ( .IN1(n1055), .IN2(n579), .IN3(n1318), .Q(n4847) );
AO221X1 U5226 ( .IN1(n483), .IN2(n1309), .IN3(n1307), .IN4(n875), .IN5(n4848), .Q(add_frac_out[35]) );
AO21X1 U5227 ( .IN1(n1056), .IN2(n579), .IN3(n1316), .Q(n4848) );
AO221X1 U5228 ( .IN1(n484), .IN2(n1308), .IN3(n66), .IN4(n876), .IN5(n4849),
.Q(add_frac_out[34]) );
AO21X1 U5229 ( .IN1(n1057), .IN2(n579), .IN3(n1317), .Q(n4849) );
AO221X1 U5230 ( .IN1(n485), .IN2(n1310), .IN3(n1306), .IN4(n877), .IN5(n4850), .Q(add_frac_out[33]) );
AO21X1 U5231 ( .IN1(n1058), .IN2(n579), .IN3(n1318), .Q(n4850) );
AO221X1 U5232 ( .IN1(n486), .IN2(n65), .IN3(n1305), .IN4(n878), .IN5(n4851),
.Q(add_frac_out[32]) );
AO21X1 U5233 ( .IN1(n1059), .IN2(n579), .IN3(n1316), .Q(n4851) );
AO221X1 U5234 ( .IN1(n487), .IN2(n1309), .IN3(n1307), .IN4(n879), .IN5(n4852), .Q(add_frac_out[31]) );
AO21X1 U5235 ( .IN1(n1060), .IN2(n579), .IN3(n1317), .Q(n4852) );
AO221X1 U5236 ( .IN1(n488), .IN2(n1308), .IN3(n66), .IN4(n880), .IN5(n4853),
.Q(add_frac_out[30]) );
AO21X1 U5237 ( .IN1(n1061), .IN2(n579), .IN3(n1318), .Q(n4853) );
AO221X1 U5238 ( .IN1(n543), .IN2(n66), .IN3(n1308), .IN4(n924), .IN5(n1315),
.Q(add_frac_out[2]) );
AO221X1 U5239 ( .IN1(n489), .IN2(n65), .IN3(n1306), .IN4(n881), .IN5(n4854),
.Q(add_frac_out[29]) );
AO21X1 U5240 ( .IN1(n1062), .IN2(n579), .IN3(n1316), .Q(n4854) );
AO221X1 U5241 ( .IN1(n969), .IN2(n579), .IN3(n517), .IN4(n1310), .IN5(n4855),
.Q(add_frac_out[28]) );
AO21X1 U5242 ( .IN1(n938), .IN2(n1306), .IN3(n1317), .Q(n4855) );
AO221X1 U5243 ( .IN1(n970), .IN2(n579), .IN3(n518), .IN4(n1309), .IN5(n4856),
.Q(add_frac_out[27]) );
AO21X1 U5244 ( .IN1(n939), .IN2(n1307), .IN3(n1318), .Q(n4856) );
AO221X1 U5245 ( .IN1(n971), .IN2(n579), .IN3(n519), .IN4(n1308), .IN5(n4857),
.Q(add_frac_out[26]) );
AO21X1 U5246 ( .IN1(n940), .IN2(n66), .IN3(n1316), .Q(n4857) );
AO221X1 U5247 ( .IN1(n972), .IN2(n579), .IN3(n520), .IN4(n65), .IN5(n4858),
.Q(add_frac_out[25]) );
AO21X1 U5248 ( .IN1(n941), .IN2(n1305), .IN3(n1317), .Q(n4858) );
AO221X1 U5249 ( .IN1(n973), .IN2(n579), .IN3(n521), .IN4(n1310), .IN5(n4859),
.Q(add_frac_out[24]) );
AO21X1 U5250 ( .IN1(n942), .IN2(n1306), .IN3(n1318), .Q(n4859) );
AO221X1 U5251 ( .IN1(n974), .IN2(n579), .IN3(n522), .IN4(n1309), .IN5(n4860),
.Q(add_frac_out[23]) );
AO21X1 U5252 ( .IN1(n943), .IN2(n1307), .IN3(n1316), .Q(n4860) );
AO221X1 U5253 ( .IN1(n975), .IN2(n579), .IN3(n523), .IN4(n1308), .IN5(n4861),
.Q(add_frac_out[22]) );
AO21X1 U5254 ( .IN1(n944), .IN2(n66), .IN3(n1317), .Q(n4861) );
AO221X1 U5255 ( .IN1(n976), .IN2(n579), .IN3(n524), .IN4(n65), .IN5(n4862),
.Q(add_frac_out[21]) );
AO21X1 U5256 ( .IN1(n945), .IN2(n1305), .IN3(n1318), .Q(n4862) );
AO221X1 U5257 ( .IN1(n977), .IN2(n579), .IN3(n525), .IN4(n1310), .IN5(n4863),
.Q(add_frac_out[20]) );
AO21X1 U5258 ( .IN1(n946), .IN2(n1306), .IN3(n1316), .Q(n4863) );
AO221X1 U5259 ( .IN1(n978), .IN2(n1306), .IN3(n65), .IN4(n551), .IN5(n1315),
.Q(add_frac_out[1]) );
AO221X1 U5260 ( .IN1(n979), .IN2(n579), .IN3(n526), .IN4(n1309), .IN5(n4864),
.Q(add_frac_out[19]) );
AO21X1 U5261 ( .IN1(n947), .IN2(n1307), .IN3(n1317), .Q(n4864) );
AO221X1 U5262 ( .IN1(n980), .IN2(n579), .IN3(n527), .IN4(n1308), .IN5(n4865),
.Q(add_frac_out[18]) );
AO21X1 U5263 ( .IN1(n948), .IN2(n66), .IN3(n1318), .Q(n4865) );
AO221X1 U5264 ( .IN1(n981), .IN2(n579), .IN3(n528), .IN4(n65), .IN5(n4866),
.Q(add_frac_out[17]) );
AO21X1 U5265 ( .IN1(n949), .IN2(n1305), .IN3(n1316), .Q(n4866) );
AO221X1 U5266 ( .IN1(n982), .IN2(n579), .IN3(n529), .IN4(n1310), .IN5(n4867),
.Q(add_frac_out[16]) );
AO21X1 U5267 ( .IN1(n950), .IN2(n1306), .IN3(n1317), .Q(n4867) );
AO221X1 U5268 ( .IN1(n983), .IN2(n579), .IN3(n530), .IN4(n1309), .IN5(n4868),
.Q(add_frac_out[15]) );
AO21X1 U5269 ( .IN1(n951), .IN2(n1307), .IN3(n1318), .Q(n4868) );
AO221X1 U5270 ( .IN1(n984), .IN2(n579), .IN3(n531), .IN4(n1308), .IN5(n4869),
.Q(add_frac_out[14]) );
AO21X1 U5271 ( .IN1(n952), .IN2(n66), .IN3(n1316), .Q(n4869) );
AO221X1 U5272 ( .IN1(n985), .IN2(n579), .IN3(n532), .IN4(n65), .IN5(n4870),
.Q(add_frac_out[13]) );
AO21X1 U5273 ( .IN1(n953), .IN2(n1305), .IN3(n1317), .Q(n4870) );
AO221X1 U5274 ( .IN1(n986), .IN2(n579), .IN3(n533), .IN4(n1310), .IN5(n4871),
.Q(add_frac_out[12]) );
AO21X1 U5275 ( .IN1(n954), .IN2(n1307), .IN3(n1315), .Q(n4871) );
AO221X1 U5276 ( .IN1(n987), .IN2(n579), .IN3(n534), .IN4(n1309), .IN5(n4872),
.Q(add_frac_out[11]) );
AO21X1 U5277 ( .IN1(n955), .IN2(n66), .IN3(n1315), .Q(n4872) );
AO221X1 U5278 ( .IN1(n908), .IN2(n1305), .IN3(n535), .IN4(n1308), .IN5(n1315), .Q(add_frac_out[10]) );
AO221X1 U5279 ( .IN1(n544), .IN2(n1305), .IN3(n1310), .IN4(n925), .IN5(n1315), .Q(add_frac_out[0]) );
NAND3X0 U5280 ( .IN1(n441), .IN2(n758), .IN3(n4873), .QN(add_exp_out[9]) );
NAND2X0 U5281 ( .IN1(\fpu_add_exp_dp/n2 ), .IN2(\fpu_add_exp_dp/n13 ), .QN(
n4873) );
NAND3X0 U5282 ( .IN1(n442), .IN2(n759), .IN3(n4874), .QN(add_exp_out[8]) );
NAND2X0 U5283 ( .IN1(\fpu_add_exp_dp/n3 ), .IN2(\fpu_add_exp_dp/n14 ), .QN(
n4874) );
NAND3X0 U5284 ( .IN1(n732), .IN2(n434), .IN3(n4875), .QN(add_exp_out[7]) );
NAND2X0 U5285 ( .IN1(\fpu_add_exp_dp/n4 ), .IN2(\fpu_add_exp_dp/n15 ), .QN(
n4875) );
NAND3X0 U5286 ( .IN1(n733), .IN2(n435), .IN3(n4876), .QN(add_exp_out[6]) );
NAND2X0 U5287 ( .IN1(\fpu_add_exp_dp/n5 ), .IN2(\fpu_add_exp_dp/n16 ), .QN(
n4876) );
NAND3X0 U5288 ( .IN1(n734), .IN2(n436), .IN3(n4877), .QN(add_exp_out[5]) );
NAND2X0 U5289 ( .IN1(\fpu_add_exp_dp/n6 ), .IN2(\fpu_add_exp_dp/n17 ), .QN(
n4877) );
NAND3X0 U5290 ( .IN1(n735), .IN2(n437), .IN3(n4878), .QN(add_exp_out[4]) );
NAND2X0 U5291 ( .IN1(\fpu_add_exp_dp/n7 ), .IN2(\fpu_add_exp_dp/n18 ), .QN(
n4878) );
NAND3X0 U5292 ( .IN1(n736), .IN2(n438), .IN3(n4879), .QN(add_exp_out[3]) );
NAND2X0 U5293 ( .IN1(\fpu_add_exp_dp/n8 ), .IN2(\fpu_add_exp_dp/n19 ), .QN(
n4879) );
NAND3X0 U5294 ( .IN1(n737), .IN2(n439), .IN3(n4880), .QN(add_exp_out[2]) );
NAND2X0 U5295 ( .IN1(\fpu_add_exp_dp/n9 ), .IN2(\fpu_add_exp_dp/n20 ), .QN(
n4880) );
NAND3X0 U5296 ( .IN1(n738), .IN2(n440), .IN3(n4881), .QN(add_exp_out[1]) );
NAND2X0 U5297 ( .IN1(\fpu_add_exp_dp/n21 ), .IN2(\fpu_add_exp_dp/n10 ), .QN(
n4881) );
NAND3X0 U5298 ( .IN1(n443), .IN2(n760), .IN3(n4882), .QN(add_exp_out[10]) );
NAND2X0 U5299 ( .IN1(\fpu_add_exp_dp/n12 ), .IN2(\fpu_add_exp_dp/n1 ), .QN(
n4882) );
NAND3X0 U5300 ( .IN1(n764), .IN2(n454), .IN3(n4883), .QN(add_exp_out[0]) );
NAND2X0 U5301 ( .IN1(\fpu_add_exp_dp/n22 ), .IN2(\fpu_add_exp_dp/n11 ), .QN(
n4883) );
INVX0 U5302 ( .INP(n4884), .ZN(add_exc_out[3]) );
NAND2X0 U5303 ( .IN1(\fpu_add_ctl/n2 ), .IN2(n4884), .QN(add_exc_out[0]) );
OA21X1 U5304 ( .IN1(\fpu_add_ctl/n5 ), .IN2(\fpu_add_frac_dp/n129 ), .IN3(
\fpu_add_ctl/n4 ), .Q(n4884) );
AOI21X1 U5305 ( .IN1(n1314), .IN2(n4809), .IN3(\fpu_add_ctl/n210 ), .QN(
a6stg_fadd_in) );
MUX21X1 U5306 ( .IN1(\fpu_add_ctl/n66 ), .IN2(n4885), .S(\fpu_add_ctl/n315 ),
.Q(n4809) );
NAND2X0 U5307 ( .IN1(n642), .IN2(n339), .QN(n4885) );
INVX0 U5308 ( .INP(n4417), .ZN(a1stg_step) );
NAND2X0 U5309 ( .IN1(n4418), .IN2(n1313), .QN(n4417) );
NOR2X0 U5310 ( .IN1(\fpu_add_ctl/n269 ), .IN2(add_dest_rdy), .QN(n3973) );
NAND2X0 U5311 ( .IN1(n355), .IN2(n4886), .QN(n4418) );
NAND4X0 U5312 ( .IN1(\fpu_add_ctl/n936 ), .IN2(\fpu_add_ctl/n314 ), .IN3(
n4887), .IN4(n158), .QN(n4886) );
NAND2X0 U5313 ( .IN1(\fpu_add_ctl/n318 ), .IN2(\fpu_add_ctl/n312 ), .QN(
n4887) );
NOR2X0 U5314 ( .IN1(n4394), .IN2(n4817), .QN(a1stg_fsdtoix) );
NOR2X0 U5315 ( .IN1(n4802), .IN2(n4408), .QN(n4817) );
AND2X1 U5316 ( .IN1(n4391), .IN2(n4389), .Q(n4394) );
NAND3X0 U5317 ( .IN1(\fpu_add_ctl/n303 ), .IN2(n254), .IN3(n4888), .QN(n4389) );
NAND3X0 U5318 ( .IN1(\fpu_add_ctl/n312 ), .IN2(n585), .IN3(n4888), .QN(n4391) );
NOR4X0 U5319 ( .IN1(n595), .IN2(n84), .IN3(n172), .IN4(n18), .QN(n4888) );
INVX0 U5320 ( .INP(n4070), .ZN(a1stg_fdtos) );
NAND2X0 U5321 ( .IN1(n4816), .IN2(\fpu_add_ctl/n314 ), .QN(n4070) );
INVX0 U5322 ( .INP(n4656), .ZN(n4816) );
NAND4X0 U5323 ( .IN1(n4408), .IN2(\fpu_add_ctl/n303 ), .IN3(n4406), .IN4(n18), .QN(n4656) );
INVX0 U5324 ( .INP(n4390), .ZN(n4408) );
NAND2X0 U5325 ( .IN1(n158), .IN2(n829), .QN(n4390) );
INVX0 U5326 ( .INP(n4046), .ZN(a1stg_faddsubs) );
NAND2X0 U5327 ( .IN1(n4802), .IN2(n4409), .QN(n4046) );
AND3X1 U5328 ( .IN1(n4406), .IN2(n172), .IN3(\fpu_add_ctl/n303 ), .Q(n4409)
);
NOR3X0 U5329 ( .IN1(n84), .IN2(n254), .IN3(n595), .QN(n4406) );
INVX0 U5330 ( .INP(n4392), .ZN(n4802) );
NAND2X0 U5331 ( .IN1(\fpu_add_ctl/n320 ), .IN2(\fpu_add_ctl/n936 ), .QN(
n4392) );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A31OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A31OI_PP_BLACKBOX_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A31OI_PP_BLACKBOX_V
|
//------------------------------------------------------------------------------
// File : axi_mux.v
// Author : Xilinx Inc.
// -----------------------------------------------------------------------------
// (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
// Description: A simple axi mux
//
//------------------------------------------------------------------------------
`timescale 1 ps/1 ps
module axi_mux (
input mux_select,
// mux inputs
input [7:0] tdata0,
input tvalid0,
input tlast0,
output reg tready0,
input [7:0] tdata1,
input tvalid1,
input tlast1,
output reg tready1,
// mux outputs
output reg [7:0] tdata,
output reg tvalid,
output reg tlast,
input tready
);
always @(mux_select or tdata0 or tvalid0 or tlast0 or tdata1 or
tvalid1 or tlast1)
begin
if (mux_select) begin
tdata = tdata1;
tvalid = tvalid1;
tlast = tlast1;
end
else begin
tdata = tdata0;
tvalid = tvalid0;
tlast = tlast0;
end
end
always @(mux_select or tready)
begin
if (mux_select) begin
tready0 = 1'b1;
end
else begin
tready0 = tready;
end
tready1 = tready;
end
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
//
// TASK0.v, testbench for NON-power gating only
//
//
always @ (posedge clk or negedge resetn) begin
// not in reset
if (resetn)
begin
case (state)
// Querry nodes
TASK1:
begin
c0_tx_addr <= {28'h000000, `CHANNEL_ENUM};
c0_tx_data <= {`CMD_CHANNEL_ENUM_QUERRY, 28'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// Enumerate with 4'h2
TASK2:
begin
c0_tx_addr <= {28'h000000, `CHANNEL_ENUM};
// address should starts with 4'h2
c0_tx_data <= {`CMD_CHANNEL_ENUM_ENUMERATE, 4'h2, 24'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// Enumerate with 4'h3
TASK3:
begin
c0_tx_addr <= {28'h000000, `CHANNEL_ENUM};
c0_tx_data <= {`CMD_CHANNEL_ENUM_ENUMERATE, 4'h3, 24'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// Enumerate with 4'h4
TASK4:
begin
c0_tx_addr <= {28'h000000, `CHANNEL_ENUM};
c0_tx_data <= {`CMD_CHANNEL_ENUM_ENUMERATE, 4'h4, 24'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// Enumerate with 4'h5
TASK5:
begin
c0_tx_addr <= {28'h000000, `CHANNEL_ENUM};
c0_tx_data <= {`CMD_CHANNEL_ENUM_ENUMERATE, 4'h5, 24'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// n1->n0 using long address
TASK6:
begin
n1_tx_addr <= {4'hf, 4'h0, 20'hbbbb0, 4'h3};
n1_tx_data <= rand_dat;
n1_tx_pend <= 0;
n1_tx_req <= 1;
n1_priority <= 0;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
state <= TX_WAIT;
end
// n1->n2 using long address
TASK7:
begin
n1_tx_addr <= {4'hf, 4'h0, 20'hbbbb2, 4'h5};
n1_tx_data <= rand_dat;
n1_tx_pend <= 0;
n1_tx_req <= 1;
n1_priority <= 0;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
state <= TX_WAIT;
end
// n1->n0 using short address
TASK8:
begin
n1_tx_addr <= {24'h0, 4'h2, 4'h5}; // last 4-bits (4'h5) are functional ID
n1_tx_data <= rand_dat;
n1_tx_pend <= 0;
n1_tx_req <= 1;
n1_priority <= 0;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
state <= TX_WAIT;
end
// n1->n2 using short address
TASK9:
begin
n1_tx_addr <= {24'h0, 4'h4, 4'h1}; // last 4-bits (4'h1) are functional ID
n1_tx_data <= rand_dat;
n1_tx_pend <= 0;
n1_tx_req <= 1;
n1_priority <= 0;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
state <= TX_WAIT;
end
// n1->n3 using short address
TASK10:
begin
n1_tx_addr <= {24'h0, 4'h5, 4'h2}; // last 4-bits (4'h2) are functional ID
n1_tx_data <= rand_dat;
n1_tx_pend <= 0;
n1_tx_req <= 1;
n1_priority <= 0;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
state <= TX_WAIT;
end
// Invalidate short address 4'h2
TASK11:
begin
c0_tx_addr <= {28'h000000, `CHANNEL_ENUM};
c0_tx_data <= {`CMD_CHANNEL_ENUM_INVALIDATE, 4'h2, 24'h0};
c0_tx_pend <= 0;
c0_tx_req <= 1;
c0_priority <= 0;
state <= TX_WAIT;
end
// Enumerate with 4'h8
TASK12:
begin
c0_tx_addr <= {28'h000000, `CHANNEL_ENUM};
c0_tx_data <= {`CMD_CHANNEL_ENUM_ENUMERATE, 4'h8, 24'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// n1->n0 using new short address
TASK13:
begin
n1_tx_addr <= {24'h0, 4'h8, 4'h1}; // last 4-bits (4'h1) are functional ID
n1_tx_data <= rand_dat;
n1_tx_pend <= 0;
n1_tx_req <= 1;
n1_priority <= 0;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
state <= TX_WAIT;
end
// Sleep n0, n2
TASK14:
begin
c0_tx_addr <= {28'h000000, `CHANNEL_POWER};
c0_tx_data <= (`CMD_CHANNEL_POWER_SEL_SLEEP<<28) | ((1'b1<<8)|(1'b1<<4))<<12 | 12'h0;
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// n2->n0 using short address
TASK16:
begin
n2_tx_addr <= {24'h0, 4'h8, 4'h2}; // last 4-bits (4'h2) are functional ID
n2_tx_data <= rand_dat;
n2_tx_pend <= 0;
n2_tx_req <= 1;
n2_priority <= 0;
$fdisplay(handle, "N2 Data in =\t32'h%h", rand_dat);
state <= TX_WAIT;
end
// Long querry nodes
TASK17:
begin
c0_tx_addr <= {28'hf00000, `CHANNEL_ENUM};
c0_tx_data <= {`CMD_CHANNEL_ENUM_QUERRY, 28'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// All layers sleep
TASK18:
begin
c0_tx_addr <= {28'hf00000, `CHANNEL_POWER};
c0_tx_data <= {`CMD_CHANNEL_POWER_ALL_SLEEP, 28'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// All layers wake
TASK19:
begin
c0_tx_addr <= {28'hf00000, `CHANNEL_POWER};
c0_tx_data <= {`CMD_CHANNEL_POWER_ALL_WAKE, 28'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// Invalidate all short address
TASK20:
begin
c0_tx_addr <= {24'he0000, 4'h0, `CHANNEL_ENUM};
c0_tx_data <= {`CMD_CHANNEL_ENUM_INVALIDATE, 4'hf, 24'h0}; // 4'hf -> all short address
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// Selective sleep N1 using full prefix
TASK21:
begin
c0_tx_addr <= {28'hf00000, `CHANNEL_POWER};
c0_tx_data <= {`CMD_CHANNEL_POWER_SEL_SLEEP_FULL, 4'h0, 20'hbbbb1, 4'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// Selective sleep processor using full prefix
TASK22:
begin
c0_tx_addr <= {28'hf00000, `CHANNEL_POWER};
c0_tx_data <= {`CMD_CHANNEL_POWER_SEL_SLEEP_FULL, 4'h0, 20'haaaa0, 4'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// n2 querry
TASK23:
begin
n2_tx_addr <= {28'hf00000, `CHANNEL_ENUM};
n2_tx_data <= {`CMD_CHANNEL_ENUM_QUERRY, 28'h0};
n2_tx_pend <= 0;
n2_tx_req <= 1;
n2_priority <= 0;
state <= TX_WAIT;
end
// n2 sends to control
TASK24:
begin
n2_tx_addr <= {28'hf00000, `CHANNEL_CTRL};
n2_tx_data <= rand_dat;
n2_tx_pend <= 0;
n2_tx_req <= 1;
n2_priority <= 0;
$fdisplay(handle, "N2 Data in =\t32'h%h", rand_dat);
state <= TX_WAIT;
end
endcase // case (state)
end
end // always @ (posedge clk or negedge resetn)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MAJ3_1_V
`define SKY130_FD_SC_HS__MAJ3_1_V
/**
* maj3: 3-input majority vote.
*
* Verilog wrapper for maj3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__maj3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__maj3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__maj3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__MAJ3_1_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dbg_port_chk.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////////////
// Debug Port A and Debug Port B checker
//
// This checker verifies the functionality of the debug port a and debug port b
// interfaces of the Niagara chip. It is also responsible for verifying the trigout
// and trigin functionality.
// This checker also provides all the permutations of Debug Port A outputs (excluding
// l2c transactions) so that the tester team can select the type of output at runtime
// on the tester and have the expected waveform without having to rerun the test case
// in simulation.
//
// Date: December 2003
//
////////////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module dbg_port_chk () ;
// signals from the rtl
wire iobdg_dbg_portb_hi_dbg_en ;
wire iobdg_dbg_portb_lo_dbg_en ;
wire iob_io_dbg_en ;
wire creg_dbg_l2_vis_ctrl_2 ;
wire pcx_sctag0_data_rdy_px2 ;
wire pcx_sctag1_data_rdy_px2 ;
wire pcx_sctag2_data_rdy_px2 ;
wire pcx_sctag3_data_rdy_px2 ;
// l2 queue
reg [47:0] l2q [31:0] ;
reg [5:0] l2q_rd_ptr ;
reg [5:0] l2q_rd_ptr_d1 ;
reg [5:0] l2q_wr_ptr ;
reg [5:0] l2q_rd_ptr_cmp ;
reg [5:0] l2q_wr_ptr_jbus ;
reg [5:0] l2q_wr_ptr_jbus_d1 ;
reg l2q_drop ;
wire l2q_full ;
wire l2q_empty ;
wire l2q_rd ;
wire l2q_wr ;
wire l2q_wr_a ;
wire l2q_wr_b ;
wire [5:0] l2q_wr_ptr_ns ;
wire [5:0] l2q_rd_ptr_ns ;
reg [7:0] l2q_timestamp ;
wire [7:0] l2q_timestamp_ns ;
reg [47:0] l2q_data ;
reg l2q_data_vld ;
wire [47:0] l2_bus ;
reg [39:0] l2_dbgbus_01_d1 ;
reg [39:0] l2_dbgbus_23_d1 ;
reg [39:0] l2_dbgbus_01_d2 ;
reg [39:0] l2_dbgbus_23_d2 ;
// replicate all control registers
reg [63:0] iob_vis_select_cfg ; // 0x98_0000_1000
reg [63:0] l2_vis_control_cfg ; // 0x98_0000_1800
reg [63:0] l2_vis_mask_a_cfg ; // 0x98_0000_1820
reg [63:0] l2_vis_mask_b_cfg ; // 0x98_0000_1828
reg [63:0] l2_vis_compare_a_cfg ; // 0x98_0000_1830
reg [63:0] l2_vis_compare_b_cfg ; // 0x98_0000_1838
reg [63:0] l2_trig_delay_cfg ; // 0x98_0000_1840
reg [63:0] db_enet_control_cfg ; // 0x98_0000_2000
reg [63:0] db_enet_idleval_cfg ; // 0x98_0000_2008
reg [63:0] l2c0_control_reg_cfg ; // 0xA9_0000_0000
reg [63:0] l2c1_control_reg_cfg ; // 0xA9_0000_0040
reg [63:0] l2c2_control_reg_cfg ; // 0xA9_0000_0080
reg [63:0] l2c3_control_reg_cfg ; // 0xA9_0000_00c0
reg [63:0] db_jbus_control_cfg ; // 0x98_0000_2100
reg [63:0] db_jbus_mask_a_hi_cfg ; // 0x98_0000_2140
reg [63:0] db_jbus_compare_a_hi_cfg ; // 0x98_0000_2148
reg [63:0] db_jbus_count_a_hi_cfg ; // 0x98_0000_2150
reg [63:0] db_jbus_mask_b_hi_cfg ; // 0x98_0000_2160
reg [63:0] db_jbus_compare_b_hi_cfg ; // 0x98_0000_2168
reg [63:0] db_jbus_count_b_hi_cfg ; // 0x98_0000_2170
reg [63:0] db_jbus_mask_a_lo_cfg ; // 0x98_0000_2180
reg [63:0] db_jbus_compare_a_lo_cfg ; // 0x98_0000_2188
reg [63:0] db_jbus_count_a_lo_cfg ; // 0x98_0000_2190
reg [63:0] db_jbus_mask_b_lo_cfg ; // 0x98_0000_21a0
reg [63:0] db_jbus_compare_b_lo_cfg ; // 0x98_0000_21a8
reg [63:0] db_jbus_count_b_lo_cfg ; // 0x98_0000_21b0
// replicate the iob debug port buses
wire [43:0] iob_vis_port_0111 ;
reg [43:0] iob_vis_port_0111_d ;
wire [43:0] iob_vis_port_0110 ;
reg [43:0] iob_vis_port_0110_d ;
wire [43:0] iob_vis_port_0011 ;
reg [43:0] iob_vis_port_0011_d ;
wire [43:0] iob_vis_port_0010 ;
wire [43:0] iob_vis_port_0001 ;
reg [43:0] iob_vis_port_0001_d ;
wire [43:0] iob_vis_port_0000 ;
wire [43:0] iob_vis_port ;
reg [43:0] iob_vis_port_d ;
// replicate the debug port a buses
wire [39:0] debug_port_a_0100 ;
wire [39:0] debug_port_a_0011 ;
wire [39:0] debug_port_a_0010 ;
wire [39:0] debug_port_a_0001 ;
wire [39:0] debug_port_a_0000 ;
wire [39:0] debug_port_a ;
wire debug_port_a_vld ;
// permutations of debug port a
wire [39:0] debug_porta_0100_iob_0000 ;
wire [39:0] debug_porta_0010_iob_0000 ;
wire [39:0] debug_porta_0010_iob_0001 ;
wire [39:0] debug_porta_0010_iob_0010 ;
wire [39:0] debug_porta_0010_iob_0011 ;
wire [39:0] debug_porta_0010_iob_0110 ;
wire [39:0] debug_porta_0010_iob_0111 ;
wire [39:0] debug_porta_0011_iob_0111 ;
wire [39:0] debug_porta_0011_iob_0110 ;
wire [39:0] debug_porta_0011_iob_0011 ;
wire debug_porta_0100_iob_0000_vld ;
wire debug_porta_0010_iob_0000_vld ;
wire debug_porta_0010_iob_0001_vld ;
wire debug_porta_0010_iob_0010_vld ;
wire debug_porta_0010_iob_0011_vld ;
wire debug_porta_0010_iob_0110_vld ;
wire debug_porta_0010_iob_0111_vld ;
wire debug_porta_0011_iob_0111_vld ;
wire debug_porta_0011_iob_0110_vld ;
wire debug_porta_0011_iob_0011_vld ;
wire [39:0] dbg_dq_a4i0 ;
wire [39:0] dbg_dq_a2i0 ;
wire [39:0] dbg_dq_a2i1 ;
wire [39:0] dbg_dq_a2i2 ;
wire [39:0] dbg_dq_a2i3 ;
wire [39:0] dbg_dq_a2i6 ;
wire [39:0] dbg_dq_a2i7 ;
wire [39:0] dbg_dq_a3i7 ;
wire [39:0] dbg_dq_a3i6 ;
wire [39:0] dbg_dq_a3i3 ;
wire [39:0] dbg_dq_porta_0100_iob_0000 ;
reg [39:0] dbg_dq_porta_0100_iob_0000_d1 ;
reg [39:0] dbg_dq_porta_0100_iob_0000_d2 ;
reg [39:0] dbg_dq_porta_0100_iob_0000_d3 ;
wire [39:0] dbg_dq_porta_0010_iob_0000 ;
reg [39:0] dbg_dq_porta_0010_iob_0000_d1 ;
reg [39:0] dbg_dq_porta_0010_iob_0000_d2 ;
reg [39:0] dbg_dq_porta_0010_iob_0000_d3 ;
wire [39:0] dbg_dq_porta_0010_iob_0001 ;
reg [39:0] dbg_dq_porta_0010_iob_0001_d1 ;
reg [39:0] dbg_dq_porta_0010_iob_0001_d2 ;
reg [39:0] dbg_dq_porta_0010_iob_0001_d3 ;
wire [39:0] dbg_dq_porta_0010_iob_0010 ;
reg [39:0] dbg_dq_porta_0010_iob_0010_d1 ;
reg [39:0] dbg_dq_porta_0010_iob_0010_d2 ;
reg [39:0] dbg_dq_porta_0010_iob_0010_d3 ;
wire [39:0] dbg_dq_porta_0010_iob_0011 ;
reg [39:0] dbg_dq_porta_0010_iob_0011_d1 ;
reg [39:0] dbg_dq_porta_0010_iob_0011_d2 ;
reg [39:0] dbg_dq_porta_0010_iob_0011_d3 ;
wire [39:0] dbg_dq_porta_0010_iob_0110 ;
reg [39:0] dbg_dq_porta_0010_iob_0110_d1 ;
reg [39:0] dbg_dq_porta_0010_iob_0110_d2 ;
reg [39:0] dbg_dq_porta_0010_iob_0110_d3 ;
wire [39:0] dbg_dq_porta_0010_iob_0111 ;
reg [39:0] dbg_dq_porta_0010_iob_0111_d1 ;
reg [39:0] dbg_dq_porta_0010_iob_0111_d2 ;
reg [39:0] dbg_dq_porta_0010_iob_0111_d3 ;
wire [39:0] dbg_dq_porta_0011_iob_0111 ;
reg [39:0] dbg_dq_porta_0011_iob_0111_d1 ;
reg [39:0] dbg_dq_porta_0011_iob_0111_d2 ;
reg [39:0] dbg_dq_porta_0011_iob_0111_d3 ;
wire [39:0] dbg_dq_porta_0011_iob_0110 ;
reg [39:0] dbg_dq_porta_0011_iob_0110_d1 ;
reg [39:0] dbg_dq_porta_0011_iob_0110_d2 ;
reg [39:0] dbg_dq_porta_0011_iob_0110_d3 ;
wire [39:0] dbg_dq_porta_0011_iob_0011 ;
reg [39:0] dbg_dq_porta_0011_iob_0011_d1 ;
reg [39:0] dbg_dq_porta_0011_iob_0011_d2 ;
reg [39:0] dbg_dq_porta_0011_iob_0011_d3 ;
// pcx_iob transacton type
wire [1:0] ttype ;
wire soh ;
wire soh_0111 ;
wire soh_0110 ;
wire soh_0011 ;
// debug port b
wire [47:0] dbg_portb_100 ;
wire dbg_portb_100_vld ;
wire [47:0] dbg_portb_011 ;
wire dbg_portb_011_vld ;
wire [47:0] dbg_portb_hi_010 ;
wire dbg_portb_hi_010_vld ;
wire [47:0] dbg_portb_lo_010 ;
wire dbg_portb_lo_010_vld ;
wire [47:0] dbg_portb_000 ;
wire dbg_portb_000_vld ;
wire [47:0] dbg_portb_lo_sel ;
wire dbg_portb_lo_vld_sel ;
wire [47:0] dbg_portb_lo ;
wire dbg_portb_lo_vld ;
wire [47:0] dbg_portb_hi_sel ;
wire dbg_portb_hi_vld_sel ;
wire [47:0] dbg_portb_hi ;
wire dbg_portb_hi_vld ;
reg [47:0] dbg_portb_lo_d1 ;
reg [47:0] dbg_portb_lo_d2 ;
reg [47:0] dbg_portb_hi_d1 ;
reg [47:0] dbg_portb_hi_d2 ;
reg dbg_portb_lo_vld_d1 ;
reg dbg_portb_lo_vld_d2 ;
reg dbg_portb_hi_vld_d1 ;
reg dbg_portb_hi_vld_d2 ;
wire [43:0] dbg_portb_mask_a_lo ;
wire [43:0] dbg_portb_mask_b_lo ;
wire [43:0] dbg_portb_mask_a_hi ;
wire [43:0] dbg_portb_mask_b_hi ;
// debug port a
wire [39:0] dbg_dq ;
reg [39:0] dbg_dq_d1 ;
reg [39:0] dbg_dq_d2 ;
reg [39:0] dbg_dq_d3 ;
// debug port pins
wire [39:0] dbg_dq_pin ;
reg dbg_trigout_pin ;
// sctag interface signals
wire l2_dbgbus_rdy ;
wire [39:0] l2_dbgbus ;
wire [39:0] l2_mask_a ;
wire [39:0] l2_mask_b ;
// checker control signals
wire error_dbg_dq ;
wire error_dbg_trigout ;
wire error_dbg_portb_lo ;
wire error_dbg_portb_hi ;
wire error_dbg_portb_hi_vld ;
wire error_dbg_portb_lo_vld ;
reg dbg_portb_hi_en;
reg dbg_portb_lo_en;
reg dbg_porta_en;
reg trig_out_en ;
reg dbg_port_chk_on ;
// debug trigout signals
reg dbg_trigout_ps ;
wire dbg_trigout_ns ;
reg [31:0] l2_trig_delay_cnt_ps ;
wire [31:0] l2_trig_delay_cnt_ns ;
////////////////////////////////////////////////////////////////////////////////
// this checker is disabled by default and must be explicitly turned on
////////////////////////////////////////////////////////////////////////////////
initial
begin
dbg_port_chk_on= 1'b0;
if( $test$plusargs("dbg_port_chk_on") ) begin
dbg_port_chk_on = 1'b1;
end
end
////////////////////////////////////////////////////////////////////////////////
// compare expected and actual output
////////////////////////////////////////////////////////////////////////////////
initial dbg_portb_hi_en = 1'b0 ;
initial dbg_portb_lo_en = 1'b0 ;
initial dbg_porta_en = 1'b0 ;
initial trig_out_en = 1'b0 ;
`ifdef GATE_SIM_IOBDG
`else
assign iobdg_dbg_portb_hi_dbg_en = cmp_top.iop.iobdg.iobdg_dbg.iobdg_dbg_portb_hi.dbg_en ;
assign iobdg_dbg_portb_lo_dbg_en = cmp_top.iop.iobdg.iobdg_dbg.iobdg_dbg_portb_lo.dbg_en ;
assign iob_io_dbg_en = cmp_top.iop.iobdg.iobdg_dbg.iobdg_dbg_porta.iob_io_dbg_en ;
assign creg_dbg_l2_vis_ctrl_2 = cmp_top.iop.iobdg.iobdg_dbg.iobdg_dbg_l2.creg_dbg_l2_vis_ctrl[2] ;
`endif // ifdef GATE_SIM_IOBDG
always @(iobdg_dbg_portb_hi_dbg_en or db_jbus_control_cfg[16]) begin
dbg_portb_hi_en = 1'b0 ;
if (iobdg_dbg_portb_hi_dbg_en === 1'b1 && db_jbus_control_cfg[16] === 1'b1 ) begin
repeat (4) @(posedge cmp_top.iop.iobdg.jbus_rclk) ;
dbg_portb_hi_en = 1'b1 ;
end
end
always @(iobdg_dbg_portb_lo_dbg_en or db_jbus_control_cfg[16]) begin
dbg_portb_lo_en = 1'b0 ;
if (iobdg_dbg_portb_lo_dbg_en === 1'b1 && db_jbus_control_cfg[16] === 1'b1 ) begin
repeat (4) @(posedge cmp_top.iop.iobdg.jbus_rclk) ;
dbg_portb_lo_en = 1'b1 ;
end
end
always @(iob_io_dbg_en) begin
dbg_porta_en = 1'b0 ;
if (iob_io_dbg_en === 1'b1) begin
repeat (4) @(posedge cmp_top.iop.iobdg.jbus_rclk) ;
dbg_porta_en = 1'b1 ;
end
end
wire l2_armin;
always @(creg_dbg_l2_vis_ctrl_2 or l2_armin) begin
trig_out_en = 1'b0 ;
if (creg_dbg_l2_vis_ctrl_2 === 1'b1 || l2_armin === 1'b1) begin
repeat (4) @(posedge cmp_top.iop.iobdg.jbus_rclk) ;
trig_out_en = 1'b1 ;
end
end
always @(posedge cmp_top.iop.iobdg.jbus_rclk) begin
if (error_dbg_dq && dbg_port_chk_on && dbg_porta_en) begin
$display ("Error on cmp_top.DBG_DQ from dbg_port_chk") ;
repeat (4) @(posedge cmp_top.iop.iobdg.jbus_rclk) ;
$finish () ;
end
if (error_dbg_trigout && dbg_port_chk_on && trig_out_en) begin
$display ("Error on cmp_top.J_ERR from dbg_port_chk") ;
repeat (4) @(posedge cmp_top.iop.iobdg.jbus_rclk) ;
$finish () ;
end
if (error_dbg_portb_lo_vld && dbg_port_chk_on && dbg_portb_lo_en) begin
$display ("Error on cmp_top.iop.iob_jbi_dbg_lo_vld from dbg_port_chk") ;
repeat (4) @(posedge cmp_top.iop.iobdg.jbus_rclk) ;
$finish () ;
end
if (error_dbg_portb_hi_vld && dbg_port_chk_on && dbg_portb_hi_en) begin
$display ("Error on cmp_top.iop.iob_jbi_dbg_hi_vld from dbg_port_chk") ;
repeat (4) @(posedge cmp_top.iop.iobdg.jbus_rclk) ;
$finish () ;
end
// verify ???
if (error_dbg_portb_lo && dbg_port_chk_on && dbg_portb_lo_en && dbg_portb_lo_vld_d2) begin
$display ("Error on cmp_top.iop.iob_jbi_dbg_lo_data from dbg_port_chk") ;
repeat (4) @(posedge cmp_top.iop.iobdg.jbus_rclk) ;
$finish () ;
end
// verify ???
if (error_dbg_portb_hi && dbg_port_chk_on && dbg_portb_hi_en && dbg_portb_hi_vld_d2) begin
$display ("Error on cmp_top.iop.iob_jbi_dbg_hi_data from dbg_port_chk") ;
repeat (4) @(posedge cmp_top.iop.iobdg.jbus_rclk) ;
$finish () ;
end
end
assign error_dbg_portb_lo_vld = (cmp_top.iop.iob_jbi_dbg_lo_vld === dbg_portb_lo_vld_d2) ? 1'b0 : 1'b1 ;
assign error_dbg_portb_hi_vld = (cmp_top.iop.iob_jbi_dbg_hi_vld === dbg_portb_hi_vld_d2) ? 1'b0 : 1'b1 ;
assign error_dbg_portb_lo = (cmp_top.iop.iob_jbi_dbg_lo_data === dbg_portb_lo_d2) ? 1'b0 : 1'b1 ;
assign error_dbg_portb_hi = (cmp_top.iop.iob_jbi_dbg_hi_data === dbg_portb_hi_d2) ? 1'b0 : 1'b1 ;
assign error_dbg_dq = (cmp_top.DBG_DQ === dbg_dq_pin) ? 1'b0 : 1'b1 ;
//assign error_dbg_trigout = (cmp_top.J_ERR === dbg_trigout_pin) ? 1'b0 : 1'b1 ;
assign error_dbg_trigout = (cmp_top.iop.iob_ctu_l2_tr === dbg_trigout_pin) ? 1'b0 : 1'b1 ;
// drive the debug port a pins
//assign dbg_dq = (debug_port_a_vld == 1'b1) && (iob_io_dbg_en === 1'b1) ? debug_port_a :
// (debug_port_a_vld == 1'b0) && (iob_io_dbg_en === 1'b1) ? db_enet_idleval_cfg [39:0] :
// 40'hffffffffff ;
assign dbg_dq = (debug_port_a_vld == 1'b1) ? debug_port_a :
(debug_port_a_vld == 1'b0) ? db_enet_idleval_cfg [39:0] :
40'hffffffffff ;
// select transaction type
`ifdef GATE_SIM_IOBDG
assign ttype = (cmp_top.iop.iobdg.c2i_packet [`UCB_PKT_HI:`UCB_PKT_LO] == `UCB_READ_REQ) ? 2'b00 :
(cmp_top.iop.iobdg.c2i_packet [`UCB_PKT_HI:`UCB_PKT_LO] == `UCB_WRITE_REQ) ? 2'b01 :
(cmp_top.iop.iobdg.c2i_packet [`UCB_PKT_HI:`UCB_PKT_LO] == `UCB_IFILL_REQ) ? 2'b10 :
2'b11 ;
`else
assign ttype = (cmp_top.iop.iobdg.c2i.c2i_sdp.c2i_packet [`UCB_PKT_HI:`UCB_PKT_LO] == `UCB_READ_REQ) ? 2'b00 :
(cmp_top.iop.iobdg.c2i.c2i_sdp.c2i_packet [`UCB_PKT_HI:`UCB_PKT_LO] == `UCB_WRITE_REQ) ? 2'b01 :
(cmp_top.iop.iobdg.c2i.c2i_sdp.c2i_packet [`UCB_PKT_HI:`UCB_PKT_LO] == `UCB_IFILL_REQ) ? 2'b10 :
2'b11 ;
`endif
assign soh = ((~iob_vis_port_d [43]) & iob_vis_port [43]) |
((~iob_vis_port_d [41]) & iob_vis_port [41]) |
((~iob_vis_port_d [39]) & iob_vis_port [39]) |
((~iob_vis_port_d [37]) & iob_vis_port [37]) |
((~iob_vis_port_d [35]) & iob_vis_port [35]) |
((~iob_vis_port_d [33]) & iob_vis_port [33]) ;
assign soh_0111 = ((~iob_vis_port_0111_d [43]) & iob_vis_port_0111 [43]) |
((~iob_vis_port_0111_d [41]) & iob_vis_port_0111 [41]) |
((~iob_vis_port_0111_d [39]) & iob_vis_port_0111 [39]) |
((~iob_vis_port_0111_d [37]) & iob_vis_port_0111 [37]) |
((~iob_vis_port_0111_d [35]) & iob_vis_port_0111 [35]) |
((~iob_vis_port_0111_d [33]) & iob_vis_port_0111 [33]) ;
assign soh_0110 = ((~iob_vis_port_0110_d [43]) & iob_vis_port_0110 [43]) |
((~iob_vis_port_0110_d [41]) & iob_vis_port_0110 [41]) |
((~iob_vis_port_0110_d [39]) & iob_vis_port_0110 [39]) |
((~iob_vis_port_0110_d [37]) & iob_vis_port_0110 [37]) |
((~iob_vis_port_0110_d [35]) & iob_vis_port_0110 [35]) |
((~iob_vis_port_0110_d [33]) & iob_vis_port_0110 [33]) ;
assign soh_0011 = ((~iob_vis_port_0011_d [43]) & iob_vis_port_0011 [43]) |
((~iob_vis_port_0011_d [41]) & iob_vis_port_0011 [41]) |
((~iob_vis_port_0011_d [39]) & iob_vis_port_0011 [39]) |
((~iob_vis_port_0011_d [37]) & iob_vis_port_0011 [37]) |
((~iob_vis_port_0011_d [35]) & iob_vis_port_0011 [35]) |
((~iob_vis_port_0011_d [33]) & iob_vis_port_0011 [33]) ;
// delay debug port a bus to match output pins
always @(posedge cmp_top.iop.iobdg.jbus_rclk) begin
dbg_dq_d3 <= dbg_dq_d2 ;
dbg_dq_d2 <= dbg_dq_d1 ;
dbg_dq_d1 <= dbg_dq ;
end
assign #1 dbg_dq_pin = dbg_dq_d3 ;
// drive debug port a bus
assign debug_port_a_vld = (db_enet_control_cfg [3:0] === 4'b0100) ? iob_vis_port [43] :
(db_enet_control_cfg [3:0] === 4'b0011) ? (iob_vis_port [43] & (~iob_vis_port [42])) |
(iob_vis_port [41] & (~iob_vis_port [40])) |
(iob_vis_port [39] & (~iob_vis_port [38])) |
(iob_vis_port [37] & (~iob_vis_port [36])) |
(iob_vis_port [35] & (~iob_vis_port [34])) |
(iob_vis_port [33] & (~iob_vis_port [32])) :
(db_enet_control_cfg [3:0] === 4'b0010) ? 1'b1 :
(db_enet_control_cfg [3:0] === 4'b0001) ? l2q_data_vld :
(db_enet_control_cfg [3:0] === 4'b0000) ? l2q_data_vld :
1'b0 ;
assign debug_port_a = (db_enet_control_cfg [3:0] === 4'b0100) ? debug_port_a_0100 :
(db_enet_control_cfg [3:0] === 4'b0011) ? debug_port_a_0011 :
(db_enet_control_cfg [3:0] === 4'b0010) ? debug_port_a_0010 :
(db_enet_control_cfg [3:0] === 4'b0001) ? debug_port_a_0001 :
(db_enet_control_cfg [3:0] === 4'b0000) ? debug_port_a_0000 :
40'hXXXXXXXXXX ;
assign debug_port_a_0100 = {
iob_vis_port [39:35],
iob_vis_port [41], // check with Bill
iob_vis_port [33:0]
} ;
assign debug_port_a_0011 = {
1'b0,
soh,
(iob_vis_port [43] & (~iob_vis_port [42])),
(iob_vis_port [41] & (~iob_vis_port [40])),
(iob_vis_port [39] & (~iob_vis_port [38])),
(iob_vis_port [37] & (~iob_vis_port [36])),
(iob_vis_port [35] & (~iob_vis_port [34])),
(iob_vis_port [33] & (~iob_vis_port [32])),
iob_vis_port [31:0]
} ;
assign debug_port_a_0010 = {
iob_vis_port [39:0]
} ;
assign debug_port_a_0001 = {l2q_data [39:30], l2q_data [47:40], l2q_data[21:0]} ;
assign debug_port_a_0000 = l2q_data ;
////////////////////////////////////////////////////////////////////////////////
// drive all the permutations of debug port a and iob vis for the tester patterns
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// debug port a - 0010 & iob vis - 0000
////////////////////////////////////////////////////////////////////////////////
assign #1 dbg_dq_a4i0 = dbg_dq_porta_0100_iob_0000_d3 ;
always @(posedge cmp_top.iop.iobdg.jbus_rclk) begin
dbg_dq_porta_0100_iob_0000_d3 <= dbg_dq_porta_0100_iob_0000_d2 ;
dbg_dq_porta_0100_iob_0000_d2 <= dbg_dq_porta_0100_iob_0000_d1 ;
dbg_dq_porta_0100_iob_0000_d1 <= dbg_dq_porta_0100_iob_0000 ;
end
assign dbg_dq_porta_0100_iob_0000 = (debug_porta_0100_iob_0000_vld) ? debug_porta_0100_iob_0000 :
(~debug_porta_0100_iob_0000_vld) ? db_enet_idleval_cfg [39:0] :
40'hXXXXXXXXXX ;
assign debug_porta_0100_iob_0000_vld = iob_vis_port_0000 [43] ;
assign debug_porta_0100_iob_0000 = {
iob_vis_port_0000 [39:35],
iob_vis_port_0000 [40],
iob_vis_port_0000 [33:0]
} ;
////////////////////////////////////////////////////////////////////////////////
// debug port a - 0010 & iob vis - 0000
////////////////////////////////////////////////////////////////////////////////
assign #1 dbg_dq_a2i0 = dbg_dq_porta_0010_iob_0000_d3 ;
always @(posedge cmp_top.iop.iobdg.jbus_rclk) begin
dbg_dq_porta_0010_iob_0000_d3 <= dbg_dq_porta_0010_iob_0000_d2 ;
dbg_dq_porta_0010_iob_0000_d2 <= dbg_dq_porta_0010_iob_0000_d1 ;
dbg_dq_porta_0010_iob_0000_d1 <= dbg_dq_porta_0010_iob_0000 ;
end
assign dbg_dq_porta_0010_iob_0000 = (debug_porta_0010_iob_0000_vld) ? debug_porta_0010_iob_0000 :
(~debug_porta_0010_iob_0000_vld) ? db_enet_idleval_cfg [39:0] :
40'hXXXXXXXXXX ;
assign debug_porta_0010_iob_0000_vld = 1'b1 ;
assign debug_porta_0010_iob_0000 = iob_vis_port_0000 [39:0] ;
////////////////////////////////////////////////////////////////////////////////
// debug port a - 0010 & iob vis - 0001
////////////////////////////////////////////////////////////////////////////////
assign #1 dbg_dq_a2i1 = dbg_dq_porta_0010_iob_0001_d3 ;
always @(posedge cmp_top.iop.iobdg.jbus_rclk) begin
dbg_dq_porta_0010_iob_0001_d3 <= dbg_dq_porta_0010_iob_0001_d2 ;
dbg_dq_porta_0010_iob_0001_d2 <= dbg_dq_porta_0010_iob_0001_d1 ;
dbg_dq_porta_0010_iob_0001_d1 <= dbg_dq_porta_0010_iob_0001 ;
end
assign dbg_dq_porta_0010_iob_0001 = (debug_porta_0010_iob_0001_vld) ? debug_porta_0010_iob_0001 :
(~debug_porta_0010_iob_0001_vld) ? db_enet_idleval_cfg [39:0] :
40'hXXXXXXXXXX ;
assign debug_porta_0010_iob_0001_vld = 1'b1 ;
assign debug_porta_0010_iob_0001 = iob_vis_port_0001 [39:0] ;
////////////////////////////////////////////////////////////////////////////////
// debug port a - 0010 & iob vis - 0010
////////////////////////////////////////////////////////////////////////////////
assign #1 dbg_dq_a2i2 = dbg_dq_porta_0010_iob_0010_d3 ;
always @(posedge cmp_top.iop.iobdg.jbus_rclk) begin
dbg_dq_porta_0010_iob_0010_d3 <= dbg_dq_porta_0010_iob_0010_d2 ;
dbg_dq_porta_0010_iob_0010_d2 <= dbg_dq_porta_0010_iob_0010_d1 ;
dbg_dq_porta_0010_iob_0010_d1 <= dbg_dq_porta_0010_iob_0010 ;
end
assign dbg_dq_porta_0010_iob_0010 = (debug_porta_0010_iob_0010_vld) ? debug_porta_0010_iob_0010 :
(~debug_porta_0010_iob_0010_vld) ? db_enet_idleval_cfg [39:0] :
40'hXXXXXXXXXX ;
assign debug_porta_0010_iob_0010_vld = 1'b1 ;
assign debug_porta_0010_iob_0010 = iob_vis_port_0010 [39:0] ;
////////////////////////////////////////////////////////////////////////////////
// debug port a - 0010 & iob vis - 0011
////////////////////////////////////////////////////////////////////////////////
assign #1 dbg_dq_a2i3 = dbg_dq_porta_0010_iob_0011_d3 ;
always @(posedge cmp_top.iop.iobdg.jbus_rclk) begin
dbg_dq_porta_0010_iob_0011_d3 <= dbg_dq_porta_0010_iob_0011_d2 ;
dbg_dq_porta_0010_iob_0011_d2 <= dbg_dq_porta_0010_iob_0011_d1 ;
dbg_dq_porta_0010_iob_0011_d1 <= dbg_dq_porta_0010_iob_0011 ;
end
assign dbg_dq_porta_0010_iob_0011 = (debug_porta_0010_iob_0011_vld) ? debug_porta_0010_iob_0011 :
(~debug_porta_0010_iob_0011_vld) ? db_enet_idleval_cfg [39:0] :
40'hXXXXXXXXXX ;
assign debug_porta_0010_iob_0011_vld = 1'b1 ;
assign debug_porta_0010_iob_0011 = iob_vis_port_0011 [39:0] ;
////////////////////////////////////////////////////////////////////////////////
// debug port a - 0010 & iob vis - 0110
////////////////////////////////////////////////////////////////////////////////
assign #1 dbg_dq_a2i6 = dbg_dq_porta_0010_iob_0110_d3 ;
always @(posedge cmp_top.iop.iobdg.jbus_rclk) begin
dbg_dq_porta_0010_iob_0110_d3 <= dbg_dq_porta_0010_iob_0110_d2 ;
dbg_dq_porta_0010_iob_0110_d2 <= dbg_dq_porta_0010_iob_0110_d1 ;
dbg_dq_porta_0010_iob_0110_d1 <= dbg_dq_porta_0010_iob_0110 ;
end
assign dbg_dq_porta_0010_iob_0110 = (debug_porta_0010_iob_0110_vld) ? debug_porta_0010_iob_0110 :
(~debug_porta_0010_iob_0110_vld) ? db_enet_idleval_cfg [39:0] :
40'hXXXXXXXXXX ;
assign debug_porta_0010_iob_0110_vld = 1'b1 ;
assign debug_porta_0010_iob_0110 = iob_vis_port_0110 [39:0] ;
////////////////////////////////////////////////////////////////////////////////
// debug port a - 0010 & iob vis - 0111
////////////////////////////////////////////////////////////////////////////////
assign #1 dbg_dq_a2i7 = dbg_dq_porta_0010_iob_0111_d3 ;
always @(posedge cmp_top.iop.iobdg.jbus_rclk) begin
dbg_dq_porta_0010_iob_0111_d3 <= dbg_dq_porta_0010_iob_0111_d2 ;
dbg_dq_porta_0010_iob_0111_d2 <= dbg_dq_porta_0010_iob_0111_d1 ;
dbg_dq_porta_0010_iob_0111_d1 <= dbg_dq_porta_0010_iob_0111 ;
end
assign dbg_dq_porta_0010_iob_0111 = (debug_porta_0010_iob_0111_vld) ? debug_porta_0010_iob_0111 :
(~debug_porta_0010_iob_0111_vld) ? db_enet_idleval_cfg [39:0] :
40'hXXXXXXXXXX ;
assign debug_porta_0010_iob_0111_vld = 1'b1 ;
assign debug_porta_0010_iob_0111 = iob_vis_port_0111 [39:0] ;
////////////////////////////////////////////////////////////////////////////////
// debug port a - 0011 & iob vis - 0111
////////////////////////////////////////////////////////////////////////////////
assign #1 dbg_dq_a3i7 = dbg_dq_porta_0011_iob_0111_d3 ;
always @(posedge cmp_top.iop.iobdg.jbus_rclk) begin
dbg_dq_porta_0011_iob_0111_d3 <= dbg_dq_porta_0011_iob_0111_d2 ;
dbg_dq_porta_0011_iob_0111_d2 <= dbg_dq_porta_0011_iob_0111_d1 ;
dbg_dq_porta_0011_iob_0111_d1 <= dbg_dq_porta_0011_iob_0111 ;
end
assign dbg_dq_porta_0011_iob_0111 = (debug_porta_0011_iob_0111_vld) ? debug_porta_0011_iob_0111 :
(~debug_porta_0011_iob_0111_vld) ? db_enet_idleval_cfg [39:0] :
40'hXXXXXXXXXX ;
assign debug_porta_0011_iob_0111_vld = iob_vis_port_0111 [43] | iob_vis_port_0111 [41] | iob_vis_port_0111 [39] | iob_vis_port_0111 [37] | iob_vis_port_0111 [35] | iob_vis_port_0111 [33] ;
assign debug_porta_0011_iob_0111 = {
1'b0,
soh_0111,
(iob_vis_port_0111 [43] & (~iob_vis_port_0111 [42])),
(iob_vis_port_0111 [41] & (~iob_vis_port_0111 [40])),
(iob_vis_port_0111 [39] & (~iob_vis_port_0111 [38])),
(iob_vis_port_0111 [37] & (~iob_vis_port_0111 [36])),
(iob_vis_port_0111 [35] & (~iob_vis_port_0111 [34])),
(iob_vis_port_0111 [33] & (~iob_vis_port_0111 [32])),
iob_vis_port_0111 [31:0]
} ;
////////////////////////////////////////////////////////////////////////////////
// debug port a - 0011 & iob vis - 0110
////////////////////////////////////////////////////////////////////////////////
assign #1 dbg_dq_a3i6 = dbg_dq_porta_0011_iob_0110_d3 ;
always @(posedge cmp_top.iop.iobdg.jbus_rclk) begin
dbg_dq_porta_0011_iob_0110_d3 <= dbg_dq_porta_0011_iob_0110_d2 ;
dbg_dq_porta_0011_iob_0110_d2 <= dbg_dq_porta_0011_iob_0110_d1 ;
dbg_dq_porta_0011_iob_0110_d1 <= dbg_dq_porta_0011_iob_0110 ;
end
assign dbg_dq_porta_0011_iob_0110 = (debug_porta_0011_iob_0110_vld) ? debug_porta_0011_iob_0110 :
(~debug_porta_0011_iob_0110_vld) ? db_enet_idleval_cfg [39:0] :
40'hXXXXXXXXXX ;
assign debug_porta_0011_iob_0110_vld = iob_vis_port_0110 [43] | iob_vis_port_0110 [41] | iob_vis_port_0110 [39] | iob_vis_port_0110 [37] | iob_vis_port_0110 [35] | iob_vis_port_0110 [33] ;
assign debug_porta_0011_iob_0110 = {
1'b0,
soh_0110,
(iob_vis_port_0110 [43] & (~iob_vis_port_0110 [42])),
(iob_vis_port_0110 [41] & (~iob_vis_port_0110 [40])),
(iob_vis_port_0110 [39] & (~iob_vis_port_0110 [38])),
(iob_vis_port_0110 [37] & (~iob_vis_port_0110 [36])),
(iob_vis_port_0110 [35] & (~iob_vis_port_0110 [34])),
(iob_vis_port_0110 [33] & (~iob_vis_port_0110 [32])),
iob_vis_port_0110 [31:0]
} ;
////////////////////////////////////////////////////////////////////////////////
// debug port a - 0011 & iob vis - 0011
////////////////////////////////////////////////////////////////////////////////
assign #1 dbg_dq_a3i3 = dbg_dq_porta_0011_iob_0011_d3 ;
always @(posedge cmp_top.iop.iobdg.jbus_rclk) begin
dbg_dq_porta_0011_iob_0011_d3 <= dbg_dq_porta_0011_iob_0011_d2 ;
dbg_dq_porta_0011_iob_0011_d2 <= dbg_dq_porta_0011_iob_0011_d1 ;
dbg_dq_porta_0011_iob_0011_d1 <= dbg_dq_porta_0011_iob_0011 ;
end
assign dbg_dq_porta_0011_iob_0011 = (debug_porta_0011_iob_0011_vld) ? debug_porta_0011_iob_0011 :
(~debug_porta_0011_iob_0011_vld) ? db_enet_idleval_cfg [39:0] :
40'hXXXXXXXXXX ;
assign debug_porta_0011_iob_0011_vld = iob_vis_port_0011 [43] | iob_vis_port_0011 [41] | iob_vis_port_0011 [39] | iob_vis_port_0011 [37] | iob_vis_port_0011 [35] | iob_vis_port_0011 [33] ;
assign debug_porta_0011_iob_0011 = {
1'b0,
soh_0011,
(iob_vis_port_0011 [43] & (~iob_vis_port_0011 [42])),
(iob_vis_port_0011 [41] & (~iob_vis_port_0011 [40])),
(iob_vis_port_0011 [39] & (~iob_vis_port_0011 [38])),
(iob_vis_port_0011 [37] & (~iob_vis_port_0011 [36])),
(iob_vis_port_0011 [35] & (~iob_vis_port_0011 [34])),
(iob_vis_port_0011 [33] & (~iob_vis_port_0011 [32])),
iob_vis_port_0011 [31:0]
} ;
////////////////////////////////////////////////////////////////////////////////
// drive the iob debug port buses
////////////////////////////////////////////////////////////////////////////////
assign iob_vis_port = (iob_vis_select_cfg [3:0] === 4'b0111) ? iob_vis_port_0111 :
(iob_vis_select_cfg [3:0] === 4'b0110) ? iob_vis_port_0110 :
(iob_vis_select_cfg [3:0] === 4'b0011) ? iob_vis_port_0011 :
(iob_vis_select_cfg [3:0] === 4'b0010) ? iob_vis_port_0010 :
(iob_vis_select_cfg [3:0] === 4'b0001) ? iob_vis_port_0001 :
(iob_vis_select_cfg [3:0] === 4'b0000) ? iob_vis_port_0000 :
44'h0 ;
always @(posedge cmp_top.iop.iobdg.jbus_rclk) begin
iob_vis_port_d <= iob_vis_port ;
iob_vis_port_0111_d <= iob_vis_port_0111 ;
iob_vis_port_0110_d <= iob_vis_port_0110 ;
iob_vis_port_0011_d <= iob_vis_port_0011 ;
iob_vis_port_0001_d <= iob_vis_port_0001 ;
end
assign iob_vis_port_0111 = {
cmp_top.iop.jbi_iob_spi_vld, // spi ack vld
cmp_top.iop.iob_jbi_spi_stall, // spi ack stall
cmp_top.iop.iob_jbi_spi_vld, // spi req vld
cmp_top.iop.jbi_iob_spi_stall, // spi req stall
cmp_top.iop.dram13_iob_vld, // dram1 ack vld
cmp_top.iop.iob_dram13_stall, // dram1 ack stall
cmp_top.iop.iob_dram13_vld, // dram1 req vld
cmp_top.iop.dram13_iob_stall, // dram1 req stall
cmp_top.iop.dram02_iob_vld, // dram0 ack vld
cmp_top.iop.iob_dram02_stall, // dram 0 ack stall
cmp_top.iop.iob_dram02_vld, // dram0 req vld
cmp_top.iop.dram02_iob_stall, // dram0 req stall
cmp_top.iop.dram13_iob_data, // dram1 ack
cmp_top.iop.iob_dram13_data, // dram1 req
cmp_top.iop.dram02_iob_data, // dram0 ack
cmp_top.iop.iob_dram02_data, // dram0 req
8'h00,
cmp_top.iop.jbi_iob_spi_data, // spi ack
cmp_top.iop.iob_jbi_spi_data // spi req
};
assign iob_vis_port_0110 = {
cmp_top.iop.tap_iob_vld, // tap ack vld
cmp_top.iop.iob_tap_stall, // tap ack stall
cmp_top.iop.iob_tap_vld, // tap req vld
cmp_top.iop.tap_iob_stall, // tap req stall
4'h0,
cmp_top.iop.clsp_iob_vld, // ctu ack vld
cmp_top.iop.iob_clsp_stall, // ctu ack stall
cmp_top.iop.iob_clsp_vld, // ctu req vld
cmp_top.iop.clsp_iob_stall, // ctu req stall
8'h00,
cmp_top.iop.clsp_iob_data, // ctu ack
cmp_top.iop.iob_clsp_data, // ctu req
cmp_top.iop.tap_iob_data, // tap ack
cmp_top.iop.iob_tap_data // tap req
} ;
assign iob_vis_port_0011 = {
cmp_top.iop.jbi_iob_pio_vld, // jbi ack vld
cmp_top.iop.iob_jbi_pio_stall, // jbi ack stall
cmp_top.iop.iob_jbi_pio_vld, // jbi req vld
cmp_top.iop.jbi_iob_pio_stall, // jbi req stall
24'h000000,
cmp_top.iop.jbi_iob_pio_data // jbi ack
} ;
assign iob_vis_port_0010 = {
cmp_top.iop.jbi_iob_pio_vld, // jbi ack vld
cmp_top.iop.iob_jbi_pio_stall, // jbi ack stall
cmp_top.iop.iob_jbi_pio_vld, // jbi req vld
cmp_top.iop.jbi_iob_pio_stall, // jbi req stall
cmp_top.iop.jbi_iob_pio_data [15:8], // jbi ack [15:8]
cmp_top.iop.iob_jbi_pio_data [63:32] // jbi req [63:32]
} ;
assign iob_vis_port_0001 = {
cmp_top.iop.jbi_iob_pio_vld, // jbi ack vld
cmp_top.iop.iob_jbi_pio_stall, // jbi ack stall
cmp_top.iop.iob_jbi_pio_vld, // jbi req vld
cmp_top.iop.jbi_iob_pio_stall, // jbi req stall
cmp_top.iop.jbi_iob_pio_data [7:0], // jbi ack [7:0]
cmp_top.iop.iob_jbi_pio_data [31:0] // jbi req [31:0]
} ;
`ifdef GATE_SIM_IOBDG
assign iob_vis_port_0000 = {
cmp_top.iop.iobdg.ucb_buf_acpt,
ttype,
cmp_top.iop.iobdg.c2i_packet [`UCB_THR_HI:`UCB_THR_LO],
cmp_top.iop.iobdg.c2i_packet [`UCB_ADDR_LO+37:`UCB_ADDR_LO+3]
} ;
`else
assign iob_vis_port_0000 = {
cmp_top.iop.iobdg.c2i.c2i_sctrl.ucb_buf_acpt,
ttype,
cmp_top.iop.iobdg.c2i.c2i_sdp.c2i_packet [`UCB_THR_HI:`UCB_THR_LO],
cmp_top.iop.iobdg.c2i.c2i_sdp.c2i_packet [`UCB_ADDR_LO+37:`UCB_ADDR_LO+3]
} ;
`endif
//`ifdef GATE_SIM_IOBDG
//assign iob_vis_port_0000 = {
// cmp_top.iop.iobdg.c2i_packet_vld,
// ttype,
// cmp_top.iop.iobdg.c2i_packet [`UCB_THR_HI:`UCB_THR_LO],
// cmp_top.iop.iobdg.c2i_packet [`UCB_ADDR_LO+37:`UCB_ADDR_LO+3]
// } ;
//`else
//assign iob_vis_port_0000 = {
// cmp_top.iop.iobdg.c2i.c2i_sctrl.c2i_packet_vld,
// ttype,
// cmp_top.iop.iobdg.c2i.c2i_sdp.c2i_packet [`UCB_THR_HI:`UCB_THR_LO],
// cmp_top.iop.iobdg.c2i.c2i_sdp.c2i_packet [`UCB_ADDR_LO+37:`UCB_ADDR_LO+3]
// } ;
//`endif
//
wire io_trigin ;
wire io_trigin_pulse;
reg io_trigin_d1;
reg io_trigin_d2;
reg io_trigin_d3;
`ifdef GATE_SIM_IOBDG
`else
assign io_trigin = cmp_top.iop.iobdg.io_trigin ;
`endif
always @(posedge cmp_top.iop.iobdg.jbus_rclk) begin
io_trigin_d1 <= io_trigin ;
io_trigin_d2 <= io_trigin_d1 ;
io_trigin_d3 <= io_trigin_d2 ;
end
assign io_trigin_pulse = io_trigin_d2 & ~io_trigin_d3 ? 1 : 0;
assign l2_armin = db_enet_control_cfg[5] & io_trigin_pulse ? 1 : 0;
////////////////////////////////////////////////////////////////////////////////
// watch the pcx bus for config cycles
////////////////////////////////////////////////////////////////////////////////
`ifdef GATE_SIM_SCTAG
assign pcx_sctag0_data_rdy_px2 = cmp_top.iop.sctag0.iqctl.ff_pcx_sctag_data_rdy_px2_q_tmp ;
assign pcx_sctag1_data_rdy_px2 = cmp_top.iop.sctag1.iqctl.ff_pcx_sctag_data_rdy_px2_q_tmp ;
assign pcx_sctag2_data_rdy_px2 = cmp_top.iop.sctag2.iqctl.ff_pcx_sctag_data_rdy_px2_q_tmp ;
assign pcx_sctag3_data_rdy_px2 = cmp_top.iop.sctag3.iqctl.ff_pcx_sctag_data_rdy_px2_q_tmp ;
`else
assign pcx_sctag0_data_rdy_px2 = cmp_top.iop.sctag0.iqctl.pcx_sctag_data_rdy_px2 ;
assign pcx_sctag1_data_rdy_px2 = cmp_top.iop.sctag1.iqctl.pcx_sctag_data_rdy_px2 ;
assign pcx_sctag2_data_rdy_px2 = cmp_top.iop.sctag2.iqctl.pcx_sctag_data_rdy_px2 ;
assign pcx_sctag3_data_rdy_px2 = cmp_top.iop.sctag3.iqctl.pcx_sctag_data_rdy_px2 ;
`endif
always @(posedge cmp_top.iop.iobdg.cmp_rclk) begin
if ((cmp_top.iop.pcx_iob_data_rdy_px2) &&
(cmp_top.iop.pcx_iob_data_px2 [`PCX_VLD]) &&
(cmp_top.iop.pcx_iob_data_px2 [`PCX_RQ_HI:`PCX_RQ_LO] == `STORE_RQ)
) begin
case (cmp_top.iop.pcx_iob_data_px2 [`PCX_AD_HI:`PCX_AD_LO])
40'h98_0000_1000 : iob_vis_select_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_1800 : l2_vis_control_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_1820 : l2_vis_mask_a_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_1828 : l2_vis_mask_b_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_1830 : l2_vis_compare_a_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_1838 : l2_vis_compare_b_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_1840 : l2_trig_delay_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_2000 : db_enet_control_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_2008 : db_enet_idleval_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'hA9_0000_0000 : l2c0_control_reg_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'hA9_0000_0040 : l2c1_control_reg_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'hA9_0000_0080 : l2c2_control_reg_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'hA9_0000_00c0 : l2c3_control_reg_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_2100 : db_jbus_control_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_2140 : db_jbus_mask_a_hi_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_2148 : db_jbus_compare_a_hi_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_2150 : db_jbus_count_a_hi_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_2160 : db_jbus_mask_b_hi_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_2168 : db_jbus_compare_b_hi_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_2170 : db_jbus_count_b_hi_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_2180 : db_jbus_mask_a_lo_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_2188 : db_jbus_compare_a_lo_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_2190 : db_jbus_count_a_lo_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_21a0 : db_jbus_mask_b_lo_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_21a8 : db_jbus_compare_b_lo_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
40'h98_0000_21b0 : db_jbus_count_b_lo_cfg = cmp_top.iop.pcx_iob_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
endcase // case
end // if
if ((pcx_sctag0_data_rdy_px2) &&
(cmp_top.iop.sctag0.pcx_sctag_data_px2 [`PCX_VLD]) &&
(cmp_top.iop.sctag0.pcx_sctag_data_px2 [`PCX_RQ_HI:`PCX_RQ_LO] == `STORE_RQ) &&
(cmp_top.iop.sctag0.pcx_sctag_data_px2 [`PCX_AD_HI:`PCX_AD_LO] == 40'ha9_0000_0000)
) begin
l2c0_control_reg_cfg = cmp_top.iop.sctag0.pcx_sctag_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
end // if
if ((pcx_sctag1_data_rdy_px2) &&
(cmp_top.iop.sctag1.pcx_sctag_data_px2 [`PCX_VLD]) &&
(cmp_top.iop.sctag1.pcx_sctag_data_px2 [`PCX_RQ_HI:`PCX_RQ_LO] == `STORE_RQ) &&
(cmp_top.iop.sctag1.pcx_sctag_data_px2 [`PCX_AD_HI:`PCX_AD_LO] == 40'ha9_0000_0040)
) begin
l2c1_control_reg_cfg = cmp_top.iop.sctag1.pcx_sctag_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
end // if
if ((pcx_sctag2_data_rdy_px2) &&
(cmp_top.iop.sctag2.pcx_sctag_data_px2 [`PCX_VLD]) &&
(cmp_top.iop.sctag2.pcx_sctag_data_px2 [`PCX_RQ_HI:`PCX_RQ_LO] == `STORE_RQ) &&
(cmp_top.iop.sctag2.pcx_sctag_data_px2 [`PCX_AD_HI:`PCX_AD_LO] == 40'ha9_0000_0080)
) begin
l2c2_control_reg_cfg = cmp_top.iop.sctag2.pcx_sctag_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
end // if
if ((pcx_sctag3_data_rdy_px2) &&
(cmp_top.iop.sctag3.pcx_sctag_data_px2 [`PCX_VLD]) &&
(cmp_top.iop.sctag3.pcx_sctag_data_px2 [`PCX_RQ_HI:`PCX_RQ_LO] == `STORE_RQ) &&
(cmp_top.iop.sctag3.pcx_sctag_data_px2 [`PCX_AD_HI:`PCX_AD_LO] == 40'ha9_0000_00c0)
) begin
l2c3_control_reg_cfg = cmp_top.iop.sctag3.pcx_sctag_data_px2 [`PCX_DA_HI:`PCX_DA_LO] ;
end // if
end
////////////////////////////////////////////////////////////////////////////////
// l2 visibility ports
////////////////////////////////////////////////////////////////////////////////
// watch the l2c buses for valid cycles
initial begin
l2_dbgbus_01_d1<= 40'h0000000000 ;
l2_dbgbus_23_d1<= 40'h0000000000 ;
l2_dbgbus_01_d2<= 40'h0000000000 ;
l2_dbgbus_23_d2<= 40'h0000000000 ;
end
always @(posedge cmp_top.iop.iobdg.cmp_rclk) begin
l2_dbgbus_01_d1 <= cmp_top.iop.l2_dbgbus_01 ;
l2_dbgbus_23_d1 <= cmp_top.iop.l2_dbgbus_23 ;
l2_dbgbus_01_d2 <= l2_dbgbus_01_d1 ;
l2_dbgbus_23_d2 <= l2_dbgbus_23_d1 ;
end
assign l2_dbgbus = l2c0_control_reg_cfg [20] | l2c1_control_reg_cfg [20] ? l2_dbgbus_01_d2 :
l2c2_control_reg_cfg [20] | l2c3_control_reg_cfg [20] ? l2_dbgbus_23_d2 :
40'hXXXXXXXXXX ;
assign l2_dbgbus_rdy = l2c0_control_reg_cfg [20] | l2c1_control_reg_cfg [20] ? l2_dbgbus_01_d2 [39] :
l2c2_control_reg_cfg [20] | l2c3_control_reg_cfg [20] ? l2_dbgbus_23_d2 [39] :
1'bX ;
assign l2_bus = {
l2q_timestamp [7:0],
l2_dbgbus [38:35],
l2q_drop,
l2_dbgbus [34:0]
} ;
assign l2_mask_a =
l2_dbgbus [38:0]
&
{
l2_vis_mask_a_cfg [51:48], // 4
l2_vis_mask_a_cfg [44:40], // 5
l2_vis_mask_a_cfg [33:8], // 26
l2_vis_mask_a_cfg [5:2] // 5
} ;
assign l2_mask_b =
l2_dbgbus [38:0]
&
{
l2_vis_mask_b_cfg [51:48], // 4
l2_vis_mask_b_cfg [44:40], // 5
l2_vis_mask_b_cfg [33:8], // 26
l2_vis_mask_b_cfg [5:2] // 5
} ;
assign l2q_wr_a = (l2_vis_control_cfg [3] &&
l2_dbgbus_rdy &&
(l2_mask_a === {
l2_vis_compare_a_cfg [51:48],
l2_vis_compare_a_cfg [44:40],
l2_vis_compare_a_cfg [33:8],
l2_vis_compare_a_cfg [5:2]
})
) ? 1 : 0 ;
assign l2q_wr_b = (l2_vis_control_cfg [3] &&
l2_dbgbus_rdy &&
(l2_mask_b === {
l2_vis_compare_b_cfg [51:48],
l2_vis_compare_b_cfg [44:40],
l2_vis_compare_b_cfg [33:8],
l2_vis_compare_b_cfg [5:2]
})
) ? 1 : 0 ;
assign l2q_wr = l2q_wr_a || l2q_wr_b;
// l2 queue
initial begin
l2q_rd_ptr = 6'b000000 ;
l2q_rd_ptr_d1 = 6'b000000 ;
l2q_wr_ptr = 6'b000000 ;
l2q_rd_ptr_cmp = 6'b000000 ;
l2q_wr_ptr_jbus = 6'b000000 ;
l2q_drop = 1'b0 ;
end
assign l2q_wr_ptr_ns = l2q_wr_ptr + 1 ;
assign l2q_full = ((l2q_rd_ptr_cmp [4:0] == l2q_wr_ptr_ns [4:0]) && (l2q_rd_ptr_cmp [5] != l2q_wr_ptr_ns [5])) ? 1'b1 : 1'b0 ;
always @(posedge cmp_top.iop.iobdg.cmp_rclk) begin
if (l2q_wr) begin
l2q [l2q_wr_ptr[4:0]] <= l2_bus ;
end
if (l2q_wr && ~l2q_full) begin
l2q_wr_ptr <= l2q_wr_ptr_ns ;
l2q_drop <= 1'b0 ;
end
if (l2q_wr && l2q_full) begin
l2q_drop <= 1'b1 ;
end
if (cmp_top.iop.iobdg.rx_sync) begin
l2q_rd_ptr_cmp <= l2q_rd_ptr_d1 ;
end
if (cmp_top.iop.iobdg.tx_sync) begin
l2q_wr_ptr_jbus <= l2q_wr_ptr ;
end
end
assign l2q_rd_ptr_ns = l2q_rd_ptr + 1 ;
assign l2q_empty = (l2q_rd_ptr == l2q_wr_ptr_jbus_d1) ? 1'b1 : 1'b0 ;
assign l2q_rd = ~l2q_empty ;
integer i;
initial
begin
for(i=0; i< 32; i=i+1)
begin
l2q[i] = 48'hffffffffffff;
end
end
always @(posedge cmp_top.iop.iobdg.jbus_rclk) begin
if (l2q_rd) begin
l2q_rd_ptr <= l2q_rd_ptr_ns ;
end
l2q_rd_ptr_d1 <= l2q_rd_ptr ;
l2q_data_vld <= l2q_rd ;
l2q_data <= l2q [l2q_rd_ptr[4:0]] ;
l2q_wr_ptr_jbus_d1 <= l2q_wr_ptr_jbus ;
end
assign l2q_timestamp_ns = (cmp_top.iop.iobdg.rst_l == 1'b0) ? 8'h00 : (l2q_timestamp + 1) ;
always @(posedge cmp_top.iop.iobdg.cmp_rclk) begin
l2q_timestamp <= l2q_timestamp_ns ;
end
////////////////////////////////////////////////////////////////////////////////
// trigout
////////////////////////////////////////////////////////////////////////////////
reg dbg_trigout;
reg dbg_trigout_cmpclk;
reg dbg_trigout_jbusclk;
initial begin
l2_trig_delay_cnt_ps = 8'h00 ;
dbg_trigout_ps = 1'b0 ;
dbg_trigout_pin = 1'b0 ;
dbg_trigout = 1'b0 ;
dbg_trigout_cmpclk = 1'b0 ;
dbg_trigout_jbusclk = 1'b0 ;
end
assign l2_trig_delay_cnt_ns = (l2q_wr_b && l2_vis_control_cfg [2]) ? l2_trig_delay_cfg [31:0] :
((l2_trig_delay_cnt_ps !== 8'h00) && l2_vis_control_cfg [2]) ? l2_trig_delay_cnt_ps - 1 :
8'h00 ;
always @(posedge cmp_top.iop.iobdg.cmp_rclk) begin
l2_trig_delay_cnt_ps <= l2_trig_delay_cnt_ns ;
end
assign dbg_trigout_ns = ((l2_trig_delay_cnt_ps === 8'h01) && (l2_trig_delay_cnt_ns === 8'h00)) ? 1'b1 :
1'b0 ;
always @(posedge cmp_top.iop.iobdg.cmp_rclk) begin
dbg_trigout_ps <= dbg_trigout_ns ;
end
always @(posedge cmp_top.iop.iobdg.cmp_rclk) begin
if(dbg_trigout_ns) begin
dbg_trigout <= 1'b1 ;
end
else if(cmp_top.iop.iobdg.tx_sync) begin
dbg_trigout <= 1'b0 ;
end
end
always @(posedge cmp_top.iop.iobdg.cmp_rclk) begin
if(cmp_top.iop.iobdg.tx_sync) begin
dbg_trigout_cmpclk <= dbg_trigout ;
end
end
always @(posedge cmp_top.iop.iobdg.jbus_rclk) begin
dbg_trigout_jbusclk <= dbg_trigout_cmpclk ;
dbg_trigout_pin <= dbg_trigout_jbusclk ;
end
////////////////////////////////////////////////////////////////////////////////
// debug port b
////////////////////////////////////////////////////////////////////////////////
always @(posedge cmp_top.iop.iobdg.jbus_rclk) begin
dbg_portb_lo_d1 <= dbg_portb_lo ;
dbg_portb_lo_d2 <= dbg_portb_lo_d1 ;
dbg_portb_hi_d1 <= dbg_portb_hi ;
dbg_portb_hi_d2 <= dbg_portb_hi_d1 ;
dbg_portb_lo_vld_d1 <= dbg_portb_lo_vld ;
dbg_portb_lo_vld_d2 <= dbg_portb_lo_vld_d1 ;
dbg_portb_hi_vld_d1 <= dbg_portb_hi_vld ;
dbg_portb_hi_vld_d2 <= dbg_portb_hi_vld_d1 ;
end
wire dbg_portb_lo_vo_a;
wire dbg_portb_lo_vo_b;
reg [7:0] dbg_portb_lo_count_a;
reg [7:0] dbg_portb_lo_count_b;
wire dbg_portb_lo_hit_a;
wire dbg_portb_lo_hit_b;
initial
begin
dbg_portb_lo_count_a = 8'h00;
dbg_portb_lo_count_b = 8'h00;
end
assign dbg_portb_lo_vo_a = db_jbus_count_a_lo_cfg[8];
assign dbg_portb_lo_vo_b = db_jbus_count_b_lo_cfg[8];
//assign dbg_portb_lo_hit_a = (db_jbus_mask_a_lo_cfg [45] &
// ((~db_jbus_mask_a_lo_cfg [44]) & (dbg_portb_mask_a_lo [43:0] === db_jbus_compare_a_lo_cfg [43:0])) |
// (( db_jbus_mask_a_lo_cfg [44]) & (dbg_portb_mask_a_lo [43:0] !== db_jbus_compare_a_lo_cfg [43:0]))
// ) ? 1'b1 : 1'b0 ;
//
//assign dbg_portb_lo_hit_b = (db_jbus_mask_b_lo_cfg [45] &
// ((~db_jbus_mask_b_lo_cfg [44]) & (dbg_portb_mask_b_lo [43:0] === db_jbus_compare_b_lo_cfg [43:0])) |
// (( db_jbus_mask_b_lo_cfg [44]) & (dbg_portb_mask_b_lo [43:0] !== db_jbus_compare_b_lo_cfg [43:0]))
// ) ? 1'b1 : 1'b0 ;
assign dbg_portb_lo_hit_a = (db_jbus_mask_a_lo_cfg [45] &
((~db_jbus_mask_a_lo_cfg [44]) & (dbg_portb_mask_a_lo [43:0] == db_jbus_compare_a_lo_cfg [43:0])) |
(( db_jbus_mask_a_lo_cfg [44]) & (dbg_portb_mask_a_lo [43:0] != db_jbus_compare_a_lo_cfg [43:0]))
) ;
assign dbg_portb_lo_hit_b = (db_jbus_mask_b_lo_cfg [45] &
((~db_jbus_mask_b_lo_cfg [44]) & (dbg_portb_mask_b_lo [43:0] == db_jbus_compare_b_lo_cfg [43:0])) |
(( db_jbus_mask_b_lo_cfg [44]) & (dbg_portb_mask_b_lo [43:0] != db_jbus_compare_b_lo_cfg [43:0]))
) ;
always @(posedge cmp_top.iop.iobdg.jbus_rclk) begin
if(dbg_portb_lo_hit_a) begin
dbg_portb_lo_count_a = db_jbus_count_a_lo_cfg[7:0];
end
else if(dbg_portb_lo_count_a != 0) begin
dbg_portb_lo_count_a = dbg_portb_lo_count_a - 1 ;
end
if(dbg_portb_lo_hit_b) begin
dbg_portb_lo_count_b = db_jbus_count_b_lo_cfg[7:0];
end
else if(dbg_portb_lo_count_b != 0) begin
dbg_portb_lo_count_b = dbg_portb_lo_count_b - 1 ;
end
end
assign dbg_portb_lo_vld = (db_jbus_control_cfg[16] & (dbg_portb_lo_hit_a || dbg_portb_lo_hit_b ||
((|dbg_portb_lo_count_a) & ((dbg_portb_lo_vld_sel & dbg_portb_lo_vo_a) || ~dbg_portb_lo_vo_a)) ||
((|dbg_portb_lo_count_b) & ((dbg_portb_lo_vld_sel & dbg_portb_lo_vo_b) || ~dbg_portb_lo_vo_b)))) ?1'b1 : 1'b0 ;
//assign dbg_portb_lo_vld = (db_jbus_mask_a_lo_cfg [45] &
// ((~db_jbus_mask_a_lo_cfg [44]) & (dbg_portb_mask_a_lo [43:0] === db_jbus_compare_a_lo_cfg [43:0])) |
// (( db_jbus_mask_a_lo_cfg [44]) & (dbg_portb_mask_a_lo [43:0] !== db_jbus_compare_a_lo_cfg [43:0]))
// ) |
// (db_jbus_mask_b_lo_cfg [45] &
// ((~db_jbus_mask_b_lo_cfg [44]) & (dbg_portb_mask_b_lo [43:0] === db_jbus_compare_b_lo_cfg [43:0])) |
// (( db_jbus_mask_b_lo_cfg [44]) & (dbg_portb_mask_b_lo [43:0] !== db_jbus_compare_b_lo_cfg [43:0]))
// ) ? 1'b1 : 1'b0 ;
//assign dbg_portb_mask_a_lo = (db_jbus_control_cfg [2:0] === 3'b100) ? {dbg_portb_lo_sel [43:41], dbg_portb_lo_vld, dbg_portb_lo_sel [39:0]} & db_jbus_mask_a_lo_cfg [43:0] :
// dbg_portb_lo_sel & db_jbus_mask_a_lo_cfg [43:0] ;
//
//assign dbg_portb_mask_b_lo = (db_jbus_control_cfg [2:0] === 3'b100) ? {dbg_portb_lo_sel [43:41], dbg_portb_lo_vld, dbg_portb_lo_sel [39:0]} & db_jbus_mask_b_lo_cfg [43:0] :
// dbg_portb_lo_sel & db_jbus_mask_a_lo_cfg [43:0] ;
assign dbg_portb_mask_a_lo = {dbg_portb_lo_sel [43:41], dbg_portb_lo_vld, dbg_portb_lo_sel [39:0]} & db_jbus_mask_a_lo_cfg [43:0] ;
assign dbg_portb_mask_b_lo = {dbg_portb_lo_sel [43:41], dbg_portb_lo_vld, dbg_portb_lo_sel [39:0]} & db_jbus_mask_b_lo_cfg [43:0] ;
assign dbg_portb_lo_sel = (db_jbus_control_cfg [2:0] === 3'b000) ? dbg_portb_000 :
(db_jbus_control_cfg [2:0] === 3'b010) ? dbg_portb_lo_010 :
(db_jbus_control_cfg [2:0] === 3'b011) ? dbg_portb_011 :
(db_jbus_control_cfg [2:0] === 3'b100) ? dbg_portb_100 :
48'hXXXXXXXXXXXX ;
assign dbg_portb_lo_vld_sel = (db_jbus_control_cfg [2:0] === 3'b000) ? dbg_portb_000_vld :
(db_jbus_control_cfg [2:0] === 3'b010) ? dbg_portb_lo_010_vld :
(db_jbus_control_cfg [2:0] === 3'b011) ? dbg_portb_011_vld :
(db_jbus_control_cfg [2:0] === 3'b100) ? dbg_portb_100_vld :
48'hXXXXXXXXXXXX ;
//assign dbg_portb_lo = dbg_portb_lo_vld_sel ? dbg_portb_lo_sel : 48'hffffffffffff ;
assign dbg_portb_lo = db_jbus_control_cfg[16] ? dbg_portb_lo_sel : 48'h0 ;
wire dbg_portb_hi_vo_a;
wire dbg_portb_hi_vo_b;
reg [7:0] dbg_portb_hi_count_a;
reg [7:0] dbg_portb_hi_count_b;
wire dbg_portb_hi_hit_a;
wire dbg_portb_hi_hit_b;
initial
begin
dbg_portb_hi_count_a = 8'h00;
dbg_portb_hi_count_b = 8'h00;
end
assign dbg_portb_hi_vo_a = db_jbus_count_a_hi_cfg[8];
assign dbg_portb_hi_vo_b = db_jbus_count_b_hi_cfg[8];
//assign dbg_portb_hi_hit_a = (db_jbus_mask_a_hi_cfg [45] &
// ((~db_jbus_mask_a_hi_cfg [44]) & (dbg_portb_mask_a_hi [43:0] === db_jbus_compare_a_hi_cfg [43:0])) |
// (( db_jbus_mask_a_hi_cfg [44]) & (dbg_portb_mask_a_hi [43:0] !== db_jbus_compare_a_hi_cfg [43:0]))
// ) ? 1'b1 : 1'b0 ;
//
//assign dbg_portb_hi_hit_b = (db_jbus_mask_b_hi_cfg [45] &
// ((~db_jbus_mask_b_hi_cfg [44]) & (dbg_portb_mask_b_hi [43:0] === db_jbus_compare_b_hi_cfg [43:0])) |
// (( db_jbus_mask_b_hi_cfg [44]) & (dbg_portb_mask_b_hi [43:0] !== db_jbus_compare_b_hi_cfg [43:0]))
// ) ? 1'b1 : 1'b0 ;
assign dbg_portb_hi_hit_a = (db_jbus_mask_a_hi_cfg [45] &
((~db_jbus_mask_a_hi_cfg [44]) & (dbg_portb_mask_a_hi [43:0] == db_jbus_compare_a_hi_cfg [43:0])) |
(( db_jbus_mask_a_hi_cfg [44]) & (dbg_portb_mask_a_hi [43:0] != db_jbus_compare_a_hi_cfg [43:0]))
) ;
assign dbg_portb_hi_hit_b = (db_jbus_mask_b_hi_cfg [45] &
((~db_jbus_mask_b_hi_cfg [44]) & (dbg_portb_mask_b_hi [43:0] == db_jbus_compare_b_hi_cfg [43:0])) |
(( db_jbus_mask_b_hi_cfg [44]) & (dbg_portb_mask_b_hi [43:0] != db_jbus_compare_b_hi_cfg [43:0]))
) ;
always @(posedge cmp_top.iop.iobdg.jbus_rclk) begin
if(dbg_portb_hi_hit_a) begin
dbg_portb_hi_count_a = db_jbus_count_a_hi_cfg[7:0];
end
else if(dbg_portb_hi_count_a != 0) begin
dbg_portb_hi_count_a = dbg_portb_hi_count_a - 1 ;
end
if(dbg_portb_hi_hit_b) begin
dbg_portb_hi_count_b = db_jbus_count_b_hi_cfg[7:0];
end
else if(dbg_portb_hi_count_b != 0) begin
dbg_portb_hi_count_b = dbg_portb_hi_count_b - 1 ;
end
end
assign dbg_portb_hi_vld = (db_jbus_control_cfg[16] & (dbg_portb_hi_hit_a | dbg_portb_hi_hit_b ||
((|dbg_portb_hi_count_a) & ((dbg_portb_hi_vld_sel & dbg_portb_hi_vo_a) || ~dbg_portb_hi_vo_a)) ||
((|dbg_portb_hi_count_b) & ((dbg_portb_hi_vld_sel & dbg_portb_hi_vo_b) || ~dbg_portb_hi_vo_b)))) ? 1'b1 : 1'b0 ;
//assign dbg_portb_hi_vld = (db_jbus_mask_a_hi_cfg [45] &
// ((~db_jbus_mask_a_hi_cfg [44]) & (dbg_portb_mask_a_hi [43:0] === db_jbus_compare_a_hi_cfg [43:0])) |
// (( db_jbus_mask_a_hi_cfg [44]) & (dbg_portb_mask_a_hi [43:0] !== db_jbus_compare_a_hi_cfg [43:0]))
// ) |
// (db_jbus_mask_b_hi_cfg [45] &
// ((~db_jbus_mask_b_hi_cfg [44]) & (dbg_portb_mask_b_hi [43:0] === db_jbus_compare_b_hi_cfg [43:0])) |
// (( db_jbus_mask_b_hi_cfg [44]) & (dbg_portb_mask_b_hi [43:0] !== db_jbus_compare_b_hi_cfg [43:0]))
// ) ? 1'b1 : 1'b0 ;
//assign dbg_portb_mask_a_hi = (db_jbus_control_cfg [6:4] === 3'b100) ? {dbg_portb_hi_sel [43:41], dbg_portb_hi_vld, dbg_portb_hi_sel [39:0]} & db_jbus_mask_a_hi_cfg [43:0] :
// dbg_portb_hi_sel & db_jbus_mask_a_hi_cfg [43:0] ;
//
//assign dbg_portb_mask_b_hi = (db_jbus_control_cfg [6:4] === 3'b100) ? {dbg_portb_hi_sel [43:41], dbg_portb_hi_vld, dbg_portb_hi_sel [39:0]} & db_jbus_mask_b_hi_cfg [43:0] :
// dbg_portb_hi_sel & db_jbus_mask_b_hi_cfg [43:0] ;
assign dbg_portb_mask_a_hi = {dbg_portb_hi_sel [43:41], dbg_portb_hi_vld, dbg_portb_hi_sel [39:0]} & db_jbus_mask_a_hi_cfg [43:0] ;
assign dbg_portb_mask_b_hi = {dbg_portb_hi_sel [43:41], dbg_portb_hi_vld, dbg_portb_hi_sel [39:0]} & db_jbus_mask_b_hi_cfg [43:0] ;
assign dbg_portb_hi_sel = (db_jbus_control_cfg [6:4] === 3'b000) ? dbg_portb_000 :
(db_jbus_control_cfg [6:4] === 3'b010) ? dbg_portb_hi_010 :
(db_jbus_control_cfg [6:4] === 3'b011) ? dbg_portb_011 :
(db_jbus_control_cfg [6:4] === 3'b100) ? dbg_portb_100 :
48'hXXXXXXXXXXXX ;
assign dbg_portb_hi_vld_sel = (db_jbus_control_cfg [6:4] === 3'b000) ? dbg_portb_000_vld :
(db_jbus_control_cfg [6:4] === 3'b010) ? dbg_portb_hi_010_vld :
(db_jbus_control_cfg [6:4] === 3'b011) ? dbg_portb_011_vld :
(db_jbus_control_cfg [6:4] === 3'b100) ? dbg_portb_100_vld :
48'hXXXXXXXXXXXX ;
//assign dbg_portb_hi = dbg_portb_hi_vld_sel ? dbg_portb_hi_sel : 48'hffffffffffff ;
assign dbg_portb_hi = db_jbus_control_cfg[16] ? dbg_portb_hi_sel : 48'h0 ;
assign dbg_portb_100_vld = 1'b1 ;
assign dbg_portb_100 = {4'b0000,
iob_vis_port [43:0]} ;
assign dbg_portb_011_vld = (iob_vis_port [43] & (~iob_vis_port [42])) |
(iob_vis_port [41] & (~iob_vis_port [40])) |
(iob_vis_port [39] & (~iob_vis_port [38])) |
(iob_vis_port [37] & (~iob_vis_port [36])) |
(iob_vis_port [35] & (~iob_vis_port [34])) |
(iob_vis_port [33] & (~iob_vis_port [32])) ;
assign dbg_portb_011 = {4'b0000,
(~iob_vis_port_d [43]) & iob_vis_port [43],
(~iob_vis_port_d [41]) & iob_vis_port [41],
iob_vis_port [43] & (~iob_vis_port [42]),
iob_vis_port [41] & (~iob_vis_port [40]),
(~iob_vis_port_d [39]) & iob_vis_port [39],
(~iob_vis_port_d [37]) & iob_vis_port [37],
(~iob_vis_port_d [35]) & iob_vis_port [35],
(~iob_vis_port_d [33]) & iob_vis_port [33],
iob_vis_port [39] & (~iob_vis_port [38]),
iob_vis_port [37] & (~iob_vis_port [36]),
iob_vis_port [35] & (~iob_vis_port [34]),
iob_vis_port [33] & (~iob_vis_port [32]),
iob_vis_port [31:0]} ;
assign dbg_portb_hi_010_vld = (iob_vis_port [43] & (~iob_vis_port [42])) |
(iob_vis_port [41] & (~iob_vis_port [40])) ;
assign dbg_portb_hi_010 = {4'b0000,
(~iob_vis_port_d [43]) & iob_vis_port [43],
(~iob_vis_port_d [41]) & iob_vis_port [41],
iob_vis_port [43] & (~iob_vis_port [42]),
iob_vis_port [41] & (~iob_vis_port [40]),
iob_vis_port [39:0]} ;
//assign dbg_portb_lo_010_vld = (iob_vis_port_0001 [43] & (~iob_vis_port_0001 [42])) |
// (iob_vis_port_0001 [41] & (~iob_vis_port_0001 [40])) ;
assign dbg_portb_lo_010_vld = (iob_vis_port [43] & (~iob_vis_port [42])) |
(iob_vis_port [41] & (~iob_vis_port [40])) ;
assign dbg_portb_lo_010 = {4'b0000,
(~iob_vis_port_d [43]) & iob_vis_port [43],
(~iob_vis_port_d [41]) & iob_vis_port [41],
iob_vis_port [43] & (~iob_vis_port [42]),
iob_vis_port [41] & (~iob_vis_port [40]),
iob_vis_port_0001 [39:0]};
assign dbg_portb_000_vld = l2q_data_vld ;
assign dbg_portb_000 = l2q_data [47:0];
endmodule
|
`include "../../../rtl/verilog/gfx/gfx_fragment_processor.v"
`include "../../../rtl/verilog/gfx/gfx_color.v"
module fragment_bench();
reg clk_i;
reg rst_i;
parameter point_width = 16;
reg [7:0] pixel_alpha_i;
// from raster
reg [point_width-1:0] x_counter_i;
reg [point_width-1:0] y_counter_i;
reg signed [point_width-1:0] z_i;
reg [point_width-1:0] u_i;
reg [point_width-1:0] v_i;
reg [point_width-1:0] bezier_factor0_i;
reg [point_width-1:0] bezier_factor1_i;
reg bezier_inside_i;
reg [31:0] pixel_color_i;
reg write_i;
reg curve_write_i;
reg ack_i;
//to blender
wire [point_width-1:0] pixel_x_o;
wire [point_width-1:0] pixel_y_o;
wire [31:0] pixel_color_o;
wire [7:0] pixel_alpha_o;
wire write_o;
wire ack_o;
// to/from wishbone master read
reg texture_ack_i;
reg [31:0] texture_data_i;
wire [31:2] texture_addr_o;
wire [3:0] texture_sel_o;
wire texture_request_o;
// from wishbone slave
reg texture_enable_i;
reg [31:2] tex0_base_i;
reg [point_width-1:0] tex0_size_x_i;
reg [point_width-1:0] tex0_size_y_i;
reg [1:0] color_depth_i;
reg colorkey_enable_i;
reg [31:0] colorkey_i;
initial begin
$dumpfile("fragment.vcd");
$dumpvars(0,fragment_bench);
// init values
clk_i = 0;
rst_i = 1;
write_i = 0;
curve_write_i = 0;
bezier_inside_i = 0;
texture_enable_i = 0;
color_depth_i = 2'b01;
ack_i = 0;
pixel_alpha_i = 8'hff;
pixel_color_i = 32'h12345678;
tex0_base_i = 32'h12341234;
tex0_size_x_i = 12;
tex0_size_y_i = 10;
u_i = 0;
v_i = 0;
z_i = 10;
bezier_factor0_i = 0;
bezier_factor1_i = 0;
x_counter_i = 0;
y_counter_i = 0;
texture_data_i = 32'hf800ffff;
colorkey_enable_i = 0;
colorkey_i = 32'h00000000;
//timing
#4 rst_i = 0;
#2 write_i = 1;
#2 write_i = 0;
#6 texture_enable_i = 1;
#40 write_i = 1;
#2 write_i = 0;
// end sim
#100 $finish;
end
always @(posedge clk_i)
begin
ack_i <= #1 write_o;
texture_ack_i <= #1 texture_request_o;
end
always begin
#1 clk_i = ~clk_i;
end
gfx_fragment_processor fragment(
.clk_i (clk_i),
.rst_i (rst_i),
.pixel_alpha_i (pixel_alpha_i),
.x_counter_i (x_counter_i),
.y_counter_i (y_counter_i),
.z_i (z_i),
.u_i (u_i),
.v_i (v_i),
.bezier_factor0_i (bezier_factor0_i),
.bezier_factor1_i (bezier_factor1_i),
.bezier_inside_i (bezier_inside_i),
.pixel_color_i (pixel_color_i),
.write_i (write_i),
.curve_write_i (curve_write_i),
.ack_i (ack_i),
.pixel_x_o (pixel_x_o),
.pixel_y_o (pixel_y_o),
.pixel_color_o (pixel_color_o),
.pixel_alpha_o (pixel_alpha_o),
.write_o (write_o),
.ack_o (ack_o),
.texture_ack_i (texture_ack_i),
.texture_data_i (texture_data_i),
.texture_addr_o (texture_addr_o),
.texture_sel_o (texture_sel_o),
.texture_request_o(texture_request_o),
.texture_enable_i (texture_enable_i),
.tex0_base_i (tex0_base_i),
.tex0_size_x_i (tex0_size_x_i),
.tex0_size_y_i (tex0_size_y_i),
.color_depth_i (color_depth_i),
.colorkey_enable_i(colorkey_enable_i),
.colorkey_i (colorkey_i)
);
endmodule
|
`timescale 1ns / 1ps
module SHDCollector #(parameter DNA_DATA_WIDTH = 128, NUM_CLUSTERS = 8, NUM_PES = 8) (
input clk,
input rst,
//Cluster Interface
output reg[NUM_CLUSTERS - 1:0] cluster_rd_en,
input[NUM_CLUSTERS * NUM_PES - 1:0] cluster_data,
input[NUM_CLUSTERS - 1:0] cluster_valid,
//Sender Interface
input sender_ready,
output sender_data_valid,
output[NUM_PES - 1:0] sender_data
);
//Cluster iterator
wire cluster_fetched;
parameter CLUSTER_BITS = $clog2(NUM_CLUSTERS);
reg[CLUSTER_BITS - 1:0] cluster_iterator = 0;
wire advance_cluster_it;
always@(posedge clk) begin
if(rst) begin
cluster_iterator <= 0;
end
else begin
if(advance_cluster_it) begin
cluster_iterator <= cluster_iterator + 1'b1;
end
end
end
assign advance_cluster_it = cluster_fetched;
//Register Input
reg[NUM_PES - 1:0] dna_err_r;
reg dna_err_valid_r;
wire accept_cluster_data;
always@(posedge clk) begin
if(rst) begin
dna_err_r <= 0;
dna_err_valid_r <= 1'b0;
end
else begin
if(accept_cluster_data) begin
dna_err_r <= cluster_data[cluster_iterator*NUM_PES +: NUM_PES];
dna_err_valid_r <= cluster_valid[cluster_iterator];
end
end
end
always@* begin
cluster_rd_en = 0;
cluster_rd_en[cluster_iterator] = accept_cluster_data;
end
assign cluster_fetched = accept_cluster_data && cluster_valid[cluster_iterator];
assign accept_cluster_data = sender_ready;
assign sender_data_valid = dna_err_valid_r;
assign sender_data = dna_err_r;
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// A separate module which instantiates a simple reset combining primitive.
// The primitive is simply an AND gate.
module ResetEither(A_RST,
B_RST,
RST_OUT
) ;
input A_RST;
input B_RST;
output RST_OUT;
assign RST_OUT = A_RST & B_RST ;
endmodule
|
`include "../include/tune.v"
// Pentevo project (c) NedoPC 2011-2012
//
// address generation module for video data fetching
module video_addrgen(
input wire clk, // 28 MHz clock
output reg [20:0] video_addr, // DRAM arbiter signals
input wire video_next, //
input wire line_start, // some video sync signals
input wire int_start, //
input wire vpix, //
input wire scr_page, // which screen to use
input wire mode_atm_n_pent, // decoded modes
input wire mode_zx, //
input wire mode_p_16c, //
input wire mode_p_hmclr, //
//
input wire mode_a_hmclr, //
input wire mode_a_16c, //
input wire mode_a_text, //
input wire mode_a_txt_1page,//
output wire [ 2:0] typos // Y position in text mode symbols
);
wire mode_ag;
assign mode_ag = mode_a_16c | mode_a_hmclr;
wire line_init, frame_init;
wire gnext,tnext,ldaddr;
reg line_start_r;
reg frame_init_r;
reg line_init_r;
always @(posedge clk)
line_start_r <= line_start;
assign line_init = line_start_r & vpix;
assign frame_init = int_start;
reg [13:0] gctr;
reg [7:0] tyctr; // text Y counter
reg [6:0] txctr; // text X counter
reg not_used;
always @(posedge clk)
frame_init_r <= frame_init;
always @(posedge clk)
line_init_r <= line_init;
assign gnext = video_next | frame_init_r;
assign tnext = video_next | line_init_r;
assign ldaddr = mode_a_text ? tnext : gnext;
// gfx counter
//
initial gctr <= 0;
//
always @(posedge clk)
if( frame_init )
gctr <= 0;
else if( gnext )
gctr <= gctr + 1;
// text counters
always @(posedge clk)
if( frame_init )
tyctr <= 8'b0011_0111;
else if( line_init )
tyctr <= tyctr + 1;
always @(posedge clk)
if( line_init )
txctr <= 7'b000_0000;
else if( tnext )
txctr <= txctr + 1;
assign typos = tyctr[2:0];
// zx mode:
// [0] - attr or pix
// [4:1] - horiz pos 0..15 (words)
// [12:5] - vert pos
wire [20:0] addr_zx; // standard zx mode
wire [20:0] addr_phm; // pentagon hardware multicolor
wire [20:0] addr_p16c; // pentagon 16c
wire [20:0] addr_ag; // atm gfx: 16c (x320) or hard multicolor (x640) - same sequence!
wire [20:0] addr_at; // atm text
wire [11:0] addr_zx_pix;
wire [11:0] addr_zx_attr;
wire [11:0] addr_zx_p16c;
assign addr_zx_pix = { gctr[12:11], gctr[7:5], gctr[10:8], gctr[4:1] };
assign addr_zx_attr = { 3'b110, gctr[12:8], gctr[4:1] };
assign addr_zx_p16c = { gctr[13:12], gctr[8:6], gctr[11:9], gctr[5:2] };
assign addr_zx = { 6'b000001, scr_page, 2'b10, ( gctr[0] ? addr_zx_attr : addr_zx_pix ) };
assign addr_phm = { 6'b000001, scr_page, 1'b1, gctr[0], addr_zx_pix };
assign addr_p16c = { 6'b000001, scr_page, ~gctr[0], gctr[1], addr_zx_p16c };
assign addr_ag = { 5'b00000, ~gctr[0], scr_page, 1'b1, gctr[1], gctr[13:2] };
// 5 or 1 +0 or +2 ~4,0 +0k or +2k
// assign addr_at = { 5'b00000, ~txctr[0], scr_page, 1'b1, txctr[1], 2'b00, tyctr[7:3], txctr[6:2] };
// assign addt_et = { 5'b00001, 1'b0 , scr_page, 1'b0, txctr[0], txctr[1], 0, --//00 };
assign addr_at = { 4'b0000,
mode_a_txt_1page, // if 1page, 8 and 10 pages instead of 5,1 and 7,3
mode_a_txt_1page ? 1'b0 : ~txctr[0], // 5 or 1 pages for usual mode
scr_page, // actually not used
~mode_a_txt_1page, // 5,1 (not 4,0) pages for usual mode
mode_a_txt_1page ? txctr[0] : txctr[1], // 0,+2 interleave for even-odd or 0,+1 for 1page
mode_a_txt_1page ? txctr[1] : 1'b0, // sym/attr interleave 0,+1 for 1page
1'b0,
tyctr[7:3],
txctr[6:2]
};
initial video_addr <= 0;
//
always @(posedge clk) if( ldaddr )
begin
{ video_addr[20:15], not_used, video_addr[13:0] } <=
( {21{mode_zx }} & addr_zx ) |
( {21{mode_p_16c }} & addr_p16c) |
( {21{mode_p_hmclr}} & addr_phm ) |
( {21{mode_ag }} & addr_ag ) |
( {21{mode_a_text }} & addr_at ) ;
end
always @(posedge clk)
video_addr[14] <= scr_page;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BOI_BLACKBOX_V
`define SKY130_FD_SC_HD__A21BOI_BLACKBOX_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BOI_BLACKBOX_V
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: openMSP430_fpga.v
//
// *Module Description:
// openMSP430 FPGA Top-level for the Xilinx synthesis.
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 37 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
//----------------------------------------------------------------------------
`include "timescale.v"
`include "openMSP430_defines.v"
module openMSP430_fpga (
// OUTPUTs
aclk_en, // ACLK enable
dbg_freeze, // Freeze peripherals
dbg_uart_txd, // Debug interface: UART TXD
irq_acc, // Interrupt request accepted (one-hot signal)
per_addr, // Peripheral address
per_din, // Peripheral data input
per_wen, // Peripheral write enable (high active)
per_en, // Peripheral enable (high active)
smclk_en, // SMCLK enable
// INPUTs
dbg_uart_rxd, // Debug interface: UART RXD
dco_clk, // Fast oscillator (fast clock)
irq, // Maskable interrupts
lfxt_clk, // Low frequency oscillator (typ 32kHz)
nmi, // Non-maskable interrupt (asynchronous)
per_dout, // Peripheral data output
reset_n // Reset Pin (low active)
);
// OUTPUTs
//=========
output aclk_en; // ACLK enable
output dbg_freeze; // Freeze peripherals
output dbg_uart_txd; // Debug interface: UART TXD
output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
output [7:0] per_addr; // Peripheral address
output [15:0] per_din; // Peripheral data input
output [1:0] per_wen; // Peripheral write enable (high active)
output per_en; // Peripheral enable (high active)
output smclk_en; // SMCLK enable
// INPUTs
//=========
input dbg_uart_rxd; // Debug interface: UART RXD
input dco_clk; // Fast oscillator (fast clock)
input [13:0] irq; // Maskable interrupts
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
input nmi; // Non-maskable interrupt (asynchronous)
input [15:0] per_dout; // Peripheral data output
input reset_n; // Reset Pin (active low)
//=============================================================================
// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
//=============================================================================
wire [`DMEM_MSB:0] dmem_addr;
wire dmem_cen;
wire [15:0] dmem_din;
wire [1:0] dmem_wen;
wire [15:0] dmem_dout;
wire [`PMEM_MSB:0] pmem_addr;
wire pmem_cen;
wire [15:0] pmem_din;
wire [1:0] pmem_wen;
wire [15:0] pmem_dout;
wire mclk;
wire puc;
//=============================================================================
// 2) PROGRAM AND DATA MEMORIES
//=============================================================================
dmem dmem_hi (.WD(dmem_din[15:8]), .RD(dmem_dout[15:8]), .WEN(dmem_wen[1] | dmem_cen), .REN(dmem_cen), .WADDR(dmem_addr) , .RADDR(dmem_addr), .RWCLK(mclk), .RESET(puc));
dmem dmem_lo (.WD(dmem_din[7:0]), .RD(dmem_dout[7:0]), .WEN(dmem_wen[0] | dmem_cen), .REN(dmem_cen), .WADDR(dmem_addr) , .RADDR(dmem_addr), .RWCLK(mclk), .RESET(puc));
pmem pmem_hi (.WD(pmem_din[15:8]), .RD(pmem_dout[15:8]), .WEN(pmem_wen[1] | pmem_cen), .REN(pmem_cen), .WADDR(pmem_addr) , .RADDR(pmem_addr), .RWCLK(mclk), .RESET(puc));
pmem pmem_lo (.WD(pmem_din[7:0]), .RD(pmem_dout[7:0]), .WEN(pmem_wen[0] | pmem_cen), .REN(pmem_cen), .WADDR(pmem_addr) , .RADDR(pmem_addr), .RWCLK(mclk), .RESET(puc));
//=============================================================================
// 3) OPENMSP430
//=============================================================================
openMSP430 openMSP430_0 (
// OUTPUTs
.aclk_en (aclk_en), // ACLK enable
.dbg_freeze (dbg_freeze), // Freeze peripherals
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
.dmem_addr (dmem_addr), // Data Memory address
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
.dmem_din (dmem_din), // Data Memory data input
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_wen (per_wen), // Peripheral write enable (high active)
.per_en (per_en), // Peripheral enable (high active)
.pmem_addr (pmem_addr), // Program Memory address
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
.pmem_din (pmem_din), // Program Memory data input (optional)
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
.puc (puc), // Main system reset
.smclk_en (smclk_en), // SMCLK enable
// INPUTs
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
.dco_clk (dco_clk), // Fast oscillator (fast clock)
.dmem_dout (dmem_dout), // Data Memory data output
.irq (irq), // Maskable interrupts
.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
.nmi (nmi), // Non-maskable interrupt (asynchronous)
.per_dout (per_dout), // Peripheral data output
.pmem_dout (pmem_dout), // Program Memory data output
.reset_n (reset_n) // Reset Pin (low active)
);
endmodule // openMSP430_fpga
|
module ALU_Controller(ALU_op,ALU_ctr);
input [3:0] ALU_op;
output [2:0] ALU_ctr;
assign ALU_ctr[2] = ((!ALU_op[3])&(!ALU_op[1]))|(!ALU_op[3]& ALU_op[2]& ALU_op[0])|(ALU_op[3]&ALU_op[1]);
assign ALU_ctr[1] = (!ALU_op[3]&!ALU_op[2]&!ALU_op[1])|(ALU_op[3]&!ALU_op[2]&!ALU_op[0])|(ALU_op[2]&ALU_op[1]&!ALU_op[0])|(ALU_op[3]&ALU_op[1]);
assign ALU_ctr[0] = (!ALU_op[2]&!ALU_op[1])|(!ALU_op[3]&ALU_op[2]&ALU_op[0])|(ALU_op[3]&ALU_op[2]&ALU_op[1]);
endmodule
module Adder(A_in,B_in,Cin,Zero,Carry,Overflow,Negative,Output);
input [31:0] A_in,B_in;
output [31:0] Output;
input Cin;
output Zero,Carry,Overflow,Negative;
assign {Carry,Output} = A_in + B_in + Cin;
assign Zero = (Output == 32'b0)? 1'b1 : 1'b0;
assign Overflow = (!(A_in[31]^B_in[31])&(B_in[31]^Output[31]));
assign Negative = Output[31];
endmodule
module MUX8_1_ALU(Sel,S0,S1,S2,S3,S4,S5,S6,S7,ALU_out);
input [2:0] Sel;
input [31:0] S0,S1,S2,S3,S4,S5,S6,S7;
output [31:0]ALU_out;
assign ALU_out = (Sel[2])? (Sel[1]?(Sel[0]?S7:S6) : (Sel[0]?S5:S4)) : (Sel[1]?(Sel[0]?S3:S2) : (Sel[0]?S1:S0));
endmodule
module JudgeBit(NumIn,Num);
input [31:0] NumIn;
output reg[31:0] Num;
integer i = 0;
always@(NumIn)
begin
Num = 32;
for(i = 31;i >= 0;i = i-1)
if(NumIn[i] == 1'b1 && Num == 32)
Num = 31 - i;
end
endmodule
module ALU(
input [31:0] A_in,B_in,
input [3:0] ALU_op,
output Zero,Less,Overflow_out,
output [31:0] ALU_out
);
wire [31:0] AndOut,OrOut,XorOut,NorOut;
wire [31:0] SEX;
wire [31:0] XorOut_Count;
wire Carry,Overflow,Negative;
wire [31:0] Output,Cmp;
wire [31:0] NumBit;
wire Cin;
wire [2:0] ALU_ctr;
ALU_Controller ALU_Con(ALU_op,ALU_ctr);
MUX8_1_ALU MUX(ALU_ctr,NumBit,XorOut,OrOut,NorOut,AndOut,Cmp,SEX,Output,ALU_out);
JudgeBit Judge(XorOut_Count,NumBit);
Adder adder(A_in,B_in^{32{ALU_op[0]}},Cin,Zero,Carry,Overflow,Negative,Output);
//assign NumBit = 32'b0;
assign Cin = ALU_op[0];
assign AndOut = A_in & B_in;
assign OrOut = A_in | B_in;
assign XorOut = A_in ^ B_in;
assign NorOut = !OrOut;
assign SEX = (ALU_op[0])?({{16{B_in[7]}},B_in[15:0]}):({{24{B_in[7]}},B_in[7:0]});
assign XorOut_Count = {32{ALU_op[0]}}^A_in[31:0];
assign Cmp = Less ? 32'hffffffff : 32'b0;
assign Less = ((!ALU_op[3])&ALU_op[2]&ALU_op[1]&ALU_op[0])?(!Carry):(Overflow^Negative);
assign Overflow_out = (ALU_op[1]&ALU_op[2]&ALU_op[3])? Overflow:1'b0;
//Zero is assigned!
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221O_4_V
`define SKY130_FD_SC_HD__A221O_4_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a221o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a221o_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a221o_4 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221O_4_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 4.0
// \ \ Application : MIG
// / / Filename : ddr_axi_mig.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM
// Purpose :
// Top-level module. This module can be instantiated in the
// system and interconnect as shown in user design wrapper file (user top module).
// In addition to the memory controller, the module instantiates:
// 1. Clock generation/distribution, reset logic
// 2. IDELAY control block
// 3. Debug logic
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module ddr_axi_mig #
(
parameter RST_ACT_LOW = 1,
// =1 for active low reset,
// =0 for active high.
//***************************************************************************
// The following parameters refer to width of various ports
//***************************************************************************
parameter BANK_WIDTH = 3,
// # of memory Bank Address bits.
parameter CK_WIDTH = 1,
// # of CK/CK# outputs to memory.
parameter COL_WIDTH = 10,
// # of memory Column Address bits.
parameter CS_WIDTH = 1,
// # of unique CS outputs to memory.
parameter nCS_PER_RANK = 1,
// # of unique CS outputs per rank for phy
parameter CKE_WIDTH = 1,
// # of CKE outputs to memory.
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DQ_CNT_WIDTH = 4,
// = ceil(log2(DQ_WIDTH))
parameter DQ_PER_DM = 8,
parameter DM_WIDTH = 2,
// # of DM (data mask)
parameter DQ_WIDTH = 16,
// # of DQ (data)
parameter DQS_WIDTH = 2,
parameter DQS_CNT_WIDTH = 1,
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8,
// # of DQ per DQS
parameter ECC = "OFF",
parameter DATA_WIDTH = 16,
parameter ECC_TEST = "OFF",
parameter PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
//Possible Parameters
//1.BANK_ROW_COLUMN : Address mapping is
// in form of Bank Row Column.
//2.ROW_BANK_COLUMN : Address mapping is
// in the form of Row Bank Column.
//3.TG_TEST : Scrambles Address bits
// for distributed Addressing.
//parameter nBANK_MACHS = 4,
parameter nBANK_MACHS = 4,
parameter RANKS = 1,
// # of Ranks.
parameter ODT_WIDTH = 1,
// # of ODT outputs to memory.
parameter ROW_WIDTH = 13,
// # of memory Row Address bits.
parameter ADDR_WIDTH = 27,
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
// Chip Select is always tied to low for
// single rank devices
parameter USE_CS_PORT = 1,
// # = 1, When Chip Select (CS#) output is enabled
// = 0, When Chip Select (CS#) output is disabled
// If CS_N disabled, user must connect
// DRAM CS_N input(s) to ground
parameter USE_DM_PORT = 1,
// # = 1, When Data Mask option is enabled
// = 0, When Data Mask option is disbaled
// When Data Mask option is disabled in
// MIG Controller Options page, the logic
// related to Data Mask should not get
// synthesized
parameter USE_ODT_PORT = 1,
// # = 1, When ODT output is enabled
// = 0, When ODT output is disabled
parameter PHY_CONTROL_MASTER_BANK = 0,
// The bank index where master PHY_CONTROL resides,
// equal to the PLL residing bank
parameter MEM_DENSITY = "1Gb",
// Indicates the density of the Memory part
// Added for the sake of Vivado simulations
parameter MEM_SPEEDGRADE = "25E",
// Indicates the Speed grade of Memory Part
// Added for the sake of Vivado simulations
parameter MEM_DEVICE_WIDTH = 16,
// Indicates the device width of the Memory Part
// Added for the sake of Vivado simulations
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter AL = "0",
// DDR3 SDRAM:
// Additive Latency (Mode Register 1).
// # = "0", "CL-1", "CL-2".
// DDR2 SDRAM:
// Additive Latency (Extended Mode Register).
parameter nAL = 0,
// # Additive Latency in number of clock
// cycles.
parameter BURST_MODE = "8",
// DDR3 SDRAM:
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
// DDR2 SDRAM:
// Burst Length (Mode Register).
// # = "8", "4".
parameter BURST_TYPE = "SEQ",
// DDR3 SDRAM: Burst Type (Mode Register 0).
// DDR2 SDRAM: Burst Type (Mode Register).
// # = "SEQ" - (Sequential),
// = "INT" - (Interleaved).
parameter CL = 5,
// in number of clock cycles
// DDR3 SDRAM: CAS Latency (Mode Register 0).
// DDR2 SDRAM: CAS Latency (Mode Register).
parameter OUTPUT_DRV = "HIGH",
// Output Drive Strength (Extended Mode Register).
// # = "HIGH" - FULL,
// = "LOW" - REDUCED.
parameter RTT_NOM = "50",
// RTT (Nominal) (Extended Mode Register).
// = "150" - 150 Ohms,
// = "75" - 75 Ohms,
// = "50" - 50 Ohms.
parameter ADDR_CMD_MODE = "1T" ,
// # = "1T", "2T".
parameter REG_CTRL = "OFF",
// # = "ON" - RDIMMs,
// = "OFF" - Components, SODIMMs, UDIMMs.
//***************************************************************************
// The following parameters are multiplier and divisor factors for PLLE2.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
parameter CLKIN_PERIOD = 4999,
// Input Clock Period
parameter CLKFBOUT_MULT = 6,
// write PLL VCO multiplier
parameter DIVCLK_DIVIDE = 1,
// write PLL VCO divisor
parameter CLKOUT0_PHASE = 0.0,
// Phase for PLL output clock (CLKOUT0)
parameter CLKOUT0_DIVIDE = 2,
// VCO output divisor for PLL output clock (CLKOUT0)
parameter CLKOUT1_DIVIDE = 4,
// VCO output divisor for PLL output clock (CLKOUT1)
parameter CLKOUT2_DIVIDE = 64,
// VCO output divisor for PLL output clock (CLKOUT2)
parameter CLKOUT3_DIVIDE = 8,
// VCO output divisor for PLL output clock (CLKOUT3)
parameter MMCM_VCO = 1200,
// Max Freq (MHz) of MMCM VCO
parameter MMCM_MULT_F = 7,
// write MMCM VCO multiplier
parameter MMCM_DIVCLK_DIVIDE = 1,
// write MMCM VCO divisor
//***************************************************************************
// Memory Timing Parameters. These parameters varies based on the selected
// memory part.
//***************************************************************************
parameter tCKE = 7500,
// memory tCKE paramter in pS
parameter tFAW = 45000,
// memory tRAW paramter in pS.
parameter tPRDI = 1_000_000,
// memory tPRDI paramter in pS.
parameter tRAS = 40000,
// memory tRAS paramter in pS.
parameter tRCD = 15000,
// memory tRCD paramter in pS.
parameter tREFI = 7800000,
// memory tREFI paramter in pS.
parameter tRFC = 127500,
// memory tRFC paramter in pS.
parameter tRP = 12500,
// memory tRP paramter in pS.
parameter tRRD = 10000,
// memory tRRD paramter in pS.
parameter tRTP = 7500,
// memory tRTP paramter in pS.
parameter tWTR = 7500,
// memory tWTR paramter in pS.
parameter tZQI = 128_000_000,
// memory tZQI paramter in nS.
parameter tZQCS = 64,
// memory tZQCS paramter in clock cycles.
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIM_BYPASS_INIT_CAL = "OFF",
// # = "OFF" - Complete memory init &
// calibration sequence
// # = "SKIP" - Not supported
// # = "FAST" - Complete memory init & use
// abbreviated calib sequence
parameter SIMULATION = "FALSE",
// Should be TRUE during design simulations and
// FALSE during implementations
//***************************************************************************
// The following parameters varies based on the pin out entered in MIG GUI.
// Do not change any of these parameters directly by editing the RTL.
// Any changes required should be done through GUI and the design regenerated.
//***************************************************************************
parameter BYTE_LANES_B0 = 4'b1111,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B1 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B2 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B3 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B4 = 4'b0000,
// Byte lanes used in an IO column.
parameter DATA_CTL_B0 = 4'b0101,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B1 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B2 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B3 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B4 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter PHY_0_BITLANES = 48'hFFC_3F7_FFF_3FE,
parameter PHY_1_BITLANES = 48'h000_000_000_000,
parameter PHY_2_BITLANES = 48'h000_000_000_000,
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_03,
parameter ADDR_MAP
= 192'h000_000_000_010_033_01A_019_032_03A_034_018_036_012_011_017_015,
parameter BANK_MAP = 36'h013_016_01B,
parameter CAS_MAP = 12'h039,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_038,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_035,
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_037,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h014,
parameter WE_MAP = 12'h03B,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02_00,
parameter DATA0_MAP = 96'h008_004_009_007_005_001_006_003,
parameter DATA1_MAP = 96'h022_028_020_024_027_025_026_021,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_029_002,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter SLOT_0_CONFIG = 8'b0000_0001,
// Mapping of Ranks.
parameter SLOT_1_CONFIG = 8'b0000_0000,
// Mapping of Ranks.
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter IBUF_LPWR_MODE = "OFF",
// to phy_top
parameter DATA_IO_IDLE_PWRDWN = "OFF",
// # = "ON", "OFF"
parameter BANK_TYPE = "HR_IO",
// # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT",
// # = "HP_LP", "HR_LP", "DEFAULT"
parameter CKE_ODT_AUX = "FALSE",
parameter USER_REFRESH = "OFF",
parameter WRLVL = "OFF",
// # = "ON" - DDR3 SDRAM
// = "OFF" - DDR2 SDRAM.
parameter ORDERING = "STRICT",
// # = "NORM", "STRICT", "RELAXED".
parameter CALIB_ROW_ADD = 16'h0000,
// Calibration row address will be used for
// calibration read and write operations
parameter CALIB_COL_ADD = 12'h000,
// Calibration column address will be used for
// calibration read and write operations
parameter CALIB_BA_ADD = 3'h0,
// Calibration bank address will be used for
// calibration read and write operations
parameter TCQ = 100,
parameter IODELAY_GRP0 = "DDR_AXI_IODELAY_MIG0",
// It is associated to a set of IODELAYs with
// an IDELAYCTRL that have same IODELAY CONTROLLER
// clock frequency (200MHz).
parameter SYSCLK_TYPE = "NO_BUFFER",
// System clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER
parameter REFCLK_TYPE = "USE_SYSTEM_CLOCK",
// Reference clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER, USE_SYSTEM_CLOCK
parameter SYS_RST_PORT = "FALSE",
// "TRUE" - if pin is selected for sys_rst
// and IBUF will be instantiated.
// "FALSE" - if pin is not selected for sys_rst
parameter CMD_PIPE_PLUS1 = "ON",
// add pipeline stage between MC and PHY
parameter DRAM_TYPE = "DDR2",
parameter CAL_WIDTH = "HALF",
parameter STARVE_LIMIT = 2,
// # = 2,3,4.
//***************************************************************************
// Referece clock frequency parameters
//***************************************************************************
parameter REFCLK_FREQ = 200.0,
// IODELAYCTRL reference clock frequency
parameter DIFF_TERM_REFCLK = "TRUE",
// Differential Termination for idelay
// reference clock input pins
//***************************************************************************
// System clock frequency parameters
//***************************************************************************
parameter tCK = 3333,
// memory tCK paramter.
// # = Clock Period in pS.
parameter nCK_PER_CLK = 2,
// # of memory CKs per fabric CLK
parameter DIFF_TERM_SYSCLK = "TRUE",
// Differential Termination for System
// clock input pins
//***************************************************************************
// AXI4 Shim parameters
//***************************************************************************
parameter UI_EXTRA_CLOCKS = "FALSE",
// Generates extra clocks as
// 1/2, 1/4 and 1/8 of fabrick clock.
// Valid for DDR2/DDR3 AXI interfaces
// based on GUI selection
parameter C_S_AXI_ID_WIDTH = 4,
// Width of all master and slave ID signals.
// # = >= 1.
parameter C_S_AXI_MEM_SIZE = "134217728",
// Address Space required for this component
parameter C_S_AXI_ADDR_WIDTH = 32,
// Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and
// M_AXI_ARADDR for all SI/MI slots.
// # = 32.
parameter C_S_AXI_DATA_WIDTH = 32,
// Width of WDATA and RDATA on SI slot.
// Must be <= APP_DATA_WIDTH.
// # = 32, 64, 128, 256.
parameter C_MC_nCK_PER_CLK = 2,
// Indicates whether to instatiate upsizer
// Range: 0, 1
parameter C_S_AXI_SUPPORTS_NARROW_BURST = 0,
// Indicates whether to instatiate upsizer
// Range: 0, 1
parameter C_RD_WR_ARB_ALGORITHM = "RD_PRI_REG",
// Indicates the Arbitration
// Allowed values - "TDM", "ROUND_ROBIN",
// "RD_PRI_REG", "RD_PRI_REG_STARVE_LIMIT"
// "WRITE_PRIORITY", "WRITE_PRIORITY_REG"
parameter C_S_AXI_REG_EN0 = 20'h00000,
// C_S_AXI_REG_EN0[00] = Reserved
// C_S_AXI_REG_EN0[04] = AW CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[05] = W CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[06] = B CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[07] = R CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[08] = AW CHANNEL UPSIZER REGISTER SLICE
// C_S_AXI_REG_EN0[09] = W CHANNEL UPSIZER REGISTER SLICE
// C_S_AXI_REG_EN0[10] = AR CHANNEL UPSIZER REGISTER SLICE
// C_S_AXI_REG_EN0[11] = R CHANNEL UPSIZER REGISTER SLICE
parameter C_S_AXI_REG_EN1 = 20'h00000,
// Instatiates register slices after the upsizer.
// The type of register is specified for each channel
// in a vector. 4 bits per channel are used.
// C_S_AXI_REG_EN1[03:00] = AW CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN1[07:04] = W CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN1[11:08] = B CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN1[15:12] = AR CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN1[20:16] = R CHANNEL REGISTER SLICE
// Possible values for each channel are:
//
// 0 => BYPASS = The channel is just wired through the
// module.
// 1 => FWD = The master VALID and payload signals
// are registrated.
// 2 => REV = The slave ready signal is registrated
// 3 => FWD_REV = Both FWD and REV
// 4 => SLAVE_FWD = All slave side signals and master
// VALID and payload are registrated.
// 5 => SLAVE_RDY = All slave side signals and master
// READY are registrated.
// 6 => INPUTS = Slave and Master side inputs are
// registrated.
// 7 => ADDRESS = Optimized for address channel
parameter C_S_AXI_CTRL_ADDR_WIDTH = 32,
// Width of AXI-4-Lite address bus
parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
// Width of AXI-4-Lite data buses
parameter C_S_AXI_BASEADDR = 32'h0000_0000,
// Base address of AXI4 Memory Mapped bus.
parameter C_ECC_ONOFF_RESET_VALUE = 1,
// Controls ECC on/off value at startup/reset
parameter C_ECC_CE_COUNTER_WIDTH = 8,
// The external memory to controller clock ratio.
//***************************************************************************
// Debug parameters
//***************************************************************************
parameter DEBUG_PORT = "OFF",
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
//***************************************************************************
// Temparature monitor parameter
//***************************************************************************
parameter TEMP_MON_CONTROL = "EXTERNAL"
// # = "INTERNAL", "EXTERNAL"
// parameter RST_ACT_LOW = 1
// =1 for active low reset,
// =0 for active high.
)
(
// Inouts
inout [DQ_WIDTH-1:0] ddr2_dq,
inout [DQS_WIDTH-1:0] ddr2_dqs_n,
inout [DQS_WIDTH-1:0] ddr2_dqs_p,
// Outputs
output [ROW_WIDTH-1:0] ddr2_addr,
output [BANK_WIDTH-1:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [CK_WIDTH-1:0] ddr2_ck_p,
output [CK_WIDTH-1:0] ddr2_ck_n,
output [CKE_WIDTH-1:0] ddr2_cke,
output [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr2_cs_n,
output [DM_WIDTH-1:0] ddr2_dm,
output [ODT_WIDTH-1:0] ddr2_odt,
// Inputs
// Single-ended system clock
input sys_clk_i,
// user interface signals
output ui_clk,
output ui_clk_sync_rst,
output mmcm_locked,
input aresetn,
input app_sr_req,
input app_ref_req,
input app_zq_req,
output app_sr_active,
output app_ref_ack,
output app_zq_ack,
// Slave Interface Write Address Ports
input [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input [0:0] s_axi_awlock,
input [3:0] s_axi_awcache,
input [2:0] s_axi_awprot,
input [3:0] s_axi_awqos,
input s_axi_awvalid,
output s_axi_awready,
// Slave Interface Write Data Ports
input [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
// Slave Interface Write Response Ports
input s_axi_bready,
output [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
// Slave Interface Read Address Ports
input [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input [0:0] s_axi_arlock,
input [3:0] s_axi_arcache,
input [2:0] s_axi_arprot,
input [3:0] s_axi_arqos,
input s_axi_arvalid,
output s_axi_arready,
// Slave Interface Read Data Ports
input s_axi_rready,
output [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
output init_calib_complete,
input [11:0] device_temp_i,
// The 12 MSB bits of the temperature sensor transfer
// function need to be connected to this port. This port
// will be synchronized w.r.t. to fabric clock internally.
// System reset - Default polarity of sys_rst pin is Active Low.
// System reset polarity will change based on the option
// selected in GUI.
input sys_rst
);
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam BM_CNT_WIDTH = clogb2(nBANK_MACHS);
localparam RANK_WIDTH = clogb2(RANKS);
localparam ECC_WIDTH = (ECC == "OFF")?
0 : (DATA_WIDTH <= 4)?
4 : (DATA_WIDTH <= 10)?
5 : (DATA_WIDTH <= 26)?
6 : (DATA_WIDTH <= 57)?
7 : (DATA_WIDTH <= 120)?
8 : (DATA_WIDTH <= 247)?
9 : 10;
localparam DATA_BUF_OFFSET_WIDTH = 1;
localparam MC_ERR_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH)
+ BANK_WIDTH + ROW_WIDTH + COL_WIDTH
+ DATA_BUF_OFFSET_WIDTH;
localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
localparam TEMP_MON_EN = (SIMULATION == "FALSE") ? "ON" : "OFF";
// Enable or disable the temp monitor module
localparam tTEMPSAMPLE = 10000000; // sample every 10 us
localparam XADC_CLK_PERIOD = 5000; // Use 200 MHz IODELAYCTRL clock
localparam TAPSPERKCLK = 56;
// Wire declarations
wire [BM_CNT_WIDTH-1:0] bank_mach_next;
wire clk;
wire [1:0] clk_ref;
wire [1:0] iodelay_ctrl_rdy;
wire clk_ref_in;
wire sys_rst_o;
wire clk_div2;
wire rst_div2;
wire freq_refclk ;
wire mem_refclk ;
wire pll_lock ;
wire sync_pulse;
wire mmcm_ps_clk;
wire poc_sample_pd;
wire psen;
wire psincdec;
wire psdone;
wire iddr_rst;
wire ref_dll_lock;
wire rst_phaser_ref;
wire pll_locked;
wire rst;
wire [(2*nCK_PER_CLK)-1:0] app_ecc_multiple_err;
wire [(2*nCK_PER_CLK)-1:0] app_ecc_single_err;
wire ddr2_reset_n;
wire ddr2_parity;
// AXI CTRL port
wire s_axi_ctrl_awvalid;
wire s_axi_ctrl_awready;
wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr;
// Slave Interface Write Data Ports
wire s_axi_ctrl_wvalid;
wire s_axi_ctrl_wready;
wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata;
// Slave Interface Write Response Ports
wire s_axi_ctrl_bvalid;
wire s_axi_ctrl_bready;
wire [1:0] s_axi_ctrl_bresp;
// Slave Interface Read Address Ports
wire s_axi_ctrl_arvalid;
wire s_axi_ctrl_arready;
wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr;
// Slave Interface Read Data Ports
wire s_axi_ctrl_rvalid;
wire s_axi_ctrl_rready;
wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata;
wire [1:0] s_axi_ctrl_rresp;
// Interrupt output
wire interrupt;
wire sys_clk_p;
wire sys_clk_n;
wire mmcm_clk;
wire clk_ref_p;
wire clk_ref_n;
wire clk_ref_i;
wire [11:0] device_temp;
// Debug port signals
wire dbg_idel_down_all;
wire dbg_idel_down_cpt;
wire dbg_idel_up_all;
wire dbg_idel_up_cpt;
wire dbg_sel_all_idel_cpt;
wire [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt;
wire dbg_sel_pi_incdec;
wire [DQS_CNT_WIDTH:0] dbg_byte_sel;
wire dbg_pi_f_inc;
wire dbg_pi_f_dec;
wire [5:0] dbg_pi_counter_read_val;
wire [8:0] dbg_po_counter_read_val;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_tap_cnt;
wire [(5*DQS_WIDTH*RANKS)-1:0] dbg_dq_idelay_tap_cnt;
wire [255:0] dbg_calib_top;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_first_edge_cnt;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_second_edge_cnt;
wire [(6*RANKS)-1:0] dbg_rd_data_offset;
wire [255:0] dbg_phy_rdlvl;
wire [99:0] dbg_phy_wrcal;
wire [(6*DQS_WIDTH)-1:0] dbg_final_po_fine_tap_cnt;
wire [(3*DQS_WIDTH)-1:0] dbg_final_po_coarse_tap_cnt;
wire [255:0] dbg_phy_wrlvl;
wire [255:0] dbg_phy_init;
wire [255:0] dbg_prbs_rdlvl;
wire [255:0] dbg_dqs_found_cal;
wire dbg_pi_phaselock_start;
wire dbg_pi_phaselocked_done;
wire dbg_pi_phaselock_err;
wire dbg_pi_dqsfound_start;
wire dbg_pi_dqsfound_done;
wire dbg_pi_dqsfound_err;
wire dbg_wrcal_start;
wire dbg_wrcal_done;
wire dbg_wrcal_err;
wire [11:0] dbg_pi_dqs_found_lanes_phy4lanes;
wire [11:0] dbg_pi_phase_locked_phy4lanes;
wire dbg_oclkdelay_calib_start;
wire dbg_oclkdelay_calib_done;
wire [255:0] dbg_phy_oclkdelay_cal;
wire [(DRAM_WIDTH*16)-1:0] dbg_oclkdelay_rd_data;
wire [DQS_WIDTH-1:0] dbg_rd_data_edge_detect;
wire [(2*nCK_PER_CLK*DQ_WIDTH)-1:0] dbg_rddata;
wire dbg_rddata_valid;
wire [1:0] dbg_rdlvl_done;
wire [1:0] dbg_rdlvl_err;
wire [1:0] dbg_rdlvl_start;
wire [(6*DQS_WIDTH)-1:0] dbg_wrlvl_fine_tap_cnt;
wire [(3*DQS_WIDTH)-1:0] dbg_wrlvl_coarse_tap_cnt;
wire [5:0] dbg_tap_cnt_during_wrlvl;
wire dbg_wl_edge_detect_valid;
wire dbg_wrlvl_done;
wire dbg_wrlvl_err;
wire dbg_wrlvl_start;
reg [63:0] dbg_rddata_r;
reg dbg_rddata_valid_r;
wire [53:0] ocal_tap_cnt;
wire [4:0] dbg_dqs;
wire [8:0] dbg_bit;
wire [8:0] rd_data_edge_detect_r;
wire [53:0] wl_po_fine_cnt;
wire [26:0] wl_po_coarse_cnt;
wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_1;
wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_2;
wire [5:0] dbg_data_offset;
wire [5:0] dbg_data_offset_1;
wire [5:0] dbg_data_offset_2;
wire [390:0] ddr2_ila_wrpath_int;
wire [1023:0] ddr2_ila_rdpath_int;
wire [119:0] ddr2_ila_basic_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_final_dqs_tap_cnt_r_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_first_edge_taps_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_second_edge_taps_int;
//***************************************************************************
assign ui_clk = clk;
assign ui_clk_sync_rst = rst;
assign sys_clk_p = 1'b0;
assign sys_clk_n = 1'b0;
assign clk_ref_i = 1'b0;
generate
if (REFCLK_TYPE == "USE_SYSTEM_CLOCK")
assign clk_ref_in = mmcm_clk;
else
assign clk_ref_in = clk_ref_i;
endgenerate
mig_7series_v4_0_iodelay_ctrl #
(
.TCQ (TCQ),
.IODELAY_GRP0 (IODELAY_GRP0),
.REFCLK_TYPE (REFCLK_TYPE),
.SYSCLK_TYPE (SYSCLK_TYPE),
.SYS_RST_PORT (SYS_RST_PORT),
.RST_ACT_LOW (RST_ACT_LOW),
.DIFF_TERM_REFCLK (DIFF_TERM_REFCLK)
)
u_iodelay_ctrl
(
// Outputs
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.sys_rst_o (sys_rst_o),
.clk_ref (clk_ref),
// Inputs
.clk_ref_p (clk_ref_p),
.clk_ref_n (clk_ref_n),
.clk_ref_i (clk_ref_in),
.sys_rst (sys_rst)
);
mig_7series_v4_0_clk_ibuf #
(
.SYSCLK_TYPE (SYSCLK_TYPE),
.DIFF_TERM_SYSCLK (DIFF_TERM_SYSCLK)
)
u_ddr2_clk_ibuf
(
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.sys_clk_i (sys_clk_i),
.mmcm_clk (mmcm_clk)
);
// Temperature monitoring logic
generate
if (TEMP_MON_EN == "ON") begin: temp_mon_enabled
mig_7series_v4_0_tempmon #
(
.TCQ (TCQ),
.TEMP_MON_CONTROL (TEMP_MON_CONTROL),
.XADC_CLK_PERIOD (XADC_CLK_PERIOD),
.tTEMPSAMPLE (tTEMPSAMPLE)
)
u_tempmon
(
.clk (clk),
.xadc_clk (clk_ref[0]),
.rst (rst),
.device_temp_i (device_temp_i),
.device_temp (device_temp)
);
end else begin: temp_mon_disabled
assign device_temp = 'b0;
end
endgenerate
mig_7series_v4_0_infrastructure #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLKIN_PERIOD (CLKIN_PERIOD),
.SYSCLK_TYPE (SYSCLK_TYPE),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKOUT0_PHASE (CLKOUT0_PHASE),
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.MMCM_VCO (MMCM_VCO),
.MMCM_MULT_F (MMCM_MULT_F),
.MMCM_DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE),
.RST_ACT_LOW (RST_ACT_LOW),
.tCK (tCK),
.MEM_TYPE (DRAM_TYPE)
)
u_ddr2_infrastructure
(
// Outputs
.rstdiv0 (rst),
.clk (clk),
.clk_div2 (clk_div2),
.rst_div2 (rst_div2),
.mem_refclk (mem_refclk),
.freq_refclk (freq_refclk),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.psdone (psdone),
.iddr_rst (iddr_rst),
// .auxout_clk (),
.ui_addn_clk_0 (),
.ui_addn_clk_1 (),
.ui_addn_clk_2 (),
.ui_addn_clk_3 (),
.ui_addn_clk_4 (),
.pll_locked (pll_locked),
.mmcm_locked (mmcm_locked),
.rst_phaser_ref (rst_phaser_ref),
// Inputs
.psen (psen),
.psincdec (psincdec),
.mmcm_clk (mmcm_clk),
.sys_rst (sys_rst_o),
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.ref_dll_lock (ref_dll_lock)
);
mig_7series_v4_0_memc_ui_top_axi #
(
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.ECC_TEST (ECC_TEST),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.IODELAY_GRP0 (IODELAY_GRP0),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.CL (CL),
.tCK (tCK),
.tCKE (tCKE),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.USER_REFRESH (USER_REFRESH),
.TEMP_MON_EN (TEMP_MON_EN),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.IDELAY_ADJ ("OFF"),
.FINE_PER_BIT ("OFF"),
.CENTER_COMP_MODE ("OFF"),
.PI_VAL_ADJ ("OFF"),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
.STARVE_LIMIT (STARVE_LIMIT),
.C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_S_AXI_SUPPORTS_NARROW_BURST (C_S_AXI_SUPPORTS_NARROW_BURST),
.C_RD_WR_ARB_ALGORITHM (C_RD_WR_ARB_ALGORITHM),
.C_S_AXI_REG_EN0 (C_S_AXI_REG_EN0),
.C_S_AXI_REG_EN1 (C_S_AXI_REG_EN1),
.C_S_AXI_CTRL_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH),
.C_S_AXI_CTRL_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH),
.C_S_AXI_BASEADDR (C_S_AXI_BASEADDR),
.C_ECC_ONOFF_RESET_VALUE (C_ECC_ONOFF_RESET_VALUE),
.C_ECC_CE_COUNTER_WIDTH (C_ECC_CE_COUNTER_WIDTH),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.MASTER_PHY_CTL (PHY_CONTROL_MASTER_BANK),
.TAPSPERKCLK (TAPSPERKCLK),
.SKIP_CALIB ("FALSE"),
.FPGA_VOLT_TYPE ("N")
)
u_memc_ui_top_axi
(
.clk (clk),
.clk_div2 (clk_div2),
.rst_div2 (rst_div2),
.clk_ref (clk_ref),
.mem_refclk (mem_refclk), //memory clock
.freq_refclk (freq_refclk),
.pll_lock (pll_locked),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.psdone (psdone),
.iddr_rst (iddr_rst),
.psen (psen),
.psincdec (psincdec),
.rst (rst),
.rst_phaser_ref (rst_phaser_ref),
.ref_dll_lock (ref_dll_lock),
// Memory interface ports
.ddr_dq (ddr2_dq),
.ddr_dqs_n (ddr2_dqs_n),
.ddr_dqs (ddr2_dqs_p),
.ddr_addr (ddr2_addr),
.ddr_ba (ddr2_ba),
.ddr_cas_n (ddr2_cas_n),
.ddr_ck_n (ddr2_ck_n),
.ddr_ck (ddr2_ck_p),
.ddr_cke (ddr2_cke),
.ddr_cs_n (ddr2_cs_n),
.ddr_dm (ddr2_dm),
.ddr_odt (ddr2_odt),
.ddr_ras_n (ddr2_ras_n),
.ddr_reset_n (ddr2_reset_n),
.ddr_parity (ddr2_parity),
.ddr_we_n (ddr2_we_n),
.bank_mach_next (bank_mach_next),
// Application interface ports
.app_ecc_multiple_err_o (),
.app_ecc_single_err (),
.device_temp (device_temp),
.calib_tap_req (),
.calib_tap_load (1'b0),
.calib_tap_addr (7'b0),
.calib_tap_val (8'b0),
.calib_tap_load_done (1'b0),
// Debug logic ports
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_rd_data_offset (dbg_rd_data_offset),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rddata_valid (dbg_rddata_valid),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_pi_counter_read_val (dbg_pi_counter_read_val),
.dbg_po_counter_read_val (dbg_po_counter_read_val),
.dbg_prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r_int),
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps_int),
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps_int),
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),
.dbg_pi_phaselock_err (dbg_pi_phaselock_err),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),
.dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),
.dbg_data_offset (dbg_data_offset),
.dbg_data_offset_1 (dbg_data_offset_1),
.dbg_data_offset_2 (dbg_data_offset_2),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_wrcal_err (dbg_wrcal_err),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.aresetn (aresetn),
.app_sr_req (app_sr_req),
.app_sr_active (app_sr_active),
.app_ref_req (app_ref_req),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.app_zq_ack (app_zq_ack),
// Slave Interface Write Address Ports
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awlock (s_axi_awlock),
.s_axi_awcache (s_axi_awcache),
.s_axi_awprot (s_axi_awprot),
.s_axi_awqos (s_axi_awqos),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
// Slave Interface Write Data Ports
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
// Slave Interface Write Response Ports
.s_axi_bid (s_axi_bid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
// Slave Interface Read Address Ports
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arlock (s_axi_arlock),
.s_axi_arcache (s_axi_arcache),
.s_axi_arprot (s_axi_arprot),
.s_axi_arqos (s_axi_arqos),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
// Slave Interface Read Data Ports
.s_axi_rid (s_axi_rid),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rlast (s_axi_rlast),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
// AXI CTRL port
.s_axi_ctrl_awvalid (s_axi_ctrl_awvalid),
.s_axi_ctrl_awready (s_axi_ctrl_awready),
.s_axi_ctrl_awaddr (s_axi_ctrl_awaddr),
// Slave Interface Write Data Ports
.s_axi_ctrl_wvalid (s_axi_ctrl_wvalid),
.s_axi_ctrl_wready (s_axi_ctrl_wready),
.s_axi_ctrl_wdata (s_axi_ctrl_wdata),
// Slave Interface Write Response Ports
.s_axi_ctrl_bvalid (s_axi_ctrl_bvalid),
.s_axi_ctrl_bready (s_axi_ctrl_bready),
.s_axi_ctrl_bresp (s_axi_ctrl_bresp),
// Slave Interface Read Address Ports
.s_axi_ctrl_arvalid (s_axi_ctrl_arvalid),
.s_axi_ctrl_arready (s_axi_ctrl_arready),
.s_axi_ctrl_araddr (s_axi_ctrl_araddr),
// Slave Interface Read Data Ports
.s_axi_ctrl_rvalid (s_axi_ctrl_rvalid),
.s_axi_ctrl_rready (s_axi_ctrl_rready),
.s_axi_ctrl_rdata (s_axi_ctrl_rdata),
.s_axi_ctrl_rresp (s_axi_ctrl_rresp),
// Interrupt output
.interrupt (interrupt),
.init_calib_complete (init_calib_complete),
.dbg_poc (dbg_poc)
);
//*********************************************************************
// Resetting all RTL debug inputs as the debug ports are not enabled
//*********************************************************************
assign dbg_idel_down_all = 1'b0;
assign dbg_idel_down_cpt = 1'b0;
assign dbg_idel_up_all = 1'b0;
assign dbg_idel_up_cpt = 1'b0;
assign dbg_sel_all_idel_cpt = 1'b0;
assign dbg_sel_idel_cpt = 'b0;
assign dbg_byte_sel = 'd0;
assign dbg_sel_pi_incdec = 1'b0;
assign dbg_pi_f_inc = 1'b0;
assign dbg_pi_f_dec = 1'b0;
assign dbg_po_f_inc = 'b0;
assign dbg_po_f_dec = 'b0;
assign dbg_po_f_stg23_sel = 'b0;
assign dbg_sel_po_incdec = 'b0;
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.1
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module sample_iterator_get_offset (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
i_index,
i_sample,
indices_req_din,
indices_req_full_n,
indices_req_write,
indices_rsp_empty_n,
indices_rsp_read,
indices_address,
indices_datain,
indices_dataout,
indices_size,
sample_buffer_size,
sample_length,
ap_return
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 2'b00;
parameter ap_ST_st2_fsm_1 = 2'b1;
parameter ap_ST_st3_fsm_2 = 2'b10;
parameter ap_ST_st4_fsm_3 = 2'b11;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_30 = 32'b110000;
parameter ap_const_lv32_37 = 32'b110111;
parameter ap_const_lv56_0 = 56'b00000000000000000000000000000000000000000000000000000000;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input [15:0] i_index;
input [15:0] i_sample;
output indices_req_din;
input indices_req_full_n;
output indices_req_write;
input indices_rsp_empty_n;
output indices_rsp_read;
output [31:0] indices_address;
input [55:0] indices_datain;
output [55:0] indices_dataout;
output [31:0] indices_size;
input [31:0] sample_buffer_size;
input [15:0] sample_length;
output [31:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg indices_req_write;
reg indices_rsp_read;
reg [1:0] ap_CS_fsm = 2'b00;
wire [31:0] tmp_4_fu_92_p1;
reg [31:0] tmp_4_reg_134;
reg [7:0] indices_stride_load_new_reg_139;
wire [63:0] tmp_fu_81_p1;
wire [15:0] tmp_s_fu_113_p0;
wire [7:0] tmp_s_fu_113_p1;
wire [23:0] tmp_s_fu_113_p2;
wire [31:0] tmp_17_cast_fu_119_p1;
reg [1:0] ap_NS_fsm;
wire [23:0] tmp_s_fu_113_p00;
wire [23:0] tmp_s_fu_113_p10;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st3_fsm_2 == ap_CS_fsm) & ~(indices_rsp_empty_n == ap_const_logic_0))) begin
indices_stride_load_new_reg_139 <= {{indices_datain[ap_const_lv32_37 : ap_const_lv32_30]}};
tmp_4_reg_134 <= tmp_4_fu_92_p1;
end
end
/// ap_done assign process. ///
always @ (ap_start or ap_CS_fsm)
begin
if (((~(ap_const_logic_1 == ap_start) & (ap_ST_st1_fsm_0 == ap_CS_fsm)) | (ap_ST_st4_fsm_3 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_CS_fsm)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st1_fsm_0 == ap_CS_fsm))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st4_fsm_3 == ap_CS_fsm)) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// indices_req_write assign process. ///
always @ (ap_start or ap_CS_fsm)
begin
if (((ap_ST_st1_fsm_0 == ap_CS_fsm) & ~(ap_start == ap_const_logic_0))) begin
indices_req_write = ap_const_logic_1;
end else begin
indices_req_write = ap_const_logic_0;
end
end
/// indices_rsp_read assign process. ///
always @ (ap_CS_fsm or indices_rsp_empty_n)
begin
if (((ap_ST_st3_fsm_2 == ap_CS_fsm) & ~(indices_rsp_empty_n == ap_const_logic_0))) begin
indices_rsp_read = ap_const_logic_1;
end else begin
indices_rsp_read = ap_const_logic_0;
end
end
always @ (ap_start or ap_CS_fsm or indices_rsp_empty_n)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
if (~(ap_start == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
ap_ST_st2_fsm_1 :
ap_NS_fsm = ap_ST_st3_fsm_2;
ap_ST_st3_fsm_2 :
if (~(indices_rsp_empty_n == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end else begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end
ap_ST_st4_fsm_3 :
ap_NS_fsm = ap_ST_st1_fsm_0;
default :
ap_NS_fsm = 'bx;
endcase
end
assign ap_return = (tmp_17_cast_fu_119_p1 + tmp_4_reg_134);
assign indices_address = tmp_fu_81_p1;
assign indices_dataout = ap_const_lv56_0;
assign indices_req_din = ap_const_logic_0;
assign indices_size = ap_const_lv32_1;
assign tmp_17_cast_fu_119_p1 = $unsigned(tmp_s_fu_113_p2);
assign tmp_4_fu_92_p1 = indices_datain[31:0];
assign tmp_fu_81_p1 = $unsigned(i_index);
assign tmp_s_fu_113_p0 = tmp_s_fu_113_p00;
assign tmp_s_fu_113_p00 = $unsigned(i_sample);
assign tmp_s_fu_113_p1 = tmp_s_fu_113_p10;
assign tmp_s_fu_113_p10 = $unsigned(indices_stride_load_new_reg_139);
assign tmp_s_fu_113_p2 = ($signed({{1'b0}, {tmp_s_fu_113_p0}}) * $signed({{1'b0}, {tmp_s_fu_113_p1}}));
endmodule //sample_iterator_get_offset
|
// file: system_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1____25.000______0.000______50.0______312.659____245.713
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________125.000____________0.010
`timescale 1ps/1ps
module system_clk_wiz_0_0_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input resetn,
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_system_clk_wiz_0_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_system_clk_wiz_0_0;
wire clkfbout_buf_system_clk_wiz_0_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (5),
.CLKFBOUT_MULT_F (36.500),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (36.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (8.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_system_clk_wiz_0_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_system_clk_wiz_0_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_system_clk_wiz_0_0),
.CLKIN1 (clk_in1_system_clk_wiz_0_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = ~resetn;
assign locked = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_system_clk_wiz_0_0),
.I (clkfbout_system_clk_wiz_0_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_system_clk_wiz_0_0));
endmodule
|
/*
--------------------------------------------------------------------------
Pegasus - Copyright (C) 2012 Gregory Matthew James.
This file is part of Pegasus.
Pegasus is free; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
Pegasus is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------
*/
/*
--------------------------------------------------------------------------
-- Project Code : pegasus
-- Module Name : peg_l2_mac_pause_cntr
-- Author : mammenx
-- Associated modules:
-- Function : This block is a counter used to generate pause
intervals.
--------------------------------------------------------------------------
*/
`timescale 1ns / 10ps
module peg_l2_mac_pause_cntr #(
parameter BPCLK = 64, //Bits per clock cycle
parameter MAC_SPEED = 100000000 //bps
)
(
input clk,
input rst_n,
//Config
input pause_en,
//Inputs from Parser
input pause_time_valid,
input [15:0] pause_time,
//Pause Status
output pause_valid
);
//----------------------- Global parameters Declarations ------------------
localparam PAUSE_SCALE_FAC = $clog(512 / BPCLK);
localparam CNTR_W = 16 + PAUSE_SCALE_FAC;
//----------------------- Input Declarations ------------------------------
//----------------------- Inout Declarations ------------------------------
//----------------------- Output Declarations -----------------------------
//----------------------- Output Register Declaration ---------------------
//----------------------- Internal Register Declarations ------------------
reg [15:0] pause_time_f;
reg [CNTR_W-1:0] pause_cntr_f;
//----------------------- Internal Wire Declarations ----------------------
//----------------------- Input/Output Registers --------------------------
//----------------------- Start of Code -----------------------------------
always@(posedge clk, negedge rst_n)
begin
if(~rst_n)
begin
pause_time_f <= 0;
pause_cntr_f <= 0;
end
else
begin
//Register the pause time from parser
pause_time_f <= pause_time_valid ? pause_time : pause_time_f;
//Counter logic
if(pause_valid)
begin
pause_cntr_f <= 0;
end
else if(pause_en)
begin
pause_cntr_f <= pause_cntr_f + 1'b1;
end
else
begin
pause_cntr_f <= pause_cntr_f;
end
end
end
//Generate status
assign pause_en = (pause_time_f > pause_cntr_f[CNTR_W-1:PAUSE_SCALE_FAC]) ? 1'b1 : 1'b0;
endmodule // peg_l2_mac_pause_cntr
/*
--------------------------------------------------------------------------
-- <Header>
-- <Log>
[02-07-2014 12:52:58 AM][mammenx] Initial version
[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file
--------------------------------------------------------------------------
*/
|
/*
* @Author: tmh
* @Date: 2017-07-20 15:16:05
* @File Name: RegisterFile.v
*/
`include "define.v"
module RegisterFile (
input clk , // Clock
input rst , // Asynchronous reset active low
input [ 2:0] writeCommand,
input [ 4:0] fileAddr ,
input [`DATA_WIDTH-1:0] writeDataIn ,
input [`DATA_WIDTH-1:0] statusIn ,
input [`IO_A_WIDTH-1:0] portAIn ,
input [`IO_B_WIDTH-1:0] portBIn ,
input [`IO_C_WIDTH-1:0] portCIn ,
input [ `PC_WIDTH-1:0] pcIn ,
output [`DATA_WIDTH-1:0] fsrOut , // First Select Register out
output [`DATA_WIDTH-1:0] regfileOut , // regfile out
output [`DATA_WIDTH-1:0] statusOut , //status out
output [`IO_A_WIDTH-1:0] portAOut ,
output [`IO_B_WIDTH-1:0] portBOut ,
output [`IO_C_WIDTH-1:0] portCOut
);
// Reg
reg[`DATA_WIDTH - 1:0] status;
reg[`DATA_WIDTH - 1:0] FSReg;
reg[`IO_A_WIDTH - 1:0] portA;
reg[`IO_B_WIDTH - 1:0] portB;
reg[`IO_C_WIDTH - 1:0] portC;
reg[`DATA_WIDTH - 1:0] indirect; // not real register
reg[`DATA_WIDTH - 1:0] direct; // not real register
// MEM
reg [`DATA_WIDTH - 1:0] GPR [31:8];
//assign
assign fsrOut = FSReg;
assign regfileOut = (fileAddr == `ADDR_INDF) ? indirect : direct;
assign statusOut = status;
assign portAOut = portA;
assign portBOut = portB;
assign portCOut = portC;
// fsr indirect read
always @(*) begin
case (FSReg[4:0])
`ADDR_INDF: begin
indirect = `DATA_WIDTH'b0;
end
`ADDR_TMR0: begin
indirect = `DATA_WIDTH'b0;
end
`ADDR_PCL: begin
indirect = pcIn[7:0];
end
`ADDR_STATUS: begin
indirect = status;
end
`ADDR_FSR: begin
indirect = FSReg;
end
`ADDR_PORTA: begin
indirect = {4'b0000, portAIn};
end
`ADDR_PORTB: begin
indirect = portBIn;
end
`ADDR_PORTC: begin
indirect = portCIn;
end
5'h08, 5'h09, 5'h0A, 5'h0B, 5'h0C,5'h0D,
5'h0E, 5'h0F, 5'h10, 5'h11, 5'h12, 5'h13,
5'h14,5'h15, 5'h16, 5'h17, 5'h18, 5'h19,
5'h1A, 5'h1B, 5'h1C, 5'h1D, 5'h1E, 5'h1F:begin
indirect = GPR[FSReg[4:0]];
end
default: ;
endcase
end
// fsr direct read
always @(*) begin
case (fileAddr)
`ADDR_INDF: begin
direct = `DATA_WIDTH'bX;
end
`ADDR_TMR0: begin
direct = `DATA_WIDTH'bX;
end
`ADDR_PCL: begin
direct = pcIn[7:0];
end
`ADDR_STATUS: begin
direct = status;
end
`ADDR_FSR: begin
direct = FSReg;
end
`ADDR_PORTA: begin
direct = {4'b0000, portAIn};
end
`ADDR_PORTB: begin
direct = portBIn;
end
`ADDR_PORTC: begin
direct = portCIn;
end
5'h08, 5'h09, 5'h0A, 5'h0B, 5'h0C,5'h0D,
5'h0E, 5'h0F, 5'h10, 5'h11, 5'h12, 5'h13,
5'h14,5'h15, 5'h16, 5'h17, 5'h18, 5'h19,
5'h1A, 5'h1B, 5'h1C, 5'h1D, 5'h1E, 5'h1F: begin
direct = GPR[fileAddr];
end
default: ;
endcase
end
integer index;
// write block
always@(posedge clk) begin
if(!rst) begin
status <= `DATA_WIDTH'b0001_1xxx;
FSReg <= `DATA_WIDTH'b1xxx_xxxx;
portA <= `IO_A_WIDTH'bxxxx;
portB <= `IO_B_WIDTH'bxxxx_xxxx;
portC <= `IO_C_WIDTH'bxxxx_xxxx;
GPR[8] <= `DATA_WIDTH'b0000_0000;
GPR[9] <= `DATA_WIDTH'b0000_0000;
GPR[10] <= `DATA_WIDTH'b0000_0000;
GPR[11] <= `DATA_WIDTH'b0000_0000;
GPR[12] <= `DATA_WIDTH'b0000_0000;
GPR[13] <= `DATA_WIDTH'b0000_0000;
GPR[14] <= `DATA_WIDTH'b0000_0000;
GPR[15] <= `DATA_WIDTH'b0000_0000;
end
else begin
case (writeCommand)
3'b010,3'b011: begin
if(writeCommand == 3'b011) begin
status <= statusIn;
end
case (fileAddr)
`ADDR_INDF: begin
case(FSReg[4:0])
`ADDR_INDF: begin
end
`ADDR_TMR0: begin
end
`ADDR_PCL: begin
end
`ADDR_STATUS: begin
status <= {writeDataIn[7:5],status[4:3],writeDataIn[2:0]};
end
`ADDR_FSR: begin
FSReg <= writeDataIn;
end
`ADDR_PORTA: begin
portA <= writeDataIn[`IO_A_WIDTH - 1:0];
end
`ADDR_PORTB: begin
portB <= writeDataIn;
end
`ADDR_PORTC: begin
portC <= writeDataIn;
end
5'h08, 5'h09, 5'h0A, 5'h0B, 5'h0C,5'h0D,
5'h0E, 5'h0F, 5'h10, 5'h11, 5'h12, 5'h13,
5'h14,5'h15, 5'h16, 5'h17, 5'h18, 5'h19,
5'h1A, 5'h1B, 5'h1C, 5'h1D, 5'h1E, 5'h1F: begin
GPR[FSReg[4:0]] <= writeDataIn;
end
default: ;
endcase
end
`ADDR_TMR0: begin
end
`ADDR_PCL: begin
end
`ADDR_STATUS: begin
status <= {writeDataIn[7:5],status[4:3],writeDataIn[2:0]};
end
`ADDR_FSR: begin
FSReg <= writeDataIn;
end
`ADDR_PORTA: begin
portA <= writeDataIn[`IO_A_WIDTH - 1:0];
end
`ADDR_PORTB: begin
portB <= writeDataIn;
end
`ADDR_PORTC: begin
portC <= writeDataIn;
end
5'h08, 5'h09, 5'h0A, 5'h0B, 5'h0C,5'h0D,
5'h0E, 5'h0F, 5'h10, 5'h11, 5'h12, 5'h13,
5'h14,5'h15, 5'h16, 5'h17, 5'h18, 5'h19,
5'h1A, 5'h1B, 5'h1C, 5'h1D, 5'h1E, 5'h1F: begin
GPR[fileAddr] <= writeDataIn;
end
default : /* default */;
endcase
end
3'b001: begin
status <= statusIn;
end
3'b100: begin
FSReg <= writeDataIn;
end
default : /* default */;
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:50:47 03/17/2011
// Design Name:
// Module Name: contador_a
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/* Contador de 9 bits. Cuenta desde 000h hasta 19Fh.
Toma como entrada la señal de reloj maestro, y su salida más
lenta es de 64us. Cuenta píxeles dentro de una línea */
module clineas(
input wire clk,
output wire [8:0] cnt
);
reg [8:0] contador = 9'b0;
assign cnt = contador;
always @(negedge clk)
contador <= (contador==9'h19f)? 9'b0 : contador+1;
endmodule
/* Contador de 9 bits, cuyo reloj es la salida mas lenta del contador anterior.
Cuenta líneas dentro de un campo. Su salida más lenta es de 50Hz. */
module cframes(
input wire clk,
output wire [8:0] cnt
);
reg [8:0] contador = 9'b0;
assign cnt = contador;
always @(negedge clk)
contador <= (contador==9'h137)? 9'b0 : contador+1;
endmodule
/* El contador maestro consta de los dos contadores anteriores, en cascada (ripple). */
module master_cnt(
input wire clk,
output wire [17:0] cnt
);
wire [8:0] ca;
wire [8:0] cb;
assign cnt = {cb,ca};
clineas cnta (clk, ca);
cframes cntb (ca[8], cb);
endmodule
/* El generador de sincronismos toma algunas de las salidas del contador maestro
para implementar los pulsos de sincronismo de línea y cuadro. */
module gensync(
input wire c5,
input wire c6,
input wire c7,
input wire c8,
input wire c12,
input wire c13,
input wire c14,
input wire c15,
input wire c16,
output wire intr,
output wire sync);
wire line, field;
assign line = ~(c5 | c7) & c6 & c8;
assign field = c12 & c13 & c14 & c15 & c16;
assign sync = ~(line | field);
assign intr = ~field;
endmodule
/* Control del teclado, altavoz, micrófono y señal EAR */
module io(
input wire clk,
input wire en254r,
input wire en254w,
input wire [4:0] kbd,
input wire ear,
input wire d3,
output wire [5:0] dout,
output wire mic,
output wire spk
);
reg ffmic;
reg ffspk;
reg [5:0] ear_y_teclado;
assign dout = (!en254r)? ear_y_teclado : 6'bzzzzzz;
assign mic = ffmic;
assign spk = ffspk;
always @(posedge clk)
ear_y_teclado <= {ear,kbd};
/* El micrófono se activa con el bit D3 en escritura */
always @(posedge clk)
if (!en254w)
ffmic <= d3;
/* Implementación del comportamiento del altavoz. */
always @(posedge clk)
if (!en254r)
ffspk <= 1;
else if (!en254w)
ffspk <= 0;
endmodule
module decodificador(
input wire [15:0] a,
input wire mreq,
input wire iorq,
input wire rd,
input wire wr,
output wire romce,
output wire ramce,
output wire xramce,
output wire vramdec,
output wire en254r,
output wire en254w
);
wire en254;
/* Ecuaciones del 74LS138 */
assign romce = mreq | a[15] | a[14] | a[13] | rd;
assign ramce = mreq | a[15] | a[14] | ~a[13] | ~a[12]; /* modelo básico con 1K de RAM */
assign xramce = mreq | a[15] | ~a[14]; /* ampliación de 16K de user RAM */
assign vramdec = mreq | a[15] | a[14] | ~a[13] | a[12];
assign en254 = iorq | a[0]; /* Decodificación parcial del puerto 254 */
assign en254r = en254 | rd;
assign en254w = en254 | wr;
endmodule
/* Módulo de generación de video y arbitrador de acceso a memoria */
module videogen_and_cpuctrl(
input wire clk,
input wire [15:0] a, /* bus de direcciones CPU */
input wire wr,
input wire vramdec, /* El procesador quiere acceder a la VRAM */
input wire [17:0] cnt, /* Las salidas del contador maestro */
input wire [7:0] DinShiftR, /* Entrada paralelo al registro de desplazamiento. Viene del bus de datos de la RAM de caracteres */
input wire videoinverso, /* Bit 7 leído de la RAM de pantalla. Indica si el caracter debe invertirse o no */
output wire cpuwait, /* Salida WAIT al procesador */
output wire [9:0] ASRAMVideo, /* Al bus de direcciones de la RAM de pantalla */
output wire [2:0] ACRAMVideo, /* Al bus de direcciones de la RAM de caracteres */
output wire sramce, /* Habilitación de la RAM de pantalla */
output wire cramce, /* Habilitación de la RAM de caracteres */
output wire scramoe, /* OE de ambas RAM's: de pantalla y de caracteres */
output wire scramwr, /* WE de ambas RAM's: de pantalla y de caracteres */
output wire video /* Señal de video, sin sincronismos */
);
wire vhold;
wire viden;
wire shld;
reg ffvideoi; /* biestable para guardar el estado de pixel invertido */
reg envramab; /* señal resultante del lío con la resistencia y el diodo */
reg [7:0] shiftreg;
assign viden = ~(cnt[16] & cnt[15]) & (~(cnt[17] | cnt[8]));
assign vhold = ~(a[10] & viden);
assign cpuwait = vhold | vramdec;
/* Esto implementa lo del diodo y la resistencia para el 74LS367 */
always @(posedge clk)
if (vhold)
envramab <= vramdec;
else
envramab <= vramdec | envramab;
assign cramce = ~(a[11] | envramab);
assign sramce = ~(envramab | cramce);
assign scramwr = envramab | wr;
assign scramoe = ~scramwr;
assign ASRAMVideo = {cnt[16:12],cnt[7:3]};
assign ACRAMVideo = cnt[11:9];
always @(posedge clk)
if (&cnt[2:0])
ffvideoi <= (videoinverso & viden);
assign shld = ~(&cnt[2:0] & viden);
/* 74LS166. Registro serializador */
always @(posedge clk)
if (shld)
shiftreg <= shiftreg<<1;
else
shiftreg <= DinShiftR;
/* La señal serializada se pasa por una puerta XOR que la invierte o no */
assign video = (shiftreg[7] ^ ffvideoi);
endmodule
module jace(
input wire clkm,
input wire clk,
output wire cpuclk,
input wire [15:0] a, /* bus de direcciones CPU */
input wire d3,
output wire [5:0] dout, /* bus de datos de la CPU */
input wire wr,
input wire vramdec,
output wire intr,
output wire cpuwait, /* Salida WAIT al procesador */
input wire en254r,
input wire en254w,
output wire sramce, /* Habilitación de la RAM de pantalla */
output wire cramce, /* Habilitación de la RAM de caracteres */
output wire scramoe, /* OE de ambas RAM's: de pantalla y de caracteres */
output wire scramwr, /* WE de ambas RAM's: de pantalla y de caracteres */
input wire [7:0] DinShiftR, /* Entrada paralelo al registro de desplazamiento. Viene del bus de datos de la RAM de caracteres */
input wire videoinverso, /* Bit 7 leído de la RAM de pantalla. Indica si el caracter debe invertirse o no */
output wire [9:0] ASRAMVideo, /* Al bus de direcciones de la RAM de pantalla */
output wire [2:0] ACRAMVideo, /* Al bus de direcciones de la RAM de caracteres */
input wire [4:0] kbd,
input wire ear,
output wire mic,
output wire spk,
output wire sync,
output wire video /* Señal de video, sin sincronismos */
);
wire [17:0] c;
assign cpuclk = c[0];
master_cnt cont (clk, c);
gensync gsync (c[5],c[6],c[7],c[8],c[12],c[13],c[14],c[15],c[16],intr,sync);
io modulo_io (
.clk(clkm),
.en254r(en254r),
.en254w(en254w),
.kbd(kbd),
.ear(ear),
.d3(d3),
.dout(dout),
.mic(mic),
.spk(spk)
);
videogen_and_cpuctrl arbitrador(
.clk(clk),
.a(a), /* bus de direcciones CPU */
.wr(wr),
.vramdec(vramdec), /* El procesador quiere acceder a la VRAM */
.cnt(c), /* Las salidas del contador maestro */
.DinShiftR(DinShiftR), /* Entrada paralelo al registro de desplazamiento. Viene del bus de datos de la RAM de caracteres */
.videoinverso(videoinverso), /* Bit 7 leído de la RAM de pantalla. Indica si el caracter debe invertirse o no */
.cpuwait(cpuwait), /* Salida WAIT al procesador */
.ASRAMVideo(ASRAMVideo), /* Al bus de direcciones de la RAM de pantalla */
.ACRAMVideo(ACRAMVideo), /* Al bus de direcciones de la RAM de caracteres */
.sramce(sramce), /* Habilitación de la RAM de pantalla */
.cramce(cramce), /* Habilitación de la RAM de caracteres */
.scramoe(scramoe), /* OE de ambas RAM's: de pantalla y de caracteres */
.scramwr(scramwr), /* WE de ambas RAM's: de pantalla y de caracteres */
.video(video) /* Señal de video, sin sincronismos */
);
endmodule
|
`define CONFIG_SWITCHES 32'h0
module LX9CoPro32016 (
input fastclk,
// GOP Signals
output[8:1] test,
input [3:0] sw,
// Tube signals
input h_phi2,
input [2:0] h_addr,
inout [7:0] h_data,
input h_rdnw,
input h_cs_b,
input h_rst_b,
output h_irq_b,
// Ram Signals
output reg ram_ub_b,
output reg ram_lb_b,
output reg ram_cs,
output reg ram_oe,
output reg ram_wr,
output reg [18:0] ram_addr,
inout [31:0] ram_data
);
wire clk;
wire nclk;
reg rst_reg;
reg nmi_reg;
reg irq_reg;
wire [2:0] p_addr;
wire p_cs_b;
wire [7:0] p_data_in;
wire [7:0] p_data_out;
wire p_rd_b;
wire p_wr_b;
wire p_rst_b;
wire p_nmi_b;
wire p_irq_b;
wire IO_WR;
wire IO_RD;
wire [31:0] IO_A;
wire [3:0] IO_BE;
wire [31:0] IO_DI;
wire [31:0] IO_Q;
wire IO_READY;
wire ram_enable;
wire rom_enable;
wire tube_enable;
wire config_enable;
reg [31:0] ram_dout;
wire [31:0] rom_dout;
reg bootmode;
reg rd_rdy;
wire [3:0] status;
wire [7:0] statsigs;
ICAP_config inst_ICAP_config (
.fastclk(fastclk),
.sw_in (sw),
.sw_out (),
.h_addr (h_addr),
.h_cs_b (h_cs_b),
.h_data (h_data),
.h_phi2 (h_phi2),
.h_rdnw (h_rdnw),
.h_rst_b(h_rst_b)
);
assign clk = fastclk;
assign nclk = ~fastclk;
M32632 cpu (
// ++++++++++ Basic Signals
.BCLK(clk), // input
.MCLK(~clk), // input
.WRCFG(1'b1), // input
.BRESET(rst_reg), // input
.NMI_N(nmi_reg), // input
.INT_N(irq_reg), // input
.STATUS(status), // output
.ILO(), // output
.STATSIGS(statsigs), // output
// +++++++++ General Purpose Interface
.IO_WR(IO_WR), // output
.IO_RD(IO_RD), // output
.IO_A(IO_A), // output
.IO_BE(IO_BE), // output
.IO_DI(IO_DI), // output
.IO_Q(IO_Q), // input
.IO_READY(IO_READY), // input
// +++++++++ DRAM Interface In
.ENDRAM(1'b0), // input
.IC_MDONE(1'b0), // input
.DC_MDONE(1'b0), // input
.ENWR(1'b0), // input
.WAMUX(1'b0), // input
.WADDR(10'b0), // input
.DRAM_Q(32'b0), // input
.DWCTRL(3'b0), // input
.IWCTRL(3'b0), // input
// +++++++++ DRAM Interface Out
.IC_ACC(),
.IDRAM_ADR(), // output
.DC_ACC(), // output
.DC_WR(), // output
.DRAM_ADR(), // output
.DRAM_DI(), // output
// +++++++++ DMA Interface
.HOLD(1'b1), // input
.HLDA(), // output
.FILLRAM(1'b0), // input
.DMA_AA(24'b0), // input
// ++++++++++ Coprocessor Interface
.COP_GO(), // output
.COP_OP(), // output
.COP_OUT(), // output
.COP_DONE(1'b0), // input
.COP_IN(64'b0) // input
);
assign IO_Q = ram_enable ? ram_dout :
rom_enable ? rom_dout :
tube_enable ? {p_data_out, p_data_out, p_data_out, p_data_out} :
config_enable ? 32'b0 :
32'b0;
// Memory Map during booting
// 000000-FFFFFF ROM (32KB, repeating)
// Memory Map after booting
// 000000-1FFFFF RAM (2MB)
// F00000-F3FFFF ROM (32KB, repeating)
// F90000 Config Switches (A is bit 7, H is bit 0, 1=present)
// A - RSVD; B - RSVD; C - RSVD; D - RSVD;
// E - RSVD; F - RSVD; G - MMU; H - FPU;
// FFFFF0-FFFFFE Tube (even bytes)
assign rom_enable = (IO_RD) & ( bootmode | (IO_A[23:18] == 6'b111100));
assign ram_enable = (IO_RD | IO_WR) & (!bootmode & (IO_A[23:21] == 3'b000));
assign tube_enable = (IO_RD | IO_WR) & (!bootmode & (IO_A[23: 4] == 20'hFFFFF));
assign config_enable = (IO_RD) & (!bootmode & (IO_A[23: 4] == 20'hF9000));
// Internal ROM 8Kx32 bits
tuberom_32016 rom(
.clk(nclk),
.addr(IO_A[14:2]),
.data(rom_dout)
);
// Tube
assign p_data_in = IO_A[1] ? IO_DI[23:16] : IO_DI[7:0];
assign p_cs_b = !tube_enable;
assign p_addr = IO_A[3:1];
assign p_wr_b = !IO_WR;
tube tube_inst(
.h_addr(h_addr),
.h_cs_b(h_cs_b),
.h_data(h_data),
.h_phi2(h_phi2),
.h_rdnw(h_rdnw),
.h_rst_b(h_rst_b),
.h_irq_b(),
.p_addr(p_addr),
.p_cs_b(p_cs_b),
.p_data_in(p_data_in),
.p_data_out(p_data_out),
.p_rdnw(p_wr_b),
.p_phi2(clk),
.p_rst_b(p_rst_b),
.p_nmi_b(p_nmi_b),
.p_irq_b(p_irq_b)
);
always @(posedge clk)
begin
rst_reg <= p_rst_b;
nmi_reg <= p_nmi_b;
irq_reg <= p_irq_b;
if (!rst_reg)
bootmode <= 1'b1;
else if (IO_RD & (IO_A[23:18] == 6'b111100))
bootmode <= 1'b0;
end
assign IO_READY = ram_enable ? ram_rdy : // Ram controlled by state machine
(IO_WR | IO_RD); // Everying else is immediate
// Note, this signal not actually connected to the tube connector on the PCB
assign h_irq_b = 1;
//----------------------------------------------------------------------------
// State Machine machine performing read-modify-write cycles
//----------------------------------------------------------------------------
// External RAM signals
// in spite of the naming, these are all active low
parameter rd_latency = 1; // 0 .. 7, must be odd or m32632 messes up
parameter wr_latency = 1; // 0 .. 7
parameter rmw_rd_latency = 1; // 0 .. 7
parameter rmw_wr_latency = 1; // 0 .. 7
parameter s_idle = 0;
parameter s_read = 1;
parameter s_read_modify_write = 2;
parameter s_write = 3;
parameter s_done = 4;
reg [2:0] state;
reg ram_rdy;
// Latency countdown
reg [2:0] lcount;
// Tri-State-Driver
reg [31:0] wdat;
reg wdat_oe;
assign ram_data = wdat_oe ? wdat : 32'bz;
// Merged data for byte enables writes
wire [31:0] merged_dat = {(IO_BE[3] ? IO_DI[31:24] : ram_data[31:24]),
(IO_BE[2] ? IO_DI[23:16] : ram_data[23:16]),
(IO_BE[1] ? IO_DI[15: 8] : ram_data[15: 8]),
(IO_BE[0] ? IO_DI[ 7: 0] : ram_data[ 7: 0])};
always @(posedge clk) begin
if (~rst_reg) begin
state <= s_idle;
lcount <= 0;
ram_rdy <= 0;
end else begin
case (state)
s_idle: begin
ram_rdy <= 0;
if (ram_enable & IO_RD) begin
ram_cs <= 0;
ram_oe <= 0;
ram_wr <= 1;
ram_addr <= IO_A[20:2];
ram_ub_b <= 0;
ram_lb_b <= 0;
wdat_oe <= 0;
lcount <= rd_latency;
state <= s_read;
end else if (ram_enable & IO_WR & (IO_BE == 4'b1111)) begin
ram_cs <= 0;
ram_oe <= 1;
ram_wr <= 0;
ram_addr <= IO_A[20:2];
ram_ub_b <= 0;
ram_lb_b <= 0;
wdat <= IO_DI;
wdat_oe <= 1;
lcount <= wr_latency;
state <= s_write;
end else if (ram_enable & IO_WR) begin
ram_cs <= 0;
ram_oe <= 0;
ram_wr <= 1;
ram_addr <= IO_A[20:2];
ram_ub_b <= 0;
ram_lb_b <= 0;
wdat_oe <= 0;
lcount <= rmw_rd_latency;
state <= s_read_modify_write;
end else begin
ram_cs <= 1;
ram_oe <= 1;
ram_wr <= 1;
wdat_oe <= 0;
end
end
s_read: begin
if (lcount != 0) begin
lcount <= lcount - 1;
end else begin
ram_cs <= 1;
ram_oe <= 1;
ram_wr <= 1;
ram_dout <= ram_data;
ram_rdy <= 1;
state <= s_done;
end
end
s_read_modify_write: begin
if (lcount != 0) begin
lcount <= lcount - 1;
end else begin
ram_cs <= 0;
ram_oe <= 1;
ram_wr <= 0;
ram_addr <= IO_A[20:2];
ram_ub_b <= 0;
ram_lb_b <= 0;
wdat <= merged_dat;
wdat_oe <= 1;
lcount <= rmw_wr_latency;
state <= s_write;
end
end
s_write: begin
if (lcount != 0) begin
lcount <= lcount - 1;
end else begin
ram_cs <= 1;
ram_oe <= 1;
ram_wr <= 1;
ram_rdy <= 1; // XXX We could acknoledge write XXX
state <= s_done; // XXX requests 1 cycle ahead XXX
end
end
s_done: begin
ram_rdy <= 0;
state <= s_idle;
end
endcase
end
end
//----------------------------------------------------------------------------
// Test outputs
//----------------------------------------------------------------------------
// default to hi-impedence, to avoid conflicts with
// a Raspberry Pi connected to the test connector
assign test = 8'bZ;
//----------------------------------------------------------------------------
// Test setups for debugging
//----------------------------------------------------------------------------
// // For Udo's CPU Test Program
// assign rom_enable = (IO_RD) & (IO_A[23:13] == 11'b00000000000);
// assign ram_enable = (IO_RD | IO_WR) & (IO_A[23:13] != 11'b00000000000);
// assign tube_enable = 0;
// assign config_enable = 0;
// wire [7:0] trig;
// wire fetchc;
// wire fetchd;
// assign fetchc = IO_RD & (status == 4'b1000);
// assign fetchd = IO_RD & (status == 4'b1010);
// assign trig[5] = fetchc & (IO_A[23:0] == 24'h000000);
// assign trig[4] = fetchc & (IO_A[23:0] == 24'h000A60);
// assign trig[3] = fetchc & (IO_A[23:0] == 24'h001C70);
// assign trig[2] = fetchc & (IO_A[23:0] == 24'h001CA8);
// assign trig[1] = fetchc & (IO_A[23:0] == 24'h001CA9);
// assign trig[0] = fetchc & (IO_A[23:0] == 24'h001CB8);
// assign test = sw[3] ? {rst_reg, fetchc, IO_A[17:12]} :
// sw[2] ? {rst_reg, fetchc, IO_A[11:6]} :
// sw[1] ? {rst_reg, fetchc, IO_A[5:0]} :
// sw[0] ? {rst_reg, fetchc, trig[5:0]} :
// {p_irq_b, p_nmi_b, bootmode, IO_RD, IO_WR, ram_enable, rom_enable, tube_enable};
// assign test = sw[3] ? {rst_reg, fetchc, fetchd, bootmode, status} :
// sw[2] ? {rst_reg, fetchc, fetchd, IO_A[14:10]} :
// sw[1] ? {rst_reg, ram_enable, IO_RD, IO_WR, ram_cs, ram_oe, ram_wr, ram_rdy} :
// sw[0] ? {rst_reg, tube_enable, p_cs_b, p_wr_b, p_data_in[3:0]} :
// {p_irq_b, p_nmi_b, bootmode, IO_RD, IO_WR, ram_enable, rom_enable, tube_enable};
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_data_decoder(
ck,
reset_n,
code,
pattern
);
parameter DATA_WIDTH = "";
parameter AFI_RATIO = "";
input ck;
input reset_n;
input [3:0] code;
output [2 * DATA_WIDTH * AFI_RATIO - 1 : 0] pattern;
reg [3:0] code_R;
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
code_R <= 4'b0000;
end
else begin
code_R <= code;
end
end
genvar j;
generate
for(j = 0; j < DATA_WIDTH; j = j + 1)
begin : bit_pattern
if(j % 2 == 0) begin
assign pattern[j] = code_R[3];
assign pattern[j + DATA_WIDTH] = code_R[2];
if (AFI_RATIO == 2) begin
assign pattern[j + 2 * DATA_WIDTH] = code_R[3] ^ code_R[1];
assign pattern[j + 3 * DATA_WIDTH] = code_R[2] ^ code_R[1];
end else if (AFI_RATIO == 4) begin
assign pattern[j + 2 * DATA_WIDTH] = code_R[3] ^ code_R[1];
assign pattern[j + 3 * DATA_WIDTH] = code_R[2] ^ code_R[1];
assign pattern[j + 4 * DATA_WIDTH] = code_R[3];
assign pattern[j + 5 * DATA_WIDTH] = code_R[2];
assign pattern[j + 6 * DATA_WIDTH] = code_R[3] ^ code_R[1];
assign pattern[j + 7 * DATA_WIDTH] = code_R[2] ^ code_R[1];
end
end
else begin
assign pattern[j] = code_R[3] ^ code_R[0];
assign pattern[j + DATA_WIDTH] = code_R[2] ^ code_R[0];
if (AFI_RATIO == 2) begin
assign pattern[j + 2 * DATA_WIDTH] = code_R[3] ^ code_R[1] ^ code_R[0];
assign pattern[j + 3 * DATA_WIDTH] = code_R[2] ^ code_R[1] ^ code_R[0];
end else if (AFI_RATIO == 4) begin
assign pattern[j + 2 * DATA_WIDTH] = code_R[3] ^ code_R[1] ^ code_R[0];
assign pattern[j + 3 * DATA_WIDTH] = code_R[2] ^ code_R[1] ^ code_R[0];
assign pattern[j + 4 * DATA_WIDTH] = code_R[3] ^ code_R[0];
assign pattern[j + 5 * DATA_WIDTH] = code_R[2] ^ code_R[0];
assign pattern[j + 6 * DATA_WIDTH] = code_R[3] ^ code_R[1] ^ code_R[0];
assign pattern[j + 7 * DATA_WIDTH] = code_R[2] ^ code_R[1] ^ code_R[0];
end
end
end
endgenerate
endmodule
|
/* Copyright (C) 2015-2016 by John Cronin
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module cpu(clk, rst_, addr, data, dbg, cs_, oe_, we_, cpu_int, cpu_int_ack);
input clk;
input rst_;
inout [7:0] data;
output [31:0] addr;
output [31:0] dbg;
output we_;
output cs_;
output oe_;
input cpu_int;
output cpu_int_ack;
// uses around 75% of CycloneII with REGS 16, ~50% with REGS 6 */
parameter REGS = 16; // Total number of registers (also change REGS_MAX_BIT if changing this)
parameter REGS_MAX_BIT = 3; // Number of bits to encode registers minus one
// 2 = 8 registers
// 3 = 16 registers
// 4 = 32 registers
parameter PC = 0;
parameter LIT_REG = 1;
parameter SP_REG = 7;
localparam CUR_INST = REGS;
`ifdef USE_DBG
reg [31:0] dbg = 31'd0;
`else
assign dbg = 31'd0;
`endif
reg [31:0] addr = 31'd0;
wire [7:0] data;
reg we_ = 1;
reg cs_ = 1;
reg oe_ = 1;
reg cpu_int_ack = 0;
reg [32:0] r[0:REGS];
reg [7:0] state = 8'd0;
reg [2:0] memory_state = 3'd0;
reg [2:0] bytes_to_xmit = 3'd0;
reg [1:0] reg_part = 2'd0;
reg [4:0] mem_reg = 5'd0;
reg [7:0] next_state = 8'd0;
reg [7:0] data_out = 8'd0;
reg [31:0] srca = 32'd0;
reg [31:0] srcb = 32'd0;
reg [31:0] srcab = 32'd0;
reg [31:0] srcbcond = 32'd0;
reg [31:0] srcabcond = 32'd0;
reg [31:0] irpt_val = 32'd0;
reg ab_is_imm = 1'b0;
reg abcond_is_imm = 1'b0;
reg [4:0] dest_idx = 5'd0;
reg [32:0] cond_reg = 33'd0;
integer i;
assign data = we_ ? 8'bZ : data_out;
//`define DEBUG
`ifdef DEBUG
wire start_inst;
assign start_inst = state == 8'd0;
wire [3:0] opcode = r[CUR_INST][29:26];
wire [3:0] cond_code = r[CUR_INST][25:22];
wire [4:0] dest_idx_w = r[CUR_INST][21:17];
wire [4:0] cond_reg_idx = r[CUR_INST][16:12];
wire [5:0] srcb_idx = r[CUR_INST][11:6];
wire [5:0] srca_idx = r[CUR_INST][5:0];
wire [32:0] dest_reg_dbg = r[dest_idx_w];
wire [32:0] cond_reg_dbg = r[cond_reg_idx];
wire [32:0] srca_reg_dbg = r[srca_idx[4:0]];
wire [32:0] srcb_reg_dbg = r[srcb_idx[4:0]];
`endif
`ifndef USE_RST_LOGIC
initial
for(i = 0; i <= REGS; i=i+1) r[i] = 33'd0;
`endif
//`define COALESCE_REG_WRITES
`ifdef COALESCE_REG_WRITES
`define DEST_REG r[dest_idx]
`define POST_PROC_STATE 8'd0
`else
reg [32:0] dreg = 33'd0;
`define DEST_REG dreg
`define POST_PROC_STATE 8'd7
`endif
always @(posedge clk)
`ifdef USE_RST_LOGIC
if(~rst_)
begin
we_ = 1;
cs_ = 1;
oe_ = 1;
for(i = 0; i <= REGS; i=i+1) r[i] = 33'd0;
`ifdef USE_DBG
dbg = 32'hffffffff;
`endif
srca = 32'd0;
srcb = 32'd0;
srcab = 32'd0;
srcbcond = 32'd0;
srcabcond = 32'd0;
cond_reg = 33'd0;
dest_idx = 5'd0;
ab_is_imm = 1'b0;
abcond_is_imm = 1'b0;
state = 8'hf0; // introduce a delay post reset
end
else
`endif
casez (state)
8'd0: // start of instruction - read 4x bytes to instruction buffer from PC, store to CUR_INST
if(cpu_int)
{ state, irpt_val, cpu_int_ack } <= { 8'd8, 32'd0, 1'b0 };
else
{ state, memory_state, bytes_to_xmit, mem_reg, addr, reg_part, next_state, cpu_int_ack } <= { 8'd1, 3'd1, 3'd4, CUR_INST[4:0], r[PC][31:0], 2'd0, 8'd3, 1'b0 };
8'd1: // memory read to mem_reg
case(memory_state)
3'd0: // zero destination (in case of reads < 4 bytes - skipped by PC reads)
{ memory_state, r[mem_reg] } <= { 3'd1, 33'd0 };
3'd1: // set cs, oe
{ memory_state, cs_, oe_ } <= { 3'd2, 1'b0, 1'b0 };
3'd2: // pause for cselect circuitry to work
{ memory_state } <= { 3'd3 };
3'd3: // pause for memory chips to respond
{ memory_state } <= { 3'd4 };
3'd4: // pause 2 for memory chips to respond
{ memory_state } <= { 3'd5 };
3'd5: // read memory, increment addr, decrement bytes_to_xmit, clear cs, oe, increment reg_part
case(reg_part)
2'd0:
{ memory_state, r[mem_reg][7:0], addr, bytes_to_xmit, cs_, oe_, reg_part } <= { 3'd6, data, addr + 32'd1, bytes_to_xmit - 3'd1, 1'b1, 1'b1, reg_part + 2'd1 };
2'd1:
{ memory_state, r[mem_reg][15:8], addr, bytes_to_xmit, cs_, oe_, reg_part } <= { 3'd6, data, addr + 32'd1, bytes_to_xmit - 3'd1, 1'b1, 1'b1, reg_part + 2'd1 };
2'd2:
{ memory_state, r[mem_reg][23:16], addr, bytes_to_xmit, cs_, oe_, reg_part } <= { 3'd6, data, addr + 32'd1, bytes_to_xmit - 3'd1, 1'b1, 1'b1, reg_part + 2'd1 };
2'd3: // clear carry bit in this step
{ memory_state, r[mem_reg][32], r[mem_reg][31:24], addr, bytes_to_xmit, cs_, oe_, reg_part } <= { 3'd6, 1'b0, data, addr + 32'd1, bytes_to_xmit - 3'd1, 1'b1, 1'b1, reg_part + 2'd1 };
endcase
3'd6: // loop to next byte if required (this could be included in previous state, but is done here for simplicity)
if(|bytes_to_xmit)
{ memory_state } <= { 3'd1 }; // skip clearing destination
else
{ state } <= { next_state };
endcase
8'd2: // memory write from mem_reg
case(memory_state)
3'd0: // set data, we (in preparation for cs next step - so addr and data are valid before cs is set)
case(reg_part)
2'd0:
{ memory_state, data_out, we_, reg_part, bytes_to_xmit } <= { 3'd1, srca[7:0], 1'b0, reg_part + 2'd1, bytes_to_xmit - 3'd1 };
2'd1:
{ memory_state, data_out, we_, reg_part, bytes_to_xmit } <= { 3'd1, srca[15:8], 1'b0, reg_part + 2'd1, bytes_to_xmit - 3'd1 };
2'd2:
{ memory_state, data_out, we_, reg_part, bytes_to_xmit } <= { 3'd1, srca[23:16], 1'b0, reg_part + 2'd1, bytes_to_xmit - 3'd1 };
2'd3:
{ memory_state, data_out, we_, reg_part, bytes_to_xmit } <= { 3'd1, srca[31:24], 1'b0, reg_part + 2'd1, bytes_to_xmit - 3'd1 };
endcase
3'd1: // set cs
{ memory_state, cs_ } <= { 3'd2, 1'b0 };
3'd2: // pause 1
memory_state <= 3'd3;
3'd3: // pause 2
memory_state <= 3'd4;
3'd4: // assume write has completed, clear cs, we, increment addr
{ memory_state, cs_, we_, addr } <= { 3'd5, 1'b1, 1'b1, addr + 32'd1 };
3'd5: // loop to next byte if required (this could be included in previous state, but is done here for simplicity)
if(|bytes_to_xmit)
{ memory_state } <= { 3'd0 };
else
{ state } <= { next_state };
endcase
8'd3: // decode inst type, handle literal instructions, increment pc
case(r[CUR_INST][31:30])
2'b00: { state, r[PC][31:0], dest_idx } <= { 8'd4, r[PC][31:0] + 32'd4, r[CUR_INST][21:17] };
2'b01: { state, r[PC][31:0], r[r[CUR_INST][29:25]] } <= { 8'd0, r[PC][31:0] + 32'd4, 8'b0, r[CUR_INST][24:0] };
default: { state, r[PC][31:0], r[LIT_REG] } <= { 8'd0, r[PC][31:0] + 32'd4, 2'b0, r[CUR_INST][30:0] };
endcase
8'd4: // source reg decode
begin
if(r[CUR_INST][5]) // is srca an immediate
begin
if(r[CUR_INST][4]) // is it negative?
srca <= { 28'hfffffff, r[CUR_INST][3:0] };
else
srca <= { 28'h0, r[CUR_INST][3:0] };
end
else
srca <= r[r[CUR_INST][0 + REGS_MAX_BIT:0]][31:0];
if(r[CUR_INST][11]) // is srcb an immediate?
begin
if(r[CUR_INST][10]) // is it negative?
{ srcb, srcab, ab_is_imm } <= { 28'hfffffff, r[CUR_INST][9:6], 22'h3fffff, r[CUR_INST][9:0], 1'b1 };
else
{ srcb, srcab, ab_is_imm } <= { 28'h0, r[CUR_INST][9:6], 22'h0, r[CUR_INST][9:0], 1'b1 };
end
else
{ srcb, srcab, ab_is_imm } <= { r[r[CUR_INST][6 + REGS_MAX_BIT:6]][31:0], r[r[CUR_INST][0 + REGS_MAX_BIT:0]][31:0], 1'b0 };
if(r[CUR_INST][16]) // is condreg an immediate?
begin
if(r[CUR_INST][15]) // is it negative?
{ srcbcond, srcabcond, abcond_is_imm } <= { 23'h7fffff, r[CUR_INST][14:6], 17'h1ffff, r[CUR_INST][14:0], 1'b1 };
else
{ srcbcond, srcabcond, abcond_is_imm } <= { 23'h0, r[CUR_INST][14:6], 17'h0, r[CUR_INST][14:0], 1'b1 };
end
else
{ srcbcond, srcabcond, abcond_is_imm } <= { r[r[CUR_INST][6 + REGS_MAX_BIT:6]][31:0], r[r[CUR_INST][0 + REGS_MAX_BIT:0]][31:0], 1'b0 };
cond_reg <= r[r[CUR_INST][12 + REGS_MAX_BIT:12]];
state <= 8'd5;
end
8'd5: // cond decode
case(r[CUR_INST][25:22])
4'd0: // Never
state <= 8'd0;
4'd1: // Equals (zero)
state <= (~|cond_reg[31:0]) ? 8'd6 : 8'd0;
4'd2: // Not equals (not zero)
state <= (|cond_reg[31:0]) ? 8'd6 : 8'd0;
4'd3: // Positive (sign bit zero, not zero)
state <= ((~cond_reg[31]) & (|cond_reg[31:0])) ? 8'd6 : 8'd0;
4'd4: // Negative (sign bit one)
state <= cond_reg[31] ? 8'd6 : 8'd0;
4'd5: // Positive or equal (sign bit zero)
state <= (~cond_reg[31]) ? 8'd6 : 8'd0;
4'd6: // Negative or equal (sign bit one or zero)
state <= (cond_reg[31] | (~|cond_reg[31:0])) ? 8'd6 : 8'd0;
4'd7: // Signed overflow TODO
state <= 8'd0;
4'd8: // Not signed overflow TODO
state <= 8'd0;
4'd9: // Unsigned overflow
state <= cond_reg[31] ? 8'd6 : 8'd0;
4'd10: // Not unsigned overflow
state <= ~cond_reg[31] ? 8'd6 : 8'd0;
4'd15: // Always - srcb/srcab expands into condreg
{ state, srcb, srcab, ab_is_imm } <= { 8'd6, srcbcond, srcabcond, abcond_is_imm };
default:
state <= 8'd0;
endcase
8'd6: // instruction decode and execute
case(r[CUR_INST][29:26])
4'd0: // LOAD
{ state, memory_state, bytes_to_xmit, mem_reg, addr, reg_part, next_state } <= { 8'd1, 3'd0, srcb[2:0], dest_idx[4:0], srca, 2'd0, 8'd0 };
4'd1: // STORE
{ state, memory_state, bytes_to_xmit, addr, reg_part, next_state } <= { 8'd2, 3'd0, srcb[2:0], r[dest_idx][31:0], 2'd0, 8'd0 };
4'd2: // MOVE
if(~|dest_idx)
if(ab_is_imm) // immediate move to PC is an add instruction
begin
state <= `POST_PROC_STATE;
`DEST_REG[31:0] <= r[PC][31:0] + srcab;
`DEST_REG[32] <= 1'b0;
end
else // register move to PC is standard move
begin
state <= `POST_PROC_STATE;
`DEST_REG[31:0] <= srcab;
`DEST_REG[32] <= 1'b0;
end
else // all else is also standard move
begin
state <= `POST_PROC_STATE;
`DEST_REG[31:0] <= srcab;
`DEST_REG[32] <= 1'b0;
end
4'd3: // ADD
begin
state <= `POST_PROC_STATE;
`DEST_REG <= srca + srcb;
end
4'd4: // SUB
begin
state <= `POST_PROC_STATE;
`DEST_REG <= srca - srcb;
end
4'd5: // SEXT
case(srcb[2:0])
2'd1:
begin
state <= `POST_PROC_STATE;
`DEST_REG[32:0] <= { srca[7] ? 25'h1ffffff : 25'h0, srca[7:0] };
end
2'd2:
begin
state <= `POST_PROC_STATE;
`DEST_REG[32:0] <= { srca[15] ? 17'h1ffff : 17'h0, srca[15:0] };
end
default:
begin
state <= `POST_PROC_STATE;
`DEST_REG[32:0] <= { 1'b0, srca[31:0] };
end
endcase
4'd6: // MUL
begin
state <= `POST_PROC_STATE;
`DEST_REG <= srca * srcb;
end
4'd7: // IRET = pop PC (load SP, 4 -> PC; add SP, 4 -> SP;)
{ state, memory_state, bytes_to_xmit, mem_reg, addr, reg_part, next_state } <= { 8'd1, 3'd1, 3'd4, PC[4:0], r[SP_REG][31:0], 2'd0, 8'd13 };
4'd8: // NOT
{ state, `DEST_REG } <= { `POST_PROC_STATE, 1'b0, ~srca };
4'd9: // AND
begin
state <= `POST_PROC_STATE;
`DEST_REG[31:0] <= srca & srcb;
`DEST_REG[32] <= 1'b0;
end
4'd10: // OR
begin
state <= `POST_PROC_STATE;
`DEST_REG[31:0] <= srca | srcb;
`DEST_REG[32] <= 1'b0;
end
4'd11: // XOR
begin
state <= `POST_PROC_STATE;
`DEST_REG[31:0] <= srca ^ srcb;
`DEST_REG[32] <= 1'b0;
end
4'd12: // XNOR
begin
state <= `POST_PROC_STATE;
`DEST_REG[31:0] <= srca ~^ srcb;
`DEST_REG[32] <= 1'b0;
end
4'd13: // LSH
begin
state <= `POST_PROC_STATE;
`DEST_REG[31:0] <= srca << srcb[4:0];
`DEST_REG[32] <= 1'b0;
end
4'd14: // RSH
begin
state <= `POST_PROC_STATE;
`DEST_REG[31:0] <= srcb[31] ? (srca >>> srcb[4:0]) : (srca >> srcb[4:0]);
`DEST_REG[32] <= 1'b0;
end
`ifdef USE_DBG
4'd15: // DBG
{ state, dbg } <= { 8'd0, srca };
`else
4'd15: // DBG - if not enabled, treat as NOP
state <= 8'd0;
`endif
default: // signal unknown opcode exception
{ state, irpt_val } <= { 8'd8, 32'h80000000 };
endcase
`ifndef COALESCE_REG_WRITES
8'd7: // move dreg to actual destination if coalesced register assignment is off
{ state, r[dest_idx] } <= { 8'd0, dreg };
`endif
8'd8: // interrupt. sub SP, 4 -> SP
{ state, r[SP_REG], cpu_int_ack } <= { 8'd9, r[SP_REG] - 33'd4, 1'b1 };
8'd9: // store PC -> SP
{ state, memory_state, bytes_to_xmit, addr, reg_part, next_state, srca } <= { 8'd2, 3'd1, 3'd4, r[SP_REG][31:0], 2'd0, 8'd10, r[PC][31:0] };
8'd10: // sub SP, 4 -> SP
{ state, r[SP_REG] } <= { 8'd11, r[SP_REG] - 33'd4 };
8'd11: // store irpt_val -> SP
{ state, memory_state, bytes_to_xmit, addr, reg_part, next_state, srca } <= { 8'd2, 3'd1, 3'd4, r[SP_REG][31:0], 2'd0, 8'd12, irpt_val };
8'd12: // load 4 -> PC
{ state, memory_state, bytes_to_xmit, mem_reg, addr, reg_part, next_state } <= { 8'd1, 3'd1, 3'd4, PC[4:0], 32'd4, 2'd0, 8'd0 };
8'd13: // part of IRET: add SP, 4 -> SP
{ state, r[SP_REG] } <= { 8'd0, r[SP_REG] + 33'd4 };
8'hf?: // delay states before returning to 0
{ state, cpu_int_ack } <= { state + 8'd1, 1'b0 };
default: { state } <= { 8'd0 };
endcase
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BO_FUNCTIONAL_V
`define SKY130_FD_SC_LP__A21BO_FUNCTIONAL_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a21bo (
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire nand0_out ;
wire nand1_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X, B1_N, nand0_out);
buf buf0 (X , nand1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BO_FUNCTIONAL_V |
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's VR, UPR and Configuration Registers ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// According to OR1K architectural and OR1200 specifications. ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_cfgr.v,v $
// Revision 1.1 2008/05/07 22:43:21 daughtry
// Initial Demo RTL check-in
//
// Revision 1.4 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.3 2002/03/29 15:16:54 lampret
// Some of the warnings fixed.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:21 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_cfgr(
// RISC Internal Interface
spr_addr, spr_dat_o
);
//
// RISC Internal Interface
//
input [31:0] spr_addr; // SPR Address
output [31:0] spr_dat_o; // SPR Read Data
//
// Internal wires & registers
//
reg [31:0] spr_dat_o; // SPR Read Data
`ifdef OR1200_CFGR_IMPLEMENTED
//
// Implementation of VR, UPR and configuration registers
//
always @(spr_addr)
`ifdef OR1200_SYS_FULL_DECODE
if (~|spr_addr[31:4])
`endif
case(spr_addr[3:0]) // synopsys parallel_case
`OR1200_SPRGRP_SYS_VR: begin
spr_dat_o[`OR1200_VR_REV_BITS] = `OR1200_VR_REV;
spr_dat_o[`OR1200_VR_RES1_BITS] = `OR1200_VR_RES1;
spr_dat_o[`OR1200_VR_CFG_BITS] = `OR1200_VR_CFG;
spr_dat_o[`OR1200_VR_VER_BITS] = `OR1200_VR_VER;
end
`OR1200_SPRGRP_SYS_UPR: begin
spr_dat_o[`OR1200_UPR_UP_BITS] = `OR1200_UPR_UP;
spr_dat_o[`OR1200_UPR_DCP_BITS] = `OR1200_UPR_DCP;
spr_dat_o[`OR1200_UPR_ICP_BITS] = `OR1200_UPR_ICP;
spr_dat_o[`OR1200_UPR_DMP_BITS] = `OR1200_UPR_DMP;
spr_dat_o[`OR1200_UPR_IMP_BITS] = `OR1200_UPR_IMP;
spr_dat_o[`OR1200_UPR_MP_BITS] = `OR1200_UPR_MP;
spr_dat_o[`OR1200_UPR_DUP_BITS] = `OR1200_UPR_DUP;
spr_dat_o[`OR1200_UPR_PCUP_BITS] = `OR1200_UPR_PCUP;
spr_dat_o[`OR1200_UPR_PMP_BITS] = `OR1200_UPR_PMP;
spr_dat_o[`OR1200_UPR_PICP_BITS] = `OR1200_UPR_PICP;
spr_dat_o[`OR1200_UPR_TTP_BITS] = `OR1200_UPR_TTP;
spr_dat_o[`OR1200_UPR_RES1_BITS] = `OR1200_UPR_RES1;
spr_dat_o[`OR1200_UPR_CUP_BITS] = `OR1200_UPR_CUP;
end
`OR1200_SPRGRP_SYS_CPUCFGR: begin
spr_dat_o[`OR1200_CPUCFGR_NSGF_BITS] = `OR1200_CPUCFGR_NSGF;
spr_dat_o[`OR1200_CPUCFGR_HGF_BITS] = `OR1200_CPUCFGR_HGF;
spr_dat_o[`OR1200_CPUCFGR_OB32S_BITS] = `OR1200_CPUCFGR_OB32S;
spr_dat_o[`OR1200_CPUCFGR_OB64S_BITS] = `OR1200_CPUCFGR_OB64S;
spr_dat_o[`OR1200_CPUCFGR_OF32S_BITS] = `OR1200_CPUCFGR_OF32S;
spr_dat_o[`OR1200_CPUCFGR_OF64S_BITS] = `OR1200_CPUCFGR_OF64S;
spr_dat_o[`OR1200_CPUCFGR_OV64S_BITS] = `OR1200_CPUCFGR_OV64S;
spr_dat_o[`OR1200_CPUCFGR_RES1_BITS] = `OR1200_CPUCFGR_RES1;
end
`OR1200_SPRGRP_SYS_DMMUCFGR: begin
spr_dat_o[`OR1200_DMMUCFGR_NTW_BITS] = `OR1200_DMMUCFGR_NTW;
spr_dat_o[`OR1200_DMMUCFGR_NTS_BITS] = `OR1200_DMMUCFGR_NTS;
spr_dat_o[`OR1200_DMMUCFGR_NAE_BITS] = `OR1200_DMMUCFGR_NAE;
spr_dat_o[`OR1200_DMMUCFGR_CRI_BITS] = `OR1200_DMMUCFGR_CRI;
spr_dat_o[`OR1200_DMMUCFGR_PRI_BITS] = `OR1200_DMMUCFGR_PRI;
spr_dat_o[`OR1200_DMMUCFGR_TEIRI_BITS] = `OR1200_DMMUCFGR_TEIRI;
spr_dat_o[`OR1200_DMMUCFGR_HTR_BITS] = `OR1200_DMMUCFGR_HTR;
spr_dat_o[`OR1200_DMMUCFGR_RES1_BITS] = `OR1200_DMMUCFGR_RES1;
end
`OR1200_SPRGRP_SYS_IMMUCFGR: begin
spr_dat_o[`OR1200_IMMUCFGR_NTW_BITS] = `OR1200_IMMUCFGR_NTW;
spr_dat_o[`OR1200_IMMUCFGR_NTS_BITS] = `OR1200_IMMUCFGR_NTS;
spr_dat_o[`OR1200_IMMUCFGR_NAE_BITS] = `OR1200_IMMUCFGR_NAE;
spr_dat_o[`OR1200_IMMUCFGR_CRI_BITS] = `OR1200_IMMUCFGR_CRI;
spr_dat_o[`OR1200_IMMUCFGR_PRI_BITS] = `OR1200_IMMUCFGR_PRI;
spr_dat_o[`OR1200_IMMUCFGR_TEIRI_BITS] = `OR1200_IMMUCFGR_TEIRI;
spr_dat_o[`OR1200_IMMUCFGR_HTR_BITS] = `OR1200_IMMUCFGR_HTR;
spr_dat_o[`OR1200_IMMUCFGR_RES1_BITS] = `OR1200_IMMUCFGR_RES1;
end
`OR1200_SPRGRP_SYS_DCCFGR: begin
spr_dat_o[`OR1200_DCCFGR_NCW_BITS] = `OR1200_DCCFGR_NCW;
spr_dat_o[`OR1200_DCCFGR_NCS_BITS] = `OR1200_DCCFGR_NCS;
spr_dat_o[`OR1200_DCCFGR_CBS_BITS] = `OR1200_DCCFGR_CBS;
spr_dat_o[`OR1200_DCCFGR_CWS_BITS] = `OR1200_DCCFGR_CWS;
spr_dat_o[`OR1200_DCCFGR_CCRI_BITS] = `OR1200_DCCFGR_CCRI;
spr_dat_o[`OR1200_DCCFGR_CBIRI_BITS] = `OR1200_DCCFGR_CBIRI;
spr_dat_o[`OR1200_DCCFGR_CBPRI_BITS] = `OR1200_DCCFGR_CBPRI;
spr_dat_o[`OR1200_DCCFGR_CBLRI_BITS] = `OR1200_DCCFGR_CBLRI;
spr_dat_o[`OR1200_DCCFGR_CBFRI_BITS] = `OR1200_DCCFGR_CBFRI;
spr_dat_o[`OR1200_DCCFGR_CBWBRI_BITS] = `OR1200_DCCFGR_CBWBRI;
spr_dat_o[`OR1200_DCCFGR_RES1_BITS] = `OR1200_DCCFGR_RES1;
end
`OR1200_SPRGRP_SYS_ICCFGR: begin
spr_dat_o[`OR1200_ICCFGR_NCW_BITS] = `OR1200_ICCFGR_NCW;
spr_dat_o[`OR1200_ICCFGR_NCS_BITS] = `OR1200_ICCFGR_NCS;
spr_dat_o[`OR1200_ICCFGR_CBS_BITS] = `OR1200_ICCFGR_CBS;
spr_dat_o[`OR1200_ICCFGR_CWS_BITS] = `OR1200_ICCFGR_CWS;
spr_dat_o[`OR1200_ICCFGR_CCRI_BITS] = `OR1200_ICCFGR_CCRI;
spr_dat_o[`OR1200_ICCFGR_CBIRI_BITS] = `OR1200_ICCFGR_CBIRI;
spr_dat_o[`OR1200_ICCFGR_CBPRI_BITS] = `OR1200_ICCFGR_CBPRI;
spr_dat_o[`OR1200_ICCFGR_CBLRI_BITS] = `OR1200_ICCFGR_CBLRI;
spr_dat_o[`OR1200_ICCFGR_CBFRI_BITS] = `OR1200_ICCFGR_CBFRI;
spr_dat_o[`OR1200_ICCFGR_CBWBRI_BITS] = `OR1200_ICCFGR_CBWBRI;
spr_dat_o[`OR1200_ICCFGR_RES1_BITS] = `OR1200_ICCFGR_RES1;
end
`OR1200_SPRGRP_SYS_DCFGR: begin
spr_dat_o[`OR1200_DCFGR_NDP_BITS] = `OR1200_DCFGR_NDP;
spr_dat_o[`OR1200_DCFGR_WPCI_BITS] = `OR1200_DCFGR_WPCI;
spr_dat_o[`OR1200_DCFGR_RES1_BITS] = `OR1200_DCFGR_RES1;
end
default: spr_dat_o = 32'h0000_0000;
endcase
`ifdef OR1200_SYS_FULL_DECODE
else
spr_dat_o = 32'h0000_0000;
`endif
`else
//
// When configuration registers are not implemented, only
// implement VR and UPR
//
always @(spr_addr)
`ifdef OR1200_SYS_FULL_DECODE
if (!spr_addr[31:4])
`endif
case(spr_addr[3:0])
`OR1200_SPRGRP_SYS_VR: begin
spr_dat_o[`OR1200_VR_REV_BITS] = `OR1200_VR_REV;
spr_dat_o[`OR1200_VR_RES1_BITS] = `OR1200_VR_RES1;
spr_dat_o[`OR1200_VR_CFG_BITS] = `OR1200_VR_CFG;
spr_dat_o[`OR1200_VR_VER_BITS] = `OR1200_VR_VER;
end
`OR1200_SPRGRP_SYS_UPR: begin
spr_dat_o[`OR1200_UPR_UP_BITS] = `OR1200_UPR_UP;
spr_dat_o[`OR1200_UPR_DCP_BITS] = `OR1200_UPR_DCP;
spr_dat_o[`OR1200_UPR_ICP_BITS] = `OR1200_UPR_ICP;
spr_dat_o[`OR1200_UPR_DMP_BITS] = `OR1200_UPR_DMP;
spr_dat_o[`OR1200_UPR_IMP_BITS] = `OR1200_UPR_IMP;
spr_dat_o[`OR1200_UPR_MP_BITS] = `OR1200_UPR_MP;
spr_dat_o[`OR1200_UPR_DUP_BITS] = `OR1200_UPR_DUP;
spr_dat_o[`OR1200_UPR_PCUP_BITS] = `OR1200_UPR_PCUP;
spr_dat_o[`OR1200_UPR_PMP_BITS] = `OR1200_UPR_PMP;
spr_dat_o[`OR1200_UPR_PICP_BITS] = `OR1200_UPR_PICP;
spr_dat_o[`OR1200_UPR_TTP_BITS] = `OR1200_UPR_TTP;
spr_dat_o[`OR1200_UPR_RES1_BITS] = `OR1200_UPR_RES1;
spr_dat_o[`OR1200_UPR_CUP_BITS] = `OR1200_UPR_CUP;
end
default: spr_dat_o = 32'h0000_0000;
endcase
`ifdef OR1200_SYS_FULL_DECODE
else
spr_dat_o = 32'h0000_0000;
`endif
`endif
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:28:50 05/03/2008
// Design Name: ecsmul
// Module Name: tb1.v
// Project Name: smul_sca
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: ecsmul
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb1_v;
// Inputs
reg clk;
reg nrst;
reg [31:0]key;
// Outputs
wire [232:0] sx;
wire [232:0] sy;
wire done;
// Instantiate the Unit Under Test (UUT)
ecsmul uut (
.clk(clk),
.nrst(nrst),
.key(key),
.sx(sx),
.sy(sy),
.done(done)
);
initial begin
// Initialize Inputs
clk = 0;
key = 32'hFFFF0000; // B9B9B9B9;
nrst = 1'b1;
// Wait 100 ns for global reset to finish
#200;
// Add stimulus here
#10 nrst = 1'b0;
#110 nrst = 1'b1;
end
initial begin
$dumpfile ("dump.vcd");
$dumpvars;
$dumpon;
#100000 $dumpoff;
end
always begin
#100 clk =~clk;
end
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module fast_spi_rx
#(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter IDENTYFIER = 4'b0001
)(
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
input wire SCLK,
input wire SDI,
input wire SEN,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #( .BASEADDR(BASEADDR), .HIGHADDR(HIGHADDR), .ABUSWIDTH(ABUSWIDTH) ) i_bus_to_ip
(
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
fast_spi_rx_core
#(
.ABUSWIDTH(ABUSWIDTH),
.IDENTYFIER(IDENTYFIER)
) i_fast_spi_rx_core
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.SCLK(SCLK),
.SDI(SDI),
.SEN(SEN),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA)
);
endmodule
|
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* WATCHDOG TIMER */
/*---------------------------------------------------------------------------*/
/* Test the Watdog timer: */
/* - Interval timer mode. */
/* */
/* Author(s): */
/* - Olivier Girard, [email protected] */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
`define LONG_TIMEOUT
integer dco_clk_cnt;
always @(negedge dco_clk)
dco_clk_cnt <= dco_clk_cnt+1;
integer mclk_cnt;
always @(negedge mclk)
mclk_cnt <= mclk_cnt+1;
integer smclk_cnt;
always @(negedge smclk)
smclk_cnt <= smclk_cnt+1;
integer aclk_cnt;
`ifdef ASIC_CLOCKING
always @(negedge aclk)
aclk_cnt <= aclk_cnt+1;
`else
always @(negedge lfxt_clk)
aclk_cnt <= aclk_cnt+1;
`endif
integer inst_cnt;
always @(inst_number)
inst_cnt <= inst_cnt+1;
reg watchdog_clock;
`ifdef ASIC_CLOCKING
`ifdef WATCHDOG_MUX
always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;
`else
`ifdef WATCHDOG_NOMUX_ACLK
always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;
`else
always @(posedge dco_clk or negedge dco_clk) watchdog_clock <= dco_clk;
`endif
`endif
`else
always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;
`endif
integer watchdog_clock_cnt;
always @(posedge watchdog_clock)
watchdog_clock_cnt <= watchdog_clock_cnt+1;
always @(posedge dut.wdt_irq)
watchdog_clock_cnt = 1'b0;
integer ii;
integer jj;
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
repeat(5) @(posedge mclk);
stimulus_done = 0;
ii = 0;
jj = 0;
`ifdef WATCHDOG
// WATCHDOG TEST: INTERVAL MODE /64
//--------------------------------------------------------
@(r15==16'h1000);
`ifdef ASIC_CLOCKING
`ifdef WATCHDOG_MUX
`ifdef ACLK_DIVIDER
repeat(5) @(posedge watchdog_clock);
`else
repeat(4) @(posedge watchdog_clock);
`endif
`else
`ifdef WATCHDOG_NOMUX_ACLK
`ifdef ACLK_DIVIDER
repeat(6) @(posedge watchdog_clock);
`else
repeat(5) @(posedge watchdog_clock);
`endif
`else
repeat(21) @(posedge watchdog_clock);
`endif
`endif
`endif
for ( ii=0; ii < 9; ii=ii+1)
begin
repeat(1) @(posedge watchdog_clock);
jj = 1;
dco_clk_cnt = 0;
mclk_cnt = 0;
smclk_cnt = 0;
aclk_cnt = 0;
inst_cnt = 0;
`ifdef ASIC_CLOCKING
`ifdef WATCHDOG_MUX
repeat(62) @(posedge watchdog_clock);
jj = 2;
if (dco_clk_cnt !== 0) tb_error("====== DCO_CLK is running (CONFIG 1) =====");
if (mclk_cnt !== 0) tb_error("====== MCLK is running (CONFIG 1) =====");
if (smclk_cnt !== 0) tb_error("====== SMCLK is running (CONFIG 1) =====");
if (aclk_cnt !== 62) tb_error("====== ACLK is not running (CONFIG 1) =====");
if (inst_cnt !== 0) tb_error("====== CPU is executing (CONFIG 1) =====");
if (r6 !== ii) tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 1) =====");
repeat(1) @(posedge watchdog_clock);
jj = 3;
if (r6 !== ii+1) tb_error("====== WATCHDOG interrupt was not taken (CONFIG 1) =====");
`else
`ifdef WATCHDOG_NOMUX_ACLK
repeat(62) @(posedge watchdog_clock);
jj = 2;
if (dco_clk_cnt !== 0) tb_error("====== DCO_CLK is running (CONFIG 2) =====");
if (mclk_cnt !== 0) tb_error("====== MCLK is running (CONFIG 2) =====");
if (smclk_cnt !== 0) tb_error("====== SMCLK is running (CONFIG 2) =====");
if (aclk_cnt !== 62) tb_error("====== ACLK is not running (CONFIG 2) =====");
if (inst_cnt !== 0) tb_error("====== CPU is executing (CONFIG 2) =====");
if (r6 !== ii) tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 2) =====");
repeat(1) @(posedge watchdog_clock);
jj = 3;
if (r6 !== ii+1) tb_error("====== WATCHDOG interrupt was not taken (CONFIG 2) =====");
`else
repeat(39) @(posedge watchdog_clock);
jj = 2;
if (dco_clk_cnt !== 39) tb_error("====== DCO_CLK is not running (CONFIG 3) =====");
if (mclk_cnt !== 0) tb_error("====== MCLK is running (CONFIG 3) =====");
if (smclk_cnt !== 39) tb_error("====== SMCLK is not running (CONFIG 3) =====");
if (aclk_cnt === 0) tb_error("====== ACLK is not running (CONFIG 3) =====");
if (inst_cnt !== 0) tb_error("====== CPU is executing (CONFIG 3) =====");
if (r6 !== ii) tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 3) =====");
repeat(24) @(posedge watchdog_clock);
jj = 3;
if (r6 !== ii+1) tb_error("====== WATCHDOG interrupt was not taken (CONFIG 3) =====");
`endif
`endif
`else
repeat(62) @(posedge watchdog_clock);
jj = 2;
if (dco_clk_cnt < 1800) tb_error("====== DCO_CLK is not running (CONFIG 4) =====");
if (mclk_cnt < 1800) tb_error("====== MCLK is not running (CONFIG 4) =====");
if (smclk_cnt < 1800) tb_error("====== SMCLK is not running (CONFIG 4) =====");
if (aclk_cnt !== 62) tb_error("====== ACLK is not running (CONFIG 4) =====");
if (inst_cnt !== 0) tb_error("====== CPU is executing (CONFIG 4) =====");
if (r6 !== ii) tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 4) =====");
repeat(1) @(posedge watchdog_clock);
jj = 3;
if (r6 !== ii+1) tb_error("====== WATCHDOG interrupt was not taken (CONFIG 4) =====");
`endif
end
// WATCHDOG TEST: RESET MODE /64
//--------------------------------------------------------
@(r15==16'h5000);
if (r7 !== 16'h0000) tb_error("====== WATCHDOG reset was not taken =====");
`else
tb_skip_finish("| (the Watchdog is not included) |");
`endif
stimulus_done = 1;
end
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1P_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__INPUTISO1P_FUNCTIONAL_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__inputiso1p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Name Output Other arguments
or or0 (X , A, SLEEP );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1P_FUNCTIONAL_V |
///////////////////////////////////////////////////////////////////////////////
// Title : alt_mem_ddrx_mm_st_converter
//
// File : alt_mem_ddrx_mm_st_converter.v
//
// Abstract : take in Avalon MM interface and convert it to single cmd and
// multiple data Avalon ST
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_mem_ddrx_mm_st_converter # (
parameter
AVL_SIZE_WIDTH = 3,
AVL_ADDR_WIDTH = 25,
AVL_DATA_WIDTH = 32,
LOCAL_ID_WIDTH = 8,
CFG_DWIDTH_RATIO = 4,
CFG_MM_ST_CONV_REG = 0
)
(
ctl_clk, // controller clock
ctl_reset_n, // controller reset_n, synchronous to ctl_clk
ctl_half_clk, // controller clock, half-rate
ctl_half_clk_reset_n, // controller reset_n, synchronous to ctl_half_clk
// Avalon data slave interface
avl_ready, // Avalon wait_n
avl_read_req, // Avalon read
avl_write_req, // Avalon write
avl_size, // Avalon burstcount
avl_burstbegin, // Avalon burstbegin
avl_addr, // Avalon address
avl_rdata_valid, // Avalon readdata_valid
avl_rdata, // Avalon readdata
avl_wdata, // Avalon writedata
avl_be, // Avalon byteenble
local_rdata_error, // Avalon readdata_error
local_multicast, // In-band multicast
local_autopch_req, // In-band auto-precharge request signal
local_priority, // In-band priority signal
// cmd channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
// write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id
);
localparam AVL_BE_WIDTH = AVL_DATA_WIDTH / 8;
input ctl_clk;
input ctl_reset_n;
input ctl_half_clk;
input ctl_half_clk_reset_n;
output avl_ready;
input avl_read_req;
input avl_write_req;
input [AVL_SIZE_WIDTH-1:0] avl_size;
input avl_burstbegin;
input [AVL_ADDR_WIDTH-1:0] avl_addr;
output avl_rdata_valid;
output [3:0] local_rdata_error;
output [AVL_DATA_WIDTH-1:0] avl_rdata;
input [AVL_DATA_WIDTH-1:0] avl_wdata;
input [AVL_BE_WIDTH-1:0] avl_be;
input local_multicast;
input local_autopch_req;
input local_priority;
input itf_cmd_ready;
output itf_cmd_valid;
output itf_cmd;
output [AVL_ADDR_WIDTH-1:0] itf_cmd_address;
output [AVL_SIZE_WIDTH-1:0] itf_cmd_burstlen;
output [LOCAL_ID_WIDTH-1:0] itf_cmd_id;
output itf_cmd_priority;
output itf_cmd_autopercharge;
output itf_cmd_multicast;
input itf_wr_data_ready;
output itf_wr_data_valid;
output [AVL_DATA_WIDTH-1:0] itf_wr_data;
output [AVL_BE_WIDTH-1:0] itf_wr_data_byte_en;
output itf_wr_data_begin;
output itf_wr_data_last;
output [LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
output itf_rd_data_ready;
input itf_rd_data_valid;
input [AVL_DATA_WIDTH-1:0] itf_rd_data;
input itf_rd_data_error;
input itf_rd_data_begin;
input itf_rd_data_last;
input [LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
reg [AVL_SIZE_WIDTH-1:0] burst_count;
wire int_ready;
wire itf_cmd; // high is write
wire itf_wr_if_ready;
wire [LOCAL_ID_WIDTH-1:0] itf_cmd_id;
wire itf_wr_data_begin;
wire itf_wr_data_last;
wire [LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
reg data_pass;
reg [AVL_SIZE_WIDTH-1:0] burst_counter;
reg avl_read_req_reg;
reg avl_write_req_reg;
reg [AVL_SIZE_WIDTH-1:0] avl_size_reg;
reg avl_burstbegin_reg;
reg [AVL_ADDR_WIDTH-1:0] avl_addr_reg;
reg [AVL_DATA_WIDTH-1:0] avl_wdata_reg;
reg [AVL_DATA_WIDTH/8-1:0] avl_be_reg;
reg itf_rd_data_valid_reg;
reg [AVL_DATA_WIDTH-1:0] itf_rd_data_reg;
reg [3:0] itf_rd_data_error_reg;
reg local_multicast_reg;
reg local_autopch_req_reg;
reg local_priority_reg;
generate
if (CFG_MM_ST_CONV_REG == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
avl_read_req_reg <= 1'b0;
avl_write_req_reg <= 1'b0;
avl_size_reg <= {AVL_SIZE_WIDTH{1'b0}};
avl_burstbegin_reg <= 1'b0;
avl_addr_reg <= {AVL_ADDR_WIDTH{1'b0}};
avl_wdata_reg <= {AVL_DATA_WIDTH{1'b0}};
avl_be_reg <= {AVL_BE_WIDTH{1'b0}};
itf_rd_data_valid_reg <= 1'b0;
itf_rd_data_reg <= {AVL_DATA_WIDTH{1'b0}};
itf_rd_data_error_reg <= 4'b0;
local_multicast_reg <= 1'b0;
local_autopch_req_reg <= 1'b0;
local_priority_reg <= 1'b0;
end else
begin
if (int_ready)
begin
avl_read_req_reg <= avl_read_req;
avl_write_req_reg <= avl_write_req;
avl_size_reg <= avl_size;
avl_burstbegin_reg <= avl_burstbegin;
avl_addr_reg <= avl_addr;
avl_wdata_reg <= avl_wdata;
avl_be_reg <= avl_be;
local_multicast_reg <= local_multicast;
local_autopch_req_reg <= local_autopch_req;
local_priority_reg <= local_priority;
end
itf_rd_data_valid_reg <= itf_rd_data_valid;
itf_rd_data_reg <= itf_rd_data;
itf_rd_data_error_reg <= itf_rd_data_error;
end
end
end else
begin
always @ (*)
begin
avl_read_req_reg = avl_read_req;
avl_write_req_reg = avl_write_req;
avl_size_reg = avl_size;
avl_burstbegin_reg = avl_burstbegin;
avl_addr_reg = avl_addr;
avl_wdata_reg = avl_wdata;
avl_be_reg = avl_be;
itf_rd_data_valid_reg = itf_rd_data_valid;
itf_rd_data_reg = itf_rd_data;
itf_rd_data_error_reg = {4{itf_rd_data_error}};
local_multicast_reg = local_multicast;
local_autopch_req_reg = local_autopch_req;
local_priority_reg = local_priority;
end
end
endgenerate
// when cmd_ready = 1'b1, avl_ready = 1'b1;
// when avl_write_req = 1'b1,
// take this write req and then then drive avl_ready until receive # of beats = avl_size?
// we will look at cmd_ready, if cmd_ready = 1'b0, avl_ready = 1'b0
// when cmd_ready = 1'b1, avl_ready = 1'b1;
// when local_ready_req = 1'b1,
// take this read_req
// we will look at cmd_ready, if cmd_ready = 1'b0, avl_ready = 1'b0
assign itf_cmd_valid = avl_read_req_reg | itf_wr_if_ready;
assign itf_wr_if_ready = itf_wr_data_ready & avl_write_req_reg & ~data_pass;
assign avl_ready = int_ready;
assign itf_rd_data_ready = 1'b1;
assign itf_cmd_address = avl_addr_reg ;
assign itf_cmd_burstlen = avl_size_reg ;
assign itf_cmd_autopercharge = local_autopch_req_reg ;
assign itf_cmd_priority = local_priority_reg ;
assign itf_cmd_multicast = local_multicast_reg ;
assign itf_cmd = avl_write_req_reg;
assign itf_cmd_id = {LOCAL_ID_WIDTH{1'b0}};
assign itf_wr_data_begin = 1'b0;
assign itf_wr_data_last = 1'b0;
assign itf_wr_data_id = {LOCAL_ID_WIDTH{1'b0}};
// write data channel
assign itf_wr_data_valid = (data_pass) ? avl_write_req_reg : itf_cmd_ready & avl_write_req_reg;
assign itf_wr_data = avl_wdata_reg ;
assign itf_wr_data_byte_en = avl_be_reg ;
// read data channel
assign avl_rdata_valid = itf_rd_data_valid_reg;
assign avl_rdata = itf_rd_data_reg;
assign local_rdata_error = itf_rd_data_error_reg;
assign int_ready = (data_pass) ? itf_wr_data_ready : ((itf_cmd) ? (itf_wr_data_ready & itf_cmd_ready) : itf_cmd_ready);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
burst_counter <= {AVL_SIZE_WIDTH{1'b0}};
else
begin
if (itf_wr_if_ready && avl_size_reg > 1 && itf_cmd_ready)
burst_counter <= avl_size_reg - 1'b1;
else if (avl_write_req_reg && itf_wr_data_ready)
burst_counter <= burst_counter - 1'b1;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
data_pass <= 1'b0;
else
begin
if (itf_wr_if_ready && avl_size_reg > 1 && itf_cmd_ready)
data_pass <= 1'b1;
else if (burst_counter == 1 && avl_write_req_reg && itf_wr_data_ready)
data_pass <= 1'b0;
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_pipe_clock.v
// Version : 1.3
//------------------------------------------------------------------------------
// Filename : pipe_clock.v
// Description : PIPE Clock Module for 7 Series Transceiver
// Version : 11.0
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Clock Module -------------------------------------------------
module pcie_7x_v1_3_pipe_clock #
(
parameter PCIE_USE_MODE = "1.1", // PCIe use mode
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_LANE = 1, // PCIe number of lanes
parameter PCIE_LINK_SPEED = 2, // PCIe link speed
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
parameter PCIE_USERCLK1_FREQ = 2, // PCIe user clock 1 frequency
parameter PCIE_USERCLK2_FREQ = 2, // PCIe user clock 2 frequency
parameter PCIE_DEBUG_MODE = 0 // PCIe Debug mode
)
(
//---------- Input -------------------------------------
input CLK_CLK,
input CLK_TXOUTCLK,
input [PCIE_LANE-1:0] CLK_RXOUTCLK_IN,
input CLK_RST_N,
input [PCIE_LANE-1:0] CLK_PCLK_SEL,
input CLK_GEN3,
//---------- Output ------------------------------------
output CLK_PCLK,
output CLK_RXUSRCLK,
output [PCIE_LANE-1:0] CLK_RXOUTCLK_OUT,
output CLK_DCLK,
output CLK_USERCLK1,
output CLK_USERCLK2,
output CLK_MMCM_LOCK
);
//---------- Select Clock Divider ----------------------
localparam DIVCLK_DIVIDE = (PCIE_REFCLK_FREQ == 2) ? 2 :
(PCIE_REFCLK_FREQ == 1) ? 1 : 1;
localparam CLKFBOUT_MULT_F = (PCIE_REFCLK_FREQ == 2) ? 8 :
(PCIE_REFCLK_FREQ == 1) ? 8 : 10;
localparam CLKOUT0_DIVIDE_F = 8;
localparam CLKOUT1_DIVIDE = 4;
localparam CLKIN1_PERIOD = (PCIE_REFCLK_FREQ == 2) ? 4 :
(PCIE_REFCLK_FREQ == 1) ? 8 : 10;
localparam CLKOUT2_DIVIDE = (PCIE_USERCLK1_FREQ == 5) ? 2 :
(PCIE_USERCLK1_FREQ == 4) ? 4 :
(PCIE_USERCLK1_FREQ == 3) ? 8 :
(PCIE_USERCLK1_FREQ == 1) ? 32 : 16;
localparam CLKOUT3_DIVIDE = (PCIE_USERCLK2_FREQ == 5) ? 2 :
(PCIE_USERCLK2_FREQ == 4) ? 4 :
(PCIE_USERCLK2_FREQ == 3) ? 8 :
(PCIE_USERCLK2_FREQ == 1) ? 32 : 16;
//---------- Select Reference Clock --------------------
localparam REFCLK_SEL = ((PCIE_TXBUF_EN == "TRUE") && (PCIE_LINK_SPEED != 3)) ? 1'd1 : 1'd0;
//---------- Input Registers ---------------------------
reg [PCIE_LANE-1:0] pclk_sel_reg1 = {PCIE_LANE{1'd0}};
reg gen3_reg1 = 1'd0;
reg [PCIE_LANE-1:0] pclk_sel_reg2 = {PCIE_LANE{1'd0}};
reg gen3_reg2 = 1'd0;
//---------- Internal Signals --------------------------
wire refclk;
wire mmcm_fb;
wire clk_125mhz;
wire clk_250mhz;
wire userclk1;
wire userclk2;
reg pclk_sel = 1'd0;
//---------- Output Registers --------------------------
wire pclk_1;
wire pclk;
wire userclk1_1;
wire userclk2_1;
wire mmcm_lock;
//---------- Generate Per-Lane Signals -----------------
genvar i; // Index for per-lane signals
//---------- Input FF ----------------------------------------------------------
always @ (posedge pclk)
begin
if (!CLK_RST_N)
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= {PCIE_LANE{1'd0}};
gen3_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= {PCIE_LANE{1'd0}};
gen3_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= CLK_PCLK_SEL;
gen3_reg1 <= CLK_GEN3;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= pclk_sel_reg1;
gen3_reg2 <= gen3_reg1;
end
end
//---------- Select Reference clock or TXOUTCLK --------------------------------
generate if ((PCIE_TXBUF_EN == "TRUE") && (PCIE_LINK_SPEED != 3))
begin : refclk_i
//---------- Select Reference Clock ----------------------------------------
BUFG refclk_i
(
//---------- Input -------------------------------------
.I (CLK_CLK),
//---------- Output ------------------------------------
.O (refclk)
);
end
else
begin : txoutclk_i
//---------- Select TXOUTCLK -----------------------------------------------
BUFG txoutclk_i
(
//---------- Input -------------------------------------
.I (CLK_TXOUTCLK),
//---------- Output ------------------------------------
.O (refclk)
);
end
endgenerate
//---------- MMCM --------------------------------------------------------------
MMCME2_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (CLKOUT0_DIVIDE_F),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (CLKIN1_PERIOD),
.REF_JITTER1 (0.010)
)
mmcm_i
(
//---------- Input ------------------------------------
.CLKIN1 (refclk),
//.CLKIN2 (1'd0), // Removed for ISE
.CLKINSEL (1'd1),
.CLKFBIN (mmcm_fb),
.RST (!CLK_RST_N),
.PWRDWN (1'd0),
//---------- Output ------------------------------------
.CLKFBOUT (mmcm_fb),
.CLKFBOUTB (),
.CLKOUT0 (clk_125mhz),
.CLKOUT0B (),
.CLKOUT1 (clk_250mhz),
.CLKOUT1B (),
.CLKOUT2 (userclk1),
.CLKOUT2B (),
.CLKOUT3 (userclk2),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.LOCKED (mmcm_lock),
//---------- Dynamic Reconfiguration -------------------
.DCLK ( 1'd0),
.DADDR ( 7'd0),
.DEN ( 1'd0),
.DWE ( 1'd0),
.DI (16'd0),
.DO (),
.DRDY (),
//---------- Dynamic Phase Shift -----------------------
.PSCLK (1'd0),
.PSEN (1'd0),
.PSINCDEC (1'd0),
.PSDONE (),
//---------- Control and Status ------------------------
.CLKINSTOPPED (),
.CLKFBSTOPPED ()
);
//---------- Select PCLK MUX ---------------------------------------------------
generate if (PCIE_LINK_SPEED != 1)
begin : pclk_i1_bufgctrl
//---------- PCLK Mux ----------------------------------
BUFGCTRL pclk_i1
(
//---------- Input ---------------------------------
.CE0 (1'd1),
.CE1 (1'd1),
.I0 (clk_125mhz),
.I1 (clk_250mhz),
.IGNORE0 (1'd0),
.IGNORE1 (1'd0),
.S0 (~pclk_sel),
.S1 ( pclk_sel),
//---------- Output --------------------------------
.O (pclk_1)
);
end
else
//---------- Select PCLK Buffer ------------------------
begin : pclk_i1_bufg
//---------- PCLK Buffer -------------------------------
BUFG pclk_i1
(
//---------- Input ---------------------------------
.I (clk_125mhz),
//---------- Output --------------------------------
.O (pclk_1)
);
end
endgenerate
//---------- Generate RXOUTCLK Buffer for Debug --------------------------------
generate if (PCIE_DEBUG_MODE == 1)
begin : rxoutclk_per_lane
//---------- Generate per Lane -------------------------
for (i=0; i<PCIE_LANE; i=i+1)
begin : rxoutclk_i
//---------- RXOUTCLK Buffer -----------------------
BUFG rxoutclk_i
(
//---------- Input -----------------------------
.I (CLK_RXOUTCLK_IN[i]),
//---------- Output ----------------------------
.O (CLK_RXOUTCLK_OUT[i])
);
end
end
else
//---------- Disable RXOUTCLK Buffer for Normal Operation
begin : rxoutclk_i_disable
assign CLK_RXOUTCLK_OUT = {PCIE_LANE{1'd0}};
end
endgenerate
//---------- Generate DCLK Buffer ----------------------------------------------
generate if (PCIE_LINK_SPEED != 1)
begin : dclk_i
//---------- DCLK Buffer -------------------------------
BUFG dclk_i
(
//---------- Input ---------------------------------
.I (clk_125mhz),
//---------- Output --------------------------------
.O (CLK_DCLK)
);
end
else
//---------- Disable DCLK Buffer -----------------------
begin : dclk_i_disable
assign CLK_DCLK = pclk_1;
end
endgenerate
//---------- Generate USERCLK1 Buffer ------------------------------------------
generate if (PCIE_USERCLK1_FREQ != 0)
begin : userclk1_i1
//---------- USERCLK1 Buffer ---------------------------
BUFG usrclk1_i1
(
//---------- Input ---------------------------------
.I (userclk1),
//---------- Output --------------------------------
.O (userclk1_1)
);
end
else
//---------- Disable USERCLK1 Buffer -------------------
begin : disable_userclk1_i1
assign userclk1_1 = 1'd0;
end
endgenerate
//---------- Generate USERCLK2 Buffer ------------------------------------------
generate if (PCIE_USERCLK2_FREQ != 0)
begin : userclk2_i1
//---------- USERCLK2 Buffer ---------------------------
BUFG usrclk2_i1
(
//---------- Input ---------------------------------
.I (userclk2),
//---------- Output --------------------------------
.O (userclk2_1)
);
end
else
//---------- Disable USERCLK2 Buffer -------------------
begin : userclk2_i1_disable
assign userclk2_1 = 1'd0;
end
endgenerate
//---------- Generate 2nd Stage Buffers ----------------------------------------
generate if ((PCIE_LINK_SPEED == 3) && (PCIE_ASYNC_EN == "TRUE"))
begin : second_stage_buf
//---------- PCLK Buffer ---------------------------------------------------
BUFG pclk_i2
(
//---------- Input -------------------------------------
.I (pclk_1),
//---------- Output ------------------------------------
.O (pclk)
);
//---------- RXUSRCLK Mux --------------------------------------------------
BUFGCTRL rxusrclk_i2
(
//---------- Input ---------------------------------
.CE0 (1'b1),
.CE1 (1'b1),
.I0 (pclk_1),
.I1 (CLK_RXOUTCLK_IN[0]),
.IGNORE0 (1'b0),
.IGNORE1 (1'b0),
.S0 (~gen3_reg2),
.S1 ( gen3_reg2),
//---------- Output --------------------------------
.O (CLK_RXUSRCLK)
);
//---------- Generate USERCLK1 Buffer --------------------------------------
if (PCIE_USERCLK1_FREQ != 0)
begin : userclk1_i2
//---------- USERCLK1 Buffer -----------------------
BUFG usrclk1_i2
(
//---------- Input -----------------------------
.I (userclk1_1),
//---------- Output ----------------------------
.O (CLK_USERCLK1)
);
end
else
//---------- Disable USERCLK1 Buffer ---------------
begin : userclk1_i2_disable
assign CLK_USRCLK1 = userclk1_1;
end
//---------- Generate USERCLK2 Buffer --------------------------------------
if (PCIE_USERCLK2_FREQ != 0)
begin : userclk2_i2
//---------- USERCLK2 Buffer -----------------------
BUFG usrclk2_i2
(
//---------- Input -----------------------------
.I (userclk2_1),
//---------- Output ----------------------------
.O (CLK_USERCLK2)
);
end
else
//---------- Disable USERCLK2 Buffer ---------------
begin : userclk2_i2_disable
assign CLK_USRCLK2 = userclk2_1;
end
end
else
//---------- Disable 2nd Stage Buffer --------------------------------------
begin : second_stage_buf_disable
assign pclk = pclk_1;
assign CLK_RXUSRCLK = pclk_1;
assign CLK_USERCLK1 = userclk1_1;
assign CLK_USERCLK2 = userclk2_1;
end
endgenerate
//---------- Select PCLK -------------------------------------------------------
always @ (posedge pclk)
begin
if (!CLK_RST_N)
pclk_sel <= 1'd0;
else
begin
//---------- Set 250 MHz ---------------------------
if (&pclk_sel_reg2)
pclk_sel <= 1'd1;
//---------- Set 125 MHz ---------------------------
else if (&(~pclk_sel_reg2))
pclk_sel <= 1'd0;
//---------- Hold PCLK -----------------------------
else
pclk_sel <= pclk_sel;
end
end
//---------- PIPE Clock Output -------------------------------------------------
assign CLK_PCLK = pclk;
assign CLK_MMCM_LOCK = mmcm_lock;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFBBN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DFBBN_FUNCTIONAL_PP_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET;
wire SET ;
wire CLK ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFBBN_FUNCTIONAL_PP_V |
`timescale 1ns/1ns
//-----------------------------------------------------------------------------
// Copyright (C) 2009 OutputLogic.com
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//-----------------------------------------------------------------------------
// CRC module for data[10:0] , crc[4:0]=1+x^2+x^5;
//-----------------------------------------------------------------------------
// MQ 3/7/2015: invert output
module usb_crc5(
input [10:0] data_in,
input crc_en,
output [4:0] crc_out,
input rst,
input clk);
reg [4:0] lfsr_q,lfsr_c;
assign crc_out = ~lfsr_q;
always @(*) begin
lfsr_c[0] = lfsr_q[0] ^ lfsr_q[3] ^ lfsr_q[4] ^ data_in[0] ^ data_in[3] ^ data_in[5] ^ data_in[6] ^ data_in[9] ^ data_in[10];
lfsr_c[1] = lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[4] ^ data_in[1] ^ data_in[4] ^ data_in[6] ^ data_in[7] ^ data_in[10];
lfsr_c[2] = lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[4] ^ data_in[0] ^ data_in[2] ^ data_in[3] ^ data_in[6] ^ data_in[7] ^ data_in[8] ^ data_in[9] ^ data_in[10];
lfsr_c[3] = lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[4] ^ data_in[1] ^ data_in[3] ^ data_in[4] ^ data_in[7] ^ data_in[8] ^ data_in[9] ^ data_in[10];
lfsr_c[4] = lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[4] ^ data_in[2] ^ data_in[4] ^ data_in[5] ^ data_in[8] ^ data_in[9] ^ data_in[10];
end // always
always @(posedge clk, posedge rst) begin
if(rst) begin
lfsr_q <= {5{1'b1}};
end
else begin
lfsr_q <= crc_en ? lfsr_c : lfsr_q;
end
end // always
endmodule // crc
`ifdef TEST_USB_CRC5
module tb();
reg [10:0] data_in;
reg crc_en;
wire [4:0] crc_out;
reg rst;
wire clk;
sim_clk #(125) clk_125_r(.clk(clk));
usb_crc5 dut(.*);
wire [4:0] to_wire = ~crc_out; //{ crc_out[0], crc_out[1], crc_out[2], crc_out[3], crc_out[4] };
initial begin
$dumpfile("crc5.lxt");
$dumpvars();
rst <= 1'b0;
crc_en <= 1'b0;
wait(clk);
wait(~clk);
rst <= 1'b1;
wait(clk);
wait(~clk);
rst <= 1'b0;
wait(clk);
wait(~clk);
data_in <= 11'b10000000000;
crc_en <= 1'b1;
wait(clk);
wait(~clk);
rst <= 1'b1;
crc_en <= 1'b0;
wait(clk);
wait(~clk);
rst <= 1'b0;
crc_en <= 1'b1;
data_in <= 11'b01000000000;
#1000;
$finish();
end
endmodule
`endif
|
module opicorv32_pcpi_if_wrap (
pcpi_ready,
pcpi_wait,
pcpi_rd,
pcpi_wr,
pcpi_rs2,
pcpi_rs1,
pcpi_insn,
pcpi_valid,
resetn,
clk,
pcpi_int_wr,
pcpi_int_rd,
pcpi_int_wait,
pcpi_int_ready
);
input pcpi_ready;
input pcpi_wait;
input [31:0] pcpi_rd;
input pcpi_wr;
input [31:0] pcpi_rs2;
input [31:0] pcpi_rs1;
input [31:0] pcpi_insn;
input pcpi_valid;
input resetn;
input clk;
output pcpi_int_wr;
output [31:0] pcpi_int_rd;
output pcpi_int_wait;
output pcpi_int_ready;
/* signal declarations */
wire _2562;
wire _2558;
wire compare_pcpi_int_ready;
wire _2564;
wire _2565;
wire _2559;
wire compare_pcpi_int_wait;
wire _2567;
wire [31:0] _2568;
wire [31:0] _2560;
wire [31:0] compare_pcpi_int_rd;
wire [31:0] _2570;
wire [34:0] _2555;
wire _2571;
wire [34:0] _2557;
wire _2561;
wire compare_pcpi_int_wr;
wire _2573;
/* logic */
assign _2562 = _2555[34:34];
assign _2558 = _2557[34:34];
assign compare_pcpi_int_ready = _2558 ^ _2562;
assign _2564 = compare_pcpi_int_ready ^ _2562;
assign _2565 = _2555[33:33];
assign _2559 = _2557[33:33];
assign compare_pcpi_int_wait = _2559 ^ _2565;
assign _2567 = compare_pcpi_int_wait ^ _2565;
assign _2568 = _2555[32:1];
assign _2560 = _2557[32:1];
assign compare_pcpi_int_rd = _2560 ^ _2568;
assign _2570 = compare_pcpi_int_rd ^ _2568;
picorv32_pcpi_if
#( .ENABLE_PCPI(0), .ENABLE_MUL(1) )
the_picorv32_pcpi_if
( .clk(clk), .resetn(resetn), .pcpi_valid(pcpi_valid), .pcpi_insn(pcpi_insn), .pcpi_rs1(pcpi_rs1), .pcpi_rs2(pcpi_rs2), .pcpi_wr(pcpi_wr), .pcpi_rd(pcpi_rd), .pcpi_wait(pcpi_wait), .pcpi_ready(pcpi_ready), .pcpi_int_ready(_2555[34:34]), .pcpi_int_wait(_2555[33:33]), .pcpi_int_rd(_2555[32:1]), .pcpi_int_wr(_2555[0:0]) );
assign _2571 = _2555[0:0];
opicorv32_pcpi_if
the_opicorv32_pcpi_if
( .clk(clk), .resetn(resetn), .pcpi_valid(pcpi_valid), .pcpi_insn(pcpi_insn), .pcpi_rs1(pcpi_rs1), .pcpi_rs2(pcpi_rs2), .pcpi_wr(pcpi_wr), .pcpi_rd(pcpi_rd), .pcpi_wait(pcpi_wait), .pcpi_ready(pcpi_ready), .pcpi_int_ready(_2557[34:34]), .pcpi_int_wait(_2557[33:33]), .pcpi_int_rd(_2557[32:1]), .pcpi_int_wr(_2557[0:0]) );
assign _2561 = _2557[0:0];
assign compare_pcpi_int_wr = _2561 ^ _2571;
assign _2573 = compare_pcpi_int_wr ^ _2571;
/* aliases */
/* output assignments */
assign pcpi_int_wr = _2573;
assign pcpi_int_rd = _2570;
assign pcpi_int_wait = _2567;
assign pcpi_int_ready = _2564;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311OI_SYMBOL_V
`define SKY130_FD_SC_LS__A311OI_SYMBOL_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a311oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311OI_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2011 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001))
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer i;
reg [63:0] b;
real r, r2;
integer cyc=0;
realtime uninit;
initial if (uninit != 0.0) $stop;
sub_cast_bug374 sub (.cyc5(cyc[4:0]), .*);
initial begin
if (1_00_0.0_1 != 1000.01) $stop;
// rtoi truncates
if ($rtoi(36.7) != 36) $stop;
if ($rtoi(36.5) != 36) $stop;
if ($rtoi(36.4) != 36) $stop;
// casting rounds
if ((integer '(36.7)) != 37) $stop;
if ((integer '(36.5)) != 37) $stop;
if ((integer '(36.4)) != 36) $stop;
// assignment rounds
// verilator lint_off REALCVT
i = 36.7; if (i != 37) $stop;
i = 36.5; if (i != 37) $stop;
i = 36.4; if (i != 36) $stop;
r = 10'd38; if (r!=38.0) $stop;
// verilator lint_on REALCVT
// operators
if ((-(1.5)) != -1.5) $stop;
if ((+(1.5)) != 1.5) $stop;
if (((1.5)+(1.25)) != 2.75) $stop;
if (((1.5)-(1.25)) != 0.25) $stop;
if (((1.5)*(1.25)) != 1.875) $stop;
if (((1.5)/(1.25)) != 1.2) $stop;
//
if (((1.5)==(2)) != 1'b0) $stop; // note 2 becomes real 2.0
if (((1.5)!=(2)) != 1'b1) $stop;
if (((1.5)> (2)) != 1'b0) $stop;
if (((1.5)>=(2)) != 1'b0) $stop;
if (((1.5)< (2)) != 1'b1) $stop;
if (((1.5)<=(2)) != 1'b1) $stop;
if (((1.5)==(1.5)) != 1'b1) $stop;
if (((1.5)!=(1.5)) != 1'b0) $stop;
if (((1.5)> (1.5)) != 1'b0) $stop;
if (((1.5)>=(1.5)) != 1'b1) $stop;
if (((1.5)< (1.5)) != 1'b0) $stop;
if (((1.5)<=(1.5)) != 1'b1) $stop;
if (((1.6)==(1.5)) != 1'b0) $stop;
if (((1.6)!=(1.5)) != 1'b1) $stop;
if (((1.6)> (1.5)) != 1'b1) $stop;
if (((1.6)>=(1.5)) != 1'b1) $stop;
if (((1.6)< (1.5)) != 1'b0) $stop;
if (((1.6)<=(1.5)) != 1'b0) $stop;
//
if (((0.0)?(2.0):(1.1)) != 1.1) $stop;
if (((1.5)?(2.0):(1.1)) != 2.0) $stop;
//
if (!1.7) $stop;
if (!(!0.0)) $stop;
if (1.8 && 0.0) $stop;
if (!(1.8 || 0.0)) $stop;
//
i=0;
for (r=1.0; r<2.0; r=r+0.1) i++;
if (i!=10) $stop;
// bug
r = $bitstoreal($realtobits(1.414));
if (r != 1.414) $stop;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
end
else if (cyc<90) begin
if ($time != {32'h0, $rtoi($realtime)}) $stop;
if ($itor(cyc) != cyc) $stop;
//Unsup: if ((real `($time)) != $realtime) $stop;
r = $itor(cyc*2);
i = $rtoi(r);
if (i!=cyc*2) $stop;
//
r = $itor(cyc)/1.5;
b = $realtobits(r);
r2 = $bitstoreal(b);
if (r != r2) $stop;
//
// Trust the integer math as a comparison
r = $itor(cyc);
if ($rtoi(-r) != -cyc) $stop;
if ($rtoi(+r) != cyc) $stop;
if ($rtoi(r+2.0) != (cyc+2)) $stop;
if ($rtoi(r-2.0) != (cyc-2)) $stop;
if ($rtoi(r*2.0) != (cyc*2)) $stop;
if ($rtoi(r/2.0) != (cyc/2)) $stop;
r2 = (2.0/(r-60)); // When zero, result indeterminate, but no crash
//
r2 = $itor(cyc);
case (r)
(r2-1.0): $stop;
r2: ;
default: $stop;
endcase
//
r = $itor(cyc);
if ((r==50.0) != (cyc==50)) $stop;
if ((r!=50.0) != (cyc!=50)) $stop;
if ((r> 50.0) != (cyc> 50)) $stop;
if ((r>=50.0) != (cyc>=50)) $stop;
if ((r< 50.0) != (cyc< 50)) $stop;
if ((r<=50.0) != (cyc<=50)) $stop;
//
if ($rtoi((r-50.0) ? 10.0 : 20.0)
!= (((cyc-50)!=0) ? 10 : 20)) $stop;
//
if ((!(r-50.0)) != (!((cyc-50) != 0))) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub_cast_bug374(input clk, input [4:0] cyc5);
integer i;
always @(posedge clk) begin
i <= integer'(cyc5);
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Spartan-6 Integrated Block for PCI Express
// File : axi_basic_rx_pipeline.v
//----------------------------------------------------------------------------//
// File: axi_basic_rx_pipeline.v //
// //
// Description: //
// TRN to AXI RX pipeline. Converts received data from TRN protocol to AXI. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// axi_basic_rx_pipeline //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_rx_pipeline #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter STRB_WIDTH = C_DATA_WIDTH / 8 // TKEEP width
) (
// AXI RX
//-----------
output reg [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output reg m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [STRB_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output reg [21:0] m_axis_rx_tuser, // RX user signals
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output reg trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// Null Inputs
//-----------
input null_rx_tvalid, // NULL generated tvalid
input null_rx_tlast, // NULL generated tlast
input [STRB_WIDTH-1:0] null_rx_tkeep, // NULL generated tkeep
input null_rdst_rdy, // NULL generated rdst_rdy
input [4:0] null_is_eof, // NULL generated is_eof
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires and regs for creating AXI signals
wire [4:0] is_sof;
wire [4:0] is_sof_prev;
wire [4:0] is_eof;
wire [4:0] is_eof_prev;
reg [STRB_WIDTH-1:0] reg_tkeep;
wire [STRB_WIDTH-1:0] tkeep;
wire [STRB_WIDTH-1:0] tkeep_prev;
reg reg_tlast;
wire rsrc_rdy_filtered;
// Wires and regs for previous value buffer
wire [C_DATA_WIDTH-1:0] trn_rd_DW_swapped;
reg [C_DATA_WIDTH-1:0] trn_rd_prev;
wire data_hold;
reg data_prev;
reg trn_reof_prev;
reg [REM_WIDTH-1:0] trn_rrem_prev;
reg trn_rsrc_rdy_prev;
reg trn_rsrc_dsc_prev;
reg trn_rsof_prev;
reg [6:0] trn_rbar_hit_prev;
reg trn_rerrfwd_prev;
reg trn_recrc_err_prev;
// Null packet handling signals
reg null_mux_sel;
reg trn_in_packet;
wire dsc_flag;
wire dsc_detect;
reg reg_dsc_detect;
reg trn_rsrc_dsc_d;
// Create "filtered" version of rsrc_rdy, where discontinued SOFs are removed.
assign rsrc_rdy_filtered = trn_rsrc_rdy &&
(trn_in_packet || (trn_rsof && !trn_rsrc_dsc));
//----------------------------------------------------------------------------//
// Previous value buffer //
// --------------------- //
// We are inserting a pipeline stage in between TRN and AXI, which causes //
// some issues with handshaking signals m_axis_rx_tready/trn_rdst_rdy. The //
// added cycle of latency in the path causes the user design to fall behind //
// the TRN interface whenever it throttles. //
// //
// To avoid loss of data, we must keep the previous value of all trn_r* //
// signals in case the user throttles. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
trn_rd_prev <= #TCQ {C_DATA_WIDTH{1'b0}};
trn_rsof_prev <= #TCQ 1'b0;
trn_rrem_prev <= #TCQ {REM_WIDTH{1'b0}};
trn_rsrc_rdy_prev <= #TCQ 1'b0;
trn_rbar_hit_prev <= #TCQ 7'h00;
trn_rerrfwd_prev <= #TCQ 1'b0;
trn_recrc_err_prev <= #TCQ 1'b0;
trn_reof_prev <= #TCQ 1'b0;
trn_rsrc_dsc_prev <= #TCQ 1'b0;
end
else begin
// prev buffer works by checking trn_rdst_rdy. When trn_rdst_rdy is
// asserted, a new value is present on the interface.
if(trn_rdst_rdy) begin
trn_rd_prev <= #TCQ trn_rd_DW_swapped;
trn_rsof_prev <= #TCQ trn_rsof;
trn_rrem_prev <= #TCQ trn_rrem;
trn_rbar_hit_prev <= #TCQ trn_rbar_hit;
trn_rerrfwd_prev <= #TCQ trn_rerrfwd;
trn_recrc_err_prev <= #TCQ trn_recrc_err;
trn_rsrc_rdy_prev <= #TCQ rsrc_rdy_filtered;
trn_reof_prev <= #TCQ trn_reof;
trn_rsrc_dsc_prev <= #TCQ trn_rsrc_dsc || dsc_flag;
end
end
end
//----------------------------------------------------------------------------//
// Create TDATA //
//----------------------------------------------------------------------------//
// Convert TRN data format to AXI data format. AXI is DWORD swapped from TRN
// 128-bit: 64-bit: 32-bit:
// TRN DW0 maps to AXI DW3 TRN DW0 maps to AXI DW1 TNR DW0 maps to AXI DW0
// TRN DW1 maps to AXI DW2 TRN DW1 maps to AXI DW0
// TRN DW2 maps to AXI DW1
// TRN DW3 maps to AXI DW0
generate
if(C_DATA_WIDTH == 128) begin : rd_DW_swap_128
assign trn_rd_DW_swapped = {trn_rd[31:0],
trn_rd[63:32],
trn_rd[95:64],
trn_rd[127:96]};
end
else if(C_DATA_WIDTH == 64) begin : rd_DW_swap_64
assign trn_rd_DW_swapped = {trn_rd[31:0], trn_rd[63:32]};
end
else begin : rd_DW_swap_32
assign trn_rd_DW_swapped = trn_rd;
end
endgenerate
// Create special buffer which locks in the proper value of TDATA depending
// on whether the user is throttling or not. This buffer has three states:
//
// HOLD state: TDATA maintains its current value
// - the user has throttled the PCIe block
// PREVIOUS state: the buffer provides the previous value on trn_rd
// - the user has finished throttling, and is a little behind
// the PCIe block
// CURRENT state: the buffer passes the current value on trn_rd
// - the user is caught up and ready to receive the latest
// data from the PCIe block
always @(posedge user_clk) begin
if(user_rst) begin
m_axis_rx_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
end
else begin
if(!data_hold) begin
// PREVIOUS state
if(data_prev) begin
m_axis_rx_tdata <= #TCQ trn_rd_prev;
end
// CURRENT state
else begin
m_axis_rx_tdata <= #TCQ trn_rd_DW_swapped;
end
end
// else HOLD state
end
end
// Logic to instruct pipeline to hold its value
assign data_hold = (!m_axis_rx_tready && m_axis_rx_tvalid);
// Logic to instruct pipeline to use previous bus values. Always use previous
// value after holding a value.
always @(posedge user_clk) begin
if(user_rst) begin
data_prev <= #TCQ 1'b0;
end
else begin
data_prev <= #TCQ data_hold;
end
end
//----------------------------------------------------------------------------//
// Create TVALID, TLAST, TKEEP, TUSER //
// ----------------------------------- //
// Use the same strategy for these signals as for TDATA, except here we need //
// an extra provision for null packets. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
m_axis_rx_tvalid <= #TCQ 1'b0;
reg_tlast <= #TCQ 1'b0;
reg_tkeep <= #TCQ {STRB_WIDTH{1'b1}};
m_axis_rx_tuser <= #TCQ 22'h0;
end
else begin
if(!data_hold) begin
// If in a null packet, use null generated value
if(null_mux_sel) begin
m_axis_rx_tvalid <= #TCQ null_rx_tvalid;
reg_tlast <= #TCQ null_rx_tlast;
reg_tkeep <= #TCQ null_rx_tkeep;
m_axis_rx_tuser <= #TCQ {null_is_eof, 17'h0000};
end
// PREVIOUS state
else if(data_prev) begin
m_axis_rx_tvalid <= #TCQ (trn_rsrc_rdy_prev || dsc_flag);
reg_tlast <= #TCQ trn_reof_prev;
reg_tkeep <= #TCQ tkeep_prev;
m_axis_rx_tuser <= #TCQ {is_eof_prev, // TUSER bits [21:17]
2'b00, // TUSER bits [16:15]
is_sof_prev, // TUSER bits [14:10]
1'b0, // TUSER bit [9]
trn_rbar_hit_prev, // TUSER bits [8:2]
trn_rerrfwd_prev, // TUSER bit [1]
trn_recrc_err_prev}; // TUSER bit [0]
end
// CURRENT state
else begin
m_axis_rx_tvalid <= #TCQ (rsrc_rdy_filtered || dsc_flag);
reg_tlast <= #TCQ trn_reof;
reg_tkeep <= #TCQ tkeep;
m_axis_rx_tuser <= #TCQ {is_eof, // TUSER bits [21:17]
2'b00, // TUSER bits [16:15]
is_sof, // TUSER bits [14:10]
1'b0, // TUSER bit [9]
trn_rbar_hit, // TUSER bits [8:2]
trn_rerrfwd, // TUSER bit [1]
trn_recrc_err}; // TUSER bit [0]
end
end
// else HOLD state
end
end
// Hook up TLAST and TKEEP depending on interface width
generate
// For 128-bit interface, don't pass TLAST and TKEEP to user (is_eof and
// is_data passed to user instead). reg_tlast is still used internally.
if(C_DATA_WIDTH == 128) begin : tlast_tkeep_hookup_128
assign m_axis_rx_tlast = 1'b0;
assign m_axis_rx_tkeep = {STRB_WIDTH{1'b1}};
end
// For 64/32-bit interface, pass TLAST to user.
else begin : tlast_tkeep_hookup_64_32
assign m_axis_rx_tlast = reg_tlast;
assign m_axis_rx_tkeep = reg_tkeep;
end
endgenerate
//----------------------------------------------------------------------------//
// Create TKEEP //
// ------------ //
// Convert RREM to STRB. Here, we are converting the encoding method for the //
// location of the EOF from TRN flavor (rrem) to AXI (TKEEP). //
// //
// NOTE: for each configuration, we need two values of TKEEP, the current and //
// previous values. The need for these two values is described below. //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : rrem_to_tkeep_128
// TLAST and TKEEP not used in 128-bit interface. is_sof and is_eof used
// instead.
assign tkeep = 16'h0000;
assign tkeep_prev = 16'h0000;
end
else if(C_DATA_WIDTH == 64) begin : rrem_to_tkeep_64
// 64-bit interface: contains 2 DWORDs per cycle, for a total of 8 bytes
// - TKEEP has only two possible values here, 0xFF or 0x0F
assign tkeep = trn_rrem ? 8'hFF : 8'h0F;
assign tkeep_prev = trn_rrem_prev ? 8'hFF : 8'h0F;
end
else begin : rrem_to_tkeep_32
// 32-bit interface: contains 1 DWORD per cycle, for a total of 4 bytes
// - TKEEP is always 0xF in this case, due to the nature of the PCIe block
assign tkeep = 4'hF;
assign tkeep_prev = 4'hF;
end
endgenerate
//----------------------------------------------------------------------------//
// Create is_sof //
// ------------- //
// is_sof is a signal to the user indicating the location of SOF in TDATA . //
// Due to inherent 64-bit alignment of packets from the block, the only //
// possible values are: //
// Value Valid data widths //
// 5'b11000 (sof @ byte 8) 128 //
// 5'b10000 (sof @ byte 0) 128, 64, 32 //
// 5'b00000 (sof not present) 128, 64, 32 //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : is_sof_128
assign is_sof = {(trn_rsof && !trn_rsrc_dsc), // bit 4: enable
(trn_rsof && !trn_rrem[1]), // bit 3: sof @ byte 8?
3'b000}; // bit 2-0: hardwired 0
assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4
(trn_rsof_prev && !trn_rrem_prev[1]), // bit 3
3'b000}; // bit 2-0
end
else begin : is_sof_64_32
assign is_sof = {(trn_rsof && !trn_rsrc_dsc), // bit 4: enable
4'b0000}; // bit 3-0: hardwired 0
assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4
4'b0000}; // bit 3-0
end
endgenerate
//----------------------------------------------------------------------------//
// Create is_eof //
// ------------- //
// is_eof is a signal to the user indicating the location of EOF in TDATA . //
// Due to DWORD granularity of packets from the block, the only //
// possible values are: //
// Value Valid data widths //
// 5'b11111 (eof @ byte 15) 128 //
// 5'b11011 (eof @ byte 11) 128 //
// 5'b10111 (eof @ byte 7) 128, 64 //
// 5'b10011 (eof @ byte 3)` 128, 64, 32 //
// 5'b00011 (eof not present) 128, 64, 32 //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : is_eof_128
assign is_eof = {trn_reof, // bit 4: enable
trn_rrem, // bit 3-2: encoded eof loc rom block
2'b11}; // bit 1-0: hardwired 1
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
trn_rrem_prev, // bit 3-2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
end
else if(C_DATA_WIDTH == 64) begin : is_eof_64
assign is_eof = {trn_reof, // bit 4: enable
1'b0, // bit 3: hardwired 0
trn_rrem, // bit 2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
1'b0, // bit 3: hardwired 0
trn_rrem_prev, // bit 2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
end
else begin : is_eof_32
assign is_eof = {trn_reof, // bit 4: enable
4'b0011}; // bit 3-0: hardwired to byte 3
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
4'b0011}; // bit 3-0: hardwired to byte 3
end
endgenerate
//----------------------------------------------------------------------------//
// Create trn_rdst_rdy //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
trn_rdst_rdy <= #TCQ 1'b0;
end
else begin
// If in a null packet, use null generated value
if(null_mux_sel && m_axis_rx_tready) begin
trn_rdst_rdy <= #TCQ null_rdst_rdy;
end
// If a discontinue needs to be serviced, throttle the block until we are
// ready to pad out the packet.
else if(dsc_flag) begin
trn_rdst_rdy <= #TCQ 1'b0;
end
// If in a packet, pass user back-pressure directly to block
else if(m_axis_rx_tvalid) begin
trn_rdst_rdy <= #TCQ m_axis_rx_tready;
end
// If idle, default to no back-pressure. We need to default to the
// "ready to accept data" state to make sure we catch the first
// clock of data of a new packet.
else begin
trn_rdst_rdy <= #TCQ 1'b1;
end
end
end
//----------------------------------------------------------------------------//
// Create null_mux_sel //
// null_mux_sel is the signal used to detect a discontinue situation and //
// mux in the null packet generated in rx_null_gen. Only mux in null data //
// when not at the beginningof a packet. SOF discontinues do not require //
// padding, as the whole packet is simply squashed instead. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
null_mux_sel <= #TCQ 1'b0;
end
else begin
// NULL packet done
if(null_mux_sel && null_rx_tlast && m_axis_rx_tready)
begin
null_mux_sel <= #TCQ 1'b0;
end
// Discontinue detected and we're in packet, so switch to NULL packet
else if(dsc_flag && !data_hold) begin
null_mux_sel <= #TCQ 1'b1;
end
end
end
//----------------------------------------------------------------------------//
// Create discontinue tracking signals //
//----------------------------------------------------------------------------//
// Create signal trn_in_packet, which is needed to validate trn_rsrc_dsc. We
// should ignore trn_rsrc_dsc when it's asserted out-of-packet.
always @(posedge user_clk) begin
if(user_rst) begin
trn_in_packet <= #TCQ 1'b0;
end
else begin
if(trn_rsof && !trn_reof && rsrc_rdy_filtered && trn_rdst_rdy)
begin
trn_in_packet <= #TCQ 1'b1;
end
else if(trn_rsrc_dsc) begin
trn_in_packet <= #TCQ 1'b0;
end
else if(trn_reof && !trn_rsof && trn_rsrc_rdy && trn_rdst_rdy) begin
trn_in_packet <= #TCQ 1'b0;
end
end
end
// Create dsc_flag, which identifies and stores mid-packet discontinues that
// require null packet padding. This signal is edge sensitive to trn_rsrc_dsc,
// to make sure we don't service the same dsc twice in the event that
// trn_rsrc_dsc stays asserted for longer than it takes to pad out the packet.
assign dsc_detect = trn_rsrc_dsc && !trn_rsrc_dsc_d && trn_in_packet &&
(!trn_rsof || trn_reof) && !(trn_rdst_rdy && trn_reof);
always @(posedge user_clk) begin
if(user_rst) begin
reg_dsc_detect <= #TCQ 1'b0;
trn_rsrc_dsc_d <= #TCQ 1'b0;
end
else begin
if(dsc_detect) begin
reg_dsc_detect <= #TCQ 1'b1;
end
else if(null_mux_sel) begin
reg_dsc_detect <= #TCQ 1'b0;
end
trn_rsrc_dsc_d <= #TCQ trn_rsrc_dsc;
end
end
assign dsc_flag = dsc_detect || reg_dsc_detect;
//----------------------------------------------------------------------------//
// Create np_counter (V6 128-bit only). This counter tells the V6 128-bit //
// interface core how many NP packets have left the RX pipeline. The V6 //
// 128-bit interface uses this count to perform rnp_ok modulation. //
//----------------------------------------------------------------------------//
generate
if(C_FAMILY == "V6" && C_DATA_WIDTH == 128) begin : np_cntr_to_128_enabled
reg [2:0] reg_np_counter;
// Look for NP packets beginning on lower (i.e. unaligned) start
wire mrd_lower = (!(|m_axis_rx_tdata[92:88]) && !m_axis_rx_tdata[94]);
wire mrd_lk_lower = (m_axis_rx_tdata[92:88] == 5'b00001);
wire io_rdwr_lower = (m_axis_rx_tdata[92:88] == 5'b00010);
wire cfg_rdwr_lower = (m_axis_rx_tdata[92:89] == 4'b0010);
wire atomic_lower = ((&m_axis_rx_tdata[91:90]) && m_axis_rx_tdata[94]);
wire np_pkt_lower = (mrd_lower ||
mrd_lk_lower ||
io_rdwr_lower ||
cfg_rdwr_lower ||
atomic_lower) && m_axis_rx_tuser[13];
// Look for NP packets beginning on upper (i.e. aligned) start
wire mrd_upper = (!(|m_axis_rx_tdata[28:24]) && !m_axis_rx_tdata[30]);
wire mrd_lk_upper = (m_axis_rx_tdata[28:24] == 5'b00001);
wire io_rdwr_upper = (m_axis_rx_tdata[28:24] == 5'b00010);
wire cfg_rdwr_upper = (m_axis_rx_tdata[28:25] == 4'b0010);
wire atomic_upper = ((&m_axis_rx_tdata[27:26]) && m_axis_rx_tdata[30]);
wire np_pkt_upper = (mrd_upper ||
mrd_lk_upper ||
io_rdwr_upper ||
cfg_rdwr_upper ||
atomic_upper) && !m_axis_rx_tuser[13];
wire pkt_accepted =
m_axis_rx_tuser[14] && m_axis_rx_tready && m_axis_rx_tvalid;
// Increment counter whenever an NP packet leaves the RX pipeline
always @(posedge user_clk) begin
if (user_rst) begin
reg_np_counter <= #TCQ 0;
end
else begin
if((np_pkt_lower || np_pkt_upper) && pkt_accepted)
begin
reg_np_counter <= #TCQ reg_np_counter + 3'h1;
end
end
end
assign np_counter = reg_np_counter;
end
else begin : np_cntr_to_128_disabled
assign np_counter = 3'h0;
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
`include "defines.vh"
module mips_tb;
parameter DATA_WIDTH = 32;
parameter CODE_FILE = "mips/benchmarkpp.hex";
parameter IM_BUS_WIDTH = 10;
parameter DM_BUS_WIDTH = 24;
parameter CLK_HZ = 0;
parameter COUNT = 100000;
parameter DELAY = 5;
parameter TIME = (COUNT * DELAY);
reg raw_clk;
reg raw_rst;
reg raw_en;
reg switch_rst;
reg switch_stat;
reg switch_ram;
reg switch_correctprediction;
reg switch_misprediction;
reg switch_loaduse;
reg switch_branchstall;
reg [4:0] switch_addr;
wire [7:0] anodes;
wire [7:0] cnodes;
mips #(
.DATA_WIDTH(DATA_WIDTH),
.CODE_FILE(CODE_FILE),
.IM_BUS_WIDTH(IM_BUS_WIDTH),
.DM_BUS_WIDTH(DM_BUS_WIDTH),
.CLK_HZ(CLK_HZ)
) mips (
.raw_clk(raw_clk),
.raw_rst(raw_rst),
.raw_en(raw_en),
.switch_rst(switch_rst),
.switch_stat(switch_stat),
.switch_ram(switch_ram),
.switch_correctprediction(switch_correctprediction),
.switch_misprediction(switch_misprediction),
.switch_loaduse(switch_loaduse),
.switch_branchstall(switch_branchstall),
.switch_addr(switch_addr),
.anodes(anodes),
.cnodes(cnodes)
);
always begin
#DELAY raw_clk <= ~raw_clk;
end
initial begin
$dumpfile("vcd/mips_tb.vcd");
$dumpvars(0, mips_tb);
$display("led_data,\tstat_count,\tstat_correctprediction,\tstat_misprediction\t,stat_loaduse,\tstat_branchstall");
$monitor("%x, %x/%4d, %x/%3d, %x/%3d, %x/%3d, %x/%3d, %x/%3d",
mips.led_data,
mips.stat_count,
mips.stat_count,
mips.stat_correctprediction,
mips.stat_correctprediction,
mips.stat_misprediction,
mips.stat_misprediction,
mips.stat_flushD,
mips.stat_flushD,
mips.stat_loaduse,
mips.stat_loaduse,
mips.stat_branchstall,
mips.stat_branchstall
// mips.regfile.regfile[`V0][31:0], /* $v0 */
// mips.regfile.regfile[`A0][31:0], /* $a0 */
// mips.MEM_WB.WB_IR
);
raw_clk <= 1'b0;
raw_rst <= 1'b1;
raw_en <= 1'b1;
switch_rst <= 1'b0;
switch_stat <= 1'b0;
switch_ram <= 1'b0;
switch_correctprediction <= 1'b0;
switch_misprediction <= 1'b0;
switch_loaduse <= 1'b0;
switch_branchstall <= 1'b0;
switch_addr <= 5'b00000;
@(posedge raw_clk);
@(posedge raw_clk);
@(posedge raw_clk);
@(posedge raw_clk);
@(posedge raw_clk);
@(posedge raw_clk);
raw_rst <= 1'b0;
#TIME $finish;
end
endmodule // mips_tb
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sat May 27 21:33:31 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_comparator_0_0/system_comparator_0_0_stub.v
// Design : system_comparator_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "comparator,Vivado 2016.4" *)
module system_comparator_0_0(x, y, z)
/* synthesis syn_black_box black_box_pad_pin="x[31:0],y[31:0],z" */;
input [31:0]x;
input [31:0]y;
output z;
endmodule
|
//this is the collision detection module
module denise_collision
(
input clk, // 28MHz clock
input clk7_en,
input reset, //reset
input aga, // aga enabled
input [8:1] reg_address_in, //register adress inputs
input [15:0] data_in, //bus data in
output [15:0] data_out, //bus data out
input dblpf, //dual playfield signal, required to support undocumented feature
input [7:0] bpldata, //bitplane serial video data in
input [7:0] nsprite
);
//register names and adresses
parameter CLXCON = 9'h098;
parameter CLXCON2 = 9'h10e;
parameter CLXDAT = 9'h00e;
//local signals
reg [15:0] clxcon; //collision detection control register
reg [15:0] clxcon2; // collision reg 2
reg [14:0] clxdat; //collision detection data register
wire [3:0] sprmatch; //sprite group matches clxcon settings
wire oddmatch; //odd bitplane data matches clxcon settings
wire evenmatch; //even bitplane data matches clxcon settings
//--------------------------------------------------------------------------------------
//CLXCON register
always @(posedge clk)
if (clk7_en) begin
if (reset) //reset to safe value
clxcon <= 16'h0fff;
else if (reg_address_in[8:1] == CLXCON[8:1])
clxcon <= data_in;
end
always @ (posedge clk) begin
if (clk7_en) begin
if (reset || (reg_address_in[8:1] == CLXCON[8:1]))
clxcon2 <= #1 16'h0000;
else if (aga && (reg_address_in[8:1] == CLXCON2[8:1]))
clxcon2 <= #1 data_in;
end
end
//--------------------------------------------------------------------------------------
//generate bitplane match signal
wire [7:0] bm;
assign bm = (bpldata[7:0] ^ ~{clxcon2[1:0],clxcon[5:0]}) | (~{clxcon2[7:6],clxcon[11:6]}); // JB: playfield collision detection fix
// this is the implementation of an undocumented function in the real Denise chip, developed by Yaqube.
// trigger was the game Rotor. mentioned in WinUAE sources to be the only known game needing this feature.
// it also fixes the Spaceport instandly helicopter crash at takeoff
// and Archon-1 'sticky effect' of player sprite at the battlefield.
// the OCS mystery is cleaning up :)
assign oddmatch = bm[6] & bm[4] & bm[2] & bm[0] & (dblpf | evenmatch);
assign evenmatch = bm[7] & bm[5] & bm[3] & bm[1];
//generate sprite group match signal
/*assign sprmatch[0] = (nsprite[0] | (nsprite[1]) & clxcon[12]);*/
/*assign sprmatch[1] = (nsprite[2] | (nsprite[3]) & clxcon[13]);*/
/*assign sprmatch[2] = (nsprite[4] | (nsprite[5]) & clxcon[14]);*/
/*assign sprmatch[3] = (nsprite[6] | (nsprite[7]) & clxcon[15]);*/
assign sprmatch[0] = nsprite[0] | (nsprite[1] & clxcon[12]);
assign sprmatch[1] = nsprite[2] | (nsprite[3] & clxcon[13]);
assign sprmatch[2] = nsprite[4] | (nsprite[5] & clxcon[14]);
assign sprmatch[3] = nsprite[6] | (nsprite[7] & clxcon[15]);
//--------------------------------------------------------------------------------------
//detect collisions
wire [14:0] cl;
reg clxdat_read_del;
assign cl[0] = evenmatch & oddmatch; //odd to even bitplanes
assign cl[1] = oddmatch & sprmatch[0]; //odd bitplanes to sprite 0(or 1)
assign cl[2] = oddmatch & sprmatch[1]; //odd bitplanes to sprite 2(or 3)
assign cl[3] = oddmatch & sprmatch[2]; //odd bitplanes to sprite 4(or 5)
assign cl[4] = oddmatch & sprmatch[3]; //odd bitplanes to sprite 6(or 7)
assign cl[5] = evenmatch & sprmatch[0]; //even bitplanes to sprite 0(or 1)
assign cl[6] = evenmatch & sprmatch[1]; //even bitplanes to sprite 2(or 3)
assign cl[7] = evenmatch & sprmatch[2]; //even bitplanes to sprite 4(or 5)
assign cl[8] = evenmatch & sprmatch[3]; //even bitplanes to sprite 6(or 7)
assign cl[9] = sprmatch[0] & sprmatch[1]; //sprite 0(or 1) to sprite 2(or 3)
assign cl[10] = sprmatch[0] & sprmatch[2]; //sprite 0(or 1) to sprite 4(or 5)
assign cl[11] = sprmatch[0] & sprmatch[3]; //sprite 0(or 1) to sprite 6(or 7)
assign cl[12] = sprmatch[1] & sprmatch[2]; //sprite 2(or 3) to sprite 4(or 5)
assign cl[13] = sprmatch[1] & sprmatch[3]; //sprite 2(or 3) to sprite 6(or 7)
assign cl[14] = sprmatch[2] & sprmatch[3]; //sprite 4(or 5) to sprite 6(or 7)
wire clxdat_read = (reg_address_in[8:1]==CLXDAT[8:1]);// clxdat read
always @(posedge clk)
if (clk7_en) begin
clxdat_read_del <= clxdat_read;
end
//register detected collisions
always @(posedge clk)
if (clk7_en) begin
// if (reg_address_in[8:1]==CLXDAT[8:1]) //if clxdat is read, clxdat is cleared to all zero's
if (!clxdat_read & clxdat_read_del) //if clxdat is read, clxdat is cleared to all zero's after read
clxdat <= 0;
else //else register collisions
clxdat <= clxdat[14:0] | cl[14:0];
end
//--------------------------------------------------------------------------------------
//reading of clxdat register
assign data_out = reg_address_in[8:1]==CLXDAT[8:1] ? {1'b1,clxdat[14:0]} : 16'd0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3B_4_V
`define SKY130_FD_SC_LS__NAND3B_4_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand3b_4 (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand3b_4 (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3B_4_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file spartan3_dmem.v when simulating
// the core, spartan3_dmem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module spartan3_dmem(
clka,
ena,
wea,
addra,
dina,
douta);
input clka;
input ena;
input [0 : 0] wea;
input [9 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V3_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3"))
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of spartan3_dmem is "black_box"
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module system_sdram_input_efifo_module (
// inputs:
clk,
rd,
reset,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
)
;
output almost_empty;
output almost_full;
output empty;
output full;
output [ 61: 0] rd_data;
input clk;
input rd;
input reset;
input wr;
input [ 61: 0] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ 1: 0] entries;
reg [ 61: 0] entry_0;
reg [ 61: 0] entry_1;
wire full;
reg rd_address;
reg [ 61: 0] rd_data;
wire [ 1: 0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == 2;
assign almost_full = entries >= 1;
assign empty = entries == 0;
assign almost_empty = entries <= 1;
always @(entry_0 or entry_1 or rd_address)
begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk)
begin
if (reset)
begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end
else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full)
begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty)
begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk)
begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module system_sdram (
// inputs:
az_addr,
az_be_n,
az_cs,
az_data,
az_rd_n,
az_wr_n,
clk,
reset,
// outputs:
za_data,
za_valid,
za_waitrequest,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dq,
zs_dqm,
zs_ras_n,
zs_we_n
)
;
output [ 31: 0] za_data;
output za_valid;
output za_waitrequest;
output [ 12: 0] zs_addr;
output [ 1: 0] zs_ba;
output zs_cas_n;
output zs_cke;
output zs_cs_n;
inout [ 31: 0] zs_dq;
output [ 3: 0] zs_dqm;
output zs_ras_n;
output zs_we_n;
input [ 24: 0] az_addr;
input [ 3: 0] az_be_n;
input az_cs;
input [ 31: 0] az_data;
input az_rd_n;
input az_wr_n;
input clk;
input reset;
wire [ 23: 0] CODE;
reg ack_refresh_request;
reg [ 24: 0] active_addr;
wire [ 1: 0] active_bank;
reg active_cs_n;
reg [ 31: 0] active_data;
reg [ 3: 0] active_dqm;
reg active_rnw;
wire almost_empty;
wire almost_full;
wire bank_match;
wire [ 9: 0] cas_addr;
wire clk_en;
wire [ 3: 0] cmd_all;
wire [ 2: 0] cmd_code;
wire cs_n;
wire csn_decode;
wire csn_match;
wire [ 24: 0] f_addr;
wire [ 1: 0] f_bank;
wire f_cs_n;
wire [ 31: 0] f_data;
wire [ 3: 0] f_dqm;
wire f_empty;
reg f_pop;
wire f_rnw;
wire f_select;
wire [ 61: 0] fifo_read_data;
reg [ 12: 0] i_addr;
reg [ 3: 0] i_cmd;
reg [ 2: 0] i_count;
reg [ 2: 0] i_next;
reg [ 2: 0] i_refs;
reg [ 2: 0] i_state;
reg init_done;
reg [ 12: 0] m_addr /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 1: 0] m_bank /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 3: 0] m_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 2: 0] m_count;
reg [ 31: 0] m_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON" */;
reg [ 3: 0] m_dqm /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 8: 0] m_next;
reg [ 8: 0] m_state;
reg oe /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;
wire pending;
wire rd_strobe;
reg [ 1: 0] rd_valid;
reg [ 11: 0] refresh_counter;
reg refresh_request;
wire rnw_match;
wire row_match;
wire [ 23: 0] txt_code;
reg za_cannotrefresh;
reg [ 31: 0] za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;
reg za_valid;
wire za_waitrequest;
wire [ 12: 0] zs_addr;
wire [ 1: 0] zs_ba;
wire zs_cas_n;
wire zs_cke;
wire zs_cs_n;
wire [ 31: 0] zs_dq;
wire [ 3: 0] zs_dqm;
wire zs_ras_n;
wire zs_we_n;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = m_cmd;
assign zs_addr = m_addr;
assign zs_cke = clk_en;
assign zs_dq = oe?m_data:{32{1'bz}};
assign zs_dqm = m_dqm;
assign zs_ba = m_bank;
assign f_select = f_pop & pending;
assign f_cs_n = 1'b0;
assign cs_n = f_select ? f_cs_n : active_cs_n;
assign csn_decode = cs_n;
assign {f_rnw, f_addr, f_dqm, f_data} = fifo_read_data;
system_sdram_input_efifo_module the_system_sdram_input_efifo_module
(
.almost_empty (almost_empty),
.almost_full (almost_full),
.clk (clk),
.empty (f_empty),
.full (za_waitrequest),
.rd (f_select),
.rd_data (fifo_read_data),
.reset (reset),
.wr ((~az_wr_n | ~az_rd_n) & !za_waitrequest),
.wr_data ({az_wr_n, az_addr, az_wr_n ? 4'b0 : az_be_n, az_data})
);
assign f_bank = {f_addr[24],f_addr[10]};
// Refresh/init counter.
always @(posedge clk)
begin
if (reset)
refresh_counter <= 3000;
else if (refresh_counter == 0)
refresh_counter <= 468;
else
refresh_counter <= refresh_counter - 1'b1;
end
// Refresh request signal.
always @(posedge clk)
begin
if (reset)
refresh_request <= 0;
else if (1)
refresh_request <= ((refresh_counter == 0) | refresh_request) & ~ack_refresh_request & init_done;
end
// Generate an Interrupt if two ref_reqs occur before one ack_refresh_request
always @(posedge clk)
begin
if (reset)
za_cannotrefresh <= 0;
else if (1)
za_cannotrefresh <= (refresh_counter == 0) & refresh_request;
end
// Initialization-done flag.
always @(posedge clk)
begin
if (reset)
init_done <= 0;
else if (1)
init_done <= init_done | (i_state == 3'b101);
end
// **** Init FSM ****
always @(posedge clk)
begin
if (reset)
begin
i_state <= 3'b000;
i_next <= 3'b000;
i_cmd <= 4'b1111;
i_addr <= {13{1'b1}};
i_count <= {3{1'b0}};
end
else
begin
i_addr <= {13{1'b1}};
case (i_state) // synthesis parallel_case full_case
3'b000: begin
i_cmd <= 4'b1111;
i_refs <= 3'b0;
//Wait for refresh count-down after reset
if (refresh_counter == 0)
i_state <= 3'b001;
end // 3'b000
3'b001: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h2};
i_count <= 0;
i_next <= 3'b010;
end // 3'b001
3'b010: begin
i_cmd <= {{1{1'b0}},3'h1};
i_refs <= i_refs + 1'b1;
i_state <= 3'b011;
i_count <= 2;
// Count up init_refresh_commands
if (i_refs == 3'h1)
i_next <= 3'b111;
else
i_next <= 3'b010;
end // 3'b010
3'b011: begin
i_cmd <= {{1{1'b0}},3'h7};
//WAIT til safe to Proceed...
if (i_count > 1)
i_count <= i_count - 1'b1;
else
i_state <= i_next;
end // 3'b011
3'b101: begin
i_state <= 3'b101;
end // 3'b101
3'b111: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h0};
i_addr <= {{3{1'b0}},1'b0,2'b00,3'h2,4'h0};
i_count <= 4;
i_next <= 3'b101;
end // 3'b111
default: begin
i_state <= 3'b000;
end // default
endcase // i_state
end
end
assign active_bank = {active_addr[24],active_addr[10]};
assign csn_match = active_cs_n == f_cs_n;
assign rnw_match = active_rnw == f_rnw;
assign bank_match = active_bank == f_bank;
assign row_match = {active_addr[23 : 11]} == {f_addr[23 : 11]};
assign pending = csn_match && rnw_match && bank_match && row_match && !f_empty;
assign cas_addr = f_select ? { {3{1'b0}},f_addr[9 : 0] } : { {3{1'b0}},active_addr[9 : 0] };
// **** Main FSM ****
always @(posedge clk)
begin
if (reset)
begin
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= 4'b1111;
m_bank <= 2'b00;
m_addr <= 13'b0000000000000;
m_data <= 32'b00000000000000000000000000000000;
m_dqm <= 4'b0000;
m_count <= 3'b000;
ack_refresh_request <= 1'b0;
f_pop <= 1'b0;
oe <= 1'b0;
end
else
begin
f_pop <= 1'b0;
oe <= 1'b0;
case (m_state) // synthesis parallel_case full_case
9'b000000001: begin
//Wait for init-fsm to be done...
if (init_done)
begin
//Hold bus if another cycle ended to arf.
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= 4'b1111;
ack_refresh_request <= 1'b0;
//Wait for a read/write request.
if (refresh_request)
begin
m_state <= 9'b001000000;
m_next <= 9'b010000000;
m_count <= 0;
active_cs_n <= 1'b1;
end
else if (!f_empty)
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
m_state <= 9'b000000010;
end
end
else
begin
m_addr <= i_addr;
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= i_cmd;
end
end // 9'b000000001
9'b000000010: begin
m_state <= 9'b000000100;
m_cmd <= {csn_decode,3'h3};
m_bank <= active_bank;
m_addr <= active_addr[23 : 11];
m_data <= active_data;
m_dqm <= active_dqm;
m_count <= 1;
m_next <= active_rnw ? 9'b000001000 : 9'b000010000;
end // 9'b000000010
9'b000000100: begin
// precharge all if arf, else precharge csn_decode
if (m_next == 9'b010000000)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
m_state <= m_next;
end // 9'b000000100
9'b000001000: begin
m_cmd <= {csn_decode,3'h5};
m_bank <= f_select ? f_bank : active_bank;
m_dqm <= f_select ? f_dqm : active_dqm;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end RD spin cycle if fifo mt
if (~pending & f_pop)
m_cmd <= {csn_decode,3'h7};
m_state <= 9'b100000000;
end
end // 9'b000001000
9'b000010000: begin
m_cmd <= {csn_decode,3'h4};
oe <= 1'b1;
m_data <= f_select ? f_data : active_data;
m_dqm <= f_select ? f_dqm : active_dqm;
m_bank <= f_select ? f_bank : active_bank;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end WR spin cycle if fifo empty
if (~pending & f_pop)
begin
m_cmd <= {csn_decode,3'h7};
oe <= 1'b0;
end
m_state <= 9'b100000000;
end
end // 9'b000010000
9'b000100000: begin
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
begin
m_state <= 9'b001000000;
m_count <= 0;
end
end // 9'b000100000
9'b001000000: begin
m_state <= 9'b000000100;
m_addr <= {13{1'b1}};
// precharge all if arf, else precharge csn_decode
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h2};
else
m_cmd <= {csn_decode,3'h2};
end // 9'b001000000
9'b010000000: begin
ack_refresh_request <= 1'b1;
m_state <= 9'b000000100;
m_cmd <= {{1{1'b0}},3'h1};
m_count <= 2;
m_next <= 9'b000000001;
end // 9'b010000000
9'b100000000: begin
m_cmd <= {csn_decode,3'h7};
//if we need to ARF, bail, else spin
if (refresh_request)
m_state <= 9'b000000001;
else //wait for fifo to have contents
if (!f_empty)
//Are we 'pending' yet?
if (csn_match && rnw_match && bank_match && row_match)
begin
m_state <= f_rnw ? 9'b000001000 : 9'b000010000;
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
else
begin
m_state <= 9'b001000000;
m_next <= 9'b000000001;
m_count <= 0;
end
end // 9'b100000000
// synthesis translate_off
default: begin
m_state <= m_state;
m_cmd <= 4'b1111;
f_pop <= 1'b0;
oe <= 1'b0;
end // default
// synthesis translate_on
endcase // m_state
end
end
assign rd_strobe = m_cmd[2 : 0] == 3'h5;
//Track RD Req's based on cas_latency w/shift reg
always @(posedge clk)
begin
if (reset)
rd_valid <= {2{1'b0}};
else
rd_valid <= (rd_valid << 1) | { {1{1'b0}}, rd_strobe };
end
// Register dq data.
always @(posedge clk)
begin
if (reset)
za_data <= 0;
else
za_data <= zs_dq;
end
// Delay za_valid to match registered data.
always @(posedge clk)
begin
if (reset)
za_valid <= 0;
else if (1)
za_valid <= rd_valid[1];
end
assign cmd_code = m_cmd[2 : 0];
assign cmd_all = m_cmd;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
initial
begin
$write("\n");
$write("This reference design requires a vendor simulation model.\n");
$write("To simulate accesses to SDRAM, you must:\n");
$write(" - Download the vendor model\n");
$write(" - Install the model in the system_sim directory\n");
$write(" - `include the vendor model in the the top-level system file,\n");
$write(" - Instantiate sdram simulation models and wire them to testbench signals\n");
$write(" - Be aware that you may have to disable some timing checks in the vendor model\n");
$write(" (because this simulation is zero-delay based)\n");
$write("\n");
end
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
assign CODE = &(cmd_all|4'h7) ? 24'h494e48 : txt_code;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module JOUST_ROM (
clka,
addra,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [14 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [7 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(3),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("JOUST_ROM.mif"),
.C_INIT_FILE("JOUST_ROM.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(32768),
.C_READ_DEPTH_A(32768),
.C_ADDRA_WIDTH(15),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(32768),
.C_READ_DEPTH_B(32768),
.C_ADDRB_WIDTH(15),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("8"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.326399 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(1'B0),
.addra(addra),
.dina(8'B0),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(15'B0),
.dinb(8'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
// This file has been automatically generated by goFB and should not be edited by hand
// Compiler written by Hammond Pearce and available at github.com/kiwih/goFB
// Verilog support is EXPERIMENTAL ONLY
// This file represents the Basic Function Block for InjectorMotorController
//defines for state names used internally
`define STATE_MoveArmUp 0
`define STATE_Await_Bottle 1
`define STATE_MoveArmDown 2
`define STATE_Await_Pumping 3
module FB_InjectorMotorController
(
input wire clk,
//input events
input wire InjectorArmFinishedMovement_eI,
input wire EmergencyStopChanged_eI,
input wire ConveyorStoppedForInject_eI,
input wire PumpFinished_eI,
//output events
output wire StartPump_eO,
output wire InjectDone_eO,
output wire InjectorPositionChanged_eO,
output wire InjectRunning_eO,
//input variables
input wire EmergencyStop_I,
//output variables
output reg [7:0] InjectorPosition_O ,
input reset
);
////BEGIN internal copies of I/O
//input events
wire InjectorArmFinishedMovement;
assign InjectorArmFinishedMovement = InjectorArmFinishedMovement_eI;
wire EmergencyStopChanged;
assign EmergencyStopChanged = EmergencyStopChanged_eI;
wire ConveyorStoppedForInject;
assign ConveyorStoppedForInject = ConveyorStoppedForInject_eI;
wire PumpFinished;
assign PumpFinished = PumpFinished_eI;
//output events
reg StartPump;
assign StartPump_eO = StartPump;
reg InjectDone;
assign InjectDone_eO = InjectDone;
reg InjectorPositionChanged;
assign InjectorPositionChanged_eO = InjectorPositionChanged;
reg InjectRunning;
assign InjectRunning_eO = InjectRunning;
//input variables
reg EmergencyStop ;
//output variables
reg [7:0] InjectorPosition ;
////END internal copies of I/O
////BEGIN internal vars
////END internal vars
//BEGIN STATE variables
reg [1:0] state = `STATE_MoveArmUp;
reg entered = 1'b0;
//END STATE variables
//BEGIN algorithm triggers
reg SetArmDownPosition_alg_en = 1'b0;
reg SetArmUpPosition_alg_en = 1'b0;
//END algorithm triggers
always@(posedge clk) begin
if(reset) begin
//reset state
state = `STATE_MoveArmUp;
//reset I/O registers
StartPump = 1'b0;
InjectDone = 1'b0;
InjectorPositionChanged = 1'b0;
InjectRunning = 1'b0;
EmergencyStop = 0;
InjectorPosition = 0;
//reset internal vars
end else begin
//BEGIN clear output events
StartPump = 1'b0;
InjectDone = 1'b0;
InjectorPositionChanged = 1'b0;
InjectRunning = 1'b0;
//END clear output events
//BEGIN update internal inputs on relevant events
if(EmergencyStopChanged) begin
EmergencyStop = EmergencyStop_I;
end
//END update internal inputs
//BEGIN ecc
entered = 1'b0;
case(state)
`STATE_MoveArmUp: begin
if(InjectorArmFinishedMovement) begin
state = `STATE_Await_Bottle;
entered = 1'b1;
end
end
`STATE_Await_Bottle: begin
if(ConveyorStoppedForInject) begin
state = `STATE_MoveArmDown;
entered = 1'b1;
end
end
`STATE_MoveArmDown: begin
if(InjectorArmFinishedMovement) begin
state = `STATE_Await_Pumping;
entered = 1'b1;
end
end
`STATE_Await_Pumping: begin
if(PumpFinished) begin
state = `STATE_MoveArmUp;
entered = 1'b1;
end
end
default: begin
state = 0;
end
endcase
//END ecc
//BEGIN triggers
SetArmDownPosition_alg_en = 1'b0;
SetArmUpPosition_alg_en = 1'b0;
if(entered) begin
case(state)
`STATE_MoveArmUp: begin
SetArmUpPosition_alg_en = 1'b1;
InjectorPositionChanged = 1'b1;
end
`STATE_Await_Bottle: begin
InjectDone = 1'b1;
end
`STATE_MoveArmDown: begin
SetArmDownPosition_alg_en = 1'b1;
InjectorPositionChanged = 1'b1;
InjectRunning = 1'b1;
end
`STATE_Await_Pumping: begin
StartPump = 1'b1;
end
default: begin
end
endcase
end
//END triggers
//BEGIN algorithms
if(SetArmDownPosition_alg_en) begin
InjectorPosition = 255;
end
if(SetArmUpPosition_alg_en) begin
InjectorPosition = 0;
end
//END algorithms
//BEGIN update external output variables on relevant events
if(InjectorPositionChanged) begin
InjectorPosition_O = InjectorPosition;
end
//END update external output variables
end
end
endmodule |
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_burst_gen #
( parameter
CFG_DWIDTH_RATIO = 4,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_REG_GRANT = 0,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_LOCAL_ID_WIDTH = 10,
CFG_DATA_ID_WIDTH = 10,
CFG_INT_SIZE_WIDTH = 4,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_ENABLE_BURST_INTERRUPT = 0,
CFG_ENABLE_BURST_TERMINATE = 0,
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_TCCD = 4,
CFG_ENABLE_BURST_GEN_OUTPUT_REG = 0
)
(
ctl_clk,
ctl_reset_n,
// MMR Interface
cfg_type,
cfg_burst_length,
cfg_tccd,
// Arbiter Interface
arb_do_write,
arb_do_read,
arb_do_burst_chop,
arb_do_burst_terminate,
arb_do_auto_precharge,
arb_do_rmw_correct,
arb_do_rmw_partial,
arb_do_activate,
arb_do_precharge,
arb_do_precharge_all,
arb_do_refresh,
arb_do_self_refresh,
arb_do_power_down,
arb_do_deep_pdown,
arb_do_zq_cal,
arb_do_lmr,
arb_to_chipsel,
arb_to_chip,
arb_to_bank,
arb_to_row,
arb_to_col,
arb_localid,
arb_dataid,
arb_size,
// AFI Interface
bg_do_write_combi,
bg_do_read_combi,
bg_do_burst_chop_combi,
bg_do_burst_terminate_combi,
bg_do_activate_combi,
bg_do_precharge_combi,
bg_to_chip_combi,
bg_effective_size_combi,
bg_interrupt_ready_combi,
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_burst_terminate,
bg_do_auto_precharge,
bg_do_rmw_correct,
bg_do_rmw_partial,
bg_do_activate,
bg_do_precharge,
bg_do_precharge_all,
bg_do_refresh,
bg_do_self_refresh,
bg_do_power_down,
bg_do_deep_pdown,
bg_do_zq_cal,
bg_do_lmr,
bg_to_chipsel,
bg_to_chip,
bg_to_bank,
bg_to_row,
bg_to_col,
bg_doing_write,
bg_doing_read,
bg_rdwr_data_valid,
bg_interrupt_ready,
bg_localid,
bg_dataid,
bg_size,
bg_effective_size
);
localparam AFI_INTF_LOW_PHASE = 0;
localparam AFI_INTF_HIGH_PHASE = 1;
input ctl_clk;
input ctl_reset_n;
// MMR Interface
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_TCCD - 1 : 0] cfg_tccd;
// Arbiter Interface
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
input [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
input [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
// AFI Interface
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge_combi;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip_combi;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size_combi;
output bg_interrupt_ready_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] bg_to_chipsel;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
output bg_doing_write;
output bg_doing_read;
output bg_rdwr_data_valid;
output bg_interrupt_ready;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
output [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
// AFI Interface
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] bg_to_chipsel;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
reg bg_doing_write;
reg bg_doing_read;
reg bg_rdwr_data_valid;
reg bg_interrupt_ready;
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
// Burst generation logic
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_size;
reg [CFG_DATA_ID_WIDTH - 1 : 0] int_dataid;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] int_to_col;
reg [2 : 0] int_col_address;
reg [2 : 0] int_address_left;
reg int_do_row_req;
reg int_do_col_req;
reg int_do_rd_req;
reg int_do_wr_req;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_rmw_partial;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] size;
reg [CFG_DATA_ID_WIDTH - 1 : 0] dataid;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] to_col;
reg [2 : 0] col_address;
reg [2 : 0] address_left;
reg do_row_req;
reg do_col_req;
reg do_rd_req;
reg do_wr_req;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_rmw_partial;
reg [3 : 0] max_local_burst_size;
reg [3 : 0] max_local_burst_size_divide_2;
reg [3 : 0] max_local_burst_size_minus_2;
reg [3 : 0] max_local_burst_size_divide_2_and_minus_2;
reg [3 : 0] burst_left;
reg current_valid;
reg delayed_valid;
reg combined_valid;
reg [3 : 0] max_burst_left;
reg delayed_doing;
reg last_is_write;
reg last_is_read;
// Burst interrupt logic
reg [CFG_PORT_WIDTH_TCCD - 2 : 0] n_prefetch;
reg int_allow_interrupt;
reg int_interrupt_ready;
reg int_interrupt_gate;
// Burst terminate logic
reg int_allow_terminate;
reg int_do_burst_terminate;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_effective_size;
reg int_do_req;
reg doing_burst_terminate;
reg terminate_doing;
// RMW Info
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] delayed_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] delayed_do_rmw_partial;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] combined_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] combined_do_rmw_partial;
// Data ID
reg [CFG_DATA_ID_WIDTH - 1 : 0] delayed_dataid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] combined_dataid;
// Column address
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] modified_to_col;
// Common
wire zero = 1'b0;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge_combi;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip_combi;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size_combi;
reg bg_interrupt_ready_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_burst_terminate;
reg doing_write;
reg doing_read;
reg rdwr_data_valid;
reg interrupt_ready;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] effective_size;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Outputs
//
//--------------------------------------------------------------------------------------------------------
// Do signals
generate
if (CFG_ENABLE_BURST_GEN_OUTPUT_REG == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (! ctl_reset_n)
begin
bg_do_write <= 0;
bg_do_read <= 0;
bg_do_auto_precharge <= 0;
bg_do_rmw_correct <= 0;
bg_do_rmw_partial <= 0;
bg_do_activate <= 0;
bg_do_precharge <= 0;
bg_do_precharge_all <= 0;
bg_do_refresh <= 0;
bg_do_self_refresh <= 0;
bg_do_power_down <= 0;
bg_do_deep_pdown <= 0;
bg_do_zq_cal <= 0;
bg_do_lmr <= 0;
bg_to_chip <= 0;
bg_to_chipsel <= 0;
bg_to_bank <= 0;
bg_to_row <= 0;
bg_localid <= 0;
bg_size <= 0;
bg_to_col <= 0;
bg_dataid <= 0;
bg_do_burst_chop <= 0;
bg_do_burst_terminate <= 0;
bg_doing_write <= 0;
bg_doing_read <= 0;
bg_rdwr_data_valid <= 0;
bg_interrupt_ready <= 0;
bg_effective_size <= 0;
end
else
begin
bg_do_write <= arb_do_write;
bg_do_read <= arb_do_read;
bg_do_auto_precharge <= arb_do_auto_precharge;
bg_do_rmw_correct <= combined_do_rmw_correct;
bg_do_rmw_partial <= combined_do_rmw_partial;
bg_do_activate <= arb_do_activate;
bg_do_precharge <= arb_do_precharge;
bg_do_precharge_all <= arb_do_precharge_all;
bg_do_refresh <= arb_do_refresh;
bg_do_self_refresh <= arb_do_self_refresh;
bg_do_power_down <= arb_do_power_down;
bg_do_deep_pdown <= arb_do_deep_pdown;
bg_do_zq_cal <= arb_do_zq_cal;
bg_do_lmr <= arb_do_lmr;
bg_to_chip <= arb_to_chip;
bg_to_chipsel <= arb_to_chipsel;
bg_to_bank <= arb_to_bank;
bg_to_row <= arb_to_row;
bg_localid <= arb_localid;
bg_size <= arb_size;
bg_to_col <= modified_to_col;
bg_dataid <= combined_dataid;
bg_do_burst_chop <= do_burst_chop;
bg_do_burst_terminate <= do_burst_terminate;
bg_doing_write <= doing_write;
bg_doing_read <= doing_read;
bg_rdwr_data_valid <= rdwr_data_valid;
bg_interrupt_ready <= interrupt_ready;
bg_effective_size <= effective_size;
end
end
end
else
begin
always @ (*)
begin
bg_do_write = arb_do_write;
bg_do_read = arb_do_read;
bg_do_auto_precharge = arb_do_auto_precharge;
bg_do_activate = arb_do_activate;
bg_do_precharge = arb_do_precharge;
bg_do_precharge_all = arb_do_precharge_all;
bg_do_refresh = arb_do_refresh;
bg_do_self_refresh = arb_do_self_refresh;
bg_do_power_down = arb_do_power_down;
bg_do_deep_pdown = arb_do_deep_pdown;
bg_do_zq_cal = arb_do_zq_cal;
bg_do_lmr = arb_do_lmr;
bg_to_chip = arb_to_chip;
bg_to_chipsel = arb_to_chipsel;
bg_to_bank = arb_to_bank;
bg_to_row = arb_to_row;
bg_localid = arb_localid;
bg_size = arb_size;
bg_do_burst_chop = do_burst_chop;
bg_do_burst_terminate = do_burst_terminate;
bg_doing_write = doing_write;
bg_doing_read = doing_read;
bg_rdwr_data_valid = rdwr_data_valid;
bg_interrupt_ready = interrupt_ready;
bg_effective_size = effective_size;
end
// To column
always @ (*)
begin
bg_to_col = modified_to_col;
end
// RMW info
always @ (*)
begin
bg_do_rmw_correct = combined_do_rmw_correct;
bg_do_rmw_partial = combined_do_rmw_partial;
end
// Data ID
always @ (*)
begin
bg_dataid = combined_dataid;
end
end
endgenerate
// Regardless whether CFG_ENABLE_BURST_GEN_OUTPUT_REG is 1/0
// following signals (inputs to rank_timer) need to be combi
always @ (*)
begin
bg_do_write_combi = arb_do_write;
bg_do_read_combi = arb_do_read;
bg_do_burst_chop_combi = do_burst_chop;
bg_do_burst_terminate_combi = do_burst_terminate;
bg_do_activate_combi = arb_do_activate;
bg_do_precharge_combi = arb_do_precharge;
bg_to_chip_combi = arb_to_chip;
bg_effective_size_combi = effective_size;
bg_interrupt_ready_combi = interrupt_ready;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Outputs
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Burst Generation Logic
//
// Doing read/write signal will indicate the "FULL" burst duration of a request
// Data Valid signal will indicate "VALID" burst duration of a request
//
// Example: Without address shifting (maximum local burst size of 4)
//
// Clock ____/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
//
// Input Request ----X W R X-----------------X W R X-----------------X W R X-----------------X W R X-----------------------
// Input Column Address [2 : 0] ----X 0 X-----------------X 0 X-----------------X 0 X-----------------X 0 X-----------------------
// Input Size ----X 1 X-----------------X 2 X-----------------X 3 X-----------------X 4 X-----------------------
//
// Output Column Address [2 : 0] ----X 0 X-----------------X 0 X-----------------X 0 X-----------------X 0 X-----------------------
// Output Doing Signal ____/ 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 \_____
// Output Valid Signal ____/ 1 \_________________/ 1 X 2 \___________/ 1 X 2 X 3 \_____/ 1 X 2 X 3 X 4 \_____
//
// Example: With address shifting (maximum local burst size of 4)
//
// Clock ____/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
//
// Input Request ----X W R X-----------------X W R X-----------------X W R X-----------------------
// Input Column Address [2 : 0] ----X 1 X-----------------X 2 X-----------------X 2 X-----------------------
// Input Size ----X 1 X-----------------X 1 X-----------------X 2 X-----------------------
//
// Output Column Address [2 : 0] ----X 0 X-----------------X 0 X-----------------X 0 X-----------------------
// Output Doing Signal ____/ 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 \_____
// Output Valid Signal __________/ 1 \_______________________/ 1 \_________________/ 1 X 2 \_____
// <-----> <-----------> <----------->
// Offset Offset Offset
//
// Example: Burst chop for DDR3 only (maximum local burst size of 4)
//
// Clock ____/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
//
// Input Request ----X W R X-----------------X W R X-----------------X W R X-----------------X W R X-----------------------
// Input Column Address [2 : 0] ----X 0 X-----------------X 1 X-----------------X 2 X-----------------X 3 X-----------------------
// Input Size ----X 1 X-----------------X 1 X-----------------X 1 X-----------------X 1 X-----------------------
//
// Output Column Address [2 : 0] ----X 0 X-----------------X 0 X-----------------X 2 X-----------------X 2 X-----------------------
// Output Burst Chop Signal ____/ 1 \_________________/ 1 \_________________/ 1 \_________________/ 1 \_______________________
// Output Doing Signal ____/ 1 X 2 \___________/ 1 X 2 \___________/ 1 X 2 \___________/ 1 X 2 \_________________
// Output Valid Signal ____/ 1 \_______________________/ 1 \___________/ 1 \_______________________/ 1 \_________________
// <-----> <----->
// Offset Offset
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Maximum local burst size
//----------------------------------------------------------------------------------------------------
// Calculate maximum local burst size
// based on burst length and controller rate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size <= 0;
end
else
begin
max_local_burst_size <= cfg_burst_length / CFG_DWIDTH_RATIO;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size_divide_2 <= 0;
max_local_burst_size_minus_2 <= 0;
max_local_burst_size_divide_2_and_minus_2 <= 0;
end
else
begin
max_local_burst_size_divide_2 <= max_local_burst_size / 2;
max_local_burst_size_minus_2 <= max_local_burst_size - 2'd2;
max_local_burst_size_divide_2_and_minus_2 <= (max_local_burst_size / 2) - 2'd2;
end
end
//----------------------------------------------------------------------------------------------------
// Address shifting
//----------------------------------------------------------------------------------------------------
// Column address
// we only require address [2 - 0] because the maximum supported
// local burst count is 8 which is BL of 16 in full rate
// we only take low phase of arb_to_col address because high and low phase is identical
always @ (*)
begin
int_col_address = 0;
if (cfg_type == `MMR_TYPE_DDR3 && do_burst_chop) // DDR3 and burst chop, we don't want address shifting during burst chop
begin
if (max_local_burst_size [2]) // max local burst of 4
int_col_address [0 ] = arb_to_col [(CFG_DWIDTH_RATIO / 2)];
else
// max local burst of 1, 2 - address shifting in burst chop is not possible
// max local burst of 8 - not supported in DDR3, there is no BL 16 support in DDR3
int_col_address = 0;
end
else if (max_local_burst_size [0]) // max local burst of 1
int_col_address = 0;
else if (max_local_burst_size [1]) // max local burst of 2
int_col_address [0 ] = arb_to_col [(CFG_DWIDTH_RATIO / 2)];
else if (max_local_burst_size [2]) // max local burst of 4
int_col_address [1 : 0] = arb_to_col [(CFG_DWIDTH_RATIO / 2) + 1 : (CFG_DWIDTH_RATIO / 2)];
else if (max_local_burst_size [3]) // max local burst of 8
int_col_address [2 : 0] = arb_to_col [(CFG_DWIDTH_RATIO / 2) + 2 : (CFG_DWIDTH_RATIO / 2)];
end
always @ (*)
begin
col_address = int_col_address;
end
//----------------------------------------------------------------------------------------------------
// Command Info
//----------------------------------------------------------------------------------------------------
// To col address
always @ (*)
begin
int_to_col = arb_to_col;
end
// Row request
always @ (*)
begin
int_do_row_req = (|arb_do_activate) | (|arb_do_precharge);
end
// Column request
always @ (*)
begin
int_do_col_req = (|arb_do_write) | (|arb_do_read);
end
// Read and write request
always @ (*)
begin
int_do_rd_req = |arb_do_read;
int_do_wr_req = |arb_do_write;
end
// Burst chop
always @ (*)
begin
int_do_burst_chop = arb_do_burst_chop;
end
// RMW info
always @ (*)
begin
int_do_rmw_correct = arb_do_rmw_correct;
int_do_rmw_partial = arb_do_rmw_partial;
end
// Other Info: size, dataid
always @ (*)
begin
int_size = arb_size;
int_dataid = arb_dataid;
end
always @ (*)
begin
size = int_size;
dataid = int_dataid;
to_col = int_to_col;
do_row_req = int_do_row_req;
do_col_req = int_do_col_req;
do_rd_req = int_do_rd_req;
do_wr_req = int_do_wr_req;
do_burst_chop = int_do_burst_chop;
do_rmw_correct = int_do_rmw_correct;
do_rmw_partial = int_do_rmw_partial;
end
//----------------------------------------------------------------------------------------------------
// Address Count
//----------------------------------------------------------------------------------------------------
// Address counting logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
address_left <= 0;
end
else
begin
if (do_col_req)
begin
if (col_address > 1'b1)
address_left <= col_address - 2'd2;
else
address_left <= 0;
end
else if (address_left != 0)
address_left <= address_left - 1'b1;
end
end
//----------------------------------------------------------------------------------------------------
// Valid Signal
//----------------------------------------------------------------------------------------------------
// Burst counting logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
burst_left <= 0;
end
else
begin
if (do_col_req)
begin
if (col_address == 0) // no shifting required
begin
if (size > 1'b1)
burst_left <= size - 2'd2;
else
burst_left <= 0;
end
else if (col_address == 1'b1) // require shifting
begin
burst_left <= size - 1'b1;
end
else // require shifting
begin
burst_left <= size;
end
end
else if (address_left == 0 && burst_left != 0) // start decreasing only after addres shifting is completed
burst_left <= burst_left - 1'b1;
end
end
// Current valid signal
// when there is a column request and column address is "0"
// valid signal must be asserted along with column request
always @ (*)
begin
if (do_col_req && col_address == 0)
current_valid = 1'b1;
else
current_valid = 1'b0;
end
// Delayed valid signal
// when there is a column request with size larger than "1"
// valid signal will be asserted according to the request size
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_valid <= 0;
end
else
begin
if (do_col_req && ((col_address == 0 && size > 1) || col_address == 1'b1))
delayed_valid <= 1'b1;
else if (address_left == 0 && burst_left > 0)
delayed_valid <= 1'b1;
else
delayed_valid <= 1'b0;
end
end
// Combined valid signal
always @ (*)
begin
combined_valid = current_valid | delayed_valid;
end
// Read write valid signal
always @ (*)
begin
rdwr_data_valid = combined_valid;
end
//----------------------------------------------------------------------------------------------------
// Doing Signal
//----------------------------------------------------------------------------------------------------
// Maximum burst counting logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_burst_left <= 0;
end
else
begin
if (do_col_req)
begin
if (do_burst_chop)
begin
if (max_local_burst_size_divide_2 <= 2)
max_burst_left <= 0;
else
max_burst_left <= max_local_burst_size_divide_2_and_minus_2;
end
else
begin
if (max_local_burst_size <= 2)
max_burst_left <= 0;
else
max_burst_left <= max_local_burst_size_minus_2;
end
end
else if (max_burst_left != 0)
max_burst_left <= max_burst_left - 1'b1;
end
end
// Delayed doing signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_doing <= 0;
end
else
begin
if (do_col_req)
begin
if (max_local_burst_size <= 1'b1) //do not generate delayed_doing if max burst count is 1
delayed_doing <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 2'd2)
delayed_doing <= 1'b0;
else
delayed_doing <= 1'b1;
end
else if (max_burst_left > 0)
delayed_doing <= 1'b1;
else
delayed_doing <= 1'b0;
end
end
// Keep track of last commands
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
last_is_write <= 1'b0;
last_is_read <= 1'b0;
end
else
begin
if (do_wr_req)
begin
last_is_write <= 1'b1;
last_is_read <= 1'b0;
end
else if (do_rd_req)
begin
last_is_write <= 1'b0;
last_is_read <= 1'b1;
end
end
end
// Doing write signal
always @ (*)
begin
if (do_rd_req)
doing_write = 1'b0;
else if (do_wr_req)
doing_write = ~terminate_doing;
else if (last_is_write)
doing_write = delayed_doing & ~terminate_doing;
else
doing_write = 1'b0;
end
// Doing read signal
always @ (*)
begin
if (do_wr_req)
doing_read = 1'b0;
else if (do_rd_req)
doing_read = ~terminate_doing;
else if (last_is_read)
doing_read = delayed_doing & ~terminate_doing;
else
doing_read = 1'b0;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Burst Generation Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] RMW Info
//
//--------------------------------------------------------------------------------------------------------
// Registered arb_do_rmw_* signal when there is a coumn request
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_do_rmw_correct <= 0;
delayed_do_rmw_partial <= 0;
end
else
begin
if (do_col_req)
begin
delayed_do_rmw_correct <= do_rmw_correct;
delayed_do_rmw_partial <= do_rmw_partial;
end
end
end
// Prolong RMW information until doing signal is deasserted
always @ (*)
begin
if (do_col_req)
begin
combined_do_rmw_correct = do_rmw_correct;
combined_do_rmw_partial = do_rmw_partial;
end
else if (delayed_doing)
begin
combined_do_rmw_correct = delayed_do_rmw_correct;
combined_do_rmw_partial = delayed_do_rmw_partial;
end
else
begin
combined_do_rmw_correct = 0;
combined_do_rmw_partial = 0;
end
end
//--------------------------------------------------------------------------------------------------------
//
// [START] RMW Info
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Data ID
//
//--------------------------------------------------------------------------------------------------------
// Register data ID when there is a column request
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_dataid <= 0;
end
else
begin
if (do_col_req)
delayed_dataid <= dataid;
end
end
// Prolong data ID information until doing signal is deasserted
always @ (*)
begin
if (do_col_req)
combined_dataid = dataid;
else if (delayed_doing)
combined_dataid = delayed_dataid;
else
combined_dataid = 0;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Data ID
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Column Address
//
//--------------------------------------------------------------------------------------------------------
// Change column address bit [2 : 0]
// see waveform examples in burst generation logic portion
always @ (*)
begin
modified_to_col = to_col;
// During burst chop in DDR3 only, retain original column address
// maximum local burst in DDR3 is 4 which is BL8 in full rate
if (do_burst_chop && cfg_type == `MMR_TYPE_DDR3)
begin
if (max_local_burst_size [1]) // max local burst of 2
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 0 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 0 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [2]) // max local burst of 4
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 1 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 1 : CFG_MEM_IF_COL_WIDTH] = 0;
end
end
else
begin
if (max_local_burst_size [0]) // max local burst of 1
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 0 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 0 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [1]) // max local burst of 2
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 1 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 1 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [2]) // max local burst of 4
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 2 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 2 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [3]) // max local burst of 8
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 3 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 3 : CFG_MEM_IF_COL_WIDTH] = 0;
end
end
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Column Address
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Burst Interrupt
//
// DDR, DDR2, LPDDR and LPDDR2 specific
//
// This logic re-use most of the existing logic in burst generation section (valid signal)
// This signal will be used in rank timer block to gate can_read and can_write signals
//
// Example: (DDR2 full rate, burst length of 8, this will result in maximum local burst of 4)
//
// Clock ____/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
//
// Do Signal ____/ 1 \_________________/ 1 \_________________/ 1 \_________________/ 1 \_______________________
// Doing Signal ____/ 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 \_____
// Valid Signal ____/ 1 \_______________________/ 1 \_______________________/ 1 \_______________________/ 1 \_____
//
// Interrupt Ready (tCCD = 1) / HIGH \_____/ HIGH \___________/ HIGH \_________________/
// Interrupt Ready (tCCD = 2) / HIGH \_____/ HIGH \_____/ HIGH \_________________/ \_________________/
//
//--------------------------------------------------------------------------------------------------------
generate
begin
if (CFG_ENABLE_BURST_INTERRUPT || CFG_ENABLE_BURST_TERMINATE)
begin
// n-prefetch architecture, related tCCD value (only support 1, 2 and 4)
// if tCCD is set to 1, command can be interrupted / terminated at every 2 memory burst boundary (1 memory clock cycle)
// if tCCD is set to 2, command can be interrupted / terminated at every 4 memory burst boundary (2 memory clock cycle)
// if tCCD is set to 4, command can be interrupted / terminated at every 8 memory burst boundary (4 memory clock cycle)
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
n_prefetch <= 0;
end
else
begin
n_prefetch <= cfg_tccd / (CFG_DWIDTH_RATIO / 2);
end
end
end
end
endgenerate
generate
begin
if (CFG_ENABLE_BURST_INTERRUPT)
begin
// For n_prefetch of 0 and 1, we will allow interrupt at any controller clock cycles
// for n_prefetch of n, we will allow interrupt at any n controller clock cycles interval
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_allow_interrupt <= 1'b1;
end
else
begin
if (cfg_type == `MMR_TYPE_DDR3) // DDR3 specific, interrupt masking is handled by setting read-to-read and write-to-write to BL/2
int_allow_interrupt <= 1'b1;
else
begin
if (n_prefetch <= 1) // allow interrupt at any clock cycle
begin
if (do_col_req && ((col_address == 0 && size > 1) || col_address != 0))
int_allow_interrupt <= 1'b0;
else if (address_left == 0 && burst_left == 0)
int_allow_interrupt <= 1'b1;
end
else if (n_prefetch == 2)
begin
if (do_col_req)
int_allow_interrupt <= 1'b0;
else if (address_left == 0 && burst_left == 0 && max_burst_left [0] == 0)
int_allow_interrupt <= 1'b1;
end
else if (n_prefetch == 4)
begin
if (do_col_req)
int_allow_interrupt <= 1'b0;
else if (address_left == 0 && burst_left == 0 && max_burst_left [1 : 0] == 0)
int_allow_interrupt <= 1'b1;
end
end
end
end
always @ (*)
begin
int_interrupt_ready = int_allow_interrupt;
end
end
else
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_interrupt_ready <= 0;
end
else
begin
if (do_col_req)
begin
if (CFG_REG_GRANT)
begin
if (max_local_burst_size <= 2'd2) //do not generate int_interrupt_ready
int_interrupt_ready <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 3'd4)
int_interrupt_ready <= 1'b0;
else
int_interrupt_ready <= 1'b1;
end
else
begin
if (max_local_burst_size <= 1'b1) //do not generate int_interrupt_ready if max burst count is 1
int_interrupt_ready <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 2'd2)
int_interrupt_ready <= 1'b0;
else
int_interrupt_ready <= 1'b1;
end
end
else if (!CFG_REG_GRANT && max_burst_left > 0)
int_interrupt_ready <= 1'b1;
else if ( CFG_REG_GRANT && max_burst_left > 1'b1)
int_interrupt_ready <= 1'b1;
else
int_interrupt_ready <= 1'b0;
end
end
end
end
endgenerate
// Assign to output ports
always @ (*)
begin
interrupt_ready = ~int_interrupt_ready;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Burst Interrupt
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Burst Terminate
//
// LPDDR1 and LPDDR2 specific only
//
//--------------------------------------------------------------------------------------------------------
generate
begin
if (CFG_ENABLE_BURST_TERMINATE)
begin
// For n_prefetch of 0 and 1, we will allow terminate at any controller clock cycles
// for n_prefetch of n, we will allow terminate at any n controller clock cycles interval
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else
begin
if (cfg_type == `MMR_TYPE_LPDDR1 || cfg_type == `MMR_TYPE_LPDDR2) // LPDDR1 and LPDDR2 only
begin
if (n_prefetch <= 1) // allow terminate at any clock cycle
begin
if (do_col_req && col_address != 0)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (do_col_req && col_address == 0 && size == 1'b1)
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else if (address_left == 0 && burst_left == 0 && max_burst_left > 0)
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
else if (n_prefetch == 2)
begin
if (do_col_req)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (address_left == 0 && burst_left == 0 && max_burst_left > 0 && (max_burst_left [0] == 0 || int_allow_terminate == 1'b1))
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
else if (n_prefetch == 4)
begin
if (do_col_req)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (address_left == 0 && burst_left == 0 && max_burst_left > 0 && (max_burst_left [1 : 0] == 0 || int_allow_terminate == 1'b1))
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
end
else
begin
int_allow_terminate <= 1'b0;
end
end
end
// Effective size, actual issued size migh be smaller that maximum local burst size
// we need to inform rank timer about this information for efficient DQ bus turnaround operation
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_effective_size <= 0;
end
else
begin
if (do_col_req)
int_effective_size <= 1'b1;
else if (int_effective_size != {CFG_INT_SIZE_WIDTH{1'b1}})
int_effective_size <= int_effective_size + 1'b1;
end
end
end
else
begin
always @ (*)
begin
int_do_burst_terminate = zero;
end
always @ (*)
begin
int_effective_size = {CFG_INT_SIZE_WIDTH{zero}};
end
end
end
endgenerate
// Terminate doing signal, this signal will be used to mask off doing_read or doing_write signal
// when we issue a burst terminate signal, we should also terminate doing_read and doing_write signal
// to prevent unwanted DQS toggle on the memory interface
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_terminate <= 1'b0;
end
else
begin
if (address_left == 0 && burst_left == 0 && max_burst_left > 0 && ((|do_burst_terminate) == 1'b1 || doing_burst_terminate == 1'b1))
doing_burst_terminate <= 1'b1;
else
doing_burst_terminate <= 1'b0;
end
end
always @ (*)
begin
terminate_doing = (|do_burst_terminate) | doing_burst_terminate;
end
// Burst terminate output ports
// set burst terminate signal to '0' when there is a do_col_req (in half and quarter rate)
// or both do_col_req and do_row_req (full rate) because this indicate there is a incoming command
// any command from arbiter is have higher priority compared to burst terminate command
always @ (*)
begin
if (CFG_DWIDTH_RATIO == 2)
int_do_req = do_col_req | do_row_req;
else
int_do_req = do_col_req;
end
generate
begin
if (CFG_CTL_ARBITER_TYPE == "ROWCOL")
begin
always @ (*)
begin
do_burst_terminate = 0;
if (int_do_req)
do_burst_terminate [AFI_INTF_HIGH_PHASE] = 0;
else
do_burst_terminate [AFI_INTF_HIGH_PHASE] = int_do_burst_terminate;
end
end
else if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
always @ (*)
begin
do_burst_terminate = 0;
if (int_do_req)
do_burst_terminate [AFI_INTF_LOW_PHASE] = 0;
else
do_burst_terminate [AFI_INTF_LOW_PHASE] = int_do_burst_terminate;
end
end
end
endgenerate
// Effective size output ports
always @ (*)
begin
effective_size = int_effective_size;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Burst Terminate
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Burst Chop
//
// DDR3 specific only
//
//--------------------------------------------------------------------------------------------------------
// yyong generate
// yyong begin
// yyong if (CFG_DWIDTH_RATIO == 2)
// yyong begin
// yyong always @ (*)
// yyong begin
// yyong if (cfg_type == `MMR_TYPE_DDR3) // DDR3 only
// yyong begin
// yyong if (arb_size <= 2 && arb_to_col [(CFG_DWIDTH_RATIO / 2)] == 1'b0)
// yyong do_burst_chop = arb_do_write | arb_do_read;
// yyong else if (arb_size == 1)
// yyong do_burst_chop = arb_do_write | arb_do_read;
// yyong else
// yyong do_burst_chop = 0;
// yyong end
// yyong else // Other memory types
// yyong begin
// yyong do_burst_chop = 0;
// yyong end
// yyong end
// yyong end
// yyong else if (CFG_DWIDTH_RATIO == 4)
// yyong begin
// yyong always @ (*)
// yyong begin
// yyong do_burst_chop = 0;
// yyong
// yyong if (cfg_type == `MMR_TYPE_DDR3) // DDR3 only
// yyong begin
// yyong if (arb_size == 1)
// yyong do_burst_chop = arb_do_write | arb_do_read;
// yyong else
// yyong do_burst_chop = 0;
// yyong end
// yyong else // Other memory types
// yyong begin
// yyong do_burst_chop = 0;
// yyong end
// yyong end
// yyong end
// yyong else if (CFG_DWIDTH_RATIO == 8)
// yyong begin
// yyong // Burst chop is not available in quarter rate
// yyong always @ (*)
// yyong begin
// yyong do_burst_chop = {CFG_AFI_INTF_PHASE_NUM{zero}};
// yyong end
// yyong end
// yyong end
// yyong endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Burst Chop
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S2S_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DLYMETAL6S2S_PP_SYMBOL_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlymetal6s2s (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S2S_PP_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:45:00 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_dlmb_v10_0 -prefix
// system_dlmb_v10_0_ system_ilmb_v10_0_sim_netlist.v
// Design : system_ilmb_v10_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* C_EXT_RESET_HIGH = "1" *) (* C_LMB_AWIDTH = "32" *) (* C_LMB_DWIDTH = "32" *)
(* C_LMB_NUM_SLAVES = "1" *)
module system_dlmb_v10_0_lmb_v10
(LMB_Clk,
SYS_Rst,
LMB_Rst,
M_ABus,
M_ReadStrobe,
M_WriteStrobe,
M_AddrStrobe,
M_DBus,
M_BE,
Sl_DBus,
Sl_Ready,
Sl_Wait,
Sl_UE,
Sl_CE,
LMB_ABus,
LMB_ReadStrobe,
LMB_WriteStrobe,
LMB_AddrStrobe,
LMB_ReadDBus,
LMB_WriteDBus,
LMB_Ready,
LMB_Wait,
LMB_UE,
LMB_CE,
LMB_BE);
input LMB_Clk;
input SYS_Rst;
output LMB_Rst;
input [0:31]M_ABus;
input M_ReadStrobe;
input M_WriteStrobe;
input M_AddrStrobe;
input [0:31]M_DBus;
input [0:3]M_BE;
input [0:31]Sl_DBus;
input [0:0]Sl_Ready;
input [0:0]Sl_Wait;
input [0:0]Sl_UE;
input [0:0]Sl_CE;
output [0:31]LMB_ABus;
output LMB_ReadStrobe;
output LMB_WriteStrobe;
output LMB_AddrStrobe;
output [0:31]LMB_ReadDBus;
output [0:31]LMB_WriteDBus;
output LMB_Ready;
output LMB_Wait;
output LMB_UE;
output LMB_CE;
output [0:3]LMB_BE;
wire LMB_Clk;
wire LMB_Rst;
wire [0:31]M_ABus;
wire M_AddrStrobe;
wire [0:3]M_BE;
wire [0:31]M_DBus;
wire M_ReadStrobe;
wire M_WriteStrobe;
wire SYS_Rst;
wire [0:0]Sl_CE;
wire [0:31]Sl_DBus;
wire [0:0]Sl_Ready;
wire [0:0]Sl_UE;
wire [0:0]Sl_Wait;
assign LMB_ABus[0:31] = M_ABus;
assign LMB_AddrStrobe = M_AddrStrobe;
assign LMB_BE[0:3] = M_BE;
assign LMB_CE = Sl_CE;
assign LMB_ReadDBus[0:31] = Sl_DBus;
assign LMB_ReadStrobe = M_ReadStrobe;
assign LMB_Ready = Sl_Ready;
assign LMB_UE = Sl_UE;
assign LMB_Wait = Sl_Wait;
assign LMB_WriteDBus[0:31] = M_DBus;
assign LMB_WriteStrobe = M_WriteStrobe;
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDS" *)
FDSE #(
.INIT(1'b1))
POR_FF_I
(.C(LMB_Clk),
.CE(1'b1),
.D(1'b0),
.Q(LMB_Rst),
.S(SYS_Rst));
endmodule
(* CHECK_LICENSE_TYPE = "system_ilmb_v10_0,lmb_v10,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "lmb_v10,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_dlmb_v10_0
(LMB_Clk,
SYS_Rst,
LMB_Rst,
M_ABus,
M_ReadStrobe,
M_WriteStrobe,
M_AddrStrobe,
M_DBus,
M_BE,
Sl_DBus,
Sl_Ready,
Sl_Wait,
Sl_UE,
Sl_CE,
LMB_ABus,
LMB_ReadStrobe,
LMB_WriteStrobe,
LMB_AddrStrobe,
LMB_ReadDBus,
LMB_WriteDBus,
LMB_Ready,
LMB_Wait,
LMB_UE,
LMB_CE,
LMB_BE);
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK" *) input LMB_Clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST" *) input SYS_Rst;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_M RST" *) output LMB_Rst;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M ABUS" *) input [0:31]M_ABus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE" *) input M_ReadStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE" *) input M_WriteStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE" *) input M_AddrStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS" *) input [0:31]M_DBus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M BE" *) input [0:3]M_BE;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS" *) input [0:31]Sl_DBus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY" *) input [0:0]Sl_Ready;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT" *) input [0:0]Sl_Wait;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE" *) input [0:0]Sl_UE;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE" *) input [0:0]Sl_CE;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS" *) output [0:31]LMB_ABus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE" *) output LMB_ReadStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE" *) output LMB_WriteStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE" *) output LMB_AddrStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M READDBUS" *) output [0:31]LMB_ReadDBus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS" *) output [0:31]LMB_WriteDBus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M READY" *) output LMB_Ready;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M WAIT" *) output LMB_Wait;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M UE" *) output LMB_UE;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_M CE" *) output LMB_CE;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE" *) output [0:3]LMB_BE;
wire [0:31]LMB_ABus;
wire LMB_AddrStrobe;
wire [0:3]LMB_BE;
wire LMB_CE;
wire LMB_Clk;
wire [0:31]LMB_ReadDBus;
wire LMB_ReadStrobe;
wire LMB_Ready;
wire LMB_Rst;
wire LMB_UE;
wire LMB_Wait;
wire [0:31]LMB_WriteDBus;
wire LMB_WriteStrobe;
wire [0:31]M_ABus;
wire M_AddrStrobe;
wire [0:3]M_BE;
wire [0:31]M_DBus;
wire M_ReadStrobe;
wire M_WriteStrobe;
wire SYS_Rst;
wire [0:0]Sl_CE;
wire [0:31]Sl_DBus;
wire [0:0]Sl_Ready;
wire [0:0]Sl_UE;
wire [0:0]Sl_Wait;
(* C_EXT_RESET_HIGH = "1" *)
(* C_LMB_AWIDTH = "32" *)
(* C_LMB_DWIDTH = "32" *)
(* C_LMB_NUM_SLAVES = "1" *)
system_dlmb_v10_0_lmb_v10 U0
(.LMB_ABus(LMB_ABus),
.LMB_AddrStrobe(LMB_AddrStrobe),
.LMB_BE(LMB_BE),
.LMB_CE(LMB_CE),
.LMB_Clk(LMB_Clk),
.LMB_ReadDBus(LMB_ReadDBus),
.LMB_ReadStrobe(LMB_ReadStrobe),
.LMB_Ready(LMB_Ready),
.LMB_Rst(LMB_Rst),
.LMB_UE(LMB_UE),
.LMB_Wait(LMB_Wait),
.LMB_WriteDBus(LMB_WriteDBus),
.LMB_WriteStrobe(LMB_WriteStrobe),
.M_ABus(M_ABus),
.M_AddrStrobe(M_AddrStrobe),
.M_BE(M_BE),
.M_DBus(M_DBus),
.M_ReadStrobe(M_ReadStrobe),
.M_WriteStrobe(M_WriteStrobe),
.SYS_Rst(SYS_Rst),
.Sl_CE(Sl_CE),
.Sl_DBus(Sl_DBus),
.Sl_Ready(Sl_Ready),
.Sl_UE(Sl_UE),
.Sl_Wait(Sl_Wait));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21A_SYMBOL_V
`define SKY130_FD_SC_LS__O21A_SYMBOL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o21a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21A_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4BB_TB_V
`define SKY130_FD_SC_HD__NOR4BB_TB_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor4bb.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C_N = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C_N = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C_N = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C_N = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hd__nor4bb dut (.A(A), .B(B), .C_N(C_N), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4BB_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_MUX_2TO1_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_MUX_2TO1_BLACKBOX_V
/**
* udp_mux_2to1: Two to one multiplexer
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_mux_2to1 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_MUX_2TO1_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr/sky130_fd_sc_hvl__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_hvl__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_V |
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_MATLAB_Function_block.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_MATLAB_Function_block
// Source Path: velocityControlHdl/Sin_Cos1/Mark_Extract_Bits1/MATLAB Function
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_MATLAB_Function_block
(
u,
y
);
input [17:0] u; // ufix18
output [8:0] y; // ufix9
//MATLAB Function 'Sin_Cos/Mark_Extract_Bits1/MATLAB Function': '<S39>:1'
// Non-tunable mask parameter
//'<S39>:1:8'
//'<S39>:1:10'
assign y = u[8:0];
//'<S39>:1:14'
endmodule // velocityControlHdl_MATLAB_Function_block
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:22:07 05/17/2016
// Design Name:
// Module Name: prueba_imagenes
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module prueba_imagenes
(
input wire clk, reset,
output wire hsync,vsync,pic_on,pixel_tick,
output wire [7:0] RGB
);
wire video_on;
wire [9:0] pixel_x, pixel_y;
//reg [11:0] RGB_reg, RGB_next;
timing_generator_VGA instancia_timing_generator_VGA
(
.clk(clk),.reset(reset),
.hsync(hsync),.vsync(vsync),.video_on(video_on),.p_tick(pixel_tick),
.pixel_x(pixel_x), .pixel_y(pixel_y)
);
picture_hora instancia_picture_hora
(
.video_on(video_on),//señal que indica que se encuentra en la región visible de resolución 640x480
.pixel_x(pixel_x), .pixel_y(pixel_y),
.pic_on(pic_on),
.pic_RGB(RGB)
);
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1491173463 : 0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2_BLACKBOX_V
`define SKY130_FD_SC_LP__AND2_BLACKBOX_V
/**
* and2: 2-input AND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2_BLACKBOX_V
|
/*
Execute Module (64-bit, Combined)
*/
`include "ExOp64_3A.v"
`include "ExOp64_3B.v"
module ExOp64_3C(
/* verilator lint_off UNUSED */
clock, reset,
opStepPc, idInGenPc, regOutOK,
regIdRs1, regValRs1, regIdRt1, regValRt1,
regIdRn1, regValRn1, regIdRw1, regValRw1,
immValRi1, opCmd1,
regIdRs2, regValRs2, regIdRt2, regValRt2,
regIdRn2, regValRn2, regIdRw2, regValRw2,
immValRi2, opCmd2,
regIdRs3, regValRs3, regIdRt3, regValRt3,
regIdRn3, regValRn3, regIdRw3, regValRw3,
immValRi3, opCmd3,
regIdRs4, regValRs4, regIdRt4, regValRt4,
regIdRn4, regValRn4, regIdRw4, regValRw4,
immValRi4, opCmd4,
regIdRs5, regValRs5, regIdRt5, regValRt5,
regIdRn5, regValRn5, regIdRw5, regValRw5,
immValRi5, opCmd5,
memAddr, memData,
memLoad, memStore,
memOpMode, memOpCmd2,
ctlInSr, ctlOutSr,
ctlInPr, ctlOutPr,
ctlInPc, ctlOutPc,
ctlInMach, ctlOutMach,
ctlInMacl, ctlOutMacl,
ctlInSp, ctlOutSp,
ctlInGbr, ctlOutGbr,
ctlInVbr, ctlOutVbr,
ctlInSSr, ctlOutSSr,
ctlInSPc, ctlOutSPc,
ctlInSGr, ctlOutSGr
);
input clock;
input reset;
input[3:0] opStepPc;
input[63:0] idInGenPc; //ID's Next PC (Next Fetch)
output[1:0] regOutOK; //execute status
/* Lane 1 */
input[6:0] regIdRs1;
input[6:0] regIdRt1;
input[6:0] regIdRn1;
output[6:0] regIdRw1; //Rn, value to write
input[63:0] regValRs1; //Rs input value
input[63:0] regValRt1; //Rt input value
input[63:0] regValRn1; //Rn input value
output[63:0] regValRw1; //Rn output value
input[63:0] immValRi1; //immediate/disp value
input[7:0] opCmd1; //command opcode
/* Lane 2 */
input[6:0] regIdRs2;
input[6:0] regIdRt2;
input[6:0] regIdRn2;
output[6:0] regIdRw2; //Rn, value to write
input[63:0] regValRs2; //Rs input value
input[63:0] regValRt2; //Rt input value
input[63:0] regValRn2; //Rn input value
output[63:0] regValRw2; //Rn output value
input[63:0] immValRi2; //immediate/disp value
input[7:0] opCmd2; //command opcode
/* Lane 3 */
input[6:0] regIdRs3;
input[6:0] regIdRt3;
input[6:0] regIdRn3;
output[6:0] regIdRw3; //Rn, value to write
input[63:0] regValRs3; //Rs input value
input[63:0] regValRt3; //Rt input value
input[63:0] regValRn3; //Rn input value
output[63:0] regValRw3; //Rn output value
input[63:0] immValRi3; //immediate/disp value
input[7:0] opCmd3; //command opcode
/* Lane 4 */
input[6:0] regIdRs4;
input[6:0] regIdRt4;
input[6:0] regIdRn4;
output[6:0] regIdRw4; //Rn, value to write
input[63:0] regValRs4; //Rs input value
input[63:0] regValRt4; //Rt input value
input[63:0] regValRn4; //Rn input value
output[63:0] regValRw4; //Rn output value
input[63:0] immValRi4; //immediate/disp value
input[7:0] opCmd4; //command opcode
/* Lane 5 */
input[6:0] regIdRs5;
input[6:0] regIdRt5;
input[6:0] regIdRn5;
output[6:0] regIdRw5; //Rn, value to write
input[63:0] regValRs5; //Rs input value
input[63:0] regValRt5; //Rt input value
input[63:0] regValRn5; //Rn input value
output[63:0] regValRw5; //Rn output value
input[63:0] immValRi5; //immediate/disp value
input[7:0] opCmd5; //command opcode
/* Memory */
output[63:0] memAddr; //memory address
output[63:0] memData; //memory data (write)
output memLoad; //load from memory
output memStore; //store to memory
output[4:0] memOpMode; //mem op mode
output[7:0] memOpCmd2; //mem EX chain
/* Special Registers */
input[63:0] ctlInSr; //SR in
input[63:0] ctlInPr; //PR in
input[63:0] ctlInPc; //PC in
output[63:0] ctlOutSr; //SR out
output[63:0] ctlOutPr; //PR out
output[63:0] ctlOutPc; //PC out
input[63:0] ctlInMach; //MACH:MACL in
input[63:0] ctlInMacl; //MACH:MACL in
output[63:0] ctlOutMach; //MACH:MACL out
output[63:0] ctlOutMacl; //MACH:MACL out
input[63:0] ctlInSp; //SP in
output[63:0] ctlOutSp; //SP out
input[63:0] ctlInGbr;
input[63:0] ctlInVbr;
input[63:0] ctlInSSr;
input[63:0] ctlInSPc;
input[63:0] ctlInSGr;
output[63:0] ctlOutGbr;
output[63:0] ctlOutVbr;
output[63:0] ctlOutSSr;
output[63:0] ctlOutSPc;
output[63:0] ctlOutSGr;
wire[1:0] tRegOutOK;
wire[1:0] tRegOutOK1;
wire[1:0] tRegOutOK2;
wire[1:0] tRegOutOK3;
wire[1:0] tRegOutOK4;
wire[1:0] tRegOutOK5;
wire tRegOutHold;
wire tRegOutFault;
assign tRegOutHold =
((tRegOutOK1==UMEM_OK_HOLD) ||
(tRegOutOK2==UMEM_OK_HOLD) ||
(tRegOutOK3==UMEM_OK_HOLD) ||
(tRegOutOK4==UMEM_OK_HOLD) ||
(tRegOutOK5==UMEM_OK_HOLD));
assign tRegOutFault =
((tRegOutOK1==UMEM_OK_FAULT) ||
(tRegOutOK2==UMEM_OK_FAULT) ||
(tRegOutOK3==UMEM_OK_FAULT) ||
(tRegOutOK4==UMEM_OK_FAULT) ||
(tRegOutOK5==UMEM_OK_FAULT));
assign tRegOutOK =
tRegOutHold ? UMEM_OK_HOLD :
tRegOutFault ? UMEM_OK_FAULT :
UMEM_OK_OK;
assign regOutOK = tRegOutOK;
ExOp64_3A ex3a1(
clock, reset,
opCmd1, opStepPc,
regIdRs1, regValRs1,
regIdRt1, regValRt1,
regIdRn1, regValRn1,
immValRi1, idInGenPc,
regIdRw1, regValRw1,
tRegOutOK1,
memAddr, memData,
memLoad, memStore,
memOpMode, memOpCmd2,
ctlInSr, ctlOutSr,
ctlInPr, ctlOutPr,
ctlInPc, ctlOutPc,
ctlInMach, ctlOutMach,
ctlInMacl, ctlOutMacl,
ctlInSp, ctlOutSp,
ctlInGbr, ctlOutGbr,
ctlInVbr, ctlOutVbr,
ctlInSSr, ctlOutSSr,
ctlInSPc, ctlOutSPc,
ctlInSGr, ctlOutSGr
);
ExOp64_3B ex3b2(
clock, reset,
opCmd2, opStepPc,
regIdRs2, regValRs2,
regIdRt2, regValRt2,
regIdRn2, regValRn2,
immValRi2, idInGenPc,
regIdRw2, regValRw2,
tRegOutOK2, ctlInSr);
ExOp64_3B ex3b3(
clock, reset,
opCmd3, opStepPc,
regIdRs3, regValRs3,
regIdRt3, regValRt3,
regIdRn3, regValRn3,
immValRi3, idInGenPc,
regIdRw3, regValRw3,
tRegOutOK3, ctlInSr);
ExOp64_3B ex3b4(
clock, reset,
opCmd4, opStepPc,
regIdRs4, regValRs4,
regIdRt4, regValRt4,
regIdRn4, regValRn4,
immValRi4, idInGenPc,
regIdRw4, regValRw4,
tRegOutOK4, ctlInSr);
ExOp64_3B ex3b5(
clock, reset,
opCmd5, opStepPc,
regIdRs5, regValRs5,
regIdRt5, regValRt5,
regIdRn5, regValRn5,
immValRi5, idInGenPc,
regIdRw5, regValRw5,
tRegOutOK5, ctlInSr);
endmodule
|
//
// ataio.v -- parallel ATA I/O
//
module ata_io (clk, reset,
bus_en, bus_wr, bus_addr, bus_din, bus_dout, bus_wait,
ata_d, ata_a, ata_cs0_n, ata_cs1_n,
ata_dior_n, ata_diow_n, ata_iordy);
input clk;
input reset;
//
input bus_en;
input bus_wr;
input [3:0] bus_addr;
input [15:0] bus_din;
output reg [15:0] bus_dout;
output bus_wait;
//
inout [15:0] ata_d;
output reg [2:0] ata_a;
output reg ata_cs0_n;
output reg ata_cs1_n;
output reg ata_dior_n;
output reg ata_diow_n;
input ata_iordy;
reg [2:0] state;
reg [4:0] delay_counter;
reg ata_d_drive;
assign ata_d = ata_d_drive ? bus_din : 16'bzzzzzzzzzzzzzzzz;
assign bus_wait = bus_en & (state != 3'd5);
always @(posedge clk) begin
if (reset == 1'b1) begin
state <= 3'd0;
delay_counter <= 5'd31;
ata_d_drive <= 1'b0;
ata_a <= 3'b000;
ata_cs0_n <= 1'b1;
ata_cs1_n <= 1'b1;
ata_dior_n <= 1'b1;
ata_diow_n <= 1'b1;
bus_dout <= 16'd0;
end else begin
if (delay_counter == 5'd0) begin
case (state)
// ready - wait for request from the bus
3'd0: begin
if (bus_en & ata_iordy) begin
// assert address and -> state 1, wait 3+1
// address mapping
// 0xxx : control block registers
// 1xxx : command block registers
ata_a[2:0] <= bus_addr[2:0];
ata_cs0_n <= ~bus_addr[3];
ata_cs1_n <= bus_addr[3];
state <= 3'd1;
delay_counter <= 5'd3;
end
end
// assert data-out and RW strobes, then -> state 2, wait 14+1
3'd1: begin
ata_d_drive <= bus_wr;
ata_dior_n <= bus_wr;
ata_diow_n <= ~bus_wr;
state <= 3'd2;
delay_counter <= 5'd14;
end
// de-assert RW strobes and sample data-in,
// then -> state 3, wait 1+1
3'd2: begin
bus_dout <= ata_d;
ata_dior_n <= 1'b1;
ata_diow_n <= 1'b1;
state <= 3'd3;
delay_counter <= 5'd1;
end
// de-assert data and address, then -> state 4, wait 7+1
// (such that 600 ns min cycle time is satisfied)
3'd3: begin
ata_d_drive <= 1'b0;
ata_cs0_n <= 1'b1;
ata_cs1_n <= 1'b1;
state <= 3'd4;
delay_counter <= 5'd7;
end
// auxiliary state, for necessity see comment in state 5
3'd4: begin
state <= 3'd5;
delay_counter <= 5'd0;
end
// finish - used to release bus wait
// WARNING: This state must not be entered with a delay!
// Otherwise bus wait will be released too early and
// subsequent bus cycles will not work properly.
3'd5: begin
state <= 3'd0;
delay_counter <= 5'd0;
end
endcase
end else begin
delay_counter <= delay_counter - 1;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SCHMITTBUF_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__SCHMITTBUF_FUNCTIONAL_V
/**
* schmittbuf: Schmitt Trigger Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__schmittbuf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SCHMITTBUF_FUNCTIONAL_V |
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
// On Tue Jan 22 07:32:43 EST 2013
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wsiS0_SThreadBusy O 1
// wsiS0_SReset_n O 1
// wsiM0_MCmd O 3
// wsiM0_MReqLast O 1
// wsiM0_MBurstPrecise O 1
// wsiM0_MBurstLength O 12
// wsiM0_MData O 32 reg
// wsiM0_MByteEn O 4 reg
// wsiM0_MReqInfo O 8
// wsiM0_MReset_n O 1
// wmemiM0_MCmd O 3 reg
// wmemiM0_MReqLast O 1 reg
// wmemiM0_MAddr O 36 reg
// wmemiM0_MBurstLength O 12 reg
// wmemiM0_MDataValid O 1 reg
// wmemiM0_MDataLast O 1 reg
// wmemiM0_MData O 128 reg
// wmemiM0_MDataByteEn O 16 reg
// wmemiM0_MReset_n O 1
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 32
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
// wsiS0_MCmd I 3
// wsiS0_MBurstLength I 12
// wsiS0_MData I 32
// wsiS0_MByteEn I 4
// wsiS0_MReqInfo I 8
// wmemiM0_SResp I 2
// wmemiM0_SData I 128
// wsiS0_MReqLast I 1
// wsiS0_MBurstPrecise I 1
// wsiS0_MReset_n I 1 reg
// wsiM0_SThreadBusy I 1 reg
// wsiM0_SReset_n I 1 reg
// wmemiM0_SRespLast I 1
// wmemiM0_SCmdAccept I 1
// wmemiM0_SDataAccept I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkDelayWorker4B(wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag,
wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo,
wsiS0_SThreadBusy,
wsiS0_SReset_n,
wsiS0_MReset_n,
wsiM0_MCmd,
wsiM0_MReqLast,
wsiM0_MBurstPrecise,
wsiM0_MBurstLength,
wsiM0_MData,
wsiM0_MByteEn,
wsiM0_MReqInfo,
wsiM0_SThreadBusy,
wsiM0_MReset_n,
wsiM0_SReset_n,
wmemiM0_MCmd,
wmemiM0_MReqLast,
wmemiM0_MAddr,
wmemiM0_MBurstLength,
wmemiM0_MDataValid,
wmemiM0_MDataLast,
wmemiM0_MData,
wmemiM0_MDataByteEn,
wmemiM0_SResp,
wmemiM0_SRespLast,
wmemiM0_SData,
wmemiM0_SCmdAccept,
wmemiM0_SDataAccept,
wmemiM0_MReset_n);
parameter [31 : 0] dlyCtrlInit = 32'b0;
parameter [0 : 0] hasDebugLogic = 1'b0;
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [31 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// action method wsiS0_mCmd
input [2 : 0] wsiS0_MCmd;
// action method wsiS0_mReqLast
input wsiS0_MReqLast;
// action method wsiS0_mBurstPrecise
input wsiS0_MBurstPrecise;
// action method wsiS0_mBurstLength
input [11 : 0] wsiS0_MBurstLength;
// action method wsiS0_mData
input [31 : 0] wsiS0_MData;
// action method wsiS0_mByteEn
input [3 : 0] wsiS0_MByteEn;
// action method wsiS0_mReqInfo
input [7 : 0] wsiS0_MReqInfo;
// action method wsiS0_mDataInfo
// value method wsiS0_sThreadBusy
output wsiS0_SThreadBusy;
// value method wsiS0_sReset_n
output wsiS0_SReset_n;
// action method wsiS0_mReset_n
input wsiS0_MReset_n;
// value method wsiM0_mCmd
output [2 : 0] wsiM0_MCmd;
// value method wsiM0_mReqLast
output wsiM0_MReqLast;
// value method wsiM0_mBurstPrecise
output wsiM0_MBurstPrecise;
// value method wsiM0_mBurstLength
output [11 : 0] wsiM0_MBurstLength;
// value method wsiM0_mData
output [31 : 0] wsiM0_MData;
// value method wsiM0_mByteEn
output [3 : 0] wsiM0_MByteEn;
// value method wsiM0_mReqInfo
output [7 : 0] wsiM0_MReqInfo;
// value method wsiM0_mDataInfo
// action method wsiM0_sThreadBusy
input wsiM0_SThreadBusy;
// value method wsiM0_mReset_n
output wsiM0_MReset_n;
// action method wsiM0_sReset_n
input wsiM0_SReset_n;
// value method wmemiM0_mCmd
output [2 : 0] wmemiM0_MCmd;
// value method wmemiM0_mReqLast
output wmemiM0_MReqLast;
// value method wmemiM0_mAddr
output [35 : 0] wmemiM0_MAddr;
// value method wmemiM0_mBurstLength
output [11 : 0] wmemiM0_MBurstLength;
// value method wmemiM0_mDataValid
output wmemiM0_MDataValid;
// value method wmemiM0_mDataLast
output wmemiM0_MDataLast;
// value method wmemiM0_mData
output [127 : 0] wmemiM0_MData;
// value method wmemiM0_mDataByteEn
output [15 : 0] wmemiM0_MDataByteEn;
// action method wmemiM0_sResp
input [1 : 0] wmemiM0_SResp;
// action method wmemiM0_sRespLast
input wmemiM0_SRespLast;
// action method wmemiM0_sData
input [127 : 0] wmemiM0_SData;
// action method wmemiM0_sCmdAccept
input wmemiM0_SCmdAccept;
// action method wmemiM0_sDataAccept
input wmemiM0_SDataAccept;
// value method wmemiM0_mReset_n
output wmemiM0_MReset_n;
// signals for module outputs
wire [127 : 0] wmemiM0_MData;
wire [35 : 0] wmemiM0_MAddr;
wire [31 : 0] wciS0_SData, wsiM0_MData;
wire [15 : 0] wmemiM0_MDataByteEn;
wire [11 : 0] wmemiM0_MBurstLength, wsiM0_MBurstLength;
wire [7 : 0] wsiM0_MReqInfo;
wire [3 : 0] wsiM0_MByteEn;
wire [2 : 0] wmemiM0_MCmd, wsiM0_MCmd;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy,
wmemiM0_MDataLast,
wmemiM0_MDataValid,
wmemiM0_MReqLast,
wmemiM0_MReset_n,
wsiM0_MBurstPrecise,
wsiM0_MReqLast,
wsiM0_MReset_n,
wsiS0_SReset_n,
wsiS0_SThreadBusy;
// inlined wires
wire [145 : 0] wmemi_dhF_x_wire$wget;
wire [130 : 0] wmemi_wmemiResponse$wget;
wire [127 : 0] wmemi_Em_sData_w$wget;
wire [95 : 0] wsiM_extStatusW$wget, wsiS_extStatusW$wget;
wire [71 : 0] wci_wslv_wciReq$wget;
wire [60 : 0] wsiM_reqFifo_x_wire$wget, wsiS_wsiReq$wget;
wire [51 : 0] wmemi_reqF_x_wire$wget;
wire [33 : 0] wci_wslv_respF_x_wire$wget;
wire [31 : 0] mesgWF_wDataIn$wget,
mesgWF_wDataOut$wget,
wci_wci_Es_mAddr_w$wget,
wci_wci_Es_mData_w$wget,
wsi_Es_mData_w$wget;
wire [24 : 0] dlyWordsStored_acc_v1$wget, dlyWordsStored_acc_v2$wget;
wire [15 : 0] dlyReadyToWrite_acc_v1$wget, dlyReadyToWrite_acc_v2$wget;
wire [11 : 0] wsi_Es_mBurstLength_w$wget;
wire [7 : 0] dlyReadCredit_acc_v1$wget,
dlyReadCredit_acc_v2$wget,
wsi_Es_mReqInfo_w$wget;
wire [3 : 0] wci_wci_Es_mByteEn_w$wget, wsi_Es_mByteEn_w$wget;
wire [2 : 0] wci_wci_Es_mCmd_w$wget,
wci_wslv_wEdge$wget,
wsi_Es_mCmd_w$wget;
wire [1 : 0] wmemi_Em_sResp_w$wget;
wire dlyReadCredit_acc_v1$whas,
dlyReadCredit_acc_v2$whas,
dlyReadyToWrite_acc_v1$whas,
dlyReadyToWrite_acc_v2$whas,
dlyWordsStored_acc_v1$whas,
dlyWordsStored_acc_v2$whas,
mesgWF_pwDequeue$whas,
mesgWF_pwEnqueue$whas,
mesgWF_wDataIn$whas,
mesgWF_wDataOut$whas,
wci_wci_Es_mAddrSpace_w$wget,
wci_wci_Es_mAddrSpace_w$whas,
wci_wci_Es_mAddr_w$whas,
wci_wci_Es_mByteEn_w$whas,
wci_wci_Es_mCmd_w$whas,
wci_wci_Es_mData_w$whas,
wci_wslv_ctlAckReg_1$wget,
wci_wslv_ctlAckReg_1$whas,
wci_wslv_reqF_r_clr$whas,
wci_wslv_reqF_r_deq$whas,
wci_wslv_reqF_r_enq$whas,
wci_wslv_respF_dequeueing$whas,
wci_wslv_respF_enqueueing$whas,
wci_wslv_respF_x_wire$whas,
wci_wslv_sFlagReg_1$wget,
wci_wslv_sFlagReg_1$whas,
wci_wslv_sThreadBusy_pw$whas,
wci_wslv_wEdge$whas,
wci_wslv_wciReq$whas,
wci_wslv_wci_cfrd_pw$whas,
wci_wslv_wci_cfwr_pw$whas,
wci_wslv_wci_ctrl_pw$whas,
wmemi_Em_sData_w$whas,
wmemi_Em_sRespLast_w$whas,
wmemi_Em_sResp_w$whas,
wmemi_dhF_dequeueing$whas,
wmemi_dhF_enqueueing$whas,
wmemi_dhF_x_wire$whas,
wmemi_operateD_1$wget,
wmemi_operateD_1$whas,
wmemi_peerIsReady_1$wget,
wmemi_peerIsReady_1$whas,
wmemi_reqF_dequeueing$whas,
wmemi_reqF_enqueueing$whas,
wmemi_reqF_x_wire$whas,
wmemi_sCmdAccept_w$wget,
wmemi_sCmdAccept_w$whas,
wmemi_sDataAccept_w$wget,
wmemi_sDataAccept_w$whas,
wmemi_wmemiResponse$whas,
wsiM_operateD_1$wget,
wsiM_operateD_1$whas,
wsiM_peerIsReady_1$wget,
wsiM_peerIsReady_1$whas,
wsiM_reqFifo_dequeueing$whas,
wsiM_reqFifo_enqueueing$whas,
wsiM_reqFifo_x_wire$whas,
wsiM_sThreadBusy_pw$whas,
wsiS_operateD_1$wget,
wsiS_operateD_1$whas,
wsiS_peerIsReady_1$wget,
wsiS_peerIsReady_1$whas,
wsiS_reqFifo_doResetClr$whas,
wsiS_reqFifo_doResetDeq$whas,
wsiS_reqFifo_doResetEnq$whas,
wsiS_reqFifo_r_clr$whas,
wsiS_reqFifo_r_deq$whas,
wsiS_reqFifo_r_enq$whas,
wsiS_sThreadBusy_dw$wget,
wsiS_sThreadBusy_dw$whas,
wsiS_wsiReq$whas,
wsi_Es_mBurstLength_w$whas,
wsi_Es_mBurstPrecise_w$whas,
wsi_Es_mByteEn_w$whas,
wsi_Es_mCmd_w$whas,
wsi_Es_mDataInfo_w$whas,
wsi_Es_mData_w$whas,
wsi_Es_mReqInfo_w$whas,
wsi_Es_mReqLast_w$whas;
// register bytesRead
reg [31 : 0] bytesRead;
wire [31 : 0] bytesRead$D_IN;
wire bytesRead$EN;
// register bytesThisMessage
reg [23 : 0] bytesThisMessage;
wire [23 : 0] bytesThisMessage$D_IN;
wire bytesThisMessage$EN;
// register bytesWritten
reg [31 : 0] bytesWritten;
wire [31 : 0] bytesWritten$D_IN;
wire bytesWritten$EN;
// register cyclesPassed
reg [31 : 0] cyclesPassed;
wire [31 : 0] cyclesPassed$D_IN;
wire cyclesPassed$EN;
// register dlyCtrl
reg [31 : 0] dlyCtrl;
wire [31 : 0] dlyCtrl$D_IN;
wire dlyCtrl$EN;
// register dlyHoldoffBytes
reg [31 : 0] dlyHoldoffBytes;
wire [31 : 0] dlyHoldoffBytes$D_IN;
wire dlyHoldoffBytes$EN;
// register dlyHoldoffCycles
reg [31 : 0] dlyHoldoffCycles;
wire [31 : 0] dlyHoldoffCycles$D_IN;
wire dlyHoldoffCycles$EN;
// register dlyRAG
reg [22 : 0] dlyRAG;
wire [22 : 0] dlyRAG$D_IN;
wire dlyRAG$EN;
// register dlyRdOpOther
reg [31 : 0] dlyRdOpOther;
wire [31 : 0] dlyRdOpOther$D_IN;
wire dlyRdOpOther$EN;
// register dlyRdOpZero
reg [31 : 0] dlyRdOpZero;
wire [31 : 0] dlyRdOpZero$D_IN;
wire dlyRdOpZero$EN;
// register dlyReadCredit_value
reg [7 : 0] dlyReadCredit_value;
wire [7 : 0] dlyReadCredit_value$D_IN;
wire dlyReadCredit_value$EN;
// register dlyReadyToWrite_value
reg [15 : 0] dlyReadyToWrite_value;
wire [15 : 0] dlyReadyToWrite_value$D_IN;
wire dlyReadyToWrite_value$EN;
// register dlyWAG
reg [22 : 0] dlyWAG;
wire [22 : 0] dlyWAG$D_IN;
wire dlyWAG$EN;
// register dlyWordsStored_value
reg [24 : 0] dlyWordsStored_value;
wire [24 : 0] dlyWordsStored_value$D_IN;
wire dlyWordsStored_value$EN;
// register mesgLengthSoFar
reg [13 : 0] mesgLengthSoFar;
wire [13 : 0] mesgLengthSoFar$D_IN;
wire mesgLengthSoFar$EN;
// register mesgRdCount
reg [31 : 0] mesgRdCount;
wire [31 : 0] mesgRdCount$D_IN;
wire mesgRdCount$EN;
// register mesgWF_rCache
reg [45 : 0] mesgWF_rCache;
wire [45 : 0] mesgWF_rCache$D_IN;
wire mesgWF_rCache$EN;
// register mesgWF_rRdPtr
reg [12 : 0] mesgWF_rRdPtr;
wire [12 : 0] mesgWF_rRdPtr$D_IN;
wire mesgWF_rRdPtr$EN;
// register mesgWF_rWrPtr
reg [12 : 0] mesgWF_rWrPtr;
wire [12 : 0] mesgWF_rWrPtr$D_IN;
wire mesgWF_rWrPtr$EN;
// register mesgWtCount
reg [31 : 0] mesgWtCount;
wire [31 : 0] mesgWtCount$D_IN;
wire mesgWtCount$EN;
// register rdSerAddr
reg [31 : 0] rdSerAddr;
wire [31 : 0] rdSerAddr$D_IN;
wire rdSerAddr$EN;
// register rdSerEmpty
reg rdSerEmpty;
wire rdSerEmpty$D_IN, rdSerEmpty$EN;
// register rdSerMeta
reg [31 : 0] rdSerMeta;
wire [31 : 0] rdSerMeta$D_IN;
wire rdSerMeta$EN;
// register rdSerPos
reg [1 : 0] rdSerPos;
wire [1 : 0] rdSerPos$D_IN;
wire rdSerPos$EN;
// register rdSerStage
reg [31 : 0] rdSerStage;
wire [31 : 0] rdSerStage$D_IN;
wire rdSerStage$EN;
// register rdSerStage_1
reg [31 : 0] rdSerStage_1;
wire [31 : 0] rdSerStage_1$D_IN;
wire rdSerStage_1$EN;
// register rdSerStage_2
reg [31 : 0] rdSerStage_2;
wire [31 : 0] rdSerStage_2$D_IN;
wire rdSerStage_2$EN;
// register rdSerStage_3
reg [31 : 0] rdSerStage_3;
wire [31 : 0] rdSerStage_3$D_IN;
wire rdSerStage_3$EN;
// register rdSerUnroll
reg [15 : 0] rdSerUnroll;
wire [15 : 0] rdSerUnroll$D_IN;
wire rdSerUnroll$EN;
// register rdSyncWord
reg rdSyncWord;
reg rdSyncWord$D_IN;
wire rdSyncWord$EN;
// register readMeta
reg [31 : 0] readMeta;
wire [31 : 0] readMeta$D_IN;
wire readMeta$EN;
// register tog50
reg tog50;
wire tog50$D_IN, tog50$EN;
// register unrollCnt
reg [15 : 0] unrollCnt;
wire [15 : 0] unrollCnt$D_IN;
wire unrollCnt$EN;
// register wci_wslv_cEdge
reg [2 : 0] wci_wslv_cEdge;
wire [2 : 0] wci_wslv_cEdge$D_IN;
wire wci_wslv_cEdge$EN;
// register wci_wslv_cState
reg [2 : 0] wci_wslv_cState;
wire [2 : 0] wci_wslv_cState$D_IN;
wire wci_wslv_cState$EN;
// register wci_wslv_ctlAckReg
reg wci_wslv_ctlAckReg;
wire wci_wslv_ctlAckReg$D_IN, wci_wslv_ctlAckReg$EN;
// register wci_wslv_ctlOpActive
reg wci_wslv_ctlOpActive;
wire wci_wslv_ctlOpActive$D_IN, wci_wslv_ctlOpActive$EN;
// register wci_wslv_illegalEdge
reg wci_wslv_illegalEdge;
wire wci_wslv_illegalEdge$D_IN, wci_wslv_illegalEdge$EN;
// register wci_wslv_isReset_isInReset
reg wci_wslv_isReset_isInReset;
wire wci_wslv_isReset_isInReset$D_IN, wci_wslv_isReset_isInReset$EN;
// register wci_wslv_nState
reg [2 : 0] wci_wslv_nState;
reg [2 : 0] wci_wslv_nState$D_IN;
wire wci_wslv_nState$EN;
// register wci_wslv_reqF_countReg
reg [1 : 0] wci_wslv_reqF_countReg;
wire [1 : 0] wci_wslv_reqF_countReg$D_IN;
wire wci_wslv_reqF_countReg$EN;
// register wci_wslv_respF_c_r
reg [1 : 0] wci_wslv_respF_c_r;
wire [1 : 0] wci_wslv_respF_c_r$D_IN;
wire wci_wslv_respF_c_r$EN;
// register wci_wslv_respF_q_0
reg [33 : 0] wci_wslv_respF_q_0;
reg [33 : 0] wci_wslv_respF_q_0$D_IN;
wire wci_wslv_respF_q_0$EN;
// register wci_wslv_respF_q_1
reg [33 : 0] wci_wslv_respF_q_1;
reg [33 : 0] wci_wslv_respF_q_1$D_IN;
wire wci_wslv_respF_q_1$EN;
// register wci_wslv_sFlagReg
reg wci_wslv_sFlagReg;
wire wci_wslv_sFlagReg$D_IN, wci_wslv_sFlagReg$EN;
// register wci_wslv_sThreadBusy_d
reg wci_wslv_sThreadBusy_d;
wire wci_wslv_sThreadBusy_d$D_IN, wci_wslv_sThreadBusy_d$EN;
// register wmemiRdReq
reg [31 : 0] wmemiRdReq;
wire [31 : 0] wmemiRdReq$D_IN;
wire wmemiRdReq$EN;
// register wmemiRdResp1
reg [31 : 0] wmemiRdResp1;
wire [31 : 0] wmemiRdResp1$D_IN;
wire wmemiRdResp1$EN;
// register wmemiRdResp2
reg [31 : 0] wmemiRdResp2;
wire [31 : 0] wmemiRdResp2$D_IN;
wire wmemiRdResp2$EN;
// register wmemiWrReq
reg [31 : 0] wmemiWrReq;
wire [31 : 0] wmemiWrReq$D_IN;
wire wmemiWrReq$EN;
// register wmemi_busyWithMessage
reg wmemi_busyWithMessage;
wire wmemi_busyWithMessage$D_IN, wmemi_busyWithMessage$EN;
// register wmemi_dhF_c_r
reg [1 : 0] wmemi_dhF_c_r;
wire [1 : 0] wmemi_dhF_c_r$D_IN;
wire wmemi_dhF_c_r$EN;
// register wmemi_dhF_q_0
reg [145 : 0] wmemi_dhF_q_0;
reg [145 : 0] wmemi_dhF_q_0$D_IN;
wire wmemi_dhF_q_0$EN;
// register wmemi_dhF_q_1
reg [145 : 0] wmemi_dhF_q_1;
reg [145 : 0] wmemi_dhF_q_1$D_IN;
wire wmemi_dhF_q_1$EN;
// register wmemi_errorSticky
reg wmemi_errorSticky;
wire wmemi_errorSticky$D_IN, wmemi_errorSticky$EN;
// register wmemi_isReset_isInReset
reg wmemi_isReset_isInReset;
wire wmemi_isReset_isInReset$D_IN, wmemi_isReset_isInReset$EN;
// register wmemi_operateD
reg wmemi_operateD;
wire wmemi_operateD$D_IN, wmemi_operateD$EN;
// register wmemi_peerIsReady
reg wmemi_peerIsReady;
wire wmemi_peerIsReady$D_IN, wmemi_peerIsReady$EN;
// register wmemi_reqF_c_r
reg [1 : 0] wmemi_reqF_c_r;
wire [1 : 0] wmemi_reqF_c_r$D_IN;
wire wmemi_reqF_c_r$EN;
// register wmemi_reqF_q_0
reg [51 : 0] wmemi_reqF_q_0;
reg [51 : 0] wmemi_reqF_q_0$D_IN;
wire wmemi_reqF_q_0$EN;
// register wmemi_reqF_q_1
reg [51 : 0] wmemi_reqF_q_1;
reg [51 : 0] wmemi_reqF_q_1$D_IN;
wire wmemi_reqF_q_1$EN;
// register wmemi_statusR
reg [7 : 0] wmemi_statusR;
wire [7 : 0] wmemi_statusR$D_IN;
wire wmemi_statusR$EN;
// register wmemi_trafficSticky
reg wmemi_trafficSticky;
wire wmemi_trafficSticky$D_IN, wmemi_trafficSticky$EN;
// register wrtSerAddr
reg [31 : 0] wrtSerAddr;
wire [31 : 0] wrtSerAddr$D_IN;
wire wrtSerAddr$EN;
// register wrtSerPos
reg [1 : 0] wrtSerPos;
wire [1 : 0] wrtSerPos$D_IN;
wire wrtSerPos$EN;
// register wrtSerStage
reg [31 : 0] wrtSerStage;
wire [31 : 0] wrtSerStage$D_IN;
wire wrtSerStage$EN;
// register wrtSerStage_1
reg [31 : 0] wrtSerStage_1;
wire [31 : 0] wrtSerStage_1$D_IN;
wire wrtSerStage_1$EN;
// register wrtSerStage_2
reg [31 : 0] wrtSerStage_2;
wire [31 : 0] wrtSerStage_2$D_IN;
wire wrtSerStage_2$EN;
// register wrtSerStage_3
reg [31 : 0] wrtSerStage_3;
wire [31 : 0] wrtSerStage_3$D_IN;
wire wrtSerStage_3$EN;
// register wrtSerUnroll
reg [15 : 0] wrtSerUnroll;
wire [15 : 0] wrtSerUnroll$D_IN;
wire wrtSerUnroll$EN;
// register wsiM_burstKind
reg [1 : 0] wsiM_burstKind;
wire [1 : 0] wsiM_burstKind$D_IN;
wire wsiM_burstKind$EN;
// register wsiM_errorSticky
reg wsiM_errorSticky;
wire wsiM_errorSticky$D_IN, wsiM_errorSticky$EN;
// register wsiM_iMesgCount
reg [31 : 0] wsiM_iMesgCount;
wire [31 : 0] wsiM_iMesgCount$D_IN;
wire wsiM_iMesgCount$EN;
// register wsiM_isReset_isInReset
reg wsiM_isReset_isInReset;
wire wsiM_isReset_isInReset$D_IN, wsiM_isReset_isInReset$EN;
// register wsiM_operateD
reg wsiM_operateD;
wire wsiM_operateD$D_IN, wsiM_operateD$EN;
// register wsiM_pMesgCount
reg [31 : 0] wsiM_pMesgCount;
wire [31 : 0] wsiM_pMesgCount$D_IN;
wire wsiM_pMesgCount$EN;
// register wsiM_peerIsReady
reg wsiM_peerIsReady;
wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN;
// register wsiM_reqFifo_c_r
reg [1 : 0] wsiM_reqFifo_c_r;
wire [1 : 0] wsiM_reqFifo_c_r$D_IN;
wire wsiM_reqFifo_c_r$EN;
// register wsiM_reqFifo_q_0
reg [60 : 0] wsiM_reqFifo_q_0;
reg [60 : 0] wsiM_reqFifo_q_0$D_IN;
wire wsiM_reqFifo_q_0$EN;
// register wsiM_reqFifo_q_1
reg [60 : 0] wsiM_reqFifo_q_1;
reg [60 : 0] wsiM_reqFifo_q_1$D_IN;
wire wsiM_reqFifo_q_1$EN;
// register wsiM_sThreadBusy_d
reg wsiM_sThreadBusy_d;
wire wsiM_sThreadBusy_d$D_IN, wsiM_sThreadBusy_d$EN;
// register wsiM_statusR
reg [7 : 0] wsiM_statusR;
wire [7 : 0] wsiM_statusR$D_IN;
wire wsiM_statusR$EN;
// register wsiM_tBusyCount
reg [31 : 0] wsiM_tBusyCount;
wire [31 : 0] wsiM_tBusyCount$D_IN;
wire wsiM_tBusyCount$EN;
// register wsiM_trafficSticky
reg wsiM_trafficSticky;
wire wsiM_trafficSticky$D_IN, wsiM_trafficSticky$EN;
// register wsiS_burstKind
reg [1 : 0] wsiS_burstKind;
wire [1 : 0] wsiS_burstKind$D_IN;
wire wsiS_burstKind$EN;
// register wsiS_errorSticky
reg wsiS_errorSticky;
wire wsiS_errorSticky$D_IN, wsiS_errorSticky$EN;
// register wsiS_iMesgCount
reg [31 : 0] wsiS_iMesgCount;
wire [31 : 0] wsiS_iMesgCount$D_IN;
wire wsiS_iMesgCount$EN;
// register wsiS_isReset_isInReset
reg wsiS_isReset_isInReset;
wire wsiS_isReset_isInReset$D_IN, wsiS_isReset_isInReset$EN;
// register wsiS_mesgWordLength
reg [11 : 0] wsiS_mesgWordLength;
wire [11 : 0] wsiS_mesgWordLength$D_IN;
wire wsiS_mesgWordLength$EN;
// register wsiS_operateD
reg wsiS_operateD;
wire wsiS_operateD$D_IN, wsiS_operateD$EN;
// register wsiS_pMesgCount
reg [31 : 0] wsiS_pMesgCount;
wire [31 : 0] wsiS_pMesgCount$D_IN;
wire wsiS_pMesgCount$EN;
// register wsiS_peerIsReady
reg wsiS_peerIsReady;
wire wsiS_peerIsReady$D_IN, wsiS_peerIsReady$EN;
// register wsiS_reqFifo_countReg
reg [1 : 0] wsiS_reqFifo_countReg;
wire [1 : 0] wsiS_reqFifo_countReg$D_IN;
wire wsiS_reqFifo_countReg$EN;
// register wsiS_reqFifo_levelsValid
reg wsiS_reqFifo_levelsValid;
wire wsiS_reqFifo_levelsValid$D_IN, wsiS_reqFifo_levelsValid$EN;
// register wsiS_statusR
reg [7 : 0] wsiS_statusR;
wire [7 : 0] wsiS_statusR$D_IN;
wire wsiS_statusR$EN;
// register wsiS_tBusyCount
reg [31 : 0] wsiS_tBusyCount;
wire [31 : 0] wsiS_tBusyCount$D_IN;
wire wsiS_tBusyCount$EN;
// register wsiS_trafficSticky
reg wsiS_trafficSticky;
wire wsiS_trafficSticky$D_IN, wsiS_trafficSticky$EN;
// register wsiS_wordCount
reg [11 : 0] wsiS_wordCount;
wire [11 : 0] wsiS_wordCount$D_IN;
wire wsiS_wordCount$EN;
// ports of submodule mesgRF
wire [31 : 0] mesgRF$D_IN, mesgRF$D_OUT;
wire mesgRF$CLR, mesgRF$DEQ, mesgRF$EMPTY_N, mesgRF$ENQ, mesgRF$FULL_N;
// ports of submodule mesgWF_memory
wire [31 : 0] mesgWF_memory$DIA, mesgWF_memory$DIB, mesgWF_memory$DOB;
wire [11 : 0] mesgWF_memory$ADDRA, mesgWF_memory$ADDRB;
wire mesgWF_memory$ENA,
mesgWF_memory$ENB,
mesgWF_memory$WEA,
mesgWF_memory$WEB;
// ports of submodule metaRF
wire [31 : 0] metaRF$D_IN, metaRF$D_OUT;
wire metaRF$CLR, metaRF$DEQ, metaRF$EMPTY_N, metaRF$ENQ, metaRF$FULL_N;
// ports of submodule metaWF
wire [31 : 0] metaWF$D_IN, metaWF$D_OUT;
wire metaWF$CLR, metaWF$DEQ, metaWF$EMPTY_N, metaWF$ENQ, metaWF$FULL_N;
// ports of submodule wci_wslv_reqF
wire [71 : 0] wci_wslv_reqF$D_IN, wci_wslv_reqF$D_OUT;
wire wci_wslv_reqF$CLR,
wci_wslv_reqF$DEQ,
wci_wslv_reqF$EMPTY_N,
wci_wslv_reqF$ENQ;
// ports of submodule wide16Fa
wire [127 : 0] wide16Fa$D_IN, wide16Fa$D_OUT;
wire wide16Fa$CLR,
wide16Fa$DEQ,
wide16Fa$EMPTY_N,
wide16Fa$ENQ,
wide16Fa$FULL_N;
// ports of submodule wide16Fb
wire [127 : 0] wide16Fb$D_IN, wide16Fb$D_OUT;
wire wide16Fb$CLR,
wide16Fb$DEQ,
wide16Fb$EMPTY_N,
wide16Fb$ENQ,
wide16Fb$FULL_N;
// ports of submodule wide16Fc
wire [127 : 0] wide16Fc$D_IN, wide16Fc$D_OUT;
wire wide16Fc$CLR,
wide16Fc$DEQ,
wide16Fc$EMPTY_N,
wide16Fc$ENQ,
wide16Fc$FULL_N;
// ports of submodule wmemi_respF
wire [130 : 0] wmemi_respF$D_IN, wmemi_respF$D_OUT;
wire wmemi_respF$CLR,
wmemi_respF$DEQ,
wmemi_respF$EMPTY_N,
wmemi_respF$ENQ,
wmemi_respF$FULL_N;
// ports of submodule wsiS_reqFifo
wire [60 : 0] wsiS_reqFifo$D_IN, wsiS_reqFifo$D_OUT;
wire wsiS_reqFifo$CLR,
wsiS_reqFifo$DEQ,
wsiS_reqFifo$EMPTY_N,
wsiS_reqFifo$ENQ,
wsiS_reqFifo$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_delay_read_req,
WILL_FIRE_RL_delay_read_req,
WILL_FIRE_RL_delay_write_req,
WILL_FIRE_RL_rdSer_begin,
WILL_FIRE_RL_rdSer_body,
WILL_FIRE_RL_rdSer_sync,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctrl_EiI,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_wslv_ctl_op_complete,
WILL_FIRE_RL_wci_wslv_ctl_op_start,
WILL_FIRE_RL_wci_wslv_respF_both,
WILL_FIRE_RL_wci_wslv_respF_decCtr,
WILL_FIRE_RL_wci_wslv_respF_incCtr,
WILL_FIRE_RL_wmemi_dhF_both,
WILL_FIRE_RL_wmemi_dhF_decCtr,
WILL_FIRE_RL_wmemi_dhF_incCtr,
WILL_FIRE_RL_wmemi_reqF_both,
WILL_FIRE_RL_wmemi_reqF_decCtr,
WILL_FIRE_RL_wmemi_reqF_incCtr,
WILL_FIRE_RL_wmrd_mesgBegin,
WILL_FIRE_RL_wmrd_mesgBodyResponse,
WILL_FIRE_RL_wmwt_mesg_ingress,
WILL_FIRE_RL_wrtSer_begin,
WILL_FIRE_RL_wrtSer_body,
WILL_FIRE_RL_wsiM_reqFifo_both,
WILL_FIRE_RL_wsiM_reqFifo_decCtr,
WILL_FIRE_RL_wsiM_reqFifo_deq,
WILL_FIRE_RL_wsiM_reqFifo_incCtr,
WILL_FIRE_RL_wsiS_reqFifo_enq,
WILL_FIRE_RL_wsiS_reqFifo_reset,
WILL_FIRE_RL_wsipass_doMessagePush;
// inputs to muxes for submodule ports
reg [127 : 0] MUX_wide16Fa$enq_1__VAL_1, MUX_wide16Fa$enq_1__VAL_2;
reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_1;
wire [145 : 0] MUX_wmemi_dhF_q_0$write_1__VAL_1,
MUX_wmemi_dhF_q_0$write_1__VAL_2,
MUX_wmemi_dhF_q_1$write_1__VAL_2;
wire [60 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1,
MUX_wsiM_reqFifo_q_0$write_1__VAL_2,
MUX_wsiM_reqFifo_q_1$write_1__VAL_2,
MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1;
wire [51 : 0] MUX_wmemi_reqF_q_0$write_1__VAL_1,
MUX_wmemi_reqF_q_0$write_1__VAL_2,
MUX_wmemi_reqF_q_1$write_1__VAL_2,
MUX_wmemi_reqF_x_wire$wset_1__VAL_1,
MUX_wmemi_reqF_x_wire$wset_1__VAL_2;
wire [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2,
MUX_wci_wslv_respF_q_1$write_1__VAL_2,
MUX_wci_wslv_respF_x_wire$wset_1__VAL_1,
MUX_wci_wslv_respF_x_wire$wset_1__VAL_2;
wire [31 : 0] MUX_mesgRdCount$write_1__VAL_1,
MUX_mesgWtCount$write_1__VAL_1;
wire [24 : 0] MUX_dlyWordsStored_value$write_1__VAL_2;
wire [22 : 0] MUX_dlyRAG$write_1__VAL_1, MUX_dlyWAG$write_1__VAL_1;
wire [15 : 0] MUX_dlyReadyToWrite_value$write_1__VAL_2,
MUX_rdSerUnroll$write_1__VAL_2,
MUX_unrollCnt$write_1__VAL_1,
MUX_unrollCnt$write_1__VAL_2,
MUX_wrtSerUnroll$write_1__VAL_2;
wire [7 : 0] MUX_dlyReadCredit_value$write_1__VAL_2;
wire [1 : 0] MUX_rdSerPos$write_1__VAL_1,
MUX_wci_wslv_respF_c_r$write_1__VAL_1,
MUX_wci_wslv_respF_c_r$write_1__VAL_2,
MUX_wmemi_dhF_c_r$write_1__VAL_1,
MUX_wmemi_dhF_c_r$write_1__VAL_2,
MUX_wmemi_reqF_c_r$write_1__VAL_1,
MUX_wmemi_reqF_c_r$write_1__VAL_2,
MUX_wrtSerPos$write_1__VAL_1,
MUX_wrtSerPos$write_1__VAL_2,
MUX_wsiM_reqFifo_c_r$write_1__VAL_1,
MUX_wsiM_reqFifo_c_r$write_1__VAL_2;
wire MUX_mesgRdCount$write_1__SEL_1,
MUX_mesgWtCount$write_1__SEL_1,
MUX_rdSerEmpty$write_1__PSEL_1,
MUX_rdSerEmpty$write_1__SEL_1,
MUX_rdSyncWord$write_1__VAL_1,
MUX_rdSyncWord$write_1__VAL_2,
MUX_wci_wslv_illegalEdge$write_1__SEL_1,
MUX_wci_wslv_illegalEdge$write_1__SEL_2,
MUX_wci_wslv_illegalEdge$write_1__VAL_2,
MUX_wci_wslv_respF_q_0$write_1__SEL_1,
MUX_wci_wslv_respF_q_1$write_1__SEL_1,
MUX_wide16Fa$enq_1__SEL_1,
MUX_wmemi_dhF_q_0$write_1__SEL_1,
MUX_wmemi_dhF_q_1$write_1__SEL_1,
MUX_wmemi_reqF_q_0$write_1__SEL_1,
MUX_wmemi_reqF_q_1$write_1__SEL_1,
MUX_wrtSerStage$write_1__SEL_1,
MUX_wrtSerStage_1$write_1__SEL_1,
MUX_wrtSerStage_2$write_1__SEL_1,
MUX_wrtSerStage_3$write_1__SEL_1,
MUX_wsiM_reqFifo_q_0$write_1__SEL_1,
MUX_wsiM_reqFifo_q_1$write_1__SEL_1;
// remaining internal signals
reg [63 : 0] v__h24065, v__h3739, v__h3914, v__h4058;
reg [31 : 0] g_data__h23399, v__h21048;
reg CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q2,
CASE_wrtSerPos_NOT_wrtSerPos_EQ_3_OR_wide16Fa_ETC__q1;
wire [127 : 0] IF_wrtSerPos_90_EQ_2_00_THEN_0x0_ELSE_mesgWF_w_ETC___d557,
IF_wrtSerPos_90_EQ_2_00_THEN_0x0_ELSE_metaWF_f_ETC___d528,
x__h19290,
x__h19317,
x__h19946,
x__h19970;
wire [35 : 0] addr__h20380, addr__h20732;
wire [31 : 0] data__h19661,
delayStatus__h23019,
rdat__h23426,
rdat__h23432,
rdat__h23438,
rdat__h23444,
rdat__h23568,
rdat__h23582,
rdat__h23590,
rdat__h23596,
rdat__h23610,
rdat__h23618,
rdat__h23624,
rdat__h23630,
rdat__h23636,
rdat__h23642,
rdat__h23653,
rdat__h23664,
rdat__h23675,
rdat__h23696,
rdat__h23751,
rdat__h23760,
rdat__h23769,
rdat__h23778,
x__h16006;
wire [26 : 0] x__h20438, x__h20777;
wire [23 : 0] btm__h18537, x__h23448;
wire [13 : 0] mesgLengthSoFar_73_PLUS_1___d909;
wire [12 : 0] x__h16107;
wire [11 : 0] x_burstLength__h22925;
wire [3 : 0] x_byteEn__h22926;
wire [1 : 0] wrtSerPos_90_PLUS_1___d908;
wire IF_wrtSerPos_90_EQ_0_98_OR_wrtSerPos_90_EQ_1_9_ETC___d543,
NOT_mesgWF_rRdPtr_04_EQ_mesgWF_rWrPtr_95_31___d532,
NOT_mesgWF_rRdPtr_04_PLUS_2048_60_EQ_mesgWF_rW_ETC___d462,
NOT_wrtSerPos_90_EQ_3_91_92_AND_NOT_metaWF_fir_ETC___d506,
bytesWritten_86_ULT_dlyHoldoffBytes_65___d995,
cyclesPassed_56_ULT_dlyHoldoffCycles_68___d993,
dlyWordsStored_value_17_SLE_0_64_OR_bytesWritt_ETC___d572,
dlyWordsStored_value_17_SLE_0___d994,
dlyWordsStored_value_17_SLT_8388608___d574,
mesgRF_i_notFull__71_AND_NOT_rdSerEmpty_21_22__ETC___d672,
metaRF_i_notFull__20_AND_NOT_rdSerEmpty_21_22__ETC___d631,
wci_wslv_cState_6_EQ_2_7_AND_dlyCtrl_48_BITS_3_ETC___d592;
// value method wciS0_sResp
assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_wslv_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy =
wci_wslv_reqF_countReg > 2'd1 || wci_wslv_isReset_isInReset ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_wslv_sFlagReg } ;
// value method wsiS0_sThreadBusy
assign wsiS0_SThreadBusy =
!wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget ;
// value method wsiS0_sReset_n
assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ;
// value method wsiM0_mCmd
assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[60:58] ;
// value method wsiM0_mReqLast
assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[57] ;
// value method wsiM0_mBurstPrecise
assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[56] ;
// value method wsiM0_mBurstLength
assign wsiM0_MBurstLength =
wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[55:44] ;
// value method wsiM0_mData
assign wsiM0_MData = wsiM_reqFifo_q_0[43:12] ;
// value method wsiM0_mByteEn
assign wsiM0_MByteEn = wsiM_reqFifo_q_0[11:8] ;
// value method wsiM0_mReqInfo
assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ;
// value method wsiM0_mReset_n
assign wsiM0_MReset_n = !wsiM_isReset_isInReset && wsiM_operateD ;
// value method wmemiM0_mCmd
assign wmemiM0_MCmd = wmemi_reqF_q_0[51:49] ;
// value method wmemiM0_mReqLast
assign wmemiM0_MReqLast = wmemi_reqF_q_0[48] ;
// value method wmemiM0_mAddr
assign wmemiM0_MAddr = wmemi_reqF_q_0[47:12] ;
// value method wmemiM0_mBurstLength
assign wmemiM0_MBurstLength = wmemi_reqF_q_0[11:0] ;
// value method wmemiM0_mDataValid
assign wmemiM0_MDataValid = wmemi_dhF_q_0[145] ;
// value method wmemiM0_mDataLast
assign wmemiM0_MDataLast = wmemi_dhF_q_0[144] ;
// value method wmemiM0_mData
assign wmemiM0_MData = wmemi_dhF_q_0[143:16] ;
// value method wmemiM0_mDataByteEn
assign wmemiM0_MDataByteEn = wmemi_dhF_q_0[15:0] ;
// value method wmemiM0_mReset_n
assign wmemiM0_MReset_n = !wmemi_isReset_isInReset && wmemi_operateD ;
// submodule mesgRF
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd15),
.p3cntr_width(32'd4),
.guarded(32'd1)) mesgRF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(mesgRF$D_IN),
.ENQ(mesgRF$ENQ),
.DEQ(mesgRF$DEQ),
.CLR(mesgRF$CLR),
.D_OUT(mesgRF$D_OUT),
.FULL_N(mesgRF$FULL_N),
.EMPTY_N(mesgRF$EMPTY_N));
// submodule mesgWF_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd12),
.DATA_WIDTH(32'd32),
.MEMSIZE(13'd4096)) mesgWF_memory(.CLKA(wciS0_Clk),
.CLKB(wciS0_Clk),
.ADDRA(mesgWF_memory$ADDRA),
.ADDRB(mesgWF_memory$ADDRB),
.DIA(mesgWF_memory$DIA),
.DIB(mesgWF_memory$DIB),
.WEA(mesgWF_memory$WEA),
.WEB(mesgWF_memory$WEB),
.ENA(mesgWF_memory$ENA),
.ENB(mesgWF_memory$ENB),
.DOA(),
.DOB(mesgWF_memory$DOB));
// submodule metaRF
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd15),
.p3cntr_width(32'd4),
.guarded(32'd1)) metaRF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(metaRF$D_IN),
.ENQ(metaRF$ENQ),
.DEQ(metaRF$DEQ),
.CLR(metaRF$CLR),
.D_OUT(metaRF$D_OUT),
.FULL_N(metaRF$FULL_N),
.EMPTY_N(metaRF$EMPTY_N));
// submodule metaWF
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd15),
.p3cntr_width(32'd4),
.guarded(32'd1)) metaWF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(metaWF$D_IN),
.ENQ(metaWF$ENQ),
.DEQ(metaWF$DEQ),
.CLR(metaWF$CLR),
.D_OUT(metaWF$D_OUT),
.FULL_N(metaWF$FULL_N),
.EMPTY_N(metaWF$EMPTY_N));
// submodule wci_wslv_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_wslv_reqF$D_IN),
.ENQ(wci_wslv_reqF$ENQ),
.DEQ(wci_wslv_reqF$DEQ),
.CLR(wci_wslv_reqF$CLR),
.D_OUT(wci_wslv_reqF$D_OUT),
.FULL_N(),
.EMPTY_N(wci_wslv_reqF$EMPTY_N));
// submodule wide16Fa
SizedFIFO #(.p1width(32'd128),
.p2depth(32'd15),
.p3cntr_width(32'd4),
.guarded(32'd1)) wide16Fa(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wide16Fa$D_IN),
.ENQ(wide16Fa$ENQ),
.DEQ(wide16Fa$DEQ),
.CLR(wide16Fa$CLR),
.D_OUT(wide16Fa$D_OUT),
.FULL_N(wide16Fa$FULL_N),
.EMPTY_N(wide16Fa$EMPTY_N));
// submodule wide16Fb
SizedFIFO #(.p1width(32'd128),
.p2depth(32'd15),
.p3cntr_width(32'd4),
.guarded(32'd1)) wide16Fb(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wide16Fb$D_IN),
.ENQ(wide16Fb$ENQ),
.DEQ(wide16Fb$DEQ),
.CLR(wide16Fb$CLR),
.D_OUT(wide16Fb$D_OUT),
.FULL_N(wide16Fb$FULL_N),
.EMPTY_N(wide16Fb$EMPTY_N));
// submodule wide16Fc
SizedFIFO #(.p1width(32'd128),
.p2depth(32'd15),
.p3cntr_width(32'd4),
.guarded(32'd1)) wide16Fc(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wide16Fc$D_IN),
.ENQ(wide16Fc$ENQ),
.DEQ(wide16Fc$DEQ),
.CLR(wide16Fc$CLR),
.D_OUT(wide16Fc$D_OUT),
.FULL_N(wide16Fc$FULL_N),
.EMPTY_N(wide16Fc$EMPTY_N));
// submodule wmemi_respF
FIFO2 #(.width(32'd131), .guarded(32'd1)) wmemi_respF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wmemi_respF$D_IN),
.ENQ(wmemi_respF$ENQ),
.DEQ(wmemi_respF$DEQ),
.CLR(wmemi_respF$CLR),
.D_OUT(wmemi_respF$D_OUT),
.FULL_N(wmemi_respF$FULL_N),
.EMPTY_N(wmemi_respF$EMPTY_N));
// submodule wsiS_reqFifo
SizedFIFO #(.p1width(32'd61),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsiS_reqFifo$D_IN),
.ENQ(wsiS_reqFifo$ENQ),
.DEQ(wsiS_reqFifo$DEQ),
.CLR(wsiS_reqFifo$CLR),
.D_OUT(wsiS_reqFifo$D_OUT),
.FULL_N(wsiS_reqFifo$FULL_N),
.EMPTY_N(wsiS_reqFifo$EMPTY_N));
// rule RL_rdSer_sync
assign WILL_FIRE_RL_rdSer_sync =
wci_wslv_cState == 3'd2 && dlyCtrl[3:0] == 4'h7 && rdSyncWord ;
// rule RL_wci_wslv_ctl_op_start
assign WILL_FIRE_RL_wci_wslv_ctl_op_start =
wci_wslv_reqF$EMPTY_N && wci_wslv_wci_ctrl_pw$whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_ctrl_EiI
assign WILL_FIRE_RL_wci_ctrl_EiI =
wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd0 &&
wci_wslv_reqF$D_OUT[36:34] == 3'd0 ;
// rule RL_wci_ctrl_OrE
assign WILL_FIRE_RL_wci_ctrl_OrE =
wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd2 &&
wci_wslv_reqF$D_OUT[36:34] == 3'd3 ;
// rule RL_wsipass_doMessagePush
assign WILL_FIRE_RL_wsipass_doMessagePush =
wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h0 ;
// rule RL_wci_cfrd
assign WILL_FIRE_RL_wci_cfrd =
wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N &&
wci_wslv_wci_cfrd_pw$whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wrtSer_begin
assign WILL_FIRE_RL_wrtSer_begin =
metaWF$EMPTY_N &&
NOT_wrtSerPos_90_EQ_3_91_92_AND_NOT_metaWF_fir_ETC___d506 &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 &&
wrtSerUnroll == 16'd0 ;
// rule RL_delay_write_req
assign WILL_FIRE_RL_delay_write_req =
wmemi_reqF_c_r != 2'd2 && wmemi_dhF_c_r != 2'd2 &&
wmemi_operateD &&
wmemi_peerIsReady &&
wide16Fa$EMPTY_N &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 &&
dlyWordsStored_value_17_SLE_0_64_OR_bytesWritt_ETC___d572 &&
dlyWordsStored_value_17_SLT_8388608___d574 ;
// rule RL_delay_read_req
assign CAN_FIRE_RL_delay_read_req =
wmemi_reqF_c_r != 2'd2 && wmemi_operateD && wmemi_peerIsReady &&
wci_wslv_cState_6_EQ_2_7_AND_dlyCtrl_48_BITS_3_ETC___d592 &&
(dlyReadCredit_value ^ 8'h80) > 8'd128 &&
wsiM_reqFifo_c_r != 2'd2 ;
assign WILL_FIRE_RL_delay_read_req =
CAN_FIRE_RL_delay_read_req && !WILL_FIRE_RL_delay_write_req ;
// rule RL_wmwt_mesg_ingress
assign WILL_FIRE_RL_wmwt_mesg_ingress =
NOT_mesgWF_rRdPtr_04_PLUS_2048_60_EQ_mesgWF_rW_ETC___d462 &&
wsiS_reqFifo$EMPTY_N &&
(!wsiS_reqFifo$D_OUT[57] || metaWF$FULL_N) &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 ;
// rule RL_rdSer_begin
assign WILL_FIRE_RL_rdSer_begin =
metaRF_i_notFull__20_AND_NOT_rdSerEmpty_21_22__ETC___d631 &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 &&
rdSerUnroll == 16'd0 &&
!rdSyncWord ;
// rule RL_rdSer_body
assign WILL_FIRE_RL_rdSer_body =
mesgRF_i_notFull__71_AND_NOT_rdSerEmpty_21_22__ETC___d672 &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 &&
rdSerUnroll != 16'd0 &&
!rdSyncWord ;
// rule RL_wmrd_mesgBegin
assign WILL_FIRE_RL_wmrd_mesgBegin =
metaRF$EMPTY_N && wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 &&
unrollCnt == 16'd0 ;
// rule RL_wmrd_mesgBodyResponse
assign WILL_FIRE_RL_wmrd_mesgBodyResponse =
wsiM_reqFifo_c_r != 2'd2 && mesgRF$EMPTY_N &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 &&
unrollCnt != 16'd0 ;
// rule RL_wsiM_reqFifo_deq
assign WILL_FIRE_RL_wsiM_reqFifo_deq =
wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ;
// rule RL_wsiM_reqFifo_incCtr
assign WILL_FIRE_RL_wsiM_reqFifo_incCtr =
((wsiM_reqFifo_c_r == 2'd0) ?
wsiM_reqFifo_enqueueing$whas :
wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) &&
wsiM_reqFifo_enqueueing$whas &&
!WILL_FIRE_RL_wsiM_reqFifo_deq ;
// rule RL_wsiM_reqFifo_decCtr
assign WILL_FIRE_RL_wsiM_reqFifo_decCtr =
WILL_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing$whas ;
// rule RL_wsiM_reqFifo_both
assign WILL_FIRE_RL_wsiM_reqFifo_both =
((wsiM_reqFifo_c_r == 2'd1) ?
wsiM_reqFifo_enqueueing$whas :
wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) &&
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_enqueueing$whas ;
// rule RL_wmemi_reqF_incCtr
assign WILL_FIRE_RL_wmemi_reqF_incCtr =
((wmemi_reqF_c_r == 2'd0) ?
wmemi_reqF_x_wire$whas :
wmemi_reqF_c_r != 2'd1 || wmemi_reqF_x_wire$whas) &&
wmemi_reqF_enqueueing$whas &&
!wmemi_reqF_dequeueing$whas ;
// rule RL_wmemi_reqF_decCtr
assign WILL_FIRE_RL_wmemi_reqF_decCtr =
wmemi_reqF_dequeueing$whas && !wmemi_reqF_enqueueing$whas ;
// rule RL_wmemi_reqF_both
assign WILL_FIRE_RL_wmemi_reqF_both =
((wmemi_reqF_c_r == 2'd1) ?
wmemi_reqF_x_wire$whas :
wmemi_reqF_c_r != 2'd2 || wmemi_reqF_x_wire$whas) &&
wmemi_reqF_dequeueing$whas &&
wmemi_reqF_enqueueing$whas ;
// rule RL_wmemi_dhF_incCtr
assign WILL_FIRE_RL_wmemi_dhF_incCtr =
((wmemi_dhF_c_r == 2'd0) ?
WILL_FIRE_RL_delay_write_req :
wmemi_dhF_c_r != 2'd1 || WILL_FIRE_RL_delay_write_req) &&
WILL_FIRE_RL_delay_write_req &&
!wmemi_dhF_dequeueing$whas ;
// rule RL_wmemi_dhF_decCtr
assign WILL_FIRE_RL_wmemi_dhF_decCtr =
wmemi_dhF_dequeueing$whas && !WILL_FIRE_RL_delay_write_req ;
// rule RL_wmemi_dhF_both
assign WILL_FIRE_RL_wmemi_dhF_both =
((wmemi_dhF_c_r == 2'd1) ?
WILL_FIRE_RL_delay_write_req :
wmemi_dhF_c_r != 2'd2 || WILL_FIRE_RL_delay_write_req) &&
wmemi_dhF_dequeueing$whas &&
WILL_FIRE_RL_delay_write_req ;
// rule RL_wrtSer_body
assign WILL_FIRE_RL_wrtSer_body =
NOT_mesgWF_rRdPtr_04_EQ_mesgWF_rWrPtr_95_31___d532 &&
IF_wrtSerPos_90_EQ_0_98_OR_wrtSerPos_90_EQ_1_9_ETC___d543 &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 &&
wrtSerUnroll != 16'd0 ;
// rule RL_wci_cfwr
assign WILL_FIRE_RL_wci_cfwr =
wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N &&
wci_wslv_wci_cfwr_pw$whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_ctrl_IsO
assign WILL_FIRE_RL_wci_ctrl_IsO =
wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd1 &&
wci_wslv_reqF$D_OUT[36:34] == 3'd1 ;
// rule RL_wci_wslv_ctl_op_complete
assign WILL_FIRE_RL_wci_wslv_ctl_op_complete =
wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive &&
wci_wslv_ctlAckReg ;
// rule RL_wci_wslv_respF_incCtr
assign WILL_FIRE_RL_wci_wslv_respF_incCtr =
((wci_wslv_respF_c_r == 2'd0) ?
wci_wslv_respF_x_wire$whas :
wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) &&
wci_wslv_respF_enqueueing$whas &&
!(wci_wslv_respF_c_r != 2'd0) ;
// rule RL_wci_wslv_respF_decCtr
assign WILL_FIRE_RL_wci_wslv_respF_decCtr =
wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ;
// rule RL_wci_wslv_respF_both
assign WILL_FIRE_RL_wci_wslv_respF_both =
((wci_wslv_respF_c_r == 2'd1) ?
wci_wslv_respF_x_wire$whas :
wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) &&
wci_wslv_respF_c_r != 2'd0 &&
wci_wslv_respF_enqueueing$whas ;
// rule RL_wsiS_reqFifo_enq
assign WILL_FIRE_RL_wsiS_reqFifo_enq =
wsiS_reqFifo$FULL_N && wsiS_operateD && wsiS_peerIsReady &&
wsiS_wsiReq$wget[60:58] == 3'd1 ;
// rule RL_wsiS_reqFifo_reset
assign WILL_FIRE_RL_wsiS_reqFifo_reset =
WILL_FIRE_RL_wsiS_reqFifo_enq || wsiS_reqFifo_r_deq$whas ;
// inputs to muxes for submodule ports
assign MUX_mesgRdCount$write_1__SEL_1 =
WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 ;
assign MUX_mesgWtCount$write_1__SEL_1 =
WILL_FIRE_RL_wmwt_mesg_ingress && wsiS_reqFifo$D_OUT[57] ;
assign MUX_rdSerEmpty$write_1__PSEL_1 =
WILL_FIRE_RL_rdSer_body || WILL_FIRE_RL_rdSer_begin ;
assign MUX_rdSerEmpty$write_1__SEL_1 =
MUX_rdSerEmpty$write_1__PSEL_1 &&
(rdSerEmpty || rdSerPos == 2'd0) ;
assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
assign MUX_wci_wslv_illegalEdge$write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
wci_wslv_cState != 3'd3 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd2 && wci_wslv_cState != 3'd2 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd3 && wci_wslv_cState != 3'd3 &&
wci_wslv_cState != 3'd2 &&
wci_wslv_cState != 3'd1 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd4 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd5 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd6 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd7) ;
assign MUX_wci_wslv_respF_q_0$write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd0 ;
assign MUX_wci_wslv_respF_q_1$write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd1 ;
assign MUX_wide16Fa$enq_1__SEL_1 =
WILL_FIRE_RL_wrtSer_begin &&
(wrtSerPos == 2'd3 || metaWF$D_OUT[23:0] == 24'd0) ;
assign MUX_wmemi_dhF_q_0$write_1__SEL_1 =
WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'd0 ;
assign MUX_wmemi_dhF_q_1$write_1__SEL_1 =
WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'd1 ;
assign MUX_wmemi_reqF_q_0$write_1__SEL_1 =
WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'd0 ;
assign MUX_wmemi_reqF_q_1$write_1__SEL_1 =
WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'd1 ;
assign MUX_wrtSerStage$write_1__SEL_1 =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd0 ;
assign MUX_wrtSerStage_1$write_1__SEL_1 =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd1 ;
assign MUX_wrtSerStage_2$write_1__SEL_1 =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd2 ;
assign MUX_wrtSerStage_3$write_1__SEL_1 =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd3 ;
assign MUX_wsiM_reqFifo_q_0$write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ;
assign MUX_wsiM_reqFifo_q_1$write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ;
assign MUX_dlyRAG$write_1__VAL_1 = dlyRAG + 23'd1 ;
assign MUX_dlyReadCredit_value$write_1__VAL_2 =
dlyReadCredit_value +
(WILL_FIRE_RL_delay_read_req ? 8'd255 : 8'd0) +
(dlyReadCredit_acc_v2$whas ? 8'd1 : 8'd0) ;
assign MUX_dlyReadyToWrite_value$write_1__VAL_2 =
dlyReadyToWrite_value +
(dlyReadyToWrite_acc_v1$whas ? 16'd1 : 16'd0) +
(WILL_FIRE_RL_delay_write_req ? 16'd65535 : 16'd0) ;
assign MUX_dlyWAG$write_1__VAL_1 = dlyWAG + 23'd1 ;
assign MUX_dlyWordsStored_value$write_1__VAL_2 =
dlyWordsStored_value +
(WILL_FIRE_RL_delay_write_req ? 25'd1 : 25'd0) +
(WILL_FIRE_RL_delay_read_req ? 25'd33554431 : 25'd0) ;
assign MUX_mesgRdCount$write_1__VAL_1 = mesgRdCount + 32'd1 ;
assign MUX_mesgWtCount$write_1__VAL_1 = mesgWtCount + 32'd1 ;
assign MUX_rdSerPos$write_1__VAL_1 = rdSerPos + 2'd1 ;
assign MUX_rdSerUnroll$write_1__VAL_2 = rdSerUnroll - 16'd1 ;
assign MUX_rdSyncWord$write_1__VAL_1 =
rdSerPos != 2'd3 && v__h21048[23:0] == 24'd0 ;
assign MUX_rdSyncWord$write_1__VAL_2 =
rdSerPos != 2'd3 && rdSerUnroll == 16'd1 ;
assign MUX_unrollCnt$write_1__VAL_1 =
(metaRF$D_OUT[23:0] == 24'd0) ? 16'd1 : metaRF$D_OUT[17:2] ;
assign MUX_unrollCnt$write_1__VAL_2 = unrollCnt - 16'd1 ;
assign MUX_wci_wslv_illegalEdge$write_1__VAL_2 =
wci_wslv_reqF$D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd6 ;
assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ;
assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ;
always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or
MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 or
WILL_FIRE_RL_wci_cfrd or
MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_wslv_ctl_op_complete:
MUX_wci_wslv_respF_q_0$write_1__VAL_1 =
MUX_wci_wslv_respF_x_wire$wset_1__VAL_1;
WILL_FIRE_RL_wci_cfrd:
MUX_wci_wslv_respF_q_0$write_1__VAL_1 =
MUX_wci_wslv_respF_x_wire$wset_1__VAL_2;
WILL_FIRE_RL_wci_cfwr:
MUX_wci_wslv_respF_q_0$write_1__VAL_1 = 34'h1C0DE4201;
default: MUX_wci_wslv_respF_q_0$write_1__VAL_1 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
(wci_wslv_respF_c_r == 2'd1) ?
MUX_wci_wslv_respF_q_0$write_1__VAL_1 :
wci_wslv_respF_q_1 ;
assign MUX_wci_wslv_respF_q_1$write_1__VAL_2 =
(wci_wslv_respF_c_r == 2'd2) ?
MUX_wci_wslv_respF_q_0$write_1__VAL_1 :
34'h0AAAAAAAA ;
assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 =
wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h23399 } ;
always@(wrtSerPos or
IF_wrtSerPos_90_EQ_2_00_THEN_0x0_ELSE_metaWF_f_ETC___d528 or
x__h19290 or x__h19317)
begin
case (wrtSerPos)
2'd0: MUX_wide16Fa$enq_1__VAL_1 = x__h19290;
2'd1: MUX_wide16Fa$enq_1__VAL_1 = x__h19317;
default: MUX_wide16Fa$enq_1__VAL_1 =
IF_wrtSerPos_90_EQ_2_00_THEN_0x0_ELSE_metaWF_f_ETC___d528;
endcase
end
always@(wrtSerPos or
IF_wrtSerPos_90_EQ_2_00_THEN_0x0_ELSE_mesgWF_w_ETC___d557 or
x__h19946 or x__h19970)
begin
case (wrtSerPos)
2'd0: MUX_wide16Fa$enq_1__VAL_2 = x__h19946;
2'd1: MUX_wide16Fa$enq_1__VAL_2 = x__h19970;
default: MUX_wide16Fa$enq_1__VAL_2 =
IF_wrtSerPos_90_EQ_2_00_THEN_0x0_ELSE_mesgWF_w_ETC___d557;
endcase
end
assign MUX_wmemi_dhF_c_r$write_1__VAL_1 = wmemi_dhF_c_r + 2'd1 ;
assign MUX_wmemi_dhF_c_r$write_1__VAL_2 = wmemi_dhF_c_r - 2'd1 ;
assign MUX_wmemi_dhF_q_0$write_1__VAL_1 =
{ 2'd3, wide16Fa$D_OUT, 16'd65535 } ;
assign MUX_wmemi_dhF_q_0$write_1__VAL_2 =
(wmemi_dhF_c_r == 2'd1) ?
MUX_wmemi_dhF_q_0$write_1__VAL_1 :
wmemi_dhF_q_1 ;
assign MUX_wmemi_dhF_q_1$write_1__VAL_2 =
(wmemi_dhF_c_r == 2'd2) ?
MUX_wmemi_dhF_q_0$write_1__VAL_1 :
146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign MUX_wmemi_reqF_c_r$write_1__VAL_1 = wmemi_reqF_c_r + 2'd1 ;
assign MUX_wmemi_reqF_c_r$write_1__VAL_2 = wmemi_reqF_c_r - 2'd1 ;
assign MUX_wmemi_reqF_q_0$write_1__VAL_1 =
WILL_FIRE_RL_delay_write_req ?
MUX_wmemi_reqF_x_wire$wset_1__VAL_1 :
MUX_wmemi_reqF_x_wire$wset_1__VAL_2 ;
assign MUX_wmemi_reqF_q_0$write_1__VAL_2 =
(wmemi_reqF_c_r == 2'd1) ?
MUX_wmemi_reqF_q_0$write_1__VAL_1 :
wmemi_reqF_q_1 ;
assign MUX_wmemi_reqF_q_1$write_1__VAL_2 =
(wmemi_reqF_c_r == 2'd2) ?
MUX_wmemi_reqF_q_0$write_1__VAL_1 :
52'h0AAAAAAAAAAAA ;
assign MUX_wmemi_reqF_x_wire$wset_1__VAL_1 = { 4'd3, addr__h20380, 12'd1 } ;
assign MUX_wmemi_reqF_x_wire$wset_1__VAL_2 = { 4'd5, addr__h20732, 12'd1 } ;
assign MUX_wrtSerPos$write_1__VAL_1 =
(metaWF$D_OUT[23:0] == 24'd0) ?
2'd0 :
wrtSerPos_90_PLUS_1___d908 ;
assign MUX_wrtSerPos$write_1__VAL_2 =
(wrtSerUnroll == 16'd1) ? 2'd0 : wrtSerPos_90_PLUS_1___d908 ;
assign MUX_wrtSerUnroll$write_1__VAL_2 = wrtSerUnroll - 16'd1 ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ;
assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 =
WILL_FIRE_RL_wmrd_mesgBodyResponse ?
MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1 :
wsiS_reqFifo$D_OUT ;
assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 =
(wsiM_reqFifo_c_r == 2'd1) ?
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 :
wsiM_reqFifo_q_1 ;
assign MUX_wsiM_reqFifo_q_1$write_1__VAL_2 =
(wsiM_reqFifo_c_r == 2'd2) ?
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 :
61'h00000AAAAAAAAA00 ;
assign MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1 =
{ 3'd1,
unrollCnt == 16'd1,
1'd1,
x_burstLength__h22925,
mesgRF$D_OUT,
x_byteEn__h22926,
readMeta[31:24] } ;
// inlined wires
assign wci_wslv_wciReq$wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wslv_wciReq$whas = 1'd1 ;
assign wci_wslv_respF_x_wire$wget = MUX_wci_wslv_respF_q_0$write_1__VAL_1 ;
assign wci_wslv_respF_x_wire$whas =
WILL_FIRE_RL_wci_wslv_ctl_op_complete || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_wslv_wEdge$wget = wci_wslv_reqF$D_OUT[36:34] ;
assign wci_wslv_wEdge$whas = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_sFlagReg_1$wget = 1'b0 ;
assign wci_wslv_sFlagReg_1$whas = 1'b0 ;
assign wci_wslv_ctlAckReg_1$wget = 1'd1 ;
assign wci_wslv_ctlAckReg_1$whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
WILL_FIRE_RL_wci_ctrl_EiI ;
assign wci_wci_Es_mCmd_w$wget = wciS0_MCmd ;
assign wci_wci_Es_mCmd_w$whas = 1'd1 ;
assign wci_wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ;
assign wci_wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign wci_wci_Es_mByteEn_w$wget = wciS0_MByteEn ;
assign wci_wci_Es_mByteEn_w$whas = 1'd1 ;
assign wci_wci_Es_mAddr_w$wget = wciS0_MAddr ;
assign wci_wci_Es_mAddr_w$whas = 1'd1 ;
assign wci_wci_Es_mData_w$wget = wciS0_MData ;
assign wci_wci_Es_mData_w$whas = 1'd1 ;
assign wsiS_wsiReq$wget =
{ wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo } ;
assign wsiS_wsiReq$whas = 1'd1 ;
assign wsiS_operateD_1$wget = 1'd1 ;
assign wsiS_operateD_1$whas = wci_wslv_cState == 3'd2 ;
assign wsiS_peerIsReady_1$wget = 1'd1 ;
assign wsiS_peerIsReady_1$whas = wsiS0_MReset_n ;
assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ;
assign wsiS_sThreadBusy_dw$whas =
wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ;
assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_1 ;
assign wsiM_reqFifo_x_wire$whas = wsiM_reqFifo_enqueueing$whas ;
assign wsiM_operateD_1$wget = 1'd1 ;
assign wsiM_operateD_1$whas = wci_wslv_cState == 3'd2 ;
assign wsiM_peerIsReady_1$wget = 1'd1 ;
assign wsiM_peerIsReady_1$whas = wsiM0_SReset_n ;
assign wmemi_reqF_x_wire$wget = MUX_wmemi_reqF_q_0$write_1__VAL_1 ;
assign wmemi_reqF_x_wire$whas =
WILL_FIRE_RL_delay_write_req || WILL_FIRE_RL_delay_read_req ;
assign wmemi_dhF_x_wire$wget = MUX_wmemi_dhF_q_0$write_1__VAL_1 ;
assign wmemi_dhF_x_wire$whas = WILL_FIRE_RL_delay_write_req ;
assign wmemi_wmemiResponse$wget =
{ wmemiM0_SResp, wmemiM0_SRespLast, wmemiM0_SData } ;
assign wmemi_wmemiResponse$whas = 1'd1 ;
assign wmemi_sCmdAccept_w$wget = 1'd1 ;
assign wmemi_sCmdAccept_w$whas = wmemiM0_SCmdAccept ;
assign wmemi_sDataAccept_w$wget = 1'd1 ;
assign wmemi_sDataAccept_w$whas = wmemiM0_SDataAccept ;
assign wmemi_operateD_1$wget = 1'd1 ;
assign wmemi_operateD_1$whas = wci_wslv_cState == 3'd2 ;
assign wmemi_peerIsReady_1$wget = 1'b0 ;
assign wmemi_peerIsReady_1$whas = 1'b0 ;
assign mesgWF_wDataIn$wget = wsiS_reqFifo$D_OUT[43:12] ;
assign mesgWF_wDataIn$whas = WILL_FIRE_RL_wmwt_mesg_ingress ;
assign mesgWF_wDataOut$wget = data__h19661 ;
assign mesgWF_wDataOut$whas = 1'd1 ;
assign dlyWordsStored_acc_v1$wget = 25'd1 ;
assign dlyWordsStored_acc_v1$whas = WILL_FIRE_RL_delay_write_req ;
assign dlyWordsStored_acc_v2$wget = 25'd33554431 ;
assign dlyWordsStored_acc_v2$whas = WILL_FIRE_RL_delay_read_req ;
assign dlyReadCredit_acc_v1$wget = 8'd255 ;
assign dlyReadCredit_acc_v1$whas = WILL_FIRE_RL_delay_read_req ;
assign dlyReadCredit_acc_v2$wget = 8'd1 ;
assign dlyReadCredit_acc_v2$whas =
wide16Fc$FULL_N && wide16Fb$EMPTY_N && wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 ;
assign dlyReadyToWrite_acc_v1$wget = 16'd1 ;
assign dlyReadyToWrite_acc_v1$whas =
WILL_FIRE_RL_wrtSer_body || WILL_FIRE_RL_wrtSer_begin ;
assign dlyReadyToWrite_acc_v2$wget = 16'd65535 ;
assign dlyReadyToWrite_acc_v2$whas = WILL_FIRE_RL_delay_write_req ;
assign wsi_Es_mCmd_w$wget = wsiS0_MCmd ;
assign wsi_Es_mCmd_w$whas = 1'd1 ;
assign wsi_Es_mBurstLength_w$wget = wsiS0_MBurstLength ;
assign wsi_Es_mBurstLength_w$whas = 1'd1 ;
assign wsi_Es_mData_w$wget = wsiS0_MData ;
assign wsi_Es_mData_w$whas = 1'd1 ;
assign wsi_Es_mByteEn_w$wget = wsiS0_MByteEn ;
assign wsi_Es_mByteEn_w$whas = 1'd1 ;
assign wsi_Es_mReqInfo_w$wget = wsiS0_MReqInfo ;
assign wsi_Es_mReqInfo_w$whas = 1'd1 ;
assign wmemi_Em_sResp_w$wget = wmemiM0_SResp ;
assign wmemi_Em_sResp_w$whas = 1'd1 ;
assign wmemi_Em_sData_w$wget = wmemiM0_SData ;
assign wmemi_Em_sData_w$whas = 1'd1 ;
assign wci_wslv_reqF_r_enq$whas = wci_wslv_wciReq$wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_r_deq$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_reqF_r_clr$whas = 1'b0 ;
assign wci_wslv_respF_enqueueing$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ;
assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ;
assign wci_wslv_wci_cfwr_pw$whas =
wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] &&
wci_wslv_reqF$D_OUT[71:69] == 3'd1 ;
assign wci_wslv_wci_cfrd_pw$whas =
wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] &&
wci_wslv_reqF$D_OUT[71:69] == 3'd2 ;
assign wci_wslv_wci_ctrl_pw$whas =
wci_wslv_reqF$EMPTY_N && !wci_wslv_reqF$D_OUT[68] &&
wci_wslv_reqF$D_OUT[71:69] == 3'd2 ;
assign wsiS_reqFifo_r_enq$whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_r_deq$whas =
WILL_FIRE_RL_wmwt_mesg_ingress ||
WILL_FIRE_RL_wsipass_doMessagePush ;
assign wsiS_reqFifo_r_clr$whas = 1'b0 ;
assign wsiS_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_doResetDeq$whas = wsiS_reqFifo_r_deq$whas ;
assign wsiS_reqFifo_doResetClr$whas = 1'b0 ;
assign wsiM_reqFifo_enqueueing$whas =
WILL_FIRE_RL_wmrd_mesgBodyResponse ||
WILL_FIRE_RL_wsipass_doMessagePush ;
assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ;
assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ;
assign wmemi_reqF_enqueueing$whas =
WILL_FIRE_RL_delay_read_req || WILL_FIRE_RL_delay_write_req ;
assign wmemi_reqF_dequeueing$whas =
wmemiM0_SCmdAccept && wmemi_reqF_c_r != 2'd0 ;
assign wmemi_dhF_enqueueing$whas = WILL_FIRE_RL_delay_write_req ;
assign wmemi_dhF_dequeueing$whas =
wmemiM0_SDataAccept && wmemi_dhF_c_r != 2'd0 ;
assign mesgWF_pwDequeue$whas = WILL_FIRE_RL_wrtSer_body ;
assign mesgWF_pwEnqueue$whas = WILL_FIRE_RL_wmwt_mesg_ingress ;
assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ;
assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ;
assign wsi_Es_mDataInfo_w$whas = 1'd1 ;
assign wmemi_Em_sRespLast_w$whas = wmemiM0_SRespLast ;
assign wsiS_extStatusW$wget =
{ wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ;
assign wsiM_extStatusW$wget =
{ wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ;
// register bytesRead
assign bytesRead$D_IN = bytesRead + 32'd4 ;
assign bytesRead$EN =
MUX_rdSerEmpty$write_1__PSEL_1 && bytesRead != 32'hFFFFFFFF ;
// register bytesThisMessage
assign bytesThisMessage$D_IN = btm__h18537 ;
assign bytesThisMessage$EN = MUX_mesgWtCount$write_1__SEL_1 ;
// register bytesWritten
assign bytesWritten$D_IN = bytesWritten + 32'd4 ;
assign bytesWritten$EN =
WILL_FIRE_RL_wmwt_mesg_ingress && bytesWritten < 32'hFFFFFFFB ;
// register cyclesPassed
assign cyclesPassed$D_IN = cyclesPassed + 32'd1 ;
assign cyclesPassed$EN = wsiS_statusR[0] && cyclesPassed != 32'hFFFFFFFF ;
// register dlyCtrl
assign dlyCtrl$D_IN = wci_wslv_reqF$D_OUT[31:0] ;
assign dlyCtrl$EN =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:32] == 32'h0 ;
// register dlyHoldoffBytes
assign dlyHoldoffBytes$D_IN = wci_wslv_reqF$D_OUT[31:0] ;
assign dlyHoldoffBytes$EN =
WILL_FIRE_RL_wci_cfwr &&
wci_wslv_reqF$D_OUT[63:32] == 32'h00000004 ;
// register dlyHoldoffCycles
assign dlyHoldoffCycles$D_IN = wci_wslv_reqF$D_OUT[31:0] ;
assign dlyHoldoffCycles$EN =
WILL_FIRE_RL_wci_cfwr &&
wci_wslv_reqF$D_OUT[63:32] == 32'h00000008 ;
// register dlyRAG
assign dlyRAG$D_IN =
WILL_FIRE_RL_delay_read_req ? MUX_dlyRAG$write_1__VAL_1 : 23'd0 ;
assign dlyRAG$EN =
WILL_FIRE_RL_delay_read_req || WILL_FIRE_RL_wci_ctrl_IsO ;
// register dlyRdOpOther
assign dlyRdOpOther$D_IN = dlyRdOpOther + 32'd1 ;
assign dlyRdOpOther$EN =
WILL_FIRE_RL_rdSer_begin && v__h21048[31:24] != 8'd0 ;
// register dlyRdOpZero
assign dlyRdOpZero$D_IN = dlyRdOpZero + 32'd1 ;
assign dlyRdOpZero$EN =
WILL_FIRE_RL_rdSer_begin && v__h21048[31:24] == 8'd0 ;
// register dlyReadCredit_value
assign dlyReadCredit_value$D_IN =
WILL_FIRE_RL_wci_ctrl_IsO ?
8'd12 :
MUX_dlyReadCredit_value$write_1__VAL_2 ;
assign dlyReadCredit_value$EN = 1'b1 ;
// register dlyReadyToWrite_value
assign dlyReadyToWrite_value$D_IN =
WILL_FIRE_RL_wci_ctrl_IsO ?
16'd0 :
MUX_dlyReadyToWrite_value$write_1__VAL_2 ;
assign dlyReadyToWrite_value$EN = 1'b1 ;
// register dlyWAG
assign dlyWAG$D_IN =
WILL_FIRE_RL_delay_write_req ?
MUX_dlyWAG$write_1__VAL_1 :
23'd0 ;
assign dlyWAG$EN =
WILL_FIRE_RL_delay_write_req || WILL_FIRE_RL_wci_ctrl_IsO ;
// register dlyWordsStored_value
assign dlyWordsStored_value$D_IN =
WILL_FIRE_RL_wci_ctrl_IsO ?
25'd0 :
MUX_dlyWordsStored_value$write_1__VAL_2 ;
assign dlyWordsStored_value$EN = 1'b1 ;
// register mesgLengthSoFar
assign mesgLengthSoFar$D_IN =
wsiS_reqFifo$D_OUT[57] ?
14'd0 :
mesgLengthSoFar_73_PLUS_1___d909 ;
assign mesgLengthSoFar$EN = WILL_FIRE_RL_wmwt_mesg_ingress ;
// register mesgRdCount
assign mesgRdCount$D_IN =
MUX_mesgRdCount$write_1__SEL_1 ?
MUX_mesgRdCount$write_1__VAL_1 :
32'd0 ;
assign mesgRdCount$EN =
WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 ||
WILL_FIRE_RL_wci_ctrl_IsO ;
// register mesgWF_rCache
assign mesgWF_rCache$D_IN = { 1'd1, mesgWF_rWrPtr, x__h16006 } ;
assign mesgWF_rCache$EN = WILL_FIRE_RL_wmwt_mesg_ingress ;
// register mesgWF_rRdPtr
assign mesgWF_rRdPtr$D_IN = x__h16107 ;
assign mesgWF_rRdPtr$EN = WILL_FIRE_RL_wrtSer_body ;
// register mesgWF_rWrPtr
assign mesgWF_rWrPtr$D_IN = mesgWF_rWrPtr + 13'd1 ;
assign mesgWF_rWrPtr$EN = WILL_FIRE_RL_wmwt_mesg_ingress ;
// register mesgWtCount
assign mesgWtCount$D_IN =
MUX_mesgWtCount$write_1__SEL_1 ?
MUX_mesgWtCount$write_1__VAL_1 :
32'd0 ;
assign mesgWtCount$EN =
WILL_FIRE_RL_wmwt_mesg_ingress && wsiS_reqFifo$D_OUT[57] ||
WILL_FIRE_RL_wci_ctrl_IsO ;
// register rdSerAddr
assign rdSerAddr$D_IN = 32'h0 ;
assign rdSerAddr$EN = 1'b0 ;
// register rdSerEmpty
assign rdSerEmpty$D_IN = !MUX_rdSerEmpty$write_1__SEL_1 ;
assign rdSerEmpty$EN =
(WILL_FIRE_RL_rdSer_body || WILL_FIRE_RL_rdSer_begin) &&
(rdSerEmpty || rdSerPos == 2'd0) ||
WILL_FIRE_RL_rdSer_sync ;
// register rdSerMeta
assign rdSerMeta$D_IN = v__h21048 ;
assign rdSerMeta$EN = WILL_FIRE_RL_rdSer_begin ;
// register rdSerPos
assign rdSerPos$D_IN =
MUX_rdSerEmpty$write_1__PSEL_1 ?
MUX_rdSerPos$write_1__VAL_1 :
2'd0 ;
assign rdSerPos$EN =
WILL_FIRE_RL_rdSer_body || WILL_FIRE_RL_rdSer_begin ||
WILL_FIRE_RL_rdSer_sync ;
// register rdSerStage
assign rdSerStage$D_IN = wide16Fc$D_OUT[31:0] ;
assign rdSerStage$EN =
MUX_rdSerEmpty$write_1__PSEL_1 &&
(rdSerEmpty || rdSerPos == 2'd0) ;
// register rdSerStage_1
assign rdSerStage_1$D_IN = wide16Fc$D_OUT[63:32] ;
assign rdSerStage_1$EN =
MUX_rdSerEmpty$write_1__PSEL_1 &&
(rdSerEmpty || rdSerPos == 2'd0) ;
// register rdSerStage_2
assign rdSerStage_2$D_IN = wide16Fc$D_OUT[95:64] ;
assign rdSerStage_2$EN =
MUX_rdSerEmpty$write_1__PSEL_1 &&
(rdSerEmpty || rdSerPos == 2'd0) ;
// register rdSerStage_3
assign rdSerStage_3$D_IN = wide16Fc$D_OUT[127:96] ;
assign rdSerStage_3$EN =
MUX_rdSerEmpty$write_1__PSEL_1 &&
(rdSerEmpty || rdSerPos == 2'd0) ;
// register rdSerUnroll
assign rdSerUnroll$D_IN =
WILL_FIRE_RL_rdSer_begin ?
v__h21048[17:2] :
MUX_rdSerUnroll$write_1__VAL_2 ;
assign rdSerUnroll$EN =
WILL_FIRE_RL_rdSer_begin || WILL_FIRE_RL_rdSer_body ;
// register rdSyncWord
always@(WILL_FIRE_RL_rdSer_begin or
MUX_rdSyncWord$write_1__VAL_1 or
WILL_FIRE_RL_rdSer_body or
MUX_rdSyncWord$write_1__VAL_2 or WILL_FIRE_RL_rdSer_sync)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rdSer_begin:
rdSyncWord$D_IN = MUX_rdSyncWord$write_1__VAL_1;
WILL_FIRE_RL_rdSer_body:
rdSyncWord$D_IN = MUX_rdSyncWord$write_1__VAL_2;
WILL_FIRE_RL_rdSer_sync: rdSyncWord$D_IN = 1'd0;
default: rdSyncWord$D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign rdSyncWord$EN =
WILL_FIRE_RL_rdSer_begin || WILL_FIRE_RL_rdSer_body ||
WILL_FIRE_RL_rdSer_sync ;
// register readMeta
assign readMeta$D_IN = metaRF$D_OUT ;
assign readMeta$EN = WILL_FIRE_RL_wmrd_mesgBegin ;
// register tog50
assign tog50$D_IN = !tog50 ;
assign tog50$EN = wci_wslv_cState == 3'd2 ;
// register unrollCnt
assign unrollCnt$D_IN =
WILL_FIRE_RL_wmrd_mesgBegin ?
MUX_unrollCnt$write_1__VAL_1 :
MUX_unrollCnt$write_1__VAL_2 ;
assign unrollCnt$EN =
WILL_FIRE_RL_wmrd_mesgBegin ||
WILL_FIRE_RL_wmrd_mesgBodyResponse ;
// register wci_wslv_cEdge
assign wci_wslv_cEdge$D_IN = wci_wslv_reqF$D_OUT[36:34] ;
assign wci_wslv_cEdge$EN = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_cState
assign wci_wslv_cState$D_IN = wci_wslv_nState ;
assign wci_wslv_cState$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge ;
// register wci_wslv_ctlAckReg
assign wci_wslv_ctlAckReg$D_IN = wci_wslv_ctlAckReg_1$whas ;
assign wci_wslv_ctlAckReg$EN = 1'd1 ;
// register wci_wslv_ctlOpActive
assign wci_wslv_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_ctlOpActive$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge$D_IN =
!MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
MUX_wci_wslv_illegalEdge$write_1__VAL_2 ;
assign wci_wslv_illegalEdge$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ||
MUX_wci_wslv_illegalEdge$write_1__SEL_2 ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset$D_IN = 1'd0 ;
assign wci_wslv_isReset_isInReset$EN = wci_wslv_isReset_isInReset ;
// register wci_wslv_nState
always@(wci_wslv_reqF$D_OUT)
begin
case (wci_wslv_reqF$D_OUT[36:34])
3'd0: wci_wslv_nState$D_IN = 3'd1;
3'd1: wci_wslv_nState$D_IN = 3'd2;
3'd2: wci_wslv_nState$D_IN = 3'd3;
default: wci_wslv_nState$D_IN = 3'd0;
endcase
end
assign wci_wslv_nState$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState == 3'd0 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd1 &&
(wci_wslv_cState == 3'd1 || wci_wslv_cState == 3'd3) ||
wci_wslv_reqF$D_OUT[36:34] == 3'd2 && wci_wslv_cState == 3'd2 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd3 &&
(wci_wslv_cState == 3'd3 || wci_wslv_cState == 3'd2 ||
wci_wslv_cState == 3'd1)) ;
// register wci_wslv_reqF_countReg
assign wci_wslv_reqF_countReg$D_IN =
(wci_wslv_wciReq$wget[71:69] != 3'd0) ?
wci_wslv_reqF_countReg + 2'd1 :
wci_wslv_reqF_countReg - 2'd1 ;
assign wci_wslv_reqF_countReg$EN =
(wci_wslv_wciReq$wget[71:69] != 3'd0) !=
wci_wslv_reqF_r_deq$whas ;
// register wci_wslv_respF_c_r
assign wci_wslv_respF_c_r$D_IN =
WILL_FIRE_RL_wci_wslv_respF_incCtr ?
MUX_wci_wslv_respF_c_r$write_1__VAL_1 :
MUX_wci_wslv_respF_c_r$write_1__VAL_2 ;
assign wci_wslv_respF_c_r$EN =
WILL_FIRE_RL_wci_wslv_respF_incCtr ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_respF_q_0
always@(MUX_wci_wslv_respF_q_0$write_1__SEL_1 or
MUX_wci_wslv_respF_q_0$write_1__VAL_1 or
WILL_FIRE_RL_wci_wslv_respF_both or
MUX_wci_wslv_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_q_0$write_1__SEL_1:
wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1;
WILL_FIRE_RL_wci_wslv_respF_both:
wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_0$D_IN = wci_wslv_respF_q_1;
default: wci_wslv_respF_q_0$D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_0$EN =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd0 ||
WILL_FIRE_RL_wci_wslv_respF_both ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_respF_q_1
always@(MUX_wci_wslv_respF_q_1$write_1__SEL_1 or
MUX_wci_wslv_respF_q_0$write_1__VAL_1 or
WILL_FIRE_RL_wci_wslv_respF_both or
MUX_wci_wslv_respF_q_1$write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_q_1$write_1__SEL_1:
wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1;
WILL_FIRE_RL_wci_wslv_respF_both:
wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_1$D_IN = 34'h0AAAAAAAA;
default: wci_wslv_respF_q_1$D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_1$EN =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd1 ||
WILL_FIRE_RL_wci_wslv_respF_both ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_sFlagReg
assign wci_wslv_sFlagReg$D_IN = 1'b0 ;
assign wci_wslv_sFlagReg$EN = 1'd1 ;
// register wci_wslv_sThreadBusy_d
assign wci_wslv_sThreadBusy_d$D_IN = 1'b0 ;
assign wci_wslv_sThreadBusy_d$EN = 1'd1 ;
// register wmemiRdReq
assign wmemiRdReq$D_IN = wmemiRdReq + 32'd1 ;
assign wmemiRdReq$EN = WILL_FIRE_RL_delay_read_req ;
// register wmemiRdResp1
assign wmemiRdResp1$D_IN = wmemiRdResp1 + 32'd1 ;
assign wmemiRdResp1$EN =
wmemi_respF$EMPTY_N && wide16Fb$FULL_N &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 ;
// register wmemiRdResp2
assign wmemiRdResp2$D_IN = wmemiRdResp2 + 32'd1 ;
assign wmemiRdResp2$EN = dlyReadCredit_acc_v2$whas ;
// register wmemiWrReq
assign wmemiWrReq$D_IN = wmemiWrReq + 32'd1 ;
assign wmemiWrReq$EN = WILL_FIRE_RL_delay_write_req ;
// register wmemi_busyWithMessage
assign wmemi_busyWithMessage$D_IN = 1'b0 ;
assign wmemi_busyWithMessage$EN = 1'b0 ;
// register wmemi_dhF_c_r
assign wmemi_dhF_c_r$D_IN =
WILL_FIRE_RL_wmemi_dhF_incCtr ?
MUX_wmemi_dhF_c_r$write_1__VAL_1 :
MUX_wmemi_dhF_c_r$write_1__VAL_2 ;
assign wmemi_dhF_c_r$EN =
WILL_FIRE_RL_wmemi_dhF_incCtr || WILL_FIRE_RL_wmemi_dhF_decCtr ;
// register wmemi_dhF_q_0
always@(MUX_wmemi_dhF_q_0$write_1__SEL_1 or
MUX_wmemi_dhF_q_0$write_1__VAL_1 or
WILL_FIRE_RL_wmemi_dhF_both or
MUX_wmemi_dhF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wmemi_dhF_decCtr or wmemi_dhF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wmemi_dhF_q_0$write_1__SEL_1:
wmemi_dhF_q_0$D_IN = MUX_wmemi_dhF_q_0$write_1__VAL_1;
WILL_FIRE_RL_wmemi_dhF_both:
wmemi_dhF_q_0$D_IN = MUX_wmemi_dhF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wmemi_dhF_decCtr: wmemi_dhF_q_0$D_IN = wmemi_dhF_q_1;
default: wmemi_dhF_q_0$D_IN =
146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmemi_dhF_q_0$EN =
WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'd0 ||
WILL_FIRE_RL_wmemi_dhF_both ||
WILL_FIRE_RL_wmemi_dhF_decCtr ;
// register wmemi_dhF_q_1
always@(MUX_wmemi_dhF_q_1$write_1__SEL_1 or
MUX_wmemi_dhF_q_0$write_1__VAL_1 or
WILL_FIRE_RL_wmemi_dhF_both or
MUX_wmemi_dhF_q_1$write_1__VAL_2 or WILL_FIRE_RL_wmemi_dhF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wmemi_dhF_q_1$write_1__SEL_1:
wmemi_dhF_q_1$D_IN = MUX_wmemi_dhF_q_0$write_1__VAL_1;
WILL_FIRE_RL_wmemi_dhF_both:
wmemi_dhF_q_1$D_IN = MUX_wmemi_dhF_q_1$write_1__VAL_2;
WILL_FIRE_RL_wmemi_dhF_decCtr:
wmemi_dhF_q_1$D_IN = 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
default: wmemi_dhF_q_1$D_IN =
146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmemi_dhF_q_1$EN =
WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'd1 ||
WILL_FIRE_RL_wmemi_dhF_both ||
WILL_FIRE_RL_wmemi_dhF_decCtr ;
// register wmemi_errorSticky
assign wmemi_errorSticky$D_IN = 1'b0 ;
assign wmemi_errorSticky$EN = 1'b0 ;
// register wmemi_isReset_isInReset
assign wmemi_isReset_isInReset$D_IN = 1'd0 ;
assign wmemi_isReset_isInReset$EN = wmemi_isReset_isInReset ;
// register wmemi_operateD
assign wmemi_operateD$D_IN = wci_wslv_cState == 3'd2 ;
assign wmemi_operateD$EN = 1'd1 ;
// register wmemi_peerIsReady
assign wmemi_peerIsReady$D_IN = 1'b1 ;
assign wmemi_peerIsReady$EN = 1'd1 ;
// register wmemi_reqF_c_r
assign wmemi_reqF_c_r$D_IN =
WILL_FIRE_RL_wmemi_reqF_incCtr ?
MUX_wmemi_reqF_c_r$write_1__VAL_1 :
MUX_wmemi_reqF_c_r$write_1__VAL_2 ;
assign wmemi_reqF_c_r$EN =
WILL_FIRE_RL_wmemi_reqF_incCtr ||
WILL_FIRE_RL_wmemi_reqF_decCtr ;
// register wmemi_reqF_q_0
always@(MUX_wmemi_reqF_q_0$write_1__SEL_1 or
MUX_wmemi_reqF_q_0$write_1__VAL_1 or
WILL_FIRE_RL_wmemi_reqF_both or
MUX_wmemi_reqF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wmemi_reqF_decCtr or wmemi_reqF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wmemi_reqF_q_0$write_1__SEL_1:
wmemi_reqF_q_0$D_IN = MUX_wmemi_reqF_q_0$write_1__VAL_1;
WILL_FIRE_RL_wmemi_reqF_both:
wmemi_reqF_q_0$D_IN = MUX_wmemi_reqF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wmemi_reqF_decCtr: wmemi_reqF_q_0$D_IN = wmemi_reqF_q_1;
default: wmemi_reqF_q_0$D_IN =
52'hAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmemi_reqF_q_0$EN =
WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'd0 ||
WILL_FIRE_RL_wmemi_reqF_both ||
WILL_FIRE_RL_wmemi_reqF_decCtr ;
// register wmemi_reqF_q_1
always@(MUX_wmemi_reqF_q_1$write_1__SEL_1 or
MUX_wmemi_reqF_q_0$write_1__VAL_1 or
WILL_FIRE_RL_wmemi_reqF_both or
MUX_wmemi_reqF_q_1$write_1__VAL_2 or WILL_FIRE_RL_wmemi_reqF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wmemi_reqF_q_1$write_1__SEL_1:
wmemi_reqF_q_1$D_IN = MUX_wmemi_reqF_q_0$write_1__VAL_1;
WILL_FIRE_RL_wmemi_reqF_both:
wmemi_reqF_q_1$D_IN = MUX_wmemi_reqF_q_1$write_1__VAL_2;
WILL_FIRE_RL_wmemi_reqF_decCtr: wmemi_reqF_q_1$D_IN = 52'h0AAAAAAAAAAAA;
default: wmemi_reqF_q_1$D_IN =
52'hAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmemi_reqF_q_1$EN =
WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'd1 ||
WILL_FIRE_RL_wmemi_reqF_both ||
WILL_FIRE_RL_wmemi_reqF_decCtr ;
// register wmemi_statusR
assign wmemi_statusR$D_IN =
{ wmemi_isReset_isInReset,
!wmemi_peerIsReady,
!wmemi_operateD,
wmemi_errorSticky,
3'd0,
wmemi_trafficSticky } ;
assign wmemi_statusR$EN = 1'd1 ;
// register wmemi_trafficSticky
assign wmemi_trafficSticky$D_IN = 1'd1 ;
assign wmemi_trafficSticky$EN = wmemiM0_SCmdAccept ;
// register wrtSerAddr
assign wrtSerAddr$D_IN = 32'h0 ;
assign wrtSerAddr$EN = 1'b0 ;
// register wrtSerPos
assign wrtSerPos$D_IN =
WILL_FIRE_RL_wrtSer_begin ?
MUX_wrtSerPos$write_1__VAL_1 :
MUX_wrtSerPos$write_1__VAL_2 ;
assign wrtSerPos$EN =
WILL_FIRE_RL_wrtSer_begin || WILL_FIRE_RL_wrtSer_body ;
// register wrtSerStage
assign wrtSerStage$D_IN =
MUX_wrtSerStage$write_1__SEL_1 ? data__h19661 : metaWF$D_OUT ;
assign wrtSerStage$EN =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd0 ||
WILL_FIRE_RL_wrtSer_begin && wrtSerPos == 2'd0 ;
// register wrtSerStage_1
assign wrtSerStage_1$D_IN =
MUX_wrtSerStage_1$write_1__SEL_1 ? data__h19661 : metaWF$D_OUT ;
assign wrtSerStage_1$EN =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd1 ||
WILL_FIRE_RL_wrtSer_begin && wrtSerPos == 2'd1 ;
// register wrtSerStage_2
assign wrtSerStage_2$D_IN =
MUX_wrtSerStage_2$write_1__SEL_1 ? data__h19661 : metaWF$D_OUT ;
assign wrtSerStage_2$EN =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd2 ||
WILL_FIRE_RL_wrtSer_begin && wrtSerPos == 2'd2 ;
// register wrtSerStage_3
assign wrtSerStage_3$D_IN =
MUX_wrtSerStage_3$write_1__SEL_1 ? data__h19661 : metaWF$D_OUT ;
assign wrtSerStage_3$EN =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd3 ||
WILL_FIRE_RL_wrtSer_begin && wrtSerPos == 2'd3 ;
// register wrtSerUnroll
assign wrtSerUnroll$D_IN =
WILL_FIRE_RL_wrtSer_begin ?
metaWF$D_OUT[17:2] :
MUX_wrtSerUnroll$write_1__VAL_2 ;
assign wrtSerUnroll$EN =
WILL_FIRE_RL_wrtSer_begin || WILL_FIRE_RL_wrtSer_body ;
// register wsiM_burstKind
assign wsiM_burstKind$D_IN =
(wsiM_burstKind == 2'd0) ?
(wsiM_reqFifo_q_0[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiM_burstKind$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
(wsiM_burstKind == 2'd0 ||
(wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) &&
wsiM_reqFifo_q_0[57]) ;
// register wsiM_errorSticky
assign wsiM_errorSticky$D_IN = 1'b0 ;
assign wsiM_errorSticky$EN = 1'b0 ;
// register wsiM_iMesgCount
assign wsiM_iMesgCount$D_IN = wsiM_iMesgCount + 32'd1 ;
assign wsiM_iMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
wsiM_burstKind == 2'd2 &&
wsiM_reqFifo_q_0[57] ;
// register wsiM_isReset_isInReset
assign wsiM_isReset_isInReset$D_IN = 1'd0 ;
assign wsiM_isReset_isInReset$EN = wsiM_isReset_isInReset ;
// register wsiM_operateD
assign wsiM_operateD$D_IN = wci_wslv_cState == 3'd2 ;
assign wsiM_operateD$EN = 1'd1 ;
// register wsiM_pMesgCount
assign wsiM_pMesgCount$D_IN = wsiM_pMesgCount + 32'd1 ;
assign wsiM_pMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
wsiM_burstKind == 2'd1 &&
wsiM_reqFifo_q_0[57] ;
// register wsiM_peerIsReady
assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ;
assign wsiM_peerIsReady$EN = 1'd1 ;
// register wsiM_reqFifo_c_r
assign wsiM_reqFifo_c_r$D_IN =
WILL_FIRE_RL_wsiM_reqFifo_incCtr ?
MUX_wsiM_reqFifo_c_r$write_1__VAL_1 :
MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ;
assign wsiM_reqFifo_c_r$EN =
WILL_FIRE_RL_wsiM_reqFifo_incCtr ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_0
always@(MUX_wsiM_reqFifo_q_0$write_1__SEL_1 or
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or
WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_0$write_1__SEL_1:
wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1;
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1;
default: wsiM_reqFifo_q_0$D_IN =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_0$EN =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ||
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_1
always@(MUX_wsiM_reqFifo_q_1$write_1__SEL_1 or
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or
WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_1$write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_1$write_1__SEL_1:
wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1;
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_1$D_IN = 61'h00000AAAAAAAAA00;
default: wsiM_reqFifo_q_1$D_IN =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_1$EN =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ||
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_sThreadBusy_d
assign wsiM_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ;
assign wsiM_sThreadBusy_d$EN = 1'd1 ;
// register wsiM_statusR
assign wsiM_statusR$D_IN =
{ wsiM_isReset_isInReset,
!wsiM_peerIsReady,
!wsiM_operateD,
wsiM_errorSticky,
wsiM_burstKind != 2'd0,
wsiM_sThreadBusy_d,
1'd0,
wsiM_trafficSticky } ;
assign wsiM_statusR$EN = 1'd1 ;
// register wsiM_tBusyCount
assign wsiM_tBusyCount$D_IN = wsiM_tBusyCount + 32'd1 ;
assign wsiM_tBusyCount$EN =
wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ;
// register wsiM_trafficSticky
assign wsiM_trafficSticky$D_IN = 1'd1 ;
assign wsiM_trafficSticky$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 ;
// register wsiS_burstKind
assign wsiS_burstKind$D_IN =
(wsiS_burstKind == 2'd0) ?
(wsiS_wsiReq$wget[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiS_burstKind$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq &&
(wsiS_burstKind == 2'd0 ||
(wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) &&
wsiS_wsiReq$wget[57]) ;
// register wsiS_errorSticky
assign wsiS_errorSticky$D_IN = 1'b0 ;
assign wsiS_errorSticky$EN = 1'b0 ;
// register wsiS_iMesgCount
assign wsiS_iMesgCount$D_IN = wsiS_iMesgCount + 32'd1 ;
assign wsiS_iMesgCount$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd2 &&
wsiS_wsiReq$wget[57] ;
// register wsiS_isReset_isInReset
assign wsiS_isReset_isInReset$D_IN = 1'd0 ;
assign wsiS_isReset_isInReset$EN = wsiS_isReset_isInReset ;
// register wsiS_mesgWordLength
assign wsiS_mesgWordLength$D_IN = wsiS_wordCount ;
assign wsiS_mesgWordLength$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_wsiReq$wget[57] ;
// register wsiS_operateD
assign wsiS_operateD$D_IN = wci_wslv_cState == 3'd2 ;
assign wsiS_operateD$EN = 1'd1 ;
// register wsiS_pMesgCount
assign wsiS_pMesgCount$D_IN = wsiS_pMesgCount + 32'd1 ;
assign wsiS_pMesgCount$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd1 &&
wsiS_wsiReq$wget[57] ;
// register wsiS_peerIsReady
assign wsiS_peerIsReady$D_IN = wsiS0_MReset_n ;
assign wsiS_peerIsReady$EN = 1'd1 ;
// register wsiS_reqFifo_countReg
assign wsiS_reqFifo_countReg$D_IN =
WILL_FIRE_RL_wsiS_reqFifo_enq ?
wsiS_reqFifo_countReg + 2'd1 :
wsiS_reqFifo_countReg - 2'd1 ;
assign wsiS_reqFifo_countReg$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq != wsiS_reqFifo_r_deq$whas ;
// register wsiS_reqFifo_levelsValid
assign wsiS_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ;
assign wsiS_reqFifo_levelsValid$EN =
WILL_FIRE_RL_wmwt_mesg_ingress ||
WILL_FIRE_RL_wsipass_doMessagePush ||
WILL_FIRE_RL_wsiS_reqFifo_enq ||
WILL_FIRE_RL_wsiS_reqFifo_reset ;
// register wsiS_statusR
assign wsiS_statusR$D_IN =
{ wsiS_isReset_isInReset,
!wsiS_peerIsReady,
!wsiS_operateD,
wsiS_errorSticky,
wsiS_burstKind != 2'd0,
!wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget,
1'd0,
wsiS_trafficSticky } ;
assign wsiS_statusR$EN = 1'd1 ;
// register wsiS_tBusyCount
assign wsiS_tBusyCount$D_IN = wsiS_tBusyCount + 32'd1 ;
assign wsiS_tBusyCount$EN =
wsiS_operateD && wsiS_peerIsReady &&
(!wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget) ;
// register wsiS_trafficSticky
assign wsiS_trafficSticky$D_IN = 1'd1 ;
assign wsiS_trafficSticky$EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// register wsiS_wordCount
assign wsiS_wordCount$D_IN =
wsiS_wsiReq$wget[57] ? 12'd1 : wsiS_wordCount + 12'd1 ;
assign wsiS_wordCount$EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// submodule mesgRF
assign mesgRF$D_IN = v__h21048 ;
assign mesgRF$ENQ = WILL_FIRE_RL_rdSer_body ;
assign mesgRF$DEQ = WILL_FIRE_RL_wmrd_mesgBodyResponse ;
assign mesgRF$CLR = 1'b0 ;
// submodule mesgWF_memory
assign mesgWF_memory$ADDRA = mesgWF_rWrPtr[11:0] ;
assign mesgWF_memory$ADDRB =
WILL_FIRE_RL_wrtSer_body ?
x__h16107[11:0] :
mesgWF_rRdPtr[11:0] ;
assign mesgWF_memory$DIA = x__h16006 ;
assign mesgWF_memory$DIB = 32'hAAAAAAAA /* unspecified value */ ;
assign mesgWF_memory$WEA = WILL_FIRE_RL_wmwt_mesg_ingress ;
assign mesgWF_memory$WEB = 1'd0 ;
assign mesgWF_memory$ENA = 1'd1 ;
assign mesgWF_memory$ENB = 1'd1 ;
// submodule metaRF
assign metaRF$D_IN = v__h21048 ;
assign metaRF$ENQ = WILL_FIRE_RL_rdSer_begin ;
assign metaRF$DEQ = WILL_FIRE_RL_wmrd_mesgBegin ;
assign metaRF$CLR = 1'b0 ;
// submodule metaWF
assign metaWF$D_IN = { wsiS_reqFifo$D_OUT[7:0], btm__h18537 } ;
assign metaWF$ENQ = MUX_mesgWtCount$write_1__SEL_1 ;
assign metaWF$DEQ = WILL_FIRE_RL_wrtSer_begin ;
assign metaWF$CLR = 1'b0 ;
// submodule wci_wslv_reqF
assign wci_wslv_reqF$D_IN = wci_wslv_wciReq$wget ;
assign wci_wslv_reqF$ENQ = wci_wslv_wciReq$wget[71:69] != 3'd0 ;
assign wci_wslv_reqF$DEQ = wci_wslv_reqF_r_deq$whas ;
assign wci_wslv_reqF$CLR = 1'b0 ;
// submodule wide16Fa
assign wide16Fa$D_IN =
MUX_wide16Fa$enq_1__SEL_1 ?
MUX_wide16Fa$enq_1__VAL_1 :
MUX_wide16Fa$enq_1__VAL_2 ;
assign wide16Fa$ENQ =
WILL_FIRE_RL_wrtSer_begin &&
(wrtSerPos == 2'd3 || metaWF$D_OUT[23:0] == 24'd0) ||
WILL_FIRE_RL_wrtSer_body &&
(wrtSerPos == 2'd3 || wrtSerUnroll == 16'd1) ;
assign wide16Fa$DEQ = WILL_FIRE_RL_delay_write_req ;
assign wide16Fa$CLR = 1'b0 ;
// submodule wide16Fb
assign wide16Fb$D_IN = wmemi_respF$D_OUT[127:0] ;
assign wide16Fb$ENQ =
wmemi_respF$EMPTY_N && wide16Fb$FULL_N &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 ;
assign wide16Fb$DEQ = dlyReadCredit_acc_v2$whas ;
assign wide16Fb$CLR = 1'b0 ;
// submodule wide16Fc
assign wide16Fc$D_IN = wide16Fb$D_OUT ;
assign wide16Fc$ENQ = dlyReadCredit_acc_v2$whas ;
assign wide16Fc$DEQ =
MUX_rdSerEmpty$write_1__PSEL_1 &&
(rdSerEmpty || rdSerPos == 2'd0) ;
assign wide16Fc$CLR = 1'b0 ;
// submodule wmemi_respF
assign wmemi_respF$D_IN = wmemi_wmemiResponse$wget ;
assign wmemi_respF$ENQ =
wmemi_respF$FULL_N && wmemi_operateD && wmemi_peerIsReady &&
wmemi_wmemiResponse$wget[130:129] != 2'd0 ;
assign wmemi_respF$DEQ =
wmemi_respF$EMPTY_N && wide16Fb$FULL_N &&
wci_wslv_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 ;
assign wmemi_respF$CLR = 1'b0 ;
// submodule wsiS_reqFifo
assign wsiS_reqFifo$D_IN = wsiS_wsiReq$wget ;
assign wsiS_reqFifo$ENQ = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo$DEQ = wsiS_reqFifo_r_deq$whas ;
assign wsiS_reqFifo$CLR = 1'b0 ;
// remaining internal signals
assign IF_wrtSerPos_90_EQ_0_98_OR_wrtSerPos_90_EQ_1_9_ETC___d543 =
CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q2 &&
(wrtSerPos != 2'd3 && wrtSerUnroll != 16'd1 ||
CASE_wrtSerPos_NOT_wrtSerPos_EQ_3_OR_wide16Fa_ETC__q1) ;
assign IF_wrtSerPos_90_EQ_2_00_THEN_0x0_ELSE_mesgWF_w_ETC___d557 =
{ (wrtSerPos == 2'd2) ? 32'h0 : data__h19661,
(wrtSerPos == 2'd2) ? data__h19661 : wrtSerStage_2,
wrtSerStage_1,
wrtSerStage } ;
assign IF_wrtSerPos_90_EQ_2_00_THEN_0x0_ELSE_metaWF_f_ETC___d528 =
{ (wrtSerPos == 2'd2) ? 32'h0 : metaWF$D_OUT,
(wrtSerPos == 2'd2) ? metaWF$D_OUT : wrtSerStage_2,
wrtSerStage_1,
wrtSerStage } ;
assign NOT_mesgWF_rRdPtr_04_EQ_mesgWF_rWrPtr_95_31___d532 =
mesgWF_rRdPtr != mesgWF_rWrPtr ;
assign NOT_mesgWF_rRdPtr_04_PLUS_2048_60_EQ_mesgWF_rW_ETC___d462 =
mesgWF_rRdPtr + 13'd2048 != mesgWF_rWrPtr ;
assign NOT_wrtSerPos_90_EQ_3_91_92_AND_NOT_metaWF_fir_ETC___d506 =
wrtSerPos != 2'd3 && metaWF$D_OUT[23:0] != 24'd0 ||
CASE_wrtSerPos_NOT_wrtSerPos_EQ_3_OR_wide16Fa_ETC__q1 ;
assign addr__h20380 = { 9'd0, x__h20438 } ;
assign addr__h20732 = { 9'd0, x__h20777 } ;
assign btm__h18537 =
{ wsiS_reqFifo$D_OUT[56] ?
{ 10'd0, wsiS_reqFifo$D_OUT[55:44] } :
{ 8'd0, mesgLengthSoFar_73_PLUS_1___d909 },
2'd0 } ;
assign bytesWritten_86_ULT_dlyHoldoffBytes_65___d995 =
bytesWritten < dlyHoldoffBytes ;
assign cyclesPassed_56_ULT_dlyHoldoffCycles_68___d993 =
cyclesPassed < dlyHoldoffCycles ;
assign data__h19661 =
(mesgWF_rCache[45] && mesgWF_rCache[44:32] == mesgWF_rRdPtr) ?
mesgWF_rCache[31:0] :
mesgWF_memory$DOB ;
assign delayStatus__h23019 =
{ 14'h0,
!dlyWordsStored_value_17_SLE_0___d994 &&
!bytesWritten_86_ULT_dlyHoldoffBytes_65___d995 &&
!cyclesPassed_56_ULT_dlyHoldoffCycles_68___d993,
dlyWordsStored_value_17_SLE_0_64_OR_bytesWritt_ETC___d572,
dlyWordsStored_value_17_SLT_8388608___d574,
wsiM_reqFifo_c_r != 2'd2,
metaWF$FULL_N,
metaWF$EMPTY_N,
NOT_mesgWF_rRdPtr_04_PLUS_2048_60_EQ_mesgWF_rW_ETC___d462,
NOT_mesgWF_rRdPtr_04_EQ_mesgWF_rWrPtr_95_31___d532,
metaRF$FULL_N,
metaRF$EMPTY_N,
mesgRF$FULL_N,
mesgRF$EMPTY_N,
wide16Fa$FULL_N,
wide16Fa$EMPTY_N,
wide16Fb$FULL_N,
wide16Fb$EMPTY_N,
wide16Fc$FULL_N,
wide16Fc$EMPTY_N } ;
assign dlyWordsStored_value_17_SLE_0_64_OR_bytesWritt_ETC___d572 =
dlyWordsStored_value_17_SLE_0___d994 ||
bytesWritten_86_ULT_dlyHoldoffBytes_65___d995 ||
cyclesPassed_56_ULT_dlyHoldoffCycles_68___d993 ||
wsiM_reqFifo_c_r == 2'd2 ||
tog50 ;
assign dlyWordsStored_value_17_SLE_0___d994 =
(dlyWordsStored_value ^ 25'h1000000) <= 25'd16777216 ;
assign dlyWordsStored_value_17_SLT_8388608___d574 =
(dlyWordsStored_value ^ 25'h1000000) < 25'd25165824 ;
assign mesgLengthSoFar_73_PLUS_1___d909 = mesgLengthSoFar + 14'd1 ;
assign mesgRF_i_notFull__71_AND_NOT_rdSerEmpty_21_22__ETC___d672 =
mesgRF$FULL_N &&
(!rdSerEmpty && rdSerPos != 2'd0 || wide16Fc$EMPTY_N) ;
assign metaRF_i_notFull__20_AND_NOT_rdSerEmpty_21_22__ETC___d631 =
metaRF$FULL_N &&
(!rdSerEmpty && rdSerPos != 2'd0 || wide16Fc$EMPTY_N) ;
assign rdat__h23426 = hasDebugLogic ? mesgWtCount : 32'd0 ;
assign rdat__h23432 = hasDebugLogic ? mesgRdCount : 32'd0 ;
assign rdat__h23438 = hasDebugLogic ? bytesWritten : 32'd0 ;
assign rdat__h23444 = hasDebugLogic ? { 8'd0, x__h23448 } : 32'd0 ;
assign rdat__h23568 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h23582 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h23590 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ;
assign rdat__h23596 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h23610 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h23618 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ;
assign rdat__h23624 = hasDebugLogic ? wmemiWrReq : 32'd0 ;
assign rdat__h23630 = hasDebugLogic ? wmemiRdReq : 32'd0 ;
assign rdat__h23636 = hasDebugLogic ? wmemiRdResp1 : 32'd0 ;
assign rdat__h23642 =
hasDebugLogic ?
{ {7{dlyWordsStored_value[24]}}, dlyWordsStored_value } :
32'd0 ;
assign rdat__h23653 =
hasDebugLogic ?
{ {24{dlyReadCredit_value[7]}}, dlyReadCredit_value } :
32'd0 ;
assign rdat__h23664 = hasDebugLogic ? { 9'd0, dlyWAG } : 32'd0 ;
assign rdat__h23675 = hasDebugLogic ? { 9'd0, dlyRAG } : 32'd0 ;
assign rdat__h23696 = hasDebugLogic ? wmemiRdResp2 : 32'd0 ;
assign rdat__h23751 =
{ {16{dlyReadyToWrite_value[15]}}, dlyReadyToWrite_value } ;
assign rdat__h23760 = { 16'd0, wrtSerUnroll } ;
assign rdat__h23769 = { 8'd0, bytesThisMessage } ;
assign rdat__h23778 = { 18'd0, mesgLengthSoFar } ;
assign wci_wslv_cState_6_EQ_2_7_AND_dlyCtrl_48_BITS_3_ETC___d592 =
wci_wslv_cState == 3'd2 && dlyCtrl[3:0] == 4'h7 &&
!dlyWordsStored_value_17_SLE_0___d994 &&
!bytesWritten_86_ULT_dlyHoldoffBytes_65___d995 &&
!cyclesPassed_56_ULT_dlyHoldoffCycles_68___d993 ;
assign wrtSerPos_90_PLUS_1___d908 = wrtSerPos + 2'd1 ;
assign x__h16006 =
WILL_FIRE_RL_wmwt_mesg_ingress ?
wsiS_reqFifo$D_OUT[43:12] :
32'd0 ;
assign x__h16107 = mesgWF_rRdPtr + 13'd1 ;
assign x__h19290 = { 96'd0, metaWF$D_OUT } ;
assign x__h19317 = { 64'd0, metaWF$D_OUT, wrtSerStage } ;
assign x__h19946 = { 96'd0, data__h19661 } ;
assign x__h19970 = { 64'd0, data__h19661, wrtSerStage } ;
assign x__h20438 = { dlyWAG, 4'h0 } ;
assign x__h20777 = { dlyRAG, 4'h0 } ;
assign x__h23448 = { wmemi_statusR, wsiS_statusR, wsiM_statusR } ;
assign x_burstLength__h22925 =
(readMeta[23:0] == 24'd0) ? 12'd1 : readMeta[13:2] ;
assign x_byteEn__h22926 = (readMeta[23:0] == 24'd0) ? 4'd0 : 4'd15 ;
always@(rdSerPos or
rdSerStage_3 or wide16Fc$D_OUT or rdSerStage_1 or rdSerStage_2)
begin
case (rdSerPos)
2'd0: v__h21048 = wide16Fc$D_OUT[31:0];
2'd1: v__h21048 = rdSerStage_1;
2'd2: v__h21048 = rdSerStage_2;
2'd3: v__h21048 = rdSerStage_3;
endcase
end
always@(wrtSerPos or wide16Fa$FULL_N)
begin
case (wrtSerPos)
2'd0, 2'd1, 2'd2:
CASE_wrtSerPos_NOT_wrtSerPos_EQ_3_OR_wide16Fa_ETC__q1 =
wide16Fa$FULL_N;
2'd3:
CASE_wrtSerPos_NOT_wrtSerPos_EQ_3_OR_wide16Fa_ETC__q1 =
wrtSerPos != 2'd3 || wide16Fa$FULL_N;
endcase
end
always@(wrtSerPos)
begin
case (wrtSerPos)
2'd0, 2'd1, 2'd2, 2'd3: CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q2 = 1'd1;
endcase
end
always@(wci_wslv_reqF$D_OUT or
dlyCtrl or
dlyHoldoffBytes or
dlyHoldoffCycles or
rdat__h23426 or
rdat__h23432 or
rdat__h23438 or
rdat__h23444 or
rdat__h23568 or
rdat__h23582 or
rdat__h23590 or
rdat__h23596 or
rdat__h23610 or
rdat__h23618 or
rdat__h23624 or
rdat__h23630 or
rdat__h23636 or
rdat__h23642 or
rdat__h23653 or
rdat__h23664 or
rdat__h23675 or
dlyRdOpZero or
dlyRdOpOther or
rdat__h23696 or
delayStatus__h23019 or
rdat__h23751 or rdat__h23760 or rdat__h23769 or rdat__h23778)
begin
case (wci_wslv_reqF$D_OUT[63:32])
32'h0: g_data__h23399 = dlyCtrl;
32'h00000004: g_data__h23399 = dlyHoldoffBytes;
32'h00000008: g_data__h23399 = dlyHoldoffCycles;
32'h0000000C: g_data__h23399 = rdat__h23426;
32'h00000010: g_data__h23399 = rdat__h23432;
32'h00000014: g_data__h23399 = rdat__h23438;
32'h00000018: g_data__h23399 = rdat__h23444;
32'h0000001C: g_data__h23399 = 32'd0;
32'h00000020: g_data__h23399 = rdat__h23568;
32'h00000024: g_data__h23399 = rdat__h23582;
32'h00000028: g_data__h23399 = rdat__h23590;
32'h0000002C: g_data__h23399 = rdat__h23596;
32'h00000030: g_data__h23399 = rdat__h23610;
32'h00000034: g_data__h23399 = rdat__h23618;
32'h00000038: g_data__h23399 = rdat__h23624;
32'h0000003C: g_data__h23399 = rdat__h23630;
32'h00000040: g_data__h23399 = rdat__h23636;
32'h00000044: g_data__h23399 = rdat__h23642;
32'h00000048: g_data__h23399 = rdat__h23653;
32'h0000004C: g_data__h23399 = rdat__h23664;
32'h00000050: g_data__h23399 = rdat__h23675;
32'h00000058: g_data__h23399 = dlyRdOpZero;
32'h0000005C: g_data__h23399 = dlyRdOpOther;
32'h00000060: g_data__h23399 = rdat__h23696;
32'h00000064: g_data__h23399 = delayStatus__h23019;
32'h00000068: g_data__h23399 = rdat__h23751;
32'h0000006C: g_data__h23399 = rdat__h23760;
32'h00000070: g_data__h23399 = rdat__h23769;
32'h00000074: g_data__h23399 = rdat__h23778;
default: g_data__h23399 = 32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
bytesRead <= `BSV_ASSIGNMENT_DELAY 32'd0;
bytesThisMessage <= `BSV_ASSIGNMENT_DELAY 24'd0;
bytesWritten <= `BSV_ASSIGNMENT_DELAY 32'd0;
cyclesPassed <= `BSV_ASSIGNMENT_DELAY 32'd0;
dlyCtrl <= `BSV_ASSIGNMENT_DELAY dlyCtrlInit;
dlyHoldoffBytes <= `BSV_ASSIGNMENT_DELAY 32'd0;
dlyHoldoffCycles <= `BSV_ASSIGNMENT_DELAY 32'd0;
dlyRAG <= `BSV_ASSIGNMENT_DELAY 23'd0;
dlyRdOpOther <= `BSV_ASSIGNMENT_DELAY 32'd0;
dlyRdOpZero <= `BSV_ASSIGNMENT_DELAY 32'd0;
dlyReadCredit_value <= `BSV_ASSIGNMENT_DELAY 8'd0;
dlyReadyToWrite_value <= `BSV_ASSIGNMENT_DELAY 16'd0;
dlyWAG <= `BSV_ASSIGNMENT_DELAY 23'd0;
dlyWordsStored_value <= `BSV_ASSIGNMENT_DELAY 25'd0;
mesgLengthSoFar <= `BSV_ASSIGNMENT_DELAY 14'd0;
mesgRdCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
mesgWF_rCache <= `BSV_ASSIGNMENT_DELAY 46'h0AAAAAAAAAAA;
mesgWF_rRdPtr <= `BSV_ASSIGNMENT_DELAY 13'd0;
mesgWF_rWrPtr <= `BSV_ASSIGNMENT_DELAY 13'd0;
mesgWtCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
rdSerAddr <= `BSV_ASSIGNMENT_DELAY 32'd0;
rdSerEmpty <= `BSV_ASSIGNMENT_DELAY 1'd1;
rdSerPos <= `BSV_ASSIGNMENT_DELAY 2'd0;
rdSerUnroll <= `BSV_ASSIGNMENT_DELAY 16'd0;
rdSyncWord <= `BSV_ASSIGNMENT_DELAY 1'd0;
tog50 <= `BSV_ASSIGNMENT_DELAY 1'd0;
unrollCnt <= `BSV_ASSIGNMENT_DELAY 16'd0;
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmemiRdReq <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmemiRdResp1 <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmemiRdResp2 <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmemiWrReq <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmemi_busyWithMessage <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmemi_dhF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmemi_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY
146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmemi_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY
146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmemi_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmemi_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmemi_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmemi_reqF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmemi_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 52'h0AAAAAAAAAAAA;
wmemi_reqF_q_1 <= `BSV_ASSIGNMENT_DELAY 52'h0AAAAAAAAAAAA;
wmemi_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wrtSerAddr <= `BSV_ASSIGNMENT_DELAY 32'd0;
wrtSerPos <= `BSV_ASSIGNMENT_DELAY 2'd0;
wrtSerUnroll <= `BSV_ASSIGNMENT_DELAY 16'd0;
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
end
else
begin
if (bytesRead$EN) bytesRead <= `BSV_ASSIGNMENT_DELAY bytesRead$D_IN;
if (bytesThisMessage$EN)
bytesThisMessage <= `BSV_ASSIGNMENT_DELAY bytesThisMessage$D_IN;
if (bytesWritten$EN)
bytesWritten <= `BSV_ASSIGNMENT_DELAY bytesWritten$D_IN;
if (cyclesPassed$EN)
cyclesPassed <= `BSV_ASSIGNMENT_DELAY cyclesPassed$D_IN;
if (dlyCtrl$EN) dlyCtrl <= `BSV_ASSIGNMENT_DELAY dlyCtrl$D_IN;
if (dlyHoldoffBytes$EN)
dlyHoldoffBytes <= `BSV_ASSIGNMENT_DELAY dlyHoldoffBytes$D_IN;
if (dlyHoldoffCycles$EN)
dlyHoldoffCycles <= `BSV_ASSIGNMENT_DELAY dlyHoldoffCycles$D_IN;
if (dlyRAG$EN) dlyRAG <= `BSV_ASSIGNMENT_DELAY dlyRAG$D_IN;
if (dlyRdOpOther$EN)
dlyRdOpOther <= `BSV_ASSIGNMENT_DELAY dlyRdOpOther$D_IN;
if (dlyRdOpZero$EN)
dlyRdOpZero <= `BSV_ASSIGNMENT_DELAY dlyRdOpZero$D_IN;
if (dlyReadCredit_value$EN)
dlyReadCredit_value <= `BSV_ASSIGNMENT_DELAY
dlyReadCredit_value$D_IN;
if (dlyReadyToWrite_value$EN)
dlyReadyToWrite_value <= `BSV_ASSIGNMENT_DELAY
dlyReadyToWrite_value$D_IN;
if (dlyWAG$EN) dlyWAG <= `BSV_ASSIGNMENT_DELAY dlyWAG$D_IN;
if (dlyWordsStored_value$EN)
dlyWordsStored_value <= `BSV_ASSIGNMENT_DELAY
dlyWordsStored_value$D_IN;
if (mesgLengthSoFar$EN)
mesgLengthSoFar <= `BSV_ASSIGNMENT_DELAY mesgLengthSoFar$D_IN;
if (mesgRdCount$EN)
mesgRdCount <= `BSV_ASSIGNMENT_DELAY mesgRdCount$D_IN;
if (mesgWF_rCache$EN)
mesgWF_rCache <= `BSV_ASSIGNMENT_DELAY mesgWF_rCache$D_IN;
if (mesgWF_rRdPtr$EN)
mesgWF_rRdPtr <= `BSV_ASSIGNMENT_DELAY mesgWF_rRdPtr$D_IN;
if (mesgWF_rWrPtr$EN)
mesgWF_rWrPtr <= `BSV_ASSIGNMENT_DELAY mesgWF_rWrPtr$D_IN;
if (mesgWtCount$EN)
mesgWtCount <= `BSV_ASSIGNMENT_DELAY mesgWtCount$D_IN;
if (rdSerAddr$EN) rdSerAddr <= `BSV_ASSIGNMENT_DELAY rdSerAddr$D_IN;
if (rdSerEmpty$EN)
rdSerEmpty <= `BSV_ASSIGNMENT_DELAY rdSerEmpty$D_IN;
if (rdSerPos$EN) rdSerPos <= `BSV_ASSIGNMENT_DELAY rdSerPos$D_IN;
if (rdSerUnroll$EN)
rdSerUnroll <= `BSV_ASSIGNMENT_DELAY rdSerUnroll$D_IN;
if (rdSyncWord$EN)
rdSyncWord <= `BSV_ASSIGNMENT_DELAY rdSyncWord$D_IN;
if (tog50$EN) tog50 <= `BSV_ASSIGNMENT_DELAY tog50$D_IN;
if (unrollCnt$EN) unrollCnt <= `BSV_ASSIGNMENT_DELAY unrollCnt$D_IN;
if (wci_wslv_cEdge$EN)
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY wci_wslv_cEdge$D_IN;
if (wci_wslv_cState$EN)
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY wci_wslv_cState$D_IN;
if (wci_wslv_ctlAckReg$EN)
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_ctlAckReg$D_IN;
if (wci_wslv_ctlOpActive$EN)
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY
wci_wslv_ctlOpActive$D_IN;
if (wci_wslv_illegalEdge$EN)
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY
wci_wslv_illegalEdge$D_IN;
if (wci_wslv_nState$EN)
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY wci_wslv_nState$D_IN;
if (wci_wslv_reqF_countReg$EN)
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY
wci_wslv_reqF_countReg$D_IN;
if (wci_wslv_respF_c_r$EN)
wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN;
if (wci_wslv_respF_q_0$EN)
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN;
if (wci_wslv_respF_q_1$EN)
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_1$D_IN;
if (wci_wslv_sFlagReg$EN)
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_sFlagReg$D_IN;
if (wci_wslv_sThreadBusy_d$EN)
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wci_wslv_sThreadBusy_d$D_IN;
if (wmemiRdReq$EN)
wmemiRdReq <= `BSV_ASSIGNMENT_DELAY wmemiRdReq$D_IN;
if (wmemiRdResp1$EN)
wmemiRdResp1 <= `BSV_ASSIGNMENT_DELAY wmemiRdResp1$D_IN;
if (wmemiRdResp2$EN)
wmemiRdResp2 <= `BSV_ASSIGNMENT_DELAY wmemiRdResp2$D_IN;
if (wmemiWrReq$EN)
wmemiWrReq <= `BSV_ASSIGNMENT_DELAY wmemiWrReq$D_IN;
if (wmemi_busyWithMessage$EN)
wmemi_busyWithMessage <= `BSV_ASSIGNMENT_DELAY
wmemi_busyWithMessage$D_IN;
if (wmemi_dhF_c_r$EN)
wmemi_dhF_c_r <= `BSV_ASSIGNMENT_DELAY wmemi_dhF_c_r$D_IN;
if (wmemi_dhF_q_0$EN)
wmemi_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY wmemi_dhF_q_0$D_IN;
if (wmemi_dhF_q_1$EN)
wmemi_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY wmemi_dhF_q_1$D_IN;
if (wmemi_errorSticky$EN)
wmemi_errorSticky <= `BSV_ASSIGNMENT_DELAY wmemi_errorSticky$D_IN;
if (wmemi_operateD$EN)
wmemi_operateD <= `BSV_ASSIGNMENT_DELAY wmemi_operateD$D_IN;
if (wmemi_peerIsReady$EN)
wmemi_peerIsReady <= `BSV_ASSIGNMENT_DELAY wmemi_peerIsReady$D_IN;
if (wmemi_reqF_c_r$EN)
wmemi_reqF_c_r <= `BSV_ASSIGNMENT_DELAY wmemi_reqF_c_r$D_IN;
if (wmemi_reqF_q_0$EN)
wmemi_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wmemi_reqF_q_0$D_IN;
if (wmemi_reqF_q_1$EN)
wmemi_reqF_q_1 <= `BSV_ASSIGNMENT_DELAY wmemi_reqF_q_1$D_IN;
if (wmemi_trafficSticky$EN)
wmemi_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wmemi_trafficSticky$D_IN;
if (wrtSerAddr$EN)
wrtSerAddr <= `BSV_ASSIGNMENT_DELAY wrtSerAddr$D_IN;
if (wrtSerPos$EN) wrtSerPos <= `BSV_ASSIGNMENT_DELAY wrtSerPos$D_IN;
if (wrtSerUnroll$EN)
wrtSerUnroll <= `BSV_ASSIGNMENT_DELAY wrtSerUnroll$D_IN;
if (wsiM_burstKind$EN)
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind$D_IN;
if (wsiM_errorSticky$EN)
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky$D_IN;
if (wsiM_iMesgCount$EN)
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount$D_IN;
if (wsiM_operateD$EN)
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD$D_IN;
if (wsiM_pMesgCount$EN)
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN;
if (wsiM_peerIsReady$EN)
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN;
if (wsiM_reqFifo_c_r$EN)
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN;
if (wsiM_reqFifo_q_0$EN)
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN;
if (wsiM_reqFifo_q_1$EN)
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1$D_IN;
if (wsiM_sThreadBusy_d$EN)
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d$D_IN;
if (wsiM_tBusyCount$EN)
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount$D_IN;
if (wsiM_trafficSticky$EN)
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky$D_IN;
if (wsiS_burstKind$EN)
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind$D_IN;
if (wsiS_errorSticky$EN)
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky$D_IN;
if (wsiS_iMesgCount$EN)
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount$D_IN;
if (wsiS_operateD$EN)
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD$D_IN;
if (wsiS_pMesgCount$EN)
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount$D_IN;
if (wsiS_peerIsReady$EN)
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady$D_IN;
if (wsiS_reqFifo_countReg$EN)
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_countReg$D_IN;
if (wsiS_reqFifo_levelsValid$EN)
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_levelsValid$D_IN;
if (wsiS_tBusyCount$EN)
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount$D_IN;
if (wsiS_trafficSticky$EN)
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky$D_IN;
if (wsiS_wordCount$EN)
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount$D_IN;
end
if (rdSerMeta$EN) rdSerMeta <= `BSV_ASSIGNMENT_DELAY rdSerMeta$D_IN;
if (rdSerStage$EN) rdSerStage <= `BSV_ASSIGNMENT_DELAY rdSerStage$D_IN;
if (rdSerStage_1$EN)
rdSerStage_1 <= `BSV_ASSIGNMENT_DELAY rdSerStage_1$D_IN;
if (rdSerStage_2$EN)
rdSerStage_2 <= `BSV_ASSIGNMENT_DELAY rdSerStage_2$D_IN;
if (rdSerStage_3$EN)
rdSerStage_3 <= `BSV_ASSIGNMENT_DELAY rdSerStage_3$D_IN;
if (readMeta$EN) readMeta <= `BSV_ASSIGNMENT_DELAY readMeta$D_IN;
if (wmemi_statusR$EN)
wmemi_statusR <= `BSV_ASSIGNMENT_DELAY wmemi_statusR$D_IN;
if (wrtSerStage$EN) wrtSerStage <= `BSV_ASSIGNMENT_DELAY wrtSerStage$D_IN;
if (wrtSerStage_1$EN)
wrtSerStage_1 <= `BSV_ASSIGNMENT_DELAY wrtSerStage_1$D_IN;
if (wrtSerStage_2$EN)
wrtSerStage_2 <= `BSV_ASSIGNMENT_DELAY wrtSerStage_2$D_IN;
if (wrtSerStage_3$EN)
wrtSerStage_3 <= `BSV_ASSIGNMENT_DELAY wrtSerStage_3$D_IN;
if (wsiM_statusR$EN)
wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR$D_IN;
if (wsiS_mesgWordLength$EN)
wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength$D_IN;
if (wsiS_statusR$EN)
wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN;
end
always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmemi_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wci_wslv_isReset_isInReset$EN)
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wci_wslv_isReset_isInReset$D_IN;
if (wmemi_isReset_isInReset$EN)
wmemi_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wmemi_isReset_isInReset$D_IN;
if (wsiM_isReset_isInReset$EN)
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiM_isReset_isInReset$D_IN;
if (wsiS_isReset_isInReset$EN)
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiS_isReset_isInReset$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
bytesRead = 32'hAAAAAAAA;
bytesThisMessage = 24'hAAAAAA;
bytesWritten = 32'hAAAAAAAA;
cyclesPassed = 32'hAAAAAAAA;
dlyCtrl = 32'hAAAAAAAA;
dlyHoldoffBytes = 32'hAAAAAAAA;
dlyHoldoffCycles = 32'hAAAAAAAA;
dlyRAG = 23'h2AAAAA;
dlyRdOpOther = 32'hAAAAAAAA;
dlyRdOpZero = 32'hAAAAAAAA;
dlyReadCredit_value = 8'hAA;
dlyReadyToWrite_value = 16'hAAAA;
dlyWAG = 23'h2AAAAA;
dlyWordsStored_value = 25'h0AAAAAA;
mesgLengthSoFar = 14'h2AAA;
mesgRdCount = 32'hAAAAAAAA;
mesgWF_rCache = 46'h2AAAAAAAAAAA;
mesgWF_rRdPtr = 13'h0AAA;
mesgWF_rWrPtr = 13'h0AAA;
mesgWtCount = 32'hAAAAAAAA;
rdSerAddr = 32'hAAAAAAAA;
rdSerEmpty = 1'h0;
rdSerMeta = 32'hAAAAAAAA;
rdSerPos = 2'h2;
rdSerStage = 32'hAAAAAAAA;
rdSerStage_1 = 32'hAAAAAAAA;
rdSerStage_2 = 32'hAAAAAAAA;
rdSerStage_3 = 32'hAAAAAAAA;
rdSerUnroll = 16'hAAAA;
rdSyncWord = 1'h0;
readMeta = 32'hAAAAAAAA;
tog50 = 1'h0;
unrollCnt = 16'hAAAA;
wci_wslv_cEdge = 3'h2;
wci_wslv_cState = 3'h2;
wci_wslv_ctlAckReg = 1'h0;
wci_wslv_ctlOpActive = 1'h0;
wci_wslv_illegalEdge = 1'h0;
wci_wslv_isReset_isInReset = 1'h0;
wci_wslv_nState = 3'h2;
wci_wslv_reqF_countReg = 2'h2;
wci_wslv_respF_c_r = 2'h2;
wci_wslv_respF_q_0 = 34'h2AAAAAAAA;
wci_wslv_respF_q_1 = 34'h2AAAAAAAA;
wci_wslv_sFlagReg = 1'h0;
wci_wslv_sThreadBusy_d = 1'h0;
wmemiRdReq = 32'hAAAAAAAA;
wmemiRdResp1 = 32'hAAAAAAAA;
wmemiRdResp2 = 32'hAAAAAAAA;
wmemiWrReq = 32'hAAAAAAAA;
wmemi_busyWithMessage = 1'h0;
wmemi_dhF_c_r = 2'h2;
wmemi_dhF_q_0 = 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmemi_dhF_q_1 = 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmemi_errorSticky = 1'h0;
wmemi_isReset_isInReset = 1'h0;
wmemi_operateD = 1'h0;
wmemi_peerIsReady = 1'h0;
wmemi_reqF_c_r = 2'h2;
wmemi_reqF_q_0 = 52'hAAAAAAAAAAAAA;
wmemi_reqF_q_1 = 52'hAAAAAAAAAAAAA;
wmemi_statusR = 8'hAA;
wmemi_trafficSticky = 1'h0;
wrtSerAddr = 32'hAAAAAAAA;
wrtSerPos = 2'h2;
wrtSerStage = 32'hAAAAAAAA;
wrtSerStage_1 = 32'hAAAAAAAA;
wrtSerStage_2 = 32'hAAAAAAAA;
wrtSerStage_3 = 32'hAAAAAAAA;
wrtSerUnroll = 16'hAAAA;
wsiM_burstKind = 2'h2;
wsiM_errorSticky = 1'h0;
wsiM_iMesgCount = 32'hAAAAAAAA;
wsiM_isReset_isInReset = 1'h0;
wsiM_operateD = 1'h0;
wsiM_pMesgCount = 32'hAAAAAAAA;
wsiM_peerIsReady = 1'h0;
wsiM_reqFifo_c_r = 2'h2;
wsiM_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA;
wsiM_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA;
wsiM_sThreadBusy_d = 1'h0;
wsiM_statusR = 8'hAA;
wsiM_tBusyCount = 32'hAAAAAAAA;
wsiM_trafficSticky = 1'h0;
wsiS_burstKind = 2'h2;
wsiS_errorSticky = 1'h0;
wsiS_iMesgCount = 32'hAAAAAAAA;
wsiS_isReset_isInReset = 1'h0;
wsiS_mesgWordLength = 12'hAAA;
wsiS_operateD = 1'h0;
wsiS_pMesgCount = 32'hAAAAAAAA;
wsiS_peerIsReady = 1'h0;
wsiS_reqFifo_countReg = 2'h2;
wsiS_reqFifo_levelsValid = 1'h0;
wsiS_statusR = 8'hAA;
wsiS_tBusyCount = 32'hAAAAAAAA;
wsiS_trafficSticky = 1'h0;
wsiS_wordCount = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
begin
v__h3739 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3739,
wci_wslv_reqF$D_OUT[36:34],
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO)
begin
v__h24065 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO)
$display("[%0d]: %m: Starting DelayWorker dlyCtrl:%0x",
v__h24065,
dlyCtrl);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DelayWorker.bsv\", line 380, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/DelayWorker.bsv\", line 380, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/DelayWorker.bsv\", line 380, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/wrk/DelayWorker.bsv\", line 380, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DelayWorker.bsv\", line 380, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/DelayWorker.bsv\", line 380, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/DelayWorker.bsv\", line 380, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DelayWorker.bsv\", line 380, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DelayWorker.bsv\", line 380, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/DelayWorker.bsv\", line 380, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
begin
v__h4058 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h4058,
wci_wslv_cEdge,
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
begin
v__h3914 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h3914,
wci_wslv_cEdge,
wci_wslv_cState,
wci_wslv_nState);
end
// synopsys translate_on
endmodule // mkDelayWorker4B
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAH_FUNCTIONAL_V
`define SKY130_FD_SC_LP__FAH_FUNCTIONAL_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__fah (
COUT,
SUM ,
A ,
B ,
CI
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Local signals
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM, A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAH_FUNCTIONAL_V |
// FIXME:
//
// Any l2 cache pipe can go to any directory (and viceversa). The reason is to
// allow a per bank SMT option (dc_pipe and l2_pipe) and to handle the TLB
// misses that can go out of bank.
//
// Effectively, a 4 pipe dual core can switch to a 8 independent l2 coherent
// cores. No need to have a switch command as the DCs and L2s are coherent.
module net_2core2dr(
/* verilator lint_off UNUSED */
/* verilator lint_off UNDRIVEN */
input clk
,input reset
// c0 core L2I
,input logic c0_l2itodr_req_valid
,output logic c0_l2itodr_req_retry
,input I_l2todr_req_type c0_l2itodr_req
,output logic c0_drtol2i_snack_valid
,input logic c0_drtol2i_snack_retry
,output I_drtol2_snack_type c0_drtol2i_snack
,input c0_l2itodr_snoop_ack_valid
,output c0_l2itodr_snoop_ack_retry
,input I_l2snoop_ack_type c0_l2itodr_snoop_ack
,input logic c0_l2itodr_disp_valid
,output logic c0_l2itodr_disp_retry
,input I_l2todr_disp_type c0_l2itodr_disp
,output logic c0_drtol2i_dack_valid
,input logic c0_drtol2i_dack_retry
,output I_drtol2_dack_type c0_drtol2i_dack
,input logic c0_l2itodr_pfreq_valid
,output logic c0_l2itodr_pfreq_retry
,input I_l2todr_pfreq_type c0_l2itodr_pfreq
// c0 core L2I TLB
,input logic c0_l2ittodr_req_valid
,output logic c0_l2ittodr_req_retry
,input I_l2todr_req_type c0_l2ittodr_req
,output logic c0_drtol2it_snack_valid
,input logic c0_drtol2it_snack_retry
,output I_drtol2_snack_type c0_drtol2it_snack
,input c0_l2ittodr_snoop_ack_valid
,output c0_l2ittodr_snoop_ack_retry
,input I_l2snoop_ack_type c0_l2ittodr_snoop_ack
,input logic c0_l2ittodr_disp_valid
,output logic c0_l2ittodr_disp_retry
,input I_l2todr_disp_type c0_l2ittodr_disp
,output logic c0_drtol2it_dack_valid
,input logic c0_drtol2it_dack_retry
,output I_drtol2_dack_type c0_drtol2it_dack
// c0 core L2D
,input logic c0_l2d_0todr_req_valid
,output logic c0_l2d_0todr_req_retry
,input I_l2todr_req_type c0_l2d_0todr_req
,output logic c0_drtol2d_0_snack_valid
,input logic c0_drtol2d_0_snack_retry
,output I_drtol2_snack_type c0_drtol2d_0_snack
,input c0_l2d_0todr_snoop_ack_valid
,output c0_l2d_0todr_snoop_ack_retry
,input I_l2snoop_ack_type c0_l2d_0todr_snoop_ack
,input logic c0_l2d_0todr_disp_valid
,output logic c0_l2d_0todr_disp_retry
,input I_l2todr_disp_type c0_l2d_0todr_disp
,output logic c0_drtol2d_0_dack_valid
,input logic c0_drtol2d_0_dack_retry
,output I_drtol2_dack_type c0_drtol2d_0_dack
,input logic c0_l2d_0todr_pfreq_valid
,output logic c0_l2d_0todr_pfreq_retry
,input I_l2todr_pfreq_type c0_l2d_0todr_pfreq
// c0 core L2D TLB
,input logic c0_l2dt_0todr_req_valid
,output logic c0_l2dt_0todr_req_retry
,input I_l2todr_req_type c0_l2dt_0todr_req
,output logic c0_drtol2dt_0_snack_valid
,input logic c0_drtol2dt_0_snack_retry
,output I_drtol2_snack_type c0_drtol2dt_0_snack
,input c0_l2dt_0todr_snoop_ack_valid
,output c0_l2dt_0todr_snoop_ack_retry
,input I_l2snoop_ack_type c0_l2dt_0todr_snoop_ack
,input logic c0_l2dt_0todr_disp_valid
,output logic c0_l2dt_0todr_disp_retry
,input I_l2todr_disp_type c0_l2dt_0todr_disp
,output logic c0_drtol2dt_0_dack_valid
,input logic c0_drtol2dt_0_dack_retry
,output I_drtol2_dack_type c0_drtol2dt_0_dack
// c1 core L2I
,input logic c1_l2itodr_req_valid
,output logic c1_l2itodr_req_retry
,input I_l2todr_req_type c1_l2itodr_req
,output logic c1_drtol2i_snack_valid
,input logic c1_drtol2i_snack_retry
,output I_drtol2_snack_type c1_drtol2i_snack
,input c1_l2itodr_snoop_ack_valid
,output c1_l2itodr_snoop_ack_retry
,input I_l2snoop_ack_type c1_l2itodr_snoop_ack
,input logic c1_l2itodr_disp_valid
,output logic c1_l2itodr_disp_retry
,input I_l2todr_disp_type c1_l2itodr_disp
,output logic c1_drtol2i_dack_valid
,input logic c1_drtol2i_dack_retry
,output I_drtol2_dack_type c1_drtol2i_dack
,input logic c1_l2itodr_pfreq_valid
,output logic c1_l2itodr_pfreq_retry
,input I_l2todr_pfreq_type c1_l2itodr_pfreq
// c1 core L2I TLB
,input logic c1_l2ittodr_req_valid
,output logic c1_l2ittodr_req_retry
,input I_l2todr_req_type c1_l2ittodr_req
,output logic c1_drtol2it_snack_valid
,input logic c1_drtol2it_snack_retry
,output I_drtol2_snack_type c1_drtol2it_snack
,input c1_l2ittodr_snoop_ack_valid
,output c1_l2ittodr_snoop_ack_retry
,input I_l2snoop_ack_type c1_l2ittodr_snoop_ack
,input logic c1_l2ittodr_disp_valid
,output logic c1_l2ittodr_disp_retry
,input I_l2todr_disp_type c1_l2ittodr_disp
,output logic c1_drtol2it_dack_valid
,input logic c1_drtol2it_dack_retry
,output I_drtol2_dack_type c1_drtol2it_dack
// c1 core L2D
,input logic c1_l2d_0todr_req_valid
,output logic c1_l2d_0todr_req_retry
,input I_l2todr_req_type c1_l2d_0todr_req
,output logic c1_drtol2d_0_snack_valid
,input logic c1_drtol2d_0_snack_retry
,output I_drtol2_snack_type c1_drtol2d_0_snack
,input c1_l2d_0todr_snoop_ack_valid
,output c1_l2d_0todr_snoop_ack_retry
,input I_l2snoop_ack_type c1_l2d_0todr_snoop_ack
,input logic c1_l2d_0todr_disp_valid
,output logic c1_l2d_0todr_disp_retry
,input I_l2todr_disp_type c1_l2d_0todr_disp
,output logic c1_drtol2d_0_dack_valid
,input logic c1_drtol2d_0_dack_retry
,output I_drtol2_dack_type c1_drtol2d_0_dack
,input logic c1_l2d_0todr_pfreq_valid
,output logic c1_l2d_0todr_pfreq_retry
,input I_l2todr_pfreq_type c1_l2d_0todr_pfreq
// c1 core L2D TLB
,input logic c1_l2dt_0todr_req_valid
,output logic c1_l2dt_0todr_req_retry
,input I_l2todr_req_type c1_l2dt_0todr_req
,output logic c1_drtol2dt_0_snack_valid
,input logic c1_drtol2dt_0_snack_retry
,output I_drtol2_snack_type c1_drtol2dt_0_snack
,input c1_l2dt_0todr_snoop_ack_valid
,output c1_l2dt_0todr_snoop_ack_retry
,input I_l2snoop_ack_type c1_l2dt_0todr_snoop_ack
,input logic c1_l2dt_0todr_disp_valid
,output logic c1_l2dt_0todr_disp_retry
,input I_l2todr_disp_type c1_l2dt_0todr_disp
,output logic c1_drtol2dt_0_dack_valid
,input logic c1_drtol2dt_0_dack_retry
,output I_drtol2_dack_type c1_drtol2dt_0_dack
// directory 0
,output l2todr0_req_valid
,input l2todr0_req_retry
,output I_l2todr_req_type l2todr0_req
,input dr0tol2_snack_valid
,output dr0tol2_snack_retry
,input I_drtol2_snack_type dr0tol2_snack
,output l2todr0_disp_valid
,input l2todr0_disp_retry
,output I_l2todr_disp_type l2todr0_disp
,input dr0tol2_dack_valid
,output dr0tol2_dack_retry
,input I_drtol2_dack_type dr0tol2_dack
,output l2todr0_snoop_ack_valid
,input l2todr0_snoop_ack_retry
,output I_drsnoop_ack_type l2todr0_snoop_ack
,output logic l2todr0_pfreq_valid
,input logic l2todr0_pfreq_retry
,output I_l2todr_pfreq_type l2todr0_pfreq
// directory 1
,output l2todr1_req_valid
,input l2todr1_req_retry
,output I_l2todr_req_type l2todr1_req
,input dr1tol2_snack_valid
,output dr1tol2_snack_retry
,input I_drtol2_snack_type dr1tol2_snack
,output l2todr1_disp_valid
,input l2todr1_disp_retry
,output I_l2todr_disp_type l2todr1_disp
,input dr1tol2_dack_valid
,output dr1tol2_dack_retry
,input I_drtol2_dack_type dr1tol2_dack
,output l2todr1_snoop_ack_valid
,input l2todr1_snoop_ack_retry
,output I_drsnoop_ack_type l2todr1_snoop_ack
,output logic l2todr1_pfreq_valid
,input logic l2todr1_pfreq_retry
,output I_l2todr_pfreq_type l2todr1_pfreq
/* verilator lint_on UNUSED */
/* verilator lint_on UNDRIVEN */
);
// Input reqs to directory
I_l2todr_req_type l2todr0_req_next;
I_l2todr_req_type l2todr1_req_next;
// Give some order to our valid REQ signals (add group by dr# on input, c# on output)
// c0 l2 instruction cache
logic c0_l2itodr0_req_valid;
assign c0_l2itodr0_req_valid = c0_l2itodr_req_valid & ~c0_l2itodr_req.paddr[9];
logic c0_l2itodr1_req_valid;
assign c0_l2itodr1_req_valid = c0_l2itodr_req_valid & c0_l2itodr_req.paddr[9];
// c0 l2 instruction cache tlb
logic c0_l2ittodr0_req_valid;
assign c0_l2ittodr0_req_valid = c0_l2ittodr_req_valid & ~c0_l2ittodr_req.paddr[9];
logic c0_l2ittodr1_req_valid;
assign c0_l2ittodr1_req_valid = c0_l2ittodr_req_valid & c0_l2ittodr_req.paddr[9];
// c0 l2 data cache
logic c0_l2d_0todr0_req_valid;
assign c0_l2d_0todr0_req_valid = c0_l2d_0todr_req_valid & ~c0_l2d_0todr_req.paddr[9];
logic c0_l2d_0todr1_req_valid;
assign c0_l2d_0todr1_req_valid = c0_l2d_0todr_req_valid & c0_l2d_0todr_req.paddr[9];
// c0 l2 data tlb
logic c0_l2dt_0todr0_req_valid;
assign c0_l2dt_0todr0_req_valid = c0_l2dt_0todr_req_valid & ~c0_l2dt_0todr_req.paddr[9];
logic c0_l2dt_0todr1_req_valid;
assign c0_l2dt_0todr1_req_valid = c0_l2dt_0todr_req_valid & c0_l2dt_0todr_req.paddr[9];
// c1 l2 instruction cache
logic c1_l2itodr0_req_valid;
assign c1_l2itodr0_req_valid = c1_l2itodr_req_valid & ~c1_l2itodr_req.paddr[9];
logic c1_l2itodr1_req_valid;
assign c1_l2itodr1_req_valid = c1_l2itodr_req_valid & c1_l2itodr_req.paddr[9];
// c1 l2 instruction cache tlb
logic c1_l2ittodr0_req_valid;
assign c1_l2ittodr0_req_valid = c1_l2ittodr_req_valid & ~c1_l2ittodr_req.paddr[9];
logic c1_l2ittodr1_req_valid;
assign c1_l2ittodr1_req_valid = c1_l2ittodr_req_valid & c1_l2ittodr_req.paddr[9];
// c1 l2 data cache
logic c1_l2d_0todr0_req_valid;
assign c1_l2d_0todr0_req_valid = c1_l2d_0todr_req_valid & ~c1_l2d_0todr_req.paddr[9];
logic c1_l2d_0todr1_req_valid;
assign c1_l2d_0todr1_req_valid = c1_l2d_0todr_req_valid & c1_l2d_0todr_req.paddr[9];
// c1 l2 data tlb
logic c1_l2dt_0todr0_req_valid;
assign c1_l2dt_0todr0_req_valid = c1_l2dt_0todr_req_valid & ~c1_l2dt_0todr_req.paddr[9];
logic c1_l2dt_0todr1_req_valid;
assign c1_l2dt_0todr1_req_valid = c1_l2dt_0todr_req_valid & c1_l2dt_0todr_req.paddr[9];
logic c0_l2todr0_req_valid;
logic c0_l2todr1_req_valid;
logic c1_l2todr0_req_valid;
logic c1_l2todr1_req_valid;
logic l2todr0_req_inp_valid;
logic l2todr1_req_inp_valid;
assign c0_l2todr0_req_valid = c0_l2itodr0_req_valid|c0_l2ittodr0_req_valid|c0_l2d_0todr0_req_valid|c0_l2dt_0todr0_req_valid;
assign c0_l2todr1_req_valid = c0_l2itodr1_req_valid|c0_l2ittodr1_req_valid|c0_l2d_0todr1_req_valid|c0_l2dt_0todr1_req_valid;
assign c1_l2todr0_req_valid = c1_l2itodr0_req_valid|c1_l2ittodr0_req_valid|c1_l2d_0todr0_req_valid|c1_l2dt_0todr0_req_valid;
assign c1_l2todr1_req_valid = c1_l2itodr1_req_valid|c1_l2ittodr1_req_valid|c1_l2d_0todr1_req_valid|c1_l2dt_0todr1_req_valid;
assign l2todr0_req_inp_valid = c0_l2todr0_req_valid | c1_l2todr0_req_valid;
assign l2todr1_req_inp_valid = c0_l2todr1_req_valid | c1_l2todr1_req_valid;
logic c0_l2itodr0_req_retry;
logic c0_l2ittodr0_req_retry;
logic c0_l2d_0todr0_req_retry;
logic c0_l2dt_0todr0_req_retry;
logic c1_l2itodr0_req_retry;
logic c1_l2ittodr0_req_retry;
logic c1_l2d_0todr0_req_retry;
logic c1_l2dt_0todr0_req_retry;
logic c0_l2itodr1_req_retry;
logic c0_l2ittodr1_req_retry;
logic c0_l2d_0todr1_req_retry;
logic c0_l2dt_0todr1_req_retry;
logic c1_l2itodr1_req_retry;
logic c1_l2ittodr1_req_retry;
logic c1_l2d_0todr1_req_retry;
logic c1_l2dt_0todr1_req_retry;
logic l2todr_req_inp0_retry;
logic l2todr_req_inp1_retry;
//***********************REQs**********************
// For every request if the request is valid we
// will pass it through. We also must set retries here.
// Handle DIR 0 reqs
always_comb begin
c0_l2itodr0_req_retry = 1;
c0_l2ittodr0_req_retry = 1;
c0_l2d_0todr0_req_retry = 1;
c0_l2dt_0todr0_req_retry = 1;
c1_l2itodr0_req_retry = 1;
c1_l2ittodr0_req_retry = 1;
c1_l2d_0todr0_req_retry = 1;
c1_l2dt_0todr0_req_retry = 1;
if (c0_l2itodr0_req_valid) begin
l2todr0_req_next = c0_l2itodr_req;
c0_l2itodr0_req_retry = l2todr_req_inp0_retry;
end else if (c0_l2ittodr0_req_valid) begin
c0_l2ittodr0_req_retry = l2todr_req_inp0_retry;
l2todr0_req_next = c0_l2ittodr_req;
end else if (c0_l2d_0todr0_req_valid) begin
c0_l2d_0todr0_req_retry = l2todr_req_inp0_retry;
l2todr0_req_next = c0_l2d_0todr_req;
end else if (c0_l2dt_0todr0_req_valid) begin
c0_l2dt_0todr0_req_retry = l2todr_req_inp0_retry;
l2todr0_req_next = c0_l2dt_0todr_req;
end else if (c1_l2itodr0_req_valid) begin
l2todr0_req_next = c1_l2itodr_req;
c1_l2itodr0_req_retry = l2todr_req_inp0_retry;
end else if (c1_l2ittodr0_req_valid) begin
c1_l2ittodr0_req_retry = l2todr_req_inp0_retry;
l2todr0_req_next = c1_l2ittodr_req;
end else if (c1_l2d_0todr0_req_valid) begin
c1_l2d_0todr0_req_retry = l2todr_req_inp0_retry;
l2todr0_req_next = c1_l2d_0todr_req;
end else if (c1_l2dt_0todr0_req_valid) begin
c1_l2dt_0todr0_req_retry = l2todr_req_inp0_retry;
l2todr0_req_next = c1_l2dt_0todr_req;
end
end
// Handle DIR 1 reqs
always_comb begin
c0_l2itodr1_req_retry = 1;
c0_l2ittodr1_req_retry = 1;
c0_l2d_0todr1_req_retry = 1;
c0_l2dt_0todr1_req_retry = 1;
c1_l2itodr1_req_retry = 1;
c1_l2ittodr1_req_retry = 1;
c1_l2d_0todr1_req_retry = 1;
c1_l2dt_0todr1_req_retry = 1;
if (c0_l2itodr1_req_valid) begin
c0_l2itodr1_req_retry = l2todr_req_inp1_retry;
l2todr1_req_next = c0_l2itodr_req;
end else if (c0_l2ittodr1_req_valid) begin
c0_l2ittodr1_req_retry = l2todr_req_inp1_retry;
l2todr1_req_next = c0_l2ittodr_req;
end else if (c0_l2d_0todr1_req_valid) begin
c0_l2d_0todr1_req_retry = l2todr_req_inp1_retry;
l2todr1_req_next = c0_l2d_0todr_req;
end else if (c0_l2dt_0todr1_req_valid) begin
c0_l2dt_0todr1_req_retry = l2todr_req_inp0_retry;
l2todr0_req_next = c0_l2dt_0todr_req;
end else if (c1_l2itodr1_req_valid) begin
c1_l2itodr1_req_retry = l2todr_req_inp1_retry;
l2todr1_req_next = c1_l2itodr_req;
end else if (c1_l2ittodr1_req_valid) begin
c1_l2ittodr1_req_retry = l2todr_req_inp1_retry;
l2todr1_req_next = c1_l2ittodr_req;
end else if (c1_l2d_0todr1_req_valid) begin
c1_l2d_0todr1_req_retry = l2todr_req_inp1_retry;
l2todr1_req_next = c1_l2d_0todr_req;
end else if (c1_l2d_0todr1_req_valid) begin
c1_l2dt_0todr1_req_retry = l2todr_req_inp0_retry;
l2todr0_req_next = c1_l2dt_0todr_req;
end
end
// set final retry signals for l2 modules
// retry will only be high if dr0_retry and dr1_retry are both set high
// if one is set low that means there is a valid request to that directory
// and other retry can be ignored
always_comb begin
c0_l2itodr_req_retry = c0_l2itodr0_req_retry & c0_l2itodr1_req_retry;
c0_l2ittodr_req_retry = c0_l2ittodr0_req_retry & c0_l2ittodr1_req_retry;
c0_l2d_0todr_req_retry = c0_l2d_0todr0_req_retry & c0_l2d_0todr1_req_retry;
c0_l2dt_0todr_req_retry = c0_l2dt_0todr0_req_retry & c0_l2dt_0todr1_req_retry;
c1_l2itodr_req_retry = c1_l2itodr0_req_retry & c1_l2itodr1_req_retry;
c1_l2ittodr_req_retry = c1_l2ittodr0_req_retry & c1_l2ittodr1_req_retry;
c1_l2d_0todr_req_retry = c1_l2d_0todr0_req_retry & c1_l2d_0todr1_req_retry;
c1_l2dt_0todr_req_retry = c1_l2dt_0todr0_req_retry & c1_l2dt_0todr1_req_retry;
end
fflop #(.Size($bits(I_l2todr_req_type))) req_dir0_ff (
.clk (clk),
.reset (reset),
.din (l2todr0_req_next),
.dinValid (l2todr0_req_inp_valid),
.dinRetry (l2todr_req_inp0_retry),
.q (l2todr0_req),
.qValid (l2todr0_req_valid),
.qRetry (l2todr0_req_retry)
);
fflop #(.Size($bits(I_l2todr_req_type))) req_dir1_ff (
.clk (clk),
.reset (reset),
.din (l2todr1_req_next),
.dinValid (l2todr1_req_inp_valid),
.dinRetry (l2todr_req_inp1_retry),
.q (l2todr1_req),
.qValid (l2todr1_req_valid),
.qRetry (l2todr1_req_retry)
);
// Input disps to directory
I_l2todr_disp_type l2todr0_disp_next;
I_l2todr_disp_type l2todr1_disp_next;
// Give some order to our valid DISP signals (add group by dr# on input, c# on output)
// c0 l2 instruction cache
logic c0_l2itodr0_disp_valid;
assign c0_l2itodr0_disp_valid = c0_l2itodr_disp_valid & ~c0_l2itodr_disp.paddr[9];
logic c0_l2itodr1_disp_valid;
assign c0_l2itodr1_disp_valid = c0_l2itodr_disp_valid & c0_l2itodr_disp.paddr[9];
// c0 l2 instruction cache tlb
logic c0_l2ittodr0_disp_valid;
assign c0_l2ittodr0_disp_valid = c0_l2ittodr_disp_valid & ~c0_l2ittodr_disp.paddr[9];
logic c0_l2ittodr1_disp_valid;
assign c0_l2ittodr1_disp_valid = c0_l2ittodr_disp_valid & c0_l2ittodr_disp.paddr[9];
// c0 l2 data cache
logic c0_l2d_0todr0_disp_valid;
assign c0_l2d_0todr0_disp_valid = c0_l2d_0todr_disp_valid & ~c0_l2d_0todr_disp.paddr[9];
logic c0_l2d_0todr1_disp_valid;
assign c0_l2d_0todr1_disp_valid = c0_l2d_0todr_disp_valid & c0_l2d_0todr_disp.paddr[9];
// c0 l2 data tlb
logic c0_l2dt_0todr0_disp_valid;
assign c0_l2dt_0todr0_disp_valid = c0_l2dt_0todr_disp_valid & ~c0_l2dt_0todr_disp.paddr[9];
logic c0_l2dt_0todr1_disp_valid;
assign c0_l2dt_0todr1_disp_valid = c0_l2dt_0todr_disp_valid & c0_l2dt_0todr_disp.paddr[9];
// c1 l2 instruction cache
logic c1_l2itodr0_disp_valid;
assign c1_l2itodr0_disp_valid = c1_l2itodr_disp_valid & ~c1_l2itodr_disp.paddr[9];
logic c1_l2itodr1_disp_valid;
assign c1_l2itodr1_disp_valid = c1_l2itodr_disp_valid & c1_l2itodr_disp.paddr[9];
// c1 l2 instruction cache tlb
logic c1_l2ittodr0_disp_valid;
assign c1_l2ittodr0_disp_valid = c1_l2ittodr_disp_valid & ~c1_l2ittodr_disp.paddr[9];
logic c1_l2ittodr1_disp_valid;
assign c1_l2ittodr1_disp_valid = c1_l2ittodr_disp_valid & c1_l2ittodr_disp.paddr[9];
// c1 l2 data cache
logic c1_l2d_0todr0_disp_valid;
assign c1_l2d_0todr0_disp_valid = c1_l2d_0todr_disp_valid & ~c1_l2d_0todr_disp.paddr[9];
logic c1_l2d_0todr1_disp_valid;
assign c1_l2d_0todr1_disp_valid = c1_l2d_0todr_disp_valid & c1_l2d_0todr_disp.paddr[9];
// c1 l2 data tlb
logic c1_l2dt_0todr0_disp_valid;
assign c1_l2dt_0todr0_disp_valid = c1_l2dt_0todr_disp_valid & ~c1_l2dt_0todr_disp.paddr[9];
logic c1_l2dt_0todr1_disp_valid;
assign c1_l2dt_0todr1_disp_valid = c1_l2dt_0todr_disp_valid & c1_l2dt_0todr_disp.paddr[9];
logic c0_l2todr0_disp_valid;
logic c0_l2todr1_disp_valid;
logic c1_l2todr0_disp_valid;
logic c1_l2todr1_disp_valid;
logic l2todr0_disp_inp_valid;
logic l2todr1_disp_inp_valid;
assign c0_l2todr0_disp_valid = c0_l2itodr0_disp_valid|c0_l2ittodr0_disp_valid|c0_l2d_0todr0_disp_valid|c0_l2dt_0todr0_disp_valid;
assign c0_l2todr1_disp_valid = c0_l2itodr1_disp_valid|c0_l2ittodr1_disp_valid|c0_l2d_0todr1_disp_valid|c0_l2dt_0todr1_disp_valid;
assign c1_l2todr0_disp_valid = c1_l2itodr0_disp_valid|c1_l2ittodr0_disp_valid|c1_l2d_0todr0_disp_valid|c1_l2dt_0todr0_disp_valid;
assign c1_l2todr1_disp_valid = c1_l2itodr1_disp_valid|c1_l2ittodr1_disp_valid|c1_l2d_0todr1_disp_valid|c1_l2dt_0todr1_disp_valid;
assign l2todr0_disp_inp_valid = c0_l2todr0_disp_valid | c1_l2todr0_disp_valid;
assign l2todr1_disp_inp_valid = c0_l2todr1_disp_valid | c1_l2todr1_disp_valid;
logic c0_l2itodr0_disp_retry;
logic c0_l2ittodr0_disp_retry;
logic c0_l2d_0todr0_disp_retry;
logic c0_l2dt_0todr0_disp_retry;
logic c1_l2itodr0_disp_retry;
logic c1_l2ittodr0_disp_retry;
logic c1_l2d_0todr0_disp_retry;
logic c1_l2dt_0todr0_disp_retry;
logic c0_l2itodr1_disp_retry;
logic c0_l2ittodr1_disp_retry;
logic c0_l2d_0todr1_disp_retry;
logic c0_l2dt_0todr1_disp_retry;
logic c1_l2itodr1_disp_retry;
logic c1_l2ittodr1_disp_retry;
logic c1_l2d_0todr1_disp_retry;
logic c1_l2dt_0todr1_disp_retry;
logic l2todr_disp_inp0_retry;
logic l2todr_disp_inp1_retry;
//***********************disps**********************
// For every disp if the disp is valid we
// will pass it through. We also must set retries here.
// Handle DIR 0 disps
always_comb begin
c0_l2itodr0_disp_retry = 1;
c0_l2ittodr0_disp_retry = 1;
c0_l2d_0todr0_disp_retry = 1;
c0_l2dt_0todr0_disp_retry = 1;
c1_l2itodr0_disp_retry = 1;
c1_l2ittodr0_disp_retry = 1;
c1_l2d_0todr0_disp_retry = 1;
c1_l2dt_0todr0_disp_retry = 1;
if (c0_l2itodr0_disp_valid) begin
l2todr0_disp_next = c0_l2itodr_disp;
c0_l2itodr0_disp_retry = l2todr_disp_inp0_retry;
end else if (c0_l2ittodr0_disp_valid) begin
c0_l2ittodr0_disp_retry = l2todr_disp_inp0_retry;
l2todr0_disp_next = c0_l2ittodr_disp;
end else if (c0_l2d_0todr0_disp_valid) begin
c0_l2d_0todr0_disp_retry = l2todr_disp_inp0_retry;
l2todr0_disp_next = c0_l2d_0todr_disp;
end else if (c0_l2dt_0todr0_disp_valid) begin
c0_l2dt_0todr0_disp_retry = l2todr_disp_inp0_retry;
l2todr0_disp_next = c0_l2dt_0todr_disp;
end else if (c1_l2itodr0_disp_valid) begin
l2todr0_disp_next = c1_l2itodr_disp;
c1_l2itodr0_disp_retry = l2todr_disp_inp0_retry;
end else if (c1_l2ittodr0_disp_valid) begin
c1_l2ittodr0_disp_retry = l2todr_disp_inp0_retry;
l2todr0_disp_next = c1_l2ittodr_disp;
end else if (c1_l2d_0todr0_disp_valid) begin
c1_l2d_0todr0_disp_retry = l2todr_disp_inp0_retry;
l2todr0_disp_next = c1_l2d_0todr_disp;
end else if (c1_l2dt_0todr0_disp_valid) begin
c1_l2dt_0todr0_disp_retry = l2todr_disp_inp0_retry;
l2todr0_disp_next = c1_l2dt_0todr_disp;
end
end
// Handle DIR 1 disps
always_comb begin
c0_l2itodr1_disp_retry = 1;
c0_l2ittodr1_disp_retry = 1;
c0_l2d_0todr1_disp_retry = 1;
c0_l2dt_0todr1_disp_retry = 1;
c1_l2itodr1_disp_retry = 1;
c1_l2ittodr1_disp_retry = 1;
c1_l2d_0todr1_disp_retry = 1;
c1_l2dt_0todr1_disp_retry = 1;
if (c0_l2itodr1_disp_valid) begin
c0_l2itodr1_disp_retry = l2todr_disp_inp1_retry;
l2todr1_disp_next = c0_l2itodr_disp;
end else if (c0_l2ittodr1_disp_valid) begin
c0_l2ittodr1_disp_retry = l2todr_disp_inp1_retry;
l2todr1_disp_next = c0_l2ittodr_disp;
end else if (c0_l2d_0todr1_disp_valid) begin
c0_l2d_0todr1_disp_retry = l2todr_disp_inp1_retry;
l2todr1_disp_next = c0_l2d_0todr_disp;
end else if (c0_l2dt_0todr1_disp_valid) begin
c0_l2dt_0todr1_disp_retry = l2todr_disp_inp0_retry;
l2todr0_disp_next = c0_l2dt_0todr_disp;
end else if (c1_l2itodr1_disp_valid) begin
c1_l2itodr1_disp_retry = l2todr_disp_inp1_retry;
l2todr1_disp_next = c1_l2itodr_disp;
end else if (c1_l2ittodr1_disp_valid) begin
c1_l2ittodr1_disp_retry = l2todr_disp_inp1_retry;
l2todr1_disp_next = c1_l2ittodr_disp;
end else if (c1_l2d_0todr1_disp_valid) begin
c1_l2d_0todr1_disp_retry = l2todr_disp_inp1_retry;
l2todr1_disp_next = c1_l2d_0todr_disp;
end else if (c1_l2d_0todr1_disp_valid) begin
c1_l2dt_0todr1_disp_retry = l2todr_disp_inp0_retry;
l2todr0_disp_next = c1_l2dt_0todr_disp;
end
end
// set final retry signals for l2 modules
// retry will only be high if dr0_retry and dr1_retry are both set high
// if one is set low that means there is a valid dispuest to that directory
// and other retry can be ignored
always_comb begin
c0_l2itodr_disp_retry = c0_l2itodr0_disp_retry & c0_l2itodr1_disp_retry;
c0_l2ittodr_disp_retry = c0_l2ittodr0_disp_retry & c0_l2ittodr1_disp_retry;
c0_l2d_0todr_disp_retry = c0_l2d_0todr0_disp_retry & c0_l2d_0todr1_disp_retry;
c0_l2dt_0todr_disp_retry = c0_l2dt_0todr0_disp_retry & c0_l2dt_0todr1_disp_retry;
c1_l2itodr_disp_retry = c1_l2itodr0_disp_retry & c1_l2itodr1_disp_retry;
c1_l2ittodr_disp_retry = c1_l2ittodr0_disp_retry & c1_l2ittodr1_disp_retry;
c1_l2d_0todr_disp_retry = c1_l2d_0todr0_disp_retry & c1_l2d_0todr1_disp_retry;
c1_l2dt_0todr_disp_retry = c1_l2dt_0todr0_disp_retry & c1_l2dt_0todr1_disp_retry;
end
fflop #(.Size($bits(I_l2todr_disp_type))) disp_dir0_ff (
.clk (clk),
.reset (reset),
.din (l2todr0_disp_next),
.dinValid (l2todr0_disp_inp_valid),
.dinRetry (l2todr_disp_inp0_retry),
.q (l2todr0_disp),
.qValid (l2todr0_disp_valid),
.qRetry (l2todr0_disp_retry)
);
fflop #(.Size($bits(I_l2todr_disp_type))) disp_dir1_ff (
.clk (clk),
.reset (reset),
.din (l2todr1_disp_next),
.dinValid (l2todr1_disp_inp_valid),
.dinRetry (l2todr_disp_inp1_retry),
.q (l2todr1_disp),
.qValid (l2todr1_disp_valid),
.qRetry (l2todr1_disp_retry)
);
// Input pfreqs to directory
I_l2todr_pfreq_type l2todr0_pfreq_next;
I_l2todr_pfreq_type l2todr1_pfreq_next;
// Give some order to our valid pfreq signals (add group by dr# on input, c# on output)
// c0 l2 instruction cache
logic c0_l2itodr0_pfreq_valid;
assign c0_l2itodr0_pfreq_valid = c0_l2itodr_pfreq_valid & ~c0_l2itodr_pfreq.paddr[9];
logic c0_l2itodr1_pfreq_valid;
assign c0_l2itodr1_pfreq_valid = c0_l2itodr_pfreq_valid & c0_l2itodr_pfreq.paddr[9];
// c0 l2 data cache
logic c0_l2d_0todr0_pfreq_valid;
assign c0_l2d_0todr0_pfreq_valid = c0_l2d_0todr_pfreq_valid & ~c0_l2d_0todr_pfreq.paddr[9];
logic c0_l2d_0todr1_pfreq_valid;
assign c0_l2d_0todr1_pfreq_valid = c0_l2d_0todr_pfreq_valid & c0_l2d_0todr_pfreq.paddr[9];
// c1 l2 instruction cache
logic c1_l2itodr0_pfreq_valid;
assign c1_l2itodr0_pfreq_valid = c1_l2itodr_pfreq_valid & ~c1_l2itodr_pfreq.paddr[9];
logic c1_l2itodr1_pfreq_valid;
assign c1_l2itodr1_pfreq_valid = c1_l2itodr_pfreq_valid & c1_l2itodr_pfreq.paddr[9];
// c1 l2 data cache
logic c1_l2d_0todr0_pfreq_valid;
assign c1_l2d_0todr0_pfreq_valid = c1_l2d_0todr_pfreq_valid & ~c1_l2d_0todr_pfreq.paddr[9];
logic c1_l2d_0todr1_pfreq_valid;
assign c1_l2d_0todr1_pfreq_valid = c1_l2d_0todr_pfreq_valid & c1_l2d_0todr_pfreq.paddr[9];
logic c0_l2todr0_pfreq_valid;
logic c0_l2todr1_pfreq_valid;
logic c1_l2todr0_pfreq_valid;
logic c1_l2todr1_pfreq_valid;
logic l2todr0_pfreq_inp_valid;
logic l2todr1_pfreq_inp_valid;
assign c0_l2todr0_pfreq_valid = c0_l2itodr0_pfreq_valid|c0_l2d_0todr0_pfreq_valid;
assign c0_l2todr1_pfreq_valid = c0_l2itodr1_pfreq_valid|c0_l2d_0todr1_pfreq_valid;
assign c1_l2todr0_pfreq_valid = c1_l2itodr0_pfreq_valid|c1_l2d_0todr0_pfreq_valid;
assign c1_l2todr1_pfreq_valid = c1_l2itodr1_pfreq_valid|c1_l2d_0todr1_pfreq_valid;
assign l2todr0_pfreq_inp_valid = c0_l2todr0_pfreq_valid | c1_l2todr0_pfreq_valid;
assign l2todr1_pfreq_inp_valid = c0_l2todr1_pfreq_valid | c1_l2todr1_pfreq_valid;
logic c0_l2itodr0_pfreq_retry;
logic c0_l2d_0todr0_pfreq_retry;
logic c1_l2itodr0_pfreq_retry;
logic c1_l2d_0todr0_pfreq_retry;
logic c0_l2itodr1_pfreq_retry;
logic c0_l2d_0todr1_pfreq_retry;
logic c1_l2itodr1_pfreq_retry;
logic c1_l2d_0todr1_pfreq_retry;
logic l2todr_pfreq_inp0_retry;
logic l2todr_pfreq_inp1_retry;
//***********************pfreqs**********************
// For every pfreq if the pfreq is valid we
// will pass it through. We also must set retries here.
// Handle DIR 0 pfreqs
always_comb begin
c0_l2itodr0_pfreq_retry = 1;
c0_l2d_0todr0_pfreq_retry = 1;
c1_l2itodr0_pfreq_retry = 1;
c1_l2d_0todr0_pfreq_retry = 1;
if (c0_l2itodr0_pfreq_valid) begin
l2todr0_pfreq_next = c0_l2itodr_pfreq;
c0_l2itodr0_pfreq_retry = l2todr_pfreq_inp0_retry;
end else if (c0_l2d_0todr0_pfreq_valid) begin
c0_l2d_0todr0_pfreq_retry = l2todr_pfreq_inp0_retry;
l2todr0_pfreq_next = c0_l2d_0todr_pfreq;
end else if (c1_l2itodr0_pfreq_valid) begin
l2todr0_pfreq_next = c1_l2itodr_pfreq;
c1_l2itodr0_pfreq_retry = l2todr_pfreq_inp0_retry;
end else if (c1_l2d_0todr0_pfreq_valid) begin
c1_l2d_0todr0_pfreq_retry = l2todr_pfreq_inp0_retry;
l2todr0_pfreq_next = c1_l2d_0todr_pfreq;
end
end
// Handle DIR 1 pfreqs
always_comb begin
c0_l2itodr1_pfreq_retry = 1;
c0_l2d_0todr1_pfreq_retry = 1;
c1_l2itodr1_pfreq_retry = 1;
c1_l2d_0todr1_pfreq_retry = 1;
if (c0_l2itodr1_pfreq_valid) begin
c0_l2itodr1_pfreq_retry = l2todr_pfreq_inp1_retry;
l2todr1_pfreq_next = c0_l2itodr_pfreq;
end else if (c0_l2d_0todr1_pfreq_valid) begin
c0_l2d_0todr1_pfreq_retry = l2todr_pfreq_inp1_retry;
l2todr1_pfreq_next = c0_l2d_0todr_pfreq;
end else if (c1_l2itodr1_pfreq_valid) begin
c1_l2itodr1_pfreq_retry = l2todr_pfreq_inp1_retry;
l2todr1_pfreq_next = c1_l2itodr_pfreq;
end else if (c1_l2d_0todr1_pfreq_valid) begin
c1_l2d_0todr1_pfreq_retry = l2todr_pfreq_inp1_retry;
l2todr1_pfreq_next = c1_l2d_0todr_pfreq;
end
end
// set final retry signals for l2 modules
// retry will only be high if dr0_retry and dr1_retry are both set high
// if one is set low that means there is a valid pfrequest to that directory
// and other retry can be ignored
always_comb begin
c0_l2itodr_pfreq_retry = c0_l2itodr0_pfreq_retry & c0_l2itodr1_pfreq_retry;
c0_l2d_0todr_pfreq_retry = c0_l2d_0todr0_pfreq_retry & c0_l2d_0todr1_pfreq_retry;
c1_l2itodr_pfreq_retry = c1_l2itodr0_pfreq_retry & c1_l2itodr1_pfreq_retry;
c1_l2d_0todr_pfreq_retry = c1_l2d_0todr0_pfreq_retry & c1_l2d_0todr1_pfreq_retry;
end
fflop #(.Size($bits(I_l2todr_pfreq_type))) pfreq_dir0_ff (
.clk (clk),
.reset (reset),
.din (l2todr0_pfreq_next),
.dinValid (l2todr0_pfreq_inp_valid),
.dinRetry (l2todr_pfreq_inp0_retry),
.q (l2todr0_pfreq),
.qValid (l2todr0_pfreq_valid),
.qRetry (l2todr0_pfreq_retry)
);
fflop #(.Size($bits(I_l2todr_pfreq_type))) pfreq_dir1_ff (
.clk (clk),
.reset (reset),
.din (l2todr1_pfreq_next),
.dinValid (l2todr1_pfreq_inp_valid),
.dinRetry (l2todr_pfreq_inp1_retry),
.q (l2todr1_pfreq),
.qValid (l2todr1_pfreq_valid),
.qRetry (l2todr1_pfreq_retry)
);
// Input snoop_acks to directory
I_l2snoop_ack_type l2todr0_snoop_ack_next;
I_l2snoop_ack_type l2todr1_snoop_ack_next;
// Give some order to our valid snoop_ack signals (add group by dr# on input, c# on output)
// c0 l2 instruction cache
logic c0_l2itodr0_snoop_ack_valid;
assign c0_l2itodr0_snoop_ack_valid = c0_l2itodr_snoop_ack_valid & ~c0_l2itodr_snoop_ack.directory_id[0];
logic c0_l2itodr1_snoop_ack_valid;
assign c0_l2itodr1_snoop_ack_valid = c0_l2itodr_snoop_ack_valid & c0_l2itodr_snoop_ack.directory_id[0];
// c0 l2 instruction cache tlb
logic c0_l2ittodr0_snoop_ack_valid;
assign c0_l2ittodr0_snoop_ack_valid = c0_l2ittodr_snoop_ack_valid & ~c0_l2ittodr_snoop_ack.directory_id[0];
logic c0_l2ittodr1_snoop_ack_valid;
assign c0_l2ittodr1_snoop_ack_valid = c0_l2ittodr_snoop_ack_valid & c0_l2ittodr_snoop_ack.directory_id[0];
// c0 l2 data cache
logic c0_l2d_0todr0_snoop_ack_valid;
assign c0_l2d_0todr0_snoop_ack_valid = c0_l2d_0todr_snoop_ack_valid & ~c0_l2d_0todr_snoop_ack.directory_id[0];
logic c0_l2d_0todr1_snoop_ack_valid;
assign c0_l2d_0todr1_snoop_ack_valid = c0_l2d_0todr_snoop_ack_valid & c0_l2d_0todr_snoop_ack.directory_id[0];
// c0 l2 data tlb
logic c0_l2dt_0todr0_snoop_ack_valid;
assign c0_l2dt_0todr0_snoop_ack_valid = c0_l2dt_0todr_snoop_ack_valid & ~c0_l2dt_0todr_snoop_ack.directory_id[0];
logic c0_l2dt_0todr1_snoop_ack_valid;
assign c0_l2dt_0todr1_snoop_ack_valid = c0_l2dt_0todr_snoop_ack_valid & c0_l2dt_0todr_snoop_ack.directory_id[0];
// c1 l2 instruction cache
logic c1_l2itodr0_snoop_ack_valid;
assign c1_l2itodr0_snoop_ack_valid = c1_l2itodr_snoop_ack_valid & ~c1_l2itodr_snoop_ack.directory_id[0];
logic c1_l2itodr1_snoop_ack_valid;
assign c1_l2itodr1_snoop_ack_valid = c1_l2itodr_snoop_ack_valid & c1_l2itodr_snoop_ack.directory_id[0];
// c1 l2 instruction cache tlb
logic c1_l2ittodr0_snoop_ack_valid;
assign c1_l2ittodr0_snoop_ack_valid = c1_l2ittodr_snoop_ack_valid & ~c1_l2ittodr_snoop_ack.directory_id[0];
logic c1_l2ittodr1_snoop_ack_valid;
assign c1_l2ittodr1_snoop_ack_valid = c1_l2ittodr_snoop_ack_valid & c1_l2ittodr_snoop_ack.directory_id[0];
// c1 l2 data cache
logic c1_l2d_0todr0_snoop_ack_valid;
assign c1_l2d_0todr0_snoop_ack_valid = c1_l2d_0todr_snoop_ack_valid & ~c1_l2d_0todr_snoop_ack.directory_id[0];
logic c1_l2d_0todr1_snoop_ack_valid;
assign c1_l2d_0todr1_snoop_ack_valid = c1_l2d_0todr_snoop_ack_valid & c1_l2d_0todr_snoop_ack.directory_id[0];
// c1 l2 data tlb
logic c1_l2dt_0todr0_snoop_ack_valid;
assign c1_l2dt_0todr0_snoop_ack_valid = c1_l2dt_0todr_snoop_ack_valid & ~c1_l2dt_0todr_snoop_ack.directory_id[0];
logic c1_l2dt_0todr1_snoop_ack_valid;
assign c1_l2dt_0todr1_snoop_ack_valid = c1_l2dt_0todr_snoop_ack_valid & c1_l2dt_0todr_snoop_ack.directory_id[0];
logic c0_l2todr0_snoop_ack_valid;
logic c0_l2todr1_snoop_ack_valid;
logic c1_l2todr0_snoop_ack_valid;
logic c1_l2todr1_snoop_ack_valid;
logic l2todr0_snoop_ack_inp_valid;
logic l2todr1_snoop_ack_inp_valid;
assign c0_l2todr0_snoop_ack_valid = c0_l2itodr0_snoop_ack_valid|c0_l2ittodr0_snoop_ack_valid|c0_l2d_0todr0_snoop_ack_valid|c0_l2dt_0todr0_snoop_ack_valid;
assign c0_l2todr1_snoop_ack_valid = c0_l2itodr1_snoop_ack_valid|c0_l2ittodr1_snoop_ack_valid|c0_l2d_0todr1_snoop_ack_valid|c0_l2dt_0todr1_snoop_ack_valid;
assign c1_l2todr0_snoop_ack_valid = c1_l2itodr0_snoop_ack_valid|c1_l2ittodr0_snoop_ack_valid|c1_l2d_0todr0_snoop_ack_valid|c1_l2dt_0todr0_snoop_ack_valid;
assign c1_l2todr1_snoop_ack_valid = c1_l2itodr1_snoop_ack_valid|c1_l2ittodr1_snoop_ack_valid|c1_l2d_0todr1_snoop_ack_valid|c1_l2dt_0todr1_snoop_ack_valid;
assign l2todr0_snoop_ack_inp_valid = c0_l2todr0_snoop_ack_valid | c1_l2todr0_snoop_ack_valid;
assign l2todr1_snoop_ack_inp_valid = c0_l2todr1_snoop_ack_valid | c1_l2todr1_snoop_ack_valid;
logic c0_l2itodr0_snoop_ack_retry;
logic c0_l2ittodr0_snoop_ack_retry;
logic c0_l2d_0todr0_snoop_ack_retry;
logic c0_l2dt_0todr0_snoop_ack_retry;
logic c1_l2itodr0_snoop_ack_retry;
logic c1_l2ittodr0_snoop_ack_retry;
logic c1_l2d_0todr0_snoop_ack_retry;
logic c1_l2dt_0todr0_snoop_ack_retry;
logic c0_l2itodr1_snoop_ack_retry;
logic c0_l2ittodr1_snoop_ack_retry;
logic c0_l2d_0todr1_snoop_ack_retry;
logic c0_l2dt_0todr1_snoop_ack_retry;
logic c1_l2itodr1_snoop_ack_retry;
logic c1_l2ittodr1_snoop_ack_retry;
logic c1_l2d_0todr1_snoop_ack_retry;
logic c1_l2dt_0todr1_snoop_ack_retry;
logic l2todr_snoop_ack_inp0_retry;
logic l2todr_snoop_ack_inp1_retry;
//***********************snoop_acks**********************
// For every snoop_ack if the snoop_ack is valid we
// will pass it through. We also must set retries here.
// Handle DIR 0 snoop_acks
always_comb begin
c0_l2itodr0_snoop_ack_retry = 1;
c0_l2ittodr0_snoop_ack_retry = 1;
c0_l2d_0todr0_snoop_ack_retry = 1;
c0_l2dt_0todr0_snoop_ack_retry = 1;
c1_l2itodr0_snoop_ack_retry = 1;
c1_l2ittodr0_snoop_ack_retry = 1;
c1_l2d_0todr0_snoop_ack_retry = 1;
c1_l2dt_0todr0_snoop_ack_retry = 1;
if (c0_l2itodr0_snoop_ack_valid) begin
l2todr0_snoop_ack_next = c0_l2itodr_snoop_ack;
c0_l2itodr0_snoop_ack_retry = l2todr_snoop_ack_inp0_retry;
end else if (c0_l2ittodr0_snoop_ack_valid) begin
c0_l2ittodr0_snoop_ack_retry = l2todr_snoop_ack_inp0_retry;
l2todr0_snoop_ack_next = c0_l2ittodr_snoop_ack;
end else if (c0_l2d_0todr0_snoop_ack_valid) begin
c0_l2d_0todr0_snoop_ack_retry = l2todr_snoop_ack_inp0_retry;
l2todr0_snoop_ack_next = c0_l2d_0todr_snoop_ack;
end else if (c0_l2dt_0todr0_snoop_ack_valid) begin
c0_l2dt_0todr0_snoop_ack_retry = l2todr_snoop_ack_inp0_retry;
l2todr0_snoop_ack_next = c0_l2dt_0todr_snoop_ack;
end else if (c1_l2itodr0_snoop_ack_valid) begin
l2todr0_snoop_ack_next = c1_l2itodr_snoop_ack;
c1_l2itodr0_snoop_ack_retry = l2todr_snoop_ack_inp0_retry;
end else if (c1_l2ittodr0_snoop_ack_valid) begin
c1_l2ittodr0_snoop_ack_retry = l2todr_snoop_ack_inp0_retry;
l2todr0_snoop_ack_next = c1_l2ittodr_snoop_ack;
end else if (c1_l2d_0todr0_snoop_ack_valid) begin
c1_l2d_0todr0_snoop_ack_retry = l2todr_snoop_ack_inp0_retry;
l2todr0_snoop_ack_next = c1_l2d_0todr_snoop_ack;
end else if (c1_l2dt_0todr0_snoop_ack_valid) begin
c1_l2dt_0todr0_snoop_ack_retry = l2todr_snoop_ack_inp0_retry;
l2todr0_snoop_ack_next = c1_l2dt_0todr_snoop_ack;
end
end
// Handle DIR 1 snoop_acks
always_comb begin
c0_l2itodr1_snoop_ack_retry = 1;
c0_l2ittodr1_snoop_ack_retry = 1;
c0_l2d_0todr1_snoop_ack_retry = 1;
c0_l2dt_0todr1_snoop_ack_retry = 1;
c1_l2itodr1_snoop_ack_retry = 1;
c1_l2ittodr1_snoop_ack_retry = 1;
c1_l2d_0todr1_snoop_ack_retry = 1;
c1_l2dt_0todr1_snoop_ack_retry = 1;
if (c0_l2itodr1_snoop_ack_valid) begin
c0_l2itodr1_snoop_ack_retry = l2todr_snoop_ack_inp1_retry;
l2todr1_snoop_ack_next = c0_l2itodr_snoop_ack;
end else if (c0_l2ittodr1_snoop_ack_valid) begin
c0_l2ittodr1_snoop_ack_retry = l2todr_snoop_ack_inp1_retry;
l2todr1_snoop_ack_next = c0_l2ittodr_snoop_ack;
end else if (c0_l2d_0todr1_snoop_ack_valid) begin
c0_l2d_0todr1_snoop_ack_retry = l2todr_snoop_ack_inp1_retry;
l2todr1_snoop_ack_next = c0_l2d_0todr_snoop_ack;
end else if (c0_l2dt_0todr1_snoop_ack_valid) begin
c0_l2dt_0todr1_snoop_ack_retry = l2todr_snoop_ack_inp0_retry;
l2todr0_snoop_ack_next = c0_l2dt_0todr_snoop_ack;
end else if (c1_l2itodr1_snoop_ack_valid) begin
c1_l2itodr1_snoop_ack_retry = l2todr_snoop_ack_inp1_retry;
l2todr1_snoop_ack_next = c1_l2itodr_snoop_ack;
end else if (c1_l2ittodr1_snoop_ack_valid) begin
c1_l2ittodr1_snoop_ack_retry = l2todr_snoop_ack_inp1_retry;
l2todr1_snoop_ack_next = c1_l2ittodr_snoop_ack;
end else if (c1_l2d_0todr1_snoop_ack_valid) begin
c1_l2d_0todr1_snoop_ack_retry = l2todr_snoop_ack_inp1_retry;
l2todr1_snoop_ack_next = c1_l2d_0todr_snoop_ack;
end else if (c1_l2d_0todr1_snoop_ack_valid) begin
c1_l2dt_0todr1_snoop_ack_retry = l2todr_snoop_ack_inp0_retry;
l2todr0_snoop_ack_next = c1_l2dt_0todr_snoop_ack;
end
end
// set final retry signals for l2 modules
// retry will only be high if dr0_retry and dr1_retry are both set high
// if one is set low that means there is a valid snoop_ack to that directory
// and other retry can be ignored
always_comb begin
c0_l2itodr_snoop_ack_retry = c0_l2itodr0_snoop_ack_retry & c0_l2itodr1_snoop_ack_retry;
c0_l2ittodr_snoop_ack_retry = c0_l2ittodr0_snoop_ack_retry & c0_l2ittodr1_snoop_ack_retry;
c0_l2d_0todr_snoop_ack_retry = c0_l2d_0todr0_snoop_ack_retry & c0_l2d_0todr1_snoop_ack_retry;
c0_l2dt_0todr_snoop_ack_retry = c0_l2dt_0todr0_snoop_ack_retry & c0_l2dt_0todr1_snoop_ack_retry;
c1_l2itodr_snoop_ack_retry = c1_l2itodr0_snoop_ack_retry & c1_l2itodr1_snoop_ack_retry;
c1_l2ittodr_snoop_ack_retry = c1_l2ittodr0_snoop_ack_retry & c1_l2ittodr1_snoop_ack_retry;
c1_l2d_0todr_snoop_ack_retry = c1_l2d_0todr0_snoop_ack_retry & c1_l2d_0todr1_snoop_ack_retry;
c1_l2dt_0todr_snoop_ack_retry = c1_l2dt_0todr0_snoop_ack_retry & c1_l2dt_0todr1_snoop_ack_retry;
end
fflop #(.Size($bits(I_drsnoop_ack_type))) snoop_ack_dir0_ff (
.clk (clk),
.reset (reset),
.din (l2todr0_snoop_ack_next),
.dinValid (l2todr0_snoop_ack_inp_valid),
.dinRetry (l2todr_snoop_ack_inp0_retry),
.q (l2todr0_snoop_ack),
.qValid (l2todr0_snoop_ack_valid),
.qRetry (l2todr0_snoop_ack_retry)
);
fflop #(.Size($bits(I_drsnoop_ack_type))) snoop_ack_dir1_ff (
.clk (clk),
.reset (reset),
.din (l2todr1_snoop_ack_next),
.dinValid (l2todr1_snoop_ack_inp_valid),
.dinRetry (l2todr_snoop_ack_inp1_retry),
.q (l2todr1_snoop_ack),
.qValid (l2todr1_snoop_ack_valid),
.qRetry (l2todr1_snoop_ack_retry)
);
I_drtol2_snack_type c0_drtol2i_snack_next;
I_drtol2_snack_type c0_drtol2it_snack_next;
I_drtol2_snack_type c0_drtol2d_0_snack_next;
I_drtol2_snack_type c0_drtol2dt_0_snack_next;
I_drtol2_snack_type c1_drtol2i_snack_next;
I_drtol2_snack_type c1_drtol2it_snack_next;
I_drtol2_snack_type c1_drtol2d_0_snack_next;
I_drtol2_snack_type c1_drtol2dt_0_snack_next;
logic c0_drtol2i_snack_valid_next;
logic c0_drtol2it_snack_valid_next;
logic c0_drtol2d_0_snack_valid_next;
logic c0_drtol2dt_0_snack_valid_next;
logic c1_drtol2i_snack_valid_next;
logic c1_drtol2it_snack_valid_next;
logic c1_drtol2d_0_snack_valid_next;
logic c1_drtol2dt_0_snack_valid_next;
always_comb begin
// start retry signals high so they must be set low to pass through
dr0tol2_snack_retry = 1;
dr1tol2_snack_retry = 1;
// Set all valids low so they have to be set high to pass through
c0_drtol2i_snack_valid_next = 1'b0;
c0_drtol2it_snack_valid_next = 1'b0;
c0_drtol2d_0_snack_valid_next = 1'b0;
c0_drtol2dt_0_snack_valid_next = 1'b0;
c1_drtol2i_snack_valid_next = 1'b0;
c1_drtol2it_snack_valid_next = 1'b0;
c1_drtol2d_0_snack_valid_next = 1'b0;
c1_drtol2dt_0_snack_valid_next = 1'b0;
if (dr0tol2_snack_valid & (dr0tol2_snack.nid[2:0] == 3'b000)) begin
c0_drtol2i_snack_next = dr0tol2_snack;
dr0tol2_snack_retry = c0_drtol2i_snack_retry;
c0_drtol2i_snack_valid_next = 1'b1;
end else if (dr1tol2_snack_valid & (dr1tol2_snack.nid[2:0] == 3'b000)) begin
c0_drtol2i_snack_next = dr1tol2_snack;
dr0tol2_snack_retry = c0_drtol2i_snack_retry;
c0_drtol2i_snack_valid_next = 1'b1;
end
if (dr0tol2_snack_valid & (dr0tol2_snack.nid[2:0] == 3'b001)) begin
c0_drtol2it_snack_valid_next = 1'b1;
c0_drtol2it_snack_next = dr0tol2_snack;
dr0tol2_snack_retry = c0_drtol2it_snack_retry;
end else if (dr1tol2_snack_valid & (dr1tol2_snack.nid[2:0] == 3'b001)) begin
c0_drtol2it_snack_next = dr1tol2_snack;
dr1tol2_snack_retry = c0_drtol2it_snack_retry;
c0_drtol2it_snack_valid_next = 1'b1;
end
if (dr0tol2_snack_valid & (dr0tol2_snack.nid[2:0] == 3'b010)) begin
c0_drtol2d_0_snack_next = dr0tol2_snack;
dr0tol2_snack_retry = c0_drtol2d_0_snack_retry;
c0_drtol2d_0_snack_valid_next = 1'b1;
end else if (dr1tol2_snack_valid & (dr1tol2_snack.nid[2:0] == 3'b010)) begin
c0_drtol2d_0_snack_next = dr1tol2_snack;
dr1tol2_snack_retry = c0_drtol2d_0_snack_retry;
c0_drtol2d_0_snack_valid_next = 1'b1;
end
if (dr0tol2_snack_valid & (dr0tol2_snack.nid[2:0] == 3'b011)) begin
c0_drtol2dt_0_snack_next = dr0tol2_snack;
dr0tol2_snack_retry = c0_drtol2dt_0_snack_retry;
c0_drtol2dt_0_snack_valid_next = 1'b1;
end else if (dr1tol2_snack_valid & (dr1tol2_snack.nid[2:0] == 3'b011)) begin
c0_drtol2dt_0_snack_next = dr1tol2_snack;
dr1tol2_snack_retry = c0_drtol2dt_0_snack_retry;
c0_drtol2dt_0_snack_valid_next = 1'b1;
end
if (dr0tol2_snack_valid & (dr0tol2_snack.nid[2:0] == 3'b100)) begin
c1_drtol2i_snack_next = dr0tol2_snack;
dr0tol2_snack_retry = c1_drtol2i_snack_retry;
c1_drtol2i_snack_valid_next = 1'b1;
end else if (dr1tol2_snack_valid & (dr1tol2_snack.nid[2:0] == 3'b100)) begin
c1_drtol2i_snack_next = dr1tol2_snack;
dr1tol2_snack_retry = c1_drtol2i_snack_retry;
c1_drtol2i_snack_valid_next = 1'b1;
end
if (dr0tol2_snack_valid & (dr0tol2_snack.nid[2:0] == 3'b101)) begin
c1_drtol2it_snack_next = dr0tol2_snack;
dr0tol2_snack_retry = c1_drtol2it_snack_retry;
c1_drtol2it_snack_valid_next = 1'b1;
end else if (dr1tol2_snack_valid & (dr1tol2_snack.nid[2:0] == 3'b101)) begin
c1_drtol2it_snack_next = dr1tol2_snack;
dr1tol2_snack_retry = c1_drtol2it_snack_retry;
c1_drtol2it_snack_valid_next = 1'b1;
end
if (dr0tol2_snack_valid & (dr0tol2_snack.nid[2:0] == 3'b110)) begin
c1_drtol2d_0_snack_next = dr0tol2_snack;
dr0tol2_snack_retry = c1_drtol2d_0_snack_retry;
c1_drtol2d_0_snack_valid_next = 1'b1;
end else if (dr1tol2_snack_valid & (dr1tol2_snack.nid[2:0] == 3'b110)) begin
c1_drtol2d_0_snack_next = dr1tol2_snack;
dr1tol2_snack_retry = c1_drtol2d_0_snack_retry;
c1_drtol2d_0_snack_valid_next = 1'b1;
end
if (dr0tol2_snack_valid & (dr0tol2_snack.nid[2:0] == 3'b111)) begin
c1_drtol2dt_0_snack_next = dr0tol2_snack;
dr0tol2_snack_retry = c1_drtol2dt_0_snack_retry;
c1_drtol2dt_0_snack_valid_next = 1'b1;
end else if (dr1tol2_snack_valid & (dr1tol2_snack.nid[2:0] == 3'b111)) begin
c1_drtol2dt_0_snack_next = dr1tol2_snack;
dr1tol2_snack_retry = c1_drtol2dt_0_snack_retry;
c1_drtol2dt_0_snack_valid_next = 1'b1;
end
end
fflop #(.Size($bits(I_drtol2_snack_type))) c0_drtol2i_snack_ff (
.clk (clk),
.reset (reset),
.din (c0_drtol2i_snack_next),
.dinValid (c0_drtol2i_snack_valid_next),
.dinRetry (dr0tol2_snack_retry),
.q (c0_drtol2i_snack),
.qValid (c0_drtol2i_snack_valid),
.qRetry (c0_drtol2i_snack_retry)
);
fflop #(.Size($bits(I_drtol2_snack_type))) c0_drtol2it_snack_ff (
.clk (clk),
.reset (reset),
.din (c0_drtol2it_snack_next),
.dinValid (c0_drtol2it_snack_valid_next),
.dinRetry (dr0tol2_snack_retry),
.q (c0_drtol2it_snack),
.qValid (c0_drtol2it_snack_valid),
.qRetry (c0_drtol2it_snack_retry)
);
fflop #(.Size($bits(I_drtol2_snack_type))) c0_drtol2d_0_snack_ff (
.clk (clk),
.reset (reset),
.din (c0_drtol2d_0_snack_next),
.dinValid (c0_drtol2d_0_snack_valid_next),
.dinRetry (dr0tol2_snack_retry),
.q (c0_drtol2d_0_snack),
.qValid (c0_drtol2d_0_snack_valid),
.qRetry (c0_drtol2d_0_snack_retry)
);
fflop #(.Size($bits(I_drtol2_snack_type))) c0_drtol2dt_0_snack_ff (
.clk (clk),
.reset (reset),
.din (c0_drtol2dt_0_snack_next),
.dinValid (c0_drtol2dt_0_snack_valid_next),
.dinRetry (dr0tol2_snack_retry),
.q (c0_drtol2dt_0_snack),
.qValid (c0_drtol2dt_0_snack_valid),
.qRetry (c0_drtol2dt_0_snack_retry)
);
fflop #(.Size($bits(I_drtol2_snack_type))) c1_drtol2i_snack_ff (
.clk (clk),
.reset (reset),
.din (c1_drtol2i_snack_next),
.dinValid (c1_drtol2i_snack_valid_next),
.dinRetry (dr0tol2_snack_retry),
.q (c1_drtol2i_snack),
.qValid (c1_drtol2i_snack_valid),
.qRetry (c1_drtol2i_snack_retry)
);
fflop #(.Size($bits(I_drtol2_snack_type))) c1_drtol2it_snack_ff (
.clk (clk),
.reset (reset),
.din (c1_drtol2it_snack_next),
.dinValid (c1_drtol2it_snack_valid_next),
.dinRetry (dr0tol2_snack_retry),
.q (c1_drtol2it_snack),
.qValid (c1_drtol2it_snack_valid),
.qRetry (c1_drtol2it_snack_retry)
);
fflop #(.Size($bits(I_drtol2_snack_type))) c1_drtol2d_0_snack_ff (
.clk (clk),
.reset (reset),
.din (c1_drtol2d_0_snack_next),
.dinValid (c1_drtol2d_0_snack_valid_next),
.dinRetry (dr0tol2_snack_retry),
.q (c1_drtol2d_0_snack),
.qValid (c1_drtol2d_0_snack_valid),
.qRetry (c1_drtol2d_0_snack_retry)
);
fflop #(.Size($bits(I_drtol2_snack_type))) c1_drtol2dt_0_snack_ff (
.clk (clk),
.reset (reset),
.din (c1_drtol2dt_0_snack_next),
.dinValid (c1_drtol2dt_0_snack_valid_next),
.dinRetry (dr0tol2_snack_retry),
.q (c1_drtol2dt_0_snack),
.qValid (c1_drtol2dt_0_snack_valid),
.qRetry (c1_drtol2dt_0_snack_retry)
);
I_drtol2_dack_type c0_drtol2i_dack_next;
I_drtol2_dack_type c0_drtol2it_dack_next;
I_drtol2_dack_type c0_drtol2d_0_dack_next;
I_drtol2_dack_type c0_drtol2dt_0_dack_next;
I_drtol2_dack_type c1_drtol2i_dack_next;
I_drtol2_dack_type c1_drtol2it_dack_next;
I_drtol2_dack_type c1_drtol2d_0_dack_next;
I_drtol2_dack_type c1_drtol2dt_0_dack_next;
logic c0_drtol2i_dack_valid_next;
logic c0_drtol2it_dack_valid_next;
logic c0_drtol2d_0_dack_valid_next;
logic c0_drtol2dt_0_dack_valid_next;
logic c1_drtol2i_dack_valid_next;
logic c1_drtol2it_dack_valid_next;
logic c1_drtol2d_0_dack_valid_next;
logic c1_drtol2dt_0_dack_valid_next;
always_comb begin
// start retry signals high so they must be set low to pass through
dr0tol2_dack_retry = 1;
dr1tol2_dack_retry = 1;
// stary valid signals low so they must be set high to pass through
c0_drtol2i_dack_valid_next = 1'b0;
c0_drtol2it_dack_valid_next = 1'b0;
c0_drtol2d_0_dack_valid_next = 1'b0;
c0_drtol2dt_0_dack_valid_next = 1'b0;
c1_drtol2i_dack_valid_next = 1'b0;
c1_drtol2it_dack_valid_next = 1'b0;
c1_drtol2d_0_dack_valid_next = 1'b0;
c1_drtol2dt_0_dack_valid_next = 1'b0;
if (dr0tol2_dack_valid & (dr0tol2_dack.nid[2:0] == 3'b000)) begin
c0_drtol2i_dack_next = dr0tol2_dack;
dr0tol2_dack_retry = c0_drtol2i_dack_retry;
c0_drtol2i_dack_valid_next = 1'b1;
end else if (dr1tol2_dack_valid & (dr1tol2_dack.nid[2:0] == 3'b000)) begin
c0_drtol2i_dack_next = dr1tol2_dack;
dr0tol2_dack_retry = c0_drtol2i_dack_retry;
c0_drtol2i_dack_valid_next = 1'b1;
end
if (dr0tol2_dack_valid & (dr0tol2_dack.nid[2:0] == 3'b001)) begin
c0_drtol2it_dack_next = dr0tol2_dack;
dr0tol2_dack_retry = c0_drtol2it_dack_retry;
c0_drtol2it_dack_valid_next = 1'b1;
end else if (dr1tol2_dack_valid & (dr1tol2_dack.nid[2:0] == 3'b001)) begin
c0_drtol2it_dack_next = dr1tol2_dack;
dr1tol2_dack_retry = c0_drtol2it_dack_retry;
c0_drtol2it_dack_valid_next = 1'b1;
end
if (dr0tol2_dack_valid & (dr0tol2_dack.nid[2:0] == 3'b010)) begin
c0_drtol2d_0_dack_next = dr0tol2_dack;
dr0tol2_dack_retry = c0_drtol2d_0_dack_retry;
c0_drtol2d_0_dack_valid_next = 1'b1;
end else if (dr1tol2_dack_valid & (dr1tol2_dack.nid[2:0] == 3'b010)) begin
c0_drtol2d_0_dack_next = dr1tol2_dack;
dr1tol2_dack_retry = c0_drtol2d_0_dack_retry;
c0_drtol2d_0_dack_valid_next = 1'b1;
end
if (dr0tol2_dack_valid & (dr0tol2_dack.nid[2:0] == 3'b011)) begin
c0_drtol2dt_0_dack_next = dr0tol2_dack;
dr0tol2_dack_retry = c0_drtol2dt_0_dack_retry;
c0_drtol2dt_0_dack_valid_next = 1'b1;
end else if (dr1tol2_dack_valid & (dr1tol2_dack.nid[2:0] == 3'b011)) begin
c0_drtol2dt_0_dack_next = dr1tol2_dack;
dr1tol2_dack_retry = c0_drtol2dt_0_dack_retry;
c0_drtol2dt_0_dack_valid_next = 1'b1;
end
if (dr0tol2_dack_valid & (dr0tol2_dack.nid[2:0] == 3'b100)) begin
c1_drtol2i_dack_next = dr0tol2_dack;
dr0tol2_dack_retry = c1_drtol2i_dack_retry;
c1_drtol2i_dack_valid_next = 1'b1;
end else if (dr1tol2_dack_valid & (dr1tol2_dack.nid[2:0] == 3'b100)) begin
c1_drtol2i_dack_next = dr1tol2_dack;
dr1tol2_dack_retry = c1_drtol2i_dack_retry;
c1_drtol2i_dack_valid_next = 1'b1;
end
if (dr0tol2_dack_valid & (dr0tol2_dack.nid[2:0] == 3'b101)) begin
c1_drtol2it_dack_next = dr0tol2_dack;
dr0tol2_dack_retry = c1_drtol2it_dack_retry;
c1_drtol2it_dack_valid_next = 1'b1;
end else if (dr1tol2_dack_valid & (dr1tol2_dack.nid[2:0] == 3'b101)) begin
c1_drtol2it_dack_next = dr1tol2_dack;
dr1tol2_dack_retry = c1_drtol2it_dack_retry;
c1_drtol2it_dack_valid_next = 1'b1;
end
if (dr0tol2_dack_valid & (dr0tol2_dack.nid[2:0] == 3'b110)) begin
c1_drtol2d_0_dack_next = dr0tol2_dack;
dr0tol2_dack_retry = c1_drtol2d_0_dack_retry;
c1_drtol2d_0_dack_valid_next = 1'b1;
end else if (dr1tol2_dack_valid & (dr1tol2_dack.nid[2:0] == 3'b110)) begin
c1_drtol2d_0_dack_next = dr1tol2_dack;
dr1tol2_dack_retry = c1_drtol2d_0_dack_retry;
c1_drtol2d_0_dack_valid_next = 1'b1;
end
if (dr0tol2_dack_valid & (dr0tol2_dack.nid[2:0] == 3'b111)) begin
c1_drtol2dt_0_dack_next = dr0tol2_dack;
dr0tol2_dack_retry = c1_drtol2dt_0_dack_retry;
c1_drtol2dt_0_dack_valid_next = 1'b1;
end else if (dr1tol2_dack_valid & (dr1tol2_dack.nid[2:0] == 3'b111)) begin
c1_drtol2dt_0_dack_next = dr1tol2_dack;
dr1tol2_dack_retry = c1_drtol2dt_0_dack_retry;
c1_drtol2dt_0_dack_valid_next = 1'b1;
end
end
fflop #(.Size($bits(I_drtol2_dack_type))) c0_drtol2i_dack_ff (
.clk (clk),
.reset (reset),
.din (c0_drtol2i_dack_next),
.dinValid (c0_drtol2i_dack_valid_next),
.dinRetry (dr0tol2_dack_retry),
.q (c0_drtol2i_dack),
.qValid (c0_drtol2i_dack_valid),
.qRetry (c0_drtol2i_dack_retry)
);
fflop #(.Size($bits(I_drtol2_dack_type))) c0_drtol2it_dack_ff (
.clk (clk),
.reset (reset),
.din (c0_drtol2it_dack_next),
.dinValid (c0_drtol2it_dack_valid_next),
.dinRetry (dr0tol2_dack_retry),
.q (c0_drtol2it_dack),
.qValid (c0_drtol2it_dack_valid),
.qRetry (c0_drtol2it_dack_retry)
);
fflop #(.Size($bits(I_drtol2_dack_type))) c0_drtol2d_0_dack_ff (
.clk (clk),
.reset (reset),
.din (c0_drtol2d_0_dack_next),
.dinValid (c0_drtol2d_0_dack_valid_next),
.dinRetry (dr0tol2_dack_retry),
.q (c0_drtol2d_0_dack),
.qValid (c0_drtol2d_0_dack_valid),
.qRetry (c0_drtol2d_0_dack_retry)
);
fflop #(.Size($bits(I_drtol2_dack_type))) c0_drtol2dt_0_dack_ff (
.clk (clk),
.reset (reset),
.din (c0_drtol2dt_0_dack_next),
.dinValid (c0_drtol2dt_0_dack_valid_next),
.dinRetry (dr0tol2_dack_retry),
.q (c0_drtol2dt_0_dack),
.qValid (c0_drtol2dt_0_dack_valid),
.qRetry (c0_drtol2dt_0_dack_retry)
);
fflop #(.Size($bits(I_drtol2_dack_type))) c1_drtol2i_dack_ff (
.clk (clk),
.reset (reset),
.din (c1_drtol2i_dack_next),
.dinValid (c1_drtol2i_dack_valid_next),
.dinRetry (dr0tol2_dack_retry),
.q (c1_drtol2i_dack),
.qValid (c1_drtol2i_dack_valid),
.qRetry (c1_drtol2i_dack_retry)
);
fflop #(.Size($bits(I_drtol2_dack_type))) c1_drtol2it_dack_ff (
.clk (clk),
.reset (reset),
.din (c1_drtol2it_dack_next),
.dinValid (c1_drtol2it_dack_valid_next),
.dinRetry (dr0tol2_dack_retry),
.q (c1_drtol2it_dack),
.qValid (c1_drtol2it_dack_valid),
.qRetry (c1_drtol2it_dack_retry)
);
fflop #(.Size($bits(I_drtol2_dack_type))) c1_drtol2d_0_dack_ff (
.clk (clk),
.reset (reset),
.din (c1_drtol2d_0_dack_next),
.dinValid (c1_drtol2d_0_dack_valid_next),
.dinRetry (dr0tol2_dack_retry),
.q (c1_drtol2d_0_dack),
.qValid (c1_drtol2d_0_dack_valid),
.qRetry (c1_drtol2d_0_dack_retry)
);
fflop #(.Size($bits(I_drtol2_dack_type))) c1_drtol2dt_0_dack_ff (
.clk (clk),
.reset (reset),
.din (c1_drtol2dt_0_dack_next),
.dinValid (c1_drtol2dt_0_dack_valid_next),
.dinRetry (dr0tol2_dack_retry),
.q (c1_drtol2dt_0_dack),
.qValid (c1_drtol2dt_0_dack_valid),
.qRetry (c1_drtol2dt_0_dack_retry)
);
endmodule |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_rst (
// clock reset
preset,
clk,
rst);
// clock reset
input preset;
input clk;
output rst;
// internal registers
reg rst_p = 'd0;
reg rst = 'd0;
// simple reset gen
always @(posedge clk or posedge preset) begin
if (preset == 1'b1) begin
rst_p <= 1'd1;
rst <= 1'd1;
end else begin
rst_p <= 1'b0;
rst <= rst_p;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/************************
* Willard Wider
* 6-5-17
* ELEC3725
* alu32.v
* building a 32 bit ALU
************************/
`timescale 1ns / 1ps//Unit time
//The top module of the entire project. The declaration of the entire ALU itself.
module alu32 (d, Cout, V, a, b, Cin, S);
output[31:0] d;//the output bus
output Cout, V;//Cout is the bit for it it needs to carry over to the next circuit/ V is the overflow bit.
input [31:0] a, b;//the two input buses
input Cin;//the bit for marking if it is carrying over from a previous circuit
input [2:0] S;//The select bus. It defines the operation to do with input busses a and b
wire [31:0] c, g, p;
wire gout, pout;
//The core ALU bus
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
//the top Look-Ahead-Carry module.
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
//the overflow module
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule
//The module to handle a single bit operation for the top ALU module
module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;//acts as an inversion for the xnor so it can be processed as xor
g = a & bint;//used for overflow, uses xor and a value from a. covers case of last bit being high
p = a ^ bint;//xor, for xor and xnor
cint = S[1] & c;//for add or sub, already processed by the lacs
//if it's supposed to be a 1, it will be a 1 if the command is add or subtract
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;//or
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);//nor
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;//and
end
else
d = 1;
end
end
endmodule
//The module to handle the overflow bit
module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule
//Look-Ahead Carry unit level 1. Used for the root (level 1) and first child leafs (level 2)
module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule
//Look-Ahead Carry unit level 2. Contains LACs for the root and level 1. Used in level 3
module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 3. Contains LACs for the root and level 2. Used in level 4
module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 4. Contains LACs for the root and level 3. Used in level 5
module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 1. Caontains LACs for the root and level 4. Used in the core alu32 module
module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Async clears must not race with clocks if we want repeatable results
reg set_l = in[20];
reg clr_l = in[21];
always @ (negedge clk) begin
set_l <= in[20];
clr_l <= in[21];
end
//====== Mux
wire [1:0] qm;
// delay z a b sel
udp_mux2 #(0.1) m0 (qm[0], in[0], in[2], in[4]);
udp_mux2 #0.1 m1 (qm[1], in[1], in[3], in[4]);
`define verilatorxx
`ifdef verilatorxx
reg [1:0] ql;
reg [1:0] qd;
// No sequential tables, yet
// always @* begin
// if (!clk) ql = in[13:12];
// end
always @(posedge clk or negedge set_l or negedge clr_l) begin
if (!set_l) qd <= ~2'b0;
else if (!clr_l) qd <= 2'b0;
else qd <= in[17:16];
end
`else
//====== Latch
// wire [1:0] ql;
// // q clk d
// udp_latch l0 (ql[0], !in[8], in[12]);
// udp_latch l1 (ql[1], !in[8], in[13]);
//====== DFF
wire [1:0] qd;
//always @* $display("UL q=%b c=%b d=%b", ql[1:0], in[8], in[13:12]);
// q clk d set_l clr_l
udp_dff d0 (qd[0], in[8], in[16], set_l, clr_l);
udp_dff d2 (qd[1], in[8], in[17], set_l, clr_l);
`endif
// Aggregate outputs into a single result vector
wire [63:0] result = {52'h0, 2'b0,qd, 4'b0, 2'b0,qm};
// wire [63:0] result = {52'h0, 2'b0,qd, 2'b0,ql, 2'b0,qm};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
// Note not all simulators agree about the latch result. Maybe have a race?
`define EXPECTED_SUM 64'hb73acf228acaeaa3
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
primitive udp_mux2 (z, a, b, sel);
output z;
input a, b, sel;
table
//a b s o
? 1 1 : 1 ;
? 0 1 : 0 ;
1 ? 0 : 1 ;
0 ? 0 : 0 ;
1 1 x : 1 ;
0 0 x : 0 ;
endtable
endprimitive
primitive udp_latch (q, clk, d);
output q; reg q;
input clk, d;
table
//clk d q q'
0 1 : ? : 1;
0 0 : ? : 0;
1 ? : ? : -;
endtable
endprimitive
primitive udp_dff (q, clk, d, set_l, clr_l);
output q;
input clk, d, set_l, clr_l;
reg q;
table
//ck d s c : q : q'
r 0 1 ? : ? : 0 ;
r 1 ? 1 : ? : 1 ;
* 1 ? 1 : 1 : 1 ;
* 0 1 ? : 0 : 0 ;
f ? ? ? : ? : - ;
b * ? ? : ? : - ;
? ? 0 ? : ? : 1 ;
b ? * 1 : 1 : 1 ;
x 1 * 1 : 1 : 1 ;
? ? 1 0 : ? : 0 ;
b ? 1 * : 0 : 0 ;
x 0 1 * : 0 : 0 ;
endtable
endprimitive
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:09:46 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_0_stub.v
// Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_bram_ctrl,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awid,
s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache,
s_axi_awprot, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast,
s_axi_rvalid, s_axi_rready, bram_rst_a, bram_clk_a, bram_en_a, bram_we_a, bram_addr_a,
bram_wrdata_a, bram_rddata_a, bram_rst_b, bram_clk_b, bram_en_b, bram_we_b, bram_addr_b,
bram_wrdata_b, bram_rddata_b)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awid[11:0],s_axi_awaddr[15:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock,s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[15:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock,s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[15:0],bram_wrdata_a[31:0],bram_rddata_a[31:0],bram_rst_b,bram_clk_b,bram_en_b,bram_we_b[3:0],bram_addr_b[15:0],bram_wrdata_b[31:0],bram_rddata_b[31:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [11:0]s_axi_awid;
input [15:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [15:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output bram_rst_a;
output bram_clk_a;
output bram_en_a;
output [3:0]bram_we_a;
output [15:0]bram_addr_a;
output [31:0]bram_wrdata_a;
input [31:0]bram_rddata_a;
output bram_rst_b;
output bram_clk_b;
output bram_en_b;
output [3:0]bram_we_b;
output [15:0]bram_addr_b;
output [31:0]bram_wrdata_b;
input [31:0]bram_rddata_b;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// XESS SRAM interface ////
//// ////
//// This file is part of the OR1K test application ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Connects the SoC to SRAM. It does RMW for byte accesses ////
//// because XSV board has WEs on a 16-bit basis. ////
//// ////
//// To Do: ////
//// - nothing really ////
//// ////
//// Author(s): ////
//// - Simon Srot, [email protected] ////
//// - Igor Mohor, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: sram_top.v,v $
// Revision 1.2 2006-12-22 08:34:00 vak
// The design is successfully compiled using on-chip RAM.
//
// Revision 1.1 2006/12/21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.7 2004/04/05 08:44:55 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.5 2002/09/16 02:51:23 lampret
// Delayed wb_err_o. Disabled wb_ack_o when wb_err_o is asserted.
//
// Revision 1.4 2002/08/18 19:55:30 lampret
// Added variable delay for SRAM.
//
// Revision 1.3 2002/08/14 06:24:43 lampret
// Fixed size of generic flash/sram to exactly 2MB
//
// Revision 1.2 2002/08/12 05:34:06 lampret
// Added SRAM_GENERIC
//
// Revision 1.1.1.1 2002/03/21 16:55:44 lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.3 2002/01/23 07:50:44 lampret
// Added wb_err_o to flash and sram i/f for testing the buserr exception.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1.1.1 2001/11/04 19:00:09 lampret
// First import.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`define SRAM_GENERIC
`ifdef SRAM_GENERIC
module sram_top (
wb_clk_i, wb_rst_i,
wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o,
r_cen, r0_wen, r1_wen, r_oen, r_a, r_d_i, r_d_o, d_oe,
l_cen, l0_wen, l1_wen, l_oen, l_a, l_d_i, l_d_o
);
//
// Paraneters
//
parameter aw = 19;
//
// I/O Ports
//
input wb_clk_i;
input wb_rst_i;
//
// WB slave i/f
//
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
//
// Right SRAM bank
//
output r_oen;
output r0_wen;
output r1_wen;
output r_cen;
input [15:0] r_d_i;
output [15:0] r_d_o;
output [aw-1:0] r_a;
//
// Left SRAM bank
//
output l_oen;
output l0_wen;
output l1_wen;
output l_cen;
input [15:0] l_d_i;
output [15:0] l_d_o;
output [aw-1:0] l_a;
//
// Common SRAM signals
//
output d_oe;
//
// Internal wires and regs
//
reg [7:0] mem [2097151:0];
integer i;
wire [31:0] adr;
`ifdef SRAM_GENERIC_REGISTERED
reg wb_err_o;
reg [31:0] prev_adr;
reg [1:0] delay;
`else
wire [1:0] delay;
`endif
wire wb_err;
//
// Aliases and simple assignments
//
assign wb_err = wb_cyc_i & wb_stb_i & (delay == 2'd0) & (|wb_adr_i[23:21]); // If Access to > 2MB (8-bit leading prefix ignored)
assign adr = {8'h00, wb_adr_i[23:2], 2'b00};
//
// Reading from SRAM model
//
assign wb_dat_o[7:0] = mem[adr+3];
assign wb_dat_o[15:8] = mem[adr+2];
assign wb_dat_o[23:16] = mem[adr+1];
assign wb_dat_o[31:24] = mem[adr+0];
//
// Writing to SRAM model
//
always @(posedge wb_rst_i or posedge wb_clk_i)
if (wb_cyc_i & wb_stb_i & wb_we_i) begin
if (wb_sel_i[0])
mem[adr+3] <= #1 wb_dat_i[7:0];
if (wb_sel_i[1])
mem[adr+2] <= #1 wb_dat_i[15:8];
if (wb_sel_i[2])
mem[adr+1] <= #1 wb_dat_i[23:16];
if (wb_sel_i[3])
mem[adr+0] <= #1 wb_dat_i[31:24];
end
`ifdef SRAM_GENERIC_REGISTERED
//
// WB Acknowledge
//
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i) begin
delay <= #1 2'd3;
prev_adr <= #1 32'h0000_0000;
end
else if (delay && (wb_adr_i == prev_adr) && wb_cyc_i && wb_stb_i)
delay <= #1 delay - 2'd1;
else if (wb_ack_o || wb_err_o || (wb_adr_i != prev_adr) || ~wb_stb_i) begin
delay <= #1 2'd2; // delay ... can range from 3 to 0
prev_adr <= #1 wb_adr_i;
end
`else
assign delay = 2'd0;
`endif
assign wb_ack_o = wb_cyc_i & wb_stb_i & ~wb_err & (delay == 2'd0)
`ifdef SRAM_GENERIC_REGISTERED
& (wb_adr_i == prev_adr)
`endif
;
`ifdef SRAM_GENERIC_REGISTERED
//
// WB Error
//
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_err_o <= #1 1'b0;
else
wb_err_o <= #1 wb_err & !wb_err_o;
`else
assign wb_err_o = wb_err;
`endif
//
// SRAM i/f monitor
//
// synopsys translate_off
integer fsram;
initial begin
fsram = $fopen("sram.log");
for (i = 0; i < 2097152; i = i + 1)
mem[i] = 0;
end
always @(posedge wb_clk_i)
if (wb_cyc_i)
if (wb_stb_i & wb_we_i) begin
if (wb_sel_i[3])
mem[{wb_adr_i[23:2], 2'b00}+0] = wb_dat_i[31:24];
if (wb_sel_i[2])
mem[{wb_adr_i[23:2], 2'b00}+1] = wb_dat_i[23:16];
if (wb_sel_i[1])
mem[{wb_adr_i[23:2], 2'b00}+2] = wb_dat_i[15:8];
if (wb_sel_i[0])
mem[{wb_adr_i[23:2], 2'b00}+3] = wb_dat_i[7:0];
$fdisplay(fsram, "%t [%h] <- write %h, byte sel %b", $time, wb_adr_i, wb_dat_i, wb_sel_i);
end else if (wb_ack_o)
$fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o);
// synopsys translate_on
endmodule
`else
module sram_top (
wb_clk_i, wb_rst_i,
wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o,
r_cen, r0_wen, r1_wen, r_oen, r_a, r_d_i, r_d_o, d_oe,
l_cen, l0_wen, l1_wen, l_oen, l_a, l_d_i, l_d_o
);
//
// Paraneters
//
parameter aw = 19;
//
// I/O Ports
//
input wb_clk_i;
input wb_rst_i;
//
// WB slave i/f
//
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
//
// Right SRAM bank
//
output r_oen;
output r0_wen;
output r1_wen;
output r_cen;
input [15:0] r_d_i;
output [15:0] r_d_o;
output [aw-1:0] r_a;
//
// Left SRAM bank
//
output l_oen;
output l0_wen;
output l1_wen;
output l_cen;
input [15:0] l_d_i;
output [15:0] l_d_o;
output [aw-1:0] l_a;
//
// Common SRAM signals
//
output d_oe;
//
// Internal regs and wires
//
reg [15:0] r_data;
reg [15:0] l_data;
reg l0_wen;
wire l1_wen = l0_wen;
reg r0_wen;
wire r1_wen = r0_wen;
reg [31:0] latch_data;
reg ack_we;
wire l_oe;
wire r_oe;
wire r_ack;
reg Mux;
reg [aw-1:0] LatchedAddr;
reg [15:0] l_read;
reg [15:0] r_read;
reg d_oe;
reg [15:0] l_mux;
reg [15:0] r_mux;
//
// Aliases and simple assignments
//
assign wb_dat_o = {r_d_i, l_d_i};
assign l_oen = ~l_oe;
assign r_oen = ~r_oe;
assign l_a = Mux ? LatchedAddr : wb_adr_i[aw+1:2];
assign r_a = l_a;
assign l_d_o = l_mux;
assign r_d_o = r_mux;
assign l_oe = wb_cyc_i & wb_stb_i & l0_wen;
assign r_oe = wb_cyc_i & wb_stb_i & r0_wen;
assign l_cen = ~(wb_cyc_i & wb_stb_i);
assign r_cen = l_cen;
assign wb_ack_o = (wb_cyc_i & wb_stb_i & ~wb_err & ~wb_we_i) | ack_we;
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[27:21]); // If Access to > 2MB (4-bit leading prefix ignored)
//
// RMW mux control
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
Mux <= 1'b0;
else
if (ack_we)
Mux <= #1 1'b1;
else
Mux <= #1 1'b0;
end
//
// Latch address
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
LatchedAddr <= 'h0;
else
if (wb_cyc_i & wb_stb_i)
LatchedAddr <= #1 wb_adr_i[aw+1:2];
end
//
// Latch data from RAM (read data)
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
l_read <= 16'h0;
r_read <= 16'h0;
end
else
if (wb_cyc_i & wb_stb_i)
begin
l_read <= #1 l_d_i[15:0];
r_read <= #1 r_d_i[15:0];
end
end
//
// Mux and latch data for writing left SRAM bank (bytes 0 and 1)
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
l_mux <= 16'h0;
else
if (~l0_wen)
begin
if (wb_sel_i[0])
l_mux[7:0] <= #1 wb_dat_i[7:0];
else
l_mux[7:0] <= #1 l_read[7:0];
if (wb_sel_i[1])
l_mux[15:8] <= #1 wb_dat_i[15:8];
else
l_mux[15:8] <= #1 l_read[15:8];
end
else
l_mux[15:0] <= #1 16'hz;
end
//
// Mux and latch data for writing right SRAM bank (bytes 2 and 3)
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
r_mux <= 16'h0;
else
if (~r0_wen)
begin
if (wb_sel_i[2])
r_mux[7:0] <= #1 wb_dat_i[23:16];
else
r_mux[7:0] <= #1 r_read[7:0];
if (wb_sel_i[3])
r_mux[15:8] <= #1 wb_dat_i[31:24];
else
r_mux[15:8] <= #1 r_read[15:8];
end
else
r_mux <= #1 16'hz;
end
//
// Left WE
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
l0_wen <= 1'b1;
else
if (wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[1:0]) & ~wb_ack_o)
l0_wen <= #1 1'b0;
else
l0_wen <= #1 1'b1;
end
//
// Right WE
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
r0_wen <= 1'b1;
else
if (wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:2]) & ~wb_ack_o)
r0_wen <= #1 1'b0;
else
r0_wen <= #1 1'b1;
end
//
// Write acknowledge
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_we <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
ack_we <= #1 1'b1;
else
ack_we <= #1 1'b0;
end
//
// Generate d_oe signal (tristate control)
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
d_oe <= 1'b0;
else
if (~l0_wen | ~r0_wen)
d_oe <= 1'b1;
else
d_oe <= 1'b0;
end
//
// SRAM i/f monitor
//
// synopsys translate_off
integer fsram;
initial fsram = $fopen("sram.log");
always @(posedge wb_clk_i)
begin
if (~l0_wen | ~r0_wen)
$fdisplay(fsram, "%t [%h] <- write %h", $time, wb_adr_i, {r_d_o, l_d_o});
else
if ((l_oe | r_oe) & ~wb_we_i)
$fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, {r_d_i, l_d_i});
end
// synopsys translate_on
endmodule
`endif
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : alt_mem_ddrx_mm_st_converter
//
// File : alt_mem_ddrx_mm_st_converter.v
//
// Abstract : take in Avalon MM interface and convert it to single cmd and
// multiple data Avalon ST
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_mem_ddrx_mm_st_converter # (
parameter
AVL_SIZE_WIDTH = 3,
AVL_ADDR_WIDTH = 25,
AVL_DATA_WIDTH = 32,
LOCAL_ID_WIDTH = 8,
CFG_DWIDTH_RATIO = 4,
CFG_MM_ST_CONV_REG = 0
)
(
ctl_clk, // controller clock
ctl_reset_n, // controller reset_n, synchronous to ctl_clk
ctl_half_clk, // controller clock, half-rate
ctl_half_clk_reset_n, // controller reset_n, synchronous to ctl_half_clk
// Avalon data slave interface
avl_ready, // Avalon wait_n
avl_read_req, // Avalon read
avl_write_req, // Avalon write
avl_size, // Avalon burstcount
avl_burstbegin, // Avalon burstbegin
avl_addr, // Avalon address
avl_rdata_valid, // Avalon readdata_valid
avl_rdata, // Avalon readdata
avl_wdata, // Avalon writedata
avl_be, // Avalon byteenble
local_rdata_error, // Avalon readdata_error
local_multicast, // In-band multicast
local_autopch_req, // In-band auto-precharge request signal
local_priority, // In-band priority signal
// cmd channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
// write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id
);
localparam AVL_BE_WIDTH = AVL_DATA_WIDTH / 8;
input ctl_clk;
input ctl_reset_n;
input ctl_half_clk;
input ctl_half_clk_reset_n;
output avl_ready;
input avl_read_req;
input avl_write_req;
input [AVL_SIZE_WIDTH-1:0] avl_size;
input avl_burstbegin;
input [AVL_ADDR_WIDTH-1:0] avl_addr;
output avl_rdata_valid;
output [3:0] local_rdata_error;
output [AVL_DATA_WIDTH-1:0] avl_rdata;
input [AVL_DATA_WIDTH-1:0] avl_wdata;
input [AVL_BE_WIDTH-1:0] avl_be;
input local_multicast;
input local_autopch_req;
input local_priority;
input itf_cmd_ready;
output itf_cmd_valid;
output itf_cmd;
output [AVL_ADDR_WIDTH-1:0] itf_cmd_address;
output [AVL_SIZE_WIDTH-1:0] itf_cmd_burstlen;
output [LOCAL_ID_WIDTH-1:0] itf_cmd_id;
output itf_cmd_priority;
output itf_cmd_autopercharge;
output itf_cmd_multicast;
input itf_wr_data_ready;
output itf_wr_data_valid;
output [AVL_DATA_WIDTH-1:0] itf_wr_data;
output [AVL_BE_WIDTH-1:0] itf_wr_data_byte_en;
output itf_wr_data_begin;
output itf_wr_data_last;
output [LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
output itf_rd_data_ready;
input itf_rd_data_valid;
input [AVL_DATA_WIDTH-1:0] itf_rd_data;
input itf_rd_data_error;
input itf_rd_data_begin;
input itf_rd_data_last;
input [LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
reg [AVL_SIZE_WIDTH-1:0] burst_count;
wire int_ready;
wire itf_cmd; // high is write
wire itf_wr_if_ready;
wire [LOCAL_ID_WIDTH-1:0] itf_cmd_id;
wire itf_wr_data_begin;
wire itf_wr_data_last;
wire [LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
reg data_pass;
reg [AVL_SIZE_WIDTH-1:0] burst_counter;
reg avl_read_req_reg;
reg avl_write_req_reg;
reg [AVL_SIZE_WIDTH-1:0] avl_size_reg;
reg avl_burstbegin_reg;
reg [AVL_ADDR_WIDTH-1:0] avl_addr_reg;
reg [AVL_DATA_WIDTH-1:0] avl_wdata_reg;
reg [AVL_DATA_WIDTH/8-1:0] avl_be_reg;
reg itf_rd_data_valid_reg;
reg [AVL_DATA_WIDTH-1:0] itf_rd_data_reg;
reg [3:0] itf_rd_data_error_reg;
reg local_multicast_reg;
reg local_autopch_req_reg;
reg local_priority_reg;
generate
if (CFG_MM_ST_CONV_REG == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
avl_read_req_reg <= 1'b0;
avl_write_req_reg <= 1'b0;
avl_size_reg <= {AVL_SIZE_WIDTH{1'b0}};
avl_burstbegin_reg <= 1'b0;
avl_addr_reg <= {AVL_ADDR_WIDTH{1'b0}};
avl_wdata_reg <= {AVL_DATA_WIDTH{1'b0}};
avl_be_reg <= {AVL_BE_WIDTH{1'b0}};
itf_rd_data_valid_reg <= 1'b0;
itf_rd_data_reg <= {AVL_DATA_WIDTH{1'b0}};
itf_rd_data_error_reg <= 4'b0;
local_multicast_reg <= 1'b0;
local_autopch_req_reg <= 1'b0;
local_priority_reg <= 1'b0;
end else
begin
if (int_ready)
begin
avl_read_req_reg <= avl_read_req;
avl_write_req_reg <= avl_write_req;
avl_size_reg <= avl_size;
avl_burstbegin_reg <= avl_burstbegin;
avl_addr_reg <= avl_addr;
avl_wdata_reg <= avl_wdata;
avl_be_reg <= avl_be;
local_multicast_reg <= local_multicast;
local_autopch_req_reg <= local_autopch_req;
local_priority_reg <= local_priority;
end
itf_rd_data_valid_reg <= itf_rd_data_valid;
itf_rd_data_reg <= itf_rd_data;
itf_rd_data_error_reg <= itf_rd_data_error;
end
end
end else
begin
always @ (*)
begin
avl_read_req_reg = avl_read_req;
avl_write_req_reg = avl_write_req;
avl_size_reg = avl_size;
avl_burstbegin_reg = avl_burstbegin;
avl_addr_reg = avl_addr;
avl_wdata_reg = avl_wdata;
avl_be_reg = avl_be;
itf_rd_data_valid_reg = itf_rd_data_valid;
itf_rd_data_reg = itf_rd_data;
itf_rd_data_error_reg = {4{itf_rd_data_error}};
local_multicast_reg = local_multicast;
local_autopch_req_reg = local_autopch_req;
local_priority_reg = local_priority;
end
end
endgenerate
// when cmd_ready = 1'b1, avl_ready = 1'b1;
// when avl_write_req = 1'b1,
// take this write req and then then drive avl_ready until receive # of beats = avl_size?
// we will look at cmd_ready, if cmd_ready = 1'b0, avl_ready = 1'b0
// when cmd_ready = 1'b1, avl_ready = 1'b1;
// when local_ready_req = 1'b1,
// take this read_req
// we will look at cmd_ready, if cmd_ready = 1'b0, avl_ready = 1'b0
assign itf_cmd_valid = avl_read_req_reg | itf_wr_if_ready;
assign itf_wr_if_ready = itf_wr_data_ready & avl_write_req_reg & ~data_pass;
assign avl_ready = int_ready;
assign itf_rd_data_ready = 1'b1;
assign itf_cmd_address = avl_addr_reg ;
assign itf_cmd_burstlen = avl_size_reg ;
assign itf_cmd_autopercharge = local_autopch_req_reg ;
assign itf_cmd_priority = local_priority_reg ;
assign itf_cmd_multicast = local_multicast_reg ;
assign itf_cmd = avl_write_req_reg;
assign itf_cmd_id = {LOCAL_ID_WIDTH{1'b0}};
assign itf_wr_data_begin = 1'b0;
assign itf_wr_data_last = 1'b0;
assign itf_wr_data_id = {LOCAL_ID_WIDTH{1'b0}};
// write data channel
assign itf_wr_data_valid = (data_pass) ? avl_write_req_reg : itf_cmd_ready & avl_write_req_reg;
assign itf_wr_data = avl_wdata_reg ;
assign itf_wr_data_byte_en = avl_be_reg ;
// read data channel
assign avl_rdata_valid = itf_rd_data_valid_reg;
assign avl_rdata = itf_rd_data_reg;
assign local_rdata_error = itf_rd_data_error_reg;
assign int_ready = (data_pass) ? itf_wr_data_ready : ((itf_cmd) ? (itf_wr_data_ready & itf_cmd_ready) : itf_cmd_ready);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
burst_counter <= {AVL_SIZE_WIDTH{1'b0}};
else
begin
if (itf_wr_if_ready && avl_size_reg > 1 && itf_cmd_ready)
burst_counter <= avl_size_reg - 1'b1;
else if (avl_write_req_reg && itf_wr_data_ready)
burst_counter <= burst_counter - 1'b1;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
data_pass <= 1'b0;
else
begin
if (itf_wr_if_ready && avl_size_reg > 1 && itf_cmd_ready)
data_pass <= 1'b1;
else if (burst_counter == 1 && avl_write_req_reg && itf_wr_data_ready)
data_pass <= 1'b0;
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Sun Jun 18 18:22:31 2017
// Host : DESKTOP-GKPSR1F running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.v
// Design : clk_wiz_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(clk_out1,
reset,
locked,
clk_in1);
output clk_out1;
input reset;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire locked;
wire reset;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.locked(locked),
.reset(reset));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz
(clk_out1,
reset,
locked,
clk_in1);
output clk_out1;
input reset;
output locked;
input clk_in1;
wire clk_in1;
wire clk_in1_clk_wiz_0;
wire clk_out1;
wire clk_out1_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfbout_clk_wiz_0;
wire locked;
wire reset;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_wiz_0),
.O(clkfbout_buf_clk_wiz_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_clk_wiz_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_clk_wiz_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(10.250000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(12.500000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_wiz_0),
.CLKFBOUT(clkfbout_clk_wiz_0),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_clk_wiz_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_clk_wiz_0),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(reset));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Fri Oct 21 16:43:13 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
output [63:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5, intAS, SIGN_FLAG_EXP,
OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1,
ZERO_FLAG_SHT1, ADD_OVRFLW_NRM, left_right_SHT2, bit_shift_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, ADD_OVRFLW_NRM2,
SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM,
SIGN_FLAG_SFG, OP_FLAG_SFG, ZERO_FLAG_SFG,
inst_FSM_INPUT_ENABLE_state_next_1_, n1102, n1103, n1104, n1105,
n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115,
n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125,
n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135,
n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145,
n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155,
n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165,
n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175,
n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185,
n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195,
n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205,
n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215,
n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225,
n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235,
n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245,
n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255,
n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265,
n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275,
n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285,
n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295,
n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305,
n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315,
n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325,
n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335,
n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345,
n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355,
n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365,
n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375,
n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385,
n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395,
n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405,
n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415,
n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425,
n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435,
n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445,
n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455,
n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465,
n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475,
n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515,
n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525,
n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545,
n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555,
n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565,
n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585,
n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615,
n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625,
n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635,
n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645,
n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655,
n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665,
n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675,
n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685,
n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1695, n1696,
n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706,
n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716,
n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726,
n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736,
n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746,
n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756,
n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766,
n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776,
n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786,
n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796,
n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806,
n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816,
n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826,
n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836,
n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846,
n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856,
n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866,
n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876,
n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886,
n1887, n1888, n1889, n1890, n1891, n1892, DP_OP_15J2_122_2221_n35,
n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904,
n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914,
n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924,
n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934,
n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944,
n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954,
n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964,
n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974,
n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984,
n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994,
n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004,
n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014,
n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024,
n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034,
n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044,
n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054,
n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064,
n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074,
n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084,
n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094,
n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104,
n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114,
n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124,
n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134,
n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144,
n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154,
n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164,
n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174,
n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184,
n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194,
n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204,
n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214,
n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224,
n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234,
n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244,
n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254,
n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264,
n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274,
n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284,
n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294,
n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304,
n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314,
n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324,
n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334,
n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344,
n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354,
n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364,
n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374,
n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384,
n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394,
n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404,
n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414,
n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424,
n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434,
n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444,
n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454,
n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464,
n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474,
n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484,
n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494,
n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504,
n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514,
n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524,
n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534,
n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544,
n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554,
n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564,
n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574,
n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584,
n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594,
n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604,
n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614,
n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624,
n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634,
n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644,
n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654,
n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664,
n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674,
n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684,
n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694,
n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704,
n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714,
n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724,
n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734,
n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744,
n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754,
n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764,
n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774,
n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784,
n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794,
n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804,
n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814,
n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824,
n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834,
n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844,
n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854,
n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864,
n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874,
n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884,
n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894,
n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904,
n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914,
n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924,
n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934,
n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944,
n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954,
n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964,
n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974,
n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984,
n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994,
n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004,
n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014,
n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024,
n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034,
n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044,
n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054,
n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064,
n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074,
n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084,
n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094,
n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104,
n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114,
n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124,
n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134,
n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144,
n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154,
n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164,
n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174,
n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184,
n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194,
n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204,
n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214,
n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224,
n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234,
n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244,
n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254,
n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264,
n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274,
n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284,
n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294,
n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304,
n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314,
n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324,
n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334,
n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344,
n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354,
n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364,
n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374,
n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384,
n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394,
n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404,
n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414,
n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424,
n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434,
n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444,
n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454,
n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464,
n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474,
n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484,
n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494,
n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504,
n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514,
n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524,
n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534,
n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544,
n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554,
n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564,
n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574,
n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584,
n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594,
n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604,
n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614,
n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624,
n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634,
n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644,
n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654,
n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664,
n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674,
n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684,
n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694,
n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704,
n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714,
n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724,
n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734,
n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744,
n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754,
n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764,
n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774,
n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784,
n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794,
n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804,
n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814,
n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824,
n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834,
n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844,
n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854,
n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864,
n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874,
n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884,
n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894,
n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904,
n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914,
n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924,
n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934,
n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944,
n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954,
n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964,
n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974,
n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984,
n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994,
n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004,
n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014,
n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024,
n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034,
n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044,
n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054,
n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064,
n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074,
n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084,
n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094,
n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104,
n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114,
n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124,
n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134,
n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144,
n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154,
n4155, n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164,
n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174,
n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184,
n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194,
n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204,
n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214,
n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224,
n4225, n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234,
n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244,
n4245, n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254,
n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264,
n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274,
n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284,
n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294,
n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304,
n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314,
n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324,
n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334,
n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344,
n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354,
n4356, n4357, n4358, n4359, n4360;
wire [3:0] Shift_reg_FLAGS_7;
wire [63:0] intDX_EWSW;
wire [63:0] intDY_EWSW;
wire [62:0] DMP_EXP_EWSW;
wire [57:0] DmP_EXP_EWSW;
wire [62:0] DMP_SHT1_EWSW;
wire [51:0] DmP_mant_SHT1_SW;
wire [5:0] Shift_amount_SHT1_EWR;
wire [54:1] Raw_mant_NRM_SWR;
wire [54:0] Data_array_SWR;
wire [62:0] DMP_SHT2_EWSW;
wire [5:2] shift_value_SHT2_EWR;
wire [10:0] DMP_exp_NRM2_EW;
wire [10:0] DMP_exp_NRM_EW;
wire [5:0] LZD_output_NRM2_EW;
wire [62:0] DMP_SFG;
wire [54:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n1892), .CK(clk), .RN(
n4275), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1883), .CK(clk), .RN(n4275),
.Q(intDX_EWSW[0]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1882), .CK(clk), .RN(n4275),
.Q(intDX_EWSW[1]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1881), .CK(clk), .RN(n4275),
.Q(intDX_EWSW[2]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1879), .CK(clk), .RN(n4276),
.Q(intDX_EWSW[4]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1878), .CK(clk), .RN(n4276),
.Q(intDX_EWSW[5]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1877), .CK(clk), .RN(n4276),
.Q(intDX_EWSW[6]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1876), .CK(clk), .RN(n4276),
.Q(intDX_EWSW[7]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1874), .CK(clk), .RN(n4276),
.Q(intDX_EWSW[9]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1873), .CK(clk), .RN(n4276),
.Q(intDX_EWSW[10]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1867), .CK(clk), .RN(n4277),
.Q(intDX_EWSW[16]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1859), .CK(clk), .RN(n4278),
.Q(intDX_EWSW[24]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_32_ ( .D(n1851), .CK(clk), .RN(n4278),
.Q(intDX_EWSW[32]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_37_ ( .D(n1846), .CK(clk), .RN(n4279),
.Q(intDX_EWSW[37]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_38_ ( .D(n1845), .CK(clk), .RN(n4279),
.Q(intDX_EWSW[38]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_39_ ( .D(n1844), .CK(clk), .RN(n4279),
.Q(intDX_EWSW[39]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_40_ ( .D(n1843), .CK(clk), .RN(n4279),
.Q(intDX_EWSW[40]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_44_ ( .D(n1839), .CK(clk), .RN(n4280),
.Q(intDX_EWSW[44]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_47_ ( .D(n1836), .CK(clk), .RN(n4280),
.Q(intDX_EWSW[47]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_48_ ( .D(n1835), .CK(clk), .RN(n4280),
.Q(intDX_EWSW[48]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_52_ ( .D(n1831), .CK(clk), .RN(n4280),
.Q(intDX_EWSW[52]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_63_ ( .D(n1820), .CK(clk), .RN(n4282),
.Q(intDX_EWSW[63]) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1819), .CK(clk), .RN(n4282), .Q(
intAS) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(n1900), .CK(clk), .RN(n4282), .Q(ready) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_58_ ( .D(n1760), .CK(clk), .RN(n4288),
.Q(intDY_EWSW[58]) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_59_ ( .D(n1759), .CK(clk), .RN(n4288),
.Q(intDY_EWSW[59]) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_60_ ( .D(n1758), .CK(clk), .RN(n4288),
.Q(intDY_EWSW[60]) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_62_ ( .D(n1756), .CK(clk), .RN(n4288),
.Q(intDY_EWSW[62]) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_63_ ( .D(n1755), .CK(clk), .RN(n4288),
.Q(intDY_EWSW[63]) );
DFFRXLTS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n1697), .CK(clk), .RN(n4288),
.Q(shift_value_SHT2_EWR[2]) );
DFFRXLTS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n1696), .CK(clk), .RN(n4289),
.Q(shift_value_SHT2_EWR[3]), .QN(n4153) );
DFFRXLTS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n1695), .CK(clk), .RN(n4289),
.Q(shift_value_SHT2_EWR[4]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_54_ ( .D(n1752), .CK(clk), .RN(n4338), .Q(
Data_array_SWR[54]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_27_ ( .D(n1725), .CK(clk), .RN(n4329), .Q(
Data_array_SWR[27]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_26_ ( .D(n1724), .CK(clk), .RN(n4328), .Q(
Data_array_SWR[26]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_53_ ( .D(n1751), .CK(clk), .RN(n4338), .Q(
Data_array_SWR[53]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_52_ ( .D(n1750), .CK(clk), .RN(n4331), .Q(
Data_array_SWR[52]), .QN(n4092) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_49_ ( .D(n1747), .CK(clk), .RN(n4328), .Q(
Data_array_SWR[49]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_48_ ( .D(n1746), .CK(clk), .RN(n4338), .Q(
Data_array_SWR[48]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_43_ ( .D(n1741), .CK(clk), .RN(n4337), .Q(
Data_array_SWR[43]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_42_ ( .D(n1740), .CK(clk), .RN(n4334), .Q(
Data_array_SWR[42]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_41_ ( .D(n1739), .CK(clk), .RN(n4328), .Q(
Data_array_SWR[41]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_40_ ( .D(n1738), .CK(clk), .RN(n4328), .Q(
Data_array_SWR[40]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_39_ ( .D(n1737), .CK(clk), .RN(n4329), .Q(
Data_array_SWR[39]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_38_ ( .D(n1736), .CK(clk), .RN(n4328), .Q(
Data_array_SWR[38]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_37_ ( .D(n1735), .CK(clk), .RN(n4327), .Q(
Data_array_SWR[37]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_36_ ( .D(n1734), .CK(clk), .RN(n4328), .Q(
Data_array_SWR[36]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_35_ ( .D(n1733), .CK(clk), .RN(n4329), .Q(
Data_array_SWR[35]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_34_ ( .D(n1732), .CK(clk), .RN(n4328), .Q(
Data_array_SWR[34]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_33_ ( .D(n1731), .CK(clk), .RN(n4327), .Q(
Data_array_SWR[33]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_32_ ( .D(n1730), .CK(clk), .RN(n4328), .Q(
Data_array_SWR[32]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_31_ ( .D(n1729), .CK(clk), .RN(n4329), .Q(
Data_array_SWR[31]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_29_ ( .D(n1727), .CK(clk), .RN(n4328), .Q(
Data_array_SWR[29]), .QN(n4230) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1723), .CK(clk), .RN(n4327), .Q(
Data_array_SWR[25]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1722), .CK(clk), .RN(n4327), .Q(
Data_array_SWR[24]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1719), .CK(clk), .RN(n4333), .Q(
Data_array_SWR[21]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1718), .CK(clk), .RN(n4333), .Q(
Data_array_SWR[20]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1717), .CK(clk), .RN(n4327), .Q(
Data_array_SWR[19]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1716), .CK(clk), .RN(n4327), .Q(
Data_array_SWR[18]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1715), .CK(clk), .RN(n4327), .Q(
Data_array_SWR[17]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1714), .CK(clk), .RN(n4327), .Q(
Data_array_SWR[16]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1713), .CK(clk), .RN(n4339), .Q(
Data_array_SWR[15]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1712), .CK(clk), .RN(n4327), .Q(
Data_array_SWR[14]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1711), .CK(clk), .RN(n4327), .Q(
Data_array_SWR[13]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1710), .CK(clk), .RN(n4326), .Q(
Data_array_SWR[12]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1709), .CK(clk), .RN(n4336), .Q(
Data_array_SWR[11]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1707), .CK(clk), .RN(n4326), .Q(
Data_array_SWR[9]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1706), .CK(clk), .RN(n4326), .Q(
Data_array_SWR[8]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1705), .CK(clk), .RN(n4339), .Q(
Data_array_SWR[7]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1704), .CK(clk), .RN(n4326), .Q(
Data_array_SWR[6]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1703), .CK(clk), .RN(n4326), .Q(
Data_array_SWR[5]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1702), .CK(clk), .RN(n4326), .Q(
Data_array_SWR[4]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1701), .CK(clk), .RN(n4326), .Q(
Data_array_SWR[3]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1700), .CK(clk), .RN(n4326), .Q(
Data_array_SWR[2]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1699), .CK(clk), .RN(n4326), .Q(
Data_array_SWR[1]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1698), .CK(clk), .RN(n4326), .Q(
Data_array_SWR[0]) );
DFFRXLTS SHT2_STAGE_SHFTVARS1_Q_reg_5_ ( .D(n1693), .CK(clk), .RN(n4289),
.Q(shift_value_SHT2_EWR[5]), .QN(n4175) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1692), .CK(clk), .RN(n4344),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1691), .CK(clk), .RN(n4340),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1690), .CK(clk), .RN(n4289),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1689), .CK(clk), .RN(n4289),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1688), .CK(clk), .RN(n4289),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_5_ ( .D(n1687), .CK(clk), .RN(n4289),
.Q(Shift_amount_SHT1_EWR[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n1675), .CK(clk), .RN(n4289), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n1674), .CK(clk), .RN(n4289), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n1673), .CK(clk), .RN(n4289), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n1672), .CK(clk), .RN(n4290), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n1671), .CK(clk), .RN(n4290), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n1670), .CK(clk), .RN(n4290), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n1669), .CK(clk), .RN(n4290), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n1668), .CK(clk), .RN(n4290), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n1667), .CK(clk), .RN(n4290), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n1666), .CK(clk), .RN(n4290), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n1665), .CK(clk), .RN(n4290), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n1664), .CK(clk), .RN(n4290), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n1663), .CK(clk), .RN(n4290), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n1662), .CK(clk), .RN(n4291), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n1661), .CK(clk), .RN(n4291), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n1660), .CK(clk), .RN(n4291), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n1659), .CK(clk), .RN(n4291), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n1658), .CK(clk), .RN(n4291), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n1657), .CK(clk), .RN(n4291), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n1656), .CK(clk), .RN(n4291), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n1655), .CK(clk), .RN(n4291), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n1654), .CK(clk), .RN(n4291), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n1653), .CK(clk), .RN(n4291), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_23_ ( .D(n1652), .CK(clk), .RN(n4292), .Q(
DMP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_24_ ( .D(n1651), .CK(clk), .RN(n4292), .Q(
DMP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_25_ ( .D(n1650), .CK(clk), .RN(n4292), .Q(
DMP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_26_ ( .D(n1649), .CK(clk), .RN(n4292), .Q(
DMP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n1648), .CK(clk), .RN(n4292), .Q(
DMP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n1647), .CK(clk), .RN(n4292), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n1646), .CK(clk), .RN(n4292), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n1645), .CK(clk), .RN(n4292), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_31_ ( .D(n1644), .CK(clk), .RN(n4292), .Q(
DMP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_32_ ( .D(n1643), .CK(clk), .RN(n4292), .Q(
DMP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_33_ ( .D(n1642), .CK(clk), .RN(n4293), .Q(
DMP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_34_ ( .D(n1641), .CK(clk), .RN(n4293), .Q(
DMP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_35_ ( .D(n1640), .CK(clk), .RN(n4293), .Q(
DMP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_36_ ( .D(n1639), .CK(clk), .RN(n4293), .Q(
DMP_EXP_EWSW[36]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_37_ ( .D(n1638), .CK(clk), .RN(n4293), .Q(
DMP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_38_ ( .D(n1637), .CK(clk), .RN(n4293), .Q(
DMP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_39_ ( .D(n1636), .CK(clk), .RN(n4293), .Q(
DMP_EXP_EWSW[39]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_40_ ( .D(n1635), .CK(clk), .RN(n4293), .Q(
DMP_EXP_EWSW[40]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_41_ ( .D(n1634), .CK(clk), .RN(n4293), .Q(
DMP_EXP_EWSW[41]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_42_ ( .D(n1633), .CK(clk), .RN(n4293), .Q(
DMP_EXP_EWSW[42]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_43_ ( .D(n1632), .CK(clk), .RN(n4294), .Q(
DMP_EXP_EWSW[43]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_44_ ( .D(n1631), .CK(clk), .RN(n4294), .Q(
DMP_EXP_EWSW[44]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_45_ ( .D(n1630), .CK(clk), .RN(n4294), .Q(
DMP_EXP_EWSW[45]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_46_ ( .D(n1629), .CK(clk), .RN(n4294), .Q(
DMP_EXP_EWSW[46]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_47_ ( .D(n1628), .CK(clk), .RN(n4294), .Q(
DMP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_48_ ( .D(n1627), .CK(clk), .RN(n4294), .Q(
DMP_EXP_EWSW[48]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_49_ ( .D(n1626), .CK(clk), .RN(n4294), .Q(
DMP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_50_ ( .D(n1625), .CK(clk), .RN(n4294), .Q(
DMP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_51_ ( .D(n1624), .CK(clk), .RN(n4294), .Q(
DMP_EXP_EWSW[51]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_52_ ( .D(n1623), .CK(clk), .RN(n4294), .Q(
DMP_EXP_EWSW[52]), .QN(n4239) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_53_ ( .D(n1622), .CK(clk), .RN(n4295), .Q(
DMP_EXP_EWSW[53]), .QN(n4213) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_54_ ( .D(n1621), .CK(clk), .RN(n4295), .Q(
DMP_EXP_EWSW[54]), .QN(n4225) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_55_ ( .D(n1620), .CK(clk), .RN(n4295), .Q(
DMP_EXP_EWSW[55]), .QN(n4214) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_56_ ( .D(n1619), .CK(clk), .RN(n4295), .Q(
DMP_EXP_EWSW[56]), .QN(n4246) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_57_ ( .D(n1618), .CK(clk), .RN(n4295), .Q(
DMP_EXP_EWSW[57]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_58_ ( .D(n1617), .CK(clk), .RN(n4295), .Q(
DMP_EXP_EWSW[58]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_59_ ( .D(n1616), .CK(clk), .RN(n4295), .Q(
DMP_EXP_EWSW[59]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_60_ ( .D(n1615), .CK(clk), .RN(n4295), .Q(
DMP_EXP_EWSW[60]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_61_ ( .D(n1614), .CK(clk), .RN(n4295), .Q(
DMP_EXP_EWSW[61]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_62_ ( .D(n1613), .CK(clk), .RN(n4295), .Q(
DMP_EXP_EWSW[62]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1612), .CK(clk), .RN(n4296), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n1611), .CK(clk), .RN(n4296), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1610), .CK(clk), .RN(n4296), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1609), .CK(clk), .RN(n4296), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1608), .CK(clk), .RN(n4345), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1606), .CK(clk), .RN(n4296), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1605), .CK(clk), .RN(n4345), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1603), .CK(clk), .RN(n4296), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1602), .CK(clk), .RN(n4345), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n1601), .CK(clk), .RN(n4345), .Q(
DMP_SFG[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1600), .CK(clk), .RN(n4296), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1599), .CK(clk), .RN(n4345), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1597), .CK(clk), .RN(n4296), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1596), .CK(clk), .RN(n4353), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1594), .CK(clk), .RN(n4296), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1593), .CK(clk), .RN(n4353), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_5_ ( .D(n1592), .CK(clk), .RN(n4353), .Q(
DMP_SFG[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1591), .CK(clk), .RN(n4296), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1590), .CK(clk), .RN(n4353), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n1589), .CK(clk), .RN(n4353), .Q(
DMP_SFG[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1588), .CK(clk), .RN(n4297), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1587), .CK(clk), .RN(n4353), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1585), .CK(clk), .RN(n4297), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1584), .CK(clk), .RN(n4354), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_8_ ( .D(n1583), .CK(clk), .RN(n4359), .Q(
DMP_SFG[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1582), .CK(clk), .RN(n4297), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1581), .CK(clk), .RN(n4346), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1579), .CK(clk), .RN(n4297), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1578), .CK(clk), .RN(n4346), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1576), .CK(clk), .RN(n4297), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1575), .CK(clk), .RN(n4346), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n1574), .CK(clk), .RN(n4346), .Q(
DMP_SFG[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1573), .CK(clk), .RN(n4297), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1572), .CK(clk), .RN(n4346), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n1571), .CK(clk), .RN(n4346), .Q(
DMP_SFG[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1570), .CK(clk), .RN(n4297), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1569), .CK(clk), .RN(n4346), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n1568), .CK(clk), .RN(n4346), .Q(
DMP_SFG[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1567), .CK(clk), .RN(n4297), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1566), .CK(clk), .RN(n4347), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n1565), .CK(clk), .RN(n4347), .Q(
DMP_SFG[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1564), .CK(clk), .RN(n4297), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1563), .CK(clk), .RN(n4347), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1561), .CK(clk), .RN(n4297), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1560), .CK(clk), .RN(n4347), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1558), .CK(clk), .RN(n4298), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1557), .CK(clk), .RN(n4347), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n1556), .CK(clk), .RN(n4347), .Q(
DMP_SFG[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1555), .CK(clk), .RN(n4298), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1554), .CK(clk), .RN(n4347), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n1553), .CK(clk), .RN(n4347), .Q(
DMP_SFG[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1552), .CK(clk), .RN(n4298), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1551), .CK(clk), .RN(n4348), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1549), .CK(clk), .RN(n4298), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1548), .CK(clk), .RN(n4348), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n1547), .CK(clk), .RN(n4348), .Q(
DMP_SFG[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1546), .CK(clk), .RN(n4298), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1545), .CK(clk), .RN(n4348), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n1544), .CK(clk), .RN(n4348), .Q(
DMP_SFG[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1543), .CK(clk), .RN(n4298), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1542), .CK(clk), .RN(n4348), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n1541), .CK(clk), .RN(n4348), .Q(
DMP_SFG[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1540), .CK(clk), .RN(n4298), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1539), .CK(clk), .RN(n4348), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n1538), .CK(clk), .RN(n4348), .Q(
DMP_SFG[23]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1537), .CK(clk), .RN(n4298), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1536), .CK(clk), .RN(n4349), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n1535), .CK(clk), .RN(n4349), .Q(
DMP_SFG[24]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1534), .CK(clk), .RN(n4298), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1533), .CK(clk), .RN(n4349), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n1532), .CK(clk), .RN(n4349), .Q(
DMP_SFG[25]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1531), .CK(clk), .RN(n4298), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1530), .CK(clk), .RN(n4349), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n1529), .CK(clk), .RN(n4349), .Q(
DMP_SFG[26]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1528), .CK(clk), .RN(n4299), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1527), .CK(clk), .RN(n4349), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n1526), .CK(clk), .RN(n4349), .Q(
DMP_SFG[27]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1525), .CK(clk), .RN(n4299), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1524), .CK(clk), .RN(n4349), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n1523), .CK(clk), .RN(n4349), .Q(
DMP_SFG[28]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1522), .CK(clk), .RN(n4299), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1521), .CK(clk), .RN(n4350), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n1520), .CK(clk), .RN(n4350), .Q(
DMP_SFG[29]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1519), .CK(clk), .RN(n4299), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1518), .CK(clk), .RN(n4350), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n1517), .CK(clk), .RN(n4350), .Q(
DMP_SFG[30]), .QN(n1934) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_31_ ( .D(n1516), .CK(clk), .RN(n4299), .Q(
DMP_SHT1_EWSW[31]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_31_ ( .D(n1515), .CK(clk), .RN(n4350), .Q(
DMP_SHT2_EWSW[31]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_31_ ( .D(n1514), .CK(clk), .RN(n4350), .Q(
DMP_SFG[31]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_32_ ( .D(n1513), .CK(clk), .RN(n4299), .Q(
DMP_SHT1_EWSW[32]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_32_ ( .D(n1512), .CK(clk), .RN(n4350), .Q(
DMP_SHT2_EWSW[32]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_32_ ( .D(n1511), .CK(clk), .RN(n4350), .Q(
DMP_SFG[32]), .QN(n1935) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_33_ ( .D(n1510), .CK(clk), .RN(n4299), .Q(
DMP_SHT1_EWSW[33]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_33_ ( .D(n1509), .CK(clk), .RN(n4350), .Q(
DMP_SHT2_EWSW[33]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_33_ ( .D(n1508), .CK(clk), .RN(n4350), .Q(
DMP_SFG[33]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_34_ ( .D(n1507), .CK(clk), .RN(n4299), .Q(
DMP_SHT1_EWSW[34]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_34_ ( .D(n1506), .CK(clk), .RN(n4351), .Q(
DMP_SHT2_EWSW[34]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_34_ ( .D(n1505), .CK(clk), .RN(n4351), .Q(
DMP_SFG[34]), .QN(n1936) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_35_ ( .D(n1504), .CK(clk), .RN(n4299), .Q(
DMP_SHT1_EWSW[35]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_35_ ( .D(n1503), .CK(clk), .RN(n4299), .Q(
DMP_SHT2_EWSW[35]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_35_ ( .D(n1502), .CK(clk), .RN(n4351), .Q(
DMP_SFG[35]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_36_ ( .D(n1501), .CK(clk), .RN(n4300), .Q(
DMP_SHT1_EWSW[36]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_36_ ( .D(n1500), .CK(clk), .RN(n4300), .Q(
DMP_SHT2_EWSW[36]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_36_ ( .D(n1499), .CK(clk), .RN(n4351), .Q(
DMP_SFG[36]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_37_ ( .D(n1498), .CK(clk), .RN(n4300), .Q(
DMP_SHT1_EWSW[37]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_37_ ( .D(n1497), .CK(clk), .RN(n4300), .Q(
DMP_SHT2_EWSW[37]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_37_ ( .D(n1496), .CK(clk), .RN(n4351), .Q(
DMP_SFG[37]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_38_ ( .D(n1495), .CK(clk), .RN(n4300), .Q(
DMP_SHT1_EWSW[38]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_38_ ( .D(n1494), .CK(clk), .RN(n4300), .Q(
DMP_SHT2_EWSW[38]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_38_ ( .D(n1493), .CK(clk), .RN(n4351), .Q(
DMP_SFG[38]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_39_ ( .D(n1492), .CK(clk), .RN(n4300), .Q(
DMP_SHT1_EWSW[39]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_39_ ( .D(n1491), .CK(clk), .RN(n4300), .Q(
DMP_SHT2_EWSW[39]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_39_ ( .D(n1490), .CK(clk), .RN(n4351), .Q(
DMP_SFG[39]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_40_ ( .D(n1489), .CK(clk), .RN(n4300), .Q(
DMP_SHT1_EWSW[40]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_40_ ( .D(n1488), .CK(clk), .RN(n4300), .Q(
DMP_SHT2_EWSW[40]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_40_ ( .D(n1487), .CK(clk), .RN(n4351), .Q(
DMP_SFG[40]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_41_ ( .D(n1486), .CK(clk), .RN(n4301), .Q(
DMP_SHT1_EWSW[41]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_41_ ( .D(n1485), .CK(clk), .RN(n4301), .Q(
DMP_SHT2_EWSW[41]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_41_ ( .D(n1484), .CK(clk), .RN(n4351), .Q(
DMP_SFG[41]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_42_ ( .D(n1483), .CK(clk), .RN(n4301), .Q(
DMP_SHT1_EWSW[42]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_42_ ( .D(n1482), .CK(clk), .RN(n4301), .Q(
DMP_SHT2_EWSW[42]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_42_ ( .D(n1481), .CK(clk), .RN(n4351), .Q(
DMP_SFG[42]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_43_ ( .D(n1480), .CK(clk), .RN(n4301), .Q(
DMP_SHT1_EWSW[43]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_43_ ( .D(n1479), .CK(clk), .RN(n4301), .Q(
DMP_SHT2_EWSW[43]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_43_ ( .D(n1478), .CK(clk), .RN(n4352), .Q(
DMP_SFG[43]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_44_ ( .D(n1477), .CK(clk), .RN(n4301), .Q(
DMP_SHT1_EWSW[44]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_44_ ( .D(n1476), .CK(clk), .RN(n4301), .Q(
DMP_SHT2_EWSW[44]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_44_ ( .D(n1475), .CK(clk), .RN(n4352), .Q(
DMP_SFG[44]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_45_ ( .D(n1474), .CK(clk), .RN(n4301), .Q(
DMP_SHT1_EWSW[45]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_45_ ( .D(n1473), .CK(clk), .RN(n4301), .Q(
DMP_SHT2_EWSW[45]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_45_ ( .D(n1472), .CK(clk), .RN(n4352), .Q(
DMP_SFG[45]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_46_ ( .D(n1471), .CK(clk), .RN(n4302), .Q(
DMP_SHT1_EWSW[46]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_46_ ( .D(n1470), .CK(clk), .RN(n4302), .Q(
DMP_SHT2_EWSW[46]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_46_ ( .D(n1469), .CK(clk), .RN(n4352), .Q(
DMP_SFG[46]), .QN(n1939) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_47_ ( .D(n1468), .CK(clk), .RN(n4302), .Q(
DMP_SHT1_EWSW[47]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_47_ ( .D(n1467), .CK(clk), .RN(n4302), .Q(
DMP_SHT2_EWSW[47]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_47_ ( .D(n1466), .CK(clk), .RN(n4352), .Q(
DMP_SFG[47]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_48_ ( .D(n1465), .CK(clk), .RN(n4302), .Q(
DMP_SHT1_EWSW[48]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_48_ ( .D(n1464), .CK(clk), .RN(n4302), .Q(
DMP_SHT2_EWSW[48]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_48_ ( .D(n1463), .CK(clk), .RN(n4352), .Q(
DMP_SFG[48]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_49_ ( .D(n1462), .CK(clk), .RN(n4302), .Q(
DMP_SHT1_EWSW[49]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_49_ ( .D(n1461), .CK(clk), .RN(n4302), .Q(
DMP_SHT2_EWSW[49]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_49_ ( .D(n1460), .CK(clk), .RN(n4352), .Q(
DMP_SFG[49]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_50_ ( .D(n1459), .CK(clk), .RN(n4302), .Q(
DMP_SHT1_EWSW[50]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_50_ ( .D(n1458), .CK(clk), .RN(n4302), .Q(
DMP_SHT2_EWSW[50]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_50_ ( .D(n1457), .CK(clk), .RN(n4352), .Q(
DMP_SFG[50]), .QN(n1938) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_51_ ( .D(n1456), .CK(clk), .RN(n4303), .Q(
DMP_SHT1_EWSW[51]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_51_ ( .D(n1455), .CK(clk), .RN(n4303), .Q(
DMP_SHT2_EWSW[51]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_51_ ( .D(n1454), .CK(clk), .RN(n4352), .Q(
DMP_SFG[51]), .QN(n1937) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_52_ ( .D(n1453), .CK(clk), .RN(n4303), .Q(
DMP_SHT1_EWSW[52]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_52_ ( .D(n1452), .CK(clk), .RN(n4303), .Q(
DMP_SHT2_EWSW[52]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_52_ ( .D(n1451), .CK(clk), .RN(n4303), .Q(
DMP_SFG[52]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1450), .CK(clk), .RN(n4303), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1449), .CK(clk), .RN(n4330), .Q(
DMP_exp_NRM2_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_53_ ( .D(n1448), .CK(clk), .RN(n4303), .Q(
DMP_SHT1_EWSW[53]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_53_ ( .D(n1447), .CK(clk), .RN(n4303), .Q(
DMP_SHT2_EWSW[53]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_53_ ( .D(n1446), .CK(clk), .RN(n4303), .Q(
DMP_SFG[53]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1445), .CK(clk), .RN(n4303), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1444), .CK(clk), .RN(n4330), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_54_ ( .D(n1443), .CK(clk), .RN(n4304), .Q(
DMP_SHT1_EWSW[54]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_54_ ( .D(n1442), .CK(clk), .RN(n4304), .Q(
DMP_SHT2_EWSW[54]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_54_ ( .D(n1441), .CK(clk), .RN(n4304), .Q(
DMP_SFG[54]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1440), .CK(clk), .RN(n4304), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1439), .CK(clk), .RN(n4330), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_55_ ( .D(n1438), .CK(clk), .RN(n4304), .Q(
DMP_SHT1_EWSW[55]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_55_ ( .D(n1437), .CK(clk), .RN(n4304), .Q(
DMP_SHT2_EWSW[55]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_55_ ( .D(n1436), .CK(clk), .RN(n4304), .Q(
DMP_SFG[55]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1435), .CK(clk), .RN(n4304), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1434), .CK(clk), .RN(n4330), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_56_ ( .D(n1433), .CK(clk), .RN(n4304), .Q(
DMP_SHT1_EWSW[56]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_56_ ( .D(n1432), .CK(clk), .RN(n4304), .Q(
DMP_SHT2_EWSW[56]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_56_ ( .D(n1431), .CK(clk), .RN(n4305), .Q(
DMP_SFG[56]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1430), .CK(clk), .RN(n4305), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1429), .CK(clk), .RN(n4330), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_57_ ( .D(n1428), .CK(clk), .RN(n4305), .Q(
DMP_SHT1_EWSW[57]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_57_ ( .D(n1427), .CK(clk), .RN(n4305), .Q(
DMP_SHT2_EWSW[57]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_57_ ( .D(n1426), .CK(clk), .RN(n4305), .Q(
DMP_SFG[57]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1425), .CK(clk), .RN(n4305), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1424), .CK(clk), .RN(n4330), .Q(
DMP_exp_NRM2_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_58_ ( .D(n1423), .CK(clk), .RN(n4305), .Q(
DMP_SHT1_EWSW[58]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_58_ ( .D(n1422), .CK(clk), .RN(n4305), .Q(
DMP_SHT2_EWSW[58]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_58_ ( .D(n1421), .CK(clk), .RN(n4305), .Q(
DMP_SFG[58]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1420), .CK(clk), .RN(n4305), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1419), .CK(clk), .RN(n4330), .Q(
DMP_exp_NRM2_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_59_ ( .D(n1418), .CK(clk), .RN(n4306), .Q(
DMP_SHT1_EWSW[59]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_59_ ( .D(n1417), .CK(clk), .RN(n4306), .Q(
DMP_SHT2_EWSW[59]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_59_ ( .D(n1416), .CK(clk), .RN(n4306), .Q(
DMP_SFG[59]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1415), .CK(clk), .RN(n4306), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1414), .CK(clk), .RN(n4330), .Q(
DMP_exp_NRM2_EW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_60_ ( .D(n1413), .CK(clk), .RN(n4306), .Q(
DMP_SHT1_EWSW[60]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_60_ ( .D(n1412), .CK(clk), .RN(n4306), .Q(
DMP_SHT2_EWSW[60]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_60_ ( .D(n1411), .CK(clk), .RN(n4306), .Q(
DMP_SFG[60]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_8_ ( .D(n1410), .CK(clk), .RN(n4306), .Q(
DMP_exp_NRM_EW[8]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1409), .CK(clk), .RN(n4330), .Q(
DMP_exp_NRM2_EW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_61_ ( .D(n1408), .CK(clk), .RN(n4306), .Q(
DMP_SHT1_EWSW[61]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_61_ ( .D(n1407), .CK(clk), .RN(n4306), .Q(
DMP_SHT2_EWSW[61]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_61_ ( .D(n1406), .CK(clk), .RN(n4307), .Q(
DMP_SFG[61]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_9_ ( .D(n1405), .CK(clk), .RN(n4307), .Q(
DMP_exp_NRM_EW[9]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1404), .CK(clk), .RN(n4331), .Q(
DMP_exp_NRM2_EW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_62_ ( .D(n1403), .CK(clk), .RN(n4307), .Q(
DMP_SHT1_EWSW[62]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_62_ ( .D(n1402), .CK(clk), .RN(n4307), .Q(
DMP_SHT2_EWSW[62]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_62_ ( .D(n1401), .CK(clk), .RN(n4307), .Q(
DMP_SFG[62]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_10_ ( .D(n1400), .CK(clk), .RN(n4307), .Q(
DMP_exp_NRM_EW[10]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1399), .CK(clk), .RN(n4331),
.Q(DMP_exp_NRM2_EW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n1398), .CK(clk), .RN(n4307), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1397), .CK(clk), .RN(n4307), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n1396), .CK(clk), .RN(n4307), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1395), .CK(clk), .RN(n4307), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n1394), .CK(clk), .RN(n4308), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1393), .CK(clk), .RN(n4308), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n1392), .CK(clk), .RN(n4308), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1391), .CK(clk), .RN(n4308), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n1390), .CK(clk), .RN(n4308), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1389), .CK(clk), .RN(n4308), .Q(
DmP_mant_SHT1_SW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n1388), .CK(clk), .RN(n4308), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1387), .CK(clk), .RN(n4308), .Q(
DmP_mant_SHT1_SW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n1386), .CK(clk), .RN(n4308), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1385), .CK(clk), .RN(n4308), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n1384), .CK(clk), .RN(n4309), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1383), .CK(clk), .RN(n4309), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n1382), .CK(clk), .RN(n4309), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1381), .CK(clk), .RN(n4309), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n1380), .CK(clk), .RN(n4309), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1379), .CK(clk), .RN(n4309), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n1378), .CK(clk), .RN(n4309), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1377), .CK(clk), .RN(n4309),
.Q(DmP_mant_SHT1_SW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n1376), .CK(clk), .RN(n4309), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1375), .CK(clk), .RN(n4309),
.Q(DmP_mant_SHT1_SW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n1374), .CK(clk), .RN(n4310), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1373), .CK(clk), .RN(n4310),
.Q(DmP_mant_SHT1_SW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n1372), .CK(clk), .RN(n4310), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1371), .CK(clk), .RN(n4310),
.Q(DmP_mant_SHT1_SW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n1370), .CK(clk), .RN(n4310), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1369), .CK(clk), .RN(n4310),
.Q(DmP_mant_SHT1_SW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n1368), .CK(clk), .RN(n4310), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1367), .CK(clk), .RN(n4310),
.Q(DmP_mant_SHT1_SW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n1366), .CK(clk), .RN(n4310), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1365), .CK(clk), .RN(n4310),
.Q(DmP_mant_SHT1_SW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n1364), .CK(clk), .RN(n4311), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1363), .CK(clk), .RN(n4311),
.Q(DmP_mant_SHT1_SW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n1362), .CK(clk), .RN(n4311), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1361), .CK(clk), .RN(n4311),
.Q(DmP_mant_SHT1_SW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n1360), .CK(clk), .RN(n4311), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1359), .CK(clk), .RN(n4311),
.Q(DmP_mant_SHT1_SW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n1358), .CK(clk), .RN(n4311), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1357), .CK(clk), .RN(n4311),
.Q(DmP_mant_SHT1_SW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n1356), .CK(clk), .RN(n4311), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1355), .CK(clk), .RN(n4311),
.Q(DmP_mant_SHT1_SW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n1354), .CK(clk), .RN(n4312), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1353), .CK(clk), .RN(n4337),
.Q(DmP_mant_SHT1_SW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(n1352), .CK(clk), .RN(n4312), .Q(
DmP_EXP_EWSW[23]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_23_ ( .D(n1351), .CK(clk), .RN(n4337),
.Q(DmP_mant_SHT1_SW[23]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_24_ ( .D(n1350), .CK(clk), .RN(n4312), .Q(
DmP_EXP_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_24_ ( .D(n1349), .CK(clk), .RN(n4336),
.Q(DmP_mant_SHT1_SW[24]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_25_ ( .D(n1348), .CK(clk), .RN(n4312), .Q(
DmP_EXP_EWSW[25]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_25_ ( .D(n1347), .CK(clk), .RN(n4312),
.Q(DmP_mant_SHT1_SW[25]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_26_ ( .D(n1346), .CK(clk), .RN(n4312), .Q(
DmP_EXP_EWSW[26]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_26_ ( .D(n1345), .CK(clk), .RN(n4312),
.Q(DmP_mant_SHT1_SW[26]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_27_ ( .D(n1344), .CK(clk), .RN(n4312), .Q(
DmP_EXP_EWSW[27]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_27_ ( .D(n1343), .CK(clk), .RN(n4312),
.Q(DmP_mant_SHT1_SW[27]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_28_ ( .D(n1342), .CK(clk), .RN(n4312), .Q(
DmP_EXP_EWSW[28]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_28_ ( .D(n1341), .CK(clk), .RN(n4313),
.Q(DmP_mant_SHT1_SW[28]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_29_ ( .D(n1340), .CK(clk), .RN(n4313), .Q(
DmP_EXP_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_29_ ( .D(n1339), .CK(clk), .RN(n4313),
.Q(DmP_mant_SHT1_SW[29]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_30_ ( .D(n1338), .CK(clk), .RN(n4313), .Q(
DmP_EXP_EWSW[30]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_30_ ( .D(n1337), .CK(clk), .RN(n4313),
.Q(DmP_mant_SHT1_SW[30]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_31_ ( .D(n1336), .CK(clk), .RN(n4313), .Q(
DmP_EXP_EWSW[31]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_31_ ( .D(n1335), .CK(clk), .RN(n4313),
.Q(DmP_mant_SHT1_SW[31]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_32_ ( .D(n1334), .CK(clk), .RN(n4313), .Q(
DmP_EXP_EWSW[32]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_32_ ( .D(n1333), .CK(clk), .RN(n4313),
.Q(DmP_mant_SHT1_SW[32]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_33_ ( .D(n1332), .CK(clk), .RN(n4313), .Q(
DmP_EXP_EWSW[33]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_33_ ( .D(n1331), .CK(clk), .RN(n4314),
.Q(DmP_mant_SHT1_SW[33]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_34_ ( .D(n1330), .CK(clk), .RN(n4314), .Q(
DmP_EXP_EWSW[34]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_34_ ( .D(n1329), .CK(clk), .RN(n4314),
.Q(DmP_mant_SHT1_SW[34]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_35_ ( .D(n1328), .CK(clk), .RN(n4314), .Q(
DmP_EXP_EWSW[35]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_35_ ( .D(n1327), .CK(clk), .RN(n4314),
.Q(DmP_mant_SHT1_SW[35]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_36_ ( .D(n1326), .CK(clk), .RN(n4314), .Q(
DmP_EXP_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_36_ ( .D(n1325), .CK(clk), .RN(n4314),
.Q(DmP_mant_SHT1_SW[36]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_37_ ( .D(n1324), .CK(clk), .RN(n4314), .Q(
DmP_EXP_EWSW[37]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_37_ ( .D(n1323), .CK(clk), .RN(n4314),
.Q(DmP_mant_SHT1_SW[37]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_38_ ( .D(n1322), .CK(clk), .RN(n4314), .Q(
DmP_EXP_EWSW[38]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_38_ ( .D(n1321), .CK(clk), .RN(n4315),
.Q(DmP_mant_SHT1_SW[38]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_39_ ( .D(n1320), .CK(clk), .RN(n4315), .Q(
DmP_EXP_EWSW[39]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_39_ ( .D(n1319), .CK(clk), .RN(n4315),
.Q(DmP_mant_SHT1_SW[39]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_40_ ( .D(n1318), .CK(clk), .RN(n4315), .Q(
DmP_EXP_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_40_ ( .D(n1317), .CK(clk), .RN(n4315),
.Q(DmP_mant_SHT1_SW[40]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_41_ ( .D(n1316), .CK(clk), .RN(n4315), .Q(
DmP_EXP_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_41_ ( .D(n1315), .CK(clk), .RN(n4315),
.Q(DmP_mant_SHT1_SW[41]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_42_ ( .D(n1314), .CK(clk), .RN(n4315), .Q(
DmP_EXP_EWSW[42]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_42_ ( .D(n1313), .CK(clk), .RN(n4315),
.Q(DmP_mant_SHT1_SW[42]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_43_ ( .D(n1312), .CK(clk), .RN(n4315), .Q(
DmP_EXP_EWSW[43]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_43_ ( .D(n1311), .CK(clk), .RN(n4316),
.Q(DmP_mant_SHT1_SW[43]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_44_ ( .D(n1310), .CK(clk), .RN(n4316), .Q(
DmP_EXP_EWSW[44]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_44_ ( .D(n1309), .CK(clk), .RN(n4316),
.Q(DmP_mant_SHT1_SW[44]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_45_ ( .D(n1308), .CK(clk), .RN(n4316), .Q(
DmP_EXP_EWSW[45]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_45_ ( .D(n1307), .CK(clk), .RN(n4316),
.Q(DmP_mant_SHT1_SW[45]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_46_ ( .D(n1306), .CK(clk), .RN(n4316), .Q(
DmP_EXP_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_46_ ( .D(n1305), .CK(clk), .RN(n4316),
.Q(DmP_mant_SHT1_SW[46]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_47_ ( .D(n1304), .CK(clk), .RN(n4316), .Q(
DmP_EXP_EWSW[47]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_47_ ( .D(n1303), .CK(clk), .RN(n4316),
.Q(DmP_mant_SHT1_SW[47]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_48_ ( .D(n1302), .CK(clk), .RN(n4316), .Q(
DmP_EXP_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_48_ ( .D(n1301), .CK(clk), .RN(n4317),
.Q(DmP_mant_SHT1_SW[48]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_49_ ( .D(n1300), .CK(clk), .RN(n4317), .Q(
DmP_EXP_EWSW[49]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_49_ ( .D(n1299), .CK(clk), .RN(n4317),
.Q(DmP_mant_SHT1_SW[49]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_50_ ( .D(n1298), .CK(clk), .RN(n4317), .Q(
DmP_EXP_EWSW[50]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_50_ ( .D(n1297), .CK(clk), .RN(n4340),
.Q(DmP_mant_SHT1_SW[50]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_51_ ( .D(n1296), .CK(clk), .RN(n4317), .Q(
DmP_EXP_EWSW[51]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_52_ ( .D(n1294), .CK(clk), .RN(n4317), .Q(
DmP_EXP_EWSW[52]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_56_ ( .D(n1290), .CK(clk), .RN(n4317), .Q(
DmP_EXP_EWSW[56]), .QN(n4243) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_57_ ( .D(n1289), .CK(clk), .RN(n4318), .Q(
DmP_EXP_EWSW[57]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n1286), .CK(clk), .RN(n4318), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n1285), .CK(clk), .RN(n4318), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n1284), .CK(clk), .RN(n4318), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n1283), .CK(clk), .RN(n4318), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1282), .CK(clk), .RN(n4318),
.Q(ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1280), .CK(clk), .RN(n4318), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1279), .CK(clk), .RN(n4319), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1278), .CK(clk), .RN(n4344), .Q(
OP_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1277), .CK(clk), .RN(n4331), .Q(
ADD_OVRFLW_NRM) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1275), .CK(clk), .RN(n4319), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1274), .CK(clk), .RN(n4319), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1273), .CK(clk), .RN(n4319), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1272), .CK(clk), .RN(n4319), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1271), .CK(clk), .RN(n4319),
.Q(SIGN_FLAG_SHT1SHT2) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1269), .CK(clk), .RN(n4344), .QN(
n4174) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1265), .CK(clk), .RN(n4344), .Q(
Raw_mant_NRM_SWR[4]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1264), .CK(clk), .RN(n4343), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1258), .CK(clk), .RN(n4342), .Q(
Raw_mant_NRM_SWR[11]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1253), .CK(clk), .RN(n4340), .Q(
Raw_mant_NRM_SWR[16]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1250), .CK(clk), .RN(n4344), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1249), .CK(clk), .RN(n4342), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1248), .CK(clk), .RN(n4335), .Q(
Raw_mant_NRM_SWR[21]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1246), .CK(clk), .RN(n4342), .Q(
Raw_mant_NRM_SWR[23]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1245), .CK(clk), .RN(n4344), .Q(
Raw_mant_NRM_SWR[24]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_27_ ( .D(n1242), .CK(clk), .RN(n4344), .Q(
Raw_mant_NRM_SWR[27]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_33_ ( .D(n1236), .CK(clk), .RN(n4343), .Q(
Raw_mant_NRM_SWR[33]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_36_ ( .D(n1233), .CK(clk), .RN(n4343), .Q(
Raw_mant_NRM_SWR[36]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_37_ ( .D(n1232), .CK(clk), .RN(n4340), .Q(
Raw_mant_NRM_SWR[37]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_38_ ( .D(n1231), .CK(clk), .RN(n4339), .Q(
Raw_mant_NRM_SWR[38]), .QN(n4189) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_39_ ( .D(n1230), .CK(clk), .RN(n4341), .Q(
Raw_mant_NRM_SWR[39]), .QN(n4184) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_40_ ( .D(n1229), .CK(clk), .RN(n4341), .Q(
Raw_mant_NRM_SWR[40]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_41_ ( .D(n1228), .CK(clk), .RN(n4343), .Q(
Raw_mant_NRM_SWR[41]), .QN(n4058) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_42_ ( .D(n1227), .CK(clk), .RN(n4337), .Q(
Raw_mant_NRM_SWR[42]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_43_ ( .D(n1226), .CK(clk), .RN(n4342), .Q(
Raw_mant_NRM_SWR[43]), .QN(n4182) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_44_ ( .D(n1225), .CK(clk), .RN(n4342), .Q(
Raw_mant_NRM_SWR[44]), .QN(n4113) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_45_ ( .D(n1224), .CK(clk), .RN(n4341), .Q(
Raw_mant_NRM_SWR[45]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_47_ ( .D(n1222), .CK(clk), .RN(n4341), .Q(
Raw_mant_NRM_SWR[47]), .QN(n4176) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_48_ ( .D(n1221), .CK(clk), .RN(n4340), .Q(
Raw_mant_NRM_SWR[48]), .QN(n4114) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_50_ ( .D(n1219), .CK(clk), .RN(n4340), .Q(
Raw_mant_NRM_SWR[50]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_52_ ( .D(n1217), .CK(clk), .RN(n4341), .Q(
Raw_mant_NRM_SWR[52]), .QN(n4186) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_53_ ( .D(n1216), .CK(clk), .RN(n4340), .Q(
Raw_mant_NRM_SWR[53]), .QN(n4090) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_54_ ( .D(n1215), .CK(clk), .RN(n4331), .Q(
Raw_mant_NRM_SWR[54]), .QN(n4240) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_13_ ( .D(n1214), .CK(clk), .RN(n4329),
.Q(LZD_output_NRM2_EW[2]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_14_ ( .D(n1213), .CK(clk), .RN(n4329),
.Q(LZD_output_NRM2_EW[3]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1212), .CK(clk), .RN(n4329),
.Q(LZD_output_NRM2_EW[1]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_15_ ( .D(n1211), .CK(clk), .RN(n4329),
.Q(LZD_output_NRM2_EW[4]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1210), .CK(clk), .RN(n4329),
.Q(LZD_output_NRM2_EW[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_16_ ( .D(n1209), .CK(clk), .RN(n4330),
.Q(LZD_output_NRM2_EW[5]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1155), .CK(clk), .RN(n4343), .Q(
DmP_mant_SFG_SWR[1]), .QN(n1940) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_44_ ( .D(n1742), .CK(clk), .RN(n4338), .Q(
Data_array_SWR[44]), .QN(n4237) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_46_ ( .D(n1744), .CK(clk), .RN(n4338), .Q(
Data_array_SWR[46]), .QN(n4235) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_50_ ( .D(n1748), .CK(clk), .RN(n4338), .Q(
Data_array_SWR[50]), .QN(n4093) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_51_ ( .D(n1749), .CK(clk), .RN(n4340), .Q(
Data_array_SWR[51]), .QN(n4091) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1288), .CK(clk), .RN(n4318), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1281), .CK(clk), .RN(n4318), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_62_ ( .D(n1676), .CK(clk), .RN(n4324), .Q(
final_result_ieee[62]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_63_ ( .D(n1270), .CK(clk), .RN(n4319), .Q(
final_result_ieee[63]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1287), .CK(clk), .RN(n4318), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_52_ ( .D(n1686), .CK(clk), .RN(n4325), .Q(
final_result_ieee[52]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_53_ ( .D(n1685), .CK(clk), .RN(n4325), .Q(
final_result_ieee[53]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_54_ ( .D(n1684), .CK(clk), .RN(n4325), .Q(
final_result_ieee[54]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_57_ ( .D(n1681), .CK(clk), .RN(n4325), .Q(
final_result_ieee[57]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_58_ ( .D(n1680), .CK(clk), .RN(n4325), .Q(
final_result_ieee[58]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_59_ ( .D(n1679), .CK(clk), .RN(n4325), .Q(
final_result_ieee[59]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_61_ ( .D(n1677), .CK(clk), .RN(n4325), .Q(
final_result_ieee[61]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1208), .CK(clk), .RN(n4319), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1199), .CK(clk), .RN(n4320), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1198), .CK(clk), .RN(n4320), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1197), .CK(clk), .RN(n4320), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1196), .CK(clk), .RN(n4320), .Q(
final_result_ieee[31]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1195), .CK(clk), .RN(n4321), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_32_ ( .D(n1194), .CK(clk), .RN(n4321), .Q(
final_result_ieee[32]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1191), .CK(clk), .RN(n4321), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_34_ ( .D(n1190), .CK(clk), .RN(n4321), .Q(
final_result_ieee[34]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1189), .CK(clk), .RN(n4321), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_35_ ( .D(n1188), .CK(clk), .RN(n4321), .Q(
final_result_ieee[35]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1187), .CK(clk), .RN(n4321), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_36_ ( .D(n1186), .CK(clk), .RN(n4321), .Q(
final_result_ieee[36]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_37_ ( .D(n1184), .CK(clk), .RN(n4322), .Q(
final_result_ieee[37]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1183), .CK(clk), .RN(n4322), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_38_ ( .D(n1182), .CK(clk), .RN(n4322), .Q(
final_result_ieee[38]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1181), .CK(clk), .RN(n4322), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_39_ ( .D(n1180), .CK(clk), .RN(n4322), .Q(
final_result_ieee[39]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1179), .CK(clk), .RN(n4322), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_40_ ( .D(n1178), .CK(clk), .RN(n4322), .Q(
final_result_ieee[40]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1167), .CK(clk), .RN(n4323), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_46_ ( .D(n1166), .CK(clk), .RN(n4323), .Q(
final_result_ieee[46]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1165), .CK(clk), .RN(n4324), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_47_ ( .D(n1164), .CK(clk), .RN(n4324), .Q(
final_result_ieee[47]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1163), .CK(clk), .RN(n4324), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_48_ ( .D(n1162), .CK(clk), .RN(n4324), .Q(
final_result_ieee[48]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_55_ ( .D(n1683), .CK(clk), .RN(n4325), .Q(
final_result_ieee[55]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_56_ ( .D(n1682), .CK(clk), .RN(n4325), .Q(
final_result_ieee[56]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_60_ ( .D(n1678), .CK(clk), .RN(n4325), .Q(
final_result_ieee[60]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1185), .CK(clk), .RN(n4322), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1207), .CK(clk), .RN(n4319), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1206), .CK(clk), .RN(n4319), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1205), .CK(clk), .RN(n4320), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1204), .CK(clk), .RN(n4320), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1203), .CK(clk), .RN(n4320), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1202), .CK(clk), .RN(n4320), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1201), .CK(clk), .RN(n4320), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1200), .CK(clk), .RN(n4320), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1193), .CK(clk), .RN(n4321), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_33_ ( .D(n1192), .CK(clk), .RN(n4321), .Q(
final_result_ieee[33]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1177), .CK(clk), .RN(n4322), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_41_ ( .D(n1176), .CK(clk), .RN(n4322), .Q(
final_result_ieee[41]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1175), .CK(clk), .RN(n4323), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_42_ ( .D(n1174), .CK(clk), .RN(n4323), .Q(
final_result_ieee[42]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1173), .CK(clk), .RN(n4323), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_43_ ( .D(n1172), .CK(clk), .RN(n4323), .Q(
final_result_ieee[43]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1171), .CK(clk), .RN(n4323), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_44_ ( .D(n1170), .CK(clk), .RN(n4323), .Q(
final_result_ieee[44]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1169), .CK(clk), .RN(n4323), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_45_ ( .D(n1168), .CK(clk), .RN(n4323), .Q(
final_result_ieee[45]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1161), .CK(clk), .RN(n4324), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_49_ ( .D(n1160), .CK(clk), .RN(n4324), .Q(
final_result_ieee[49]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1159), .CK(clk), .RN(n4324), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_50_ ( .D(n1158), .CK(clk), .RN(n4324), .Q(
final_result_ieee[50]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_51_ ( .D(n1157), .CK(clk), .RN(n4324), .Q(
final_result_ieee[51]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1708), .CK(clk), .RN(n4337), .Q(
Data_array_SWR[10]), .QN(n4242) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_28_ ( .D(n1726), .CK(clk), .RN(n4328), .Q(
Data_array_SWR[28]), .QN(n4231) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1720), .CK(clk), .RN(n4337), .Q(
Data_array_SWR[22]), .QN(n4234) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1721), .CK(clk), .RN(n4336), .Q(
Data_array_SWR[23]), .QN(n4236) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_30_ ( .D(n1728), .CK(clk), .RN(n4335), .Q(
Data_array_SWR[30]), .QN(n4233) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_47_ ( .D(n1745), .CK(clk), .RN(n4339), .Q(
Data_array_SWR[47]), .QN(n4232) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_45_ ( .D(n1743), .CK(clk), .RN(n4335), .Q(
Data_array_SWR[45]), .QN(n4241) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_49_ ( .D(n1220), .CK(clk), .RN(n4341), .Q(
Raw_mant_NRM_SWR[49]), .QN(n4062) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_46_ ( .D(n1223), .CK(clk), .RN(n4341), .Q(
Raw_mant_NRM_SWR[46]), .QN(n4188) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n1559), .CK(clk), .RN(n4347), .Q(
DMP_SFG[16]) );
DFFRX1TS SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1276), .CK(clk), .RN(n4329),
.Q(ADD_OVRFLW_NRM2), .QN(DP_OP_15J2_122_2221_n35) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1132), .CK(clk), .RN(n4334), .Q(
DmP_mant_SFG_SWR[24]), .QN(n4253) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1268), .CK(clk), .RN(n4343), .Q(
Raw_mant_NRM_SWR[1]), .QN(n4053) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1138), .CK(clk), .RN(n4333), .Q(
DmP_mant_SFG_SWR[18]), .QN(n4103) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1149), .CK(clk), .RN(n4332), .Q(
DmP_mant_SFG_SWR[7]), .QN(n4260) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1861), .CK(clk), .RN(n4277),
.Q(intDX_EWSW[22]), .QN(n4155) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1864), .CK(clk), .RN(n4277),
.Q(intDX_EWSW[19]), .QN(n4151) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_38_ ( .D(n1780), .CK(clk), .RN(n4286),
.Q(intDY_EWSW[38]), .QN(n4204) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1794), .CK(clk), .RN(n4284),
.Q(intDY_EWSW[24]), .QN(n4169) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_61_ ( .D(n1822), .CK(clk), .RN(n4281),
.Q(intDX_EWSW[61]), .QN(n4071) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1853), .CK(clk), .RN(n4278),
.Q(intDX_EWSW[30]), .QN(n4154) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_45_ ( .D(n1773), .CK(clk), .RN(n4286),
.Q(intDY_EWSW[45]), .QN(n4193) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1816), .CK(clk), .RN(n4282),
.Q(intDY_EWSW[2]), .QN(n4171) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_53_ ( .D(n1293), .CK(clk), .RN(n4317), .Q(
DmP_EXP_EWSW[53]), .QN(n4226) );
DFFRXLTS inst_ShiftRegister_Q_reg_0_ ( .D(n1884), .CK(clk), .RN(n4275), .Q(
Shift_reg_FLAGS_7[0]), .QN(n4358) );
DFFRXLTS inst_ShiftRegister_Q_reg_2_ ( .D(n1886), .CK(clk), .RN(n4353), .Q(
Shift_reg_FLAGS_7[2]), .QN(n4357) );
DFFRXLTS inst_ShiftRegister_Q_reg_6_ ( .D(n1890), .CK(clk), .RN(n4275), .Q(
Shift_reg_FLAGS_7_6), .QN(n4360) );
DFFRXLTS inst_ShiftRegister_Q_reg_1_ ( .D(n1885), .CK(clk), .RN(n4352), .Q(
Shift_reg_FLAGS_7[1]), .QN(n4356) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n1753), .CK(clk), .RN(n4288),
.Q(left_right_SHT2), .QN(n4126) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n1595), .CK(clk), .RN(n4353), .Q(
DMP_SFG[4]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_7_ ( .D(n1586), .CK(clk), .RN(n4353), .Q(
DMP_SFG[7]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_0_ ( .D(n1607), .CK(clk), .RN(n4345), .Q(
DMP_SFG[0]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n1598), .CK(clk), .RN(n4345), .Q(
DMP_SFG[3]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n1577), .CK(clk), .RN(n4346), .Q(
DMP_SFG[10]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_9_ ( .D(n1580), .CK(clk), .RN(n4346), .Q(
DMP_SFG[9]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n1562), .CK(clk), .RN(n4347), .Q(
DMP_SFG[15]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n1550), .CK(clk), .RN(n4348), .Q(
DMP_SFG[19]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_1_ ( .D(n1604), .CK(clk), .RN(n4345), .Q(
DMP_SFG[1]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_51_ ( .D(n1218), .CK(clk), .RN(n4341), .Q(
Raw_mant_NRM_SWR[51]), .QN(n4157) );
DFFRXLTS inst_ShiftRegister_Q_reg_4_ ( .D(n1888), .CK(clk), .RN(n4353), .Q(
n4094), .QN(n4262) );
DFFRXLTS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n4275), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n4079) );
DFFRXLTS inst_ShiftRegister_Q_reg_5_ ( .D(n1889), .CK(clk), .RN(n4275), .Q(
Shift_reg_FLAGS_7_5), .QN(n4095) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_51_ ( .D(n1295), .CK(clk), .RN(n4340),
.Q(DmP_mant_SHT1_SW[51]), .QN(n4273) );
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n1887), .CK(clk), .RN(n4275), .Q(
Shift_reg_FLAGS_7[3]), .QN(n4187) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n1754), .CK(clk), .RN(n4288),
.Q(bit_shift_SHT2), .QN(n4210) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_27_ ( .D(n1129), .CK(clk), .RN(n4334), .Q(
DmP_mant_SFG_SWR[27]), .QN(n4099) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_29_ ( .D(n1127), .CK(clk), .RN(n4334), .Q(
DmP_mant_SFG_SWR[29]), .QN(n4272) );
DFFRXLTS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n1891), .CK(clk), .RN(
n4275), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n4211) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1244), .CK(clk), .RN(n4337), .Q(
Raw_mant_NRM_SWR[25]), .QN(n4118) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1252), .CK(clk), .RN(n4339), .Q(
Raw_mant_NRM_SWR[17]), .QN(n4181) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1263), .CK(clk), .RN(n4343), .Q(
Raw_mant_NRM_SWR[6]), .QN(n4179) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1133), .CK(clk), .RN(n4334), .Q(
DmP_mant_SFG_SWR[23]), .QN(n4254) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1137), .CK(clk), .RN(n4333), .Q(
DmP_mant_SFG_SWR[19]), .QN(n4255) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_26_ ( .D(n1130), .CK(clk), .RN(n4334), .Q(
DmP_mant_SFG_SWR[26]), .QN(n4251) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1131), .CK(clk), .RN(n4334), .Q(
DmP_mant_SFG_SWR[25]), .QN(n4252) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_35_ ( .D(n1121), .CK(clk), .RN(n4335), .Q(
DmP_mant_SFG_SWR[35]), .QN(n4270) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_31_ ( .D(n1125), .CK(clk), .RN(n4334), .Q(
DmP_mant_SFG_SWR[31]), .QN(n4271) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_30_ ( .D(n1126), .CK(clk), .RN(n4334), .Q(
DmP_mant_SFG_SWR[30]), .QN(n4265) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_28_ ( .D(n1128), .CK(clk), .RN(n4334), .Q(
DmP_mant_SFG_SWR[28]), .QN(n4266) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1262), .CK(clk), .RN(n4342), .Q(
Raw_mant_NRM_SWR[7]), .QN(n4185) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1266), .CK(clk), .RN(n4344), .Q(
Raw_mant_NRM_SWR[3]), .QN(n4183) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_26_ ( .D(n1243), .CK(clk), .RN(n4336), .Q(
Raw_mant_NRM_SWR[26]), .QN(n4227) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1256), .CK(clk), .RN(n4338), .Q(
Raw_mant_NRM_SWR[13]), .QN(n4158) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1259), .CK(clk), .RN(n4339), .Q(
Raw_mant_NRM_SWR[10]), .QN(n4152) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1255), .CK(clk), .RN(n4336), .Q(
Raw_mant_NRM_SWR[14]), .QN(n4248) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1257), .CK(clk), .RN(n4342), .Q(
Raw_mant_NRM_SWR[12]), .QN(n4177) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1251), .CK(clk), .RN(n4340), .Q(
Raw_mant_NRM_SWR[18]), .QN(n4125) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_31_ ( .D(n1238), .CK(clk), .RN(n4344), .Q(
Raw_mant_NRM_SWR[31]), .QN(n4117) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1267), .CK(clk), .RN(n4343), .Q(
Raw_mant_NRM_SWR[2]), .QN(n4224) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1260), .CK(clk), .RN(n4342), .Q(
Raw_mant_NRM_SWR[9]), .QN(n4072) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_32_ ( .D(n1237), .CK(clk), .RN(n4343), .Q(
Raw_mant_NRM_SWR[32]), .QN(n4180) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1261), .CK(clk), .RN(n4342), .Q(
Raw_mant_NRM_SWR[8]), .QN(n4249) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1254), .CK(clk), .RN(n4342), .Q(
Raw_mant_NRM_SWR[15]), .QN(n4076) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_29_ ( .D(n1240), .CK(clk), .RN(n4341), .Q(
Raw_mant_NRM_SWR[29]), .QN(n4142) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_28_ ( .D(n1241), .CK(clk), .RN(n4341), .Q(
Raw_mant_NRM_SWR[28]), .QN(n4229) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_30_ ( .D(n1239), .CK(clk), .RN(n4337), .Q(
Raw_mant_NRM_SWR[30]), .QN(n4228) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1247), .CK(clk), .RN(n4337), .Q(
Raw_mant_NRM_SWR[22]), .QN(n4139) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1139), .CK(clk), .RN(n4333), .Q(
DmP_mant_SFG_SWR[17]), .QN(n4104) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1140), .CK(clk), .RN(n4333), .Q(
DmP_mant_SFG_SWR[16]), .QN(n4105) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1156), .CK(clk), .RN(n4344), .Q(
DmP_mant_SFG_SWR[0]), .QN(n4274) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1134), .CK(clk), .RN(n4333), .Q(
DmP_mant_SFG_SWR[22]), .QN(n4100) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1135), .CK(clk), .RN(n4333), .Q(
DmP_mant_SFG_SWR[21]), .QN(n4101) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1136), .CK(clk), .RN(n4333), .Q(
DmP_mant_SFG_SWR[20]), .QN(n4102) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_33_ ( .D(n1123), .CK(clk), .RN(n4335), .Q(
DmP_mant_SFG_SWR[33]), .QN(n4116) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_34_ ( .D(n1122), .CK(clk), .RN(n4335), .Q(
DmP_mant_SFG_SWR[34]), .QN(n4049) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_32_ ( .D(n1124), .CK(clk), .RN(n4335), .Q(
DmP_mant_SFG_SWR[32]), .QN(n4048) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_54_ ( .D(n1102), .CK(clk), .RN(n4345), .Q(
DmP_mant_SFG_SWR[54]), .QN(n4250) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_37_ ( .D(n1119), .CK(clk), .RN(n4335), .Q(
DmP_mant_SFG_SWR[37]), .QN(n4123) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_36_ ( .D(n1120), .CK(clk), .RN(n4335), .Q(
DmP_mant_SFG_SWR[36]), .QN(n4050) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_38_ ( .D(n1118), .CK(clk), .RN(n4335), .Q(
DmP_mant_SFG_SWR[38]), .QN(n4120) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_53_ ( .D(n1103), .CK(clk), .RN(n4345), .Q(
DmP_mant_SFG_SWR[53]), .QN(n4238) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1154), .CK(clk), .RN(n4331), .Q(
DmP_mant_SFG_SWR[2]), .QN(n4261) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1147), .CK(clk), .RN(n4332), .Q(
DmP_mant_SFG_SWR[9]), .QN(n4258) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1148), .CK(clk), .RN(n4332), .Q(
DmP_mant_SFG_SWR[8]), .QN(n4259) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_47_ ( .D(n1109), .CK(clk), .RN(n4338), .Q(
DmP_mant_SFG_SWR[47]), .QN(n4267) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_45_ ( .D(n1111), .CK(clk), .RN(n4338), .Q(
DmP_mant_SFG_SWR[45]), .QN(n4268) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_52_ ( .D(n1104), .CK(clk), .RN(n4331), .Q(
DmP_mant_SFG_SWR[52]), .QN(n4263) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_34_ ( .D(n1235), .CK(clk), .RN(n4333), .Q(
Raw_mant_NRM_SWR[34]), .QN(n4115) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1153), .CK(clk), .RN(n4331), .Q(
DmP_mant_SFG_SWR[3]), .QN(n4098) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_51_ ( .D(n1105), .CK(clk), .RN(n4339), .Q(
DmP_mant_SFG_SWR[51]), .QN(n4208) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1854), .CK(clk), .RN(n4278),
.Q(intDX_EWSW[29]), .QN(n4132) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1855), .CK(clk), .RN(n4278),
.Q(intDX_EWSW[28]), .QN(n4136) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1856), .CK(clk), .RN(n4278),
.Q(intDX_EWSW[27]), .QN(n4150) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1857), .CK(clk), .RN(n4278),
.Q(intDX_EWSW[26]), .QN(n4075) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1858), .CK(clk), .RN(n4278),
.Q(intDX_EWSW[25]), .QN(n4144) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1860), .CK(clk), .RN(n4278),
.Q(intDX_EWSW[23]), .QN(n4061) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1145), .CK(clk), .RN(n4332), .Q(
DmP_mant_SFG_SWR[11]), .QN(n4256) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_41_ ( .D(n1115), .CK(clk), .RN(n4336), .Q(
DmP_mant_SFG_SWR[41]), .QN(n4128) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_42_ ( .D(n1114), .CK(clk), .RN(n4336), .Q(
DmP_mant_SFG_SWR[42]), .QN(n4127) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_43_ ( .D(n1113), .CK(clk), .RN(n4336), .Q(
DmP_mant_SFG_SWR[43]), .QN(n4269) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1143), .CK(clk), .RN(n4332), .Q(
DmP_mant_SFG_SWR[13]), .QN(n4108) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1144), .CK(clk), .RN(n4332), .Q(
DmP_mant_SFG_SWR[12]), .QN(n4109) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_40_ ( .D(n1116), .CK(clk), .RN(n4336), .Q(
DmP_mant_SFG_SWR[40]), .QN(n4119) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_39_ ( .D(n1117), .CK(clk), .RN(n4336), .Q(
DmP_mant_SFG_SWR[39]), .QN(n4122) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1141), .CK(clk), .RN(n4332), .Q(
DmP_mant_SFG_SWR[15]), .QN(n4106) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1142), .CK(clk), .RN(n4332), .Q(
DmP_mant_SFG_SWR[14]), .QN(n4107) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1146), .CK(clk), .RN(n4332), .Q(
DmP_mant_SFG_SWR[10]), .QN(n4257) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_44_ ( .D(n1112), .CK(clk), .RN(n4337), .Q(
DmP_mant_SFG_SWR[44]), .QN(n4264) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1862), .CK(clk), .RN(n4277),
.Q(intDX_EWSW[21]), .QN(n4134) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1863), .CK(clk), .RN(n4277),
.Q(intDX_EWSW[20]), .QN(n4137) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1865), .CK(clk), .RN(n4277),
.Q(intDX_EWSW[18]), .QN(n4074) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1868), .CK(clk), .RN(n4277),
.Q(intDX_EWSW[15]), .QN(n4060) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1870), .CK(clk), .RN(n4277),
.Q(intDX_EWSW[13]), .QN(n4133) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1880), .CK(clk), .RN(n4276),
.Q(intDX_EWSW[3]), .QN(n4121) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1866), .CK(clk), .RN(n4277),
.Q(intDX_EWSW[17]), .QN(n4146) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1869), .CK(clk), .RN(n4277),
.Q(intDX_EWSW[14]), .QN(n4124) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1871), .CK(clk), .RN(n4276),
.Q(intDX_EWSW[12]), .QN(n4138) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1872), .CK(clk), .RN(n4276),
.Q(intDX_EWSW[11]), .QN(n4145) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1875), .CK(clk), .RN(n4276),
.Q(intDX_EWSW[8]), .QN(n4147) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_35_ ( .D(n1234), .CK(clk), .RN(n4343), .Q(
Raw_mant_NRM_SWR[35]), .QN(n4178) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1791), .CK(clk), .RN(n4285),
.Q(intDY_EWSW[27]), .QN(n4069) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_50_ ( .D(n1768), .CK(clk), .RN(n4287),
.Q(intDY_EWSW[50]), .QN(n4205) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_49_ ( .D(n1769), .CK(clk), .RN(n4287),
.Q(intDY_EWSW[49]), .QN(n4209) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_48_ ( .D(n1770), .CK(clk), .RN(n4287),
.Q(intDY_EWSW[48]), .QN(n4190) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_37_ ( .D(n1781), .CK(clk), .RN(n4286),
.Q(intDY_EWSW[37]), .QN(n4202) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_36_ ( .D(n1782), .CK(clk), .RN(n4285),
.Q(intDY_EWSW[36]), .QN(n4194) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_35_ ( .D(n1783), .CK(clk), .RN(n4285),
.Q(intDY_EWSW[35]), .QN(n4081) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_34_ ( .D(n1784), .CK(clk), .RN(n4285),
.Q(intDY_EWSW[34]), .QN(n4196) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_33_ ( .D(n1785), .CK(clk), .RN(n4285),
.Q(intDY_EWSW[33]), .QN(n4192) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_32_ ( .D(n1786), .CK(clk), .RN(n4285),
.Q(intDY_EWSW[32]), .QN(n4172) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1787), .CK(clk), .RN(n4285),
.Q(intDY_EWSW[31]), .QN(n4088) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_55_ ( .D(n1763), .CK(clk), .RN(n4287),
.Q(intDY_EWSW[55]), .QN(n4063) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_40_ ( .D(n1778), .CK(clk), .RN(n4286),
.Q(intDY_EWSW[40]), .QN(n4200) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1788), .CK(clk), .RN(n4285),
.Q(intDY_EWSW[30]), .QN(n4218) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1789), .CK(clk), .RN(n4285),
.Q(intDY_EWSW[29]), .QN(n4065) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1790), .CK(clk), .RN(n4285),
.Q(intDY_EWSW[28]), .QN(n4166) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1792), .CK(clk), .RN(n4284),
.Q(intDY_EWSW[26]), .QN(n4168) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1793), .CK(clk), .RN(n4284),
.Q(intDY_EWSW[25]), .QN(n4067) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1795), .CK(clk), .RN(n4284),
.Q(intDY_EWSW[23]), .QN(n4087) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1796), .CK(clk), .RN(n4284),
.Q(intDY_EWSW[22]), .QN(n4217) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1797), .CK(clk), .RN(n4284),
.Q(intDY_EWSW[21]), .QN(n4161) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1800), .CK(clk), .RN(n4284),
.Q(intDY_EWSW[18]), .QN(n4167) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1801), .CK(clk), .RN(n4284),
.Q(intDY_EWSW[17]), .QN(n4066) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1802), .CK(clk), .RN(n4283),
.Q(intDY_EWSW[16]), .QN(n4191) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1803), .CK(clk), .RN(n4283),
.Q(intDY_EWSW[15]), .QN(n4086) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1804), .CK(clk), .RN(n4283),
.Q(intDY_EWSW[14]), .QN(n4216) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1805), .CK(clk), .RN(n4283),
.Q(intDY_EWSW[13]), .QN(n4160) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1806), .CK(clk), .RN(n4283),
.Q(intDY_EWSW[12]), .QN(n4164) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1811), .CK(clk), .RN(n4283),
.Q(intDY_EWSW[7]), .QN(n4221) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1815), .CK(clk), .RN(n4282),
.Q(intDY_EWSW[3]), .QN(n4064) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1818), .CK(clk), .RN(n4282),
.Q(intDY_EWSW[0]), .QN(n4170) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_62_ ( .D(n1821), .CK(clk), .RN(n4281),
.Q(intDX_EWSW[62]), .QN(n4215) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_59_ ( .D(n1824), .CK(clk), .RN(n4281),
.Q(intDX_EWSW[59]), .QN(n4077) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_58_ ( .D(n1825), .CK(clk), .RN(n4281),
.Q(intDX_EWSW[58]), .QN(n4219) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_53_ ( .D(n1830), .CK(clk), .RN(n4281),
.Q(intDX_EWSW[53]), .QN(n4244) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_49_ ( .D(n1834), .CK(clk), .RN(n4280),
.Q(intDX_EWSW[49]), .QN(n4223) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_55_ ( .D(n1828), .CK(clk), .RN(n4281),
.Q(intDX_EWSW[55]), .QN(n4245) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_54_ ( .D(n1829), .CK(clk), .RN(n4281),
.Q(intDX_EWSW[54]), .QN(n4096) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_57_ ( .D(n1826), .CK(clk), .RN(n4281),
.Q(intDX_EWSW[57]), .QN(n4149) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_50_ ( .D(n1833), .CK(clk), .RN(n4280),
.Q(intDX_EWSW[50]), .QN(n4148) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_45_ ( .D(n1838), .CK(clk), .RN(n4280),
.Q(intDX_EWSW[45]), .QN(n4143) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_43_ ( .D(n1840), .CK(clk), .RN(n4280),
.Q(intDX_EWSW[43]), .QN(n4056) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_36_ ( .D(n1847), .CK(clk), .RN(n4279),
.Q(intDX_EWSW[36]), .QN(n4131) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_35_ ( .D(n1848), .CK(clk), .RN(n4279),
.Q(intDX_EWSW[35]), .QN(n4057) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_33_ ( .D(n1850), .CK(clk), .RN(n4279),
.Q(intDX_EWSW[33]), .QN(n4129) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1852), .CK(clk), .RN(n4278),
.Q(intDX_EWSW[31]), .QN(n4059) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_42_ ( .D(n1841), .CK(clk), .RN(n4279),
.Q(intDX_EWSW[42]), .QN(n4140) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_34_ ( .D(n1849), .CK(clk), .RN(n4279),
.Q(intDX_EWSW[34]), .QN(n4141) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_41_ ( .D(n1842), .CK(clk), .RN(n4279),
.Q(intDX_EWSW[41]), .QN(n4130) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_46_ ( .D(n1837), .CK(clk), .RN(n4280),
.Q(intDX_EWSW[46]), .QN(n4135) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_51_ ( .D(n1832), .CK(clk), .RN(n4280),
.Q(intDX_EWSW[51]), .QN(n4073) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_61_ ( .D(n1757), .CK(clk), .RN(n4288),
.Q(intDY_EWSW[61]), .QN(n4156) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_57_ ( .D(n1761), .CK(clk), .RN(n4288),
.Q(intDY_EWSW[57]), .QN(n4206) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_56_ ( .D(n1762), .CK(clk), .RN(n4287),
.Q(intDY_EWSW[56]), .QN(n4055) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_54_ ( .D(n1764), .CK(clk), .RN(n4287),
.Q(intDY_EWSW[54]), .QN(n4080) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_53_ ( .D(n1765), .CK(clk), .RN(n4287),
.Q(intDY_EWSW[53]), .QN(n4054) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_52_ ( .D(n1766), .CK(clk), .RN(n4287),
.Q(intDY_EWSW[52]), .QN(n4222) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_51_ ( .D(n1767), .CK(clk), .RN(n4287),
.Q(intDY_EWSW[51]), .QN(n4198) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_47_ ( .D(n1771), .CK(clk), .RN(n4287),
.Q(intDY_EWSW[47]), .QN(n4201) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_46_ ( .D(n1772), .CK(clk), .RN(n4286),
.Q(intDY_EWSW[46]), .QN(n4083) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_44_ ( .D(n1774), .CK(clk), .RN(n4286),
.Q(intDY_EWSW[44]), .QN(n4195) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_43_ ( .D(n1775), .CK(clk), .RN(n4286),
.Q(intDY_EWSW[43]), .QN(n4082) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_42_ ( .D(n1776), .CK(clk), .RN(n4286),
.Q(intDY_EWSW[42]), .QN(n4197) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_41_ ( .D(n1777), .CK(clk), .RN(n4286),
.Q(intDY_EWSW[41]), .QN(n4084) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_39_ ( .D(n1779), .CK(clk), .RN(n4286),
.Q(intDY_EWSW[39]), .QN(n4199) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1798), .CK(clk), .RN(n4284),
.Q(intDY_EWSW[20]), .QN(n4165) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1799), .CK(clk), .RN(n4284),
.Q(intDY_EWSW[19]), .QN(n4068) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1807), .CK(clk), .RN(n4283),
.Q(intDY_EWSW[11]), .QN(n4085) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1808), .CK(clk), .RN(n4283),
.Q(intDY_EWSW[10]), .QN(n4162) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1809), .CK(clk), .RN(n4283),
.Q(intDY_EWSW[9]), .QN(n4163) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1810), .CK(clk), .RN(n4283),
.Q(intDY_EWSW[8]), .QN(n4070) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1812), .CK(clk), .RN(n4282),
.Q(intDY_EWSW[6]), .QN(n4089) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1813), .CK(clk), .RN(n4282),
.Q(intDY_EWSW[5]), .QN(n4207) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1814), .CK(clk), .RN(n4282),
.Q(intDY_EWSW[4]), .QN(n4078) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1817), .CK(clk), .RN(n4282),
.Q(intDY_EWSW[1]), .QN(n4203) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_60_ ( .D(n1823), .CK(clk), .RN(n4281),
.Q(intDX_EWSW[60]), .QN(n4220) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_56_ ( .D(n1827), .CK(clk), .RN(n4281),
.Q(intDX_EWSW[56]), .QN(n4097) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1150), .CK(clk), .RN(n4332), .Q(
DmP_mant_SFG_SWR[6]), .QN(n4110) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1151), .CK(clk), .RN(n4331), .Q(
DmP_mant_SFG_SWR[5]), .QN(n4111) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1152), .CK(clk), .RN(n4331), .Q(
DmP_mant_SFG_SWR[4]), .QN(n4112) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_50_ ( .D(n1106), .CK(clk), .RN(n4339), .Q(
DmP_mant_SFG_SWR[50]), .QN(n4159) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_49_ ( .D(n1107), .CK(clk), .RN(n4339), .Q(
DmP_mant_SFG_SWR[49]), .QN(n4173) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_48_ ( .D(n1108), .CK(clk), .RN(n4339), .Q(
DmP_mant_SFG_SWR[48]), .QN(n4052) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_55_ ( .D(n1291), .CK(clk), .RN(n4317), .Q(
DmP_EXP_EWSW[55]), .QN(n4247) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_54_ ( .D(n1292), .CK(clk), .RN(n4317), .Q(
DmP_EXP_EWSW[54]), .QN(n4212) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_46_ ( .D(n1110), .CK(clk), .RN(n4338), .Q(
DmP_mant_SFG_SWR[46]), .QN(n4051) );
XNOR2X1TS U1897 ( .A(n3883), .B(DmP_mant_SFG_SWR[54]), .Y(n2035) );
NAND2X1TS U1898 ( .A(n4047), .B(n1911), .Y(n3131) );
NOR2X1TS U1899 ( .A(n2548), .B(n1908), .Y(n2187) );
CLKBUFX2TS U1900 ( .A(n2237), .Y(n1908) );
NOR2X1TS U1901 ( .A(n2656), .B(n2377), .Y(n2739) );
NOR2X1TS U1902 ( .A(n2698), .B(n2362), .Y(n2689) );
CMPR32X2TS U1903 ( .A(DP_OP_15J2_122_2221_n35), .B(DMP_exp_NRM2_EW[7]), .C(
n2213), .CO(n2215), .S(n2224) );
NAND2X1TS U1904 ( .A(n2666), .B(n4158), .Y(n2698) );
NOR2X1TS U1905 ( .A(n2671), .B(Raw_mant_NRM_SWR[14]), .Y(n2666) );
CMPR32X2TS U1906 ( .A(n2211), .B(DMP_exp_NRM2_EW[5]), .C(n2210), .CO(n2209),
.S(n2230) );
CMPR32X2TS U1907 ( .A(n2207), .B(DMP_exp_NRM2_EW[4]), .C(n2206), .CO(n2210),
.S(n3902) );
NOR2X1TS U1908 ( .A(n2694), .B(n2357), .Y(n2734) );
INVX2TS U1909 ( .A(n2747), .Y(n2748) );
INVX2TS U1910 ( .A(n2751), .Y(n2753) );
INVX2TS U1911 ( .A(n2137), .Y(n2143) );
NOR2XLTS U1912 ( .A(Raw_mant_NRM_SWR[41]), .B(Raw_mant_NRM_SWR[36]), .Y(
n2354) );
NOR2XLTS U1913 ( .A(Raw_mant_NRM_SWR[40]), .B(Raw_mant_NRM_SWR[39]), .Y(
n2745) );
OAI21XLTS U1914 ( .A0(intDY_EWSW[50]), .A1(n4148), .B0(n2158), .Y(n2162) );
NOR2XLTS U1915 ( .A(n4143), .B(intDY_EWSW[45]), .Y(n2121) );
NOR2XLTS U1916 ( .A(DMP_SFG[13]), .B(DmP_mant_SFG_SWR[15]), .Y(n3420) );
NOR2XLTS U1917 ( .A(DMP_SFG[11]), .B(DmP_mant_SFG_SWR[13]), .Y(n3649) );
NOR2XLTS U1918 ( .A(DMP_SFG[5]), .B(DmP_mant_SFG_SWR[7]), .Y(n3374) );
NOR2XLTS U1919 ( .A(DMP_SFG[21]), .B(DmP_mant_SFG_SWR[23]), .Y(n3360) );
OAI21XLTS U1920 ( .A0(n3420), .A1(n3707), .B0(n3421), .Y(n3554) );
INVX2TS U1921 ( .A(n2172), .Y(n2148) );
OAI211XLTS U1922 ( .A0(intDY_EWSW[28]), .A1(n4136), .B0(n2591), .C0(n2046),
.Y(n2101) );
AOI211XLTS U1923 ( .A0(intDX_EWSW[52]), .A1(n4222), .B0(n2040), .C0(n2153),
.Y(n2155) );
INVX2TS U1924 ( .A(n2672), .Y(n2676) );
OAI21XLTS U1925 ( .A0(n1964), .A1(n3703), .B0(n1963), .Y(n3417) );
OAI21XLTS U1926 ( .A0(n3257), .A1(n2022), .B0(n2021), .Y(n3220) );
NOR2XLTS U1927 ( .A(DMP_SFG[15]), .B(DmP_mant_SFG_SWR[17]), .Y(n3586) );
OR2X1TS U1928 ( .A(LZD_output_NRM2_EW[0]), .B(ADD_OVRFLW_NRM2), .Y(n2198) );
NOR2XLTS U1929 ( .A(n2214), .B(n3906), .Y(n2216) );
INVX2TS U1930 ( .A(n2375), .Y(n2369) );
OAI21XLTS U1931 ( .A0(n3360), .A1(n3693), .B0(n3361), .Y(n3260) );
NOR2XLTS U1932 ( .A(DMP_SFG[8]), .B(DmP_mant_SFG_SWR[10]), .Y(n3606) );
INVX2TS U1933 ( .A(n2724), .Y(n2733) );
INVX2TS U1934 ( .A(n2690), .Y(n2715) );
NOR2XLTS U1935 ( .A(DMP_SFG[22]), .B(DmP_mant_SFG_SWR[24]), .Y(n3671) );
NOR2XLTS U1936 ( .A(n1910), .B(n1908), .Y(n3808) );
NAND2X1TS U1937 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[5]),
.Y(n3640) );
INVX2TS U1938 ( .A(n2656), .Y(n2645) );
NAND2X1TS U1939 ( .A(n2992), .B(Raw_mant_NRM_SWR[5]), .Y(n2819) );
NAND2X1TS U1940 ( .A(n3000), .B(Raw_mant_NRM_SWR[14]), .Y(n2878) );
NAND2X1TS U1941 ( .A(n2958), .B(Raw_mant_NRM_SWR[17]), .Y(n2959) );
NAND2X1TS U1942 ( .A(n3000), .B(Raw_mant_NRM_SWR[23]), .Y(n3001) );
NAND2X1TS U1943 ( .A(n2981), .B(Raw_mant_NRM_SWR[36]), .Y(n2982) );
INVX2TS U1944 ( .A(n2811), .Y(n2813) );
NAND2X1TS U1945 ( .A(n2689), .B(n2363), .Y(n2656) );
OAI21XLTS U1946 ( .A0(n3810), .A1(n2237), .B0(n2554), .Y(n3162) );
NOR2XLTS U1947 ( .A(n1911), .B(n4028), .Y(n3130) );
NAND2X1TS U1948 ( .A(n3792), .B(n3791), .Y(n3794) );
NOR2XLTS U1949 ( .A(n4187), .B(Shift_reg_FLAGS_7[0]), .Y(n2535) );
AOI211XLTS U1950 ( .A0(n2176), .A1(n2175), .B0(n2174), .C0(n2173), .Y(n2177)
);
NOR2XLTS U1951 ( .A(n1920), .B(n3205), .Y(n2381) );
NOR2XLTS U1952 ( .A(n2812), .B(n3090), .Y(n2980) );
INVX2TS U1953 ( .A(n2812), .Y(n2788) );
INVX2TS U1954 ( .A(n3172), .Y(n3185) );
NOR2XLTS U1955 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n4211), .Y(n3911) );
INVX2TS U1956 ( .A(n3157), .Y(n3168) );
AFHCINX2TS U1957 ( .CIN(n3527), .B(n4173), .A(DMP_SFG[47]), .S(n3531), .CO(
n3533) );
INVX2TS U1958 ( .A(n3130), .Y(n1899) );
INVX2TS U1959 ( .A(n3130), .Y(n1898) );
INVX2TS U1960 ( .A(n2223), .Y(n3907) );
INVX2TS U1961 ( .A(n2222), .Y(n3908) );
NOR2XLTS U1962 ( .A(n2551), .B(n2550), .Y(n3147) );
NAND2X1TS U1963 ( .A(n3197), .B(LZD_output_NRM2_EW[3]), .Y(n2708) );
INVX2TS U1964 ( .A(n2434), .Y(n2509) );
INVX2TS U1965 ( .A(n2434), .Y(n2513) );
INVX2TS U1966 ( .A(n2434), .Y(n2445) );
INVX2TS U1967 ( .A(n2635), .Y(n2518) );
INVX2TS U1968 ( .A(n1919), .Y(n1921) );
INVX2TS U1969 ( .A(n2434), .Y(n2644) );
OR2X1TS U1970 ( .A(n2177), .B(n4360), .Y(n2492) );
INVX2TS U1971 ( .A(n2825), .Y(n2929) );
OR2X1TS U1972 ( .A(n2811), .B(n2812), .Y(n1941) );
INVX2TS U1973 ( .A(n3877), .Y(n2792) );
INVX2TS U1974 ( .A(n3911), .Y(n3910) );
OAI211XLTS U1975 ( .A0(n3117), .A1(n3054), .B0(n3053), .C0(n3052), .Y(n1743)
);
OAI211XLTS U1976 ( .A0(n3006), .A1(n2906), .B0(n2905), .C0(n2904), .Y(n1749)
);
INVX2TS U1977 ( .A(n2443), .Y(n1294) );
OAI31X1TS U1978 ( .A0(n3966), .A1(n2633), .A2(n3997), .B0(n2632), .Y(n1610)
);
INVX2TS U1979 ( .A(n2450), .Y(n1623) );
INVX2TS U1980 ( .A(n2382), .Y(n1693) );
OAI211XLTS U1981 ( .A0(n3006), .A1(n2877), .B0(n2876), .C0(n2875), .Y(n1705)
);
OAI211XLTS U1982 ( .A0(n3117), .A1(n3029), .B0(n3028), .C0(n3027), .Y(n1718)
);
OAI211XLTS U1983 ( .A0(n3117), .A1(n3032), .B0(n3031), .C0(n3030), .Y(n1737)
);
OAI21X1TS U1984 ( .A0(n1958), .A1(n3603), .B0(n1957), .Y(n3435) );
OAI211X1TS U1985 ( .A0(n3117), .A1(n3041), .B0(n3040), .C0(n3039), .Y(n1740)
);
OAI211X1TS U1986 ( .A0(n3117), .A1(n3116), .B0(n3115), .C0(n3114), .Y(n1728)
);
OAI211X1TS U1987 ( .A0(n3006), .A1(n2937), .B0(n2936), .C0(n2935), .Y(n1708)
);
OAI211X1TS U1988 ( .A0(n3117), .A1(n2987), .B0(n2986), .C0(n2985), .Y(n1733)
);
OAI211X1TS U1989 ( .A0(n3006), .A1(n2853), .B0(n2852), .C0(n2851), .Y(n1746)
);
OAI211X1TS U1990 ( .A0(n3117), .A1(n2941), .B0(n2940), .C0(n2939), .Y(n1741)
);
OAI211X1TS U1991 ( .A0(n3006), .A1(n2848), .B0(n2847), .C0(n2846), .Y(n1745)
);
OAI211X1TS U1992 ( .A0(n3117), .A1(n3080), .B0(n3079), .C0(n3078), .Y(n1721)
);
OAI211X1TS U1993 ( .A0(n3006), .A1(n2843), .B0(n2842), .C0(n2841), .Y(n1744)
);
OAI211X1TS U1994 ( .A0(n3117), .A1(n3073), .B0(n3072), .C0(n3071), .Y(n1719)
);
OAI211X1TS U1995 ( .A0(n3117), .A1(n3013), .B0(n3012), .C0(n3011), .Y(n1709)
);
OAI211X1TS U1996 ( .A0(n3006), .A1(n2866), .B0(n2865), .C0(n2864), .Y(n1742)
);
OAI211X1TS U1997 ( .A0(n3006), .A1(n2975), .B0(n2974), .C0(n2973), .Y(n1713)
);
OAI211X1TS U1998 ( .A0(n3006), .A1(n3005), .B0(n3004), .C0(n3003), .Y(n1720)
);
OAI211X1TS U1999 ( .A0(n3006), .A1(n2859), .B0(n2858), .C0(n2857), .Y(n1748)
);
OAI211X1TS U2000 ( .A0(n3129), .A1(n2972), .B0(n2971), .C0(n2970), .Y(n1738)
);
OAI211X1TS U2001 ( .A0(n3129), .A1(n3022), .B0(n3021), .C0(n3020), .Y(n1734)
);
OAI211X1TS U2002 ( .A0(n3100), .A1(n2888), .B0(n2887), .C0(n2886), .Y(n1710)
);
OAI211X1TS U2003 ( .A0(n3100), .A1(n2963), .B0(n2962), .C0(n2961), .Y(n1714)
);
OAI211X1TS U2004 ( .A0(n3100), .A1(n3068), .B0(n3067), .C0(n3066), .Y(n1712)
);
OAI211X1TS U2005 ( .A0(n2929), .A1(n2928), .B0(n2927), .C0(n2926), .Y(n1703)
);
OAI211X1TS U2006 ( .A0(n3129), .A1(n3026), .B0(n3025), .C0(n3024), .Y(n1730)
);
OAI211X1TS U2007 ( .A0(n2929), .A1(n2915), .B0(n2914), .C0(n2913), .Y(n1704)
);
OAI211X1TS U2008 ( .A0(n3129), .A1(n3047), .B0(n3046), .C0(n3045), .Y(n1747)
);
OAI211X1TS U2009 ( .A0(n3129), .A1(n3106), .B0(n3105), .C0(n3104), .Y(n1731)
);
OAI211X1TS U2010 ( .A0(n3100), .A1(n3038), .B0(n3037), .C0(n3036), .Y(n1715)
);
OAI211X1TS U2011 ( .A0(n3100), .A1(n2953), .B0(n2952), .C0(n2951), .Y(n1717)
);
OAI211X1TS U2012 ( .A0(n2929), .A1(n2911), .B0(n2910), .C0(n2909), .Y(n1701)
);
OAI211X1TS U2013 ( .A0(n3100), .A1(n2903), .B0(n2902), .C0(n2901), .Y(n1706)
);
OAI211X1TS U2014 ( .A0(n3129), .A1(n3035), .B0(n3034), .C0(n3033), .Y(n1736)
);
OAI211X1TS U2015 ( .A0(n3100), .A1(n3099), .B0(n3098), .C0(n3097), .Y(n1735)
);
OAI211X1TS U2016 ( .A0(n3129), .A1(n3128), .B0(n3127), .C0(n3126), .Y(n1739)
);
OAI211X1TS U2017 ( .A0(n3100), .A1(n2894), .B0(n2893), .C0(n2892), .Y(n1707)
);
OAI211X1TS U2018 ( .A0(n3129), .A1(n3016), .B0(n3015), .C0(n3014), .Y(n1732)
);
OAI211X1TS U2019 ( .A0(n3129), .A1(n3084), .B0(n3083), .C0(n3082), .Y(n1726)
);
OAI211X1TS U2020 ( .A0(n3100), .A1(n2900), .B0(n2899), .C0(n2898), .Y(n1711)
);
OAI211X1TS U2021 ( .A0(n3100), .A1(n3060), .B0(n3059), .C0(n3058), .Y(n1716)
);
OAI211X1TS U2022 ( .A0(n3129), .A1(n2997), .B0(n2996), .C0(n2995), .Y(n1729)
);
CLKBUFX2TS U2023 ( .A(n2825), .Y(n3897) );
INVX2TS U2024 ( .A(n2825), .Y(n3129) );
OAI2BB1X1TS U2025 ( .A0N(n4238), .A1N(DMP_SFG[51]), .B0(n2001), .Y(n2002) );
NAND2X1TS U2026 ( .A(n2798), .B(n3153), .Y(n2811) );
OR2X2TS U2027 ( .A(n3090), .B(n2788), .Y(n1942) );
OAI21X1TS U2028 ( .A0(n2738), .A1(n2957), .B0(n2737), .Y(n1211) );
AND2X2TS U2029 ( .A(n3888), .B(n2787), .Y(n2812) );
OAI21X1TS U2030 ( .A0(n2786), .A1(n2785), .B0(n1920), .Y(n3888) );
NAND3X1TS U2031 ( .A(n2766), .B(n2765), .C(n2764), .Y(n3887) );
NAND3X1TS U2032 ( .A(n2784), .B(n2783), .C(n2782), .Y(n2785) );
INVX1TS U2033 ( .A(n2739), .Y(n2744) );
INVX1TS U2034 ( .A(n2689), .Y(n2703) );
NAND3BX1TS U2035 ( .AN(n2669), .B(n2668), .C(n2667), .Y(n2670) );
INVX1TS U2036 ( .A(n2698), .Y(n2700) );
OAI22X2TS U2037 ( .A0(n3483), .A1(n2033), .B0(DmP_mant_SFG_SWR[46]), .B1(
DMP_SFG[44]), .Y(n3489) );
NAND2XLTS U2038 ( .A(n2366), .B(n2667), .Y(n2367) );
NAND2XLTS U2039 ( .A(n2666), .B(Raw_mant_NRM_SWR[13]), .Y(n2667) );
OAI21XLTS U2040 ( .A0(n3138), .A1(n1906), .B0(n2236), .Y(n1161) );
NAND2X1TS U2041 ( .A(n2763), .B(n2361), .Y(n2671) );
OAI21XLTS U2042 ( .A0(n3173), .A1(n1906), .B0(n2294), .Y(n1159) );
OAI21XLTS U2043 ( .A0(n3182), .A1(n1906), .B0(n2265), .Y(n1170) );
OAI21X1TS U2044 ( .A0(n2696), .A1(Raw_mant_NRM_SWR[20]), .B0(n2665), .Y(
n2669) );
OAI21XLTS U2045 ( .A0(n3179), .A1(n3131), .B0(n2325), .Y(n1201) );
OAI21XLTS U2046 ( .A0(n3176), .A1(n3131), .B0(n2271), .Y(n1192) );
OAI21XLTS U2047 ( .A0(n3188), .A1(n3131), .B0(n2251), .Y(n1174) );
OAI21XLTS U2048 ( .A0(n3163), .A1(n3131), .B0(n2311), .Y(n1205) );
OAI21XLTS U2049 ( .A0(n3171), .A1(n3131), .B0(n2348), .Y(n1172) );
OAI21XLTS U2050 ( .A0(n3165), .A1(n3131), .B0(n2319), .Y(n1207) );
OAI21XLTS U2051 ( .A0(n3195), .A1(n3131), .B0(n2340), .Y(n1176) );
NOR2X1TS U2052 ( .A(n2769), .B(Raw_mant_NRM_SWR[17]), .Y(n2763) );
INVX1TS U2053 ( .A(n2769), .Y(n2781) );
NAND2X1TS U2054 ( .A(n2365), .B(n4125), .Y(n2769) );
NOR2X1TS U2055 ( .A(n2646), .B(n2360), .Y(n2365) );
NOR2X1TS U2056 ( .A(n2652), .B(n2651), .Y(n2736) );
INVX1TS U2057 ( .A(n2646), .Y(n2657) );
INVX1TS U2058 ( .A(n4028), .Y(n4045) );
NOR2X1TS U2059 ( .A(n2664), .B(n2663), .Y(n2665) );
NOR2X1TS U2060 ( .A(n2690), .B(n2358), .Y(n2679) );
INVX1TS U2061 ( .A(n2718), .Y(n2664) );
NAND3X1TS U2062 ( .A(n2686), .B(n2755), .C(n2724), .Y(n2687) );
OAI21X1TS U2063 ( .A0(n2761), .A1(Raw_mant_NRM_SWR[29]), .B0(n2760), .Y(
n2762) );
OAI21X1TS U2064 ( .A0(n2662), .A1(n4142), .B0(n2661), .Y(n2663) );
OAI31XLTS U2065 ( .A0(Raw_mant_NRM_SWR[27]), .A1(n2694), .A2(n4227), .B0(
n2693), .Y(n2697) );
NOR3X1TS U2066 ( .A(n3908), .B(n3907), .C(n2233), .Y(n2235) );
NAND2X1TS U2067 ( .A(n2673), .B(n2356), .Y(n2694) );
NAND2XLTS U2068 ( .A(n2673), .B(Raw_mant_NRM_SWR[28]), .Y(n2761) );
NOR2X1TS U2069 ( .A(n2731), .B(Raw_mant_NRM_SWR[30]), .Y(n2673) );
NAND2X1TS U2070 ( .A(n2658), .B(n4117), .Y(n2731) );
NAND3BX1TS U2071 ( .AN(n3905), .B(n3906), .C(n2232), .Y(n2233) );
INVX1TS U2072 ( .A(n3158), .Y(n3170) );
NOR2X1TS U2073 ( .A(n2660), .B(n2355), .Y(n2658) );
NAND2BX1TS U2074 ( .AN(n2250), .B(n2249), .Y(n3186) );
INVX1TS U2075 ( .A(n2660), .Y(n2714) );
INVX1TS U2076 ( .A(n2635), .Y(n2522) );
INVX1TS U2077 ( .A(n2224), .Y(n3905) );
AND2X2TS U2078 ( .A(Shift_reg_FLAGS_7_6), .B(n2177), .Y(n2635) );
NOR2X1TS U2079 ( .A(n2778), .B(Raw_mant_NRM_SWR[35]), .Y(n2728) );
OAI21X1TS U2080 ( .A0(n2778), .A1(n4178), .B0(n2777), .Y(n2779) );
INVX1TS U2081 ( .A(n2710), .Y(n2712) );
NAND2XLTS U2082 ( .A(n2992), .B(Raw_mant_NRM_SWR[20]), .Y(n2946) );
NAND2XLTS U2083 ( .A(n2889), .B(Raw_mant_NRM_SWR[24]), .Y(n2805) );
OAI211X1TS U2084 ( .A0(n2549), .A1(n2270), .B0(n2269), .C0(n3751), .Y(n3155)
);
NOR2X1TS U2085 ( .A(n2776), .B(n2725), .Y(n2710) );
NAND2XLTS U2086 ( .A(n2992), .B(Raw_mant_NRM_SWR[40]), .Y(n2968) );
NAND2XLTS U2087 ( .A(n2981), .B(Raw_mant_NRM_SWR[37]), .Y(n2976) );
NAND2XLTS U2088 ( .A(n2981), .B(Raw_mant_NRM_SWR[38]), .Y(n2978) );
NOR2X1TS U2089 ( .A(n2767), .B(n2923), .Y(n2768) );
NAND2XLTS U2090 ( .A(n2981), .B(Raw_mant_NRM_SWR[41]), .Y(n2966) );
NAND2XLTS U2091 ( .A(n2981), .B(Raw_mant_NRM_SWR[6]), .Y(n2907) );
NAND2XLTS U2092 ( .A(n2981), .B(Raw_mant_NRM_SWR[19]), .Y(n2949) );
AOI211X1TS U2093 ( .A0(n2591), .A1(n2054), .B0(n2053), .C0(n2052), .Y(n2106)
);
NAND2XLTS U2094 ( .A(n2948), .B(Raw_mant_NRM_SWR[2]), .Y(n2855) );
NAND3X1TS U2095 ( .A(n2330), .B(n2307), .C(n2306), .Y(n3736) );
NOR2X1TS U2096 ( .A(n2648), .B(Raw_mant_NRM_SWR[42]), .Y(n2759) );
OAI21X1TS U2097 ( .A0(n2270), .A1(n2237), .B0(n2554), .Y(n3136) );
NAND3X1TS U2098 ( .A(n2259), .B(n2258), .C(n2257), .Y(n3852) );
NAND3X1TS U2099 ( .A(n2278), .B(n2277), .C(n2276), .Y(n3849) );
NAND4X1TS U2100 ( .A(n2128), .B(n2126), .C(n2039), .D(n2038), .Y(n2170) );
NAND3X1TS U2101 ( .A(n2155), .B(n2164), .C(n2042), .Y(n2172) );
OAI21X1TS U2102 ( .A0(n3286), .A1(n1956), .B0(n1955), .Y(n3400) );
NAND2X1TS U2103 ( .A(n2353), .B(n2771), .Y(n2648) );
OAI21X1TS U2104 ( .A0(n2754), .A1(n2753), .B0(n2752), .Y(n2756) );
INVX1TS U2105 ( .A(n3847), .Y(n2554) );
AOI211X1TS U2106 ( .A0(intDX_EWSW[44]), .A1(n4195), .B0(n2121), .C0(n2130),
.Y(n2128) );
INVX1TS U2107 ( .A(n2155), .Y(n2161) );
NAND2BX1TS U2108 ( .AN(n3847), .B(n2237), .Y(n2343) );
AND2X2TS U2109 ( .A(beg_OP), .B(n3916), .Y(n3937) );
NOR2X1TS U2110 ( .A(n2675), .B(n2672), .Y(n2771) );
INVX1TS U2111 ( .A(n2796), .Y(n2767) );
OAI211X1TS U2112 ( .A0(intDY_EWSW[36]), .A1(n4131), .B0(n2146), .C0(n2135),
.Y(n2137) );
OAI211X1TS U2113 ( .A0(intDY_EWSW[60]), .A1(n4220), .B0(n2117), .C0(n2113),
.Y(n2119) );
OAI21X1TS U2114 ( .A0(intDY_EWSW[58]), .A1(n4219), .B0(n2109), .Y(n2111) );
NOR2X1TS U2115 ( .A(n2370), .B(Raw_mant_NRM_SWR[9]), .Y(n2363) );
XOR2X1TS U2116 ( .A(n1904), .B(n2195), .Y(n2200) );
XOR2X1TS U2117 ( .A(n1904), .B(n2196), .Y(n2203) );
INVX1TS U2118 ( .A(n2256), .Y(n2314) );
NAND2XLTS U2119 ( .A(n3197), .B(LZD_output_NRM2_EW[2]), .Y(n2682) );
NAND2XLTS U2120 ( .A(n3197), .B(LZD_output_NRM2_EW[4]), .Y(n2737) );
INVX1TS U2121 ( .A(n4003), .Y(n4004) );
NAND2BX1TS U2122 ( .AN(intDY_EWSW[62]), .B(intDX_EWSW[62]), .Y(n2117) );
NAND2BX1TS U2123 ( .AN(intDY_EWSW[59]), .B(intDX_EWSW[59]), .Y(n2109) );
NOR2X1TS U2124 ( .A(n4149), .B(intDY_EWSW[57]), .Y(n2107) );
NOR2X1TS U2125 ( .A(n4223), .B(intDY_EWSW[49]), .Y(n2156) );
NOR2X1TS U2126 ( .A(Raw_mant_NRM_SWR[50]), .B(Raw_mant_NRM_SWR[49]), .Y(
n2747) );
NAND2BX1TS U2127 ( .AN(intDY_EWSW[51]), .B(intDX_EWSW[51]), .Y(n2158) );
NOR2X1TS U2128 ( .A(n4053), .B(Raw_mant_NRM_SWR[2]), .Y(n2379) );
OR2X2TS U2129 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[24]), .Y(n2358) );
NOR2X1TS U2130 ( .A(Raw_mant_NRM_SWR[12]), .B(Raw_mant_NRM_SWR[11]), .Y(
n2699) );
NOR2X1TS U2131 ( .A(Raw_mant_NRM_SWR[22]), .B(Raw_mant_NRM_SWR[21]), .Y(
n2359) );
OR2X2TS U2132 ( .A(Raw_mant_NRM_SWR[20]), .B(Raw_mant_NRM_SWR[19]), .Y(n2360) );
NOR2X1TS U2133 ( .A(Raw_mant_NRM_SWR[16]), .B(Raw_mant_NRM_SWR[15]), .Y(
n2361) );
NOR2X1TS U2134 ( .A(Raw_mant_NRM_SWR[52]), .B(Raw_mant_NRM_SWR[51]), .Y(
n2751) );
NOR2X1TS U2135 ( .A(Raw_mant_NRM_SWR[54]), .B(Raw_mant_NRM_SWR[53]), .Y(
n2752) );
NOR2X1TS U2136 ( .A(Raw_mant_NRM_SWR[29]), .B(Raw_mant_NRM_SWR[28]), .Y(
n2356) );
CLKAND2X2TS U2137 ( .A(DmP_mant_SFG_SWR[32]), .B(DMP_SFG[30]), .Y(n2027) );
NOR2X1TS U2138 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[3]), .Y(n2376)
);
NOR2X1TS U2139 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .Y(n2375)
);
CLKAND2X2TS U2140 ( .A(DmP_mant_SFG_SWR[42]), .B(DMP_SFG[40]), .Y(n2031) );
OR2X2TS U2141 ( .A(Raw_mant_NRM_SWR[26]), .B(Raw_mant_NRM_SWR[27]), .Y(n2357) );
CLKAND2X2TS U2142 ( .A(DmP_mant_SFG_SWR[36]), .B(DMP_SFG[34]), .Y(n2029) );
OR2X4TS U2143 ( .A(n4010), .B(n4012), .Y(n4028) );
NOR2X1TS U2144 ( .A(n3245), .B(n1987), .Y(n3209) );
AFHCINX4TS U2145 ( .CIN(n3463), .B(n4269), .A(DMP_SFG[41]), .S(n3467), .CO(
n3469) );
OAI22X2TS U2146 ( .A0(n3505), .A1(n1997), .B0(n4266), .B1(DMP_SFG[26]), .Y(
n3510) );
OAI22X2TS U2147 ( .A0(n3469), .A1(n1998), .B0(n4264), .B1(DMP_SFG[42]), .Y(
n3476) );
AFHCINX4TS U2148 ( .CIN(n3341), .B(n4116), .A(DMP_SFG[31]), .S(n3345), .CO(
n3826) );
OAI2BB1X2TS U2149 ( .A0N(n3526), .A1N(n2037), .B0(n2036), .Y(n1215) );
AFHCINX4TS U2150 ( .CIN(n3319), .B(n4128), .A(DMP_SFG[39]), .S(n3323), .CO(
n3663) );
AFHCINX4TS U2151 ( .CIN(n3227), .B(n4271), .A(DMP_SFG[29]), .S(n3231), .CO(
n3335) );
AFHCINX4TS U2152 ( .CIN(n3330), .B(n4270), .A(DMP_SFG[33]), .S(n3334), .CO(
n3324) );
OAI2BB2X2TS U2153 ( .B0(n3540), .B1(n2034), .A0N(n1939), .A1N(n4052), .Y(
n3528) );
AFHCINX4TS U2154 ( .CIN(n3577), .B(n4123), .A(DMP_SFG[35]), .S(n3581), .CO(
n3596) );
AFHCINX4TS U2155 ( .CIN(n3487), .B(n4267), .A(DMP_SFG[45]), .S(n3493), .CO(
n3538) );
OAI21X1TS U2156 ( .A0(n3313), .A1(n1944), .B0(n1943), .Y(n3266) );
NAND2X1TS U2157 ( .A(n2734), .B(n4118), .Y(n2690) );
NOR2XLTS U2158 ( .A(n3769), .B(n3763), .Y(n2018) );
OAI21XLTS U2159 ( .A0(n1977), .A1(n3348), .B0(n1976), .Y(n1978) );
OAI211XLTS U2160 ( .A0(intDY_EWSW[12]), .A1(n4138), .B0(n2607), .C0(n2056),
.Y(n2084) );
NAND2BXLTS U2161 ( .AN(intDY_EWSW[13]), .B(intDX_EWSW[13]), .Y(n2056) );
OR2X1TS U2162 ( .A(n4251), .B(DMP_SFG[24]), .Y(n1990) );
OAI21XLTS U2163 ( .A0(n3763), .A1(n3768), .B0(n3764), .Y(n2017) );
OR2X1TS U2164 ( .A(Raw_mant_NRM_SWR[33]), .B(Raw_mant_NRM_SWR[32]), .Y(n2355) );
NAND2X1TS U2165 ( .A(n2710), .B(n2354), .Y(n2778) );
NOR2XLTS U2166 ( .A(n4099), .B(DMP_SFG[25]), .Y(n1992) );
OAI21XLTS U2167 ( .A0(n1983), .A1(n3251), .B0(n1982), .Y(n1984) );
NOR2XLTS U2168 ( .A(n3426), .B(n2014), .Y(n2016) );
XOR2XLTS U2169 ( .A(DP_OP_15J2_122_2221_n35), .B(n2193), .Y(n2211) );
AND3X1TS U2170 ( .A(n2227), .B(n2226), .C(n2225), .Y(n2228) );
NAND4BXLTS U2171 ( .AN(n2224), .B(n2212), .C(n3904), .D(n3903), .Y(n2214) );
NOR2XLTS U2172 ( .A(n2208), .B(n3902), .Y(n2212) );
NAND4BXLTS U2173 ( .AN(n3901), .B(n3898), .C(n3900), .D(n3899), .Y(n2208) );
NAND2X1TS U2174 ( .A(n3887), .B(n2948), .Y(n2797) );
CLKAND2X2TS U2175 ( .A(n2723), .B(n2722), .Y(n2766) );
NOR2XLTS U2176 ( .A(n2721), .B(n2720), .Y(n2722) );
NAND4XLTS U2177 ( .A(n2719), .B(n2718), .C(n2717), .D(n2716), .Y(n2721) );
AOI2BB2XLTS U2178 ( .B0(n2714), .B1(n2713), .A0N(n2712), .A1N(n2711), .Y(
n2717) );
NAND3BXLTS U2179 ( .AN(Raw_mant_NRM_SWR[24]), .B(n2734), .C(
Raw_mant_NRM_SWR[23]), .Y(n2686) );
AFHCINX2TS U2180 ( .CIN(n3477), .B(DMP_SFG[43]), .A(DmP_mant_SFG_SWR[45]),
.S(n3478), .CO(n3483) );
CLKAND2X2TS U2181 ( .A(DmP_mant_SFG_SWR[44]), .B(DMP_SFG[42]), .Y(n2032) );
NAND2BXLTS U2182 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n2073) );
NAND3XLTS U2183 ( .A(n4147), .B(n2071), .C(intDY_EWSW[8]), .Y(n2072) );
NOR2XLTS U2184 ( .A(intDX_EWSW[10]), .B(n2069), .Y(n2070) );
NOR2XLTS U2185 ( .A(n3452), .B(n3649), .Y(n2010) );
OAI21XLTS U2186 ( .A0(intDY_EWSW[46]), .A1(n4135), .B0(n2120), .Y(n2130) );
NAND2BXLTS U2187 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2120) );
NOR2XLTS U2188 ( .A(n2088), .B(intDX_EWSW[16]), .Y(n2089) );
NAND2BXLTS U2189 ( .AN(intDY_EWSW[29]), .B(intDX_EWSW[29]), .Y(n2046) );
OAI21XLTS U2190 ( .A0(intDY_EWSW[26]), .A1(n4075), .B0(n2048), .Y(n2102) );
NAND3BXLTS U2191 ( .AN(n2093), .B(n2086), .C(n2085), .Y(n2105) );
NAND2X1TS U2192 ( .A(n2679), .B(n2359), .Y(n2646) );
NAND2X1TS U2193 ( .A(n2728), .B(n4115), .Y(n2660) );
NOR2XLTS U2194 ( .A(n4107), .B(DMP_SFG[12]), .Y(n1964) );
NOR2XLTS U2195 ( .A(n4259), .B(DMP_SFG[6]), .Y(n1952) );
NOR2XLTS U2196 ( .A(n3549), .B(n3586), .Y(n2012) );
OAI21XLTS U2197 ( .A0(n1960), .A1(n3448), .B0(n1959), .Y(n1961) );
NOR2XLTS U2198 ( .A(n4100), .B(DMP_SFG[20]), .Y(n1981) );
NOR2XLTS U2199 ( .A(n4103), .B(DMP_SFG[16]), .Y(n1975) );
NOR2XLTS U2200 ( .A(DMP_SFG[12]), .B(DmP_mant_SFG_SWR[14]), .Y(n3427) );
NOR2XLTS U2201 ( .A(n4257), .B(DMP_SFG[8]), .Y(n1958) );
NOR2XLTS U2202 ( .A(n4260), .B(DMP_SFG[5]), .Y(n3387) );
NOR2XLTS U2203 ( .A(n3606), .B(n3438), .Y(n3455) );
NOR2XLTS U2204 ( .A(n4108), .B(DMP_SFG[11]), .Y(n3702) );
NOR2XLTS U2205 ( .A(n3406), .B(n3401), .Y(n2006) );
OAI21XLTS U2206 ( .A0(n3673), .A1(n3670), .B0(n3674), .Y(n2019) );
NOR2XLTS U2207 ( .A(n4252), .B(DMP_SFG[23]), .Y(n3717) );
XOR2XLTS U2208 ( .A(n1904), .B(n2197), .Y(n2205) );
AOI2BB1XLTS U2209 ( .A0N(n2776), .A1N(n2775), .B0(n2774), .Y(n2777) );
OAI21XLTS U2210 ( .A0(Raw_mant_NRM_SWR[54]), .A1(n2773), .B0(n2772), .Y(
n2774) );
NOR2XLTS U2211 ( .A(DMP_SFG[24]), .B(DmP_mant_SFG_SWR[26]), .Y(n3719) );
NOR2XLTS U2212 ( .A(n3692), .B(n3360), .Y(n3261) );
NOR2XLTS U2213 ( .A(n4254), .B(DMP_SFG[21]), .Y(n3252) );
NOR2XLTS U2214 ( .A(n3427), .B(n3420), .Y(n3553) );
NOR2XLTS U2215 ( .A(n2369), .B(n2376), .Y(n2374) );
NAND3XLTS U2216 ( .A(n2666), .B(Raw_mant_NRM_SWR[11]), .C(n4177), .Y(n2668)
);
OAI211XLTS U2217 ( .A0(n3846), .A1(n3796), .B0(n2531), .C0(n2530), .Y(n2532)
);
NOR2XLTS U2218 ( .A(n3210), .B(n1992), .Y(n1994) );
AOI2BB1XLTS U2219 ( .A0N(n3817), .A1N(n3796), .B0(n2293), .Y(n3173) );
NAND3BXLTS U2220 ( .AN(n2292), .B(n2291), .C(n2290), .Y(n2293) );
OAI211XLTS U2221 ( .A0(n3640), .A1(n2270), .B0(n2191), .C0(n2190), .Y(n2192)
);
NAND4XLTS U2222 ( .A(n2283), .B(n2282), .C(n2281), .D(n3751), .Y(n3157) );
AOI2BB2XLTS U2223 ( .B0(n1932), .B1(n3849), .A0N(n2320), .A1N(n1903), .Y(
n2281) );
NAND4XLTS U2224 ( .A(n2264), .B(n2263), .C(n2262), .D(n3751), .Y(n3172) );
AOI2BB2XLTS U2225 ( .B0(n1932), .B1(n3852), .A0N(n2295), .A1N(n1903), .Y(
n2262) );
NAND4XLTS U2226 ( .A(n2347), .B(n2346), .C(n2345), .D(n3751), .Y(n3158) );
AOI2BB2XLTS U2227 ( .B0(n1932), .B1(n3856), .A0N(n2344), .A1N(n1903), .Y(
n2345) );
AOI2BB2XLTS U2228 ( .B0(n1932), .B1(n3859), .A0N(n2312), .A1N(n1903), .Y(
n2249) );
OAI21XLTS U2229 ( .A0(n4242), .A1(n1895), .B0(n2244), .Y(n2250) );
OAI211XLTS U2230 ( .A0(n4236), .A1(n2333), .B0(n3751), .C0(n2332), .Y(n2334)
);
XOR2XLTS U2231 ( .A(DP_OP_15J2_122_2221_n35), .B(n2194), .Y(n2207) );
OAI211XLTS U2232 ( .A0(n3825), .A1(n3796), .B0(n2543), .C0(n2542), .Y(n2551)
);
OAI2BB1X2TS U2233 ( .A0N(n4263), .A1N(DMP_SFG[50]), .B0(n2000), .Y(n2407) );
CLKAND2X2TS U2234 ( .A(DmP_mant_SFG_SWR[46]), .B(DMP_SFG[44]), .Y(n2033) );
AFHCINX2TS U2235 ( .CIN(n3578), .B(DMP_SFG[35]), .A(DmP_mant_SFG_SWR[37]),
.S(n3579), .CO(n3598) );
OAI2BB2X2TS U2236 ( .B0(n3326), .B1(n2029), .A0N(n1936), .A1N(n4050), .Y(
n3578) );
MXI2XLTS U2237 ( .A(n2804), .B(n3076), .S0(n2812), .Y(n3091) );
MXI2XLTS U2238 ( .A(n3087), .B(n2804), .S0(n2812), .Y(n2933) );
NAND4BXLTS U2239 ( .AN(n2736), .B(n2766), .C(n2735), .D(n2784), .Y(n2740) );
NOR4BXLTS U2240 ( .AN(n2783), .B(n2706), .C(n2705), .D(n2704), .Y(n2709) );
OAI211XLTS U2241 ( .A0(n4249), .A1(n2703), .B0(n2702), .C0(n2701), .Y(n2706)
);
NAND3XLTS U2242 ( .A(n2700), .B(n2699), .C(Raw_mant_NRM_SWR[10]), .Y(n2701)
);
AOI22X1TS U2243 ( .A0(n2035), .A1(n3830), .B0(Raw_mant_NRM_SWR[54]), .B1(
n3829), .Y(n2036) );
NOR2XLTS U2244 ( .A(n4145), .B(intDY_EWSW[11]), .Y(n2069) );
OAI211XLTS U2245 ( .A0(n4121), .A1(intDY_EWSW[3]), .B0(n2061), .C0(n2060),
.Y(n2064) );
NAND2BXLTS U2246 ( .AN(intDY_EWSW[19]), .B(intDX_EWSW[19]), .Y(n2090) );
NAND2BXLTS U2247 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n2048) );
NOR2XLTS U2248 ( .A(n4146), .B(intDY_EWSW[17]), .Y(n2088) );
NAND2BXLTS U2249 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n2071) );
AOI211XLTS U2250 ( .A0(n2607), .A1(n2080), .B0(n2079), .C0(n2078), .Y(n2081)
);
OAI211XLTS U2251 ( .A0(intDY_EWSW[20]), .A1(n4137), .B0(n2599), .C0(n2055),
.Y(n2093) );
NAND2BXLTS U2252 ( .AN(intDY_EWSW[21]), .B(intDX_EWSW[21]), .Y(n2055) );
OAI21XLTS U2253 ( .A0(intDY_EWSW[18]), .A1(n4074), .B0(n2090), .Y(n2094) );
NOR2XLTS U2254 ( .A(n4109), .B(DMP_SFG[10]), .Y(n1960) );
NOR2XLTS U2255 ( .A(n3447), .B(n1960), .Y(n1962) );
NAND3XLTS U2256 ( .A(n4131), .B(n2135), .C(intDY_EWSW[36]), .Y(n2136) );
AOI2BB2XLTS U2257 ( .B0(intDY_EWSW[53]), .B1(n4244), .A0N(intDX_EWSW[52]),
.A1N(n2152), .Y(n2154) );
NOR2XLTS U2258 ( .A(n4253), .B(DMP_SFG[22]), .Y(n1983) );
NOR2XLTS U2259 ( .A(n3252), .B(n1983), .Y(n1985) );
OAI21XLTS U2260 ( .A0(n3586), .A1(n3582), .B0(n3587), .Y(n2011) );
OAI21XLTS U2261 ( .A0(n3649), .A1(n3654), .B0(n3650), .Y(n2009) );
OAI21XLTS U2262 ( .A0(n3374), .A1(n3378), .B0(n3375), .Y(n3392) );
OAI21XLTS U2263 ( .A0(n3401), .A1(n3405), .B0(n3402), .Y(n2005) );
NOR2XLTS U2264 ( .A(n3303), .B(n3374), .Y(n3393) );
NOR2XLTS U2265 ( .A(DMP_SFG[10]), .B(DmP_mant_SFG_SWR[12]), .Y(n3452) );
NOR2XLTS U2266 ( .A(n3671), .B(n3673), .Y(n2020) );
NOR2XLTS U2267 ( .A(DMP_SFG[4]), .B(DmP_mant_SFG_SWR[6]), .Y(n3303) );
NOR2XLTS U2268 ( .A(n3544), .B(n1966), .Y(n1968) );
NAND3XLTS U2269 ( .A(n2771), .B(Raw_mant_NRM_SWR[45]), .C(n4188), .Y(n2772)
);
NOR2XLTS U2270 ( .A(DMP_SFG[16]), .B(DmP_mant_SFG_SWR[18]), .Y(n3238) );
NOR2XLTS U2271 ( .A(DMP_SFG[14]), .B(DmP_mant_SFG_SWR[16]), .Y(n3549) );
OAI21XLTS U2272 ( .A0(n2131), .A1(n2130), .B0(n2129), .Y(n2133) );
NAND2BXLTS U2273 ( .AN(intDY_EWSW[41]), .B(intDX_EWSW[41]), .Y(n2039) );
NAND2BXLTS U2274 ( .AN(intDY_EWSW[40]), .B(intDX_EWSW[40]), .Y(n2038) );
NAND2BXLTS U2275 ( .AN(intDY_EWSW[32]), .B(intDX_EWSW[32]), .Y(n2043) );
NAND2BXLTS U2276 ( .AN(intDX_EWSW[62]), .B(intDY_EWSW[62]), .Y(n2115) );
NAND3XLTS U2277 ( .A(n4220), .B(n2113), .C(intDY_EWSW[60]), .Y(n2114) );
AOI211XLTS U2278 ( .A0(n2599), .A1(n2098), .B0(n2097), .C0(n2096), .Y(n2104)
);
AOI2BB2XLTS U2279 ( .B0(n2763), .B1(Raw_mant_NRM_SWR[15]), .A0N(n2698),
.A1N(n2699), .Y(n2371) );
NOR2XLTS U2280 ( .A(n4180), .B(Raw_mant_NRM_SWR[33]), .Y(n2713) );
OR2X1TS U2281 ( .A(Raw_mant_NRM_SWR[38]), .B(Raw_mant_NRM_SWR[37]), .Y(n2725) );
NAND2X1TS U2282 ( .A(n2759), .B(n2745), .Y(n2776) );
NOR2XLTS U2283 ( .A(n4101), .B(DMP_SFG[19]), .Y(n3690) );
NOR2XLTS U2284 ( .A(n3719), .B(n3214), .Y(n2024) );
OAI21XLTS U2285 ( .A0(n3211), .A1(n1992), .B0(n1991), .Y(n1993) );
NOR2XLTS U2286 ( .A(DMP_SFG[7]), .B(DmP_mant_SFG_SWR[9]), .Y(n3401) );
NOR2XLTS U2287 ( .A(n3387), .B(n1952), .Y(n1954) );
NOR2XLTS U2288 ( .A(n4104), .B(DMP_SFG[15]), .Y(n3563) );
NOR2XLTS U2289 ( .A(n4256), .B(DMP_SFG[9]), .Y(n3447) );
NOR2XLTS U2290 ( .A(n4258), .B(DMP_SFG[7]), .Y(n3604) );
OAI21XLTS U2291 ( .A0(n3605), .A1(n3415), .B0(n3414), .Y(n3706) );
NOR2XLTS U2292 ( .A(n3299), .B(n1950), .Y(n3372) );
OAI21XLTS U2293 ( .A0(n3287), .A1(n3291), .B0(n3288), .Y(n2003) );
NOR2XLTS U2294 ( .A(n3292), .B(n3287), .Y(n2004) );
NAND3BXLTS U2295 ( .AN(n2273), .B(n2544), .C(n2272), .Y(n3749) );
OAI21XLTS U2296 ( .A0(n4231), .A1(n2327), .B0(n2260), .Y(n2261) );
OAI21XLTS U2297 ( .A0(n4230), .A1(n2327), .B0(n2303), .Y(n2304) );
OAI211XLTS U2298 ( .A0(n3640), .A1(n3818), .B0(n3628), .C0(n3627), .Y(n3629)
);
OAI211XLTS U2299 ( .A0(n3640), .A1(n3837), .B0(n3639), .C0(n3638), .Y(n3641)
);
OAI211XLTS U2300 ( .A0(n2326), .A1(n4093), .B0(n2246), .C0(n2245), .Y(n3859)
);
NAND4XLTS U2301 ( .A(n3734), .B(n3733), .C(n3732), .D(n3751), .Y(n3858) );
NAND4XLTS U2302 ( .A(n3740), .B(n3739), .C(n3738), .D(n3751), .Y(n3855) );
NAND4XLTS U2303 ( .A(n3746), .B(n3745), .C(n3744), .D(n3751), .Y(n3851) );
NAND4XLTS U2304 ( .A(n3754), .B(n3753), .C(n3752), .D(n3751), .Y(n3848) );
OAI21XLTS U2305 ( .A0(n4234), .A1(n2327), .B0(n2285), .Y(n2286) );
AOI2BB1XLTS U2306 ( .A0N(n2548), .A1N(n4235), .B0(n2289), .Y(n3811) );
OAI21XLTS U2307 ( .A0(Data_array_SWR[52]), .A1(n2553), .B0(n2552), .Y(n3810)
);
OAI21XLTS U2308 ( .A0(shift_value_SHT2_EWR[4]), .A1(n1910), .B0(n3798), .Y(
n3835) );
AOI2BB1XLTS U2309 ( .A0N(n2548), .A1N(n4237), .B0(n2527), .Y(n3839) );
OAI21XLTS U2310 ( .A0(Data_array_SWR[54]), .A1(n2553), .B0(n2552), .Y(n3837)
);
OAI21XLTS U2311 ( .A0(Data_array_SWR[53]), .A1(n2553), .B0(n2552), .Y(n3818)
);
OAI21XLTS U2312 ( .A0(n4230), .A1(n2548), .B0(n2539), .Y(n2540) );
AOI2BB1XLTS U2313 ( .A0N(n2548), .A1N(n4241), .B0(n2547), .Y(n3819) );
INVX2TS U2314 ( .A(n3256), .Y(n3259) );
INVX2TS U2315 ( .A(n3257), .Y(n3258) );
OAI21XLTS U2316 ( .A0(n1981), .A1(n3689), .B0(n1980), .Y(n3249) );
NOR2XLTS U2317 ( .A(n3690), .B(n1981), .Y(n3250) );
INVX2TS U2318 ( .A(n3245), .Y(n3248) );
OAI21XLTS U2319 ( .A0(n3234), .A1(n3567), .B0(n3235), .Y(n3354) );
NOR2XLTS U2320 ( .A(n3238), .B(n3234), .Y(n3355) );
OAI21XLTS U2321 ( .A0(n1975), .A1(n3564), .B0(n1974), .Y(n3232) );
NOR2XLTS U2322 ( .A(n3563), .B(n1975), .Y(n3233) );
NOR2XLTS U2323 ( .A(n3604), .B(n1958), .Y(n3434) );
NOR2XLTS U2324 ( .A(DMP_SFG[3]), .B(DmP_mant_SFG_SWR[5]), .Y(n3287) );
OAI21XLTS U2325 ( .A0(n1908), .A1(n3837), .B0(n2554), .Y(n2536) );
INVX2TS U2326 ( .A(n3692), .Y(n3694) );
CLKAND2X2TS U2327 ( .A(n4266), .B(DMP_SFG[26]), .Y(n1997) );
OAI21XLTS U2328 ( .A0(n3653), .A1(n3419), .B0(n3418), .Y(n3548) );
INVX2TS U2329 ( .A(n3400), .Y(n3605) );
AFHCINX2TS U2330 ( .CIN(n3228), .B(DMP_SFG[29]), .A(DmP_mant_SFG_SWR[31]),
.S(n3229), .CO(n3337) );
INVX2TS U2331 ( .A(n3219), .Y(n3572) );
OAI21XLTS U2332 ( .A0(n3612), .A1(n3458), .B0(n3457), .Y(n3657) );
INVX2TS U2333 ( .A(n3456), .Y(n3457) );
INVX2TS U2334 ( .A(n3719), .Y(n3721) );
INVX2TS U2335 ( .A(n3207), .Y(n3592) );
INVX2TS U2336 ( .A(n3586), .Y(n3588) );
CLKAND2X2TS U2337 ( .A(DmP_mant_SFG_SWR[48]), .B(DMP_SFG[46]), .Y(n2034) );
NAND2BXLTS U2338 ( .AN(n3847), .B(n2274), .Y(n2275) );
NAND2BXLTS U2339 ( .AN(n3847), .B(n2254), .Y(n2255) );
NAND2BXLTS U2340 ( .AN(n3847), .B(n2341), .Y(n2342) );
NAND2BXLTS U2341 ( .AN(n3847), .B(n2240), .Y(n2241) );
NAND2BXLTS U2342 ( .AN(n3847), .B(n3795), .Y(n2331) );
OAI21XLTS U2343 ( .A0(n2270), .A1(n3796), .B0(n3793), .Y(n2266) );
OAI21XLTS U2344 ( .A0(n2320), .A1(n2237), .B0(n3793), .Y(n2321) );
OAI21XLTS U2345 ( .A0(n2344), .A1(n2237), .B0(n3793), .Y(n2305) );
AOI211XLTS U2346 ( .A0(n1909), .A1(n3859), .B0(n2313), .C0(n3798), .Y(n3165)
);
NOR2XLTS U2347 ( .A(n2312), .B(n2237), .Y(n2313) );
OAI21XLTS U2348 ( .A0(n3846), .A1(n1897), .B0(n3759), .Y(n4027) );
OAI21XLTS U2349 ( .A0(n3838), .A1(n3837), .B0(n3787), .Y(n3758) );
OAI21XLTS U2350 ( .A0(n3846), .A1(n1922), .B0(n3845), .Y(n4025) );
AOI211XLTS U2351 ( .A0(n1926), .A1(n3844), .B0(n3843), .C0(n3842), .Y(n3845)
);
OAI21XLTS U2352 ( .A0(n3825), .A1(n1897), .B0(n3762), .Y(n4024) );
AOI211XLTS U2353 ( .A0(n1923), .A1(n3823), .B0(n3761), .C0(n3760), .Y(n3762)
);
OAI21XLTS U2354 ( .A0(n3838), .A1(n3818), .B0(n3787), .Y(n3761) );
OAI21XLTS U2355 ( .A0(n3825), .A1(n1922), .B0(n3824), .Y(n4023) );
AOI211XLTS U2356 ( .A0(n1927), .A1(n3823), .B0(n3822), .C0(n3821), .Y(n3824)
);
AOI211XLTS U2357 ( .A0(n1923), .A1(n3815), .B0(n3777), .C0(n3776), .Y(n3778)
);
OAI21XLTS U2358 ( .A0(n3838), .A1(n3810), .B0(n3787), .Y(n3777) );
OAI21XLTS U2359 ( .A0(n3817), .A1(n1922), .B0(n3816), .Y(n4021) );
AOI211XLTS U2360 ( .A0(n1926), .A1(n3815), .B0(n3814), .C0(n3813), .Y(n3816)
);
OAI21XLTS U2361 ( .A0(n3811), .A1(n1922), .B0(n3781), .Y(n4020) );
OAI21XLTS U2362 ( .A0(n3811), .A1(n1897), .B0(n3809), .Y(n4019) );
OAI21XLTS U2363 ( .A0(n3819), .A1(n1922), .B0(n3784), .Y(n4018) );
OAI211XLTS U2364 ( .A0(n3818), .A1(n3788), .B0(n3787), .C0(n3782), .Y(n3783)
);
OAI21XLTS U2365 ( .A0(n3819), .A1(n1897), .B0(n3804), .Y(n4017) );
OAI21XLTS U2366 ( .A0(n3839), .A1(n1922), .B0(n3790), .Y(n4016) );
OAI211XLTS U2367 ( .A0(n3837), .A1(n3788), .B0(n3787), .C0(n3786), .Y(n3789)
);
OAI21XLTS U2368 ( .A0(n3839), .A1(n1897), .B0(n3801), .Y(n4015) );
OAI211XLTS U2369 ( .A0(n3796), .A1(n3795), .B0(n3794), .C0(n3793), .Y(n4014)
);
AND3X1TS U2370 ( .A(n2231), .B(n2230), .C(n2229), .Y(n2232) );
NOR2BX1TS U2371 ( .AN(n2221), .B(n2234), .Y(n4010) );
CLKAND2X2TS U2372 ( .A(n3206), .B(left_right_SHT2), .Y(n3167) );
OAI21XLTS U2373 ( .A0(n2237), .A1(n3818), .B0(n2554), .Y(n3145) );
OAI22X1TS U2374 ( .A0(n3533), .A1(n1999), .B0(n4159), .B1(DMP_SFG[48]), .Y(
n3521) );
ACHCINX2TS U2375 ( .CIN(n3489), .A(DMP_SFG[45]), .B(DmP_mant_SFG_SWR[47]),
.CO(n3540) );
CLKAND2X2TS U2376 ( .A(n4264), .B(DMP_SFG[42]), .Y(n1998) );
XOR2XLTS U2377 ( .A(DmP_mant_SFG_SWR[44]), .B(DMP_SFG[42]), .Y(n3470) );
XOR2XLTS U2378 ( .A(n4264), .B(DMP_SFG[42]), .Y(n3468) );
AFHCINX2TS U2379 ( .CIN(n3494), .B(n4122), .A(DMP_SFG[37]), .S(n3498), .CO(
n3499) );
CLKAND2X2TS U2380 ( .A(DmP_mant_SFG_SWR[38]), .B(DMP_SFG[36]), .Y(n2030) );
CLKAND2X2TS U2381 ( .A(DmP_mant_SFG_SWR[34]), .B(DMP_SFG[32]), .Y(n2028) );
OAI21XLTS U2382 ( .A0(n3725), .A1(n3719), .B0(n3720), .Y(n3223) );
INVX2TS U2383 ( .A(n3214), .Y(n3216) );
INVX2TS U2384 ( .A(n3210), .Y(n3213) );
INVX2TS U2385 ( .A(n3211), .Y(n3212) );
INVX2TS U2386 ( .A(n3671), .Y(n3253) );
OAI21XLTS U2387 ( .A0(n3364), .A1(n3252), .B0(n3251), .Y(n3255) );
OAI21XLTS U2388 ( .A0(n3365), .A1(n3692), .B0(n3693), .Y(n3367) );
INVX2TS U2389 ( .A(n3360), .Y(n3362) );
OAI21XLTS U2390 ( .A0(n3770), .A1(n3769), .B0(n3768), .Y(n3772) );
INVX2TS U2391 ( .A(n3763), .Y(n3765) );
INVX2TS U2392 ( .A(n3769), .Y(n3351) );
INVX2TS U2393 ( .A(n3234), .Y(n3236) );
OAI21XLTS U2394 ( .A0(n3712), .A1(n3556), .B0(n3555), .Y(n3585) );
INVX2TS U2395 ( .A(n3553), .Y(n3556) );
NAND4XLTS U2396 ( .A(n2380), .B(n2765), .C(n2723), .D(n2784), .Y(n3886) );
OAI21XLTS U2397 ( .A0(n3151), .A1(n4224), .B0(n2815), .Y(n3896) );
OAI21XLTS U2398 ( .A0(n3151), .A1(n4183), .B0(n2814), .Y(n3893) );
OAI21XLTS U2399 ( .A0(n4178), .A1(n3151), .B0(n2984), .Y(n3101) );
OAI21XLTS U2400 ( .A0(n4182), .A1(n3151), .B0(n2938), .Y(n3118) );
NOR2XLTS U2401 ( .A(n2874), .B(n4186), .Y(n2854) );
OAI21XLTS U2402 ( .A0(n4229), .A1(n2874), .B0(n2795), .Y(n3087) );
OAI21XLTS U2403 ( .A0(n2874), .A1(n4142), .B0(n2828), .Y(n3085) );
NOR2XLTS U2404 ( .A(n2948), .B(n4240), .Y(n2789) );
NAND3XLTS U2405 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n4079), .C(
n4211), .Y(n3909) );
MXI2XLTS U2406 ( .A(n3197), .B(n3829), .S0(n3915), .Y(n1885) );
MXI2XLTS U2407 ( .A(n3829), .B(n4187), .S0(n3915), .Y(n1886) );
MX2X1TS U2408 ( .A(n4040), .B(DmP_mant_SFG_SWR[48]), .S0(n3785), .Y(n1108)
);
MX2X1TS U2409 ( .A(n4043), .B(DmP_mant_SFG_SWR[49]), .S0(n3785), .Y(n1107)
);
MX2X1TS U2410 ( .A(n4046), .B(DmP_mant_SFG_SWR[50]), .S0(n3979), .Y(n1106)
);
MX2X1TS U2411 ( .A(n4044), .B(DmP_mant_SFG_SWR[4]), .S0(n3979), .Y(n1152) );
OAI21XLTS U2412 ( .A0(n3138), .A1(n3193), .B0(n2557), .Y(n1105) );
OAI21XLTS U2413 ( .A0(n3138), .A1(n3190), .B0(n2558), .Y(n1153) );
XOR2XLTS U2414 ( .A(n3828), .B(n3827), .Y(n3831) );
XOR2XLTS U2415 ( .A(DmP_mant_SFG_SWR[34]), .B(DMP_SFG[32]), .Y(n3827) );
OAI21XLTS U2416 ( .A0(n2538), .A1(n3193), .B0(n2534), .Y(n1102) );
XOR2XLTS U2417 ( .A(n3430), .B(n3429), .Y(n3431) );
XOR2XLTS U2418 ( .A(n3337), .B(n3336), .Y(n3338) );
XOR2XLTS U2419 ( .A(DmP_mant_SFG_SWR[32]), .B(DMP_SFG[30]), .Y(n3336) );
XOR2XLTS U2420 ( .A(n3725), .B(n3724), .Y(n3726) );
MXI2XLTS U2421 ( .A(n3980), .B(n4005), .S0(n3915), .Y(n1888) );
XNOR2X1TS U2422 ( .A(n3483), .B(n3482), .Y(n3484) );
OAI21XLTS U2423 ( .A0(n3147), .A1(n1898), .B0(n3146), .Y(n1157) );
OAI21XLTS U2424 ( .A0(n3173), .A1(n1898), .B0(n3143), .Y(n1158) );
OAI21XLTS U2425 ( .A0(n3138), .A1(n1898), .B0(n3137), .Y(n1160) );
OAI21XLTS U2426 ( .A0(n3169), .A1(n1899), .B0(n3132), .Y(n1169) );
OAI21XLTS U2427 ( .A0(n3182), .A1(n1898), .B0(n3134), .Y(n1171) );
OAI21XLTS U2428 ( .A0(n3171), .A1(n1899), .B0(n3133), .Y(n1173) );
OAI21XLTS U2429 ( .A0(n3188), .A1(n1899), .B0(n3142), .Y(n1175) );
OAI21XLTS U2430 ( .A0(n3195), .A1(n1899), .B0(n3140), .Y(n1177) );
OAI21XLTS U2431 ( .A0(n3176), .A1(n1899), .B0(n3139), .Y(n1193) );
OAI21XLTS U2432 ( .A0(n3179), .A1(n1898), .B0(n3135), .Y(n1200) );
OAI21XLTS U2433 ( .A0(n3177), .A1(n1899), .B0(n3144), .Y(n1202) );
OAI21XLTS U2434 ( .A0(n3163), .A1(n1899), .B0(n3150), .Y(n1204) );
OAI21XLTS U2435 ( .A0(n3165), .A1(n1898), .B0(n3148), .Y(n1206) );
AO22XLTS U2436 ( .A0(final_result_ieee[13]), .A1(n4035), .B0(n4045), .B1(
n4029), .Y(n1185) );
AO22XLTS U2437 ( .A0(n4047), .A1(n4046), .B0(final_result_ieee[48]), .B1(
n1901), .Y(n1162) );
AO22XLTS U2438 ( .A0(n4045), .A1(n4044), .B0(final_result_ieee[2]), .B1(
n1901), .Y(n1163) );
AO22XLTS U2439 ( .A0(n4045), .A1(n4043), .B0(final_result_ieee[47]), .B1(
n4042), .Y(n1164) );
AO22XLTS U2440 ( .A0(n4045), .A1(n4041), .B0(final_result_ieee[3]), .B1(
n4042), .Y(n1165) );
AO22XLTS U2441 ( .A0(n4045), .A1(n4040), .B0(final_result_ieee[46]), .B1(
n1901), .Y(n1166) );
AO22XLTS U2442 ( .A0(n4039), .A1(n4038), .B0(final_result_ieee[4]), .B1(
n4042), .Y(n1167) );
AO22XLTS U2443 ( .A0(n4039), .A1(n4037), .B0(final_result_ieee[40]), .B1(
n4042), .Y(n1178) );
AO22XLTS U2444 ( .A0(n4039), .A1(n4036), .B0(final_result_ieee[10]), .B1(
n4035), .Y(n1179) );
AO22XLTS U2445 ( .A0(n4039), .A1(n4034), .B0(final_result_ieee[39]), .B1(
n4035), .Y(n1180) );
AO22XLTS U2446 ( .A0(n4039), .A1(n4033), .B0(final_result_ieee[11]), .B1(
n4035), .Y(n1181) );
AO22XLTS U2447 ( .A0(n4039), .A1(n4032), .B0(final_result_ieee[38]), .B1(
n4035), .Y(n1182) );
AO22XLTS U2448 ( .A0(n4039), .A1(n4031), .B0(final_result_ieee[12]), .B1(
n4035), .Y(n1183) );
AO22XLTS U2449 ( .A0(n4039), .A1(n4030), .B0(final_result_ieee[37]), .B1(
n4042), .Y(n1184) );
AO22XLTS U2450 ( .A0(n4039), .A1(n4027), .B0(final_result_ieee[36]), .B1(
n4035), .Y(n1186) );
AO22XLTS U2451 ( .A0(n4026), .A1(n4025), .B0(final_result_ieee[14]), .B1(
n4035), .Y(n1187) );
AO22XLTS U2452 ( .A0(n4026), .A1(n4024), .B0(final_result_ieee[35]), .B1(
n4042), .Y(n1188) );
AO22XLTS U2453 ( .A0(n4026), .A1(n4023), .B0(final_result_ieee[15]), .B1(
n4035), .Y(n1189) );
AO22XLTS U2454 ( .A0(n4026), .A1(n4022), .B0(final_result_ieee[34]), .B1(
n4035), .Y(n1190) );
AO22XLTS U2455 ( .A0(n4026), .A1(n4021), .B0(final_result_ieee[16]), .B1(
n4042), .Y(n1191) );
AO22XLTS U2456 ( .A0(n4026), .A1(n4020), .B0(final_result_ieee[32]), .B1(
n4042), .Y(n1194) );
AO22XLTS U2457 ( .A0(n4026), .A1(n4019), .B0(final_result_ieee[18]), .B1(
n1901), .Y(n1195) );
AO22XLTS U2458 ( .A0(n4026), .A1(n4018), .B0(final_result_ieee[31]), .B1(
n4042), .Y(n1196) );
AO22XLTS U2459 ( .A0(n4026), .A1(n4017), .B0(final_result_ieee[19]), .B1(
n1901), .Y(n1197) );
AO22XLTS U2460 ( .A0(n4026), .A1(n4016), .B0(final_result_ieee[30]), .B1(
n1901), .Y(n1198) );
AO22XLTS U2461 ( .A0(n4047), .A1(n4015), .B0(final_result_ieee[20]), .B1(
n4042), .Y(n1199) );
AO22XLTS U2462 ( .A0(n4039), .A1(n4014), .B0(final_result_ieee[25]), .B1(
n1901), .Y(n1208) );
AOI2BB2XLTS U2463 ( .B0(n4047), .B1(n3907), .A0N(n1900), .A1N(
final_result_ieee[61]), .Y(n1677) );
AOI2BB2XLTS U2464 ( .B0(n4047), .B1(n3905), .A0N(n1900), .A1N(
final_result_ieee[59]), .Y(n1679) );
AOI2BB2XLTS U2465 ( .B0(n4047), .B1(n3904), .A0N(n1900), .A1N(
final_result_ieee[58]), .Y(n1680) );
AOI2BB2XLTS U2466 ( .B0(n4047), .B1(n3903), .A0N(n1900), .A1N(
final_result_ieee[57]), .Y(n1681) );
AOI2BB2XLTS U2467 ( .B0(n4047), .B1(n3900), .A0N(n1900), .A1N(
final_result_ieee[54]), .Y(n1684) );
AOI2BB2XLTS U2468 ( .B0(n4047), .B1(n3899), .A0N(n1900), .A1N(
final_result_ieee[53]), .Y(n1685) );
AOI2BB2XLTS U2469 ( .B0(n4047), .B1(n3898), .A0N(Shift_reg_FLAGS_7[0]),
.A1N(final_result_ieee[52]), .Y(n1686) );
AO22XLTS U2470 ( .A0(Shift_reg_FLAGS_7[0]), .A1(n4010), .B0(n4011), .B1(
underflow_flag), .Y(n1288) );
OAI21XLTS U2471 ( .A0(n3147), .A1(n3190), .B0(n2556), .Y(n1155) );
MX2X1TS U2472 ( .A(n3886), .B(LZD_output_NRM2_EW[5]), .S0(n1919), .Y(n1209)
);
MX2X1TS U2473 ( .A(n3887), .B(LZD_output_NRM2_EW[1]), .S0(n1919), .Y(n1212)
);
OAI21XLTS U2474 ( .A0(n2709), .A1(n2957), .B0(n2708), .Y(n1213) );
OAI21XLTS U2475 ( .A0(n2684), .A1(n1919), .B0(n2682), .Y(n1214) );
OAI2BB1X1TS U2476 ( .A0N(n3669), .A1N(n2411), .B0(n2410), .Y(n1216) );
XOR2XLTS U2477 ( .A(n2407), .B(n2406), .Y(n2411) );
XOR2XLTS U2478 ( .A(n4238), .B(DMP_SFG[51]), .Y(n2406) );
XNOR2X1TS U2479 ( .A(n3533), .B(n3532), .Y(n3537) );
XOR2X1TS U2480 ( .A(n3489), .B(n3488), .Y(n3491) );
XOR2XLTS U2481 ( .A(n3469), .B(n3468), .Y(n3474) );
XOR2X1TS U2482 ( .A(n3471), .B(n3470), .Y(n3472) );
XOR2X1TS U2483 ( .A(n3665), .B(n3664), .Y(n3666) );
XOR2XLTS U2484 ( .A(DmP_mant_SFG_SWR[42]), .B(DMP_SFG[40]), .Y(n3664) );
XOR2X1TS U2485 ( .A(n3598), .B(n3597), .Y(n3600) );
XOR2XLTS U2486 ( .A(DmP_mant_SFG_SWR[38]), .B(DMP_SFG[36]), .Y(n3597) );
XOR2XLTS U2487 ( .A(n3672), .B(n3262), .Y(n3263) );
AO22XLTS U2488 ( .A0(n3885), .A1(n3884), .B0(ADD_OVRFLW_NRM), .B1(n3978),
.Y(n1277) );
OAI21XLTS U2489 ( .A0(n4198), .A1(n3999), .B0(n2638), .Y(n1296) );
OAI21XLTS U2490 ( .A0(n4221), .A1(n2518), .B0(n2403), .Y(n1384) );
OAI21XLTS U2491 ( .A0(n4207), .A1(n2518), .B0(n2404), .Y(n1388) );
OAI21XLTS U2492 ( .A0(n4064), .A1(n2518), .B0(n2402), .Y(n1392) );
OAI21XLTS U2493 ( .A0(n4171), .A1(n2518), .B0(n2401), .Y(n1394) );
OAI21XLTS U2494 ( .A0(n4215), .A1(n2644), .B0(n2640), .Y(n1613) );
OAI21XLTS U2495 ( .A0(n4071), .A1(n2644), .B0(n2639), .Y(n1614) );
OAI21XLTS U2496 ( .A0(n4077), .A1(n2644), .B0(n2643), .Y(n1616) );
OAI21XLTS U2497 ( .A0(n4171), .A1(n3997), .B0(n2178), .Y(n1673) );
AO22XLTS U2498 ( .A0(Raw_mant_NRM_SWR[54]), .A1(n3890), .B0(n3889), .B1(
Data_array_SWR[0]), .Y(n3891) );
OAI211XLTS U2499 ( .A0(n1941), .A1(n2818), .B0(n2817), .C0(n2816), .Y(n1699)
);
OAI211XLTS U2500 ( .A0(n1941), .A1(n2911), .B0(n2822), .C0(n2821), .Y(n1700)
);
OAI211XLTS U2501 ( .A0(n2929), .A1(n2919), .B0(n2918), .C0(n2917), .Y(n1702)
);
OAI211XLTS U2502 ( .A0(n3091), .A1(n2811), .B0(n2808), .C0(n2807), .Y(n1722)
);
OAI211XLTS U2503 ( .A0(n2933), .A1(n2811), .B0(n2803), .C0(n2802), .Y(n1723)
);
OAI211XLTS U2504 ( .A0(n1941), .A1(n3116), .B0(n2832), .C0(n2831), .Y(n1727)
);
OAI21XLTS U2505 ( .A0(n2906), .A1(n1942), .B0(n2794), .Y(n1751) );
OAI211XLTS U2506 ( .A0(n3091), .A1(n3090), .B0(n3089), .C0(n3088), .Y(n1724)
);
OAI21XLTS U2507 ( .A0(n1942), .A1(n2792), .B0(n2791), .Y(n1752) );
OAI211XLTS U2508 ( .A0(n2855), .A1(n2744), .B0(n2743), .C0(n2742), .Y(n1695)
);
OAI21XLTS U2509 ( .A0(n2709), .A1(n3152), .B0(n2707), .Y(n1696) );
OAI21XLTS U2510 ( .A0(n2684), .A1(n3152), .B0(n2683), .Y(n1697) );
AO22XLTS U2511 ( .A0(n3943), .A1(Data_Y[62]), .B0(n3942), .B1(intDY_EWSW[62]), .Y(n1756) );
AO22XLTS U2512 ( .A0(n3943), .A1(Data_Y[59]), .B0(n3942), .B1(intDY_EWSW[59]), .Y(n1759) );
OR2X1TS U2513 ( .A(n2553), .B(n1908), .Y(n1895) );
OR2X1TS U2514 ( .A(n2327), .B(n1908), .Y(n1896) );
OR2X1TS U2515 ( .A(n1911), .B(n2237), .Y(n1897) );
INVX2TS U2516 ( .A(n4358), .Y(n1900) );
INVX2TS U2517 ( .A(n1900), .Y(n1901) );
INVX2TS U2518 ( .A(n3796), .Y(n1902) );
INVX2TS U2519 ( .A(n1902), .Y(n1903) );
INVX2TS U2520 ( .A(ADD_OVRFLW_NRM2), .Y(n1904) );
INVX2TS U2521 ( .A(n3131), .Y(n1905) );
INVX2TS U2522 ( .A(n1905), .Y(n1906) );
INVX2TS U2523 ( .A(n4357), .Y(n1907) );
INVX2TS U2524 ( .A(n1903), .Y(n1909) );
INVX2TS U2525 ( .A(n4126), .Y(n1910) );
INVX2TS U2526 ( .A(n1910), .Y(n1911) );
INVX2TS U2527 ( .A(n1895), .Y(n1912) );
INVX2TS U2528 ( .A(n1895), .Y(n1913) );
INVX2TS U2529 ( .A(Shift_reg_FLAGS_7[2]), .Y(n1914) );
INVX2TS U2530 ( .A(n1907), .Y(n1915) );
INVX2TS U2531 ( .A(n4360), .Y(n1916) );
INVX2TS U2532 ( .A(n1916), .Y(n1917) );
INVX2TS U2533 ( .A(n1916), .Y(n1918) );
INVX2TS U2534 ( .A(Shift_reg_FLAGS_7[1]), .Y(n1919) );
INVX2TS U2535 ( .A(n1919), .Y(n1920) );
OAI21XLTS U2536 ( .A0(n3837), .A1(n3836), .B0(n3835), .Y(n3843) );
OAI21XLTS U2537 ( .A0(n3836), .A1(n3818), .B0(n3835), .Y(n3822) );
OAI21XLTS U2538 ( .A0(n3836), .A1(n3810), .B0(n3835), .Y(n3814) );
OAI211XLTS U2539 ( .A0(n3810), .A1(n3840), .B0(n3835), .C0(n3806), .Y(n3807)
);
OAI211XLTS U2540 ( .A0(n3818), .A1(n3840), .B0(n3835), .C0(n3802), .Y(n3803)
);
OAI211XLTS U2541 ( .A0(n3837), .A1(n3840), .B0(n3835), .C0(n3799), .Y(n3800)
);
INVX2TS U2542 ( .A(n3808), .Y(n1922) );
INVX2TS U2543 ( .A(n1922), .Y(n1923) );
INVX2TS U2544 ( .A(n1896), .Y(n1924) );
INVX2TS U2545 ( .A(n1896), .Y(n1925) );
INVX2TS U2546 ( .A(n1897), .Y(n1926) );
INVX2TS U2547 ( .A(n1897), .Y(n1927) );
CLKBUFX2TS U2548 ( .A(n3130), .Y(n1928) );
INVX2TS U2549 ( .A(n1906), .Y(n3149) );
INVX2TS U2550 ( .A(n2333), .Y(n1929) );
INVX2TS U2551 ( .A(n2548), .Y(n1930) );
INVX2TS U2552 ( .A(n2548), .Y(n1931) );
OAI22X1TS U2553 ( .A0(n3598), .A1(n2030), .B0(DMP_SFG[36]), .B1(
DmP_mant_SFG_SWR[38]), .Y(n3495) );
NOR2X1TS U2554 ( .A(n3792), .B(n4210), .Y(n3847) );
OAI22X1TS U2555 ( .A0(n3471), .A1(n2032), .B0(DMP_SFG[42]), .B1(
DmP_mant_SFG_SWR[44]), .Y(n3477) );
NOR2X1TS U2556 ( .A(ADD_OVRFLW_NRM), .B(n3197), .Y(n3890) );
NOR2X1TS U2557 ( .A(n3829), .B(OP_FLAG_SFG), .Y(n3884) );
INVX2TS U2558 ( .A(n2549), .Y(n1932) );
CLKBUFX2TS U2559 ( .A(n3748), .Y(n1933) );
OAI21XLTS U2560 ( .A0(Raw_mant_NRM_SWR[50]), .A1(n4062), .B0(n4157), .Y(
n2770) );
OAI21XLTS U2561 ( .A0(intDY_EWSW[15]), .A1(n4060), .B0(intDY_EWSW[14]), .Y(
n2077) );
NOR2XLTS U2562 ( .A(n4105), .B(DMP_SFG[14]), .Y(n1966) );
NOR2XLTS U2563 ( .A(n4102), .B(DMP_SFG[18]), .Y(n1977) );
OAI21XLTS U2564 ( .A0(n1966), .A1(n3545), .B0(n1965), .Y(n1967) );
OAI211XLTS U2565 ( .A0(intDY_EWSW[8]), .A1(n4147), .B0(n2071), .C0(n2074),
.Y(n2082) );
OAI21XLTS U2566 ( .A0(n3214), .A1(n3720), .B0(n3215), .Y(n2023) );
NOR2XLTS U2567 ( .A(n4091), .B(n2327), .Y(n2273) );
AND3X1TS U2568 ( .A(n3902), .B(n3901), .C(n2228), .Y(n2229) );
NOR2XLTS U2569 ( .A(DMP_SFG[25]), .B(DmP_mant_SFG_SWR[27]), .Y(n3214) );
NOR2XLTS U2570 ( .A(n2154), .B(n2153), .Y(n2167) );
INVX2TS U2571 ( .A(n3420), .Y(n3422) );
INVX2TS U2572 ( .A(n3455), .Y(n3458) );
AOI21X1TS U2573 ( .A0(n1962), .A1(n3435), .B0(n1961), .Y(n3414) );
NOR2XLTS U2574 ( .A(n4110), .B(DMP_SFG[4]), .Y(n1950) );
OAI21XLTS U2575 ( .A0(n4233), .A1(n2327), .B0(n2247), .Y(n2248) );
NOR2XLTS U2576 ( .A(n4106), .B(DMP_SFG[13]), .Y(n3544) );
AOI211XLTS U2577 ( .A0(intDY_EWSW[46]), .A1(n2134), .B0(n2133), .C0(n2132),
.Y(n2171) );
OAI2BB2X1TS U2578 ( .B0(n3828), .B1(n2028), .A0N(n1935), .A1N(n4049), .Y(
n3331) );
INVX2TS U2579 ( .A(n3424), .Y(n3612) );
OAI21XLTS U2580 ( .A0(n1950), .A1(n3300), .B0(n1949), .Y(n3371) );
INVX2TS U2581 ( .A(n3673), .Y(n3675) );
OAI21XLTS U2582 ( .A0(Data_array_SWR[51]), .A1(n2553), .B0(n2552), .Y(n2270)
);
OAI211XLTS U2583 ( .A0(n3640), .A1(n3810), .B0(n3619), .C0(n3618), .Y(n3620)
);
OAI21XLTS U2584 ( .A0(n4231), .A1(n2548), .B0(n2528), .Y(n2529) );
OAI211XLTS U2585 ( .A0(n3810), .A1(n3788), .B0(n3787), .C0(n3779), .Y(n3780)
);
OAI2BB1X1TS U2586 ( .A0N(n1937), .A1N(DmP_mant_SFG_SWR[53]), .B0(n2407), .Y(
n2001) );
OAI2BB2X2TS U2587 ( .B0(n3337), .B1(n2027), .A0N(n1934), .A1N(n4048), .Y(
n3342) );
NOR2XLTS U2588 ( .A(n4255), .B(DMP_SFG[17]), .Y(n3349) );
OAI21XLTS U2589 ( .A0(n3612), .A1(n3606), .B0(n3607), .Y(n3443) );
NOR2XLTS U2590 ( .A(n4243), .B(DMP_EXP_EWSW[56]), .Y(n3959) );
NOR2XLTS U2591 ( .A(n2789), .B(n3197), .Y(n2790) );
AFHCINX2TS U2592 ( .CIN(n3331), .B(DMP_SFG[33]), .A(DmP_mant_SFG_SWR[35]),
.S(n3332), .CO(n3326) );
OAI21XLTS U2593 ( .A0(n3718), .A1(n3717), .B0(n3716), .Y(n3723) );
OAI21XLTS U2594 ( .A0(n3672), .A1(n3671), .B0(n3670), .Y(n3676) );
OAI21XLTS U2595 ( .A0(n2295), .A1(n2237), .B0(n3793), .Y(n2296) );
AOI211XLTS U2596 ( .A0(n1923), .A1(n3844), .B0(n3758), .C0(n3757), .Y(n3759)
);
XNOR2X1TS U2597 ( .A(n3540), .B(n3539), .Y(n3541) );
AFHCINX2TS U2598 ( .CIN(n3342), .B(DMP_SFG[31]), .A(DmP_mant_SFG_SWR[33]),
.S(n3343), .CO(n3828) );
OAI21XLTS U2599 ( .A0(n3605), .A1(n3437), .B0(n3436), .Y(n3451) );
OAI21XLTS U2600 ( .A0(n2633), .A1(n4360), .B0(n2644), .Y(n2631) );
OAI21XLTS U2601 ( .A0(DmP_EXP_EWSW[55]), .A1(n4214), .B0(n3955), .Y(n3952)
);
OAI21XLTS U2602 ( .A0(n2874), .A1(n4185), .B0(n2873), .Y(n2920) );
OAI21XLTS U2603 ( .A0(n4184), .A1(n3151), .B0(n3019), .Y(n3092) );
OAI21XLTS U2604 ( .A0(n2874), .A1(n4227), .B0(n2801), .Y(n3076) );
NOR2XLTS U2605 ( .A(n2533), .B(n2532), .Y(n2538) );
XOR2XLTS U2606 ( .A(n3505), .B(n3504), .Y(n3509) );
AOI32X1TS U2607 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n3196), .B1(n4211), .Y(n3915)
);
OAI21XLTS U2608 ( .A0(n3817), .A1(n1897), .B0(n3778), .Y(n4022) );
INVX2TS U2609 ( .A(n4028), .Y(n4047) );
OR2X1TS U2610 ( .A(n3883), .B(DmP_mant_SFG_SWR[54]), .Y(n3885) );
AOI211XLTS U2611 ( .A0(n3894), .A1(n3893), .B0(n3892), .C0(n3891), .Y(n3895)
);
NAND2X1TS U2612 ( .A(n2797), .B(n2768), .Y(n3090) );
NOR3XLTS U2613 ( .A(n2705), .B(n2786), .C(n2681), .Y(n2684) );
OAI21XLTS U2614 ( .A0(n3147), .A1(n3193), .B0(n2555), .Y(n1103) );
OAI21XLTS U2615 ( .A0(n2538), .A1(n3190), .B0(n2537), .Y(n1156) );
OAI21XLTS U2616 ( .A0(n3911), .A1(n2412), .B0(n3909), .Y(n1891) );
OAI21XLTS U2617 ( .A0(n3169), .A1(n1906), .B0(n2284), .Y(n1168) );
OAI21XLTS U2618 ( .A0(n3177), .A1(n1906), .B0(n2300), .Y(n1203) );
OAI21XLTS U2619 ( .A0(n4198), .A1(n4000), .B0(n2636), .Y(n1624) );
OAI21XLTS U2620 ( .A0(n4064), .A1(n3997), .B0(n2179), .Y(n1672) );
OAI211XLTS U2621 ( .A0(n2933), .A1(n3090), .B0(n2932), .C0(n2931), .Y(n1725)
);
CLKBUFX2TS U2622 ( .A(n1914), .Y(n3978) );
NOR2BX1TS U2623 ( .AN(OP_FLAG_SFG), .B(n3978), .Y(n3347) );
CLKBUFX2TS U2624 ( .A(n3347), .Y(n3526) );
NAND2X1TS U2625 ( .A(n1940), .B(n4274), .Y(n3313) );
NOR2XLTS U2626 ( .A(n4261), .B(DMP_SFG[0]), .Y(n1944) );
NAND2X1TS U2627 ( .A(n4261), .B(DMP_SFG[0]), .Y(n1943) );
NOR2XLTS U2628 ( .A(n4098), .B(DMP_SFG[1]), .Y(n3268) );
NOR2XLTS U2629 ( .A(n4112), .B(DMP_SFG[2]), .Y(n1946) );
NOR2XLTS U2630 ( .A(n3268), .B(n1946), .Y(n1948) );
NAND2X1TS U2631 ( .A(n4098), .B(DMP_SFG[1]), .Y(n3267) );
NAND2X1TS U2632 ( .A(n4112), .B(DMP_SFG[2]), .Y(n1945) );
OAI21XLTS U2633 ( .A0(n1946), .A1(n3267), .B0(n1945), .Y(n1947) );
AOI21X1TS U2634 ( .A0(n3266), .A1(n1948), .B0(n1947), .Y(n3286) );
NOR2XLTS U2635 ( .A(n4111), .B(DMP_SFG[3]), .Y(n3299) );
NAND2X1TS U2636 ( .A(n3372), .B(n1954), .Y(n1956) );
NAND2X1TS U2637 ( .A(n4111), .B(DMP_SFG[3]), .Y(n3300) );
NAND2X1TS U2638 ( .A(n4110), .B(DMP_SFG[4]), .Y(n1949) );
NAND2X1TS U2639 ( .A(n4260), .B(DMP_SFG[5]), .Y(n3386) );
NAND2X1TS U2640 ( .A(n4259), .B(DMP_SFG[6]), .Y(n1951) );
OAI21X1TS U2641 ( .A0(n1952), .A1(n3386), .B0(n1951), .Y(n1953) );
AOI21X1TS U2642 ( .A0(n1954), .A1(n3371), .B0(n1953), .Y(n1955) );
NAND2X1TS U2643 ( .A(n3434), .B(n1962), .Y(n3415) );
NOR2X1TS U2644 ( .A(n3702), .B(n1964), .Y(n3416) );
NAND2X1TS U2645 ( .A(n3416), .B(n1968), .Y(n1970) );
NOR2X1TS U2646 ( .A(n3415), .B(n1970), .Y(n1972) );
NAND2X1TS U2647 ( .A(n4258), .B(DMP_SFG[7]), .Y(n3603) );
NAND2X1TS U2648 ( .A(n4257), .B(DMP_SFG[8]), .Y(n1957) );
NAND2X1TS U2649 ( .A(n4256), .B(DMP_SFG[9]), .Y(n3448) );
NAND2X1TS U2650 ( .A(n4109), .B(DMP_SFG[10]), .Y(n1959) );
NAND2X1TS U2651 ( .A(n4108), .B(DMP_SFG[11]), .Y(n3703) );
NAND2X1TS U2652 ( .A(n4107), .B(DMP_SFG[12]), .Y(n1963) );
NAND2X1TS U2653 ( .A(n4106), .B(DMP_SFG[13]), .Y(n3545) );
NAND2X1TS U2654 ( .A(n4105), .B(DMP_SFG[14]), .Y(n1965) );
AOI21X1TS U2655 ( .A0(n1968), .A1(n3417), .B0(n1967), .Y(n1969) );
OAI21X1TS U2656 ( .A0(n3414), .A1(n1970), .B0(n1969), .Y(n1971) );
AOI21X1TS U2657 ( .A0(n3400), .A1(n1972), .B0(n1971), .Y(n3207) );
NOR2X1TS U2658 ( .A(n3349), .B(n1977), .Y(n1979) );
NAND2X1TS U2659 ( .A(n3233), .B(n1979), .Y(n3245) );
NAND2X1TS U2660 ( .A(n3250), .B(n1985), .Y(n1987) );
INVX2TS U2661 ( .A(n3717), .Y(n1973) );
NAND2X1TS U2662 ( .A(n1973), .B(n1990), .Y(n3210) );
NAND2X1TS U2663 ( .A(n3209), .B(n1994), .Y(n1996) );
NAND2X1TS U2664 ( .A(n4104), .B(DMP_SFG[15]), .Y(n3564) );
NAND2X1TS U2665 ( .A(n4103), .B(DMP_SFG[16]), .Y(n1974) );
NAND2X1TS U2666 ( .A(n4255), .B(DMP_SFG[17]), .Y(n3348) );
NAND2X1TS U2667 ( .A(n4102), .B(DMP_SFG[18]), .Y(n1976) );
AOI21X1TS U2668 ( .A0(n1979), .A1(n3232), .B0(n1978), .Y(n3246) );
NAND2X1TS U2669 ( .A(n4101), .B(DMP_SFG[19]), .Y(n3689) );
NAND2X1TS U2670 ( .A(n4100), .B(DMP_SFG[20]), .Y(n1980) );
NAND2X1TS U2671 ( .A(n4254), .B(DMP_SFG[21]), .Y(n3251) );
NAND2X1TS U2672 ( .A(n4253), .B(DMP_SFG[22]), .Y(n1982) );
AOI21X1TS U2673 ( .A0(n1985), .A1(n3249), .B0(n1984), .Y(n1986) );
OAI21X1TS U2674 ( .A0(n3246), .A1(n1987), .B0(n1986), .Y(n3208) );
NAND2X1TS U2675 ( .A(n4252), .B(DMP_SFG[23]), .Y(n3716) );
INVX2TS U2676 ( .A(n3716), .Y(n1989) );
CLKAND2X2TS U2677 ( .A(n4251), .B(DMP_SFG[24]), .Y(n1988) );
AOI21X1TS U2678 ( .A0(n1990), .A1(n1989), .B0(n1988), .Y(n3211) );
NAND2X1TS U2679 ( .A(n4099), .B(DMP_SFG[25]), .Y(n1991) );
AOI21X1TS U2680 ( .A0(n3208), .A1(n1994), .B0(n1993), .Y(n1995) );
OAI21X2TS U2681 ( .A0(n3207), .A1(n1996), .B0(n1995), .Y(n3505) );
CLKAND2X2TS U2682 ( .A(n4159), .B(DMP_SFG[48]), .Y(n1999) );
OAI2BB1X2TS U2683 ( .A0N(n1938), .A1N(DmP_mant_SFG_SWR[52]), .B0(n3516), .Y(
n2000) );
XNOR2X1TS U2684 ( .A(n2002), .B(n4250), .Y(n2037) );
NOR2X1TS U2685 ( .A(DMP_SFG[2]), .B(DmP_mant_SFG_SWR[4]), .Y(n3292) );
NOR2X1TS U2686 ( .A(DMP_SFG[1]), .B(DmP_mant_SFG_SWR[3]), .Y(n3277) );
NAND2X1TS U2687 ( .A(DMP_SFG[0]), .B(DmP_mant_SFG_SWR[2]), .Y(n3311) );
NAND2X1TS U2688 ( .A(DMP_SFG[1]), .B(DmP_mant_SFG_SWR[3]), .Y(n3278) );
OAI21X1TS U2689 ( .A0(n3277), .A1(n3311), .B0(n3278), .Y(n3272) );
NAND2X1TS U2690 ( .A(DMP_SFG[2]), .B(DmP_mant_SFG_SWR[4]), .Y(n3291) );
NAND2X1TS U2691 ( .A(DMP_SFG[3]), .B(DmP_mant_SFG_SWR[5]), .Y(n3288) );
AOI21X1TS U2692 ( .A0(n2004), .A1(n3272), .B0(n2003), .Y(n3306) );
NOR2X1TS U2693 ( .A(DMP_SFG[6]), .B(DmP_mant_SFG_SWR[8]), .Y(n3406) );
NAND2X1TS U2694 ( .A(n3393), .B(n2006), .Y(n2008) );
NAND2X1TS U2695 ( .A(DMP_SFG[4]), .B(DmP_mant_SFG_SWR[6]), .Y(n3378) );
NAND2X1TS U2696 ( .A(DMP_SFG[5]), .B(DmP_mant_SFG_SWR[7]), .Y(n3375) );
NAND2X1TS U2697 ( .A(DMP_SFG[6]), .B(DmP_mant_SFG_SWR[8]), .Y(n3405) );
NAND2X1TS U2698 ( .A(DMP_SFG[7]), .B(DmP_mant_SFG_SWR[9]), .Y(n3402) );
AOI21X1TS U2699 ( .A0(n3392), .A1(n2006), .B0(n2005), .Y(n2007) );
OAI21X1TS U2700 ( .A0(n3306), .A1(n2008), .B0(n2007), .Y(n3424) );
NOR2X1TS U2701 ( .A(DMP_SFG[9]), .B(DmP_mant_SFG_SWR[11]), .Y(n3438) );
NAND2X1TS U2702 ( .A(n3455), .B(n2010), .Y(n3426) );
NAND2X1TS U2703 ( .A(n3553), .B(n2012), .Y(n2014) );
NAND2X1TS U2704 ( .A(DMP_SFG[8]), .B(DmP_mant_SFG_SWR[10]), .Y(n3607) );
NAND2X1TS U2705 ( .A(DMP_SFG[9]), .B(DmP_mant_SFG_SWR[11]), .Y(n3439) );
OAI21X1TS U2706 ( .A0(n3438), .A1(n3607), .B0(n3439), .Y(n3456) );
NAND2X1TS U2707 ( .A(DMP_SFG[10]), .B(DmP_mant_SFG_SWR[12]), .Y(n3654) );
NAND2X1TS U2708 ( .A(DMP_SFG[11]), .B(DmP_mant_SFG_SWR[13]), .Y(n3650) );
AOI21X1TS U2709 ( .A0(n2010), .A1(n3456), .B0(n2009), .Y(n3425) );
NAND2X1TS U2710 ( .A(DMP_SFG[12]), .B(DmP_mant_SFG_SWR[14]), .Y(n3707) );
NAND2X1TS U2711 ( .A(DMP_SFG[13]), .B(DmP_mant_SFG_SWR[15]), .Y(n3421) );
NAND2X1TS U2712 ( .A(DMP_SFG[14]), .B(DmP_mant_SFG_SWR[16]), .Y(n3582) );
NAND2X1TS U2713 ( .A(DMP_SFG[15]), .B(DmP_mant_SFG_SWR[17]), .Y(n3587) );
AOI21X1TS U2714 ( .A0(n2012), .A1(n3554), .B0(n2011), .Y(n2013) );
OAI21X1TS U2715 ( .A0(n3425), .A1(n2014), .B0(n2013), .Y(n2015) );
AOI21X2TS U2716 ( .A0(n3424), .A1(n2016), .B0(n2015), .Y(n3219) );
NOR2X1TS U2717 ( .A(DMP_SFG[18]), .B(DmP_mant_SFG_SWR[20]), .Y(n3769) );
NOR2X1TS U2718 ( .A(DMP_SFG[19]), .B(DmP_mant_SFG_SWR[21]), .Y(n3763) );
NOR2X1TS U2719 ( .A(DMP_SFG[17]), .B(DmP_mant_SFG_SWR[19]), .Y(n3234) );
NAND2X1TS U2720 ( .A(n2018), .B(n3355), .Y(n3256) );
NOR2X1TS U2721 ( .A(DMP_SFG[20]), .B(DmP_mant_SFG_SWR[22]), .Y(n3692) );
NOR2X1TS U2722 ( .A(DMP_SFG[23]), .B(DmP_mant_SFG_SWR[25]), .Y(n3673) );
NAND2X1TS U2723 ( .A(n3261), .B(n2020), .Y(n2022) );
NOR2X1TS U2724 ( .A(n3256), .B(n2022), .Y(n3221) );
NAND2X1TS U2725 ( .A(n3221), .B(n2024), .Y(n2026) );
NAND2X1TS U2726 ( .A(DMP_SFG[16]), .B(DmP_mant_SFG_SWR[18]), .Y(n3567) );
NAND2X1TS U2727 ( .A(DMP_SFG[17]), .B(DmP_mant_SFG_SWR[19]), .Y(n3235) );
NAND2X1TS U2728 ( .A(DMP_SFG[18]), .B(DmP_mant_SFG_SWR[20]), .Y(n3768) );
NAND2X1TS U2729 ( .A(DMP_SFG[19]), .B(DmP_mant_SFG_SWR[21]), .Y(n3764) );
AOI21X1TS U2730 ( .A0(n2018), .A1(n3354), .B0(n2017), .Y(n3257) );
NAND2X1TS U2731 ( .A(DMP_SFG[20]), .B(DmP_mant_SFG_SWR[22]), .Y(n3693) );
NAND2X1TS U2732 ( .A(DMP_SFG[21]), .B(DmP_mant_SFG_SWR[23]), .Y(n3361) );
NAND2X1TS U2733 ( .A(DMP_SFG[22]), .B(DmP_mant_SFG_SWR[24]), .Y(n3670) );
NAND2X1TS U2734 ( .A(DMP_SFG[23]), .B(DmP_mant_SFG_SWR[25]), .Y(n3674) );
AOI21X1TS U2735 ( .A0(n2020), .A1(n3260), .B0(n2019), .Y(n2021) );
NAND2X1TS U2736 ( .A(DMP_SFG[24]), .B(DmP_mant_SFG_SWR[26]), .Y(n3720) );
NAND2X1TS U2737 ( .A(DMP_SFG[25]), .B(DmP_mant_SFG_SWR[27]), .Y(n3215) );
AOI21X1TS U2738 ( .A0(n3220), .A1(n2024), .B0(n2023), .Y(n2025) );
OAI21X2TS U2739 ( .A0(n3219), .A1(n2026), .B0(n2025), .Y(n3506) );
OAI22X2TS U2740 ( .A0(n3665), .A1(n2031), .B0(DMP_SFG[40]), .B1(
DmP_mant_SFG_SWR[42]), .Y(n3464) );
CLKBUFX2TS U2741 ( .A(n1914), .Y(n3829) );
CLKBUFX2TS U2742 ( .A(n3884), .Y(n3830) );
NOR2BX1TS U2743 ( .AN(intDX_EWSW[39]), .B(intDY_EWSW[39]), .Y(n2147) );
AOI21X1TS U2744 ( .A0(intDX_EWSW[38]), .A1(n4204), .B0(n2147), .Y(n2146) );
NAND2X1TS U2745 ( .A(n4202), .B(intDX_EWSW[37]), .Y(n2135) );
OA22X1TS U2746 ( .A0(n4140), .A1(intDY_EWSW[42]), .B0(n4056), .B1(
intDY_EWSW[43]), .Y(n2126) );
NOR2XLTS U2747 ( .A(n4244), .B(intDY_EWSW[53]), .Y(n2040) );
OAI22X1TS U2748 ( .A0(n4245), .A1(intDY_EWSW[55]), .B0(intDY_EWSW[54]), .B1(
n4096), .Y(n2153) );
NOR2BX1TS U2749 ( .AN(intDX_EWSW[56]), .B(intDY_EWSW[56]), .Y(n2041) );
NAND2X1TS U2750 ( .A(n4156), .B(intDX_EWSW[61]), .Y(n2113) );
NOR4XLTS U2751 ( .A(n2107), .B(n2041), .C(n2119), .D(n2111), .Y(n2164) );
AOI211XLTS U2752 ( .A0(intDX_EWSW[48]), .A1(n4190), .B0(n2156), .C0(n2162),
.Y(n2042) );
OA22X1TS U2753 ( .A0(n4141), .A1(intDY_EWSW[34]), .B0(n4057), .B1(
intDY_EWSW[35]), .Y(n2141) );
OAI211XLTS U2754 ( .A0(n4129), .A1(intDY_EWSW[33]), .B0(n2043), .C0(n2141),
.Y(n2044) );
NOR4XLTS U2755 ( .A(n2137), .B(n2170), .C(n2172), .D(n2044), .Y(n2176) );
OA22X1TS U2756 ( .A0(n4154), .A1(intDY_EWSW[30]), .B0(n4059), .B1(
intDY_EWSW[31]), .Y(n2591) );
OAI21XLTS U2757 ( .A0(intDY_EWSW[29]), .A1(n4132), .B0(intDY_EWSW[28]), .Y(
n2045) );
OAI2BB2XLTS U2758 ( .B0(intDX_EWSW[28]), .B1(n2045), .A0N(intDY_EWSW[29]),
.A1N(n4132), .Y(n2054) );
NOR2XLTS U2759 ( .A(n4144), .B(intDY_EWSW[25]), .Y(n2099) );
NOR2XLTS U2760 ( .A(intDX_EWSW[24]), .B(n2099), .Y(n2047) );
AOI22X1TS U2761 ( .A0(intDY_EWSW[24]), .A1(n2047), .B0(intDY_EWSW[25]), .B1(
n4144), .Y(n2050) );
AOI32X1TS U2762 ( .A0(n2048), .A1(n4075), .A2(intDY_EWSW[26]), .B0(
intDY_EWSW[27]), .B1(n4150), .Y(n2049) );
OAI32X1TS U2763 ( .A0(n2102), .A1(n2101), .A2(n2050), .B0(n2049), .B1(n2101),
.Y(n2053) );
OAI21XLTS U2764 ( .A0(intDY_EWSW[31]), .A1(n4059), .B0(intDY_EWSW[30]), .Y(
n2051) );
OAI2BB2XLTS U2765 ( .B0(intDX_EWSW[30]), .B1(n2051), .A0N(intDY_EWSW[31]),
.A1N(n4059), .Y(n2052) );
OA22X1TS U2766 ( .A0(n4155), .A1(intDY_EWSW[22]), .B0(n4061), .B1(
intDY_EWSW[23]), .Y(n2599) );
OA22X1TS U2767 ( .A0(n4124), .A1(intDY_EWSW[14]), .B0(n4060), .B1(
intDY_EWSW[15]), .Y(n2607) );
OAI2BB1X1TS U2768 ( .A0N(n4207), .A1N(intDX_EWSW[5]), .B0(intDY_EWSW[4]),
.Y(n2057) );
OAI22X1TS U2769 ( .A0(intDX_EWSW[4]), .A1(n2057), .B0(n4207), .B1(
intDX_EWSW[5]), .Y(n2067) );
OAI2BB1X1TS U2770 ( .A0N(n4221), .A1N(intDX_EWSW[7]), .B0(intDY_EWSW[6]),
.Y(n2058) );
OAI22X1TS U2771 ( .A0(intDX_EWSW[6]), .A1(n2058), .B0(n4221), .B1(
intDX_EWSW[7]), .Y(n2066) );
NAND2BXLTS U2772 ( .AN(intDY_EWSW[2]), .B(intDX_EWSW[2]), .Y(n2061) );
OAI21XLTS U2773 ( .A0(intDX_EWSW[1]), .A1(n4203), .B0(intDX_EWSW[0]), .Y(
n2059) );
AOI2BB2XLTS U2774 ( .B0(intDX_EWSW[1]), .B1(n4203), .A0N(intDY_EWSW[0]),
.A1N(n2059), .Y(n2060) );
OAI21XLTS U2775 ( .A0(intDY_EWSW[3]), .A1(n4121), .B0(intDY_EWSW[2]), .Y(
n2062) );
AOI2BB2XLTS U2776 ( .B0(intDY_EWSW[3]), .B1(n4121), .A0N(intDX_EWSW[2]),
.A1N(n2062), .Y(n2063) );
AOI222XLTS U2777 ( .A0(intDX_EWSW[4]), .A1(n4078), .B0(intDX_EWSW[5]), .B1(
n4207), .C0(n2064), .C1(n2063), .Y(n2065) );
AOI22X1TS U2778 ( .A0(intDX_EWSW[7]), .A1(n4221), .B0(intDX_EWSW[6]), .B1(
n4089), .Y(n2615) );
OAI32X1TS U2779 ( .A0(n2067), .A1(n2066), .A2(n2065), .B0(n2615), .B1(n2066),
.Y(n2083) );
AOI21X1TS U2780 ( .A0(intDX_EWSW[10]), .A1(n4162), .B0(n2069), .Y(n2074) );
OAI21XLTS U2781 ( .A0(intDY_EWSW[13]), .A1(n4133), .B0(intDY_EWSW[12]), .Y(
n2068) );
OAI2BB2XLTS U2782 ( .B0(intDX_EWSW[12]), .B1(n2068), .A0N(intDY_EWSW[13]),
.A1N(n4133), .Y(n2080) );
AOI22X1TS U2783 ( .A0(intDY_EWSW[10]), .A1(n2070), .B0(intDY_EWSW[11]), .B1(
n4145), .Y(n2076) );
AOI21X1TS U2784 ( .A0(n2073), .A1(n2072), .B0(n2084), .Y(n2075) );
OAI2BB2XLTS U2785 ( .B0(n2076), .B1(n2084), .A0N(n2075), .A1N(n2074), .Y(
n2079) );
OAI2BB2XLTS U2786 ( .B0(intDX_EWSW[14]), .B1(n2077), .A0N(intDY_EWSW[15]),
.A1N(n4060), .Y(n2078) );
OAI31X1TS U2787 ( .A0(n2084), .A1(n2083), .A2(n2082), .B0(n2081), .Y(n2086)
);
AOI211XLTS U2788 ( .A0(intDX_EWSW[16]), .A1(n4191), .B0(n2088), .C0(n2094),
.Y(n2085) );
OAI21XLTS U2789 ( .A0(intDY_EWSW[21]), .A1(n4134), .B0(intDY_EWSW[20]), .Y(
n2087) );
OAI2BB2XLTS U2790 ( .B0(intDX_EWSW[20]), .B1(n2087), .A0N(intDY_EWSW[21]),
.A1N(n4134), .Y(n2098) );
AOI22X1TS U2791 ( .A0(n2089), .A1(intDY_EWSW[16]), .B0(intDY_EWSW[17]), .B1(
n4146), .Y(n2092) );
AOI32X1TS U2792 ( .A0(n4074), .A1(n2090), .A2(intDY_EWSW[18]), .B0(
intDY_EWSW[19]), .B1(n4151), .Y(n2091) );
OAI32X1TS U2793 ( .A0(n2094), .A1(n2093), .A2(n2092), .B0(n2091), .B1(n2093),
.Y(n2097) );
OAI21XLTS U2794 ( .A0(intDY_EWSW[23]), .A1(n4061), .B0(intDY_EWSW[22]), .Y(
n2095) );
OAI2BB2XLTS U2795 ( .B0(intDX_EWSW[22]), .B1(n2095), .A0N(intDY_EWSW[23]),
.A1N(n4061), .Y(n2096) );
NOR2BX1TS U2796 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n2100) );
OR4X2TS U2797 ( .A(n2102), .B(n2101), .C(n2100), .D(n2099), .Y(n2103) );
AOI32X1TS U2798 ( .A0(n2106), .A1(n2105), .A2(n2104), .B0(n2103), .B1(n2106),
.Y(n2175) );
NOR2XLTS U2799 ( .A(intDX_EWSW[56]), .B(n2107), .Y(n2108) );
AOI22X1TS U2800 ( .A0(intDY_EWSW[56]), .A1(n2108), .B0(intDY_EWSW[57]), .B1(
n4149), .Y(n2112) );
AOI32X1TS U2801 ( .A0(n2109), .A1(n4219), .A2(intDY_EWSW[58]), .B0(
intDY_EWSW[59]), .B1(n4077), .Y(n2110) );
OA21XLTS U2802 ( .A0(n2112), .A1(n2111), .B0(n2110), .Y(n2118) );
OAI211XLTS U2803 ( .A0(intDX_EWSW[61]), .A1(n4156), .B0(n2115), .C0(n2114),
.Y(n2116) );
OAI2BB2XLTS U2804 ( .B0(n2119), .B1(n2118), .A0N(n2117), .A1N(n2116), .Y(
n2174) );
NOR2BX1TS U2805 ( .AN(n2120), .B(intDX_EWSW[46]), .Y(n2134) );
NOR2XLTS U2806 ( .A(intDX_EWSW[44]), .B(n2121), .Y(n2122) );
AOI22X1TS U2807 ( .A0(intDY_EWSW[44]), .A1(n2122), .B0(intDY_EWSW[45]), .B1(
n4143), .Y(n2131) );
OAI21XLTS U2808 ( .A0(intDY_EWSW[41]), .A1(n4130), .B0(intDY_EWSW[40]), .Y(
n2123) );
OAI2BB2XLTS U2809 ( .B0(intDX_EWSW[40]), .B1(n2123), .A0N(intDY_EWSW[41]),
.A1N(n4130), .Y(n2127) );
OAI21XLTS U2810 ( .A0(intDY_EWSW[43]), .A1(n4056), .B0(intDY_EWSW[42]), .Y(
n2124) );
OAI2BB2XLTS U2811 ( .B0(intDX_EWSW[42]), .B1(n2124), .A0N(intDY_EWSW[43]),
.A1N(n4056), .Y(n2125) );
AOI32X1TS U2812 ( .A0(n2128), .A1(n2127), .A2(n2126), .B0(n2125), .B1(n2128),
.Y(n2129) );
NOR2BX1TS U2813 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2132) );
OAI21XLTS U2814 ( .A0(intDX_EWSW[37]), .A1(n4202), .B0(n2136), .Y(n2145) );
OAI21XLTS U2815 ( .A0(intDY_EWSW[33]), .A1(n4129), .B0(intDY_EWSW[32]), .Y(
n2138) );
OAI2BB2XLTS U2816 ( .B0(intDX_EWSW[32]), .B1(n2138), .A0N(intDY_EWSW[33]),
.A1N(n4129), .Y(n2142) );
OAI21XLTS U2817 ( .A0(intDY_EWSW[35]), .A1(n4057), .B0(intDY_EWSW[34]), .Y(
n2139) );
OAI2BB2XLTS U2818 ( .B0(intDX_EWSW[34]), .B1(n2139), .A0N(intDY_EWSW[35]),
.A1N(n4057), .Y(n2140) );
AOI32X1TS U2819 ( .A0(n2143), .A1(n2142), .A2(n2141), .B0(n2140), .B1(n2143),
.Y(n2144) );
OAI2BB1X1TS U2820 ( .A0N(n2146), .A1N(n2145), .B0(n2144), .Y(n2151) );
NOR3XLTS U2821 ( .A(n4204), .B(intDX_EWSW[38]), .C(n2147), .Y(n2150) );
NOR2BX1TS U2822 ( .AN(intDY_EWSW[39]), .B(intDX_EWSW[39]), .Y(n2149) );
OAI31X1TS U2823 ( .A0(n2151), .A1(n2150), .A2(n2149), .B0(n2148), .Y(n2169)
);
OAI21XLTS U2824 ( .A0(intDY_EWSW[53]), .A1(n4244), .B0(intDY_EWSW[52]), .Y(
n2152) );
NOR2XLTS U2825 ( .A(intDX_EWSW[48]), .B(n2156), .Y(n2157) );
AOI22X1TS U2826 ( .A0(intDY_EWSW[48]), .A1(n2157), .B0(intDY_EWSW[49]), .B1(
n4223), .Y(n2160) );
AOI32X1TS U2827 ( .A0(n2158), .A1(n4148), .A2(intDY_EWSW[50]), .B0(
intDY_EWSW[51]), .B1(n4073), .Y(n2159) );
OAI32X1TS U2828 ( .A0(n2162), .A1(n2161), .A2(n2160), .B0(n2159), .B1(n2161),
.Y(n2166) );
OAI21XLTS U2829 ( .A0(intDY_EWSW[55]), .A1(n4245), .B0(intDY_EWSW[54]), .Y(
n2163) );
OAI2BB2XLTS U2830 ( .B0(intDX_EWSW[54]), .B1(n2163), .A0N(intDY_EWSW[55]),
.A1N(n4245), .Y(n2165) );
OAI31X1TS U2831 ( .A0(n2167), .A1(n2166), .A2(n2165), .B0(n2164), .Y(n2168)
);
OAI221XLTS U2832 ( .A0(n2172), .A1(n2171), .B0(n2170), .B1(n2169), .C0(n2168), .Y(n2173) );
CLKBUFX2TS U2833 ( .A(n1917), .Y(n2424) );
CLKBUFX2TS U2834 ( .A(n2492), .Y(n3997) );
CLKBUFX2TS U2835 ( .A(n2635), .Y(n2434) );
CLKBUFX2TS U2836 ( .A(n2434), .Y(n2495) );
AOI22X1TS U2837 ( .A0(intDX_EWSW[2]), .A1(n2495), .B0(DMP_EXP_EWSW[2]), .B1(
n4360), .Y(n2178) );
AOI22X1TS U2838 ( .A0(intDX_EWSW[3]), .A1(n2495), .B0(DMP_EXP_EWSW[3]), .B1(
n1918), .Y(n2179) );
CLKBUFX2TS U2839 ( .A(n2492), .Y(n3998) );
CLKBUFX2TS U2840 ( .A(n3998), .Y(n4000) );
CLKBUFX2TS U2841 ( .A(n1917), .Y(n2634) );
AOI22X1TS U2842 ( .A0(intDX_EWSW[50]), .A1(n2434), .B0(DMP_EXP_EWSW[50]),
.B1(n2634), .Y(n2180) );
OAI21XLTS U2843 ( .A0(n4205), .A1(n4000), .B0(n2180), .Y(n1625) );
AOI22X1TS U2844 ( .A0(intDX_EWSW[49]), .A1(n2434), .B0(DMP_EXP_EWSW[49]),
.B1(n2634), .Y(n2181) );
OAI21XLTS U2845 ( .A0(n4209), .A1(n4000), .B0(n2181), .Y(n1626) );
INVX2TS U2846 ( .A(n3998), .Y(n2637) );
CLKBUFX2TS U2847 ( .A(n1917), .Y(n3912) );
AOI22X1TS U2848 ( .A0(intDX_EWSW[49]), .A1(n2637), .B0(DmP_EXP_EWSW[49]),
.B1(n3912), .Y(n2182) );
OAI21XLTS U2849 ( .A0(n4209), .A1(n2509), .B0(n2182), .Y(n1300) );
OR2X1TS U2850 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n2256) );
CLKBUFX2TS U2851 ( .A(n2256), .Y(n2553) );
NAND2X1TS U2852 ( .A(n2553), .B(n4210), .Y(n2552) );
NAND2X1TS U2853 ( .A(n4175), .B(shift_value_SHT2_EWR[4]), .Y(n3796) );
INVX2TS U2854 ( .A(n2553), .Y(n3624) );
OR2X1TS U2855 ( .A(shift_value_SHT2_EWR[2]), .B(n4153), .Y(n2326) );
INVX2TS U2856 ( .A(n2326), .Y(n2315) );
AOI22X1TS U2857 ( .A0(Data_array_SWR[19]), .A1(n3624), .B0(
Data_array_SWR[27]), .B1(n2315), .Y(n2184) );
NAND2X1TS U2858 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n2548) );
INVX2TS U2859 ( .A(n2548), .Y(n3645) );
NAND2X1TS U2860 ( .A(n4153), .B(shift_value_SHT2_EWR[2]), .Y(n2327) );
INVX2TS U2861 ( .A(n2327), .Y(n2541) );
CLKBUFX2TS U2862 ( .A(n2541), .Y(n3635) );
AOI22X1TS U2863 ( .A0(Data_array_SWR[31]), .A1(n1930), .B0(
Data_array_SWR[23]), .B1(n3635), .Y(n2183) );
NAND2X1TS U2864 ( .A(n2184), .B(n2183), .Y(n2267) );
NOR2X1TS U2865 ( .A(shift_value_SHT2_EWR[4]), .B(n4175), .Y(n3797) );
INVX2TS U2866 ( .A(n2326), .Y(n3643) );
AOI22X1TS U2867 ( .A0(Data_array_SWR[43]), .A1(n3643), .B0(
Data_array_SWR[35]), .B1(n3624), .Y(n2186) );
AOI22X1TS U2868 ( .A0(Data_array_SWR[47]), .A1(n3645), .B0(
Data_array_SWR[39]), .B1(n2541), .Y(n2185) );
NAND2X1TS U2869 ( .A(n2186), .B(n2185), .Y(n2268) );
AOI22X1TS U2870 ( .A0(n1909), .A1(n2267), .B0(n1932), .B1(n2268), .Y(n2191)
);
NOR2X1TS U2871 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[5]),
.Y(n3792) );
INVX2TS U2872 ( .A(n3792), .Y(n2237) );
NOR2X1TS U2873 ( .A(n2326), .B(n1908), .Y(n3748) );
AOI22X1TS U2874 ( .A0(Data_array_SWR[11]), .A1(n1933), .B0(Data_array_SWR[3]), .B1(n1913), .Y(n2188) );
OAI2BB1X1TS U2875 ( .A0N(n1925), .A1N(Data_array_SWR[7]), .B0(n2188), .Y(
n2189) );
AOI21X1TS U2876 ( .A0(Data_array_SWR[15]), .A1(n1929), .B0(n2189), .Y(n2190)
);
INVX2TS U2877 ( .A(n2192), .Y(n3138) );
NOR2BX1TS U2878 ( .AN(LZD_output_NRM2_EW[5]), .B(ADD_OVRFLW_NRM2), .Y(n2193)
);
NOR2BX1TS U2879 ( .AN(LZD_output_NRM2_EW[4]), .B(ADD_OVRFLW_NRM2), .Y(n2194)
);
NOR2BX1TS U2880 ( .AN(LZD_output_NRM2_EW[3]), .B(ADD_OVRFLW_NRM2), .Y(n2195)
);
NOR2BX1TS U2881 ( .AN(LZD_output_NRM2_EW[2]), .B(ADD_OVRFLW_NRM2), .Y(n2196)
);
NOR2BX1TS U2882 ( .AN(LZD_output_NRM2_EW[1]), .B(ADD_OVRFLW_NRM2), .Y(n2197)
);
XOR2X1TS U2883 ( .A(n1904), .B(n2198), .Y(n2201) );
CMPR32X2TS U2884 ( .A(n2200), .B(DMP_exp_NRM2_EW[3]), .C(n2199), .CO(n2206),
.S(n3901) );
CMPR32X2TS U2885 ( .A(DMP_exp_NRM2_EW[0]), .B(n1904), .C(n2201), .CO(n2204),
.S(n2226) );
INVX2TS U2886 ( .A(n2226), .Y(n3898) );
CMPR32X2TS U2887 ( .A(n2203), .B(DMP_exp_NRM2_EW[2]), .C(n2202), .CO(n2199),
.S(n2227) );
INVX2TS U2888 ( .A(n2227), .Y(n3900) );
CMPR32X2TS U2889 ( .A(n2205), .B(DMP_exp_NRM2_EW[1]), .C(n2204), .CO(n2202),
.S(n2225) );
INVX2TS U2890 ( .A(n2225), .Y(n3899) );
CMPR32X2TS U2891 ( .A(DP_OP_15J2_122_2221_n35), .B(DMP_exp_NRM2_EW[6]), .C(
n2209), .CO(n2213), .S(n2231) );
INVX2TS U2892 ( .A(n2231), .Y(n3904) );
INVX2TS U2893 ( .A(n2230), .Y(n3903) );
ADDFHX1TS U2894 ( .A(DP_OP_15J2_122_2221_n35), .B(DMP_exp_NRM2_EW[8]), .CI(
n2215), .CO(n2217), .S(n3906) );
NOR2BX1TS U2895 ( .AN(n2216), .B(n2223), .Y(n2218) );
ADDFHX1TS U2896 ( .A(DP_OP_15J2_122_2221_n35), .B(DMP_exp_NRM2_EW[9]), .CI(
n2217), .CO(n2219), .S(n2223) );
NOR2BX1TS U2897 ( .AN(n2218), .B(n2222), .Y(n2221) );
ADDFHX1TS U2898 ( .A(DP_OP_15J2_122_2221_n35), .B(DMP_exp_NRM2_EW[10]), .CI(
n2219), .CO(n2220), .S(n2222) );
XNOR2X1TS U2899 ( .A(n2220), .B(ADD_OVRFLW_NRM2), .Y(n2234) );
OAI2BB1X1TS U2900 ( .A0N(n2235), .A1N(n2234), .B0(Shift_reg_FLAGS_7[0]), .Y(
n4012) );
CLKBUFX2TS U2901 ( .A(n1901), .Y(n4011) );
AOI22X1TS U2902 ( .A0(n1928), .A1(n3136), .B0(final_result_ieee[1]), .B1(
n4011), .Y(n2236) );
NAND2X1TS U2903 ( .A(n3645), .B(bit_shift_SHT2), .Y(n2330) );
OAI22X1TS U2904 ( .A0(n4237), .A1(n2256), .B0(n4092), .B1(n2326), .Y(n2238)
);
AOI21X1TS U2905 ( .A0(Data_array_SWR[48]), .A1(n3635), .B0(n2238), .Y(n2239)
);
NAND2X1TS U2906 ( .A(n2330), .B(n2239), .Y(n3730) );
INVX2TS U2907 ( .A(n3730), .Y(n2240) );
NAND2X1TS U2908 ( .A(n2343), .B(n2241), .Y(n3188) );
AOI22X1TS U2909 ( .A0(Data_array_SWR[18]), .A1(n3748), .B0(
Data_array_SWR[14]), .B1(n1924), .Y(n2242) );
NAND2X1TS U2910 ( .A(shift_value_SHT2_EWR[5]), .B(bit_shift_SHT2), .Y(n3793)
);
INVX2TS U2911 ( .A(n3793), .Y(n3798) );
NAND2X1TS U2912 ( .A(shift_value_SHT2_EWR[4]), .B(n3798), .Y(n3751) );
NAND2X1TS U2913 ( .A(n2242), .B(n3751), .Y(n2243) );
AOI21X1TS U2914 ( .A0(Data_array_SWR[22]), .A1(n2187), .B0(n2243), .Y(n2244)
);
INVX2TS U2915 ( .A(n2553), .Y(n3642) );
NAND2X1TS U2916 ( .A(Data_array_SWR[42]), .B(n3642), .Y(n2246) );
AOI22X1TS U2917 ( .A0(Data_array_SWR[46]), .A1(n2541), .B0(
Data_array_SWR[54]), .B1(n3645), .Y(n2245) );
AOI22X1TS U2918 ( .A0(Data_array_SWR[34]), .A1(n2315), .B0(
Data_array_SWR[26]), .B1(n2314), .Y(n2247) );
AOI21X1TS U2919 ( .A0(Data_array_SWR[38]), .A1(n1931), .B0(n2248), .Y(n2312)
);
CLKBUFX2TS U2920 ( .A(n4358), .Y(n3141) );
AOI22X1TS U2921 ( .A0(n1928), .A1(n3186), .B0(final_result_ieee[42]), .B1(
n3141), .Y(n2251) );
OAI22X1TS U2922 ( .A0(n4235), .A1(n2553), .B0(n2327), .B1(n4093), .Y(n2252)
);
AOI21X1TS U2923 ( .A0(Data_array_SWR[54]), .A1(n3643), .B0(n2252), .Y(n2253)
);
NAND2X1TS U2924 ( .A(n2330), .B(n2253), .Y(n3742) );
INVX2TS U2925 ( .A(n3742), .Y(n2254) );
NAND2X1TS U2926 ( .A(n2343), .B(n2255), .Y(n3182) );
AOI22X1TS U2927 ( .A0(Data_array_SWR[20]), .A1(n1929), .B0(Data_array_SWR[8]), .B1(n1913), .Y(n2264) );
AOI22X1TS U2928 ( .A0(Data_array_SWR[16]), .A1(n1933), .B0(
Data_array_SWR[12]), .B1(n1925), .Y(n2263) );
NAND2X1TS U2929 ( .A(Data_array_SWR[44]), .B(n3635), .Y(n2259) );
NAND2X1TS U2930 ( .A(Data_array_SWR[52]), .B(n1930), .Y(n2258) );
INVX2TS U2931 ( .A(n2256), .Y(n3633) );
AOI22X1TS U2932 ( .A0(Data_array_SWR[48]), .A1(n2315), .B0(
Data_array_SWR[40]), .B1(n3633), .Y(n2257) );
AOI22X1TS U2933 ( .A0(Data_array_SWR[32]), .A1(n3643), .B0(
Data_array_SWR[24]), .B1(n3642), .Y(n2260) );
AOI21X1TS U2934 ( .A0(Data_array_SWR[36]), .A1(n1931), .B0(n2261), .Y(n2295)
);
AOI22X1TS U2935 ( .A0(n1928), .A1(n3172), .B0(final_result_ieee[44]), .B1(
n4011), .Y(n2265) );
AOI21X1TS U2936 ( .A0(n2268), .A1(n3792), .B0(n2266), .Y(n3176) );
INVX2TS U2937 ( .A(n3797), .Y(n2549) );
AOI22X1TS U2938 ( .A0(n1902), .A1(n2268), .B0(n3792), .B1(n2267), .Y(n2269)
);
AOI22X1TS U2939 ( .A0(n1928), .A1(n3155), .B0(final_result_ieee[33]), .B1(
n3141), .Y(n2271) );
NAND2X1TS U2940 ( .A(shift_value_SHT2_EWR[3]), .B(bit_shift_SHT2), .Y(n2544)
);
NAND2X1TS U2941 ( .A(Data_array_SWR[47]), .B(n3642), .Y(n2272) );
INVX2TS U2942 ( .A(n3749), .Y(n2274) );
NAND2X1TS U2943 ( .A(n2343), .B(n2275), .Y(n3169) );
AOI22X1TS U2944 ( .A0(Data_array_SWR[19]), .A1(n1929), .B0(Data_array_SWR[7]), .B1(n1913), .Y(n2283) );
AOI22X1TS U2945 ( .A0(Data_array_SWR[15]), .A1(n1933), .B0(
Data_array_SWR[11]), .B1(n1925), .Y(n2282) );
NAND2X1TS U2946 ( .A(Data_array_SWR[43]), .B(n3635), .Y(n2278) );
NAND2X1TS U2947 ( .A(Data_array_SWR[51]), .B(n3645), .Y(n2277) );
INVX2TS U2948 ( .A(n2326), .Y(n3634) );
AOI22X1TS U2949 ( .A0(Data_array_SWR[47]), .A1(n3634), .B0(
Data_array_SWR[39]), .B1(n3633), .Y(n2276) );
CLKBUFX2TS U2950 ( .A(n2541), .Y(n3644) );
AOI22X1TS U2951 ( .A0(Data_array_SWR[31]), .A1(n3643), .B0(
Data_array_SWR[23]), .B1(n3642), .Y(n2279) );
OAI2BB1X1TS U2952 ( .A0N(Data_array_SWR[27]), .A1N(n3644), .B0(n2279), .Y(
n2280) );
AOI21X1TS U2953 ( .A0(Data_array_SWR[35]), .A1(n1930), .B0(n2280), .Y(n2320)
);
AOI22X1TS U2954 ( .A0(n3130), .A1(n3157), .B0(final_result_ieee[45]), .B1(
n4011), .Y(n2284) );
AOI22X1TS U2955 ( .A0(Data_array_SWR[18]), .A1(n3624), .B0(
Data_array_SWR[26]), .B1(n2315), .Y(n2285) );
AOI21X1TS U2956 ( .A0(Data_array_SWR[30]), .A1(n1930), .B0(n2286), .Y(n3817)
);
AOI22X1TS U2957 ( .A0(Data_array_SWR[50]), .A1(n3642), .B0(
Data_array_SWR[54]), .B1(n3635), .Y(n2287) );
NAND2X1TS U2958 ( .A(n2287), .B(n2544), .Y(n3871) );
INVX2TS U2959 ( .A(n3871), .Y(n3812) );
AOI22X1TS U2960 ( .A0(Data_array_SWR[42]), .A1(n3634), .B0(
Data_array_SWR[34]), .B1(n3624), .Y(n2288) );
OAI2BB1X1TS U2961 ( .A0N(Data_array_SWR[38]), .A1N(n3644), .B0(n2288), .Y(
n2289) );
OAI22X1TS U2962 ( .A0(n3812), .A1(n3640), .B0(n3811), .B1(n2549), .Y(n2292)
);
AOI22X1TS U2963 ( .A0(Data_array_SWR[14]), .A1(n2187), .B0(Data_array_SWR[6]), .B1(n1925), .Y(n2291) );
AOI22X1TS U2964 ( .A0(Data_array_SWR[10]), .A1(n1933), .B0(Data_array_SWR[2]), .B1(n1913), .Y(n2290) );
AOI22X1TS U2965 ( .A0(n1928), .A1(n3162), .B0(final_result_ieee[0]), .B1(
n4011), .Y(n2294) );
AOI21X1TS U2966 ( .A0(n1909), .A1(n3852), .B0(n2296), .Y(n3177) );
AOI22X1TS U2967 ( .A0(Data_array_SWR[38]), .A1(n2315), .B0(
Data_array_SWR[30]), .B1(n3633), .Y(n2298) );
AOI22X1TS U2968 ( .A0(Data_array_SWR[42]), .A1(n1931), .B0(
Data_array_SWR[34]), .B1(n2541), .Y(n2297) );
NAND2X1TS U2969 ( .A(n2298), .B(n2297), .Y(n3743) );
AOI22X1TS U2970 ( .A0(n1909), .A1(n3742), .B0(n3792), .B1(n3743), .Y(n2299)
);
NAND2X1TS U2971 ( .A(n2299), .B(n3793), .Y(n3159) );
CLKBUFX2TS U2972 ( .A(n1901), .Y(n3914) );
AOI22X1TS U2973 ( .A0(n3130), .A1(n3159), .B0(final_result_ieee[22]), .B1(
n3914), .Y(n2300) );
AOI22X1TS U2974 ( .A0(Data_array_SWR[49]), .A1(n2315), .B0(
Data_array_SWR[41]), .B1(n2314), .Y(n2302) );
AOI22X1TS U2975 ( .A0(Data_array_SWR[45]), .A1(n2541), .B0(
Data_array_SWR[53]), .B1(n1931), .Y(n2301) );
NAND2X1TS U2976 ( .A(n2302), .B(n2301), .Y(n3856) );
AOI22X1TS U2977 ( .A0(Data_array_SWR[33]), .A1(n3643), .B0(
Data_array_SWR[25]), .B1(n3642), .Y(n2303) );
AOI21X1TS U2978 ( .A0(Data_array_SWR[37]), .A1(n1931), .B0(n2304), .Y(n2344)
);
AOI21X1TS U2979 ( .A0(n3856), .A1(n1909), .B0(n2305), .Y(n3163) );
AOI22X1TS U2980 ( .A0(Data_array_SWR[49]), .A1(n3644), .B0(
Data_array_SWR[45]), .B1(n3633), .Y(n2307) );
NAND2X1TS U2981 ( .A(Data_array_SWR[53]), .B(n3643), .Y(n2306) );
AOI22X1TS U2982 ( .A0(Data_array_SWR[37]), .A1(n2315), .B0(
Data_array_SWR[29]), .B1(n3633), .Y(n2309) );
AOI22X1TS U2983 ( .A0(Data_array_SWR[41]), .A1(n1930), .B0(
Data_array_SWR[33]), .B1(n2541), .Y(n2308) );
NAND2X1TS U2984 ( .A(n2309), .B(n2308), .Y(n3737) );
AOI22X1TS U2985 ( .A0(n1909), .A1(n3736), .B0(n3792), .B1(n3737), .Y(n2310)
);
NAND2X1TS U2986 ( .A(n2310), .B(n3793), .Y(n3154) );
AOI22X1TS U2987 ( .A0(n1928), .A1(n3154), .B0(final_result_ieee[23]), .B1(
n3141), .Y(n2311) );
AOI22X1TS U2988 ( .A0(Data_array_SWR[36]), .A1(n2315), .B0(
Data_array_SWR[28]), .B1(n2314), .Y(n2317) );
AOI22X1TS U2989 ( .A0(Data_array_SWR[40]), .A1(n3645), .B0(
Data_array_SWR[32]), .B1(n2541), .Y(n2316) );
NAND2X1TS U2990 ( .A(n2317), .B(n2316), .Y(n3731) );
AOI22X1TS U2991 ( .A0(n1909), .A1(n3730), .B0(n3792), .B1(n3731), .Y(n2318)
);
NAND2X1TS U2992 ( .A(n2318), .B(n3793), .Y(n3161) );
AOI22X1TS U2993 ( .A0(n1928), .A1(n3161), .B0(final_result_ieee[24]), .B1(
n3914), .Y(n2319) );
AOI21X1TS U2994 ( .A0(n1909), .A1(n3849), .B0(n2321), .Y(n3179) );
AOI22X1TS U2995 ( .A0(Data_array_SWR[39]), .A1(n3634), .B0(
Data_array_SWR[31]), .B1(n3633), .Y(n2323) );
AOI22X1TS U2996 ( .A0(Data_array_SWR[43]), .A1(n1931), .B0(
Data_array_SWR[35]), .B1(n3644), .Y(n2322) );
NAND2X1TS U2997 ( .A(n2323), .B(n2322), .Y(n3750) );
AOI22X1TS U2998 ( .A0(n1909), .A1(n3749), .B0(n3792), .B1(n3750), .Y(n2324)
);
NAND2X1TS U2999 ( .A(n2324), .B(n3793), .Y(n3160) );
AOI22X1TS U3000 ( .A0(n1928), .A1(n3160), .B0(final_result_ieee[21]), .B1(
n3914), .Y(n2325) );
OAI22X1TS U3001 ( .A0(n4232), .A1(n2327), .B0(n4091), .B1(n2326), .Y(n2328)
);
AOI21X1TS U3002 ( .A0(Data_array_SWR[43]), .A1(n3624), .B0(n2328), .Y(n2329)
);
NAND2X1TS U3003 ( .A(n2330), .B(n2329), .Y(n2337) );
INVX2TS U3004 ( .A(n2337), .Y(n3795) );
NAND2X1TS U3005 ( .A(n2343), .B(n2331), .Y(n3195) );
INVX2TS U3006 ( .A(n2187), .Y(n2333) );
AOI22X1TS U3007 ( .A0(Data_array_SWR[19]), .A1(n3748), .B0(
Data_array_SWR[15]), .B1(n1925), .Y(n2332) );
AOI21X1TS U3008 ( .A0(Data_array_SWR[11]), .A1(n1913), .B0(n2334), .Y(n2339)
);
AOI22X1TS U3009 ( .A0(Data_array_SWR[35]), .A1(n3643), .B0(
Data_array_SWR[27]), .B1(n3624), .Y(n2336) );
AOI22X1TS U3010 ( .A0(Data_array_SWR[39]), .A1(n3645), .B0(
Data_array_SWR[31]), .B1(n2541), .Y(n2335) );
NAND2X1TS U3011 ( .A(n2336), .B(n2335), .Y(n3791) );
AOI22X1TS U3012 ( .A0(n1909), .A1(n3791), .B0(n1932), .B1(n2337), .Y(n2338)
);
NAND2X1TS U3013 ( .A(n2339), .B(n2338), .Y(n3189) );
AOI22X1TS U3014 ( .A0(n1928), .A1(n3189), .B0(final_result_ieee[41]), .B1(
n3141), .Y(n2340) );
INVX2TS U3015 ( .A(n3736), .Y(n2341) );
NAND2X1TS U3016 ( .A(n2343), .B(n2342), .Y(n3171) );
AOI22X1TS U3017 ( .A0(Data_array_SWR[21]), .A1(n1929), .B0(Data_array_SWR[9]), .B1(n1913), .Y(n2347) );
AOI22X1TS U3018 ( .A0(Data_array_SWR[17]), .A1(n1933), .B0(
Data_array_SWR[13]), .B1(n1925), .Y(n2346) );
AOI22X1TS U3019 ( .A0(n1928), .A1(n3158), .B0(final_result_ieee[43]), .B1(
n3141), .Y(n2348) );
AOI22X1TS U3020 ( .A0(DMP_EXP_EWSW[57]), .A1(n3912), .B0(intDX_EWSW[57]),
.B1(n2495), .Y(n2349) );
OAI21XLTS U3021 ( .A0(n4206), .A1(n4000), .B0(n2349), .Y(n1618) );
AOI22X1TS U3022 ( .A0(intDX_EWSW[50]), .A1(n2637), .B0(DmP_EXP_EWSW[50]),
.B1(n3912), .Y(n2350) );
OAI21XLTS U3023 ( .A0(n4205), .A1(n2509), .B0(n2350), .Y(n1298) );
AOI22X1TS U3024 ( .A0(intDX_EWSW[0]), .A1(n2635), .B0(DMP_EXP_EWSW[0]), .B1(
n4360), .Y(n2351) );
OAI21XLTS U3025 ( .A0(n4170), .A1(n4000), .B0(n2351), .Y(n1675) );
INVX2TS U3026 ( .A(n3997), .Y(n2642) );
CLKBUFX2TS U3027 ( .A(n1917), .Y(n2641) );
AOI22X1TS U3028 ( .A0(intDX_EWSW[0]), .A1(n2642), .B0(DmP_EXP_EWSW[0]), .B1(
n2641), .Y(n2352) );
OAI21XLTS U3029 ( .A0(n4170), .A1(n2644), .B0(n2352), .Y(n1398) );
NOR2X1TS U3030 ( .A(Raw_mant_NRM_SWR[46]), .B(Raw_mant_NRM_SWR[45]), .Y(
n2746) );
NAND2X1TS U3031 ( .A(n4113), .B(n2746), .Y(n2692) );
NOR3X1TS U3032 ( .A(n2692), .B(Raw_mant_NRM_SWR[47]), .C(
Raw_mant_NRM_SWR[43]), .Y(n2353) );
NAND2X1TS U3033 ( .A(n2751), .B(n2752), .Y(n2675) );
NAND2X1TS U3034 ( .A(n4114), .B(n2747), .Y(n2672) );
NAND2X1TS U3035 ( .A(n2699), .B(n4152), .Y(n2362) );
OR2X1TS U3036 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[7]), .Y(n2370)
);
AOI21X1TS U3037 ( .A0(n2375), .A1(n4224), .B0(n2656), .Y(n2368) );
OR4X2TS U3038 ( .A(Raw_mant_NRM_SWR[14]), .B(Raw_mant_NRM_SWR[17]), .C(
Raw_mant_NRM_SWR[18]), .D(Raw_mant_NRM_SWR[16]), .Y(n2364) );
AOI22X1TS U3039 ( .A0(n2666), .A1(Raw_mant_NRM_SWR[10]), .B0(n2365), .B1(
n2364), .Y(n2366) );
AOI211XLTS U3040 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n2689), .B0(n2368), .C0(
n2367), .Y(n2380) );
NAND2X1TS U3041 ( .A(n2370), .B(n4072), .Y(n2372) );
OAI21X1TS U3042 ( .A0(n2703), .A1(n2372), .B0(n2371), .Y(n2373) );
AOI21X1TS U3043 ( .A0(n2645), .A1(n2374), .B0(n2373), .Y(n2765) );
NAND2X1TS U3044 ( .A(n2376), .B(n2375), .Y(n2377) );
NOR3XLTS U3045 ( .A(n4174), .B(Raw_mant_NRM_SWR[2]), .C(Raw_mant_NRM_SWR[1]),
.Y(n2378) );
NAND2X1TS U3046 ( .A(n2739), .B(n2378), .Y(n2723) );
NAND2X1TS U3047 ( .A(n2739), .B(n2379), .Y(n2784) );
CLKBUFX2TS U3048 ( .A(n4356), .Y(n3197) );
CLKBUFX2TS U3049 ( .A(n4262), .Y(n3980) );
INVX2TS U3050 ( .A(n3980), .Y(n3205) );
INVX2TS U3051 ( .A(n2381), .Y(n3153) );
INVX2TS U3052 ( .A(n3153), .Y(n3889) );
NOR2XLTS U3053 ( .A(n1920), .B(n3889), .Y(n2741) );
AOI222XLTS U3054 ( .A0(n3886), .A1(n3890), .B0(n2741), .B1(
Shift_amount_SHT1_EWR[5]), .C0(n2381), .C1(shift_value_SHT2_EWR[5]),
.Y(n2382) );
CLKBUFX2TS U3055 ( .A(n3998), .Y(n2454) );
CLKBUFX2TS U3056 ( .A(n2434), .Y(n2452) );
AOI22X1TS U3057 ( .A0(intDX_EWSW[9]), .A1(n2452), .B0(DMP_EXP_EWSW[9]), .B1(
n4360), .Y(n2383) );
OAI21XLTS U3058 ( .A0(n4163), .A1(n2454), .B0(n2383), .Y(n1666) );
CLKBUFX2TS U3059 ( .A(n3998), .Y(n2433) );
CLKBUFX2TS U3060 ( .A(n2434), .Y(n2431) );
CLKBUFX2TS U3061 ( .A(n2424), .Y(n2451) );
AOI22X1TS U3062 ( .A0(intDX_EWSW[22]), .A1(n2431), .B0(DMP_EXP_EWSW[22]),
.B1(n2451), .Y(n2384) );
OAI21XLTS U3063 ( .A0(n4217), .A1(n2433), .B0(n2384), .Y(n1653) );
AOI22X1TS U3064 ( .A0(intDX_EWSW[12]), .A1(n2452), .B0(DMP_EXP_EWSW[12]),
.B1(n1918), .Y(n2385) );
OAI21XLTS U3065 ( .A0(n4164), .A1(n2454), .B0(n2385), .Y(n1663) );
AOI22X1TS U3066 ( .A0(intDX_EWSW[13]), .A1(n2452), .B0(DMP_EXP_EWSW[13]),
.B1(n2451), .Y(n2386) );
OAI21XLTS U3067 ( .A0(n4160), .A1(n2454), .B0(n2386), .Y(n1662) );
AOI22X1TS U3068 ( .A0(intDX_EWSW[14]), .A1(n2452), .B0(DMP_EXP_EWSW[14]),
.B1(n2451), .Y(n2387) );
OAI21XLTS U3069 ( .A0(n4216), .A1(n2454), .B0(n2387), .Y(n1661) );
AOI22X1TS U3070 ( .A0(intDX_EWSW[26]), .A1(n2431), .B0(DMP_EXP_EWSW[26]),
.B1(n2424), .Y(n2388) );
OAI21XLTS U3071 ( .A0(n4168), .A1(n2433), .B0(n2388), .Y(n1649) );
AOI22X1TS U3072 ( .A0(intDX_EWSW[24]), .A1(n2431), .B0(DMP_EXP_EWSW[24]),
.B1(n2424), .Y(n2389) );
OAI21XLTS U3073 ( .A0(n4169), .A1(n2433), .B0(n2389), .Y(n1651) );
CLKBUFX2TS U3074 ( .A(n3998), .Y(n2505) );
CLKBUFX2TS U3075 ( .A(n2434), .Y(n2503) );
AOI22X1TS U3076 ( .A0(intDX_EWSW[31]), .A1(n2503), .B0(DMP_EXP_EWSW[31]),
.B1(n2424), .Y(n2390) );
OAI21XLTS U3077 ( .A0(n4088), .A1(n2505), .B0(n2390), .Y(n1644) );
AOI22X1TS U3078 ( .A0(intDX_EWSW[18]), .A1(n2452), .B0(DMP_EXP_EWSW[18]),
.B1(n2451), .Y(n2391) );
OAI21XLTS U3079 ( .A0(n4167), .A1(n2454), .B0(n2391), .Y(n1657) );
AOI22X1TS U3080 ( .A0(intDX_EWSW[11]), .A1(n2452), .B0(DMP_EXP_EWSW[11]),
.B1(n2424), .Y(n2392) );
OAI21XLTS U3081 ( .A0(n4085), .A1(n2454), .B0(n2392), .Y(n1664) );
AOI22X1TS U3082 ( .A0(intDX_EWSW[17]), .A1(n2452), .B0(DMP_EXP_EWSW[17]),
.B1(n2451), .Y(n2393) );
OAI21XLTS U3083 ( .A0(n4066), .A1(n2454), .B0(n2393), .Y(n1658) );
AOI22X1TS U3084 ( .A0(intDX_EWSW[21]), .A1(n2431), .B0(DMP_EXP_EWSW[21]),
.B1(n2451), .Y(n2394) );
OAI21XLTS U3085 ( .A0(n4161), .A1(n2433), .B0(n2394), .Y(n1654) );
AOI22X1TS U3086 ( .A0(intDX_EWSW[20]), .A1(n2431), .B0(DMP_EXP_EWSW[20]),
.B1(n2451), .Y(n2395) );
OAI21XLTS U3087 ( .A0(n4165), .A1(n2433), .B0(n2395), .Y(n1655) );
AOI22X1TS U3088 ( .A0(intDX_EWSW[28]), .A1(n2431), .B0(DMP_EXP_EWSW[28]),
.B1(n2424), .Y(n2396) );
OAI21XLTS U3089 ( .A0(n4166), .A1(n2433), .B0(n2396), .Y(n1647) );
AOI22X1TS U3090 ( .A0(intDX_EWSW[19]), .A1(n2452), .B0(DMP_EXP_EWSW[19]),
.B1(n2451), .Y(n2397) );
OAI21XLTS U3091 ( .A0(n4068), .A1(n2454), .B0(n2397), .Y(n1656) );
AOI22X1TS U3092 ( .A0(intDX_EWSW[23]), .A1(n2431), .B0(DMP_EXP_EWSW[23]),
.B1(n2424), .Y(n2398) );
OAI21XLTS U3093 ( .A0(n4087), .A1(n2433), .B0(n2398), .Y(n1652) );
AOI22X1TS U3094 ( .A0(intDX_EWSW[15]), .A1(n2452), .B0(DMP_EXP_EWSW[15]),
.B1(n2451), .Y(n2399) );
OAI21XLTS U3095 ( .A0(n4086), .A1(n2454), .B0(n2399), .Y(n1660) );
INVX2TS U3096 ( .A(n3998), .Y(n2466) );
CLKBUFX2TS U3097 ( .A(n1917), .Y(n2519) );
AOI22X1TS U3098 ( .A0(intDX_EWSW[23]), .A1(n2466), .B0(DmP_EXP_EWSW[23]),
.B1(n2519), .Y(n2400) );
OAI21XLTS U3099 ( .A0(n4087), .A1(n2445), .B0(n2400), .Y(n1352) );
AOI22X1TS U3100 ( .A0(intDX_EWSW[2]), .A1(n2642), .B0(DmP_EXP_EWSW[2]), .B1(
n2641), .Y(n2401) );
INVX2TS U3101 ( .A(n3997), .Y(n2516) );
AOI22X1TS U3102 ( .A0(intDX_EWSW[3]), .A1(n2516), .B0(DmP_EXP_EWSW[3]), .B1(
n2641), .Y(n2402) );
CLKBUFX2TS U3103 ( .A(n1917), .Y(n2515) );
AOI22X1TS U3104 ( .A0(intDX_EWSW[7]), .A1(n2516), .B0(DmP_EXP_EWSW[7]), .B1(
n2515), .Y(n2403) );
AOI22X1TS U3105 ( .A0(intDX_EWSW[5]), .A1(n2516), .B0(DmP_EXP_EWSW[5]), .B1(
n2515), .Y(n2404) );
AOI22X1TS U3106 ( .A0(DmP_EXP_EWSW[57]), .A1(n3912), .B0(intDX_EWSW[57]),
.B1(n2642), .Y(n2405) );
OAI21XLTS U3107 ( .A0(n4206), .A1(n2445), .B0(n2405), .Y(n1289) );
CLKBUFX2TS U3108 ( .A(n3347), .Y(n3669) );
ADDFHX2TS U3109 ( .A(DMP_SFG[51]), .B(DmP_mant_SFG_SWR[53]), .CI(n2408),
.CO(n3883), .S(n2409) );
CLKBUFX2TS U3110 ( .A(n3884), .Y(n3573) );
CLKBUFX2TS U3111 ( .A(n1914), .Y(n3685) );
AOI22X1TS U3112 ( .A0(n2409), .A1(n3573), .B0(Raw_mant_NRM_SWR[53]), .B1(
n3685), .Y(n2410) );
AOI2BB2XLTS U3113 ( .B0(beg_OP), .B1(n4079), .A0N(n4079), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n2412) );
CLKBUFX2TS U3114 ( .A(n3998), .Y(n2500) );
CLKBUFX2TS U3115 ( .A(n2635), .Y(n2498) );
CLKBUFX2TS U3116 ( .A(n1917), .Y(n2502) );
AOI22X1TS U3117 ( .A0(intDX_EWSW[39]), .A1(n2498), .B0(DMP_EXP_EWSW[39]),
.B1(n2502), .Y(n2413) );
OAI21XLTS U3118 ( .A0(n4199), .A1(n2500), .B0(n2413), .Y(n1636) );
AOI22X1TS U3119 ( .A0(intDX_EWSW[41]), .A1(n2498), .B0(DMP_EXP_EWSW[41]),
.B1(n2502), .Y(n2414) );
OAI21XLTS U3120 ( .A0(n4084), .A1(n2500), .B0(n2414), .Y(n1634) );
AOI22X1TS U3121 ( .A0(intDX_EWSW[42]), .A1(n2498), .B0(DMP_EXP_EWSW[42]),
.B1(n2502), .Y(n2415) );
OAI21XLTS U3122 ( .A0(n4197), .A1(n2500), .B0(n2415), .Y(n1633) );
AOI22X1TS U3123 ( .A0(intDX_EWSW[30]), .A1(n2503), .B0(DMP_EXP_EWSW[30]),
.B1(n1918), .Y(n2416) );
OAI21XLTS U3124 ( .A0(n4218), .A1(n2505), .B0(n2416), .Y(n1645) );
AOI22X1TS U3125 ( .A0(intDX_EWSW[43]), .A1(n2498), .B0(DMP_EXP_EWSW[43]),
.B1(n2634), .Y(n2417) );
OAI21XLTS U3126 ( .A0(n4082), .A1(n2500), .B0(n2417), .Y(n1632) );
AOI22X1TS U3127 ( .A0(intDX_EWSW[29]), .A1(n2503), .B0(DMP_EXP_EWSW[29]),
.B1(n2424), .Y(n2418) );
OAI21XLTS U3128 ( .A0(n4065), .A1(n2433), .B0(n2418), .Y(n1646) );
AOI22X1TS U3129 ( .A0(intDX_EWSW[36]), .A1(n2503), .B0(DMP_EXP_EWSW[36]),
.B1(n2502), .Y(n2419) );
OAI21XLTS U3130 ( .A0(n4194), .A1(n2505), .B0(n2419), .Y(n1639) );
AOI22X1TS U3131 ( .A0(intDX_EWSW[40]), .A1(n2431), .B0(DMP_EXP_EWSW[40]),
.B1(n2502), .Y(n2420) );
OAI21XLTS U3132 ( .A0(n4200), .A1(n2500), .B0(n2420), .Y(n1635) );
AOI22X1TS U3133 ( .A0(intDX_EWSW[35]), .A1(n2503), .B0(DMP_EXP_EWSW[35]),
.B1(n1918), .Y(n2421) );
OAI21XLTS U3134 ( .A0(n4081), .A1(n2505), .B0(n2421), .Y(n1640) );
AOI22X1TS U3135 ( .A0(intDX_EWSW[34]), .A1(n2503), .B0(DMP_EXP_EWSW[34]),
.B1(n2502), .Y(n2422) );
OAI21XLTS U3136 ( .A0(n4196), .A1(n2505), .B0(n2422), .Y(n1641) );
AOI22X1TS U3137 ( .A0(intDX_EWSW[33]), .A1(n2503), .B0(DMP_EXP_EWSW[33]),
.B1(n2502), .Y(n2423) );
OAI21XLTS U3138 ( .A0(n4192), .A1(n2505), .B0(n2423), .Y(n1642) );
AOI22X1TS U3139 ( .A0(intDX_EWSW[32]), .A1(n2503), .B0(DMP_EXP_EWSW[32]),
.B1(n2424), .Y(n2425) );
OAI21XLTS U3140 ( .A0(n4172), .A1(n2505), .B0(n2425), .Y(n1643) );
AOI22X1TS U3141 ( .A0(intDX_EWSW[45]), .A1(n2498), .B0(DMP_EXP_EWSW[45]),
.B1(n2502), .Y(n2426) );
OAI21XLTS U3142 ( .A0(n4193), .A1(n2500), .B0(n2426), .Y(n1630) );
AOI22X1TS U3143 ( .A0(intDX_EWSW[46]), .A1(n2498), .B0(DMP_EXP_EWSW[46]),
.B1(n2634), .Y(n2427) );
OAI21XLTS U3144 ( .A0(n4083), .A1(n2500), .B0(n2427), .Y(n1629) );
AOI22X1TS U3145 ( .A0(intDX_EWSW[47]), .A1(n2498), .B0(DMP_EXP_EWSW[47]),
.B1(n2634), .Y(n2428) );
OAI21XLTS U3146 ( .A0(n4201), .A1(n2500), .B0(n2428), .Y(n1628) );
AOI22X1TS U3147 ( .A0(intDX_EWSW[27]), .A1(n2431), .B0(DMP_EXP_EWSW[27]),
.B1(n1918), .Y(n2429) );
OAI21XLTS U3148 ( .A0(n4069), .A1(n2433), .B0(n2429), .Y(n1648) );
AOI22X1TS U3149 ( .A0(intDX_EWSW[10]), .A1(n2495), .B0(DMP_EXP_EWSW[10]),
.B1(n1918), .Y(n2430) );
OAI21XLTS U3150 ( .A0(n4162), .A1(n2505), .B0(n2430), .Y(n1665) );
AOI22X1TS U3151 ( .A0(intDX_EWSW[25]), .A1(n2431), .B0(DMP_EXP_EWSW[25]),
.B1(n2634), .Y(n2432) );
OAI21XLTS U3152 ( .A0(n4067), .A1(n2433), .B0(n2432), .Y(n1650) );
INVX2TS U3153 ( .A(n3998), .Y(n2511) );
CLKBUFX2TS U3154 ( .A(n1917), .Y(n2464) );
AOI22X1TS U3155 ( .A0(intDX_EWSW[31]), .A1(n2511), .B0(DmP_EXP_EWSW[31]),
.B1(n2464), .Y(n2435) );
OAI21XLTS U3156 ( .A0(n4088), .A1(n2513), .B0(n2435), .Y(n1336) );
AOI22X1TS U3157 ( .A0(intDX_EWSW[22]), .A1(n2466), .B0(DmP_EXP_EWSW[22]),
.B1(n2519), .Y(n2436) );
OAI21XLTS U3158 ( .A0(n4217), .A1(n2445), .B0(n2436), .Y(n1354) );
AOI22X1TS U3159 ( .A0(intDX_EWSW[30]), .A1(n2466), .B0(DmP_EXP_EWSW[30]),
.B1(n2464), .Y(n2437) );
OAI21XLTS U3160 ( .A0(n4218), .A1(n2445), .B0(n2437), .Y(n1338) );
AOI22X1TS U3161 ( .A0(intDX_EWSW[26]), .A1(n2466), .B0(DmP_EXP_EWSW[26]),
.B1(n2464), .Y(n2438) );
OAI21XLTS U3162 ( .A0(n4168), .A1(n2445), .B0(n2438), .Y(n1346) );
AOI22X1TS U3163 ( .A0(intDX_EWSW[25]), .A1(n2466), .B0(DmP_EXP_EWSW[25]),
.B1(n2641), .Y(n2439) );
OAI21XLTS U3164 ( .A0(n4067), .A1(n2445), .B0(n2439), .Y(n1348) );
AOI22X1TS U3165 ( .A0(intDX_EWSW[28]), .A1(n2466), .B0(DmP_EXP_EWSW[28]),
.B1(n2464), .Y(n2440) );
OAI21XLTS U3166 ( .A0(n4166), .A1(n2445), .B0(n2440), .Y(n1342) );
AOI22X1TS U3167 ( .A0(intDX_EWSW[27]), .A1(n2466), .B0(DmP_EXP_EWSW[27]),
.B1(n2464), .Y(n2441) );
OAI21XLTS U3168 ( .A0(n4069), .A1(n2445), .B0(n2441), .Y(n1344) );
AOI22X1TS U3169 ( .A0(intDX_EWSW[29]), .A1(n2466), .B0(DmP_EXP_EWSW[29]),
.B1(n2464), .Y(n2442) );
OAI21XLTS U3170 ( .A0(n4065), .A1(n2445), .B0(n2442), .Y(n1340) );
AOI222XLTS U3171 ( .A0(n2642), .A1(intDX_EWSW[52]), .B0(DmP_EXP_EWSW[52]),
.B1(n2424), .C0(intDY_EWSW[52]), .C1(n2635), .Y(n2443) );
AOI22X1TS U3172 ( .A0(intDX_EWSW[24]), .A1(n2466), .B0(DmP_EXP_EWSW[24]),
.B1(n2464), .Y(n2444) );
OAI21XLTS U3173 ( .A0(n4169), .A1(n2445), .B0(n2444), .Y(n1350) );
INVX2TS U3174 ( .A(n3997), .Y(n2520) );
AOI22X1TS U3175 ( .A0(intDX_EWSW[15]), .A1(n2520), .B0(DmP_EXP_EWSW[15]),
.B1(n2519), .Y(n2446) );
OAI21XLTS U3176 ( .A0(n4086), .A1(n2522), .B0(n2446), .Y(n1368) );
AOI22X1TS U3177 ( .A0(intDX_EWSW[14]), .A1(n2520), .B0(DmP_EXP_EWSW[14]),
.B1(n2519), .Y(n2447) );
OAI21XLTS U3178 ( .A0(n4216), .A1(n2522), .B0(n2447), .Y(n1370) );
AOI22X1TS U3179 ( .A0(intDX_EWSW[11]), .A1(n2516), .B0(DmP_EXP_EWSW[11]),
.B1(n2515), .Y(n2448) );
OAI21XLTS U3180 ( .A0(n4085), .A1(n2518), .B0(n2448), .Y(n1376) );
AOI22X1TS U3181 ( .A0(intDX_EWSW[12]), .A1(n2520), .B0(DmP_EXP_EWSW[12]),
.B1(n2515), .Y(n2449) );
OAI21XLTS U3182 ( .A0(n4164), .A1(n2522), .B0(n2449), .Y(n1374) );
AOI222XLTS U3183 ( .A0(n2635), .A1(intDX_EWSW[52]), .B0(DMP_EXP_EWSW[52]),
.B1(n4360), .C0(intDY_EWSW[52]), .C1(n2642), .Y(n2450) );
AOI22X1TS U3184 ( .A0(intDX_EWSW[16]), .A1(n2452), .B0(DMP_EXP_EWSW[16]),
.B1(n2451), .Y(n2453) );
OAI21XLTS U3185 ( .A0(n4191), .A1(n2454), .B0(n2453), .Y(n1659) );
CLKBUFX2TS U3186 ( .A(n1917), .Y(n2510) );
AOI22X1TS U3187 ( .A0(intDX_EWSW[43]), .A1(n2637), .B0(DmP_EXP_EWSW[43]),
.B1(n2510), .Y(n2455) );
OAI21XLTS U3188 ( .A0(n4082), .A1(n2509), .B0(n2455), .Y(n1312) );
AOI22X1TS U3189 ( .A0(intDX_EWSW[35]), .A1(n2511), .B0(DmP_EXP_EWSW[35]),
.B1(n2464), .Y(n2456) );
OAI21XLTS U3190 ( .A0(n4081), .A1(n2513), .B0(n2456), .Y(n1328) );
AOI22X1TS U3191 ( .A0(intDX_EWSW[45]), .A1(n2637), .B0(DmP_EXP_EWSW[45]),
.B1(n2510), .Y(n2457) );
OAI21XLTS U3192 ( .A0(n4193), .A1(n2509), .B0(n2457), .Y(n1308) );
AOI22X1TS U3193 ( .A0(intDX_EWSW[33]), .A1(n2511), .B0(DmP_EXP_EWSW[33]),
.B1(n2464), .Y(n2458) );
OAI21XLTS U3194 ( .A0(n4192), .A1(n2513), .B0(n2458), .Y(n1332) );
AOI22X1TS U3195 ( .A0(intDX_EWSW[36]), .A1(n2511), .B0(DmP_EXP_EWSW[36]),
.B1(n2510), .Y(n2459) );
OAI21XLTS U3196 ( .A0(n4194), .A1(n2513), .B0(n2459), .Y(n1326) );
AOI22X1TS U3197 ( .A0(intDX_EWSW[34]), .A1(n2511), .B0(DmP_EXP_EWSW[34]),
.B1(n2510), .Y(n2460) );
OAI21XLTS U3198 ( .A0(n4196), .A1(n2513), .B0(n2460), .Y(n1330) );
AOI22X1TS U3199 ( .A0(intDX_EWSW[42]), .A1(n2637), .B0(DmP_EXP_EWSW[42]),
.B1(n2510), .Y(n2461) );
OAI21XLTS U3200 ( .A0(n4197), .A1(n2509), .B0(n2461), .Y(n1314) );
AOI22X1TS U3201 ( .A0(intDX_EWSW[41]), .A1(n2511), .B0(DmP_EXP_EWSW[41]),
.B1(n2510), .Y(n2462) );
OAI21XLTS U3202 ( .A0(n4084), .A1(n2509), .B0(n2462), .Y(n1316) );
AOI22X1TS U3203 ( .A0(intDX_EWSW[46]), .A1(n2637), .B0(DmP_EXP_EWSW[46]),
.B1(n3912), .Y(n2463) );
OAI21XLTS U3204 ( .A0(n4083), .A1(n2509), .B0(n2463), .Y(n1306) );
AOI22X1TS U3205 ( .A0(intDX_EWSW[32]), .A1(n2511), .B0(DmP_EXP_EWSW[32]),
.B1(n2464), .Y(n2465) );
OAI21XLTS U3206 ( .A0(n4172), .A1(n2513), .B0(n2465), .Y(n1334) );
AOI22X1TS U3207 ( .A0(intDX_EWSW[39]), .A1(n2466), .B0(DmP_EXP_EWSW[39]),
.B1(n2510), .Y(n2467) );
OAI21XLTS U3208 ( .A0(n4199), .A1(n2513), .B0(n2467), .Y(n1320) );
AOI22X1TS U3209 ( .A0(intDX_EWSW[40]), .A1(n2511), .B0(DmP_EXP_EWSW[40]),
.B1(n2510), .Y(n2468) );
OAI21XLTS U3210 ( .A0(n4200), .A1(n2513), .B0(n2468), .Y(n1318) );
AOI22X1TS U3211 ( .A0(intDX_EWSW[47]), .A1(n2637), .B0(DmP_EXP_EWSW[47]),
.B1(n3912), .Y(n2469) );
OAI21XLTS U3212 ( .A0(n4201), .A1(n2509), .B0(n2469), .Y(n1304) );
AOI22X1TS U3213 ( .A0(intDX_EWSW[18]), .A1(n2520), .B0(DmP_EXP_EWSW[18]),
.B1(n2519), .Y(n2470) );
OAI21XLTS U3214 ( .A0(n4167), .A1(n2522), .B0(n2470), .Y(n1362) );
AOI22X1TS U3215 ( .A0(intDX_EWSW[8]), .A1(n2516), .B0(DmP_EXP_EWSW[8]), .B1(
n2515), .Y(n2471) );
OAI21XLTS U3216 ( .A0(n4070), .A1(n2518), .B0(n2471), .Y(n1382) );
AOI22X1TS U3217 ( .A0(intDX_EWSW[17]), .A1(n2520), .B0(DmP_EXP_EWSW[17]),
.B1(n2519), .Y(n2472) );
OAI21XLTS U3218 ( .A0(n4066), .A1(n2522), .B0(n2472), .Y(n1364) );
AOI22X1TS U3219 ( .A0(intDX_EWSW[20]), .A1(n2520), .B0(DmP_EXP_EWSW[20]),
.B1(n2519), .Y(n2473) );
OAI21XLTS U3220 ( .A0(n4165), .A1(n2522), .B0(n2473), .Y(n1358) );
AOI22X1TS U3221 ( .A0(intDX_EWSW[13]), .A1(n2520), .B0(DmP_EXP_EWSW[13]),
.B1(n2515), .Y(n2474) );
OAI21XLTS U3222 ( .A0(n4160), .A1(n2522), .B0(n2474), .Y(n1372) );
AOI22X1TS U3223 ( .A0(intDX_EWSW[21]), .A1(n2520), .B0(DmP_EXP_EWSW[21]),
.B1(n2519), .Y(n2475) );
OAI21XLTS U3224 ( .A0(n4161), .A1(n2522), .B0(n2475), .Y(n1356) );
AOI22X1TS U3225 ( .A0(intDX_EWSW[19]), .A1(n2520), .B0(DmP_EXP_EWSW[19]),
.B1(n2519), .Y(n2476) );
OAI21XLTS U3226 ( .A0(n4068), .A1(n2522), .B0(n2476), .Y(n1360) );
AOI22X1TS U3227 ( .A0(intDX_EWSW[6]), .A1(n2516), .B0(DmP_EXP_EWSW[6]), .B1(
n2515), .Y(n2477) );
OAI21XLTS U3228 ( .A0(n4089), .A1(n2518), .B0(n2477), .Y(n1386) );
AOI22X1TS U3229 ( .A0(intDX_EWSW[9]), .A1(n2516), .B0(DmP_EXP_EWSW[9]), .B1(
n2515), .Y(n2478) );
OAI21XLTS U3230 ( .A0(n4163), .A1(n2518), .B0(n2478), .Y(n1380) );
AOI22X1TS U3231 ( .A0(intDX_EWSW[1]), .A1(n2516), .B0(DmP_EXP_EWSW[1]), .B1(
n2641), .Y(n2479) );
OAI21XLTS U3232 ( .A0(n4203), .A1(n2644), .B0(n2479), .Y(n1396) );
INVX2TS U3233 ( .A(n2498), .Y(n3999) );
AOI22X1TS U3234 ( .A0(intDY_EWSW[58]), .A1(n2642), .B0(DMP_EXP_EWSW[58]),
.B1(n2634), .Y(n2480) );
OAI21XLTS U3235 ( .A0(n4219), .A1(n3999), .B0(n2480), .Y(n1617) );
AOI22X1TS U3236 ( .A0(intDX_EWSW[10]), .A1(n2516), .B0(DmP_EXP_EWSW[10]),
.B1(n2515), .Y(n2481) );
OAI21XLTS U3237 ( .A0(n4162), .A1(n2518), .B0(n2481), .Y(n1378) );
INVX2TS U3238 ( .A(rst), .Y(n4359) );
CLKBUFX2TS U3239 ( .A(n4359), .Y(n2482) );
CLKBUFX2TS U3240 ( .A(n2482), .Y(n4313) );
CLKBUFX2TS U3241 ( .A(n4359), .Y(n2483) );
CLKBUFX2TS U3242 ( .A(n2483), .Y(n4295) );
CLKBUFX2TS U3243 ( .A(n2482), .Y(n4312) );
CLKBUFX2TS U3244 ( .A(n2482), .Y(n4311) );
CLKBUFX2TS U3245 ( .A(n2482), .Y(n4310) );
CLKBUFX2TS U3246 ( .A(n2482), .Y(n4309) );
CLKBUFX2TS U3247 ( .A(n2482), .Y(n4308) );
CLKBUFX2TS U3248 ( .A(n4359), .Y(n2487) );
CLKBUFX2TS U3249 ( .A(n2487), .Y(n4290) );
CLKBUFX2TS U3250 ( .A(n4359), .Y(n2485) );
CLKBUFX2TS U3251 ( .A(n2485), .Y(n4317) );
CLKBUFX2TS U3252 ( .A(n2487), .Y(n4291) );
CLKBUFX2TS U3253 ( .A(n2485), .Y(n4316) );
CLKBUFX2TS U3254 ( .A(n2487), .Y(n4292) );
CLKBUFX2TS U3255 ( .A(n2485), .Y(n4315) );
CLKBUFX2TS U3256 ( .A(n2487), .Y(n4293) );
CLKBUFX2TS U3257 ( .A(n2487), .Y(n4294) );
CLKBUFX2TS U3258 ( .A(n2482), .Y(n4314) );
CLKBUFX2TS U3259 ( .A(n2483), .Y(n4300) );
CLKBUFX2TS U3260 ( .A(n4359), .Y(n4354) );
CLKBUFX2TS U3261 ( .A(n4354), .Y(n4351) );
CLKBUFX2TS U3262 ( .A(n4354), .Y(n4350) );
CLKBUFX2TS U3263 ( .A(n2483), .Y(n4299) );
CLKBUFX2TS U3264 ( .A(n4354), .Y(n4347) );
CLKBUFX2TS U3265 ( .A(n4354), .Y(n4349) );
CLKBUFX2TS U3266 ( .A(n2483), .Y(n4298) );
CLKBUFX2TS U3267 ( .A(n2483), .Y(n4296) );
CLKBUFX2TS U3268 ( .A(n2482), .Y(n4306) );
CLKBUFX2TS U3269 ( .A(n2482), .Y(n4305) );
CLKBUFX2TS U3270 ( .A(n2482), .Y(n4307) );
CLKBUFX2TS U3271 ( .A(n2483), .Y(n4304) );
CLKBUFX2TS U3272 ( .A(n2483), .Y(n4303) );
CLKBUFX2TS U3273 ( .A(n2483), .Y(n4297) );
CLKBUFX2TS U3274 ( .A(n4354), .Y(n4346) );
CLKBUFX2TS U3275 ( .A(n2483), .Y(n4302) );
CLKBUFX2TS U3276 ( .A(n2483), .Y(n4301) );
CLKBUFX2TS U3277 ( .A(n4359), .Y(n2484) );
CLKBUFX2TS U3278 ( .A(n2484), .Y(n4281) );
CLKBUFX2TS U3279 ( .A(n2485), .Y(n4318) );
CLKBUFX2TS U3280 ( .A(n4354), .Y(n4352) );
CLKBUFX2TS U3281 ( .A(n2484), .Y(n4282) );
CLKBUFX2TS U3282 ( .A(n2484), .Y(n4283) );
CLKBUFX2TS U3283 ( .A(n2484), .Y(n4284) );
CLKBUFX2TS U3284 ( .A(n2484), .Y(n4275) );
CLKBUFX2TS U3285 ( .A(n2485), .Y(n4320) );
CLKBUFX2TS U3286 ( .A(n2484), .Y(n4277) );
CLKBUFX2TS U3287 ( .A(n4359), .Y(n2488) );
CLKBUFX2TS U3288 ( .A(n2488), .Y(n4325) );
CLKBUFX2TS U3289 ( .A(n2485), .Y(n4324) );
CLKBUFX2TS U3290 ( .A(n2484), .Y(n4278) );
CLKBUFX2TS U3291 ( .A(n2485), .Y(n4323) );
CLKBUFX2TS U3292 ( .A(n2484), .Y(n4279) );
CLKBUFX2TS U3293 ( .A(n2485), .Y(n4321) );
CLKBUFX2TS U3294 ( .A(n2484), .Y(n4280) );
CLKBUFX2TS U3295 ( .A(n2485), .Y(n4322) );
CLKBUFX2TS U3296 ( .A(n2488), .Y(n4330) );
CLKBUFX2TS U3297 ( .A(n2488), .Y(n4329) );
CLKBUFX2TS U3298 ( .A(n2488), .Y(n4328) );
CLKBUFX2TS U3299 ( .A(n2488), .Y(n4333) );
CLKBUFX2TS U3300 ( .A(n4359), .Y(n2486) );
CLKBUFX2TS U3301 ( .A(n2486), .Y(n4341) );
CLKBUFX2TS U3302 ( .A(n2488), .Y(n4327) );
CLKBUFX2TS U3303 ( .A(n2488), .Y(n4326) );
CLKBUFX2TS U3304 ( .A(n2486), .Y(n4342) );
CLKBUFX2TS U3305 ( .A(n2486), .Y(n4340) );
CLKBUFX2TS U3306 ( .A(n2486), .Y(n4343) );
CLKBUFX2TS U3307 ( .A(n2487), .Y(n4289) );
CLKBUFX2TS U3308 ( .A(n2486), .Y(n4344) );
CLKBUFX2TS U3309 ( .A(n2485), .Y(n4319) );
CLKBUFX2TS U3310 ( .A(n4354), .Y(n4348) );
CLKBUFX2TS U3311 ( .A(n2486), .Y(n4337) );
CLKBUFX2TS U3312 ( .A(n2486), .Y(n4336) );
CLKBUFX2TS U3313 ( .A(n2486), .Y(n4339) );
CLKBUFX2TS U3314 ( .A(n2487), .Y(n4286) );
CLKBUFX2TS U3315 ( .A(n4354), .Y(n4345) );
CLKBUFX2TS U3316 ( .A(n2488), .Y(n4334) );
CLKBUFX2TS U3317 ( .A(n2488), .Y(n4331) );
CLKBUFX2TS U3318 ( .A(n2487), .Y(n4287) );
CLKBUFX2TS U3319 ( .A(n2487), .Y(n4285) );
CLKBUFX2TS U3320 ( .A(n2486), .Y(n4338) );
CLKBUFX2TS U3321 ( .A(n4354), .Y(n4353) );
CLKBUFX2TS U3322 ( .A(n2486), .Y(n4335) );
CLKBUFX2TS U3323 ( .A(n2487), .Y(n4288) );
CLKBUFX2TS U3324 ( .A(n2488), .Y(n4332) );
AOI22X1TS U3325 ( .A0(intDX_EWSW[8]), .A1(n2495), .B0(DMP_EXP_EWSW[8]), .B1(
n1918), .Y(n2489) );
OAI21XLTS U3326 ( .A0(n4070), .A1(n2492), .B0(n2489), .Y(n1667) );
AOI22X1TS U3327 ( .A0(intDX_EWSW[6]), .A1(n2495), .B0(DMP_EXP_EWSW[6]), .B1(
n1918), .Y(n2490) );
OAI21XLTS U3328 ( .A0(n4089), .A1(n2492), .B0(n2490), .Y(n1669) );
AOI22X1TS U3329 ( .A0(intDX_EWSW[4]), .A1(n2495), .B0(DMP_EXP_EWSW[4]), .B1(
n1918), .Y(n2491) );
OAI21XLTS U3330 ( .A0(n4078), .A1(n2492), .B0(n2491), .Y(n1671) );
AOI22X1TS U3331 ( .A0(intDX_EWSW[7]), .A1(n2495), .B0(DMP_EXP_EWSW[7]), .B1(
n1918), .Y(n2493) );
OAI21XLTS U3332 ( .A0(n4221), .A1(n3997), .B0(n2493), .Y(n1668) );
AOI22X1TS U3333 ( .A0(intDX_EWSW[5]), .A1(n2495), .B0(DMP_EXP_EWSW[5]), .B1(
n1917), .Y(n2494) );
OAI21XLTS U3334 ( .A0(n4207), .A1(n3997), .B0(n2494), .Y(n1670) );
AOI22X1TS U3335 ( .A0(intDX_EWSW[1]), .A1(n2495), .B0(DMP_EXP_EWSW[1]), .B1(
n4360), .Y(n2496) );
OAI21XLTS U3336 ( .A0(n4203), .A1(n3997), .B0(n2496), .Y(n1674) );
AOI22X1TS U3337 ( .A0(intDX_EWSW[44]), .A1(n2498), .B0(DMP_EXP_EWSW[44]),
.B1(n2634), .Y(n2497) );
OAI21XLTS U3338 ( .A0(n4195), .A1(n2500), .B0(n2497), .Y(n1631) );
AOI22X1TS U3339 ( .A0(intDX_EWSW[48]), .A1(n2498), .B0(DMP_EXP_EWSW[48]),
.B1(n2634), .Y(n2499) );
OAI21XLTS U3340 ( .A0(n4190), .A1(n2500), .B0(n2499), .Y(n1627) );
AOI22X1TS U3341 ( .A0(intDX_EWSW[37]), .A1(n2503), .B0(DMP_EXP_EWSW[37]),
.B1(n2502), .Y(n2501) );
OAI21XLTS U3342 ( .A0(n4202), .A1(n2505), .B0(n2501), .Y(n1638) );
AOI22X1TS U3343 ( .A0(intDX_EWSW[38]), .A1(n2503), .B0(DMP_EXP_EWSW[38]),
.B1(n2502), .Y(n2504) );
OAI21XLTS U3344 ( .A0(n4204), .A1(n2505), .B0(n2504), .Y(n1637) );
AOI22X1TS U3345 ( .A0(intDX_EWSW[48]), .A1(n2637), .B0(DmP_EXP_EWSW[48]),
.B1(n3912), .Y(n2506) );
OAI21XLTS U3346 ( .A0(n4190), .A1(n2509), .B0(n2506), .Y(n1302) );
AOI22X1TS U3347 ( .A0(intDX_EWSW[37]), .A1(n2511), .B0(DmP_EXP_EWSW[37]),
.B1(n2510), .Y(n2507) );
OAI21XLTS U3348 ( .A0(n4202), .A1(n2513), .B0(n2507), .Y(n1324) );
AOI22X1TS U3349 ( .A0(intDX_EWSW[44]), .A1(n2637), .B0(DmP_EXP_EWSW[44]),
.B1(n3912), .Y(n2508) );
OAI21XLTS U3350 ( .A0(n4195), .A1(n2509), .B0(n2508), .Y(n1310) );
AOI22X1TS U3351 ( .A0(intDX_EWSW[38]), .A1(n2511), .B0(DmP_EXP_EWSW[38]),
.B1(n2510), .Y(n2512) );
OAI21XLTS U3352 ( .A0(n4204), .A1(n2513), .B0(n2512), .Y(n1322) );
AOI22X1TS U3353 ( .A0(intDY_EWSW[60]), .A1(n2642), .B0(DMP_EXP_EWSW[60]),
.B1(n2641), .Y(n2514) );
OAI21XLTS U3354 ( .A0(n4220), .A1(n2644), .B0(n2514), .Y(n1615) );
AOI22X1TS U3355 ( .A0(intDX_EWSW[4]), .A1(n2516), .B0(DmP_EXP_EWSW[4]), .B1(
n2515), .Y(n2517) );
OAI21XLTS U3356 ( .A0(n4078), .A1(n2518), .B0(n2517), .Y(n1390) );
AOI22X1TS U3357 ( .A0(intDX_EWSW[16]), .A1(n2520), .B0(DmP_EXP_EWSW[16]),
.B1(n2519), .Y(n2521) );
OAI21XLTS U3358 ( .A0(n4191), .A1(n2522), .B0(n2521), .Y(n1366) );
CLKBUFX2TS U3359 ( .A(Shift_reg_FLAGS_7_5), .Y(n3988) );
INVX2TS U3360 ( .A(n3988), .Y(n4005) );
NAND2X1TS U3361 ( .A(DmP_EXP_EWSW[52]), .B(n4239), .Y(n3947) );
OA21XLTS U3362 ( .A0(DmP_EXP_EWSW[52]), .A1(n4239), .B0(n3947), .Y(n2524) );
NAND2X1TS U3363 ( .A(n4005), .B(Shift_amount_SHT1_EWR[0]), .Y(n2523) );
OAI21XLTS U3364 ( .A0(n4005), .A1(n2524), .B0(n2523), .Y(n1692) );
CLKBUFX2TS U3365 ( .A(n4262), .Y(n4007) );
INVX2TS U3366 ( .A(n4007), .Y(busy) );
AOI22X1TS U3367 ( .A0(Data_array_SWR[52]), .A1(n3635), .B0(
Data_array_SWR[48]), .B1(n3642), .Y(n2525) );
NAND2X1TS U3368 ( .A(n2525), .B(n2544), .Y(n3862) );
INVX2TS U3369 ( .A(n3862), .Y(n3841) );
AOI22X1TS U3370 ( .A0(Data_array_SWR[40]), .A1(n3634), .B0(
Data_array_SWR[32]), .B1(n3633), .Y(n2526) );
OAI2BB1X1TS U3371 ( .A0N(Data_array_SWR[36]), .A1N(n3644), .B0(n2526), .Y(
n2527) );
OAI22X1TS U3372 ( .A0(n3841), .A1(n3640), .B0(n3839), .B1(n2549), .Y(n2533)
);
AOI22X1TS U3373 ( .A0(Data_array_SWR[24]), .A1(n3643), .B0(
Data_array_SWR[16]), .B1(n3642), .Y(n2528) );
AOI21X1TS U3374 ( .A0(Data_array_SWR[20]), .A1(n3635), .B0(n2529), .Y(n3846)
);
AOI22X1TS U3375 ( .A0(Data_array_SWR[12]), .A1(n1929), .B0(Data_array_SWR[4]), .B1(n1925), .Y(n2531) );
AOI22X1TS U3376 ( .A0(Data_array_SWR[8]), .A1(n1933), .B0(Data_array_SWR[0]),
.B1(n1913), .Y(n2530) );
INVX2TS U3377 ( .A(n2535), .Y(n3979) );
CLKBUFX2TS U3378 ( .A(n3979), .Y(n4002) );
INVX2TS U3379 ( .A(n4002), .Y(n3206) );
INVX2TS U3380 ( .A(n3167), .Y(n3193) );
NAND2X1TS U3381 ( .A(n3206), .B(n1911), .Y(n3194) );
INVX2TS U3382 ( .A(n3194), .Y(n3156) );
AOI22X1TS U3383 ( .A0(n2536), .A1(n3156), .B0(DmP_mant_SFG_SWR[54]), .B1(
n4002), .Y(n2534) );
INVX2TS U3384 ( .A(n3156), .Y(n3190) );
INVX2TS U3385 ( .A(n2535), .Y(n3977) );
AOI22X1TS U3386 ( .A0(n2536), .A1(n3167), .B0(DmP_mant_SFG_SWR[0]), .B1(
n3977), .Y(n2537) );
AOI22X1TS U3387 ( .A0(Data_array_SWR[25]), .A1(n3643), .B0(
Data_array_SWR[17]), .B1(n3642), .Y(n2539) );
AOI21X1TS U3388 ( .A0(Data_array_SWR[21]), .A1(n2541), .B0(n2540), .Y(n3825)
);
AOI22X1TS U3389 ( .A0(Data_array_SWR[13]), .A1(n1929), .B0(Data_array_SWR[5]), .B1(n1925), .Y(n2543) );
AOI22X1TS U3390 ( .A0(Data_array_SWR[9]), .A1(n1933), .B0(Data_array_SWR[1]),
.B1(n1913), .Y(n2542) );
AOI22X1TS U3391 ( .A0(Data_array_SWR[49]), .A1(n3624), .B0(
Data_array_SWR[53]), .B1(n3644), .Y(n2545) );
NAND2X1TS U3392 ( .A(n2545), .B(n2544), .Y(n3866) );
INVX2TS U3393 ( .A(n3866), .Y(n3820) );
AOI22X1TS U3394 ( .A0(Data_array_SWR[41]), .A1(n3634), .B0(
Data_array_SWR[33]), .B1(n3633), .Y(n2546) );
OAI2BB1X1TS U3395 ( .A0N(Data_array_SWR[37]), .A1N(n3644), .B0(n2546), .Y(
n2547) );
OAI22X1TS U3396 ( .A0(n3820), .A1(n3640), .B0(n3819), .B1(n2549), .Y(n2550)
);
AOI22X1TS U3397 ( .A0(n3145), .A1(n3156), .B0(DmP_mant_SFG_SWR[53]), .B1(
n3977), .Y(n2555) );
AOI22X1TS U3398 ( .A0(n3145), .A1(n3167), .B0(DmP_mant_SFG_SWR[1]), .B1(
n4002), .Y(n2556) );
AOI22X1TS U3399 ( .A0(n3136), .A1(n3156), .B0(DmP_mant_SFG_SWR[51]), .B1(
n3979), .Y(n2557) );
AOI22X1TS U3400 ( .A0(n3136), .A1(n3167), .B0(DmP_mant_SFG_SWR[3]), .B1(
n4002), .Y(n2558) );
AOI22X1TS U3401 ( .A0(n4085), .A1(intDX_EWSW[11]), .B0(n4205), .B1(
intDX_EWSW[50]), .Y(n2559) );
OAI221XLTS U3402 ( .A0(n4085), .A1(intDX_EWSW[11]), .B0(n4205), .B1(
intDX_EWSW[50]), .C0(n2559), .Y(n2560) );
AOI221XLTS U3403 ( .A0(intDY_EWSW[49]), .A1(n4223), .B0(n4209), .B1(
intDX_EWSW[49]), .C0(n2560), .Y(n2574) );
OAI22X1TS U3404 ( .A0(n4054), .A1(intDX_EWSW[53]), .B0(n4080), .B1(
intDX_EWSW[54]), .Y(n2561) );
AOI221XLTS U3405 ( .A0(n4054), .A1(intDX_EWSW[53]), .B0(intDX_EWSW[54]),
.B1(n4080), .C0(n2561), .Y(n2573) );
OAI22X1TS U3406 ( .A0(n4198), .A1(intDX_EWSW[51]), .B0(n4222), .B1(
intDX_EWSW[52]), .Y(n2562) );
AOI221XLTS U3407 ( .A0(n4198), .A1(intDX_EWSW[51]), .B0(intDX_EWSW[52]),
.B1(n4222), .C0(n2562), .Y(n2572) );
AOI22X1TS U3408 ( .A0(n4219), .A1(intDY_EWSW[58]), .B0(n4206), .B1(
intDX_EWSW[57]), .Y(n2563) );
OAI221XLTS U3409 ( .A0(n4219), .A1(intDY_EWSW[58]), .B0(n4206), .B1(
intDX_EWSW[57]), .C0(n2563), .Y(n2570) );
AOI22X1TS U3410 ( .A0(n4055), .A1(intDX_EWSW[56]), .B0(n4063), .B1(
intDX_EWSW[55]), .Y(n2564) );
OAI221XLTS U3411 ( .A0(n4055), .A1(intDX_EWSW[56]), .B0(n4063), .B1(
intDX_EWSW[55]), .C0(n2564), .Y(n2569) );
AOI22X1TS U3412 ( .A0(n4215), .A1(intDY_EWSW[62]), .B0(n4071), .B1(
intDY_EWSW[61]), .Y(n2565) );
OAI221XLTS U3413 ( .A0(n4215), .A1(intDY_EWSW[62]), .B0(n4071), .B1(
intDY_EWSW[61]), .C0(n2565), .Y(n2568) );
AOI22X1TS U3414 ( .A0(n4220), .A1(intDY_EWSW[60]), .B0(n4077), .B1(
intDY_EWSW[59]), .Y(n2566) );
OAI221XLTS U3415 ( .A0(n4220), .A1(intDY_EWSW[60]), .B0(n4077), .B1(
intDY_EWSW[59]), .C0(n2566), .Y(n2567) );
NOR4XLTS U3416 ( .A(n2570), .B(n2569), .C(n2568), .D(n2567), .Y(n2571) );
NAND4XLTS U3417 ( .A(n2574), .B(n2573), .C(n2572), .D(n2571), .Y(n2630) );
OAI22X1TS U3418 ( .A0(n4197), .A1(intDX_EWSW[42]), .B0(n4082), .B1(
intDX_EWSW[43]), .Y(n2575) );
AOI221XLTS U3419 ( .A0(n4197), .A1(intDX_EWSW[42]), .B0(intDX_EWSW[43]),
.B1(n4082), .C0(n2575), .Y(n2582) );
OAI22X1TS U3420 ( .A0(n4200), .A1(intDX_EWSW[40]), .B0(n4084), .B1(
intDX_EWSW[41]), .Y(n2576) );
AOI221XLTS U3421 ( .A0(n4200), .A1(intDX_EWSW[40]), .B0(intDX_EWSW[41]),
.B1(n4084), .C0(n2576), .Y(n2581) );
OAI22X1TS U3422 ( .A0(n4083), .A1(intDX_EWSW[46]), .B0(n4201), .B1(
intDX_EWSW[47]), .Y(n2577) );
AOI221XLTS U3423 ( .A0(n4083), .A1(intDX_EWSW[46]), .B0(intDX_EWSW[47]),
.B1(n4201), .C0(n2577), .Y(n2580) );
OAI22X1TS U3424 ( .A0(n4195), .A1(intDX_EWSW[44]), .B0(n4193), .B1(
intDX_EWSW[45]), .Y(n2578) );
AOI221XLTS U3425 ( .A0(n4195), .A1(intDX_EWSW[44]), .B0(intDX_EWSW[45]),
.B1(n4193), .C0(n2578), .Y(n2579) );
NAND4XLTS U3426 ( .A(n2582), .B(n2581), .C(n2580), .D(n2579), .Y(n2629) );
OAI22X1TS U3427 ( .A0(n4196), .A1(intDX_EWSW[34]), .B0(n4081), .B1(
intDX_EWSW[35]), .Y(n2583) );
AOI221XLTS U3428 ( .A0(n4196), .A1(intDX_EWSW[34]), .B0(intDX_EWSW[35]),
.B1(n4081), .C0(n2583), .Y(n2590) );
OAI22X1TS U3429 ( .A0(n4203), .A1(intDX_EWSW[1]), .B0(n4192), .B1(
intDX_EWSW[33]), .Y(n2584) );
AOI221XLTS U3430 ( .A0(n4203), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[33]), .B1(
n4192), .C0(n2584), .Y(n2589) );
OAI22X1TS U3431 ( .A0(n4204), .A1(intDX_EWSW[38]), .B0(n4199), .B1(
intDX_EWSW[39]), .Y(n2585) );
AOI221XLTS U3432 ( .A0(n4204), .A1(intDX_EWSW[38]), .B0(intDX_EWSW[39]),
.B1(n4199), .C0(n2585), .Y(n2588) );
OAI22X1TS U3433 ( .A0(n4194), .A1(intDX_EWSW[36]), .B0(n4202), .B1(
intDX_EWSW[37]), .Y(n2586) );
AOI221XLTS U3434 ( .A0(n4194), .A1(intDX_EWSW[36]), .B0(intDX_EWSW[37]),
.B1(n4202), .C0(n2586), .Y(n2587) );
NAND4XLTS U3435 ( .A(n2590), .B(n2589), .C(n2588), .D(n2587), .Y(n2628) );
OAI221XLTS U3436 ( .A0(n4088), .A1(intDX_EWSW[31]), .B0(n4218), .B1(
intDX_EWSW[30]), .C0(n2591), .Y(n2598) );
AOI22X1TS U3437 ( .A0(n4065), .A1(intDX_EWSW[29]), .B0(n4165), .B1(
intDX_EWSW[20]), .Y(n2592) );
OAI221XLTS U3438 ( .A0(n4065), .A1(intDX_EWSW[29]), .B0(n4165), .B1(
intDX_EWSW[20]), .C0(n2592), .Y(n2597) );
AOI22X1TS U3439 ( .A0(n4069), .A1(intDX_EWSW[27]), .B0(n4168), .B1(
intDX_EWSW[26]), .Y(n2593) );
OAI221XLTS U3440 ( .A0(n4069), .A1(intDX_EWSW[27]), .B0(n4168), .B1(
intDX_EWSW[26]), .C0(n2593), .Y(n2596) );
AOI22X1TS U3441 ( .A0(n4067), .A1(intDX_EWSW[25]), .B0(n4172), .B1(
intDX_EWSW[32]), .Y(n2594) );
OAI221XLTS U3442 ( .A0(n4067), .A1(intDX_EWSW[25]), .B0(n4172), .B1(
intDX_EWSW[32]), .C0(n2594), .Y(n2595) );
NOR4XLTS U3443 ( .A(n2598), .B(n2597), .C(n2596), .D(n2595), .Y(n2626) );
OAI221XLTS U3444 ( .A0(n4087), .A1(intDX_EWSW[23]), .B0(n4217), .B1(
intDX_EWSW[22]), .C0(n2599), .Y(n2606) );
AOI22X1TS U3445 ( .A0(n4161), .A1(intDX_EWSW[21]), .B0(n4190), .B1(
intDX_EWSW[48]), .Y(n2600) );
OAI221XLTS U3446 ( .A0(n4161), .A1(intDX_EWSW[21]), .B0(n4190), .B1(
intDX_EWSW[48]), .C0(n2600), .Y(n2605) );
AOI22X1TS U3447 ( .A0(n4068), .A1(intDX_EWSW[19]), .B0(n4167), .B1(
intDX_EWSW[18]), .Y(n2601) );
OAI221XLTS U3448 ( .A0(n4068), .A1(intDX_EWSW[19]), .B0(n4167), .B1(
intDX_EWSW[18]), .C0(n2601), .Y(n2604) );
AOI22X1TS U3449 ( .A0(n4066), .A1(intDX_EWSW[17]), .B0(n4169), .B1(
intDX_EWSW[24]), .Y(n2602) );
OAI221XLTS U3450 ( .A0(n4066), .A1(intDX_EWSW[17]), .B0(n4169), .B1(
intDX_EWSW[24]), .C0(n2602), .Y(n2603) );
NOR4XLTS U3451 ( .A(n2606), .B(n2605), .C(n2604), .D(n2603), .Y(n2625) );
OAI221XLTS U3452 ( .A0(n4086), .A1(intDX_EWSW[15]), .B0(n4216), .B1(
intDX_EWSW[14]), .C0(n2607), .Y(n2614) );
AOI22X1TS U3453 ( .A0(n4160), .A1(intDX_EWSW[13]), .B0(n4078), .B1(
intDX_EWSW[4]), .Y(n2608) );
OAI221XLTS U3454 ( .A0(n4160), .A1(intDX_EWSW[13]), .B0(n4078), .B1(
intDX_EWSW[4]), .C0(n2608), .Y(n2613) );
AOI22X1TS U3455 ( .A0(n4162), .A1(intDX_EWSW[10]), .B0(n4164), .B1(
intDX_EWSW[12]), .Y(n2609) );
OAI221XLTS U3456 ( .A0(n4162), .A1(intDX_EWSW[10]), .B0(n4164), .B1(
intDX_EWSW[12]), .C0(n2609), .Y(n2612) );
AOI22X1TS U3457 ( .A0(n4163), .A1(intDX_EWSW[9]), .B0(n4191), .B1(
intDX_EWSW[16]), .Y(n2610) );
OAI221XLTS U3458 ( .A0(n4163), .A1(intDX_EWSW[9]), .B0(n4191), .B1(
intDX_EWSW[16]), .C0(n2610), .Y(n2611) );
NOR4XLTS U3459 ( .A(n2614), .B(n2613), .C(n2612), .D(n2611), .Y(n2624) );
OAI221XLTS U3460 ( .A0(n4221), .A1(intDX_EWSW[7]), .B0(n4089), .B1(
intDX_EWSW[6]), .C0(n2615), .Y(n2622) );
AOI22X1TS U3461 ( .A0(n4207), .A1(intDX_EWSW[5]), .B0(n4166), .B1(
intDX_EWSW[28]), .Y(n2616) );
OAI221XLTS U3462 ( .A0(n4207), .A1(intDX_EWSW[5]), .B0(n4166), .B1(
intDX_EWSW[28]), .C0(n2616), .Y(n2621) );
AOI22X1TS U3463 ( .A0(n4064), .A1(intDX_EWSW[3]), .B0(n4171), .B1(
intDX_EWSW[2]), .Y(n2617) );
OAI221XLTS U3464 ( .A0(n4064), .A1(intDX_EWSW[3]), .B0(n4171), .B1(
intDX_EWSW[2]), .C0(n2617), .Y(n2620) );
AOI22X1TS U3465 ( .A0(n4170), .A1(intDX_EWSW[0]), .B0(n4070), .B1(
intDX_EWSW[8]), .Y(n2618) );
OAI221XLTS U3466 ( .A0(n4170), .A1(intDX_EWSW[0]), .B0(n4070), .B1(
intDX_EWSW[8]), .C0(n2618), .Y(n2619) );
NOR4XLTS U3467 ( .A(n2622), .B(n2621), .C(n2620), .D(n2619), .Y(n2623) );
NAND4XLTS U3468 ( .A(n2626), .B(n2625), .C(n2624), .D(n2623), .Y(n2627) );
NOR4XLTS U3469 ( .A(n2630), .B(n2629), .C(n2628), .D(n2627), .Y(n3966) );
XOR2XLTS U3470 ( .A(intDY_EWSW[63]), .B(intAS), .Y(n3964) );
INVX2TS U3471 ( .A(n3964), .Y(n2633) );
AOI22X1TS U3472 ( .A0(intDX_EWSW[63]), .A1(n2631), .B0(SIGN_FLAG_EXP), .B1(
n2641), .Y(n2632) );
AOI22X1TS U3473 ( .A0(intDX_EWSW[51]), .A1(n2635), .B0(DMP_EXP_EWSW[51]),
.B1(n2634), .Y(n2636) );
AOI22X1TS U3474 ( .A0(intDX_EWSW[51]), .A1(n2637), .B0(DmP_EXP_EWSW[51]),
.B1(n3912), .Y(n2638) );
AOI22X1TS U3475 ( .A0(intDY_EWSW[61]), .A1(n2642), .B0(DMP_EXP_EWSW[61]),
.B1(n2641), .Y(n2639) );
AOI22X1TS U3476 ( .A0(intDY_EWSW[62]), .A1(n2642), .B0(DMP_EXP_EWSW[62]),
.B1(n2641), .Y(n2640) );
AOI22X1TS U3477 ( .A0(intDY_EWSW[59]), .A1(n2642), .B0(DMP_EXP_EWSW[59]),
.B1(n2641), .Y(n2643) );
NOR2XLTS U3478 ( .A(Raw_mant_NRM_SWR[40]), .B(Raw_mant_NRM_SWR[42]), .Y(
n2649) );
OAI21XLTS U3479 ( .A0(Raw_mant_NRM_SWR[6]), .A1(Raw_mant_NRM_SWR[4]), .B0(
n2645), .Y(n2647) );
NAND2X1TS U3480 ( .A(n2657), .B(Raw_mant_NRM_SWR[20]), .Y(n2719) );
OAI211XLTS U3481 ( .A0(n2649), .A1(n2648), .B0(n2647), .C0(n2719), .Y(n2705)
);
NOR2XLTS U3482 ( .A(n4183), .B(Raw_mant_NRM_SWR[4]), .Y(n2650) );
OAI21XLTS U3483 ( .A0(n2650), .A1(Raw_mant_NRM_SWR[5]), .B0(n4179), .Y(n2655) );
OAI21XLTS U3484 ( .A0(Raw_mant_NRM_SWR[40]), .A1(n4184), .B0(n4058), .Y(
n2653) );
CLKINVX1TS U3485 ( .A(n2679), .Y(n2652) );
NAND2X1TS U3486 ( .A(n4139), .B(Raw_mant_NRM_SWR[21]), .Y(n2651) );
AOI21X1TS U3487 ( .A0(n2759), .A1(n2653), .B0(n2736), .Y(n2654) );
OAI21X1TS U3488 ( .A0(n2656), .A1(n2655), .B0(n2654), .Y(n2704) );
NAND2X1TS U3489 ( .A(n2657), .B(Raw_mant_NRM_SWR[19]), .Y(n2696) );
CLKINVX1TS U3490 ( .A(n2694), .Y(n2659) );
AOI22X1TS U3491 ( .A0(n2659), .A1(Raw_mant_NRM_SWR[27]), .B0(n2658), .B1(
Raw_mant_NRM_SWR[31]), .Y(n2718) );
CLKINVX1TS U3492 ( .A(n2673), .Y(n2662) );
AOI22X1TS U3493 ( .A0(n2714), .A1(Raw_mant_NRM_SWR[33]), .B0(
Raw_mant_NRM_SWR[47]), .B1(n2771), .Y(n2661) );
OR2X2TS U3494 ( .A(n2704), .B(n2670), .Y(n2786) );
NOR2XLTS U3495 ( .A(n2671), .B(n4248), .Y(n2678) );
OAI21XLTS U3496 ( .A0(Raw_mant_NRM_SWR[34]), .A1(Raw_mant_NRM_SWR[32]), .B0(
n2728), .Y(n2674) );
OAI211XLTS U3497 ( .A0(n2676), .A1(n2675), .B0(n2761), .C0(n2674), .Y(n2677)
);
AOI211XLTS U3498 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n2679), .B0(n2678), .C0(
n2677), .Y(n2680) );
OAI21XLTS U3499 ( .A0(n2698), .A1(n4177), .B0(n2680), .Y(n2681) );
INVX2TS U3500 ( .A(n3890), .Y(n3152) );
INVX2TS U3501 ( .A(n3153), .Y(n2923) );
AOI22X1TS U3502 ( .A0(n2923), .A1(shift_value_SHT2_EWR[2]), .B0(n2741), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n2683) );
OAI21XLTS U3503 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n4185), .B0(n4072), .Y(n2688) );
NOR3XLTS U3504 ( .A(n2692), .B(Raw_mant_NRM_SWR[47]), .C(n4182), .Y(n2685)
);
NAND2X1TS U3505 ( .A(n2685), .B(n2771), .Y(n2755) );
NAND2X1TS U3506 ( .A(n2734), .B(Raw_mant_NRM_SWR[25]), .Y(n2724) );
AOI21X1TS U3507 ( .A0(n2689), .A1(n2688), .B0(n2687), .Y(n2783) );
NOR2XLTS U3508 ( .A(n2731), .B(n4228), .Y(n2691) );
AOI31XLTS U3509 ( .A0(n2771), .A1(n4176), .A2(n2692), .B0(n2691), .Y(n2693)
);
NAND2X1TS U3510 ( .A(n2715), .B(Raw_mant_NRM_SWR[24]), .Y(n2695) );
NAND2X1TS U3511 ( .A(n2696), .B(n2695), .Y(n2720) );
AOI211XLTS U3512 ( .A0(n2715), .A1(Raw_mant_NRM_SWR[22]), .B0(n2697), .C0(
n2720), .Y(n2702) );
AOI22X1TS U3513 ( .A0(n2923), .A1(shift_value_SHT2_EWR[3]), .B0(n2741), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n2707) );
CLKBUFX2TS U3514 ( .A(n4356), .Y(n2957) );
OAI21XLTS U3515 ( .A0(Raw_mant_NRM_SWR[36]), .A1(Raw_mant_NRM_SWR[35]), .B0(
n4058), .Y(n2711) );
NAND2X1TS U3516 ( .A(n2715), .B(Raw_mant_NRM_SWR[23]), .Y(n2716) );
NOR4XLTS U3517 ( .A(Raw_mant_NRM_SWR[30]), .B(Raw_mant_NRM_SWR[28]), .C(
Raw_mant_NRM_SWR[26]), .D(Raw_mant_NRM_SWR[29]), .Y(n2730) );
NAND2X1TS U3518 ( .A(n2725), .B(n4058), .Y(n2726) );
OAI22X1TS U3519 ( .A0(n2778), .A1(n4115), .B0(n2776), .B1(n2726), .Y(n2727)
);
AOI21X1TS U3520 ( .A0(n2728), .A1(Raw_mant_NRM_SWR[33]), .B0(n2727), .Y(
n2729) );
OAI21XLTS U3521 ( .A0(n2731), .A1(n2730), .B0(n2729), .Y(n2732) );
AOI211XLTS U3522 ( .A0(n2734), .A1(Raw_mant_NRM_SWR[22]), .B0(n2733), .C0(
n2732), .Y(n2735) );
AOI21X1TS U3523 ( .A0(n2739), .A1(Raw_mant_NRM_SWR[2]), .B0(n2740), .Y(n2738) );
INVX2TS U3524 ( .A(n3152), .Y(n2948) );
NAND2X1TS U3525 ( .A(n2740), .B(n2948), .Y(n2743) );
AOI22X1TS U3526 ( .A0(n2923), .A1(shift_value_SHT2_EWR[4]), .B0(n2741), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n2742) );
NOR2XLTS U3527 ( .A(n2745), .B(Raw_mant_NRM_SWR[41]), .Y(n2758) );
NAND2X1TS U3528 ( .A(n2746), .B(Raw_mant_NRM_SWR[44]), .Y(n2750) );
NOR2XLTS U3529 ( .A(Raw_mant_NRM_SWR[47]), .B(Raw_mant_NRM_SWR[48]), .Y(
n2749) );
AOI21X1TS U3530 ( .A0(n2750), .A1(n2749), .B0(n2748), .Y(n2754) );
NAND2X1TS U3531 ( .A(n2756), .B(n2755), .Y(n2757) );
AOI21X1TS U3532 ( .A0(n2759), .A1(n2758), .B0(n2757), .Y(n2760) );
AOI21X1TS U3533 ( .A0(n2763), .A1(Raw_mant_NRM_SWR[16]), .B0(n2762), .Y(
n2764) );
NAND2X1TS U3534 ( .A(n3197), .B(Shift_amount_SHT1_EWR[1]), .Y(n2796) );
OAI21XLTS U3535 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n4076), .B0(n4181), .Y(
n2780) );
NAND2X1TS U3536 ( .A(n4189), .B(Raw_mant_NRM_SWR[37]), .Y(n2775) );
AOI21X1TS U3537 ( .A0(n2770), .A1(n4186), .B0(Raw_mant_NRM_SWR[53]), .Y(
n2773) );
AOI21X1TS U3538 ( .A0(n2781), .A1(n2780), .B0(n2779), .Y(n2782) );
NAND2X1TS U3539 ( .A(ADD_OVRFLW_NRM), .B(n1920), .Y(n3151) );
CLKBUFX2TS U3540 ( .A(n3151), .Y(n2874) );
INVX2TS U3541 ( .A(n2874), .Y(n2981) );
CLKBUFX2TS U3542 ( .A(n2981), .Y(n2992) );
AOI21X1TS U3543 ( .A0(n2957), .A1(Shift_amount_SHT1_EWR[0]), .B0(n2992), .Y(
n2787) );
OAI21XLTS U3544 ( .A0(n3152), .A1(n4174), .B0(n2790), .Y(n3877) );
AOI21X1TS U3545 ( .A0(n3889), .A1(Data_array_SWR[54]), .B0(n2992), .Y(n2791)
);
OAI22X1TS U3546 ( .A0(n4273), .A1(n1920), .B0(n4090), .B1(n2874), .Y(n2793)
);
AOI21X1TS U3547 ( .A0(n3890), .A1(Raw_mant_NRM_SWR[1]), .B0(n2793), .Y(n2906) );
CLKBUFX2TS U3548 ( .A(n2980), .Y(n3113) );
AOI22X1TS U3549 ( .A0(n3113), .A1(n3877), .B0(n3889), .B1(Data_array_SWR[53]), .Y(n2794) );
INVX2TS U3550 ( .A(n3152), .Y(n2989) );
CLKBUFX2TS U3551 ( .A(n4356), .Y(n2988) );
AOI22X1TS U3552 ( .A0(Raw_mant_NRM_SWR[26]), .A1(n2989), .B0(n2988), .B1(
DmP_mant_SHT1_SW[26]), .Y(n2795) );
MX2X1TS U3553 ( .A(DmP_mant_SHT1_SW[25]), .B(Raw_mant_NRM_SWR[27]), .S0(
n1920), .Y(n2804) );
NAND2X1TS U3554 ( .A(n2797), .B(n2796), .Y(n2798) );
INVX2TS U3555 ( .A(n1942), .Y(n3125) );
INVX2TS U3556 ( .A(n3152), .Y(n2999) );
CLKBUFX2TS U3557 ( .A(n4356), .Y(n2998) );
AOI22X1TS U3558 ( .A0(Raw_mant_NRM_SWR[29]), .A1(n2999), .B0(n2998), .B1(
DmP_mant_SHT1_SW[23]), .Y(n2800) );
CLKBUFX2TS U3559 ( .A(n2981), .Y(n3000) );
NAND2X1TS U3560 ( .A(n3000), .B(Raw_mant_NRM_SWR[25]), .Y(n2799) );
NAND2X1TS U3561 ( .A(n2800), .B(n2799), .Y(n3074) );
INVX2TS U3562 ( .A(n3153), .Y(n3123) );
AOI22X1TS U3563 ( .A0(n3125), .A1(n3074), .B0(n3123), .B1(Data_array_SWR[25]), .Y(n2803) );
AOI22X1TS U3564 ( .A0(Raw_mant_NRM_SWR[28]), .A1(n2989), .B0(n2988), .B1(
DmP_mant_SHT1_SW[24]), .Y(n2801) );
NAND2X1TS U3565 ( .A(n3113), .B(n3076), .Y(n2802) );
AOI22X1TS U3566 ( .A0(Raw_mant_NRM_SWR[30]), .A1(n2999), .B0(n2998), .B1(
DmP_mant_SHT1_SW[22]), .Y(n2806) );
CLKBUFX2TS U3567 ( .A(n2981), .Y(n2889) );
NAND2X1TS U3568 ( .A(n2806), .B(n2805), .Y(n3075) );
INVX2TS U3569 ( .A(n3153), .Y(n3064) );
AOI22X1TS U3570 ( .A0(n3125), .A1(n3075), .B0(n3064), .B1(Data_array_SWR[24]), .Y(n2808) );
NAND2X1TS U3571 ( .A(n3113), .B(n3074), .Y(n2807) );
AOI22X1TS U3572 ( .A0(Raw_mant_NRM_SWR[50]), .A1(n2948), .B0(n3197), .B1(
DmP_mant_SHT1_SW[2]), .Y(n2810) );
NAND2X1TS U3573 ( .A(n2889), .B(Raw_mant_NRM_SWR[4]), .Y(n2809) );
NAND2X1TS U3574 ( .A(n2810), .B(n2809), .Y(n2916) );
INVX2TS U3575 ( .A(n2916), .Y(n2818) );
AND2X2TS U3576 ( .A(n2813), .B(n2812), .Y(n2825) );
AOI22X1TS U3577 ( .A0(Raw_mant_NRM_SWR[51]), .A1(n2948), .B0(n3197), .B1(
DmP_mant_SHT1_SW[1]), .Y(n2814) );
CLKBUFX2TS U3578 ( .A(n2980), .Y(n3120) );
AOI22X1TS U3579 ( .A0(n2948), .A1(Raw_mant_NRM_SWR[52]), .B0(
DmP_mant_SHT1_SW[0]), .B1(n2957), .Y(n2815) );
AOI22X1TS U3580 ( .A0(n3897), .A1(n3893), .B0(n3120), .B1(n3896), .Y(n2817)
);
INVX2TS U3581 ( .A(n1942), .Y(n3081) );
OAI22X1TS U3582 ( .A0(n3152), .A1(n4090), .B0(n2874), .B1(n4053), .Y(n3892)
);
AOI22X1TS U3583 ( .A0(n3081), .A1(n3892), .B0(n2923), .B1(Data_array_SWR[1]),
.Y(n2816) );
AOI22X1TS U3584 ( .A0(Raw_mant_NRM_SWR[49]), .A1(n2948), .B0(n3197), .B1(
DmP_mant_SHT1_SW[3]), .Y(n2820) );
NAND2X1TS U3585 ( .A(n2820), .B(n2819), .Y(n2924) );
INVX2TS U3586 ( .A(n2924), .Y(n2911) );
AOI22X1TS U3587 ( .A0(n3897), .A1(n2916), .B0(n3113), .B1(n3893), .Y(n2822)
);
INVX2TS U3588 ( .A(n1942), .Y(n2925) );
AOI22X1TS U3589 ( .A0(n2925), .A1(n3896), .B0(n2923), .B1(Data_array_SWR[2]),
.Y(n2821) );
AOI22X1TS U3590 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n2989), .B0(n2988), .B1(
DmP_mant_SHT1_SW[30]), .Y(n2824) );
NAND2X1TS U3591 ( .A(n3000), .B(Raw_mant_NRM_SWR[32]), .Y(n2823) );
NAND2X1TS U3592 ( .A(n2824), .B(n2823), .Y(n3023) );
INVX2TS U3593 ( .A(n3023), .Y(n3116) );
AOI22X1TS U3594 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n2989), .B0(n2988), .B1(
DmP_mant_SHT1_SW[29]), .Y(n2827) );
NAND2X1TS U3595 ( .A(n3000), .B(Raw_mant_NRM_SWR[31]), .Y(n2826) );
NAND2X1TS U3596 ( .A(n2827), .B(n2826), .Y(n3112) );
INVX2TS U3597 ( .A(n1942), .Y(n3108) );
INVX2TS U3598 ( .A(n3152), .Y(n3018) );
CLKBUFX2TS U3599 ( .A(n4356), .Y(n3017) );
AOI22X1TS U3600 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n3018), .B0(n3017), .B1(
DmP_mant_SHT1_SW[27]), .Y(n2828) );
AOI22X1TS U3601 ( .A0(n2825), .A1(n3112), .B0(n3108), .B1(n3085), .Y(n2832)
);
AOI22X1TS U3602 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n2989), .B0(n2988), .B1(
DmP_mant_SHT1_SW[28]), .Y(n2830) );
NAND2X1TS U3603 ( .A(n3000), .B(Raw_mant_NRM_SWR[30]), .Y(n2829) );
NAND2X1TS U3604 ( .A(n2830), .B(n2829), .Y(n3107) );
AOI22X1TS U3605 ( .A0(n3113), .A1(n3107), .B0(n3123), .B1(Data_array_SWR[29]), .Y(n2831) );
INVX2TS U3606 ( .A(n3897), .Y(n3006) );
INVX2TS U3607 ( .A(n3152), .Y(n2895) );
CLKBUFX2TS U3608 ( .A(n4356), .Y(n2954) );
AOI22X1TS U3609 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n2895), .B0(n2954), .B1(
DmP_mant_SHT1_SW[46]), .Y(n2834) );
NAND2X1TS U3610 ( .A(n2889), .B(Raw_mant_NRM_SWR[48]), .Y(n2833) );
NAND2X1TS U3611 ( .A(n2834), .B(n2833), .Y(n3050) );
INVX2TS U3612 ( .A(n3050), .Y(n2843) );
INVX2TS U3613 ( .A(n1941), .Y(n3894) );
AOI22X1TS U3614 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n2895), .B0(n2954), .B1(
DmP_mant_SHT1_SW[47]), .Y(n2836) );
CLKBUFX2TS U3615 ( .A(n2981), .Y(n2958) );
NAND2X1TS U3616 ( .A(n2958), .B(Raw_mant_NRM_SWR[49]), .Y(n2835) );
NAND2X1TS U3617 ( .A(n2836), .B(n2835), .Y(n3044) );
CLKBUFX2TS U3618 ( .A(n2980), .Y(n3009) );
AOI22X1TS U3619 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n2895), .B0(n2954), .B1(
DmP_mant_SHT1_SW[45]), .Y(n2838) );
NAND2X1TS U3620 ( .A(n2889), .B(Raw_mant_NRM_SWR[47]), .Y(n2837) );
NAND2X1TS U3621 ( .A(n2838), .B(n2837), .Y(n3048) );
AOI22X1TS U3622 ( .A0(n3894), .A1(n3044), .B0(n3009), .B1(n3048), .Y(n2842)
);
AOI22X1TS U3623 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n2999), .B0(n2954), .B1(
DmP_mant_SHT1_SW[44]), .Y(n2840) );
NAND2X1TS U3624 ( .A(n2889), .B(Raw_mant_NRM_SWR[46]), .Y(n2839) );
NAND2X1TS U3625 ( .A(n2840), .B(n2839), .Y(n3049) );
AOI22X1TS U3626 ( .A0(n3108), .A1(n3049), .B0(n3889), .B1(Data_array_SWR[46]), .Y(n2841) );
INVX2TS U3627 ( .A(n3044), .Y(n2848) );
AOI22X1TS U3628 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n2895), .B0(n2954), .B1(
DmP_mant_SHT1_SW[48]), .Y(n2845) );
NAND2X1TS U3629 ( .A(n2958), .B(Raw_mant_NRM_SWR[50]), .Y(n2844) );
NAND2X1TS U3630 ( .A(n2845), .B(n2844), .Y(n3043) );
AOI22X1TS U3631 ( .A0(n3894), .A1(n3043), .B0(n3009), .B1(n3050), .Y(n2847)
);
AOI22X1TS U3632 ( .A0(n3108), .A1(n3048), .B0(n3889), .B1(Data_array_SWR[47]), .Y(n2846) );
INVX2TS U3633 ( .A(n3043), .Y(n2853) );
AOI22X1TS U3634 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n3890), .B0(n2957), .B1(
DmP_mant_SHT1_SW[49]), .Y(n2850) );
NAND2X1TS U3635 ( .A(n2958), .B(Raw_mant_NRM_SWR[51]), .Y(n2849) );
NAND2X1TS U3636 ( .A(n2850), .B(n2849), .Y(n3042) );
AOI22X1TS U3637 ( .A0(n3894), .A1(n3042), .B0(n3009), .B1(n3044), .Y(n2852)
);
AOI22X1TS U3638 ( .A0(n3108), .A1(n3050), .B0(n3889), .B1(Data_array_SWR[48]), .Y(n2851) );
AOI21X1TS U3639 ( .A0(n2957), .A1(DmP_mant_SHT1_SW[50]), .B0(n2854), .Y(
n2856) );
NAND2X1TS U3640 ( .A(n2856), .B(n2855), .Y(n3879) );
INVX2TS U3641 ( .A(n3879), .Y(n2859) );
INVX2TS U3642 ( .A(n2906), .Y(n3875) );
AOI22X1TS U3643 ( .A0(n3894), .A1(n3875), .B0(n3009), .B1(n3042), .Y(n2858)
);
AOI22X1TS U3644 ( .A0(n3108), .A1(n3043), .B0(n3889), .B1(Data_array_SWR[50]), .Y(n2857) );
INVX2TS U3645 ( .A(n3049), .Y(n2866) );
AOI22X1TS U3646 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n2999), .B0(n2998), .B1(
DmP_mant_SHT1_SW[43]), .Y(n2861) );
NAND2X1TS U3647 ( .A(n2889), .B(Raw_mant_NRM_SWR[45]), .Y(n2860) );
NAND2X1TS U3648 ( .A(n2861), .B(n2860), .Y(n3051) );
AOI22X1TS U3649 ( .A0(n3894), .A1(n3048), .B0(n3009), .B1(n3051), .Y(n2865)
);
AOI22X1TS U3650 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n2999), .B0(n2954), .B1(
DmP_mant_SHT1_SW[42]), .Y(n2863) );
NAND2X1TS U3651 ( .A(n2889), .B(Raw_mant_NRM_SWR[44]), .Y(n2862) );
NAND2X1TS U3652 ( .A(n2863), .B(n2862), .Y(n3121) );
AOI22X1TS U3653 ( .A0(n3108), .A1(n3121), .B0(n3889), .B1(Data_array_SWR[44]), .Y(n2864) );
AOI22X1TS U3654 ( .A0(Raw_mant_NRM_SWR[45]), .A1(n2895), .B0(n2957), .B1(
DmP_mant_SHT1_SW[7]), .Y(n2868) );
NAND2X1TS U3655 ( .A(n2958), .B(Raw_mant_NRM_SWR[9]), .Y(n2867) );
NAND2X1TS U3656 ( .A(n2868), .B(n2867), .Y(n2912) );
INVX2TS U3657 ( .A(n2912), .Y(n2877) );
AOI22X1TS U3658 ( .A0(Raw_mant_NRM_SWR[44]), .A1(n2895), .B0(n2957), .B1(
DmP_mant_SHT1_SW[8]), .Y(n2870) );
NAND2X1TS U3659 ( .A(n2958), .B(Raw_mant_NRM_SWR[10]), .Y(n2869) );
NAND2X1TS U3660 ( .A(n2870), .B(n2869), .Y(n2934) );
AOI22X1TS U3661 ( .A0(Raw_mant_NRM_SWR[46]), .A1(n2895), .B0(n2954), .B1(
DmP_mant_SHT1_SW[6]), .Y(n2872) );
NAND2X1TS U3662 ( .A(n2958), .B(Raw_mant_NRM_SWR[8]), .Y(n2871) );
NAND2X1TS U3663 ( .A(n2872), .B(n2871), .Y(n2922) );
AOI22X1TS U3664 ( .A0(n3894), .A1(n2934), .B0(n3009), .B1(n2922), .Y(n2876)
);
AOI22X1TS U3665 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n2895), .B0(n2954), .B1(
DmP_mant_SHT1_SW[5]), .Y(n2873) );
AOI22X1TS U3666 ( .A0(n3108), .A1(n2920), .B0(n3889), .B1(Data_array_SWR[7]),
.Y(n2875) );
INVX2TS U3667 ( .A(n2825), .Y(n3100) );
AOI22X1TS U3668 ( .A0(Raw_mant_NRM_SWR[40]), .A1(n2989), .B0(n2988), .B1(
DmP_mant_SHT1_SW[12]), .Y(n2879) );
NAND2X1TS U3669 ( .A(n2879), .B(n2878), .Y(n3065) );
INVX2TS U3670 ( .A(n3065), .Y(n2888) );
INVX2TS U3671 ( .A(n1941), .Y(n2930) );
AOI22X1TS U3672 ( .A0(Raw_mant_NRM_SWR[39]), .A1(n2895), .B0(n2954), .B1(
DmP_mant_SHT1_SW[13]), .Y(n2881) );
NAND2X1TS U3673 ( .A(n2958), .B(Raw_mant_NRM_SWR[15]), .Y(n2880) );
NAND2X1TS U3674 ( .A(n2881), .B(n2880), .Y(n3062) );
CLKBUFX2TS U3675 ( .A(n2980), .Y(n3094) );
AOI22X1TS U3676 ( .A0(Raw_mant_NRM_SWR[41]), .A1(n2999), .B0(n2998), .B1(
DmP_mant_SHT1_SW[11]), .Y(n2883) );
NAND2X1TS U3677 ( .A(n2889), .B(Raw_mant_NRM_SWR[13]), .Y(n2882) );
NAND2X1TS U3678 ( .A(n2883), .B(n2882), .Y(n3007) );
AOI22X1TS U3679 ( .A0(n2930), .A1(n3062), .B0(n3094), .B1(n3007), .Y(n2887)
);
AOI22X1TS U3680 ( .A0(Raw_mant_NRM_SWR[42]), .A1(n2999), .B0(n2998), .B1(
DmP_mant_SHT1_SW[10]), .Y(n2885) );
NAND2X1TS U3681 ( .A(n2889), .B(Raw_mant_NRM_SWR[12]), .Y(n2884) );
NAND2X1TS U3682 ( .A(n2885), .B(n2884), .Y(n3008) );
AOI22X1TS U3683 ( .A0(n2925), .A1(n3008), .B0(n3123), .B1(Data_array_SWR[12]), .Y(n2886) );
AOI22X1TS U3684 ( .A0(Raw_mant_NRM_SWR[43]), .A1(n2999), .B0(n2998), .B1(
DmP_mant_SHT1_SW[9]), .Y(n2891) );
NAND2X1TS U3685 ( .A(n2889), .B(Raw_mant_NRM_SWR[11]), .Y(n2890) );
NAND2X1TS U3686 ( .A(n2891), .B(n2890), .Y(n3010) );
INVX2TS U3687 ( .A(n3010), .Y(n2894) );
AOI22X1TS U3688 ( .A0(n2930), .A1(n3008), .B0(n3113), .B1(n2934), .Y(n2893)
);
AOI22X1TS U3689 ( .A0(n2925), .A1(n2912), .B0(n3064), .B1(Data_array_SWR[9]),
.Y(n2892) );
INVX2TS U3690 ( .A(n3062), .Y(n2900) );
AOI22X1TS U3691 ( .A0(Raw_mant_NRM_SWR[38]), .A1(n2895), .B0(n2957), .B1(
DmP_mant_SHT1_SW[14]), .Y(n2897) );
NAND2X1TS U3692 ( .A(n2958), .B(Raw_mant_NRM_SWR[16]), .Y(n2896) );
NAND2X1TS U3693 ( .A(n2897), .B(n2896), .Y(n3061) );
AOI22X1TS U3694 ( .A0(n2930), .A1(n3061), .B0(n3094), .B1(n3065), .Y(n2899)
);
AOI22X1TS U3695 ( .A0(n2925), .A1(n3007), .B0(n3064), .B1(Data_array_SWR[13]), .Y(n2898) );
INVX2TS U3696 ( .A(n2934), .Y(n2903) );
AOI22X1TS U3697 ( .A0(n2930), .A1(n3010), .B0(n3094), .B1(n2912), .Y(n2902)
);
AOI22X1TS U3698 ( .A0(n2925), .A1(n2922), .B0(n3064), .B1(Data_array_SWR[8]),
.Y(n2901) );
AOI22X1TS U3699 ( .A0(n2930), .A1(n3877), .B0(n3113), .B1(n3879), .Y(n2905)
);
AOI22X1TS U3700 ( .A0(n2925), .A1(n3042), .B0(n2923), .B1(Data_array_SWR[51]), .Y(n2904) );
AOI22X1TS U3701 ( .A0(Raw_mant_NRM_SWR[48]), .A1(n2948), .B0(n3017), .B1(
DmP_mant_SHT1_SW[4]), .Y(n2908) );
NAND2X1TS U3702 ( .A(n2908), .B(n2907), .Y(n2921) );
AOI22X1TS U3703 ( .A0(n2930), .A1(n2921), .B0(n3113), .B1(n2916), .Y(n2910)
);
AOI22X1TS U3704 ( .A0(n2925), .A1(n3893), .B0(n2923), .B1(Data_array_SWR[3]),
.Y(n2909) );
INVX2TS U3705 ( .A(n2922), .Y(n2915) );
AOI22X1TS U3706 ( .A0(n2930), .A1(n2912), .B0(n3094), .B1(n2920), .Y(n2914)
);
AOI22X1TS U3707 ( .A0(n2925), .A1(n2921), .B0(n3064), .B1(Data_array_SWR[6]),
.Y(n2913) );
INVX2TS U3708 ( .A(n2921), .Y(n2919) );
AOI22X1TS U3709 ( .A0(n2930), .A1(n2920), .B0(n3094), .B1(n2924), .Y(n2918)
);
AOI22X1TS U3710 ( .A0(n2925), .A1(n2916), .B0(n2923), .B1(Data_array_SWR[4]),
.Y(n2917) );
INVX2TS U3711 ( .A(n2920), .Y(n2928) );
AOI22X1TS U3712 ( .A0(n2930), .A1(n2922), .B0(n3113), .B1(n2921), .Y(n2927)
);
AOI22X1TS U3713 ( .A0(n2925), .A1(n2924), .B0(n2923), .B1(Data_array_SWR[5]),
.Y(n2926) );
INVX2TS U3714 ( .A(n3153), .Y(n3878) );
AOI22X1TS U3715 ( .A0(n2825), .A1(n3085), .B0(n3878), .B1(Data_array_SWR[27]), .Y(n2932) );
NAND2X1TS U3716 ( .A(n2930), .B(n3107), .Y(n2931) );
INVX2TS U3717 ( .A(n3008), .Y(n2937) );
INVX2TS U3718 ( .A(n1941), .Y(n3110) );
AOI22X1TS U3719 ( .A0(n3110), .A1(n3007), .B0(n3009), .B1(n3010), .Y(n2936)
);
INVX2TS U3720 ( .A(n3153), .Y(n3111) );
AOI22X1TS U3721 ( .A0(n3108), .A1(n2934), .B0(n3111), .B1(Data_array_SWR[10]), .Y(n2935) );
INVX2TS U3722 ( .A(n3897), .Y(n3117) );
INVX2TS U3723 ( .A(n3051), .Y(n2941) );
AOI22X1TS U3724 ( .A0(n3110), .A1(n3049), .B0(n3009), .B1(n3121), .Y(n2940)
);
INVX2TS U3725 ( .A(n1942), .Y(n3880) );
AOI22X1TS U3726 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n2989), .B0(n2998), .B1(
DmP_mant_SHT1_SW[41]), .Y(n2938) );
AOI22X1TS U3727 ( .A0(n3880), .A1(n3118), .B0(n3111), .B1(Data_array_SWR[43]), .Y(n2939) );
AOI22X1TS U3728 ( .A0(Raw_mant_NRM_SWR[33]), .A1(n2989), .B0(n2988), .B1(
DmP_mant_SHT1_SW[19]), .Y(n2943) );
NAND2X1TS U3729 ( .A(n3000), .B(Raw_mant_NRM_SWR[21]), .Y(n2942) );
NAND2X1TS U3730 ( .A(n2943), .B(n2942), .Y(n3070) );
INVX2TS U3731 ( .A(n3070), .Y(n2953) );
INVX2TS U3732 ( .A(n1941), .Y(n3122) );
AOI22X1TS U3733 ( .A0(Raw_mant_NRM_SWR[32]), .A1(n2999), .B0(n2998), .B1(
DmP_mant_SHT1_SW[20]), .Y(n2945) );
NAND2X1TS U3734 ( .A(n3000), .B(Raw_mant_NRM_SWR[22]), .Y(n2944) );
NAND2X1TS U3735 ( .A(n2945), .B(n2944), .Y(n3069) );
AOI22X1TS U3736 ( .A0(Raw_mant_NRM_SWR[34]), .A1(n3018), .B0(n2988), .B1(
DmP_mant_SHT1_SW[18]), .Y(n2947) );
NAND2X1TS U3737 ( .A(n2947), .B(n2946), .Y(n3055) );
AOI22X1TS U3738 ( .A0(n3122), .A1(n3069), .B0(n3094), .B1(n3055), .Y(n2952)
);
AOI22X1TS U3739 ( .A0(Raw_mant_NRM_SWR[35]), .A1(n2948), .B0(n3017), .B1(
DmP_mant_SHT1_SW[17]), .Y(n2950) );
NAND2X1TS U3740 ( .A(n2950), .B(n2949), .Y(n3056) );
AOI22X1TS U3741 ( .A0(n3125), .A1(n3056), .B0(n3064), .B1(Data_array_SWR[19]), .Y(n2951) );
AOI22X1TS U3742 ( .A0(Raw_mant_NRM_SWR[36]), .A1(n3890), .B0(n2954), .B1(
DmP_mant_SHT1_SW[16]), .Y(n2956) );
NAND2X1TS U3743 ( .A(n2958), .B(Raw_mant_NRM_SWR[18]), .Y(n2955) );
NAND2X1TS U3744 ( .A(n2956), .B(n2955), .Y(n3057) );
INVX2TS U3745 ( .A(n3057), .Y(n2963) );
INVX2TS U3746 ( .A(n1941), .Y(n3086) );
AOI22X1TS U3747 ( .A0(Raw_mant_NRM_SWR[37]), .A1(n3890), .B0(n2957), .B1(
DmP_mant_SHT1_SW[15]), .Y(n2960) );
NAND2X1TS U3748 ( .A(n2960), .B(n2959), .Y(n3063) );
AOI22X1TS U3749 ( .A0(n3086), .A1(n3056), .B0(n3094), .B1(n3063), .Y(n2962)
);
AOI22X1TS U3750 ( .A0(n3125), .A1(n3061), .B0(n3064), .B1(Data_array_SWR[16]), .Y(n2961) );
AOI22X1TS U3751 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n2989), .B0(n2988), .B1(
DmP_mant_SHT1_SW[40]), .Y(n2965) );
NAND2X1TS U3752 ( .A(n3000), .B(Raw_mant_NRM_SWR[42]), .Y(n2964) );
NAND2X1TS U3753 ( .A(n2965), .B(n2964), .Y(n3119) );
INVX2TS U3754 ( .A(n3119), .Y(n2972) );
AOI22X1TS U3755 ( .A0(Raw_mant_NRM_SWR[13]), .A1(n3018), .B0(n3017), .B1(
DmP_mant_SHT1_SW[39]), .Y(n2967) );
NAND2X1TS U3756 ( .A(n2967), .B(n2966), .Y(n3124) );
AOI22X1TS U3757 ( .A0(n3122), .A1(n3118), .B0(n3120), .B1(n3124), .Y(n2971)
);
AOI22X1TS U3758 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n3018), .B0(n3017), .B1(
DmP_mant_SHT1_SW[38]), .Y(n2969) );
NAND2X1TS U3759 ( .A(n2969), .B(n2968), .Y(n3095) );
AOI22X1TS U3760 ( .A0(n3081), .A1(n3095), .B0(n3123), .B1(Data_array_SWR[40]), .Y(n2970) );
INVX2TS U3761 ( .A(n3063), .Y(n2975) );
AOI22X1TS U3762 ( .A0(n3110), .A1(n3057), .B0(n2980), .B1(n3061), .Y(n2974)
);
AOI22X1TS U3763 ( .A0(n3108), .A1(n3062), .B0(n3111), .B1(Data_array_SWR[15]), .Y(n2973) );
AOI22X1TS U3764 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n3018), .B0(n3017), .B1(
DmP_mant_SHT1_SW[35]), .Y(n2977) );
NAND2X1TS U3765 ( .A(n2977), .B(n2976), .Y(n3096) );
INVX2TS U3766 ( .A(n3096), .Y(n2987) );
AOI22X1TS U3767 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n3018), .B0(n3017), .B1(
DmP_mant_SHT1_SW[36]), .Y(n2979) );
NAND2X1TS U3768 ( .A(n2979), .B(n2978), .Y(n3093) );
CLKBUFX2TS U3769 ( .A(n2980), .Y(n3876) );
AOI22X1TS U3770 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n3018), .B0(n2998), .B1(
DmP_mant_SHT1_SW[34]), .Y(n2983) );
NAND2X1TS U3771 ( .A(n2983), .B(n2982), .Y(n3103) );
AOI22X1TS U3772 ( .A0(n3086), .A1(n3093), .B0(n3876), .B1(n3103), .Y(n2986)
);
AOI22X1TS U3773 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n3018), .B0(n3017), .B1(
DmP_mant_SHT1_SW[33]), .Y(n2984) );
AOI22X1TS U3774 ( .A0(n3880), .A1(n3101), .B0(n3878), .B1(Data_array_SWR[35]), .Y(n2985) );
AOI22X1TS U3775 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n2989), .B0(n2988), .B1(
DmP_mant_SHT1_SW[31]), .Y(n2991) );
NAND2X1TS U3776 ( .A(n3000), .B(Raw_mant_NRM_SWR[33]), .Y(n2990) );
NAND2X1TS U3777 ( .A(n2991), .B(n2990), .Y(n3109) );
INVX2TS U3778 ( .A(n3109), .Y(n2997) );
AOI22X1TS U3779 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n3018), .B0(n3017), .B1(
DmP_mant_SHT1_SW[32]), .Y(n2994) );
NAND2X1TS U3780 ( .A(n2992), .B(Raw_mant_NRM_SWR[34]), .Y(n2993) );
NAND2X1TS U3781 ( .A(n2994), .B(n2993), .Y(n3102) );
AOI22X1TS U3782 ( .A0(n3086), .A1(n3102), .B0(n3876), .B1(n3023), .Y(n2996)
);
AOI22X1TS U3783 ( .A0(n3081), .A1(n3112), .B0(n3878), .B1(Data_array_SWR[31]), .Y(n2995) );
INVX2TS U3784 ( .A(n3075), .Y(n3005) );
AOI22X1TS U3785 ( .A0(Raw_mant_NRM_SWR[31]), .A1(n2999), .B0(n2998), .B1(
DmP_mant_SHT1_SW[21]), .Y(n3002) );
NAND2X1TS U3786 ( .A(n3002), .B(n3001), .Y(n3077) );
AOI22X1TS U3787 ( .A0(n3110), .A1(n3074), .B0(n3009), .B1(n3077), .Y(n3004)
);
AOI22X1TS U3788 ( .A0(n3880), .A1(n3069), .B0(n3111), .B1(Data_array_SWR[22]), .Y(n3003) );
INVX2TS U3789 ( .A(n3007), .Y(n3013) );
AOI22X1TS U3790 ( .A0(n3110), .A1(n3065), .B0(n3009), .B1(n3008), .Y(n3012)
);
AOI22X1TS U3791 ( .A0(n3880), .A1(n3010), .B0(n3111), .B1(Data_array_SWR[11]), .Y(n3011) );
INVX2TS U3792 ( .A(n3103), .Y(n3016) );
AOI22X1TS U3793 ( .A0(n3086), .A1(n3096), .B0(n3876), .B1(n3101), .Y(n3015)
);
AOI22X1TS U3794 ( .A0(n3081), .A1(n3102), .B0(n3878), .B1(Data_array_SWR[34]), .Y(n3014) );
INVX2TS U3795 ( .A(n3093), .Y(n3022) );
AOI22X1TS U3796 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n3018), .B0(n3017), .B1(
DmP_mant_SHT1_SW[37]), .Y(n3019) );
AOI22X1TS U3797 ( .A0(n3086), .A1(n3092), .B0(n3120), .B1(n3096), .Y(n3021)
);
AOI22X1TS U3798 ( .A0(n3081), .A1(n3103), .B0(n3878), .B1(Data_array_SWR[36]), .Y(n3020) );
INVX2TS U3799 ( .A(n3102), .Y(n3026) );
AOI22X1TS U3800 ( .A0(n3122), .A1(n3101), .B0(n3120), .B1(n3109), .Y(n3025)
);
AOI22X1TS U3801 ( .A0(n3081), .A1(n3023), .B0(n3123), .B1(Data_array_SWR[32]), .Y(n3024) );
INVX2TS U3802 ( .A(n3069), .Y(n3029) );
AOI22X1TS U3803 ( .A0(n3086), .A1(n3077), .B0(n3876), .B1(n3070), .Y(n3028)
);
AOI22X1TS U3804 ( .A0(n3880), .A1(n3055), .B0(n3878), .B1(Data_array_SWR[20]), .Y(n3027) );
INVX2TS U3805 ( .A(n3124), .Y(n3032) );
AOI22X1TS U3806 ( .A0(n3086), .A1(n3119), .B0(n3876), .B1(n3095), .Y(n3031)
);
AOI22X1TS U3807 ( .A0(n3081), .A1(n3092), .B0(n3878), .B1(Data_array_SWR[39]), .Y(n3030) );
INVX2TS U3808 ( .A(n3095), .Y(n3035) );
AOI22X1TS U3809 ( .A0(n3086), .A1(n3124), .B0(n3120), .B1(n3092), .Y(n3034)
);
AOI22X1TS U3810 ( .A0(n3081), .A1(n3093), .B0(n3878), .B1(Data_array_SWR[38]), .Y(n3033) );
INVX2TS U3811 ( .A(n3056), .Y(n3038) );
AOI22X1TS U3812 ( .A0(n3122), .A1(n3055), .B0(n3094), .B1(n3057), .Y(n3037)
);
AOI22X1TS U3813 ( .A0(n3125), .A1(n3063), .B0(n3064), .B1(Data_array_SWR[17]), .Y(n3036) );
INVX2TS U3814 ( .A(n3121), .Y(n3041) );
AOI22X1TS U3815 ( .A0(n3110), .A1(n3051), .B0(n3876), .B1(n3118), .Y(n3040)
);
AOI22X1TS U3816 ( .A0(n3880), .A1(n3119), .B0(n3111), .B1(Data_array_SWR[42]), .Y(n3039) );
INVX2TS U3817 ( .A(n3042), .Y(n3047) );
AOI22X1TS U3818 ( .A0(n3122), .A1(n3879), .B0(n3120), .B1(n3043), .Y(n3046)
);
AOI22X1TS U3819 ( .A0(n3081), .A1(n3044), .B0(n3123), .B1(Data_array_SWR[49]), .Y(n3045) );
INVX2TS U3820 ( .A(n3048), .Y(n3054) );
AOI22X1TS U3821 ( .A0(n3110), .A1(n3050), .B0(n3876), .B1(n3049), .Y(n3053)
);
AOI22X1TS U3822 ( .A0(n3880), .A1(n3051), .B0(n3111), .B1(Data_array_SWR[45]), .Y(n3052) );
INVX2TS U3823 ( .A(n3055), .Y(n3060) );
AOI22X1TS U3824 ( .A0(n3122), .A1(n3070), .B0(n3120), .B1(n3056), .Y(n3059)
);
AOI22X1TS U3825 ( .A0(n3125), .A1(n3057), .B0(n3064), .B1(Data_array_SWR[18]), .Y(n3058) );
INVX2TS U3826 ( .A(n3061), .Y(n3068) );
AOI22X1TS U3827 ( .A0(n3122), .A1(n3063), .B0(n3094), .B1(n3062), .Y(n3067)
);
AOI22X1TS U3828 ( .A0(n3125), .A1(n3065), .B0(n3064), .B1(Data_array_SWR[14]), .Y(n3066) );
INVX2TS U3829 ( .A(n3077), .Y(n3073) );
AOI22X1TS U3830 ( .A0(n3110), .A1(n3075), .B0(n3876), .B1(n3069), .Y(n3072)
);
AOI22X1TS U3831 ( .A0(n3880), .A1(n3070), .B0(n3111), .B1(Data_array_SWR[21]), .Y(n3071) );
INVX2TS U3832 ( .A(n3074), .Y(n3080) );
AOI22X1TS U3833 ( .A0(n3110), .A1(n3076), .B0(n3876), .B1(n3075), .Y(n3079)
);
AOI22X1TS U3834 ( .A0(n3880), .A1(n3077), .B0(n3111), .B1(Data_array_SWR[23]), .Y(n3078) );
INVX2TS U3835 ( .A(n3107), .Y(n3084) );
AOI22X1TS U3836 ( .A0(n3086), .A1(n3112), .B0(n3120), .B1(n3085), .Y(n3083)
);
AOI22X1TS U3837 ( .A0(n3081), .A1(n3087), .B0(n3123), .B1(Data_array_SWR[28]), .Y(n3082) );
AOI22X1TS U3838 ( .A0(n3086), .A1(n3085), .B0(n3878), .B1(Data_array_SWR[26]), .Y(n3089) );
NAND2X1TS U3839 ( .A(n3897), .B(n3087), .Y(n3088) );
INVX2TS U3840 ( .A(n3092), .Y(n3099) );
AOI22X1TS U3841 ( .A0(n3122), .A1(n3095), .B0(n3094), .B1(n3093), .Y(n3098)
);
AOI22X1TS U3842 ( .A0(n3125), .A1(n3096), .B0(n3123), .B1(Data_array_SWR[37]), .Y(n3097) );
INVX2TS U3843 ( .A(n3101), .Y(n3106) );
AOI22X1TS U3844 ( .A0(n3122), .A1(n3103), .B0(n3120), .B1(n3102), .Y(n3105)
);
AOI22X1TS U3845 ( .A0(n3125), .A1(n3109), .B0(n3123), .B1(Data_array_SWR[33]), .Y(n3104) );
AOI22X1TS U3846 ( .A0(n3110), .A1(n3109), .B0(n3108), .B1(n3107), .Y(n3115)
);
AOI22X1TS U3847 ( .A0(n3113), .A1(n3112), .B0(n3111), .B1(Data_array_SWR[30]), .Y(n3114) );
INVX2TS U3848 ( .A(n3118), .Y(n3128) );
AOI22X1TS U3849 ( .A0(n3122), .A1(n3121), .B0(n3120), .B1(n3119), .Y(n3127)
);
AOI22X1TS U3850 ( .A0(n3125), .A1(n3124), .B0(n3123), .B1(Data_array_SWR[41]), .Y(n3126) );
AOI22X1TS U3851 ( .A0(n3149), .A1(n3157), .B0(final_result_ieee[5]), .B1(
n4011), .Y(n3132) );
AOI22X1TS U3852 ( .A0(n3149), .A1(n3158), .B0(final_result_ieee[7]), .B1(
n3141), .Y(n3133) );
AOI22X1TS U3853 ( .A0(n3149), .A1(n3172), .B0(final_result_ieee[6]), .B1(
n3141), .Y(n3134) );
AOI22X1TS U3854 ( .A0(n3149), .A1(n3160), .B0(final_result_ieee[29]), .B1(
n3914), .Y(n3135) );
AOI22X1TS U3855 ( .A0(n3149), .A1(n3136), .B0(final_result_ieee[49]), .B1(
n4011), .Y(n3137) );
AOI22X1TS U3856 ( .A0(n1905), .A1(n3155), .B0(final_result_ieee[17]), .B1(
n3141), .Y(n3139) );
AOI22X1TS U3857 ( .A0(n1905), .A1(n3189), .B0(final_result_ieee[9]), .B1(
n3141), .Y(n3140) );
AOI22X1TS U3858 ( .A0(n1905), .A1(n3186), .B0(final_result_ieee[8]), .B1(
n3141), .Y(n3142) );
AOI22X1TS U3859 ( .A0(n3149), .A1(n3162), .B0(final_result_ieee[50]), .B1(
n4011), .Y(n3143) );
AOI22X1TS U3860 ( .A0(n3149), .A1(n3159), .B0(final_result_ieee[28]), .B1(
n3914), .Y(n3144) );
AOI22X1TS U3861 ( .A0(n3149), .A1(n3145), .B0(final_result_ieee[51]), .B1(
n3914), .Y(n3146) );
AOI22X1TS U3862 ( .A0(n3149), .A1(n3161), .B0(final_result_ieee[26]), .B1(
n3914), .Y(n3148) );
AOI22X1TS U3863 ( .A0(n3149), .A1(n3154), .B0(final_result_ieee[27]), .B1(
n3914), .Y(n3150) );
OAI21XLTS U3864 ( .A0(n1921), .A1(DP_OP_15J2_122_2221_n35), .B0(n3151), .Y(
n1276) );
OAI21XLTS U3865 ( .A0(n3153), .A1(n4210), .B0(n3151), .Y(n1754) );
OAI21XLTS U3866 ( .A0(n3153), .A1(n4126), .B0(n3152), .Y(n1753) );
INVX2TS U3867 ( .A(n3154), .Y(n3164) );
INVX2TS U3868 ( .A(n3977), .Y(n3180) );
OAI222X1TS U3869 ( .A0(n3194), .A1(n3164), .B0(n4272), .B1(n3180), .C0(n3193), .C1(n3163), .Y(n1127) );
INVX2TS U3870 ( .A(n3167), .Y(n3184) );
INVX2TS U3871 ( .A(n3155), .Y(n3175) );
INVX2TS U3872 ( .A(n3156), .Y(n3183) );
OAI222X1TS U3873 ( .A0(n3184), .A1(n3175), .B0(n4270), .B1(n3180), .C0(n3183), .C1(n3176), .Y(n1121) );
INVX2TS U3874 ( .A(n3977), .Y(n3198) );
OAI222X1TS U3875 ( .A0(n3169), .A1(n3194), .B0(n4267), .B1(n3198), .C0(n3168), .C1(n3193), .Y(n1109) );
OAI222X1TS U3876 ( .A0(n3171), .A1(n3194), .B0(n4268), .B1(n3198), .C0(n3170), .C1(n3184), .Y(n1111) );
INVX2TS U3877 ( .A(n3159), .Y(n3178) );
OAI222X1TS U3878 ( .A0(n3183), .A1(n3178), .B0(n4265), .B1(n3180), .C0(n3193), .C1(n3177), .Y(n1126) );
INVX2TS U3879 ( .A(n3160), .Y(n3181) );
OAI222X1TS U3880 ( .A0(n3183), .A1(n3181), .B0(n4271), .B1(n3180), .C0(n3193), .C1(n3179), .Y(n1125) );
INVX2TS U3881 ( .A(n3161), .Y(n3166) );
OAI222X1TS U3882 ( .A0(n3183), .A1(n3166), .B0(n4266), .B1(n3180), .C0(n3193), .C1(n3165), .Y(n1128) );
INVX2TS U3883 ( .A(n3977), .Y(n4009) );
INVX2TS U3884 ( .A(n3162), .Y(n3174) );
OAI222X1TS U3885 ( .A0(n3184), .A1(n3173), .B0(n4263), .B1(n4009), .C0(n3183), .C1(n3174), .Y(n1104) );
OAI222X1TS U3886 ( .A0(n3184), .A1(n3164), .B0(n4252), .B1(n3180), .C0(n3183), .C1(n3163), .Y(n1131) );
OAI222X1TS U3887 ( .A0(n3184), .A1(n3166), .B0(n4251), .B1(n3180), .C0(n3183), .C1(n3165), .Y(n1130) );
INVX2TS U3888 ( .A(n3167), .Y(n3191) );
OAI222X1TS U3889 ( .A0(n3169), .A1(n3191), .B0(n4260), .B1(n4009), .C0(n3168), .C1(n3183), .Y(n1149) );
OAI222X1TS U3890 ( .A0(n3171), .A1(n3191), .B0(n4258), .B1(n4009), .C0(n3170), .C1(n3183), .Y(n1147) );
OAI222X1TS U3891 ( .A0(n3182), .A1(n3191), .B0(n4259), .B1(n4009), .C0(n3190), .C1(n3185), .Y(n1148) );
OAI222X1TS U3892 ( .A0(n3184), .A1(n3174), .B0(n4261), .B1(n4009), .C0(n3190), .C1(n3173), .Y(n1154) );
OAI222X1TS U3893 ( .A0(n3184), .A1(n3176), .B0(n4255), .B1(n3180), .C0(n3190), .C1(n3175), .Y(n1137) );
OAI222X1TS U3894 ( .A0(n3184), .A1(n3178), .B0(n4253), .B1(n3180), .C0(n3190), .C1(n3177), .Y(n1132) );
OAI222X1TS U3895 ( .A0(n3184), .A1(n3181), .B0(n4254), .B1(n3180), .C0(n3190), .C1(n3179), .Y(n1133) );
OAI222X1TS U3896 ( .A0(n3185), .A1(n3184), .B0(n4051), .B1(n3198), .C0(n3183), .C1(n3182), .Y(n1110) );
INVX2TS U3897 ( .A(n3186), .Y(n3187) );
OAI222X1TS U3898 ( .A0(n3188), .A1(n3191), .B0(n4257), .B1(n4009), .C0(n3190), .C1(n3187), .Y(n1146) );
OAI222X1TS U3899 ( .A0(n3188), .A1(n3194), .B0(n4264), .B1(n3198), .C0(n3193), .C1(n3187), .Y(n1112) );
INVX2TS U3900 ( .A(n3189), .Y(n3192) );
OAI222X1TS U3901 ( .A0(n3195), .A1(n3191), .B0(n4256), .B1(n4009), .C0(n3190), .C1(n3192), .Y(n1145) );
OAI222X1TS U3902 ( .A0(n3195), .A1(n3194), .B0(n4269), .B1(n3198), .C0(n3193), .C1(n3192), .Y(n1113) );
CLKBUFX2TS U3903 ( .A(n4359), .Y(n4276) );
NOR2XLTS U3904 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n3196) );
INVX2TS U3905 ( .A(n4002), .Y(n3202) );
MX2X1TS U3906 ( .A(DMP_SFG[51]), .B(DMP_SHT2_EWSW[51]), .S0(n3202), .Y(n1454) );
MX2X1TS U3907 ( .A(DMP_SFG[50]), .B(DMP_SHT2_EWSW[50]), .S0(n3198), .Y(n1457) );
MX2X1TS U3908 ( .A(DMP_SFG[49]), .B(DMP_SHT2_EWSW[49]), .S0(n3198), .Y(n1460) );
MX2X1TS U3909 ( .A(DMP_SFG[48]), .B(DMP_SHT2_EWSW[48]), .S0(n3198), .Y(n1463) );
MX2X1TS U3910 ( .A(DMP_SFG[47]), .B(DMP_SHT2_EWSW[47]), .S0(n3198), .Y(n1466) );
MX2X1TS U3911 ( .A(DMP_SFG[46]), .B(DMP_SHT2_EWSW[46]), .S0(n3198), .Y(n1469) );
INVX2TS U3912 ( .A(n3977), .Y(n3199) );
MX2X1TS U3913 ( .A(DMP_SFG[45]), .B(DMP_SHT2_EWSW[45]), .S0(n3199), .Y(n1472) );
MX2X1TS U3914 ( .A(DMP_SFG[44]), .B(DMP_SHT2_EWSW[44]), .S0(n3199), .Y(n1475) );
MX2X1TS U3915 ( .A(DMP_SFG[43]), .B(DMP_SHT2_EWSW[43]), .S0(n3199), .Y(n1478) );
MX2X1TS U3916 ( .A(DMP_SFG[42]), .B(DMP_SHT2_EWSW[42]), .S0(n3199), .Y(n1481) );
MX2X1TS U3917 ( .A(DMP_SFG[41]), .B(DMP_SHT2_EWSW[41]), .S0(n3199), .Y(n1484) );
MX2X1TS U3918 ( .A(DMP_SFG[40]), .B(DMP_SHT2_EWSW[40]), .S0(n3199), .Y(n1487) );
MX2X1TS U3919 ( .A(DMP_SFG[39]), .B(DMP_SHT2_EWSW[39]), .S0(n3199), .Y(n1490) );
MX2X1TS U3920 ( .A(DMP_SFG[38]), .B(DMP_SHT2_EWSW[38]), .S0(n3199), .Y(n1493) );
MX2X1TS U3921 ( .A(DMP_SFG[37]), .B(DMP_SHT2_EWSW[37]), .S0(n3199), .Y(n1496) );
MX2X1TS U3922 ( .A(DMP_SFG[36]), .B(DMP_SHT2_EWSW[36]), .S0(n3199), .Y(n1499) );
INVX2TS U3923 ( .A(n3977), .Y(n3200) );
MX2X1TS U3924 ( .A(DMP_SFG[35]), .B(DMP_SHT2_EWSW[35]), .S0(n3200), .Y(n1502) );
MX2X1TS U3925 ( .A(DMP_SHT2_EWSW[34]), .B(DMP_SHT1_EWSW[34]), .S0(n3205),
.Y(n1506) );
MX2X1TS U3926 ( .A(DMP_SFG[34]), .B(DMP_SHT2_EWSW[34]), .S0(n3200), .Y(n1505) );
CLKBUFX2TS U3927 ( .A(n4262), .Y(n3972) );
INVX2TS U3928 ( .A(n3972), .Y(n3970) );
MX2X1TS U3929 ( .A(DMP_SHT2_EWSW[33]), .B(DMP_SHT1_EWSW[33]), .S0(n3970),
.Y(n1509) );
MX2X1TS U3930 ( .A(DMP_SFG[33]), .B(DMP_SHT2_EWSW[33]), .S0(n3200), .Y(n1508) );
MX2X1TS U3931 ( .A(DMP_SHT2_EWSW[32]), .B(DMP_SHT1_EWSW[32]), .S0(n3970),
.Y(n1512) );
MX2X1TS U3932 ( .A(DMP_SFG[32]), .B(DMP_SHT2_EWSW[32]), .S0(n3200), .Y(n1511) );
MX2X1TS U3933 ( .A(DMP_SHT2_EWSW[31]), .B(DMP_SHT1_EWSW[31]), .S0(n3970),
.Y(n1515) );
MX2X1TS U3934 ( .A(DMP_SFG[31]), .B(DMP_SHT2_EWSW[31]), .S0(n3200), .Y(n1514) );
MX2X1TS U3935 ( .A(DMP_SHT2_EWSW[30]), .B(DMP_SHT1_EWSW[30]), .S0(n3970),
.Y(n1518) );
MX2X1TS U3936 ( .A(DMP_SFG[30]), .B(DMP_SHT2_EWSW[30]), .S0(n3200), .Y(n1517) );
MX2X1TS U3937 ( .A(DMP_SHT2_EWSW[29]), .B(DMP_SHT1_EWSW[29]), .S0(n3970),
.Y(n1521) );
MX2X1TS U3938 ( .A(DMP_SFG[29]), .B(DMP_SHT2_EWSW[29]), .S0(n3200), .Y(n1520) );
MX2X1TS U3939 ( .A(DMP_SHT2_EWSW[28]), .B(DMP_SHT1_EWSW[28]), .S0(n3970),
.Y(n1524) );
MX2X1TS U3940 ( .A(DMP_SFG[28]), .B(DMP_SHT2_EWSW[28]), .S0(n3200), .Y(n1523) );
INVX2TS U3941 ( .A(n3972), .Y(n3201) );
MX2X1TS U3942 ( .A(DMP_SHT2_EWSW[27]), .B(DMP_SHT1_EWSW[27]), .S0(n3201),
.Y(n1527) );
MX2X1TS U3943 ( .A(DMP_SFG[27]), .B(DMP_SHT2_EWSW[27]), .S0(n3200), .Y(n1526) );
MX2X1TS U3944 ( .A(DMP_SHT2_EWSW[26]), .B(DMP_SHT1_EWSW[26]), .S0(n3201),
.Y(n1530) );
MX2X1TS U3945 ( .A(DMP_SFG[26]), .B(DMP_SHT2_EWSW[26]), .S0(n3200), .Y(n1529) );
MX2X1TS U3946 ( .A(DMP_SHT2_EWSW[25]), .B(DMP_SHT1_EWSW[25]), .S0(n3201),
.Y(n1533) );
MX2X1TS U3947 ( .A(DMP_SFG[25]), .B(DMP_SHT2_EWSW[25]), .S0(n3202), .Y(n1532) );
MX2X1TS U3948 ( .A(DMP_SHT2_EWSW[24]), .B(DMP_SHT1_EWSW[24]), .S0(n3201),
.Y(n1536) );
MX2X1TS U3949 ( .A(DMP_SFG[24]), .B(DMP_SHT2_EWSW[24]), .S0(n3202), .Y(n1535) );
MX2X1TS U3950 ( .A(DMP_SHT2_EWSW[23]), .B(DMP_SHT1_EWSW[23]), .S0(n3201),
.Y(n1539) );
MX2X1TS U3951 ( .A(DMP_SFG[23]), .B(DMP_SHT2_EWSW[23]), .S0(n3202), .Y(n1538) );
MX2X1TS U3952 ( .A(DMP_SHT2_EWSW[22]), .B(DMP_SHT1_EWSW[22]), .S0(n3201),
.Y(n1542) );
MX2X1TS U3953 ( .A(DMP_SFG[22]), .B(DMP_SHT2_EWSW[22]), .S0(n3202), .Y(n1541) );
MX2X1TS U3954 ( .A(DMP_SHT2_EWSW[21]), .B(DMP_SHT1_EWSW[21]), .S0(n3201),
.Y(n1545) );
MX2X1TS U3955 ( .A(DMP_SFG[21]), .B(DMP_SHT2_EWSW[21]), .S0(n3202), .Y(n1544) );
MX2X1TS U3956 ( .A(DMP_SHT2_EWSW[20]), .B(DMP_SHT1_EWSW[20]), .S0(n3201),
.Y(n1548) );
MX2X1TS U3957 ( .A(DMP_SFG[20]), .B(DMP_SHT2_EWSW[20]), .S0(n3202), .Y(n1547) );
INVX2TS U3958 ( .A(n3972), .Y(n3203) );
MX2X1TS U3959 ( .A(DMP_SHT2_EWSW[19]), .B(DMP_SHT1_EWSW[19]), .S0(n3203),
.Y(n1551) );
MX2X1TS U3960 ( .A(DMP_SFG[19]), .B(DMP_SHT2_EWSW[19]), .S0(n3202), .Y(n1550) );
MX2X1TS U3961 ( .A(DMP_SHT2_EWSW[18]), .B(DMP_SHT1_EWSW[18]), .S0(n3201),
.Y(n1554) );
MX2X1TS U3962 ( .A(DMP_SFG[18]), .B(DMP_SHT2_EWSW[18]), .S0(n3202), .Y(n1553) );
MX2X1TS U3963 ( .A(DMP_SHT2_EWSW[17]), .B(DMP_SHT1_EWSW[17]), .S0(n3201),
.Y(n1557) );
MX2X1TS U3964 ( .A(DMP_SFG[17]), .B(DMP_SHT2_EWSW[17]), .S0(n3202), .Y(n1556) );
MX2X1TS U3965 ( .A(DMP_SHT2_EWSW[16]), .B(DMP_SHT1_EWSW[16]), .S0(n3203),
.Y(n1560) );
INVX2TS U3966 ( .A(n4002), .Y(n3204) );
MX2X1TS U3967 ( .A(DMP_SFG[16]), .B(DMP_SHT2_EWSW[16]), .S0(n3204), .Y(n1559) );
MX2X1TS U3968 ( .A(DMP_SHT2_EWSW[15]), .B(DMP_SHT1_EWSW[15]), .S0(n3203),
.Y(n1563) );
MX2X1TS U3969 ( .A(DMP_SFG[15]), .B(DMP_SHT2_EWSW[15]), .S0(n3204), .Y(n1562) );
MX2X1TS U3970 ( .A(DMP_SHT2_EWSW[14]), .B(DMP_SHT1_EWSW[14]), .S0(n3203),
.Y(n1566) );
MX2X1TS U3971 ( .A(DMP_SFG[14]), .B(DMP_SHT2_EWSW[14]), .S0(n3204), .Y(n1565) );
MX2X1TS U3972 ( .A(DMP_SHT2_EWSW[13]), .B(DMP_SHT1_EWSW[13]), .S0(n3203),
.Y(n1569) );
MX2X1TS U3973 ( .A(DMP_SFG[13]), .B(DMP_SHT2_EWSW[13]), .S0(n3204), .Y(n1568) );
MX2X1TS U3974 ( .A(DMP_SHT2_EWSW[12]), .B(DMP_SHT1_EWSW[12]), .S0(n3203),
.Y(n1572) );
MX2X1TS U3975 ( .A(DMP_SFG[12]), .B(DMP_SHT2_EWSW[12]), .S0(n3204), .Y(n1571) );
MX2X1TS U3976 ( .A(DMP_SHT2_EWSW[11]), .B(DMP_SHT1_EWSW[11]), .S0(n3203),
.Y(n1575) );
MX2X1TS U3977 ( .A(DMP_SFG[11]), .B(DMP_SHT2_EWSW[11]), .S0(n3204), .Y(n1574) );
MX2X1TS U3978 ( .A(DMP_SHT2_EWSW[10]), .B(DMP_SHT1_EWSW[10]), .S0(n3203),
.Y(n1578) );
MX2X1TS U3979 ( .A(DMP_SFG[10]), .B(DMP_SHT2_EWSW[10]), .S0(n3204), .Y(n1577) );
MX2X1TS U3980 ( .A(DMP_SHT2_EWSW[9]), .B(DMP_SHT1_EWSW[9]), .S0(n3203), .Y(
n1581) );
MX2X1TS U3981 ( .A(DMP_SFG[9]), .B(DMP_SHT2_EWSW[9]), .S0(n3204), .Y(n1580)
);
MX2X1TS U3982 ( .A(DMP_SHT2_EWSW[8]), .B(DMP_SHT1_EWSW[8]), .S0(n3203), .Y(
n1584) );
MX2X1TS U3983 ( .A(DMP_SFG[8]), .B(DMP_SHT2_EWSW[8]), .S0(n3204), .Y(n1583)
);
MX2X1TS U3984 ( .A(DMP_SHT2_EWSW[7]), .B(DMP_SHT1_EWSW[7]), .S0(n3205), .Y(
n1587) );
MX2X1TS U3985 ( .A(DMP_SFG[7]), .B(DMP_SHT2_EWSW[7]), .S0(n3204), .Y(n1586)
);
MX2X1TS U3986 ( .A(DMP_SHT2_EWSW[6]), .B(DMP_SHT1_EWSW[6]), .S0(n3205), .Y(
n1590) );
MX2X1TS U3987 ( .A(DMP_SFG[6]), .B(DMP_SHT2_EWSW[6]), .S0(n3206), .Y(n1589)
);
MX2X1TS U3988 ( .A(DMP_SHT2_EWSW[5]), .B(DMP_SHT1_EWSW[5]), .S0(n3205), .Y(
n1593) );
MX2X1TS U3989 ( .A(DMP_SFG[5]), .B(DMP_SHT2_EWSW[5]), .S0(n3206), .Y(n1592)
);
MX2X1TS U3990 ( .A(DMP_SHT2_EWSW[4]), .B(DMP_SHT1_EWSW[4]), .S0(n3205), .Y(
n1596) );
MX2X1TS U3991 ( .A(DMP_SFG[4]), .B(DMP_SHT2_EWSW[4]), .S0(n3206), .Y(n1595)
);
MX2X1TS U3992 ( .A(DMP_SHT2_EWSW[3]), .B(DMP_SHT1_EWSW[3]), .S0(n3205), .Y(
n1599) );
MX2X1TS U3993 ( .A(DMP_SFG[3]), .B(DMP_SHT2_EWSW[3]), .S0(n3206), .Y(n1598)
);
MX2X1TS U3994 ( .A(DMP_SHT2_EWSW[2]), .B(DMP_SHT1_EWSW[2]), .S0(n3205), .Y(
n1602) );
MX2X1TS U3995 ( .A(DMP_SFG[2]), .B(DMP_SHT2_EWSW[2]), .S0(n3206), .Y(n1601)
);
MX2X1TS U3996 ( .A(DMP_SHT2_EWSW[1]), .B(DMP_SHT1_EWSW[1]), .S0(n3205), .Y(
n1605) );
MX2X1TS U3997 ( .A(DMP_SFG[1]), .B(DMP_SHT2_EWSW[1]), .S0(n3206), .Y(n1604)
);
MX2X1TS U3998 ( .A(DMP_SHT2_EWSW[0]), .B(DMP_SHT1_EWSW[0]), .S0(n3205), .Y(
n1608) );
MX2X1TS U3999 ( .A(DMP_SFG[0]), .B(DMP_SHT2_EWSW[0]), .S0(n3206), .Y(n1607)
);
MX2X1TS U4000 ( .A(OP_FLAG_SFG), .B(OP_FLAG_SHT2), .S0(n3206), .Y(n1278) );
CLKBUFX2TS U4001 ( .A(n3347), .Y(n3834) );
AOI21X1TS U4002 ( .A0(n3592), .A1(n3209), .B0(n3208), .Y(n3718) );
INVX2TS U4003 ( .A(n3718), .Y(n3679) );
AOI21X1TS U4004 ( .A0(n3679), .A1(n3213), .B0(n3212), .Y(n3218) );
NAND2X1TS U4005 ( .A(n3216), .B(n3215), .Y(n3222) );
INVX2TS U4006 ( .A(n3222), .Y(n3217) );
XOR2XLTS U4007 ( .A(n3218), .B(n3217), .Y(n3226) );
AOI21X1TS U4008 ( .A0(n3572), .A1(n3221), .B0(n3220), .Y(n3725) );
XNOR2X1TS U4009 ( .A(n3223), .B(n3222), .Y(n3224) );
AOI22X1TS U4010 ( .A0(n3224), .A1(n3830), .B0(Raw_mant_NRM_SWR[27]), .B1(
n3978), .Y(n3225) );
OAI2BB1X1TS U4011 ( .A0N(n3834), .A1N(n3226), .B0(n3225), .Y(n1242) );
CLKBUFX2TS U4012 ( .A(n3884), .Y(n3410) );
AOI22X1TS U4013 ( .A0(n3229), .A1(n3410), .B0(Raw_mant_NRM_SWR[31]), .B1(
n3978), .Y(n3230) );
OAI2BB1X1TS U4014 ( .A0N(n3347), .A1N(n3231), .B0(n3230), .Y(n1238) );
AOI21X1TS U4015 ( .A0(n3592), .A1(n3233), .B0(n3232), .Y(n3350) );
NAND2X1TS U4016 ( .A(n3236), .B(n3235), .Y(n3240) );
INVX2TS U4017 ( .A(n3240), .Y(n3237) );
XOR2XLTS U4018 ( .A(n3350), .B(n3237), .Y(n3244) );
CLKBUFX2TS U4019 ( .A(n3884), .Y(n3727) );
INVX2TS U4020 ( .A(n3238), .Y(n3568) );
INVX2TS U4021 ( .A(n3567), .Y(n3239) );
AOI21X1TS U4022 ( .A0(n3572), .A1(n3568), .B0(n3239), .Y(n3241) );
XOR2XLTS U4023 ( .A(n3241), .B(n3240), .Y(n3242) );
AOI22X1TS U4024 ( .A0(n3727), .A1(n3242), .B0(Raw_mant_NRM_SWR[19]), .B1(
n3978), .Y(n3243) );
OAI2BB1X1TS U4025 ( .A0N(n3347), .A1N(n3244), .B0(n3243), .Y(n1250) );
CLKBUFX2TS U4026 ( .A(n3347), .Y(n3346) );
INVX2TS U4027 ( .A(n3246), .Y(n3247) );
AOI21X1TS U4028 ( .A0(n3592), .A1(n3248), .B0(n3247), .Y(n3691) );
INVX2TS U4029 ( .A(n3691), .Y(n3767) );
AOI21X1TS U4030 ( .A0(n3767), .A1(n3250), .B0(n3249), .Y(n3364) );
NAND2X1TS U4031 ( .A(n3253), .B(n3670), .Y(n3262) );
INVX2TS U4032 ( .A(n3262), .Y(n3254) );
XNOR2X1TS U4033 ( .A(n3255), .B(n3254), .Y(n3265) );
AOI21X1TS U4034 ( .A0(n3572), .A1(n3259), .B0(n3258), .Y(n3365) );
INVX2TS U4035 ( .A(n3365), .Y(n3698) );
AOI21X1TS U4036 ( .A0(n3698), .A1(n3261), .B0(n3260), .Y(n3672) );
AOI22X1TS U4037 ( .A0(n3727), .A1(n3263), .B0(Raw_mant_NRM_SWR[24]), .B1(
n3978), .Y(n3264) );
OAI2BB1X1TS U4038 ( .A0N(n3346), .A1N(n3265), .B0(n3264), .Y(n1245) );
MXI2XLTS U4039 ( .A(n4174), .B(n4274), .S0(n1907), .Y(n1269) );
INVX2TS U4040 ( .A(n3266), .Y(n3281) );
OAI21XLTS U4041 ( .A0(n3281), .A1(n3268), .B0(n3267), .Y(n3271) );
INVX2TS U4042 ( .A(n3292), .Y(n3269) );
NAND2X1TS U4043 ( .A(n3269), .B(n3291), .Y(n3273) );
INVX2TS U4044 ( .A(n3273), .Y(n3270) );
XNOR2X1TS U4045 ( .A(n3271), .B(n3270), .Y(n3276) );
INVX2TS U4046 ( .A(n3272), .Y(n3293) );
XOR2XLTS U4047 ( .A(n3293), .B(n3273), .Y(n3274) );
AOI22X1TS U4048 ( .A0(n3727), .A1(n3274), .B0(Raw_mant_NRM_SWR[4]), .B1(
n3978), .Y(n3275) );
OAI2BB1X1TS U4049 ( .A0N(n3347), .A1N(n3276), .B0(n3275), .Y(n1265) );
INVX2TS U4050 ( .A(n3277), .Y(n3279) );
NAND2X1TS U4051 ( .A(n3279), .B(n3278), .Y(n3282) );
INVX2TS U4052 ( .A(n3282), .Y(n3280) );
XOR2XLTS U4053 ( .A(n3281), .B(n3280), .Y(n3285) );
XOR2XLTS U4054 ( .A(n3282), .B(n3311), .Y(n3283) );
AOI22X1TS U4055 ( .A0(n3727), .A1(n3283), .B0(Raw_mant_NRM_SWR[3]), .B1(
n3978), .Y(n3284) );
OAI2BB1X1TS U4056 ( .A0N(n3346), .A1N(n3285), .B0(n3284), .Y(n1266) );
INVX2TS U4057 ( .A(n3286), .Y(n3373) );
INVX2TS U4058 ( .A(n3287), .Y(n3289) );
NAND2X1TS U4059 ( .A(n3289), .B(n3288), .Y(n3294) );
INVX2TS U4060 ( .A(n3294), .Y(n3290) );
XNOR2X1TS U4061 ( .A(n3373), .B(n3290), .Y(n3298) );
OAI21XLTS U4062 ( .A0(n3293), .A1(n3292), .B0(n3291), .Y(n3295) );
XNOR2X1TS U4063 ( .A(n3295), .B(n3294), .Y(n3296) );
AOI22X1TS U4064 ( .A0(n3296), .A1(n3884), .B0(Raw_mant_NRM_SWR[5]), .B1(
n3978), .Y(n3297) );
OAI2BB1X1TS U4065 ( .A0N(n3346), .A1N(n3298), .B0(n3297), .Y(n1264) );
INVX2TS U4066 ( .A(n3299), .Y(n3302) );
INVX2TS U4067 ( .A(n3300), .Y(n3301) );
AOI21X1TS U4068 ( .A0(n3373), .A1(n3302), .B0(n3301), .Y(n3305) );
INVX2TS U4069 ( .A(n3303), .Y(n3380) );
NAND2X1TS U4070 ( .A(n3380), .B(n3378), .Y(n3307) );
INVX2TS U4071 ( .A(n3307), .Y(n3304) );
XOR2XLTS U4072 ( .A(n3305), .B(n3304), .Y(n3310) );
INVX2TS U4073 ( .A(n3306), .Y(n3394) );
XNOR2X1TS U4074 ( .A(n3394), .B(n3307), .Y(n3308) );
CLKBUFX2TS U4075 ( .A(n1914), .Y(n3396) );
AOI22X1TS U4076 ( .A0(n3308), .A1(n3884), .B0(Raw_mant_NRM_SWR[6]), .B1(
n3396), .Y(n3309) );
OAI2BB1X1TS U4077 ( .A0N(n3346), .A1N(n3310), .B0(n3309), .Y(n1263) );
OR2X1TS U4078 ( .A(DMP_SFG[0]), .B(DmP_mant_SFG_SWR[2]), .Y(n3312) );
CLKAND2X2TS U4079 ( .A(n3312), .B(n3311), .Y(n3314) );
XOR2XLTS U4080 ( .A(n3314), .B(n3313), .Y(n3316) );
AOI22X1TS U4081 ( .A0(n3314), .A1(n3410), .B0(Raw_mant_NRM_SWR[2]), .B1(
n3396), .Y(n3315) );
OAI2BB1X1TS U4082 ( .A0N(n3346), .A1N(n3316), .B0(n3315), .Y(n1267) );
XNOR2X1TS U4083 ( .A(DmP_mant_SFG_SWR[1]), .B(n4274), .Y(n3318) );
AOI22X1TS U4084 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n3410), .B0(n3829), .B1(
Raw_mant_NRM_SWR[1]), .Y(n3317) );
OAI2BB1X1TS U4085 ( .A0N(n3318), .A1N(n3347), .B0(n3317), .Y(n1268) );
AFHCINX2TS U4086 ( .CIN(n3320), .B(DMP_SFG[39]), .A(DmP_mant_SFG_SWR[41]),
.S(n3321), .CO(n3665) );
AOI22X1TS U4087 ( .A0(n3321), .A1(n3410), .B0(Raw_mant_NRM_SWR[41]), .B1(
n3396), .Y(n3322) );
OAI2BB1X1TS U4088 ( .A0N(n3346), .A1N(n3323), .B0(n3322), .Y(n1228) );
AFHCONX2TS U4089 ( .A(DMP_SFG[34]), .B(n4050), .CI(n3324), .CON(n3577), .S(
n3329) );
XNOR2X1TS U4090 ( .A(DmP_mant_SFG_SWR[36]), .B(DMP_SFG[34]), .Y(n3325) );
XNOR2X1TS U4091 ( .A(n3326), .B(n3325), .Y(n3327) );
AOI22X1TS U4092 ( .A0(n3327), .A1(n3410), .B0(Raw_mant_NRM_SWR[36]), .B1(
n3396), .Y(n3328) );
OAI2BB1X1TS U4093 ( .A0N(n3346), .A1N(n3329), .B0(n3328), .Y(n1233) );
AOI22X1TS U4094 ( .A0(n3332), .A1(n3410), .B0(Raw_mant_NRM_SWR[35]), .B1(
n3396), .Y(n3333) );
OAI2BB1X1TS U4095 ( .A0N(n3346), .A1N(n3334), .B0(n3333), .Y(n1234) );
AFHCONX2TS U4096 ( .A(DMP_SFG[30]), .B(n4048), .CI(n3335), .CON(n3341), .S(
n3340) );
AOI22X1TS U4097 ( .A0(n3338), .A1(n3410), .B0(Raw_mant_NRM_SWR[32]), .B1(
n3396), .Y(n3339) );
OAI2BB1X1TS U4098 ( .A0N(n3346), .A1N(n3340), .B0(n3339), .Y(n1237) );
CLKBUFX2TS U4099 ( .A(n1914), .Y(n3490) );
AOI22X1TS U4100 ( .A0(n3343), .A1(n3410), .B0(Raw_mant_NRM_SWR[33]), .B1(
n3490), .Y(n3344) );
OAI2BB1X1TS U4101 ( .A0N(n3346), .A1N(n3345), .B0(n3344), .Y(n1236) );
CLKBUFX2TS U4102 ( .A(n3347), .Y(n3475) );
OAI21XLTS U4103 ( .A0(n3350), .A1(n3349), .B0(n3348), .Y(n3353) );
NAND2X1TS U4104 ( .A(n3351), .B(n3768), .Y(n3356) );
INVX2TS U4105 ( .A(n3356), .Y(n3352) );
XNOR2X1TS U4106 ( .A(n3353), .B(n3352), .Y(n3359) );
AOI21X1TS U4107 ( .A0(n3572), .A1(n3355), .B0(n3354), .Y(n3770) );
XOR2XLTS U4108 ( .A(n3770), .B(n3356), .Y(n3357) );
AOI22X1TS U4109 ( .A0(n3727), .A1(n3357), .B0(Raw_mant_NRM_SWR[20]), .B1(
n3396), .Y(n3358) );
OAI2BB1X1TS U4110 ( .A0N(n3475), .A1N(n3359), .B0(n3358), .Y(n1249) );
NAND2X1TS U4111 ( .A(n3362), .B(n3361), .Y(n3366) );
INVX2TS U4112 ( .A(n3366), .Y(n3363) );
XOR2XLTS U4113 ( .A(n3364), .B(n3363), .Y(n3370) );
XNOR2X1TS U4114 ( .A(n3367), .B(n3366), .Y(n3368) );
AOI22X1TS U4115 ( .A0(n3368), .A1(n3410), .B0(Raw_mant_NRM_SWR[23]), .B1(
n3396), .Y(n3369) );
OAI2BB1X1TS U4116 ( .A0N(n3475), .A1N(n3370), .B0(n3369), .Y(n1246) );
AOI21X1TS U4117 ( .A0(n3373), .A1(n3372), .B0(n3371), .Y(n3388) );
INVX2TS U4118 ( .A(n3374), .Y(n3376) );
NAND2X1TS U4119 ( .A(n3376), .B(n3375), .Y(n3381) );
INVX2TS U4120 ( .A(n3381), .Y(n3377) );
XOR2XLTS U4121 ( .A(n3388), .B(n3377), .Y(n3385) );
INVX2TS U4122 ( .A(n3378), .Y(n3379) );
AOI21X1TS U4123 ( .A0(n3394), .A1(n3380), .B0(n3379), .Y(n3382) );
XOR2XLTS U4124 ( .A(n3382), .B(n3381), .Y(n3383) );
AOI22X1TS U4125 ( .A0(n3727), .A1(n3383), .B0(Raw_mant_NRM_SWR[7]), .B1(
n3396), .Y(n3384) );
OAI2BB1X1TS U4126 ( .A0N(n3475), .A1N(n3385), .B0(n3384), .Y(n1262) );
OAI21XLTS U4127 ( .A0(n3388), .A1(n3387), .B0(n3386), .Y(n3391) );
INVX2TS U4128 ( .A(n3406), .Y(n3389) );
NAND2X1TS U4129 ( .A(n3389), .B(n3405), .Y(n3395) );
INVX2TS U4130 ( .A(n3395), .Y(n3390) );
XNOR2X1TS U4131 ( .A(n3391), .B(n3390), .Y(n3399) );
AOI21X1TS U4132 ( .A0(n3394), .A1(n3393), .B0(n3392), .Y(n3407) );
XOR2XLTS U4133 ( .A(n3407), .B(n3395), .Y(n3397) );
AOI22X1TS U4134 ( .A0(n3830), .A1(n3397), .B0(Raw_mant_NRM_SWR[8]), .B1(
n3396), .Y(n3398) );
OAI2BB1X1TS U4135 ( .A0N(n3475), .A1N(n3399), .B0(n3398), .Y(n1261) );
INVX2TS U4136 ( .A(n3401), .Y(n3403) );
NAND2X1TS U4137 ( .A(n3403), .B(n3402), .Y(n3408) );
INVX2TS U4138 ( .A(n3408), .Y(n3404) );
XOR2XLTS U4139 ( .A(n3605), .B(n3404), .Y(n3413) );
OAI21XLTS U4140 ( .A0(n3407), .A1(n3406), .B0(n3405), .Y(n3409) );
XNOR2X1TS U4141 ( .A(n3409), .B(n3408), .Y(n3411) );
AOI22X1TS U4142 ( .A0(n3411), .A1(n3410), .B0(Raw_mant_NRM_SWR[9]), .B1(
n3490), .Y(n3412) );
OAI2BB1X1TS U4143 ( .A0N(n3475), .A1N(n3413), .B0(n3412), .Y(n1260) );
INVX2TS U4144 ( .A(n3706), .Y(n3653) );
INVX2TS U4145 ( .A(n3416), .Y(n3419) );
INVX2TS U4146 ( .A(n3417), .Y(n3418) );
NAND2X1TS U4147 ( .A(n3422), .B(n3421), .Y(n3429) );
INVX2TS U4148 ( .A(n3429), .Y(n3423) );
XNOR2X1TS U4149 ( .A(n3548), .B(n3423), .Y(n3433) );
OAI21XLTS U4150 ( .A0(n3612), .A1(n3426), .B0(n3425), .Y(n3552) );
INVX2TS U4151 ( .A(n3427), .Y(n3708) );
INVX2TS U4152 ( .A(n3707), .Y(n3428) );
AOI21X1TS U4153 ( .A0(n3552), .A1(n3708), .B0(n3428), .Y(n3430) );
AOI22X1TS U4154 ( .A0(n3830), .A1(n3431), .B0(Raw_mant_NRM_SWR[15]), .B1(
n3490), .Y(n3432) );
OAI2BB1X1TS U4155 ( .A0N(n3475), .A1N(n3433), .B0(n3432), .Y(n1254) );
INVX2TS U4156 ( .A(n3434), .Y(n3437) );
INVX2TS U4157 ( .A(n3435), .Y(n3436) );
INVX2TS U4158 ( .A(n3438), .Y(n3440) );
NAND2X1TS U4159 ( .A(n3440), .B(n3439), .Y(n3442) );
INVX2TS U4160 ( .A(n3442), .Y(n3441) );
XNOR2X1TS U4161 ( .A(n3451), .B(n3441), .Y(n3446) );
XNOR2X1TS U4162 ( .A(n3443), .B(n3442), .Y(n3444) );
CLKBUFX2TS U4163 ( .A(n3884), .Y(n3599) );
AOI22X1TS U4164 ( .A0(n3444), .A1(n3599), .B0(Raw_mant_NRM_SWR[11]), .B1(
n3490), .Y(n3445) );
OAI2BB1X1TS U4165 ( .A0N(n3475), .A1N(n3446), .B0(n3445), .Y(n1258) );
INVX2TS U4166 ( .A(n3447), .Y(n3450) );
INVX2TS U4167 ( .A(n3448), .Y(n3449) );
AOI21X1TS U4168 ( .A0(n3451), .A1(n3450), .B0(n3449), .Y(n3454) );
INVX2TS U4169 ( .A(n3452), .Y(n3656) );
NAND2X1TS U4170 ( .A(n3656), .B(n3654), .Y(n3459) );
INVX2TS U4171 ( .A(n3459), .Y(n3453) );
XOR2XLTS U4172 ( .A(n3454), .B(n3453), .Y(n3462) );
XNOR2X1TS U4173 ( .A(n3657), .B(n3459), .Y(n3460) );
AOI22X1TS U4174 ( .A0(n3460), .A1(n3599), .B0(Raw_mant_NRM_SWR[12]), .B1(
n3490), .Y(n3461) );
OAI2BB1X1TS U4175 ( .A0N(n3475), .A1N(n3462), .B0(n3461), .Y(n1257) );
AFHCINX2TS U4176 ( .CIN(n3464), .B(DMP_SFG[41]), .A(DmP_mant_SFG_SWR[43]),
.S(n3465), .CO(n3471) );
AOI22X1TS U4177 ( .A0(n3465), .A1(n3599), .B0(Raw_mant_NRM_SWR[43]), .B1(
n3490), .Y(n3466) );
OAI2BB1X1TS U4178 ( .A0N(n3475), .A1N(n3467), .B0(n3466), .Y(n1226) );
AOI22X1TS U4179 ( .A0(n3472), .A1(n3599), .B0(Raw_mant_NRM_SWR[44]), .B1(
n3490), .Y(n3473) );
OAI2BB1X1TS U4180 ( .A0N(n3475), .A1N(n3474), .B0(n3473), .Y(n1225) );
AFHCINX2TS U4181 ( .CIN(n3476), .B(n4268), .A(DMP_SFG[43]), .S(n3480), .CO(
n3481) );
AOI22X1TS U4182 ( .A0(n3478), .A1(n3599), .B0(Raw_mant_NRM_SWR[45]), .B1(
n3490), .Y(n3479) );
OAI2BB1X1TS U4183 ( .A0N(n3526), .A1N(n3480), .B0(n3479), .Y(n1224) );
AFHCONX2TS U4184 ( .A(DMP_SFG[44]), .B(n4051), .CI(n3481), .CON(n3487), .S(
n3486) );
XNOR2X1TS U4185 ( .A(DmP_mant_SFG_SWR[46]), .B(DMP_SFG[44]), .Y(n3482) );
AOI22X1TS U4186 ( .A0(n3484), .A1(n3599), .B0(Raw_mant_NRM_SWR[46]), .B1(
n3490), .Y(n3485) );
OAI2BB1X1TS U4187 ( .A0N(n3526), .A1N(n3486), .B0(n3485), .Y(n1223) );
XNOR2X1TS U4188 ( .A(DmP_mant_SFG_SWR[47]), .B(DMP_SFG[45]), .Y(n3488) );
AOI22X1TS U4189 ( .A0(n3491), .A1(n3599), .B0(Raw_mant_NRM_SWR[47]), .B1(
n3490), .Y(n3492) );
OAI2BB1X1TS U4190 ( .A0N(n3526), .A1N(n3493), .B0(n3492), .Y(n1222) );
AFHCINX2TS U4191 ( .CIN(n3495), .B(DMP_SFG[37]), .A(DmP_mant_SFG_SWR[39]),
.S(n3496), .CO(n3500) );
AOI22X1TS U4192 ( .A0(n3496), .A1(n3599), .B0(Raw_mant_NRM_SWR[39]), .B1(
n1915), .Y(n3497) );
OAI2BB1X1TS U4193 ( .A0N(n3526), .A1N(n3498), .B0(n3497), .Y(n1230) );
AFHCONX2TS U4194 ( .A(DMP_SFG[38]), .B(n4119), .CI(n3499), .CON(n3319), .S(
n3503) );
AFHCONX2TS U4195 ( .A(DmP_mant_SFG_SWR[40]), .B(DMP_SFG[38]), .CI(n3500),
.CON(n3320), .S(n3501) );
AOI22X1TS U4196 ( .A0(n3501), .A1(n3599), .B0(Raw_mant_NRM_SWR[40]), .B1(
n1915), .Y(n3502) );
OAI2BB1X1TS U4197 ( .A0N(n3526), .A1N(n3503), .B0(n3502), .Y(n1229) );
XOR2XLTS U4198 ( .A(n4266), .B(DMP_SFG[26]), .Y(n3504) );
AFHCONX2TS U4199 ( .A(DmP_mant_SFG_SWR[28]), .B(DMP_SFG[26]), .CI(n3506),
.CON(n3511), .S(n3507) );
AOI22X1TS U4200 ( .A0(n3507), .A1(n3573), .B0(Raw_mant_NRM_SWR[28]), .B1(
n1915), .Y(n3508) );
OAI2BB1X1TS U4201 ( .A0N(n3526), .A1N(n3509), .B0(n3508), .Y(n1241) );
AFHCINX2TS U4202 ( .CIN(n3510), .B(n4272), .A(DMP_SFG[27]), .S(n3514), .CO(
n3683) );
AFHCINX2TS U4203 ( .CIN(n3511), .B(DMP_SFG[27]), .A(DmP_mant_SFG_SWR[29]),
.S(n3512), .CO(n3684) );
AOI22X1TS U4204 ( .A0(n3512), .A1(n3573), .B0(Raw_mant_NRM_SWR[29]), .B1(
n1915), .Y(n3513) );
OAI2BB1X1TS U4205 ( .A0N(n3526), .A1N(n3514), .B0(n3513), .Y(n1240) );
XNOR2X1TS U4206 ( .A(n4263), .B(DMP_SFG[50]), .Y(n3515) );
XNOR2X1TS U4207 ( .A(n3516), .B(n3515), .Y(n3520) );
ADDFHX2TS U4208 ( .A(DMP_SFG[50]), .B(DmP_mant_SFG_SWR[52]), .CI(n3517),
.CO(n2408), .S(n3518) );
AOI22X1TS U4209 ( .A0(n3518), .A1(n3573), .B0(Raw_mant_NRM_SWR[52]), .B1(
n1915), .Y(n3519) );
OAI2BB1X1TS U4210 ( .A0N(n3526), .A1N(n3520), .B0(n3519), .Y(n1217) );
AFHCINX2TS U4211 ( .CIN(n3521), .B(n4208), .A(DMP_SFG[49]), .S(n3525), .CO(
n3516) );
AFHCINX2TS U4212 ( .CIN(n3522), .B(DMP_SFG[49]), .A(DmP_mant_SFG_SWR[51]),
.S(n3523), .CO(n3517) );
AOI22X1TS U4213 ( .A0(n3523), .A1(n3573), .B0(Raw_mant_NRM_SWR[51]), .B1(
n1915), .Y(n3524) );
OAI2BB1X1TS U4214 ( .A0N(n3526), .A1N(n3525), .B0(n3524), .Y(n1218) );
AFHCINX2TS U4215 ( .CIN(n3528), .B(DMP_SFG[47]), .A(DmP_mant_SFG_SWR[49]),
.S(n3529), .CO(n3534) );
AOI22X1TS U4216 ( .A0(n3529), .A1(n3573), .B0(Raw_mant_NRM_SWR[49]), .B1(
n1915), .Y(n3530) );
OAI2BB1X1TS U4217 ( .A0N(n3669), .A1N(n3531), .B0(n3530), .Y(n1220) );
XNOR2X1TS U4218 ( .A(n4159), .B(DMP_SFG[48]), .Y(n3532) );
AFHCONX2TS U4219 ( .A(DmP_mant_SFG_SWR[50]), .B(DMP_SFG[48]), .CI(n3534),
.CON(n3522), .S(n3535) );
AOI22X1TS U4220 ( .A0(n3535), .A1(n3573), .B0(Raw_mant_NRM_SWR[50]), .B1(
n1915), .Y(n3536) );
OAI2BB1X1TS U4221 ( .A0N(n3669), .A1N(n3537), .B0(n3536), .Y(n1219) );
AFHCONX2TS U4222 ( .A(DMP_SFG[46]), .B(n4052), .CI(n3538), .CON(n3527), .S(
n3543) );
XNOR2X1TS U4223 ( .A(DmP_mant_SFG_SWR[48]), .B(DMP_SFG[46]), .Y(n3539) );
AOI22X1TS U4224 ( .A0(n3541), .A1(n3573), .B0(Raw_mant_NRM_SWR[48]), .B1(
n1915), .Y(n3542) );
OAI2BB1X1TS U4225 ( .A0N(n3669), .A1N(n3543), .B0(n3542), .Y(n1221) );
INVX2TS U4226 ( .A(n3544), .Y(n3547) );
INVX2TS U4227 ( .A(n3545), .Y(n3546) );
AOI21X1TS U4228 ( .A0(n3548), .A1(n3547), .B0(n3546), .Y(n3551) );
INVX2TS U4229 ( .A(n3549), .Y(n3584) );
NAND2X1TS U4230 ( .A(n3584), .B(n3582), .Y(n3557) );
INVX2TS U4231 ( .A(n3557), .Y(n3550) );
XOR2XLTS U4232 ( .A(n3551), .B(n3550), .Y(n3560) );
INVX2TS U4233 ( .A(n3552), .Y(n3712) );
INVX2TS U4234 ( .A(n3554), .Y(n3555) );
XNOR2X1TS U4235 ( .A(n3585), .B(n3557), .Y(n3558) );
AOI22X1TS U4236 ( .A0(n3558), .A1(n3573), .B0(Raw_mant_NRM_SWR[16]), .B1(
n1915), .Y(n3559) );
OAI2BB1X1TS U4237 ( .A0N(n3669), .A1N(n3560), .B0(n3559), .Y(n1253) );
NAND2X1TS U4238 ( .A(DmP_EXP_EWSW[53]), .B(n4213), .Y(n3946) );
OAI21XLTS U4239 ( .A0(DmP_EXP_EWSW[53]), .A1(n4213), .B0(n3946), .Y(n3561)
);
XNOR2X1TS U4240 ( .A(n3947), .B(n3561), .Y(n3562) );
CLKBUFX2TS U4241 ( .A(Shift_reg_FLAGS_7_5), .Y(n4003) );
MX2X1TS U4242 ( .A(Shift_amount_SHT1_EWR[1]), .B(n3562), .S0(n4003), .Y(
n1691) );
CLKBUFX2TS U4243 ( .A(Shift_reg_FLAGS_7_5), .Y(n3974) );
CLKBUFX2TS U4244 ( .A(n3974), .Y(n3995) );
MX2X1TS U4245 ( .A(DmP_mant_SHT1_SW[51]), .B(DmP_EXP_EWSW[51]), .S0(n3995),
.Y(n1295) );
CLKBUFX2TS U4246 ( .A(n4003), .Y(n3992) );
MX2X1TS U4247 ( .A(DmP_mant_SHT1_SW[50]), .B(DmP_EXP_EWSW[50]), .S0(n3992),
.Y(n1297) );
INVX2TS U4248 ( .A(n3563), .Y(n3566) );
INVX2TS U4249 ( .A(n3564), .Y(n3565) );
AOI21X1TS U4250 ( .A0(n3592), .A1(n3566), .B0(n3565), .Y(n3570) );
NAND2X1TS U4251 ( .A(n3568), .B(n3567), .Y(n3571) );
INVX2TS U4252 ( .A(n3571), .Y(n3569) );
XOR2XLTS U4253 ( .A(n3570), .B(n3569), .Y(n3576) );
XNOR2X1TS U4254 ( .A(n3572), .B(n3571), .Y(n3574) );
AOI22X1TS U4255 ( .A0(n3574), .A1(n3573), .B0(Raw_mant_NRM_SWR[18]), .B1(
n3685), .Y(n3575) );
OAI2BB1X1TS U4256 ( .A0N(n3669), .A1N(n3576), .B0(n3575), .Y(n1251) );
AOI22X1TS U4257 ( .A0(n3579), .A1(n3830), .B0(Raw_mant_NRM_SWR[37]), .B1(
n3685), .Y(n3580) );
OAI2BB1X1TS U4258 ( .A0N(n3669), .A1N(n3581), .B0(n3580), .Y(n1232) );
INVX2TS U4259 ( .A(n3582), .Y(n3583) );
AOI21X1TS U4260 ( .A0(n3585), .A1(n3584), .B0(n3583), .Y(n3589) );
NAND2X1TS U4261 ( .A(n3588), .B(n3587), .Y(n3590) );
XOR2XLTS U4262 ( .A(n3589), .B(n3590), .Y(n3595) );
INVX2TS U4263 ( .A(n3590), .Y(n3591) );
XNOR2X1TS U4264 ( .A(n3592), .B(n3591), .Y(n3593) );
AOI22X1TS U4265 ( .A0(n3593), .A1(n3834), .B0(Raw_mant_NRM_SWR[17]), .B1(
n3685), .Y(n3594) );
OAI2BB1X1TS U4266 ( .A0N(n3884), .A1N(n3595), .B0(n3594), .Y(n1252) );
AFHCONX2TS U4267 ( .A(DMP_SFG[36]), .B(n4120), .CI(n3596), .CON(n3494), .S(
n3602) );
AOI22X1TS U4268 ( .A0(n3600), .A1(n3599), .B0(Raw_mant_NRM_SWR[38]), .B1(
n3685), .Y(n3601) );
OAI2BB1X1TS U4269 ( .A0N(n3669), .A1N(n3602), .B0(n3601), .Y(n1231) );
OAI21XLTS U4270 ( .A0(n3605), .A1(n3604), .B0(n3603), .Y(n3610) );
INVX2TS U4271 ( .A(n3606), .Y(n3608) );
NAND2X1TS U4272 ( .A(n3608), .B(n3607), .Y(n3611) );
INVX2TS U4273 ( .A(n3611), .Y(n3609) );
XNOR2X1TS U4274 ( .A(n3610), .B(n3609), .Y(n3615) );
XOR2XLTS U4275 ( .A(n3612), .B(n3611), .Y(n3613) );
AOI22X1TS U4276 ( .A0(n3727), .A1(n3613), .B0(Raw_mant_NRM_SWR[10]), .B1(
n3685), .Y(n3614) );
OAI2BB1X1TS U4277 ( .A0N(n3669), .A1N(n3615), .B0(n3614), .Y(n1259) );
AOI22X1TS U4278 ( .A0(Data_array_SWR[44]), .A1(n3634), .B0(
Data_array_SWR[36]), .B1(n3624), .Y(n3617) );
AOI22X1TS U4279 ( .A0(Data_array_SWR[48]), .A1(n3645), .B0(
Data_array_SWR[40]), .B1(n3644), .Y(n3616) );
NAND2X1TS U4280 ( .A(n3617), .B(n3616), .Y(n3815) );
AOI22X1TS U4281 ( .A0(Data_array_SWR[12]), .A1(n3748), .B0(Data_array_SWR[4]), .B1(n1912), .Y(n3619) );
AOI22X1TS U4282 ( .A0(Data_array_SWR[16]), .A1(n2187), .B0(Data_array_SWR[8]), .B1(n1924), .Y(n3618) );
AOI21X1TS U4283 ( .A0(n3797), .A1(n3815), .B0(n3620), .Y(n3874) );
NOR2X1TS U4284 ( .A(n1911), .B(n1903), .Y(n3805) );
AOI22X1TS U4285 ( .A0(Data_array_SWR[28]), .A1(n3634), .B0(
Data_array_SWR[20]), .B1(n3624), .Y(n3622) );
AOI22X1TS U4286 ( .A0(Data_array_SWR[32]), .A1(n1930), .B0(
Data_array_SWR[24]), .B1(n3635), .Y(n3621) );
NAND2X1TS U4287 ( .A(n3622), .B(n3621), .Y(n3869) );
AOI22X1TS U4288 ( .A0(n1923), .A1(n3871), .B0(n3805), .B1(n3869), .Y(n3623)
);
NAND2X1TS U4289 ( .A(n3847), .B(n1911), .Y(n3755) );
OAI211XLTS U4290 ( .A0(n3874), .A1(n4126), .B0(n3623), .C0(n3755), .Y(n4046)
);
AOI22X1TS U4291 ( .A0(Data_array_SWR[45]), .A1(n3634), .B0(
Data_array_SWR[37]), .B1(n3624), .Y(n3626) );
AOI22X1TS U4292 ( .A0(Data_array_SWR[49]), .A1(n1930), .B0(
Data_array_SWR[41]), .B1(n3644), .Y(n3625) );
NAND2X1TS U4293 ( .A(n3626), .B(n3625), .Y(n3823) );
AOI22X1TS U4294 ( .A0(Data_array_SWR[13]), .A1(n3748), .B0(Data_array_SWR[5]), .B1(n1912), .Y(n3628) );
AOI22X1TS U4295 ( .A0(Data_array_SWR[17]), .A1(n2187), .B0(Data_array_SWR[9]), .B1(n1924), .Y(n3627) );
AOI21X1TS U4296 ( .A0(n3797), .A1(n3823), .B0(n3629), .Y(n3868) );
AOI22X1TS U4297 ( .A0(Data_array_SWR[29]), .A1(n3634), .B0(
Data_array_SWR[21]), .B1(n3633), .Y(n3631) );
AOI22X1TS U4298 ( .A0(Data_array_SWR[33]), .A1(n1931), .B0(
Data_array_SWR[25]), .B1(n3635), .Y(n3630) );
NAND2X1TS U4299 ( .A(n3631), .B(n3630), .Y(n3865) );
AOI22X1TS U4300 ( .A0(n1923), .A1(n3866), .B0(n3805), .B1(n3865), .Y(n3632)
);
OAI211XLTS U4301 ( .A0(n3868), .A1(n4126), .B0(n3632), .C0(n3755), .Y(n4043)
);
CLKBUFX2TS U4302 ( .A(n3977), .Y(n3785) );
AOI22X1TS U4303 ( .A0(Data_array_SWR[46]), .A1(n3634), .B0(
Data_array_SWR[38]), .B1(n3633), .Y(n3637) );
AOI22X1TS U4304 ( .A0(Data_array_SWR[42]), .A1(n3635), .B0(
Data_array_SWR[50]), .B1(n1930), .Y(n3636) );
NAND2X1TS U4305 ( .A(n3637), .B(n3636), .Y(n3844) );
AOI22X1TS U4306 ( .A0(Data_array_SWR[14]), .A1(n3748), .B0(Data_array_SWR[6]), .B1(n1912), .Y(n3639) );
AOI22X1TS U4307 ( .A0(Data_array_SWR[18]), .A1(n2187), .B0(
Data_array_SWR[10]), .B1(n1924), .Y(n3638) );
AOI21X1TS U4308 ( .A0(n3797), .A1(n3844), .B0(n3641), .Y(n3864) );
AOI22X1TS U4309 ( .A0(Data_array_SWR[30]), .A1(n3643), .B0(
Data_array_SWR[22]), .B1(n3642), .Y(n3647) );
AOI22X1TS U4310 ( .A0(Data_array_SWR[34]), .A1(n3645), .B0(
Data_array_SWR[26]), .B1(n3644), .Y(n3646) );
NAND2X1TS U4311 ( .A(n3647), .B(n3646), .Y(n3861) );
AOI22X1TS U4312 ( .A0(n1923), .A1(n3862), .B0(n3805), .B1(n3861), .Y(n3648)
);
OAI211XLTS U4313 ( .A0(n3864), .A1(n4126), .B0(n3648), .C0(n3755), .Y(n4040)
);
INVX2TS U4314 ( .A(n3649), .Y(n3651) );
NAND2X1TS U4315 ( .A(n3651), .B(n3650), .Y(n3658) );
INVX2TS U4316 ( .A(n3658), .Y(n3652) );
XOR2XLTS U4317 ( .A(n3653), .B(n3652), .Y(n3662) );
INVX2TS U4318 ( .A(n3654), .Y(n3655) );
AOI21X1TS U4319 ( .A0(n3657), .A1(n3656), .B0(n3655), .Y(n3659) );
XOR2XLTS U4320 ( .A(n3659), .B(n3658), .Y(n3660) );
AOI22X1TS U4321 ( .A0(n3727), .A1(n3660), .B0(Raw_mant_NRM_SWR[13]), .B1(
n3685), .Y(n3661) );
OAI2BB1X1TS U4322 ( .A0N(n3834), .A1N(n3662), .B0(n3661), .Y(n1256) );
AFHCONX2TS U4323 ( .A(DMP_SFG[40]), .B(n4127), .CI(n3663), .CON(n3463), .S(
n3668) );
AOI22X1TS U4324 ( .A0(n3666), .A1(n3830), .B0(Raw_mant_NRM_SWR[42]), .B1(
n3685), .Y(n3667) );
OAI2BB1X1TS U4325 ( .A0N(n3669), .A1N(n3668), .B0(n3667), .Y(n1227) );
MX2X1TS U4326 ( .A(DmP_mant_SHT1_SW[23]), .B(DmP_EXP_EWSW[23]), .S0(n3974),
.Y(n1351) );
NAND2X1TS U4327 ( .A(n3675), .B(n3674), .Y(n3677) );
XNOR2X1TS U4328 ( .A(n3676), .B(n3677), .Y(n3682) );
INVX2TS U4329 ( .A(n3677), .Y(n3678) );
XNOR2X1TS U4330 ( .A(n3679), .B(n3678), .Y(n3680) );
AOI22X1TS U4331 ( .A0(n3680), .A1(n3834), .B0(Raw_mant_NRM_SWR[25]), .B1(
n3685), .Y(n3681) );
OAI2BB1X1TS U4332 ( .A0N(n3884), .A1N(n3682), .B0(n3681), .Y(n1244) );
MX2X1TS U4333 ( .A(DmP_mant_SHT1_SW[22]), .B(DmP_EXP_EWSW[22]), .S0(n3974),
.Y(n1353) );
AFHCONX2TS U4334 ( .A(DMP_SFG[28]), .B(n4265), .CI(n3683), .CON(n3227), .S(
n3688) );
AFHCONX2TS U4335 ( .A(DmP_mant_SFG_SWR[30]), .B(DMP_SFG[28]), .CI(n3684),
.CON(n3228), .S(n3686) );
AOI22X1TS U4336 ( .A0(n3686), .A1(n3830), .B0(Raw_mant_NRM_SWR[30]), .B1(
n3685), .Y(n3687) );
OAI2BB1X1TS U4337 ( .A0N(n3834), .A1N(n3688), .B0(n3687), .Y(n1239) );
OAI21XLTS U4338 ( .A0(n3691), .A1(n3690), .B0(n3689), .Y(n3696) );
NAND2X1TS U4339 ( .A(n3694), .B(n3693), .Y(n3697) );
INVX2TS U4340 ( .A(n3697), .Y(n3695) );
XNOR2X1TS U4341 ( .A(n3696), .B(n3695), .Y(n3701) );
XNOR2X1TS U4342 ( .A(n3698), .B(n3697), .Y(n3699) );
AOI22X1TS U4343 ( .A0(n3699), .A1(n3830), .B0(Raw_mant_NRM_SWR[22]), .B1(
n3829), .Y(n3700) );
OAI2BB1X1TS U4344 ( .A0N(n3834), .A1N(n3701), .B0(n3700), .Y(n1247) );
INVX2TS U4345 ( .A(n3702), .Y(n3705) );
INVX2TS U4346 ( .A(n3703), .Y(n3704) );
AOI21X1TS U4347 ( .A0(n3706), .A1(n3705), .B0(n3704), .Y(n3710) );
NAND2X1TS U4348 ( .A(n3708), .B(n3707), .Y(n3711) );
INVX2TS U4349 ( .A(n3711), .Y(n3709) );
XOR2XLTS U4350 ( .A(n3710), .B(n3709), .Y(n3715) );
XOR2XLTS U4351 ( .A(n3712), .B(n3711), .Y(n3713) );
AOI22X1TS U4352 ( .A0(n3727), .A1(n3713), .B0(Raw_mant_NRM_SWR[14]), .B1(
n3829), .Y(n3714) );
OAI2BB1X1TS U4353 ( .A0N(n3834), .A1N(n3715), .B0(n3714), .Y(n1255) );
MX2X1TS U4354 ( .A(DmP_mant_SHT1_SW[24]), .B(DmP_EXP_EWSW[24]), .S0(n3988),
.Y(n1349) );
NAND2X1TS U4355 ( .A(n3721), .B(n3720), .Y(n3724) );
INVX2TS U4356 ( .A(n3724), .Y(n3722) );
XNOR2X1TS U4357 ( .A(n3723), .B(n3722), .Y(n3729) );
AOI22X1TS U4358 ( .A0(n3727), .A1(n3726), .B0(Raw_mant_NRM_SWR[26]), .B1(
n3829), .Y(n3728) );
OAI2BB1X1TS U4359 ( .A0N(n3834), .A1N(n3729), .B0(n3728), .Y(n1243) );
AOI22X1TS U4360 ( .A0(Data_array_SWR[12]), .A1(n1912), .B0(
Data_array_SWR[24]), .B1(n2187), .Y(n3734) );
AOI22X1TS U4361 ( .A0(Data_array_SWR[20]), .A1(n3748), .B0(
Data_array_SWR[16]), .B1(n1924), .Y(n3733) );
AOI22X1TS U4362 ( .A0(n1902), .A1(n3731), .B0(n3797), .B1(n3730), .Y(n3732)
);
AOI22X1TS U4363 ( .A0(left_right_SHT2), .A1(n3858), .B0(n1923), .B1(n3859),
.Y(n3735) );
NAND2X1TS U4364 ( .A(n3735), .B(n3755), .Y(n4037) );
MX2X1TS U4365 ( .A(n4037), .B(DmP_mant_SFG_SWR[42]), .S0(n3785), .Y(n1114)
);
AOI22X1TS U4366 ( .A0(Data_array_SWR[13]), .A1(n1913), .B0(
Data_array_SWR[25]), .B1(n2187), .Y(n3740) );
AOI22X1TS U4367 ( .A0(Data_array_SWR[21]), .A1(n3748), .B0(
Data_array_SWR[17]), .B1(n1925), .Y(n3739) );
AOI22X1TS U4368 ( .A0(n1902), .A1(n3737), .B0(n3797), .B1(n3736), .Y(n3738)
);
AOI22X1TS U4369 ( .A0(left_right_SHT2), .A1(n3855), .B0(n1923), .B1(n3856),
.Y(n3741) );
NAND2X1TS U4370 ( .A(n3741), .B(n3755), .Y(n4034) );
MX2X1TS U4371 ( .A(n4034), .B(DmP_mant_SFG_SWR[41]), .S0(n3785), .Y(n1115)
);
AOI22X1TS U4372 ( .A0(Data_array_SWR[14]), .A1(n1912), .B0(
Data_array_SWR[26]), .B1(n2187), .Y(n3746) );
AOI22X1TS U4373 ( .A0(Data_array_SWR[18]), .A1(n1925), .B0(
Data_array_SWR[22]), .B1(n3748), .Y(n3745) );
AOI22X1TS U4374 ( .A0(n1902), .A1(n3743), .B0(n3797), .B1(n3742), .Y(n3744)
);
AOI22X1TS U4375 ( .A0(left_right_SHT2), .A1(n3851), .B0(n3808), .B1(n3852),
.Y(n3747) );
NAND2X1TS U4376 ( .A(n3747), .B(n3755), .Y(n4032) );
CLKBUFX2TS U4377 ( .A(n3977), .Y(n3854) );
MX2X1TS U4378 ( .A(n4032), .B(DmP_mant_SFG_SWR[40]), .S0(n3854), .Y(n1116)
);
AOI22X1TS U4379 ( .A0(Data_array_SWR[15]), .A1(n1912), .B0(
Data_array_SWR[27]), .B1(n2187), .Y(n3754) );
AOI22X1TS U4380 ( .A0(Data_array_SWR[19]), .A1(n1924), .B0(
Data_array_SWR[23]), .B1(n3748), .Y(n3753) );
AOI22X1TS U4381 ( .A0(n1902), .A1(n3750), .B0(n3797), .B1(n3749), .Y(n3752)
);
AOI22X1TS U4382 ( .A0(left_right_SHT2), .A1(n3848), .B0(n1923), .B1(n3849),
.Y(n3756) );
NAND2X1TS U4383 ( .A(n3756), .B(n3755), .Y(n4030) );
MX2X1TS U4384 ( .A(n4030), .B(DmP_mant_SFG_SWR[39]), .S0(n3785), .Y(n1117)
);
NOR2X1TS U4385 ( .A(left_right_SHT2), .B(n1903), .Y(n3870) );
INVX2TS U4386 ( .A(n3870), .Y(n3838) );
OAI21XLTS U4387 ( .A0(shift_value_SHT2_EWR[4]), .A1(n1911), .B0(n3798), .Y(
n3787) );
NAND2X1TS U4388 ( .A(n1910), .B(n3797), .Y(n3788) );
INVX2TS U4389 ( .A(n3805), .Y(n3836) );
OAI22X1TS U4390 ( .A0(n3841), .A1(n3788), .B0(n3839), .B1(n3836), .Y(n3757)
);
MX2X1TS U4391 ( .A(n4027), .B(DmP_mant_SFG_SWR[38]), .S0(n3785), .Y(n1118)
);
OAI22X1TS U4392 ( .A0(n3820), .A1(n3788), .B0(n3819), .B1(n3836), .Y(n3760)
);
MX2X1TS U4393 ( .A(n4024), .B(DmP_mant_SFG_SWR[37]), .S0(n3785), .Y(n1119)
);
NAND2X1TS U4394 ( .A(n3765), .B(n3764), .Y(n3771) );
INVX2TS U4395 ( .A(n3771), .Y(n3766) );
XNOR2X1TS U4396 ( .A(n3767), .B(n3766), .Y(n3775) );
XNOR2X1TS U4397 ( .A(n3772), .B(n3771), .Y(n3773) );
AOI22X1TS U4398 ( .A0(n3773), .A1(n3830), .B0(Raw_mant_NRM_SWR[21]), .B1(
n3829), .Y(n3774) );
OAI2BB1X1TS U4399 ( .A0N(n3834), .A1N(n3775), .B0(n3774), .Y(n1248) );
OAI22X1TS U4400 ( .A0(n3812), .A1(n3788), .B0(n3811), .B1(n3836), .Y(n3776)
);
MX2X1TS U4401 ( .A(n4022), .B(DmP_mant_SFG_SWR[36]), .S0(n3785), .Y(n1120)
);
AOI22X1TS U4402 ( .A0(n3870), .A1(n3871), .B0(n3805), .B1(n3815), .Y(n3779)
);
AOI21X1TS U4403 ( .A0(n1927), .A1(n3869), .B0(n3780), .Y(n3781) );
MX2X1TS U4404 ( .A(n4020), .B(DmP_mant_SFG_SWR[34]), .S0(n3785), .Y(n1122)
);
AOI22X1TS U4405 ( .A0(n3870), .A1(n3866), .B0(n3805), .B1(n3823), .Y(n3782)
);
AOI21X1TS U4406 ( .A0(n1927), .A1(n3865), .B0(n3783), .Y(n3784) );
MX2X1TS U4407 ( .A(n4018), .B(DmP_mant_SFG_SWR[33]), .S0(n3785), .Y(n1123)
);
AOI22X1TS U4408 ( .A0(n3870), .A1(n3862), .B0(n3805), .B1(n3844), .Y(n3786)
);
AOI21X1TS U4409 ( .A0(n1927), .A1(n3861), .B0(n3789), .Y(n3790) );
MX2X1TS U4410 ( .A(n4016), .B(DmP_mant_SFG_SWR[32]), .S0(n3854), .Y(n1124)
);
MX2X1TS U4411 ( .A(n4014), .B(DmP_mant_SFG_SWR[27]), .S0(n3854), .Y(n1129)
);
NAND2X1TS U4412 ( .A(n3797), .B(n1911), .Y(n3840) );
AOI22X1TS U4413 ( .A0(n3870), .A1(n3844), .B0(n3805), .B1(n3862), .Y(n3799)
);
AOI21X1TS U4414 ( .A0(n3808), .A1(n3861), .B0(n3800), .Y(n3801) );
MX2X1TS U4415 ( .A(n4015), .B(DmP_mant_SFG_SWR[22]), .S0(n3854), .Y(n1134)
);
AOI22X1TS U4416 ( .A0(n3870), .A1(n3823), .B0(n3805), .B1(n3866), .Y(n3802)
);
AOI21X1TS U4417 ( .A0(n3808), .A1(n3865), .B0(n3803), .Y(n3804) );
MX2X1TS U4418 ( .A(n4017), .B(DmP_mant_SFG_SWR[21]), .S0(n3854), .Y(n1135)
);
AOI22X1TS U4419 ( .A0(n3870), .A1(n3815), .B0(n3805), .B1(n3871), .Y(n3806)
);
AOI21X1TS U4420 ( .A0(n3808), .A1(n3869), .B0(n3807), .Y(n3809) );
MX2X1TS U4421 ( .A(n4019), .B(DmP_mant_SFG_SWR[20]), .S0(n3854), .Y(n1136)
);
OAI22X1TS U4422 ( .A0(n3812), .A1(n3840), .B0(n3811), .B1(n3838), .Y(n3813)
);
MX2X1TS U4423 ( .A(n4021), .B(DmP_mant_SFG_SWR[18]), .S0(n3854), .Y(n1138)
);
OAI22X1TS U4424 ( .A0(n3820), .A1(n3840), .B0(n3819), .B1(n3838), .Y(n3821)
);
MX2X1TS U4425 ( .A(n4023), .B(DmP_mant_SFG_SWR[17]), .S0(n3854), .Y(n1139)
);
AFHCONX2TS U4426 ( .A(DMP_SFG[32]), .B(n4049), .CI(n3826), .CON(n3330), .S(
n3833) );
AOI22X1TS U4427 ( .A0(n3831), .A1(n3830), .B0(Raw_mant_NRM_SWR[34]), .B1(
n3829), .Y(n3832) );
OAI2BB1X1TS U4428 ( .A0N(n3834), .A1N(n3833), .B0(n3832), .Y(n1235) );
OAI22X1TS U4429 ( .A0(n3841), .A1(n3840), .B0(n3839), .B1(n3838), .Y(n3842)
);
MX2X1TS U4430 ( .A(n4025), .B(DmP_mant_SFG_SWR[16]), .S0(n3854), .Y(n1140)
);
NAND2X1TS U4431 ( .A(left_right_SHT2), .B(n3847), .Y(n3873) );
AOI22X1TS U4432 ( .A0(n1927), .A1(n3849), .B0(n4126), .B1(n3848), .Y(n3850)
);
NAND2X1TS U4433 ( .A(n3873), .B(n3850), .Y(n4029) );
MX2X1TS U4434 ( .A(n4029), .B(DmP_mant_SFG_SWR[15]), .S0(n3979), .Y(n1141)
);
AOI22X1TS U4435 ( .A0(n1927), .A1(n3852), .B0(n4126), .B1(n3851), .Y(n3853)
);
NAND2X1TS U4436 ( .A(n3873), .B(n3853), .Y(n4031) );
MX2X1TS U4437 ( .A(n4031), .B(DmP_mant_SFG_SWR[14]), .S0(n3854), .Y(n1142)
);
AOI22X1TS U4438 ( .A0(n1927), .A1(n3856), .B0(n4126), .B1(n3855), .Y(n3857)
);
NAND2X1TS U4439 ( .A(n3873), .B(n3857), .Y(n4033) );
MX2X1TS U4440 ( .A(n4033), .B(DmP_mant_SFG_SWR[13]), .S0(n3979), .Y(n1143)
);
AOI22X1TS U4441 ( .A0(n1927), .A1(n3859), .B0(n4126), .B1(n3858), .Y(n3860)
);
NAND2X1TS U4442 ( .A(n3873), .B(n3860), .Y(n4036) );
MX2X1TS U4443 ( .A(n4036), .B(DmP_mant_SFG_SWR[12]), .S0(n3979), .Y(n1144)
);
AOI22X1TS U4444 ( .A0(n1927), .A1(n3862), .B0(n3870), .B1(n3861), .Y(n3863)
);
OAI211XLTS U4445 ( .A0(n3864), .A1(left_right_SHT2), .B0(n3873), .C0(n3863),
.Y(n4038) );
MX2X1TS U4446 ( .A(n4038), .B(DmP_mant_SFG_SWR[6]), .S0(n3979), .Y(n1150) );
AOI22X1TS U4447 ( .A0(n1927), .A1(n3866), .B0(n3870), .B1(n3865), .Y(n3867)
);
OAI211XLTS U4448 ( .A0(n3868), .A1(left_right_SHT2), .B0(n3873), .C0(n3867),
.Y(n4041) );
MX2X1TS U4449 ( .A(n4041), .B(DmP_mant_SFG_SWR[5]), .S0(n3979), .Y(n1151) );
AOI22X1TS U4450 ( .A0(n1926), .A1(n3871), .B0(n3870), .B1(n3869), .Y(n3872)
);
OAI211XLTS U4451 ( .A0(n3874), .A1(left_right_SHT2), .B0(n3873), .C0(n3872),
.Y(n4044) );
AOI22X1TS U4452 ( .A0(n2825), .A1(n3877), .B0(n3876), .B1(n3875), .Y(n3882)
);
AOI22X1TS U4453 ( .A0(n3880), .A1(n3879), .B0(n3878), .B1(Data_array_SWR[52]), .Y(n3881) );
NAND2X1TS U4454 ( .A(n3882), .B(n3881), .Y(n1750) );
MX2X1TS U4455 ( .A(DMP_exp_NRM2_EW[10]), .B(DMP_exp_NRM_EW[10]), .S0(n1920),
.Y(n1399) );
MX2X1TS U4456 ( .A(DMP_exp_NRM2_EW[9]), .B(DMP_exp_NRM_EW[9]), .S0(n1920),
.Y(n1404) );
MX2X1TS U4457 ( .A(DMP_exp_NRM2_EW[8]), .B(DMP_exp_NRM_EW[8]), .S0(n1921),
.Y(n1409) );
MX2X1TS U4458 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n1921),
.Y(n1414) );
MX2X1TS U4459 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n1921),
.Y(n1419) );
MX2X1TS U4460 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n1921),
.Y(n1424) );
MX2X1TS U4461 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n1921),
.Y(n1429) );
MX2X1TS U4462 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n1921),
.Y(n1434) );
MX2X1TS U4463 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n1921),
.Y(n1439) );
MX2X1TS U4464 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n1921),
.Y(n1444) );
MX2X1TS U4465 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n1921),
.Y(n1449) );
OAI2BB1X1TS U4466 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n1919), .B0(n3888),
.Y(n1210) );
OAI2BB1X1TS U4467 ( .A0N(n3897), .A1N(n3896), .B0(n3895), .Y(n1698) );
OA22X1TS U4468 ( .A0(n4028), .A1(n3901), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[55]), .Y(n1683) );
OA22X1TS U4469 ( .A0(n4028), .A1(n3902), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[56]), .Y(n1682) );
OA22X1TS U4470 ( .A0(n4028), .A1(n3906), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[60]), .Y(n1678) );
OAI2BB2XLTS U4471 ( .B0(n4028), .B1(n3908), .A0N(final_result_ieee[62]),
.A1N(n3914), .Y(n1676) );
AOI22X1TS U4472 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n3910), .B1(n4079), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U4473 ( .A(n3910), .B(n3909), .Y(n1892) );
INVX2TS U4474 ( .A(n3915), .Y(n3913) );
AOI22X1TS U4475 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n3911), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n4079), .Y(n3916) );
AO22XLTS U4476 ( .A0(n3913), .A1(Shift_reg_FLAGS_7_6), .B0(n3915), .B1(n3916), .Y(n1890) );
AOI22X1TS U4477 ( .A0(n3915), .A1(n3912), .B0(n4005), .B1(n3913), .Y(n1889)
);
AO22XLTS U4478 ( .A0(n3915), .A1(busy), .B0(n3913), .B1(Shift_reg_FLAGS_7[3]), .Y(n1887) );
AOI22X1TS U4479 ( .A0(n3915), .A1(n1919), .B0(n3914), .B1(n3913), .Y(n1884)
);
CLKBUFX2TS U4480 ( .A(n3937), .Y(n3945) );
CLKBUFX2TS U4481 ( .A(n3937), .Y(n3926) );
CLKBUFX2TS U4482 ( .A(n3926), .Y(n3918) );
INVX2TS U4483 ( .A(n3918), .Y(n3942) );
AO22XLTS U4484 ( .A0(n3945), .A1(Data_X[0]), .B0(n3942), .B1(intDX_EWSW[0]),
.Y(n1883) );
CLKBUFX2TS U4485 ( .A(n3937), .Y(n3943) );
INVX2TS U4486 ( .A(n3943), .Y(n3917) );
AO22XLTS U4487 ( .A0(n3918), .A1(Data_X[1]), .B0(n3917), .B1(intDX_EWSW[1]),
.Y(n1882) );
CLKBUFX2TS U4488 ( .A(n3926), .Y(n3923) );
AO22XLTS U4489 ( .A0(n3923), .A1(Data_X[2]), .B0(n3917), .B1(intDX_EWSW[2]),
.Y(n1881) );
CLKBUFX2TS U4490 ( .A(n3926), .Y(n3927) );
AO22XLTS U4491 ( .A0(n3927), .A1(Data_X[3]), .B0(n3917), .B1(intDX_EWSW[3]),
.Y(n1880) );
AO22XLTS U4492 ( .A0(n3923), .A1(Data_X[4]), .B0(n3917), .B1(intDX_EWSW[4]),
.Y(n1879) );
AO22XLTS U4493 ( .A0(n3918), .A1(Data_X[5]), .B0(n3917), .B1(intDX_EWSW[5]),
.Y(n1878) );
AO22XLTS U4494 ( .A0(n3918), .A1(Data_X[6]), .B0(n3917), .B1(intDX_EWSW[6]),
.Y(n1877) );
AO22XLTS U4495 ( .A0(n3918), .A1(Data_X[7]), .B0(n3917), .B1(intDX_EWSW[7]),
.Y(n1876) );
CLKBUFX2TS U4496 ( .A(n3926), .Y(n3925) );
AO22XLTS U4497 ( .A0(n3925), .A1(Data_X[8]), .B0(n3917), .B1(intDX_EWSW[8]),
.Y(n1875) );
AO22XLTS U4498 ( .A0(n3918), .A1(Data_X[9]), .B0(n3917), .B1(intDX_EWSW[9]),
.Y(n1874) );
INVX2TS U4499 ( .A(n3945), .Y(n3919) );
AO22XLTS U4500 ( .A0(n3923), .A1(Data_X[10]), .B0(n3919), .B1(intDX_EWSW[10]), .Y(n1873) );
AO22XLTS U4501 ( .A0(n3918), .A1(Data_X[11]), .B0(n3919), .B1(intDX_EWSW[11]), .Y(n1872) );
AO22XLTS U4502 ( .A0(n3918), .A1(Data_X[12]), .B0(n3919), .B1(intDX_EWSW[12]), .Y(n1871) );
AO22XLTS U4503 ( .A0(n3927), .A1(Data_X[13]), .B0(n3919), .B1(intDX_EWSW[13]), .Y(n1870) );
AO22XLTS U4504 ( .A0(n3918), .A1(Data_X[14]), .B0(n3919), .B1(intDX_EWSW[14]), .Y(n1869) );
AO22XLTS U4505 ( .A0(n3927), .A1(Data_X[15]), .B0(n3919), .B1(intDX_EWSW[15]), .Y(n1868) );
AO22XLTS U4506 ( .A0(n3923), .A1(Data_X[16]), .B0(n3919), .B1(intDX_EWSW[16]), .Y(n1867) );
AO22XLTS U4507 ( .A0(n3918), .A1(Data_X[17]), .B0(n3919), .B1(intDX_EWSW[17]), .Y(n1866) );
AO22XLTS U4508 ( .A0(n3927), .A1(Data_X[18]), .B0(n3919), .B1(intDX_EWSW[18]), .Y(n1865) );
AO22XLTS U4509 ( .A0(n3927), .A1(Data_X[19]), .B0(n3919), .B1(intDX_EWSW[19]), .Y(n1864) );
CLKBUFX2TS U4510 ( .A(n3937), .Y(n3922) );
INVX2TS U4511 ( .A(n3922), .Y(n3920) );
AO22XLTS U4512 ( .A0(n3927), .A1(Data_X[20]), .B0(n3920), .B1(intDX_EWSW[20]), .Y(n1863) );
AO22XLTS U4513 ( .A0(n3927), .A1(Data_X[21]), .B0(n3920), .B1(intDX_EWSW[21]), .Y(n1862) );
AO22XLTS U4514 ( .A0(n3922), .A1(Data_X[22]), .B0(n3920), .B1(intDX_EWSW[22]), .Y(n1861) );
AO22XLTS U4515 ( .A0(n3922), .A1(Data_X[23]), .B0(n3920), .B1(intDX_EWSW[23]), .Y(n1860) );
AO22XLTS U4516 ( .A0(n3945), .A1(Data_X[24]), .B0(n3920), .B1(intDX_EWSW[24]), .Y(n1859) );
AO22XLTS U4517 ( .A0(n3945), .A1(Data_X[25]), .B0(n3920), .B1(intDX_EWSW[25]), .Y(n1858) );
AO22XLTS U4518 ( .A0(n3945), .A1(Data_X[26]), .B0(n3920), .B1(intDX_EWSW[26]), .Y(n1857) );
AO22XLTS U4519 ( .A0(n3943), .A1(Data_X[27]), .B0(n3920), .B1(intDX_EWSW[27]), .Y(n1856) );
AO22XLTS U4520 ( .A0(n3945), .A1(Data_X[28]), .B0(n3920), .B1(intDX_EWSW[28]), .Y(n1855) );
AO22XLTS U4521 ( .A0(n3945), .A1(Data_X[29]), .B0(n3920), .B1(intDX_EWSW[29]), .Y(n1854) );
INVX2TS U4522 ( .A(n3925), .Y(n3921) );
AO22XLTS U4523 ( .A0(n3945), .A1(Data_X[30]), .B0(n3921), .B1(intDX_EWSW[30]), .Y(n1853) );
AO22XLTS U4524 ( .A0(n3925), .A1(Data_X[31]), .B0(n3921), .B1(intDX_EWSW[31]), .Y(n1852) );
AO22XLTS U4525 ( .A0(n3925), .A1(Data_X[32]), .B0(n3921), .B1(intDX_EWSW[32]), .Y(n1851) );
AO22XLTS U4526 ( .A0(n3922), .A1(Data_X[33]), .B0(n3921), .B1(intDX_EWSW[33]), .Y(n1850) );
AO22XLTS U4527 ( .A0(n3925), .A1(Data_X[34]), .B0(n3921), .B1(intDX_EWSW[34]), .Y(n1849) );
AO22XLTS U4528 ( .A0(n3922), .A1(Data_X[35]), .B0(n3921), .B1(intDX_EWSW[35]), .Y(n1848) );
AO22XLTS U4529 ( .A0(n3922), .A1(Data_X[36]), .B0(n3921), .B1(intDX_EWSW[36]), .Y(n1847) );
AO22XLTS U4530 ( .A0(n3922), .A1(Data_X[37]), .B0(n3921), .B1(intDX_EWSW[37]), .Y(n1846) );
AO22XLTS U4531 ( .A0(n3922), .A1(Data_X[38]), .B0(n3921), .B1(intDX_EWSW[38]), .Y(n1845) );
AO22XLTS U4532 ( .A0(n3922), .A1(Data_X[39]), .B0(n3921), .B1(intDX_EWSW[39]), .Y(n1844) );
INVX2TS U4533 ( .A(n3923), .Y(n3924) );
AO22XLTS U4534 ( .A0(n3922), .A1(Data_X[40]), .B0(n3924), .B1(intDX_EWSW[40]), .Y(n1843) );
AO22XLTS U4535 ( .A0(n3923), .A1(Data_X[41]), .B0(n3924), .B1(intDX_EWSW[41]), .Y(n1842) );
AO22XLTS U4536 ( .A0(n3923), .A1(Data_X[42]), .B0(n3924), .B1(intDX_EWSW[42]), .Y(n1841) );
AO22XLTS U4537 ( .A0(n3923), .A1(Data_X[43]), .B0(n3924), .B1(intDX_EWSW[43]), .Y(n1840) );
AO22XLTS U4538 ( .A0(n3923), .A1(Data_X[44]), .B0(n3924), .B1(intDX_EWSW[44]), .Y(n1839) );
AO22XLTS U4539 ( .A0(n3923), .A1(Data_X[45]), .B0(n3924), .B1(intDX_EWSW[45]), .Y(n1838) );
AO22XLTS U4540 ( .A0(n3925), .A1(Data_X[46]), .B0(n3924), .B1(intDX_EWSW[46]), .Y(n1837) );
AO22XLTS U4541 ( .A0(n3925), .A1(Data_X[47]), .B0(n3924), .B1(intDX_EWSW[47]), .Y(n1836) );
AO22XLTS U4542 ( .A0(n3925), .A1(Data_X[48]), .B0(n3924), .B1(intDX_EWSW[48]), .Y(n1835) );
CLKBUFX2TS U4543 ( .A(n3926), .Y(n3933) );
INVX2TS U4544 ( .A(n3933), .Y(n3932) );
CLKBUFX2TS U4545 ( .A(n3926), .Y(n3938) );
AO22XLTS U4546 ( .A0(n3932), .A1(intDX_EWSW[49]), .B0(n3938), .B1(Data_X[49]), .Y(n1834) );
AO22XLTS U4547 ( .A0(n3925), .A1(Data_X[50]), .B0(n3924), .B1(intDX_EWSW[50]), .Y(n1833) );
AO22XLTS U4548 ( .A0(n3925), .A1(Data_X[51]), .B0(n3942), .B1(intDX_EWSW[51]), .Y(n1832) );
AO22XLTS U4549 ( .A0(n3945), .A1(Data_X[52]), .B0(n3942), .B1(intDX_EWSW[52]), .Y(n1831) );
CLKBUFX2TS U4550 ( .A(n3926), .Y(n3931) );
INVX2TS U4551 ( .A(n3931), .Y(n3929) );
AO22XLTS U4552 ( .A0(n3929), .A1(intDX_EWSW[53]), .B0(n3938), .B1(Data_X[53]), .Y(n1830) );
INVX2TS U4553 ( .A(n3938), .Y(n3928) );
AO22XLTS U4554 ( .A0(n3928), .A1(intDX_EWSW[54]), .B0(n3927), .B1(Data_X[54]), .Y(n1829) );
AO22XLTS U4555 ( .A0(n3929), .A1(intDX_EWSW[55]), .B0(n3927), .B1(Data_X[55]), .Y(n1828) );
CLKBUFX2TS U4556 ( .A(n3937), .Y(n3934) );
CLKBUFX2TS U4557 ( .A(n3934), .Y(n3930) );
AO22XLTS U4558 ( .A0(n3928), .A1(intDX_EWSW[56]), .B0(n3930), .B1(Data_X[56]), .Y(n1827) );
AO22XLTS U4559 ( .A0(n3943), .A1(Data_X[57]), .B0(n3942), .B1(intDX_EWSW[57]), .Y(n1826) );
AO22XLTS U4560 ( .A0(n3928), .A1(intDX_EWSW[58]), .B0(n3938), .B1(Data_X[58]), .Y(n1825) );
AO22XLTS U4561 ( .A0(n3928), .A1(intDX_EWSW[59]), .B0(n3938), .B1(Data_X[59]), .Y(n1824) );
AO22XLTS U4562 ( .A0(n3928), .A1(intDX_EWSW[60]), .B0(n3930), .B1(Data_X[60]), .Y(n1823) );
AO22XLTS U4563 ( .A0(n3929), .A1(intDX_EWSW[61]), .B0(n3938), .B1(Data_X[61]), .Y(n1822) );
AO22XLTS U4564 ( .A0(n3928), .A1(intDX_EWSW[62]), .B0(n3938), .B1(Data_X[62]), .Y(n1821) );
AO22XLTS U4565 ( .A0(n3943), .A1(Data_X[63]), .B0(n3942), .B1(intDX_EWSW[63]), .Y(n1820) );
AO22XLTS U4566 ( .A0(n3943), .A1(add_subt), .B0(n3942), .B1(intAS), .Y(n1819) );
AO22XLTS U4567 ( .A0(n3928), .A1(intDY_EWSW[0]), .B0(n3938), .B1(Data_Y[0]),
.Y(n1818) );
INVX2TS U4568 ( .A(n3927), .Y(n3944) );
AO22XLTS U4569 ( .A0(n3944), .A1(intDY_EWSW[1]), .B0(n3930), .B1(Data_Y[1]),
.Y(n1817) );
AO22XLTS U4570 ( .A0(n3928), .A1(intDY_EWSW[2]), .B0(n3930), .B1(Data_Y[2]),
.Y(n1816) );
AO22XLTS U4571 ( .A0(n3944), .A1(intDY_EWSW[3]), .B0(n3933), .B1(Data_Y[3]),
.Y(n1815) );
AO22XLTS U4572 ( .A0(n3944), .A1(intDY_EWSW[4]), .B0(n3930), .B1(Data_Y[4]),
.Y(n1814) );
AO22XLTS U4573 ( .A0(n3944), .A1(intDY_EWSW[5]), .B0(n3930), .B1(Data_Y[5]),
.Y(n1813) );
AO22XLTS U4574 ( .A0(n3944), .A1(intDY_EWSW[6]), .B0(n3930), .B1(Data_Y[6]),
.Y(n1812) );
AO22XLTS U4575 ( .A0(n3944), .A1(intDY_EWSW[7]), .B0(n3933), .B1(Data_Y[7]),
.Y(n1811) );
CLKBUFX2TS U4576 ( .A(n3934), .Y(n3939) );
AO22XLTS U4577 ( .A0(n3944), .A1(intDY_EWSW[8]), .B0(n3939), .B1(Data_Y[8]),
.Y(n1810) );
AO22XLTS U4578 ( .A0(n3944), .A1(intDY_EWSW[9]), .B0(n3939), .B1(Data_Y[9]),
.Y(n1809) );
AO22XLTS U4579 ( .A0(n3928), .A1(intDY_EWSW[10]), .B0(n3939), .B1(Data_Y[10]), .Y(n1808) );
AO22XLTS U4580 ( .A0(n3928), .A1(intDY_EWSW[11]), .B0(n3930), .B1(Data_Y[11]), .Y(n1807) );
AO22XLTS U4581 ( .A0(n3929), .A1(intDY_EWSW[12]), .B0(n3933), .B1(Data_Y[12]), .Y(n1806) );
AO22XLTS U4582 ( .A0(n3929), .A1(intDY_EWSW[13]), .B0(n3933), .B1(Data_Y[13]), .Y(n1805) );
AO22XLTS U4583 ( .A0(n3929), .A1(intDY_EWSW[14]), .B0(n3933), .B1(Data_Y[14]), .Y(n1804) );
AO22XLTS U4584 ( .A0(n3929), .A1(intDY_EWSW[15]), .B0(n3931), .B1(Data_Y[15]), .Y(n1803) );
AO22XLTS U4585 ( .A0(n3929), .A1(intDY_EWSW[16]), .B0(n3933), .B1(Data_Y[16]), .Y(n1802) );
AO22XLTS U4586 ( .A0(n3929), .A1(intDY_EWSW[17]), .B0(n3933), .B1(Data_Y[17]), .Y(n1801) );
AO22XLTS U4587 ( .A0(n3932), .A1(intDY_EWSW[18]), .B0(n3933), .B1(Data_Y[18]), .Y(n1800) );
CLKBUFX2TS U4588 ( .A(n3934), .Y(n3940) );
AO22XLTS U4589 ( .A0(n3929), .A1(intDY_EWSW[19]), .B0(n3940), .B1(Data_Y[19]), .Y(n1799) );
AO22XLTS U4590 ( .A0(n3932), .A1(intDY_EWSW[20]), .B0(n3930), .B1(Data_Y[20]), .Y(n1798) );
AO22XLTS U4591 ( .A0(n3932), .A1(intDY_EWSW[21]), .B0(n3931), .B1(Data_Y[21]), .Y(n1797) );
AO22XLTS U4592 ( .A0(n3932), .A1(intDY_EWSW[22]), .B0(n3931), .B1(Data_Y[22]), .Y(n1796) );
AO22XLTS U4593 ( .A0(n3932), .A1(intDY_EWSW[23]), .B0(n3931), .B1(Data_Y[23]), .Y(n1795) );
AO22XLTS U4594 ( .A0(n3932), .A1(intDY_EWSW[24]), .B0(n3931), .B1(Data_Y[24]), .Y(n1794) );
AO22XLTS U4595 ( .A0(n3932), .A1(intDY_EWSW[25]), .B0(n3931), .B1(Data_Y[25]), .Y(n1793) );
INVX2TS U4596 ( .A(n3930), .Y(n3935) );
AO22XLTS U4597 ( .A0(n3935), .A1(intDY_EWSW[26]), .B0(n3931), .B1(Data_Y[26]), .Y(n1792) );
AO22XLTS U4598 ( .A0(n3932), .A1(intDY_EWSW[27]), .B0(n3937), .B1(Data_Y[27]), .Y(n1791) );
AO22XLTS U4599 ( .A0(n3935), .A1(intDY_EWSW[28]), .B0(n3931), .B1(Data_Y[28]), .Y(n1790) );
AO22XLTS U4600 ( .A0(n3932), .A1(intDY_EWSW[29]), .B0(n3931), .B1(Data_Y[29]), .Y(n1789) );
AO22XLTS U4601 ( .A0(n3935), .A1(intDY_EWSW[30]), .B0(n3933), .B1(Data_Y[30]), .Y(n1788) );
AO22XLTS U4602 ( .A0(n3935), .A1(intDY_EWSW[31]), .B0(n3934), .B1(Data_Y[31]), .Y(n1787) );
INVX2TS U4603 ( .A(n3939), .Y(n3936) );
AO22XLTS U4604 ( .A0(n3936), .A1(intDY_EWSW[32]), .B0(n3937), .B1(Data_Y[32]), .Y(n1786) );
AO22XLTS U4605 ( .A0(n3935), .A1(intDY_EWSW[33]), .B0(n3934), .B1(Data_Y[33]), .Y(n1785) );
AO22XLTS U4606 ( .A0(n3935), .A1(intDY_EWSW[34]), .B0(n3934), .B1(Data_Y[34]), .Y(n1784) );
AO22XLTS U4607 ( .A0(n3935), .A1(intDY_EWSW[35]), .B0(n3934), .B1(Data_Y[35]), .Y(n1783) );
AO22XLTS U4608 ( .A0(n3935), .A1(intDY_EWSW[36]), .B0(n3934), .B1(Data_Y[36]), .Y(n1782) );
AO22XLTS U4609 ( .A0(n3935), .A1(intDY_EWSW[37]), .B0(n3934), .B1(Data_Y[37]), .Y(n1781) );
AO22XLTS U4610 ( .A0(n3936), .A1(intDY_EWSW[38]), .B0(n3934), .B1(Data_Y[38]), .Y(n1780) );
AO22XLTS U4611 ( .A0(n3935), .A1(intDY_EWSW[39]), .B0(n3940), .B1(Data_Y[39]), .Y(n1779) );
AO22XLTS U4612 ( .A0(n3936), .A1(intDY_EWSW[40]), .B0(n3938), .B1(Data_Y[40]), .Y(n1778) );
AO22XLTS U4613 ( .A0(n3936), .A1(intDY_EWSW[41]), .B0(n3940), .B1(Data_Y[41]), .Y(n1777) );
AO22XLTS U4614 ( .A0(n3936), .A1(intDY_EWSW[42]), .B0(n3940), .B1(Data_Y[42]), .Y(n1776) );
AO22XLTS U4615 ( .A0(n3936), .A1(intDY_EWSW[43]), .B0(n3940), .B1(Data_Y[43]), .Y(n1775) );
INVX2TS U4616 ( .A(n3940), .Y(n3941) );
AO22XLTS U4617 ( .A0(n3941), .A1(intDY_EWSW[44]), .B0(n3940), .B1(Data_Y[44]), .Y(n1774) );
AO22XLTS U4618 ( .A0(n3936), .A1(intDY_EWSW[45]), .B0(n3940), .B1(Data_Y[45]), .Y(n1773) );
AO22XLTS U4619 ( .A0(n3936), .A1(intDY_EWSW[46]), .B0(n3940), .B1(Data_Y[46]), .Y(n1772) );
AO22XLTS U4620 ( .A0(n3936), .A1(intDY_EWSW[47]), .B0(n3939), .B1(Data_Y[47]), .Y(n1771) );
AO22XLTS U4621 ( .A0(n3941), .A1(intDY_EWSW[48]), .B0(n3937), .B1(Data_Y[48]), .Y(n1770) );
AO22XLTS U4622 ( .A0(n3936), .A1(intDY_EWSW[49]), .B0(n3937), .B1(Data_Y[49]), .Y(n1769) );
AO22XLTS U4623 ( .A0(n3941), .A1(intDY_EWSW[50]), .B0(n3937), .B1(Data_Y[50]), .Y(n1768) );
AO22XLTS U4624 ( .A0(n3941), .A1(intDY_EWSW[51]), .B0(n3939), .B1(Data_Y[51]), .Y(n1767) );
AO22XLTS U4625 ( .A0(n3941), .A1(intDY_EWSW[52]), .B0(n3939), .B1(Data_Y[52]), .Y(n1766) );
AO22XLTS U4626 ( .A0(n3941), .A1(intDY_EWSW[53]), .B0(n3939), .B1(Data_Y[53]), .Y(n1765) );
AO22XLTS U4627 ( .A0(n3941), .A1(intDY_EWSW[54]), .B0(n3939), .B1(Data_Y[54]), .Y(n1764) );
AO22XLTS U4628 ( .A0(n3941), .A1(intDY_EWSW[55]), .B0(n3938), .B1(Data_Y[55]), .Y(n1763) );
AO22XLTS U4629 ( .A0(n3941), .A1(intDY_EWSW[56]), .B0(n3939), .B1(Data_Y[56]), .Y(n1762) );
AO22XLTS U4630 ( .A0(n3941), .A1(intDY_EWSW[57]), .B0(n3940), .B1(Data_Y[57]), .Y(n1761) );
AO22XLTS U4631 ( .A0(n3943), .A1(Data_Y[58]), .B0(n3942), .B1(intDY_EWSW[58]), .Y(n1760) );
AO22XLTS U4632 ( .A0(n3943), .A1(Data_Y[60]), .B0(n3942), .B1(intDY_EWSW[60]), .Y(n1758) );
AO22XLTS U4633 ( .A0(n3943), .A1(Data_Y[61]), .B0(n3944), .B1(intDY_EWSW[61]), .Y(n1757) );
AO22XLTS U4634 ( .A0(n3945), .A1(Data_Y[63]), .B0(n3944), .B1(intDY_EWSW[63]), .Y(n1755) );
AOI22X1TS U4635 ( .A0(DMP_EXP_EWSW[53]), .A1(n4226), .B0(n3947), .B1(n3946),
.Y(n3950) );
NOR2XLTS U4636 ( .A(n4212), .B(DMP_EXP_EWSW[54]), .Y(n3951) );
AOI21X1TS U4637 ( .A0(DMP_EXP_EWSW[54]), .A1(n4212), .B0(n3951), .Y(n3948)
);
XNOR2X1TS U4638 ( .A(n3950), .B(n3948), .Y(n3949) );
AO22XLTS U4639 ( .A0(n4003), .A1(n3949), .B0(n4005), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n1690) );
OAI22X1TS U4640 ( .A0(n3951), .A1(n3950), .B0(DmP_EXP_EWSW[54]), .B1(n4225),
.Y(n3954) );
NAND2X1TS U4641 ( .A(DmP_EXP_EWSW[55]), .B(n4214), .Y(n3955) );
XNOR2X1TS U4642 ( .A(n3954), .B(n3952), .Y(n3953) );
AO22XLTS U4643 ( .A0(n3995), .A1(n3953), .B0(n4005), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n1689) );
AOI22X1TS U4644 ( .A0(DMP_EXP_EWSW[55]), .A1(n4247), .B0(n3955), .B1(n3954),
.Y(n3958) );
AOI21X1TS U4645 ( .A0(DMP_EXP_EWSW[56]), .A1(n4243), .B0(n3959), .Y(n3956)
);
XNOR2X1TS U4646 ( .A(n3958), .B(n3956), .Y(n3957) );
AO22XLTS U4647 ( .A0(n3992), .A1(n3957), .B0(n4005), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n1688) );
OAI22X1TS U4648 ( .A0(n3959), .A1(n3958), .B0(DmP_EXP_EWSW[56]), .B1(n4246),
.Y(n3961) );
XNOR2X1TS U4649 ( .A(DmP_EXP_EWSW[57]), .B(DMP_EXP_EWSW[57]), .Y(n3960) );
XOR2XLTS U4650 ( .A(n3961), .B(n3960), .Y(n3962) );
AO22XLTS U4651 ( .A0(n3974), .A1(n3962), .B0(n4005), .B1(
Shift_amount_SHT1_EWR[5]), .Y(n1687) );
OAI222X1TS U4652 ( .A0(n3999), .A1(n4244), .B0(n4213), .B1(
Shift_reg_FLAGS_7_6), .C0(n4054), .C1(n4000), .Y(n1622) );
OAI222X1TS U4653 ( .A0(n3999), .A1(n4096), .B0(n4225), .B1(
Shift_reg_FLAGS_7_6), .C0(n4080), .C1(n4000), .Y(n1621) );
OAI222X1TS U4654 ( .A0(n3999), .A1(n4245), .B0(n4214), .B1(
Shift_reg_FLAGS_7_6), .C0(n4063), .C1(n4000), .Y(n1620) );
OAI222X1TS U4655 ( .A0(n3999), .A1(n4097), .B0(n4246), .B1(
Shift_reg_FLAGS_7_6), .C0(n4055), .C1(n4000), .Y(n1619) );
OAI21XLTS U4656 ( .A0(n3964), .A1(intDX_EWSW[63]), .B0(Shift_reg_FLAGS_7_6),
.Y(n3963) );
AOI21X1TS U4657 ( .A0(n3964), .A1(intDX_EWSW[63]), .B0(n3963), .Y(n3965) );
AO21XLTS U4658 ( .A0(OP_FLAG_EXP), .A1(n4360), .B0(n3965), .Y(n1612) );
AO22XLTS U4659 ( .A0(n3966), .A1(n3965), .B0(ZERO_FLAG_EXP), .B1(n4360), .Y(
n1611) );
AO22XLTS U4660 ( .A0(n3974), .A1(DMP_EXP_EWSW[0]), .B0(n4005), .B1(
DMP_SHT1_EWSW[0]), .Y(n1609) );
CLKBUFX2TS U4661 ( .A(Shift_reg_FLAGS_7_5), .Y(n4006) );
CLKBUFX2TS U4662 ( .A(n4006), .Y(n3985) );
INVX2TS U4663 ( .A(n3985), .Y(n3967) );
AO22XLTS U4664 ( .A0(n3988), .A1(DMP_EXP_EWSW[1]), .B0(n3967), .B1(
DMP_SHT1_EWSW[1]), .Y(n1606) );
CLKBUFX2TS U4665 ( .A(n4006), .Y(n3987) );
AO22XLTS U4666 ( .A0(n3987), .A1(DMP_EXP_EWSW[2]), .B0(n3967), .B1(
DMP_SHT1_EWSW[2]), .Y(n1603) );
AO22XLTS U4667 ( .A0(n3987), .A1(DMP_EXP_EWSW[3]), .B0(n3967), .B1(
DMP_SHT1_EWSW[3]), .Y(n1600) );
AO22XLTS U4668 ( .A0(n3987), .A1(DMP_EXP_EWSW[4]), .B0(n3967), .B1(
DMP_SHT1_EWSW[4]), .Y(n1597) );
AO22XLTS U4669 ( .A0(n3987), .A1(DMP_EXP_EWSW[5]), .B0(n3967), .B1(
DMP_SHT1_EWSW[5]), .Y(n1594) );
AO22XLTS U4670 ( .A0(n3987), .A1(DMP_EXP_EWSW[6]), .B0(n3967), .B1(
DMP_SHT1_EWSW[6]), .Y(n1591) );
CLKBUFX2TS U4671 ( .A(n4006), .Y(n3986) );
AO22XLTS U4672 ( .A0(n3986), .A1(DMP_EXP_EWSW[7]), .B0(n3967), .B1(
DMP_SHT1_EWSW[7]), .Y(n1588) );
AO22XLTS U4673 ( .A0(n3986), .A1(DMP_EXP_EWSW[8]), .B0(n3967), .B1(
DMP_SHT1_EWSW[8]), .Y(n1585) );
AO22XLTS U4674 ( .A0(n3986), .A1(DMP_EXP_EWSW[9]), .B0(n3967), .B1(
DMP_SHT1_EWSW[9]), .Y(n1582) );
AO22XLTS U4675 ( .A0(n3986), .A1(DMP_EXP_EWSW[10]), .B0(n3967), .B1(
DMP_SHT1_EWSW[10]), .Y(n1579) );
CLKBUFX2TS U4676 ( .A(n4003), .Y(n3989) );
INVX2TS U4677 ( .A(n3989), .Y(n3968) );
AO22XLTS U4678 ( .A0(n3986), .A1(DMP_EXP_EWSW[11]), .B0(n3968), .B1(
DMP_SHT1_EWSW[11]), .Y(n1576) );
AO22XLTS U4679 ( .A0(n3985), .A1(DMP_EXP_EWSW[12]), .B0(n3968), .B1(
DMP_SHT1_EWSW[12]), .Y(n1573) );
AO22XLTS U4680 ( .A0(n3986), .A1(DMP_EXP_EWSW[13]), .B0(n3968), .B1(
DMP_SHT1_EWSW[13]), .Y(n1570) );
AO22XLTS U4681 ( .A0(n3985), .A1(DMP_EXP_EWSW[14]), .B0(n3968), .B1(
DMP_SHT1_EWSW[14]), .Y(n1567) );
AO22XLTS U4682 ( .A0(n3986), .A1(DMP_EXP_EWSW[15]), .B0(n3968), .B1(
DMP_SHT1_EWSW[15]), .Y(n1564) );
AO22XLTS U4683 ( .A0(n4006), .A1(DMP_EXP_EWSW[16]), .B0(n3968), .B1(
DMP_SHT1_EWSW[16]), .Y(n1561) );
CLKBUFX2TS U4684 ( .A(n3974), .Y(n3990) );
AO22XLTS U4685 ( .A0(n3990), .A1(DMP_EXP_EWSW[17]), .B0(n3968), .B1(
DMP_SHT1_EWSW[17]), .Y(n1558) );
AO22XLTS U4686 ( .A0(n3990), .A1(DMP_EXP_EWSW[18]), .B0(n3968), .B1(
DMP_SHT1_EWSW[18]), .Y(n1555) );
AO22XLTS U4687 ( .A0(n3990), .A1(DMP_EXP_EWSW[19]), .B0(n3968), .B1(
DMP_SHT1_EWSW[19]), .Y(n1552) );
AO22XLTS U4688 ( .A0(n3990), .A1(DMP_EXP_EWSW[20]), .B0(n3968), .B1(
DMP_SHT1_EWSW[20]), .Y(n1549) );
INVX2TS U4689 ( .A(n3990), .Y(n3969) );
AO22XLTS U4690 ( .A0(n3990), .A1(DMP_EXP_EWSW[21]), .B0(n3969), .B1(
DMP_SHT1_EWSW[21]), .Y(n1546) );
AO22XLTS U4691 ( .A0(n3989), .A1(DMP_EXP_EWSW[22]), .B0(n3969), .B1(
DMP_SHT1_EWSW[22]), .Y(n1543) );
AO22XLTS U4692 ( .A0(n3989), .A1(DMP_EXP_EWSW[23]), .B0(n3969), .B1(
DMP_SHT1_EWSW[23]), .Y(n1540) );
AO22XLTS U4693 ( .A0(n3989), .A1(DMP_EXP_EWSW[24]), .B0(n3969), .B1(
DMP_SHT1_EWSW[24]), .Y(n1537) );
INVX2TS U4694 ( .A(n3987), .Y(n3981) );
AO22XLTS U4695 ( .A0(n3989), .A1(DMP_EXP_EWSW[25]), .B0(n3981), .B1(
DMP_SHT1_EWSW[25]), .Y(n1534) );
AO22XLTS U4696 ( .A0(n3989), .A1(DMP_EXP_EWSW[26]), .B0(n3969), .B1(
DMP_SHT1_EWSW[26]), .Y(n1531) );
AO22XLTS U4697 ( .A0(n3985), .A1(DMP_EXP_EWSW[27]), .B0(n3969), .B1(
DMP_SHT1_EWSW[27]), .Y(n1528) );
AO22XLTS U4698 ( .A0(n3985), .A1(DMP_EXP_EWSW[28]), .B0(n3969), .B1(
DMP_SHT1_EWSW[28]), .Y(n1525) );
AO22XLTS U4699 ( .A0(n3985), .A1(DMP_EXP_EWSW[29]), .B0(n3969), .B1(
DMP_SHT1_EWSW[29]), .Y(n1522) );
AO22XLTS U4700 ( .A0(n3985), .A1(DMP_EXP_EWSW[30]), .B0(n3969), .B1(
DMP_SHT1_EWSW[30]), .Y(n1519) );
AO22XLTS U4701 ( .A0(n3985), .A1(DMP_EXP_EWSW[31]), .B0(n3969), .B1(
DMP_SHT1_EWSW[31]), .Y(n1516) );
INVX2TS U4702 ( .A(n3987), .Y(n3971) );
AO22XLTS U4703 ( .A0(n3988), .A1(DMP_EXP_EWSW[32]), .B0(n3971), .B1(
DMP_SHT1_EWSW[32]), .Y(n1513) );
AO22XLTS U4704 ( .A0(n3988), .A1(DMP_EXP_EWSW[33]), .B0(n3971), .B1(
DMP_SHT1_EWSW[33]), .Y(n1510) );
AO22XLTS U4705 ( .A0(n3988), .A1(DMP_EXP_EWSW[34]), .B0(n3971), .B1(
DMP_SHT1_EWSW[34]), .Y(n1507) );
AO22XLTS U4706 ( .A0(n3988), .A1(DMP_EXP_EWSW[35]), .B0(n3971), .B1(
DMP_SHT1_EWSW[35]), .Y(n1504) );
AO22XLTS U4707 ( .A0(n3970), .A1(DMP_SHT1_EWSW[35]), .B0(n3972), .B1(
DMP_SHT2_EWSW[35]), .Y(n1503) );
AO22XLTS U4708 ( .A0(n3988), .A1(DMP_EXP_EWSW[36]), .B0(n3971), .B1(
DMP_SHT1_EWSW[36]), .Y(n1501) );
AO22XLTS U4709 ( .A0(n3970), .A1(DMP_SHT1_EWSW[36]), .B0(n3972), .B1(
DMP_SHT2_EWSW[36]), .Y(n1500) );
CLKBUFX2TS U4710 ( .A(n4003), .Y(n3973) );
AO22XLTS U4711 ( .A0(n3973), .A1(DMP_EXP_EWSW[37]), .B0(n3971), .B1(
DMP_SHT1_EWSW[37]), .Y(n1498) );
AO22XLTS U4712 ( .A0(n3970), .A1(DMP_SHT1_EWSW[37]), .B0(n3972), .B1(
DMP_SHT2_EWSW[37]), .Y(n1497) );
AO22XLTS U4713 ( .A0(n3973), .A1(DMP_EXP_EWSW[38]), .B0(n3971), .B1(
DMP_SHT1_EWSW[38]), .Y(n1495) );
AO22XLTS U4714 ( .A0(n3970), .A1(DMP_SHT1_EWSW[38]), .B0(n3972), .B1(
DMP_SHT2_EWSW[38]), .Y(n1494) );
AO22XLTS U4715 ( .A0(n3973), .A1(DMP_EXP_EWSW[39]), .B0(n3971), .B1(
DMP_SHT1_EWSW[39]), .Y(n1492) );
AO22XLTS U4716 ( .A0(n4094), .A1(DMP_SHT1_EWSW[39]), .B0(n3972), .B1(
DMP_SHT2_EWSW[39]), .Y(n1491) );
AO22XLTS U4717 ( .A0(n3973), .A1(DMP_EXP_EWSW[40]), .B0(n3971), .B1(
DMP_SHT1_EWSW[40]), .Y(n1489) );
AO22XLTS U4718 ( .A0(n4094), .A1(DMP_SHT1_EWSW[40]), .B0(n3972), .B1(
DMP_SHT2_EWSW[40]), .Y(n1488) );
AO22XLTS U4719 ( .A0(n3973), .A1(DMP_EXP_EWSW[41]), .B0(n3971), .B1(
DMP_SHT1_EWSW[41]), .Y(n1486) );
AO22XLTS U4720 ( .A0(n4094), .A1(DMP_SHT1_EWSW[41]), .B0(n3972), .B1(
DMP_SHT2_EWSW[41]), .Y(n1485) );
INVX2TS U4721 ( .A(n3986), .Y(n3975) );
AO22XLTS U4722 ( .A0(n3973), .A1(DMP_EXP_EWSW[42]), .B0(n3975), .B1(
DMP_SHT1_EWSW[42]), .Y(n1483) );
CLKBUFX2TS U4723 ( .A(n4262), .Y(n3976) );
AO22XLTS U4724 ( .A0(n4094), .A1(DMP_SHT1_EWSW[42]), .B0(n3976), .B1(
DMP_SHT2_EWSW[42]), .Y(n1482) );
AO22XLTS U4725 ( .A0(n3973), .A1(DMP_EXP_EWSW[43]), .B0(n3975), .B1(
DMP_SHT1_EWSW[43]), .Y(n1480) );
AO22XLTS U4726 ( .A0(n4094), .A1(DMP_SHT1_EWSW[43]), .B0(n3976), .B1(
DMP_SHT2_EWSW[43]), .Y(n1479) );
AO22XLTS U4727 ( .A0(n3973), .A1(DMP_EXP_EWSW[44]), .B0(n3975), .B1(
DMP_SHT1_EWSW[44]), .Y(n1477) );
AO22XLTS U4728 ( .A0(busy), .A1(DMP_SHT1_EWSW[44]), .B0(n3976), .B1(
DMP_SHT2_EWSW[44]), .Y(n1476) );
AO22XLTS U4729 ( .A0(n3973), .A1(DMP_EXP_EWSW[45]), .B0(n3975), .B1(
DMP_SHT1_EWSW[45]), .Y(n1474) );
AO22XLTS U4730 ( .A0(n4094), .A1(DMP_SHT1_EWSW[45]), .B0(n3976), .B1(
DMP_SHT2_EWSW[45]), .Y(n1473) );
AO22XLTS U4731 ( .A0(n3973), .A1(DMP_EXP_EWSW[46]), .B0(n3975), .B1(
DMP_SHT1_EWSW[46]), .Y(n1471) );
AO22XLTS U4732 ( .A0(n4094), .A1(DMP_SHT1_EWSW[46]), .B0(n3976), .B1(
DMP_SHT2_EWSW[46]), .Y(n1470) );
AO22XLTS U4733 ( .A0(n3974), .A1(DMP_EXP_EWSW[47]), .B0(n3975), .B1(
DMP_SHT1_EWSW[47]), .Y(n1468) );
AO22XLTS U4734 ( .A0(n4094), .A1(DMP_SHT1_EWSW[47]), .B0(n3976), .B1(
DMP_SHT2_EWSW[47]), .Y(n1467) );
AO22XLTS U4735 ( .A0(n3974), .A1(DMP_EXP_EWSW[48]), .B0(n3975), .B1(
DMP_SHT1_EWSW[48]), .Y(n1465) );
AO22XLTS U4736 ( .A0(n4094), .A1(DMP_SHT1_EWSW[48]), .B0(n3976), .B1(
DMP_SHT2_EWSW[48]), .Y(n1464) );
AO22XLTS U4737 ( .A0(n3974), .A1(DMP_EXP_EWSW[49]), .B0(n3975), .B1(
DMP_SHT1_EWSW[49]), .Y(n1462) );
INVX2TS U4738 ( .A(n4007), .Y(n3983) );
AO22XLTS U4739 ( .A0(n3983), .A1(DMP_SHT1_EWSW[49]), .B0(n3976), .B1(
DMP_SHT2_EWSW[49]), .Y(n1461) );
AO22XLTS U4740 ( .A0(n3974), .A1(DMP_EXP_EWSW[50]), .B0(n3975), .B1(
DMP_SHT1_EWSW[50]), .Y(n1459) );
AO22XLTS U4741 ( .A0(n4094), .A1(DMP_SHT1_EWSW[50]), .B0(n3976), .B1(
DMP_SHT2_EWSW[50]), .Y(n1458) );
AO22XLTS U4742 ( .A0(n3995), .A1(DMP_EXP_EWSW[51]), .B0(n3975), .B1(
DMP_SHT1_EWSW[51]), .Y(n1456) );
AO22XLTS U4743 ( .A0(n3983), .A1(DMP_SHT1_EWSW[51]), .B0(n3976), .B1(
DMP_SHT2_EWSW[51]), .Y(n1455) );
AO22XLTS U4744 ( .A0(n3995), .A1(DMP_EXP_EWSW[52]), .B0(n3981), .B1(
DMP_SHT1_EWSW[52]), .Y(n1453) );
AO22XLTS U4745 ( .A0(n3983), .A1(DMP_SHT1_EWSW[52]), .B0(n3980), .B1(
DMP_SHT2_EWSW[52]), .Y(n1452) );
INVX2TS U4746 ( .A(n3977), .Y(n3982) );
CLKBUFX2TS U4747 ( .A(n4002), .Y(n4008) );
AO22XLTS U4748 ( .A0(n3982), .A1(DMP_SHT2_EWSW[52]), .B0(n4008), .B1(
DMP_SFG[52]), .Y(n1451) );
AO22XLTS U4749 ( .A0(n1907), .A1(DMP_SFG[52]), .B0(n3978), .B1(
DMP_exp_NRM_EW[0]), .Y(n1450) );
AO22XLTS U4750 ( .A0(n3990), .A1(DMP_EXP_EWSW[53]), .B0(n3981), .B1(
DMP_SHT1_EWSW[53]), .Y(n1448) );
AO22XLTS U4751 ( .A0(n3983), .A1(DMP_SHT1_EWSW[53]), .B0(n3980), .B1(
DMP_SHT2_EWSW[53]), .Y(n1447) );
AO22XLTS U4752 ( .A0(n3982), .A1(DMP_SHT2_EWSW[53]), .B0(n3979), .B1(
DMP_SFG[53]), .Y(n1446) );
AO22XLTS U4753 ( .A0(n1907), .A1(DMP_SFG[53]), .B0(n1914), .B1(
DMP_exp_NRM_EW[1]), .Y(n1445) );
AO22XLTS U4754 ( .A0(n3995), .A1(DMP_EXP_EWSW[54]), .B0(n3981), .B1(
DMP_SHT1_EWSW[54]), .Y(n1443) );
AO22XLTS U4755 ( .A0(n3983), .A1(DMP_SHT1_EWSW[54]), .B0(n3980), .B1(
DMP_SHT2_EWSW[54]), .Y(n1442) );
AO22XLTS U4756 ( .A0(n3982), .A1(DMP_SHT2_EWSW[54]), .B0(n4008), .B1(
DMP_SFG[54]), .Y(n1441) );
AO22XLTS U4757 ( .A0(n1907), .A1(DMP_SFG[54]), .B0(n4357), .B1(
DMP_exp_NRM_EW[2]), .Y(n1440) );
AO22XLTS U4758 ( .A0(n3995), .A1(DMP_EXP_EWSW[55]), .B0(n3981), .B1(
DMP_SHT1_EWSW[55]), .Y(n1438) );
AO22XLTS U4759 ( .A0(n3983), .A1(DMP_SHT1_EWSW[55]), .B0(n3980), .B1(
DMP_SHT2_EWSW[55]), .Y(n1437) );
AO22XLTS U4760 ( .A0(n3982), .A1(DMP_SHT2_EWSW[55]), .B0(n4008), .B1(
DMP_SFG[55]), .Y(n1436) );
AO22XLTS U4761 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[55]), .B0(n4357),
.B1(DMP_exp_NRM_EW[3]), .Y(n1435) );
AO22XLTS U4762 ( .A0(n3990), .A1(DMP_EXP_EWSW[56]), .B0(n3981), .B1(
DMP_SHT1_EWSW[56]), .Y(n1433) );
AO22XLTS U4763 ( .A0(n3983), .A1(DMP_SHT1_EWSW[56]), .B0(n3980), .B1(
DMP_SHT2_EWSW[56]), .Y(n1432) );
AO22XLTS U4764 ( .A0(n3982), .A1(DMP_SHT2_EWSW[56]), .B0(n4008), .B1(
DMP_SFG[56]), .Y(n1431) );
AO22XLTS U4765 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[56]), .B0(n4357),
.B1(DMP_exp_NRM_EW[4]), .Y(n1430) );
AO22XLTS U4766 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[57]), .B0(n3981),
.B1(DMP_SHT1_EWSW[57]), .Y(n1428) );
AO22XLTS U4767 ( .A0(n3983), .A1(DMP_SHT1_EWSW[57]), .B0(n3980), .B1(
DMP_SHT2_EWSW[57]), .Y(n1427) );
AO22XLTS U4768 ( .A0(n3982), .A1(DMP_SHT2_EWSW[57]), .B0(n4008), .B1(
DMP_SFG[57]), .Y(n1426) );
AO22XLTS U4769 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[57]), .B0(n4357),
.B1(DMP_exp_NRM_EW[5]), .Y(n1425) );
AO22XLTS U4770 ( .A0(n3995), .A1(DMP_EXP_EWSW[58]), .B0(n3981), .B1(
DMP_SHT1_EWSW[58]), .Y(n1423) );
AO22XLTS U4771 ( .A0(n3983), .A1(DMP_SHT1_EWSW[58]), .B0(n3980), .B1(
DMP_SHT2_EWSW[58]), .Y(n1422) );
AO22XLTS U4772 ( .A0(n3982), .A1(DMP_SHT2_EWSW[58]), .B0(n4008), .B1(
DMP_SFG[58]), .Y(n1421) );
AO22XLTS U4773 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[58]), .B0(n4357),
.B1(DMP_exp_NRM_EW[6]), .Y(n1420) );
AO22XLTS U4774 ( .A0(n3995), .A1(DMP_EXP_EWSW[59]), .B0(n3981), .B1(
DMP_SHT1_EWSW[59]), .Y(n1418) );
AO22XLTS U4775 ( .A0(busy), .A1(DMP_SHT1_EWSW[59]), .B0(n3980), .B1(
DMP_SHT2_EWSW[59]), .Y(n1417) );
AO22XLTS U4776 ( .A0(n3982), .A1(DMP_SHT2_EWSW[59]), .B0(n4008), .B1(
DMP_SFG[59]), .Y(n1416) );
AO22XLTS U4777 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[59]), .B0(n1914),
.B1(DMP_exp_NRM_EW[7]), .Y(n1415) );
AO22XLTS U4778 ( .A0(n3990), .A1(DMP_EXP_EWSW[60]), .B0(n3981), .B1(
DMP_SHT1_EWSW[60]), .Y(n1413) );
AO22XLTS U4779 ( .A0(busy), .A1(DMP_SHT1_EWSW[60]), .B0(n4262), .B1(
DMP_SHT2_EWSW[60]), .Y(n1412) );
AO22XLTS U4780 ( .A0(n3982), .A1(DMP_SHT2_EWSW[60]), .B0(n4008), .B1(
DMP_SFG[60]), .Y(n1411) );
AO22XLTS U4781 ( .A0(n1907), .A1(DMP_SFG[60]), .B0(n1914), .B1(
DMP_exp_NRM_EW[8]), .Y(n1410) );
INVX2TS U4782 ( .A(n3988), .Y(n3984) );
AO22XLTS U4783 ( .A0(n3995), .A1(DMP_EXP_EWSW[61]), .B0(n3984), .B1(
DMP_SHT1_EWSW[61]), .Y(n1408) );
AO22XLTS U4784 ( .A0(busy), .A1(DMP_SHT1_EWSW[61]), .B0(n4262), .B1(
DMP_SHT2_EWSW[61]), .Y(n1407) );
AO22XLTS U4785 ( .A0(n3982), .A1(DMP_SHT2_EWSW[61]), .B0(n4008), .B1(
DMP_SFG[61]), .Y(n1406) );
AO22XLTS U4786 ( .A0(n1907), .A1(DMP_SFG[61]), .B0(n4357), .B1(
DMP_exp_NRM_EW[9]), .Y(n1405) );
AO22XLTS U4787 ( .A0(n3992), .A1(DMP_EXP_EWSW[62]), .B0(n3984), .B1(
DMP_SHT1_EWSW[62]), .Y(n1403) );
AO22XLTS U4788 ( .A0(n3983), .A1(DMP_SHT1_EWSW[62]), .B0(n4262), .B1(
DMP_SHT2_EWSW[62]), .Y(n1402) );
AO22XLTS U4789 ( .A0(n4009), .A1(DMP_SHT2_EWSW[62]), .B0(n4002), .B1(
DMP_SFG[62]), .Y(n1401) );
AO22XLTS U4790 ( .A0(n1907), .A1(DMP_SFG[62]), .B0(n4357), .B1(
DMP_exp_NRM_EW[10]), .Y(n1400) );
AO22XLTS U4791 ( .A0(n3992), .A1(DmP_EXP_EWSW[0]), .B0(n3984), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1397) );
AO22XLTS U4792 ( .A0(n3989), .A1(DmP_EXP_EWSW[1]), .B0(n3984), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1395) );
AO22XLTS U4793 ( .A0(n3992), .A1(DmP_EXP_EWSW[2]), .B0(n3984), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1393) );
AO22XLTS U4794 ( .A0(n3992), .A1(DmP_EXP_EWSW[3]), .B0(n3984), .B1(
DmP_mant_SHT1_SW[3]), .Y(n1391) );
AO22XLTS U4795 ( .A0(n3989), .A1(DmP_EXP_EWSW[4]), .B0(n3984), .B1(
DmP_mant_SHT1_SW[4]), .Y(n1389) );
AO22XLTS U4796 ( .A0(n3989), .A1(DmP_EXP_EWSW[5]), .B0(n3984), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1387) );
AO22XLTS U4797 ( .A0(n3985), .A1(DmP_EXP_EWSW[6]), .B0(n3984), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1385) );
AO22XLTS U4798 ( .A0(n3986), .A1(DmP_EXP_EWSW[7]), .B0(n3984), .B1(
DmP_mant_SHT1_SW[7]), .Y(n1383) );
AO22XLTS U4799 ( .A0(n3987), .A1(DmP_EXP_EWSW[8]), .B0(n4095), .B1(
DmP_mant_SHT1_SW[8]), .Y(n1381) );
AO22XLTS U4800 ( .A0(n3985), .A1(DmP_EXP_EWSW[9]), .B0(n4095), .B1(
DmP_mant_SHT1_SW[9]), .Y(n1379) );
AO22XLTS U4801 ( .A0(n3986), .A1(DmP_EXP_EWSW[10]), .B0(n4095), .B1(
DmP_mant_SHT1_SW[10]), .Y(n1377) );
AO22XLTS U4802 ( .A0(n3987), .A1(DmP_EXP_EWSW[11]), .B0(n4095), .B1(
DmP_mant_SHT1_SW[11]), .Y(n1375) );
AO22XLTS U4803 ( .A0(n3987), .A1(DmP_EXP_EWSW[12]), .B0(n4095), .B1(
DmP_mant_SHT1_SW[12]), .Y(n1373) );
AO22XLTS U4804 ( .A0(n3988), .A1(DmP_EXP_EWSW[13]), .B0(n4095), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1371) );
AO22XLTS U4805 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[14]), .B0(n4095),
.B1(DmP_mant_SHT1_SW[14]), .Y(n1369) );
AO22XLTS U4806 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[15]), .B0(n4095),
.B1(DmP_mant_SHT1_SW[15]), .Y(n1367) );
AO22XLTS U4807 ( .A0(n3992), .A1(DmP_EXP_EWSW[16]), .B0(n4095), .B1(
DmP_mant_SHT1_SW[16]), .Y(n1365) );
AO22XLTS U4808 ( .A0(n3989), .A1(DmP_EXP_EWSW[17]), .B0(n4095), .B1(
DmP_mant_SHT1_SW[17]), .Y(n1363) );
INVX2TS U4809 ( .A(n3990), .Y(n3991) );
AO22XLTS U4810 ( .A0(n4003), .A1(DmP_EXP_EWSW[18]), .B0(n3991), .B1(
DmP_mant_SHT1_SW[18]), .Y(n1361) );
AO22XLTS U4811 ( .A0(n4003), .A1(DmP_EXP_EWSW[19]), .B0(n3991), .B1(
DmP_mant_SHT1_SW[19]), .Y(n1359) );
AO22XLTS U4812 ( .A0(n4003), .A1(DmP_EXP_EWSW[20]), .B0(n3991), .B1(
DmP_mant_SHT1_SW[20]), .Y(n1357) );
AO22XLTS U4813 ( .A0(n4003), .A1(DmP_EXP_EWSW[21]), .B0(n3991), .B1(
DmP_mant_SHT1_SW[21]), .Y(n1355) );
AO22XLTS U4814 ( .A0(n3992), .A1(DmP_EXP_EWSW[25]), .B0(n3991), .B1(
DmP_mant_SHT1_SW[25]), .Y(n1347) );
AO22XLTS U4815 ( .A0(n3992), .A1(DmP_EXP_EWSW[26]), .B0(n3991), .B1(
DmP_mant_SHT1_SW[26]), .Y(n1345) );
CLKBUFX2TS U4816 ( .A(Shift_reg_FLAGS_7_5), .Y(n3993) );
AO22XLTS U4817 ( .A0(n3993), .A1(DmP_EXP_EWSW[27]), .B0(n3991), .B1(
DmP_mant_SHT1_SW[27]), .Y(n1343) );
AO22XLTS U4818 ( .A0(n3993), .A1(DmP_EXP_EWSW[28]), .B0(n3991), .B1(
DmP_mant_SHT1_SW[28]), .Y(n1341) );
AO22XLTS U4819 ( .A0(n3993), .A1(DmP_EXP_EWSW[29]), .B0(n3991), .B1(
DmP_mant_SHT1_SW[29]), .Y(n1339) );
AO22XLTS U4820 ( .A0(n3993), .A1(DmP_EXP_EWSW[30]), .B0(n3991), .B1(
DmP_mant_SHT1_SW[30]), .Y(n1337) );
INVX2TS U4821 ( .A(n3992), .Y(n3994) );
AO22XLTS U4822 ( .A0(n3993), .A1(DmP_EXP_EWSW[31]), .B0(n3994), .B1(
DmP_mant_SHT1_SW[31]), .Y(n1335) );
AO22XLTS U4823 ( .A0(n3993), .A1(DmP_EXP_EWSW[32]), .B0(n3994), .B1(
DmP_mant_SHT1_SW[32]), .Y(n1333) );
AO22XLTS U4824 ( .A0(n3993), .A1(DmP_EXP_EWSW[33]), .B0(n3994), .B1(
DmP_mant_SHT1_SW[33]), .Y(n1331) );
AO22XLTS U4825 ( .A0(n3993), .A1(DmP_EXP_EWSW[34]), .B0(n3994), .B1(
DmP_mant_SHT1_SW[34]), .Y(n1329) );
AO22XLTS U4826 ( .A0(n3993), .A1(DmP_EXP_EWSW[35]), .B0(n3994), .B1(
DmP_mant_SHT1_SW[35]), .Y(n1327) );
AO22XLTS U4827 ( .A0(n3993), .A1(DmP_EXP_EWSW[36]), .B0(n3994), .B1(
DmP_mant_SHT1_SW[36]), .Y(n1325) );
CLKBUFX2TS U4828 ( .A(Shift_reg_FLAGS_7_5), .Y(n3996) );
AO22XLTS U4829 ( .A0(n3996), .A1(DmP_EXP_EWSW[37]), .B0(n3994), .B1(
DmP_mant_SHT1_SW[37]), .Y(n1323) );
AO22XLTS U4830 ( .A0(n3996), .A1(DmP_EXP_EWSW[38]), .B0(n3994), .B1(
DmP_mant_SHT1_SW[38]), .Y(n1321) );
AO22XLTS U4831 ( .A0(n3996), .A1(DmP_EXP_EWSW[39]), .B0(n3994), .B1(
DmP_mant_SHT1_SW[39]), .Y(n1319) );
AO22XLTS U4832 ( .A0(n3996), .A1(DmP_EXP_EWSW[40]), .B0(n3994), .B1(
DmP_mant_SHT1_SW[40]), .Y(n1317) );
INVX2TS U4833 ( .A(n3995), .Y(n4001) );
AO22XLTS U4834 ( .A0(n3996), .A1(DmP_EXP_EWSW[41]), .B0(n4001), .B1(
DmP_mant_SHT1_SW[41]), .Y(n1315) );
AO22XLTS U4835 ( .A0(n3996), .A1(DmP_EXP_EWSW[42]), .B0(n4001), .B1(
DmP_mant_SHT1_SW[42]), .Y(n1313) );
AO22XLTS U4836 ( .A0(n3996), .A1(DmP_EXP_EWSW[43]), .B0(n4001), .B1(
DmP_mant_SHT1_SW[43]), .Y(n1311) );
AO22XLTS U4837 ( .A0(n3996), .A1(DmP_EXP_EWSW[44]), .B0(n4001), .B1(
DmP_mant_SHT1_SW[44]), .Y(n1309) );
AO22XLTS U4838 ( .A0(n3996), .A1(DmP_EXP_EWSW[45]), .B0(n4001), .B1(
DmP_mant_SHT1_SW[45]), .Y(n1307) );
AO22XLTS U4839 ( .A0(n3996), .A1(DmP_EXP_EWSW[46]), .B0(n4001), .B1(
DmP_mant_SHT1_SW[46]), .Y(n1305) );
AO22XLTS U4840 ( .A0(n4006), .A1(DmP_EXP_EWSW[47]), .B0(n4001), .B1(
DmP_mant_SHT1_SW[47]), .Y(n1303) );
AO22XLTS U4841 ( .A0(n4006), .A1(DmP_EXP_EWSW[48]), .B0(n4001), .B1(
DmP_mant_SHT1_SW[48]), .Y(n1301) );
AO22XLTS U4842 ( .A0(n4006), .A1(DmP_EXP_EWSW[49]), .B0(n4001), .B1(
DmP_mant_SHT1_SW[49]), .Y(n1299) );
OAI222X1TS U4843 ( .A0(n3997), .A1(n4244), .B0(n4226), .B1(
Shift_reg_FLAGS_7_6), .C0(n4054), .C1(n3999), .Y(n1293) );
OAI222X1TS U4844 ( .A0(n3998), .A1(n4096), .B0(n4212), .B1(
Shift_reg_FLAGS_7_6), .C0(n4080), .C1(n3999), .Y(n1292) );
OAI222X1TS U4845 ( .A0(n3998), .A1(n4245), .B0(n4247), .B1(
Shift_reg_FLAGS_7_6), .C0(n4063), .C1(n3999), .Y(n1291) );
OAI222X1TS U4846 ( .A0(n4000), .A1(n4097), .B0(n4243), .B1(n1916), .C0(n4055), .C1(n3999), .Y(n1290) );
OA21XLTS U4847 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n4012),
.Y(n1287) );
AO22XLTS U4848 ( .A0(n4006), .A1(ZERO_FLAG_EXP), .B0(n4001), .B1(
ZERO_FLAG_SHT1), .Y(n1286) );
AO22XLTS U4849 ( .A0(busy), .A1(ZERO_FLAG_SHT1), .B0(n4007), .B1(
ZERO_FLAG_SHT2), .Y(n1285) );
AO22XLTS U4850 ( .A0(n4009), .A1(ZERO_FLAG_SHT2), .B0(n4002), .B1(
ZERO_FLAG_SFG), .Y(n1284) );
AO22XLTS U4851 ( .A0(n1907), .A1(ZERO_FLAG_SFG), .B0(n4357), .B1(
ZERO_FLAG_NRM), .Y(n1283) );
AO22XLTS U4852 ( .A0(n1920), .A1(ZERO_FLAG_NRM), .B0(n1919), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n1282) );
AO22XLTS U4853 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n4011), .B1(zero_flag), .Y(n1281) );
AO22XLTS U4854 ( .A0(n4006), .A1(OP_FLAG_EXP), .B0(n4004), .B1(OP_FLAG_SHT1),
.Y(n1280) );
AO22XLTS U4855 ( .A0(busy), .A1(OP_FLAG_SHT1), .B0(n4007), .B1(OP_FLAG_SHT2),
.Y(n1279) );
AO22XLTS U4856 ( .A0(n4006), .A1(SIGN_FLAG_EXP), .B0(n4005), .B1(
SIGN_FLAG_SHT1), .Y(n1275) );
AO22XLTS U4857 ( .A0(busy), .A1(SIGN_FLAG_SHT1), .B0(n4007), .B1(
SIGN_FLAG_SHT2), .Y(n1274) );
AO22XLTS U4858 ( .A0(n4009), .A1(SIGN_FLAG_SHT2), .B0(n4008), .B1(
SIGN_FLAG_SFG), .Y(n1273) );
AO22XLTS U4859 ( .A0(n1907), .A1(SIGN_FLAG_SFG), .B0(n4357), .B1(
SIGN_FLAG_NRM), .Y(n1272) );
AO22XLTS U4860 ( .A0(n1920), .A1(SIGN_FLAG_NRM), .B0(n1919), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n1271) );
NOR2XLTS U4861 ( .A(n4010), .B(SIGN_FLAG_SHT1SHT2), .Y(n4013) );
OAI2BB2XLTS U4862 ( .B0(n4013), .B1(n4012), .A0N(final_result_ieee[63]),
.A1N(n4011), .Y(n1270) );
INVX2TS U4863 ( .A(n4028), .Y(n4039) );
CLKBUFX2TS U4864 ( .A(n4358), .Y(n4042) );
INVX2TS U4865 ( .A(n4028), .Y(n4026) );
CLKBUFX2TS U4866 ( .A(n1901), .Y(n4035) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_syn.sdf");
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`define sb200
//************************************************************************
//************************************************************************
//** This model is the property of Cypress Semiconductor Corp and is **
//** protected by the US copyright laws, any unauthorized copying and **
//** distribution is prohibited. Cypress reserves the right to change **
//** any of the functional specifications without any prior notice. **
//** Cypress is not liable for any damages which may result from the **
//** use of this functional model. **
//** **
//** File Name : CY7C1356 **
//** **
//** Revision : 1.0 - 08/03/2004 **
//** **
//** The timings are to be selected by the user depending upon the **
//** frequency of operation from the datasheet. **
//** **
//** Model : CY7C1356C - NoBL Pipelined SRAM **
//** Queries : MPD Applications **
//** Website: www.cypress.com/support **
//************************************************************************
//************************************************************************
`timescale 1ns / 10ps
// NOTE : Any setup/hold errors will force input signal to x state
// or if results indeterminant (write addr) core is reset x
// define fixed values
`define wordsize (18 -1) //
`define no_words (1048576 -1) // 1M x 18 RAM
module cy1356 ( d, clk, a, bws, we_b, adv_lb, ce1b, ce2, ce3b, oeb, cenb, mode);
inout [`wordsize:0] d;
input clk, // clock input (R)
we_b, // byte write enable(L)
adv_lb, // burst(H)/load(L) address
ce1b, // chip enable(L)
ce2, // chip enable(H)
ce3b, // chip enable(L)
oeb, // async output enable(L)(read)
cenb, // clock enable(L)
mode; // interleave(H)/linear(L) burst
input [1:0] bws; // byte write select(L)
input [18:0] a; // address bus
// *** NOTE DEVICE OPERATES #0.01 AFTER CLOCK ***
// *** THEREFORE DELAYS HAVE TO TAKE THIS INTO ACCOUNT ***
//**********************************************************************
// Timings for 225MHz
//**********************************************************************
`ifdef sb225
`define teohz #2.8
`define teolz #0
`define tchz #2.8
`define tclz #1.25
`define tco #2.8
`define tdoh #1.25
`define tas 1.4
`define tah 0.4
`endif
//***********************************************************************
// Timings for 200MHz
//**********************************************************************
`ifdef sb200
`define teohz #3.2
`define teolz #0
`define tchz #3.2
`define tclz #1.5
`define tco #3.2
`define tdoh #1.5
`define tas 1.5
`define tah 0.5
`endif
//***********************************************************************
//**********************************************************************
// This model is configured for 166 MHz Operation (CY7C1356-166).
//**********************************************************************
`ifdef sb166
`define teohz #3.5
`define teolz #0
`define tchz #3.5
`define tclz #1.5
`define tco #3.5
`define tdoh #1.5
`define tas 1.5
`define tah 0.5
`endif
reg notifier; // error support reg's
reg noti1_0;
reg noti1_1;
reg noti1_2;
reg noti1_3;
reg noti1_4;
reg noti1_5;
reg noti1_6;
reg noti2;
wire chipen; // combined chip enable (high for an active chip)
reg chipen_d; // _d = delayed
reg chipen_o; // _o = operational = delayed sig or _d sig
wire writestate; // holds 1 if any of writebus is low
reg writestate_d;
reg writestate_o;
wire loadcyc; // holds 1 for load cycles (setup and hold checks)
wire writecyc; // holds 1 for write cycles (setup and hold checks)
wire [1:0] bws; // holds the bws values
wire [1:0] writebusb; // holds the "internal" bws bus based on we_b
reg [1:0] writebusb_d;
reg [1:0] writebusb_o;
wire [2:0] operation; // holds chipen, adv_ld and writestate
reg [2:0] operation_d;
reg [2:0] operation_o;
wire [18:0] a; // address input bus
reg [18:0] a_d;
reg [18:0] a_o;
reg [`wordsize:0] do; // data output reg
reg [`wordsize:0] di; // data input bus
reg [`wordsize:0] dd; // data delayed bus
wire tristate; // tristate output (on a bytewise basis) when asserted
reg cetri; // register set by chip disable which sets the tristate
reg oetri; // register set by oe which sets the tristate
reg enable; // register to make the ram enabled when equal to 1
reg [18:0] addreg; // register to hold the input address
reg [`wordsize:0] pipereg; // register for the output data
reg [`wordsize:0] mem [0:`no_words]; // RAM array
reg [`wordsize:0] writeword; // temporary holding register for the write data
reg burstinit; // register to hold a[0] for burst type
reg [18:0] i; // temporary register used to write to all mem locs.
reg writetri; // tristate
reg lw, bw; // pipelined write functions
reg we_bl;
wire [`wordsize:0] d = !tristate ? do[`wordsize:0] : 18'bz ; // data bus
assign chipen = (adv_lb == 1 ) ? chipen_d :
~ce1b & ce2 & ~ce3b ;
assign writestate = ~& writebusb;
assign operation = {chipen, adv_lb, writestate};
assign writebusb[1:0] = ( we_b ==0 & adv_lb ==0) ? bws[1:0]:
( we_b ==1 & adv_lb ==0) ? 2'b11 :
( we_bl ==0 & adv_lb ==1) ? bws[1:0]:
( we_bl ==1 & adv_lb ==1) ? 2'b11 :
2'bxx ;
assign loadcyc = chipen & !cenb;
assign writecyc = writestate_d & enable & ~cenb & chipen; // check
assign tristate = cetri | writetri | oetri;
pullup (mode);
// formers for notices/errors etc
//
//$display("NOTICE : xxx :");
//$display("WARNING : xxx :");
//$display("ERROR *** : xxx :");
// initialize the output to be tri-state, ram to be disabled
initial
begin
// signals
writetri = 0;
cetri = 1;
enable = 0;
lw = 0;
bw = 0;
// error signals
notifier = 0;
noti1_0 = 0;
noti1_1 = 0;
noti1_2 = 0;
noti1_3 = 0;
noti1_4 = 0;
noti1_5 = 0;
noti1_6 = 0;
noti2 = 0;
end
// asynchronous OE
always @(oeb)
begin
if (oeb == 1)
oetri <= `teohz 1;
else
oetri <= `teolz 0;
end
// *** SETUP / HOLD VIOLATIONS ***
always @(noti2)
begin
$display("NOTICE : 020 : Data bus corruption");
force d =18'bx;
#1;
release d;
end
always @(noti1_0)
begin
$display("NOTICE : 010 : Byte write corruption");
force bws = 2'bx;
#1;
release bws;
end
always @(noti1_1)
begin
$display("NOTICE : 011 : Byte enable corruption");
force we_b = 1'bx;
#1;
release we_b;
end
always @(noti1_2)
begin
$display("NOTICE : 012 : CE1B corruption");
force ce1b =1'bx;
#1;
release ce1b;
end
always @(noti1_3)
begin
$display("NOTICE : 013 : CE2 corruption");
force ce2 =1'bx;
#1;
release ce2;
end
always @(noti1_4)
begin
$display("NOTICE : 014 : CE3B corruption");
force ce3b =1'bx;
#1;
release ce3b;
end
always @(noti1_5)
begin
$display("NOTICE : 015 : CENB corruption");
force cenb =1'bx;
#1;
release cenb;
end
always @(noti1_6)
begin
$display("NOTICE : 016 : ADV_LB corruption");
force adv_lb = 1'bx;
#1;
release adv_lb;
end
// synchronous functions from clk edge
always @(posedge clk)
if (!cenb)
begin
#0.01;
// latch conditions on adv_lb
if (adv_lb)
we_bl <= we_bl;
else
we_bl <= we_b;
chipen_d <= chipen;
chipen_o <= chipen;
writestate_o <= writestate;
writestate_d <= writestate_o;
writebusb_o <= writebusb;
writebusb_d <= writebusb_o;
operation_o <= operation;
a_o <= a;
a_d <= a_o;
di = d;
// execute previously pipelined fns
if (lw) begin
loadwrite;
lw =0;
end
if (bw) begin
burstwrite;
bw =0;
end
// decode input/piplined state
casex (operation_o)
3'b0?? : turnoff;
3'b101 : setlw;
3'b111 : setbw;
3'b100 : loadread;
3'b110 : burstread;
default : unknown; // output unknown values and display an error message
endcase
do <= `tco pipereg;
end
// *** task section ***
task read;
begin
if (enable) cetri <= `tclz 0;
writetri <= `tchz 0;
do <= `tdoh 18'hx;
pipereg = mem[addreg];
end
endtask
task write;
begin
if (enable) cetri <= `tclz 0;
writeword = mem[addreg]; // set up a word to hold the data for the current location
/* overwrite the current word for the bytes being written to */
if (!writebusb_d[1]) writeword[17:9] = di[17:9];
if (!writebusb_d[0]) writeword[8:0] = di[8:0];
writeword = writeword & writeword; //convert z to x states
mem[addreg] = writeword; // store the new word into the memory location
//writetri <= `tchz 1; // tristate the outputs
end
endtask
task setlw;
begin
lw =1;
writetri <= `tchz 1; // tristate the outputs
end
endtask
task setbw;
begin
bw =1;
writetri <= `tchz 1; // tristate the outputs
end
endtask
task loadread;
begin
burstinit = a_o[0];
addreg = a_o;
enable = 1;
read;
end
endtask
task loadwrite;
begin
burstinit = a_d[0];
addreg = a_d;
enable = 1;
write;
end
endtask
task burstread;
begin
burst;
read;
end
endtask
task burstwrite;
begin
burst;
write;
end
endtask
task unknown;
begin
do = 18'bx;
// $display ("Unknown function: Operation = %b\n", operation);
end
endtask
task turnoff;
begin
enable = 0;
cetri <= `tchz 1;
pipereg = 18'h0;
end
endtask
task burst;
begin
if (burstinit == 0 || mode == 0)
begin
case (addreg[1:0])
2'b00: addreg[1:0] = 2'b01;
2'b01: addreg[1:0] = 2'b10;
2'b10: addreg[1:0] = 2'b11;
2'b11: addreg[1:0] = 2'b00;
default: addreg[1:0] = 2'bxx;
endcase
end
else
begin
case (addreg[1:0])
2'b00: addreg[1:0] = 2'b11;
2'b01: addreg[1:0] = 2'b00;
2'b10: addreg[1:0] = 2'b01;
2'b11: addreg[1:0] = 2'b10;
default: addreg[1:0] = 2'bxx;
endcase
end
end
endtask
// IO checks
specify
// specify the setup and hold checks
// notifier will wipe memory as result is indeterminent
$setuphold(posedge clk &&& loadcyc, a, `tas, `tah, notifier);
// noti1 should make ip = 'bx;
$setuphold(posedge clk, bws, `tas, `tah, noti1_0);
$setuphold(posedge clk, we_b, `tas, `tah, noti1_1);
$setuphold(posedge clk, ce1b, `tas, `tah, noti1_2);
$setuphold(posedge clk, ce2, `tas, `tah, noti1_3);
$setuphold(posedge clk, ce3b, `tas, `tah, noti1_4);
// noti2 should make d = 18'hxxxxx;
$setuphold(posedge clk &&& writecyc, d, `tas, `tah, noti2);
// add extra tests here.
$setuphold(posedge clk, cenb, `tas, `tah, noti1_5);
$setuphold(posedge clk, adv_lb, `tas, `tah, noti1_6);
endspecify
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BA_FUNCTIONAL_V
`define SKY130_FD_SC_HS__O21BA_FUNCTIONAL_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o21ba (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire nor0_out ;
wire nor1_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X , B1_N, nor0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, nor1_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BA_FUNCTIONAL_V |
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream 4 port arbitrated multiplexer (64 bit datapath)
*/
module axis_arb_mux_64_4 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
)
(
input wire clk,
input wire rst,
/*
* AXI inputs
*/
input wire [DATA_WIDTH-1:0] input_0_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_0_axis_tkeep,
input wire input_0_axis_tvalid,
output wire input_0_axis_tready,
input wire input_0_axis_tlast,
input wire input_0_axis_tuser,
input wire [DATA_WIDTH-1:0] input_1_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_1_axis_tkeep,
input wire input_1_axis_tvalid,
output wire input_1_axis_tready,
input wire input_1_axis_tlast,
input wire input_1_axis_tuser,
input wire [DATA_WIDTH-1:0] input_2_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_2_axis_tkeep,
input wire input_2_axis_tvalid,
output wire input_2_axis_tready,
input wire input_2_axis_tlast,
input wire input_2_axis_tuser,
input wire [DATA_WIDTH-1:0] input_3_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_3_axis_tkeep,
input wire input_3_axis_tvalid,
output wire input_3_axis_tready,
input wire input_3_axis_tlast,
input wire input_3_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
);
wire [3:0] request;
wire [3:0] acknowledge;
wire [3:0] grant;
wire grant_valid;
wire [1:0] grant_encoded;
assign acknowledge[0] = input_0_axis_tvalid & input_0_axis_tready & input_0_axis_tlast;
assign request[0] = input_0_axis_tvalid & ~acknowledge[0];
assign acknowledge[1] = input_1_axis_tvalid & input_1_axis_tready & input_1_axis_tlast;
assign request[1] = input_1_axis_tvalid & ~acknowledge[1];
assign acknowledge[2] = input_2_axis_tvalid & input_2_axis_tready & input_2_axis_tlast;
assign request[2] = input_2_axis_tvalid & ~acknowledge[2];
assign acknowledge[3] = input_3_axis_tvalid & input_3_axis_tready & input_3_axis_tlast;
assign request[3] = input_3_axis_tvalid & ~acknowledge[3];
// mux instance
axis_mux_64_4 #(
.DATA_WIDTH(DATA_WIDTH)
)
mux_inst (
.clk(clk),
.rst(rst),
.input_0_axis_tdata(input_0_axis_tdata),
.input_0_axis_tkeep(input_0_axis_tkeep),
.input_0_axis_tvalid(input_0_axis_tvalid & grant[0]),
.input_0_axis_tready(input_0_axis_tready),
.input_0_axis_tlast(input_0_axis_tlast),
.input_0_axis_tuser(input_0_axis_tuser),
.input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tkeep(input_1_axis_tkeep),
.input_1_axis_tvalid(input_1_axis_tvalid & grant[1]),
.input_1_axis_tready(input_1_axis_tready),
.input_1_axis_tlast(input_1_axis_tlast),
.input_1_axis_tuser(input_1_axis_tuser),
.input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tkeep(input_2_axis_tkeep),
.input_2_axis_tvalid(input_2_axis_tvalid & grant[2]),
.input_2_axis_tready(input_2_axis_tready),
.input_2_axis_tlast(input_2_axis_tlast),
.input_2_axis_tuser(input_2_axis_tuser),
.input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tkeep(input_3_axis_tkeep),
.input_3_axis_tvalid(input_3_axis_tvalid & grant[3]),
.input_3_axis_tready(input_3_axis_tready),
.input_3_axis_tlast(input_3_axis_tlast),
.input_3_axis_tuser(input_3_axis_tuser),
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
.enable(grant_valid),
.select(grant_encoded)
);
// arbiter instance
arbiter #(
.PORTS(4),
.TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
)
arb_inst (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
endmodule
|
//======================================================================
//
// blake2.v
// --------
// Top level wrapper for the blake2 hash function core providing
// a simple memory like interface with 32 bit data access.
//
//
// Author: Joachim Strömbergson
// Copyright (c) 2014, Secworks Sweden AB
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`include "blake2_core.v"
module blake2(
// Clock and reset.
input wire clk,
input wire reset_n,
// Control.
input wire cs,
input wire we,
// Data ports.
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter ADDR_CTRL = 8'h00;
parameter CTRL_INIT_BIT = 0;
parameter CTRL_NEXT_BIT = 1;
parameter ADDR_STATUS = 8'h01;
parameter STATUS_READY_BIT = 0;
parameter ADDR_BLOCK_W00 = 8'h10;
parameter ADDR_BLOCK_W31 = 8'h2f;
parameter ADDR_DIGEST00 = 8'h80;
parameter ADDR_DIGEST15 = 8'h8f;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg init_reg;
reg next_reg;
reg ctrl_we;
reg ready_reg;
reg digest_valid_reg;
reg [31 : 0] block_mem [0 : 31];
reg block_mem_we;
reg [31 : 0] digest_mem [0 : 16];
reg digest_mem_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire core_init;
wire core_next;
wire core_ready;
wire [1023 : 0] core_block;
wire [511 : 0] core_digest;
wire core_digest_valid;
reg [31 : 0] tmp_read_data;
reg tmp_error;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign core_init = init_reg;
assign core_next = next_reg;
assign core_block = {block_mem[00], block_mem[01], block_mem[02], block_mem[03],
block_mem[04], block_mem[05], block_mem[06], block_mem[07],
block_mem[08], block_mem[09], block_mem[10], block_mem[11],
block_mem[12], block_mem[13], block_mem[14], block_mem[15],
block_mem[16], block_mem[17], block_mem[18], block_mem[19],
block_mem[20], block_mem[21], block_mem[22], block_mem[23],
block_mem[24], block_mem[25], block_mem[26], block_mem[27],
block_mem[28], block_mem[29], block_mem[30], block_mem[31]};
assign read_data = tmp_read_data;
assign error = tmp_error;
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
blake2_core core (
.clk(clk),
.reset_n(reset_n),
.init(core_init),
.next(core_next),
.block(core_block),
.ready(core_ready),
.digest(core_digest),
.digest_valid(core_digest_valid)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
reg [6 : 0] i;
if (!reset_n)
begin
init_reg <= 0;
next_reg <= 0;
ready_reg <= 0;
digest_valid_reg <= 0;
for (i = 0 ; i < 32 ; i = i + 1)
begin
block_mem[i] <= 32'h00000000;
end
for (i = 0 ; i < 16 ; i = i + 1)
begin
digest_mem[i] <= 32'h00000000;
end
end
else
begin
ready_reg <= core_ready;
digest_valid_reg <= core_digest_valid;
if (ctrl_we)
begin
init_reg <= write_data[CTRL_INIT_BIT];
next_reg <= write_data[CTRL_NEXT_BIT];
end
if (block_mem_we)
begin
block_mem[address[4 : 0]] <= write_data;
end
end
end // reg_update
//----------------------------------------------------------------
// Address decoder logic.
//----------------------------------------------------------------
always @*
begin : addr_decoder
block_mem_we = 0;
digest_mem_we = 0;
tmp_read_data = 32'h00000000;
tmp_error = 0;
if (cs)
begin
if (we)
begin
if ((address >= ADDR_BLOCK_W00) && (address <= ADDR_BLOCK_W31))
begin
block_mem_we = 1;
end
case (address)
ADDR_CTRL:
begin
ctrl_we = 1;
end
endcase // case (address)
end // if (we)
else
begin
case (address)
ADDR_CTRL:
begin
tmp_read_data = {28'h0000000, 2'b00, next_reg, init_reg};
end
ADDR_STATUS:
begin
tmp_read_data = {28'h0000000, 2'b00,
{digest_valid_reg, ready_reg}};
end
default:
begin
tmp_error = 1;
end
endcase // case (address)
end
end
end // addr_decoder
endmodule // blake2
//======================================================================
// EOF blake2.v
//======================================================================
|
// Filename: receive.v
// Author: Danny Dutton
// Date: 03/23/15
// Version: 1
// Description: Module that receives a 10-bit bus which is fed into a register.
// This data is also fed into a 9-bit parity generator. The ODD ouput
// is compared to the 10th data bit which is an even parity bit.
module receive(clk, data_in, data_out, data_valid);
input clk; // Clock to be generated in test bench with clk module
input[9:0] data_in; // Data coming from transmit, into reg and parity gen
output[8:0] data_out; // 9-bit bus coming out of reg
output data_valid; // Output of comparator
wire[8:0] data_out;
wire data_valid;
wire odd_in; // Even parity bit going to comparator
wire odd, even; // Outputs of parity generator
// 10-bit register
// Input from transmit module, output goes to output, parity gen, and comparator
register_10bit U4(clk, data_in, {odd_in, data_out});
// 9-bit parity generator
// Input from data_out, output to comparator
hc280 U5(data_out, even, odd);
// Parity bit comparator (XNOR gate). Since the hc280 outputs high on odd when
// there is an odd number of 1s in its input, this odd output is used as an even
// parity bit (odd number of 1s plus another 1 = even number of ones). So XNOR is
// used to check if there is either an odd number of ones and a high even parity
// bit or an even number of ones and a low even parity bit.
xnor U6(data_valid, odd, odd_in);
endmodule |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 18Kb FIFO (First-In-First-Out) Block RAM Memory
// /___/ /\ Filename : FIFO18E2.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 11/30/2012 - intial
// 12/12/2012 - yaml update, 691724 and 691715
// 02/07/2013 - 699628 - correction to DO_PIPELINED mode
// 02/28/2013 - update to keep in sync with RAMB models
// 03/18/2013 - 707083 reads should clear FULL when RD & WR in CDC.
// 03/22/2013 - sync5 yaml update, port ordering, *RSTBUSY
// 03/25/2013 - 707652 - RST = 1 n enters RST sequence but does not hold it there.
// 03/25/2013 - 707719 - Add sync5 cascade feature
// 03/27/2013 - 708820 - FULL flag deassert during WREN ind clocks.
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module FIFO18E2 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter CASCADE_ORDER = "NONE",
parameter CLOCK_DOMAINS = "INDEPENDENT",
parameter FIRST_WORD_FALL_THROUGH = "FALSE",
parameter [35:0] INIT = 36'h000000000,
parameter [0:0] IS_RDCLK_INVERTED = 1'b0,
parameter [0:0] IS_RDEN_INVERTED = 1'b0,
parameter [0:0] IS_RSTREG_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter [0:0] IS_WRCLK_INVERTED = 1'b0,
parameter [0:0] IS_WREN_INVERTED = 1'b0,
parameter integer PROG_EMPTY_THRESH = 256,
parameter integer PROG_FULL_THRESH = 256,
parameter RDCOUNT_TYPE = "RAW_PNTR",
parameter integer READ_WIDTH = 4,
parameter REGISTER_MODE = "UNREGISTERED",
parameter RSTREG_PRIORITY = "RSTREG",
parameter SLEEP_ASYNC = "FALSE",
parameter [35:0] SRVAL = 36'h000000000,
parameter WRCOUNT_TYPE = "RAW_PNTR",
parameter integer WRITE_WIDTH = 4
)(
output [31:0] CASDOUT,
output [3:0] CASDOUTP,
output CASNXTEMPTY,
output CASPRVRDEN,
output [31:0] DOUT,
output [3:0] DOUTP,
output EMPTY,
output FULL,
output PROGEMPTY,
output PROGFULL,
output [12:0] RDCOUNT,
output RDERR,
output RDRSTBUSY,
output [12:0] WRCOUNT,
output WRERR,
output WRRSTBUSY,
input [31:0] CASDIN,
input [3:0] CASDINP,
input CASDOMUX,
input CASDOMUXEN,
input CASNXTRDEN,
input CASOREGIMUX,
input CASOREGIMUXEN,
input CASPRVEMPTY,
input [31:0] DIN,
input [3:0] DINP,
input RDCLK,
input RDEN,
input REGCE,
input RST,
input RSTREG,
input SLEEP,
input WRCLK,
input WREN
);
// define constants
localparam MODULE_NAME = "FIFO18E2";
// Parameter encodings and registers
localparam CASCADE_ORDER_FIRST = 1;
localparam CASCADE_ORDER_LAST = 2;
localparam CASCADE_ORDER_MIDDLE = 3;
localparam CASCADE_ORDER_NONE = 0;
localparam CASCADE_ORDER_PARALLEL = 4;
localparam CLOCK_DOMAINS_COMMON = 1;
localparam CLOCK_DOMAINS_INDEPENDENT = 0;
localparam FIRST_WORD_FALL_THROUGH_FALSE = 0;
localparam FIRST_WORD_FALL_THROUGH_TRUE = 1;
localparam RDCOUNT_TYPE_EXTENDED_DATACOUNT = 1;
localparam RDCOUNT_TYPE_RAW_PNTR = 0;
localparam RDCOUNT_TYPE_SIMPLE_DATACOUNT = 2;
localparam RDCOUNT_TYPE_SYNC_PNTR = 3;
localparam READ_WIDTH_18 = 16;
localparam READ_WIDTH_36 = 32;
localparam READ_WIDTH_4 = 4;
localparam READ_WIDTH_9 = 8;
localparam REGISTER_MODE_DO_PIPELINED = 1;
localparam REGISTER_MODE_REGISTERED = 2;
localparam REGISTER_MODE_UNREGISTERED = 0;
localparam RSTREG_PRIORITY_REGCE = 1;
localparam RSTREG_PRIORITY_RSTREG = 0;
localparam SLEEP_ASYNC_FALSE = 0;
localparam SLEEP_ASYNC_TRUE = 1;
localparam WRCOUNT_TYPE_EXTENDED_DATACOUNT = 1;
localparam WRCOUNT_TYPE_RAW_PNTR = 0;
localparam WRCOUNT_TYPE_SIMPLE_DATACOUNT = 2;
localparam WRCOUNT_TYPE_SYNC_PNTR = 3;
localparam WRITE_WIDTH_18 = 16;
localparam WRITE_WIDTH_36 = 32;
localparam WRITE_WIDTH_4 = 4;
localparam WRITE_WIDTH_9 = 8;
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
`ifdef XIL_DR
`include "FIFO18E2_dr.v"
`else
localparam [64:1] CASCADE_ORDER_REG = CASCADE_ORDER;
localparam [88:1] CLOCK_DOMAINS_REG = CLOCK_DOMAINS;
localparam [40:1] FIRST_WORD_FALL_THROUGH_REG = FIRST_WORD_FALL_THROUGH;
localparam [35:0] INIT_REG = INIT;
localparam [0:0] IS_RDCLK_INVERTED_REG = IS_RDCLK_INVERTED;
localparam [0:0] IS_RDEN_INVERTED_REG = IS_RDEN_INVERTED;
localparam [0:0] IS_RSTREG_INVERTED_REG = IS_RSTREG_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
localparam [0:0] IS_WRCLK_INVERTED_REG = IS_WRCLK_INVERTED;
localparam [0:0] IS_WREN_INVERTED_REG = IS_WREN_INVERTED;
localparam [12:0] PROG_EMPTY_THRESH_REG = PROG_EMPTY_THRESH;
localparam [12:0] PROG_FULL_THRESH_REG = PROG_FULL_THRESH;
localparam [144:1] RDCOUNT_TYPE_REG = RDCOUNT_TYPE;
localparam [5:0] READ_WIDTH_REG = READ_WIDTH;
localparam [96:1] REGISTER_MODE_REG = REGISTER_MODE;
localparam [48:1] RSTREG_PRIORITY_REG = RSTREG_PRIORITY;
localparam [40:1] SLEEP_ASYNC_REG = SLEEP_ASYNC;
localparam [35:0] SRVAL_REG = SRVAL;
localparam [144:1] WRCOUNT_TYPE_REG = WRCOUNT_TYPE;
localparam [5:0] WRITE_WIDTH_REG = WRITE_WIDTH;
`endif
wire [2:0] CASCADE_ORDER_BIN;
wire CLOCK_DOMAINS_BIN;
wire FIRST_WORD_FALL_THROUGH_BIN;
wire [35:0] INIT_BIN;
wire IS_RDCLK_INVERTED_BIN;
wire IS_RDEN_INVERTED_BIN;
wire IS_RSTREG_INVERTED_BIN;
wire IS_RST_INVERTED_BIN;
wire IS_WRCLK_INVERTED_BIN;
wire IS_WREN_INVERTED_BIN;
wire [12:0] PROG_EMPTY_THRESH_BIN;
wire [12:0] PROG_FULL_THRESH_BIN;
wire [1:0] RDCOUNT_TYPE_BIN;
wire [5:0] READ_WIDTH_BIN;
wire [1:0] REGISTER_MODE_BIN;
wire RSTREG_PRIORITY_BIN;
wire SLEEP_ASYNC_BIN;
wire [35:0] SRVAL_BIN;
wire [1:0] WRCOUNT_TYPE_BIN;
wire [6:0] WRITE_WIDTH_BIN;
reg INIT_MEM = 0;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR || INIT_MEM;
wire CASNXTEMPTY_out;
wire CASPRVRDEN_out;
wire EMPTY_out;
wire FULL_out;
wire PROGEMPTY_out;
wire PROGFULL_out;
wire RDERR_out;
wire RDRSTBUSY_out;
wire WRERR_out;
wire WRRSTBUSY_out;
wire [12:0] RDCOUNT_out;
wire [12:0] WRCOUNT_out;
wire [31:0] CASDOUT_out;
reg [31:0] DOUT_out;
wire [3:0] CASDOUTP_out;
reg [3:0] DOUTP_out;
wire CASDOMUXEN_in;
wire CASDOMUX_in;
wire CASNXTRDEN_in;
wire CASOREGIMUXEN_in;
wire CASOREGIMUX_in;
wire CASPRVEMPTY_in;
wire RDCLK_in;
wire RDEN_in;
wire REGCE_in;
wire RSTREG_in;
wire RST_in;
wire SLEEP_in;
wire WRCLK_in;
wire WREN_in;
wire [31:0] CASDIN_in;
reg [31:0] DIN_in;
wire [3:0] CASDINP_in;
reg [3:0] DINP_in;
`ifdef XIL_TIMING
wire CASDOMUXEN_delay;
wire CASDOMUX_delay;
wire CASNXTRDEN_delay;
wire CASOREGIMUXEN_delay;
wire CASOREGIMUX_delay;
wire CASPRVEMPTY_delay;
wire RDCLK_delay;
wire RDEN_delay;
wire REGCE_delay;
wire RSTREG_delay;
wire RST_delay;
wire SLEEP_delay;
wire WRCLK_delay;
wire WREN_delay;
wire [31:0] CASDIN_delay;
wire [31:0] DIN_delay;
wire [3:0] CASDINP_delay;
wire [3:0] DINP_delay;
`endif
assign CASDOUT = CASDOUT_out;
assign CASDOUTP = CASDOUTP_out;
assign CASNXTEMPTY = CASNXTEMPTY_out;
assign CASPRVRDEN = CASPRVRDEN_out;
assign DOUT = DOUT_out;
assign DOUTP = DOUTP_out;
assign EMPTY = EMPTY_out;
assign FULL = FULL_out;
assign PROGEMPTY = PROGEMPTY_out;
assign PROGFULL = PROGFULL_out;
assign RDCOUNT = RDCOUNT_out;
assign RDERR = RDERR_out;
assign RDRSTBUSY = RDRSTBUSY_out;
assign WRCOUNT = WRCOUNT_out;
assign WRERR = WRERR_out;
assign WRRSTBUSY = WRRSTBUSY_out;
`ifdef XIL_TIMING
assign CASDINP_in[0] = (CASDINP[0] !== 1'bz) && CASDINP_delay[0]; // rv 0
assign CASDINP_in[1] = (CASDINP[1] !== 1'bz) && CASDINP_delay[1]; // rv 0
assign CASDINP_in[2] = (CASDINP[2] !== 1'bz) && CASDINP_delay[2]; // rv 0
assign CASDINP_in[3] = (CASDINP[3] !== 1'bz) && CASDINP_delay[3]; // rv 0
assign CASDIN_in[0] = (CASDIN[0] !== 1'bz) && CASDIN_delay[0]; // rv 0
assign CASDIN_in[10] = (CASDIN[10] !== 1'bz) && CASDIN_delay[10]; // rv 0
assign CASDIN_in[11] = (CASDIN[11] !== 1'bz) && CASDIN_delay[11]; // rv 0
assign CASDIN_in[12] = (CASDIN[12] !== 1'bz) && CASDIN_delay[12]; // rv 0
assign CASDIN_in[13] = (CASDIN[13] !== 1'bz) && CASDIN_delay[13]; // rv 0
assign CASDIN_in[14] = (CASDIN[14] !== 1'bz) && CASDIN_delay[14]; // rv 0
assign CASDIN_in[15] = (CASDIN[15] !== 1'bz) && CASDIN_delay[15]; // rv 0
assign CASDIN_in[16] = (CASDIN[16] !== 1'bz) && CASDIN_delay[16]; // rv 0
assign CASDIN_in[17] = (CASDIN[17] !== 1'bz) && CASDIN_delay[17]; // rv 0
assign CASDIN_in[18] = (CASDIN[18] !== 1'bz) && CASDIN_delay[18]; // rv 0
assign CASDIN_in[19] = (CASDIN[19] !== 1'bz) && CASDIN_delay[19]; // rv 0
assign CASDIN_in[1] = (CASDIN[1] !== 1'bz) && CASDIN_delay[1]; // rv 0
assign CASDIN_in[20] = (CASDIN[20] !== 1'bz) && CASDIN_delay[20]; // rv 0
assign CASDIN_in[21] = (CASDIN[21] !== 1'bz) && CASDIN_delay[21]; // rv 0
assign CASDIN_in[22] = (CASDIN[22] !== 1'bz) && CASDIN_delay[22]; // rv 0
assign CASDIN_in[23] = (CASDIN[23] !== 1'bz) && CASDIN_delay[23]; // rv 0
assign CASDIN_in[24] = (CASDIN[24] !== 1'bz) && CASDIN_delay[24]; // rv 0
assign CASDIN_in[25] = (CASDIN[25] !== 1'bz) && CASDIN_delay[25]; // rv 0
assign CASDIN_in[26] = (CASDIN[26] !== 1'bz) && CASDIN_delay[26]; // rv 0
assign CASDIN_in[27] = (CASDIN[27] !== 1'bz) && CASDIN_delay[27]; // rv 0
assign CASDIN_in[28] = (CASDIN[28] !== 1'bz) && CASDIN_delay[28]; // rv 0
assign CASDIN_in[29] = (CASDIN[29] !== 1'bz) && CASDIN_delay[29]; // rv 0
assign CASDIN_in[2] = (CASDIN[2] !== 1'bz) && CASDIN_delay[2]; // rv 0
assign CASDIN_in[30] = (CASDIN[30] !== 1'bz) && CASDIN_delay[30]; // rv 0
assign CASDIN_in[31] = (CASDIN[31] !== 1'bz) && CASDIN_delay[31]; // rv 0
assign CASDIN_in[3] = (CASDIN[3] !== 1'bz) && CASDIN_delay[3]; // rv 0
assign CASDIN_in[4] = (CASDIN[4] !== 1'bz) && CASDIN_delay[4]; // rv 0
assign CASDIN_in[5] = (CASDIN[5] !== 1'bz) && CASDIN_delay[5]; // rv 0
assign CASDIN_in[6] = (CASDIN[6] !== 1'bz) && CASDIN_delay[6]; // rv 0
assign CASDIN_in[7] = (CASDIN[7] !== 1'bz) && CASDIN_delay[7]; // rv 0
assign CASDIN_in[8] = (CASDIN[8] !== 1'bz) && CASDIN_delay[8]; // rv 0
assign CASDIN_in[9] = (CASDIN[9] !== 1'bz) && CASDIN_delay[9]; // rv 0
assign CASDOMUXEN_in = (CASDOMUXEN === 1'bz) || CASDOMUXEN_delay; // rv 1
assign CASDOMUX_in = (CASDOMUX !== 1'bz) && CASDOMUX_delay; // rv 0
assign CASNXTRDEN_in = (CASNXTRDEN !== 1'bz) && CASNXTRDEN_delay; // rv 0
assign CASOREGIMUXEN_in = (CASOREGIMUXEN === 1'bz) || CASOREGIMUXEN_delay; // rv 1
assign CASOREGIMUX_in = (CASOREGIMUX !== 1'bz) && CASOREGIMUX_delay; // rv 0
assign CASPRVEMPTY_in = (CASPRVEMPTY !== 1'bz) && CASPRVEMPTY_delay; // rv 0
always @ (*) DINP_in = DINP_delay;
always @ (*) DIN_in = DIN_delay;
assign RDCLK_in = (RDCLK !== 1'bz) && (RDCLK_delay ^ IS_RDCLK_INVERTED_BIN); // rv 0
assign RDEN_in = (RDEN !== 1'bz) && (RDEN_delay ^ IS_RDEN_INVERTED_BIN); // rv 0
assign REGCE_in = (REGCE === 1'bz) || REGCE_delay; // rv 1
assign RSTREG_in = (RSTREG !== 1'bz) && (RSTREG_delay ^ IS_RSTREG_INVERTED_BIN); // rv 0
assign RST_in = (RST !== 1'bz) && (RST_delay ^ IS_RST_INVERTED_BIN); // rv 0
assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP_delay; // rv 0
assign WRCLK_in = (WRCLK !== 1'bz) && (WRCLK_delay ^ IS_WRCLK_INVERTED_BIN); // rv 0
assign WREN_in = (WREN !== 1'bz) && (WREN_delay ^ IS_WREN_INVERTED_BIN); // rv 0
`else
assign CASDINP_in[0] = (CASDINP[0] !== 1'bz) && CASDINP[0]; // rv 0
assign CASDINP_in[1] = (CASDINP[1] !== 1'bz) && CASDINP[1]; // rv 0
assign CASDINP_in[2] = (CASDINP[2] !== 1'bz) && CASDINP[2]; // rv 0
assign CASDINP_in[3] = (CASDINP[3] !== 1'bz) && CASDINP[3]; // rv 0
assign CASDIN_in[0] = (CASDIN[0] !== 1'bz) && CASDIN[0]; // rv 0
assign CASDIN_in[10] = (CASDIN[10] !== 1'bz) && CASDIN[10]; // rv 0
assign CASDIN_in[11] = (CASDIN[11] !== 1'bz) && CASDIN[11]; // rv 0
assign CASDIN_in[12] = (CASDIN[12] !== 1'bz) && CASDIN[12]; // rv 0
assign CASDIN_in[13] = (CASDIN[13] !== 1'bz) && CASDIN[13]; // rv 0
assign CASDIN_in[14] = (CASDIN[14] !== 1'bz) && CASDIN[14]; // rv 0
assign CASDIN_in[15] = (CASDIN[15] !== 1'bz) && CASDIN[15]; // rv 0
assign CASDIN_in[16] = (CASDIN[16] !== 1'bz) && CASDIN[16]; // rv 0
assign CASDIN_in[17] = (CASDIN[17] !== 1'bz) && CASDIN[17]; // rv 0
assign CASDIN_in[18] = (CASDIN[18] !== 1'bz) && CASDIN[18]; // rv 0
assign CASDIN_in[19] = (CASDIN[19] !== 1'bz) && CASDIN[19]; // rv 0
assign CASDIN_in[1] = (CASDIN[1] !== 1'bz) && CASDIN[1]; // rv 0
assign CASDIN_in[20] = (CASDIN[20] !== 1'bz) && CASDIN[20]; // rv 0
assign CASDIN_in[21] = (CASDIN[21] !== 1'bz) && CASDIN[21]; // rv 0
assign CASDIN_in[22] = (CASDIN[22] !== 1'bz) && CASDIN[22]; // rv 0
assign CASDIN_in[23] = (CASDIN[23] !== 1'bz) && CASDIN[23]; // rv 0
assign CASDIN_in[24] = (CASDIN[24] !== 1'bz) && CASDIN[24]; // rv 0
assign CASDIN_in[25] = (CASDIN[25] !== 1'bz) && CASDIN[25]; // rv 0
assign CASDIN_in[26] = (CASDIN[26] !== 1'bz) && CASDIN[26]; // rv 0
assign CASDIN_in[27] = (CASDIN[27] !== 1'bz) && CASDIN[27]; // rv 0
assign CASDIN_in[28] = (CASDIN[28] !== 1'bz) && CASDIN[28]; // rv 0
assign CASDIN_in[29] = (CASDIN[29] !== 1'bz) && CASDIN[29]; // rv 0
assign CASDIN_in[2] = (CASDIN[2] !== 1'bz) && CASDIN[2]; // rv 0
assign CASDIN_in[30] = (CASDIN[30] !== 1'bz) && CASDIN[30]; // rv 0
assign CASDIN_in[31] = (CASDIN[31] !== 1'bz) && CASDIN[31]; // rv 0
assign CASDIN_in[3] = (CASDIN[3] !== 1'bz) && CASDIN[3]; // rv 0
assign CASDIN_in[4] = (CASDIN[4] !== 1'bz) && CASDIN[4]; // rv 0
assign CASDIN_in[5] = (CASDIN[5] !== 1'bz) && CASDIN[5]; // rv 0
assign CASDIN_in[6] = (CASDIN[6] !== 1'bz) && CASDIN[6]; // rv 0
assign CASDIN_in[7] = (CASDIN[7] !== 1'bz) && CASDIN[7]; // rv 0
assign CASDIN_in[8] = (CASDIN[8] !== 1'bz) && CASDIN[8]; // rv 0
assign CASDIN_in[9] = (CASDIN[9] !== 1'bz) && CASDIN[9]; // rv 0
assign CASDOMUXEN_in = (CASDOMUXEN === 1'bz) || CASDOMUXEN; // rv 1
assign CASDOMUX_in = (CASDOMUX !== 1'bz) && CASDOMUX; // rv 0
assign CASNXTRDEN_in = (CASNXTRDEN !== 1'bz) && CASNXTRDEN; // rv 0
assign CASOREGIMUXEN_in = (CASOREGIMUXEN === 1'bz) || CASOREGIMUXEN; // rv 1
assign CASOREGIMUX_in = (CASOREGIMUX !== 1'bz) && CASOREGIMUX; // rv 0
assign CASPRVEMPTY_in = (CASPRVEMPTY !== 1'bz) && CASPRVEMPTY; // rv 0
always @ (*) DINP_in = DINP;
always @ (*) DIN_in = DIN;
assign RDCLK_in = (RDCLK !== 1'bz) && (RDCLK ^ IS_RDCLK_INVERTED_BIN); // rv 0
assign RDEN_in = (RDEN !== 1'bz) && (RDEN ^ IS_RDEN_INVERTED_BIN); // rv 0
assign REGCE_in = (REGCE === 1'bz) || REGCE; // rv 1
assign RSTREG_in = (RSTREG !== 1'bz) && (RSTREG ^ IS_RSTREG_INVERTED_BIN); // rv 0
assign RST_in = (RST !== 1'bz) && (RST ^ IS_RST_INVERTED_BIN); // rv 0
assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP; // rv 0
assign WRCLK_in = (WRCLK !== 1'bz) && (WRCLK ^ IS_WRCLK_INVERTED_BIN); // rv 0
assign WREN_in = (WREN !== 1'bz) && (WREN ^ IS_WREN_INVERTED_BIN); // rv 0
`endif
// internal variables, signals, busses
localparam integer ADDR_WIDTH = 14;
localparam integer INIT_WIDTH = 36;
localparam integer D_WIDTH = 32;
localparam integer DP_WIDTH = 4;
localparam mem_width = 1;
localparam memp_width = 1;
localparam mem_size = 16384;
localparam mem_depth = mem_size;
localparam memp_depth = mem_size/8;
localparam mem_pad = 32;
localparam memp_pad = 4;
integer i=0;
integer j=0;
integer k=0;
integer ra=0;
integer raa=0;
integer raw=0;
integer wb=0;
integer rd_loops_a = 1;
integer wr_loops_b = 1;
localparam max_rd_loops = D_WIDTH;
localparam max_wr_loops = D_WIDTH;
integer rdcount_adj = 0;
integer wrcount_adj = 0;
integer wr_adj = 0;
wire RDEN_int;
wire RDEN_lat;
wire WREN_int;
wire WREN_lat;
wire RDEN_reg;
reg fill_lat=0;
reg fill_reg=0;
wire SLEEP_A_int;
wire SLEEP_B_int;
reg [1:0] SLEEP_A_reg = 2'b0;
reg [1:0] SLEEP_B_reg = 2'b0;
wire RSTREG_A_int;
wire REGCE_A_int;
wire [3:0] DINP_int;
reg CASDOMUXA_reg = 1'b0;
reg CASOREGIMUXA_reg = 1'b0;
wire prog_empty;
reg prog_empty_cc = 1;
reg ram_full_c = 0;
wire ram_empty;
reg ram_empty_i = 1;
reg ram_empty_c = 1;
reg o_lat_empty = 1;
reg o_reg_empty = 1;
wire [1:0] output_stages;
wire o_stages_full;
wire o_stages_empty;
reg o_stages_full_sync=0;
reg o_stages_full_sync1=0;
reg o_stages_full_sync2=0;
reg o_stages_full_sync3=0;
wire prog_full;
reg prog_full_reg = 1'b0;
reg rderr_reg = 1'b0;
reg wrerr_reg = 1'b0;
wire [INIT_WIDTH-1:0] INIT_A_int;
wire [INIT_WIDTH-1:0] SRVAL_A_int;
wire mem_wr_en_b;
reg mem_wr_en_b_wf = 1'b0;
wire [D_WIDTH-1:0] mem_we_b;
wire [DP_WIDTH-1:0] memp_we_b;
wire [D_WIDTH-1:0] mem_rm_douta;
wire [DP_WIDTH-1:0] memp_rm_douta;
wire mem_rd_en_a;
wire mem_rst_a;
reg mem_is_rst_a = 1'b0;
reg rdcount_en = 1'b0;
reg mem [0 : mem_depth+mem_pad-1];
reg [D_WIDTH-1 : 0] ram_rd_a;
reg [D_WIDTH-1 : 0] mem_wr_b;
reg wr_b_event = 1'b0;
reg [D_WIDTH-1 : 0] mem_rd_b_rf;
reg [D_WIDTH-1 : 0] mem_rd_b_wf;
reg [D_WIDTH-1 : 0] mem_a_reg;
reg [D_WIDTH-1 : 0] mem_a_reg_mux;
reg [D_WIDTH-1 : 0] mem_a_lat;
reg memp [0 : memp_depth+memp_pad-1];
reg [DP_WIDTH-1 : 0] ramp_rd_a;
wire [DP_WIDTH-1 : 0] memp_wr_b;
reg [DP_WIDTH-1 : 0] memp_rd_b_rf;
reg [DP_WIDTH-1 : 0] memp_rd_b_wf;
reg [DP_WIDTH-1 : 0] memp_a_reg;
reg [DP_WIDTH-1 : 0] memp_a_reg_mux;
reg [DP_WIDTH-1 : 0] memp_a_lat;
reg [DP_WIDTH-1 : 0] memp_a_out;
wire [ADDR_WIDTH-1:0] wr_addr_b_mask;
reg [ADDR_WIDTH-1:0] rd_addr_a = 0;
reg [ADDR_WIDTH-1:0] wr_addr_b = 0;
reg [ADDR_WIDTH-1:0] rd_addr_a_wr = 0;
reg [ADDR_WIDTH-1:0] wr_addr_b_rd = 0;
reg [ADDR_WIDTH-1:0] rd_addr_sync_wr = 0;
reg [ADDR_WIDTH-1:0] rd_addr_sync_wr2 = 0;
reg [ADDR_WIDTH-1:0] rd_addr_sync_wr1 = 0;
reg [ADDR_WIDTH-1:0] wr_addr_sync_rd = 0;
reg [ADDR_WIDTH-1:0] wr_addr_sync_rd2 = 0;
reg [ADDR_WIDTH-1:0] wr_addr_sync_rd1 = 0;
wire [ADDR_WIDTH-1:0] rd_addr_wr;
wire [ADDR_WIDTH-1:0] next_rd_addr_wr;
wire [ADDR_WIDTH-1:0] wr_addr_rd;
wire [ADDR_WIDTH-1:0] next_wr_addr_rd;
wire [ADDR_WIDTH:0] wr_simple_raw;
// wire [ADDR_WIDTH:0] rd_simple_raw;
wire [ADDR_WIDTH-1:0] wr_simple;
wire [ADDR_WIDTH:0] rd_simple;
reg [ADDR_WIDTH-1:0] rd_simple_cc = 0;
reg [ADDR_WIDTH-1:0] wr_simple_sync = 0;
reg [ADDR_WIDTH-1:0] rd_simple_sync = 0;
//reset logic variables
reg WRRST_int = 1'b0;
reg RST_sync = 1'b0;
reg WRRST_done = 1'b0;
reg WRRST_done1 = 1'b0;
reg WRRST_done2 = 1'b0;
wire RDRST_int;
reg RDRST_done = 1'b0;
reg RDRST_done1 = 1'b0;
reg RDRST_done2 = 1'b0;
wire WRRST_done_wr;
reg WRRST_in_sync_rd = 1'b0;
reg WRRST_in_sync_rd1 = 1'b0;
reg WRRSTBUSY_dly = 1'b0;
reg WRRSTBUSY_dly1 = 1'b0;
reg RDRSTBUSY_dly = 1'b0;
reg RDRSTBUSY_dly1 = 1'b0;
reg RDRSTBUSY_dly2 = 1'b0;
reg sdp_mode = 1'b1;
reg sdp_mode_wr = 1'b1;
reg sdp_mode_rd = 1'b1;
// full/empty variables
wire [ADDR_WIDTH-1:0] full_count;
wire [ADDR_WIDTH-1:0] next_full_count;
wire [ADDR_WIDTH-1:0] full_count_masked;
wire [8:0] m_full;
wire [8:0] m_full_raw;
wire [5:0] n_empty;
wire [5:0] unr_ratio;
wire [ADDR_WIDTH+1:0] prog_full_val;
wire [ADDR_WIDTH+1:0] prog_empty_val;
reg ram_full_i;
wire ram_one_from_full_i;
wire ram_two_from_full_i;
wire ram_one_from_full;
wire ram_two_from_full;
wire ram_one_read_from_not_full;
wire [ADDR_WIDTH-1:0] empty_count;
wire [ADDR_WIDTH-1:0] next_empty_count;
wire ram_one_read_from_empty_i;
wire ram_one_read_from_empty;
wire ram_one_write_from_not_empty;
wire ram_one_write_from_not_empty_i;
reg en_clk_sync = 1'b0;
reg cas_warning = 1'b0;
task is_cas_connected;
integer i;
begin
for (i=0;i<=31;i=i+1) begin
if (CASDIN[i] === 1'bz) begin
cas_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASDIN[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i);
end
end
for (i=0;i<=3;i=i+1) begin
if (CASDINP[i] === 1'bz) begin
cas_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASDINP[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i);
end
end
if (CASDOMUX === 1'bz) begin
cas_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASDOMUX signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CASDOMUXEN === 1'bz) begin
cas_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASDOMUXEN signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CASNXTRDEN === 1'bz) begin
cas_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASNXTRDEN signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CASOREGIMUX === 1'bz) begin
cas_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASOREGIMUX signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CASOREGIMUXEN === 1'bz) begin
cas_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASOREGIMUXEN signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
end
endtask // is_cas_connected
assign RDEN_int = ((CASCADE_ORDER_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ?
CASNXTRDEN_in && ~SLEEP_A_int : RDEN_in;
assign WREN_int = ((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ?
~(CASPRVEMPTY_in || FULL_out || SLEEP_B_int) : WREN_in;
assign DINP_int = ((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ? CASDINP_in : DINP_in;
assign mem_wr_en_b = WREN_int && ~FULL_out && ~WRRSTBUSY_out;
assign mem_rd_en_a = (RDEN_int ||
((fill_lat || fill_reg) && ~SLEEP_A_int)) &&
~ram_empty && ~RDRST_int;
always @ (*) begin
if ((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE))
mem_wr_b = CASDIN_in;
else
mem_wr_b = DIN_in;
end
assign memp_wr_b = DINP_int;
//victor DRC
reg sleep_is_asserted;
reg sleep_is_deasserted;
reg RDEN_p1;
reg RDEN_p2;
reg RDEN_p3;
reg RDEN_p4;
reg RDEN_p5;
reg RDEN_p6;
reg WREN_p1;
reg WREN_p2;
reg WREN_p3;
reg SLEEPA_p1;
reg SLEEPA_p2;
reg SLEEPB_p1;
reg SLEEPB_p2;
always @(SLEEP_in) begin
sleep_is_asserted <= 1'b0;
sleep_is_deasserted <= 1'b0;
if (SLEEP_in == 1'b1)
sleep_is_asserted <= 1'b1;
else if (SLEEP_in == 1'b0)
sleep_is_deasserted <= 1'b1;
end
//victor drc #5
always @(posedge RDCLK_in) begin
if (sleep_is_asserted && RDEN_in) begin
$display("Error: [Unisim %s-23] DRC : RDEN must be LOW in the clock cycle when SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME);
end
end
always @(posedge WRCLK_in) begin
if (sleep_is_asserted && WREN_in) begin
$display("Error: [Unisim %s-23] DRC : WREN must be LOW in the clock cycle when SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME);
end
end
always @(posedge RDCLK_in) begin
if (glblGSR) begin
RDEN_p1 <= 1'b0;
RDEN_p2 <= 1'b0;
RDEN_p3 <= 1'b0;
RDEN_p4 <= 1'b0;
RDEN_p5 <= 1'b0;
RDEN_p6 <= 1'b0;
end
else begin
RDEN_p1 <= RDEN_in;
RDEN_p2 <= RDEN_p1;
RDEN_p3 <= RDEN_p2;
RDEN_p4 <= RDEN_p3;
RDEN_p5 <= RDEN_p4;
RDEN_p6 <= RDEN_p5;
end
end
always @(posedge WRCLK_in) begin
if (glblGSR) begin
WREN_p1 <= 1'b0;
WREN_p2 <= 1'b0;
WREN_p3 <= 1'b0;
end
else begin
WREN_p1 <= WREN_in;
WREN_p2 <= WREN_p1;
WREN_p3 <= WREN_p2;
end
end
always @(posedge RDCLK_in or posedge WRCLK_in) begin
if (FIRST_WORD_FALL_THROUGH_REG == "FALSE") begin
if (sleep_is_asserted && RDEN_p1)
$display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, RDEN must be LOW at least one RDCLK cycle before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME);
if (sleep_is_asserted && WREN_p1)
$display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, WREN must be LOW at least one WRCLK cycle before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME);
end
end
always @(posedge RDCLK_in or posedge WRCLK_in) begin
if ((FIRST_WORD_FALL_THROUGH_REG == "TRUE") && (CLOCK_DOMAINS_REG == "COMMON")) begin
if (sleep_is_asserted && RDEN_p1)
$display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, RDEN must be LOW at least one cycle before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME);
if (sleep_is_asserted && WREN_p3)
$display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, WREN must be LOW at least three cycle before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME);
end
end
always @(posedge RDCLK_in or posedge WRCLK_in) begin
if ((FIRST_WORD_FALL_THROUGH_REG == "TRUE") && (CLOCK_DOMAINS_REG == "INDEPENDENT")) begin
if (sleep_is_asserted && RDEN_p1)
$display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, RDEN must be LOW at least one cycle before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME);
if (sleep_is_asserted && WREN_p3 && RDEN_p6)
$display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, WREN must be LOW at least one WRCLK plus six RDCLK cycles before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME);
end
end
//victor drc #6
always @(posedge RDCLK_in) begin
if (glblGSR) begin
SLEEPA_p1 <= 1'b0;
SLEEPA_p2 <= 1'b0;
end
else begin
SLEEPA_p1 <= SLEEP_in;
SLEEPA_p2 <= SLEEPA_p1;
end
end
always @(posedge WRCLK_in) begin
if (glblGSR) begin
SLEEPB_p1 <= 1'b0;
SLEEPB_p2 <= 1'b0;
end
else begin
SLEEPB_p1 <= SLEEP_in;
SLEEPB_p2 <= SLEEPB_p1;
end
end
always @(RDEN_in) begin
if (RDEN_in && SLEEPA_p2)
$display("Error: [Unisim %s-23] DRC : RDEN can be asserted at least 2 cycles RDCLK after SLEEP signal has been de-asserted. Instance: %m", MODULE_NAME);
end
always @(WREN_in) begin
if (WREN_in && SLEEPB_p2)
$display("Error: [Unisim %s-23] DRC : WREN can be asserted at least 2 cycles WRCLK after SLEEP signal has been de-asserted. Instance: %m", MODULE_NAME);
end
assign CASCADE_ORDER_BIN =
(CASCADE_ORDER_REG == "NONE") ? CASCADE_ORDER_NONE :
(CASCADE_ORDER_REG == "FIRST") ? CASCADE_ORDER_FIRST :
(CASCADE_ORDER_REG == "LAST") ? CASCADE_ORDER_LAST :
(CASCADE_ORDER_REG == "MIDDLE") ? CASCADE_ORDER_MIDDLE :
(CASCADE_ORDER_REG == "PARALLEL") ? CASCADE_ORDER_PARALLEL :
CASCADE_ORDER_NONE;
assign CLOCK_DOMAINS_BIN =
(CLOCK_DOMAINS_REG == "INDEPENDENT") ? CLOCK_DOMAINS_INDEPENDENT :
(CLOCK_DOMAINS_REG == "COMMON") ? CLOCK_DOMAINS_COMMON :
CLOCK_DOMAINS_INDEPENDENT;
assign FIRST_WORD_FALL_THROUGH_BIN =
(FIRST_WORD_FALL_THROUGH_REG == "FALSE") ? FIRST_WORD_FALL_THROUGH_FALSE :
(FIRST_WORD_FALL_THROUGH_REG == "TRUE") ? FIRST_WORD_FALL_THROUGH_TRUE :
FIRST_WORD_FALL_THROUGH_FALSE;
assign INIT_BIN = INIT_REG;
assign IS_RDCLK_INVERTED_BIN = IS_RDCLK_INVERTED_REG;
assign IS_RDEN_INVERTED_BIN = IS_RDEN_INVERTED_REG;
assign IS_RSTREG_INVERTED_BIN = IS_RSTREG_INVERTED_REG;
assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG;
assign IS_WRCLK_INVERTED_BIN = IS_WRCLK_INVERTED_REG;
assign IS_WREN_INVERTED_BIN = IS_WREN_INVERTED_REG;
assign PROG_EMPTY_THRESH_BIN = PROG_EMPTY_THRESH_REG;
assign PROG_FULL_THRESH_BIN = PROG_FULL_THRESH_REG;
assign RDCOUNT_TYPE_BIN =
(RDCOUNT_TYPE_REG == "RAW_PNTR") ? RDCOUNT_TYPE_RAW_PNTR :
(RDCOUNT_TYPE_REG == "EXTENDED_DATACOUNT") ? RDCOUNT_TYPE_EXTENDED_DATACOUNT :
(RDCOUNT_TYPE_REG == "SIMPLE_DATACOUNT") ? RDCOUNT_TYPE_SIMPLE_DATACOUNT :
(RDCOUNT_TYPE_REG == "SYNC_PNTR") ? RDCOUNT_TYPE_SYNC_PNTR :
RDCOUNT_TYPE_RAW_PNTR;
assign READ_WIDTH_BIN =
(READ_WIDTH_REG == 4) ? READ_WIDTH_4 :
(READ_WIDTH_REG == 9) ? READ_WIDTH_9 :
(READ_WIDTH_REG == 18) ? READ_WIDTH_18 :
(READ_WIDTH_REG == 36) ? READ_WIDTH_36 :
READ_WIDTH_4;
assign REGISTER_MODE_BIN =
(REGISTER_MODE_REG == "UNREGISTERED") ? REGISTER_MODE_UNREGISTERED :
(REGISTER_MODE_REG == "DO_PIPELINED") ? REGISTER_MODE_DO_PIPELINED :
(REGISTER_MODE_REG == "REGISTERED") ? REGISTER_MODE_REGISTERED :
REGISTER_MODE_UNREGISTERED;
assign RSTREG_PRIORITY_BIN =
(RSTREG_PRIORITY_REG == "RSTREG") ? RSTREG_PRIORITY_RSTREG :
(RSTREG_PRIORITY_REG == "REGCE") ? RSTREG_PRIORITY_REGCE :
RSTREG_PRIORITY_RSTREG;
assign SLEEP_ASYNC_BIN =
(SLEEP_ASYNC_REG == "FALSE") ? SLEEP_ASYNC_FALSE :
(SLEEP_ASYNC_REG == "TRUE") ? SLEEP_ASYNC_TRUE :
SLEEP_ASYNC_FALSE;
assign SRVAL_BIN = SRVAL_REG;
assign WRCOUNT_TYPE_BIN =
(WRCOUNT_TYPE_REG == "RAW_PNTR") ? WRCOUNT_TYPE_RAW_PNTR :
(WRCOUNT_TYPE_REG == "EXTENDED_DATACOUNT") ? WRCOUNT_TYPE_EXTENDED_DATACOUNT :
(WRCOUNT_TYPE_REG == "SIMPLE_DATACOUNT") ? WRCOUNT_TYPE_SIMPLE_DATACOUNT :
(WRCOUNT_TYPE_REG == "SYNC_PNTR") ? WRCOUNT_TYPE_SYNC_PNTR :
WRCOUNT_TYPE_RAW_PNTR;
assign WRITE_WIDTH_BIN =
(WRITE_WIDTH_REG == 4) ? WRITE_WIDTH_4 :
(WRITE_WIDTH_REG == 9) ? WRITE_WIDTH_9 :
(WRITE_WIDTH_REG == 18) ? WRITE_WIDTH_18 :
(WRITE_WIDTH_REG == 36) ? WRITE_WIDTH_36 :
WRITE_WIDTH_4;
initial begin
#1;
trig_attr = 1'b1;
#100;
trig_attr = 1'b0;
end
always @ (posedge trig_attr) begin
INIT_MEM <= #100 1'b1;
INIT_MEM <= #200 1'b0;
if ((attr_test == 1'b1) ||
((CASCADE_ORDER_REG != "NONE") &&
(CASCADE_ORDER_REG != "FIRST") &&
(CASCADE_ORDER_REG != "LAST") &&
(CASCADE_ORDER_REG != "MIDDLE") &&
(CASCADE_ORDER_REG != "PARALLEL"))) begin
$display("Error: [Unisim %s-101] CASCADE_ORDER attribute is set to %s. Legal values for this attribute are NONE, FIRST, LAST, MIDDLE or PARALLEL. Instance: %m", MODULE_NAME, CASCADE_ORDER_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLOCK_DOMAINS_REG != "INDEPENDENT") &&
(CLOCK_DOMAINS_REG != "COMMON"))) begin
$display("Error: [Unisim %s-103] CLOCK_DOMAINS attribute is set to %s. Legal values for this attribute are INDEPENDENT or COMMON. Instance: %m", MODULE_NAME, CLOCK_DOMAINS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((FIRST_WORD_FALL_THROUGH_REG != "FALSE") &&
(FIRST_WORD_FALL_THROUGH_REG != "TRUE"))) begin
$display("Error: [Unisim %s-106] FIRST_WORD_FALL_THROUGH attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FIRST_WORD_FALL_THROUGH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PROG_EMPTY_THRESH_REG < 1) || (PROG_EMPTY_THRESH_REG > 8191))) begin
$display("Error: [Unisim %s-114] PROG_EMPTY_THRESH attribute is set to %d. Legal values for this attribute are 1 to 8191. Instance: %m", MODULE_NAME, PROG_EMPTY_THRESH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PROG_FULL_THRESH_REG < 1) || (PROG_FULL_THRESH_REG > 8191))) begin
$display("Error: [Unisim %s-115] PROG_FULL_THRESH attribute is set to %d. Legal values for this attribute are 1 to 8191. Instance: %m", MODULE_NAME, PROG_FULL_THRESH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RDCOUNT_TYPE_REG != "RAW_PNTR") &&
(RDCOUNT_TYPE_REG != "EXTENDED_DATACOUNT") &&
(RDCOUNT_TYPE_REG != "SIMPLE_DATACOUNT") &&
(RDCOUNT_TYPE_REG != "SYNC_PNTR"))) begin
$display("Error: [Unisim %s-116] RDCOUNT_TYPE attribute is set to %s. Legal values for this attribute are RAW_PNTR, EXTENDED_DATACOUNT, SIMPLE_DATACOUNT or SYNC_PNTR. Instance: %m", MODULE_NAME, RDCOUNT_TYPE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_WIDTH_REG != 4) &&
(READ_WIDTH_REG != 9) &&
(READ_WIDTH_REG != 18) &&
(READ_WIDTH_REG != 36))) begin
$display("Error: [Unisim %s-117] READ_WIDTH attribute is set to %d. Legal values for this attribute are 4, 9, 18 or 36. Instance: %m", MODULE_NAME, READ_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((REGISTER_MODE_REG != "UNREGISTERED") &&
(REGISTER_MODE_REG != "DO_PIPELINED") &&
(REGISTER_MODE_REG != "REGISTERED"))) begin
$display("Error: [Unisim %s-118] REGISTER_MODE attribute is set to %s. Legal values for this attribute are UNREGISTERED, DO_PIPELINED or REGISTERED. Instance: %m", MODULE_NAME, REGISTER_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RSTREG_PRIORITY_REG != "RSTREG") &&
(RSTREG_PRIORITY_REG != "REGCE"))) begin
$display("Error: [Unisim %s-119] RSTREG_PRIORITY attribute is set to %s. Legal values for this attribute are RSTREG or REGCE. Instance: %m", MODULE_NAME, RSTREG_PRIORITY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SLEEP_ASYNC_REG != "FALSE") &&
(SLEEP_ASYNC_REG != "TRUE"))) begin
$display("Error: [Unisim %s-273] SLEEP_ASYNC attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SLEEP_ASYNC_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRCOUNT_TYPE_REG != "RAW_PNTR") &&
(WRCOUNT_TYPE_REG != "EXTENDED_DATACOUNT") &&
(WRCOUNT_TYPE_REG != "SIMPLE_DATACOUNT") &&
(WRCOUNT_TYPE_REG != "SYNC_PNTR"))) begin
$display("Error: [Unisim %s-122] WRCOUNT_TYPE attribute is set to %s. Legal values for this attribute are RAW_PNTR, EXTENDED_DATACOUNT, SIMPLE_DATACOUNT or SYNC_PNTR. Instance: %m", MODULE_NAME, WRCOUNT_TYPE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_WIDTH_REG != 4) &&
(WRITE_WIDTH_REG != 9) &&
(WRITE_WIDTH_REG != 18) &&
(WRITE_WIDTH_REG != 36))) begin
$display("Error: [Unisim %s-123] WRITE_WIDTH attribute is set to %d. Legal values for this attribute are 4, 9, 18 or 36. Instance: %m", MODULE_NAME, WRITE_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(PROG_EMPTY_THRESH_REG < 1) ||
(PROG_EMPTY_THRESH_REG >= mem_depth/READ_WIDTH_BIN)) begin
$display("Error: [Unisim %s-124] PROG_EMPTY_THRESH is set to %d. When READ_WIDTH is set to %d PROG_EMPTY_THRESH must be greater than 0 and less than %d. Instance: %m", MODULE_NAME, PROG_EMPTY_THRESH_REG, READ_WIDTH_REG, mem_depth/READ_WIDTH_BIN);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(PROG_FULL_THRESH_REG < 1) ||
(PROG_FULL_THRESH_REG >= mem_depth/WRITE_WIDTH_BIN)) begin
$display("Error: [Unisim %s-125] PROG_FULL_THRESH is set to %d. When WRITE_WIDTH is set to %d PROG_FULL_THRESH must be greater than 0 and less than %d. Instance: %m", MODULE_NAME, PROG_FULL_THRESH_REG, WRITE_WIDTH_REG, mem_depth/WRITE_WIDTH_BIN);
attr_err = 1'b1;
end
if ((CASCADE_ORDER_REG == "LAST") ||
(CASCADE_ORDER_REG == "MIDDLE") ||
(CASCADE_ORDER_REG == "PARALLEL")) begin
is_cas_connected;
if (cas_warning) $display("Warning: [Unisim %s-126] CASCADE_ORDER attribute is set to %s and some or all of the CASCADE signals are unconnected. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly connected. Instance: %m", MODULE_NAME, CASCADE_ORDER_REG);
end
if (attr_err == 1'b1) #100 $finish;
end
initial begin
INIT_MEM <= #100 1'b1;
INIT_MEM <= #200 1'b0;
end
assign output_stages =
((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) &&
(FIRST_WORD_FALL_THROUGH_BIN == FIRST_WORD_FALL_THROUGH_TRUE)) ? 2'b10 :
((REGISTER_MODE_BIN != REGISTER_MODE_REGISTERED) &&
(FIRST_WORD_FALL_THROUGH_BIN != FIRST_WORD_FALL_THROUGH_TRUE)) ? 2'b00 : 2'b01;
assign wr_addr_b_mask =
(WRITE_WIDTH_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} :
(WRITE_WIDTH_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} :
(WRITE_WIDTH_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} :
(WRITE_WIDTH_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} :
{{ADDR_WIDTH-6{1'b1}}, 6'h3f};
always @(READ_WIDTH_BIN) rd_loops_a <= READ_WIDTH_BIN;
always @(WRITE_WIDTH_BIN) wr_loops_b <= WRITE_WIDTH_BIN;
always @ (posedge RDCLK_in) begin
if (glblGSR) begin
SLEEP_A_reg <= 2'b0;
end
else begin
SLEEP_A_reg <= {SLEEP_A_reg[0], SLEEP_in};
end
end
always @ (posedge WRCLK_in) begin
if (glblGSR) begin
SLEEP_B_reg <= 2'b0;
end
else begin
SLEEP_B_reg <= {SLEEP_B_reg[0], SLEEP_in};
end
end
assign SLEEP_A_int = SLEEP_A_reg[1] || SLEEP_A_reg[0] || SLEEP_in;
assign SLEEP_B_int = SLEEP_B_reg[1] || SLEEP_B_reg[0] || SLEEP_in;
assign REGCE_A_int = (REGISTER_MODE_BIN != REGISTER_MODE_DO_PIPELINED) ? RDEN_reg :
REGCE_in;
assign RSTREG_A_int = (REGISTER_MODE_BIN != REGISTER_MODE_DO_PIPELINED) ? RDRST_int :
(RSTREG_PRIORITY_BIN == RSTREG_PRIORITY_RSTREG) ? RSTREG_in :
(RSTREG_in && REGCE_in);
assign RDEN_lat = RDEN_int || ((fill_reg || fill_lat) && ~SLEEP_A_int);
assign WREN_lat = mem_rd_en_a;
assign RDEN_reg = RDEN_int || fill_reg ;
always @ (*) begin
if (((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) && CASDOMUXA_reg)
DOUT_out = CASDIN_in;
else if ((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) ||
(REGISTER_MODE_BIN == REGISTER_MODE_DO_PIPELINED))
DOUT_out = mem_a_reg ^ mem_rm_douta;
else
DOUT_out = mem_a_lat ^ mem_rm_douta;
end
always @ (*) begin
if (((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) && CASDOMUXA_reg)
DOUTP_out = CASDINP_in;
else if ((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) ||
(REGISTER_MODE_BIN == REGISTER_MODE_DO_PIPELINED))
DOUTP_out = memp_a_reg ^ memp_rm_douta;
else
DOUTP_out = memp_a_lat ^ memp_rm_douta;
end
assign INIT_A_int =
(READ_WIDTH_BIN <= READ_WIDTH_9) ? {{4{INIT_BIN[8]}}, {4{INIT_BIN[7:0]}}} :
(READ_WIDTH_BIN == READ_WIDTH_18) ? {{2{INIT_BIN[17:16]}}, {2{INIT_BIN[15:0]}}} :
INIT_BIN;
assign SRVAL_A_int =
(READ_WIDTH_BIN <= READ_WIDTH_9) ? {{4{SRVAL_BIN[8]}}, {4{SRVAL_BIN[7:0]}}} :
(READ_WIDTH_BIN == READ_WIDTH_18) ? {{2{SRVAL_BIN[17:16]}}, {2{SRVAL_BIN[15:0]}}} :
SRVAL_BIN;
assign rd_addr_wr = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? rd_addr_a : rd_addr_sync_wr;
assign wr_addr_rd = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? wr_addr_b : wr_addr_sync_rd;
// in clock domains common what is important is the result of the next clock edge.
assign next_rd_addr_wr = (mem_rd_en_a == 1'b1) ? rd_addr_a + rd_loops_a : rd_addr_a;
assign next_wr_addr_rd = (mem_wr_en_b == 1'b1) ? wr_addr_b + wr_loops_b : wr_addr_b;
assign o_stages_empty =
(output_stages==2'b00) ? ram_empty :
(output_stages==2'b01) ? o_lat_empty :
o_reg_empty; // 2
assign o_stages_full = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? ~o_stages_empty : o_stages_full_sync;
// cascade out
assign CASDOUT_out = ((CASCADE_ORDER_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ?
DOUT_out : {D_WIDTH-1{1'b0}};
assign CASDOUTP_out = ((CASCADE_ORDER_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ?
DOUTP_out : {DP_WIDTH-1{1'b0}};
assign CASNXTEMPTY_out = ((CASCADE_ORDER_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ?
EMPTY_out || SLEEP_A_int : 1'b0;
assign CASPRVRDEN_out = ((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ?
~(CASPRVEMPTY_in || FULL_out || SLEEP_B_int) : 1'b0;
// start model internals
// integers / constants
always begin
if (rd_loops_a>=wr_loops_b) wr_adj = rd_loops_a/wr_loops_b;
else wr_adj = 1;
@(wr_loops_b or rd_loops_a);
end
always begin
if (((wr_loops_b>=rd_loops_a) && (output_stages==0)) ||
((wr_loops_b>=output_stages*rd_loops_a) && (output_stages>0)))
wrcount_adj = 1;
else if ((output_stages>1) ||
(FIRST_WORD_FALL_THROUGH_BIN == FIRST_WORD_FALL_THROUGH_TRUE))
wrcount_adj = output_stages*wr_adj;
else
wrcount_adj = 0;
if (RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_SIMPLE_DATACOUNT)
rdcount_adj = 0;
else if (RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_EXTENDED_DATACOUNT)
rdcount_adj = output_stages;
@(wr_adj or output_stages or wr_loops_b or rd_loops_a or FIRST_WORD_FALL_THROUGH_BIN or RDCOUNT_TYPE_BIN);
end
// reset logic
assign RDRSTBUSY_out = RDRST_int;
assign WRRSTBUSY_out = WRRST_int || WRRSTBUSY_dly;
assign mem_rst_a = RDRST_int;
// RST_in sampled by WRCLK cleared by WR done
always @ (posedge WRCLK_in) begin
if (RST_in && ~RST_sync) begin
RST_sync <= 1'b1;
end
else if (WRRST_done) begin
RST_sync <= 1'b0;
end
end
assign WRRST_done_wr = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? WRRST_int : WRRST_done;
always @ (posedge WRCLK_in) begin
if (RST_in && ~WRRSTBUSY_out) begin
WRRST_int <= #1 1'b1;
end
else if (WRRST_done_wr) begin
WRRST_int <= #1 1'b0;
end
end
// WRRST_int sampled by RDCLK twice => RDRST_int in CDI
assign RDRST_int = (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON) ? WRRST_int: WRRST_in_sync_rd;
always @ (posedge RDCLK_in) begin
if (glblGSR) begin
WRRST_in_sync_rd1 <= 1'b0;
WRRST_in_sync_rd <= 1'b0;
end
else begin
WRRST_in_sync_rd1 <= #1 WRRST_int;
WRRST_in_sync_rd <= #1 WRRST_in_sync_rd1;
end
end
// 3 rdclks to be done RD side
always @ (posedge RDCLK_in) begin
if (glblGSR || ~RDRST_int || (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON)) begin
RDRST_done2 <= 1'b0;
RDRST_done1 <= 1'b0;
RDRST_done <= 1'b0;
end
else begin
RDRST_done2 <= RDRST_int;
RDRST_done1 <= RDRST_done2;
RDRST_done <= RDRST_done1;
end
end
// 3 wrclks to be done WR side after RDRST_done
always @ (posedge WRCLK_in) begin
if (glblGSR || WRRST_done || (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON)) begin
WRRST_done2 <= 1'b0;
WRRST_done1 <= 1'b0;
WRRST_done <= 1'b0;
end
else if (WRRST_int) begin
WRRST_done2 <= RDRST_done;
WRRST_done1 <= WRRST_done2;
WRRST_done <= WRRST_done1;
end
end
// bug fix - 3 rd 2 wr. rtl verified
always @ (posedge RDCLK_in) begin
if (glblGSR || (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON)) begin
RDRSTBUSY_dly2 <= 1'b0;
RDRSTBUSY_dly1 <= 1'b0;
RDRSTBUSY_dly <= 1'b0;
end
else begin
RDRSTBUSY_dly2 <= RDRST_int;
RDRSTBUSY_dly1 <= RDRSTBUSY_dly2;
RDRSTBUSY_dly <= RDRSTBUSY_dly1;
end
end
always @ (posedge WRCLK_in) begin
if (glblGSR || (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON)) begin
WRRSTBUSY_dly1 <= 1'b0;
WRRSTBUSY_dly <= 1'b0;
end
else begin
WRRSTBUSY_dly1 <= RDRSTBUSY_dly;
WRRSTBUSY_dly <= WRRSTBUSY_dly1;
end
end
// cascade control
always @ (posedge RDCLK_in) begin
if (glblGSR) CASDOMUXA_reg <= 1'b0;
else CASDOMUXA_reg <= CASDOMUX_in; // EN tied to 1 in FIFO
end
always @ (posedge RDCLK_in) begin
if (glblGSR) CASOREGIMUXA_reg <= 1'b0;
else CASOREGIMUXA_reg <= CASOREGIMUX_in; // EN tied to 1 in FIFO
end
// output register
always @ (*) begin
if (((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) &&
CASOREGIMUXA_reg) mem_a_reg_mux = CASDIN_in;
else mem_a_reg_mux = mem_a_lat;
end
always @ (*) begin
if (((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) &&
CASOREGIMUXA_reg) memp_a_reg_mux = CASDINP_in;
else memp_a_reg_mux = memp_a_lat;
end
always @ (posedge RDCLK_in or posedge INIT_MEM or glblGSR) begin
if (glblGSR || INIT_MEM) begin
{memp_a_reg, mem_a_reg} <= #100 INIT_A_int;
end
else if (RSTREG_A_int) begin
{memp_a_reg, mem_a_reg} <= #100 SRVAL_A_int;
end
else if (REGCE_A_int) begin
mem_a_reg <= #100 mem_a_reg_mux;
memp_a_reg <= #100 memp_a_reg_mux;
end
end
wire fifo_cc_count;
assign fifo_cc_count = (WRITE_WIDTH_BIN==READ_WIDTH_BIN) && (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON);
// RDCOUNT sync to RDCLK
// assign rd_simple_raw = {1'b1, wr_addr_rd}-{1'b0, rd_addr_a};
assign rd_simple = {1'b1, wr_addr_rd}-{1'b0, rd_addr_a};
// assign rd_simple = rd_simple_raw[ADDR_WIDTH-1:0];
assign RDCOUNT_out =
(RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_RAW_PNTR) ? (rd_addr_a/(rd_loops_a)) :
(RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_SYNC_PNTR) ? (rd_addr_wr/(rd_loops_a)) :
(RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_SIMPLE_DATACOUNT) ? rd_simple_sync :
(RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_EXTENDED_DATACOUNT) && ~fifo_cc_count ? rd_simple_sync :
(RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_EXTENDED_DATACOUNT) && fifo_cc_count ? rd_simple_cc :
(rd_addr_a/rd_loops_a);
always @ (posedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int)
rd_simple_cc <= 0;
else if (fifo_cc_count)
if ((RDEN_int && ~EMPTY_out) && ~mem_wr_en_b)
rd_simple_cc <= rd_simple_cc - 1;
else if ((~RDEN_int || EMPTY_out) && mem_wr_en_b)
rd_simple_cc <= rd_simple_cc + 1;
end
always @ (posedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int)
rd_simple_sync <= 0;
else if (rdcount_en)
if (rd_simple[ADDR_WIDTH-1:0] == {ADDR_WIDTH-1{1'b0}})
rd_simple_sync <= {FULL_out, rd_simple[ADDR_WIDTH-2:0]}/rd_loops_a + rdcount_adj;
else
rd_simple_sync <= rd_simple[ADDR_WIDTH-1:0]/rd_loops_a + rdcount_adj;
end
// WRCOUNT sync to WRCLK
assign wr_simple_raw = {1'b1, wr_addr_b}-{1'b0,rd_addr_wr};
assign wr_simple = wr_simple_raw[ADDR_WIDTH-1:0];
assign WRCOUNT_out =
(WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_RAW_PNTR) ? wr_addr_b/wr_loops_b :
(WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_SYNC_PNTR) ? wr_addr_rd/wr_loops_b :
(WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_SIMPLE_DATACOUNT) ? wr_simple_sync :
(WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_EXTENDED_DATACOUNT) ? wr_simple_sync :
wr_addr_b/wr_loops_b;
always @ (posedge WRCLK_in or glblGSR) begin
if (glblGSR || WRRSTBUSY_out)
wr_simple_sync <= 0;
else if (WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_SIMPLE_DATACOUNT)
wr_simple_sync <= wr_simple/wr_loops_b;
else if (WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_EXTENDED_DATACOUNT)
wr_simple_sync <= (wr_simple/wr_loops_b) + wrcount_adj;
end
// with any output stage or FWFT fill the ouptut latch
// when ram not empty and o_latch empty
always @ (posedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int) begin
o_lat_empty <= 1;
end
else if (RDEN_lat) begin
o_lat_empty <= ram_empty;
end
else if (WREN_lat == 1) begin
o_lat_empty <= 0;
end
end
always @ (negedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int || SLEEP_A_int) begin
fill_lat <= 0;
end
else if (o_lat_empty == 1) begin
if (output_stages>0) begin
fill_lat <= ~ram_empty;
end
end
else begin
fill_lat <= 0;
end
end
// FWFT and
// REGISTERED fill the ouptut register when o_latch not empty.
// Empty on external read and prev stage also empty
always @ (posedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int) begin
o_reg_empty <= 1;
end
else if ((o_lat_empty == 0) && RDEN_reg) begin
o_reg_empty <= 0;
end
else if ((o_lat_empty == 1) && RDEN_reg) begin
o_reg_empty <= 1;
end
end
always @ (negedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int || SLEEP_A_int) begin
fill_reg <= 0;
end
else if ((o_lat_empty == 0) && (o_reg_empty == 1) &&
(output_stages==2)) begin
fill_reg <= 1;
end
else begin
fill_reg <= 0;
end
end
// read engine
always @ (rd_addr_a or mem_rd_en_a or mem_rst_a or wr_b_event or INIT_MEM) begin
if ((mem_rd_en_a || INIT_MEM) && ~mem_rst_a) begin
for (raa=0;raa<rd_loops_a;raa=raa+1) begin
ram_rd_a[raa] = mem [rd_addr_a+raa];
end
if (rd_loops_a >= 8) begin
for (raa=0;raa<rd_loops_a/8;raa=raa+1) begin
ramp_rd_a[raa] = memp [(rd_addr_a/8)+raa];
end
end
end
end
assign RDERR_out = rderr_reg;
always @ (posedge RDCLK_in or glblGSR) begin
if (glblGSR)
rderr_reg <= 1'b0;
else if (RDEN_int && (EMPTY_out || RDRST_int))
rderr_reg <= 1'b1;
else
rderr_reg <= 1'b0;
end
always @(posedge RDCLK_in or posedge INIT_MEM or posedge glblGSR) begin
if (glblGSR || INIT_MEM) begin
mem_is_rst_a <= 1'b0;
for (ra=0;ra<rd_loops_a;ra=ra+1) begin
mem_a_lat[ra] <= #100 INIT_A_int >> ra;
if (ra<rd_loops_a/8) begin
memp_a_lat[ra] <= #100 INIT_A_int >> (D_WIDTH+ra);
end
end
rdcount_en <= 1'b0;
end
else if (SLEEP_A_int && mem_rd_en_a) begin
$display("Error: [Unisim %s-23] DRC : READ on port A attempted while in SLEEP mode at time %.3f ns. Instance: %m.", MODULE_NAME, $time/1000.0);
mem_is_rst_a <= 1'b0;
for (ra=0;ra<rd_loops_a;ra=ra+1) begin
mem_a_lat[ra] <= #100 1'bx;
if (ra<rd_loops_a/8) begin
memp_a_lat[ra] <= #100 1'bx;
end
end
end
else if (mem_rst_a) begin
if (~mem_is_rst_a) begin
mem_is_rst_a <= 1'b1;
for (ra=0;ra<rd_loops_a;ra=ra+1) begin
mem_a_lat[ra] <= #100 SRVAL_A_int >> ra;
if (ra<rd_loops_a/8) begin
memp_a_lat[ra] <= #100 SRVAL_A_int >> (D_WIDTH+ra);
end
end
end
end
else if (WREN_lat) begin
mem_is_rst_a <= 1'b0;
mem_a_lat <= #100 ram_rd_a;
memp_a_lat <= #100 ramp_rd_a;
rdcount_en <= 1'b1;
end
else if (RDEN_int) begin
rdcount_en <= 1'b1;
end
end
always @ (posedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int) begin
rd_addr_a <= {ADDR_WIDTH-1{1'b0}};
rd_addr_a_wr <= {ADDR_WIDTH-1{1'b0}};
wr_addr_sync_rd2 <= {ADDR_WIDTH-1{1'b0}};
wr_addr_sync_rd1 <= {ADDR_WIDTH-1{1'b0}};
wr_addr_sync_rd <= {ADDR_WIDTH-1{1'b0}};
end
else begin
if (mem_rd_en_a) begin
rd_addr_a <= rd_addr_a + rd_loops_a;
end
rd_addr_a_wr <= rd_addr_a;
wr_addr_sync_rd2 <= wr_addr_b_rd;
wr_addr_sync_rd1 <= wr_addr_sync_rd2;
wr_addr_sync_rd <= wr_addr_sync_rd1;
end
end
// write engine
always @ (posedge WRCLK_in or posedge INIT_MEM) begin
if (INIT_MEM == 1'b1) begin
// initialize memory
for (i=0;i<mem_depth;i=i+1) begin
mem [i] <= 1'b0;
end
// initialize memory p
for (i=0;i<memp_depth;i=i+1) begin
memp [i] <= 1'b0;
end
end
else if (mem_wr_en_b && ~glblGSR) begin
if (SLEEP_B_int) begin
$display("Error: [Unisim %s-26] DRC : WRITE on port B attempted while in SLEEP mode at time %.3f ns. Instance: %m.", MODULE_NAME, $time/1000.0);
end
else begin
for (wb=0;wb<wr_loops_b;wb=wb+1) begin
mem [wr_addr_b+wb] <= mem_wr_b[wb];
end
if (WRITE_WIDTH_BIN > WRITE_WIDTH_4) begin
for (wb=0;wb<wr_loops_b/8;wb=wb+1) begin
memp [(wr_addr_b/8)+wb] <= memp_wr_b[wb];
end
end
wr_b_event <= ~wr_b_event;
end
end
end
assign mem_rm_douta = {D_WIDTH{1'b0}};
assign memp_rm_douta = {DP_WIDTH{1'b0}};
// assign mem_we_b = {{D_WIDTH{1'b1}}};
// assign memp_we_b = (WRITE_WIDTH_BIN > WRITE_WIDTH_4) ? {{DP_WIDTH{1'b1}}} : {{DP_WIDTH{1'b0}}};
assign WRERR_out = wrerr_reg;
always @ (posedge WRCLK_in or glblGSR) begin
if (glblGSR)
wrerr_reg <= 1'b0;
else if (WREN_int && (FULL_out || WRRSTBUSY_out))
wrerr_reg <= 1'b1;
else
wrerr_reg <= 1'b0;
end
always @ (posedge WRCLK_in or glblGSR) begin
if (glblGSR || WRRSTBUSY_out) begin
wr_addr_b <= {ADDR_WIDTH-1{1'b0}};
wr_addr_b_rd <= {ADDR_WIDTH-1{1'b0}};
o_stages_full_sync2 <= 1'b0;
o_stages_full_sync1 <= 1'b0;
o_stages_full_sync <= 1'b0;
rd_addr_sync_wr2 <= {ADDR_WIDTH-1{1'b0}};
rd_addr_sync_wr1 <= {ADDR_WIDTH-1{1'b0}};
rd_addr_sync_wr <= {ADDR_WIDTH-1{1'b0}};
end
else begin
if (mem_wr_en_b) begin
wr_addr_b <= wr_addr_b + wr_loops_b;
end
wr_addr_b_rd <= wr_addr_b;
o_stages_full_sync2 <= ~o_stages_empty;
o_stages_full_sync1 <= o_stages_full_sync2;
o_stages_full_sync <= o_stages_full_sync1;
rd_addr_sync_wr2 <= rd_addr_a_wr;
rd_addr_sync_wr1 <= rd_addr_sync_wr2;
rd_addr_sync_wr <= rd_addr_sync_wr1;
end
end
// full flag
assign prog_full = ((full_count_masked <= prog_full_val) && ((full_count > 0) || FULL_out));
assign prog_full_val = mem_depth - (PROG_FULL_THRESH_BIN * wr_loops_b) + m_full;
assign unr_ratio = (wr_loops_b>=rd_loops_a) ? wr_loops_b/rd_loops_a - 1 : 0;
assign m_full = (output_stages == 0) ? 0 : ((((m_full_raw-1)/wr_loops_b)+1)*wr_loops_b);
assign m_full_raw = output_stages*rd_loops_a;
assign n_empty = output_stages;
assign prog_empty_val = (PROG_EMPTY_THRESH_BIN - n_empty + 1)*rd_loops_a;
assign full_count_masked = full_count & wr_addr_b_mask;
assign full_count = {1'b1, rd_addr_wr} - {1'b0, wr_addr_b};
assign next_full_count = {1'b1, next_rd_addr_wr} - {1'b0, next_wr_addr_rd};
assign FULL_out = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? ram_full_c : ram_full_i;
// ram_full independent clocks is one_from_full common clocks
assign ram_one_from_full_i = ((full_count < 2*wr_loops_b) && (full_count > 0));
assign ram_two_from_full_i = ((full_count < 3*wr_loops_b) && (full_count > 0));
assign ram_one_from_full = (next_full_count < wr_loops_b) && ~ram_full_c;
assign ram_two_from_full = (next_full_count < 2*wr_loops_b) && ~ram_full_c;
// when full common clocks, next read makes it not full
// assign ram_one_read_from_not_full = ((full_count + rd_loops_a >= wr_loops_b) && ram_full_c);
assign ram_one_read_from_not_full = (next_full_count >= wr_loops_b) && ram_full_c;
always @ (posedge WRCLK_in or glblGSR) begin
if (glblGSR || WRRSTBUSY_out) begin
ram_full_c <= 1'b0;
end
else if (mem_wr_en_b &&
(mem_rd_en_a && (rd_loops_a < wr_loops_b)) &&
ram_one_from_full) begin
ram_full_c <= 1'b1;
end
else if (mem_wr_en_b && ~mem_rd_en_a && ram_one_from_full) begin
ram_full_c <= 1'b1;
end
else if (mem_rd_en_a && ram_one_read_from_not_full) begin
ram_full_c <= 1'b0;
end
else begin
ram_full_c <= ram_full_c;
end
end
always @ (posedge WRCLK_in or glblGSR) begin
if (glblGSR || WRRSTBUSY_out) begin
ram_full_i <= 1'b0;
end
else if (mem_wr_en_b && ram_two_from_full_i && ~ram_full_i) begin
ram_full_i <= 1'b1;
end
else if (~ram_one_from_full_i) begin
ram_full_i <= 1'b0;
end
else begin
ram_full_i <= ram_full_i;
end
end
assign PROGFULL_out = prog_full_reg;
always @ (posedge WRCLK_in or glblGSR) begin
if (glblGSR || WRRSTBUSY_out) begin
prog_full_reg <= 1'b0;
end
else begin
prog_full_reg <= prog_full;
end
end
// empty flag
assign empty_count = {1'b1, wr_addr_rd} - {1'b0, rd_addr_a};
assign next_empty_count = {1'b1, next_wr_addr_rd} - {1'b0, next_rd_addr_wr};
assign EMPTY_out = o_stages_empty;
assign ram_empty = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? ram_empty_c : ram_empty_i;
assign ram_one_read_from_empty_i = (empty_count < 2*rd_loops_a) && (empty_count >= rd_loops_a) && ~ram_empty;
assign ram_one_read_from_empty = (next_empty_count < rd_loops_a) && ~ram_empty;
assign ram_one_write_from_not_empty = (next_empty_count >= rd_loops_a) && ram_empty;
assign ram_one_write_from_not_empty_i = (rd_loops_a < wr_loops_b) ? EMPTY_out : ((empty_count + wr_loops_b) >= rd_loops_a);
assign prog_empty = ((empty_count < prog_empty_val) || (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON && ram_empty)) && (~FULL_out || (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_INDEPENDENT));
always @ (posedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int)
ram_empty_c <= 1'b1;
// RD only makes empty
else if (~mem_wr_en_b &&
mem_rd_en_a &&
(ram_one_read_from_empty || ram_empty_c))
ram_empty_c <= 1'b1;
// RD and WR when one read from empty and RD more than WR makes empty
else if (mem_wr_en_b &&
(mem_rd_en_a && (rd_loops_a > wr_loops_b)) &&
(ram_one_read_from_empty || ram_empty_c))
ram_empty_c <= 1'b1;
// CR701309 CC WR when empty always makes not empty. simultaneous RD gets ERR
else if ( mem_wr_en_b && (ram_one_write_from_not_empty && ram_empty_c))
ram_empty_c <= 1'b0;
else
ram_empty_c <= ram_empty_c;
end
always @ (posedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int)
ram_empty_i <= 1'b1;
else if (mem_rd_en_a && ram_one_read_from_empty_i) // RDEN_in ?
ram_empty_i <= 1'b1;
else if (empty_count < rd_loops_a)
ram_empty_i <= 1'b1;
else
ram_empty_i <= 1'b0;
end
// assign PROGEMPTY_out = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? prog_empty_cc : prog_empty;
assign PROGEMPTY_out = prog_empty_cc;
always @ (posedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int)
prog_empty_cc <= 1'b1;
else
prog_empty_cc <= prog_empty;
end
`ifdef XIL_TIMING
reg notifier;
wire rdclk_en_n;
wire rdclk_en_p;
wire wrclk_en_n;
wire wrclk_en_p;
assign rdclk_en_n = IS_RDCLK_INVERTED_BIN;
assign rdclk_en_p = ~IS_RDCLK_INVERTED_BIN;
assign wrclk_en_n = IS_WRCLK_INVERTED_BIN;
assign wrclk_en_p = ~IS_WRCLK_INVERTED_BIN;
`endif
specify
(CASDIN *> CASDOUT) = (0:0:0, 0:0:0);
(CASDIN *> DOUT) = (0:0:0, 0:0:0);
(CASDINP *> CASDOUTP) = (0:0:0, 0:0:0);
(CASDINP *> DOUTP) = (0:0:0, 0:0:0);
(CASPRVEMPTY => CASPRVRDEN) = (0:0:0, 0:0:0);
(RDCLK *> CASDOUT) = (100:100:100, 100:100:100);
(RDCLK *> CASDOUTP) = (100:100:100, 100:100:100);
(RDCLK *> DOUT) = (100:100:100, 100:100:100);
(RDCLK *> DOUTP) = (100:100:100, 100:100:100);
(RDCLK *> RDCOUNT) = (100:100:100, 100:100:100);
(RDCLK *> WRCOUNT) = (100:100:100, 100:100:100);
(RDCLK => CASNXTEMPTY) = (100:100:100, 100:100:100);
(RDCLK => EMPTY) = (100:100:100, 100:100:100);
(RDCLK => PROGEMPTY) = (100:100:100, 100:100:100);
(RDCLK => RDERR) = (100:100:100, 100:100:100);
(RDCLK => RDRSTBUSY) = (100:100:100, 100:100:100);
(WRCLK *> CASDOUT) = (100:100:100, 100:100:100);
(WRCLK *> CASDOUTP) = (100:100:100, 100:100:100);
(WRCLK *> DOUT) = (100:100:100, 100:100:100);
(WRCLK *> DOUTP) = (100:100:100, 100:100:100);
(WRCLK *> RDCOUNT) = (100:100:100, 100:100:100);
(WRCLK *> WRCOUNT) = (100:100:100, 100:100:100);
(WRCLK => CASPRVRDEN) = (100:100:100, 100:100:100);
(WRCLK => FULL) = (100:100:100, 100:100:100);
(WRCLK => PROGFULL) = (100:100:100, 100:100:100);
(WRCLK => RDRSTBUSY) = (100:100:100, 100:100:100);
(WRCLK => WRERR) = (100:100:100, 100:100:100);
(WRCLK => WRRSTBUSY) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge RDCLK, 0:0:0, notifier);
$period (negedge WRCLK, 0:0:0, notifier);
$period (posedge RDCLK, 0:0:0, notifier);
$period (posedge WRCLK, 0:0:0, notifier);
$setuphold (negedge RDCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDIN_delay);
$setuphold (negedge RDCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDINP_delay);
$setuphold (negedge RDCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDOMUX_delay);
$setuphold (negedge RDCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDOMUXEN_delay);
$setuphold (negedge RDCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASNXTRDEN_delay);
$setuphold (negedge RDCLK, negedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASOREGIMUX_delay);
$setuphold (negedge RDCLK, negedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASOREGIMUXEN_delay);
$setuphold (negedge RDCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASPRVEMPTY_delay);
$setuphold (negedge RDCLK, negedge DIN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, DIN_delay);
$setuphold (negedge RDCLK, negedge DINP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, DINP_delay);
$setuphold (negedge RDCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, RDEN_delay);
$setuphold (negedge RDCLK, negedge REGCE, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, REGCE_delay);
$setuphold (negedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, RSTREG_delay);
$setuphold (negedge RDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, SLEEP_delay);
$setuphold (negedge RDCLK, negedge WREN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, WREN_delay);
$setuphold (negedge RDCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDIN_delay);
$setuphold (negedge RDCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDINP_delay);
$setuphold (negedge RDCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDOMUX_delay);
$setuphold (negedge RDCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDOMUXEN_delay);
$setuphold (negedge RDCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASNXTRDEN_delay);
$setuphold (negedge RDCLK, posedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASOREGIMUX_delay);
$setuphold (negedge RDCLK, posedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASOREGIMUXEN_delay);
$setuphold (negedge RDCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASPRVEMPTY_delay);
$setuphold (negedge RDCLK, posedge DIN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, DIN_delay);
$setuphold (negedge RDCLK, posedge DINP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, DINP_delay);
$setuphold (negedge RDCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, RDEN_delay);
$setuphold (negedge RDCLK, posedge REGCE, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, REGCE_delay);
$setuphold (negedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, RSTREG_delay);
$setuphold (negedge RDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, SLEEP_delay);
$setuphold (negedge RDCLK, posedge WREN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, WREN_delay);
$setuphold (negedge WRCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDIN_delay);
$setuphold (negedge WRCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDINP_delay);
$setuphold (negedge WRCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDOMUX_delay);
$setuphold (negedge WRCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDOMUXEN_delay);
$setuphold (negedge WRCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASNXTRDEN_delay);
$setuphold (negedge WRCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASPRVEMPTY_delay);
$setuphold (negedge WRCLK, negedge DIN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, DIN_delay);
$setuphold (negedge WRCLK, negedge DINP, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, DINP_delay);
$setuphold (negedge WRCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, RDEN_delay);
$setuphold (negedge WRCLK, negedge RST, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, RST_delay);
$setuphold (negedge WRCLK, negedge WREN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, WREN_delay);
$setuphold (negedge WRCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDIN_delay);
$setuphold (negedge WRCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDINP_delay);
$setuphold (negedge WRCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDOMUX_delay);
$setuphold (negedge WRCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDOMUXEN_delay);
$setuphold (negedge WRCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASNXTRDEN_delay);
$setuphold (negedge WRCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASPRVEMPTY_delay);
$setuphold (negedge WRCLK, posedge DIN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, DIN_delay);
$setuphold (negedge WRCLK, posedge DINP, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, DINP_delay);
$setuphold (negedge WRCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, RDEN_delay);
$setuphold (negedge WRCLK, posedge RST, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, RST_delay);
$setuphold (negedge WRCLK, posedge WREN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, WREN_delay);
$setuphold (posedge RDCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDIN_delay);
$setuphold (posedge RDCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDINP_delay);
$setuphold (posedge RDCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDOMUX_delay);
$setuphold (posedge RDCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDOMUXEN_delay);
$setuphold (posedge RDCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASNXTRDEN_delay);
$setuphold (posedge RDCLK, negedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASOREGIMUX_delay);
$setuphold (posedge RDCLK, negedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASOREGIMUXEN_delay);
$setuphold (posedge RDCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASPRVEMPTY_delay);
$setuphold (posedge RDCLK, negedge DIN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, DIN_delay);
$setuphold (posedge RDCLK, negedge DINP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, DINP_delay);
$setuphold (posedge RDCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, RDEN_delay);
$setuphold (posedge RDCLK, negedge REGCE, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, REGCE_delay);
$setuphold (posedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, RSTREG_delay);
$setuphold (posedge RDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, SLEEP_delay);
$setuphold (posedge RDCLK, negedge WREN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, WREN_delay);
$setuphold (posedge RDCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDIN_delay);
$setuphold (posedge RDCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDINP_delay);
$setuphold (posedge RDCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDOMUX_delay);
$setuphold (posedge RDCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDOMUXEN_delay);
$setuphold (posedge RDCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASNXTRDEN_delay);
$setuphold (posedge RDCLK, posedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASOREGIMUX_delay);
$setuphold (posedge RDCLK, posedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASOREGIMUXEN_delay);
$setuphold (posedge RDCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASPRVEMPTY_delay);
$setuphold (posedge RDCLK, posedge DIN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, DIN_delay);
$setuphold (posedge RDCLK, posedge DINP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, DINP_delay);
$setuphold (posedge RDCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, RDEN_delay);
$setuphold (posedge RDCLK, posedge REGCE, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, REGCE_delay);
$setuphold (posedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, RSTREG_delay);
$setuphold (posedge RDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, SLEEP_delay);
$setuphold (posedge RDCLK, posedge WREN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, WREN_delay);
$setuphold (posedge WRCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDIN_delay);
$setuphold (posedge WRCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDINP_delay);
$setuphold (posedge WRCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDOMUX_delay);
$setuphold (posedge WRCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDOMUXEN_delay);
$setuphold (posedge WRCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASNXTRDEN_delay);
$setuphold (posedge WRCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASPRVEMPTY_delay);
$setuphold (posedge WRCLK, negedge DIN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, DIN_delay);
$setuphold (posedge WRCLK, negedge DINP, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, DINP_delay);
$setuphold (posedge WRCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, RDEN_delay);
$setuphold (posedge WRCLK, negedge RST, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, RST_delay);
$setuphold (posedge WRCLK, negedge WREN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, WREN_delay);
$setuphold (posedge WRCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDIN_delay);
$setuphold (posedge WRCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDINP_delay);
$setuphold (posedge WRCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDOMUX_delay);
$setuphold (posedge WRCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDOMUXEN_delay);
$setuphold (posedge WRCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASNXTRDEN_delay);
$setuphold (posedge WRCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASPRVEMPTY_delay);
$setuphold (posedge WRCLK, posedge DIN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, DIN_delay);
$setuphold (posedge WRCLK, posedge DINP, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, DINP_delay);
$setuphold (posedge WRCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, RDEN_delay);
$setuphold (posedge WRCLK, posedge RST, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, RST_delay);
$setuphold (posedge WRCLK, posedge WREN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, WREN_delay);
$width (negedge RDCLK, 0:0:0, 0, notifier);
$width (negedge WRCLK, 0:0:0, 0, notifier);
$width (posedge RDCLK, 0:0:0, 0, notifier);
$width (posedge WRCLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAP_1_V
`define SKY130_FD_SC_LS__TAP_1_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog wrapper for tap with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__tap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__tap_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__tap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__tap_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__tap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAP_1_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_bs_fsdq_2x.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// bw_io_bs_fsdq_2x
// _____________________________________________________________________________
//
module bw_io_bs_fsdq_2x (/*AUTOARG*/
// Outputs
q,
// Inputs
d, up_dr
);
output [2:0] q;
input [2:0] d;
input up_dr;
supply1 vdd;
bw_u1_scanlg_2x Iq0 (
.so (q[0]),
.sd (d[0]),
.ck (up_dr),
.se (vdd)
);
bw_u1_scanlg_2x Iq1 (
.so (q[1]),
.sd (d[1]),
.ck (up_dr),
.se (vdd)
);
bw_u1_scanlg_2x Iq2 (
.so (q[2]),
.sd (d[2]),
.ck (up_dr),
.se (vdd)
);
endmodule
// Local Variables:
// verilog-auto-sense-defines-constant:t
// End:
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 16:59:27 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25,
n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39,
n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53,
n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67,
n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81,
n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95,
n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107,
n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118,
n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129,
n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, n140,
n141, n142, n143, n144, n145, n146, n147, n148, n149, n150, n151,
n152, n153, n154, n155, n156, n157, n158, n159, n160, n161, n162,
n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, n173,
n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, n184,
n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195,
n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206,
n207, n208, n209, n210, n211, n212, n213, n214, n215, n216, n217,
n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228,
n229, n230, n231, n232, n233, n234, n235, n236, n237, n238, n239,
n240, n241, n242, n243, n244, n245, n246, n247, n248, n249, n250,
n251, n252, n253, n254, n255, n256, n257, n258, n259, n260, n261,
n262, n263, n264, n265, n266, n267, n268, n269, n270, n271, n272,
n273, n274, n275, n276, n277, n278, n279, n280, n281, n282, n283,
n284, n285, n286, n287, n288, n289, n290, n291, n292, n293, n294,
n295, n296, n297, n298, n299, n300, n301, n302, n303, n304, n305,
n306, n307, n308, n309;
NAND2X1TS U46 ( .A(n45), .B(n195), .Y(n196) );
NAND2X1TS U47 ( .A(n44), .B(n187), .Y(n188) );
NAND2X1TS U48 ( .A(n43), .B(n191), .Y(n192) );
NAND2X1TS U49 ( .A(n223), .B(n222), .Y(n224) );
NAND2X1TS U50 ( .A(n216), .B(n215), .Y(n217) );
NAND2X1TS U51 ( .A(n209), .B(n208), .Y(n210) );
NAND2XLTS U52 ( .A(n42), .B(n161), .Y(n158) );
OAI21X1TS U53 ( .A0(n241), .A1(n237), .B0(n238), .Y(n236) );
CLKINVX1TS U54 ( .A(n221), .Y(n223) );
OR2X2TS U55 ( .A(n170), .B(in1[31]), .Y(n169) );
CLKMX2X2TS U56 ( .A(in2[31]), .B(n168), .S0(add_sub), .Y(n170) );
NAND2X1TS U57 ( .A(n296), .B(n295), .Y(n305) );
BUFX6TS U58 ( .A(n179), .Y(n180) );
AND2X4TS U59 ( .A(n150), .B(n37), .Y(n31) );
CLKMX2X2TS U60 ( .A(in2[30]), .B(n156), .S0(n20), .Y(n157) );
MX2X1TS U61 ( .A(in2[29]), .B(n153), .S0(add_sub), .Y(n154) );
CLKINVX2TS U62 ( .A(n126), .Y(n37) );
NOR2X1TS U63 ( .A(n166), .B(in2[30]), .Y(n167) );
NOR2X4TS U64 ( .A(n214), .B(n207), .Y(n124) );
OAI21X2TS U65 ( .A0(n215), .A1(n207), .B0(n208), .Y(n123) );
NOR2X2TS U66 ( .A(n119), .B(in1[21]), .Y(n219) );
NAND2X2TS U67 ( .A(n142), .B(in1[26]), .Y(n195) );
CLKMX2X2TS U68 ( .A(in2[18]), .B(n15), .S0(add_sub), .Y(n91) );
NAND2X4TS U69 ( .A(n119), .B(in1[21]), .Y(n226) );
MX2X2TS U70 ( .A(in2[28]), .B(n136), .S0(n20), .Y(n146) );
NOR2X6TS U71 ( .A(n121), .B(in1[23]), .Y(n214) );
MXI2X2TS U72 ( .A(n99), .B(n98), .S0(n19), .Y(n101) );
OR2X2TS U73 ( .A(n73), .B(in1[14]), .Y(n46) );
NOR2X2TS U74 ( .A(n152), .B(n137), .Y(n138) );
NAND2X2TS U75 ( .A(n73), .B(in1[14]), .Y(n265) );
XOR2X1TS U76 ( .A(n78), .B(in2[15]), .Y(n79) );
NAND2X1TS U77 ( .A(n134), .B(n133), .Y(n137) );
NOR2X1TS U78 ( .A(in2[25]), .B(in2[24]), .Y(n134) );
OR2X2TS U79 ( .A(in2[21]), .B(in2[20]), .Y(n111) );
NAND2X1TS U80 ( .A(n301), .B(in2[10]), .Y(n47) );
INVX4TS U81 ( .A(n14), .Y(n292) );
NOR2X1TS U82 ( .A(in2[19]), .B(in2[18]), .Y(n96) );
XOR2X2TS U83 ( .A(n77), .B(in2[12]), .Y(n64) );
NOR2X2TS U84 ( .A(in2[17]), .B(in2[16]), .Y(n97) );
NAND2X4TS U85 ( .A(n77), .B(n67), .Y(n68) );
CLKINVX6TS U86 ( .A(add_sub), .Y(n301) );
INVX3TS U87 ( .A(n60), .Y(n23) );
NOR2X6TS U88 ( .A(in2[3]), .B(in2[5]), .Y(n22) );
NOR2X6TS U89 ( .A(in2[4]), .B(in2[2]), .Y(n21) );
INVX8TS U90 ( .A(in2[7]), .Y(n27) );
CLKINVX6TS U91 ( .A(in2[6]), .Y(n28) );
CLKINVX6TS U92 ( .A(in2[8]), .Y(n25) );
XNOR2X2TS U93 ( .A(n130), .B(n132), .Y(n131) );
INVX12TS U94 ( .A(in2[0]), .Y(n29) );
INVX12TS U95 ( .A(in2[1]), .Y(n30) );
NOR2X1TS U96 ( .A(n289), .B(in2[4]), .Y(n296) );
OAI21XLTS U97 ( .A0(n288), .A1(n308), .B0(n287), .Y(res[5]) );
INVX2TS U98 ( .A(n232), .Y(n234) );
NOR2X4TS U99 ( .A(n250), .B(n248), .Y(n90) );
XNOR2X2TS U100 ( .A(n128), .B(in2[26]), .Y(n129) );
INVX2TS U101 ( .A(n12), .Y(n41) );
NAND2BX2TS U102 ( .AN(in2[29]), .B(n155), .Y(n166) );
NAND2X4TS U103 ( .A(n150), .B(n36), .Y(n35) );
AOI21X2TS U104 ( .A0(n42), .A1(n163), .B0(n162), .Y(n164) );
NAND2X2TS U105 ( .A(n42), .B(n176), .Y(n165) );
INVX2TS U106 ( .A(n214), .Y(n216) );
INVX2TS U107 ( .A(n175), .Y(n163) );
INVX2TS U108 ( .A(n187), .Y(n147) );
NAND2X1TS U109 ( .A(n234), .B(n233), .Y(n235) );
OR2X6TS U110 ( .A(n146), .B(in1[28]), .Y(n44) );
NAND2X4TS U111 ( .A(n141), .B(in1[25]), .Y(n198) );
MXI2X4TS U112 ( .A(n132), .B(n131), .S0(n20), .Y(n141) );
NOR2X4TS U113 ( .A(n152), .B(n151), .Y(n135) );
NOR2X2TS U114 ( .A(n92), .B(in2[18]), .Y(n93) );
NOR4X2TS U115 ( .A(n106), .B(n111), .C(in2[23]), .D(in2[22]), .Y(n107) );
BUFX8TS U116 ( .A(n301), .Y(n308) );
INVX12TS U117 ( .A(n180), .Y(n201) );
XNOR2X1TS U118 ( .A(n236), .B(n235), .Y(res[20]) );
INVX8TS U119 ( .A(n32), .Y(n174) );
XOR2X1TS U120 ( .A(n241), .B(n240), .Y(res[19]) );
XOR2X1TS U121 ( .A(n254), .B(n253), .Y(res[17]) );
NAND2X2TS U122 ( .A(n170), .B(in1[31]), .Y(n172) );
OR2X6TS U123 ( .A(n142), .B(in1[26]), .Y(n45) );
NOR2X4TS U124 ( .A(n237), .B(n232), .Y(n102) );
XOR2X1TS U125 ( .A(n271), .B(n270), .Y(res[13]) );
NOR2X4TS U126 ( .A(n141), .B(in1[25]), .Y(n194) );
OR2X6TS U127 ( .A(n145), .B(in1[27]), .Y(n43) );
NAND2X4TS U128 ( .A(n273), .B(n40), .Y(n39) );
MXI2X4TS U129 ( .A(n133), .B(n129), .S0(n20), .Y(n142) );
XNOR2X2TS U130 ( .A(n103), .B(n105), .Y(n104) );
INVX2TS U131 ( .A(n265), .Y(n74) );
OAI21X1TS U132 ( .A0(n309), .A1(n308), .B0(n307), .Y(res[7]) );
XOR2X1TS U133 ( .A(n92), .B(in2[18]), .Y(n15) );
NOR2X4TS U134 ( .A(n152), .B(in2[24]), .Y(n130) );
XNOR2X2TS U135 ( .A(n152), .B(in2[24]), .Y(n109) );
MX2X2TS U136 ( .A(in2[15]), .B(n79), .S0(add_sub), .Y(n80) );
OAI21XLTS U137 ( .A0(n294), .A1(n308), .B0(n293), .Y(res[9]) );
OAI21X1TS U138 ( .A0(n298), .A1(n301), .B0(n297), .Y(res[6]) );
NOR2X1TS U139 ( .A(n305), .B(in2[6]), .Y(n306) );
NAND3X1TS U140 ( .A(n77), .B(n76), .C(n75), .Y(n78) );
OAI21XLTS U141 ( .A0(n302), .A1(n301), .B0(n300), .Y(res[8]) );
OAI21XLTS U142 ( .A0(n291), .A1(n301), .B0(n290), .Y(res[4]) );
OAI21XLTS U143 ( .A0(n281), .A1(n308), .B0(n280), .Y(res[3]) );
OAI21XLTS U144 ( .A0(n284), .A1(n301), .B0(n283), .Y(res[2]) );
OAI21XLTS U145 ( .A0(n304), .A1(n308), .B0(n303), .Y(res[1]) );
NAND2X2TS U146 ( .A(n97), .B(n96), .Y(n106) );
OR2X1TS U147 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
NOR2X4TS U148 ( .A(n65), .B(in1[12]), .Y(n12) );
NOR3X6TS U149 ( .A(n299), .B(in2[10]), .C(n60), .Y(n57) );
INVX12TS U150 ( .A(in2[9]), .Y(n24) );
XNOR2X4TS U151 ( .A(n13), .B(in2[10]), .Y(n48) );
NAND3X4TS U152 ( .A(n49), .B(n23), .C(n50), .Y(n13) );
NAND3X4TS U153 ( .A(n53), .B(in1[9]), .C(n52), .Y(n54) );
OR2X4TS U154 ( .A(n299), .B(in2[8]), .Y(n14) );
NOR2X8TS U155 ( .A(n267), .B(n12), .Y(n40) );
MXI2X4TS U156 ( .A(n75), .B(n72), .S0(n20), .Y(n73) );
NAND2X8TS U157 ( .A(n71), .B(n76), .Y(n81) );
OAI2BB1X4TS U158 ( .A0N(n34), .A1N(n31), .B0(n33), .Y(n32) );
NAND2X2TS U159 ( .A(n127), .B(n134), .Y(n128) );
MX2X4TS U160 ( .A(n58), .B(in2[11]), .S0(n308), .Y(n59) );
NOR2X6TS U161 ( .A(n120), .B(in1[22]), .Y(n221) );
XNOR2X4TS U162 ( .A(n116), .B(n118), .Y(n117) );
NAND3X6TS U163 ( .A(n39), .B(n268), .C(n38), .Y(n264) );
NAND2X4TS U164 ( .A(n59), .B(in1[11]), .Y(n276) );
OAI21X4TS U165 ( .A0(n48), .A1(n308), .B0(n47), .Y(n56) );
NAND2X8TS U166 ( .A(n108), .B(n107), .Y(n152) );
NAND2X2TS U167 ( .A(n91), .B(in1[18]), .Y(n244) );
MXI2X4TS U168 ( .A(n86), .B(n85), .S0(n20), .Y(n87) );
XOR2X2TS U169 ( .A(n108), .B(in2[16]), .Y(n85) );
NAND2X4TS U170 ( .A(n124), .B(n213), .Y(n126) );
OAI21X4TS U171 ( .A0(n174), .A1(n160), .B0(n175), .Y(n159) );
NAND2X4TS U172 ( .A(n65), .B(in1[12]), .Y(n272) );
CLKINVX6TS U173 ( .A(n272), .Y(n66) );
NOR2X2TS U174 ( .A(n91), .B(in1[18]), .Y(n243) );
BUFX12TS U175 ( .A(n71), .Y(n77) );
INVX8TS U176 ( .A(n34), .Y(n202) );
MXI2X4TS U177 ( .A(n84), .B(n83), .S0(add_sub), .Y(n88) );
XOR2X4TS U178 ( .A(n82), .B(in2[17]), .Y(n83) );
OA21X4TS U179 ( .A0(n182), .A1(n149), .B0(n148), .Y(n17) );
OAI21X2TS U180 ( .A0(n202), .A1(n126), .B0(n125), .Y(n179) );
NOR2X4TS U181 ( .A(in2[11]), .B(in2[10]), .Y(n61) );
NOR3X4TS U182 ( .A(n115), .B(in2[22]), .C(n111), .Y(n103) );
NAND2X2TS U183 ( .A(n169), .B(n172), .Y(n171) );
OA21X4TS U184 ( .A0(n238), .A1(n232), .B0(n233), .Y(n16) );
NAND2X2TS U185 ( .A(n101), .B(in1[20]), .Y(n233) );
MXI2X4TS U186 ( .A(n105), .B(n104), .S0(add_sub), .Y(n121) );
NAND2X2TS U187 ( .A(n70), .B(in1[13]), .Y(n268) );
INVX2TS U188 ( .A(n152), .Y(n127) );
NOR2X2TS U189 ( .A(n87), .B(in1[16]), .Y(n248) );
INVX2TS U190 ( .A(n191), .Y(n183) );
INVX2TS U191 ( .A(in2[3]), .Y(n286) );
INVX2TS U192 ( .A(in2[5]), .Y(n295) );
NOR2X2TS U193 ( .A(n80), .B(in1[15]), .Y(n259) );
NAND2X2TS U194 ( .A(n80), .B(in1[15]), .Y(n260) );
NAND2X2TS U195 ( .A(n87), .B(in1[16]), .Y(n255) );
INVX2TS U196 ( .A(n248), .Y(n256) );
CLKBUFX2TS U197 ( .A(n247), .Y(n258) );
NAND2X4TS U198 ( .A(n120), .B(in1[22]), .Y(n222) );
NAND2X4TS U199 ( .A(n121), .B(in1[23]), .Y(n215) );
INVX2TS U200 ( .A(n194), .Y(n199) );
NAND2X2TS U201 ( .A(n145), .B(in1[27]), .Y(n191) );
NAND2X4TS U202 ( .A(n45), .B(n199), .Y(n190) );
INVX2TS U203 ( .A(n195), .Y(n143) );
INVX2TS U204 ( .A(n198), .Y(n144) );
NAND2X2TS U205 ( .A(n146), .B(in1[28]), .Y(n187) );
INVX2TS U206 ( .A(n190), .Y(n181) );
AOI21X1TS U207 ( .A0(n184), .A1(n43), .B0(n183), .Y(n185) );
INVX2TS U208 ( .A(n182), .Y(n184) );
INVX2TS U209 ( .A(in2[12]), .Y(n67) );
NOR2X2TS U210 ( .A(in2[13]), .B(in2[12]), .Y(n76) );
NAND2X4TS U211 ( .A(n43), .B(n44), .Y(n149) );
AND2X2TS U212 ( .A(n108), .B(n86), .Y(n82) );
XNOR2X1TS U213 ( .A(n115), .B(in2[20]), .Y(n98) );
MXI2X4TS U214 ( .A(n118), .B(n117), .S0(n20), .Y(n119) );
MXI2X4TS U215 ( .A(n114), .B(n113), .S0(n19), .Y(n120) );
XNOR2X2TS U216 ( .A(n112), .B(n114), .Y(n113) );
XOR2X1TS U217 ( .A(n166), .B(in2[30]), .Y(n156) );
NOR2X4TS U218 ( .A(n190), .B(n149), .Y(n150) );
INVX2TS U219 ( .A(n161), .Y(n162) );
NAND3X2TS U220 ( .A(n299), .B(n19), .C(in2[9]), .Y(n53) );
AO22X1TS U221 ( .A0(n19), .A1(n24), .B0(n51), .B1(in2[9]), .Y(n52) );
NOR2X4TS U222 ( .A(n88), .B(in1[17]), .Y(n250) );
INVX2TS U223 ( .A(n255), .Y(n249) );
NAND2X2TS U224 ( .A(n88), .B(in1[17]), .Y(n251) );
NOR2X4TS U225 ( .A(n101), .B(in1[20]), .Y(n232) );
INVX2TS U226 ( .A(n231), .Y(n241) );
CLKBUFX2TS U227 ( .A(n230), .Y(n231) );
INVX2TS U228 ( .A(n219), .Y(n227) );
INVX2TS U229 ( .A(n226), .Y(n220) );
NOR2X4TS U230 ( .A(n221), .B(n219), .Y(n213) );
NOR2X4TS U231 ( .A(n122), .B(in1[24]), .Y(n207) );
OAI21X1TS U232 ( .A0(n204), .A1(n214), .B0(n215), .Y(n205) );
NOR2X1TS U233 ( .A(n203), .B(n214), .Y(n206) );
INVX2TS U234 ( .A(n213), .Y(n203) );
NAND2X2TS U235 ( .A(n122), .B(in1[24]), .Y(n208) );
INVX2TS U236 ( .A(n202), .Y(n229) );
INVX2TS U237 ( .A(n160), .Y(n176) );
NAND2X2TS U238 ( .A(n157), .B(in1[30]), .Y(n161) );
NOR2X2TS U239 ( .A(n154), .B(in1[29]), .Y(n160) );
NAND2X2TS U240 ( .A(n154), .B(in1[29]), .Y(n175) );
OR2X2TS U241 ( .A(n157), .B(in1[30]), .Y(n42) );
NAND2X1TS U242 ( .A(n277), .B(n276), .Y(n279) );
INVX2TS U243 ( .A(n275), .Y(n277) );
NAND2X1TS U244 ( .A(n41), .B(n272), .Y(n274) );
NAND2X1TS U245 ( .A(n269), .B(n268), .Y(n271) );
INVX2TS U246 ( .A(n267), .Y(n269) );
NAND2X1TS U247 ( .A(n46), .B(n265), .Y(n266) );
NAND2X1TS U248 ( .A(n261), .B(n260), .Y(n262) );
INVX2TS U249 ( .A(n259), .Y(n261) );
NAND2X1TS U250 ( .A(n256), .B(n255), .Y(n257) );
NAND2X1TS U251 ( .A(n252), .B(n251), .Y(n253) );
AOI21X1TS U252 ( .A0(n258), .A1(n256), .B0(n249), .Y(n254) );
INVX2TS U253 ( .A(n250), .Y(n252) );
XOR2XLTS U254 ( .A(n242), .B(n246), .Y(res[18]) );
INVX2TS U255 ( .A(n243), .Y(n245) );
NAND2X1TS U256 ( .A(n239), .B(n238), .Y(n240) );
INVX2TS U257 ( .A(n237), .Y(n239) );
XNOR2X1TS U258 ( .A(n229), .B(n228), .Y(res[21]) );
NAND2X1TS U259 ( .A(n227), .B(n226), .Y(n228) );
XOR2X1TS U260 ( .A(n201), .B(n200), .Y(res[25]) );
NAND2X1TS U261 ( .A(n199), .B(n198), .Y(n200) );
NAND2X1TS U262 ( .A(n181), .B(n43), .Y(n186) );
XNOR2X1TS U263 ( .A(n178), .B(n177), .Y(res[29]) );
NAND2X1TS U264 ( .A(n176), .B(n175), .Y(n177) );
INVX2TS U265 ( .A(n174), .Y(n178) );
XNOR2X1TS U266 ( .A(n173), .B(n171), .Y(res[31]) );
NOR2X4TS U267 ( .A(n100), .B(in1[19]), .Y(n237) );
NAND2X4TS U268 ( .A(n100), .B(in1[19]), .Y(n238) );
NOR2X4TS U269 ( .A(n59), .B(in1[11]), .Y(n275) );
INVX4TS U270 ( .A(n62), .Y(n63) );
INVX12TS U271 ( .A(add_sub), .Y(n18) );
AOI21X4TS U272 ( .A0(n45), .A1(n144), .B0(n143), .Y(n182) );
INVX8TS U273 ( .A(n18), .Y(n19) );
INVX4TS U274 ( .A(n18), .Y(n20) );
AFHCONX2TS U275 ( .A(in1[10]), .B(n56), .CI(n55), .CON(n278), .S(res[10]) );
AOI21X1TS U276 ( .A0(n273), .A1(n41), .B0(n66), .Y(n270) );
MXI2X4TS U277 ( .A(n64), .B(n67), .S0(n301), .Y(n65) );
MX2X4TS U278 ( .A(n69), .B(in2[13]), .S0(n301), .Y(n70) );
OR2X4TS U279 ( .A(n137), .B(in2[27]), .Y(n151) );
CLKINVX6TS U280 ( .A(n125), .Y(n36) );
XNOR2X2TS U281 ( .A(n57), .B(in2[11]), .Y(n58) );
XOR2X4TS U282 ( .A(n211), .B(n210), .Y(res[24]) );
XOR2X4TS U283 ( .A(n218), .B(n217), .Y(res[23]) );
XOR2X4TS U284 ( .A(n225), .B(n224), .Y(res[22]) );
NAND2X2TS U285 ( .A(n108), .B(n97), .Y(n92) );
AND2X8TS U286 ( .A(n22), .B(n21), .Y(n50) );
NAND2X8TS U287 ( .A(n25), .B(n24), .Y(n60) );
NOR2X8TS U288 ( .A(n282), .B(n26), .Y(n49) );
NAND2X8TS U289 ( .A(n28), .B(n27), .Y(n26) );
NAND2X8TS U290 ( .A(n30), .B(n29), .Y(n282) );
AND2X8TS U291 ( .A(n17), .B(n35), .Y(n33) );
OAI21X4TS U292 ( .A0(n174), .A1(n165), .B0(n164), .Y(n173) );
OAI2BB1X4TS U293 ( .A0N(n230), .A1N(n102), .B0(n16), .Y(n34) );
NAND2BX4TS U294 ( .AN(n267), .B(n66), .Y(n38) );
AOI21X4TS U295 ( .A0(n264), .A1(n46), .B0(n74), .Y(n263) );
OAI21X4TS U296 ( .A0(n275), .A1(n278), .B0(n276), .Y(n273) );
AOI21X4TS U297 ( .A0(n292), .A1(n24), .B0(n54), .Y(n55) );
NAND2BX4TS U298 ( .AN(n106), .B(n108), .Y(n115) );
XOR2XLTS U299 ( .A(n263), .B(n262), .Y(res[15]) );
XNOR2X1TS U300 ( .A(n274), .B(n273), .Y(res[12]) );
XOR2XLTS U301 ( .A(n279), .B(n278), .Y(res[11]) );
INVX2TS U302 ( .A(n212), .Y(n204) );
NAND2X1TS U303 ( .A(n245), .B(n244), .Y(n246) );
NAND2X8TS U304 ( .A(n50), .B(n49), .Y(n299) );
NAND2X1TS U305 ( .A(in2[8]), .B(add_sub), .Y(n51) );
NOR2BX4TS U306 ( .AN(n61), .B(n60), .Y(n62) );
NOR2X8TS U307 ( .A(n299), .B(n63), .Y(n71) );
XOR2X4TS U308 ( .A(n68), .B(in2[13]), .Y(n69) );
NOR2X8TS U309 ( .A(n70), .B(in1[13]), .Y(n267) );
INVX2TS U310 ( .A(in2[14]), .Y(n75) );
XNOR2X1TS U311 ( .A(in2[14]), .B(n81), .Y(n72) );
OAI21X4TS U312 ( .A0(n263), .A1(n259), .B0(n260), .Y(n247) );
INVX2TS U313 ( .A(in2[17]), .Y(n84) );
NOR3X8TS U314 ( .A(n81), .B(in2[15]), .C(in2[14]), .Y(n108) );
INVX2TS U315 ( .A(in2[16]), .Y(n86) );
OAI21X4TS U316 ( .A0(n250), .A1(n255), .B0(n251), .Y(n89) );
AOI21X4TS U317 ( .A0(n247), .A1(n90), .B0(n89), .Y(n242) );
OAI21X4TS U318 ( .A0(n242), .A1(n243), .B0(n244), .Y(n230) );
INVX2TS U319 ( .A(in2[19]), .Y(n95) );
XNOR2X1TS U320 ( .A(n93), .B(n95), .Y(n94) );
MXI2X4TS U321 ( .A(n95), .B(n94), .S0(n19), .Y(n100) );
INVX2TS U322 ( .A(in2[20]), .Y(n99) );
INVX2TS U323 ( .A(in2[23]), .Y(n105) );
INVX2TS U324 ( .A(in2[24]), .Y(n110) );
MXI2X2TS U325 ( .A(n110), .B(n109), .S0(add_sub), .Y(n122) );
INVX2TS U326 ( .A(in2[22]), .Y(n114) );
NOR2X4TS U327 ( .A(n115), .B(n111), .Y(n112) );
INVX2TS U328 ( .A(in2[21]), .Y(n118) );
NOR2X4TS U329 ( .A(n115), .B(in2[20]), .Y(n116) );
OAI21X4TS U330 ( .A0(n221), .A1(n226), .B0(n222), .Y(n212) );
AOI21X4TS U331 ( .A0(n212), .A1(n124), .B0(n123), .Y(n125) );
INVX2TS U332 ( .A(in2[26]), .Y(n133) );
INVX2TS U333 ( .A(in2[25]), .Y(n132) );
XNOR2X1TS U334 ( .A(n135), .B(in2[28]), .Y(n136) );
INVX2TS U335 ( .A(in2[27]), .Y(n140) );
XOR2X1TS U336 ( .A(n138), .B(in2[27]), .Y(n139) );
MXI2X4TS U337 ( .A(n140), .B(n139), .S0(n20), .Y(n145) );
AOI21X4TS U338 ( .A0(n44), .A1(n183), .B0(n147), .Y(n148) );
NOR3X4TS U339 ( .A(n152), .B(in2[28]), .C(n151), .Y(n155) );
XNOR2X1TS U340 ( .A(n155), .B(in2[29]), .Y(n153) );
XNOR2X1TS U341 ( .A(n159), .B(n158), .Y(res[30]) );
XNOR2X1TS U342 ( .A(n167), .B(in2[31]), .Y(n168) );
OAI2BB1X2TS U343 ( .A0N(n169), .A1N(n173), .B0(n172), .Y(res[32]) );
OAI21X4TS U344 ( .A0(n201), .A1(n186), .B0(n185), .Y(n189) );
XNOR2X4TS U345 ( .A(n189), .B(n188), .Y(res[28]) );
OAI21X4TS U346 ( .A0(n201), .A1(n190), .B0(n182), .Y(n193) );
XNOR2X4TS U347 ( .A(n193), .B(n192), .Y(res[27]) );
OAI21X4TS U348 ( .A0(n201), .A1(n194), .B0(n198), .Y(n197) );
XNOR2X4TS U349 ( .A(n197), .B(n196), .Y(res[26]) );
AOI21X4TS U350 ( .A0(n229), .A1(n206), .B0(n205), .Y(n211) );
INVX2TS U351 ( .A(n207), .Y(n209) );
AOI21X4TS U352 ( .A0(n229), .A1(n213), .B0(n212), .Y(n218) );
AOI21X4TS U353 ( .A0(n229), .A1(n227), .B0(n220), .Y(n225) );
XNOR2X1TS U354 ( .A(n258), .B(n257), .Y(res[16]) );
XNOR2X1TS U355 ( .A(n264), .B(n266), .Y(res[14]) );
NOR2X1TS U356 ( .A(n282), .B(in2[2]), .Y(n285) );
XNOR2X1TS U357 ( .A(n285), .B(n286), .Y(n281) );
AOI21X1TS U358 ( .A0(n18), .A1(in2[3]), .B0(in1[3]), .Y(n280) );
XNOR2X1TS U359 ( .A(n282), .B(in2[2]), .Y(n284) );
AOI21X1TS U360 ( .A0(n18), .A1(in2[2]), .B0(in1[2]), .Y(n283) );
NAND2X1TS U361 ( .A(n286), .B(n285), .Y(n289) );
XNOR2X1TS U362 ( .A(n296), .B(n295), .Y(n288) );
AOI21X1TS U363 ( .A0(n301), .A1(in2[5]), .B0(in1[5]), .Y(n287) );
XNOR2X1TS U364 ( .A(n289), .B(in2[4]), .Y(n291) );
AOI21X1TS U365 ( .A0(n18), .A1(in2[4]), .B0(in1[4]), .Y(n290) );
XOR2X1TS U366 ( .A(n292), .B(in2[9]), .Y(n294) );
AOI21X1TS U367 ( .A0(n18), .A1(in2[9]), .B0(in1[9]), .Y(n293) );
XNOR2X1TS U368 ( .A(n305), .B(in2[6]), .Y(n298) );
AOI21X1TS U369 ( .A0(n308), .A1(in2[6]), .B0(in1[6]), .Y(n297) );
XNOR2X1TS U370 ( .A(n299), .B(in2[8]), .Y(n302) );
AOI21X1TS U371 ( .A0(n308), .A1(in2[8]), .B0(in1[8]), .Y(n300) );
XNOR2X1TS U372 ( .A(in2[0]), .B(in2[1]), .Y(n304) );
AOI21X1TS U373 ( .A0(n18), .A1(in2[1]), .B0(in1[1]), .Y(n303) );
XOR2X1TS U374 ( .A(n306), .B(in2[7]), .Y(n309) );
AOI21X1TS U375 ( .A0(n308), .A1(in2[7]), .B0(in1[7]), .Y(n307) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_LOALPL10_syn.sdf");
endmodule
|
`include "mem_beh.v"
`include "regfile_beh.v"
`include "components.v"
`include "control_units.v"
`include "alu_beh.v"
`include "mux2to1_beh.v"
module kustar;
reg clock, clear;
wire Zero;
// Signal //
/*
//Ex
[8:7] ALUOp
[6] ALUSrc
[5] RegDst,
//M
[4] Branch
[3] MemRead
[2] MemWrite
//WB
[1] RegWrite
[0] MemtoReg
*/
// IF_ID
reg [31:0] IF_ID_AddedPC;
reg [31:0] IF_ID_Inst;
// ID_EX
reg [31:0] ID_EX_AddedPC;
reg [31:0] ID_EX_ReadData1;
reg [31:0] ID_EX_ReadData2;
reg [31:0] ID_EX_ExtendedAddr;
reg [4:0] ID_EX_Inst20_16;
reg [4:0] ID_EX_Inst15_11;
reg [8:0] ID_EX_Signal;
// EX_MEM
reg [31:0] EX_MEM_AddedPC;
reg EX_MEM_Zero;
reg [31:0] EX_MEM_ALU_Result;
reg [31:0] EX_MEM_ReadData2;
reg [4:0] EX_MEM_RegWriteDst;
reg [4:0] EX_MEM_Signal;
// MEM_WB
reg [31:0] MEM_WB_MemReadData;
reg [31:0] MEM_WB_ALU_Result;
reg [4:0] MEM_WB_RegWriteDst;
reg [2:0] MEM_WB_Signal;
wire [31:0] MuxToPC, PCToInstMem, AddToIF_ID, InstMemToIF_ID, IF_ID_AddedPC_To_ID_EX;
wire [31:0] RegtoA, RegtoB, MuxtoWriteData, ExtendToID_EX, ShifttoConcat, JumpAddress;
wire [31:0] EX_MEM_TO_PC_MUX;
wire [4:0] MuxToRegDst;
wire [31:0] MuxToALU, ShiftToAdd, AddToEX_MEM_AddedPC, ALUOut;
wire [2:0] ALUcontrol;
wire [31:0] DataMemResult;
wire MemRead, MemWrite, MemtoReg, ALUSrc, RegWrite, RegDst, Branch;
wire [1:0] ALUOp;
wire JumpSignal;
reg [31:0] four;
reg yesItAlwaysTure;
reg yesItAlwyasFalse;
reg [31:0] unused;
mux4to1 PrePCMux (AddToIF_ID, EX_MEM_AddedPC, JumpAddress, JumpAddress, MuxToPC, {JumpSignal,{EX_MEM_Signal[4] & EX_MEM_Zero}});
single_register PC (MuxToPC, PCToInstMem, clock, clear, yesItAlwaysTure);
Adder PCAdder (PCToInstMem, four, AddToIF_ID);
mem InstMem (PCToInstMem, unused, InstMemToIF_ID, yesItAlwyasFalse, yesItAlwaysTure, clock);
shiftleft2 JumpShift (IF_ID_Inst, ShifttoConcat);
concatenate4to28 PCConcat (ShifttoConcat, PCToInstMem, JumpAddress);
registerfile Registers ({IF_ID_Inst[25:21]}, RegtoA, {IF_ID_Inst[20:16]}, RegtoB, MEM_WB_RegWriteDst, MuxtoWriteData, clock, yesItAlwyasFalse, MEM_WB_Signal[1]);
signextd SignExtend ({IF_ID_Inst[15:0]}, ExtendToID_EX);
mcu YesThisIsMCU (clock, clear, {IF_ID_Inst[31:26]},
MemRead, MemWrite, MemtoReg, ALUOp, ALUSrc, RegWrite, RegDst, Branch,
JumpSignal);
mux2to1 ALUMux (ID_EX_ReadData2, ID_EX_ExtendedAddr, MuxToALU, {ID_EX_Signal[6]});
mux2to1for5bit RegDstMux (ID_EX_Inst20_16, ID_EX_Inst15_11, MuxToRegDst, ID_EX_Signal[5]);
shiftleft2 Shift (ID_EX_ExtendedAddr, ShiftToAdd);
Adder BranchAdder (ID_EX_AddedPC, ShiftToAdd, AddToEX_MEM_AddedPC);
ALU YesThisIsALU (ID_EX_ReadData1, MuxToALU, ALUcontrol, ALUOut, Zero);
acu YesThisIsACU (ID_EX_ExtendedAddr[5:0], ID_EX_Signal[8:7], ALUcontrol);
mem DataMem (EX_MEM_ALU_Result, EX_MEM_ReadData2, DataMemResult, EX_MEM_Signal[2], EX_MEM_Signal[1], clock);
mux2to1 MemToRegMux (MEM_WB_ALU_Result, MEM_WB_MemReadData, MuxtoWriteData, MEM_WB_Signal[0]);
/*
module acu(funct, ALUOp, ALUcontrol);
input [5:0] funct;
input [1:0] ALUOp;
output [2:0] ALUcontrol;
-------------------------------------------------------
module mcu(clk, clr, OP, PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, PCSource, ALUOp, ALUSrcB, ALUSrcA, RegWrite, RegDst);
input clk, clr;
input [5:0] OP;
output PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, ALUSrcA, RegWrite, RegDst;
output [1:0] PCSource, ALUOp, ALUSrcB;
-------------------------------------------------------------
// concatenate pcin[31-28] with datain[27-0] to form a jump address
module concatenate4to28(datain, pcin, pcout);
input [31:0] datain, pcin;
output [31:0] pcout;
-------------------------------------------------------------
module ALU(inputA, inputB, ALUop, result, zero);
input [31:0] inputA, inputB;
input [2:0] ALUop;
output [31:0] result;
output zero;
---------------------------------------------------------------
module mux4to1(datain0, datain1, datain2, datain3, dataout, select);
input [31:0] datain0, datain1, datain2, datain3;
input[1:0] select;
output [31:0] dataout;
-------------------------------------------
module shiftleft2(datain, dataout);
input [31:0] datain;
output [31:0] dataout;
-----------------------------------------------------------
module signextd(datain, dataout);
input [15:0] datain;
output [31:0] dataout;
------------------------------------------------------------
module registerfile(ADDA, DATAA, ADDB, DATAB, ADDC, DATAC, clk, clr, WE);
input [4:0] ADDA,ADDB, ADDC;
input [31:0] DATAC;
input clk, clr, WE;
output [31:0] DATAA, DATAB;
---------------------------------------------
module single_register(datain, dataout, clk, clr, WE);
input [31:0] datain;
output [31:0] dataout;
input clk, clr, WE;
----------------
module mem(addr,datain,dataout, MemWrite, MemRead, clk);
input clk;
input [31:0] addr, datain;
output [31:0] dataout;
input MemWrite, MemRead;
------------------------------
module mux2to1(datain0,datain1, dataout, select);
input [31:0] datain0, datain1;
input select;
output [31:0] dataout;
*/
initial
forever #50 clock = ~clock;
initial
begin
clock = 1;
#5;
four = 4;
yesItAlwaysTure = 1;
yesItAlwyasFalse = 0;
clear = 1;
EX_MEM_Signal[4] = 0;
EX_MEM_Zero = 0;
/* we may not connect clear to register file and memory because we don't want our initial data get cleared*/
#10 clear = 0;
end
always @(negedge clock)
begin
#10
MEM_WB_MemReadData = DataMemResult;
MEM_WB_Signal = EX_MEM_Signal[1:0];
MEM_WB_ALU_Result = EX_MEM_ALU_Result;
MEM_WB_RegWriteDst = EX_MEM_RegWriteDst;
EX_MEM_Signal = ID_EX_Signal[4:0];
EX_MEM_Zero = Zero;
EX_MEM_AddedPC = AddToEX_MEM_AddedPC;
EX_MEM_ReadData2 = ID_EX_ReadData2;
EX_MEM_ALU_Result = ALUOut;
EX_MEM_RegWriteDst = MuxToRegDst;
ID_EX_AddedPC = IF_ID_AddedPC;
ID_EX_ReadData1 = RegtoA;
ID_EX_ReadData2 = RegtoB;
ID_EX_ExtendedAddr = ExtendToID_EX;
ID_EX_Inst20_16 = IF_ID_Inst[20:16];
ID_EX_Inst15_11 = IF_ID_Inst[15:11];
ID_EX_Signal = {ALUOp[1:0],ALUSrc,RegDst,Branch,MemRead,MemWrite,RegWrite,MemtoReg};
IF_ID_Inst = InstMemToIF_ID;
IF_ID_AddedPC = AddToIF_ID;
end
initial
#10000 $stop;
endmodule
|
//----------------------------------------------------------------------------------------
module lc_3b_processor(clk,reset,clk_1);//r8
input clk,reset,clk_1;//use 128 as depth not 128
wire [15:0] IR;
wire N, Z, P;
wire [4:0] StateID;
wire Mux1;
wire [1:0] Mux2;
wire [2:0] Mux3;
wire [1:0] Mux4;
wire [1:0] Mux5;
wire [1:0] Mux6;
wire [1:0] Mux7;
wire Mux11;
wire wrf;
wire wpc;
wire wir;
wire lccr;
wire [1:0] aluop;
wire [1:0] alushop;
wire wmem;
wire wa,wb, lalu;
wire [15:0]ALUreg_wire,ALU_out_wire;
wire [15:0]A_out_wire,B_out_wire,PC_out_wire;
wire[15:0]outir;
datapath d1(.reset(reset),.clk(clk),.IR(IR),.N(N), .P(P), .Z(Z), .Mux1(Mux1), .Mux2(Mux2), .Mux3(Mux3), .Mux4(Mux4),
.Mux5(Mux5), .Mux6(Mux6), .Mux7(Mux7), .Mux11(Mux11), .wrf(wrf), .wpc(wpc), .wir(wir), .lccr(lccr), .aluop(aluop),
.alushop(alushop), .wmem(wmem), .ALUreg_wire(ALUreg_wire), .A_out_wire(A_out_wire), .B_out_wire(B_out_wire),
.PC_out_wire(PC_out_wire), .ALU_out_wire(ALU_out_wire),.wa(wa),.wb(wb), .lalu(lalu),.outir(outir));
controller c1(.reset(reset),.clk(clk), .IR(IR), .N(N), .Z(Z), .P(P), .StateID(StateID), .Mux1(Mux1), .Mux2(Mux2), .Mux3(Mux3),
.Mux4(Mux4), .Mux5(Mux5), .Mux6(Mux6), .Mux7(Mux7), .Mux11(Mux11), .wrf(wrf), .wpc(wpc), .wir(wir),
.lccr(lccr), .aluop(aluop), .alushop(alushop), .wmem(wmem),.wa(wa),.wb(wb), .lalu(lalu));
endmodule
module controller(reset,clk, IR, N, Z, P, StateID, Mux1, Mux2, Mux3, Mux4, Mux5, Mux6, Mux7, Mux11, wrf, wpc, wir,wa,wb, lccr, aluop, alushop, wmem, nextStateID, lalu); // Implements the designed controller for LC-3b.
input [15:0] IR;
input clk, N, Z, P,reset;
output reg [4:0] StateID;
output reg Mux1;
output reg [1:0] Mux2;
output reg [2:0] Mux3;
output reg [1:0] Mux4;
output reg [1:0] Mux5;
output reg [1:0] Mux6;
output reg [1:0] Mux7;
output reg Mux11;
output reg wrf;
output reg wpc;
output reg wir;
output reg wa;
output reg wb;
output reg lalu;
output reg lccr;
output reg [1:0] aluop;
output reg [1:0] alushop;
output reg wmem;
output reg [4:0] nextStateID;
always@(*) begin
case(StateID)
1: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b01;
Mux5 = 2'b01;
Mux6 = 2'b10;
Mux7 = 2'b10;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = ~|IR;
wir = 1'b0;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
2: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b0;
wb = 1'b0;
lalu = 1'b1;
end
3: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b0;
aluop = {IR[15], IR[14]};
alushop = {IR[5], IR[4]};
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b0;
end
4: begin
Mux1 = 1'b1;
Mux2 = 2'b01;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b0;
wrf = 1'b0;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
5: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b010;
Mux4 = 2'b01;
Mux5 = 2'b11;
Mux6 = 2'b00;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
6: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
7: begin
Mux1 = 1'b1;
Mux2 = 2'b10;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b0;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
8: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b000;
Mux4 = 2'b01;
Mux5 = 2'b11;
Mux6 = 2'b01;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
9: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b100;
Mux4 = 2'b00;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b0;
end
10: begin
Mux1 = 1'b0;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b0;
wb = 1'b1;
lalu = 1'b1;
end
11: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b01;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b0;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
12:begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b001;
Mux4 = 2'b00;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b0;
end
13:begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b01;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
14:begin
Mux1 = 1'b1;
Mux2 = 2'b00;
Mux3 = 3'b111;
Mux4 = 2'b10;
Mux5 = 2'b10;
Mux6 = 2'b11;
Mux7 = 2'b01;
Mux11 = 1'b0;
wrf = 1'b0;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b0;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
15:begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b010;
Mux4 = 2'b01;
Mux5 = 2'b11;//three not dc
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b0;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b0;
end
16:begin
Mux1 = 1'b1;
Mux2 = 2'b01;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b0;
wrf = 1'b0;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
default: begin
Mux1 = 1'b0;
Mux2 = 2'b00;
Mux3 = 3'b000;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b00;
Mux7 = 2'b00;
Mux11 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b00;
wmem = 1'b1;
wa = 1'b1;
wb = 1'b1;
lalu = 1'b1;
end
endcase
end
always@(posedge clk) begin
if(reset ==0)
StateID = 0;
else
StateID = nextStateID;
end
always@(*) begin
if(reset == 1) begin
case(StateID)
0: nextStateID=1;
1: begin
if(IR ==0)
nextStateID=1;
else
case(IR[15:12])
0: nextStateID=5;//
4: nextStateID=7;//
14: nextStateID=15;//
default: nextStateID=2;
endcase
end
2: begin
case(IR[15:12])
7: nextStateID=12;
6: nextStateID=12;
3: nextStateID=9;
2: nextStateID=9;
12: nextStateID=6;
4: nextStateID=8;
default: nextStateID=3;
endcase
end
3: nextStateID=4;
4: nextStateID=1;
5: nextStateID=1;
6: nextStateID=1;
7: nextStateID=2;
8: nextStateID=1;
9: begin
case(IR[15:12])
3: nextStateID=10;
2: nextStateID=13;
default: nextStateID=10;
endcase
end
10: nextStateID=11;
11: nextStateID=1;
12: begin
case(IR[15:12])
7: nextStateID=10;
6: nextStateID=13;
default: nextStateID=10;
endcase
end
13: nextStateID=14;
14: nextStateID=1;
15: nextStateID=16;
16: nextStateID=1;
default: nextStateID=1;
endcase
end
else
nextStateID = 1;
end
endmodule
module datapath(reset,clk,IR,N,P,Z,Mux1,Mux2,Mux3,Mux4,Mux5,Mux6,Mux7,Mux11,wrf, wpc, wir, wa,wb,lccr, aluop, alushop, wmem
,ALUreg_wire,A_out_wire,B_out_wire,PC_out_wire,ALU_out_wire, mem_out_wire, mdr_wire, lalu,outir);
input clk,reset;
output [15:0]IR;
input Mux1,Mux11;
input [1:0] Mux2,Mux4,Mux5,Mux6,Mux7;
input [2:0]Mux3;
output N,P,Z;
input wrf, wpc, wir, lccr, wmem,wa,wb, lalu;
input[1:0] aluop, alushop;
output [15:0]ALUreg_wire,A_out_wire,B_out_wire,PC_out_wire,ALU_out_wire;//
wire [15:0] A_out_wire,ALUreg_wire,PC_out_wire,mem_address_wire;
wire[15:0] mux6_in_1_wire,mux6_in_0_wire;
output wire[15:0] mem_out_wire, mdr_wire,outir;
mux16x2 m7(.data0(A_out_wire),.data1(ALUreg_wire),.data2(PC_out_wire),.data3(PC_out_wire),.selectinput(Mux7),.out(mem_address_wire));//data3 is never slelcted(just done this to prevent latch formation
mem16 memory(.outir(outir),.address(mem_address_wire), .write(wmem),.clk(clk), .in(A_out_wire),.out(mem_out_wire),.ir14(IR[14]), .reset(reset));
latch16 inst_reg(.in(outir),.out(IR),.write(wir));
latch16 mdr(.in(mem_out_wire),.out(mdr_wire),.write(1'b0));
wire [2:0] IA1_wire,WA_wire;
mux3x1 m1(.data0(IR[11:9]),.data1(IR[8:6]),.selectinput(Mux1),.out(IA1_wire));
mux3x1 m11(.data0(IR[11:9]),.data1(3'd7),.selectinput(Mux11),.out(WA_wire)); // Is this right ?
wire [15:0]reg_file_data_in_wire;
mux16x2 m2(.data0(mdr_wire),.data1(ALUreg_wire),.data2(PC_out_wire),.data3(PC_out_wire),.selectinput(Mux2),.out(reg_file_data_in_wire));
wire [15:0]data0,data1,data2,data3,data4,data5,data6,data7;
wire[15:0] A_in_wire,B_in_wire,regfile_out2_wire;
register_file rf1(.clk(clk), .out1(A_in_wire), .out2(regfile_out2_wire),
.readAdd1(IA1_wire),.readAdd2(IR[2:0]),.write(wrf),.writeAdd(WA_wire),.in(reg_file_data_in_wire), .reset(reset),.data0(data0),.data1(data1),.data2(data2),.data3(data3),.data4(data4), .data5(data5), .data6(data6), .data7(data7));
wire[15:0] sext11_0_wire, sext8_0_wire,sext5_0_wire;
sext12 s11_0(.in(IR[10:0]),.out(sext11_0_wire));
sext9 s8_0(.in(IR[8:0]),.out(sext8_0_wire));
sext6 s5_0(.in(IR[5:0]),.out(sext5_0_wire));
wire[15:0] lshf11_0_wire, lshf8_0_wire,lshf5_0_wire;
lshift1 lshf11_0(.in(sext11_0_wire),.out(lshf11_0_wire));
lshift1 lshf8_0(.in(sext8_0_wire),.out(lshf8_0_wire));
lshift1 lshf5_0(.in(sext5_0_wire),.out(lshf5_0_wire));
wire [15:0] mux5_in_3_wire;
mux16x1 m8(.data0(regfile_out2_wire),.data1(sext5_0_wire),.selectinput(IR[5]),.out(B_in_wire));
mux16x3 m3(.data0(lshf11_0_wire),.data1(lshf5_0_wire),.data2(lshf8_0_wire),.data3(sext11_0_wire),.data4(sext5_0_wire),.selectinput(Mux3),.out(mux5_in_3_wire));
wire[15:0] B_out_wire;
register16 A (.clk(clk), .out(A_out_wire),.in(A_in_wire),.write(wa),.reset(reset));
register16 B (.clk(clk), .out(B_out_wire),.in(B_in_wire),.write(wb),.reset(reset));
wire[15:0] ALU_in_1_wire,ALU_in_2_wire;
mux16x2 m4(.data0(A_out_wire),.data1(PC_out_wire),.data2(mdr_wire),.data3(mdr_wire),.selectinput(Mux4),.out(ALU_in_1_wire));
mux16x2 m5 (.data0(B_out_wire),.data1(16'd2),.data2(16'd0),.data3(mux5_in_3_wire),.selectinput(Mux5),.out(ALU_in_2_wire));
wire[15:0]ALU_out_wire;
wire zero,negative,positive;
alu ALU(.in1(ALU_in_1_wire), .in2(ALU_in_2_wire),.op(aluop), .shop(alushop),.shift(IR[3:0]), .out(ALU_out_wire), .zero(zero),.positive(positive),.negative(negative));
register1b neg_reg(.clk(clk),.out(N),.in(negative),.write(lccr),.reset(reset));
register1b pos_reg(.clk(clk),.out(P),.in(positive),.write(lccr),.reset(reset));
register1b zero_reg(.clk(clk),.out(Z),.in(zero),.write(lccr),.reset(reset));
wire[15:0] PC_in_wire;
register16 PC (.clk(clk), .out(PC_out_wire),.in(PC_in_wire),.write(wpc),.reset(reset));
wire hc;
assign hc =( (IR[11]&&N)|| (IR[10]&&Z)||(IR[9]&&P));
mux16x1 m9(.data0(PC_out_wire),.data1(ALU_out_wire),.selectinput(hc),.out(mux6_in_0_wire));
register16 ALUreg(.clk(clk),.out(ALUreg_wire),.in(ALU_out_wire),.write(lalu),.reset(reset));
mux16x1 m10(.data0(A_out_wire),.data1(ALU_out_wire),.selectinput(IR[11]),.out(mux6_in_1_wire));
mux16x2 m6(.data0(mux6_in_0_wire),.data1(mux6_in_1_wire),.data2(ALU_out_wire),.data3(A_out_wire),.selectinput(Mux6),.out(PC_in_wire));
endmodule
module sext9(in,out);
input [8:0] in;
output[15:0] out;
assign out= {{7{in[8]}},in[8:0]};
endmodule
module sext12(in,out);
input [10:0] in;
output[15:0] out;
assign out= {{4{in[10]}},in[10:0]};
endmodule
module sext6(in,out);
input [5:0] in;
output[15:0] out;
assign out= {{10{in[5]}},in[5:0]};
endmodule
module register16(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [15:0] out;
input [15:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 16'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register1b(clk, out, in, write, reset); // Negedge-triggered 1 bit flipflop register for with active-low write signal and reset
output reg out;
input in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 1'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register_file(clk, out1, out2, readAdd1, readAdd2, write, writeAdd, in, reset,data0,data1,data2,data3,data4, data5, data6, data7);
output [15:0] out1, out2;
input [15:0] in;
input [2:0] readAdd1, readAdd2, writeAdd;
input write, clk, reset;
output wire [15:0] data0, data1, data2, data3, data4, data5, data6, data7;
wire [7:0] writeLinesInit, writeLines;
demux8 dem(writeAdd, writeLinesInit);
mux16x8 mux1(data0, data1, data2, data3, data4, data5, data6, data7, readAdd1, out1);
mux16x8 mux2(data0, data1, data2, data3, data4, data5, data6, data7, readAdd2, out2);
or a0(writeLines[0], write, ~writeLinesInit[0]);
or a1(writeLines[1], write, ~writeLinesInit[1]);
or a2(writeLines[2], write, ~writeLinesInit[2]);
or a3(writeLines[3], write, ~writeLinesInit[3]);
or a4(writeLines[4], write, ~writeLinesInit[4]);
or a5(writeLines[5], write, ~writeLinesInit[5]);
or a6(writeLines[6], write, ~writeLinesInit[6]);
or a7(writeLines[7], write, ~writeLinesInit[7]);
register16 r0(clk, data0, in, writeLines[0], reset);
register16 r1(clk, data1, in, writeLines[1], reset);
register16 r2(clk, data2, in, writeLines[2], reset);
register16 r3(clk, data3, in, writeLines[3], reset);
register16 r4(clk, data4, in, writeLines[4], reset);
register16 r5(clk, data5, in, writeLines[5], reset);
register16 r6(clk, data6, in, writeLines[6], reset);
register16 r7(clk, data7, in, writeLines[7], reset);
endmodule
module mux16x1(data0,data1,selectinput,out);//used in mux 1,8,9,10,11
input [15:0] data0,data1;
input selectinput;
output reg [15:0] out;
always @(*)
begin
case (selectinput)
0:
out = data0;
1:
out = data1;
default:
out = data0;
endcase
end
endmodule
module mux3x1(data0,data1,selectinput,out);//used in mux 1,8,9,10,11
input [2:0] data0,data1;
input selectinput;
output reg [2:0] out;
always @(*)
begin
case (selectinput)
0:
out = data0;
1:
out = data1;
default:
out = data0;
endcase
end
endmodule
module mux16x2(data0,data1,data2,data3,selectinput,out);//used in mux 2,4,5,6,7
input [15:0] data0,data1,data2,data3;
input [1:0]selectinput;
output reg [15:0] out;
always @(*)
begin
case (selectinput)
0:
out = data0;
1:
out = data1;
2:
out = data2;
3:
out = data3;
default:
out = data0;
endcase
end
endmodule
module mux16x3(data0,data1,data2,data3,data4,data5,selectinput,out);//used in mux 2,4,5,6,7
input [15:0] data0,data1,data2,data3,data4,data5;
input [2:0]selectinput;
output reg [15:0] out;
always @(*)
begin
case (selectinput)
0:
out = data0;
1:
out = data1;
2:
out = data2;
3:
out = data3;
4:
out = data4;
5:
out = data5;
default:
out = data0;
endcase
end
endmodule
module muxalu(data0, data1, data2, data3, data4, data5, op, shop, out); // 8-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1, data2, data3, data4, data5;
input [1:0] op;
input [1:0]shop;
always@(*) begin
case(op)
0: out = data0;
1: out = data1;
2: out = data2;
default:
case(shop)
0: out = data3;
1: out = data4;
3: out = data5;
default: out = data5;
endcase
endcase
end
endmodule
module mux16x8(data0, data1, data2, data3, data4, data5, data6, data7, selectInput, out); // 8-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1, data2, data3, data4, data5, data6, data7;
input [2:0] selectInput;
always@(data0 or data1 or data2 or data3 or data4 or data5 or data6 or data7 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
2: out = data2;
3: out = data3;
4: out = data4;
5: out = data5;
6: out = data6;
7: out = data7;
endcase
end
endmodule
module memory1(reset,address,in,out,write,clk, testWire); // LSB
input [7:0] in;
input clk,write,reset;
input [14:0] address;
output reg [7:0] out;
output wire [7:0] testWire;
reg [7:0] mem [0:255];
integer i;
assign testWire = mem[7];
always @(negedge clk)
begin
out = mem[address];
if(reset== 1'b0)
begin
for(i=0;i<256;i=i+1)
mem [i] = 0;
mem[0] = 8'b00111111;
mem[1] = 8'b00000000;
mem[2] = 8'b10000001;
mem[3] = 8'b00000111;
mem[4] = 8'b00001110;
mem[5] = 8'b00010100;
mem[26]= 8'b11000000;
mem[31]= 8'b00000001;
mem[33]= 8'b00000010;
end
else
if(write ==1'b0)
begin
mem[address] <= in;
end
end
endmodule
module memory2(reset,address,in,out,write,clk, testWire); // MSB
input [7:0] in;
input clk,write,reset;
input [14:0] address;
output reg [7:0] out;
output wire [7:0] testWire;
reg [7:0] mem [0:255];
integer i;
assign testWire = mem[7];
always @(negedge clk)
begin
out = mem[address];
if(reset== 1'b0)
begin
for(i=0;i<256;i=i+1)
mem [i] = 0;
mem[0] = 8'b10010010;//IR = 0x 923f -> NOT of R0, into R1 (R0 was 0)
mem[1] = 8'b01100100; //IR = 0x 6400 -> R2 = mem(0) (mem0 was 923f)
mem[2] = 8'b00010110; //IR = 0x 1681 -> R3 = R1 + R2 (ffff+923f = 923e)
mem[3] = 8'b01110111; //IR = 0x7707 ->
mem[4] = 8'b00101111; //load mem(14) into R7
mem[5] = 8'b00000010;// branch conditional on p set, to 52..
mem[26] =8'b11000001;//jump to value stored in R7 (0x3E or 62)(JMP)
mem[31] = 8'b01001000;//JSR, add 2 to incremented PC, resulting in next PC = 66 instead of 64...( 64 is stored in R7)
mem[33] = 8'b11100001;//lea = incremented pc + (-1) = 66
end
if(write ==1'b0)
begin
mem[address] <= in;
end
end
endmodule
module mem16(reset,address, write,clk, in, out,ir14,outir);
input [15:0] in;
input [15:0] address;
input write,clk,ir14,reset;
output reg [15:0] out;
output [15:0]outir;
reg wreven,wrodd;
wire [7:0] outeven,outodd;
reg [7:0] ineven,inodd;
memory1 even(.reset(reset),.address(address[15:1]),.in(ineven),.out(outeven),.clk(clk),.write(wreven));
memory2 odd (.reset(reset),.address(address[15:1]),.in(inodd),.out(outodd),.clk(clk),.write(wrodd));
//for in signals of individual memories
always @(*)
begin
if(ir14==0)
begin
ineven<=in[7:0];
inodd<=in[7:0];
end
else
begin
ineven<= in[7:0];
inodd<=in[15:8];
end
end
//-----------------------------------------------
assign outir[15:8] = outodd;
assign outir[7:0] = outeven;
//for out signals of individual memories
always @(*)
begin
if(ir14 ==1'b1)
begin
out[15:8]<=outodd;
out[7:0]<=outeven;
end
else
if(address[0]==0)
begin
out<= {{8{outeven[7]}},outeven[7:0]};
end
else
begin
out<= {{8{outodd[7]}},outodd[7:0]};
end
end
//-------------------------------------------------
//for write signal
always @(*)
begin
if(ir14==0&&address[0]==1'b1)
begin
wreven<=1'b1;
end
else
begin
wreven<=write;
end
end
always @(*)
begin
if(ir14==0&&address[0]==1'b0)
begin
wrodd<=1'b1;
end
else
begin
wrodd<=write;
end
end
endmodule
module lshift1(in,out);
input [15:0] in;
output [15:0] out;
assign out = {in[14:0],1'b0};
endmodule
module latch16(in,out,write);
input [15:0]in;
input write;//active low wrie
output reg [15:0] out;
always @(*)
begin
if(write == 1'b0)
out = in;
else
out = out;
end
endmodule
module demux8(selectInput, out); // 8-output demux
output reg [7:0] out;
input [2:0] selectInput;
always@(selectInput) begin
case(selectInput)
0: out = 8'b00000001;
1: out = 8'b00000010;
2: out = 8'b00000100;
3: out = 8'b00001000;
4: out = 8'b00010000;
5: out = 8'b00100000;
6: out = 8'b01000000;
7: out = 8'b10000000;
endcase
end
endmodule
module alu(in1, in2, op,shop,shift, out, zero, positive, negative);
output [15:0] out;
input [15:0] in1, in2;
input [1:0] op,shop;
input [3:0] shift;
output zero, positive,negative;
nor n1(zero,out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7],out[8],out[9],out[10],out[11],out[12],out[13],out[14],out[15]);
assign positive = (~out[15])&(~zero);
assign negative = out[15];
wire [15:0] outAdd, outAnd, outXor, outLshf, outRshfl, outRshfa;
muxalu m1(outAdd, outAnd, outXor, outLshf, outRshfl, outRshfa, op, shop, out);
adder16 add1(in1, in2, outAdd);
and16 and1(in1, in2, outAnd);
xor16 xor1(in1, in2, outXor);
left_shift lshf1(in1, outLshf, shift);
right_shift_logical rshfl1(in1, outRshfl, shift);
right_shift_arithmetic rshfa1(in1, outRshfa, shift);
endmodule
module adder16(in1, in2 , out); // Implements a full 16-bit adder
input [15:0] in1, in2;
output [15:0] out;
assign out = in1 + in2;
endmodule
module and16(in1, in2, out); // Implements bitwise AND for two 16-bit numbers
input [15:0] in1, in2;
output [15:0] out;
assign out = in1 & in2;
endmodule
module left_shift(in, out, shift);
output [15:0] out;
input [15:0] in;
input [3:0] shift;
assign out = in << shift;
endmodule
module right_shift_arithmetic(in, out, shift);
output reg [15:0] out;
input [15:0] in;
input [3:0] shift;
always @(*) begin
case(shift)
4'd0: out=in;
4'd1: out={in[15],in[15:1]};
4'd2: out={{2{in[15]}},in[15:2]};
4'd3: out={{3{in[15]}},in[15:3]};
4'd4: out={{4{in[15]}},in[15:4]};
4'd5: out={{5{in[15]}},in[15:5]};
4'd6: out={{6{in[15]}},in[15:6]};
4'd7: out={{7{in[15]}},in[15:7]};
4'd8: out={{8{in[15]}},in[15:8]};
4'd9: out={{9{in[15]}},in[15:9]};
4'd10: out={{10{in[15]}},in[15:10]};
4'd11: out={{11{in[15]}},in[15:11]};
4'd12: out={{12{in[15]}},in[15:12]};
4'd13: out={{13{in[15]}},in[15:13]};
4'd14: out={{14{in[15]}},in[15:14]};
4'd15: out={16{in[15]}};
endcase
end
endmodule
module right_shift_logical(in, out, shift);
output [15:0] out;
input [15:0] in;
input [3:0] shift;
assign out = in >> shift;
endmodule
module xor16(in1, in2, out); // Implements bitwise XOR for two 16-bit numbers
input [15:0] in1, in2;
output [15:0] out;
assign out = in1 ^ in2;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3_BLACKBOX_V
`define SKY130_FD_SC_HD__NAND3_BLACKBOX_V
/**
* nand3: 3-input NAND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand3 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3_BLACKBOX_V
|
`default_nettype none
`include "mnemonics.h"
`include "registers.h"
`include "senior_defines.vh"
module id_decode_logic
#(parameter nat_w = `SENIOR_NATIVE_WIDTH)
(
input wire [31:0] pm_inst_bus_i,
output reg [`AGU_CTRL_WIDTH-1:0] agu_ctrl_o,
output reg [`ALU_CTRL_WIDTH-1:0] alu_ctrl_o,
output reg [`MAC_CTRL_WIDTH-1:0] mac_ctrl_o,
output reg [`COND_LOGIC_CTRL_WIDTH-1:0] cond_logic_ctrl_o,
output reg [`LC_CTRL_WIDTH-1:0] loop_counter_ctrl_o,
output reg [`WB_MUX_CTRL_WIDTH-1:0] wb_mux_ctrl_o,
output reg [`PFC_CTRL_WIDTH-1:0] pc_fsm_ctrl_o,
output reg [`RF_CTRL_WIDTH-1:0] rf_ctrl_o,
output reg [`IO_CTRL_WIDTH-1:0] io_ctrl_o,
output reg [`OPSEL_CTRL_WIDTH-1:0] opsel_ctrl_o,
output reg [`SENIOR_NATIVE_WIDTH-1:0] imm_val_o,
output reg [`ID_PIPE_TYPE_WIDTH-1:0] pipeline_type_o,
output reg [`SPR_CTRL_WIDTH-1:0] spr_ctrl_o,
output reg [`DM_DATA_SELECT_CTRL_WIDTH-1:0] dm_data_select_ctrl_o);
//signals to P4
`include "std_messages.vh"
//Set pipeline type
always@* begin
casez(pm_inst_bus_i[31:22])
`CONV_DEPTH_INSTRUCTIONS: pipeline_type_o = `ID_CONV_PIPE;
`E1_DEPTH_INSTRUCTIONS: pipeline_type_o = `ID_E1_PIPE;
`MACLD, `MULLD, `MULDBLLD: pipeline_type_o = `ID_EARLY_WRITE_E2_PIPE;
`E2_DEPTH_INSTRUCTIONS: pipeline_type_o = `ID_E2_PIPE;
default: begin
pipeline_type_o = `ID_E1_PIPE;
if(defined_but_illegal(pm_inst_bus_i[31:22],10,"pm_inst_bus_i[31:22]")) begin
$stop;
end
end
endcase
end
reg [1:0] gacr01;
reg [1:0] gacr23;
reg [3:0] hacr;
reg [3:0] lacr;
always@* begin
gacr01 = 0;
gacr23 = 0;
hacr = 0;
lacr = 0;
case (pm_inst_bus_i[18:17])
2'b00:
begin
gacr01 = 2'b01;
hacr[0] = 1'b1;
lacr[0] = 1'b1;
end
2'b01:
begin
gacr01 = 2'b10;
hacr[1] = 1'b1;
lacr[1] = 1'b1;
end
2'b10:
begin
gacr23 = 2'b01;
hacr[2] = 1'b1;
lacr[2] = 1'b1;
end
2'b11:
begin
gacr23 = 2'b10;
hacr[3] = 1'b1;
lacr[3] = 1'b1;
end // case: 2'b11
endcase // case (pm_inst_bus_i[18:17])
end
wire [1:0] agu_other_val0;
wire agu_pre_op0;
wire agu_modulo0;
wire agu_br0;
wire agu_ar_out0;
wire agu_imm0;
wire agu_ar_wren0;
reg [2:0] amd0_mode;
reg [2:0] amd1_mode;
always@* begin
casez(pm_inst_bus_i[31:22])
`CONV: amd0_mode = pm_inst_bus_i[16:14];
`MULLD, `MACLD: amd0_mode = pm_inst_bus_i[21:19];
`MULDBLLD: begin
if(pm_inst_bus_i[26])
amd0_mode = 3'b111;
else
amd0_mode = 3'b010;
end
default: amd0_mode = pm_inst_bus_i[29:27];
endcase // casez(pm_inst_bus_i[31:22])
end // always@ *
always@* begin
casez(pm_inst_bus_i[31:22])
`MULDBLLD: begin
if(pm_inst_bus_i[25])
amd1_mode = 3'b111;
else
amd1_mode = 3'b010;
end
default: amd1_mode = pm_inst_bus_i[11:9];
endcase
end
addressing_mode_decoder amd0
(
// Outputs
.pre_op_o (agu_pre_op0),
.other_val_o (agu_other_val0),
.modulo_o (agu_modulo0),
.br_o (agu_br0),
.ar_out_o (agu_ar_out0),
.imm_o (agu_imm0),
.ar_wren_o (agu_ar_wren0),
// Inputs
.mode_i (amd0_mode));
wire [1:0] agu_other_val1;
wire agu_pre_op1;
wire agu_modulo1;
wire agu_br1;
wire agu_ar_out1;
wire agu_imm1;
wire agu_ar_wren1;
addressing_mode_decoder amd1
(
// Outputs
.pre_op_o (agu_pre_op1),
.other_val_o (agu_other_val1),
.modulo_o (agu_modulo1),
.br_o (agu_br1),
.ar_out_o (agu_ar_out1),
.imm_o (agu_imm1),
.ar_wren_o (agu_ar_wren1),
// Inputs
.mode_i (amd1_mode));
wire [nat_w-1:0] alu_imm12s_extd;
assign alu_imm12s_extd = {{(nat_w-12){pm_inst_bus_i[11]}},pm_inst_bus_i[11:0]};
wire [nat_w-1:0] alu_imm5z_extd;
assign alu_imm5z_extd = {{(nat_w-5){1'b0}},pm_inst_bus_i[11:7]};
always@* begin
agu_ctrl_o = 0;
alu_ctrl_o`ALU_ORG = 0;
mac_ctrl_o = 0;
cond_logic_ctrl_o = 0;
loop_counter_ctrl_o = 0;
wb_mux_ctrl_o = 0;
pc_fsm_ctrl_o = 0;
rf_ctrl_o = 0;
io_ctrl_o = 0;
imm_val_o = 0;
spr_ctrl_o = 0;
opsel_ctrl_o = 0;
dm_data_select_ctrl_o = 0;
casez(pm_inst_bus_i[31:22])
`MOVE_1: begin //Tested
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
spr_ctrl_o`SPR_ADR = pm_inst_bus_i[16:12];
if (pm_inst_bus_i[16:12] == `FL0) alu_ctrl_o`ALU_OUT = 3'b110;
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0110;
end
`MOVE_2: begin //Tested
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
spr_ctrl_o`SPR_ADR = pm_inst_bus_i[21:17];
spr_ctrl_o`SPR_WREN = 1;
spr_ctrl_o`SPR_SOURCE = `SPR_SOURCE_RF;
end
`MOVE_3: begin //Tested
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0001;
mac_ctrl_o`MAC_OPBADR = {1'b0, pm_inst_bus_i[13:12]};
mac_ctrl_o`MAC_OPAADR = {1'b0, {2{pm_inst_bus_i[6]}}}; //Rounding
mac_ctrl_o`MAC_SCALE = pm_inst_bus_i[10:8];
mac_ctrl_o`MAC_RND = pm_inst_bus_i[6];
mac_ctrl_o`MAC_SAT = pm_inst_bus_i[5];
mac_ctrl_o`MAC_MS = 1'b1;
mac_ctrl_o`MAC_OP = `MAC_MOVE;
if(pm_inst_bus_i[6]) begin
mac_ctrl_o`MAC_OP = `MAC_MOVE_ROUND;
end
end
`MOVE_4: begin //Tested
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_OPBADR = 3'b110;
if (pm_inst_bus_i[19]) mac_ctrl_o`MAC_SCALE = 3'b111;
mac_ctrl_o`MAC_GACR01 = 0;
mac_ctrl_o`MAC_GACR23 = 0;
if(pm_inst_bus_i[19]) begin
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
end
else begin
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_LACR3 = lacr[3];
end
mac_ctrl_o`MAC_OP = `MAC_MOVE;
end
`SET_1: begin //Tested
rf_ctrl_o`RF_OPA = 6'b100000;
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
imm_val_o = pm_inst_bus_i[15:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0000;
end
`SET_2: begin //Tested
rf_ctrl_o`RF_OPA = 6'b100000;
imm_val_o = pm_inst_bus_i[15:0];
spr_ctrl_o`SPR_ADR = pm_inst_bus_i[21:17];
spr_ctrl_o`SPR_WREN = 1;
end
`LD: begin //Tested
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
if (pm_inst_bus_i[29:27] == `A_ABS) begin
imm_val_o = pm_inst_bus_i[15:0];
end
else if (pm_inst_bus_i[29:27] == `A_OFS) begin
imm_val_o = {3'b0, pm_inst_bus_i[12:0]};
agu_ctrl_o`AGU_SP_EN = pm_inst_bus_i[15];
end
else
agu_ctrl_o`AGU_SP_EN = pm_inst_bus_i[15];
wb_mux_ctrl_o`WB_MUX_SEL = {3'b010, pm_inst_bus_i[16]};
agu_ctrl_o`AGU_OUT_MODE = pm_inst_bus_i[16];
agu_ctrl_o`AGU_PRE_OP_0 = agu_pre_op0;
agu_ctrl_o`AGU_OTHER_VAL0 = agu_other_val0;
agu_ctrl_o`AGU_MODULO_0 = agu_modulo0;
agu_ctrl_o`AGU_BR0 = agu_br0;
agu_ctrl_o`AGU_AR0_OUT = agu_ar_out0;
agu_ctrl_o`AGU_IMM0_VALUE = agu_imm0;
agu_ctrl_o`AGU_AR0_WREN = pm_inst_bus_i[15] ? 0 : agu_ar_wren0;
agu_ctrl_o`AGU_AR0_SEL = pm_inst_bus_i[15] ? 0 : pm_inst_bus_i[14:13];
end
`ST: begin //Tested
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[21:17]};
if (pm_inst_bus_i[29:27] == `A_ABS) begin
imm_val_o = pm_inst_bus_i[15:0];
end
else if (pm_inst_bus_i[29:27] == `A_OFS) begin
imm_val_o = {3'b0, pm_inst_bus_i[12:0]};
agu_ctrl_o`AGU_SP_EN = pm_inst_bus_i[15];
end
else
agu_ctrl_o`AGU_SP_EN = pm_inst_bus_i[15];
agu_ctrl_o`AGU_DM1_WREN = pm_inst_bus_i[16];
agu_ctrl_o`AGU_DM0_WREN = ~pm_inst_bus_i[16];
agu_ctrl_o`AGU_OUT_MODE = pm_inst_bus_i[16];
agu_ctrl_o`AGU_PRE_OP_0 = agu_pre_op0;
agu_ctrl_o`AGU_OTHER_VAL0 = agu_other_val0;
agu_ctrl_o`AGU_MODULO_0 = agu_modulo0;
agu_ctrl_o`AGU_BR0 = agu_br0;
agu_ctrl_o`AGU_AR0_OUT = agu_ar_out0;
agu_ctrl_o`AGU_IMM0_VALUE = agu_imm0;
agu_ctrl_o`AGU_AR0_WREN = pm_inst_bus_i[15] ? 0 : agu_ar_wren0;
agu_ctrl_o`AGU_AR0_SEL = pm_inst_bus_i[15] ? 0 : pm_inst_bus_i[14:13];
end // case: `ST
`DBLLD: begin
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN_DM = 1'b1;
rf_ctrl_o`RF_WRITE_REG_SEL_DM = pm_inst_bus_i[16:12];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0100;
imm_val_o = 0;
agu_ctrl_o`AGU_PRE_OP_0 = agu_pre_op0;
agu_ctrl_o`AGU_OTHER_VAL0 = agu_other_val0;
agu_ctrl_o`AGU_MODULO_0 = agu_modulo0;
agu_ctrl_o`AGU_BR0 = agu_br0;
agu_ctrl_o`AGU_AR0_OUT = agu_ar_out0;
agu_ctrl_o`AGU_IMM0_VALUE = agu_imm0;
agu_ctrl_o`AGU_AR0_WREN = agu_ar_wren0;
agu_ctrl_o`AGU_AR0_SEL = pm_inst_bus_i[8:7];
agu_ctrl_o`AGU_PRE_OP_1 = agu_pre_op1;
agu_ctrl_o`AGU_OTHER_VAL1 = agu_other_val1;
agu_ctrl_o`AGU_MODULO_1 = agu_modulo1;
agu_ctrl_o`AGU_BR1 = agu_br1;
agu_ctrl_o`AGU_AR1_OUT = agu_ar_out1;
agu_ctrl_o`AGU_IMM1_VALUE = agu_imm1;
agu_ctrl_o`AGU_AR1_WREN = agu_ar_wren1;
agu_ctrl_o`AGU_AR1_SEL = pm_inst_bus_i[6:5];
end
`DBLST: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[21:17]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[16:12]};
imm_val_o = 0;
dm_data_select_ctrl_o`DM0_SELECT = 1;
agu_ctrl_o`AGU_DM0_WREN = 1'b1;
agu_ctrl_o`AGU_PRE_OP_0 = agu_pre_op0;
agu_ctrl_o`AGU_OTHER_VAL0 = agu_other_val0;
agu_ctrl_o`AGU_MODULO_0 = agu_modulo0;
agu_ctrl_o`AGU_BR0 = agu_br0;
agu_ctrl_o`AGU_AR0_OUT = agu_ar_out0;
agu_ctrl_o`AGU_IMM0_VALUE = agu_imm0;
agu_ctrl_o`AGU_AR0_WREN = agu_ar_wren0;
agu_ctrl_o`AGU_AR0_SEL = pm_inst_bus_i[8:7];
agu_ctrl_o`AGU_DM1_WREN = 1'b1;
agu_ctrl_o`AGU_PRE_OP_1 = agu_pre_op1;
agu_ctrl_o`AGU_OTHER_VAL1 = agu_other_val1;
agu_ctrl_o`AGU_MODULO_1 = agu_modulo1;
agu_ctrl_o`AGU_BR1 = agu_br1;
agu_ctrl_o`AGU_AR1_OUT = agu_ar_out1;
agu_ctrl_o`AGU_IMM1_VALUE = agu_imm1;
agu_ctrl_o`AGU_AR1_WREN = agu_ar_wren1;
agu_ctrl_o`AGU_AR1_SEL = pm_inst_bus_i[6:5];
end
`IN: begin //Tested
io_ctrl_o`IO_ADDR = pm_inst_bus_i[7:0];
io_ctrl_o`IO_RDEN = 1'b1;
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
wb_mux_ctrl_o`WB_MUX_SEL = 4'b1000;
end
`OUT: begin //Tested
io_ctrl_o`IO_ADDR = pm_inst_bus_i[7:0];
io_ctrl_o`IO_WREN = 1'b1;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[21:17]};
end
`ADDN_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OUT = 3'b100;
end
`ADDN_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
imm_val_o = alu_imm12s_extd;
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OUT = 3'b100;
end
`ADDC_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_CIN = 3'b011;
alu_ctrl_o`ALU_OUT = 3'b100;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AV = 2'b01;
alu_ctrl_o`ALU_AC = 3'b011;
alu_ctrl_o`ALU_AN = 2'b01;
end
`ADDC_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
imm_val_o = alu_imm12s_extd;
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_CIN = 3'b011;
alu_ctrl_o`ALU_OUT = 3'b100;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AV = 2'b01;
alu_ctrl_o`ALU_AC = 3'b011;
alu_ctrl_o`ALU_AN = 2'b01;
end
`ADDS_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OUT = 3'b101;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AV = 2'b11;
alu_ctrl_o`ALU_AC = 3'b110;
alu_ctrl_o`ALU_AN = 2'b01;
end
`ADDS_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
imm_val_o = alu_imm12s_extd;
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OUT = 3'b101;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AV = 2'b11;
alu_ctrl_o`ALU_AC = 3'b110;
alu_ctrl_o`ALU_AN = 2'b01;
end
`ADD_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OUT = 3'b100;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AV = 2'b01;
alu_ctrl_o`ALU_AC = 3'b011;
alu_ctrl_o`ALU_AN = 2'b01;
end
`ADD_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
imm_val_o = alu_imm12s_extd;
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OUT = 3'b100;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AV = 2'b01;
alu_ctrl_o`ALU_AC = 3'b011;
alu_ctrl_o`ALU_AN = 2'b01;
end
`SUBN_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OPA = 2'b01;
alu_ctrl_o`ALU_CIN = 3'b001;
alu_ctrl_o`ALU_OUT = 3'b100;
end
`SUBN_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
imm_val_o = alu_imm12s_extd;
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OPA = 2'b01;
alu_ctrl_o`ALU_CIN = 3'b001;
alu_ctrl_o`ALU_OUT = 3'b100;
end
`SUBC_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OPA = 2'b01;
alu_ctrl_o`ALU_CIN = 3'b011;
alu_ctrl_o`ALU_OUT = 3'b100;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AV = 2'b01;
alu_ctrl_o`ALU_AC = 3'b101;
alu_ctrl_o`ALU_AN = 2'b01;
end
`SUBC_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
imm_val_o = alu_imm12s_extd;
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OPA = 2'b01;
alu_ctrl_o`ALU_CIN = 3'b011;
alu_ctrl_o`ALU_OUT = 3'b100;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AV = 2'b01;
alu_ctrl_o`ALU_AC = 3'b101;
alu_ctrl_o`ALU_AN = 2'b01;
end
`SUBS_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OPA = 2'b01;
alu_ctrl_o`ALU_CIN = 3'b001;
alu_ctrl_o`ALU_OUT = 3'b101;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AV = 2'b11;
alu_ctrl_o`ALU_AC = 3'b110;
alu_ctrl_o`ALU_AN = 2'b01;
end
`SUBS_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
imm_val_o = alu_imm12s_extd;
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OPA = 2'b01;
alu_ctrl_o`ALU_CIN = 3'b001;
alu_ctrl_o`ALU_OUT = 3'b101;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AV = 2'b11;
alu_ctrl_o`ALU_AC = 3'b110;
alu_ctrl_o`ALU_AN = 2'b01;
end
`SUB_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OPA = 2'b01;
alu_ctrl_o`ALU_CIN = 3'b001;
alu_ctrl_o`ALU_OUT = 3'b100;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AV = 2'b01;
alu_ctrl_o`ALU_AC = 3'b101;
alu_ctrl_o`ALU_AN = 2'b01;
end
`SUB_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
imm_val_o = alu_imm12s_extd;
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OPA = 2'b01;
alu_ctrl_o`ALU_CIN = 3'b001;
alu_ctrl_o`ALU_OUT = 3'b100;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AV = 2'b01;
alu_ctrl_o`ALU_AC = 3'b101;
alu_ctrl_o`ALU_AN = 2'b01;
end
`CMP_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
alu_ctrl_o`ALU_OPA = 2'b01;
alu_ctrl_o`ALU_CIN = 3'b001;
alu_ctrl_o`ALU_OUT = 3'b100;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AV = 2'b01;
alu_ctrl_o`ALU_AC = 3'b101;
alu_ctrl_o`ALU_AN = 2'b01;
end
`CMP_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
imm_val_o = {pm_inst_bus_i[20:17],pm_inst_bus_i[11:0]};
alu_ctrl_o`ALU_OPA = 2'b01;
alu_ctrl_o`ALU_CIN = 3'b001;
alu_ctrl_o`ALU_OUT = 3'b100;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AV = 2'b01;
alu_ctrl_o`ALU_AC = 3'b101;
alu_ctrl_o`ALU_AN = 2'b01;
end
`MAX_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OPA = 2'b11;
alu_ctrl_o`ALU_OPB = 2'b11;
alu_ctrl_o`ALU_CIN = 3'b001;
alu_ctrl_o`ALU_OUT = 3'b011;
end
`MAX_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
imm_val_o = alu_imm12s_extd;
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OPA = 2'b11;
alu_ctrl_o`ALU_OPB = 2'b11;
alu_ctrl_o`ALU_CIN = 3'b001;
alu_ctrl_o`ALU_OUT = 3'b011;
end
`MIN_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OPA = 2'b11;
alu_ctrl_o`ALU_OPB = 2'b11;
alu_ctrl_o`ALU_CIN = 3'b001;
alu_ctrl_o`ALU_CMP = 1'b1;
alu_ctrl_o`ALU_OUT = 3'b011;
end
`MIN_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
imm_val_o = alu_imm12s_extd;
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OPA = 2'b11;
alu_ctrl_o`ALU_OPB = 2'b11;
alu_ctrl_o`ALU_CIN = 3'b001;
alu_ctrl_o`ALU_CMP = 1'b1;
alu_ctrl_o`ALU_OUT = 3'b011;
end
`ABS: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OPA = 2'b10;
alu_ctrl_o`ALU_OPB = 2'b01;
alu_ctrl_o`ALU_CIN = 3'b010;
alu_ctrl_o`ALU_OUT = {2'b10,pm_inst_bus_i[5]};
alu_ctrl_o`ALU_ABS_SAT = pm_inst_bus_i[5];
end
`ANDN_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OUT = 3'b010;
end
`ANDN_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
imm_val_o = alu_imm12s_extd;
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OUT = 3'b010;
end
`AND_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OUT = 3'b010;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b111;
alu_ctrl_o`ALU_AV = 3'b11;
end
`AND_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
imm_val_o = alu_imm12s_extd;
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_OUT = 3'b010;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b111;
alu_ctrl_o`ALU_AV = 3'b11;
end
`ORN_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_LED = 2'b01;
alu_ctrl_o`ALU_LOGIC = 2'b01;
alu_ctrl_o`ALU_OUT = 3'b010;
end
`ORN_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
imm_val_o = alu_imm12s_extd;
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_LED = 2'b01;
alu_ctrl_o`ALU_LOGIC = 2'b01;
alu_ctrl_o`ALU_OUT = 3'b010;
end
`OR_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_LED = 2'b01;
alu_ctrl_o`ALU_LOGIC = 2'b01;
alu_ctrl_o`ALU_OUT = 3'b010;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b111;
alu_ctrl_o`ALU_AV = 3'b11;
end
`OR_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
imm_val_o = alu_imm12s_extd;
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_LED = 2'b01;
alu_ctrl_o`ALU_LOGIC = 2'b01;
alu_ctrl_o`ALU_OUT = 3'b010;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b111;
alu_ctrl_o`ALU_AV = 3'b11;
end
`XORN_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_LED = 2'b10;
alu_ctrl_o`ALU_LOGIC = 2'b10;
alu_ctrl_o`ALU_OUT = 3'b010;
end
`XORN_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
imm_val_o = alu_imm12s_extd;
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_LED = 2'b10;
alu_ctrl_o`ALU_LOGIC = 2'b10;
alu_ctrl_o`ALU_OUT = 3'b010;
end
`XOR_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_LED = 2'b10;
alu_ctrl_o`ALU_LOGIC = 2'b10;
alu_ctrl_o`ALU_OUT = 3'b010;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b111;
alu_ctrl_o`ALU_AV = 3'b11;
end
`XOR_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
imm_val_o = alu_imm12s_extd;
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_LED = 2'b10;
alu_ctrl_o`ALU_LOGIC = 2'b10;
alu_ctrl_o`ALU_OUT = 3'b010;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b111;
alu_ctrl_o`ALU_AV = 3'b11;
end
`ANDF: begin
rf_ctrl_o`RF_OPA = 6'b100000;
imm_val_o = {11'b0,pm_inst_bus_i[11:7]};
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_AZ = 2'b10;
alu_ctrl_o`ALU_AV = 2'b10;
alu_ctrl_o`ALU_AC = 3'b100;
alu_ctrl_o`ALU_AN = 2'b10;
mac_ctrl_o`MAC_MZ_MUX1 = 1'b1;
mac_ctrl_o`MAC_MN_MUX1 = 1'b1;
mac_ctrl_o`MAC_MS_MUX1 = 1'b1;
mac_ctrl_o`MAC_MV_MUX1 = 1'b1;
end
`ORF: begin
rf_ctrl_o`RF_OPA = 6'b100000;
imm_val_o = {11'b0,pm_inst_bus_i[11:7]};
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_AOX = 2'b01;
alu_ctrl_o`ALU_AZ = 2'b10;
alu_ctrl_o`ALU_AV = 2'b10;
alu_ctrl_o`ALU_AC = 3'b100;
alu_ctrl_o`ALU_AN = 2'b10;
mac_ctrl_o`MAC_MZ_MUX1 = 1'b1;
mac_ctrl_o`MAC_MN_MUX1 = 1'b1;
mac_ctrl_o`MAC_MS_MUX1 = 1'b1;
mac_ctrl_o`MAC_MV_MUX1 = 1'b1;
end
`XORF: begin
rf_ctrl_o`RF_OPA = 6'b100000;
imm_val_o = {11'b0,pm_inst_bus_i[11:7]};
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_AOX = 2'b10;
alu_ctrl_o`ALU_AZ = 2'b10;
alu_ctrl_o`ALU_AV = 2'b10;
alu_ctrl_o`ALU_AC = 3'b100;
alu_ctrl_o`ALU_AN = 2'b10;
mac_ctrl_o`MAC_MZ_MUX1 = 1'b1;
mac_ctrl_o`MAC_MN_MUX1 = 1'b1;
mac_ctrl_o`MAC_MS_MUX1 = 1'b1;
mac_ctrl_o`MAC_MV_MUX1 = 1'b1;
end
`LED_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
end
`LED_2: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
end
`LED_3: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
end
`ASR_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_SHIFT = pm_inst_bus_i[25:23];
alu_ctrl_o`ALU_OUT = 3'b001;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b010;
end
`ASR_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
imm_val_o = alu_imm5z_extd;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_SHIFT = pm_inst_bus_i[25:23];
alu_ctrl_o`ALU_OUT = 3'b001;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b010;
end
`ASL_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_SHIFT = pm_inst_bus_i[25:23];
alu_ctrl_o`ALU_OUT = 3'b001;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b010;
end
`ASL_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
imm_val_o = alu_imm5z_extd;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_SHIFT = pm_inst_bus_i[25:23];
alu_ctrl_o`ALU_OUT = 3'b001;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b010;
end
`LSR_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_SHIFT = pm_inst_bus_i[25:23];
alu_ctrl_o`ALU_OUT = 3'b001;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b010;
end
`LSR_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
imm_val_o = alu_imm5z_extd;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_SHIFT = pm_inst_bus_i[25:23];
alu_ctrl_o`ALU_OUT = 3'b001;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b010;
end
`LSL_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_SHIFT = pm_inst_bus_i[25:23];
alu_ctrl_o`ALU_OUT = 3'b001;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b010;
end
`LSL_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
imm_val_o = alu_imm5z_extd;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_SHIFT = pm_inst_bus_i[25:23];
alu_ctrl_o`ALU_OUT = 3'b001;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b010;
end
`ROR_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_SHIFT = pm_inst_bus_i[25:23];
alu_ctrl_o`ALU_OUT = 3'b001;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b010;
end
`ROR_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
imm_val_o = alu_imm5z_extd;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_SHIFT = pm_inst_bus_i[25:23];
alu_ctrl_o`ALU_OUT = 3'b001;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b010;
end
`ROL_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_SHIFT = pm_inst_bus_i[25:23];
alu_ctrl_o`ALU_OUT = 3'b001;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b010;
end
`ROL_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
imm_val_o = alu_imm5z_extd;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_SHIFT = pm_inst_bus_i[25:23];
alu_ctrl_o`ALU_OUT = 3'b001;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b010;
end
`RCR_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_SHIFT = pm_inst_bus_i[25:23];
alu_ctrl_o`ALU_OUT = 3'b001;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b010;
end
`RCR_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
imm_val_o = alu_imm5z_extd;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_SHIFT = pm_inst_bus_i[25:23];
alu_ctrl_o`ALU_OUT = 3'b001;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b010;
end
`RCL_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_SHIFT = pm_inst_bus_i[25:23];
alu_ctrl_o`ALU_OUT = 3'b001;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b010;
end
`RCL_2: begin
opsel_ctrl_o`OPSEL_OPB = 2;
imm_val_o = alu_imm5z_extd;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0010;
alu_ctrl_o`ALU_SHIFT = pm_inst_bus_i[25:23];
alu_ctrl_o`ALU_OUT = 3'b001;
alu_ctrl_o`ALU_AZ = 2'b01;
alu_ctrl_o`ALU_AN = 2'b01;
alu_ctrl_o`ALU_AC = 3'b010;
end
`ADDL_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_OPBADR = {1'b0, pm_inst_bus_i[11:10]};
mac_ctrl_o`MAC_MUX1 = pm_inst_bus_i[13:12];
mac_ctrl_o`MAC_OPAADR = 3'b010;
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_ADD;
end
`ADDL_2: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_OPBMUL = 1'b1;
mac_ctrl_o`MAC_REGOP = 3'b011;
mac_ctrl_o`MAC_OPBADR = 3'b110;
mac_ctrl_o`MAC_MUX1 = pm_inst_bus_i[13:12];
mac_ctrl_o`MAC_OPAADR = 3'b010;
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_ADD;
end
`ADDL_3: begin
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_OPBMUL = 1'b1;
mac_ctrl_o`MAC_REGOP = 3'b010;
mac_ctrl_o`MAC_OPBADR = 3'b110;
mac_ctrl_o`MAC_MUX1 = pm_inst_bus_i[13:12];
mac_ctrl_o`MAC_OPAADR = 3'b010;
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_ADD;
end
`ADDL_4: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_OPAMUL = 1'b1;
mac_ctrl_o`MAC_OPBMUL = 1'b1;
mac_ctrl_o`MAC_REGOP = 3'b100;
mac_ctrl_o`MAC_OPBADR = 3'b110;
mac_ctrl_o`MAC_MUX1 = pm_inst_bus_i[6:5];
mac_ctrl_o`MAC_OPAADR = 3'b010;
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_ADD;
end // case: `ADDL_4
`ADDL_5: begin
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0001;
mac_ctrl_o`MAC_REGOP = 3'b011; //zero extend
mac_ctrl_o`MAC_MUX1 = pm_inst_bus_i[13:12];
mac_ctrl_o`MAC_SAT = pm_inst_bus_i[5];
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_MS = 1'b1;
mac_ctrl_o`MAC_OPAADR = 3'b010;
mac_ctrl_o`MAC_OPBADR = 3'b110;
mac_ctrl_o`MAC_OUT_RND = pm_inst_bus_i[6];
mac_ctrl_o`MAC_OP = `MAC_ADD;
end
`ADDL_6: begin
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0001;
mac_ctrl_o`MAC_REGOP = 3'b010; //sign extend
mac_ctrl_o`MAC_MUX1 = pm_inst_bus_i[13:12];
mac_ctrl_o`MAC_SAT = pm_inst_bus_i[5];
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_MS = 1'b1;
mac_ctrl_o`MAC_OPAADR = 3'b010;
mac_ctrl_o`MAC_OPBADR = 3'b110;
mac_ctrl_o`MAC_OUT_RND = pm_inst_bus_i[6];
mac_ctrl_o`MAC_OP = `MAC_ADD;
end
`SUBL_1: begin
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_OPBADR = {1'b0, pm_inst_bus_i[11:10]};
mac_ctrl_o`MAC_MUX1 = pm_inst_bus_i[13:12];
mac_ctrl_o`MAC_OPAADR = 3'b010;
mac_ctrl_o`MAC_INV = 2'b01;
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_SUB;
end
`SUBL_2: begin
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_OPBMUL = 1'b1;
mac_ctrl_o`MAC_REGOP = 3'b011;
mac_ctrl_o`MAC_OPBADR = 3'b110;
mac_ctrl_o`MAC_MUX1 = pm_inst_bus_i[13:12];
mac_ctrl_o`MAC_OPAADR = 3'b010;
mac_ctrl_o`MAC_INV = 2'b01;
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_SUB;
end
`SUBL_3: begin
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_OPBMUL = 1'b1;
mac_ctrl_o`MAC_REGOP = 3'b010;
mac_ctrl_o`MAC_OPBADR = 3'b110;
mac_ctrl_o`MAC_MUX1 = pm_inst_bus_i[13:12];
mac_ctrl_o`MAC_OPAADR = 3'b010;
mac_ctrl_o`MAC_INV = 2'b01;
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_SUB;
end
`SUBL_4: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_OPAMUL = 1'b1;
mac_ctrl_o`MAC_OPBMUL = 1'b1;
mac_ctrl_o`MAC_REGOP = 3'b100;
mac_ctrl_o`MAC_OPBADR = 3'b110;
mac_ctrl_o`MAC_MUX1 = pm_inst_bus_i[6:5];
mac_ctrl_o`MAC_OPAADR = 3'b010;
mac_ctrl_o`MAC_INV = 2'b01;
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_SUB;
end
`SUBLST_1: begin
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[4:0]};
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0001;
mac_ctrl_o`MAC_REGOP = 3'b001;
mac_ctrl_o`MAC_SAT = pm_inst_bus_i[5];
mac_ctrl_o`MAC_OPBADR = {1'b0, pm_inst_bus_i[13:12]};
mac_ctrl_o`MAC_OPAADR = 3'b010;
mac_ctrl_o`MAC_MUX1 = 3'b100; // Select regpair
mac_ctrl_o`MAC_INV = 2'b01;
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_MS = 1'b1;
mac_ctrl_o`MAC_OUT_RND = pm_inst_bus_i[6];
mac_ctrl_o`MAC_OP = `MAC_SUB;
//Store (inc addressing mode)
agu_ctrl_o`AGU_DM1_WREN = pm_inst_bus_i[16];
agu_ctrl_o`AGU_DM0_WREN = ~pm_inst_bus_i[16];
agu_ctrl_o`AGU_OUT_MODE = pm_inst_bus_i[16];
agu_ctrl_o`AGU_OTHER_VAL0 = 2'b01;
agu_ctrl_o`AGU_AR0_OUT = 1;
agu_ctrl_o`AGU_AR0_WREN = 1;
agu_ctrl_o`AGU_AR0_SEL = pm_inst_bus_i[15:14];
end
`SUBLST_2: begin
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[21:17];
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[11:7]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[4:0]};
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0001;
mac_ctrl_o`MAC_REGOP = 3'b000;
mac_ctrl_o`MAC_SAT = pm_inst_bus_i[5];
mac_ctrl_o`MAC_OPBADR = {1'b0, pm_inst_bus_i[13:12]};
mac_ctrl_o`MAC_OPAADR = 3'b010;
mac_ctrl_o`MAC_MUX1 = 3'b100; // Select regpair
mac_ctrl_o`MAC_INV = 2'b01;
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_MS = 1'b1;
mac_ctrl_o`MAC_OUT_RND = pm_inst_bus_i[6];
mac_ctrl_o`MAC_OP = `MAC_SUB;
//Store (inc addressing mode)
agu_ctrl_o`AGU_DM1_WREN = pm_inst_bus_i[16];
agu_ctrl_o`AGU_DM0_WREN = ~pm_inst_bus_i[16];
agu_ctrl_o`AGU_OUT_MODE = pm_inst_bus_i[16];
agu_ctrl_o`AGU_OTHER_VAL0 = 2'b01;
agu_ctrl_o`AGU_AR0_OUT = 1;
agu_ctrl_o`AGU_AR0_WREN = 1;
agu_ctrl_o`AGU_AR0_SEL = pm_inst_bus_i[15:14];
end
`CMPL_1: begin
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_OPBADR = {1'b0, pm_inst_bus_i[11:10]};
mac_ctrl_o`MAC_MUX1 = {1'b0, pm_inst_bus_i[13:12]};
mac_ctrl_o`MAC_OPAADR = 3'b010;
mac_ctrl_o`MAC_INV = 2'b01;
mac_ctrl_o`MAC_SAT = 1;
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_MS = 1'b1;
mac_ctrl_o`MAC_OP = `MAC_CMP;
end
`CMPL_2: begin
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_OPBMUL = 1'b1;
mac_ctrl_o`MAC_REGOP = 3'b011;
mac_ctrl_o`MAC_OPBADR = 3'b110;
mac_ctrl_o`MAC_MUX1 = pm_inst_bus_i[13:12];
mac_ctrl_o`MAC_OPAADR = 3'b010;
mac_ctrl_o`MAC_INV = 2'b01;
mac_ctrl_o`MAC_SAT = 1;
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_MS = 1'b1;
mac_ctrl_o`MAC_OP = `MAC_CMP;
end
`CMPL_3: begin
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_OPBMUL = 1'b1;
mac_ctrl_o`MAC_REGOP = 3'b010;
mac_ctrl_o`MAC_OPBADR = 3'b110;
mac_ctrl_o`MAC_MUX1 = pm_inst_bus_i[13:12];
mac_ctrl_o`MAC_OPAADR = 3'b010;
mac_ctrl_o`MAC_INV = 2'b01;
mac_ctrl_o`MAC_SAT = 1;
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_MS = 1'b1;
mac_ctrl_o`MAC_OP = `MAC_CMP;
end
`CMPL_4: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_OPAMUL = 1'b1;
mac_ctrl_o`MAC_OPBMUL = 1'b1;
mac_ctrl_o`MAC_REGOP = 3'b100;
mac_ctrl_o`MAC_OPBADR = 3'b110;
mac_ctrl_o`MAC_MUX1 = pm_inst_bus_i[7:6];
mac_ctrl_o`MAC_OPAADR = 3'b010;
mac_ctrl_o`MAC_SAT = 1;
mac_ctrl_o`MAC_INV = 2'b01;
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_MS = 1'b1;
mac_ctrl_o`MAC_OP = `MAC_CMP;
end
`ABSL_1: begin
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_OPBADR = {1'b0, pm_inst_bus_i[13:12]};
mac_ctrl_o`MAC_INV = 2'b10;
mac_ctrl_o`MAC_SAT = pm_inst_bus_i[5];
mac_ctrl_o`MAC_ABS_SAT = pm_inst_bus_i[5];
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_MS = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_ABS;
end
`ABSL_2: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_REGOP = {2'b0,pm_inst_bus_i[6]};
mac_ctrl_o`MAC_OPBADR = 3'b110;
mac_ctrl_o`MAC_INV = 2'b10;
mac_ctrl_o`MAC_SAT = pm_inst_bus_i[5];
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_MS = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_ABS;
end
`NEGL_1: begin
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_OPBADR = {1'b0, pm_inst_bus_i[13:12]};
mac_ctrl_o`MAC_OPAADR = 3'b000;
mac_ctrl_o`MAC_INV = 2'b01;
mac_ctrl_o`MAC_SAT = pm_inst_bus_i[5];
mac_ctrl_o`MAC_ABS_SAT = pm_inst_bus_i[5];
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_MS = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_NEG;
end
`NEGL_2: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_REGOP = {2'b0,pm_inst_bus_i[6]};
mac_ctrl_o`MAC_OPBADR = 3'b110;
mac_ctrl_o`MAC_OPAADR = 3'b000;
mac_ctrl_o`MAC_INV = 2'b01;
mac_ctrl_o`MAC_SAT = pm_inst_bus_i[5];
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_MS = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_NEG;
end
`MOVEL_1: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_OPAMUL = 1'b1;
mac_ctrl_o`MAC_OPBMUL = 1'b1;
mac_ctrl_o`MAC_REGOP = 3'b100;
mac_ctrl_o`MAC_OPBADR = 3'b110;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_MOVE;
end
`MOVEL_2: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_REGOP = {2'b0,pm_inst_bus_i[6]};
mac_ctrl_o`MAC_OPBADR = 3'b110;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_MOVE;
end
`CLR: begin
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_OPBADR = 3'b101;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_CLR;
end
`POSTOP: begin
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
mac_ctrl_o`MAC_OPBADR = {1'b0, pm_inst_bus_i[11:10]};
mac_ctrl_o`MAC_OPAADR = {1'b0, {2{pm_inst_bus_i[6]}}}; //Rounding
mac_ctrl_o`MAC_SCALE = pm_inst_bus_i[21:19];
mac_ctrl_o`MAC_RND = pm_inst_bus_i[6];
mac_ctrl_o`MAC_SAT = pm_inst_bus_i[5];
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_MS = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_MOVE;
if(pm_inst_bus_i[6]) begin
mac_ctrl_o`MAC_OP = `MAC_MOVE_ROUND;
end
end
`MUL: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
mac_ctrl_o`MAC_OPAMUL = 1'b1;
mac_ctrl_o`MAC_OPBMUL = 1'b1;
mac_ctrl_o`MAC_OPASGN = pm_inst_bus_i[6];
mac_ctrl_o`MAC_OPBSGN = pm_inst_bus_i[5];
mac_ctrl_o`MAC_OPBADR = 3'b100;
mac_ctrl_o`MAC_SCALE = pm_inst_bus_i[21:19];
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_MUL;
end
`MAC: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
mac_ctrl_o`MAC_OPAMUL = 1'b1;
mac_ctrl_o`MAC_OPBMUL = 1'b1;
mac_ctrl_o`MAC_OPASGN = pm_inst_bus_i[6];
mac_ctrl_o`MAC_OPBSGN = pm_inst_bus_i[5];
mac_ctrl_o`MAC_OPBADR = 3'b100;
mac_ctrl_o`MAC_OPAADR = 3'b010;
mac_ctrl_o`MAC_SCALE = pm_inst_bus_i[21:19];
mac_ctrl_o`MAC_MUX1 = pm_inst_bus_i[18:17];
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_MAC;
end
`MDM: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
mac_ctrl_o`MAC_OPAMUL = 1'b1;
mac_ctrl_o`MAC_OPBMUL = 1'b1;
mac_ctrl_o`MAC_OPASGN = pm_inst_bus_i[6];
mac_ctrl_o`MAC_OPBSGN = pm_inst_bus_i[5];
mac_ctrl_o`MAC_OPBADR = 3'b100;
mac_ctrl_o`MAC_MUX1 = pm_inst_bus_i[18:17];
mac_ctrl_o`MAC_OPAADR = 3'b010;
mac_ctrl_o`MAC_SCALE = pm_inst_bus_i[21:19];
mac_ctrl_o`MAC_INV = 2'b01;
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_MDM;
end
`MULLD: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
mac_ctrl_o`MAC_OPAMUL = 1'b1;
mac_ctrl_o`MAC_OPBMUL = 1'b1;
mac_ctrl_o`MAC_OPASGN = 1'b1;
mac_ctrl_o`MAC_OPBSGN = 1'b1;
mac_ctrl_o`MAC_OPBADR = 3'b100;
mac_ctrl_o`MAC_SCALE = 0;
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_MUL;
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[6:2];
imm_val_o = 0;
wb_mux_ctrl_o`WB_MUX_SEL = {3'b010, pm_inst_bus_i[1]};
agu_ctrl_o`AGU_OUT_MODE = pm_inst_bus_i[1];
agu_ctrl_o`AGU_PRE_OP_0 = agu_pre_op0;
agu_ctrl_o`AGU_OTHER_VAL0 = agu_other_val0;
agu_ctrl_o`AGU_MODULO_0 = agu_modulo0;
agu_ctrl_o`AGU_BR0 = agu_br0;
agu_ctrl_o`AGU_AR0_OUT = agu_ar_out0;
agu_ctrl_o`AGU_IMM0_VALUE = agu_imm0;
agu_ctrl_o`AGU_AR0_WREN = agu_ar_wren0;
agu_ctrl_o`AGU_AR0_SEL = pm_inst_bus_i[26:25];
end
`MACLD: begin
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
mac_ctrl_o`MAC_OPAMUL = 1'b1;
mac_ctrl_o`MAC_OPBMUL = 1'b1;
mac_ctrl_o`MAC_OPASGN = 1'b1;
mac_ctrl_o`MAC_OPBSGN = 1'b1;
mac_ctrl_o`MAC_OPBADR = 3'b100;
mac_ctrl_o`MAC_OPAADR = 3'b010;
mac_ctrl_o`MAC_SCALE = 0;
mac_ctrl_o`MAC_MUX1 = pm_inst_bus_i[18:17];
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_MAC;
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[6:2];
imm_val_o = 0;
wb_mux_ctrl_o`WB_MUX_SEL = {3'b010, pm_inst_bus_i[1]};
agu_ctrl_o`AGU_OUT_MODE = pm_inst_bus_i[1];
agu_ctrl_o`AGU_PRE_OP_0 = agu_pre_op0;
agu_ctrl_o`AGU_OTHER_VAL0 = agu_other_val0;
agu_ctrl_o`AGU_MODULO_0 = agu_modulo0;
agu_ctrl_o`AGU_BR0 = agu_br0;
agu_ctrl_o`AGU_AR0_OUT = agu_ar_out0;
agu_ctrl_o`AGU_IMM0_VALUE = agu_imm0;
agu_ctrl_o`AGU_AR0_WREN = agu_ar_wren0;
agu_ctrl_o`AGU_AR0_SEL = pm_inst_bus_i[26:25];
end
`MULDBLLD: begin
// rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[21:19], pm_inst_bus_i[16:15]};
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
rf_ctrl_o`RF_OPB = {1'b0, pm_inst_bus_i[11:7]};
mac_ctrl_o`MAC_OPAMUL = 1'b1;
mac_ctrl_o`MAC_OPBMUL = 1'b1;
mac_ctrl_o`MAC_OPASGN = 1'b1;
mac_ctrl_o`MAC_OPBSGN = 1'b1;
mac_ctrl_o`MAC_OPBADR = 3'b100;
mac_ctrl_o`MAC_SCALE = 0;
mac_ctrl_o`MAC_MV = 1'b1;
mac_ctrl_o`MAC_MZ = 1'b1;
mac_ctrl_o`MAC_MN = 1'b1;
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
mac_ctrl_o`MAC_OP = `MAC_MUL;
rf_ctrl_o`RF_WRITE_REG_EN = 1'b1;
rf_ctrl_o`RF_WRITE_REG_SEL = pm_inst_bus_i[6:2];
rf_ctrl_o`RF_WRITE_REG_EN_DM = 1'b1;
rf_ctrl_o`RF_WRITE_REG_SEL_DM = {pm_inst_bus_i[21:19], pm_inst_bus_i[1:0]};
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0100;
imm_val_o = 0;
agu_ctrl_o`AGU_PRE_OP_0 = agu_pre_op0;
agu_ctrl_o`AGU_OTHER_VAL0 = agu_other_val0;
agu_ctrl_o`AGU_MODULO_0 = agu_modulo0;
agu_ctrl_o`AGU_BR0 = agu_br0;
agu_ctrl_o`AGU_AR0_OUT = agu_ar_out0;
agu_ctrl_o`AGU_IMM0_VALUE = agu_imm0;
agu_ctrl_o`AGU_AR0_WREN = agu_ar_wren0;
agu_ctrl_o`AGU_AR0_SEL = 2'b00;
agu_ctrl_o`AGU_PRE_OP_1 = agu_pre_op1;
agu_ctrl_o`AGU_OTHER_VAL1 = agu_other_val1;
agu_ctrl_o`AGU_MODULO_1 = agu_modulo1;
agu_ctrl_o`AGU_BR1 = agu_br1;
agu_ctrl_o`AGU_AR1_OUT = agu_ar_out1;
agu_ctrl_o`AGU_IMM1_VALUE = agu_imm1;
agu_ctrl_o`AGU_AR1_WREN = agu_ar_wren1;
agu_ctrl_o`AGU_AR1_SEL = 2'b01;
end
`CONV: begin
mac_ctrl_o`MAC_OPASGN = pm_inst_bus_i[6];
mac_ctrl_o`MAC_OPBSGN = pm_inst_bus_i[5];
mac_ctrl_o`MAC_OPBADR = 3'b100;
mac_ctrl_o`MAC_MUX1 = pm_inst_bus_i[18:17];
mac_ctrl_o`MAC_OPAADR = 3'b010;
mac_ctrl_o`MAC_SCALE = pm_inst_bus_i[21:19];
mac_ctrl_o`MAC_INV = {1'b0,pm_inst_bus_i[3]};
//mac_ctrl_o`MAC_MV = 1'b1; //FIXME: why is this not set during convolution
mac_ctrl_o`MAC_GACR01 = gacr01;
mac_ctrl_o`MAC_GACR23 = gacr23;
mac_ctrl_o`MAC_HACR0 = hacr[0];
mac_ctrl_o`MAC_LACR0 = lacr[0];
mac_ctrl_o`MAC_HACR1 = hacr[1];
mac_ctrl_o`MAC_LACR1 = lacr[1];
mac_ctrl_o`MAC_HACR2 = hacr[2];
mac_ctrl_o`MAC_LACR2 = lacr[2];
mac_ctrl_o`MAC_HACR3 = hacr[3];
mac_ctrl_o`MAC_LACR3 = lacr[3];
loop_counter_ctrl_o`LC_LOOPE = 1'b1;
loop_counter_ctrl_o`LC_LOOPB = 1'b1;
if(pm_inst_bus_i[3]) begin
mac_ctrl_o`MAC_OP = `MAC_MDM;
end else begin
mac_ctrl_o`MAC_OP = `MAC_MAC;
end
agu_ctrl_o`AGU_PRE_OP_0 = agu_pre_op0;
agu_ctrl_o`AGU_OTHER_VAL0 = agu_other_val0;
agu_ctrl_o`AGU_MODULO_0 = agu_modulo0;
agu_ctrl_o`AGU_BR0 = agu_br0;
agu_ctrl_o`AGU_AR0_OUT = agu_ar_out0;
agu_ctrl_o`AGU_IMM0_VALUE = agu_imm0;
agu_ctrl_o`AGU_AR0_WREN = agu_ar_wren0;
agu_ctrl_o`AGU_AR0_SEL = pm_inst_bus_i[13:12];
agu_ctrl_o`AGU_PRE_OP_1 = agu_pre_op1;
agu_ctrl_o`AGU_OTHER_VAL1 = agu_other_val1;
agu_ctrl_o`AGU_MODULO_1 = agu_modulo1;
agu_ctrl_o`AGU_BR1 = agu_br1;
agu_ctrl_o`AGU_AR1_OUT = agu_ar_out1;
agu_ctrl_o`AGU_IMM1_VALUE = agu_imm1;
agu_ctrl_o`AGU_AR1_WREN = agu_ar_wren1;
agu_ctrl_o`AGU_AR1_SEL = pm_inst_bus_i[8:7];
end
`REP: begin
if (pm_inst_bus_i[6:0] == 7'b0000001)
pc_fsm_ctrl_o`PFC_REPEAT_X = 1'b1;
else
pc_fsm_ctrl_o`PFC_REPEAT_X = 1'b0;
imm_val_o = {4'b0,pm_inst_bus_i[21:10]};
loop_counter_ctrl_o`LC_LOOPE = 1'b1;
loop_counter_ctrl_o`LC_LOOPB = 1'b1;
loop_counter_ctrl_o`LC_LOOPN1 = 1'b1;
loop_counter_ctrl_o`LC_LOOPB1 = 1'b1;
loop_counter_ctrl_o`LC_LOOPE1 = 1'b1;
loop_counter_ctrl_o`LC_LOOPN_VAL = {4'b0,pm_inst_bus_i[21:10]};
loop_counter_ctrl_o`LC_LOOPE_VAL = {9'b0,pm_inst_bus_i[6:0]};
end
`JUMP_1: begin
pc_fsm_ctrl_o`PFC_JUMP = 1'b1; // immediate not clocked
pc_fsm_ctrl_o`PFC_DELAY_SLOT = pm_inst_bus_i[28:27];//--PFC-- delay value
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
end
`JUMP_2: begin
pc_fsm_ctrl_o`PFC_JUMP = 1'b1; // immediate not clocked
pc_fsm_ctrl_o`PFC_DELAY_SLOT = pm_inst_bus_i[28:27];//--PFC-- delay value
rf_ctrl_o`RF_OPA = 6'b100000;
imm_val_o = pm_inst_bus_i[21:6];
cond_logic_ctrl_o = pm_inst_bus_i[4:0];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0;
end
`CALL_1: begin
pc_fsm_ctrl_o`PFC_JUMP = 1'b1; // immediate not clocked
pc_fsm_ctrl_o`PFC_DELAY_SLOT = pm_inst_bus_i[28:27];//--PFC-- delay value
rf_ctrl_o`RF_OPA = {1'b0, pm_inst_bus_i[16:12]};
pc_fsm_ctrl_o`PFC_CALL = 1'b1;
if (pm_inst_bus_i[28:27] == 2'b11) begin
dm_data_select_ctrl_o`DM1_SELECT = 2'b10;
end
else begin
dm_data_select_ctrl_o`DM1_SELECT = 2'b01;
end
agu_ctrl_o`AGU_DM1_WREN = 1'b1;
agu_ctrl_o`AGU_PRE_OP_0 = 0;
agu_ctrl_o`AGU_OTHER_VAL0 = 2'b01;
agu_ctrl_o`AGU_MODULO_0 = 0;
agu_ctrl_o`AGU_BR0 = 0;
agu_ctrl_o`AGU_AR0_OUT = 1;
agu_ctrl_o`AGU_IMM0_VALUE = 0;
agu_ctrl_o`AGU_AR0_WREN = 0;
agu_ctrl_o`AGU_AR0_SEL = 0;
agu_ctrl_o`AGU_OUT_MODE = 1;
agu_ctrl_o`AGU_SP_EN = 1;
end
`CALL_2: begin
pc_fsm_ctrl_o`PFC_JUMP = 1'b1; // immediate not clocked
pc_fsm_ctrl_o`PFC_DELAY_SLOT = pm_inst_bus_i[28:27];//--PFC-- delay value
imm_val_o = pm_inst_bus_i[21:6];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0;
pc_fsm_ctrl_o`PFC_CALL = 1'b1;
if (pm_inst_bus_i[28:27] == 2'b11) begin
dm_data_select_ctrl_o`DM1_SELECT = 2'b10;
end
else begin
dm_data_select_ctrl_o`DM1_SELECT = 2'b01;
end
rf_ctrl_o`RF_OPA = 6'b100000;
agu_ctrl_o`AGU_DM1_WREN = 1'b1;
agu_ctrl_o`AGU_PRE_OP_0 = 0;
agu_ctrl_o`AGU_OTHER_VAL0 = 2'b01;
agu_ctrl_o`AGU_MODULO_0 = 0;
agu_ctrl_o`AGU_BR0 = 0;
agu_ctrl_o`AGU_AR0_OUT = 1;
agu_ctrl_o`AGU_IMM0_VALUE = 0;
agu_ctrl_o`AGU_AR0_WREN = 0;
agu_ctrl_o`AGU_AR0_SEL = 0;
agu_ctrl_o`AGU_OUT_MODE = 1;
agu_ctrl_o`AGU_SP_EN = 1;
end
`NOP: begin
end
`RET: begin
pc_fsm_ctrl_o`PFC_RET = 1'b1;
pc_fsm_ctrl_o`PFC_JUMP = 1'b1; // immediate not clocked
pc_fsm_ctrl_o`PFC_DELAY_SLOT = pm_inst_bus_i[28:27];//--PFC-- delay value
agu_ctrl_o`AGU_PRE_OP_0 = 1;
agu_ctrl_o`AGU_OTHER_VAL0 = 2'b11;
agu_ctrl_o`AGU_MODULO_0 = 0;
agu_ctrl_o`AGU_BR0 = 0;
agu_ctrl_o`AGU_AR0_OUT = 1;
agu_ctrl_o`AGU_IMM0_VALUE = 0;
agu_ctrl_o`AGU_AR0_WREN = 0;
agu_ctrl_o`AGU_AR0_SEL = 0;
agu_ctrl_o`AGU_OUT_MODE = 1;
agu_ctrl_o`AGU_SP_EN = 1;
end
`RETI: begin
imm_val_o = pm_inst_bus_i[21:6];
pc_fsm_ctrl_o`PFC_RET = 1'b1;
end
`SLEEP_1: begin
end
`SLEEP_2: begin
rf_ctrl_o`RF_OPA = 6'b100000;
imm_val_o = pm_inst_bus_i[21:6];
wb_mux_ctrl_o`WB_MUX_SEL = 4'b0;
end
endcase
end
always@* begin
alu_ctrl_o`ALU_STUD = 0;
casez(pm_inst_bus_i[31:22])
`ADDN_1,
`ADDN_2,
`ADDS_1,
`ADDS_2,
`ADD_1,
`ADD_2: begin
alu_ctrl_o`ALU_FUNCTION = 3'b000;
end
`ADDC_1,
`ADDC_2: begin
alu_ctrl_o`ALU_FUNCTION = 3'b001;
end
`SUBN_1,
`SUBN_2,
`SUBS_1,
`SUBS_2,
`SUB_1,
`SUB_2: begin
alu_ctrl_o`ALU_FUNCTION = 3'b010;
end
`SUBC_1,
`SUBC_2: begin
alu_ctrl_o`ALU_FUNCTION = 3'b011;
end
`ABS: begin
alu_ctrl_o`ALU_FUNCTION = 3'b100;
end
`CMP_1,
`CMP_2: begin
alu_ctrl_o`ALU_FUNCTION = 3'b101;
end
`MAX_1,
`MAX_2: begin
alu_ctrl_o`ALU_FUNCTION = 3'b110;
end
`MIN_1,
`MIN_2: begin
alu_ctrl_o`ALU_FUNCTION = 3'b111;
end
endcase
end
endmodule // ID_new
|
module user_design(clk, rst, exception, input_timer, input_rs232_rx, input_ps2, input_i2c, input_switches, input_eth_rx, input_buttons, input_timer_stb, input_rs232_rx_stb, input_ps2_stb, input_i2c_stb, input_switches_stb, input_eth_rx_stb, input_buttons_stb, input_timer_ack, input_rs232_rx_ack, input_ps2_ack, input_i2c_ack, input_switches_ack, input_eth_rx_ack, input_buttons_ack, output_seven_segment_annode, output_eth_tx, output_rs232_tx, output_leds, output_audio, output_led_g, output_seven_segment_cathode, output_led_b, output_i2c, output_vga, output_led_r, output_seven_segment_annode_stb, output_eth_tx_stb, output_rs232_tx_stb, output_leds_stb, output_audio_stb, output_led_g_stb, output_seven_segment_cathode_stb, output_led_b_stb, output_i2c_stb, output_vga_stb, output_led_r_stb, output_seven_segment_annode_ack, output_eth_tx_ack, output_rs232_tx_ack, output_leds_ack, output_audio_ack, output_led_g_ack, output_seven_segment_cathode_ack, output_led_b_ack, output_i2c_ack, output_vga_ack, output_led_r_ack);
input clk;
input rst;
output exception;
input [31:0] input_timer;
input input_timer_stb;
output input_timer_ack;
input [31:0] input_rs232_rx;
input input_rs232_rx_stb;
output input_rs232_rx_ack;
input [31:0] input_ps2;
input input_ps2_stb;
output input_ps2_ack;
input [31:0] input_i2c;
input input_i2c_stb;
output input_i2c_ack;
input [31:0] input_switches;
input input_switches_stb;
output input_switches_ack;
input [31:0] input_eth_rx;
input input_eth_rx_stb;
output input_eth_rx_ack;
input [31:0] input_buttons;
input input_buttons_stb;
output input_buttons_ack;
output [31:0] output_seven_segment_annode;
output output_seven_segment_annode_stb;
input output_seven_segment_annode_ack;
output [31:0] output_eth_tx;
output output_eth_tx_stb;
input output_eth_tx_ack;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
input output_rs232_tx_ack;
output [31:0] output_leds;
output output_leds_stb;
input output_leds_ack;
output [31:0] output_audio;
output output_audio_stb;
input output_audio_ack;
output [31:0] output_led_g;
output output_led_g_stb;
input output_led_g_ack;
output [31:0] output_seven_segment_cathode;
output output_seven_segment_cathode_stb;
input output_seven_segment_cathode_ack;
output [31:0] output_led_b;
output output_led_b_stb;
input output_led_b_ack;
output [31:0] output_i2c;
output output_i2c_stb;
input output_i2c_ack;
output [31:0] output_vga;
output output_vga_stb;
input output_vga_ack;
output [31:0] output_led_r;
output output_led_r_stb;
input output_led_r_ack;
wire exception_139931275014224;
wire exception_139931284058264;
wire exception_139931275014800;
wire exception_139931283364248;
wire exception_139931277768032;
wire exception_139931277612960;
wire exception_139931282859432;
wire exception_139931283977280;
wire exception_139931280790448;
wire exception_139931278706448;
wire exception_139931285244168;
wire exception_139931283531752;
wire exception_139931284930360;
wire exception_139931278105848;
wire exception_139931283236408;
wire exception_139931278705368;
main_0 main_0_139931275014224(
.clk(clk),
.rst(rst),
.exception(exception_139931275014224),
.input_i2c_in(input_i2c),
.input_i2c_in_stb(input_i2c_stb),
.input_i2c_in_ack(input_i2c_ack),
.output_rs232_tx(output_rs232_tx),
.output_rs232_tx_stb(output_rs232_tx_stb),
.output_rs232_tx_ack(output_rs232_tx_ack),
.output_i2c_out(output_i2c),
.output_i2c_out_stb(output_i2c_stb),
.output_i2c_out_ack(output_i2c_ack));
main_1 main_1_139931284058264(
.clk(clk),
.rst(rst),
.exception(exception_139931284058264),
.input_in(input_timer),
.input_in_stb(input_timer_stb),
.input_in_ack(input_timer_ack));
main_2 main_2_139931275014800(
.clk(clk),
.rst(rst),
.exception(exception_139931275014800),
.input_in(input_rs232_rx),
.input_in_stb(input_rs232_rx_stb),
.input_in_ack(input_rs232_rx_ack));
main_3 main_3_139931283364248(
.clk(clk),
.rst(rst),
.exception(exception_139931283364248),
.input_in(input_ps2),
.input_in_stb(input_ps2_stb),
.input_in_ack(input_ps2_ack));
main_4 main_4_139931277768032(
.clk(clk),
.rst(rst),
.exception(exception_139931277768032),
.input_in(input_switches),
.input_in_stb(input_switches_stb),
.input_in_ack(input_switches_ack));
main_5 main_5_139931277612960(
.clk(clk),
.rst(rst),
.exception(exception_139931277612960),
.input_in(input_eth_rx),
.input_in_stb(input_eth_rx_stb),
.input_in_ack(input_eth_rx_ack));
main_6 main_6_139931282859432(
.clk(clk),
.rst(rst),
.exception(exception_139931282859432),
.input_in(input_buttons),
.input_in_stb(input_buttons_stb),
.input_in_ack(input_buttons_ack));
main_7 main_7_139931283977280(
.clk(clk),
.rst(rst),
.exception(exception_139931283977280),
.output_out(output_seven_segment_annode),
.output_out_stb(output_seven_segment_annode_stb),
.output_out_ack(output_seven_segment_annode_ack));
main_8 main_8_139931280790448(
.clk(clk),
.rst(rst),
.exception(exception_139931280790448),
.output_out(output_eth_tx),
.output_out_stb(output_eth_tx_stb),
.output_out_ack(output_eth_tx_ack));
main_9 main_9_139931278706448(
.clk(clk),
.rst(rst),
.exception(exception_139931278706448),
.output_out(output_leds),
.output_out_stb(output_leds_stb),
.output_out_ack(output_leds_ack));
main_10 main_10_139931285244168(
.clk(clk),
.rst(rst),
.exception(exception_139931285244168),
.output_out(output_audio),
.output_out_stb(output_audio_stb),
.output_out_ack(output_audio_ack));
main_11 main_11_139931283531752(
.clk(clk),
.rst(rst),
.exception(exception_139931283531752),
.output_out(output_led_g),
.output_out_stb(output_led_g_stb),
.output_out_ack(output_led_g_ack));
main_12 main_12_139931284930360(
.clk(clk),
.rst(rst),
.exception(exception_139931284930360),
.output_out(output_seven_segment_cathode),
.output_out_stb(output_seven_segment_cathode_stb),
.output_out_ack(output_seven_segment_cathode_ack));
main_13 main_13_139931278105848(
.clk(clk),
.rst(rst),
.exception(exception_139931278105848),
.output_out(output_led_b),
.output_out_stb(output_led_b_stb),
.output_out_ack(output_led_b_ack));
main_14 main_14_139931283236408(
.clk(clk),
.rst(rst),
.exception(exception_139931283236408),
.output_out(output_vga),
.output_out_stb(output_vga_stb),
.output_out_ack(output_vga_ack));
main_15 main_15_139931278705368(
.clk(clk),
.rst(rst),
.exception(exception_139931278705368),
.output_out(output_led_r),
.output_out_stb(output_led_r_stb),
.output_out_ack(output_led_r_ack));
assign exception = exception_139931275014224 || exception_139931284058264 || exception_139931275014800 || exception_139931283364248 || exception_139931277768032 || exception_139931277612960 || exception_139931282859432 || exception_139931283977280 || exception_139931280790448 || exception_139931278706448 || exception_139931285244168 || exception_139931283531752 || exception_139931284930360 || exception_139931278105848 || exception_139931283236408 || exception_139931278705368;
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_always_assert
assert_always_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_always_assume
assert_always_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_always.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_always_assert (clk, reset_n, test_expr, xzcheck_enable);
input clk, reset_n, test_expr, xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_always_assume (clk, reset_n, test_expr, xzcheck_enable);
input clk, reset_n, test_expr, xzcheck_enable;
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2020 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file msu_databuf.v when simulating
// the core, msu_databuf. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module msu_databuf(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [13 : 0] addra;
input [7 : 0] dina;
input clkb;
input [13 : 0] addrb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_1 #(
.C_ADDRA_WIDTH(14),
.C_ADDRB_WIDTH(14),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(16384),
.C_READ_DEPTH_B(16384),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(16384),
.C_WRITE_DEPTH_B(16384),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_SN_TB_V
`define SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_SN_TB_V
/**
* udp_dff$NR_pp$PKG$sN: Negative edge triggered D flip-flop with
* active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_dff_nr_pp_pkg_sn.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg SLEEP_B;
reg NOTIFIER;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 NOTIFIER = 1'b0;
#80 RESET = 1'b0;
#100 SLEEP_B = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 KAPWR = 1'b1;
#200 NOTIFIER = 1'b1;
#220 RESET = 1'b1;
#240 SLEEP_B = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 KAPWR = 1'b0;
#340 NOTIFIER = 1'b0;
#360 RESET = 1'b0;
#380 SLEEP_B = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 SLEEP_B = 1'b1;
#500 RESET = 1'b1;
#520 NOTIFIER = 1'b1;
#540 KAPWR = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 SLEEP_B = 1'bx;
#640 RESET = 1'bx;
#660 NOTIFIER = 1'bx;
#680 KAPWR = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_lp__udp_dff$NR_pp$PKG$sN dut (.D(D), .RESET(RESET), .SLEEP_B(SLEEP_B), .NOTIFIER(NOTIFIER), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_SN_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FA_2_V
`define SKY130_FD_SC_LS__FA_2_V
/**
* fa: Full adder.
*
* Verilog wrapper for fa with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fa.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fa_2 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fa_2 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__FA_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAH_BLACKBOX_V
`define SKY130_FD_SC_LS__FAH_BLACKBOX_V
/**
* fah: Full adder.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fah (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAH_BLACKBOX_V
|
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