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////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// ii2dcam.v: indirectly-indexed 2D BCAM (II2DCAM) top hierarchy //
// //
// Author: Ameer M. S. Abdelhadi ( [email protected] ; [email protected] ) //
// SRAM-based Modular II-2D-BCAM ; The University of British Columbia , Sep. 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
// include config file for synthesis mode
`ifndef SIM
`include "config.vh"
`endif
module ii2dcam
#( parameter CDEP = `CDEP , // CAM depth (k-entries, power of 2)
parameter PWID = `PWID , // pattern width (9-bits multiply)
parameter PIPE = `PIPE , // pipelined?
parameter REGI = `REGI , // register inputs?
parameter REGO = `REGO ) // register outputs?
( input clk , // clock
input rst , // global reset
input wEnb , // write enable
input [`log2(CDEP)+9:0] wAddr , // write address
input [PWID*9-1:0] mPatt , // match pattern
input [PWID*9-1:0] wPatt , // write pattern
output match , // match
output [`log2(CDEP)+9:0] mAddr ); // match indicators
// register inputs
reg wEnbR ;
reg [`log2(CDEP)+9:0] wAddrR;
reg [PWID*9-1:0] mPattR;
reg [PWID*9-1:0] wPattR;
wire wEnbI ;
wire [`log2(CDEP)+9:0] wAddrI;
wire [PWID*9-1:0] mPattI;
wire [PWID*9-1:0] wPattI;
always @(posedge clk, posedge rst)
if (rst) {wEnbR,wAddrR,mPattR,wPattR} <= {(`log2(CDEP)+18*PWID+11){1'b0}};
else {wEnbR,wAddrR,mPattR,wPattR} <=
{wEnb ,wAddr ,mPatt ,wPatt } ;
assign {wEnbI,wAddrI,mPattI,wPattI} = REGI ?
{wEnbR,wAddrR,mPattR,wPattR} :
{wEnb ,wAddr ,mPatt ,wPatt } ;
// register outputs
reg matchR;
reg [`log2(CDEP)+9:0] mAddrR;
wire matchI;
wire [`log2(CDEP)+9:0] mAddrI;
always @(posedge clk, posedge rst)
if (rst) {matchR,mAddrR} <= {(`log2(CDEP)+11){1'b0}};
else {matchR,mAddrR} <=
{matchI,mAddrI} ;
assign {match ,mAddr } = REGO ?
{matchR,mAddrR} :
{matchI,mAddrI} ;
// instantiate slices of ii2dcam9b for each 9-bits of pattern
wire [CDEP*1024-1:0] mIndc_i [PWID-1:0];
genvar gi;
generate
for (gi=0 ; gi<PWID ; gi=gi+1) begin: STG
// instantiate ii2dcam9b
ii2dcam9b #( .CDEP (CDEP ), // depth (k-entries)
.PIPE (PIPE )) // pipelined?
ii2dcam9bi ( .clk (clk ), // clock // input
.rst (rst ), // global reset // input
.wEnb (wEnbI ), // write enable // input
.wAddr(wAddrI ), // write address // input [`log2(DEP)+9:0]
.mPatt(mPattI[gi*9 +: 9]), // match pattern // input [8 :0]
.wPatt(wPattI[gi*9 +: 9]), // write pattern // input [8 :0]
.mIndc(mIndc_i[gi] )); // match indicators // output [DEP*1024-1:0]
end
endgenerate
// cascading by AND'ing matches
integer i;
reg [CDEP*1024-1:0] mIndc; // match one-hot
always @(*) begin
mIndc = {(CDEP*1024){1'b1}};
for (i=0; i<PWID; i=i+1)
mIndc = mIndc & mIndc_i[i];
end
// binary match (priority encoded) with CDEPx1k width
`ifdef SIM
pe_bhv #( .OHW(CDEP*1024) ) // behavioural priority encoder
`else
pe_cam // generated automatically by ./pe script
`endif
pe_cam_inst (
.clk(clk ), // clock for pipelined priority encoder
.rst(rst ), // registers reset for pipelined priority encoder
.oht(mIndc ), // one-hot match input / in : [ CDEP -1:0]
.bin(mAddrI), // first match index / out: [`log2(CDEP)-1:0]
.vld(matchI) // match indicator / out
);
endmodule
|
// file: Clk_Wizard.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// VGA_clock___108.025______0.000______50.0______144.053____157.495
// Main_clock____99.432______0.000______50.0______146.499____157.495
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "Clk_Wizard,clk_wiz_v5_3_3_0,{component_name=Clk_Wizard,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module Clk_Wizard
(
// Clock out ports
output VGA_clock,
output Main_clock,
// Status and control signals
input resetn,
output locked,
// Clock in ports
input Clock_Board
);
Clk_Wizard_clk_wiz inst
(
// Clock out ports
.VGA_clock(VGA_clock),
.Main_clock(Main_clock),
// Status and control signals
.resetn(resetn),
.locked(locked),
// Clock in ports
.Clock_Board(Clock_Board)
);
endmodule
|
// diseño de una fifo ciclica, para implementar en cada bloque de proyecto
// ferney alberto beltran 2016 electrónica digital 1 universidad Nacional
module fifo
#(
parameter adr_width = 4,
parameter dat_width = 8
)
(
input clk, reset,
input rd, wr,
input [dat_width-1:0] data_in,
output [dat_width-1:0] data_out,
output empty,
output full
);
parameter depth = (1 << adr_width);
//declaración de registros
reg [dat_width-1:0] array_reg [depth-1:0];// register array FIFO
reg [adr_width-1:0] w_ptr_reg, w_ptr_next;
reg [adr_width-1:0] r_ptr_reg, r_ptr_next;
reg full_reg, empty_reg, full_next, empty_next;
wire wr_en;
reg [1:0] orden;
assign data_out = array_reg[r_ptr_reg];
assign wr_en = wr & ~full_reg;
assign full = full_reg;
assign empty = empty_reg;
always @(posedge clk) begin
if (wr_en)
array_reg[w_ptr_reg] <= data_in;
end
// fifo control logic
// register for read and write pointers
always @(posedge clk, posedge reset) begin
if (reset)
begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
end
else
begin
w_ptr_reg <= w_ptr_next;
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
end
always @(posedge clk)
begin
if(wr&&!rd)
begin
orden = 2'b01;
end
if(!wr&&rd)
begin
orden = 2'b10;
end
if(wr&&rd)
begin
orden = 2'b11;
end
end
//always @(posedge reset or posedge wr or posedge rd)
always @(posedge clk)
begin
if (reset) begin
w_ptr_next = 0;
r_ptr_next = 0;
end else begin
full_next = full_reg;
empty_next = empty_reg;
case (orden)
2'b01: // read
if (~empty_reg) // not empty
begin
r_ptr_next = r_ptr_reg + 1;
full_next = 1'b0;
if (r_ptr_next==w_ptr_reg)
empty_next = 1'b1;
end
2'b10: // write
if (~full_reg) // not full
begin
w_ptr_next = w_ptr_reg + 1;
empty_next = 1'b0;
if (w_ptr_next==r_ptr_reg)
full_next = 1'b1;
end
2'b11: // write and read
begin
w_ptr_next = w_ptr_reg + 1;
r_ptr_next = r_ptr_reg + 1;
end
endcase
end
end
endmodule
|
/*!
* <b>Module:</b>ahci_sata_layers
* @file ahci_sata_layers.v
* @date 2016-01-19
* @author Andrey Filippov
*
* @brief Link and PHY SATA layers
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_sata_layers.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ahci_sata_layers.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*/
`timescale 1ns/1ps
//`define CHECK_LOW_H2D_FIFO // reduce actual h2d fifo size during simulation, to test h2d_ready
/** TODO:
1. Check nothing is left in H2D FIFO after data is sent - it will happen after DPATp received.
2. Make DPATp an error? It is not easy to insert 0x00000046" data FIS header before remaining data (already in FIS)
- it may also hold fis_transmit, as maximal data fis is 4x of the FIFO size.
*/
module ahci_sata_layers #(
`ifdef USE_DATASCOPE
parameter ADDRESS_BITS = 10, //for datascope
parameter DATASCOPE_START_BIT = 14, // bit of DRP "other_control" to start recording after 0->1 (needs DRP)
parameter DATASCOPE_POST_MEAS = 16, // number of measurements to perform after event
`endif
parameter BITS_TO_START_XMIT = 6, // wait H2D FIFO to have 1 << BITS_TO_START_XMIT to start FIS transmission (or all FIS fits)
parameter DATA_BYTE_WIDTH = 4,
parameter ELASTIC_DEPTH = 4, //5, With 4/7 got infrequent overflows!
parameter ELASTIC_OFFSET = 7, // 5 //10
parameter FREQ_METER_WIDTH = 12
)(
input exrst, // master reset that resets PLL and GTX
input reliable_clk, // use aclk that runs independently of the GTX
output rst, // PHY-generated reset after PLL lock
output clk, // PHY-generated clock, 75MHz for SATA2
// Data/type FIFO, host -> device
// Data System memory or FIS -> device
input [31:0] h2d_data, // 32-bit data from the system memory to HBA (dma data)
input [ 1:0] h2d_mask, // set to 2'b11
input [ 1:0] h2d_type, // 0 - data, 1 - FIS head, 2 - FIS LAST
input h2d_valid, // output register full
output h2d_ready, // h2d FIFO has room for data (>= 8? dwords)
// Data/type FIFO, device -> host
output [31:0] d2h_data, // FIFO input data
output [ 1:0] d2h_mask, // set to 2'b11
output [ 1:0] d2h_type, // 0 - data, 1 - FIS head, 2 - R_OK, 3 - R_ERR (last two - after data, so ignore data with R_OK/R_ERR)
output d2h_valid, // Data available from the transport layer in FIFO
output d2h_many, // Multiple DWORDs available from the transport layer in FIFO
input d2h_ready, // This module or DMA consumes DWORD
// communication with link/phys layers
output [ 1:0] phy_speed, // 0 - not ready, 1..3 - negotiated speed (Now 0/2)
output gtx_ready, // How to use it?
output xmit_ok, // received R_OK after transmission
output xmit_err, // Error during/after sending of a FIS (got R_ERR)
output x_rdy_collision, // X_RDY/X_RDY collision on interface
output syncesc_recv, // Where to get it?
input pcmd_st_cleared, // PxCMD.ST 1->0 transition by software
input syncesc_send, // Send sync escape
output syncesc_send_done, // "SYNC escape until the interface is quiescent..."
input comreset_send, // Not possible yet?
output cominit_got,
input set_offline, // electrically idle
input send_R_OK, // Should it be originated in this layer SM?
input send_R_ERR,
// additional errors from SATA layers (single-clock pulses):
output serr_DT, // RWC: Transport state transition error
output serr_DS, // RWC: Link sequence error
output serr_DH, // RWC: Handshake Error (i.e. Device got CRC error)
output serr_DC, // RWC: CRC error in Link layer
output serr_DB, // RWC: 10B to 8B decode error
output serr_DW, // RWC: COMMWAKE signal was detected
output serr_DI, // RWC: PHY Internal Error
// sirq_PRC,
output serr_EE, // RWC: Internal error (such as elastic buffer overflow or primitive mis-alignment)
output serr_EP, // RWC: Protocol Error - a violation of SATA protocol detected
output serr_EC, // RWC: Persistent Communication or Data Integrity Error
output serr_ET, // RWC: Transient Data Integrity Error (error not recovered by the interface)
output serr_EM, // RWC: Communication between the device and host was lost but re-established
output serr_EI, // RWC: Recovered Data integrity Error
// additional control signals for SATA layers
input [3:0] sctl_ipm, // Interface power management transitions allowed // @SuppressThisWarning Veditor Unused (yet)
input [3:0] sctl_spd, // Interface maximal speed // @SuppressThisWarning Veditor Unused (yet)
// Device high speed pads and clock inputs
// ref clk from an external source, shall be connected to pads
input wire extclk_p,
input wire extclk_n,
// sata link data pins
output wire txp_out,
output wire txn_out,
input wire rxp_in,
input wire rxn_in,
output debug_is_data, // @clk (sata clk) - last symbol was data output
output debug_dmatp, // @clk (sata clk) - received CODE_DMATP
`ifdef USE_DATASCOPE
// Datascope interface (write to memory that can be software-read)
output datascope_clk,
output [ADDRESS_BITS-1:0] datascope_waddr,
output datascope_we,
output [31:0] datascope_di,
`endif
`ifdef USE_DRP
input drp_rst,
input drp_clk,
input drp_en, // @aclk strobes drp_ad
input drp_we,
input [14:0] drp_addr,
input [15:0] drp_di,
output drp_rdy,
output [15:0] drp_do ,
`endif
output [FREQ_METER_WIDTH - 1:0] xclk_period, // relative (to 2*clk) xclk period
output [31:0] debug_phy,
output [31:0] debug_link,
input hclk // just for testing
);
localparam PHY_SPEED = 2; // SATA2
localparam FIFO_ADDR_WIDTH = 9;
localparam D2H_TYPE_DMA = 0;
localparam D2H_TYPE_FIS_HEAD = 1;
localparam D2H_TYPE_OK = 2;
localparam D2H_TYPE_ERR = 3;
localparam H2D_TYPE_FIS_DATA = 0; // @SuppressThisWarning VEditor unused
localparam H2D_TYPE_FIS_HEAD = 1;
localparam H2D_TYPE_FIS_LAST = 2;
`ifdef SIMULATION
`ifdef CHECK_LOW_H2D_FIFO
localparam H2D_FIFO_THRESHOLD = 4; // to test h2d_ready - will turn off frequently, much earlier than fifo almost full
`endif
`endif
wire phy_ready; // active when GTX gets aligned output
wire link_established; // Received 3 back-to-back non-ALIGNp
wire [31:0] ll_h2d_data_in;
wire [1:0] ll_h2d_mask_in;
wire ll_strobe_out;
wire ll_h2d_last;
wire [1:0] h2d_type_out;
wire [31:0] ll_d2h_data_out;
wire [ 1:0] ll_d2h_mask_out;
wire ll_d2h_valid;
wire ll_d2h_almost_full;
reg [1:0] d2h_type_in;
reg fis_over_r; // push 1 more DWORD (ignore) + type (ERR/OK) when received FIS is done/error
reg ll_frame_req; // -> link // request for a new frame transition
wire ll_frame_ackn; // acknowledge for ll_frame_req
wire ll_incom_start; // link -> // if started an incoming transaction assuming this and next 2 are single-cycle
wire ll_incom_done; // link -> // if incoming transition was completed
wire ll_incom_invalidate; // link -> // if incoming transition had errors
reg ll_incom_invalidate_r; // error delayed by 1 clock - if eof was incorrect (because of earlier data error)
// let last data dword to pass through
wire ll_link_reset = ~phy_ready; // -> link // oob sequence is reinitiated and link now is not established or rxelecidle //TODO Alexey:mb it shall be independent
wire [DATA_BYTE_WIDTH*8 - 1:0] ph2ll_data_out;
wire [DATA_BYTE_WIDTH - 1:0] ph2ll_charisk_out; // charisk
wire [DATA_BYTE_WIDTH - 1:0] ph2ll_err_out; // disperr | notintable
wire [DATA_BYTE_WIDTH*8 - 1:0] ll2ph_data_in;
wire [DATA_BYTE_WIDTH - 1:0] ll2ph_charisk_in; // charisk
wire [FIFO_ADDR_WIDTH-1:0] h2d_raddr;
wire [1:0] h2d_fifo_re_regen;
wire [FIFO_ADDR_WIDTH-1:0] h2d_waddr;
wire [FIFO_ADDR_WIDTH:0] h2d_fill;
wire h2d_nempty;
wire [FIFO_ADDR_WIDTH-1:0] d2h_raddr;
wire [1:0] d2h_fifo_re_regen;
wire [FIFO_ADDR_WIDTH-1:0] d2h_waddr;
wire [FIFO_ADDR_WIDTH:0] d2h_fill;
wire d2h_nempty;
wire h2d_fifo_rd = h2d_nempty && ll_strobe_out; // TODO: check latency in link.v
// wire h2d_fifo_wr = h2d_valid;
//2016.12.10
wire h2d_fifo_wr = h2d_valid && h2d_ready; // or should valid depend on ready in the fis_transmit?
wire d2h_fifo_rd = d2h_valid && d2h_ready;
wire d2h_fifo_wr = ll_d2h_valid || fis_over_r; // fis_over_r will push FIS end to FIFO
reg h2d_pending; // HBA started sending FIS to fifo
wire rxelsfull;
wire rxelsempty;
wire xclk; // output receive clock, just to measure frequency
wire debug_detected_alignp; // oob detects ALIGNp, but not the link layer
wire [31:0] debug_phy0;
`ifdef USE_DATASCOPE
wire [31:0] datascope0_di;
`endif
assign ll_h2d_last = (h2d_type_out == H2D_TYPE_FIS_LAST);
assign d2h_valid = d2h_nempty;
assign d2h_many = |d2h_fill[FIFO_ADDR_WIDTH:3]; //
// assign h2d_ready = !h2d_fill[FIFO_ADDR_WIDTH] && !(&h2d_fill[FIFO_ADDR_WIDTH:3]);
// 2016:12:10 sometimes overflow happened because of a BUG
`ifdef SIMULATION
`ifdef CHECK_LOW_H2D_FIFO
assign h2d_ready = !h2d_fill[FIFO_ADDR_WIDTH] && (h2d_fill < ((1 << BITS_TO_START_XMIT) + H2D_FIFO_THRESHOLD ));
`else
assign h2d_ready = !h2d_fill[FIFO_ADDR_WIDTH] && !(&h2d_fill[FIFO_ADDR_WIDTH-1:3]); // same as with synthesis
`endif
`else
assign h2d_ready = !h2d_fill[FIFO_ADDR_WIDTH] && !(&h2d_fill[FIFO_ADDR_WIDTH-1:3]);
`endif
assign ll_d2h_almost_full = d2h_fill[FIFO_ADDR_WIDTH] || &d2h_fill[FIFO_ADDR_WIDTH-1:6]; // 63 dwords (maybe use :5?) - time to tell device to stop
// assign ll_frame_req_w = !ll_frame_busy && h2d_pending && (((h2d_type == H2D_TYPE_FIS_LAST) && h2d_fifo_wr ) || (|h2d_fill[FIFO_ADDR_WIDTH : BITS_TO_START_XMIT]));
// Separating different types of errors, sync_escape from other problems. TODO: route individual errors to set SERR bits
//assign incom_invalidate = state_rcvr_eof & crc_bad & ~alignes_pair | state_rcvr_data & dword_val & rcvd_dword[CODE_WTRMP];
// assign phy_speed = phy_ready ? PHY_SPEED:0;
// assign serr_DB = phy_ready && (|ph2ll_err_out);
// assign serr_DH = phy_ready && (xmit_err);
assign phy_speed = link_established ? PHY_SPEED:0;
assign serr_DB = link_established && (|ph2ll_err_out);
assign serr_DH = link_established && (xmit_err);
//
// not yet assigned errors
/// assign serr_DT = phy_ready && (comreset_send); // RWC: Transport state transition error
/// assign serr_DS = phy_ready && (cominit_got); // RWC: Link sequence error
/// assign serr_DC = phy_ready && (serr_DW); // RWC: CRC error in Link layer
assign serr_DT = phy_ready && (0); // RWC: Transport state transition error
// assign serr_DS = phy_ready && (0); // RWC: Link sequence error
// assign serr_DC = phy_ready && (0); // RWC: CRC error in Link layer
// assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error
assign serr_EE = phy_ready && (rxelsfull || rxelsempty);
assign serr_DI = phy_ready && (0); // rxelsfull); // RWC: PHY Internal Error // just debugging
assign serr_EP = phy_ready && (0); // rxelsempty); // RWC: Protocol Error - a violation of SATA protocol detected // just debugging
assign serr_EC = phy_ready && (0); // RWC: Persistent Communication or Data Integrity Error
assign serr_ET = phy_ready && (0); // RWC: Transient Data Integrity Error (error not recovered by the interface)
assign serr_EM = phy_ready && (0); // RWC: Communication between the device and host was lost but re-established
assign serr_EI = phy_ready && (0); // RWC: Recovered Data integrity Error
reg [1:0] debug_last_d2h_type_in;
reg [1:0] debug_last_d2h_type;
always @ (posedge clk) begin
if (d2h_fifo_wr) debug_last_d2h_type_in<= d2h_type_in;
if (d2h_fifo_rd) debug_last_d2h_type<= d2h_type;
end
assign debug_phy = debug_phy0;
`ifdef USE_DATASCOPE
`ifdef DATASCOPE_INCOMING_RAW
assign datascope_di = {5'b0,debug_link[5],datascope0_di[25:0]};// aligns_pair tx
`else
// Mix transmitted alignes pair, but only to the closest group of 6 primitives
reg dbg_was_link5; // alignes pair sent
wire dbg_was_link5_xclk; // alignes pair sent
always @ (posedge datascope_clk) begin
if (dbg_was_link5_xclk) dbg_was_link5 <= 1;
else if (datascope_we) dbg_was_link5 <= 0;
end
pulse_cross_clock #(
.EXTRA_DLY(0)
) dbg_was_link5_i (
.rst (rst), // input
.src_clk (clk), // input
.dst_clk (datascope_clk), // input
.in_pulse (debug_link[5]), // input// is actually a two-cycle
.out_pulse (dbg_was_link5_xclk), // output
.busy() // output
);
assign datascope_di = {dbg_was_link5,datascope0_di[30:0]};// aligns_pair tx
`endif
`endif
link #(
.DATA_BYTE_WIDTH(4)
) link (
.rst (rst), // input wire
.clk (clk), // input wire
// data inputs from transport layer
.data_in (ll_h2d_data_in), // input[31:0] wire // input data stream (if any data during OOB setting => ignored)
// TODO, for now not supported, all mask bits are assumed to be set
.data_mask_in (ll_h2d_mask_in), // input[1:0] wire
.data_strobe_out (ll_strobe_out), // output wire // buffer read strobe
.data_last_in (ll_h2d_last), // input wire // transaction's last data budle pulse
.data_val_in (h2d_nempty), // input wire // read data is valid (if 0 while last pulse wasn't received => need to hold the line)
.data_out (ll_d2h_data_out), // output[31:0] wire // read data, same as related inputs
.data_mask_out (ll_d2h_mask_out), // output[1:0] wire // same thing - all 1s for now. TODO
.data_val_out (ll_d2h_valid), // output wire // count every data bundle read by transport layer, even if busy flag is set // let the transport layer handle oveflows by himself
.data_busy_in (ll_d2h_almost_full), // input wire // transport layer tells if its inner buffer is almost full
.data_last_out (), // ll_d2h_last), // output wire not used
.frame_req (ll_frame_req), // input wire // request for a new frame transmission
.frame_busy (), // ll_frame_busy), // output wire // a little bit of overkill with the cound of response signals, think of throwing out 1 of them // LL tells back if it cant handle the request for now
.frame_ack (ll_frame_ackn), // ll_frame_ack), // output wire // LL tells if the request is transmitting
.frame_rej (x_rdy_collision), // output wire // or if it was cancelled because of simultanious incoming transmission
.frame_done_good (xmit_ok), // output wire // TL tell if the outcoming transaction is done and how it was done
.frame_done_bad (xmit_err), // output wire
.incom_start (ll_incom_start), // output wire // if started an incoming transaction
.incom_done (ll_incom_done), // output wire // if incoming transition was completed
.incom_invalidate (ll_incom_invalidate), // output wire // if incoming transition had errors
.incom_sync_escape(syncesc_recv), // output wire - received sync escape
.incom_ack_good (send_R_OK), // input wire // transport layer responds on a completion of a FIS
.incom_ack_bad (send_R_ERR), // input wire // oob sequence is reinitiated and link now is not established or rxelecidle
.link_reset (ll_link_reset), // input wire // oob sequence is reinitiated and link now is not established or rxelecidle
.sync_escape_req (syncesc_send), // input wire // TL demands to brutally cancel current transaction
.sync_escape_ack (syncesc_send_done), // output wire // acknowlegement of a successful reception?
.incom_stop_req (pcmd_st_cleared), // input wire // TL demands to stop current receiving session
.link_established (link_established), // output wire
.link_bad_crc (serr_DC), // output wire // Bad CRC at EOF
// inputs from phy
.phy_ready (phy_ready), // input wire // phy is ready - link is established
// data-primitives stream from phy
.phy_data_in (ph2ll_data_out), // input[31:0] wire // phy_data_in
.phy_isk_in (ph2ll_charisk_out), // input[3:0] wire // charisk
.phy_err_in (ph2ll_err_out), // input[3:0] wire // disperr | notintable
// to phy
.phy_data_out (ll2ph_data_in), // output[31:0] wire
.phy_isk_out (ll2ph_charisk_in), // output[3:0] wire // charisk
.debug_is_data (debug_is_data), // output reg @clk (sata clk) - last symbol was data output
.debug_dmatp (debug_dmatp), // output reg @clk (sata clk) - received CODE_DMATP
.debug_out (debug_link)
);
always @ (posedge clk) begin
ll_incom_invalidate_r <= ll_incom_invalidate;
// FIS receive D2H
// add head if ll_d2h_valid and (d2h_type_in == D2H_TYPE_OK) || (d2h_type_in == D2H_TYPE_ERR)? Or signal some internal error
if (rst || ll_incom_start) d2h_type_in <= D2H_TYPE_FIS_HEAD; // FIS head
else if (ll_d2h_valid) d2h_type_in <= D2H_TYPE_DMA; // FIS BODY
else if (ll_incom_done || ll_incom_invalidate_r) d2h_type_in <= ll_incom_invalidate_r ? D2H_TYPE_ERR: D2H_TYPE_OK;
if (rst) fis_over_r <= 0;
else fis_over_r <= (ll_incom_done || ll_incom_invalidate_r) && (d2h_type_in == D2H_TYPE_DMA); // make sure it is only once
// Second - generate internal error?
// FIS transmit H2D
// Start if all FIS is in FIFO (last word received) or at least that many is in FIFO
if (rst || ll_frame_req) h2d_pending <= 0; // ?
else if ((h2d_type == H2D_TYPE_FIS_HEAD) && h2d_fifo_wr) h2d_pending <= 1;
if (rst) ll_frame_req <= 0;
// else ll_frame_req <= ll_frame_req_w;
else if (h2d_pending &&
(((h2d_type == H2D_TYPE_FIS_LAST) && h2d_fifo_wr ) ||
(|h2d_fill[FIFO_ADDR_WIDTH : BITS_TO_START_XMIT]))) ll_frame_req <= 1;
else if (ll_frame_ackn) ll_frame_req <= 0;
end
sata_phy #(
`ifdef USE_DATASCOPE
.ADDRESS_BITS (ADDRESS_BITS), // for datascope
.DATASCOPE_START_BIT (DATASCOPE_START_BIT),
.DATASCOPE_POST_MEAS (DATASCOPE_POST_MEAS),
`endif
.DATA_BYTE_WIDTH (DATA_BYTE_WIDTH),
.ELASTIC_DEPTH (ELASTIC_DEPTH),
.ELASTIC_OFFSET (ELASTIC_OFFSET)
) phy (
.extrst (exrst), // input wire
.clk (clk), // output wire
.rst (rst), // output wire
.reliable_clk (reliable_clk), // input wire
.phy_ready (phy_ready), // output wire
.gtx_ready (gtx_ready), // output wire
.debug_cnt (), // output[11:0] wire
.extclk_p (extclk_p), // input wire
.extclk_n (extclk_n), // input wire
.txp_out (txp_out), // output wire
.txn_out (txn_out), // output wire
.rxp_in (rxp_in), // input wire
.rxn_in (rxn_in), // input wire
.ll_data_out (ph2ll_data_out), // output[31:0] wire
.ll_charisk_out (ph2ll_charisk_out), // output[3:0] wire
.ll_err_out (ph2ll_err_out), // output[3:0] wire
.ll_data_in (ll2ph_data_in), // input[31:0] wire
.ll_charisk_in (ll2ph_charisk_in), // input[3:0] wire
.set_offline (set_offline), // input
.comreset_send (comreset_send), // input
.cominit_got (cominit_got), // output wire
.comwake_got (serr_DW), // output wire
.rxelsfull (rxelsfull), // output wire
.rxelsempty (rxelsempty), // output wire
.cplllock_debug (),
.usrpll_locked_debug (),
.re_aligned (serr_DS), // output reg
.xclk (xclk), // output receive clock, just to measure frequency
`ifdef USE_DATASCOPE
.datascope_clk (datascope_clk), // output
.datascope_waddr (datascope_waddr), // output[9:0]
.datascope_we (datascope_we), // output
.datascope_di (datascope0_di), // output[31:0]
.datascope_trig (ll_incom_invalidate ), // ll_frame_ackn), // input datascope external trigger
// .datascope_trig (debug_link[4:0] == 'h0a), // state_send_eof // input datascope external trigger
/// .datascope_trig (debug_link[4:0] == 'h02), // state_rcvr_goodcrc // input datascope external trigger
//debug_link
`endif
`ifdef USE_DRP
.drp_rst (drp_rst), // input
.drp_clk (drp_clk), // input
.drp_en (drp_en), // input
.drp_we (drp_we), // input
.drp_addr (drp_addr), // input[14:0]
.drp_di (drp_di), // input[15:0]
.drp_rdy (drp_rdy), // output
.drp_do (drp_do), // output[15:0]
`endif
.debug_sata (debug_phy0)
,.debug_detected_alignp(debug_detected_alignp)
);
fifo_sameclock_control #(
.WIDTH(9)
) fifo_h2d_control_i (
.clk (clk), // input
.rst (rst || pcmd_st_cleared), // input
.wr (h2d_fifo_wr), // input
.rd (h2d_fifo_rd), // input
.nempty (h2d_nempty), // output
.fill_in (h2d_fill), // output[9:0]
.mem_wa (h2d_waddr), // output[8:0] reg
.mem_ra (h2d_raddr), // output[8:0] reg
.mem_re (h2d_fifo_re_regen[0]), // output
.mem_regen(h2d_fifo_re_regen[1]), // output
.over (), // output reg
.under () //h2d_under) // output reg
);
ram18p_var_w_var_r #(
.REGISTERS (1),
.LOG2WIDTH_WR (5),
.LOG2WIDTH_RD (5)
) fifo_h2d_i (
.rclk (clk), // input
.raddr (h2d_raddr), // input[8:0]
.ren (h2d_fifo_re_regen[0]), // input
.regen (h2d_fifo_re_regen[1]), // input
.data_out ({h2d_type_out, ll_h2d_mask_in, ll_h2d_data_in}), // output[35:0]
.wclk (clk), // input
.waddr (h2d_waddr), // input[8:0]
.we (h2d_fifo_wr), // input
.web (4'hf), // input[3:0]
.data_in ({h2d_type,h2d_mask,h2d_data}) // input[35:0]
);
fifo_sameclock_control #(
.WIDTH(9)
) fifo_d2h_control_i (
.clk (clk), // input
.rst (rst || pcmd_st_cleared), // input
.wr (d2h_fifo_wr), // input
.rd (d2h_fifo_rd), // input
.nempty (d2h_nempty), // output
.fill_in (d2h_fill), // output[9:0]
.mem_wa (d2h_waddr), // output[8:0] reg
.mem_ra (d2h_raddr), // output[8:0] reg
.mem_re (d2h_fifo_re_regen[0]), // output
.mem_regen(d2h_fifo_re_regen[1]), // output
.over (), //d2h_over), // output reg
.under () // output reg
);
ram18p_var_w_var_r #(
.REGISTERS (1),
.LOG2WIDTH_WR (5),
.LOG2WIDTH_RD (5)
) fifo_d2h_i (
.rclk (clk), // input
.raddr (d2h_raddr), // input[8:0]
.ren (d2h_fifo_re_regen[0]), // input
.regen (d2h_fifo_re_regen[1]), // input
.data_out ({d2h_type, d2h_mask, d2h_data}), // output[35:0]
.wclk (clk), // input
.waddr (d2h_waddr), // input[8:0]
.we (d2h_fifo_wr), // input
.web (4'hf), // input[3:0]
.data_in ({d2h_type_in, ll_d2h_mask_out, ll_d2h_data_out}) // input[35:0]
);
freq_meter #(
.WIDTH (FREQ_METER_WIDTH),
.PRESCALE (1)
) freq_meter_i (
.rst (rst), // input
.clk (clk), // input
.xclk (xclk), // hclk), //xclk), // input
.dout (xclk_period) // output[11:0] reg
);
endmodule
|
(** * MoreInd: More on Induction *)
Require Export "ProofObjects".
(* ##################################################### *)
(** * Induction Principles *)
(** This is a good point to pause and take a deeper look at induction
principles.
Every time we declare a new [Inductive] datatype, Coq
automatically generates and proves an _induction principle_
for this type.
The induction principle for a type [t] is called [t_ind]. Here is
the one for natural numbers: *)
Check nat_ind.
(* ===> nat_ind :
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n *)
(** *** *)
(** The [induction] tactic is a straightforward wrapper that, at
its core, simply performs [apply t_ind]. To see this more
clearly, let's experiment a little with using [apply nat_ind]
directly, instead of the [induction] tactic, to carry out some
proofs. Here, for example, is an alternate proof of a theorem
that we saw in the [Basics] chapter. *)
Theorem mult_0_r' : forall n:nat,
n * 0 = 0.
Proof.
apply nat_ind.
- (* O *) reflexivity.
- (* S *) simpl. intros n IHn. rewrite -> IHn.
reflexivity. Qed.
(** This proof is basically the same as the earlier one, but a
few minor differences are worth noting. First, in the induction
step of the proof (the ["S"] case), we have to do a little
bookkeeping manually (the [intros]) that [induction] does
automatically.
Second, we do not introduce [n] into the context before applying
[nat_ind] -- the conclusion of [nat_ind] is a quantified formula,
and [apply] needs this conclusion to exactly match the shape of
the goal state, including the quantifier. The [induction] tactic
works either with a variable in the context or a quantified
variable in the goal.
Third, the [apply] tactic automatically chooses variable names for
us (in the second subgoal, here), whereas [induction] lets us
specify (with the [as...] clause) what names should be used. The
automatic choice is actually a little unfortunate, since it
re-uses the name [n] for a variable that is different from the [n]
in the original theorem. This is we have labeled the second
subgoal just [S] -- if we tried to write it out in the more
explicit form that we've been using for most proofs, we'd have to
write [n = S n], which doesn't make a lot of sense! All of these
conveniences make [induction] nicer to use in practice than
applying induction principles like [nat_ind] directly. But it is
important to realize that, modulo this little bit of bookkeeping,
applying [nat_ind] is what we are really doing. *)
(** **** Exercise: 2 stars, optional (plus_one_r') *)
(** Complete this proof as we did [mult_0_r'] above, without using
the [induction] tactic. *)
Theorem plus_one_r' : forall n:nat,
n + 1 = S n.
Proof.
apply nat_ind.
- simpl. reflexivity.
- intros. simpl. rewrite H. reflexivity.
Qed.
(** [] *)
(** Coq generates induction principles for every datatype defined with
[Inductive], including those that aren't recursive. (Although
we don't need induction to prove properties of non-recursive
datatypes, the idea of an induction principle still makes sense
for them: it gives a way to prove that a property holds for all
values of the type.)
These generated principles follow a similar pattern. If we define a
type [t] with constructors [c1] ... [cn], Coq generates a theorem
with this shape:
t_ind :
forall P : t -> Prop,
... case for c1 ... ->
... case for c2 ... ->
...
... case for cn ... ->
forall n : t, P n
The specific shape of each case depends on the arguments to the
corresponding constructor. Before trying to write down a general
rule, let's look at some more examples. First, an example where
the constructors take no arguments: *)
Inductive yesno : Type :=
| yes : yesno
| no : yesno.
Check yesno_ind.
(* ===> yesno_ind : forall P : yesno -> Prop,
P yes ->
P no ->
forall y : yesno, P y *)
(** **** Exercise: 1 star, optional (rgb) *)
(** Write out the induction principle that Coq will generate for the
following datatype. Write down your answer on paper or type it
into a comment, and then compare it with what Coq prints. *)
Inductive rgb : Type :=
| red : rgb
| green : rgb
| blue : rgb.
Check rgb_ind.
(** [] *)
(** Here's another example, this time with one of the constructors
taking some arguments. *)
Inductive natlist : Type :=
| nnil : natlist
| ncons : nat -> natlist -> natlist.
Check natlist_ind.
(* ===> (modulo a little variable renaming for clarity)
natlist_ind :
forall P : natlist -> Prop,
P nnil ->
(forall (n : nat) (l : natlist), P l -> P (ncons n l)) ->
forall n : natlist, P n *)
(** **** Exercise: 1 star, optional (natlist1) *)
(** Suppose we had written the above definition a little
differently: *)
Inductive natlist1 : Type :=
| nnil1 : natlist1
| nsnoc1 : natlist1 -> nat -> natlist1.
(** Now what will the induction principle look like? *)
(** [] *)
(** From these examples, we can extract this general rule:
- The type declaration gives several constructors; each
corresponds to one clause of the induction principle.
- Each constructor [c] takes argument types [a1]...[an].
- Each [ai] can be either [t] (the datatype we are defining) or
some other type [s].
- The corresponding case of the induction principle
says (in English):
- "for all values [x1]...[xn] of types [a1]...[an], if [P]
holds for each of the inductive arguments (each [xi] of
type [t]), then [P] holds for [c x1 ... xn]".
*)
(** **** Exercise: 1 star, optional (byntree_ind) *)
(** Write out the induction principle that Coq will generate for the
following datatype. Write down your answer on paper or type it
into a comment, and then compare it with what Coq prints. *)
Inductive byntree : Type :=
| bempty : byntree
| bleaf : yesno -> byntree
| nbranch : yesno -> byntree -> byntree -> byntree.
(** [] *)
(** **** Exercise: 1 star, optional (ex_set) *)
(** Here is an induction principle for an inductively defined
set.
ExSet_ind :
forall P : ExSet -> Prop,
(forall b : bool, P (con1 b)) ->
(forall (n : nat) (e : ExSet), P e -> P (con2 n e)) ->
forall e : ExSet, P e
Give an [Inductive] definition of [ExSet]: *)
Inductive ExSet : Type :=
| con1 : bool -> ExSet
| con2 : nat -> ExSet -> ExSet
.
(** [] *)
(** What about polymorphic datatypes?
The inductive definition of polymorphic lists
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
is very similar to that of [natlist]. The main difference is
that, here, the whole definition is _parameterized_ on a set [X]:
that is, we are defining a _family_ of inductive types [list X],
one for each [X]. (Note that, wherever [list] appears in the body
of the declaration, it is always applied to the parameter [X].)
The induction principle is likewise parameterized on [X]:
list_ind :
forall (X : Type) (P : list X -> Prop),
P [] ->
(forall (x : X) (l : list X), P l -> P (x :: l)) ->
forall l : list X, P l
Note the wording here (and, accordingly, the form of [list_ind]):
The _whole_ induction principle is parameterized on [X]. That is,
[list_ind] can be thought of as a polymorphic function that, when
applied to a type [X], gives us back an induction principle
specialized to the type [list X]. *)
(** **** Exercise: 1 star, optional (tree) *)
(** Write out the induction principle that Coq will generate for
the following datatype. Compare your answer with what Coq
prints. *)
Inductive tree (X:Type) : Type :=
| leaf : X -> tree X
| node : tree X -> tree X -> tree X.
Check tree_ind.
(** [] *)
(** **** Exercise: 1 star, optional (mytype) *)
(** Find an inductive definition that gives rise to the
following induction principle:
mytype_ind :
forall (X : Type) (P : mytype X -> Prop),
(forall x : X, P (constr1 X x)) ->
(forall n : nat, P (constr2 X n)) ->
(forall m : mytype X, P m ->
forall n : nat, P (constr3 X m n)) ->
forall m : mytype X, P m
*)
Inductive mytype (X:Type) : Type :=
| constr1 : X -> mytype X
| constr2 : nat -> mytype X
| constr3 : mytype X -> nat -> mytype X
.
Check mytype_ind.
(** **** Exercise: 1 star, optional (foo) *)
(** Find an inductive definition that gives rise to the
following induction principle:
foo_ind :
forall (X Y : Type) (P : foo X Y -> Prop),
(forall x : X, P (bar X Y x)) ->
(forall y : Y, P (baz X Y y)) ->
(forall f1 : nat -> foo X Y,
(forall n : nat, P (f1 n)) -> P (quux X Y f1)) ->
forall f2 : foo X Y, P f2
*)
Inductive foo (X Y :Type) : Type :=
| bar : X -> foo X Y
| baz : Y -> foo X Y
| quux : (nat -> foo X Y) -> foo X Y
.
Check foo_ind.
(** Exercise: 1 star, optional (foo') *)
(** Consider the following inductive definition: *)
Inductive foo' (X:Type) : Type :=
| C1 : list X -> foo' X -> foo' X
| C2 : foo' X.
(** What induction principle will Coq generate for [foo']? Fill
in the blanks, then check your answer with Coq.)
foo'_ind :
forall (X : Type) (P : foo' X -> Prop),
(forall (l : list X) (f : foo' X),
_______________________ ->
_______________________ ) ->
___________________________________________ ->
forall f : foo' X, ________________________
*)
(** [] *)
(* ##################################################### *)
(** ** Induction Hypotheses *)
(** Where does the phrase "induction hypothesis" fit into this story?
The induction principle for numbers
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n
is a generic statement that holds for all propositions
[P] (strictly speaking, for all families of propositions [P]
indexed by a number [n]). Each time we use this principle, we
are choosing [P] to be a particular expression of type
[nat->Prop].
We can make the proof more explicit by giving this expression a
name. For example, instead of stating the theorem [mult_0_r] as
"[forall n, n * 0 = 0]," we can write it as "[forall n, P_m0r
n]", where [P_m0r] is defined as... *)
Definition P_m0r (n:nat) : Prop :=
n * 0 = 0.
(** ... or equivalently... *)
Definition P_m0r' : nat->Prop :=
fun n => n * 0 = 0.
(** Now when we do the proof it is easier to see where [P_m0r]
appears. *)
Theorem mult_0_r'' : forall n:nat,
P_m0r n.
Proof.
apply nat_ind.
- (* n = O *) reflexivity.
- (* n = S n' *)
(* Note the proof state at this point! *)
intros n IHn.
unfold P_m0r in IHn. unfold P_m0r. simpl. apply IHn. Qed.
(** This extra naming step isn't something that we'll do in
normal proofs, but it is useful to do it explicitly for an example
or two, because it allows us to see exactly what the induction
hypothesis is. If we prove [forall n, P_m0r n] by induction on
[n] (using either [induction] or [apply nat_ind]), we see that the
first subgoal requires us to prove [P_m0r 0] ("[P] holds for
zero"), while the second subgoal requires us to prove [forall n',
P_m0r n' -> P_m0r n' (S n')] (that is "[P] holds of [S n'] if it
holds of [n']" or, more elegantly, "[P] is preserved by [S]").
The _induction hypothesis_ is the premise of this latter
implication -- the assumption that [P] holds of [n'], which we are
allowed to use in proving that [P] holds for [S n']. *)
(* ##################################################### *)
(** ** More on the [induction] Tactic *)
(** The [induction] tactic actually does even more low-level
bookkeeping for us than we discussed above.
Recall the informal statement of the induction principle for
natural numbers:
- If [P n] is some proposition involving a natural number n, and
we want to show that P holds for _all_ numbers n, we can
reason like this:
- show that [P O] holds
- show that, if [P n'] holds, then so does [P (S n')]
- conclude that [P n] holds for all n.
So, when we begin a proof with [intros n] and then [induction n],
we are first telling Coq to consider a _particular_ [n] (by
introducing it into the context) and then telling it to prove
something about _all_ numbers (by using induction).
What Coq actually does in this situation, internally, is to
"re-generalize" the variable we perform induction on. For
example, in our original proof that [plus] is associative...
*)
Theorem plus_assoc' : forall n m p : nat,
n + (m + p) = (n + m) + p.
Proof.
(* ...we first introduce all 3 variables into the context,
which amounts to saying "Consider an arbitrary [n], [m], and
[p]..." *)
intros n m p.
(* ...We now use the [induction] tactic to prove [P n] (that
is, [n + (m + p) = (n + m) + p]) for _all_ [n],
and hence also for the particular [n] that is in the context
at the moment. *)
induction n as [| n'].
- (* n = O *) reflexivity.
- (* n = S n' *)
(* In the second subgoal generated by [induction] -- the
"inductive step" -- we must prove that [P n'] implies
[P (S n')] for all [n']. The [induction] tactic
automatically introduces [n'] and [P n'] into the context
for us, leaving just [P (S n')] as the goal. *)
simpl. rewrite -> IHn'. reflexivity. Qed.
(** It also works to apply [induction] to a variable that is
quantified in the goal. *)
Theorem plus_comm' : forall n m : nat,
n + m = m + n.
Proof.
induction n as [| n'].
- (* n = O *) intros m. rewrite -> plus_0_r. reflexivity.
- (* n = S n' *) intros m. simpl. rewrite -> IHn'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** Note that [induction n] leaves [m] still bound in the goal --
i.e., what we are proving inductively is a statement beginning
with [forall m].
If we do [induction] on a variable that is quantified in the goal
_after_ some other quantifiers, the [induction] tactic will
automatically introduce the variables bound by these quantifiers
into the context. *)
Theorem plus_comm'' : forall n m : nat,
n + m = m + n.
Proof.
(* Let's do induction on [m] this time, instead of [n]... *)
induction m as [| m'].
- (* m = O *) simpl. rewrite -> plus_0_r. reflexivity.
- (* m = S m' *) simpl. rewrite <- IHm'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** **** Exercise: 1 star, optional (plus_explicit_prop) *)
(** Rewrite both [plus_assoc'] and [plus_comm'] and their proofs in
the same style as [mult_0_r''] above -- that is, for each theorem,
give an explicit [Definition] of the proposition being proved by
induction, and state the theorem and proof in terms of this
defined proposition. *)
(* FILL IN HERE *)
(** [] *)
(** ** Generalizing Inductions. *)
(** One potentially confusing feature of the [induction] tactic is
that it happily lets you try to set up an induction over a term
that isn't sufficiently general. The net effect of this will be
to lose information (much as [destruct] can do), and leave
you unable to complete the proof. Here's an example: *)
Lemma one_not_beautiful_FAILED: ~ beautiful 1.
Proof.
intro H.
(* Just doing an [inversion] on [H] won't get us very far in the [b_sum]
case. (Try it!). So we'll need induction. A naive first attempt: *)
induction H.
(* But now, although we get four cases, as we would expect from
the definition of [beautiful], we lose all information about [H] ! *)
Abort.
(** The problem is that [induction] over a Prop only works properly over
completely general instances of the Prop, i.e. one in which all
the arguments are free (unconstrained) variables.
In this respect it behaves more
like [destruct] than like [inversion].
When you're tempted to do use [induction] like this, it is generally
an indication that you need to be proving something more general.
But in some cases, it suffices to pull out any concrete arguments
into separate equations, like this: *)
Lemma one_not_beautiful: forall n, n = 1 -> ~ beautiful n.
Proof.
intros n E H.
induction H as [| | | p q Hp IHp Hq IHq].
- (* b_0 *)
inversion E.
- (* b_3 *)
inversion E.
- (* b_5 *)
inversion E.
- (* b_sum *)
(* the rest is a tedious case analysis *)
destruct p as [|p'].
+ (* p = 0 *)
destruct q as [|q'].
* (* q = 0 *)
inversion E.
* (* q = S q' *)
apply IHq. apply E.
+ (* p = S p' *)
destruct q as [|q'].
* (* q = 0 *)
apply IHp. rewrite plus_0_r in E. apply E.
* (* q = S q' *)
simpl in E. inversion E. destruct p'. inversion H0. inversion H0.
Qed.
(** There's a handy [remember] tactic that can generate the second
proof state out of the original one. *)
Lemma one_not_beautiful': ~ beautiful 1.
Proof.
intros H.
remember 1 as n eqn:E.
(* now carry on as above *)
induction H.
Admitted.
(* ####################################################### *)
(** * Informal Proofs (Advanced) *)
(** Q: What is the relation between a formal proof of a proposition
[P] and an informal proof of the same proposition [P]?
A: The latter should _teach_ the reader how to produce the
former.
Q: How much detail is needed??
Unfortunately, There is no single right answer; rather, there is a
range of choices.
At one end of the spectrum, we can essentially give the reader the
whole formal proof (i.e., the informal proof amounts to just
transcribing the formal one into words). This gives the reader
the _ability_ to reproduce the formal one for themselves, but it
doesn't _teach_ them anything.
At the other end of the spectrum, we can say "The theorem is true
and you can figure out why for yourself if you think about it hard
enough." This is also not a good teaching strategy, because
usually writing the proof requires some deep insights into the
thing we're proving, and most readers will give up before they
rediscover all the same insights as we did.
In the middle is the golden mean -- a proof that includes all of
the essential insights (saving the reader the hard part of work
that we went through to find the proof in the first place) and
clear high-level suggestions for the more routine parts to save the
reader from spending too much time reconstructing these
parts (e.g., what the IH says and what must be shown in each case
of an inductive proof), but not so much detail that the main ideas
are obscured.
Another key point: if we're comparing a formal proof of a
proposition [P] and an informal proof of [P], the proposition [P]
doesn't change. That is, formal and informal proofs are _talking
about the same world_ and they _must play by the same rules_. *)
(** ** Informal Proofs by Induction *)
(** Since we've spent much of this chapter looking "under the hood" at
formal proofs by induction, now is a good moment to talk a little
about _informal_ proofs by induction.
In the real world of mathematical communication, written proofs
range from extremely longwinded and pedantic to extremely brief
and telegraphic. The ideal is somewhere in between, of course,
but while you are getting used to the style it is better to start
out at the pedantic end. Also, during the learning phase, it is
probably helpful to have a clear standard to compare against.
With this in mind, we offer two templates below -- one for proofs
by induction over _data_ (i.e., where the thing we're doing
induction on lives in [Type]) and one for proofs by induction over
_evidence_ (i.e., where the inductively defined thing lives in
[Prop]). In the rest of this course, please follow one of the two
for _all_ of your inductive proofs. *)
(** *** Induction Over an Inductively Defined Set *)
(** _Template_:
- _Theorem_: <Universally quantified proposition of the form
"For all [n:S], [P(n)]," where [S] is some inductively defined
set.>
_Proof_: By induction on [n].
<one case for each constructor [c] of [S]...>
- Suppose [n = c a1 ... ak], where <...and here we state
the IH for each of the [a]'s that has type [S], if any>.
We must show <...and here we restate [P(c a1 ... ak)]>.
<go on and prove [P(n)] to finish the case...>
- <other cases similarly...> []
_Example_:
- _Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index (S n) l = None].
_Proof_: By induction on [l].
- Suppose [l = []]. We must show, for all numbers [n],
that, if [length [] = n], then [index (S n) [] =
None].
This follows immediately from the definition of index.
- Suppose [l = x :: l'] for some [x] and [l'], where
[length l' = n'] implies [index (S n') l' = None], for
any number [n']. We must show, for all [n], that, if
[length (x::l') = n] then [index (S n) (x::l') =
None].
Let [n] be a number with [length l = n]. Since
length l = length (x::l') = S (length l'),
it suffices to show that
index (S (length l')) l' = None.
]]
But this follows directly from the induction hypothesis,
picking [n'] to be [length l']. [] *)
(** *** Induction Over an Inductively Defined Proposition *)
(** Since inductively defined proof objects are often called
"derivation trees," this form of proof is also known as _induction
on derivations_.
_Template_:
- _Theorem_: <Proposition of the form "[Q -> P]," where [Q] is
some inductively defined proposition (more generally,
"For all [x] [y] [z], [Q x y z -> P x y z]")>
_Proof_: By induction on a derivation of [Q]. <Or, more
generally, "Suppose we are given [x], [y], and [z]. We
show that [Q x y z] implies [P x y z], by induction on a
derivation of [Q x y z]"...>
<one case for each constructor [c] of [Q]...>
- Suppose the final rule used to show [Q] is [c]. Then
<...and here we state the types of all of the [a]'s
together with any equalities that follow from the
definition of the constructor and the IH for each of
the [a]'s that has type [Q], if there are any>. We must
show <...and here we restate [P]>.
<go on and prove [P] to finish the case...>
- <other cases similarly...> []
_Example_
- _Theorem_: The [<=] relation is transitive -- i.e., for all
numbers [n], [m], and [o], if [n <= m] and [m <= o], then
[n <= o].
_Proof_: By induction on a derivation of [m <= o].
- Suppose the final rule used to show [m <= o] is
[le_n]. Then [m = o] and we must show that [n <= m],
which is immediate by hypothesis.
- Suppose the final rule used to show [m <= o] is
[le_S]. Then [o = S o'] for some [o'] with [m <= o'].
We must show that [n <= S o'].
By induction hypothesis, [n <= o'].
But then, by [le_S], [n <= S o']. [] *)
(* ##################################################### *)
(** * Induction Principles in [Prop] (Advanced) *)
(** The remainder of this chapter offers some additional details on
how induction works in Coq, the process of building proof trees,
and the "trusted computing base" that underlies Coq proofs. It
can safely be skimmed on a first reading. (As with the other
advanced sections, we recommend skimming rather than skipping over
it outright: it answers some questions that occur to many Coq
users at some point, so it is useful to have a rough idea of
what's here.) *)
(** Earlier, we looked in detail at the induction principles that Coq
generates for inductively defined _sets_. The induction
principles for inductively defined _propositions_ like [gorgeous]
are a tiny bit more complicated. As with all induction
principles, we want to use the induction principle on [gorgeous]
to prove things by inductively considering the possible shapes
that something in [gorgeous] can have -- either it is evidence
that [0] is gorgeous, or it is evidence that, for some [n], [3+n]
is gorgeous, or it is evidence that, for some [n], [5+n] is
gorgeous and it includes evidence that [n] itself is. Intuitively
speaking, however, what we want to prove are not statements about
_evidence_ but statements about _numbers_. So we want an
induction principle that lets us prove properties of numbers by
induction on evidence.
For example, from what we've said so far, you might expect the
inductive definition of [gorgeous]...
Inductive gorgeous : nat -> Prop :=
g_0 : gorgeous 0
| g_plus3 : forall n, gorgeous n -> gorgeous (3+m)
| g_plus5 : forall n, gorgeous n -> gorgeous (5+m).
...to give rise to an induction principle that looks like this...
gorgeous_ind_max :
forall P : (forall n : nat, gorgeous n -> Prop),
P O g_0 ->
(forall (m : nat) (e : gorgeous m),
P m e -> P (3+m) (g_plus3 m e)) ->
(forall (m : nat) (e : gorgeous m),
P m e -> P (5+m) (g_plus5 m e)) ->
forall (n : nat) (e : gorgeous n), P n e
... because:
- Since [gorgeous] is indexed by a number [n] (every [gorgeous]
object [e] is a piece of evidence that some particular number
[n] is gorgeous), the proposition [P] is parameterized by both
[n] and [e] -- that is, the induction principle can be used to
prove assertions involving both a gorgeous number and the
evidence that it is gorgeous.
- Since there are three ways of giving evidence of gorgeousness
([gorgeous] has three constructors), applying the induction
principle generates three subgoals:
- We must prove that [P] holds for [O] and [b_0].
- We must prove that, whenever [n] is a gorgeous
number and [e] is an evidence of its gorgeousness,
if [P] holds of [n] and [e],
then it also holds of [3+n] and [g_plus3 n e].
- We must prove that, whenever [n] is a gorgeous
number and [e] is an evidence of its gorgeousness,
if [P] holds of [n] and [e],
then it also holds of [5+n] and [g_plus5 n e].
- If these subgoals can be proved, then the induction principle
tells us that [P] is true for _all_ gorgeous numbers [n] and
evidence [e] of their gorgeousness.
But this is a little more flexibility than we actually need or
want: it is giving us a way to prove logical assertions where the
assertion involves properties of some piece of _evidence_ of
gorgeousness, while all we really care about is proving
properties of _numbers_ that are gorgeous -- we are interested in
assertions about numbers, not about evidence. It would therefore
be more convenient to have an induction principle for proving
propositions [P] that are parameterized just by [n] and whose
conclusion establishes [P] for all gorgeous numbers [n]:
forall P : nat -> Prop,
... ->
forall n : nat, gorgeous n -> P n
For this reason, Coq actually generates the following simplified
induction principle for [gorgeous]: *)
Check gorgeous_ind.
(* ===> gorgeous_ind
: forall P : nat -> Prop,
P 0 ->
(forall n : nat, gorgeous n -> P n -> P (3 + n)) ->
(forall n : nat, gorgeous n -> P n -> P (5 + n)) ->
forall n : nat, gorgeous n -> P n *)
(** In particular, Coq has dropped the evidence term [e] as a
parameter of the the proposition [P], and consequently has
rewritten the assumption [forall (n : nat) (e: gorgeous n), ...]
to be [forall (n : nat), gorgeous n -> ...]; i.e., we no longer
require explicit evidence of the provability of [gorgeous n]. *)
(** In English, [gorgeous_ind] says:
- Suppose, [P] is a property of natural numbers (that is, [P n] is
a [Prop] for every [n]). To show that [P n] holds whenever [n]
is gorgeous, it suffices to show:
- [P] holds for [0],
- for any [n], if [n] is gorgeous and [P] holds for
[n], then [P] holds for [3+n],
- for any [n], if [n] is gorgeous and [P] holds for
[n], then [P] holds for [5+n]. *)
(** As expected, we can apply [gorgeous_ind] directly instead of using [induction]. *)
Theorem gorgeous__beautiful' : forall n, gorgeous n -> beautiful n.
Proof.
intros.
apply gorgeous_ind.
- (* g_0 *)
apply b_0.
- (* g_plus3 *)
intros.
apply b_sum. apply b_3.
apply H1.
- (* g_plus5 *)
intros.
apply b_sum. apply b_5.
apply H1.
- apply H.
Qed.
(** The precise form of an Inductive definition can affect the
induction principle Coq generates.
For example, in [Logic], we have defined [<=] as: *)
(* Inductive le : nat -> nat -> Prop :=
| le_n : forall n, le n n
| le_S : forall n m, (le n m) -> (le n (S m)). *)
(** This definition can be streamlined a little by observing that the
left-hand argument [n] is the same everywhere in the definition,
so we can actually make it a "general parameter" to the whole
definition, rather than an argument to each constructor. *)
Inductive le (n:nat) : nat -> Prop :=
| le_n : le n n
| le_S : forall m, (le n m) -> (le n (S m)).
Notation "m <= n" := (le m n).
(** The second one is better, even though it looks less symmetric.
Why? Because it gives us a simpler induction principle. *)
Check le_ind.
(* ===> forall (n : nat) (P : nat -> Prop),
P n ->
(forall m : nat, n <= m -> P m -> P (S m)) ->
forall n0 : nat, n <= n0 -> P n0 *)
(** By contrast, the induction principle that Coq calculates for the
first definition has a lot of extra quantifiers, which makes it
messier to work with when proving things by induction. Here is
the induction principle for the first [le]: *)
(* le_ind :
forall P : nat -> nat -> Prop,
(forall n : nat, P n n) ->
(forall n m : nat, le n m -> P n m -> P n (S m)) ->
forall n n0 : nat, le n n0 -> P n n0 *)
(* ##################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 2 stars, optional (foo_ind_principle) *)
(** Suppose we make the following inductive definition:
Inductive foo (X : Set) (Y : Set) : Set :=
| foo1 : X -> foo X Y
| foo2 : Y -> foo X Y
| foo3 : foo X Y -> foo X Y.
Fill in the blanks to complete the induction principle that will be
generated by Coq.
foo_ind
: forall (X Y : Set) (P : foo X Y -> Prop),
(forall x : X, __________________________________) ->
(forall y : Y, __________________________________) ->
(________________________________________________) ->
________________________________________________
*)
(** [] *)
(** **** Exercise: 2 stars, optional (bar_ind_principle) *)
(** Consider the following induction principle:
bar_ind
: forall P : bar -> Prop,
(forall n : nat, P (bar1 n)) ->
(forall b : bar, P b -> P (bar2 b)) ->
(forall (b : bool) (b0 : bar), P b0 -> P (bar3 b b0)) ->
forall b : bar, P b
Write out the corresponding inductive set definition.
Inductive bar : Set :=
| bar1 : ________________________________________
| bar2 : ________________________________________
| bar3 : ________________________________________.
*)
(** [] *)
(** **** Exercise: 2 stars, optional (no_longer_than_ind) *)
(** Given the following inductively defined proposition:
Inductive no_longer_than (X : Set) : (list X) -> nat -> Prop :=
| nlt_nil : forall n, no_longer_than X [] n
| nlt_cons : forall x l n, no_longer_than X l n ->
no_longer_than X (x::l) (S n)
| nlt_succ : forall l n, no_longer_than X l n ->
no_longer_than X l (S n).
write the induction principle generated by Coq.
no_longer_than_ind
: forall (X : Set) (P : list X -> nat -> Prop),
(forall n : nat, ____________________) ->
(forall (x : X) (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
(forall (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
forall (l : list X) (n : nat), no_longer_than X l n ->
____________________
*)
(** [] *)
(* ##################################################### *)
(** ** Induction Principles for other Logical Propositions *)
(** Similarly, in [Logic] we have defined [eq] as: *)
(* Inductive eq (X:Type) : X -> X -> Prop :=
refl_equal : forall x, eq X x x. *)
(** In the Coq standard library, the definition of equality is
slightly different: *)
Inductive eq' (X:Type) (x:X) : X -> Prop :=
refl_equal' : eq' X x x.
(** The induction principle that Coq derives from this definition
is the following: *)
Check eq'_ind.
(* ===>
forall (X : Type) (x : X) (P : X -> Prop),
P x -> forall y : X, x =' y -> P y *)
(* ===> (i.e., after a little reorganization)
forall (X : Type) (x : X) forall y : X,
x =' y ->
forall P : X -> Prop, P x -> P y *)
(** This principle says that if [x] and [y] are equal then every
property that is true of [x] is also true of [y], i.e. there is no
context that distinguishes [x] and [y]. (Formally, this is the
dual of a principle enunciated by Leibniz, which says that [x] and
[y] are equal if they cannot be distinguished by any context. Note
that the implication in this converse direction is trivially true
in Coq: we simply instantiate [P] with the property of being equal
to [x]. Leibniz took this principle itself as the _definition_ of
equality, whereas in Coq it is a _consequence_ of defining
equality as an inductive type.) *)
(** The induction principles for conjunction and disjunction are a
good illustration of Coq's way of generating simplified induction
principles for [Inductive]ly defined propositions, which we
discussed above. You try first: *)
(** **** Exercise: 1 star, optional (and_ind_principle) *)
(** See if you can predict the induction principle for conjunction. *)
(* Check and_ind. *)
(** [] *)
(** **** Exercise: 1 star, optional (or_ind_principle) *)
(** See if you can predict the induction principle for disjunction. *)
(* Check or_ind. *)
(** [] *)
Check and_ind.
(** From the inductive definition of the proposition [and P Q]
Inductive and (P Q : Prop) : Prop :=
conj : P -> Q -> (and P Q).
we might expect Coq to generate this induction principle
and_ind_max :
forall (P Q : Prop) (P0 : P /\ Q -> Prop),
(forall (a : P) (b : Q), P0 (conj P Q a b)) ->
forall a : P /\ Q, P0 a
but actually it generates this simpler and more useful one:
and_ind :
forall P Q P0 : Prop,
(P -> Q -> P0) ->
P /\ Q -> P0
In the same way, when given the inductive definition of [or P Q]
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
instead of the "maximal induction principle"
or_ind_max :
forall (P Q : Prop) (P0 : P \/ Q -> Prop),
(forall a : P, P0 (or_introl P Q a)) ->
(forall b : Q, P0 (or_intror P Q b)) ->
forall o : P \/ Q, P0 o
what Coq actually generates is this:
or_ind :
forall P Q P0 : Prop,
(P -> P0) ->
(Q -> P0) ->
P \/ Q -> P0
]]
*)
(** **** Exercise: 1 star, optional (False_ind_principle) *)
(** Can you predict the induction principle for falsehood? *)
(* Check False_ind. *)
(** [] *)
(** Here's the induction principle that Coq generates for existentials: *)
Check ex_ind.
(* ===> forall (X:Type) (P: X->Prop) (Q: Prop),
(forall witness:X, P witness -> Q) ->
ex X P ->
Q *)
(** This induction principle can be understood as follows: If we have
a function [f] that can construct evidence for [Q] given _any_
witness of type [X] together with evidence that this witness has
property [P], then from a proof of [ex X P] we can extract the
witness and evidence that must have been supplied to the
constructor, give these to [f], and thus obtain a proof of [Q]. *)
(* ######################################################### *)
(** ** Explicit Proof Objects for Induction *)
(** Although tactic-based proofs are normally much easier to
work with, the ability to write a proof term directly is sometimes
very handy, particularly when we want Coq to do something slightly
non-standard. *)
(** Recall the induction principle on naturals that Coq generates for
us automatically from the Inductive declation for [nat]. *)
Check nat_ind.
(* ===>
nat_ind : forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n *)
(** There's nothing magic about this induction lemma: it's just
another Coq lemma that requires a proof. Coq generates the proof
automatically too... *)
Print nat_ind.
Print nat_rect.
(* ===> (after some manual inlining and tidying)
nat_ind =
fun (P : nat -> Prop)
(f : P 0)
(f0 : forall n : nat, P n -> P (S n)) =>
fix F (n : nat) : P n :=
match n with
| 0 => f
| S n0 => f0 n0 (F n0)
end.
*)
(** We can read this as follows:
Suppose we have evidence [f] that [P] holds on 0, and
evidence [f0] that [forall n:nat, P n -> P (S n)].
Then we can prove that [P] holds of an arbitrary nat [n] via
a recursive function [F] (here defined using the expression
form [Fix] rather than by a top-level [Fixpoint]
declaration). [F] pattern matches on [n]:
- If it finds 0, [F] uses [f] to show that [P n] holds.
- If it finds [S n0], [F] applies itself recursively on [n0]
to obtain evidence that [P n0] holds; then it applies [f0]
on that evidence to show that [P (S n)] holds.
[F] is just an ordinary recursive function that happens to
operate on evidence in [Prop] rather than on terms in [Set].
*)
(** We can adapt this approach to proving [nat_ind] to help prove
_non-standard_ induction principles too. Recall our desire to
prove that
[forall n : nat, even n -> ev n].
Attempts to do this by standard induction on [n] fail, because the
induction principle only lets us proceed when we can prove that
[even n -> even (S n)] -- which is of course never provable. What
we did in [Logic] was a bit of a hack:
[Theorem even__ev : forall n : nat,
(even n -> ev n) /\ (even (S n) -> ev (S n))].
We can make a much better proof by defining and proving a
non-standard induction principle that goes "by twos": *)
Definition nat_ind2 :
forall (P : nat -> Prop),
P 0 ->
P 1 ->
(forall n : nat, P n -> P (S(S n))) ->
forall n : nat , P n :=
fun P => fun P0 => fun P1 => fun PSS =>
fix f (n:nat) := match n with
0 => P0
| 1 => P1
| S (S n') => PSS n' (f n')
end.
(** Once you get the hang of it, it is entirely straightforward to
give an explicit proof term for induction principles like this.
Proving this as a lemma using tactics is much less intuitive (try
it!).
The [induction ... using] tactic variant gives a convenient way to
specify a non-standard induction principle like this. *)
Lemma even__ev' : forall n, even n -> ev n.
Proof.
intros.
induction n as [ | |n'] using nat_ind2.
- (* even 0 *)
apply ev_0.
- (* even 1 *)
inversion H.
- (* even (S(S n')) *)
apply ev_SS.
apply IHn'. unfold even. unfold even in H. simpl in H. apply H.
Qed.
(* ######################################################### *)
(** ** The Coq Trusted Computing Base *)
(** One issue that arises with any automated proof assistant is "why
trust it?": what if there is a bug in the implementation that
renders all its reasoning suspect?
While it is impossible to allay such concerns completely, the fact
that Coq is based on the Curry-Howard correspondence gives it a
strong foundation. Because propositions are just types and proofs
are just terms, checking that an alleged proof of a proposition is
valid just amounts to _type-checking_ the term. Type checkers are
relatively small and straightforward programs, so the "trusted
computing base" for Coq -- the part of the code that we have to
believe is operating correctly -- is small too.
What must a typechecker do? Its primary job is to make sure that
in each function application the expected and actual argument
types match, that the arms of a [match] expression are constructor
patterns belonging to the inductive type being matched over and
all arms of the [match] return the same type, and so on.
There are a few additional wrinkles:
- Since Coq types can themselves be expressions, the checker must
normalize these (by using the computation rules) before
comparing them.
- The checker must make sure that [match] expressions are
_exhaustive_. That is, there must be an arm for every possible
constructor. To see why, consider the following alleged proof
object:
Definition or_bogus : forall P Q, P \/ Q -> P :=
fun (P Q : Prop) (A : P \/ Q) =>
match A with
| or_introl H => H
end.
All the types here match correctly, but the [match] only
considers one of the possible constructors for [or]. Coq's
exhaustiveness check will reject this definition.
- The checker must make sure that each [fix] expression
terminates. It does this using a syntactic check to make sure
that each recursive call is on a subexpression of the original
argument. To see why this is essential, consider this alleged
proof:
Definition nat_false : forall (n:nat), False :=
fix f (n:nat) : False := f n.
Again, this is perfectly well-typed, but (fortunately) Coq will
reject it. *)
(** Note that the soundness of Coq depends only on the correctness of
this typechecking engine, not on the tactic machinery. If there
is a bug in a tactic implementation (and this certainly does
happen!), that tactic might construct an invalid proof term. But
when you type [Qed], Coq checks the term for validity from
scratch. Only lemmas whose proofs pass the type-checker can be
used in further proof developments. *)
(** $Date: 2015-08-11 18:03:04 +0200 (Tue, 11 Aug 2015) $ *)
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_dbg_uart.v
//
// *Module Description:
// Debug UART communication interface (8N1, Half-duplex)
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 34 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Di, 29 Dez 2009) $
//----------------------------------------------------------------------------
`include "timescale.v"
`include "openMSP430_defines.v"
module omsp_dbg_uart (
// OUTPUTs
dbg_addr, // Debug register address
dbg_din, // Debug register data input
dbg_rd, // Debug register data read
dbg_uart_txd, // Debug interface: UART TXD
dbg_wr, // Debug register data write
// INPUTs
dbg_dout, // Debug register data output
dbg_rd_rdy, // Debug register data is ready for read
dbg_uart_rxd, // Debug interface: UART RXD
mclk, // Main system clock
mem_burst, // Burst on going
mem_burst_end, // End TX/RX burst
mem_burst_rd, // Start TX burst
mem_burst_wr, // Start RX burst
mem_bw, // Burst byte width
por // Power on reset
);
// OUTPUTs
//=========
output [5:0] dbg_addr; // Debug register address
output [15:0] dbg_din; // Debug register data input
output dbg_rd; // Debug register data read
output dbg_uart_txd; // Debug interface: UART TXD
output dbg_wr; // Debug register data write
// INPUTs
//=========
input [15:0] dbg_dout; // Debug register data output
input dbg_rd_rdy; // Debug register data is ready for read
input dbg_uart_rxd; // Debug interface: UART RXD
input mclk; // Main system clock
input mem_burst; // Burst on going
input mem_burst_end; // End TX/RX burst
input mem_burst_rd; // Start TX burst
input mem_burst_wr; // Start RX burst
input mem_bw; // Burst byte width
input por; // Power on reset
//=============================================================================
// 1) UART RECEIVE LINE SYNCHRONIZTION & FILTERING
//=============================================================================
// Synchronize RXD input & buffer
//--------------------------------
reg [3:0] rxd_sync;
always @ (posedge mclk or posedge por)
if (por) rxd_sync <= 4'h0;
else rxd_sync <= {rxd_sync[2:0], dbg_uart_rxd};
// Majority decision
//------------------------
reg rxd_maj;
wire [1:0] rxd_maj_cnt = {1'b0, rxd_sync[1]} +
{1'b0, rxd_sync[2]} +
{1'b0, rxd_sync[3]};
wire rxd_maj_nxt = (rxd_maj_cnt>=2'b10);
always @ (posedge mclk or posedge por)
if (por) rxd_maj <= 1'b0;
else rxd_maj <= rxd_maj_nxt;
wire rxd_s = rxd_maj;
wire rxd_fe = rxd_maj & ~rxd_maj_nxt;
wire rxd_re = ~rxd_maj & rxd_maj_nxt;
//=============================================================================
// 2) UART STATE MACHINE
//=============================================================================
// Receive state
//------------------------
reg [2:0] uart_state;
reg [2:0] uart_state_nxt;
wire sync_done;
wire xfer_done;
reg [19:0] xfer_buf;
// State machine definition
parameter RX_SYNC = 3'h0;
parameter RX_CMD = 3'h1;
parameter RX_DATA1 = 3'h2;
parameter RX_DATA2 = 3'h3;
parameter TX_DATA1 = 3'h4;
parameter TX_DATA2 = 3'h5;
// State transition
always @(uart_state or xfer_buf or mem_burst or mem_burst_wr or mem_burst_rd or mem_burst_end or mem_bw)
case (uart_state)
RX_SYNC : uart_state_nxt = RX_CMD;
RX_CMD : uart_state_nxt = mem_burst_wr ?
(mem_bw ? RX_DATA2 : RX_DATA1) :
mem_burst_rd ?
(mem_bw ? TX_DATA2 : TX_DATA1) :
(xfer_buf[`DBG_UART_WR] ?
(xfer_buf[`DBG_UART_BW] ? RX_DATA2 : RX_DATA1) :
(xfer_buf[`DBG_UART_BW] ? TX_DATA2 : TX_DATA1));
RX_DATA1 : uart_state_nxt = RX_DATA2;
RX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
(mem_bw ? RX_DATA2 : RX_DATA1) :
RX_CMD;
TX_DATA1 : uart_state_nxt = TX_DATA2;
TX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
(mem_bw ? TX_DATA2 : TX_DATA1) :
RX_CMD;
default : uart_state_nxt = RX_CMD;
endcase
// State machine
always @(posedge mclk or posedge por)
if (por) uart_state <= RX_SYNC;
else if (xfer_done | sync_done |
mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt;
// Utility signals
wire cmd_valid = (uart_state==RX_CMD) & xfer_done;
wire tx_active = (uart_state==TX_DATA1) | (uart_state==TX_DATA2);
//=============================================================================
// 3) UART SYNCHRONIZATION
//=============================================================================
// After POR, the host needs to fist send a synchronization character (0x80)
// If this feature doesn't work properly, it is possible to disable it by
// commenting the DBG_UART_AUTO_SYNC define in the openMSP430.inc file.
reg sync_busy;
always @ (posedge mclk or posedge por)
if (por) sync_busy <= 1'b0;
else if ((uart_state==RX_SYNC) & rxd_fe) sync_busy <= 1'b1;
else if ((uart_state==RX_SYNC) & rxd_re) sync_busy <= 1'b0;
assign sync_done = (uart_state==RX_SYNC) & rxd_re & sync_busy;
`ifdef DBG_UART_AUTO_SYNC
reg [14:0] sync_cnt;
always @ (posedge mclk or posedge por)
if (por) sync_cnt <= 15'h7ff8;
else if (sync_busy) sync_cnt <= sync_cnt+15'h0001;
wire [11:0] bit_cnt_max = sync_cnt[14:3];
`else
wire [11:0] bit_cnt_max = `DBG_UART_CNT;
`endif
//=============================================================================
// 4) UART RECEIVE / TRANSMIT
//=============================================================================
// Transfer counter
//------------------------
reg [3:0] xfer_bit;
reg [11:0] xfer_cnt;
wire txd_start = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1));
wire rxd_start = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC));
wire xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt==12'h000);
assign xfer_done = (xfer_bit==4'hb);
always @ (posedge mclk or posedge por)
if (por) xfer_bit <= 4'h0;
else if (txd_start | rxd_start) xfer_bit <= 4'h1;
else if (xfer_done) xfer_bit <= 4'h0;
else if (xfer_bit_inc) xfer_bit <= xfer_bit+4'h1;
always @ (posedge mclk or posedge por)
if (por) xfer_cnt <= 12'h000;
else if (rxd_start) xfer_cnt <= {1'b0, bit_cnt_max[11:1]};
else if (txd_start | xfer_bit_inc) xfer_cnt <= bit_cnt_max;
else xfer_cnt <= xfer_cnt+12'hfff;
// Receive/Transmit buffer
//-------------------------
wire [19:0] xfer_buf_nxt = {rxd_s, xfer_buf[19:1]};
always @ (posedge mclk or posedge por)
if (por) xfer_buf <= 18'h00000;
else if (dbg_rd_rdy) xfer_buf <= {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0};
else if (xfer_bit_inc) xfer_buf <= xfer_buf_nxt;
// Generate TXD output
//------------------------
reg dbg_uart_txd;
always @ (posedge mclk or posedge por)
if (por) dbg_uart_txd <= 1'b1;
else if (xfer_bit_inc & tx_active) dbg_uart_txd <= xfer_buf[0];
//=============================================================================
// 5) INTERFACE TO DEBUG REGISTERS
//=============================================================================
reg [5:0] dbg_addr;
always @ (posedge mclk or posedge por)
if (por) dbg_addr <= 6'h00;
else if (cmd_valid) dbg_addr <= xfer_buf[`DBG_UART_ADDR];
reg dbg_bw;
always @ (posedge mclk or posedge por)
if (por) dbg_bw <= 1'b0;
else if (cmd_valid) dbg_bw <= xfer_buf[`DBG_UART_BW];
wire dbg_din_bw = mem_burst ? mem_bw : dbg_bw;
wire [15:0] dbg_din = dbg_din_bw ? {8'h00, xfer_buf[18:11]} :
{xfer_buf[18:11], xfer_buf[8:1]};
wire dbg_wr = (xfer_done & (uart_state==RX_DATA2));
wire dbg_rd = mem_burst ? (xfer_done & (uart_state==TX_DATA2)) :
(cmd_valid & ~xfer_buf[`DBG_UART_WR]) | mem_burst_rd;
endmodule // omsp_dbg_uart
`include "openMSP430_undefines.v"
|
`timescale 1ns/10ps
module usb_121pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("20.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(2),
.output_clock_frequency0("60.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("60.000000 MHz"),
.phase_shift1("8333 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
`timescale 1ns / 1ps
// sonic_sensor.v ver 1.0
// Description by Kazushi Yamashina
// Utsunomiya University
// [email protected]
// _ _ _ _
//clk _| |__| |__ ........... __| |__| |_
// ____
//req __| |___________________________
// ____ ___
//busy ______| ........... |_______
// ______________
//out_data ____________ ....... __result______
//
// req : If you wanna get sensor value, assert req.
// busy : Module is processing while "busy" asserts.
// sig : assign to ultra sonic distance sensor.
// out_data : If "busy" negates, value is publisehd.
module sonic_sensor(
input clk,
input rst,
input req,
output busy,
inout sig,
output [31:0] out_data
output [3:0] led;
);
parameter STATE_INIT = 0,
STATE_IDLE = 1,
STATE_OUT_SIG = 2,
STATE_OUT_END = 3,
STATE_WAIT750 = 4,
STATE_IN_SIG_WAIT = 5,
STATE_IN_SIG = 6,
STATE_IN_SIG_END = 7,
STATE_WAIT200 = 8;
reg [3:0] state;
reg [31:0] echo;
reg [32:0] counter;
reg [31:0] result;
wire count_5u;
wire count_750u;
wire count_200u;
wire time_out;
wire echo_fl;
//for debug
// assign count_5u = counter == 249;
// assign count_750u = counter == 37;
// assign count_200u = counter == 10;
// assign echo_fl = (counter > 25)? 1 : 0;
// assign time_out = counter == 10;
assign count_5u = counter == 499;
assign count_750u = counter == 74998;
assign count_200u = counter == 19999;
assign time_out = counter == 2000;
assign echo_fl = (echo > 1850000)? 1 : 0;
assign sig = (state == STATE_OUT_SIG)? 1 : 1'bZ;
assign busy = (state > STATE_IDLE)?1 : 0;
//state unit
always @(posedge clk)
begin
if(rst)
state <= 0;
else case(state)
STATE_INIT: state <= STATE_IDLE;
STATE_IDLE:if(req) state <= STATE_OUT_SIG;
STATE_OUT_SIG:if(count_5u) state <= STATE_OUT_END;
STATE_OUT_END: state <= STATE_WAIT750;
STATE_WAIT750:if(count_750u) state <= STATE_IN_SIG_WAIT;
STATE_IN_SIG_WAIT: state <= STATE_IN_SIG;
STATE_IN_SIG:begin
if(echo_fl || sig == 0) state <= STATE_IN_SIG_END;
else if(echo == 0 && time_out) state <= STATE_INIT;
end
STATE_IN_SIG_END: state <= STATE_WAIT200;
STATE_WAIT200:if(count_200u) state <= STATE_IDLE;
endcase
end
//counter
always @(posedge clk)
begin
if(rst)
counter <= 0;
else
case(state)
STATE_OUT_SIG: counter <= counter + 1;
STATE_WAIT750: counter <= counter + 1;
STATE_IN_SIG : counter <= counter + 1;
STATE_WAIT200: counter <= counter + 1;
default counter <= 0;
endcase
end
//output
always @(posedge clk)
begin
if(rst)
echo <= 0;
else if(state == STATE_IN_SIG)begin
echo <= echo + 1;
end
else
echo <= 0;
end
always @(posedge clk)begin
if(rst)
result <= 0;
else if(state == STATE_IN_SIG_END)
result <= echo;
end
assign out_data = result[31:0];
assign led = state;
endmodule
|
Require Export Arith.
Require Export Ensembles.
Require Export Classical.
Require Export ProjectiveGeometry.Dev.basic_space_facts.
Require Export ProjectiveGeometry.Dev.proof_irrevelance.
(*****************************************************************************)
(** Flat **)
Ltac last_hyp := match goal with H:_ |- _ => destruct H as [H|H]; contradiction || (subst; new_subst) end.
Section s_flat.
Context `{PS : ProjectiveSpace}.
Context `{EP : EqDecidability Point}.
Context `{EL : EqDecidabilityL Line}.
Lemma strong_a2 : forall A B C D:Point, forall lAB lCD lAC lBD :Line,
~ A [==] C -> ~ B [==] D ->
Incid A lAB/\Incid B lAB ->
Incid C lCD/\Incid D lCD ->
Incid A lAC/\Incid C lAC ->
Incid B lBD/\Incid D lBD ->
(exists I:Point, (Incid I lAB /\ Incid I lCD)) ->
exists J:Point, (Incid J lAC /\Incid J lBD).
Proof.
intros A B C D lAB lCD lAC lBD HAC HBD.
intros.
DecompAndAll.
assert (T:exists I : Point, Incid I lAB /\ Incid I lCD) by assumption.
elim T; intros I (HI1,HI2); clear T.
elim (eq_dec_u A D).
intros HAD; new_subst.
exists D; intuition.
intros .
elim (eq_dec_u B C).
intros HB; new_subst.
exists C; solve [intuition].
intros.
elim (eq_dec_u A B).
intros; new_subst.
exists B; solve [intuition].
intros.
elim (eq_dec_u C D).
intros; new_subst.
solve [eauto].
intros.
eapply (a2 A B C D lAB lCD lAC lBD).
split;intuition.
split;intuition.
split;intuition.
split;intuition.
split;intuition.
destruct H3.
exists x.
split;intuition.
Qed.
Definition pset := Ensemble Point.
Parameter v_subst : forall v : pset, forall A B : Point, A[==]B -> v A -> v B.
Definition pempty : pset := fun (x:Point) => False.
Definition pspace : pset := fun (x:Point) => True.
Definition psingleton (x:Point) : pset := fun (y:Point) => (x[==]y).
Definition pline (l:Line) : pset := fun (x:Point) => Incid x l.
Definition pplane (l1 l2 : Line) (H1 : l1<>l2) (H2 : Intersect l1 l2) : pset :=
fun (x:Point) => exists l : Line, Incid x l /\ exists I, exists J, ~I[==]J /\ Intersect_In l l1 I /\ Intersect_In l l2 J.
Definition flat (v:pset) : Prop :=
forall A B:Point, v A -> v B -> ~ A [==] B ->
forall l:Line, Incid A l -> Incid B l ->
forall C:Point, Incid C l -> v C.
(**********************************************************************************)
(* Lemmas *)
(**********************************************************************************)
(* the empty set is a flat *)
Lemma fp_empty : flat (pempty).
unfold flat, pempty.
intros; tauto.
Qed.
(* the whole space is a flat *)
Lemma fp_space : flat (pspace).
unfold flat, pspace.
tauto.
Qed.
(* singleton points are flats *)
Lemma fp_singleton : forall x:Point, flat (psingleton x).
intros X; unfold flat,psingleton.
intros A B.
intros.
rewrite H in *.
rewrite H0 in *.
assert False; solve [intuition].
Qed.
(* lines are flats *)
Lemma fp_line : forall l:Line, flat (pline l).
intros l.
unfold pline, flat.
intros A B.
intros HAl HBl HAB.
intros l0 HAl0 HBl0.
assert (A [==] B\/(l=l0)).
assert (HH := uniqueness A B l l0 HAl HBl HAl0 HBl0).
destruct HH.
left;rewrite H;reflexivity.
right;assumption.
assert (l=l0) by intuition.
subst l0.
intros C HCl.
trivial.
Qed.
(* general case : A I1 I2 B J1 J2 distincts *)
Lemma fp_plane :
forall l1 l2:Line, forall (H2:l1<>l2), forall (H3:Intersect l1 l2), flat (pplane l1 l2 H2 H3).
intros l1 l2 H2 H3.
unfold flat.
assert (foo := H3); unfold Intersect in ;
elim foo; intro I; intros (HI1, HI2);clear foo.
intros A B HA HB HAB.
intros l HAl HBl C HCl.
unfold pplane in HA, HB.
elim HA; clear HA; intros lA (HAlA,Hexists).
elim Hexists; clear Hexists; intros A1 HA1;
elim HA1; clear HA1; intros A2 (HA1A2,(HIlAl1,HIlAl2)).
elim HB; clear HB; intros lB (HBlB,Hexists).
elim Hexists; clear Hexists; intros B1 HB1;
elim HB1; clear HB1; intros B2 (HB1B2,(HIlBl1,HIlBl2)).
intros.
unfold Intersect_In in *.
DecompAndAll.
(* let's get rid of special cases ... *)
elim (incid_dec A l1).
intros HAl1.
elim (incid_dec B l2).
intros HBl2.
unfold pplane.
exists l.
split.
intuition.
exists A.
exists B.
solve [unfold Intersect_In; intuition].
intros HBl2.
assert (HlAlB:exists J : Point, Incid J lA /\ Incid J lB).
apply (strong_a2 A1 B1 A2 B2 l1 l2 lA lB);unfold Intersect_In in *;(solve [intuition]).
elim (eq_dec_u A2 B2).
intro HA2B2; new_subst.
unfold pplane.
CleanDuplicatedHyps.
compute_case.
assert (X:A1[==]A \/ lA = l1) by assumption.
elim X; clear X.
intro; new_subst.
elim (eq_dec_u I B2).
intro HKB2; new_subst.
Collapse2; last_hyp.
Collapse2; last_hyp.
Collapse2; last_hyp.
elim (second_point B2 l2).
intros D (HD1 , HD2).
elim (a1_exist C D).
intros x (HlC, HlD).
exists x.
split; auto.
exists C.
exists D.
unfold Intersect_In.
split.
intro; new_subst.
Collapse2; last_hyp.
Collapse2; last_hyp.
solve [intuition].
solve [intuition].
intro HKB2.
assert (T : exists J, Incid J l2 /\ Incid J l).
apply (strong_a2 I A B2 B l1 lB l2 l); solve [assumption | split; assumption | intuition fo].
elim T; clear T.
intros L (HL1, HL2).
elim (eq_dec_u A L).
intro; new_subst.
Collapse2; last_hyp.
elim (a1_exist C B2).
intros lCB2 (HZ1, HZ2).
assert (T: exists J : Point, Incid J lCB2 /\ Incid J l1).
apply (strong_a2 C I B2 B1 l lB lCB2 l1).
intro;new_subst.
Collapse2; last_hyp.
contradiction.
intro;new_subst.
Collapse2; last_hyp.
contradiction.
assert(HH := uniqueness I L l1 lA HI1 H8 HI2 HAlA).
last_hyp.
solve[intuition].
Collapse2; last_hyp.
Collapse2; last_hyp.
solve[intuition].
solve[intuition].
solve[intuition].
fo.
elim T; clear T; intros M (HM1 , HM2).
exists lCB2.
split.
solve [intuition].
exists M.
exists B2.
split.
intro; new_subst.
Collapse2; last_hyp.
Collapse2; last_hyp.
solve [unfold Intersect_In; intuition].
intro.
exists l.
split.
solve [auto].
exists A.
exists L.
split; solve [unfold Intersect_In; intuition].
intro; subst.
CleanDuplicatedHyps.
Collapse2; last_hyp.
Collapse2; last_hyp.
elim (second_point B2 l2).
intros D (HD1 , HD2).
elim (a1_exist C D).
intros x (HlC, HlD).
exists x.
split.
solve [auto].
exists C.
exists D.
unfold Intersect_In.
split.
intro;new_subst.
Collapse2; last_hyp.
solve[intuition].
solve[intuition].
intros HA2B2.
unfold pplane.
assert (HNEI2 : (exists J : Point, Incid J l /\ Incid J l2)).
apply (strong_a2 A A2 B B2 lA lB l l2); solve [unfold Intersect_In in *; intuition | fo].
elim HNEI2; clear HNEI2.
intros newI (HnewI1,HnewI2).
elim (incid_dec B l1).
intros HBl1.
assert (Hll1: l=l1).
eapply (a1_unique A B l l1 HAB); solve [intuition].
subst l.
exists l1.
split.
solve [intuition].
elim (second_point newI l1).
intros newJ (HIJ, HJl1).
exists newJ.
exists newI.
split.
assumption.
unfold Intersect_In.
split; solve [intuition].
solve [intuition].
intros HBl1.
assert (Hll1:l<>l1).
intro; subst.
solve [intuition].
elim (eq_dec_l lA l1).
intro; subst.
CleanDuplicatedHyps.
elim (eq_dec_u A newI).
intro HAnewI; rewrite HAnewI in *; clear HAnewI.
Collapse2; last_hyp.
elim (eq_dec_u C B1).
intro; new_subst.
assert(HH := uniqueness newI B1 l l1 HAl HCl H5 H4).
last_hyp.
Collapse2; last_hyp.
contradiction.
intro.
elim (a1_exist C B1).
intros lCB1 (HClCB1 , HB1lCB1).
assert (T:exists J : Point, Incid J lCB1 /\ Incid J l2).
apply (strong_a2 C newI B1 B2 l lB lCB1 l2);(solve [assumption | (split; assumption) | intuition fo]).
elim T; clear T; intros J (HJ1, HJ2).
exists lCB1.
split.
solve [auto].
exists B1.
exists J.
split.
intro HB1J; rewrite HB1J in *; clear HB1J.
Collapse2; last_hyp.
contradiction.
solve [unfold Intersect_In; intuition].
intro HAnewI.
exists l.
split.
solve [auto].
exists A.
exists newI.
split.
auto.
solve [unfold Intersect_In; auto].
intro HlAl1.
Collapse2; last_hyp.
assert (T: exists J : Point, Incid J l /\ Incid J l2).
apply (strong_a2 B B2 A A2 lB lA l l2); (solve [intuition | destruct HlAlB; fo]).
elim T;intros J (HJ1, HJ2);clear T.
elim (eq_dec_l l l2).
intro;subst.
contradiction.
intros.
elim (eq_dec_u A J).
intro; new_subst.
elim (a1_exist C A2).
intros lCA2 (HlCA2C, HlCA2A2).
elim (a1_exist B1 C).
intros lB1C (HlB1C1, HlB1C2).
assert (T: exists J : Point, Incid J lB /\ Incid J lCA2).
apply (strong_a2 B2 A2 B C l2 l lB lCA2).
intro;new_subst.
Collapse2; last_hyp.
intro;new_subst.
Collapse2; last_hyp.
Collapse2; last_hyp.
solve[intuition].
solve[intuition].
solve[intuition].
solve[intuition].
fo.
elim T; clear T;intros J' (HJ'1, HJ'2).
assert (T: exists J : Point, Incid J lB1C /\ Incid J l2).
apply (strong_a2 B1 B2 C A2 lB lCA2 lB1C l2).
intro;new_subst.
Collapse2; last_hyp.
Collapse2; last_hyp.
Collapse2; last_hyp.
Collapse2; last_hyp.
Collapse2; last_hyp.
intro;new_subst.
Collapse2; last_hyp.
apply HA2B2; reflexivity.
solve[intuition].
solve[intuition].
solve[intuition].
solve[intuition].
fo.
elim T; clear T;intros K (HK1, HK2).
assert (T: exists J : Point, Incid J l1 /\ Incid J lCA2).
apply (strong_a2 B1 C I A2 lB1C l2 l1 lCA2).
intro;new_subst.
Collapse2; last_hyp.
Collapse2; last_hyp.
contradiction.
intro;new_subst.
Collapse2; last_hyp.
Collapse2; last_hyp.
solve[intuition].
solve[intuition].
solve[intuition].
solve[intuition].
fo.
elim T; clear T;intros L (HL1, HL2).
exists lCA2.
split.
solve [auto].
exists L.
exists A2.
split.
intro;new_subst.
Collapse2; last_hyp.
Collapse2; last_hyp.
Collapse2; last_hyp.
solve [unfold Intersect_In; intuition].
intro.
Collapse2; last_hyp.
exists l.
split.
solve [auto].
exists A.
exists J.
solve [unfold Intersect_In; intuition].
intros HAl1.
elim (incid_dec B l1).
intro.
compute_cases. (* TODO: transform the following in last_hyp *)
assert (X : B1[==]B \/ lB = l1) by assumption.
elim X; clear X.
intro; new_subst.
elim (eq_dec_u A2 B2).
intro; new_subst.
unfold pplane.
CleanDuplicatedHyps.
elim (eq_dec_l l l2).
intro; subst.
Collapse2; last_hyp.
exists l2.
split.
solve [auto].
exists B; exists B2;repeat split;
solve [unfold Intersect_In in *; intuition].
intro Hll2.
elim (eq_dec_u A B2).
intro; new_subst.
Collapse2; last_hyp.
exists lB.
split.
solve [auto].
exists B; exists B2; repeat split;
solve [unfold Intersect_In in *; intuition].
intro HAB2.
elim (eq_dec_u B2 I).
intro; new_subst.
Collapse2; last_hyp.
Collapse2; last_hyp.
intro HBIII.
assert (T:exists J : Point, Incid J l /\ Incid J l2).
apply (strong_a2 A B2 B I lA l1 l l2);(solve [intuition | (intro; new_subst;intuition) |fo]).
elim T; intro Q; intros (HQ1, HQ2);clear T.
elim (eq_dec_u B Q).
intro; new_subst.
Collapse2; last_hyp.
elim (a1_exist C A1).
intro lCA1.
intros (Hx1, Hx2).
elim (eq_dec_u C A1).
intro.
Collapse2; last_hyp.
destruct (a1_exist A1 B2) as [lA1B2 (HA1B2a,HA1B2b)].
exists lA1B2.
split.
new_subst.
solve [auto].
exists A1.
exists B2.
solve [unfold Intersect_In in *; intuition].
intro.
assert (T:exists J : Point, Incid J lCA1 /\ Incid J l2).
apply (strong_a2 C Q A1 B2 l lA lCA1 l2); (solve [assumption | split; assumption | intuition fo]).
exists lCA1.
split;auto.
exists A1.
elim T;intro Q';intros (HQ1', HQ2'); clear T.
exists Q'.
unfold Intersect_In; repeat split.
intro; new_subst.
Collapse2; last_hyp.
Collapse2; last_hyp.
solve[intuition].
solve[intuition].
solve[intuition].
solve[intuition].
intro HnotBQ.
exists l.
split.
solve [auto].
exists B.
exists Q.
solve [unfold Intersect_In; split; auto].
intro HA2B2.
elim (eq_dec_u B I).
intro; new_subst.
Collapse2. (* ??? *)
elim (a1_exist C A2).
intro lCA2.
intros (HX, HY).
elim (eq_dec_u C A2).
intro; new_subst.
unfold pplane.
exists lA.
split.
solve [auto].
exists A1; exists A2; repeat split; solve [unfold Intersect_In in *; intuition].
intros HCA2.
elim (eq_dec_u I A1).
intro; new_subst.
Collapse2; last_hyp.
Collapse2; last_hyp.
Collapse2; last_hyp.
exists l2.
split.
solve [auto].
exists A1; exists B2;
solve [unfold Intersect_In in *; intuition].
intros HIA1.
assert (X:exists J : Point, Incid J lCA2 /\ Incid J l1).
apply (strong_a2 C I A2 A1 l lA lCA2 l1); (solve [assumption | split; assumption | intuition fo]).
elim X;intro Q;intros (HQ1,HQ2);clear X.
exists lCA2.
split.
solve [auto].
exists Q.
exists A2.
split.
intro; new_subst.
Collapse2; last_hyp.
contradiction.
solve [unfold Intersect_In;auto].
intro HI.
assert (X:exists J : Point, Incid J lA /\ Incid J lB).
apply (strong_a2 A1 B A2 B2 l1 l2 lA lB); (solve [intuition]).
assert (T:exists J : Point, Incid J l /\ Incid J l2).
apply (strong_a2 A A2 B B2 lA lB l l2); (solve [intuition]).
elim T;intro R; intros (HR1, HR2);clear T.
exists l.
unfold Intersect_In.
split.
solve [auto].
exists B.
exists R.
split.
intro; new_subst.
Collapse2; last_hyp.
Collapse2; last_hyp.
solve[intuition].
intro; subst.
assert (T:exists J : Point, Incid J l /\ Incid J l2).
apply (strong_a2 A A2 B B2 lA l1 l l2).
intro;new_subst.
Collapse2; last_hyp.
intro;new_subst.
Collapse2; last_hyp.
contradiction.
solve[intuition].
solve[intuition].
solve[intuition].
solve[intuition].
fo.
elim T; intros Q (HQ1,HQ2); clear T.
elim (eq_dec_u B Q).
intro; new_subst.
Collapse2; last_hyp.
elim (eq_dec_u C A1).
intro; new_subst.
CleanDuplicatedHypsModulo.
exists l1; split; [solve [auto] | idtac].
exists B1; exists Q.
solve [unfold Intersect_In; intuition].
intros HCA1x.
elim (a1_exist C A1).
intros CA1 (HCA1,HCA1').
assert (T:exists J : Point, Incid J CA1 /\ Incid J l2).
apply (strong_a2 C Q A1 A2 l lA CA1 l2).
intro; new_subst.
Collapse2; last_hyp.
solve[intuition].
intro;new_subst.
Collapse2; last_hyp.
revert H1; intros H1; last_hyp.
solve [intuition].
solve[intuition].
solve[intuition].
solve[intuition].
solve[intuition].
fo.
elim T; intros R (HR1,HR2); clear T.
elim (eq_dec_u A1 R).
intro; new_subst.
Collapse2; last_hyp.
solve [exists l; firstorder].
intros HA1R.
exists CA1.
split; auto.
exists A1.
exists R.
split.
assumption.
solve [unfold Intersect_In; intuition].
intros HBQ.
exists l.
split; auto.
exists B.
exists Q.
solve [split; unfold Intersect_In; auto].
intros HBl1.
elim (incid_dec A l2).
intros HAl2.
assert (T:exists J : Point, Incid J lA /\ Incid J lB).
apply (strong_a2 A1 B1 A B2 l1 l2 lA lB).
intro;new_subst.
Collapse2; last_hyp.
assumption.
solve[intuition].
solve[intuition].
solve[intuition].
solve[intuition].
fo.
elim (eq_dec_u A1 B1).
intro; new_subst.
elim (eq_dec_u I B1).
(* A1=B1 et I=B1 *)
intro; new_subst.
Collapse2; last_hyp.
Collapse2; last_hyp.
Collapse2; last_hyp.
exists l2.
split.
solve [auto].
exists B1.
exists A2.
solve [unfold Intersect_In in *; intuition].
intros HIB1.
assert (X:exists J : Point, Incid J l /\ Incid J l1).
apply (strong_a2 A I B B1 l2 lB l l1); (solve [intuition | exists B2; intuition]).
elim X; intros Q (HQ1,HQ2); clear X.
exists l.
split; auto.
exists Q.
exists A.
split.
intro; new_subst.
Collapse2; last_hyp.
solve [unfold Intersect_In; split; intuition].
intros HA1B1.
assert (U:exists J : Point, Incid J l1 /\ Incid J l).
apply (strong_a2 A1 A B1 B lA lB l1 l); (solve [intuition]).
elim U; intros Q (HQ1,HQ2); clear U.
unfold pplane.
exists l.
split; auto.
exists Q.
exists A.
split ; [idtac | unfold Intersect_In; intuition].
intro;new_subst.
Collapse2; last_hyp.
intros HAl2.
elim (incid_dec B l2).
intros HBl2.
assert (exists J : Point, Incid J lA /\ Incid J lB).
apply (strong_a2 A1 B1 A2 B l1 l2 lA lB).
assumption.
intro; new_subst.
Collapse2; last_hyp.
solve[intuition].
solve[intuition].
solve[intuition].
solve[intuition].
fo.
elim (eq_dec_u A1 B1).
intro; new_subst.
assert (T: exists J : Point, Incid J l1 /\ Incid J l).
apply (strong_a2 B1 A I B lA l2 l1 l).
intro; new_subst.
Collapse2; last_hyp.
contradiction.
solve[intuition].
solve[intuition].
solve[intuition].
solve[intuition].
solve[intuition].
fo.
elim T; intros Q (HQ1,HQ2); clear T.
exists l.
split; auto.
exists Q.
exists B.
split.
intro; new_subst.
Collapse2; last_hyp.
solve [unfold Intersect_In; intuition].
intros HA1B1.
assert (T:exists J : Point, Incid J l /\ Incid J l1).
apply (strong_a2 A A1 B B1 lA lB l l1); (solve[intuition]).
elim T; intros Q (HQ1,HQ2); clear T.
exists l.
split; auto.
exists Q.
exists B.
split.
intro; new_subst.
Collapse2; last_hyp.
solve [unfold Intersect_In; intuition].
intros HBl2.
(* main case : A and B do not belong to l1 and l2. *)
elim (eq_dec_u A1 B1).
intro; new_subst.
elim (a1_exist I A).
intros KA (HKA1, HKA2).
elim (eq_dec_u I A).
intro; new_subst; solve [intuition].
intro.
assert (T:exists J : Point, Incid J KA /\ Incid J lB).
apply (strong_a2 I B2 A B1 l2 lA KA lB);solve[intuition | fo].
elim T; clear T; intros M (HM1, HM2).
elim (eq_dec_u I B1).
intro; new_subst.
Collapse2; last_hyp.
Collapse2; last_hyp.
solve[intuition].
intro.
assert (U:exists J : Point, Incid J l1 /\ Incid J l).
apply (strong_a2 I A B1 B KA lB l1 l); (solve [assumption | split; assumption| intuition fo]).
elim U; intros N (HN1 , HN2);clear U.
elim (eq_dec_u A2 B2).
intro; new_subst.
Collapse2; last_hyp.
Collapse2; last_hyp.
compute_case; last_hyp.
compute_cases; last_hyp.
unfold pplane.
exists lA.
split.
solve [auto].
exists N.
exists B2.
solve [unfold Intersect_In; intuition].
unfold pplane.
exists lA.
split.
solve [auto].
exists N.
exists B2.
solve [unfold Intersect_In; intuition].
unfold pplane.
exists lA.
split.
solve [auto].
exists N.
exists B2.
solve [unfold Intersect_In; intuition].
intro.
assert (V:exists J : Point, Incid J l /\ Incid J l2).
apply (strong_a2 A A2 B B2 lA lB l l2); (solve [assumption | split; assumption | intuition fo]).
elim V;clear V; intros P (HP1, HP2).
elim (eq_dec_u P N).
intro; new_subst.
Collapse2; last_hyp.
Collapse2; last_hyp.
compute_case.
assert(V := uniqueness M B lB KA HM2 HBlB HM1 HBl).
assert(VV := V).
elim V; clear V.
intro; new_subst.
CleanDuplicatedHyps.
unfold pplane.
elim (a1_exist C B1).
intros CB1 (HCB1, HCB2).
assert (T: exists J : Point, Incid J l2 /\ Incid J CB1).
apply (strong_a2 N C A2 B1 KA lA l2 CB1).
intro;new_subst.
Collapse2; last_hyp.
contradiction.
intro;new_subst.
Collapse2; last_hyp.
contradiction.
solve[intuition].
solve[intuition].
solve[intuition].
solve[intuition].
fo.
elim T; clear T; intros J (HJ1, HJ2).
elim (eq_dec_u B1 J).
intro; new_subst.
Collapse2; last_hyp.
intro.
exists CB1.
split.
solve [auto].
exists B1.
exists J.
solve [unfold Intersect_In; intuition].
intro; subst.
Collapse2; last_hyp.
contradiction.
intro HPN.
exists l.
split.
solve [auto].
exists N.
exists P.
split.
intro; apply HPN; symmetry; assumption.
solve [unfold Intersect_In;auto].
intros HA1B1.
elim (eq_dec_u A2 B2).
intros HA2B2; new_subst.
elim (a1_exist A I).
intros AK (HAK1, HAK2).
assert (T:exists J : Point, Incid J AK /\ Incid J lB).
apply (strong_a2 A B2 I B1 lA l1 AK lB).
intro;new_subst;solve[intuition].
solve[intuition].
solve[intuition].
solve[intuition].
solve[intuition].
solve[intuition].
fo.
elim T; clear T; intros M (HM1, HM2).
assert (U:exists J : Point, Incid J l /\ Incid J l2).
apply (strong_a2 A I B B2 AK lB l l2).
solve[intuition].
intro;new_subst.
Collapse2; last_hyp.
contradiction.
solve[intuition].
solve[intuition].
solve[intuition].
solve[intuition].
fo.
elim U; intros N (HN1,HN2).
assert (V:exists J : Point, Incid J l /\ Incid J l1).
apply (strong_a2 A A1 B B1 lA lB l l1); (solve [assumption | split; assumption | intuition fo]).
elim V; intros P (HP1,HP2).
elim (eq_dec_u P N).
intro; new_subst.
Collapse2; last_hyp.
compute_cases_old.
assert (W:A[==]N \/ AK = l) by assumption.
elim W; clear W.
intro; new_subst.
CleanDuplicatedHyps.
solve[intuition].
intro; subst.
CleanDuplicatedHyps.
elim (a1_exist C B2).
intros CB2 (HCB2,HCB2').
elim (a1_exist C A1).
intros CA1 (HCA1, HCA1').
elim (eq_dec_u C A1).
intro; new_subst.
assert (W:A1[==]B2\/lA=CB2) by (compute_cases_old; assumption).
elim W; clear W.
solve [intro; intuition].
intro; subst.
exists CB2.
split.
assumption.
exists A1; exists B2; repeat split; solve [intuition].
intros HnotCA1.
elim (eq_dec_u C B2).
intro; new_subst.
unfold pplane.
exists CA1.
split.
solve [auto].
exists A1.
exists B2.
split.
solve [intuition].
split; solve [unfold Intersect_In in *; intuition].
intro.
exists CB2.
split.
solve [auto].
elim (eq_dec_u B B1).
intro; new_subst; solve[intuition].
intros HBB1.
assert (W:exists I:Point, Incid I lB /\ Incid I CA1).
apply (strong_a2 B1 A1 B C l1 l lB CA1); solve [intuition | destruct V; fo].
assert (X:exists J : Point, Incid J CB2 /\ Incid J l1).
eapply (strong_a2 C A1 B2 B1 CA1 lB CB2 l1); solve [intuition| destruct W; fo].
elim X; intros Z (HZ1,HZ2); clear X.
exists Z.
exists B2.
split.
intro; new_subst.
Collapse2; last_hyp.
contradiction.
solve [unfold Intersect_In; intuition].
intros HPN.
unfold pplane.
exists l.
split.
solve [auto].
exists P.
exists N.
split.
solve [auto].
solve [unfold Intersect_In; intuition].
(* ok *)
intros HA2B2.
assert (exists J : Point, Incid J lA /\ Incid J lB).
apply (strong_a2 A1 B1 A2 B2 l1 l2 lA lB); unfold Intersect_In in *; (solve [intuition]).
(* lA lB meet ! *)
assert (HNEI1 : (exists J : Point, Incid J l /\ Incid J l1)).
apply (a2 A A1 B B1 lA lB l l1) ; unfold Intersect_In in *;
repeat split; solve [intuition | intro; new_subst; Collapse2; intuition].
assert (HNEI2 : (exists J : Point, Incid J l /\ Incid J l2)).
apply (strong_a2 A A2 B B2 lA lB l l2); solve [intuition].
elim HNEI1; clear HNEI1.
elim HNEI2; clear HNEI2.
intros P2 (HP2l,HP2l2); intros P1 (HP1l,HP1l1).
elim (eq_dec_u P1 P2).
intros HP1P2; new_subst.
assert (Hdist3 : ~(A1[==]P2) /\ ~(A2[==]C)).
split.
intro; new_subst.
Collapse2; last_hyp.
solve[intuition].
intro; new_subst.
elim (eq_dec_u A C).
intro; new_subst.
Collapse2; last_hyp.
intros; Collapse2; last_hyp.
elim (eq_dec_u A1 P2).
intros; new_subst.
Collapse2; last_hyp.
contradiction.
intros; Collapse2; last_hyp.
contradiction.
generalize (a1_exist A2 C); intros Hlnew; elim Hlnew; clear Hlnew; intros lnew Hlnew.
assert (HNEI: exists J : Point, Incid J l1 /\ Incid J lnew).
apply (strong_a2 A1 A2 P2 C lA l l1 lnew); solve [intuition | fo].
elim HNEI; intros X HX.
exists lnew.
split.
intuition.
exists X.
exists A2.
split.
DecompAndAll.
intro; new_subst.
Collapse2; last_hyp.
contradiction.
solve [unfold Intersect_In; intuition].
intros HP1P2.
exists l.
split.
solve [intuition].
exists P1.
exists P2.
solve [unfold Intersect_In; intuition].
Qed.
(* characterization *)
(* decomposition requires excluded middle *)
Lemma set01 : forall v:pset, (exists x:Point, v(x)) \/ forall x:Point, ~v(x).
intros v.
elim (classic (exists x:Point, v(x))).
intros; left; intuition.
intros H2; right.
intros x Hx.
apply H2.
exists x.
assumption.
Qed.
Lemma set12 : forall v:pset, (exists x:Point, v(x)) ->
(exists a :Point, exists b:Point, ~(a[==]b)/\v(a)/\v(b))\/(exists w:Point, v(w)/\forall p:Point, ~(p[==]w) -> ~v(p)).
intros v H2.
elim H2; intros v1 Hv1; clear H2.
elim (classic (forall p:Point, ~(p[==]v1) -> ~v(p))).
intros Hc.
right.
exists v1.
intuition.
intros Hc.
left.
exists v1.
apply not_all_not_ex.
intros H2.
apply Hc.
intros p Hpv1.
generalize (H2 p).
intuition.
Qed.
Lemma set23 : forall v:pset, (exists a :Point, exists b:Point, ~(a[==]b)/\v(a)/\v(b)) ->
(exists a :Point, exists b:Point, exists c:Point, ~(a[==]b)/\~(a[==]c)/\~(b[==]c)/\v(a)/\v(b)/\v(c))
\/(exists a:Point, exists b:Point, ~(a[==]b)/\v(a)/\v(b)/\forall p:Point, ~(p[==]a) -> ~(p[==]b) -> ~v(p)).
intros v H2.
elim H2; intros a Ha; clear H2.
elim Ha; intros b (Hab,(Hva,Hvb)).
elim (classic (forall p:Point, ~(p[==]a) -> ~(p[==]b) -> ~v(p))).
intros Hc.
right.
exists a.
exists b.
intuition.
intros Hc.
left.
exists a.
exists b.
apply not_all_not_ex.
intros H2.
apply Hc.
intros p Hpa Hpb.
generalize (H2 p).
intuition.
Qed.
(* either zero, one, two or at least 3 points in v *)
Lemma pset_decompose :
forall v:pset,
(forall x:Point, ~(v x))
\/(exists y:Point, v y /\ forall x:Point, ~x[==]y -> ~v x)
\/(exists x:Point, exists y:Point, ~(x[==]y)/\v(x)/\v(y)/\forall p:Point, ~(p[==]x) -> ~(p[==]y) -> ~v(p))
\/(exists x :Point, exists y:Point, exists z:Point, ~(x[==]y)/\~(x[==]z)/\~(y[==]z)/\v(x)/\v(y)/\v(z)).
Proof.
intros v.
elim (set01 v).
intros H2.
elim (set12 v H2).
intros H'.
elim (set23 v H').
right;right;right.
assumption.
intros H''.
right;right;left.
assumption.
intros H''.
right;left.
assumption.
left.
assumption.
Qed.
(* either v is included in w or there exists p in v and not in w *)
Lemma included_or_not : forall v w: pset,
(forall p:Point, v(p) -> w(p))\/(exists p:Point, v(p)/\~ w(p)).
intros v w.
elim (classic (forall p : Point, v p -> w p)).
intros; left; intuition.
intros;right.
apply not_all_not_ex.
intros H'.
apply H.
intros p Hvp.
elim (not_and_or (v p) (~ w p) (H' p)).
intros H3; cut False.
intros Hf; elim Hf.
apply H3; assumption.
intros Hnotnot.
elim (classic (w p)).
intuition.
intros Hnot.
elim (Hnotnot Hnot).
Qed.
(* "en dim 3, les seuls plats sont : l'ensemble vide, les points (singletons), les droites (d:M | Incid M d), les plans (l1, l2) et l'espace tout entier" *)
(* intermediate lemma : a line and a plane always intersect *)
Lemma plane_line : forall l1 l2:Line, forall l:Line, forall (H:l1<>l2), forall (H':Intersect l1 l2),
exists P:Point, pplane l1 l2 H H' P /\ Incid P l.
intros l1 l2 l H2 H'.
elim (eq_line_dec l1 l).
intro; subst.
elim (a3_1 l).
intros A HA; elim HA; clear HA; intros B HB; elim HB; clear HB; intros C (HABC,(HA',(HB',HC'))).
elim (incid_dec A l2).
intros HAl2.
assert (~Incid B l2).
intro HBl2.
compute_cases.
DecompAndAll.
Collapse2.
solve [intuition].
elim (a3_1 l2).
intros A2 HA2; elim HA2; clear HA2; intros B2 HB2; elim HB2; clear HB2;
intros C2 (HABC2,(HA2,(HB2,HC2))).
exists B.
elim (incid_dec A2 l).
intros HA2l2.
assert (~Incid B2 l).
intro HB2l.
compute_cases.
DecompAndAll.
Collapse2.
solve [intuition].
elim (a1_exist B B2).
intros m (HBm, HB2m).
unfold pplane.
split; [idtac | auto].
exists m.
split.
auto.
exists B.
exists B2.
split.
intro; new_subst; solve [intuition].
solve [unfold Intersect_In;intuition].
DecompAndAll;solve[intuition].
intros HA2l.
split; [idtac | auto].
elim (a1_exist B A2).
intros m (HBm, HB2m).
unfold pplane.
exists m.
split.
auto.
exists B.
exists A2.
split.
intro; new_subst; solve [intuition].
solve [unfold Intersect_In; intuition].
DecompAndAll;solve[intuition].
intros HAl2.
exists A.
elim (a3_1 l2).
intros A2 HA2; elim HA2; clear HA2; intros B2 HB2; elim HB2; clear HB2;
intros C2 (HABC2,(HA2,(HB2,HC2))).
elim (incid_dec A2 l).
intros HA2l.
assert (~Incid B2 l).
intro HB2l.
compute_cases.
DecompAndAll.
Collapse2.
solve [intuition].
elim (a1_exist A B2).
intros m (HBm, HB2m).
split.
unfold pplane.
exists m.
split.
auto.
exists A.
exists B2.
split.
intro;new_subst; solve [intuition].
solve [unfold Intersect_In; intuition].
DecompAndAll;assumption.
intros HA2l.
elim (a1_exist A A2).
intros m (HBm, HA2m).
split.
unfold pplane.
exists m.
split.
auto.
exists A.
exists A2.
split.
intro; new_subst; solve [intuition].
solve [unfold Intersect_In; intuition].
DecompAndAll;assumption.
intros Hl1l.
elim (eq_line_dec l2 l).
intros; subst.
elim (a3_1 l).
intros A HA; elim HA; clear HA; intros B HB; elim HB; clear HB;
intros C (HABC,(HA,(HB,HC))).
elim (a3_1 l1).
intros A1 HA1; elim HA1; clear HA1; intros B1 HB1; elim HB1; clear HB1;
intros C1 (HABC1,(HA1,(HB1,HC1))).
elim (incid_dec A l1).
intro HAl1.
assert (~Incid B l1).
intro HBl1.
compute_cases.
DecompAndAll.
Collapse2.
solve [intuition].
exists B.
elim (incid_dec A1 l).
intros HA1l.
assert (~Incid B1 l).
intro HB1l.
compute_cases.
DecompAndAll.
Collapse2.
solve [intuition].
split; [idtac | auto].
unfold pplane.
elim (a1_exist B B1).
intros m (HmB,HmB1).
exists m.
split.
auto.
exists B1.
exists B.
split.
intro; new_subst; solve [intuition].
solve [unfold Intersect_In; intuition].
DecompAndAll;solve [intuition].
intros HA1l.
elim (a1_exist B A1).
intros m (HmB,HmA1).
split; [idtac|auto].
exists m.
split;auto.
exists A1.
exists B.
split.
intro; new_subst; solve [intuition].
solve [unfold Intersect_In; intuition].
DecompAndAll;solve [intuition].
intros HAl1.
exists A.
elim (incid_dec A1 l).
intros HA1l.
assert (~Incid B1 l).
intro.
compute_cases.
DecompAndAll.
Collapse2.
solve [intuition].
elim (a1_exist B1 A).
intros m (HmB1,HmA).
split.
exists m.
split.
auto.
exists B1.
exists A.
split.
intro; new_subst; solve [intuition].
solve [unfold Intersect_In; intuition].
DecompAndAll;assumption.
intros HA1l.
elim (a1_exist A1 A).
intros m (HmA1,HmA).
split.
exists m.
split.
auto.
exists A1.
exists A.
split.
intro; new_subst; solve [intuition].
solve [unfold Intersect_In; intuition].
DecompAndAll;assumption.
intros Hl2l.
elim (a3_3 l l1 l2).
intros l4 H'4.
elim H'4; clear H'4;intros J1 HJ1;elim HJ1; clear HJ1;
intros J2 HJ2; elim HJ2; clear HJ2.
intros J3 (HJ1,(HJ2,HJ3)).
(* ici commence les problemes*)
exists J1.
split.
exists l.
split.
solve [unfold Intersect_In in *; intuition].
admit.
solve [unfold Intersect_In in *; intuition].
(*
exists J1.
split.
exists l4.
split.
solve [unfold Intersect_In in *; intuition].
exists J2.
exists J3.
solve [unfold Intersect_In in *; intuition].
solve [unfold Intersect_In in *; intuition].*)
solve [intuition].
Admitted.
Section s_flatPI.
Context `{PI : ProofIrrevelance}.
Lemma characterization : forall v:pset, flat v ->
(forall x:Point, (v x)<->(pempty x))
\/ (exists y:Point, forall x:Point, ((v x) <-> ((psingleton y) x)))
\/ (exists l:Line, forall x:Point, ((v x) <-> ((pline l) x)))
\/ (exists l1:Line, exists l2:Line, forall H:l1<>l2, forall H':Intersect l1 l2, forall x:Point, ((v x) <-> (pplane l1 l2 H H' x)))
\/(forall x:Point, (v x) <-> (pspace x)).
intros v Hflat.
unfold flat in Hflat.
elim (pset_decompose v).
(* empty set *)
intros Hempty.
left.
unfold pempty.
intros x; split.
apply Hempty.
intuition.
intros Helim; elim Helim.
(* singleton *)
intros Hsingleton.
right; left.
elim Hsingleton.
intros wit [Hwit1 Hwit2].
unfold psingleton.
exists wit.
intros x; split.
generalize Hwit1 Hwit2; case (eq_dec_u wit x).
solve [intuition].
intros Hwitx Hvwit Hforall Hvx0.
assert (~(x [==] wit)) by intuition.
elim (Hwit2 x H Hvx0).
intros.
apply v_subst with (A:=wit).
assumption.
assumption.
clear Helim; intros Hatleast2.
(* at least 2 elements *)
elim Hatleast2; [intro Hequal2 | intro Hatleast3]; clear Hatleast2.
(* exactly 2 points *)
elim Hequal2; intros A H'; elim H'; clear H'.
intros B.
(* a line *)
intros [ HnAB [HvA [HvB Hv]]].
elim (a1_exist A B).
intros l [ HAl HBl ].
right;right;left.
exists l.
unfold pline.
intros x; elim (incid_dec x l).
intros Hxl.
split.
intuition.
intros HIncid.
eapply Hflat with (A:=A) (B:=B) (l:=l) ; assumption.
intros nIncid.
split.
intros Hvx.
case (eq_dec_u x A).
intro; new_subst; solve [intuition].
intros HxA.
case (eq_dec_u x B).
intro; new_subst; solve [intuition].
intros HxB.
elim (Hv x HxA HxB Hvx).
intros Hf; cut False; solve [intuition].
(* at least 3 points *)
elim Hatleast3; clear Hatleast3;
intros x Ha1; elim Ha1; clear Ha1; intros y Ha2; elim Ha2; clear Ha2; intros z (Hxy,(Hxz, (Hyz, (Hvx, (Hvy, Hvz))))).
elim (a1_exist x y).
intros l (Hlx,Hly).
elim (included_or_not v (fun p => Incid p l)).
(* every single point belongs to l *)
intros Hline.
right;right;left.
unfold pline.
exists l; intros a; split.
intuition.
eapply Hflat with (l:=l) (A:=x) (B:=y); intuition.
(* at least a plane : one point outside l *)
intros Hex; elim Hex; clear Hex; intros O (HvO,HnIncid).
elim (a1_exist x O).
intros l2 (Hxl2, HOl2).
assert (H'1 : (l<>l2)).
intro; subst; intuition.
assert (H'2:(Intersect l l2)).
unfold Intersect.
exists x; intuition.
(* everything in v is in the plane ! *)
elim (included_or_not v (pplane l l2 H'1 H'2)).
intros Hplane.
right;right;right;left.
exists l.
exists l2.
intros Ha Hb w; split.
intros Hvw.
rewrite (proof_irr (l<>l2) Ha H'1).
rewrite (proof_irr (Intersect l l2) Hb H'2).
intuition.
unfold pplane.
intros Hpplane.
elim Hpplane.
intros lw (Hwlw, Hex).
elim Hex; clear Hex; intros I HI; elim HI; intros J (HIJ,(HIlw, HJlw)).
eapply Hflat with (l:=lw) (A:=I) (B:=J); unfold Intersect_In in *;try (solve [intuition]).
eapply Hflat with (l:=l) (A:=x) (B:=y); (solve [intuition]).
eapply Hflat with (l:=l2) (A:=O) (B:=x); try (solve [intuition]).
intro; new_subst; solve [intuition].
(* at least one point is outside the plane *)
intros Hext; elim Hext; clear Hext; intros Q (HQ1,HQ2).
right;right;right;right.
intros w; unfold pspace; split.
trivial.
intros Htrue.
elim (eq_dec_u Q w).
intros; apply v_subst with (A:=Q); assumption.
intros HQw.
elim (a1_exist Q w); intros Qw (HQw1,HQw2).
elim (plane_line l l2 Qw H'1 H'2).
intros P (HP1,HP2).
eapply Hflat with (l:=Qw) (A:=Q) (B:=P); try (solve [intuition]).
elim HP1.
intros m (Hm1, Hex).
elim Hex; clear Hex; intros I HI; elim HI; intros J (HIJ,(HIlw, HJlw)).
eapply Hflat with (l:=m) (A:=I) (B:=J); unfold Intersect_In in *; try (solve [intuition]).
eapply Hflat with (l:=l) (A:=x) (B:=y); (solve [intuition]).
eapply Hflat with (l:=l2) (A:=O) (B:=x); try (solve [intuition]).
intro; new_subst; solve [intuition].
intro; new_subst; solve [intuition].
Qed.
End s_flatPI.
End s_flat.
(* Local Variables: *)
(* coq-prog-name: "coqtop" *)
(* coq-load-path: (("/Users/magaud/containers/theories" "Containers") ("/Users/magaud/galapagos/dev/trunk/ProjectiveGeometry/" "ProjectiveGeometry") ) *)
(* suffixes: .v *)
(* End: *) |
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
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// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// related to, arising under or in connection with these
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_ck_addr_cmd_delay.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Module to decrement initial PO delay to 0 and add 1/4 tck for tdqss
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_0_ddr_phy_wrlvl_off_delay #
(
parameter TCQ = 100,
parameter tCK = 3636,
parameter nCK_PER_CLK = 2,
parameter CLK_PERIOD = 4,
parameter PO_INITIAL_DLY= 46,
parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 8,
parameter N_CTL_LANES = 3
)
(
input clk,
input rst,
input pi_fine_dly_dec_done,
input cmd_delay_start,
// Control lane being shifted using Phaser_Out fine delay taps
output reg [DQS_CNT_WIDTH:0] ctl_lane_cnt,
// Inc/dec Phaser_Out fine delay line
output reg po_s2_incdec_f,
output reg po_en_s2_f,
// Inc/dec Phaser_Out coarse delay line
output reg po_s2_incdec_c,
output reg po_en_s2_c,
// Completed adjusting delays for dq, dqs for tdqss
output po_ck_addr_cmd_delay_done,
// completed decrementing initialPO delays
output po_dec_done,
output phy_ctl_rdy_dly
);
localparam TAP_LIMIT = 63;
// PO fine delay tap resolution change by frequency. tCK > 2500, need
// twice the amount of taps
// localparam D_DLY_F = (tCK > 2500 ) ? D_DLY * 2 : D_DLY;
// coarse delay tap is added DQ/DQS to meet the TDQSS specification.
localparam TDQSS_DLY = (tCK > 2500 )? 2: 1;
reg delay_done;
reg delay_done_r1;
reg delay_done_r2;
reg delay_done_r3;
reg delay_done_r4;
reg [5:0] po_delay_cnt_r;
reg po_cnt_inc;
reg cmd_delay_start_r1;
reg cmd_delay_start_r2;
reg cmd_delay_start_r3;
reg cmd_delay_start_r4;
reg cmd_delay_start_r5;
reg cmd_delay_start_r6;
reg po_delay_done;
reg po_delay_done_r1;
reg po_delay_done_r2;
reg po_delay_done_r3;
reg po_delay_done_r4;
reg pi_fine_dly_dec_done_r;
reg po_en_stg2_c;
reg po_en_stg2_f;
reg po_stg2_incdec_c;
reg po_stg2_f_incdec;
reg [DQS_CNT_WIDTH:0] lane_cnt_dqs_c_r;
reg [DQS_CNT_WIDTH:0] lane_cnt_po_r;
reg [5:0] delay_cnt_r;
always @(posedge clk) begin
cmd_delay_start_r1 <= #TCQ cmd_delay_start;
cmd_delay_start_r2 <= #TCQ cmd_delay_start_r1;
cmd_delay_start_r3 <= #TCQ cmd_delay_start_r2;
cmd_delay_start_r4 <= #TCQ cmd_delay_start_r3;
cmd_delay_start_r5 <= #TCQ cmd_delay_start_r4;
cmd_delay_start_r6 <= #TCQ cmd_delay_start_r5;
pi_fine_dly_dec_done_r <= #TCQ pi_fine_dly_dec_done;
end
assign phy_ctl_rdy_dly = cmd_delay_start_r6;
// logic for decrementing initial fine delay taps for all PO
// Decrement done for add, ctrl and data phaser outs
assign po_dec_done = (PO_INITIAL_DLY == 0) ? 1 : po_delay_done_r4;
always @(posedge clk)
if (rst || ~cmd_delay_start_r6 || po_delay_done) begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b0;
end else if (po_delay_cnt_r > 6'd0) begin
po_en_stg2_f <= #TCQ ~po_en_stg2_f;
end
always @(posedge clk)
if (rst || ~cmd_delay_start_r6 || (po_delay_cnt_r == 6'd0))
// set all the PO delays to 31. Decrement from 46 to 31.
// Requirement comes from dqs_found logic
po_delay_cnt_r <= #TCQ (PO_INITIAL_DLY - 31);
else if ( po_en_stg2_f && (po_delay_cnt_r > 6'd0))
po_delay_cnt_r <= #TCQ po_delay_cnt_r - 1;
always @(posedge clk)
if (rst)
lane_cnt_po_r <= #TCQ 'd0;
else if ( po_en_stg2_f && (po_delay_cnt_r == 6'd1))
lane_cnt_po_r <= #TCQ lane_cnt_po_r + 1;
always @(posedge clk)
if (rst || ~cmd_delay_start_r6 )
po_delay_done <= #TCQ 1'b0;
else if ((po_delay_cnt_r == 6'd1) && (lane_cnt_po_r ==1'b0))
po_delay_done <= #TCQ 1'b1;
always @(posedge clk) begin
po_delay_done_r1 <= #TCQ po_delay_done;
po_delay_done_r2 <= #TCQ po_delay_done_r1;
po_delay_done_r3 <= #TCQ po_delay_done_r2;
po_delay_done_r4 <= #TCQ po_delay_done_r3;
end
// logic to select between all PO delays and data path delay.
always @(posedge clk) begin
po_s2_incdec_f <= #TCQ po_stg2_f_incdec;
po_en_s2_f <= #TCQ po_en_stg2_f;
end
// Logic to add 1/4 taps amount of delay to data path for tdqss.
// After all the initial PO delays are decremented the 1/4 delay will
// be added. Coarse delay taps will be added here .
// Delay added only to data path
assign po_ck_addr_cmd_delay_done = (TDQSS_DLY == 0) ? pi_fine_dly_dec_done_r
: delay_done_r4;
always @(posedge clk)
if (rst || ~pi_fine_dly_dec_done_r || delay_done) begin
po_stg2_incdec_c <= #TCQ 1'b1;
po_en_stg2_c <= #TCQ 1'b0;
end else if (delay_cnt_r > 6'd0) begin
po_en_stg2_c <= #TCQ ~po_en_stg2_c;
end
always @(posedge clk)
if (rst || ~pi_fine_dly_dec_done_r || (delay_cnt_r == 6'd0))
delay_cnt_r <= #TCQ TDQSS_DLY;
else if ( po_en_stg2_c && (delay_cnt_r > 6'd0))
delay_cnt_r <= #TCQ delay_cnt_r - 1;
always @(posedge clk)
if (rst)
lane_cnt_dqs_c_r <= #TCQ 'd0;
else if ( po_en_stg2_c && (delay_cnt_r == 6'd1))
lane_cnt_dqs_c_r <= #TCQ lane_cnt_dqs_c_r + 1;
always @(posedge clk)
if (rst || ~pi_fine_dly_dec_done_r)
delay_done <= #TCQ 1'b0;
else if ((delay_cnt_r == 6'd1) && (lane_cnt_dqs_c_r == 1'b0))
delay_done <= #TCQ 1'b1;
always @(posedge clk) begin
delay_done_r1 <= #TCQ delay_done;
delay_done_r2 <= #TCQ delay_done_r1;
delay_done_r3 <= #TCQ delay_done_r2;
delay_done_r4 <= #TCQ delay_done_r3;
end
always @(posedge clk) begin
po_s2_incdec_c <= #TCQ po_stg2_incdec_c;
po_en_s2_c <= #TCQ po_en_stg2_c;
ctl_lane_cnt <= #TCQ lane_cnt_dqs_c_r;
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.4.1 (win64) Build 2117270 Tue Jan 30 15:32:00 MST 2018
// Date : Wed Apr 4 23:01:45 2018
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_1_sim_netlist.v
// Design : design_1_processing_system7_0_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg400-3
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "design_1_processing_system7_0_1,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.4.1" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(GPIO_I,
GPIO_O,
GPIO_T,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_I" *) input [63:0]GPIO_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_O" *) output [63:0]GPIO_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_T" *) output [63:0]GPIO_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_1_FCLK_CLK0" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 49999947, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_1_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_1_FCLK_CLK0" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB0_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB0_PORT_INDCTL_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *)
(* C_GP1_EN_MODIFIABLE_TXN = "1" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg400" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "design_1_processing_system7_0_1.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={867} load={0.5} /><MEMORY name={code} memType={LPDDR2} dataWidth={32} clockFreq={400} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={26} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS18} bidis={5} ioBank={Vcco_p1} clockFreq={166.666489} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={49.999947} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p0} clockFreq={99.999893} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={99.999893} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1733.332} /><PLL domain={Memory} vco={1599.998} /><PLL domain={IO} vco={1999.998} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={49} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I(GPIO_I),
.GPIO_O(GPIO_O),
.GPIO_T(GPIO_T),
.I2C0_SCL_I(1'b0),
.I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
.I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
.I2C0_SDA_I(1'b0),
.I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
.I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(1'b0),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(1'b0),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED),
.TTC0_WAVE1_OUT(NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED),
.TTC0_WAVE2_OUT(NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(NLW_inst_USB0_PORT_INDCTL_UNCONNECTED[1:0]),
.USB0_VBUS_PWRFAULT(1'b0),
.USB0_VBUS_PWRSELECT(NLW_inst_USB0_VBUS_PWRSELECT_UNCONNECTED),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg400" *) (* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "design_1_processing_system7_0_1.hwdef" *) (* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={867} load={0.5} /><MEMORY name={code} memType={LPDDR2} dataWidth={32} clockFreq={400} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={26} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS18} bidis={5} ioBank={Vcco_p1} clockFreq={166.666489} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={49.999947} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p0} clockFreq={99.999893} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={99.999893} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1733.332} /><PLL domain={Memory} vco={1599.998} /><PLL domain={IO} vco={1999.998} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={49} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire \<const1> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [0:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]\^M_AXI_GP0_ARCACHE ;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]\^M_AXI_GP0_AWCACHE ;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]\^M_AXI_GP1_ARCACHE ;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]\^M_AXI_GP1_AWCACHE ;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2];
assign M_AXI_GP0_ARCACHE[1] = \<const1> ;
assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0];
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2];
assign M_AXI_GP0_AWCACHE[1] = \<const1> ;
assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2];
assign M_AXI_GP1_ARCACHE[1] = \<const1> ;
assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2];
assign M_AXI_GP1_AWCACHE[1] = \<const1> ;
assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
VCC VCC
(.P(\<const1> ));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_V
/**
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__clkdlybuf4s50 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_V |
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream rate limiter
*/
module axis_rate_limit #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Configuration
*/
input wire [7:0] rate_num,
input wire [7:0] rate_denom,
input wire rate_by_frame
);
// internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int = 0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
reg [23:0] acc_reg = 0, acc_next;
reg pause;
reg frame_reg = 0, frame_next;
reg input_axis_tready_reg = 0, input_axis_tready_next;
assign input_axis_tready = input_axis_tready_reg;
always @* begin
acc_next = acc_reg;
pause = 0;
frame_next = frame_reg & ~input_axis_tlast;
if (acc_reg >= rate_num) begin
acc_next = acc_reg - rate_num;
end
if (input_axis_tready & input_axis_tvalid) begin
// read input
frame_next = ~input_axis_tlast;
acc_next = acc_reg + (rate_denom - rate_num);
end
if (acc_next >= rate_num) begin
if (rate_by_frame) begin
pause = ~frame_next;
end else begin
pause = 1;
end
end
input_axis_tready_next = output_axis_tready_int_early & ~pause;
output_axis_tdata_int = input_axis_tdata;
output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
acc_reg <= 0;
frame_reg <= 0;
input_axis_tready_reg <= 0;
end else begin
acc_reg <= acc_next;
frame_reg <= frame_next;
input_axis_tready_reg <= input_axis_tready_next;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
reg output_axis_tvalid_reg = 0;
reg output_axis_tlast_reg = 0;
reg output_axis_tuser_reg = 0;
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = 0;
reg temp_axis_tvalid_reg = 0;
reg temp_axis_tlast_reg = 0;
reg temp_axis_tuser_reg = 0;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & ~output_axis_tvalid_reg) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
always @(posedge clk or posedge rst) begin
if (rst) begin
output_axis_tdata_reg <= 0;
output_axis_tvalid_reg <= 0;
output_axis_tlast_reg <= 0;
output_axis_tuser_reg <= 0;
output_axis_tready_int <= 0;
temp_axis_tdata_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
output_axis_tready_int <= output_axis_tready_int_early;
if (output_axis_tready_int) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tvalid_reg <= output_axis_tvalid_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else begin
// output is not ready, store input in temp
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tvalid_reg <= output_axis_tvalid_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end else if (output_axis_tready) begin
// input is not ready, but output is ready
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tvalid_reg <= temp_axis_tvalid_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
temp_axis_tdata_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:40:47 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire n1654, Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP,
ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1,
left_right_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2,
SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM,
SIGN_FLAG_SFG, OP_FLAG_SFG, ZERO_FLAG_SFG,
inst_FSM_INPUT_ENABLE_state_next_1_, n463, n464, n465, n466, n467,
n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, n478,
n479, n480, n481, n482, n483, n484, n485, n486, n487, n488, n489,
n490, n491, n492, n493, n494, n495, n496, n497, n498, n499, n500,
n501, n502, n503, n504, n505, n506, n507, n508, n509, n510, n511,
n512, n513, n514, n515, n516, n517, n518, n519, n520, n521, n522,
n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, n533,
n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544,
n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555,
n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566,
n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577,
n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588,
n589, n590, n591, n592, n593, n594, n595, n596, n597, n598, n599,
n600, n601, n602, n603, n604, n605, n606, n607, n608, n609, n610,
n611, n612, n613, n614, n615, n616, n617, n618, n619, n620, n621,
n622, n623, n624, n625, n626, n627, n628, n629, n630, n631, n632,
n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, n643,
n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, n654,
n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665,
n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676,
n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698,
n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720,
n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, n731,
n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742,
n743, n744, n745, n746, n747, n748, n749, n750, n751, n752, n753,
n754, n755, n756, n757, n758, n759, n760, n761, n762, n763, n764,
n765, n766, n767, n769, n770, n771, n772, n773, n774, n775, n776,
n777, n778, n779, n780, n781, n782, n783, n784, n785, n786, n787,
n788, n789, n790, n791, n792, n793, n794, n795, n796, n797, n798,
n799, n800, n801, n802, n803, n804, n805, n806, n807, n808, n809,
n810, n811, n812, n813, n814, n815, n816, n817, n818, n819, n820,
n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831,
n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, n842,
n843, n844, n845, n846, n847, n848, n849, n850, n851, n852, n853,
n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, n864,
n866, n867, n868, n869, n870, n871, DP_OP_15J49_123_3372_n8,
DP_OP_15J49_123_3372_n7, DP_OP_15J49_123_3372_n6,
DP_OP_15J49_123_3372_n5, DP_OP_15J49_123_3372_n4, intadd_51_B_12_,
intadd_51_B_11_, intadd_51_B_10_, intadd_51_B_9_, intadd_51_B_8_,
intadd_51_B_7_, intadd_51_B_6_, intadd_51_B_5_, intadd_51_B_4_,
intadd_51_B_3_, intadd_51_B_2_, intadd_51_B_1_, intadd_51_B_0_,
intadd_51_CI, intadd_51_SUM_12_, intadd_51_SUM_11_, intadd_51_SUM_10_,
intadd_51_SUM_9_, intadd_51_SUM_8_, intadd_51_SUM_7_,
intadd_51_SUM_6_, intadd_51_SUM_5_, intadd_51_SUM_4_,
intadd_51_SUM_3_, intadd_51_SUM_2_, intadd_51_SUM_1_,
intadd_51_SUM_0_, intadd_51_n13, intadd_51_n12, intadd_51_n11,
intadd_51_n10, intadd_51_n9, intadd_51_n8, intadd_51_n7, intadd_51_n6,
intadd_51_n5, intadd_51_n4, intadd_51_n3, intadd_51_n2, intadd_51_n1,
intadd_52_A_2_, intadd_52_A_1_, intadd_52_B_2_, intadd_52_B_1_,
intadd_52_B_0_, intadd_52_CI, intadd_52_SUM_2_, intadd_52_SUM_1_,
intadd_52_SUM_0_, intadd_52_n3, intadd_52_n2, intadd_52_n1,
intadd_53_A_2_, intadd_53_A_1_, intadd_53_B_1_, intadd_53_B_0_,
intadd_53_CI, intadd_53_SUM_2_, intadd_53_SUM_1_, intadd_53_SUM_0_,
intadd_53_n3, intadd_53_n2, intadd_53_n1, n872, n873, n874, n875,
n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886,
n887, n888, n889, n890, n891, n892, n893, n894, n895, n896, n897,
n898, n899, n900, n901, n902, n903, n904, n905, n906, n907, n908,
n909, n910, n911, n912, n913, n914, n915, n916, n917, n918, n919,
n920, n921, n922, n923, n924, n925, n926, n927, n928, n929, n930,
n931, n932, n933, n934, n935, n936, n937, n938, n939, n940, n941,
n942, n943, n944, n945, n946, n947, n948, n949, n950, n951, n952,
n953, n954, n955, n956, n957, n958, n959, n960, n961, n962, n963,
n964, n965, n966, n967, n968, n969, n970, n971, n972, n973, n974,
n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, n985,
n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, n996,
n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006,
n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016,
n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026,
n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036,
n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046,
n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056,
n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066,
n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076,
n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086,
n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096,
n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106,
n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116,
n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126,
n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136,
n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146,
n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156,
n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166,
n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176,
n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186,
n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196,
n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206,
n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216,
n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226,
n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236,
n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246,
n1247, n1248, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1382, n1383, n1384, n1385, n1386, n1387, n1389,
n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399,
n1400, n1401, n1402, n1403, n1405, n1406, n1407, n1408, n1409, n1410,
n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420,
n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430,
n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440,
n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450,
n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460,
n1461, n1462, n1463, n1464, n1465, n1466, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1508, n1509, n1510, n1512, n1513,
n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523,
n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533,
n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543,
n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553,
n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563,
n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573,
n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583,
n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593,
n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603,
n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613,
n1614, n1615, n1616, n1618, n1619, n1620, n1621, n1622, n1623, n1624,
n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634,
n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644,
n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1653;
wire [1:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:2] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [25:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n866), .CK(clk), .RN(n1621), .QN(
n893) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n830), .CK(clk), .RN(n1619), .Q(
intAS) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n765), .CK(clk), .RN(n1620),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n764), .CK(clk), .RN(n1643),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n763), .CK(clk), .RN(n1622),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n762), .CK(clk), .RN(n1634),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n753), .CK(clk), .RN(n1642), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n752), .CK(clk), .RN(n1626), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n751), .CK(clk), .RN(n1644), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n750), .CK(clk), .RN(n1625), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n749), .CK(clk), .RN(n1649), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n748), .CK(clk), .RN(n1626), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n747), .CK(clk), .RN(n1636), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n746), .CK(clk), .RN(n1644), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n745), .CK(clk), .RN(n1623), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n744), .CK(clk), .RN(n1633), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n743), .CK(clk), .RN(n1635), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n742), .CK(clk), .RN(n1637), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n741), .CK(clk), .RN(n1626), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n740), .CK(clk), .RN(n1639), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n739), .CK(clk), .RN(n1623), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n738), .CK(clk), .RN(n1640), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n737), .CK(clk), .RN(n1649), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n736), .CK(clk), .RN(n1642), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n735), .CK(clk), .RN(n1648), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n734), .CK(clk), .RN(n1633), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n733), .CK(clk), .RN(n1635), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n732), .CK(clk), .RN(n918), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n731), .CK(clk), .RN(n1627), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n726), .CK(clk), .RN(n1628), .QN(n899)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n725), .CK(clk), .RN(n1631), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n724), .CK(clk), .RN(n1630), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n723), .CK(clk), .RN(n1629), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n970), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n721), .CK(clk), .RN(n1632), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n720), .CK(clk), .RN(n970), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n719), .CK(clk), .RN(n1632), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n718), .CK(clk), .RN(n918), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n716), .CK(clk), .RN(n1627), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n715), .CK(clk), .RN(n1628), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n713), .CK(clk), .RN(n1631), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n712), .CK(clk), .RN(n1630), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n711), .CK(clk), .RN(n1632), .Q(
DMP_SFG[2]), .QN(n1600) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n710), .CK(clk), .RN(n1629), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n709), .CK(clk), .RN(n970), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n708), .CK(clk), .RN(n1627), .Q(
DMP_SFG[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n1628), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n706), .CK(clk), .RN(n1631), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n705), .CK(clk), .RN(n1630), .Q(
DMP_SFG[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n704), .CK(clk), .RN(n1629), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n703), .CK(clk), .RN(n1632), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n701), .CK(clk), .RN(n1627), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n700), .CK(clk), .RN(n1628), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n699), .CK(clk), .RN(n1629), .Q(
DMP_SFG[6]), .QN(n1601) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n698), .CK(clk), .RN(n1631), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n697), .CK(clk), .RN(n1630), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_7_ ( .D(n696), .CK(clk), .RN(n1632), .Q(
DMP_SFG[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n695), .CK(clk), .RN(n918), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n694), .CK(clk), .RN(n1627), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_8_ ( .D(n693), .CK(clk), .RN(n1628), .Q(
DMP_SFG[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n692), .CK(clk), .RN(n1631), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n691), .CK(clk), .RN(n1630), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n689), .CK(clk), .RN(n1629), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n688), .CK(clk), .RN(n970), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n687), .CK(clk), .RN(n1627), .Q(
DMP_SFG[10]), .QN(n1556) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n686), .CK(clk), .RN(n1632), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n685), .CK(clk), .RN(n918), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n684), .CK(clk), .RN(n1628), .Q(
DMP_SFG[11]), .QN(n1555) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n683), .CK(clk), .RN(n1628), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n682), .CK(clk), .RN(n1631), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n681), .CK(clk), .RN(n1630), .Q(
DMP_SFG[12]), .QN(n1562) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n680), .CK(clk), .RN(n1630), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n679), .CK(clk), .RN(n1629), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n678), .CK(clk), .RN(n1631), .Q(
DMP_SFG[13]), .QN(n1561) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n677), .CK(clk), .RN(n970), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n676), .CK(clk), .RN(n1632), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n675), .CK(clk), .RN(n1629), .Q(
DMP_SFG[14]), .QN(n1565) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n674), .CK(clk), .RN(n918), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n673), .CK(clk), .RN(n1627), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n672), .CK(clk), .RN(n1631), .Q(
DMP_SFG[15]), .QN(n1583) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n671), .CK(clk), .RN(n1627), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n670), .CK(clk), .RN(n1628), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n669), .CK(clk), .RN(n1629), .Q(
DMP_SFG[16]), .QN(n1582) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n668), .CK(clk), .RN(n1631), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n667), .CK(clk), .RN(n1630), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n666), .CK(clk), .RN(n1630), .Q(
DMP_SFG[17]), .QN(n1595) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n665), .CK(clk), .RN(n1629), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n664), .CK(clk), .RN(n1632), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n663), .CK(clk), .RN(n1632), .Q(
DMP_SFG[18]), .QN(n1594) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n662), .CK(clk), .RN(n1627), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n661), .CK(clk), .RN(n1628), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n660), .CK(clk), .RN(n1623), .Q(
DMP_SFG[19]), .QN(n1604) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n659), .CK(clk), .RN(n1633), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n658), .CK(clk), .RN(n1635), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n657), .CK(clk), .RN(n1649), .Q(
DMP_SFG[20]), .QN(n1603) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n656), .CK(clk), .RN(n1637), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n655), .CK(clk), .RN(n1626), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n654), .CK(clk), .RN(n1642), .Q(
DMP_SFG[21]), .QN(n1615) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n653), .CK(clk), .RN(n1622), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n652), .CK(clk), .RN(n1639), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n651), .CK(clk), .RN(n1639), .Q(
DMP_SFG[22]), .QN(n1614) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n650), .CK(clk), .RN(n1623), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n1640), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n648), .CK(clk), .RN(n1647), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n647), .CK(clk), .RN(n1645), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n645), .CK(clk), .RN(n1646), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n644), .CK(clk), .RN(n1644), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n643), .CK(clk), .RN(n1634), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n642), .CK(clk), .RN(n1636), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n640), .CK(clk), .RN(n1638), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n639), .CK(clk), .RN(n1625), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n638), .CK(clk), .RN(n1643), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n637), .CK(clk), .RN(n1641), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n635), .CK(clk), .RN(n1618), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n634), .CK(clk), .RN(n1647), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n633), .CK(clk), .RN(n1648), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n632), .CK(clk), .RN(n1622), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n630), .CK(clk), .RN(n1633), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n629), .CK(clk), .RN(n1635), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n628), .CK(clk), .RN(n1637), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n627), .CK(clk), .RN(n1626), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n625), .CK(clk), .RN(n1639), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n624), .CK(clk), .RN(n1623), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n623), .CK(clk), .RN(n1640), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n622), .CK(clk), .RN(n1649), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n620), .CK(clk), .RN(n1642), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n619), .CK(clk), .RN(n1648), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n618), .CK(clk), .RN(n1644), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n617), .CK(clk), .RN(n1634), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n615), .CK(clk), .RN(n1636), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n614), .CK(clk), .RN(n1638), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n613), .CK(clk), .RN(n1625), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n612), .CK(clk), .RN(n1643), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n610), .CK(clk), .RN(n1641), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n609), .CK(clk), .RN(n1625), .QN(
n894) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n608), .CK(clk), .RN(n1643), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n607), .CK(clk), .RN(n1641), .QN(
n895) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n606), .CK(clk), .RN(n1618), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n604), .CK(clk), .RN(n1637), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n603), .CK(clk), .RN(n1626), .QN(
n897) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n602), .CK(clk), .RN(n1622), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n601), .CK(clk), .RN(n1639), .QN(
n883) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n600), .CK(clk), .RN(n1623), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n599), .CK(clk), .RN(n1640), .QN(
n896) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n598), .CK(clk), .RN(n1639), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n597), .CK(clk), .RN(n1623), .QN(
n881) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n596), .CK(clk), .RN(n1640), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n595), .CK(clk), .RN(n1649), .QN(
n898) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n594), .CK(clk), .RN(n1642), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n592), .CK(clk), .RN(n1644), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n591), .CK(clk), .RN(n1634), .QN(
n892) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n590), .CK(clk), .RN(n1636), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n588), .CK(clk), .RN(n1638), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n587), .CK(clk), .RN(n1625),
.QN(n882) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n586), .CK(clk), .RN(n1643), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n585), .CK(clk), .RN(n1641),
.QN(n900) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n584), .CK(clk), .RN(n1618), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n583), .CK(clk), .RN(n1647),
.QN(n879) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n582), .CK(clk), .RN(n1645), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n581), .CK(clk), .RN(n1646),
.QN(n901) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n580), .CK(clk), .RN(n1637), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n578), .CK(clk), .RN(n1646), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n576), .CK(clk), .RN(n1638), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n574), .CK(clk), .RN(n1635), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n572), .CK(clk), .RN(n1625), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n570), .CK(clk), .RN(n1640), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n568), .CK(clk), .RN(n1633), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n566), .CK(clk), .RN(n1634), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n557), .CK(clk), .RN(n1641), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n556), .CK(clk), .RN(n1633), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n555), .CK(clk), .RN(n1642), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n554), .CK(clk), .RN(n1639), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n553), .CK(clk), .RN(n1618), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n551), .CK(clk), .RN(n1641), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n550), .CK(clk), .RN(n1648), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n548), .CK(clk), .RN(n1639), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n547), .CK(clk), .RN(n1643), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n546), .CK(clk), .RN(n1634), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n545), .CK(clk), .RN(n1640), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n544), .CK(clk), .RN(n1622), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n516), .CK(clk), .RN(n1622), .Q(
LZD_output_NRM2_EW[3]), .QN(n1566) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n515), .CK(clk), .RN(n1640), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n514), .CK(clk), .RN(n1626), .Q(
LZD_output_NRM2_EW[2]), .QN(n1563) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n513), .CK(clk), .RN(n1635), .Q(
LZD_output_NRM2_EW[1]), .QN(n1557) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n512), .CK(clk), .RN(n1637), .Q(
LZD_output_NRM2_EW[4]), .QN(n1567) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n488), .CK(clk), .RN(n1638), .Q(
DmP_mant_SFG_SWR[0]), .QN(n958) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n487), .CK(clk), .RN(n1625), .Q(
DmP_mant_SFG_SWR[1]), .QN(n959) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n486), .CK(clk), .RN(n1643), .Q(
DmP_mant_SFG_SWR[2]), .QN(n960) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n485), .CK(clk), .RN(n1641), .Q(
DmP_mant_SFG_SWR[3]), .QN(n961) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n484), .CK(clk), .RN(n1618), .Q(
DmP_mant_SFG_SWR[4]), .QN(n962) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n482), .CK(clk), .RN(n1625), .Q(
DmP_mant_SFG_SWR[6]), .QN(n967) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n481), .CK(clk), .RN(n1643), .Q(
DmP_mant_SFG_SWR[7]), .QN(n965) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n480), .CK(clk), .RN(n1641), .Q(
DmP_mant_SFG_SWR[8]), .QN(n964) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n472), .CK(clk), .RN(n1641), .Q(
DmP_mant_SFG_SWR[16]), .QN(n950) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n471), .CK(clk), .RN(n1645), .Q(
DmP_mant_SFG_SWR[17]), .QN(n951) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n470), .CK(clk), .RN(n1646), .Q(
DmP_mant_SFG_SWR[18]), .QN(n952) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n469), .CK(clk), .RN(n1644), .Q(
DmP_mant_SFG_SWR[19]), .QN(n953) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n468), .CK(clk), .RN(n1634), .Q(
DmP_mant_SFG_SWR[20]), .QN(n954) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n467), .CK(clk), .RN(n1636), .Q(
DmP_mant_SFG_SWR[21]), .QN(n955) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n466), .CK(clk), .RN(n1638), .Q(
DmP_mant_SFG_SWR[22]), .QN(n956) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n465), .CK(clk), .RN(n1642), .Q(
DmP_mant_SFG_SWR[23]), .QN(n1599) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n464), .CK(clk), .RN(n1649), .Q(
DmP_mant_SFG_SWR[24]), .QN(n1612) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n463), .CK(clk), .RN(n1648), .Q(
DmP_mant_SFG_SWR[25]), .QN(n1616) );
CMPR32X2TS intadd_51_U14 ( .A(n1556), .B(intadd_51_B_0_), .C(intadd_51_CI),
.CO(intadd_51_n13), .S(intadd_51_SUM_0_) );
CMPR32X2TS intadd_51_U13 ( .A(n1555), .B(intadd_51_B_1_), .C(intadd_51_n13),
.CO(intadd_51_n12), .S(intadd_51_SUM_1_) );
CMPR32X2TS intadd_51_U12 ( .A(n1562), .B(intadd_51_B_2_), .C(intadd_51_n12),
.CO(intadd_51_n11), .S(intadd_51_SUM_2_) );
CMPR32X2TS intadd_51_U11 ( .A(n1561), .B(intadd_51_B_3_), .C(intadd_51_n11),
.CO(intadd_51_n10), .S(intadd_51_SUM_3_) );
CMPR32X2TS intadd_51_U10 ( .A(n1565), .B(intadd_51_B_4_), .C(intadd_51_n10),
.CO(intadd_51_n9), .S(intadd_51_SUM_4_) );
CMPR32X2TS intadd_51_U9 ( .A(n1583), .B(intadd_51_B_5_), .C(intadd_51_n9),
.CO(intadd_51_n8), .S(intadd_51_SUM_5_) );
CMPR32X2TS intadd_51_U8 ( .A(n1582), .B(intadd_51_B_6_), .C(intadd_51_n8),
.CO(intadd_51_n7), .S(intadd_51_SUM_6_) );
CMPR32X2TS intadd_51_U7 ( .A(n1595), .B(intadd_51_B_7_), .C(intadd_51_n7),
.CO(intadd_51_n6), .S(intadd_51_SUM_7_) );
CMPR32X2TS intadd_51_U6 ( .A(n1594), .B(intadd_51_B_8_), .C(intadd_51_n6),
.CO(intadd_51_n5), .S(intadd_51_SUM_8_) );
CMPR32X2TS intadd_51_U5 ( .A(n1604), .B(intadd_51_B_9_), .C(intadd_51_n5),
.CO(intadd_51_n4), .S(intadd_51_SUM_9_) );
CMPR32X2TS intadd_51_U4 ( .A(n1603), .B(intadd_51_B_10_), .C(intadd_51_n4),
.CO(intadd_51_n3), .S(intadd_51_SUM_10_) );
CMPR32X2TS intadd_51_U3 ( .A(n1615), .B(intadd_51_B_11_), .C(intadd_51_n3),
.CO(intadd_51_n2), .S(intadd_51_SUM_11_) );
CMPR32X2TS intadd_51_U2 ( .A(n1614), .B(intadd_51_B_12_), .C(intadd_51_n2),
.CO(intadd_51_n1), .S(intadd_51_SUM_12_) );
CMPR32X2TS intadd_52_U4 ( .A(n1601), .B(intadd_52_B_0_), .C(intadd_52_CI),
.CO(intadd_52_n3), .S(intadd_52_SUM_0_) );
CMPR32X2TS intadd_52_U3 ( .A(intadd_52_A_1_), .B(intadd_52_B_1_), .C(
intadd_52_n3), .CO(intadd_52_n2), .S(intadd_52_SUM_1_) );
CMPR32X2TS intadd_52_U2 ( .A(intadd_52_A_2_), .B(intadd_52_B_2_), .C(
intadd_52_n2), .CO(intadd_52_n1), .S(intadd_52_SUM_2_) );
CMPR32X2TS intadd_53_U4 ( .A(n1600), .B(intadd_53_B_0_), .C(intadd_53_CI),
.CO(intadd_53_n3), .S(intadd_53_SUM_0_) );
CMPR32X2TS intadd_53_U3 ( .A(intadd_53_A_1_), .B(intadd_53_B_1_), .C(
intadd_53_n3), .CO(intadd_53_n2), .S(intadd_53_SUM_1_) );
CMPR32X2TS intadd_53_U2 ( .A(intadd_53_A_2_), .B(n923), .C(intadd_53_n2),
.CO(intadd_53_n1), .S(intadd_53_SUM_2_) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n781), .CK(clk), .RN(n1633), .Q(
Data_array_SWR[10]), .QN(n1611) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n562), .CK(clk), .RN(n1635), .Q(
DmP_EXP_EWSW[25]), .QN(n1610) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n727), .CK(clk), .RN(n970), .Q(
DMP_EXP_EWSW[26]), .QN(n1609) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n561), .CK(clk), .RN(n1625), .Q(
DmP_EXP_EWSW[26]), .QN(n1605) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n611), .CK(clk), .RN(n971), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1602) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n728), .CK(clk), .RN(n1629), .Q(
DMP_EXP_EWSW[25]), .QN(n1597) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n541), .CK(clk), .RN(n1626), .Q(
Raw_mant_NRM_SWR[1]), .QN(n1596) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n828), .CK(clk), .RN(n1621), .Q(
intDY_EWSW[0]), .QN(n1585) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n621), .CK(clk), .RN(n1649), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1581) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n616), .CK(clk), .RN(n972), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1580) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n801), .CK(clk), .RN(n1624),
.Q(intDY_EWSW[27]), .QN(n1579) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n805), .CK(clk), .RN(n1622),
.Q(intDY_EWSW[23]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n800), .CK(clk), .RN(n1621),
.Q(intDY_EWSW[28]), .QN(n1578) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n821), .CK(clk), .RN(n1624), .Q(
intDY_EWSW[7]), .QN(n1577) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n824), .CK(clk), .RN(n1619), .Q(
intDY_EWSW[4]), .QN(n1574) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n826), .CK(clk), .RN(n1647), .Q(
intDY_EWSW[2]), .QN(n1573) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n819), .CK(clk), .RN(n1620), .Q(
intDY_EWSW[9]), .QN(n1570) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n822), .CK(clk), .RN(n1618), .Q(
intDY_EWSW[6]), .QN(n1569) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n870), .CK(clk), .RN(
n1620), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1564) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n834), .CK(clk), .RN(n1648),
.Q(intDX_EWSW[28]), .QN(n1559) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n646), .CK(clk), .RN(n1642), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1554) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n537), .CK(clk), .RN(n1645), .Q(
Raw_mant_NRM_SWR[5]), .QN(n1552) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n540), .CK(clk), .RN(n1648), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1551) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n521), .CK(clk), .RN(n1646), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1548) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n769), .CK(clk), .RN(n1642), .Q(
shift_value_SHT2_EWR[3]), .QN(n1547) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n525), .CK(clk), .RN(n1637), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1546) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n520), .CK(clk), .RN(n1645), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1545) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n836), .CK(clk), .RN(n1619),
.Q(intDX_EWSW[26]), .QN(n1544) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n533), .CK(clk), .RN(n1633), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1542) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n536), .CK(clk), .RN(n1626), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1541) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n529), .CK(clk), .RN(n1647), .Q(
Raw_mant_NRM_SWR[13]), .QN(n1540) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n729), .CK(clk), .RN(n1630), .Q(
DMP_EXP_EWSW[24]), .QN(n1539) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n563), .CK(clk), .RN(n1636), .Q(
DmP_EXP_EWSW[24]), .QN(n1538) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n809), .CK(clk), .RN(n1643),
.Q(intDY_EWSW[19]), .QN(n1536) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n812), .CK(clk), .RN(n1620),
.Q(intDY_EWSW[16]), .QN(n1534) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n823), .CK(clk), .RN(n1621), .Q(
intDY_EWSW[5]), .QN(n1532) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n534), .CK(clk), .RN(n1636), .Q(
Raw_mant_NRM_SWR[8]), .QN(n1530) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n542), .CK(clk), .RN(n1634), .Q(
Raw_mant_NRM_SWR[0]), .QN(n1529) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n535), .CK(clk), .RN(n1639), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1527) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n532), .CK(clk), .RN(n1644), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1525) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n528), .CK(clk), .RN(n1635), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1523) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n527), .CK(clk), .RN(n1642), .Q(
Raw_mant_NRM_SWR[15]), .QN(n1522) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n804), .CK(clk), .RN(n917), .Q(
intDY_EWSW[24]), .QN(n1519) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n526), .CK(clk), .RN(n1643), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1517) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n519), .CK(clk), .RN(n1637), .Q(
Raw_mant_NRM_SWR[23]), .QN(n1515) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1620),
.Q(ready) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n559), .CK(clk), .RN(n1636), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n552), .CK(clk), .RN(n1647), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n505), .CK(clk), .RN(n1645), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n504), .CK(clk), .RN(n1639), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n503), .CK(clk), .RN(n1635), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n502), .CK(clk), .RN(n1645), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n501), .CK(clk), .RN(n1644), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n500), .CK(clk), .RN(n1634), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n499), .CK(clk), .RN(n1636), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n498), .CK(clk), .RN(n1638), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n497), .CK(clk), .RN(n1625), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n496), .CK(clk), .RN(n1643), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n495), .CK(clk), .RN(n1641), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n494), .CK(clk), .RN(n1618), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n493), .CK(clk), .RN(n1647), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n492), .CK(clk), .RN(n1645), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n491), .CK(clk), .RN(n1646), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n490), .CK(clk), .RN(n1644), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n489), .CK(clk), .RN(n1646), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n558), .CK(clk), .RN(n1648), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n510), .CK(clk), .RN(n1636), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n509), .CK(clk), .RN(n1623), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n508), .CK(clk), .RN(n1637), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n507), .CK(clk), .RN(n1638), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n506), .CK(clk), .RN(n1646), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n761), .CK(clk), .RN(n1633), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n760), .CK(clk), .RN(n1633), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n759), .CK(clk), .RN(n1635), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n758), .CK(clk), .RN(n1637), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n757), .CK(clk), .RN(n1626), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n756), .CK(clk), .RN(n1622), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n755), .CK(clk), .RN(n1639), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n511), .CK(clk), .RN(n1640), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n754), .CK(clk), .RN(n1623), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n543), .CK(clk), .RN(n1640), .Q(
final_result_ieee[31]) );
DFFSX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n880), .CK(clk), .SN(n972), .Q(
n1651), .QN(n1650) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1620), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1531) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n539), .CK(clk), .RN(n1625), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1593) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n531), .CK(clk), .RN(n1649), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1518) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n820), .CK(clk), .RN(n1621), .Q(
intDY_EWSW[8]), .QN(n1589) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n806), .CK(clk), .RN(n1621),
.Q(intDY_EWSW[22]), .QN(n1535) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n798), .CK(clk), .RN(n1634),
.Q(intDY_EWSW[30]), .QN(n1591) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n799), .CK(clk), .RN(n1639),
.Q(intDY_EWSW[29]), .QN(n1537) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n802), .CK(clk), .RN(n1625),
.Q(intDY_EWSW[26]), .QN(n1590) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n803), .CK(clk), .RN(n1642),
.Q(intDY_EWSW[25]), .QN(n1584) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n807), .CK(clk), .RN(n918), .Q(
intDY_EWSW[21]), .QN(n1572) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n810), .CK(clk), .RN(n1619),
.Q(intDY_EWSW[18]), .QN(n1592) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n811), .CK(clk), .RN(n1646),
.Q(intDY_EWSW[17]), .QN(n1587) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n813), .CK(clk), .RN(n1624),
.Q(intDY_EWSW[15]), .QN(n1586) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n814), .CK(clk), .RN(n1643),
.Q(intDY_EWSW[14]), .QN(n1533) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n815), .CK(clk), .RN(n1640),
.Q(intDY_EWSW[13]), .QN(n1571) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n816), .CK(clk), .RN(n917), .Q(
intDY_EWSW[12]), .QN(n1575) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n825), .CK(clk), .RN(n1619), .Q(
intDY_EWSW[3]), .QN(n1568) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n827), .CK(clk), .RN(n918), .Q(
intDY_EWSW[1]), .QN(n1588) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n837), .CK(clk), .RN(n1632),
.Q(intDX_EWSW[25]), .QN(n1543) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n838), .CK(clk), .RN(n1624),
.Q(intDX_EWSW[24]), .QN(n1608) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n846), .CK(clk), .RN(n1620),
.Q(intDX_EWSW[16]), .QN(n1558) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n855), .CK(clk), .RN(n1621), .Q(
intDX_EWSW[7]), .QN(n1528) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n856), .CK(clk), .RN(n1620), .Q(
intDX_EWSW[6]), .QN(n1553) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n857), .CK(clk), .RN(n1636), .Q(
intDX_EWSW[5]), .QN(n1549) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n858), .CK(clk), .RN(n1623), .Q(
intDX_EWSW[4]), .QN(n1524) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n767), .CK(clk), .RN(n1619), .Q(
shift_value_SHT2_EWR[4]), .QN(n1550) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n794), .CK(clk), .RN(n1621), .Q(
Data_array_SWR[23]), .QN(n1598) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n785), .CK(clk), .RN(n1637), .Q(
Data_array_SWR[14]), .QN(n1607) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n783), .CK(clk), .RN(n1618), .Q(
Data_array_SWR[12]), .QN(n1606) );
DFFRX4TS inst_ShiftRegister_Q_reg_5_ ( .D(n868), .CK(clk), .RN(n1619), .Q(
n1520), .QN(n1613) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n859), .CK(clk), .RN(n917), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n841), .CK(clk), .RN(n1621),
.Q(intDX_EWSW[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n849), .CK(clk), .RN(n1619),
.Q(intDX_EWSW[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n839), .CK(clk), .RN(n918), .Q(
intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n847), .CK(clk), .RN(n1619),
.Q(intDX_EWSW[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n793), .CK(clk), .RN(n1619), .Q(
Data_array_SWR[22]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n796), .CK(clk), .RN(n917), .Q(
Data_array_SWR[25]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n795), .CK(clk), .RN(n1621), .Q(
Data_array_SWR[24]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n854), .CK(clk), .RN(n1624), .Q(
intDX_EWSW[8]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n522), .CK(clk), .RN(n1635), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n845), .CK(clk), .RN(n1621),
.Q(intDX_EWSW[17]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n851), .CK(clk), .RN(n1624),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n861), .CK(clk), .RN(n1621), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n853), .CK(clk), .RN(n1620), .Q(
intDX_EWSW[9]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n530), .CK(clk), .RN(n1647), .Q(
Raw_mant_NRM_SWR[12]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n770), .CK(clk), .RN(n1624), .Q(
shift_value_SHT2_EWR[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n786), .CK(clk), .RN(n1633), .Q(
Data_array_SWR[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n784), .CK(clk), .RN(n1646), .Q(
Data_array_SWR[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n862), .CK(clk), .RN(n1644), .Q(
intDX_EWSW[0]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n523), .CK(clk), .RN(n1623), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n844), .CK(clk), .RN(n1624),
.Q(intDX_EWSW[18]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n833), .CK(clk), .RN(n1619),
.Q(intDX_EWSW[29]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n871), .CK(clk), .RN(
n1640), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n835), .CK(clk), .RN(n1620),
.Q(intDX_EWSW[27]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n779), .CK(clk), .RN(n1624), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n790), .CK(clk), .RN(n1622), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n787), .CK(clk), .RN(n1641), .Q(
Data_array_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n538), .CK(clk), .RN(n1645), .Q(
Raw_mant_NRM_SWR[4]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n524), .CK(clk), .RN(n1643), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n777), .CK(clk), .RN(n1620), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n778), .CK(clk), .RN(n1624), .Q(
Data_array_SWR[7]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n775), .CK(clk), .RN(n1619), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n776), .CK(clk), .RN(n1622), .Q(
Data_array_SWR[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n690), .CK(clk), .RN(n1627), .Q(
DMP_SFG[9]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n918), .Q(
DMP_SFG[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n714), .CK(clk), .RN(n1628), .Q(
DMP_SFG[1]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n831), .CK(clk), .RN(n1624),
.Q(intDX_EWSW[31]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n517), .CK(clk), .RN(n1647), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1521) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n818), .CK(clk), .RN(n1630),
.Q(intDY_EWSW[10]), .QN(n876) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n717), .CK(clk), .RN(n1631), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n473), .CK(clk), .RN(n1618), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n474), .CK(clk), .RN(n1647), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n475), .CK(clk), .RN(n1643), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n476), .CK(clk), .RN(n1625), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n478), .CK(clk), .RN(n1644), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n1624),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n1632), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n631), .CK(clk), .RN(n1623), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n636), .CK(clk), .RN(n1639), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n641), .CK(clk), .RN(n1640), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n817), .CK(clk), .RN(n1638),
.Q(intDY_EWSW[11]), .QN(n1560) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n797), .CK(clk), .RN(n1620),
.Q(intDY_EWSW[31]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n850), .CK(clk), .RN(n1621),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n842), .CK(clk), .RN(n1620),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n848), .CK(clk), .RN(n1621),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n840), .CK(clk), .RN(n1638),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n860), .CK(clk), .RN(n918), .Q(
intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n852), .CK(clk), .RN(n1619),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n832), .CK(clk), .RN(n1624),
.Q(intDX_EWSW[30]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n843), .CK(clk), .RN(n1639),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n780), .CK(clk), .RN(n1626), .Q(
Data_array_SWR[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n782), .CK(clk), .RN(n1639), .Q(
Data_array_SWR[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n792), .CK(clk), .RN(n1620), .Q(
Data_array_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n789), .CK(clk), .RN(n1625), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n788), .CK(clk), .RN(n1641), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n791), .CK(clk), .RN(n1648), .Q(
Data_array_SWR[20]) );
DFFRX2TS inst_ShiftRegister_Q_reg_4_ ( .D(n867), .CK(clk), .RN(n1619), .Q(
n1654), .QN(n1653) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n518), .CK(clk), .RN(n1641), .Q(
Raw_mant_NRM_SWR[24]), .QN(n1516) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n1649), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n589), .CK(clk), .RN(n1641), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n573), .CK(clk), .RN(n1618), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n565), .CK(clk), .RN(n1640), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n605), .CK(clk), .RN(n1618), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n567), .CK(clk), .RN(n1623), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n579), .CK(clk), .RN(n1634), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n571), .CK(clk), .RN(n1649), .Q(
DmP_mant_SHT1_SW[19]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n577), .CK(clk), .RN(n1638), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n575), .CK(clk), .RN(n1623), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n569), .CK(clk), .RN(n1622), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n477), .CK(clk), .RN(n1641), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n808), .CK(clk), .RN(n1620),
.Q(intDY_EWSW[20]), .QN(n1576) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n483), .CK(clk), .RN(n1647), .Q(
DmP_mant_SFG_SWR[5]), .QN(n966) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n479), .CK(clk), .RN(n1645), .Q(
DmP_mant_SFG_SWR[9]), .QN(n963) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n564), .CK(clk), .RN(n1625), .Q(
DmP_EXP_EWSW[23]), .QN(n957) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n626), .CK(clk), .RN(n1648), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n774), .CK(clk), .RN(n1624), .Q(
Data_array_SWR[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n773), .CK(clk), .RN(n1645), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n772), .CK(clk), .RN(n1643), .Q(
Data_array_SWR[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n771), .CK(clk), .RN(n1640), .Q(
Data_array_SWR[0]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n560), .CK(clk), .RN(n1623), .Q(
DmP_EXP_EWSW[27]) );
ADDFX1TS DP_OP_15J49_123_3372_U8 ( .A(n1557), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J49_123_3372_n8), .CO(DP_OP_15J49_123_3372_n7), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J49_123_3372_U7 ( .A(n1563), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J49_123_3372_n7), .CO(DP_OP_15J49_123_3372_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J49_123_3372_U6 ( .A(n1566), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J49_123_3372_n6), .CO(DP_OP_15J49_123_3372_n5), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J49_123_3372_U5 ( .A(n1567), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J49_123_3372_n5), .CO(DP_OP_15J49_123_3372_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX4TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n549), .CK(clk), .RN(n1646), .Q(
OP_FLAG_SFG), .QN(n1526) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n864), .CK(clk), .RN(n1624), .Q(
Shift_reg_FLAGS_7[1]), .QN(n877) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n863), .CK(clk), .RN(n1648), .Q(
Shift_reg_FLAGS_7[0]), .QN(n872) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n869), .CK(clk), .RN(n1619), .Q(
Shift_reg_FLAGS_7_6), .QN(n968) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n829), .CK(clk), .RN(n1621), .Q(
left_right_SHT2), .QN(n878) );
AOI222X1TS U897 ( .A0(n1439), .A1(left_right_SHT2), .B0(Data_array_SWR[7]),
.B1(n940), .C0(n1438), .C1(n1455), .Y(n1501) );
NAND2X4TS U898 ( .A(n924), .B(n872), .Y(n1374) );
AOI222X4TS U899 ( .A0(Data_array_SWR[14]), .A1(n942), .B0(Data_array_SWR[22]), .B1(n1472), .C0(Data_array_SWR[18]), .C1(n944), .Y(n1423) );
AOI222X4TS U900 ( .A0(Data_array_SWR[24]), .A1(n1433), .B0(
Data_array_SWR[20]), .B1(n1448), .C0(Data_array_SWR[16]), .C1(n1447),
.Y(n1476) );
AOI222X4TS U901 ( .A0(Data_array_SWR[21]), .A1(n1448), .B0(
Data_array_SWR[17]), .B1(n1447), .C0(Data_array_SWR[25]), .C1(n1433),
.Y(n1470) );
AOI222X4TS U902 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n911), .B0(n913), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1254), .C1(DmP_mant_SHT1_SW[17]), .Y(n1234) );
NOR2X4TS U903 ( .A(n1205), .B(n1264), .Y(n1206) );
AOI211X2TS U904 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1172), .B0(n1306), .C0(
n1171), .Y(n1187) );
OAI222X1TS U905 ( .A0(n1611), .A1(n1351), .B0(n946), .B1(n1342), .C0(n910),
.C1(n1341), .Y(n781) );
OAI222X1TS U906 ( .A0(n1351), .A1(n1607), .B0(n946), .B1(n1340), .C0(n910),
.C1(n1334), .Y(n785) );
OAI222X1TS U907 ( .A0(n1598), .A1(n1351), .B0(n946), .B1(n1331), .C0(n910),
.C1(n1330), .Y(n794) );
AOI211X1TS U908 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n1387), .B0(n1335), .C0(
n1265), .Y(n1329) );
NAND3X1TS U909 ( .A(n1157), .B(n1300), .C(Raw_mant_NRM_SWR[1]), .Y(n1294) );
OAI211X1TS U910 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1163), .B0(n1299), .C0(
n1552), .Y(n1164) );
OAI21X1TS U911 ( .A0(Raw_mant_NRM_SWR[6]), .A1(Raw_mant_NRM_SWR[7]), .B0(
n1155), .Y(n1156) );
BUFX3TS U912 ( .A(n1047), .Y(n873) );
INVX3TS U913 ( .A(n1351), .Y(n1185) );
INVX3TS U914 ( .A(n908), .Y(n875) );
INVX1TS U915 ( .A(LZD_output_NRM2_EW[0]), .Y(n1288) );
INVX1TS U916 ( .A(DMP_SFG[7]), .Y(intadd_52_A_1_) );
OAI222X1TS U917 ( .A0(n1606), .A1(n1351), .B0(n946), .B1(n1341), .C0(n910),
.C1(n1340), .Y(n783) );
INVX3TS U918 ( .A(n1184), .Y(n946) );
BUFX3TS U919 ( .A(n1203), .Y(n910) );
CLKBUFX3TS U920 ( .A(n1190), .Y(n1269) );
AND2X2TS U921 ( .A(n1186), .B(n1351), .Y(n1184) );
AOI222X1TS U922 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n911), .B0(n913), .B1(n933),
.C0(n1254), .C1(n925), .Y(n1261) );
AOI222X1TS U923 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n912), .B0(n914), .B1(
DmP_mant_SHT1_SW[19]), .C0(n1254), .C1(DmP_mant_SHT1_SW[20]), .Y(n1250) );
AOI222X1TS U924 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n912), .B0(n913), .B1(n931),
.C0(n1335), .C1(n927), .Y(n1245) );
AOI222X1TS U925 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n912), .B0(n914), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1254), .C1(DmP_mant_SHT1_SW[18]), .Y(n1253) );
INVX3TS U926 ( .A(n1338), .Y(n912) );
NAND3X1TS U927 ( .A(n1178), .B(n1164), .C(n1295), .Y(n1306) );
INVX3TS U928 ( .A(n1150), .Y(n1382) );
INVX3TS U929 ( .A(n1150), .Y(n1093) );
INVX3TS U930 ( .A(n1146), .Y(n1380) );
INVX3TS U931 ( .A(n1146), .Y(n1073) );
NOR2X4TS U932 ( .A(n1046), .B(n968), .Y(n1047) );
AOI32X1TS U933 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1351), .A2(n1387), .B0(
shift_value_SHT2_EWR[2]), .B1(n1348), .Y(n1350) );
AO22XLTS U934 ( .A0(n1321), .A1(add_subt), .B0(n921), .B1(intAS), .Y(n830)
);
AOI211XLTS U935 ( .A0(intDY_EWSW[16]), .A1(n1558), .B0(n1033), .C0(n1103),
.Y(n1025) );
BUFX3TS U936 ( .A(n1321), .Y(n874) );
OAI211X2TS U937 ( .A0(intDX_EWSW[20]), .A1(n1576), .B0(n1038), .C0(n1024),
.Y(n1033) );
INVX3TS U938 ( .A(n887), .Y(n914) );
INVX3TS U939 ( .A(OP_FLAG_SFG), .Y(n1407) );
OAI211X2TS U940 ( .A0(intDX_EWSW[12]), .A1(n1575), .B0(n1019), .C0(n1005),
.Y(n1021) );
INVX3TS U941 ( .A(n1654), .Y(n1376) );
NAND4XLTS U942 ( .A(n1521), .B(n1516), .C(n1515), .D(n1545), .Y(n1303) );
NAND3X1TS U943 ( .A(n1546), .B(n1522), .C(n1517), .Y(n1292) );
CLKINVX2TS U944 ( .A(DMP_SFG[8]), .Y(intadd_52_A_2_) );
INVX3TS U945 ( .A(n1651), .Y(n1406) );
INVX4TS U946 ( .A(rst), .Y(n918) );
NAND2X1TS U947 ( .A(n1155), .B(n1527), .Y(n1162) );
AOI2BB2XLTS U948 ( .B0(DmP_mant_SFG_SWR[12]), .B1(n1407), .A0N(n1526), .A1N(
DmP_mant_SFG_SWR[12]), .Y(intadd_51_CI) );
AOI2BB2XLTS U949 ( .B0(DmP_mant_SFG_SWR[14]), .B1(n1407), .A0N(n1526), .A1N(
DmP_mant_SFG_SWR[14]), .Y(intadd_51_B_2_) );
NAND2BXLTS U950 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n996) );
AOI2BB2XLTS U951 ( .B0(intDX_EWSW[3]), .B1(n1568), .A0N(intDY_EWSW[2]),
.A1N(n998), .Y(n999) );
NAND2BXLTS U952 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1011) );
NAND3XLTS U953 ( .A(n1589), .B(n1009), .C(intDX_EWSW[8]), .Y(n1010) );
NAND2BXLTS U954 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1030) );
NOR2XLTS U955 ( .A(n1041), .B(intDY_EWSW[24]), .Y(n983) );
NAND2BXLTS U956 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n984) );
NAND2BXLTS U957 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n1009) );
NAND2BXLTS U958 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n1005) );
NAND2BXLTS U959 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1024) );
CLKAND2X2TS U960 ( .A(n1447), .B(shift_value_SHT2_EWR[4]), .Y(n1440) );
NOR2XLTS U961 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(n1173) );
AOI32X1TS U962 ( .A0(n1516), .A1(n1183), .A2(n1166), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1183), .Y(n1167) );
NAND2X1TS U963 ( .A(n1177), .B(n1518), .Y(n1170) );
NAND2X1TS U964 ( .A(n1165), .B(n1523), .Y(n1293) );
OAI2BB2XLTS U965 ( .B0(intDY_EWSW[22]), .B1(n1034), .A0N(intDX_EWSW[23]),
.A1N(n938), .Y(n1035) );
NAND2BXLTS U966 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n985) );
NAND3XLTS U967 ( .A(n1590), .B(n984), .C(intDX_EWSW[26]), .Y(n986) );
NAND2BXLTS U968 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1039) );
NAND3BXLTS U969 ( .AN(n1028), .B(n1026), .C(n1025), .Y(n1044) );
AOI222X4TS U970 ( .A0(Data_array_SWR[21]), .A1(n944), .B0(Data_array_SWR[17]), .B1(n942), .C0(Data_array_SWR[25]), .C1(n1472), .Y(n1416) );
NAND2BXLTS U971 ( .AN(n1273), .B(n1310), .Y(n1274) );
NAND3XLTS U972 ( .A(n1309), .B(exp_rslt_NRM2_EW1[4]), .C(n1272), .Y(n1273)
);
OR2X1TS U973 ( .A(n981), .B(n1271), .Y(n1280) );
NAND2BXLTS U974 ( .AN(n1310), .B(n978), .Y(n981) );
NAND4BXLTS U975 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n976), .C(n975), .D(n974),
.Y(n977) );
INVX2TS U976 ( .A(n886), .Y(n923) );
AO22XLTS U977 ( .A0(DmP_mant_SFG_SWR[6]), .A1(n1407), .B0(n1403), .B1(n967),
.Y(n886) );
NOR2XLTS U978 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(n1176) );
AO21XLTS U979 ( .A0(n1518), .A1(n1540), .B0(n1293), .Y(n1301) );
AOI221X1TS U980 ( .A0(n1535), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]), .B1(
n938), .C0(n1105), .Y(n1106) );
OAI21XLTS U981 ( .A0(n1552), .A1(n1338), .B0(n1232), .Y(n1233) );
AOI222X1TS U982 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n912), .B0(n914), .B1(n932),
.C0(n1254), .C1(DmP_mant_SHT1_SW[10]), .Y(n1248) );
AOI222X1TS U983 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n912), .B0(n914), .B1(n926),
.C0(n1254), .C1(n929), .Y(n1215) );
AOI222X1TS U984 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n912), .B0(n914), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1254), .C1(n926), .Y(n1220) );
AOI222X1TS U985 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n912), .B0(n914), .B1(n925),
.C0(n1254), .C1(DmP_mant_SHT1_SW[8]), .Y(n1223) );
AOI222X1TS U986 ( .A0(n1270), .A1(DMP_SFG[1]), .B0(n1270), .B1(n919), .C0(
DMP_SFG[1]), .C1(n919), .Y(intadd_53_CI) );
AOI222X1TS U987 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n911), .B0(n930), .B1(n1254), .C0(n913), .C1(n928), .Y(n1242) );
AOI222X1TS U988 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n912), .B0(n914), .B1(
DmP_mant_SHT1_SW[15]), .C0(n1254), .C1(DmP_mant_SHT1_SW[16]), .Y(n1241) );
OAI21XLTS U989 ( .A0(n1542), .A1(n1338), .B0(n1228), .Y(n1229) );
AO22XLTS U990 ( .A0(DmP_mant_SFG_SWR[3]), .A1(n1403), .B0(n1407), .B1(n961),
.Y(n885) );
CLKAND2X2TS U991 ( .A(n1602), .B(n1276), .Y(n1277) );
NOR2XLTS U992 ( .A(n1279), .B(n1274), .Y(n1278) );
AOI2BB2XLTS U993 ( .B0(DmP_mant_SFG_SWR[15]), .B1(n1407), .A0N(n1526), .A1N(
DmP_mant_SFG_SWR[15]), .Y(intadd_51_B_3_) );
AO22XLTS U994 ( .A0(DmP_mant_SFG_SWR[7]), .A1(n1403), .B0(n1407), .B1(n965),
.Y(n884) );
AOI2BB2XLTS U995 ( .B0(DmP_mant_SFG_SWR[13]), .B1(n1407), .A0N(n1526), .A1N(
DmP_mant_SFG_SWR[13]), .Y(intadd_51_B_1_) );
NAND3XLTS U996 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1531), .C(n1564), .Y(n1312) );
OAI21XLTS U997 ( .A0(n1540), .A1(n1338), .B0(n1337), .Y(n1339) );
AOI222X1TS U998 ( .A0(n1435), .A1(n875), .B0(Data_array_SWR[8]), .B1(n903),
.C0(n1434), .C1(n1454), .Y(n1487) );
OAI21XLTS U999 ( .A0(n1529), .A1(n1158), .B0(n1294), .Y(n1159) );
NOR2XLTS U1000 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1153)
);
NAND4XLTS U1001 ( .A(n1296), .B(n1295), .C(n1294), .D(n1301), .Y(n1297) );
BUFX4TS U1002 ( .A(n1049), .Y(n1145) );
AO22XLTS U1003 ( .A0(n1320), .A1(intDY_EWSW[20]), .B0(n922), .B1(Data_Y[20]),
.Y(n808) );
AO22XLTS U1004 ( .A0(n1491), .A1(DmP_mant_SFG_SWR[11]), .B0(n1497), .B1(
n1490), .Y(n477) );
AO22XLTS U1005 ( .A0(n949), .A1(DmP_EXP_EWSW[20]), .B0(n1379), .B1(
DmP_mant_SHT1_SW[20]), .Y(n569) );
AO22XLTS U1006 ( .A0(n949), .A1(DmP_EXP_EWSW[17]), .B0(n1379), .B1(
DmP_mant_SHT1_SW[17]), .Y(n575) );
AO22XLTS U1007 ( .A0(n949), .A1(DmP_EXP_EWSW[16]), .B0(n1379), .B1(
DmP_mant_SHT1_SW[16]), .Y(n577) );
AO22XLTS U1008 ( .A0(n949), .A1(DmP_EXP_EWSW[19]), .B0(n1379), .B1(
DmP_mant_SHT1_SW[19]), .Y(n571) );
AO22XLTS U1009 ( .A0(n949), .A1(DmP_EXP_EWSW[15]), .B0(n1379), .B1(
DmP_mant_SHT1_SW[15]), .Y(n579) );
AO22XLTS U1010 ( .A0(n949), .A1(DmP_EXP_EWSW[21]), .B0(n1379), .B1(
DmP_mant_SHT1_SW[21]), .Y(n567) );
AO22XLTS U1011 ( .A0(n1520), .A1(DmP_EXP_EWSW[2]), .B0(n1378), .B1(
DmP_mant_SHT1_SW[2]), .Y(n605) );
AO22XLTS U1012 ( .A0(n949), .A1(DmP_EXP_EWSW[22]), .B0(n1379), .B1(
DmP_mant_SHT1_SW[22]), .Y(n565) );
AO22XLTS U1013 ( .A0(n949), .A1(DmP_EXP_EWSW[18]), .B0(n1379), .B1(
DmP_mant_SHT1_SW[18]), .Y(n573) );
AO22XLTS U1014 ( .A0(n1520), .A1(DmP_EXP_EWSW[10]), .B0(n1378), .B1(
DmP_mant_SHT1_SW[10]), .Y(n589) );
AO22XLTS U1015 ( .A0(n1520), .A1(DmP_EXP_EWSW[8]), .B0(n1378), .B1(
DmP_mant_SHT1_SW[8]), .Y(n593) );
OAI21XLTS U1016 ( .A0(n1258), .A1(n946), .B0(n1257), .Y(n791) );
OAI211XLTS U1017 ( .A0(n1241), .A1(n946), .B0(n1240), .C0(n1239), .Y(n788)
);
OAI211XLTS U1018 ( .A0(n1223), .A1(n946), .B0(n1222), .C0(n1221), .Y(n780)
);
AOI2BB2XLTS U1019 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1343), .A0N(n1248),
.A1N(n910), .Y(n1221) );
AO22XLTS U1020 ( .A0(n1321), .A1(Data_X[19]), .B0(n1327), .B1(intDX_EWSW[19]), .Y(n843) );
AO22XLTS U1021 ( .A0(n922), .A1(Data_X[30]), .B0(n1327), .B1(intDX_EWSW[30]),
.Y(n832) );
AO22XLTS U1022 ( .A0(n1325), .A1(Data_X[10]), .B0(n1322), .B1(intDX_EWSW[10]), .Y(n852) );
AO22XLTS U1023 ( .A0(n1328), .A1(Data_X[2]), .B0(n1327), .B1(intDX_EWSW[2]),
.Y(n860) );
AO22XLTS U1024 ( .A0(n874), .A1(Data_X[22]), .B0(n1324), .B1(intDX_EWSW[22]),
.Y(n840) );
AO22XLTS U1025 ( .A0(n1328), .A1(Data_X[14]), .B0(n1322), .B1(intDX_EWSW[14]), .Y(n848) );
AO22XLTS U1026 ( .A0(n1328), .A1(Data_X[20]), .B0(n1320), .B1(intDX_EWSW[20]), .Y(n842) );
AO22XLTS U1027 ( .A0(n1323), .A1(Data_X[12]), .B0(n1319), .B1(intDX_EWSW[12]), .Y(n850) );
AO22XLTS U1028 ( .A0(n874), .A1(Data_Y[31]), .B0(n921), .B1(intDY_EWSW[31]),
.Y(n797) );
AO22XLTS U1029 ( .A0(n1324), .A1(intDY_EWSW[11]), .B0(n874), .B1(Data_Y[11]),
.Y(n817) );
OAI21XLTS U1030 ( .A0(n938), .A1(n1382), .B0(n1094), .Y(n730) );
AO22XLTS U1031 ( .A0(n1498), .A1(DmP_mant_SFG_SWR[10]), .B0(n1497), .B1(
n1489), .Y(n478) );
AO22XLTS U1032 ( .A0(n1498), .A1(DmP_mant_SFG_SWR[12]), .B0(n1493), .B1(
n1492), .Y(n476) );
AO22XLTS U1033 ( .A0(n1498), .A1(DmP_mant_SFG_SWR[13]), .B0(n1493), .B1(
n1494), .Y(n475) );
AO22XLTS U1034 ( .A0(n1498), .A1(DmP_mant_SFG_SWR[14]), .B0(n1497), .B1(
n1495), .Y(n474) );
AO22XLTS U1035 ( .A0(n1498), .A1(DmP_mant_SFG_SWR[15]), .B0(n1493), .B1(
n1496), .Y(n473) );
AO22XLTS U1036 ( .A0(n1497), .A1(DMP_SHT2_EWSW[0]), .B0(n1498), .B1(
DMP_SFG[0]), .Y(n717) );
AO22XLTS U1037 ( .A0(n1326), .A1(intDY_EWSW[10]), .B0(n922), .B1(Data_Y[10]),
.Y(n818) );
AO22XLTS U1038 ( .A0(n874), .A1(Data_X[31]), .B0(n1324), .B1(intDX_EWSW[31]),
.Y(n831) );
AO22XLTS U1039 ( .A0(n1497), .A1(DMP_SHT2_EWSW[1]), .B0(n1374), .B1(
DMP_SFG[1]), .Y(n714) );
AO22XLTS U1040 ( .A0(n1509), .A1(DMP_SHT2_EWSW[5]), .B0(n1512), .B1(
DMP_SFG[5]), .Y(n702) );
AO22XLTS U1041 ( .A0(n1509), .A1(DMP_SHT2_EWSW[9]), .B0(n1512), .B1(
DMP_SFG[9]), .Y(n690) );
OAI211XLTS U1042 ( .A0(n1220), .A1(n946), .B0(n1202), .C0(n1201), .Y(n775)
);
AOI2BB2XLTS U1043 ( .B0(n1650), .B1(intadd_51_SUM_6_), .A0N(
Raw_mant_NRM_SWR[18]), .A1N(n1402), .Y(n524) );
OAI211XLTS U1044 ( .A0(n1253), .A1(n946), .B0(n1252), .C0(n1251), .Y(n790)
);
AO22XLTS U1045 ( .A0(n1328), .A1(Data_X[27]), .B0(n1322), .B1(intDX_EWSW[27]), .Y(n835) );
AO22XLTS U1046 ( .A0(n1325), .A1(Data_X[29]), .B0(n1322), .B1(intDX_EWSW[29]), .Y(n833) );
AO22XLTS U1047 ( .A0(n1323), .A1(Data_X[18]), .B0(n1320), .B1(intDX_EWSW[18]), .Y(n844) );
AOI2BB2XLTS U1048 ( .B0(n1650), .B1(intadd_51_SUM_7_), .A0N(
Raw_mant_NRM_SWR[19]), .A1N(n1402), .Y(n523) );
AO22XLTS U1049 ( .A0(n1321), .A1(Data_X[0]), .B0(n1327), .B1(intDX_EWSW[0]),
.Y(n862) );
OAI211XLTS U1050 ( .A0(n1242), .A1(n946), .B0(n1238), .C0(n1237), .Y(n786)
);
AOI2BB2XLTS U1051 ( .B0(n1650), .B1(intadd_51_SUM_0_), .A0N(
Raw_mant_NRM_SWR[12]), .A1N(n1402), .Y(n530) );
AO22XLTS U1052 ( .A0(n1323), .A1(Data_X[9]), .B0(n921), .B1(intDX_EWSW[9]),
.Y(n853) );
AO22XLTS U1053 ( .A0(n1328), .A1(Data_X[1]), .B0(n1320), .B1(intDX_EWSW[1]),
.Y(n861) );
AO22XLTS U1054 ( .A0(n874), .A1(Data_X[11]), .B0(n1320), .B1(intDX_EWSW[11]),
.Y(n851) );
AO22XLTS U1055 ( .A0(n1328), .A1(Data_X[17]), .B0(n1319), .B1(intDX_EWSW[17]), .Y(n845) );
AOI2BB2XLTS U1056 ( .B0(n1650), .B1(intadd_51_SUM_8_), .A0N(
Raw_mant_NRM_SWR[20]), .A1N(n1650), .Y(n522) );
AO22XLTS U1057 ( .A0(n874), .A1(Data_X[8]), .B0(n1319), .B1(intDX_EWSW[8]),
.Y(n854) );
OAI21XLTS U1058 ( .A0(n1551), .A1(n1269), .B0(n1268), .Y(n793) );
AO22XLTS U1059 ( .A0(n1323), .A1(Data_X[15]), .B0(n921), .B1(intDX_EWSW[15]),
.Y(n847) );
AO22XLTS U1060 ( .A0(n874), .A1(Data_X[23]), .B0(n921), .B1(intDX_EWSW[23]),
.Y(n839) );
AO22XLTS U1061 ( .A0(n1323), .A1(Data_X[13]), .B0(n1324), .B1(intDX_EWSW[13]), .Y(n849) );
AO22XLTS U1062 ( .A0(n922), .A1(Data_X[21]), .B0(n1319), .B1(intDX_EWSW[21]),
.Y(n841) );
AO22XLTS U1063 ( .A0(n1321), .A1(Data_X[3]), .B0(n1324), .B1(intDX_EWSW[3]),
.Y(n859) );
AO22XLTS U1064 ( .A0(n1323), .A1(Data_X[4]), .B0(n1320), .B1(intDX_EWSW[4]),
.Y(n858) );
AO22XLTS U1065 ( .A0(n874), .A1(Data_X[5]), .B0(n1324), .B1(intDX_EWSW[5]),
.Y(n857) );
AO22XLTS U1066 ( .A0(n922), .A1(Data_X[6]), .B0(n1322), .B1(intDX_EWSW[6]),
.Y(n856) );
AO22XLTS U1067 ( .A0(n922), .A1(Data_X[7]), .B0(n1319), .B1(intDX_EWSW[7]),
.Y(n855) );
AO22XLTS U1068 ( .A0(n874), .A1(Data_X[16]), .B0(n921), .B1(intDX_EWSW[16]),
.Y(n846) );
AO22XLTS U1069 ( .A0(n1322), .A1(intDX_EWSW[24]), .B0(n1323), .B1(Data_X[24]), .Y(n838) );
AO22XLTS U1070 ( .A0(n1320), .A1(intDX_EWSW[25]), .B0(n1328), .B1(Data_X[25]), .Y(n837) );
AO22XLTS U1071 ( .A0(n1319), .A1(intDY_EWSW[1]), .B0(n1328), .B1(Data_Y[1]),
.Y(n827) );
AO22XLTS U1072 ( .A0(n1324), .A1(intDY_EWSW[3]), .B0(n874), .B1(Data_Y[3]),
.Y(n825) );
AO22XLTS U1073 ( .A0(n1324), .A1(intDY_EWSW[12]), .B0(n1323), .B1(Data_Y[12]), .Y(n816) );
AO22XLTS U1074 ( .A0(n1319), .A1(intDY_EWSW[13]), .B0(n922), .B1(Data_Y[13]),
.Y(n815) );
AO22XLTS U1075 ( .A0(n1327), .A1(intDY_EWSW[14]), .B0(n922), .B1(Data_Y[14]),
.Y(n814) );
AO22XLTS U1076 ( .A0(n1322), .A1(intDY_EWSW[15]), .B0(n922), .B1(Data_Y[15]),
.Y(n813) );
AO22XLTS U1077 ( .A0(n1320), .A1(intDY_EWSW[17]), .B0(n922), .B1(Data_Y[17]),
.Y(n811) );
AO22XLTS U1078 ( .A0(n921), .A1(intDY_EWSW[18]), .B0(n922), .B1(Data_Y[18]),
.Y(n810) );
AO22XLTS U1079 ( .A0(n1324), .A1(intDY_EWSW[21]), .B0(n922), .B1(Data_Y[21]),
.Y(n807) );
AO22XLTS U1080 ( .A0(n1322), .A1(intDY_EWSW[25]), .B0(n1328), .B1(Data_Y[25]), .Y(n803) );
AO22XLTS U1081 ( .A0(n921), .A1(intDY_EWSW[26]), .B0(n1323), .B1(Data_Y[26]),
.Y(n802) );
AO22XLTS U1082 ( .A0(n1327), .A1(intDY_EWSW[29]), .B0(n922), .B1(Data_Y[29]),
.Y(n799) );
AO22XLTS U1083 ( .A0(n1319), .A1(intDY_EWSW[30]), .B0(n1328), .B1(Data_Y[30]), .Y(n798) );
AO22XLTS U1084 ( .A0(n1327), .A1(intDY_EWSW[22]), .B0(n1323), .B1(Data_Y[22]), .Y(n806) );
AO22XLTS U1085 ( .A0(n921), .A1(intDY_EWSW[8]), .B0(n874), .B1(Data_Y[8]),
.Y(n820) );
NOR2XLTS U1086 ( .A(n1412), .B(SIGN_FLAG_SHT1SHT2), .Y(n1281) );
AO22XLTS U1087 ( .A0(final_result_ieee[10]), .A1(n1471), .B0(n1428), .B1(
n1492), .Y(n511) );
AO22XLTS U1088 ( .A0(n1428), .A1(n1496), .B0(final_result_ieee[13]), .B1(
n1471), .Y(n506) );
AO22XLTS U1089 ( .A0(n1428), .A1(n1489), .B0(final_result_ieee[8]), .B1(
n1471), .Y(n507) );
AO22XLTS U1090 ( .A0(n1428), .A1(n1495), .B0(final_result_ieee[12]), .B1(
n1471), .Y(n508) );
AO22XLTS U1091 ( .A0(n1428), .A1(n1490), .B0(final_result_ieee[9]), .B1(
n1471), .Y(n509) );
AO22XLTS U1092 ( .A0(n1428), .A1(n1494), .B0(final_result_ieee[11]), .B1(
n1471), .Y(n510) );
AO22XLTS U1093 ( .A0(n1324), .A1(intDY_EWSW[24]), .B0(n1328), .B1(Data_Y[24]), .Y(n804) );
AO22XLTS U1094 ( .A0(n1326), .A1(intDY_EWSW[5]), .B0(n874), .B1(Data_Y[5]),
.Y(n823) );
AO22XLTS U1095 ( .A0(n1327), .A1(intDY_EWSW[16]), .B0(n922), .B1(Data_Y[16]),
.Y(n812) );
AO22XLTS U1096 ( .A0(n1326), .A1(intDY_EWSW[19]), .B0(n922), .B1(Data_Y[19]),
.Y(n809) );
AO22XLTS U1097 ( .A0(n1327), .A1(intDX_EWSW[26]), .B0(n1323), .B1(Data_X[26]), .Y(n836) );
AO22XLTS U1098 ( .A0(n1325), .A1(Data_X[28]), .B0(n1327), .B1(intDX_EWSW[28]), .Y(n834) );
OAI21XLTS U1099 ( .A0(n1314), .A1(n982), .B0(n1312), .Y(n870) );
AOI2BB2XLTS U1100 ( .B0(beg_OP), .B1(n1531), .A0N(n1531), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n982) );
AO22XLTS U1101 ( .A0(n1322), .A1(intDY_EWSW[6]), .B0(n874), .B1(Data_Y[6]),
.Y(n822) );
AO22XLTS U1102 ( .A0(n1319), .A1(intDY_EWSW[9]), .B0(n1328), .B1(Data_Y[9]),
.Y(n819) );
AO22XLTS U1103 ( .A0(n921), .A1(intDY_EWSW[2]), .B0(n1323), .B1(Data_Y[2]),
.Y(n826) );
AO22XLTS U1104 ( .A0(n1322), .A1(intDY_EWSW[4]), .B0(n1328), .B1(Data_Y[4]),
.Y(n824) );
AO22XLTS U1105 ( .A0(n1319), .A1(intDY_EWSW[7]), .B0(n1328), .B1(Data_Y[7]),
.Y(n821) );
AO22XLTS U1106 ( .A0(n1326), .A1(intDY_EWSW[28]), .B0(n1323), .B1(Data_Y[28]), .Y(n800) );
AO22XLTS U1107 ( .A0(n1320), .A1(intDY_EWSW[23]), .B0(n1323), .B1(Data_Y[23]), .Y(n805) );
AO22XLTS U1108 ( .A0(n1326), .A1(intDY_EWSW[27]), .B0(n874), .B1(Data_Y[27]),
.Y(n801) );
AO22XLTS U1109 ( .A0(n1320), .A1(intDY_EWSW[0]), .B0(n1325), .B1(Data_Y[0]),
.Y(n828) );
AO21XLTS U1110 ( .A0(LZD_output_NRM2_EW[1]), .A1(n1387), .B0(n1307), .Y(n513) );
AO21XLTS U1111 ( .A0(LZD_output_NRM2_EW[0]), .A1(n1387), .B0(n1336), .Y(n515) );
AOI2BB1XLTS U1112 ( .A0N(Shift_reg_FLAGS_7[1]), .A1N(LZD_output_NRM2_EW[3]),
.B0(n1353), .Y(n516) );
AO22XLTS U1113 ( .A0(n1493), .A1(ZERO_FLAG_SHT2), .B0(n1512), .B1(
ZERO_FLAG_SFG), .Y(n555) );
OAI21XLTS U1114 ( .A0(n1535), .A1(n1380), .B0(n1051), .Y(n566) );
OAI21XLTS U1115 ( .A0(n1572), .A1(n1380), .B0(n1058), .Y(n568) );
OAI21XLTS U1116 ( .A0(n1536), .A1(n1380), .B0(n1052), .Y(n572) );
OAI21XLTS U1117 ( .A0(n1592), .A1(n1380), .B0(n1064), .Y(n574) );
OAI21XLTS U1118 ( .A0(n1587), .A1(n1380), .B0(n1057), .Y(n576) );
OAI21XLTS U1119 ( .A0(n1586), .A1(n1073), .B0(n1072), .Y(n580) );
AO22XLTS U1120 ( .A0(n1520), .A1(DmP_EXP_EWSW[14]), .B0(n1379), .B1(n930),
.Y(n581) );
OAI21XLTS U1121 ( .A0(n1533), .A1(n1073), .B0(n1050), .Y(n582) );
AO22XLTS U1122 ( .A0(n1520), .A1(DmP_EXP_EWSW[13]), .B0(n1379), .B1(n928),
.Y(n583) );
OAI21XLTS U1123 ( .A0(n1571), .A1(n1073), .B0(n1059), .Y(n584) );
AO22XLTS U1124 ( .A0(n1520), .A1(DmP_EXP_EWSW[12]), .B0(n1379), .B1(n927),
.Y(n585) );
OAI21XLTS U1125 ( .A0(n1575), .A1(n1073), .B0(n1066), .Y(n586) );
AO22XLTS U1126 ( .A0(n1520), .A1(DmP_EXP_EWSW[11]), .B0(n1378), .B1(n931),
.Y(n587) );
OAI21XLTS U1127 ( .A0(n1112), .A1(n1073), .B0(n1069), .Y(n588) );
OAI21XLTS U1128 ( .A0(n876), .A1(n1073), .B0(n1060), .Y(n590) );
AO22XLTS U1129 ( .A0(n1520), .A1(DmP_EXP_EWSW[9]), .B0(n1378), .B1(n932),
.Y(n591) );
OAI21XLTS U1130 ( .A0(n1570), .A1(n1073), .B0(n1062), .Y(n592) );
OAI21XLTS U1131 ( .A0(n1589), .A1(n1073), .B0(n1067), .Y(n594) );
AO22XLTS U1132 ( .A0(n1520), .A1(DmP_EXP_EWSW[7]), .B0(n1378), .B1(n925),
.Y(n595) );
OAI21XLTS U1133 ( .A0(n1577), .A1(n1073), .B0(n1063), .Y(n596) );
AO22XLTS U1134 ( .A0(n1520), .A1(DmP_EXP_EWSW[6]), .B0(n1378), .B1(n933),
.Y(n597) );
OAI21XLTS U1135 ( .A0(n1569), .A1(n1073), .B0(n1055), .Y(n598) );
AO22XLTS U1136 ( .A0(n1520), .A1(DmP_EXP_EWSW[5]), .B0(n1378), .B1(n934),
.Y(n599) );
OAI21XLTS U1137 ( .A0(n1532), .A1(n1073), .B0(n1054), .Y(n600) );
AO22XLTS U1138 ( .A0(n1520), .A1(DmP_EXP_EWSW[4]), .B0(n1378), .B1(n929),
.Y(n601) );
OAI21XLTS U1139 ( .A0(n1574), .A1(n1073), .B0(n1056), .Y(n602) );
AO22XLTS U1140 ( .A0(n1520), .A1(DmP_EXP_EWSW[3]), .B0(n1378), .B1(n926),
.Y(n603) );
OAI21XLTS U1141 ( .A0(n1568), .A1(n1131), .B0(n1070), .Y(n604) );
OAI21XLTS U1142 ( .A0(n1573), .A1(n1131), .B0(n1068), .Y(n606) );
AO22XLTS U1143 ( .A0(n1520), .A1(DmP_EXP_EWSW[1]), .B0(n1378), .B1(n935),
.Y(n607) );
OAI21XLTS U1144 ( .A0(n1588), .A1(n1131), .B0(n1065), .Y(n608) );
AO22XLTS U1145 ( .A0(n949), .A1(DmP_EXP_EWSW[0]), .B0(n1385), .B1(n936), .Y(
n609) );
OAI21XLTS U1146 ( .A0(n1585), .A1(n1131), .B0(n1048), .Y(n610) );
AO22XLTS U1147 ( .A0(n1509), .A1(DMP_SHT2_EWSW[29]), .B0(n1512), .B1(
DMP_SFG[29]), .Y(n618) );
AO22XLTS U1148 ( .A0(n1491), .A1(DMP_SFG[22]), .B0(n1497), .B1(
DMP_SHT2_EWSW[22]), .Y(n651) );
AO22XLTS U1149 ( .A0(n1491), .A1(DMP_SFG[21]), .B0(n1493), .B1(
DMP_SHT2_EWSW[21]), .Y(n654) );
AO22XLTS U1150 ( .A0(n1491), .A1(DMP_SFG[20]), .B0(n1497), .B1(
DMP_SHT2_EWSW[20]), .Y(n657) );
AO22XLTS U1151 ( .A0(n1491), .A1(DMP_SFG[19]), .B0(n1493), .B1(
DMP_SHT2_EWSW[19]), .Y(n660) );
AO22XLTS U1152 ( .A0(n1491), .A1(DMP_SFG[17]), .B0(n1493), .B1(
DMP_SHT2_EWSW[17]), .Y(n666) );
AO22XLTS U1153 ( .A0(n1491), .A1(DMP_SFG[15]), .B0(n1497), .B1(
DMP_SHT2_EWSW[15]), .Y(n672) );
AO22XLTS U1154 ( .A0(n1491), .A1(DMP_SFG[13]), .B0(n1493), .B1(
DMP_SHT2_EWSW[13]), .Y(n678) );
AO22XLTS U1155 ( .A0(n1491), .A1(DMP_SFG[11]), .B0(n1497), .B1(
DMP_SHT2_EWSW[11]), .Y(n684) );
AO22XLTS U1156 ( .A0(n1491), .A1(DMP_SFG[6]), .B0(n1493), .B1(
DMP_SHT2_EWSW[6]), .Y(n699) );
OAI21XLTS U1157 ( .A0(n1135), .A1(n1049), .B0(n1131), .Y(n1133) );
AO22XLTS U1158 ( .A0(n1373), .A1(n1372), .B0(ZERO_FLAG_EXP), .B1(n1049), .Y(
n721) );
OAI21XLTS U1159 ( .A0(n1591), .A1(n1382), .B0(n1085), .Y(n723) );
OAI21XLTS U1160 ( .A0(n1537), .A1(n1382), .B0(n1084), .Y(n724) );
OAI21XLTS U1161 ( .A0(n1578), .A1(n1382), .B0(n1082), .Y(n725) );
OAI21XLTS U1162 ( .A0(n1579), .A1(n1382), .B0(n1083), .Y(n726) );
OAI21XLTS U1163 ( .A0(n1535), .A1(n1093), .B0(n1075), .Y(n731) );
OAI21XLTS U1164 ( .A0(n1572), .A1(n1093), .B0(n1079), .Y(n732) );
OAI21XLTS U1165 ( .A0(n1536), .A1(n1093), .B0(n1088), .Y(n734) );
OAI21XLTS U1166 ( .A0(n1592), .A1(n1093), .B0(n1074), .Y(n735) );
OAI21XLTS U1167 ( .A0(n1534), .A1(n1093), .B0(n1089), .Y(n737) );
OAI21XLTS U1168 ( .A0(n1586), .A1(n1093), .B0(n1081), .Y(n738) );
OAI21XLTS U1169 ( .A0(n1533), .A1(n1093), .B0(n1078), .Y(n739) );
OAI21XLTS U1170 ( .A0(n1571), .A1(n1093), .B0(n1080), .Y(n740) );
OAI21XLTS U1171 ( .A0(n1575), .A1(n1093), .B0(n1076), .Y(n741) );
OAI21XLTS U1172 ( .A0(n1112), .A1(n1093), .B0(n1090), .Y(n742) );
OAI21XLTS U1173 ( .A0(n876), .A1(n1148), .B0(n1147), .Y(n743) );
OAI21XLTS U1174 ( .A0(n1570), .A1(n1148), .B0(n1141), .Y(n744) );
OAI21XLTS U1175 ( .A0(n1589), .A1(n1148), .B0(n1138), .Y(n745) );
OAI21XLTS U1176 ( .A0(n1577), .A1(n1148), .B0(n1139), .Y(n746) );
OAI21XLTS U1177 ( .A0(n1569), .A1(n1148), .B0(n1140), .Y(n747) );
OAI21XLTS U1178 ( .A0(n1532), .A1(n1148), .B0(n1144), .Y(n748) );
OAI21XLTS U1179 ( .A0(n1574), .A1(n1148), .B0(n1143), .Y(n749) );
OAI21XLTS U1180 ( .A0(n1573), .A1(n1148), .B0(n1142), .Y(n751) );
OAI21XLTS U1181 ( .A0(n1588), .A1(n1382), .B0(n1086), .Y(n752) );
OAI21XLTS U1182 ( .A0(n1585), .A1(n1093), .B0(n1087), .Y(n753) );
AO22XLTS U1183 ( .A0(n1317), .A1(busy), .B0(n1316), .B1(n924), .Y(n866) );
INVX3TS U1184 ( .A(n907), .Y(n1387) );
AOI22X1TS U1185 ( .A0(n1316), .A1(n1650), .B0(n1317), .B1(n924), .Y(n880) );
OR2X1TS U1186 ( .A(n907), .B(Shift_amount_SHT1_EWR[0]), .Y(n887) );
OR2X1TS U1187 ( .A(n908), .B(n1458), .Y(n888) );
OR2X1TS U1188 ( .A(shift_value_SHT2_EWR[4]), .B(n1427), .Y(n889) );
OR2X1TS U1189 ( .A(n875), .B(n1458), .Y(n890) );
OR3X1TS U1190 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[2]),
.C(n1547), .Y(n891) );
INVX2TS U1191 ( .A(n947), .Y(n948) );
INVX2TS U1192 ( .A(n888), .Y(n902) );
INVX2TS U1193 ( .A(n888), .Y(n903) );
INVX2TS U1194 ( .A(n1325), .Y(n1326) );
INVX2TS U1195 ( .A(n1428), .Y(n904) );
INVX2TS U1196 ( .A(n1428), .Y(n905) );
INVX2TS U1197 ( .A(Shift_reg_FLAGS_7[1]), .Y(n906) );
INVX2TS U1198 ( .A(n877), .Y(n907) );
INVX2TS U1199 ( .A(n878), .Y(n908) );
INVX2TS U1200 ( .A(left_right_SHT2), .Y(n909) );
INVX2TS U1201 ( .A(n1338), .Y(n911) );
CLKINVX3TS U1202 ( .A(n887), .Y(n913) );
INVX2TS U1203 ( .A(n948), .Y(n915) );
INVX2TS U1204 ( .A(n915), .Y(n916) );
OAI21XLTS U1205 ( .A0(n1579), .A1(n1073), .B0(n1071), .Y(n560) );
OAI211XLTS U1206 ( .A0(n1193), .A1(n946), .B0(n1192), .C0(n1191), .Y(n772)
);
BUFX4TS U1207 ( .A(n1374), .Y(n1512) );
INVX2TS U1208 ( .A(rst), .Y(n917) );
OAI211XLTS U1209 ( .A0(n987), .A1(n1096), .B0(n986), .C0(n985), .Y(n992) );
OAI21X2TS U1210 ( .A0(intDX_EWSW[26]), .A1(n1590), .B0(n984), .Y(n1096) );
INVX2TS U1211 ( .A(n885), .Y(n919) );
INVX2TS U1212 ( .A(n884), .Y(n920) );
INVX2TS U1213 ( .A(n1325), .Y(n921) );
INVX4TS U1214 ( .A(n1326), .Y(n922) );
NOR2X4TS U1215 ( .A(shift_value_SHT2_EWR[4]), .B(left_right_SHT2), .Y(n1455)
);
OAI21XLTS U1216 ( .A0(n1342), .A1(n910), .B0(n1263), .Y(n779) );
OAI21XLTS U1217 ( .A0(n1258), .A1(n910), .B0(n1236), .Y(n789) );
OAI211XLTS U1218 ( .A0(n1220), .A1(n910), .B0(n1219), .C0(n1218), .Y(n773)
);
OAI211XLTS U1219 ( .A0(n1215), .A1(n910), .B0(n1214), .C0(n1213), .Y(n774)
);
OAI211XLTS U1220 ( .A0(n1223), .A1(n910), .B0(n1211), .C0(n1210), .Y(n778)
);
OAI211XLTS U1221 ( .A0(n1261), .A1(n910), .B0(n1208), .C0(n1207), .Y(n777)
);
AOI221X1TS U1222 ( .A0(n1576), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1572), .C0(n1104), .Y(n1107) );
OAI21XLTS U1223 ( .A0(n1576), .A1(n1380), .B0(n1061), .Y(n570) );
OAI21XLTS U1224 ( .A0(n1576), .A1(n1093), .B0(n1092), .Y(n733) );
BUFX4TS U1225 ( .A(n1498), .Y(n1491) );
BUFX4TS U1226 ( .A(n1146), .Y(n1149) );
BUFX4TS U1227 ( .A(n1627), .Y(n1624) );
BUFX4TS U1228 ( .A(n1628), .Y(n1619) );
BUFX4TS U1229 ( .A(n1631), .Y(n1620) );
BUFX4TS U1230 ( .A(n1629), .Y(n1621) );
BUFX3TS U1231 ( .A(n917), .Y(n971) );
INVX2TS U1232 ( .A(n893), .Y(n924) );
AOI2BB2X2TS U1233 ( .B0(DmP_mant_SFG_SWR[11]), .B1(n1403), .A0N(OP_FLAG_SFG),
.A1N(DmP_mant_SFG_SWR[11]), .Y(n1399) );
AOI222X4TS U1234 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n911), .B0(n914), .B1(
DmP_mant_SHT1_SW[20]), .C0(n1254), .C1(DmP_mant_SHT1_SW[21]), .Y(n1266) );
INVX2TS U1235 ( .A(n898), .Y(n925) );
INVX2TS U1236 ( .A(n897), .Y(n926) );
BUFX4TS U1237 ( .A(n1651), .Y(n1409) );
INVX2TS U1238 ( .A(n900), .Y(n927) );
INVX2TS U1239 ( .A(n879), .Y(n928) );
INVX2TS U1240 ( .A(n883), .Y(n929) );
INVX2TS U1241 ( .A(n901), .Y(n930) );
INVX2TS U1242 ( .A(n882), .Y(n931) );
INVX2TS U1243 ( .A(n892), .Y(n932) );
INVX2TS U1244 ( .A(n881), .Y(n933) );
INVX2TS U1245 ( .A(n896), .Y(n934) );
INVX2TS U1246 ( .A(n895), .Y(n935) );
INVX2TS U1247 ( .A(n894), .Y(n936) );
INVX2TS U1248 ( .A(n899), .Y(n937) );
AOI211X1TS U1249 ( .A0(n1176), .A1(n1175), .B0(Raw_mant_NRM_SWR[25]), .C0(
Raw_mant_NRM_SWR[24]), .Y(n1182) );
INVX2TS U1250 ( .A(intDY_EWSW[23]), .Y(n938) );
INVX2TS U1251 ( .A(n890), .Y(n939) );
INVX2TS U1252 ( .A(n890), .Y(n940) );
INVX2TS U1253 ( .A(n889), .Y(n941) );
INVX2TS U1254 ( .A(n889), .Y(n942) );
INVX2TS U1255 ( .A(n891), .Y(n943) );
INVX2TS U1256 ( .A(n891), .Y(n944) );
INVX2TS U1257 ( .A(n1184), .Y(n945) );
INVX4TS U1258 ( .A(n1498), .Y(n1493) );
INVX4TS U1259 ( .A(n1498), .Y(n1497) );
INVX3TS U1260 ( .A(n1651), .Y(n1402) );
INVX4TS U1261 ( .A(n1374), .Y(n1509) );
INVX4TS U1262 ( .A(n1374), .Y(n1514) );
INVX2TS U1263 ( .A(n1653), .Y(n947) );
AOI222X4TS U1264 ( .A0(Data_array_SWR[24]), .A1(n1472), .B0(
Data_array_SWR[20]), .B1(n944), .C0(Data_array_SWR[16]), .C1(n942),
.Y(n1415) );
OAI211XLTS U1265 ( .A0(n1248), .A1(n945), .B0(n1247), .C0(n1246), .Y(n782)
);
AOI222X1TS U1266 ( .A0(n1430), .A1(n909), .B0(Data_array_SWR[9]), .B1(n903),
.C0(n1429), .C1(n1454), .Y(n1488) );
AOI222X1TS U1267 ( .A0(n1430), .A1(left_right_SHT2), .B0(Data_array_SWR[9]),
.B1(n940), .C0(n1429), .C1(n1455), .Y(n1499) );
AOI32X1TS U1268 ( .A0(n1592), .A1(n1030), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1536), .Y(n1031) );
AOI221X1TS U1269 ( .A0(n1592), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1536), .C0(n1103), .Y(n1108) );
AOI221X1TS U1270 ( .A0(n1591), .A1(intDX_EWSW[30]), .B0(intDX_EWSW[17]),
.B1(n1587), .C0(n1102), .Y(n1109) );
AOI221X1TS U1271 ( .A0(intDX_EWSW[30]), .A1(n1591), .B0(intDX_EWSW[29]),
.B1(n1537), .C0(n989), .Y(n991) );
AOI221X1TS U1272 ( .A0(n876), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]), .B1(
n1112), .C0(n1111), .Y(n1117) );
AOI221X1TS U1273 ( .A0(n1573), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1568), .C0(n1120), .Y(n1125) );
AOI221X1TS U1274 ( .A0(n1533), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1586), .C0(n1114), .Y(n1115) );
AOI221X1TS U1275 ( .A0(n1575), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1571), .C0(n1113), .Y(n1116) );
OAI31XLTS U1276 ( .A0(n1373), .A1(n1135), .A2(n1382), .B0(n1134), .Y(n720)
);
NOR2X2TS U1277 ( .A(n957), .B(DMP_EXP_EWSW[23]), .Y(n1358) );
XNOR2X2TS U1278 ( .A(DMP_exp_NRM2_EW[0]), .B(n1288), .Y(n1308) );
XNOR2X2TS U1279 ( .A(DMP_exp_NRM2_EW[6]), .B(n979), .Y(n1310) );
XNOR2X2TS U1280 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J49_123_3372_n4), .Y(
n1309) );
NOR2X4TS U1281 ( .A(shift_value_SHT2_EWR[4]), .B(n875), .Y(n1454) );
BUFX4TS U1282 ( .A(n972), .Y(n1639) );
BUFX4TS U1283 ( .A(n971), .Y(n1625) );
BUFX4TS U1284 ( .A(n972), .Y(n1623) );
BUFX4TS U1285 ( .A(n971), .Y(n1641) );
BUFX4TS U1286 ( .A(n972), .Y(n1640) );
BUFX4TS U1287 ( .A(n971), .Y(n1643) );
BUFX3TS U1288 ( .A(n917), .Y(n972) );
AOI2BB2X2TS U1289 ( .B0(DmP_mant_SFG_SWR[10]), .B1(n1407), .A0N(n1407),
.A1N(DmP_mant_SFG_SWR[10]), .Y(intadd_52_B_2_) );
NOR2XLTS U1290 ( .A(n1007), .B(intDY_EWSW[10]), .Y(n1008) );
NOR2X4TS U1291 ( .A(n1412), .B(n1411), .Y(n1428) );
OAI2BB1X2TS U1292 ( .A0N(n1278), .A1N(n1277), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1411) );
AOI22X2TS U1293 ( .A0(DmP_mant_SFG_SWR[9]), .A1(n1405), .B0(n1403), .B1(n963), .Y(intadd_52_B_1_) );
AOI22X2TS U1294 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n1405), .B0(n1403), .B1(n966), .Y(intadd_53_B_1_) );
BUFX4TS U1295 ( .A(OP_FLAG_SFG), .Y(n1403) );
AOI222X4TS U1296 ( .A0(DMP_SFG[5]), .A1(n920), .B0(DMP_SFG[5]), .B1(n1284),
.C0(n920), .C1(n1284), .Y(intadd_52_CI) );
AOI222X4TS U1297 ( .A0(DMP_SFG[9]), .A1(n1399), .B0(DMP_SFG[9]), .B1(n1287),
.C0(n1399), .C1(n1287), .Y(intadd_51_B_0_) );
AOI222X1TS U1298 ( .A0(n1449), .A1(n909), .B0(n903), .B1(Data_array_SWR[5]),
.C0(n1450), .C1(n1454), .Y(n1483) );
AOI222X1TS U1299 ( .A0(n1449), .A1(n908), .B0(Data_array_SWR[5]), .B1(n940),
.C0(n1450), .C1(n1455), .Y(n1503) );
AOI222X1TS U1300 ( .A0(n1457), .A1(n875), .B0(n903), .B1(Data_array_SWR[4]),
.C0(n1456), .C1(n1454), .Y(n1482) );
AOI222X1TS U1301 ( .A0(n1457), .A1(n908), .B0(Data_array_SWR[4]), .B1(n940),
.C0(n1456), .C1(n1455), .Y(n1504) );
AOI222X1TS U1302 ( .A0(n1439), .A1(n875), .B0(Data_array_SWR[7]), .B1(n903),
.C0(n1438), .C1(n1454), .Y(n1485) );
AOI222X1TS U1303 ( .A0(n1444), .A1(n909), .B0(Data_array_SWR[6]), .B1(n903),
.C0(n1443), .C1(n1454), .Y(n1484) );
AOI222X1TS U1304 ( .A0(n1444), .A1(left_right_SHT2), .B0(Data_array_SWR[6]),
.B1(n940), .C0(n1443), .C1(n1455), .Y(n1502) );
OAI21XLTS U1305 ( .A0(n1334), .A1(n946), .B0(n1231), .Y(n787) );
AOI222X4TS U1306 ( .A0(Data_array_SWR[23]), .A1(n1472), .B0(
Data_array_SWR[19]), .B1(n944), .C0(Data_array_SWR[15]), .C1(n942),
.Y(n1419) );
AOI222X1TS U1307 ( .A0(n1435), .A1(left_right_SHT2), .B0(Data_array_SWR[8]),
.B1(n940), .C0(n1434), .C1(n1455), .Y(n1500) );
AOI221X1TS U1308 ( .A0(n1590), .A1(intDX_EWSW[26]), .B0(intDX_EWSW[27]),
.B1(n1579), .C0(n1096), .Y(n1100) );
NOR2X2TS U1309 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1564), .Y(n1314) );
OAI21X2TS U1310 ( .A0(intDX_EWSW[18]), .A1(n1592), .B0(n1030), .Y(n1103) );
NOR3X1TS U1311 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1304) );
OAI211XLTS U1312 ( .A0(n1245), .A1(n945), .B0(n1244), .C0(n1243), .Y(n784)
);
NOR2X4TS U1313 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1447) );
OAI21XLTS U1314 ( .A0(intDX_EWSW[1]), .A1(n1588), .B0(intDX_EWSW[0]), .Y(
n995) );
OAI211XLTS U1315 ( .A0(intDX_EWSW[8]), .A1(n1589), .B0(n1009), .C0(n1012),
.Y(n1023) );
OAI21XLTS U1316 ( .A0(intDX_EWSW[13]), .A1(n1571), .B0(intDX_EWSW[12]), .Y(
n1006) );
OAI21XLTS U1317 ( .A0(intDX_EWSW[21]), .A1(n1572), .B0(intDX_EWSW[20]), .Y(
n1027) );
OAI21XLTS U1318 ( .A0(intDX_EWSW[3]), .A1(n1568), .B0(intDX_EWSW[2]), .Y(
n998) );
OAI211XLTS U1319 ( .A0(n1568), .A1(intDX_EWSW[3]), .B0(n997), .C0(n996), .Y(
n1000) );
INVX2TS U1320 ( .A(n1613), .Y(n949) );
NOR2XLTS U1321 ( .A(n1560), .B(intDX_EWSW[11]), .Y(n1007) );
OAI21XLTS U1322 ( .A0(intDX_EWSW[15]), .A1(n1586), .B0(intDX_EWSW[14]), .Y(
n1015) );
NOR2XLTS U1323 ( .A(n1028), .B(intDY_EWSW[16]), .Y(n1029) );
NOR2XLTS U1324 ( .A(n1308), .B(exp_rslt_NRM2_EW1[1]), .Y(n976) );
OAI21XLTS U1325 ( .A0(intDX_EWSW[23]), .A1(n938), .B0(intDX_EWSW[22]), .Y(
n1034) );
NOR2XLTS U1326 ( .A(n977), .B(n1309), .Y(n978) );
AOI31XLTS U1327 ( .A0(n1168), .A1(Raw_mant_NRM_SWR[16]), .A2(n1546), .B0(
n1167), .Y(n1169) );
OAI21XLTS U1328 ( .A0(n1518), .A1(n1338), .B0(n1332), .Y(n1333) );
OAI21XLTS U1329 ( .A0(n1523), .A1(n1264), .B0(n1259), .Y(n1260) );
OAI21XLTS U1330 ( .A0(n1596), .A1(n1264), .B0(n1224), .Y(n1225) );
OAI211XLTS U1331 ( .A0(n1351), .A1(n1550), .B0(n1290), .C0(n1161), .Y(n767)
);
OAI21XLTS U1332 ( .A0(n1534), .A1(n1380), .B0(n1053), .Y(n578) );
OAI21XLTS U1333 ( .A0(n1587), .A1(n1093), .B0(n1077), .Y(n736) );
OAI21XLTS U1334 ( .A0(n1568), .A1(n1148), .B0(n1136), .Y(n750) );
OAI211XLTS U1335 ( .A0(n1215), .A1(n945), .B0(n1198), .C0(n1197), .Y(n776)
);
OAI21XLTS U1336 ( .A0(n1331), .A1(n910), .B0(n1227), .Y(n792) );
NOR2XLTS U1337 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n969) );
AOI32X4TS U1338 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n969), .B1(n1564), .Y(n1317)
);
INVX2TS U1339 ( .A(n1317), .Y(n1316) );
INVX1TS U1340 ( .A(DMP_SFG[3]), .Y(intadd_53_A_1_) );
INVX1TS U1341 ( .A(DMP_SFG[4]), .Y(intadd_53_A_2_) );
BUFX3TS U1342 ( .A(n917), .Y(n1632) );
CLKBUFX2TS U1343 ( .A(n918), .Y(n970) );
BUFX3TS U1344 ( .A(n972), .Y(n1633) );
BUFX3TS U1345 ( .A(n971), .Y(n1634) );
BUFX3TS U1346 ( .A(n972), .Y(n1635) );
BUFX3TS U1347 ( .A(n971), .Y(n1636) );
BUFX3TS U1348 ( .A(n972), .Y(n1637) );
BUFX3TS U1349 ( .A(n971), .Y(n1638) );
BUFX3TS U1350 ( .A(n972), .Y(n1626) );
BUFX3TS U1351 ( .A(n917), .Y(n1629) );
BUFX3TS U1352 ( .A(n917), .Y(n1630) );
BUFX3TS U1353 ( .A(n918), .Y(n1631) );
BUFX3TS U1354 ( .A(n971), .Y(n1645) );
BUFX3TS U1355 ( .A(n918), .Y(n1628) );
BUFX3TS U1356 ( .A(n972), .Y(n1622) );
BUFX3TS U1357 ( .A(n972), .Y(n1649) );
BUFX3TS U1358 ( .A(n971), .Y(n1618) );
BUFX3TS U1359 ( .A(n918), .Y(n1627) );
BUFX3TS U1360 ( .A(n971), .Y(n1646) );
BUFX3TS U1361 ( .A(n972), .Y(n1642) );
BUFX3TS U1362 ( .A(n972), .Y(n1648) );
BUFX3TS U1363 ( .A(n971), .Y(n1644) );
BUFX3TS U1364 ( .A(n971), .Y(n1647) );
INVX4TS U1365 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1471) );
AO22XLTS U1366 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1471), .B1(zero_flag), .Y(n552) );
INVX2TS U1367 ( .A(DP_OP_15J49_123_3372_n4), .Y(n973) );
NAND2X1TS U1368 ( .A(n1581), .B(n973), .Y(n979) );
INVX2TS U1369 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n975) );
INVX2TS U1370 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n974) );
INVX2TS U1371 ( .A(n979), .Y(n980) );
NAND2X1TS U1372 ( .A(n1580), .B(n980), .Y(n1275) );
XNOR2X1TS U1373 ( .A(DMP_exp_NRM2_EW[7]), .B(n1275), .Y(n1271) );
NAND2X2TS U1374 ( .A(n1280), .B(Shift_reg_FLAGS_7[0]), .Y(n1311) );
OA22X1TS U1375 ( .A0(n1311), .A1(exp_rslt_NRM2_EW1[4]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[27]), .Y(n757) );
OA22X1TS U1376 ( .A0(n1311), .A1(exp_rslt_NRM2_EW1[1]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[24]), .Y(n760) );
OA22X1TS U1377 ( .A0(n1311), .A1(exp_rslt_NRM2_EW1[2]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[25]), .Y(n759) );
OA22X1TS U1378 ( .A0(n1311), .A1(exp_rslt_NRM2_EW1[3]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[26]), .Y(n758) );
INVX4TS U1379 ( .A(n1376), .Y(busy) );
OAI21XLTS U1380 ( .A0(n947), .A1(n875), .B0(n1387), .Y(n829) );
NOR2X1TS U1381 ( .A(n1584), .B(intDX_EWSW[25]), .Y(n1041) );
AOI22X1TS U1382 ( .A0(intDX_EWSW[25]), .A1(n1584), .B0(intDX_EWSW[24]), .B1(
n983), .Y(n987) );
NOR2X1TS U1383 ( .A(n1591), .B(intDX_EWSW[30]), .Y(n990) );
NOR2X1TS U1384 ( .A(n1537), .B(intDX_EWSW[29]), .Y(n988) );
AOI211X1TS U1385 ( .A0(intDY_EWSW[28]), .A1(n1559), .B0(n990), .C0(n988),
.Y(n1040) );
NOR3X1TS U1386 ( .A(n1559), .B(n988), .C(intDY_EWSW[28]), .Y(n989) );
AOI2BB2X1TS U1387 ( .B0(n992), .B1(n1040), .A0N(n991), .A1N(n990), .Y(n1045)
);
NOR2X1TS U1388 ( .A(n1587), .B(intDX_EWSW[17]), .Y(n1028) );
INVX2TS U1389 ( .A(intDY_EWSW[11]), .Y(n1112) );
OAI22X1TS U1390 ( .A0(n876), .A1(intDX_EWSW[10]), .B0(n1112), .B1(
intDX_EWSW[11]), .Y(n1111) );
INVX2TS U1391 ( .A(n1111), .Y(n1012) );
OAI2BB1X1TS U1392 ( .A0N(n1549), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n993) );
OAI22X1TS U1393 ( .A0(intDY_EWSW[4]), .A1(n993), .B0(n1549), .B1(
intDY_EWSW[5]), .Y(n1004) );
OAI2BB1X1TS U1394 ( .A0N(n1528), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n994) );
OAI22X1TS U1395 ( .A0(intDY_EWSW[6]), .A1(n994), .B0(n1528), .B1(
intDY_EWSW[7]), .Y(n1003) );
OAI2BB2XLTS U1396 ( .B0(intDY_EWSW[0]), .B1(n995), .A0N(intDX_EWSW[1]),
.A1N(n1588), .Y(n997) );
AOI222X1TS U1397 ( .A0(intDY_EWSW[4]), .A1(n1524), .B0(n1000), .B1(n999),
.C0(intDY_EWSW[5]), .C1(n1549), .Y(n1002) );
AOI22X1TS U1398 ( .A0(intDY_EWSW[7]), .A1(n1528), .B0(intDY_EWSW[6]), .B1(
n1553), .Y(n1001) );
OAI32X1TS U1399 ( .A0(n1004), .A1(n1003), .A2(n1002), .B0(n1001), .B1(n1003),
.Y(n1022) );
OA22X1TS U1400 ( .A0(n1533), .A1(intDX_EWSW[14]), .B0(n1586), .B1(
intDX_EWSW[15]), .Y(n1019) );
OAI2BB2XLTS U1401 ( .B0(intDY_EWSW[12]), .B1(n1006), .A0N(intDX_EWSW[13]),
.A1N(n1571), .Y(n1018) );
AOI22X1TS U1402 ( .A0(intDX_EWSW[11]), .A1(n1560), .B0(intDX_EWSW[10]), .B1(
n1008), .Y(n1014) );
AOI21X1TS U1403 ( .A0(n1011), .A1(n1010), .B0(n1021), .Y(n1013) );
OAI2BB2XLTS U1404 ( .B0(n1014), .B1(n1021), .A0N(n1013), .A1N(n1012), .Y(
n1017) );
OAI2BB2XLTS U1405 ( .B0(intDY_EWSW[14]), .B1(n1015), .A0N(intDX_EWSW[15]),
.A1N(n1586), .Y(n1016) );
AOI211X1TS U1406 ( .A0(n1019), .A1(n1018), .B0(n1017), .C0(n1016), .Y(n1020)
);
OAI31X1TS U1407 ( .A0(n1023), .A1(n1022), .A2(n1021), .B0(n1020), .Y(n1026)
);
OA22X1TS U1408 ( .A0(n1535), .A1(intDX_EWSW[22]), .B0(n938), .B1(
intDX_EWSW[23]), .Y(n1038) );
OAI2BB2XLTS U1409 ( .B0(intDY_EWSW[20]), .B1(n1027), .A0N(intDX_EWSW[21]),
.A1N(n1572), .Y(n1037) );
AOI22X1TS U1410 ( .A0(intDX_EWSW[17]), .A1(n1587), .B0(intDX_EWSW[16]), .B1(
n1029), .Y(n1032) );
OAI32X1TS U1411 ( .A0(n1103), .A1(n1033), .A2(n1032), .B0(n1031), .B1(n1033),
.Y(n1036) );
AOI211X1TS U1412 ( .A0(n1038), .A1(n1037), .B0(n1036), .C0(n1035), .Y(n1043)
);
NAND4BBX1TS U1413 ( .AN(n1096), .BN(n1041), .C(n1040), .D(n1039), .Y(n1042)
);
AOI32X1TS U1414 ( .A0(n1045), .A1(n1044), .A2(n1043), .B0(n1042), .B1(n1045),
.Y(n1046) );
AND2X2TS U1415 ( .A(Shift_reg_FLAGS_7_6), .B(n1046), .Y(n1146) );
INVX2TS U1416 ( .A(n1146), .Y(n1131) );
INVX2TS U1417 ( .A(Shift_reg_FLAGS_7_6), .Y(n1049) );
BUFX3TS U1418 ( .A(n1049), .Y(n1091) );
AOI22X1TS U1419 ( .A0(intDX_EWSW[0]), .A1(n1047), .B0(DmP_EXP_EWSW[0]), .B1(
n1091), .Y(n1048) );
BUFX3TS U1420 ( .A(n1145), .Y(n1132) );
AOI22X1TS U1421 ( .A0(intDX_EWSW[14]), .A1(n1047), .B0(DmP_EXP_EWSW[14]),
.B1(n1132), .Y(n1050) );
BUFX3TS U1422 ( .A(n1145), .Y(n1315) );
AOI22X1TS U1423 ( .A0(intDX_EWSW[22]), .A1(n1047), .B0(DmP_EXP_EWSW[22]),
.B1(n1315), .Y(n1051) );
AOI22X1TS U1424 ( .A0(intDX_EWSW[19]), .A1(n1047), .B0(DmP_EXP_EWSW[19]),
.B1(n1315), .Y(n1052) );
AOI22X1TS U1425 ( .A0(intDX_EWSW[16]), .A1(n873), .B0(DmP_EXP_EWSW[16]),
.B1(n1315), .Y(n1053) );
AOI22X1TS U1426 ( .A0(intDX_EWSW[5]), .A1(n873), .B0(DmP_EXP_EWSW[5]), .B1(
n1132), .Y(n1054) );
AOI22X1TS U1427 ( .A0(intDX_EWSW[6]), .A1(n873), .B0(DmP_EXP_EWSW[6]), .B1(
n1132), .Y(n1055) );
AOI22X1TS U1428 ( .A0(intDX_EWSW[4]), .A1(n873), .B0(DmP_EXP_EWSW[4]), .B1(
n1132), .Y(n1056) );
AOI22X1TS U1429 ( .A0(intDX_EWSW[17]), .A1(n873), .B0(DmP_EXP_EWSW[17]),
.B1(n1315), .Y(n1057) );
AOI22X1TS U1430 ( .A0(intDX_EWSW[21]), .A1(n873), .B0(DmP_EXP_EWSW[21]),
.B1(n1315), .Y(n1058) );
AOI22X1TS U1431 ( .A0(intDX_EWSW[13]), .A1(n873), .B0(DmP_EXP_EWSW[13]),
.B1(n1315), .Y(n1059) );
AOI22X1TS U1432 ( .A0(intDX_EWSW[10]), .A1(n873), .B0(DmP_EXP_EWSW[10]),
.B1(n1091), .Y(n1060) );
AOI22X1TS U1433 ( .A0(intDX_EWSW[20]), .A1(n873), .B0(DmP_EXP_EWSW[20]),
.B1(n1315), .Y(n1061) );
AOI22X1TS U1434 ( .A0(intDX_EWSW[9]), .A1(n873), .B0(DmP_EXP_EWSW[9]), .B1(
n1132), .Y(n1062) );
BUFX3TS U1435 ( .A(n873), .Y(n1150) );
AOI22X1TS U1436 ( .A0(intDX_EWSW[7]), .A1(n1150), .B0(DmP_EXP_EWSW[7]), .B1(
n1132), .Y(n1063) );
AOI22X1TS U1437 ( .A0(intDX_EWSW[18]), .A1(n1150), .B0(DmP_EXP_EWSW[18]),
.B1(n1315), .Y(n1064) );
AOI22X1TS U1438 ( .A0(intDX_EWSW[1]), .A1(n1150), .B0(DmP_EXP_EWSW[1]), .B1(
n1132), .Y(n1065) );
AOI22X1TS U1439 ( .A0(intDX_EWSW[12]), .A1(n1150), .B0(DmP_EXP_EWSW[12]),
.B1(n1132), .Y(n1066) );
AOI22X1TS U1440 ( .A0(intDX_EWSW[8]), .A1(n1150), .B0(DmP_EXP_EWSW[8]), .B1(
n1132), .Y(n1067) );
AOI22X1TS U1441 ( .A0(intDX_EWSW[2]), .A1(n1150), .B0(DmP_EXP_EWSW[2]), .B1(
n1132), .Y(n1068) );
AOI22X1TS U1442 ( .A0(intDX_EWSW[11]), .A1(n1150), .B0(DmP_EXP_EWSW[11]),
.B1(n1132), .Y(n1069) );
AOI22X1TS U1443 ( .A0(intDX_EWSW[3]), .A1(n1150), .B0(DmP_EXP_EWSW[3]), .B1(
n1132), .Y(n1070) );
AOI22X1TS U1444 ( .A0(DmP_EXP_EWSW[27]), .A1(n1315), .B0(intDX_EWSW[27]),
.B1(n1150), .Y(n1071) );
AOI22X1TS U1445 ( .A0(intDX_EWSW[15]), .A1(n1047), .B0(DmP_EXP_EWSW[15]),
.B1(n1315), .Y(n1072) );
BUFX3TS U1446 ( .A(n1146), .Y(n1137) );
AOI22X1TS U1447 ( .A0(intDX_EWSW[18]), .A1(n1149), .B0(DMP_EXP_EWSW[18]),
.B1(n1091), .Y(n1074) );
AOI22X1TS U1448 ( .A0(intDX_EWSW[22]), .A1(n1149), .B0(DMP_EXP_EWSW[22]),
.B1(n1091), .Y(n1075) );
AOI22X1TS U1449 ( .A0(intDX_EWSW[12]), .A1(n1149), .B0(DMP_EXP_EWSW[12]),
.B1(n1145), .Y(n1076) );
AOI22X1TS U1450 ( .A0(intDX_EWSW[17]), .A1(n1137), .B0(DMP_EXP_EWSW[17]),
.B1(n1091), .Y(n1077) );
AOI22X1TS U1451 ( .A0(intDX_EWSW[14]), .A1(n1149), .B0(DMP_EXP_EWSW[14]),
.B1(n1145), .Y(n1078) );
AOI22X1TS U1452 ( .A0(intDX_EWSW[21]), .A1(n1149), .B0(DMP_EXP_EWSW[21]),
.B1(n1091), .Y(n1079) );
AOI22X1TS U1453 ( .A0(intDX_EWSW[13]), .A1(n1149), .B0(DMP_EXP_EWSW[13]),
.B1(n1145), .Y(n1080) );
AOI22X1TS U1454 ( .A0(intDX_EWSW[15]), .A1(n1149), .B0(DMP_EXP_EWSW[15]),
.B1(n1145), .Y(n1081) );
AOI22X1TS U1455 ( .A0(intDX_EWSW[28]), .A1(n1137), .B0(DMP_EXP_EWSW[28]),
.B1(n1091), .Y(n1082) );
AOI22X1TS U1456 ( .A0(n937), .A1(n1315), .B0(intDX_EWSW[27]), .B1(n1137),
.Y(n1083) );
AOI22X1TS U1457 ( .A0(intDX_EWSW[29]), .A1(n1137), .B0(DMP_EXP_EWSW[29]),
.B1(n1091), .Y(n1084) );
AOI22X1TS U1458 ( .A0(intDX_EWSW[30]), .A1(n1149), .B0(DMP_EXP_EWSW[30]),
.B1(n1091), .Y(n1085) );
AOI22X1TS U1459 ( .A0(intDX_EWSW[1]), .A1(n1149), .B0(DMP_EXP_EWSW[1]), .B1(
n1049), .Y(n1086) );
AOI22X1TS U1460 ( .A0(intDX_EWSW[0]), .A1(n1137), .B0(DMP_EXP_EWSW[0]), .B1(
n1049), .Y(n1087) );
AOI22X1TS U1461 ( .A0(intDX_EWSW[19]), .A1(n1137), .B0(DMP_EXP_EWSW[19]),
.B1(n1091), .Y(n1088) );
AOI22X1TS U1462 ( .A0(intDX_EWSW[16]), .A1(n1137), .B0(DMP_EXP_EWSW[16]),
.B1(n1091), .Y(n1089) );
AOI22X1TS U1463 ( .A0(intDX_EWSW[11]), .A1(n1149), .B0(DMP_EXP_EWSW[11]),
.B1(n1091), .Y(n1090) );
AOI22X1TS U1464 ( .A0(intDX_EWSW[20]), .A1(n1137), .B0(DMP_EXP_EWSW[20]),
.B1(n1091), .Y(n1092) );
AOI22X1TS U1465 ( .A0(DMP_EXP_EWSW[23]), .A1(n1315), .B0(intDX_EWSW[23]),
.B1(n1137), .Y(n1094) );
OAI22X1TS U1466 ( .A0(n1588), .A1(intDX_EWSW[1]), .B0(n1584), .B1(
intDX_EWSW[25]), .Y(n1095) );
AOI221X1TS U1467 ( .A0(n1588), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[25]), .B1(
n1584), .C0(n1095), .Y(n1101) );
OAI22X1TS U1468 ( .A0(n1578), .A1(intDX_EWSW[28]), .B0(n1537), .B1(
intDX_EWSW[29]), .Y(n1097) );
AOI221X1TS U1469 ( .A0(n1578), .A1(intDX_EWSW[28]), .B0(intDX_EWSW[29]),
.B1(n1537), .C0(n1097), .Y(n1099) );
AOI2BB2XLTS U1470 ( .B0(intDX_EWSW[7]), .B1(n1577), .A0N(n1577), .A1N(
intDX_EWSW[7]), .Y(n1098) );
NAND4XLTS U1471 ( .A(n1101), .B(n1100), .C(n1099), .D(n1098), .Y(n1130) );
OAI22X1TS U1472 ( .A0(n1591), .A1(intDX_EWSW[30]), .B0(n1587), .B1(
intDX_EWSW[17]), .Y(n1102) );
OAI22X1TS U1473 ( .A0(n1576), .A1(intDX_EWSW[20]), .B0(n1572), .B1(
intDX_EWSW[21]), .Y(n1104) );
OAI22X1TS U1474 ( .A0(n1535), .A1(intDX_EWSW[22]), .B0(n938), .B1(
intDX_EWSW[23]), .Y(n1105) );
NAND4XLTS U1475 ( .A(n1109), .B(n1108), .C(n1107), .D(n1106), .Y(n1129) );
OAI22X1TS U1476 ( .A0(n1519), .A1(intDX_EWSW[24]), .B0(n1570), .B1(
intDX_EWSW[9]), .Y(n1110) );
AOI221X1TS U1477 ( .A0(n1519), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1570), .C0(n1110), .Y(n1118) );
OAI22X1TS U1478 ( .A0(n1575), .A1(intDX_EWSW[12]), .B0(n1571), .B1(
intDX_EWSW[13]), .Y(n1113) );
OAI22X1TS U1479 ( .A0(n1533), .A1(intDX_EWSW[14]), .B0(n1586), .B1(
intDX_EWSW[15]), .Y(n1114) );
NAND4XLTS U1480 ( .A(n1118), .B(n1117), .C(n1116), .D(n1115), .Y(n1128) );
OAI22X1TS U1481 ( .A0(n1534), .A1(intDX_EWSW[16]), .B0(n1585), .B1(
intDX_EWSW[0]), .Y(n1119) );
AOI221X1TS U1482 ( .A0(n1534), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n1585), .C0(n1119), .Y(n1126) );
OAI22X1TS U1483 ( .A0(n1573), .A1(intDX_EWSW[2]), .B0(n1568), .B1(
intDX_EWSW[3]), .Y(n1120) );
OAI22X1TS U1484 ( .A0(n1574), .A1(intDX_EWSW[4]), .B0(n1532), .B1(
intDX_EWSW[5]), .Y(n1121) );
AOI221X1TS U1485 ( .A0(n1574), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1532), .C0(n1121), .Y(n1124) );
OAI22X1TS U1486 ( .A0(n1589), .A1(intDX_EWSW[8]), .B0(n1569), .B1(
intDX_EWSW[6]), .Y(n1122) );
AOI221X1TS U1487 ( .A0(n1589), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1569), .C0(n1122), .Y(n1123) );
NAND4XLTS U1488 ( .A(n1126), .B(n1125), .C(n1124), .D(n1123), .Y(n1127) );
NOR4X1TS U1489 ( .A(n1130), .B(n1129), .C(n1128), .D(n1127), .Y(n1373) );
CLKXOR2X2TS U1490 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1371) );
INVX2TS U1491 ( .A(n1371), .Y(n1135) );
AOI22X1TS U1492 ( .A0(intDX_EWSW[31]), .A1(n1133), .B0(SIGN_FLAG_EXP), .B1(
n1132), .Y(n1134) );
INVX2TS U1493 ( .A(n873), .Y(n1148) );
AOI22X1TS U1494 ( .A0(intDX_EWSW[3]), .A1(n1137), .B0(DMP_EXP_EWSW[3]), .B1(
n1145), .Y(n1136) );
AOI22X1TS U1495 ( .A0(intDX_EWSW[8]), .A1(n1137), .B0(DMP_EXP_EWSW[8]), .B1(
n1145), .Y(n1138) );
AOI22X1TS U1496 ( .A0(intDX_EWSW[7]), .A1(n1149), .B0(DMP_EXP_EWSW[7]), .B1(
n1145), .Y(n1139) );
AOI22X1TS U1497 ( .A0(intDX_EWSW[6]), .A1(n1149), .B0(DMP_EXP_EWSW[6]), .B1(
n1145), .Y(n1140) );
AOI22X1TS U1498 ( .A0(intDX_EWSW[9]), .A1(n1149), .B0(DMP_EXP_EWSW[9]), .B1(
n1145), .Y(n1141) );
AOI22X1TS U1499 ( .A0(intDX_EWSW[2]), .A1(n1149), .B0(DMP_EXP_EWSW[2]), .B1(
n1145), .Y(n1142) );
AOI22X1TS U1500 ( .A0(intDX_EWSW[4]), .A1(n1149), .B0(DMP_EXP_EWSW[4]), .B1(
n1145), .Y(n1143) );
AOI22X1TS U1501 ( .A0(intDX_EWSW[5]), .A1(n1146), .B0(DMP_EXP_EWSW[5]), .B1(
n1145), .Y(n1144) );
AOI22X1TS U1502 ( .A0(intDX_EWSW[10]), .A1(n1146), .B0(DMP_EXP_EWSW[10]),
.B1(n1145), .Y(n1147) );
AOI222X1TS U1503 ( .A0(n1150), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1049), .C0(intDY_EWSW[23]), .C1(n1137), .Y(n1151) );
INVX2TS U1504 ( .A(n1151), .Y(n564) );
NAND2X2TS U1505 ( .A(n906), .B(n916), .Y(n1351) );
NOR2BX2TS U1506 ( .AN(n1304), .B(n1303), .Y(n1168) );
NOR2BX1TS U1507 ( .AN(n1168), .B(Raw_mant_NRM_SWR[18]), .Y(n1291) );
NOR2BX1TS U1508 ( .AN(n1291), .B(n1292), .Y(n1165) );
NOR2X2TS U1509 ( .A(Raw_mant_NRM_SWR[13]), .B(n1293), .Y(n1177) );
NOR2X2TS U1510 ( .A(Raw_mant_NRM_SWR[12]), .B(n1170), .Y(n1298) );
NAND2X1TS U1511 ( .A(n1298), .B(n1525), .Y(n1152) );
NOR2X1TS U1512 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[5]), .Y(n1154)
);
NOR3X1TS U1513 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .C(n1152),
.Y(n1155) );
OAI22X1TS U1514 ( .A0(n1153), .A1(n1152), .B0(n1154), .B1(n1162), .Y(n1160)
);
NOR2X1TS U1515 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1157)
);
NOR2X2TS U1516 ( .A(Raw_mant_NRM_SWR[6]), .B(n1162), .Y(n1299) );
NAND2X1TS U1517 ( .A(n1299), .B(n1154), .Y(n1158) );
OAI21X1TS U1518 ( .A0(n1157), .A1(n1158), .B0(n1156), .Y(n1181) );
INVX2TS U1519 ( .A(n1158), .Y(n1300) );
OAI31X1TS U1520 ( .A0(n1160), .A1(n1181), .A2(n1159), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1290) );
NAND3XLTS U1521 ( .A(n947), .B(Shift_amount_SHT1_EWR[4]), .C(n1387), .Y(
n1161) );
INVX2TS U1522 ( .A(n1162), .Y(n1172) );
AOI22X1TS U1523 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1168), .B0(n1298), .B1(
Raw_mant_NRM_SWR[10]), .Y(n1178) );
OAI32X1TS U1524 ( .A0(Raw_mant_NRM_SWR[3]), .A1(Raw_mant_NRM_SWR[1]), .A2(
n1529), .B0(n1551), .B1(Raw_mant_NRM_SWR[3]), .Y(n1163) );
NAND2X1TS U1525 ( .A(Raw_mant_NRM_SWR[12]), .B(n1177), .Y(n1295) );
NAND2X1TS U1526 ( .A(Raw_mant_NRM_SWR[14]), .B(n1165), .Y(n1183) );
AOI32X1TS U1527 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1515), .A2(n1548), .B0(
Raw_mant_NRM_SWR[22]), .B1(n1515), .Y(n1166) );
OAI31X1TS U1528 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n1170), .A2(n1530), .B0(
n1169), .Y(n1171) );
NAND2X2TS U1529 ( .A(n907), .B(n1187), .Y(n1338) );
NOR2BX1TS U1530 ( .AN(Shift_amount_SHT1_EWR[0]), .B(Shift_reg_FLAGS_7[1]),
.Y(n1194) );
BUFX3TS U1531 ( .A(n1194), .Y(n1335) );
AOI22X1TS U1532 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n912), .B0(n1335), .B1(n936), .Y(n1193) );
NOR2X1TS U1533 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1174) );
AOI32X1TS U1534 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1174), .A2(n1173), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1174), .Y(n1175) );
INVX2TS U1535 ( .A(n1177), .Y(n1179) );
OAI31X1TS U1536 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1518), .A2(n1179), .B0(
n1178), .Y(n1180) );
NOR4BX2TS U1537 ( .AN(n1183), .B(n1182), .C(n1181), .D(n1180), .Y(n1205) );
NOR2X1TS U1538 ( .A(n1205), .B(n906), .Y(n1307) );
AOI21X1TS U1539 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n906), .B0(n1307), .Y(
n1186) );
BUFX3TS U1540 ( .A(n1185), .Y(n1348) );
NOR2X2TS U1541 ( .A(n1185), .B(n1186), .Y(n1345) );
NOR2X4TS U1542 ( .A(n1187), .B(n906), .Y(n1336) );
AOI22X1TS U1543 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1336), .B0(n1335), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1189) );
AOI22X1TS U1544 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n911), .B0(n913), .B1(n935),
.Y(n1188) );
NAND2X1TS U1545 ( .A(n1189), .B(n1188), .Y(n1212) );
AOI22X1TS U1546 ( .A0(n1348), .A1(Data_array_SWR[1]), .B0(n1345), .B1(n1212),
.Y(n1192) );
NAND2X1TS U1547 ( .A(n1205), .B(n1336), .Y(n1190) );
INVX2TS U1548 ( .A(n1269), .Y(n1343) );
NAND2X1TS U1549 ( .A(Raw_mant_NRM_SWR[23]), .B(n1343), .Y(n1191) );
BUFX3TS U1550 ( .A(n1194), .Y(n1254) );
AOI22X1TS U1551 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1336), .B0(n1335), .B1(
n933), .Y(n1196) );
AOI22X1TS U1552 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n911), .B0(n913), .B1(n934),
.Y(n1195) );
NAND2X1TS U1553 ( .A(n1196), .B(n1195), .Y(n1209) );
AOI22X1TS U1554 ( .A0(n1348), .A1(Data_array_SWR[5]), .B0(n1345), .B1(n1209),
.Y(n1198) );
NAND2X1TS U1555 ( .A(Raw_mant_NRM_SWR[19]), .B(n1343), .Y(n1197) );
AOI22X1TS U1556 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1336), .B0(n1335), .B1(
n934), .Y(n1200) );
AOI22X1TS U1557 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n911), .B0(n913), .B1(n929),
.Y(n1199) );
NAND2X1TS U1558 ( .A(n1200), .B(n1199), .Y(n1204) );
AOI22X1TS U1559 ( .A0(n1348), .A1(Data_array_SWR[4]), .B0(n1345), .B1(n1204),
.Y(n1202) );
NAND2X1TS U1560 ( .A(Raw_mant_NRM_SWR[20]), .B(n1343), .Y(n1201) );
INVX2TS U1561 ( .A(n1345), .Y(n1203) );
AOI22X1TS U1562 ( .A0(n1348), .A1(Data_array_SWR[6]), .B0(n1184), .B1(n1204),
.Y(n1208) );
INVX2TS U1563 ( .A(n1336), .Y(n1264) );
NAND2X1TS U1564 ( .A(Raw_mant_NRM_SWR[16]), .B(n1206), .Y(n1207) );
AOI22X1TS U1565 ( .A0(n1348), .A1(Data_array_SWR[7]), .B0(n1184), .B1(n1209),
.Y(n1211) );
NAND2X1TS U1566 ( .A(Raw_mant_NRM_SWR[15]), .B(n1206), .Y(n1210) );
AOI22X1TS U1567 ( .A0(n1348), .A1(Data_array_SWR[3]), .B0(n1184), .B1(n1212),
.Y(n1214) );
NAND2X1TS U1568 ( .A(Raw_mant_NRM_SWR[19]), .B(n1206), .Y(n1213) );
AOI22X1TS U1569 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1336), .B0(n1335), .B1(
n935), .Y(n1217) );
AOI22X1TS U1570 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n911), .B0(n913), .B1(n936),
.Y(n1216) );
NAND2X1TS U1571 ( .A(n1217), .B(n1216), .Y(n1344) );
AOI22X1TS U1572 ( .A0(n1348), .A1(Data_array_SWR[2]), .B0(n1184), .B1(n1344),
.Y(n1219) );
NAND2X1TS U1573 ( .A(Raw_mant_NRM_SWR[20]), .B(n1206), .Y(n1218) );
AOI22X1TS U1574 ( .A0(n1348), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1206), .Y(n1222) );
AOI22X1TS U1575 ( .A0(n913), .A1(DmP_mant_SHT1_SW[21]), .B0(n1335), .B1(
DmP_mant_SHT1_SW[22]), .Y(n1224) );
AOI21X1TS U1576 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n912), .B0(n1225), .Y(n1331)
);
OAI22X1TS U1577 ( .A0(n1250), .A1(n945), .B0(n1593), .B1(n1269), .Y(n1226)
);
AOI21X1TS U1578 ( .A0(n1185), .A1(Data_array_SWR[21]), .B0(n1226), .Y(n1227)
);
AOI22X1TS U1579 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1336), .B0(
DmP_mant_SHT1_SW[15]), .B1(n1335), .Y(n1228) );
AOI21X1TS U1580 ( .A0(n930), .A1(n914), .B0(n1229), .Y(n1334) );
INVX2TS U1581 ( .A(n1206), .Y(n1255) );
OAI22X1TS U1582 ( .A0(n1234), .A1(n1203), .B0(n1541), .B1(n1255), .Y(n1230)
);
AOI21X1TS U1583 ( .A0(n1185), .A1(Data_array_SWR[16]), .B0(n1230), .Y(n1231)
);
AOI22X1TS U1584 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1336), .B0(n1335), .B1(
DmP_mant_SHT1_SW[19]), .Y(n1232) );
AOI21X1TS U1585 ( .A0(n914), .A1(DmP_mant_SHT1_SW[18]), .B0(n1233), .Y(n1258) );
OAI22X1TS U1586 ( .A0(n1234), .A1(n945), .B0(n1541), .B1(n1269), .Y(n1235)
);
AOI21X1TS U1587 ( .A0(n1185), .A1(Data_array_SWR[18]), .B0(n1235), .Y(n1236)
);
AOI22X1TS U1588 ( .A0(n1185), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1206), .Y(n1238) );
OA22X1TS U1589 ( .A0(n1542), .A1(n1269), .B0(n1241), .B1(n1203), .Y(n1237)
);
AOI22X1TS U1590 ( .A0(n1348), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1206), .Y(n1240) );
OA22X1TS U1591 ( .A0(n1527), .A1(n1269), .B0(n1253), .B1(n1203), .Y(n1239)
);
AOI22X1TS U1592 ( .A0(n1348), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1206), .Y(n1244) );
OA22X1TS U1593 ( .A0(n1518), .A1(n1269), .B0(n1242), .B1(n1203), .Y(n1243)
);
AOI22X1TS U1594 ( .A0(n1348), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1206), .Y(n1247) );
OA22X1TS U1595 ( .A0(n1540), .A1(n1269), .B0(n1245), .B1(n1203), .Y(n1246)
);
AOI22X1TS U1596 ( .A0(n1185), .A1(Data_array_SWR[19]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1206), .Y(n1252) );
OA22X1TS U1597 ( .A0(n1552), .A1(n1269), .B0(n1250), .B1(n1203), .Y(n1251)
);
OAI22X1TS U1598 ( .A0(n1266), .A1(n1203), .B0(n1551), .B1(n1255), .Y(n1256)
);
AOI21X1TS U1599 ( .A0(n1185), .A1(Data_array_SWR[20]), .B0(n1256), .Y(n1257)
);
AOI22X1TS U1600 ( .A0(n913), .A1(DmP_mant_SHT1_SW[8]), .B0(n1335), .B1(n932),
.Y(n1259) );
AOI21X1TS U1601 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n912), .B0(n1260), .Y(n1342) );
OAI22X1TS U1602 ( .A0(n1261), .A1(n945), .B0(n1517), .B1(n1269), .Y(n1262)
);
AOI21X1TS U1603 ( .A0(n1185), .A1(Data_array_SWR[8]), .B0(n1262), .Y(n1263)
);
OAI22X1TS U1604 ( .A0(n1596), .A1(n1338), .B0(n1529), .B1(n1264), .Y(n1265)
);
OAI22X1TS U1605 ( .A0(n1329), .A1(n1203), .B0(n1266), .B1(n945), .Y(n1267)
);
AOI21X1TS U1606 ( .A0(n1185), .A1(Data_array_SWR[22]), .B0(n1267), .Y(n1268)
);
AOI22X1TS U1607 ( .A0(DmP_mant_SFG_SWR[2]), .A1(n1403), .B0(n1407), .B1(n960), .Y(n1391) );
NAND2X1TS U1608 ( .A(n1391), .B(DMP_SFG[0]), .Y(n1394) );
INVX2TS U1609 ( .A(n1394), .Y(n1270) );
INVX2TS U1610 ( .A(n1271), .Y(n1279) );
AND4X1TS U1611 ( .A(exp_rslt_NRM2_EW1[3]), .B(n1308), .C(
exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n1272) );
INVX2TS U1612 ( .A(n1275), .Y(n1276) );
OAI2BB2XLTS U1613 ( .B0(n1411), .B1(n1279), .A0N(n872), .A1N(
final_result_ieee[30]), .Y(n754) );
INVX2TS U1614 ( .A(n1280), .Y(n1412) );
OAI2BB2XLTS U1615 ( .B0(n1281), .B1(n1411), .A0N(n872), .A1N(
final_result_ieee[31]), .Y(n543) );
INVX4TS U1616 ( .A(OP_FLAG_SFG), .Y(n1405) );
AOI22X1TS U1617 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n1407), .B0(n1403), .B1(n962), .Y(intadd_53_B_0_) );
AOI21X1TS U1618 ( .A0(intadd_53_A_1_), .A1(intadd_53_B_1_), .B0(
intadd_53_B_0_), .Y(n1282) );
AOI2BB2X1TS U1619 ( .B0(DMP_SFG[2]), .B1(n1282), .A0N(intadd_53_A_1_), .A1N(
intadd_53_B_1_), .Y(n1283) );
AOI222X1TS U1620 ( .A0(n1283), .A1(intadd_53_A_2_), .B0(n1283), .B1(n923),
.C0(intadd_53_A_2_), .C1(n923), .Y(n1284) );
AOI22X1TS U1621 ( .A0(DmP_mant_SFG_SWR[8]), .A1(n1405), .B0(n1403), .B1(n964), .Y(intadd_52_B_0_) );
AOI21X1TS U1622 ( .A0(intadd_52_A_1_), .A1(intadd_52_B_1_), .B0(
intadd_52_B_0_), .Y(n1285) );
AOI2BB2X1TS U1623 ( .B0(DMP_SFG[6]), .B1(n1285), .A0N(intadd_52_A_1_), .A1N(
intadd_52_B_1_), .Y(n1286) );
AOI222X1TS U1624 ( .A0(n1286), .A1(intadd_52_A_2_), .B0(n1286), .B1(
intadd_52_B_2_), .C0(intadd_52_A_2_), .C1(intadd_52_B_2_), .Y(n1287)
);
INVX2TS U1625 ( .A(n1288), .Y(n1289) );
NAND2X1TS U1626 ( .A(n1554), .B(n1289), .Y(DP_OP_15J49_123_3372_n8) );
MX2X1TS U1627 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n611) );
MX2X1TS U1628 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n907),
.Y(n616) );
MX2X1TS U1629 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n621) );
MX2X1TS U1630 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n626) );
MX2X1TS U1631 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n631) );
MX2X1TS U1632 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n636) );
MX2X1TS U1633 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n641) );
MX2X1TS U1634 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n907),
.Y(n646) );
OAI2BB1X1TS U1635 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n877), .B0(n1290), .Y(
n512) );
OAI32X1TS U1636 ( .A0(n1387), .A1(Raw_mant_NRM_SWR[14]), .A2(n1292), .B0(
n1291), .B1(n1387), .Y(n1296) );
AOI21X1TS U1637 ( .A0(n1298), .A1(Raw_mant_NRM_SWR[10]), .B0(n1297), .Y(
n1353) );
AOI22X1TS U1638 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1300), .B0(n1299), .B1(
Raw_mant_NRM_SWR[5]), .Y(n1302) );
OAI211XLTS U1639 ( .A0(n1304), .A1(n1303), .B0(n1302), .C0(n1301), .Y(n1305)
);
OAI21X1TS U1640 ( .A0(n1306), .A1(n1305), .B0(Shift_reg_FLAGS_7[1]), .Y(
n1349) );
OAI2BB1X1TS U1641 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n1387), .B0(n1349),
.Y(n514) );
OA22X1TS U1642 ( .A0(n1311), .A1(n1308), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[23]), .Y(n761) );
OA22X1TS U1643 ( .A0(n1311), .A1(n1309), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[28]), .Y(n756) );
OA22X1TS U1644 ( .A0(n1311), .A1(n1310), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[29]), .Y(n755) );
OA21XLTS U1645 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1411),
.Y(n558) );
INVX2TS U1646 ( .A(n1314), .Y(n1313) );
AOI22X1TS U1647 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1313), .B1(n1531), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1648 ( .A(n1313), .B(n1312), .Y(n871) );
AOI22X1TS U1649 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1314), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1531), .Y(n1318) );
AO22XLTS U1650 ( .A0(n1316), .A1(Shift_reg_FLAGS_7_6), .B0(n1317), .B1(n1318), .Y(n869) );
AOI22X1TS U1651 ( .A0(n1317), .A1(n1315), .B0(n1613), .B1(n1316), .Y(n868)
);
AOI22X1TS U1652 ( .A0(n1317), .A1(n1613), .B0(n916), .B1(n1316), .Y(n867) );
CLKBUFX2TS U1653 ( .A(n1651), .Y(n1392) );
AOI22X1TS U1654 ( .A0(n1317), .A1(n1651), .B0(n1387), .B1(n1316), .Y(n864)
);
AOI22X1TS U1655 ( .A0(n1317), .A1(n1387), .B0(n872), .B1(n1316), .Y(n863) );
AND2X2TS U1656 ( .A(beg_OP), .B(n1318), .Y(n1321) );
INVX2TS U1657 ( .A(n1325), .Y(n1319) );
BUFX3TS U1658 ( .A(n1321), .Y(n1325) );
INVX2TS U1659 ( .A(n1325), .Y(n1320) );
BUFX3TS U1660 ( .A(n1321), .Y(n1328) );
BUFX3TS U1661 ( .A(n1321), .Y(n1323) );
INVX2TS U1662 ( .A(n1325), .Y(n1327) );
INVX2TS U1663 ( .A(n1325), .Y(n1322) );
INVX2TS U1664 ( .A(n1325), .Y(n1324) );
AOI21X1TS U1665 ( .A0(n912), .A1(Raw_mant_NRM_SWR[0]), .B0(n914), .Y(n1330)
);
OAI2BB2XLTS U1666 ( .B0(n1330), .B1(n946), .A0N(n1185), .A1N(
Data_array_SWR[25]), .Y(n796) );
OAI2BB2XLTS U1667 ( .B0(n1329), .B1(n946), .A0N(n1185), .A1N(
Data_array_SWR[24]), .Y(n795) );
AOI22X1TS U1668 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1336), .B0(n1335), .B1(
n928), .Y(n1332) );
AOI21X1TS U1669 ( .A0(n914), .A1(n927), .B0(n1333), .Y(n1340) );
AOI22X1TS U1670 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1336), .B0(n1335), .B1(
n931), .Y(n1337) );
AOI21X1TS U1671 ( .A0(n914), .A1(DmP_mant_SHT1_SW[10]), .B0(n1339), .Y(n1341) );
AOI22X1TS U1672 ( .A0(n1348), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1343), .Y(n1347) );
AOI22X1TS U1673 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n912), .B0(n1345), .B1(
n1344), .Y(n1346) );
NAND2X1TS U1674 ( .A(n1347), .B(n1346), .Y(n771) );
NAND2X1TS U1675 ( .A(n1350), .B(n1349), .Y(n770) );
AOI21X1TS U1676 ( .A0(n947), .A1(Shift_amount_SHT1_EWR[3]), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1352) );
OAI22X1TS U1677 ( .A0(n1353), .A1(n1352), .B0(n1351), .B1(n1547), .Y(n769)
);
INVX2TS U1678 ( .A(n1613), .Y(n1375) );
AOI21X1TS U1679 ( .A0(DMP_EXP_EWSW[23]), .A1(n957), .B0(n1358), .Y(n1354) );
AOI2BB2XLTS U1680 ( .B0(n1375), .B1(n1354), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1375), .Y(n766) );
NOR2X1TS U1681 ( .A(n1538), .B(DMP_EXP_EWSW[24]), .Y(n1357) );
AOI21X1TS U1682 ( .A0(DMP_EXP_EWSW[24]), .A1(n1538), .B0(n1357), .Y(n1355)
);
XNOR2X1TS U1683 ( .A(n1358), .B(n1355), .Y(n1356) );
AO22XLTS U1684 ( .A0(n1375), .A1(n1356), .B0(n1613), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n765) );
OAI22X1TS U1685 ( .A0(n1358), .A1(n1357), .B0(DmP_EXP_EWSW[24]), .B1(n1539),
.Y(n1361) );
NAND2X1TS U1686 ( .A(DmP_EXP_EWSW[25]), .B(n1597), .Y(n1362) );
OAI21XLTS U1687 ( .A0(DmP_EXP_EWSW[25]), .A1(n1597), .B0(n1362), .Y(n1359)
);
XNOR2X1TS U1688 ( .A(n1361), .B(n1359), .Y(n1360) );
AO22XLTS U1689 ( .A0(n1375), .A1(n1360), .B0(n1385), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n764) );
AOI22X1TS U1690 ( .A0(DMP_EXP_EWSW[25]), .A1(n1610), .B0(n1362), .B1(n1361),
.Y(n1365) );
NOR2X1TS U1691 ( .A(n1605), .B(DMP_EXP_EWSW[26]), .Y(n1366) );
AOI21X1TS U1692 ( .A0(DMP_EXP_EWSW[26]), .A1(n1605), .B0(n1366), .Y(n1363)
);
XNOR2X1TS U1693 ( .A(n1365), .B(n1363), .Y(n1364) );
AO22XLTS U1694 ( .A0(n1375), .A1(n1364), .B0(n1377), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n763) );
OAI22X1TS U1695 ( .A0(n1366), .A1(n1365), .B0(DmP_EXP_EWSW[26]), .B1(n1609),
.Y(n1368) );
XNOR2X1TS U1696 ( .A(DmP_EXP_EWSW[27]), .B(n937), .Y(n1367) );
XOR2XLTS U1697 ( .A(n1368), .B(n1367), .Y(n1369) );
AO22XLTS U1698 ( .A0(n1375), .A1(n1369), .B0(n1378), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n762) );
OAI222X1TS U1699 ( .A0(n1380), .A1(n1608), .B0(n1539), .B1(
Shift_reg_FLAGS_7_6), .C0(n1519), .C1(n1382), .Y(n729) );
OAI222X1TS U1700 ( .A0(n1380), .A1(n1543), .B0(n1597), .B1(
Shift_reg_FLAGS_7_6), .C0(n1584), .C1(n1382), .Y(n728) );
OAI222X1TS U1701 ( .A0(n1380), .A1(n1544), .B0(n1609), .B1(
Shift_reg_FLAGS_7_6), .C0(n1590), .C1(n1382), .Y(n727) );
OAI21XLTS U1702 ( .A0(n1371), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1370) );
AOI21X1TS U1703 ( .A0(n1371), .A1(intDX_EWSW[31]), .B0(n1370), .Y(n1372) );
AO21XLTS U1704 ( .A0(OP_FLAG_EXP), .A1(n1049), .B0(n1372), .Y(n722) );
AO22XLTS U1705 ( .A0(n1375), .A1(DMP_EXP_EWSW[0]), .B0(n1379), .B1(
DMP_SHT1_EWSW[0]), .Y(n719) );
AO22XLTS U1706 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n1376), .B1(
DMP_SHT2_EWSW[0]), .Y(n718) );
BUFX3TS U1707 ( .A(n1374), .Y(n1498) );
AO22XLTS U1708 ( .A0(n1375), .A1(DMP_EXP_EWSW[1]), .B0(n1385), .B1(
DMP_SHT1_EWSW[1]), .Y(n716) );
AO22XLTS U1709 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n916), .B1(
DMP_SHT2_EWSW[1]), .Y(n715) );
AO22XLTS U1710 ( .A0(n1375), .A1(DMP_EXP_EWSW[2]), .B0(n1377), .B1(
DMP_SHT1_EWSW[2]), .Y(n713) );
AO22XLTS U1711 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n1376), .B1(
DMP_SHT2_EWSW[2]), .Y(n712) );
BUFX3TS U1712 ( .A(n1498), .Y(n1486) );
AO22XLTS U1713 ( .A0(n1486), .A1(DMP_SFG[2]), .B0(n1497), .B1(
DMP_SHT2_EWSW[2]), .Y(n711) );
INVX4TS U1714 ( .A(n1613), .Y(n1384) );
AO22XLTS U1715 ( .A0(n1384), .A1(DMP_EXP_EWSW[3]), .B0(n1378), .B1(
DMP_SHT1_EWSW[3]), .Y(n710) );
AO22XLTS U1716 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n948), .B1(
DMP_SHT2_EWSW[3]), .Y(n709) );
AO22XLTS U1717 ( .A0(n1486), .A1(DMP_SFG[3]), .B0(n1493), .B1(
DMP_SHT2_EWSW[3]), .Y(n708) );
AO22XLTS U1718 ( .A0(n1384), .A1(DMP_EXP_EWSW[4]), .B0(n1379), .B1(
DMP_SHT1_EWSW[4]), .Y(n707) );
AO22XLTS U1719 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n1653), .B1(
DMP_SHT2_EWSW[4]), .Y(n706) );
AO22XLTS U1720 ( .A0(n1486), .A1(DMP_SFG[4]), .B0(n1493), .B1(
DMP_SHT2_EWSW[4]), .Y(n705) );
AO22XLTS U1721 ( .A0(n1384), .A1(DMP_EXP_EWSW[5]), .B0(n1385), .B1(
DMP_SHT1_EWSW[5]), .Y(n704) );
AO22XLTS U1722 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n948), .B1(
DMP_SHT2_EWSW[5]), .Y(n703) );
AO22XLTS U1723 ( .A0(n1384), .A1(DMP_EXP_EWSW[6]), .B0(n1377), .B1(
DMP_SHT1_EWSW[6]), .Y(n701) );
AO22XLTS U1724 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1653), .B1(
DMP_SHT2_EWSW[6]), .Y(n700) );
AO22XLTS U1725 ( .A0(n1384), .A1(DMP_EXP_EWSW[7]), .B0(n1378), .B1(
DMP_SHT1_EWSW[7]), .Y(n698) );
AO22XLTS U1726 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n948), .B1(
DMP_SHT2_EWSW[7]), .Y(n697) );
AO22XLTS U1727 ( .A0(n1486), .A1(DMP_SFG[7]), .B0(n1497), .B1(
DMP_SHT2_EWSW[7]), .Y(n696) );
AO22XLTS U1728 ( .A0(n1384), .A1(DMP_EXP_EWSW[8]), .B0(n1379), .B1(
DMP_SHT1_EWSW[8]), .Y(n695) );
AO22XLTS U1729 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n1653), .B1(
DMP_SHT2_EWSW[8]), .Y(n694) );
AO22XLTS U1730 ( .A0(n1486), .A1(DMP_SFG[8]), .B0(n1497), .B1(
DMP_SHT2_EWSW[8]), .Y(n693) );
AO22XLTS U1731 ( .A0(n1384), .A1(DMP_EXP_EWSW[9]), .B0(n1613), .B1(
DMP_SHT1_EWSW[9]), .Y(n692) );
AO22XLTS U1732 ( .A0(busy), .A1(DMP_SHT1_EWSW[9]), .B0(n948), .B1(
DMP_SHT2_EWSW[9]), .Y(n691) );
AO22XLTS U1733 ( .A0(n1384), .A1(DMP_EXP_EWSW[10]), .B0(n1613), .B1(
DMP_SHT1_EWSW[10]), .Y(n689) );
AO22XLTS U1734 ( .A0(n915), .A1(DMP_SHT1_EWSW[10]), .B0(n1376), .B1(
DMP_SHT2_EWSW[10]), .Y(n688) );
AO22XLTS U1735 ( .A0(n1486), .A1(DMP_SFG[10]), .B0(n1493), .B1(
DMP_SHT2_EWSW[10]), .Y(n687) );
BUFX3TS U1736 ( .A(n1613), .Y(n1377) );
AO22XLTS U1737 ( .A0(n1384), .A1(DMP_EXP_EWSW[11]), .B0(n1377), .B1(
DMP_SHT1_EWSW[11]), .Y(n686) );
AO22XLTS U1738 ( .A0(n915), .A1(DMP_SHT1_EWSW[11]), .B0(n1376), .B1(
DMP_SHT2_EWSW[11]), .Y(n685) );
AO22XLTS U1739 ( .A0(n1384), .A1(DMP_EXP_EWSW[12]), .B0(n1377), .B1(
DMP_SHT1_EWSW[12]), .Y(n683) );
AO22XLTS U1740 ( .A0(busy), .A1(DMP_SHT1_EWSW[12]), .B0(n1653), .B1(
DMP_SHT2_EWSW[12]), .Y(n682) );
AO22XLTS U1741 ( .A0(n1486), .A1(DMP_SFG[12]), .B0(n1493), .B1(
DMP_SHT2_EWSW[12]), .Y(n681) );
AO22XLTS U1742 ( .A0(n1384), .A1(DMP_EXP_EWSW[13]), .B0(n1377), .B1(
DMP_SHT1_EWSW[13]), .Y(n680) );
AO22XLTS U1743 ( .A0(busy), .A1(DMP_SHT1_EWSW[13]), .B0(n948), .B1(
DMP_SHT2_EWSW[13]), .Y(n679) );
AO22XLTS U1744 ( .A0(n1384), .A1(DMP_EXP_EWSW[14]), .B0(n1377), .B1(
DMP_SHT1_EWSW[14]), .Y(n677) );
AO22XLTS U1745 ( .A0(busy), .A1(DMP_SHT1_EWSW[14]), .B0(n1376), .B1(
DMP_SHT2_EWSW[14]), .Y(n676) );
AO22XLTS U1746 ( .A0(n1486), .A1(DMP_SFG[14]), .B0(n1497), .B1(
DMP_SHT2_EWSW[14]), .Y(n675) );
AO22XLTS U1747 ( .A0(n1384), .A1(DMP_EXP_EWSW[15]), .B0(n1377), .B1(
DMP_SHT1_EWSW[15]), .Y(n674) );
AO22XLTS U1748 ( .A0(busy), .A1(DMP_SHT1_EWSW[15]), .B0(n1376), .B1(
DMP_SHT2_EWSW[15]), .Y(n673) );
AO22XLTS U1749 ( .A0(n1384), .A1(DMP_EXP_EWSW[16]), .B0(n1377), .B1(
DMP_SHT1_EWSW[16]), .Y(n671) );
AO22XLTS U1750 ( .A0(n1654), .A1(DMP_SHT1_EWSW[16]), .B0(n1376), .B1(
DMP_SHT2_EWSW[16]), .Y(n670) );
AO22XLTS U1751 ( .A0(n1486), .A1(DMP_SFG[16]), .B0(n1509), .B1(
DMP_SHT2_EWSW[16]), .Y(n669) );
INVX4TS U1752 ( .A(n1613), .Y(n1386) );
AO22XLTS U1753 ( .A0(n1386), .A1(DMP_EXP_EWSW[17]), .B0(n1377), .B1(
DMP_SHT1_EWSW[17]), .Y(n668) );
AO22XLTS U1754 ( .A0(n1654), .A1(DMP_SHT1_EWSW[17]), .B0(n1376), .B1(
DMP_SHT2_EWSW[17]), .Y(n667) );
AO22XLTS U1755 ( .A0(n1386), .A1(DMP_EXP_EWSW[18]), .B0(n1377), .B1(
DMP_SHT1_EWSW[18]), .Y(n665) );
AO22XLTS U1756 ( .A0(n1654), .A1(DMP_SHT1_EWSW[18]), .B0(n1376), .B1(
DMP_SHT2_EWSW[18]), .Y(n664) );
AO22XLTS U1757 ( .A0(n1486), .A1(DMP_SFG[18]), .B0(n1514), .B1(
DMP_SHT2_EWSW[18]), .Y(n663) );
AO22XLTS U1758 ( .A0(n1386), .A1(DMP_EXP_EWSW[19]), .B0(n1377), .B1(
DMP_SHT1_EWSW[19]), .Y(n662) );
AO22XLTS U1759 ( .A0(n1654), .A1(DMP_SHT1_EWSW[19]), .B0(n1376), .B1(
DMP_SHT2_EWSW[19]), .Y(n661) );
AO22XLTS U1760 ( .A0(n1386), .A1(DMP_EXP_EWSW[20]), .B0(n1377), .B1(
DMP_SHT1_EWSW[20]), .Y(n659) );
AO22XLTS U1761 ( .A0(n1654), .A1(DMP_SHT1_EWSW[20]), .B0(n1376), .B1(
DMP_SHT2_EWSW[20]), .Y(n658) );
AO22XLTS U1762 ( .A0(n1386), .A1(DMP_EXP_EWSW[21]), .B0(n1377), .B1(
DMP_SHT1_EWSW[21]), .Y(n656) );
AO22XLTS U1763 ( .A0(n1654), .A1(DMP_SHT1_EWSW[21]), .B0(n1653), .B1(
DMP_SHT2_EWSW[21]), .Y(n655) );
BUFX3TS U1764 ( .A(n1613), .Y(n1385) );
AO22XLTS U1765 ( .A0(n1386), .A1(DMP_EXP_EWSW[22]), .B0(n1385), .B1(
DMP_SHT1_EWSW[22]), .Y(n653) );
AO22XLTS U1766 ( .A0(n1654), .A1(DMP_SHT1_EWSW[22]), .B0(n948), .B1(
DMP_SHT2_EWSW[22]), .Y(n652) );
AO22XLTS U1767 ( .A0(n1386), .A1(DMP_EXP_EWSW[23]), .B0(n1385), .B1(
DMP_SHT1_EWSW[23]), .Y(n650) );
AO22XLTS U1768 ( .A0(n947), .A1(DMP_SHT1_EWSW[23]), .B0(n1653), .B1(
DMP_SHT2_EWSW[23]), .Y(n649) );
AO22XLTS U1769 ( .A0(n1509), .A1(DMP_SHT2_EWSW[23]), .B0(n1374), .B1(
DMP_SFG[23]), .Y(n648) );
AO22XLTS U1770 ( .A0(n1402), .A1(DMP_SFG[23]), .B0(n1392), .B1(
DMP_exp_NRM_EW[0]), .Y(n647) );
AO22XLTS U1771 ( .A0(n1386), .A1(DMP_EXP_EWSW[24]), .B0(n1385), .B1(
DMP_SHT1_EWSW[24]), .Y(n645) );
AO22XLTS U1772 ( .A0(n947), .A1(DMP_SHT1_EWSW[24]), .B0(n948), .B1(
DMP_SHT2_EWSW[24]), .Y(n644) );
AO22XLTS U1773 ( .A0(n1497), .A1(DMP_SHT2_EWSW[24]), .B0(n1374), .B1(
DMP_SFG[24]), .Y(n643) );
AO22XLTS U1774 ( .A0(n1402), .A1(DMP_SFG[24]), .B0(n1392), .B1(
DMP_exp_NRM_EW[1]), .Y(n642) );
AO22XLTS U1775 ( .A0(n1386), .A1(DMP_EXP_EWSW[25]), .B0(n1385), .B1(
DMP_SHT1_EWSW[25]), .Y(n640) );
AO22XLTS U1776 ( .A0(n947), .A1(DMP_SHT1_EWSW[25]), .B0(n1653), .B1(
DMP_SHT2_EWSW[25]), .Y(n639) );
AO22XLTS U1777 ( .A0(n1509), .A1(DMP_SHT2_EWSW[25]), .B0(n1374), .B1(
DMP_SFG[25]), .Y(n638) );
AO22XLTS U1778 ( .A0(n1402), .A1(DMP_SFG[25]), .B0(n1392), .B1(
DMP_exp_NRM_EW[2]), .Y(n637) );
AO22XLTS U1779 ( .A0(n1386), .A1(DMP_EXP_EWSW[26]), .B0(n1385), .B1(
DMP_SHT1_EWSW[26]), .Y(n635) );
AO22XLTS U1780 ( .A0(n1654), .A1(DMP_SHT1_EWSW[26]), .B0(n948), .B1(
DMP_SHT2_EWSW[26]), .Y(n634) );
AO22XLTS U1781 ( .A0(n1509), .A1(DMP_SHT2_EWSW[26]), .B0(n1374), .B1(
DMP_SFG[26]), .Y(n633) );
AO22XLTS U1782 ( .A0(n1402), .A1(DMP_SFG[26]), .B0(n1392), .B1(
DMP_exp_NRM_EW[3]), .Y(n632) );
AO22XLTS U1783 ( .A0(n1386), .A1(n937), .B0(n1385), .B1(DMP_SHT1_EWSW[27]),
.Y(n630) );
AO22XLTS U1784 ( .A0(n947), .A1(DMP_SHT1_EWSW[27]), .B0(n1653), .B1(
DMP_SHT2_EWSW[27]), .Y(n629) );
AO22XLTS U1785 ( .A0(n1493), .A1(DMP_SHT2_EWSW[27]), .B0(n1512), .B1(
DMP_SFG[27]), .Y(n628) );
AO22XLTS U1786 ( .A0(n1402), .A1(DMP_SFG[27]), .B0(n1409), .B1(
DMP_exp_NRM_EW[4]), .Y(n627) );
AO22XLTS U1787 ( .A0(n1386), .A1(DMP_EXP_EWSW[28]), .B0(n1385), .B1(
DMP_SHT1_EWSW[28]), .Y(n625) );
AO22XLTS U1788 ( .A0(n915), .A1(DMP_SHT1_EWSW[28]), .B0(n916), .B1(
DMP_SHT2_EWSW[28]), .Y(n624) );
AO22XLTS U1789 ( .A0(n1514), .A1(DMP_SHT2_EWSW[28]), .B0(n1486), .B1(
DMP_SFG[28]), .Y(n623) );
AO22XLTS U1790 ( .A0(n1402), .A1(DMP_SFG[28]), .B0(n1409), .B1(
DMP_exp_NRM_EW[5]), .Y(n622) );
AO22XLTS U1791 ( .A0(n1386), .A1(DMP_EXP_EWSW[29]), .B0(n1385), .B1(
DMP_SHT1_EWSW[29]), .Y(n620) );
AO22XLTS U1792 ( .A0(n947), .A1(DMP_SHT1_EWSW[29]), .B0(n1653), .B1(
DMP_SHT2_EWSW[29]), .Y(n619) );
AO22XLTS U1793 ( .A0(n1402), .A1(DMP_SFG[29]), .B0(n1409), .B1(
DMP_exp_NRM_EW[6]), .Y(n617) );
AO22XLTS U1794 ( .A0(n1520), .A1(DMP_EXP_EWSW[30]), .B0(n1385), .B1(
DMP_SHT1_EWSW[30]), .Y(n615) );
AO22XLTS U1795 ( .A0(n915), .A1(DMP_SHT1_EWSW[30]), .B0(n1376), .B1(
DMP_SHT2_EWSW[30]), .Y(n614) );
AO22XLTS U1796 ( .A0(n1497), .A1(DMP_SHT2_EWSW[30]), .B0(n1498), .B1(
DMP_SFG[30]), .Y(n613) );
AO22XLTS U1797 ( .A0(n1402), .A1(DMP_SFG[30]), .B0(n1409), .B1(
DMP_exp_NRM_EW[7]), .Y(n612) );
BUFX3TS U1798 ( .A(n1613), .Y(n1378) );
BUFX3TS U1799 ( .A(n1613), .Y(n1379) );
OAI222X1TS U1800 ( .A0(n1382), .A1(n1608), .B0(n1538), .B1(
Shift_reg_FLAGS_7_6), .C0(n1519), .C1(n1380), .Y(n563) );
OAI222X1TS U1801 ( .A0(n1382), .A1(n1543), .B0(n1610), .B1(
Shift_reg_FLAGS_7_6), .C0(n1584), .C1(n1380), .Y(n562) );
OAI222X1TS U1802 ( .A0(n1382), .A1(n1544), .B0(n1605), .B1(
Shift_reg_FLAGS_7_6), .C0(n1590), .C1(n1380), .Y(n561) );
NAND2X1TS U1803 ( .A(n1412), .B(Shift_reg_FLAGS_7[0]), .Y(n1383) );
OAI2BB1X1TS U1804 ( .A0N(underflow_flag), .A1N(n1471), .B0(n1383), .Y(n559)
);
AO22XLTS U1805 ( .A0(n1386), .A1(ZERO_FLAG_EXP), .B0(n1613), .B1(
ZERO_FLAG_SHT1), .Y(n557) );
AO22XLTS U1806 ( .A0(n947), .A1(ZERO_FLAG_SHT1), .B0(n948), .B1(
ZERO_FLAG_SHT2), .Y(n556) );
AO22XLTS U1807 ( .A0(n1402), .A1(ZERO_FLAG_SFG), .B0(n1409), .B1(
ZERO_FLAG_NRM), .Y(n554) );
AO22XLTS U1808 ( .A0(n907), .A1(ZERO_FLAG_NRM), .B0(n1387), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n553) );
AO22XLTS U1809 ( .A0(n1384), .A1(OP_FLAG_EXP), .B0(n1613), .B1(OP_FLAG_SHT1),
.Y(n551) );
AO22XLTS U1810 ( .A0(n915), .A1(OP_FLAG_SHT1), .B0(n1376), .B1(OP_FLAG_SHT2),
.Y(n550) );
AO22XLTS U1811 ( .A0(n1491), .A1(OP_FLAG_SFG), .B0(n1509), .B1(OP_FLAG_SHT2),
.Y(n549) );
AO22XLTS U1812 ( .A0(n1386), .A1(SIGN_FLAG_EXP), .B0(n1385), .B1(
SIGN_FLAG_SHT1), .Y(n548) );
AO22XLTS U1813 ( .A0(n915), .A1(SIGN_FLAG_SHT1), .B0(n916), .B1(
SIGN_FLAG_SHT2), .Y(n547) );
AO22XLTS U1814 ( .A0(n1493), .A1(SIGN_FLAG_SHT2), .B0(n1498), .B1(
SIGN_FLAG_SFG), .Y(n546) );
AO22XLTS U1815 ( .A0(n1402), .A1(SIGN_FLAG_SFG), .B0(n1392), .B1(
SIGN_FLAG_NRM), .Y(n545) );
AO22XLTS U1816 ( .A0(n907), .A1(SIGN_FLAG_NRM), .B0(n1387), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n544) );
AOI22X1TS U1817 ( .A0(DmP_mant_SFG_SWR[0]), .A1(n1405), .B0(OP_FLAG_SFG),
.B1(n958), .Y(n1389) );
AOI22X1TS U1818 ( .A0(n1406), .A1(n1389), .B0(n1529), .B1(n1651), .Y(n542)
);
AOI22X1TS U1819 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n1407), .B0(n1403), .B1(n959), .Y(n1390) );
AOI22X1TS U1820 ( .A0(n1406), .A1(n1390), .B0(n1596), .B1(n1651), .Y(n541)
);
OAI21XLTS U1821 ( .A0(n1391), .A1(DMP_SFG[0]), .B0(n1394), .Y(n1393) );
AOI22X1TS U1822 ( .A0(n1406), .A1(n1393), .B0(n1551), .B1(n1392), .Y(n540)
);
XNOR2X1TS U1823 ( .A(DMP_SFG[1]), .B(n1394), .Y(n1395) );
XNOR2X1TS U1824 ( .A(n1395), .B(n919), .Y(n1396) );
AOI22X1TS U1825 ( .A0(n1406), .A1(n1396), .B0(n1593), .B1(n1651), .Y(n539)
);
AOI2BB2XLTS U1826 ( .B0(n1650), .B1(intadd_53_SUM_0_), .A0N(
Raw_mant_NRM_SWR[4]), .A1N(n1402), .Y(n538) );
AOI22X1TS U1827 ( .A0(n1650), .A1(intadd_53_SUM_1_), .B0(n1552), .B1(n1651),
.Y(n537) );
AOI22X1TS U1828 ( .A0(n1650), .A1(intadd_53_SUM_2_), .B0(n1541), .B1(n1409),
.Y(n536) );
XNOR2X1TS U1829 ( .A(DMP_SFG[5]), .B(n920), .Y(n1397) );
XNOR2X1TS U1830 ( .A(intadd_53_n1), .B(n1397), .Y(n1398) );
AOI22X1TS U1831 ( .A0(n1650), .A1(n1398), .B0(n1527), .B1(n1409), .Y(n535)
);
AOI22X1TS U1832 ( .A0(n1650), .A1(intadd_52_SUM_0_), .B0(n1530), .B1(n1409),
.Y(n534) );
AOI22X1TS U1833 ( .A0(n1650), .A1(intadd_52_SUM_1_), .B0(n1542), .B1(n1409),
.Y(n533) );
AOI22X1TS U1834 ( .A0(n1650), .A1(intadd_52_SUM_2_), .B0(n1525), .B1(n1409),
.Y(n532) );
XNOR2X1TS U1835 ( .A(DMP_SFG[9]), .B(n1399), .Y(n1400) );
XNOR2X1TS U1836 ( .A(intadd_52_n1), .B(n1400), .Y(n1401) );
AOI22X1TS U1837 ( .A0(n1650), .A1(n1401), .B0(n1518), .B1(n1409), .Y(n531)
);
AOI22X1TS U1838 ( .A0(n1406), .A1(intadd_51_SUM_1_), .B0(n1540), .B1(n1409),
.Y(n529) );
AOI22X1TS U1839 ( .A0(n1406), .A1(intadd_51_SUM_2_), .B0(n1523), .B1(n1409),
.Y(n528) );
AOI22X1TS U1840 ( .A0(n1406), .A1(intadd_51_SUM_3_), .B0(n1522), .B1(n1409),
.Y(n527) );
AOI22X1TS U1841 ( .A0(DmP_mant_SFG_SWR[16]), .A1(n1405), .B0(n1403), .B1(
n950), .Y(intadd_51_B_4_) );
AOI22X1TS U1842 ( .A0(n1406), .A1(intadd_51_SUM_4_), .B0(n1517), .B1(n1392),
.Y(n526) );
AOI22X1TS U1843 ( .A0(DmP_mant_SFG_SWR[17]), .A1(n1405), .B0(n1403), .B1(
n951), .Y(intadd_51_B_5_) );
AOI22X1TS U1844 ( .A0(n1406), .A1(intadd_51_SUM_5_), .B0(n1546), .B1(n1651),
.Y(n525) );
AOI22X1TS U1845 ( .A0(DmP_mant_SFG_SWR[18]), .A1(n1405), .B0(n1403), .B1(
n952), .Y(intadd_51_B_6_) );
AOI22X1TS U1846 ( .A0(DmP_mant_SFG_SWR[19]), .A1(n1405), .B0(n1403), .B1(
n953), .Y(intadd_51_B_7_) );
AOI22X1TS U1847 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n1405), .B0(n1403), .B1(
n954), .Y(intadd_51_B_8_) );
AOI22X1TS U1848 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n1405), .B0(OP_FLAG_SFG),
.B1(n955), .Y(intadd_51_B_9_) );
AOI22X1TS U1849 ( .A0(n1406), .A1(intadd_51_SUM_9_), .B0(n1548), .B1(n1651),
.Y(n521) );
AOI22X1TS U1850 ( .A0(DmP_mant_SFG_SWR[22]), .A1(n1405), .B0(OP_FLAG_SFG),
.B1(n956), .Y(intadd_51_B_10_) );
AOI22X1TS U1851 ( .A0(n1406), .A1(intadd_51_SUM_10_), .B0(n1545), .B1(n1651),
.Y(n520) );
AOI22X1TS U1852 ( .A0(DmP_mant_SFG_SWR[23]), .A1(n1405), .B0(OP_FLAG_SFG),
.B1(n1599), .Y(intadd_51_B_11_) );
AOI22X1TS U1853 ( .A0(n1406), .A1(intadd_51_SUM_11_), .B0(n1515), .B1(n1651),
.Y(n519) );
AOI22X1TS U1854 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1405), .B0(OP_FLAG_SFG),
.B1(n1612), .Y(intadd_51_B_12_) );
AOI22X1TS U1855 ( .A0(n1406), .A1(intadd_51_SUM_12_), .B0(n1516), .B1(n1651),
.Y(n518) );
AOI22X1TS U1856 ( .A0(DmP_mant_SFG_SWR[25]), .A1(OP_FLAG_SFG), .B0(n1407),
.B1(n1616), .Y(n1408) );
XNOR2X1TS U1857 ( .A(intadd_51_n1), .B(n1408), .Y(n1410) );
AOI22X1TS U1858 ( .A0(n1650), .A1(n1410), .B0(n1521), .B1(n1409), .Y(n517)
);
AND3X4TS U1859 ( .A(shift_value_SHT2_EWR[2]), .B(n1550), .C(
shift_value_SHT2_EWR[3]), .Y(n1472) );
NAND2X1TS U1860 ( .A(shift_value_SHT2_EWR[2]), .B(n1547), .Y(n1427) );
NAND2X1TS U1861 ( .A(n1447), .B(n1550), .Y(n1458) );
AOI22X1TS U1862 ( .A0(Data_array_SWR[12]), .A1(n902), .B0(Data_array_SWR[13]), .B1(n939), .Y(n1413) );
OAI221X1TS U1863 ( .A0(n908), .A1(n1415), .B0(n909), .B1(n1416), .C0(n1413),
.Y(n1492) );
AOI22X1TS U1864 ( .A0(Data_array_SWR[12]), .A1(n939), .B0(Data_array_SWR[13]), .B1(n902), .Y(n1414) );
OAI221X1TS U1865 ( .A0(left_right_SHT2), .A1(n1416), .B0(n875), .B1(n1415),
.C0(n1414), .Y(n1494) );
AOI22X1TS U1866 ( .A0(Data_array_SWR[22]), .A1(n943), .B0(Data_array_SWR[18]), .B1(n942), .Y(n1420) );
AOI22X1TS U1867 ( .A0(Data_array_SWR[14]), .A1(n939), .B0(Data_array_SWR[11]), .B1(n902), .Y(n1417) );
OAI221X1TS U1868 ( .A0(left_right_SHT2), .A1(n1419), .B0(n875), .B1(n1420),
.C0(n1417), .Y(n1490) );
AOI22X1TS U1869 ( .A0(Data_array_SWR[14]), .A1(n902), .B0(Data_array_SWR[11]), .B1(n939), .Y(n1418) );
OAI221X1TS U1870 ( .A0(n908), .A1(n1420), .B0(n909), .B1(n1419), .C0(n1418),
.Y(n1495) );
AOI22X1TS U1871 ( .A0(Data_array_SWR[23]), .A1(n943), .B0(Data_array_SWR[19]), .B1(n942), .Y(n1424) );
AOI22X1TS U1872 ( .A0(Data_array_SWR[10]), .A1(n902), .B0(Data_array_SWR[15]), .B1(n939), .Y(n1421) );
OAI221X1TS U1873 ( .A0(n908), .A1(n1423), .B0(n909), .B1(n1424), .C0(n1421),
.Y(n1489) );
AOI22X1TS U1874 ( .A0(Data_array_SWR[10]), .A1(n939), .B0(Data_array_SWR[15]), .B1(n902), .Y(n1422) );
OAI221X1TS U1875 ( .A0(left_right_SHT2), .A1(n1424), .B0(n875), .B1(n1423),
.C0(n1422), .Y(n1496) );
AOI22X1TS U1876 ( .A0(Data_array_SWR[17]), .A1(n944), .B0(Data_array_SWR[13]), .B1(n941), .Y(n1426) );
AOI22X1TS U1877 ( .A0(Data_array_SWR[21]), .A1(n1472), .B0(
Data_array_SWR[25]), .B1(n1440), .Y(n1425) );
NAND2X1TS U1878 ( .A(n1426), .B(n1425), .Y(n1430) );
NOR2X1TS U1879 ( .A(shift_value_SHT2_EWR[2]), .B(n1547), .Y(n1433) );
INVX2TS U1880 ( .A(n1427), .Y(n1448) );
INVX2TS U1881 ( .A(n1476), .Y(n1429) );
OAI2BB2XLTS U1882 ( .B0(n1488), .B1(n904), .A0N(final_result_ieee[7]), .A1N(
n1471), .Y(n505) );
OAI2BB2XLTS U1883 ( .B0(n1499), .B1(n905), .A0N(final_result_ieee[14]),
.A1N(n1471), .Y(n504) );
AOI22X1TS U1884 ( .A0(Data_array_SWR[12]), .A1(n942), .B0(Data_array_SWR[16]), .B1(n943), .Y(n1432) );
AOI22X1TS U1885 ( .A0(Data_array_SWR[24]), .A1(n1440), .B0(
Data_array_SWR[20]), .B1(n1472), .Y(n1431) );
NAND2X1TS U1886 ( .A(n1432), .B(n1431), .Y(n1435) );
INVX2TS U1887 ( .A(n1470), .Y(n1434) );
OAI2BB2XLTS U1888 ( .B0(n1487), .B1(n905), .A0N(final_result_ieee[6]), .A1N(
n1471), .Y(n503) );
OAI2BB2XLTS U1889 ( .B0(n1500), .B1(n905), .A0N(final_result_ieee[15]),
.A1N(n1471), .Y(n502) );
AOI22X1TS U1890 ( .A0(Data_array_SWR[15]), .A1(n944), .B0(Data_array_SWR[11]), .B1(n942), .Y(n1437) );
AOI22X1TS U1891 ( .A0(Data_array_SWR[23]), .A1(n1440), .B0(
Data_array_SWR[19]), .B1(n1472), .Y(n1436) );
NAND2X1TS U1892 ( .A(n1437), .B(n1436), .Y(n1439) );
AOI22X1TS U1893 ( .A0(Data_array_SWR[22]), .A1(n1448), .B0(
Data_array_SWR[18]), .B1(n1447), .Y(n1464) );
INVX2TS U1894 ( .A(n1464), .Y(n1438) );
OAI2BB2XLTS U1895 ( .B0(n1485), .B1(n905), .A0N(final_result_ieee[5]), .A1N(
n1471), .Y(n501) );
OAI2BB2XLTS U1896 ( .B0(n1501), .B1(n905), .A0N(final_result_ieee[16]),
.A1N(n1471), .Y(n500) );
AOI22X1TS U1897 ( .A0(Data_array_SWR[14]), .A1(n944), .B0(Data_array_SWR[10]), .B1(n941), .Y(n1442) );
AOI22X1TS U1898 ( .A0(Data_array_SWR[22]), .A1(n1440), .B0(
Data_array_SWR[18]), .B1(n1472), .Y(n1441) );
NAND2X1TS U1899 ( .A(n1442), .B(n1441), .Y(n1444) );
AOI22X1TS U1900 ( .A0(Data_array_SWR[23]), .A1(n1448), .B0(
Data_array_SWR[19]), .B1(n1447), .Y(n1461) );
INVX2TS U1901 ( .A(n1461), .Y(n1443) );
OAI2BB2XLTS U1902 ( .B0(n1484), .B1(n905), .A0N(final_result_ieee[4]), .A1N(
n872), .Y(n499) );
OAI2BB2XLTS U1903 ( .B0(n1502), .B1(n905), .A0N(final_result_ieee[17]),
.A1N(n872), .Y(n498) );
AOI22X1TS U1904 ( .A0(Data_array_SWR[21]), .A1(n1447), .B0(
Data_array_SWR[25]), .B1(n1448), .Y(n1453) );
AOI22X1TS U1905 ( .A0(Data_array_SWR[13]), .A1(n943), .B0(Data_array_SWR[9]),
.B1(n941), .Y(n1446) );
NAND2X1TS U1906 ( .A(Data_array_SWR[17]), .B(n1472), .Y(n1445) );
OAI211X1TS U1907 ( .A0(n1453), .A1(n1550), .B0(n1446), .C0(n1445), .Y(n1449)
);
AO22X1TS U1908 ( .A0(Data_array_SWR[24]), .A1(n1448), .B0(Data_array_SWR[20]), .B1(n1447), .Y(n1450) );
OAI2BB2XLTS U1909 ( .B0(n1483), .B1(n904), .A0N(final_result_ieee[3]), .A1N(
n872), .Y(n497) );
OAI2BB2XLTS U1910 ( .B0(n1503), .B1(n904), .A0N(final_result_ieee[18]),
.A1N(n872), .Y(n496) );
AOI22X1TS U1911 ( .A0(Data_array_SWR[12]), .A1(n944), .B0(Data_array_SWR[8]),
.B1(n941), .Y(n1452) );
AOI22X1TS U1912 ( .A0(Data_array_SWR[16]), .A1(n1472), .B0(
shift_value_SHT2_EWR[4]), .B1(n1450), .Y(n1451) );
NAND2X1TS U1913 ( .A(n1452), .B(n1451), .Y(n1457) );
INVX2TS U1914 ( .A(n1453), .Y(n1456) );
OAI2BB2XLTS U1915 ( .B0(n1482), .B1(n905), .A0N(final_result_ieee[2]), .A1N(
n872), .Y(n495) );
OAI2BB2XLTS U1916 ( .B0(n1504), .B1(n905), .A0N(final_result_ieee[19]),
.A1N(n872), .Y(n494) );
AOI22X1TS U1917 ( .A0(Data_array_SWR[15]), .A1(n1472), .B0(
Data_array_SWR[11]), .B1(n943), .Y(n1460) );
INVX2TS U1918 ( .A(n1458), .Y(n1473) );
AOI22X1TS U1919 ( .A0(Data_array_SWR[7]), .A1(n941), .B0(Data_array_SWR[3]),
.B1(n1473), .Y(n1459) );
OAI211X1TS U1920 ( .A0(n1461), .A1(n1550), .B0(n1460), .C0(n1459), .Y(n1465)
);
AOI22X1TS U1921 ( .A0(Data_array_SWR[22]), .A1(n939), .B0(n909), .B1(n1465),
.Y(n1481) );
OAI2BB2XLTS U1922 ( .B0(n1481), .B1(n904), .A0N(final_result_ieee[1]), .A1N(
n872), .Y(n493) );
AOI22X1TS U1923 ( .A0(Data_array_SWR[14]), .A1(n1472), .B0(
Data_array_SWR[10]), .B1(n943), .Y(n1463) );
AOI22X1TS U1924 ( .A0(Data_array_SWR[6]), .A1(n941), .B0(Data_array_SWR[2]),
.B1(n1473), .Y(n1462) );
OAI211X1TS U1925 ( .A0(n1464), .A1(n1550), .B0(n1463), .C0(n1462), .Y(n1466)
);
AOI22X1TS U1926 ( .A0(Data_array_SWR[23]), .A1(n940), .B0(n909), .B1(n1466),
.Y(n1480) );
OAI2BB2XLTS U1927 ( .B0(n1480), .B1(n904), .A0N(final_result_ieee[0]), .A1N(
n872), .Y(n492) );
AOI22X1TS U1928 ( .A0(Data_array_SWR[22]), .A1(n903), .B0(left_right_SHT2),
.B1(n1465), .Y(n1505) );
OAI2BB2XLTS U1929 ( .B0(n1505), .B1(n904), .A0N(final_result_ieee[20]),
.A1N(n872), .Y(n491) );
AOI22X1TS U1930 ( .A0(Data_array_SWR[23]), .A1(n902), .B0(left_right_SHT2),
.B1(n1466), .Y(n1506) );
OAI2BB2XLTS U1931 ( .B0(n1506), .B1(n904), .A0N(final_result_ieee[21]),
.A1N(n872), .Y(n490) );
AOI22X1TS U1932 ( .A0(Data_array_SWR[13]), .A1(n1472), .B0(Data_array_SWR[9]), .B1(n943), .Y(n1469) );
AOI22X1TS U1933 ( .A0(Data_array_SWR[5]), .A1(n941), .B0(Data_array_SWR[1]),
.B1(n1473), .Y(n1468) );
OAI211X1TS U1934 ( .A0(n1470), .A1(n1550), .B0(n1469), .C0(n1468), .Y(n1478)
);
AOI22X1TS U1935 ( .A0(Data_array_SWR[24]), .A1(n903), .B0(left_right_SHT2),
.B1(n1478), .Y(n1508) );
OAI2BB2XLTS U1936 ( .B0(n1508), .B1(n904), .A0N(final_result_ieee[22]),
.A1N(n1471), .Y(n489) );
AOI22X1TS U1937 ( .A0(Data_array_SWR[12]), .A1(n1472), .B0(Data_array_SWR[8]), .B1(n944), .Y(n1475) );
AOI22X1TS U1938 ( .A0(Data_array_SWR[4]), .A1(n942), .B0(Data_array_SWR[0]),
.B1(n1473), .Y(n1474) );
OAI211X1TS U1939 ( .A0(n1476), .A1(n1550), .B0(n1475), .C0(n1474), .Y(n1510)
);
AOI22X1TS U1940 ( .A0(Data_array_SWR[25]), .A1(n940), .B0(n909), .B1(n1510),
.Y(n1477) );
AOI22X1TS U1941 ( .A0(n1514), .A1(n1477), .B0(n1491), .B1(n958), .Y(n488) );
AOI22X1TS U1942 ( .A0(Data_array_SWR[24]), .A1(n940), .B0(n875), .B1(n1478),
.Y(n1479) );
AOI22X1TS U1943 ( .A0(n1514), .A1(n1479), .B0(n1491), .B1(n959), .Y(n487) );
AOI22X1TS U1944 ( .A0(n1514), .A1(n1480), .B0(n1491), .B1(n960), .Y(n486) );
AOI22X1TS U1945 ( .A0(n1514), .A1(n1481), .B0(n1512), .B1(n961), .Y(n485) );
AOI22X1TS U1946 ( .A0(n1509), .A1(n1482), .B0(n1486), .B1(n962), .Y(n484) );
AOI22X1TS U1947 ( .A0(n1514), .A1(n1483), .B0(n966), .B1(n1512), .Y(n483) );
AOI22X1TS U1948 ( .A0(n1514), .A1(n1484), .B0(n1491), .B1(n967), .Y(n482) );
AOI22X1TS U1949 ( .A0(n1509), .A1(n1485), .B0(n1512), .B1(n965), .Y(n481) );
AOI22X1TS U1950 ( .A0(n1509), .A1(n1487), .B0(n1486), .B1(n964), .Y(n480) );
AOI22X1TS U1951 ( .A0(n1509), .A1(n1488), .B0(n963), .B1(n1512), .Y(n479) );
AOI22X1TS U1952 ( .A0(n1509), .A1(n1499), .B0(n1512), .B1(n950), .Y(n472) );
AOI22X1TS U1953 ( .A0(n1509), .A1(n1500), .B0(n1512), .B1(n951), .Y(n471) );
AOI22X1TS U1954 ( .A0(n1509), .A1(n1501), .B0(n1512), .B1(n952), .Y(n470) );
AOI22X1TS U1955 ( .A0(n1514), .A1(n1502), .B0(n1512), .B1(n953), .Y(n469) );
AOI22X1TS U1956 ( .A0(n1514), .A1(n1503), .B0(n1512), .B1(n954), .Y(n468) );
AOI22X1TS U1957 ( .A0(n1514), .A1(n1504), .B0(n1374), .B1(n955), .Y(n467) );
AOI22X1TS U1958 ( .A0(n1514), .A1(n1505), .B0(n1374), .B1(n956), .Y(n466) );
AOI22X1TS U1959 ( .A0(n1514), .A1(n1506), .B0(n1374), .B1(n1599), .Y(n465)
);
AOI22X1TS U1960 ( .A0(n1514), .A1(n1508), .B0(n1374), .B1(n1612), .Y(n464)
);
AOI22X1TS U1961 ( .A0(Data_array_SWR[25]), .A1(n903), .B0(left_right_SHT2),
.B1(n1510), .Y(n1513) );
AOI22X1TS U1962 ( .A0(n1514), .A1(n1513), .B0(n1512), .B1(n1616), .Y(n463)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk20.tcl_GeArN16R4P4_syn.sdf");
endmodule
|
//-----------------------------------------------------------------------------
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
// and the ARM. In the low-frequency modes it passes the data straight
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
// frequency modes, the FPGA might perform some demodulation first, to
// reduce the amount of data that we must send to the ARM.
//
// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
// could be improved.
//
// Jonathan Westhues, March 2006
// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
// iZsh <izsh at fail0verflow.com>, June 2014
//-----------------------------------------------------------------------------
`include "hi_read_tx.v"
`include "hi_read_rx_xcorr.v"
`include "hi_simulate.v"
`include "hi_iso14443a.v"
`include "hi_sniffer.v"
`include "util.v"
`include "hi_flite.v"
module fpga_hf(
input spck, output miso, input mosi, input ncs,
input pck0, input ck_1356meg, input ck_1356megb,
output pwr_lo, output pwr_hi,
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
input [7:0] adc_d, output adc_clk, output adc_noe,
output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
input cross_hi, input cross_lo,
output dbg
);
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg;
reg [7:0] conf_word;
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without
// glitching, or else we will glitch the transmitted carrier.
always @(posedge ncs)
begin
case(shift_reg[15:12])
4'b0001: conf_word <= shift_reg[7:0]; // FPGA_CMD_SET_CONFREG
endcase
end
always @(posedge spck)
begin
if(~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
wire [2:0] major_mode;
assign major_mode = conf_word[7:5];
// For the high-frequency transmit configuration: modulation depth, either
// 100% (just quite driving antenna, steady LOW), or shallower (tri-state
// some fraction of the buffers)
wire hi_read_tx_shallow_modulation = conf_word[0];
// For the high-frequency receive correlator: frequency against which to
// correlate.
wire hi_read_rx_xcorr_848 = conf_word[0];
// and whether to drive the coil (reader) or just short it (snooper)
wire hi_read_rx_xcorr_snoop = conf_word[1];
// divide subcarrier frequency by 4
wire hi_read_rx_xcorr_quarter = conf_word[2];
// For the high-frequency simulated tag: what kind of modulation to use.
wire [2:0] hi_simulate_mod_type = conf_word[2:0];
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
hi_read_tx ht(
pck0, ck_1356meg, ck_1356megb,
ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
adc_d, ht_adc_clk,
ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
cross_hi, cross_lo,
ht_dbg,
hi_read_tx_shallow_modulation
);
hi_read_rx_xcorr hrxc(
pck0, ck_1356meg, ck_1356megb,
hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,
adc_d, hrxc_adc_clk,
hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
cross_hi, cross_lo,
hrxc_dbg,
hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
);
hi_simulate hs(
pck0, ck_1356meg, ck_1356megb,
hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
adc_d, hs_adc_clk,
hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
cross_hi, cross_lo,
hs_dbg,
hi_simulate_mod_type
);
hi_iso14443a hisn(
pck0, ck_1356meg, ck_1356megb,
hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
adc_d, hisn_adc_clk,
hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
cross_hi, cross_lo,
hisn_dbg,
hi_simulate_mod_type
);
hi_sniffer he(
pck0, ck_1356meg, ck_1356megb,
he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
adc_d, he_adc_clk,
he_ssp_frame, he_ssp_din, ssp_dout, he_ssp_clk,
cross_hi, cross_lo,
he_dbg,
hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
);
hi_flite hfl(
pck0, ck_1356meg, ck_1356megb,
hfl_pwr_lo, hfl_pwr_hi, hfl_pwr_oe1, hfl_pwr_oe2, hfl_pwr_oe3, hfl_pwr_oe4,
adc_d, hfl_adc_clk,
hfl_ssp_frame, hfl_ssp_din, ssp_dout, hfl_ssp_clk,
cross_hi, cross_lo,
hfl_dbg,
hi_simulate_mod_type
);
// Major modes:
// 000 -- HF reader, transmitting to tag; modulation depth selectable
// 001 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
// 010 -- HF simulated tag
// 011 -- HF ISO14443-A
// 100 -- HF Snoop
// 101 -- Felica modem, reusing HF reader
// 110 -- none
// 111 -- everything off
mux8 mux_ssp_clk (major_mode, ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, he_ssp_clk, hfl_ssp_clk, 1'b0, 1'b0);
mux8 mux_ssp_din (major_mode, ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, he_ssp_din, hfl_ssp_din, 1'b0, 1'b0);
mux8 mux_ssp_frame (major_mode, ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, he_ssp_frame, hfl_ssp_frame, 1'b0, 1'b0);
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, he_pwr_oe1, hfl_pwr_oe1, 1'b0, 1'b0);
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, he_pwr_oe2, hfl_pwr_oe2, 1'b0, 1'b0);
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, he_pwr_oe3, hfl_pwr_oe3, 1'b0, 1'b0);
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, he_pwr_oe4, hfl_pwr_oe4, 1'b0, 1'b0);
mux8 mux_pwr_lo (major_mode, pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, he_pwr_lo, hfl_pwr_lo, 1'b0, 1'b0);
mux8 mux_pwr_hi (major_mode, pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, he_pwr_hi, hfl_pwr_hi, 1'b0, 1'b0);
mux8 mux_adc_clk (major_mode, adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, he_adc_clk, hfl_adc_clk, 1'b0, 1'b0);
mux8 mux_dbg (major_mode, dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, he_dbg, hfl_dbg, 1'b0, 1'b0);
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A32OI_SYMBOL_V
`define SKY130_FD_SC_HDLL__A32OI_SYMBOL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a32oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A32OI_SYMBOL_V
|
// Generated by DDR3 High Performance Controller 11.0 [Altera, IP Toolbench 1.3.0 Build 208]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2011 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module ddr3_s4_amphy (
local_address,
local_write_req,
local_read_req,
local_burstbegin,
local_wdata,
local_be,
local_size,
oct_ctl_rs_value,
oct_ctl_rt_value,
global_reset_n,
pll_ref_clk,
soft_reset_n,
local_ready,
local_rdata,
local_rdata_valid,
local_refresh_ack,
local_init_done,
reset_phy_clk_n,
dll_reference_clk,
dqs_delay_ctrl_export,
aux_scan_clk_reset_n,
aux_scan_clk,
mem_odt,
mem_cs_n,
mem_cke,
mem_addr,
mem_ba,
mem_ras_n,
mem_cas_n,
mem_we_n,
mem_dm,
mem_reset_n,
phy_clk,
aux_full_rate_clk,
aux_half_rate_clk,
reset_request_n,
mem_clk,
mem_clk_n,
mem_dq,
mem_dqs,
mem_dqsn);
input [23:0] local_address;
input local_write_req;
input local_read_req;
input local_burstbegin;
input [31:0] local_wdata;
input [3:0] local_be;
input [2:0] local_size;
input [13:0] oct_ctl_rs_value;
input [13:0] oct_ctl_rt_value;
input global_reset_n;
input pll_ref_clk;
input soft_reset_n;
output local_ready;
output [31:0] local_rdata;
output local_rdata_valid;
output local_refresh_ack;
output local_init_done;
output reset_phy_clk_n;
output dll_reference_clk;
output [5:0] dqs_delay_ctrl_export;
output aux_scan_clk_reset_n;
output aux_scan_clk;
output [0:0] mem_odt;
output [0:0] mem_cs_n;
output [0:0] mem_cke;
output [12:0] mem_addr;
output [2:0] mem_ba;
output mem_ras_n;
output mem_cas_n;
output mem_we_n;
output [0:0] mem_dm;
output mem_reset_n;
output phy_clk;
output aux_full_rate_clk;
output aux_half_rate_clk;
output reset_request_n;
inout [0:0] mem_clk;
inout [0:0] mem_clk_n;
inout [7:0] mem_dq;
inout [0:0] mem_dqs;
inout [0:0] mem_dqsn;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:07:08 03/14/2015
// Design Name:
// Module Name: deserializer_gen_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module deserializer_gen_test(
output rxd,
output clk
);
reg rxd_buf;
reg clk_buf;
reg [7:0] data_buf;
assign clk = clk_buf;
assign rxd = rxd_buf;
integer data_src;
integer i;
integer j;
initial
begin
rxd_buf = 0;
clk_buf = 1;
data_src = $fopen("test_serializer/data/serial_vector.txt", "rb");
#100;
for(i = 0; i < 16*(8+4); i = i + 1)
begin
#1;
data_buf = $fgetc(data_src);
if(data_buf == "1") rxd_buf = 1;
if(data_buf == "0") rxd_buf = 0;
#1;
clk_buf = 0;
#2;
clk_buf = 1;
end
#2;
clk_buf = 0;
#2;
clk_buf = 1;
#2;
clk_buf = 0;
#2;
clk_buf = 1;
#2;
clk_buf = 0;
#2;
clk_buf = 1;
$fclose(data_src);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBN_TB_V
`define SKY130_FD_SC_LP__DLXBN_TB_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlxbn.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_lp__dlxbn dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE_N(GATE_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBN_TB_V
|
module jaxa (
autostart_external_connection_export,
clk_clk,
controlflagsin_external_connection_export,
controlflagsout_external_connection_export,
creditcount_external_connection_export,
errorstatus_external_connection_export,
linkdisable_external_connection_export,
linkstart_external_connection_export,
linkstatus_external_connection_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
outstandingcount_external_connection_export,
pll_0_outclk0_clk,
receiveactivity_external_connection_export,
receiveclock_external_connection_export,
receivefifodatacount_external_connection_export,
receivefifodataout_external_connection_export,
receivefifoempty_external_connection_export,
receivefifofull_external_connection_export,
receivefiforeadenable_external_connection_export,
spacewiredatain_external_connection_export,
spacewiredataout_external_connection_export,
spacewirestrobein_external_connection_export,
spacewirestrobeout_external_connection_export,
statisticalinformation_0_external_connection_export,
statisticalinformation_1_external_connection_export,
statisticalinformationclear_external_connection_export,
tickin_external_connection_export,
tickout_external_connection_export,
timein_external_connection_export,
timeout_external_connection_export,
transmitactivity_external_connection_export,
transmitclock_external_connection_export,
transmitclockdividevalue_external_connection_export,
transmitfifodatacount_external_connection_export,
transmitfifodatain_external_connection_export,
transmitfifofull_external_connection_export,
transmitfifowriteenable_external_connection_export);
output autostart_external_connection_export;
input clk_clk;
output [1:0] controlflagsin_external_connection_export;
input [1:0] controlflagsout_external_connection_export;
input [5:0] creditcount_external_connection_export;
input [7:0] errorstatus_external_connection_export;
output linkdisable_external_connection_export;
output linkstart_external_connection_export;
input [15:0] linkstatus_external_connection_export;
output [12:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [7:0] memory_mem_dq;
inout memory_mem_dqs;
inout memory_mem_dqs_n;
output memory_mem_odt;
output memory_mem_dm;
input memory_oct_rzqin;
input [5:0] outstandingcount_external_connection_export;
output pll_0_outclk0_clk;
input receiveactivity_external_connection_export;
output receiveclock_external_connection_export;
input receivefifodatacount_external_connection_export;
input [8:0] receivefifodataout_external_connection_export;
input receivefifoempty_external_connection_export;
input receivefifofull_external_connection_export;
output receivefiforeadenable_external_connection_export;
output spacewiredatain_external_connection_export;
input spacewiredataout_external_connection_export;
output spacewirestrobein_external_connection_export;
input spacewirestrobeout_external_connection_export;
input [31:0] statisticalinformation_0_external_connection_export;
output [7:0] statisticalinformation_1_external_connection_export;
output statisticalinformationclear_external_connection_export;
output tickin_external_connection_export;
input tickout_external_connection_export;
output [5:0] timein_external_connection_export;
input [5:0] timeout_external_connection_export;
input transmitactivity_external_connection_export;
output transmitclock_external_connection_export;
output [5:0] transmitclockdividevalue_external_connection_export;
input [5:0] transmitfifodatacount_external_connection_export;
output [8:0] transmitfifodatain_external_connection_export;
input transmitfifofull_external_connection_export;
output transmitfifowriteenable_external_connection_export;
endmodule
|
(** * Poly: Polymorphism and Higher-Order Functions *)
(** In this chapter we continue our development of basic
concepts of functional programming. The critical new ideas are
_polymorphism_ (abstracting functions over the types of the data
they manipulate) and _higher-order functions_ (treating functions
as data).
*)
Require Export Lists.
(* ###################################################### *)
(** * Polymorphism *)
(* ###################################################### *)
(** ** Polymorphic Lists *)
(** For the last couple of chapters, we've been working just
with lists of numbers. Obviously, interesting programs also need
to be able to manipulate lists with elements from other types --
lists of strings, lists of booleans, lists of lists, etc. We
_could_ just define a new inductive datatype for each of these,
for example... *)
Inductive boollist : Type :=
| bool_nil : boollist
| bool_cons : bool -> boollist -> boollist.
(** ... but this would quickly become tedious, partly because we
have to make up different constructor names for each datatype, but
mostly because we would also need to define new versions of all
our list manipulating functions ([length], [rev], etc.) for each
new datatype definition. *)
(** *** *)
(** To avoid all this repetition, Coq supports _polymorphic_
inductive type definitions. For example, here is a _polymorphic
list_ datatype. *)
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
(** This is exactly like the definition of [natlist] from the
previous chapter, except that the [nat] argument to the [cons]
constructor has been replaced by an arbitrary type [X], a binding
for [X] has been added to the header, and the occurrences of
[natlist] in the types of the constructors have been replaced by
[list X]. (We can re-use the constructor names [nil] and [cons]
because the earlier definition of [natlist] was inside of a
[Module] definition that is now out of scope.) *)
(** What sort of thing is [list] itself? One good way to think
about it is that [list] is a _function_ from [Type]s to
[Inductive] definitions; or, to put it another way, [list] is a
function from [Type]s to [Type]s. For any particular type [X],
the type [list X] is an [Inductive]ly defined set of lists whose
elements are things of type [X]. *)
(** With this definition, when we use the constructors [nil] and
[cons] to build lists, we need to tell Coq the type of the
elements in the lists we are building -- that is, [nil] and [cons]
are now _polymorphic constructors_. Observe the types of these
constructors: *)
Check nil.
(* ===> nil : forall X : Type, list X *)
Check cons.
(* ===> cons : forall X : Type, X -> list X -> list X *)
(** The "[forall X]" in these types can be read as an additional
argument to the constructors that determines the expected types of
the arguments that follow. When [nil] and [cons] are used, these
arguments are supplied in the same way as the others. For
example, the list containing [2] and [1] is written like this: *)
Check (cons nat 2 (cons nat 1 (nil nat))).
(** (We've gone back to writing [nil] and [cons] explicitly here
because we haven't yet defined the [ [] ] and [::] notations for
the new version of lists. We'll do that in a bit.) *)
(** We can now go back and make polymorphic (or "generic")
versions of all the list-processing functions that we wrote
before. Here is [length], for example: *)
(** *** *)
Fixpoint length (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length X t)
end.
(** Note that the uses of [nil] and [cons] in [match] patterns
do not require any type annotations: Coq already knows that the list
[l] contains elements of type [X], so there's no reason to include
[X] in the pattern. (More precisely, the type [X] is a parameter
of the whole definition of [list], not of the individual
constructors. We'll come back to this point later.)
As with [nil] and [cons], we can use [length] by applying it first
to a type and then to its list argument: *)
Example test_length1 :
length nat (cons nat 1 (cons nat 2 (nil nat))) = 2.
Proof. reflexivity. Qed.
(** To use our length with other kinds of lists, we simply
instantiate it with an appropriate type parameter: *)
Example test_length2 :
length bool (cons bool true (nil bool)) = 1.
Proof. reflexivity. Qed.
(** *** *)
(** Let's close this subsection by re-implementing a few other
standard list functions on our new polymorphic lists: *)
Fixpoint app (X : Type) (l1 l2 : list X)
: (list X) :=
match l1 with
| nil => l2
| cons h t => cons X h (app X t l2)
end.
Fixpoint snoc (X:Type) (l:list X) (v:X) : (list X) :=
match l with
| nil => cons X v (nil X)
| cons h t => cons X h (snoc X t v)
end.
Fixpoint rev (X:Type) (l:list X) : list X :=
match l with
| nil => nil X
| cons h t => snoc X (rev X t) h
end.
Example test_rev1 :
rev nat (cons nat 1 (cons nat 2 (nil nat)))
= (cons nat 2 (cons nat 1 (nil nat))).
Proof. reflexivity. Qed.
Example test_rev2:
rev bool (nil bool) = nil bool.
Proof. reflexivity. Qed.
Module MumbleBaz.
(** **** Exercise: 2 stars (mumble_grumble) *)
(** Consider the following two inductively defined types. *)
Inductive mumble : Type :=
| a : mumble
| b : mumble -> nat -> mumble
| c : mumble.
Inductive grumble (X:Type) : Type :=
| d : mumble -> grumble X
| e : X -> grumble X.
(** Which of the following are well-typed elements of [grumble X] for
some type [X]?
- [d (b a 5)]
- [d mumble (b a 5)]
- [d bool (b a 5)]
- [e bool true]
- [e mumble (b c 0)]
- [e bool (b c 0)]
- [c]
(* FILL IN HERE *)
d (b a 5) - no, because type is missing
d mumble (b a 5) : grumble mumble
d bool (b a 5) : grumble bool
e bool true : grumble bool
e mumble (b c 0) : grumble mumble
e bool (b c 0) - no, parameter has wrong type.
c : mumble
*)
(** [] *)
(** **** Exercise: 2 stars (baz_num_elts) *)
(** Consider the following inductive definition: *)
Inductive baz : Type :=
| x : baz -> baz
| y : baz -> bool -> baz.
(** How _many_ elements does the type [baz] have?
(* FILL IN HERE *)
0 because it cannot be instantiated.
*)
(** [] *)
End MumbleBaz.
(* ###################################################### *)
(** *** Type Annotation Inference *)
(** Let's write the definition of [app] again, but this time we won't
specify the types of any of the arguments. Will Coq still accept
it? *)
Fixpoint app' X l1 l2 : list X :=
match l1 with
| nil => l2
| cons h t => cons X h (app' X t l2)
end.
(** Indeed it will. Let's see what type Coq has assigned to [app']: *)
Check app'.
(* ===> forall X : Type, list X -> list X -> list X *)
Check app.
(* ===> forall X : Type, list X -> list X -> list X *)
(** It has exactly the same type type as [app]. Coq was able to
use a process called _type inference_ to deduce what the types of
[X], [l1], and [l2] must be, based on how they are used. For
example, since [X] is used as an argument to [cons], it must be a
[Type], since [cons] expects a [Type] as its first argument;
matching [l1] with [nil] and [cons] means it must be a [list]; and
so on.
This powerful facility means we don't always have to write
explicit type annotations everywhere, although explicit type
annotations are still quite useful as documentation and sanity
checks. You should try to find a balance in your own code between
too many type annotations (so many that they clutter and distract)
and too few (which forces readers to perform type inference in
their heads in order to understand your code). *)
(* ###################################################### *)
(** *** Type Argument Synthesis *)
(** Whenever we use a polymorphic function, we need to pass it
one or more types in addition to its other arguments. For
example, the recursive call in the body of the [length] function
above must pass along the type [X]. But just like providing
explicit type annotations everywhere, this is heavy and verbose.
Since the second argument to [length] is a list of [X]s, it seems
entirely obvious that the first argument can only be [X] -- why
should we have to write it explicitly?
Fortunately, Coq permits us to avoid this kind of redundancy. In
place of any type argument we can write the "implicit argument"
[_], which can be read as "Please figure out for yourself what
type belongs here." More precisely, when Coq encounters a [_], it
will attempt to _unify_ all locally available information -- the
type of the function being applied, the types of the other
arguments, and the type expected by the context in which the
application appears -- to determine what concrete type should
replace the [_].
This may sound similar to type annotation inference -- and,
indeed, the two procedures rely on the same underlying mechanisms.
Instead of simply omitting the types of some arguments to a
function, like
app' X l1 l2 : list X :=
we can also replace the types with [_], like
app' (X : _) (l1 l2 : _) : list X :=
which tells Coq to attempt to infer the missing information, just
as with argument synthesis.
Using implicit arguments, the [length] function can be written
like this: *)
Fixpoint length' (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length' _ t)
end.
(** In this instance, we don't save much by writing [_] instead of
[X]. But in many cases the difference can be significant. For
example, suppose we want to write down a list containing the
numbers [1], [2], and [3]. Instead of writing this... *)
Definition list123 :=
cons nat 1 (cons nat 2 (cons nat 3 (nil nat))).
(** ...we can use argument synthesis to write this: *)
Definition list123' := cons _ 1 (cons _ 2 (cons _ 3 (nil _))).
(* ###################################################### *)
(** *** Implicit Arguments *)
(** In fact, we can go further. To avoid having to sprinkle [_]'s
throughout our programs, we can tell Coq _always_ to infer the
type argument(s) of a given function. The [Arguments] directive
specifies the name of the function or constructor, and then lists
its argument names, with curly braces around any arguments to be
treated as implicit.
*)
Arguments nil {X}.
Arguments cons {X} _ _. (* use underscore for argument position that has no name *)
Arguments length {X} l.
Arguments app {X} l1 l2.
Arguments rev {X} l.
Arguments snoc {X} l v.
(* note: no _ arguments required... *)
Definition list123'' := cons 1 (cons 2 (cons 3 nil)).
Check (length list123'').
(** *** *)
(** Alternatively, we can declare an argument to be implicit while
defining the function itself, by surrounding the argument in curly
braces. For example: *)
Fixpoint length'' {X:Type} (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length'' t)
end.
(** (Note that we didn't even have to provide a type argument to
the recursive call to [length'']; indeed, it is invalid to provide
one.) We will use this style whenever possible, although we will
continue to use use explicit [Argument] declarations for
[Inductive] constructors. *)
(** *** *)
(** One small problem with declaring arguments [Implicit] is
that, occasionally, Coq does not have enough local information to
determine a type argument; in such cases, we need to tell Coq that
we want to give the argument explicitly this time, even though
we've globally declared it to be [Implicit]. For example, suppose we
write this: *)
(* Definition mynil := nil. *)
(** If we uncomment this definition, Coq will give us an error,
because it doesn't know what type argument to supply to [nil]. We
can help it by providing an explicit type declaration (so that Coq
has more information available when it gets to the "application"
of [nil]): *)
Definition mynil : list nat := nil.
(** Alternatively, we can force the implicit arguments to be explicit by
prefixing the function name with [@]. *)
Check @nil.
Definition mynil' := @nil nat.
(** *** *)
(** Using argument synthesis and implicit arguments, we can
define convenient notation for lists, as before. Since we have
made the constructor type arguments implicit, Coq will know to
automatically infer these when we use the notations. *)
Notation "x :: y" := (cons x y)
(at level 60, right associativity).
Notation "[ ]" := nil.
Notation "[ x ; .. ; y ]" := (cons x .. (cons y []) ..).
Notation "x ++ y" := (app x y)
(at level 60, right associativity).
(** Now lists can be written just the way we'd hope: *)
Definition list123''' := [1; 2; 3].
(* ###################################################### *)
(** *** Exercises: Polymorphic Lists *)
(** **** Exercise: 2 stars, optional (poly_exercises) *)
(** Here are a few simple exercises, just like ones in the [Lists]
chapter, for practice with polymorphism. Fill in the definitions
and complete the proofs below. *)
Fixpoint repeat {X : Type} (n : X) (count : nat) : list X :=
match count with
| 0 => []
| S count' => n :: repeat n count'
end.
Example test_repeat1:
repeat true 2 = cons true (cons true nil).
Proof. reflexivity. Qed.
Theorem nil_app : forall X:Type, forall l:list X,
app [] l = l.
Proof.
intros X l. reflexivity.
Qed.
Theorem rev_snoc : forall X : Type,
forall v : X,
forall s : list X,
rev (snoc s v) = v :: (rev s).
Proof.
intros X v s. induction s.
reflexivity.
simpl. rewrite -> IHs. simpl. reflexivity.
Qed.
Theorem rev_involutive : forall X : Type, forall l : list X,
rev (rev l) = l.
Proof.
intros X l. induction l. reflexivity.
simpl. rewrite -> rev_snoc. rewrite -> IHl. reflexivity.
Qed.
Theorem snoc_with_append : forall X : Type,
forall l1 l2 : list X,
forall v : X,
snoc (l1 ++ l2) v = l1 ++ (snoc l2 v).
Proof.
intros X l1 l2 v. induction l1. reflexivity.
simpl. rewrite -> IHl1. reflexivity.
Qed.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Pairs *)
(** Following the same pattern, the type definition we gave in
the last chapter for pairs of numbers can be generalized to
_polymorphic pairs_ (or _products_): *)
Inductive prod (X Y : Type) : Type :=
pair : X -> Y -> prod X Y.
Arguments pair {X} {Y} _ _.
(** As with lists, we make the type arguments implicit and define the
familiar concrete notation. *)
Notation "( x , y )" := (pair x y).
(** We can also use the [Notation] mechanism to define the standard
notation for pair _types_: *)
Notation "X * Y" := (prod X Y) : type_scope.
(** (The annotation [: type_scope] tells Coq that this abbreviation
should be used when parsing types. This avoids a clash with the
multiplication symbol.) *)
(** *** *)
(** A note of caution: it is easy at first to get [(x,y)] and
[X*Y] confused. Remember that [(x,y)] is a _value_ built from two
other values; [X*Y] is a _type_ built from two other types. If
[x] has type [X] and [y] has type [Y], then [(x,y)] has type
[X*Y]. *)
(** The first and second projection functions now look pretty
much as they would in any functional programming language. *)
Definition fst {X Y : Type} (p : X * Y) : X :=
match p with (x,y) => x end.
Definition snd {X Y : Type} (p : X * Y) : Y :=
match p with (x,y) => y end.
(** The following function takes two lists and combines them
into a list of pairs. In many functional programming languages,
it is called [zip]. We call it [combine] for consistency with
Coq's standard library. *)
(** Note that the pair notation can be used both in expressions and in
patterns... *)
Fixpoint combine {X Y : Type} (lx : list X) (ly : list Y)
: list (X*Y) :=
match (lx,ly) with
| ([],_) => []
| (_,[]) => []
| (x::tx, y::ty) => (x,y) :: (combine tx ty)
end.
(** **** Exercise: 1 star, optional (combine_checks) *)
(** Try answering the following questions on paper and
checking your answers in coq:
- What is the type of [combine] (i.e., what does [Check
@combine] print?)
[combine : forall X Y : Type, list X -> list Y -> list (X * Y)]
- What does
Eval compute in (combine [1;2] [false;false;true;true])
print? [(1,false),(2,false)]
*)
(** **** Exercise: 2 stars (split) *)
(** The function [split] is the right inverse of combine: it takes a
list of pairs and returns a pair of lists. In many functional
programing languages, this function is called [unzip].
Uncomment the material below and fill in the definition of
[split]. Make sure it passes the given unit tests. *)
Fixpoint split {X Y : Type} (l : list (X*Y)) : (list X) * (list Y) :=
match l with
| [] => ([], [])
| (x, y)::l' => match split l' with (lx, ly) => (x::lx, y::ly) end
end.
Example test_split:
split [(1,false);(2,false)] = ([1;2],[false;false]).
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Options *)
(** One last polymorphic type for now: _polymorphic options_.
The type declaration generalizes the one for [natoption] in the
previous chapter: *)
Inductive option (X:Type) : Type :=
| Some : X -> option X
| None : option X.
Arguments Some {X} _.
Arguments None {X}.
(** *** *)
(** We can now rewrite the [index] function so that it works
with any type of lists. *)
Fixpoint index {X : Type} (n : nat)
(l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Example test_index1 : index 0 [4;5;6;7] = Some 4.
Proof. reflexivity. Qed.
Example test_index2 : index 1 [[1];[2]] = Some [2].
Proof. reflexivity. Qed.
Example test_index3 : index 2 [true] = None.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, optional (hd_opt_poly) *)
(** Complete the definition of a polymorphic version of the
[hd_opt] function from the last chapter. Be sure that it
passes the unit tests below. *)
Definition hd_opt {X : Type} (l : list X) : option X :=
match l with
| [] => None
| x::_ => Some x
end.
(** Once again, to force the implicit arguments to be explicit,
we can use [@] before the name of the function. *)
Check @hd_opt.
Example test_hd_opt1 : hd_opt [1;2] = Some 1.
Proof. reflexivity. Admitted.
Example test_hd_opt2 : hd_opt [[1];[2]] = Some [1].
Proof. reflexivity. Admitted.
(** [] *)
(* ###################################################### *)
(** * Functions as Data *)
(* ###################################################### *)
(** ** Higher-Order Functions *)
(** Like many other modern programming languages -- including
all _functional languages_ (ML, Haskell, Scheme, etc.) -- Coq
treats functions as first-class citizens, allowing functions to be
passed as arguments to other functions, returned as results,
stored in data structures, etc.
Functions that manipulate other functions are often called
_higher-order_ functions. Here's a simple one: *)
Definition doit3times {X:Type} (f:X->X) (n:X) : X :=
f (f (f n)).
(** The argument [f] here is itself a function (from [X] to
[X]); the body of [doit3times] applies [f] three times to some
value [n]. *)
Check @doit3times.
(* ===> doit3times : forall X : Type, (X -> X) -> X -> X *)
Example test_doit3times: doit3times minustwo 9 = 3.
Proof. reflexivity. Qed.
Example test_doit3times': doit3times negb true = false.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Partial Application *)
(** In fact, the multiple-argument functions we have already
seen are also examples of passing functions as data. To see why,
recall the type of [plus]. *)
Check plus.
(* ==> nat -> nat -> nat *)
(** Each [->] in this expression is actually a _binary_ operator
on types. (This is the same as saying that Coq primitively
supports only one-argument functions -- do you see why?) This
operator is _right-associative_, so the type of [plus] is really a
shorthand for [nat -> (nat -> nat)] -- i.e., it can be read as
saying that "[plus] is a one-argument function that takes a [nat]
and returns a one-argument function that takes another [nat] and
returns a [nat]." In the examples above, we have always applied
[plus] to both of its arguments at once, but if we like we can
supply just the first. This is called _partial application_. *)
Definition plus3 := plus 3.
Check plus3.
Example test_plus3 : plus3 4 = 7.
Proof. reflexivity. Qed.
Example test_plus3' : doit3times plus3 0 = 9.
Proof. reflexivity. Qed.
Example test_plus3'' : doit3times (plus 3) 0 = 9.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Digression: Currying *)
(** **** Exercise: 2 stars, advanced (currying) *)
(** In Coq, a function [f : A -> B -> C] really has the type [A
-> (B -> C)]. That is, if you give [f] a value of type [A], it
will give you function [f' : B -> C]. If you then give [f'] a
value of type [B], it will return a value of type [C]. This
allows for partial application, as in [plus3]. Processing a list
of arguments with functions that return functions is called
_currying_, in honor of the logician Haskell Curry.
Conversely, we can reinterpret the type [A -> B -> C] as [(A *
B) -> C]. This is called _uncurrying_. With an uncurried binary
function, both arguments must be given at once as a pair; there is
no partial application. *)
(** We can define currying as follows: *)
Definition prod_curry {X Y Z : Type}
(f : X * Y -> Z) (x : X) (y : Y) : Z := f (x, y).
(** As an exercise, define its inverse, [prod_uncurry]. Then prove
the theorems below to show that the two are inverses. *)
Definition prod_uncurry {X Y Z : Type}
(f : X -> Y -> Z) (p : X * Y) : Z := f (fst p) (snd p).
(** (Thought exercise: before running these commands, can you
calculate the types of [prod_curry] and [prod_uncurry]?) *)
Check @prod_curry.
Check @prod_uncurry.
Theorem uncurry_curry : forall (X Y Z : Type) (f : X -> Y -> Z) x y,
prod_curry (prod_uncurry f) x y = f x y.
Proof. intros X Y Z f x y. reflexivity. Qed.
Theorem curry_uncurry : forall (X Y Z : Type)
(f : (X * Y) -> Z) (p : X * Y),
prod_uncurry (prod_curry f) p = f p.
Proof. intros X Y Z f p. destruct p. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Filter *)
(** Here is a useful higher-order function, which takes a list
of [X]s and a _predicate_ on [X] (a function from [X] to [bool])
and "filters" the list, returning a new list containing just those
elements for which the predicate returns [true]. *)
Fixpoint filter {X:Type} (test: X->bool) (l:list X)
: (list X) :=
match l with
| [] => []
| h :: t => if test h then h :: (filter test t)
else filter test t
end.
(** For example, if we apply [filter] to the predicate [evenb]
and a list of numbers [l], it returns a list containing just the
even members of [l]. *)
Example test_filter1: filter evenb [1;2;3;4] = [2;4].
Proof. reflexivity. Qed.
(** *** *)
Definition length_is_1 {X : Type} (l : list X) : bool :=
beq_nat (length l) 1.
Example test_filter2:
filter length_is_1
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** *** *)
(** We can use [filter] to give a concise version of the
[countoddmembers] function from the [Lists] chapter. *)
Definition countoddmembers' (l:list nat) : nat :=
length (filter oddb l).
Example test_countoddmembers'1: countoddmembers' [1;0;3;1;4;5] = 4.
Proof. reflexivity. Qed.
Example test_countoddmembers'2: countoddmembers' [0;2;4] = 0.
Proof. reflexivity. Qed.
Example test_countoddmembers'3: countoddmembers' nil = 0.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Anonymous Functions *)
(** It is a little annoying to be forced to define the function
[length_is_1] and give it a name just to be able to pass it as an
argument to [filter], since we will probably never use it again.
Moreover, this is not an isolated example. When using
higher-order functions, we often want to pass as arguments
"one-off" functions that we will never use again; having to give
each of these functions a name would be tedious.
Fortunately, there is a better way. It is also possible to
construct a function "on the fly" without declaring it at the top
level or giving it a name; this is analogous to the notation we've
been using for writing down constant lists, natural numbers, and
so on. *)
Example test_anon_fun':
doit3times (fun n => n * n) 2 = 256.
Proof. reflexivity. Qed.
(** Here is the motivating example from before, rewritten to use
an anonymous function. *)
Example test_filter2':
filter (fun l => beq_nat (length l) 1)
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (filter_even_gt7) *)
(** Use [filter] (instead of [Fixpoint]) to write a Coq function
[filter_even_gt7] that takes a list of natural numbers as input
and returns a list of just those that are even and greater than
7. *)
Definition filter_even_gt7 (l : list nat) : list nat :=
filter (fun n => andb (blt_nat 7 n) (evenb n)) l.
Example test_filter_even_gt7_1 :
filter_even_gt7 [1;2;6;9;10;3;12;8] = [10;12;8].
Proof. reflexivity. Qed.
Example test_filter_even_gt7_2 :
filter_even_gt7 [5;2;6;19;129] = [].
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars (partition) *)
(** Use [filter] to write a Coq function [partition]:
partition : forall X : Type,
(X -> bool) -> list X -> list X * list X
Given a set [X], a test function of type [X -> bool] and a [list
X], [partition] should return a pair of lists. The first member of
the pair is the sublist of the original list containing the
elements that satisfy the test, and the second is the sublist
containing those that fail the test. The order of elements in the
two sublists should be the same as their order in the original
list.
*)
Definition partition {X : Type} (test : X -> bool) (l : list X)
: list X * list X :=
(filter (fun x => test x) l, filter (fun x => negb (test x)) l).
Example test_partition1: partition oddb [1;2;3;4;5] = ([1;3;5], [2;4]).
Proof. reflexivity. Qed.
Example test_partition2: partition (fun x => false) [5;9;0] = ([], [5;9;0]).
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Map *)
(** Another handy higher-order function is called [map]. *)
Fixpoint map {X Y:Type} (f:X->Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| h :: t => (f h) :: (map f t)
end.
(** *** *)
(** It takes a function [f] and a list [ l = [n1, n2, n3, ...] ]
and returns the list [ [f n1, f n2, f n3,...] ], where [f] has
been applied to each element of [l] in turn. For example: *)
Example test_map1: map (plus 3) [2;0;2] = [5;3;5].
Proof. reflexivity. Qed.
(** The element types of the input and output lists need not be
the same ([map] takes _two_ type arguments, [X] and [Y]). This
version of [map] can thus be applied to a list of numbers and a
function from numbers to booleans to yield a list of booleans: *)
Example test_map2: map oddb [2;1;2;5] = [false;true;false;true].
Proof. reflexivity. Qed.
(** It can even be applied to a list of numbers and
a function from numbers to _lists_ of booleans to
yield a list of lists of booleans: *)
Example test_map3:
map (fun n => [evenb n;oddb n]) [2;1;2;5]
= [[true;false];[false;true];[true;false];[false;true]].
Proof. reflexivity. Qed.
(** ** Map for options *)
(** **** Exercise: 3 stars (map_rev) *)
(** Show that [map] and [rev] commute. You may need to define an
auxiliary lemma. *)
Lemma snoc_app : forall (X: Type) (l: list X) (x: X),
snoc l x = l ++ [x].
Proof.
intros X l x. induction l. reflexivity.
simpl. rewrite -> IHl. reflexivity.
Qed.
Lemma fmap_app : forall (X Y: Type) (f: X -> Y) (l1: list X) (l2: list X),
map f (l1 ++ l2) = map f l1 ++ map f l2.
Proof.
intros X Y f l1 l2. induction l1. reflexivity.
simpl. rewrite -> IHl1. reflexivity.
Qed.
Theorem map_rev : forall (X Y : Type) (f : X -> Y) (l : list X),
map f (rev l) = rev (map f l).
Proof.
intros X Y f l. induction l. reflexivity.
simpl. rewrite -> snoc_app. rewrite -> snoc_app.
rewrite -> fmap_app. rewrite IHl. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars (flat_map) *)
(** The function [map] maps a [list X] to a [list Y] using a function
of type [X -> Y]. We can define a similar function, [flat_map],
which maps a [list X] to a [list Y] using a function [f] of type
[X -> list Y]. Your definition should work by 'flattening' the
results of [f], like so:
flat_map (fun n => [n;n+1;n+2]) [1;5;10]
= [1; 2; 3; 5; 6; 7; 10; 11; 12].
*)
Fixpoint foldr {X Y: Type}
(f: X -> Y -> Y)
(y: Y)
(l: list X) : Y :=
match l with
| [] => y
| x::xs => f x (foldr f y xs)
end.
Fixpoint flat_map {X Y:Type} (f:X -> list Y) (l:list X)
: (list Y) :=
foldr app [] (map f l).
Example test_flat_map1:
flat_map (fun n => [n;n;n]) [1;5;4]
= [1; 1; 1; 5; 5; 5; 4; 4; 4].
Proof. reflexivity. Qed.
(** [] *)
(** Lists are not the only inductive type that we can write a
[map] function for. Here is the definition of [map] for the
[option] type: *)
Definition option_map {X Y : Type} (f : X -> Y) (xo : option X)
: option Y :=
match xo with
| None => None
| Some x => Some (f x)
end.
(** **** Exercise: 2 stars, optional (implicit_args) *)
(** The definitions and uses of [filter] and [map] use implicit
arguments in many places. Replace the curly braces around the
implicit arguments with parentheses, and then fill in explicit
type parameters where necessary and use Coq to check that you've
done so correctly. (This exercise is not to be turned in; it is
probably easiest to do it on a _copy_ of this file that you can
throw away afterwards.) [] *)
(* ###################################################### *)
(** ** Fold *)
(** An even more powerful higher-order function is called
[fold]. This function is the inspiration for the "[reduce]"
operation that lies at the heart of Google's map/reduce
distributed programming framework. *)
Fixpoint fold {X Y:Type} (f: X->Y->Y) (l:list X) (b:Y) : Y :=
match l with
| nil => b
| h :: t => f h (fold f t b)
end.
(** *** *)
(** Intuitively, the behavior of the [fold] operation is to
insert a given binary operator [f] between every pair of elements
in a given list. For example, [ fold plus [1;2;3;4] ] intuitively
means [1+2+3+4]. To make this precise, we also need a "starting
element" that serves as the initial second input to [f]. So, for
example,
fold plus [1;2;3;4] 0
yields
1 + (2 + (3 + (4 + 0))).
Here are some more examples:
*)
Check (fold andb).
(* ===> fold andb : list bool -> bool -> bool *)
Example fold_example1 : fold mult [1;2;3;4] 1 = 24.
Proof. reflexivity. Qed.
Example fold_example2 : fold andb [true;true;false;true] true = false.
Proof. reflexivity. Qed.
Example fold_example3 : fold app [[1];[];[2;3];[4]] [] = [1;2;3;4].
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, advanced (fold_types_different) *)
(** Observe that the type of [fold] is parameterized by _two_ type
variables, [X] and [Y], and the parameter [f] is a binary operator
that takes an [X] and a [Y] and returns a [Y]. Can you think of a
situation where it would be useful for [X] and [Y] to be
different? *)
(* ###################################################### *)
(** ** Functions For Constructing Functions *)
(** Most of the higher-order functions we have talked about so
far take functions as _arguments_. Now let's look at some
examples involving _returning_ functions as the results of other
functions.
To begin, here is a function that takes a value [x] (drawn from
some type [X]) and returns a function from [nat] to [X] that
yields [x] whenever it is called, ignoring its [nat] argument. *)
Definition constfun {X: Type} (x: X) : nat->X :=
fun (k:nat) => x.
Definition ftrue := constfun true.
Example constfun_example1 : ftrue 0 = true.
Proof. reflexivity. Qed.
Example constfun_example2 : (constfun 5) 99 = 5.
Proof. reflexivity. Qed.
(** *** *)
(** Similarly, but a bit more interestingly, here is a function
that takes a function [f] from numbers to some type [X], a number
[k], and a value [x], and constructs a function that behaves
exactly like [f] except that, when called with the argument [k],
it returns [x]. *)
Definition override {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if beq_nat k k' then x else f k'.
(** For example, we can apply [override] twice to obtain a
function from numbers to booleans that returns [false] on [1] and
[3] and returns [true] on all other arguments. *)
Definition fmostlytrue := override (override ftrue 1 false) 3 false.
(** *** *)
Example override_example1 : fmostlytrue 0 = true.
Proof. reflexivity. Qed.
Example override_example2 : fmostlytrue 1 = false.
Proof. reflexivity. Qed.
Example override_example3 : fmostlytrue 2 = true.
Proof. reflexivity. Qed.
Example override_example4 : fmostlytrue 3 = false.
Proof. reflexivity. Qed.
(** *** *)
(** **** Exercise: 1 star (override_example) *)
(** Before starting to work on the following proof, make sure you
understand exactly what the theorem is saying and can paraphrase
it in your own words. The proof itself is straightforward. *)
Theorem override_example : forall (b:bool),
(override (constfun b) 3 true) 2 = b.
Proof.
intros b. destruct b. reflexivity. reflexivity.
Qed.
(** [] *)
(** We'll use function overriding heavily in parts of the rest of the
course, and we will end up needing to know quite a bit about its
properties. To prove these properties, though, we need to know
about a few more of Coq's tactics; developing these is the main
topic of the next chapter. For now, though, let's introduce just
one very useful tactic that will also help us with proving
properties of some of the other functions we have introduced in
this chapter. *)
(* ###################################################### *)
(* ###################################################### *)
(** * The [unfold] Tactic *)
(** Sometimes, a proof will get stuck because Coq doesn't
automatically expand a function call into its definition. (This
is a feature, not a bug: if Coq automatically expanded everything
possible, our proof goals would quickly become enormous -- hard to
read and slow for Coq to manipulate!) *)
Theorem unfold_example_bad : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
(* At this point, we'd like to do [rewrite -> H], since
[plus3 n] is definitionally equal to [3 + n]. However,
Coq doesn't automatically expand [plus3 n] to its
definition. *)
Abort.
(** The [unfold] tactic can be used to explicitly replace a
defined name by the right-hand side of its definition. *)
Theorem unfold_example : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
unfold plus3.
rewrite -> H.
reflexivity. Qed.
(** Now we can prove a first property of [override]: If we
override a function at some argument [k] and then look up [k], we
get back the overridden value. *)
Theorem override_eq : forall {X:Type} x k (f:nat->X),
(override f k x) k = x.
Proof.
intros X x k f.
unfold override.
rewrite <- beq_nat_refl.
reflexivity. Qed.
(** This proof was straightforward, but note that it requires
[unfold] to expand the definition of [override]. *)
(** **** Exercise: 2 stars (override_neq) *)
Theorem override_neq : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
f k1 = x1 ->
beq_nat k2 k1 = false ->
(override f k2 x2) k1 = x1.
Proof.
intros X x1 x2 k1 k2 f H1 H2.
unfold override. rewrite -> H2. rewrite -> H1. reflexivity.
Qed.
(** [] *)
(** As the inverse of [unfold], Coq also provides a tactic
[fold], which can be used to "unexpand" a definition. It is used
much less often. *)
(* ##################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 2 stars (fold_length) *)
(** Many common functions on lists can be implemented in terms of
[fold]. For example, here is an alternative definition of [length]: *)
Definition fold_length {X : Type} (l : list X) : nat :=
fold (fun _ n => S n) l 0.
Example test_fold_length1 : fold_length [4;7;0] = 3.
Proof. reflexivity. Qed.
(** Prove the correctness of [fold_length]. *)
Theorem fold_length_correct : forall X (l : list X),
fold_length l = length l.
intros X l. induction l. reflexivity.
simpl. rewrite <- IHl. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (fold_map) *)
(** We can also define [map] in terms of [fold]. Finish [fold_map]
below. *)
Definition fold_map {X Y:Type} (f : X -> Y) (l : list X) : list Y :=
fold (fun x ys => f x :: ys) l [].
(** Write down a theorem [fold_map_correct] in Coq stating that
[fold_map] is correct, and prove it. *)
Theorem fold_map_correct : forall (X Y: Type) (f: X -> Y) (l: list X),
map f l = fold_map f l.
Proof.
intros X Y f l. induction l. reflexivity.
simpl. rewrite -> IHl. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced (index_informal) *)
(** Recall the definition of the [index] function:
Fixpoint index {X : Type} (n : nat) (l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Write an informal proof of the following theorem:
forall X n l, length l = n -> @index X n l = None.
(* FILL IN HERE *)
*)
(** [] *)
(** **** Exercise: 4 stars, advanced (church_numerals) *)
Module Church.
(** In this exercise, we will explore an alternative way of defining
natural numbers, using the so-called _Church numerals_, named
after mathematician Alonzo Church. We can represent a natural
number [n] as a function that takes a function [f] as a parameter
and returns [f] iterated [n] times. More formally, *)
Definition nat := forall X : Type, (X -> X) -> X -> X.
(** Let's see how to write some numbers with this notation. Any
function [f] iterated once shouldn't change. Thus, *)
Definition one : nat :=
fun (X : Type) (f : X -> X) (x : X) => f x.
(** [two] should apply [f] twice to its argument: *)
Definition two : nat :=
fun (X : Type) (f : X -> X) (x : X) => f (f x).
(** [zero] is somewhat trickier: how can we apply a function zero
times? The answer is simple: just leave the argument untouched. *)
Definition zero : nat :=
fun (X : Type) (f : X -> X) (x : X) => x.
(** More generally, a number [n] will be written as [fun X f x => f (f
... (f x) ...)], with [n] occurrences of [f]. Notice in particular
how the [doit3times] function we've defined previously is actually
just the representation of [3]. *)
Definition three : nat := @doit3times.
(** Complete the definitions of the following functions. Make sure
that the corresponding unit tests pass by proving them with
[reflexivity]. *)
(** Successor of a natural number *)
Definition succ (n : nat) : nat :=
fun (X: Type) (f: X -> X) (x : X) => f (n X f x).
Example succ_1 : succ zero = one.
Proof. reflexivity. Admitted.
Example succ_2 : succ one = two.
Proof. reflexivity. Admitted.
Example succ_3 : succ two = three.
Proof. reflexivity. Admitted.
(** Addition of two natural numbers *)
Definition plus (n m : nat) : nat :=
fun (X: Type) (f: X -> X) (x: X) => m X f (n X f x).
Example plus_1 : plus zero one = one.
Proof. reflexivity. Admitted.
Example plus_2 : plus two three = plus three two.
Proof. reflexivity. Admitted.
Example plus_3 :
plus (plus two two) three = plus one (plus three three).
Proof. reflexivity. Admitted.
(** Multiplication *)
Definition mult (n m : nat) : nat :=
fun (X: Type) (f: X -> X) (x: X) => m X (n X f) x.
Example mult_1 : mult one one = one.
Proof. reflexivity. Admitted.
Example mult_2 : mult zero (plus three three) = zero.
Proof. reflexivity. Admitted.
Example mult_3 : mult two three = plus three three.
Proof. reflexivity. Admitted.
(** Exponentiation *)
(** Hint: Polymorphism plays a crucial role here. However, choosing
the right type to iterate over can be tricky. If you hit a
"Universe inconsistency" error, try iterating over a different
type: [nat] itself is usually problematic. *)
(* three nat doesn't work - because of universe inconsistenty;
a violation of the stratification of languages.
yet this is what we need. maybe one should implement nats at another level?.
*)
Definition const (X: Type) (Y: Type): X -> Y -> X :=
fun x _ => x.
Definition exp (n m : nat) : nat :=
(* generating of list of the right length *)
let unit_list := m (list unit) (app [tt]) [] in
(* replacing unit with curried multiplication *)
let fun_list := map (const (nat -> nat) unit (mult n)) unit_list in
(* folding of the list with 'one' as a seed *)
fold (fun (f: nat -> nat) (n: nat) => f n) fun_list one.
Example exp_1 : exp two two = plus two two.
Proof. reflexivity. Qed.
Example exp_2 : exp three two = plus (mult two (mult two two)) one.
Proof. reflexivity. Qed.
Example exp_3 : exp three zero = one.
Proof. reflexivity. Qed.
End Church.
(** [] *)
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
//=============================================================
//
// Copyright (c) 2017 Simon Southwell. All rights reserved.
//
// Date: 22nd May 2017
//
// This code is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// The code is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this code. If not, see <http://www.gnu.org/licenses/>.
//
// $Id: address_decode.v,v 1.4 2017/08/22 09:16:05 simon Exp $
// $Source: /home/simon/CVS/src/cpu/mico32/HDL/rtl/address_decode.v,v $
//
//=============================================================
// ------------------------------------------------
// Address decoder.
//
// Decode's CPU's data wishbone bus and generates
// strobe signals to peripheral devices (i.e. chip
// select). One for each of SRAM, UART and timer.
// It combines acks to send back to CPU's wb_ack,
// and muxes the read data to the return data bus.
//
// ------------------------------------------------
module address_decode (
sys_clk,
nreset,
wb_adr,
wb_ack_uart,
wb_ack_timer,
wb_ack_ctrl,
wb_stb,
wb_dat_uart_o,
wb_dat_timer_o,
wb_dat_ctrl_i,
sram_stb,
uart0_stb,
timer_stb,
local_stb,
wb_ack,
wb_dat_i
);
`include "regs.vh"
input sys_clk;
input nreset;
input [31:0] wb_adr;
input wb_ack_uart;
input wb_ack_timer;
input wb_ack_ctrl;
input wb_stb;
input [7:0] wb_dat_uart_o;
input [31:0] wb_dat_timer_o;
input [31:0] wb_dat_ctrl_i;
output sram_stb;
output uart0_stb;
output timer_stb;
output local_stb;
output wb_ack;
output [31:0] wb_dat_i;
wire [31:0] uart0_addr = `LM32_UART0_BASE_ADDR;
wire [31:0] timer_addr = `LM32_TIMER_BASE_ADDR;
// Decode address for peripheral targets
wire sram_sel = ~wb_adr[31];
// Decode addresses on top 8 bits, and on 4K pages (first 16)
// This assumption is specific to this project's address mapping,
// and may need to change if ported to a different project, with
// different mappings to get correct resolution.
wire uart0_sel = (wb_adr[31:24] == uart0_addr[31:24] && wb_adr[15:12] == uart0_addr[15:12]) ? 1'b1 : 1'b0;
wire timer_sel = (wb_adr[31:24] == timer_addr[31:24] && wb_adr[15:12] == timer_addr[15:12]) ? 1'b1 : 1'b0;
// Local register decode for any address not in the above selects.
// The controller will always acknowledge, so this mops up all unused
// addresses
wire local_sel = ~uart0_sel & ~timer_sel & ~sram_sel;
// Generate strobes (i.e. 'chip selects') for relevant peripheral
assign sram_stb = wb_stb & sram_sel;
assign uart0_stb = wb_stb & uart0_sel;
assign timer_stb = wb_stb & timer_sel;
assign local_stb = wb_stb & local_sel;
// Combine all acks (including dummy ACK) to send back to CPU.
assign wb_ack = wb_ack_ctrl | wb_ack_uart | wb_ack_timer;
// Multiplex read data from peripherals to return to CPU. If no peripheral
// selected, data is a dummy pattern to aid diagnostics. Controller
// handles both SRAM and local accesses.
assign wb_dat_i = (sram_sel | local_sel) ? wb_dat_ctrl_i :
uart0_sel ? {{24'h000000, wb_dat_uart_o}} :
timer_sel ? wb_dat_timer_o :
32'hcccccccc;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINVLP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__CLKINVLP_PP_SYMBOL_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkinvlp (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINVLP_PP_SYMBOL_V
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bg4_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module bg4_new (
address,
clock,
q);
input [14:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites-new/bg4-new.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32768,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 15,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/bg4-new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/bg4-new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bg4_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg4_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg4_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg4_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg4_new_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg4_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// file: Clock70HMz_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module Clock70HMz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Clock70HMz_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
// Freq Check
endmodule
|
module transform_memory(
clk,
rst,
i_valid,
i_transize,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
i_16,
i_17,
i_18,
i_19,
i_20,
i_21,
i_22,
i_23,
i_24,
i_25,
i_26,
i_27,
i_28,
i_29,
i_30,
i_31,
o_valid,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15,
o_16,
o_17,
o_18,
o_19,
o_20,
o_21,
o_22,
o_23,
o_24,
o_25,
o_26,
o_27,
o_28,
o_29,
o_30,
o_31
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk;
input rst;
input i_valid;
input signed [1:0] i_transize;
input signed [15:0] i_0;
input signed [15:0] i_1;
input signed [15:0] i_2;
input signed [15:0] i_3;
input signed [15:0] i_4;
input signed [15:0] i_5;
input signed [15:0] i_6;
input signed [15:0] i_7;
input signed [15:0] i_8;
input signed [15:0] i_9;
input signed [15:0] i_10;
input signed [15:0] i_11;
input signed [15:0] i_12;
input signed [15:0] i_13;
input signed [15:0] i_14;
input signed [15:0] i_15;
input signed [15:0] i_16;
input signed [15:0] i_17;
input signed [15:0] i_18;
input signed [15:0] i_19;
input signed [15:0] i_20;
input signed [15:0] i_21;
input signed [15:0] i_22;
input signed [15:0] i_23;
input signed [15:0] i_24;
input signed [15:0] i_25;
input signed [15:0] i_26;
input signed [15:0] i_27;
input signed [15:0] i_28;
input signed [15:0] i_29;
input signed [15:0] i_30;
input signed [15:0] i_31;
output reg o_valid;
output signed [15:0] o_0;
output signed [15:0] o_1;
output signed [15:0] o_2;
output signed [15:0] o_3;
output signed [15:0] o_4;
output signed [15:0] o_5;
output signed [15:0] o_6;
output signed [15:0] o_7;
output signed [15:0] o_8;
output signed [15:0] o_9;
output signed [15:0] o_10;
output signed [15:0] o_11;
output signed [15:0] o_12;
output signed [15:0] o_13;
output signed [15:0] o_14;
output signed [15:0] o_15;
output signed [15:0] o_16;
output signed [15:0] o_17;
output signed [15:0] o_18;
output signed [15:0] o_19;
output signed [15:0] o_20;
output signed [15:0] o_21;
output signed [15:0] o_22;
output signed [15:0] o_23;
output signed [15:0] o_24;
output signed [15:0] o_25;
output signed [15:0] o_26;
output signed [15:0] o_27;
output signed [15:0] o_28;
output signed [15:0] o_29;
output signed [15:0] o_30;
output signed [15:0] o_31;
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
wire wen;
wire enable;
wire [4:0] counter;
wire [4:0] badd_0 ;
wire [4:0] badd_1 ;
wire [4:0] badd_2 ;
wire [4:0] badd_3 ;
wire [4:0] badd_4 ;
wire [4:0] badd_5 ;
wire [4:0] badd_6 ;
wire [4:0] badd_7 ;
wire [4:0] badd_8 ;
wire [4:0] badd_9 ;
wire [4:0] badd_10;
wire [4:0] badd_11;
wire [4:0] badd_12;
wire [4:0] badd_13;
wire [4:0] badd_14;
wire [4:0] badd_15;
wire [4:0] badd_16;
wire [4:0] badd_17;
wire [4:0] badd_18;
wire [4:0] badd_19;
wire [4:0] badd_20;
wire [4:0] badd_21;
wire [4:0] badd_22;
wire [4:0] badd_23;
wire [4:0] badd_24;
wire [4:0] badd_25;
wire [4:0] badd_26;
wire [4:0] badd_27;
wire [4:0] badd_28;
wire [4:0] badd_29;
wire [4:0] badd_30;
wire [4:0] badd_31;
wire [4:0] add_0 ;
wire [4:0] add_1 ;
wire [4:0] add_2 ;
wire [4:0] add_3 ;
wire [4:0] add_4 ;
wire [4:0] add_5 ;
wire [4:0] add_6 ;
wire [4:0] add_7 ;
wire [4:0] add_8 ;
wire [4:0] add_9 ;
wire [4:0] add_10;
wire [4:0] add_11;
wire [4:0] add_12;
wire [4:0] add_13;
wire [4:0] add_14;
wire [4:0] add_15;
wire [4:0] add_16;
wire [4:0] add_17;
wire [4:0] add_18;
wire [4:0] add_19;
wire [4:0] add_20;
wire [4:0] add_21;
wire [4:0] add_22;
wire [4:0] add_23;
wire [4:0] add_24;
wire [4:0] add_25;
wire [4:0] add_26;
wire [4:0] add_27;
wire [4:0] add_28;
wire [4:0] add_29;
wire [4:0] add_30;
wire [4:0] add_31;
wire signed [15:0] i_m_0 ;
wire signed [15:0] i_m_1 ;
wire signed [15:0] i_m_2 ;
wire signed [15:0] i_m_3 ;
wire signed [15:0] i_m_4 ;
wire signed [15:0] i_m_5 ;
wire signed [15:0] i_m_6 ;
wire signed [15:0] i_m_7 ;
wire signed [15:0] i_m_8 ;
wire signed [15:0] i_m_9 ;
wire signed [15:0] i_m_10;
wire signed [15:0] i_m_11;
wire signed [15:0] i_m_12;
wire signed [15:0] i_m_13;
wire signed [15:0] i_m_14;
wire signed [15:0] i_m_15;
wire signed [15:0] i_m_16;
wire signed [15:0] i_m_17;
wire signed [15:0] i_m_18;
wire signed [15:0] i_m_19;
wire signed [15:0] i_m_20;
wire signed [15:0] i_m_21;
wire signed [15:0] i_m_22;
wire signed [15:0] i_m_23;
wire signed [15:0] i_m_24;
wire signed [15:0] i_m_25;
wire signed [15:0] i_m_26;
wire signed [15:0] i_m_27;
wire signed [15:0] i_m_28;
wire signed [15:0] i_m_29;
wire signed [15:0] i_m_30;
wire signed [15:0] i_m_31;
wire signed [15:0] o_m_0 ;
wire signed [15:0] o_m_1 ;
wire signed [15:0] o_m_2 ;
wire signed [15:0] o_m_3 ;
wire signed [15:0] o_m_4 ;
wire signed [15:0] o_m_5 ;
wire signed [15:0] o_m_6 ;
wire signed [15:0] o_m_7 ;
wire signed [15:0] o_m_8 ;
wire signed [15:0] o_m_9 ;
wire signed [15:0] o_m_10;
wire signed [15:0] o_m_11;
wire signed [15:0] o_m_12;
wire signed [15:0] o_m_13;
wire signed [15:0] o_m_14;
wire signed [15:0] o_m_15;
wire signed [15:0] o_m_16;
wire signed [15:0] o_m_17;
wire signed [15:0] o_m_18;
wire signed [15:0] o_m_19;
wire signed [15:0] o_m_20;
wire signed [15:0] o_m_21;
wire signed [15:0] o_m_22;
wire signed [15:0] o_m_23;
wire signed [15:0] o_m_24;
wire signed [15:0] o_m_25;
wire signed [15:0] o_m_26;
wire signed [15:0] o_m_27;
wire signed [15:0] o_m_28;
wire signed [15:0] o_m_29;
wire signed [15:0] o_m_30;
wire signed [15:0] o_m_31;
wire signed [15:0] i_s_0 ;
wire signed [15:0] i_s_1 ;
wire signed [15:0] i_s_2 ;
wire signed [15:0] i_s_3 ;
wire signed [15:0] i_s_4 ;
wire signed [15:0] i_s_5 ;
wire signed [15:0] i_s_6 ;
wire signed [15:0] i_s_7 ;
wire signed [15:0] i_s_8 ;
wire signed [15:0] i_s_9 ;
wire signed [15:0] i_s_10;
wire signed [15:0] i_s_11;
wire signed [15:0] i_s_12;
wire signed [15:0] i_s_13;
wire signed [15:0] i_s_14;
wire signed [15:0] i_s_15;
wire signed [15:0] i_s_16;
wire signed [15:0] i_s_17;
wire signed [15:0] i_s_18;
wire signed [15:0] i_s_19;
wire signed [15:0] i_s_20;
wire signed [15:0] i_s_21;
wire signed [15:0] i_s_22;
wire signed [15:0] i_s_23;
wire signed [15:0] i_s_24;
wire signed [15:0] i_s_25;
wire signed [15:0] i_s_26;
wire signed [15:0] i_s_27;
wire signed [15:0] i_s_28;
wire signed [15:0] i_s_29;
wire signed [15:0] i_s_30;
wire signed [15:0] i_s_31;
wire signed [15:0] o_s_0 ;
wire signed [15:0] o_s_1 ;
wire signed [15:0] o_s_2 ;
wire signed [15:0] o_s_3 ;
wire signed [15:0] o_s_4 ;
wire signed [15:0] o_s_5 ;
wire signed [15:0] o_s_6 ;
wire signed [15:0] o_s_7 ;
wire signed [15:0] o_s_8 ;
wire signed [15:0] o_s_9 ;
wire signed [15:0] o_s_10;
wire signed [15:0] o_s_11;
wire signed [15:0] o_s_12;
wire signed [15:0] o_s_13;
wire signed [15:0] o_s_14;
wire signed [15:0] o_s_15;
wire signed [15:0] o_s_16;
wire signed [15:0] o_s_17;
wire signed [15:0] o_s_18;
wire signed [15:0] o_s_19;
wire signed [15:0] o_s_20;
wire signed [15:0] o_s_21;
wire signed [15:0] o_s_22;
wire signed [15:0] o_s_23;
wire signed [15:0] o_s_24;
wire signed [15:0] o_s_25;
wire signed [15:0] o_s_26;
wire signed [15:0] o_s_27;
wire signed [15:0] o_s_28;
wire signed [15:0] o_s_29;
wire signed [15:0] o_s_30;
wire signed [15:0] o_s_31;
// ********************************************
//
// Reg DECLARATION
//
// ********************************************
reg o_chose;
reg wen_0;
reg wen_1;
reg enable_0;
reg signed [15:0] i_r_0;
reg signed [15:0] i_r_1;
reg signed [15:0] i_r_2;
reg signed [15:0] i_r_3;
reg signed [15:0] i_r_4;
reg signed [15:0] i_r_5;
reg signed [15:0] i_r_6;
reg signed [15:0] i_r_7;
reg signed [15:0] i_r_8;
reg signed [15:0] i_r_9;
reg signed [15:0] i_r_10;
reg signed [15:0] i_r_11;
reg signed [15:0] i_r_12;
reg signed [15:0] i_r_13;
reg signed [15:0] i_r_14;
reg signed [15:0] i_r_15;
reg signed [15:0] i_r_16;
reg signed [15:0] i_r_17;
reg signed [15:0] i_r_18;
reg signed [15:0] i_r_19;
reg signed [15:0] i_r_20;
reg signed [15:0] i_r_21;
reg signed [15:0] i_r_22;
reg signed [15:0] i_r_23;
reg signed [15:0] i_r_24;
reg signed [15:0] i_r_25;
reg signed [15:0] i_r_26;
reg signed [15:0] i_r_27;
reg signed [15:0] i_r_28;
reg signed [15:0] i_r_29;
reg signed [15:0] i_r_30;
reg signed [15:0] i_r_31;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign i_m_0 =wen_1?o_s_0 :i_0 ;
assign i_m_1 =wen_1?o_s_1 :i_1 ;
assign i_m_2 =wen_1?o_s_2 :i_2 ;
assign i_m_3 =wen_1?o_s_3 :i_3 ;
assign i_m_4 =wen_1?o_s_4 :i_4 ;
assign i_m_5 =wen_1?o_s_5 :i_5 ;
assign i_m_6 =wen_1?o_s_6 :i_6 ;
assign i_m_7 =wen_1?o_s_7 :i_7 ;
assign i_m_8 =wen_1?o_s_8 :i_8 ;
assign i_m_9 =wen_1?o_s_9 :i_9 ;
assign i_m_10=wen_1?o_s_10:i_10;
assign i_m_11=wen_1?o_s_11:i_11;
assign i_m_12=wen_1?o_s_12:i_12;
assign i_m_13=wen_1?o_s_13:i_13;
assign i_m_14=wen_1?o_s_14:i_14;
assign i_m_15=wen_1?o_s_15:i_15;
assign i_m_16=wen_1?o_s_16:i_16;
assign i_m_17=wen_1?o_s_17:i_17;
assign i_m_18=wen_1?o_s_18:i_18;
assign i_m_19=wen_1?o_s_19:i_19;
assign i_m_20=wen_1?o_s_20:i_20;
assign i_m_21=wen_1?o_s_21:i_21;
assign i_m_22=wen_1?o_s_22:i_22;
assign i_m_23=wen_1?o_s_23:i_23;
assign i_m_24=wen_1?o_s_24:i_24;
assign i_m_25=wen_1?o_s_25:i_25;
assign i_m_26=wen_1?o_s_26:i_26;
assign i_m_27=wen_1?o_s_27:i_27;
assign i_m_28=wen_1?o_s_28:i_28;
assign i_m_29=wen_1?o_s_29:i_29;
assign i_m_30=wen_1?o_s_30:i_30;
assign i_m_31=wen_1?o_s_31:i_31;
assign i_s_0 =wen_0?16'b0:o_m_0 ;
assign i_s_1 =wen_0?16'b0:o_m_1 ;
assign i_s_2 =wen_0?16'b0:o_m_2 ;
assign i_s_3 =wen_0?16'b0:o_m_3 ;
assign i_s_4 =wen_0?16'b0:o_m_4 ;
assign i_s_5 =wen_0?16'b0:o_m_5 ;
assign i_s_6 =wen_0?16'b0:o_m_6 ;
assign i_s_7 =wen_0?16'b0:o_m_7 ;
assign i_s_8 =wen_0?16'b0:o_m_8 ;
assign i_s_9 =wen_0?16'b0:o_m_9 ;
assign i_s_10=wen_0?16'b0:o_m_10;
assign i_s_11=wen_0?16'b0:o_m_11;
assign i_s_12=wen_0?16'b0:o_m_12;
assign i_s_13=wen_0?16'b0:o_m_13;
assign i_s_14=wen_0?16'b0:o_m_14;
assign i_s_15=wen_0?16'b0:o_m_15;
assign i_s_16=wen_0?16'b0:o_m_16;
assign i_s_17=wen_0?16'b0:o_m_17;
assign i_s_18=wen_0?16'b0:o_m_18;
assign i_s_19=wen_0?16'b0:o_m_19;
assign i_s_20=wen_0?16'b0:o_m_20;
assign i_s_21=wen_0?16'b0:o_m_21;
assign i_s_22=wen_0?16'b0:o_m_22;
assign i_s_23=wen_0?16'b0:o_m_23;
assign i_s_24=wen_0?16'b0:o_m_24;
assign i_s_25=wen_0?16'b0:o_m_25;
assign i_s_26=wen_0?16'b0:o_m_26;
assign i_s_27=wen_0?16'b0:o_m_27;
assign i_s_28=wen_0?16'b0:o_m_28;
assign i_s_29=wen_0?16'b0:o_m_29;
assign i_s_30=wen_0?16'b0:o_m_30;
assign i_s_31=wen_0?16'b0:o_m_31;
assign o_0 =o_chose?o_m_0: 16'b0;
assign o_1 =o_chose?o_m_1: 16'b0;
assign o_2 =o_chose?o_m_2: 16'b0;
assign o_3 =o_chose?o_m_3: 16'b0;
assign o_4 =o_chose?o_m_4: 16'b0;
assign o_5 =o_chose?o_m_5: 16'b0;
assign o_6 =o_chose?o_m_6: 16'b0;
assign o_7 =o_chose?o_m_7: 16'b0;
assign o_8 =o_chose?o_m_8: 16'b0;
assign o_9 =o_chose?o_m_9: 16'b0;
assign o_10 =o_chose?o_m_10:16'b0;
assign o_11 =o_chose?o_m_11:16'b0;
assign o_12 =o_chose?o_m_12:16'b0;
assign o_13 =o_chose?o_m_13:16'b0;
assign o_14 =o_chose?o_m_14:16'b0;
assign o_15 =o_chose?o_m_15:16'b0;
assign o_16 =o_chose?o_m_16:16'b0;
assign o_17 =o_chose?o_m_17:16'b0;
assign o_18 =o_chose?o_m_18:16'b0;
assign o_19 =o_chose?o_m_19:16'b0;
assign o_20 =o_chose?o_m_20:16'b0;
assign o_21 =o_chose?o_m_21:16'b0;
assign o_22 =o_chose?o_m_22:16'b0;
assign o_23 =o_chose?o_m_23:16'b0;
assign o_24 =o_chose?o_m_24:16'b0;
assign o_25 =o_chose?o_m_25:16'b0;
assign o_26 =o_chose?o_m_26:16'b0;
assign o_27 =o_chose?o_m_27:16'b0;
assign o_28 =o_chose?o_m_28:16'b0;
assign o_29 =o_chose?o_m_29:16'b0;
assign o_30 =o_chose?o_m_30:16'b0;
assign o_31 =o_chose?o_m_31:16'b0;
always@(*)
o_valid=o_chose;
// ********************************************
//
// Sequential Logic
//
// ********************************************
always@(posedge clk or negedge rst)
if(!rst)
o_chose<=1'b0;
else
if(i_transize==2'b00)
o_chose<=i_valid;
else
o_chose<=wen_1;
always@(posedge clk or negedge rst)
if(!rst)
enable_0<=1'b0;
else
enable_0<=enable;
always@(posedge clk or negedge rst)
if(!rst)
wen_0<=1'b0;
else
wen_0<=wen;
always@(posedge clk or negedge rst)
if(!rst)
wen_1<=1'b0;
else
wen_1<=wen_0;
always@(posedge clk or negedge rst)
if(!rst)
begin
i_r_0<=16'b0;
i_r_1<=16'b0;
i_r_2<=16'b0;
i_r_3<=16'b0;
i_r_4<=16'b0;
i_r_5<=16'b0;
i_r_6<=16'b0;
i_r_7<=16'b0;
i_r_8<=16'b0;
i_r_9<=16'b0;
i_r_10<=16'b0;
i_r_11<=16'b0;
i_r_12<=16'b0;
i_r_13<=16'b0;
i_r_14<=16'b0;
i_r_15<=16'b0;
i_r_16<=16'b0;
i_r_17<=16'b0;
i_r_18<=16'b0;
i_r_19<=16'b0;
i_r_20<=16'b0;
i_r_21<=16'b0;
i_r_22<=16'b0;
i_r_23<=16'b0;
i_r_24<=16'b0;
i_r_25<=16'b0;
i_r_26<=16'b0;
i_r_27<=16'b0;
i_r_28<=16'b0;
i_r_29<=16'b0;
i_r_30<=16'b0;
i_r_31<=16'b0;
end
else
begin
i_r_0 <= i_m_0 ;
i_r_1 <= i_m_1 ;
i_r_2 <= i_m_2 ;
i_r_3 <= i_m_3 ;
i_r_4 <= i_m_4 ;
i_r_5 <= i_m_5 ;
i_r_6 <= i_m_6 ;
i_r_7 <= i_m_7 ;
i_r_8 <= i_m_8 ;
i_r_9 <= i_m_9 ;
i_r_10<= i_m_10;
i_r_11<= i_m_11;
i_r_12<= i_m_12;
i_r_13<= i_m_13;
i_r_14<= i_m_14;
i_r_15<= i_m_15;
i_r_16<= i_m_16;
i_r_17<= i_m_17;
i_r_18<= i_m_18;
i_r_19<= i_m_19;
i_r_20<= i_m_20;
i_r_21<= i_m_21;
i_r_22<= i_m_22;
i_r_23<= i_m_23;
i_r_24<= i_m_24;
i_r_25<= i_m_25;
i_r_26<= i_m_26;
i_r_27<= i_m_27;
i_r_28<= i_m_28;
i_r_29<= i_m_29;
i_r_30<= i_m_30;
i_r_31<= i_m_31;
end
// ********************************************
//
// Sub Modules
//
// ********************************************
ctrl_transmemory ctrl_transmemory_0(
clk,
rst,
i_valid,
i_transize,
wen,
enable,
counter
);
addr add0_0(
clk,
rst,
enable,
wen,
counter,
i_transize,
badd_0 ,
badd_1 ,
badd_2 ,
badd_3 ,
badd_4 ,
badd_5 ,
badd_6 ,
badd_7 ,
badd_8 ,
badd_9 ,
badd_10,
badd_11,
badd_12,
badd_13,
badd_14,
badd_15,
badd_16,
badd_17,
badd_18,
badd_19,
badd_20,
badd_21,
badd_22,
badd_23,
badd_24,
badd_25,
badd_26,
badd_27,
badd_28,
badd_29,
badd_30,
badd_31,
add_0 ,
add_1 ,
add_2 ,
add_3 ,
add_4 ,
add_5 ,
add_6 ,
add_7 ,
add_8 ,
add_9 ,
add_10,
add_11,
add_12,
add_13,
add_14,
add_15,
add_16,
add_17,
add_18,
add_19,
add_20,
add_21,
add_22,
add_23,
add_24,
add_25,
add_26,
add_27,
add_28,
add_29,
add_30,
add_31
);
mux_32 mux_32_0(
badd_0,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_0
);
mux_32 mux_32_1(
badd_1,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_1
);
mux_32 mux_32_2(
badd_2,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_2
);
mux_32 mux_32_3(
badd_3,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_3
);
mux_32 mux_32_4(
badd_4,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_4
);
mux_32 mux_32_5(
badd_5,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_5
);
mux_32 mux_32_6(
badd_6,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_6
);
mux_32 mux_32_7(
badd_7,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_7
);
mux_32 mux_32_8(
badd_8,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_8
);
mux_32 mux_32_9(
badd_9,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_9
);
mux_32 mux_32_10(
badd_10,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_10
);
mux_32 mux_32_11(
badd_11,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_11
);
mux_32 mux_32_12(
badd_12,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_12
);
mux_32 mux_32_13(
badd_13,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_13
);
mux_32 mux_32_14(
badd_14,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_14
);
mux_32 mux_32_15(
badd_15,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_15
);
mux_32 mux_32_16(
badd_16,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_16
);
mux_32 mux_32_17(
badd_17,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_17
);
mux_32 mux_32_18(
badd_18,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_18
);
mux_32 mux_32_19(
badd_19,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_19
);
mux_32 mux_32_20(
badd_20,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_20
);
mux_32 mux_32_21(
badd_21,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_21
);
mux_32 mux_32_22(
badd_22,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_22
);
mux_32 mux_32_23(
badd_23,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_23
);
mux_32 mux_32_24(
badd_24,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_24
);
mux_32 mux_32_25(
badd_25,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_25
);
mux_32 mux_32_26(
badd_26,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_26
);
mux_32 mux_32_27(
badd_27,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_27
);
mux_32 mux_32_28(
badd_28,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_28
);
mux_32 mux_32_29(
badd_29,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_29
);
mux_32 mux_32_30(
badd_30,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_30
);
mux_32 mux_32_31(
badd_31,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_31
);
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_0(.data_o(o_s_0),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_0),.data_i(i_s_0),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_1(.data_o(o_s_1),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_1),.data_i(i_s_1),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_2(.data_o(o_s_2),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_2),.data_i(i_s_2),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_3(.data_o(o_s_3),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_3),.data_i(i_s_3),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_4(.data_o(o_s_4),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_4),.data_i(i_s_4),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_5(.data_o(o_s_5),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_5),.data_i(i_s_5),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_6(.data_o(o_s_6),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_6),.data_i(i_s_6),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_7(.data_o(o_s_7),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_7),.data_i(i_s_7),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_8(.data_o(o_s_8),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_8),.data_i(i_s_8),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_9(.data_o(o_s_9),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_9),.data_i(i_s_9),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_10(.data_o(o_s_10),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_10),.data_i(i_s_10),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_11(.data_o(o_s_11),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_11),.data_i(i_s_11),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_12(.data_o(o_s_12),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_12),.data_i(i_s_12),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_13(.data_o(o_s_13),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_13),.data_i(i_s_13),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_14(.data_o(o_s_14),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_14),.data_i(i_s_14),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_15(.data_o(o_s_15),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_15),.data_i(i_s_15),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_16(.data_o(o_s_16),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_16),.data_i(i_s_16),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_17(.data_o(o_s_17),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_17),.data_i(i_s_17),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_18(.data_o(o_s_18),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_18),.data_i(i_s_18),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_19(.data_o(o_s_19),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_19),.data_i(i_s_19),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_20(.data_o(o_s_20),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_20),.data_i(i_s_20),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_21(.data_o(o_s_21),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_21),.data_i(i_s_21),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_22(.data_o(o_s_22),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_22),.data_i(i_s_22),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_23(.data_o(o_s_23),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_23),.data_i(i_s_23),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_24(.data_o(o_s_24),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_24),.data_i(i_s_24),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_25(.data_o(o_s_25),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_25),.data_i(i_s_25),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_26(.data_o(o_s_26),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_26),.data_i(i_s_26),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_27(.data_o(o_s_27),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_27),.data_i(i_s_27),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_28(.data_o(o_s_28),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_28),.data_i(i_s_28),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_29(.data_o(o_s_29),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_29),.data_i(i_s_29),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_30(.data_o(o_s_30),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_30),.data_i(i_s_30),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_31(.data_o(o_s_31),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_31),.data_i(i_s_31),.oen_i(!wen_1));
endmodule |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ecb_e
//
// Generated
// by: wig
// on: Mon Mar 22 13:27:29 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ecb_e.v,v 1.1 2004/04/06 10:50:28 wig Exp $
// $Date: 2004/04/06 10:50:28 $
// $Log: inst_ecb_e.v,v $
// Revision 1.1 2004/04/06 10:50:28 wig
// Adding result/mde_tests
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ecb_e
//
// No `defines in this module
module inst_ecb_e
//
// Generated module inst_ecb
//
(
nreset,
nreset_s
);
// Generated Module Inputs:
input nreset;
input nreset_s;
// Generated Wires:
wire nreset;
wire nreset_s;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_ecb_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
`include "raycast_defines.v"
module raycaster(
wb_clk,
wb_rst,
// WB Slave
wb_adr_i, wb_dat_i,
wb_we_i, wb_cyc_i, wb_stb_i,
wb_cti_i, wb_bte_i,
wb_dat_o, wb_ack_o, wb_err_o, wb_rty_o,
// WB Master
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
m_wb_cti_o, m_wb_bte_o,
// Interrupt
irq_o
);
// = Parameters =
// --
// = Ports =
input wb_clk;
input wb_rst;
// Wishbone Slave
input [7:0] wb_adr_i;
input [7:0] wb_dat_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
input [2:0] wb_cti_i;
input [1:0] wb_bte_i;
output [7:0] wb_dat_o; // constantly sampling gpio in bus
output wb_ack_o;
output wb_err_o;
output wb_rty_o;
// Wishbone master
output [31:0] m_wb_adr_o;
output [3:0] m_wb_sel_o;
output m_wb_we_o;
input [31:0] m_wb_dat_i;
output [31:0] m_wb_dat_o;
output m_wb_cyc_o;
output m_wb_stb_o;
input m_wb_ack_i;
input m_wb_err_i;
output [2:0] m_wb_cti_o; // Cycle Type Identifier
output [1:0] m_wb_bte_o; // Burst Type Extension
//
output irq_o;
// --
// = Wires =
wire [31:0] cache_hits;
wire [31:0] cache_miss;
wire [511:0] pm;
wire [511:0] mm;
wire [127:0] test;
// Slave -> Controller
wire rayc_start ;
wire rayc_lol ;
wire [31:0] ray_buf_adr ;
wire [31:0] ray_buf_count ;
wire [31:0] octree_adr ;
wire [31:0] fb_adr ;
wire rayc_finished;
// Controller <-> Master
wire [31:0] ctrl_wb_adr_o;
wire [3:0] ctrl_wb_sel_o;
wire ctrl_wb_we_o ;
wire [31:0] ctrl_wb_dat_i;
wire [31:0] ctrl_wb_dat_o;
wire ctrl_wb_cyc_o;
wire ctrl_wb_stb_o;
wire ctrl_wb_ack_i;
wire [2:0] ctrl_wb_cti_o;
wire [1:0] ctrl_wb_bte_o;
// Cores
`ifdef CORE0
wire c0_start ;
wire [31:0] c0_root_adr ;
wire [2:0] c0_dir_mask ;
wire [31:0] c0_tx0 ;
wire [31:0] c0_ty0 ;
wire [31:0] c0_tz0 ;
wire [31:0] c0_tx1 ;
wire [31:0] c0_ty1 ;
wire [31:0] c0_tz1 ;
wire [31:0] c0_wb_adr_o;
wire [31:0] c0_wb_dat_i;
wire c0_wb_cyc_o;
wire c0_wb_stb_o;
wire c0_wb_ack_i;
wire c0_finished ;
wire c0_leaf ;
wire [31:0] c0_final_t ;
wire [4:0] c0_final_level ;
`endif
`ifdef CORE1
wire c1_start ;
wire [31:0] c1_root_adr ;
wire [2:0] c1_dir_mask ;
wire [31:0] c1_tx0 ;
wire [31:0] c1_ty0 ;
wire [31:0] c1_tz0 ;
wire [31:0] c1_tx1 ;
wire [31:0] c1_ty1 ;
wire [31:0] c1_tz1 ;
wire [31:0] c1_wb_adr_o;
wire [31:0] c1_wb_dat_i;
wire c1_wb_cyc_o;
wire c1_wb_stb_o;
wire c1_wb_ack_i;
wire c1_finished ;
wire c1_leaf ;
wire [31:0] c1_final_t ;
wire [4:0] c1_final_level ;
`endif
`ifdef CORE2
wire c2_start ;
wire [31:0] c2_root_adr ;
wire [2:0] c2_dir_mask ;
wire [31:0] c2_tx0 ;
wire [31:0] c2_ty0 ;
wire [31:0] c2_tz0 ;
wire [31:0] c2_tx1 ;
wire [31:0] c2_ty1 ;
wire [31:0] c2_tz1 ;
wire [31:0] c2_wb_adr_o;
wire [31:0] c2_wb_dat_i;
wire c2_wb_cyc_o;
wire c2_wb_stb_o;
wire c2_wb_ack_i;
wire c2_finished ;
wire c2_leaf ;
wire [31:0] c2_final_t ;
wire [4:0] c2_final_level ;
`endif
`ifdef CORE3
wire c3_start ;
wire [31:0] c3_root_adr ;
wire [2:0] c3_dir_mask ;
wire [31:0] c3_tx0 ;
wire [31:0] c3_ty0 ;
wire [31:0] c3_tz0 ;
wire [31:0] c3_tx1 ;
wire [31:0] c3_ty1 ;
wire [31:0] c3_tz1 ;
wire [31:0] c3_wb_adr_o;
wire [31:0] c3_wb_dat_i;
wire c3_wb_cyc_o;
wire c3_wb_stb_o;
wire c3_wb_ack_i;
wire c3_finished ;
wire c3_leaf ;
wire [31:0] c3_final_t ;
wire [4:0] c3_final_level ;
`endif
// --
// = Raycast Control =
raycast_ctrl raycast_ctrl
(
.clk (wb_clk),
.rst (wb_rst),
.rayc_start_i (rayc_start ),
.rayc_lol_i (rayc_lol ),
.ray_buf_adr_i (ray_buf_adr ),
.ray_buf_count_i (ray_buf_count),
.octree_adr_i (octree_adr ),
.fb_adr_i (fb_adr ),
.pm_i (pm),
.mm_i (mm),
.test_o (test),
.m_wb_adr_o (ctrl_wb_adr_o),
.m_wb_sel_o (ctrl_wb_sel_o),
.m_wb_we_o (ctrl_wb_we_o ),
.m_wb_dat_o (ctrl_wb_dat_o),
.m_wb_dat_i (ctrl_wb_dat_i),
.m_wb_cyc_o (ctrl_wb_cyc_o),
.m_wb_stb_o (ctrl_wb_stb_o),
.m_wb_ack_i (ctrl_wb_ack_i),
.m_wb_cti_o (ctrl_wb_cti_o),
.m_wb_bte_o (ctrl_wb_bte_o),
/* .ctrl_adr_o (ctrl_adr),
.ray_data_req_o (ray_data_req ),
.ray_data_ack_i (ray_data_ack ),
.ray_data_i (ray_data ),
.fb_w_req_o (fb_w_req ),
.fb_w_dat_o (fb_w_dat ),
.fb_w_ack_i (fb_w_ack ),*/
`ifdef CORE0
.c0_start_o (c0_start ),
.c0_root_adr_o (c0_root_adr),
.c0_dir_mask_o (c0_dir_mask),
.c0_tx0_o (c0_tx0 ),
.c0_ty0_o (c0_ty0 ),
.c0_tz0_o (c0_tz0 ),
.c0_tx1_o (c0_tx1 ),
.c0_ty1_o (c0_ty1 ),
.c0_tz1_o (c0_tz1 ),
.c0_finished_i (c0_finished),
.c0_leaf_i (c0_leaf),
.c0_final_t_i (c0_final_t),
.c0_final_level_i (c0_final_level),
`endif
`ifdef CORE1
.c1_start_o (c1_start ),
.c1_root_adr_o (c1_root_adr),
.c1_dir_mask_o (c1_dir_mask),
.c1_tx0_o (c1_tx0 ),
.c1_ty0_o (c1_ty0 ),
.c1_tz0_o (c1_tz0 ),
.c1_tx1_o (c1_tx1 ),
.c1_ty1_o (c1_ty1 ),
.c1_tz1_o (c1_tz1 ),
.c1_finished_i (c1_finished),
.c1_leaf_i (c1_leaf),
.c1_final_t_i (c1_final_t),
.c1_final_level_i (c1_final_level),
`endif
`ifdef CORE2
.c2_start_o (c2_start ),
.c2_root_adr_o (c2_root_adr),
.c2_dir_mask_o (c2_dir_mask),
.c2_tx0_o (c2_tx0 ),
.c2_ty0_o (c2_ty0 ),
.c2_tz0_o (c2_tz0 ),
.c2_tx1_o (c2_tx1 ),
.c2_ty1_o (c2_ty1 ),
.c2_tz1_o (c2_tz1 ),
.c2_finished_i (c2_finished),
.c2_leaf_i (c2_leaf),
.c2_final_t_i (c2_final_t),
.c2_final_level_i (c2_final_level),
`endif
`ifdef CORE3
.c3_start_o (c3_start ),
.c3_root_adr_o (c3_root_adr),
.c3_dir_mask_o (c3_dir_mask),
.c3_tx0_o (c3_tx0 ),
.c3_ty0_o (c3_ty0 ),
.c3_tz0_o (c3_tz0 ),
.c3_tx1_o (c3_tx1 ),
.c3_ty1_o (c3_ty1 ),
.c3_tz1_o (c3_tz1 ),
.c3_finished_i (c3_finished),
.c3_leaf_i (c3_leaf),
.c3_final_t_i (c3_final_t),
.c3_final_level_i (c3_final_level),
`endif
.rayc_finished_o (rayc_finished)
);
// --
// = Raycast master interface =
raycast_master raycast_master
(
// .cache_hits (cache_hits),
// .cache_miss (cache_miss),
.m_wb_adr_o (m_wb_adr_o ),
.m_wb_sel_o (m_wb_sel_o ),
.m_wb_we_o (m_wb_we_o ),
.m_wb_dat_o (m_wb_dat_o ),
.m_wb_dat_i (m_wb_dat_i ),
.m_wb_cyc_o (m_wb_cyc_o ),
.m_wb_stb_o (m_wb_stb_o ),
.m_wb_ack_i (m_wb_ack_i ),
.m_wb_err_i (m_wb_err_i ),
.m_wb_cti_o (m_wb_cti_o ),
.m_wb_bte_o (m_wb_bte_o ),
.ctrl_wb_adr_i (ctrl_wb_adr_o),
.ctrl_wb_sel_i (ctrl_wb_sel_o),
.ctrl_wb_we_i (ctrl_wb_we_o ),
.ctrl_wb_dat_o (ctrl_wb_dat_i),
.ctrl_wb_dat_i (ctrl_wb_dat_o),
.ctrl_wb_cyc_i (ctrl_wb_cyc_o),
.ctrl_wb_stb_i (ctrl_wb_stb_o),
.ctrl_wb_ack_o (ctrl_wb_ack_i),
.ctrl_wb_cti_i (ctrl_wb_cti_o),
.ctrl_wb_bte_i (ctrl_wb_bte_o),
`ifdef CORE0
.c0_wb_adr_i (c0_wb_adr_o),
.c0_wb_dat_o (c0_wb_dat_i),
.c0_wb_cyc_i (c0_wb_cyc_o),
.c0_wb_stb_i (c0_wb_stb_o),
.c0_wb_ack_o (c0_wb_ack_i),
`endif
`ifdef CORE1
.c1_wb_adr_i (c1_wb_adr_o),
.c1_wb_dat_o (c1_wb_dat_i),
.c1_wb_cyc_i (c1_wb_cyc_o),
.c1_wb_stb_i (c1_wb_stb_o),
.c1_wb_ack_o (c1_wb_ack_i),
`endif
`ifdef CORE2
.c2_wb_adr_i (c2_wb_adr_o),
.c2_wb_dat_o (c2_wb_dat_i),
.c2_wb_cyc_i (c2_wb_cyc_o),
.c2_wb_stb_i (c2_wb_stb_o),
.c2_wb_ack_o (c2_wb_ack_i),
`endif
`ifdef CORE3
.c3_wb_adr_i (c3_wb_adr_o),
.c3_wb_dat_o (c3_wb_dat_i),
.c3_wb_cyc_i (c3_wb_cyc_o),
.c3_wb_stb_i (c3_wb_stb_o),
.c3_wb_ack_o (c3_wb_ack_i),
`endif
.wb_clk (wb_clk ),
.wb_rst (wb_rst )
);
// --
// = Raycast slave interface =
raycast_slave raycast_slave
(
.wb_clk (wb_clk ),
.wb_rst (wb_rst ),
.wb_adr_i (wb_adr_i),
.wb_dat_i (wb_dat_i),
.wb_we_i (wb_we_i ),
.wb_cyc_i (wb_cyc_i),
.wb_stb_i (wb_stb_i),
.wb_cti_i (wb_cti_i),
.wb_bte_i (wb_bte_i),
.wb_dat_o (wb_dat_o),
.wb_ack_o (wb_ack_o),
.wb_err_o (wb_err_o),
.wb_rty_o (wb_rty_o),
.rayc_start_o (rayc_start ),
.rayc_lol_o (rayc_lol ),
.ray_buf_adr_o (ray_buf_adr ),
.ray_buf_count_o (ray_buf_count),
.octree_adr_o (octree_adr ),
.fb_adr_o (fb_adr ),
.rayc_finished_i (rayc_finished),
.cache_hits_i (cache_hits),
.cache_miss_i (cache_miss),
.irq_o (irq_o),
.pm_o (pm),
.mm_o (mm),
.test_i (test)
);
// --
// = Raycast cores =
`ifdef CORE0
raycast_core core0
(
.clk (wb_clk ),
.rst (wb_rst ),
.start_i (c0_start ),
.root_adr_i (c0_root_adr ),
.dir_mask_i (c0_dir_mask ),
.tx0_i (c0_tx0 ),
.ty0_i (c0_ty0 ),
.tz0_i (c0_tz0 ),
.tx1_i (c0_tx1 ),
.ty1_i (c0_ty1 ),
.tz1_i (c0_tz1 ),
.m_wb_adr_o (c0_wb_adr_o),
.m_wb_dat_i (c0_wb_dat_i),
.m_wb_cyc_o (c0_wb_cyc_o),
.m_wb_stb_o (c0_wb_stb_o),
.m_wb_ack_i (c0_wb_ack_i),
.finished_o (c0_finished ),
.leaf_o (c0_leaf),
.t_o (c0_final_t ),
.level_o (c0_final_level )
);
`endif
`ifdef CORE1
raycast_core core1
(
.clk (wb_clk ),
.rst (wb_rst ),
.start_i (c1_start ),
.root_adr_i (c1_root_adr ),
.dir_mask_i (c1_dir_mask ),
.tx0_i (c1_tx0 ),
.ty0_i (c1_ty0 ),
.tz0_i (c1_tz0 ),
.tx1_i (c1_tx1 ),
.ty1_i (c1_ty1 ),
.tz1_i (c1_tz1 ),
.m_wb_adr_o (c1_wb_adr_o),
.m_wb_dat_i (c1_wb_dat_i),
.m_wb_cyc_o (c1_wb_cyc_o),
.m_wb_stb_o (c1_wb_stb_o),
.m_wb_ack_i (c1_wb_ack_i),
.finished_o (c1_finished ),
.leaf_o (c1_leaf),
.t_o (c1_final_t ),
.level_o (c1_final_level )
);
`endif
`ifdef CORE2
raycast_core core2
(
.clk (wb_clk ),
.rst (wb_rst ),
.start_i (c2_start ),
.root_adr_i (c2_root_adr ),
.dir_mask_i (c2_dir_mask ),
.tx0_i (c2_tx0 ),
.ty0_i (c2_ty0 ),
.tz0_i (c2_tz0 ),
.tx1_i (c2_tx1 ),
.ty1_i (c2_ty1 ),
.tz1_i (c2_tz1 ),
.m_wb_adr_o (c2_wb_adr_o),
.m_wb_dat_i (c2_wb_dat_i),
.m_wb_cyc_o (c2_wb_cyc_o),
.m_wb_stb_o (c2_wb_stb_o),
.m_wb_ack_i (c2_wb_ack_i),
.finished_o (c2_finished ),
.leaf_o (c2_leaf),
.t_o (c2_final_t ),
.level_o (c2_final_level )
);
`endif
`ifdef CORE3
raycast_core core3
(
.clk (wb_clk ),
.rst (wb_rst ),
.start_i (c3_start ),
.root_adr_i (c3_root_adr ),
.dir_mask_i (c3_dir_mask ),
.tx0_i (c3_tx0 ),
.ty0_i (c3_ty0 ),
.tz0_i (c3_tz0 ),
.tx1_i (c3_tx1 ),
.ty1_i (c3_ty1 ),
.tz1_i (c3_tz1 ),
.m_wb_adr_o (c3_wb_adr_o),
.m_wb_dat_i (c3_wb_dat_i),
.m_wb_cyc_o (c3_wb_cyc_o),
.m_wb_stb_o (c3_wb_stb_o),
.m_wb_ack_i (c3_wb_ack_i),
.finished_o (c3_finished ),
.leaf_o (c3_leaf),
.t_o (c3_final_t ),
.level_o (c3_final_level )
);
`endif
// --
endmodule // raycaster |
// TimeHoldOver_Qsys.v
// Generated using ACDS version 16.0 222
`timescale 1 ps / 1 ps
module TimeHoldOver_Qsys (
input wire clk_clk, // clk.clk
output wire epcs_flash_controller_dclk, // epcs_flash_controller.dclk
output wire epcs_flash_controller_sce, // .sce
output wire epcs_flash_controller_sdo, // .sdo
input wire epcs_flash_controller_data0, // .data0
output wire io_update_ctrl_export, // io_update_ctrl.export
input wire ocxo_lock_export, // ocxo_lock.export
output wire [8:0] on_chip_rst_and_pps_switch_export, // on_chip_rst_and_pps_switch.export
input wire pps_interrupt_export, // pps_interrupt.export
input wire reset_reset_n, // reset.reset_n
output wire [11:0] sdram_controller_addr, // sdram_controller.addr
output wire [1:0] sdram_controller_ba, // .ba
output wire sdram_controller_cas_n, // .cas_n
output wire sdram_controller_cke, // .cke
output wire sdram_controller_cs_n, // .cs_n
inout wire [15:0] sdram_controller_dq, // .dq
output wire [1:0] sdram_controller_dqm, // .dqm
output wire sdram_controller_ras_n, // .ras_n
output wire sdram_controller_we_n, // .we_n
input wire timer_ecc_fault_itr_export, // timer_ecc_fault_itr.export
output wire [192:0] timer_interface_coe_sec_cnt_set_data_out, // timer_interface.coe_sec_cnt_set_data_out
input wire [191:0] timer_interface_coe_sec_cnt_get_data_in, // .coe_sec_cnt_get_data_in
output wire [96:0] timer_interface_coe_ns_cnt_set_data_out, // .coe_ns_cnt_set_data_out
input wire [95:0] timer_interface_coe_ns_cnt_get_data_in, // .coe_ns_cnt_get_data_in
output wire [24:0] timer_interface_coe_ctrl_cnt_set_out, // .coe_ctrl_cnt_set_out
input wire [23:0] timer_interface_coe_ctrl_cnt_get_in, // .coe_ctrl_cnt_get_in
input wire [23:0] timer_interface_coe_err_cnt_in, // .coe_err_cnt_in
input wire [55:0] timer_interface_coe_utc_time_in, // .coe_utc_time_in
output wire [8:0] timer_interface_coe_time_zone_set_out, // .coe_time_zone_set_out
input wire [7:0] timer_interface_coe_time_zone_get_in, // .coe_time_zone_get_in
output wire [16:0] timer_interface_coe_leap_cnt_set_out, // .coe_leap_cnt_set_out
input wire [15:0] timer_interface_coe_leap_cnt_get_in, // .coe_leap_cnt_get_in
output wire [64:0] timer_interface_coe_leap_occur_set_out, // .coe_leap_occur_set_out
input wire [63:0] timer_interface_coe_leap_occur_get_in, // .coe_leap_occur_get_in
output wire [64:0] timer_interface_coe_dst_ingress_set_out, // .coe_dst_ingress_set_out
input wire [63:0] timer_interface_coe_dst_ingress_get_in, // .coe_dst_ingress_get_in
output wire [64:0] timer_interface_coe_dst_engress_set_out, // .coe_dst_engress_set_out
input wire [63:0] timer_interface_coe_dst_engress_get_in, // .coe_dst_engress_get_in
input wire [7:0] timer_interface_coe_leap_direct_get_in, // .coe_leap_direct_get_in
output wire [8:0] timer_interface_coe_leap_direct_set_out, // .coe_leap_direct_set_out
input wire timer_interface_coe_io_update_in, // .coe_io_update_in
input wire [7:0] timer_interface_coe_time_quality_get_in, // .coe_time_quality_get_in
output wire [8:0] timer_interface_coe_time_quality_set_out, // .coe_time_quality_set_out
input wire uart_0_external_connection_rxd, // uart_0_external_connection.rxd
output wire uart_0_external_connection_txd, // .txd
input wire uart_1_external_connection_rxd, // uart_1_external_connection.rxd
output wire uart_1_external_connection_txd, // .txd
input wire uart_2_external_connection_rxd, // uart_2_external_connection.rxd
output wire uart_2_external_connection_txd, // .txd
input wire uart_3_external_connection_rxd, // uart_3_external_connection.rxd
output wire uart_3_external_connection_txd // .txd
);
wire [31:0] nios2_gen2_0_data_master_readdata; // mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
wire nios2_gen2_0_data_master_waitrequest; // mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
wire nios2_gen2_0_data_master_debugaccess; // nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
wire [24:0] nios2_gen2_0_data_master_address; // nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
wire [3:0] nios2_gen2_0_data_master_byteenable; // nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
wire nios2_gen2_0_data_master_read; // nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
wire nios2_gen2_0_data_master_readdatavalid; // mm_interconnect_0:nios2_gen2_0_data_master_readdatavalid -> nios2_gen2_0:d_readdatavalid
wire nios2_gen2_0_data_master_write; // nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
wire [31:0] nios2_gen2_0_data_master_writedata; // nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
wire [31:0] nios2_gen2_0_instruction_master_readdata; // mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
wire nios2_gen2_0_instruction_master_waitrequest; // mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
wire [24:0] nios2_gen2_0_instruction_master_address; // nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
wire nios2_gen2_0_instruction_master_read; // nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
wire nios2_gen2_0_instruction_master_readdatavalid; // mm_interconnect_0:nios2_gen2_0_instruction_master_readdatavalid -> nios2_gen2_0:i_readdatavalid
wire [31:0] mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_readdata; // avalon_mapped_timer_reg_buf_0:avs_readdata -> mm_interconnect_0:avalon_mapped_timer_reg_buf_0_avalon_slave_0_readdata
wire [4:0] mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_address; // mm_interconnect_0:avalon_mapped_timer_reg_buf_0_avalon_slave_0_address -> avalon_mapped_timer_reg_buf_0:avs_address
wire mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_read; // mm_interconnect_0:avalon_mapped_timer_reg_buf_0_avalon_slave_0_read -> avalon_mapped_timer_reg_buf_0:avs_read_n
wire mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_write; // mm_interconnect_0:avalon_mapped_timer_reg_buf_0_avalon_slave_0_write -> avalon_mapped_timer_reg_buf_0:avs_write_n
wire [31:0] mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_writedata; // mm_interconnect_0:avalon_mapped_timer_reg_buf_0_avalon_slave_0_writedata -> avalon_mapped_timer_reg_buf_0:avs_writedata
wire [31:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata; // nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest; // nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
wire [8:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
wire [3:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
wire [31:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
wire mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_chipselect; // mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_chipselect -> epcs_flash_controller_0:chipselect
wire [31:0] mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_readdata; // epcs_flash_controller_0:readdata -> mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_readdata
wire [8:0] mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_address; // mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_address -> epcs_flash_controller_0:address
wire mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read; // mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_read -> epcs_flash_controller_0:read_n
wire mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write; // mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_write -> epcs_flash_controller_0:write_n
wire [31:0] mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_writedata; // mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_writedata -> epcs_flash_controller_0:writedata
wire mm_interconnect_0_onchip_rst_and_pps_switch_s1_chipselect; // mm_interconnect_0:onchip_rst_and_pps_switch_s1_chipselect -> onchip_rst_and_pps_switch:chipselect
wire [31:0] mm_interconnect_0_onchip_rst_and_pps_switch_s1_readdata; // onchip_rst_and_pps_switch:readdata -> mm_interconnect_0:onchip_rst_and_pps_switch_s1_readdata
wire [1:0] mm_interconnect_0_onchip_rst_and_pps_switch_s1_address; // mm_interconnect_0:onchip_rst_and_pps_switch_s1_address -> onchip_rst_and_pps_switch:address
wire mm_interconnect_0_onchip_rst_and_pps_switch_s1_write; // mm_interconnect_0:onchip_rst_and_pps_switch_s1_write -> onchip_rst_and_pps_switch:write_n
wire [31:0] mm_interconnect_0_onchip_rst_and_pps_switch_s1_writedata; // mm_interconnect_0:onchip_rst_and_pps_switch_s1_writedata -> onchip_rst_and_pps_switch:writedata
wire mm_interconnect_0_io_update_s1_chipselect; // mm_interconnect_0:io_update_s1_chipselect -> io_update:chipselect
wire [31:0] mm_interconnect_0_io_update_s1_readdata; // io_update:readdata -> mm_interconnect_0:io_update_s1_readdata
wire [1:0] mm_interconnect_0_io_update_s1_address; // mm_interconnect_0:io_update_s1_address -> io_update:address
wire mm_interconnect_0_io_update_s1_write; // mm_interconnect_0:io_update_s1_write -> io_update:write_n
wire [31:0] mm_interconnect_0_io_update_s1_writedata; // mm_interconnect_0:io_update_s1_writedata -> io_update:writedata
wire mm_interconnect_0_ocxo_lock_s1_chipselect; // mm_interconnect_0:ocxo_lock_s1_chipselect -> ocxo_lock:chipselect
wire [31:0] mm_interconnect_0_ocxo_lock_s1_readdata; // ocxo_lock:readdata -> mm_interconnect_0:ocxo_lock_s1_readdata
wire [1:0] mm_interconnect_0_ocxo_lock_s1_address; // mm_interconnect_0:ocxo_lock_s1_address -> ocxo_lock:address
wire mm_interconnect_0_ocxo_lock_s1_write; // mm_interconnect_0:ocxo_lock_s1_write -> ocxo_lock:write_n
wire [31:0] mm_interconnect_0_ocxo_lock_s1_writedata; // mm_interconnect_0:ocxo_lock_s1_writedata -> ocxo_lock:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_chipselect; // mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_readdata; // onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
wire [11:0] mm_interconnect_0_onchip_memory2_0_s1_address; // mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
wire [3:0] mm_interconnect_0_onchip_memory2_0_s1_byteenable; // mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
wire mm_interconnect_0_onchip_memory2_0_s1_write; // mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_writedata; // mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_clken; // mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
wire mm_interconnect_0_pps_interrupt_s1_chipselect; // mm_interconnect_0:pps_interrupt_s1_chipselect -> pps_interrupt:chipselect
wire [31:0] mm_interconnect_0_pps_interrupt_s1_readdata; // pps_interrupt:readdata -> mm_interconnect_0:pps_interrupt_s1_readdata
wire [1:0] mm_interconnect_0_pps_interrupt_s1_address; // mm_interconnect_0:pps_interrupt_s1_address -> pps_interrupt:address
wire mm_interconnect_0_pps_interrupt_s1_write; // mm_interconnect_0:pps_interrupt_s1_write -> pps_interrupt:write_n
wire [31:0] mm_interconnect_0_pps_interrupt_s1_writedata; // mm_interconnect_0:pps_interrupt_s1_writedata -> pps_interrupt:writedata
wire mm_interconnect_0_timer_ecc_fault_itr_s1_chipselect; // mm_interconnect_0:timer_ecc_fault_itr_s1_chipselect -> timer_ecc_fault_itr:chipselect
wire [31:0] mm_interconnect_0_timer_ecc_fault_itr_s1_readdata; // timer_ecc_fault_itr:readdata -> mm_interconnect_0:timer_ecc_fault_itr_s1_readdata
wire [1:0] mm_interconnect_0_timer_ecc_fault_itr_s1_address; // mm_interconnect_0:timer_ecc_fault_itr_s1_address -> timer_ecc_fault_itr:address
wire mm_interconnect_0_timer_ecc_fault_itr_s1_write; // mm_interconnect_0:timer_ecc_fault_itr_s1_write -> timer_ecc_fault_itr:write_n
wire [31:0] mm_interconnect_0_timer_ecc_fault_itr_s1_writedata; // mm_interconnect_0:timer_ecc_fault_itr_s1_writedata -> timer_ecc_fault_itr:writedata
wire mm_interconnect_0_sdram_controller_0_s1_chipselect; // mm_interconnect_0:sdram_controller_0_s1_chipselect -> sdram_controller_0:az_cs
wire [15:0] mm_interconnect_0_sdram_controller_0_s1_readdata; // sdram_controller_0:za_data -> mm_interconnect_0:sdram_controller_0_s1_readdata
wire mm_interconnect_0_sdram_controller_0_s1_waitrequest; // sdram_controller_0:za_waitrequest -> mm_interconnect_0:sdram_controller_0_s1_waitrequest
wire [21:0] mm_interconnect_0_sdram_controller_0_s1_address; // mm_interconnect_0:sdram_controller_0_s1_address -> sdram_controller_0:az_addr
wire mm_interconnect_0_sdram_controller_0_s1_read; // mm_interconnect_0:sdram_controller_0_s1_read -> sdram_controller_0:az_rd_n
wire [1:0] mm_interconnect_0_sdram_controller_0_s1_byteenable; // mm_interconnect_0:sdram_controller_0_s1_byteenable -> sdram_controller_0:az_be_n
wire mm_interconnect_0_sdram_controller_0_s1_readdatavalid; // sdram_controller_0:za_valid -> mm_interconnect_0:sdram_controller_0_s1_readdatavalid
wire mm_interconnect_0_sdram_controller_0_s1_write; // mm_interconnect_0:sdram_controller_0_s1_write -> sdram_controller_0:az_wr_n
wire [15:0] mm_interconnect_0_sdram_controller_0_s1_writedata; // mm_interconnect_0:sdram_controller_0_s1_writedata -> sdram_controller_0:az_data
wire mm_interconnect_0_uart_0_s1_chipselect; // mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect
wire [15:0] mm_interconnect_0_uart_0_s1_readdata; // uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata
wire [2:0] mm_interconnect_0_uart_0_s1_address; // mm_interconnect_0:uart_0_s1_address -> uart_0:address
wire mm_interconnect_0_uart_0_s1_read; // mm_interconnect_0:uart_0_s1_read -> uart_0:read_n
wire mm_interconnect_0_uart_0_s1_begintransfer; // mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer
wire mm_interconnect_0_uart_0_s1_write; // mm_interconnect_0:uart_0_s1_write -> uart_0:write_n
wire [15:0] mm_interconnect_0_uart_0_s1_writedata; // mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata
wire mm_interconnect_0_uart_1_s1_chipselect; // mm_interconnect_0:uart_1_s1_chipselect -> uart_1:chipselect
wire [15:0] mm_interconnect_0_uart_1_s1_readdata; // uart_1:readdata -> mm_interconnect_0:uart_1_s1_readdata
wire [2:0] mm_interconnect_0_uart_1_s1_address; // mm_interconnect_0:uart_1_s1_address -> uart_1:address
wire mm_interconnect_0_uart_1_s1_read; // mm_interconnect_0:uart_1_s1_read -> uart_1:read_n
wire mm_interconnect_0_uart_1_s1_begintransfer; // mm_interconnect_0:uart_1_s1_begintransfer -> uart_1:begintransfer
wire mm_interconnect_0_uart_1_s1_write; // mm_interconnect_0:uart_1_s1_write -> uart_1:write_n
wire [15:0] mm_interconnect_0_uart_1_s1_writedata; // mm_interconnect_0:uart_1_s1_writedata -> uart_1:writedata
wire mm_interconnect_0_uart_2_s1_chipselect; // mm_interconnect_0:uart_2_s1_chipselect -> uart_2:chipselect
wire [15:0] mm_interconnect_0_uart_2_s1_readdata; // uart_2:readdata -> mm_interconnect_0:uart_2_s1_readdata
wire [2:0] mm_interconnect_0_uart_2_s1_address; // mm_interconnect_0:uart_2_s1_address -> uart_2:address
wire mm_interconnect_0_uart_2_s1_read; // mm_interconnect_0:uart_2_s1_read -> uart_2:read_n
wire mm_interconnect_0_uart_2_s1_begintransfer; // mm_interconnect_0:uart_2_s1_begintransfer -> uart_2:begintransfer
wire mm_interconnect_0_uart_2_s1_write; // mm_interconnect_0:uart_2_s1_write -> uart_2:write_n
wire [15:0] mm_interconnect_0_uart_2_s1_writedata; // mm_interconnect_0:uart_2_s1_writedata -> uart_2:writedata
wire mm_interconnect_0_uart_3_s1_chipselect; // mm_interconnect_0:uart_3_s1_chipselect -> uart_3:chipselect
wire [15:0] mm_interconnect_0_uart_3_s1_readdata; // uart_3:readdata -> mm_interconnect_0:uart_3_s1_readdata
wire [2:0] mm_interconnect_0_uart_3_s1_address; // mm_interconnect_0:uart_3_s1_address -> uart_3:address
wire mm_interconnect_0_uart_3_s1_read; // mm_interconnect_0:uart_3_s1_read -> uart_3:read_n
wire mm_interconnect_0_uart_3_s1_begintransfer; // mm_interconnect_0:uart_3_s1_begintransfer -> uart_3:begintransfer
wire mm_interconnect_0_uart_3_s1_write; // mm_interconnect_0:uart_3_s1_write -> uart_3:write_n
wire [15:0] mm_interconnect_0_uart_3_s1_writedata; // mm_interconnect_0:uart_3_s1_writedata -> uart_3:writedata
wire irq_mapper_receiver0_irq; // uart_0:irq -> irq_mapper:receiver0_irq
wire irq_mapper_receiver1_irq; // uart_1:irq -> irq_mapper:receiver1_irq
wire irq_mapper_receiver2_irq; // uart_2:irq -> irq_mapper:receiver2_irq
wire irq_mapper_receiver3_irq; // uart_3:irq -> irq_mapper:receiver3_irq
wire irq_mapper_receiver4_irq; // pps_interrupt:irq -> irq_mapper:receiver4_irq
wire irq_mapper_receiver5_irq; // timer_ecc_fault_itr:irq -> irq_mapper:receiver5_irq
wire irq_mapper_receiver6_irq; // ocxo_lock:irq -> irq_mapper:receiver6_irq
wire irq_mapper_receiver7_irq; // epcs_flash_controller_0:irq -> irq_mapper:receiver7_irq
wire [31:0] nios2_gen2_0_irq_irq; // irq_mapper:sender_irq -> nios2_gen2_0:irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [avalon_mapped_timer_reg_buf_0:csi_reset_n, epcs_flash_controller_0:reset_n, io_update:reset_n, irq_mapper:reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, nios2_gen2_0:reset_n, ocxo_lock:reset_n, onchip_memory2_0:reset, onchip_rst_and_pps_switch:reset_n, pps_interrupt:reset_n, rst_translator:in_reset, sdram_controller_0:reset_n, timer_ecc_fault_itr:reset_n, uart_0:reset_n, uart_1:reset_n, uart_2:reset_n, uart_3:reset_n]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [epcs_flash_controller_0:reset_req, nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
wire nios2_gen2_0_debug_reset_request_reset; // nios2_gen2_0:debug_reset_request -> rst_controller:reset_in1
TimeHoldOver_Qsys_avalon_mapped_timer_reg_buf_0 avalon_mapped_timer_reg_buf_0 (
.csi_clk (clk_clk), // clock.clk
.csi_reset_n (~rst_controller_reset_out_reset), // clock_reset.reset_n
.coe_sec_cnt_set_data_out (timer_interface_coe_sec_cnt_set_data_out), // timer_interface.coe_sec_cnt_set_data_out
.coe_sec_cnt_get_data_in (timer_interface_coe_sec_cnt_get_data_in), // .coe_sec_cnt_get_data_in
.coe_ns_cnt_set_data_out (timer_interface_coe_ns_cnt_set_data_out), // .coe_ns_cnt_set_data_out
.coe_ns_cnt_get_data_in (timer_interface_coe_ns_cnt_get_data_in), // .coe_ns_cnt_get_data_in
.coe_ctrl_cnt_set_out (timer_interface_coe_ctrl_cnt_set_out), // .coe_ctrl_cnt_set_out
.coe_ctrl_cnt_get_in (timer_interface_coe_ctrl_cnt_get_in), // .coe_ctrl_cnt_get_in
.coe_err_cnt_in (timer_interface_coe_err_cnt_in), // .coe_err_cnt_in
.coe_utc_time_in (timer_interface_coe_utc_time_in), // .coe_utc_time_in
.coe_time_zone_set_out (timer_interface_coe_time_zone_set_out), // .coe_time_zone_set_out
.coe_time_zone_get_in (timer_interface_coe_time_zone_get_in), // .coe_time_zone_get_in
.coe_leap_cnt_set_out (timer_interface_coe_leap_cnt_set_out), // .coe_leap_cnt_set_out
.coe_leap_cnt_get_in (timer_interface_coe_leap_cnt_get_in), // .coe_leap_cnt_get_in
.coe_leap_occur_set_out (timer_interface_coe_leap_occur_set_out), // .coe_leap_occur_set_out
.coe_leap_occur_get_in (timer_interface_coe_leap_occur_get_in), // .coe_leap_occur_get_in
.coe_dst_ingress_set_out (timer_interface_coe_dst_ingress_set_out), // .coe_dst_ingress_set_out
.coe_dst_ingress_get_in (timer_interface_coe_dst_ingress_get_in), // .coe_dst_ingress_get_in
.coe_dst_engress_set_out (timer_interface_coe_dst_engress_set_out), // .coe_dst_engress_set_out
.coe_dst_engress_get_in (timer_interface_coe_dst_engress_get_in), // .coe_dst_engress_get_in
.coe_leap_direct_get_in (timer_interface_coe_leap_direct_get_in), // .coe_leap_direct_get_in
.coe_leap_direct_set_out (timer_interface_coe_leap_direct_set_out), // .coe_leap_direct_set_out
.coe_io_update_in (timer_interface_coe_io_update_in), // .coe_io_update_in
.coe_time_quality_get_in (timer_interface_coe_time_quality_get_in), // .coe_time_quality_get_in
.coe_time_quality_set_out (timer_interface_coe_time_quality_set_out), // .coe_time_quality_set_out
.avs_address (mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_address), // avalon_slave_0.address
.avs_read_n (~mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_read), // .read_n
.avs_readdata (mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_readdata), // .readdata
.avs_write_n (~mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_write), // .write_n
.avs_writedata (mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_writedata) // .writedata
);
TimeHoldOver_Qsys_epcs_flash_controller_0 epcs_flash_controller_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.address (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_address), // epcs_control_port.address
.chipselect (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_chipselect), // .chipselect
.read_n (~mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read), // .read_n
.readdata (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_readdata), // .readdata
.write_n (~mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write), // .write_n
.writedata (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_writedata), // .writedata
.irq (irq_mapper_receiver7_irq), // irq.irq
.dclk (epcs_flash_controller_dclk), // external.export
.sce (epcs_flash_controller_sce), // .export
.sdo (epcs_flash_controller_sdo), // .export
.data0 (epcs_flash_controller_data0) // .export
);
TimeHoldOver_Qsys_io_update io_update (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_io_update_s1_address), // s1.address
.write_n (~mm_interconnect_0_io_update_s1_write), // .write_n
.writedata (mm_interconnect_0_io_update_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_io_update_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_io_update_s1_readdata), // .readdata
.out_port (io_update_ctrl_export) // external_connection.export
);
TimeHoldOver_Qsys_nios2_gen2_0 nios2_gen2_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.d_address (nios2_gen2_0_data_master_address), // data_master.address
.d_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.d_read (nios2_gen2_0_data_master_read), // .read
.d_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.d_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.d_write (nios2_gen2_0_data_master_write), // .write
.d_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.d_readdatavalid (nios2_gen2_0_data_master_readdatavalid), // .readdatavalid
.debug_mem_slave_debugaccess_to_roms (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.i_address (nios2_gen2_0_instruction_master_address), // instruction_master.address
.i_read (nios2_gen2_0_instruction_master_read), // .read
.i_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.i_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.i_readdatavalid (nios2_gen2_0_instruction_master_readdatavalid), // .readdatavalid
.irq (nios2_gen2_0_irq_irq), // irq.irq
.debug_reset_request (nios2_gen2_0_debug_reset_request_reset), // debug_reset_request.reset
.debug_mem_slave_address (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read), // .read
.debug_mem_slave_readdata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write), // .write
.debug_mem_slave_writedata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.dummy_ci_port () // custom_instruction_master.readra
);
TimeHoldOver_Qsys_ocxo_lock ocxo_lock (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_ocxo_lock_s1_address), // s1.address
.write_n (~mm_interconnect_0_ocxo_lock_s1_write), // .write_n
.writedata (mm_interconnect_0_ocxo_lock_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_ocxo_lock_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_ocxo_lock_s1_readdata), // .readdata
.in_port (ocxo_lock_export), // external_connection.export
.irq (irq_mapper_receiver6_irq) // irq.irq
);
TimeHoldOver_Qsys_onchip_memory2_0 onchip_memory2_0 (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_0_onchip_memory2_0_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
TimeHoldOver_Qsys_onchip_rst_and_pps_switch onchip_rst_and_pps_switch (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_onchip_rst_and_pps_switch_s1_address), // s1.address
.write_n (~mm_interconnect_0_onchip_rst_and_pps_switch_s1_write), // .write_n
.writedata (mm_interconnect_0_onchip_rst_and_pps_switch_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_onchip_rst_and_pps_switch_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_onchip_rst_and_pps_switch_s1_readdata), // .readdata
.out_port (on_chip_rst_and_pps_switch_export) // external_connection.export
);
TimeHoldOver_Qsys_pps_interrupt pps_interrupt (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_pps_interrupt_s1_address), // s1.address
.write_n (~mm_interconnect_0_pps_interrupt_s1_write), // .write_n
.writedata (mm_interconnect_0_pps_interrupt_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_pps_interrupt_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_pps_interrupt_s1_readdata), // .readdata
.in_port (pps_interrupt_export), // external_connection.export
.irq (irq_mapper_receiver4_irq) // irq.irq
);
TimeHoldOver_Qsys_sdram_controller_0 sdram_controller_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.az_addr (mm_interconnect_0_sdram_controller_0_s1_address), // s1.address
.az_be_n (~mm_interconnect_0_sdram_controller_0_s1_byteenable), // .byteenable_n
.az_cs (mm_interconnect_0_sdram_controller_0_s1_chipselect), // .chipselect
.az_data (mm_interconnect_0_sdram_controller_0_s1_writedata), // .writedata
.az_rd_n (~mm_interconnect_0_sdram_controller_0_s1_read), // .read_n
.az_wr_n (~mm_interconnect_0_sdram_controller_0_s1_write), // .write_n
.za_data (mm_interconnect_0_sdram_controller_0_s1_readdata), // .readdata
.za_valid (mm_interconnect_0_sdram_controller_0_s1_readdatavalid), // .readdatavalid
.za_waitrequest (mm_interconnect_0_sdram_controller_0_s1_waitrequest), // .waitrequest
.zs_addr (sdram_controller_addr), // wire.export
.zs_ba (sdram_controller_ba), // .export
.zs_cas_n (sdram_controller_cas_n), // .export
.zs_cke (sdram_controller_cke), // .export
.zs_cs_n (sdram_controller_cs_n), // .export
.zs_dq (sdram_controller_dq), // .export
.zs_dqm (sdram_controller_dqm), // .export
.zs_ras_n (sdram_controller_ras_n), // .export
.zs_we_n (sdram_controller_we_n) // .export
);
TimeHoldOver_Qsys_pps_interrupt timer_ecc_fault_itr (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_timer_ecc_fault_itr_s1_address), // s1.address
.write_n (~mm_interconnect_0_timer_ecc_fault_itr_s1_write), // .write_n
.writedata (mm_interconnect_0_timer_ecc_fault_itr_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_timer_ecc_fault_itr_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_timer_ecc_fault_itr_s1_readdata), // .readdata
.in_port (timer_ecc_fault_itr_export), // external_connection.export
.irq (irq_mapper_receiver5_irq) // irq.irq
);
TimeHoldOver_Qsys_uart_0 uart_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_uart_0_s1_address), // s1.address
.begintransfer (mm_interconnect_0_uart_0_s1_begintransfer), // .begintransfer
.chipselect (mm_interconnect_0_uart_0_s1_chipselect), // .chipselect
.read_n (~mm_interconnect_0_uart_0_s1_read), // .read_n
.write_n (~mm_interconnect_0_uart_0_s1_write), // .write_n
.writedata (mm_interconnect_0_uart_0_s1_writedata), // .writedata
.readdata (mm_interconnect_0_uart_0_s1_readdata), // .readdata
.rxd (uart_0_external_connection_rxd), // external_connection.export
.txd (uart_0_external_connection_txd), // .export
.irq (irq_mapper_receiver0_irq) // irq.irq
);
TimeHoldOver_Qsys_uart_0 uart_1 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_uart_1_s1_address), // s1.address
.begintransfer (mm_interconnect_0_uart_1_s1_begintransfer), // .begintransfer
.chipselect (mm_interconnect_0_uart_1_s1_chipselect), // .chipselect
.read_n (~mm_interconnect_0_uart_1_s1_read), // .read_n
.write_n (~mm_interconnect_0_uart_1_s1_write), // .write_n
.writedata (mm_interconnect_0_uart_1_s1_writedata), // .writedata
.readdata (mm_interconnect_0_uart_1_s1_readdata), // .readdata
.rxd (uart_1_external_connection_rxd), // external_connection.export
.txd (uart_1_external_connection_txd), // .export
.irq (irq_mapper_receiver1_irq) // irq.irq
);
TimeHoldOver_Qsys_uart_0 uart_2 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_uart_2_s1_address), // s1.address
.begintransfer (mm_interconnect_0_uart_2_s1_begintransfer), // .begintransfer
.chipselect (mm_interconnect_0_uart_2_s1_chipselect), // .chipselect
.read_n (~mm_interconnect_0_uart_2_s1_read), // .read_n
.write_n (~mm_interconnect_0_uart_2_s1_write), // .write_n
.writedata (mm_interconnect_0_uart_2_s1_writedata), // .writedata
.readdata (mm_interconnect_0_uart_2_s1_readdata), // .readdata
.rxd (uart_2_external_connection_rxd), // external_connection.export
.txd (uart_2_external_connection_txd), // .export
.irq (irq_mapper_receiver2_irq) // irq.irq
);
TimeHoldOver_Qsys_uart_0 uart_3 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_uart_3_s1_address), // s1.address
.begintransfer (mm_interconnect_0_uart_3_s1_begintransfer), // .begintransfer
.chipselect (mm_interconnect_0_uart_3_s1_chipselect), // .chipselect
.read_n (~mm_interconnect_0_uart_3_s1_read), // .read_n
.write_n (~mm_interconnect_0_uart_3_s1_write), // .write_n
.writedata (mm_interconnect_0_uart_3_s1_writedata), // .writedata
.readdata (mm_interconnect_0_uart_3_s1_readdata), // .readdata
.rxd (uart_3_external_connection_rxd), // external_connection.export
.txd (uart_3_external_connection_txd), // .export
.irq (irq_mapper_receiver3_irq) // irq.irq
);
TimeHoldOver_Qsys_mm_interconnect_0 mm_interconnect_0 (
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.nios2_gen2_0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // nios2_gen2_0_reset_reset_bridge_in_reset.reset
.nios2_gen2_0_data_master_address (nios2_gen2_0_data_master_address), // nios2_gen2_0_data_master.address
.nios2_gen2_0_data_master_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.nios2_gen2_0_data_master_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.nios2_gen2_0_data_master_read (nios2_gen2_0_data_master_read), // .read
.nios2_gen2_0_data_master_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.nios2_gen2_0_data_master_readdatavalid (nios2_gen2_0_data_master_readdatavalid), // .readdatavalid
.nios2_gen2_0_data_master_write (nios2_gen2_0_data_master_write), // .write
.nios2_gen2_0_data_master_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.nios2_gen2_0_data_master_debugaccess (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.nios2_gen2_0_instruction_master_address (nios2_gen2_0_instruction_master_address), // nios2_gen2_0_instruction_master.address
.nios2_gen2_0_instruction_master_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.nios2_gen2_0_instruction_master_read (nios2_gen2_0_instruction_master_read), // .read
.nios2_gen2_0_instruction_master_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.nios2_gen2_0_instruction_master_readdatavalid (nios2_gen2_0_instruction_master_readdatavalid), // .readdatavalid
.avalon_mapped_timer_reg_buf_0_avalon_slave_0_address (mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_address), // avalon_mapped_timer_reg_buf_0_avalon_slave_0.address
.avalon_mapped_timer_reg_buf_0_avalon_slave_0_write (mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_write), // .write
.avalon_mapped_timer_reg_buf_0_avalon_slave_0_read (mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_read), // .read
.avalon_mapped_timer_reg_buf_0_avalon_slave_0_readdata (mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_readdata), // .readdata
.avalon_mapped_timer_reg_buf_0_avalon_slave_0_writedata (mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_writedata), // .writedata
.epcs_flash_controller_0_epcs_control_port_address (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_address), // epcs_flash_controller_0_epcs_control_port.address
.epcs_flash_controller_0_epcs_control_port_write (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write), // .write
.epcs_flash_controller_0_epcs_control_port_read (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read), // .read
.epcs_flash_controller_0_epcs_control_port_readdata (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_readdata), // .readdata
.epcs_flash_controller_0_epcs_control_port_writedata (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_writedata), // .writedata
.epcs_flash_controller_0_epcs_control_port_chipselect (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_chipselect), // .chipselect
.io_update_s1_address (mm_interconnect_0_io_update_s1_address), // io_update_s1.address
.io_update_s1_write (mm_interconnect_0_io_update_s1_write), // .write
.io_update_s1_readdata (mm_interconnect_0_io_update_s1_readdata), // .readdata
.io_update_s1_writedata (mm_interconnect_0_io_update_s1_writedata), // .writedata
.io_update_s1_chipselect (mm_interconnect_0_io_update_s1_chipselect), // .chipselect
.nios2_gen2_0_debug_mem_slave_address (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address), // nios2_gen2_0_debug_mem_slave.address
.nios2_gen2_0_debug_mem_slave_write (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write), // .write
.nios2_gen2_0_debug_mem_slave_read (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read), // .read
.nios2_gen2_0_debug_mem_slave_readdata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.nios2_gen2_0_debug_mem_slave_writedata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.nios2_gen2_0_debug_mem_slave_byteenable (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.nios2_gen2_0_debug_mem_slave_waitrequest (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.nios2_gen2_0_debug_mem_slave_debugaccess (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.ocxo_lock_s1_address (mm_interconnect_0_ocxo_lock_s1_address), // ocxo_lock_s1.address
.ocxo_lock_s1_write (mm_interconnect_0_ocxo_lock_s1_write), // .write
.ocxo_lock_s1_readdata (mm_interconnect_0_ocxo_lock_s1_readdata), // .readdata
.ocxo_lock_s1_writedata (mm_interconnect_0_ocxo_lock_s1_writedata), // .writedata
.ocxo_lock_s1_chipselect (mm_interconnect_0_ocxo_lock_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_address (mm_interconnect_0_onchip_memory2_0_s1_address), // onchip_memory2_0_s1.address
.onchip_memory2_0_s1_write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.onchip_memory2_0_s1_readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.onchip_memory2_0_s1_writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.onchip_memory2_0_s1_byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.onchip_memory2_0_s1_chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.onchip_rst_and_pps_switch_s1_address (mm_interconnect_0_onchip_rst_and_pps_switch_s1_address), // onchip_rst_and_pps_switch_s1.address
.onchip_rst_and_pps_switch_s1_write (mm_interconnect_0_onchip_rst_and_pps_switch_s1_write), // .write
.onchip_rst_and_pps_switch_s1_readdata (mm_interconnect_0_onchip_rst_and_pps_switch_s1_readdata), // .readdata
.onchip_rst_and_pps_switch_s1_writedata (mm_interconnect_0_onchip_rst_and_pps_switch_s1_writedata), // .writedata
.onchip_rst_and_pps_switch_s1_chipselect (mm_interconnect_0_onchip_rst_and_pps_switch_s1_chipselect), // .chipselect
.pps_interrupt_s1_address (mm_interconnect_0_pps_interrupt_s1_address), // pps_interrupt_s1.address
.pps_interrupt_s1_write (mm_interconnect_0_pps_interrupt_s1_write), // .write
.pps_interrupt_s1_readdata (mm_interconnect_0_pps_interrupt_s1_readdata), // .readdata
.pps_interrupt_s1_writedata (mm_interconnect_0_pps_interrupt_s1_writedata), // .writedata
.pps_interrupt_s1_chipselect (mm_interconnect_0_pps_interrupt_s1_chipselect), // .chipselect
.sdram_controller_0_s1_address (mm_interconnect_0_sdram_controller_0_s1_address), // sdram_controller_0_s1.address
.sdram_controller_0_s1_write (mm_interconnect_0_sdram_controller_0_s1_write), // .write
.sdram_controller_0_s1_read (mm_interconnect_0_sdram_controller_0_s1_read), // .read
.sdram_controller_0_s1_readdata (mm_interconnect_0_sdram_controller_0_s1_readdata), // .readdata
.sdram_controller_0_s1_writedata (mm_interconnect_0_sdram_controller_0_s1_writedata), // .writedata
.sdram_controller_0_s1_byteenable (mm_interconnect_0_sdram_controller_0_s1_byteenable), // .byteenable
.sdram_controller_0_s1_readdatavalid (mm_interconnect_0_sdram_controller_0_s1_readdatavalid), // .readdatavalid
.sdram_controller_0_s1_waitrequest (mm_interconnect_0_sdram_controller_0_s1_waitrequest), // .waitrequest
.sdram_controller_0_s1_chipselect (mm_interconnect_0_sdram_controller_0_s1_chipselect), // .chipselect
.timer_ecc_fault_itr_s1_address (mm_interconnect_0_timer_ecc_fault_itr_s1_address), // timer_ecc_fault_itr_s1.address
.timer_ecc_fault_itr_s1_write (mm_interconnect_0_timer_ecc_fault_itr_s1_write), // .write
.timer_ecc_fault_itr_s1_readdata (mm_interconnect_0_timer_ecc_fault_itr_s1_readdata), // .readdata
.timer_ecc_fault_itr_s1_writedata (mm_interconnect_0_timer_ecc_fault_itr_s1_writedata), // .writedata
.timer_ecc_fault_itr_s1_chipselect (mm_interconnect_0_timer_ecc_fault_itr_s1_chipselect), // .chipselect
.uart_0_s1_address (mm_interconnect_0_uart_0_s1_address), // uart_0_s1.address
.uart_0_s1_write (mm_interconnect_0_uart_0_s1_write), // .write
.uart_0_s1_read (mm_interconnect_0_uart_0_s1_read), // .read
.uart_0_s1_readdata (mm_interconnect_0_uart_0_s1_readdata), // .readdata
.uart_0_s1_writedata (mm_interconnect_0_uart_0_s1_writedata), // .writedata
.uart_0_s1_begintransfer (mm_interconnect_0_uart_0_s1_begintransfer), // .begintransfer
.uart_0_s1_chipselect (mm_interconnect_0_uart_0_s1_chipselect), // .chipselect
.uart_1_s1_address (mm_interconnect_0_uart_1_s1_address), // uart_1_s1.address
.uart_1_s1_write (mm_interconnect_0_uart_1_s1_write), // .write
.uart_1_s1_read (mm_interconnect_0_uart_1_s1_read), // .read
.uart_1_s1_readdata (mm_interconnect_0_uart_1_s1_readdata), // .readdata
.uart_1_s1_writedata (mm_interconnect_0_uart_1_s1_writedata), // .writedata
.uart_1_s1_begintransfer (mm_interconnect_0_uart_1_s1_begintransfer), // .begintransfer
.uart_1_s1_chipselect (mm_interconnect_0_uart_1_s1_chipselect), // .chipselect
.uart_2_s1_address (mm_interconnect_0_uart_2_s1_address), // uart_2_s1.address
.uart_2_s1_write (mm_interconnect_0_uart_2_s1_write), // .write
.uart_2_s1_read (mm_interconnect_0_uart_2_s1_read), // .read
.uart_2_s1_readdata (mm_interconnect_0_uart_2_s1_readdata), // .readdata
.uart_2_s1_writedata (mm_interconnect_0_uart_2_s1_writedata), // .writedata
.uart_2_s1_begintransfer (mm_interconnect_0_uart_2_s1_begintransfer), // .begintransfer
.uart_2_s1_chipselect (mm_interconnect_0_uart_2_s1_chipselect), // .chipselect
.uart_3_s1_address (mm_interconnect_0_uart_3_s1_address), // uart_3_s1.address
.uart_3_s1_write (mm_interconnect_0_uart_3_s1_write), // .write
.uart_3_s1_read (mm_interconnect_0_uart_3_s1_read), // .read
.uart_3_s1_readdata (mm_interconnect_0_uart_3_s1_readdata), // .readdata
.uart_3_s1_writedata (mm_interconnect_0_uart_3_s1_writedata), // .writedata
.uart_3_s1_begintransfer (mm_interconnect_0_uart_3_s1_begintransfer), // .begintransfer
.uart_3_s1_chipselect (mm_interconnect_0_uart_3_s1_chipselect) // .chipselect
);
TimeHoldOver_Qsys_irq_mapper irq_mapper (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.receiver2_irq (irq_mapper_receiver2_irq), // receiver2.irq
.receiver3_irq (irq_mapper_receiver3_irq), // receiver3.irq
.receiver4_irq (irq_mapper_receiver4_irq), // receiver4.irq
.receiver5_irq (irq_mapper_receiver5_irq), // receiver5.irq
.receiver6_irq (irq_mapper_receiver6_irq), // receiver6.irq
.receiver7_irq (irq_mapper_receiver7_irq), // receiver7.irq
.sender_irq (nios2_gen2_0_irq_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (nios2_gen2_0_debug_reset_request_reset), // reset_in1.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module fifo_w16_d2_A_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module fifo_w16_d2_A (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
fifo_w16_d2_A_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_fifo_w16_d2_A_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
// usb_system_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.04.28.18:25:01
`timescale 1 ps / 1 ps
module usb_system_mm_interconnect_0 (
input wire clk_clk_clk, // clk_clk.clk
input wire clocks_c0_clk, // clocks_c0.clk
input wire cpu_reset_n_reset_bridge_in_reset_reset, // cpu_reset_n_reset_bridge_in_reset.reset
input wire sdram_reset_reset_bridge_in_reset_reset, // sdram_reset_reset_bridge_in_reset.reset
input wire [28:0] cpu_data_master_address, // cpu_data_master.address
output wire cpu_data_master_waitrequest, // .waitrequest
input wire [3:0] cpu_data_master_byteenable, // .byteenable
input wire cpu_data_master_read, // .read
output wire [31:0] cpu_data_master_readdata, // .readdata
input wire cpu_data_master_write, // .write
input wire [31:0] cpu_data_master_writedata, // .writedata
input wire cpu_data_master_debugaccess, // .debugaccess
input wire [28:0] cpu_instruction_master_address, // cpu_instruction_master.address
output wire cpu_instruction_master_waitrequest, // .waitrequest
input wire cpu_instruction_master_read, // .read
output wire [31:0] cpu_instruction_master_readdata, // .readdata
output wire [21:0] clock_crossing_io_s0_address, // clock_crossing_io_s0.address
output wire clock_crossing_io_s0_write, // .write
output wire clock_crossing_io_s0_read, // .read
input wire [31:0] clock_crossing_io_s0_readdata, // .readdata
output wire [31:0] clock_crossing_io_s0_writedata, // .writedata
output wire [0:0] clock_crossing_io_s0_burstcount, // .burstcount
output wire [3:0] clock_crossing_io_s0_byteenable, // .byteenable
input wire clock_crossing_io_s0_readdatavalid, // .readdatavalid
input wire clock_crossing_io_s0_waitrequest, // .waitrequest
output wire clock_crossing_io_s0_debugaccess, // .debugaccess
output wire [1:0] clocks_pll_slave_address, // clocks_pll_slave.address
output wire clocks_pll_slave_write, // .write
output wire clocks_pll_slave_read, // .read
input wire [31:0] clocks_pll_slave_readdata, // .readdata
output wire [31:0] clocks_pll_slave_writedata, // .writedata
output wire [8:0] cpu_jtag_debug_module_address, // cpu_jtag_debug_module.address
output wire cpu_jtag_debug_module_write, // .write
output wire cpu_jtag_debug_module_read, // .read
input wire [31:0] cpu_jtag_debug_module_readdata, // .readdata
output wire [31:0] cpu_jtag_debug_module_writedata, // .writedata
output wire [3:0] cpu_jtag_debug_module_byteenable, // .byteenable
input wire cpu_jtag_debug_module_waitrequest, // .waitrequest
output wire cpu_jtag_debug_module_debugaccess, // .debugaccess
output wire [0:0] jtag_uart_avalon_jtag_slave_address, // jtag_uart_avalon_jtag_slave.address
output wire jtag_uart_avalon_jtag_slave_write, // .write
output wire jtag_uart_avalon_jtag_slave_read, // .read
input wire [31:0] jtag_uart_avalon_jtag_slave_readdata, // .readdata
output wire [31:0] jtag_uart_avalon_jtag_slave_writedata, // .writedata
input wire jtag_uart_avalon_jtag_slave_waitrequest, // .waitrequest
output wire jtag_uart_avalon_jtag_slave_chipselect, // .chipselect
output wire [1:0] keycode_s1_address, // keycode_s1.address
output wire keycode_s1_write, // .write
input wire [31:0] keycode_s1_readdata, // .readdata
output wire [31:0] keycode_s1_writedata, // .writedata
output wire keycode_s1_chipselect, // .chipselect
output wire [24:0] sdram_s1_address, // sdram_s1.address
output wire sdram_s1_write, // .write
output wire sdram_s1_read, // .read
input wire [31:0] sdram_s1_readdata, // .readdata
output wire [31:0] sdram_s1_writedata, // .writedata
output wire [3:0] sdram_s1_byteenable, // .byteenable
input wire sdram_s1_readdatavalid, // .readdatavalid
input wire sdram_s1_waitrequest, // .waitrequest
output wire sdram_s1_chipselect // .chipselect
);
wire cpu_data_master_translator_avalon_universal_master_0_waitrequest; // cpu_data_master_agent:av_waitrequest -> cpu_data_master_translator:uav_waitrequest
wire [2:0] cpu_data_master_translator_avalon_universal_master_0_burstcount; // cpu_data_master_translator:uav_burstcount -> cpu_data_master_agent:av_burstcount
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_writedata; // cpu_data_master_translator:uav_writedata -> cpu_data_master_agent:av_writedata
wire [28:0] cpu_data_master_translator_avalon_universal_master_0_address; // cpu_data_master_translator:uav_address -> cpu_data_master_agent:av_address
wire cpu_data_master_translator_avalon_universal_master_0_lock; // cpu_data_master_translator:uav_lock -> cpu_data_master_agent:av_lock
wire cpu_data_master_translator_avalon_universal_master_0_write; // cpu_data_master_translator:uav_write -> cpu_data_master_agent:av_write
wire cpu_data_master_translator_avalon_universal_master_0_read; // cpu_data_master_translator:uav_read -> cpu_data_master_agent:av_read
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_readdata; // cpu_data_master_agent:av_readdata -> cpu_data_master_translator:uav_readdata
wire cpu_data_master_translator_avalon_universal_master_0_debugaccess; // cpu_data_master_translator:uav_debugaccess -> cpu_data_master_agent:av_debugaccess
wire [3:0] cpu_data_master_translator_avalon_universal_master_0_byteenable; // cpu_data_master_translator:uav_byteenable -> cpu_data_master_agent:av_byteenable
wire cpu_data_master_translator_avalon_universal_master_0_readdatavalid; // cpu_data_master_agent:av_readdatavalid -> cpu_data_master_translator:uav_readdatavalid
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> cpu_data_master_agent:rp_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> cpu_data_master_agent:rp_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> cpu_data_master_agent:rp_startofpacket
wire [104:0] rsp_mux_src_data; // rsp_mux:src_data -> cpu_data_master_agent:rp_data
wire [5:0] rsp_mux_src_channel; // rsp_mux:src_channel -> cpu_data_master_agent:rp_channel
wire rsp_mux_src_ready; // cpu_data_master_agent:rp_ready -> rsp_mux:src_ready
wire cpu_instruction_master_translator_avalon_universal_master_0_waitrequest; // cpu_instruction_master_agent:av_waitrequest -> cpu_instruction_master_translator:uav_waitrequest
wire [2:0] cpu_instruction_master_translator_avalon_universal_master_0_burstcount; // cpu_instruction_master_translator:uav_burstcount -> cpu_instruction_master_agent:av_burstcount
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_writedata; // cpu_instruction_master_translator:uav_writedata -> cpu_instruction_master_agent:av_writedata
wire [28:0] cpu_instruction_master_translator_avalon_universal_master_0_address; // cpu_instruction_master_translator:uav_address -> cpu_instruction_master_agent:av_address
wire cpu_instruction_master_translator_avalon_universal_master_0_lock; // cpu_instruction_master_translator:uav_lock -> cpu_instruction_master_agent:av_lock
wire cpu_instruction_master_translator_avalon_universal_master_0_write; // cpu_instruction_master_translator:uav_write -> cpu_instruction_master_agent:av_write
wire cpu_instruction_master_translator_avalon_universal_master_0_read; // cpu_instruction_master_translator:uav_read -> cpu_instruction_master_agent:av_read
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_readdata; // cpu_instruction_master_agent:av_readdata -> cpu_instruction_master_translator:uav_readdata
wire cpu_instruction_master_translator_avalon_universal_master_0_debugaccess; // cpu_instruction_master_translator:uav_debugaccess -> cpu_instruction_master_agent:av_debugaccess
wire [3:0] cpu_instruction_master_translator_avalon_universal_master_0_byteenable; // cpu_instruction_master_translator:uav_byteenable -> cpu_instruction_master_agent:av_byteenable
wire cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid; // cpu_instruction_master_agent:av_readdatavalid -> cpu_instruction_master_translator:uav_readdatavalid
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> cpu_instruction_master_agent:rp_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> cpu_instruction_master_agent:rp_valid
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> cpu_instruction_master_agent:rp_startofpacket
wire [104:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> cpu_instruction_master_agent:rp_data
wire [5:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> cpu_instruction_master_agent:rp_channel
wire rsp_mux_001_src_ready; // cpu_instruction_master_agent:rp_ready -> rsp_mux_001:src_ready
wire jtag_uart_avalon_jtag_slave_agent_m0_waitrequest; // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_agent:m0_waitrequest
wire [2:0] jtag_uart_avalon_jtag_slave_agent_m0_burstcount; // jtag_uart_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_writedata; // jtag_uart_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata
wire [28:0] jtag_uart_avalon_jtag_slave_agent_m0_address; // jtag_uart_avalon_jtag_slave_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address
wire jtag_uart_avalon_jtag_slave_agent_m0_write; // jtag_uart_avalon_jtag_slave_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write
wire jtag_uart_avalon_jtag_slave_agent_m0_lock; // jtag_uart_avalon_jtag_slave_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock
wire jtag_uart_avalon_jtag_slave_agent_m0_read; // jtag_uart_avalon_jtag_slave_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_readdata; // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_agent:m0_readdata
wire jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid; // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_agent:m0_readdatavalid
wire jtag_uart_avalon_jtag_slave_agent_m0_debugaccess; // jtag_uart_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess
wire [3:0] jtag_uart_avalon_jtag_slave_agent_m0_byteenable; // jtag_uart_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket; // jtag_uart_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rf_source_valid; // jtag_uart_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_valid
wire jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket; // jtag_uart_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
wire [105:0] jtag_uart_avalon_jtag_slave_agent_rf_source_data; // jtag_uart_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_data
wire jtag_uart_avalon_jtag_slave_agent_rf_source_ready; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_agent:rf_source_ready
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_agent:rf_sink_valid
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_startofpacket
wire [105:0] jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_agent:rf_sink_data
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready; // jtag_uart_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_ready
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_valid
wire [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_data
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> jtag_uart_avalon_jtag_slave_agent:cp_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_startofpacket
wire [104:0] cmd_mux_src_data; // cmd_mux:src_data -> jtag_uart_avalon_jtag_slave_agent:cp_data
wire [5:0] cmd_mux_src_channel; // cmd_mux:src_channel -> jtag_uart_avalon_jtag_slave_agent:cp_channel
wire cmd_mux_src_ready; // jtag_uart_avalon_jtag_slave_agent:cp_ready -> cmd_mux:src_ready
wire cpu_jtag_debug_module_agent_m0_waitrequest; // cpu_jtag_debug_module_translator:uav_waitrequest -> cpu_jtag_debug_module_agent:m0_waitrequest
wire [2:0] cpu_jtag_debug_module_agent_m0_burstcount; // cpu_jtag_debug_module_agent:m0_burstcount -> cpu_jtag_debug_module_translator:uav_burstcount
wire [31:0] cpu_jtag_debug_module_agent_m0_writedata; // cpu_jtag_debug_module_agent:m0_writedata -> cpu_jtag_debug_module_translator:uav_writedata
wire [28:0] cpu_jtag_debug_module_agent_m0_address; // cpu_jtag_debug_module_agent:m0_address -> cpu_jtag_debug_module_translator:uav_address
wire cpu_jtag_debug_module_agent_m0_write; // cpu_jtag_debug_module_agent:m0_write -> cpu_jtag_debug_module_translator:uav_write
wire cpu_jtag_debug_module_agent_m0_lock; // cpu_jtag_debug_module_agent:m0_lock -> cpu_jtag_debug_module_translator:uav_lock
wire cpu_jtag_debug_module_agent_m0_read; // cpu_jtag_debug_module_agent:m0_read -> cpu_jtag_debug_module_translator:uav_read
wire [31:0] cpu_jtag_debug_module_agent_m0_readdata; // cpu_jtag_debug_module_translator:uav_readdata -> cpu_jtag_debug_module_agent:m0_readdata
wire cpu_jtag_debug_module_agent_m0_readdatavalid; // cpu_jtag_debug_module_translator:uav_readdatavalid -> cpu_jtag_debug_module_agent:m0_readdatavalid
wire cpu_jtag_debug_module_agent_m0_debugaccess; // cpu_jtag_debug_module_agent:m0_debugaccess -> cpu_jtag_debug_module_translator:uav_debugaccess
wire [3:0] cpu_jtag_debug_module_agent_m0_byteenable; // cpu_jtag_debug_module_agent:m0_byteenable -> cpu_jtag_debug_module_translator:uav_byteenable
wire cpu_jtag_debug_module_agent_rf_source_endofpacket; // cpu_jtag_debug_module_agent:rf_source_endofpacket -> cpu_jtag_debug_module_agent_rsp_fifo:in_endofpacket
wire cpu_jtag_debug_module_agent_rf_source_valid; // cpu_jtag_debug_module_agent:rf_source_valid -> cpu_jtag_debug_module_agent_rsp_fifo:in_valid
wire cpu_jtag_debug_module_agent_rf_source_startofpacket; // cpu_jtag_debug_module_agent:rf_source_startofpacket -> cpu_jtag_debug_module_agent_rsp_fifo:in_startofpacket
wire [105:0] cpu_jtag_debug_module_agent_rf_source_data; // cpu_jtag_debug_module_agent:rf_source_data -> cpu_jtag_debug_module_agent_rsp_fifo:in_data
wire cpu_jtag_debug_module_agent_rf_source_ready; // cpu_jtag_debug_module_agent_rsp_fifo:in_ready -> cpu_jtag_debug_module_agent:rf_source_ready
wire cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket; // cpu_jtag_debug_module_agent_rsp_fifo:out_endofpacket -> cpu_jtag_debug_module_agent:rf_sink_endofpacket
wire cpu_jtag_debug_module_agent_rsp_fifo_out_valid; // cpu_jtag_debug_module_agent_rsp_fifo:out_valid -> cpu_jtag_debug_module_agent:rf_sink_valid
wire cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket; // cpu_jtag_debug_module_agent_rsp_fifo:out_startofpacket -> cpu_jtag_debug_module_agent:rf_sink_startofpacket
wire [105:0] cpu_jtag_debug_module_agent_rsp_fifo_out_data; // cpu_jtag_debug_module_agent_rsp_fifo:out_data -> cpu_jtag_debug_module_agent:rf_sink_data
wire cpu_jtag_debug_module_agent_rsp_fifo_out_ready; // cpu_jtag_debug_module_agent:rf_sink_ready -> cpu_jtag_debug_module_agent_rsp_fifo:out_ready
wire cpu_jtag_debug_module_agent_rdata_fifo_src_valid; // cpu_jtag_debug_module_agent:rdata_fifo_src_valid -> cpu_jtag_debug_module_agent:rdata_fifo_sink_valid
wire [33:0] cpu_jtag_debug_module_agent_rdata_fifo_src_data; // cpu_jtag_debug_module_agent:rdata_fifo_src_data -> cpu_jtag_debug_module_agent:rdata_fifo_sink_data
wire cpu_jtag_debug_module_agent_rdata_fifo_src_ready; // cpu_jtag_debug_module_agent:rdata_fifo_sink_ready -> cpu_jtag_debug_module_agent:rdata_fifo_src_ready
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> cpu_jtag_debug_module_agent:cp_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> cpu_jtag_debug_module_agent:cp_valid
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> cpu_jtag_debug_module_agent:cp_startofpacket
wire [104:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> cpu_jtag_debug_module_agent:cp_data
wire [5:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> cpu_jtag_debug_module_agent:cp_channel
wire cmd_mux_001_src_ready; // cpu_jtag_debug_module_agent:cp_ready -> cmd_mux_001:src_ready
wire clocks_pll_slave_agent_m0_waitrequest; // clocks_pll_slave_translator:uav_waitrequest -> clocks_pll_slave_agent:m0_waitrequest
wire [2:0] clocks_pll_slave_agent_m0_burstcount; // clocks_pll_slave_agent:m0_burstcount -> clocks_pll_slave_translator:uav_burstcount
wire [31:0] clocks_pll_slave_agent_m0_writedata; // clocks_pll_slave_agent:m0_writedata -> clocks_pll_slave_translator:uav_writedata
wire [28:0] clocks_pll_slave_agent_m0_address; // clocks_pll_slave_agent:m0_address -> clocks_pll_slave_translator:uav_address
wire clocks_pll_slave_agent_m0_write; // clocks_pll_slave_agent:m0_write -> clocks_pll_slave_translator:uav_write
wire clocks_pll_slave_agent_m0_lock; // clocks_pll_slave_agent:m0_lock -> clocks_pll_slave_translator:uav_lock
wire clocks_pll_slave_agent_m0_read; // clocks_pll_slave_agent:m0_read -> clocks_pll_slave_translator:uav_read
wire [31:0] clocks_pll_slave_agent_m0_readdata; // clocks_pll_slave_translator:uav_readdata -> clocks_pll_slave_agent:m0_readdata
wire clocks_pll_slave_agent_m0_readdatavalid; // clocks_pll_slave_translator:uav_readdatavalid -> clocks_pll_slave_agent:m0_readdatavalid
wire clocks_pll_slave_agent_m0_debugaccess; // clocks_pll_slave_agent:m0_debugaccess -> clocks_pll_slave_translator:uav_debugaccess
wire [3:0] clocks_pll_slave_agent_m0_byteenable; // clocks_pll_slave_agent:m0_byteenable -> clocks_pll_slave_translator:uav_byteenable
wire clocks_pll_slave_agent_rf_source_endofpacket; // clocks_pll_slave_agent:rf_source_endofpacket -> clocks_pll_slave_agent_rsp_fifo:in_endofpacket
wire clocks_pll_slave_agent_rf_source_valid; // clocks_pll_slave_agent:rf_source_valid -> clocks_pll_slave_agent_rsp_fifo:in_valid
wire clocks_pll_slave_agent_rf_source_startofpacket; // clocks_pll_slave_agent:rf_source_startofpacket -> clocks_pll_slave_agent_rsp_fifo:in_startofpacket
wire [105:0] clocks_pll_slave_agent_rf_source_data; // clocks_pll_slave_agent:rf_source_data -> clocks_pll_slave_agent_rsp_fifo:in_data
wire clocks_pll_slave_agent_rf_source_ready; // clocks_pll_slave_agent_rsp_fifo:in_ready -> clocks_pll_slave_agent:rf_source_ready
wire clocks_pll_slave_agent_rsp_fifo_out_endofpacket; // clocks_pll_slave_agent_rsp_fifo:out_endofpacket -> clocks_pll_slave_agent:rf_sink_endofpacket
wire clocks_pll_slave_agent_rsp_fifo_out_valid; // clocks_pll_slave_agent_rsp_fifo:out_valid -> clocks_pll_slave_agent:rf_sink_valid
wire clocks_pll_slave_agent_rsp_fifo_out_startofpacket; // clocks_pll_slave_agent_rsp_fifo:out_startofpacket -> clocks_pll_slave_agent:rf_sink_startofpacket
wire [105:0] clocks_pll_slave_agent_rsp_fifo_out_data; // clocks_pll_slave_agent_rsp_fifo:out_data -> clocks_pll_slave_agent:rf_sink_data
wire clocks_pll_slave_agent_rsp_fifo_out_ready; // clocks_pll_slave_agent:rf_sink_ready -> clocks_pll_slave_agent_rsp_fifo:out_ready
wire clocks_pll_slave_agent_rdata_fifo_src_valid; // clocks_pll_slave_agent:rdata_fifo_src_valid -> clocks_pll_slave_agent:rdata_fifo_sink_valid
wire [33:0] clocks_pll_slave_agent_rdata_fifo_src_data; // clocks_pll_slave_agent:rdata_fifo_src_data -> clocks_pll_slave_agent:rdata_fifo_sink_data
wire clocks_pll_slave_agent_rdata_fifo_src_ready; // clocks_pll_slave_agent:rdata_fifo_sink_ready -> clocks_pll_slave_agent:rdata_fifo_src_ready
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> clocks_pll_slave_agent:cp_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> clocks_pll_slave_agent:cp_valid
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> clocks_pll_slave_agent:cp_startofpacket
wire [104:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> clocks_pll_slave_agent:cp_data
wire [5:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> clocks_pll_slave_agent:cp_channel
wire cmd_mux_002_src_ready; // clocks_pll_slave_agent:cp_ready -> cmd_mux_002:src_ready
wire clock_crossing_io_s0_agent_m0_waitrequest; // clock_crossing_io_s0_translator:uav_waitrequest -> clock_crossing_io_s0_agent:m0_waitrequest
wire [2:0] clock_crossing_io_s0_agent_m0_burstcount; // clock_crossing_io_s0_agent:m0_burstcount -> clock_crossing_io_s0_translator:uav_burstcount
wire [31:0] clock_crossing_io_s0_agent_m0_writedata; // clock_crossing_io_s0_agent:m0_writedata -> clock_crossing_io_s0_translator:uav_writedata
wire [28:0] clock_crossing_io_s0_agent_m0_address; // clock_crossing_io_s0_agent:m0_address -> clock_crossing_io_s0_translator:uav_address
wire clock_crossing_io_s0_agent_m0_write; // clock_crossing_io_s0_agent:m0_write -> clock_crossing_io_s0_translator:uav_write
wire clock_crossing_io_s0_agent_m0_lock; // clock_crossing_io_s0_agent:m0_lock -> clock_crossing_io_s0_translator:uav_lock
wire clock_crossing_io_s0_agent_m0_read; // clock_crossing_io_s0_agent:m0_read -> clock_crossing_io_s0_translator:uav_read
wire [31:0] clock_crossing_io_s0_agent_m0_readdata; // clock_crossing_io_s0_translator:uav_readdata -> clock_crossing_io_s0_agent:m0_readdata
wire clock_crossing_io_s0_agent_m0_readdatavalid; // clock_crossing_io_s0_translator:uav_readdatavalid -> clock_crossing_io_s0_agent:m0_readdatavalid
wire clock_crossing_io_s0_agent_m0_debugaccess; // clock_crossing_io_s0_agent:m0_debugaccess -> clock_crossing_io_s0_translator:uav_debugaccess
wire [3:0] clock_crossing_io_s0_agent_m0_byteenable; // clock_crossing_io_s0_agent:m0_byteenable -> clock_crossing_io_s0_translator:uav_byteenable
wire clock_crossing_io_s0_agent_rf_source_endofpacket; // clock_crossing_io_s0_agent:rf_source_endofpacket -> clock_crossing_io_s0_agent_rsp_fifo:in_endofpacket
wire clock_crossing_io_s0_agent_rf_source_valid; // clock_crossing_io_s0_agent:rf_source_valid -> clock_crossing_io_s0_agent_rsp_fifo:in_valid
wire clock_crossing_io_s0_agent_rf_source_startofpacket; // clock_crossing_io_s0_agent:rf_source_startofpacket -> clock_crossing_io_s0_agent_rsp_fifo:in_startofpacket
wire [105:0] clock_crossing_io_s0_agent_rf_source_data; // clock_crossing_io_s0_agent:rf_source_data -> clock_crossing_io_s0_agent_rsp_fifo:in_data
wire clock_crossing_io_s0_agent_rf_source_ready; // clock_crossing_io_s0_agent_rsp_fifo:in_ready -> clock_crossing_io_s0_agent:rf_source_ready
wire clock_crossing_io_s0_agent_rsp_fifo_out_endofpacket; // clock_crossing_io_s0_agent_rsp_fifo:out_endofpacket -> clock_crossing_io_s0_agent:rf_sink_endofpacket
wire clock_crossing_io_s0_agent_rsp_fifo_out_valid; // clock_crossing_io_s0_agent_rsp_fifo:out_valid -> clock_crossing_io_s0_agent:rf_sink_valid
wire clock_crossing_io_s0_agent_rsp_fifo_out_startofpacket; // clock_crossing_io_s0_agent_rsp_fifo:out_startofpacket -> clock_crossing_io_s0_agent:rf_sink_startofpacket
wire [105:0] clock_crossing_io_s0_agent_rsp_fifo_out_data; // clock_crossing_io_s0_agent_rsp_fifo:out_data -> clock_crossing_io_s0_agent:rf_sink_data
wire clock_crossing_io_s0_agent_rsp_fifo_out_ready; // clock_crossing_io_s0_agent:rf_sink_ready -> clock_crossing_io_s0_agent_rsp_fifo:out_ready
wire clock_crossing_io_s0_agent_rdata_fifo_src_valid; // clock_crossing_io_s0_agent:rdata_fifo_src_valid -> clock_crossing_io_s0_agent:rdata_fifo_sink_valid
wire [33:0] clock_crossing_io_s0_agent_rdata_fifo_src_data; // clock_crossing_io_s0_agent:rdata_fifo_src_data -> clock_crossing_io_s0_agent:rdata_fifo_sink_data
wire clock_crossing_io_s0_agent_rdata_fifo_src_ready; // clock_crossing_io_s0_agent:rdata_fifo_sink_ready -> clock_crossing_io_s0_agent:rdata_fifo_src_ready
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> clock_crossing_io_s0_agent:cp_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> clock_crossing_io_s0_agent:cp_valid
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> clock_crossing_io_s0_agent:cp_startofpacket
wire [104:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> clock_crossing_io_s0_agent:cp_data
wire [5:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> clock_crossing_io_s0_agent:cp_channel
wire cmd_mux_003_src_ready; // clock_crossing_io_s0_agent:cp_ready -> cmd_mux_003:src_ready
wire keycode_s1_agent_m0_waitrequest; // keycode_s1_translator:uav_waitrequest -> keycode_s1_agent:m0_waitrequest
wire [2:0] keycode_s1_agent_m0_burstcount; // keycode_s1_agent:m0_burstcount -> keycode_s1_translator:uav_burstcount
wire [31:0] keycode_s1_agent_m0_writedata; // keycode_s1_agent:m0_writedata -> keycode_s1_translator:uav_writedata
wire [28:0] keycode_s1_agent_m0_address; // keycode_s1_agent:m0_address -> keycode_s1_translator:uav_address
wire keycode_s1_agent_m0_write; // keycode_s1_agent:m0_write -> keycode_s1_translator:uav_write
wire keycode_s1_agent_m0_lock; // keycode_s1_agent:m0_lock -> keycode_s1_translator:uav_lock
wire keycode_s1_agent_m0_read; // keycode_s1_agent:m0_read -> keycode_s1_translator:uav_read
wire [31:0] keycode_s1_agent_m0_readdata; // keycode_s1_translator:uav_readdata -> keycode_s1_agent:m0_readdata
wire keycode_s1_agent_m0_readdatavalid; // keycode_s1_translator:uav_readdatavalid -> keycode_s1_agent:m0_readdatavalid
wire keycode_s1_agent_m0_debugaccess; // keycode_s1_agent:m0_debugaccess -> keycode_s1_translator:uav_debugaccess
wire [3:0] keycode_s1_agent_m0_byteenable; // keycode_s1_agent:m0_byteenable -> keycode_s1_translator:uav_byteenable
wire keycode_s1_agent_rf_source_endofpacket; // keycode_s1_agent:rf_source_endofpacket -> keycode_s1_agent_rsp_fifo:in_endofpacket
wire keycode_s1_agent_rf_source_valid; // keycode_s1_agent:rf_source_valid -> keycode_s1_agent_rsp_fifo:in_valid
wire keycode_s1_agent_rf_source_startofpacket; // keycode_s1_agent:rf_source_startofpacket -> keycode_s1_agent_rsp_fifo:in_startofpacket
wire [105:0] keycode_s1_agent_rf_source_data; // keycode_s1_agent:rf_source_data -> keycode_s1_agent_rsp_fifo:in_data
wire keycode_s1_agent_rf_source_ready; // keycode_s1_agent_rsp_fifo:in_ready -> keycode_s1_agent:rf_source_ready
wire keycode_s1_agent_rsp_fifo_out_endofpacket; // keycode_s1_agent_rsp_fifo:out_endofpacket -> keycode_s1_agent:rf_sink_endofpacket
wire keycode_s1_agent_rsp_fifo_out_valid; // keycode_s1_agent_rsp_fifo:out_valid -> keycode_s1_agent:rf_sink_valid
wire keycode_s1_agent_rsp_fifo_out_startofpacket; // keycode_s1_agent_rsp_fifo:out_startofpacket -> keycode_s1_agent:rf_sink_startofpacket
wire [105:0] keycode_s1_agent_rsp_fifo_out_data; // keycode_s1_agent_rsp_fifo:out_data -> keycode_s1_agent:rf_sink_data
wire keycode_s1_agent_rsp_fifo_out_ready; // keycode_s1_agent:rf_sink_ready -> keycode_s1_agent_rsp_fifo:out_ready
wire keycode_s1_agent_rdata_fifo_src_valid; // keycode_s1_agent:rdata_fifo_src_valid -> keycode_s1_agent:rdata_fifo_sink_valid
wire [33:0] keycode_s1_agent_rdata_fifo_src_data; // keycode_s1_agent:rdata_fifo_src_data -> keycode_s1_agent:rdata_fifo_sink_data
wire keycode_s1_agent_rdata_fifo_src_ready; // keycode_s1_agent:rdata_fifo_sink_ready -> keycode_s1_agent:rdata_fifo_src_ready
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> keycode_s1_agent:cp_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> keycode_s1_agent:cp_valid
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> keycode_s1_agent:cp_startofpacket
wire [104:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> keycode_s1_agent:cp_data
wire [5:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> keycode_s1_agent:cp_channel
wire cmd_mux_004_src_ready; // keycode_s1_agent:cp_ready -> cmd_mux_004:src_ready
wire sdram_s1_agent_m0_waitrequest; // sdram_s1_translator:uav_waitrequest -> sdram_s1_agent:m0_waitrequest
wire [2:0] sdram_s1_agent_m0_burstcount; // sdram_s1_agent:m0_burstcount -> sdram_s1_translator:uav_burstcount
wire [31:0] sdram_s1_agent_m0_writedata; // sdram_s1_agent:m0_writedata -> sdram_s1_translator:uav_writedata
wire [28:0] sdram_s1_agent_m0_address; // sdram_s1_agent:m0_address -> sdram_s1_translator:uav_address
wire sdram_s1_agent_m0_write; // sdram_s1_agent:m0_write -> sdram_s1_translator:uav_write
wire sdram_s1_agent_m0_lock; // sdram_s1_agent:m0_lock -> sdram_s1_translator:uav_lock
wire sdram_s1_agent_m0_read; // sdram_s1_agent:m0_read -> sdram_s1_translator:uav_read
wire [31:0] sdram_s1_agent_m0_readdata; // sdram_s1_translator:uav_readdata -> sdram_s1_agent:m0_readdata
wire sdram_s1_agent_m0_readdatavalid; // sdram_s1_translator:uav_readdatavalid -> sdram_s1_agent:m0_readdatavalid
wire sdram_s1_agent_m0_debugaccess; // sdram_s1_agent:m0_debugaccess -> sdram_s1_translator:uav_debugaccess
wire [3:0] sdram_s1_agent_m0_byteenable; // sdram_s1_agent:m0_byteenable -> sdram_s1_translator:uav_byteenable
wire sdram_s1_agent_rf_source_endofpacket; // sdram_s1_agent:rf_source_endofpacket -> sdram_s1_agent_rsp_fifo:in_endofpacket
wire sdram_s1_agent_rf_source_valid; // sdram_s1_agent:rf_source_valid -> sdram_s1_agent_rsp_fifo:in_valid
wire sdram_s1_agent_rf_source_startofpacket; // sdram_s1_agent:rf_source_startofpacket -> sdram_s1_agent_rsp_fifo:in_startofpacket
wire [105:0] sdram_s1_agent_rf_source_data; // sdram_s1_agent:rf_source_data -> sdram_s1_agent_rsp_fifo:in_data
wire sdram_s1_agent_rf_source_ready; // sdram_s1_agent_rsp_fifo:in_ready -> sdram_s1_agent:rf_source_ready
wire sdram_s1_agent_rsp_fifo_out_endofpacket; // sdram_s1_agent_rsp_fifo:out_endofpacket -> sdram_s1_agent:rf_sink_endofpacket
wire sdram_s1_agent_rsp_fifo_out_valid; // sdram_s1_agent_rsp_fifo:out_valid -> sdram_s1_agent:rf_sink_valid
wire sdram_s1_agent_rsp_fifo_out_startofpacket; // sdram_s1_agent_rsp_fifo:out_startofpacket -> sdram_s1_agent:rf_sink_startofpacket
wire [105:0] sdram_s1_agent_rsp_fifo_out_data; // sdram_s1_agent_rsp_fifo:out_data -> sdram_s1_agent:rf_sink_data
wire sdram_s1_agent_rsp_fifo_out_ready; // sdram_s1_agent:rf_sink_ready -> sdram_s1_agent_rsp_fifo:out_ready
wire sdram_s1_agent_rdata_fifo_src_valid; // sdram_s1_agent:rdata_fifo_src_valid -> sdram_s1_agent_rdata_fifo:in_valid
wire [33:0] sdram_s1_agent_rdata_fifo_src_data; // sdram_s1_agent:rdata_fifo_src_data -> sdram_s1_agent_rdata_fifo:in_data
wire sdram_s1_agent_rdata_fifo_src_ready; // sdram_s1_agent_rdata_fifo:in_ready -> sdram_s1_agent:rdata_fifo_src_ready
wire sdram_s1_agent_rdata_fifo_out_valid; // sdram_s1_agent_rdata_fifo:out_valid -> sdram_s1_agent:rdata_fifo_sink_valid
wire [33:0] sdram_s1_agent_rdata_fifo_out_data; // sdram_s1_agent_rdata_fifo:out_data -> sdram_s1_agent:rdata_fifo_sink_data
wire sdram_s1_agent_rdata_fifo_out_ready; // sdram_s1_agent:rdata_fifo_sink_ready -> sdram_s1_agent_rdata_fifo:out_ready
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> sdram_s1_agent:cp_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> sdram_s1_agent:cp_valid
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> sdram_s1_agent:cp_startofpacket
wire [104:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> sdram_s1_agent:cp_data
wire [5:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> sdram_s1_agent:cp_channel
wire cmd_mux_005_src_ready; // sdram_s1_agent:cp_ready -> cmd_mux_005:src_ready
wire cpu_data_master_agent_cp_endofpacket; // cpu_data_master_agent:cp_endofpacket -> router:sink_endofpacket
wire cpu_data_master_agent_cp_valid; // cpu_data_master_agent:cp_valid -> router:sink_valid
wire cpu_data_master_agent_cp_startofpacket; // cpu_data_master_agent:cp_startofpacket -> router:sink_startofpacket
wire [104:0] cpu_data_master_agent_cp_data; // cpu_data_master_agent:cp_data -> router:sink_data
wire cpu_data_master_agent_cp_ready; // router:sink_ready -> cpu_data_master_agent:cp_ready
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire [104:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire [5:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire cpu_instruction_master_agent_cp_endofpacket; // cpu_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire cpu_instruction_master_agent_cp_valid; // cpu_instruction_master_agent:cp_valid -> router_001:sink_valid
wire cpu_instruction_master_agent_cp_startofpacket; // cpu_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire [104:0] cpu_instruction_master_agent_cp_data; // cpu_instruction_master_agent:cp_data -> router_001:sink_data
wire cpu_instruction_master_agent_cp_ready; // router_001:sink_ready -> cpu_instruction_master_agent:cp_ready
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire [104:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire [5:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire jtag_uart_avalon_jtag_slave_agent_rp_endofpacket; // jtag_uart_avalon_jtag_slave_agent:rp_endofpacket -> router_002:sink_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rp_valid; // jtag_uart_avalon_jtag_slave_agent:rp_valid -> router_002:sink_valid
wire jtag_uart_avalon_jtag_slave_agent_rp_startofpacket; // jtag_uart_avalon_jtag_slave_agent:rp_startofpacket -> router_002:sink_startofpacket
wire [104:0] jtag_uart_avalon_jtag_slave_agent_rp_data; // jtag_uart_avalon_jtag_slave_agent:rp_data -> router_002:sink_data
wire jtag_uart_avalon_jtag_slave_agent_rp_ready; // router_002:sink_ready -> jtag_uart_avalon_jtag_slave_agent:rp_ready
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire [104:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire [5:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire cpu_jtag_debug_module_agent_rp_endofpacket; // cpu_jtag_debug_module_agent:rp_endofpacket -> router_003:sink_endofpacket
wire cpu_jtag_debug_module_agent_rp_valid; // cpu_jtag_debug_module_agent:rp_valid -> router_003:sink_valid
wire cpu_jtag_debug_module_agent_rp_startofpacket; // cpu_jtag_debug_module_agent:rp_startofpacket -> router_003:sink_startofpacket
wire [104:0] cpu_jtag_debug_module_agent_rp_data; // cpu_jtag_debug_module_agent:rp_data -> router_003:sink_data
wire cpu_jtag_debug_module_agent_rp_ready; // router_003:sink_ready -> cpu_jtag_debug_module_agent:rp_ready
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire [104:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire [5:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire clocks_pll_slave_agent_rp_endofpacket; // clocks_pll_slave_agent:rp_endofpacket -> router_004:sink_endofpacket
wire clocks_pll_slave_agent_rp_valid; // clocks_pll_slave_agent:rp_valid -> router_004:sink_valid
wire clocks_pll_slave_agent_rp_startofpacket; // clocks_pll_slave_agent:rp_startofpacket -> router_004:sink_startofpacket
wire [104:0] clocks_pll_slave_agent_rp_data; // clocks_pll_slave_agent:rp_data -> router_004:sink_data
wire clocks_pll_slave_agent_rp_ready; // router_004:sink_ready -> clocks_pll_slave_agent:rp_ready
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire [104:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire [5:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire clock_crossing_io_s0_agent_rp_endofpacket; // clock_crossing_io_s0_agent:rp_endofpacket -> router_005:sink_endofpacket
wire clock_crossing_io_s0_agent_rp_valid; // clock_crossing_io_s0_agent:rp_valid -> router_005:sink_valid
wire clock_crossing_io_s0_agent_rp_startofpacket; // clock_crossing_io_s0_agent:rp_startofpacket -> router_005:sink_startofpacket
wire [104:0] clock_crossing_io_s0_agent_rp_data; // clock_crossing_io_s0_agent:rp_data -> router_005:sink_data
wire clock_crossing_io_s0_agent_rp_ready; // router_005:sink_ready -> clock_crossing_io_s0_agent:rp_ready
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_003:sink_valid
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire [104:0] router_005_src_data; // router_005:src_data -> rsp_demux_003:sink_data
wire [5:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel
wire router_005_src_ready; // rsp_demux_003:sink_ready -> router_005:src_ready
wire keycode_s1_agent_rp_endofpacket; // keycode_s1_agent:rp_endofpacket -> router_006:sink_endofpacket
wire keycode_s1_agent_rp_valid; // keycode_s1_agent:rp_valid -> router_006:sink_valid
wire keycode_s1_agent_rp_startofpacket; // keycode_s1_agent:rp_startofpacket -> router_006:sink_startofpacket
wire [104:0] keycode_s1_agent_rp_data; // keycode_s1_agent:rp_data -> router_006:sink_data
wire keycode_s1_agent_rp_ready; // router_006:sink_ready -> keycode_s1_agent:rp_ready
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_004:sink_valid
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire [104:0] router_006_src_data; // router_006:src_data -> rsp_demux_004:sink_data
wire [5:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_004:sink_channel
wire router_006_src_ready; // rsp_demux_004:sink_ready -> router_006:src_ready
wire sdram_s1_agent_rp_endofpacket; // sdram_s1_agent:rp_endofpacket -> router_007:sink_endofpacket
wire sdram_s1_agent_rp_valid; // sdram_s1_agent:rp_valid -> router_007:sink_valid
wire sdram_s1_agent_rp_startofpacket; // sdram_s1_agent:rp_startofpacket -> router_007:sink_startofpacket
wire [104:0] sdram_s1_agent_rp_data; // sdram_s1_agent:rp_data -> router_007:sink_data
wire sdram_s1_agent_rp_ready; // router_007:sink_ready -> sdram_s1_agent:rp_ready
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_005:sink_valid
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire [104:0] router_007_src_data; // router_007:src_data -> rsp_demux_005:sink_data
wire [5:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_005:sink_channel
wire router_007_src_ready; // rsp_demux_005:sink_ready -> router_007:src_ready
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire [104:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire [5:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire [104:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire [5:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire [104:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire [5:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire [104:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire [5:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire [104:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire [5:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux_001:sink1_valid
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux_001:sink1_startofpacket
wire [104:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux_001:sink1_data
wire [5:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src0_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src0_ready
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_002:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_002:sink1_valid
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_002:sink1_startofpacket
wire [104:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_002:sink1_data
wire [5:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_001_src1_ready; // cmd_mux_002:sink1_ready -> cmd_demux_001:src1_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire [104:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire [5:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire [104:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire [5:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink0_valid
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire [104:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink0_data
wire [5:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux_001:src1_ready
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire [104:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire [5:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_001:sink1_valid
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire [104:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_001:sink1_data
wire [5:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_002_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_002:src1_ready
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire [104:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire [5:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire [104:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire [5:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> crosser:in_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> crosser:in_valid
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> crosser:in_startofpacket
wire [104:0] cmd_demux_src5_data; // cmd_demux:src5_data -> crosser:in_data
wire [5:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> crosser:in_channel
wire cmd_demux_src5_ready; // crosser:in_ready -> cmd_demux:src5_ready
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux_005:sink0_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux_005:sink0_valid
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux_005:sink0_startofpacket
wire [104:0] crosser_out_data; // crosser:out_data -> cmd_mux_005:sink0_data
wire [5:0] crosser_out_channel; // crosser:out_channel -> cmd_mux_005:sink0_channel
wire crosser_out_ready; // cmd_mux_005:sink0_ready -> crosser:out_ready
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> crosser_001:in_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> crosser_001:in_valid
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> crosser_001:in_startofpacket
wire [104:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> crosser_001:in_data
wire [5:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> crosser_001:in_channel
wire cmd_demux_001_src2_ready; // crosser_001:in_ready -> cmd_demux_001:src2_ready
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> cmd_mux_005:sink1_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> cmd_mux_005:sink1_valid
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> cmd_mux_005:sink1_startofpacket
wire [104:0] crosser_001_out_data; // crosser_001:out_data -> cmd_mux_005:sink1_data
wire [5:0] crosser_001_out_channel; // crosser_001:out_channel -> cmd_mux_005:sink1_channel
wire crosser_001_out_ready; // cmd_mux_005:sink1_ready -> crosser_001:out_ready
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> crosser_002:in_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> crosser_002:in_valid
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> crosser_002:in_startofpacket
wire [104:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> crosser_002:in_data
wire [5:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> crosser_002:in_channel
wire rsp_demux_005_src0_ready; // crosser_002:in_ready -> rsp_demux_005:src0_ready
wire crosser_002_out_endofpacket; // crosser_002:out_endofpacket -> rsp_mux:sink5_endofpacket
wire crosser_002_out_valid; // crosser_002:out_valid -> rsp_mux:sink5_valid
wire crosser_002_out_startofpacket; // crosser_002:out_startofpacket -> rsp_mux:sink5_startofpacket
wire [104:0] crosser_002_out_data; // crosser_002:out_data -> rsp_mux:sink5_data
wire [5:0] crosser_002_out_channel; // crosser_002:out_channel -> rsp_mux:sink5_channel
wire crosser_002_out_ready; // rsp_mux:sink5_ready -> crosser_002:out_ready
wire rsp_demux_005_src1_endofpacket; // rsp_demux_005:src1_endofpacket -> crosser_003:in_endofpacket
wire rsp_demux_005_src1_valid; // rsp_demux_005:src1_valid -> crosser_003:in_valid
wire rsp_demux_005_src1_startofpacket; // rsp_demux_005:src1_startofpacket -> crosser_003:in_startofpacket
wire [104:0] rsp_demux_005_src1_data; // rsp_demux_005:src1_data -> crosser_003:in_data
wire [5:0] rsp_demux_005_src1_channel; // rsp_demux_005:src1_channel -> crosser_003:in_channel
wire rsp_demux_005_src1_ready; // crosser_003:in_ready -> rsp_demux_005:src1_ready
wire crosser_003_out_endofpacket; // crosser_003:out_endofpacket -> rsp_mux_001:sink2_endofpacket
wire crosser_003_out_valid; // crosser_003:out_valid -> rsp_mux_001:sink2_valid
wire crosser_003_out_startofpacket; // crosser_003:out_startofpacket -> rsp_mux_001:sink2_startofpacket
wire [104:0] crosser_003_out_data; // crosser_003:out_data -> rsp_mux_001:sink2_data
wire [5:0] crosser_003_out_channel; // crosser_003:out_channel -> rsp_mux_001:sink2_channel
wire crosser_003_out_ready; // rsp_mux_001:sink2_ready -> crosser_003:out_ready
altera_merlin_master_translator #(
.AV_ADDRESS_W (29),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) cpu_data_master_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.av_byteenable (cpu_data_master_byteenable), // .byteenable
.av_read (cpu_data_master_read), // .read
.av_readdata (cpu_data_master_readdata), // .readdata
.av_write (cpu_data_master_write), // .write
.av_writedata (cpu_data_master_writedata), // .writedata
.av_debugaccess (cpu_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (29),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) cpu_instruction_master_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.av_read (cpu_instruction_master_read), // .read
.av_readdata (cpu_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_avalon_jtag_slave_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (jtag_uart_avalon_jtag_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_avalon_jtag_slave_agent_m0_read), // .read
.uav_write (jtag_uart_avalon_jtag_slave_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_avalon_jtag_slave_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_avalon_jtag_slave_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_avalon_jtag_slave_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_avalon_jtag_slave_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_avalon_jtag_slave_write), // .write
.av_read (jtag_uart_avalon_jtag_slave_read), // .read
.av_readdata (jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_writedata (jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) cpu_jtag_debug_module_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_jtag_debug_module_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (cpu_jtag_debug_module_agent_m0_burstcount), // .burstcount
.uav_read (cpu_jtag_debug_module_agent_m0_read), // .read
.uav_write (cpu_jtag_debug_module_agent_m0_write), // .write
.uav_waitrequest (cpu_jtag_debug_module_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_jtag_debug_module_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_jtag_debug_module_agent_m0_byteenable), // .byteenable
.uav_readdata (cpu_jtag_debug_module_agent_m0_readdata), // .readdata
.uav_writedata (cpu_jtag_debug_module_agent_m0_writedata), // .writedata
.uav_lock (cpu_jtag_debug_module_agent_m0_lock), // .lock
.uav_debugaccess (cpu_jtag_debug_module_agent_m0_debugaccess), // .debugaccess
.av_address (cpu_jtag_debug_module_address), // avalon_anti_slave_0.address
.av_write (cpu_jtag_debug_module_write), // .write
.av_read (cpu_jtag_debug_module_read), // .read
.av_readdata (cpu_jtag_debug_module_readdata), // .readdata
.av_writedata (cpu_jtag_debug_module_writedata), // .writedata
.av_byteenable (cpu_jtag_debug_module_byteenable), // .byteenable
.av_waitrequest (cpu_jtag_debug_module_waitrequest), // .waitrequest
.av_debugaccess (cpu_jtag_debug_module_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) clocks_pll_slave_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (clocks_pll_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (clocks_pll_slave_agent_m0_burstcount), // .burstcount
.uav_read (clocks_pll_slave_agent_m0_read), // .read
.uav_write (clocks_pll_slave_agent_m0_write), // .write
.uav_waitrequest (clocks_pll_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (clocks_pll_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (clocks_pll_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (clocks_pll_slave_agent_m0_readdata), // .readdata
.uav_writedata (clocks_pll_slave_agent_m0_writedata), // .writedata
.uav_lock (clocks_pll_slave_agent_m0_lock), // .lock
.uav_debugaccess (clocks_pll_slave_agent_m0_debugaccess), // .debugaccess
.av_address (clocks_pll_slave_address), // avalon_anti_slave_0.address
.av_write (clocks_pll_slave_write), // .write
.av_read (clocks_pll_slave_read), // .read
.av_readdata (clocks_pll_slave_readdata), // .readdata
.av_writedata (clocks_pll_slave_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (22),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) clock_crossing_io_s0_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (clock_crossing_io_s0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (clock_crossing_io_s0_agent_m0_burstcount), // .burstcount
.uav_read (clock_crossing_io_s0_agent_m0_read), // .read
.uav_write (clock_crossing_io_s0_agent_m0_write), // .write
.uav_waitrequest (clock_crossing_io_s0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (clock_crossing_io_s0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (clock_crossing_io_s0_agent_m0_byteenable), // .byteenable
.uav_readdata (clock_crossing_io_s0_agent_m0_readdata), // .readdata
.uav_writedata (clock_crossing_io_s0_agent_m0_writedata), // .writedata
.uav_lock (clock_crossing_io_s0_agent_m0_lock), // .lock
.uav_debugaccess (clock_crossing_io_s0_agent_m0_debugaccess), // .debugaccess
.av_address (clock_crossing_io_s0_address), // avalon_anti_slave_0.address
.av_write (clock_crossing_io_s0_write), // .write
.av_read (clock_crossing_io_s0_read), // .read
.av_readdata (clock_crossing_io_s0_readdata), // .readdata
.av_writedata (clock_crossing_io_s0_writedata), // .writedata
.av_burstcount (clock_crossing_io_s0_burstcount), // .burstcount
.av_byteenable (clock_crossing_io_s0_byteenable), // .byteenable
.av_readdatavalid (clock_crossing_io_s0_readdatavalid), // .readdatavalid
.av_waitrequest (clock_crossing_io_s0_waitrequest), // .waitrequest
.av_debugaccess (clock_crossing_io_s0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) keycode_s1_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (keycode_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (keycode_s1_agent_m0_burstcount), // .burstcount
.uav_read (keycode_s1_agent_m0_read), // .read
.uav_write (keycode_s1_agent_m0_write), // .write
.uav_waitrequest (keycode_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (keycode_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (keycode_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (keycode_s1_agent_m0_readdata), // .readdata
.uav_writedata (keycode_s1_agent_m0_writedata), // .writedata
.uav_lock (keycode_s1_agent_m0_lock), // .lock
.uav_debugaccess (keycode_s1_agent_m0_debugaccess), // .debugaccess
.av_address (keycode_s1_address), // avalon_anti_slave_0.address
.av_write (keycode_s1_write), // .write
.av_readdata (keycode_s1_readdata), // .readdata
.av_writedata (keycode_s1_writedata), // .writedata
.av_chipselect (keycode_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sdram_s1_translator (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sdram_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sdram_s1_agent_m0_burstcount), // .burstcount
.uav_read (sdram_s1_agent_m0_read), // .read
.uav_write (sdram_s1_agent_m0_write), // .write
.uav_waitrequest (sdram_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sdram_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sdram_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sdram_s1_agent_m0_readdata), // .readdata
.uav_writedata (sdram_s1_agent_m0_writedata), // .writedata
.uav_lock (sdram_s1_agent_m0_lock), // .lock
.uav_debugaccess (sdram_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sdram_s1_address), // avalon_anti_slave_0.address
.av_write (sdram_s1_write), // .write
.av_read (sdram_s1_read), // .read
.av_readdata (sdram_s1_readdata), // .readdata
.av_writedata (sdram_s1_writedata), // .writedata
.av_byteenable (sdram_s1_byteenable), // .byteenable
.av_readdatavalid (sdram_s1_readdatavalid), // .readdatavalid
.av_waitrequest (sdram_s1_waitrequest), // .waitrequest
.av_chipselect (sdram_s1_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BEGIN_BURST (84),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_TRANS_EXCLUSIVE (70),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_THREAD_ID_H (92),
.PKT_THREAD_ID_L (92),
.PKT_CACHE_H (99),
.PKT_CACHE_L (96),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.PKT_QOS_H (85),
.PKT_QOS_L (85),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_DATA_W (105),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_data_master_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (cpu_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_data_master_agent_cp_valid), // cp.valid
.cp_data (cpu_data_master_agent_cp_data), // .data
.cp_startofpacket (cpu_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_data_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BEGIN_BURST (84),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_TRANS_EXCLUSIVE (70),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_THREAD_ID_H (92),
.PKT_THREAD_ID_L (92),
.PKT_CACHE_H (99),
.PKT_CACHE_L (96),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.PKT_QOS_H (85),
.PKT_QOS_L (85),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_DATA_W (105),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_instruction_master_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_instruction_master_agent_cp_valid), // cp.valid
.cp_data (cpu_instruction_master_agent_cp_data), // .data
.cp_startofpacket (cpu_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_instruction_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) jtag_uart_avalon_jtag_slave_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (jtag_uart_avalon_jtag_slave_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_avalon_jtag_slave_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_avalon_jtag_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_avalon_jtag_slave_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_avalon_jtag_slave_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_avalon_jtag_slave_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_avalon_jtag_slave_agent_rp_ready), // .ready
.rp_valid (jtag_uart_avalon_jtag_slave_agent_rp_valid), // .valid
.rp_data (jtag_uart_avalon_jtag_slave_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_avalon_jtag_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_avalon_jtag_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_avalon_jtag_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_avalon_jtag_slave_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_uart_avalon_jtag_slave_agent_rf_source_data), // in.data
.in_valid (jtag_uart_avalon_jtag_slave_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_avalon_jtag_slave_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_jtag_debug_module_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (cpu_jtag_debug_module_agent_m0_address), // m0.address
.m0_burstcount (cpu_jtag_debug_module_agent_m0_burstcount), // .burstcount
.m0_byteenable (cpu_jtag_debug_module_agent_m0_byteenable), // .byteenable
.m0_debugaccess (cpu_jtag_debug_module_agent_m0_debugaccess), // .debugaccess
.m0_lock (cpu_jtag_debug_module_agent_m0_lock), // .lock
.m0_readdata (cpu_jtag_debug_module_agent_m0_readdata), // .readdata
.m0_readdatavalid (cpu_jtag_debug_module_agent_m0_readdatavalid), // .readdatavalid
.m0_read (cpu_jtag_debug_module_agent_m0_read), // .read
.m0_waitrequest (cpu_jtag_debug_module_agent_m0_waitrequest), // .waitrequest
.m0_writedata (cpu_jtag_debug_module_agent_m0_writedata), // .writedata
.m0_write (cpu_jtag_debug_module_agent_m0_write), // .write
.rp_endofpacket (cpu_jtag_debug_module_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (cpu_jtag_debug_module_agent_rp_ready), // .ready
.rp_valid (cpu_jtag_debug_module_agent_rp_valid), // .valid
.rp_data (cpu_jtag_debug_module_agent_rp_data), // .data
.rp_startofpacket (cpu_jtag_debug_module_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (cpu_jtag_debug_module_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (cpu_jtag_debug_module_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (cpu_jtag_debug_module_agent_rsp_fifo_out_data), // .data
.rf_source_ready (cpu_jtag_debug_module_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (cpu_jtag_debug_module_agent_rf_source_valid), // .valid
.rf_source_startofpacket (cpu_jtag_debug_module_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (cpu_jtag_debug_module_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (cpu_jtag_debug_module_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (cpu_jtag_debug_module_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (cpu_jtag_debug_module_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (cpu_jtag_debug_module_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (cpu_jtag_debug_module_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (cpu_jtag_debug_module_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (cpu_jtag_debug_module_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) cpu_jtag_debug_module_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (cpu_jtag_debug_module_agent_rf_source_data), // in.data
.in_valid (cpu_jtag_debug_module_agent_rf_source_valid), // .valid
.in_ready (cpu_jtag_debug_module_agent_rf_source_ready), // .ready
.in_startofpacket (cpu_jtag_debug_module_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (cpu_jtag_debug_module_agent_rf_source_endofpacket), // .endofpacket
.out_data (cpu_jtag_debug_module_agent_rsp_fifo_out_data), // out.data
.out_valid (cpu_jtag_debug_module_agent_rsp_fifo_out_valid), // .valid
.out_ready (cpu_jtag_debug_module_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) clocks_pll_slave_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (clocks_pll_slave_agent_m0_address), // m0.address
.m0_burstcount (clocks_pll_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (clocks_pll_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (clocks_pll_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (clocks_pll_slave_agent_m0_lock), // .lock
.m0_readdata (clocks_pll_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (clocks_pll_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (clocks_pll_slave_agent_m0_read), // .read
.m0_waitrequest (clocks_pll_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (clocks_pll_slave_agent_m0_writedata), // .writedata
.m0_write (clocks_pll_slave_agent_m0_write), // .write
.rp_endofpacket (clocks_pll_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (clocks_pll_slave_agent_rp_ready), // .ready
.rp_valid (clocks_pll_slave_agent_rp_valid), // .valid
.rp_data (clocks_pll_slave_agent_rp_data), // .data
.rp_startofpacket (clocks_pll_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (clocks_pll_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (clocks_pll_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (clocks_pll_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (clocks_pll_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (clocks_pll_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (clocks_pll_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (clocks_pll_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (clocks_pll_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (clocks_pll_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (clocks_pll_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (clocks_pll_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (clocks_pll_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (clocks_pll_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (clocks_pll_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (clocks_pll_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (clocks_pll_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) clocks_pll_slave_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (clocks_pll_slave_agent_rf_source_data), // in.data
.in_valid (clocks_pll_slave_agent_rf_source_valid), // .valid
.in_ready (clocks_pll_slave_agent_rf_source_ready), // .ready
.in_startofpacket (clocks_pll_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (clocks_pll_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (clocks_pll_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (clocks_pll_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (clocks_pll_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (clocks_pll_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (clocks_pll_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) clock_crossing_io_s0_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (clock_crossing_io_s0_agent_m0_address), // m0.address
.m0_burstcount (clock_crossing_io_s0_agent_m0_burstcount), // .burstcount
.m0_byteenable (clock_crossing_io_s0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (clock_crossing_io_s0_agent_m0_debugaccess), // .debugaccess
.m0_lock (clock_crossing_io_s0_agent_m0_lock), // .lock
.m0_readdata (clock_crossing_io_s0_agent_m0_readdata), // .readdata
.m0_readdatavalid (clock_crossing_io_s0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (clock_crossing_io_s0_agent_m0_read), // .read
.m0_waitrequest (clock_crossing_io_s0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (clock_crossing_io_s0_agent_m0_writedata), // .writedata
.m0_write (clock_crossing_io_s0_agent_m0_write), // .write
.rp_endofpacket (clock_crossing_io_s0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (clock_crossing_io_s0_agent_rp_ready), // .ready
.rp_valid (clock_crossing_io_s0_agent_rp_valid), // .valid
.rp_data (clock_crossing_io_s0_agent_rp_data), // .data
.rp_startofpacket (clock_crossing_io_s0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (clock_crossing_io_s0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (clock_crossing_io_s0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (clock_crossing_io_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (clock_crossing_io_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (clock_crossing_io_s0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (clock_crossing_io_s0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (clock_crossing_io_s0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (clock_crossing_io_s0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (clock_crossing_io_s0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (clock_crossing_io_s0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (clock_crossing_io_s0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (clock_crossing_io_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (clock_crossing_io_s0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (clock_crossing_io_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (clock_crossing_io_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (clock_crossing_io_s0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (129),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) clock_crossing_io_s0_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (clock_crossing_io_s0_agent_rf_source_data), // in.data
.in_valid (clock_crossing_io_s0_agent_rf_source_valid), // .valid
.in_ready (clock_crossing_io_s0_agent_rf_source_ready), // .ready
.in_startofpacket (clock_crossing_io_s0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (clock_crossing_io_s0_agent_rf_source_endofpacket), // .endofpacket
.out_data (clock_crossing_io_s0_agent_rsp_fifo_out_data), // out.data
.out_valid (clock_crossing_io_s0_agent_rsp_fifo_out_valid), // .valid
.out_ready (clock_crossing_io_s0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (clock_crossing_io_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (clock_crossing_io_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) keycode_s1_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (keycode_s1_agent_m0_address), // m0.address
.m0_burstcount (keycode_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (keycode_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (keycode_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (keycode_s1_agent_m0_lock), // .lock
.m0_readdata (keycode_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (keycode_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (keycode_s1_agent_m0_read), // .read
.m0_waitrequest (keycode_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (keycode_s1_agent_m0_writedata), // .writedata
.m0_write (keycode_s1_agent_m0_write), // .write
.rp_endofpacket (keycode_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (keycode_s1_agent_rp_ready), // .ready
.rp_valid (keycode_s1_agent_rp_valid), // .valid
.rp_data (keycode_s1_agent_rp_data), // .data
.rp_startofpacket (keycode_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (keycode_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (keycode_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (keycode_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (keycode_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (keycode_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (keycode_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (keycode_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (keycode_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (keycode_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (keycode_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (keycode_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (keycode_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (keycode_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (keycode_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (keycode_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (keycode_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) keycode_s1_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (keycode_s1_agent_rf_source_data), // in.data
.in_valid (keycode_s1_agent_rf_source_valid), // .valid
.in_ready (keycode_s1_agent_rf_source_ready), // .ready
.in_startofpacket (keycode_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (keycode_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (keycode_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (keycode_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (keycode_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (keycode_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (keycode_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sdram_s1_agent (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sdram_s1_agent_m0_address), // m0.address
.m0_burstcount (sdram_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sdram_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sdram_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sdram_s1_agent_m0_lock), // .lock
.m0_readdata (sdram_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sdram_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sdram_s1_agent_m0_read), // .read
.m0_waitrequest (sdram_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sdram_s1_agent_m0_writedata), // .writedata
.m0_write (sdram_s1_agent_m0_write), // .write
.rp_endofpacket (sdram_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sdram_s1_agent_rp_ready), // .ready
.rp_valid (sdram_s1_agent_rp_valid), // .valid
.rp_data (sdram_s1_agent_rp_data), // .data
.rp_startofpacket (sdram_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (sdram_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sdram_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sdram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sdram_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sdram_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sdram_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sdram_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sdram_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sdram_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sdram_s1_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sdram_s1_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (sdram_s1_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (sdram_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sdram_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sdram_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_s1_agent_rsp_fifo (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_s1_agent_rf_source_data), // in.data
.in_valid (sdram_s1_agent_rf_source_valid), // .valid
.in_ready (sdram_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sdram_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sdram_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sdram_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sdram_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sdram_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sdram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_s1_agent_rdata_fifo (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (sdram_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (sdram_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (sdram_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (sdram_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (sdram_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
usb_system_mm_interconnect_0_router router (
.sink_ready (cpu_data_master_agent_cp_ready), // sink.ready
.sink_valid (cpu_data_master_agent_cp_valid), // .valid
.sink_data (cpu_data_master_agent_cp_data), // .data
.sink_startofpacket (cpu_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_data_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_001 router_001 (
.sink_ready (cpu_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (cpu_instruction_master_agent_cp_valid), // .valid
.sink_data (cpu_instruction_master_agent_cp_data), // .data
.sink_startofpacket (cpu_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_002 router_002 (
.sink_ready (jtag_uart_avalon_jtag_slave_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_avalon_jtag_slave_agent_rp_valid), // .valid
.sink_data (jtag_uart_avalon_jtag_slave_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_003 router_003 (
.sink_ready (cpu_jtag_debug_module_agent_rp_ready), // sink.ready
.sink_valid (cpu_jtag_debug_module_agent_rp_valid), // .valid
.sink_data (cpu_jtag_debug_module_agent_rp_data), // .data
.sink_startofpacket (cpu_jtag_debug_module_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_jtag_debug_module_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_003 router_004 (
.sink_ready (clocks_pll_slave_agent_rp_ready), // sink.ready
.sink_valid (clocks_pll_slave_agent_rp_valid), // .valid
.sink_data (clocks_pll_slave_agent_rp_data), // .data
.sink_startofpacket (clocks_pll_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (clocks_pll_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_002 router_005 (
.sink_ready (clock_crossing_io_s0_agent_rp_ready), // sink.ready
.sink_valid (clock_crossing_io_s0_agent_rp_valid), // .valid
.sink_data (clock_crossing_io_s0_agent_rp_data), // .data
.sink_startofpacket (clock_crossing_io_s0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (clock_crossing_io_s0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_002 router_006 (
.sink_ready (keycode_s1_agent_rp_ready), // sink.ready
.sink_valid (keycode_s1_agent_rp_valid), // .valid
.sink_data (keycode_s1_agent_rp_data), // .data
.sink_startofpacket (keycode_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (keycode_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_003 router_007 (
.sink_ready (sdram_s1_agent_rp_ready), // sink.ready
.sink_valid (sdram_s1_agent_rp_valid), // .valid
.sink_data (sdram_s1_agent_rp_data), // .data
.sink_startofpacket (sdram_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sdram_s1_agent_rp_endofpacket), // .endofpacket
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_demux cmd_demux (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_mux cmd_mux (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_mux_001 cmd_mux_002 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_mux cmd_mux_003 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_mux cmd_mux_004 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_mux_001 cmd_mux_005 (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket), // .endofpacket
.sink1_ready (crosser_001_out_ready), // sink1.ready
.sink1_valid (crosser_001_out_valid), // .valid
.sink1_channel (crosser_001_out_channel), // .channel
.sink1_data (crosser_001_out_data), // .data
.sink1_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_001_out_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_demux rsp_demux (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_demux_001 rsp_demux_001 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_demux_001 rsp_demux_002 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_demux rsp_demux_003 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_demux rsp_demux_004 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_demux_001 rsp_demux_005 (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_005_src1_ready), // src1.ready
.src1_valid (rsp_demux_005_src1_valid), // .valid
.src1_data (rsp_demux_005_src1_data), // .data
.src1_channel (rsp_demux_005_src1_channel), // .channel
.src1_startofpacket (rsp_demux_005_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_005_src1_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_mux rsp_mux (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (crosser_002_out_ready), // sink5.ready
.sink5_valid (crosser_002_out_valid), // .valid
.sink5_channel (crosser_002_out_channel), // .channel
.sink5_data (crosser_002_out_data), // .data
.sink5_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.sink5_endofpacket (crosser_002_out_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_001_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_001_src1_valid), // .valid
.sink0_channel (rsp_demux_001_src1_channel), // .channel
.sink0_data (rsp_demux_001_src1_data), // .data
.sink0_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_002_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_002_src1_valid), // .valid
.sink1_channel (rsp_demux_002_src1_channel), // .channel
.sink1_data (rsp_demux_002_src1_data), // .data
.sink1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_002_src1_endofpacket), // .endofpacket
.sink2_ready (crosser_003_out_ready), // sink2.ready
.sink2_valid (crosser_003_out_valid), // .valid
.sink2_channel (crosser_003_out_channel), // .channel
.sink2_data (crosser_003_out_data), // .data
.sink2_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.sink2_endofpacket (crosser_003_out_endofpacket) // .endofpacket
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (105),
.BITS_PER_SYMBOL (105),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (clk_clk_clk), // in_clk.clk
.in_reset (cpu_reset_n_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clocks_c0_clk), // out_clk.clk
.out_reset (sdram_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src5_ready), // in.ready
.in_valid (cmd_demux_src5_valid), // .valid
.in_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.in_channel (cmd_demux_src5_channel), // .channel
.in_data (cmd_demux_src5_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (105),
.BITS_PER_SYMBOL (105),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (clk_clk_clk), // in_clk.clk
.in_reset (cpu_reset_n_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clocks_c0_clk), // out_clk.clk
.out_reset (sdram_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_001_src2_ready), // in.ready
.in_valid (cmd_demux_001_src2_valid), // .valid
.in_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_001_src2_endofpacket), // .endofpacket
.in_channel (cmd_demux_001_src2_channel), // .channel
.in_data (cmd_demux_001_src2_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (105),
.BITS_PER_SYMBOL (105),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_002 (
.in_clk (clocks_c0_clk), // in_clk.clk
.in_reset (sdram_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_clk_clk), // out_clk.clk
.out_reset (cpu_reset_n_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_005_src0_ready), // in.ready
.in_valid (rsp_demux_005_src0_valid), // .valid
.in_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_005_src0_channel), // .channel
.in_data (rsp_demux_005_src0_data), // .data
.out_ready (crosser_002_out_ready), // out.ready
.out_valid (crosser_002_out_valid), // .valid
.out_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.out_channel (crosser_002_out_channel), // .channel
.out_data (crosser_002_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (105),
.BITS_PER_SYMBOL (105),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_003 (
.in_clk (clocks_c0_clk), // in_clk.clk
.in_reset (sdram_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_clk_clk), // out_clk.clk
.out_reset (cpu_reset_n_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_005_src1_ready), // in.ready
.in_valid (rsp_demux_005_src1_valid), // .valid
.in_startofpacket (rsp_demux_005_src1_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_005_src1_endofpacket), // .endofpacket
.in_channel (rsp_demux_005_src1_channel), // .channel
.in_data (rsp_demux_005_src1_data), // .data
.out_ready (crosser_003_out_ready), // out.ready
.out_valid (crosser_003_out_valid), // .valid
.out_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.out_channel (crosser_003_out_channel), // .channel
.out_data (crosser_003_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_tagdp_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// Description:
// This module contains the control required for detecting
// a parity error in a tag read.
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
`include "iop.h"
`include "sctag.h"
module sctag_tagdp_ctl( /*AUTOARG*/
// Outputs
triad0_muxsel_c3, triad1_muxsel_c3, triad2_muxsel_c3,
triad3_muxsel_c3, tag_quad_muxsel_c3, bist_vuad_wr_data,
bist_vuad_index, bist_vuad_vd, bist_vuad_write,
vuad_dp_diag_data_c7_buf, tagdp_mbctl_par_err_c3,
tagdp_tagctl_par_err_c3, tagdp_arbctl_par_err_c3, tag_error_c8,
so, lru_way_sel_c3, evict_c3, invalid_evict_c3,
// Inputs
vuad_dp_valid_c2, tag_parity_c2, tag_way_sel_c2,
vuad_tagdp_sel_c2_d1, bist_way_px, bist_enable_px,
arbdp_diag_wr_way_c2, arbctl_tecc_way_c2, arbctl_normal_tagacc_c2,
arbctl_tagdp_tecc_c2, arbctl_tagdp_perr_vld_c2, mbctl_hit_c3,
l2_dir_map_on, arbctl_l2tag_vld_c4, rst_tri_en, mbist_write_data,
mbist_l2v_index, mbist_l2v_vd, mbist_l2v_write,
vuad_dp_diag_data_c7, rclk, si, se, grst_l, arst_l, dbginit_l,
vuad_dp_used_c2, vuad_dp_alloc_c2, arbctl_evict_vld_c2
);
input [11:0] vuad_dp_valid_c2;
input [11:0] tag_parity_c2; // from tagdp.needs to be mapped
// @ the top level.
input [11:0] tag_way_sel_c2; // This can be a delayed version of the way selects.POST_3.0
input vuad_tagdp_sel_c2_d1; //POST_3.0
// Adding all the mux control logic for tagdp and tagl_dp into
// this block.
// All bist inputs come from a PX2 flop in the bist controller.
input [3:0] bist_way_px; // from tagbist
input bist_enable_px; // from tagbist
// calculations.
output [2:0] triad0_muxsel_c3;
output [2:0] triad1_muxsel_c3;
output [2:0] triad2_muxsel_c3;
output [2:0] triad3_muxsel_c3;
output [3:0] tag_quad_muxsel_c3 ; // to tagdp
input [3:0] arbdp_diag_wr_way_c2 ; // Wr or read way for tag Diagnostic Accesses.
input [3:0] arbctl_tecc_way_c2;
input arbctl_normal_tagacc_c2 ; // indicates that lru way from vuad is used for
// tag selection
input arbctl_tagdp_tecc_c2; // NEW_PIN . sel tecc way
input arbctl_tagdp_perr_vld_c2; // POST_2.0 PIN
input mbctl_hit_c3; // POST_2.0 PIN
input l2_dir_map_on; // NEW_PIN from csr
input arbctl_l2tag_vld_c4; // from tagctl
input rst_tri_en;
input [7:0] mbist_write_data; // POST_4.2 signals
output [7:0] bist_vuad_wr_data ; // POST_4.2 signals.
input [9:0] mbist_l2v_index; // POST_4.2 signals
input mbist_l2v_vd; // POST_4.2 signals
input mbist_l2v_write; // POST_4.2 signals
output [9:0] bist_vuad_index; // POST_4.2 signals
output bist_vuad_vd; // POST_4.2 signals
output bist_vuad_write; // POST_4.2 signals
input [25:0] vuad_dp_diag_data_c7 ; // POST_4.2 signals
output [25:0] vuad_dp_diag_data_c7_buf; // POST_4.2 signals
input rclk;
input si, se;
input grst_l;
input arst_l;
input dbginit_l;
output tagdp_mbctl_par_err_c3 ; // can be made a C3 signal.
output tagdp_tagctl_par_err_c3; // used to gate off eviction way
output tagdp_arbctl_par_err_c3; // used to gate off an eviction signal
output tag_error_c8; // to fbctl and csr.
output so;
input [11:0] vuad_dp_used_c2 ;
input [11:0] vuad_dp_alloc_c2 ;
output [11:0] lru_way_sel_c3;
// to tagdp
// All outputs are xmitted in C2 and used in C3.
// Buffer the following so that they can transmit to tagdp.
input arbctl_evict_vld_c2;
output evict_c3;
output invalid_evict_c3;
wire par_err_c2, par_err_c3;
wire tagdp_par_err_c4, tagdp_par_err_c5;
wire tag_error_c6, tag_error_c7 ;
wire [2:0] lru_triad0_muxsel_c2 ;
wire [2:0] lru_triad1_muxsel_c2 ;
wire [2:0] lru_triad2_muxsel_c2 ;
wire [2:0] lru_triad3_muxsel_c2 ;
wire [3:0] diag_wr_way_c3;
wire [3:0] diag_wr_way_c4;
wire [3:0] dec_lower_tag_way_c2;
wire [3:0] dec_high_tag_way_c2;
wire [3:0] bist_way_c1;
wire [3:0] bist_way_c2;
wire bist_enable_c1;
wire bist_enable_c2;
wire [3:0] lru_quad_muxsel_c2;
wire [3:0] lru_quad_muxsel_c3;
wire [2:0] tag_triad0_muxsel_c2 ;
wire [2:0] tag_triad1_muxsel_c2 ;
wire [2:0] tag_triad2_muxsel_c2 ;
wire [2:0] tag_triad3_muxsel_c2 ;
wire [2:0] dir_triad0_way_c2, dir_triad1_way_c2 ;
wire [2:0] dir_triad2_way_c2, dir_triad3_way_c2 ;
wire [2:0] tag_triad0_muxsel_c3;
wire [2:0] tag_triad1_muxsel_c3;
wire [2:0] tag_triad2_muxsel_c3;
wire [2:0] tag_triad3_muxsel_c3;
wire [3:0] dir_quad_way_c2;
wire [3:0] dir_quad_way_c3;
wire sel_bist_way_c2 ;
wire sel_diag_way_c4 ;
wire sel_tecc_way_c2 ;
wire [1:0] enc_high_tag_way_c2;
wire [1:0] enc_lower_tag_way_c2;
wire use_dec_sel_c2;
wire use_dec_sel_c3;
wire l2_dir_map_on_d1;
wire sel_dir_way_c2; // pick way indicated by addr<21:18>
wire [2:0] muxsel_triad0_way_c2 ;
wire [2:0] muxsel_triad1_way_c2 ;
wire [2:0] muxsel_triad2_way_c2 ;
wire [2:0] muxsel_triad3_way_c2 ;
wire nondep_tagdp_par_err_c3;
wire evict_vld_c3_1, evict_vld_c3_2;
wire evict_c3_1;
wire dbb_rst_l;
wire par_err_c3_2;
wire [11:0] lru_way_sel_c3_1;
wire [11:0] valid_c3;
// ----------------------\/ POST 4.2 repeater addition \/-------------------------
assign bist_vuad_wr_data = mbist_write_data ;
assign bist_vuad_write = mbist_l2v_write ;
assign bist_vuad_vd = mbist_l2v_vd ;
assign bist_vuad_index = mbist_l2v_index ;
assign vuad_dp_diag_data_c7_buf = vuad_dp_diag_data_c7 ;
// ----------------------\/ POST 4.2 repeater addition \/-------------------------
///////////////////////////////////////////////////////////////////
// Reset flop
///////////////////////////////////////////////////////////////////
dffrl_async #(1) reset_flop (.q(dbb_rst_l),
.clk(rclk),
.rst_l(arst_l),
.din(grst_l),
.se(se), .si(), .so());
dff_s #(1) ff_evict_c3_1
(.q (evict_vld_c3_1),
.din (arbctl_evict_vld_c2),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_evict_c3_2
(.q (evict_vld_c3_2),
.din (arbctl_evict_vld_c2),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign evict_c3 = evict_vld_c3_1 & ~par_err_c3 ;
assign evict_c3_1 = evict_vld_c3_2 & ~par_err_c3_2 ;
// evict qualification is performed in arbctl.
assign invalid_evict_c3 = |(lru_way_sel_c3_1 & ~valid_c3) ;
////////////////////////////////////////////
// The tag compare operation is a 27 bit
// compare. The overall Parity bit is
// not part of the compare.
//
// An error in any bit of the tag will cause
// the lkup operation to fail except for
// that in the overall parity bit.
// In case of an error in P, we need to
// turn off signalling a parity error.
//
// That is done using the not_hit_way_c2 signal
//assign tagdp_par_err_c2 = arbctl_tagdp_perr_vld_c2 & // inst vld from arbctl
// (|( tag_parity_c2 & not_hit_way_c2 )) ;
////////////////////////////////////////////
////////////////////////////////////////////
// An eviction is turned off if
// par_err_c3 is asserted. This is becuase
// the eviction could very well pick a way
// with a corrupted tag and this would end
// up in memory corruption.
////////////////////////////////////////////
// the following signal is used for reporting purposes only
assign par_err_c2 = arbctl_tagdp_perr_vld_c2 & |(tag_parity_c2 & vuad_dp_valid_c2);
// the following signals are used for control in the pipeline.
// In mbctl, tagctl, vuad, arbctl this par err signal is used
// for different purposes. In all cases it is used only for
// an EVICT instruction or for a miss.
// In mbctl, it is used in the insertion expression provided
// the instruction also misses the $ and FB.
dff_s #(1) ff_tagdp_par_err_c3 (.din(par_err_c2), .clk(rclk),
.q(par_err_c3), .se(se), .si(), .so());
dff_s #(1) ff_tagdp_par_err_c3_2 (.din(par_err_c2), .clk(rclk),
.q(par_err_c3_2), .se(se), .si(), .so());
dff_s #(1) ff_tagdp_mbctl_par_err_c3 (.din(par_err_c2), .clk(rclk),
.q(tagdp_mbctl_par_err_c3), .se(se), .si(), .so());
dff_s #(1) ff_tagdp_tagctl_par_err_c3 (.din(par_err_c2), .clk(rclk),
.q(tagdp_tagctl_par_err_c3), .se(se), .si(), .so());
dff_s #(1) ff_tagdp_arbctl_par_err_c3 (.din(par_err_c2), .clk(rclk),
.q(tagdp_arbctl_par_err_c3), .se(se), .si(), .so());
// In all the destination blocks, vuad, tagctl, mbctl and arbctl, this
// par_err signal is used only for a non-dep instruction.
// Dependents will not report a parity error at all.
// Hovewer, reporting is enabled for all hit cases that encounter a
// tag corruption.
assign nondep_tagdp_par_err_c3 = par_err_c3 & ~mbctl_hit_c3;
dff_s #(1) ff_tagdp_par_err_c4 (.din(nondep_tagdp_par_err_c3), .clk(rclk),
.q(tagdp_par_err_c4), .se(se), .si(), .so());
dff_s #(1) ff_tagdp_par_err_c5 (.din(tagdp_par_err_c4), .clk(rclk),
.q(tagdp_par_err_c5), .se(se), .si(), .so());
dff_s #(1) ff_tag_error_c6 (.din(tagdp_par_err_c5), .clk(rclk),
.q(tag_error_c6), .se(se), .si(), .so());
dff_s #(1) ff_tag_error_c7 (.din(tag_error_c6), .clk(rclk),
.q(tag_error_c7), .se(se), .si(), .so());
dff_s #(1) ff_tag_error_c8 (.din(tag_error_c7), .clk(rclk),
.q(tag_error_c8), .se(se), .si(), .so());
/////////////////////////////////////////////
// Mux select generation to read
// out the evicted tag &
// 16:1 muxing of the tag read
//
// In C2 we generate the muxselects for all the
// 4 triads.
// These mux selects are generated for the following
// 2 categories of accesses.
// I)Normal accesses: sels generated by vuad_dp
// II) Direct Accesses: Diagnostic/direct mapped, BIST, tecc
//
// In C3 we generate the mux selects for the 4-1 mux in
// this block.
/////////////////////////////////////////////
dff_s #(1) ff_l2_dir_map_on_d1 (.din(l2_dir_map_on), .clk(rclk),
.q(l2_dir_map_on_d1), .se(se), .si(), .so());
dff_s #(4) ff_diag_way_c3 (.din(arbdp_diag_wr_way_c2[3:0]), .clk(rclk),
.q(diag_wr_way_c3[3:0]), .se(se), .si(), .so());
dff_s #(4) ff_diag_way_c4 (.din(diag_wr_way_c3[3:0]), .clk(rclk),
.q(diag_wr_way_c4[3:0]), .se(se), .si(), .so());
dff_s #(4) ff_lru_quad_muxsel_c2 (.din(lru_quad_muxsel_c2[3:0]), .clk(rclk),
.q(lru_quad_muxsel_c3[3:0]), .se(se), .si(), .so());
dff_s #(4) ff_bist_way_c1 (.din(bist_way_px[3:0]), .clk(rclk),
.q(bist_way_c1[3:0]), .se(se), .si(), .so());
dff_s #(4) ff_bist_way_c2 (.din(bist_way_c1[3:0]), .clk(rclk),
.q(bist_way_c2[3:0]), .se(se), .si(), .so());
dff_s #(1) ff_bist_enable_c1 (.din(bist_enable_px), .clk(rclk),
.q(bist_enable_c1), .se(se), .si(), .so());
dff_s #(1) ff_bist_enable_c2 (.din(bist_enable_c1), .clk(rclk),
.q(bist_enable_c2), .se(se), .si(), .so());
assign sel_bist_way_c2 = bist_enable_c2 ;
assign sel_diag_way_c4 = ~bist_enable_c2 & arbctl_l2tag_vld_c4;
assign sel_tecc_way_c2 = ~bist_enable_c2 & ~arbctl_l2tag_vld_c4 &
arbctl_tagdp_tecc_c2 ;
assign sel_dir_way_c2 = ~arbctl_tagdp_tecc_c2 & ~bist_enable_c2 &
~arbctl_l2tag_vld_c4 ;
mux4ds #(2) mux_way_low ( .dout (enc_lower_tag_way_c2[1:0]),
.in0(bist_way_c2[1:0]), // bist way c2
.in1(diag_wr_way_c4[1:0]), // diag way c4
.in2(arbctl_tecc_way_c2[1:0]),// tecc way c2( from a counter in arbdec)
.in3(arbdp_diag_wr_way_c2[1:0]),// addr_c2<19:18>
.sel0(sel_bist_way_c2), // bist way sel
.sel1(sel_diag_way_c4), // no bist way sel and diag sel.
.sel2(sel_tecc_way_c2), // tecc way
.sel3(sel_dir_way_c2)); // default is dir mapped way.
assign dec_lower_tag_way_c2[0] =(enc_lower_tag_way_c2 == 2'd0 ) ;
assign dec_lower_tag_way_c2[1] =(enc_lower_tag_way_c2 == 2'd1 ) ;
assign dec_lower_tag_way_c2[2] =(enc_lower_tag_way_c2 == 2'd2 ) ;
assign dec_lower_tag_way_c2[3] =(enc_lower_tag_way_c2 == 2'd3 ) ;
mux4ds #(2) mux_way_high (.dout (enc_high_tag_way_c2[1:0]),
.in0(bist_way_c2[3:2]), // bist way c2
.in1(diag_wr_way_c4[3:2]), // diag way c4
.in2(arbctl_tecc_way_c2[3:2]), // tecc way c2( from a counter in arbdec)
.in3(arbdp_diag_wr_way_c2[3:2]),// addr_c2<21:20>
.sel0(sel_bist_way_c2), // bist way sel
.sel1(sel_diag_way_c4), // no bist way sel and diag sel.
.sel2(sel_tecc_way_c2), // tecc
.sel3(sel_dir_way_c2)); // default is dir mapped way.
assign dec_high_tag_way_c2[0] = (enc_high_tag_way_c2 == 2'd0 ) ;
assign dec_high_tag_way_c2[1] = (enc_high_tag_way_c2 == 2'd1 ) ;
assign dec_high_tag_way_c2[2] = (enc_high_tag_way_c2 == 2'd2 ) ;
assign dec_high_tag_way_c2[3] = (enc_high_tag_way_c2 == 2'd3 ) ;
// Triad0 muxselects
// Tags in Triad0 correspond to way=0,1,2
assign dir_triad0_way_c2[0] = dec_high_tag_way_c2[0] &
dec_lower_tag_way_c2[0] ; // 0000
assign dir_triad0_way_c2[1] = dec_high_tag_way_c2[0] &
dec_lower_tag_way_c2[1] ; // 0001
assign dir_triad0_way_c2[2] = dec_high_tag_way_c2[0] &
dec_lower_tag_way_c2[2] ; // 0010
assign dir_quad_way_c2[0] = |( dir_triad0_way_c2 ) ;
assign muxsel_triad0_way_c2[1:0] = dir_triad0_way_c2[1:0];
assign muxsel_triad0_way_c2[2] = ~( dir_triad0_way_c2[1] |
dir_triad0_way_c2[0] ) ;
// Triad1 muxselects
// Tags in Triad1 correspond to way=3,4 or 12,5 or 13
assign dir_triad1_way_c2[0] = dec_high_tag_way_c2[0] &
dec_lower_tag_way_c2[3] ; // 0011
assign dir_triad1_way_c2[1] = ( dec_high_tag_way_c2[1] |
dec_high_tag_way_c2[3] ) &
dec_lower_tag_way_c2[0] ; // 0100 or 1100
assign dir_triad1_way_c2[2] = ( dec_high_tag_way_c2[1] |
dec_high_tag_way_c2[3] ) &
dec_lower_tag_way_c2[1] ; // 0101 or 1101
assign dir_quad_way_c2[1] = |( dir_triad1_way_c2 ) ;
assign muxsel_triad1_way_c2[1:0] = dir_triad1_way_c2[1:0];
assign muxsel_triad1_way_c2[2] = ~( dir_triad1_way_c2[1] |
dir_triad1_way_c2[0] ) ;
// Triad2 muxselects
// Tags in Triad2 correspond to way=6 or 14,7 or 15,8
assign dir_triad2_way_c2[0] = ( dec_high_tag_way_c2[1] |
dec_high_tag_way_c2[3] ) &
dec_lower_tag_way_c2[2] ; // 0110 or 1110
assign dir_triad2_way_c2[1] = ( dec_high_tag_way_c2[1] |
dec_high_tag_way_c2[3] ) &
dec_lower_tag_way_c2[3] ; // 0111 or 1111
assign dir_triad2_way_c2[2] = dec_high_tag_way_c2[2] &
dec_lower_tag_way_c2[0] ; // 1000
assign dir_quad_way_c2[2] = |( dir_triad2_way_c2 ) ;
assign muxsel_triad2_way_c2[1:0] = dir_triad2_way_c2[1:0];
assign muxsel_triad2_way_c2[2] = ~( dir_triad2_way_c2[1] |
dir_triad2_way_c2[0] ) ;
// Triad3 muxselects
// Tags in Triad3 correspond to way=9, 10, 11
assign dir_triad3_way_c2[0] = dec_high_tag_way_c2[2] &
dec_lower_tag_way_c2[1] ; // 1001
assign dir_triad3_way_c2[1] = dec_high_tag_way_c2[2] &
dec_lower_tag_way_c2[2] ; // 1010
assign dir_triad3_way_c2[2] = dec_high_tag_way_c2[2] &
dec_lower_tag_way_c2[3] ; // 1011
assign dir_quad_way_c2[3] = |( dir_triad3_way_c2 ) ;
assign use_dec_sel_c2 = ( ~arbctl_normal_tagacc_c2 |
bist_enable_c2 |
l2_dir_map_on_d1 ) ;
dff_s #(1) ff_use_dec_sel_c3 (.din(use_dec_sel_c2), .clk(rclk),
.q(use_dec_sel_c3), .se(se), .si(), .so());
assign muxsel_triad3_way_c2[1:0] = dir_triad3_way_c2[1:0];
assign muxsel_triad3_way_c2[2] = ~( dir_triad3_way_c2[1] |
dir_triad3_way_c2[0] ) ;
/////////
// TRIAD0
/////////
// Use a mux flop for the following to reduce the setup on lru_triad0_muxsel_c2
mux2ds #(3) mux_tag_triad0_muxsel_c2 ( .dout (tag_triad0_muxsel_c2[2:0]),
.in0(muxsel_triad0_way_c2[2:0]),
.in1(lru_triad0_muxsel_c2[2:0]),
.sel0(use_dec_sel_c2),
.sel1(~use_dec_sel_c2));
dff_s #(3) ff_tag_triad0_muxsel_c2 (.din(tag_triad0_muxsel_c2[2:0]), .clk(rclk),
.q(tag_triad0_muxsel_c3[2:0]), .se(se), .si(), .so());
// rst_tri_en required for mux ex
assign triad0_muxsel_c3[2:1] = tag_triad0_muxsel_c3[2:1] & ~{2{rst_tri_en}} ;
assign triad0_muxsel_c3[0] = tag_triad0_muxsel_c3[0] | rst_tri_en ;
/////////
// TRIAD1
/////////
// Use a mux flop for the following to reduce the setup on lru_triad1_muxsel_c2
mux2ds #(3) mux_tag_triad1_muxsel_c2 ( .dout (tag_triad1_muxsel_c2[2:0]),
.in0(muxsel_triad1_way_c2[2:0]),
.in1(lru_triad1_muxsel_c2[2:0]),
.sel0(use_dec_sel_c2),
.sel1(~use_dec_sel_c2));
dff_s #(3) ff_tag_triad1_muxsel_c2 (.din(tag_triad1_muxsel_c2[2:0]), .clk(rclk),
.q(tag_triad1_muxsel_c3[2:0]), .se(se), .si(), .so());
// rst_tri_en required for mux ex
assign triad1_muxsel_c3[2:1] = tag_triad1_muxsel_c3[2:1] & ~{2{rst_tri_en}} ;
assign triad1_muxsel_c3[0] = tag_triad1_muxsel_c3[0] | rst_tri_en ;
/////////
// TRIAD2
/////////
// Use a mux flop for the following to reduce the setup on lru_triad2_muxsel_c2
mux2ds #(3) mux_tag_triad2_muxsel_c2 ( .dout (tag_triad2_muxsel_c2[2:0]),
.in0(muxsel_triad2_way_c2[2:0]),
.in1(lru_triad2_muxsel_c2[2:0]),
.sel0(use_dec_sel_c2),
.sel1(~use_dec_sel_c2));
dff_s #(3) ff_tag_triad2_muxsel_c2 (.din(tag_triad2_muxsel_c2[2:0]), .clk(rclk),
.q(tag_triad2_muxsel_c3[2:0]), .se(se), .si(), .so());
// rst_tri_en required for mux ex
assign triad2_muxsel_c3[2:1] = tag_triad2_muxsel_c3[2:1] & ~{2{rst_tri_en}} ;
assign triad2_muxsel_c3[0] = tag_triad2_muxsel_c3[0] | rst_tri_en ;
/////////
// TRIAD3
/////////
// Use a mux flop for the following to reduce the setup on lru_triad3_muxsel_c2
mux2ds #(3) mux_tag_triad3_muxsel_c2 ( .dout (tag_triad3_muxsel_c2[2:0]),
.in0(muxsel_triad3_way_c2[2:0]),
.in1(lru_triad3_muxsel_c2[2:0]),
.sel0(use_dec_sel_c2),
.sel1(~use_dec_sel_c2));
dff_s #(3) ff_tag_triad3_muxsel_c2 (.din(tag_triad3_muxsel_c2[2:0]), .clk(rclk),
.q(tag_triad3_muxsel_c3[2:0]), .se(se), .si(), .so());
// rst_tri_en required for mux ex
assign triad3_muxsel_c3[2:1] = tag_triad3_muxsel_c3[2:1] & ~{2{rst_tri_en}} ;
assign triad3_muxsel_c3[0] = tag_triad3_muxsel_c3[0] | rst_tri_en ;
dff_s #(4) ff_dir_quad_way_c3 (.din(dir_quad_way_c2[3:0]), .clk(rclk),
.q(dir_quad_way_c3[3:0]), .se(se), .si(), .so());
/////////
// QUAD
/////////
// Use the C5 select from the diagnostic read/BIST or the C3 select from Lru.
assign tag_quad_muxsel_c3[0] = (( dir_quad_way_c3[0] & use_dec_sel_c3 )
| ( ~use_dec_sel_c3 & lru_quad_muxsel_c3[0] ))
& ~rst_tri_en ;
assign tag_quad_muxsel_c3[1] = (( dir_quad_way_c3[1] & use_dec_sel_c3 )
| ( ~use_dec_sel_c3 & lru_quad_muxsel_c3[1] ))
& ~rst_tri_en ;
assign tag_quad_muxsel_c3[2] = (( dir_quad_way_c3[2] & use_dec_sel_c3 )
| ( ~use_dec_sel_c3 & lru_quad_muxsel_c3[2] ))
& ~rst_tri_en ;
assign tag_quad_muxsel_c3[3] = (( dir_quad_way_c3[3] & use_dec_sel_c3 )
| ( ~use_dec_sel_c3 & lru_quad_muxsel_c3[3] ))
| rst_tri_en ;
//*****************************************************************************
// LRU state flop.
// * initialized to 1 on reset.
// * left shifted ( rotate) on every eviction.
// * else maintains its state.
//*****************************************************************************
wire lshift_lru_triad0;
wire no_lshift_lru_triad0;
wire [2:0] lru_state_lshift_triad0;
wire [2:0] lru_state_triad0 ;
wire [2:0] lru_state_triad0_p ;
wire lshift_lru_triad1;
wire no_lshift_lru_triad1;
wire [2:0] lru_state_lshift_triad1;
wire [2:0] lru_state_triad1 ;
wire [2:0] lru_state_triad1_p ;
wire lshift_lru_triad2;
wire no_lshift_lru_triad2;
wire [2:0] lru_state_lshift_triad2;
wire [2:0] lru_state_triad2 ;
wire [2:0] lru_state_triad2_p ;
wire lshift_lru_triad3;
wire no_lshift_lru_triad3;
wire [2:0] lru_state_lshift_triad3;
wire [2:0] lru_state_triad3 ;
wire [2:0] lru_state_triad3_p ;
wire pick_triad0;
wire pick_triad1;
wire pick_triad2;
wire pick_triad3;
wire [11:0] vec_unvuad_dp_used_c2;
wire [11:0] vec_unvuad_dp_alloc_c2;
wire sel_unvuad_dp_used_c2;
//wire vuad_dp_way_avail_c2;
wire vec_unalloc0to2_c2;
wire vec_unalloc3to5_c2;
wire vec_unalloc6to8_c2;
wire vec_unalloc9to11_c2;
wire vec_unused0to2_c2;
wire vec_unused3to5_c2;
wire vec_unused6to8_c2;
wire vec_unused9to11_c2;
wire [3:0] used_lru_quad_c2;
wire [2:0] used_lru_triad0_c2;
wire [2:0] used_lru_triad1_c2;
wire [2:0] used_lru_triad2_c2;
wire [2:0] used_lru_triad3_c2;
wire [3:0] alloc_lru_quad_c2;
wire [2:0] alloc_lru_triad0_c2;
wire [2:0] alloc_lru_triad1_c2;
wire [2:0] alloc_lru_triad2_c2;
wire [2:0] alloc_lru_triad3_c2;
wire [2:0] used_triad0_tagsel_c2;
wire [2:0] alloc_triad0_tagsel_c2;
wire [2:0] lru_triad0_tagsel_c2;
wire [2:0] used_triad1_tagsel_c2;
wire [2:0] alloc_triad1_tagsel_c2;
wire [2:0] lru_triad1_tagsel_c2;
wire [2:0] used_triad2_tagsel_c2;
wire [2:0] alloc_triad2_tagsel_c2;
wire [2:0] lru_triad2_tagsel_c2;
wire [2:0] used_triad3_tagsel_c2;
wire [2:0] alloc_triad3_tagsel_c2;
wire [2:0] lru_triad3_tagsel_c2;
wire [3:0] used_quad_sel_c2;
wire [3:0] alloc_quad_sel_c2;
wire [3:0] lru_quad_sel_c2;
wire [11:0] lru_way_sel_c2;
wire lshift_lru;
wire no_lshift_lru;
wire [3:0] lru_state_lshift;
wire [3:0] lru_state_p;
wire [3:0] lru_state;
wire init_lru_state;
wire [3:0] dec_lo_dir_way_c2;
wire [3:0] dec_hi_dir_way_c2;
wire [11:0] dec_dir_way_c2;
wire [11:0] evict_way_sel_c2;
wire [11:0] spec_alloc_c2, spec_alloc_c3;
wire [11:0] mod_alloc_c2;
////////////////////////////////////////////////////////////////////////////////
// LRU algorithm is used to select a way, out of 16 ways, to be evicted out of
// the L2 Cache. The algorithm used for the way select is not a tru LRU (Least
// Recently Used) algorithm but Round Robin arbitration. Round Robin arbitration
// is done in two stages by dividing 12 ways in 4 triads of 3 ways each
// Triad0[3:0] = Way[2:0],
// Triad1[3:0] = Way[5:3],
// Triad2[3:0] = Way[8:6],
// Triad3[3:0] = Way[11:9].
//
// First Round Robin is done within each quads to select one of the 3 ways
// and then Round Robin is done to select one of the four quads.
// A 4 bit one hot shift register maintains the state of the arbiter. An one
// at the bit location corresponding to a way represents highest priority for
// that way. Everytime an eviction takes place, state register is updated by
// shifting it left by one bit otherwise state of the register does not change.
// State register is used in C2 for the way selection and it is updated in the
// C3. On reset state rtegister is initialized to a state such that way0 has the
// highest priority.
//
// Way selection algorithm depends on the Used and Allocate bit of the VUAD
// array, read during C1, for the way selection. First priority is given to the
// ways that has not been Used and has not been Allocated for the eviction in
// the previous cycle. If there is no Unused and Unallocated way then a way that
// has not been previously Allocated is given preference.
// Note : Invalid bit is not used for the way selection as if a way is Invalid
// then its Used bit will not be set, so checking Invalid bit is
// redundant.
////////////////////////////////////////////////////////////////////////////////
// QUAD ANCHOR
assign init_lru_state = ~dbb_rst_l | ~dbginit_l ;
assign lshift_lru = evict_c3_1 & ~init_lru_state;
assign no_lshift_lru = ~evict_c3_1 & ~init_lru_state ;
assign lru_state_lshift = { lru_state[2:0], lru_state[3] } ;
mux3ds #(4) mux_lru_st (.dout (lru_state_p[3:0]),
.in0(4'b0001),
.in1(lru_state_lshift[3:0]),
.in2(lru_state[3:0]),
.sel0(init_lru_state),
.sel1(lshift_lru),
.sel2(no_lshift_lru));
dff_s #(4) ff_lru_state (.din(lru_state_p[3:0]),
.clk(rclk),
.q(lru_state[3:0]),
.se(se),
.si(),
.so());
// Triad0 ANCHOR
assign lshift_lru_triad0 = evict_c3_1 & pick_triad0 & ~init_lru_state;
assign no_lshift_lru_triad0 = ~( evict_c3_1 & pick_triad0 ) & ~init_lru_state ;
assign lru_state_lshift_triad0 = { lru_state_triad0[1:0], lru_state_triad0[2] } ;
mux3ds #(3) mux_lru_st_triad0 (.dout (lru_state_triad0_p[2:0]),
.in0(3'b001),
.in1(lru_state_lshift_triad0[2:0]),
.in2(lru_state_triad0[2:0]),
.sel0(init_lru_state),
.sel1(lshift_lru_triad0),
.sel2(no_lshift_lru_triad0));
dff_s #(3) ff_lru_state_triad0 (.din(lru_state_triad0_p[2:0]),
.clk(rclk),
.q(lru_state_triad0[2:0]),
.se(se),
.si(),
.so());
// Triad1 ANCHOR
assign lshift_lru_triad1 = evict_c3_1 & pick_triad1 & ~init_lru_state;
assign no_lshift_lru_triad1 = ~( evict_c3_1 & pick_triad1 ) & ~init_lru_state ;
assign lru_state_lshift_triad1 = { lru_state_triad1[1:0], lru_state_triad1[2] } ;
mux3ds #(3) mux_lru_st_triad1 (.dout (lru_state_triad1_p[2:0]),
.in0(3'b001),
.in1(lru_state_lshift_triad1[2:0]),
.in2(lru_state_triad1[2:0]),
.sel0(init_lru_state),
.sel1(lshift_lru_triad1),
.sel2(no_lshift_lru_triad1));
dff_s #(3) ff_lru_state_triad1 (.din(lru_state_triad1_p[2:0]),
.clk(rclk),
.q(lru_state_triad1[2:0]),
.se(se),
.si(),
.so());
// Triad2 ANCHOR
assign lshift_lru_triad2 = evict_c3_1 & pick_triad2 & ~init_lru_state;
assign no_lshift_lru_triad2 = ~( evict_c3_1 & pick_triad2 ) & ~init_lru_state ;
assign lru_state_lshift_triad2 = { lru_state_triad2[1:0], lru_state_triad2[2] } ;
mux3ds #(3) mux_lru_st_triad2 (.dout (lru_state_triad2_p[2:0]),
.in0(3'b001),
.in1(lru_state_lshift_triad2[2:0]),
.in2(lru_state_triad2[2:0]),
.sel0(init_lru_state),
.sel1(lshift_lru_triad2),
.sel2(no_lshift_lru_triad2));
dff_s #(3) ff_lru_state_triad2 (.din(lru_state_triad2_p[2:0]),
.clk(rclk),
.q(lru_state_triad2[2:0]),
.se(se),
.si(),
.so());
// Triad2 ANCHOR
assign lshift_lru_triad3 = evict_c3_1 & pick_triad3 & ~init_lru_state;
assign no_lshift_lru_triad3 = ~( evict_c3_1 & pick_triad3 ) & ~init_lru_state ;
assign lru_state_lshift_triad3 = { lru_state_triad3[1:0], lru_state_triad3[2] } ;
mux3ds #(3) mux_lru_st_triad3 (.dout (lru_state_triad3_p[2:0]),
.in0(3'b001),
.in1(lru_state_lshift_triad3[2:0]),
.in2(lru_state_triad3[2:0]),
.sel0(init_lru_state),
.sel1(lshift_lru_triad3),
.sel2(no_lshift_lru_triad3));
dff_s #(3) ff_lru_state_triad3 (.din(lru_state_triad3_p[2:0]),
.clk(rclk),
.q(lru_state_triad3[2:0]),
.se(se),
.si(),
.so());
//************************************************************************************
// LRU algorithm
// * 3 vectors are computed ( Invalid[15:0], Unused[15:0], Unallocated[15:0] )
// * On vector is selected based on the 3 select bits read out of the array in C1,
// invalid, unused, unallocated
// * A state register is used to decide which quadrant to pick.
// * The same state register picks a way in each of the 4 quadrants.
//************************************************************************************
//
// If an instruction in C2 sets the alloc bit, it needs to be bypassed
// to the instruction that immediately follows it. This is done speculatively
// using the spec_alloc_c3 signal if the instruction in C2 is to the same index
// as an instruction in C3.
assign spec_alloc_c2 = ( tag_way_sel_c2 & vuad_dp_valid_c2 ) ;
dff_s #(12) ff_spec_alloc_c3 (.din(spec_alloc_c2[11:0]),
.clk(rclk), .q(spec_alloc_c3[11:0]),
.se(se), .si(), .so());
assign mod_alloc_c2 = ( vuad_dp_alloc_c2 |
( spec_alloc_c3 & {12{vuad_tagdp_sel_c2_d1}} ) );
// 2-3 gates.
assign vec_unvuad_dp_used_c2 = ~vuad_dp_used_c2 & ~mod_alloc_c2 ;
assign vec_unvuad_dp_alloc_c2 = ~mod_alloc_c2 ;
assign sel_unvuad_dp_used_c2 = |( vec_unvuad_dp_used_c2) ; // WAY lock will be ORED to this
// 2-3 gates.
assign vec_unused0to2_c2 = |(vec_unvuad_dp_used_c2[2:0]);
assign vec_unused3to5_c2 = |(vec_unvuad_dp_used_c2[5:3]);
assign vec_unused6to8_c2 = |(vec_unvuad_dp_used_c2[8:6]);
assign vec_unused9to11_c2 = |(vec_unvuad_dp_used_c2[11:9]);
// vec_unallocxtoxc2 is used to select one of the four quads.
assign vec_unalloc0to2_c2 = |(vec_unvuad_dp_alloc_c2[2:0]);
assign vec_unalloc3to5_c2 = |(vec_unvuad_dp_alloc_c2[5:3]);
assign vec_unalloc6to8_c2 = |(vec_unvuad_dp_alloc_c2[8:6]);
assign vec_unalloc9to11_c2 = |(vec_unvuad_dp_alloc_c2[11:9]);
/////////////////////////////
//UNUSED ROUND ROBIN PICK
/////////////////////////////
assign used_lru_quad_c2 = { vec_unused9to11_c2,
vec_unused6to8_c2,
vec_unused3to5_c2,
vec_unused0to2_c2 } ;
assign used_lru_triad0_c2 = vec_unvuad_dp_used_c2[2:0] ;
assign used_lru_triad1_c2 = vec_unvuad_dp_used_c2[5:3] ;
assign used_lru_triad2_c2 = vec_unvuad_dp_used_c2[8:6] ;
assign used_lru_triad3_c2 = vec_unvuad_dp_used_c2[11:9] ;
/////////////////////////////
//UNALLOC ROUND ROBIN PICK
/////////////////////////////
assign alloc_lru_quad_c2 = { vec_unalloc9to11_c2,
vec_unalloc6to8_c2,
vec_unalloc3to5_c2,
vec_unalloc0to2_c2 } ;
assign alloc_lru_triad0_c2 = vec_unvuad_dp_alloc_c2[2:0] ;
assign alloc_lru_triad1_c2 = vec_unvuad_dp_alloc_c2[5:3] ;
assign alloc_lru_triad2_c2 = vec_unvuad_dp_alloc_c2[8:6] ;
assign alloc_lru_triad3_c2 = vec_unvuad_dp_alloc_c2[11:9] ;
/************ LRU way within triad0 ************************/
assign used_triad0_tagsel_c2[0] = used_lru_triad0_c2[0] &
( lru_state_triad0[0] |
( lru_state_triad0[1] & ~( used_lru_triad0_c2[1] |
used_lru_triad0_c2[2] ) ) |
( lru_state_triad0[2] & ~used_lru_triad0_c2[2] ) ) ;
assign used_triad0_tagsel_c2[1] = used_lru_triad0_c2[1] &
( lru_state_triad0[1] |
( lru_state_triad0[2] & ~( used_lru_triad0_c2[2] |
used_lru_triad0_c2[0] )) |
( lru_state_triad0[0] & ~used_lru_triad0_c2[0]) ) ;
assign used_triad0_tagsel_c2[2] = used_lru_triad0_c2[2] &
( lru_state_triad0[2] |
( lru_state_triad0[0] & ~(used_lru_triad0_c2[0] |
used_lru_triad0_c2[1])) |
( lru_state_triad0[1] & ~used_lru_triad0_c2[1] ) ) ;
assign alloc_triad0_tagsel_c2[0] = alloc_lru_triad0_c2[0] &
( lru_state_triad0[0] |
( lru_state_triad0[1] & ~( alloc_lru_triad0_c2[1] |
alloc_lru_triad0_c2[2] ) ) |
( lru_state_triad0[2] & ~alloc_lru_triad0_c2[2] ) ) ;
assign alloc_triad0_tagsel_c2[1] = alloc_lru_triad0_c2[1] &
( lru_state_triad0[1] |
( lru_state_triad0[2] & ~( alloc_lru_triad0_c2[2] |
alloc_lru_triad0_c2[0] )) |
( lru_state_triad0[0] & ~alloc_lru_triad0_c2[0]) ) ;
assign alloc_triad0_tagsel_c2[2] = alloc_lru_triad0_c2[2] &
( lru_state_triad0[2] |
( lru_state_triad0[0] & ~(alloc_lru_triad0_c2[0] |
alloc_lru_triad0_c2[1])) |
( lru_state_triad0[1] & ~alloc_lru_triad0_c2[1] ) ) ;
mux2ds #(3) mux_used_lru_triad0 (.dout (lru_triad0_tagsel_c2[2:0]),
.in0(used_triad0_tagsel_c2[2:0]),
.in1(alloc_triad0_tagsel_c2[2:0]),
.sel0(sel_unvuad_dp_used_c2),
.sel1(~sel_unvuad_dp_used_c2));
assign lru_triad0_muxsel_c2[1:0] = lru_triad0_tagsel_c2[1:0] ;
assign lru_triad0_muxsel_c2[2] = ~( lru_triad0_tagsel_c2[1] | lru_triad0_tagsel_c2[0] ) ;
/************ LRU way within triad1 ************************/
assign used_triad1_tagsel_c2[0] = used_lru_triad1_c2[0] &
( lru_state_triad1[0] |
( lru_state_triad1[1] & ~( used_lru_triad1_c2[1] |
used_lru_triad1_c2[2] ) ) |
( lru_state_triad1[2] & ~used_lru_triad1_c2[2] ) ) ;
assign used_triad1_tagsel_c2[1] = used_lru_triad1_c2[1] &
( lru_state_triad1[1] |
( lru_state_triad1[2] & ~( used_lru_triad1_c2[2] |
used_lru_triad1_c2[0] )) |
( lru_state_triad1[0] & ~used_lru_triad1_c2[0]) ) ;
assign used_triad1_tagsel_c2[2] = used_lru_triad1_c2[2] &
( lru_state_triad1[2] |
( lru_state_triad1[0] & ~(used_lru_triad1_c2[0] |
used_lru_triad1_c2[1])) |
( lru_state_triad1[1] & ~used_lru_triad1_c2[1] ) ) ;
assign alloc_triad1_tagsel_c2[0] = alloc_lru_triad1_c2[0] &
( lru_state_triad1[0] |
( lru_state_triad1[1] & ~( alloc_lru_triad1_c2[1] |
alloc_lru_triad1_c2[2] ) ) |
( lru_state_triad1[2] & ~alloc_lru_triad1_c2[2] ) ) ;
assign alloc_triad1_tagsel_c2[1] = alloc_lru_triad1_c2[1] &
( lru_state_triad1[1] |
( lru_state_triad1[2] & ~( alloc_lru_triad1_c2[2] |
alloc_lru_triad1_c2[0] )) |
( lru_state_triad1[0] & ~alloc_lru_triad1_c2[0]) ) ;
assign alloc_triad1_tagsel_c2[2] = alloc_lru_triad1_c2[2] &
( lru_state_triad1[2] |
( lru_state_triad1[0] & ~(alloc_lru_triad1_c2[0] |
alloc_lru_triad1_c2[1])) |
( lru_state_triad1[1] & ~alloc_lru_triad1_c2[1] ) ) ;
mux2ds #(3) mux_used_lru_triad1 (.dout (lru_triad1_tagsel_c2[2:0]),
.in0(used_triad1_tagsel_c2[2:0]),
.in1(alloc_triad1_tagsel_c2[2:0]),
.sel0(sel_unvuad_dp_used_c2),
.sel1(~sel_unvuad_dp_used_c2));
assign lru_triad1_muxsel_c2[1:0] = lru_triad1_tagsel_c2[1:0] ;
assign lru_triad1_muxsel_c2[2] = ~( lru_triad1_tagsel_c2[1] | lru_triad1_tagsel_c2[0] ) ;
/************ LRU way within triad2 ************************/
assign used_triad2_tagsel_c2[0] = used_lru_triad2_c2[0] &
( lru_state_triad2[0] |
( lru_state_triad2[1] & ~( used_lru_triad2_c2[1] |
used_lru_triad2_c2[2] ) ) |
( lru_state_triad2[2] & ~used_lru_triad2_c2[2] ) ) ;
assign used_triad2_tagsel_c2[1] = used_lru_triad2_c2[1] &
( lru_state_triad2[1] |
( lru_state_triad2[2] & ~( used_lru_triad2_c2[2] |
used_lru_triad2_c2[0] )) |
( lru_state_triad2[0] & ~used_lru_triad2_c2[0]) ) ;
assign used_triad2_tagsel_c2[2] = used_lru_triad2_c2[2] &
( lru_state_triad2[2] |
( lru_state_triad2[0] & ~(used_lru_triad2_c2[0] |
used_lru_triad2_c2[1])) |
( lru_state_triad2[1] & ~used_lru_triad2_c2[1] ) ) ;
assign alloc_triad2_tagsel_c2[0] = alloc_lru_triad2_c2[0] &
( lru_state_triad2[0] |
( lru_state_triad2[1] & ~( alloc_lru_triad2_c2[1] |
alloc_lru_triad2_c2[2] ) ) |
( lru_state_triad2[2] & ~alloc_lru_triad2_c2[2] ) ) ;
assign alloc_triad2_tagsel_c2[1] = alloc_lru_triad2_c2[1] &
( lru_state_triad2[1] |
( lru_state_triad2[2] & ~( alloc_lru_triad2_c2[2] |
alloc_lru_triad2_c2[0] )) |
( lru_state_triad2[0] & ~alloc_lru_triad2_c2[0]) ) ;
assign alloc_triad2_tagsel_c2[2] = alloc_lru_triad2_c2[2] &
( lru_state_triad2[2] |
( lru_state_triad2[0] & ~(alloc_lru_triad2_c2[0] |
alloc_lru_triad2_c2[1])) |
( lru_state_triad2[1] & ~alloc_lru_triad2_c2[1] ) ) ;
mux2ds #(3) mux_used_lru_triad2 (.dout (lru_triad2_tagsel_c2[2:0]),
.in0(used_triad2_tagsel_c2[2:0]),
.in1(alloc_triad2_tagsel_c2[2:0]),
.sel0(sel_unvuad_dp_used_c2),
.sel1(~sel_unvuad_dp_used_c2));
assign lru_triad2_muxsel_c2[1:0] = lru_triad2_tagsel_c2[1:0] ;
assign lru_triad2_muxsel_c2[2] = ~( lru_triad2_tagsel_c2[1] | lru_triad2_tagsel_c2[0] ) ;
/************ LRU way within triad3 ************************/
assign used_triad3_tagsel_c2[0] = used_lru_triad3_c2[0] &
( lru_state_triad3[0] |
( lru_state_triad3[1] & ~( used_lru_triad3_c2[1] |
used_lru_triad3_c2[2] ) ) |
( lru_state_triad3[2] & ~used_lru_triad3_c2[2] ) ) ;
assign used_triad3_tagsel_c2[1] = used_lru_triad3_c2[1] &
( lru_state_triad3[1] |
( lru_state_triad3[2] & ~( used_lru_triad3_c2[2] |
used_lru_triad3_c2[0] )) |
( lru_state_triad3[0] & ~used_lru_triad3_c2[0]) ) ;
assign used_triad3_tagsel_c2[2] = used_lru_triad3_c2[2] &
( lru_state_triad3[2] |
( lru_state_triad3[0] & ~(used_lru_triad3_c2[0] |
used_lru_triad3_c2[1])) |
( lru_state_triad3[1] & ~used_lru_triad3_c2[1] ) ) ;
assign alloc_triad3_tagsel_c2[0] = alloc_lru_triad3_c2[0] &
( lru_state_triad3[0] |
( lru_state_triad3[1] & ~( alloc_lru_triad3_c2[1] |
alloc_lru_triad3_c2[2] ) ) |
( lru_state_triad3[2] & ~alloc_lru_triad3_c2[2] ) ) ;
assign alloc_triad3_tagsel_c2[1] = alloc_lru_triad3_c2[1] &
( lru_state_triad3[1] |
( lru_state_triad3[2] & ~( alloc_lru_triad3_c2[2] |
alloc_lru_triad3_c2[0] )) |
( lru_state_triad3[0] & ~alloc_lru_triad3_c2[0]) ) ;
assign alloc_triad3_tagsel_c2[2] = alloc_lru_triad3_c2[2] &
( lru_state_triad3[2] |
( lru_state_triad3[0] & ~(alloc_lru_triad3_c2[0] |
alloc_lru_triad3_c2[1])) |
( lru_state_triad3[1] & ~alloc_lru_triad3_c2[1] ) ) ;
mux2ds #(3) mux_used_lru_triad3 (.dout (lru_triad3_tagsel_c2[2:0]),
.in0(used_triad3_tagsel_c2[2:0]),
.in1(alloc_triad3_tagsel_c2[2:0]),
.sel0(sel_unvuad_dp_used_c2),
.sel1(~sel_unvuad_dp_used_c2));
assign lru_triad3_muxsel_c2[1:0] = lru_triad3_tagsel_c2[1:0] ;
assign lru_triad3_muxsel_c2[2] = ~( lru_triad3_tagsel_c2[1] | lru_triad3_tagsel_c2[0] ) ;
/************ LRU quad ************************/
assign used_quad_sel_c2[0] = used_lru_quad_c2[0] &
( lru_state[0] |
( lru_state[1] & ~( used_lru_quad_c2[1] |
used_lru_quad_c2[2] | used_lru_quad_c2[3] )) |
( lru_state[2] & ~( used_lru_quad_c2[2] | used_lru_quad_c2[3] )) |
( lru_state[3] & ~(used_lru_quad_c2[3] )) ) ;
assign used_quad_sel_c2[1] = used_lru_quad_c2[1] &
( lru_state[1] |
( lru_state[2] & ~( used_lru_quad_c2[0] |
used_lru_quad_c2[2] | used_lru_quad_c2[3] )) |
( lru_state[3] & ~( used_lru_quad_c2[3] | used_lru_quad_c2[0] )) |
( lru_state[0] & ~(used_lru_quad_c2[0] )) ) ;
assign used_quad_sel_c2[2] = used_lru_quad_c2[2] &
( lru_state[2] |
( lru_state[3] & ~( used_lru_quad_c2[0] |
used_lru_quad_c2[1] | used_lru_quad_c2[3] )) |
( lru_state[0] & ~( used_lru_quad_c2[0] | used_lru_quad_c2[1] )) |
( lru_state[1] & ~(used_lru_quad_c2[1] )) ) ;
assign used_quad_sel_c2[3] = used_lru_quad_c2[3] &
( lru_state[3] |
( lru_state[0] & ~( used_lru_quad_c2[0] |
used_lru_quad_c2[1] | used_lru_quad_c2[2] )) |
( lru_state[1] & ~( used_lru_quad_c2[2] | used_lru_quad_c2[1] )) |
( lru_state[2] & ~(used_lru_quad_c2[2] )) ) ;
assign alloc_quad_sel_c2[0] = alloc_lru_quad_c2[0] &
( lru_state[0] |
( lru_state[1] & ~( alloc_lru_quad_c2[1] |
alloc_lru_quad_c2[2] | alloc_lru_quad_c2[3] )) |
( lru_state[2] & ~( alloc_lru_quad_c2[2] | alloc_lru_quad_c2[3] )) |
( lru_state[3] & ~(alloc_lru_quad_c2[3] )) ) ;
assign alloc_quad_sel_c2[1] = alloc_lru_quad_c2[1] &
( lru_state[1] |
( lru_state[2] & ~( alloc_lru_quad_c2[0] |
alloc_lru_quad_c2[2] | alloc_lru_quad_c2[3] )) |
( lru_state[3] & ~( alloc_lru_quad_c2[3] | alloc_lru_quad_c2[0] )) |
( lru_state[0] & ~(alloc_lru_quad_c2[0] )) ) ;
assign alloc_quad_sel_c2[2] = alloc_lru_quad_c2[2] &
( lru_state[2] |
( lru_state[3] & ~( alloc_lru_quad_c2[0] |
alloc_lru_quad_c2[1] | alloc_lru_quad_c2[3] )) |
( lru_state[0] & ~( alloc_lru_quad_c2[0] | alloc_lru_quad_c2[1] )) |
( lru_state[1] & ~(alloc_lru_quad_c2[1] )) ) ;
assign alloc_quad_sel_c2[3] = alloc_lru_quad_c2[3] &
( lru_state[3] |
( lru_state[0] & ~( alloc_lru_quad_c2[0] |
alloc_lru_quad_c2[1] | alloc_lru_quad_c2[2] )) |
( lru_state[1] & ~( alloc_lru_quad_c2[2] | alloc_lru_quad_c2[1] )) |
( lru_state[2] & ~(alloc_lru_quad_c2[2] )) ) ;
mux2ds #(4) mux_used_lru_quad (.dout (lru_quad_sel_c2[3:0]),
.in0(used_quad_sel_c2[3:0]),
.in1(alloc_quad_sel_c2[3:0]),
.sel0(sel_unvuad_dp_used_c2),
.sel1(~sel_unvuad_dp_used_c2));
assign lru_quad_muxsel_c2[2:0] = lru_quad_sel_c2[2:0] ;
assign lru_quad_muxsel_c2[3] = ~( lru_quad_sel_c2[2] | lru_quad_sel_c2[1] | lru_quad_sel_c2[0] ) ;
// lru_way_sel_c2 takes 14-15 gates to compute.
assign lru_way_sel_c2[2:0] = lru_triad0_tagsel_c2 & {3{lru_quad_sel_c2[0]}} ;
assign lru_way_sel_c2[5:3] = lru_triad1_tagsel_c2 & {3{lru_quad_sel_c2[1]}} ;
assign lru_way_sel_c2[8:6] = lru_triad2_tagsel_c2 & {3{lru_quad_sel_c2[2]}} ;
assign lru_way_sel_c2[11:9] = lru_triad3_tagsel_c2 & {3{lru_quad_sel_c2[3]}} ;
assign dec_lo_dir_way_c2[0] = ( arbdp_diag_wr_way_c2[1:0]==2'd0 ) ;
assign dec_lo_dir_way_c2[1] = ( arbdp_diag_wr_way_c2[1:0]==2'd1 ) ;
assign dec_lo_dir_way_c2[2] = ( arbdp_diag_wr_way_c2[1:0]==2'd2 ) ;
assign dec_lo_dir_way_c2[3] = ( arbdp_diag_wr_way_c2[1:0]==2'd3 ) ;
assign dec_hi_dir_way_c2[0] = ( arbdp_diag_wr_way_c2[3:2]==2'd0 ) ;
assign dec_hi_dir_way_c2[1] = ( arbdp_diag_wr_way_c2[3:2]==2'd1 ) ;
assign dec_hi_dir_way_c2[2] = ( arbdp_diag_wr_way_c2[3:2]==2'd2 ) ;
assign dec_hi_dir_way_c2[3] = ( arbdp_diag_wr_way_c2[3:2]==2'd3 ) ;
assign dec_dir_way_c2[0] = dec_hi_dir_way_c2[0] &
dec_lo_dir_way_c2[0] ; // 0000
assign dec_dir_way_c2[1] = dec_hi_dir_way_c2[0] &
dec_lo_dir_way_c2[1] ; // 0001
assign dec_dir_way_c2[2] = dec_hi_dir_way_c2[0] &
dec_lo_dir_way_c2[2] ; // 0010
assign dec_dir_way_c2[3] = dec_hi_dir_way_c2[0] &
dec_lo_dir_way_c2[3] ; // 0011
assign dec_dir_way_c2[4] = ( dec_hi_dir_way_c2[1] |
dec_hi_dir_way_c2[3] ) &
dec_lo_dir_way_c2[0] ; // 0100 or 1100
assign dec_dir_way_c2[5] = ( dec_hi_dir_way_c2[1] |
dec_hi_dir_way_c2[3] ) &
dec_lo_dir_way_c2[1] ; // 0101 or 1101
assign dec_dir_way_c2[6] = ( dec_hi_dir_way_c2[1] |
dec_hi_dir_way_c2[3] ) &
dec_lo_dir_way_c2[2] ; // 0110 or 1110
assign dec_dir_way_c2[7] = ( dec_hi_dir_way_c2[1] |
dec_hi_dir_way_c2[3] ) &
dec_lo_dir_way_c2[3] ; // 0111 or 1111
assign dec_dir_way_c2[8] = dec_hi_dir_way_c2[2] &
dec_lo_dir_way_c2[0] ; // 1000
assign dec_dir_way_c2[9] = dec_hi_dir_way_c2[2] &
dec_lo_dir_way_c2[1] ; // 1001
assign dec_dir_way_c2[10] = dec_hi_dir_way_c2[2] &
dec_lo_dir_way_c2[2] ; // 1010
assign dec_dir_way_c2[11] = dec_hi_dir_way_c2[2] &
dec_lo_dir_way_c2[3] ; // 1011
mux2ds #(12) mux_evict_way_sel_c2
(.dout (evict_way_sel_c2[11:0]),
.in0 (dec_dir_way_c2[11:0]), .sel0 (l2_dir_map_on_d1),
.in1 (lru_way_sel_c2[11:0]), .sel1 (~l2_dir_map_on_d1)
) ;
dff_s #(12) ff_lru_way_c3 (.din(evict_way_sel_c2[11:0]),
.clk(rclk),
.q(lru_way_sel_c3[11:0]),
.se(se),
.si(),
.so());
dff_s #(12) ff_lru_way_c3_1 (.din(evict_way_sel_c2[11:0]),
.clk(rclk),
.q(lru_way_sel_c3_1[11:0]),
.se(se),
.si(),
.so());
dff_s #(12) ff_valid_c3 (.din(vuad_dp_valid_c2[11:0]),
.clk(rclk),
.q(valid_c3[11:0]),
.se(se),
.si(),
.so());
assign pick_triad0 = |(lru_way_sel_c3_1[2:0] ) ;
assign pick_triad1 = |(lru_way_sel_c3_1[5:3] ) ;
assign pick_triad2 = |(lru_way_sel_c3_1[8:6] ) ;
assign pick_triad3 = |(lru_way_sel_c3_1[11:9]) ;
endmodule
|
(** * Stlc: The Simply Typed Lambda-Calculus *)
Require Export Types.
(* ###################################################################### *)
(** * The Simply Typed Lambda-Calculus *)
(** The simply typed lambda-calculus (STLC) is a tiny core calculus
embodying the key concept of _functional abstraction_, which shows
up in pretty much every real-world programming language in some
form (functions, procedures, methods, etc.).
We will follow exactly the same pattern as in the previous
chapter when formalizing this calculus (syntax, small-step
semantics, typing rules) and its main properties (progress and
preservation). The new technical challenges (which will take some
work to deal with) all arise from the mechanisms of _variable
binding_ and _substitution_. *)
(* ###################################################################### *)
(** ** Overview *)
(** The STLC is built on some collection of _base types_ -- booleans,
numbers, strings, etc. The exact choice of base types doesn't
matter -- the construction of the language and its theoretical
properties work out pretty much the same -- so for the sake of
brevity let's take just [Bool] for the moment. At the end of the
chapter we'll see how to add more base types, and in later
chapters we'll enrich the pure STLC with other useful constructs
like pairs, records, subtyping, and mutable state.
Starting from the booleans, we add three things:
- variables
- function abstractions
- application
This gives us the following collection of abstract syntax
constructors (written out here in informal BNF notation -- we'll
formalize it below).
*)
(** Informal concrete syntax:
t ::= x variable
| \x:T1.t2 abstraction
| t1 t2 application
| true constant true
| false constant false
| if t1 then t2 else t3 conditional
*)
(** The [\] symbol (backslash, in ascii) in a function abstraction
[\x:T1.t2] is generally written as a greek letter "lambda" (hence
the name of the calculus). The variable [x] is called the
_parameter_ to the function; the term [t2] is its _body_. The
annotation [:T] specifies the type of arguments that the function
can be applied to. *)
(** Some examples:
- [\x:Bool. x]
The identity function for booleans.
- [(\x:Bool. x) true]
The identity function for booleans, applied to the boolean [true].
- [\x:Bool. if x then false else true]
The boolean "not" function.
- [\x:Bool. true]
The constant function that takes every (boolean) argument to
[true]. *)
(**
- [\x:Bool. \y:Bool. x]
A two-argument function that takes two booleans and returns
the first one. (Note that, as in Coq, a two-argument function
is really a one-argument function whose body is also a
one-argument function.)
- [(\x:Bool. \y:Bool. x) false true]
A two-argument function that takes two booleans and returns
the first one, applied to the booleans [false] and [true].
Note that, as in Coq, application associates to the left --
i.e., this expression is parsed as [((\x:Bool. \y:Bool. x)
false) true].
- [\f:Bool->Bool. f (f true)]
A higher-order function that takes a _function_ [f] (from
booleans to booleans) as an argument, applies [f] to [true],
and applies [f] again to the result.
- [(\f:Bool->Bool. f (f true)) (\x:Bool. false)]
The same higher-order function, applied to the constantly
[false] function. *)
(** As the last several examples show, the STLC is a language of
_higher-order_ functions: we can write down functions that take
other functions as arguments and/or return other functions as
results.
Another point to note is that the STLC doesn't provide any
primitive syntax for defining _named_ functions -- all functions
are "anonymous." We'll see in chapter [MoreStlc] that it is easy
to add named functions to what we've got -- indeed, the
fundamental naming and binding mechanisms are exactly the same.
The _types_ of the STLC include [Bool], which classifies the
boolean constants [true] and [false] as well as more complex
computations that yield booleans, plus _arrow types_ that classify
functions. *)
(**
T ::= Bool
| T1 -> T2
For example:
- [\x:Bool. false] has type [Bool->Bool]
- [\x:Bool. x] has type [Bool->Bool]
- [(\x:Bool. x) true] has type [Bool]
- [\x:Bool. \y:Bool. x] has type [Bool->Bool->Bool] (i.e. [Bool -> (Bool->Bool)])
- [(\x:Bool. \y:Bool. x) false] has type [Bool->Bool]
- [(\x:Bool. \y:Bool. x) false true] has type [Bool]
*)
(* ###################################################################### *)
(** ** Syntax *)
Module STLC.
(* ################################### *)
(** *** Types *)
Inductive ty : Type :=
| TBool : ty
| TArrow : ty -> ty -> ty.
(* ################################### *)
(** *** Terms *)
Inductive tm : Type :=
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp"
| Case_aux c "tabs" | Case_aux c "ttrue"
| Case_aux c "tfalse" | Case_aux c "tif" ].
(** Note that an abstraction [\x:T.t] (formally, [tabs x T t]) is
always annotated with the type [T] of its parameter, in contrast
to Coq (and other functional languages like ML, Haskell, etc.),
which use _type inference_ to fill in missing annotations. We're
not considering type inference here, to keep things simple. *)
(** Some examples... *)
Definition x := (Id 0).
Definition y := (Id 1).
Definition z := (Id 2).
Hint Unfold x.
Hint Unfold y.
Hint Unfold z.
(** [idB = \x:Bool. x] *)
Notation idB :=
(tabs x TBool (tvar x)).
(** [idBB = \x:Bool->Bool. x] *)
Notation idBB :=
(tabs x (TArrow TBool TBool) (tvar x)).
(** [idBBBB = \x:(Bool->Bool) -> (Bool->Bool). x] *)
Notation idBBBB :=
(tabs x (TArrow (TArrow TBool TBool)
(TArrow TBool TBool))
(tvar x)).
(** [k = \x:Bool. \y:Bool. x] *)
Notation k := (tabs x TBool (tabs y TBool (tvar x))).
(** [notB = \x:Bool. if x then false else true] *)
Notation notB := (tabs x TBool (tif (tvar x) tfalse ttrue)).
(** (We write these as [Notation]s rather than [Definition]s to make
things easier for [auto].) *)
(* ###################################################################### *)
(** ** Operational Semantics *)
(** To define the small-step semantics of STLC terms, we begin -- as
always -- by defining the set of values. Next, we define the
critical notions of _free variables_ and _substitution_, which are
used in the reduction rule for application expressions. And
finally we give the small-step relation itself. *)
(* ################################### *)
(** *** Values *)
(** To define the values of the STLC, we have a few cases to consider.
First, for the boolean part of the language, the situation is
clear: [true] and [false] are the only values. An [if]
expression is never a value. *)
(** Second, an application is clearly not a value: It represents a
function being invoked on some argument, which clearly still has
work left to do. *)
(** Third, for abstractions, we have a choice:
- We can say that [\x:T.t1] is a value only when [t1] is a
value -- i.e., only if the function's body has been
reduced (as much as it can be without knowing what argument it
is going to be applied to).
- Or we can say that [\x:T.t1] is always a value, no matter
whether [t1] is one or not -- in other words, we can say that
reduction stops at abstractions.
Coq, in its built-in functional programming langauge, makes the
first choice -- for example,
Eval simpl in (fun x:bool => 3 + 4)
yields [fun x:bool => 7].
Most real-world functional programming languages make the second
choice -- reduction of a function's body only begins when the
function is actually applied to an argument. We also make the
second choice here. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_true :
value ttrue
| v_false :
value tfalse.
Hint Constructors value.
(** Finally, we must consider what constitutes a _complete_ program.
Intuitively, a "complete" program must not refer to any undefined
variables. We'll see shortly how to define the "free" variables
in a STLC term. A program is "closed", that is, it contains no
free variables.
*)
(** Having made the choice not to reduce under abstractions,
we don't need to worry about whether variables are values, since
we'll always be reducing programs "from the outside in," and that
means the [step] relation will always be working with closed
terms (ones with no free variables). *)
(* ###################################################################### *)
(** *** Substitution *)
(** Now we come to the heart of the STLC: the operation of
substituting one term for a variable in another term.
This operation will be used below to define the operational
semantics of function application, where we will need to
substitute the argument term for the function parameter in the
function's body. For example, we reduce
(\x:Bool. if x then true else x) false
to
if false then true else false
]]
by substituting [false] for the parameter [x] in the body of the
function.
In general, we need to be able to substitute some given
term [s] for occurrences of some variable [x] in another term [t].
In informal discussions, this is usually written [ [x:=s]t ] and
pronounced "substitute [x] with [s] in [t]." *)
(** Here are some examples:
- [[x:=true] (if x then x else false)] yields [if true then true else false]
- [[x:=true] x] yields [true]
- [[x:=true] (if x then x else y)] yields [if true then true else y]
- [[x:=true] y] yields [y]
- [[x:=true] false] yields [false] (vacuous substitution)
- [[x:=true] (\y:Bool. if y then x else false)] yields [\y:Bool. if y then true else false]
- [[x:=true] (\y:Bool. x)] yields [\y:Bool. true]
- [[x:=true] (\y:Bool. y)] yields [\y:Bool. y]
- [[x:=true] (\x:Bool. x)] yields [\x:Bool. x]
The last example is very important: substituting [x] with [true] in
[\x:Bool. x] does _not_ yield [\x:Bool. true]! The reason for
this is that the [x] in the body of [\x:Bool. x] is _bound_ by the
abstraction: it is a new, local name that just happens to be
spelled the same as some global name [x]. *)
(** Here is the definition, informally...
[x:=s]x = s
[x:=s]y = y if x <> y
[x:=s](\x:T11.t12) = \x:T11. t12
[x:=s](\y:T11.t12) = \y:T11. [x:=s]t12 if x <> y
[x:=s](t1 t2) = ([x:=s]t1) ([x:=s]t2)
[x:=s]true = true
[x:=s]false = false
[x:=s](if t1 then t2 else t3) =
if [x:=s]t1 then [x:=s]t2 else [x:=s]t3
]]
*)
(** ... and formally: *)
Reserved Notation "'[' x ':=' s ']' t" (at level 20).
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar x' =>
if eq_id_dec x x' then s else t
| tabs x' T t1 =>
tabs x' T (if eq_id_dec x x' then t1 else ([x:=s] t1))
| tapp t1 t2 =>
tapp ([x:=s] t1) ([x:=s] t2)
| ttrue =>
ttrue
| tfalse =>
tfalse
| tif t1 t2 t3 =>
tif ([x:=s] t1) ([x:=s] t2) ([x:=s] t3)
end
where "'[' x ':=' s ']' t" := (subst x s t).
(** _Technical note_: Substitution becomes trickier to define if we
consider the case where [s], the term being substituted for a
variable in some other term, may itself contain free variables.
Since we are only interested here in defining the [step] relation
on closed terms (i.e., terms like [\x:Bool. x], that do not mention
variables are not bound by some enclosing lambda), we can skip
this extra complexity here, but it must be dealt with when
formalizing richer languages. *)
(** *** *)
(** **** Exercise: 3 stars (substi) *)
(** The definition that we gave above uses Coq's [Fixpoint] facility
to define substitution as a _function_. Suppose, instead, we
wanted to define substitution as an inductive _relation_ [substi].
We've begun the definition by providing the [Inductive] header and
one of the constructors; your job is to fill in the rest of the
constructors. *)
Inductive substi (s:tm) (x:id) : tm -> tm -> Prop :=
| s_var1 :
substi s x (tvar x) s
| s_var2 :
forall y,
x <> y ->
substi s x (tvar y) (tvar y)
| s_abs1 :
forall T t1,
substi s x (tabs x T t1) (tabs x T t1)
| s_abs2 :
forall y T t1,
x <> y ->
substi s x (tabs y T t1) (tabs y T ([x:=s] t1))
| s_app :
forall t1 t2,
substi s x (tapp t1 t2) (tapp ([x:=s] t1) ([x:=s] t2))
| s_true :
substi s x ttrue ttrue
| s_false :
substi s x tfalse tfalse
| s_if :
forall t1 t2 t3,
substi s x (tif t1 t2 t3) (tif ([x:=s] t1) ([x:=s] t2) ([x:=s] t3)).
Hint Constructors substi.
Theorem substi_correct : forall s x t t',
[x:=s]t = t' <-> substi s x t t'.
Proof.
split; intros.
Case "->".
destruct t.
simpl in H.
destruct (eq_id_dec x0 i).
rewrite e. rewrite H. apply s_var1.
rewrite <- H. apply s_var2. assumption.
rewrite <- H. simpl. apply s_app.
simpl in H.
destruct (eq_id_dec x0 i).
rewrite <- H. rewrite <- e. apply s_abs1.
rewrite <- H. apply s_abs2. assumption.
rewrite <- H. simpl. apply s_true.
rewrite <- H. simpl. apply s_false.
rewrite <- H. simpl. apply s_if.
Case "<-".
inversion H.
simpl. rewrite eq_id. reflexivity.
simpl. apply neq_id. assumption.
simpl. rewrite eq_id. reflexivity.
simpl. rewrite neq_id. reflexivity. assumption.
reflexivity.
reflexivity.
reflexivity.
simpl. reflexivity.
Qed.
(** [] *)
(* ################################### *)
(** *** Reduction *)
(** The small-step reduction relation for STLC now follows the same
pattern as the ones we have seen before. Intuitively, to reduce a
function application, we first reduce its left-hand side until it
becomes a literal function; then we reduce its right-hand
side (the argument) until it is also a value; and finally we
substitute the argument for the bound variable in the body of the
function. This last rule, written informally as
(\x:T.t12) v2 ==> [x:=v2]t12
is traditionally called "beta-reduction". *)
(**
value v2
---------------------------- (ST_AppAbs)
(\x:T.t12) v2 ==> [x:=v2]t12
t1 ==> t1'
---------------- (ST_App1)
t1 t2 ==> t1' t2
value v1
t2 ==> t2'
---------------- (ST_App2)
v1 t2 ==> v1 t2'
*)
(** ... plus the usual rules for booleans:
-------------------------------- (ST_IfTrue)
(if true then t1 else t2) ==> t1
--------------------------------- (ST_IfFalse)
(if false then t1 else t2) ==> t2
t1 ==> t1'
---------------------------------------------------- (ST_If)
(if t1 then t2 else t3) ==> (if t1' then t2 else t3)
*)
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
tapp t1 t2 ==> tapp t1' t2
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
tapp v1 t2 ==> tapp v1 t2'
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1"
| Case_aux c "ST_App2" | Case_aux c "ST_IfTrue"
| Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
Hint Constructors step.
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
(* ##################################### *)
(* ##################################### *)
(** *** Examples *)
(** Example:
((\x:Bool->Bool. x) (\x:Bool. x)) ==>* (\x:Bool. x)
i.e.
(idBB idB) ==>* idB
*)
Lemma step_example1 :
(tapp idBB idB) ==>* idB.
Proof.
eapply multi_step.
apply ST_AppAbs.
apply v_abs.
simpl.
apply multi_refl. Qed.
(** Example:
((\x:Bool->Bool. x) ((\x:Bool->Bool. x) (\x:Bool. x)))
==>* (\x:Bool. x)
i.e.
(idBB (idBB idB)) ==>* idB.
*)
Lemma step_example2 :
(tapp idBB (tapp idBB idB)) ==>* idB.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto.
eapply multi_step.
apply ST_AppAbs. simpl. auto.
simpl. apply multi_refl. Qed.
(** Example:
((\x:Bool->Bool. x) (\x:Bool. if x then false
else true)) true)
==>* false
i.e.
((idBB notB) ttrue) ==>* tfalse.
*)
Lemma step_example3 :
tapp (tapp idBB notB) ttrue ==>* tfalse.
Proof.
eapply multi_step.
apply ST_App1. apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_IfTrue. apply multi_refl. Qed.
(** Example:
((\x:Bool -> Bool. x) ((\x:Bool. if x then false
else true) true))
==>* false
i.e.
(idBB (notB ttrue)) ==>* tfalse.
*)
Lemma step_example4 :
tapp idBB (tapp notB ttrue) ==>* tfalse.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_App2. auto.
apply ST_IfTrue.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
apply multi_refl. Qed.
(** A more automatic proof *)
Lemma step_example1' :
(tapp idBB idB) ==>* idB.
Proof. normalize. Qed.
(** Again, we can use the [normalize] tactic from above to simplify
the proof. *)
Lemma step_example2' :
(tapp idBB (tapp idBB idB)) ==>* idB.
Proof.
normalize.
Qed.
Lemma step_example3' :
tapp (tapp idBB notB) ttrue ==>* tfalse.
Proof. normalize. Qed.
Lemma step_example4' :
tapp idBB (tapp notB ttrue) ==>* tfalse.
Proof. normalize. Qed.
(** **** Exercise: 2 stars (step_example3) *)
(** Try to do this one both with and without [normalize]. *)
Lemma step_example5 :
(tapp (tapp idBBBB idBB) idB)
==>* idB.
Proof.
(* normalize. *)
eapply multi_step.
apply ST_App1.
apply ST_AppAbs. auto.
simpl.
eapply multi_step.
apply ST_AppAbs. auto.
simpl. apply multi_refl.
Qed.
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** ** Typing *)
(* ################################### *)
(** *** Contexts *)
(** _Question_: What is the type of the term "[x y]"?
_Answer_: It depends on the types of [x] and [y]!
I.e., in order to assign a type to a term, we need to know
what assumptions we should make about the types of its free
variables.
This leads us to a three-place "typing judgment", informally
written [Gamma |- t \in T], where [Gamma] is a
"typing context" -- a mapping from variables to their types. *)
(** We hide the definition of partial maps in a module since it is
actually defined in [SfLib]. *)
Module PartialMap.
Definition partial_map (A:Type) := id -> option A.
Definition empty {A:Type} : partial_map A := (fun _ => None).
(** Informally, we'll write [Gamma, x:T] for "extend the partial
function [Gamma] to also map [x] to [T]." Formally, we use the
function [extend] to add a binding to a partial map. *)
Definition extend {A:Type} (Gamma : partial_map A) (x:id) (T : A) :=
fun x' => if eq_id_dec x x' then Some T else Gamma x'.
Lemma extend_eq : forall A (ctxt: partial_map A) x T,
(extend ctxt x T) x = Some T.
Proof.
intros. unfold extend. rewrite eq_id. auto.
Qed.
Lemma extend_neq : forall A (ctxt: partial_map A) x1 T x2,
x2 <> x1 ->
(extend ctxt x2 T) x1 = ctxt x1.
Proof.
intros. unfold extend. rewrite neq_id; auto.
Qed.
End PartialMap.
Definition context := partial_map ty.
(* ################################### *)
(** *** Typing Relation *)
(**
Gamma x = T
-------------- (T_Var)
Gamma |- x \in T
Gamma , x:T11 |- t12 \in T12
---------------------------- (T_Abs)
Gamma |- \x:T11.t12 \in T11->T12
Gamma |- t1 \in T11->T12
Gamma |- t2 \in T11
---------------------- (T_App)
Gamma |- t1 t2 \in T12
-------------------- (T_True)
Gamma |- true \in Bool
--------------------- (T_False)
Gamma |- false \in Bool
Gamma |- t1 \in Bool Gamma |- t2 \in T Gamma |- t3 \in T
-------------------------------------------------------- (T_If)
Gamma |- if t1 then t2 else t3 \in T
We can read the three-place relation [Gamma |- t \in T] as:
"to the term [t] we can assign the type [T] using as types for
the free variables of [t] the ones specified in the context
[Gamma]." *)
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
extend Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T11 T12 Gamma t1 t2,
Gamma |- t1 \in TArrow T11 T12 ->
Gamma |- t2 \in T11 ->
Gamma |- tapp t1 t2 \in T12
| T_True : forall Gamma,
Gamma |- ttrue \in TBool
| T_False : forall Gamma,
Gamma |- tfalse \in TBool
| T_If : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TBool ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- tif t1 t2 t3 \in T
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs"
| Case_aux c "T_App" | Case_aux c "T_True"
| Case_aux c "T_False" | Case_aux c "T_If" ].
Hint Constructors has_type.
(* ################################### *)
(** *** Examples *)
Example typing_example_1 :
empty |- tabs x TBool (tvar x) \in TArrow TBool TBool.
Proof.
apply T_Abs. apply T_Var. reflexivity. Qed.
(** Note that since we added the [has_type] constructors to the hints
database, auto can actually solve this one immediately. *)
Example typing_example_1' :
empty |- tabs x TBool (tvar x) \in TArrow TBool TBool.
Proof. auto. Qed.
(** Another example:
empty |- \x:A. \y:A->A. y (y x))
\in A -> (A->A) -> A.
*)
Example typing_example_2 :
empty |-
(tabs x TBool
(tabs y (TArrow TBool TBool)
(tapp (tvar y) (tapp (tvar y) (tvar x))))) \in
(TArrow TBool (TArrow (TArrow TBool TBool) TBool)).
Proof with auto using extend_eq.
apply T_Abs.
apply T_Abs.
eapply T_App. apply T_Var...
eapply T_App. apply T_Var...
apply T_Var...
Qed.
(** **** Exercise: 2 stars, optional (typing_example_2_full) *)
(** Prove the same result without using [auto], [eauto], or
[eapply]. *)
Example typing_example_2_full :
empty |-
(tabs x TBool
(tabs y (TArrow TBool TBool)
(tapp (tvar y) (tapp (tvar y) (tvar x))))) \in
(TArrow TBool (TArrow (TArrow TBool TBool) TBool)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (typing_example_3) *)
(** Formally prove the following typing derivation holds: *)
(**
empty |- \x:Bool->B. \y:Bool->Bool. \z:Bool.
y (x z)
\in T.
*)
Example typing_example_3 :
exists T,
empty |-
(tabs x (TArrow TBool TBool)
(tabs y (TArrow TBool TBool)
(tabs z TBool
(tapp (tvar y) (tapp (tvar x) (tvar z)))))) \in
T.
Proof with auto.
exists (TArrow (TArrow TBool TBool)
(TArrow (TArrow TBool TBool)
(TArrow TBool TBool))).
apply T_Abs.
apply T_Abs.
apply T_Abs.
apply T_App with (T11 := TBool).
apply T_Var. reflexivity.
apply T_App with (T11 := TBool).
apply T_Var. reflexivity.
apply T_Var. reflexivity.
Qed.
(** [] *)
(** We can also show that terms are _not_ typable. For example, let's
formally check that there is no typing derivation assigning a type
to the term [\x:Bool. \y:Bool, x y] -- i.e.,
~ exists T,
empty |- \x:Bool. \y:Bool, x y : T.
*)
Example typing_nonexample_1 :
~ exists T,
empty |-
(tabs x TBool
(tabs y TBool
(tapp (tvar x) (tvar y)))) \in
T.
Proof.
intros Hc. inversion Hc.
(* The [clear] tactic is useful here for tidying away bits of
the context that we're not going to need again. *)
inversion H. subst. clear H.
inversion H5. subst. clear H5.
inversion H4. subst. clear H4.
inversion H2. subst. clear H2.
inversion H5. subst. clear H5.
(* rewrite extend_neq in H1. rewrite extend_eq in H1. *)
inversion H1. Qed.
(** **** Exercise: 3 stars, optional (typing_nonexample_3) *)
(** Another nonexample:
~ (exists S, exists T,
empty |- \x:S. x x : T).
*)
Example typing_nonexample_3 :
~ (exists S, exists T,
empty |-
(tabs x S
(tapp (tvar x) (tvar x))) \in
T).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End STLC.
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
`define AND 4'b0000
`define OR 4'b0001
`define ADD 4'b0010
`define SUB 4'b0110
`define SLT 4'b0111
`define NOR 4'b1100
`include "../ALU/one_bit_alu.v"
module alu (
input [3:0] op,
input signed [31:0] a, b,
output signed [31:0] z,
output zero);
wire set;
wire [30:0] carry;
one_bit_alu alu0 (.op(op), .r(z[0 ]), .a(a[0 ]), .b(b[0 ]), .cin(1'b0 ), .cout(carry[0 ]), .less(set ));
one_bit_alu alu1 (.op(op), .r(z[1 ]), .a(a[1 ]), .b(b[1 ]), .cin(carry[0 ]), .cout(carry[1 ]), .less(1'b0));
one_bit_alu alu2 (.op(op), .r(z[2 ]), .a(a[2 ]), .b(b[2 ]), .cin(carry[1 ]), .cout(carry[2 ]), .less(1'b0));
one_bit_alu alu3 (.op(op), .r(z[3 ]), .a(a[3 ]), .b(b[3 ]), .cin(carry[2 ]), .cout(carry[3 ]), .less(1'b0));
one_bit_alu alu4 (.op(op), .r(z[4 ]), .a(a[4 ]), .b(b[4 ]), .cin(carry[3 ]), .cout(carry[4 ]), .less(1'b0));
one_bit_alu alu5 (.op(op), .r(z[5 ]), .a(a[5 ]), .b(b[5 ]), .cin(carry[4 ]), .cout(carry[5 ]), .less(1'b0));
one_bit_alu alu6 (.op(op), .r(z[6 ]), .a(a[6 ]), .b(b[6 ]), .cin(carry[5 ]), .cout(carry[6 ]), .less(1'b0));
one_bit_alu alu7 (.op(op), .r(z[7 ]), .a(a[7 ]), .b(b[7 ]), .cin(carry[6 ]), .cout(carry[7 ]), .less(1'b0));
one_bit_alu alu8 (.op(op), .r(z[8 ]), .a(a[8 ]), .b(b[8 ]), .cin(carry[7 ]), .cout(carry[8 ]), .less(1'b0));
one_bit_alu alu9 (.op(op), .r(z[9 ]), .a(a[9 ]), .b(b[9 ]), .cin(carry[8 ]), .cout(carry[9 ]), .less(1'b0));
one_bit_alu alu10 (.op(op), .r(z[10]), .a(a[10]), .b(b[10]), .cin(carry[9 ]), .cout(carry[10]), .less(1'b0));
one_bit_alu alu11 (.op(op), .r(z[11]), .a(a[11]), .b(b[11]), .cin(carry[10]), .cout(carry[11]), .less(1'b0));
one_bit_alu alu12 (.op(op), .r(z[12]), .a(a[12]), .b(b[12]), .cin(carry[11]), .cout(carry[12]), .less(1'b0));
one_bit_alu alu13 (.op(op), .r(z[13]), .a(a[13]), .b(b[13]), .cin(carry[12]), .cout(carry[13]), .less(1'b0));
one_bit_alu alu14 (.op(op), .r(z[14]), .a(a[14]), .b(b[14]), .cin(carry[13]), .cout(carry[14]), .less(1'b0));
one_bit_alu alu15 (.op(op), .r(z[15]), .a(a[15]), .b(b[15]), .cin(carry[14]), .cout(carry[15]), .less(1'b0));
one_bit_alu alu16 (.op(op), .r(z[16]), .a(a[16]), .b(b[16]), .cin(carry[15]), .cout(carry[16]), .less(1'b0));
one_bit_alu alu17 (.op(op), .r(z[17]), .a(a[17]), .b(b[17]), .cin(carry[16]), .cout(carry[17]), .less(1'b0));
one_bit_alu alu18 (.op(op), .r(z[18]), .a(a[18]), .b(b[18]), .cin(carry[17]), .cout(carry[18]), .less(1'b0));
one_bit_alu alu19 (.op(op), .r(z[19]), .a(a[19]), .b(b[19]), .cin(carry[18]), .cout(carry[19]), .less(1'b0));
one_bit_alu alu20 (.op(op), .r(z[20]), .a(a[20]), .b(b[20]), .cin(carry[19]), .cout(carry[20]), .less(1'b0));
one_bit_alu alu21 (.op(op), .r(z[21]), .a(a[21]), .b(b[21]), .cin(carry[20]), .cout(carry[21]), .less(1'b0));
one_bit_alu alu22 (.op(op), .r(z[22]), .a(a[22]), .b(b[22]), .cin(carry[21]), .cout(carry[22]), .less(1'b0));
one_bit_alu alu23 (.op(op), .r(z[23]), .a(a[23]), .b(b[23]), .cin(carry[22]), .cout(carry[23]), .less(1'b0));
one_bit_alu alu24 (.op(op), .r(z[24]), .a(a[24]), .b(b[24]), .cin(carry[23]), .cout(carry[24]), .less(1'b0));
one_bit_alu alu25 (.op(op), .r(z[25]), .a(a[25]), .b(b[25]), .cin(carry[24]), .cout(carry[25]), .less(1'b0));
one_bit_alu alu26 (.op(op), .r(z[26]), .a(a[26]), .b(b[26]), .cin(carry[25]), .cout(carry[26]), .less(1'b0));
one_bit_alu alu27 (.op(op), .r(z[27]), .a(a[27]), .b(b[27]), .cin(carry[26]), .cout(carry[27]), .less(1'b0));
one_bit_alu alu28 (.op(op), .r(z[28]), .a(a[28]), .b(b[28]), .cin(carry[27]), .cout(carry[28]), .less(1'b0));
one_bit_alu alu29 (.op(op), .r(z[29]), .a(a[29]), .b(b[29]), .cin(carry[28]), .cout(carry[29]), .less(1'b0));
one_bit_alu alu30 (.op(op), .r(z[30]), .a(a[30]), .b(b[30]), .cin(carry[29]), .cout(carry[30]), .less(1'b0));
one_bit_alu alu31 (.op(op), .r(z[31]), .a(a[31]), .b(b[31]), .cin(carry[30]), .set (set ), .less(1'b0));
nor (zero, z[0 ], z[1 ], z[2 ], z[3 ], z[4 ], z[5 ], z[6 ], z[7 ], z[8 ], z[9 ],
z[10], z[11], z[12], z[13], z[14], z[15], z[16], z[17], z[18], z[19],
z[20], z[21], z[22], z[23], z[24], z[25], z[26], z[27], z[28], z[29],
z[30], z[31]);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : PIO_TO_CTRL.v
// Version : 2.4
//--
//-- Description: Turn-off Control Unit.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module PIO_TO_CTRL (
clk,
rst_n,
req_compl_i,
compl_done_i,
cfg_to_turnoff,
cfg_turnoff_ok
);
input clk;
input rst_n;
input req_compl_i;
input compl_done_i;
input cfg_to_turnoff;
output cfg_turnoff_ok;
reg trn_pending;
reg cfg_turnoff_ok;
// * Check if completion is pending
always @ ( posedge clk or negedge rst_n ) begin
if (!rst_n ) begin
trn_pending <= 0;
end else begin
if (!trn_pending && req_compl_i)
trn_pending <= 1'b1;
else if (compl_done_i)
trn_pending <= 1'b0;
end
end
// * Turn-off OK if requested and no transaction is pending
always @ ( posedge clk or negedge rst_n ) begin
if (!rst_n ) begin
cfg_turnoff_ok <= 1'b0;
end else begin
if ( cfg_to_turnoff && !trn_pending)
cfg_turnoff_ok <= 1'b1;
else
cfg_turnoff_ok <= 1'b0;
end
end
endmodule // PIO_TO_CTRL
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: arriagx_pmem.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module arriagx_pmem (
address,
byteena,
clken,
clock,
data,
wren,
q);
input [11:0] address;
input [1:0] byteena;
input clken;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clocken0 (clken),
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena),
.address_a (address),
.data_a (data),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Arria GX",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[11..0]
// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0]
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_pmem.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_pmem.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_pmem.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_pmem.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_pmem_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_pmem_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_pmem_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_pmem_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns/1ps
`default_nettype none
module main;
reg p4VDC = 1;
wire p4VSW;
reg GND = 0;
reg SIM_RST = 1;
reg SIM_CLK = 1;
reg BLKUPL_n = 1; //input
reg BMGXM = 0; //input
reg BMGXP = 0; //input
reg BMGYM = 0; //input
reg BMGYP = 0; //input
reg BMGZM = 0; //input
reg BMGZP = 0; //input
reg CAURST = 0; //input
reg CDUFAL = 0; //input
reg CDUXM = 0; //input
reg CDUXP = 0; //input
reg CDUYM = 0; //input
reg CDUYP = 0; //input
reg CDUZM = 0; //input
reg CDUZP = 0; //input
reg CLOCK = 0;
reg CTLSAT = 0; //input
wire DBLTST; //monitor input
wire DKBSNC; //input
wire DKEND; //input
wire DKSTRT; //input
wire DOSCAL; //monitor input
reg FLTOUT = 0;
reg FREFUN = 0; //input
reg GATEX_n = 1; //input
reg GATEY_n = 1; //input
reg GATEZ_n = 1; //input
reg GCAPCL = 0; //input
reg GUIREL = 0; //input
reg HOLFUN = 0; //input
reg IMUCAG = 0; //input
reg IMUFAL = 0; //input
reg IMUOPR = 0; //input
reg IN3008 = 0; //input
reg IN3212 = 0; //input
reg IN3213 = 0; //input
reg IN3214 = 0; //input
reg IN3216 = 0; //input
reg IN3301 = 0; //input
reg ISSTOR = 0; //input
reg LEMATT = 0; //input
reg LFTOFF = 0; //input
reg LRIN0 = 0; //input
reg LRIN1 = 0; //input
reg LRRLSC = 0; //input
reg LVDAGD = 0; //input
reg MAINRS = 0; //input
wire MAMU; //monitor input
reg MANmP = 0; //input
reg MANmR = 0; //input
reg MANmY = 0; //input
reg MANpP = 0; //input
reg MANpR = 0; //input
reg MANpY = 0; //input
reg MARK = 0; //input
wire MDT01; //monitor input
wire MDT02; //monitor input
wire MDT03; //monitor input
wire MDT04; //monitor input
wire MDT05; //monitor input
wire MDT06; //monitor input
wire MDT07; //monitor input
wire MDT08; //monitor input
wire MDT09; //monitor input
wire MDT10; //monitor input
wire MDT11; //monitor input
wire MDT12; //monitor input
wire MDT13; //monitor input
wire MDT14; //monitor input
wire MDT15; //monitor input
wire MDT16; //monitor input
reg MKEY1 = 0; //input
reg MKEY2 = 0; //input
reg MKEY3 = 0; //input
reg MKEY4 = 0; //input
reg MKEY5 = 0; //input
wire MLDCH; //monitor input
wire MLOAD; //monitor input
wire MNHNC; //monitor input
wire MNHRPT; //monitor input
wire MNHSBF; //monitor input
reg MNIMmP = 0; //input
reg MNIMmR = 0; //input
reg MNIMmY = 0; //input
reg MNIMpP = 0; //input
reg MNIMpR = 0; //input
reg MNIMpY = 0; //input
wire MONPAR; //monitor input
wire MONWBK; //monitor input
wire MRDCH; //monitor input
wire MREAD; //monitor input
reg MRKREJ = 0; //input
reg MRKRST = 0; //input
wire MSTP; //monitor input
wire MSTRT; //monitor input
wire MTCSAI; //monitor input
reg MYCLMP = 0;
reg NAVRST = 0; //input
wire NHALGA; //monitor input
reg NHVFAL = 0; //input
reg NKEY1 = 0; //input
reg NKEY2 = 0; //input
reg NKEY3 = 0; //input
reg NKEY4 = 0; //input
reg NKEY5 = 0; //input
reg OPCDFL = 0; //input
reg OPMSW2 = 0; //input
reg OPMSW3 = 0; //input
reg PCHGOF = 0; //input
wire PIPAXm; //input
wire PIPAXp; //input
wire PIPAYm; //input
wire PIPAYp; //input
wire PIPAZm; //input
wire PIPAZp; //input
reg ROLGOF = 0; //input
reg RRIN0 = 0; //input
reg RRIN1 = 0; //input
reg RRPONA = 0; //input
reg RRRLSC = 0; //input
reg S4BSAB = 0; //input
reg SBYBUT = 0; //input
reg SCAFAL = 0;
reg SHAFTM = 0; //input
reg SHAFTP = 0; //input
reg SIGNX = 0; //input
reg SIGNY = 0; //input
reg SIGNZ = 0; //input
reg SMSEPR = 0; //input
reg SPSRDY = 0; //input
reg STRPRS = 0; //input
reg STRT2 = 0;
reg TEMPIN = 0; //input
reg TRANmX = 0; //input
reg TRANmY = 0; //input
reg TRANmZ = 0; //input
reg TRANpX = 0; //input
reg TRANpY = 0; //input
reg TRANpZ = 0; //input
reg TRNM = 0; //input
reg TRNP = 0; //input
reg TRST10 = 0; //input
reg TRST9 = 0; //input
reg ULLTHR = 0; //input
reg UPL0 = 0; //input
reg UPL1 = 0; //input
reg VFAIL = 0;
reg XLNK0 = 0; //input
reg XLNK1 = 0; //input
reg ZEROP = 0; //input
reg n2FSFAL = 0;
wire CDUXDP; //output
wire CDUXDM; //output
wire CDUYDP; //output
wire CDUYDM; //output
wire CDUZDP; //output
wire CDUZDM; //output
wire CLK; //output
wire COMACT; //output
wire DKDATA; // output
wire KYRLS; //output
wire MBR1; //monitor output
wire MBR2; //monitor output
wire MCTRAL_n; //monitor output
wire MGOJAM; //monitor output
wire MGP_n; //monitor output
wire MIIP; //monitor output
wire MINHL; //monitor output
wire MINKL; //monitor output
wire MNISQ; //monitor output
wire MON800; //monitor output
wire MONWT; //monitor output
wire MOSCAL_n; //monitor output
wire MPAL_n; //monitor output
wire MPIPAL_n; //monitor output
wire MRAG; //monitor output
wire MRCH; //monitor output
wire MREQIN; //monitor output
wire MRGG; //monitor output
wire MRLG; //monitor output
wire MRPTAL_n; //monitor output
wire MRSC; //monitor output
wire MRULOG; //monitor output
wire MSBSTP; //monitor input
wire MSCAFL_n; //monitor output
wire MSCDBL_n; //monitor output
wire MSP; //monitor output
wire MSQ10; //monitor output
wire MSQ11; //monitor output
wire MSQ12; //monitor output
wire MSQ13; //monitor output
wire MSQ14; //monitor output
wire MSQ16; //monitor output
wire MSQEXT; //monitor output
wire MST1; //monitor output
wire MST2; //monitor output
wire MST3; //monitor output
wire MSTPIT_n; //monitor output
wire MT01; //monitor output
wire MT02; //monitor output
wire MT03; //monitor output
wire MT04; //monitor output
wire MT05; //monitor output
wire MT06; //monitor output
wire MT07; //monitor output
wire MT08; //monitor output
wire MT09; //monitor output
wire MT10; //monitor output
wire MT11; //monitor output
wire MT12; //monitor output
wire MTCAL_n; //monitor output
wire MTCSA_n; //monitor output
wire MVFAIL_n; //monitor output
wire MWAG; //monitor output
wire MWARNF_n; //monitor output
wire MWATCH_n; //monitor output
wire MWBBEG; //monitor output
wire MWBG; //monitor output
wire MWCH; //monitor output
wire MWEBG; //monitor output
wire MWFBG; //monitor output
wire MWG; //monitor output
wire MWL01; //monitor output
wire MWL02; //monitor output
wire MWL03; //monitor output
wire MWL04; //monitor output
wire MWL05; //monitor output
wire MWL06; //monitor output
wire MWL07; //monitor output
wire MWL08; //monitor output
wire MWL09; //monitor output
wire MWL10; //monitor output
wire MWL11; //monitor output
wire MWL12; //monitor output
wire MWL13; //monitor output
wire MWL14; //monitor output
wire MWL15; //monitor output
wire MWL16; //monitor output
wire MWLG; //monitor output
wire MWQG; //monitor output
wire MWSG; //monitor output
wire MWYG; //monitor output
wire MWZG; //monitor output
wire OPEROR; //output
wire PIPASW; //output
wire PIPDAT; //output
wire RESTRT; //output
wire RLYB01; //output
wire RLYB02; //output
wire RLYB03; //output
wire RLYB04; //output
wire RLYB05; //output
wire RLYB06; //output
wire RLYB07; //output
wire RLYB08; //output
wire RLYB09; //output
wire RLYB10; //output
wire RLYB11; //output
wire RYWD12; //output
wire RYWD13; //output
wire RYWD14; //output
wire RYWD16; //output
wire SBYLIT; //output
wire SBYREL_n;
wire TMPCAU; //output
wire UPLACT; //output
wire VNFLSH; //output
assign p4VSW = p4VDC && SBYREL_n;
// PIPA spoofing -- simulate 3-3 moding on PIPA inputs, synced with PIPDAT
// and counting on PIPASW
reg [2:0] moding_counter = 3'b0;
always @(posedge PIPASW) begin
moding_counter = moding_counter + 3'b1;
if (moding_counter == 3'd6) begin
moding_counter = 3'b0;
end
end
assign PIPAXm = PIPDAT && (moding_counter >= 3'd3);
assign PIPAYm = PIPDAT && (moding_counter >= 3'd3);
assign PIPAZm = PIPDAT && (moding_counter >= 3'd3);
assign PIPAXp = PIPDAT && (moding_counter < 3'd3);
assign PIPAYp = PIPDAT && (moding_counter < 3'd3);
assign PIPAZp = PIPDAT && (moding_counter < 3'd3);
// PCM simulation
reg [4:0] pcm_counter = 5'd19;
reg dlk_clk = 1'b0;
reg [9:0] dlk_counter = 10'd1023;
always @(posedge CLK) begin
if (pcm_counter == 5'd20) begin
pcm_counter <= 5'b0;
end else begin
pcm_counter <= pcm_counter + 5'b1;
if (pcm_counter == 5'd0) begin
dlk_clk <= 1'b1;
dlk_counter <= dlk_counter + 10'b1;
end else if (pcm_counter == 5'd4) begin
dlk_clk <= 1'b0;
end
end
end
assign DKSTRT = dlk_clk && (dlk_counter == 10'd0);
assign DKBSNC = dlk_clk && (dlk_counter > 10'd0) && (dlk_counter < 10'd41);
assign DKEND = dlk_clk && (dlk_counter == 10'd41);
always #244.140625 CLOCK = !CLOCK;
`ifdef TARGET_FPGA
always #10 SIM_CLK = !SIM_CLK;
wire EPCS_CSN;
wire EPCS_ASDI;
wire EPCS_DCLK;
reg EPCS_DATA = 0;
fpga_agc AGC(VCC, GND, SIM_RST, SIM_CLK, ALGA, C24A, C25A, C26A, C27A, C30A, C37P, C40P, C41P, C42P, C43P, C44P, CA2_n, CA3_n, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CDUSTB_n, CH01, CH02, CH03, CH04, CH05, CH06, CH07, CH08, CH09, CH10, CH11, CH12, CH13, CH14, CH16, CHINC, CHINC_n, CLOCK, DINC, DINC_n, DLKPLS, E5, E6, E7_n, EPCS_DATA, FETCH0, FETCH0_n, FETCH1, HNDRPT, INCSET_n, INKL, INKL_n, INOTLD, KYRPT1, KYRPT2, MAMU, MCDU, MDT01, MDT02, MDT03, MDT04, MDT05, MDT06, MDT07, MDT08, MDT09, MDT10, MDT11, MDT12, MDT13, MDT14, MDT15, MDT16, MINC, MKRPT, MNHRPT, MNHSBF, MONPAR, MONPCH, MONWBK, MON_n, MSTP, MSTRTP, MTCSAI, OVNHRP, PCDU, PIPPLS_n, RADRPT, RCHAT_n, RCHBT_n, SBY, SHANC_n, SHIFT, SHIFT_n, STFET1_n, STORE1_n, STRT1, STRT2, UPRUPT, ZOUT_n, EPCS_ASDI, EPCS_DCLK, EPCS_CSN, MGOJAM, MT01, MT02, MT03, MT04, MT05, MT06, MT07, MT08, MT09, MT10, MT11, MT12);
`else
ch77_alarm_box RestartMonitor(SIM_RST, SIM_CLK, p4VSW, GND, MDT01, MT01, MDT02, MT05, MDT03, MT12, MDT04, MWL01, MDT05, MWL02, MDT06, MWL03, MDT07, MWL04, MDT08, MWL05, MDT09, MWL06, MDT10, MRCH, MDT11, MWCH, MDT12, MWSG, MDT13, MPAL_n, MDT14, MTCAL_n, MDT15, MRPTAL_n, MDT16, MWATCH_n, MNHSBF, MVFAIL_n, MNHNC, MCTRAL_n, MNHRPT, MSCAFL_n, MTCSAI, MSCDBL_n, MSTRT, MAMU, MSTP, MSBSTP, MRDCH, MLDCH, MONPAR, MONWBK, MLOAD, MREAD, NHALGA, DOSCAL, DBLTST);
agc AGC(p4VDC, p4VSW, GND, SIM_RST, SIM_CLK, BLKUPL_n, BMGXM, BMGXP, BMGYM, BMGYP, BMGZM, BMGZP, CAURST, CDUFAL, CDUXM, CDUXP, CDUYM, CDUYP, CDUZM, CDUZP, CLOCK, CTLSAT, DBLTST, DKBSNC, DKEND, DKSTRT, DOSCAL, FLTOUT, FREFUN, GATEX_n, GATEY_n, GATEZ_n, GCAPCL, GUIREL, HOLFUN, IMUCAG, IMUFAL, IMUOPR, IN3008, IN3212, IN3213, IN3214, IN3216, IN3301, ISSTOR, LEMATT, LFTOFF, LRIN0, LRIN1, LRRLSC, LVDAGD, MAINRS, MAMU, MANmP, MANmR, MANmY, MANpP, MANpR, MANpY, MARK, MDT01, MDT02, MDT03, MDT04, MDT05, MDT06, MDT07, MDT08, MDT09, MDT10, MDT11, MDT12, MDT13, MDT14, MDT15, MDT16, MKEY1, MKEY2, MKEY3, MKEY4, MKEY5, MLDCH, MLOAD, MNHNC, MNHRPT, MNHSBF, MNIMmP, MNIMmR, MNIMmY, MNIMpP, MNIMpR, MNIMpY, MONPAR, MONWBK, MRDCH, MREAD, MRKREJ, MRKRST, MSTP, MSTRT, MTCSAI, MYCLMP, NAVRST, NHALGA, NHVFAL, NKEY1, NKEY2, NKEY3, NKEY4, NKEY5, OPCDFL, OPMSW2, OPMSW3, PCHGOF, PIPAXm, PIPAXp, PIPAYm, PIPAYp, PIPAZm, PIPAZp, ROLGOF, RRIN0, RRIN1, RRPONA, RRRLSC, S4BSAB, SBYBUT, SCAFAL, SHAFTM, SHAFTP, SIGNX, SIGNY, SIGNZ, SMSEPR, SPSRDY, STRPRS, STRT2, TEMPIN, TRANmX, TRANmY, TRANmZ, TRANpX, TRANpY, TRANpZ, TRNM, TRNP, TRST10, TRST9, ULLTHR, UPL0, UPL1, VFAIL, XLNK0, XLNK1, ZEROP, n2FSFAL, CDUXDM, CDUXDP, CDUYDM, CDUYDP, CDUZDM, CDUZDP, CLK, COMACT, DKDATA, KYRLS, MBR1, MBR2, MCTRAL_n, MGOJAM, MGP_n, MIIP, MINHL, MINKL, MNISQ, MON800, MONWT, MOSCAL_n, MPAL_n, MPIPAL_n, MRAG, MRCH, MREQIN, MRGG, MRLG, MRPTAL_n, MRSC, MRULOG, MSCAFL_n, MSCDBL_n, MSP, MSQ10, MSQ11, MSQ12, MSQ13, MSQ14, MSQ16, MSQEXT, MST1, MST2, MST3, MSTPIT_n, MT01, MT02, MT03, MT04, MT05, MT06, MT07, MT08, MT09, MT10, MT11, MT12, MTCAL_n, MTCSA_n, MVFAIL_n, MWAG, MWARNF_n, MWATCH_n, MWBBEG, MWBG, MWCH, MWEBG, MWFBG, MWG, MWL01, MWL02, MWL03, MWL04, MWL05, MWL06, MWL07, MWL08, MWL09, MWL10, MWL11, MWL12, MWL13, MWL14, MWL15, MWL16, MWLG, MWQG, MWSG, MWYG, MWZG, OPEROR, PIPASW, PIPDAT, RESTRT, RLYB01, RLYB02, RLYB03, RLYB04, RLYB05, RLYB06, RLYB07, RLYB08, RLYB09, RLYB10, RLYB11, RYWD12, RYWD13, RYWD14, RYWD16, SBYLIT, SBYREL_n, TMPCAU, UPLACT, VNFLSH);
`endif
initial begin
$dumpfile("dump.lxt");
$dumpvars(0, main);
#5000 SIM_RST = 0;
#400000000 $finish;
end
endmodule
|
//======================================================================
//
// sha256_axi4.v
// -------------
// Top level wrapper for the SHA-256 hash function providing
// an AXI4 Slave interface.
//
//
// Author: Sanjay A Menon
// Copyright (c) 2020.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module sha256_axi4 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 8
)
(
// Users to add ports here
// User ports ends
output wire hash_complete,
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
sha256_axi4_slave # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) sha256_axi4_slave_inst (
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
//.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam CTRL_MODE_BIT = 2;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam STATUS_VALID_BIT = 1;
localparam ADDR_BLOCK0 = 8'h10;
localparam ADDR_BLOCK15 = 8'h1f;
localparam ADDR_DIGEST0 = 8'h20;
localparam ADDR_DIGEST7 = 8'h27;
localparam CORE_NAME0 = 32'h73686132; // "sha2"
localparam CORE_NAME1 = 32'h2d323536; // "-256"
localparam CORE_VERSION = 32'h312e3830; // "1.80"
localparam MODE_SHA_224 = 1'h0;
localparam MODE_SHA_256 = 1'h1;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg init_reg;
reg init_new;
reg next_reg;
reg next_new;
reg mode_reg;
reg mode_new;
reg mode_we;
reg ready_reg;
reg [31 : 0] block_reg [0 : 15];
reg block_we;
reg [255 : 0] digest_reg;
reg digest_valid_reg;
reg hash_complete_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire core_ready;
wire [511 : 0] core_block;
wire [255 : 0] core_digest;
wire core_digest_valid;
reg [31 : 0] tmp_read_data;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign core_block = {block_reg[00], block_reg[01], block_reg[02], block_reg[03],
block_reg[04], block_reg[05], block_reg[06], block_reg[07],
block_reg[08], block_reg[09], block_reg[10], block_reg[11],
block_reg[12], block_reg[13], block_reg[14], block_reg[15]};
assign s00_axi_rdata = tmp_read_data;
assign hash_complete = hash_complete_reg;
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
sha256_core core(
.clk(s00_axi_aclk),
.reset_n(s00_axi_aresetn),
.init(init_reg),
.next(next_reg),
.mode(mode_reg),
.block(core_block),
.ready(core_ready),
.digest(core_digest),
.digest_valid(core_digest_valid)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge s00_axi_aclk or negedge s00_axi_aresetn)
begin : reg_update
integer i;
if (!s00_axi_aresetn)
begin
for (i = 0 ; i < 16 ; i = i + 1)
block_reg[i] <= 32'h0;
init_reg <= 1'h0;
next_reg <= 1'h0;
ready_reg <= 1'h0;
mode_reg <= MODE_SHA_256;
digest_reg <= 256'h0;
hash_complete_reg <= 1'h0;
digest_valid_reg <= 1'h0;
end
else
begin
ready_reg <= core_ready;
digest_valid_reg <= core_digest_valid;
init_reg <= init_new;
next_reg <= next_new;
if (mode_we)
mode_reg <= mode_new;
if (core_digest_valid)
begin
digest_reg <= core_digest;
hash_complete_reg <= 1'h1;
end
if (block_we)
begin
hash_complete_reg <= 1'h0;
block_reg[s00_axi_awaddr[3 : 0]] <= s00_axi_wdata;
end
end
end // reg_update
//----------------------------------------------------------------
// api_logic
//
// Implementation of the api logic. If s00_axi_awprot is enabled will either
// try to write to or read from the internal registers.
//----------------------------------------------------------------
always @*
begin : api_logic
init_new = 0;
next_new = 0;
mode_new = 0;
mode_we = 0;
block_we = 0;
tmp_read_data = 32'h0;
if (s00_axi_awprot)
begin
if (s00_axi_awvalid)
begin
if (s00_axi_awaddr == ADDR_CTRL)
begin
init_new = s00_axi_wdata[CTRL_INIT_BIT];
next_new = s00_axi_wdata[CTRL_NEXT_BIT];
mode_new = s00_axi_wdata[CTRL_MODE_BIT];
mode_we = 1;
end
if ((s00_axi_awaddr >= ADDR_BLOCK0) && (s00_axi_awaddr <= ADDR_BLOCK15))
begin
block_we = 1;
end
end // if (s00_axi_awvalid)
else
begin
if ((s00_axi_araddr >= ADDR_BLOCK0) && (s00_axi_araddr <= ADDR_BLOCK15))
tmp_read_data = block_reg[s00_axi_awaddr[3 : 0]];
if ((s00_axi_araddr >= ADDR_DIGEST0) && (s00_axi_araddr <= ADDR_DIGEST7))
begin
tmp_read_data = digest_reg[(7 - (s00_axi_araddr - ADDR_DIGEST0)) * 32 +: 32] ;
end
case (s00_axi_araddr)
// Read operations.
ADDR_NAME0:
tmp_read_data = CORE_NAME0;
ADDR_NAME1:
tmp_read_data = CORE_NAME1;
ADDR_VERSION:
tmp_read_data = CORE_VERSION;
ADDR_CTRL:
tmp_read_data = {29'h0, mode_reg, next_reg, init_reg};
ADDR_STATUS:
tmp_read_data = {30'h0, digest_valid_reg, ready_reg};
default:
begin
end
endcase // case (s00_axi_awaddr)
end
end
end // addr_decoder
endmodule // sha256_axi4
//======================================================================
// EOF sha256_axi4.v
//======================================================================
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={650.000000} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525.000000} readRate={0.5} writeRate={0.5} /><IO interface={Timer} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP0} dataWidth={64} clockFreq={100} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=525.000000, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=14, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.75, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=-0.073, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=-0.034, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.03, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.082, PCW_UIPARAM_DDR_BOARD_DELAY0=0.176, PCW_UIPARAM_DDR_BOARD_DELAY1=0.159, PCW_UIPARAM_DDR_BOARD_DELAY2=0.162, PCW_UIPARAM_DDR_BOARD_DELAY3=0.187, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=27.85, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=22.87, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=22.9, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=29.9, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=27, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=22.8, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=24, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=30.45, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=20.6, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=20.6, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=20.6, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=20.6, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=165, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=165, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=165, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=165, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=50.000000, PCW_APU_PERIPHERAL_FREQMHZ=650.000000, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100.000000, PCW_FPGA1_PERIPHERAL_FREQMHZ=175.000000, PCW_FPGA2_PERIPHERAL_FREQMHZ=12.288000, PCW_FPGA3_PERIPHERAL_FREQMHZ=100.000000, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=26, PCW_IOPLL_CTRL_FBDIV=20, PCW_DDRPLL_CTRL_FBDIV=21, PCW_CPU_CPU_PLL_FREQMHZ=1300.000, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1050.000, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=1, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=100, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41K128M16 JT-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=0, PCW_SD0_GRP_CD_ENABLE=0, PCW_SD0_GRP_WP_ENABLE=0, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=MIO 30 .. 31, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=0, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=1, PCW_GPIO_MIO_GPIO_ENABLE=0, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=DDR PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=ARM PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *)
(* HW_HANDOFF = "block_design_processing_system7_0_0.hwdef" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0,
// Enable and disable AFI Secure transaction
parameter C_USE_AXI_NONSECURE = 0,
//parameters for HP enable ports
parameter C_USE_S_AXI_HP0 = 0,
parameter C_USE_S_AXI_HP1 = 0,
parameter C_USE_S_AXI_HP2 = 0,
parameter C_USE_S_AXI_HP3 = 0,
//parameters for GP and ACP enable ports */
parameter C_USE_M_AXI_GP0 = 0,
parameter C_USE_M_AXI_GP1 = 0,
parameter C_USE_S_AXI_GP0 = 0,
parameter C_USE_S_AXI_GP1 = 0,
parameter C_USE_S_AXI_ACP = 0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN = 'b0,
output reg ENET0_GMII_TX_ER = 'b0,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN = 'b0,
output reg ENET1_GMII_TX_ER = 'b0,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
// Wires for connecting to the PS7
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
wire FCLK_CLK0_temp;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire S_AXI_HP0_ACLK_temp;
wire S_AXI_HP1_ACLK_temp;
wire S_AXI_HP2_ACLK_temp;
wire S_AXI_HP3_ACLK_temp;
wire M_AXI_GP0_ACLK_temp;
wire M_AXI_GP1_ACLK_temp;
wire S_AXI_GP0_ACLK_temp;
wire S_AXI_GP1_ACLK_temp;
wire S_AXI_ACP_ACLK_temp;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
(* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
(* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
else
begin
always @*
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= 1'b0;
TRACE_DATA_PIPE[j-1] <= 1'b0;
end
TRACE_CLK_OUT <= 1'b0;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
else
always@*
begin
ENET0_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= 'b0;
ENET0_GMII_CRS_i <= 'b0;
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET0_GMII_RXD_i <= 0;
ENET0_GMII_RX_DV_i <= 0;
ENET0_GMII_RX_ER_i <= 0;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
else
begin
always@*
begin
ENET1_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET1_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET1_GMII_COL_i <= 0;
ENET1_GMII_CRS_i <= 0;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET1_GMII_RXD_i <= 'b0;
ENET1_GMII_RX_DV_i <= 'b0;
ENET1_GMII_RX_ER_i <= 'b0;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
else
begin
assign FTMD_TRACEIN_DATA_i = 1'b0;
assign FTMD_TRACEIN_VALID_i = 1'b0;
assign FTMD_TRACEIN_ATID_i = 1'b0;
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
else
begin
assign PJTAG_TDO = 1'b0;
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
assign FCLK_CLK0 = FCLK_CLK0_temp;
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
// Connect FCLK in case of disable the AXI port for non Secure Transaction
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin
assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin
assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin
assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin
assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP3_ACLK_temp = S_AXI_HP3_ACLK;
end
endgenerate
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin
assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin
assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin
assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin
assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin
assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK;
end
endgenerate
//END
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), // (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK_temp),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_data;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (ram_data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_data;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (ram_data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_nios2_oci_debug (
// inputs:
clk,
dbrk_break,
debugreq,
hbreak_enabled,
jdo,
jrst_n,
ocireg_ers,
ocireg_mrs,
reset,
st_ready_test_idle,
take_action_ocimem_a,
take_action_ocireg,
xbrk_break,
// outputs:
debugack,
monitor_error,
monitor_go,
monitor_ready,
oci_hbreak_req,
resetlatch,
resetrequest
)
;
output debugack;
output monitor_error;
output monitor_go;
output monitor_ready;
output oci_hbreak_req;
output resetlatch;
output resetrequest;
input clk;
input dbrk_break;
input debugreq;
input hbreak_enabled;
input [ 37: 0] jdo;
input jrst_n;
input ocireg_ers;
input ocireg_mrs;
input reset;
input st_ready_test_idle;
input take_action_ocimem_a;
input take_action_ocireg;
input xbrk_break;
reg break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire debugack;
reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire oci_hbreak_req;
wire reset_sync;
reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire unxcomplemented_resetxx0;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (clk),
.din (reset),
.dout (reset_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
break_on_reset <= 1'b0;
resetrequest <= 1'b0;
jtag_break <= 1'b0;
end
else if (take_action_ocimem_a)
begin
resetrequest <= jdo[22];
jtag_break <= jdo[21] ? 1
: jdo[20] ? 0
: jtag_break;
break_on_reset <= jdo[19] ? 1
: jdo[18] ? 0
: break_on_reset;
resetlatch <= jdo[24] ? 0 : resetlatch;
end
else if (reset_sync)
begin
jtag_break <= break_on_reset;
resetlatch <= 1;
end
else if (debugreq & ~debugack & break_on_reset)
jtag_break <= 1'b1;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
monitor_ready <= 1'b0;
monitor_error <= 1'b0;
monitor_go <= 1'b0;
end
else
begin
if (take_action_ocimem_a && jdo[25])
monitor_ready <= 1'b0;
else if (take_action_ocireg && ocireg_mrs)
monitor_ready <= 1'b1;
if (take_action_ocimem_a && jdo[25])
monitor_error <= 1'b0;
else if (take_action_ocireg && ocireg_ers)
monitor_error <= 1'b1;
if (take_action_ocimem_a && jdo[23])
monitor_go <= 1'b1;
else if (st_ready_test_idle)
monitor_go <= 1'b0;
end
end
assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq;
assign debugack = ~hbreak_enabled;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input [ 7: 0] address;
input [ 3: 0] byteenable;
input clock;
input [ 31: 0] data;
input reset_req;
input wren;
wire clocken;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign clocken = ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clock),
.clocken0 (clocken),
.data_a (data),
.q_a (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 256,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 8;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_nios2_ocimem (
// inputs:
address,
byteenable,
clk,
debugaccess,
jdo,
jrst_n,
read,
reset_req,
take_action_ocimem_a,
take_action_ocimem_b,
take_no_action_ocimem_a,
write,
writedata,
// outputs:
MonDReg,
ociram_readdata,
waitrequest
)
;
output [ 31: 0] MonDReg;
output [ 31: 0] ociram_readdata;
output waitrequest;
input [ 8: 0] address;
input [ 3: 0] byteenable;
input clk;
input debugaccess;
input [ 37: 0] jdo;
input jrst_n;
input read;
input reset_req;
input take_action_ocimem_a;
input take_action_ocimem_b;
input take_no_action_ocimem_a;
input write;
input [ 31: 0] writedata;
reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 8: 0] MonARegAddrInc;
wire MonARegAddrIncAccessingRAM;
reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire avalon_ram_wr;
wire [ 31: 0] cfgrom_readdata;
reg jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 7: 0] ociram_addr;
wire [ 3: 0] ociram_byteenable;
wire [ 31: 0] ociram_readdata;
wire [ 31: 0] ociram_wr_data;
wire ociram_wr_en;
reg waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
jtag_rd <= 1'b0;
jtag_rd_d1 <= 1'b0;
jtag_ram_wr <= 1'b0;
jtag_ram_rd <= 1'b0;
jtag_ram_rd_d1 <= 1'b0;
jtag_ram_access <= 1'b0;
MonAReg <= 0;
MonDReg <= 0;
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else
begin
if (take_no_action_ocimem_a)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
jtag_rd <= 1'b1;
jtag_ram_rd <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else if (take_action_ocimem_a)
begin
MonAReg[10 : 2] <= { jdo[17],
jdo[33 : 26] };
jtag_rd <= 1'b1;
jtag_ram_rd <= ~jdo[17];
jtag_ram_access <= ~jdo[17];
end
else if (take_action_ocimem_b)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
MonDReg <= jdo[34 : 3];
jtag_ram_wr <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else
begin
jtag_rd <= 0;
jtag_ram_wr <= 0;
jtag_ram_rd <= 0;
jtag_ram_access <= 0;
if (jtag_rd_d1)
MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata;
end
jtag_rd_d1 <= jtag_rd;
jtag_ram_rd_d1 <= jtag_ram_rd;
if (~waitrequest)
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else if (write)
waitrequest <= ~address[8] & jtag_ram_access;
else if (read)
begin
avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access);
waitrequest <= ~avalon_ociram_readdata_ready;
end
else
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
end
end
assign MonARegAddrInc = MonAReg[10 : 2]+1;
assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8];
assign avalon_ram_wr = write & ~address[8] & debugaccess;
assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0];
assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata;
assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable;
assign ociram_wr_en = jtag_ram_access ? jtag_ram_wr : avalon_ram_wr;
//limbus_nios2_qsys_0_ociram_sp_ram, which is an nios_sp_ram
limbus_nios2_qsys_0_ociram_sp_ram_module limbus_nios2_qsys_0_ociram_sp_ram
(
.address (ociram_addr),
.byteenable (ociram_byteenable),
.clock (clk),
.data (ociram_wr_data),
.q (ociram_readdata),
.reset_req (reset_req),
.wren (ociram_wr_en)
);
//synthesis translate_off
`ifdef NO_PLI
defparam limbus_nios2_qsys_0_ociram_sp_ram.lpm_file = "limbus_nios2_qsys_0_ociram_default_contents.dat";
`else
defparam limbus_nios2_qsys_0_ociram_sp_ram.lpm_file = "limbus_nios2_qsys_0_ociram_default_contents.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam limbus_nios2_qsys_0_ociram_sp_ram.lpm_file = "limbus_nios2_qsys_0_ociram_default_contents.mif";
//synthesis read_comments_as_HDL off
assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h10000020 :
(MonAReg[4 : 2] == 3'd1)? 32'h00001d1d :
(MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
(MonAReg[4 : 2] == 3'd3)? 32'h00000100 :
(MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
(MonAReg[4 : 2] == 3'd5)? 32'h10000000 :
(MonAReg[4 : 2] == 3'd6)? 32'h00000000 :
32'h00000000;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
)
;
output [ 31: 0] oci_ienable;
output [ 31: 0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [ 8: 0] address;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [ 31: 0] writedata;
reg [ 31: 0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [ 31: 0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_single_step_mode <= 1'b0;
else if (take_action_ocireg)
oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_ienable <= 32'b00000000000000000000000000000001;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000000000001);
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_nios2_oci_break (
// inputs:
clk,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
jdo,
jrst_n,
reset_n,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
xbrk_goto0,
xbrk_goto1,
// outputs:
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
trigbrktype,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3
)
;
output [ 31: 0] break_readreg;
output dbrk_hit0_latch;
output dbrk_hit1_latch;
output dbrk_hit2_latch;
output dbrk_hit3_latch;
output trigbrktype;
output trigger_state_0;
output trigger_state_1;
output [ 7: 0] xbrk_ctrl0;
output [ 7: 0] xbrk_ctrl1;
output [ 7: 0] xbrk_ctrl2;
output [ 7: 0] xbrk_ctrl3;
input clk;
input dbrk_break;
input dbrk_goto0;
input dbrk_goto1;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_break_a;
input take_action_break_b;
input take_action_break_c;
input take_no_action_break_a;
input take_no_action_break_b;
input take_no_action_break_c;
input xbrk_goto0;
input xbrk_goto1;
wire [ 3: 0] break_a_wpr;
wire [ 1: 0] break_a_wpr_high_bits;
wire [ 1: 0] break_a_wpr_low_bits;
wire [ 1: 0] break_b_rr;
wire [ 1: 0] break_c_rr;
reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire dbrk0_high_value;
wire dbrk0_low_value;
wire dbrk1_high_value;
wire dbrk1_low_value;
wire dbrk2_high_value;
wire dbrk2_low_value;
wire dbrk3_high_value;
wire dbrk3_low_value;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire take_action_any_break;
reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg trigger_state;
wire trigger_state_0;
wire trigger_state_1;
wire [ 31: 0] xbrk0_value;
wire [ 31: 0] xbrk1_value;
wire [ 31: 0] xbrk2_value;
wire [ 31: 0] xbrk3_value;
reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
assign break_a_wpr = jdo[35 : 32];
assign break_a_wpr_high_bits = break_a_wpr[3 : 2];
assign break_a_wpr_low_bits = break_a_wpr[1 : 0];
assign break_b_rr = jdo[33 : 32];
assign break_c_rr = jdo[33 : 32];
assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
xbrk_ctrl0 <= 0;
xbrk_ctrl1 <= 0;
xbrk_ctrl2 <= 0;
xbrk_ctrl3 <= 0;
trigbrktype <= 0;
end
else
begin
if (take_action_any_break)
trigbrktype <= 0;
else if (dbrk_break)
trigbrktype <= 1;
if (take_action_break_b)
begin
if ((break_b_rr == 2'b00) && (0 >= 1))
begin
xbrk_ctrl0[0] <= jdo[27];
xbrk_ctrl0[1] <= jdo[28];
xbrk_ctrl0[2] <= jdo[29];
xbrk_ctrl0[3] <= jdo[30];
xbrk_ctrl0[4] <= jdo[21];
xbrk_ctrl0[5] <= jdo[20];
xbrk_ctrl0[6] <= jdo[19];
xbrk_ctrl0[7] <= jdo[18];
end
if ((break_b_rr == 2'b01) && (0 >= 2))
begin
xbrk_ctrl1[0] <= jdo[27];
xbrk_ctrl1[1] <= jdo[28];
xbrk_ctrl1[2] <= jdo[29];
xbrk_ctrl1[3] <= jdo[30];
xbrk_ctrl1[4] <= jdo[21];
xbrk_ctrl1[5] <= jdo[20];
xbrk_ctrl1[6] <= jdo[19];
xbrk_ctrl1[7] <= jdo[18];
end
if ((break_b_rr == 2'b10) && (0 >= 3))
begin
xbrk_ctrl2[0] <= jdo[27];
xbrk_ctrl2[1] <= jdo[28];
xbrk_ctrl2[2] <= jdo[29];
xbrk_ctrl2[3] <= jdo[30];
xbrk_ctrl2[4] <= jdo[21];
xbrk_ctrl2[5] <= jdo[20];
xbrk_ctrl2[6] <= jdo[19];
xbrk_ctrl2[7] <= jdo[18];
end
if ((break_b_rr == 2'b11) && (0 >= 4))
begin
xbrk_ctrl3[0] <= jdo[27];
xbrk_ctrl3[1] <= jdo[28];
xbrk_ctrl3[2] <= jdo[29];
xbrk_ctrl3[3] <= jdo[30];
xbrk_ctrl3[4] <= jdo[21];
xbrk_ctrl3[5] <= jdo[20];
xbrk_ctrl3[6] <= jdo[19];
xbrk_ctrl3[7] <= jdo[18];
end
end
end
end
assign dbrk_hit0_latch = 1'b0;
assign dbrk0_low_value = 0;
assign dbrk0_high_value = 0;
assign dbrk_hit1_latch = 1'b0;
assign dbrk1_low_value = 0;
assign dbrk1_high_value = 0;
assign dbrk_hit2_latch = 1'b0;
assign dbrk2_low_value = 0;
assign dbrk2_high_value = 0;
assign dbrk_hit3_latch = 1'b0;
assign dbrk3_low_value = 0;
assign dbrk3_high_value = 0;
assign xbrk0_value = 32'b0;
assign xbrk1_value = 32'b0;
assign xbrk2_value = 32'b0;
assign xbrk3_value = 32'b0;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
break_readreg <= 32'b0;
else if (take_action_any_break)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_a)
case (break_a_wpr_high_bits)
2'd0: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= xbrk0_value;
end // 2'd0
2'd1: begin
break_readreg <= xbrk1_value;
end // 2'd1
2'd2: begin
break_readreg <= xbrk2_value;
end // 2'd2
2'd3: begin
break_readreg <= xbrk3_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd0
2'd1: begin
break_readreg <= 32'b0;
end // 2'd1
2'd2: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_low_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_low_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_low_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_low_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd2
2'd3: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_high_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_high_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_high_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_high_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd3
endcase // break_a_wpr_high_bits
else if (take_no_action_break_b)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_c)
break_readreg <= jdo[31 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trigger_state <= 0;
else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0))
trigger_state <= 0;
else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1))
trigger_state <= -1;
end
assign trigger_state_0 = ~trigger_state;
assign trigger_state_1 = trigger_state;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_nios2_oci_xbrk (
// inputs:
D_valid,
E_valid,
F_pc,
clk,
reset_n,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3,
// outputs:
xbrk_break,
xbrk_goto0,
xbrk_goto1,
xbrk_traceoff,
xbrk_traceon,
xbrk_trigout
)
;
output xbrk_break;
output xbrk_goto0;
output xbrk_goto1;
output xbrk_traceoff;
output xbrk_traceon;
output xbrk_trigout;
input D_valid;
input E_valid;
input [ 26: 0] F_pc;
input clk;
input reset_n;
input trigger_state_0;
input trigger_state_1;
input [ 7: 0] xbrk_ctrl0;
input [ 7: 0] xbrk_ctrl1;
input [ 7: 0] xbrk_ctrl2;
input [ 7: 0] xbrk_ctrl3;
wire D_cpu_addr_en;
wire E_cpu_addr_en;
reg E_xbrk_goto0;
reg E_xbrk_goto1;
reg E_xbrk_traceoff;
reg E_xbrk_traceon;
reg E_xbrk_trigout;
wire [ 28: 0] cpu_i_address;
wire xbrk0_armed;
wire xbrk0_break_hit;
wire xbrk0_goto0_hit;
wire xbrk0_goto1_hit;
wire xbrk0_toff_hit;
wire xbrk0_ton_hit;
wire xbrk0_tout_hit;
wire xbrk1_armed;
wire xbrk1_break_hit;
wire xbrk1_goto0_hit;
wire xbrk1_goto1_hit;
wire xbrk1_toff_hit;
wire xbrk1_ton_hit;
wire xbrk1_tout_hit;
wire xbrk2_armed;
wire xbrk2_break_hit;
wire xbrk2_goto0_hit;
wire xbrk2_goto1_hit;
wire xbrk2_toff_hit;
wire xbrk2_ton_hit;
wire xbrk2_tout_hit;
wire xbrk3_armed;
wire xbrk3_break_hit;
wire xbrk3_goto0_hit;
wire xbrk3_goto1_hit;
wire xbrk3_toff_hit;
wire xbrk3_ton_hit;
wire xbrk3_tout_hit;
reg xbrk_break;
wire xbrk_break_hit;
wire xbrk_goto0;
wire xbrk_goto0_hit;
wire xbrk_goto1;
wire xbrk_goto1_hit;
wire xbrk_toff_hit;
wire xbrk_ton_hit;
wire xbrk_tout_hit;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
assign cpu_i_address = {F_pc, 2'b00};
assign D_cpu_addr_en = D_valid;
assign E_cpu_addr_en = E_valid;
assign xbrk0_break_hit = 0;
assign xbrk0_ton_hit = 0;
assign xbrk0_toff_hit = 0;
assign xbrk0_tout_hit = 0;
assign xbrk0_goto0_hit = 0;
assign xbrk0_goto1_hit = 0;
assign xbrk1_break_hit = 0;
assign xbrk1_ton_hit = 0;
assign xbrk1_toff_hit = 0;
assign xbrk1_tout_hit = 0;
assign xbrk1_goto0_hit = 0;
assign xbrk1_goto1_hit = 0;
assign xbrk2_break_hit = 0;
assign xbrk2_ton_hit = 0;
assign xbrk2_toff_hit = 0;
assign xbrk2_tout_hit = 0;
assign xbrk2_goto0_hit = 0;
assign xbrk2_goto1_hit = 0;
assign xbrk3_break_hit = 0;
assign xbrk3_ton_hit = 0;
assign xbrk3_toff_hit = 0;
assign xbrk3_tout_hit = 0;
assign xbrk3_goto0_hit = 0;
assign xbrk3_goto1_hit = 0;
assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit);
assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit);
assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit);
assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit);
assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit);
assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
xbrk_break <= 0;
else if (E_cpu_addr_en)
xbrk_break <= xbrk_break_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceon <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceon <= xbrk_ton_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceoff <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceoff <= xbrk_toff_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_trigout <= 0;
else if (E_cpu_addr_en)
E_xbrk_trigout <= xbrk_tout_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto0 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto0 <= xbrk_goto0_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto1 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto1 <= xbrk_goto1_hit;
end
assign xbrk_traceon = 1'b0;
assign xbrk_traceoff = 1'b0;
assign xbrk_trigout = 1'b0;
assign xbrk_goto0 = 1'b0;
assign xbrk_goto1 = 1'b0;
assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) ||
(xbrk_ctrl0[5] & trigger_state_1);
assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) ||
(xbrk_ctrl1[5] & trigger_state_1);
assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) ||
(xbrk_ctrl2[5] & trigger_state_1);
assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) ||
(xbrk_ctrl3[5] & trigger_state_1);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_nios2_oci_dbrk (
// inputs:
E_st_data,
av_ld_data_aligned_filtered,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugack,
reset_n,
// outputs:
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dbrk_trigout
)
;
output [ 28: 0] cpu_d_address;
output cpu_d_read;
output [ 31: 0] cpu_d_readdata;
output cpu_d_wait;
output cpu_d_write;
output [ 31: 0] cpu_d_writedata;
output dbrk_break;
output dbrk_goto0;
output dbrk_goto1;
output dbrk_traceme;
output dbrk_traceoff;
output dbrk_traceon;
output dbrk_trigout;
input [ 31: 0] E_st_data;
input [ 31: 0] av_ld_data_aligned_filtered;
input clk;
input [ 28: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugack;
input reset_n;
wire [ 28: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk0_armed;
wire dbrk0_break_pulse;
wire dbrk0_goto0;
wire dbrk0_goto1;
wire dbrk0_traceme;
wire dbrk0_traceoff;
wire dbrk0_traceon;
wire dbrk0_trigout;
wire dbrk1_armed;
wire dbrk1_break_pulse;
wire dbrk1_goto0;
wire dbrk1_goto1;
wire dbrk1_traceme;
wire dbrk1_traceoff;
wire dbrk1_traceon;
wire dbrk1_trigout;
wire dbrk2_armed;
wire dbrk2_break_pulse;
wire dbrk2_goto0;
wire dbrk2_goto1;
wire dbrk2_traceme;
wire dbrk2_traceoff;
wire dbrk2_traceon;
wire dbrk2_trigout;
wire dbrk3_armed;
wire dbrk3_break_pulse;
wire dbrk3_goto0;
wire dbrk3_goto1;
wire dbrk3_traceme;
wire dbrk3_traceoff;
wire dbrk3_traceon;
wire dbrk3_trigout;
reg dbrk_break;
reg dbrk_break_pulse;
wire [ 31: 0] dbrk_data;
reg dbrk_goto0;
reg dbrk_goto1;
reg dbrk_traceme;
reg dbrk_traceoff;
reg dbrk_traceon;
reg dbrk_trigout;
assign cpu_d_address = d_address;
assign cpu_d_readdata = av_ld_data_aligned_filtered;
assign cpu_d_read = d_read;
assign cpu_d_writedata = E_st_data;
assign cpu_d_write = d_write;
assign cpu_d_wait = d_waitrequest;
assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbrk_break <= 0;
else
dbrk_break <= dbrk_break ? ~debugack
: dbrk_break_pulse;
end
assign dbrk0_armed = 1'b0;
assign dbrk0_trigout = 1'b0;
assign dbrk0_break_pulse = 1'b0;
assign dbrk0_traceoff = 1'b0;
assign dbrk0_traceon = 1'b0;
assign dbrk0_traceme = 1'b0;
assign dbrk0_goto0 = 1'b0;
assign dbrk0_goto1 = 1'b0;
assign dbrk1_armed = 1'b0;
assign dbrk1_trigout = 1'b0;
assign dbrk1_break_pulse = 1'b0;
assign dbrk1_traceoff = 1'b0;
assign dbrk1_traceon = 1'b0;
assign dbrk1_traceme = 1'b0;
assign dbrk1_goto0 = 1'b0;
assign dbrk1_goto1 = 1'b0;
assign dbrk2_armed = 1'b0;
assign dbrk2_trigout = 1'b0;
assign dbrk2_break_pulse = 1'b0;
assign dbrk2_traceoff = 1'b0;
assign dbrk2_traceon = 1'b0;
assign dbrk2_traceme = 1'b0;
assign dbrk2_goto0 = 1'b0;
assign dbrk2_goto1 = 1'b0;
assign dbrk3_armed = 1'b0;
assign dbrk3_trigout = 1'b0;
assign dbrk3_break_pulse = 1'b0;
assign dbrk3_traceoff = 1'b0;
assign dbrk3_traceon = 1'b0;
assign dbrk3_traceme = 1'b0;
assign dbrk3_goto0 = 1'b0;
assign dbrk3_goto1 = 1'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
dbrk_trigout <= 0;
dbrk_break_pulse <= 0;
dbrk_traceoff <= 0;
dbrk_traceon <= 0;
dbrk_traceme <= 0;
dbrk_goto0 <= 0;
dbrk_goto1 <= 0;
end
else
begin
dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout;
dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse;
dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff;
dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon;
dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme;
dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0;
dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_nios2_oci_itrace (
// inputs:
clk,
dbrk_traceoff,
dbrk_traceon,
jdo,
jrst_n,
take_action_tracectrl,
trc_enb,
xbrk_traceoff,
xbrk_traceon,
xbrk_wrap_traceoff,
// outputs:
dct_buffer,
dct_count,
itm,
trc_ctrl,
trc_on
)
;
output [ 29: 0] dct_buffer;
output [ 3: 0] dct_count;
output [ 35: 0] itm;
output [ 15: 0] trc_ctrl;
output trc_on;
input clk;
input dbrk_traceoff;
input dbrk_traceon;
input [ 15: 0] jdo;
input jrst_n;
input take_action_tracectrl;
input trc_enb;
input xbrk_traceoff;
input xbrk_traceon;
input xbrk_wrap_traceoff;
wire advanced_exc_occured;
wire curr_pid;
reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] dct_code;
reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dct_is_taken;
wire [ 31: 0] eic_addr;
wire [ 31: 0] exc_addr;
wire instr_retired;
wire is_cond_dct;
wire is_dct;
wire is_exception_no_break;
wire is_external_interrupt;
wire is_fast_tlb_miss_exception;
wire is_idct;
reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire not_in_debug_mode;
reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exc /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_exc_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_exc_handler /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exc_record_handler /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_dct_outcome_in_sync;
wire record_itrace;
wire [ 31: 0] retired_pcb;
reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] sync_code;
wire [ 6: 0] sync_interval;
reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 6: 0] sync_timer_next;
wire sync_timer_reached_zero;
reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire [ 15: 0] trc_ctrl;
reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire trc_on;
assign is_cond_dct = 1'b0;
assign is_dct = 1'b0;
assign dct_is_taken = 1'b0;
assign is_idct = 1'b0;
assign retired_pcb = 32'b0;
assign not_in_debug_mode = 1'b0;
assign instr_retired = 1'b0;
assign advanced_exc_occured = 1'b0;
assign is_exception_no_break = 1'b0;
assign is_external_interrupt = 1'b0;
assign is_fast_tlb_miss_exception = 1'b0;
assign curr_pid = 1'b0;
assign exc_addr = 32'b0;
assign eic_addr = 32'b0;
assign sync_code = trc_ctrl[3 : 2];
assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 };
assign sync_timer_reached_zero = sync_timer == 0;
assign record_dct_outcome_in_sync = dct_is_taken & sync_timer_reached_zero;
assign sync_timer_next = sync_timer_reached_zero ? sync_timer : (sync_timer - 1);
assign record_itrace = trc_on & trc_ctrl[4];
assign dct_code = {is_cond_dct, dct_is_taken};
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
trc_clear <= 0;
else
trc_clear <= ~trc_enb &
take_action_tracectrl & jdo[4];
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exc <= 0;
pending_exc_addr <= 0;
pending_exc_handler <= 0;
pending_exc_record_handler <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else if (trc_clear || (!0 && !0))
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exc <= 0;
pending_exc_addr <= 0;
pending_exc_handler <= 0;
pending_exc_record_handler <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else
begin
if (!prev_pid_valid)
begin
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if (instr_retired | advanced_exc_occured)
begin
if (~record_itrace)
pending_frametype <= 4'b1010;
else if (is_exception_no_break)
begin
pending_exc <= 1;
pending_exc_addr <= exc_addr;
pending_exc_record_handler <= 0;
if (is_external_interrupt)
pending_exc_handler <= eic_addr;
else if (is_fast_tlb_miss_exception)
pending_exc_handler <= 32'h0;
else
pending_exc_handler <= 32'h10000020;
pending_frametype <= 4'b0000;
end
else if (is_idct)
pending_frametype <= 4'b1001;
else if (record_dct_outcome_in_sync)
pending_frametype <= 4'b1000;
else if (!is_dct & snapped_pid)
begin
pending_frametype <= 4'b0011;
pending_curr_pid <= snapped_curr_pid;
pending_prev_pid <= snapped_prev_pid;
snapped_pid <= 0;
end
else
pending_frametype <= 4'b0000;
if ((dct_count != 0) &
(~record_itrace |
is_exception_no_break |
is_idct |
record_dct_outcome_in_sync |
(!is_dct & snapped_pid)))
begin
itm <= {4'b0001, dct_buffer, 2'b00};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
begin
if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~advanced_exc_occured)
begin
dct_buffer <= {dct_code, dct_buffer[29 : 2]};
dct_count <= dct_count + 1;
end
if (record_itrace & (
(pending_frametype == 4'b1000) |
(pending_frametype == 4'b1010) |
(pending_frametype == 4'b1001)))
begin
itm <= {pending_frametype, retired_pcb};
sync_timer <= sync_interval;
if (0 &
((pending_frametype == 4'b1000) | (pending_frametype == 4'b1010)) &
!snapped_pid & prev_pid_valid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
end
end
else if (record_itrace &
0 & (pending_frametype == 4'b0011))
itm <= {4'b0011, 2'b00, pending_prev_pid, 2'b00, pending_curr_pid};
else if (record_itrace & is_dct)
begin
if (dct_count == 4'd15)
begin
itm <= {4'b0001, dct_code, dct_buffer};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
itm <= 4'b0000;
end
else
itm <= {4'b0000, 32'b0};
end
end
else if (record_itrace & pending_exc)
begin
if (pending_exc_record_handler)
begin
itm <= {4'b0010, pending_exc_handler[31 : 1], 1'b1};
pending_exc <= 1'b0;
pending_exc_record_handler <= 1'b0;
end
else
begin
itm <= {4'b0010, pending_exc_addr[31 : 1], 1'b0};
pending_exc_record_handler <= 1'b1;
end
end
else
itm <= {4'b0000, 32'b0};
end
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_ctrl_reg[0] <= 1'b0;
trc_ctrl_reg[1] <= 1'b0;
trc_ctrl_reg[3 : 2] <= 2'b00;
trc_ctrl_reg[4] <= 1'b0;
trc_ctrl_reg[7 : 5] <= 3'b000;
trc_ctrl_reg[8] <= 0;
trc_ctrl_reg[9] <= 1'b0;
trc_ctrl_reg[10] <= 1'b0;
end
else if (take_action_tracectrl)
begin
trc_ctrl_reg[0] <= jdo[5];
trc_ctrl_reg[1] <= jdo[6];
trc_ctrl_reg[3 : 2] <= jdo[8 : 7];
trc_ctrl_reg[4] <= jdo[9];
trc_ctrl_reg[9] <= jdo[14];
trc_ctrl_reg[10] <= jdo[2];
if (0)
trc_ctrl_reg[7 : 5] <= jdo[12 : 10];
if (0 & 0)
trc_ctrl_reg[8] <= jdo[13];
end
else if (xbrk_wrap_traceoff)
begin
trc_ctrl_reg[1] <= 0;
trc_ctrl_reg[0] <= 0;
end
else if (dbrk_traceoff | xbrk_traceoff)
trc_ctrl_reg[1] <= 0;
else if (trc_ctrl_reg[0] &
(dbrk_traceon | xbrk_traceon))
trc_ctrl_reg[1] <= 1;
end
assign trc_ctrl = (0 || 0) ? {6'b000000, trc_ctrl_reg} : 0;
assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
)
;
output [ 3: 0] td_mode;
input [ 8: 0] ctrl;
wire [ 2: 0] ctrl_bits_for_mux;
reg [ 3: 0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux)
begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
)
;
output [ 35: 0] atm;
output [ 35: 0] dtm;
input clk;
input [ 28: 0] cpu_d_address;
input cpu_d_read;
input [ 31: 0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [ 31: 0] cpu_d_writedata;
input jrst_n;
input [ 15: 0] trc_ctrl;
reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 31: 0] cpu_d_address_0_padded;
wire [ 31: 0] cpu_d_readdata_0_padded;
wire [ 31: 0] cpu_d_writedata_0_padded;
reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3: 0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//limbus_nios2_qsys_0_nios2_oci_trc_ctrl_td_mode, which is an e_instance
limbus_nios2_qsys_0_nios2_oci_td_mode limbus_nios2_qsys_0_nios2_oci_trc_ctrl_td_mode
(
.ctrl (trc_ctrl[8 : 0]),
.td_mode (td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
atm <= 0;
dtm <= 0;
end
else if (0)
begin
if (cpu_d_write & ~cpu_d_wait & record_store_addr)
atm <= {4'b0101, cpu_d_address_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_addr)
atm <= {4'b0100, cpu_d_address_0_padded};
else
atm <= {4'b0000, cpu_d_address_0_padded};
if (cpu_d_write & ~cpu_d_wait & record_store_data)
dtm <= {4'b0111, cpu_d_writedata_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_data)
dtm <= {4'b0110, cpu_d_readdata_0_padded};
else
dtm <= {4'b0000, cpu_d_readdata_0_padded};
end
else
begin
atm <= 0;
dtm <= 0;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
)
;
output [ 1: 0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [ 1: 0] compute_input_tm_cnt;
wire [ 2: 0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux)
begin
case (switch_for_mux)
3'b000: begin
compute_input_tm_cnt = 0;
end // 3'b000
3'b001: begin
compute_input_tm_cnt = 1;
end // 3'b001
3'b010: begin
compute_input_tm_cnt = 1;
end // 3'b010
3'b011: begin
compute_input_tm_cnt = 2;
end // 3'b011
3'b100: begin
compute_input_tm_cnt = 1;
end // 3'b100
3'b101: begin
compute_input_tm_cnt = 2;
end // 3'b101
3'b110: begin
compute_input_tm_cnt = 2;
end // 3'b110
3'b111: begin
compute_input_tm_cnt = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
)
;
output [ 3: 0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [ 1: 0] input_tm_cnt;
reg [ 3: 0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or input_tm_cnt)
begin
if (ge3_free & (input_tm_cnt == 3))
fifo_wrptr_inc = 3;
else if (ge2_free & (input_tm_cnt >= 2))
fifo_wrptr_inc = 2;
else if (input_tm_cnt >= 1)
fifo_wrptr_inc = 1;
else
fifo_wrptr_inc = 0;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
)
;
output [ 4: 0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [ 1: 0] input_tm_cnt;
reg [ 4: 0] fifo_cnt_inc;
always @(empty or ge2_free or ge3_free or input_tm_cnt)
begin
if (empty)
fifo_cnt_inc = input_tm_cnt[1 : 0];
else if (ge3_free & (input_tm_cnt == 3))
fifo_cnt_inc = 2;
else if (ge2_free & (input_tm_cnt >= 2))
fifo_cnt_inc = 1;
else if (input_tm_cnt >= 1)
fifo_cnt_inc = 0;
else
fifo_cnt_inc = {5{1'b1}};
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_nios2_oci_fifo (
// inputs:
atm,
clk,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dct_buffer,
dct_count,
dtm,
itm,
jrst_n,
reset_n,
test_ending,
test_has_ended,
trc_on,
// outputs:
tw
)
;
output [ 35: 0] tw;
input [ 35: 0] atm;
input clk;
input dbrk_traceme;
input dbrk_traceoff;
input dbrk_traceon;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input [ 35: 0] dtm;
input [ 35: 0] itm;
input jrst_n;
input reset_n;
input test_ending;
input test_has_ended;
input trc_on;
wire atm_valid;
wire [ 1: 0] compute_input_tm_cnt;
wire dtm_valid;
wire empty;
reg [ 35: 0] fifo_0;
wire fifo_0_enable;
wire [ 35: 0] fifo_0_mux;
reg [ 35: 0] fifo_1;
reg [ 35: 0] fifo_10;
wire fifo_10_enable;
wire [ 35: 0] fifo_10_mux;
reg [ 35: 0] fifo_11;
wire fifo_11_enable;
wire [ 35: 0] fifo_11_mux;
reg [ 35: 0] fifo_12;
wire fifo_12_enable;
wire [ 35: 0] fifo_12_mux;
reg [ 35: 0] fifo_13;
wire fifo_13_enable;
wire [ 35: 0] fifo_13_mux;
reg [ 35: 0] fifo_14;
wire fifo_14_enable;
wire [ 35: 0] fifo_14_mux;
reg [ 35: 0] fifo_15;
wire fifo_15_enable;
wire [ 35: 0] fifo_15_mux;
wire fifo_1_enable;
wire [ 35: 0] fifo_1_mux;
reg [ 35: 0] fifo_2;
wire fifo_2_enable;
wire [ 35: 0] fifo_2_mux;
reg [ 35: 0] fifo_3;
wire fifo_3_enable;
wire [ 35: 0] fifo_3_mux;
reg [ 35: 0] fifo_4;
wire fifo_4_enable;
wire [ 35: 0] fifo_4_mux;
reg [ 35: 0] fifo_5;
wire fifo_5_enable;
wire [ 35: 0] fifo_5_mux;
reg [ 35: 0] fifo_6;
wire fifo_6_enable;
wire [ 35: 0] fifo_6_mux;
reg [ 35: 0] fifo_7;
wire fifo_7_enable;
wire [ 35: 0] fifo_7_mux;
reg [ 35: 0] fifo_8;
wire fifo_8_enable;
wire [ 35: 0] fifo_8_mux;
reg [ 35: 0] fifo_9;
wire fifo_9_enable;
wire [ 35: 0] fifo_9_mux;
reg [ 4: 0] fifo_cnt /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 4: 0] fifo_cnt_inc;
wire [ 35: 0] fifo_head;
reg [ 3: 0] fifo_rdptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] fifo_read_mux;
reg [ 3: 0] fifo_wrptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 3: 0] fifo_wrptr_inc;
wire [ 3: 0] fifo_wrptr_plus1;
wire [ 3: 0] fifo_wrptr_plus2;
wire ge2_free;
wire ge3_free;
wire input_ge1;
wire input_ge2;
wire input_ge3;
wire [ 1: 0] input_tm_cnt;
wire itm_valid;
reg overflow_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] overflow_pending_atm;
wire [ 35: 0] overflow_pending_dtm;
wire trc_this;
wire [ 35: 0] tw;
assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme;
assign itm_valid = |itm[35 : 32];
assign atm_valid = |atm[35 : 32] & trc_this;
assign dtm_valid = |dtm[35 : 32] & trc_this;
assign ge2_free = ~fifo_cnt[4];
assign ge3_free = ge2_free & ~&fifo_cnt[3 : 0];
assign empty = ~|fifo_cnt;
assign fifo_wrptr_plus1 = fifo_wrptr + 1;
assign fifo_wrptr_plus2 = fifo_wrptr + 2;
limbus_nios2_qsys_0_nios2_oci_compute_input_tm_cnt the_limbus_nios2_qsys_0_nios2_oci_compute_input_tm_cnt
(
.atm_valid (atm_valid),
.compute_input_tm_cnt (compute_input_tm_cnt),
.dtm_valid (dtm_valid),
.itm_valid (itm_valid)
);
assign input_tm_cnt = compute_input_tm_cnt;
limbus_nios2_qsys_0_nios2_oci_fifo_wrptr_inc the_limbus_nios2_qsys_0_nios2_oci_fifo_wrptr_inc
(
.fifo_wrptr_inc (fifo_wrptr_inc),
.ge2_free (ge2_free),
.ge3_free (ge3_free),
.input_tm_cnt (input_tm_cnt)
);
limbus_nios2_qsys_0_nios2_oci_fifo_cnt_inc the_limbus_nios2_qsys_0_nios2_oci_fifo_cnt_inc
(
.empty (empty),
.fifo_cnt_inc (fifo_cnt_inc),
.ge2_free (ge2_free),
.ge3_free (ge3_free),
.input_tm_cnt (input_tm_cnt)
);
limbus_nios2_qsys_0_oci_test_bench the_limbus_nios2_qsys_0_oci_test_bench
(
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.test_ending (test_ending),
.test_has_ended (test_has_ended)
);
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
fifo_rdptr <= 0;
fifo_wrptr <= 0;
fifo_cnt <= 0;
overflow_pending <= 1;
end
else
begin
fifo_wrptr <= fifo_wrptr + fifo_wrptr_inc;
fifo_cnt <= fifo_cnt + fifo_cnt_inc;
if (~empty)
fifo_rdptr <= fifo_rdptr + 1;
if (~trc_this || (~ge2_free & input_ge2) || (~ge3_free & input_ge3))
overflow_pending <= 1;
else if (atm_valid | dtm_valid)
overflow_pending <= 0;
end
end
assign fifo_head = fifo_read_mux;
assign tw = 0 ? { (empty ? 4'h0 : fifo_head[35 : 32]), fifo_head[31 : 0]} : itm;
assign fifo_0_enable = ((fifo_wrptr == 4'd0) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd0) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd0) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_0 <= 0;
else if (fifo_0_enable)
fifo_0 <= fifo_0_mux;
end
assign fifo_0_mux = (((fifo_wrptr == 4'd0) && itm_valid))? itm :
(((fifo_wrptr == 4'd0) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd0) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_1_enable = ((fifo_wrptr == 4'd1) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd1) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd1) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_1 <= 0;
else if (fifo_1_enable)
fifo_1 <= fifo_1_mux;
end
assign fifo_1_mux = (((fifo_wrptr == 4'd1) && itm_valid))? itm :
(((fifo_wrptr == 4'd1) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd1) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_2_enable = ((fifo_wrptr == 4'd2) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd2) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd2) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_2 <= 0;
else if (fifo_2_enable)
fifo_2 <= fifo_2_mux;
end
assign fifo_2_mux = (((fifo_wrptr == 4'd2) && itm_valid))? itm :
(((fifo_wrptr == 4'd2) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd2) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_3_enable = ((fifo_wrptr == 4'd3) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd3) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd3) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_3 <= 0;
else if (fifo_3_enable)
fifo_3 <= fifo_3_mux;
end
assign fifo_3_mux = (((fifo_wrptr == 4'd3) && itm_valid))? itm :
(((fifo_wrptr == 4'd3) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd3) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_4_enable = ((fifo_wrptr == 4'd4) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd4) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd4) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_4 <= 0;
else if (fifo_4_enable)
fifo_4 <= fifo_4_mux;
end
assign fifo_4_mux = (((fifo_wrptr == 4'd4) && itm_valid))? itm :
(((fifo_wrptr == 4'd4) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd4) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_5_enable = ((fifo_wrptr == 4'd5) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd5) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd5) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_5 <= 0;
else if (fifo_5_enable)
fifo_5 <= fifo_5_mux;
end
assign fifo_5_mux = (((fifo_wrptr == 4'd5) && itm_valid))? itm :
(((fifo_wrptr == 4'd5) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd5) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_6_enable = ((fifo_wrptr == 4'd6) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd6) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd6) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_6 <= 0;
else if (fifo_6_enable)
fifo_6 <= fifo_6_mux;
end
assign fifo_6_mux = (((fifo_wrptr == 4'd6) && itm_valid))? itm :
(((fifo_wrptr == 4'd6) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd6) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_7_enable = ((fifo_wrptr == 4'd7) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd7) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd7) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_7 <= 0;
else if (fifo_7_enable)
fifo_7 <= fifo_7_mux;
end
assign fifo_7_mux = (((fifo_wrptr == 4'd7) && itm_valid))? itm :
(((fifo_wrptr == 4'd7) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd7) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_8_enable = ((fifo_wrptr == 4'd8) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd8) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd8) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_8 <= 0;
else if (fifo_8_enable)
fifo_8 <= fifo_8_mux;
end
assign fifo_8_mux = (((fifo_wrptr == 4'd8) && itm_valid))? itm :
(((fifo_wrptr == 4'd8) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd8) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_9_enable = ((fifo_wrptr == 4'd9) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd9) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd9) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_9 <= 0;
else if (fifo_9_enable)
fifo_9 <= fifo_9_mux;
end
assign fifo_9_mux = (((fifo_wrptr == 4'd9) && itm_valid))? itm :
(((fifo_wrptr == 4'd9) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd9) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_10_enable = ((fifo_wrptr == 4'd10) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd10) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd10) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_10 <= 0;
else if (fifo_10_enable)
fifo_10 <= fifo_10_mux;
end
assign fifo_10_mux = (((fifo_wrptr == 4'd10) && itm_valid))? itm :
(((fifo_wrptr == 4'd10) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd10) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_11_enable = ((fifo_wrptr == 4'd11) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd11) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd11) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_11 <= 0;
else if (fifo_11_enable)
fifo_11 <= fifo_11_mux;
end
assign fifo_11_mux = (((fifo_wrptr == 4'd11) && itm_valid))? itm :
(((fifo_wrptr == 4'd11) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd11) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_12_enable = ((fifo_wrptr == 4'd12) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd12) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd12) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_12 <= 0;
else if (fifo_12_enable)
fifo_12 <= fifo_12_mux;
end
assign fifo_12_mux = (((fifo_wrptr == 4'd12) && itm_valid))? itm :
(((fifo_wrptr == 4'd12) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd12) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_13_enable = ((fifo_wrptr == 4'd13) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd13) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd13) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_13 <= 0;
else if (fifo_13_enable)
fifo_13 <= fifo_13_mux;
end
assign fifo_13_mux = (((fifo_wrptr == 4'd13) && itm_valid))? itm :
(((fifo_wrptr == 4'd13) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd13) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_14_enable = ((fifo_wrptr == 4'd14) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd14) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd14) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_14 <= 0;
else if (fifo_14_enable)
fifo_14 <= fifo_14_mux;
end
assign fifo_14_mux = (((fifo_wrptr == 4'd14) && itm_valid))? itm :
(((fifo_wrptr == 4'd14) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd14) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_15_enable = ((fifo_wrptr == 4'd15) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd15) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd15) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_15 <= 0;
else if (fifo_15_enable)
fifo_15 <= fifo_15_mux;
end
assign fifo_15_mux = (((fifo_wrptr == 4'd15) && itm_valid))? itm :
(((fifo_wrptr == 4'd15) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd15) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign input_ge1 = |input_tm_cnt;
assign input_ge2 = input_tm_cnt[1];
assign input_ge3 = &input_tm_cnt;
assign overflow_pending_atm = {overflow_pending, atm[34 : 0]};
assign overflow_pending_dtm = {overflow_pending, dtm[34 : 0]};
assign fifo_read_mux = (fifo_rdptr == 4'd0)? fifo_0 :
(fifo_rdptr == 4'd1)? fifo_1 :
(fifo_rdptr == 4'd2)? fifo_2 :
(fifo_rdptr == 4'd3)? fifo_3 :
(fifo_rdptr == 4'd4)? fifo_4 :
(fifo_rdptr == 4'd5)? fifo_5 :
(fifo_rdptr == 4'd6)? fifo_6 :
(fifo_rdptr == 4'd7)? fifo_7 :
(fifo_rdptr == 4'd8)? fifo_8 :
(fifo_rdptr == 4'd9)? fifo_9 :
(fifo_rdptr == 4'd10)? fifo_10 :
(fifo_rdptr == 4'd11)? fifo_11 :
(fifo_rdptr == 4'd12)? fifo_12 :
(fifo_rdptr == 4'd13)? fifo_13 :
(fifo_rdptr == 4'd14)? fifo_14 :
fifo_15;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
)
;
output tr_clk;
output [ 17: 0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [ 35: 0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 17: 0] tr_data;
reg [ 17: 0] tr_data_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
assign phase = x1^x2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
x1 <= 0;
else
x1 <= ~x1;
end
always @(posedge clkx2 or negedge jrst_n)
begin
if (jrst_n == 0)
begin
x2 <= 0;
tr_clk_reg <= 0;
tr_data_reg <= 0;
end
else
begin
x2 <= x1;
tr_clk_reg <= ~phase;
tr_data_reg <= phase ? tw[17 : 0] : tw[35 : 18];
end
end
assign tr_clk = 0 ? tr_clk_reg : 0;
assign tr_data = 0 ? tr_data_reg : 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
)
;
output tracemem_on;
output [ 35: 0] tracemem_trcdata;
output tracemem_tw;
output trc_enb;
output [ 6: 0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_tracectrl;
input take_action_tracemem_a;
input take_action_tracemem_b;
input take_no_action_tracemem_a;
input [ 15: 0] trc_ctrl;
input [ 35: 0] tw;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire trc_enb;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 35: 0] trc_im_data;
reg [ 16: 0] trc_jtag_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (!0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (take_action_tracectrl &&
(jdo[4] | jdo[3]))
begin
if (jdo[4])
trc_im_addr <= 0;
if (jdo[3])
trc_wrap <= 0;
end
else if (trc_enb & trc_on_chip & tw_valid)
begin
trc_im_addr <= trc_im_addr+1;
if (&trc_im_addr)
trc_wrap <= 1;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trc_jtag_addr <= 0;
else if (take_action_tracemem_a ||
take_no_action_tracemem_a ||
take_action_tracemem_b)
trc_jtag_addr <= take_action_tracemem_a ?
jdo[35 : 19] :
trc_jtag_addr + 1;
end
assign trc_enb = trc_ctrl[0];
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_tw = trc_wrap;
assign tracemem_on = trc_enb;
assign tracemem_trcdata = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_nios2_performance_monitors
;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_nios2_oci (
// inputs:
D_valid,
E_st_data,
E_valid,
F_pc,
address_nxt,
av_ld_data_aligned_filtered,
byteenable_nxt,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugaccess_nxt,
hbreak_enabled,
read_nxt,
reset,
reset_n,
reset_req,
test_ending,
test_has_ended,
write_nxt,
writedata_nxt,
// outputs:
jtag_debug_module_debugaccess_to_roms,
oci_hbreak_req,
oci_ienable,
oci_single_step_mode,
readdata,
resetrequest,
waitrequest
)
;
output jtag_debug_module_debugaccess_to_roms;
output oci_hbreak_req;
output [ 31: 0] oci_ienable;
output oci_single_step_mode;
output [ 31: 0] readdata;
output resetrequest;
output waitrequest;
input D_valid;
input [ 31: 0] E_st_data;
input E_valid;
input [ 26: 0] F_pc;
input [ 8: 0] address_nxt;
input [ 31: 0] av_ld_data_aligned_filtered;
input [ 3: 0] byteenable_nxt;
input clk;
input [ 28: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugaccess_nxt;
input hbreak_enabled;
input read_nxt;
input reset;
input reset_n;
input reset_req;
input test_ending;
input test_has_ended;
input write_nxt;
input [ 31: 0] writedata_nxt;
wire [ 31: 0] MonDReg;
reg [ 8: 0] address;
wire [ 35: 0] atm;
wire [ 31: 0] break_readreg;
reg [ 3: 0] byteenable;
wire clkx2;
wire [ 28: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk_break;
wire dbrk_goto0;
wire dbrk_goto1;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire dbrk_traceme;
wire dbrk_traceoff;
wire dbrk_traceon;
wire dbrk_trigout;
wire [ 29: 0] dct_buffer;
wire [ 3: 0] dct_count;
reg debugaccess;
wire debugack;
wire debugreq;
wire [ 35: 0] dtm;
wire dummy_sink;
wire [ 35: 0] itm;
wire [ 37: 0] jdo;
wire jrst_n;
wire jtag_debug_module_debugaccess_to_roms;
wire monitor_error;
wire monitor_go;
wire monitor_ready;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire [ 31: 0] oci_reg_readdata;
wire oci_single_step_mode;
wire [ 31: 0] ociram_readdata;
wire ocireg_ers;
wire ocireg_mrs;
reg read;
reg [ 31: 0] readdata;
wire resetlatch;
wire resetrequest;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_ocireg;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire tr_clk;
wire [ 17: 0] tr_data;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire [ 15: 0] trc_ctrl;
wire trc_enb;
wire [ 6: 0] trc_im_addr;
wire trc_on;
wire trc_wrap;
wire trigbrktype;
wire trigger_state_0;
wire trigger_state_1;
wire trigout;
wire [ 35: 0] tw;
wire waitrequest;
reg write;
reg [ 31: 0] writedata;
wire xbrk_break;
wire [ 7: 0] xbrk_ctrl0;
wire [ 7: 0] xbrk_ctrl1;
wire [ 7: 0] xbrk_ctrl2;
wire [ 7: 0] xbrk_ctrl3;
wire xbrk_goto0;
wire xbrk_goto1;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
wire xbrk_wrap_traceoff;
limbus_nios2_qsys_0_nios2_oci_debug the_limbus_nios2_qsys_0_nios2_oci_debug
(
.clk (clk),
.dbrk_break (dbrk_break),
.debugack (debugack),
.debugreq (debugreq),
.hbreak_enabled (hbreak_enabled),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_hbreak_req (oci_hbreak_req),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset (reset),
.resetlatch (resetlatch),
.resetrequest (resetrequest),
.st_ready_test_idle (st_ready_test_idle),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocireg (take_action_ocireg),
.xbrk_break (xbrk_break)
);
limbus_nios2_qsys_0_nios2_ocimem the_limbus_nios2_qsys_0_nios2_ocimem
(
.MonDReg (MonDReg),
.address (address),
.byteenable (byteenable),
.clk (clk),
.debugaccess (debugaccess),
.jdo (jdo),
.jrst_n (jrst_n),
.ociram_readdata (ociram_readdata),
.read (read),
.reset_req (reset_req),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata)
);
limbus_nios2_qsys_0_nios2_avalon_reg the_limbus_nios2_qsys_0_nios2_avalon_reg
(
.address (address),
.clk (clk),
.debugaccess (debugaccess),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_ienable (oci_ienable),
.oci_reg_readdata (oci_reg_readdata),
.oci_single_step_mode (oci_single_step_mode),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset_n (reset_n),
.take_action_ocireg (take_action_ocireg),
.write (write),
.writedata (writedata)
);
limbus_nios2_qsys_0_nios2_oci_break the_limbus_nios2_qsys_0_nios2_oci_break
(
.break_readreg (break_readreg),
.clk (clk),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.trigbrktype (trigbrktype),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1)
);
limbus_nios2_qsys_0_nios2_oci_xbrk the_limbus_nios2_qsys_0_nios2_oci_xbrk
(
.D_valid (D_valid),
.E_valid (E_valid),
.F_pc (F_pc),
.clk (clk),
.reset_n (reset_n),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_break (xbrk_break),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_trigout (xbrk_trigout)
);
limbus_nios2_qsys_0_nios2_oci_dbrk the_limbus_nios2_qsys_0_nios2_oci_dbrk
(
.E_st_data (E_st_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dbrk_trigout (dbrk_trigout),
.debugack (debugack),
.reset_n (reset_n)
);
limbus_nios2_qsys_0_nios2_oci_itrace the_limbus_nios2_qsys_0_nios2_oci_itrace
(
.clk (clk),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.itm (itm),
.jdo (jdo),
.jrst_n (jrst_n),
.take_action_tracectrl (take_action_tracectrl),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_on (trc_on),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
limbus_nios2_qsys_0_nios2_oci_dtrace the_limbus_nios2_qsys_0_nios2_oci_dtrace
(
.atm (atm),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.dtm (dtm),
.jrst_n (jrst_n),
.trc_ctrl (trc_ctrl)
);
limbus_nios2_qsys_0_nios2_oci_fifo the_limbus_nios2_qsys_0_nios2_oci_fifo
(
.atm (atm),
.clk (clk),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.dtm (dtm),
.itm (itm),
.jrst_n (jrst_n),
.reset_n (reset_n),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.trc_on (trc_on),
.tw (tw)
);
limbus_nios2_qsys_0_nios2_oci_pib the_limbus_nios2_qsys_0_nios2_oci_pib
(
.clk (clk),
.clkx2 (clkx2),
.jrst_n (jrst_n),
.tr_clk (tr_clk),
.tr_data (tr_data),
.tw (tw)
);
limbus_nios2_qsys_0_nios2_oci_im the_limbus_nios2_qsys_0_nios2_oci_im
(
.clk (clk),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_im_addr (trc_im_addr),
.trc_wrap (trc_wrap),
.tw (tw),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
assign trigout = dbrk_trigout | xbrk_trigout;
assign jtag_debug_module_debugaccess_to_roms = debugack;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
address <= 0;
else
address <= address_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
byteenable <= 0;
else
byteenable <= byteenable_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
writedata <= 0;
else
writedata <= writedata_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
debugaccess <= 0;
else
debugaccess <= debugaccess_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
read <= 0;
else
read <= read ? waitrequest : read_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
write <= 0;
else
write <= write ? waitrequest : write_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
readdata <= 0;
else
readdata <= address[8] ? oci_reg_readdata : ociram_readdata;
end
limbus_nios2_qsys_0_jtag_debug_module_wrapper the_limbus_nios2_qsys_0_jtag_debug_module_wrapper
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.clk (clk),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.st_ready_test_idle (st_ready_test_idle),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1)
);
//dummy sink, which is an e_mux
assign dummy_sink = tr_clk |
tr_data |
trigout |
debugack;
assign debugreq = 0;
assign clkx2 = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0 (
// inputs:
clk,
d_irq,
d_readdata,
d_waitrequest,
i_readdata,
i_waitrequest,
jtag_debug_module_address,
jtag_debug_module_byteenable,
jtag_debug_module_debugaccess,
jtag_debug_module_read,
jtag_debug_module_write,
jtag_debug_module_writedata,
reset_n,
reset_req,
// outputs:
d_address,
d_byteenable,
d_read,
d_write,
d_writedata,
i_address,
i_read,
jtag_debug_module_debugaccess_to_roms,
jtag_debug_module_readdata,
jtag_debug_module_resetrequest,
jtag_debug_module_waitrequest,
no_ci_readra
)
;
output [ 28: 0] d_address;
output [ 3: 0] d_byteenable;
output d_read;
output d_write;
output [ 31: 0] d_writedata;
output [ 28: 0] i_address;
output i_read;
output jtag_debug_module_debugaccess_to_roms;
output [ 31: 0] jtag_debug_module_readdata;
output jtag_debug_module_resetrequest;
output jtag_debug_module_waitrequest;
output no_ci_readra;
input clk;
input [ 31: 0] d_irq;
input [ 31: 0] d_readdata;
input d_waitrequest;
input [ 31: 0] i_readdata;
input i_waitrequest;
input [ 8: 0] jtag_debug_module_address;
input [ 3: 0] jtag_debug_module_byteenable;
input jtag_debug_module_debugaccess;
input jtag_debug_module_read;
input jtag_debug_module_write;
input [ 31: 0] jtag_debug_module_writedata;
input reset_n;
input reset_req;
wire [ 1: 0] D_compare_op;
wire D_ctrl_alu_force_xor;
wire D_ctrl_alu_signed_comparison;
wire D_ctrl_alu_subtract;
wire D_ctrl_b_is_dst;
wire D_ctrl_br;
wire D_ctrl_br_cmp;
wire D_ctrl_br_uncond;
wire D_ctrl_break;
wire D_ctrl_crst;
wire D_ctrl_custom;
wire D_ctrl_custom_multi;
wire D_ctrl_exception;
wire D_ctrl_force_src2_zero;
wire D_ctrl_hi_imm16;
wire D_ctrl_ignore_dst;
wire D_ctrl_implicit_dst_eretaddr;
wire D_ctrl_implicit_dst_retaddr;
wire D_ctrl_jmp_direct;
wire D_ctrl_jmp_indirect;
wire D_ctrl_ld;
wire D_ctrl_ld_io;
wire D_ctrl_ld_non_io;
wire D_ctrl_ld_signed;
wire D_ctrl_logic;
wire D_ctrl_rdctl_inst;
wire D_ctrl_retaddr;
wire D_ctrl_rot_right;
wire D_ctrl_shift_logical;
wire D_ctrl_shift_right_arith;
wire D_ctrl_shift_rot;
wire D_ctrl_shift_rot_right;
wire D_ctrl_src2_choose_imm;
wire D_ctrl_st;
wire D_ctrl_uncond_cti_non_br;
wire D_ctrl_unsigned_lo_imm16;
wire D_ctrl_wrctl_inst;
wire [ 4: 0] D_dst_regnum;
wire [ 55: 0] D_inst;
reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 4: 0] D_iw_a;
wire [ 4: 0] D_iw_b;
wire [ 4: 0] D_iw_c;
wire [ 2: 0] D_iw_control_regnum;
wire [ 7: 0] D_iw_custom_n;
wire D_iw_custom_readra;
wire D_iw_custom_readrb;
wire D_iw_custom_writerc;
wire [ 15: 0] D_iw_imm16;
wire [ 25: 0] D_iw_imm26;
wire [ 4: 0] D_iw_imm5;
wire [ 1: 0] D_iw_memsz;
wire [ 5: 0] D_iw_op;
wire [ 5: 0] D_iw_opx;
wire [ 4: 0] D_iw_shift_imm5;
wire [ 4: 0] D_iw_trap_break_imm5;
wire [ 26: 0] D_jmp_direct_target_waddr;
wire [ 1: 0] D_logic_op;
wire [ 1: 0] D_logic_op_raw;
wire D_mem16;
wire D_mem32;
wire D_mem8;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
reg D_valid;
wire [ 55: 0] D_vinst;
wire D_wr_dst_reg;
wire [ 31: 0] E_alu_result;
reg E_alu_sub;
wire [ 32: 0] E_arith_result;
wire [ 31: 0] E_arith_src1;
wire [ 31: 0] E_arith_src2;
wire E_ci_multi_stall;
wire [ 31: 0] E_ci_result;
wire E_cmp_result;
wire [ 31: 0] E_control_rd_data;
wire E_eq;
reg E_invert_arith_src_msb;
wire E_ld_stall;
wire [ 31: 0] E_logic_result;
wire E_logic_result_is_0;
wire E_lt;
wire [ 28: 0] E_mem_baddr;
wire [ 3: 0] E_mem_byte_en;
reg E_new_inst;
reg [ 4: 0] E_shift_rot_cnt;
wire [ 4: 0] E_shift_rot_cnt_nxt;
wire E_shift_rot_done;
wire E_shift_rot_fill_bit;
reg [ 31: 0] E_shift_rot_result;
wire [ 31: 0] E_shift_rot_result_nxt;
wire E_shift_rot_stall;
reg [ 31: 0] E_src1;
reg [ 31: 0] E_src2;
wire [ 31: 0] E_st_data;
wire E_st_stall;
wire E_stall;
reg E_valid;
wire [ 55: 0] E_vinst;
wire E_wrctl_bstatus;
wire E_wrctl_estatus;
wire E_wrctl_ienable;
wire E_wrctl_status;
wire [ 31: 0] F_av_iw;
wire [ 4: 0] F_av_iw_a;
wire [ 4: 0] F_av_iw_b;
wire [ 4: 0] F_av_iw_c;
wire [ 2: 0] F_av_iw_control_regnum;
wire [ 7: 0] F_av_iw_custom_n;
wire F_av_iw_custom_readra;
wire F_av_iw_custom_readrb;
wire F_av_iw_custom_writerc;
wire [ 15: 0] F_av_iw_imm16;
wire [ 25: 0] F_av_iw_imm26;
wire [ 4: 0] F_av_iw_imm5;
wire [ 1: 0] F_av_iw_memsz;
wire [ 5: 0] F_av_iw_op;
wire [ 5: 0] F_av_iw_opx;
wire [ 4: 0] F_av_iw_shift_imm5;
wire [ 4: 0] F_av_iw_trap_break_imm5;
wire F_av_mem16;
wire F_av_mem32;
wire F_av_mem8;
wire [ 55: 0] F_inst;
wire [ 31: 0] F_iw;
wire [ 4: 0] F_iw_a;
wire [ 4: 0] F_iw_b;
wire [ 4: 0] F_iw_c;
wire [ 2: 0] F_iw_control_regnum;
wire [ 7: 0] F_iw_custom_n;
wire F_iw_custom_readra;
wire F_iw_custom_readrb;
wire F_iw_custom_writerc;
wire [ 15: 0] F_iw_imm16;
wire [ 25: 0] F_iw_imm26;
wire [ 4: 0] F_iw_imm5;
wire [ 1: 0] F_iw_memsz;
wire [ 5: 0] F_iw_op;
wire [ 5: 0] F_iw_opx;
wire [ 4: 0] F_iw_shift_imm5;
wire [ 4: 0] F_iw_trap_break_imm5;
wire F_jmp_direct_pc_hi;
wire F_mem16;
wire F_mem32;
wire F_mem8;
wire F_op_add;
wire F_op_addi;
wire F_op_and;
wire F_op_andhi;
wire F_op_andi;
wire F_op_beq;
wire F_op_bge;
wire F_op_bgeu;
wire F_op_blt;
wire F_op_bltu;
wire F_op_bne;
wire F_op_br;
wire F_op_break;
wire F_op_bret;
wire F_op_call;
wire F_op_callr;
wire F_op_cmpeq;
wire F_op_cmpeqi;
wire F_op_cmpge;
wire F_op_cmpgei;
wire F_op_cmpgeu;
wire F_op_cmpgeui;
wire F_op_cmplt;
wire F_op_cmplti;
wire F_op_cmpltu;
wire F_op_cmpltui;
wire F_op_cmpne;
wire F_op_cmpnei;
wire F_op_crst;
wire F_op_custom;
wire F_op_div;
wire F_op_divu;
wire F_op_eret;
wire F_op_flushd;
wire F_op_flushda;
wire F_op_flushi;
wire F_op_flushp;
wire F_op_hbreak;
wire F_op_initd;
wire F_op_initda;
wire F_op_initi;
wire F_op_intr;
wire F_op_jmp;
wire F_op_jmpi;
wire F_op_ldb;
wire F_op_ldbio;
wire F_op_ldbu;
wire F_op_ldbuio;
wire F_op_ldh;
wire F_op_ldhio;
wire F_op_ldhu;
wire F_op_ldhuio;
wire F_op_ldl;
wire F_op_ldw;
wire F_op_ldwio;
wire F_op_mul;
wire F_op_muli;
wire F_op_mulxss;
wire F_op_mulxsu;
wire F_op_mulxuu;
wire F_op_nextpc;
wire F_op_nor;
wire F_op_opx;
wire F_op_or;
wire F_op_orhi;
wire F_op_ori;
wire F_op_rdctl;
wire F_op_rdprs;
wire F_op_ret;
wire F_op_rol;
wire F_op_roli;
wire F_op_ror;
wire F_op_rsv02;
wire F_op_rsv09;
wire F_op_rsv10;
wire F_op_rsv17;
wire F_op_rsv18;
wire F_op_rsv25;
wire F_op_rsv26;
wire F_op_rsv33;
wire F_op_rsv34;
wire F_op_rsv41;
wire F_op_rsv42;
wire F_op_rsv49;
wire F_op_rsv57;
wire F_op_rsv61;
wire F_op_rsv62;
wire F_op_rsv63;
wire F_op_rsvx00;
wire F_op_rsvx10;
wire F_op_rsvx15;
wire F_op_rsvx17;
wire F_op_rsvx21;
wire F_op_rsvx25;
wire F_op_rsvx33;
wire F_op_rsvx34;
wire F_op_rsvx35;
wire F_op_rsvx42;
wire F_op_rsvx43;
wire F_op_rsvx44;
wire F_op_rsvx47;
wire F_op_rsvx50;
wire F_op_rsvx51;
wire F_op_rsvx55;
wire F_op_rsvx56;
wire F_op_rsvx60;
wire F_op_rsvx63;
wire F_op_sll;
wire F_op_slli;
wire F_op_sra;
wire F_op_srai;
wire F_op_srl;
wire F_op_srli;
wire F_op_stb;
wire F_op_stbio;
wire F_op_stc;
wire F_op_sth;
wire F_op_sthio;
wire F_op_stw;
wire F_op_stwio;
wire F_op_sub;
wire F_op_sync;
wire F_op_trap;
wire F_op_wrctl;
wire F_op_wrprs;
wire F_op_xor;
wire F_op_xorhi;
wire F_op_xori;
reg [ 26: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire F_pc_en;
wire [ 26: 0] F_pc_no_crst_nxt;
wire [ 26: 0] F_pc_nxt;
wire [ 26: 0] F_pc_plus_one;
wire [ 1: 0] F_pc_sel_nxt;
wire [ 28: 0] F_pcb;
wire [ 28: 0] F_pcb_nxt;
wire [ 28: 0] F_pcb_plus_four;
wire F_valid;
wire [ 55: 0] F_vinst;
reg [ 1: 0] R_compare_op;
reg R_ctrl_alu_force_xor;
wire R_ctrl_alu_force_xor_nxt;
reg R_ctrl_alu_signed_comparison;
wire R_ctrl_alu_signed_comparison_nxt;
reg R_ctrl_alu_subtract;
wire R_ctrl_alu_subtract_nxt;
reg R_ctrl_b_is_dst;
wire R_ctrl_b_is_dst_nxt;
reg R_ctrl_br;
reg R_ctrl_br_cmp;
wire R_ctrl_br_cmp_nxt;
wire R_ctrl_br_nxt;
reg R_ctrl_br_uncond;
wire R_ctrl_br_uncond_nxt;
reg R_ctrl_break;
wire R_ctrl_break_nxt;
reg R_ctrl_crst;
wire R_ctrl_crst_nxt;
reg R_ctrl_custom;
reg R_ctrl_custom_multi;
wire R_ctrl_custom_multi_nxt;
wire R_ctrl_custom_nxt;
reg R_ctrl_exception;
wire R_ctrl_exception_nxt;
reg R_ctrl_force_src2_zero;
wire R_ctrl_force_src2_zero_nxt;
reg R_ctrl_hi_imm16;
wire R_ctrl_hi_imm16_nxt;
reg R_ctrl_ignore_dst;
wire R_ctrl_ignore_dst_nxt;
reg R_ctrl_implicit_dst_eretaddr;
wire R_ctrl_implicit_dst_eretaddr_nxt;
reg R_ctrl_implicit_dst_retaddr;
wire R_ctrl_implicit_dst_retaddr_nxt;
reg R_ctrl_jmp_direct;
wire R_ctrl_jmp_direct_nxt;
reg R_ctrl_jmp_indirect;
wire R_ctrl_jmp_indirect_nxt;
reg R_ctrl_ld;
reg R_ctrl_ld_io;
wire R_ctrl_ld_io_nxt;
reg R_ctrl_ld_non_io;
wire R_ctrl_ld_non_io_nxt;
wire R_ctrl_ld_nxt;
reg R_ctrl_ld_signed;
wire R_ctrl_ld_signed_nxt;
reg R_ctrl_logic;
wire R_ctrl_logic_nxt;
reg R_ctrl_rdctl_inst;
wire R_ctrl_rdctl_inst_nxt;
reg R_ctrl_retaddr;
wire R_ctrl_retaddr_nxt;
reg R_ctrl_rot_right;
wire R_ctrl_rot_right_nxt;
reg R_ctrl_shift_logical;
wire R_ctrl_shift_logical_nxt;
reg R_ctrl_shift_right_arith;
wire R_ctrl_shift_right_arith_nxt;
reg R_ctrl_shift_rot;
wire R_ctrl_shift_rot_nxt;
reg R_ctrl_shift_rot_right;
wire R_ctrl_shift_rot_right_nxt;
reg R_ctrl_src2_choose_imm;
wire R_ctrl_src2_choose_imm_nxt;
reg R_ctrl_st;
wire R_ctrl_st_nxt;
reg R_ctrl_uncond_cti_non_br;
wire R_ctrl_uncond_cti_non_br_nxt;
reg R_ctrl_unsigned_lo_imm16;
wire R_ctrl_unsigned_lo_imm16_nxt;
reg R_ctrl_wrctl_inst;
wire R_ctrl_wrctl_inst_nxt;
reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire R_en;
reg [ 1: 0] R_logic_op;
wire [ 31: 0] R_rf_a;
wire [ 31: 0] R_rf_b;
wire [ 31: 0] R_src1;
wire [ 31: 0] R_src2;
wire [ 15: 0] R_src2_hi;
wire [ 15: 0] R_src2_lo;
reg R_src2_use_imm;
wire [ 7: 0] R_stb_data;
wire [ 15: 0] R_sth_data;
reg R_valid;
wire [ 55: 0] R_vinst;
reg R_wr_dst_reg;
reg [ 31: 0] W_alu_result;
wire W_br_taken;
reg W_bstatus_reg;
wire W_bstatus_reg_inst_nxt;
wire W_bstatus_reg_nxt;
reg W_cmp_result;
reg [ 31: 0] W_control_rd_data;
wire [ 31: 0] W_cpuid_reg;
reg W_estatus_reg;
wire W_estatus_reg_inst_nxt;
wire W_estatus_reg_nxt;
reg [ 31: 0] W_ienable_reg;
wire [ 31: 0] W_ienable_reg_nxt;
reg [ 31: 0] W_ipending_reg;
wire [ 31: 0] W_ipending_reg_nxt;
wire [ 28: 0] W_mem_baddr;
wire [ 31: 0] W_rf_wr_data;
wire W_rf_wren;
wire W_status_reg;
reg W_status_reg_pie;
wire W_status_reg_pie_inst_nxt;
wire W_status_reg_pie_nxt;
reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 55: 0] W_vinst;
wire [ 31: 0] W_wr_data;
wire [ 31: 0] W_wr_data_non_zero;
wire av_fill_bit;
reg [ 1: 0] av_ld_align_cycle;
wire [ 1: 0] av_ld_align_cycle_nxt;
wire av_ld_align_one_more_cycle;
reg av_ld_aligning_data;
wire av_ld_aligning_data_nxt;
reg [ 7: 0] av_ld_byte0_data;
wire [ 7: 0] av_ld_byte0_data_nxt;
reg [ 7: 0] av_ld_byte1_data;
wire av_ld_byte1_data_en;
wire [ 7: 0] av_ld_byte1_data_nxt;
reg [ 7: 0] av_ld_byte2_data;
wire [ 7: 0] av_ld_byte2_data_nxt;
reg [ 7: 0] av_ld_byte3_data;
wire [ 7: 0] av_ld_byte3_data_nxt;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire [ 31: 0] av_ld_data_aligned_unfiltered;
wire av_ld_done;
wire av_ld_extend;
wire av_ld_getting_data;
wire av_ld_rshift8;
reg av_ld_waiting_for_data;
wire av_ld_waiting_for_data_nxt;
wire av_sign_bit;
wire [ 28: 0] d_address;
reg [ 3: 0] d_byteenable;
reg d_read;
wire d_read_nxt;
reg d_write;
wire d_write_nxt;
reg [ 31: 0] d_writedata;
reg hbreak_enabled;
reg hbreak_pending;
wire hbreak_pending_nxt;
wire hbreak_req;
wire [ 28: 0] i_address;
reg i_read;
wire i_read_nxt;
wire [ 31: 0] iactive;
wire intr_req;
wire jtag_debug_module_clk;
wire jtag_debug_module_debugaccess_to_roms;
wire [ 31: 0] jtag_debug_module_readdata;
wire jtag_debug_module_reset;
wire jtag_debug_module_resetrequest;
wire jtag_debug_module_waitrequest;
wire no_ci_readra;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire oci_single_step_mode;
wire oci_tb_hbreak_req;
wire test_ending;
wire test_has_ended;
reg wait_for_one_post_bret_inst;
//the_limbus_nios2_qsys_0_test_bench, which is an e_instance
limbus_nios2_qsys_0_test_bench the_limbus_nios2_qsys_0_test_bench
(
.D_iw (D_iw),
.D_iw_op (D_iw_op),
.D_iw_opx (D_iw_opx),
.D_valid (D_valid),
.E_valid (E_valid),
.F_pcb (F_pcb),
.F_valid (F_valid),
.R_ctrl_ld (R_ctrl_ld),
.R_ctrl_ld_non_io (R_ctrl_ld_non_io),
.R_dst_regnum (R_dst_regnum),
.R_wr_dst_reg (R_wr_dst_reg),
.W_valid (W_valid),
.W_vinst (W_vinst),
.W_wr_data (W_wr_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered),
.clk (clk),
.d_address (d_address),
.d_byteenable (d_byteenable),
.d_read (d_read),
.d_write (d_write),
.i_address (i_address),
.i_read (i_read),
.i_readdata (i_readdata),
.i_waitrequest (i_waitrequest),
.reset_n (reset_n),
.test_has_ended (test_has_ended)
);
assign F_av_iw_a = F_av_iw[31 : 27];
assign F_av_iw_b = F_av_iw[26 : 22];
assign F_av_iw_c = F_av_iw[21 : 17];
assign F_av_iw_custom_n = F_av_iw[13 : 6];
assign F_av_iw_custom_readra = F_av_iw[16];
assign F_av_iw_custom_readrb = F_av_iw[15];
assign F_av_iw_custom_writerc = F_av_iw[14];
assign F_av_iw_opx = F_av_iw[16 : 11];
assign F_av_iw_op = F_av_iw[5 : 0];
assign F_av_iw_shift_imm5 = F_av_iw[10 : 6];
assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm16 = F_av_iw[21 : 6];
assign F_av_iw_imm26 = F_av_iw[31 : 6];
assign F_av_iw_memsz = F_av_iw[4 : 3];
assign F_av_iw_control_regnum = F_av_iw[8 : 6];
assign F_av_mem8 = F_av_iw_memsz == 2'b00;
assign F_av_mem16 = F_av_iw_memsz == 2'b01;
assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1;
assign F_iw_a = F_iw[31 : 27];
assign F_iw_b = F_iw[26 : 22];
assign F_iw_c = F_iw[21 : 17];
assign F_iw_custom_n = F_iw[13 : 6];
assign F_iw_custom_readra = F_iw[16];
assign F_iw_custom_readrb = F_iw[15];
assign F_iw_custom_writerc = F_iw[14];
assign F_iw_opx = F_iw[16 : 11];
assign F_iw_op = F_iw[5 : 0];
assign F_iw_shift_imm5 = F_iw[10 : 6];
assign F_iw_trap_break_imm5 = F_iw[10 : 6];
assign F_iw_imm5 = F_iw[10 : 6];
assign F_iw_imm16 = F_iw[21 : 6];
assign F_iw_imm26 = F_iw[31 : 6];
assign F_iw_memsz = F_iw[4 : 3];
assign F_iw_control_regnum = F_iw[8 : 6];
assign F_mem8 = F_iw_memsz == 2'b00;
assign F_mem16 = F_iw_memsz == 2'b01;
assign F_mem32 = F_iw_memsz[1] == 1'b1;
assign D_iw_a = D_iw[31 : 27];
assign D_iw_b = D_iw[26 : 22];
assign D_iw_c = D_iw[21 : 17];
assign D_iw_custom_n = D_iw[13 : 6];
assign D_iw_custom_readra = D_iw[16];
assign D_iw_custom_readrb = D_iw[15];
assign D_iw_custom_writerc = D_iw[14];
assign D_iw_opx = D_iw[16 : 11];
assign D_iw_op = D_iw[5 : 0];
assign D_iw_shift_imm5 = D_iw[10 : 6];
assign D_iw_trap_break_imm5 = D_iw[10 : 6];
assign D_iw_imm5 = D_iw[10 : 6];
assign D_iw_imm16 = D_iw[21 : 6];
assign D_iw_imm26 = D_iw[31 : 6];
assign D_iw_memsz = D_iw[4 : 3];
assign D_iw_control_regnum = D_iw[8 : 6];
assign D_mem8 = D_iw_memsz == 2'b00;
assign D_mem16 = D_iw_memsz == 2'b01;
assign D_mem32 = D_iw_memsz[1] == 1'b1;
assign F_op_call = F_iw_op == 0;
assign F_op_jmpi = F_iw_op == 1;
assign F_op_ldbu = F_iw_op == 3;
assign F_op_addi = F_iw_op == 4;
assign F_op_stb = F_iw_op == 5;
assign F_op_br = F_iw_op == 6;
assign F_op_ldb = F_iw_op == 7;
assign F_op_cmpgei = F_iw_op == 8;
assign F_op_ldhu = F_iw_op == 11;
assign F_op_andi = F_iw_op == 12;
assign F_op_sth = F_iw_op == 13;
assign F_op_bge = F_iw_op == 14;
assign F_op_ldh = F_iw_op == 15;
assign F_op_cmplti = F_iw_op == 16;
assign F_op_initda = F_iw_op == 19;
assign F_op_ori = F_iw_op == 20;
assign F_op_stw = F_iw_op == 21;
assign F_op_blt = F_iw_op == 22;
assign F_op_ldw = F_iw_op == 23;
assign F_op_cmpnei = F_iw_op == 24;
assign F_op_flushda = F_iw_op == 27;
assign F_op_xori = F_iw_op == 28;
assign F_op_stc = F_iw_op == 29;
assign F_op_bne = F_iw_op == 30;
assign F_op_ldl = F_iw_op == 31;
assign F_op_cmpeqi = F_iw_op == 32;
assign F_op_ldbuio = F_iw_op == 35;
assign F_op_muli = F_iw_op == 36;
assign F_op_stbio = F_iw_op == 37;
assign F_op_beq = F_iw_op == 38;
assign F_op_ldbio = F_iw_op == 39;
assign F_op_cmpgeui = F_iw_op == 40;
assign F_op_ldhuio = F_iw_op == 43;
assign F_op_andhi = F_iw_op == 44;
assign F_op_sthio = F_iw_op == 45;
assign F_op_bgeu = F_iw_op == 46;
assign F_op_ldhio = F_iw_op == 47;
assign F_op_cmpltui = F_iw_op == 48;
assign F_op_initd = F_iw_op == 51;
assign F_op_orhi = F_iw_op == 52;
assign F_op_stwio = F_iw_op == 53;
assign F_op_bltu = F_iw_op == 54;
assign F_op_ldwio = F_iw_op == 55;
assign F_op_rdprs = F_iw_op == 56;
assign F_op_flushd = F_iw_op == 59;
assign F_op_xorhi = F_iw_op == 60;
assign F_op_rsv02 = F_iw_op == 2;
assign F_op_rsv09 = F_iw_op == 9;
assign F_op_rsv10 = F_iw_op == 10;
assign F_op_rsv17 = F_iw_op == 17;
assign F_op_rsv18 = F_iw_op == 18;
assign F_op_rsv25 = F_iw_op == 25;
assign F_op_rsv26 = F_iw_op == 26;
assign F_op_rsv33 = F_iw_op == 33;
assign F_op_rsv34 = F_iw_op == 34;
assign F_op_rsv41 = F_iw_op == 41;
assign F_op_rsv42 = F_iw_op == 42;
assign F_op_rsv49 = F_iw_op == 49;
assign F_op_rsv57 = F_iw_op == 57;
assign F_op_rsv61 = F_iw_op == 61;
assign F_op_rsv62 = F_iw_op == 62;
assign F_op_rsv63 = F_iw_op == 63;
assign F_op_eret = F_op_opx & (F_iw_opx == 1);
assign F_op_roli = F_op_opx & (F_iw_opx == 2);
assign F_op_rol = F_op_opx & (F_iw_opx == 3);
assign F_op_flushp = F_op_opx & (F_iw_opx == 4);
assign F_op_ret = F_op_opx & (F_iw_opx == 5);
assign F_op_nor = F_op_opx & (F_iw_opx == 6);
assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7);
assign F_op_cmpge = F_op_opx & (F_iw_opx == 8);
assign F_op_bret = F_op_opx & (F_iw_opx == 9);
assign F_op_ror = F_op_opx & (F_iw_opx == 11);
assign F_op_flushi = F_op_opx & (F_iw_opx == 12);
assign F_op_jmp = F_op_opx & (F_iw_opx == 13);
assign F_op_and = F_op_opx & (F_iw_opx == 14);
assign F_op_cmplt = F_op_opx & (F_iw_opx == 16);
assign F_op_slli = F_op_opx & (F_iw_opx == 18);
assign F_op_sll = F_op_opx & (F_iw_opx == 19);
assign F_op_wrprs = F_op_opx & (F_iw_opx == 20);
assign F_op_or = F_op_opx & (F_iw_opx == 22);
assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23);
assign F_op_cmpne = F_op_opx & (F_iw_opx == 24);
assign F_op_srli = F_op_opx & (F_iw_opx == 26);
assign F_op_srl = F_op_opx & (F_iw_opx == 27);
assign F_op_nextpc = F_op_opx & (F_iw_opx == 28);
assign F_op_callr = F_op_opx & (F_iw_opx == 29);
assign F_op_xor = F_op_opx & (F_iw_opx == 30);
assign F_op_mulxss = F_op_opx & (F_iw_opx == 31);
assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32);
assign F_op_divu = F_op_opx & (F_iw_opx == 36);
assign F_op_div = F_op_opx & (F_iw_opx == 37);
assign F_op_rdctl = F_op_opx & (F_iw_opx == 38);
assign F_op_mul = F_op_opx & (F_iw_opx == 39);
assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40);
assign F_op_initi = F_op_opx & (F_iw_opx == 41);
assign F_op_trap = F_op_opx & (F_iw_opx == 45);
assign F_op_wrctl = F_op_opx & (F_iw_opx == 46);
assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48);
assign F_op_add = F_op_opx & (F_iw_opx == 49);
assign F_op_break = F_op_opx & (F_iw_opx == 52);
assign F_op_hbreak = F_op_opx & (F_iw_opx == 53);
assign F_op_sync = F_op_opx & (F_iw_opx == 54);
assign F_op_sub = F_op_opx & (F_iw_opx == 57);
assign F_op_srai = F_op_opx & (F_iw_opx == 58);
assign F_op_sra = F_op_opx & (F_iw_opx == 59);
assign F_op_intr = F_op_opx & (F_iw_opx == 61);
assign F_op_crst = F_op_opx & (F_iw_opx == 62);
assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0);
assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10);
assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15);
assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17);
assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21);
assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25);
assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33);
assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34);
assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35);
assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42);
assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43);
assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44);
assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47);
assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50);
assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51);
assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55);
assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56);
assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60);
assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63);
assign F_op_opx = F_iw_op == 58;
assign F_op_custom = F_iw_op == 50;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
assign R_en = 1'b1;
assign E_ci_result = 0;
//custom_instruction_master, which is an e_custom_instruction_master
assign no_ci_readra = 1'b0;
assign E_ci_multi_stall = 1'b0;
assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000000000001;
assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 :
R_ctrl_break ? 2'b01 :
(W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 :
2'b11;
assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 67108872 :
(F_pc_sel_nxt == 2'b01)? 67240456 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[28 : 2] :
F_pc_plus_one;
assign F_pc_nxt = F_pc_no_crst_nxt;
assign F_pcb_nxt = {F_pc_nxt, 2'b00};
assign F_pc_en = W_valid;
assign F_pc_plus_one = F_pc + 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
F_pc <= 67108864;
else if (F_pc_en)
F_pc <= F_pc_nxt;
end
assign F_pcb = {F_pc, 2'b00};
assign F_pcb_plus_four = {F_pc_plus_one, 2'b00};
assign F_valid = i_read & ~i_waitrequest;
assign i_read_nxt = W_valid | (i_read & i_waitrequest);
assign i_address = {F_pc, 2'b00};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
i_read <= 1'b1;
else
i_read <= i_read_nxt;
end
assign oci_tb_hbreak_req = oci_hbreak_req;
assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid);
assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled
: hbreak_req;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wait_for_one_post_bret_inst <= 1'b0;
else
wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_pending <= 1'b0;
else
hbreak_pending <= hbreak_pending_nxt;
end
assign intr_req = W_status_reg_pie & (W_ipending_reg != 0);
assign F_av_iw = i_readdata;
assign F_iw = hbreak_req ? 4040762 :
1'b0 ? 127034 :
intr_req ? 3926074 :
F_av_iw;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_iw <= 0;
else if (F_valid)
D_iw <= F_iw;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_valid <= 0;
else
D_valid <= F_valid;
end
assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 :
D_ctrl_implicit_dst_eretaddr ? 5'd29 :
D_ctrl_b_is_dst ? D_iw_b :
D_iw_c;
assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst;
assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw;
assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign F_jmp_direct_pc_hi = F_pc[26];
assign D_jmp_direct_target_waddr = {F_jmp_direct_pc_hi, D_iw[31 : 6]};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_valid <= 0;
else
R_valid <= D_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_wr_dst_reg <= 0;
else
R_wr_dst_reg <= D_wr_dst_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_dst_regnum <= 0;
else
R_dst_regnum <= D_dst_regnum;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_logic_op <= 0;
else
R_logic_op <= D_logic_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_compare_op <= 0;
else
R_compare_op <= D_compare_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_src2_use_imm <= 0;
else
R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid);
end
assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n;
assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data;
//limbus_nios2_qsys_0_register_bank_a, which is an nios_sdp_ram
limbus_nios2_qsys_0_register_bank_a_module limbus_nios2_qsys_0_register_bank_a
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_a),
.rdaddress (D_iw_a),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam limbus_nios2_qsys_0_register_bank_a.lpm_file = "limbus_nios2_qsys_0_rf_ram_a.dat";
`else
defparam limbus_nios2_qsys_0_register_bank_a.lpm_file = "limbus_nios2_qsys_0_rf_ram_a.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam limbus_nios2_qsys_0_register_bank_a.lpm_file = "limbus_nios2_qsys_0_rf_ram_a.mif";
//synthesis read_comments_as_HDL off
//limbus_nios2_qsys_0_register_bank_b, which is an nios_sdp_ram
limbus_nios2_qsys_0_register_bank_b_module limbus_nios2_qsys_0_register_bank_b
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_b),
.rdaddress (D_iw_b),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam limbus_nios2_qsys_0_register_bank_b.lpm_file = "limbus_nios2_qsys_0_rf_ram_b.dat";
`else
defparam limbus_nios2_qsys_0_register_bank_b.lpm_file = "limbus_nios2_qsys_0_rf_ram_b.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam limbus_nios2_qsys_0_register_bank_b.lpm_file = "limbus_nios2_qsys_0_rf_ram_b.mif";
//synthesis read_comments_as_HDL off
assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} :
((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} :
R_rf_a;
assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 :
(R_src2_use_imm)? D_iw_imm16 :
R_rf_b[15 : 0];
assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 :
(R_ctrl_hi_imm16)? D_iw_imm16 :
(R_src2_use_imm)? {16 {D_iw_imm16[15]}} :
R_rf_b[31 : 16];
assign R_src2 = {R_src2_hi, R_src2_lo};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_valid <= 0;
else
E_valid <= R_valid | E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_new_inst <= 0;
else
E_new_inst <= R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src1 <= 0;
else
E_src1 <= R_src1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src2 <= 0;
else
E_src2 <= R_src2;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_invert_arith_src_msb <= 0;
else
E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_alu_sub <= 0;
else
E_alu_sub <= D_ctrl_alu_subtract & R_valid;
end
assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall;
assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb,
E_src1[30 : 0]};
assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb,
E_src2[30 : 0]};
assign E_arith_result = E_alu_sub ?
E_arith_src1 - E_arith_src2 :
E_arith_src1 + E_arith_src2;
assign E_mem_baddr = E_arith_result[28 : 0];
assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
(R_logic_op == 2'b01)? (E_src1 & E_src2) :
(R_logic_op == 2'b10)? (E_src1 | E_src2) :
(E_src1 ^ E_src2);
assign E_logic_result_is_0 = E_logic_result == 0;
assign E_eq = E_logic_result_is_0;
assign E_lt = E_arith_result[32];
assign E_cmp_result = (R_compare_op == 2'b00)? E_eq :
(R_compare_op == 2'b01)? ~E_lt :
(R_compare_op == 2'b10)? E_lt :
~E_eq;
assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1;
assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst;
assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done;
assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 :
(R_ctrl_rot_right ? E_shift_rot_result[0] :
E_shift_rot_result[31]);
assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 :
(R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} :
{E_shift_rot_result[30 : 0], E_shift_rot_fill_bit};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_result <= 0;
else
E_shift_rot_result <= E_shift_rot_result_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_cnt <= 0;
else
E_shift_rot_cnt <= E_shift_rot_cnt_nxt;
end
assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg :
(D_iw_control_regnum == 3'd1)? W_estatus_reg :
(D_iw_control_regnum == 3'd2)? W_bstatus_reg :
(D_iw_control_regnum == 3'd3)? W_ienable_reg :
(D_iw_control_regnum == 3'd4)? W_ipending_reg :
W_cpuid_reg;
assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 :
(R_ctrl_shift_rot)? E_shift_rot_result :
(R_ctrl_logic)? E_logic_result :
(R_ctrl_custom)? E_ci_result :
E_arith_result;
assign R_stb_data = R_rf_b[7 : 0];
assign R_sth_data = R_rf_b[15 : 0];
assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} :
(D_mem16)? {R_sth_data, R_sth_data} :
R_rf_b;
assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 :
4'b1111;
assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest);
assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst);
assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest);
assign E_st_stall = d_write_nxt;
assign d_address = W_mem_baddr;
assign av_ld_getting_data = d_read & ~d_waitrequest;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_read <= 0;
else
d_read <= d_read_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_writedata <= 0;
else
d_writedata <= E_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_byteenable <= 0;
else
d_byteenable <= E_mem_byte_en;
end
assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1);
assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3);
assign av_ld_aligning_data_nxt = av_ld_aligning_data ?
~av_ld_align_one_more_cycle :
(~D_mem32 & av_ld_getting_data);
assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ?
~av_ld_getting_data :
(R_ctrl_ld & E_new_inst);
assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt);
assign av_ld_rshift8 = av_ld_aligning_data &
(av_ld_align_cycle < (W_mem_baddr[1 : 0]));
assign av_ld_extend = av_ld_aligning_data;
assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data :
av_ld_extend ? av_ld_byte0_data :
d_readdata[7 : 0];
assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[15 : 8];
assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[23 : 16];
assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[31 : 24];
assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8);
assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data,
av_ld_byte1_data, av_ld_byte0_data};
assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7];
assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_align_cycle <= 0;
else
av_ld_align_cycle <= av_ld_align_cycle_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_waiting_for_data <= 0;
else
av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_aligning_data <= 0;
else
av_ld_aligning_data <= av_ld_aligning_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte0_data <= 0;
else
av_ld_byte0_data <= av_ld_byte0_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte1_data <= 0;
else if (av_ld_byte1_data_en)
av_ld_byte1_data <= av_ld_byte1_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte2_data <= 0;
else
av_ld_byte2_data <= av_ld_byte2_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte3_data <= 0;
else
av_ld_byte3_data <= av_ld_byte3_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid <= 0;
else
W_valid <= E_valid & ~E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_control_rd_data <= 0;
else
W_control_rd_data <= E_control_rd_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cmp_result <= 0;
else
W_cmp_result <= E_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_alu_result <= 0;
else
W_alu_result <= E_alu_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_status_reg_pie <= 0;
else
W_status_reg_pie <= W_status_reg_pie_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_estatus_reg <= 0;
else
W_estatus_reg <= W_estatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_bstatus_reg <= 0;
else
W_bstatus_reg <= W_bstatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ienable_reg <= 0;
else
W_ienable_reg <= W_ienable_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ipending_reg <= 0;
else
W_ipending_reg <= W_ipending_reg_nxt;
end
assign W_cpuid_reg = 0;
assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result :
R_ctrl_rdctl_inst ? W_control_rd_data :
W_alu_result[31 : 0];
assign W_wr_data = W_wr_data_non_zero;
assign W_br_taken = R_ctrl_br & W_cmp_result;
assign W_mem_baddr = W_alu_result[28 : 0];
assign W_status_reg = W_status_reg_pie;
assign E_wrctl_status = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd0);
assign E_wrctl_estatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd1);
assign E_wrctl_bstatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd2);
assign E_wrctl_ienable = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd3);
assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 :
(D_op_eret) ? W_estatus_reg :
(D_op_bret) ? W_bstatus_reg :
(E_wrctl_status) ? E_src1[0] :
W_status_reg_pie;
assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie;
assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 :
(R_ctrl_exception) ? W_status_reg :
(E_wrctl_estatus) ? E_src1[0] :
W_estatus_reg;
assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg;
assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg :
(E_wrctl_bstatus) ? E_src1[0] :
W_bstatus_reg;
assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg;
assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ?
E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000000001;
assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000000001;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_enabled <= 1'b1;
else if (E_valid)
hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_write <= 0;
else
d_write <= d_write_nxt;
end
limbus_nios2_qsys_0_nios2_oci the_limbus_nios2_qsys_0_nios2_oci
(
.D_valid (D_valid),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pc (F_pc),
.address_nxt (jtag_debug_module_address),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.byteenable_nxt (jtag_debug_module_byteenable),
.clk (jtag_debug_module_clk),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.debugaccess_nxt (jtag_debug_module_debugaccess),
.hbreak_enabled (hbreak_enabled),
.jtag_debug_module_debugaccess_to_roms (jtag_debug_module_debugaccess_to_roms),
.oci_hbreak_req (oci_hbreak_req),
.oci_ienable (oci_ienable),
.oci_single_step_mode (oci_single_step_mode),
.read_nxt (jtag_debug_module_read),
.readdata (jtag_debug_module_readdata),
.reset (jtag_debug_module_reset),
.reset_n (reset_n),
.reset_req (reset_req),
.resetrequest (jtag_debug_module_resetrequest),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.waitrequest (jtag_debug_module_waitrequest),
.write_nxt (jtag_debug_module_write),
.writedata_nxt (jtag_debug_module_writedata)
);
//jtag_debug_module, which is an e_avalon_slave
assign jtag_debug_module_clk = clk;
assign jtag_debug_module_reset = ~reset_n;
assign D_ctrl_custom = 1'b0;
assign R_ctrl_custom_nxt = D_ctrl_custom;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom <= 0;
else if (R_en)
R_ctrl_custom <= R_ctrl_custom_nxt;
end
assign D_ctrl_custom_multi = 1'b0;
assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom_multi <= 0;
else if (R_en)
R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt;
end
assign D_ctrl_jmp_indirect = D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_indirect <= 0;
else if (R_en)
R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt;
end
assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi;
assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_direct <= 0;
else if (R_en)
R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt;
end
assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02;
assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_retaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt;
end
assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu;
assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_eretaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt;
end
assign D_ctrl_exception = D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60;
assign R_ctrl_exception_nxt = D_ctrl_exception;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_exception <= 0;
else if (R_en)
R_ctrl_exception <= R_ctrl_exception_nxt;
end
assign D_ctrl_break = D_op_break|D_op_hbreak;
assign R_ctrl_break_nxt = D_ctrl_break;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_break <= 0;
else if (R_en)
R_ctrl_break <= R_ctrl_break_nxt;
end
assign D_ctrl_crst = D_op_crst|D_op_rsvx63;
assign R_ctrl_crst_nxt = D_ctrl_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_crst <= 0;
else if (R_en)
R_ctrl_crst <= R_ctrl_crst_nxt;
end
assign D_ctrl_uncond_cti_non_br = D_op_call|
D_op_jmpi|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_uncond_cti_non_br <= 0;
else if (R_en)
R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt;
end
assign D_ctrl_retaddr = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak;
assign R_ctrl_retaddr_nxt = D_ctrl_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_retaddr <= 0;
else if (R_en)
R_ctrl_retaddr <= R_ctrl_retaddr_nxt;
end
assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl;
assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_logical <= 0;
else if (R_en)
R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt;
end
assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra;
assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_right_arith <= 0;
else if (R_en)
R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt;
end
assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43;
assign R_ctrl_rot_right_nxt = D_ctrl_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rot_right <= 0;
else if (R_en)
R_ctrl_rot_right <= R_ctrl_rot_right_nxt;
end
assign D_ctrl_shift_rot_right = D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot_right <= 0;
else if (R_en)
R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt;
end
assign D_ctrl_shift_rot = D_op_slli|
D_op_rsvx50|
D_op_sll|
D_op_rsvx51|
D_op_roli|
D_op_rsvx34|
D_op_rol|
D_op_rsvx35|
D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot <= 0;
else if (R_en)
R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt;
end
assign D_ctrl_logic = D_op_and|
D_op_or|
D_op_xor|
D_op_nor|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori;
assign R_ctrl_logic_nxt = D_ctrl_logic;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_logic <= 0;
else if (R_en)
R_ctrl_logic <= R_ctrl_logic_nxt;
end
assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi;
assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_hi_imm16 <= 0;
else if (R_en)
R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt;
end
assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui|
D_op_cmpltui|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_unsigned_lo_imm16 <= 0;
else if (R_en)
R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt;
end
assign D_ctrl_br_uncond = D_op_br|D_op_rsv02;
assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_uncond <= 0;
else if (R_en)
R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt;
end
assign D_ctrl_br = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62;
assign R_ctrl_br_nxt = D_ctrl_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br <= 0;
else if (R_en)
R_ctrl_br <= R_ctrl_br_nxt;
end
assign D_ctrl_alu_subtract = D_op_sub|
D_op_rsvx25|
D_op_cmplti|
D_op_cmpltui|
D_op_cmplt|
D_op_cmpltu|
D_op_blt|
D_op_bltu|
D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpge|
D_op_cmpgeu|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42;
assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_subtract <= 0;
else if (R_en)
R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt;
end
assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt;
assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_signed_comparison <= 0;
else if (R_en)
R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt;
end
assign D_ctrl_br_cmp = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_rsvx00|
D_op_cmpge|
D_op_cmplt|
D_op_cmpne|
D_op_cmpgeu|
D_op_cmpltu|
D_op_cmpeq|
D_op_rsvx56;
assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_cmp <= 0;
else if (R_en)
R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt;
end
assign D_ctrl_ld_signed = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63;
assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_signed <= 0;
else if (R_en)
R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt;
end
assign D_ctrl_ld = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio;
assign R_ctrl_ld_nxt = D_ctrl_ld;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld <= 0;
else if (R_en)
R_ctrl_ld <= R_ctrl_ld_nxt;
end
assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl;
assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_non_io <= 0;
else if (R_en)
R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt;
end
assign D_ctrl_st = D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61;
assign R_ctrl_st_nxt = D_ctrl_st;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_st <= 0;
else if (R_en)
R_ctrl_st <= R_ctrl_st_nxt;
end
assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63;
assign R_ctrl_ld_io_nxt = D_ctrl_ld_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_io <= 0;
else if (R_en)
R_ctrl_ld_io <= R_ctrl_ld_io_nxt;
end
assign D_ctrl_b_is_dst = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda;
assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_b_is_dst <= 0;
else if (R_en)
R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt;
end
assign D_ctrl_ignore_dst = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57;
assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ignore_dst <= 0;
else if (R_en)
R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt;
end
assign D_ctrl_src2_choose_imm = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_src2_choose_imm <= 0;
else if (R_en)
R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt;
end
assign D_ctrl_wrctl_inst = D_op_wrctl;
assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_wrctl_inst <= 0;
else if (R_en)
R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt;
end
assign D_ctrl_rdctl_inst = D_op_rdctl;
assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rdctl_inst <= 0;
else if (R_en)
R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt;
end
assign D_ctrl_force_src2_zero = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_jmpi;
assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_force_src2_zero <= 0;
else if (R_en)
R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt;
end
assign D_ctrl_alu_force_xor = D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpeqi|
D_op_cmpge|
D_op_cmpgeu|
D_op_cmpeq|
D_op_cmpnei|
D_op_cmpne|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42|
D_op_beq|
D_op_rsv34|
D_op_bne|
D_op_rsv62|
D_op_br|
D_op_rsv02;
assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_force_xor <= 0;
else if (R_en)
R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt;
end
//data_master, which is an e_avalon_master
//instruction_master, which is an e_avalon_master
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign F_inst = (F_op_call)? 56'h20202063616c6c :
(F_op_jmpi)? 56'h2020206a6d7069 :
(F_op_ldbu)? 56'h2020206c646275 :
(F_op_addi)? 56'h20202061646469 :
(F_op_stb)? 56'h20202020737462 :
(F_op_br)? 56'h20202020206272 :
(F_op_ldb)? 56'h202020206c6462 :
(F_op_cmpgei)? 56'h20636d70676569 :
(F_op_ldhu)? 56'h2020206c646875 :
(F_op_andi)? 56'h202020616e6469 :
(F_op_sth)? 56'h20202020737468 :
(F_op_bge)? 56'h20202020626765 :
(F_op_ldh)? 56'h202020206c6468 :
(F_op_cmplti)? 56'h20636d706c7469 :
(F_op_initda)? 56'h20696e69746461 :
(F_op_ori)? 56'h202020206f7269 :
(F_op_stw)? 56'h20202020737477 :
(F_op_blt)? 56'h20202020626c74 :
(F_op_ldw)? 56'h202020206c6477 :
(F_op_cmpnei)? 56'h20636d706e6569 :
(F_op_flushda)? 56'h666c7573686461 :
(F_op_xori)? 56'h202020786f7269 :
(F_op_bne)? 56'h20202020626e65 :
(F_op_cmpeqi)? 56'h20636d70657169 :
(F_op_ldbuio)? 56'h206c646275696f :
(F_op_muli)? 56'h2020206d756c69 :
(F_op_stbio)? 56'h2020737462696f :
(F_op_beq)? 56'h20202020626571 :
(F_op_ldbio)? 56'h20206c6462696f :
(F_op_cmpgeui)? 56'h636d7067657569 :
(F_op_ldhuio)? 56'h206c646875696f :
(F_op_andhi)? 56'h2020616e646869 :
(F_op_sthio)? 56'h2020737468696f :
(F_op_bgeu)? 56'h20202062676575 :
(F_op_ldhio)? 56'h20206c6468696f :
(F_op_cmpltui)? 56'h636d706c747569 :
(F_op_initd)? 56'h2020696e697464 :
(F_op_orhi)? 56'h2020206f726869 :
(F_op_stwio)? 56'h2020737477696f :
(F_op_bltu)? 56'h202020626c7475 :
(F_op_ldwio)? 56'h20206c6477696f :
(F_op_flushd)? 56'h20666c75736864 :
(F_op_xorhi)? 56'h2020786f726869 :
(F_op_eret)? 56'h20202065726574 :
(F_op_roli)? 56'h202020726f6c69 :
(F_op_rol)? 56'h20202020726f6c :
(F_op_flushp)? 56'h20666c75736870 :
(F_op_ret)? 56'h20202020726574 :
(F_op_nor)? 56'h202020206e6f72 :
(F_op_mulxuu)? 56'h206d756c787575 :
(F_op_cmpge)? 56'h2020636d706765 :
(F_op_bret)? 56'h20202062726574 :
(F_op_ror)? 56'h20202020726f72 :
(F_op_flushi)? 56'h20666c75736869 :
(F_op_jmp)? 56'h202020206a6d70 :
(F_op_and)? 56'h20202020616e64 :
(F_op_cmplt)? 56'h2020636d706c74 :
(F_op_slli)? 56'h202020736c6c69 :
(F_op_sll)? 56'h20202020736c6c :
(F_op_or)? 56'h20202020206f72 :
(F_op_mulxsu)? 56'h206d756c787375 :
(F_op_cmpne)? 56'h2020636d706e65 :
(F_op_srli)? 56'h20202073726c69 :
(F_op_srl)? 56'h2020202073726c :
(F_op_nextpc)? 56'h206e6578747063 :
(F_op_callr)? 56'h202063616c6c72 :
(F_op_xor)? 56'h20202020786f72 :
(F_op_mulxss)? 56'h206d756c787373 :
(F_op_cmpeq)? 56'h2020636d706571 :
(F_op_divu)? 56'h20202064697675 :
(F_op_div)? 56'h20202020646976 :
(F_op_rdctl)? 56'h2020726463746c :
(F_op_mul)? 56'h202020206d756c :
(F_op_cmpgeu)? 56'h20636d70676575 :
(F_op_initi)? 56'h2020696e697469 :
(F_op_trap)? 56'h20202074726170 :
(F_op_wrctl)? 56'h2020777263746c :
(F_op_cmpltu)? 56'h20636d706c7475 :
(F_op_add)? 56'h20202020616464 :
(F_op_break)? 56'h2020627265616b :
(F_op_hbreak)? 56'h2068627265616b :
(F_op_sync)? 56'h20202073796e63 :
(F_op_sub)? 56'h20202020737562 :
(F_op_srai)? 56'h20202073726169 :
(F_op_sra)? 56'h20202020737261 :
(F_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign D_inst = (D_op_call)? 56'h20202063616c6c :
(D_op_jmpi)? 56'h2020206a6d7069 :
(D_op_ldbu)? 56'h2020206c646275 :
(D_op_addi)? 56'h20202061646469 :
(D_op_stb)? 56'h20202020737462 :
(D_op_br)? 56'h20202020206272 :
(D_op_ldb)? 56'h202020206c6462 :
(D_op_cmpgei)? 56'h20636d70676569 :
(D_op_ldhu)? 56'h2020206c646875 :
(D_op_andi)? 56'h202020616e6469 :
(D_op_sth)? 56'h20202020737468 :
(D_op_bge)? 56'h20202020626765 :
(D_op_ldh)? 56'h202020206c6468 :
(D_op_cmplti)? 56'h20636d706c7469 :
(D_op_initda)? 56'h20696e69746461 :
(D_op_ori)? 56'h202020206f7269 :
(D_op_stw)? 56'h20202020737477 :
(D_op_blt)? 56'h20202020626c74 :
(D_op_ldw)? 56'h202020206c6477 :
(D_op_cmpnei)? 56'h20636d706e6569 :
(D_op_flushda)? 56'h666c7573686461 :
(D_op_xori)? 56'h202020786f7269 :
(D_op_bne)? 56'h20202020626e65 :
(D_op_cmpeqi)? 56'h20636d70657169 :
(D_op_ldbuio)? 56'h206c646275696f :
(D_op_muli)? 56'h2020206d756c69 :
(D_op_stbio)? 56'h2020737462696f :
(D_op_beq)? 56'h20202020626571 :
(D_op_ldbio)? 56'h20206c6462696f :
(D_op_cmpgeui)? 56'h636d7067657569 :
(D_op_ldhuio)? 56'h206c646875696f :
(D_op_andhi)? 56'h2020616e646869 :
(D_op_sthio)? 56'h2020737468696f :
(D_op_bgeu)? 56'h20202062676575 :
(D_op_ldhio)? 56'h20206c6468696f :
(D_op_cmpltui)? 56'h636d706c747569 :
(D_op_initd)? 56'h2020696e697464 :
(D_op_orhi)? 56'h2020206f726869 :
(D_op_stwio)? 56'h2020737477696f :
(D_op_bltu)? 56'h202020626c7475 :
(D_op_ldwio)? 56'h20206c6477696f :
(D_op_flushd)? 56'h20666c75736864 :
(D_op_xorhi)? 56'h2020786f726869 :
(D_op_eret)? 56'h20202065726574 :
(D_op_roli)? 56'h202020726f6c69 :
(D_op_rol)? 56'h20202020726f6c :
(D_op_flushp)? 56'h20666c75736870 :
(D_op_ret)? 56'h20202020726574 :
(D_op_nor)? 56'h202020206e6f72 :
(D_op_mulxuu)? 56'h206d756c787575 :
(D_op_cmpge)? 56'h2020636d706765 :
(D_op_bret)? 56'h20202062726574 :
(D_op_ror)? 56'h20202020726f72 :
(D_op_flushi)? 56'h20666c75736869 :
(D_op_jmp)? 56'h202020206a6d70 :
(D_op_and)? 56'h20202020616e64 :
(D_op_cmplt)? 56'h2020636d706c74 :
(D_op_slli)? 56'h202020736c6c69 :
(D_op_sll)? 56'h20202020736c6c :
(D_op_or)? 56'h20202020206f72 :
(D_op_mulxsu)? 56'h206d756c787375 :
(D_op_cmpne)? 56'h2020636d706e65 :
(D_op_srli)? 56'h20202073726c69 :
(D_op_srl)? 56'h2020202073726c :
(D_op_nextpc)? 56'h206e6578747063 :
(D_op_callr)? 56'h202063616c6c72 :
(D_op_xor)? 56'h20202020786f72 :
(D_op_mulxss)? 56'h206d756c787373 :
(D_op_cmpeq)? 56'h2020636d706571 :
(D_op_divu)? 56'h20202064697675 :
(D_op_div)? 56'h20202020646976 :
(D_op_rdctl)? 56'h2020726463746c :
(D_op_mul)? 56'h202020206d756c :
(D_op_cmpgeu)? 56'h20636d70676575 :
(D_op_initi)? 56'h2020696e697469 :
(D_op_trap)? 56'h20202074726170 :
(D_op_wrctl)? 56'h2020777263746c :
(D_op_cmpltu)? 56'h20636d706c7475 :
(D_op_add)? 56'h20202020616464 :
(D_op_break)? 56'h2020627265616b :
(D_op_hbreak)? 56'h2068627265616b :
(D_op_sync)? 56'h20202073796e63 :
(D_op_sub)? 56'h20202020737562 :
(D_op_srai)? 56'h20202073726169 :
(D_op_sra)? 56'h20202020737261 :
(D_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign F_vinst = F_valid ? F_inst : {7{8'h2d}};
assign D_vinst = D_valid ? D_inst : {7{8'h2d}};
assign R_vinst = R_valid ? D_inst : {7{8'h2d}};
assign E_vinst = E_valid ? D_inst : {7{8'h2d}};
assign W_vinst = W_valid ? D_inst : {7{8'h2d}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3_M_V
`define SKY130_FD_SC_LP__NAND3_M_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3_m (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3_m (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3_M_V
|
/****************************************************************************************
*
* File Name: ddr3.v
* Version: 1.60
* Model: BUS Functional
*
* Dependencies: ddr3_model_parameters.vh
*
* Description: Micron SDRAM DDR3 (Double Data Rate 3)
*
* Limitation: - doesn't check for average refresh timings
* - positive ck and ck_n edges are used to form internal clock
* - positive dqs and dqs_n edges are used to latch data
* - test mode is not modeled
* - Duty Cycle Corrector is not modeled
* - Temperature Compensated Self Refresh is not modeled
* - DLL off mode is not modeled.
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set DEBUG = 0 to disable $display messages
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
* Rev Author Date Changes
* ---------------------------------------------------------------------------------------
* 0.41 JMK 05/12/06 Removed auto-precharge to power down error check.
* 0.42 JMK 08/25/06 Created internal clock using ck and ck_n.
* TDQS can only be enabled in EMR for x8 configurations.
* CAS latency is checked vs frequency when DLL locks.
* Improved checking of DQS during writes.
* Added true BL4 operation.
* 0.43 JMK 08/14/06 Added checking for setting reserved bits in Mode Registers.
* Added ODTS Readout.
* Replaced tZQCL with tZQinit and tZQoper
* Fixed tWRPDEN and tWRAPDEN during BC4MRS and BL4MRS.
* Added tRFC checking for Refresh to Power-Down Re-Entry.
* Added tXPDLL checking for Power-Down Exit to Refresh to Power-Down Entry
* Added Clock Frequency Change during Precharge Power-Down.
* Added -125x speed grades.
* Fixed tRCD checking during Write.
* 1.00 JMK 05/11/07 Initial release
* 1.10 JMK 06/26/07 Fixed ODTH8 check during BLOTF
* Removed temp sensor readout from MPR
* Updated initialization sequence
* Updated timing parameters
* 1.20 JMK 09/05/07 Updated clock frequency change
* Added ddr3_dimm module
* 1.30 JMK 01/23/08 Updated timing parameters
* 1.40 JMK 12/02/08 Added support for DDR3-1866 and DDR3-2133
* renamed ddr3_dimm.v to ddr3_module.v and added SODIMM support.
* Added multi-chip package model support in ddr3_mcp.v
* 1.50 JMK 05/04/08 Added 1866 and 2133 speed grades.
* 1.60 MYY 07/10/09 Merging of 1.50 version and pre-1.0 version changes
*****************************************************************************************/
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
`timescale 1ps / 1ps
// model flags
// `define MODEL_PASR
module ddr3 (
rst_n,
ck,
ck_n,
cke,
cs_n,
ras_n,
cas_n,
we_n,
dm_tdqs,
ba,
addr,
dq,
dqs,
dqs_n,
tdqs_n,
odt
);
`define x1Gb
`define sg187E
`define x16
/* `include "ddr3_model_parameters.vh" */
/****************************************************************************************
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
****************************************************************************************/
// Parameters current with 1Gb and 2Gb datasheet rev D
// Timing parameters based on Speed Grade
// SYMBOL UNITS DESCRIPTION
// ------ ----- -----------
`ifdef x1Gb // 1Gb parameters
`ifdef sg094E // sg094E is equivalent to the JEDEC DDR3-2133 (13-13-13) speed bin
parameter TCK_MIN = 937.5; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 50; // tJIT(per) ps Period JItter
parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 73; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 85; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 98; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 117; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 275; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 455; // tIPW ps Control and Address input Pulse Width
parameter TIS = 35; // tIS ps Input Setup Time
parameter TIH = 75; // tIH ps Input Hold Time
parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 12187; // tRCD ps Active to Read/Write command time
parameter TRP = 12187; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 122; // tWLS ps Setup time for tDQS flop
parameter TWLH = 122; // tWLH ps Hold time of tDQS flop
parameter TWLO = 7500; // tWLO ps Write levelization output delay
parameter TAA_MIN = 12187; // TAA ps Internal READ command to first data
parameter CL_TIME = 12187; // CL ps Minimum CAS Latency
`else `ifdef sg094 // sg094 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin
parameter TCK_MIN = 937.5; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 50; // tJIT(per) ps Period JItter
parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 73; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 85; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 98; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 117; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 275; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 455; // tIPW ps Control and Address input Pulse Width
parameter TIS = 35; // tIS ps Input Setup Time
parameter TIH = 75; // tIH ps Input Hold Time
parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 13125; // tRCD ps Active to Read/Write command time
parameter TRP = 13125; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 122; // tWLS ps Setup time for tDQS flop
parameter TWLH = 122; // tWLH ps Hold time of tDQS flop
parameter TWLO = 7500; // tWLO ps Write levelization output delay
parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data
parameter CL_TIME = 13125; // CL ps Minimum CAS Latency
`else `ifdef sg107F // sg107F is equivalent to the JEDEC DDR3-1866 (12-12-12) speed bin
parameter TCK_MIN = 15e3/14; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 60; // tJIT(per) ps Period JItter
parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 103; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 140; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 300; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 505; // tIPW ps Control and Address input Pulse Width
parameter TIS = 50; // tIS ps Input Setup Time
parameter TIH = 100; // tIH ps Input Hold Time
parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 12857; // tRCD ps Active to Read/Write command time
parameter TRP = 12857; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 140; // tWLS ps Setup time for tDQS flop
parameter TWLH = 140; // tWLH ps Hold time of tDQS flop
parameter TWLO = 7500; // tWLO ps Write levelization output delay
parameter TAA_MIN = 12857; // TAA ps Internal READ command to first data
parameter CL_TIME = 12857; // CL ps Minimum CAS Latency
`else `ifdef sg107E // sg107E is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin
parameter TCK_MIN = 15e3/14; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 60; // tJIT(per) ps Period JItter
parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 103; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 140; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 300; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 505; // tIPW ps Control and Address input Pulse Width
parameter TIS = 50; // tIS ps Input Setup Time
parameter TIH = 100; // tIH ps Input Hold Time
parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 13928; // tRCD ps Active to Read/Write command time
parameter TRP = 13928; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 140; // tWLS ps Setup time for tDQS flop
parameter TWLH = 140; // tWLH ps Hold time of tDQS flop
parameter TWLO = 7500; // tWLO ps Write levelization output delay
parameter TAA_MIN = 13928; // TAA ps Internal READ command to first data
parameter CL_TIME = 13928; // CL ps Minimum CAS Latency
`else `ifdef sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (14-14-14) speed bin
parameter TCK_MIN = 15e3/14; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 60; // tJIT(per) ps Period JItter
parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 103; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 140; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 300; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 505; // tIPW ps Control and Address input Pulse Width
parameter TIS = 50; // tIS ps Input Setup Time
parameter TIH = 100; // tIH ps Input Hold Time
parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
parameter TRP = 15000; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 140; // tWLS ps Setup time for tDQS flop
parameter TWLH = 140; // tWLH ps Hold time of tDQS flop
parameter TWLO = 7500; // tWLO ps Write levelization output delay
parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
`else `ifdef sg125F // sg125F is equivalent to the JEDEC DDR3-1600 (9-9-9) speed bin
parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 70; // tJIT(per) ps Period JItter
parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width
parameter TIS = 170; // tIS ps Input Setup Time
parameter TIH = 120; // tIH ps Input Hold Time
parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 11250; // tRCD ps Active to Read/Write command time
parameter TRP = 11250; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 165; // tWLS ps Setup time for tDQS flop
parameter TWLH = 165; // tWLH ps Hold time of tDQS flop
parameter TWLO = 7500; // tWLO ps Write levelization output delay
parameter TAA_MIN = 11250; // TAA ps Internal READ command to first data
parameter CL_TIME = 11250; // CL ps Minimum CAS Latency
`else `ifdef sg125E // sg125E is equivalent to the JEDEC DDR3-1600 (10-10-10) speed bin
parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 70; // tJIT(per) ps Period JItter
parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width
parameter TIS = 170; // tIS ps Input Setup Time
parameter TIH = 120; // tIH ps Input Hold Time
parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 47500; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 12500; // tRCD ps Active to Read/Write command time
parameter TRP = 12500; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 165; // tWLS ps Setup time for tDQS flop
parameter TWLH = 165; // tWLH ps Hold time of tDQS flop
parameter TWLO = 7500; // tWLO ps Write levelization output delay
parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
`else `ifdef sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin
parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 70; // tJIT(per) ps Period JItter
parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width
parameter TIS = 170; // tIS ps Input Setup Time
parameter TIH = 120; // tIH ps Input Hold Time
parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 48750; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 13125; // tRCD ps Active to Read/Write command time
parameter TRP = 13125; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 165; // tWLS ps Setup time for tDQS flop
parameter TWLH = 165; // tWLH ps Hold time of tDQS flop
parameter TWLO = 7500; // tWLO ps Write levelization output delay
parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data
parameter CL_TIME = 13125; // CL ps Minimum CAS Latency
`else `ifdef sg15E // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin
parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 80; // tJIT(per) ps Period JItter
parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width
parameter TIS = 190; // tIS ps Input Setup Time
parameter TIH = 140; // tIH ps Input Hold Time
parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 49500; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 13125; // tRCD ps Active to Read/Write command time
parameter TRP = 13125; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 195; // tWLS ps Setup time for tDQS flop
parameter TWLH = 195; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data
parameter CL_TIME = 13125; // CL ps Minimum CAS Latency
`else `ifdef sg15 // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin
parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 80; // tJIT(per) ps Period JItter
parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width
parameter TIS = 190; // tIS ps Input Setup Time
parameter TIH = 140; // tIH ps Input Hold Time
parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
parameter TRP = 15000; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 195; // tWLS ps Setup time for tDQS flop
parameter TWLH = 195; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
`else `ifdef sg187E // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin
parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 90; // tJIT(per) ps Period JItter
parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width
parameter TIS = 275; // tIS ps Input Setup Time
parameter TIH = 200; // tIH ps Input Hold Time
parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 13125; // tRCD ps Active to Read/Write command time
parameter TRP = 13125; // tRP ps Precharge command period
parameter TXP = 7500; // tXP ps Exit power down to a valid command
parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 245; // tWLS ps Setup time for tDQS flop
parameter TWLH = 245; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data
parameter CL_TIME = 13125; // CL ps Minimum CAS Latency
`else `ifdef sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin
parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 90; // tJIT(per) ps Period JItter
parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width
parameter TIS = 275; // tIS ps Input Setup Time
parameter TIH = 200; // tIH ps Input Hold Time
parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
parameter TRP = 15000; // tRP ps Precharge command period
parameter TXP = 7500; // tXP ps Exit power down to a valid command
parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 245; // tWLS ps Setup time for tDQS flop
parameter TWLH = 245; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
`else `ifdef sg25E // sg25E is equivalent to the JEDEC DDR3-800D (5-5-5) speed bin
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width
parameter TIS = 350; // tIS ps Input Setup Time
parameter TIH = 275; // tIH ps Input Hold Time
parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 12500; // tRCD ps Active to Read/Write command time
parameter TRP = 12500; // tRP ps Precharge command period
parameter TXP = 7500; // tXP ps Exit power down to a valid command
parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 325; // tWLS ps Setup time for tDQS flop
parameter TWLH = 325; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
`else
`define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width
parameter TIS = 350; // tIS ps Input Setup Time
parameter TIH = 275; // tIH ps Input Hold Time
parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
parameter TRP = 15000; // tRP ps Precharge command period
parameter TXP = 7500; // tXP ps Exit power down to a valid command
parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 325; // tWLS ps Setup time for tDQS flop
parameter TWLH = 325; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
`endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif
`ifdef x16
`ifdef sg094E
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 30000; // tFAW ps (2KB page size) Four Bank Activate window
`else `ifdef sg094
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 30000; // tFAW ps (2KB page size) Four Bank Activate window
`else `ifdef sg107F
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window
`else `ifdef sg107E
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window
`else `ifdef sg107
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window
`else `ifdef sg125F
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window
`else `ifdef sg125E
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window
`else `ifdef sg125
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window
`else `ifdef sg15E
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window
`else `ifdef sg15
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window
`else // sg187E, sg187, sg25, sg25E
parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window
`endif `endif `endif `endif `endif `endif `endif `endif `endif `endif
`else // x4, x8
`ifdef sg094E
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg094
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg107F
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg107E
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg107
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg125F
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg125E
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg125
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg15E
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg15
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg187E
parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg187
parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window
`else // sg25, sg25E
parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window
`endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif
`endif
// Timing Parameters
// Mode Register
parameter CL_MIN = 5; // CL tCK Minimum CAS Latency
parameter CL_MAX = 14; // CL tCK Maximum CAS Latency
parameter AL_MIN = 0; // AL tCK Minimum Additive Latency
parameter AL_MAX = 2; // AL tCK Maximum Additive Latency
parameter WR_MIN = 5; // WR tCK Minimum Write Recovery
parameter WR_MAX = 16; // WR tCK Maximum Write Recovery
parameter BL_MIN = 4; // BL tCK Minimum Burst Length
parameter BL_MAX = 8; // BL tCK Minimum Burst Length
parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency
parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency
// Clock
parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time
parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width
parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width
parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width
parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width
parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width
parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width
parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width
parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data
// Data OUT
parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS#
// Data Strobe OUT
parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble
parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble
// Data Strobe IN
parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width
parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width
parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble
parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble
// Command and Address
parameter TZQCS = 64; // tZQCS tCK ZQ Cal (Short) time
parameter TZQINIT = 512; // tZQinit tCK ZQ Cal (Long) time
parameter TZQOPER = 256; // tZQoper tCK ZQ Cal (Long) time
parameter TCCD = 4; // tCCD tCK Cas to Cas command delay
parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group
parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time
parameter TWR = 15000; // tWR ps Write recovery time
parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time
parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time
parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time
parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time
parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group
parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group
parameter TRTP = 7500; // tRTP ps Read to Precharge command delay
parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay
parameter TWTR = 7500; // tWTR ps Write to Read command delay
parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group
parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay
parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group
parameter TDLLK = 512; // tDLLK tCK DLL locking time
// Refresh - 1Gb
parameter TRFC_MIN = 110000; // tRFC ps Refresh to Refresh Command interval minimum value
parameter TRFC_MAX =70312500; // tRFC ps Refresh to Refresh Command Interval maximum value
// Power Down
parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command
parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode)
parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode)
parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry
parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry
parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry
parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay
parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing
parameter TXPR = 120000; // tXPR ps Exit Reset from CKE assertion to a valid command
parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command
// Self Refresh
parameter TXS = 120000; // tXS ps Exit self refesh to a non-read or write command
parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command
parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command
parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit.
parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE)
parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE)
parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX)
parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX)
parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing
// ODT
parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference
parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen)
parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen)
parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4)
parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8)
parameter TADC = 0.7; // tADC tCK RTT dynamic change skew
// Write Levelization
parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed
parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed
parameter TWLOE = 2000; // tWLOE ps Write levelization output error
// Size Parameters based on Part Width
`ifdef x4
parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used
parameter ADDR_BITS = 14; // MAX Address Bits
parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used
parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used
parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width**
parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used
`else `ifdef x8
parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used
parameter ADDR_BITS = 14; // MAX Address Bits
parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width**
parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used
`else
`define x16
parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used
parameter ADDR_BITS = 13; // MAX Address Bits
parameter ROW_BITS = 13; // Set this parameter to control how many Address bits are used
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width**
parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used
`endif `endif
// Size Parameters
parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used
parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024.
parameter AP = 10; // the address bit that controls auto-precharge and precharge-all
parameter BC = 12; // the address bit that controls burst chop
parameter BL_BITS = 3; // the number of bits required to count to BL_MAX
parameter BO_BITS = 2; // the number of Burst Order Bits
`ifdef QUAD_RANK
`define DUAL_RANK // also define DUAL_RANK
parameter CS_BITS = 4; // Number of Chip Select Bits
parameter RANKS = 4; // Number of Chip Selects
`else `ifdef DUAL_RANK
parameter CS_BITS = 2; // Number of Chip Select Bits
parameter RANKS = 2; // Number of Chip Selects
`else
parameter CS_BITS = 2; // Number of Chip Select Bits
parameter RANKS = 1; // Number of Chip Selects
`endif `endif
// Simulation parameters
parameter RZQ = 240; // termination resistance
parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout
parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors
parameter DEBUG = 0; // Turn on Debug messages
parameter BUS_DELAY = 0; // delay in nanoseconds
parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
parameter RANDOM_SEED = 711689044; //seed value for random generator.
parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe
parameter RDQSEN_PST = 1; // DQS driving time after last read strobe
parameter RDQS_PRE = 2; // DQS low time prior to first read strobe
parameter RDQS_PST = 1; // DQS low time after last read strobe
parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data
parameter RDQEN_PST = 0; // DQ/DM driving time after last read data
parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe
parameter WDQS_PST = 1; // DQS half clock periods after last write strobe
// check for legal cas latency based on the cas write latency
function valid_cl;
input [3:0] cl;
input [3:0] cwl;
case ({cwl, cl})
`ifdef sg094E
{4'd5, 4'd5 },
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10},
{4'd8, 4'd10},
{4'd8, 4'd11},
{4'd8, 4'd12},
{4'd9, 4'd12},
{4'd9, 4'd13},
{4'd9, 4'd14},
{4'd10, 4'd13},
{4'd10, 4'd14}: valid_cl = 1;
`else `ifdef sg094
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd10},
{4'd8, 4'd11},
{4'd8, 4'd12},
{4'd9, 4'd13},
{4'd9, 4'd14},
{4'd10, 4'd14}: valid_cl = 1;
`else `ifdef sg107F
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10},
{4'd8, 4'd11},
{4'd8, 4'd12},
{4'd9, 4'd12},
{4'd9, 4'd13},
{4'd9, 4'd14}: valid_cl = 1;
`else `ifdef sg107E
{4'd5, 4'd6 },
{4'd6, 4'd8 },
{4'd7, 4'd10},
{4'd8, 4'd12},
{4'd9, 4'd13},
{4'd9, 4'd14}: valid_cl = 1;
`else `ifdef sg107
{4'd5, 4'd6 },
{4'd6, 4'd8 },
{4'd7, 4'd10},
{4'd8, 4'd12},
{4'd9, 4'd14}: valid_cl = 1;
`else `ifdef sg125F
{4'd5, 4'd5 },
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10},
{4'd8, 4'd9 },
{4'd8, 4'd10},
{4'd8, 4'd11}: valid_cl = 1;
`else `ifdef sg125E
{4'd5, 4'd5 },
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10},
{4'd8, 4'd10},
{4'd8, 4'd11}: valid_cl = 1;
`else `ifdef sg125
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10},
{4'd8, 4'd11}: valid_cl = 1;
`else `ifdef sg15E
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10}: valid_cl = 1;
`else `ifdef sg15
{4'd5, 4'd6 },
{4'd6, 4'd8 },
{4'd7, 4'd10}: valid_cl = 1;
`else `ifdef sg187E
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 }: valid_cl = 1;
`else `ifdef sg187
{4'd5, 4'd6 },
{4'd6, 4'd8 }: valid_cl = 1;
`else `ifdef sg25E
{4'd5, 4'd5 },
{4'd5, 4'd6 }: valid_cl = 1;
`else `ifdef sg25
{4'd5, 4'd6 }: valid_cl = 1;
`endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif
default : valid_cl = 0;
endcase
endfunction
// find the minimum valid cas write latency
function [3:0] min_cwl;
input period;
real period;
min_cwl = (period >= 2500.0) ? 5:
(period >= 1875.0) ? 6:
(period >= 1500.0) ? 7:
(period >= 1250.0) ? 8:
(period >= 15e3/14) ? 9:
10; // (period >= 937.5)
endfunction
// find the minimum valid cas latency
function [3:0] min_cl;
input period;
real period;
reg [3:0] cwl;
reg [3:0] cl;
begin
cwl = min_cwl(period);
for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin
if (valid_cl(cl, cwl)) begin
min_cl = cl;
end
end
end
endfunction
`elsif x2Gb // 2Gb parts
// SYMBOL UNITS DESCRIPTION
// ------ ----- -----------
`ifdef sg15E // sg15E is equivelant to the JEDEC DDR3-1333H (9-9-9) speed bin
parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 80; // tJIT(per) ps Period JItter
parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width
parameter TIS = 190; // tIS ps Input Setup Time
parameter TIH = 140; // tIH ps Input Hold Time
parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 49500; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 13500; // tRCD ps Active to Read/Write command time
parameter TRP = 13500; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 195; // tWLS ps Setup time for tDQS flop
parameter TWLH = 195; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 13500; // TAA ps Internal READ command to first data
parameter CL_TIME = 13500; // CL ps Minimum CAS Latency
`else `ifdef sg15 // sg15 is equivelant to the JEDEC DDR3-1333J (10-10-10) speed bin
parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 80; // tJIT(per) ps Period JItter
parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width
parameter TIS = 190; // tIS ps Input Setup Time
parameter TIH = 140; // tIH ps Input Hold Time
parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
parameter TRP = 15000; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 195; // tWLS ps Setup time for tDQS flop
parameter TWLH = 195; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
`else `ifdef sg187E // sg187E is equivelant to the JEDEC DDR3-1066F (7-7-7) speed bin
parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 90; // tJIT(per) ps Period JItter
parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 25; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width
parameter TIS = 125; // tIS ps Input Setup Time
parameter TIH = 200; // tIH ps Input Hold Time
parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 13125; // tRCD ps Active to Read/Write command time
parameter TRP = 13125; // tRP ps Precharge command period
parameter TXP = 7500; // tXP ps Exit power down to a valid command
parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 245; // tWLS ps Setup time for tDQS flop
parameter TWLH = 245; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data
parameter CL_TIME = 13125; // CL ps Minimum CAS Latency
`else `ifdef sg187 // sg187 is equivelant to the JEDEC DDR3-1066G (8-8-8) speed bin
parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 90; // tJIT(per) ps Period JItter
parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 25; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width
parameter TIS = 125; // tIS ps Input Setup Time
parameter TIH = 200; // tIH ps Input Hold Time
parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
parameter TRP = 15000; // tRP ps Precharge command period
parameter TXP = 7500; // tXP ps Exit power down to a valid command
parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 245; // tWLS ps Setup time for tDQS flop
parameter TWLH = 245; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
`else `ifdef sg25E // sg25E is equivelant to the JEDEC DDR3-800D (5-5-5) speed bin
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width
parameter TIS = 200; // tIS ps Input Setup Time
parameter TIH = 275; // tIH ps Input Hold Time
parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 12500; // tRCD ps Active to Read/Write command time
parameter TRP = 12500; // tRP ps Precharge command period
parameter TXP = 7500; // tXP ps Exit power down to a valid command
parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 325; // tWLS ps Setup time for tDQS flop
parameter TWLH = 325; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
`else
`define sg25 // sg25 is equivelant to the JEDEC DDR3-800E (6-6-6) speed bin
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width
parameter TIS = 200; // tIS ps Input Setup Time
parameter TIH = 275; // tIH ps Input Hold Time
parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
parameter TRP = 15000; // tRP ps Precharge command period
parameter TXP = 7500; // tXP ps Exit power down to a valid command
parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 325; // tWLS ps Setup time for tDQS flop
parameter TWLH = 325; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
`endif `endif `endif `endif `endif
`ifdef x16
`ifdef sg15E
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window
`else `ifdef sg15
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window
`else // sg187E, sg187, sg25, sg25E
parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window
`endif `endif
`else // x4, x8
`ifdef sg15E
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg15
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg187E
parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg187
parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window
`else // sg25, sg25E
parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window
`endif `endif `endif `endif
`endif
// Timing Parameters
// Mode Register
parameter CL_MIN = 5; // CL tCK Minimum CAS Latency
parameter CL_MAX = 11; // CL tCK Maximum CAS Latency
parameter AL_MIN = 0; // AL tCK Minimum Additive Latency
parameter AL_MAX = 2; // AL tCK Maximum Additive Latency
parameter WR_MIN = 5; // WR tCK Minimum Write Recovery
parameter WR_MAX = 12; // WR tCK Maximum Write Recovery
parameter BL_MIN = 4; // BL tCK Minimum Burst Length
parameter BL_MAX = 8; // BL tCK Minimum Burst Length
parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency
parameter CWL_MAX = 8; // CWL tCK Maximum CAS Write Latency
// Clock
parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time
parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width
parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width
parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width
parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width
parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width
parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width
parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width
parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data
// Data OUT
parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS#
// Data Strobe OUT
parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble
parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble
// Data Strobe IN
parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width
parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width
parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble
parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble
// Command and Address
parameter TZQCS = 64; // tZQCS tCK ZQ Cal (Short) time
parameter TZQINIT = 512; // tZQinit tCK ZQ Cal (Long) time
parameter TZQOPER = 256; // tZQoper tCK ZQ Cal (Long) time
parameter TCCD = 4; // tCCD tCK Cas to Cas command delay
parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group
parameter TRAS_MAX =70312500; // tRAS ps Maximum Active to Precharge command time
parameter TWR = 15000; // tWR ps Write recovery time
parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time
parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time
parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time
parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time
parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group
parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group
parameter TRTP = 7500; // tRTP ps Read to Precharge command delay
parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay
parameter TWTR = 7500; // tWTR ps Write to Read command delay
parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group
parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay
parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group
parameter TDLLK = 512; // tDLLK tCK DLL locking time
// Refresh - 2Gb
parameter TRFC_MIN = 160000; // tRFC ps Refresh to Refresh Command interval minimum value
parameter TRFC_MAX =70312500; // tRFC ps Refresh to Refresh Command Interval maximum value
// Power Down
parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command
parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode)
parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode)
parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry
parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry
parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry
parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay
parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing
parameter TXPR = 170000; // tXPR ps Exit Reset from CKE assertion to a valid command
parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command
// Self Refresh
parameter TXS = 170000; // tXS ps Exit self refesh to a non-read or write command
parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command
parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command
parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit.
parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE)
parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE)
parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX)
parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX)
parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing
// ODT
parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference
parameter TAONPD = 9000; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen)
parameter TAOFPD = 9000; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen)
parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4)
parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8)
parameter TADC = 0.7; // tADC tCK RTT dynamic change skew
// Write Levelization
parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed
parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed
parameter TWLOE = 2000; // tWLOE ps Write levelization output error
// Size Parameters based on Part Width
`ifdef x4
parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used
parameter ADDR_BITS = 15; // MAX Address Bits
parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used
parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used
parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width**
parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used
`else `ifdef x8
parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used
parameter ADDR_BITS = 15; // MAX Address Bits
parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width**
parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used
`else
`define x16
parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used
parameter ADDR_BITS = 14; // MAX Address Bits
parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width**
parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used
`endif `endif
// Size Parameters
parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used
parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024.
parameter AP = 10; // the address bit that controls auto-precharge and precharge-all
parameter BC = 12; // the address bit that controls burst chop
parameter BL_BITS = 3; // the number of bits required to count to BL_MAX
parameter BO_BITS = 2; // the number of Burst Order Bits
`ifdef QUAD_RANK
`define DUAL_RANK // also define DUAL_RANK
parameter CS_BITS = 4; // Number of Chip Select Bits
parameter RANKS = 4; // Number of Chip Selects
`else `ifdef DUAL_RANK
parameter CS_BITS = 2; // Number of Chip Select Bits
parameter RANKS = 2; // Number of Chip Selects
`else
parameter CS_BITS = 2; // Number of Chip Select Bits
parameter RANKS = 1; // Number of Chip Selects
`endif `endif
// Simulation parameters
parameter RZQ = 240; // termination resistance
parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout
parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors
parameter DEBUG = 0; // Turn on Debug messages
parameter BUS_DELAY = 0; // delay in nanoseconds
parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
parameter RANDOM_SEED = 711689044; //seed value for random generator.
parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe
parameter RDQSEN_PST = 1; // DQS driving time after last read strobe
parameter RDQS_PRE = 2; // DQS low time prior to first read strobe
parameter RDQS_PST = 1; // DQS low time after last read strobe
parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data
parameter RDQEN_PST = 0; // DQ/DM driving time after last read data
parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe
parameter WDQS_PST = 1; // DQS half clock periods after last write strobe
// check for legal cas latency based on the cas write latency
function valid_cl;
input [3:0] cl;
input [3:0] cwl;
case ({cwl, cl})
`ifdef sg15E
{4'd5, 4'd6 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10}: valid_cl = 1;
`else `ifdef sg15
{4'd5, 4'd6 },
{4'd6, 4'd8 },
{4'd7, 4'd10}: valid_cl = 1;
`else `ifdef sg187E
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 }: valid_cl = 1;
`else `ifdef sg187
{4'd5, 4'd6 },
{4'd6, 4'd8 }: valid_cl = 1;
`else `ifdef sg25E
{4'd5, 4'd5 },
{4'd5, 4'd6 }: valid_cl = 1;
`else `ifdef sg25
{4'd5, 4'd6 }: valid_cl = 1;
`endif `endif `endif `endif `endif `endif
default : valid_cl = 0;
endcase
endfunction
// find the minimum valid cas write latency
function [3:0] min_cwl;
input period;
real period;
min_cwl = (period >= 2500.0) ? 5:
(period >= 1875.0) ? 6:
(period >= 1500.0) ? 7:
8; //(period >= 1250.0)
endfunction
// find the minimum valid cas latency
function [3:0] min_cl;
input period;
real period;
reg [3:0] cwl;
reg [3:0] cl;
begin
cwl = min_cwl(period);
for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin
if (valid_cl(cl, cwl)) begin
min_cl = cl;
end
end
end
endfunction
`endif
parameter check_strict_mrbits = 1;
parameter check_strict_timing = 1;
parameter feature_pasr = 1;
parameter feature_truebl4 = 0;
// text macros
`define DQ_PER_DQS DQ_BITS/DQS_BITS
`define BANKS (1<<BA_BITS)
`define MAX_BITS (BA_BITS+ROW_BITS+COL_BITS-BL_BITS)
`define MAX_SIZE (1<<(BA_BITS+ROW_BITS+COL_BITS-BL_BITS))
`define MEM_SIZE (1<<MEM_BITS)
`define MAX_PIPE 4*CL_MAX
// Declare Ports
input rst_n;
input ck;
input ck_n;
input cke;
input cs_n;
input ras_n;
input cas_n;
input we_n;
inout [DM_BITS-1:0] dm_tdqs;
input [BA_BITS-1:0] ba;
input [ADDR_BITS-1:0] addr;
inout [DQ_BITS-1:0] dq;
inout [DQS_BITS-1:0] dqs;
inout [DQS_BITS-1:0] dqs_n;
output [DQS_BITS-1:0] tdqs_n;
input odt;
// clock jitter
real tck_avg;
time tck_sample [TDLLK-1:0];
time tch_sample [TDLLK-1:0];
time tcl_sample [TDLLK-1:0];
time tck_i;
time tch_i;
time tcl_i;
real tch_avg;
real tcl_avg;
time tm_ck_pos;
time tm_ck_neg;
real tjit_per_rtime;
integer tjit_cc_time;
real terr_nper_rtime;
//DDR3 clock jitter variables
real tjit_ch_rtime;
real duty_cycle;
// clock skew
real out_delay;
integer dqsck [DQS_BITS-1:0];
integer dqsck_min;
integer dqsck_max;
integer dqsq_min;
integer dqsq_max;
integer seed;
// Mode Registers
reg [ADDR_BITS-1:0] mode_reg [`BANKS-1:0];
reg burst_order;
reg [BL_BITS:0] burst_length;
reg blotf;
reg truebl4;
integer cas_latency;
reg dll_reset;
reg dll_locked;
integer write_recovery;
reg low_power;
reg dll_en;
reg [2:0] odt_rtt_nom;
reg [1:0] odt_rtt_wr;
reg odt_en;
reg dyn_odt_en;
reg [1:0] al;
integer additive_latency;
reg write_levelization;
reg duty_cycle_corrector;
reg tdqs_en;
reg out_en;
reg [2:0] pasr;
integer cas_write_latency;
reg asr; // auto self refresh
reg srt; // self refresh temperature range
reg [1:0] mpr_select;
reg mpr_en;
reg odts_readout;
integer read_latency;
integer write_latency;
// cmd encoding
parameter // {cs, ras, cas, we}
LOAD_MODE = 4'b0000,
REFRESH = 4'b0001,
PRECHARGE = 4'b0010,
ACTIVATE = 4'b0011,
WRITE = 4'b0100,
READ = 4'b0101,
ZQ = 4'b0110,
NOP = 4'b0111,
// DESEL = 4'b1xxx,
PWR_DOWN = 4'b1000,
SELF_REF = 4'b1001
;
reg [8*9-1:0] cmd_string [9:0];
initial begin
cmd_string[LOAD_MODE] = "Load Mode";
cmd_string[REFRESH ] = "Refresh ";
cmd_string[PRECHARGE] = "Precharge";
cmd_string[ACTIVATE ] = "Activate ";
cmd_string[WRITE ] = "Write ";
cmd_string[READ ] = "Read ";
cmd_string[ZQ ] = "ZQ ";
cmd_string[NOP ] = "No Op ";
cmd_string[PWR_DOWN ] = "Pwr Down ";
cmd_string[SELF_REF ] = "Self Ref ";
end
// command state
reg [`BANKS-1:0] active_bank;
reg [`BANKS-1:0] auto_precharge_bank;
reg [`BANKS-1:0] write_precharge_bank;
reg [`BANKS-1:0] read_precharge_bank;
reg [ROW_BITS-1:0] active_row [`BANKS-1:0];
reg in_power_down;
reg in_self_refresh;
reg [3:0] init_mode_reg;
reg init_dll_reset;
reg init_done;
integer init_step;
reg zq_set;
reg er_trfc_max;
reg odt_state;
reg odt_state_dly;
reg dyn_odt_state;
reg dyn_odt_state_dly;
reg prev_odt;
wire [7:0] calibration_pattern = 8'b10101010; // value returned during mpr pre-defined pattern readout
wire [7:0] temp_sensor = 8'h01; // value returned during mpr temp sensor readout
reg [1:0] mr_chk;
reg rd_bc;
integer banki;
// cmd timers/counters
integer ref_cntr;
integer odt_cntr;
integer ck_cntr;
integer ck_txpr;
integer ck_load_mode;
integer ck_refresh;
integer ck_precharge;
integer ck_activate;
integer ck_write;
integer ck_read;
integer ck_zqinit;
integer ck_zqoper;
integer ck_zqcs;
integer ck_power_down;
integer ck_slow_exit_pd;
integer ck_self_refresh;
integer ck_freq_change;
integer ck_odt;
integer ck_odth8;
integer ck_dll_reset;
integer ck_cke_cmd;
integer ck_bank_write [`BANKS-1:0];
integer ck_bank_read [`BANKS-1:0];
integer ck_group_activate [1:0];
integer ck_group_write [1:0];
integer ck_group_read [1:0];
time tm_txpr;
time tm_load_mode;
time tm_refresh;
time tm_precharge;
time tm_activate;
time tm_write_end;
time tm_power_down;
time tm_slow_exit_pd;
time tm_self_refresh;
time tm_freq_change;
time tm_cke_cmd;
time tm_ttsinit;
time tm_bank_precharge [`BANKS-1:0];
time tm_bank_activate [`BANKS-1:0];
time tm_bank_write_end [`BANKS-1:0];
time tm_bank_read_end [`BANKS-1:0];
time tm_group_activate [1:0];
time tm_group_write_end [1:0];
// pipelines
reg [`MAX_PIPE:0] al_pipeline;
reg [`MAX_PIPE:0] wr_pipeline;
reg [`MAX_PIPE:0] rd_pipeline;
reg [`MAX_PIPE:0] odt_pipeline;
reg [`MAX_PIPE:0] dyn_odt_pipeline;
reg [BL_BITS:0] bl_pipeline [`MAX_PIPE:0];
reg [BA_BITS-1:0] ba_pipeline [`MAX_PIPE:0];
reg [ROW_BITS-1:0] row_pipeline [`MAX_PIPE:0];
reg [COL_BITS-1:0] col_pipeline [`MAX_PIPE:0];
reg prev_cke;
// data state
reg [BL_MAX*DQ_BITS-1:0] memory_data;
reg [BL_MAX*DQ_BITS-1:0] bit_mask;
reg [BL_BITS-1:0] burst_position;
reg [BL_BITS:0] burst_cntr;
reg [DQ_BITS-1:0] dq_temp;
reg [31:0] check_write_postamble;
reg [31:0] check_write_preamble;
reg [31:0] check_write_dqs_high;
reg [31:0] check_write_dqs_low;
reg [15:0] check_dm_tdipw;
reg [63:0] check_dq_tdipw;
// data timers/counters
time tm_rst_n;
time tm_cke;
time tm_odt;
time tm_tdqss;
time tm_dm [15:0];
time tm_dqs [15:0];
time tm_dqs_pos [31:0];
time tm_dqss_pos [31:0];
time tm_dqs_neg [31:0];
time tm_dq [63:0];
time tm_cmd_addr [22:0];
reg [8*7-1:0] cmd_addr_string [22:0];
initial begin
cmd_addr_string[ 0] = "CS_N ";
cmd_addr_string[ 1] = "RAS_N ";
cmd_addr_string[ 2] = "CAS_N ";
cmd_addr_string[ 3] = "WE_N ";
cmd_addr_string[ 4] = "BA 0 ";
cmd_addr_string[ 5] = "BA 1 ";
cmd_addr_string[ 6] = "BA 2 ";
cmd_addr_string[ 7] = "ADDR 0";
cmd_addr_string[ 8] = "ADDR 1";
cmd_addr_string[ 9] = "ADDR 2";
cmd_addr_string[10] = "ADDR 3";
cmd_addr_string[11] = "ADDR 4";
cmd_addr_string[12] = "ADDR 5";
cmd_addr_string[13] = "ADDR 6";
cmd_addr_string[14] = "ADDR 7";
cmd_addr_string[15] = "ADDR 8";
cmd_addr_string[16] = "ADDR 9";
cmd_addr_string[17] = "ADDR 10";
cmd_addr_string[18] = "ADDR 11";
cmd_addr_string[19] = "ADDR 12";
cmd_addr_string[20] = "ADDR 13";
cmd_addr_string[21] = "ADDR 14";
cmd_addr_string[22] = "ADDR 15";
end
reg [8*5-1:0] dqs_string [1:0];
initial begin
dqs_string[0] = "DQS ";
dqs_string[1] = "DQS_N";
end
// Memory Storage
`ifdef MAX_MEM
parameter RFF_BITS = DQ_BITS*BL_MAX;
// %z format uses 8 bytes for every 32 bits or less.
parameter RFF_CHUNK = 8 * (RFF_BITS/32 + (RFF_BITS%32 ? 1 : 0));
reg [1024:1] tmp_model_dir;
integer memfd[`BANKS-1:0];
initial
begin : file_io_open
integer bank;
if (!$value$plusargs("model_data+%s", tmp_model_dir))
begin
tmp_model_dir = "/tmp";
$display(
"%m: at time %t WARNING: no +model_data option specified, using /tmp.",
$time
);
end
for (bank = 0; bank < `BANKS; bank = bank + 1)
memfd[bank] = open_bank_file(bank);
end
`else
reg [BL_MAX*DQ_BITS-1:0] memory [0:`MEM_SIZE-1];
reg [`MAX_BITS-1:0] address [0:`MEM_SIZE-1];
reg [MEM_BITS:0] memory_index;
reg [MEM_BITS:0] memory_used = 0;
`endif
// receive
reg rst_n_in;
reg ck_in;
reg ck_n_in;
reg cke_in;
reg cs_n_in;
reg ras_n_in;
reg cas_n_in;
reg we_n_in;
reg [15:0] dm_in;
reg [2:0] ba_in;
reg [15:0] addr_in;
reg [63:0] dq_in;
reg [31:0] dqs_in;
reg odt_in;
reg [15:0] dm_in_pos;
reg [15:0] dm_in_neg;
reg [63:0] dq_in_pos;
reg [63:0] dq_in_neg;
reg dq_in_valid;
reg dqs_in_valid;
integer wdqs_cntr;
integer wdq_cntr;
integer wdqs_pos_cntr [31:0];
reg b2b_write;
reg [BL_BITS:0] wr_burst_length;
reg [31:0] prev_dqs_in;
reg diff_ck;
always @(rst_n ) rst_n_in <= #BUS_DELAY rst_n;
always @(ck ) ck_in <= #BUS_DELAY ck;
always @(ck_n ) ck_n_in <= #BUS_DELAY ck_n;
always @(cke ) cke_in <= #BUS_DELAY cke;
always @(cs_n ) cs_n_in <= #BUS_DELAY cs_n;
always @(ras_n ) ras_n_in <= #BUS_DELAY ras_n;
always @(cas_n ) cas_n_in <= #BUS_DELAY cas_n;
always @(we_n ) we_n_in <= #BUS_DELAY we_n;
always @(dm_tdqs) dm_in <= #BUS_DELAY dm_tdqs;
always @(ba ) ba_in <= #BUS_DELAY ba;
always @(addr ) addr_in <= #BUS_DELAY addr;
always @(dq ) dq_in <= #BUS_DELAY dq;
always @(dqs or dqs_n) dqs_in <= #BUS_DELAY (dqs_n<<16) | dqs;
always @(odt ) odt_in <= #BUS_DELAY odt;
// create internal clock
always @(posedge ck_in) diff_ck <= ck_in;
always @(posedge ck_n_in) diff_ck <= ~ck_n_in;
wire [15:0] dqs_even = dqs_in[15:0];
wire [15:0] dqs_odd = dqs_in[31:16];
wire [3:0] cmd_n_in = !cs_n_in ? {ras_n_in, cas_n_in, we_n_in} : NOP; //deselect = nop
// transmit
reg dqs_out_en;
reg [DQS_BITS-1:0] dqs_out_en_dly;
reg dqs_out;
reg [DQS_BITS-1:0] dqs_out_dly;
reg dq_out_en;
reg [DQ_BITS-1:0] dq_out_en_dly;
reg [DQ_BITS-1:0] dq_out;
reg [DQ_BITS-1:0] dq_out_dly;
integer rdqsen_cntr;
integer rdqs_cntr;
integer rdqen_cntr;
integer rdq_cntr;
bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
bufif1 buf_dqs_n [DQS_BITS-1:0] (dqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
bufif1 buf_dq [DQ_BITS-1:0] (dq, dq_out_dly, dq_out_en_dly & {DQ_BITS {out_en}});
assign tdqs_n = {DQS_BITS{1'bz}};
initial begin
if (BL_MAX < 2)
$display("%m ERROR: BL_MAX parameter must be >= 2. \nBL_MAX = %d", BL_MAX);
if ((1<<BO_BITS) > BL_MAX)
$display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter.");
$timeformat (-12, 1, " ps", 1);
seed = RANDOM_SEED;
ck_cntr = 0;
end
function integer get_rtt_wr;
input [1:0] rtt;
begin
get_rtt_wr = RZQ/{rtt[0], rtt[1], 1'b0};
end
endfunction
function integer get_rtt_nom;
input [2:0] rtt;
begin
case (rtt)
1: get_rtt_nom = RZQ/4;
2: get_rtt_nom = RZQ/2;
3: get_rtt_nom = RZQ/6;
4: get_rtt_nom = RZQ/12;
5: get_rtt_nom = RZQ/8;
default : get_rtt_nom = 0;
endcase
end
endfunction
// calculate the absolute value of a real number
function real abs_value;
input arg;
real arg;
begin
if (arg < 0.0)
abs_value = -1.0 * arg;
else
abs_value = arg;
end
endfunction
function integer ceil;
input number;
real number;
// LMR 4.1.7
// When either operand of a relational expression is a real operand then the other operand shall be converted
// to an equivalent real value, and the expression shall be interpreted as a comparison between two real values.
if (number > $rtoi(number))
ceil = $rtoi(number) + 1;
else
ceil = number;
endfunction
function integer floor;
input number;
real number;
// LMR 4.1.7
// When either operand of a relational expression is a real operand then the other operand shall be converted
// to an equivalent real value, and the expression shall be interpreted as a comparison between two real values.
if (number < $rtoi(number))
floor = $rtoi(number) - 1;
else
floor = number;
endfunction
`ifdef MAX_MEM
function integer open_bank_file( input integer bank );
integer fd;
reg [2048:1] filename;
begin
$sformat( filename, "%0s/%m.%0d", tmp_model_dir, bank );
fd = $fopen(filename, "w+");
if (fd == 0)
begin
$display("%m: at time %0t ERROR: failed to open %0s.", $time, filename);
$finish;
end
else
begin
if (DEBUG) $display("%m: at time %0t INFO: opening %0s.", $time, filename);
open_bank_file = fd;
end
end
endfunction
function [RFF_BITS:1] read_from_file(
input integer fd,
input integer index
);
integer code;
integer offset;
reg [1024:1] msg;
reg [RFF_BITS:1] read_value;
begin
offset = index * RFF_CHUNK;
code = $fseek( fd, offset, 0 );
// $fseek returns 0 on success, -1 on failure
if (code != 0)
begin
$display("%m: at time %t ERROR: fseek to %d failed", $time, offset);
$finish;
end
code = $fscanf(fd, "%z", read_value);
// $fscanf returns number of items read
if (code != 1)
begin
if ($ferror(fd,msg) != 0)
begin
$display("%m: at time %t ERROR: fscanf failed at %d", $time, index);
$display(msg);
$finish;
end
else
read_value = 'hx;
end
/* when reading from unwritten portions of the file, 0 will be returned.
* Use 0 in bit 1 as indicator that invalid data has been read.
* A true 0 is encoded as Z.
*/
if (read_value[1] === 1'bz)
// true 0 encoded as Z, data is valid
read_value[1] = 1'b0;
else if (read_value[1] === 1'b0)
// read from file section that has not been written
read_value = 'hx;
read_from_file = read_value;
end
endfunction
task write_to_file(
input integer fd,
input integer index,
input [RFF_BITS:1] data
);
integer code;
integer offset;
begin
offset = index * RFF_CHUNK;
code = $fseek( fd, offset, 0 );
if (code != 0)
begin
$display("%m: at time %t ERROR: fseek to %d failed", $time, offset);
$finish;
end
// encode a valid data
if (data[1] === 1'bz)
data[1] = 1'bx;
else if (data[1] === 1'b0)
data[1] = 1'bz;
$fwrite( fd, "%z", data );
end
endtask
`else
function get_index;
input [`MAX_BITS-1:0] addr;
begin : index
get_index = 0;
for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
if (address[memory_index] == addr) begin
get_index = 1;
disable index;
end
end
end
endfunction
`endif
task memory_write;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
input [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
`ifdef MAX_MEM
addr = {row, col}/BL_MAX;
write_to_file( memfd[bank], addr, data );
`else
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
if (get_index(addr)) begin
address[memory_index] = addr;
memory[memory_index] = data;
end else if (memory_used == `MEM_SIZE) begin
$display ("%m: at time %t ERROR: Memory overflow. Write to Address %h with Data %h will be lost.\nYou must increase the MEM_BITS parameter or define MAX_MEM.", $time, addr, data);
if (STOP_ON_ERROR) $stop(0);
end else begin
address[memory_used] = addr;
memory[memory_used] = data;
memory_used = memory_used + 1;
end
`endif
end
endtask
task memory_read;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
output [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
`ifdef MAX_MEM
addr = {row, col}/BL_MAX;
data = read_from_file( memfd[bank], addr );
`else
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
if (get_index(addr)) begin
data = memory[memory_index];
end else begin
data = {BL_MAX*DQ_BITS{1'bx}};
end
`endif
end
endtask
task set_latency;
begin
if (al == 0) begin
additive_latency = 0;
end else begin
additive_latency = cas_latency - al;
end
read_latency = cas_latency + additive_latency;
write_latency = cas_write_latency + additive_latency;
end
endtask
// this task will erase the contents of 0 or more banks
task erase_banks;
input [`BANKS-1:0] banks; //one select bit per bank
reg [BA_BITS-1:0] ba;
reg [`MAX_BITS-1:0] i;
integer bank;
begin
`ifdef MAX_MEM
for (bank = 0; bank < `BANKS; bank = bank + 1)
if (banks[bank] === 1'b1) begin
$fclose(memfd[bank]);
memfd[bank] = open_bank_file(bank);
end
`else
memory_index = 0;
i = 0;
// remove the selected banks
for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
ba = (address[memory_index]>>(ROW_BITS+COL_BITS-BL_BITS));
if (!banks[ba]) begin //bank is selected to keep
address[i] = address[memory_index];
memory[i] = memory[memory_index];
i = i + 1;
end
end
// clean up the unused banks
for (memory_index=i; memory_index<memory_used; memory_index=memory_index+1) begin
address[memory_index] = 'bx;
memory[memory_index] = {8*DQ_BITS{1'bx}};
end
memory_used = i;
`endif
end
endtask
// Before this task runs, the model must be in a valid state for precharge power down and out of reset.
// After this task runs, NOP commands must be issued until TZQINIT has been met
task initialize;
input [ADDR_BITS-1:0] mode_reg0;
input [ADDR_BITS-1:0] mode_reg1;
input [ADDR_BITS-1:0] mode_reg2;
input [ADDR_BITS-1:0] mode_reg3;
begin
if (DEBUG) $display ("%m: at time %t INFO: Performing Initialization Sequence", $time);
cmd_task(1, NOP, 'bx, 'bx);
cmd_task(1, ZQ, 'bx, 'h400); //ZQCL
cmd_task(1, LOAD_MODE, 3, mode_reg3);
cmd_task(1, LOAD_MODE, 2, mode_reg2);
cmd_task(1, LOAD_MODE, 1, mode_reg1);
cmd_task(1, LOAD_MODE, 0, mode_reg0 | 'h100); // DLL Reset
cmd_task(0, NOP, 'bx, 'bx);
end
endtask
task reset_task;
integer i;
begin
// disable inputs
dq_in_valid = 0;
dqs_in_valid <= 0;
wdqs_cntr = 0;
wdq_cntr = 0;
for (i=0; i<31; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
b2b_write <= 0;
// disable outputs
out_en = 0;
dq_out_en = 0;
rdq_cntr = 0;
dqs_out_en = 0;
rdqs_cntr = 0;
// disable ODT
odt_en = 0;
dyn_odt_en = 0;
odt_state = 0;
dyn_odt_state = 0;
// reset bank state
active_bank = 0;
auto_precharge_bank = 0;
read_precharge_bank = 0;
write_precharge_bank = 0;
// require initialization sequence
init_done = 0;
mpr_en = 0;
init_step = 0;
init_mode_reg = 0;
init_dll_reset = 0;
zq_set = 0;
// reset DLL
dll_en = 0;
dll_reset = 0;
dll_locked = 0;
// exit power down and self refresh
prev_cke = 1'bx;
in_power_down = 0;
in_self_refresh = 0;
// clear pipelines
al_pipeline = 0;
wr_pipeline = 0;
rd_pipeline = 0;
odt_pipeline = 0;
dyn_odt_pipeline = 0;
end
endtask
parameter SAME_BANK = 2'd0; // same bank, same group
parameter DIFF_BANK = 2'd1; // different bank, same group
parameter DIFF_GROUP = 2'd2; // different bank, different group
task chk_err;
input [1:0] relationship;
input [BA_BITS-1:0] bank;
input [3:0] fromcmd;
input [3:0] cmd;
reg err;
begin
// $display ("truebl4 = %d, relationship = %d, fromcmd = %h, cmd = %h", truebl4, relationship, fromcmd, cmd);
casex ({truebl4, relationship, fromcmd, cmd})
// load mode
{1'bx, DIFF_BANK , LOAD_MODE, LOAD_MODE} : begin if (ck_cntr - ck_load_mode < TMRD) $display ("%m: at time %t ERROR: tMRD violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , LOAD_MODE, READ } : begin if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK)) $display ("%m: at time %t ERROR: tMOD violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , LOAD_MODE, REFRESH } ,
{1'bx, DIFF_BANK , LOAD_MODE, PRECHARGE} ,
{1'bx, DIFF_BANK , LOAD_MODE, ACTIVATE } ,
{1'bx, DIFF_BANK , LOAD_MODE, ZQ } ,
{1'bx, DIFF_BANK , LOAD_MODE, PWR_DOWN } ,
{1'bx, DIFF_BANK , LOAD_MODE, SELF_REF } : begin if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK)) $display ("%m: at time %t ERROR: tMOD violation during %s", $time, cmd_string[cmd]); end
// refresh
{1'bx, DIFF_BANK , REFRESH , LOAD_MODE} ,
{1'bx, DIFF_BANK , REFRESH , REFRESH } ,
{1'bx, DIFF_BANK , REFRESH , PRECHARGE} ,
{1'bx, DIFF_BANK , REFRESH , ACTIVATE } ,
{1'bx, DIFF_BANK , REFRESH , ZQ } ,
{1'bx, DIFF_BANK , REFRESH , SELF_REF } : begin if ($time - tm_refresh < TRFC_MIN) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , REFRESH , PWR_DOWN } : begin if (ck_cntr - ck_refresh < TREFPDEN) $display ("%m: at time %t ERROR: tREFPDEN violation during %s", $time, cmd_string[cmd]); end
// precharge
{1'bx, SAME_BANK , PRECHARGE, ACTIVATE } : begin if ($time - tm_bank_precharge[bank] < TRP) $display ("%m: at time %t ERROR: tRP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , PRECHARGE, LOAD_MODE} ,
{1'bx, DIFF_BANK , PRECHARGE, REFRESH } ,
{1'bx, DIFF_BANK , PRECHARGE, ZQ } ,
{1'bx, DIFF_BANK , PRECHARGE, SELF_REF } : begin if ($time - tm_precharge < TRP) $display ("%m: at time %t ERROR: tRP violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PRECHARGE, PWR_DOWN } : ; //tPREPDEN = 1 tCK, can be concurrent with auto precharge
// activate
{1'bx, SAME_BANK , ACTIVATE , PRECHARGE} : begin if ($time - tm_bank_activate[bank] > TRAS_MAX) $display ("%m: at time %t ERROR: tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank);
if ($time - tm_bank_activate[bank] < TRAS_MIN) $display ("%m: at time %t ERROR: tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end
{1'bx, SAME_BANK , ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC) $display ("%m: at time %t ERROR: tRC violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, SAME_BANK , ACTIVATE , WRITE } ,
{1'bx, SAME_BANK , ACTIVATE , READ } : ; // tRCD is checked outside this task
{1'b0, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD) || (ck_cntr - ck_activate < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_group_activate[bank[1]] < TRRD) || (ck_cntr - ck_group_activate[bank[1]] < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD_DG) || (ck_cntr - ck_activate < TRRD_DG_TCK)) $display ("%m: at time %t ERROR: tRRD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , ACTIVATE , REFRESH } : begin if ($time - tm_activate < TRC) $display ("%m: at time %t ERROR: tRC violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , ACTIVATE , PWR_DOWN } : begin if (ck_cntr - ck_activate < TACTPDEN) $display ("%m: at time %t ERROR: tACTPDEN violation during %s", $time, cmd_string[cmd]); end
// write
{1'bx, SAME_BANK , WRITE , PRECHARGE} : begin if (($time - tm_bank_write_end[bank] < TWR) || (ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_group_write[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_group_write[bank[1]] < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_DG_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , WRITE , PWR_DOWN } : begin if (($time - tm_write_end < TWR) || (ck_cntr - ck_write < write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWRPDEN violation during %s", $time, cmd_string[cmd]); end
// read
{1'bx, SAME_BANK , READ , PRECHARGE} : begin if (($time - tm_bank_read_end[bank] < TRTP) || (ck_cntr - ck_bank_read[bank] < additive_latency + TRTP_TCK)) $display ("%m: at time %t ERROR: tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task
{1'b1, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task
{1'b0, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_read < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_group_read[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, READ , WRITE } : ; // tRTW is checked outside this task
{1'b1, DIFF_GROUP, READ , READ } : begin if (ck_cntr - ck_read < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , READ , PWR_DOWN } : begin if (ck_cntr - ck_read < read_latency + 5) $display ("%m: at time %t ERROR: tRDPDEN violation during %s", $time, cmd_string[cmd]); end
// zq
{1'bx, DIFF_BANK , ZQ , LOAD_MODE} : ; // 1 tCK
{1'bx, DIFF_BANK , ZQ , REFRESH } ,
{1'bx, DIFF_BANK , ZQ , PRECHARGE} ,
{1'bx, DIFF_BANK , ZQ , ACTIVATE } ,
{1'bx, DIFF_BANK , ZQ , ZQ } ,
{1'bx, DIFF_BANK , ZQ , PWR_DOWN } ,
{1'bx, DIFF_BANK , ZQ , SELF_REF } : begin if (ck_cntr - ck_zqinit < TZQINIT) $display ("%m: at time %t ERROR: tZQinit violation during %s", $time, cmd_string[cmd]);
if (ck_cntr - ck_zqoper < TZQOPER) $display ("%m: at time %t ERROR: tZQoper violation during %s", $time, cmd_string[cmd]);
if (ck_cntr - ck_zqcs < TZQCS) $display ("%m: at time %t ERROR: tZQCS violation during %s", $time, cmd_string[cmd]); end
// power down
{1'bx, DIFF_BANK , PWR_DOWN , LOAD_MODE} ,
{1'bx, DIFF_BANK , PWR_DOWN , REFRESH } ,
{1'bx, DIFF_BANK , PWR_DOWN , PRECHARGE} ,
{1'bx, DIFF_BANK , PWR_DOWN , ACTIVATE } ,
{1'bx, DIFF_BANK , PWR_DOWN , WRITE } ,
{1'bx, DIFF_BANK , PWR_DOWN , ZQ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PWR_DOWN , READ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]);
else if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PWR_DOWN , PWR_DOWN } ,
{1'bx, DIFF_BANK , PWR_DOWN , SELF_REF } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]);
if ((tm_power_down > tm_refresh) && ($time - tm_refresh < TRFC_MIN)) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]);
if ((tm_refresh > tm_power_down) && (($time - tm_power_down < TXPDLL) || (ck_cntr - ck_power_down < TXPDLL_TCK))) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]);
if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end
// self refresh
{1'bx, DIFF_BANK , SELF_REF , LOAD_MODE} ,
{1'bx, DIFF_BANK , SELF_REF , REFRESH } ,
{1'bx, DIFF_BANK , SELF_REF , PRECHARGE} ,
{1'bx, DIFF_BANK , SELF_REF , ACTIVATE } ,
{1'bx, DIFF_BANK , SELF_REF , WRITE } ,
{1'bx, DIFF_BANK , SELF_REF , ZQ } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , SELF_REF , READ } : begin if (ck_cntr - ck_self_refresh < TXSDLL) $display ("%m: at time %t ERROR: tXSDLL violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , SELF_REF , PWR_DOWN } ,
{1'bx, DIFF_BANK , SELF_REF , SELF_REF } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]);
if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end
endcase
end
endtask
task cmd_task;
input cke;
input [2:0] cmd;
input [BA_BITS-1:0] bank;
input [ADDR_BITS-1:0] addr;
reg [`BANKS:0] i;
integer j;
reg [`BANKS:0] tfaw_cntr;
reg [COL_BITS-1:0] col;
reg group;
begin
// tRFC max check
if (!er_trfc_max && !in_self_refresh) begin
if ($time - tm_refresh > TRFC_MAX && check_strict_timing) begin
$display ("%m: at time %t ERROR: tRFC maximum violation during %s", $time, cmd_string[cmd]);
er_trfc_max = 1;
end
end
if (cke) begin
if ((cmd < NOP) && (cmd != PRECHARGE)) begin
if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK))
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(SAME_BANK , bank, j, cmd);
chk_err(DIFF_BANK , bank, j, cmd);
chk_err(DIFF_GROUP, bank, j, cmd);
end
end
case (cmd)
LOAD_MODE : begin
if (|odt_pipeline)
$display ("%m: at time %t ERROR: ODTL violation during %s", $time, cmd_string[cmd]);
if (odt_state)
$display ("%m: at time %t ERROR: ODT must be off prior to %s", $time, cmd_string[cmd]);
if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank);
if (bank>>2) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bank bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
case (bank)
0 : begin
// Burst Length
if (addr[1:0] == 2'b00) begin
burst_length = 8;
blotf = 0;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
end else if (addr[1:0] == 2'b01) begin
burst_length = 8;
blotf = 1;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Select via A12", $time, cmd_string[cmd], bank);
end else if (addr[1:0] == 2'b10) begin
burst_length = 4;
blotf = 0;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Fixed %d (chop)", $time, cmd_string[cmd], bank, burst_length);
end else if (feature_truebl4 && (addr[1:0] == 2'b11)) begin
burst_length = 4;
blotf = 0;
truebl4 = 1;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = True %d", $time, cmd_string[cmd], bank, burst_length);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, addr[1:0]);
end
// Burst Order
burst_order = addr[3];
if (!burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank);
end else if (burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order);
end
// CAS Latency
cas_latency = {addr[2],addr[6:4]} + 4;
set_latency;
if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end
// Reserved
if (addr[7] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// DLL Reset
dll_reset = addr[8];
if (!dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank);
end else if (dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank);
dll_locked = 0;
init_dll_reset = 1;
ck_dll_reset <= ck_cntr;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset);
end
// Write Recovery
if (addr[11:9] == 0) begin
write_recovery = 16;
end else if (addr[11:9] < 4) begin
write_recovery = addr[11:9] + 4;
end else begin
write_recovery = 2*addr[11:9];
end
if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end
// Power Down Mode
low_power = !addr[12];
if (!low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL on", $time, cmd_string[cmd], bank);
end else if (low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL off", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power);
end
// Reserved
if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
1 : begin
// DLL Enable
dll_en = !addr[0];
if (!dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d DLL off mode is not modeled", $time, cmd_string[cmd], bank);
end else if (dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en);
end
// Output Drive Strength
if ({addr[5], addr[1]} == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/6);
end else if ({addr[5], addr[1]} == 2'b01) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/7);
end else if ({addr[5], addr[1]} == 2'b11) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/5);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, {addr[5], addr[1]});
end
// ODT Rtt (Rtt_NOM)
odt_rtt_nom = {addr[9], addr[6], addr[2]};
if (odt_rtt_nom == 3'b000) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank);
odt_en = 0;
end else if ((odt_rtt_nom < 4) || ((!addr[7] || (addr[7] && addr[12])) && (odt_rtt_nom < 6))) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_nom(odt_rtt_nom));
odt_en = 1;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt_nom);
odt_en = 0;
end
// Report the additive latency value
al = addr[4:3];
set_latency;
if (al == 0) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, al);
end else if ((al >= AL_MIN) && (al <= AL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = CL - %d", $time, cmd_string[cmd], bank, al);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, al);
end
// Write Levelization
write_levelization = addr[7];
if (!write_levelization) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Disabled", $time, cmd_string[cmd], bank);
end else if (write_levelization) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Write Levelization = %d", $time, cmd_string[cmd], bank, write_levelization);
end
// Reserved
if (addr[8] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// Reserved
if (addr[10] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// TDQS Enable
tdqs_en = addr[11];
if (!tdqs_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (tdqs_en) begin
if (8 == DQ_BITS) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Enabled", $time, cmd_string[cmd], bank);
end
else begin
$display ("%m: at time %t WARNING: %s %d Illegal TDQS Enable. TDQS only exists on a x8 part", $time, cmd_string[cmd], bank);
tdqs_en = 0;
end
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal TDQS Enable = %d", $time, cmd_string[cmd], bank, tdqs_en);
end
// Output Enable
out_en = !addr[12];
if (!out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Disabled", $time, cmd_string[cmd], bank);
end else if (out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Qoff = %d", $time, cmd_string[cmd], bank, out_en);
end
// Reserved
if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
2 : begin
if (feature_pasr) begin
// Partial Array Self Refresh
pasr = addr[2:0];
case (pasr)
3'b000 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-7", $time, cmd_string[cmd], bank);
3'b001 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-3", $time, cmd_string[cmd], bank);
3'b010 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-1", $time, cmd_string[cmd], bank);
3'b011 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0", $time, cmd_string[cmd], bank);
3'b100 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 2-7", $time, cmd_string[cmd], bank);
3'b101 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 4-7", $time, cmd_string[cmd], bank);
3'b110 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 6-7", $time, cmd_string[cmd], bank);
3'b111 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 7", $time, cmd_string[cmd], bank);
default : $display ("%m: at time %t ERROR: %s %d Illegal Partial Array Self Refresh = %d", $time, cmd_string[cmd], bank, pasr);
endcase
end
else
if (addr[2:0] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// CAS Write Latency
cas_write_latency = addr[5:3]+5;
set_latency;
if ((cas_write_latency >= CWL_MIN) && (cas_write_latency <= CWL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency);
end
// Auto Self Refresh Method
asr = addr[6];
if (!asr) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Disabled", $time, cmd_string[cmd], bank);
end else if (asr) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Enabled", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Auto Self Refresh is not modeled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Auto Self Refresh = %d", $time, cmd_string[cmd], bank, asr);
end
// Self Refresh Temperature
srt = addr[7];
if (!srt) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Normal", $time, cmd_string[cmd], bank);
end else if (srt) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Extended", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Self Refresh Temperature is not modeled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Self Refresh Temperature = %d", $time, cmd_string[cmd], bank, srt);
end
if (asr && srt)
$display ("%m: at time %t ERROR: %s %d SRT must be set to 0 when ASR is enabled.", $time, cmd_string[cmd], bank);
// Reserved
if (addr[8] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// Dynamic ODT (Rtt_WR)
odt_rtt_wr = addr[10:9];
if (odt_rtt_wr == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT = Disabled", $time, cmd_string[cmd], bank);
dyn_odt_en = 0;
end else if ((odt_rtt_wr > 0) && (odt_rtt_wr < 3)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_wr(odt_rtt_wr));
dyn_odt_en = 1;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Dynamic ODT = %d", $time, cmd_string[cmd], bank, odt_rtt_wr);
dyn_odt_en = 0;
end
// Reserved
if (ADDR_BITS>13 && addr[13:11] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
3 : begin
mpr_select = addr[1:0];
// MultiPurpose Register Select
if (mpr_select == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Select = Pre-defined pattern", $time, cmd_string[cmd], bank);
end else begin
if (check_strict_mrbits) $display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Select = %d", $time, cmd_string[cmd], bank, mpr_select);
end
// MultiPurpose Register Enable
mpr_en = addr[2];
if (!mpr_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (mpr_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Enable = %d", $time, cmd_string[cmd], bank, mpr_en);
end
// Reserved
if (ADDR_BITS>13 && addr[13:3] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
endcase
if (dyn_odt_en && write_levelization)
$display ("%m: at time %t ERROR: Dynamic ODT is not available during Write Leveling mode.", $time);
init_mode_reg[bank] = 1;
mode_reg[bank] = addr;
tm_load_mode <= $time;
ck_load_mode <= ck_cntr;
end
end
REFRESH : begin
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]);
er_trfc_max = 0;
ref_cntr = ref_cntr + 1;
tm_refresh <= $time;
ck_refresh <= ck_cntr;
end
end
PRECHARGE : begin
if (addr[AP]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]);
end
// PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state),
// or if the previously open row is already in the process of precharging
if (|active_bank) begin
if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK))
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]);
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
for (i=0; i<`BANKS; i=i+1) begin
if (active_bank[i]) begin
if (addr[AP] || (i == bank)) begin
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(SAME_BANK, i, j, cmd);
chk_err(DIFF_BANK, i, j, cmd);
end
if (auto_precharge_bank[i]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], i);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], i);
active_bank[i] = 1'b0;
tm_bank_precharge[i] <= $time;
tm_precharge <= $time;
ck_precharge <= ck_cntr;
end
end
end
end
end
end
end
ACTIVATE : begin
tfaw_cntr = 0;
for (i=0; i<`BANKS; i=i+1) begin
if ($time - tm_bank_activate[i] < TFAW) begin
tfaw_cntr = tfaw_cntr + 1;
end
end
if (tfaw_cntr > 3) begin
$display ("%m: at time %t ERROR: tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (active_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Bank %d must be Precharged.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr >= 1<<ROW_BITS) begin
$display ("%m: at time %t WARNING: row = %h does not exist. Maximum row = %h", $time, addr, (1<<ROW_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d row %h", $time, cmd_string[cmd], bank, addr);
active_bank[bank] = 1'b1;
active_row[bank] = addr;
tm_group_activate[bank[1]] <= $time;
tm_activate <= $time;
tm_bank_activate[bank] <= $time;
ck_group_activate[bank[1]] <= ck_cntr;
ck_activate <= ck_cntr;
end
end
WRITE : begin
if ((!rd_bc && blotf) || (burst_length == 4)) begin // BL=4
if (truebl4) begin
if (ck_cntr - ck_group_read[bank[1]] < read_latency + TCCD/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
if (ck_cntr - ck_read < read_latency + TCCD_DG/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW_DG violation during %s to bank %d", $time, cmd_string[cmd], bank);
end else begin
if (ck_cntr - ck_read < read_latency + TCCD/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
end else begin // BL=8
if (ck_cntr - ck_read < read_latency + TCCD + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank]) begin
if (check_strict_timing) $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (ck_cntr - ck_write < burst_length/2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP]) begin
auto_precharge_bank[bank] = 1'b1;
write_precharge_bank[bank] = 1'b1;
end
col = {addr[BC-1:AP+1], addr[AP-1:0]}; // assume BC > AP
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
col = col & -4;
end else begin // BL=8
col = col & -8;
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
wr_pipeline[2*write_latency + 1] = 1;
ba_pipeline[2*write_latency + 1] = bank;
row_pipeline[2*write_latency + 1] = active_row[bank];
col_pipeline[2*write_latency + 1] = col;
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
bl_pipeline[2*write_latency + 1] = 4;
if (mpr_en && col%4) begin
$display ("%m: at time %t WARNING: col[1:0] must be set to 2'b00 during a BL4 Multipurpose Register read", $time);
end
end else begin // BL=8
bl_pipeline[2*write_latency + 1] = 8;
if (odt_in) begin
ck_odth8 <= ck_cntr;
end
end
for (j=0; j<(burst_length + 4); j=j+1) begin
dyn_odt_pipeline[2*(write_latency - 2) + j] = 1'b1; // ODTLcnw = WL - 2, ODTLcwn = BL/2 + 2
end
ck_bank_write[bank] <= ck_cntr;
ck_group_write[bank[1]] <= ck_cntr;
ck_write <= ck_cntr;
end
end
READ : begin
if (!dll_locked)
$display ("%m: at time %t WARNING: tDLLK violation during %s.", $time, cmd_string[cmd]);
if (mpr_en && (addr[1:0] != 2'b00)) begin
$display ("%m: at time %t ERROR: %s Failure. addr[1:0] must be zero during Multipurpose Register Read.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank] && !mpr_en) begin
if (check_strict_timing) $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (ck_cntr - ck_read < burst_length/2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP] && !mpr_en) begin
auto_precharge_bank[bank] = 1'b1;
read_precharge_bank[bank] = 1'b1;
end
col = {addr[BC-1:AP+1], addr[AP-1:0]}; // assume BC > AP
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
rd_pipeline[2*read_latency - 1] = 1;
ba_pipeline[2*read_latency - 1] = bank;
row_pipeline[2*read_latency - 1] = active_row[bank];
col_pipeline[2*read_latency - 1] = col;
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
bl_pipeline[2*read_latency - 1] = 4;
if (mpr_en && col%4) begin
$display ("%m: at time %t WARNING: col[1:0] must be set to 2'b00 during a BL4 Multipurpose Register read", $time);
end
end else begin // BL=8
bl_pipeline[2*read_latency - 1] = 8;
if (mpr_en && col%8) begin
$display ("%m: at time %t WARNING: col[2:0] must be set to 3'b000 during a BL8 Multipurpose Register read", $time);
end
end
rd_bc = addr[BC];
ck_bank_read[bank] <= ck_cntr;
ck_group_read[bank[1]] <= ck_cntr;
ck_read <= ck_cntr;
end
end
ZQ : begin
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s long = %d", $time, cmd_string[cmd], addr[AP]);
if (addr[AP]) begin
zq_set = 1;
if (init_done) begin
ck_zqoper <= ck_cntr;
end else begin
ck_zqinit <= ck_cntr;
end
end else begin
ck_zqcs <= ck_cntr;
end
end
end
NOP: begin
if (in_power_down) begin
if (($time - tm_freq_change < TCKSRX) || (ck_cntr - ck_freq_change < TCKSRX_TCK))
$display ("%m: at time %t ERROR: tCKSRX violation during Power Down Exit", $time);
if ($time - tm_cke_cmd > TPD_MAX)
$display ("%m: at time %t ERROR: tPD maximum violation during Power Down Exit", $time);
if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time);
in_power_down = 0;
if ((active_bank == 0) && low_power) begin // precharge power down with dll off
if (ck_cntr - ck_odt < write_latency - 1)
$display ("%m: at time %t WARNING: tANPD violation during Power Down Exit. Synchronous or asynchronous change in termination resistance is possible.", $time);
tm_slow_exit_pd <= $time;
ck_slow_exit_pd <= ck_cntr;
end
tm_power_down <= $time;
ck_power_down <= ck_cntr;
end
if (in_self_refresh) begin
if (($time - tm_freq_change < TCKSRX) || (ck_cntr - ck_freq_change < TCKSRX_TCK))
$display ("%m: at time %t ERROR: tCKSRX violation during Self Refresh Exit", $time);
if (ck_cntr - ck_cke_cmd < TCKESR_TCK)
$display ("%m: at time %t ERROR: tCKESR violation during Self Refresh Exit", $time);
if ($time - tm_cke < TISXR)
$display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time);
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time);
in_self_refresh = 0;
ck_dll_reset <= ck_cntr;
ck_self_refresh <= ck_cntr;
tm_self_refresh <= $time;
tm_refresh <= $time;
end
end
endcase
if ((prev_cke !== 1) && (cmd !== NOP)) begin
$display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time);
end
if (!init_done) begin
case (init_step)
0 : begin
if ($time - tm_rst_n < 500000000 && check_strict_timing)
$display ("%m at time %t WARNING: 500 us is required after RST_N goes inactive before CKE goes active.", $time);
tm_txpr <= $time;
ck_txpr <= ck_cntr;
init_step = init_step + 1;
end
1 : if (dll_en) init_step = init_step + 1;
2 : begin
if (&init_mode_reg && init_dll_reset && zq_set) begin
if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time);
init_done = 1;
end
end
endcase
end
end else if (prev_cke) begin
if ((!init_done) && (init_step > 1)) begin
$display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end
case (cmd)
REFRESH : begin
if ($time - tm_txpr < TXPR)
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[SELF_REF]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(DIFF_BANK, bank, j, SELF_REF);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. Multipurpose Register must be disabled.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. All banks must be Precharged.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (odt_state) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. ODT must be off prior to entering Self Refresh", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time);
if (feature_pasr)
// Partial Array Self Refresh
case (pasr)
3'b000 : ;//keep Bank 0-7
3'b001 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 4-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hF0); end
3'b010 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 2-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFC); end
3'b011 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 1-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFE); end
3'b100 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-1 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h03); end
3'b101 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-3 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h0F); end
3'b110 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-5 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h3F); end
3'b111 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-6 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h7F); end
endcase
in_self_refresh = 1;
dll_locked = 0;
end
end
NOP : begin
// entering precharge power down with dll off and tANPD has not been satisfied
if (low_power && (active_bank == 0) && |odt_pipeline)
$display ("%m: at time %t WARNING: tANPD violation during %s. Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]);
if ($time - tm_txpr < TXPR)
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[PWR_DOWN]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(DIFF_BANK, bank, j, PWR_DOWN);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: Power Down Failure. Multipurpose Register must be disabled.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: Power Down Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) begin
if (|active_bank) begin
$display ("%m: at time %t INFO: Active Power Down Enter", $time);
end else begin
$display ("%m: at time %t INFO: Precharge Power Down Enter", $time);
end
end
in_power_down = 1;
end
end
default : begin
$display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time);
end
endcase
end else if (in_self_refresh || in_power_down) begin
if ((ck_cntr - ck_cke_cmd <= TCPDED) && (cmd !== NOP))
$display ("%m: at time %t ERROR: tCPDED violation during Power Down or Self Refresh Entry. NOP or Deselect is required.", $time);
end
prev_cke = cke;
end
endtask
task data_task;
reg [BA_BITS-1:0] bank;
reg [ROW_BITS-1:0] row;
reg [COL_BITS-1:0] col;
integer i;
integer j;
begin
if (diff_ck) begin
for (i=0; i<32; i=i+1) begin
if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg)))
$display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/16], i%16);
if (check_write_dqs_high[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/16], i%16);
end
check_write_dqs_high <= 0;
end else begin
for (i=0; i<32; i=i+1) begin
if (dll_locked && dq_in_valid) begin
tm_tdqss = abs_value(1.0*tm_ck_pos - tm_dqss_pos[i]);
if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg))
$display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
if (check_write_dqs_low[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/16], i%16);
end
check_write_preamble <= 0;
check_write_postamble <= 0;
check_write_dqs_low <= 0;
end
if (wr_pipeline[0] || rd_pipeline[0]) begin
bank = ba_pipeline[0];
row = row_pipeline[0];
col = col_pipeline[0];
burst_cntr = 0;
memory_read(bank, row, col, memory_data);
end
// burst counter
if (burst_cntr < burst_length) begin
burst_position = col ^ burst_cntr;
if (!burst_order) begin
burst_position[BO_BITS-1:0] = col + burst_cntr;
end
burst_cntr = burst_cntr + 1;
end
// write dqs counter
if (wr_pipeline[WDQS_PRE + 1]) begin
wdqs_cntr = WDQS_PRE + bl_pipeline[WDQS_PRE + 1] + WDQS_PST - 1;
end
// write dqs
if ((wr_pipeline[2]) && (wdq_cntr == 0)) begin //write preamble
check_write_preamble <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 1) begin // write data
if ((wdqs_cntr - WDQS_PST)%2) begin
check_write_dqs_high <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end else begin
check_write_dqs_low <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
end
if (wdqs_cntr == WDQS_PST) begin // write postamble
check_write_postamble <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 0) begin
wdqs_cntr = wdqs_cntr - 1;
end
// write dq
if (dq_in_valid) begin // write data
bit_mask = 0;
if (diff_ck) begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_neg[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_neg<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end else begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_pos[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_pos<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end
dq_temp = memory_data>>(burst_position*DQ_BITS);
if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
if (burst_cntr%BL_MIN == 0) begin
memory_write(bank, row, col, memory_data);
end
end
if (wr_pipeline[1]) begin
wdq_cntr = bl_pipeline[1];
end
if (wdq_cntr > 0) begin
wdq_cntr = wdq_cntr - 1;
dq_in_valid = 1'b1;
end else begin
dq_in_valid = 1'b0;
dqs_in_valid <= 1'b0;
for (i=0; i<31; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
end
if (wr_pipeline[0]) begin
b2b_write <= 1'b0;
end
if (wr_pipeline[2]) begin
if (dqs_in_valid) begin
b2b_write <= 1'b1;
end
dqs_in_valid <= 1'b1;
wr_burst_length = bl_pipeline[2];
end
// read dqs enable counter
if (rd_pipeline[RDQSEN_PRE]) begin
rdqsen_cntr = RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1;
end
if (rdqsen_cntr > 0) begin
rdqsen_cntr = rdqsen_cntr - 1;
dqs_out_en = 1'b1;
end else begin
dqs_out_en = 1'b0;
end
// read dqs counter
if (rd_pipeline[RDQS_PRE]) begin
rdqs_cntr = RDQS_PRE + bl_pipeline[RDQS_PRE] + RDQS_PST - 1;
end
// read dqs
if (((rd_pipeline>>1 & {RDQS_PRE{1'b1}}) > 0) && (rdq_cntr == 0)) begin //read preamble
dqs_out = 1'b0;
end else if (rdqs_cntr > RDQS_PST) begin // read data
dqs_out = rdqs_cntr - RDQS_PST;
end else if (rdqs_cntr > 0) begin // read postamble
dqs_out = 1'b0;
end else begin
dqs_out = 1'b1;
end
if (rdqs_cntr > 0) begin
rdqs_cntr = rdqs_cntr - 1;
end
// read dq enable counter
if (rd_pipeline[RDQEN_PRE]) begin
rdqen_cntr = RDQEN_PRE + bl_pipeline[RDQEN_PRE] + RDQEN_PST;
end
if (rdqen_cntr > 0) begin
rdqen_cntr = rdqen_cntr - 1;
dq_out_en = 1'b1;
end else begin
dq_out_en = 1'b0;
end
// read dq
if (rd_pipeline[0]) begin
rdq_cntr = bl_pipeline[0];
end
if (rdq_cntr > 0) begin // read data
if (mpr_en) begin
`ifdef MPR_DQ0 // DQ0 output MPR data, other DQ low
if (mpr_select == 2'b00) begin // Calibration Pattern
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, calibration_pattern[burst_position]}};
end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS)
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, temp_sensor[burst_position]}};
end else begin // Reserved
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, 1'bx}};
end
`else // all DQ output MPR data
if (mpr_select == 2'b00) begin // Calibration Pattern
dq_temp = {DQS_BITS{{`DQ_PER_DQS{calibration_pattern[burst_position]}}}};
end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS)
dq_temp = {DQS_BITS{{`DQ_PER_DQS{temp_sensor[burst_position]}}}};
end else begin // Reserved
dq_temp = {DQS_BITS{{`DQ_PER_DQS{1'bx}}}};
end
`endif
if (DEBUG) $display ("%m: at time %t READ @ DQS MultiPurpose Register %d, col = %d, data = %b", $time, mpr_select, burst_position, dq_temp[0]);
end else begin
dq_temp = memory_data>>(burst_position*DQ_BITS);
if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
end
dq_out = dq_temp;
rdq_cntr = rdq_cntr - 1;
end else begin
dq_out = {DQ_BITS{1'b1}};
end
// delay signals prior to output
if (RANDOM_OUT_DELAY && (dqs_out_en || (|dqs_out_en_dly) || dq_out_en || (|dq_out_en_dly))) begin
for (i=0; i<DQS_BITS; i=i+1) begin
// DQSCK requirements
// 1.) less than tDQSCK
// 2.) greater than -tDQSCK
// 3.) cannot change more than tQH + tDQSQ from previous DQS edge
dqsck_max = TDQSCK;
if (dqsck_max > dqsck[i] + TQH*tck_avg + TDQSQ) begin
dqsck_max = dqsck[i] + TQH*tck_avg + TDQSQ;
end
dqsck_min = -1*TDQSCK;
if (dqsck_min < dqsck[i] - TQH*tck_avg - TDQSQ) begin
dqsck_min = dqsck[i] - TQH*tck_avg - TDQSQ;
end
// DQSQ requirements
// 1.) less than tDQSQ
// 2.) greater than 0
// 3.) greater than tQH from the previous DQS edge
dqsq_min = 0;
if (dqsq_min < dqsck[i] - TQH*tck_avg) begin
dqsq_min = dqsck[i] - TQH*tck_avg;
end
if (dqsck_min == dqsck_max) begin
dqsck[i] = dqsck_min;
end else begin
dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max);
end
dqsq_max = TDQSQ + dqsck[i];
dqs_out_en_dly[i] <= #(tck_avg/2) dqs_out_en;
dqs_out_dly[i] <= #(tck_avg/2 + dqsck[i]) dqs_out;
if (!write_levelization) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2) dq_out_en;
if (dqsq_min == dqsq_max) begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + dqsq_min) dq_out[i*`DQ_PER_DQS + j];
end else begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j];
end
end
end
end
end else begin
out_delay = tck_avg/2;
dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}};
dqs_out_dly <= #(out_delay) {DQS_BITS{dqs_out }};
if (write_levelization !== 1'b1) begin
dq_out_en_dly <= #(out_delay) {DQ_BITS {dq_out_en }};
dq_out_dly <= #(out_delay) {DQ_BITS {dq_out }};
end
end
end
endtask
always @ (posedge rst_n_in) begin : reset
integer i;
if (rst_n_in) begin
if ($time < 200000000 && check_strict_timing)
$display ("%m at time %t WARNING: 200 us is required before RST_N goes inactive.", $time);
if (cke_in !== 1'b0)
$display ("%m: at time %t ERROR: CKE must be inactive when RST_N goes inactive.", $time);
if ($time - tm_cke < 10000)
$display ("%m: at time %t ERROR: CKE must be maintained inactive for 10 ns before RST_N goes inactive.", $time);
// clear memory
`ifdef MAX_MEM
// verification group does not erase memory
// for (banki = 0; banki < `BANKS; banki = banki + 1) begin
// $fclose(memfd[banki]);
// memfd[banki] = open_bank_file(banki);
// end
`else
memory_used <= 0; //erase memory
`endif
end
end
always @(negedge rst_n_in or posedge diff_ck or negedge diff_ck) begin : main
integer i;
if (!rst_n_in) begin
reset_task;
end else begin
if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1))
$display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time);
data_task;
// Clock Frequency Change is legal:
// 1.) During Self Refresh
// 2.) During Precharge Power Down (DLL on or off)
if (in_self_refresh || (in_power_down && (active_bank == 0))) begin
if (diff_ck) begin
tjit_per_rtime = $time - tm_ck_pos - tck_avg;
end else begin
tjit_per_rtime = $time - tm_ck_neg - tck_avg;
end
if (dll_locked && (abs_value(tjit_per_rtime) > TJIT_PER)) begin
if ((tm_ck_pos - tm_cke_cmd < TCKSRE) || (ck_cntr - ck_cke_cmd < TCKSRE_TCK))
$display ("%m: at time %t ERROR: tCKSRE violation during Self Refresh or Precharge Power Down Entry", $time);
if (odt_state) begin
$display ("%m: at time %t ERROR: Clock Frequency Change Failure. ODT must be off prior to Clock Frequency Change.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Clock Frequency Change detected. DLL Reset is Required.", $time);
tm_freq_change <= $time;
ck_freq_change <= ck_cntr;
dll_locked = 0;
end
end
end
if (diff_ck) begin
// check setup of command signals
if ($time > TIS) begin
if ($time - tm_cke < TIS)
$display ("%m: at time %t ERROR: tIS violation on CKE by %t", $time, tm_cke + TIS - $time);
if (cke_in) begin
for (i=0; i<22; i=i+1) begin
if ($time - tm_cmd_addr[i] < TIS)
$display ("%m: at time %t ERROR: tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time);
end
end
end
// update current state
if (dll_locked) begin
if (mr_chk == 0) begin
mr_chk = 1;
end else if (init_mode_reg[0] && (mr_chk == 1)) begin
// check CL value against the clock frequency
if (cas_latency*tck_avg < CL_TIME && check_strict_timing)
$display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg);
// check WR value against the clock frequency
if (ceil(write_recovery*tck_avg) < TWR)
$display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg);
// check the CWL value against the clock frequency
if (check_strict_timing) begin
case (cas_write_latency)
5 : if (tck_avg < 2500.0) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
6 : if ((tck_avg < 1875.0) || (tck_avg >= 2500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
7 : if ((tck_avg < 1500.0) || (tck_avg >= 1875.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
8 : if ((tck_avg < 1250.0) || (tck_avg >= 1500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
9 : if ((tck_avg < 15e3/14) || (tck_avg >= 1250.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
10: if ((tck_avg < 937.5) || (tck_avg >= 15e3/14)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
default : $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
endcase
// check the CL value against the clock frequency
if (!valid_cl(cas_latency, cas_write_latency))
$display ("%m: at time %t ERROR: CAS Latency = %d is not valid when CAS Write Latency = %d", $time, cas_latency, cas_write_latency);
end
mr_chk = 2;
end
end else if (!in_self_refresh) begin
mr_chk = 0;
if (ck_cntr - ck_dll_reset == TDLLK) begin
dll_locked = 1;
end
end
if (|auto_precharge_bank) begin
for (i=0; i<`BANKS; i=i+1) begin
// Write with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Write Latency PLUS BL/2 cycles PLUS WR after Write command
if (write_precharge_bank[i]) begin
if ($time - tm_bank_activate[i] >= TRAS_MIN) begin
if (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
write_precharge_bank[i] = 0;
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
ck_precharge = ck_cntr;
end
end
end
// Read with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Additive Latency plus 4 cycles after Read command
// 3. tRTP after the last 8-bit prefetch
if (read_precharge_bank[i]) begin
if (($time - tm_bank_activate[i] >= TRAS_MIN) && (ck_cntr - ck_bank_read[i] >= additive_latency + TRTP_TCK)) begin
read_precharge_bank[i] = 0;
// In case the internal precharge is pushed out by tRTP, tRP starts at the point where
// the internal precharge happens (not at the next rising clock edge after this event).
if ($time - tm_bank_read_end[i] < TRTP) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i);
active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
ck_precharge = ck_cntr;
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
ck_precharge = ck_cntr;
end
end
end
end
end
// respond to incoming command
if (cke_in ^ prev_cke) begin
tm_cke_cmd <= $time;
ck_cke_cmd <= ck_cntr;
end
cmd_task(cke_in, cmd_n_in, ba_in, addr_in);
if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin
al_pipeline[2*additive_latency] = 1'b1;
end
if (al_pipeline[0]) begin
// check tRCD after additive latency
if ((rd_pipeline[2*cas_latency - 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD))
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[READ]);
if ((wr_pipeline[2*cas_write_latency + 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_write_latency + 1]] < TRCD))
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[WRITE]);
// check tWTR after additive latency
if (rd_pipeline[2*cas_latency - 1]) begin //{
if (truebl4) begin //{
i = ba_pipeline[2*cas_latency - 1];
if ($time - tm_group_write_end[i[1]] < TWTR)
$display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]);
if ($time - tm_write_end < TWTR_DG)
$display ("%m: at time %t ERROR: tWTR_DG violation during %s", $time, cmd_string[READ]);
end else begin
if ($time - tm_write_end < TWTR)
$display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]);
end
end
end
if (rd_pipeline) begin
if (rd_pipeline[2*cas_latency - 1]) begin
tm_bank_read_end[ba_pipeline[2*cas_latency - 1]] <= $time;
end
end
for (i=0; i<`BANKS; i=i+1) begin
if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin
tm_bank_write_end[i] <= $time;
tm_group_write_end[i[1]] <= $time;
tm_write_end <= $time;
end
end
// clk pin is disabled during self refresh
if (!in_self_refresh && tm_ck_pos ) begin
tjit_cc_time = $time - tm_ck_pos - tck_i;
tck_i = $time - tm_ck_pos;
tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tck_avg = tck_avg + tck_i/$itor(TDLLK);
tck_sample[ck_cntr%TDLLK] = tck_i;
tjit_per_rtime = tck_i - tck_avg;
if (dll_locked && check_strict_timing) begin
// check accumulated error
terr_nper_rtime = 0;
for (i=0; i<12; i=i+1) begin
terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg;
terr_nper_rtime = abs_value(terr_nper_rtime);
case (i)
0 :;
1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER);
2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER);
3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER);
4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER);
5 : if (terr_nper_rtime - TERR_6PER >= 1.0) $display ("%m: at time %t ERROR: tERR(6per) violation by %f ps.", $time, terr_nper_rtime - TERR_6PER);
6 : if (terr_nper_rtime - TERR_7PER >= 1.0) $display ("%m: at time %t ERROR: tERR(7per) violation by %f ps.", $time, terr_nper_rtime - TERR_7PER);
7 : if (terr_nper_rtime - TERR_8PER >= 1.0) $display ("%m: at time %t ERROR: tERR(8per) violation by %f ps.", $time, terr_nper_rtime - TERR_8PER);
8 : if (terr_nper_rtime - TERR_9PER >= 1.0) $display ("%m: at time %t ERROR: tERR(9per) violation by %f ps.", $time, terr_nper_rtime - TERR_9PER);
9 : if (terr_nper_rtime - TERR_10PER >= 1.0) $display ("%m: at time %t ERROR: tERR(10per) violation by %f ps.", $time, terr_nper_rtime - TERR_10PER);
10 : if (terr_nper_rtime - TERR_11PER >= 1.0) $display ("%m: at time %t ERROR: tERR(11per) violation by %f ps.", $time, terr_nper_rtime - TERR_11PER);
11 : if (terr_nper_rtime - TERR_12PER >= 1.0) $display ("%m: at time %t ERROR: tERR(12per) violation by %f ps.", $time, terr_nper_rtime - TERR_12PER);
endcase
end
// check tCK min/max/jitter
if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0)
$display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER);
if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0)
$display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC);
if (TCK_MIN - tck_avg >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg);
if (tck_avg - TCK_MAX >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX);
// check tCL
if (tm_ck_neg - $time < TCL_ABS_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, TCL_ABS_MIN*tck_avg - tm_ck_neg + $time);
if (tcl_avg < TCL_AVG_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_AVG_MIN*tck_avg - tcl_avg);
if (tcl_avg > TCL_AVG_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_AVG_MAX*tck_avg);
end
// calculate the tch avg jitter
tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tch_avg = tch_avg + tch_i/$itor(TDLLK);
tch_sample[ck_cntr%TDLLK] = tch_i;
tjit_ch_rtime = tch_i - tch_avg;
duty_cycle = tch_avg/tck_avg;
// update timers/counters
tcl_i <= $time - tm_ck_neg;
end
prev_odt <= odt_in;
// update timers/counters
ck_cntr <= ck_cntr + 1;
tm_ck_pos = $time;
end else begin
// clk pin is disabled during self refresh
if (!in_self_refresh) begin
if (dll_locked && check_strict_timing) begin
if ($time - tm_ck_pos < TCH_ABS_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, TCH_ABS_MIN*tck_avg - $time + tm_ck_pos);
if (tch_avg < TCH_AVG_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_AVG_MIN*tck_avg - tch_avg);
if (tch_avg > TCH_AVG_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_AVG_MAX*tck_avg);
end
// calculate the tcl avg jitter
tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tcl_avg = tcl_avg + tcl_i/$itor(TDLLK);
tcl_sample[ck_cntr%TDLLK] = tcl_i;
// update timers/counters
tch_i <= $time - tm_ck_pos;
end
tm_ck_neg = $time;
end
// on die termination
if (odt_en || dyn_odt_en) begin
// odt pin is disabled during self refresh
if (!in_self_refresh && diff_ck) begin
if ($time - tm_odt < TIS)
$display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time);
if (prev_odt ^ odt_in) begin
if (!dll_locked)
$display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time);
if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK))
$display ("%m: at time %t ERROR: tMOD violation during ODT transition", $time);
if (ck_cntr - ck_zqinit < TZQINIT)
$display ("%m: at time %t ERROR: TZQinit violation during ODT transition", $time);
if (ck_cntr - ck_zqoper < TZQOPER)
$display ("%m: at time %t ERROR: TZQoper violation during ODT transition", $time);
if (ck_cntr - ck_zqcs < TZQCS)
$display ("%m: at time %t ERROR: tZQcs violation during ODT transition", $time);
// if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK))
// $display ("%m: at time %t ERROR: tXPDLL violation during ODT transition", $time);
if (ck_cntr - ck_self_refresh < TXSDLL)
$display ("%m: at time %t ERROR: tXSDLL violation during ODT transition", $time);
if (in_self_refresh)
$display ("%m: at time %t ERROR: Illegal ODT transition during Self Refresh.", $time);
if (!odt_in && (ck_cntr - ck_odt < ODTH4))
$display ("%m: at time %t ERROR: ODTH4 violation during ODT transition", $time);
if (!odt_in && (ck_cntr - ck_odth8 < ODTH8))
$display ("%m: at time %t ERROR: ODTH8 violation during ODT transition", $time);
if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK))
$display ("%m: at time %t WARNING: tXPDLL during ODT transition. Synchronous or asynchronous change in termination resistance is possible.", $time);
// async ODT mode applies:
// 1.) during precharge power down with DLL off
// 2.) if tANPD has not been satisfied
// 3.) until tXPDLL has been satisfied
if ((in_power_down && low_power && (active_bank == 0)) || ($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) begin
odt_state = odt_in;
if (DEBUG && odt_en) $display ("%m: at time %t INFO: Async On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom));
if (odt_state) begin
odt_state_dly <= #(TAONPD) odt_state;
end else begin
odt_state_dly <= #(TAOFPD) odt_state;
end
// sync ODT mode applies:
// 1.) during normal operation
// 2.) during active power down
// 3.) during precharge power down with DLL on
end else begin
odt_pipeline[2*(write_latency - 2)] = 1'b1; // ODTLon, ODTLoff
end
ck_odt <= ck_cntr;
end
end
if (odt_pipeline[0]) begin
odt_state = ~odt_state;
if (DEBUG && odt_en) $display ("%m: at time %t INFO: Sync On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom));
if (odt_state) begin
odt_state_dly <= #(TAON) odt_state;
end else begin
odt_state_dly <= #(TAOF*tck_avg) odt_state;
end
end
if (rd_pipeline[RDQSEN_PRE]) begin
odt_cntr = 1 + RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1;
end
if (odt_cntr > 0) begin
if (odt_state) begin
$display ("%m: at time %t ERROR: On Die Termination must be OFF during Read data transfer.", $time);
end
odt_cntr = odt_cntr - 1;
end
if (dyn_odt_en && odt_state) begin
if (DEBUG && (dyn_odt_state ^ dyn_odt_pipeline[0]))
$display ("%m: at time %t INFO: Sync On Die Termination Rtt_WR = %d Ohm", $time, {32{dyn_odt_pipeline[0]}} & get_rtt_wr(odt_rtt_wr));
dyn_odt_state = dyn_odt_pipeline[0];
end
dyn_odt_state_dly <= #(TADC*tck_avg) dyn_odt_state;
end
/*
if (cke_in && write_levelization) begin
for (i=0; i<DQS_BITS; i=i+1) begin
if ($time - tm_dqs_pos[i] < TWLH)
$display ("%m: at time %t WARNING: tWLH violation on DQS bit %d positive edge. Indeterminate CK capture is possible.", $time, i);
end
end
*/
// shift pipelines
if (|wr_pipeline || |rd_pipeline || |al_pipeline) begin
al_pipeline = al_pipeline>>1;
wr_pipeline = wr_pipeline>>1;
rd_pipeline = rd_pipeline>>1;
for (i=0; i<`MAX_PIPE; i=i+1) begin
bl_pipeline[i] = bl_pipeline[i+1];
ba_pipeline[i] = ba_pipeline[i+1];
row_pipeline[i] = row_pipeline[i+1];
col_pipeline[i] = col_pipeline[i+1];
end
end
if (|odt_pipeline || |dyn_odt_pipeline) begin
odt_pipeline = odt_pipeline>>1;
dyn_odt_pipeline = dyn_odt_pipeline>>1;
end
end
end
// receiver(s)
task dqs_even_receiver;
input [3:0] i;
reg [63:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_even[i]) begin
if (tdqs_en) begin // tdqs disables dm
dm_in_pos[i] = 1'b0;
end else begin
dm_in_pos[i] = dm_in[i];
end
dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask);
end
end
endtask
always @(posedge dqs_even[ 0]) dqs_even_receiver( 0);
always @(posedge dqs_even[ 1]) dqs_even_receiver( 1);
always @(posedge dqs_even[ 2]) dqs_even_receiver( 2);
always @(posedge dqs_even[ 3]) dqs_even_receiver( 3);
always @(posedge dqs_even[ 4]) dqs_even_receiver( 4);
always @(posedge dqs_even[ 5]) dqs_even_receiver( 5);
always @(posedge dqs_even[ 6]) dqs_even_receiver( 6);
always @(posedge dqs_even[ 7]) dqs_even_receiver( 7);
always @(posedge dqs_even[ 8]) dqs_even_receiver( 8);
always @(posedge dqs_even[ 9]) dqs_even_receiver( 9);
always @(posedge dqs_even[10]) dqs_even_receiver(10);
always @(posedge dqs_even[11]) dqs_even_receiver(11);
always @(posedge dqs_even[12]) dqs_even_receiver(12);
always @(posedge dqs_even[13]) dqs_even_receiver(13);
always @(posedge dqs_even[14]) dqs_even_receiver(14);
always @(posedge dqs_even[15]) dqs_even_receiver(15);
task dqs_odd_receiver;
input [3:0] i;
reg [63:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_odd[i]) begin
if (tdqs_en) begin // tdqs disables dm
dm_in_neg[i] = 1'b0;
end else begin
dm_in_neg[i] = dm_in[i];
end
dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask);
end
end
endtask
always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0);
always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1);
always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2);
always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3);
always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4);
always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5);
always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6);
always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7);
always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8);
always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9);
always @(posedge dqs_odd[10]) dqs_odd_receiver(10);
always @(posedge dqs_odd[11]) dqs_odd_receiver(11);
always @(posedge dqs_odd[12]) dqs_odd_receiver(12);
always @(posedge dqs_odd[13]) dqs_odd_receiver(13);
always @(posedge dqs_odd[14]) dqs_odd_receiver(14);
always @(posedge dqs_odd[15]) dqs_odd_receiver(15);
// Processes to check hold and pulse width of control signals
always @(posedge rst_n_in) begin
if ($time > 100000) begin
if (tm_rst_n + 100000 > $time)
$display ("%m: at time %t ERROR: RST_N pulse width violation by %t", $time, tm_rst_n + 100000 - $time);
end
tm_rst_n = $time;
end
always @(cke_in) begin
if (rst_n_in) begin
if ($time > TIH) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time);
end
if ($time - tm_cke < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW - $time);
end
tm_cke = $time;
end
always @(odt_in) begin
if (rst_n_in && odt_en && !in_self_refresh) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time);
if ($time - tm_odt < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW - $time);
end
tm_odt = $time;
end
task cmd_addr_timing_check;
input i;
reg [4:0] i;
begin
if (rst_n_in && prev_cke) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
if ($time - tm_cmd_addr[i] < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW - $time);
end
tm_cmd_addr[i] = $time;
end
endtask
always @(cs_n_in ) cmd_addr_timing_check( 0);
always @(ras_n_in ) cmd_addr_timing_check( 1);
always @(cas_n_in ) cmd_addr_timing_check( 2);
always @(we_n_in ) cmd_addr_timing_check( 3);
always @(ba_in [ 0]) cmd_addr_timing_check( 4);
always @(ba_in [ 1]) cmd_addr_timing_check( 5);
always @(ba_in [ 2]) cmd_addr_timing_check( 6);
always @(addr_in[ 0]) cmd_addr_timing_check( 7);
always @(addr_in[ 1]) cmd_addr_timing_check( 8);
always @(addr_in[ 2]) cmd_addr_timing_check( 9);
always @(addr_in[ 3]) cmd_addr_timing_check(10);
always @(addr_in[ 4]) cmd_addr_timing_check(11);
always @(addr_in[ 5]) cmd_addr_timing_check(12);
always @(addr_in[ 6]) cmd_addr_timing_check(13);
always @(addr_in[ 7]) cmd_addr_timing_check(14);
always @(addr_in[ 8]) cmd_addr_timing_check(15);
always @(addr_in[ 9]) cmd_addr_timing_check(16);
always @(addr_in[10]) cmd_addr_timing_check(17);
always @(addr_in[11]) cmd_addr_timing_check(18);
always @(addr_in[12]) cmd_addr_timing_check(19);
always @(addr_in[13]) cmd_addr_timing_check(20);
always @(addr_in[14]) cmd_addr_timing_check(21);
always @(addr_in[15]) cmd_addr_timing_check(22);
// Processes to check setup and hold of data signals
task dm_timing_check;
input i;
reg [3:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time);
if (check_dm_tdipw[i]) begin
if ($time - tm_dm[i] < TDIPW)
$display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW - $time);
end
end
check_dm_tdipw[i] <= 1'b0;
tm_dm[i] = $time;
end
endtask
always @(dm_in[ 0]) dm_timing_check( 0);
always @(dm_in[ 1]) dm_timing_check( 1);
always @(dm_in[ 2]) dm_timing_check( 2);
always @(dm_in[ 3]) dm_timing_check( 3);
always @(dm_in[ 4]) dm_timing_check( 4);
always @(dm_in[ 5]) dm_timing_check( 5);
always @(dm_in[ 6]) dm_timing_check( 6);
always @(dm_in[ 7]) dm_timing_check( 7);
always @(dm_in[ 8]) dm_timing_check( 8);
always @(dm_in[ 9]) dm_timing_check( 9);
always @(dm_in[10]) dm_timing_check(10);
always @(dm_in[11]) dm_timing_check(11);
always @(dm_in[12]) dm_timing_check(12);
always @(dm_in[13]) dm_timing_check(13);
always @(dm_in[14]) dm_timing_check(14);
always @(dm_in[15]) dm_timing_check(15);
task dq_timing_check;
input i;
reg [5:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time);
if (check_dq_tdipw[i]) begin
if ($time - tm_dq[i] < TDIPW)
$display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW - $time);
end
end
check_dq_tdipw[i] <= 1'b0;
tm_dq[i] = $time;
end
endtask
always @(dq_in[ 0]) dq_timing_check( 0);
always @(dq_in[ 1]) dq_timing_check( 1);
always @(dq_in[ 2]) dq_timing_check( 2);
always @(dq_in[ 3]) dq_timing_check( 3);
always @(dq_in[ 4]) dq_timing_check( 4);
always @(dq_in[ 5]) dq_timing_check( 5);
always @(dq_in[ 6]) dq_timing_check( 6);
always @(dq_in[ 7]) dq_timing_check( 7);
always @(dq_in[ 8]) dq_timing_check( 8);
always @(dq_in[ 9]) dq_timing_check( 9);
always @(dq_in[10]) dq_timing_check(10);
always @(dq_in[11]) dq_timing_check(11);
always @(dq_in[12]) dq_timing_check(12);
always @(dq_in[13]) dq_timing_check(13);
always @(dq_in[14]) dq_timing_check(14);
always @(dq_in[15]) dq_timing_check(15);
always @(dq_in[16]) dq_timing_check(16);
always @(dq_in[17]) dq_timing_check(17);
always @(dq_in[18]) dq_timing_check(18);
always @(dq_in[19]) dq_timing_check(19);
always @(dq_in[20]) dq_timing_check(20);
always @(dq_in[21]) dq_timing_check(21);
always @(dq_in[22]) dq_timing_check(22);
always @(dq_in[23]) dq_timing_check(23);
always @(dq_in[24]) dq_timing_check(24);
always @(dq_in[25]) dq_timing_check(25);
always @(dq_in[26]) dq_timing_check(26);
always @(dq_in[27]) dq_timing_check(27);
always @(dq_in[28]) dq_timing_check(28);
always @(dq_in[29]) dq_timing_check(29);
always @(dq_in[30]) dq_timing_check(30);
always @(dq_in[31]) dq_timing_check(31);
always @(dq_in[32]) dq_timing_check(32);
always @(dq_in[33]) dq_timing_check(33);
always @(dq_in[34]) dq_timing_check(34);
always @(dq_in[35]) dq_timing_check(35);
always @(dq_in[36]) dq_timing_check(36);
always @(dq_in[37]) dq_timing_check(37);
always @(dq_in[38]) dq_timing_check(38);
always @(dq_in[39]) dq_timing_check(39);
always @(dq_in[40]) dq_timing_check(40);
always @(dq_in[41]) dq_timing_check(41);
always @(dq_in[42]) dq_timing_check(42);
always @(dq_in[43]) dq_timing_check(43);
always @(dq_in[44]) dq_timing_check(44);
always @(dq_in[45]) dq_timing_check(45);
always @(dq_in[46]) dq_timing_check(46);
always @(dq_in[47]) dq_timing_check(47);
always @(dq_in[48]) dq_timing_check(48);
always @(dq_in[49]) dq_timing_check(49);
always @(dq_in[50]) dq_timing_check(50);
always @(dq_in[51]) dq_timing_check(51);
always @(dq_in[52]) dq_timing_check(52);
always @(dq_in[53]) dq_timing_check(53);
always @(dq_in[54]) dq_timing_check(54);
always @(dq_in[55]) dq_timing_check(55);
always @(dq_in[56]) dq_timing_check(56);
always @(dq_in[57]) dq_timing_check(57);
always @(dq_in[58]) dq_timing_check(58);
always @(dq_in[59]) dq_timing_check(59);
always @(dq_in[60]) dq_timing_check(60);
always @(dq_in[61]) dq_timing_check(61);
always @(dq_in[62]) dq_timing_check(62);
always @(dq_in[63]) dq_timing_check(63);
task dqs_pos_timing_check;
input i;
reg [4:0] i;
reg [3:0] j;
begin
if (write_levelization && i<16) begin
if (ck_cntr - ck_load_mode < TWLMRD)
$display ("%m: at time %t ERROR: tWLMRD violation on DQS bit %d positive edge.", $time, i);
/*
if (($time - tm_ck_pos < TWLS) || ($time - tm_ck_neg < TWLS))
$display ("%m: at time %t WARNING: tWLS violation on DQS bit %d positive edge. Indeterminate CK capture is possible.", $time, i);
*/
if (DEBUG)
$display ("%m: at time %t Write Leveling @ DQS ck = %b", $time, diff_ck);
dq_out_en_dly[i*`DQ_PER_DQS] <= #(TWLO) 1'b1;
dq_out_dly[i*`DQ_PER_DQS] <= #(TWLO) diff_ck;
for (j=1; j<`DQ_PER_DQS; j=j+1) begin
dq_out_en_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b1;
dq_out_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b0;
end
end
if (dqs_in_valid && ((wdqs_pos_cntr[i] < wr_burst_length/2) || b2b_write)) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if (check_write_preamble[i]) begin
if ($time - tm_dqs_pos[i] < $rtoi(TWPRE*tck_avg))
$display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/16], i%16);
end else if (check_write_postamble[i]) begin
if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg))
$display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/16], i%16);
end else begin
if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg))
$display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
if ($time - tm_dm[i%16] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%16] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[(i%16)*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%16)*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[(i%16)*`DQ_PER_DQS+j] <= 1'b1;
end
end
if ((wdqs_pos_cntr[i] < wr_burst_length/2) && !b2b_write) begin
wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1;
end else begin
wdqs_pos_cntr[i] <= 1;
end
check_dm_tdipw[i%16] <= 1'b1;
check_write_preamble[i] <= 1'b0;
check_write_postamble[i] <= 1'b0;
check_write_dqs_low[i] <= 1'b0;
tm_dqs[i%16] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
tm_dqss_pos[i] <= $time;
tm_dqs_pos[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0);
always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1);
always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2);
always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3);
always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4);
always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5);
always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6);
always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7);
always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8);
always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9);
always @(posedge dqs_in[10]) dqs_pos_timing_check(10);
always @(posedge dqs_in[11]) dqs_pos_timing_check(11);
always @(posedge dqs_in[12]) dqs_pos_timing_check(12);
always @(posedge dqs_in[13]) dqs_pos_timing_check(13);
always @(posedge dqs_in[14]) dqs_pos_timing_check(14);
always @(posedge dqs_in[15]) dqs_pos_timing_check(15);
always @(negedge dqs_in[16]) dqs_pos_timing_check(16);
always @(negedge dqs_in[17]) dqs_pos_timing_check(17);
always @(negedge dqs_in[18]) dqs_pos_timing_check(18);
always @(negedge dqs_in[19]) dqs_pos_timing_check(19);
always @(negedge dqs_in[20]) dqs_pos_timing_check(20);
always @(negedge dqs_in[21]) dqs_pos_timing_check(21);
always @(negedge dqs_in[22]) dqs_pos_timing_check(22);
always @(negedge dqs_in[23]) dqs_pos_timing_check(23);
always @(negedge dqs_in[24]) dqs_pos_timing_check(24);
always @(negedge dqs_in[25]) dqs_pos_timing_check(25);
always @(negedge dqs_in[26]) dqs_pos_timing_check(26);
always @(negedge dqs_in[27]) dqs_pos_timing_check(27);
always @(negedge dqs_in[28]) dqs_pos_timing_check(28);
always @(negedge dqs_in[29]) dqs_pos_timing_check(29);
always @(negedge dqs_in[30]) dqs_pos_timing_check(30);
always @(negedge dqs_in[31]) dqs_pos_timing_check(31);
task dqs_neg_timing_check;
input i;
reg [4:0] i;
reg [3:0] j;
begin
if (write_levelization && i<16) begin
if (ck_cntr - ck_load_mode < TWLDQSEN)
$display ("%m: at time %t ERROR: tWLDQSEN violation on DQS bit %d.", $time, i);
if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
$display ("%m: at time %t ERROR: tDQSH violation on DQS bit %d by %t", $time, i, tm_dqs_pos[i] + TDQSH*tck_avg - $time);
end
if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i]) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
$display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/16], i%16);
if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg))
$display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
if ($time - tm_dm[i%16] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%16] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[(i%16)*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%16)*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[(i%16)*`DQ_PER_DQS+j] <= 1'b1;
end
end
check_dm_tdipw[i%16] <= 1'b1;
tm_dqs[i%16] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
check_write_dqs_high[i] <= 1'b0;
tm_dqs_neg[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0);
always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1);
always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2);
always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3);
always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4);
always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5);
always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6);
always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7);
always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8);
always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9);
always @(negedge dqs_in[10]) dqs_neg_timing_check(10);
always @(negedge dqs_in[11]) dqs_neg_timing_check(11);
always @(negedge dqs_in[12]) dqs_neg_timing_check(12);
always @(negedge dqs_in[13]) dqs_neg_timing_check(13);
always @(negedge dqs_in[14]) dqs_neg_timing_check(14);
always @(negedge dqs_in[15]) dqs_neg_timing_check(15);
always @(posedge dqs_in[16]) dqs_neg_timing_check(16);
always @(posedge dqs_in[17]) dqs_neg_timing_check(17);
always @(posedge dqs_in[18]) dqs_neg_timing_check(18);
always @(posedge dqs_in[19]) dqs_neg_timing_check(19);
always @(posedge dqs_in[20]) dqs_neg_timing_check(20);
always @(posedge dqs_in[21]) dqs_neg_timing_check(21);
always @(posedge dqs_in[22]) dqs_neg_timing_check(22);
always @(posedge dqs_in[23]) dqs_neg_timing_check(23);
always @(posedge dqs_in[24]) dqs_neg_timing_check(24);
always @(posedge dqs_in[25]) dqs_neg_timing_check(25);
always @(posedge dqs_in[26]) dqs_neg_timing_check(26);
always @(posedge dqs_in[27]) dqs_neg_timing_check(27);
always @(posedge dqs_in[28]) dqs_neg_timing_check(28);
always @(posedge dqs_in[29]) dqs_neg_timing_check(29);
always @(posedge dqs_in[30]) dqs_neg_timing_check(30);
always @(posedge dqs_in[31]) dqs_neg_timing_check(31);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2B_BEHAVIORAL_V
`define SKY130_FD_SC_HS__NOR2B_BEHAVIORAL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor2b (
Y ,
A ,
B_N ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
// Local signals
wire Y not0_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y , not0_out, B_N );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2B_BEHAVIORAL_V |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Host Interface State Machine
// File : hif_sm.v
// Author : Frank Bruno
// Created : 29-DEC-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This state machine controls the interaction
// between host and VGA core. It monitors
// t_svga_sel, t_hrd_hwr_n, t_mem_io_n, ready signals
// from VGA core sub_modules and generates h_t_ready_n,
// h_iord, h_iowr and other related signals.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module hif_sm
(
input h_reset_n,
input t_svga_sel, // Valid address decoded
input h_hclk,
input a_ready_n, // IO cycle to attribute module is done
input c_ready_n, // IO cycle to crtc module is done
input g_ready_n, // IO cycle to graphics module is done
input m_ready_n, // IO cycle to memory module is done
input g_mem_ready_n, // mem cycle to memory module is done
input h_hrd_hwr_n, // 1 - read, 0 - write
input h_mem_io_n, // 1 - Mem, 0 - IO.
input m_cpurd_state1, // To reset svga_sel_ff (mem)
input g_cpult_state1, // To reset svga_sel_ff (graph)
input g_lt_hwr_cmd, // cpu_wr cycle sm is idle
output h_iord, // The current IO cycle is read
output h_iowr, // The current IO cycle is write
output h_t_ready_n, // Done, Ready for next cycle
output reg host_cycle,
output io_cycle,
output h_svga_sel,
output wrbus_io_cycle
);
parameter idle_s = 2'b00,
dxfer_s0 = 2'b01,
dxfer_s1 = 2'b10,
turn_ar_s = 2'b11;
reg [1:0] current_state_ff;
reg [1:0] next_state;
reg svga_sel_ff;
reg svga_sel_reset; // to reset svga_sel_ff
reg io_ready_n;
reg io_cycle_bus;
wire svga_sel_ff_din;
wire int_ready_n;
wire tmp_int_ready_n;
wire comb_ready_n;
wire mem_write;
reg [4:0] tmo_cnt;
wire timer_ready_n;
wire dummy_out_0;
assign tmp_int_ready_n = a_ready_n & c_ready_n & g_ready_n &
m_ready_n;
assign int_ready_n = tmp_int_ready_n & timer_ready_n;
always @(posedge h_hclk, negedge h_reset_n)
if(~h_reset_n) current_state_ff <= idle_s;
else current_state_ff <= next_state;
always @* begin
host_cycle = 1'b0;
io_ready_n = 1'b1;
svga_sel_reset = 1'b0;
io_cycle_bus = 1'b0;
case(current_state_ff) // synopsys parallel_case full_case
idle_s: begin
if(h_svga_sel & g_lt_hwr_cmd & (~h_mem_io_n) )
next_state = dxfer_s0;
else
next_state = idle_s;
end
dxfer_s0: begin
host_cycle = 1'b1;
io_cycle_bus = 1'b1;
svga_sel_reset = 1'b1;
if(~int_ready_n) next_state = dxfer_s1;
else next_state = dxfer_s0;
end
dxfer_s1: begin
host_cycle = 1'b1;
io_cycle_bus = 1'b1;
next_state = turn_ar_s;
end
turn_ar_s: begin
io_ready_n = 1'b0;
io_cycle_bus = 1'b1;
next_state = idle_s;
end
endcase
end
assign io_cycle = host_cycle & (~h_mem_io_n);
assign wrbus_io_cycle = io_cycle_bus & (~h_mem_io_n);
assign h_iord = io_cycle & h_hrd_hwr_n;
assign h_iowr = io_cycle & (~h_hrd_hwr_n);
assign comb_ready_n = io_ready_n & g_mem_ready_n;
assign mem_write = h_mem_io_n & (~h_hrd_hwr_n);
// Generating timer_ready_n signal incase ready_n is not coming from any
// of the modules. If ready_n does not get generated from any of the modules
// for 25 h_hclk's then timer_ready_n gets generated.
always @(posedge h_hclk, negedge h_reset_n)
if (!h_reset_n) tmo_cnt <= 5'b0;
else if (t_svga_sel) tmo_cnt <= 5'b0;
else tmo_cnt <= tmo_cnt + io_cycle;
assign timer_ready_n = ~(tmo_cnt == 5'h19);
assign h_t_ready_n = comb_ready_n;
assign svga_sel_ff_din = ( ((~(m_cpurd_state1 | g_cpult_state1 |
svga_sel_reset)) &
(svga_sel_ff)) ) | ( t_svga_sel );
// Latching t_svga_sel and converting level to pulse
always @(posedge h_hclk, negedge h_reset_n)
if(~h_reset_n) svga_sel_ff <= 1'b0;
else svga_sel_ff <= #1 svga_sel_ff_din;
assign h_svga_sel = svga_sel_ff | t_svga_sel;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_SYMBOL_V
/**
* lpflow_inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_inputiso0n (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_SYMBOL_V
|
/**************************************************************
date:2016/3/30
designer:ZhaiShaoMin
module name :tb_arbiter_for_IN_node
module function : check out errors about arbiter_for_IN_node
**************************************************************/
`timescale 1ns/1ps
module tb_arbiter_IN_node();
//input
reg clk;
reg rst;
reg in_req_rdy;
reg in_rep_rdy;
reg [1:0] req_ctrl_in;
reg [1:0] rep_ctrl_in;
reg [15:0] req_flit_in;
reg [15:0] rep_flit_in;
reg [1:0] ic_download_state_in;
reg [1:0] dc_download_state_in;
reg [1:0] mem_download_state_in;
//output
wire ack_req;
wire ack_rep;
wire v_ic;
wire [15:0] flit_ic;
wire [1:0] ctrl_ic;
wire v_dc;
wire [15:0] flit_dc;
wire [1:0] ctrl_dc;
wire v_mem;
wire [15:0] flit_mem;
wire [1:0] ctrl_mem;
//instante the design unit
arbiter_IN_node uut (//input
.clk(clk),
.rst(rst),
.in_req_rdy(in_req_rdy),
.in_rep_rdy(in_rep_rdy),
.req_ctrl_in(req_ctrl_in),
.rep_ctrl_in(rep_ctrl_in),
.req_flit_in(req_flit_in),
.rep_flit_in(rep_flit_in),
.ic_download_state_in(ic_download_state_in),
.dc_download_state_in(dc_download_state_in),
.mem_download_state_in(mem_download_state_in),
//output
.ack_req(ack_req),
.ack_rep(ack_rep),
.v_ic(v_ic),
.flit_ic(flit_ic),
.ctrl_ic(ctrl_ic),
.v_dc(v_dc),
.flit_dc(flit_dc),
.ctrl_dc(ctrl_dc),
.v_mem(v_mem),
.flit_mem(flit_mem),
.ctrl_mem(ctrl_mem)
);
integer log_file;
//initial inputs
initial
begin
clk=1'b0;
rst=1'b1;
in_req_rdy=1'b0;
in_rep_rdy=1'b0;
req_ctrl_in=2'b00;
rep_ctrl_in=2'b00;
req_flit_in=16'h0000;
rep_flit_in=16'h0000;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
log_file=$fopen("log_arbiter_IN_node");
end
`define clk_step #14;
always #7 clk=~clk;
/////////////////////////////////////////////////////////////////
/////////////BEGIN TEST!/////////////////////////////////////////
initial begin
`clk_step
$display("BEGIN TEST!");
$fdisplay(log_file,"BEGIN TEST!");
rst=1'b0;
/////////////////////////////////////////////////////////////
///////////first case : ic rep flit and dc req come////////
////first flit come anad both ic_download and dc_download are ready
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hc0de;
rep_flit_in=16'hc280;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
///second flits ,both ready
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b10;
req_flit_in=16'hc1de;
rep_flit_in=16'hc380;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b00;//mem_idle
///3rd flits ,both ready
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b10;
req_flit_in=16'hc2de;
rep_flit_in=16'hc480;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b00;//mem_idle
////after a while ,last flits both come
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b11;
rep_ctrl_in=2'b11;
req_flit_in=16'hc3de;
rep_flit_in=16'hc580;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b00;//mem_idle
///this time make ic busy for a moment
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hc0de;
rep_flit_in=16'hc280;
ic_download_state_in=2'b10;//ic_busy
dc_download_state_in=2'b00;
mem_download_state_in=2'b00;
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b01;
req_flit_in=16'hc1de;
rep_flit_in=16'hc280;
ic_download_state_in=2'b10;//ic_busy
dc_download_state_in=2'b01;
mem_download_state_in=2'b00;
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b01;
req_flit_in=16'hc2de;
rep_flit_in=16'hc280;
ic_download_state_in=2'b10;//ic_busy
dc_download_state_in=2'b01;
mem_download_state_in=2'b00;
////now ic_donwload is idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b11;
rep_ctrl_in=2'b01;
req_flit_in=16'hc3de;
rep_flit_in=16'hc280;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;
mem_download_state_in=2'b00;
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hc0df;
rep_flit_in=16'hc0de;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b10;//dc_rdy
mem_download_state_in=2'b00;
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hc0df;
rep_flit_in=16'hc1de;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b10;//dc_rdy
mem_download_state_in=2'b00;
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b11;
req_flit_in=16'hc0df;
rep_flit_in=16'hc2de;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b10;//dc_rdy
mem_download_state_in=2'b00;
`clk_step
////////////////////////////////////////////////////////////
////////////second case :ic rep flit and mem req come ///////
///both mem and ic idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hc280;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
///second flits ,both ready
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b10;
req_flit_in=16'h1234;
rep_flit_in=16'hc380;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b00;//mem_idle
///3rd flits ,both ready
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b10;
req_flit_in=16'habcd;
rep_flit_in=16'hc480;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b00;//mem_idle
////after a while ,last flits both come
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b11;
rep_ctrl_in=2'b11;
req_flit_in=16'hfed8;
rep_flit_in=16'hc580;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b00;//mem_idle
///this time make mem rdy for a moment
//first flit to ic and mem download is ready for mem now
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hc280;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b10;//mem_rdy
//second flit to ic and mem is still rdy for m_dl
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed0;
rep_flit_in=16'hc380;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b10;//mem_rdy
//third flit to ic and first flit to mem
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed0;
rep_flit_in=16'hc480;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
//4th to ic and 2nd to mem
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b10;
req_flit_in=16'h1234;
rep_flit_in=16'hc580;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
//last to ic and 7th to mem
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b11;
req_flit_in=16'habcd;
rep_flit_in=16'hc980;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
//no flit to ic and last to mem
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b11;
rep_ctrl_in=2'b00;
req_flit_in=16'h1357;
rep_flit_in=16'hc980;
ic_download_state_in=2'b10;//ic_rdy
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
////////////////////////////////////////////////////////////
///////////third case: only ic comes !//////////////////////
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b00;
rep_ctrl_in=2'b01;
req_flit_in=16'h1234;
rep_flit_in=16'hc280;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b00;
rep_ctrl_in=2'b10;
req_flit_in=16'h1234;
rep_flit_in=16'hc380;
ic_download_state_in=2'b01;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b00;
rep_ctrl_in=2'b10;
req_flit_in=16'h1234;
rep_flit_in=16'hc480;
ic_download_state_in=2'b01;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b00;
rep_ctrl_in=2'b11;
req_flit_in=16'h1234;
rep_flit_in=16'hc580;
ic_download_state_in=2'b01;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
////////////////////////////////////////////////////////////
///////////4th case: dc rep and mem req come////////////////
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hc0de;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed1;
rep_flit_in=16'hc1de;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed2;
rep_flit_in=16'hc2de;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed3;
rep_flit_in=16'hc3de;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b11;
req_flit_in=16'hfed4;
rep_flit_in=16'hc4de;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed5;
rep_flit_in=16'hc5de;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b10;//dc_rdy
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b11;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed4;
rep_flit_in=16'hc4de;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b10;//dc_rdy
mem_download_state_in=2'b01;//mem_busy
////////////////////////////////////////////////////////////
///////////5th case: mem rep and dc req come/////////////////
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hc0de;
rep_flit_in=16'hfed0;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b10;
req_flit_in=16'hc1de;
rep_flit_in=16'hfed1;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b10;
req_flit_in=16'hc2de;
rep_flit_in=16'hfed2;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b11;
rep_ctrl_in=2'b10;
req_flit_in=16'hc3de;
rep_flit_in=16'hfed3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b11;
req_flit_in=16'hc0de;
rep_flit_in=16'hfed4;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b10;//dc_rdy
mem_download_state_in=2'b01;//mem_busy
////////////////////////////////////////////////////////////
///////////6th case:dc rep and dc req come!/////////////////
// both come and dc rep win
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hc0de;
rep_flit_in=16'hc0ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hc0de;
rep_flit_in=16'hc1ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hc0de;
rep_flit_in=16'hc2ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b11;
req_flit_in=16'hc0de;
rep_flit_in=16'hc3ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
`clk_step
`clk_step
`clk_step
/////////////////////////////
//it's turn of dc req////////
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hc0de;
rep_flit_in=16'hc3ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b01;
req_flit_in=16'hc1de;
rep_flit_in=16'hc3ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b01;
req_flit_in=16'hc2de;
rep_flit_in=16'hc3ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b11;
rep_ctrl_in=2'b01;
req_flit_in=16'hc2de;
rep_flit_in=16'hc4ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
//next cycle dc_rdy
////////////////////////////////////////////////////////////
///////////7th case:mem rep and mem req come////////////////
// both come and mem rep win
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb0;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb1;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb2;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b11;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
`clk_step
`clk_step
`clk_step
/////////////////////////////
//it's turn of dc req////////
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed1;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed2;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_idle
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b11;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed3;
rep_flit_in=16'hfeb0;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_busy
mem_download_state_in=2'b01;//mem_busy
//mem will reject coming flit whatever kind
////////////////////////////////////////////////////////////
//////////8th case:only dc rep comes////////////////////////
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hc0de;
rep_flit_in=16'hc0ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hc0de;
rep_flit_in=16'hc1ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hc0de;
rep_flit_in=16'hc2ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b11;
req_flit_in=16'hc0de;
rep_flit_in=16'hc3ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
////////////////////////////////////////////////////////////
///////////9th case:only dc req come////////////////////////
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hc0de;
rep_flit_in=16'hc0ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hc0de;
rep_flit_in=16'hc1ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hc0de;
rep_flit_in=16'hc2ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b11;
req_flit_in=16'hc0de;
rep_flit_in=16'hc3ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
////////////////////////////////////////////////////////////
///////////10th case:only mem rep comes/////////////////////
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb0;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb1;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb2;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b11;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
////////////////////////////////////////////////////////////
////////////11th case: only mem req comes //////////////////
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb0;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb1;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb2;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b11;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
////////////////////////////////////////////////////////////
/////////////12th case: nothing comes///////////////////////
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb0;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb1;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb2;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b11;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
`clk_step
$display("FINISH TEST!");
$fdisplay(log_file,"FINISH TEST!");
$stop;
end
endmodule
|
// Copyright 2006,2007 Dennis van Weeren
//
// This file is part of Minimig
//
// Minimig is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License,or
// (at your option) any later version.
//
// Minimig is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not,see <http://www.gnu.org/licenses/>.
//
//
//
// This is the Blitter (part of the Agnus chip)
//
// 14-08-2005 -started coding
// 16-08-2005 -done more coding
// 19-08-2005 -added C source channel
// -added minterm function generator
// 21-08-2005 -added proper masking for A channel
// -added fill logic and D destination channel
// -added normal/line mode control logic
// -added address generator but it needs more work to reduce slices
// 23-08-2005 -done more work
// -added blitsize counter
// 24-08-2005 -done some cleanup
// 28-08-2005 -redesigned address generator module
// -started coding of main state machine
// 29-08-2005 -added blitter zero detect
// -added logic for special line mode to channel D
// 31-08-2005 -blitsize is now decremented automatically during channel D cycle
// -added delayed version for lwt called lwtd (needed for pipelining)
// 04-09-2005 -added state machine for normal blitter mode
// -added data output gate in channel D (needed for integration into Agnus)
// 05-09-2005 -fixed bug in bltaddress module
// -modified state machine start of blit handling
// 06-09-2005 -restored state machine,we should now have a working blitter (normal mode)
// -fixed bug,channel B preload didn't work
// 14-09-2005 -fixed bug in channel A masking logic when doing 1 word wide blits
// (and subsequently found another error in the Hardware Reference Manual)
// 18-09-2005 -added sign bit handling for line mode
// -redesigned address pointer ALU
// -adapted state machine to use new style ALU codes
// -added experimental line mode for octant 0,3,4,7
// 19-09-2005 -fixed bugs in line mode state machine and it begins to start working..
// 20-09-2005 -testing
// 25-09-2005 -complete redesign of controller logic
// -added new linemode logic for all octants
// 27-09-2005 -fixed problem in linemode with dma/channel D modulo: it seems like the real blitter
// uses only C modulo for channel C and D during linemode,same for USEC/USED
// -sign is taken from bit 15 of pointer A,NOT bit 20! -->fixed
// -line drawing in octant 0,3,4,7 now works!
// 28-09-2005 -line drawing in octant 1,2,5,6 now works too!
// 02-10-2005 -special line draw mode added (single bit per horizontal line)
// this completes the blitter (but some bugs may still remain...)
// 17-10-2005 -fixed typo in sensitivity list of always block
// 22-01-2006 -fixed bug in special line draw mode
// 25-01-2006 -added bblck signal
// 14-02-2006 -improved bblck table
// 07-07-2006 -added some comments
// ----------
// JB:
// 2008-03-03 - added BLTCON0L, BLTSIZH and BLTSIZV
// 2008-07-08 - clean up
// 2008-10-20 - changed name of horbeam[0] to bltena
// 2009-05-24 - clean-up & renaming
// 2009-05-29 - changed enable signal to be more cycle exact
// - removed bblck as not needed anymore
// - there is still incopatibility when C channel is selected without D: extra idle cycle is inserted
// 2009-12-15 - fixed channel B data flow
// 2009-12-19 - ECS extensions available only with ECS chipset selected
module agnus_blitter
(
input clk, // bus clock
input clk7_en,
input reset, // reset
input ecs, // enable ECS extensions
input clkena, // enables blitter operation (used to slow it down)
input enadma, // no other dma channel is granted the bus
output reqdma, // blitter requests dma cycle
input ackdma, // agnus dma priority logic grants dma cycle
output we, // write enable (blitter writes to memory)
output reg zero, // blitter zero status
output reg busy, // blitter busy status
output int3, // blitter finish interrupt request
input [15:0] data_in, // bus data in
output [15:0] data_out, // bus data out
input [8:1] reg_address_in, // register address inputs
output [20:1] address_out, // chip address outputs
output reg [8:1] reg_address_out // register address outputs
);
//register names and adresses
parameter BLTCON0 = 9'h040;
parameter BLTCON0L = 9'h05A;
parameter BLTCON1 = 9'h042;
parameter BLTAFWM = 9'h044;
parameter BLTALWM = 9'h046;
parameter BLTADAT = 9'h074;
parameter BLTBDAT = 9'h072;
parameter BLTCDAT = 9'h070;
parameter BLTDDAT = 9'h000;
parameter BLTSIZE = 9'h058;
parameter BLTSIZH = 9'h05E;
parameter BLTSIZV = 9'h05C;
//channel select codes
parameter CHA = 2'b10; // channel A
parameter CHB = 2'b01; // channel B
parameter CHC = 2'b00; // channel C
parameter CHD = 2'b11; // channel D
parameter BLT_IDLE = 5'b00000;
parameter BLT_INIT = 5'b00001;
parameter BLT_A = 5'b01001;
parameter BLT_B = 5'b01011;
parameter BLT_C = 5'b01010;
parameter BLT_D = 5'b01000;
parameter BLT_E = 5'b01100;
parameter BLT_F = 5'b00100;
parameter BLT_L1 = 5'b11001;
parameter BLT_L2 = 5'b11011;
parameter BLT_L3 = 5'b11010;
parameter BLT_L4 = 5'b11000;
//local signals
reg [15:0] bltcon0; // blitter control register 0
wire [3:0] ash; // bltcon0 aliases
wire usea;
wire useb;
wire usec;
wire used;
reg enad; // do not disable D channel
reg [15:0] bltcon1; // blitter control register 1
wire [3:0] bsh; // bltcon1 aliases
wire desc; // enable descending mode (and not line mode)
wire line; // enable line mode
wire ife; // enable inclusive fill mode
wire efe; // enable exclusive fill mode
reg [15:0] bltafwm; // blitter first word mask for source A
reg [15:0] bltalwm; // blitter last word mask for source A
reg [15:0] bltadat; // blitter source A data register
reg [15:0] bltbdat; // blitter source B data register
reg [15:0] bltcdat; // blitter source C data register
reg [15:0] bltaold; // blitter source A 'old' data
reg [15:0] bltbold; // blitter source B 'old' data
reg [15:0] bltahold; // A holding register
reg [15:0] bltbhold; // B holding register
reg [15:0] bltdhold; // D holding register
reg [10:0] width; // blitsize number of words (width)
reg [14:0] height; // blitsize number of lines (height)
reg [4:0] blt_state; // blitter state
reg [4:0] blt_next; // blitter next state
wire enable; // blit cycle enable signal
reg [1:0] chsel; // channel selection - affects register bus address during DMA transactions
reg [1:0] ptrsel; // pointer selection - DMA memory bus address
reg [1:0] modsel; // modulo selection (blitter is a little bit weird in line mode0
reg enaptr; // enable selected pointer
reg incptr; // increment selected pointer
reg decptr; // decrement selected pointer
reg addmod; // add selected modulo
reg submod; // substract selected modulo
wire incash; // increment ASH (line mode)
wire decash; // decrement ASH (line mode)
wire decbsh; // decrement BSH (line mode)
wire sign_out; // new accumulator sign calculated by address generator (line mode)
reg sign; // current sign of accumulator (line mode)
reg sign_del;
reg first_pixel; // first pixel in a horizontal segment (used in one-dot line mode)
reg first_line_pixel; // first pixel of line (use D pointer)
reg start; // busy delayed by one blitter cycle (for cycle exact compatibility)
wire init; // blitter initialization cycle
wire next_word; // indicates last cycle of a single sequence
reg store_result; // updates D hold register
reg pipeline_full; // indicated update of D holding register
wire first_word; // first word of a line
reg first_word_del; // delayed signal for use in fill mode (initial fill carry selection)
wire last_word; // last word of a line
reg last_word_del; // delayed signal for adding modulo to D channel pointer register
wire last_line; // last line of the blit
wire done; // indicates the end of the blit (clears busy)
wire [15:0] minterm_out; // minterm generator output
wire [15:0] fill_out; // fill logic output
wire fci; // fill carry in
wire fco; // fill carry out
reg fcy; // fill carry latch (for the next word)
reg [10:0] width_cnt; // blitter width counter (in words)
wire width_cnt_dec; // decrement width counter
wire width_cnt_rld; // reload width counter
reg [14:0] height_cnt; // blitter height counter (in lines)
reg [15:0] bltamask;
wire [15:0] shiftaout;
wire [15:0] shiftbout;
reg dma_req;
wire dma_ack;
//--------------------------------------------------------------------------------------
//bltcon0: ASH part
always @(posedge clk)
if (clk7_en) begin
if (reset)
bltcon0[15:12] <= 0;
else if (enable && incash) // increment ash (line mode)
bltcon0[15:12] <= bltcon0[15:12] + 4'b0001;
else if (enable && decash) // decrement ash (line mode)
bltcon0[15:12] <= bltcon0[15:12] - 4'b0001;
else if (reg_address_in[8:1]==BLTCON0[8:1])
bltcon0[15:12] <= data_in[15:12];
end
assign ash[3:0] = bltcon0[15:12];
//bltcon0: USE part
always @(posedge clk)
if (clk7_en) begin
if (reset)
bltcon0[11:8] <= 0;
else if (reg_address_in[8:1]==BLTCON0[8:1])
bltcon0[11:8] <= data_in[11:8];
end
// writing blitcon0 while a blit is active disables D channel (not always but it's very likely)
always @(posedge clk)
if (clk7_en) begin
if (init)
enad <= 1'b1;
else if (reg_address_in[8:1]==BLTCON0[8:1] && busy)
enad <= 1'b0;
end
assign {usea, useb, usec, used} = {bltcon0[11:9], bltcon0[8] & enad}; // DMA channels enable
//bltcon0: LF part
always @(posedge clk)
if (clk7_en) begin
if (reset)
bltcon0[7:0] <= 0;
else if (reg_address_in[8:1]==BLTCON0[8:1] || reg_address_in[8:1]==BLTCON0L[8:1] && ecs)
bltcon0[7:0] <= data_in[7:0];
end
//bltcon1: BSH part
always @(posedge clk)
if (clk7_en) begin
if (reset)
bltcon1[15:12] <= 0;
else if (enable && decbsh) // decrement bsh (line mode - texturing)
bltcon1[15:12] <= bltcon1[15:12] - 4'b0001;
else if (reg_address_in[8:1]==BLTCON1[8:1])
bltcon1[15:12] <= data_in[15:12];
end
assign bsh[3:0] = bltcon1[15:12];
//bltcon1: the rest
always @(posedge clk)
if (clk7_en) begin
if (reset)
bltcon1[11:0] <= 0;
else if (reg_address_in[8:1]==BLTCON1[8:1])
bltcon1[11:0] <= data_in[11:0];
end
assign line = bltcon1[0]; // line mode
assign desc = ~line & bltcon1[1]; // descending blit mode
assign efe = ~line & bltcon1[4]; // exclusive fill mode
assign ife = ~line & bltcon1[3]; // inclusive fill mode
//--------------------------------------------------------------------------------------
//bltafwm register (first word mask for channel A)
always @(posedge clk)
if (clk7_en) begin
if (reset)
bltafwm[15:0] <= 0;
else if (reg_address_in[8:1]==BLTAFWM[8:1])
bltafwm[15:0] <= data_in[15:0];
end
//bltalwm register (last word mask for channel A)
always @(posedge clk)
if (clk7_en) begin
if (reset)
bltalwm[15:0] <= 0;
else if (reg_address_in[8:1]==BLTALWM[8:1])
bltalwm[15:0] <= data_in[15:0];
end
//channel A mask select
always @(*)
if (first_word && last_word)
bltamask[15:0] = bltafwm[15:0] & bltalwm[15:0];
else if (first_word)
bltamask[15:0] = bltafwm[15:0];
else if (last_word)
bltamask[15:0] = bltalwm[15:0];
else
bltamask[15:0] = 16'hFF_FF;
//bltadat register
always @(posedge clk)
if (clk7_en) begin
if (reset)
bltadat[15:0] <= 0;
else if (reg_address_in[8:1]==BLTADAT[8:1])
bltadat[15:0] <= data_in[15:0];
end
//channel A 'old' register
always @(posedge clk)
if (clk7_en) begin
if (enable)
if (init)
bltaold[15:0] <= 0;
else if (next_word && !line) // in line mode this register is equal zero all the time
bltaold[15:0] <= bltadat[15:0] & bltamask[15:0];
end
//channel A barrel shifter
agnus_blitter_barrelshifter barrel_shifter_A
(
.desc(desc),
.shift(ash),
.new_val(bltadat & bltamask),
.old_val(bltaold),
.out(shiftaout)
);
//channel A holding register
always @(posedge clk)
if (clk7_en) begin
if (enable)
bltahold[15:0] <= shiftaout[15:0];
end
//--------------------------------------------------------------------------------------
//bltbdat register
always @(posedge clk)
if (clk7_en) begin
if (reset)
bltbdat[15:0] <= 0;
else if (reg_address_in[8:1]==BLTBDAT[8:1])
bltbdat[15:0] <= data_in[15:0];
end
reg bltbold_init;
always @(posedge clk)
if (clk7_en) begin
if (reset || done)
bltbold_init <= 1'b1;
else if (reg_address_in[8:1]==BLTBDAT[8:1])
bltbold_init <= 1'b0;
end
//channel B 'old' register
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1]==BLTBDAT[8:1])
if (bltbold_init)
bltbold[15:0] <= 0;
else
bltbold[15:0] <= bltbdat[15:0];
end
reg bltbdat_wrtn;
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1]==BLTBDAT[8:1])
bltbdat_wrtn <= 1'b1;
else
bltbdat_wrtn <= 1'b0;
end
//channel B barrel shifter
agnus_blitter_barrelshifter barrel_shifter_B
(
.desc(desc),
.shift(bsh),
.new_val(bltbdat),
.old_val(bltbold),
.out(shiftbout)
);
//channel B holding register
always @(posedge clk)
if (clk7_en) begin
if (line)
bltbhold[15:0] <= {16{shiftbout[0]}}; // in line mode only one selected bit of BLTBDAT register (LSB) is used for texturing
else if (bltbdat_wrtn)
bltbhold[15:0] <= shiftbout[15:0];
end
//--------------------------------------------------------------------------------------
//bltcdat register
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1]==BLTCDAT[8:1])
bltcdat[15:0] <= data_in[15:0];
end
//--------------------------------------------------------------------------------------
always @(posedge clk)
if (clk7_en) begin
if (next_word && enable)
last_word_del <= last_word;
end
always @(posedge clk)
if (clk7_en) begin
if (next_word && enable)
first_word_del <= first_word; // used in fill mode for selecting initial fci state
end
//--------------------------------------------------------------------------------------
//minterm generator instantation
agnus_blitter_minterm bltmt1
(
.lf(bltcon0[7:0]),
.ain(bltahold[15:0]),
.bin(bltbhold[15:0]),
.cin(bltcdat[15:0]),
.out(minterm_out[15:0])
);
//fill logic instantiation
agnus_blitter_fill bltfl1
(
.ife(ife),
.efe(efe),
.fci(fci),
.fco(fco),
.in(minterm_out[15:0]),
.out(fill_out[15:0])
);
//fill carry input
assign fci = first_word_del ? bltcon1[2] : fcy;
// carry out latch (updated at the same time as channel D holding register)
always @(posedge clk)
if (clk7_en) begin
if (store_result)
fcy <= fco;
end
// channel D holding register (updated one cycle later after a write to other holding registers)
always @(posedge clk)
if (clk7_en) begin
if (store_result)
bltdhold[15:0] <= fill_out[15:0];
end
// channel D 'zero' flag
always @(posedge clk)
if (clk7_en) begin
if (reset)
zero <= 1;
else if (enable && init)
zero <= 1;
else if (store_result && |fill_out[15:0])
zero <= 0;
end
//channel D data output
assign data_out[15:0] = ackdma && chsel[1:0]==CHD ? bltdhold[15:0] : 16'h00_00;
assign we = ackdma && chsel[1:0]==CHD ? 1'b1 : 1'b0;
//--------------------------------------------------------------------------------------
// 'busy' flag control
always @(posedge clk)
if (clk7_en) begin
if (reset)
busy <= 0;
else if (reg_address_in[8:1]==BLTSIZE[8:1] || reg_address_in[8:1]==BLTSIZH[8:1] && ecs) // set immediately after a write to BLTSIZE or BLTSIZH (ECS)
busy <= 1;
else if (done) // cleared when the blit is done
busy <= 0;
end
// blitter finish interrupt request
assign int3 = done;
// FSM start control (one bus clock cycle delay for cycle exact compatibility)
always @(posedge clk)
if (clk7_en) begin
if (reset || done)
start <= 0;
else if (clkena && busy)
start <= 1;
end
// blit width register (backup)
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1]==BLTSIZE[8:1]) // OCS
width[10:0] <= {4'b0000, ~|data_in[5:0], data_in[5:0]};
else if (reg_address_in[8:1]==BLTSIZH[8:1] && ecs) // ECS
width[10:0] <= data_in[10:0];
end
assign width_cnt_dec = enable & next_word;
assign width_cnt_rld = enable & next_word & last_word | init & enable;
// blit width counter
always @(posedge clk)
if (clk7_en) begin
if (width_cnt_rld) // reload counter
width_cnt[10:0] <= width[10:0];
else if (width_cnt_dec) // decrement counter
width_cnt[10:0] <= width_cnt[10:0] - 1'b1;
end
assign last_word = width_cnt[10:0]==1 ? 1'b1 : 1'b0;
assign first_word = width_cnt[10:0]==width[10:0] ? 1'b1 : 1'b0;
assign last_line = height_cnt[14:0]==1 ? 1'b1 : 1'b0;
// ECS large blit height holding register
always @(posedge clk)
if (clk7_en) begin
if (reset)
height[14:0] <= 0;
else if (reg_address_in[8:1]==BLTSIZV[8:1]) // ECS BLTSIZV register
height[14:0] <= data_in[14:0];
end
// blit height counter
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1]==BLTSIZE[8:1]) // OCS
height_cnt[14:0] <= {4'b0000, ~|data_in[15:6], data_in[15:6]};
else if (reg_address_in[8:1]==BLTSIZH[8:1] && ecs) // ECS
height_cnt[14:0] <= height[14:0];
else if (enable && next_word && last_word) // decrement height counter
height_cnt[14:0] <= height_cnt[14:0] - 1'b1;
end
// pipeline is full (first set of sources has been fetched)
always @(posedge clk)
if (clk7_en) begin
if (enable)
if (init)
pipeline_full <= 0;
else if (next_word)
pipeline_full <= 1;
end
//--------------------------------------------------------------------------------------
// instantiate address generation unit
agnus_blitter_adrgen address_generator_1
(
.clk(clk),
.clk7_en(clk7_en),
.reset(reset),
.first_line_pixel(line && first_line_pixel),
.ptrsel(ptrsel),
.modsel(modsel),
.enaptr(enaptr),
.incptr(incptr),
.decptr(decptr),
.addmod(addmod),
.submod(submod),
.sign_out(sign_out),
.data_in(data_in),
.reg_address_in(reg_address_in),
.address_out(address_out)
);
// custom register address output
always @(*)
case (chsel)
CHA : reg_address_out = BLTADAT[8:1];
CHB : reg_address_out = BLTBDAT[8:1];
CHC : reg_address_out = BLTCDAT[8:1];
CHD : reg_address_out = BLTDDAT[8:1];
endcase
//--------------------------------------------------------------------------------------
assign enable = enadma & clkena;
assign reqdma = dma_req & enable;
assign dma_ack = ackdma;
// blitter FSM
always @(posedge clk)
if (clk7_en) begin
if (reset)
blt_state <= BLT_IDLE;
else
blt_state <= blt_next;
end
always @(*)
case (blt_state)
BLT_IDLE:
begin
chsel = 2'bXX;
ptrsel = 2'bXX;
modsel = 2'bXX;
enaptr = 1'b0;
incptr = 1'bX;
decptr = 1'bX;
addmod = 1'bX;
submod = 1'bX;
dma_req = 1'b0;
if (enable)
if (start)
blt_next = BLT_INIT;
else
blt_next = BLT_IDLE;
else
blt_next = BLT_IDLE;
end
BLT_INIT:
begin
chsel = 2'bXX;
ptrsel = 2'bXX;
modsel = 2'bXX;
enaptr = 1'b0;
incptr = 1'bX;
decptr = 1'bX;
addmod = 1'bX;
submod = 1'bX;
dma_req = 1'b0;
if (enable)
if (line)
blt_next = BLT_L1; // go to first line draw cycle
else
blt_next = BLT_A;
else
blt_next = BLT_INIT;
end
BLT_A: // first blit cycle (channel A source data fetch or empty cycle)
begin
chsel = CHA;
ptrsel = CHA;
modsel = CHA;
enaptr = dma_ack;
incptr = ~desc;
decptr = desc;
addmod = ~desc & last_word; // add or substract modulo when last word in a line is fetched
submod = desc & last_word;
dma_req = usea; // empty cycle if channel A is not enabled
if (enable)
if (useb)
blt_next = BLT_B;
else if (usec || ife || efe) // in fill modes channel C cycle is always used (might be empty if channel C is not enabled)
blt_next = BLT_C;
else
blt_next = BLT_D;
else
blt_next = BLT_A;
end
BLT_B: // second blit cycle (always channel B fetch - if channel B is not enabled this cycle is skipped)
begin
chsel = CHB;
ptrsel = CHB;
modsel = CHB;
enaptr = dma_ack;
incptr = ~desc;
decptr = desc;
addmod = ~desc & last_word;
submod = desc & last_word;
dma_req = 1'b1; // we can only reach this state if channel B is enabled (USEB is set)
if (enable)
if (usec || ife || efe) // in fill modes channel C cycle is always used (might be empty if channel C is not enabled)
blt_next = BLT_C;
else
blt_next = BLT_D;
else
blt_next = BLT_B;
end
BLT_C:
begin
chsel = CHC;
ptrsel = CHC;
modsel = CHC;
enaptr = dma_ack;
incptr = ~desc;
decptr = desc;
addmod = ~desc & last_word;
submod = desc & last_word;
dma_req = usec; // channel C is enabled when USEC is set - in fill mode empty cycle if not enabled
if (enable)
if (used)
blt_next = BLT_D;
else if (last_word && last_line)
blt_next = BLT_IDLE;
else
blt_next = BLT_A;
else
blt_next = BLT_C;
end
BLT_D:
begin
chsel = CHD;
ptrsel = CHD;
modsel = CHD;
enaptr = dma_ack;
incptr = ~desc;
decptr = desc;
addmod = ~desc & last_word_del;
submod = desc & last_word_del;
dma_req = used & pipeline_full; // request DMA cycle if channel D holding register is full
if (enable)
if (last_word && last_line)
if (used)
blt_next = BLT_E; // if last data store cycle go to the first pipeline flush state
else
blt_next = BLT_IDLE; // if D channel is not used go to IDLE state
else
blt_next = BLT_A;
else
blt_next = BLT_D;
end
BLT_E: // empty cycle to allow data propagation through D hold register
begin
chsel = 2'bXX;
ptrsel = 2'bXX;
modsel = 2'bXX;
enaptr = 1'b0;
incptr = 1'bX;
decptr = 1'bX;
addmod = 1'bX;
submod = 1'bX;
dma_req = 1'b0;
if (clkena)
blt_next = BLT_F; // go to the last D hold register store cycle
else
blt_next = BLT_E;
end
BLT_F: // flush pipeline (store the last D hold register value)
begin
chsel = CHD;
ptrsel = CHD;
modsel = CHD;
enaptr = dma_ack;
incptr = ~desc;
decptr = desc;
addmod = ~desc & last_word_del;
submod = desc & last_word_del;
dma_req = 1'b1; // request DMA cycle (D holding register is full)
if (enable)
blt_next = BLT_IDLE; // it's the last cycle so go to IDLE state
else
blt_next = BLT_F;
end
BLT_L1: // update error accumulator
begin
chsel = CHA;
ptrsel = CHA;
modsel = sign ? CHB : CHA;
enaptr = enable;
incptr = 0;
decptr = 0;
addmod = 1;//pipeline_full; // update error accumulator
submod = 0;
dma_req = 0; // internal cycle - no DMA access
if (enable)
blt_next = BLT_L2;
else
blt_next = BLT_L1;
end
BLT_L2: // fetch source data from channel C
begin
chsel = CHC;
ptrsel = CHC;
modsel = CHC;
enaptr = enable; // no pointer increment
incptr = 0;
decptr = 0;
addmod = 0;
submod = 0;
dma_req = usec;
if (enable)
blt_next = BLT_L3;
else
blt_next = BLT_L2;
end
BLT_L3: // free cycle (data propagates from source holding registers to channel D hold register - no pipelining)
begin
chsel = CHA;
ptrsel = CHA;
modsel = CHA;
enaptr = 0;
incptr = 0;
decptr = 0;
addmod = 0;
submod = 0;
dma_req = 0;
if (enable)
blt_next = BLT_L4;
else
blt_next = BLT_L3;
end
BLT_L4: // store cycle - initial write @ D ptr, all succesive @ C ptr, always modulo C used
begin
chsel = CHD;
ptrsel = CHC;
modsel = CHC;
enaptr = enable;
incptr = (bltcon1[4] && !bltcon1[2] || !bltcon1[4] && !bltcon1[3] && !sign_del) && ash==4'b1111 ? 1'b1 : 1'b0;
decptr = (bltcon1[4] && bltcon1[2] || !bltcon1[4] && bltcon1[3] && !sign_del) && ash==4'b0000 ? 1'b1 : 1'b0;
addmod = !bltcon1[4] && !bltcon1[2] || bltcon1[4] && !bltcon1[3] && !sign_del ? 1'b1 : 1'b0;
submod = !bltcon1[4] && bltcon1[2] || bltcon1[4] && bltcon1[3] && !sign_del ? 1'b1 : 1'b0;
// in 'one dot' mode this might be a free bus cycle
dma_req = usec & (~bltcon1[1] | ~bltcon1[4] | first_pixel); // request DMA cycle
if (enable)
if (last_line) // if last data store go to idle state
blt_next = BLT_IDLE;
else
blt_next = BLT_L1;
else
blt_next = BLT_L4;
end
default:
begin
chsel = CHA;
ptrsel = 2'bXX;
modsel = 2'bXX;
enaptr = 0;
incptr = 0;
decptr = 0;
addmod = 0;
submod = 0;
dma_req = 0;
blt_next = BLT_IDLE;
end
endcase
// init blitter pipeline (reload height counter)
assign init = blt_state==BLT_INIT ? 1'b1 : 1'b0;
// indicates last cycle of a single sequence
assign next_word = blt_state==BLT_C && !used || blt_state==BLT_D || blt_state==BLT_L2 || blt_state==BLT_L4 ? 1'b1 : 1'b0;
// stores a new value to D hold register
always @(posedge clk)
if (clk7_en) begin
if (reset)
store_result <= 0;
else
store_result <= enable && next_word;
end
// blitter busy flag is cleared immediately after last source data is fetched (if D channel is not enabled) or the last but one result is stored
// signal 'done' is used to clear the 'busy' and 'start' flags
//assign done = (blt_state==BLT_C && !used || blt_state==BLT_D) && last_word && last_line || blt_state==BLT_L4 && last_line ? enable : 1'b0;
// This is temporary solution. Needs further investigation. With heavy display load and 060 CPU an ISR could run before the last pipelined data write.
assign done = (blt_state==BLT_C || blt_state==BLT_D) && !used && last_word && last_line || blt_state==BLT_F || blt_state==BLT_L4 && last_line ? enable : 1'b0;
always @(posedge clk)
if (clk7_en) begin
if (enable)
if (blt_state==BLT_INIT)
first_pixel <= 1'b1;
else if (blt_state==BLT_L4)
first_pixel <= ~sign_del;
end
always @ (posedge clk) begin
if (clk7_en) begin
if (reset) begin
first_line_pixel <= #1 1'b0;
end else if (enable) begin
if (blt_state == BLT_INIT)
first_line_pixel <= #1 1'b1;
else if (blt_state == BLT_L4)
first_line_pixel <= #1 1'b0;
end
end
end
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1]==BLTCON1[8:1])
sign <= data_in[6]; // initial sign value
else if (enable && blt_state==BLT_L1)
sign <= sign_out; // latch sign output from error accumulator
end
always @(posedge clk)
if (clk7_en) begin
if (enable && blt_state==BLT_L1)
sign_del <= sign;
end
assign incash = enable && blt_state==BLT_L4 && (bltcon1[4] && !bltcon1[2] || !bltcon1[4] && !bltcon1[3] && !sign_del) ? 1'b1 : 1'b0;
assign decash = enable && blt_state==BLT_L4 && (bltcon1[4] && bltcon1[2] || !bltcon1[4] && bltcon1[3] && !sign_del) ? 1'b1 : 1'b0;
assign decbsh = enable && blt_state==BLT_L4 ? 1'b1 : 1'b0;
//--------------------------------------------------------------------------------------
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//
// This file is part of Descrypt Ztex Bruteforcer
// Copyright (C) 2014 Alexey Osipov <giftsungiv3n at gmail dot com>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////
module pc2(
input [0:55] cd,
output [0:47] k
);
assign k = {cd[13], cd[16], cd[10], cd[23], cd[0], cd[4], cd[2], cd[27], cd[14], cd[5], cd[20], cd[9], cd[22], cd[18], cd[11], cd[3], cd[25], cd[7], cd[15], cd[6], cd[26], cd[19], cd[12], cd[1], cd[40], cd[51], cd[30], cd[36], cd[46], cd[54], cd[29], cd[39], cd[50], cd[44], cd[32], cd[47], cd[43], cd[48], cd[38], cd[55], cd[33], cd[52], cd[45], cd[41], cd[49], cd[35], cd[28], cd[31]};
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_t
//
// Generated
// by: wig
// on: Mon Oct 24 10:52:44 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_t.v,v 1.1 2005/10/25 13:15:36 wig Exp $
// $Date: 2005/10/25 13:15:36 $
// $Log: ent_t.v,v $
// Revision 1.1 2005/10/25 13:15:36 wig
// Testcase result update
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.62 2005/10/19 15:40:06 wig Exp
//
// Generator: mix_0.pl Revision: 1.38 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_t
//
// No `defines in this module
module ent_t
//
// Generated module inst_t
//
(
input wire sig_i_a,
input wire sig_i_a2,
input wire [6:0] sig_i_ae,
output wire sig_o_a,
output wire sig_o_a2,
output wire [7:0] sig_o_ae
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_01;
wire sig_03;
wire sig_04;
wire [3:0] sig_05;
wire [3:0] sig_06;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [4:0] sig_13;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_a
ent_a inst_a (
.p_mix_sig_01_go(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.p_mix_sig_03_go(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.p_mix_sig_04_gi(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.p_mix_sig_05_2_1_go(sig_05[2:1]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.p_mix_sig_06_gi(sig_06), // Conflicting definition (X2)
.p_mix_sig_i_ae_gi(sig_i_ae), // Input Bus
.p_mix_sig_o_ae_go(sig_o_ae), // Output Bus
.port_i_a(sig_i_a), // Input Port
.port_o_a(sig_o_a), // Output Port
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(sig_13), // Create internal signal name
.sig_i_a2(sig_i_a2), // Input Port
.sig_o_a2(sig_o_a2) // Output Port
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_b
ent_b inst_b (
.port_b_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_b_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_b_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_b_5_1(sig_05[2]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_b_5_2(sig_05[1]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_b_6i(sig_06), // Conflicting definition (X2)
.port_b_6o(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08) // VHDL intermediate needed (port name)
);
// End of Generated Instance Port Map for inst_b
endmodule
//
// End of Generated Module rtl of ent_t
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BAI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O21BAI_FUNCTIONAL_PP_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o21bai (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , b, or0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BAI_FUNCTIONAL_PP_V |
///////////////////////////////////////////////////////////////////////////////
/// Andrew Mattheisen
/// Zhiyang Ong
///
/// EE-577b 2007 fall
/// VITERBI DECODER
/// pmsm module (Path Metric State Memory)
///
/**
* @modified by Zhiyang Ong on November 1, 2007
* The reset values for the 2nd to the 4th
* registers are modified to achieve a unique solution,
* and avoid a set of equivalent paths for the solution.
* See subsequent comments in the code for further
* elaboration
*/
/// @modified by AJM - uncommented the change mentioned above
///////////////////////////////////////////////////////////////////////////////
module pmsm (npm0, npm1, npm2, npm3, pm0, pm1, pm2, pm3, clk, reset);
// outputs
output [3:0] pm0, pm1, pm2, pm3;
// inputs
input clk, reset;
input [3:0] npm0, npm1, npm2, npm3;
reg [3:0] pm0, pm1, pm2, pm3;
reg [3:0] npm0norm, npm1norm, npm2norm, npm3norm;
// Defining constants: parameter [name_of_constant] = value;
parameter saturating_value = 4'd15;
always @ (npm0 or npm1 or npm2 or npm3)
begin
if ((npm0 <= npm1)&&(npm0 <= npm2)&&(npm0 <= npm3))
begin
npm0norm <= 0;
npm1norm <= npm1-npm0;
npm2norm <= npm2-npm0;
npm3norm <= npm3-npm0;
end
else if ((npm1 <= npm0)&&(npm1 <= npm2)&&(npm1 <= npm3))
begin
npm0norm <= npm0-npm1;
npm1norm <= 0;
npm2norm <= npm2-npm1;
npm3norm <= npm3-npm1;
end
else if ((npm2 <= npm0)&&(npm2 <= npm1)&&(npm2 <= npm3))
begin
npm0norm <= npm0-npm2;
npm1norm <= npm1-npm2;
npm2norm <= 0;
npm3norm <= npm3-npm2;
end
else if ((npm3 <= npm0)&&(npm3 <= npm1)&&(npm3 <= npm2))
begin
npm0norm <= npm0-npm3;
npm1norm <= npm1-npm3;
npm2norm <= npm2-npm3;
npm3norm <= 0;
end
end // always @ (npm0 or npm1 or npm2 or npm3)
/**
* @modified by Zhiyang Ong, November 1, 2007
* Note that the first register is reset to zero,
* and the rest are reset to infinity, which is
* represented by the saturating value of 15
* = 2^n - 1 = 2^4 - 1.
*
* This prevents the solution from arriving at a
* set of false/incorrect set of equivalent
* paths in the Trellis diagram. Multiple paths
* with zero costs indicate no unique solution.
* Also, these infinite/saturated values will be
* "removed"/diminished in 2 clock cycles.
*/
always @ (posedge clk)
begin
if (reset)
begin
pm0 <= 4'd0;
pm1 <= saturating_value;
pm2 <= saturating_value;
pm3 <= saturating_value;
end
else
begin
pm0 <= npm0norm;
pm1 <= npm1norm;
pm2 <= npm2norm;
pm3 <= npm3norm;
end
end // always @ (posedge clk)
endmodule
|
// file: clk_200_400_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module clk_200_400_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 5.000*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_200_400_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
endmodule
|
//
// iverilog -DNO_DEBUG tb_top.v ...
//
//
`timescale 1ns/1ns
module tb_top;
reg clk, rst;
wire [31:0] addr;
wire write_en;
wire [31:0] wdata;
wire [31:0] rdata;
initial begin
clk <= 0;
rst <= 1;
#105
rst <= 0;
#1000
$finish;
end
always begin
#10 clk = ~clk;
end
`ifndef NO_DEBUG
// always @(posedge clk) begin
// $display("time %t, %d %d", $time, rst, dut.top_main_inst.cur_st);
// end
`endif
top dut(.clk(clk), .rst(rst)
`ifndef NO_MEMORY
,
.sram_addr(addr), .sram_wdata_en(write_en),
.sram_wdata(wdata), .sram_rdata(rdata)
`endif
);
`ifndef NO_MEMORY
mem16k mem(.clk_i(clk), .rst_i(rst),
.addr_i(addr[31:2]), .write_en_i(write_en),
.wdata_i(wdata), .rdata_o(rdata));
`endif
endmodule
// 1word = 4bytes
module mem16k(clk_i, rst_i, addr_i, write_en_i, wdata_i, rdata_o);
input clk_i, rst_i;
input [29:0] addr_i;
input write_en_i;
input [31:0] wdata_i;
output [31:0] rdata_o;
reg [31:0] storage[0:4095];
integer i;
initial begin
`ifndef NO_DEBUG
$display("mem16k init");
`endif
for (i = 0; i < 4096; i = i + 1) begin
storage[i] = 0;
end
end
always @(posedge clk_i) begin
if (rst_i) begin
end else begin
// $display("%t mem:read addr=%x,data=%x", $time, addr_i<<2, storage[addr_i[11:0]]);
if (write_en_i) begin
// $display("%t mem:write addr=%x,data=%x\n", $time, addr_i<<2, wdata_i);
storage[addr_i[11:0]] <= wdata_i;
end
end
end
assign rdata_o = storage[addr_i[11:0]];
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Thu Nov 3 18:10:39 2016
/////////////////////////////////////////////////////////////
module CORDIC_Arch3v1_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, add_subt_dataA, add_subt_dataB,
result_add_subt, op_add_subt, ready_add_subt, enab_cont_iter );
input [63:0] data_in;
input [1:0] shift_region_flag;
output [63:0] data_output;
output [63:0] add_subt_dataA;
output [63:0] add_subt_dataB;
input [63:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, op_add_subt, enab_cont_iter;
wire d_ff1_operation_out, d_ff3_sign_out, n1181, n1182, n1183, n1184,
n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204,
n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214,
n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224,
n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234,
n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244,
n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254,
n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264,
n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274,
n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284,
n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294,
n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304,
n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314,
n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324,
n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334,
n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344,
n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354,
n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364,
n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374,
n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384,
n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394,
n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404,
n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414,
n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424,
n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434,
n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444,
n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454,
n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464,
n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474,
n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484,
n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494,
n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504,
n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514,
n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524,
n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534,
n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544,
n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554,
n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564,
n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574,
n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584,
n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594,
n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604,
n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614,
n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624,
n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634,
n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644,
n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654,
n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664,
n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674,
n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684,
n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694,
n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704,
n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714,
n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724,
n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734,
n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744,
n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754,
n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764,
n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774,
n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784,
n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794,
n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804,
n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814,
n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824,
n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834,
n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844,
n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854,
n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864,
n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874,
n1875, n1876, n1877, n1878, n2009, n2010, n2011, n2012, n2013, n2014,
n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024,
n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2035,
n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045,
n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055,
n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065,
n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075,
n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085,
n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095,
n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105,
n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115,
n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125,
n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135,
n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145,
n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155,
n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165,
n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175,
n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185,
n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195,
n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205,
n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215,
n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225,
n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235,
n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245,
n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255,
n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265,
n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275,
n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285,
n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295,
n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305,
n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315,
n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325,
n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335,
n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345,
n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355,
n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365,
n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375,
n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385,
n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395,
n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405,
n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415,
n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425,
n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435,
n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445,
n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455,
n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465,
n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475,
n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485,
n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495,
n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505,
n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515,
n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525,
n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535,
n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545,
n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555,
n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565,
n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575,
n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585,
n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595,
n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605,
n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615,
n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625,
n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635,
n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645,
n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655,
n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665,
n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675,
n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685,
n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695,
n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705,
n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715,
n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725,
n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735,
n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745,
n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755,
n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765,
n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775,
n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785,
n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795,
n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805,
n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815,
n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825,
n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835,
n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845,
n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855,
n2856, n2857, n2858, n2859, n2860, n2861, n2862;
wire [3:0] cont_iter_out;
wire [1:0] cont_var_out;
wire [1:0] d_ff1_shift_region_flag_out;
wire [63:0] d_ff1_Z;
wire [63:0] d_ff_Xn;
wire [63:0] d_ff_Yn;
wire [63:0] d_ff_Zn;
wire [63:0] d_ff2_X;
wire [63:0] d_ff2_Y;
wire [63:0] d_ff2_Z;
wire [63:0] d_ff3_sh_x_out;
wire [63:0] d_ff3_sh_y_out;
wire [55:0] d_ff3_LUT_out;
wire [7:0] inst_CORDIC_FSM_v3_state_next;
wire [7:0] inst_CORDIC_FSM_v3_state_reg;
DFFRXLTS reg_LUT_Q_reg_53_ ( .D(n1505), .CK(n2833), .RN(n2747), .QN(n2715)
);
DFFRXLTS reg_LUT_Q_reg_45_ ( .D(n1509), .CK(n2859), .RN(n2747), .QN(n2714)
);
DFFRXLTS reg_LUT_Q_reg_41_ ( .D(n1512), .CK(n2835), .RN(n2748), .QN(n2713)
);
DFFRXLTS reg_LUT_Q_reg_22_ ( .D(n1527), .CK(n2832), .RN(n2749), .QN(n2712)
);
DFFRXLTS reg_LUT_Q_reg_20_ ( .D(n1529), .CK(n2839), .RN(n2749), .QN(n2711)
);
DFFRXLTS reg_LUT_Q_reg_35_ ( .D(n1515), .CK(n2830), .RN(n2748), .QN(n2710)
);
DFFRXLTS reg_LUT_Q_reg_31_ ( .D(n1519), .CK(n2840), .RN(n2748), .QN(n2709)
);
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n1525), .CK(n2838), .RN(n2749), .QN(n2708)
);
DFFRXLTS reg_LUT_Q_reg_16_ ( .D(n1533), .CK(n2830), .RN(n2750), .QN(n2707)
);
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n1537), .CK(n2826), .RN(n2750), .QN(n2706)
);
DFFRX1TS reg_val_muxY_2stage_Q_reg_52_ ( .D(n1332), .CK(n2849), .RN(n2728),
.Q(d_ff2_Y[52]), .QN(n2704) );
DFFRXLTS reg_LUT_Q_reg_50_ ( .D(n1507), .CK(n2836), .RN(n2747), .QN(n2703)
);
DFFRX1TS reg_shift_y_Q_reg_61_ ( .D(n1312), .CK(n2841), .RN(n2759), .QN(
n2702) );
DFFRX1TS reg_LUT_Q_reg_56_ ( .D(n1502), .CK(n2839), .RN(n2747), .QN(n2701)
);
DFFRX1TS reg_val_muxX_2stage_Q_reg_57_ ( .D(n1199), .CK(n2854), .RN(n2718),
.Q(d_ff2_X[57]), .QN(n2700) );
DFFRX1TS reg_LUT_Q_reg_32_ ( .D(n1518), .CK(n2829), .RN(n2748), .QN(n2699)
);
DFFRX1TS reg_LUT_Q_reg_4_ ( .D(n1545), .CK(n2820), .RN(n2751), .QN(n2698) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
inst_CORDIC_FSM_v3_state_next[7]), .CK(n2798), .RN(n2780), .Q(
inst_CORDIC_FSM_v3_state_reg[7]), .QN(n2697) );
DFFRX1TS reg_LUT_Q_reg_34_ ( .D(n1516), .CK(n2053), .RN(n2748), .QN(n2696)
);
DFFRX1TS reg_val_muxY_2stage_Q_reg_60_ ( .D(n1324), .CK(n2850), .RN(n2728),
.Q(d_ff2_Y[60]), .QN(n2695) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_58_ ( .D(n1326), .CK(n2850), .RN(n2728),
.Q(d_ff2_Y[58]), .QN(n2694) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_60_ ( .D(n1196), .CK(n2857), .RN(n2718),
.Q(d_ff2_X[60]), .QN(n2693) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_58_ ( .D(n1198), .CK(n2852), .RN(n2718),
.Q(d_ff2_X[58]), .QN(n2692) );
DFFRX1TS reg_LUT_Q_reg_28_ ( .D(n1521), .CK(n2832), .RN(n2749), .QN(n2691)
);
DFFRX1TS reg_val_muxX_2stage_Q_reg_52_ ( .D(n1204), .CK(n2049), .RN(n2782),
.QN(n2690) );
DFFRX2TS VAR_CONT_temp_reg_0_ ( .D(n1873), .CK(n2798), .RN(n2780), .Q(
cont_var_out[0]), .QN(n2689) );
DFFRX2TS reg_val_muxY_2stage_Q_reg_53_ ( .D(n1331), .CK(n2849), .RN(n2728),
.QN(n2688) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
inst_CORDIC_FSM_v3_state_next[6]), .CK(n2845), .RN(n2781), .Q(
inst_CORDIC_FSM_v3_state_reg[6]), .QN(n2685) );
DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(n1871), .CK(n2795), .RN(n2780), .Q(
d_ff1_shift_region_flag_out[0]), .QN(n2684) );
DFFRX2TS ITER_CONT_temp_reg_1_ ( .D(n1876), .CK(n2028), .RN(n2781), .Q(
cont_iter_out[1]), .QN(n2683) );
DFFRX1TS reg_shift_y_Q_reg_56_ ( .D(n1317), .CK(n2838), .RN(n2038), .QN(
n2682) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(n1870), .CK(n2795), .RN(n2719), .Q(
d_ff1_shift_region_flag_out[1]), .QN(n2681) );
DFFRX1TS reg_shift_x_Q_reg_56_ ( .D(n1189), .CK(n2831), .RN(n2792), .QN(
n2680) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n1613), .CK(n2811), .RN(n2762), .Q(
data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n1612), .CK(n2815), .RN(n2762), .Q(
data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n1611), .CK(n2815), .RN(n2762), .Q(
data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n1610), .CK(n2815), .RN(n2761), .Q(
data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n1609), .CK(n2815), .RN(n2761), .Q(
data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n1608), .CK(n2815), .RN(n2761), .Q(
data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n1607), .CK(n2820), .RN(n2761), .Q(
data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n1606), .CK(n2853), .RN(n2761), .Q(
data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n1605), .CK(n2024), .RN(n2760), .Q(
data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n1604), .CK(n2826), .RN(n2760), .Q(
data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n1602), .CK(n2817), .RN(n2760), .Q(
data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n1601), .CK(n2817), .RN(n2760), .Q(
data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n1600), .CK(n2817), .RN(n2719), .Q(
data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n1599), .CK(n2817), .RN(n2753), .Q(
data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n1598), .CK(n2817), .RN(n2038), .Q(
data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n1597), .CK(n2818), .RN(n2792), .Q(
data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n1596), .CK(n2818), .RN(n2790), .Q(
data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n1595), .CK(n2818), .RN(n2759), .Q(
data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n1594), .CK(n2818), .RN(n2038), .Q(
data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n1593), .CK(n2818), .RN(n2759), .Q(
data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n1592), .CK(n2819), .RN(n2038), .Q(
data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n1591), .CK(n2819), .RN(n2759), .Q(
data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n1590), .CK(n2819), .RN(n2758), .Q(
data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n1589), .CK(n2819), .RN(n2758), .Q(
data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n1588), .CK(n2819), .RN(n2758), .Q(
data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n1587), .CK(n2827), .RN(n2758), .Q(
data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n1586), .CK(n2828), .RN(n2758), .Q(
data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n1585), .CK(n2853), .RN(n2786), .Q(
data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n1584), .CK(n2820), .RN(n2037), .Q(
data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n1583), .CK(n2024), .RN(n2035), .Q(
data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n1582), .CK(n2814), .RN(n2786), .Q(
data_output[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_32_ ( .D(n1581), .CK(n2027), .RN(n2035), .Q(
data_output[32]) );
DFFRXLTS d_ff5_data_out_Q_reg_33_ ( .D(n1580), .CK(n2814), .RN(n2757), .Q(
data_output[33]) );
DFFRXLTS d_ff5_data_out_Q_reg_34_ ( .D(n1579), .CK(n2811), .RN(n2757), .Q(
data_output[34]) );
DFFRXLTS d_ff5_data_out_Q_reg_35_ ( .D(n1578), .CK(n2823), .RN(n2757), .Q(
data_output[35]) );
DFFRXLTS d_ff5_data_out_Q_reg_36_ ( .D(n1577), .CK(n2823), .RN(n2757), .Q(
data_output[36]) );
DFFRXLTS d_ff5_data_out_Q_reg_37_ ( .D(n1576), .CK(n2812), .RN(n2757), .Q(
data_output[37]) );
DFFRXLTS d_ff5_data_out_Q_reg_38_ ( .D(n1575), .CK(n2050), .RN(n2756), .Q(
data_output[38]) );
DFFRXLTS d_ff5_data_out_Q_reg_39_ ( .D(n1574), .CK(n2821), .RN(n2756), .Q(
data_output[39]) );
DFFRXLTS d_ff5_data_out_Q_reg_40_ ( .D(n1573), .CK(n2050), .RN(n2756), .Q(
data_output[40]) );
DFFRXLTS d_ff5_data_out_Q_reg_41_ ( .D(n1572), .CK(n2812), .RN(n2756), .Q(
data_output[41]) );
DFFRXLTS d_ff5_data_out_Q_reg_42_ ( .D(n1571), .CK(n2822), .RN(n2756), .Q(
data_output[42]) );
DFFRXLTS d_ff5_data_out_Q_reg_43_ ( .D(n1570), .CK(n2822), .RN(n2755), .Q(
data_output[43]) );
DFFRXLTS d_ff5_data_out_Q_reg_44_ ( .D(n1569), .CK(n2811), .RN(n2755), .Q(
data_output[44]) );
DFFRXLTS d_ff5_data_out_Q_reg_45_ ( .D(n1568), .CK(n2812), .RN(n2755), .Q(
data_output[45]) );
DFFRXLTS d_ff5_data_out_Q_reg_46_ ( .D(n1567), .CK(n2796), .RN(n2755), .Q(
data_output[46]) );
DFFRXLTS d_ff5_data_out_Q_reg_47_ ( .D(n1566), .CK(n2858), .RN(n2755), .Q(
data_output[47]) );
DFFRXLTS d_ff5_data_out_Q_reg_48_ ( .D(n1565), .CK(n2824), .RN(n2754), .Q(
data_output[48]) );
DFFRXLTS d_ff5_data_out_Q_reg_49_ ( .D(n1564), .CK(n2853), .RN(n2754), .Q(
data_output[49]) );
DFFRXLTS d_ff5_data_out_Q_reg_50_ ( .D(n1563), .CK(n2050), .RN(n2754), .Q(
data_output[50]) );
DFFRXLTS d_ff5_data_out_Q_reg_51_ ( .D(n1562), .CK(n2051), .RN(n2754), .Q(
data_output[51]) );
DFFRXLTS d_ff5_data_out_Q_reg_52_ ( .D(n1561), .CK(n2051), .RN(n2754), .Q(
data_output[52]) );
DFFRXLTS d_ff5_data_out_Q_reg_53_ ( .D(n1560), .CK(n2051), .RN(n2782), .Q(
data_output[53]) );
DFFRXLTS d_ff5_data_out_Q_reg_54_ ( .D(n1559), .CK(n2051), .RN(n2787), .Q(
data_output[54]) );
DFFRXLTS d_ff5_data_out_Q_reg_55_ ( .D(n1558), .CK(n2825), .RN(n2779), .Q(
data_output[55]) );
DFFRXLTS d_ff5_data_out_Q_reg_56_ ( .D(n1557), .CK(n2826), .RN(n2719), .Q(
data_output[56]) );
DFFRXLTS d_ff5_data_out_Q_reg_57_ ( .D(n1556), .CK(n2826), .RN(n2753), .Q(
data_output[57]) );
DFFRXLTS d_ff5_data_out_Q_reg_58_ ( .D(n1555), .CK(n2826), .RN(n2752), .Q(
data_output[58]) );
DFFRXLTS d_ff5_data_out_Q_reg_59_ ( .D(n1554), .CK(n2826), .RN(n2752), .Q(
data_output[59]) );
DFFRXLTS d_ff5_data_out_Q_reg_60_ ( .D(n1553), .CK(n2826), .RN(n2752), .Q(
data_output[60]) );
DFFRXLTS d_ff5_data_out_Q_reg_61_ ( .D(n1552), .CK(n2827), .RN(n2752), .Q(
data_output[61]) );
DFFRXLTS d_ff5_data_out_Q_reg_62_ ( .D(n1551), .CK(n2820), .RN(n2752), .Q(
data_output[62]) );
DFFRXLTS reg_shift_y_Q_reg_63_ ( .D(n1309), .CK(n2850), .RN(n2727), .Q(
d_ff3_sh_y_out[63]) );
DFFRXLTS reg_shift_x_Q_reg_63_ ( .D(n1181), .CK(n2858), .RN(n2718), .Q(
d_ff3_sh_x_out[63]) );
DFFRXLTS reg_shift_x_Q_reg_62_ ( .D(n1183), .CK(n2834), .RN(n2744), .Q(
d_ff3_sh_x_out[62]) );
DFFRXLTS reg_shift_y_Q_reg_62_ ( .D(n1311), .CK(n2835), .RN(n2744), .Q(
d_ff3_sh_y_out[62]) );
DFFRXLTS d_ff5_data_out_Q_reg_63_ ( .D(n1550), .CK(n2826), .RN(n2751), .Q(
data_output[63]) );
DFFRXLTS reg_LUT_Q_reg_52_ ( .D(n1506), .CK(n2831), .RN(n2747), .Q(
d_ff3_LUT_out[52]) );
DFFRXLTS reg_LUT_Q_reg_44_ ( .D(n1510), .CK(n2841), .RN(n2747), .Q(
d_ff3_LUT_out[44]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n1805), .CK(n2804), .RN(n2774), .Q(
d_ff_Zn[0]) );
DFFRXLTS reg_shift_y_Q_reg_54_ ( .D(n1319), .CK(n2829), .RN(n2745), .Q(
d_ff3_sh_y_out[54]) );
DFFRXLTS reg_shift_y_Q_reg_55_ ( .D(n1318), .CK(n2053), .RN(n2737), .Q(
d_ff3_sh_y_out[55]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n1435), .CK(n2829), .RN(n2738), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n1433), .CK(n2053), .RN(n2738), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n1431), .CK(n2839), .RN(n2744), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n1429), .CK(n2838), .RN(n2745), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n1425), .CK(n2030), .RN(n2792), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n1423), .CK(n2030), .RN(n2737), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n1421), .CK(n2030), .RN(n2736), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n1419), .CK(n2030), .RN(n2736), .Q(
d_ff3_sh_y_out[8]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n1417), .CK(n2030), .RN(n2736), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n1415), .CK(n2835), .RN(n2736), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n1413), .CK(n2836), .RN(n2736), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n1409), .CK(n2824), .RN(n2735), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n1407), .CK(n2047), .RN(n2735), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n1405), .CK(n2842), .RN(n2735), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n1401), .CK(n2842), .RN(n2746), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n1399), .CK(n2842), .RN(n2037), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n1397), .CK(n2842), .RN(n2791), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n1393), .CK(n2843), .RN(n2791), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(n1389), .CK(n2843), .RN(n2734), .Q(
d_ff3_sh_y_out[23]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n1385), .CK(n2844), .RN(n2734), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n1383), .CK(n2844), .RN(n2734), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n1381), .CK(n2844), .RN(n2733), .Q(
d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n1377), .CK(n2844), .RN(n2733), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_33_ ( .D(n1369), .CK(n2797), .RN(n2732), .Q(
d_ff3_sh_y_out[33]) );
DFFRXLTS reg_shift_y_Q_reg_37_ ( .D(n1361), .CK(n2797), .RN(n2731), .Q(
d_ff3_sh_y_out[37]) );
DFFRXLTS reg_shift_y_Q_reg_39_ ( .D(n1357), .CK(n2798), .RN(n2731), .Q(
d_ff3_sh_y_out[39]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n1804), .CK(n2801), .RN(n2774), .Q(
d_ff_Zn[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n1803), .CK(n2799), .RN(n2774), .Q(
d_ff_Zn[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n1802), .CK(n2801), .RN(n2774), .Q(
d_ff_Zn[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n1801), .CK(n2804), .RN(n2774), .Q(
d_ff_Zn[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n1800), .CK(n2025), .RN(n2773), .Q(
d_ff_Zn[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n1799), .CK(n2804), .RN(n2773), .Q(
d_ff_Zn[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n1798), .CK(n2799), .RN(n2773), .Q(
d_ff_Zn[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n1797), .CK(n2799), .RN(n2773), .Q(
d_ff_Zn[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n1796), .CK(n2801), .RN(n2773), .Q(
d_ff_Zn[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n1795), .CK(n2025), .RN(n2773), .Q(
d_ff_Zn[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n1794), .CK(n2804), .RN(n2773), .Q(
d_ff_Zn[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n1793), .CK(n2803), .RN(n2773), .Q(
d_ff_Zn[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n1792), .CK(n2800), .RN(n2773), .Q(
d_ff_Zn[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n1791), .CK(n2800), .RN(n2773), .Q(
d_ff_Zn[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n1790), .CK(n2025), .RN(n2772), .Q(
d_ff_Zn[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n1789), .CK(n2799), .RN(n2772), .Q(
d_ff_Zn[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n1788), .CK(n2803), .RN(n2772), .Q(
d_ff_Zn[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n1787), .CK(n2803), .RN(n2772), .Q(
d_ff_Zn[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n1786), .CK(n2800), .RN(n2772), .Q(
d_ff_Zn[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n1785), .CK(n2025), .RN(n2772), .Q(
d_ff_Zn[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n1784), .CK(n2803), .RN(n2772), .Q(
d_ff_Zn[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n1783), .CK(n2800), .RN(n2772), .Q(
d_ff_Zn[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n1782), .CK(n2800), .RN(n2772), .Q(
d_ff_Zn[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n1781), .CK(n2802), .RN(n2772), .Q(
d_ff_Zn[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n1780), .CK(n2025), .RN(n2771), .Q(
d_ff_Zn[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n1779), .CK(n2801), .RN(n2771), .Q(
d_ff_Zn[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n1778), .CK(n2803), .RN(n2771), .Q(
d_ff_Zn[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n1777), .CK(n2799), .RN(n2771), .Q(
d_ff_Zn[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n1776), .CK(n2802), .RN(n2771), .Q(
d_ff_Zn[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n1775), .CK(n2025), .RN(n2771), .Q(
d_ff_Zn[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n1774), .CK(n2807), .RN(n2771), .Q(
d_ff_Zn[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_32_ ( .D(n1773), .CK(n2808), .RN(n2771), .Q(
d_ff_Zn[32]) );
DFFRXLTS d_ff4_Zn_Q_reg_33_ ( .D(n1772), .CK(n2808), .RN(n2771), .Q(
d_ff_Zn[33]) );
DFFRXLTS d_ff4_Zn_Q_reg_34_ ( .D(n1771), .CK(n2809), .RN(n2771), .Q(
d_ff_Zn[34]) );
DFFRXLTS d_ff4_Zn_Q_reg_35_ ( .D(n1770), .CK(n2806), .RN(n2770), .Q(
d_ff_Zn[35]) );
DFFRXLTS d_ff4_Zn_Q_reg_36_ ( .D(n1769), .CK(n2808), .RN(n2770), .Q(
d_ff_Zn[36]) );
DFFRXLTS d_ff4_Zn_Q_reg_37_ ( .D(n1768), .CK(n2808), .RN(n2770), .Q(
d_ff_Zn[37]) );
DFFRXLTS d_ff4_Zn_Q_reg_38_ ( .D(n1767), .CK(n2806), .RN(n2770), .Q(
d_ff_Zn[38]) );
DFFRXLTS d_ff4_Zn_Q_reg_39_ ( .D(n1766), .CK(n2805), .RN(n2770), .Q(
d_ff_Zn[39]) );
DFFRXLTS d_ff4_Zn_Q_reg_40_ ( .D(n1765), .CK(n2807), .RN(n2770), .Q(
d_ff_Zn[40]) );
DFFRXLTS d_ff4_Zn_Q_reg_41_ ( .D(n1764), .CK(n2808), .RN(n2770), .Q(
d_ff_Zn[41]) );
DFFRXLTS d_ff4_Zn_Q_reg_42_ ( .D(n1763), .CK(n2805), .RN(n2770), .Q(
d_ff_Zn[42]) );
DFFRXLTS d_ff4_Zn_Q_reg_43_ ( .D(n1762), .CK(n2808), .RN(n2770), .Q(
d_ff_Zn[43]) );
DFFRXLTS d_ff4_Zn_Q_reg_44_ ( .D(n1761), .CK(n2807), .RN(n2770), .Q(
d_ff_Zn[44]) );
DFFRXLTS d_ff4_Zn_Q_reg_45_ ( .D(n1760), .CK(n2805), .RN(n2769), .Q(
d_ff_Zn[45]) );
DFFRXLTS d_ff4_Zn_Q_reg_46_ ( .D(n1759), .CK(n2026), .RN(n2769), .Q(
d_ff_Zn[46]) );
DFFRXLTS d_ff4_Zn_Q_reg_47_ ( .D(n1758), .CK(n2808), .RN(n2769), .Q(
d_ff_Zn[47]) );
DFFRXLTS d_ff4_Zn_Q_reg_48_ ( .D(n1757), .CK(n2808), .RN(n2769), .Q(
d_ff_Zn[48]) );
DFFRXLTS d_ff4_Zn_Q_reg_49_ ( .D(n1756), .CK(n2806), .RN(n2769), .Q(
d_ff_Zn[49]) );
DFFRXLTS d_ff4_Zn_Q_reg_50_ ( .D(n1755), .CK(n2809), .RN(n2769), .Q(
d_ff_Zn[50]) );
DFFRXLTS d_ff4_Zn_Q_reg_51_ ( .D(n1754), .CK(n2806), .RN(n2769), .Q(
d_ff_Zn[51]) );
DFFRXLTS d_ff4_Zn_Q_reg_52_ ( .D(n1753), .CK(n2807), .RN(n2769), .Q(
d_ff_Zn[52]) );
DFFRXLTS d_ff4_Zn_Q_reg_53_ ( .D(n1752), .CK(n2809), .RN(n2769), .Q(
d_ff_Zn[53]) );
DFFRXLTS d_ff4_Zn_Q_reg_54_ ( .D(n1751), .CK(n2805), .RN(n2769), .Q(
d_ff_Zn[54]) );
DFFRXLTS d_ff4_Zn_Q_reg_55_ ( .D(n1750), .CK(n2806), .RN(n2768), .Q(
d_ff_Zn[55]) );
DFFRXLTS d_ff4_Zn_Q_reg_56_ ( .D(n1749), .CK(n2807), .RN(n2768), .Q(
d_ff_Zn[56]) );
DFFRXLTS d_ff4_Zn_Q_reg_57_ ( .D(n1748), .CK(n2026), .RN(n2768), .Q(
d_ff_Zn[57]) );
DFFRXLTS d_ff4_Zn_Q_reg_58_ ( .D(n1747), .CK(n2026), .RN(n2768), .Q(
d_ff_Zn[58]) );
DFFRXLTS d_ff4_Zn_Q_reg_59_ ( .D(n1746), .CK(n2026), .RN(n2768), .Q(
d_ff_Zn[59]) );
DFFRXLTS d_ff4_Zn_Q_reg_60_ ( .D(n1745), .CK(n2026), .RN(n2768), .Q(
d_ff_Zn[60]) );
DFFRXLTS d_ff4_Zn_Q_reg_61_ ( .D(n1744), .CK(n2808), .RN(n2768), .Q(
d_ff_Zn[61]) );
DFFRXLTS d_ff4_Zn_Q_reg_62_ ( .D(n1743), .CK(n2809), .RN(n2768), .Q(
d_ff_Zn[62]) );
DFFRXLTS d_ff4_Zn_Q_reg_63_ ( .D(n1742), .CK(n2808), .RN(n2768), .Q(
d_ff_Zn[63]) );
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n1864), .CK(n2846), .RN(n2782), .Q(d_ff1_Z[5])
);
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n1863), .CK(n2794), .RN(n2787), .Q(d_ff1_Z[6])
);
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n1862), .CK(n2798), .RN(n2779), .Q(d_ff1_Z[7])
);
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n1861), .CK(n2846), .RN(n2719), .Q(d_ff1_Z[8])
);
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n1860), .CK(n2845), .RN(n2789), .Q(d_ff1_Z[9])
);
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n1859), .CK(n2845), .RN(n2753), .Q(
d_ff1_Z[10]) );
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n1858), .CK(n2794), .RN(n2789), .Q(
d_ff1_Z[11]) );
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n1857), .CK(n2798), .RN(n2790), .Q(
d_ff1_Z[12]) );
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n1856), .CK(n2846), .RN(n2789), .Q(
d_ff1_Z[13]) );
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n1855), .CK(n2845), .RN(n2782), .Q(
d_ff1_Z[14]) );
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n1854), .CK(n2028), .RN(n2035), .Q(
d_ff1_Z[15]) );
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n1853), .CK(n2845), .RN(n2789), .Q(
d_ff1_Z[16]) );
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n1852), .CK(n2794), .RN(n2787), .Q(
d_ff1_Z[17]) );
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n1851), .CK(n2794), .RN(n2035), .Q(
d_ff1_Z[18]) );
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n1850), .CK(n2797), .RN(n2778), .Q(
d_ff1_Z[19]) );
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n1849), .CK(n2028), .RN(n2778), .Q(
d_ff1_Z[20]) );
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n1848), .CK(n2794), .RN(n2778), .Q(
d_ff1_Z[21]) );
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n1847), .CK(n2798), .RN(n2778), .Q(
d_ff1_Z[22]) );
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n1846), .CK(n2798), .RN(n2778), .Q(
d_ff1_Z[23]) );
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n1845), .CK(n2797), .RN(n2778), .Q(
d_ff1_Z[24]) );
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n1844), .CK(n2028), .RN(n2778), .Q(
d_ff1_Z[25]) );
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n1843), .CK(n2798), .RN(n2778), .Q(
d_ff1_Z[26]) );
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n1842), .CK(n2845), .RN(n2778), .Q(
d_ff1_Z[27]) );
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n1841), .CK(n2845), .RN(n2778), .Q(
d_ff1_Z[28]) );
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n1840), .CK(n2797), .RN(n2777), .Q(
d_ff1_Z[29]) );
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n1839), .CK(n2028), .RN(n2777), .Q(
d_ff1_Z[30]) );
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n1838), .CK(n2846), .RN(n2777), .Q(
d_ff1_Z[31]) );
DFFRXLTS reg_Z0_Q_reg_32_ ( .D(n1837), .CK(n2028), .RN(n2777), .Q(
d_ff1_Z[32]) );
DFFRXLTS reg_Z0_Q_reg_33_ ( .D(n1836), .CK(n2846), .RN(n2777), .Q(
d_ff1_Z[33]) );
DFFRXLTS reg_Z0_Q_reg_34_ ( .D(n1835), .CK(n2797), .RN(n2777), .Q(
d_ff1_Z[34]) );
DFFRXLTS reg_Z0_Q_reg_35_ ( .D(n1834), .CK(n2799), .RN(n2777), .Q(
d_ff1_Z[35]) );
DFFRXLTS reg_Z0_Q_reg_36_ ( .D(n1833), .CK(n2803), .RN(n2777), .Q(
d_ff1_Z[36]) );
DFFRXLTS reg_Z0_Q_reg_37_ ( .D(n1832), .CK(n2804), .RN(n2777), .Q(
d_ff1_Z[37]) );
DFFRXLTS reg_Z0_Q_reg_38_ ( .D(n1831), .CK(n2801), .RN(n2777), .Q(
d_ff1_Z[38]) );
DFFRXLTS reg_Z0_Q_reg_39_ ( .D(n1830), .CK(n2799), .RN(n2776), .Q(
d_ff1_Z[39]) );
DFFRXLTS reg_Z0_Q_reg_40_ ( .D(n1829), .CK(n2803), .RN(n2776), .Q(
d_ff1_Z[40]) );
DFFRXLTS reg_Z0_Q_reg_41_ ( .D(n1828), .CK(n2804), .RN(n2776), .Q(
d_ff1_Z[41]) );
DFFRXLTS reg_Z0_Q_reg_42_ ( .D(n1827), .CK(n2801), .RN(n2776), .Q(
d_ff1_Z[42]) );
DFFRXLTS reg_Z0_Q_reg_43_ ( .D(n1826), .CK(n2799), .RN(n2776), .Q(
d_ff1_Z[43]) );
DFFRXLTS reg_Z0_Q_reg_44_ ( .D(n1825), .CK(n2803), .RN(n2776), .Q(
d_ff1_Z[44]) );
DFFRXLTS reg_Z0_Q_reg_45_ ( .D(n1824), .CK(n2803), .RN(n2776), .Q(
d_ff1_Z[45]) );
DFFRXLTS reg_Z0_Q_reg_46_ ( .D(n1823), .CK(n2801), .RN(n2776), .Q(
d_ff1_Z[46]) );
DFFRXLTS reg_Z0_Q_reg_47_ ( .D(n1822), .CK(n2801), .RN(n2776), .Q(
d_ff1_Z[47]) );
DFFRXLTS reg_Z0_Q_reg_48_ ( .D(n1821), .CK(n2799), .RN(n2776), .Q(
d_ff1_Z[48]) );
DFFRXLTS reg_Z0_Q_reg_49_ ( .D(n1820), .CK(n2025), .RN(n2775), .Q(
d_ff1_Z[49]) );
DFFRXLTS reg_Z0_Q_reg_50_ ( .D(n1819), .CK(n2799), .RN(n2775), .Q(
d_ff1_Z[50]) );
DFFRXLTS reg_Z0_Q_reg_51_ ( .D(n1818), .CK(n2804), .RN(n2775), .Q(
d_ff1_Z[51]) );
DFFRXLTS reg_Z0_Q_reg_52_ ( .D(n1817), .CK(n2804), .RN(n2775), .Q(
d_ff1_Z[52]) );
DFFRXLTS reg_Z0_Q_reg_53_ ( .D(n1816), .CK(n2802), .RN(n2775), .Q(
d_ff1_Z[53]) );
DFFRXLTS reg_Z0_Q_reg_54_ ( .D(n1815), .CK(n2025), .RN(n2775), .Q(
d_ff1_Z[54]) );
DFFRXLTS reg_Z0_Q_reg_55_ ( .D(n1814), .CK(n2801), .RN(n2775), .Q(
d_ff1_Z[55]) );
DFFRXLTS reg_Z0_Q_reg_56_ ( .D(n1813), .CK(n2804), .RN(n2775), .Q(
d_ff1_Z[56]) );
DFFRXLTS reg_Z0_Q_reg_57_ ( .D(n1812), .CK(n2802), .RN(n2775), .Q(
d_ff1_Z[57]) );
DFFRXLTS reg_Z0_Q_reg_58_ ( .D(n1811), .CK(n2025), .RN(n2775), .Q(
d_ff1_Z[58]) );
DFFRXLTS reg_Z0_Q_reg_59_ ( .D(n1810), .CK(n2801), .RN(n2774), .Q(
d_ff1_Z[59]) );
DFFRXLTS reg_Z0_Q_reg_60_ ( .D(n1809), .CK(n2804), .RN(n2774), .Q(
d_ff1_Z[60]) );
DFFRXLTS reg_Z0_Q_reg_61_ ( .D(n1808), .CK(n2803), .RN(n2774), .Q(
d_ff1_Z[61]) );
DFFRXLTS reg_Z0_Q_reg_62_ ( .D(n1807), .CK(n2802), .RN(n2774), .Q(
d_ff1_Z[62]) );
DFFRXLTS reg_Z0_Q_reg_63_ ( .D(n1806), .CK(n2025), .RN(n2774), .Q(
d_ff1_Z[63]) );
DFFRXLTS reg_shift_x_Q_reg_52_ ( .D(n1193), .CK(n2836), .RN(n2792), .Q(
d_ff3_sh_x_out[52]) );
DFFRXLTS reg_shift_x_Q_reg_54_ ( .D(n1191), .CK(n2047), .RN(n2737), .Q(
d_ff3_sh_x_out[54]) );
DFFRXLTS reg_shift_x_Q_reg_55_ ( .D(n1190), .CK(n2796), .RN(n2746), .Q(
d_ff3_sh_x_out[55]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n1305), .CK(n2857), .RN(n2727), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n1303), .CK(n2861), .RN(n2727), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n1301), .CK(n2852), .RN(n2726), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n1297), .CK(n2049), .RN(n2726), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n1295), .CK(n2855), .RN(n2726), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n1293), .CK(n2854), .RN(n2726), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n1291), .CK(n2857), .RN(n2792), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n1289), .CK(n2861), .RN(n2791), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n1287), .CK(n2861), .RN(n2786), .Q(
d_ff3_sh_x_out[10]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n1285), .CK(n2826), .RN(n2789), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n1279), .CK(n2853), .RN(n2725), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n1277), .CK(n2828), .RN(n2725), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n1273), .CK(n2851), .RN(n2725), .Q(
d_ff3_sh_x_out[17]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n1271), .CK(n2855), .RN(n2724), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n1269), .CK(n2854), .RN(n2724), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n1265), .CK(n2852), .RN(n2724), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(n1261), .CK(n2049), .RN(n2781), .Q(
d_ff3_sh_x_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n1257), .CK(n2851), .RN(n2792), .Q(
d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n1255), .CK(n2856), .RN(n2791), .Q(
d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n1253), .CK(n2856), .RN(n2786), .Q(
d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(n1249), .CK(n2856), .RN(n2723), .Q(
d_ff3_sh_x_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_33_ ( .D(n1241), .CK(n2851), .RN(n2722), .Q(
d_ff3_sh_x_out[33]) );
DFFRXLTS reg_shift_x_Q_reg_37_ ( .D(n1233), .CK(n2858), .RN(n2722), .Q(
d_ff3_sh_x_out[37]) );
DFFRXLTS reg_shift_x_Q_reg_39_ ( .D(n1229), .CK(n2858), .RN(n2721), .Q(
d_ff3_sh_x_out[39]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n1528), .CK(n2840), .RN(n2749), .Q(
d_ff3_LUT_out[21]) );
DFFRXLTS reg_shift_x_Q_reg_61_ ( .D(n1184), .CK(n2834), .RN(n2744), .Q(
d_ff3_sh_x_out[61]) );
DFFRXLTS reg_LUT_Q_reg_37_ ( .D(n1514), .CK(n2833), .RN(n2748), .Q(
d_ff3_LUT_out[37]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n1542), .CK(n2024), .RN(n2751), .Q(
d_ff3_LUT_out[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1494), .CK(n2841), .RN(n2745),
.Q(d_ff2_Z[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1491), .CK(n2833), .RN(n2743),
.Q(d_ff2_Z[10]) );
DFFRXLTS reg_shift_y_Q_reg_58_ ( .D(n1315), .CK(n2832), .RN(n2746), .Q(
d_ff3_sh_y_out[58]) );
DFFRXLTS reg_shift_y_Q_reg_60_ ( .D(n1313), .CK(n2831), .RN(n2744), .Q(
d_ff3_sh_y_out[60]) );
DFFRXLTS reg_shift_x_Q_reg_53_ ( .D(n1192), .CK(n2841), .RN(n2745), .Q(
d_ff3_sh_x_out[53]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n1427), .CK(n2832), .RN(n2746), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n1411), .CK(n2831), .RN(n2735), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n1403), .CK(n2842), .RN(n2735), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n1395), .CK(n2843), .RN(n2036), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n1391), .CK(n2843), .RN(n2734), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n1387), .CK(n2830), .RN(n2734), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n1379), .CK(n2844), .RN(n2733), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n1375), .CK(n2794), .RN(n2733), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n1373), .CK(n2846), .RN(n2733), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS reg_shift_y_Q_reg_32_ ( .D(n1371), .CK(n2028), .RN(n2732), .Q(
d_ff3_sh_y_out[32]) );
DFFRXLTS reg_shift_y_Q_reg_34_ ( .D(n1367), .CK(n2797), .RN(n2732), .Q(
d_ff3_sh_y_out[34]) );
DFFRXLTS reg_shift_y_Q_reg_35_ ( .D(n1365), .CK(n2846), .RN(n2732), .Q(
d_ff3_sh_y_out[35]) );
DFFRXLTS reg_shift_y_Q_reg_36_ ( .D(n1363), .CK(n2845), .RN(n2732), .Q(
d_ff3_sh_y_out[36]) );
DFFRXLTS reg_shift_y_Q_reg_38_ ( .D(n1359), .CK(n2797), .RN(n2731), .Q(
d_ff3_sh_y_out[38]) );
DFFRXLTS reg_shift_y_Q_reg_40_ ( .D(n1355), .CK(n2847), .RN(n2731), .Q(
d_ff3_sh_y_out[40]) );
DFFRXLTS reg_shift_y_Q_reg_41_ ( .D(n1353), .CK(n2847), .RN(n2731), .Q(
d_ff3_sh_y_out[41]) );
DFFRXLTS reg_shift_y_Q_reg_42_ ( .D(n1351), .CK(n2847), .RN(n2730), .Q(
d_ff3_sh_y_out[42]) );
DFFRXLTS reg_shift_y_Q_reg_43_ ( .D(n1349), .CK(n2847), .RN(n2730), .Q(
d_ff3_sh_y_out[43]) );
DFFRXLTS reg_shift_y_Q_reg_44_ ( .D(n1347), .CK(n2847), .RN(n2730), .Q(
d_ff3_sh_y_out[44]) );
DFFRXLTS reg_shift_y_Q_reg_45_ ( .D(n1345), .CK(n2848), .RN(n2730), .Q(
d_ff3_sh_y_out[45]) );
DFFRXLTS reg_shift_y_Q_reg_46_ ( .D(n1343), .CK(n2848), .RN(n2730), .Q(
d_ff3_sh_y_out[46]) );
DFFRXLTS reg_shift_y_Q_reg_47_ ( .D(n1341), .CK(n2848), .RN(n2729), .Q(
d_ff3_sh_y_out[47]) );
DFFRXLTS reg_shift_y_Q_reg_48_ ( .D(n1339), .CK(n2848), .RN(n2729), .Q(
d_ff3_sh_y_out[48]) );
DFFRXLTS reg_shift_y_Q_reg_49_ ( .D(n1337), .CK(n2848), .RN(n2729), .Q(
d_ff3_sh_y_out[49]) );
DFFRXLTS reg_shift_y_Q_reg_50_ ( .D(n1335), .CK(n2849), .RN(n2729), .Q(
d_ff3_sh_y_out[50]) );
DFFRXLTS reg_shift_y_Q_reg_51_ ( .D(n1333), .CK(n2849), .RN(n2729), .Q(
d_ff3_sh_y_out[51]) );
DFFRXLTS reg_shift_y_Q_reg_57_ ( .D(n1316), .CK(n2839), .RN(n2745), .Q(
d_ff3_sh_y_out[57]) );
DFFRXLTS reg_shift_y_Q_reg_59_ ( .D(n1314), .CK(n2833), .RN(n2737), .Q(
d_ff3_sh_y_out[59]) );
DFFRXLTS reg_shift_x_Q_reg_58_ ( .D(n1187), .CK(n2834), .RN(n2792), .Q(
d_ff3_sh_x_out[58]) );
DFFRXLTS reg_shift_x_Q_reg_60_ ( .D(n1185), .CK(n2834), .RN(n2737), .Q(
d_ff3_sh_x_out[60]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n1299), .CK(n2851), .RN(n2726), .Q(
d_ff3_sh_x_out[4]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n1283), .CK(n2828), .RN(n2790), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n1275), .CK(n2857), .RN(n2725), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n1267), .CK(n2861), .RN(n2724), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n1263), .CK(n2855), .RN(n2724), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n1259), .CK(n2854), .RN(n2789), .Q(
d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n1251), .CK(n2856), .RN(n2723), .Q(
d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n1247), .CK(n2856), .RN(n2723), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n1245), .CK(n2855), .RN(n2723), .Q(
d_ff3_sh_x_out[31]) );
DFFRXLTS reg_shift_x_Q_reg_32_ ( .D(n1243), .CK(n2854), .RN(n2723), .Q(
d_ff3_sh_x_out[32]) );
DFFRXLTS reg_shift_x_Q_reg_34_ ( .D(n1239), .CK(n2857), .RN(n2722), .Q(
d_ff3_sh_x_out[34]) );
DFFRXLTS reg_shift_x_Q_reg_35_ ( .D(n1237), .CK(n2861), .RN(n2722), .Q(
d_ff3_sh_x_out[35]) );
DFFRXLTS reg_shift_x_Q_reg_36_ ( .D(n1235), .CK(n2858), .RN(n2722), .Q(
d_ff3_sh_x_out[36]) );
DFFRXLTS reg_shift_x_Q_reg_38_ ( .D(n1231), .CK(n2858), .RN(n2721), .Q(
d_ff3_sh_x_out[38]) );
DFFRXLTS reg_shift_x_Q_reg_40_ ( .D(n1227), .CK(n2858), .RN(n2721), .Q(
d_ff3_sh_x_out[40]) );
DFFRXLTS reg_shift_x_Q_reg_41_ ( .D(n1225), .CK(n2031), .RN(n2721), .Q(
d_ff3_sh_x_out[41]) );
DFFRXLTS reg_shift_x_Q_reg_42_ ( .D(n1223), .CK(n2031), .RN(n2721), .Q(
d_ff3_sh_x_out[42]) );
DFFRXLTS reg_shift_x_Q_reg_43_ ( .D(n1221), .CK(n2031), .RN(n2720), .Q(
d_ff3_sh_x_out[43]) );
DFFRXLTS reg_shift_x_Q_reg_44_ ( .D(n1219), .CK(n2031), .RN(n2720), .Q(
d_ff3_sh_x_out[44]) );
DFFRXLTS reg_shift_x_Q_reg_45_ ( .D(n1217), .CK(n2031), .RN(n2720), .Q(
d_ff3_sh_x_out[45]) );
DFFRXLTS reg_shift_x_Q_reg_46_ ( .D(n1215), .CK(n2860), .RN(n2720), .Q(
d_ff3_sh_x_out[46]) );
DFFRXLTS reg_shift_x_Q_reg_47_ ( .D(n1213), .CK(n2860), .RN(n2720), .Q(
d_ff3_sh_x_out[47]) );
DFFRXLTS reg_shift_x_Q_reg_48_ ( .D(n1211), .CK(n2860), .RN(n2779), .Q(
d_ff3_sh_x_out[48]) );
DFFRXLTS reg_shift_x_Q_reg_49_ ( .D(n1209), .CK(n2860), .RN(n2719), .Q(
d_ff3_sh_x_out[49]) );
DFFRXLTS reg_shift_x_Q_reg_50_ ( .D(n1207), .CK(n2860), .RN(n2753), .Q(
d_ff3_sh_x_out[50]) );
DFFRXLTS reg_shift_x_Q_reg_51_ ( .D(n1205), .CK(n2852), .RN(n2790), .Q(
d_ff3_sh_x_out[51]) );
DFFRXLTS reg_shift_y_Q_reg_53_ ( .D(n1320), .CK(n2838), .RN(n2746), .Q(
d_ff3_sh_y_out[53]) );
DFFRXLTS reg_shift_x_Q_reg_57_ ( .D(n1188), .CK(n2833), .RN(n2746), .Q(
d_ff3_sh_x_out[57]) );
DFFRX1TS reg_LUT_Q_reg_8_ ( .D(n1541), .CK(n2853), .RN(n2751), .Q(
d_ff3_LUT_out[8]) );
DFFRX1TS reg_shift_y_Q_reg_52_ ( .D(n1321), .CK(n2830), .RN(n2747), .Q(
d_ff3_sh_y_out[52]) );
DFFRX1TS reg_LUT_Q_reg_1_ ( .D(n1548), .CK(n2827), .RN(n2751), .Q(
d_ff3_LUT_out[1]) );
DFFRX1TS reg_LUT_Q_reg_2_ ( .D(n1547), .CK(n2827), .RN(n2751), .Q(
d_ff3_LUT_out[2]) );
DFFRX1TS reg_LUT_Q_reg_3_ ( .D(n1546), .CK(n2827), .RN(n2751), .Q(
d_ff3_LUT_out[3]) );
DFFRX1TS reg_LUT_Q_reg_5_ ( .D(n1544), .CK(n2828), .RN(n2751), .Q(
d_ff3_LUT_out[5]) );
DFFRX1TS reg_LUT_Q_reg_6_ ( .D(n1543), .CK(n2816), .RN(n2751), .Q(
d_ff3_LUT_out[6]) );
DFFRX1TS reg_LUT_Q_reg_9_ ( .D(n1540), .CK(n2024), .RN(n2750), .Q(
d_ff3_LUT_out[9]) );
DFFRX1TS reg_LUT_Q_reg_11_ ( .D(n1538), .CK(n2816), .RN(n2750), .Q(
d_ff3_LUT_out[11]) );
DFFRX1TS reg_LUT_Q_reg_14_ ( .D(n1535), .CK(n2828), .RN(n2750), .Q(
d_ff3_LUT_out[14]) );
DFFRX1TS reg_LUT_Q_reg_15_ ( .D(n1534), .CK(n2053), .RN(n2750), .Q(
d_ff3_LUT_out[15]) );
DFFRX1TS reg_LUT_Q_reg_17_ ( .D(n1532), .CK(n2832), .RN(n2750), .Q(
d_ff3_LUT_out[17]) );
DFFRX1TS reg_LUT_Q_reg_18_ ( .D(n1531), .CK(n2839), .RN(n2750), .Q(
d_ff3_LUT_out[18]) );
DFFRX1TS reg_LUT_Q_reg_19_ ( .D(n1530), .CK(n2838), .RN(n2749), .Q(
d_ff3_LUT_out[19]) );
DFFRX1TS reg_LUT_Q_reg_23_ ( .D(n1526), .CK(n2830), .RN(n2749), .Q(
d_ff3_LUT_out[23]) );
DFFRX1TS reg_LUT_Q_reg_25_ ( .D(n1524), .CK(n2839), .RN(n2749), .Q(
d_ff3_LUT_out[25]) );
DFFRX1TS reg_LUT_Q_reg_27_ ( .D(n1522), .CK(n2838), .RN(n2749), .Q(
d_ff3_LUT_out[27]) );
DFFRX1TS reg_LUT_Q_reg_29_ ( .D(n1520), .CK(n2053), .RN(n2748), .Q(
d_ff3_LUT_out[29]) );
DFFRX1TS reg_LUT_Q_reg_33_ ( .D(n1517), .CK(n2053), .RN(n2748), .Q(
d_ff3_LUT_out[33]) );
DFFRX1TS reg_LUT_Q_reg_39_ ( .D(n1513), .CK(n2831), .RN(n2748), .Q(
d_ff3_LUT_out[39]) );
DFFRX1TS reg_LUT_Q_reg_54_ ( .D(n1504), .CK(n2840), .RN(n2747), .Q(
d_ff3_LUT_out[54]) );
DFFRX1TS reg_LUT_Q_reg_55_ ( .D(n1503), .CK(n2829), .RN(n2747), .Q(
d_ff3_LUT_out[55]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_52_ ( .D(n1449), .CK(n2838), .RN(n2739),
.Q(d_ff2_Z[52]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_53_ ( .D(n1448), .CK(n2830), .RN(n2739),
.Q(d_ff2_Z[53]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_56_ ( .D(n1445), .CK(n2830), .RN(n2739),
.Q(d_ff2_Z[56]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_57_ ( .D(n1444), .CK(n2840), .RN(n2739),
.Q(d_ff2_Z[57]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_58_ ( .D(n1443), .CK(n2829), .RN(n2739),
.Q(d_ff2_Z[58]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_60_ ( .D(n1441), .CK(n2839), .RN(n2738),
.Q(d_ff2_Z[60]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_61_ ( .D(n1440), .CK(n2838), .RN(n2738),
.Q(d_ff2_Z[61]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_62_ ( .D(n1439), .CK(n2830), .RN(n2738),
.Q(d_ff2_Z[62]) );
DFFRX1TS reg_LUT_Q_reg_42_ ( .D(n1511), .CK(n2047), .RN(n2748), .Q(
d_ff3_LUT_out[42]) );
DFFRX1TS d_ff4_Xn_Q_reg_62_ ( .D(n1615), .CK(n2827), .RN(n2752), .Q(
d_ff_Xn[62]) );
DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n1676), .CK(n2823), .RN(n2762), .Q(
d_ff_Xn[1]) );
DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n1675), .CK(n2815), .RN(n2762), .Q(
d_ff_Xn[2]) );
DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n1673), .CK(n2815), .RN(n2761), .Q(
d_ff_Xn[4]) );
DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n1672), .CK(n2815), .RN(n2761), .Q(
d_ff_Xn[5]) );
DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n1667), .CK(n2820), .RN(n2760), .Q(
d_ff_Xn[10]) );
DFFRX1TS d_ff4_Xn_Q_reg_12_ ( .D(n1665), .CK(n2817), .RN(n2760), .Q(
d_ff_Xn[12]) );
DFFRX1TS d_ff4_Xn_Q_reg_15_ ( .D(n1662), .CK(n2817), .RN(n2035), .Q(
d_ff_Xn[15]) );
DFFRX1TS d_ff4_Xn_Q_reg_16_ ( .D(n1661), .CK(n2817), .RN(n2779), .Q(
d_ff_Xn[16]) );
DFFRX1TS d_ff4_Xn_Q_reg_17_ ( .D(n1660), .CK(n2818), .RN(n2783), .Q(
d_ff_Xn[17]) );
DFFRX1TS d_ff4_Xn_Q_reg_18_ ( .D(n1659), .CK(n2818), .RN(n2759), .Q(
d_ff_Xn[18]) );
DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n1657), .CK(n2818), .RN(n2759), .Q(
d_ff_Xn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n1656), .CK(n2818), .RN(n2038), .Q(
d_ff_Xn[21]) );
DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n1655), .CK(n2819), .RN(n2759), .Q(
d_ff_Xn[22]) );
DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n1654), .CK(n2819), .RN(n2038), .Q(
d_ff_Xn[23]) );
DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n1652), .CK(n2819), .RN(n2758), .Q(
d_ff_Xn[25]) );
DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n1650), .CK(n2816), .RN(n2758), .Q(
d_ff_Xn[27]) );
DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n1647), .CK(n2816), .RN(n2786), .Q(
d_ff_Xn[30]) );
DFFRX1TS d_ff4_Xn_Q_reg_33_ ( .D(n1644), .CK(n2821), .RN(n2786), .Q(
d_ff_Xn[33]) );
DFFRX1TS d_ff4_Xn_Q_reg_37_ ( .D(n1640), .CK(n2823), .RN(n2757), .Q(
d_ff_Xn[37]) );
DFFRX1TS d_ff4_Xn_Q_reg_38_ ( .D(n1639), .CK(n2812), .RN(n2757), .Q(
d_ff_Xn[38]) );
DFFRX1TS d_ff4_Xn_Q_reg_40_ ( .D(n1637), .CK(n2811), .RN(n2756), .Q(
d_ff_Xn[40]) );
DFFRX1TS d_ff4_Xn_Q_reg_44_ ( .D(n1633), .CK(n2811), .RN(n2755), .Q(
d_ff_Xn[44]) );
DFFRX1TS d_ff4_Xn_Q_reg_47_ ( .D(n1630), .CK(n2828), .RN(n2755), .Q(
d_ff_Xn[47]) );
DFFRX1TS d_ff4_Xn_Q_reg_50_ ( .D(n1627), .CK(n2823), .RN(n2754), .Q(
d_ff_Xn[50]) );
DFFRX1TS d_ff4_Xn_Q_reg_51_ ( .D(n1626), .CK(n2800), .RN(n2754), .Q(
d_ff_Xn[51]) );
DFFRX1TS d_ff4_Yn_Q_reg_1_ ( .D(n1740), .CK(n2806), .RN(n2767), .Q(
d_ff_Yn[1]) );
DFFRX1TS d_ff4_Yn_Q_reg_2_ ( .D(n1739), .CK(n2809), .RN(n2767), .Q(
d_ff_Yn[2]) );
DFFRX1TS d_ff4_Yn_Q_reg_3_ ( .D(n1738), .CK(n2026), .RN(n2767), .Q(
d_ff_Yn[3]) );
DFFRX1TS d_ff4_Yn_Q_reg_4_ ( .D(n1737), .CK(n2806), .RN(n2767), .Q(
d_ff_Yn[4]) );
DFFRX1TS d_ff4_Yn_Q_reg_5_ ( .D(n1736), .CK(n2806), .RN(n2767), .Q(
d_ff_Yn[5]) );
DFFRX1TS d_ff4_Yn_Q_reg_6_ ( .D(n1735), .CK(n2805), .RN(n2767), .Q(
d_ff_Yn[6]) );
DFFRX1TS d_ff4_Yn_Q_reg_7_ ( .D(n1734), .CK(n2805), .RN(n2767), .Q(
d_ff_Yn[7]) );
DFFRX1TS d_ff4_Yn_Q_reg_8_ ( .D(n1733), .CK(n2809), .RN(n2767), .Q(
d_ff_Yn[8]) );
DFFRX1TS d_ff4_Yn_Q_reg_9_ ( .D(n1732), .CK(n2805), .RN(n2767), .Q(
d_ff_Yn[9]) );
DFFRX1TS d_ff4_Yn_Q_reg_10_ ( .D(n1731), .CK(n2809), .RN(n2767), .Q(
d_ff_Yn[10]) );
DFFRX1TS d_ff4_Yn_Q_reg_11_ ( .D(n1730), .CK(n2807), .RN(n2766), .Q(
d_ff_Yn[11]) );
DFFRX1TS d_ff4_Yn_Q_reg_12_ ( .D(n1729), .CK(n2809), .RN(n2766), .Q(
d_ff_Yn[12]) );
DFFRX1TS d_ff4_Yn_Q_reg_13_ ( .D(n1728), .CK(n2026), .RN(n2766), .Q(
d_ff_Yn[13]) );
DFFRX1TS d_ff4_Yn_Q_reg_14_ ( .D(n1727), .CK(n2026), .RN(n2766), .Q(
d_ff_Yn[14]) );
DFFRX1TS d_ff4_Yn_Q_reg_15_ ( .D(n1726), .CK(n2805), .RN(n2766), .Q(
d_ff_Yn[15]) );
DFFRX1TS d_ff4_Yn_Q_reg_16_ ( .D(n1725), .CK(n2809), .RN(n2766), .Q(
d_ff_Yn[16]) );
DFFRX1TS d_ff4_Yn_Q_reg_17_ ( .D(n1724), .CK(n2026), .RN(n2766), .Q(
d_ff_Yn[17]) );
DFFRX1TS d_ff4_Yn_Q_reg_18_ ( .D(n1723), .CK(n2806), .RN(n2766), .Q(
d_ff_Yn[18]) );
DFFRX1TS d_ff4_Yn_Q_reg_19_ ( .D(n1722), .CK(n2806), .RN(n2766), .Q(
d_ff_Yn[19]) );
DFFRX1TS d_ff4_Yn_Q_reg_20_ ( .D(n1721), .CK(n2809), .RN(n2766), .Q(
d_ff_Yn[20]) );
DFFRX1TS d_ff4_Yn_Q_reg_21_ ( .D(n1720), .CK(n2805), .RN(n2765), .Q(
d_ff_Yn[21]) );
DFFRX1TS d_ff4_Yn_Q_reg_22_ ( .D(n1719), .CK(n2807), .RN(n2765), .Q(
d_ff_Yn[22]) );
DFFRX1TS d_ff4_Yn_Q_reg_23_ ( .D(n1718), .CK(n2805), .RN(n2765), .Q(
d_ff_Yn[23]) );
DFFRX1TS d_ff4_Yn_Q_reg_24_ ( .D(n1717), .CK(n2807), .RN(n2765), .Q(
d_ff_Yn[24]) );
DFFRX1TS d_ff4_Yn_Q_reg_25_ ( .D(n1716), .CK(n2807), .RN(n2765), .Q(
d_ff_Yn[25]) );
DFFRX1TS d_ff4_Yn_Q_reg_26_ ( .D(n1715), .CK(n2026), .RN(n2765), .Q(
d_ff_Yn[26]) );
DFFRX1TS d_ff4_Yn_Q_reg_27_ ( .D(n1714), .CK(n2821), .RN(n2765), .Q(
d_ff_Yn[27]) );
DFFRX1TS d_ff4_Yn_Q_reg_28_ ( .D(n1713), .CK(n2821), .RN(n2765), .Q(
d_ff_Yn[28]) );
DFFRX1TS d_ff4_Yn_Q_reg_29_ ( .D(n1712), .CK(n2814), .RN(n2765), .Q(
d_ff_Yn[29]) );
DFFRX1TS d_ff4_Yn_Q_reg_30_ ( .D(n1711), .CK(n2027), .RN(n2765), .Q(
d_ff_Yn[30]) );
DFFRX1TS d_ff4_Yn_Q_reg_31_ ( .D(n1710), .CK(n2812), .RN(n2785), .Q(
d_ff_Yn[31]) );
DFFRX1TS d_ff4_Yn_Q_reg_32_ ( .D(n1709), .CK(n2027), .RN(n2784), .Q(
d_ff_Yn[32]) );
DFFRX1TS d_ff4_Yn_Q_reg_33_ ( .D(n1708), .CK(n2814), .RN(n2791), .Q(
d_ff_Yn[33]) );
DFFRX1TS d_ff4_Yn_Q_reg_34_ ( .D(n1707), .CK(n2050), .RN(n2785), .Q(
d_ff_Yn[34]) );
DFFRX1TS d_ff4_Yn_Q_reg_35_ ( .D(n1706), .CK(n2812), .RN(n2784), .Q(
d_ff_Yn[35]) );
DFFRX1TS d_ff4_Yn_Q_reg_36_ ( .D(n1705), .CK(n2027), .RN(n2038), .Q(
d_ff_Yn[36]) );
DFFRX1TS d_ff4_Yn_Q_reg_37_ ( .D(n1704), .CK(n2050), .RN(n2785), .Q(
d_ff_Yn[37]) );
DFFRX1TS d_ff4_Yn_Q_reg_38_ ( .D(n1703), .CK(n2821), .RN(n2784), .Q(
d_ff_Yn[38]) );
DFFRX1TS d_ff4_Yn_Q_reg_39_ ( .D(n1702), .CK(n2821), .RN(n2781), .Q(
d_ff_Yn[39]) );
DFFRX1TS d_ff4_Yn_Q_reg_40_ ( .D(n1701), .CK(n2821), .RN(n2785), .Q(
d_ff_Yn[40]) );
DFFRX1TS d_ff4_Yn_Q_reg_41_ ( .D(n1700), .CK(n2822), .RN(n2764), .Q(
d_ff_Yn[41]) );
DFFRX1TS d_ff4_Yn_Q_reg_42_ ( .D(n1699), .CK(n2814), .RN(n2764), .Q(
d_ff_Yn[42]) );
DFFRX1TS d_ff4_Yn_Q_reg_43_ ( .D(n1698), .CK(n2027), .RN(n2764), .Q(
d_ff_Yn[43]) );
DFFRX1TS d_ff4_Yn_Q_reg_44_ ( .D(n1697), .CK(n2823), .RN(n2764), .Q(
d_ff_Yn[44]) );
DFFRX1TS d_ff4_Yn_Q_reg_45_ ( .D(n1696), .CK(n2814), .RN(n2764), .Q(
d_ff_Yn[45]) );
DFFRX1TS d_ff4_Yn_Q_reg_46_ ( .D(n1695), .CK(n2027), .RN(n2764), .Q(
d_ff_Yn[46]) );
DFFRX1TS d_ff4_Yn_Q_reg_47_ ( .D(n1694), .CK(n2813), .RN(n2764), .Q(
d_ff_Yn[47]) );
DFFRX1TS d_ff4_Yn_Q_reg_48_ ( .D(n1693), .CK(n2813), .RN(n2764), .Q(
d_ff_Yn[48]) );
DFFRX1TS d_ff4_Yn_Q_reg_49_ ( .D(n1692), .CK(n2813), .RN(n2764), .Q(
d_ff_Yn[49]) );
DFFRX1TS d_ff4_Yn_Q_reg_50_ ( .D(n1691), .CK(n2813), .RN(n2764), .Q(
d_ff_Yn[50]) );
DFFRX1TS d_ff4_Yn_Q_reg_51_ ( .D(n1690), .CK(n2813), .RN(n2763), .Q(
d_ff_Yn[51]) );
DFFRX1TS d_ff4_Yn_Q_reg_54_ ( .D(n1687), .CK(n2813), .RN(n2763), .Q(
d_ff_Yn[54]) );
DFFRX1TS d_ff4_Yn_Q_reg_55_ ( .D(n1686), .CK(n2813), .RN(n2763), .Q(
d_ff_Yn[55]) );
DFFRX1TS d_ff4_Yn_Q_reg_56_ ( .D(n1685), .CK(n2813), .RN(n2763), .Q(
d_ff_Yn[56]) );
DFFRX1TS d_ff4_Yn_Q_reg_57_ ( .D(n1684), .CK(n2823), .RN(n2763), .Q(
d_ff_Yn[57]) );
DFFRX1TS d_ff4_Yn_Q_reg_59_ ( .D(n1682), .CK(n2027), .RN(n2763), .Q(
d_ff_Yn[59]) );
DFFRX1TS d_ff4_Yn_Q_reg_61_ ( .D(n1680), .CK(n2814), .RN(n2762), .Q(
d_ff_Yn[61]) );
DFFRX1TS d_ff4_Yn_Q_reg_62_ ( .D(n1679), .CK(n2050), .RN(n2762), .Q(
d_ff_Yn[62]) );
DFFRX1TS d_ff4_Xn_Q_reg_57_ ( .D(n1620), .CK(n2024), .RN(n2719), .Q(
d_ff_Xn[57]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n1306), .CK(n2850), .RN(n2727),
.Q(d_ff2_X[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n1304), .CK(n2861), .RN(n2727),
.Q(d_ff2_X[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n1300), .CK(n2049), .RN(n2726),
.Q(d_ff2_X[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_5_ ( .D(n1298), .CK(n2049), .RN(n2726),
.Q(d_ff2_X[5]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n1288), .CK(n2855), .RN(n2784),
.Q(d_ff2_X[10]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n1284), .CK(n2853), .RN(n2037),
.Q(d_ff2_X[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n1278), .CK(n2853), .RN(n2725),
.Q(d_ff2_X[15]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n1276), .CK(n2024), .RN(n2725),
.Q(d_ff2_X[16]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n1274), .CK(n2857), .RN(n2725),
.Q(d_ff2_X[17]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n1272), .CK(n2852), .RN(n2725),
.Q(d_ff2_X[18]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n1268), .CK(n2049), .RN(n2724),
.Q(d_ff2_X[20]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n1266), .CK(n2861), .RN(n2724),
.Q(d_ff2_X[21]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n1264), .CK(n2855), .RN(n2724),
.Q(d_ff2_X[22]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n1262), .CK(n2854), .RN(n2724),
.Q(d_ff2_X[23]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(n1258), .CK(n2857), .RN(n2790),
.Q(d_ff2_X[25]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n1254), .CK(n2856), .RN(n2784),
.Q(d_ff2_X[27]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n1248), .CK(n2856), .RN(n2723),
.Q(d_ff2_X[30]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_33_ ( .D(n1242), .CK(n2852), .RN(n2723),
.Q(d_ff2_X[33]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_37_ ( .D(n1234), .CK(n2862), .RN(n2722),
.Q(d_ff2_X[37]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_38_ ( .D(n1232), .CK(n2862), .RN(n2722),
.Q(d_ff2_X[38]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_40_ ( .D(n1228), .CK(n2862), .RN(n2721),
.Q(d_ff2_X[40]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_44_ ( .D(n1220), .CK(n2031), .RN(n2720),
.Q(d_ff2_X[44]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_47_ ( .D(n1214), .CK(n2860), .RN(n2720),
.Q(d_ff2_X[47]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_50_ ( .D(n1208), .CK(n2860), .RN(n2779),
.Q(d_ff2_X[50]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_51_ ( .D(n1206), .CK(n2860), .RN(n2719),
.Q(d_ff2_X[51]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_63_ ( .D(n1182), .CK(n2862), .RN(n2718),
.Q(d_ff2_X[63]) );
DFFRX1TS d_ff4_Yn_Q_reg_0_ ( .D(n1741), .CK(n2807), .RN(n2768), .Q(
d_ff_Yn[0]) );
DFFRX1TS reg_sign_Q_reg_0_ ( .D(n1437), .CK(n2840), .RN(n2738), .Q(
d_ff3_sign_out) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n1308), .CK(n2850), .RN(n2727),
.Q(d_ff2_X[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n1302), .CK(n2049), .RN(n2727),
.Q(d_ff2_X[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n1296), .CK(n2851), .RN(n2726),
.Q(d_ff2_X[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n1294), .CK(n2854), .RN(n2726),
.Q(d_ff2_X[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n1292), .CK(n2857), .RN(n2726),
.Q(d_ff2_X[8]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n1290), .CK(n2852), .RN(n2792),
.Q(d_ff2_X[9]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n1286), .CK(n2861), .RN(n2036),
.Q(d_ff2_X[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n1282), .CK(n2828), .RN(n2792),
.Q(d_ff2_X[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n1280), .CK(n2820), .RN(n2725),
.Q(d_ff2_X[14]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n1270), .CK(n2851), .RN(n2724),
.Q(d_ff2_X[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n1260), .CK(n2852), .RN(n2037),
.Q(d_ff2_X[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n1256), .CK(n2049), .RN(n2781),
.Q(d_ff2_X[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_28_ ( .D(n1252), .CK(n2856), .RN(n2036),
.Q(d_ff2_X[28]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n1250), .CK(n2856), .RN(n2723),
.Q(d_ff2_X[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n1246), .CK(n2856), .RN(n2723),
.Q(d_ff2_X[31]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_32_ ( .D(n1244), .CK(n2049), .RN(n2723),
.Q(d_ff2_X[32]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_34_ ( .D(n1240), .CK(n2861), .RN(n2722),
.Q(d_ff2_X[34]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_35_ ( .D(n1238), .CK(n2851), .RN(n2722),
.Q(d_ff2_X[35]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_36_ ( .D(n1236), .CK(n2855), .RN(n2722),
.Q(d_ff2_X[36]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_39_ ( .D(n1230), .CK(n2862), .RN(n2721),
.Q(d_ff2_X[39]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_41_ ( .D(n1226), .CK(n2858), .RN(n2721),
.Q(d_ff2_X[41]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_42_ ( .D(n1224), .CK(n2031), .RN(n2721),
.Q(d_ff2_X[42]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_43_ ( .D(n1222), .CK(n2031), .RN(n2721),
.Q(d_ff2_X[43]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_45_ ( .D(n1218), .CK(n2031), .RN(n2720),
.Q(d_ff2_X[45]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_46_ ( .D(n1216), .CK(n2031), .RN(n2720),
.Q(d_ff2_X[46]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_48_ ( .D(n1212), .CK(n2860), .RN(n2720),
.Q(d_ff2_X[48]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_49_ ( .D(n1210), .CK(n2860), .RN(n2753),
.Q(d_ff2_X[49]) );
DFFRX1TS d_ff4_Xn_Q_reg_52_ ( .D(n1625), .CK(n2051), .RN(n2754), .Q(
d_ff_Xn[52]) );
DFFRX1TS d_ff4_Yn_Q_reg_52_ ( .D(n1689), .CK(n2813), .RN(n2763), .Q(
d_ff_Yn[52]) );
DFFRX1TS d_ff4_Yn_Q_reg_53_ ( .D(n1688), .CK(n2813), .RN(n2763), .Q(
d_ff_Yn[53]) );
DFFRX1TS d_ff4_Yn_Q_reg_58_ ( .D(n1683), .CK(n2822), .RN(n2763), .Q(
d_ff_Yn[58]) );
DFFRX1TS d_ff4_Yn_Q_reg_60_ ( .D(n1681), .CK(n2811), .RN(n2763), .Q(
d_ff_Yn[60]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n1436), .CK(n2840), .RN(n2738),
.Q(d_ff2_Y[0]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n1434), .CK(n2829), .RN(n2738),
.Q(d_ff2_Y[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n1432), .CK(n2053), .RN(n2783),
.Q(d_ff2_Y[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n1430), .CK(n2832), .RN(n2783),
.Q(d_ff2_Y[3]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n1428), .CK(n2839), .RN(n2783),
.Q(d_ff2_Y[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n1426), .CK(n2030), .RN(n2783),
.Q(d_ff2_Y[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n1424), .CK(n2030), .RN(n2038),
.Q(d_ff2_Y[6]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n1422), .CK(n2030), .RN(n2736),
.Q(d_ff2_Y[7]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n1420), .CK(n2030), .RN(n2736),
.Q(d_ff2_Y[8]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n1418), .CK(n2030), .RN(n2736),
.Q(d_ff2_Y[9]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n1416), .CK(n2810), .RN(n2736),
.Q(d_ff2_Y[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n1414), .CK(n2835), .RN(n2736),
.Q(d_ff2_Y[11]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n1412), .CK(n2836), .RN(n2735),
.Q(d_ff2_Y[12]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n1410), .CK(n2841), .RN(n2735),
.Q(d_ff2_Y[13]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n1408), .CK(n2831), .RN(n2735),
.Q(d_ff2_Y[14]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n1406), .CK(n2842), .RN(n2735),
.Q(d_ff2_Y[15]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n1404), .CK(n2842), .RN(n2735),
.Q(d_ff2_Y[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n1402), .CK(n2842), .RN(n2791),
.Q(d_ff2_Y[17]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n1400), .CK(n2842), .RN(n2791),
.Q(d_ff2_Y[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n1398), .CK(n2842), .RN(n2744),
.Q(d_ff2_Y[19]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n1396), .CK(n2843), .RN(n2782),
.Q(d_ff2_Y[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n1394), .CK(n2843), .RN(n2745),
.Q(d_ff2_Y[21]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n1392), .CK(n2843), .RN(n2734),
.Q(d_ff2_Y[22]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n1390), .CK(n2843), .RN(n2734),
.Q(d_ff2_Y[23]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n1388), .CK(n2843), .RN(n2734),
.Q(d_ff2_Y[24]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n1386), .CK(n2844), .RN(n2734),
.Q(d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n1384), .CK(n2844), .RN(n2734),
.Q(d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n1382), .CK(n2844), .RN(n2733),
.Q(d_ff2_Y[27]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n1380), .CK(n2844), .RN(n2733),
.Q(d_ff2_Y[28]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n1378), .CK(n2844), .RN(n2733),
.Q(d_ff2_Y[29]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n1376), .CK(n2028), .RN(n2733),
.Q(d_ff2_Y[30]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n1374), .CK(n2794), .RN(n2733),
.Q(d_ff2_Y[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_32_ ( .D(n1372), .CK(n2798), .RN(n2732),
.Q(d_ff2_Y[32]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_33_ ( .D(n1370), .CK(n2845), .RN(n2732),
.Q(d_ff2_Y[33]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_34_ ( .D(n1368), .CK(n2846), .RN(n2732),
.Q(d_ff2_Y[34]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_35_ ( .D(n1366), .CK(n2798), .RN(n2732),
.Q(d_ff2_Y[35]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_36_ ( .D(n1364), .CK(n2028), .RN(n2732),
.Q(d_ff2_Y[36]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_37_ ( .D(n1362), .CK(n2845), .RN(n2731),
.Q(d_ff2_Y[37]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_38_ ( .D(n1360), .CK(n2028), .RN(n2731),
.Q(d_ff2_Y[38]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_39_ ( .D(n1358), .CK(n2794), .RN(n2731),
.Q(d_ff2_Y[39]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_40_ ( .D(n1356), .CK(n2847), .RN(n2731),
.Q(d_ff2_Y[40]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_41_ ( .D(n1354), .CK(n2847), .RN(n2731),
.Q(d_ff2_Y[41]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_42_ ( .D(n1352), .CK(n2847), .RN(n2730),
.Q(d_ff2_Y[42]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_43_ ( .D(n1350), .CK(n2847), .RN(n2730),
.Q(d_ff2_Y[43]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_44_ ( .D(n1348), .CK(n2847), .RN(n2730),
.Q(d_ff2_Y[44]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_45_ ( .D(n1346), .CK(n2848), .RN(n2730),
.Q(d_ff2_Y[45]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_46_ ( .D(n1344), .CK(n2848), .RN(n2730),
.Q(d_ff2_Y[46]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_47_ ( .D(n1342), .CK(n2848), .RN(n2729),
.Q(d_ff2_Y[47]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_48_ ( .D(n1340), .CK(n2848), .RN(n2729),
.Q(d_ff2_Y[48]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_49_ ( .D(n1338), .CK(n2848), .RN(n2729),
.Q(d_ff2_Y[49]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_50_ ( .D(n1336), .CK(n2849), .RN(n2729),
.Q(d_ff2_Y[50]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_51_ ( .D(n1334), .CK(n2849), .RN(n2729),
.Q(d_ff2_Y[51]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_63_ ( .D(n1310), .CK(n2850), .RN(n2727),
.Q(d_ff2_Y[63]) );
DFFRX1TS d_ff4_Xn_Q_reg_56_ ( .D(n1621), .CK(n2051), .RN(n2753), .Q(
d_ff_Xn[56]) );
DFFRX1TS d_ff4_Xn_Q_reg_58_ ( .D(n1619), .CK(n2820), .RN(n2790), .Q(
d_ff_Xn[58]) );
DFFRX1TS d_ff4_Xn_Q_reg_59_ ( .D(n1618), .CK(n2816), .RN(n2752), .Q(
d_ff_Xn[59]) );
DFFRX1TS d_ff4_Xn_Q_reg_60_ ( .D(n1617), .CK(n2853), .RN(n2752), .Q(
d_ff_Xn[60]) );
DFFRX1TS d_ff4_Xn_Q_reg_61_ ( .D(n1616), .CK(n2828), .RN(n2752), .Q(
d_ff_Xn[61]) );
DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n1674), .CK(n2815), .RN(n2762), .Q(
d_ff_Xn[3]) );
DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n1671), .CK(n2815), .RN(n2761), .Q(
d_ff_Xn[6]) );
DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n1670), .CK(n2024), .RN(n2761), .Q(
d_ff_Xn[7]) );
DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n1669), .CK(n2024), .RN(n2761), .Q(
d_ff_Xn[8]) );
DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n1668), .CK(n2816), .RN(n2760), .Q(
d_ff_Xn[9]) );
DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n1666), .CK(n2853), .RN(n2760), .Q(
d_ff_Xn[11]) );
DFFRX1TS d_ff4_Xn_Q_reg_13_ ( .D(n1664), .CK(n2817), .RN(n2760), .Q(
d_ff_Xn[13]) );
DFFRX1TS d_ff4_Xn_Q_reg_14_ ( .D(n1663), .CK(n2817), .RN(n2783), .Q(
d_ff_Xn[14]) );
DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n1658), .CK(n2818), .RN(n2759), .Q(
d_ff_Xn[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n1653), .CK(n2819), .RN(n2758), .Q(
d_ff_Xn[24]) );
DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n1651), .CK(n2819), .RN(n2758), .Q(
d_ff_Xn[26]) );
DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n1649), .CK(n2820), .RN(n2758), .Q(
d_ff_Xn[28]) );
DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n1648), .CK(n2828), .RN(n2035), .Q(
d_ff_Xn[29]) );
DFFRX1TS d_ff4_Xn_Q_reg_31_ ( .D(n1646), .CK(n2827), .RN(n2035), .Q(
d_ff_Xn[31]) );
DFFRX1TS d_ff4_Xn_Q_reg_32_ ( .D(n1645), .CK(n2050), .RN(n2037), .Q(
d_ff_Xn[32]) );
DFFRX1TS d_ff4_Xn_Q_reg_34_ ( .D(n1643), .CK(n2812), .RN(n2757), .Q(
d_ff_Xn[34]) );
DFFRX1TS d_ff4_Xn_Q_reg_35_ ( .D(n1642), .CK(n2821), .RN(n2757), .Q(
d_ff_Xn[35]) );
DFFRX1TS d_ff4_Xn_Q_reg_36_ ( .D(n1641), .CK(n2823), .RN(n2757), .Q(
d_ff_Xn[36]) );
DFFRX1TS d_ff4_Xn_Q_reg_39_ ( .D(n1638), .CK(n2823), .RN(n2756), .Q(
d_ff_Xn[39]) );
DFFRX1TS d_ff4_Xn_Q_reg_41_ ( .D(n1636), .CK(n2812), .RN(n2756), .Q(
d_ff_Xn[41]) );
DFFRX1TS d_ff4_Xn_Q_reg_42_ ( .D(n1635), .CK(n2050), .RN(n2756), .Q(
d_ff_Xn[42]) );
DFFRX1TS d_ff4_Xn_Q_reg_43_ ( .D(n1634), .CK(n2814), .RN(n2756), .Q(
d_ff_Xn[43]) );
DFFRX1TS d_ff4_Xn_Q_reg_45_ ( .D(n1632), .CK(n2822), .RN(n2755), .Q(
d_ff_Xn[45]) );
DFFRX1TS d_ff4_Xn_Q_reg_46_ ( .D(n1631), .CK(n2050), .RN(n2755), .Q(
d_ff_Xn[46]) );
DFFRX1TS d_ff4_Xn_Q_reg_48_ ( .D(n1629), .CK(n2820), .RN(n2755), .Q(
d_ff_Xn[48]) );
DFFRX1TS d_ff4_Xn_Q_reg_49_ ( .D(n1628), .CK(n2862), .RN(n2754), .Q(
d_ff_Xn[49]) );
DFFRX1TS d_ff4_Xn_Q_reg_53_ ( .D(n1624), .CK(n2051), .RN(n2754), .Q(
d_ff_Xn[53]) );
DFFRX1TS d_ff4_Xn_Q_reg_54_ ( .D(n1623), .CK(n2051), .RN(n2785), .Q(
d_ff_Xn[54]) );
DFFRX1TS d_ff4_Xn_Q_reg_55_ ( .D(n1622), .CK(n2051), .RN(n2785), .Q(
d_ff_Xn[55]) );
DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n1677), .CK(n2027), .RN(n2762), .Q(
d_ff_Xn[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_62_ ( .D(n1194), .CK(n2862), .RN(n2718),
.Q(d_ff2_X[62]) );
DFFRX1TS d_ff4_Yn_Q_reg_63_ ( .D(n1678), .CK(n2812), .RN(n2762), .Q(
d_ff_Yn[63]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_63_ ( .D(n1438), .CK(n2829), .RN(n2738),
.Q(d_ff2_Z[63]) );
DFFRX1TS d_ff4_Xn_Q_reg_63_ ( .D(n1614), .CK(n2024), .RN(n2752), .Q(
d_ff_Xn[63]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_62_ ( .D(n1322), .CK(n2850), .RN(n2727),
.Q(d_ff2_Y[62]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_54_ ( .D(n1202), .CK(n2861), .RN(n2782),
.Q(d_ff2_X[54]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_55_ ( .D(n1201), .CK(n2851), .RN(n2718),
.Q(d_ff2_X[55]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_54_ ( .D(n1330), .CK(n2849), .RN(n2728),
.Q(d_ff2_Y[54]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_55_ ( .D(n1329), .CK(n2849), .RN(n2728),
.Q(d_ff2_Y[55]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_53_ ( .D(n1203), .CK(n2855), .RN(n2779),
.Q(d_ff2_X[53]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
inst_CORDIC_FSM_v3_state_next[5]), .CK(n2794), .RN(n2780), .Q(
inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
inst_CORDIC_FSM_v3_state_next[4]), .CK(n2846), .RN(n2781), .Q(
inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_59_ ( .D(n1197), .CK(n2854), .RN(n2718),
.Q(d_ff2_X[59]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_61_ ( .D(n1195), .CK(n2862), .RN(n2718),
.Q(d_ff2_X[61]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
inst_CORDIC_FSM_v3_state_next[2]), .CK(n2795), .RN(n2780), .Q(
inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
inst_CORDIC_FSM_v3_state_next[1]), .CK(n2846), .RN(n2780), .Q(
inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_59_ ( .D(n1325), .CK(n2850), .RN(n2728),
.Q(d_ff2_Y[59]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_61_ ( .D(n1323), .CK(n2850), .RN(n2728),
.Q(d_ff2_Y[61]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_57_ ( .D(n1327), .CK(n2849), .RN(n2728),
.Q(d_ff2_Y[57]) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_56_ ( .D(n1200), .CK(n2852), .RN(n2718),
.Q(d_ff2_X[56]) );
DFFRX2TS VAR_CONT_temp_reg_1_ ( .D(n1878), .CK(n2858), .RN(n2781), .Q(
cont_var_out[1]) );
DFFRX2TS reg_val_muxY_2stage_Q_reg_56_ ( .D(n1328), .CK(n2849), .RN(n2728),
.Q(d_ff2_Y[56]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n2717), .CK(n2827), .RN(
n2780), .Q(inst_CORDIC_FSM_v3_state_reg[3]), .QN(n2716) );
DFFRX1TS reg_LUT_Q_reg_48_ ( .D(n1508), .CK(n2833), .RN(n2747), .Q(
d_ff3_LUT_out[48]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_55_ ( .D(n1446), .CK(n2832), .RN(n2739),
.Q(d_ff2_Z[55]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_54_ ( .D(n1447), .CK(n2840), .RN(n2739),
.Q(d_ff2_Z[54]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_51_ ( .D(n1450), .CK(n2829), .RN(n2739),
.Q(d_ff2_Z[51]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_50_ ( .D(n1451), .CK(n2053), .RN(n2739),
.Q(d_ff2_Z[50]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_49_ ( .D(n1452), .CK(n2832), .RN(n2739),
.Q(d_ff2_Z[49]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_48_ ( .D(n1453), .CK(n2839), .RN(n2740),
.Q(d_ff2_Z[48]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_47_ ( .D(n1454), .CK(n2838), .RN(n2740),
.Q(d_ff2_Z[47]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_46_ ( .D(n1455), .CK(n2830), .RN(n2740),
.Q(d_ff2_Z[46]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_45_ ( .D(n1456), .CK(n2840), .RN(n2740),
.Q(d_ff2_Z[45]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_44_ ( .D(n1457), .CK(n2837), .RN(n2740),
.Q(d_ff2_Z[44]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_43_ ( .D(n1458), .CK(n2837), .RN(n2740),
.Q(d_ff2_Z[43]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_42_ ( .D(n1459), .CK(n2837), .RN(n2740),
.Q(d_ff2_Z[42]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_41_ ( .D(n1460), .CK(n2837), .RN(n2740),
.Q(d_ff2_Z[41]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_40_ ( .D(n1461), .CK(n2837), .RN(n2740),
.Q(d_ff2_Z[40]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_39_ ( .D(n1462), .CK(n2837), .RN(n2740),
.Q(d_ff2_Z[39]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_38_ ( .D(n1463), .CK(n2837), .RN(n2741),
.Q(d_ff2_Z[38]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_37_ ( .D(n1464), .CK(n2837), .RN(n2741),
.Q(d_ff2_Z[37]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_36_ ( .D(n1465), .CK(n2837), .RN(n2741),
.Q(d_ff2_Z[36]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_34_ ( .D(n1467), .CK(n2047), .RN(n2741),
.Q(d_ff2_Z[34]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_33_ ( .D(n1468), .CK(n2833), .RN(n2741),
.Q(d_ff2_Z[33]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_32_ ( .D(n1469), .CK(n2810), .RN(n2741),
.Q(d_ff2_Z[32]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1470), .CK(n2835), .RN(n2741),
.Q(d_ff2_Z[31]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1471), .CK(n2836), .RN(n2741),
.Q(d_ff2_Z[30]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1472), .CK(n2841), .RN(n2741),
.Q(d_ff2_Z[29]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1473), .CK(n2831), .RN(n2742),
.Q(d_ff2_Z[28]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1474), .CK(n2047), .RN(n2742),
.Q(d_ff2_Z[27]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1475), .CK(n2833), .RN(n2742),
.Q(d_ff2_Z[26]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1476), .CK(n2859), .RN(n2742),
.Q(d_ff2_Z[25]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1477), .CK(n2835), .RN(n2742),
.Q(d_ff2_Z[24]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1478), .CK(n2836), .RN(n2742),
.Q(d_ff2_Z[23]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1479), .CK(n2841), .RN(n2742),
.Q(d_ff2_Z[22]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1480), .CK(n2831), .RN(n2742),
.Q(d_ff2_Z[21]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1481), .CK(n2047), .RN(n2742),
.Q(d_ff2_Z[20]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1482), .CK(n2833), .RN(n2742),
.Q(d_ff2_Z[19]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1483), .CK(n2047), .RN(n2743),
.Q(d_ff2_Z[18]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1484), .CK(n2047), .RN(n2743),
.Q(d_ff2_Z[17]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1485), .CK(n2047), .RN(n2743),
.Q(d_ff2_Z[16]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1486), .CK(n2824), .RN(n2743),
.Q(d_ff2_Z[15]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1487), .CK(n2835), .RN(n2743),
.Q(d_ff2_Z[14]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1488), .CK(n2836), .RN(n2743),
.Q(d_ff2_Z[13]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1489), .CK(n2841), .RN(n2743),
.Q(d_ff2_Z[12]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1490), .CK(n2831), .RN(n2743),
.Q(d_ff2_Z[11]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1492), .CK(n2833), .RN(n2743),
.Q(d_ff2_Z[9]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1493), .CK(n2835), .RN(n2737),
.Q(d_ff2_Z[8]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1495), .CK(n2796), .RN(n2746),
.Q(d_ff2_Z[6]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1496), .CK(n2836), .RN(n2744),
.Q(d_ff2_Z[5]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1497), .CK(n2834), .RN(n2745),
.Q(d_ff2_Z[4]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1498), .CK(n2834), .RN(n2737),
.Q(d_ff2_Z[3]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1499), .CK(n2834), .RN(n2746),
.Q(d_ff2_Z[2]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1500), .CK(n2834), .RN(n2744),
.Q(d_ff2_Z[1]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1501), .CK(n2834), .RN(n2745),
.Q(d_ff2_Z[0]) );
DFFRX1TS reg_LUT_Q_reg_10_ ( .D(n1539), .CK(n2827), .RN(n2750), .Q(
d_ff3_LUT_out[10]) );
DFFRX1TS reg_LUT_Q_reg_26_ ( .D(n1523), .CK(n2053), .RN(n2749), .Q(
d_ff3_LUT_out[26]) );
DFFRX4TS ITER_CONT_temp_reg_0_ ( .D(n1877), .CK(n2797), .RN(n2781), .Q(
cont_iter_out[0]), .QN(n2009) );
DFFRX1TS reg_LUT_Q_reg_13_ ( .D(n1536), .CK(n2853), .RN(n2750), .Q(
d_ff3_LUT_out[13]) );
DFFRX1TS reg_shift_x_Q_reg_13_ ( .D(n1281), .CK(n2820), .RN(n2725), .Q(
d_ff3_sh_x_out[13]) );
DFFRX1TS reg_shift_x_Q_reg_0_ ( .D(n1307), .CK(n2850), .RN(n2727), .Q(
d_ff3_sh_x_out[0]) );
DFFRX1TS reg_shift_x_Q_reg_59_ ( .D(n1186), .CK(n2834), .RN(n2792), .Q(
d_ff3_sh_x_out[59]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_35_ ( .D(n1466), .CK(n2837), .RN(n2741),
.Q(d_ff2_Z[35]) );
DFFRX4TS ITER_CONT_temp_reg_3_ ( .D(n1874), .CK(n2794), .RN(n2780), .Q(
cont_iter_out[3]), .QN(n2687) );
DFFRX2TS ITER_CONT_temp_reg_2_ ( .D(n1875), .CK(n2797), .RN(n2780), .Q(
cont_iter_out[2]), .QN(n2686) );
DFFRXLTS reg_operation_Q_reg_0_ ( .D(n1872), .CK(n2795), .RN(n2780), .Q(
d_ff1_operation_out), .QN(n2705) );
DFFSX1TS inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
inst_CORDIC_FSM_v3_state_next[0]), .CK(n2862), .SN(n2781), .Q(
inst_CORDIC_FSM_v3_state_reg[0]) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n1869), .CK(n2795), .RN(n2753), .Q(d_ff1_Z[0])
);
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n1868), .CK(n2795), .RN(n2719), .Q(d_ff1_Z[1])
);
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n1867), .CK(n2795), .RN(n2779), .Q(d_ff1_Z[2])
);
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n1866), .CK(n2795), .RN(n2782), .Q(d_ff1_Z[3])
);
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n1865), .CK(n2795), .RN(n2753), .Q(d_ff1_Z[4])
);
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n1603), .CK(n2827), .RN(n2760), .Q(
data_output[10]) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n1549), .CK(n2828), .RN(n2751), .Q(
d_ff3_LUT_out[0]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_59_ ( .D(n1442), .CK(n2832), .RN(n2738),
.Q(d_ff2_Z[59]) );
NAND2X4TS U1310 ( .A(cont_var_out[1]), .B(cont_var_out[0]), .Y(n2616) );
CMPR32X2TS U1311 ( .A(n2687), .B(d_ff2_Y[55]), .C(n2440), .CO(n2656), .S(
n2441) );
NAND3XLTS U1312 ( .A(n2057), .B(n2697), .C(n2685), .Y(n2274) );
CLKINVX3TS U1313 ( .A(n2017), .Y(n2018) );
CLKINVX3TS U1314 ( .A(n2017), .Y(n2020) );
INVX2TS U1315 ( .A(n2674), .Y(n2151) );
AOI222X1TS U1316 ( .A0(n2362), .A1(d_ff2_Y[5]), .B0(n2317), .B1(d_ff2_X[5]),
.C0(d_ff2_Z[5]), .C1(n2366), .Y(n2294) );
AOI222X1TS U1317 ( .A0(n2362), .A1(d_ff2_Y[6]), .B0(n2636), .B1(d_ff2_X[6]),
.C0(d_ff2_Z[6]), .C1(n2316), .Y(n2295) );
AOI222X1TS U1318 ( .A0(n2362), .A1(d_ff2_Y[9]), .B0(n2361), .B1(d_ff2_X[9]),
.C0(d_ff2_Z[9]), .C1(n2366), .Y(n2298) );
AOI222X1TS U1319 ( .A0(n2362), .A1(d_ff2_Y[11]), .B0(n2636), .B1(d_ff2_X[11]), .C0(d_ff2_Z[11]), .C1(n2366), .Y(n2300) );
AOI222X1TS U1320 ( .A0(n2312), .A1(d_ff2_Y[12]), .B0(n2361), .B1(d_ff2_X[12]), .C0(d_ff2_Z[12]), .C1(n2366), .Y(n2301) );
AOI222X1TS U1321 ( .A0(n2362), .A1(d_ff2_Y[13]), .B0(n2317), .B1(d_ff2_X[13]), .C0(d_ff2_Z[13]), .C1(n2366), .Y(n2302) );
AOI222X1TS U1322 ( .A0(n2362), .A1(d_ff2_Y[15]), .B0(n2361), .B1(d_ff2_X[15]), .C0(d_ff2_Z[15]), .C1(n2316), .Y(n2304) );
AOI222X1TS U1323 ( .A0(n2312), .A1(d_ff2_Y[16]), .B0(n2317), .B1(d_ff2_X[16]), .C0(d_ff2_Z[16]), .C1(n2328), .Y(n2305) );
AOI222X1TS U1324 ( .A0(n2312), .A1(d_ff2_Y[17]), .B0(n2317), .B1(d_ff2_X[17]), .C0(d_ff2_Z[17]), .C1(n2316), .Y(n2306) );
AOI222X1TS U1325 ( .A0(n2312), .A1(d_ff2_Y[18]), .B0(n2636), .B1(d_ff2_X[18]), .C0(d_ff2_Z[18]), .C1(n2366), .Y(n2307) );
AOI222X1TS U1326 ( .A0(n2312), .A1(d_ff2_Y[19]), .B0(n2361), .B1(d_ff2_X[19]), .C0(d_ff2_Z[19]), .C1(n2328), .Y(n2308) );
AOI222X1TS U1327 ( .A0(n2312), .A1(d_ff2_Y[23]), .B0(n2317), .B1(d_ff2_X[23]), .C0(d_ff2_Z[23]), .C1(n2316), .Y(n2313) );
AOI222X1TS U1328 ( .A0(n2621), .A1(d_ff2_Y[24]), .B0(n2636), .B1(d_ff2_X[24]), .C0(d_ff2_Z[24]), .C1(n2328), .Y(n2314) );
AOI222X1TS U1329 ( .A0(n2324), .A1(d_ff2_Y[25]), .B0(n2361), .B1(d_ff2_X[25]), .C0(d_ff2_Z[25]), .C1(n2316), .Y(n2315) );
AOI222X1TS U1330 ( .A0(n2324), .A1(d_ff2_Y[26]), .B0(n2317), .B1(d_ff2_X[26]), .C0(d_ff2_Z[26]), .C1(n2316), .Y(n2318) );
AOI222X1TS U1331 ( .A0(n2324), .A1(d_ff2_Y[27]), .B0(n2344), .B1(d_ff2_X[27]), .C0(d_ff2_Z[27]), .C1(n2328), .Y(n2319) );
AOI222X1TS U1332 ( .A0(n2324), .A1(d_ff2_Y[28]), .B0(n2632), .B1(d_ff2_X[28]), .C0(d_ff2_Z[28]), .C1(n2328), .Y(n2320) );
AOI222X1TS U1333 ( .A0(n2324), .A1(d_ff2_Y[29]), .B0(n2344), .B1(d_ff2_X[29]), .C0(d_ff2_Z[29]), .C1(n2328), .Y(n2321) );
AOI222X1TS U1334 ( .A0(n2409), .A1(d_ff2_Y[30]), .B0(n2333), .B1(d_ff2_X[30]), .C0(d_ff2_Z[30]), .C1(n2328), .Y(n2322) );
AOI222X1TS U1335 ( .A0(n2324), .A1(d_ff2_Y[32]), .B0(n2632), .B1(d_ff2_X[32]), .C0(d_ff2_Z[32]), .C1(n2328), .Y(n2325) );
AOI222X1TS U1336 ( .A0(n2426), .A1(d_ff2_Y[33]), .B0(n2333), .B1(d_ff2_X[33]), .C0(d_ff2_Z[33]), .C1(n2328), .Y(n2329) );
AOI222X1TS U1337 ( .A0(n2634), .A1(d_ff2_Y[34]), .B0(n2344), .B1(d_ff2_X[34]), .C0(d_ff2_Z[34]), .C1(n2339), .Y(n2330) );
AOI222X1TS U1338 ( .A0(n2621), .A1(d_ff2_Y[37]), .B0(n2333), .B1(d_ff2_X[37]), .C0(d_ff2_Z[37]), .C1(n2339), .Y(n2334) );
AOI222X1TS U1339 ( .A0(n2409), .A1(d_ff2_Y[38]), .B0(n2632), .B1(d_ff2_X[38]), .C0(d_ff2_Z[38]), .C1(n2339), .Y(n2335) );
AOI222X1TS U1340 ( .A0(n2426), .A1(d_ff2_Y[39]), .B0(n2333), .B1(d_ff2_X[39]), .C0(d_ff2_Z[39]), .C1(n2339), .Y(n2336) );
AOI222X1TS U1341 ( .A0(n2634), .A1(d_ff2_Y[40]), .B0(n2344), .B1(d_ff2_X[40]), .C0(d_ff2_Z[40]), .C1(n2339), .Y(n2337) );
AOI222X1TS U1342 ( .A0(n2348), .A1(d_ff2_Y[44]), .B0(n2632), .B1(d_ff2_X[44]), .C0(d_ff2_Z[44]), .C1(n2354), .Y(n2342) );
AOI222X1TS U1343 ( .A0(n2348), .A1(d_ff2_Y[45]), .B0(n2333), .B1(d_ff2_X[45]), .C0(d_ff2_Z[45]), .C1(n2354), .Y(n2343) );
AOI222X1TS U1344 ( .A0(n2348), .A1(d_ff2_Y[46]), .B0(n2344), .B1(d_ff2_X[46]), .C0(d_ff2_Z[46]), .C1(n2354), .Y(n2345) );
AOI222X1TS U1345 ( .A0(n2348), .A1(d_ff2_Y[47]), .B0(n2421), .B1(d_ff2_X[47]), .C0(d_ff2_Z[47]), .C1(n2354), .Y(n2346) );
AOI222X1TS U1346 ( .A0(n2348), .A1(d_ff2_Y[48]), .B0(n2425), .B1(d_ff2_X[48]), .C0(d_ff2_Z[48]), .C1(n2354), .Y(n2347) );
AOI222X1TS U1347 ( .A0(n2348), .A1(d_ff2_Y[49]), .B0(n2421), .B1(d_ff2_X[49]), .C0(d_ff2_Z[49]), .C1(n2354), .Y(n2349) );
AOI222X1TS U1348 ( .A0(n2422), .A1(d_ff2_Y[50]), .B0(n2425), .B1(d_ff2_X[50]), .C0(d_ff2_Z[50]), .C1(n2354), .Y(n2350) );
AOI222X1TS U1349 ( .A0(n2634), .A1(d_ff2_Y[51]), .B0(n2421), .B1(d_ff2_X[51]), .C0(d_ff2_Z[51]), .C1(n2354), .Y(n2351) );
AOI222X1TS U1350 ( .A0(n2426), .A1(d_ff2_Y[54]), .B0(n2421), .B1(d_ff2_X[54]), .C0(d_ff2_Z[54]), .C1(n2354), .Y(n2355) );
AOI222X1TS U1351 ( .A0(n2422), .A1(d_ff2_Y[55]), .B0(n2425), .B1(d_ff2_X[55]), .C0(d_ff2_Z[55]), .C1(n2424), .Y(n2356) );
AO22XLTS U1352 ( .A0(n2562), .A1(d_ff_Yn[0]), .B0(d_ff2_Y[0]), .B1(n2158),
.Y(n1436) );
NAND2BXLTS U1353 ( .AN(n2499), .B(n2498), .Y(n1513) );
OAI2BB2XLTS U1354 ( .B0(ack_cordic), .B1(n2277), .A0N(enab_cont_iter), .A1N(
n2654), .Y(inst_CORDIC_FSM_v3_state_next[7]) );
CLKBUFX3TS U1355 ( .A(n2066), .Y(n2124) );
OR2X1TS U1356 ( .A(n2434), .B(n2683), .Y(n2010) );
CLKBUFX3TS U1357 ( .A(n2793), .Y(n2036) );
INVX2TS U1358 ( .A(n2017), .Y(n2019) );
CLKBUFX3TS U1359 ( .A(n2433), .Y(n2470) );
BUFX4TS U1360 ( .A(n2048), .Y(n2832) );
CLKBUFX2TS U1361 ( .A(clk), .Y(n2824) );
INVX2TS U1362 ( .A(n2686), .Y(n2011) );
INVX2TS U1363 ( .A(n2011), .Y(n2012) );
INVX2TS U1364 ( .A(cont_iter_out[0]), .Y(n2013) );
CLKINVX3TS U1365 ( .A(n2017), .Y(n2014) );
INVX2TS U1366 ( .A(n2017), .Y(n2015) );
INVX2TS U1367 ( .A(n2017), .Y(n2016) );
INVX2TS U1368 ( .A(n2124), .Y(n2017) );
CLKINVX3TS U1369 ( .A(rst), .Y(n2035) );
CLKINVX3TS U1370 ( .A(n2666), .Y(n2134) );
CLKINVX3TS U1371 ( .A(n2668), .Y(n2157) );
INVX2TS U1372 ( .A(n2665), .Y(n2523) );
CLKINVX3TS U1373 ( .A(n2365), .Y(n2494) );
CLKINVX3TS U1374 ( .A(n2365), .Y(n2361) );
CLKINVX3TS U1375 ( .A(n2365), .Y(n2317) );
CLKINVX3TS U1376 ( .A(n2365), .Y(n2636) );
CLKINVX3TS U1377 ( .A(n2668), .Y(n2254) );
CLKBUFX3TS U1378 ( .A(n2671), .Y(n2668) );
NAND2X1TS U1379 ( .A(n2644), .B(cont_iter_out[3]), .Y(n2268) );
CLKINVX3TS U1380 ( .A(n2538), .Y(n2644) );
CLKINVX3TS U1381 ( .A(n2717), .Y(n2113) );
INVX2TS U1382 ( .A(n2256), .Y(n2717) );
NOR2X2TS U1383 ( .A(n2638), .B(n2009), .Y(n2637) );
CLKINVX3TS U1384 ( .A(n2430), .Y(n2679) );
INVX2TS U1385 ( .A(n2430), .Y(n2144) );
INVX2TS U1386 ( .A(n2151), .Y(n2021) );
CLKINVX3TS U1387 ( .A(n2021), .Y(n2022) );
NOR2X2TS U1388 ( .A(d_ff2_X[59]), .B(n2581), .Y(n2580) );
NOR2X2TS U1389 ( .A(d_ff2_Y[59]), .B(n2535), .Y(n2574) );
CLKINVX3TS U1390 ( .A(n2669), .Y(n2279) );
INVX2TS U1391 ( .A(n2669), .Y(n2556) );
INVX2TS U1392 ( .A(n2669), .Y(n2146) );
INVX2TS U1393 ( .A(n2669), .Y(n2525) );
BUFX3TS U1394 ( .A(n2036), .Y(n2037) );
OAI21X2TS U1395 ( .A0(cont_iter_out[0]), .A1(cont_iter_out[2]), .B0(n2687),
.Y(n2497) );
AOI32X1TS U1396 ( .A0(n2648), .A1(n2662), .A2(n2683), .B0(n2703), .B1(n2430),
.Y(n1507) );
NOR2X2TS U1397 ( .A(n2141), .B(cont_iter_out[0]), .Y(n2648) );
CLKBUFX3TS U1398 ( .A(n2668), .Y(n2666) );
CLKBUFX3TS U1399 ( .A(n2668), .Y(n2665) );
CLKINVX3TS U1400 ( .A(n2605), .Y(n2620) );
CLKINVX3TS U1401 ( .A(n2605), .Y(n2623) );
CLKINVX3TS U1402 ( .A(n2605), .Y(n2401) );
BUFX3TS U1403 ( .A(n2782), .Y(n2784) );
INVX2TS U1404 ( .A(n2021), .Y(n2431) );
CLKINVX3TS U1405 ( .A(n2663), .Y(n2158) );
CLKBUFX3TS U1406 ( .A(n2460), .Y(n2449) );
AOI22X2TS U1407 ( .A0(cont_iter_out[0]), .A1(n2687), .B0(n2251), .B1(n2013),
.Y(n2452) );
CLKINVX3TS U1408 ( .A(n2399), .Y(n2405) );
CLKINVX3TS U1409 ( .A(n2399), .Y(n2425) );
CLKINVX3TS U1410 ( .A(n2399), .Y(n2421) );
BUFX3TS U1411 ( .A(n2788), .Y(n2790) );
BUFX3TS U1412 ( .A(n2753), .Y(n2789) );
BUFX3TS U1413 ( .A(n2737), .Y(n2791) );
BUFX3TS U1414 ( .A(n2746), .Y(n2786) );
CLKBUFX3TS U1415 ( .A(n2470), .Y(n2640) );
INVX2TS U1416 ( .A(n2010), .Y(n2023) );
BUFX3TS U1417 ( .A(n2793), .Y(n2781) );
NOR4BX2TS U1418 ( .AN(n2041), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[6]), .D(inst_CORDIC_FSM_v3_state_reg[3]),
.Y(n2267) );
NOR3X2TS U1419 ( .A(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(inst_CORDIC_FSM_v3_state_reg[0]),
.Y(n2041) );
CLKBUFX3TS U1420 ( .A(n2674), .Y(n2664) );
CLKBUFX3TS U1421 ( .A(n2674), .Y(n2663) );
BUFX3TS U1422 ( .A(clk), .Y(n2048) );
AOI222X1TS U1423 ( .A0(n2599), .A1(d_ff3_sh_x_out[54]), .B0(n2361), .B1(
d_ff3_sh_y_out[54]), .C0(d_ff3_LUT_out[54]), .C1(n2626), .Y(n2368) );
AOI222X1TS U1424 ( .A0(n2599), .A1(d_ff3_sh_x_out[39]), .B0(n2636), .B1(
d_ff3_sh_y_out[39]), .C0(d_ff3_LUT_out[39]), .C1(n2626), .Y(n2376) );
AOI222X1TS U1425 ( .A0(n2397), .A1(d_ff3_sh_x_out[33]), .B0(n2317), .B1(
d_ff3_sh_y_out[33]), .C0(d_ff3_LUT_out[33]), .C1(n2626), .Y(n2382) );
AOI222X1TS U1426 ( .A0(n2397), .A1(d_ff3_sh_x_out[29]), .B0(n2421), .B1(
d_ff3_sh_y_out[29]), .C0(d_ff3_LUT_out[29]), .C1(n2626), .Y(n2386) );
AOI222X1TS U1427 ( .A0(n2397), .A1(d_ff3_sh_x_out[27]), .B0(n2361), .B1(
d_ff3_sh_y_out[27]), .C0(d_ff3_LUT_out[27]), .C1(n2626), .Y(n2388) );
CLKBUFX3TS U1428 ( .A(n2326), .Y(n2626) );
BUFX3TS U1429 ( .A(n2790), .Y(n2038) );
BUFX3TS U1430 ( .A(n2782), .Y(n2792) );
NAND2X2TS U1431 ( .A(n2687), .B(n2011), .Y(n2265) );
CLKBUFX3TS U1432 ( .A(n2630), .Y(n2621) );
CLKBUFX3TS U1433 ( .A(n2630), .Y(n2409) );
CLKBUFX3TS U1434 ( .A(n2630), .Y(n2634) );
CLKBUFX3TS U1435 ( .A(n2466), .Y(n2434) );
CLKBUFX3TS U1436 ( .A(n2466), .Y(n2460) );
BUFX6TS U1437 ( .A(n2836), .Y(n2837) );
BUFX6TS U1438 ( .A(n2027), .Y(n2815) );
BUFX6TS U1439 ( .A(n2821), .Y(n2819) );
BUFX6TS U1440 ( .A(n2841), .Y(n2847) );
BUFX6TS U1441 ( .A(n2835), .Y(n2834) );
BUFX6TS U1442 ( .A(n2822), .Y(n2818) );
BUFX6TS U1443 ( .A(n2852), .Y(n2850) );
BUFX6TS U1444 ( .A(n2050), .Y(n2813) );
BUFX4TS U1445 ( .A(n2814), .Y(n2825) );
BUFX4TS U1446 ( .A(n2814), .Y(n2051) );
BUFX6TS U1447 ( .A(n2049), .Y(n2860) );
BUFX4TS U1448 ( .A(n2857), .Y(n2858) );
BUFX4TS U1449 ( .A(n2857), .Y(n2862) );
BUFX6TS U1450 ( .A(n2831), .Y(n2842) );
BUFX6TS U1451 ( .A(n2047), .Y(n2844) );
BUFX6TS U1452 ( .A(n2823), .Y(n2817) );
BUFX4TS U1453 ( .A(n2825), .Y(n2024) );
BUFX4TS U1454 ( .A(n2825), .Y(n2826) );
BUFX6TS U1455 ( .A(n2825), .Y(n2820) );
BUFX6TS U1456 ( .A(n2825), .Y(n2853) );
BUFX6TS U1457 ( .A(n2825), .Y(n2828) );
BUFX6TS U1458 ( .A(n2825), .Y(n2827) );
BUFX6TS U1459 ( .A(n2855), .Y(n2849) );
BUFX4TS U1460 ( .A(n2048), .Y(n2855) );
BUFX4TS U1461 ( .A(n2859), .Y(n2843) );
BUFX6TS U1462 ( .A(n2048), .Y(n2830) );
BUFX6TS U1463 ( .A(n2854), .Y(n2848) );
BUFX4TS U1464 ( .A(n2055), .Y(n2854) );
BUFX6TS U1465 ( .A(n2851), .Y(n2856) );
BUFX4TS U1466 ( .A(n2048), .Y(n2851) );
BUFX3TS U1467 ( .A(n2052), .Y(n2800) );
CLKINVX6TS U1468 ( .A(n2029), .Y(n2025) );
BUFX6TS U1469 ( .A(n2052), .Y(n2799) );
BUFX6TS U1470 ( .A(n2052), .Y(n2801) );
BUFX6TS U1471 ( .A(n2052), .Y(n2804) );
BUFX6TS U1472 ( .A(n2052), .Y(n2803) );
CLKINVX6TS U1473 ( .A(n2029), .Y(n2026) );
CLKBUFX2TS U1474 ( .A(n2056), .Y(n2810) );
BUFX6TS U1475 ( .A(n2056), .Y(n2808) );
BUFX6TS U1476 ( .A(n2056), .Y(n2807) );
BUFX6TS U1477 ( .A(n2056), .Y(n2806) );
BUFX6TS U1478 ( .A(n2056), .Y(n2805) );
BUFX6TS U1479 ( .A(n2056), .Y(n2809) );
BUFX4TS U1480 ( .A(n2838), .Y(n2836) );
BUFX6TS U1481 ( .A(n2048), .Y(n2838) );
BUFX4TS U1482 ( .A(n2839), .Y(n2835) );
BUFX6TS U1483 ( .A(n2048), .Y(n2839) );
BUFX4TS U1484 ( .A(n2048), .Y(n2829) );
BUFX6TS U1485 ( .A(n2048), .Y(n2053) );
BUFX4TS U1486 ( .A(n2048), .Y(n2840) );
BUFX6TS U1487 ( .A(n2055), .Y(n2852) );
BUFX6TS U1488 ( .A(clk), .Y(n2857) );
BUFX6TS U1489 ( .A(n2048), .Y(n2861) );
BUFX6TS U1490 ( .A(n2802), .Y(n2049) );
BUFX4TS U1491 ( .A(n2055), .Y(n2027) );
BUFX4TS U1492 ( .A(n2055), .Y(n2812) );
BUFX3TS U1493 ( .A(clk), .Y(n2055) );
BUFX6TS U1494 ( .A(n2055), .Y(n2823) );
BUFX6TS U1495 ( .A(n2055), .Y(n2050) );
BUFX6TS U1496 ( .A(n2055), .Y(n2814) );
BUFX4TS U1497 ( .A(n2055), .Y(n2821) );
CLKINVX6TS U1498 ( .A(n2029), .Y(n2028) );
CLKBUFX2TS U1499 ( .A(n2054), .Y(n2796) );
BUFX6TS U1500 ( .A(n2830), .Y(n2833) );
BUFX6TS U1501 ( .A(n2840), .Y(n2831) );
BUFX4TS U1502 ( .A(n2053), .Y(n2841) );
BUFX6TS U1503 ( .A(n2829), .Y(n2047) );
INVX2TS U1504 ( .A(n2810), .Y(n2029) );
CLKINVX6TS U1505 ( .A(n2029), .Y(n2030) );
CLKINVX6TS U1506 ( .A(n2029), .Y(n2031) );
CLKBUFX2TS U1507 ( .A(clk), .Y(n2859) );
BUFX6TS U1508 ( .A(n2054), .Y(n2797) );
NOR3X4TS U1509 ( .A(n2683), .B(n2013), .C(n2643), .Y(n2654) );
NOR2X4TS U1510 ( .A(n2013), .B(n2588), .Y(n2288) );
OAI21X2TS U1511 ( .A0(n2013), .A1(n2141), .B0(n2023), .Y(n2155) );
BUFX6TS U1512 ( .A(n2054), .Y(n2794) );
BUFX6TS U1513 ( .A(n2054), .Y(n2846) );
BUFX6TS U1514 ( .A(n2054), .Y(n2845) );
BUFX6TS U1515 ( .A(n2054), .Y(n2798) );
XOR2XLTS U1516 ( .A(d_ff_Yn[63]), .B(n2164), .Y(n2165) );
OAI33X4TS U1517 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(
d_ff1_operation_out), .A2(n2684), .B0(n2681), .B1(n2705), .B2(
d_ff1_shift_region_flag_out[0]), .Y(n2164) );
AOI222X1TS U1518 ( .A0(n2397), .A1(d_ff3_sh_x_out[26]), .B0(n2425), .B1(
d_ff3_sh_y_out[26]), .C0(d_ff3_LUT_out[26]), .C1(n2626), .Y(n2389) );
AOI222X1TS U1519 ( .A0(n2409), .A1(d_ff3_sh_x_out[10]), .B0(n2421), .B1(
d_ff3_sh_y_out[10]), .C0(d_ff3_LUT_out[10]), .C1(n2411), .Y(n2410) );
AOI222X1TS U1520 ( .A0(n2431), .A1(d_ff2_Z[0]), .B0(n2254), .B1(d_ff_Zn[0]),
.C0(n2019), .C1(d_ff1_Z[0]), .Y(n2100) );
AOI222X1TS U1521 ( .A0(n2362), .A1(d_ff2_Y[0]), .B0(n2494), .B1(d_ff2_X[0]),
.C0(d_ff2_Z[0]), .C1(n2339), .Y(n2327) );
AOI222X4TS U1522 ( .A0(n2504), .A1(d_ff2_Z[1]), .B0(n2016), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n2279), .Y(n2103) );
AOI222X1TS U1523 ( .A0(n2312), .A1(d_ff2_Y[1]), .B0(n2494), .B1(d_ff2_X[1]),
.C0(d_ff2_Z[1]), .C1(n2608), .Y(n2293) );
AOI222X1TS U1524 ( .A0(n2543), .A1(d_ff2_Z[2]), .B0(n2014), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n2157), .Y(n2107) );
AOI222X1TS U1525 ( .A0(n2312), .A1(d_ff2_Y[2]), .B0(n2494), .B1(d_ff2_X[2]),
.C0(d_ff2_Z[2]), .C1(n2366), .Y(n2291) );
AOI222X4TS U1526 ( .A0(n2504), .A1(d_ff2_Z[3]), .B0(n2018), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n2254), .Y(n2110) );
AOI222X1TS U1527 ( .A0(n2362), .A1(d_ff2_Y[3]), .B0(n2494), .B1(d_ff2_X[3]),
.C0(d_ff2_Z[3]), .C1(n2608), .Y(n2292) );
AOI222X1TS U1528 ( .A0(n2362), .A1(d_ff2_Y[4]), .B0(n2361), .B1(d_ff2_X[4]),
.C0(d_ff2_Z[4]), .C1(n2366), .Y(n2296) );
AOI222X4TS U1529 ( .A0(n2547), .A1(d_ff2_Z[5]), .B0(n2020), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n2254), .Y(n2115) );
AOI222X1TS U1530 ( .A0(n2158), .A1(d_ff2_Z[6]), .B0(n2015), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n2254), .Y(n2117) );
AOI222X4TS U1531 ( .A0(n2504), .A1(d_ff2_Z[8]), .B0(n2014), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n2157), .Y(n2120) );
AOI222X4TS U1532 ( .A0(n2547), .A1(d_ff2_Z[9]), .B0(n2020), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n2157), .Y(n2122) );
AOI222X1TS U1533 ( .A0(n2158), .A1(d_ff2_Z[11]), .B0(n2018), .B1(d_ff1_Z[11]), .C0(d_ff_Zn[11]), .C1(n2157), .Y(n2126) );
AOI222X1TS U1534 ( .A0(n2139), .A1(d_ff2_Z[12]), .B0(n2124), .B1(d_ff1_Z[12]), .C0(d_ff_Zn[12]), .C1(n2134), .Y(n2128) );
AOI222X1TS U1535 ( .A0(n2543), .A1(d_ff2_Z[13]), .B0(n2015), .B1(d_ff1_Z[13]), .C0(d_ff_Zn[13]), .C1(n2134), .Y(n2129) );
AOI222X4TS U1536 ( .A0(n2504), .A1(d_ff2_Z[14]), .B0(n2019), .B1(d_ff1_Z[14]), .C0(d_ff_Zn[14]), .C1(n2134), .Y(n2131) );
AOI222X4TS U1537 ( .A0(n2547), .A1(d_ff2_Z[15]), .B0(n2014), .B1(d_ff1_Z[15]), .C0(d_ff_Zn[15]), .C1(n2134), .Y(n2133) );
AOI222X1TS U1538 ( .A0(n2158), .A1(d_ff2_Z[16]), .B0(n2015), .B1(d_ff1_Z[16]), .C0(d_ff_Zn[16]), .C1(n2134), .Y(n2135) );
AOI222X1TS U1539 ( .A0(n2139), .A1(d_ff2_Z[17]), .B0(n2014), .B1(d_ff1_Z[17]), .C0(d_ff_Zn[17]), .C1(n2553), .Y(n2140) );
AOI222X4TS U1540 ( .A0(n2547), .A1(d_ff2_Z[18]), .B0(n2020), .B1(d_ff1_Z[18]), .C0(d_ff_Zn[18]), .C1(n2523), .Y(n2143) );
AOI222X1TS U1541 ( .A0(n2158), .A1(d_ff2_Z[19]), .B0(n2015), .B1(d_ff1_Z[19]), .C0(d_ff_Zn[19]), .C1(n2523), .Y(n2145) );
AOI222X1TS U1542 ( .A0(n2543), .A1(d_ff2_Z[20]), .B0(n2020), .B1(d_ff1_Z[20]), .C0(d_ff_Zn[20]), .C1(n2523), .Y(n2148) );
AOI222X1TS U1543 ( .A0(n2324), .A1(d_ff2_Y[20]), .B0(n2317), .B1(d_ff2_X[20]), .C0(d_ff2_Z[20]), .C1(n2316), .Y(n2309) );
AOI222X1TS U1544 ( .A0(n2139), .A1(d_ff2_Z[21]), .B0(n2018), .B1(d_ff1_Z[21]), .C0(d_ff_Zn[21]), .C1(n2523), .Y(n2150) );
AOI222X1TS U1545 ( .A0(n2324), .A1(d_ff2_Y[21]), .B0(n2636), .B1(d_ff2_X[21]), .C0(d_ff2_Z[21]), .C1(n2316), .Y(n2310) );
AOI222X1TS U1546 ( .A0(n2504), .A1(d_ff2_Z[22]), .B0(n2015), .B1(d_ff1_Z[22]), .C0(d_ff_Zn[22]), .C1(n2157), .Y(n2153) );
AOI222X1TS U1547 ( .A0(n2324), .A1(d_ff2_Y[22]), .B0(n2361), .B1(d_ff2_X[22]), .C0(d_ff2_Z[22]), .C1(n2316), .Y(n2311) );
AOI222X1TS U1548 ( .A0(n2547), .A1(d_ff2_Z[23]), .B0(n2018), .B1(d_ff1_Z[23]), .C0(d_ff_Zn[23]), .C1(n2157), .Y(n2156) );
AOI222X1TS U1549 ( .A0(n2158), .A1(d_ff2_Z[24]), .B0(n2124), .B1(d_ff1_Z[24]), .C0(d_ff_Zn[24]), .C1(n2157), .Y(n2159) );
AOI222X1TS U1550 ( .A0(n2022), .A1(d_ff2_Z[25]), .B0(n2015), .B1(d_ff1_Z[25]), .C0(d_ff_Zn[25]), .C1(n2157), .Y(n2152) );
AOI222X1TS U1551 ( .A0(n2139), .A1(d_ff2_Z[27]), .B0(n2124), .B1(d_ff1_Z[27]), .C0(d_ff_Zn[27]), .C1(n2519), .Y(n2147) );
AOI222X1TS U1552 ( .A0(n2022), .A1(d_ff2_Z[28]), .B0(n2014), .B1(d_ff1_Z[28]), .C0(d_ff_Zn[28]), .C1(n2525), .Y(n2142) );
AOI222X1TS U1553 ( .A0(n2022), .A1(d_ff2_Z[29]), .B0(n2015), .B1(d_ff1_Z[29]), .C0(d_ff_Zn[29]), .C1(n2146), .Y(n2136) );
AOI222X1TS U1554 ( .A0(n2022), .A1(d_ff2_Z[30]), .B0(n2014), .B1(d_ff1_Z[30]), .C0(d_ff_Zn[30]), .C1(n2556), .Y(n2132) );
AOI222X1TS U1555 ( .A0(n2348), .A1(d_ff2_Y[31]), .B0(n2344), .B1(d_ff2_X[31]), .C0(d_ff2_Z[31]), .C1(n2328), .Y(n2323) );
AOI222X1TS U1556 ( .A0(n2022), .A1(d_ff2_Z[36]), .B0(n2020), .B1(d_ff1_Z[36]), .C0(d_ff_Zn[36]), .C1(n2134), .Y(n2116) );
AOI222X1TS U1557 ( .A0(n2600), .A1(d_ff2_Y[36]), .B0(n2632), .B1(d_ff2_X[36]), .C0(d_ff2_Z[36]), .C1(n2339), .Y(n2332) );
AOI222X1TS U1558 ( .A0(n2113), .A1(d_ff2_Z[37]), .B0(n2015), .B1(d_ff1_Z[37]), .C0(d_ff_Zn[37]), .C1(n2134), .Y(n2114) );
AOI222X1TS U1559 ( .A0(n2113), .A1(d_ff2_Z[38]), .B0(n2018), .B1(d_ff1_Z[38]), .C0(d_ff_Zn[38]), .C1(n2134), .Y(n2111) );
AOI222X1TS U1560 ( .A0(n2113), .A1(d_ff2_Z[40]), .B0(n2018), .B1(d_ff1_Z[40]), .C0(d_ff_Zn[40]), .C1(n2134), .Y(n2099) );
AOI222X1TS U1561 ( .A0(n2113), .A1(d_ff2_Z[41]), .B0(n2015), .B1(d_ff1_Z[41]), .C0(d_ff_Zn[41]), .C1(n2553), .Y(n2095) );
AOI222X1TS U1562 ( .A0(n2348), .A1(d_ff2_Y[41]), .B0(n2632), .B1(d_ff2_X[41]), .C0(d_ff2_Z[41]), .C1(n2339), .Y(n2338) );
AOI222X1TS U1563 ( .A0(n2113), .A1(d_ff2_Z[42]), .B0(n2020), .B1(d_ff1_Z[42]), .C0(d_ff_Zn[42]), .C1(n2519), .Y(n2090) );
AOI222X1TS U1564 ( .A0(n2348), .A1(d_ff2_Y[42]), .B0(n2333), .B1(d_ff2_X[42]), .C0(d_ff2_Z[42]), .C1(n2339), .Y(n2340) );
AOI222X1TS U1565 ( .A0(n2348), .A1(d_ff2_Y[43]), .B0(n2344), .B1(d_ff2_X[43]), .C0(d_ff2_Z[43]), .C1(n2354), .Y(n2341) );
AOI222X1TS U1566 ( .A0(n2113), .A1(d_ff2_Z[44]), .B0(n2124), .B1(d_ff1_Z[44]), .C0(d_ff_Zn[44]), .C1(n2525), .Y(n2085) );
AOI222X1TS U1567 ( .A0(n2113), .A1(d_ff2_Z[45]), .B0(n2016), .B1(d_ff1_Z[45]), .C0(d_ff_Zn[45]), .C1(n2146), .Y(n2078) );
AOI222X1TS U1568 ( .A0(n2113), .A1(d_ff2_Z[46]), .B0(n2124), .B1(d_ff1_Z[46]), .C0(d_ff_Zn[46]), .C1(n2279), .Y(n2071) );
AOI222X1TS U1569 ( .A0(n2256), .A1(d_ff2_Z[47]), .B0(n2014), .B1(d_ff1_Z[47]), .C0(d_ff_Zn[47]), .C1(n2279), .Y(n2083) );
AOI222X1TS U1570 ( .A0(n2256), .A1(d_ff2_Z[48]), .B0(n2016), .B1(d_ff1_Z[48]), .C0(d_ff_Zn[48]), .C1(n2279), .Y(n2067) );
AOI222X1TS U1571 ( .A0(n2547), .A1(d_ff2_Z[49]), .B0(n2014), .B1(d_ff1_Z[49]), .C0(d_ff_Zn[49]), .C1(n2279), .Y(n2069) );
AOI222X1TS U1572 ( .A0(n2256), .A1(d_ff2_Z[50]), .B0(n2020), .B1(d_ff1_Z[50]), .C0(d_ff_Zn[50]), .C1(n2279), .Y(n2068) );
AOI222X1TS U1573 ( .A0(n2158), .A1(d_ff2_Z[51]), .B0(n2016), .B1(d_ff1_Z[51]), .C0(d_ff_Zn[51]), .C1(n2254), .Y(n2075) );
AOI222X1TS U1574 ( .A0(n2256), .A1(d_ff2_Z[54]), .B0(n2020), .B1(d_ff1_Z[54]), .C0(d_ff_Zn[54]), .C1(n2254), .Y(n2080) );
AOI222X1TS U1575 ( .A0(n2139), .A1(d_ff2_Z[55]), .B0(n2018), .B1(d_ff1_Z[55]), .C0(d_ff_Zn[55]), .C1(n2254), .Y(n2073) );
NOR2X2TS U1576 ( .A(n2285), .B(n2589), .Y(n2499) );
AOI221X4TS U1577 ( .A0(n2251), .A1(n2679), .B0(d_ff3_LUT_out[7]), .B1(n2538),
.C0(n2238), .Y(n2094) );
NOR2X2TS U1578 ( .A(n2287), .B(n2250), .Y(n2238) );
CLKBUFX3TS U1579 ( .A(n2508), .Y(n2507) );
CLKBUFX3TS U1580 ( .A(n2513), .Y(n2512) );
CLKBUFX3TS U1581 ( .A(n2455), .Y(n2459) );
CLKBUFX3TS U1582 ( .A(n2454), .Y(n2455) );
AOI222X1TS U1583 ( .A0(n2229), .A1(data_output[60]), .B0(n2228), .B1(
d_ff_Yn[60]), .C0(n2216), .C1(d_ff_Xn[60]), .Y(n2230) );
AOI222X1TS U1584 ( .A0(n2229), .A1(data_output[59]), .B0(n2228), .B1(
d_ff_Yn[59]), .C0(n2227), .C1(d_ff_Xn[59]), .Y(n2226) );
AOI222X1TS U1585 ( .A0(n2229), .A1(data_output[58]), .B0(n2228), .B1(
d_ff_Yn[58]), .C0(n2175), .C1(d_ff_Xn[58]), .Y(n2225) );
AOI222X1TS U1586 ( .A0(n2229), .A1(data_output[57]), .B0(n2228), .B1(
d_ff_Yn[57]), .C0(n2091), .C1(d_ff_Xn[57]), .Y(n2224) );
AOI222X1TS U1587 ( .A0(n2229), .A1(data_output[56]), .B0(n2228), .B1(
d_ff_Yn[56]), .C0(n2108), .C1(d_ff_Xn[56]), .Y(n2223) );
AOI222X1TS U1588 ( .A0(n2221), .A1(data_output[55]), .B0(n2228), .B1(
d_ff_Yn[55]), .C0(n2200), .C1(d_ff_Xn[55]), .Y(n2222) );
AOI222X1TS U1589 ( .A0(n2229), .A1(data_output[54]), .B0(n2228), .B1(
d_ff_Yn[54]), .C0(n2189), .C1(d_ff_Xn[54]), .Y(n2220) );
AOI222X1TS U1590 ( .A0(n2221), .A1(data_output[53]), .B0(n2218), .B1(
d_ff_Yn[53]), .C0(n2216), .C1(d_ff_Xn[53]), .Y(n2219) );
AOI222X1TS U1591 ( .A0(n2229), .A1(data_output[62]), .B0(n2228), .B1(
d_ff_Yn[62]), .C0(n2227), .C1(d_ff_Xn[62]), .Y(n2163) );
AOI222X1TS U1592 ( .A0(n2229), .A1(data_output[61]), .B0(n2228), .B1(
d_ff_Yn[61]), .C0(n2175), .C1(d_ff_Xn[61]), .Y(n2162) );
AOI222X4TS U1593 ( .A0(n2362), .A1(d_ff2_Y[7]), .B0(n2636), .B1(d_ff2_X[7]),
.C0(d_ff2_Z[7]), .C1(n2366), .Y(n2363) );
AOI222X1TS U1594 ( .A0(n2324), .A1(d_ff2_Y[14]), .B0(n2636), .B1(d_ff2_X[14]), .C0(d_ff2_Z[14]), .C1(n2316), .Y(n2303) );
AOI222X4TS U1595 ( .A0(n2312), .A1(d_ff2_Y[10]), .B0(n2317), .B1(d_ff2_X[10]), .C0(d_ff2_Z[10]), .C1(n2608), .Y(n2299) );
AOI222X1TS U1596 ( .A0(n2312), .A1(d_ff2_Y[8]), .B0(n2636), .B1(d_ff2_X[8]),
.C0(d_ff2_Z[8]), .C1(n2608), .Y(n2297) );
AOI222X4TS U1597 ( .A0(n2504), .A1(d_ff2_Z[59]), .B0(n2020), .B1(d_ff1_Z[59]), .C0(d_ff_Zn[59]), .C1(n2260), .Y(n2261) );
AOI222X4TS U1598 ( .A0(n2431), .A1(d_ff2_Z[58]), .B0(n2014), .B1(d_ff1_Z[58]), .C0(d_ff_Zn[58]), .C1(n2260), .Y(n2259) );
AOI222X4TS U1599 ( .A0(n2431), .A1(d_ff2_Z[57]), .B0(n2016), .B1(d_ff1_Z[57]), .C0(d_ff_Zn[57]), .C1(n2260), .Y(n2258) );
AOI222X4TS U1600 ( .A0(n2256), .A1(d_ff2_Z[56]), .B0(n2014), .B1(d_ff1_Z[56]), .C0(d_ff_Zn[56]), .C1(n2260), .Y(n2257) );
AOI222X4TS U1601 ( .A0(n2543), .A1(d_ff2_Z[26]), .B0(n2018), .B1(d_ff1_Z[26]), .C0(d_ff_Zn[26]), .C1(n2260), .Y(n2149) );
AOI222X4TS U1602 ( .A0(n2022), .A1(d_ff2_Z[31]), .B0(n2016), .B1(d_ff1_Z[31]), .C0(d_ff_Zn[31]), .C1(n2260), .Y(n2130) );
AOI222X4TS U1603 ( .A0(n2022), .A1(d_ff2_Z[32]), .B0(n2124), .B1(d_ff1_Z[32]), .C0(d_ff_Zn[32]), .C1(n2260), .Y(n2127) );
AOI222X4TS U1604 ( .A0(n2022), .A1(d_ff2_Z[33]), .B0(n2124), .B1(d_ff1_Z[33]), .C0(d_ff_Zn[33]), .C1(n2260), .Y(n2125) );
AOI222X4TS U1605 ( .A0(n2022), .A1(d_ff2_Z[34]), .B0(n2016), .B1(d_ff1_Z[34]), .C0(d_ff_Zn[34]), .C1(n2260), .Y(n2121) );
NOR3X2TS U1606 ( .A(d_ff2_X[57]), .B(d_ff2_X[56]), .C(n2676), .Y(n2583) );
NOR3X2TS U1607 ( .A(d_ff2_Y[57]), .B(d_ff2_Y[56]), .C(n2656), .Y(n2532) );
AOI222X4TS U1608 ( .A0(n2543), .A1(d_ff2_Z[10]), .B0(n2124), .B1(d_ff1_Z[10]), .C0(d_ff_Zn[10]), .C1(n2157), .Y(n2123) );
AOI222X4TS U1609 ( .A0(n2022), .A1(d_ff2_Z[35]), .B0(n2020), .B1(d_ff1_Z[35]), .C0(d_ff_Zn[35]), .C1(n2260), .Y(n2119) );
AOI222X4TS U1610 ( .A0(n2139), .A1(d_ff2_Z[7]), .B0(n2016), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n2157), .Y(n2118) );
AOI222X1TS U1611 ( .A0(n2543), .A1(d_ff2_Z[4]), .B0(n2018), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n2254), .Y(n2112) );
AOI222X1TS U1612 ( .A0(n2113), .A1(d_ff2_Z[39]), .B0(n2018), .B1(d_ff1_Z[39]), .C0(d_ff_Zn[39]), .C1(n2134), .Y(n2106) );
AOI222X1TS U1613 ( .A0(n2113), .A1(d_ff2_Z[43]), .B0(n2016), .B1(d_ff1_Z[43]), .C0(d_ff_Zn[43]), .C1(n2556), .Y(n2088) );
NOR3XLTS U1614 ( .A(cont_iter_out[1]), .B(n2431), .C(n2241), .Y(n2066) );
AOI222X1TS U1615 ( .A0(n2086), .A1(data_output[12]), .B0(n2101), .B1(
d_ff_Yn[12]), .C0(n2227), .C1(d_ff_Xn[12]), .Y(n2064) );
AOI222X1TS U1616 ( .A0(n2086), .A1(data_output[7]), .B0(n2101), .B1(
d_ff_Yn[7]), .C0(n2175), .C1(d_ff_Xn[7]), .Y(n2072) );
AOI222X1TS U1617 ( .A0(n2086), .A1(data_output[9]), .B0(n2101), .B1(
d_ff_Yn[9]), .C0(n2091), .C1(d_ff_Xn[9]), .Y(n2076) );
AOI222X1TS U1618 ( .A0(n2086), .A1(data_output[10]), .B0(n2101), .B1(
d_ff_Yn[10]), .C0(n2108), .C1(d_ff_Xn[10]), .Y(n2079) );
AOI222X1TS U1619 ( .A0(n2086), .A1(data_output[5]), .B0(n2101), .B1(
d_ff_Yn[5]), .C0(n2200), .C1(d_ff_Xn[5]), .Y(n2087) );
AOI222X1TS U1620 ( .A0(n2061), .A1(data_output[4]), .B0(n2101), .B1(
d_ff_Yn[4]), .C0(n2189), .C1(d_ff_Xn[4]), .Y(n2089) );
CLKBUFX3TS U1621 ( .A(n2179), .Y(n2101) );
AOI222X1TS U1622 ( .A0(n2426), .A1(d_ff3_sh_x_out[15]), .B0(n2421), .B1(
d_ff3_sh_y_out[15]), .C0(d_ff3_LUT_out[15]), .C1(n2411), .Y(n2403) );
AOI222X1TS U1623 ( .A0(n2426), .A1(d_ff3_sh_x_out[11]), .B0(n2425), .B1(
d_ff3_sh_y_out[11]), .C0(d_ff3_LUT_out[11]), .C1(n2411), .Y(n2408) );
AOI222X1TS U1624 ( .A0(n2426), .A1(d_ff3_sh_x_out[8]), .B0(n2421), .B1(
d_ff3_sh_y_out[8]), .C0(d_ff3_LUT_out[8]), .C1(n2424), .Y(n2413) );
AOI222X1TS U1625 ( .A0(n2426), .A1(d_ff3_sh_x_out[5]), .B0(n2425), .B1(
d_ff3_sh_y_out[5]), .C0(d_ff3_LUT_out[5]), .C1(n2424), .Y(n2416) );
AOI222X1TS U1626 ( .A0(n2426), .A1(d_ff3_sh_x_out[3]), .B0(n2425), .B1(
d_ff3_sh_y_out[3]), .C0(d_ff3_LUT_out[3]), .C1(n2424), .Y(n2419) );
CLKBUFX3TS U1627 ( .A(n2600), .Y(n2426) );
CLKBUFX3TS U1628 ( .A(n2433), .Y(n2480) );
CLKBUFX3TS U1629 ( .A(n2444), .Y(n2529) );
BUFX3TS U1630 ( .A(n2788), .Y(n2782) );
CLKBUFX3TS U1631 ( .A(n2035), .Y(n2793) );
CLKBUFX3TS U1632 ( .A(n2674), .Y(n2670) );
BUFX4TS U1633 ( .A(clk), .Y(n2795) );
NOR3X4TS U1634 ( .A(inst_CORDIC_FSM_v3_state_reg[7]), .B(n2685), .C(n2042),
.Y(enab_cont_iter) );
CLKBUFX2TS U1635 ( .A(n2616), .Y(n2032) );
CLKBUFX3TS U1636 ( .A(n2616), .Y(n2033) );
NOR3X4TS U1637 ( .A(n2430), .B(n2683), .C(n2013), .Y(n2489) );
CLKBUFX3TS U1638 ( .A(n2657), .Y(n2430) );
OAI21XLTS U1639 ( .A0(n2686), .A1(n2271), .B0(n2252), .Y(n1504) );
OAI211XLTS U1640 ( .A0(n2251), .A1(n2247), .B0(n2246), .C0(n2245), .Y(n1522)
);
OAI21XLTS U1641 ( .A0(n2704), .A1(n2465), .B0(n2286), .Y(n1321) );
OAI211XLTS U1642 ( .A0(n2646), .A1(n2451), .B0(n2097), .C0(n2096), .Y(n1539)
);
OAI21XLTS U1643 ( .A0(n2706), .A1(n2033), .B0(n2407), .Y(add_subt_dataB[12])
);
OAI21XLTS U1644 ( .A0(n2032), .A1(n2691), .B0(n2387), .Y(add_subt_dataB[28])
);
OAI21XLTS U1645 ( .A0(n2032), .A1(n2713), .B0(n2374), .Y(add_subt_dataB[41])
);
OAI211XLTS U1646 ( .A0(n2702), .A1(n2365), .B0(n2610), .C0(n2364), .Y(
add_subt_dataB[61]) );
OAI21XLTS U1647 ( .A0(n2627), .A1(n2690), .B0(n2352), .Y(add_subt_dataA[52])
);
NAND3BX2TS U1648 ( .AN(inst_CORDIC_FSM_v3_state_reg[1]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(n2267), .Y(n2256) );
CLKBUFX2TS U1649 ( .A(n2035), .Y(n2788) );
CLKBUFX2TS U1650 ( .A(n2788), .Y(n2785) );
BUFX3TS U1651 ( .A(n2784), .Y(n2765) );
BUFX3TS U1652 ( .A(n2784), .Y(n2766) );
BUFX3TS U1653 ( .A(n2719), .Y(n2778) );
BUFX3TS U1654 ( .A(n2784), .Y(n2767) );
BUFX3TS U1655 ( .A(n2779), .Y(n2777) );
CLKBUFX2TS U1656 ( .A(n2788), .Y(n2787) );
CLKBUFX2TS U1657 ( .A(n2790), .Y(n2783) );
BUFX3TS U1658 ( .A(n2038), .Y(n2772) );
BUFX3TS U1659 ( .A(n2759), .Y(n2771) );
BUFX3TS U1660 ( .A(n2784), .Y(n2770) );
BUFX3TS U1661 ( .A(n2787), .Y(n2769) );
BUFX3TS U1662 ( .A(n2779), .Y(n2764) );
BUFX3TS U1663 ( .A(n2793), .Y(n2768) );
BUFX3TS U1664 ( .A(n2781), .Y(n2776) );
BUFX3TS U1665 ( .A(n2036), .Y(n2743) );
BUFX3TS U1666 ( .A(n2036), .Y(n2742) );
BUFX3TS U1667 ( .A(n2036), .Y(n2741) );
BUFX3TS U1668 ( .A(n2791), .Y(n2740) );
BUFX3TS U1669 ( .A(n2793), .Y(n2775) );
BUFX3TS U1670 ( .A(n2791), .Y(n2739) );
BUFX3TS U1671 ( .A(n2753), .Y(n2744) );
BUFX3TS U1672 ( .A(n2788), .Y(n2779) );
BUFX3TS U1673 ( .A(n2719), .Y(n2745) );
BUFX3TS U1674 ( .A(n2793), .Y(n2755) );
BUFX3TS U1675 ( .A(n2793), .Y(n2756) );
BUFX3TS U1676 ( .A(n2036), .Y(n2757) );
BUFX3TS U1677 ( .A(n2035), .Y(n2730) );
BUFX3TS U1678 ( .A(n2036), .Y(n2729) );
BUFX3TS U1679 ( .A(n2788), .Y(n2753) );
BUFX3TS U1680 ( .A(n2782), .Y(n2758) );
BUFX3TS U1681 ( .A(n2789), .Y(n2752) );
BUFX3TS U1682 ( .A(n2790), .Y(n2759) );
BUFX3TS U1683 ( .A(n2037), .Y(n2722) );
BUFX3TS U1684 ( .A(n2745), .Y(n2734) );
BUFX3TS U1685 ( .A(n2784), .Y(n2732) );
BUFX3TS U1686 ( .A(n2037), .Y(n2721) );
BUFX3TS U1687 ( .A(n2789), .Y(n2750) );
BUFX3TS U1688 ( .A(n2793), .Y(n2749) );
BUFX3TS U1689 ( .A(n2037), .Y(n2720) );
BUFX3TS U1690 ( .A(n2036), .Y(n2735) );
BUFX3TS U1691 ( .A(n2790), .Y(n2731) );
BUFX3TS U1692 ( .A(n2793), .Y(n2754) );
BUFX3TS U1693 ( .A(n2745), .Y(n2724) );
BUFX3TS U1694 ( .A(n2744), .Y(n2723) );
BUFX3TS U1695 ( .A(n2746), .Y(n2726) );
BUFX3TS U1696 ( .A(n2787), .Y(n2763) );
BUFX3TS U1697 ( .A(n2793), .Y(n2747) );
BUFX3TS U1698 ( .A(n2737), .Y(n2725) );
BUFX3TS U1699 ( .A(n2788), .Y(n2719) );
BUFX3TS U1700 ( .A(n2737), .Y(n2774) );
BUFX3TS U1701 ( .A(n2037), .Y(n2718) );
BUFX3TS U1702 ( .A(n2789), .Y(n2728) );
BUFX3TS U1703 ( .A(n2744), .Y(n2733) );
BUFX3TS U1704 ( .A(n2038), .Y(n2773) );
BUFX3TS U1705 ( .A(n2793), .Y(n2736) );
BUFX3TS U1706 ( .A(n2037), .Y(n2748) );
BUFX3TS U1707 ( .A(n2759), .Y(n2780) );
BUFX3TS U1708 ( .A(n2789), .Y(n2751) );
BUFX3TS U1709 ( .A(n2779), .Y(n2737) );
BUFX3TS U1710 ( .A(n2791), .Y(n2738) );
BUFX3TS U1711 ( .A(n2787), .Y(n2746) );
BUFX3TS U1712 ( .A(n2786), .Y(n2727) );
NAND3XLTS U1713 ( .A(n2041), .B(n2697), .C(n2685), .Y(n2039) );
OR4X2TS U1714 ( .A(inst_CORDIC_FSM_v3_state_reg[1]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(n2716), .D(n2039), .Y(n2444) );
CLKBUFX2TS U1715 ( .A(n2444), .Y(n2466) );
CLKBUFX3TS U1716 ( .A(n2466), .Y(n2538) );
INVX2TS U1717 ( .A(n2265), .Y(n2491) );
CLKBUFX3TS U1718 ( .A(n2444), .Y(n2647) );
OAI2BB2XLTS U1719 ( .B0(n2430), .B1(n2491), .A0N(n2647), .A1N(
d_ff3_LUT_out[37]), .Y(n1514) );
CLKBUFX2TS U1720 ( .A(n2717), .Y(n2674) );
NOR2X1TS U1721 ( .A(n2011), .B(cont_iter_out[3]), .Y(n2272) );
INVX2TS U1722 ( .A(n2272), .Y(n2141) );
INVX2TS U1723 ( .A(n2648), .Y(n2241) );
OAI21XLTS U1724 ( .A0(n2241), .A1(cont_iter_out[1]), .B0(n2021), .Y(n2040)
);
CLKBUFX2TS U1725 ( .A(n2040), .Y(n2671) );
CLKBUFX2TS U1726 ( .A(n2668), .Y(n2669) );
OA22X1TS U1727 ( .A0(n2663), .A1(d_ff2_X[58]), .B0(d_ff_Xn[58]), .B1(n2673),
.Y(n1198) );
OA22X1TS U1728 ( .A0(n2670), .A1(d_ff2_X[60]), .B0(d_ff_Xn[60]), .B1(n2665),
.Y(n1196) );
NOR3X1TS U1729 ( .A(inst_CORDIC_FSM_v3_state_reg[1]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(inst_CORDIC_FSM_v3_state_reg[3]),
.Y(n2057) );
NAND2X1TS U1730 ( .A(n2057), .B(n2041), .Y(n2042) );
NOR3X2TS U1731 ( .A(inst_CORDIC_FSM_v3_state_reg[6]), .B(n2697), .C(n2042),
.Y(ready_cordic) );
INVX2TS U1732 ( .A(ready_cordic), .Y(n2277) );
NAND2X2TS U1733 ( .A(cont_iter_out[2]), .B(cont_iter_out[3]), .Y(n2643) );
NAND2X1TS U1734 ( .A(n2644), .B(cont_iter_out[0]), .Y(n2652) );
NOR2X4TS U1735 ( .A(n2434), .B(cont_iter_out[1]), .Y(n2642) );
NAND2X2TS U1736 ( .A(n2009), .B(n2642), .Y(n2250) );
INVX2TS U1737 ( .A(n2250), .Y(n2485) );
NOR2X2TS U1738 ( .A(n2687), .B(cont_iter_out[2]), .Y(n2251) );
INVX2TS U1739 ( .A(n2251), .Y(n2488) );
AOI22X1TS U1740 ( .A0(n2485), .A1(n2488), .B0(d_ff3_LUT_out[3]), .B1(n2538),
.Y(n2043) );
NAND2X1TS U1741 ( .A(n2009), .B(n2023), .Y(n2247) );
INVX2TS U1742 ( .A(n2247), .Y(n2232) );
NAND2X1TS U1743 ( .A(n2232), .B(n2643), .Y(n2093) );
OAI211XLTS U1744 ( .A0(n2011), .A1(n2652), .B0(n2043), .C0(n2093), .Y(n1546)
);
CLKBUFX3TS U1745 ( .A(n2670), .Y(n2046) );
OA22X1TS U1746 ( .A0(d_ff_Xn[46]), .A1(n2673), .B0(n2046), .B1(d_ff2_X[46]),
.Y(n1216) );
OA22X1TS U1747 ( .A0(d_ff_Xn[48]), .A1(n2673), .B0(n2046), .B1(d_ff2_X[48]),
.Y(n1212) );
OA22X1TS U1748 ( .A0(d_ff_Xn[49]), .A1(n2666), .B0(n2046), .B1(d_ff2_X[49]),
.Y(n1210) );
INVX2TS U1749 ( .A(n2023), .Y(n2589) );
CLKBUFX3TS U1750 ( .A(n2466), .Y(n2657) );
AOI22X1TS U1751 ( .A0(n2679), .A1(n2491), .B0(d_ff3_LUT_out[19]), .B1(n2657),
.Y(n2044) );
NAND2X2TS U1752 ( .A(n2643), .B(n2141), .Y(n2287) );
INVX2TS U1753 ( .A(n2238), .Y(n2289) );
OAI211XLTS U1754 ( .A0(cont_iter_out[3]), .A1(n2589), .B0(n2044), .C0(n2289),
.Y(n1530) );
INVX2TS U1755 ( .A(n2657), .Y(n2662) );
OAI21X1TS U1756 ( .A0(n2683), .A1(n2009), .B0(n2662), .Y(n2137) );
INVX2TS U1757 ( .A(n2137), .Y(n2490) );
CLKBUFX3TS U1758 ( .A(n2538), .Y(n2677) );
AOI22X1TS U1759 ( .A0(n2490), .A1(n2687), .B0(d_ff3_LUT_out[55]), .B1(n2677),
.Y(n2045) );
NAND2X1TS U1760 ( .A(n2489), .B(n2287), .Y(n2245) );
NAND2X1TS U1761 ( .A(n2045), .B(n2245), .Y(n1503) );
CLKBUFX3TS U1762 ( .A(n2668), .Y(n2673) );
OA22X1TS U1763 ( .A0(n2021), .A1(d_ff2_X[61]), .B0(d_ff_Xn[61]), .B1(n2673),
.Y(n1195) );
OA22X1TS U1764 ( .A0(n2664), .A1(d_ff2_X[59]), .B0(d_ff_Xn[59]), .B1(n2666),
.Y(n1197) );
OA22X1TS U1765 ( .A0(d_ff_Xn[53]), .A1(n2666), .B0(n2046), .B1(d_ff2_X[53]),
.Y(n1203) );
CLKBUFX2TS U1766 ( .A(n2671), .Y(n2667) );
OA22X1TS U1767 ( .A0(d_ff_Xn[55]), .A1(n2667), .B0(n2046), .B1(d_ff2_X[55]),
.Y(n1201) );
OA22X1TS U1768 ( .A0(d_ff_Xn[54]), .A1(n2665), .B0(n2046), .B1(d_ff2_X[54]),
.Y(n1202) );
OA22X1TS U1769 ( .A0(d_ff_Xn[31]), .A1(n2668), .B0(n2670), .B1(d_ff2_X[31]),
.Y(n1246) );
OA22X1TS U1770 ( .A0(d_ff_Xn[0]), .A1(n2666), .B0(n2046), .B1(d_ff2_X[0]),
.Y(n1308) );
OA22X1TS U1771 ( .A0(d_ff_Xn[19]), .A1(n2671), .B0(n2664), .B1(d_ff2_X[19]),
.Y(n1270) );
OA22X1TS U1772 ( .A0(d_ff_Xn[43]), .A1(n2668), .B0(n2021), .B1(d_ff2_X[43]),
.Y(n1222) );
OA22X1TS U1773 ( .A0(d_ff_Xn[41]), .A1(n2673), .B0(n2046), .B1(d_ff2_X[41]),
.Y(n1226) );
OA22X1TS U1774 ( .A0(d_ff_Xn[45]), .A1(n2665), .B0(n2046), .B1(d_ff2_X[45]),
.Y(n1218) );
OA22X1TS U1775 ( .A0(d_ff_Xn[42]), .A1(n2665), .B0(n2046), .B1(d_ff2_X[42]),
.Y(n1224) );
CLKBUFX2TS U1776 ( .A(clk), .Y(n2054) );
CLKBUFX2TS U1777 ( .A(clk), .Y(n2052) );
BUFX3TS U1778 ( .A(n2825), .Y(n2816) );
CLKBUFX2TS U1779 ( .A(clk), .Y(n2056) );
BUFX3TS U1780 ( .A(n2052), .Y(n2802) );
BUFX3TS U1781 ( .A(n2055), .Y(n2822) );
BUFX3TS U1782 ( .A(n2055), .Y(n2811) );
NOR2X1TS U1783 ( .A(inst_CORDIC_FSM_v3_state_reg[0]), .B(n2274), .Y(n2058)
);
NAND3BX1TS U1784 ( .AN(inst_CORDIC_FSM_v3_state_reg[5]), .B(n2058), .C(
inst_CORDIC_FSM_v3_state_reg[4]), .Y(n2617) );
NAND3BX1TS U1785 ( .AN(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(n2058), .Y(n2618) );
NAND2X1TS U1786 ( .A(n2617), .B(n2618), .Y(beg_add_subt) );
BUFX3TS U1787 ( .A(n2786), .Y(n2762) );
BUFX3TS U1788 ( .A(n2786), .Y(n2760) );
BUFX3TS U1789 ( .A(n2786), .Y(n2761) );
NAND2X1TS U1790 ( .A(n2642), .B(n2265), .Y(n2059) );
OAI211XLTS U1791 ( .A0(n2144), .A1(n2712), .B0(n2268), .C0(n2059), .Y(n1527)
);
AOI21X1TS U1792 ( .A0(enab_cont_iter), .A1(n2654), .B0(ready_cordic), .Y(
n2062) );
CLKBUFX2TS U1793 ( .A(n2062), .Y(n2205) );
CLKBUFX2TS U1794 ( .A(n2205), .Y(n2061) );
CLKBUFX3TS U1795 ( .A(n2061), .Y(n2086) );
XOR2XLTS U1796 ( .A(n2681), .B(d_ff1_operation_out), .Y(n2060) );
XOR2X1TS U1797 ( .A(n2684), .B(n2060), .Y(n2063) );
NOR2BX1TS U1798 ( .AN(n2063), .B(n2061), .Y(n2160) );
CLKBUFX2TS U1799 ( .A(n2160), .Y(n2206) );
CLKBUFX3TS U1800 ( .A(n2206), .Y(n2179) );
CLKBUFX3TS U1801 ( .A(n2062), .Y(n2229) );
OR2X2TS U1802 ( .A(n2229), .B(n2063), .Y(n2167) );
INVX2TS U1803 ( .A(n2167), .Y(n2091) );
INVX2TS U1804 ( .A(n2064), .Y(n1601) );
AOI222X1TS U1805 ( .A0(n2086), .A1(data_output[8]), .B0(n2179), .B1(
d_ff_Yn[8]), .C0(n2216), .C1(d_ff_Xn[8]), .Y(n2065) );
INVX2TS U1806 ( .A(n2065), .Y(n1605) );
INVX2TS U1807 ( .A(n2067), .Y(n1453) );
INVX2TS U1808 ( .A(n2068), .Y(n1451) );
INVX2TS U1809 ( .A(n2664), .Y(n2504) );
INVX2TS U1810 ( .A(n2069), .Y(n1452) );
INVX2TS U1811 ( .A(n2167), .Y(n2175) );
AOI222X1TS U1812 ( .A0(n2086), .A1(data_output[13]), .B0(n2179), .B1(
d_ff_Yn[13]), .C0(n2091), .C1(d_ff_Xn[13]), .Y(n2070) );
INVX2TS U1813 ( .A(n2070), .Y(n1600) );
INVX2TS U1814 ( .A(n2071), .Y(n1455) );
NAND2X1TS U1815 ( .A(n2644), .B(n2141), .Y(n2138) );
INVX2TS U1816 ( .A(n2642), .Y(n2588) );
OAI211XLTS U1817 ( .A0(n2679), .A1(n2714), .B0(n2138), .C0(n2588), .Y(n1509)
);
INVX2TS U1818 ( .A(n2072), .Y(n1606) );
INVX2TS U1819 ( .A(n2073), .Y(n1446) );
CLKBUFX3TS U1820 ( .A(n2179), .Y(n2177) );
AOI222X1TS U1821 ( .A0(n2086), .A1(data_output[14]), .B0(n2177), .B1(
d_ff_Yn[14]), .C0(n2175), .C1(d_ff_Xn[14]), .Y(n2074) );
INVX2TS U1822 ( .A(n2074), .Y(n1599) );
NAND2X1TS U1823 ( .A(n2023), .B(n2141), .Y(n2105) );
OAI211XLTS U1824 ( .A0(n2144), .A1(n2711), .B0(n2268), .C0(n2105), .Y(n1529)
);
INVX2TS U1825 ( .A(n2075), .Y(n1450) );
INVX2TS U1826 ( .A(n2489), .Y(n2271) );
OAI211XLTS U1827 ( .A0(n2679), .A1(n2715), .B0(n2271), .C0(n2250), .Y(n1505)
);
INVX2TS U1828 ( .A(n2076), .Y(n1604) );
NAND2X1TS U1829 ( .A(n2642), .B(n2452), .Y(n2077) );
NOR2X2TS U1830 ( .A(cont_iter_out[0]), .B(cont_iter_out[3]), .Y(n2285) );
NAND2X1TS U1831 ( .A(n2499), .B(n2265), .Y(n2248) );
OAI211XLTS U1832 ( .A0(n2144), .A1(n2710), .B0(n2077), .C0(n2248), .Y(n1515)
);
INVX2TS U1833 ( .A(n2078), .Y(n1456) );
INVX2TS U1834 ( .A(n2079), .Y(n1603) );
INVX2TS U1835 ( .A(n2080), .Y(n1447) );
AOI222X1TS U1836 ( .A0(n2086), .A1(data_output[6]), .B0(n2179), .B1(
d_ff_Yn[6]), .C0(n2189), .C1(d_ff_Xn[6]), .Y(n2081) );
INVX2TS U1837 ( .A(n2081), .Y(n1607) );
AOI222X1TS U1838 ( .A0(n2086), .A1(data_output[11]), .B0(n2179), .B1(
d_ff_Yn[11]), .C0(n2200), .C1(d_ff_Xn[11]), .Y(n2082) );
INVX2TS U1839 ( .A(n2082), .Y(n1602) );
INVX2TS U1840 ( .A(n2083), .Y(n1454) );
CLKBUFX3TS U1841 ( .A(n2205), .Y(n2180) );
AOI222X1TS U1842 ( .A0(n2180), .A1(data_output[15]), .B0(n2177), .B1(
d_ff_Yn[15]), .C0(n2227), .C1(d_ff_Xn[15]), .Y(n2084) );
INVX2TS U1843 ( .A(n2084), .Y(n1598) );
INVX2TS U1844 ( .A(n2085), .Y(n1457) );
OAI211XLTS U1845 ( .A0(n2679), .A1(n2713), .B0(n2268), .C0(n2155), .Y(n1512)
);
INVX2TS U1846 ( .A(n2087), .Y(n1608) );
AOI22X1TS U1847 ( .A0(n2011), .A1(n2642), .B0(n2232), .B1(n2287), .Y(n2496)
);
NAND2X1TS U1848 ( .A(n2489), .B(n2265), .Y(n2097) );
OAI211XLTS U1849 ( .A0(n2144), .A1(n2709), .B0(n2496), .C0(n2097), .Y(n1519)
);
INVX2TS U1850 ( .A(n2088), .Y(n1458) );
INVX2TS U1851 ( .A(n2089), .Y(n1609) );
NAND2X1TS U1852 ( .A(n2642), .B(n2241), .Y(n2104) );
OAI211XLTS U1853 ( .A0(n2144), .A1(n2708), .B0(n2155), .C0(n2104), .Y(n1525)
);
INVX2TS U1854 ( .A(n2090), .Y(n1459) );
AOI222X1TS U1855 ( .A0(n2061), .A1(data_output[3]), .B0(n2101), .B1(
d_ff_Yn[3]), .C0(n2108), .C1(d_ff_Xn[3]), .Y(n2092) );
INVX2TS U1856 ( .A(n2092), .Y(n1610) );
OAI211XLTS U1857 ( .A0(n2287), .A1(n2271), .B0(n2094), .C0(n2093), .Y(n1542)
);
INVX2TS U1858 ( .A(n2095), .Y(n1460) );
NOR2X1TS U1859 ( .A(cont_iter_out[3]), .B(n2683), .Y(n2646) );
OAI21X1TS U1860 ( .A0(cont_iter_out[2]), .A1(n2285), .B0(n2644), .Y(n2451)
);
CLKBUFX3TS U1861 ( .A(n2657), .Y(n2649) );
NAND2X1TS U1862 ( .A(d_ff3_LUT_out[10]), .B(n2649), .Y(n2096) );
OR2X1TS U1863 ( .A(n2285), .B(n2588), .Y(n2154) );
OAI211XLTS U1864 ( .A0(n2144), .A1(n2707), .B0(n2105), .C0(n2154), .Y(n1533)
);
INVX2TS U1865 ( .A(n2167), .Y(n2108) );
AOI222X1TS U1866 ( .A0(n2061), .A1(data_output[2]), .B0(n2179), .B1(
d_ff_Yn[2]), .C0(n2091), .C1(d_ff_Xn[2]), .Y(n2098) );
INVX2TS U1867 ( .A(n2098), .Y(n1611) );
INVX2TS U1868 ( .A(n2099), .Y(n1461) );
INVX2TS U1869 ( .A(n2100), .Y(n1501) );
AOI222X1TS U1870 ( .A0(n2061), .A1(data_output[1]), .B0(n2101), .B1(
d_ff_Yn[1]), .C0(n2175), .C1(d_ff_Xn[1]), .Y(n2102) );
INVX2TS U1871 ( .A(n2102), .Y(n1612) );
INVX2TS U1872 ( .A(n2103), .Y(n1500) );
OAI211XLTS U1873 ( .A0(n2144), .A1(n2706), .B0(n2105), .C0(n2104), .Y(n1537)
);
INVX2TS U1874 ( .A(n2106), .Y(n1462) );
INVX2TS U1875 ( .A(n2021), .Y(n2547) );
INVX2TS U1876 ( .A(n2107), .Y(n1499) );
AOI222X1TS U1877 ( .A0(n2205), .A1(data_output[0]), .B0(d_ff_Yn[0]), .B1(
n2179), .C0(d_ff_Xn[0]), .C1(n2216), .Y(n2109) );
INVX2TS U1878 ( .A(n2109), .Y(n1613) );
INVX2TS U1879 ( .A(n2110), .Y(n1498) );
INVX2TS U1880 ( .A(n2111), .Y(n1463) );
INVX2TS U1881 ( .A(n2112), .Y(n1497) );
INVX2TS U1882 ( .A(n2114), .Y(n1464) );
INVX2TS U1883 ( .A(n2115), .Y(n1496) );
INVX2TS U1884 ( .A(n2116), .Y(n1465) );
INVX2TS U1885 ( .A(n2117), .Y(n1495) );
INVX2TS U1886 ( .A(n2118), .Y(n1494) );
INVX2TS U1887 ( .A(n2665), .Y(n2260) );
INVX2TS U1888 ( .A(n2119), .Y(n1466) );
INVX2TS U1889 ( .A(n2663), .Y(n2139) );
INVX2TS U1890 ( .A(n2120), .Y(n1493) );
INVX2TS U1891 ( .A(n2121), .Y(n1467) );
INVX2TS U1892 ( .A(n2122), .Y(n1492) );
INVX2TS U1893 ( .A(n2123), .Y(n1491) );
INVX2TS U1894 ( .A(n2125), .Y(n1468) );
INVX2TS U1895 ( .A(n2126), .Y(n1490) );
NAND2X1TS U1896 ( .A(n2689), .B(cont_var_out[1]), .Y(n2606) );
INVX2TS U1897 ( .A(n2606), .Y(n2600) );
CLKBUFX3TS U1898 ( .A(n2600), .Y(n2630) );
NAND2X1TS U1899 ( .A(n2634), .B(ready_add_subt), .Y(n2448) );
CLKBUFX2TS U1900 ( .A(n2448), .Y(n2454) );
NOR2XLTS U1901 ( .A(n2618), .B(n2459), .Y(inst_CORDIC_FSM_v3_state_next[6])
);
INVX2TS U1902 ( .A(n2127), .Y(n1469) );
INVX2TS U1903 ( .A(n2128), .Y(n1489) );
INVX2TS U1904 ( .A(n2129), .Y(n1488) );
INVX2TS U1905 ( .A(n2130), .Y(n1470) );
INVX2TS U1906 ( .A(n2131), .Y(n1487) );
INVX2TS U1907 ( .A(n2132), .Y(n1471) );
INVX2TS U1908 ( .A(n2133), .Y(n1486) );
INVX2TS U1909 ( .A(n2135), .Y(n1485) );
INVX2TS U1910 ( .A(n2136), .Y(n1472) );
OAI211XLTS U1911 ( .A0(n2144), .A1(n2699), .B0(n2138), .C0(n2137), .Y(n1518)
);
INVX2TS U1912 ( .A(n2140), .Y(n1484) );
OAI21X1TS U1913 ( .A0(cont_iter_out[1]), .A1(n2141), .B0(n2644), .Y(n2650)
);
NAND2X1TS U1914 ( .A(n2644), .B(n2009), .Y(n2465) );
OAI211XLTS U1915 ( .A0(n2144), .A1(n2691), .B0(n2650), .C0(n2465), .Y(n1521)
);
INVX2TS U1916 ( .A(n2142), .Y(n1473) );
INVX2TS U1917 ( .A(n2143), .Y(n1483) );
NAND2X1TS U1918 ( .A(n2644), .B(n2497), .Y(n2645) );
OAI211XLTS U1919 ( .A0(n2144), .A1(n2698), .B0(n2645), .C0(n2155), .Y(n1545)
);
INVX2TS U1920 ( .A(n2145), .Y(n1482) );
INVX2TS U1921 ( .A(n2147), .Y(n1474) );
INVX2TS U1922 ( .A(n2148), .Y(n1481) );
INVX2TS U1923 ( .A(n2149), .Y(n1475) );
INVX2TS U1924 ( .A(n2150), .Y(n1480) );
INVX2TS U1925 ( .A(n2152), .Y(n1476) );
INVX2TS U1926 ( .A(n2153), .Y(n1479) );
OAI211XLTS U1927 ( .A0(n2679), .A1(n2696), .B0(n2155), .C0(n2154), .Y(n1516)
);
INVX2TS U1928 ( .A(n2156), .Y(n1478) );
INVX2TS U1929 ( .A(n2159), .Y(n1477) );
CLKBUFX2TS U1930 ( .A(n2160), .Y(n2161) );
CLKBUFX3TS U1931 ( .A(n2161), .Y(n2228) );
INVX2TS U1932 ( .A(n2167), .Y(n2227) );
INVX2TS U1933 ( .A(n2162), .Y(n1552) );
INVX2TS U1934 ( .A(n2163), .Y(n1551) );
XNOR2X1TS U1935 ( .A(n2164), .B(d_ff_Xn[63]), .Y(n2168) );
AOI22X1TS U1936 ( .A0(n2229), .A1(data_output[63]), .B0(n2228), .B1(n2165),
.Y(n2166) );
OAI21XLTS U1937 ( .A0(n2168), .A1(n2167), .B0(n2166), .Y(n1550) );
AOI222X1TS U1938 ( .A0(n2180), .A1(data_output[16]), .B0(n2177), .B1(
d_ff_Yn[16]), .C0(n2216), .C1(d_ff_Xn[16]), .Y(n2169) );
INVX2TS U1939 ( .A(n2169), .Y(n1597) );
AOI222X1TS U1940 ( .A0(n2180), .A1(data_output[17]), .B0(n2177), .B1(
d_ff_Yn[17]), .C0(n2189), .C1(d_ff_Xn[17]), .Y(n2170) );
INVX2TS U1941 ( .A(n2170), .Y(n1596) );
AOI222X1TS U1942 ( .A0(n2180), .A1(data_output[18]), .B0(n2177), .B1(
d_ff_Yn[18]), .C0(n2200), .C1(d_ff_Xn[18]), .Y(n2171) );
INVX2TS U1943 ( .A(n2171), .Y(n1595) );
AOI222X1TS U1944 ( .A0(n2180), .A1(data_output[19]), .B0(n2177), .B1(
d_ff_Yn[19]), .C0(n2108), .C1(d_ff_Xn[19]), .Y(n2172) );
INVX2TS U1945 ( .A(n2172), .Y(n1594) );
AOI222X1TS U1946 ( .A0(n2180), .A1(data_output[20]), .B0(n2177), .B1(
d_ff_Yn[20]), .C0(n2091), .C1(d_ff_Xn[20]), .Y(n2173) );
INVX2TS U1947 ( .A(n2173), .Y(n1593) );
AOI222X1TS U1948 ( .A0(n2180), .A1(data_output[21]), .B0(n2177), .B1(
d_ff_Yn[21]), .C0(n2175), .C1(d_ff_Xn[21]), .Y(n2174) );
INVX2TS U1949 ( .A(n2174), .Y(n1592) );
AOI222X1TS U1950 ( .A0(n2180), .A1(data_output[22]), .B0(n2177), .B1(
d_ff_Yn[22]), .C0(n2227), .C1(d_ff_Xn[22]), .Y(n2176) );
INVX2TS U1951 ( .A(n2176), .Y(n1591) );
INVX2TS U1952 ( .A(n2167), .Y(n2189) );
AOI222X1TS U1953 ( .A0(n2180), .A1(data_output[23]), .B0(n2177), .B1(
d_ff_Yn[23]), .C0(n2200), .C1(d_ff_Xn[23]), .Y(n2178) );
INVX2TS U1954 ( .A(n2178), .Y(n1590) );
AOI222X1TS U1955 ( .A0(n2180), .A1(data_output[24]), .B0(n2161), .B1(
d_ff_Yn[24]), .C0(n2108), .C1(d_ff_Xn[24]), .Y(n2181) );
INVX2TS U1956 ( .A(n2181), .Y(n1589) );
CLKBUFX3TS U1957 ( .A(n2205), .Y(n2210) );
AOI222X1TS U1958 ( .A0(n2210), .A1(data_output[25]), .B0(n2161), .B1(
d_ff_Yn[25]), .C0(n2091), .C1(d_ff_Xn[25]), .Y(n2182) );
INVX2TS U1959 ( .A(n2182), .Y(n1588) );
AOI222X1TS U1960 ( .A0(n2210), .A1(data_output[26]), .B0(n2206), .B1(
d_ff_Yn[26]), .C0(n2175), .C1(d_ff_Xn[26]), .Y(n2183) );
INVX2TS U1961 ( .A(n2183), .Y(n1587) );
AOI222X1TS U1962 ( .A0(n2210), .A1(data_output[27]), .B0(n2161), .B1(
d_ff_Yn[27]), .C0(n2227), .C1(d_ff_Xn[27]), .Y(n2184) );
INVX2TS U1963 ( .A(n2184), .Y(n1586) );
AOI222X1TS U1964 ( .A0(n2210), .A1(data_output[28]), .B0(n2206), .B1(
d_ff_Yn[28]), .C0(n2216), .C1(d_ff_Xn[28]), .Y(n2185) );
INVX2TS U1965 ( .A(n2185), .Y(n1585) );
AOI222X1TS U1966 ( .A0(n2210), .A1(data_output[29]), .B0(n2161), .B1(
d_ff_Yn[29]), .C0(n2189), .C1(d_ff_Xn[29]), .Y(n2186) );
INVX2TS U1967 ( .A(n2186), .Y(n1584) );
AOI222X1TS U1968 ( .A0(n2210), .A1(data_output[30]), .B0(n2206), .B1(
d_ff_Yn[30]), .C0(n2200), .C1(d_ff_Xn[30]), .Y(n2187) );
INVX2TS U1969 ( .A(n2187), .Y(n1583) );
AOI222X1TS U1970 ( .A0(n2210), .A1(data_output[31]), .B0(n2161), .B1(
d_ff_Yn[31]), .C0(n2108), .C1(d_ff_Xn[31]), .Y(n2188) );
INVX2TS U1971 ( .A(n2188), .Y(n1582) );
AOI222X1TS U1972 ( .A0(n2210), .A1(data_output[32]), .B0(n2179), .B1(
d_ff_Yn[32]), .C0(n2091), .C1(d_ff_Xn[32]), .Y(n2190) );
INVX2TS U1973 ( .A(n2190), .Y(n1581) );
INVX2TS U1974 ( .A(n2167), .Y(n2200) );
AOI222X1TS U1975 ( .A0(n2210), .A1(data_output[33]), .B0(n2179), .B1(
d_ff_Yn[33]), .C0(n2227), .C1(d_ff_Xn[33]), .Y(n2191) );
INVX2TS U1976 ( .A(n2191), .Y(n1580) );
CLKBUFX3TS U1977 ( .A(n2205), .Y(n2203) );
CLKBUFX3TS U1978 ( .A(n2206), .Y(n2202) );
AOI222X1TS U1979 ( .A0(n2203), .A1(data_output[34]), .B0(n2202), .B1(
d_ff_Yn[34]), .C0(n2216), .C1(d_ff_Xn[34]), .Y(n2192) );
INVX2TS U1980 ( .A(n2192), .Y(n1579) );
AOI222X1TS U1981 ( .A0(n2203), .A1(data_output[35]), .B0(n2202), .B1(
d_ff_Yn[35]), .C0(n2189), .C1(d_ff_Xn[35]), .Y(n2193) );
INVX2TS U1982 ( .A(n2193), .Y(n1578) );
AOI222X1TS U1983 ( .A0(n2203), .A1(data_output[36]), .B0(n2202), .B1(
d_ff_Yn[36]), .C0(n2200), .C1(d_ff_Xn[36]), .Y(n2194) );
INVX2TS U1984 ( .A(n2194), .Y(n1577) );
AOI222X1TS U1985 ( .A0(n2203), .A1(data_output[37]), .B0(n2202), .B1(
d_ff_Yn[37]), .C0(n2108), .C1(d_ff_Xn[37]), .Y(n2195) );
INVX2TS U1986 ( .A(n2195), .Y(n1576) );
AOI222X1TS U1987 ( .A0(n2203), .A1(data_output[38]), .B0(n2202), .B1(
d_ff_Yn[38]), .C0(n2091), .C1(d_ff_Xn[38]), .Y(n2196) );
INVX2TS U1988 ( .A(n2196), .Y(n1575) );
AOI222X1TS U1989 ( .A0(n2203), .A1(data_output[39]), .B0(n2202), .B1(
d_ff_Yn[39]), .C0(n2175), .C1(d_ff_Xn[39]), .Y(n2197) );
INVX2TS U1990 ( .A(n2197), .Y(n1574) );
AOI222X1TS U1991 ( .A0(n2203), .A1(data_output[40]), .B0(n2202), .B1(
d_ff_Yn[40]), .C0(n2227), .C1(d_ff_Xn[40]), .Y(n2198) );
INVX2TS U1992 ( .A(n2198), .Y(n1573) );
AOI222X1TS U1993 ( .A0(n2203), .A1(data_output[41]), .B0(n2202), .B1(
d_ff_Yn[41]), .C0(n2216), .C1(d_ff_Xn[41]), .Y(n2199) );
INVX2TS U1994 ( .A(n2199), .Y(n1572) );
AOI222X1TS U1995 ( .A0(n2203), .A1(data_output[42]), .B0(n2202), .B1(
d_ff_Yn[42]), .C0(n2189), .C1(d_ff_Xn[42]), .Y(n2201) );
INVX2TS U1996 ( .A(n2201), .Y(n1571) );
INVX2TS U1997 ( .A(n2167), .Y(n2216) );
AOI222X1TS U1998 ( .A0(n2203), .A1(data_output[43]), .B0(n2202), .B1(
d_ff_Yn[43]), .C0(n2189), .C1(d_ff_Xn[43]), .Y(n2204) );
INVX2TS U1999 ( .A(n2204), .Y(n1570) );
CLKBUFX3TS U2000 ( .A(n2205), .Y(n2221) );
CLKBUFX3TS U2001 ( .A(n2206), .Y(n2218) );
AOI222X1TS U2002 ( .A0(n2221), .A1(data_output[44]), .B0(n2218), .B1(
d_ff_Yn[44]), .C0(n2200), .C1(d_ff_Xn[44]), .Y(n2207) );
INVX2TS U2003 ( .A(n2207), .Y(n1569) );
AOI222X1TS U2004 ( .A0(n2221), .A1(data_output[45]), .B0(n2218), .B1(
d_ff_Yn[45]), .C0(n2108), .C1(d_ff_Xn[45]), .Y(n2208) );
INVX2TS U2005 ( .A(n2208), .Y(n1568) );
AOI222X1TS U2006 ( .A0(n2221), .A1(data_output[46]), .B0(n2218), .B1(
d_ff_Yn[46]), .C0(n2091), .C1(d_ff_Xn[46]), .Y(n2209) );
INVX2TS U2007 ( .A(n2209), .Y(n1567) );
AOI222X1TS U2008 ( .A0(n2210), .A1(data_output[47]), .B0(n2218), .B1(
d_ff_Yn[47]), .C0(n2175), .C1(d_ff_Xn[47]), .Y(n2211) );
INVX2TS U2009 ( .A(n2211), .Y(n1566) );
AOI222X1TS U2010 ( .A0(n2221), .A1(data_output[48]), .B0(n2218), .B1(
d_ff_Yn[48]), .C0(n2227), .C1(d_ff_Xn[48]), .Y(n2212) );
INVX2TS U2011 ( .A(n2212), .Y(n1565) );
AOI222X1TS U2012 ( .A0(n2221), .A1(data_output[49]), .B0(n2218), .B1(
d_ff_Yn[49]), .C0(n2216), .C1(d_ff_Xn[49]), .Y(n2213) );
INVX2TS U2013 ( .A(n2213), .Y(n1564) );
AOI222X1TS U2014 ( .A0(n2221), .A1(data_output[50]), .B0(n2218), .B1(
d_ff_Yn[50]), .C0(n2189), .C1(d_ff_Xn[50]), .Y(n2214) );
INVX2TS U2015 ( .A(n2214), .Y(n1563) );
AOI222X1TS U2016 ( .A0(n2221), .A1(data_output[51]), .B0(n2218), .B1(
d_ff_Yn[51]), .C0(n2200), .C1(d_ff_Xn[51]), .Y(n2215) );
INVX2TS U2017 ( .A(n2215), .Y(n1562) );
AOI222X1TS U2018 ( .A0(n2221), .A1(data_output[52]), .B0(n2218), .B1(
d_ff_Yn[52]), .C0(n2108), .C1(d_ff_Xn[52]), .Y(n2217) );
INVX2TS U2019 ( .A(n2217), .Y(n1561) );
INVX2TS U2020 ( .A(n2219), .Y(n1560) );
INVX2TS U2021 ( .A(n2220), .Y(n1559) );
INVX2TS U2022 ( .A(n2222), .Y(n1558) );
INVX2TS U2023 ( .A(n2223), .Y(n1557) );
INVX2TS U2024 ( .A(n2224), .Y(n1556) );
INVX2TS U2025 ( .A(n2225), .Y(n1555) );
INVX2TS U2026 ( .A(n2226), .Y(n1554) );
INVX2TS U2027 ( .A(n2230), .Y(n1553) );
AOI22X1TS U2028 ( .A0(n2499), .A1(n2012), .B0(d_ff3_LUT_out[5]), .B1(n2657),
.Y(n2231) );
OAI21XLTS U2029 ( .A0(n2588), .A1(n2287), .B0(n2231), .Y(n1544) );
AOI22X1TS U2030 ( .A0(n2489), .A1(n2687), .B0(d_ff3_LUT_out[9]), .B1(n2538),
.Y(n2234) );
INVX2TS U2031 ( .A(n2287), .Y(n2486) );
AOI22X1TS U2032 ( .A0(n2232), .A1(n2486), .B0(n2288), .B1(n2643), .Y(n2233)
);
OAI211XLTS U2033 ( .A0(n2250), .A1(n2488), .B0(n2234), .C0(n2233), .Y(n1540)
);
AOI22X1TS U2034 ( .A0(n2489), .A1(n2687), .B0(d_ff3_LUT_out[11]), .B1(n2657),
.Y(n2236) );
AOI22X1TS U2035 ( .A0(n2485), .A1(n2643), .B0(n2288), .B1(n2012), .Y(n2235)
);
OAI211XLTS U2036 ( .A0(n2488), .A1(n2247), .B0(n2236), .C0(n2235), .Y(n1538)
);
AOI22X1TS U2037 ( .A0(n2490), .A1(n2011), .B0(d_ff3_LUT_out[14]), .B1(n2538),
.Y(n2237) );
OAI21XLTS U2038 ( .A0(n2687), .A1(n2589), .B0(n2237), .Y(n1535) );
AOI22X1TS U2039 ( .A0(n2489), .A1(n2491), .B0(d_ff3_LUT_out[15]), .B1(n2657),
.Y(n2240) );
AOI21X1TS U2040 ( .A0(n2288), .A1(n2686), .B0(n2238), .Y(n2239) );
OAI211XLTS U2041 ( .A0(n2589), .A1(n2241), .B0(n2240), .C0(n2239), .Y(n1534)
);
AOI22X1TS U2042 ( .A0(n2491), .A1(n2023), .B0(d_ff3_LUT_out[17]), .B1(n2430),
.Y(n2242) );
OAI21XLTS U2043 ( .A0(n2250), .A1(n2488), .B0(n2242), .Y(n1532) );
AOI22X1TS U2044 ( .A0(n2452), .A1(n2642), .B0(d_ff3_LUT_out[18]), .B1(n2460),
.Y(n2243) );
OAI21XLTS U2045 ( .A0(n2491), .A1(n2589), .B0(n2243), .Y(n1531) );
AOI22X1TS U2046 ( .A0(n2491), .A1(n2642), .B0(d_ff3_LUT_out[25]), .B1(n2538),
.Y(n2244) );
OAI211XLTS U2047 ( .A0(n2247), .A1(n2686), .B0(n2244), .C0(n2245), .Y(n1524)
);
AOI22X1TS U2048 ( .A0(n2288), .A1(cont_iter_out[2]), .B0(d_ff3_LUT_out[27]),
.B1(n2677), .Y(n2246) );
AOI22X1TS U2049 ( .A0(n2288), .A1(n2287), .B0(d_ff3_LUT_out[33]), .B1(n2677),
.Y(n2249) );
OAI211XLTS U2050 ( .A0(n2251), .A1(n2250), .B0(n2249), .C0(n2248), .Y(n1517)
);
AOI22X1TS U2051 ( .A0(n2490), .A1(n2012), .B0(d_ff3_LUT_out[54]), .B1(n2677),
.Y(n2252) );
AOI222X1TS U2052 ( .A0(n2256), .A1(d_ff2_Z[52]), .B0(n2019), .B1(d_ff1_Z[52]), .C0(d_ff_Zn[52]), .C1(n2254), .Y(n2253) );
INVX2TS U2053 ( .A(n2253), .Y(n1449) );
AOI222X1TS U2054 ( .A0(n2431), .A1(d_ff2_Z[53]), .B0(n2019), .B1(d_ff1_Z[53]), .C0(d_ff_Zn[53]), .C1(n2254), .Y(n2255) );
INVX2TS U2055 ( .A(n2255), .Y(n1448) );
INVX2TS U2056 ( .A(n2257), .Y(n1445) );
INVX2TS U2057 ( .A(n2258), .Y(n1444) );
INVX2TS U2058 ( .A(n2259), .Y(n1443) );
INVX2TS U2059 ( .A(n2261), .Y(n1442) );
AOI222X1TS U2060 ( .A0(n2431), .A1(d_ff2_Z[60]), .B0(n2019), .B1(d_ff1_Z[60]), .C0(d_ff_Zn[60]), .C1(n2279), .Y(n2262) );
INVX2TS U2061 ( .A(n2262), .Y(n1441) );
AOI222X1TS U2062 ( .A0(n2431), .A1(d_ff2_Z[61]), .B0(n2019), .B1(d_ff1_Z[61]), .C0(d_ff_Zn[61]), .C1(n2279), .Y(n2263) );
INVX2TS U2063 ( .A(n2263), .Y(n1440) );
AOI222X1TS U2064 ( .A0(n2431), .A1(d_ff2_Z[62]), .B0(n2019), .B1(d_ff1_Z[62]), .C0(d_ff_Zn[62]), .C1(n2279), .Y(n2264) );
INVX2TS U2065 ( .A(n2264), .Y(n1439) );
AOI22X1TS U2066 ( .A0(n2023), .A1(n2265), .B0(d_ff3_LUT_out[2]), .B1(n2460),
.Y(n2266) );
OAI211XLTS U2067 ( .A0(n2285), .A1(n2588), .B0(n2266), .C0(n2271), .Y(n1547)
);
INVX2TS U2068 ( .A(enab_cont_iter), .Y(n2638) );
NAND3BXLTS U2069 ( .AN(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[1]), .C(n2267), .Y(n2275) );
OAI21XLTS U2070 ( .A0(n2654), .A1(n2638), .B0(n2275), .Y(
inst_CORDIC_FSM_v3_state_next[2]) );
INVX2TS U2071 ( .A(n2032), .Y(n2326) );
CLKBUFX3TS U2072 ( .A(n2326), .Y(n2633) );
OAI21XLTS U2073 ( .A0(n2633), .A1(n2617), .B0(n2649), .Y(
inst_CORDIC_FSM_v3_state_next[4]) );
INVX2TS U2074 ( .A(n2268), .Y(n2269) );
AOI21X1TS U2075 ( .A0(cont_iter_out[0]), .A1(n2491), .B0(n2588), .Y(n2283)
);
AOI211XLTS U2076 ( .A0(d_ff3_LUT_out[26]), .A1(n2466), .B0(n2269), .C0(n2283), .Y(n2270) );
OAI21XLTS U2077 ( .A0(n2272), .A1(n2271), .B0(n2270), .Y(n1523) );
NOR2XLTS U2078 ( .A(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .Y(n2273) );
NAND3BX1TS U2079 ( .AN(n2274), .B(n2273), .C(inst_CORDIC_FSM_v3_state_reg[0]), .Y(n2615) );
NAND2X1TS U2080 ( .A(n2275), .B(n2615), .Y(n2433) );
INVX2TS U2081 ( .A(n2640), .Y(n2471) );
NOR4X1TS U2082 ( .A(n2664), .B(n2644), .C(enab_cont_iter), .D(beg_add_subt),
.Y(n2276) );
AOI32X1TS U2083 ( .A0(n2471), .A1(n2277), .A2(n2276), .B0(ready_cordic),
.B1(ack_cordic), .Y(n2278) );
OAI21XLTS U2084 ( .A0(beg_fsm_cordic), .A1(n2615), .B0(n2278), .Y(
inst_CORDIC_FSM_v3_state_next[0]) );
AOI222X1TS U2085 ( .A0(n2431), .A1(d_ff2_Z[63]), .B0(n2019), .B1(d_ff1_Z[63]), .C0(d_ff_Zn[63]), .C1(n2279), .Y(n2280) );
INVX2TS U2086 ( .A(n2280), .Y(n1438) );
NOR2XLTS U2087 ( .A(n2689), .B(cont_var_out[1]), .Y(n2281) );
INVX2TS U2088 ( .A(n2281), .Y(n2605) );
CLKBUFX2TS U2089 ( .A(n2605), .Y(n2399) );
NOR3BX2TS U2090 ( .AN(n2617), .B(enab_cont_iter), .C(ready_add_subt), .Y(
n2432) );
AOI21X1TS U2091 ( .A0(n2432), .A1(cont_var_out[1]), .B0(n2409), .Y(n2282) );
OAI21XLTS U2092 ( .A0(n2399), .A1(n2432), .B0(n2282), .Y(n1878) );
AOI21X1TS U2093 ( .A0(d_ff3_LUT_out[8]), .A1(n2649), .B0(n2283), .Y(n2284)
);
OAI31X1TS U2094 ( .A0(n2491), .A1(n2285), .A2(n2430), .B0(n2284), .Y(n1541)
);
NOR2X2TS U2095 ( .A(d_ff2_Y[52]), .B(n2009), .Y(n2586) );
AOI22X1TS U2096 ( .A0(n2679), .A1(n2586), .B0(d_ff3_sh_y_out[52]), .B1(n2677), .Y(n2286) );
AOI22X1TS U2097 ( .A0(n2288), .A1(n2287), .B0(d_ff3_LUT_out[1]), .B1(n2449),
.Y(n2290) );
OAI211XLTS U2098 ( .A0(n2497), .A1(n2589), .B0(n2290), .C0(n2289), .Y(n1548)
);
CLKBUFX3TS U2099 ( .A(n2426), .Y(n2422) );
CLKBUFX3TS U2100 ( .A(n2422), .Y(n2312) );
CLKBUFX2TS U2101 ( .A(n2605), .Y(n2365) );
CLKBUFX3TS U2102 ( .A(n2326), .Y(n2366) );
INVX2TS U2103 ( .A(n2291), .Y(add_subt_dataA[2]) );
CLKBUFX3TS U2104 ( .A(n2634), .Y(n2362) );
CLKBUFX3TS U2105 ( .A(n2326), .Y(n2608) );
INVX2TS U2106 ( .A(n2292), .Y(add_subt_dataA[3]) );
INVX2TS U2107 ( .A(n2293), .Y(add_subt_dataA[1]) );
INVX2TS U2108 ( .A(n2294), .Y(add_subt_dataA[5]) );
CLKBUFX3TS U2109 ( .A(n2326), .Y(n2316) );
INVX2TS U2110 ( .A(n2295), .Y(add_subt_dataA[6]) );
INVX2TS U2111 ( .A(n2296), .Y(add_subt_dataA[4]) );
INVX2TS U2112 ( .A(n2297), .Y(add_subt_dataA[8]) );
INVX2TS U2113 ( .A(n2298), .Y(add_subt_dataA[9]) );
INVX2TS U2114 ( .A(n2299), .Y(add_subt_dataA[10]) );
INVX2TS U2115 ( .A(n2300), .Y(add_subt_dataA[11]) );
INVX2TS U2116 ( .A(n2301), .Y(add_subt_dataA[12]) );
INVX2TS U2117 ( .A(n2302), .Y(add_subt_dataA[13]) );
CLKBUFX3TS U2118 ( .A(n2422), .Y(n2324) );
INVX2TS U2119 ( .A(n2303), .Y(add_subt_dataA[14]) );
INVX2TS U2120 ( .A(n2304), .Y(add_subt_dataA[15]) );
CLKBUFX3TS U2121 ( .A(n2326), .Y(n2328) );
INVX2TS U2122 ( .A(n2305), .Y(add_subt_dataA[16]) );
INVX2TS U2123 ( .A(n2306), .Y(add_subt_dataA[17]) );
INVX2TS U2124 ( .A(n2307), .Y(add_subt_dataA[18]) );
INVX2TS U2125 ( .A(n2308), .Y(add_subt_dataA[19]) );
INVX2TS U2126 ( .A(n2309), .Y(add_subt_dataA[20]) );
INVX2TS U2127 ( .A(n2310), .Y(add_subt_dataA[21]) );
INVX2TS U2128 ( .A(n2311), .Y(add_subt_dataA[22]) );
INVX2TS U2129 ( .A(n2313), .Y(add_subt_dataA[23]) );
CLKBUFX2TS U2130 ( .A(n2409), .Y(n2599) );
INVX2TS U2131 ( .A(n2314), .Y(add_subt_dataA[24]) );
INVX2TS U2132 ( .A(n2315), .Y(add_subt_dataA[25]) );
INVX2TS U2133 ( .A(n2318), .Y(add_subt_dataA[26]) );
CLKBUFX2TS U2134 ( .A(n2605), .Y(n2627) );
INVX2TS U2135 ( .A(n2627), .Y(n2333) );
INVX2TS U2136 ( .A(n2319), .Y(add_subt_dataA[27]) );
INVX2TS U2137 ( .A(n2320), .Y(add_subt_dataA[28]) );
INVX2TS U2138 ( .A(n2627), .Y(n2344) );
INVX2TS U2139 ( .A(n2321), .Y(add_subt_dataA[29]) );
INVX2TS U2140 ( .A(n2322), .Y(add_subt_dataA[30]) );
CLKBUFX3TS U2141 ( .A(n2599), .Y(n2348) );
INVX2TS U2142 ( .A(n2323), .Y(add_subt_dataA[31]) );
INVX2TS U2143 ( .A(n2325), .Y(add_subt_dataA[32]) );
CLKBUFX3TS U2144 ( .A(n2326), .Y(n2339) );
INVX2TS U2145 ( .A(n2327), .Y(add_subt_dataA[0]) );
INVX2TS U2146 ( .A(n2329), .Y(add_subt_dataA[33]) );
INVX2TS U2147 ( .A(n2330), .Y(add_subt_dataA[34]) );
AOI222X1TS U2148 ( .A0(n2634), .A1(d_ff2_Y[35]), .B0(n2333), .B1(d_ff2_X[35]), .C0(d_ff2_Z[35]), .C1(n2339), .Y(n2331) );
INVX2TS U2149 ( .A(n2331), .Y(add_subt_dataA[35]) );
INVX2TS U2150 ( .A(n2332), .Y(add_subt_dataA[36]) );
INVX2TS U2151 ( .A(n2334), .Y(add_subt_dataA[37]) );
INVX2TS U2152 ( .A(n2335), .Y(add_subt_dataA[38]) );
INVX2TS U2153 ( .A(n2336), .Y(add_subt_dataA[39]) );
INVX2TS U2154 ( .A(n2337), .Y(add_subt_dataA[40]) );
INVX2TS U2155 ( .A(n2338), .Y(add_subt_dataA[41]) );
INVX2TS U2156 ( .A(n2340), .Y(add_subt_dataA[42]) );
CLKBUFX3TS U2157 ( .A(n2326), .Y(n2354) );
INVX2TS U2158 ( .A(n2341), .Y(add_subt_dataA[43]) );
INVX2TS U2159 ( .A(n2342), .Y(add_subt_dataA[44]) );
INVX2TS U2160 ( .A(n2343), .Y(add_subt_dataA[45]) );
INVX2TS U2161 ( .A(n2345), .Y(add_subt_dataA[46]) );
INVX2TS U2162 ( .A(n2346), .Y(add_subt_dataA[47]) );
INVX2TS U2163 ( .A(n2347), .Y(add_subt_dataA[48]) );
INVX2TS U2164 ( .A(n2349), .Y(add_subt_dataA[49]) );
INVX2TS U2165 ( .A(n2350), .Y(add_subt_dataA[50]) );
INVX2TS U2166 ( .A(n2351), .Y(add_subt_dataA[51]) );
AOI22X1TS U2167 ( .A0(d_ff2_Y[52]), .A1(n2634), .B0(d_ff2_Z[52]), .B1(n2633),
.Y(n2352) );
AOI22X1TS U2168 ( .A0(n2620), .A1(d_ff2_X[53]), .B0(d_ff2_Z[53]), .B1(n2633),
.Y(n2353) );
OAI21XLTS U2169 ( .A0(n2688), .A1(n2606), .B0(n2353), .Y(add_subt_dataA[53])
);
INVX2TS U2170 ( .A(n2355), .Y(add_subt_dataA[54]) );
CLKBUFX3TS U2171 ( .A(n2326), .Y(n2424) );
INVX2TS U2172 ( .A(n2356), .Y(add_subt_dataA[55]) );
AOI22X1TS U2173 ( .A0(d_ff2_Y[57]), .A1(n2630), .B0(d_ff2_Z[57]), .B1(n2633),
.Y(n2357) );
OAI21XLTS U2174 ( .A0(n2700), .A1(n2605), .B0(n2357), .Y(add_subt_dataA[57])
);
AOI22X1TS U2175 ( .A0(d_ff2_Y[58]), .A1(n2630), .B0(d_ff2_Z[58]), .B1(n2633),
.Y(n2358) );
OAI21XLTS U2176 ( .A0(n2692), .A1(n2399), .B0(n2358), .Y(add_subt_dataA[58])
);
AOI22X1TS U2177 ( .A0(d_ff2_Y[60]), .A1(n2409), .B0(d_ff2_Z[60]), .B1(n2633),
.Y(n2359) );
OAI21XLTS U2178 ( .A0(n2693), .A1(n2627), .B0(n2359), .Y(add_subt_dataA[60])
);
AOI222X1TS U2179 ( .A0(n2600), .A1(d_ff2_Y[63]), .B0(n2425), .B1(d_ff2_X[63]), .C0(d_ff2_Z[63]), .C1(n2424), .Y(n2360) );
INVX2TS U2180 ( .A(n2360), .Y(add_subt_dataA[63]) );
INVX2TS U2181 ( .A(n2363), .Y(add_subt_dataA[7]) );
NAND2X2TS U2182 ( .A(n2608), .B(d_ff3_LUT_out[48]), .Y(n2610) );
NAND2X1TS U2183 ( .A(n2600), .B(d_ff3_sh_x_out[61]), .Y(n2364) );
AOI222X1TS U2184 ( .A0(n2599), .A1(d_ff3_sh_x_out[55]), .B0(n2494), .B1(
d_ff3_sh_y_out[55]), .C0(d_ff3_LUT_out[55]), .C1(n2366), .Y(n2367) );
INVX2TS U2185 ( .A(n2367), .Y(add_subt_dataB[55]) );
INVX2TS U2186 ( .A(n2368), .Y(add_subt_dataB[54]) );
AOI22X1TS U2187 ( .A0(d_ff3_sh_y_out[53]), .A1(n2620), .B0(n2630), .B1(
d_ff3_sh_x_out[53]), .Y(n2369) );
OAI21XLTS U2188 ( .A0(n2032), .A1(n2715), .B0(n2369), .Y(add_subt_dataB[53])
);
AOI222X1TS U2189 ( .A0(n2599), .A1(d_ff3_sh_x_out[52]), .B0(n2494), .B1(
d_ff3_sh_y_out[52]), .C0(n2608), .C1(d_ff3_LUT_out[52]), .Y(n2370) );
INVX2TS U2190 ( .A(n2370), .Y(add_subt_dataB[52]) );
AOI22X1TS U2191 ( .A0(n2621), .A1(d_ff3_sh_x_out[50]), .B0(n2401), .B1(
d_ff3_sh_y_out[50]), .Y(n2371) );
OAI21XLTS U2192 ( .A0(n2032), .A1(n2703), .B0(n2371), .Y(add_subt_dataB[50])
);
AOI22X1TS U2193 ( .A0(n2621), .A1(d_ff3_sh_x_out[45]), .B0(n2620), .B1(
d_ff3_sh_y_out[45]), .Y(n2372) );
OAI21XLTS U2194 ( .A0(n2616), .A1(n2714), .B0(n2372), .Y(add_subt_dataB[45])
);
CLKBUFX3TS U2195 ( .A(n2409), .Y(n2624) );
AOI22X1TS U2196 ( .A0(n2624), .A1(d_ff3_sh_x_out[43]), .B0(n2623), .B1(
d_ff3_sh_y_out[43]), .Y(n2373) );
OAI21XLTS U2197 ( .A0(n2696), .A1(n2616), .B0(n2373), .Y(add_subt_dataB[43])
);
AOI22X1TS U2198 ( .A0(n2624), .A1(d_ff3_sh_x_out[41]), .B0(n2401), .B1(
d_ff3_sh_y_out[41]), .Y(n2374) );
AOI22X1TS U2199 ( .A0(n2624), .A1(d_ff3_sh_x_out[40]), .B0(n2401), .B1(
d_ff3_sh_y_out[40]), .Y(n2375) );
OAI21XLTS U2200 ( .A0(n2033), .A1(n2691), .B0(n2375), .Y(add_subt_dataB[40])
);
INVX2TS U2201 ( .A(n2376), .Y(add_subt_dataB[39]) );
AOI22X1TS U2202 ( .A0(n2624), .A1(d_ff3_sh_x_out[38]), .B0(n2623), .B1(
d_ff3_sh_y_out[38]), .Y(n2377) );
OAI21XLTS U2203 ( .A0(n2616), .A1(n2699), .B0(n2377), .Y(add_subt_dataB[38])
);
CLKBUFX3TS U2204 ( .A(n2634), .Y(n2397) );
AOI222X1TS U2205 ( .A0(n2397), .A1(d_ff3_sh_x_out[37]), .B0(n2494), .B1(
d_ff3_sh_y_out[37]), .C0(n2608), .C1(d_ff3_LUT_out[37]), .Y(n2378) );
INVX2TS U2206 ( .A(n2378), .Y(add_subt_dataB[37]) );
CLKBUFX3TS U2207 ( .A(n2409), .Y(n2417) );
AOI22X1TS U2208 ( .A0(n2417), .A1(d_ff3_sh_x_out[36]), .B0(n2401), .B1(
d_ff3_sh_y_out[36]), .Y(n2379) );
OAI21XLTS U2209 ( .A0(n2033), .A1(n2691), .B0(n2379), .Y(add_subt_dataB[36])
);
AOI22X1TS U2210 ( .A0(n2624), .A1(d_ff3_sh_x_out[35]), .B0(n2623), .B1(
d_ff3_sh_y_out[35]), .Y(n2380) );
OAI21XLTS U2211 ( .A0(n2710), .A1(n2033), .B0(n2380), .Y(add_subt_dataB[35])
);
AOI22X1TS U2212 ( .A0(n2417), .A1(d_ff3_sh_x_out[34]), .B0(n2623), .B1(
d_ff3_sh_y_out[34]), .Y(n2381) );
OAI21XLTS U2213 ( .A0(n2696), .A1(n2616), .B0(n2381), .Y(add_subt_dataB[34])
);
INVX2TS U2214 ( .A(n2382), .Y(add_subt_dataB[33]) );
AOI22X1TS U2215 ( .A0(n2624), .A1(d_ff3_sh_x_out[32]), .B0(n2401), .B1(
d_ff3_sh_y_out[32]), .Y(n2383) );
OAI21XLTS U2216 ( .A0(n2616), .A1(n2699), .B0(n2383), .Y(add_subt_dataB[32])
);
AOI22X1TS U2217 ( .A0(n2417), .A1(d_ff3_sh_x_out[31]), .B0(n2401), .B1(
d_ff3_sh_y_out[31]), .Y(n2384) );
OAI21XLTS U2218 ( .A0(n2709), .A1(n2033), .B0(n2384), .Y(add_subt_dataB[31])
);
AOI22X1TS U2219 ( .A0(n2624), .A1(d_ff3_sh_x_out[30]), .B0(n2623), .B1(
d_ff3_sh_y_out[30]), .Y(n2385) );
OAI21XLTS U2220 ( .A0(n2033), .A1(n2698), .B0(n2385), .Y(add_subt_dataB[30])
);
INVX2TS U2221 ( .A(n2386), .Y(add_subt_dataB[29]) );
AOI22X1TS U2222 ( .A0(n2417), .A1(d_ff3_sh_x_out[28]), .B0(n2623), .B1(
d_ff3_sh_y_out[28]), .Y(n2387) );
INVX2TS U2223 ( .A(n2388), .Y(add_subt_dataB[27]) );
INVX2TS U2224 ( .A(n2389), .Y(add_subt_dataB[26]) );
CLKBUFX3TS U2225 ( .A(n2326), .Y(n2411) );
AOI222X1TS U2226 ( .A0(n2397), .A1(d_ff3_sh_x_out[25]), .B0(n2405), .B1(
d_ff3_sh_y_out[25]), .C0(d_ff3_LUT_out[25]), .C1(n2411), .Y(n2390) );
INVX2TS U2227 ( .A(n2390), .Y(add_subt_dataB[25]) );
AOI22X1TS U2228 ( .A0(n2417), .A1(d_ff3_sh_x_out[24]), .B0(n2401), .B1(
d_ff3_sh_y_out[24]), .Y(n2391) );
OAI21XLTS U2229 ( .A0(n2708), .A1(n2616), .B0(n2391), .Y(add_subt_dataB[24])
);
AOI222X1TS U2230 ( .A0(n2397), .A1(d_ff3_sh_x_out[23]), .B0(n2405), .B1(
d_ff3_sh_y_out[23]), .C0(d_ff3_LUT_out[23]), .C1(n2411), .Y(n2392) );
INVX2TS U2231 ( .A(n2392), .Y(add_subt_dataB[23]) );
AOI22X1TS U2232 ( .A0(n2417), .A1(d_ff3_sh_x_out[22]), .B0(n2623), .B1(
d_ff3_sh_y_out[22]), .Y(n2393) );
OAI21XLTS U2233 ( .A0(n2616), .A1(n2712), .B0(n2393), .Y(add_subt_dataB[22])
);
AOI222X1TS U2234 ( .A0(n2397), .A1(d_ff3_sh_x_out[21]), .B0(n2405), .B1(
d_ff3_sh_y_out[21]), .C0(n2608), .C1(d_ff3_LUT_out[21]), .Y(n2394) );
INVX2TS U2235 ( .A(n2394), .Y(add_subt_dataB[21]) );
AOI22X1TS U2236 ( .A0(n2417), .A1(d_ff3_sh_x_out[20]), .B0(n2401), .B1(
d_ff3_sh_y_out[20]), .Y(n2395) );
OAI21XLTS U2237 ( .A0(n2033), .A1(n2711), .B0(n2395), .Y(add_subt_dataB[20])
);
AOI222X1TS U2238 ( .A0(n2397), .A1(d_ff3_sh_x_out[19]), .B0(n2405), .B1(
d_ff3_sh_y_out[19]), .C0(d_ff3_LUT_out[19]), .C1(n2411), .Y(n2396) );
INVX2TS U2239 ( .A(n2396), .Y(add_subt_dataB[19]) );
AOI222X1TS U2240 ( .A0(n2397), .A1(d_ff3_sh_x_out[18]), .B0(n2405), .B1(
d_ff3_sh_y_out[18]), .C0(d_ff3_LUT_out[18]), .C1(n2411), .Y(n2398) );
INVX2TS U2241 ( .A(n2398), .Y(add_subt_dataB[18]) );
AOI222X1TS U2242 ( .A0(n2422), .A1(d_ff3_sh_x_out[17]), .B0(n2405), .B1(
d_ff3_sh_y_out[17]), .C0(d_ff3_LUT_out[17]), .C1(n2411), .Y(n2400) );
INVX2TS U2243 ( .A(n2400), .Y(add_subt_dataB[17]) );
AOI22X1TS U2244 ( .A0(n2417), .A1(d_ff3_sh_x_out[16]), .B0(n2623), .B1(
d_ff3_sh_y_out[16]), .Y(n2402) );
OAI21XLTS U2245 ( .A0(n2707), .A1(n2033), .B0(n2402), .Y(add_subt_dataB[16])
);
INVX2TS U2246 ( .A(n2403), .Y(add_subt_dataB[15]) );
AOI222X1TS U2247 ( .A0(n2600), .A1(d_ff3_sh_x_out[14]), .B0(n2405), .B1(
d_ff3_sh_y_out[14]), .C0(d_ff3_LUT_out[14]), .C1(n2411), .Y(n2404) );
INVX2TS U2248 ( .A(n2404), .Y(add_subt_dataB[14]) );
AOI222X1TS U2249 ( .A0(n2422), .A1(d_ff3_sh_x_out[13]), .B0(n2405), .B1(
d_ff3_sh_y_out[13]), .C0(n2608), .C1(d_ff3_LUT_out[13]), .Y(n2406) );
INVX2TS U2250 ( .A(n2406), .Y(add_subt_dataB[13]) );
AOI22X1TS U2251 ( .A0(n2417), .A1(d_ff3_sh_x_out[12]), .B0(n2494), .B1(
d_ff3_sh_y_out[12]), .Y(n2407) );
INVX2TS U2252 ( .A(n2408), .Y(add_subt_dataB[11]) );
INVX2TS U2253 ( .A(n2410), .Y(add_subt_dataB[10]) );
AOI222X1TS U2254 ( .A0(n2422), .A1(d_ff3_sh_x_out[9]), .B0(n2405), .B1(
d_ff3_sh_y_out[9]), .C0(d_ff3_LUT_out[9]), .C1(n2411), .Y(n2412) );
INVX2TS U2255 ( .A(n2412), .Y(add_subt_dataB[9]) );
INVX2TS U2256 ( .A(n2413), .Y(add_subt_dataB[8]) );
AOI222X1TS U2257 ( .A0(n2600), .A1(d_ff3_sh_x_out[7]), .B0(n2405), .B1(
d_ff3_sh_y_out[7]), .C0(d_ff3_LUT_out[7]), .C1(n2424), .Y(n2414) );
INVX2TS U2258 ( .A(n2414), .Y(add_subt_dataB[7]) );
AOI222X1TS U2259 ( .A0(n2422), .A1(d_ff3_sh_x_out[6]), .B0(n2425), .B1(
d_ff3_sh_y_out[6]), .C0(d_ff3_LUT_out[6]), .C1(n2424), .Y(n2415) );
INVX2TS U2260 ( .A(n2415), .Y(add_subt_dataB[6]) );
INVX2TS U2261 ( .A(n2416), .Y(add_subt_dataB[5]) );
AOI22X1TS U2262 ( .A0(n2417), .A1(d_ff3_sh_x_out[4]), .B0(n2494), .B1(
d_ff3_sh_y_out[4]), .Y(n2418) );
OAI21XLTS U2263 ( .A0(n2616), .A1(n2698), .B0(n2418), .Y(add_subt_dataB[4])
);
INVX2TS U2264 ( .A(n2419), .Y(add_subt_dataB[3]) );
AOI222X1TS U2265 ( .A0(n2600), .A1(d_ff3_sh_x_out[2]), .B0(n2421), .B1(
d_ff3_sh_y_out[2]), .C0(d_ff3_LUT_out[2]), .C1(n2424), .Y(n2420) );
INVX2TS U2266 ( .A(n2420), .Y(add_subt_dataB[2]) );
AOI222X1TS U2267 ( .A0(n2422), .A1(d_ff3_sh_x_out[1]), .B0(n2421), .B1(
d_ff3_sh_y_out[1]), .C0(d_ff3_LUT_out[1]), .C1(n2424), .Y(n2423) );
INVX2TS U2268 ( .A(n2423), .Y(add_subt_dataB[1]) );
AOI222X1TS U2269 ( .A0(n2426), .A1(d_ff3_sh_x_out[0]), .B0(n2425), .B1(
d_ff3_sh_y_out[0]), .C0(d_ff3_LUT_out[0]), .C1(n2424), .Y(n2427) );
INVX2TS U2270 ( .A(n2427), .Y(add_subt_dataB[0]) );
INVX2TS U2271 ( .A(n2434), .Y(n2548) );
AO22XLTS U2272 ( .A0(n2548), .A1(d_ff2_X[25]), .B0(n2434), .B1(
d_ff3_sh_x_out[25]), .Y(n1257) );
INVX2TS U2273 ( .A(n2449), .Y(n2545) );
AO22XLTS U2274 ( .A0(n2545), .A1(d_ff2_X[19]), .B0(n2460), .B1(
d_ff3_sh_x_out[19]), .Y(n1269) );
INVX2TS U2275 ( .A(n2434), .Y(n2559) );
CLKBUFX3TS U2276 ( .A(n2647), .Y(n2575) );
CLKBUFX3TS U2277 ( .A(n2575), .Y(n2566) );
AO22XLTS U2278 ( .A0(n2559), .A1(d_ff2_X[37]), .B0(n2566), .B1(
d_ff3_sh_x_out[37]), .Y(n1233) );
AO22XLTS U2279 ( .A0(n2559), .A1(d_ff2_X[26]), .B0(n2449), .B1(
d_ff3_sh_x_out[26]), .Y(n1255) );
CLKBUFX3TS U2280 ( .A(n2575), .Y(n2557) );
AO22XLTS U2281 ( .A0(n2559), .A1(d_ff2_X[27]), .B0(n2557), .B1(
d_ff3_sh_x_out[27]), .Y(n1253) );
AO22XLTS U2282 ( .A0(n2548), .A1(d_ff2_X[18]), .B0(n2434), .B1(
d_ff3_sh_x_out[18]), .Y(n1271) );
AO22XLTS U2283 ( .A0(n2548), .A1(d_ff2_X[23]), .B0(n2430), .B1(
d_ff3_sh_x_out[23]), .Y(n1261) );
AO22XLTS U2284 ( .A0(n2548), .A1(d_ff2_X[17]), .B0(n2460), .B1(
d_ff3_sh_x_out[17]), .Y(n1273) );
AO22XLTS U2285 ( .A0(n2559), .A1(d_ff2_X[29]), .B0(n2557), .B1(
d_ff3_sh_x_out[29]), .Y(n1249) );
CLKBUFX3TS U2286 ( .A(n2657), .Y(n2544) );
AO22XLTS U2287 ( .A0(n2548), .A1(d_ff2_X[15]), .B0(n2544), .B1(
d_ff3_sh_x_out[15]), .Y(n1277) );
INVX2TS U2288 ( .A(n2449), .Y(n2577) );
AOI222X1TS U2289 ( .A0(cont_iter_out[1]), .A1(n2586), .B0(cont_iter_out[1]),
.B1(n2688), .C0(n2586), .C1(n2688), .Y(n2438) );
NAND2X1TS U2290 ( .A(n2532), .B(n2694), .Y(n2535) );
OAI21XLTS U2291 ( .A0(n2532), .A1(n2694), .B0(n2535), .Y(n2428) );
AO22XLTS U2292 ( .A0(n2577), .A1(n2428), .B0(n2575), .B1(d_ff3_sh_y_out[58]),
.Y(n1315) );
AO22XLTS U2293 ( .A0(n2548), .A1(d_ff2_X[21]), .B0(n2449), .B1(
d_ff3_sh_x_out[21]), .Y(n1265) );
INVX2TS U2294 ( .A(n2434), .Y(n2579) );
AO22XLTS U2295 ( .A0(n2579), .A1(d_ff2_X[39]), .B0(n2566), .B1(
d_ff3_sh_x_out[39]), .Y(n1229) );
AO22XLTS U2296 ( .A0(n2559), .A1(d_ff2_X[33]), .B0(n2557), .B1(
d_ff3_sh_x_out[33]), .Y(n1241) );
NAND2X1TS U2297 ( .A(cont_iter_out[0]), .B(n2690), .Y(n2593) );
NAND2X1TS U2298 ( .A(n2583), .B(n2692), .Y(n2581) );
NAND2X1TS U2299 ( .A(n2580), .B(n2693), .Y(n2539) );
NOR2X1TS U2300 ( .A(d_ff2_X[61]), .B(n2539), .Y(n2435) );
AOI21X1TS U2301 ( .A0(d_ff2_X[61]), .A1(n2539), .B0(n2435), .Y(n2429) );
INVX2TS U2302 ( .A(n2449), .Y(n2651) );
AOI2BB2XLTS U2303 ( .B0(n2662), .B1(n2429), .A0N(d_ff3_sh_x_out[61]), .A1N(
n2651), .Y(n1184) );
INVX2TS U2304 ( .A(n2455), .Y(n2483) );
AO22XLTS U2305 ( .A0(n2483), .A1(result_add_subt[7]), .B0(n2459), .B1(
d_ff_Zn[7]), .Y(n1798) );
NAND2X1TS U2306 ( .A(cont_iter_out[1]), .B(n2637), .Y(n2567) );
OA21XLTS U2307 ( .A0(cont_iter_out[1]), .A1(n2637), .B0(n2567), .Y(n1876) );
AOI2BB2XLTS U2308 ( .B0(n2504), .B1(n2700), .A0N(d_ff_Xn[57]), .A1N(n2666),
.Y(n1199) );
AOI2BB2XLTS U2309 ( .B0(n2432), .B1(n2689), .A0N(n2689), .A1N(n2432), .Y(
n1873) );
AO22XLTS U2310 ( .A0(n2545), .A1(d_ff2_X[14]), .B0(n2544), .B1(
d_ff3_sh_x_out[14]), .Y(n1279) );
CLKBUFX2TS U2311 ( .A(n2470), .Y(n2472) );
INVX2TS U2312 ( .A(n2472), .Y(n2477) );
AO22XLTS U2313 ( .A0(n2477), .A1(d_ff1_Z[10]), .B0(n2480), .B1(data_in[10]),
.Y(n1859) );
AO22XLTS U2314 ( .A0(n2477), .A1(d_ff1_Z[9]), .B0(n2480), .B1(data_in[9]),
.Y(n1860) );
INVX2TS U2315 ( .A(n2472), .Y(n2478) );
AO22XLTS U2316 ( .A0(n2478), .A1(d_ff1_Z[8]), .B0(n2480), .B1(data_in[8]),
.Y(n1861) );
INVX2TS U2317 ( .A(n2449), .Y(n2541) );
AO22XLTS U2318 ( .A0(n2541), .A1(d_ff2_Y[63]), .B0(n2460), .B1(
d_ff3_sh_y_out[63]), .Y(n1309) );
AO22XLTS U2319 ( .A0(n2478), .A1(d_ff1_Z[7]), .B0(n2470), .B1(data_in[7]),
.Y(n1862) );
AO22XLTS U2320 ( .A0(n2541), .A1(d_ff2_X[63]), .B0(n2444), .B1(
d_ff3_sh_x_out[63]), .Y(n1181) );
CLKBUFX2TS U2321 ( .A(n2433), .Y(n2639) );
AO22XLTS U2322 ( .A0(n2478), .A1(d_ff1_Z[6]), .B0(n2639), .B1(data_in[6]),
.Y(n1863) );
AO22XLTS U2323 ( .A0(n2478), .A1(d_ff1_Z[5]), .B0(n2639), .B1(data_in[5]),
.Y(n1864) );
INVX2TS U2324 ( .A(n2538), .Y(n2596) );
XOR2XLTS U2325 ( .A(d_ff2_X[62]), .B(n2435), .Y(n2436) );
AO22XLTS U2326 ( .A0(n2596), .A1(n2436), .B0(n2449), .B1(d_ff3_sh_x_out[62]),
.Y(n1183) );
AO22XLTS U2327 ( .A0(n2478), .A1(d_ff1_Z[4]), .B0(n2640), .B1(data_in[4]),
.Y(n1865) );
NAND2X1TS U2328 ( .A(n2574), .B(n2695), .Y(n2660) );
NOR2X1TS U2329 ( .A(d_ff2_Y[61]), .B(n2660), .Y(n2659) );
XOR2XLTS U2330 ( .A(d_ff2_Y[62]), .B(n2659), .Y(n2437) );
AO22XLTS U2331 ( .A0(n2541), .A1(n2437), .B0(n2560), .B1(d_ff3_sh_y_out[62]),
.Y(n1311) );
INVX2TS U2332 ( .A(n2472), .Y(n2468) );
AO22XLTS U2333 ( .A0(n2468), .A1(d_ff1_Z[3]), .B0(n2639), .B1(data_in[3]),
.Y(n1866) );
AO22XLTS U2334 ( .A0(n2468), .A1(d_ff1_Z[2]), .B0(n2470), .B1(data_in[2]),
.Y(n1867) );
AO22XLTS U2335 ( .A0(n2468), .A1(d_ff1_Z[1]), .B0(n2639), .B1(data_in[1]),
.Y(n1868) );
AO22XLTS U2336 ( .A0(n2468), .A1(d_ff1_Z[0]), .B0(n2639), .B1(data_in[0]),
.Y(n1869) );
INVX2TS U2337 ( .A(n2459), .Y(n2619) );
AO22XLTS U2338 ( .A0(n2619), .A1(result_add_subt[63]), .B0(n2448), .B1(
d_ff_Zn[63]), .Y(n1742) );
AO22XLTS U2339 ( .A0(n2619), .A1(result_add_subt[62]), .B0(n2454), .B1(
d_ff_Zn[62]), .Y(n1743) );
INVX2TS U2340 ( .A(n2455), .Y(n2456) );
AO22XLTS U2341 ( .A0(n2456), .A1(result_add_subt[0]), .B0(n2455), .B1(
d_ff_Zn[0]), .Y(n1805) );
AO22XLTS U2342 ( .A0(n2619), .A1(result_add_subt[61]), .B0(n2455), .B1(
d_ff_Zn[61]), .Y(n1744) );
AO22XLTS U2343 ( .A0(n2619), .A1(result_add_subt[60]), .B0(n2459), .B1(
d_ff_Zn[60]), .Y(n1745) );
CMPR32X2TS U2344 ( .A(n2012), .B(d_ff2_Y[54]), .C(n2438), .CO(n2440), .S(
n2439) );
AO22XLTS U2345 ( .A0(n2577), .A1(n2439), .B0(n2560), .B1(d_ff3_sh_y_out[54]),
.Y(n1319) );
INVX2TS U2346 ( .A(n2455), .Y(n2458) );
AO22XLTS U2347 ( .A0(n2458), .A1(result_add_subt[59]), .B0(n2455), .B1(
d_ff_Zn[59]), .Y(n1746) );
AO22XLTS U2348 ( .A0(n2577), .A1(n2441), .B0(n2444), .B1(d_ff3_sh_y_out[55]),
.Y(n1318) );
AO22XLTS U2349 ( .A0(n2456), .A1(result_add_subt[58]), .B0(n2454), .B1(
d_ff_Zn[58]), .Y(n1747) );
CLKBUFX3TS U2350 ( .A(n2454), .Y(n2442) );
AO22XLTS U2351 ( .A0(n2456), .A1(result_add_subt[57]), .B0(n2442), .B1(
d_ff_Zn[57]), .Y(n1748) );
INVX2TS U2352 ( .A(n2466), .Y(n2584) );
AO22XLTS U2353 ( .A0(n2584), .A1(d_ff2_Y[0]), .B0(n2529), .B1(
d_ff3_sh_y_out[0]), .Y(n1435) );
AO22XLTS U2354 ( .A0(n2456), .A1(result_add_subt[56]), .B0(n2442), .B1(
d_ff_Zn[56]), .Y(n1749) );
AO22XLTS U2355 ( .A0(n2584), .A1(d_ff2_Y[1]), .B0(n2560), .B1(
d_ff3_sh_y_out[1]), .Y(n1433) );
AO22XLTS U2356 ( .A0(n2456), .A1(result_add_subt[55]), .B0(n2442), .B1(
d_ff_Zn[55]), .Y(n1750) );
AO22XLTS U2357 ( .A0(n2456), .A1(result_add_subt[54]), .B0(n2442), .B1(
d_ff_Zn[54]), .Y(n1751) );
AO22XLTS U2358 ( .A0(n2584), .A1(d_ff2_Y[2]), .B0(n2647), .B1(
d_ff3_sh_y_out[2]), .Y(n1431) );
AO22XLTS U2359 ( .A0(n2456), .A1(result_add_subt[53]), .B0(n2442), .B1(
d_ff_Zn[53]), .Y(n1752) );
AO22XLTS U2360 ( .A0(n2584), .A1(d_ff2_Y[3]), .B0(n2529), .B1(
d_ff3_sh_y_out[3]), .Y(n1429) );
AO22XLTS U2361 ( .A0(n2619), .A1(result_add_subt[52]), .B0(n2442), .B1(
d_ff_Zn[52]), .Y(n1753) );
AO22XLTS U2362 ( .A0(n2619), .A1(result_add_subt[51]), .B0(n2442), .B1(
d_ff_Zn[51]), .Y(n1754) );
AO22XLTS U2363 ( .A0(n2584), .A1(d_ff2_Y[5]), .B0(n2560), .B1(
d_ff3_sh_y_out[5]), .Y(n1425) );
AO22XLTS U2364 ( .A0(n2619), .A1(result_add_subt[50]), .B0(n2442), .B1(
d_ff_Zn[50]), .Y(n1755) );
INVX2TS U2365 ( .A(n2434), .Y(n2573) );
AO22XLTS U2366 ( .A0(n2573), .A1(d_ff2_Y[6]), .B0(n2444), .B1(
d_ff3_sh_y_out[6]), .Y(n1423) );
AO22XLTS U2367 ( .A0(n2619), .A1(result_add_subt[49]), .B0(n2442), .B1(
d_ff_Zn[49]), .Y(n1756) );
INVX2TS U2368 ( .A(n2448), .Y(n2446) );
AO22XLTS U2369 ( .A0(n2446), .A1(result_add_subt[48]), .B0(n2442), .B1(
d_ff_Zn[48]), .Y(n1757) );
AO22XLTS U2370 ( .A0(n2573), .A1(d_ff2_Y[7]), .B0(n2647), .B1(
d_ff3_sh_y_out[7]), .Y(n1421) );
CLKBUFX3TS U2371 ( .A(n2454), .Y(n2443) );
AO22XLTS U2372 ( .A0(n2446), .A1(result_add_subt[47]), .B0(n2443), .B1(
d_ff_Zn[47]), .Y(n1758) );
AO22XLTS U2373 ( .A0(n2573), .A1(d_ff2_Y[8]), .B0(n2647), .B1(
d_ff3_sh_y_out[8]), .Y(n1419) );
AO22XLTS U2374 ( .A0(n2446), .A1(result_add_subt[46]), .B0(n2443), .B1(
d_ff_Zn[46]), .Y(n1759) );
AO22XLTS U2375 ( .A0(n2446), .A1(result_add_subt[45]), .B0(n2443), .B1(
d_ff_Zn[45]), .Y(n1760) );
AO22XLTS U2376 ( .A0(n2573), .A1(d_ff2_Y[9]), .B0(n2444), .B1(
d_ff3_sh_y_out[9]), .Y(n1417) );
AO22XLTS U2377 ( .A0(n2446), .A1(result_add_subt[44]), .B0(n2443), .B1(
d_ff_Zn[44]), .Y(n1761) );
CLKBUFX2TS U2378 ( .A(n2529), .Y(n2653) );
AO22XLTS U2379 ( .A0(n2573), .A1(d_ff2_Y[10]), .B0(n2653), .B1(
d_ff3_sh_y_out[10]), .Y(n1415) );
AO22XLTS U2380 ( .A0(n2446), .A1(result_add_subt[43]), .B0(n2443), .B1(
d_ff_Zn[43]), .Y(n1762) );
INVX2TS U2381 ( .A(n2455), .Y(n2457) );
AO22XLTS U2382 ( .A0(n2457), .A1(result_add_subt[42]), .B0(n2443), .B1(
d_ff_Zn[42]), .Y(n1763) );
AO22XLTS U2383 ( .A0(n2573), .A1(d_ff2_Y[11]), .B0(n2529), .B1(
d_ff3_sh_y_out[11]), .Y(n1413) );
AO22XLTS U2384 ( .A0(n2477), .A1(d_ff1_Z[11]), .B0(n2480), .B1(data_in[11]),
.Y(n1858) );
AO22XLTS U2385 ( .A0(n2457), .A1(result_add_subt[41]), .B0(n2443), .B1(
d_ff_Zn[41]), .Y(n1764) );
AO22XLTS U2386 ( .A0(n2573), .A1(d_ff2_Y[13]), .B0(n2444), .B1(
d_ff3_sh_y_out[13]), .Y(n1409) );
AO22XLTS U2387 ( .A0(n2457), .A1(result_add_subt[40]), .B0(n2443), .B1(
d_ff_Zn[40]), .Y(n1765) );
AO22XLTS U2388 ( .A0(n2457), .A1(result_add_subt[39]), .B0(n2443), .B1(
d_ff_Zn[39]), .Y(n1766) );
AO22XLTS U2389 ( .A0(n2573), .A1(d_ff2_Y[14]), .B0(n2653), .B1(
d_ff3_sh_y_out[14]), .Y(n1407) );
AO22XLTS U2390 ( .A0(n2619), .A1(result_add_subt[38]), .B0(n2443), .B1(
d_ff_Zn[38]), .Y(n1767) );
AO22XLTS U2391 ( .A0(n2573), .A1(d_ff2_Y[15]), .B0(n2560), .B1(
d_ff3_sh_y_out[15]), .Y(n1405) );
INVX2TS U2392 ( .A(n2459), .Y(n2445) );
CLKBUFX3TS U2393 ( .A(n2454), .Y(n2447) );
AO22XLTS U2394 ( .A0(n2445), .A1(result_add_subt[37]), .B0(n2447), .B1(
d_ff_Zn[37]), .Y(n1768) );
AO22XLTS U2395 ( .A0(n2445), .A1(result_add_subt[36]), .B0(n2447), .B1(
d_ff_Zn[36]), .Y(n1769) );
INVX2TS U2396 ( .A(n2460), .Y(n2561) );
AO22XLTS U2397 ( .A0(n2561), .A1(d_ff2_Y[17]), .B0(n2444), .B1(
d_ff3_sh_y_out[17]), .Y(n1401) );
AO22XLTS U2398 ( .A0(n2445), .A1(result_add_subt[35]), .B0(n2447), .B1(
d_ff_Zn[35]), .Y(n1770) );
CLKBUFX3TS U2399 ( .A(n2444), .Y(n2560) );
AO22XLTS U2400 ( .A0(n2561), .A1(d_ff2_Y[18]), .B0(n2647), .B1(
d_ff3_sh_y_out[18]), .Y(n1399) );
AO22XLTS U2401 ( .A0(n2445), .A1(result_add_subt[34]), .B0(n2447), .B1(
d_ff_Zn[34]), .Y(n1771) );
AO22XLTS U2402 ( .A0(n2445), .A1(result_add_subt[33]), .B0(n2447), .B1(
d_ff_Zn[33]), .Y(n1772) );
AO22XLTS U2403 ( .A0(n2561), .A1(d_ff2_Y[19]), .B0(n2529), .B1(
d_ff3_sh_y_out[19]), .Y(n1397) );
AO22XLTS U2404 ( .A0(n2446), .A1(result_add_subt[32]), .B0(n2447), .B1(
d_ff_Zn[32]), .Y(n1773) );
AO22XLTS U2405 ( .A0(n2561), .A1(d_ff2_Y[21]), .B0(n2560), .B1(
d_ff3_sh_y_out[21]), .Y(n1393) );
AO22XLTS U2406 ( .A0(n2446), .A1(result_add_subt[31]), .B0(n2447), .B1(
d_ff_Zn[31]), .Y(n1774) );
AO22XLTS U2407 ( .A0(n2446), .A1(result_add_subt[30]), .B0(n2447), .B1(
d_ff_Zn[30]), .Y(n1775) );
AO22XLTS U2408 ( .A0(n2561), .A1(d_ff2_Y[23]), .B0(n2647), .B1(
d_ff3_sh_y_out[23]), .Y(n1389) );
AO22XLTS U2409 ( .A0(n2446), .A1(result_add_subt[29]), .B0(n2447), .B1(
d_ff_Zn[29]), .Y(n1776) );
AO22XLTS U2410 ( .A0(n2561), .A1(d_ff2_Y[25]), .B0(n2529), .B1(
d_ff3_sh_y_out[25]), .Y(n1385) );
AO22XLTS U2411 ( .A0(n2458), .A1(result_add_subt[28]), .B0(n2447), .B1(
d_ff_Zn[28]), .Y(n1777) );
CLKBUFX3TS U2412 ( .A(n2448), .Y(n2450) );
AO22XLTS U2413 ( .A0(n2458), .A1(result_add_subt[27]), .B0(n2450), .B1(
d_ff_Zn[27]), .Y(n1778) );
INVX2TS U2414 ( .A(n2449), .Y(n2551) );
CLKBUFX3TS U2415 ( .A(n2575), .Y(n2550) );
AO22XLTS U2416 ( .A0(n2551), .A1(d_ff2_Y[26]), .B0(n2550), .B1(
d_ff3_sh_y_out[26]), .Y(n1383) );
AO22XLTS U2417 ( .A0(n2458), .A1(result_add_subt[26]), .B0(n2450), .B1(
d_ff_Zn[26]), .Y(n1779) );
AO22XLTS U2418 ( .A0(n2551), .A1(d_ff2_Y[27]), .B0(n2560), .B1(
d_ff3_sh_y_out[27]), .Y(n1381) );
AO22XLTS U2419 ( .A0(n2458), .A1(result_add_subt[25]), .B0(n2450), .B1(
d_ff_Zn[25]), .Y(n1780) );
AO22XLTS U2420 ( .A0(n2458), .A1(result_add_subt[24]), .B0(n2450), .B1(
d_ff_Zn[24]), .Y(n1781) );
AO22XLTS U2421 ( .A0(n2551), .A1(d_ff2_Y[29]), .B0(n2550), .B1(
d_ff3_sh_y_out[29]), .Y(n1377) );
AO22XLTS U2422 ( .A0(n2483), .A1(result_add_subt[23]), .B0(n2450), .B1(
d_ff_Zn[23]), .Y(n1782) );
AO22XLTS U2423 ( .A0(n2551), .A1(d_ff2_Y[33]), .B0(n2550), .B1(
d_ff3_sh_y_out[33]), .Y(n1369) );
AO22XLTS U2424 ( .A0(n2483), .A1(result_add_subt[22]), .B0(n2450), .B1(
d_ff_Zn[22]), .Y(n1783) );
AO22XLTS U2425 ( .A0(n2483), .A1(result_add_subt[21]), .B0(n2450), .B1(
d_ff_Zn[21]), .Y(n1784) );
INVX2TS U2426 ( .A(n2460), .Y(n2528) );
AO22XLTS U2427 ( .A0(n2528), .A1(d_ff2_Y[37]), .B0(n2550), .B1(
d_ff3_sh_y_out[37]), .Y(n1361) );
AO22XLTS U2428 ( .A0(n2483), .A1(result_add_subt[20]), .B0(n2450), .B1(
d_ff_Zn[20]), .Y(n1785) );
CLKBUFX3TS U2429 ( .A(n2575), .Y(n2527) );
AO22XLTS U2430 ( .A0(n2528), .A1(d_ff2_Y[39]), .B0(n2527), .B1(
d_ff3_sh_y_out[39]), .Y(n1357) );
AO22XLTS U2431 ( .A0(n2483), .A1(result_add_subt[19]), .B0(n2450), .B1(
d_ff_Zn[19]), .Y(n1786) );
AO22XLTS U2432 ( .A0(n2457), .A1(result_add_subt[18]), .B0(n2450), .B1(
d_ff_Zn[18]), .Y(n1787) );
AOI22X1TS U2433 ( .A0(n2452), .A1(n2683), .B0(n2588), .B1(n2451), .Y(n2453)
);
AO21XLTS U2434 ( .A0(d_ff3_LUT_out[0]), .A1(n2653), .B0(n2453), .Y(n1549) );
CLKBUFX3TS U2435 ( .A(n2454), .Y(n2482) );
AO22XLTS U2436 ( .A0(n2457), .A1(result_add_subt[17]), .B0(n2482), .B1(
d_ff_Zn[17]), .Y(n1788) );
AO22XLTS U2437 ( .A0(n2456), .A1(result_add_subt[1]), .B0(n2455), .B1(
d_ff_Zn[1]), .Y(n1804) );
AO22XLTS U2438 ( .A0(n2457), .A1(result_add_subt[16]), .B0(n2482), .B1(
d_ff_Zn[16]), .Y(n1789) );
AO22XLTS U2439 ( .A0(n2457), .A1(result_add_subt[15]), .B0(n2482), .B1(
d_ff_Zn[15]), .Y(n1790) );
AO22XLTS U2440 ( .A0(n2456), .A1(result_add_subt[2]), .B0(n2459), .B1(
d_ff_Zn[2]), .Y(n1803) );
AO22XLTS U2441 ( .A0(n2457), .A1(result_add_subt[14]), .B0(n2482), .B1(
d_ff_Zn[14]), .Y(n1791) );
AO22XLTS U2442 ( .A0(n2456), .A1(result_add_subt[3]), .B0(n2459), .B1(
d_ff_Zn[3]), .Y(n1802) );
AO22XLTS U2443 ( .A0(n2457), .A1(result_add_subt[13]), .B0(n2482), .B1(
d_ff_Zn[13]), .Y(n1792) );
AO22XLTS U2444 ( .A0(n2458), .A1(result_add_subt[12]), .B0(n2482), .B1(
d_ff_Zn[12]), .Y(n1793) );
AO22XLTS U2445 ( .A0(n2483), .A1(result_add_subt[4]), .B0(n2459), .B1(
d_ff_Zn[4]), .Y(n1801) );
AO22XLTS U2446 ( .A0(n2458), .A1(result_add_subt[11]), .B0(n2482), .B1(
d_ff_Zn[11]), .Y(n1794) );
AO22XLTS U2447 ( .A0(n2483), .A1(result_add_subt[5]), .B0(n2459), .B1(
d_ff_Zn[5]), .Y(n1800) );
AO22XLTS U2448 ( .A0(n2458), .A1(result_add_subt[10]), .B0(n2482), .B1(
d_ff_Zn[10]), .Y(n1795) );
AO22XLTS U2449 ( .A0(n2458), .A1(result_add_subt[9]), .B0(n2482), .B1(
d_ff_Zn[9]), .Y(n1796) );
AO22XLTS U2450 ( .A0(n2483), .A1(result_add_subt[6]), .B0(n2459), .B1(
d_ff_Zn[6]), .Y(n1799) );
AO22XLTS U2451 ( .A0(n2477), .A1(d_ff1_Z[12]), .B0(n2480), .B1(data_in[12]),
.Y(n1857) );
AO22XLTS U2452 ( .A0(n2545), .A1(d_ff2_X[13]), .B0(n2544), .B1(
d_ff3_sh_x_out[13]), .Y(n1281) );
AO22XLTS U2453 ( .A0(n2545), .A1(d_ff2_X[11]), .B0(n2544), .B1(
d_ff3_sh_x_out[11]), .Y(n1285) );
AO22XLTS U2454 ( .A0(n2541), .A1(d_ff2_X[10]), .B0(n2544), .B1(
d_ff3_sh_x_out[10]), .Y(n1287) );
AO22XLTS U2455 ( .A0(n2545), .A1(d_ff2_X[9]), .B0(n2544), .B1(
d_ff3_sh_x_out[9]), .Y(n1289) );
AO22XLTS U2456 ( .A0(n2545), .A1(d_ff2_X[8]), .B0(n2544), .B1(
d_ff3_sh_x_out[8]), .Y(n1291) );
AO22XLTS U2457 ( .A0(n2545), .A1(d_ff2_X[7]), .B0(n2544), .B1(
d_ff3_sh_x_out[7]), .Y(n1293) );
AO22XLTS U2458 ( .A0(n2545), .A1(d_ff2_X[6]), .B0(n2649), .B1(
d_ff3_sh_x_out[6]), .Y(n1295) );
AO22XLTS U2459 ( .A0(n2541), .A1(d_ff2_X[5]), .B0(n2649), .B1(
d_ff3_sh_x_out[5]), .Y(n1297) );
AO22XLTS U2460 ( .A0(n2541), .A1(d_ff2_X[3]), .B0(n2649), .B1(
d_ff3_sh_x_out[3]), .Y(n1301) );
AO22XLTS U2461 ( .A0(n2541), .A1(d_ff2_X[2]), .B0(n2649), .B1(
d_ff3_sh_x_out[2]), .Y(n1303) );
AO22XLTS U2462 ( .A0(n2541), .A1(d_ff2_X[1]), .B0(n2649), .B1(
d_ff3_sh_x_out[1]), .Y(n1305) );
AO22XLTS U2463 ( .A0(n2541), .A1(d_ff2_X[0]), .B0(n2657), .B1(
d_ff3_sh_x_out[0]), .Y(n1307) );
CMPR32X2TS U2464 ( .A(d_ff2_X[55]), .B(n2687), .C(n2461), .CO(n2676), .S(
n2462) );
CLKBUFX3TS U2465 ( .A(n2575), .Y(n2594) );
AO22XLTS U2466 ( .A0(n2596), .A1(n2462), .B0(n2594), .B1(d_ff3_sh_x_out[55]),
.Y(n1190) );
CMPR32X2TS U2467 ( .A(d_ff2_X[54]), .B(n2012), .C(n2463), .CO(n2461), .S(
n2464) );
AO22XLTS U2468 ( .A0(n2596), .A1(n2464), .B0(n2594), .B1(d_ff3_sh_x_out[54]),
.Y(n1191) );
OAI22X1TS U2469 ( .A0(n2466), .A1(n2593), .B0(n2690), .B1(n2465), .Y(n2467)
);
AO21XLTS U2470 ( .A0(d_ff3_sh_x_out[52]), .A1(n2653), .B0(n2467), .Y(n1193)
);
CLKBUFX3TS U2471 ( .A(n2470), .Y(n2476) );
AO22XLTS U2472 ( .A0(n2471), .A1(d_ff1_Z[63]), .B0(n2476), .B1(data_in[63]),
.Y(n1806) );
AO22XLTS U2473 ( .A0(n2471), .A1(d_ff1_Z[62]), .B0(n2470), .B1(data_in[62]),
.Y(n1807) );
AO22XLTS U2474 ( .A0(n2471), .A1(d_ff1_Z[61]), .B0(n2640), .B1(data_in[61]),
.Y(n1808) );
AO22XLTS U2475 ( .A0(n2471), .A1(d_ff1_Z[60]), .B0(n2472), .B1(data_in[60]),
.Y(n1809) );
AO22XLTS U2476 ( .A0(n2477), .A1(d_ff1_Z[59]), .B0(n2640), .B1(data_in[59]),
.Y(n1810) );
AO22XLTS U2477 ( .A0(n2468), .A1(d_ff1_Z[58]), .B0(n2640), .B1(data_in[58]),
.Y(n1811) );
AO22XLTS U2478 ( .A0(n2468), .A1(d_ff1_Z[57]), .B0(n2640), .B1(data_in[57]),
.Y(n1812) );
CLKBUFX3TS U2479 ( .A(n2470), .Y(n2469) );
AO22XLTS U2480 ( .A0(n2468), .A1(d_ff1_Z[56]), .B0(n2469), .B1(data_in[56]),
.Y(n1813) );
AO22XLTS U2481 ( .A0(n2468), .A1(d_ff1_Z[55]), .B0(n2469), .B1(data_in[55]),
.Y(n1814) );
AO22XLTS U2482 ( .A0(n2468), .A1(d_ff1_Z[54]), .B0(n2469), .B1(data_in[54]),
.Y(n1815) );
AO22XLTS U2483 ( .A0(n2468), .A1(d_ff1_Z[53]), .B0(n2469), .B1(data_in[53]),
.Y(n1816) );
AO22XLTS U2484 ( .A0(n2471), .A1(d_ff1_Z[52]), .B0(n2469), .B1(data_in[52]),
.Y(n1817) );
AO22XLTS U2485 ( .A0(n2471), .A1(d_ff1_Z[51]), .B0(n2469), .B1(data_in[51]),
.Y(n1818) );
AO22XLTS U2486 ( .A0(n2471), .A1(d_ff1_Z[50]), .B0(n2469), .B1(data_in[50]),
.Y(n1819) );
AO22XLTS U2487 ( .A0(n2471), .A1(d_ff1_Z[49]), .B0(n2469), .B1(data_in[49]),
.Y(n1820) );
INVX2TS U2488 ( .A(n2470), .Y(n2475) );
AO22XLTS U2489 ( .A0(n2475), .A1(d_ff1_Z[48]), .B0(n2469), .B1(data_in[48]),
.Y(n1821) );
AO22XLTS U2490 ( .A0(n2475), .A1(d_ff1_Z[47]), .B0(n2469), .B1(data_in[47]),
.Y(n1822) );
CLKBUFX3TS U2491 ( .A(n2470), .Y(n2473) );
AO22XLTS U2492 ( .A0(n2475), .A1(d_ff1_Z[46]), .B0(n2473), .B1(data_in[46]),
.Y(n1823) );
AO22XLTS U2493 ( .A0(n2475), .A1(d_ff1_Z[45]), .B0(n2473), .B1(data_in[45]),
.Y(n1824) );
AO22XLTS U2494 ( .A0(n2475), .A1(d_ff1_Z[44]), .B0(n2473), .B1(data_in[44]),
.Y(n1825) );
AO22XLTS U2495 ( .A0(n2475), .A1(d_ff1_Z[43]), .B0(n2473), .B1(data_in[43]),
.Y(n1826) );
INVX2TS U2496 ( .A(n2472), .Y(n2481) );
AO22XLTS U2497 ( .A0(n2481), .A1(d_ff1_Z[42]), .B0(n2473), .B1(data_in[42]),
.Y(n1827) );
AO22XLTS U2498 ( .A0(n2481), .A1(d_ff1_Z[41]), .B0(n2473), .B1(data_in[41]),
.Y(n1828) );
AO22XLTS U2499 ( .A0(n2481), .A1(d_ff1_Z[40]), .B0(n2473), .B1(data_in[40]),
.Y(n1829) );
AO22XLTS U2500 ( .A0(n2481), .A1(d_ff1_Z[39]), .B0(n2473), .B1(data_in[39]),
.Y(n1830) );
AO22XLTS U2501 ( .A0(n2471), .A1(d_ff1_Z[38]), .B0(n2473), .B1(data_in[38]),
.Y(n1831) );
INVX2TS U2502 ( .A(n2472), .Y(n2474) );
AO22XLTS U2503 ( .A0(n2474), .A1(d_ff1_Z[37]), .B0(n2473), .B1(data_in[37]),
.Y(n1832) );
AO22XLTS U2504 ( .A0(n2474), .A1(d_ff1_Z[36]), .B0(n2476), .B1(data_in[36]),
.Y(n1833) );
AO22XLTS U2505 ( .A0(n2474), .A1(d_ff1_Z[35]), .B0(n2476), .B1(data_in[35]),
.Y(n1834) );
AO22XLTS U2506 ( .A0(n2474), .A1(d_ff1_Z[34]), .B0(n2476), .B1(data_in[34]),
.Y(n1835) );
AO22XLTS U2507 ( .A0(n2474), .A1(d_ff1_Z[33]), .B0(n2476), .B1(data_in[33]),
.Y(n1836) );
AO22XLTS U2508 ( .A0(n2475), .A1(d_ff1_Z[32]), .B0(n2476), .B1(data_in[32]),
.Y(n1837) );
AO22XLTS U2509 ( .A0(n2475), .A1(d_ff1_Z[31]), .B0(n2476), .B1(data_in[31]),
.Y(n1838) );
AO22XLTS U2510 ( .A0(n2475), .A1(d_ff1_Z[30]), .B0(n2476), .B1(data_in[30]),
.Y(n1839) );
AO22XLTS U2511 ( .A0(n2475), .A1(d_ff1_Z[29]), .B0(n2476), .B1(data_in[29]),
.Y(n1840) );
AO22XLTS U2512 ( .A0(n2477), .A1(d_ff1_Z[28]), .B0(n2476), .B1(data_in[28]),
.Y(n1841) );
CLKBUFX3TS U2513 ( .A(n2480), .Y(n2479) );
AO22XLTS U2514 ( .A0(n2477), .A1(d_ff1_Z[27]), .B0(n2479), .B1(data_in[27]),
.Y(n1842) );
AO22XLTS U2515 ( .A0(n2477), .A1(d_ff1_Z[26]), .B0(n2479), .B1(data_in[26]),
.Y(n1843) );
AO22XLTS U2516 ( .A0(n2477), .A1(d_ff1_Z[25]), .B0(n2479), .B1(data_in[25]),
.Y(n1844) );
AO22XLTS U2517 ( .A0(n2477), .A1(d_ff1_Z[24]), .B0(n2479), .B1(data_in[24]),
.Y(n1845) );
AO22XLTS U2518 ( .A0(n2478), .A1(d_ff1_Z[23]), .B0(n2479), .B1(data_in[23]),
.Y(n1846) );
AO22XLTS U2519 ( .A0(n2478), .A1(d_ff1_Z[22]), .B0(n2479), .B1(data_in[22]),
.Y(n1847) );
AO22XLTS U2520 ( .A0(n2478), .A1(d_ff1_Z[21]), .B0(n2479), .B1(data_in[21]),
.Y(n1848) );
AO22XLTS U2521 ( .A0(n2478), .A1(d_ff1_Z[20]), .B0(n2479), .B1(data_in[20]),
.Y(n1849) );
AO22XLTS U2522 ( .A0(n2478), .A1(d_ff1_Z[19]), .B0(n2479), .B1(data_in[19]),
.Y(n1850) );
AO22XLTS U2523 ( .A0(n2481), .A1(d_ff1_Z[18]), .B0(n2479), .B1(data_in[18]),
.Y(n1851) );
AO22XLTS U2524 ( .A0(n2481), .A1(d_ff1_Z[17]), .B0(n2480), .B1(data_in[17]),
.Y(n1852) );
AO22XLTS U2525 ( .A0(n2481), .A1(d_ff1_Z[16]), .B0(n2640), .B1(data_in[16]),
.Y(n1853) );
AO22XLTS U2526 ( .A0(n2481), .A1(d_ff1_Z[15]), .B0(n2480), .B1(data_in[15]),
.Y(n1854) );
AO22XLTS U2527 ( .A0(n2481), .A1(d_ff1_Z[14]), .B0(n2470), .B1(data_in[14]),
.Y(n1855) );
AO22XLTS U2528 ( .A0(n2481), .A1(d_ff1_Z[13]), .B0(n2480), .B1(data_in[13]),
.Y(n1856) );
AO22XLTS U2529 ( .A0(n2483), .A1(result_add_subt[8]), .B0(n2482), .B1(
d_ff_Zn[8]), .Y(n1797) );
INVX2TS U2530 ( .A(n2667), .Y(n2562) );
INVX2TS U2531 ( .A(n2717), .Y(n2524) );
AO22XLTS U2532 ( .A0(n2562), .A1(d_ff_Yn[20]), .B0(d_ff2_Y[20]), .B1(n2524),
.Y(n1396) );
INVX2TS U2533 ( .A(n2667), .Y(n2598) );
INVX2TS U2534 ( .A(n2670), .Y(n2597) );
AO22XLTS U2535 ( .A0(n2598), .A1(d_ff_Xn[5]), .B0(d_ff2_X[5]), .B1(n2597),
.Y(n1298) );
NAND3BXLTS U2536 ( .AN(cont_var_out[1]), .B(ready_add_subt), .C(n2689), .Y(
n2484) );
CLKBUFX2TS U2537 ( .A(n2484), .Y(n2565) );
CLKBUFX2TS U2538 ( .A(n2565), .Y(n2569) );
INVX2TS U2539 ( .A(n2569), .Y(n2526) );
CLKBUFX3TS U2540 ( .A(n2484), .Y(n2505) );
AO22XLTS U2541 ( .A0(n2526), .A1(result_add_subt[28]), .B0(n2505), .B1(
d_ff_Xn[28]), .Y(n1649) );
INVX2TS U2542 ( .A(n2670), .Y(n2563) );
AO22XLTS U2543 ( .A0(n2598), .A1(d_ff_Xn[4]), .B0(d_ff2_X[4]), .B1(n2563),
.Y(n1300) );
AO22XLTS U2544 ( .A0(n2526), .A1(result_add_subt[26]), .B0(n2505), .B1(
d_ff_Xn[26]), .Y(n1651) );
AOI22X1TS U2545 ( .A0(n2485), .A1(cont_iter_out[2]), .B0(d_ff3_LUT_out[6]),
.B1(n2657), .Y(n2487) );
AOI32X1TS U2546 ( .A0(n2589), .A1(n2487), .A2(n2652), .B0(n2486), .B1(n2487),
.Y(n1543) );
AO22XLTS U2547 ( .A0(n2526), .A1(result_add_subt[24]), .B0(n2505), .B1(
d_ff_Xn[24]), .Y(n1653) );
AO22XLTS U2548 ( .A0(n2598), .A1(d_ff_Xn[2]), .B0(d_ff2_X[2]), .B1(n2563),
.Y(n1304) );
INVX2TS U2549 ( .A(n2569), .Y(n2503) );
AO22XLTS U2550 ( .A0(n2503), .A1(result_add_subt[19]), .B0(n2505), .B1(
d_ff_Xn[19]), .Y(n1658) );
INVX2TS U2551 ( .A(n2671), .Y(n2511) );
AO22XLTS U2552 ( .A0(n2511), .A1(d_ff_Xn[1]), .B0(d_ff2_X[1]), .B1(n2563),
.Y(n1306) );
CLKBUFX2TS U2553 ( .A(n2565), .Y(n2508) );
CLKBUFX3TS U2554 ( .A(n2508), .Y(n2502) );
AO22XLTS U2555 ( .A0(n2503), .A1(result_add_subt[14]), .B0(n2502), .B1(
d_ff_Xn[14]), .Y(n1663) );
AO22XLTS U2556 ( .A0(n2503), .A1(result_add_subt[13]), .B0(n2502), .B1(
d_ff_Xn[13]), .Y(n1664) );
CLKBUFX2TS U2557 ( .A(n2565), .Y(n2568) );
INVX2TS U2558 ( .A(n2568), .Y(n2554) );
CLKBUFX3TS U2559 ( .A(n2508), .Y(n2558) );
AO22XLTS U2560 ( .A0(n2554), .A1(result_add_subt[57]), .B0(n2558), .B1(
d_ff_Xn[57]), .Y(n1620) );
AO22XLTS U2561 ( .A0(n2503), .A1(result_add_subt[11]), .B0(n2502), .B1(
d_ff_Xn[11]), .Y(n1666) );
AOI22X1TS U2562 ( .A0(n2489), .A1(n2488), .B0(d_ff3_LUT_out[23]), .B1(n2460),
.Y(n2493) );
OAI211XLTS U2563 ( .A0(cont_iter_out[1]), .A1(cont_iter_out[0]), .B0(n2491),
.C0(n2490), .Y(n2492) );
NAND2X1TS U2564 ( .A(n2493), .B(n2492), .Y(n1526) );
NAND2X1TS U2565 ( .A(n2494), .B(ready_add_subt), .Y(n2517) );
CLKBUFX2TS U2566 ( .A(n2517), .Y(n2506) );
CLKBUFX2TS U2567 ( .A(n2506), .Y(n2530) );
INVX2TS U2568 ( .A(n2530), .Y(n2546) );
CLKBUFX2TS U2569 ( .A(n2506), .Y(n2513) );
AO22XLTS U2570 ( .A0(n2546), .A1(result_add_subt[62]), .B0(n2517), .B1(
d_ff_Yn[62]), .Y(n1679) );
INVX2TS U2571 ( .A(n2568), .Y(n2549) );
AO22XLTS U2572 ( .A0(n2549), .A1(result_add_subt[9]), .B0(n2502), .B1(
d_ff_Xn[9]), .Y(n1668) );
AO22XLTS U2573 ( .A0(n2554), .A1(result_add_subt[52]), .B0(n2558), .B1(
d_ff_Xn[52]), .Y(n1625) );
AO22XLTS U2574 ( .A0(n2549), .A1(result_add_subt[8]), .B0(n2507), .B1(
d_ff_Xn[8]), .Y(n1669) );
AO22XLTS U2575 ( .A0(n2546), .A1(result_add_subt[61]), .B0(n2517), .B1(
d_ff_Yn[61]), .Y(n1680) );
AOI22X1TS U2576 ( .A0(n2679), .A1(n2654), .B0(d_ff3_LUT_out[29]), .B1(n2677),
.Y(n2495) );
NAND2X1TS U2577 ( .A(n2496), .B(n2495), .Y(n1520) );
AO22XLTS U2578 ( .A0(n2549), .A1(result_add_subt[7]), .B0(n2507), .B1(
d_ff_Xn[7]), .Y(n1670) );
INVX2TS U2579 ( .A(n2530), .Y(n2500) );
CLKBUFX3TS U2580 ( .A(n2513), .Y(n2501) );
AO22XLTS U2581 ( .A0(n2500), .A1(result_add_subt[52]), .B0(n2501), .B1(
d_ff_Yn[52]), .Y(n1689) );
AO22XLTS U2582 ( .A0(n2500), .A1(result_add_subt[59]), .B0(n2513), .B1(
d_ff_Yn[59]), .Y(n1682) );
AOI22X1TS U2583 ( .A0(n2497), .A1(n2642), .B0(d_ff3_LUT_out[39]), .B1(n2677),
.Y(n2498) );
AO22XLTS U2584 ( .A0(n2549), .A1(result_add_subt[6]), .B0(n2507), .B1(
d_ff_Xn[6]), .Y(n1671) );
AO22XLTS U2585 ( .A0(n2549), .A1(result_add_subt[3]), .B0(n2507), .B1(
d_ff_Xn[3]), .Y(n1674) );
AO22XLTS U2586 ( .A0(n2500), .A1(result_add_subt[57]), .B0(n2501), .B1(
d_ff_Yn[57]), .Y(n1684) );
AO22XLTS U2587 ( .A0(n2500), .A1(result_add_subt[53]), .B0(n2501), .B1(
d_ff_Yn[53]), .Y(n1688) );
INVX2TS U2588 ( .A(n2568), .Y(n2542) );
CLKBUFX2TS U2589 ( .A(n2508), .Y(n2578) );
AO22XLTS U2590 ( .A0(n2542), .A1(result_add_subt[61]), .B0(n2578), .B1(
d_ff_Xn[61]), .Y(n1616) );
AO22XLTS U2591 ( .A0(n2500), .A1(result_add_subt[56]), .B0(n2501), .B1(
d_ff_Yn[56]), .Y(n1685) );
AO22XLTS U2592 ( .A0(n2542), .A1(result_add_subt[60]), .B0(n2578), .B1(
d_ff_Xn[60]), .Y(n1617) );
AO22XLTS U2593 ( .A0(n2500), .A1(result_add_subt[58]), .B0(n2501), .B1(
d_ff_Yn[58]), .Y(n1683) );
AO22XLTS U2594 ( .A0(n2554), .A1(result_add_subt[59]), .B0(n2578), .B1(
d_ff_Xn[59]), .Y(n1618) );
AO22XLTS U2595 ( .A0(n2500), .A1(result_add_subt[55]), .B0(n2501), .B1(
d_ff_Yn[55]), .Y(n1686) );
AO22XLTS U2596 ( .A0(n2554), .A1(result_add_subt[58]), .B0(n2558), .B1(
d_ff_Xn[58]), .Y(n1619) );
AO22XLTS U2597 ( .A0(n2500), .A1(result_add_subt[54]), .B0(n2501), .B1(
d_ff_Yn[54]), .Y(n1687) );
AO22XLTS U2598 ( .A0(n2554), .A1(result_add_subt[56]), .B0(n2558), .B1(
d_ff_Xn[56]), .Y(n1621) );
AO22XLTS U2599 ( .A0(n2546), .A1(result_add_subt[60]), .B0(n2506), .B1(
d_ff_Yn[60]), .Y(n1681) );
INVX2TS U2600 ( .A(n2667), .Y(n2564) );
AO22XLTS U2601 ( .A0(n2564), .A1(d_ff_Yn[63]), .B0(d_ff2_Y[63]), .B1(n2563),
.Y(n1310) );
AO22XLTS U2602 ( .A0(n2500), .A1(result_add_subt[51]), .B0(n2501), .B1(
d_ff_Yn[51]), .Y(n1690) );
INVX2TS U2603 ( .A(n2664), .Y(n2543) );
AO22XLTS U2604 ( .A0(n2564), .A1(d_ff_Yn[51]), .B0(d_ff2_Y[51]), .B1(n2504),
.Y(n1334) );
AO22XLTS U2605 ( .A0(n2542), .A1(result_add_subt[62]), .B0(n2578), .B1(
d_ff_Xn[62]), .Y(n1615) );
AO22XLTS U2606 ( .A0(n2500), .A1(result_add_subt[50]), .B0(n2501), .B1(
d_ff_Yn[50]), .Y(n1691) );
AO22XLTS U2607 ( .A0(n2598), .A1(d_ff_Yn[50]), .B0(d_ff2_Y[50]), .B1(n2547),
.Y(n1336) );
AO22XLTS U2608 ( .A0(n2549), .A1(result_add_subt[1]), .B0(n2569), .B1(
d_ff_Xn[1]), .Y(n1676) );
AO22XLTS U2609 ( .A0(n2549), .A1(result_add_subt[2]), .B0(n2507), .B1(
d_ff_Xn[2]), .Y(n1675) );
INVX2TS U2610 ( .A(n2669), .Y(n2553) );
AO22XLTS U2611 ( .A0(n2553), .A1(d_ff_Yn[49]), .B0(d_ff2_Y[49]), .B1(n2158),
.Y(n1338) );
CLKBUFX2TS U2612 ( .A(n2506), .Y(n2520) );
INVX2TS U2613 ( .A(n2520), .Y(n2509) );
AO22XLTS U2614 ( .A0(n2509), .A1(result_add_subt[49]), .B0(n2501), .B1(
d_ff_Yn[49]), .Y(n1692) );
AO22XLTS U2615 ( .A0(n2549), .A1(result_add_subt[4]), .B0(n2507), .B1(
d_ff_Xn[4]), .Y(n1673) );
AO22XLTS U2616 ( .A0(n2553), .A1(d_ff_Yn[1]), .B0(d_ff2_Y[1]), .B1(n2158),
.Y(n1434) );
AO22XLTS U2617 ( .A0(n2519), .A1(d_ff_Yn[48]), .B0(d_ff2_Y[48]), .B1(n2543),
.Y(n1340) );
AO22XLTS U2618 ( .A0(n2549), .A1(result_add_subt[5]), .B0(n2507), .B1(
d_ff_Xn[5]), .Y(n1672) );
AO22XLTS U2619 ( .A0(n2509), .A1(result_add_subt[48]), .B0(n2506), .B1(
d_ff_Yn[48]), .Y(n1693) );
AO22XLTS U2620 ( .A0(n2503), .A1(result_add_subt[10]), .B0(n2502), .B1(
d_ff_Xn[10]), .Y(n1667) );
AO22XLTS U2621 ( .A0(n2525), .A1(d_ff_Yn[47]), .B0(d_ff2_Y[47]), .B1(n2139),
.Y(n1342) );
AO22XLTS U2622 ( .A0(n2503), .A1(result_add_subt[12]), .B0(n2502), .B1(
d_ff_Xn[12]), .Y(n1665) );
AO22XLTS U2623 ( .A0(n2519), .A1(d_ff_Yn[2]), .B0(d_ff2_Y[2]), .B1(n2543),
.Y(n1432) );
AO22XLTS U2624 ( .A0(n2146), .A1(d_ff_Yn[46]), .B0(d_ff2_Y[46]), .B1(n2158),
.Y(n1344) );
AO22XLTS U2625 ( .A0(n2503), .A1(result_add_subt[15]), .B0(n2502), .B1(
d_ff_Xn[15]), .Y(n1662) );
AO22XLTS U2626 ( .A0(n2509), .A1(result_add_subt[47]), .B0(n2506), .B1(
d_ff_Yn[47]), .Y(n1694) );
AO22XLTS U2627 ( .A0(n2503), .A1(result_add_subt[16]), .B0(n2502), .B1(
d_ff_Xn[16]), .Y(n1661) );
AO22XLTS U2628 ( .A0(n2556), .A1(d_ff_Yn[45]), .B0(d_ff2_Y[45]), .B1(n2504),
.Y(n1346) );
AO22XLTS U2629 ( .A0(n2503), .A1(result_add_subt[17]), .B0(n2502), .B1(
d_ff_Xn[17]), .Y(n1660) );
AO22XLTS U2630 ( .A0(n2509), .A1(result_add_subt[46]), .B0(n2530), .B1(
d_ff_Yn[46]), .Y(n1695) );
INVX2TS U2631 ( .A(n2021), .Y(n2552) );
AO22XLTS U2632 ( .A0(n2553), .A1(d_ff_Yn[44]), .B0(d_ff2_Y[44]), .B1(n2552),
.Y(n1348) );
AO22XLTS U2633 ( .A0(n2503), .A1(result_add_subt[18]), .B0(n2502), .B1(
d_ff_Xn[18]), .Y(n1659) );
INVX2TS U2634 ( .A(n2669), .Y(n2519) );
AO22XLTS U2635 ( .A0(n2553), .A1(d_ff_Yn[3]), .B0(d_ff2_Y[3]), .B1(n2139),
.Y(n1430) );
AO22XLTS U2636 ( .A0(n2526), .A1(result_add_subt[20]), .B0(n2505), .B1(
d_ff_Xn[20]), .Y(n1657) );
INVX2TS U2637 ( .A(n2664), .Y(n2510) );
AO22XLTS U2638 ( .A0(n2525), .A1(d_ff_Yn[43]), .B0(d_ff2_Y[43]), .B1(n2510),
.Y(n1350) );
AO22XLTS U2639 ( .A0(n2509), .A1(result_add_subt[45]), .B0(n2520), .B1(
d_ff_Yn[45]), .Y(n1696) );
AO22XLTS U2640 ( .A0(n2526), .A1(result_add_subt[21]), .B0(n2505), .B1(
d_ff_Xn[21]), .Y(n1656) );
AO22XLTS U2641 ( .A0(n2511), .A1(d_ff_Yn[42]), .B0(d_ff2_Y[42]), .B1(n2510),
.Y(n1352) );
AO22XLTS U2642 ( .A0(n2526), .A1(result_add_subt[22]), .B0(n2505), .B1(
d_ff_Xn[22]), .Y(n1655) );
INVX2TS U2643 ( .A(n2663), .Y(n2516) );
AO22XLTS U2644 ( .A0(n2556), .A1(d_ff_Yn[4]), .B0(d_ff2_Y[4]), .B1(n2516),
.Y(n1428) );
AO22XLTS U2645 ( .A0(n2509), .A1(result_add_subt[44]), .B0(n2513), .B1(
d_ff_Yn[44]), .Y(n1697) );
AO22XLTS U2646 ( .A0(n2526), .A1(result_add_subt[23]), .B0(n2505), .B1(
d_ff_Xn[23]), .Y(n1654) );
AO22XLTS U2647 ( .A0(n2523), .A1(d_ff_Yn[41]), .B0(d_ff2_Y[41]), .B1(n2510),
.Y(n1354) );
AO22XLTS U2648 ( .A0(n2526), .A1(result_add_subt[25]), .B0(n2505), .B1(
d_ff_Xn[25]), .Y(n1652) );
AO22XLTS U2649 ( .A0(n2511), .A1(d_ff_Yn[40]), .B0(d_ff2_Y[40]), .B1(n2510),
.Y(n1356) );
AO22XLTS U2650 ( .A0(n2526), .A1(result_add_subt[27]), .B0(n2505), .B1(
d_ff_Xn[27]), .Y(n1650) );
AO22XLTS U2651 ( .A0(n2509), .A1(result_add_subt[43]), .B0(n2506), .B1(
d_ff_Yn[43]), .Y(n1698) );
AO22XLTS U2652 ( .A0(n2519), .A1(d_ff_Yn[5]), .B0(d_ff2_Y[5]), .B1(n2516),
.Y(n1426) );
INVX2TS U2653 ( .A(n2507), .Y(n2592) );
CLKBUFX3TS U2654 ( .A(n2508), .Y(n2591) );
AO22XLTS U2655 ( .A0(n2592), .A1(result_add_subt[30]), .B0(n2591), .B1(
d_ff_Xn[30]), .Y(n1647) );
AO22XLTS U2656 ( .A0(n2511), .A1(d_ff_Yn[39]), .B0(d_ff2_Y[39]), .B1(n2510),
.Y(n1358) );
AO22XLTS U2657 ( .A0(n2592), .A1(result_add_subt[33]), .B0(n2591), .B1(
d_ff_Xn[33]), .Y(n1644) );
AO22XLTS U2658 ( .A0(n2509), .A1(result_add_subt[42]), .B0(n2530), .B1(
d_ff_Yn[42]), .Y(n1699) );
AO22XLTS U2659 ( .A0(n2511), .A1(d_ff_Yn[38]), .B0(d_ff2_Y[38]), .B1(n2510),
.Y(n1360) );
AO22XLTS U2660 ( .A0(n2592), .A1(result_add_subt[37]), .B0(n2591), .B1(
d_ff_Xn[37]), .Y(n1640) );
AO22XLTS U2661 ( .A0(n2146), .A1(d_ff_Yn[6]), .B0(d_ff2_Y[6]), .B1(n2516),
.Y(n1424) );
AO22XLTS U2662 ( .A0(n2592), .A1(result_add_subt[38]), .B0(n2591), .B1(
d_ff_Xn[38]), .Y(n1639) );
AO22XLTS U2663 ( .A0(n2511), .A1(d_ff_Yn[37]), .B0(d_ff2_Y[37]), .B1(n2510),
.Y(n1362) );
AO22XLTS U2664 ( .A0(n2509), .A1(result_add_subt[41]), .B0(n2520), .B1(
d_ff_Yn[41]), .Y(n1700) );
INVX2TS U2665 ( .A(n2569), .Y(n2570) );
AO22XLTS U2666 ( .A0(n2570), .A1(result_add_subt[40]), .B0(n2508), .B1(
d_ff_Xn[40]), .Y(n1637) );
AO22XLTS U2667 ( .A0(n2511), .A1(d_ff_Yn[36]), .B0(d_ff2_Y[36]), .B1(n2510),
.Y(n1364) );
AO22XLTS U2668 ( .A0(n2570), .A1(result_add_subt[44]), .B0(n2578), .B1(
d_ff_Xn[44]), .Y(n1633) );
AO22XLTS U2669 ( .A0(n2509), .A1(result_add_subt[40]), .B0(n2513), .B1(
d_ff_Yn[40]), .Y(n1701) );
AO22XLTS U2670 ( .A0(n2570), .A1(result_add_subt[47]), .B0(n2565), .B1(
d_ff_Xn[47]), .Y(n1630) );
AO22XLTS U2671 ( .A0(n2511), .A1(d_ff_Yn[35]), .B0(d_ff2_Y[35]), .B1(n2510),
.Y(n1366) );
AO22XLTS U2672 ( .A0(n2525), .A1(d_ff_Yn[7]), .B0(d_ff2_Y[7]), .B1(n2516),
.Y(n1422) );
AO22XLTS U2673 ( .A0(n2554), .A1(result_add_subt[50]), .B0(n2558), .B1(
d_ff_Xn[50]), .Y(n1627) );
AO22XLTS U2674 ( .A0(n2511), .A1(d_ff_Yn[34]), .B0(d_ff2_Y[34]), .B1(n2510),
.Y(n1368) );
AO22XLTS U2675 ( .A0(n2554), .A1(result_add_subt[51]), .B0(n2558), .B1(
d_ff_Xn[51]), .Y(n1626) );
INVX2TS U2676 ( .A(n2512), .Y(n2521) );
AO22XLTS U2677 ( .A0(n2521), .A1(result_add_subt[39]), .B0(n2512), .B1(
d_ff_Yn[39]), .Y(n1702) );
INVX2TS U2678 ( .A(n2530), .Y(n2531) );
AO22XLTS U2679 ( .A0(n2531), .A1(result_add_subt[1]), .B0(n2520), .B1(
d_ff_Yn[1]), .Y(n1740) );
INVX2TS U2680 ( .A(n2670), .Y(n2514) );
AO22XLTS U2681 ( .A0(n2519), .A1(d_ff_Yn[33]), .B0(d_ff2_Y[33]), .B1(n2514),
.Y(n1370) );
AO22XLTS U2682 ( .A0(n2556), .A1(d_ff_Yn[8]), .B0(d_ff2_Y[8]), .B1(n2516),
.Y(n1420) );
AO22XLTS U2683 ( .A0(n2531), .A1(result_add_subt[2]), .B0(n2512), .B1(
d_ff_Yn[2]), .Y(n1739) );
CLKBUFX3TS U2684 ( .A(n2513), .Y(n2522) );
AO22XLTS U2685 ( .A0(n2521), .A1(result_add_subt[38]), .B0(n2522), .B1(
d_ff_Yn[38]), .Y(n1703) );
AO22XLTS U2686 ( .A0(n2511), .A1(d_ff_Yn[32]), .B0(d_ff2_Y[32]), .B1(n2514),
.Y(n1372) );
AO22XLTS U2687 ( .A0(n2531), .A1(result_add_subt[3]), .B0(n2512), .B1(
d_ff_Yn[3]), .Y(n1738) );
AO22XLTS U2688 ( .A0(n2531), .A1(result_add_subt[4]), .B0(n2512), .B1(
d_ff_Yn[4]), .Y(n1737) );
AO22XLTS U2689 ( .A0(n2525), .A1(d_ff_Yn[31]), .B0(d_ff2_Y[31]), .B1(n2514),
.Y(n1374) );
AO22XLTS U2690 ( .A0(n2521), .A1(result_add_subt[37]), .B0(n2522), .B1(
d_ff_Yn[37]), .Y(n1704) );
AO22XLTS U2691 ( .A0(n2531), .A1(result_add_subt[5]), .B0(n2512), .B1(
d_ff_Yn[5]), .Y(n1736) );
AO22XLTS U2692 ( .A0(n2146), .A1(d_ff_Yn[9]), .B0(d_ff2_Y[9]), .B1(n2516),
.Y(n1418) );
AO22XLTS U2693 ( .A0(n2553), .A1(d_ff_Yn[30]), .B0(d_ff2_Y[30]), .B1(n2514),
.Y(n1376) );
AO22XLTS U2694 ( .A0(n2531), .A1(result_add_subt[6]), .B0(n2512), .B1(
d_ff_Yn[6]), .Y(n1735) );
AO22XLTS U2695 ( .A0(n2521), .A1(result_add_subt[36]), .B0(n2522), .B1(
d_ff_Yn[36]), .Y(n1705) );
AO22XLTS U2696 ( .A0(n2531), .A1(result_add_subt[7]), .B0(n2512), .B1(
d_ff_Yn[7]), .Y(n1734) );
AO22XLTS U2697 ( .A0(n2519), .A1(d_ff_Yn[29]), .B0(d_ff2_Y[29]), .B1(n2514),
.Y(n1378) );
AO22XLTS U2698 ( .A0(n2531), .A1(result_add_subt[8]), .B0(n2512), .B1(
d_ff_Yn[8]), .Y(n1733) );
AO22XLTS U2699 ( .A0(n2553), .A1(d_ff_Yn[10]), .B0(d_ff2_Y[10]), .B1(n2516),
.Y(n1416) );
AO22XLTS U2700 ( .A0(n2525), .A1(d_ff_Yn[28]), .B0(d_ff2_Y[28]), .B1(n2514),
.Y(n1380) );
CLKBUFX3TS U2701 ( .A(n2513), .Y(n2515) );
AO22XLTS U2702 ( .A0(n2531), .A1(result_add_subt[9]), .B0(n2515), .B1(
d_ff_Yn[9]), .Y(n1732) );
AO22XLTS U2703 ( .A0(n2521), .A1(result_add_subt[35]), .B0(n2522), .B1(
d_ff_Yn[35]), .Y(n1706) );
INVX2TS U2704 ( .A(n2520), .Y(n2518) );
AO22XLTS U2705 ( .A0(n2518), .A1(result_add_subt[10]), .B0(n2515), .B1(
d_ff_Yn[10]), .Y(n1731) );
AO22XLTS U2706 ( .A0(n2146), .A1(d_ff_Yn[27]), .B0(d_ff2_Y[27]), .B1(n2514),
.Y(n1382) );
AO22XLTS U2707 ( .A0(n2518), .A1(result_add_subt[11]), .B0(n2515), .B1(
d_ff_Yn[11]), .Y(n1730) );
AO22XLTS U2708 ( .A0(n2521), .A1(result_add_subt[34]), .B0(n2522), .B1(
d_ff_Yn[34]), .Y(n1707) );
AO22XLTS U2709 ( .A0(n2519), .A1(d_ff_Yn[26]), .B0(d_ff2_Y[26]), .B1(n2514),
.Y(n1384) );
AO22XLTS U2710 ( .A0(n2518), .A1(result_add_subt[12]), .B0(n2515), .B1(
d_ff_Yn[12]), .Y(n1729) );
AO22XLTS U2711 ( .A0(n2556), .A1(d_ff_Yn[11]), .B0(d_ff2_Y[11]), .B1(n2516),
.Y(n1414) );
AO22XLTS U2712 ( .A0(n2518), .A1(result_add_subt[13]), .B0(n2515), .B1(
d_ff_Yn[13]), .Y(n1728) );
AO22XLTS U2713 ( .A0(n2553), .A1(d_ff_Yn[25]), .B0(d_ff2_Y[25]), .B1(n2514),
.Y(n1386) );
AO22XLTS U2714 ( .A0(n2521), .A1(result_add_subt[33]), .B0(n2522), .B1(
d_ff_Yn[33]), .Y(n1708) );
AO22XLTS U2715 ( .A0(n2518), .A1(result_add_subt[14]), .B0(n2515), .B1(
d_ff_Yn[14]), .Y(n1727) );
AO22XLTS U2716 ( .A0(n2525), .A1(d_ff_Yn[24]), .B0(d_ff2_Y[24]), .B1(n2514),
.Y(n1388) );
AO22XLTS U2717 ( .A0(n2518), .A1(result_add_subt[15]), .B0(n2515), .B1(
d_ff_Yn[15]), .Y(n1726) );
AO22XLTS U2718 ( .A0(n2519), .A1(d_ff_Yn[12]), .B0(d_ff2_Y[12]), .B1(n2516),
.Y(n1412) );
AO22XLTS U2719 ( .A0(n2521), .A1(result_add_subt[32]), .B0(n2522), .B1(
d_ff_Yn[32]), .Y(n1709) );
AO22XLTS U2720 ( .A0(n2518), .A1(result_add_subt[16]), .B0(n2515), .B1(
d_ff_Yn[16]), .Y(n1725) );
AO22XLTS U2721 ( .A0(n2525), .A1(d_ff_Yn[23]), .B0(d_ff2_Y[23]), .B1(n2524),
.Y(n1390) );
AO22XLTS U2722 ( .A0(n2518), .A1(result_add_subt[17]), .B0(n2515), .B1(
d_ff_Yn[17]), .Y(n1724) );
AO22XLTS U2723 ( .A0(n2556), .A1(d_ff_Yn[22]), .B0(d_ff2_Y[22]), .B1(n2524),
.Y(n1392) );
AO22XLTS U2724 ( .A0(n2518), .A1(result_add_subt[18]), .B0(n2515), .B1(
d_ff_Yn[18]), .Y(n1723) );
AO22XLTS U2725 ( .A0(n2521), .A1(result_add_subt[31]), .B0(n2522), .B1(
d_ff_Yn[31]), .Y(n1710) );
AO22XLTS U2726 ( .A0(n2523), .A1(d_ff_Yn[13]), .B0(d_ff2_Y[13]), .B1(n2516),
.Y(n1410) );
CLKBUFX3TS U2727 ( .A(n2517), .Y(n2571) );
AO22XLTS U2728 ( .A0(n2518), .A1(result_add_subt[19]), .B0(n2571), .B1(
d_ff_Yn[19]), .Y(n1722) );
AO22XLTS U2729 ( .A0(n2146), .A1(d_ff_Yn[21]), .B0(d_ff2_Y[21]), .B1(n2524),
.Y(n1394) );
INVX2TS U2730 ( .A(n2520), .Y(n2572) );
AO22XLTS U2731 ( .A0(n2572), .A1(result_add_subt[20]), .B0(n2571), .B1(
d_ff_Yn[20]), .Y(n1721) );
AO22XLTS U2732 ( .A0(n2521), .A1(result_add_subt[30]), .B0(n2522), .B1(
d_ff_Yn[30]), .Y(n1711) );
AO22XLTS U2733 ( .A0(n2572), .A1(result_add_subt[21]), .B0(n2571), .B1(
d_ff_Yn[21]), .Y(n1720) );
AO22XLTS U2734 ( .A0(n2556), .A1(d_ff_Yn[14]), .B0(d_ff2_Y[14]), .B1(n2524),
.Y(n1408) );
AO22XLTS U2735 ( .A0(n2523), .A1(d_ff_Yn[19]), .B0(d_ff2_Y[19]), .B1(n2524),
.Y(n1398) );
AO22XLTS U2736 ( .A0(n2572), .A1(result_add_subt[22]), .B0(n2571), .B1(
d_ff_Yn[22]), .Y(n1719) );
AO22XLTS U2737 ( .A0(n2572), .A1(result_add_subt[29]), .B0(n2522), .B1(
d_ff_Yn[29]), .Y(n1712) );
AO22XLTS U2738 ( .A0(n2572), .A1(result_add_subt[23]), .B0(n2571), .B1(
d_ff_Yn[23]), .Y(n1718) );
AO22XLTS U2739 ( .A0(n2523), .A1(d_ff_Yn[18]), .B0(d_ff2_Y[18]), .B1(n2524),
.Y(n1400) );
AO22XLTS U2740 ( .A0(n2572), .A1(result_add_subt[24]), .B0(n2571), .B1(
d_ff_Yn[24]), .Y(n1717) );
AO22XLTS U2741 ( .A0(n2572), .A1(result_add_subt[28]), .B0(n2571), .B1(
d_ff_Yn[28]), .Y(n1713) );
AO22XLTS U2742 ( .A0(n2523), .A1(d_ff_Yn[17]), .B0(d_ff2_Y[17]), .B1(n2524),
.Y(n1402) );
AO22XLTS U2743 ( .A0(n2572), .A1(result_add_subt[25]), .B0(n2571), .B1(
d_ff_Yn[25]), .Y(n1716) );
AO22XLTS U2744 ( .A0(n2523), .A1(d_ff_Yn[15]), .B0(d_ff2_Y[15]), .B1(n2524),
.Y(n1406) );
AO22XLTS U2745 ( .A0(n2572), .A1(result_add_subt[26]), .B0(n2571), .B1(
d_ff_Yn[26]), .Y(n1715) );
AO22XLTS U2746 ( .A0(n2146), .A1(d_ff_Yn[16]), .B0(d_ff2_Y[16]), .B1(n2524),
.Y(n1404) );
AO22XLTS U2747 ( .A0(n2526), .A1(result_add_subt[29]), .B0(n2591), .B1(
d_ff_Xn[29]), .Y(n1648) );
AO22XLTS U2748 ( .A0(n2528), .A1(d_ff2_Y[41]), .B0(n2527), .B1(
d_ff3_sh_y_out[41]), .Y(n1353) );
AO22XLTS U2749 ( .A0(n2528), .A1(d_ff2_Y[40]), .B0(n2527), .B1(
d_ff3_sh_y_out[40]), .Y(n1355) );
AO22XLTS U2750 ( .A0(n2562), .A1(d_ff_Xn[51]), .B0(d_ff2_X[51]), .B1(n2504),
.Y(n1206) );
AO22XLTS U2751 ( .A0(n2528), .A1(d_ff2_Y[42]), .B0(n2527), .B1(
d_ff3_sh_y_out[42]), .Y(n1351) );
AO22XLTS U2752 ( .A0(n2598), .A1(d_ff_Xn[63]), .B0(d_ff2_X[63]), .B1(n2547),
.Y(n1182) );
AO22XLTS U2753 ( .A0(n2528), .A1(d_ff2_Y[43]), .B0(n2527), .B1(
d_ff3_sh_y_out[43]), .Y(n1349) );
AO22XLTS U2754 ( .A0(n2528), .A1(d_ff2_Y[44]), .B0(n2527), .B1(
d_ff3_sh_y_out[44]), .Y(n1347) );
AO22XLTS U2755 ( .A0(n2562), .A1(d_ff_Xn[50]), .B0(d_ff2_X[50]), .B1(n2547),
.Y(n1208) );
AO22XLTS U2756 ( .A0(n2528), .A1(d_ff2_Y[38]), .B0(n2527), .B1(
d_ff3_sh_y_out[38]), .Y(n1359) );
AO22XLTS U2757 ( .A0(n2528), .A1(d_ff2_Y[45]), .B0(n2527), .B1(
d_ff3_sh_y_out[45]), .Y(n1345) );
AO22XLTS U2758 ( .A0(n2577), .A1(d_ff2_Y[46]), .B0(n2647), .B1(
d_ff3_sh_y_out[46]), .Y(n1343) );
AO22XLTS U2759 ( .A0(n2562), .A1(d_ff_Xn[47]), .B0(d_ff2_X[47]), .B1(n2552),
.Y(n1214) );
AO22XLTS U2760 ( .A0(n2577), .A1(d_ff2_Y[47]), .B0(n2527), .B1(
d_ff3_sh_y_out[47]), .Y(n1341) );
AO22XLTS U2761 ( .A0(n2528), .A1(d_ff2_Y[36]), .B0(n2527), .B1(
d_ff3_sh_y_out[36]), .Y(n1363) );
AO22XLTS U2762 ( .A0(n2577), .A1(d_ff2_Y[48]), .B0(n2529), .B1(
d_ff3_sh_y_out[48]), .Y(n1339) );
AO22XLTS U2763 ( .A0(n2564), .A1(d_ff_Yn[55]), .B0(d_ff2_Y[55]), .B1(n2563),
.Y(n1329) );
AO22XLTS U2764 ( .A0(n2562), .A1(d_ff_Xn[44]), .B0(d_ff2_X[44]), .B1(n2552),
.Y(n1220) );
AO22XLTS U2765 ( .A0(n2577), .A1(d_ff2_Y[49]), .B0(n2560), .B1(
d_ff3_sh_y_out[49]), .Y(n1337) );
AO22XLTS U2766 ( .A0(n2531), .A1(result_add_subt[0]), .B0(n2530), .B1(
d_ff_Yn[0]), .Y(n1741) );
AO22XLTS U2767 ( .A0(n2564), .A1(d_ff_Yn[54]), .B0(d_ff2_Y[54]), .B1(n2543),
.Y(n1330) );
AO22XLTS U2768 ( .A0(n2577), .A1(d_ff2_Y[50]), .B0(n2653), .B1(
d_ff3_sh_y_out[50]), .Y(n1335) );
AO22XLTS U2769 ( .A0(n2564), .A1(d_ff_Xn[40]), .B0(d_ff2_X[40]), .B1(n2552),
.Y(n1228) );
AO22XLTS U2770 ( .A0(n2577), .A1(d_ff2_Y[51]), .B0(n2575), .B1(
d_ff3_sh_y_out[51]), .Y(n1333) );
AO22XLTS U2771 ( .A0(n2551), .A1(d_ff2_Y[35]), .B0(n2550), .B1(
d_ff3_sh_y_out[35]), .Y(n1365) );
NOR2X1TS U2772 ( .A(d_ff2_Y[56]), .B(n2656), .Y(n2655) );
INVX2TS U2773 ( .A(n2655), .Y(n2533) );
AOI21X1TS U2774 ( .A0(d_ff2_Y[57]), .A1(n2533), .B0(n2532), .Y(n2534) );
AOI2BB2XLTS U2775 ( .B0(n2662), .B1(n2534), .A0N(d_ff3_sh_y_out[57]), .A1N(
n2584), .Y(n1316) );
AO22XLTS U2776 ( .A0(n2564), .A1(d_ff_Yn[59]), .B0(d_ff2_Y[59]), .B1(n2563),
.Y(n1325) );
AO22XLTS U2777 ( .A0(n2553), .A1(d_ff_Xn[38]), .B0(d_ff2_X[38]), .B1(n2552),
.Y(n1232) );
AO22XLTS U2778 ( .A0(n2551), .A1(d_ff2_Y[34]), .B0(n2550), .B1(
d_ff3_sh_y_out[34]), .Y(n1367) );
AOI21X1TS U2779 ( .A0(d_ff2_Y[59]), .A1(n2535), .B0(n2574), .Y(n2536) );
AOI2BB2XLTS U2780 ( .B0(n2662), .B1(n2536), .A0N(d_ff3_sh_y_out[59]), .A1N(
n2584), .Y(n1314) );
AO22XLTS U2781 ( .A0(n2564), .A1(d_ff_Yn[62]), .B0(d_ff2_Y[62]), .B1(n2563),
.Y(n1322) );
OAI21XLTS U2782 ( .A0(n2583), .A1(n2692), .B0(n2581), .Y(n2537) );
AO22XLTS U2783 ( .A0(n2596), .A1(n2537), .B0(n2594), .B1(d_ff3_sh_x_out[58]),
.Y(n1187) );
AO22XLTS U2784 ( .A0(n2519), .A1(d_ff_Xn[37]), .B0(d_ff2_X[37]), .B1(n2552),
.Y(n1234) );
AO22XLTS U2785 ( .A0(n2538), .A1(d_ff3_sign_out), .B0(n2584), .B1(
d_ff2_Z[63]), .Y(n1437) );
OAI21XLTS U2786 ( .A0(n2580), .A1(n2693), .B0(n2539), .Y(n2540) );
AO22XLTS U2787 ( .A0(n2644), .A1(n2540), .B0(n2594), .B1(d_ff3_sh_x_out[60]),
.Y(n1185) );
AO22XLTS U2788 ( .A0(n2551), .A1(d_ff2_Y[32]), .B0(n2550), .B1(
d_ff3_sh_y_out[32]), .Y(n1371) );
AO22XLTS U2789 ( .A0(n2541), .A1(d_ff2_X[4]), .B0(n2649), .B1(
d_ff3_sh_x_out[4]), .Y(n1299) );
AO22XLTS U2790 ( .A0(n2542), .A1(result_add_subt[63]), .B0(n2578), .B1(
d_ff_Xn[63]), .Y(n1614) );
AO22XLTS U2791 ( .A0(n2525), .A1(d_ff_Xn[33]), .B0(d_ff2_X[33]), .B1(n2139),
.Y(n1242) );
AO22XLTS U2792 ( .A0(n2545), .A1(d_ff2_X[12]), .B0(n2544), .B1(
d_ff3_sh_x_out[12]), .Y(n1283) );
AO22XLTS U2793 ( .A0(n2564), .A1(d_ff_Yn[61]), .B0(d_ff2_Y[61]), .B1(n2563),
.Y(n1323) );
AO22XLTS U2794 ( .A0(n2545), .A1(d_ff2_X[16]), .B0(n2544), .B1(
d_ff3_sh_x_out[16]), .Y(n1275) );
AO22XLTS U2795 ( .A0(n2551), .A1(d_ff2_Y[31]), .B0(n2550), .B1(
d_ff3_sh_y_out[31]), .Y(n1373) );
AO22XLTS U2796 ( .A0(n2146), .A1(d_ff_Xn[30]), .B0(d_ff2_X[30]), .B1(n2552),
.Y(n1248) );
AO22XLTS U2797 ( .A0(n2548), .A1(d_ff2_X[20]), .B0(n2575), .B1(
d_ff3_sh_x_out[20]), .Y(n1267) );
AO22XLTS U2798 ( .A0(n2546), .A1(result_add_subt[63]), .B0(n2512), .B1(
d_ff_Yn[63]), .Y(n1678) );
AO22XLTS U2799 ( .A0(n2548), .A1(d_ff2_X[22]), .B0(n2434), .B1(
d_ff3_sh_x_out[22]), .Y(n1263) );
AO22XLTS U2800 ( .A0(n2564), .A1(d_ff_Yn[57]), .B0(d_ff2_Y[57]), .B1(n2563),
.Y(n1327) );
INVX2TS U2801 ( .A(n2667), .Y(n2672) );
AO22XLTS U2802 ( .A0(d_ff2_X[62]), .A1(n2547), .B0(n2672), .B1(d_ff_Xn[62]),
.Y(n1194) );
AO22XLTS U2803 ( .A0(n2551), .A1(d_ff2_Y[30]), .B0(n2550), .B1(
d_ff3_sh_y_out[30]), .Y(n1375) );
AO22XLTS U2804 ( .A0(n2548), .A1(d_ff2_X[24]), .B0(n2430), .B1(
d_ff3_sh_x_out[24]), .Y(n1259) );
AO22XLTS U2805 ( .A0(n2562), .A1(d_ff_Xn[27]), .B0(d_ff2_X[27]), .B1(n2552),
.Y(n1254) );
AO22XLTS U2806 ( .A0(n2548), .A1(d_ff2_X[28]), .B0(n2557), .B1(
d_ff3_sh_x_out[28]), .Y(n1251) );
AO22XLTS U2807 ( .A0(n2549), .A1(result_add_subt[0]), .B0(n2568), .B1(
d_ff_Xn[0]), .Y(n1677) );
AO22XLTS U2808 ( .A0(n2559), .A1(d_ff2_X[30]), .B0(n2557), .B1(
d_ff3_sh_x_out[30]), .Y(n1247) );
AO22XLTS U2809 ( .A0(n2551), .A1(d_ff2_Y[28]), .B0(n2550), .B1(
d_ff3_sh_y_out[28]), .Y(n1379) );
AO22XLTS U2810 ( .A0(n2556), .A1(d_ff_Xn[25]), .B0(d_ff2_X[25]), .B1(n2552),
.Y(n1258) );
AO22XLTS U2811 ( .A0(n2554), .A1(result_add_subt[55]), .B0(n2558), .B1(
d_ff_Xn[55]), .Y(n1622) );
AO22XLTS U2812 ( .A0(n2559), .A1(d_ff2_X[31]), .B0(n2557), .B1(
d_ff3_sh_x_out[31]), .Y(n1245) );
AO22XLTS U2813 ( .A0(n2559), .A1(d_ff2_X[32]), .B0(n2557), .B1(
d_ff3_sh_x_out[32]), .Y(n1243) );
AO22XLTS U2814 ( .A0(n2554), .A1(result_add_subt[54]), .B0(n2558), .B1(
d_ff_Xn[54]), .Y(n1623) );
AO22XLTS U2815 ( .A0(n2561), .A1(d_ff2_Y[16]), .B0(n2647), .B1(
d_ff3_sh_y_out[16]), .Y(n1403) );
AO22XLTS U2816 ( .A0(n2562), .A1(d_ff_Xn[23]), .B0(d_ff2_X[23]), .B1(n2552),
.Y(n1262) );
AO22XLTS U2817 ( .A0(n2579), .A1(d_ff2_X[46]), .B0(n2566), .B1(
d_ff3_sh_x_out[46]), .Y(n1215) );
AO22XLTS U2818 ( .A0(n2559), .A1(d_ff2_X[34]), .B0(n2557), .B1(
d_ff3_sh_x_out[34]), .Y(n1239) );
AO22XLTS U2819 ( .A0(n2556), .A1(d_ff_Xn[17]), .B0(d_ff2_X[17]), .B1(n2597),
.Y(n1274) );
AO22XLTS U2820 ( .A0(n2554), .A1(result_add_subt[53]), .B0(n2558), .B1(
d_ff_Xn[53]), .Y(n1624) );
AO22XLTS U2821 ( .A0(n2579), .A1(d_ff2_X[35]), .B0(n2557), .B1(
d_ff3_sh_x_out[35]), .Y(n1237) );
NOR2XLTS U2822 ( .A(n2686), .B(n2567), .Y(n2555) );
XOR2XLTS U2823 ( .A(n2555), .B(cont_iter_out[3]), .Y(n1874) );
AO22XLTS U2824 ( .A0(n2561), .A1(d_ff2_Y[24]), .B0(n2529), .B1(
d_ff3_sh_y_out[24]), .Y(n1387) );
AO22XLTS U2825 ( .A0(n2146), .A1(d_ff_Xn[22]), .B0(d_ff2_X[22]), .B1(n2597),
.Y(n1264) );
AO22XLTS U2826 ( .A0(n2579), .A1(d_ff2_X[36]), .B0(n2557), .B1(
d_ff3_sh_x_out[36]), .Y(n1235) );
AO22XLTS U2827 ( .A0(n2570), .A1(result_add_subt[49]), .B0(n2558), .B1(
d_ff_Xn[49]), .Y(n1628) );
AO22XLTS U2828 ( .A0(n2561), .A1(d_ff2_Y[22]), .B0(n2560), .B1(
d_ff3_sh_y_out[22]), .Y(n1391) );
AO22XLTS U2829 ( .A0(n2579), .A1(d_ff2_X[38]), .B0(n2566), .B1(
d_ff3_sh_x_out[38]), .Y(n1231) );
AO22XLTS U2830 ( .A0(n2570), .A1(result_add_subt[48]), .B0(n2565), .B1(
d_ff_Xn[48]), .Y(n1629) );
AO22XLTS U2831 ( .A0(n2559), .A1(d_ff2_X[40]), .B0(n2566), .B1(
d_ff3_sh_x_out[40]), .Y(n1227) );
AO22XLTS U2832 ( .A0(n2596), .A1(d_ff2_X[50]), .B0(n2594), .B1(
d_ff3_sh_x_out[50]), .Y(n1207) );
AO22XLTS U2833 ( .A0(n2562), .A1(d_ff_Xn[21]), .B0(d_ff2_X[21]), .B1(n2597),
.Y(n1266) );
AO22XLTS U2834 ( .A0(n2596), .A1(d_ff2_X[51]), .B0(n2594), .B1(
d_ff3_sh_x_out[51]), .Y(n1205) );
AO22XLTS U2835 ( .A0(n2579), .A1(d_ff2_X[41]), .B0(n2566), .B1(
d_ff3_sh_x_out[41]), .Y(n1225) );
AO22XLTS U2836 ( .A0(n2570), .A1(result_add_subt[46]), .B0(n2568), .B1(
d_ff_Xn[46]), .Y(n1631) );
AO22XLTS U2837 ( .A0(n2592), .A1(result_add_subt[35]), .B0(n2591), .B1(
d_ff_Xn[35]), .Y(n1642) );
AO22XLTS U2838 ( .A0(n2561), .A1(d_ff2_Y[20]), .B0(n2647), .B1(
d_ff3_sh_y_out[20]), .Y(n1395) );
AO22XLTS U2839 ( .A0(n2579), .A1(d_ff2_X[42]), .B0(n2566), .B1(
d_ff3_sh_x_out[42]), .Y(n1223) );
AO22XLTS U2840 ( .A0(n2562), .A1(d_ff_Xn[20]), .B0(d_ff2_X[20]), .B1(n2597),
.Y(n1268) );
AO22XLTS U2841 ( .A0(n2570), .A1(result_add_subt[45]), .B0(n2569), .B1(
d_ff_Xn[45]), .Y(n1632) );
AO22XLTS U2842 ( .A0(n2579), .A1(d_ff2_X[43]), .B0(n2566), .B1(
d_ff3_sh_x_out[43]), .Y(n1221) );
AO22XLTS U2843 ( .A0(n2564), .A1(d_ff_Yn[56]), .B0(d_ff2_Y[56]), .B1(n2563),
.Y(n1328) );
AO22XLTS U2844 ( .A0(n2598), .A1(d_ff_Xn[12]), .B0(d_ff2_X[12]), .B1(n2597),
.Y(n1284) );
AO22XLTS U2845 ( .A0(n2579), .A1(d_ff2_X[44]), .B0(n2566), .B1(
d_ff3_sh_x_out[44]), .Y(n1219) );
AO22XLTS U2846 ( .A0(n2570), .A1(result_add_subt[43]), .B0(n2565), .B1(
d_ff_Xn[43]), .Y(n1634) );
AO22XLTS U2847 ( .A0(n2598), .A1(d_ff_Xn[18]), .B0(d_ff2_X[18]), .B1(n2597),
.Y(n1272) );
AO22XLTS U2848 ( .A0(n2596), .A1(d_ff2_X[45]), .B0(n2566), .B1(
d_ff3_sh_x_out[45]), .Y(n1217) );
AOI2BB2XLTS U2849 ( .B0(n2567), .B1(n2686), .A0N(n2012), .A1N(n2567), .Y(
n1875) );
AO22XLTS U2850 ( .A0(n2570), .A1(result_add_subt[42]), .B0(n2568), .B1(
d_ff_Xn[42]), .Y(n1635) );
AO22XLTS U2851 ( .A0(n2596), .A1(d_ff2_X[48]), .B0(n2594), .B1(
d_ff3_sh_x_out[48]), .Y(n1211) );
AO22XLTS U2852 ( .A0(n2596), .A1(d_ff2_X[47]), .B0(n2594), .B1(
d_ff3_sh_x_out[47]), .Y(n1213) );
AO22XLTS U2853 ( .A0(n2570), .A1(result_add_subt[41]), .B0(n2569), .B1(
d_ff_Xn[41]), .Y(n1636) );
AO22XLTS U2854 ( .A0(n2598), .A1(d_ff_Xn[16]), .B0(d_ff2_X[16]), .B1(n2597),
.Y(n1276) );
AO22XLTS U2855 ( .A0(n2572), .A1(result_add_subt[27]), .B0(n2571), .B1(
d_ff_Yn[27]), .Y(n1714) );
AO22XLTS U2856 ( .A0(n2573), .A1(d_ff2_Y[12]), .B0(n2575), .B1(
d_ff3_sh_y_out[12]), .Y(n1411) );
OAI21XLTS U2857 ( .A0(n2574), .A1(n2695), .B0(n2660), .Y(n2576) );
AO22XLTS U2858 ( .A0(n2577), .A1(n2576), .B0(n2575), .B1(d_ff3_sh_y_out[60]),
.Y(n1313) );
AO22XLTS U2859 ( .A0(n2592), .A1(result_add_subt[39]), .B0(n2578), .B1(
d_ff_Xn[39]), .Y(n1638) );
AO22XLTS U2860 ( .A0(n2579), .A1(d_ff2_X[49]), .B0(n2594), .B1(
d_ff3_sh_x_out[49]), .Y(n1209) );
AO22XLTS U2861 ( .A0(n2598), .A1(d_ff_Xn[15]), .B0(d_ff2_X[15]), .B1(n2597),
.Y(n1278) );
AOI21X1TS U2862 ( .A0(d_ff2_X[59]), .A1(n2581), .B0(n2580), .Y(n2582) );
AOI2BB2XLTS U2863 ( .B0(n2662), .B1(n2582), .A0N(d_ff3_sh_x_out[59]), .A1N(
n2651), .Y(n1186) );
AO22XLTS U2864 ( .A0(n2592), .A1(result_add_subt[32]), .B0(n2591), .B1(
d_ff_Xn[32]), .Y(n1645) );
AO22XLTS U2865 ( .A0(n2592), .A1(result_add_subt[36]), .B0(n2591), .B1(
d_ff_Xn[36]), .Y(n1641) );
AO22XLTS U2866 ( .A0(n2584), .A1(d_ff2_Y[4]), .B0(n2529), .B1(
d_ff3_sh_y_out[4]), .Y(n1427) );
AO22XLTS U2867 ( .A0(n2592), .A1(result_add_subt[31]), .B0(n2591), .B1(
d_ff_Xn[31]), .Y(n1646) );
NOR2X1TS U2868 ( .A(d_ff2_X[56]), .B(n2676), .Y(n2675) );
AOI2BB1XLTS U2869 ( .A0N(n2700), .A1N(n2675), .B0(n2583), .Y(n2585) );
AOI2BB2XLTS U2870 ( .B0(n2662), .B1(n2585), .A0N(d_ff3_sh_x_out[57]), .A1N(
n2584), .Y(n1188) );
XNOR2X1TS U2871 ( .A(n2586), .B(n2688), .Y(n2587) );
MXI2X1TS U2872 ( .A(n2589), .B(n2588), .S0(n2587), .Y(n2590) );
AO21XLTS U2873 ( .A0(d_ff3_sh_y_out[53]), .A1(n2560), .B0(n2590), .Y(n1320)
);
AO22XLTS U2874 ( .A0(n2592), .A1(result_add_subt[34]), .B0(n2591), .B1(
d_ff_Xn[34]), .Y(n1643) );
CMPR32X2TS U2875 ( .A(d_ff2_X[53]), .B(n2683), .C(n2593), .CO(n2463), .S(
n2595) );
AO22XLTS U2876 ( .A0(n2596), .A1(n2595), .B0(n2594), .B1(d_ff3_sh_x_out[53]),
.Y(n1192) );
AO22XLTS U2877 ( .A0(n2598), .A1(d_ff_Xn[10]), .B0(d_ff2_X[10]), .B1(n2597),
.Y(n1288) );
AO22XLTS U2878 ( .A0(n2599), .A1(d_ff3_sh_x_out[63]), .B0(n2361), .B1(
d_ff3_sh_y_out[63]), .Y(add_subt_dataB[63]) );
AO22XLTS U2879 ( .A0(d_ff3_sh_y_out[62]), .A1(n2317), .B0(d_ff3_sh_x_out[62]), .B1(n2600), .Y(add_subt_dataB[62]) );
AOI22X1TS U2880 ( .A0(n2630), .A1(d_ff3_sh_x_out[60]), .B0(n2620), .B1(
d_ff3_sh_y_out[60]), .Y(n2601) );
NAND2X1TS U2881 ( .A(n2601), .B(n2610), .Y(add_subt_dataB[60]) );
AOI22X1TS U2882 ( .A0(n2621), .A1(d_ff3_sh_x_out[59]), .B0(n2620), .B1(
d_ff3_sh_y_out[59]), .Y(n2602) );
NAND2X1TS U2883 ( .A(n2602), .B(n2610), .Y(add_subt_dataB[59]) );
AOI22X1TS U2884 ( .A0(n2621), .A1(d_ff3_sh_x_out[58]), .B0(n2620), .B1(
d_ff3_sh_y_out[58]), .Y(n2603) );
NAND2X1TS U2885 ( .A(n2603), .B(n2610), .Y(add_subt_dataB[58]) );
AOI22X1TS U2886 ( .A0(n2630), .A1(d_ff3_sh_x_out[57]), .B0(n2620), .B1(
d_ff3_sh_y_out[57]), .Y(n2604) );
NAND2X1TS U2887 ( .A(n2604), .B(n2610), .Y(add_subt_dataB[57]) );
OAI222X1TS U2888 ( .A0(n2701), .A1(n2032), .B0(n2680), .B1(n2606), .C0(n2682), .C1(n2605), .Y(add_subt_dataB[56]) );
AOI22X1TS U2889 ( .A0(n2621), .A1(d_ff3_sh_x_out[51]), .B0(n2620), .B1(
d_ff3_sh_y_out[51]), .Y(n2607) );
NAND2X1TS U2890 ( .A(n2607), .B(n2610), .Y(add_subt_dataB[51]) );
AOI22X1TS U2891 ( .A0(n2621), .A1(d_ff3_sh_x_out[49]), .B0(n2620), .B1(
d_ff3_sh_y_out[49]), .Y(n2609) );
NAND2X1TS U2892 ( .A(n2608), .B(d_ff3_LUT_out[44]), .Y(n2613) );
NAND2X1TS U2893 ( .A(n2609), .B(n2613), .Y(add_subt_dataB[49]) );
AOI22X1TS U2894 ( .A0(n2624), .A1(d_ff3_sh_x_out[48]), .B0(n2401), .B1(
d_ff3_sh_y_out[48]), .Y(n2611) );
NAND2X1TS U2895 ( .A(n2611), .B(n2610), .Y(add_subt_dataB[48]) );
AOI22X1TS U2896 ( .A0(n2624), .A1(d_ff3_sh_x_out[46]), .B0(n2623), .B1(
d_ff3_sh_y_out[46]), .Y(n2612) );
NAND2X1TS U2897 ( .A(n2612), .B(n2613), .Y(add_subt_dataB[46]) );
AOI22X1TS U2898 ( .A0(n2621), .A1(d_ff3_sh_x_out[44]), .B0(n2401), .B1(
d_ff3_sh_y_out[44]), .Y(n2614) );
NAND2X1TS U2899 ( .A(n2614), .B(n2613), .Y(add_subt_dataB[44]) );
AOI2BB2XLTS U2900 ( .B0(cont_var_out[0]), .B1(d_ff3_sign_out), .A0N(
d_ff3_sign_out), .A1N(cont_var_out[0]), .Y(op_add_subt) );
NOR2BX1TS U2901 ( .AN(beg_fsm_cordic), .B(n2615), .Y(
inst_CORDIC_FSM_v3_state_next[1]) );
OAI22X1TS U2902 ( .A0(n2619), .A1(n2618), .B0(n2617), .B1(n2032), .Y(
inst_CORDIC_FSM_v3_state_next[5]) );
AOI22X1TS U2903 ( .A0(n2409), .A1(d_ff3_sh_x_out[47]), .B0(n2620), .B1(
d_ff3_sh_y_out[47]), .Y(n2622) );
OAI2BB1X1TS U2904 ( .A0N(n2626), .A1N(d_ff3_LUT_out[42]), .B0(n2622), .Y(
add_subt_dataB[47]) );
AOI22X1TS U2905 ( .A0(n2624), .A1(d_ff3_sh_x_out[42]), .B0(n2623), .B1(
d_ff3_sh_y_out[42]), .Y(n2625) );
OAI2BB1X1TS U2906 ( .A0N(n2626), .A1N(d_ff3_LUT_out[42]), .B0(n2625), .Y(
add_subt_dataB[42]) );
INVX2TS U2907 ( .A(n2627), .Y(n2632) );
AOI22X1TS U2908 ( .A0(d_ff2_Y[62]), .A1(n2634), .B0(d_ff2_Z[62]), .B1(n2633),
.Y(n2628) );
OAI2BB1X1TS U2909 ( .A0N(d_ff2_X[62]), .A1N(n2632), .B0(n2628), .Y(
add_subt_dataA[62]) );
AOI22X1TS U2910 ( .A0(d_ff2_Y[61]), .A1(n2409), .B0(d_ff2_Z[61]), .B1(n2633),
.Y(n2629) );
OAI2BB1X1TS U2911 ( .A0N(d_ff2_X[61]), .A1N(n2333), .B0(n2629), .Y(
add_subt_dataA[61]) );
AOI22X1TS U2912 ( .A0(d_ff2_Y[59]), .A1(n2630), .B0(d_ff2_Z[59]), .B1(n2633),
.Y(n2631) );
OAI2BB1X1TS U2913 ( .A0N(d_ff2_X[59]), .A1N(n2344), .B0(n2631), .Y(
add_subt_dataA[59]) );
AOI22X1TS U2914 ( .A0(d_ff2_Y[56]), .A1(n2634), .B0(d_ff2_Z[56]), .B1(n2633),
.Y(n2635) );
OAI2BB1X1TS U2915 ( .A0N(d_ff2_X[56]), .A1N(n2636), .B0(n2635), .Y(
add_subt_dataA[56]) );
AOI21X1TS U2916 ( .A0(n2638), .A1(n2009), .B0(n2637), .Y(n1877) );
OAI2BB2XLTS U2917 ( .B0(n2640), .B1(n2705), .A0N(n2639), .A1N(operation),
.Y(n1872) );
OAI2BB2XLTS U2918 ( .B0(n2640), .B1(n2684), .A0N(n2433), .A1N(
shift_region_flag[0]), .Y(n1871) );
OAI2BB2XLTS U2919 ( .B0(n2640), .B1(n2681), .A0N(n2639), .A1N(
shift_region_flag[1]), .Y(n1870) );
OAI21XLTS U2920 ( .A0(n2662), .A1(d_ff3_LUT_out[13]), .B0(n2645), .Y(n2641)
);
OAI2BB1X1TS U2921 ( .A0N(n2643), .A1N(n2642), .B0(n2641), .Y(n1536) );
OA22X1TS U2922 ( .A0(n2646), .A1(n2645), .B0(n2644), .B1(d_ff3_LUT_out[21]),
.Y(n1528) );
OAI2BB2XLTS U2923 ( .B0(n2649), .B1(n2648), .A0N(n2529), .A1N(
d_ff3_LUT_out[42]), .Y(n1511) );
OAI2BB1X1TS U2924 ( .A0N(d_ff3_LUT_out[44]), .A1N(n2653), .B0(n2650), .Y(
n1510) );
OR2X1TS U2925 ( .A(d_ff3_LUT_out[48]), .B(n2651), .Y(n1508) );
OAI2BB1X1TS U2926 ( .A0N(d_ff3_LUT_out[52]), .A1N(n2653), .B0(n2652), .Y(
n1506) );
AOI22X1TS U2927 ( .A0(n2679), .A1(n2654), .B0(n2701), .B1(n2677), .Y(n1502)
);
OAI2BB2XLTS U2928 ( .B0(n2704), .B1(n2663), .A0N(n2672), .A1N(d_ff_Yn[52]),
.Y(n1332) );
OAI2BB2XLTS U2929 ( .B0(n2688), .B1(n2664), .A0N(n2672), .A1N(d_ff_Yn[53]),
.Y(n1331) );
OAI2BB2XLTS U2930 ( .B0(n2694), .B1(n2670), .A0N(n2672), .A1N(d_ff_Yn[58]),
.Y(n1326) );
OAI2BB2XLTS U2931 ( .B0(n2695), .B1(n2021), .A0N(n2672), .A1N(d_ff_Yn[60]),
.Y(n1324) );
AOI21X1TS U2932 ( .A0(n2656), .A1(d_ff2_Y[56]), .B0(n2655), .Y(n2658) );
AOI22X1TS U2933 ( .A0(n2662), .A1(n2658), .B0(n2682), .B1(n2538), .Y(n1317)
);
AOI21X1TS U2934 ( .A0(d_ff2_Y[61]), .A1(n2660), .B0(n2659), .Y(n2661) );
AOI22X1TS U2935 ( .A0(n2662), .A1(n2661), .B0(n2702), .B1(n2677), .Y(n1312)
);
OA22X1TS U2936 ( .A0(d_ff_Xn[3]), .A1(n2673), .B0(n2717), .B1(d_ff2_X[3]),
.Y(n1302) );
OA22X1TS U2937 ( .A0(d_ff_Xn[6]), .A1(n2665), .B0(n2717), .B1(d_ff2_X[6]),
.Y(n1296) );
OA22X1TS U2938 ( .A0(d_ff_Xn[7]), .A1(n2666), .B0(n2021), .B1(d_ff2_X[7]),
.Y(n1294) );
OA22X1TS U2939 ( .A0(d_ff_Xn[8]), .A1(n2673), .B0(n2664), .B1(d_ff2_X[8]),
.Y(n1292) );
OA22X1TS U2940 ( .A0(d_ff_Xn[9]), .A1(n2665), .B0(n2663), .B1(d_ff2_X[9]),
.Y(n1290) );
OA22X1TS U2941 ( .A0(d_ff_Xn[11]), .A1(n2666), .B0(n2670), .B1(d_ff2_X[11]),
.Y(n1286) );
OA22X1TS U2942 ( .A0(d_ff_Xn[13]), .A1(n2673), .B0(n2717), .B1(d_ff2_X[13]),
.Y(n1282) );
OA22X1TS U2943 ( .A0(d_ff_Xn[14]), .A1(n2665), .B0(n2670), .B1(d_ff2_X[14]),
.Y(n1280) );
OA22X1TS U2944 ( .A0(d_ff_Xn[24]), .A1(n2671), .B0(n2717), .B1(d_ff2_X[24]),
.Y(n1260) );
OA22X1TS U2945 ( .A0(d_ff_Xn[26]), .A1(n2666), .B0(n2663), .B1(d_ff2_X[26]),
.Y(n1256) );
OA22X1TS U2946 ( .A0(d_ff_Xn[28]), .A1(n2666), .B0(n2664), .B1(d_ff2_X[28]),
.Y(n1252) );
OA22X1TS U2947 ( .A0(d_ff_Xn[29]), .A1(n2667), .B0(n2670), .B1(d_ff2_X[29]),
.Y(n1250) );
OA22X1TS U2948 ( .A0(d_ff_Xn[32]), .A1(n2673), .B0(n2674), .B1(d_ff2_X[32]),
.Y(n1244) );
OA22X1TS U2949 ( .A0(d_ff_Xn[34]), .A1(n2671), .B0(n2663), .B1(d_ff2_X[34]),
.Y(n1240) );
OA22X1TS U2950 ( .A0(d_ff_Xn[35]), .A1(n2668), .B0(n2717), .B1(d_ff2_X[35]),
.Y(n1238) );
OA22X1TS U2951 ( .A0(d_ff_Xn[36]), .A1(n2673), .B0(n2717), .B1(d_ff2_X[36]),
.Y(n1236) );
OA22X1TS U2952 ( .A0(d_ff_Xn[39]), .A1(n2671), .B0(n2664), .B1(d_ff2_X[39]),
.Y(n1230) );
OAI2BB2XLTS U2953 ( .B0(n2690), .B1(n2663), .A0N(n2672), .A1N(d_ff_Xn[52]),
.Y(n1204) );
OA22X1TS U2954 ( .A0(n2674), .A1(d_ff2_X[56]), .B0(d_ff_Xn[56]), .B1(n2665),
.Y(n1200) );
AOI21X1TS U2955 ( .A0(n2676), .A1(d_ff2_X[56]), .B0(n2675), .Y(n2678) );
AOI22X1TS U2956 ( .A0(n2679), .A1(n2678), .B0(n2680), .B1(n2677), .Y(n1189)
);
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_noclk.tcl_syn.sdf");
endmodule
|
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: reg_grp.v
// Project: NetFPGA
// Description: Generic register group
//
// Muxes the registers for a group
//
// Note: The downstream modules should respect the rules for the number of
// cycles to hold ack high.
//
///////////////////////////////////////////////////////////////////////////////
module reg_grp #(parameter
REG_ADDR_BITS = 10,
NUM_OUTPUTS = 4
)
(
// Upstream register interface
input reg_req,
input reg_rd_wr_L,
input [REG_ADDR_BITS -1:0] reg_addr,
input [`CPCI_NF2_DATA_WIDTH -1:0] reg_wr_data,
output reg reg_ack,
output reg [`CPCI_NF2_DATA_WIDTH -1:0] reg_rd_data,
// Downstream register interface
output [NUM_OUTPUTS - 1 : 0] local_reg_req,
output [NUM_OUTPUTS - 1 : 0] local_reg_rd_wr_L,
output [NUM_OUTPUTS * (REG_ADDR_BITS - log2(NUM_OUTPUTS)) -1:0] local_reg_addr,
output [NUM_OUTPUTS * `CPCI_NF2_DATA_WIDTH -1:0] local_reg_wr_data,
input [NUM_OUTPUTS - 1 : 0] local_reg_ack,
input [NUM_OUTPUTS * `CPCI_NF2_DATA_WIDTH -1:0] local_reg_rd_data,
//-- misc
input clk,
input reset
);
// Log base 2 function
//
// Returns ceil(log2(X))
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// Register addresses
localparam SWITCH_ADDR_BITS = log2(NUM_OUTPUTS);
// ===========================================
// Local variables
wire [SWITCH_ADDR_BITS - 1 : 0] sel;
integer i;
// Internal register interface signals
reg int_reg_req[NUM_OUTPUTS - 1 : 0];
reg int_reg_rd_wr_L[NUM_OUTPUTS - 1 : 0];
reg [REG_ADDR_BITS -1:0] int_reg_addr[NUM_OUTPUTS - 1 : 0];
reg [`CPCI_NF2_DATA_WIDTH -1:0] int_reg_wr_data[NUM_OUTPUTS - 1 : 0];
wire int_reg_ack[NUM_OUTPUTS - 1 : 0];
wire [`CPCI_NF2_DATA_WIDTH -1:0] int_reg_rd_data[NUM_OUTPUTS - 1 : 0];
assign sel = reg_addr[REG_ADDR_BITS - 1 : REG_ADDR_BITS - SWITCH_ADDR_BITS];
// =====================================================
// Process register requests
always @(posedge clk)
begin
for (i = 0; i < NUM_OUTPUTS ; i = i + 1) begin
if (reset || sel != i) begin
int_reg_req[i] <= 1'b0;
int_reg_rd_wr_L[i] <= 1'b0;
int_reg_addr[i] <= 'h0;
int_reg_wr_data[i] <= 'h0;
end
else begin
int_reg_req[i] <= reg_req;
int_reg_rd_wr_L[i] <= reg_rd_wr_L;
int_reg_addr[i] <= reg_addr;
int_reg_wr_data[i] <= reg_wr_data;
end
end // for
end
always @(posedge clk)
begin
if (reset || sel >= NUM_OUTPUTS) begin
// Reset the outputs
reg_ack <= 1'b0;
reg_rd_data <= reset ? 'h0 : 'h dead_beef;
end
else begin
reg_ack <= int_reg_ack[sel];
reg_rd_data <= int_reg_rd_data[sel];
end
end
// =====================================================
// Logic to split/join inputs/outputs
genvar j;
generate
for (j = 0; j < NUM_OUTPUTS ; j = j + 1) begin : flatten
assign local_reg_req[j] = int_reg_req[j];
assign local_reg_rd_wr_L[j] = int_reg_rd_wr_L[j];
assign local_reg_addr[j * (REG_ADDR_BITS - SWITCH_ADDR_BITS) +: (REG_ADDR_BITS - SWITCH_ADDR_BITS)] = int_reg_addr[j];
assign local_reg_wr_data[j * `CPCI_NF2_DATA_WIDTH +: `CPCI_NF2_DATA_WIDTH] = int_reg_wr_data[j];
assign int_reg_ack[j] = local_reg_ack[j];
assign int_reg_rd_data[j] = local_reg_rd_data[j * `CPCI_NF2_DATA_WIDTH +: `CPCI_NF2_DATA_WIDTH];
end
endgenerate
// =====================================================
// Verify that ack is never high when the request signal is low
// synthesis translate_off
integer k;
always @(posedge clk) begin
if (reg_req === 1'b0)
for (k = 0; k < NUM_OUTPUTS ; k = k + 1)
if (int_reg_ack[k] === 1'b1)
$display($time, " %m: ERROR: int_reg_ack[%1d] is high when reg_req is low", k);
end
// synthesis translate_on
endmodule // reg_grp
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__SDFRBP_PP_BLACKBOX_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRBP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUFLP_SYMBOL_V
`define SKY130_FD_SC_LP__CLKBUFLP_SYMBOL_V
/**
* clkbuflp: Clock tree buffer, Low Power.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkbuflp (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUFLP_SYMBOL_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_dft_jtag.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "ctu.h"
module ctu_dft_jtag (/*AUTOARG*/
// Outputs
dft_tdo, io_tdo_en, jtag_creg_addr, jtag_creg_data, jtag_creg_rd_en,
jtag_creg_wr_en, jtag_creg_addr_en, jtag_creg_data_en,
jtag_creg_rdrtrn_complete, jtag_bist_serial, jtag_bist_parallel,
jtag_bist_active, jtag_bist_abort, dft_pll_div2, dft_pll_arst_l,
dft_pll_testmode, dft_pll_clamp_fltr, jtag_clsp_stop_id_vld,
jtag_clsp_stop_id, jtag_nstep_vld, jtag_nstep_domain,
jtag_nstep_count, dft_clsp_nstep_capture_l, jtag_clock_dr,
jtag_clsp_ignore_wrm_rst, jtag_clsp_sel_tck2,
jtag_clsp_force_cken_cmp, jtag_clsp_force_cken_dram,
jtag_clsp_force_cken_jbus, pll_bypass, ctu_sel_cpu, ctu_sel_dram,
ctu_sel_jbus, ctu_spc0_sscan_se, ctu_spc1_sscan_se,
ctu_spc2_sscan_se, ctu_spc3_sscan_se, ctu_spc4_sscan_se,
ctu_spc5_sscan_se, ctu_spc6_sscan_se, ctu_spc7_sscan_se,
ctu_spc0_tck, ctu_spc1_tck, ctu_spc2_tck, ctu_spc3_tck, ctu_spc4_tck,
ctu_spc5_tck, ctu_spc6_tck, ctu_spc7_tck, ctu_spc_sscan_tid,
ctu_pads_sscan_update, ctu_global_snap, ctu_ddr0_mode_ctl,
ctu_ddr0_hiz_l, ctu_ddr0_update_dr, ctu_ddr0_clock_dr,
ctu_ddr0_shift_dr, ctu_ddr1_mode_ctl, ctu_ddr1_hiz_l,
ctu_ddr1_update_dr, ctu_ddr1_clock_dr, ctu_ddr1_shift_dr,
ctu_ddr2_mode_ctl, ctu_ddr2_hiz_l, ctu_ddr2_update_dr,
ctu_ddr2_clock_dr, ctu_ddr2_shift_dr, ctu_ddr3_mode_ctl,
ctu_ddr3_hiz_l, ctu_ddr3_update_dr, ctu_ddr3_clock_dr,
ctu_ddr3_shift_dr, ctu_jbusl_mode_ctl, ctu_jbusl_hiz_l,
ctu_jbusl_update_dr, ctu_jbusl_clock_dr, ctu_jbusl_shift_dr,
ctu_jbusr_mode_ctl, ctu_jbusr_hiz_l, ctu_jbusr_update_dr,
ctu_jbusr_clock_dr, ctu_jbusr_shift_dr, ctu_debug_mode_ctl,
ctu_debug_hiz_l, ctu_debug_update_dr, ctu_debug_clock_dr,
ctu_debug_shift_dr, ctu_misc_mode_ctl, ctu_misc_hiz_l,
ctu_misc_update_dr, ctu_misc_clock_dr, ctu_misc_shift_dr,
ctu_pads_bso, global_shift_enable, global_scan_bypass_en,
dft_ctu_scan_disable, dft_pin_pscan_l, ctu_pads_so, ctu_fpu_so,
pscan_select, ctu_ddr_testmode_l, ctu_tst_scanmode,
ctu_tst_macrotest, ctu_tst_short_chain, ctu_tst_scan_disable,
ctu_efc_data_in, ctu_efc_updatedr, ctu_efc_shiftdr,
ctu_efc_capturedr, ctu_efc_tck, ctu_efc_rowaddr, ctu_efc_coladdr,
ctu_efc_read_en, ctu_efc_read_mode, ctu_efc_fuse_bypass,
ctu_efc_dest_sample, dft_rng_vctrl, dft_rng_rst_l, dft_tsr_div,
dft_tsr_tsel, dft_tsr_reset_l, testmode_l,
// Inputs
jbus_rst_l, io_tdi, io_tms, io_trst_l, io_tck, tck_l, jtag_id,
test_mode_pin, afi_rng_ctl, afi_tsr_div, afi_tsr_mode,
afi_pll_char_mode, afi_pll_div2, afi_pll_trst_l, afi_tsr_tsel,
afi_pll_clamp_fltr, creg_jtag_scratch_data, creg_jtag_rdrtrn_data,
creg_jtag_rdrtrn_vld, bist_jtag_result, bist_jtag_abort_done,
pll_bypass_pin, pll_reset_ref_l, spc0_ctu_sscan_out,
spc1_ctu_sscan_out, spc2_ctu_sscan_out, spc3_ctu_sscan_out,
spc4_ctu_sscan_out, spc5_ctu_sscan_out, spc6_ctu_sscan_out,
spc7_ctu_sscan_out, pads_ctu_bsi, pads_ctu_si,
sctag2_ctu_serial_scan_in, efc_ctu_data_out
);
//global interface
input jbus_rst_l;
//JTAG chip interface
input io_tdi;
input io_tms;
input io_trst_l;
input io_tck;
input tck_l;
output dft_tdo; //io_tdo;
output io_tdo_en;
// id info
input [3:0] jtag_id;
// test_mode pins
input test_mode_pin;
//input pscan_mode_pin;
//input shift_en_pin;
input [2:0] afi_rng_ctl;
input [9:1] afi_tsr_div;
input afi_tsr_mode;
input afi_pll_char_mode;
input [5:0] afi_pll_div2;
input afi_pll_trst_l;
input [7:0] afi_tsr_tsel;
input afi_pll_clamp_fltr;
//creg R/W interface
output [39:0] jtag_creg_addr; //address of internal register
output [63:0] jtag_creg_data; //data to load into internal register
output jtag_creg_rd_en;
output jtag_creg_wr_en;
output jtag_creg_addr_en;
output jtag_creg_data_en;
input [63:0] creg_jtag_scratch_data;
input [63:0] creg_jtag_rdrtrn_data;
input creg_jtag_rdrtrn_vld;
output jtag_creg_rdrtrn_complete;
// bist blk interface
//input bist_jtag_busy;
input [(`CTU_BIST_CNT*2)-1:0] bist_jtag_result;
input bist_jtag_abort_done;
output jtag_bist_serial;
output jtag_bist_parallel;
output [`CTU_BIST_CNT-1:0] jtag_bist_active;
output jtag_bist_abort;
// PLL and clock
input pll_bypass_pin;
input pll_reset_ref_l;
output [5:0] dft_pll_div2;
output dft_pll_arst_l;
output dft_pll_testmode;
output dft_pll_clamp_fltr;
output jtag_clsp_stop_id_vld;
output [5:0] jtag_clsp_stop_id;
output jtag_nstep_vld;
output [2:0] jtag_nstep_domain;
output [3:0] jtag_nstep_count;
output dft_clsp_nstep_capture_l;
output jtag_clock_dr;
output jtag_clsp_ignore_wrm_rst;
output jtag_clsp_sel_tck2;
//output jtag_clsp_force_cken;
output jtag_clsp_force_cken_cmp;
output jtag_clsp_force_cken_dram;
output jtag_clsp_force_cken_jbus;
//control interface
output pll_bypass;
output [2:0] ctu_sel_cpu;
output [2:0] ctu_sel_dram;
output [2:0] ctu_sel_jbus;
// shadow scan interface
input spc0_ctu_sscan_out;
input spc1_ctu_sscan_out;
input spc2_ctu_sscan_out;
input spc3_ctu_sscan_out;
input spc4_ctu_sscan_out;
input spc5_ctu_sscan_out;
input spc6_ctu_sscan_out;
input spc7_ctu_sscan_out;
output ctu_spc0_sscan_se;
output ctu_spc1_sscan_se;
output ctu_spc2_sscan_se;
output ctu_spc3_sscan_se;
output ctu_spc4_sscan_se;
output ctu_spc5_sscan_se;
output ctu_spc6_sscan_se;
output ctu_spc7_sscan_se;
output ctu_spc0_tck;
output ctu_spc1_tck;
output ctu_spc2_tck;
output ctu_spc3_tck;
output ctu_spc4_tck;
output ctu_spc5_tck;
output ctu_spc6_tck;
output ctu_spc7_tck;
output [3:0] ctu_spc_sscan_tid;
output ctu_pads_sscan_update;
output ctu_global_snap;
// Boundary Scan
output ctu_ddr0_mode_ctl;
output ctu_ddr0_hiz_l;
output ctu_ddr0_update_dr;
output ctu_ddr0_clock_dr;
output ctu_ddr0_shift_dr;
output ctu_ddr1_mode_ctl;
output ctu_ddr1_hiz_l;
output ctu_ddr1_update_dr;
output ctu_ddr1_clock_dr;
output ctu_ddr1_shift_dr;
output ctu_ddr2_mode_ctl;
output ctu_ddr2_hiz_l;
output ctu_ddr2_update_dr;
output ctu_ddr2_clock_dr;
output ctu_ddr2_shift_dr;
output ctu_ddr3_mode_ctl;
output ctu_ddr3_hiz_l;
output ctu_ddr3_update_dr;
output ctu_ddr3_clock_dr;
output ctu_ddr3_shift_dr;
output ctu_jbusl_mode_ctl;
output ctu_jbusl_hiz_l;
output ctu_jbusl_update_dr;
output ctu_jbusl_clock_dr;
output ctu_jbusl_shift_dr;
output ctu_jbusr_mode_ctl;
output ctu_jbusr_hiz_l;
output ctu_jbusr_update_dr;
output ctu_jbusr_clock_dr;
output ctu_jbusr_shift_dr;
output ctu_debug_mode_ctl;
output ctu_debug_hiz_l;
output ctu_debug_update_dr;
output ctu_debug_clock_dr;
output ctu_debug_shift_dr;
output ctu_misc_mode_ctl;
output ctu_misc_hiz_l;
output ctu_misc_update_dr;
output ctu_misc_clock_dr;
output ctu_misc_shift_dr;
output ctu_pads_bso;
input pads_ctu_bsi;
//scan signals
input pads_ctu_si;
input sctag2_ctu_serial_scan_in;
output global_shift_enable;
output global_scan_bypass_en;
output dft_ctu_scan_disable; //disable ctu cluster scan if not pin-based scan
output dft_pin_pscan_l; // select long chain is pin-based scan
output ctu_pads_so;
output ctu_fpu_so;
//pad connection for scan
output pscan_select;
// ctu and pad share scan chain
output ctu_ddr_testmode_l;
//cluster scanin
output ctu_tst_scanmode;
output ctu_tst_macrotest;
output ctu_tst_short_chain;
output ctu_tst_scan_disable;
// efuse shift interface (tck domain)
input efc_ctu_data_out; // Serial(scan) out from ctu
output ctu_efc_data_in; // Serial(scan) in to efc
output ctu_efc_updatedr;
output ctu_efc_shiftdr;
output ctu_efc_capturedr;
output ctu_efc_tck;
// efuse r/w interface
output [6:0] ctu_efc_rowaddr;
output [4:0] ctu_efc_coladdr;
output ctu_efc_read_en;
output [2:0] ctu_efc_read_mode;
output ctu_efc_fuse_bypass;
// efuse dest sample
output ctu_efc_dest_sample;
// random number generator
output [2:0] dft_rng_vctrl;
output dft_rng_rst_l;
// temperature sensor regulator
output [9:1] dft_tsr_div;
output [7:0] dft_tsr_tsel;
output dft_tsr_reset_l;
// CTU Internal scan
output testmode_l;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
reg [2:0] dft_rng_vctrl;
reg dft_rng_rst_l;
reg [9:1] dft_tsr_div;
reg [7:0] dft_tsr_tsel;
reg dft_tsr_reset_l;
reg [5:0] dft_pll_div2;
reg dft_pll_arst_l;
reg dft_pll_clamp_fltr;
reg ctu_pads_bso;
reg ctu_fpu_so;
reg [3:0] ctu_spc_sscan_tid;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
parameter TAP_CMD_LO = 0,
TAP_CMD_HI = `TAP_CMD_WIDTH - 1,
TAP_SSCAN_CFG_WIDTH = 8,
TAP_SSCAN_CFG_LO = TAP_CMD_HI + 1,
TAP_SSCAN_CFG_HI = TAP_SSCAN_CFG_LO + TAP_SSCAN_CFG_WIDTH - 1,
TAP_SSCAN_UPDATE = TAP_SSCAN_CFG_HI + 1,
TAP_MBIST_ACTIVE_WIDTH = `CTU_BIST_CNT,
TAP_MBIST_ACTIVE_LO = TAP_CMD_HI + 1,
TAP_MBIST_ACTIVE_HI = TAP_MBIST_ACTIVE_LO + TAP_MBIST_ACTIVE_WIDTH - 1,
TAP_CLK_STOP_ID_WIDTH = 6,
TAP_CLK_STOP_ID_LO = TAP_CMD_HI + 1,
TAP_CLK_STOP_ID_HI = TAP_CLK_STOP_ID_LO + TAP_CLK_STOP_ID_WIDTH - 1,
TAP_SUPPRESS_CAP_BIT = TAP_CMD_HI + 1,
TAP_CKEN_BIT = TAP_CMD_HI + 2,
TAP_SCAN_MODE_BIT = TAP_CMD_HI + 1,
TAP_SCAN_NSTEP_DOM_WIDTH = 3,
TAP_SCAN_NSTEP_CNT_WIDTH = 4,
TAP_SCAN_NSTEP_DOM_LO = TAP_CMD_HI + 1,
TAP_SCAN_NSTEP_DOM_HI = TAP_SCAN_NSTEP_DOM_LO + TAP_SCAN_NSTEP_DOM_WIDTH - 1,
TAP_SCAN_NSTEP_CNT_LO = TAP_SCAN_NSTEP_DOM_HI + 1,
TAP_SCAN_NSTEP_CNT_HI = TAP_SCAN_NSTEP_CNT_LO + TAP_SCAN_NSTEP_CNT_WIDTH - 1,
TAP_SCAN_CLK_SEL_WIDTH = 3,
TAP_SCAN_CLK_SEL_CPU_LO = TAP_CMD_HI + 1,
TAP_SCAN_CLK_SEL_CPU_HI = TAP_SCAN_CLK_SEL_CPU_LO + TAP_SCAN_CLK_SEL_WIDTH - 1,
TAP_SCAN_CLK_SEL_DRAM_LO = TAP_SCAN_CLK_SEL_CPU_HI + 1,
TAP_SCAN_CLK_SEL_DRAM_HI = TAP_SCAN_CLK_SEL_DRAM_LO + TAP_SCAN_CLK_SEL_WIDTH - 1,
TAP_SCAN_CLK_SEL_JBUS_LO = TAP_SCAN_CLK_SEL_DRAM_HI + 1,
TAP_SCAN_CLK_SEL_JBUS_HI = TAP_SCAN_CLK_SEL_JBUS_LO + TAP_SCAN_CLK_SEL_WIDTH - 1;
parameter TAP_SCAN_MODE_PARALLEL = 1'b1,
TAP_SCAN_MODE_SERIAL = 1'b0;
parameter JTAG_SDR_CNT_WIDTH = 4,
JTAG_CKEN_DRAM_WAIT = 4'd6,
JTAG_CKEN_JBUS_WAIT = 4'd6,
JTAG_CKEN_OTHER_WAIT = 4'd8;
wire [31:0] idcode;
wire [39:0] creg_addr;
wire [63:0] creg_wdata;
wire [64:0] creg_rdrtrn;
wire [63:0] scratch_reg;
wire instr_normal_scan;
wire instr_scan;
wire global_shift_enable_pre;
wire pscan_select_pre;
wire shadow_scan_instr;
wire [TAP_SSCAN_CFG_WIDTH-1:0] shadow_scan_config_reg;
wire [3:0] spc_sscan_tid;
wire suppress_capture_l;
wire pll_bypass_tap;
wire spc0_sscan_se_pre;
wire spc1_sscan_se_pre;
wire spc2_sscan_se_pre;
wire spc3_sscan_se_pre;
wire spc4_sscan_se_pre;
wire spc5_sscan_se_pre;
wire spc6_sscan_se_pre;
wire spc7_sscan_se_pre;
wire spc0_tck_pre;
wire spc1_tck_pre;
wire spc2_tck_pre;
wire spc3_tck_pre;
wire spc4_tck_pre;
wire spc5_tck_pre;
wire spc6_tck_pre;
wire spc7_tck_pre;
wire bscan_enable;
wire ddr0_clock_dr_pre;
wire ddr0_shift_dr_pre;
wire ddr1_clock_dr_pre;
wire ddr1_shift_dr_pre;
wire ddr2_clock_dr_pre;
wire ddr2_shift_dr_pre;
wire ddr3_clock_dr_pre;
wire ddr3_shift_dr_pre;
wire jbusl_clock_dr_pre;
wire jbusl_shift_dr_pre;
wire jbusr_clock_dr_pre;
wire jbusr_shift_dr_pre;
wire debug_clock_dr_pre;
wire debug_shift_dr_pre;
wire misc_clock_dr_pre;
wire misc_shift_dr_pre;
wire [6:0] efc_rowaddr;
wire [4:0] efc_coladdr;
wire [2:0] efc_read_mode;
wire efc_tck_pre;
wire [JTAG_SDR_CNT_WIDTH-1:0] scan_dump_shiftdr_cnt;
wire [JTAG_SDR_CNT_WIDTH-1:0] cken_dram_wait;
wire [JTAG_SDR_CNT_WIDTH-1:0] cken_jbus_wait;
wire [JTAG_SDR_CNT_WIDTH-1:0] cken_other_wait;
wire sel_tck2_pre;
wire nstep_mode;
reg [31:0] next_idcode;
reg [39:0] next_creg_addr;
reg [63:0] next_creg_wdata;
reg [64:0] next_creg_rdrtrn;
reg [63:0] next_scratch_reg;
wire next_instr_normal_scan;
wire next_instr_scan;
wire next_global_shift_enable_pre;
wire next_pscan_select_pre;
wire next_shadow_scan_instr;
wire [3:0] next_spc_sscan_tid;
reg [TAP_SSCAN_CFG_WIDTH-1:0] next_shadow_scan_config_reg;
wire next_pll_bypass_tap;
wire next_spc0_tck_pre;
wire next_spc1_tck_pre;
wire next_spc2_tck_pre;
wire next_spc3_tck_pre;
wire next_spc4_tck_pre;
wire next_spc5_tck_pre;
wire next_spc6_tck_pre;
wire next_spc7_tck_pre;
wire next_spc0_sscan_se_pre;
wire next_spc1_sscan_se_pre;
wire next_spc2_sscan_se_pre;
wire next_spc3_sscan_se_pre;
wire next_spc4_sscan_se_pre;
wire next_spc5_sscan_se_pre;
wire next_spc6_sscan_se_pre;
wire next_spc7_sscan_se_pre;
wire next_bscan_enable;
wire next_ddr0_clock_dr_pre;
wire next_ddr0_shift_dr_pre;
wire next_ddr1_clock_dr_pre;
wire next_ddr1_shift_dr_pre;
wire next_ddr2_clock_dr_pre;
wire next_ddr2_shift_dr_pre;
wire next_ddr3_clock_dr_pre;
wire next_ddr3_shift_dr_pre;
wire next_jbusl_clock_dr_pre;
wire next_jbusl_shift_dr_pre;
wire next_jbusr_clock_dr_pre;
wire next_jbusr_shift_dr_pre;
wire next_debug_clock_dr_pre;
wire next_debug_shift_dr_pre;
wire next_misc_clock_dr_pre;
wire next_misc_shift_dr_pre;
wire next_suppress_capture_l;
reg [6:0] next_efc_rowaddr;
reg [4:0] next_efc_coladdr;
reg [2:0] next_efc_read_mode;
wire next_efc_tck_pre;
reg next_nstep_mode;
reg [JTAG_SDR_CNT_WIDTH-1:0] next_scan_dump_shiftdr_cnt;
wire [JTAG_SDR_CNT_WIDTH-1:0] next_cken_dram_wait;
wire [JTAG_SDR_CNT_WIDTH-1:0] next_cken_jbus_wait;
wire [JTAG_SDR_CNT_WIDTH-1:0] next_cken_other_wait;
wire next_sel_tck2_pre;
wire creg_addr_shift;
wire creg_wdata_shift;
wire shadow_scan_config_reg_en;
reg [TAP_SSCAN_CFG_WIDTH-1:0] shadow_scan_config_mask;
reg shadow_scan_out;
wire pin_based_pscan_mode;
wire pin_based_shift_en;
wire pin_based_pll_bypass;
wire tap_rst_l;
wire tap_so;
wire tap_tdo_en;
wire tap_bypass_sel;
wire tap_clock_dr;
wire [`TAP_INSTR_WIDTH-1:0] tap_instructions;
wire [`TAP_INSTR_WIDTH-1:0] next_tap_instructions;
wire scratch_en_shift_dr;
wire scratch_reg_load;
wire instr_bypass;
wire instr_idcode;
wire instr_highz;
wire instr_clamp;
wire next_instr_highz;
wire next_instr_clamp;
wire next_instr_extest;
wire next_instr_sample_preload;
wire instr_creg_addr;
wire instr_creg_wdata;
wire instr_creg_rdata;
wire instr_creg_scratch;
wire instr_iob_wr;
wire instr_iob_rd;
wire instr_iob_rd_d1;
wire instr_iob_waddr;
wire instr_iob_wdata;
wire instr_iob_raddr;
wire instr_iob_raddr_d1;
wire instr_scan_parallel;
wire instr_scan_serial;
wire instr_scan_dump;
wire instr_scan_mtest;
wire next_instr_scan_parallel;
wire next_instr_scan_serial;
wire next_instr_scan_dump;
wire next_instr_scan_mtest_long;
wire next_instr_scan_mtest_short;
wire next_instr_scan_mtest;
wire next_instr_sscan_t0;
wire next_instr_sscan_t1;
wire next_instr_sscan_t2;
wire next_instr_sscan_t3;
wire instr_scan_bypass_en;
wire instr_scan_nstep;
wire instr_mbist_serial;
wire instr_mbist_parallel;
wire instr_mbist_result;
wire instr_mbist_abort;
wire next_instr_efc_read;
wire next_instr_efc_bypass_data;
wire next_instr_efc_bypass;
wire instr_efc_read;
wire instr_efc_bypass_data;
wire instr_efc_read_mode;
wire instr_efc_col_addr;
wire instr_efc_row_addr;
wire instr_efc_dest_sample;
wire instr_pll_bypass;
wire instr_clk_stop_id;
wire instr_clk_sel;
wire instr_efc_shift;
wire tap_capture_dr_state;
wire tap_shift_dr_state;
wire tap_shift_dr_state_d1;
wire tap_pause_dr_state;
wire tap_update_dr_state;
wire tap_shift_exit2_dr_state;
wire tap_update_ir_state;
wire creg_addr_instr;
wire creg_data_instr;
wire bist_result_reg_load;
wire bist_result_reg_shift;
wire [(`CTU_BIST_CNT*2)-1:0] bist_result_reg;
reg [(`CTU_BIST_CNT*2)-1:0] next_bist_result_reg;
wire toggle_pll_bypass_tap;
wire creg_rdrtrn_shift;
wire clear_creg_rdrtrn_vld;
wire creg_rdrtrn_vld;
wire next_creg_rdrtrn_vld;
wire creg_rdrtrn_out;
wire creg_rdrtrn_load;
wire creg_rdrtrn_load_d1;
wire creg_jtag_rdrtrn_vld_d;
wire creg_jtag_rdrtrn_vld_d2;
wire clock_dr_instr_scan_dump_capture;
wire [TAP_SCAN_CLK_SEL_WIDTH-1:0] clk_sel_cpu;
wire [TAP_SCAN_CLK_SEL_WIDTH-1:0] clk_sel_dram;
wire [TAP_SCAN_CLK_SEL_WIDTH-1:0] clk_sel_jbus;
wire [2:0] sel_cpu;
wire [2:0] sel_dram;
wire [2:0] sel_jbus;
wire [2:0] sel_cpu_ff;
wire [2:0] sel_dram_ff;
wire [2:0] sel_jbus_ff;
reg [2:0] next_sel_cpu_ff;
reg [2:0] next_sel_dram_ff;
reg [2:0] next_sel_jbus_ff;
wire next_jtag_bist_serial;
wire next_jtag_bist_parallel;
reg [TAP_MBIST_ACTIVE_WIDTH-1:0] next_jtag_bist_active;
wire efc_rowaddr_shift;
wire efc_coladdr_shift;
wire efc_read_mode_shift;
wire next_global_scan_bypass_en;
wire bscan_mode_ctl;
wire bscan_hiz_l;
wire bscan_update_dr;
wire bscan_clock_dr_pre;
wire bscan_shift_dr_pre;
wire next_ctu_ddr0_mode_ctl;
wire next_ctu_ddr0_hiz_l;
wire next_ctu_ddr0_update_dr;
wire next_ctu_ddr1_mode_ctl;
wire next_ctu_ddr1_hiz_l;
wire next_ctu_ddr1_update_dr;
wire next_ctu_ddr2_mode_ctl;
wire next_ctu_ddr2_hiz_l;
wire next_ctu_ddr2_update_dr;
wire next_ctu_ddr3_mode_ctl;
wire next_ctu_ddr3_hiz_l;
wire next_ctu_ddr3_update_dr;
wire next_ctu_jbusl_mode_ctl;
wire next_ctu_jbusl_hiz_l;
wire next_ctu_jbusl_update_dr;
wire next_ctu_jbusr_mode_ctl;
wire next_ctu_jbusr_hiz_l;
wire next_ctu_jbusr_update_dr;
wire next_ctu_debug_mode_ctl;
wire next_ctu_debug_hiz_l;
wire next_ctu_debug_update_dr;
wire next_ctu_misc_mode_ctl;
wire next_ctu_misc_hiz_l;
wire next_ctu_misc_update_dr;
wire pll_bypass;
wire dft_pin_pscan;
wire next_ctu_global_snap;
wire next_ctu_tst_macrotest;
wire next_ctu_tst_short_chain;
wire next_ctu_pads_sscan_update;
wire next_spc0_sscan;
wire next_spc1_sscan;
wire next_spc2_sscan;
wire next_spc3_sscan;
wire next_spc4_sscan;
wire next_spc5_sscan;
wire next_spc6_sscan;
wire next_spc7_sscan;
wire next_pads_sscan;
wire next_pads_sscan_se_pre;
wire next_pads_tck_pre;
wire next_ctu_efc_capturedr;
wire next_ctu_efc_shiftdr;
wire next_ctu_efc_updatedr;
wire next_ctu_efc_fuse_bypass;
wire next_ctu_efc_read_en;
wire next_ctu_efc_dest_sample;
wire [6:0] next_ctu_efc_rowaddr;
wire [4:0] next_ctu_efc_coladdr;
wire [2:0] next_ctu_efc_read_mode;
wire next_jtag_bist_abort;
wire next_jtag_creg_addr_en;
wire next_jtag_creg_wr_en;
wire next_jtag_creg_rd_en;
wire next_jtag_creg_data_en;
wire next_dft_clsp_nstep_capture_l;
wire next_jtag_clsp_force_cken_cmp;
wire next_jtag_clsp_force_cken_dram;
wire next_jtag_clsp_force_cken_jbus;
wire tap_update_ir_state_d1;
wire tap_update_ir_state_d2;
wire scan_dump_cken_cmp;
wire scan_dump_cken_dram;
wire scan_dump_cken_jbus;
wire scan_dump_cken_other;
wire normal_force_cken;
wire inc_scan_dump_shiftdr_cnt;
wire test_mode_pin_l;
wire trst;
wire global_scan_bypass_en_pre; // bug #5483
wire bypass_chain31; // bug #5581
reg pads_ctu_si_bypmux_out; // bug #5581
wire serial_scan; // bug #5695
wire pads_ctu_si_bypmux_out_ff; // bug #5696
//********************************************************************
// Pin-based operations
//********************************************************************
// use io_trst_l pin as pscan_mode_pin_l ans io_tms as shift_en_pin
// when test_mode_pin is asserted
//assign tap_rst_l = test_mode_pin | io_trst_l;
ctu_or2 u_or2_tap_rst_l (.a (test_mode_pin),
.b (io_trst_l),
.z (tap_rst_l)
);
//assign pin_based_pscan_mode = test_mode_pin & ~io_trst_l;
ctu_inv u_inv_test_mode_pin_l (.a (test_mode_pin),
.z (test_mode_pin_l)
);
ctu_nor2 u_nor2_pin_based_pscan_mode (.a(test_mode_pin_l),
.b(io_trst_l),
.z(pin_based_pscan_mode)
);
//assign pin_based_pll_bypass = test_mode_pin & pll_bypass_pin;
ctu_and2 u_and2_pin_based_pll_bypass (.a(test_mode_pin),
.b(pll_bypass_pin),
.z(pin_based_pll_bypass)
);
assign pin_based_shift_en = test_mode_pin & ~io_trst_l & io_tms;
//********************************************************************
// TAP Controller
//********************************************************************
ctu_dft_jtag_tap u_tap_controller (
// Inputs
.tck (io_tck),
.tck_l (tck_l),
.trst_n (tap_rst_l),
.tms (io_tms),
.tdi (io_tdi),
.so (tap_so),
.bypass_sel (tap_bypass_sel),
.dft_pin_pscan(dft_pin_pscan),
// Outputs
.capture_dr_state (tap_capture_dr_state),
.shift_dr_state (tap_shift_dr_state),
.pause_dr_state (tap_pause_dr_state),
.update_dr_state (tap_update_dr_state),
.shift_exit2_dr_state (tap_shift_exit2_dr_state),
.update_ir_state (tap_update_ir_state),
.clock_dr (tap_clock_dr),
.tdo (dft_tdo),
.tdo_en (tap_tdo_en),
.instructions (tap_instructions),
.next_instructions (next_tap_instructions)
);
//instruction decode
assign instr_bypass = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == {`TAP_CMD_WIDTH{1'b1}}
| (tap_instructions[TAP_CMD_HI:TAP_CMD_HI-3] == 4'b0001 // 0x05 thru 0x07
& (|tap_instructions[TAP_CMD_HI-4:TAP_CMD_LO]))
| (tap_instructions[TAP_CMD_HI:TAP_CMD_HI-3] == 4'b0100 // 0x11 thru 0x13
& (|tap_instructions[TAP_CMD_HI-4:TAP_CMD_LO]))
| tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == 6'h19
| tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == 6'h27
| tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == 6'h2F
| tap_instructions[TAP_CMD_HI:TAP_CMD_HI-1] == 2'd3;
assign instr_idcode = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_IDCODE;
assign instr_highz = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_HIGHZ;
assign instr_clamp = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_CLAMP;
assign next_instr_highz = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_HIGHZ;
assign next_instr_clamp = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_CLAMP;
assign next_instr_extest = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_EXTEST;
assign next_instr_sample_preload = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SAMPLE_PRELOAD;
assign instr_creg_addr = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_CREG_ADDR;
assign instr_creg_wdata = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_CREG_WDATA;
assign instr_creg_rdata = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_CREG_RDATA;
assign instr_creg_scratch = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_CREG_SCRATCH;
assign instr_iob_wr = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_IOB_WR;
assign instr_iob_rd = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_IOB_RD;
assign instr_iob_waddr = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_IOB_WADDR;
assign instr_iob_wdata = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_IOB_WDATA;
assign instr_iob_raddr = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_IOB_RADDR;
assign instr_scan_parallel = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_PARALLEL;
assign instr_scan_serial = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_SERIAL;
assign instr_scan_dump = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_DUMP;
assign next_instr_scan_parallel = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_PARALLEL;
assign next_instr_scan_serial = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_SERIAL;
assign next_instr_scan_mtest_long = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_MTEST_LONG;
assign next_instr_scan_mtest_short = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_MTEST_SHORT;
assign next_instr_scan_dump = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_DUMP;
assign next_instr_sscan_t0 = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SSCAN_T0;
assign next_instr_sscan_t1 = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SSCAN_T1;
assign next_instr_sscan_t2 = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SSCAN_T2;
assign next_instr_sscan_t3 = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SSCAN_T3;
assign instr_scan_bypass_en = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_BYPASS_EN;
assign instr_scan_nstep = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_NSTEP;
assign instr_mbist_serial = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_MBIST_SERIAL;
assign instr_mbist_parallel = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_MBIST_PARALLEL;
assign instr_mbist_result = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_MBIST_RESULT;
assign instr_mbist_abort = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_MBIST_ABORT;
assign next_instr_efc_read = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_EFC_READ;
assign next_instr_efc_bypass_data = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_EFC_BYPASS_DATA;
assign next_instr_efc_bypass = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_EFC_BYPASS;
assign instr_efc_read = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_EFC_READ;
assign instr_efc_bypass_data = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_EFC_BYPASS_DATA;
assign instr_efc_read_mode = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_EFC_READ_MODE;
assign instr_efc_col_addr = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_EFC_COL_ADDR;
assign instr_efc_row_addr = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_EFC_ROW_ADDR;
assign instr_efc_dest_sample = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_EFC_DEST_SAMPLE;
assign instr_pll_bypass = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_PLL_BYPASS;
assign instr_clk_stop_id = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_CLK_STOP_ID;
assign instr_clk_sel = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_CLK_SEL;
assign instr_scan_mtest = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_MTEST_LONG
| tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_MTEST_SHORT;
assign next_instr_scan_mtest = next_instr_scan_mtest_long | next_instr_scan_mtest_short;
assign instr_efc_shift = instr_efc_bypass_data
| instr_efc_read;
//tap_bypass_sel generation
assign tap_bypass_sel = instr_highz | instr_clamp | instr_bypass;
assign tap_so = // (idcode[31] & instr_idcode)
(idcode[0] & instr_idcode) // bug #5497
| (pads_ctu_bsi & bscan_enable)
| (creg_addr[39] & instr_creg_addr)
| (creg_wdata[63] & instr_creg_wdata)
| (scratch_reg[63] & instr_creg_scratch)
| (creg_rdrtrn_out & instr_creg_rdata)
//| (pads_ctu_si & instr_scan)
//| (pads_ctu_si_bypmux_out & instr_scan) // bug # 5581
| (pads_ctu_si_bypmux_out_ff & instr_scan) // bug # 5581 & bug #5696
| (efc_ctu_data_out & instr_efc_shift)
| (shadow_scan_out & shadow_scan_instr)
| (bist_result_reg[(`CTU_BIST_CNT*2)-1] & instr_mbist_result);
assign io_tdo_en = tap_tdo_en
| instr_creg_rdata
| dft_pin_pscan;
//********************************************************************
// IDCODE
//********************************************************************
always @ ( /*AUTOSENSE*/idcode or instr_idcode or io_tdi or jtag_id
or tap_capture_dr_state or tap_shift_dr_state) begin
if (instr_idcode & tap_capture_dr_state)
next_idcode = { jtag_id[3:0], `CTU_PART_ID, `CTU_MANUFACTURE_ID, 1'b1 };
else begin
if (instr_idcode & tap_shift_dr_state)
// next_idcode = { idcode[30:0], io_tdi };
next_idcode = { io_tdi, idcode[31:1] }; // bug #5497
else
next_idcode = idcode[31:0];
end
end
//********************************************************************
// CREG
//********************************************************************
//-----------------------
// address shift register
//-----------------------
assign creg_addr_instr = instr_creg_addr
| instr_iob_waddr
| instr_iob_raddr;
assign creg_addr_shift = creg_addr_instr & tap_shift_dr_state;
always @ ( /*AUTOSENSE*/creg_addr or creg_addr_shift or io_tdi) begin
if (creg_addr_shift)
next_creg_addr = { creg_addr[38:0], io_tdi };
else
next_creg_addr = creg_addr;
end
assign jtag_creg_addr = creg_addr[39:0];
//-----------------------
// data shift register
//-----------------------
assign creg_data_instr = instr_creg_wdata | instr_iob_wdata ;
assign creg_wdata_shift = creg_data_instr
& tap_shift_dr_state;
always @ ( /*AUTOSENSE*/creg_wdata or creg_wdata_shift or io_tdi) begin
if (creg_wdata_shift)
next_creg_wdata[63:0] = { creg_wdata[62:0], io_tdi };
else
next_creg_wdata[63:0] = creg_wdata[63:0];
end
assign jtag_creg_data = creg_wdata[63:0];
//------------------------------
//generate enables to creg block
//------------------------------
assign next_jtag_creg_addr_en = tap_update_dr_state & creg_addr_instr;
assign next_jtag_creg_wr_en = instr_iob_wr
| ( tap_update_dr_state
& ( instr_iob_wdata
| instr_iob_waddr));
assign next_jtag_creg_rd_en = instr_iob_rd
| tap_update_dr_state & instr_iob_raddr;
assign next_jtag_creg_data_en = tap_update_dr_state & creg_data_instr;
//---------------------
// Read Return Register
//---------------------
// Handshake with creg
// - load_l is generated on rising edge on creg_jtag_rdrtrn_vld
// - load delayed by one provides the output handshake to ctu_creg
assign creg_rdrtrn_load = creg_jtag_rdrtrn_vld & ~creg_jtag_rdrtrn_vld_d2;
assign jtag_creg_rdrtrn_complete = creg_rdrtrn_load_d1;
// start shifting out read data once it is valid
assign creg_rdrtrn_shift = instr_creg_rdata & tap_shift_dr_state & creg_rdrtrn_vld;
always @ ( /*AUTOSENSE*/creg_jtag_rdrtrn_data or creg_rdrtrn
or creg_rdrtrn_load or creg_rdrtrn_shift or io_tdi) begin
if (creg_rdrtrn_load)
next_creg_rdrtrn[64:0] = { 1'b1, creg_jtag_rdrtrn_data };
else begin
if (creg_rdrtrn_shift)
next_creg_rdrtrn[64:0] = { creg_rdrtrn[63:0], io_tdi };
else
next_creg_rdrtrn[64:0] = creg_rdrtrn[64:0];
end
end
// set when load data into read-return_reg
assign clear_creg_rdrtrn_vld = (instr_iob_rd & ~instr_iob_rd_d1)
| (instr_iob_raddr & ~instr_iob_raddr_d1);
assign next_creg_rdrtrn_vld = creg_rdrtrn_load
| (creg_rdrtrn_vld & ~clear_creg_rdrtrn_vld);
assign creg_rdrtrn_out = creg_rdrtrn[64] & creg_rdrtrn_vld;
//---------------------
// Scratch Register
//---------------------
assign scratch_en_shift_dr = instr_creg_scratch & tap_shift_dr_state;
assign scratch_reg_load = instr_creg_scratch & tap_capture_dr_state;
always @ ( /*AUTOSENSE*/creg_jtag_scratch_data or io_tdi
or scratch_en_shift_dr or scratch_reg or scratch_reg_load) begin
if (scratch_reg_load)
next_scratch_reg[63:0] = creg_jtag_scratch_data;
else begin
if (scratch_en_shift_dr)
next_scratch_reg[63:0] = { scratch_reg[62:0], io_tdi };
else
next_scratch_reg[63:0] = scratch_reg[63:0];
end
end
//*******************************************************************
// Internal Scan
// - parallel and serial scan
// - macro test
//********************************************************************
// to test stub
// do precalc for timing
assign next_instr_normal_scan = next_instr_scan_parallel
| next_instr_scan_serial
| next_instr_scan_mtest_long
| next_instr_scan_mtest_short;
assign next_instr_scan = next_instr_normal_scan | next_instr_scan_dump;
assign next_global_shift_enable_pre = ( instr_normal_scan
| scan_dump_cken_cmp )
& ( tap_shift_exit2_dr_state
| tap_shift_dr_state_d1); //extend shift_en by 1 cycle to ensure deassert after clock_dr (SRAM)
assign global_shift_enable = (global_shift_enable_pre & ~pin_based_pscan_mode)
| pin_based_shift_en;
assign ctu_tst_scanmode = instr_scan
| pin_based_pscan_mode; //needs to be asserted during pin base scan
assign next_ctu_tst_macrotest = next_instr_scan_mtest_long
| next_instr_scan_mtest_short;
assign next_ctu_tst_short_chain = next_instr_scan_mtest_short;
// Reuse unused ctu_tst_scan_disable as "short_scan_disable"
assign ctu_tst_scan_disable = pin_based_pscan_mode;
// ctu and pads in same scan chain
assign ctu_ddr_testmode_l = ~ctu_tst_scanmode;
// boundary scan cell
// negedge
assign next_global_scan_bypass_en = global_scan_bypass_en
^ (instr_scan_bypass_en & tap_update_ir_state_d1); //toggle cmd
// bug #5483
assign global_scan_bypass_en = global_scan_bypass_en_pre
& ~pin_based_shift_en;
// to pad cluster scan multiplexers
assign next_pscan_select_pre = next_instr_scan_parallel
| ( (next_instr_scan_dump | next_instr_scan_mtest)
& next_tap_instructions[TAP_SCAN_MODE_BIT] == TAP_SCAN_MODE_PARALLEL);
assign pscan_select = pin_based_pscan_mode | pscan_select_pre;
// si to pad cluster internal scan
assign ctu_pads_so = io_tdi;
assign dft_pin_pscan = pin_based_pscan_mode;
assign dft_pin_pscan_l = ~pin_based_pscan_mode;
// for pin-based parallel scan, ctu scan chain is included
assign dft_ctu_scan_disable = ~dft_pin_pscan;
// hookup for short vs. long chain in test stub
// - long chain activated during pin-based parallel scan
// - long chain includes boundary scan and ctu
always @ ( /*AUTOSENSE*/dft_pin_pscan or io_tdi
or pads_ctu_si_bypmux_out) begin
if (dft_pin_pscan)
// ctu_pads_bso = pads_ctu_si; // feeds pad cluster internal scan so to boudary scan si
ctu_pads_bso = pads_ctu_si_bypmux_out; // bug #5581
else
ctu_pads_bso = io_tdi;
end
// bug #5581
assign bypass_chain31 = global_scan_bypass_en
& ~pin_based_shift_en
& tap_instructions[8];
always @ ( /*AUTOSENSE*/bypass_chain31 or ctu_fpu_so or pads_ctu_si) begin
if (bypass_chain31)
pads_ctu_si_bypmux_out = ctu_fpu_so;
else
pads_ctu_si_bypmux_out = pads_ctu_si;
end
// CTU internal testmode_l - really means "pin-based parallel scan mode"
// force on all clock enables
assign testmode_l = ~pin_based_pscan_mode;
assign jtag_clsp_ignore_wrm_rst = instr_scan;
// scan clock to be distributed during internal scan
assign next_suppress_capture_l = ~(tap_capture_dr_state
& (next_instr_scan_dump
| (next_tap_instructions[TAP_SUPPRESS_CAP_BIT]
& ~nstep_mode
& (next_instr_scan_parallel | next_instr_scan_serial))));
ctu_and2 u_and2_clock_dr_scan_dump_cap
( .a(tap_clock_dr),
.b(suppress_capture_l),
.z(clock_dr_instr_scan_dump_capture)
);
ctu_mux21 u_mux21_jtag_clock_dr
( .d0(clock_dr_instr_scan_dump_capture),
.d1(io_tck),
.s (pin_based_pscan_mode),
.z (jtag_clock_dr)
);
//always @ ( /*AUTOSENSE*/ )
// jtag_clock_dr = io_tck;
// else
// jtag_clock_dr = tap_clock_dr & suppress_capture_l;
//end
//********************************************************************
// Boundary Scan
// - because IO shadow scan chanin is part of boundary scan, need
// to assert some boundary scan signals during IO shadow scan
// (bscan_clock_dr_out and bscan_shift_dr_out)
// - negedge
//********************************************************************
assign next_bscan_enable = next_instr_extest
| next_instr_sample_preload;
assign bscan_mode_ctl = next_instr_extest
| next_instr_clamp
| next_instr_highz;
assign bscan_hiz_l = ~next_instr_highz;
assign bscan_update_dr = next_bscan_enable & tap_update_dr_state;
assign bscan_clock_dr_pre = (next_bscan_enable
& ( tap_capture_dr_state
| tap_shift_dr_state))
| next_pads_tck_pre;
assign bscan_shift_dr_pre = (next_bscan_enable & tap_shift_exit2_dr_state)
| next_pads_sscan_se_pre;
// to pad_ddr0
assign next_ctu_ddr0_mode_ctl = bscan_mode_ctl;
assign next_ctu_ddr0_hiz_l = bscan_hiz_l;
assign next_ctu_ddr0_update_dr = bscan_update_dr;
assign next_ddr0_clock_dr_pre = bscan_clock_dr_pre;
assign next_ddr0_shift_dr_pre = bscan_shift_dr_pre;
assign ctu_ddr0_clock_dr = (ddr0_clock_dr_pre | pin_based_pscan_mode) & io_tck;
assign ctu_ddr0_shift_dr = ddr0_shift_dr_pre | pin_based_shift_en;
// to pad_ddr1
assign next_ctu_ddr1_mode_ctl = bscan_mode_ctl;
assign next_ctu_ddr1_hiz_l = bscan_hiz_l;
assign next_ctu_ddr1_update_dr = bscan_update_dr;
assign next_ddr1_clock_dr_pre = bscan_clock_dr_pre;
assign next_ddr1_shift_dr_pre = bscan_shift_dr_pre;
assign ctu_ddr1_clock_dr = (ddr1_clock_dr_pre | pin_based_pscan_mode) & io_tck;
assign ctu_ddr1_shift_dr = ddr1_shift_dr_pre | pin_based_shift_en;
// to pad_ddr2
assign next_ctu_ddr2_mode_ctl = bscan_mode_ctl;
assign next_ctu_ddr2_hiz_l = bscan_hiz_l;
assign next_ctu_ddr2_update_dr = bscan_update_dr;
assign next_ddr2_clock_dr_pre = bscan_clock_dr_pre;
assign next_ddr2_shift_dr_pre = bscan_shift_dr_pre;
assign ctu_ddr2_clock_dr = (ddr2_clock_dr_pre | pin_based_pscan_mode) & io_tck;
assign ctu_ddr2_shift_dr = ddr2_shift_dr_pre | pin_based_shift_en;
// to pad_ddr3
assign next_ctu_ddr3_mode_ctl = bscan_mode_ctl;
assign next_ctu_ddr3_hiz_l = bscan_hiz_l;
assign next_ctu_ddr3_update_dr = bscan_update_dr;
assign next_ddr3_clock_dr_pre = bscan_clock_dr_pre;
assign next_ddr3_shift_dr_pre = bscan_shift_dr_pre;
assign ctu_ddr3_clock_dr = (ddr3_clock_dr_pre | pin_based_pscan_mode) & io_tck;
assign ctu_ddr3_shift_dr = ddr3_shift_dr_pre | pin_based_shift_en;
// to pad_jbusl
assign next_ctu_jbusl_mode_ctl = bscan_mode_ctl;
assign next_ctu_jbusl_hiz_l = bscan_hiz_l;
assign next_ctu_jbusl_update_dr = bscan_update_dr;
assign next_jbusl_clock_dr_pre = bscan_clock_dr_pre;
assign next_jbusl_shift_dr_pre = bscan_shift_dr_pre;
assign ctu_jbusl_clock_dr = (jbusl_clock_dr_pre | pin_based_pscan_mode) & io_tck;
assign ctu_jbusl_shift_dr = jbusl_shift_dr_pre | pin_based_shift_en;
// to pad_jbusr
assign next_ctu_jbusr_mode_ctl = bscan_mode_ctl;
assign next_ctu_jbusr_hiz_l = bscan_hiz_l;
assign next_ctu_jbusr_update_dr = bscan_update_dr;
assign next_jbusr_clock_dr_pre = bscan_clock_dr_pre;
assign next_jbusr_shift_dr_pre = bscan_shift_dr_pre;
assign ctu_jbusr_clock_dr = (jbusr_clock_dr_pre | pin_based_pscan_mode) & io_tck;
assign ctu_jbusr_shift_dr = jbusr_shift_dr_pre | pin_based_shift_en;
// to pad_debug
assign next_ctu_debug_mode_ctl = bscan_mode_ctl;
assign next_ctu_debug_hiz_l = bscan_hiz_l;
assign next_ctu_debug_update_dr = bscan_update_dr;
assign next_debug_clock_dr_pre = bscan_clock_dr_pre;
assign next_debug_shift_dr_pre = bscan_shift_dr_pre;
assign ctu_debug_clock_dr = (debug_clock_dr_pre | pin_based_pscan_mode) & io_tck;
assign ctu_debug_shift_dr = debug_shift_dr_pre | pin_based_shift_en;
// to pad_misc
assign next_ctu_misc_mode_ctl = bscan_mode_ctl;
assign next_ctu_misc_hiz_l = bscan_hiz_l;
assign next_ctu_misc_update_dr = bscan_update_dr;
assign next_misc_clock_dr_pre = bscan_clock_dr_pre;
assign next_misc_shift_dr_pre = bscan_shift_dr_pre;
assign ctu_misc_clock_dr = (misc_clock_dr_pre | pin_based_pscan_mode) & io_tck;
assign ctu_misc_shift_dr = misc_shift_dr_pre | pin_based_shift_en;
//********************************************************************
// Shadow Scan
//********************************************************************
assign next_shadow_scan_instr = next_instr_sscan_t0
| next_instr_sscan_t1
| next_instr_sscan_t2
| next_instr_sscan_t3;
// Always snap except in capture_dr state when tck toggles once to
// capture
assign next_ctu_global_snap = next_shadow_scan_instr & ~tap_capture_dr_state;
assign next_spc_sscan_tid[3:0] = { next_instr_sscan_t3,
next_instr_sscan_t2,
next_instr_sscan_t1,
( next_instr_sscan_t0 // always have at least one bit of tid asserted
| ~( next_instr_sscan_t1
| next_instr_sscan_t2
| next_instr_sscan_t3)) };
// ensure one-hot during scan
always @ ( /*AUTOSENSE*/global_shift_enable or spc_sscan_tid) begin
if (global_shift_enable)
ctu_spc_sscan_tid[3:0] = 4'b0001;
else
ctu_spc_sscan_tid[3:0] = spc_sscan_tid[3:0];
end
//----------------------------
// Shadow Scan Config Register
//----------------------------
assign shadow_scan_config_reg_en = shadow_scan_instr
& ( tap_update_ir_state
| tap_pause_dr_state);
always @ ( /*AUTOSENSE*/shadow_scan_config_mask
or shadow_scan_config_reg or shadow_scan_config_reg_en
or tap_instructions or tap_update_ir_state) begin
if (shadow_scan_config_reg_en) begin
if (tap_update_ir_state) // new shadow scan instr
next_shadow_scan_config_reg = tap_instructions[TAP_SSCAN_CFG_HI:TAP_SSCAN_CFG_LO];
else
next_shadow_scan_config_reg = shadow_scan_config_reg & shadow_scan_config_mask;
end
else
next_shadow_scan_config_reg = shadow_scan_config_reg;
end
always @ ( /*AUTOSENSE*/shadow_scan_config_reg) begin
casex (shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1:0])
8'b1???_????: shadow_scan_config_mask = { 1'b0, {TAP_SSCAN_CFG_WIDTH-1{1'b1}} };
8'b01??_????: shadow_scan_config_mask = { {2{1'b0}}, {TAP_SSCAN_CFG_WIDTH-2{1'b1}} };
8'b001?_????: shadow_scan_config_mask = { {3{1'b0}}, {TAP_SSCAN_CFG_WIDTH-3{1'b1}} };
8'b0001_????: shadow_scan_config_mask = { {4{1'b0}}, {TAP_SSCAN_CFG_WIDTH-4{1'b1}} };
8'b0000_1???: shadow_scan_config_mask = { {5{1'b0}}, {TAP_SSCAN_CFG_WIDTH-5{1'b1}} };
8'b0000_01??: shadow_scan_config_mask = { {6{1'b0}}, {TAP_SSCAN_CFG_WIDTH-6{1'b1}} };
8'b0000_001?: shadow_scan_config_mask = { {7{1'b0}}, 1'b1 };
default: shadow_scan_config_mask = {TAP_SSCAN_CFG_WIDTH{1'b0}};
endcase
end
//----------------------------
// shadow scan shift enable
//----------------------------
assign next_spc0_sscan = next_shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1] == 1'b1;
assign next_spc1_sscan = next_shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1:TAP_SSCAN_CFG_WIDTH-2] == 2'b01;
assign next_spc2_sscan = next_shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1:TAP_SSCAN_CFG_WIDTH-3] == 3'b001;
assign next_spc3_sscan = next_shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1:TAP_SSCAN_CFG_WIDTH-4] == 4'b0001;
assign next_spc4_sscan = next_shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1:TAP_SSCAN_CFG_WIDTH-5] == 5'b0000_1;
assign next_spc5_sscan = next_shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1:TAP_SSCAN_CFG_WIDTH-6] == 6'b0000_01;
assign next_spc6_sscan = next_shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1:TAP_SSCAN_CFG_WIDTH-7] == 7'b0000_001;
assign next_spc7_sscan = next_shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1: 0] == 8'b0000_0001;
assign next_pads_sscan = next_shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1: 0] == 8'b0000_0000;
//negedge
assign next_spc0_sscan_se_pre = tap_shift_exit2_dr_state
& (next_instr_scan
| (next_shadow_scan_instr & next_spc0_sscan));
assign next_spc1_sscan_se_pre = tap_shift_exit2_dr_state
& (next_instr_scan
| (next_shadow_scan_instr & next_spc1_sscan));
assign next_spc2_sscan_se_pre = tap_shift_exit2_dr_state
& (next_instr_scan
| (next_shadow_scan_instr & next_spc2_sscan));
assign next_spc3_sscan_se_pre = tap_shift_exit2_dr_state
& (next_instr_scan
| (next_shadow_scan_instr & next_spc3_sscan));
assign next_spc4_sscan_se_pre = tap_shift_exit2_dr_state
& (next_instr_scan
| (next_shadow_scan_instr & next_spc4_sscan));
assign next_spc5_sscan_se_pre = tap_shift_exit2_dr_state
& (next_instr_scan
| (next_shadow_scan_instr & next_spc5_sscan));
assign next_spc6_sscan_se_pre = tap_shift_exit2_dr_state
& (next_instr_scan
| (next_shadow_scan_instr & next_spc6_sscan));
assign next_spc7_sscan_se_pre = tap_shift_exit2_dr_state
& (next_instr_scan
| (next_shadow_scan_instr & next_spc7_sscan));
assign next_pads_sscan_se_pre = tap_shift_exit2_dr_state
& (next_instr_scan
| (next_shadow_scan_instr & next_pads_sscan));
assign ctu_spc0_sscan_se = spc0_sscan_se_pre | pin_based_shift_en;
assign ctu_spc1_sscan_se = spc1_sscan_se_pre | pin_based_shift_en;
assign ctu_spc2_sscan_se = spc2_sscan_se_pre | pin_based_shift_en;
assign ctu_spc3_sscan_se = spc3_sscan_se_pre | pin_based_shift_en;
assign ctu_spc4_sscan_se = spc4_sscan_se_pre | pin_based_shift_en;
assign ctu_spc5_sscan_se = spc5_sscan_se_pre | pin_based_shift_en;
assign ctu_spc6_sscan_se = spc6_sscan_se_pre | pin_based_shift_en;
assign ctu_spc7_sscan_se = spc7_sscan_se_pre | pin_based_shift_en;
//----------------------------
// shadow scan tck
//----------------------------
//negedge
assign next_spc0_tck_pre = ( tap_capture_dr_state
& next_shadow_scan_instr)
| ( tap_shift_dr_state
& (next_instr_normal_scan
| scan_dump_cken_other
| (next_shadow_scan_instr & next_spc0_sscan)) );
assign next_spc1_tck_pre = ( tap_capture_dr_state
& next_shadow_scan_instr)
| ( tap_shift_dr_state
& (next_instr_normal_scan
| scan_dump_cken_other
| (next_shadow_scan_instr & next_spc1_sscan)) );
assign next_spc2_tck_pre = ( tap_capture_dr_state
& next_shadow_scan_instr)
| ( tap_shift_dr_state
& (next_instr_normal_scan
| scan_dump_cken_other
| (next_shadow_scan_instr & next_spc2_sscan)) );
assign next_spc3_tck_pre = ( tap_capture_dr_state
& next_shadow_scan_instr)
| ( tap_shift_dr_state
& (next_instr_normal_scan
| scan_dump_cken_other
| (next_shadow_scan_instr & next_spc3_sscan)) );
assign next_spc4_tck_pre = ( tap_capture_dr_state
& next_shadow_scan_instr)
| ( tap_shift_dr_state
& (next_instr_normal_scan
| scan_dump_cken_other
| (next_shadow_scan_instr & next_spc4_sscan)) );
assign next_spc5_tck_pre = ( tap_capture_dr_state
& next_shadow_scan_instr)
| ( tap_shift_dr_state
& (next_instr_normal_scan
| scan_dump_cken_other
| (next_shadow_scan_instr & next_spc5_sscan)) );
assign next_spc6_tck_pre = ( tap_capture_dr_state
& next_shadow_scan_instr)
| ( tap_shift_dr_state
& (next_instr_normal_scan
| scan_dump_cken_other
| (next_shadow_scan_instr & next_spc6_sscan)) );
assign next_spc7_tck_pre = ( tap_capture_dr_state
& next_shadow_scan_instr)
| ( tap_shift_dr_state
& (next_instr_normal_scan
| scan_dump_cken_other
| (next_shadow_scan_instr & next_spc7_sscan)) );
assign next_pads_tck_pre = ( tap_capture_dr_state
& next_shadow_scan_instr)
| ( tap_shift_dr_state
& (next_instr_normal_scan
| scan_dump_cken_other
| (next_shadow_scan_instr & next_pads_sscan)) );
assign ctu_spc0_tck = io_tck & (spc0_tck_pre | pin_based_pscan_mode);
assign ctu_spc1_tck = io_tck & (spc1_tck_pre | pin_based_pscan_mode);
assign ctu_spc2_tck = io_tck & (spc2_tck_pre | pin_based_pscan_mode);
assign ctu_spc3_tck = io_tck & (spc3_tck_pre | pin_based_pscan_mode);
assign ctu_spc4_tck = io_tck & (spc4_tck_pre | pin_based_pscan_mode);
assign ctu_spc5_tck = io_tck & (spc5_tck_pre | pin_based_pscan_mode);
assign ctu_spc6_tck = io_tck & (spc6_tck_pre | pin_based_pscan_mode);
assign ctu_spc7_tck = io_tck & (spc7_tck_pre | pin_based_pscan_mode);
//----------------------------
// shadow scan out
//----------------------------
always @ ( /*AUTOSENSE*/pads_ctu_bsi or shadow_scan_config_reg
or spc0_ctu_sscan_out or spc1_ctu_sscan_out
or spc2_ctu_sscan_out or spc3_ctu_sscan_out
or spc4_ctu_sscan_out or spc5_ctu_sscan_out
or spc6_ctu_sscan_out or spc7_ctu_sscan_out) begin
casex (shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1:0])
8'b1???_????: shadow_scan_out = spc0_ctu_sscan_out;
8'b01??_????: shadow_scan_out = spc1_ctu_sscan_out;
8'b001?_????: shadow_scan_out = spc2_ctu_sscan_out;
8'b0001_????: shadow_scan_out = spc3_ctu_sscan_out;
8'b0000_1???: shadow_scan_out = spc4_ctu_sscan_out;
8'b0000_01??: shadow_scan_out = spc5_ctu_sscan_out;
8'b0000_001?: shadow_scan_out = spc6_ctu_sscan_out;
8'b0000_0001: shadow_scan_out = spc7_ctu_sscan_out;
default: shadow_scan_out = pads_ctu_bsi;
endcase
end
// Update-DR: the contents of the shadow chain are latched in the io registers
assign next_ctu_pads_sscan_update = next_shadow_scan_instr
& next_shadow_scan_config_reg == 8'd0
& (tap_update_dr_state
& next_tap_instructions[TAP_SSCAN_UPDATE]);
//********************************************************************
// MBIST
//********************************************************************
// Tell mbist control blk to start MBIST
// - once mbist is kicked off, does not stop until done, unless receive an abort
// - if bist sm has not completed previous bist, new bist instruction will be ignored
assign next_jtag_bist_serial = instr_mbist_serial
& (tap_update_ir_state_d1 | tap_update_ir_state_d2);
assign next_jtag_bist_parallel = instr_mbist_parallel
& (tap_update_ir_state_d1 | tap_update_ir_state_d2);
always @ ( /*AUTOSENSE*/instr_mbist_parallel or instr_mbist_serial
or jtag_bist_active or tap_instructions
or tap_update_ir_state_d1) begin
if ( (instr_mbist_serial & tap_update_ir_state_d1)
| (instr_mbist_parallel & tap_update_ir_state_d1) )
next_jtag_bist_active = tap_instructions[TAP_MBIST_ACTIVE_HI:TAP_MBIST_ACTIVE_LO];
else
next_jtag_bist_active = jtag_bist_active;
end
// MBIST Abort
assign next_jtag_bist_abort = (instr_mbist_abort & tap_update_ir_state_d1)
| (jtag_bist_abort & ~bist_jtag_abort_done);
// MBIST Result Register
assign bist_result_reg_load = instr_mbist_result & tap_capture_dr_state;
assign bist_result_reg_shift = instr_mbist_result & tap_shift_dr_state;
always @ ( /*AUTOSENSE*/bist_jtag_result or bist_result_reg
or bist_result_reg_load or bist_result_reg_shift or io_tdi) begin
if (bist_result_reg_load)
next_bist_result_reg = bist_jtag_result;
else begin
if (bist_result_reg_shift)
next_bist_result_reg = { bist_result_reg[(`CTU_BIST_CNT*2)-2:0], io_tdi };
else
next_bist_result_reg = bist_result_reg;
end
end
//********************************************************************
// Efuse
//********************************************************************
//------------------------
// Shift Interface
//------------------------
assign next_ctu_efc_capturedr = tap_capture_dr_state
& ( next_instr_efc_bypass_data
| next_instr_efc_bypass
| next_instr_efc_read);
assign next_ctu_efc_shiftdr = tap_shift_dr_state
& ( next_instr_efc_bypass_data
| next_instr_efc_read);
assign next_ctu_efc_updatedr = tap_update_dr_state
& ( next_instr_efc_bypass_data
| next_instr_efc_bypass
| next_instr_efc_read);
assign next_efc_tck_pre = next_ctu_efc_capturedr
| next_ctu_efc_shiftdr
| ( tap_shift_dr_state
& (next_instr_normal_scan | scan_dump_cken_other));
assign ctu_efc_tck = io_tck
& ( efc_tck_pre
| pin_based_pscan_mode);
assign ctu_efc_data_in = io_tdi;
//------------------------
// R/W Interface
//------------------------
assign next_ctu_efc_fuse_bypass = next_instr_efc_bypass;
assign next_ctu_efc_read_en = next_instr_efc_read;
// row address
assign efc_rowaddr_shift = instr_efc_row_addr & tap_shift_dr_state;
always @ ( /*AUTOSENSE*/efc_rowaddr or efc_rowaddr_shift or io_tdi) begin
if (efc_rowaddr_shift)
next_efc_rowaddr[6:0] = { efc_rowaddr[5:0], io_tdi };
else
next_efc_rowaddr[6:0] = efc_rowaddr[6:0];
end
assign next_ctu_efc_rowaddr = efc_rowaddr; //negedge
// column address
assign efc_coladdr_shift = instr_efc_col_addr & tap_shift_dr_state;
always @ ( /*AUTOSENSE*/efc_coladdr or efc_coladdr_shift or io_tdi) begin
if (efc_coladdr_shift)
next_efc_coladdr[4:0] = { efc_coladdr[3:0], io_tdi };
else
next_efc_coladdr[4:0] = efc_coladdr[4:0];
end
assign next_ctu_efc_coladdr = efc_coladdr; //negedge
// read mode
assign efc_read_mode_shift = instr_efc_read_mode & tap_shift_dr_state;
always @ ( /*AUTOSENSE*/efc_read_mode or efc_read_mode_shift or io_tdi) begin
if (efc_read_mode_shift)
next_efc_read_mode[2:0] = { efc_read_mode[1:0], io_tdi };
else
next_efc_read_mode[2:0] = efc_read_mode[2:0];
end
assign next_ctu_efc_read_mode = efc_read_mode; //negedge
//------------------------
// Destination Sample
//------------------------
// negedge
assign next_ctu_efc_dest_sample = instr_efc_dest_sample & tap_update_ir_state_d1;
//********************************************************************
// Clock Control
//********************************************************************
//------------------------
// clk_sel
//------------------------
//default value of ctu_sel_* at reset is 3'b111
// value of ctu_sel* is held until next (tap_instructions[4:0] == `TAP_CLK_SEL)
assign clk_sel_cpu = next_tap_instructions[TAP_SCAN_CLK_SEL_CPU_HI :TAP_SCAN_CLK_SEL_CPU_LO];
assign clk_sel_dram = next_tap_instructions[TAP_SCAN_CLK_SEL_DRAM_HI:TAP_SCAN_CLK_SEL_DRAM_LO];
assign clk_sel_jbus = next_tap_instructions[TAP_SCAN_CLK_SEL_JBUS_HI:TAP_SCAN_CLK_SEL_JBUS_LO];
assign sel_cpu[0] = clk_sel_cpu[0]; // normal
assign sel_cpu[1] = ~clk_sel_cpu[0] & clk_sel_cpu[1] & clk_sel_cpu[2]; // io_tck mode
assign sel_cpu[2] = ~clk_sel_cpu[0] & clk_sel_cpu[1] & ~clk_sel_cpu[2]; // pll_bypass
assign sel_dram[0] = clk_sel_dram[0]; // normal
assign sel_dram[1] = ~clk_sel_dram[0] & clk_sel_dram[1] & clk_sel_dram[2]; // io_tck mode
assign sel_dram[2] = ~clk_sel_dram[0] & clk_sel_dram[1] & ~clk_sel_dram[2]; // pll_bypass
assign sel_jbus[0] = clk_sel_jbus[0]; // normal
assign sel_jbus[1] = ~clk_sel_jbus[0] & clk_sel_jbus[1] & clk_sel_jbus[2]; // io_tck mode
assign sel_jbus[2] = ~clk_sel_jbus[0] & clk_sel_jbus[1] & ~clk_sel_jbus[2]; // pll_bypass
// negedge
always @ ( /*AUTOSENSE*/instr_clk_sel or instr_scan or pll_bypass_tap
or sel_cpu or sel_cpu_ff or sel_dram or sel_dram_ff
or sel_jbus or sel_jbus_ff or tap_update_ir_state_d1) begin
if (pll_bypass_tap) begin
next_sel_cpu_ff = 3'b100; // pll_bypass mode
next_sel_dram_ff = 3'b001; // normal
next_sel_jbus_ff = 3'b100; // pll_bypass mode
end
else if (tap_update_ir_state_d1 & instr_scan) begin // auto clock sel for internal scan instructions
next_sel_cpu_ff[2:0] = 3'b010; // tck mode
next_sel_dram_ff[2:0] = 3'b010;
next_sel_jbus_ff[2:0] = 3'b010;
end
else if (tap_update_ir_state_d1 & instr_clk_sel) begin // manual clock sel through tap
next_sel_cpu_ff[2:0] = sel_cpu[2:0];
next_sel_dram_ff[2:0] = sel_dram[2:0];
next_sel_jbus_ff[2:0] = sel_jbus[2:0];
end
else begin
next_sel_cpu_ff[2:0] = sel_cpu_ff[2:0];
next_sel_dram_ff[2:0] = sel_dram_ff[2:0];
next_sel_jbus_ff[2:0] = sel_jbus_ff[2:0];
end
end
//always @ ( /*AUTOSENSE*/pin_based_pll_bypass or pin_based_pscan_mode
// or sel_cpu_ff or sel_dram_ff or sel_jbus_ff) begin
// if (pin_based_pscan_mode) begin
// ctu_sel_cpu = 3'b010; // tck mode
// ctu_sel_dram = 3'b010;
// ctu_sel_jbus = 3'b010;
// end
// else if (pin_based_pll_bypass) begin
// ctu_sel_cpu = 3'b100; // pll_bypass mode
// ctu_sel_dram = 3'b001; // normal
// ctu_sel_jbus = 3'b100; // pll_bypass mode
// end
// else begin
// ctu_sel_cpu = sel_cpu_ff;
// ctu_sel_dram = sel_dram_ff;
// ctu_sel_jbus = sel_jbus_ff;
// end
//end
//
//assign ctu_sel_cpu[0] = ~( test_mode_pin // 0->0->ff
// & (~io_trst_l | pll_bypass_pin))
// & sel_cpu_ff[0];
//assign ctu_sel_cpu[1] = (test_mode_pin & ~io_trst_l) // 1->0->ff
// | ( ~(test_mode_pin & pll_bypass_pin)
// & sel_cpu_ff[1]);
//assign ctu_sel_cpu[2] = ~(test_mode_pin & ~io_trst_l) // 0->1->ff
// & ( (test_mode_pin & pll_bypass_pin)
// | sel_cpu_ff[2]);
//
//ctu_sel_dram[0] = 0->1->ff
//ctu_sel_dram[1] = 1->0->ff
//ctu_sel_dram[2] = 0->0->ff
//
//ctu_sel_jbus[0] = 0->0->ff
//ctu_sel_jbus[1] = 1->0->ff
//ctu_sel_jbus[2] = 0->1->ff
ctu_inv u_inv_trst(.z(trst), .a(io_trst_l));
/* ctu_jtag_clk_sel_0_0_ff AUTO_TEMPLATE (
.sel_clk (ctu_sel_cpu[@]),
.sel_ff(sel_cpu_ff[@]),); */
/* ctu_jtag_clk_sel_1_0_ff AUTO_TEMPLATE (
.sel_clk (ctu_sel_cpu[@]),
.sel_ff(sel_cpu_ff[@]),); */
/* ctu_jtag_clk_sel_0_1_ff AUTO_TEMPLATE (
.sel_clk (ctu_sel_cpu[@]),
.sel_ff(sel_cpu_ff[@]),); */
ctu_jtag_clk_sel_0_0_ff u_ctu_sel_cpu0 (/*AUTOINST*/
// Outputs
.sel_clk(ctu_sel_cpu[0]), // Templated
// Inputs
.test_mode_pin(test_mode_pin),
.trst(trst),
.pll_bypass_pin(pll_bypass_pin),
.sel_ff(sel_cpu_ff[0])); // Templated
ctu_jtag_clk_sel_1_0_ff u_ctu_sel_cpu1 (/*AUTOINST*/
// Outputs
.sel_clk(ctu_sel_cpu[1]), // Templated
// Inputs
.test_mode_pin(test_mode_pin),
.trst(trst),
.pll_bypass_pin(pll_bypass_pin),
.sel_ff(sel_cpu_ff[1])); // Templated
ctu_jtag_clk_sel_0_1_ff u_ctu_sel_cpu2 (/*AUTOINST*/
// Outputs
.sel_clk(ctu_sel_cpu[2]), // Templated
// Inputs
.test_mode_pin(test_mode_pin),
.trst(trst),
.pll_bypass_pin(pll_bypass_pin),
.sel_ff(sel_cpu_ff[2])); // Templated
/* ctu_jtag_clk_sel_0_0_ff AUTO_TEMPLATE (
.sel_clk (ctu_sel_dram[@]),
.sel_ff(sel_dram_ff[@]),); */
/* ctu_jtag_clk_sel_1_0_ff AUTO_TEMPLATE (
.sel_clk (ctu_sel_dram[@]),
.sel_ff(sel_dram_ff[@]),); */
/* ctu_jtag_clk_sel_0_1_ff AUTO_TEMPLATE (
.sel_clk (ctu_sel_dram[@]),
.sel_ff(sel_dram_ff[@]),); */
ctu_jtag_clk_sel_0_1_ff u_ctu_sel_dram0 (/*AUTOINST*/
// Outputs
.sel_clk(ctu_sel_dram[0]), // Templated
// Inputs
.test_mode_pin(test_mode_pin),
.trst(trst),
.pll_bypass_pin(pll_bypass_pin),
.sel_ff(sel_dram_ff[0])); // Templated
ctu_jtag_clk_sel_1_0_ff u_ctu_sel_dram1 (/*AUTOINST*/
// Outputs
.sel_clk(ctu_sel_dram[1]), // Templated
// Inputs
.test_mode_pin(test_mode_pin),
.trst(trst),
.pll_bypass_pin(pll_bypass_pin),
.sel_ff(sel_dram_ff[1])); // Templated
ctu_jtag_clk_sel_0_0_ff u_ctu_sel_dram2 (/*AUTOINST*/
// Outputs
.sel_clk(ctu_sel_dram[2]), // Templated
// Inputs
.test_mode_pin(test_mode_pin),
.trst(trst),
.pll_bypass_pin(pll_bypass_pin),
.sel_ff(sel_dram_ff[2])); // Templated
/* ctu_jtag_clk_sel_0_0_ff AUTO_TEMPLATE (
.sel_clk (ctu_sel_jbus[@]),
.sel_ff(sel_jbus_ff[@]),); */
/* ctu_jtag_clk_sel_1_0_ff AUTO_TEMPLATE (
.sel_clk (ctu_sel_jbus[@]),
.sel_ff(sel_jbus_ff[@]),); */
/* ctu_jtag_clk_sel_0_1_ff AUTO_TEMPLATE (
.sel_clk (ctu_sel_jbus[@]),
.sel_ff(sel_jbus_ff[@]),); */
ctu_jtag_clk_sel_0_0_ff u_ctu_sel_jbus0 (/*AUTOINST*/
// Outputs
.sel_clk(ctu_sel_jbus[0]), // Templated
// Inputs
.test_mode_pin(test_mode_pin),
.trst(trst),
.pll_bypass_pin(pll_bypass_pin),
.sel_ff(sel_jbus_ff[0])); // Templated
ctu_jtag_clk_sel_1_0_ff u_ctu_sel_jbus1 (/*AUTOINST*/
// Outputs
.sel_clk(ctu_sel_jbus[1]), // Templated
// Inputs
.test_mode_pin(test_mode_pin),
.trst(trst),
.pll_bypass_pin(pll_bypass_pin),
.sel_ff(sel_jbus_ff[1])); // Templated
ctu_jtag_clk_sel_0_1_ff u_ctu_sel_jbus2 (/*AUTOINST*/
// Outputs
.sel_clk(ctu_sel_jbus[2]), // Templated
// Inputs
.test_mode_pin(test_mode_pin),
.trst(trst),
.pll_bypass_pin(pll_bypass_pin),
.sel_ff(sel_jbus_ff[2])); // Templated
//------------------------
// scan dump
// - stagger cken and delay shift_enable to compensate for cken repeater fifo not
// balanced on top level &
//------------------------
assign next_cken_dram_wait = JTAG_CKEN_DRAM_WAIT;
assign next_cken_jbus_wait = JTAG_CKEN_JBUS_WAIT;
assign next_cken_other_wait = JTAG_CKEN_OTHER_WAIT;
assign scan_dump_cken_cmp = instr_scan_dump & ~nstep_mode;
assign scan_dump_cken_dram = scan_dump_cken_cmp & (scan_dump_shiftdr_cnt >= cken_dram_wait);
assign scan_dump_cken_jbus = scan_dump_cken_cmp & (scan_dump_shiftdr_cnt >= cken_jbus_wait);
assign scan_dump_cken_other = scan_dump_cken_cmp & (scan_dump_shiftdr_cnt >= cken_other_wait);
// negedge
assign inc_scan_dump_shiftdr_cnt = instr_scan_dump & tap_shift_dr_state;
always @ ( /*AUTOSENSE*/inc_scan_dump_shiftdr_cnt or instr_scan_dump
or scan_dump_shiftdr_cnt or tap_update_ir_state_d1) begin
if (tap_update_ir_state_d1 & instr_scan_dump)
next_scan_dump_shiftdr_cnt = {JTAG_SDR_CNT_WIDTH{1'b0}};
else begin
if (inc_scan_dump_shiftdr_cnt & (~&scan_dump_shiftdr_cnt)) // do not overflow counter
next_scan_dump_shiftdr_cnt = scan_dump_shiftdr_cnt +1'b1;
else
next_scan_dump_shiftdr_cnt = scan_dump_shiftdr_cnt;
end
end
//------------------------
// force_cken
//------------------------
assign normal_force_cken = ~nstep_mode
& ( tap_instructions[TAP_CKEN_BIT]
& ( instr_scan_parallel
| instr_scan_serial
| instr_scan_mtest ));
assign next_jtag_clsp_force_cken_cmp = normal_force_cken | scan_dump_cken_cmp;
assign next_jtag_clsp_force_cken_dram = normal_force_cken | scan_dump_cken_dram;
assign next_jtag_clsp_force_cken_jbus = normal_force_cken | scan_dump_cken_jbus;
//------------------------
// stop_id
//------------------------
// clock stop sequence
assign jtag_clsp_stop_id_vld = instr_clk_stop_id
& (tap_update_ir_state_d1 | tap_update_ir_state_d2); //sync to jbus
assign jtag_clsp_stop_id[5:0] = tap_instructions[TAP_CLK_STOP_ID_HI:TAP_CLK_STOP_ID_LO];
//------------------------
// nstep
//------------------------
assign jtag_nstep_vld = instr_scan_nstep
& (tap_update_ir_state_d1 | tap_update_ir_state_d2); //sync to
assign jtag_nstep_domain = tap_instructions[TAP_SCAN_NSTEP_DOM_HI:TAP_SCAN_NSTEP_DOM_LO];
assign jtag_nstep_count = tap_instructions[TAP_SCAN_NSTEP_CNT_HI:TAP_SCAN_NSTEP_CNT_LO];
// TAP_SCAN_NSTEP sets bit, and non-scan instruction clears bit
always @ ( /*AUTOSENSE*/instr_scan or instr_scan_bypass_en
or instr_scan_nstep or jtag_nstep_vld or nstep_mode) begin
if (jtag_nstep_vld)
next_nstep_mode = 1'b1;
else if (~instr_scan & ~instr_scan_nstep & ~instr_scan_bypass_en)
next_nstep_mode = 1'b0;
else
next_nstep_mode = nstep_mode;
end
assign next_dft_clsp_nstep_capture_l = ~(tap_capture_dr_state & next_nstep_mode);
//------------------------
// sel_tck2
//------------------------
assign next_sel_tck2_pre = ~nstep_mode
& ( instr_scan_parallel
| (instr_scan_mtest & tap_instructions[TAP_SCAN_MODE_BIT] == TAP_SCAN_MODE_PARALLEL));
assign jtag_clsp_sel_tck2 = sel_tck2_pre
| pin_based_pscan_mode;
//********************************************************************
// PLL Control
//********************************************************************
//-----------------------
// PLL_BYPASS
//-----------------------
assign toggle_pll_bypass_tap = instr_pll_bypass & tap_update_ir_state_d1;
assign next_pll_bypass_tap = toggle_pll_bypass_tap ^ pll_bypass_tap;
// pll_bypass_pin signal is gated by test_mode_pin
assign pll_bypass = pin_based_pll_bypass
| (~pin_based_pscan_mode & pll_bypass_tap)
| jtag_clsp_sel_tck2;
//*******************************************************************************
// Misc Muxes
// - muxes placed here for a lack of a better place
//*******************************************************************************
// Scan
// bug #5695
assign serial_scan = instr_scan_serial
| ( tap_instructions[TAP_SCAN_MODE_BIT] == TAP_SCAN_MODE_SERIAL
& ( tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_DUMP // 6'h26
| tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_MTEST_LONG // 6'h22
| tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_MTEST_SHORT)); // 6'h23
always @ ( /*AUTOSENSE*/io_tdi or pin_based_pscan_mode
or sctag2_ctu_serial_scan_in or serial_scan) begin
// if (instr_scan_serial & ~pin_based_pscan_mode)
if (serial_scan & ~pin_based_pscan_mode) // bug #5695
ctu_fpu_so = sctag2_ctu_serial_scan_in;
else
ctu_fpu_so = io_tdi;
end
// Random Number Generator
always @ ( /*AUTOSENSE*/afi_rng_ctl or afi_tsr_mode or jbus_rst_l
or test_mode_pin) begin
if (test_mode_pin) begin
dft_rng_vctrl = afi_rng_ctl[2:0];
dft_rng_rst_l = afi_tsr_mode;
end
else begin
dft_rng_vctrl = 3'b111;
dft_rng_rst_l = jbus_rst_l;
end
end
// Temperature Sensor Regulator Divider
always @ ( /*AUTOSENSE*/afi_tsr_div or afi_tsr_mode or afi_tsr_tsel
or test_mode_pin) begin
if (test_mode_pin) begin
dft_tsr_div = afi_tsr_div[9:1];
dft_tsr_tsel = afi_tsr_tsel[7:0];
dft_tsr_reset_l = afi_tsr_mode;
end
else begin
dft_tsr_div = 9'b0_0001_1001;
dft_tsr_tsel = 8'd0;
dft_tsr_reset_l = 1'b0;
end
end
// PLL
always @ ( /*AUTOSENSE*/afi_pll_char_mode or afi_pll_clamp_fltr
or afi_pll_div2 or test_mode_pin) begin
if (test_mode_pin & afi_pll_char_mode) begin
dft_pll_div2 = afi_pll_div2[5:0];
dft_pll_clamp_fltr = afi_pll_clamp_fltr;
end
else begin
dft_pll_div2 = 6'd0;
dft_pll_clamp_fltr = 1'b0;
end
end
always @ ( /*AUTOSENSE*/afi_pll_char_mode or afi_pll_trst_l
or pin_based_pscan_mode or pll_reset_ref_l or test_mode_pin) begin
if (pin_based_pscan_mode)
dft_pll_arst_l = 1'b0;
else if (test_mode_pin & afi_pll_char_mode)
dft_pll_arst_l = afi_pll_trst_l;
else
dft_pll_arst_l = pll_reset_ref_l;
end
assign dft_pll_testmode = test_mode_pin & afi_pll_char_mode;
//*******************************************************************************
// Async Reset and Set DFFRL/DFFSL Instantiations
//*******************************************************************************
//--------------
// posedge flops
//--------------
dffrl_async_ns u_dffrl_async_creg_rdrtrn_vld
( .din (next_creg_rdrtrn_vld),
.clk (io_tck),
.rst_l (tap_rst_l),
.q (creg_rdrtrn_vld)
);
dffrl_async_ns #(64) u_dffrl_async_scratch_reg
(.din (next_scratch_reg),
.clk (io_tck),
.rst_l (tap_rst_l),
.q (scratch_reg)
);
dffrl_async_ns u_dffrl_async_jtag_bist_serial
( .din (next_jtag_bist_serial),
.rst_l (tap_rst_l),
.clk (io_tck),
.q (jtag_bist_serial)
);
dffrl_async_ns u_dffrl_async_jtag_bist_parallel
( .din (next_jtag_bist_parallel),
.rst_l (tap_rst_l),
.clk (io_tck),
.q (jtag_bist_parallel)
);
dffrl_async_ns u_dffrl_async_jtag_bist_abort
( .din (next_jtag_bist_abort),
.rst_l (tap_rst_l),
.clk (io_tck),
.q (jtag_bist_abort)
);
dffrl_async_ns #(TAP_MBIST_ACTIVE_WIDTH) u_dffrl_async_jtag_bist_active
( .din (next_jtag_bist_active),
.rst_l (tap_rst_l),
.clk (io_tck),
.q (jtag_bist_active)
);
dffrl_async_ns #(TAP_SSCAN_CFG_WIDTH) u_dffrl_async_shadow_scan_config_reg
( .din (next_shadow_scan_config_reg),
.clk (io_tck),
.rst_l (tap_rst_l),
.q (shadow_scan_config_reg)
);
dffrl_async_ns #(1) u_dffrl_async_jtag_creg_addr_en
( .din (next_jtag_creg_addr_en),
.clk (io_tck),
.rst_l (tap_rst_l),
.q (jtag_creg_addr_en)
);
dffrl_async_ns #(1) u_dffrl_async_jtag_creg_wr_en
( .din (next_jtag_creg_wr_en),
.clk (io_tck),
.rst_l (tap_rst_l),
.q (jtag_creg_wr_en)
);
dffrl_async_ns #(1) u_dffrl_async_jtag_creg_rd_en
( .din (next_jtag_creg_rd_en),
.clk (io_tck),
.rst_l (tap_rst_l),
.q (jtag_creg_rd_en)
);
dffrl_async_ns #(1) u_dffrl_async_jtag_creg_data_en
( .din (next_jtag_creg_data_en),
.clk (io_tck),
.rst_l (tap_rst_l),
.q (jtag_creg_data_en)
);
//--------------
// negedge flops
//--------------
dffrl_async_ns u_dffrl_async_global_scan_bypass_en
( .din (next_global_scan_bypass_en),
.clk (tck_l),
.rst_l (tap_rst_l),
// .q (global_scan_bypass_en));
.q (global_scan_bypass_en_pre)); // bug #5483
dffrl_async_ns u_dffrl_async_pscan_select_pre
( .din (next_pscan_select_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (pscan_select_pre));
// reset clocks in normal mode (bit 0 asserted)
dffsl_async_ns #(1) u_dffsl_async_sel_cpu_ff0
( .din (next_sel_cpu_ff[0]),
.clk (tck_l),
.set_l (tap_rst_l),
.q (sel_cpu_ff[0])
);
dffrl_async_ns #(2) u_dffrl_async_sel_cpu_ff_1to2
( .din (next_sel_cpu_ff[2:1]),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (sel_cpu_ff[2:1])
);
dffsl_async_ns #(1) u_dffsl_async_sel_dram_ff0
( .din (next_sel_dram_ff[0]),
.clk (tck_l),
.set_l (tap_rst_l),
.q (sel_dram_ff[0])
);
dffrl_async_ns #(2) u_dffrl_async_sel_dram_ff_1to2
( .din (next_sel_dram_ff[2:1]),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (sel_dram_ff[2:1])
);
dffsl_async_ns #(1) u_dffsl_async_sel_jbus_ff0
( .din (next_sel_jbus_ff[0]),
.clk (tck_l),
.set_l (tap_rst_l),
.q (sel_jbus_ff[0])
);
dffrl_async_ns #(2) u_dffrl_async_sel_jbus_ff_1to2
( .din (next_sel_jbus_ff[2:1]),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (sel_jbus_ff[2:1])
);
// boundary scan
dffrl_async_ns #(1) u_dffrl_async_bscan_enable
( .din (next_bscan_enable),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (bscan_enable)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_ddr0_mode_ctl
( .din (next_ctu_ddr0_mode_ctl),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_ddr0_mode_ctl)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_ddr1_mode_ctl
( .din (next_ctu_ddr1_mode_ctl),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_ddr1_mode_ctl)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_ddr2_mode_ctl
( .din (next_ctu_ddr2_mode_ctl),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_ddr2_mode_ctl)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_ddr3_mode_ctl
( .din (next_ctu_ddr3_mode_ctl),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_ddr3_mode_ctl)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_jbusl_mode_ctl
( .din (next_ctu_jbusl_mode_ctl),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_jbusl_mode_ctl)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_jbusr_mode_ctl
( .din (next_ctu_jbusr_mode_ctl),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_jbusr_mode_ctl)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_debug_mode_ctl
( .din (next_ctu_debug_mode_ctl),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_debug_mode_ctl)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_misc_mode_ctl
( .din (next_ctu_misc_mode_ctl),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_misc_mode_ctl)
);
dffsl_async_ns #(1) u_dffsl_async_ctu_ddr0_hiz_l
( .din (next_ctu_ddr0_hiz_l),
.clk (tck_l),
.set_l (tap_rst_l),
.q (ctu_ddr0_hiz_l)
);
dffsl_async_ns #(1) u_dffsl_async_ctu_ddr1_hiz_l
( .din (next_ctu_ddr1_hiz_l),
.clk (tck_l),
.set_l (tap_rst_l),
.q (ctu_ddr1_hiz_l)
);
dffsl_async_ns #(1) u_dffsl_async_ctu_ddr2_hiz_l
( .din (next_ctu_ddr2_hiz_l),
.clk (tck_l),
.set_l (tap_rst_l),
.q (ctu_ddr2_hiz_l)
);
dffsl_async_ns #(1) u_dffsl_async_ctu_ddr3_hiz_l
( .din (next_ctu_ddr3_hiz_l),
.clk (tck_l),
.set_l (tap_rst_l),
.q (ctu_ddr3_hiz_l)
);
dffsl_async_ns #(1) u_dffsl_async_ctu_jbusl_hiz_l
( .din (next_ctu_jbusl_hiz_l),
.clk (tck_l),
.set_l (tap_rst_l),
.q (ctu_jbusl_hiz_l)
);
dffsl_async_ns #(1) u_dffsl_async_ctu_jbusr_hiz_l
( .din (next_ctu_jbusr_hiz_l),
.clk (tck_l),
.set_l (tap_rst_l),
.q (ctu_jbusr_hiz_l)
);
dffsl_async_ns #(1) u_dffsl_async_ctu_debug_hiz_l
( .din (next_ctu_debug_hiz_l),
.clk (tck_l),
.set_l (tap_rst_l),
.q (ctu_debug_hiz_l)
);
dffsl_async_ns #(1) u_dffsl_async_ctu_misc_hiz_l
( .din (next_ctu_misc_hiz_l),
.clk (tck_l),
.set_l (tap_rst_l),
.q (ctu_misc_hiz_l)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_ddr0_update_dr
( .din (next_ctu_ddr0_update_dr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_ddr0_update_dr)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_ddr1_update_dr
( .din (next_ctu_ddr1_update_dr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_ddr1_update_dr)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_ddr2_update_dr
( .din (next_ctu_ddr2_update_dr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_ddr2_update_dr)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_ddr3_update_dr
( .din (next_ctu_ddr3_update_dr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_ddr3_update_dr)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_jbusl_update_dr
( .din (next_ctu_jbusl_update_dr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_jbusl_update_dr)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_jbusr_update_dr
( .din (next_ctu_jbusr_update_dr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_jbusr_update_dr)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_debug_update_dr
( .din (next_ctu_debug_update_dr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_debug_update_dr)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_misc_update_dr
( .din (next_ctu_misc_update_dr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_misc_update_dr)
);
dffrl_async_ns #(1) u_dffrl_async_ddr0_clock_dr_pre
( .din (next_ddr0_clock_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ddr0_clock_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_ddr1_clock_dr_pre
( .din (next_ddr1_clock_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ddr1_clock_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_ddr2_clock_dr_pre
( .din (next_ddr2_clock_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ddr2_clock_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_ddr3_clock_dr_pre
( .din (next_ddr3_clock_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ddr3_clock_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_jbusl_clock_dr_pre
( .din (next_jbusl_clock_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (jbusl_clock_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_jbusr_clock_dr_pre
( .din (next_jbusr_clock_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (jbusr_clock_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_debug_clock_dr_pre
( .din (next_debug_clock_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (debug_clock_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_misc_clock_dr_pre
( .din (next_misc_clock_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (misc_clock_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_ddr0_shift_dr_pre
( .din (next_ddr0_shift_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ddr0_shift_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_ddr1_shift_dr_pre
( .din (next_ddr1_shift_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ddr1_shift_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_ddr2_shift_dr_pre
( .din (next_ddr2_shift_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ddr2_shift_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_ddr3_shift_dr_pre
( .din (next_ddr3_shift_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ddr3_shift_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_jbusl_shift_dr_pre
( .din (next_jbusl_shift_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (jbusl_shift_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_jbusr_shift_dr_pre
( .din (next_jbusr_shift_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (jbusr_shift_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_debug_shift_dr_pre
( .din (next_debug_shift_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (debug_shift_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_misc_shift_dr_pre
( .din (next_misc_shift_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (misc_shift_dr_pre)
);
// shadow scan
dffrl_async_ns #(1) u_dffrl_async_shadow_scan_instr
( .din (next_shadow_scan_instr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (shadow_scan_instr)
);
dffsl_async_ns #(1) u_dffsl_async_spc_sscan_tid0
( .din (next_spc_sscan_tid[0]),
.clk (tck_l),
.set_l (tap_rst_l),
.q (spc_sscan_tid[0])
);
dffrl_async_ns #(3) u_dffrl_async_spc_sscan_tid1to3
( .din (next_spc_sscan_tid[3:1]),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc_sscan_tid[3:1])
);
dffrl_async_ns #(1) u_dffrl_async_ctu_pads_sscan_update
( .din (next_ctu_pads_sscan_update),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_pads_sscan_update)
);
dffrl_async_ns #(1) u_dffrl_async_spc0_sscan_se_pre
( .din (next_spc0_sscan_se_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc0_sscan_se_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc1_sscan_se_pre
( .din (next_spc1_sscan_se_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc1_sscan_se_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc2_sscan_se_pre
( .din (next_spc2_sscan_se_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc2_sscan_se_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc3_sscan_se_pre
( .din (next_spc3_sscan_se_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc3_sscan_se_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc4_sscan_se_pre
( .din (next_spc4_sscan_se_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc4_sscan_se_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc5_sscan_se_pre
( .din (next_spc5_sscan_se_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc5_sscan_se_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc6_sscan_se_pre
( .din (next_spc6_sscan_se_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc6_sscan_se_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc7_sscan_se_pre
( .din (next_spc7_sscan_se_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc7_sscan_se_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc0_tck_pre
( .din (next_spc0_tck_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc0_tck_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc1_tck_pre
( .din (next_spc1_tck_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc1_tck_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc2_tck_pre
( .din (next_spc2_tck_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc2_tck_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc3_tck_pre
( .din (next_spc3_tck_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc3_tck_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc4_tck_pre
( .din (next_spc4_tck_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc4_tck_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc5_tck_pre
( .din (next_spc5_tck_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc5_tck_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc6_tck_pre
( .din (next_spc6_tck_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc6_tck_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc7_tck_pre
( .din (next_spc7_tck_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc7_tck_pre)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_global_snap
( .din (next_ctu_global_snap),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_global_snap)
);
// scan
dffrl_async_ns #(1) u_dffrl_async_instr_normal_scan
( .din (next_instr_normal_scan),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (instr_normal_scan)
);
dffrl_async_ns #(1) u_dffrl_async_instr_scan
( .din (next_instr_scan),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (instr_scan)
);
dffrl_async_ns #(1) u_dffrl_async_global_shift_enable_pre
( .din (next_global_shift_enable_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (global_shift_enable_pre)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_tst_macrotest
( .din (next_ctu_tst_macrotest),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_tst_macrotest)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_tst_short_chain
( .din (next_ctu_tst_short_chain),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_tst_short_chain)
);
dffrl_async_ns #(JTAG_SDR_CNT_WIDTH) u_dffrl_async_scan_dump_shiftdr_cnt
(.din (next_scan_dump_shiftdr_cnt),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (scan_dump_shiftdr_cnt));
// efc
dffrl_async_ns #(1) u_dffrl_async_ctu_efc_capturedr
( .din (next_ctu_efc_capturedr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_efc_capturedr)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_efc_shiftdr
( .din (next_ctu_efc_shiftdr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_efc_shiftdr)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_efc_updatedr
( .din (next_ctu_efc_updatedr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_efc_updatedr)
);
dffrl_async_ns #(1) u_dffrl_async_efc_tck_pre
( .din (next_efc_tck_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (efc_tck_pre)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_efc_fuse_bypass
( .din (next_ctu_efc_fuse_bypass),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_efc_fuse_bypass)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_efc_read_en
( .din (next_ctu_efc_read_en),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_efc_read_en)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_efc_dest_sample
( .din (next_ctu_efc_dest_sample),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_efc_dest_sample)
);
dffsl_async_ns #(1) u_dffsl_async_suppress_capture_l
( .din (next_suppress_capture_l),
.clk (tck_l),
.set_l (tap_rst_l),
.q (suppress_capture_l)
);
dffrl_async_ns #(7) u_dffrl_async_ctu_efc_rowaddr
( .din (next_ctu_efc_rowaddr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_efc_rowaddr)
);
dffrl_async_ns #(5) u_dffrl_async_ctu_efc_coladdr
( .din (next_ctu_efc_coladdr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_efc_coladdr)
);
dffrl_async_ns #(3) u_dffrl_async_ctu_efc_read_mode
( .din (next_ctu_efc_read_mode),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_efc_read_mode)
);
// nstep
dffrl_async_ns #(1) u_dffrl_async_nstep_mode
( .din (next_nstep_mode),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (nstep_mode)
);
dffsl_async_ns #(1) u_dffsl_async_dft_clsp_nstep_capture_l
( .din (next_dft_clsp_nstep_capture_l),
.clk (tck_l),
.set_l (tap_rst_l),
.q (dft_clsp_nstep_capture_l)
);
// clock control
dffrl_async_ns u_dffrl_async_sel_tck2_pre
(.din (next_sel_tck2_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (sel_tck2_pre));
dffrl_async_ns u_dffrl_async_jtag_clsp_force_cken_cmp
(.din (next_jtag_clsp_force_cken_cmp),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (jtag_clsp_force_cken_cmp));
dffrl_async_ns u_dffrl_async_jtag_clsp_force_cken_dram
(.din (next_jtag_clsp_force_cken_dram),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (jtag_clsp_force_cken_dram));
dffrl_async_ns u_dffrl_async_jtag_clsp_force_cken_jbus
(.din (next_jtag_clsp_force_cken_jbus),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (jtag_clsp_force_cken_jbus));
dffrl_async_ns u_dffrl_async_pll_bypass_tap
(.din (next_pll_bypass_tap),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (pll_bypass_tap));
//*******************************************************************************
// DFF Instantiations
//*******************************************************************************
dff_ns u_dff_creg_rdrtrn_load_d1
( .din (creg_rdrtrn_load),
.clk (io_tck),
.q (creg_rdrtrn_load_d1)
);
dff_ns u_dff_creg_jtag_rdrtrn_vld_d
( .din (creg_jtag_rdrtrn_vld),
.clk (io_tck),
.q (creg_jtag_rdrtrn_vld_d)
);
dff_ns u_dff_creg_jtag_rdrtrn_vld_d2
( .din (creg_jtag_rdrtrn_vld_d),
.clk (io_tck),
.q (creg_jtag_rdrtrn_vld_d2)
);
dff_ns u_dff_tap_shift_dr_state_d1
(.din (tap_shift_dr_state),
.clk (io_tck),
.q (tap_shift_dr_state_d1)
);
dff_ns u_dff_tap_update_ir_state_d1
( .din (tap_update_ir_state),
.clk (io_tck),
.q (tap_update_ir_state_d1)
);
dff_ns u_dff_tap_update_ir_state_d2
( .din (tap_update_ir_state_d1),
.clk (io_tck),
.q (tap_update_ir_state_d2)
);
dff_ns u_dff_instr_iob_rd_d1
(.din (instr_iob_rd),
.clk (io_tck),
.q (instr_iob_rd_d1)
);
dff_ns u_dff_instr_iob_raddr_d1
(.din (instr_iob_raddr),
.clk (io_tck),
.q (instr_iob_raddr_d1)
);
dff_ns #(3) u_dff_efc_read_mode
(.din (next_efc_read_mode),
.clk (io_tck),
.q (efc_read_mode)
);
dff_ns #(5) u_dff_efc_coladdr
(.din (next_efc_coladdr),
.clk (io_tck),
.q (efc_coladdr)
);
dff_ns #(7) u_dff_efc_rowaddr
(.din (next_efc_rowaddr),
.clk (io_tck),
.q (efc_rowaddr)
);
dff_ns #(`CTU_BIST_CNT*2) u_dff_bist_result_reg
(.din (next_bist_result_reg),
.clk (io_tck),
.q (bist_result_reg)
);
dff_ns #(65) u_dff_creg_rdrtrn
(.din (next_creg_rdrtrn),
.clk (io_tck),
.q (creg_rdrtrn)
);
dff_ns #(64) u_dff_creg_wdata
(.din (next_creg_wdata),
.clk (io_tck),
.q (creg_wdata)
);
dff_ns #(40) u_dff_creg_addr
(.din (next_creg_addr),
.clk (io_tck),
.q (creg_addr)
);
dff_ns #(32) u_dff_idcode
(.din (next_idcode),
.clk (io_tck),
.q (idcode)
);
dff_ns #(JTAG_SDR_CNT_WIDTH) u_dff_cken_dram_wait
(.din (next_cken_dram_wait),
.clk (io_tck),
.q (cken_dram_wait)
);
dff_ns #(JTAG_SDR_CNT_WIDTH) u_dff_cken_jbus_wait
(.din (next_cken_jbus_wait),
.clk (io_tck),
.q (cken_jbus_wait)
);
dff_ns #(JTAG_SDR_CNT_WIDTH) u_dff_cken_other_wait
(.din (next_cken_other_wait),
.clk (io_tck),
.q (cken_other_wait)
);
// bug #5696
dff_ns #(1) u_dff_pads_ctu_si_bypmux_out_ff_nsr
(.din (pads_ctu_si_bypmux_out),
.clk (io_tck),
.q (pads_ctu_si_bypmux_out_ff)
);
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-files:("../common/rtl/ctu_lib.v")
// verilog-auto-sense-defines-constant:t
// End:
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:11:18 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top zqynq_lab_1_design_axi_bram_ctrl_0_bram_0 -prefix
// zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_ zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_sim_netlist.v
// Design : zqynq_lab_1_design_axi_bram_ctrl_0_bram_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_axi_bram_ctrl_0_bram_0,blk_mem_gen_v8_3_6,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_6,Vivado 2017.2" *)
(* NotValidForBitStream *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0
(clka,
rsta,
ena,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
web,
addrb,
dinb,
doutb);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *) input rsta;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [3:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [31:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [31:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [31:0]douta;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) input clkb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB RST" *) input rstb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *) input enb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *) input [3:0]web;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input [31:0]addrb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *) input [31:0]dinb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output [31:0]doutb;
wire [31:0]addra;
wire [31:0]addrb;
wire clka;
wire clkb;
wire [31:0]dina;
wire [31:0]dinb;
wire [31:0]douta;
wire [31:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [3:0]wea;
wire [3:0]web;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [31:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [31:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [31:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "32" *)
(* C_ADDRB_WIDTH = "32" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "8" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "16" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "1" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 20.388 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "1" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "1" *)
(* C_HAS_RSTB = "1" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "NONE" *)
(* C_INIT_FILE_NAME = "no_coe_file_loaded" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "0" *)
(* C_MEM_TYPE = "2" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "16384" *)
(* C_READ_DEPTH_B = "16384" *)
(* C_READ_WIDTH_A = "32" *)
(* C_READ_WIDTH_B = "32" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "1" *)
(* C_USE_BYTE_WEA = "1" *)
(* C_USE_BYTE_WEB = "1" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "4" *)
(* C_WEB_WIDTH = "4" *)
(* C_WRITE_DEPTH_A = "16384" *)
(* C_WRITE_DEPTH_B = "16384" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "32" *)
(* C_WRITE_WIDTH_B = "32" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 U0
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.eccpipece(1'b0),
.ena(ena),
.enb(enb),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[31:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(rsta),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(rstb),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[31:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[31:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0}),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(web));
endmodule
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_generic_cstr
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [31:0]douta;
output [31:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [31:0]dina;
input [31:0]dinb;
input [3:0]wea;
input [3:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [31:0]dina;
wire [31:0]dinb;
wire [31:0]douta;
wire [31:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [3:0]wea;
wire [3:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[1:0]),
.dinb(dinb[1:0]),
.douta(douta[1:0]),
.doutb(doutb[1:0]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[0]),
.web(web[0]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized9 \ramloop[10].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[21:20]),
.dinb(dinb[21:20]),
.douta(douta[21:20]),
.doutb(doutb[21:20]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[2]),
.web(web[2]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized10 \ramloop[11].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[23:22]),
.dinb(dinb[23:22]),
.douta(douta[23:22]),
.doutb(doutb[23:22]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[2]),
.web(web[2]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized11 \ramloop[12].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[25:24]),
.dinb(dinb[25:24]),
.douta(douta[25:24]),
.doutb(doutb[25:24]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[3]),
.web(web[3]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized12 \ramloop[13].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[27:26]),
.dinb(dinb[27:26]),
.douta(douta[27:26]),
.doutb(doutb[27:26]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[3]),
.web(web[3]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized13 \ramloop[14].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[29:28]),
.dinb(dinb[29:28]),
.douta(douta[29:28]),
.doutb(doutb[29:28]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[3]),
.web(web[3]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized14 \ramloop[15].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[31:30]),
.dinb(dinb[31:30]),
.douta(douta[31:30]),
.doutb(doutb[31:30]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[3]),
.web(web[3]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[3:2]),
.dinb(dinb[3:2]),
.douta(douta[3:2]),
.doutb(doutb[3:2]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[0]),
.web(web[0]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[5:4]),
.dinb(dinb[5:4]),
.douta(douta[5:4]),
.doutb(doutb[5:4]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[0]),
.web(web[0]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[7:6]),
.dinb(dinb[7:6]),
.douta(douta[7:6]),
.doutb(doutb[7:6]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[0]),
.web(web[0]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[9:8]),
.dinb(dinb[9:8]),
.douta(douta[9:8]),
.doutb(doutb[9:8]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[1]),
.web(web[1]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:10]),
.dinb(dinb[11:10]),
.douta(douta[11:10]),
.doutb(doutb[11:10]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[1]),
.web(web[1]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[13:12]),
.dinb(dinb[13:12]),
.douta(douta[13:12]),
.doutb(doutb[13:12]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[1]),
.web(web[1]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[15:14]),
.dinb(dinb[15:14]),
.douta(douta[15:14]),
.doutb(doutb[15:14]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[1]),
.web(web[1]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized7 \ramloop[8].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[17:16]),
.dinb(dinb[17:16]),
.douta(douta[17:16]),
.doutb(doutb[17:16]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[2]),
.web(web[2]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized8 \ramloop[9].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[19:18]),
.dinb(dinb[19:18]),
.douta(douta[19:18]),
.doutb(doutb[19:18]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[2]),
.web(web[2]));
endmodule
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized0
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized1
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized10
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized10 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized11
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized11 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized12
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized12 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized13
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized13 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized14
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized14 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized2
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized3
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized4
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized4 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized5
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized5 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized6
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized6 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized7
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized7 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized8
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized8 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized9
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized9 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[1:0][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized0
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[3:2][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
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.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized1
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[5:4][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized10
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[23:22][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized11
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[25:24][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized12
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[27:26][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized13
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[29:28][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
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.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized14
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[31:30][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized2
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[7:6][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized3
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[9:8][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized4
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[11:10][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized5
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[13:12][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized6
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[15:14][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized7
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[17:16][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
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.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized8
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[19:18][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized9
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[21:20][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_top
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [31:0]douta;
output [31:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [31:0]dina;
input [31:0]dinb;
input [3:0]wea;
input [3:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [31:0]dina;
wire [31:0]dinb;
wire [31:0]douta;
wire [31:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [3:0]wea;
wire [3:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
(* C_ADDRA_WIDTH = "32" *) (* C_ADDRB_WIDTH = "32" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "8" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "16" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "1" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 20.388 mW" *)
(* C_FAMILY = "zynq" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "1" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "1" *)
(* C_HAS_RSTB = "1" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "NONE" *)
(* C_INIT_FILE_NAME = "no_coe_file_loaded" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "0" *)
(* C_MEM_TYPE = "2" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "16384" *) (* C_READ_DEPTH_B = "16384" *) (* C_READ_WIDTH_A = "32" *)
(* C_READ_WIDTH_B = "32" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "1" *) (* C_USE_BYTE_WEA = "1" *) (* C_USE_BYTE_WEB = "1" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "4" *) (* C_WEB_WIDTH = "4" *)
(* C_WRITE_DEPTH_A = "16384" *) (* C_WRITE_DEPTH_B = "16384" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "32" *) (* C_WRITE_WIDTH_B = "32" *)
(* C_XDEVICEFAMILY = "zynq" *) (* downgradeipidentifiedwarnings = "yes" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [3:0]wea;
input [31:0]addra;
input [31:0]dina;
output [31:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [3:0]web;
input [31:0]addrb;
input [31:0]dinb;
output [31:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [31:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [31:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [31:0]addra;
wire [31:0]addrb;
wire clka;
wire clkb;
wire [31:0]dina;
wire [31:0]dinb;
wire [31:0]douta;
wire [31:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [3:0]wea;
wire [3:0]web;
assign dbiterr = \<const0> ;
assign rdaddrecc[31] = \<const0> ;
assign rdaddrecc[30] = \<const0> ;
assign rdaddrecc[29] = \<const0> ;
assign rdaddrecc[28] = \<const0> ;
assign rdaddrecc[27] = \<const0> ;
assign rdaddrecc[26] = \<const0> ;
assign rdaddrecc[25] = \<const0> ;
assign rdaddrecc[24] = \<const0> ;
assign rdaddrecc[23] = \<const0> ;
assign rdaddrecc[22] = \<const0> ;
assign rdaddrecc[21] = \<const0> ;
assign rdaddrecc[20] = \<const0> ;
assign rdaddrecc[19] = \<const0> ;
assign rdaddrecc[18] = \<const0> ;
assign rdaddrecc[17] = \<const0> ;
assign rdaddrecc[16] = \<const0> ;
assign rdaddrecc[15] = \<const0> ;
assign rdaddrecc[14] = \<const0> ;
assign rdaddrecc[13] = \<const0> ;
assign rdaddrecc[12] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[31] = \<const0> ;
assign s_axi_rdaddrecc[30] = \<const0> ;
assign s_axi_rdaddrecc[29] = \<const0> ;
assign s_axi_rdaddrecc[28] = \<const0> ;
assign s_axi_rdaddrecc[27] = \<const0> ;
assign s_axi_rdaddrecc[26] = \<const0> ;
assign s_axi_rdaddrecc[25] = \<const0> ;
assign s_axi_rdaddrecc[24] = \<const0> ;
assign s_axi_rdaddrecc[23] = \<const0> ;
assign s_axi_rdaddrecc[22] = \<const0> ;
assign s_axi_rdaddrecc[21] = \<const0> ;
assign s_axi_rdaddrecc[20] = \<const0> ;
assign s_axi_rdaddrecc[19] = \<const0> ;
assign s_axi_rdaddrecc[18] = \<const0> ;
assign s_axi_rdaddrecc[17] = \<const0> ;
assign s_axi_rdaddrecc[16] = \<const0> ;
assign s_axi_rdaddrecc[15] = \<const0> ;
assign s_axi_rdaddrecc[14] = \<const0> ;
assign s_axi_rdaddrecc[13] = \<const0> ;
assign s_axi_rdaddrecc[12] = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6_synth inst_blk_mem_gen
(.addra(addra[15:2]),
.addrb(addrb[15:2]),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6_synth
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [31:0]douta;
output [31:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [31:0]dina;
input [31:0]dinb;
input [3:0]wea;
input [3:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [31:0]dina;
wire [31:0]dinb;
wire [31:0]douta;
wire [31:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [3:0]wea;
wire [3:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_top \gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINVLP_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__CLKINVLP_PP_BLACKBOX_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__clkinvlp (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINVLP_PP_BLACKBOX_V
|
// Library - static, Cell - th22, View - schematic
// LAST TIME SAVED: May 23 15:00:43 2014
// NETLIST TIME: May 23 15:01:15 2014
`timescale 1ns / 1ns
module th22 ( y, a, b );
output y;
input a, b;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th22";
specparam CDS_VIEWNAME = "schematic";
endspecify
pfet_b P4 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net24));
pfet_b P3 ( .b(cds_globals.vdd_), .g(y), .s(net24), .d(net15));
pfet_b P2 ( .b(cds_globals.vdd_), .g(b), .s(cds_globals.vdd_),
.d(net24));
pfet_b P1 ( .b(cds_globals.vdd_), .g(b), .s(net35), .d(net15));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net35));
nfet_b N4 ( .d(net22), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N3 ( .d(net22), .g(a), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net15), .g(y), .s(net22), .b(cds_globals.gnd_));
nfet_b N1 ( .d(net34), .g(a), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N0 ( .d(net15), .g(b), .s(net34), .b(cds_globals.gnd_));
inv I8 ( y, net15);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2I_4_V
`define SKY130_FD_SC_HS__MUX2I_4_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__mux2i_4 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
sky130_fd_sc_hs__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__mux2i_4 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2I_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222OI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A222OI_BEHAVIORAL_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a222oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
// Local signals
wire B2 nand0_out ;
wire B2 nand1_out ;
wire B2 nand2_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y , nand0_out, nand1_out, nand2_out);
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND );
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222OI_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__NOR3B_BEHAVIORAL_PP_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3B_BEHAVIORAL_PP_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 22 02:52:02 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/system_zed_hdmi_0_0_stub.v
// Design : system_zed_hdmi_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "zed_hdmi,Vivado 2016.4" *)
module system_zed_hdmi_0_0(clk, clk_x2, clk_100, active, hsync, vsync, rgb888,
hdmi_clk, hdmi_hsync, hdmi_vsync, hdmi_d, hdmi_de, hdmi_scl, hdmi_sda)
/* synthesis syn_black_box black_box_pad_pin="clk,clk_x2,clk_100,active,hsync,vsync,rgb888[23:0],hdmi_clk,hdmi_hsync,hdmi_vsync,hdmi_d[15:0],hdmi_de,hdmi_scl,hdmi_sda" */;
input clk;
input clk_x2;
input clk_100;
input active;
input hsync;
input vsync;
input [23:0]rgb888;
output hdmi_clk;
output hdmi_hsync;
output hdmi_vsync;
output [15:0]hdmi_d;
output hdmi_de;
output hdmi_scl;
inout hdmi_sda;
endmodule
|
`timescale 1ns / 1ps
`include "constants.vh"
////////////////////////////////////////////////////////////////////////////////
// Company: TU Darmstadt
// Engineer: Mahdi Enan
//
// Create Date: 09:55:48 01/21/2017
// Design Name: pLayer
// Module Name: tb_pLayer.v
// Project Name: spongent
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: pLayer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_pLayer;
// Inputs
reg [263:0] state_in;
reg clk;
reg rst;
reg en;
// Outputs
wire [263:0] state_out;
wire out_rdy;
// Instantiate the Unit Under Test (UUT)
pLayer uut (
.state_in(state_in),
.state_out(state_out),
.clk(clk),
.rst(rst),
.en(en),
.out_rdy(out_rdy)
);
//integer i;
initial begin
// Initialize Inputs
state_in = 0;
clk = 0;
rst = 1;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
// Add stimulus here
$display("[INITIALIZING]");
en = 1;
state_in = 264'h20d6d3dcd9d5d8dad7dfd4d1d2d0dbdddee6e3ece9e5e8eae7efe4e1e2e0ebed94;
$display("state in: %h", state_in);
repeat (66)
#5;
if (out_rdy) begin
$display("state out: %h", state_out);
end
rst = 1; en = 0;
#5;
en = 1; rst = 0;
state_in = 264'ha8365886353658867333568863335688ca2ed1e22f3856833e55353353dd2d22a5;
$display("state in: %h", state_in);
repeat (66)
#5;
if (out_rdy) begin
$display("state out: %h", state_out);
end
end
always begin
#5; clk = !clk;
end
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: hdr_fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module hdr_fifo (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q);
input aclr;
input clock;
input [71:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [71:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "251"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "72"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "72"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "251"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "72"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 72 0 INPUT NODEFVAL "data[71..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 72 0 OUTPUT NODEFVAL "q[71..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 72 0 data 0 0 72 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 72 0 @q 0 0 72 0
// Retrieval info: GEN_FILE: TYPE_NORMAL hdr_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL hdr_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hdr_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hdr_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hdr_fifo_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL hdr_fifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSBP_1_V
`define SKY130_FD_SC_HD__SDFSBP_1_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfsbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSBP_1_V
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for wb_ram
*/
module test_wb_ram;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
parameter SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] adr_i = 0;
reg [DATA_WIDTH-1:0] dat_i = 0;
reg we_i = 0;
reg [SELECT_WIDTH-1:0] sel_i = 0;
reg stb_i = 0;
reg cyc_i = 0;
// Outputs
wire [DATA_WIDTH-1:0] dat_o;
wire ack_o;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
adr_i,
dat_i,
we_i,
sel_i,
stb_i,
cyc_i);
$to_myhdl(dat_o,
ack_o);
// dump file
$dumpfile("test_wb_ram.lxt");
$dumpvars(0, test_wb_ram);
end
wb_ram #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH)
)
UUT (
.clk(clk),
.adr_i(adr_i),
.dat_i(dat_i),
.dat_o(dat_o),
.we_i(we_i),
.sel_i(sel_i),
.stb_i(stb_i),
.ack_o(ack_o),
.cyc_i(cyc_i)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31OI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A31OI_BEHAVIORAL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a31oi (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31OI_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVP_TB_V
`define SKY130_FD_SC_HD__EINVP_TB_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__einvp.v"
module top();
// Inputs are registered
reg A;
reg TE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__einvp dut (.A(A), .TE(TE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVP_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__EINVP_BEHAVIORAL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__einvp (
Z ,
A ,
TE
);
// Module ports
output Z ;
input A ;
input TE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
notif1 notif10 (Z , A, TE );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVP_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:51:58 03/24/2014
// Design Name:
// Module Name: MIPS32
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mips32(/*AUTOARG*/
// Outputs
porta_out, portb_out,
// Inputs
rst, clk, porta_in, portb_in, interrupts
);
input rst;
input clk;
input porta_in;
input portb_in;
input [4:0] interrupts;
output porta_out;
output portb_out;
reg [31:0] PC;
reg [31:0] PCadd4;
wire [31:0] PCnext, PCout;
wire [31:0] HI;
wire [31:0] LO;
wire [31:0] inst;
wire [31:0] immediate;
wire [4:0] rs, rt, rd;
wire load, store, move, ssnop, nop,jump, branch,sign, regwrite,memtoreg,memread, memwrite;
wire [20:0] aluc;
wire [3:0] move_op;
wire [8:0] load_op;
wire [5:0] store_op;
wire [31:0] regrs_data, regrt_data;
wire [31:0] memaddr;
wire [31:0] memdata_in;
// IF stage
wire IF_stall;
wire IF_flush;
wire [31:0] IF_inst;
wire [31:0] IF_PC, IF_PCnext;
//wire [31:0] ID_inst;
//wire [31:0] ID_PCnext;
// ID stage
wire ID_stall;
wire ID_flush;
wire [31:0] ID_inst;
wire [31:0] ID_PCnext;
wire [4:0] ID_reg_dst;
wire [31:0] ID_data_a, ID_data_b, ID_data_c;
//wire [20:0] aluc;
wire ID_sign;
wire ID_memread, ID_memwrite;
wire [31:0] ID_memaddr;
wire [8:0] ID_load_op;
wire [5:0] ID_store_op;
wire ID_memtoreg, ID_regwrite;
wire [31:0] EX_data_a, EX_data_b, EX_data_c;
wire [20:0] EX_aluc;
wire EX_sign;
wire EX_memread, EX_memwrite;
wire [31:0] EX_memaddr;
wire [8:0] EX_load_op;
wire [5:0] EX_store_op;
wire EX_memtoreg, EX_regwrite;
// EXE stage:
wire EX_stall;
wire EX_flush;
wire [31:0] EX_alu_out;
wire [31:0] EX_alu_out_t;
wire [4:0] EX_rt_rd;
wire M_regwrite;
wire M_memtoreg;
wire M_memread;
wire M_memwrite;
wire [31:0] M_memaddr;
wire [8:0] M_load_op;
wire [5:0] M_store_op;
wire [31:0] M_alu_out;
wire [31:0] M_readdata;
wire [4:0] M_rt_rd;
wire M_flush;
wire M_stall;
wire WB_stall;
wire WB_regwrite;
wire WB_memtoreg;
wire [31:0] WB_readdata;
wire [31:0] WB_alu_out;
wire [4:0] WB_rtrd;
IF_stage IF_stage_0(/*AUTOINST*/
// Outputs
.ID_inst (ID_inst[31:0]),
.ID_PCnext (ID_PCnext[31:0]),
// Inputs
.clk (clk),
.rst (rst),
.IF_stall (IF_stall),
.IF_flush (IF_flush),
.ID_stall (ID_stall),
.IF_inst (IF_inst[31:0]),
.IF_PCnext (IF_PCnext[31:0]),
.IF_PC (IF_PC[31:0]));
always @(posedge clk) begin
if (rst)
PC <= 32'b0;
else begin
PC <= PCnext;
PCadd4 <= PC + 32'h0000_0004;
end
end
mux2 #(.WIDTH(32)) PC_mux(
.sel (jump|branch),
.in0 (PCadd4),
.in1 (PCout),
.out (PCnext)
);
rom rom_0(
.PC (PC),
.inst (IF_inst),
.clk (clk)
);
//wire [31:0] target_offset;
//wire [25:0] inst_idx;
//wire [4:0] regdst;
decode decode_0(
.clk (clk),
.inst_in (ID_inst),
.PCin (ID_PCnext),
.regrs_data (regrs_data),
.regrt_data (regrt_data),
//Outputs
.PCout (PCout),
.jump (jump),
.ssnop (ssnop),
.branch (branch),
.aluc (ID_aluc),
.sign (ID_sign),
//.base (base),
//.immediate (immediate),
.store (store),
.store_op (ID_store_op),
.op_a (ID_data_a),
.op_b (ID_data_b),
.op_sa (ID_data_c),
.move (move),
.move_op (move_op),
.rs (rs),
.rt (rt),
.rd (rd),
.nop (nop),
.load (load),
.load_op (ID_load_op),
//.target_offset(target_offset),
//.inst_idx (inst_idx),
.regwrite (ID_regwrite),
.memtoreg (ID_memtoreg),
.memread (ID_memread),
.regdst (ID_reg_dst),
.memwrite (ID_memwrite),
.memaddr (ID_memaddr)
);
ID_stage ID_stage_0(/*AUTOINST*/
// Outputs
.EX_data_a (EX_data_a[31:0]),
.EX_data_b (EX_data_b[31:0]),
.EX_data_c (EX_data_c[31:0]),
.EX_aluc (EX_aluc[20:0]),
.EX_sign (EX_sign),
.EX_memread (EX_memread),
.EX_memwrite (EX_memwrite),
.EX_memaddr (EX_memaddr),
.EX_load_op (EX_load_op[8:0]),
.EX_store_op (EX_store_op[5:0]),
.EX_memtoreg (EX_memtoreg),
.EX_regwrite (EX_regwrite),
// Inputs
.clk (clk),
.rst (rst),
.ID_stall (ID_stall),
.ID_flush (ID_flush),
.EX_stall (EX_stall),
.ID_reg_dst (ID_reg_dst[4:0]),
.ID_data_a (ID_data_a[31:0]),
.ID_data_b (ID_data_b[31:0]),
.ID_data_c (ID_data_c[31:0]),
.ID_aluc (ID_aluc),
.ID_sign (ID_sign),
.ID_memread (ID_memread),
.ID_memwrite (ID_memwrite),
.ID_memaddr (ID_memaddr),
.ID_load_op (ID_load_op[8:0]),
.ID_store_op (ID_store_op[5:0]),
.ID_memtoreg (ID_memtoreg),
.ID_regwrite (ID_regwrite));
alu alu_0(
//Inputs
//.data_c (ID_data_c),
.clk (clk),
.aluc (EX_aluc),
.sign (EX_sign),
.data_a (EX_data_a),
.data_b (EX_data_b),
.data_c (EX_data_c),
//Outputs
.data_out_t (EX_alu_out_t),
.overflow (overflow),
.ready (ready),
.data_out (EX_alu_out));
EX_stage EX_stage_0(
// Outputs
.M_regwrite (M_regwrite),
.M_memtoreg (M_memtoreg),
.M_memread (M_memread),
.M_memwrite (M_memwrite),
.M_memaddr (M_memaddr),
.M_load_op (M_load_op[8:0]),
.M_store_op (M_store_op[5:0]),
.M_alu_out (M_alu_out[31:0]),
.M_rt_rd (M_rt_rd[4:0]),
// Inputs
.clk (clk),
.rst (rst),
.EX_stall (EX_stall),
.EX_flush (EX_flush),
.M_stall (M_stall),
.EX_regwrite (EX_regwrite),
//.EX_reg_dst (ID_reg_dst),
.EX_memtoreg (EX_memtoreg),
.EX_memread (EX_memread),
.EX_memwrite (EX_memwrite),
.EX_memaddr (EX_memaddr),
.EX_load_op (EX_load_op[8:0]),
.EX_store_op (EX_store_op[5:0]),
.EX_alu_out (EX_alu_out[31:0]),
.EX_alu_out_t (EX_alu_out_t[31:0]),
.EX_rt_rd (ID_reg_dst));
reg [31:0] gpr_data_in;
always @* begin
case (WB_memtoreg)
1'b1: gpr_data_in <= WB_readdata;
1'b0: gpr_data_in <= WB_alu_out;
endcase
end
gpr gpr_0(
// Outputs
.reg_out1 (regrt_data),
.reg_out2 (regrs_data),
// Inputs
.clk (clk),
.regwrite (WB_regwrite),
.data_in (gpr_data_in),
.write_addr (WB_rtrd),
.reg_addr1 (rs),
.reg_addr2 (rt));
data_ram data_ram_0(
.clk (clk),
.rst (rst),
.m_read (M_memread),
.m_write (M_memwrite),
.m_addr (M_memaddr),
.m_din (memdata_in),
// Outputs
.m_dout (M_readdata)
);
MEM_stage MEM_stage_0(
// Outputs
.WB_regwrite (WB_regwrite),
.WB_memtoreg (WB_memtoreg),
.WB_readdata (WB_readdata),
.WB_alu_out (WB_alu_out[31:0]),
.WB_rt_rd (WB_rtrd),
// Inputs
.clk (clk),
.rst (rst),
.M_flush (M_flush),
.M_stall (M_stall),
.WB_stall (WB_stall),
.M_regwrite (M_regwrite),
.M_memtoreg (M_memtoreg),
.M_readdata (M_readdata),
.M_alu_out (M_alu_out[31:0]),
.M_rt_rd (M_rt_rd[4:0]));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A211OI_SYMBOL_V
`define SKY130_FD_SC_LS__A211OI_SYMBOL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a211oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A211OI_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2B_BEHAVIORAL_V
`define SKY130_FD_SC_LS__NAND2B_BEHAVIORAL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nand2b (
Y ,
A_N,
B
);
// Module ports
output Y ;
input A_N;
input B ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire or0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y, not0_out, A_N );
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2B_BEHAVIORAL_V |
/******************************************************************************/
/* FPGA Sort for VC707 ArchLab. TOKYO TECH */
/* Version 2014-11-26 */
/******************************************************************************/
`default_nettype none
`include "define.v"
`include "core.v"
/******************************************************************************/
module top_sim;
reg CLK, RST;
wire CLK100M = CLK;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
wire initdone;
wire sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] lcnt;
always @(posedge CLK) lcnt <= (RST) ? 0 : (c.last_phase && c.initdone) ? lcnt + 1 : lcnt;
reg [31:0] cnt0_0, cnt1_0, cnt2_0, cnt3_0, cnt4_0, cnt5_0, cnt6_0, cnt7_0, cnt8_0;
always @(posedge CLK) cnt0_0 <= (RST) ? 0 : (c.phase_a==0 && c.initdone) ? cnt0_0 + 1 : cnt0_0;
always @(posedge CLK) cnt1_0 <= (RST) ? 0 : (c.phase_a==1 && c.initdone) ? cnt1_0 + 1 : cnt1_0;
always @(posedge CLK) cnt2_0 <= (RST) ? 0 : (c.phase_a==2 && c.initdone) ? cnt2_0 + 1 : cnt2_0;
always @(posedge CLK) cnt3_0 <= (RST) ? 0 : (c.phase_a==3 && c.initdone) ? cnt3_0 + 1 : cnt3_0;
always @(posedge CLK) cnt4_0 <= (RST) ? 0 : (c.phase_a==4 && c.initdone) ? cnt4_0 + 1 : cnt4_0;
always @(posedge CLK) cnt5_0 <= (RST) ? 0 : (c.phase_a==5 && c.initdone) ? cnt5_0 + 1 : cnt5_0;
always @(posedge CLK) cnt6_0 <= (RST) ? 0 : (c.phase_a==6 && c.initdone) ? cnt6_0 + 1 : cnt6_0;
always @(posedge CLK) cnt7_0 <= (RST) ? 0 : (c.phase_a==7 && c.initdone) ? cnt7_0 + 1 : cnt7_0;
always @(posedge CLK) cnt8_0 <= (RST) ? 0 : (c.phase_a==8 && c.initdone) ? cnt8_0 + 1 : cnt8_0;
reg [31:0] cnt0_1, cnt1_1, cnt2_1, cnt3_1, cnt4_1, cnt5_1, cnt6_1, cnt7_1, cnt8_1;
always @(posedge CLK) cnt0_1 <= (RST) ? 0 : (c.phase_b==0 && c.initdone) ? cnt0_1 + 1 : cnt0_1;
always @(posedge CLK) cnt1_1 <= (RST) ? 0 : (c.phase_b==1 && c.initdone) ? cnt1_1 + 1 : cnt1_1;
always @(posedge CLK) cnt2_1 <= (RST) ? 0 : (c.phase_b==2 && c.initdone) ? cnt2_1 + 1 : cnt2_1;
always @(posedge CLK) cnt3_1 <= (RST) ? 0 : (c.phase_b==3 && c.initdone) ? cnt3_1 + 1 : cnt3_1;
always @(posedge CLK) cnt4_1 <= (RST) ? 0 : (c.phase_b==4 && c.initdone) ? cnt4_1 + 1 : cnt4_1;
always @(posedge CLK) cnt5_1 <= (RST) ? 0 : (c.phase_b==5 && c.initdone) ? cnt5_1 + 1 : cnt5_1;
always @(posedge CLK) cnt6_1 <= (RST) ? 0 : (c.phase_b==6 && c.initdone) ? cnt6_1 + 1 : cnt6_1;
always @(posedge CLK) cnt7_1 <= (RST) ? 0 : (c.phase_b==7 && c.initdone) ? cnt7_1 + 1 : cnt7_1;
always @(posedge CLK) cnt8_1 <= (RST) ? 0 : (c.phase_b==8 && c.initdone) ? cnt8_1 + 1 : cnt8_1;
generate
if (`INITTYPE=="reverse" || `INITTYPE=="sorted") begin
always @(posedge CLK) begin /// note
if (c.initdone) begin
$write("%d|%d|state(%d)", cnt[19:0], c.last_phase, c.state);
$write("|");
if (c.F01_deq0) $write("%d", c.F01_dot0); else $write(" ");
if (c.F01_deq1) $write("%d", c.F01_dot1); else $write(" ");
$write("|");
if (d.app_wdf_wren) $write(" |M%d %d ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
always @(posedge CLK) begin
if (c.sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("last(%1d): %d cycles\n", `LAST_PHASE, lcnt);
$write("phase0: %d %d cycles\n", cnt0_0, cnt0_1);
$write("phase1: %d %d cycles\n", cnt1_0, cnt1_1);
$write("phase2: %d %d cycles\n", cnt2_0, cnt2_1);
$write("phase3: %d %d cycles\n", cnt3_0, cnt3_1);
$write("phase4: %d %d cycles\n", cnt4_0, cnt4_1);
$write("phase5: %d %d cycles\n", cnt5_0, cnt5_1);
$write("phase6: %d %d cycles\n", cnt6_0, cnt6_1);
$write("phase7: %d %d cycles\n", cnt7_0, cnt7_1);
$write("phase8: %d %d cycles\n", cnt8_0, cnt8_1);
$write("Sorting finished!\n");
$finish();
end
end
end else if (`INITTYPE == "xorshift") begin
integer fp;
initial begin
fp = $fopen("test.txt", "w");
end
always @(posedge CLK) begin /// note
if (c.last_phase && c.F01_deq0) begin
$write("%08x ", c.F01_dot0);
$fwrite(fp, "%08x ", c.F01_dot0);
$fflush();
end
if (c.sortdone) begin
$fclose(fp);
$finish();
end
end
end
endgenerate
/***** DRAM Controller & DRAM Instantiation *****/
/**********************************************************************************************/
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
wire ERROR;
/***** Core Module Instantiation *****/
/**********************************************************************************************/
CORE c(CLK100M, RST, initdone, sortdone,
d_busy, d_din, d_w, d_dout, d_douten, d_req, d_initadr, d_blocks, ERROR);
endmodule
/**************************************************************************************************/
/**************************************************************************************************/
module DRAM (input wire CLK, //
input wire RST, //
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`DRAMW-1:0] D_DIN, //
output wire D_W, //
output reg [`DRAMW-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY); //
/******* DRAM ******************************************************/
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
///////////////////////////////////////////////////////////////////////////////////
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`DRAMW-1:0] app_wdf_data;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
// outputs of u_dram
wire [`DRAMW-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid=1; // in simulation, always ready !!
wire app_rdy = 1; // in simulation, always ready !!
wire app_wdf_rdy = 1; // in simulation, always ready !!
wire ui_clk = CLK;
reg [1:0] mode;
reg [`DRAMW-1:0] app_wdf_data_buf;
reg [31:0] caddr; // check address
reg [31:0] remain, remain2; //
reg [7:0] req_state; //
///////////////////////////////////////////////////////////////////////////////////
reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0];
reg [31:0] app_addr;
reg [31:0] dram_addr;
always @(posedge CLK) dram_addr <= app_addr;
always @(posedge CLK) begin /***** DRAM WRITE *****/
if (RST) begin end
else if(app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data;
end
assign app_rd_data = mem[app_addr[27:3]];
assign app_wdf_data = D_DIN;
assign D_BUSY = (mode!=M_REQ); // DRAM busy
assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
always @(posedge ui_clk) begin
if (RST) begin
mode <= M_REQ;
{app_addr, app_cmd, app_en, app_wdf_wren} <= 0;
{D_DOUT, D_DOUTEN} <= 0;
{caddr, remain, remain2, req_state} <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
else begin
app_wdf_wren <= 0;
app_en <= 0;
end
end
//////////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain2 <= remain2 - 1;
if(remain2==1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
end
end
end
/////////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
// app_wdf_data <= D_DIN;
app_wdf_wren <= 1;
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
app_en <= 0;
end
end
else app_wdf_wren <= 0;
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule
/**************************************************************************************************/
`default_nettype wire
|
//Legal Notice: (C)2021 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_tester_nios2_gen2_0_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
nios_tester_nios2_gen2_0_cpu_debug_slave_tck the_nios_tester_nios2_gen2_0_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
nios_tester_nios2_gen2_0_cpu_debug_slave_sysclk the_nios_tester_nios2_gen2_0_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic nios_tester_nios2_gen2_0_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam nios_tester_nios2_gen2_0_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// nios_tester_nios2_gen2_0_cpu_debug_slave_phy.sld_instance_index = 0,
// nios_tester_nios2_gen2_0_cpu_debug_slave_phy.sld_ir_width = 2,
// nios_tester_nios2_gen2_0_cpu_debug_slave_phy.sld_mfg_id = 70,
// nios_tester_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_action = "",
// nios_tester_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// nios_tester_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_total_length = 0,
// nios_tester_nios2_gen2_0_cpu_debug_slave_phy.sld_type_id = 34,
// nios_tester_nios2_gen2_0_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:33:51 11/06/2015
// Design Name: Booth_Multiplier_II
// Module Name: /home/sidharth/Documents/Xilinx Projects/NEW2/Booth_Tester_2.v
// Project Name: NEW2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Booth_Multiplier_II
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Booth_Tester_2;
// Inputs
reg [3:0] multiplicand;
reg [3:0] multiplier;
// Outputs
wire [7:0] product;
// Instantiate the Unit Under Test (UUT)
Booth_Multiplier_II uut (
.product(product),
.multiplicand(multiplicand),
.multiplier(multiplier)
);
initial begin
// Initialize Inputs
multiplicand = 4'b1100;
multiplier = 4'b1011;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE revB.2 compliant I2C Master controller Top-level ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_top.v,v 1.1 2008-11-08 13:15:10 sfielding Exp $
//
// $Date: 2008-11-08 13:15:10 $
// $Revision: 1.1 $
// $Author: sfielding $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.11 2005/02/27 09:26:24 rherveille
// Fixed register overwrite issue.
// Removed full_case pragma, replaced it by a default statement.
//
// Revision 1.10 2003/09/01 10:34:38 rherveille
// Fix a blocking vs. non-blocking error in the wb_dat output mux.
//
// Revision 1.9 2003/01/09 16:44:45 rherveille
// Fixed a bug in the Command Register declaration.
//
// Revision 1.8 2002/12/26 16:05:12 rherveille
// Small code simplifications
//
// Revision 1.7 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.6 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.5 2001/11/10 10:52:55 rherveille
// Changed PRER reset value from 0x0000 to 0xffff, conform specs.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "i2c_master_defines.v"
module i2c_master_top(
wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
// parameters
parameter ARST_LVL = 1'b0; // asynchronous reset level
//
// inputs & outputs
//
// wishbone signals
input wb_clk_i; // master clock input
input wb_rst_i; // synchronous active high reset
input arst_i; // asynchronous reset
input [2:0] wb_adr_i; // lower address bits
input [7:0] wb_dat_i; // databus input
output [7:0] wb_dat_o; // databus output
input wb_we_i; // write enable input
input wb_stb_i; // stobe/core select signal
input wb_cyc_i; // valid bus cycle input
output wb_ack_o; // bus cycle acknowledge output
output wb_inta_o; // interrupt request signal output
reg [7:0] wb_dat_o;
reg wb_ack_o;
reg wb_inta_o;
// I2C signals
// i2c clock line
input scl_pad_i; // SCL-line input
output scl_pad_o; // SCL-line output (always 1'b0)
output scl_padoen_o; // SCL-line output enable (active low)
// i2c data line
input sda_pad_i; // SDA-line input
output sda_pad_o; // SDA-line output (always 1'b0)
output sda_padoen_o; // SDA-line output enable (active low)
//
// variable declarations
//
// registers
reg [15:0] prer; // clock prescale register
reg [ 7:0] ctr; // control register
reg [ 7:0] txr; // transmit register
wire [ 7:0] rxr; // receive register
reg [ 7:0] cr; // command register
wire [ 7:0] sr; // status register
// done signal: command completed, clear command register
wire done;
// core enable signal
wire core_en;
wire ien;
// status register signals
wire irxack;
reg rxack; // received aknowledge from slave
reg tip; // transfer in progress
reg irq_flag; // interrupt pending flag
wire i2c_busy; // bus busy (start signal detected)
wire i2c_al; // i2c bus arbitration lost
reg al; // status register arbitration lost bit
//
// module body
//
// generate internal reset
wire rst_i = arst_i ^ ARST_LVL;
// generate wishbone signals
wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;
// generate acknowledge output signal
always @(posedge wb_clk_i)
wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
// assign DAT_O
always @(posedge wb_clk_i)
begin
case (wb_adr_i) // synopsis parallel_case
3'b000: wb_dat_o <= #1 prer[ 7:0];
3'b001: wb_dat_o <= #1 prer[15:8];
3'b010: wb_dat_o <= #1 ctr;
3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
3'b101: wb_dat_o <= #1 txr;
3'b110: wb_dat_o <= #1 cr;
3'b111: wb_dat_o <= #1 0; // reserved
endcase
end
// generate registers
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else if (wb_rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else
if (wb_wacc)
case (wb_adr_i) // synopsis parallel_case
3'b000 : prer [ 7:0] <= #1 wb_dat_i;
3'b001 : prer [15:8] <= #1 wb_dat_i;
3'b010 : ctr <= #1 wb_dat_i;
3'b011 : txr <= #1 wb_dat_i;
default: ;
endcase
// generate command register (special case)
always @(posedge wb_clk_i or negedge rst_i)
if (~rst_i)
cr <= #1 8'h0;
else if (wb_rst_i)
cr <= #1 8'h0;
else if (wb_wacc)
begin
if (core_en & (wb_adr_i == 3'b100) )
cr <= #1 wb_dat_i;
end
else
begin
if (done | i2c_al)
cr[7:4] <= #1 4'h0; // clear command bits when done
// or when aribitration lost
cr[2:1] <= #1 2'b0; // reserved bits
cr[0] <= #1 2'b0; // clear IRQ_ACK bit
end
// decode command register
wire sta = cr[7];
wire sto = cr[6];
wire rd = cr[5];
wire wr = cr[4];
wire ack = cr[3];
wire iack = cr[0];
// decode control register
assign core_en = ctr[7];
assign ien = ctr[6];
// hookup byte controller block
i2c_master_byte_ctrl byte_controller (
.clk ( wb_clk_i ),
.rst ( wb_rst_i ),
.nReset ( rst_i ),
.ena ( core_en ),
.clk_cnt ( prer ),
.start ( sta ),
.stop ( sto ),
.read ( rd ),
.write ( wr ),
.ack_in ( ack ),
.din ( txr ),
.cmd_ack ( done ),
.ack_out ( irxack ),
.dout ( rxr ),
.i2c_busy ( i2c_busy ),
.i2c_al ( i2c_al ),
.scl_i ( scl_pad_i ),
.scl_o ( scl_pad_o ),
.scl_oen ( scl_padoen_o ),
.sda_i ( sda_pad_i ),
.sda_o ( sda_pad_o ),
.sda_oen ( sda_padoen_o )
);
// status register block + interrupt request signal
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else if (wb_rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else
begin
al <= #1 i2c_al | (al & ~sta);
rxack <= #1 irxack;
tip <= #1 (rd | wr);
irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
end
// generate interrupt request signals
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
wb_inta_o <= #1 1'b0;
else if (wb_rst_i)
wb_inta_o <= #1 1'b0;
else
wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
// assign status register bits
assign sr[7] = rxack;
assign sr[6] = i2c_busy;
assign sr[5] = al;
assign sr[4:2] = 3'h0; // reserved
assign sr[1] = tip;
assign sr[0] = irq_flag;
endmodule
|
`include "Defintions.v"
`include "Collaterals.v"
module VGA_Controller (
input wire Clock,
input wire Enable,
input wire Reset,
input wire[2:0] iPixel,
output wire oHorizontalSync,
output wire oVerticalSync,
output wire oRed,
output wire oGreen,
output wire oBlue,
output wire[9:0] oColumnCount,
output wire[9:0] oRowCount
);
wire[10:0] wColumnCount;
wire wColumnReset, wRowReset;
wire[9:0] wColumnCount_2, wRowCount;
assign wColumnCount_2 = {wColumnCount[10:1]};
assign wColumnReset = (wColumnCount == 11'd1599);
assign wRowReset = (wRowCount == 10'd524 && wColumnReset);
assign oColumnCount = wColumnCount_2;
assign oRowCount = wRowCount;
UPCOUNTER_POSEDGE # ( 11 ) COLUMN_COUNTER
(
.Clock( Clock ),
.Reset( wColumnReset | Reset ),
.Initial( 11'd0 ),
.Enable( 1'b1 ),
.Q( wColumnCount )
);
UPCOUNTER_POSEDGE # ( 10 ) ROW_COUNTER
(
.Clock( Clock ),
.Reset( wRowReset | Reset ),
.Initial( 10'd0 ),
.Enable( wColumnReset ),
.Q( wRowCount )
);
parameter H_VISIBLE_AREA = 640;
parameter H_FRONT_PORCH = 16;
parameter H_PULSE = 96;
parameter H_BACK_PORCH = 48;
parameter HORIZONTAL_LINE = 800;
parameter V_VISIBLE_AREA = 480;
parameter V_FRONT_PORCH = 10;
parameter V_PULSE = 2;
parameter V_BACK_PORCH = 33;
parameter VERTICAL_LINE = 525;
assign oHorizontalSync =
(
wColumnCount_2 >= (H_VISIBLE_AREA + H_FRONT_PORCH ) &&
wColumnCount_2 <= (H_VISIBLE_AREA + H_FRONT_PORCH + H_PULSE )
) ? 1'b0 : 1'b1;
assign oVerticalSync =
(
wRowCount >= (V_VISIBLE_AREA + V_FRONT_PORCH ) &&
wRowCount <= (V_VISIBLE_AREA + V_FRONT_PORCH + V_PULSE )
) ? 1'b0 : 1'b1;
assign {oRed,oGreen,oBlue} = (wColumnCount_2 < H_VISIBLE_AREA && wRowCount < V_VISIBLE_AREA) ?
{iPixel} : //display color
{`BLACK}; //black
endmodule
|
(* Copyright (c) 2008-2012, 2015, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import List.
Require Import Cpdt.CpdtTactics.
Set Implicit Arguments.
Set Asymmetric Patterns.
(* end hide *)
(*
(** %\chapter{Proof Search in Ltac}% *)
*)
(** %\chapter{Ltac による証明探索}% *)
(**
(* We have seen many examples of proof automation so far, some with tantalizing code snippets from Ltac, Coq's domain-specific language for proof search procedures. This chapter aims to give a bottom-up presentation of the features of Ltac, focusing in particular on the Ltac %\index{tactics!match}%[match] construct, which supports a novel approach to backtracking search. First, though, we will run through some useful automation tactics that are built into Coq. They are described in detail in the manual, so we only outline what is possible. *)
これまで多くの証明の自動化の例を見てきましたが、
Coqの証明探索の手続きのためのドメイン固有言語(domain-specific language)である Ltac に
よって、一部のコードの断片は魅力的なものでした(some with tantalizing code snippets)。
この章は、Ltac の機能をボトムアップに示すことを目標に、
特に、バックトラッキング探索のための独創的なアプローチをサポートする、
Ltac の %\index{tactics!match}%[match] 構成要素(construct)に焦点をあてます。
最初に、Coqに組み込まれている便利な自動化タクティクをいくつか実行します。
それらの詳細はマニュアルに記載されているので、出来ることを概説するだけにします。
*)
(*
(** * Some Built-In Automation Tactics *)
*)
(** * 組み込み 自動化タクティク *)
(**
(* A number of tactics are called repeatedly by [crush]. The %\index{tactics!intuition}%[intuition] tactic simplifies propositional structure of goals. The %\index{tactics!congruence}%[congruence] tactic applies the rules of equality and congruence closure, plus properties of constructors of inductive types. The %\index{tactics!omega}%[omega] tactic provides a complete decision procedure for a theory that is called %\index{linear arithmetic}%quantifier-free linear arithmetic or %\index{Presburger arithmetic}%Presburger arithmetic, depending on whom you ask. That is, [omega] proves any goal that follows from looking only at parts of that goal that can be interpreted as propositional formulas whose atomic formulas are basic comparison operations on natural numbers or integers, with operands built from constants, variables, addition, and subtraction (with multiplication by a constant available as a shorthand for addition or subtraction).
*)
多くのタクティクが [crush] によって繰り返し呼び出されます。
%\index{tactics!intuition}%[intuition] タクティクは、
ゴールの命題論理的構造を簡略化(simplifies)します。
%\index{tactics!congruence}%[congruence] タクティクは、
等式と合同閉包(congruence closure)のルールに加え、帰納型のコンストラクタの属性を適用します。
%\index{tactics!omega}%[omega] タクティクは、あなたの求めに応じて(depending on whom you ask)、
%\index{linear arithmetic}%quantifier-free linear arithmetic 量化子のない線形算術、または、
%\index{Presburger arithmetic}%Presburger arithmetic プレスバーガー算術と呼ばれる
理論に対する完全な決定手続きを提供します。
すなわち [omega] は、
その原始式(atomic formulas)が、自然数または整数を基本的な比較演算の対象とし、
そのオペランドが定数、変数、加算および減算から構成された、
（加算または減算の省略形として利用可能な定数による乗算を含む）
命題論理の式として解釈されることのできる、
ゴールの部分のみを見ることに続く
(that follows from looking only at parts of that goal)
任意のゴールを証明します。
(*
The %\index{tactics!ring}%[ring] tactic solves goals by appealing to the axioms of rings or semi-rings (as in algebra), depending on the type involved. Coq developments may declare new types to be parts of rings and semi-rings by proving the associated axioms. There is a similar tactic [field] for simplifying values in fields by conversion to fractions over rings. Both [ring] and [field] can only solve goals that are equalities. The %\index{tactics!fourier}%[fourier] tactic uses Fourier's method to prove inequalities over real numbers, which are axiomatized in the Coq standard library.
*)
%\index{tactics!ring}%[ring] は、
関与する型に依存して、(代数のように)環まはた半環の公理を適用することによって、
ゴールを解きます。
Coqの開発では、関連する公理を証明することによって、
新しい型を環と半環の一部として宣言することができます。
環における分数に変換することで、
体の値を簡略化するための同様のタクティク [field] があります。
[ring] と [field] の両方は、等式のゴールだけを解くことができます。
%\index{tactics!fourier}%[fourier] タクティクは、
Coq標準ライブラリで公理化された実数の不等式を証明するフーリエの方法を使用します。
(*
The%\index{setoids}% _setoid_ facility makes it possible to register new equivalence relations to be understood by tactics like [rewrite]. For instance, [Prop] is registered as a setoid with the equivalence relation "if and only if." The ability to register new setoids can be very useful in proofs of a kind common in math, where all reasoning is done after "modding out by a relation."
*)
The%\index{setoids}% _setoid_ の手法(facility)は、
[rewrite] のようなタクティクによって理解される
新しい等価関係(equivalence relations)を
登録することを可能にします。
たとえば [Prop] は、"if and only if" の等価関係を setoid として登録されています。
新しい setoid を登録する能力は、
すべての推論(reasoning)が、
「関係によって改変された(modding out by a relation)」後に実行される箇所において、
数学で一般的な種類の証明において非常に有用です。
(*
There are several other built-in "black box" automation tactics, which one can learn about by perusing the Coq manual. The real promise of Coq, though, is in the coding of problem-specific tactics with Ltac. *)
Coq マニュアルを熟読することで学ぶことのできる、
組み込みの「ブラックボックス」な自動化タクティクがあります。
Coqの本当の約束事は、Ltacを使って、
問題に特化したタクティクのコーディングのなかにあります。
*)
(*
(** * Ltac Programming Basics *)
*)
(** * Ltac プログラミングの基礎 *)
(**
(* We have already seen many examples of Ltac programs. In the rest of this chapter, we attempt to give a thorough introduction to the important features and design patterns.
One common use for [match] tactics is identification of subjects for case analysis, as we see in this tactic definition. *)
すでに Ltac プロラムの多くの例を見てきました。
本章の残りでは、重要な機能とデザインパターンを徹底的に紹介しようとします。
[match] タクティクのひとつの共通の使い方は、
このタクティクの定義にあるように、
条件分析(case analysis)のための内容の識別です。
*)
(* begin thide *)
Ltac find_if :=
match goal with
| [ |- if ?X then _ else _ ] => destruct X
end.
(* end thide *)
(**
(* The tactic checks if the conclusion is an [if], [destruct]ing the test expression if so. Certain classes of theorem are trivial to prove automatically with such a tactic. *)
このタクティクは結論が [if] かどうかチェックし、もしそうなら、
条件式(test expression)を [destruct] します。
ある特定の種類の定理は、このようなタクティクによって、
自動的に証明することが簡単(trivial)です。
*)
Theorem hmm : forall (a b c : bool),
if a
then if b
then True
else True
else if c
then True
else True.
(* begin thide *)
intros; repeat find_if; constructor.
Qed.
(* end thide *)
(**
(* The %\index{tactics!repeat}%[repeat] that we use here is called a%\index{tactical}% _tactical_, or tactic combinator. The behavior of [repeat t] is to loop through running [t], running [t] on all generated subgoals, running [t] on _their_ generated subgoals, and so on. When [t] fails at any point in this search tree, that particular subgoal is left to be handled by later tactics. Thus, it is important never to use [repeat] with a tactic that always succeeds.
Another very useful Ltac building block is%\index{context patterns}% _context patterns_. *)
ここで使った %\index{tactics!repeat}%[repeat] は、
%\index{tactical}% _tactical_ タクティカル または タクティク・コンビネータ(tactic combinator)
と呼ばれます。
[repeat t] の振る舞いは、[t] を実行し、
すべての生成されたサブゴールに [t] を実行し、
＿それら＿ が生成したサブゴールに [t] を実行し、というぐあいに、
繰り返し続けることです。
この探索木の任意の点で [t] が失敗したとき、その特定のサブゴールは、
後のタクティクのによって扱われるために残されます。
なので、いつも成功するタクティクと一緒に [repeat] を使用しないことが重要です。
(* suhara: 繰り返しが終わらなくなるから *)
他のとても便利な Ltac の構成要素(building block)は、
%\index{context patterns}% _context patterns_ コンテキスト・パターン
です。
*)
(* begin thide *)
Ltac find_if_inside :=
match goal with
| [ |- context[if ?X then _ else _] ] => destruct X
end.
(* end thide *)
(**
(* The behavior of this tactic is to find any subterm of the conclusion that is an [if] and then [destruct] the test expression. This version subsumes [find_if]. *)
このタクティクの振る舞いは、結論の
[if] であり、その後に条件式を [destruct] する任意の部分項(subterm)を見つけることです。
このバージョンは [find_if] を含みます。
*)
Theorem hmm' : forall (a b c : bool),
if a
then if b
then True
else True
else if c
then True
else True.
(* begin thide *)
intros; repeat find_if_inside; constructor.
Qed.
(* end thide *)
(**
(* We can also use [find_if_inside] to prove goals that [find_if] does not simplify sufficiently. *)
[find_if-inside] を
[find_if] が十分に簡約できなかったゴールを証明するために使うことができます。
*)
Theorem hmm2 : forall (a b : bool),
(if a then 42 else 42) = (if b then 42 else 42).
(* begin thide *)
intros; repeat find_if_inside; reflexivity.
Qed.
(* end thide *)
(**
(* Many decision procedures can be coded in Ltac via "[repeat match] loops." For instance, we can implement a subset of the functionality of [tauto]. *)
多くの決定性の手続きは 「[repeat match] ループ」によって Ltac で記述することができます。
たとえば、[tauto] のサブセットの機能を実装することができます。
*)
(* begin thide *)
Ltac my_tauto :=
repeat match goal with
| [ H : ?P |- ?P ] => exact H
| [ |- True ] => constructor
| [ |- _ /\ _ ] => constructor
| [ |- _ -> _ ] => intro
| [ H : False |- _ ] => destruct H
| [ H : _ /\ _ |- _ ] => destruct H
| [ H : _ \/ _ |- _ ] => destruct H
| [ H1 : ?P -> ?Q, H2 : ?P |- _ ] => specialize (H1 H2)
end.
(* end thide *)
(**
(* Since [match] patterns can share unification variables between hypothesis and conclusion patterns, it is easy to figure out when the conclusion matches a hypothesis. The %\index{tactics!exact}%[exact] tactic solves a goal completely when given a proof term of the proper type.
It is also trivial to implement the introduction rules (in the sense of %\index{natural deduction}%natural deduction%~\cite{TAPLNatDed}%) for a few of the connectives. Implementing elimination rules is only a little more work, since we must give a name for a hypothesis to [destruct].
The last rule implements modus ponens, using a tactic %\index{tactics!specialize}%[specialize] which will replace a hypothesis with a version that is specialized to a provided set of arguments (for quantified variables or local hypotheses from implications). By convention, when the argument to [specialize] is an application of a hypothesis [H] to a set of arguments, the result of the specialization replaces [H]. For other terms, the outcome is the same as with [generalize]. *)
[match] のパターンはユニフィケーション変数を仮定と結論のパターンの間で共有することができ、
結論が仮説といつマッチするかを把握することは容易です。
%\index{tactics!exact}%[exact] タクティクは、適切な型の証明項が与えられているとき、
ゴールを完全に解きます。
（自然演繹 %\index{natural deduction}%natural deduction%~\cite{TAPLNatDed}% の意味において）
いくつかの結合子についての導入(introduction)のルールを実装することもまた自明です。
(* suhara: connectives 結合子 ∧と∨ *)
除去(elimination)のルールを実装することはもう少しの作業です。
[destruct]に仮説の名前を付ける必要があるからです。
最後のルールは、
仮説を与えられた引数の集合（量化された変数、または、含意による局所的仮説のため）
に特化したバージョンに置き換える %\index{tactics!specialize}%[specialize] タクティクを使って
三段論法(modus ponens)を実装します。
慣例によって、
[specialize] への引数が一連の引数に対する仮説 [H] の適用である場合、そ
の特殊化の結果が [H] に置き換えられます。
他の項については、結果は [generalize] と同じです。
*)
Section propositional.
Variables P Q R : Prop.
Theorem propositional : (P \/ Q \/ False) /\ (P -> Q) -> True /\ Q.
(* begin thide *)
my_tauto.
Qed.
(* end thide *)
End propositional.
(**
(* It was relatively easy to implement modus ponens, because we do not lose information by clearing every implication that we use. If we want to implement a similarly complete procedure for quantifier instantiation, we need a way to ensure that a particular proposition is not already included among our hypotheses. To do that effectively, we first need to learn a bit more about the semantics of [match].
*)
すべての含意(implication)を消すこと(clearing)によって情報を失なわないので、
三段論法の実装をするのは比較的簡単です。
もし、量化された含意についての同様の完全な手続きを実装するなら、
特定の命題がまだ仮説に含まれていないことを保証する方法が必要です。
これを効果的に行うには、最初に [match] の意味についてもう少し学ぶ必要があります。
(*
It is tempting to assume that [match] works like it does in ML. In fact, there are a few critical differences in its behavior. One is that we may include arbitrary expressions in patterns, instead of being restricted to variables and constructors. Another is that the same variable may appear multiple times, inducing an implicit equality constraint.
*)
[match] はMLのように動作すると想定するのは魅力的です。
実際に、その動作にはいくつかの重要な違いがあります。
ひとつは、変数やコンストラクタに制限されることなく、パターンに任意の式を含めることです。
もうひとつは、同じ変数が複数回現れることがあり、暗黙に等値の制約を含むことです。
(*
There is a related pair of two other differences that are much more important than the others. The [match] construct has a _backtracking semantics for failure_. In ML, pattern matching works by finding the first pattern to match and then executing its body. If the body raises an exception, then the overall match raises the same exception. In Coq, failures in case bodies instead trigger continued search through the list of cases.
*)
他のふたつの違いは、他のものよりはるかに重要です。
[match] 構文は、 ＿失敗によるバックトラッキングの意味＿ を持っています。
MLでは、パターンマッチングは、一致させる最初のパターンを見つけてから、
その本体を実行することによって動作します。
本体が例外を発生させた場合、全体の一致は同じ例外を発生させます。
Coqでは、ケース条件本体の失敗は、代わりにケースのリストを通じて検索を続行します。
(*
For instance, this (unnecessarily verbose) proof script works: *)
例えば、この（不必要で冗長な）証明のスクリプトはこのように動きます。
*)
Theorem m1 : True.
match goal with
| [ |- _ ] => intro
| [ |- True ] => constructor
end.
(* begin thide *)
Qed.
(* end thide *)
(**
(* The first case matches trivially, but its body tactic fails, since the conclusion does not begin with a quantifier or implication. In a similar ML match, the whole pattern-match would fail. In Coq, we backtrack and try the next pattern, which also matches. Its body tactic succeeds, so the overall tactic succeeds as well.
The example shows how failure can move to a different pattern within a [match]. Failure can also trigger an attempt to find _a different way of matching a single pattern_. Consider another example: *)
最初のケースは簡単に一致しますが、その結論は限定子や含意から始まるわけではないので、
その本体のタクティクは失敗します。
同様のMLのマッチでは、パターンマッチ全体が失敗します。
Coqでは、次のパターンを取り戻して試してみます。これも一致します。
その本体のタクティクは成功するので、全体のタクティクも成功します。
この例では、失敗が [match] 内の別のパターンにどのように移動するかを示しています。
失敗はまた、＿単一のパターンにマッチする異なる方法を見つける試み＿を引き起こします。
別の例を考えてみましょう。
*)
Theorem m2 : forall P Q R : Prop, P -> Q -> R -> Q.
intros; match goal with
| [ H : _ |- _ ] => idtac H
end.
(**
(* Coq prints "[H1]". By applying %\index{tactics!idtac}%[idtac] with an argument, a convenient debugging tool for "leaking information out of [match]es," we see that this [match] first tries binding [H] to [H1], which cannot be used to prove [Q]. Nonetheless, the following variation on the tactic succeeds at proving the goal: *)
Coq は [H1] を印刷します。
(* suhara: Goalが仮定H1と同じと言っているが、GoalがQで、仮定は H:P, H0:Q, H1:R である。 *)
ひとつの引数を取って %\index{tactics!idtac}%[idtac] を適用することは、
[match] 情報を取り出すための便利なデバッキングツールです。
この [match] は最初に [H] を [H1] に束縛しようとしますが、
[H1] は [Q] を証明するために使用できません。
(* suhara: H1 は H0 *)
それにもかかわらず、タクティクの次のバリエーションはゴールを証明するのに成功します：
*)
(* begin thide *)
match goal with
| [ H : _ |- _ ] => exact H
end.
Qed.
(* end thide *)
(**
(* The tactic first unifies [H] with [H1], as before, but [exact H] fails in that case, so the tactic engine searches for more possible values of [H]. Eventually, it arrives at the correct value, so that [exact H] and the overall tactic succeed. *)
タクティクは最初に [H] と [H1] (* suhara: [H] とするべき *) をユニファイします、
その場合は [exact H] が失敗するため、戦術エンジンは [H] の可能な値をさらに検索します。
最終的には、正しい値 (* suhara: [H0] *) に到達するので、[exact H] と全体のタクティクは成功します。
*)
(**
(* Now we are equipped to implement a tactic for checking that a proposition is not among our hypotheses: *)
では、命題が私たちの仮説の中にないことを確認するためのタクティクを実装する用意ができました：
*)
(* begin thide *)
Ltac notHyp P :=
match goal with
| [ _ : P |- _ ] => fail 1
| _ =>
match P with
| ?P1 /\ ?P2 => first [ notHyp P1 | notHyp P2 | fail 2 ]
| _ => idtac
end
end.
(* end thide *)
(**
(* We use the equality checking that is built into pattern-matching to see if there is a hypothesis that matches the proposition exactly. If so, we use the %\index{tactics!fail}%[fail] tactic. Without arguments, [fail] signals normal tactic failure, as you might expect. When [fail] is passed an argument [n], [n] is used to count outwards through the enclosing cases of backtracking search. In this case, [fail 1] says "fail not just in this pattern-matching branch, but for the whole [match]." The second case will never be tried when the [fail 1] is reached.
*)
パターン・マッチングにに組み込まれている等価性検査(equality checking)を使用して、
命題に正確に一致する仮説があるかどうかを調べます。もしそうなら、
%\index{tactics!fail}%[fail] タクティクを使用します。
引数がなければ、期待通りに、[fail] は通常のタクティクの失敗を通知します。
[fail] に引数 [n] が渡されると、
[n] は、バックトラック探索の囲む条件(case)を通して外側に向かってカウントするように使用されます。
この場合、[fail 1]は、「パターン・マッチングの分岐ではなく、[macth] 全体を失敗させる」
ことを示します。
[fail 1] に達すると、2番目の条件(case)は決して試行されません。
(*
This second case, used when [P] matches no hypothesis, checks if [P] is a conjunction. Other simplifications may have split conjunctions into their component formulas, so we need to check that at least one of those components is also not represented. To achieve this, we apply the %\index{tactics!first}%[first] tactical, which takes a list of tactics and continues down the list until one of them does not fail. The [fail 2] at the end says to [fail] both the [first] and the [match] wrapped around it.
*)
第2の条件(case)は、[P] が仮説と一致しないときに使用され、
[P] が連言(conjunction)であるかどうかをチェックします。
他の簡略化(simplification)では連言(conjunction)をその成分の式(component formula)
に分割することがあるため、
これらの成分の少なくともひとつも表現されていない
(* suhara: 成分の式がどれも「仮説を使って」表現されてない *)
ことを確認する必要があります。
これを達成するために、 %\index{tactics!first}%[first] タクティカルを適用します。
これはタクティクのリストを取り、
それらのひとつが失敗しないまで (* suhara: 最初のひとつが成功するまで *)
リストを続けます。
最後の [fail 2] は、[first] とその周囲に巻き込まれた [match] の両方が失敗することを示します。
(*
The body of the [?P1 /\ ?P2] case guarantees that, if it is reached, we either succeed completely or fail completely. Thus, if we reach the wildcard case, [P] is not a conjunction. We use %\index{tactics!idtac}%[idtac], a tactic that would be silly to apply on its own, since its effect is to succeed at doing nothing. Nonetheless, [idtac] is a useful placeholder for cases like what we see here.
*)
[?P1 /\ ?P2] の場合のボディ(* suhara: [=>] の右辺 *) は、
到達すれば完全に成功するか完全に失敗するかを保証します。
ワイルドカードの場合、[P] は連言ではありませんから、
%\index {tactics!idtac}%[idtac] を使用します。
これは、何もしないことで成功する効果があるため、単独で適用することは愚かなタクティクです。
それにもかかわらず、[idtac] は、ここで見ているような場合に便利な代用品(placeholder)です。
(*
With the non-presence check implemented, it is easy to build a tactic that takes as input a proof term and adds its conclusion as a new hypothesis, only if that conclusion is not already present, failing otherwise. *)
存在しないことのチェックを実装したことによって、
入力として証明項をとり、結論がまだ存在しない場合だけ、新しい仮説としてその結論を加え、
さもなければ失敗するタクティクを作ることは簡単です。
*)
(* begin thide *)
Ltac extend pf :=
let t := type of pf in
notHyp t; generalize pf; intro.
(* end thide *)
(**
(* We see the useful %\index{tactics!type of}%[type of] operator of Ltac. This operator could not be implemented in Gallina, but it is easy to support in Ltac. We end up with [t] bound to the type of [pf]. We check that [t] is not already present. If so, we use a [generalize]/[intro] combo to add a new hypothesis proved by [pf]. The tactic %\index{tactics!generalize}%[generalize] takes as input a term [t] (for instance, a proof of some proposition) and then changes the conclusion from [G] to [T -> G], where [T] is the type of [t] (for instance, the proposition proved by the proof [t]).
*)
Ltacの有用な %\index{tactics!type}%[type of] 演算子があります。
この演算子はGallinaでは実装できませんでしたが、Ltacでサポートするのは簡単です。
最終的に [t] は [pf] の型を束縛します。
[t] がまだ存在していないことを確認します。
もしそうなら、[generalize] / [intro] の組み合わせを使って、
[pf] によって証明された新しい仮説を追加します。
タクティク %\index{tactics!generalize}%[generalize] は、
入力として [t]（例えば命題の証明）をとり、
[T] が [t] の型であるとき、[G] から [T -> G] に結論を変えます。
(*
With these tactics defined, we can write a tactic [completer] for, among other things, adding to the context all consequences of a set of simple first-order formulas. *)
これらの定義されたタクティクで、
単純な一階論理の式の集合のすべての結果(consequence)
をコンテキストに加えるためのタクティク [completer] を書くことができます。
*)
(* begin thide *)
Ltac completer :=
repeat match goal with
| [ |- _ /\ _ ] => constructor
| [ H : _ /\ _ |- _ ] => destruct H
| [ H : ?P -> ?Q, H' : ?P |- _ ] => specialize (H H')
| [ |- forall x, _ ] => intro (* これは P x -> S x もintroする。 *)
| [ H : forall x, ?P x -> _, H' : ?P ?X |- _ ] => extend (H X H')
end.
(* end thide *)
(**
(* We use the same kind of conjunction and implication handling as previously. Note that, since [->] is the special non-dependent case of [forall], the fourth rule handles [intro] for implications, too.
*)
前の扱ったのと同じ種類の連言と含意を使います。
[->] は [forall] の(* suhara: 全称量化の変数に *) 依存しない特別な場合なので、
第4のルールでは [intro] で含意も扱うことに注意してください。
(*
In the fifth rule, when we find a [forall] fact [H] with a premise matching one of our hypotheses, we add the appropriate instantiation of [H]'s conclusion, if we have not already added it.
*)
第5のルールでは、私たちが仮説のひとつにマッチする前提で [forall] (を含む)事実 [H] を見つけたら、
まだ追加していなければ、[H] の結論を適切に具体化(instantiation)したものを追加します。
(*
We can check that [completer] is working properly, with a theorem that introduces a spurious variable whose didactic purpose we will come to shortly. *)
偽作(spurious)の変数を導入する、説明上の目的(didactic purpose)の定理を用いて、
すぐに、[completer] が正しく働いていることを確認することができます。
*)
Section firstorder.
Variable A : Set.
Variables P Q R S : A -> Prop.
Hypothesis H1 : forall x, P x -> Q x /\ R x.
Hypothesis H2 : forall x, R x -> S x.
Theorem fo : forall (y x : A), P x -> S x.
(* begin thide *)
completer.
(** [[
y : A
x : A
H : P x
H0 : Q x
H3 : R x
H4 : S x
============================
S x
]]
*)
assumption.
Qed.
(* end thide *)
End firstorder.
(**
(* We narrowly avoided a subtle pitfall in our definition of [completer]. Let us try another definition that even seems preferable to the original, to the untrained eye. (We change the second [match] case a bit to make the tactic smart enough to handle some subtleties of Ltac behavior that had not been exercised previously.) *)
かろうじて [completer] の定義における微妙な落とし穴を避けていました。
慣れていない目には、オリジナルよりも魅力的に見える別の定義を試してみましょう。
（2番目の [match] の場合を少し変更して、
これまでに行使されていなかったLtacの動作の微妙な部分を処理するのに
十分スマートなタクティクにしました）。
*)
(* begin thide *)
Ltac completer' :=
repeat match goal with
| [ |- _ /\ _ ] => constructor
| [ H : ?P /\ ?Q |- _ ] => destruct H;
(* suhara: ここからの部分は影響しない。 *)
repeat match goal with
| [ H' : P /\ Q |- _ ] => clear H'
end
(* suhara: ここまで。 *)
| [ H : ?P -> _, H' : ?P |- _ ] => specialize (H H') (* ！！！ *)
(* suhara: ↑は、H2 : forall x, R x -> S x. や H1 .. にもマッチしてしまう。 *)
(* specialize (H1 y) や specialize (H2 y) が実行されてしまう。 *)
(* x より y のほうが、前にあるのもミソである。 *)
| [ |- forall x, _ ] => intro
| [ H : forall x, ?P x -> _, H' : ?P ?X |- _ ] => extend (H X H')
end.
(* end thide *)
(**
(* The only other difference is in the modus ponens rule, where we have replaced an unused uni
fication variable [?Q] with a wildcard. Let us try our example again with this version: *)
他の唯一の違いは、未使用のユニフィケーション変数 [?Q] をワイルドカードに置き換えた三段論法
(modus ponens) のルールにあります。 このバージョンで再び例を試してみましょう：
*)
Section firstorder'.
Variable A : Set.
Variables P Q R S : A -> Prop.
Hypothesis H1 : forall x, P x -> Q x /\ R x.
Hypothesis H2 : forall x, R x -> S x.
Theorem fo' : forall (y x : A), P x -> S x.
(* suhara: completer' とおなじことを起こす例。
intros y x H.
specialize (@H1 y).
specialize (@H2 y).
Restart.
*)
completer'.
(** [[
y : A
H1 : P y -> Q y /\ R y
H2 : R y -> S y
x : A
H : P x
============================
S x
]]
(*
The quantified theorems have been instantiated with [y] instead of [x], reducing a provable goal to one that is unprovable. Our code in the last [match] case for [completer'] is careful only to instantiate quantifiers along with suitable hypotheses, so why were incorrect choices made?
*)
証明できていたゴールを証明できないものに変形(reducing)することで、
量化された定理は、[x]ではなく[y]で具体化されてしまいます。
[completer'] のための最後の [match] の条件は、
適切な仮説とともに量化子を具体化するだけに注意深くしています。
なぜ間違った選択が行われたのですか？
*)
Abort.
(* end thide *)
End firstorder'.
(**
(* A few examples should illustrate the issue. Here we see a [match]-based proof that works fine: *)
いくつかの例が問題を説明しているはずです。ここでは、
[match]にもとづく証明がうまくいくのを見ています：
*)
Theorem t1 : forall x : nat, x = x.
match goal with
| [ |- forall x, _ ] => trivial
end.
(* begin thide *)
Qed.
(* end thide *)
(** This one fails. *)
(* begin thide *)
Theorem t1' : forall x : nat, x = x.
(** %\vspace{-.25in}%[[
match goal with
| [ |- forall x, ?P ] => trivial
end.
]]
<<
User error: No matching clauses for match goal
>>
*)
Abort. (* suhara: Coq 8.5では解けてしまう。 *)
(* end thide *)
(**
(* The problem is that unification variables may not contain locally bound variables. In this case, [?P] would need to be bound to [x = x], which contains the local quantified variable [x]. By using a wildcard in the earlier version, we avoided this restriction. To understand why this restriction affects the behavior of the [completer] tactic, recall that, in Coq, implication is shorthand for degenerate universal quantification where the quantified variable is not used. Nonetheless, in an Ltac pattern, Coq is happy to match a wildcard implication against a universal quantification.
*)
問題は、ユニフィケーション変数にローカルに束縛された変数が含まれないことです。
(* suhara: forall x, Q や fun x => F の x のこと。P は、
xが含まれている Q や F とマッチしないが、ワイルドカードならマッチする。 *)
この場合、[?P] はローカルな量化変数 [x] を含む [x = x] に束縛される必要があります。
以前のバージョンでワイルドカードを使用することで、この制限は回避されました。
なぜこの制限が [completer] タクティクの振る舞いに影響を与えるのかを理解するために、
Coqでは、含意が縮退(degenerate)した全称量化の略記であることを思い出してください。
それにもかかわらず、Ltacパターンでは、
Coqはワイルドカードの含意と全称量化のマッチに満足してしまいます。
(*
The Coq 8.2 release includes a special pattern form for a unification variable with an explicit set of free variables. That unification variable is then bound to a function from the free variables to the "real" value. In Coq 8.1 and earlier, there is no such workaround. We will see an example of this fancier binding form in Section 15.5.
*)
Coq 8.2リリースには、明示的な自由変数の集合を持つユニフィケーション変数用の
特別なパターン形式が含まれています。
そのユニフィケーション変数は、
自由変数から「実」値への関数に束縛されます。
Coq 8.1以前では、このような回避策はありません。
15.5節でこの手の込んだバインディングフォームの例を見ていきます。
(*
No matter which Coq version you use, it is important to be aware of this restriction. As we have alluded to, the restriction is the culprit behind the surprising behavior of [completer']. We unintentionally match quantified facts with the modus ponens rule, circumventing the check that a suitably matching hypothesis is available and leading to different behavior, where wrong quantifier instantiations are chosen. Our earlier [completer] tactic uses a modus ponens rule that matches the implication conclusion with a variable, which blocks matching against non-trivial universal quantifiers.
*)
どのCoqバージョンを使用していても、この制限に注意することが重要です。
すでに示唆したように、その制限は [completer'] の驚くべき振る舞いの背後にある原因です。
(* suhara: match の
「| [ H : ?P -> _, H' : ?P |- _ ] => specialize (H H') 」
の H が、
「H : forall p : P, _ 」 と解釈されて、
「H2 : forall x, R x -> S x」 とマッチしてしまう。ワイルドカードなので変数xをふくんでよい。
そのため、specialize (H1 y) が実行されてしまう。
y のほうが x より前にあるのもミソである。
*)
私たちは間違って量化された事実を三段論法と突き合わせ、
適切に一致する仮説が利用可能であり、
誤った量化子の具体化が選択された異なる行動につながるというチェックを回避します。
私たちの初期の [completer] タクティクでは、
含意の結論と変数を組み合わせた三段論法を使用しています。
(*
Actually, the behavior demonstrated here applies to Coq version 8.4, but not 8.4pl1. The latter version will allow regular Ltac pattern variables to match terms that contain locally bound variables, but a tactic failure occurs if that variable is later used as a Gallina term. *)
実際、ここで示した動作はCoqバージョン8.4に適用されますが、8.4pl1には適用されません。
後者のバージョンでは、通常のLtacパターン変数がローカルに束縛された変数を含む項に
一致することができますが、
その変数が後にGallina項として使用されると、タクティクの失敗が発生します。
*)
(*
(** * Functional Programming in Ltac *)
*)
(** * Ltac による関数プログラミング *)
(* EX: Write a list length function in Ltac. *)
(**
(* Ltac supports quite convenient functional programming, with a Lisp-with-syntax kind of flavor. However, there are a few syntactic conventions involved in getting programs to be accepted. The Ltac syntax is optimized for tactic-writing, so one has to deal with some inconveniences in writing more standard functional programs.
*)
Ltacは、構文付きLisp(Lisp-with-syntax)風の非常に便利な関数型プログラミングをサポートしています。
受け入れてもらうための、プログラムに関係するいくつかの構文上の慣習があります。
Ltacの構文はタクティクの記述のために最適化されているので、
より標準的な関数プログラムを書く際にいくつかの不都合を扱わなければなりません。
(*
To illustrate, let us try to write a simple list length function. We start out writing it just as in Gallina, simply replacing [Fixpoint] (and its annotations) with [Ltac].
*)
説明のために、簡単なリストの長さを求める関数を記述しましょう。
あたかもGallinaのように、[Fixtpoint]（とその注釈(annotation)）
を[Ltac]に置き換えて書き始めます。
[[
Ltac length ls :=
match ls with
| nil => O
| _ :: ls' => S (length ls')
end.
]]
<<
Error: The reference ls' was not found in the current environment
>>
(*
At this point, we hopefully remember that pattern variable names must be prefixed by question marks in Ltac.
*)
この時点で、Ltacでは、
パターン変数の名前の先頭に疑問符を付ける必要があることを覚えておいてください。
[[
Ltac length ls :=
match ls with
| nil => O
| _ :: ?ls' => S (length ls')
end.
]]
<<
Error: The reference S was not found in the current environment
>>
(*
The problem is that Ltac treats the expression [S (length ls')] as an invocation of a tactic [S] with argument [length ls']. We need to use a special annotation to "escape into" the Gallina parsing nonterminal.%\index{tactics!constr}% *)
問題は、Ltacが式 [S (length ls')] を引数 [length ls'] を持つタクティク [S] の呼び出しとして
扱うことです。
Gallinaの非終端記号の構文解析を「エスケープ」するために特別なアノテーションを
使用する必要があります。 %\index{tactics!constr}%
*)
(* begin thide *)
(* begin hide *)
Definition red_herring := O.
(* end hide *)
Ltac length ls :=
match ls with
| nil => O
| _ :: ?ls' => constr:(S (length ls'))
end.
(**
(* This definition is accepted. It can be a little awkward to test Ltac definitions like this one. Here is one method. *)
この定義は受け入れられます。
このようなLtacの定義をテストするのはちょっと厄介です。
ひとつの方法があります。
*)
Goal False.
let n := length (1 :: 2 :: 3 :: nil) in
pose n.
(** [[
n := S (length (2 :: 3 :: nil)) : nat
============================
False
]]
(*
We use the %\index{tactics!pose}%[pose] tactic, which extends the proof context with a new variable that is set equal to a particular term. We could also have used [idtac n] in place of [pose n], which would have printed the result without changing the context.
*)
特定の項に、等号でセットされた(set equal to)、新しい変数でもって、証明のコンテキストを拡張する
%\index{tactics!pose}%[pose] タクティクを使用します。
[pose n] の代わりに [idtac n] を使用することもできました。
これは、コンテキストを変更せずに結果を出力します。
(*
The value of [n] only has the length calculation unrolled one step. What has happened here is that, by escaping into the [constr] nonterminal, we referred to the [length] function of Gallina, rather than the [length] Ltac function that we are defining. *)
[n]の値は、長さの計算の1ステップだけ展開されます。
ここで起こったことは、[constr] 非終端記号にエスケープすることによって、
私たちが定義している Ltac関数 [length] は、Gallinaの関数 [length] を参照したことです。
*)
Abort.
Reset length.
(* begin hide *)
Reset red_herring.
(* end hide *)
(**
(* The thing to remember is that Gallina terms built by tactics must be bound explicitly via [let] or a similar technique, rather than inserting Ltac calls directly in other Gallina terms. *)
覚えておくべきことは、タクティクによって作られた Gallina項は、
Ltac 呼び出しを他の Gallina項 に直接挿入するのではなく、
[let] または同様の手法を介して明示的に束縛する必要があるということです。
*)
(* begin hide *)
Definition red_herring := O.
(* end hide *)
Ltac length ls :=
match ls with
| nil => O
| _ :: ?ls' =>
let ls'' := length ls' in
constr:(S ls'')
end.
Goal False.
let n := length (1 :: 2 :: 3 :: nil) in
pose n.
(** [[
n := 3 : nat
============================
False
]]
*)
Abort.
(* end thide *)
(* EX: Write a list map function in Ltac. *)
(* begin hide *)
(* begin thide *)
Definition mapp := (map, list).
(* end thide *)
(* end hide *)
(**
(* We can also use anonymous function expressions and local function definitions in Ltac, as this example of a standard list [map] function shows. *)
標準のリストの [map] 関数のこの例が示すように、
Ltacで無名関数の式とローカルな関数定義を使用することもできます。
*)
(* begin thide *)
Ltac map T f :=
let rec map' ls :=
match ls with
| nil => constr:(@nil T)
| ?x :: ?ls' =>
let x' := f x in
let ls'' := map' ls' in
constr:(x' :: ls'')
end in
map'.
(**
(* Ltac functions can have no implicit arguments. It may seem surprising that we need to pass [T], the carried type of the output list, explicitly. We cannot just use [type of f], because [f] is an Ltac term, not a Gallina term, and Ltac programs are dynamically typed. The function [f] could use very syntactic methods to decide to return differently typed terms for different inputs. We also could not replace [constr:(@nil T)] with [constr:nil], because we have no strongly typed context to use to infer the parameter to [nil]. Luckily, we do have sufficient context within [constr:(x' :: ls'')].
Sometimes we need to employ the opposite direction of "nonterminal escape," when we want to pass a complicated tactic expression as an argument to another tactic, as we might want to do in invoking %\coqdocvar{%#<tt>#map#</tt>#%}%. *)
Ltac関数は暗黙の引数を持つことができません。
出力リストの要素の型(carried type of the output list)である[T]を
明示的に渡す必要があることは驚くようです。
[f] は Gallinaの項ではなくLtacの項であり、
Ltacプログラムは動的に型付けされているので、[type of f] を使うことはできません。
関数 [f] は、非常に構文的な方法を使用して、
異なる入力に対して異なる型の項を返すことを決定することができます。
[constr:(@nil T)] を [constr:nil] に置き換えることもできませんでした。
これは、パラメータを [nil] に推論するために使用する強く型付けされたコンテキストがないためです。
幸いにも、[constr:(x' :: ls'')] の中には十分なコンテキストを持っています。
複雑なタクティクの表現を別のタクティクに引数として渡したいときには、
%\coqdocvar{%#<tt>#map#</tt>#%}% を呼び出す際にしたように、
「非終端のエスケープ」の反対の方向を採用する必要がある場合があります。
*)
Goal False.
let ls := map (nat * nat)%type ltac:(fun x => constr:((x, x))) (1 :: 2 :: 3 :: nil) in
pose ls.
(** [[
l := (1, 1) :: (2, 2) :: (3, 3) :: nil : list (nat * nat)
============================
False
]]
*)
Abort.
(* end thide *)
(**
(* Each position within an Ltac script has a default applicable non-terminal, where [constr] and [ltac] are the main options worth thinking about, standing respectively for terms of Gallina and Ltac. The explicit colon notation can always be used to override the default non-terminal choice, though code being parsed as Gallina can no longer use such overrides. Within the [ltac] non-terminal, top-level function applications are treated as applications in Ltac, not Gallina; but the _arguments_ to such functions are parsed with [constr] by default. This choice may seem strange, until we realize that we have been relying on it all along in all the proof scripts we write! For instance, the [apply] tactic is an Ltac function, and it is natural to interpret its argument as a term of Gallina, not Ltac. We use an [ltac] prefix to parse Ltac function arguments as Ltac terms themselves, as in the call to %\coqdocvar{%#<tt>#map#</tt>#%}% above. For some simple cases, Ltac terms may be passed without an extra prefix. For instance, an identifier that has an Ltac meaning but no Gallina meaning will be interpreted in Ltac automatically.
*)
Ltacスクリプトの中の各位置には、
既定の適用可能な非終端記号があります。
ここで、[constr]と[ltac]は、
GallinaとLtacの条件をそれぞれ念頭に置く価値のある主要なオプションです。
明示的なコロン表記は、既定の非終端選択を無効にするためにいつでも使用することができますが、
Gallinaとして解析されるコードではこのような上書きは使用できなくなります。
[ltac]非終端の関数アプリケーションは、GallinaではなくLtacのアプリケーションとして扱われます。
そのような関数への ＿引数＿ はデフォルトで [constr] で解析されます。
この選択は、私たちが書いているすべての証明スクリプトにすべて頼っていることがわかるまで、
奇妙に見えるかもしれません！
例えば、[apply] タクティクはLtac関数であり、
その引数をLtacではなくGallinaの項として解釈するのは当然です。
上記の %\coqdocvar{%#<tt>#map#</tt>#%}% の呼び出しのように、
[ltac]接頭辞を使用してLtac関数の引数をLtac項として解析します。
いくつかの単純なケースでは、Ltac項は余分なプレフィックスなしで渡されることがあります。
例えば、Ltacの意味を持ち、Gallinaの意味を持たない識別子は自動的にLtacで解釈されます。
(*
One other gotcha shows up when we want to debug our Ltac functional programs. We might expect the following code to work, to give us a version of %\coqdocvar{%#<tt>#length#</tt>#%}% that prints a debug trace of the arguments it is called with. *)
Ltacの機能プログラムをデバッグしたいときには、もうひとつの問題があります。
呼び出された引数のデバッグ・トレースを出力する
%\coqdocvar{%#<tt>#length#</tt>#%}%
バージョンを提供するには、次のコードが必要です。
*)
(* begin thide *)
Reset length.
(* begin hide *)
Reset red_herring.
(* end hide *)
(* begin hide *)
Definition red_herring := O.
(* end hide *)
Ltac length ls :=
idtac ls;
match ls with
| nil => O
| _ :: ?ls' =>
let ls'' := length ls' in
constr:(S ls'')
end.
(**
(* Coq accepts the tactic definition, but the code is fatally flawed and will always lead to dynamic type errors. *)
Coqはタクティクの定義を受け入れますが、コードには致命的な欠陥があり、
常に動的なタイプのエラーにつながります。
*)
Goal False.
(** %\vspace{-.15in}%[[
let n := length (1 :: 2 :: 3 :: nil) in
pose n.
]]
<<
Error: variable n should be bound to a term.
>> *)
Abort.
(**
(* What is going wrong here? The answer has to do with the dual status of Ltac as both a purely functional and an imperative programming language. The basic programming language is purely functional, but tactic scripts are one "datatype" that can be returned by such programs, and Coq will run such a script using an imperative semantics that mutates proof states. Readers familiar with %\index{monad}\index{Haskell}%monadic programming in Haskell%~\cite{Monads,IO}% may recognize a similarity. Haskell programs with side effects can be thought of as pure programs that return _the code of programs in an imperative language_, where some out-of-band mechanism takes responsibility for running these derived programs. In this way, Haskell remains pure, while supporting usual input-output side effects and more. Ltac uses the same basic mechanism, but in a dynamically typed setting. Here the embedded imperative language includes all the tactics we have been applying so far.
*)
ここで何がうまくいかないのでしょうか？
答えは、Ltacの、純粋に関数プログラミング言語と命令的プログラミング言語の両方としての
二重状態 (dual status) と関係しています。
基本的なプログラミング言語は純粋に関数的ですが、
タクティクスクリプトはそのようなプログラムによって返される「データ型」のひとつで、
Coqは証明状態を変更する命令的なセマンティクスを使ってそのようなスクリプトを実行します。
%~\cite{Monads,IO}% Haskell の
%\index{monad}\index{Haskell}% モナド・プログラミング(monadic programming)に
精通している読者は、類似点を認識しているかもしれません。
副作用を伴うHaskellプログラムは、
＿命令型言語におけるプログラムのコード＿
(the code of programs in an imperative language) を
返す純粋なプログラムと考えることができます。
一部の帯域外(out-of-band)なメカニズムは、
これらの派生プログラムを実行する責任を負います。
このようにして、Haskellは純粋なままで、通常の入出力の副作用などをサポートします。
Ltacは同じ基本メカニズムを使用しますが、動的に型付けされます。
ここで埋め込まれた命令的言語には、これまで適用されてきたすべてのタクティクが含まれます。
(*
Even basic [idtac] is an embedded imperative program, so we may not automatically mix it with purely functional code. In fact, a semicolon operator alone marks a span of Ltac code as an embedded tactic script. This makes some amount of sense, since pure functional languages have no need for sequencing: since they lack side effects, there is no reason to run an expression and then just throw away its value and move on to another expression.
*)
基本的な [idtac] も組み込みの命令型プログラムなので、
純粋に機能的なコードと自動的には混合しないかもしれません。
実際には、セミコロン演算子だけでLtacコードのスパンを
組み込みのタクティクのスクリプトとしてマークしています。
純粋な関数型言語では順序付けの必要がないので、
副作用がないため、式を実行してからその値を捨て、別の式に移る理由はありません。
(*
An alternate explanation that avoids an analogy to Haskell monads (admittedly a tricky concept in its own right) is: An Ltac tactic program returns a function that, when run later, will perform the desired proof modification. These functions are distinct from other types of data, like numbers or Gallina terms. The prior, correctly working version of [length] computed solely with Gallina terms, but the new one is implicitly returning a tactic function, as indicated by the use of [idtac] and semicolon. However, the new version's recursive call to [length] is structured to expect a Gallina term, not a tactic function, as output. As a result, we have a basic dynamic type error, perhaps obscured by the involvement of first-class tactic scripts.
*)
Haskell のモナド（それ自体は巧妙な考え方であると思われますが）に対する類推を
避けるための代替的な説明は次のとおりです。
Ltacのタクティクのプログラムは、
後で実行されるときに望ましい証明の変形(proof modification)を実行する関数を返します。
これらの関数は、他のデータ型や数やGallina項とは異なります。
Gallina項でのみ計算された [length] の以前の正しく動作していたバージョンですが、
[idtac] とセミコロンの使用で示されるように、新しい関数は暗黙的に関数を返しています。
しかし、新しいバージョンの [length] の再帰的呼び出しは、
出力としてGallina項をタクティクの関数ではないと予想するように構成されています。
その結果、基本的な動的な型エラーが発生します。
おそらくファーストクラスのタクティクのスクリプトが関与しています。
(*
The solution is like in Haskell: we must "monadify" our pure program to give it access to side effects. The trouble is that the embedded tactic language has no [return] construct. Proof scripts are about proving theorems, not calculating results. We can apply a somewhat awkward workaround that requires translating our program into%\index{continuation-passing style}% _continuation-passing style_ %\cite{continuations}%, a program structuring idea popular in functional programming. *)
結果はHaskellに似ています。
純粋なプログラムを「モナド化」して、副作用にアクセスできるようにする必要があります。
問題は組み込まれたタクティクの言語には [return] の構造がないことです。
証明スクリプトは、結果を計算するのではなく、定理を証明することに関するものです。
プログラムを
%\index{continuation-passing style}%
＿継承渡しスタイル＿ (continuation-passing style) %\cite{continuations}%
に変換する必要があるやや難しい回避策を適用することができます。
*)
Reset length.
(* begin hide *)
Reset red_herring.
(* end hide *)
Ltac length ls k :=
idtac ls;
match ls with
| nil => k O
| _ :: ?ls' => length ls' ltac:(fun n => k (S n))
end.
(* end thide *)
(**
(* The new [length] takes a new input: a _continuation_ [k], which is a function to be called to continue whatever proving process we were in the middle of when we called %\coqdocvar{%#<tt>#length#</tt>#%}%. The argument passed to [k] may be thought of as the return value of %\coqdocvar{%#<tt>#length#</tt>#%}%. *)
新しい [length] は、新しい入力を受け取ります: ＿継続＿ (continuation) [k] は、
%\coqdocvar{%#<tt>#length#</tt>#%}% を呼び出した途中でどのようなプロセスがあったとしても
継続するために呼び出される関数です。
[k] に渡される引数は、%\coqdocvar{%#<tt>#length#</tt>#%}% の戻り値と考えることができます。
*)
(* begin thide *)
Goal False.
length (1 :: 2 :: 3 :: nil) ltac:(fun n => pose n).
(** [[
(1 :: 2 :: 3 :: nil)
(2 :: 3 :: nil)
(3 :: nil)
nil
]]
*)
Abort.
(* end thide *)
(**
(* We see exactly the trace of function arguments that we expected initially, and an examination of the proof state afterward would show that variable [n] has been added with value [3].
*)
私たちは最初に期待した関数引数のトレースを正確に見て、
その後の証明に状態を調べると、変数[n]に値[3]が追加され
ていることがわかります。
(*
Considering the comparison with Haskell's IO monad, there is an important subtlety that deserves to be mentioned. A Haskell IO computation represents (theoretically speaking, at least) a transformer from one state of the real world to another, plus a pure value to return. Some of the state can be very specific to the program, as in the case of heap-allocated mutable references, but some can be along the lines of the favorite example "launch missile," where the program has a side effect on the real world that is not possible to undo.
*)
HaskellのIOモナドとの比較を考えると、言及する価値のある微妙なことがあります。
HaskellのI/O計算は、実世界のある状態から別の状態への変換器と、返す純粋な値を
（理論的に言えば、少なくとも）表現します。
状態の一部は、ヒープ割り当ての変更可能な参照の場合のように、
プログラム固有のものもありますが、
プログラムが、現実世界に元に戻すことができない副作用を及ぼす
お気に入りの例「ミサイル発射」の線に沿っているものもあります。
(*
In contrast, Ltac scripts can be thought of as controlling just two simple kinds of mutable state. First, there is the current sequence of proof subgoals. Second, there is a partial assignment of discovered values to unification variables introduced by proof search (for instance, by [eauto], as we saw in the previous chapter). Crucially, _every mutation of this state can be undone_ during backtracking introduced by [match], [auto], and other built-in Ltac constructs. Ltac proof scripts have state, but it is purely local, and all changes to it are reversible, which is a very useful semantics for proof search. *)
対照的に、Ltacのスクリプトは、単に2つの単純な種類の可変状態を制御するものと考えることができます。
第1に、証明のサブゴールの現在のシーケンスが存在します。
第2に、前の章で見たように、証明検索によって導入されたユニフィケーション変数に発見された値を部分的に
割り当てます（たとえば、[eauto]）。
重要なことは、[match]、[auto]、および、その他のLtacを構成する組み込みのものによって導かれた
バックトラッキングの間には、
＿この状態のあらゆる変異を元に戻すことができる＿ ということです。
Ltac証明スクリプトには状態がありますが、
それは純粋にローカルなものであり、すべての変更は可逆的です。
これは証明検索のための非常に便利なセマンティクスです。
*)
(*
(** * Recursive Proof Search *)
*)
(** * 再帰的な証明探索 *)
(**
(* Deciding how to instantiate quantifiers is one of the hardest parts of automated first-order theorem proving. For a given problem, we can consider all possible bounded-length sequences of quantifier instantiations, applying only propositional reasoning at the end. This is probably a bad idea for almost all goals, but it makes for a nice example of recursive proof search procedures in Ltac.
*)
量化子をどのように具体化するかの決定は、
自動化された一階の定理の証明の最も難しい部分のひとつです。
与えられた問題によっては、最終的に命題の推論だけを適用することで、
量化子のインスタンス可能な全てからなる有限長のシーケンスを考えることができます。
これは、ほぼすべてのゴールに対して悪い考えですが、
Ltacの再帰的な証明探索の手順の素晴らしい例になります。
(*
We can consider the maximum "dependency chain" length for a first-order proof. We define the chain length for a hypothesis to be 0, and the chain length for an instantiation of a quantified fact to be one greater than the length for that fact. The tactic [inster n] is meant to try all possible proofs with chain length at most [n]. *)
一階の証明のために最大の「依存鎖(dependency chain)」の長さを考慮することができます。
仮説の鎖の長を0とし、
量化された事実を具体化したものの鎖長をその事実の長さより、1だけ大きいものと定義します。
タクティク [inster n] は、鎖の長さの最大 [n] で、可能なすべての証明を試すことを意図しています。
*)
(* begin thide *)
Ltac inster n :=
intuition;
match n with
| S ?n' =>
match goal with
| [ H : forall x : ?T, _, y : ?T |- _ ] => generalize (H y); inster n'
end
end.
(* end thide *)
(**
(* The tactic begins by applying propositional simplification. Next, it checks if any chain length remains, failing if not. Otherwise, it tries all possible ways of instantiating quantified hypotheses with properly typed local variables. It is critical to realize that, if the recursive call [inster n'] fails, then the [match goal] just seeks out another way of unifying its pattern against proof state. Thus, this small amount of code provides an elegant demonstration of how backtracking [match] enables exhaustive search.
*)
このタクティクは、命題の単純化を適用することから始まります。
次に、鎖長が残っているかどうかをチェックし、そうでない場合は失敗します。
それ以外の場合は、適切に型付けされたローカル変数を使用して
量化された仮説を具体化するすべての可能な方法を試行します。
再帰呼び出し [inster n'] が失敗した場合、[match goal] は、
そのパターンを証明の状態とユニファイする別の方法を探していることに気付くことが重要です。
したがって、この少量のコードは、バックトラック [mactch] がどのように
徹底的な検索を可能にするかについてのエレガントなデモンストレーションを提供します。
(*
We can verify the efficacy of [inster] with two short examples. The built-in [firstorder] tactic (with no extra arguments) is able to prove the first but not the second. *)
ふたつの短い例で [inster] の有効性を検証することができます。
組み込みの [firstorder] タクティク（余計な引数なし）は、
最初のものを証明することができますが、2番目のものは証明できません。
(* suhara: Goal : Q (f y) が残る。 *)
*)
Section test_inster.
Variable A : Set.
Variables P Q : A -> Prop.
Variable f : A -> A.
Variable g : A -> A -> A.
Hypothesis H1 : forall x y, P (g x y) -> Q (f x).
Theorem test_inster : forall x, P (g x x) -> Q (f x).
inster 2.
Qed.
Hypothesis H3 : forall u v, P u /\ P v /\ u <> v -> P (g u v).
Hypothesis H4 : forall u, Q (f u) -> P u /\ P (f u).
Theorem test_inster2 : forall x y, x <> y -> P x -> Q (f y) -> Q (f x).
inster 3.
Qed.
End test_inster.
(**
(* The style employed in the definition of [inster] can seem very counterintuitive to functional programmers. Usually, functional programs accumulate state changes in explicit arguments to recursive functions. In Ltac, the state of the current subgoal is always implicit. Nonetheless, recalling the discussion at the end of the last section, in contrast to general imperative programming, it is easy to undo any changes to this state, and indeed such "undoing" happens automatically at failures within [match]es. In this way, Ltac programming is similar to programming in Haskell with a stateful failure monad that supports a composition operator along the lines of the [first] tactical.
*)
[inster] の定義に採用されているスタイルは、関数的なプログラマーには直観に反するように見えます。
通常、関数プログラムは、明示的な状態変化を再帰関数にの引数に蓄積します。
Ltacでは、現在のサブゴールの状態は常に暗黙的です。
それにもかかわらず、一般的な命令型プログラミングとは対照的に、
この前の節最後の議論を思い出すなら、この状態への変更を元に戻すのは簡単です。
実際、このような「undo」は、[match] 内の失敗で自動的に起こります。
このように、Ltacプログラミングは、[first] タクティカルの行に沿って合成演算子(composition operator)
をサポートするステートフルな failure モナドを持つHaskellのプログラミングと似ています。
(*
Functional programming purists may react indignantly to the suggestion of programming this way. Nonetheless, as with other kinds of "monadic programming," many problems are much simpler to solve with Ltac than they would be with explicit, pure proof manipulation in ML or Haskell. To demonstrate, we will write a basic simplification procedure for logical implications.
*)
関数プログラミングの純粋主義者は、
このようなプログラミングの提案に対して憤慨して反応するかもしれません。
それにもかかわらず、他の種類の「モナド・プログラミング」と同様に、
多くの問題が
MLやHaskellでの明示的で純粋な証明操作よりも、
Ltacで解決するのがはるかに簡単です。
実証するために、論理的含意いのための基本的な簡略化手順を書くことにします。
(*
This procedure is inspired by one for separation logic%~\cite{separation}%, where conjuncts in formulas are thought of as "resources," such that we lose no completeness by "crossing out" equal conjuncts on the two sides of an implication. This process is complicated by the fact that, for reasons of modularity, our formulas can have arbitrary nested tree structure (branching at conjunctions) and may include existential quantifiers. It is helpful for the matching process to "go under" quantifiers and in fact decide how to instantiate existential quantifiers in the conclusion.
*)
この手順は、分離論理 %~\cite{separation}% に影響を受けています。
ここでは、式のなかの連言(conjuncts in formulas)は「リソース」と見なされ、
含意の両辺で等しい連言を「交差させる」ことによって完全性を失うことはありません。
このプロセスは、モジュール性の理由から、式が任意の入れ子ツリー構造（連言での分岐）を持つことができ、
存在量化子を含むことができるという事実によって複雑になります。
これは、マッチングプロセスが量化子を「下にいく」ことに役立ち、
実際に、存在量化子をどのように具体化するかを決定するのに役立ちます。
(*
To distinguish the implications that our tactic handles from the implications that will show up as "plumbing" in various lemmas, we define a wrapper definition, a notation, and a tactic. *)
我々のタクティクが扱う含意を
さまざまな補題で「配管」として現れる含意から区別するために、
ラッパー定義、ノーテーション、およびタクティクを定義します。
*)
Definition imp (P1 P2 : Prop) := P1 -> P2.
Infix "-->" := imp (no associativity, at level 95).
Ltac imp := unfold imp; firstorder.
(**
(* These lemmas about [imp] will be useful in the tactic that we will write. *)
[imp]に関するこれらの補題は、我々が書くタクティクに役立つでしょう。
*)
Theorem and_True_prem : forall P Q,
(P /\ True --> Q)
-> (P --> Q).
imp.
Qed.
Theorem and_True_conc : forall P Q,
(P --> Q /\ True)
-> (P --> Q).
imp.
Qed.
Theorem pick_prem1 : forall P Q R S,
(P /\ (Q /\ R) --> S)
-> ((P /\ Q) /\ R --> S).
imp.
Qed.
Theorem pick_prem2 : forall P Q R S,
(Q /\ (P /\ R) --> S)
-> ((P /\ Q) /\ R --> S).
imp.
Qed.
Theorem comm_prem : forall P Q R,
(P /\ Q --> R)
-> (Q /\ P --> R).
imp.
Qed.
Theorem pick_conc1 : forall P Q R S,
(S --> P /\ (Q /\ R))
-> (S --> (P /\ Q) /\ R).
imp.
Qed.
Theorem pick_conc2 : forall P Q R S,
(S --> Q /\ (P /\ R))
-> (S --> (P /\ Q) /\ R).
imp.
Qed.
Theorem comm_conc : forall P Q R,
(R --> P /\ Q)
-> (R --> Q /\ P).
imp.
Qed.
(**
(* The first order of business in crafting our [matcher] tactic will be auxiliary support for searching through formula trees. The [search_prem] tactic implements running its tactic argument [tac] on every subformula of an [imp] premise. As it traverses a tree, [search_prem] applies some of the above lemmas to rewrite the goal to bring different subformulas to the head of the goal. That is, for every subformula [P] of the implication premise, we want [P] to "have a turn," where the premise is rearranged into the form [P /\ Q] for some [Q]. The tactic [tac] should expect to see a goal in this form and focus its attention on the first conjunct of the premise. *)
私たちの [matcher] タクティクを作る上での最初の作業(the first order of business)は、
式の木を検索するための補助的なサポートになります。
[search_prem] タクティクは
[imp] の前提のすべての部分式(subformula)で、引数[tac]を実行するように実装されます。
木を走査するとき、[search_prem] は上記の補題のいくつかを適用して、
異なる部分式(subformula)をゴールの頭部にもっていくことで、
ゴールを書き換えます。
すなわち、
その前提が、いくつかの[Q]に対して、[P /\ Q]のかたちに再配置されるところで、
含意の前提のそれぞれの部分式 [P] に対して、[P] を 「have a turn」しようとします。
(* suhara: 最後のmatchのひとつめのcaseのこと。Qは「_」。 *)
タクティク [tac] はこのかたちでゴールを見ることを期待し、
前提の最初の連言に注意を集中するでしょう。
*)
Ltac search_prem tac :=
let rec search P :=
tac
|| (apply and_True_prem; tac)
|| match P with
| ?P1 /\ ?P2 =>
(apply pick_prem1; search P1)
|| (apply pick_prem2; search P2)
end
in match goal with
| [ |- ?P /\ _ --> _ ] => search P
| [ |- _ /\ ?P --> _ ] => apply comm_prem; search P
| [ |- _ --> _ ] => progress (tac || (apply and_True_prem; tac))
end.
(**
(* To understand how [search_prem] works, we turn first to the final [match]. If the premise begins with a conjunction, we call the [search] procedure on each of the conjuncts, or only the first conjunct, if that already yields a case where [tac] does not fail. The call [search P] expects and maintains the invariant that the premise is of the form [P /\ Q] for some [Q]. We pass [P] explicitly as a kind of decreasing induction measure, to avoid looping forever when [tac] always fails. The second [match] case calls a commutativity lemma to realize this invariant, before passing control to [search]. The final [match] case tries applying [tac] directly and then, if that fails, changes the form of the goal by adding an extraneous [True] conjunct and calls [tac] again. The %\index{tactics!progress}%[progress] tactical fails when its argument tactic succeeds without changing the current subgoal.
*)
[search_prem] がどのように機能するかを理解するために、
最初に、最後の [match] に進みます。
前提が連言で始まる場合は、各連言で[search]手続きを呼び出します。
[search P] の呼び出しは、ある [Q] のための前提が [P /\ Q] の形式であるという
不変性を期待し維持します。
[tac]が常に失敗したときに永久にループするのを避けるために、
一種の再帰の尺度として減少する、[P]を明示的に渡します。
2番目の[match]の場合は、制御を[search]に渡す前に、
この不変量を実現するために可換性(commutativity)の補題を呼び出します。
最終的な[match] の場合では [tac] を直接適用しようとしますが、
それが失敗すると、余分な[True]結合を追加してゴールの形を変え、
[tac]をもう一度呼び出します。
現在のサブゴールを変更せずに引数のタクティクが成功した場合、
%\index{tactics!progress}%[progress] タクティカルは失敗します。
(* suhara: progress は、証明が進まないことを検出したら失敗する。 *)
(*
The [search] function itself tries the same tricks as in the last case of the final [match], using the [||] operator as a shorthand for trying one tactic and then, if the first fails, trying another. Additionally, if neither works, it checks if [P] is a conjunction. If so, it calls itself recursively on each conjunct, first applying associativity/commutativity lemmas to maintain the goal-form invariant.
*)
[search] 関数自体は最後の [match] の最後の場合と同じトリックを試みますが、
[||]演算子を使ってひとつの手法を試してみます。
さらに、いずれも動作しない場合、[P]が連言であるかどうかをチェックします。
そうであれば、それはそれぞれの連言に対して再帰的に自分自身を呼び出し、
最初に 結合性(associativity) と 可換性の補題を適用してゴールの式の不変性を維持します。
(*
We will also want a dual function [search_conc], which does tree search through an [imp] conclusion. *)
また、[imp] の結論を通して木の検索を行う双対(dual)関数 [search_conc] が必要です。 *）
*)
Ltac search_conc tac :=
let rec search P :=
tac
|| (apply and_True_conc; tac)
|| match P with
| ?P1 /\ ?P2 =>
(apply pick_conc1; search P1)
|| (apply pick_conc2; search P2)
end
in match goal with
| [ |- _ --> ?P /\ _ ] => search P
| [ |- _ --> _ /\ ?P ] => apply comm_conc; search P
| [ |- _ --> _ ] => progress (tac || (apply and_True_conc; tac))
end.
(**
(* Now we can prove a number of lemmas that are suitable for application by our search tactics. A lemma that is meant to handle a premise should have the form [P /\ Q --> R] for some interesting [P], and a lemma that is meant to handle a conclusion should have the form [P --> Q /\ R] for some interesting [Q]. *)
ここでは、検索戦略によってアプリケーションに適したいくつかの補題を証明することができます。
前提を扱う補題は、[P]に関心をもった[P /\ Q -> R]の形式でなければならず、
結論を扱う補題は、[Q]に関心をもった[P --> Q /\ R]の形式でなければなりません。
*)
(* begin thide *)
Theorem False_prem : forall P Q,
False /\ P --> Q.
imp.
Qed.
Theorem True_conc : forall P Q : Prop,
(P --> Q)
-> (P --> True /\ Q).
imp.
Qed.
Theorem Match : forall P Q R : Prop,
(Q --> R)
-> (P /\ Q --> P /\ R).
imp.
Qed.
Theorem ex_prem : forall (T : Type) (P : T -> Prop) (Q R : Prop),
(forall x, P x /\ Q --> R)
-> (ex P /\ Q --> R).
imp.
Qed.
Theorem ex_conc : forall (T : Type) (P : T -> Prop) (Q R : Prop) x,
(Q --> P x /\ R)
-> (Q --> ex P /\ R).
imp.
Qed.
(**
(* We will also want a "base case" lemma for finishing proofs where cancellation has removed every constituent of the conclusion. *)
取り消しが結論のすべての構成要素を取り除いた場合の証明を完成させるための
「基本ケース」補題も必要です。
*)
Theorem imp_True : forall P,
P --> True.
imp.
Qed.
(**
(* Our final [matcher] tactic is now straightforward. First, we [intros] all variables into scope. Then we attempt simple premise simplifications, finishing the proof upon finding [False] and eliminating any existential quantifiers that we find. After that, we search through the conclusion. We remove [True] conjuncts, remove existential quantifiers by introducing unification variables for their bound variables, and search for matching premises to cancel. Finally, when no more progress is made, we see if the goal has become trivial and can be solved by [imp_True]. In each case, we use the tactic %\index{tactics!simple apply}%[simple apply] in place of [apply] to use a simpler, less expensive unification algorithm. *)
今や、最終的な[matcher]タクティクは簡単です。
最初に、すべての変数をスコープに [intro] し、
単純な前提の単純化を試み、
[False]を見つけたら証明を完成させ、
見つかった存在量化子を取り除きます。
その後、結論を検索します。
[True] の連言を取り除き、
ユニフィケーション変数を導入することによって、束縛変数のための存在量化子を取り除き、
一致する前提を探して取り除きます。
最後に、それ以上の進展がなければ、ゴールが自明かどうかをみて、
[imp_True] によって解くことができます。
それぞれの場合において、簡単にするために、[apply] の代わりに、
より安価なユニフィケーション・アルゴリズムである
%\index{tactics!simple apply}%[simple apply] タクティクを使います。
*)
Ltac matcher :=
intros;
repeat search_prem ltac:(simple apply False_prem || (simple apply ex_prem; intro));
repeat search_conc ltac:(simple apply True_conc || simple eapply ex_conc
|| search_prem ltac:(simple apply Match));
try simple apply imp_True.
(* end thide *)
(**
(* Our tactic succeeds at proving a simple example. *)
私たちの戦術は簡単な例を証明するのに成功します。
*)
Theorem t2 : forall P Q : Prop,
Q /\ (P /\ False) /\ P --> P /\ Q.
matcher.
Qed.
(**
(* In the generated proof, we find a trace of the workings of the search tactics. *)
生成された証明では、検索手法の動作の痕跡が見つかります。
*)
Print t2.
(** %\vspace{-.15in}% [[
t2 =
fun P Q : Prop =>
comm_prem (pick_prem1 (pick_prem2 (False_prem (P:=P /\ P /\ Q) (P /\ Q))))
: forall P Q : Prop, Q /\ (P /\ False) /\ P --> P /\ Q
]]
(*
%\smallskip{}%We can also see that [matcher] is well-suited for cases where some human intervention is needed after the automation finishes. *)
%\smallskip{}%
自動化が完了した後に人間の介入が必要な場合に[matcher]が適していることがわかります。
*)
Theorem t3 : forall P Q R : Prop,
P /\ Q --> Q /\ R /\ P.
matcher.
(** [[
============================
True --> R
]]
(*
Our tactic canceled those conjuncts that it was able to cancel, leaving a simplified subgoal for us, much as [intuition] does. *)
私たちのタクティクは、それが取り消すことができたそれらの連言を取り消し、
[intuition]と同じように、私たちのための簡略化されたサブゴールを残しました。 *）
*)
Abort.
(**
(* The [matcher] tactic even succeeds at guessing quantifier instantiations. It is the unification that occurs in uses of the [Match] lemma that does the real work here. *)
[matcher] タクティクは、量化の具体化を推測することにも成功します。
実際の作業を行う [Match] 補題の使用にあるのはユニフィケーションです。
*)
Theorem t4 : forall (P : nat -> Prop) Q, (exists x, P x /\ Q) --> Q /\ (exists x, P x).
matcher.
Qed.
Print t4.
(** %\vspace{-.15in}% [[
t4 =
fun (P : nat -> Prop) (Q : Prop) =>
and_True_prem
(ex_prem (P:=fun x : nat => P x /\ Q)
(fun x : nat =>
pick_prem2
(Match (P:=Q)
(and_True_conc
(ex_conc (fun x0 : nat => P x0) x
(Match (P:=P x) (imp_True (P:=True))))))))
: forall (P : nat -> Prop) (Q : Prop),
(exists x : nat, P x /\ Q) --> Q /\ (exists x : nat, P x)
]]
(*
This proof term is a mouthful, and we can be glad that we did not build it manually! *)
この証明の項はひと口で、手作業で構築していないのはうれしいことです！
*)
(*
(** * Creating Unification Variables *)
*)
(** * ユニフィケーション変数の生成 *)
(**
(* A final useful ingredient in tactic crafting is the ability to allocate new unification variables explicitly. Tactics like [eauto] introduce unification variables internally to support flexible proof search. While [eauto] and its relatives do _backward_ reasoning, we often want to do similar _forward_ reasoning, where unification variables can be useful for similar reasons.
*)
タクティクを作成するための最後の有用な要素は、新しいユニフィケーション変数を明示的に割り当てることです。
[eauto] のような戦術は、柔軟な証明検索をサポートするためにユニフィケーション変数を内部的に導入しています。
[eauto] とその親戚は ＿後ろ向き＿ の推論をしていますが、
ユニフィケーション変数が同様の理由で有用であるとき、しばしば同様に ＿前向き＿ 推論をしたいからです。
(*
For example, we can write a tactic that instantiates the quantifiers of a universally quantified hypothesis. The tactic should not need to know what the appropriate instantiations are; rather, we want these choices filled with placeholders. We hope that, when we apply the specialized hypothesis later, syntactic unification will determine concrete values.
*)
例えば、全称定化された仮説の定化子を具体化するタクティクを書くことができます。
タクティクは、適切な具体化が何であるかを知る必要はありません。
むしろ、これらの選択肢は代用品(placeholder)で満たされています。
後で、特化するための(specialized)仮説を適用すると、構文的なユニフィケーションによって、
具体的な値が決まることを願っています。
(*
Before we are ready to write a tactic, we can try out its ingredients one at a time. *)
タクティクを書く準備が整う前に、一度にひとつずつ材料を試すことができます。
*)
Theorem t5 : (forall x : nat, S x > x) -> 2 > 1.
intros.
(** [[
H : forall x : nat, S x > x
============================
2 > 1
]]
(*
To instantiate [H] generically, we first need to name the value to be used for [x].%\index{tactics!evar}% *)
一般的に、[H]を具体化するには、最初に[x]に使用する値の名前を付ける必要があります。%\index{tactics!evar}%
*)
evar (y : nat).
(** [[
H : forall x : nat, S x > x
y := ?279 : nat
============================
2 > 1
]]
(*
The proof context is extended with a new variable [y], which has been assigned to be equal to a fresh unification variable [?279]. We want to instantiate [H] with [?279]. To get ahold of the new unification variable, rather than just its alias [y], we perform a trivial unfolding in the expression [y], using the %\index{tactics!eval}%[eval] Ltac construct, which works with the same reduction strategies that we have seen in tactics (e.g., [simpl], [compute], etc.). *)
証明コンテキストは新しい変数 [y] で拡張され、
新しいユニフィケーション変数 [?279] と等しくなるように割り当てられています。
[?279] と [H] を具体化する必要があります。
エイリアス [y] だけではなく、新しいユニフィケーション変数を取得するために、Ltac の
%\index{tactics!eval}%[eval]
要素使用して式 [y] で自明な展開(unfolding)を実行します。
タクティク（例えば、[simpl]、[compute]など）で見られたのと同じ簡約戦略(reduction strategies)です。
*)
let y' := eval unfold y in y in
clear y; specialize (H y').
(** [[
H : S ?279 > ?279
============================
2 > 1
]]
(*
Our instantiation was successful. We can finish the proof by using [apply]'s unification to figure out the proper value of [?279]. *)
具体化は成功しました。
[apply] のユニフィケーションを使って [?279] の固有な値を計算することで証明を終えることができます。
*)
apply H.
Qed.
(**
(* Now we can write a tactic that encapsulates the pattern we just employed, instantiating all quantifiers of a particular hypothesis. *)
今使っているパターンをカプセル化して、特定の仮説のすべての量化子を具体化する方法を書くことができます。
*)
(* begin hide *)
Definition red_herring := O.
(* end hide *)
Ltac insterU H :=
repeat match type of H with
| forall x : ?T, _ =>
let x := fresh "x" in
evar (x : T);
let x' := eval unfold x in x in
clear x; specialize (H x')
end.
Theorem t5' : (forall x : nat, S x > x) -> 2 > 1.
intro H; insterU H; apply H.
Qed.
(**
(* This particular example is somewhat silly, since [apply] by itself would have solved the goal originally. Separate forward reasoning is more useful on hypotheses that end in existential quantifications. Before we go through an example, it is useful to define a variant of [insterU] that does not clear the base hypothesis we pass to it. We use the Ltac construct %\index{tactics!fresh}%[fresh] to generate a hypothesis name that is not already used, based on a string suggesting a good name. *)
この特定の例は、[apply] 自体が本来の目的を達成していたので、やや馬鹿げています。
別の前方推論は、存在量化の定量化で終わる仮説により有用です。
例を見る前に、
私たちが渡すベースとなる仮説を除去(clear)していない [insterU] の変種の Ltac の構成要素
%\index{tactics!fresh}%[fresh] を使用して、（引数の)文字列で示唆されるよい名前に基づいた、
まだ使用されていない仮説名を生成します。
*)
Ltac insterKeep H :=
let H' := fresh "H'" in
generalize H; intro H'; insterU H'.
Section t6.
Variables A B : Type.
Variable P : A -> B -> Prop.
Variable f : A -> A -> A.
Variable g : B -> B -> B.
Hypothesis H1 : forall v, exists u, P v u.
Hypothesis H2 : forall v1 u1 v2 u2,
P v1 u1
-> P v2 u2
-> P (f v1 v2) (g u1 u2).
Theorem t6 : forall v1 v2, exists u1, exists u2, P (f v1 v2) (g u1 u2).
intros.
(**
(* Neither [eauto] nor [firstorder] is clever enough to prove this goal. We can help out by doing some of the work with quantifiers ourselves, abbreviating the proof with the %\index{tactics!do}%[do] tactical for repetition of a tactic a set number of times. *)
[eauto] も [firstorder] もこのゴールを証明するほどには賢くはありません。
量化子を使っていくつかの作業を自分で行い、%\index{tactics!do}%[do] タクティカルによって、
一定回数のタクティクを繰り返すことで、証明を省略します。
*)
do 2 insterKeep H1.
(**
(* Our proof state is extended with two generic instances of [H1].
*)
証明状態は[H1]のふたつの一般的なインスタンスで拡張されています。
[[
H' : exists u : B, P ?4289 u
H'0 : exists u : B, P ?4288 u
============================
exists u1 : B, exists u2 : B, P (f v1 v2) (g u1 u2)
]]
(*
Normal [eauto] still cannot prove the goal, so we eliminate the two new existential quantifiers. (Recall that [ex] is the underlying type family to which uses of the [exists] syntax are compiled.) *)
通常の[eauto]はまだ目標を証明することができませんので、
ふたつの新しい存在量化子を削除します。
（[ex]は、[exists]構文の使用がコンパイルされるもとになる型ファミリであることを思い出してください）
*)
repeat match goal with
| [ H : ex _ |- _ ] => destruct H
end.
(**
(* Now the goal is simple enough to solve by logic programming. *)
ゴールは、論理プログラミングで解くには、とても単純です。
*)
eauto.
Qed.
End t6.
(**
(* Our [insterU] tactic does not fare so well with quantified hypotheses that also contain implications. We can see the problem in a slight modification of the last example. We introduce a new unary predicate [Q] and use it to state an additional requirement of our hypothesis [H1]. *)
[insterU] タクティクは、含意も含む量化仮説ではあまりうまくいきません。
最後の例をわずかに変更して問題を見ることができます。
新しい単項の述語[Q]を導入し、仮説[H1]の追加の要求を表示するのに使います。
*)
Section t7.
Variables A B : Type.
Variable Q : A -> Prop.
Variable P : A -> B -> Prop.
Variable f : A -> A -> A.
Variable g : B -> B -> B.
Hypothesis H1 : forall v, Q v -> exists u, P v u.
Hypothesis H2 : forall v1 u1 v2 u2,
P v1 u1
-> P v2 u2
-> P (f v1 v2) (g u1 u2).
Theorem t7 : forall v1 v2, Q v1 -> Q v2 -> exists u1, exists u2, P (f v1 v2) (g u1 u2).
intros; do 2 insterKeep H1;
repeat match goal with
| [ H : ex _ |- _ ] => destruct H
end; eauto.
(**
(* This proof script does not hit any errors until the very end, when an error message like this one is displayed.
この証明スクリプトは、このようなエラーメッセージが表示した最後まで、何のエラーも発生しません。
*)
<<
No more subgoals but non-instantiated existential variables :
Existential 1 =
>>
%\vspace{-.35in}%[[
?4384 : [A : Type
B : Type
Q : A -> Prop
P : A -> B -> Prop
f : A -> A -> A
g : B -> B -> B
H1 : forall v : A, Q v -> exists u : B, P v u
H2 : forall (v1 : A) (u1 : B) (v2 : A) (u2 : B),
P v1 u1 -> P v2 u2 -> P (f v1 v2) (g u1 u2)
v1 : A
v2 : A
H : Q v1
H0 : Q v2
H' : Q v2 -> exists u : B, P v2 u |- Q v2]
]]
(*
There is another similar line about a different existential variable. Here, "existential variable" means what we have also called "unification variable." In the course of the proof, some unification variable [?4384] was introduced but never unified. Unification variables are just a device to structure proof search; the language of Gallina proof terms does not include them. Thus, we cannot produce a proof term without instantiating the variable.
*)
別の存在変数(existential variable)についても同様の行があります。
ここで、「存在変数」とは、「ユニフィケーション変数」とも呼ばれるものを意味します。
証明の過程で、ユニフィケーション変数[?4384]が導入されましたが、
ユニフィケーションされませんでした。
ユニフィケーション変数は、証明検索を構造化するための単なる器(device)です。
Gallina言語の証明項にはそれらが含まれていません。
したがって、変数を具体化せずに証明項を生成することはできません。
(*
The error message shows that [?4384] is meant to be a proof of [Q v2] in a particular proof state, whose variables and hypotheses are displayed. It turns out that [?4384] was created by [insterU], as the value of a proof to pass to [H1]. Recall that, in Gallina, implication is just a degenerate case of [forall] quantification, so the [insterU] code to match against [forall] also matched the implication. Since any proof of [Q v2] is as good as any other in this context, there was never any opportunity to use unification to determine exactly which proof is appropriate. We expect similar problems with any implications in arguments to [insterU]. *)
エラーメッセージは、[?4384]が変数と仮説が表示されている特定の証明状態の
[Q v2]の証明であることを示しています。
それは[?4384]が[H1]に渡す証明の値として[insterU]によって作成されたことが判明しました。
Gallinaでは、含意は単に[forall]量化の縮退したかたちであるため、
[forall]と一致させる[insterU]コードもこの含意と一致したことを思い出してください。
この文脈で[Q v2]の証明は他の証明と同じくらい良いので、
どの証明が適切かを正確に判断するためにユニフィケーションを使う機会は決してありません。
同様に[insterU]の引数にある含意の問題を予期しています。
*)
Abort.
End t7.
Reset insterU.
(* begin hide *)
Reset red_herring.
(* end hide *)
(**
(* We can redefine [insterU] to treat implications differently. In particular, we pattern-match on the type of the type [T] in [forall x : ?T, ...]. If [T] has type [Prop], then [x]'s instantiation should be thought of as a proof. Thus, instead of picking a new unification variable for it, we instead apply a user-supplied tactic [tac]. It is important that we end this special [Prop] case with [|| fail 1], so that, if [tac] fails to prove [T], we abort the instantiation, rather than continuing on to the default quantifier handling. Also recall that the tactic form %\index{tactics!solve}%[solve [ t ]] fails if [t] does not completely solve the goal. *)
[forall x : ?T, ...]の型[T]の型をパターンマッチさせる[T]に型[Prop]、
[x]の具体化は証明のために考える必要があります。
したがって、新しい統一変数を選択するのではなく、
ユーザーが指定した戦術[tac]を適用します。
[tac]が[T]を証明するのに失敗した場合、
デフォルトの量化の処理を続けるのではなく、
具体化を中止します。また、
%\index{tactics!solve}%
が目標を完全に解決しない場合、[solve [t]] は失敗します。*）
*)
Ltac insterU tac H :=
repeat match type of H with
| forall x : ?T, _ =>
match type of T with
| Prop =>
(let H' := fresh "H'" in
assert (H' : T) by solve [ tac ];
specialize (H H'); clear H')
|| fail 1
| _ =>
let x := fresh "x" in
evar (x : T);
let x' := eval unfold x in x in
clear x; specialize (H x')
end
end.
Ltac insterKeep tac H :=
let H' := fresh "H'" in
generalize H; intro H'; insterU tac H'.
Section t7.
Variables A B : Type.
Variable Q : A -> Prop.
Variable P : A -> B -> Prop.
Variable f : A -> A -> A.
Variable g : B -> B -> B.
Hypothesis H1 : forall v, Q v -> exists u, P v u.
Hypothesis H2 : forall v1 u1 v2 u2,
P v1 u1
-> P v2 u2
-> P (f v1 v2) (g u1 u2).
Theorem t7 : forall v1 v2, Q v1 -> Q v2 -> exists u1, exists u2, P (f v1 v2) (g u1 u2).
(**
(* We can prove the goal by calling [insterKeep] with a tactic that tries to find and apply a [Q] hypothesis over a variable about which we do not yet know any [P] facts. We need to begin this tactic code with [idtac; ] to get around a strange limitation in Coq's proof engine, where a first-class tactic argument may not begin with a [match]. *)
まだ[P]の事実を知らない変数について[Q]仮説を見つけて適用しようとするタクティクで
[insterKeep]を呼び出すことによってゴールを証明することができます。
Coqの証明エンジンで、
ファーストクラスのタクティクの引数が、
[match]で始まらなければならないという奇妙な制限を回避するために、
このタクティクのコードを[idtac; ]で始める必要があります。
*)
intros; do 2 insterKeep ltac:(idtac; match goal with
| [ H : Q ?v |- _ ] =>
match goal with
| [ _ : context[P v _] |- _ ] => fail 1
| _ => apply H
end
end) H1;
repeat match goal with
| [ H : ex _ |- _ ] => destruct H
end; eauto.
Qed.
End t7.
(**
(* It is often useful to instantiate existential variables explicitly. A built-in tactic provides one way of doing so. *)
存在変数(existential variables)を明示的に具体化することはしばしば役に立ちます。
組み込みタクティクはそれをするひとつの方法を提供します。
*)
Theorem t8 : exists p : nat * nat, fst p = 3.
econstructor; instantiate (1 := (3, 2)); reflexivity.
Qed.
(**
(* The [1] above is identifying an existential variable appearing in the current goal, with the last existential appearing assigned number 1, the second-last assigned number 2, and so on. The named existential is replaced everywhere by the term to the right of the [:=].
*)
上記の[1]は、現在のゴールに現れる存在変数を特定するもので、
最後に存在するものが番号1に割り当てられ、2番目に割り当てられた番号2が割り当てられます。
名前のついた存在（変数）は、どこでも[:=]の右側の項に置き換えられます。
(*
The %\index{tactics!instantiate}%[instantiate] tactic can be convenient for exploratory proving, but it leads to very brittle proof scripts that are unlikely to adapt to changing theorem statements. It is often more helpful to have a tactic that can be used to assign a value to a term that is known to be an existential. By employing a roundabout implementation technique, we can build a tactic that generalizes this functionality. In particular, our tactic [equate] will assert that two terms are equal. If one of the terms happens to be an existential, then it will be replaced everywhere with the other term. *)
%\index{tactics!instantiate}%[instantiate] タクティクは
探索的な証明(exploratory proving)のためには便利かもしれませんが、
変化する定理には適応しにくい非常に脆い証明スクリプトにつながります。
実在すると判っている項に値を割り当てるために使用できるタクティクを持つことは、しばしば有用です。
婉曲な(roundabout)実装技術を採用することで、この機能を一般化するタクティクを作ることができます。
特に、我々の戦術[equate]は、2つの項が等しいことを主張します。
項のひとつが存在していれば、それはどこにでも置き換えられます。
*)
Ltac equate x y :=
let dummy := constr:(eq_refl x : x = y) in idtac.
(**
(* This tactic fails if it is not possible to prove [x = y] by [eq_refl]. We check the proof only for its unification side effects, ignoring the associated variable [dummy]. With [equate], we can build a less brittle version of the prior example. *)
[eq_refl]で[x = y]を証明することができない場合、この方法は失敗します。
関連する変数[dummy]を無視して、ユニフィケーションの副作用のみをチェックします。
[equate] によって先の例の脆弱なバージョンを作ることができます。
*)
Theorem t9 : exists p : nat * nat, fst p = 3.
econstructor; match goal with
| [ |- fst ?x = 3 ] => equate x (3, 2)
end; reflexivity.
Qed.
(**
(* This technique is even more useful within recursive and iterative tactics that are meant to solve broad classes of goals. *)
このテクニックは、
広範囲のゴールを解決するための再帰な繰り返しのあるタクティクの中でさらに役立ちます。
*)
(* END *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3B_PP_SYMBOL_V
`define SKY130_FD_SC_LP__NAND3B_PP_SYMBOL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand3b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3B_PP_SYMBOL_V
|
module deserializer(
clk, //serialized data proper clock
enable, //suspend while enable on low
reset, //set output to zero and reset counter to 0 on high
framesize, //number of bits to be deserialized - 1
in, //serialized data
out, //deserialized data
complete //reset counter to 0 and hold out's data while high
);
parameter BITS = 136; //size of deserializer
parameter BITS_COUNTER = 8; //size of counter, must be at least log2(BITS)
parameter COUNTER_MAX = 8'hFF; //max possible value
input clk, enable, reset, in;
input [BITS_COUNTER-1:0] framesize;
output reg complete;
output reg [BITS-1:0] out;
reg [BITS_COUNTER-1:0] counter; //we need to know which array item (out) to write on
always@(posedge reset) begin
out = 0;
counter = framesize;
complete = 0;
end
always@(posedge clk) begin
if(enable) begin
if(~complete) begin //as long there's not any reset state, count
out[counter] <= in;
counter = counter - 1; //next item
end
end else begin
complete = 0;
end
end
always@(counter) begin
if(counter == COUNTER_MAX) begin //all bits have been read
complete = 1;
end
end
always@(complete) begin
counter = framesize; //this way there's no need to reset every time we start a transaction (resetting all out bits consumes power)
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXTP_4_V
`define SKY130_FD_SC_MS__DFXTP_4_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog wrapper for dfxtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfxtp_4 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfxtp_4 (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXTP_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MAJ3_TB_V
`define SKY130_FD_SC_LP__MAJ3_TB_V
/**
* maj3: 3-input majority vote.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__maj3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_lp__maj3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__MAJ3_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD3_FUNCTIONAL_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD3_FUNCTIONAL_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__clkdlyinv3sd3 (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD3_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_PP_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__clkdlybuf4s25 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_PP_V |
/**
* Decodes the ps2 data into scan codes.
*
* The ps2 protocol is here http://www.computer-engineering.org/ps2protocol/
*/
module ps2_controller (
input reset,
input clk,
input ps2_clock,
input ps2_data,
output scan_ready,
output [7:0] scan_code
);
reg [7:0] r_scan_code;
reg [3:0] state_reg = 4'd0;
reg ready;
reg [1:0] ps2_clock_edge_detect = 2'b00;
wire ps2_clock_negedge;
assign scan_code = r_scan_code;
assign scan_ready = ready;
assign ps2_clock_negedge = (ps2_clock_edge_detect == 2'b10);
// Sample the ps2_clock.
always @(posedge clk) begin
ps2_clock_edge_detect <= {ps2_clock_edge_detect[0], ps2_clock};
end
// ps2_clock is goes low 15us after the data is set.
always @(posedge clk or posedge reset) begin
if (reset) begin
state_reg <= 4'b0;
r_scan_code <= 8'b0;
end
else if (ready) begin
// Ensure ready flag is only one system clock.
ready <= 1'b0;
end
else if (ps2_clock_negedge) begin
case (state_reg)
4'd0: // 1 start bit. This is always 0.
begin
state_reg <= state_reg + 1'b1;
ready <= 1'b0;
end
4'd9: // 1 parity bit (odd parity).
begin
if (!ps2_data == ^r_scan_code) begin
ready <= 1'b1;
end else begin
ready <= 1'b0;
end
state_reg <= state_reg + 1'b1;
end
4'd10: // 1 stop bit. This is always 1.
begin
state_reg <= 4'b0;
ready <= 1'b0;
end
default: // 8 data bits, least significant bit first.
begin
r_scan_code[state_reg - 1] <= ps2_data;
state_reg <= state_reg + 1'b1;
ready <= 1'b0;
end
endcase
end
end
endmodule
|
//#############################################################################
//# Function: Generic RAM memory #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_memory_ram # (parameter DW = 104, //memory width
parameter DEPTH = 32, //memory depth
parameter AW = $clog2(DEPTH) // address width
)
(// read-port
input rd_clk,// rd clock
input rd_en, // memory access
input [AW-1:0] rd_addr, // address
output reg [DW-1:0] rd_dout, // data output
// write-port
input wr_clk,// wr clock
input wr_en, // memory access
input [AW-1:0] wr_addr, // address
input [DW-1:0] wr_wem, // write enable vector
input [DW-1:0] wr_din // data input
);
reg [DW-1:0] ram [DEPTH-1:0];
integer i;
//registered read port
always @ (posedge rd_clk)
if(rd_en)
rd_dout[DW-1:0] <= ram[rd_addr[AW-1:0]];
//write port with vector enable
always @(posedge wr_clk)
for (i=0;i<DW;i=i+1)
if (wr_en & wr_wem[i])
ram[wr_addr[AW-1:0]][i] <= wr_din[i];
endmodule // oh_memory_ram
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : ime_best_mv_above_16.v
// Author : Huang Lei Lei
// Created : 2014-12-08
// Description : best motion vector and corressponding cost for blocks above 16 (not including 16x16)
//
//-------------------------------------------------------------------
//
// Modified : 2014-12-21
// Description : mv_cost added
// Modified : 2014-12-21
// Description : update added (to generate partition and mode)
// Modified : 2015-03-20
// Description : bugs removed (init problems)
// Modified : 2015-08-18
// Description : datawidth of mv_x_16x16_c_w and mv_y_16x16_c_w corrected
//
//-------------------------------------------------------------------
`include "enc_defines.v"
`define COST_WIDTH (`PIXEL_WIDTH+12)
module ime_best_mv_above_16 (
// global
clk ,
rstn ,
// ctrl_i
start_i ,
val_i ,
qp_i ,
// update_i
update_wrk_i ,
update_cnt_i ,
update_cst_i ,
// sad_i
sad_16x16_00_i , sad_16x16_10_i , sad_16x16_20_i , sad_16x16_30_i ,
sad_16x16_01_i , sad_16x16_11_i , sad_16x16_21_i , sad_16x16_31_i ,
sad_16x16_02_i , sad_16x16_12_i , sad_16x16_22_i , sad_16x16_32_i ,
sad_16x16_03_i , sad_16x16_13_i , sad_16x16_23_i , sad_16x16_33_i ,
// mv_i
mv_x_16x16_i ,
mv_y_16x16_i ,
// cost_o
// cost_16x32
cost_16x32_00_o , cost_16x32_20_o ,
cost_16x32_01_o , cost_16x32_21_o ,
cost_16x32_02_o , cost_16x32_22_o ,
cost_16x32_03_o , cost_16x32_23_o ,
// cost_32x16
cost_32x16_00_o , cost_32x16_20_o ,
cost_32x16_10_o , cost_32x16_30_o ,
cost_32x16_02_o , cost_32x16_22_o ,
cost_32x16_12_o , cost_32x16_32_o ,
// cost_32x32
cost_32x32_00_o , cost_32x32_20_o ,
cost_32x32_02_o , cost_32x32_22_o ,
// cost_32x64
cost_32x64_00_o ,
cost_32x64_02_o ,
// cost_64x32
cost_64x32_00_o , cost_64x32_20_o ,
// cost_64x64
cost_64x64_00_o ,
// mv_x_o
// mv_x_16x32
mv_x_16x32_00_o , mv_x_16x32_20_o ,
mv_x_16x32_01_o , mv_x_16x32_21_o ,
mv_x_16x32_02_o , mv_x_16x32_22_o ,
mv_x_16x32_03_o , mv_x_16x32_23_o ,
// mv_x_32x16
mv_x_32x16_00_o , mv_x_32x16_20_o ,
mv_x_32x16_10_o , mv_x_32x16_30_o ,
mv_x_32x16_02_o , mv_x_32x16_22_o ,
mv_x_32x16_12_o , mv_x_32x16_32_o ,
// mv_x_32x32
mv_x_32x32_00_o , mv_x_32x32_20_o ,
mv_x_32x32_02_o , mv_x_32x32_22_o ,
// mv_x_32x64
mv_x_32x64_00_o ,
mv_x_32x64_02_o ,
// mv_x_64x32
mv_x_64x32_00_o , mv_x_64x32_20_o ,
// mv_x_64x64
mv_x_64x64_00_o ,
// mv_y_o
// mv_y_16x32
mv_y_16x32_00_o , mv_y_16x32_20_o ,
mv_y_16x32_01_o , mv_y_16x32_21_o ,
mv_y_16x32_02_o , mv_y_16x32_22_o ,
mv_y_16x32_03_o , mv_y_16x32_23_o ,
// mv_y_32x16
mv_y_32x16_00_o , mv_y_32x16_20_o ,
mv_y_32x16_10_o , mv_y_32x16_30_o ,
mv_y_32x16_02_o , mv_y_32x16_22_o ,
mv_y_32x16_12_o , mv_y_32x16_32_o ,
// mv_y_32x32
mv_y_32x32_00_o , mv_y_32x32_20_o ,
mv_y_32x32_02_o , mv_y_32x32_22_o ,
// mv_y_32x64
mv_y_32x64_00_o ,
mv_y_32x64_02_o ,
// mv_y_64x32
mv_y_64x32_00_o , mv_y_64x32_20_o ,
// mv_y_64x64
mv_y_64x64_00_o
);
//*** PARAMETER DECLARATION ****************************************************
//*** INPUT/OUTPUT DECLARATION *************************************************
// global
input clk ;
input rstn ;
// ctrl_i
input start_i ;
input val_i ;
input [5 : 0] qp_i ;
// update_i
input update_wrk_i ;
input [6 : 0] update_cnt_i ;
input [`COST_WIDTH-1 : 0] update_cst_i ;
// sad_i
input [`PIXEL_WIDTH+7 : 0] sad_16x16_00_i , sad_16x16_10_i , sad_16x16_20_i , sad_16x16_30_i ;
input [`PIXEL_WIDTH+7 : 0] sad_16x16_01_i , sad_16x16_11_i , sad_16x16_21_i , sad_16x16_31_i ;
input [`PIXEL_WIDTH+7 : 0] sad_16x16_02_i , sad_16x16_12_i , sad_16x16_22_i , sad_16x16_32_i ;
input [`PIXEL_WIDTH+7 : 0] sad_16x16_03_i , sad_16x16_13_i , sad_16x16_23_i , sad_16x16_33_i ;
// mv_i
input [`IMV_WIDTH-1 : 0] mv_x_16x16_i ;
input [`IMV_WIDTH-1 : 0] mv_y_16x16_i ;
// cost_o
// cost_16x32
output reg [`COST_WIDTH-1 : 0] cost_16x32_00_o , cost_16x32_20_o ;
output reg [`COST_WIDTH-1 : 0] cost_16x32_01_o , cost_16x32_21_o ;
output reg [`COST_WIDTH-1 : 0] cost_16x32_02_o , cost_16x32_22_o ;
output reg [`COST_WIDTH-1 : 0] cost_16x32_03_o , cost_16x32_23_o ;
// cost_32x16
output reg [`COST_WIDTH-1 : 0] cost_32x16_00_o , cost_32x16_20_o ;
output reg [`COST_WIDTH-1 : 0] cost_32x16_10_o , cost_32x16_30_o ;
output reg [`COST_WIDTH-1 : 0] cost_32x16_02_o , cost_32x16_22_o ;
output reg [`COST_WIDTH-1 : 0] cost_32x16_12_o , cost_32x16_32_o ;
// cost_32x32
output reg [`COST_WIDTH-1 : 0] cost_32x32_00_o , cost_32x32_20_o ;
output reg [`COST_WIDTH-1 : 0] cost_32x32_02_o , cost_32x32_22_o ;
// cost_32x64
output reg [`COST_WIDTH-1 : 0] cost_32x64_00_o ;
output reg [`COST_WIDTH-1 : 0] cost_32x64_02_o ;
// cost_64x32
output reg [`COST_WIDTH-1 : 0] cost_64x32_00_o , cost_64x32_20_o ;
// cost_64x64
output reg [`COST_WIDTH-1 : 0] cost_64x64_00_o ;
// mv_x_o
// mv_x_16x32
output reg [`IMV_WIDTH-1 : 0] mv_x_16x32_00_o , mv_x_16x32_20_o ;
output reg [`IMV_WIDTH-1 : 0] mv_x_16x32_01_o , mv_x_16x32_21_o ;
output reg [`IMV_WIDTH-1 : 0] mv_x_16x32_02_o , mv_x_16x32_22_o ;
output reg [`IMV_WIDTH-1 : 0] mv_x_16x32_03_o , mv_x_16x32_23_o ;
// mv_x_32x16
output reg [`IMV_WIDTH-1 : 0] mv_x_32x16_00_o , mv_x_32x16_20_o ;
output reg [`IMV_WIDTH-1 : 0] mv_x_32x16_10_o , mv_x_32x16_30_o ;
output reg [`IMV_WIDTH-1 : 0] mv_x_32x16_02_o , mv_x_32x16_22_o ;
output reg [`IMV_WIDTH-1 : 0] mv_x_32x16_12_o , mv_x_32x16_32_o ;
// mv_x_32x32
output reg [`IMV_WIDTH-1 : 0] mv_x_32x32_00_o , mv_x_32x32_20_o ;
output reg [`IMV_WIDTH-1 : 0] mv_x_32x32_02_o , mv_x_32x32_22_o ;
// mv_x_32x64
output reg [`IMV_WIDTH-1 : 0] mv_x_32x64_00_o ;
output reg [`IMV_WIDTH-1 : 0] mv_x_32x64_02_o ;
// mv_x_64x32
output reg [`IMV_WIDTH-1 : 0] mv_x_64x32_00_o , mv_x_64x32_20_o ;
// mv_x_64x64
output reg [`IMV_WIDTH-1 : 0] mv_x_64x64_00_o ;
// mv_y_o
// mv_y_16x32
output reg [`IMV_WIDTH-1 : 0] mv_y_16x32_00_o , mv_y_16x32_20_o ;
output reg [`IMV_WIDTH-1 : 0] mv_y_16x32_01_o , mv_y_16x32_21_o ;
output reg [`IMV_WIDTH-1 : 0] mv_y_16x32_02_o , mv_y_16x32_22_o ;
output reg [`IMV_WIDTH-1 : 0] mv_y_16x32_03_o , mv_y_16x32_23_o ;
// mv_y_32x16
output reg [`IMV_WIDTH-1 : 0] mv_y_32x16_00_o , mv_y_32x16_20_o ;
output reg [`IMV_WIDTH-1 : 0] mv_y_32x16_10_o , mv_y_32x16_30_o ;
output reg [`IMV_WIDTH-1 : 0] mv_y_32x16_02_o , mv_y_32x16_22_o ;
output reg [`IMV_WIDTH-1 : 0] mv_y_32x16_12_o , mv_y_32x16_32_o ;
// mv_y_32x32
output reg [`IMV_WIDTH-1 : 0] mv_y_32x32_00_o , mv_y_32x32_20_o ;
output reg [`IMV_WIDTH-1 : 0] mv_y_32x32_02_o , mv_y_32x32_22_o ;
// mv_y_32x64
output reg [`IMV_WIDTH-1 : 0] mv_y_32x64_00_o ;
output reg [`IMV_WIDTH-1 : 0] mv_y_32x64_02_o ;
// mv_y_64x32
output reg [`IMV_WIDTH-1 : 0] mv_y_64x32_00_o , mv_y_64x32_20_o ;
// mv_y_64x64
output reg [`IMV_WIDTH-1 : 0] mv_y_64x64_00_o ;
//*** WIRE & REG DECLARATION ***************************************************
// sad_w
// sad_16x32
wire [`PIXEL_WIDTH+8 : 0] sad_16x32_00_w , sad_16x32_20_w ;
wire [`PIXEL_WIDTH+8 : 0] sad_16x32_01_w , sad_16x32_21_w ;
wire [`PIXEL_WIDTH+8 : 0] sad_16x32_02_w , sad_16x32_22_w ;
wire [`PIXEL_WIDTH+8 : 0] sad_16x32_03_w , sad_16x32_23_w ;
// sad_32x16
wire [`PIXEL_WIDTH+8 : 0] sad_32x16_00_w , sad_32x16_20_w ;
wire [`PIXEL_WIDTH+8 : 0] sad_32x16_10_w , sad_32x16_30_w ;
wire [`PIXEL_WIDTH+8 : 0] sad_32x16_02_w , sad_32x16_22_w ;
wire [`PIXEL_WIDTH+8 : 0] sad_32x16_12_w , sad_32x16_32_w ;
// sad_32x32
wire [`PIXEL_WIDTH+9 : 0] sad_32x32_00_w , sad_32x32_20_w ;
wire [`PIXEL_WIDTH+9 : 0] sad_32x32_02_w , sad_32x32_22_w ;
// sad_32x64
wire [`PIXEL_WIDTH+10 : 0] sad_32x64_00_w ;
wire [`PIXEL_WIDTH+10 : 0] sad_32x64_02_w ;
// sad_64x32
wire [`PIXEL_WIDTH+10 : 0] sad_64x32_00_w , sad_64x32_20_w ;
// sad_64x64
wire [`PIXEL_WIDTH+11 : 0] sad_64x64_00_w ;
// mv_cost
wire [`FMV_WIDTH-1 : 0] mv_x_16x16_s_w ;
wire [`FMV_WIDTH-1 : 0] mv_y_16x16_s_w ;
wire [`FMV_WIDTH : 0] mv_x_16x16_c_w ;
wire [`FMV_WIDTH : 0] mv_y_16x16_c_w ;
reg [4 : 0] bitsnum_x_w ;
reg [4 : 0] bitsnum_y_w ;
reg [6 : 0] lambda_w ;
wire [12 : 0] mv_cost_w ;
// cost_w
// cost_16x32
wire [`COST_WIDTH-1 : 0] cost_16x32_00_w , cost_16x32_20_w ;
wire [`COST_WIDTH-1 : 0] cost_16x32_01_w , cost_16x32_21_w ;
wire [`COST_WIDTH-1 : 0] cost_16x32_02_w , cost_16x32_22_w ;
wire [`COST_WIDTH-1 : 0] cost_16x32_03_w , cost_16x32_23_w ;
// cost_32x16
wire [`COST_WIDTH-1 : 0] cost_32x16_00_w , cost_32x16_20_w ;
wire [`COST_WIDTH-1 : 0] cost_32x16_10_w , cost_32x16_30_w ;
wire [`COST_WIDTH-1 : 0] cost_32x16_02_w , cost_32x16_22_w ;
wire [`COST_WIDTH-1 : 0] cost_32x16_12_w , cost_32x16_32_w ;
// cost_32x32
wire [`COST_WIDTH-1 : 0] cost_32x32_00_w , cost_32x32_20_w ;
wire [`COST_WIDTH-1 : 0] cost_32x32_02_w , cost_32x32_22_w ;
// cost_32x64
wire [`COST_WIDTH-1 : 0] cost_32x64_00_w ;
wire [`COST_WIDTH-1 : 0] cost_32x64_02_w ;
// cost_64x32
wire [`COST_WIDTH-1 : 0] cost_64x32_00_w , cost_64x32_20_w ;
// cost_64x64
wire [`COST_WIDTH-1 : 0] cost_64x64_00_w ;
// cover_w
// cover_16x32
wire cover_16x32_00_w , cover_16x32_20_w ;
wire cover_16x32_01_w , cover_16x32_21_w ;
wire cover_16x32_02_w , cover_16x32_22_w ;
wire cover_16x32_03_w , cover_16x32_23_w ;
// cover_32x16
wire cover_32x16_00_w , cover_32x16_20_w ;
wire cover_32x16_10_w , cover_32x16_30_w ;
wire cover_32x16_02_w , cover_32x16_22_w ;
wire cover_32x16_12_w , cover_32x16_32_w ;
// cover_32x32
wire cover_32x32_00_w , cover_32x32_20_w ;
wire cover_32x32_02_w , cover_32x32_22_w ;
// cover_32x64
wire cover_32x64_00_w ;
wire cover_32x64_02_w ;
// cover_64x32
wire cover_64x32_00_w , cover_64x32_20_w ;
// cover_64x64
wire cover_64x64_00_w ;
//*** MAIN BODY ****************************************************************
// sad_w
// sad_16x32
assign sad_16x32_00_w = sad_16x16_00_i + sad_16x16_10_i ;
assign sad_16x32_01_w = sad_16x16_01_i + sad_16x16_11_i ;
assign sad_16x32_02_w = sad_16x16_02_i + sad_16x16_12_i ;
assign sad_16x32_03_w = sad_16x16_03_i + sad_16x16_13_i ;
assign sad_16x32_20_w = sad_16x16_20_i + sad_16x16_30_i ;
assign sad_16x32_21_w = sad_16x16_21_i + sad_16x16_31_i ;
assign sad_16x32_22_w = sad_16x16_22_i + sad_16x16_32_i ;
assign sad_16x32_23_w = sad_16x16_23_i + sad_16x16_33_i ;
// sad_32x16
assign sad_32x16_00_w = sad_16x16_00_i + sad_16x16_01_i ;
assign sad_32x16_10_w = sad_16x16_10_i + sad_16x16_11_i ;
assign sad_32x16_02_w = sad_16x16_02_i + sad_16x16_03_i ;
assign sad_32x16_12_w = sad_16x16_12_i + sad_16x16_13_i ;
assign sad_32x16_20_w = sad_16x16_20_i + sad_16x16_21_i ;
assign sad_32x16_30_w = sad_16x16_30_i + sad_16x16_31_i ;
assign sad_32x16_22_w = sad_16x16_22_i + sad_16x16_23_i ;
assign sad_32x16_32_w = sad_16x16_32_i + sad_16x16_33_i ;
// sad_32x32
assign sad_32x32_00_w = sad_16x32_00_w + sad_16x32_01_w ;
assign sad_32x32_02_w = sad_16x32_02_w + sad_16x32_03_w ;
assign sad_32x32_20_w = sad_16x32_20_w + sad_16x32_21_w ;
assign sad_32x32_22_w = sad_16x32_22_w + sad_16x32_23_w ;
// sad 32x64
assign sad_32x64_00_w = sad_32x32_00_w + sad_32x32_20_w ;
assign sad_32x64_02_w = sad_32x32_02_w + sad_32x32_22_w ;
// sad 64x32
assign sad_64x32_00_w = sad_32x32_00_w + sad_32x32_02_w ;
assign sad_64x32_20_w = sad_32x32_20_w + sad_32x32_22_w ;
// sad 64x64
assign sad_64x64_00_w = sad_32x64_00_w + sad_32x64_02_w ;
// mv_cost
assign mv_x_16x16_s_w = ( mv_x_16x16_i-12 ) * 4 ; //+ mv_x_base_i ;
assign mv_y_16x16_s_w = ( mv_y_16x16_i-12 ) * 4 ; //+ mv_y_base_i ;
assign mv_x_16x16_c_w = ( mv_x_16x16_s_w[`FMV_WIDTH-1] ) ? ( {1'b0,~mv_x_16x16_s_w[`FMV_WIDTH-2:0],1'b0} + 3 ) :
( (|mv_x_16x16_s_w[`FMV_WIDTH-2:0]) ? ( {1'b0, mv_x_16x16_s_w[`FMV_WIDTH-2:0],1'b0} )
: 1 );
assign mv_y_16x16_c_w = ( mv_y_16x16_s_w[`FMV_WIDTH-1] ) ? ( {1'b0,~mv_y_16x16_s_w[`FMV_WIDTH-2:0],1'b0} + 3 ) :
( (|mv_y_16x16_s_w[`FMV_WIDTH-2:0]) ? ( {1'b0, mv_y_16x16_s_w[`FMV_WIDTH-2:0],1'b0} )
: 1 );
always @(*) begin
casex( mv_x_16x16_c_w )
'b000_0000_0001 : bitsnum_x_w = 01 ;
'b000_0000_001x : bitsnum_x_w = 03 ;
'b000_0000_01xx : bitsnum_x_w = 05 ;
'b000_0000_1xxx : bitsnum_x_w = 07 ;
'b000_0001_xxxx : bitsnum_x_w = 09 ;
'b000_001x_xxxx : bitsnum_x_w = 11 ;
'b000_01xx_xxxx : bitsnum_x_w = 13 ;
'b000_1xxx_xxxx : bitsnum_x_w = 15 ;
'b001_xxxx_xxxx : bitsnum_x_w = 17 ;
'b01x_xxxx_xxxx : bitsnum_x_w = 19 ;
'b1xx_xxxx_xxxx : bitsnum_x_w = 21 ;
default : bitsnum_x_w = 21 ;
endcase
end
always @(*) begin
casex( mv_y_16x16_c_w )
'b000_0000_0001 : bitsnum_y_w = 01 ;
'b000_0000_001x : bitsnum_y_w = 03 ;
'b000_0000_01xx : bitsnum_y_w = 05 ;
'b000_0000_1xxx : bitsnum_y_w = 07 ;
'b000_0001_xxxx : bitsnum_y_w = 09 ;
'b000_001x_xxxx : bitsnum_y_w = 11 ;
'b000_01xx_xxxx : bitsnum_y_w = 13 ;
'b000_1xxx_xxxx : bitsnum_y_w = 15 ;
'b001_xxxx_xxxx : bitsnum_y_w = 17 ;
'b01x_xxxx_xxxx : bitsnum_y_w = 19 ;
'b1xx_xxxx_xxxx : bitsnum_y_w = 21 ;
default : bitsnum_y_w = 21 ;
endcase
end
always @(*) begin
case( qp_i )
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 : lambda_w = 01 ;
16,17,18,19 : lambda_w = 02 ;
20,21,22 : lambda_w = 03 ;
23,24,25 : lambda_w = 04 ;
26 : lambda_w = 05 ;
27,28 : lambda_w = 06 ;
29 : lambda_w = 07 ;
30 : lambda_w = 08 ;
31 : lambda_w = 09 ;
32 : lambda_w = 10 ;
33 : lambda_w = 11 ;
34 : lambda_w = 13 ;
35 : lambda_w = 14 ;
36 : lambda_w = 16 ;
37 : lambda_w = 18 ;
38 : lambda_w = 20 ;
39 : lambda_w = 23 ;
40 : lambda_w = 25 ;
41 : lambda_w = 29 ;
42 : lambda_w = 32 ;
43 : lambda_w = 36 ;
44 : lambda_w = 40 ;
45 : lambda_w = 45 ;
46 : lambda_w = 51 ;
47 : lambda_w = 57 ;
48 : lambda_w = 64 ;
49 : lambda_w = 72 ;
50 : lambda_w = 81 ;
51 : lambda_w = 91 ;
default : lambda_w = 00 ;
endcase
end
assign mv_cost_w = lambda_w * ( bitsnum_x_w + bitsnum_y_w );
// cost_w
// cost_16x32
assign cost_16x32_00_w = sad_16x32_00_w + mv_cost_w ;
assign cost_16x32_01_w = sad_16x32_01_w + mv_cost_w ;
assign cost_16x32_02_w = sad_16x32_02_w + mv_cost_w ;
assign cost_16x32_03_w = sad_16x32_03_w + mv_cost_w ;
assign cost_16x32_20_w = sad_16x32_20_w + mv_cost_w ;
assign cost_16x32_21_w = sad_16x32_21_w + mv_cost_w ;
assign cost_16x32_22_w = sad_16x32_22_w + mv_cost_w ;
assign cost_16x32_23_w = sad_16x32_23_w + mv_cost_w ;
// cost_32x16
assign cost_32x16_00_w = sad_32x16_00_w + mv_cost_w ;
assign cost_32x16_10_w = sad_32x16_10_w + mv_cost_w ;
assign cost_32x16_02_w = sad_32x16_02_w + mv_cost_w ;
assign cost_32x16_12_w = sad_32x16_12_w + mv_cost_w ;
assign cost_32x16_20_w = sad_32x16_20_w + mv_cost_w ;
assign cost_32x16_30_w = sad_32x16_30_w + mv_cost_w ;
assign cost_32x16_22_w = sad_32x16_22_w + mv_cost_w ;
assign cost_32x16_32_w = sad_32x16_32_w + mv_cost_w ;
// cost_32x32
assign cost_32x32_00_w = sad_32x32_00_w + mv_cost_w ;
assign cost_32x32_02_w = sad_32x32_02_w + mv_cost_w ;
assign cost_32x32_20_w = sad_32x32_20_w + mv_cost_w ;
assign cost_32x32_22_w = sad_32x32_22_w + mv_cost_w ;
// cost 32x64
assign cost_32x64_00_w = sad_32x64_00_w + mv_cost_w ;
assign cost_32x64_02_w = sad_32x64_02_w + mv_cost_w ;
// cost 64x32
assign cost_64x32_00_w = sad_64x32_00_w + mv_cost_w ;
assign cost_64x32_20_w = sad_64x32_20_w + mv_cost_w ;
// cost 64x64
assign cost_64x64_00_w = sad_64x64_00_w + mv_cost_w ;
// cover_w
// cover_16x32
assign cover_16x32_00_w = cost_16x32_00_w < cost_16x32_00_o ;
assign cover_16x32_01_w = cost_16x32_01_w < cost_16x32_01_o ;
assign cover_16x32_02_w = cost_16x32_02_w < cost_16x32_02_o ;
assign cover_16x32_03_w = cost_16x32_03_w < cost_16x32_03_o ;
assign cover_16x32_20_w = cost_16x32_20_w < cost_16x32_20_o ;
assign cover_16x32_21_w = cost_16x32_21_w < cost_16x32_21_o ;
assign cover_16x32_22_w = cost_16x32_22_w < cost_16x32_22_o ;
assign cover_16x32_23_w = cost_16x32_23_w < cost_16x32_23_o ;
// cover_32x16
assign cover_32x16_00_w = cost_32x16_00_w < cost_32x16_00_o ;
assign cover_32x16_10_w = cost_32x16_10_w < cost_32x16_10_o ;
assign cover_32x16_02_w = cost_32x16_02_w < cost_32x16_02_o ;
assign cover_32x16_12_w = cost_32x16_12_w < cost_32x16_12_o ;
assign cover_32x16_20_w = cost_32x16_20_w < cost_32x16_20_o ;
assign cover_32x16_30_w = cost_32x16_30_w < cost_32x16_30_o ;
assign cover_32x16_22_w = cost_32x16_22_w < cost_32x16_22_o ;
assign cover_32x16_32_w = cost_32x16_32_w < cost_32x16_32_o ;
// cover_32x32
assign cover_32x32_00_w = cost_32x32_00_w < cost_32x32_00_o ;
assign cover_32x32_02_w = cost_32x32_02_w < cost_32x32_02_o ;
assign cover_32x32_20_w = cost_32x32_20_w < cost_32x32_20_o ;
assign cover_32x32_22_w = cost_32x32_22_w < cost_32x32_22_o ;
// cover 32x64
assign cover_32x64_00_w = cost_32x64_00_w < cost_32x64_00_o ;
assign cover_32x64_02_w = cost_32x64_02_w < cost_32x64_02_o ;
// cover 64x32
assign cover_64x32_00_w = cost_64x32_00_w < cost_64x32_00_o ;
assign cover_64x32_20_w = cost_64x32_20_w < cost_64x32_20_o ;
// cover 64x64
assign cover_64x64_00_w = cost_64x64_00_w < cost_64x64_00_o ;
// cost_o
always @(posedge clk or negedge rstn ) begin
if( !rstn ) begin
// cost_16x32
cost_16x32_00_o <= -1 ;
cost_16x32_01_o <= -1 ;
cost_16x32_02_o <= -1 ;
cost_16x32_03_o <= -1 ;
cost_16x32_20_o <= -1 ;
cost_16x32_21_o <= -1 ;
cost_16x32_22_o <= -1 ;
cost_16x32_23_o <= -1 ;
// cost_32x16
cost_32x16_00_o <= -1 ;
cost_32x16_10_o <= -1 ;
cost_32x16_02_o <= -1 ;
cost_32x16_12_o <= -1 ;
// cost_32x16
cost_32x16_20_o <= -1 ;
cost_32x16_30_o <= -1 ;
cost_32x16_22_o <= -1 ;
cost_32x16_32_o <= -1 ;
// cost_32x32
cost_32x32_00_o <= -1 ;
cost_32x32_02_o <= -1 ;
// cost_32x32
cost_32x32_20_o <= -1 ;
cost_32x32_22_o <= -1 ;
// cost_32x64
cost_32x64_00_o <= -1 ;
cost_32x64_02_o <= -1 ;
// cost_64x32
cost_64x32_00_o <= -1 ;
cost_64x32_20_o <= -1 ;
// cost_64x64
cost_64x64_00_o <= -1 ;
end
else if( start_i ) begin
// cost_16x32
cost_16x32_00_o <= -1 ;
cost_16x32_01_o <= -1 ;
cost_16x32_02_o <= -1 ;
cost_16x32_03_o <= -1 ;
cost_16x32_20_o <= -1 ;
cost_16x32_21_o <= -1 ;
cost_16x32_22_o <= -1 ;
cost_16x32_23_o <= -1 ;
// cost_32x16
cost_32x16_00_o <= -1 ;
cost_32x16_10_o <= -1 ;
cost_32x16_02_o <= -1 ;
cost_32x16_12_o <= -1 ;
// cost_32x16
cost_32x16_20_o <= -1 ;
cost_32x16_30_o <= -1 ;
cost_32x16_22_o <= -1 ;
cost_32x16_32_o <= -1 ;
// cost_32x32
cost_32x32_00_o <= -1 ;
cost_32x32_02_o <= -1 ;
// cost_32x32
cost_32x32_20_o <= -1 ;
cost_32x32_22_o <= -1 ;
// cost_32x64
cost_32x64_00_o <= -1 ;
cost_32x64_02_o <= -1 ;
// cost_64x32
cost_64x32_00_o <= -1 ;
cost_64x32_20_o <= -1 ;
// cost_64x64
cost_64x64_00_o <= -1 ;
end
else if( val_i ) begin
// cover_16x32
if( cover_16x32_00_w ) cost_16x32_00_o <= cost_16x32_00_w ;
if( cover_16x32_01_w ) cost_16x32_01_o <= cost_16x32_01_w ;
if( cover_16x32_02_w ) cost_16x32_02_o <= cost_16x32_02_w ;
if( cover_16x32_03_w ) cost_16x32_03_o <= cost_16x32_03_w ;
if( cover_16x32_20_w ) cost_16x32_20_o <= cost_16x32_20_w ;
if( cover_16x32_21_w ) cost_16x32_21_o <= cost_16x32_21_w ;
if( cover_16x32_22_w ) cost_16x32_22_o <= cost_16x32_22_w ;
if( cover_16x32_23_w ) cost_16x32_23_o <= cost_16x32_23_w ;
// cover_32x16
if( cover_32x16_00_w ) cost_32x16_00_o <= cost_32x16_00_w ;
if( cover_32x16_10_w ) cost_32x16_10_o <= cost_32x16_10_w ;
if( cover_32x16_02_w ) cost_32x16_02_o <= cost_32x16_02_w ;
if( cover_32x16_12_w ) cost_32x16_12_o <= cost_32x16_12_w ;
// cover_32x16
if( cover_32x16_20_w ) cost_32x16_20_o <= cost_32x16_20_w ;
if( cover_32x16_30_w ) cost_32x16_30_o <= cost_32x16_30_w ;
if( cover_32x16_22_w ) cost_32x16_22_o <= cost_32x16_22_w ;
if( cover_32x16_32_w ) cost_32x16_32_o <= cost_32x16_32_w ;
// cover_32x32
if( cover_32x32_00_w ) cost_32x32_00_o <= cost_32x32_00_w ;
if( cover_32x32_02_w ) cost_32x32_02_o <= cost_32x32_02_w ;
// cover_32x32
if( cover_32x32_20_w ) cost_32x32_20_o <= cost_32x32_20_w ;
if( cover_32x32_22_w ) cost_32x32_22_o <= cost_32x32_22_w ;
// cover_32x64
if( cover_32x64_00_w ) cost_32x64_00_o <= cost_32x64_00_w ;
if( cover_32x64_02_w ) cost_32x64_02_o <= cost_32x64_02_w ;
// cover_64x32
if( cover_64x32_00_w ) cost_64x32_00_o <= cost_64x32_00_w ;
if( cover_64x32_20_w ) cost_64x32_20_o <= cost_64x32_20_w ;
// cover_64x64
if( cover_64x64_00_w ) cost_64x64_00_o <= cost_64x64_00_w ;
end
else if( update_wrk_i ) begin
case( update_cnt_i )
16 : cost_32x32_00_o <= update_cst_i ;
17 : cost_32x32_02_o <= update_cst_i ;
18 : cost_32x32_20_o <= update_cst_i ;
19 : cost_32x32_22_o <= update_cst_i ;
20 : cost_64x64_00_o <= update_cst_i ;
endcase
end
end
// mv_x_o
always @(posedge clk or negedge rstn ) begin
if( !rstn ) begin
// mv_x_16x32
mv_x_16x32_00_o <= -1 ;
mv_x_16x32_01_o <= -1 ;
mv_x_16x32_02_o <= -1 ;
mv_x_16x32_03_o <= -1 ;
mv_x_16x32_20_o <= -1 ;
mv_x_16x32_21_o <= -1 ;
mv_x_16x32_22_o <= -1 ;
mv_x_16x32_23_o <= -1 ;
// mv_x_32x16
mv_x_32x16_00_o <= -1 ;
mv_x_32x16_10_o <= -1 ;
mv_x_32x16_02_o <= -1 ;
mv_x_32x16_12_o <= -1 ;
// mv_x_32x16
mv_x_32x16_20_o <= -1 ;
mv_x_32x16_30_o <= -1 ;
mv_x_32x16_22_o <= -1 ;
mv_x_32x16_32_o <= -1 ;
// mv_x_32x32
mv_x_32x32_00_o <= -1 ;
mv_x_32x32_02_o <= -1 ;
// mv_x_32x32
mv_x_32x32_20_o <= -1 ;
mv_x_32x32_22_o <= -1 ;
// mv_x_32x64
mv_x_32x64_00_o <= -1 ;
mv_x_32x64_02_o <= -1 ;
// mv_x_64x32
mv_x_64x32_00_o <= -1 ;
mv_x_64x32_20_o <= -1 ;
// mv_x_64x64
mv_x_64x64_00_o <= -1 ;
end
else if( val_i ) begin
// cover_16x32
if( cover_16x32_00_w ) mv_x_16x32_00_o <= mv_x_16x16_i ;
if( cover_16x32_01_w ) mv_x_16x32_01_o <= mv_x_16x16_i ;
if( cover_16x32_02_w ) mv_x_16x32_02_o <= mv_x_16x16_i ;
if( cover_16x32_03_w ) mv_x_16x32_03_o <= mv_x_16x16_i ;
if( cover_16x32_20_w ) mv_x_16x32_20_o <= mv_x_16x16_i ;
if( cover_16x32_21_w ) mv_x_16x32_21_o <= mv_x_16x16_i ;
if( cover_16x32_22_w ) mv_x_16x32_22_o <= mv_x_16x16_i ;
if( cover_16x32_23_w ) mv_x_16x32_23_o <= mv_x_16x16_i ;
// cover_32x16
if( cover_32x16_00_w ) mv_x_32x16_00_o <= mv_x_16x16_i ;
if( cover_32x16_10_w ) mv_x_32x16_10_o <= mv_x_16x16_i ;
if( cover_32x16_02_w ) mv_x_32x16_02_o <= mv_x_16x16_i ;
if( cover_32x16_12_w ) mv_x_32x16_12_o <= mv_x_16x16_i ;
// cover_32x16
if( cover_32x16_20_w ) mv_x_32x16_20_o <= mv_x_16x16_i ;
if( cover_32x16_30_w ) mv_x_32x16_30_o <= mv_x_16x16_i ;
if( cover_32x16_22_w ) mv_x_32x16_22_o <= mv_x_16x16_i ;
if( cover_32x16_32_w ) mv_x_32x16_32_o <= mv_x_16x16_i ;
// cover_32x32
if( cover_32x32_00_w ) mv_x_32x32_00_o <= mv_x_16x16_i ;
if( cover_32x32_02_w ) mv_x_32x32_02_o <= mv_x_16x16_i ;
// cover_32x32
if( cover_32x32_20_w ) mv_x_32x32_20_o <= mv_x_16x16_i ;
if( cover_32x32_22_w ) mv_x_32x32_22_o <= mv_x_16x16_i ;
// cover_32x64
if( cover_32x64_00_w ) mv_x_32x64_00_o <= mv_x_16x16_i ;
if( cover_32x64_02_w ) mv_x_32x64_02_o <= mv_x_16x16_i ;
// cover_64x32
if( cover_64x32_00_w ) mv_x_64x32_00_o <= mv_x_16x16_i ;
if( cover_64x32_20_w ) mv_x_64x32_20_o <= mv_x_16x16_i ;
// cover_64x64
if( cover_64x64_00_w ) mv_x_64x64_00_o <= mv_x_16x16_i ;
end
end
// mv_y_o
always @(posedge clk or negedge rstn ) begin
if( !rstn ) begin
// mv_y_16x32
mv_y_16x32_00_o <= -1 ;
mv_y_16x32_01_o <= -1 ;
mv_y_16x32_02_o <= -1 ;
mv_y_16x32_03_o <= -1 ;
mv_y_16x32_20_o <= -1 ;
mv_y_16x32_21_o <= -1 ;
mv_y_16x32_22_o <= -1 ;
mv_y_16x32_23_o <= -1 ;
// mv_y_32x16
mv_y_32x16_00_o <= -1 ;
mv_y_32x16_10_o <= -1 ;
mv_y_32x16_02_o <= -1 ;
mv_y_32x16_12_o <= -1 ;
// mv_y_32x16
mv_y_32x16_20_o <= -1 ;
mv_y_32x16_30_o <= -1 ;
mv_y_32x16_22_o <= -1 ;
mv_y_32x16_32_o <= -1 ;
// mv_y_32x32
mv_y_32x32_00_o <= -1 ;
mv_y_32x32_02_o <= -1 ;
// mv_y_32x32
mv_y_32x32_20_o <= -1 ;
mv_y_32x32_22_o <= -1 ;
// mv_y_32x64
mv_y_32x64_00_o <= -1 ;
mv_y_32x64_02_o <= -1 ;
// mv_y_64x32
mv_y_64x32_00_o <= -1 ;
mv_y_64x32_20_o <= -1 ;
// mv_y_64x64
mv_y_64x64_00_o <= -1 ;
end
else if( val_i ) begin
// cover_16x32
if( cover_16x32_00_w ) mv_y_16x32_00_o <= mv_y_16x16_i ;
if( cover_16x32_01_w ) mv_y_16x32_01_o <= mv_y_16x16_i ;
if( cover_16x32_02_w ) mv_y_16x32_02_o <= mv_y_16x16_i ;
if( cover_16x32_03_w ) mv_y_16x32_03_o <= mv_y_16x16_i ;
if( cover_16x32_20_w ) mv_y_16x32_20_o <= mv_y_16x16_i ;
if( cover_16x32_21_w ) mv_y_16x32_21_o <= mv_y_16x16_i ;
if( cover_16x32_22_w ) mv_y_16x32_22_o <= mv_y_16x16_i ;
if( cover_16x32_23_w ) mv_y_16x32_23_o <= mv_y_16x16_i ;
// cover_32x16
if( cover_32x16_00_w ) mv_y_32x16_00_o <= mv_y_16x16_i ;
if( cover_32x16_10_w ) mv_y_32x16_10_o <= mv_y_16x16_i ;
if( cover_32x16_02_w ) mv_y_32x16_02_o <= mv_y_16x16_i ;
if( cover_32x16_12_w ) mv_y_32x16_12_o <= mv_y_16x16_i ;
// cover_32x16
if( cover_32x16_20_w ) mv_y_32x16_20_o <= mv_y_16x16_i ;
if( cover_32x16_30_w ) mv_y_32x16_30_o <= mv_y_16x16_i ;
if( cover_32x16_22_w ) mv_y_32x16_22_o <= mv_y_16x16_i ;
if( cover_32x16_32_w ) mv_y_32x16_32_o <= mv_y_16x16_i ;
// cover_32x32
if( cover_32x32_00_w ) mv_y_32x32_00_o <= mv_y_16x16_i ;
if( cover_32x32_02_w ) mv_y_32x32_02_o <= mv_y_16x16_i ;
// cover_32x32
if( cover_32x32_20_w ) mv_y_32x32_20_o <= mv_y_16x16_i ;
if( cover_32x32_22_w ) mv_y_32x32_22_o <= mv_y_16x16_i ;
// cover_32x64
if( cover_32x64_00_w ) mv_y_32x64_00_o <= mv_y_16x16_i ;
if( cover_32x64_02_w ) mv_y_32x64_02_o <= mv_y_16x16_i ;
// cover_64x32
if( cover_64x32_00_w ) mv_y_64x32_00_o <= mv_y_16x16_i ;
if( cover_64x32_20_w ) mv_y_64x32_20_o <= mv_y_16x16_i ;
// cover_64x64
if( cover_64x64_00_w ) mv_y_64x64_00_o <= mv_y_16x16_i ;
end
end
//*** DEBUG ********************************************************************
endmodule
|
/*
* DE0Nano_Button.v
*
* ___ _ _ _ _ ___ _ _ ___
* | __._ _ _| |_ ___ _| |_| |___ _| | . | \ |_ _|
* | _>| ' ' | . / ._/ . / . / ._/ . | | || |
* |___|_|_|_|___\___\___\___\___\___|_|_|_\_||_|
*
*
* Created on : 20/06/2015
* Author : Ernesto Andres Rincon Cruz
* Web : www.embeddedant.org
* Device : EP4CE22F17C6N
* Board : DEO-NANO
*
* Revision History:
* Rev 1.0.0 - (ErnestoARC) First release 20/06/2015.
*/
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module DE0Nano_Button(
//////////// CLOCK //////////
CLOCK_50,
//////////// LED //////////
LED,
//////////// KEY //////////
KEY
);
//=======================================================
// PARAMETER declarations
//=======================================================
parameter LED_SEQUENCE_0 =8'b10000000;
parameter LED_SEQUENCE_1 =8'b01000000;
parameter LED_SEQUENCE_2 =8'b00100000;
parameter LED_SEQUENCE_3 =8'b00010000;
parameter LED_SEQUENCE_4 =8'b00001000;
parameter LED_SEQUENCE_5 =8'b00000100;
parameter LED_SEQUENCE_6 =8'b00000010;
parameter LED_SEQUENCE_7 =8'b00000001;
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_50;
//////////// LED //////////
output [7:0] LED;
//////////// KEY //////////
input [1:0] KEY;
//=======================================================
// REG/WIRE declarations
//=======================================================
reg [7:0]LedsState=LED_SEQUENCE_0;
reg [7:0]LedsNextState;
wire Clock_Sequence;
reg SequenceControl=0;
wire Btn1_Signal;
wire Btn2_Signal;
//Frequency Divider Module
ClockDivider #(.Bits_counter (28)) DIVIDER_A
( .P_CLOCK(CLOCK_50),
.P_TIMER_OUT(Clock_Sequence),
.P_COMPARATOR(28'd16000000));
// Debounce circuir for Button1
DeBounce DebBtn1 (
.clk(CLOCK_50),
.n_reset(1'b1),
.button_in(KEY[0]),
.DB_out(Btn1_Signal)
);
// Debounce circuir for Button2
DeBounce DebBtn2 (
.clk(CLOCK_50),
.n_reset(1'b1),
.button_in(KEY[1]),
.DB_out(Btn2_Signal)
);
//=======================================================
// Structural coding
//=======================================================
// Leds Sequence control
always @(*)
begin
case (LedsState)
LED_SEQUENCE_0:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_1;
else
LedsNextState=LED_SEQUENCE_7;
end
LED_SEQUENCE_1:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_2;
else
LedsNextState=LED_SEQUENCE_0;
end
LED_SEQUENCE_2:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_3;
else
LedsNextState=LED_SEQUENCE_1;
end
LED_SEQUENCE_3:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_4;
else
LedsNextState=LED_SEQUENCE_2;
end
LED_SEQUENCE_4:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_5;
else
LedsNextState=LED_SEQUENCE_3;
end
LED_SEQUENCE_5:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_6;
else
LedsNextState=LED_SEQUENCE_4;
end
LED_SEQUENCE_6:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_7;
else
LedsNextState=LED_SEQUENCE_5;
end
LED_SEQUENCE_7:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_0;
else
LedsNextState=LED_SEQUENCE_6;
end
default:
LedsNextState=LED_SEQUENCE_0;
endcase
end
// Led direction control
always @ (posedge CLOCK_50)
begin
if (Btn1_Signal==0)
SequenceControl<=0;
else if (Btn2_Signal==0)
SequenceControl<=1;
else
SequenceControl<=SequenceControl;
end
// Leds sequence registers
always @ (posedge Clock_Sequence)
begin
LedsState<=LedsNextState;
end
//=======================================================
// Connections & assigns
//=======================================================
assign LED = LedsState;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2_4_V
`define SKY130_FD_SC_LS__NOR2_4_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSHOLD_PP_SYMBOL_V
`define SKY130_FD_SC_LP__BUSHOLD_PP_SYMBOL_V
/**
* bushold: Bus signal holder (back-to-back inverter) with
* noninverting reset (gates output driver).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__bushold (
//# {{data|Data Signals}}
inout X ,
//# {{control|Control Signals}}
input RESET,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSHOLD_PP_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 22:29:13 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_sync_ref_1_0/system_vga_sync_ref_1_0_stub.v
// Design : system_vga_sync_ref_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_sync_ref,Vivado 2016.4" *)
module system_vga_sync_ref_1_0(clk, rst, hsync, vsync, start, active, xaddr, yaddr)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,hsync,vsync,start,active,xaddr[9:0],yaddr[9:0]" */;
input clk;
input rst;
input hsync;
input vsync;
output start;
output active;
output [9:0]xaddr;
output [9:0]yaddr;
endmodule
|
module ID_EX_Seg(
input Clk,
input stall,
input flush,
input [31:0]PC_Add,
input OverflowEn,
input[2:0] condition,
input Branch,
input[2:0] PC_write,//Unknown
input[3:0] Mem_Byte_Write,
input[3:0] Rd_Write_Byte_en,
input MemWBSrc,
input Jump,
input ALUShiftSrc,
input [2:0]MemDataSrc,
input ALUSrcA,ALUSrcB,
input [3:0] ALUOp,
input [1:0] RegDst,
input ShiftAmountSrc,
input [1:0] ShiftOp,
input [31:0] OperandA,OperandB,
input [4:0]Rs,Rt,Rd,
input [31:0] Immediate32,
input [4:0]Shamt,
input BranchSel,
input [1:0] RtRead,
output reg [31:0]PC_Add_out,
output reg OverflowEn_out,
output reg[2:0] condition_out,
output reg Branch_out,
output reg[2:0] PC_write_out,
output reg[3:0] Mem_Byte_Write_out,
output reg[3:0] Rd_Write_Byte_en_out,
output reg MemWBSrc_out,
output reg Jump_out,
output reg ALUShiftSrc_out,
output reg [2:0]MemDataSrc_out,
output reg ALUSrcA_out,ALUSrcB_out,
output reg [3:0] ALUOp_out,
output reg [1:0] RegDst_out,
output reg ShiftAmountSrc_out,
output reg [1:0] ShiftOp_out,
output reg [31:0] OperandA_out,OperandB_out,
output reg [4:0] Rs_out,Rt_out,Rd_out,
output reg [31:0] Immediate32_out,
output reg [4:0]Shamt_out,
output reg BranchSel_out,
output reg [1:0] RtRead_out
);
always@(posedge Clk)
begin
if(flush)begin
PC_Add_out <= 32'h0;
OverflowEn_out <= 1'b0;
condition_out <= 3'b0;
Branch_out <= 1'b0;
PC_write_out <= 3'b0;
Mem_Byte_Write_out <= 4'b0;
Rd_Write_Byte_en_out <= 4'b0;
MemWBSrc_out <= 1'b0;
Jump_out <= 1'b0;
ALUShiftSrc_out <= 1'b0;
MemDataSrc_out <= 3'b0;
ALUSrcA_out <= 1'b0;
ALUSrcB_out <= 1'b0;
ALUOp_out <= 4'b0;
RegDst_out <= 2'b0;
ShiftAmountSrc_out <= 1'b0;
ShiftOp_out <= 2'b0;//
OperandA_out <= 32'b0;
OperandB_out <= 32'b0;
Rs_out <= 5'b0;
Rt_out <= 5'b0;
Rd_out <= 5'b0;
Immediate32_out <= 32'b0;
Shamt_out <= 5'b0;
BranchSel_out <= 1'b0;
RtRead_out <= 1'b0;
end
else if(~stall)
begin
PC_Add_out <= PC_Add;
OverflowEn_out <= OverflowEn;
condition_out <= condition;
Branch_out <= Branch;
PC_write_out <= PC_write;
Mem_Byte_Write_out <= Mem_Byte_Write;
Rd_Write_Byte_en_out <= Rd_Write_Byte_en;
MemWBSrc_out <= MemWBSrc;
Jump_out <= Jump;
ALUShiftSrc_out <= ALUShiftSrc;
MemDataSrc_out <= MemDataSrc;
ALUSrcA_out <= ALUSrcA;
ALUSrcB_out <= ALUSrcB;
ALUOp_out <= ALUOp;
RegDst_out <= RegDst;
ShiftAmountSrc_out <= ShiftAmountSrc;
ShiftOp_out <= ShiftOp;
OperandA_out <= OperandA;
OperandB_out <= OperandB;
Rs_out <= Rs;
Rt_out <= Rt;
Rd_out <= Rd;
Immediate32_out <= Immediate32;
Shamt_out <= Shamt;
BranchSel_out <= BranchSel;
RtRead_out <= RtRead;
end
end
endmodule |
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
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// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
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// CRITICAL APPLICATIONS
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// safe, or for use in any application requiring fail-safe
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// regulations governing limitations on product liability.
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// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0
// IP Revision: 1
`timescale 1ns/1ps
module opl3_cpu_processing_system7_0_0 (
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
SDIO0_WP,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input SDIO0_WP;
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_5_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(10.0),
.C_FCLK_CLK1_FREQ(10.0),
.C_FCLK_CLK2_FREQ(10.0),
.C_FCLK_CLK3_FREQ(10.0),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(16'B0),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
/*
* Copyright (c) 2008 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
module alu (
input [31:0] x,
input [15:0] y,
output [31:0] out,
input [ 2:0] t,
input [ 2:0] func,
input [15:0] iflags,
output [ 8:0] oflags,
input word_op,
input [15:0] seg,
input [15:0] off,
input clk,
output div_exc
);
// Net declarations
wire [15:0] add, log, shi, rot;
wire [8:0] othflags;
wire [19:0] oth;
wire [31:0] cnv, mul;
wire af_add, af_cnv;
wire cf_cnv, cf_add, cf_mul, cf_log, cf_shi, cf_rot;
wire of_cnv, of_add, of_mul, of_log, of_shi, of_rot;
wire ofi, sfi, zfi, afi, pfi, cfi;
wire ofo, sfo, zfo, afo, pfo, cfo;
wire flags_unchanged;
wire dexc;
// Module instances
addsub add1 (x[15:0], y, add, func, word_op, cfi, cf_add, af_add, of_add);
conv cnv2 (
.x (x[15:0]),
.func (func),
.out (cnv),
.iflags ({afi, cfi}),
.oflags ({af_cnv, of_cnv, cf_cnv})
);
muldiv mul3 (
.x (x),
.y (y),
.o (mul),
.f (func),
.word_op (word_op),
.cfo (cf_mul),
.ofo (of_mul),
.clk (clk),
.exc (dexc)
);
bitlog log4 (x[15:0], y, log, func, cf_log, of_log);
shifts shi5 (x[15:0], y[4:0], shi, func[1:0], word_op, cfi, ofi, cf_shi, of_shi);
rotate rot6 (x[15:0], y[4:0], func[1:0], cfi, word_op, rot, cf_rot, ofi, of_rot);
othop oth7 (x[15:0], y, seg, off, iflags, func, word_op, oth, othflags);
mux8_16 m0(t, {8'd0, y[7:0]}, add, cnv[15:0],
mul[15:0], log, shi, rot, oth[15:0], out[15:0]);
mux8_16 m1(t, 16'd0, 16'd0, cnv[31:16], mul[31:16],
16'd0, 16'd0, 16'd0, {12'b0,oth[19:16]}, out[31:16]);
mux8_1 a1(t, 1'b0, cf_add, cf_cnv, cf_mul, cf_log, cf_shi, cf_rot, 1'b0, cfo);
mux8_1 a2(t, 1'b0, af_add, af_cnv, 1'b0, 1'b0, 1'b0, afi, 1'b0, afo);
mux8_1 a3(t, 1'b0, of_add, of_cnv, of_mul, of_log, of_shi, of_rot, 1'b0, ofo);
// Flags
assign pfo = flags_unchanged ? pfi : ^~ out[7:0];
assign zfo = flags_unchanged ? zfi
: ((word_op && (t!=3'd2)) ? ~|out[15:0] : ~|out[7:0]);
assign sfo = flags_unchanged ? sfi
: ((word_op && (t!=3'd2)) ? out[15] : out[7]);
assign oflags = (t == 3'd7) ? othflags
: { ofo, iflags[10:8], sfo, zfo, afo, pfo, cfo };
assign ofi = iflags[11];
assign sfi = iflags[7];
assign zfi = iflags[6];
assign afi = iflags[4];
assign pfi = iflags[2];
assign cfi = iflags[0];
assign flags_unchanged = (t == 3'd4 && func == 3'd2
|| t == 3'd5 && y[4:0] == 5'h0
|| t == 3'd6);
assign div_exc = func[1] && (t==3'd3) && dexc;
endmodule
module addsub (
input [15:0] x,
input [15:0] y,
output [15:0] out,
input [ 2:0] f,
input word_op,
input cfi,
output cfo,
output afo,
output ofo
);
// Net declarations
wire [15:0] op2;
wire ci;
wire cfoadd;
wire xs, ys, os;
// Module instances
fulladd16 fa0 ( // We instantiate only one adder
.x (x), // to have less hardware
.y (op2),
.ci (ci),
.co (cfoadd),
.z (out),
.s (f[2])
);
// Assignments
assign op2 = f[2] ? ~y
: ((f[1:0]==2'b11) ? { 8'b0, y[7:0] } : y);
assign ci = f[2] & f[1] | f[2] & ~f[0] & ~cfi
| f[2] & f[0] | (f==3'b0) & cfi;
assign afo = f[1] ? (f[2] ? &out[3:0] : ~|out[3:0] )
: (x[4] ^ y[4] ^ out[4]);
assign cfo = f[1] ? cfi /* inc, dec */
: (word_op ? cfoadd : (x[8]^y[8]^out[8]));
assign xs = word_op ? x[15] : x[7];
assign ys = word_op ? y[15] : y[7];
assign os = word_op ? out[15] : out[7];
assign ofo = f[2] ? (~xs & ys & os | xs & ~ys & ~os)
: (~xs & ~ys & os | xs & ys & ~os);
endmodule
module conv (
input [15:0] x,
input [ 2:0] func,
output [31:0] out,
input [ 1:0] iflags, // afi, cfi
output [ 2:0] oflags // afo, ofo, cfo
);
// Net declarations
wire afi, cfi;
wire ofo, afo, cfo;
wire [15:0] aaa, aas;
wire [ 7:0] daa, tmpdaa, das, tmpdas;
wire [15:0] cbw, cwd;
wire acond, dcond;
wire tmpcf;
// Module instances
mux8_16 m0(func, cbw, aaa, aas, 16'd0,
cwd, {x[15:8], daa}, {x[15:8], das}, 16'd0, out[15:0]);
// Assignments
assign aaa = (acond ? (x + 16'h0106) : x) & 16'hff0f;
assign aas = (acond ? (x - 16'h0106) : x) & 16'hff0f;
assign tmpdaa = acond ? (x[7:0] + 8'h06) : x[7:0];
assign daa = dcond ? (tmpdaa + 8'h60) : tmpdaa;
assign tmpdas = acond ? (x[7:0] - 8'h06) : x[7:0];
assign das = dcond ? (tmpdas - 8'h60) : tmpdas;
assign cbw = { { 8{x[ 7]}}, x[7:0] };
assign { out[31:16], cwd } = { {16{x[15]}}, x };
assign acond = ((x[7:0] & 8'h0f) > 8'h09) | afi;
assign dcond = (x[7:0] > 8'h99) | cfi;
assign afi = iflags[1];
assign cfi = iflags[0];
assign afo = acond;
assign ofo = 1'b0;
assign tmpcf = (x[7:0] < 8'h06) | cfi;
assign cfo = func[2] ? (dcond ? 1'b1 : (acond & tmpcf))
: acond;
assign oflags = { afo, ofo, cfo };
endmodule
module muldiv (
input [31:0] x, // 16 MSb for division
input [15:0] y,
output [31:0] o,
input [ 2:0] f,
input word_op,
output cfo,
output ofo,
input clk,
output exc
);
// Net declarations
wire as, bs, cfs, cfu;
wire [16:0] a, b;
wire [33:0] p;
wire div0, over, ovf, mint;
wire [33:0] zi;
wire [16:0] di;
wire [17:0] q;
wire [17:0] s;
// Module instantiations
mult signmul17 (
.clk (clk),
.a (a),
.b (b),
.p (p)
);
div_su #(34) dut (
.clk (clk),
.ena (1'b1),
.z (zi),
.d (di),
.q (q),
.s (s),
.ovf (ovf),
.div0 (div0)
);
// Sign ext. for imul
assign as = f[0] & (word_op ? x[15] : x[7]);
assign bs = f[0] & (word_op ? y[15] : y[7]);
assign a = word_op ? { as, x[15:0] }
: { {9{as}}, x[7:0] };
assign b = word_op ? { bs, y } : { {9{bs}}, y[7:0] };
assign zi = f[2] ? { 26'h0, x[7:0] }
: (word_op ? (f[0] ? { {2{x[31]}}, x }
: { 2'b0, x })
: (f[0] ? { {18{x[15]}}, x[15:0] }
: { 18'b0, x[15:0] }));
assign di = word_op ? (f[0] ? { y[15], y } : { 1'b0, y })
: (f[0] ? { {9{y[7]}}, y[7:0] }
: { 9'h000, y[7:0] });
assign o = f[2] ? { 16'h0, q[7:0], s[7:0] }
: (f[1] ? ( word_op ? {s[15:0], q[15:0]}
: {16'h0, s[7:0], q[7:0]})
: p[31:0]);
assign ofo = f[1] ? 1'b0 : cfo;
assign cfo = f[1] ? 1'b0 : !(f[0] ? cfs : cfu);
assign cfu = word_op ? (o[31:16] == 16'h0)
: (o[15:8] == 8'h0);
assign cfs = word_op ? (o[31:16] == {16{o[15]}})
: (o[15:8] == {8{o[7]}});
// Exceptions
assign over = f[2] ? 1'b0
: (word_op ? (f[0] ? (q[17:16]!={2{q[15]}})
: (q[17:16]!=2'b0) )
: (f[0] ? (q[17:8]!={10{q[7]}})
: (q[17:8]!=10'h000)));
assign mint = f[0] & (word_op ? (x==32'h80000000)
: (x==16'h8000));
assign exc = div0 | (!f[2] & ovf) | over | mint;
endmodule
module bitlog(x, y, out, func, cfo, ofo);
// IO ports
input [15:0] x, y;
input [2:0] func;
output [15:0] out;
output cfo, ofo;
// Net declarations
wire [15:0] and_n, or_n, not_n, xor_n;
// Module instantiations
mux8_16 m0(func, and_n, or_n, not_n, xor_n, 16'd0, 16'd0, 16'd0, 16'd0, out);
// Assignments
assign and_n = x & y;
assign or_n = x | y;
assign not_n = ~x;
assign xor_n = x ^ y;
assign cfo = 1'b0;
assign ofo = 1'b0;
endmodule
//
// This module implements the instructions shl/sal, sar, shr
//
module shifts(x, y, out, func, word_op, cfi, ofi, cfo, ofo);
// IO ports
input [15:0] x;
input [ 4:0] y;
input [1:0] func;
input word_op;
output [15:0] out;
output cfo, ofo;
input cfi, ofi;
// Net declarations
wire [15:0] sal, sar, shr, sal16, sar16, shr16;
wire [7:0] sal8, sar8, shr8;
wire ofo_shl, ofo_sar, ofo_shr;
wire cfo_sal8, cfo_sal16, cfo_sar8, cfo_sar16, cfo_shr8, cfo_shr16;
wire cfo16, cfo8;
wire unchanged;
// Module instantiations
mux4_16 m0(func, sal, sar, shr, 16'd0, out);
// Assignments
assign { cfo_sal16, sal16 } = x << y;
assign { sar16, cfo_sar16 } = (y > 5'd16) ? 17'h1ffff
: (({x,1'b0} >> y) | (x[15] ? (17'h1ffff << (17 - y))
: 17'h0));
assign { shr16, cfo_shr16 } = ({x,1'b0} >> y);
assign { cfo_sal8, sal8 } = x[7:0] << y;
assign { sar8, cfo_sar8 } = (y > 5'd8) ? 9'h1ff
: (({x[7:0],1'b0} >> y) | (x[7] ? (9'h1ff << (9 - y))
: 9'h0));
assign { shr8, cfo_shr8 } = ({x[7:0],1'b0} >> y);
assign sal = word_op ? sal16 : { 8'd0, sal8 };
assign shr = word_op ? shr16 : { 8'd0, shr8 };
assign sar = word_op ? sar16 : { {8{sar8[7]}}, sar8 };
assign ofo = unchanged ? ofi
: (func[1] ? ofo_shr : (func[0] ? ofo_sar : ofo_shl));
assign cfo16 = func[1] ? cfo_shr16
: (func[0] ? cfo_sar16 : cfo_sal16);
assign cfo8 = func[1] ? cfo_shr8
: (func[0] ? cfo_sar8 : cfo_sal8);
assign cfo = unchanged ? cfi : (word_op ? cfo16 : cfo8);
assign ofo_shl = word_op ? (out[15] != cfo) : (out[7] != cfo);
assign ofo_sar = 1'b0;
assign ofo_shr = word_op ? x[15] : x[7];
assign unchanged = word_op ? (y==5'b0) : (y[3:0]==4'b0);
endmodule
module othop (x, y, seg, off, iflags, func, word_op, out, oflags);
// IO ports
input [15:0] x, y, off, seg, iflags;
input [2:0] func;
input word_op;
output [19:0] out;
output [8:0] oflags;
// Net declarations
wire [15:0] deff, deff2, outf, clcm, setf, intf, strf;
wire [19:0] dcmp, dcmp2;
wire dfi;
// Module instantiations
mux8_16 m0(func, dcmp[15:0], dcmp2[15:0], deff, outf, clcm, setf,
intf, strf, out[15:0]);
assign out[19:16] = func ? dcmp2[19:16] : dcmp[19:16];
// Assignments
assign dcmp = (seg << 4) + deff;
assign dcmp2 = (seg << 4) + deff2;
assign deff = x + y + off;
assign deff2 = x + y + off + 16'd2;
assign outf = y;
assign clcm = y[2] ? (y[1] ? /* -1: clc */ {iflags[15:1], 1'b0}
: /* 4: cld */ {iflags[15:11], 1'b0, iflags[9:0]})
: (y[1] ? /* 2: cli */ {iflags[15:10], 1'b0, iflags[8:0]}
: /* 0: cmc */ {iflags[15:1], ~iflags[0]});
assign setf = y[2] ? (y[1] ? /* -1: stc */ {iflags[15:1], 1'b1}
: /* 4: std */ {iflags[15:11], 1'b1, iflags[9:0]})
: (y[1] ? /* 2: sti */ {iflags[15:10], 1'b1, iflags[8:0]}
: /* 0: outf */ iflags);
assign intf = {iflags[15:10], 2'b0, iflags[7:0]};
assign dfi = iflags[10];
assign strf = dfi ? (x - y) : (x + y);
assign oflags = word_op ? { out[11:6], out[4], out[2], out[0] }
: { iflags[11:8], out[7:6], out[4], out[2], out[0] };
endmodule
|
`timescale 1ns/10ps
module master_clock_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("150.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("40.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
//
// Prof. Taylor 7/24/2014
// <[email protected]>
//
// Updated by Paul Gao 02/2019
//
// DDR or center/edge-aligned SDR source synchronous input channel
//
// this implements:
// incoming source-synchronous capture flops
// async fifo to go from source-synchronous domain to core domain
// outgoing token channel to go from core domain deque to out of chip
// outgoing source-synchronous launch flops for token
//
// note, the default FIFO depth is set to 2^6 based on experiments on FPGA
// FIXME: update these numbers based on clocks in each clock domain and from actual waveforms.
//
// Below is a rough calculation:
//
// 2 clks for channel crossing
// 3 clks for receive fifo crossing
// 1 clk for deque
// 3 clks for receive token fifo crossing
// 4 clks for token decimation
// 2 clks for channel crossing
// 3 clks for sender token fifo crossing
// 1 clk for sender credit counter adjust
// -----------
// 19 clks
//
// This leaves us with 45 elements of margin
// for FPGA inefficiency. Since the FPGA may run
// at 4X slower, this is equivalent to 3 FPGA cycles.
//
// Aside: SERDES make bandwidth-delay product much worse
// because they simultaneously increase bandwidth and delay!
//
// io_*: signals synchronous to io_clk_i
// core_*: signals synchronous to core_clk_i
//
`include "bsg_defines.v"
module bsg_link_source_sync_downstream
#(parameter channel_width_p = 16
,parameter lg_fifo_depth_p = 6
,parameter lg_credit_to_token_decimation_p = 3
// When the async_fifo is not on critical path (e.g. when async_fifo size
// is small), bypass twofer fifo to minimize buffering and latency
,parameter bypass_twofer_fifo_p = 0
,parameter use_hardened_fifo_p = 0
)
(// control signals
input core_clk_i
,input core_link_reset_i
,input io_link_reset_i
// coming from IDDR PHY near the physical I/O. valid_i and data_i signals are assumed to be
// registered, but may be traversing long wires on the top level to reach this module.
,input io_clk_i // sdi_sclk
,input [channel_width_p-1:0] io_data_i // sdi_data
,input io_valid_i // sdi_valid
,output core_token_r_o // sdi_token; output registered
// going into core; uses core clock
,output [channel_width_p-1:0] core_data_o
,output core_valid_o
,input core_yumi_i
);
// ******************************************
// clock-crossing async fifo (with DDR interface)
//
// Note that this async fifo also serves as receive buffer
// The buffer size depends on lg_fifo_depth_p (must match bsg_link_source_sync_upstream)
//
// With token based flow control, fifo should never overflow
// io_async_fifo_full signal is only for debugging purposes
//
wire io_async_fifo_full, io_async_fifo_enq;
logic io_fifo_valid_lo, io_fifo_ready_lo;
logic [channel_width_p-1:0] io_async_fifo_data;
// synopsys translate_off
always_ff @(negedge io_clk_i)
assert(!(io_fifo_ready_lo===0 && io_valid_i===1))
else $error("attempt to enque on full async fifo");
// synopsys translate_on
if (use_hardened_fifo_p == 0)
begin
assign io_async_fifo_enq = io_valid_i;
assign io_async_fifo_data = io_data_i;
assign io_fifo_ready_lo = ~io_async_fifo_full;
end
else
begin: harden
assign io_async_fifo_enq = io_fifo_valid_lo & ~io_async_fifo_full;
bsg_fifo_1r1w_small
#(.width_p (channel_width_p)
,.els_p (1<<lg_fifo_depth_p)
,.harden_p(1)
) fifo
(.clk_i (io_clk_i)
,.reset_i (io_link_reset_i)
,.v_i (io_valid_i)
,.ready_o (io_fifo_ready_lo)
,.data_i (io_data_i)
,.v_o (io_fifo_valid_lo)
,.data_o (io_async_fifo_data)
,.yumi_i (io_async_fifo_enq)
);
end
wire core_async_fifo_deque, core_async_fifo_valid_lo;
logic [channel_width_p-1:0] core_async_fifo_data_lo;
bsg_async_fifo
#(.lg_size_p((use_hardened_fifo_p==0)?lg_fifo_depth_p:3)
,.width_p(channel_width_p)
) baf
(.w_clk_i (io_clk_i)
,.w_reset_i(io_link_reset_i)
,.w_enq_i (io_async_fifo_enq)
,.w_data_i (io_async_fifo_data)
,.w_full_o (io_async_fifo_full)
,.r_clk_i (core_clk_i)
,.r_reset_i(core_link_reset_i)
,.r_deq_i (core_async_fifo_deque)
,.r_data_o (core_async_fifo_data_lo)
,.r_valid_o(core_async_fifo_valid_lo));
if (bypass_twofer_fifo_p == 0)
begin
wire core_async_fifo_ready_li;
// Oct 17, 2014
// we insert a minimal fifo here for two purposes;
// first, this reduces critical
// paths causes by excessive access times of the async fifo.
//
// second, it ensures that asynchronous paths end inside of this module
// and do not propogate out to other modules that may be attached, complicating
// timing assertions.
//
bsg_two_fifo
#(.width_p(channel_width_p)
) twofer
(.clk_i (core_clk_i)
,.reset_i(core_link_reset_i)
// we feed this into the local yumi, but only if it is valid
,.ready_o(core_async_fifo_ready_li)
,.data_i (core_async_fifo_data_lo)
,.v_i (core_async_fifo_valid_lo)
,.v_o (core_valid_o)
,.data_o (core_data_o)
,.yumi_i (core_yumi_i)
);
// a word was transferred to fifo if ...
assign core_async_fifo_deque = core_async_fifo_valid_lo & core_async_fifo_ready_li;
end
else
begin
// keep async_fifo isolated when reset is asserted
assign core_valid_o = (core_link_reset_i)? 1'b0 : core_async_fifo_valid_lo;
assign core_data_o = core_async_fifo_data_lo;
assign core_async_fifo_deque = core_yumi_i;
end
// **********************************************
// credit return
//
// these are credits coming from the receive end of the async fifo in the core clk
// domain and passing to the io clk domain and out of the chip.
//
logic [lg_credit_to_token_decimation_p+1-1:0] core_credits_sent_r;
// which bit of the core_credits_sent_r counter we use determines
// the value of the token line in credits
//
//
// this signal's register should be placed right next to the I/O pad:
// glitch sensitive.
assign core_token_r_o = core_credits_sent_r[lg_credit_to_token_decimation_p];
// Increase token counter when dequeue from async fifo
bsg_counter_clear_up
#(.max_val_p({(lg_credit_to_token_decimation_p+1){1'b1}})
,.init_val_p(0)
,.disable_overflow_warning_p(1) // Allow overflow for this counter
)
token_counter
(.clk_i (core_clk_i)
,.reset_i(core_link_reset_i)
,.clear_i(1'b0)
,.up_i (core_async_fifo_deque)
,.count_o(core_credits_sent_r)
);
endmodule // bsg_source_sync_input |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 10:20:39 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux4x1_8_0_1/RAT_Mux4x1_8_0_1_sim_netlist.v
// Design : RAT_Mux4x1_8_0_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "RAT_Mux4x1_8_0_1,Mux4x1_8,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "Mux4x1_8,Vivado 2016.4" *)
(* NotValidForBitStream *)
module RAT_Mux4x1_8_0_1
(A,
B,
C,
D,
SEL,
X);
input [7:0]A;
input [7:0]B;
input [7:0]C;
input [7:0]D;
input [1:0]SEL;
output [7:0]X;
wire [7:0]A;
wire [7:0]B;
wire [7:0]C;
wire [7:0]D;
wire [1:0]SEL;
wire [7:0]X;
RAT_Mux4x1_8_0_1_Mux4x1_8 U0
(.A(A),
.B(B),
.C(C),
.D(D),
.SEL(SEL),
.X(X));
endmodule
(* ORIG_REF_NAME = "Mux4x1_8" *)
module RAT_Mux4x1_8_0_1_Mux4x1_8
(X,
D,
B,
C,
SEL,
A);
output [7:0]X;
input [7:0]D;
input [7:0]B;
input [7:0]C;
input [1:0]SEL;
input [7:0]A;
wire [7:0]A;
wire [7:0]B;
wire [7:0]C;
wire [7:0]D;
wire [1:0]SEL;
wire [7:0]X;
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[0]_INST_0
(.I0(D[0]),
.I1(B[0]),
.I2(C[0]),
.I3(SEL[1]),
.I4(A[0]),
.I5(SEL[0]),
.O(X[0]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[1]_INST_0
(.I0(D[1]),
.I1(B[1]),
.I2(C[1]),
.I3(SEL[1]),
.I4(A[1]),
.I5(SEL[0]),
.O(X[1]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[2]_INST_0
(.I0(D[2]),
.I1(B[2]),
.I2(C[2]),
.I3(SEL[1]),
.I4(A[2]),
.I5(SEL[0]),
.O(X[2]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[3]_INST_0
(.I0(D[3]),
.I1(B[3]),
.I2(C[3]),
.I3(SEL[1]),
.I4(A[3]),
.I5(SEL[0]),
.O(X[3]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[4]_INST_0
(.I0(D[4]),
.I1(B[4]),
.I2(C[4]),
.I3(SEL[1]),
.I4(A[4]),
.I5(SEL[0]),
.O(X[4]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[5]_INST_0
(.I0(D[5]),
.I1(B[5]),
.I2(C[5]),
.I3(SEL[1]),
.I4(A[5]),
.I5(SEL[0]),
.O(X[5]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[6]_INST_0
(.I0(D[6]),
.I1(B[6]),
.I2(C[6]),
.I3(SEL[1]),
.I4(A[6]),
.I5(SEL[0]),
.O(X[6]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[7]_INST_0
(.I0(D[7]),
.I1(B[7]),
.I2(C[7]),
.I3(SEL[1]),
.I4(A[7]),
.I5(SEL[0]),
.O(X[7]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
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