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module beh_vlog_muxf7_v8_2 (O, I0, I1, S); output O; reg O; input I0, I1, S; always @(I0 or I1 or S) if (S) O = I1; else O = I0; endmodule
module beh_vlog_ff_clr_v8_2 (Q, C, CLR, D); parameter INIT = 0; localparam FLOP_DELAY = 100; output Q; input C, CLR, D; reg Q; initial Q= 1'b0; always @(posedge C ) if (CLR) Q<= 1'b0; else Q<= #FLOP_DELAY D; endmodule
module beh_vlog_ff_pre_v8_2 (Q, C, D, PRE); parameter INIT = 0; localparam FLOP_DELAY = 100; output Q; input C, D, PRE; reg Q; initial Q= 1'b0; always @(posedge C ) if (PRE) Q <= 1'b1; else Q <= #FLOP_DELAY D; endmodule
module beh_vlog_ff_ce_clr_v8_2 (Q, C, CE, CLR, D); parameter INIT = 0; localparam FLOP_DELAY = 100; output Q; input C, CE, CLR, D; reg Q; initial Q= 1'b0; always @(posedge C ) if (CLR) Q <= 1'b0; else if (CE) Q <= #FLOP_DELAY D; endmodule
module write_netlist_v8_2 #( parameter C_AXI_TYPE = 0 ) ( S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY, w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID, S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c ); input S_ACLK; input S_ARESETN; input S_AXI_AWVALID; input S_AXI_WVALID; input S_AXI_BREADY; input w_last_c; input bready_timeout_c; output aw_ready_r; output S_AXI_WREADY; output S_AXI_BVALID; output S_AXI_WR_EN; output addr_en_c; output incr_addr_c; output bvalid_c; //------------------------------------------------------------------------- //AXI LITE //------------------------------------------------------------------------- generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm wire w_ready_r_7; wire w_ready_c; wire aw_ready_c; wire NlwRenamedSignal_bvalid_c; wire NlwRenamedSignal_incr_addr_c; wire present_state_FSM_FFd3_13; wire present_state_FSM_FFd2_14; wire present_state_FSM_FFd1_15; wire present_state_FSM_FFd4_16; wire present_state_FSM_FFd4_In; wire present_state_FSM_FFd3_In; wire present_state_FSM_FFd2_In; wire present_state_FSM_FFd1_In; wire present_state_FSM_FFd4_In1_21; wire [0:0] Mmux_aw_ready_c ; begin assign S_AXI_WREADY = w_ready_r_7, S_AXI_BVALID = NlwRenamedSignal_incr_addr_c, S_AXI_WR_EN = NlwRenamedSignal_bvalid_c, incr_addr_c = NlwRenamedSignal_incr_addr_c, bvalid_c = NlwRenamedSignal_bvalid_c; assign NlwRenamedSignal_incr_addr_c = 1'b0; beh_vlog_ff_clr_v8_2 #( .INIT (1'b0)) aw_ready_r_2 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( aw_ready_c), .Q ( aw_ready_r) ); beh_vlog_ff_clr_v8_2 #( .INIT (1'b0)) w_ready_r ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( w_ready_c), .Q ( w_ready_r_7) ); beh_vlog_ff_pre_v8_2 #( .INIT (1'b1)) present_state_FSM_FFd4 ( .C ( S_ACLK), .D ( present_state_FSM_FFd4_In), .PRE ( S_ARESETN), .Q ( present_state_FSM_FFd4_16) ); beh_vlog_ff_clr_v8_2 #( .INIT (1'b0)) present_state_FSM_FFd3 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd3_In), .Q ( present_state_FSM_FFd3_13) ); beh_vlog_ff_clr_v8_2 #( .INIT (1'b0)) present_state_FSM_FFd2 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd2_In), .Q ( present_state_FSM_FFd2_14) ); beh_vlog_ff_clr_v8_2 #( .INIT (1'b0)) present_state_FSM_FFd1 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd1_In), .Q ( present_state_FSM_FFd1_15) ); STATE_LOGIC_v8_2 #( .INIT (64'h0000000055554440)) present_state_FSM_FFd3_In1 ( .I0 ( S_AXI_WVALID), .I1 ( S_AXI_AWVALID), .I2 ( present_state_FSM_FFd2_14), .I3 ( present_state_FSM_FFd4_16), .I4 ( present_state_FSM_FFd3_13), .I5 (1'b0), .O ( present_state_FSM_FFd3_In) ); STATE_LOGIC_v8_2 #( .INIT (64'h0000000088880800)) present_state_FSM_FFd2_In1 ( .I0 ( S_AXI_AWVALID), .I1 ( S_AXI_WVALID), .I2 ( bready_timeout_c), .I3 ( present_state_FSM_FFd2_14), .I4 ( present_state_FSM_FFd4_16), .I5 (1'b0), .O ( present_state_FSM_FFd2_In) ); STATE_LOGIC_v8_2 #( .INIT (64'h00000000AAAA2000)) Mmux_addr_en_c_0_1 ( .I0 ( S_AXI_AWVALID), .I1 ( bready_timeout_c), .I2 ( present_state_FSM_FFd2_14), .I3 ( S_AXI_WVALID), .I4 ( present_state_FSM_FFd4_16), .I5 (1'b0), .O ( addr_en_c) ); STATE_LOGIC_v8_2 #( .INIT (64'hF5F07570F5F05500)) Mmux_w_ready_c_0_1 ( .I0 ( S_AXI_WVALID), .I1 ( bready_timeout_c), .I2 ( S_AXI_AWVALID), .I3 ( present_state_FSM_FFd3_13), .I4 ( present_state_FSM_FFd4_16), .I5 ( present_state_FSM_FFd2_14), .O ( w_ready_c) ); STATE_LOGIC_v8_2 #( .INIT (64'h88808880FFFF8880)) present_state_FSM_FFd1_In1 ( .I0 ( S_AXI_WVALID), .I1 ( bready_timeout_c), .I2 ( present_state_FSM_FFd3_13), .I3 ( present_state_FSM_FFd2_14), .I4 ( present_state_FSM_FFd1_15), .I5 ( S_AXI_BREADY), .O ( present_state_FSM_FFd1_In) ); STATE_LOGIC_v8_2 #( .INIT (64'h00000000000000A8)) Mmux_S_AXI_WR_EN_0_1 ( .I0 ( S_AXI_WVALID), .I1 ( present_state_FSM_FFd2_14), .I2 ( present_state_FSM_FFd3_13), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( NlwRenamedSignal_bvalid_c) ); STATE_LOGIC_v8_2 #( .INIT (64'h2F0F27072F0F2200)) present_state_FSM_FFd4_In1 ( .I0 ( S_AXI_WVALID), .I1 ( bready_timeout_c), .I2 ( S_AXI_AWVALID), .I3 ( present_state_FSM_FFd3_13), .I4 ( present_state_FSM_FFd4_16), .I5 ( present_state_FSM_FFd2_14), .O ( present_state_FSM_FFd4_In1_21) ); STATE_LOGIC_v8_2 #( .INIT (64'h00000000000000F8)) present_state_FSM_FFd4_In2 ( .I0 ( present_state_FSM_FFd1_15), .I1 ( S_AXI_BREADY), .I2 ( present_state_FSM_FFd4_In1_21), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( present_state_FSM_FFd4_In) ); STATE_LOGIC_v8_2 #( .INIT (64'h7535753575305500)) Mmux_aw_ready_c_0_1 ( .I0 ( S_AXI_AWVALID), .I1 ( bready_timeout_c), .I2 ( S_AXI_WVALID), .I3 ( present_state_FSM_FFd4_16), .I4 ( present_state_FSM_FFd3_13), .I5 ( present_state_FSM_FFd2_14), .O ( Mmux_aw_ready_c[0]) ); STATE_LOGIC_v8_2 #( .INIT (64'h00000000000000F8)) Mmux_aw_ready_c_0_2 ( .I0 ( present_state_FSM_FFd1_15), .I1 ( S_AXI_BREADY), .I2 ( Mmux_aw_ready_c[0]), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( aw_ready_c) ); end end endgenerate //--------------------------------------------------------------------- // AXI FULL //--------------------------------------------------------------------- generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm wire w_ready_r_8; wire w_ready_c; wire aw_ready_c; wire NlwRenamedSig_OI_bvalid_c; wire present_state_FSM_FFd1_16; wire present_state_FSM_FFd4_17; wire present_state_FSM_FFd3_18; wire present_state_FSM_FFd2_19; wire present_state_FSM_FFd4_In; wire present_state_FSM_FFd3_In; wire present_state_FSM_FFd2_In; wire present_state_FSM_FFd1_In; wire present_state_FSM_FFd2_In1_24; wire present_state_FSM_FFd4_In1_25; wire N2; wire N4; begin assign S_AXI_WREADY = w_ready_r_8, bvalid_c = NlwRenamedSig_OI_bvalid_c, S_AXI_BVALID = 1'b0; beh_vlog_ff_clr_v8_2 #( .INIT (1'b0)) aw_ready_r_2 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( aw_ready_c), .Q ( aw_ready_r) ); beh_vlog_ff_clr_v8_2 #( .INIT (1'b0)) w_ready_r ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( w_ready_c), .Q ( w_ready_r_8) ); beh_vlog_ff_pre_v8_2 #( .INIT (1'b1)) present_state_FSM_FFd4 ( .C ( S_ACLK), .D ( present_state_FSM_FFd4_In), .PRE ( S_ARESETN), .Q ( present_state_FSM_FFd4_17) ); beh_vlog_ff_clr_v8_2 #( .INIT (1'b0)) present_state_FSM_FFd3 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd3_In), .Q ( present_state_FSM_FFd3_18) ); beh_vlog_ff_clr_v8_2 #( .INIT (1'b0)) present_state_FSM_FFd2 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd2_In), .Q ( present_state_FSM_FFd2_19) ); beh_vlog_ff_clr_v8_2 #( .INIT (1'b0)) present_state_FSM_FFd1 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd1_In), .Q ( present_state_FSM_FFd1_16) ); STATE_LOGIC_v8_2 #( .INIT (64'h0000000000005540)) present_state_FSM_FFd3_In1 ( .I0 ( S_AXI_WVALID), .I1 ( present_state_FSM_FFd4_17), .I2 ( S_AXI_AWVALID), .I3 ( present_state_FSM_FFd3_18), .I4 (1'b0), .I5 (1'b0), .O ( present_state_FSM_FFd3_In) ); STATE_LOGIC_v8_2 #( .INIT (64'hBF3FBB33AF0FAA00)) Mmux_aw_ready_c_0_2 ( .I0 ( S_AXI_BREADY), .I1 ( bready_timeout_c), .I2 ( S_AXI_AWVALID), .I3 ( present_state_FSM_FFd1_16), .I4 ( present_state_FSM_FFd4_17), .I5 ( NlwRenamedSig_OI_bvalid_c), .O ( aw_ready_c) ); STATE_LOGIC_v8_2 #( .INIT (64'hAAAAAAAA20000000)) Mmux_addr_en_c_0_1 ( .I0 ( S_AXI_AWVALID), .I1 ( bready_timeout_c), .I2 ( present_state_FSM_FFd2_19), .I3 ( S_AXI_WVALID), .I4 ( w_last_c), .I5 ( present_state_FSM_FFd4_17), .O ( addr_en_c) ); STATE_LOGIC_v8_2 #( .INIT (64'h00000000000000A8)) Mmux_S_AXI_WR_EN_0_1 ( .I0 ( S_AXI_WVALID), .I1 ( present_state_FSM_FFd2_19), .I2 ( present_state_FSM_FFd3_18), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( S_AXI_WR_EN) ); STATE_LOGIC_v8_2 #( .INIT (64'h0000000000002220)) Mmux_incr_addr_c_0_1 ( .I0 ( S_AXI_WVALID), .I1 ( w_last_c), .I2 ( present_state_FSM_FFd2_19), .I3 ( present_state_FSM_FFd3_18), .I4 (1'b0), .I5 (1'b0), .O ( incr_addr_c) ); STATE_LOGIC_v8_2 #( .INIT (64'h0000000000008880)) Mmux_aw_ready_c_0_11 ( .I0 ( S_AXI_WVALID), .I1 ( w_last_c), .I2 ( present_state_FSM_FFd2_19), .I3 ( present_state_FSM_FFd3_18), .I4 (1'b0), .I5 (1'b0), .O ( NlwRenamedSig_OI_bvalid_c) ); STATE_LOGIC_v8_2 #( .INIT (64'h000000000000D5C0)) present_state_FSM_FFd2_In1 ( .I0 ( w_last_c), .I1 ( S_AXI_AWVALID), .I2 ( present_state_FSM_FFd4_17), .I3 ( present_state_FSM_FFd3_18), .I4 (1'b0), .I5 (1'b0), .O ( present_state_FSM_FFd2_In1_24) ); STATE_LOGIC_v8_2 #( .INIT (64'hFFFFAAAA08AAAAAA)) present_state_FSM_FFd2_In2 ( .I0 ( present_state_FSM_FFd2_19), .I1 ( S_AXI_AWVALID), .I2 ( bready_timeout_c), .I3 ( w_last_c), .I4 ( S_AXI_WVALID), .I5 ( present_state_FSM_FFd2_In1_24), .O ( present_state_FSM_FFd2_In) ); STATE_LOGIC_v8_2 #( .INIT (64'h00C0004000C00000)) present_state_FSM_FFd4_In1 ( .I0 ( S_AXI_AWVALID), .I1 ( w_last_c), .I2 ( S_AXI_WVALID), .I3 ( bready_timeout_c), .I4 ( present_state_FSM_FFd3_18), .I5 ( present_state_FSM_FFd2_19), .O ( present_state_FSM_FFd4_In1_25) ); STATE_LOGIC_v8_2 #( .INIT (64'h00000000FFFF88F8)) present_state_FSM_FFd4_In2 ( .I0 ( present_state_FSM_FFd1_16), .I1 ( S_AXI_BREADY), .I2 ( present_state_FSM_FFd4_17), .I3 ( S_AXI_AWVALID), .I4 ( present_state_FSM_FFd4_In1_25), .I5 (1'b0), .O ( present_state_FSM_FFd4_In) ); STATE_LOGIC_v8_2 #( .INIT (64'h0000000000000007)) Mmux_w_ready_c_0_SW0 ( .I0 ( w_last_c), .I1 ( S_AXI_WVALID), .I2 (1'b0), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( N2) ); STATE_LOGIC_v8_2 #( .INIT (64'hFABAFABAFAAAF000)) Mmux_w_ready_c_0_Q ( .I0 ( N2), .I1 ( bready_timeout_c), .I2 ( S_AXI_AWVALID), .I3 ( present_state_FSM_FFd4_17), .I4 ( present_state_FSM_FFd3_18), .I5 ( present_state_FSM_FFd2_19), .O ( w_ready_c) ); STATE_LOGIC_v8_2 #( .INIT (64'h0000000000000008)) Mmux_aw_ready_c_0_11_SW0 ( .I0 ( bready_timeout_c), .I1 ( S_AXI_WVALID), .I2 (1'b0), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O ( N4) ); STATE_LOGIC_v8_2 #( .INIT (64'h88808880FFFF8880)) present_state_FSM_FFd1_In1 ( .I0 ( w_last_c), .I1 ( N4), .I2 ( present_state_FSM_FFd2_19), .I3 ( present_state_FSM_FFd3_18), .I4 ( present_state_FSM_FFd1_16), .I5 ( S_AXI_BREADY), .O ( present_state_FSM_FFd1_In) ); end end endgenerate endmodule
module read_netlist_v8_2 #( parameter C_AXI_TYPE = 1, parameter C_ADDRB_WIDTH = 12 ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID, S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN, S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY, S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN); input S_AXI_R_LAST_INT; input S_ACLK; input S_ARESETN; input S_AXI_ARVALID; input S_AXI_RREADY; output S_AXI_INCR_ADDR; output S_AXI_ADDR_EN; output S_AXI_SINGLE_TRANS; output S_AXI_MUX_SEL; output S_AXI_R_LAST; output S_AXI_ARREADY; output S_AXI_RLAST; output S_AXI_RVALID; output S_AXI_RD_EN; input [7:0] S_AXI_ARLEN; wire present_state_FSM_FFd1_13 ; wire present_state_FSM_FFd2_14 ; wire gaxi_full_sm_outstanding_read_r_15 ; wire gaxi_full_sm_ar_ready_r_16 ; wire gaxi_full_sm_r_last_r_17 ; wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; wire gaxi_full_sm_r_valid_c ; wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; wire gaxi_full_sm_ar_ready_c ; wire gaxi_full_sm_outstanding_read_c ; wire NlwRenamedSig_OI_S_AXI_R_LAST ; wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; wire present_state_FSM_FFd2_In ; wire present_state_FSM_FFd1_In ; wire Mmux_S_AXI_R_LAST13 ; wire N01 ; wire N2 ; wire Mmux_gaxi_full_sm_ar_ready_c11 ; wire N4 ; wire N8 ; wire N9 ; wire N10 ; wire N11 ; wire N12 ; wire N13 ; assign S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST, S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16, S_AXI_RLAST = gaxi_full_sm_r_last_r_17, S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r; beh_vlog_ff_clr_v8_2 #( .INIT (1'b0)) gaxi_full_sm_outstanding_read_r ( .C (S_ACLK), .CLR(S_ARESETN), .D(gaxi_full_sm_outstanding_read_c), .Q(gaxi_full_sm_outstanding_read_r_15) ); beh_vlog_ff_ce_clr_v8_2 #( .INIT (1'b0)) gaxi_full_sm_r_valid_r ( .C (S_ACLK), .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), .CLR (S_ARESETN), .D (gaxi_full_sm_r_valid_c), .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r) ); beh_vlog_ff_clr_v8_2 #( .INIT (1'b0)) gaxi_full_sm_ar_ready_r ( .C (S_ACLK), .CLR (S_ARESETN), .D (gaxi_full_sm_ar_ready_c), .Q (gaxi_full_sm_ar_ready_r_16) ); beh_vlog_ff_ce_clr_v8_2 #( .INIT(1'b0)) gaxi_full_sm_r_last_r ( .C (S_ACLK), .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), .CLR (S_ARESETN), .D (NlwRenamedSig_OI_S_AXI_R_LAST), .Q (gaxi_full_sm_r_last_r_17) ); beh_vlog_ff_clr_v8_2 #( .INIT (1'b0)) present_state_FSM_FFd2 ( .C ( S_ACLK), .CLR ( S_ARESETN), .D ( present_state_FSM_FFd2_In), .Q ( present_state_FSM_FFd2_14) ); beh_vlog_ff_clr_v8_2 #( .INIT (1'b0)) present_state_FSM_FFd1 ( .C (S_ACLK), .CLR (S_ARESETN), .D (present_state_FSM_FFd1_In), .Q (present_state_FSM_FFd1_13) ); STATE_LOGIC_v8_2 #( .INIT (64'h000000000000000B)) S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 ( .I0 ( S_AXI_RREADY), .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I2 (1'b0), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o) ); STATE_LOGIC_v8_2 #( .INIT (64'h0000000000000008)) Mmux_S_AXI_SINGLE_TRANS11 ( .I0 (S_AXI_ARVALID), .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I2 (1'b0), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O (S_AXI_SINGLE_TRANS) ); STATE_LOGIC_v8_2 #( .INIT (64'h0000000000000004)) Mmux_S_AXI_ADDR_EN11 ( .I0 (present_state_FSM_FFd1_13), .I1 (S_AXI_ARVALID), .I2 (1'b0), .I3 (1'b0), .I4 (1'b0), .I5 (1'b0), .O (S_AXI_ADDR_EN) ); STATE_LOGIC_v8_2 #( .INIT (64'hECEE2022EEEE2022)) present_state_FSM_FFd2_In1 ( .I0 ( S_AXI_ARVALID), .I1 ( present_state_FSM_FFd1_13), .I2 ( S_AXI_RREADY), .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I4 ( present_state_FSM_FFd2_14), .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .O ( present_state_FSM_FFd2_In) ); STATE_LOGIC_v8_2 #( .INIT (64'h0000000044440444)) Mmux_S_AXI_R_LAST131 ( .I0 ( present_state_FSM_FFd1_13), .I1 ( S_AXI_ARVALID), .I2 ( present_state_FSM_FFd2_14), .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I4 ( S_AXI_RREADY), .I5 (1'b0), .O ( Mmux_S_AXI_R_LAST13) ); STATE_LOGIC_v8_2 #( .INIT (64'h4000FFFF40004000)) Mmux_S_AXI_INCR_ADDR11 ( .I0 ( S_AXI_R_LAST_INT), .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), .I2 ( present_state_FSM_FFd2_14), .I3 ( present_state_FSM_FFd1_13), .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I5 ( Mmux_S_AXI_R_LAST13), .O ( S_AXI_INCR_ADDR) ); STATE_LOGIC_v8_2 #( .INIT (64'h00000000000000FE)) S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 ( .I0 ( S_AXI_ARLEN[2]), .I1 ( S_AXI_ARLEN[1]), .I2 ( S_AXI_ARLEN[0]), .I3 ( 1'b0), .I4 ( 1'b0), .I5 ( 1'b0), .O ( N01) ); STATE_LOGIC_v8_2 #( .INIT (64'h0000000000000001)) S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q ( .I0 ( S_AXI_ARLEN[7]), .I1 ( S_AXI_ARLEN[6]), .I2 ( S_AXI_ARLEN[5]), .I3 ( S_AXI_ARLEN[4]), .I4 ( S_AXI_ARLEN[3]), .I5 ( N01), .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o) ); STATE_LOGIC_v8_2 #( .INIT (64'h0000000000000007)) Mmux_gaxi_full_sm_outstanding_read_c1_SW0 ( .I0 ( S_AXI_ARVALID), .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I2 ( 1'b0), .I3 ( 1'b0), .I4 ( 1'b0), .I5 ( 1'b0), .O ( N2) ); STATE_LOGIC_v8_2 #( .INIT (64'h0020000002200200)) Mmux_gaxi_full_sm_outstanding_read_c1 ( .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I1 ( S_AXI_RREADY), .I2 ( present_state_FSM_FFd1_13), .I3 ( present_state_FSM_FFd2_14), .I4 ( gaxi_full_sm_outstanding_read_r_15), .I5 ( N2), .O ( gaxi_full_sm_outstanding_read_c) ); STATE_LOGIC_v8_2 #( .INIT (64'h0000000000004555)) Mmux_gaxi_full_sm_ar_ready_c12 ( .I0 ( S_AXI_ARVALID), .I1 ( S_AXI_RREADY), .I2 ( present_state_FSM_FFd2_14), .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I4 ( 1'b0), .I5 ( 1'b0), .O ( Mmux_gaxi_full_sm_ar_ready_c11) ); STATE_LOGIC_v8_2 #( .INIT (64'h00000000000000EF)) Mmux_S_AXI_R_LAST11_SW0 ( .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I1 ( S_AXI_RREADY), .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I3 ( 1'b0), .I4 ( 1'b0), .I5 ( 1'b0), .O ( N4) ); STATE_LOGIC_v8_2 #( .INIT (64'hFCAAFC0A00AA000A)) Mmux_S_AXI_R_LAST11 ( .I0 ( S_AXI_ARVALID), .I1 ( gaxi_full_sm_outstanding_read_r_15), .I2 ( present_state_FSM_FFd2_14), .I3 ( present_state_FSM_FFd1_13), .I4 ( N4), .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), .O ( gaxi_full_sm_r_valid_c) ); STATE_LOGIC_v8_2 #( .INIT (64'h00000000AAAAAA08)) S_AXI_MUX_SEL1 ( .I0 (present_state_FSM_FFd1_13), .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I2 (S_AXI_RREADY), .I3 (present_state_FSM_FFd2_14), .I4 (gaxi_full_sm_outstanding_read_r_15), .I5 (1'b0), .O (S_AXI_MUX_SEL) ); STATE_LOGIC_v8_2 #( .INIT (64'hF3F3F755A2A2A200)) Mmux_S_AXI_RD_EN11 ( .I0 ( present_state_FSM_FFd1_13), .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I2 ( S_AXI_RREADY), .I3 ( gaxi_full_sm_outstanding_read_r_15), .I4 ( present_state_FSM_FFd2_14), .I5 ( S_AXI_ARVALID), .O ( S_AXI_RD_EN) ); beh_vlog_muxf7_v8_2 present_state_FSM_FFd1_In3 ( .I0 ( N8), .I1 ( N9), .S ( present_state_FSM_FFd1_13), .O ( present_state_FSM_FFd1_In) ); STATE_LOGIC_v8_2 #( .INIT (64'h000000005410F4F0)) present_state_FSM_FFd1_In3_F ( .I0 ( S_AXI_RREADY), .I1 ( present_state_FSM_FFd2_14), .I2 ( S_AXI_ARVALID), .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I5 ( 1'b0), .O ( N8) ); STATE_LOGIC_v8_2 #( .INIT (64'h0000000072FF7272)) present_state_FSM_FFd1_In3_G ( .I0 ( present_state_FSM_FFd2_14), .I1 ( S_AXI_R_LAST_INT), .I2 ( gaxi_full_sm_outstanding_read_r_15), .I3 ( S_AXI_RREADY), .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I5 ( 1'b0), .O ( N9) ); beh_vlog_muxf7_v8_2 Mmux_gaxi_full_sm_ar_ready_c14 ( .I0 ( N10), .I1 ( N11), .S ( present_state_FSM_FFd1_13), .O ( gaxi_full_sm_ar_ready_c) ); STATE_LOGIC_v8_2 #( .INIT (64'h00000000FFFF88A8)) Mmux_gaxi_full_sm_ar_ready_c14_F ( .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I1 ( S_AXI_RREADY), .I2 ( present_state_FSM_FFd2_14), .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I4 ( Mmux_gaxi_full_sm_ar_ready_c11), .I5 ( 1'b0), .O ( N10) ); STATE_LOGIC_v8_2 #( .INIT (64'h000000008D008D8D)) Mmux_gaxi_full_sm_ar_ready_c14_G ( .I0 ( present_state_FSM_FFd2_14), .I1 ( S_AXI_R_LAST_INT), .I2 ( gaxi_full_sm_outstanding_read_r_15), .I3 ( S_AXI_RREADY), .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I5 ( 1'b0), .O ( N11) ); beh_vlog_muxf7_v8_2 Mmux_S_AXI_R_LAST1 ( .I0 ( N12), .I1 ( N13), .S ( present_state_FSM_FFd1_13), .O ( NlwRenamedSig_OI_S_AXI_R_LAST) ); STATE_LOGIC_v8_2 #( .INIT (64'h0000000088088888)) Mmux_S_AXI_R_LAST1_F ( .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), .I1 ( S_AXI_ARVALID), .I2 ( present_state_FSM_FFd2_14), .I3 ( S_AXI_RREADY), .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I5 ( 1'b0), .O ( N12) ); STATE_LOGIC_v8_2 #( .INIT (64'h00000000E400E4E4)) Mmux_S_AXI_R_LAST1_G ( .I0 ( present_state_FSM_FFd2_14), .I1 ( gaxi_full_sm_outstanding_read_r_15), .I2 ( S_AXI_R_LAST_INT), .I3 ( S_AXI_RREADY), .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), .I5 ( 1'b0), .O ( N13) ); endmodule
module blk_mem_axi_write_wrapper_beh_v8_2 # ( // AXI Interface related parameters start here parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full; parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE; parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM; parameter C_WRITE_DEPTH_A = 0, parameter C_AXI_AWADDR_WIDTH = 32, parameter C_ADDRA_WIDTH = 12, parameter C_AXI_WDATA_WIDTH = 32, parameter C_HAS_AXI_ID = 0, parameter C_AXI_ID_WIDTH = 4, // AXI OUTSTANDING WRITES parameter C_AXI_OS_WR = 2 ) ( // AXI Global Signals input S_ACLK, input S_ARESETN, // AXI Full/Lite Slave Write Channel (write side) input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR, input [8-1:0] S_AXI_AWLEN, input [2:0] S_AXI_AWSIZE, input [1:0] S_AXI_AWBURST, input S_AXI_AWVALID, output S_AXI_AWREADY, input S_AXI_WVALID, output S_AXI_WREADY, output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0, output S_AXI_BVALID, input S_AXI_BREADY, // Signals for BMG interface output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT, output S_AXI_WR_EN ); localparam FLOP_DELAY = 100; // 100 ps localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0: ((C_AXI_WDATA_WIDTH==16)?1: ((C_AXI_WDATA_WIDTH==32)?2: ((C_AXI_WDATA_WIDTH==64)?3: ((C_AXI_WDATA_WIDTH==128)?4: ((C_AXI_WDATA_WIDTH==256)?5:0)))))); wire bvalid_c ; reg bready_timeout_c = 0; wire [1:0] bvalid_rd_cnt_c; reg bvalid_r = 0; reg [2:0] bvalid_count_r = 0; reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0; reg [1:0] bvalid_wr_cnt_r = 0; reg [1:0] bvalid_rd_cnt_r = 0; wire w_last_c ; wire addr_en_c ; wire incr_addr_c ; wire aw_ready_r ; wire dec_alen_c ; reg bvalid_d1_c = 0; reg [7:0] awlen_cntr_r = 0; reg [7:0] awlen_int = 0; reg [1:0] awburst_int = 0; integer total_bytes = 0; integer wrap_boundary = 0; integer wrap_base_addr = 0; integer num_of_bytes_c = 0; integer num_of_bytes_r = 0; // Array to store BIDs reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ; wire S_AXI_BVALID_axi_wr_fsm; //------------------------------------- //AXI WRITE FSM COMPONENT INSTANTIATION //------------------------------------- write_netlist_v8_2 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm ( .S_ACLK(S_ACLK), .S_ARESETN(S_ARESETN), .S_AXI_AWVALID(S_AXI_AWVALID), .aw_ready_r(aw_ready_r), .S_AXI_WVALID(S_AXI_WVALID), .S_AXI_WREADY(S_AXI_WREADY), .S_AXI_BREADY(S_AXI_BREADY), .S_AXI_WR_EN(S_AXI_WR_EN), .w_last_c(w_last_c), .bready_timeout_c(bready_timeout_c), .addr_en_c(addr_en_c), .incr_addr_c(incr_addr_c), .bvalid_c(bvalid_c), .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) ); //Wrap Address boundary calculation always@(*) begin num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0); total_bytes = (num_of_bytes_r)*(awlen_int+1); wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes); wrap_boundary = wrap_base_addr+total_bytes; end //------------------------------------------------------------------------- // BMG address generation //------------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin awaddr_reg <= 0; num_of_bytes_r <= 0; awburst_int <= 0; end else begin if (addr_en_c == 1'b1) begin awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ; num_of_bytes_r <= num_of_bytes_c; awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01); end else if (incr_addr_c == 1'b1) begin if (awburst_int == 2'b10) begin if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin awaddr_reg <= wrap_base_addr; end else begin awaddr_reg <= awaddr_reg + num_of_bytes_r; end end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin awaddr_reg <= awaddr_reg + num_of_bytes_r; end end end end assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg); //------------------------------------------------------------------------- // AXI wlast generation //------------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin awlen_cntr_r <= 0; awlen_int <= 0; end else begin if (addr_en_c == 1'b1) begin awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ; awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ; end else if (dec_alen_c == 1'b1) begin awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ; end end end assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0; assign dec_alen_c = (incr_addr_c | w_last_c); //------------------------------------------------------------------------- // Generation of bvalid counter for outstanding transactions //------------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin bvalid_count_r <= 0; end else begin // bvalid_count_r generation if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin bvalid_count_r <= #FLOP_DELAY bvalid_count_r ; end else if (bvalid_c == 1'b1) begin bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ; end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ; end end end //------------------------------------------------------------------------- // Generation of bvalid when BID is used //------------------------------------------------------------------------- generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin bvalid_r <= 0; bvalid_d1_c <= 0; end else begin // Delay the generation o bvalid_r for generation for BID bvalid_d1_c <= bvalid_c; //external bvalid signal generation if (bvalid_d1_c == 1'b1) begin bvalid_r <= #FLOP_DELAY 1'b1 ; end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin bvalid_r <= #FLOP_DELAY 0 ; end end end end endgenerate //------------------------------------------------------------------------- // Generation of bvalid when BID is not used //------------------------------------------------------------------------- generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin bvalid_r <= 0; end else begin //external bvalid signal generation if (bvalid_c == 1'b1) begin bvalid_r <= #FLOP_DELAY 1'b1 ; end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin bvalid_r <= #FLOP_DELAY 0 ; end end end end endgenerate //------------------------------------------------------------------------- // Generation of Bready timeout //------------------------------------------------------------------------- always @(bvalid_count_r) begin // bready_timeout_c generation if(bvalid_count_r == C_AXI_OS_WR-1) begin bready_timeout_c <= 1'b1; end else begin bready_timeout_c <= 1'b0; end end //------------------------------------------------------------------------- // Generation of BID //------------------------------------------------------------------------- generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin bvalid_wr_cnt_r <= 0; bvalid_rd_cnt_r <= 0; end else begin // STORE AWID IN AN ARRAY if(bvalid_c == 1'b1) begin bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1; end // generate BID FROM AWID ARRAY bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ; S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c]; end end assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r; //------------------------------------------------------------------------- // Storing AWID for generation of BID //------------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if(S_ARESETN == 1'b1) begin axi_bid_array[0] = 0; axi_bid_array[1] = 0; axi_bid_array[2] = 0; axi_bid_array[3] = 0; end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID; end end end endgenerate assign S_AXI_BVALID = bvalid_r; assign S_AXI_AWREADY = aw_ready_r; endmodule
module blk_mem_axi_read_wrapper_beh_v8_2 # ( //// AXI Interface related parameters start here parameter C_INTERFACE_TYPE = 0, parameter C_AXI_TYPE = 0, parameter C_AXI_SLAVE_TYPE = 0, parameter C_MEMORY_TYPE = 0, parameter C_WRITE_WIDTH_A = 4, parameter C_WRITE_DEPTH_A = 32, parameter C_ADDRA_WIDTH = 12, parameter C_AXI_PIPELINE_STAGES = 0, parameter C_AXI_ARADDR_WIDTH = 12, parameter C_HAS_AXI_ID = 0, parameter C_AXI_ID_WIDTH = 4, parameter C_ADDRB_WIDTH = 12 ) ( //// AXI Global Signals input S_ACLK, input S_ARESETN, //// AXI Full/Lite Slave Read (Read side) input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR, input [7:0] S_AXI_ARLEN, input [2:0] S_AXI_ARSIZE, input [1:0] S_AXI_ARBURST, input S_AXI_ARVALID, output S_AXI_ARREADY, output S_AXI_RLAST, output S_AXI_RVALID, input S_AXI_RREADY, input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID, output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0, //// AXI Full/Lite Read Address Signals to BRAM output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT, output S_AXI_RD_EN ); localparam FLOP_DELAY = 100; // 100 ps localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0: ((C_WRITE_WIDTH_A==16)?1: ((C_WRITE_WIDTH_A==32)?2: ((C_WRITE_WIDTH_A==64)?3: ((C_WRITE_WIDTH_A==128)?4: ((C_WRITE_WIDTH_A==256)?5:0)))))); reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0; wire addr_en_c; wire rd_en_c; wire incr_addr_c; wire single_trans_c; wire dec_alen_c; wire mux_sel_c; wire r_last_c; wire r_last_int_c; wire [C_ADDRB_WIDTH-1 : 0] araddr_out; reg [7:0] arlen_int_r=0; reg [7:0] arlen_cntr=8'h01; reg [1:0] arburst_int_c=0; reg [1:0] arburst_int_r=0; reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0; integer num_of_bytes_c = 0; integer total_bytes = 0; integer num_of_bytes_r = 0; integer wrap_base_addr_r = 0; integer wrap_boundary_r = 0; reg [7:0] arlen_int_c=0; integer total_bytes_c = 0; integer wrap_base_addr_c = 0; integer wrap_boundary_c = 0; assign dec_alen_c = incr_addr_c | r_last_int_c; read_netlist_v8_2 #(.C_AXI_TYPE (1), .C_ADDRB_WIDTH (C_ADDRB_WIDTH)) axi_read_fsm ( .S_AXI_INCR_ADDR(incr_addr_c), .S_AXI_ADDR_EN(addr_en_c), .S_AXI_SINGLE_TRANS(single_trans_c), .S_AXI_MUX_SEL(mux_sel_c), .S_AXI_R_LAST(r_last_c), .S_AXI_R_LAST_INT(r_last_int_c), //// AXI Global Signals .S_ACLK(S_ACLK), .S_ARESETN(S_ARESETN), //// AXI Full/Lite Slave Read (Read side) .S_AXI_ARLEN(S_AXI_ARLEN), .S_AXI_ARVALID(S_AXI_ARVALID), .S_AXI_ARREADY(S_AXI_ARREADY), .S_AXI_RLAST(S_AXI_RLAST), .S_AXI_RVALID(S_AXI_RVALID), .S_AXI_RREADY(S_AXI_RREADY), //// AXI Full/Lite Read Address Signals to BRAM .S_AXI_RD_EN(rd_en_c) ); always@(*) begin num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0); total_bytes = (num_of_bytes_r)*(arlen_int_r+1); wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes); wrap_boundary_r = wrap_base_addr_r+total_bytes; //////// combinatorial from interface arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN); total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1); wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c); wrap_boundary_c = wrap_base_addr_c+total_bytes_c; arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1); end ////------------------------------------------------------------------------- //// BMG address generation ////------------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin araddr_reg <= 0; arburst_int_r <= 0; num_of_bytes_r <= 0; end else begin if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin arburst_int_r <= arburst_int_c; num_of_bytes_r <= num_of_bytes_c; if (arburst_int_c == 2'b10) begin if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin araddr_reg <= wrap_base_addr_c; end else begin araddr_reg <= S_AXI_ARADDR + num_of_bytes_c; end end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin araddr_reg <= S_AXI_ARADDR + num_of_bytes_c; end end else if (addr_en_c == 1'b1) begin araddr_reg <= S_AXI_ARADDR; num_of_bytes_r <= num_of_bytes_c; arburst_int_r <= arburst_int_c; end else if (incr_addr_c == 1'b1) begin if (arburst_int_r == 2'b10) begin if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin araddr_reg <= wrap_base_addr_r; end else begin araddr_reg <= araddr_reg + num_of_bytes_r; end end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin araddr_reg <= araddr_reg + num_of_bytes_r; end end end end assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg); ////----------------------------------------------------------------------- //// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM ////----------------------------------------------------------------------- always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin arlen_cntr <= 8'h01; arlen_int_r <= 0; end else begin if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; arlen_cntr <= S_AXI_ARLEN - 1'b1; end else if (addr_en_c == 1'b1) begin arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; end else if (dec_alen_c == 1'b1) begin arlen_cntr <= arlen_cntr - 1'b1 ; end else begin arlen_cntr <= arlen_cntr; end end end assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0; ////------------------------------------------------------------------------ //// AXI FULL FSM //// Mux Selection of ARADDR //// ARADDR is driven out from the read fsm based on the mux_sel_c //// Based on mux_sel either ARADDR is given out or the latched ARADDR is //// given out to BRAM ////------------------------------------------------------------------------ assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out; ////------------------------------------------------------------------------ //// Assign output signals - AXI FULL FSM ////------------------------------------------------------------------------ assign S_AXI_RD_EN = rd_en_c; generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r always @(posedge S_ACLK or S_ARESETN) begin if (S_ARESETN == 1'b1) begin S_AXI_RID <= 0; ar_id_r <= 0; end else begin if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin S_AXI_RID <= S_AXI_ARID; ar_id_r <= S_AXI_ARID; end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin ar_id_r <= S_AXI_ARID; end else if (rd_en_c == 1'b1) begin S_AXI_RID <= ar_id_r; end end end end endgenerate endmodule
module blk_mem_axi_regs_fwd_v8_2 #(parameter C_DATA_WIDTH = 8 )( input ACLK, input ARESET, input S_VALID, output S_READY, input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, output M_VALID, input M_READY, output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA ); reg [C_DATA_WIDTH-1:0] STORAGE_DATA; wire S_READY_I; reg M_VALID_I; reg [1:0] ARESET_D; //assign local signal to its output signal assign S_READY = S_READY_I; assign M_VALID = M_VALID_I; always @(posedge ACLK) begin ARESET_D <= {ARESET_D[0], ARESET}; end //Save payload data whenever we have a transaction on the slave side always @(posedge ACLK or ARESET) begin if (ARESET == 1'b1) begin STORAGE_DATA <= 0; end else begin if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin STORAGE_DATA <= S_PAYLOAD_DATA; end end end always @(posedge ACLK) begin M_PAYLOAD_DATA = STORAGE_DATA; end //M_Valid set to high when we have a completed transfer on slave side //Is removed on a M_READY except if we have a new transfer on the slave side always @(posedge ACLK or ARESET_D) begin if (ARESET_D != 2'b00) begin M_VALID_I <= 1'b0; end else begin if (S_VALID == 1'b1) begin //Always set M_VALID_I when slave side is valid M_VALID_I <= 1'b1; end else if (M_READY == 1'b1 ) begin //Clear (or keep) when no slave side is valid but master side is ready M_VALID_I <= 1'b0; end end end //Slave Ready is either when Master side drives M_READY or we have space in our storage data assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D)); endmodule
module BLK_MEM_GEN_v8_2_output_stage #(parameter C_FAMILY = "virtex7", parameter C_XDEVICEFAMILY = "virtex7", parameter C_RST_TYPE = "SYNC", parameter C_HAS_RST = 0, parameter C_RSTRAM = 0, parameter C_RST_PRIORITY = "CE", parameter C_INIT_VAL = "0", parameter C_HAS_EN = 0, parameter C_HAS_REGCE = 0, parameter C_DATA_WIDTH = 32, parameter C_ADDRB_WIDTH = 10, parameter C_HAS_MEM_OUTPUT_REGS = 0, parameter C_USE_SOFTECC = 0, parameter C_USE_ECC = 0, parameter NUM_STAGES = 1, parameter C_EN_ECC_PIPE = 0, parameter FLOP_DELAY = 100 ) ( input CLK, input RST, input EN, input REGCE, input [C_DATA_WIDTH-1:0] DIN_I, output reg [C_DATA_WIDTH-1:0] DOUT, input SBITERR_IN_I, input DBITERR_IN_I, output reg SBITERR, output reg DBITERR, input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I, input ECCPIPECE, output reg [C_ADDRB_WIDTH-1:0] RDADDRECC ); //****************************** // Port and Generic Definitions //****************************** ////////////////////////////////////////////////////////////////////////// // Generic Definitions ////////////////////////////////////////////////////////////////////////// // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following // options are available - "spartan3", "spartan6", // "virtex4", "virtex5", "virtex6" and "virtex6l". // C_RST_TYPE : Type of reset - Synchronous or Asynchronous // C_HAS_RST : Determines the presence of the RST port // C_RSTRAM : Determines if special reset behavior is used // C_RST_PRIORITY : Determines the priority between CE and SR // C_INIT_VAL : Initialization value // C_HAS_EN : Determines the presence of the EN port // C_HAS_REGCE : Determines the presence of the REGCE port // C_DATA_WIDTH : Memory write/read width // C_ADDRB_WIDTH : Width of the ADDRB input port // C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output // of the RAM primitive // C_USE_SOFTECC : Determines if the Soft ECC feature is used or // not. Only applicable Spartan-6 // C_USE_ECC : Determines if the ECC feature is used or // not. Only applicable for V5 and V6 // NUM_STAGES : Determines the number of output stages // FLOP_DELAY : Constant delay for register assignments ////////////////////////////////////////////////////////////////////////// // Port Definitions ////////////////////////////////////////////////////////////////////////// // CLK : Clock to synchronize all read and write operations // RST : Reset input to reset memory outputs to a user-defined // reset state // EN : Enable all read and write operations // REGCE : Register Clock Enable to control each pipeline output // register stages // DIN : Data input to the Output stage. // DOUT : Final Data output // SBITERR_IN : SBITERR input signal to the Output stage. // SBITERR : Final SBITERR Output signal. // DBITERR_IN : DBITERR input signal to the Output stage. // DBITERR : Final DBITERR Output signal. // RDADDRECC_IN : RDADDRECC input signal to the Output stage. // RDADDRECC : Final RDADDRECC Output signal. ////////////////////////////////////////////////////////////////////////// // Fix for CR-509792 localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1; // Declare the pipeline registers // (includes mem output reg, mux pipeline stages, and mux output reg) reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs; reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs; reg [REG_STAGES-1:0] sbiterr_regs; reg [REG_STAGES-1:0] dbiterr_regs; reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL; reg [C_DATA_WIDTH-1:0] init_val ; //********************************************* // Wire off optional inputs based on parameters //********************************************* wire en_i; wire regce_i; wire rst_i; // Internal signals reg [C_DATA_WIDTH-1:0] DIN; reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN; reg SBITERR_IN; reg DBITERR_IN; // Internal enable for output registers is tied to user EN or '1' depending // on parameters assign en_i = (C_HAS_EN==0 || EN); // Internal register enable for output registers is tied to user REGCE, EN or // '1' depending on parameters // For V4 ECC, REGCE is always 1 // Virtex-4 ECC Not Yet Supported assign regce_i = ((C_HAS_REGCE==1) && REGCE) || ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN)); //Internal SRR is tied to user RST or '0' depending on parameters assign rst_i = (C_HAS_RST==1) && RST; //**************************************************** // Power on: load up the output registers and latches //**************************************************** initial begin if (!($sscanf(init_str, "%h", init_val))) begin init_val = 0; end DOUT = init_val; RDADDRECC = 0; SBITERR = 1'b0; DBITERR = 1'b0; DIN = {(C_DATA_WIDTH){1'b0}}; RDADDRECC_IN = 0; SBITERR_IN = 0; DBITERR_IN = 0; // This will be one wider than need, but 0 is an error out_regs = {(REG_STAGES+1){init_val}}; rdaddrecc_regs = 0; sbiterr_regs = {(REG_STAGES+1){1'b0}}; dbiterr_regs = {(REG_STAGES+1){1'b0}}; end //*********************************************** // NUM_STAGES = 0 (No output registers. RAM only) //*********************************************** generate if (NUM_STAGES == 0) begin : zero_stages always @* begin DOUT = DIN; RDADDRECC = RDADDRECC_IN; SBITERR = SBITERR_IN; DBITERR = DBITERR_IN; end end endgenerate generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg always @* begin DIN = DIN_I; SBITERR_IN = SBITERR_IN_I; DBITERR_IN = DBITERR_IN_I; RDADDRECC_IN = RDADDRECC_IN_I; end end endgenerate generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg always @(posedge CLK) begin if(ECCPIPECE == 1) begin DIN <= #FLOP_DELAY DIN_I; SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I; DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I; RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I; end end end endgenerate //*********************************************** // NUM_STAGES = 1 // (Mem Output Reg only or Mux Output Reg only) //*********************************************** // Possible valid combinations: // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1) // +-----------------------------------------+ // | C_RSTRAM_* | Reset Behavior | // +----------------+------------------------+ // | 0 | Normal Behavior | // +----------------+------------------------+ // | 1 | Special Behavior | // +----------------+------------------------+ // // Normal = REGCE gates reset, as in the case of all families except S3ADSP. // Special = EN gates reset, as in the case of S3ADSP. generate if (NUM_STAGES == 1 && (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) || C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0)) begin : one_stages_norm always @(posedge CLK) begin if (C_RST_PRIORITY == "CE") begin //REGCE has priority if (regce_i && rst_i) begin DOUT <= #FLOP_DELAY init_val; RDADDRECC <= #FLOP_DELAY 0; SBITERR <= #FLOP_DELAY 1'b0; DBITERR <= #FLOP_DELAY 1'b0; end else if (regce_i) begin DOUT <= #FLOP_DELAY DIN; RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; SBITERR <= #FLOP_DELAY SBITERR_IN; DBITERR <= #FLOP_DELAY DBITERR_IN; end //Output signal assignments end else begin //RST has priority if (rst_i) begin DOUT <= #FLOP_DELAY init_val; RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; SBITERR <= #FLOP_DELAY 1'b0; DBITERR <= #FLOP_DELAY 1'b0; end else if (regce_i) begin DOUT <= #FLOP_DELAY DIN; RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; SBITERR <= #FLOP_DELAY SBITERR_IN; DBITERR <= #FLOP_DELAY DBITERR_IN; end //Output signal assignments end //end Priority conditions end //end RST Type conditions end //end one_stages_norm generate statement endgenerate // Special Reset Behavior for S3ADSP generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp")) begin : one_stage_splbhv always @(posedge CLK) begin if (en_i && rst_i) begin DOUT <= #FLOP_DELAY init_val; end else if (regce_i && !rst_i) begin DOUT <= #FLOP_DELAY DIN; end //Output signal assignments end //end CLK end //end one_stage_splbhv generate statement endgenerate //************************************************************ // NUM_STAGES > 1 // Mem Output Reg + Mux Output Reg // or // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg // or // Mux Pipeline Stages (>0) + Mux Output Reg //************************************************************* generate if (NUM_STAGES > 1) begin : multi_stage //Asynchronous Reset always @(posedge CLK) begin if (C_RST_PRIORITY == "CE") begin //REGCE has priority if (regce_i && rst_i) begin DOUT <= #FLOP_DELAY init_val; RDADDRECC <= #FLOP_DELAY 0; SBITERR <= #FLOP_DELAY 1'b0; DBITERR <= #FLOP_DELAY 1'b0; end else if (regce_i) begin DOUT <= #FLOP_DELAY out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; end //Output signal assignments end else begin //RST has priority if (rst_i) begin DOUT <= #FLOP_DELAY init_val; RDADDRECC <= #FLOP_DELAY 0; SBITERR <= #FLOP_DELAY 1'b0; DBITERR <= #FLOP_DELAY 1'b0; end else if (regce_i) begin DOUT <= #FLOP_DELAY out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; end //Output signal assignments end //end Priority conditions // Shift the data through the output stages if (en_i) begin out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN; rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN; sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN; dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN; end end //end CLK end //end multi_stage generate statement endgenerate endmodule
module BLK_MEM_GEN_v8_2_softecc_output_reg_stage #(parameter C_DATA_WIDTH = 32, parameter C_ADDRB_WIDTH = 10, parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, parameter C_USE_SOFTECC = 0, parameter FLOP_DELAY = 100 ) ( input CLK, input [C_DATA_WIDTH-1:0] DIN, output reg [C_DATA_WIDTH-1:0] DOUT, input SBITERR_IN, input DBITERR_IN, output reg SBITERR, output reg DBITERR, input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN, output reg [C_ADDRB_WIDTH-1:0] RDADDRECC ); //****************************** // Port and Generic Definitions //****************************** ////////////////////////////////////////////////////////////////////////// // Generic Definitions ////////////////////////////////////////////////////////////////////////// // C_DATA_WIDTH : Memory write/read width // C_ADDRB_WIDTH : Width of the ADDRB input port // C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output // of the RAM primitive // C_USE_SOFTECC : Determines if the Soft ECC feature is used or // not. Only applicable Spartan-6 // FLOP_DELAY : Constant delay for register assignments ////////////////////////////////////////////////////////////////////////// // Port Definitions ////////////////////////////////////////////////////////////////////////// // CLK : Clock to synchronize all read and write operations // DIN : Data input to the Output stage. // DOUT : Final Data output // SBITERR_IN : SBITERR input signal to the Output stage. // SBITERR : Final SBITERR Output signal. // DBITERR_IN : DBITERR input signal to the Output stage. // DBITERR : Final DBITERR Output signal. // RDADDRECC_IN : RDADDRECC input signal to the Output stage. // RDADDRECC : Final RDADDRECC Output signal. ////////////////////////////////////////////////////////////////////////// reg [C_DATA_WIDTH-1:0] dout_i = 0; reg sbiterr_i = 0; reg dbiterr_i = 0; reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0; //*********************************************** // NO OUTPUT REGISTERS. //*********************************************** generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage always @* begin DOUT = DIN; RDADDRECC = RDADDRECC_IN; SBITERR = SBITERR_IN; DBITERR = DBITERR_IN; end end endgenerate //*********************************************** // WITH OUTPUT REGISTERS. //*********************************************** generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage always @(posedge CLK) begin dout_i <= #FLOP_DELAY DIN; rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN; sbiterr_i <= #FLOP_DELAY SBITERR_IN; dbiterr_i <= #FLOP_DELAY DBITERR_IN; end always @* begin DOUT = dout_i; RDADDRECC = rdaddrecc_i; SBITERR = sbiterr_i; DBITERR = dbiterr_i; end //end always end //end in_or_out_stage generate statement endgenerate endmodule
module //*************************************************************** // Port A assign rsta_outp_stage = RSTA & (~SLEEP); BLK_MEM_GEN_v8_2_output_stage #(.C_FAMILY (C_FAMILY), .C_XDEVICEFAMILY (C_XDEVICEFAMILY), .C_RST_TYPE ("SYNC"), .C_HAS_RST (C_HAS_RSTA), .C_RSTRAM (C_RSTRAM_A), .C_RST_PRIORITY (C_RST_PRIORITY_A), .C_INIT_VAL (C_INITA_VAL), .C_HAS_EN (C_HAS_ENA), .C_HAS_REGCE (C_HAS_REGCEA), .C_DATA_WIDTH (C_READ_WIDTH_A), .C_ADDRB_WIDTH (C_ADDRB_WIDTH), .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A), .C_USE_SOFTECC (C_USE_SOFTECC), .C_USE_ECC (C_USE_ECC), .NUM_STAGES (NUM_OUTPUT_STAGES_A), .C_EN_ECC_PIPE (0), .FLOP_DELAY (FLOP_DELAY)) reg_a (.CLK (CLKA), .RST (rsta_outp_stage),//(RSTA), .EN (ENA), .REGCE (REGCEA), .DIN_I (memory_out_a), .DOUT (DOUTA), .SBITERR_IN_I (1'b0), .DBITERR_IN_I (1'b0), .SBITERR (), .DBITERR (), .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}), .ECCPIPECE (1'b0), .RDADDRECC () ); assign rstb_outp_stage = RSTB & (~SLEEP); // Port B BLK_MEM_GEN_v8_2_output_stage #(.C_FAMILY (C_FAMILY), .C_XDEVICEFAMILY (C_XDEVICEFAMILY), .C_RST_TYPE ("SYNC"), .C_HAS_RST (C_HAS_RSTB), .C_RSTRAM (C_RSTRAM_B), .C_RST_PRIORITY (C_RST_PRIORITY_B), .C_INIT_VAL (C_INITB_VAL), .C_HAS_EN (C_HAS_ENB), .C_HAS_REGCE (C_HAS_REGCEB), .C_DATA_WIDTH (C_READ_WIDTH_B), .C_ADDRB_WIDTH (C_ADDRB_WIDTH), .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B), .C_USE_SOFTECC (C_USE_SOFTECC), .C_USE_ECC (C_USE_ECC), .NUM_STAGES (NUM_OUTPUT_STAGES_B), .C_EN_ECC_PIPE (C_EN_ECC_PIPE), .FLOP_DELAY (FLOP_DELAY)) reg_b (.CLK (CLKB), .RST (rstb_outp_stage),//(RSTB), .EN (ENB), .REGCE (REGCEB), .DIN_I (memory_out_b), .DOUT (dout_i), .SBITERR_IN_I (sbiterr_in), .DBITERR_IN_I (dbiterr_in), .SBITERR (sbiterr_i), .DBITERR (dbiterr_i), .RDADDRECC_IN_I (rdaddrecc_in), .ECCPIPECE (ECCPIPECE), .RDADDRECC (rdaddrecc_i) ); //*************************************************************** // Instantiate the Input and Output register stages //*************************************************************** BLK_MEM_GEN_v8_2_softecc_output_reg_stage #(.C_DATA_WIDTH (C_READ_WIDTH_B), .C_ADDRB_WIDTH (C_ADDRB_WIDTH), .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), .C_USE_SOFTECC (C_USE_SOFTECC), .FLOP_DELAY (FLOP_DELAY)) has_softecc_output_reg_stage (.CLK (CLKB), .DIN (dout_i), .DOUT (DOUTB), .SBITERR_IN (sbiterr_i), .DBITERR_IN (dbiterr_i), .SBITERR (sbiterr_sdp), .DBITERR (dbiterr_sdp), .RDADDRECC_IN (rdaddrecc_i), .RDADDRECC (rdaddrecc_sdp) ); //**************************************************** // Synchronous collision checks //**************************************************** // CR 780544 : To make verilog model's collison warnings in consistant with // vhdl model, the non-blocking assignments are replaced with blocking // assignments. generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll always @(posedge CLKA) begin // Possible collision if both are enabled and the addresses match if (ena_i && enb_i) begin if (wea_i || web_i) begin is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i); end else begin is_collision = 0; end end else begin is_collision = 0; end // If the write port is in READ_FIRST mode, there is no collision if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin is_collision = 0; end if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin is_collision = 0; end // Only flag if one of the accesses is a write if (is_collision && (wea_i || web_i)) begin $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", C_CORENAME, $time); $fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n", wea_i ? "write" : "read", ADDRA, web_i ? "write" : "read", ADDRB); end end //**************************************************** // Asynchronous collision checks //**************************************************** end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll // Delay A and B addresses in order to mimic setup/hold times wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA; wire [0:0] #COLL_DELAY wea_delay = wea_i; wire #COLL_DELAY ena_delay = ena_i; wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB; wire [0:0] #COLL_DELAY web_delay = web_i; wire #COLL_DELAY enb_delay = enb_i; // Do the checks w/rt A always @(posedge CLKA) begin // Possible collision if both are enabled and the addresses match if (ena_i && enb_i) begin if (wea_i || web_i) begin is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i); end else begin is_collision_a = 0; end end else begin is_collision_a = 0; end if (ena_i && enb_delay) begin if(wea_i || web_delay) begin is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay, web_delay); end else begin is_collision_delay_a = 0; end end else begin is_collision_delay_a = 0; end // Only flag if B access is a write if (is_collision_a && web_i) begin $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", C_CORENAME, $time); $fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n", wea_i ? "write" : "read", ADDRA, ADDRB); end else if (is_collision_delay_a && web_delay) begin $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", C_CORENAME, $time); $fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n", wea_i ? "write" : "read", ADDRA, addrb_delay); end end // Do the checks w/rt B always @(posedge CLKB) begin // Possible collision if both are enabled and the addresses match if (ena_i && enb_i) begin if (wea_i || web_i) begin is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i); end else begin is_collision_b = 0; end end else begin is_collision_b = 0; end if (ena_delay && enb_i) begin if (wea_delay || web_i) begin is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB, web_i); end else begin is_collision_delay_b = 0; end end else begin is_collision_delay_b = 0; end // Only flag if A access is a write if (is_collision_b && wea_i) begin $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", C_CORENAME, $time); $fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n", ADDRA, web_i ? "write" : "read", ADDRB); end else if (is_collision_delay_b && wea_delay) begin $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", C_CORENAME, $time); $fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n", addra_delay, web_i ? "write" : "read", ADDRB); end end end endgenerate endmodule
module blk_mem_gen_v8_2 #(parameter C_CORENAME = "blk_mem_gen_v8_2", parameter C_FAMILY = "virtex7", parameter C_XDEVICEFAMILY = "virtex7", parameter C_ELABORATION_DIR = "", parameter C_INTERFACE_TYPE = 0, parameter C_USE_BRAM_BLOCK = 0, parameter C_CTRL_ECC_ALGO = "NONE", parameter C_ENABLE_32BIT_ADDRESS = 0, parameter C_AXI_TYPE = 0, parameter C_AXI_SLAVE_TYPE = 0, parameter C_HAS_AXI_ID = 0, parameter C_AXI_ID_WIDTH = 4, parameter C_MEM_TYPE = 2, parameter C_BYTE_SIZE = 9, parameter C_ALGORITHM = 1, parameter C_PRIM_TYPE = 3, parameter C_LOAD_INIT_FILE = 0, parameter C_INIT_FILE_NAME = "", parameter C_INIT_FILE = "", parameter C_USE_DEFAULT_DATA = 0, parameter C_DEFAULT_DATA = "0", //parameter C_RST_TYPE = "SYNC", parameter C_HAS_RSTA = 0, parameter C_RST_PRIORITY_A = "CE", parameter C_RSTRAM_A = 0, parameter C_INITA_VAL = "0", parameter C_HAS_ENA = 1, parameter C_HAS_REGCEA = 0, parameter C_USE_BYTE_WEA = 0, parameter C_WEA_WIDTH = 1, parameter C_WRITE_MODE_A = "WRITE_FIRST", parameter C_WRITE_WIDTH_A = 32, parameter C_READ_WIDTH_A = 32, parameter C_WRITE_DEPTH_A = 64, parameter C_READ_DEPTH_A = 64, parameter C_ADDRA_WIDTH = 5, parameter C_HAS_RSTB = 0, parameter C_RST_PRIORITY_B = "CE", parameter C_RSTRAM_B = 0, parameter C_INITB_VAL = "", parameter C_HAS_ENB = 1, parameter C_HAS_REGCEB = 0, parameter C_USE_BYTE_WEB = 0, parameter C_WEB_WIDTH = 1, parameter C_WRITE_MODE_B = "WRITE_FIRST", parameter C_WRITE_WIDTH_B = 32, parameter C_READ_WIDTH_B = 32, parameter C_WRITE_DEPTH_B = 64, parameter C_READ_DEPTH_B = 64, parameter C_ADDRB_WIDTH = 5, parameter C_HAS_MEM_OUTPUT_REGS_A = 0, parameter C_HAS_MEM_OUTPUT_REGS_B = 0, parameter C_HAS_MUX_OUTPUT_REGS_A = 0, parameter C_HAS_MUX_OUTPUT_REGS_B = 0, parameter C_HAS_SOFTECC_INPUT_REGS_A = 0, parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, parameter C_MUX_PIPELINE_STAGES = 0, parameter C_USE_SOFTECC = 0, parameter C_USE_ECC = 0, parameter C_EN_ECC_PIPE = 0, parameter C_HAS_INJECTERR = 0, parameter C_SIM_COLLISION_CHECK = "NONE", parameter C_COMMON_CLK = 1, parameter C_DISABLE_WARN_BHV_COLL = 0, parameter C_EN_SLEEP_PIN = 0, parameter C_DISABLE_WARN_BHV_RANGE = 0, parameter C_COUNT_36K_BRAM = "", parameter C_COUNT_18K_BRAM = "", parameter C_EST_POWER_SUMMARY = "" ) (input clka, input rsta, input ena, input regcea, input [C_WEA_WIDTH-1:0] wea, input [C_ADDRA_WIDTH-1:0] addra, input [C_WRITE_WIDTH_A-1:0] dina, output [C_READ_WIDTH_A-1:0] douta, input clkb, input rstb, input enb, input regceb, input [C_WEB_WIDTH-1:0] web, input [C_ADDRB_WIDTH-1:0] addrb, input [C_WRITE_WIDTH_B-1:0] dinb, output [C_READ_WIDTH_B-1:0] doutb, input injectsbiterr, input injectdbiterr, output sbiterr, output dbiterr, output [C_ADDRB_WIDTH-1:0] rdaddrecc, input eccpipece, input sleep, //AXI BMG Input and Output Port Declarations //AXI Global Signals input s_aclk, input s_aresetn, //AXI Full/lite slave write (write side) input [C_AXI_ID_WIDTH-1:0] s_axi_awid, input [31:0] s_axi_awaddr, input [7:0] s_axi_awlen, input [2:0] s_axi_awsize, input [1:0] s_axi_awburst, input s_axi_awvalid, output s_axi_awready, input [C_WRITE_WIDTH_A-1:0] s_axi_wdata, input [C_WEA_WIDTH-1:0] s_axi_wstrb, input s_axi_wlast, input s_axi_wvalid, output s_axi_wready, output [C_AXI_ID_WIDTH-1:0] s_axi_bid, output [1:0] s_axi_bresp, output s_axi_bvalid, input s_axi_bready, //AXI Full/lite slave read (write side) input [C_AXI_ID_WIDTH-1:0] s_axi_arid, input [31:0] s_axi_araddr, input [7:0] s_axi_arlen, input [2:0] s_axi_arsize, input [1:0] s_axi_arburst, input s_axi_arvalid, output s_axi_arready, output [C_AXI_ID_WIDTH-1:0] s_axi_rid, output [C_WRITE_WIDTH_B-1:0] s_axi_rdata, output [1:0] s_axi_rresp, output s_axi_rlast, output s_axi_rvalid, input s_axi_rready, //AXI Full/lite sideband signals input s_axi_injectsbiterr, input s_axi_injectdbiterr, output s_axi_sbiterr, output s_axi_dbiterr, output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc ); //****************************** // Port and Generic Definitions //****************************** ////////////////////////////////////////////////////////////////////////// // Generic Definitions ////////////////////////////////////////////////////////////////////////// // C_CORENAME : Instance name of the Block Memory Generator core // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following // options are available - "spartan3", "spartan6", // "virtex4", "virtex5", "virtex6" and "virtex6l". // C_MEM_TYPE : Designates memory type. // It can be // 0 - Single Port Memory // 1 - Simple Dual Port Memory // 2 - True Dual Port Memory // 3 - Single Port Read Only Memory // 4 - Dual Port Read Only Memory // C_BYTE_SIZE : Size of a byte (8 or 9 bits) // C_ALGORITHM : Designates the algorithm method used // for constructing the memory. // It can be Fixed_Primitives, Minimum_Area or // Low_Power // C_PRIM_TYPE : Designates the user selected primitive used to // construct the memory. // // C_LOAD_INIT_FILE : Designates the use of an initialization file to // initialize memory contents. // C_INIT_FILE_NAME : Memory initialization file name. // C_USE_DEFAULT_DATA : Designates whether to fill remaining // initialization space with default data // C_DEFAULT_DATA : Default value of all memory locations // not initialized by the memory // initialization file. // C_RST_TYPE : Type of reset - Synchronous or Asynchronous // C_HAS_RSTA : Determines the presence of the RSTA port // C_RST_PRIORITY_A : Determines the priority between CE and SR for // Port A. // C_RSTRAM_A : Determines if special reset behavior is used for // Port A // C_INITA_VAL : The initialization value for Port A // C_HAS_ENA : Determines the presence of the ENA port // C_HAS_REGCEA : Determines the presence of the REGCEA port // C_USE_BYTE_WEA : Determines if the Byte Write is used or not. // C_WEA_WIDTH : The width of the WEA port // C_WRITE_MODE_A : Configurable write mode for Port A. It can be // WRITE_FIRST, READ_FIRST or NO_CHANGE. // C_WRITE_WIDTH_A : Memory write width for Port A. // C_READ_WIDTH_A : Memory read width for Port A. // C_WRITE_DEPTH_A : Memory write depth for Port A. // C_READ_DEPTH_A : Memory read depth for Port A. // C_ADDRA_WIDTH : Width of the ADDRA input port // C_HAS_RSTB : Determines the presence of the RSTB port // C_RST_PRIORITY_B : Determines the priority between CE and SR for // Port B. // C_RSTRAM_B : Determines if special reset behavior is used for // Port B // C_INITB_VAL : The initialization value for Port B // C_HAS_ENB : Determines the presence of the ENB port // C_HAS_REGCEB : Determines the presence of the REGCEB port // C_USE_BYTE_WEB : Determines if the Byte Write is used or not. // C_WEB_WIDTH : The width of the WEB port // C_WRITE_MODE_B : Configurable write mode for Port B. It can be // WRITE_FIRST, READ_FIRST or NO_CHANGE. // C_WRITE_WIDTH_B : Memory write width for Port B. // C_READ_WIDTH_B : Memory read width for Port B. // C_WRITE_DEPTH_B : Memory write depth for Port B. // C_READ_DEPTH_B : Memory read depth for Port B. // C_ADDRB_WIDTH : Width of the ADDRB input port // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output // of the RAM primitive for Port A. // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output // of the RAM primitive for Port B. // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output // of the MUX for Port A. // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output // of the MUX for Port B. // C_HAS_SOFTECC_INPUT_REGS_A : // C_HAS_SOFTECC_OUTPUT_REGS_B : // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in // between the muxes. // C_USE_SOFTECC : Determines if the Soft ECC feature is used or // not. Only applicable Spartan-6 // C_USE_ECC : Determines if the ECC feature is used or // not. Only applicable for V5 and V6 // C_HAS_INJECTERR : Determines if the error injection pins // are present or not. If the ECC feature // is not used, this value is defaulted to // 0, else the following are the allowed // values: // 0 : No INJECTSBITERR or INJECTDBITERR pins // 1 : Only INJECTSBITERR pin exists // 2 : Only INJECTDBITERR pin exists // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision // warnings. It can be "ALL", "NONE", // "Warnings_Only" or "Generate_X_Only". // C_COMMON_CLK : Determins if the core has a single CLK input. // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range // warnings ////////////////////////////////////////////////////////////////////////// // Port Definitions ////////////////////////////////////////////////////////////////////////// // CLKA : Clock to synchronize all read and write operations of Port A. // RSTA : Reset input to reset memory outputs to a user-defined // reset state for Port A. // ENA : Enable all read and write operations of Port A. // REGCEA : Register Clock Enable to control each pipeline output // register stages for Port A. // WEA : Write Enable to enable all write operations of Port A. // ADDRA : Address of Port A. // DINA : Data input of Port A. // DOUTA : Data output of Port A. // CLKB : Clock to synchronize all read and write operations of Port B. // RSTB : Reset input to reset memory outputs to a user-defined // reset state for Port B. // ENB : Enable all read and write operations of Port B. // REGCEB : Register Clock Enable to control each pipeline output // register stages for Port B. // WEB : Write Enable to enable all write operations of Port B. // ADDRB : Address of Port B. // DINB : Data input of Port B. // DOUTB : Data output of Port B. // INJECTSBITERR : Single Bit ECC Error Injection Pin. // INJECTDBITERR : Double Bit ECC Error Injection Pin. // SBITERR : Output signal indicating that a Single Bit ECC Error has been // detected and corrected. // DBITERR : Output signal indicating that a Double Bit ECC Error has been // detected. // RDADDRECC : Read Address Output signal indicating address at which an // ECC error has occurred. ////////////////////////////////////////////////////////////////////////// wire SBITERR; wire DBITERR; wire S_AXI_AWREADY; wire S_AXI_WREADY; wire S_AXI_BVALID; wire S_AXI_ARREADY; wire S_AXI_RLAST; wire S_AXI_RVALID; wire S_AXI_SBITERR; wire S_AXI_DBITERR; wire [C_WEA_WIDTH-1:0] WEA = wea; wire [C_ADDRA_WIDTH-1:0] ADDRA = addra; wire [C_WRITE_WIDTH_A-1:0] DINA = dina; wire [C_READ_WIDTH_A-1:0] DOUTA; wire [C_WEB_WIDTH-1:0] WEB = web; wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb; wire [C_WRITE_WIDTH_B-1:0] DINB = dinb; wire [C_READ_WIDTH_B-1:0] DOUTB; wire [C_ADDRB_WIDTH-1:0] RDADDRECC; wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid; wire [31:0] S_AXI_AWADDR = s_axi_awaddr; wire [7:0] S_AXI_AWLEN = s_axi_awlen; wire [2:0] S_AXI_AWSIZE = s_axi_awsize; wire [1:0] S_AXI_AWBURST = s_axi_awburst; wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata; wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb; wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID; wire [1:0] S_AXI_BRESP; wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid; wire [31:0] S_AXI_ARADDR = s_axi_araddr; wire [7:0] S_AXI_ARLEN = s_axi_arlen; wire [2:0] S_AXI_ARSIZE = s_axi_arsize; wire [1:0] S_AXI_ARBURST = s_axi_arburst; wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID; wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA; wire [1:0] S_AXI_RRESP; wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC; // Added to fix the simulation warning #CR731605 wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0; wire ECCPIPECE; wire SLEEP; assign CLKA = clka; assign RSTA = rsta; assign ENA = ena; assign REGCEA = regcea; assign CLKB = clkb; assign RSTB = rstb; assign ENB = enb; assign REGCEB = regceb; assign INJECTSBITERR = injectsbiterr; assign INJECTDBITERR = injectdbiterr; assign ECCPIPECE = eccpipece; assign SLEEP = sleep; assign sbiterr = SBITERR; assign dbiterr = DBITERR; assign S_ACLK = s_aclk; assign S_ARESETN = s_aresetn; assign S_AXI_AWVALID = s_axi_awvalid; assign s_axi_awready = S_AXI_AWREADY; assign S_AXI_WLAST = s_axi_wlast; assign S_AXI_WVALID = s_axi_wvalid; assign s_axi_wready = S_AXI_WREADY; assign s_axi_bvalid = S_AXI_BVALID; assign S_AXI_BREADY = s_axi_bready; assign S_AXI_ARVALID = s_axi_arvalid; assign s_axi_arready = S_AXI_ARREADY; assign s_axi_rlast = S_AXI_RLAST; assign s_axi_rvalid = S_AXI_RVALID; assign S_AXI_RREADY = s_axi_rready; assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr; assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr; assign s_axi_sbiterr = S_AXI_SBITERR; assign s_axi_dbiterr = S_AXI_DBITERR; assign doutb = DOUTB; assign douta = DOUTA; assign rdaddrecc = RDADDRECC; assign s_axi_bid = S_AXI_BID; assign s_axi_bresp = S_AXI_BRESP; assign s_axi_rid = S_AXI_RID; assign s_axi_rdata = S_AXI_RDATA; assign s_axi_rresp = S_AXI_RRESP; assign s_axi_rdaddrecc = S_AXI_RDADDRECC; localparam FLOP_DELAY = 100; // 100 ps reg injectsbiterr_in; reg injectdbiterr_in; reg rsta_in; reg ena_in; reg regcea_in; reg [C_WEA_WIDTH-1:0] wea_in; reg [C_ADDRA_WIDTH-1:0] addra_in; reg [C_WRITE_WIDTH_A-1:0] dina_in; wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c; wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c; wire s_axi_wr_en_c; wire s_axi_rd_en_c; wire s_aresetn_a_c; wire [7:0] s_axi_arlen_c ; wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c; wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c; wire [1:0] s_axi_rresp_c; wire s_axi_rlast_c; wire s_axi_rvalid_c; wire s_axi_rready_c; wire regceb_c; localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3; wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c; wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c; //************** // log2roundup //************** function integer log2roundup (input integer data_value); integer width; integer cnt; begin width = 0; if (data_value > 1) begin for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin width = width + 1; end //loop end //if log2roundup = width; end //log2roundup endfunction //************** // log2int //************** function integer log2int (input integer data_value); integer width; integer cnt; begin width = 0; cnt= data_value; for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin width = width + 1; end //loop log2int = width; end //log2int endfunction //************************************************************************** // FUNCTION : divroundup // Returns the ceiling value of the division // Data_value - the quantity to be divided, dividend // Divisor - the value to divide the data_value by //************************************************************************** function integer divroundup (input integer data_value,input integer divisor); integer div; begin div = data_value/divisor; if ((data_value % divisor) != 0) begin div = div+1; end //if divroundup = div; end //if endfunction localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0); localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8); localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB; //Data Width Number of LSB address bits to be discarded //1 to 16 1 //17 to 32 2 //33 to 64 3 //65 to 128 4 //129 to 256 5 //257 to 512 6 //513 to 1024 7 // The following two constants determine this. localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8))); localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL); localparam C_AXI_OS_WR = 2; //*********************************************** // INPUT REGISTERS. //*********************************************** generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage always @* begin injectsbiterr_in = INJECTSBITERR; injectdbiterr_in = INJECTDBITERR; rsta_in = RSTA; ena_in = ENA; regcea_in = REGCEA; wea_in = WEA; addra_in = ADDRA; dina_in = DINA; end //end always end //end no_softecc_input_reg_stage endgenerate generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage always @(posedge CLKA) begin injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR; injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR; rsta_in <= #FLOP_DELAY RSTA; ena_in <= #FLOP_DELAY ENA; regcea_in <= #FLOP_DELAY REGCEA; wea_in <= #FLOP_DELAY WEA; addra_in <= #FLOP_DELAY ADDRA; dina_in <= #FLOP_DELAY DINA; end //end always end //end input_reg_stages generate statement endgenerate generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module BLK_MEM_GEN_v8_2_mem_module #(.C_CORENAME (C_CORENAME), .C_FAMILY (C_FAMILY), .C_XDEVICEFAMILY (C_XDEVICEFAMILY), .C_MEM_TYPE (C_MEM_TYPE), .C_BYTE_SIZE (C_BYTE_SIZE), .C_ALGORITHM (C_ALGORITHM), .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), .C_PRIM_TYPE (C_PRIM_TYPE), .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), .C_INIT_FILE_NAME (C_INIT_FILE_NAME), .C_INIT_FILE (C_INIT_FILE), .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), .C_DEFAULT_DATA (C_DEFAULT_DATA), .C_RST_TYPE ("SYNC"), .C_HAS_RSTA (C_HAS_RSTA), .C_RST_PRIORITY_A (C_RST_PRIORITY_A), .C_RSTRAM_A (C_RSTRAM_A), .C_INITA_VAL (C_INITA_VAL), .C_HAS_ENA (C_HAS_ENA), .C_HAS_REGCEA (C_HAS_REGCEA), .C_USE_BYTE_WEA (C_USE_BYTE_WEA), .C_WEA_WIDTH (C_WEA_WIDTH), .C_WRITE_MODE_A (C_WRITE_MODE_A), .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), .C_READ_WIDTH_A (C_READ_WIDTH_A), .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), .C_READ_DEPTH_A (C_READ_DEPTH_A), .C_ADDRA_WIDTH (C_ADDRA_WIDTH), .C_HAS_RSTB (C_HAS_RSTB), .C_RST_PRIORITY_B (C_RST_PRIORITY_B), .C_RSTRAM_B (C_RSTRAM_B), .C_INITB_VAL (C_INITB_VAL), .C_HAS_ENB (C_HAS_ENB), .C_HAS_REGCEB (C_HAS_REGCEB), .C_USE_BYTE_WEB (C_USE_BYTE_WEB), .C_WEB_WIDTH (C_WEB_WIDTH), .C_WRITE_MODE_B (C_WRITE_MODE_B), .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), .C_READ_WIDTH_B (C_READ_WIDTH_B), .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), .C_READ_DEPTH_B (C_READ_DEPTH_B), .C_ADDRB_WIDTH (C_ADDRB_WIDTH), .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), .C_USE_SOFTECC (C_USE_SOFTECC), .C_USE_ECC (C_USE_ECC), .C_HAS_INJECTERR (C_HAS_INJECTERR), .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), .C_COMMON_CLK (C_COMMON_CLK), .FLOP_DELAY (FLOP_DELAY), .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), .C_EN_ECC_PIPE (C_EN_ECC_PIPE), .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) blk_mem_gen_v8_2_inst (.CLKA (CLKA), .RSTA (rsta_in), .ENA (ena_in), .REGCEA (regcea_in), .WEA (wea_in), .ADDRA (addra_in), .DINA (dina_in), .DOUTA (DOUTA), .CLKB (CLKB), .RSTB (RSTB), .ENB (ENB), .REGCEB (REGCEB), .WEB (WEB), .ADDRB (ADDRB), .DINB (DINB), .DOUTB (DOUTB), .INJECTSBITERR (injectsbiterr_in), .INJECTDBITERR (injectdbiterr_in), .ECCPIPECE (ECCPIPECE), .SLEEP (SLEEP), .SBITERR (SBITERR), .DBITERR (DBITERR), .RDADDRECC (RDADDRECC) ); end endgenerate generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A); localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B); localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8); localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8); // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8); // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8); localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB; localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB; // Data Width Number of LSB address bits to be discarded // 1 to 16 1 // 17 to 32 2 // 33 to 64 3 // 65 to 128 4 // 129 to 256 5 // 257 to 512 6 // 513 to 1024 7 // The following two constants determine this. localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8))); localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8))); localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A; localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B; wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i; wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i; wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i; assign msb_zero_i = 0; assign lsb_zero_i = 0; assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i}; BLK_MEM_GEN_v8_2_mem_module #(.C_CORENAME (C_CORENAME), .C_FAMILY (C_FAMILY), .C_XDEVICEFAMILY (C_XDEVICEFAMILY), .C_MEM_TYPE (C_MEM_TYPE), .C_BYTE_SIZE (C_BYTE_SIZE), .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), .C_ALGORITHM (C_ALGORITHM), .C_PRIM_TYPE (C_PRIM_TYPE), .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), .C_INIT_FILE_NAME (C_INIT_FILE_NAME), .C_INIT_FILE (C_INIT_FILE), .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), .C_DEFAULT_DATA (C_DEFAULT_DATA), .C_RST_TYPE ("SYNC"), .C_HAS_RSTA (C_HAS_RSTA), .C_RST_PRIORITY_A (C_RST_PRIORITY_A), .C_RSTRAM_A (C_RSTRAM_A), .C_INITA_VAL (C_INITA_VAL), .C_HAS_ENA (C_HAS_ENA), .C_HAS_REGCEA (C_HAS_REGCEA), .C_USE_BYTE_WEA (C_USE_BYTE_WEA), .C_WEA_WIDTH (C_WEA_WIDTH), .C_WRITE_MODE_A (C_WRITE_MODE_A), .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), .C_READ_WIDTH_A (C_READ_WIDTH_A), .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), .C_READ_DEPTH_A (C_READ_DEPTH_A), .C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL), .C_HAS_RSTB (C_HAS_RSTB), .C_RST_PRIORITY_B (C_RST_PRIORITY_B), .C_RSTRAM_B (C_RSTRAM_B), .C_INITB_VAL (C_INITB_VAL), .C_HAS_ENB (C_HAS_ENB), .C_HAS_REGCEB (C_HAS_REGCEB), .C_USE_BYTE_WEB (C_USE_BYTE_WEB), .C_WEB_WIDTH (C_WEB_WIDTH), .C_WRITE_MODE_B (C_WRITE_MODE_B), .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), .C_READ_WIDTH_B (C_READ_WIDTH_B), .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), .C_READ_DEPTH_B (C_READ_DEPTH_B), .C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL), .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), .C_USE_SOFTECC (C_USE_SOFTECC), .C_USE_ECC (C_USE_ECC), .C_HAS_INJECTERR (C_HAS_INJECTERR), .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), .C_COMMON_CLK (C_COMMON_CLK), .FLOP_DELAY (FLOP_DELAY), .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), .C_EN_ECC_PIPE (C_EN_ECC_PIPE), .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) blk_mem_gen_v8_2_inst (.CLKA (CLKA), .RSTA (rsta_in), .ENA (ena_in), .REGCEA (regcea_in), .WEA (wea_in), .ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]), .DINA (dina_in), .DOUTA (DOUTA), .CLKB (CLKB), .RSTB (RSTB), .ENB (ENB), .REGCEB (REGCEB), .WEB (WEB), .ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]), .DINB (DINB), .DOUTB (DOUTB), .INJECTSBITERR (injectsbiterr_in), .INJECTDBITERR (injectdbiterr_in), .ECCPIPECE (ECCPIPECE), .SLEEP (SLEEP), .SBITERR (SBITERR), .DBITERR (DBITERR), .RDADDRECC (rdaddrecc_i) ); end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs assign S_AXI_RDATA = s_axi_rdata_c; assign S_AXI_RLAST = s_axi_rlast_c; assign S_AXI_RVALID = s_axi_rvalid_c; assign S_AXI_RID = s_axi_rid_c; assign S_AXI_RRESP = s_axi_rresp_c; assign s_axi_rready_c = S_AXI_RREADY; end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb assign regceb_c = s_axi_rvalid_c && s_axi_rready_c; end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb assign regceb_c = REGCEB; end endgenerate generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c}; assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH]; assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B]; assign S_AXI_RRESP = m_axi_payload_c[2:1]; assign S_AXI_RLAST = m_axi_payload_c[0]; end endgenerate generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c}; assign S_AXI_RDATA = s_axi_rdata_c; assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH]; assign S_AXI_RRESP = m_axi_payload_c[2:1]; assign S_AXI_RLAST = m_axi_payload_c[0]; end endgenerate generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd blk_mem_axi_regs_fwd_v8_2 #(.C_DATA_WIDTH (C_AXI_PAYLOAD)) axi_regs_inst ( .ACLK (S_ACLK), .ARESET (s_aresetn_a_c), .S_VALID (s_axi_rvalid_c), .S_READY (s_axi_rready_c), .S_PAYLOAD_DATA (s_axi_payload_c), .M_VALID (S_AXI_RVALID), .M_READY (S_AXI_RREADY), .M_PAYLOAD_DATA (m_axi_payload_c) ); end endgenerate generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module assign s_aresetn_a_c = !S_ARESETN; assign S_AXI_BRESP = 2'b00; assign s_axi_rresp_c = 2'b00; assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0; blk_mem_axi_write_wrapper_beh_v8_2 #(.C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_AXI_TYPE (C_AXI_TYPE), .C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE), .C_MEMORY_TYPE (C_MEM_TYPE), .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), .C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), .C_HAS_AXI_ID (C_HAS_AXI_ID), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_ADDRA_WIDTH (C_ADDRA_WIDTH), .C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A), .C_AXI_OS_WR (C_AXI_OS_WR)) axi_wr_fsm ( // AXI Global Signals .S_ACLK (S_ACLK), .S_ARESETN (s_aresetn_a_c), // AXI Full/Lite Slave Write interface .S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]), .S_AXI_AWLEN (S_AXI_AWLEN), .S_AXI_AWID (S_AXI_AWID), .S_AXI_AWSIZE (S_AXI_AWSIZE), .S_AXI_AWBURST (S_AXI_AWBURST), .S_AXI_AWVALID (S_AXI_AWVALID), .S_AXI_AWREADY (S_AXI_AWREADY), .S_AXI_WVALID (S_AXI_WVALID), .S_AXI_WREADY (S_AXI_WREADY), .S_AXI_BVALID (S_AXI_BVALID), .S_AXI_BREADY (S_AXI_BREADY), .S_AXI_BID (S_AXI_BID), // Signals for BRAM interfac( .S_AXI_AWADDR_OUT (s_axi_awaddr_out_c), .S_AXI_WR_EN (s_axi_wr_en_c) ); blk_mem_axi_read_wrapper_beh_v8_2 #(.C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_AXI_TYPE (C_AXI_TYPE), .C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE), .C_MEMORY_TYPE (C_MEM_TYPE), .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), .C_ADDRA_WIDTH (C_ADDRA_WIDTH), .C_AXI_PIPELINE_STAGES (1), .C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), .C_HAS_AXI_ID (C_HAS_AXI_ID), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_ADDRB_WIDTH (C_ADDRB_WIDTH)) axi_rd_sm( //AXI Global Signals .S_ACLK (S_ACLK), .S_ARESETN (s_aresetn_a_c), //AXI Full/Lite Read Side .S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]), .S_AXI_ARLEN (s_axi_arlen_c), .S_AXI_ARSIZE (S_AXI_ARSIZE), .S_AXI_ARBURST (S_AXI_ARBURST), .S_AXI_ARVALID (S_AXI_ARVALID), .S_AXI_ARREADY (S_AXI_ARREADY), .S_AXI_RLAST (s_axi_rlast_c), .S_AXI_RVALID (s_axi_rvalid_c), .S_AXI_RREADY (s_axi_rready_c), .S_AXI_ARID (S_AXI_ARID), .S_AXI_RID (s_axi_rid_c), //AXI Full/Lite Read FSM Outputs .S_AXI_ARADDR_OUT (s_axi_araddr_out_c), .S_AXI_RD_EN (s_axi_rd_en_c) ); BLK_MEM_GEN_v8_2_mem_module #(.C_CORENAME (C_CORENAME), .C_FAMILY (C_FAMILY), .C_XDEVICEFAMILY (C_XDEVICEFAMILY), .C_MEM_TYPE (C_MEM_TYPE), .C_BYTE_SIZE (C_BYTE_SIZE), .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), .C_ALGORITHM (C_ALGORITHM), .C_PRIM_TYPE (C_PRIM_TYPE), .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), .C_INIT_FILE_NAME (C_INIT_FILE_NAME), .C_INIT_FILE (C_INIT_FILE), .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), .C_DEFAULT_DATA (C_DEFAULT_DATA), .C_RST_TYPE ("SYNC"), .C_HAS_RSTA (C_HAS_RSTA), .C_RST_PRIORITY_A (C_RST_PRIORITY_A), .C_RSTRAM_A (C_RSTRAM_A), .C_INITA_VAL (C_INITA_VAL), .C_HAS_ENA (1), .C_HAS_REGCEA (C_HAS_REGCEA), .C_USE_BYTE_WEA (1), .C_WEA_WIDTH (C_WEA_WIDTH), .C_WRITE_MODE_A (C_WRITE_MODE_A), .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), .C_READ_WIDTH_A (C_READ_WIDTH_A), .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), .C_READ_DEPTH_A (C_READ_DEPTH_A), .C_ADDRA_WIDTH (C_ADDRA_WIDTH), .C_HAS_RSTB (C_HAS_RSTB), .C_RST_PRIORITY_B (C_RST_PRIORITY_B), .C_RSTRAM_B (C_RSTRAM_B), .C_INITB_VAL (C_INITB_VAL), .C_HAS_ENB (1), .C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B), .C_USE_BYTE_WEB (1), .C_WEB_WIDTH (C_WEB_WIDTH), .C_WRITE_MODE_B (C_WRITE_MODE_B), .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), .C_READ_WIDTH_B (C_READ_WIDTH_B), .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), .C_READ_DEPTH_B (C_READ_DEPTH_B), .C_ADDRB_WIDTH (C_ADDRB_WIDTH), .C_HAS_MEM_OUTPUT_REGS_A (0), .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), .C_HAS_MUX_OUTPUT_REGS_A (0), .C_HAS_MUX_OUTPUT_REGS_B (0), .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), .C_USE_SOFTECC (C_USE_SOFTECC), .C_USE_ECC (C_USE_ECC), .C_HAS_INJECTERR (C_HAS_INJECTERR), .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), .C_COMMON_CLK (C_COMMON_CLK), .FLOP_DELAY (FLOP_DELAY), .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), .C_EN_ECC_PIPE (0), .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) blk_mem_gen_v8_2_inst (.CLKA (S_ACLK), .RSTA (s_aresetn_a_c), .ENA (s_axi_wr_en_c), .REGCEA (regcea_in), .WEA (S_AXI_WSTRB), .ADDRA (s_axi_awaddr_out_c), .DINA (S_AXI_WDATA), .DOUTA (DOUTA), .CLKB (S_ACLK), .RSTB (s_aresetn_a_c), .ENB (s_axi_rd_en_c), .REGCEB (regceb_c), .WEB (WEB_parameterized), .ADDRB (s_axi_araddr_out_c), .DINB (DINB), .DOUTB (s_axi_rdata_c), .INJECTSBITERR (injectsbiterr_in), .INJECTDBITERR (injectdbiterr_in), .SBITERR (SBITERR), .DBITERR (DBITERR), .ECCPIPECE (1'b0), .SLEEP (1'b0), .RDADDRECC (RDADDRECC) ); end endgenerate endmodule
module MM_to_ST_Adapter ( clk, reset, length, length_counter, address, reads_pending, start, readdata, readdatavalid, fifo_data, fifo_write, fifo_empty, fifo_sop, fifo_eop ); parameter DATA_WIDTH = 32; // 8, 16, 32, 64, 128, or 256 are valid values (if 8 is used then disable unaligned accesses and turn on full word only accesses) parameter LENGTH_WIDTH = 32; parameter ADDRESS_WIDTH = 32; parameter BYTE_ADDRESS_WIDTH = 2; // log2(DATA_WIDTH/8) parameter READS_PENDING_WIDTH = 5; parameter EMPTY_WIDTH = 2; // log2(DATA_WIDTH/8) parameter PACKET_SUPPORT = 1; // when set to 1 eop, sop, and empty will be driven, otherwise they will be grounded // only set one of these at a time parameter UNALIGNED_ACCESS_ENABLE = 1; // when set to 1 this block will support packets and starting/ending on any boundary, do not use this if DATA_WIDTH is 8 (use 'FULL_WORD_ACCESS_ONLY') parameter FULL_WORD_ACCESS_ONLY = 0; // when set to 1 this block will assume only full words are arriving (must start and stop on a word boundary). input clk; input reset; input [LENGTH_WIDTH-1:0] length; input [LENGTH_WIDTH-1:0] length_counter; input [ADDRESS_WIDTH-1:0] address; input [READS_PENDING_WIDTH-1:0] reads_pending; input start; // one cycle strobe at the start of a transfer used to capture bytes_to_transfer input [DATA_WIDTH-1:0] readdata; input readdatavalid; output wire [DATA_WIDTH-1:0] fifo_data; output wire fifo_write; output wire [EMPTY_WIDTH-1:0] fifo_empty; output wire fifo_sop; output wire fifo_eop; // internal registers and wires reg [DATA_WIDTH-1:0] readdata_d1; reg readdatavalid_d1; wire [DATA_WIDTH-1:0] data_in; // data_in will either be readdata or a pipelined copy of readdata depending on whether unaligned access support is enabled wire valid_in; // valid in will either be readdatavalid or a pipelined copy of readdatavalid depending on whether unaligned access support is enabled reg valid_in_d1; wire [DATA_WIDTH-1:0] barrelshifter_A; // shifted current read data wire [DATA_WIDTH-1:0] barrelshifter_B; reg [DATA_WIDTH-1:0] barrelshifter_B_d1; // shifted previously read data wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap) wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs wire extra_access_enable; reg extra_access; wire last_unaligned_fifo_write; reg first_access_seen; reg second_access_seen; wire first_access_seen_rising_edge; wire second_access_seen_rising_edge; reg [BYTE_ADDRESS_WIDTH-1:0] byte_address; reg [EMPTY_WIDTH-1:0] last_empty; // only the last word written into the FIFO can have empty bytes reg start_and_end_same_cycle; // when the amount of data to transfer is only a full word or less generate if (UNALIGNED_ACCESS_ENABLE == 1) // unaligned so using a pipelined input begin assign data_in = readdata_d1; assign valid_in = readdatavalid_d1; end else begin assign data_in = readdata; // no barrelshifters in this case so pipelining is not necessary assign valid_in = readdatavalid; end endgenerate always @ (posedge clk or posedge reset) begin if (reset) begin readdata_d1 <= 0; end else begin if (readdatavalid == 1) begin readdata_d1 <= readdata; end end end always @ (posedge clk or posedge reset) begin if (reset) begin readdatavalid_d1 <= 0; valid_in_d1 <= 0; end else begin readdatavalid_d1 <= readdatavalid; valid_in_d1 <= valid_in; // used to flush the pipeline (extra fifo write) and prolong eop for one additional clock cycle end end always @ (posedge clk or posedge reset) begin if (reset == 1) begin barrelshifter_B_d1 <= 0; end else begin if (valid_in == 1) begin barrelshifter_B_d1 <= barrelshifter_B; end end end always @ (posedge clk or posedge reset) begin if (reset) begin first_access_seen <= 0; end else begin if (start == 1) begin first_access_seen <= 0; end else if (valid_in == 1) begin first_access_seen <= 1; end end end always @ (posedge clk or posedge reset) begin if (reset) begin second_access_seen <= 0; end else begin if (start == 1) begin second_access_seen <= 0; end else if ((first_access_seen == 1) & (valid_in == 1)) begin second_access_seen <= 1; end end end always @ (posedge clk or posedge reset) begin if (reset) begin byte_address <= 0; end else if (start == 1) begin byte_address <= address[BYTE_ADDRESS_WIDTH-1:0]; end end always @ (posedge clk or posedge reset) begin if (reset) begin last_empty <= 0; end else if (start == 1) begin last_empty <= ((DATA_WIDTH/8) - length[EMPTY_WIDTH-1:0]) & {EMPTY_WIDTH{1'b1}}; // if length isn't a multiple of the word size then we'll have some empty symbols/bytes during the last fifo write end end always @ (posedge clk or posedge reset) begin if (reset) begin extra_access <= 0; end else if (start == 1) begin extra_access <= extra_access_enable; // when set the number of reads and fifo writes are equal, otherwise there will be 1 less fifo write than reads (unaligned accesses only) end end always @ (posedge clk or posedge reset) begin if (reset) begin start_and_end_same_cycle <= 0; end else if (start == 1) begin start_and_end_same_cycle <= (length <= (DATA_WIDTH/8)); end end /* These barrelshifters will take the unaligned data coming into this block and shift the byte lanes appropriately to form a single packed word. Zeros are shifted into the byte lanes that do not contain valid data for the combined word that will be buffered. This allows both barrelshifters to be logically OR'ed together to form a single packed word. Shifter A is used to shift the current read data towards the upper bytes of the combined word (since those are the upper addresses of the combined word). Shifter B after the pipeline stage called 'barrelshifter_B_d1' contains the previously read data shifted towards the lower bytes (since those are the lower addresses of the combined word). */ generate genvar input_offset; for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1) begin: barrel_shifter_inputs assign barrelshifter_input_A[input_offset] = data_in << (8 * ((DATA_WIDTH/8) - input_offset)); assign barrelshifter_input_B[input_offset] = data_in >> (8 * input_offset); end endgenerate assign barrelshifter_A = barrelshifter_input_A[byte_address]; // upper portion of the packed word assign barrelshifter_B = barrelshifter_input_B[byte_address]; // lower portion of the packed word (will be pipelined so it will be the previous word read by the master) assign combined_word = (barrelshifter_A | barrelshifter_B_d1); // barrelshifters shift in zeros so we can just OR the words together here to create a packed word assign first_access_seen_rising_edge = (valid_in == 1) & (first_access_seen == 0); assign second_access_seen_rising_edge = ((first_access_seen == 1) & (valid_in == 1)) & (second_access_seen == 0); assign extra_access_enable = (((DATA_WIDTH/8) - length[EMPTY_WIDTH-1:0]) & {EMPTY_WIDTH{1'b1}}) >= address[BYTE_ADDRESS_WIDTH-1:0]; // enable when empty >= byte address /* Need to keep track of the last write to the FIFO so that we can fire EOP correctly as well as flush the pipeline when unaligned accesses is enabled. The first read is filtered since it is considered to be only a partial word to be written into the FIFO but there are cases when there is extra data that is buffered in 'barrelshifter_B_d1' but the transfer is done so we need to issue an additional write. In general for every 'N' Avalon-MM reads 'N-1' writes to the FIFO will occur unless there is data still buffered in which one more write to the FIFO will immediately follow the last read. */ assign last_unaligned_fifo_write = (reads_pending == 0) & (length_counter == 0) & ( ((extra_access == 0) & (valid_in == 1)) | // don't need a pipeline flush ((extra_access == 1) & (valid_in_d1 == 1) & (valid_in == 0)) ); // last write to flush the pipeline (need to make sure valid_in isn't asserted to make sure the last data is indeed coming since valid_in is pipelined) // This block should be optimized down depending on the packet support or access type settings. In the case where packet support is off // and only full accesses are used this block should become zero logic elements. generate if (PACKET_SUPPORT == 1) begin if (UNALIGNED_ACCESS_ENABLE == 1) begin assign fifo_sop = (second_access_seen_rising_edge == 1) | ((start_and_end_same_cycle == 1) & (last_unaligned_fifo_write == 1)); assign fifo_eop = last_unaligned_fifo_write; assign fifo_empty = (fifo_eop == 1)? last_empty : 0; // always full accesses until the last word end else begin assign fifo_sop = first_access_seen_rising_edge; assign fifo_eop = (length_counter == 0) & (reads_pending == 1) & (valid_in == 1); // not using last_unaligned_fifo_write since it's pipelined and when unaligned accesses are disabled the input is not pipelined if (FULL_WORD_ACCESS_ONLY == 1) begin assign fifo_empty = 0; // full accesses so no empty symbols throughout the transfer end else begin assign fifo_empty = (fifo_eop == 1)? last_empty : 0; // always full accesses until the last word end end end else begin assign fifo_eop = 0; assign fifo_sop = 0; assign fifo_empty = 0; end if (UNALIGNED_ACCESS_ENABLE == 1) begin assign fifo_data = combined_word; assign fifo_write = (first_access_seen == 1) & ((valid_in == 1) | (last_unaligned_fifo_write == 1)); // last_unaligned_fifo_write will inject an extra pulse right after the last read occurs when flushing of the pipeline is needed end else begin // don't need to pipeline since the data will not go through the barrel shifters assign fifo_data = data_in; // don't need to barrelshift when aligned accesses are used assign fifo_write = valid_in; // the number of writes to the fifo needs to always equal the number of reads from memory end endgenerate endmodule
module MM_to_ST_Adapter ( clk, reset, length, length_counter, address, reads_pending, start, readdata, readdatavalid, fifo_data, fifo_write, fifo_empty, fifo_sop, fifo_eop ); parameter DATA_WIDTH = 32; // 8, 16, 32, 64, 128, or 256 are valid values (if 8 is used then disable unaligned accesses and turn on full word only accesses) parameter LENGTH_WIDTH = 32; parameter ADDRESS_WIDTH = 32; parameter BYTE_ADDRESS_WIDTH = 2; // log2(DATA_WIDTH/8) parameter READS_PENDING_WIDTH = 5; parameter EMPTY_WIDTH = 2; // log2(DATA_WIDTH/8) parameter PACKET_SUPPORT = 1; // when set to 1 eop, sop, and empty will be driven, otherwise they will be grounded // only set one of these at a time parameter UNALIGNED_ACCESS_ENABLE = 1; // when set to 1 this block will support packets and starting/ending on any boundary, do not use this if DATA_WIDTH is 8 (use 'FULL_WORD_ACCESS_ONLY') parameter FULL_WORD_ACCESS_ONLY = 0; // when set to 1 this block will assume only full words are arriving (must start and stop on a word boundary). input clk; input reset; input [LENGTH_WIDTH-1:0] length; input [LENGTH_WIDTH-1:0] length_counter; input [ADDRESS_WIDTH-1:0] address; input [READS_PENDING_WIDTH-1:0] reads_pending; input start; // one cycle strobe at the start of a transfer used to capture bytes_to_transfer input [DATA_WIDTH-1:0] readdata; input readdatavalid; output wire [DATA_WIDTH-1:0] fifo_data; output wire fifo_write; output wire [EMPTY_WIDTH-1:0] fifo_empty; output wire fifo_sop; output wire fifo_eop; // internal registers and wires reg [DATA_WIDTH-1:0] readdata_d1; reg readdatavalid_d1; wire [DATA_WIDTH-1:0] data_in; // data_in will either be readdata or a pipelined copy of readdata depending on whether unaligned access support is enabled wire valid_in; // valid in will either be readdatavalid or a pipelined copy of readdatavalid depending on whether unaligned access support is enabled reg valid_in_d1; wire [DATA_WIDTH-1:0] barrelshifter_A; // shifted current read data wire [DATA_WIDTH-1:0] barrelshifter_B; reg [DATA_WIDTH-1:0] barrelshifter_B_d1; // shifted previously read data wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap) wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs wire extra_access_enable; reg extra_access; wire last_unaligned_fifo_write; reg first_access_seen; reg second_access_seen; wire first_access_seen_rising_edge; wire second_access_seen_rising_edge; reg [BYTE_ADDRESS_WIDTH-1:0] byte_address; reg [EMPTY_WIDTH-1:0] last_empty; // only the last word written into the FIFO can have empty bytes reg start_and_end_same_cycle; // when the amount of data to transfer is only a full word or less generate if (UNALIGNED_ACCESS_ENABLE == 1) // unaligned so using a pipelined input begin assign data_in = readdata_d1; assign valid_in = readdatavalid_d1; end else begin assign data_in = readdata; // no barrelshifters in this case so pipelining is not necessary assign valid_in = readdatavalid; end endgenerate always @ (posedge clk or posedge reset) begin if (reset) begin readdata_d1 <= 0; end else begin if (readdatavalid == 1) begin readdata_d1 <= readdata; end end end always @ (posedge clk or posedge reset) begin if (reset) begin readdatavalid_d1 <= 0; valid_in_d1 <= 0; end else begin readdatavalid_d1 <= readdatavalid; valid_in_d1 <= valid_in; // used to flush the pipeline (extra fifo write) and prolong eop for one additional clock cycle end end always @ (posedge clk or posedge reset) begin if (reset == 1) begin barrelshifter_B_d1 <= 0; end else begin if (valid_in == 1) begin barrelshifter_B_d1 <= barrelshifter_B; end end end always @ (posedge clk or posedge reset) begin if (reset) begin first_access_seen <= 0; end else begin if (start == 1) begin first_access_seen <= 0; end else if (valid_in == 1) begin first_access_seen <= 1; end end end always @ (posedge clk or posedge reset) begin if (reset) begin second_access_seen <= 0; end else begin if (start == 1) begin second_access_seen <= 0; end else if ((first_access_seen == 1) & (valid_in == 1)) begin second_access_seen <= 1; end end end always @ (posedge clk or posedge reset) begin if (reset) begin byte_address <= 0; end else if (start == 1) begin byte_address <= address[BYTE_ADDRESS_WIDTH-1:0]; end end always @ (posedge clk or posedge reset) begin if (reset) begin last_empty <= 0; end else if (start == 1) begin last_empty <= ((DATA_WIDTH/8) - length[EMPTY_WIDTH-1:0]) & {EMPTY_WIDTH{1'b1}}; // if length isn't a multiple of the word size then we'll have some empty symbols/bytes during the last fifo write end end always @ (posedge clk or posedge reset) begin if (reset) begin extra_access <= 0; end else if (start == 1) begin extra_access <= extra_access_enable; // when set the number of reads and fifo writes are equal, otherwise there will be 1 less fifo write than reads (unaligned accesses only) end end always @ (posedge clk or posedge reset) begin if (reset) begin start_and_end_same_cycle <= 0; end else if (start == 1) begin start_and_end_same_cycle <= (length <= (DATA_WIDTH/8)); end end /* These barrelshifters will take the unaligned data coming into this block and shift the byte lanes appropriately to form a single packed word. Zeros are shifted into the byte lanes that do not contain valid data for the combined word that will be buffered. This allows both barrelshifters to be logically OR'ed together to form a single packed word. Shifter A is used to shift the current read data towards the upper bytes of the combined word (since those are the upper addresses of the combined word). Shifter B after the pipeline stage called 'barrelshifter_B_d1' contains the previously read data shifted towards the lower bytes (since those are the lower addresses of the combined word). */ generate genvar input_offset; for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1) begin: barrel_shifter_inputs assign barrelshifter_input_A[input_offset] = data_in << (8 * ((DATA_WIDTH/8) - input_offset)); assign barrelshifter_input_B[input_offset] = data_in >> (8 * input_offset); end endgenerate assign barrelshifter_A = barrelshifter_input_A[byte_address]; // upper portion of the packed word assign barrelshifter_B = barrelshifter_input_B[byte_address]; // lower portion of the packed word (will be pipelined so it will be the previous word read by the master) assign combined_word = (barrelshifter_A | barrelshifter_B_d1); // barrelshifters shift in zeros so we can just OR the words together here to create a packed word assign first_access_seen_rising_edge = (valid_in == 1) & (first_access_seen == 0); assign second_access_seen_rising_edge = ((first_access_seen == 1) & (valid_in == 1)) & (second_access_seen == 0); assign extra_access_enable = (((DATA_WIDTH/8) - length[EMPTY_WIDTH-1:0]) & {EMPTY_WIDTH{1'b1}}) >= address[BYTE_ADDRESS_WIDTH-1:0]; // enable when empty >= byte address /* Need to keep track of the last write to the FIFO so that we can fire EOP correctly as well as flush the pipeline when unaligned accesses is enabled. The first read is filtered since it is considered to be only a partial word to be written into the FIFO but there are cases when there is extra data that is buffered in 'barrelshifter_B_d1' but the transfer is done so we need to issue an additional write. In general for every 'N' Avalon-MM reads 'N-1' writes to the FIFO will occur unless there is data still buffered in which one more write to the FIFO will immediately follow the last read. */ assign last_unaligned_fifo_write = (reads_pending == 0) & (length_counter == 0) & ( ((extra_access == 0) & (valid_in == 1)) | // don't need a pipeline flush ((extra_access == 1) & (valid_in_d1 == 1) & (valid_in == 0)) ); // last write to flush the pipeline (need to make sure valid_in isn't asserted to make sure the last data is indeed coming since valid_in is pipelined) // This block should be optimized down depending on the packet support or access type settings. In the case where packet support is off // and only full accesses are used this block should become zero logic elements. generate if (PACKET_SUPPORT == 1) begin if (UNALIGNED_ACCESS_ENABLE == 1) begin assign fifo_sop = (second_access_seen_rising_edge == 1) | ((start_and_end_same_cycle == 1) & (last_unaligned_fifo_write == 1)); assign fifo_eop = last_unaligned_fifo_write; assign fifo_empty = (fifo_eop == 1)? last_empty : 0; // always full accesses until the last word end else begin assign fifo_sop = first_access_seen_rising_edge; assign fifo_eop = (length_counter == 0) & (reads_pending == 1) & (valid_in == 1); // not using last_unaligned_fifo_write since it's pipelined and when unaligned accesses are disabled the input is not pipelined if (FULL_WORD_ACCESS_ONLY == 1) begin assign fifo_empty = 0; // full accesses so no empty symbols throughout the transfer end else begin assign fifo_empty = (fifo_eop == 1)? last_empty : 0; // always full accesses until the last word end end end else begin assign fifo_eop = 0; assign fifo_sop = 0; assign fifo_empty = 0; end if (UNALIGNED_ACCESS_ENABLE == 1) begin assign fifo_data = combined_word; assign fifo_write = (first_access_seen == 1) & ((valid_in == 1) | (last_unaligned_fifo_write == 1)); // last_unaligned_fifo_write will inject an extra pulse right after the last read occurs when flushing of the pipeline is needed end else begin // don't need to pipeline since the data will not go through the barrel shifters assign fifo_data = data_in; // don't need to barrelshift when aligned accesses are used assign fifo_write = valid_in; // the number of writes to the fifo needs to always equal the number of reads from memory end endgenerate endmodule
module acl_iface_ll_fifo(clk, reset, data_in, write, data_out, read, empty, full); /* Parameters */ parameter WIDTH = 32; parameter DEPTH = 32; /* Ports */ input clk; input reset; input [WIDTH-1:0] data_in; input write; output [WIDTH-1:0] data_out; input read; output empty; output full; /* Architecture */ // One-hot write-pointer bit (indicates next position to write at), // last bit indicates the FIFO is full reg [DEPTH:0] wptr; // Replicated copy of the stall / valid logic reg [DEPTH:0] wptr_copy /* synthesis dont_merge */; // FIFO data registers reg [DEPTH-1:0][WIDTH-1:0] data; // Write pointer updates: wire wptr_hold; // Hold the value wire wptr_dir; // Direction to shift // Data register updates: wire [DEPTH-1:0] data_hold; // Hold the value wire [DEPTH-1:0] data_new; // Write the new data value in // Write location is constant unless the occupancy changes assign wptr_hold = !(read ^ write); assign wptr_dir = read; // Hold the value unless we are reading, or writing to this // location genvar i; generate for(i = 0; i < DEPTH; i++) begin : data_mux assign data_hold[i] = !(read | (write & wptr[i])); assign data_new[i] = !read | wptr[i+1]; end endgenerate // The data registers generate for(i = 0; i < DEPTH-1; i++) begin : data_reg always@(posedge clk or posedge reset) begin if(reset == 1'b1) data[i] <= {WIDTH{1'b0}}; else data[i] <= data_hold[i] ? data[i] : data_new[i] ? data_in : data[i+1]; end end endgenerate always@(posedge clk or posedge reset) begin if(reset == 1'b1) data[DEPTH-1] <= {WIDTH{1'b0}}; else data[DEPTH-1] <= data_hold[DEPTH-1] ? data[DEPTH-1] : data_in; end // The write pointer always@(posedge clk or posedge reset) begin if(reset == 1'b1) begin wptr <= {{DEPTH{1'b0}}, 1'b1}; wptr_copy <= {{DEPTH{1'b0}}, 1'b1}; end else begin wptr <= wptr_hold ? wptr : wptr_dir ? {1'b0, wptr[DEPTH:1]} : {wptr[DEPTH-1:0], 1'b0}; wptr_copy <= wptr_hold ? wptr_copy : wptr_dir ? {1'b0, wptr_copy[DEPTH:1]} : {wptr_copy[DEPTH-1:0], 1'b0}; end end // Outputs assign empty = wptr_copy[0]; assign full = wptr_copy[DEPTH]; assign data_out = data[0]; endmodule
module acl_iface_ll_fifo(clk, reset, data_in, write, data_out, read, empty, full); /* Parameters */ parameter WIDTH = 32; parameter DEPTH = 32; /* Ports */ input clk; input reset; input [WIDTH-1:0] data_in; input write; output [WIDTH-1:0] data_out; input read; output empty; output full; /* Architecture */ // One-hot write-pointer bit (indicates next position to write at), // last bit indicates the FIFO is full reg [DEPTH:0] wptr; // Replicated copy of the stall / valid logic reg [DEPTH:0] wptr_copy /* synthesis dont_merge */; // FIFO data registers reg [DEPTH-1:0][WIDTH-1:0] data; // Write pointer updates: wire wptr_hold; // Hold the value wire wptr_dir; // Direction to shift // Data register updates: wire [DEPTH-1:0] data_hold; // Hold the value wire [DEPTH-1:0] data_new; // Write the new data value in // Write location is constant unless the occupancy changes assign wptr_hold = !(read ^ write); assign wptr_dir = read; // Hold the value unless we are reading, or writing to this // location genvar i; generate for(i = 0; i < DEPTH; i++) begin : data_mux assign data_hold[i] = !(read | (write & wptr[i])); assign data_new[i] = !read | wptr[i+1]; end endgenerate // The data registers generate for(i = 0; i < DEPTH-1; i++) begin : data_reg always@(posedge clk or posedge reset) begin if(reset == 1'b1) data[i] <= {WIDTH{1'b0}}; else data[i] <= data_hold[i] ? data[i] : data_new[i] ? data_in : data[i+1]; end end endgenerate always@(posedge clk or posedge reset) begin if(reset == 1'b1) data[DEPTH-1] <= {WIDTH{1'b0}}; else data[DEPTH-1] <= data_hold[DEPTH-1] ? data[DEPTH-1] : data_in; end // The write pointer always@(posedge clk or posedge reset) begin if(reset == 1'b1) begin wptr <= {{DEPTH{1'b0}}, 1'b1}; wptr_copy <= {{DEPTH{1'b0}}, 1'b1}; end else begin wptr <= wptr_hold ? wptr : wptr_dir ? {1'b0, wptr[DEPTH:1]} : {wptr[DEPTH-1:0], 1'b0}; wptr_copy <= wptr_hold ? wptr_copy : wptr_dir ? {1'b0, wptr_copy[DEPTH:1]} : {wptr_copy[DEPTH-1:0], 1'b0}; end end // Outputs assign empty = wptr_copy[0]; assign full = wptr_copy[DEPTH]; assign data_out = data[0]; endmodule
module snoop_adapter ( clk, reset, kernel_clk, kernel_reset, address, read, readdata, readdatavalid, write, writedata, burstcount, byteenable, waitrequest, burstbegin, snoop_data, snoop_valid, snoop_ready, export_address, export_read, export_readdata, export_readdatavalid, export_write, export_writedata, export_burstcount, export_burstbegin, export_byteenable, export_waitrequest ); parameter NUM_BYTES = 4; parameter BYTE_ADDRESS_WIDTH = 32; parameter WORD_ADDRESS_WIDTH = 32; parameter BURSTCOUNT_WIDTH = 1; localparam DATA_WIDTH = NUM_BYTES * 8; localparam ADDRESS_SHIFT = BYTE_ADDRESS_WIDTH - WORD_ADDRESS_WIDTH; localparam DEVICE_BLOCKRAM_MIN_DEPTH = 256; //Stratix IV M9Ks localparam FIFO_SIZE = DEVICE_BLOCKRAM_MIN_DEPTH; localparam LOG2_FIFO_SIZE =$clog2(FIFO_SIZE); input clk; input reset; input kernel_clk; input kernel_reset; input [WORD_ADDRESS_WIDTH-1:0] address; input read; output [DATA_WIDTH-1:0] readdata; output readdatavalid; input write; input [DATA_WIDTH-1:0] writedata; input [BURSTCOUNT_WIDTH-1:0] burstcount; input burstbegin; input [NUM_BYTES-1:0] byteenable; output waitrequest; output [1+WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0] snoop_data; output snoop_valid; input snoop_ready; output [BYTE_ADDRESS_WIDTH-1:0] export_address; output export_read; input [DATA_WIDTH-1:0] export_readdata; input export_readdatavalid; output export_write; output [DATA_WIDTH-1:0] export_writedata; output [BURSTCOUNT_WIDTH-1:0] export_burstcount; output export_burstbegin; output [NUM_BYTES-1:0] export_byteenable; input export_waitrequest; reg snoop_overflow; // Register snoop data first reg [WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0] snoop_data_r; //word-address reg snoop_valid_r; wire snoop_fifo_empty; wire overflow; wire [ LOG2_FIFO_SIZE-1 : 0 ] rdusedw; always@(posedge clk) begin snoop_data_r<={address,export_burstcount}; snoop_valid_r<=export_write && !export_waitrequest; end // 1) Fifo to store snooped accesses from host dcfifo dcfifo_component ( .wrclk (clk), .data (snoop_data_r), .wrreq (snoop_valid_r), .rdclk (kernel_clk), .rdreq (snoop_valid & snoop_ready), .q (snoop_data[WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0]), .rdempty (snoop_fifo_empty), .rdfull (overflow), .aclr (1'b0), .rdusedw (rdusedw), .wrempty (), .wrfull (), .wrusedw ()); defparam dcfifo_component.intended_device_family = "Stratix IV", dcfifo_component.lpm_numwords = FIFO_SIZE, dcfifo_component.lpm_showahead = "ON", dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH, dcfifo_component.lpm_widthu = LOG2_FIFO_SIZE, dcfifo_component.overflow_checking = "ON", dcfifo_component.rdsync_delaypipe = 4, dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON", dcfifo_component.wrsync_delaypipe = 4; assign snoop_valid=~snoop_fifo_empty; always@(posedge kernel_clk) snoop_overflow = ( rdusedw >= ( FIFO_SIZE - 12 ) ); // Overflow piggy backed onto MSB of stream. Since overflow guarantees // there is something to be read out, we can be sure that this will reach // the cache. assign snoop_data[WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH] = snoop_overflow; assign export_address = address << ADDRESS_SHIFT; assign export_read = read; assign readdata = export_readdata; assign readdatavalid = export_readdatavalid; assign export_write = write; assign export_writedata = writedata; assign export_burstcount = burstcount; assign export_burstbegin = burstbegin; assign export_byteenable = byteenable; assign waitrequest = export_waitrequest; endmodule
module snoop_adapter ( clk, reset, kernel_clk, kernel_reset, address, read, readdata, readdatavalid, write, writedata, burstcount, byteenable, waitrequest, burstbegin, snoop_data, snoop_valid, snoop_ready, export_address, export_read, export_readdata, export_readdatavalid, export_write, export_writedata, export_burstcount, export_burstbegin, export_byteenable, export_waitrequest ); parameter NUM_BYTES = 4; parameter BYTE_ADDRESS_WIDTH = 32; parameter WORD_ADDRESS_WIDTH = 32; parameter BURSTCOUNT_WIDTH = 1; localparam DATA_WIDTH = NUM_BYTES * 8; localparam ADDRESS_SHIFT = BYTE_ADDRESS_WIDTH - WORD_ADDRESS_WIDTH; localparam DEVICE_BLOCKRAM_MIN_DEPTH = 256; //Stratix IV M9Ks localparam FIFO_SIZE = DEVICE_BLOCKRAM_MIN_DEPTH; localparam LOG2_FIFO_SIZE =$clog2(FIFO_SIZE); input clk; input reset; input kernel_clk; input kernel_reset; input [WORD_ADDRESS_WIDTH-1:0] address; input read; output [DATA_WIDTH-1:0] readdata; output readdatavalid; input write; input [DATA_WIDTH-1:0] writedata; input [BURSTCOUNT_WIDTH-1:0] burstcount; input burstbegin; input [NUM_BYTES-1:0] byteenable; output waitrequest; output [1+WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0] snoop_data; output snoop_valid; input snoop_ready; output [BYTE_ADDRESS_WIDTH-1:0] export_address; output export_read; input [DATA_WIDTH-1:0] export_readdata; input export_readdatavalid; output export_write; output [DATA_WIDTH-1:0] export_writedata; output [BURSTCOUNT_WIDTH-1:0] export_burstcount; output export_burstbegin; output [NUM_BYTES-1:0] export_byteenable; input export_waitrequest; reg snoop_overflow; // Register snoop data first reg [WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0] snoop_data_r; //word-address reg snoop_valid_r; wire snoop_fifo_empty; wire overflow; wire [ LOG2_FIFO_SIZE-1 : 0 ] rdusedw; always@(posedge clk) begin snoop_data_r<={address,export_burstcount}; snoop_valid_r<=export_write && !export_waitrequest; end // 1) Fifo to store snooped accesses from host dcfifo dcfifo_component ( .wrclk (clk), .data (snoop_data_r), .wrreq (snoop_valid_r), .rdclk (kernel_clk), .rdreq (snoop_valid & snoop_ready), .q (snoop_data[WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0]), .rdempty (snoop_fifo_empty), .rdfull (overflow), .aclr (1'b0), .rdusedw (rdusedw), .wrempty (), .wrfull (), .wrusedw ()); defparam dcfifo_component.intended_device_family = "Stratix IV", dcfifo_component.lpm_numwords = FIFO_SIZE, dcfifo_component.lpm_showahead = "ON", dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH, dcfifo_component.lpm_widthu = LOG2_FIFO_SIZE, dcfifo_component.overflow_checking = "ON", dcfifo_component.rdsync_delaypipe = 4, dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON", dcfifo_component.wrsync_delaypipe = 4; assign snoop_valid=~snoop_fifo_empty; always@(posedge kernel_clk) snoop_overflow = ( rdusedw >= ( FIFO_SIZE - 12 ) ); // Overflow piggy backed onto MSB of stream. Since overflow guarantees // there is something to be read out, we can be sure that this will reach // the cache. assign snoop_data[WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH] = snoop_overflow; assign export_address = address << ADDRESS_SHIFT; assign export_read = read; assign readdata = export_readdata; assign readdatavalid = export_readdatavalid; assign export_write = write; assign export_writedata = writedata; assign export_burstcount = burstcount; assign export_burstbegin = burstbegin; assign export_byteenable = byteenable; assign waitrequest = export_waitrequest; endmodule
module generic_baseblocks_v2_1_0_comparator_sel_mask # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire S, input wire [C_DATA_WIDTH-1:0] A, input wire [C_DATA_WIDTH-1:0] B, input wire [C_DATA_WIDTH-1:0] M, input wire [C_DATA_WIDTH-1:0] V, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar lut_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 1; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_FIX_DATA_WIDTH-1:0] m_local; wire [C_FIX_DATA_WIDTH-1:0] v_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = B; assign m_local = M; assign v_local = V; end // Instantiate one generic_baseblocks_v2_1_0_carry and per level. for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) | ( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) ); // Instantiate each LUT level. generic_baseblocks_v2_1_0_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[lut_cnt+1]), .CIN (carry_local[lut_cnt]), .S (sel[lut_cnt]) ); end // end for lut_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule
module generic_baseblocks_v2_1_0_comparator_sel_mask # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire S, input wire [C_DATA_WIDTH-1:0] A, input wire [C_DATA_WIDTH-1:0] B, input wire [C_DATA_WIDTH-1:0] M, input wire [C_DATA_WIDTH-1:0] V, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar lut_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 1; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_FIX_DATA_WIDTH-1:0] m_local; wire [C_FIX_DATA_WIDTH-1:0] v_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = B; assign m_local = M; assign v_local = V; end // Instantiate one generic_baseblocks_v2_1_0_carry and per level. for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) | ( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) ); // Instantiate each LUT level. generic_baseblocks_v2_1_0_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[lut_cnt+1]), .CIN (carry_local[lut_cnt]), .S (sel[lut_cnt]) ); end // end for lut_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule
module generic_baseblocks_v2_1_0_comparator_sel_mask # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire S, input wire [C_DATA_WIDTH-1:0] A, input wire [C_DATA_WIDTH-1:0] B, input wire [C_DATA_WIDTH-1:0] M, input wire [C_DATA_WIDTH-1:0] V, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar lut_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 1; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_FIX_DATA_WIDTH-1:0] m_local; wire [C_FIX_DATA_WIDTH-1:0] v_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = B; assign m_local = M; assign v_local = V; end // Instantiate one generic_baseblocks_v2_1_0_carry and per level. for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) | ( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) ); // Instantiate each LUT level. generic_baseblocks_v2_1_0_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[lut_cnt+1]), .CIN (carry_local[lut_cnt]), .S (sel[lut_cnt]) ); end // end for lut_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule
module generic_baseblocks_v2_1_0_comparator_mask # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire [C_DATA_WIDTH-1:0] A, input wire [C_DATA_WIDTH-1:0] B, input wire [C_DATA_WIDTH-1:0] M, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar lut_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 2; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_FIX_DATA_WIDTH-1:0] m_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = B; assign m_local = M; end // Instantiate one generic_baseblocks_v2_1_0_carry and per level. for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ); // Instantiate each LUT level. generic_baseblocks_v2_1_0_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[lut_cnt+1]), .CIN (carry_local[lut_cnt]), .S (sel[lut_cnt]) ); end // end for lut_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule
module generic_baseblocks_v2_1_0_comparator_mask # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire [C_DATA_WIDTH-1:0] A, input wire [C_DATA_WIDTH-1:0] B, input wire [C_DATA_WIDTH-1:0] M, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar lut_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 2; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_FIX_DATA_WIDTH-1:0] m_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = B; assign m_local = M; end // Instantiate one generic_baseblocks_v2_1_0_carry and per level. for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ); // Instantiate each LUT level. generic_baseblocks_v2_1_0_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[lut_cnt+1]), .CIN (carry_local[lut_cnt]), .S (sel[lut_cnt]) ); end // end for lut_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule
module generic_baseblocks_v2_1_0_comparator_mask # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire [C_DATA_WIDTH-1:0] A, input wire [C_DATA_WIDTH-1:0] B, input wire [C_DATA_WIDTH-1:0] M, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar lut_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 2; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_FIX_DATA_WIDTH-1:0] m_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = B; assign m_local = M; end // Instantiate one generic_baseblocks_v2_1_0_carry and per level. for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ); // Instantiate each LUT level. generic_baseblocks_v2_1_0_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[lut_cnt+1]), .CIN (carry_local[lut_cnt]), .S (sel[lut_cnt]) ); end // end for lut_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule
module generic_baseblocks_v2_1_0_comparator_sel # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire S, input wire [C_DATA_WIDTH-1:0] A, input wire [C_DATA_WIDTH-1:0] B, input wire [C_DATA_WIDTH-1:0] V, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar bit_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 1; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_FIX_DATA_WIDTH-1:0] v_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = B; assign v_local = V; end // Instantiate one generic_baseblocks_v2_1_0_carry and per level. for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) | ( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) ); // Instantiate each LUT level. generic_baseblocks_v2_1_0_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[bit_cnt+1]), .CIN (carry_local[bit_cnt]), .S (sel[bit_cnt]) ); end // end for bit_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule
module generic_baseblocks_v2_1_0_comparator_sel # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire S, input wire [C_DATA_WIDTH-1:0] A, input wire [C_DATA_WIDTH-1:0] B, input wire [C_DATA_WIDTH-1:0] V, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar bit_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 1; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_FIX_DATA_WIDTH-1:0] v_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = B; assign v_local = V; end // Instantiate one generic_baseblocks_v2_1_0_carry and per level. for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) | ( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) ); // Instantiate each LUT level. generic_baseblocks_v2_1_0_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[bit_cnt+1]), .CIN (carry_local[bit_cnt]), .S (sel[bit_cnt]) ); end // end for bit_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule
module uses it .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end else if (BYTEENABLE_WIDTH == 4) begin thirty_two_bit_byteenable_FSM the_thirty_two_bit_byteenable_FSM( .clk (clk), .reset (reset), .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end else if (BYTEENABLE_WIDTH == 8) begin sixty_four_bit_byteenable_FSM the_sixty_four_bit_byteenable_FSM( .clk (clk), .reset (reset), .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end else if (BYTEENABLE_WIDTH == 16) begin one_hundred_twenty_eight_bit_byteenable_FSM the_one_hundred_twenty_eight_bit_byteenable_FSM( .clk (clk), .reset (reset), .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end else if (BYTEENABLE_WIDTH == 32) begin two_hundred_fifty_six_bit_byteenable_FSM the_two_hundred_fifty_six_bit_byteenable_FSM( .clk (clk), .reset (reset), .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end else if (BYTEENABLE_WIDTH == 64) begin five_hundred_twelve_bit_byteenable_FSM the_five_hundred_twelve_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end else if (BYTEENABLE_WIDTH == 128) begin one_thousand_twenty_four_byteenable_FSM the_one_thousand_twenty_four_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end endgenerate endmodule
module one_thousand_twenty_four_byteenable_FSM ( clk, reset, write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input clk; input reset; input write_in; input [127:0] byteenable_in; output wire waitrequest_out; output wire [127:0] byteenable_out; input waitrequest_in; // internal statemachine signals wire partial_lower_half_transfer; wire full_lower_half_transfer; wire partial_upper_half_transfer; wire full_upper_half_transfer; wire full_word_transfer; reg state_bit; wire transfer_done; wire advance_to_next_state; wire lower_enable; wire upper_enable; wire lower_stall; wire upper_stall; wire two_stage_transfer; always @ (posedge clk or posedge reset) begin if (reset) begin state_bit <= 0; end else begin if (transfer_done == 1) begin state_bit <= 0; end else if (advance_to_next_state == 1) begin state_bit <= 1; end end end assign partial_lower_half_transfer = (byteenable_in[63:0] != 0); assign full_lower_half_transfer = (byteenable_in[63:0] == 64'hFFFFFFFFFFFFFFFF); assign partial_upper_half_transfer = (byteenable_in[127:64] != 0); assign full_upper_half_transfer = (byteenable_in[127:64] == 64'hFFFFFFFFFFFFFFFF); assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1); assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1); assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer) assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer) five_hundred_twelve_bit_byteenable_FSM lower_five_hundred_twelve_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (lower_enable), .byteenable_in (byteenable_in[63:0]), .waitrequest_out (lower_stall), .byteenable_out (byteenable_out[63:0]), .waitrequest_in (waitrequest_in) ); five_hundred_twelve_bit_byteenable_FSM upper_five_hundred_twelve_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (upper_enable), .byteenable_in (byteenable_in[127:64]), .waitrequest_out (upper_stall), .byteenable_out (byteenable_out[127:64]), .waitrequest_in (waitrequest_in) ); assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1)); endmodule
module five_hundred_twelve_bit_byteenable_FSM ( clk, reset, write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input clk; input reset; input write_in; input [63:0] byteenable_in; output wire waitrequest_out; output wire [63:0] byteenable_out; input waitrequest_in; // internal statemachine signals wire partial_lower_half_transfer; wire full_lower_half_transfer; wire partial_upper_half_transfer; wire full_upper_half_transfer; wire full_word_transfer; reg state_bit; wire transfer_done; wire advance_to_next_state; wire lower_enable; wire upper_enable; wire lower_stall; wire upper_stall; wire two_stage_transfer; always @ (posedge clk or posedge reset) begin if (reset) begin state_bit <= 0; end else begin if (transfer_done == 1) begin state_bit <= 0; end else if (advance_to_next_state == 1) begin state_bit <= 1; end end end assign partial_lower_half_transfer = (byteenable_in[31:0] != 0); assign full_lower_half_transfer = (byteenable_in[31:0] == 32'hFFFFFFFF); assign partial_upper_half_transfer = (byteenable_in[63:32] != 0); assign full_upper_half_transfer = (byteenable_in[63:32] == 32'hFFFFFFFF); assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1); assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1); assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer) assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer) two_hundred_fifty_six_bit_byteenable_FSM lower_two_hundred_fifty_six_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (lower_enable), .byteenable_in (byteenable_in[31:0]), .waitrequest_out (lower_stall), .byteenable_out (byteenable_out[31:0]), .waitrequest_in (waitrequest_in) ); two_hundred_fifty_six_bit_byteenable_FSM upper_two_hundred_fifty_six_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (upper_enable), .byteenable_in (byteenable_in[63:32]), .waitrequest_out (upper_stall), .byteenable_out (byteenable_out[63:32]), .waitrequest_in (waitrequest_in) ); assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1)); endmodule
module two_hundred_fifty_six_bit_byteenable_FSM ( clk, reset, write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input clk; input reset; input write_in; input [31:0] byteenable_in; output wire waitrequest_out; output wire [31:0] byteenable_out; input waitrequest_in; // internal statemachine signals wire partial_lower_half_transfer; wire full_lower_half_transfer; wire partial_upper_half_transfer; wire full_upper_half_transfer; wire full_word_transfer; reg state_bit; wire transfer_done; wire advance_to_next_state; wire lower_enable; wire upper_enable; wire lower_stall; wire upper_stall; wire two_stage_transfer; always @ (posedge clk or posedge reset) begin if (reset) begin state_bit <= 0; end else begin if (transfer_done == 1) begin state_bit <= 0; end else if (advance_to_next_state == 1) begin state_bit <= 1; end end end assign partial_lower_half_transfer = (byteenable_in[15:0] != 0); assign full_lower_half_transfer = (byteenable_in[15:0] == 16'hFFFF); assign partial_upper_half_transfer = (byteenable_in[31:16] != 0); assign full_upper_half_transfer = (byteenable_in[31:16] == 16'hFFFF); assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1); assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1); assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer) assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer) one_hundred_twenty_eight_bit_byteenable_FSM lower_one_hundred_twenty_eight_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (lower_enable), .byteenable_in (byteenable_in[15:0]), .waitrequest_out (lower_stall), .byteenable_out (byteenable_out[15:0]), .waitrequest_in (waitrequest_in) ); one_hundred_twenty_eight_bit_byteenable_FSM upper_one_hundred_twenty_eight_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (upper_enable), .byteenable_in (byteenable_in[31:16]), .waitrequest_out (upper_stall), .byteenable_out (byteenable_out[31:16]), .waitrequest_in (waitrequest_in) ); assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1)); endmodule
module one_hundred_twenty_eight_bit_byteenable_FSM ( clk, reset, write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input clk; input reset; input write_in; input [15:0] byteenable_in; output wire waitrequest_out; output wire [15:0] byteenable_out; input waitrequest_in; // internal statemachine signals wire partial_lower_half_transfer; wire full_lower_half_transfer; wire partial_upper_half_transfer; wire full_upper_half_transfer; wire full_word_transfer; reg state_bit; wire transfer_done; wire advance_to_next_state; wire lower_enable; wire upper_enable; wire lower_stall; wire upper_stall; wire two_stage_transfer; always @ (posedge clk or posedge reset) begin if (reset) begin state_bit <= 0; end else begin if (transfer_done == 1) begin state_bit <= 0; end else if (advance_to_next_state == 1) begin state_bit <= 1; end end end assign partial_lower_half_transfer = (byteenable_in[7:0] != 0); assign full_lower_half_transfer = (byteenable_in[7:0] == 8'hFF); assign partial_upper_half_transfer = (byteenable_in[15:8] != 0); assign full_upper_half_transfer = (byteenable_in[15:8] == 8'hFF); assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1); assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1); assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer) assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer) sixty_four_bit_byteenable_FSM lower_sixty_four_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (lower_enable), .byteenable_in (byteenable_in[7:0]), .waitrequest_out (lower_stall), .byteenable_out (byteenable_out[7:0]), .waitrequest_in (waitrequest_in) ); sixty_four_bit_byteenable_FSM upper_sixty_four_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (upper_enable), .byteenable_in (byteenable_in[15:8]), .waitrequest_out (upper_stall), .byteenable_out (byteenable_out[15:8]), .waitrequest_in (waitrequest_in) ); assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1)); endmodule
module sixty_four_bit_byteenable_FSM ( clk, reset, write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input clk; input reset; input write_in; input [7:0] byteenable_in; output wire waitrequest_out; output wire [7:0] byteenable_out; input waitrequest_in; // internal statemachine signals wire partial_lower_half_transfer; wire full_lower_half_transfer; wire partial_upper_half_transfer; wire full_upper_half_transfer; wire full_word_transfer; reg state_bit; wire transfer_done; wire advance_to_next_state; wire lower_enable; wire upper_enable; wire lower_stall; wire upper_stall; wire two_stage_transfer; always @ (posedge clk or posedge reset) begin if (reset) begin state_bit <= 0; end else begin if (transfer_done == 1) begin state_bit <= 0; end else if (advance_to_next_state == 1) begin state_bit <= 1; end end end assign partial_lower_half_transfer = (byteenable_in[3:0] != 0); assign full_lower_half_transfer = (byteenable_in[3:0] == 4'hF); assign partial_upper_half_transfer = (byteenable_in[7:4] != 0); assign full_upper_half_transfer = (byteenable_in[7:4] == 4'hF); assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1); assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1); assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer) assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer) thirty_two_bit_byteenable_FSM lower_thirty_two_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (lower_enable), .byteenable_in (byteenable_in[3:0]), .waitrequest_out (lower_stall), .byteenable_out (byteenable_out[3:0]), .waitrequest_in (waitrequest_in) ); thirty_two_bit_byteenable_FSM upper_thirty_two_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (upper_enable), .byteenable_in (byteenable_in[7:4]), .waitrequest_out (upper_stall), .byteenable_out (byteenable_out[7:4]), .waitrequest_in (waitrequest_in) ); assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1)); endmodule
module thirty_two_bit_byteenable_FSM ( clk, reset, write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input clk; input reset; input write_in; input [3:0] byteenable_in; output wire waitrequest_out; output wire [3:0] byteenable_out; input waitrequest_in; // internal statemachine signals wire partial_lower_half_transfer; wire full_lower_half_transfer; wire partial_upper_half_transfer; wire full_upper_half_transfer; wire full_word_transfer; reg state_bit; wire transfer_done; wire advance_to_next_state; wire lower_enable; wire upper_enable; wire lower_stall; wire upper_stall; wire two_stage_transfer; always @ (posedge clk or posedge reset) begin if (reset) begin state_bit <= 0; end else begin if (transfer_done == 1) begin state_bit <= 0; end else if (advance_to_next_state == 1) begin state_bit <= 1; end end end assign partial_lower_half_transfer = (byteenable_in[1:0] != 0); assign full_lower_half_transfer = (byteenable_in[1:0] == 2'h3); assign partial_upper_half_transfer = (byteenable_in[3:2] != 0); assign full_upper_half_transfer = (byteenable_in[3:2] == 2'h3); assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1); assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1); assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer) assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer) sixteen_bit_byteenable_FSM lower_sixteen_bit_byteenable_FSM ( .write_in (lower_enable), .byteenable_in (byteenable_in[1:0]), .waitrequest_out (lower_stall), .byteenable_out (byteenable_out[1:0]), .waitrequest_in (waitrequest_in) ); sixteen_bit_byteenable_FSM upper_sixteen_bit_byteenable_FSM ( .write_in (upper_enable), .byteenable_in (byteenable_in[3:2]), .waitrequest_out (upper_stall), .byteenable_out (byteenable_out[3:2]), .waitrequest_in (waitrequest_in) ); assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1)); endmodule
module sixteen_bit_byteenable_FSM ( write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input write_in; input [1:0] byteenable_in; output wire waitrequest_out; output wire [1:0] byteenable_out; input waitrequest_in; assign byteenable_out = byteenable_in & {2{write_in}}; // all 2 bit byte enable pairs are supported, masked with write in to turn the byte lanes off when writing is disabled assign waitrequest_out = (write_in == 1) & (waitrequest_in == 1); // transfer always completes on the first cycle unless waitrequest is asserted endmodule
module uses it .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end else if (BYTEENABLE_WIDTH == 4) begin thirty_two_bit_byteenable_FSM the_thirty_two_bit_byteenable_FSM( .clk (clk), .reset (reset), .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end else if (BYTEENABLE_WIDTH == 8) begin sixty_four_bit_byteenable_FSM the_sixty_four_bit_byteenable_FSM( .clk (clk), .reset (reset), .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end else if (BYTEENABLE_WIDTH == 16) begin one_hundred_twenty_eight_bit_byteenable_FSM the_one_hundred_twenty_eight_bit_byteenable_FSM( .clk (clk), .reset (reset), .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end else if (BYTEENABLE_WIDTH == 32) begin two_hundred_fifty_six_bit_byteenable_FSM the_two_hundred_fifty_six_bit_byteenable_FSM( .clk (clk), .reset (reset), .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end else if (BYTEENABLE_WIDTH == 64) begin five_hundred_twelve_bit_byteenable_FSM the_five_hundred_twelve_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end else if (BYTEENABLE_WIDTH == 128) begin one_thousand_twenty_four_byteenable_FSM the_one_thousand_twenty_four_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end endgenerate endmodule
module one_thousand_twenty_four_byteenable_FSM ( clk, reset, write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input clk; input reset; input write_in; input [127:0] byteenable_in; output wire waitrequest_out; output wire [127:0] byteenable_out; input waitrequest_in; // internal statemachine signals wire partial_lower_half_transfer; wire full_lower_half_transfer; wire partial_upper_half_transfer; wire full_upper_half_transfer; wire full_word_transfer; reg state_bit; wire transfer_done; wire advance_to_next_state; wire lower_enable; wire upper_enable; wire lower_stall; wire upper_stall; wire two_stage_transfer; always @ (posedge clk or posedge reset) begin if (reset) begin state_bit <= 0; end else begin if (transfer_done == 1) begin state_bit <= 0; end else if (advance_to_next_state == 1) begin state_bit <= 1; end end end assign partial_lower_half_transfer = (byteenable_in[63:0] != 0); assign full_lower_half_transfer = (byteenable_in[63:0] == 64'hFFFFFFFFFFFFFFFF); assign partial_upper_half_transfer = (byteenable_in[127:64] != 0); assign full_upper_half_transfer = (byteenable_in[127:64] == 64'hFFFFFFFFFFFFFFFF); assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1); assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1); assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer) assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer) five_hundred_twelve_bit_byteenable_FSM lower_five_hundred_twelve_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (lower_enable), .byteenable_in (byteenable_in[63:0]), .waitrequest_out (lower_stall), .byteenable_out (byteenable_out[63:0]), .waitrequest_in (waitrequest_in) ); five_hundred_twelve_bit_byteenable_FSM upper_five_hundred_twelve_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (upper_enable), .byteenable_in (byteenable_in[127:64]), .waitrequest_out (upper_stall), .byteenable_out (byteenable_out[127:64]), .waitrequest_in (waitrequest_in) ); assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1)); endmodule
module five_hundred_twelve_bit_byteenable_FSM ( clk, reset, write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input clk; input reset; input write_in; input [63:0] byteenable_in; output wire waitrequest_out; output wire [63:0] byteenable_out; input waitrequest_in; // internal statemachine signals wire partial_lower_half_transfer; wire full_lower_half_transfer; wire partial_upper_half_transfer; wire full_upper_half_transfer; wire full_word_transfer; reg state_bit; wire transfer_done; wire advance_to_next_state; wire lower_enable; wire upper_enable; wire lower_stall; wire upper_stall; wire two_stage_transfer; always @ (posedge clk or posedge reset) begin if (reset) begin state_bit <= 0; end else begin if (transfer_done == 1) begin state_bit <= 0; end else if (advance_to_next_state == 1) begin state_bit <= 1; end end end assign partial_lower_half_transfer = (byteenable_in[31:0] != 0); assign full_lower_half_transfer = (byteenable_in[31:0] == 32'hFFFFFFFF); assign partial_upper_half_transfer = (byteenable_in[63:32] != 0); assign full_upper_half_transfer = (byteenable_in[63:32] == 32'hFFFFFFFF); assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1); assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1); assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer) assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer) two_hundred_fifty_six_bit_byteenable_FSM lower_two_hundred_fifty_six_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (lower_enable), .byteenable_in (byteenable_in[31:0]), .waitrequest_out (lower_stall), .byteenable_out (byteenable_out[31:0]), .waitrequest_in (waitrequest_in) ); two_hundred_fifty_six_bit_byteenable_FSM upper_two_hundred_fifty_six_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (upper_enable), .byteenable_in (byteenable_in[63:32]), .waitrequest_out (upper_stall), .byteenable_out (byteenable_out[63:32]), .waitrequest_in (waitrequest_in) ); assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1)); endmodule
module two_hundred_fifty_six_bit_byteenable_FSM ( clk, reset, write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input clk; input reset; input write_in; input [31:0] byteenable_in; output wire waitrequest_out; output wire [31:0] byteenable_out; input waitrequest_in; // internal statemachine signals wire partial_lower_half_transfer; wire full_lower_half_transfer; wire partial_upper_half_transfer; wire full_upper_half_transfer; wire full_word_transfer; reg state_bit; wire transfer_done; wire advance_to_next_state; wire lower_enable; wire upper_enable; wire lower_stall; wire upper_stall; wire two_stage_transfer; always @ (posedge clk or posedge reset) begin if (reset) begin state_bit <= 0; end else begin if (transfer_done == 1) begin state_bit <= 0; end else if (advance_to_next_state == 1) begin state_bit <= 1; end end end assign partial_lower_half_transfer = (byteenable_in[15:0] != 0); assign full_lower_half_transfer = (byteenable_in[15:0] == 16'hFFFF); assign partial_upper_half_transfer = (byteenable_in[31:16] != 0); assign full_upper_half_transfer = (byteenable_in[31:16] == 16'hFFFF); assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1); assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1); assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer) assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer) one_hundred_twenty_eight_bit_byteenable_FSM lower_one_hundred_twenty_eight_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (lower_enable), .byteenable_in (byteenable_in[15:0]), .waitrequest_out (lower_stall), .byteenable_out (byteenable_out[15:0]), .waitrequest_in (waitrequest_in) ); one_hundred_twenty_eight_bit_byteenable_FSM upper_one_hundred_twenty_eight_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (upper_enable), .byteenable_in (byteenable_in[31:16]), .waitrequest_out (upper_stall), .byteenable_out (byteenable_out[31:16]), .waitrequest_in (waitrequest_in) ); assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1)); endmodule
module one_hundred_twenty_eight_bit_byteenable_FSM ( clk, reset, write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input clk; input reset; input write_in; input [15:0] byteenable_in; output wire waitrequest_out; output wire [15:0] byteenable_out; input waitrequest_in; // internal statemachine signals wire partial_lower_half_transfer; wire full_lower_half_transfer; wire partial_upper_half_transfer; wire full_upper_half_transfer; wire full_word_transfer; reg state_bit; wire transfer_done; wire advance_to_next_state; wire lower_enable; wire upper_enable; wire lower_stall; wire upper_stall; wire two_stage_transfer; always @ (posedge clk or posedge reset) begin if (reset) begin state_bit <= 0; end else begin if (transfer_done == 1) begin state_bit <= 0; end else if (advance_to_next_state == 1) begin state_bit <= 1; end end end assign partial_lower_half_transfer = (byteenable_in[7:0] != 0); assign full_lower_half_transfer = (byteenable_in[7:0] == 8'hFF); assign partial_upper_half_transfer = (byteenable_in[15:8] != 0); assign full_upper_half_transfer = (byteenable_in[15:8] == 8'hFF); assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1); assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1); assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer) assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer) sixty_four_bit_byteenable_FSM lower_sixty_four_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (lower_enable), .byteenable_in (byteenable_in[7:0]), .waitrequest_out (lower_stall), .byteenable_out (byteenable_out[7:0]), .waitrequest_in (waitrequest_in) ); sixty_four_bit_byteenable_FSM upper_sixty_four_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (upper_enable), .byteenable_in (byteenable_in[15:8]), .waitrequest_out (upper_stall), .byteenable_out (byteenable_out[15:8]), .waitrequest_in (waitrequest_in) ); assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1)); endmodule
module sixty_four_bit_byteenable_FSM ( clk, reset, write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input clk; input reset; input write_in; input [7:0] byteenable_in; output wire waitrequest_out; output wire [7:0] byteenable_out; input waitrequest_in; // internal statemachine signals wire partial_lower_half_transfer; wire full_lower_half_transfer; wire partial_upper_half_transfer; wire full_upper_half_transfer; wire full_word_transfer; reg state_bit; wire transfer_done; wire advance_to_next_state; wire lower_enable; wire upper_enable; wire lower_stall; wire upper_stall; wire two_stage_transfer; always @ (posedge clk or posedge reset) begin if (reset) begin state_bit <= 0; end else begin if (transfer_done == 1) begin state_bit <= 0; end else if (advance_to_next_state == 1) begin state_bit <= 1; end end end assign partial_lower_half_transfer = (byteenable_in[3:0] != 0); assign full_lower_half_transfer = (byteenable_in[3:0] == 4'hF); assign partial_upper_half_transfer = (byteenable_in[7:4] != 0); assign full_upper_half_transfer = (byteenable_in[7:4] == 4'hF); assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1); assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1); assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer) assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer) thirty_two_bit_byteenable_FSM lower_thirty_two_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (lower_enable), .byteenable_in (byteenable_in[3:0]), .waitrequest_out (lower_stall), .byteenable_out (byteenable_out[3:0]), .waitrequest_in (waitrequest_in) ); thirty_two_bit_byteenable_FSM upper_thirty_two_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (upper_enable), .byteenable_in (byteenable_in[7:4]), .waitrequest_out (upper_stall), .byteenable_out (byteenable_out[7:4]), .waitrequest_in (waitrequest_in) ); assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1)); endmodule
module thirty_two_bit_byteenable_FSM ( clk, reset, write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input clk; input reset; input write_in; input [3:0] byteenable_in; output wire waitrequest_out; output wire [3:0] byteenable_out; input waitrequest_in; // internal statemachine signals wire partial_lower_half_transfer; wire full_lower_half_transfer; wire partial_upper_half_transfer; wire full_upper_half_transfer; wire full_word_transfer; reg state_bit; wire transfer_done; wire advance_to_next_state; wire lower_enable; wire upper_enable; wire lower_stall; wire upper_stall; wire two_stage_transfer; always @ (posedge clk or posedge reset) begin if (reset) begin state_bit <= 0; end else begin if (transfer_done == 1) begin state_bit <= 0; end else if (advance_to_next_state == 1) begin state_bit <= 1; end end end assign partial_lower_half_transfer = (byteenable_in[1:0] != 0); assign full_lower_half_transfer = (byteenable_in[1:0] == 2'h3); assign partial_upper_half_transfer = (byteenable_in[3:2] != 0); assign full_upper_half_transfer = (byteenable_in[3:2] == 2'h3); assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1); assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1); assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer) assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer) sixteen_bit_byteenable_FSM lower_sixteen_bit_byteenable_FSM ( .write_in (lower_enable), .byteenable_in (byteenable_in[1:0]), .waitrequest_out (lower_stall), .byteenable_out (byteenable_out[1:0]), .waitrequest_in (waitrequest_in) ); sixteen_bit_byteenable_FSM upper_sixteen_bit_byteenable_FSM ( .write_in (upper_enable), .byteenable_in (byteenable_in[3:2]), .waitrequest_out (upper_stall), .byteenable_out (byteenable_out[3:2]), .waitrequest_in (waitrequest_in) ); assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1)); endmodule
module sixteen_bit_byteenable_FSM ( write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input write_in; input [1:0] byteenable_in; output wire waitrequest_out; output wire [1:0] byteenable_out; input waitrequest_in; assign byteenable_out = byteenable_in & {2{write_in}}; // all 2 bit byte enable pairs are supported, masked with write in to turn the byte lanes off when writing is disabled assign waitrequest_out = (write_in == 1) & (waitrequest_in == 1); // transfer always completes on the first cycle unless waitrequest is asserted endmodule
module uses it .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end else if (BYTEENABLE_WIDTH == 4) begin thirty_two_bit_byteenable_FSM the_thirty_two_bit_byteenable_FSM( .clk (clk), .reset (reset), .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end else if (BYTEENABLE_WIDTH == 8) begin sixty_four_bit_byteenable_FSM the_sixty_four_bit_byteenable_FSM( .clk (clk), .reset (reset), .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end else if (BYTEENABLE_WIDTH == 16) begin one_hundred_twenty_eight_bit_byteenable_FSM the_one_hundred_twenty_eight_bit_byteenable_FSM( .clk (clk), .reset (reset), .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end else if (BYTEENABLE_WIDTH == 32) begin two_hundred_fifty_six_bit_byteenable_FSM the_two_hundred_fifty_six_bit_byteenable_FSM( .clk (clk), .reset (reset), .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end else if (BYTEENABLE_WIDTH == 64) begin five_hundred_twelve_bit_byteenable_FSM the_five_hundred_twelve_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end else if (BYTEENABLE_WIDTH == 128) begin one_thousand_twenty_four_byteenable_FSM the_one_thousand_twenty_four_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (write_in), .byteenable_in (byteenable_in), .waitrequest_out (waitrequest_out), .byteenable_out (byteenable_out), .waitrequest_in (waitrequest_in) ); end endgenerate endmodule
module one_thousand_twenty_four_byteenable_FSM ( clk, reset, write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input clk; input reset; input write_in; input [127:0] byteenable_in; output wire waitrequest_out; output wire [127:0] byteenable_out; input waitrequest_in; // internal statemachine signals wire partial_lower_half_transfer; wire full_lower_half_transfer; wire partial_upper_half_transfer; wire full_upper_half_transfer; wire full_word_transfer; reg state_bit; wire transfer_done; wire advance_to_next_state; wire lower_enable; wire upper_enable; wire lower_stall; wire upper_stall; wire two_stage_transfer; always @ (posedge clk or posedge reset) begin if (reset) begin state_bit <= 0; end else begin if (transfer_done == 1) begin state_bit <= 0; end else if (advance_to_next_state == 1) begin state_bit <= 1; end end end assign partial_lower_half_transfer = (byteenable_in[63:0] != 0); assign full_lower_half_transfer = (byteenable_in[63:0] == 64'hFFFFFFFFFFFFFFFF); assign partial_upper_half_transfer = (byteenable_in[127:64] != 0); assign full_upper_half_transfer = (byteenable_in[127:64] == 64'hFFFFFFFFFFFFFFFF); assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1); assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1); assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer) assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer) five_hundred_twelve_bit_byteenable_FSM lower_five_hundred_twelve_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (lower_enable), .byteenable_in (byteenable_in[63:0]), .waitrequest_out (lower_stall), .byteenable_out (byteenable_out[63:0]), .waitrequest_in (waitrequest_in) ); five_hundred_twelve_bit_byteenable_FSM upper_five_hundred_twelve_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (upper_enable), .byteenable_in (byteenable_in[127:64]), .waitrequest_out (upper_stall), .byteenable_out (byteenable_out[127:64]), .waitrequest_in (waitrequest_in) ); assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1)); endmodule
module five_hundred_twelve_bit_byteenable_FSM ( clk, reset, write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input clk; input reset; input write_in; input [63:0] byteenable_in; output wire waitrequest_out; output wire [63:0] byteenable_out; input waitrequest_in; // internal statemachine signals wire partial_lower_half_transfer; wire full_lower_half_transfer; wire partial_upper_half_transfer; wire full_upper_half_transfer; wire full_word_transfer; reg state_bit; wire transfer_done; wire advance_to_next_state; wire lower_enable; wire upper_enable; wire lower_stall; wire upper_stall; wire two_stage_transfer; always @ (posedge clk or posedge reset) begin if (reset) begin state_bit <= 0; end else begin if (transfer_done == 1) begin state_bit <= 0; end else if (advance_to_next_state == 1) begin state_bit <= 1; end end end assign partial_lower_half_transfer = (byteenable_in[31:0] != 0); assign full_lower_half_transfer = (byteenable_in[31:0] == 32'hFFFFFFFF); assign partial_upper_half_transfer = (byteenable_in[63:32] != 0); assign full_upper_half_transfer = (byteenable_in[63:32] == 32'hFFFFFFFF); assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1); assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1); assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer) assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer) two_hundred_fifty_six_bit_byteenable_FSM lower_two_hundred_fifty_six_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (lower_enable), .byteenable_in (byteenable_in[31:0]), .waitrequest_out (lower_stall), .byteenable_out (byteenable_out[31:0]), .waitrequest_in (waitrequest_in) ); two_hundred_fifty_six_bit_byteenable_FSM upper_two_hundred_fifty_six_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (upper_enable), .byteenable_in (byteenable_in[63:32]), .waitrequest_out (upper_stall), .byteenable_out (byteenable_out[63:32]), .waitrequest_in (waitrequest_in) ); assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1)); endmodule
module two_hundred_fifty_six_bit_byteenable_FSM ( clk, reset, write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input clk; input reset; input write_in; input [31:0] byteenable_in; output wire waitrequest_out; output wire [31:0] byteenable_out; input waitrequest_in; // internal statemachine signals wire partial_lower_half_transfer; wire full_lower_half_transfer; wire partial_upper_half_transfer; wire full_upper_half_transfer; wire full_word_transfer; reg state_bit; wire transfer_done; wire advance_to_next_state; wire lower_enable; wire upper_enable; wire lower_stall; wire upper_stall; wire two_stage_transfer; always @ (posedge clk or posedge reset) begin if (reset) begin state_bit <= 0; end else begin if (transfer_done == 1) begin state_bit <= 0; end else if (advance_to_next_state == 1) begin state_bit <= 1; end end end assign partial_lower_half_transfer = (byteenable_in[15:0] != 0); assign full_lower_half_transfer = (byteenable_in[15:0] == 16'hFFFF); assign partial_upper_half_transfer = (byteenable_in[31:16] != 0); assign full_upper_half_transfer = (byteenable_in[31:16] == 16'hFFFF); assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1); assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1); assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer) assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer) one_hundred_twenty_eight_bit_byteenable_FSM lower_one_hundred_twenty_eight_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (lower_enable), .byteenable_in (byteenable_in[15:0]), .waitrequest_out (lower_stall), .byteenable_out (byteenable_out[15:0]), .waitrequest_in (waitrequest_in) ); one_hundred_twenty_eight_bit_byteenable_FSM upper_one_hundred_twenty_eight_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (upper_enable), .byteenable_in (byteenable_in[31:16]), .waitrequest_out (upper_stall), .byteenable_out (byteenable_out[31:16]), .waitrequest_in (waitrequest_in) ); assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1)); endmodule
module one_hundred_twenty_eight_bit_byteenable_FSM ( clk, reset, write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input clk; input reset; input write_in; input [15:0] byteenable_in; output wire waitrequest_out; output wire [15:0] byteenable_out; input waitrequest_in; // internal statemachine signals wire partial_lower_half_transfer; wire full_lower_half_transfer; wire partial_upper_half_transfer; wire full_upper_half_transfer; wire full_word_transfer; reg state_bit; wire transfer_done; wire advance_to_next_state; wire lower_enable; wire upper_enable; wire lower_stall; wire upper_stall; wire two_stage_transfer; always @ (posedge clk or posedge reset) begin if (reset) begin state_bit <= 0; end else begin if (transfer_done == 1) begin state_bit <= 0; end else if (advance_to_next_state == 1) begin state_bit <= 1; end end end assign partial_lower_half_transfer = (byteenable_in[7:0] != 0); assign full_lower_half_transfer = (byteenable_in[7:0] == 8'hFF); assign partial_upper_half_transfer = (byteenable_in[15:8] != 0); assign full_upper_half_transfer = (byteenable_in[15:8] == 8'hFF); assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1); assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1); assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer) assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer) sixty_four_bit_byteenable_FSM lower_sixty_four_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (lower_enable), .byteenable_in (byteenable_in[7:0]), .waitrequest_out (lower_stall), .byteenable_out (byteenable_out[7:0]), .waitrequest_in (waitrequest_in) ); sixty_four_bit_byteenable_FSM upper_sixty_four_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (upper_enable), .byteenable_in (byteenable_in[15:8]), .waitrequest_out (upper_stall), .byteenable_out (byteenable_out[15:8]), .waitrequest_in (waitrequest_in) ); assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1)); endmodule
module sixty_four_bit_byteenable_FSM ( clk, reset, write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input clk; input reset; input write_in; input [7:0] byteenable_in; output wire waitrequest_out; output wire [7:0] byteenable_out; input waitrequest_in; // internal statemachine signals wire partial_lower_half_transfer; wire full_lower_half_transfer; wire partial_upper_half_transfer; wire full_upper_half_transfer; wire full_word_transfer; reg state_bit; wire transfer_done; wire advance_to_next_state; wire lower_enable; wire upper_enable; wire lower_stall; wire upper_stall; wire two_stage_transfer; always @ (posedge clk or posedge reset) begin if (reset) begin state_bit <= 0; end else begin if (transfer_done == 1) begin state_bit <= 0; end else if (advance_to_next_state == 1) begin state_bit <= 1; end end end assign partial_lower_half_transfer = (byteenable_in[3:0] != 0); assign full_lower_half_transfer = (byteenable_in[3:0] == 4'hF); assign partial_upper_half_transfer = (byteenable_in[7:4] != 0); assign full_upper_half_transfer = (byteenable_in[7:4] == 4'hF); assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1); assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1); assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer) assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer) thirty_two_bit_byteenable_FSM lower_thirty_two_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (lower_enable), .byteenable_in (byteenable_in[3:0]), .waitrequest_out (lower_stall), .byteenable_out (byteenable_out[3:0]), .waitrequest_in (waitrequest_in) ); thirty_two_bit_byteenable_FSM upper_thirty_two_bit_byteenable_FSM ( .clk (clk), .reset (reset), .write_in (upper_enable), .byteenable_in (byteenable_in[7:4]), .waitrequest_out (upper_stall), .byteenable_out (byteenable_out[7:4]), .waitrequest_in (waitrequest_in) ); assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1)); endmodule
module thirty_two_bit_byteenable_FSM ( clk, reset, write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input clk; input reset; input write_in; input [3:0] byteenable_in; output wire waitrequest_out; output wire [3:0] byteenable_out; input waitrequest_in; // internal statemachine signals wire partial_lower_half_transfer; wire full_lower_half_transfer; wire partial_upper_half_transfer; wire full_upper_half_transfer; wire full_word_transfer; reg state_bit; wire transfer_done; wire advance_to_next_state; wire lower_enable; wire upper_enable; wire lower_stall; wire upper_stall; wire two_stage_transfer; always @ (posedge clk or posedge reset) begin if (reset) begin state_bit <= 0; end else begin if (transfer_done == 1) begin state_bit <= 0; end else if (advance_to_next_state == 1) begin state_bit <= 1; end end end assign partial_lower_half_transfer = (byteenable_in[1:0] != 0); assign full_lower_half_transfer = (byteenable_in[1:0] == 2'h3); assign partial_upper_half_transfer = (byteenable_in[3:2] != 0); assign full_upper_half_transfer = (byteenable_in[3:2] == 2'h3); assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1); assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1); assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer) assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer) sixteen_bit_byteenable_FSM lower_sixteen_bit_byteenable_FSM ( .write_in (lower_enable), .byteenable_in (byteenable_in[1:0]), .waitrequest_out (lower_stall), .byteenable_out (byteenable_out[1:0]), .waitrequest_in (waitrequest_in) ); sixteen_bit_byteenable_FSM upper_sixteen_bit_byteenable_FSM ( .write_in (upper_enable), .byteenable_in (byteenable_in[3:2]), .waitrequest_out (upper_stall), .byteenable_out (byteenable_out[3:2]), .waitrequest_in (waitrequest_in) ); assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1)); endmodule
module sixteen_bit_byteenable_FSM ( write_in, byteenable_in, waitrequest_out, byteenable_out, waitrequest_in ); input write_in; input [1:0] byteenable_in; output wire waitrequest_out; output wire [1:0] byteenable_out; input waitrequest_in; assign byteenable_out = byteenable_in & {2{write_in}}; // all 2 bit byte enable pairs are supported, masked with write in to turn the byte lanes off when writing is disabled assign waitrequest_out = (write_in == 1) & (waitrequest_in == 1); // transfer always completes on the first cycle unless waitrequest is asserted endmodule
module generic_baseblocks_v2_1_0_command_fifo # ( parameter C_FAMILY = "virtex6", parameter integer C_ENABLE_S_VALID_CARRY = 0, parameter integer C_ENABLE_REGISTERED_OUTPUT = 0, parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG // Range = [4:5]. parameter integer C_FIFO_WIDTH = 64 // Width of payload [1:512] ) ( // Global inputs input wire ACLK, // Clock input wire ARESET, // Reset // Information output wire EMPTY, // FIFO empty (all stages) // Slave Port input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals) input wire S_VALID, // FIFO push output wire S_READY, // FIFO not full // Master Port output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload output wire M_VALID, // FIFO not empty input wire M_READY // FIFO pop ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for data vector. genvar addr_cnt; genvar bit_cnt; integer index; ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIFO_DEPTH_LOG-1:0] addr; wire buffer_Full; wire buffer_Empty; wire next_Data_Exists; reg data_Exists_I; wire valid_Write; wire new_write; wire [C_FIFO_DEPTH_LOG-1:0] hsum_A; wire [C_FIFO_DEPTH_LOG-1:0] sum_A; wire [C_FIFO_DEPTH_LOG-1:0] addr_cy; wire buffer_full_early; wire [C_FIFO_WIDTH-1:0] M_MESG_I; // Payload wire M_VALID_I; // FIFO not empty wire M_READY_I; // FIFO pop ///////////////////////////////////////////////////////////////////////////// // Create Flags ///////////////////////////////////////////////////////////////////////////// assign buffer_full_early = ( (addr == {{C_FIFO_DEPTH_LOG-1{1'b1}}, 1'b0}) & valid_Write & ~M_READY_I ) | ( buffer_Full & ~M_READY_I ); assign S_READY = ~buffer_Full; assign buffer_Empty = (addr == {C_FIFO_DEPTH_LOG{1'b0}}); assign next_Data_Exists = (data_Exists_I & ~buffer_Empty) | (buffer_Empty & S_VALID) | (data_Exists_I & ~(M_READY_I & data_Exists_I)); always @ (posedge ACLK) begin if (ARESET) begin data_Exists_I <= 1'b0; end else begin data_Exists_I <= next_Data_Exists; end end assign M_VALID_I = data_Exists_I; // Select RTL or FPGA optimized instatiations for critical parts. generate if ( C_FAMILY == "rtl" || C_ENABLE_S_VALID_CARRY == 0 ) begin : USE_RTL_VALID_WRITE reg buffer_Full_q; assign valid_Write = S_VALID & ~buffer_Full; assign new_write = (S_VALID | ~buffer_Empty); assign addr_cy[0] = valid_Write; always @ (posedge ACLK) begin if (ARESET) begin buffer_Full_q <= 1'b0; end else if ( data_Exists_I ) begin buffer_Full_q <= buffer_full_early; end end assign buffer_Full = buffer_Full_q; end else begin : USE_FPGA_VALID_WRITE wire s_valid_dummy1; wire s_valid_dummy2; wire sel_s_valid; wire sel_new_write; wire valid_Write_dummy1; wire valid_Write_dummy2; assign sel_s_valid = ~buffer_Full; generic_baseblocks_v2_1_0_carry_and # ( .C_FAMILY(C_FAMILY) ) s_valid_dummy_inst1 ( .CIN(S_VALID), .S(1'b1), .COUT(s_valid_dummy1) ); generic_baseblocks_v2_1_0_carry_and # ( .C_FAMILY(C_FAMILY) ) s_valid_dummy_inst2 ( .CIN(s_valid_dummy1), .S(1'b1), .COUT(s_valid_dummy2) ); generic_baseblocks_v2_1_0_carry_and # ( .C_FAMILY(C_FAMILY) ) valid_write_inst ( .CIN(s_valid_dummy2), .S(sel_s_valid), .COUT(valid_Write) ); assign sel_new_write = ~buffer_Empty; generic_baseblocks_v2_1_0_carry_latch_or # ( .C_FAMILY(C_FAMILY) ) new_write_inst ( .CIN(valid_Write), .I(sel_new_write), .O(new_write) ); generic_baseblocks_v2_1_0_carry_and # ( .C_FAMILY(C_FAMILY) ) valid_write_dummy_inst1 ( .CIN(valid_Write), .S(1'b1), .COUT(valid_Write_dummy1) ); generic_baseblocks_v2_1_0_carry_and # ( .C_FAMILY(C_FAMILY) ) valid_write_dummy_inst2 ( .CIN(valid_Write_dummy1), .S(1'b1), .COUT(valid_Write_dummy2) ); generic_baseblocks_v2_1_0_carry_and # ( .C_FAMILY(C_FAMILY) ) valid_write_dummy_inst3 ( .CIN(valid_Write_dummy2), .S(1'b1), .COUT(addr_cy[0]) ); FDRE #( .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) ) FDRE_I1 ( .Q(buffer_Full), // Data output .C(ACLK), // Clock input .CE(data_Exists_I), // Clock enable input .R(ARESET), // Synchronous reset input .D(buffer_full_early) // Data input ); end endgenerate ///////////////////////////////////////////////////////////////////////////// // Create address pointer ///////////////////////////////////////////////////////////////////////////// generate if ( C_FAMILY == "rtl" ) begin : USE_RTL_ADDR reg [C_FIFO_DEPTH_LOG-1:0] addr_q; always @ (posedge ACLK) begin if (ARESET) begin addr_q <= {C_FIFO_DEPTH_LOG{1'b0}}; end else if ( data_Exists_I ) begin if ( valid_Write & ~(M_READY_I & data_Exists_I) ) begin addr_q <= addr_q + 1'b1; end else if ( ~valid_Write & (M_READY_I & data_Exists_I) & ~buffer_Empty ) begin addr_q <= addr_q - 1'b1; end else begin addr_q <= addr_q; end end else begin addr_q <= addr_q; end end assign addr = addr_q; end else begin : USE_FPGA_ADDR for (addr_cnt = 0; addr_cnt < C_FIFO_DEPTH_LOG ; addr_cnt = addr_cnt + 1) begin : ADDR_GEN assign hsum_A[addr_cnt] = ((M_READY_I & data_Exists_I) ^ addr[addr_cnt]) & new_write; // Don't need the last muxcy, addr_cy(last) is not used anywhere if ( addr_cnt < C_FIFO_DEPTH_LOG - 1 ) begin : USE_MUXCY MUXCY MUXCY_inst ( .DI(addr[addr_cnt]), .CI(addr_cy[addr_cnt]), .S(hsum_A[addr_cnt]), .O(addr_cy[addr_cnt+1]) ); end else begin : NO_MUXCY end XORCY XORCY_inst ( .LI(hsum_A[addr_cnt]), .CI(addr_cy[addr_cnt]), .O(sum_A[addr_cnt]) ); FDRE #( .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) ) FDRE_inst ( .Q(addr[addr_cnt]), // Data output .C(ACLK), // Clock input .CE(data_Exists_I), // Clock enable input .R(ARESET), // Synchronous reset input .D(sum_A[addr_cnt]) // Data input ); end // end for bit_cnt end // C_FAMILY endgenerate ///////////////////////////////////////////////////////////////////////////// // Data storage ///////////////////////////////////////////////////////////////////////////// generate if ( C_FAMILY == "rtl" ) begin : USE_RTL_FIFO reg [C_FIFO_WIDTH-1:0] data_srl[2 ** C_FIFO_DEPTH_LOG-1:0]; always @ (posedge ACLK) begin if ( valid_Write ) begin for (index = 0; index < 2 ** C_FIFO_DEPTH_LOG-1 ; index = index + 1) begin data_srl[index+1] <= data_srl[index]; end data_srl[0] <= S_MESG; end end assign M_MESG_I = data_srl[addr]; end else begin : USE_FPGA_FIFO for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN if ( C_FIFO_DEPTH_LOG == 5 ) begin : USE_32 SRLC32E # ( .INIT(32'h00000000) // Initial Value of Shift Register ) SRLC32E_inst ( .Q(M_MESG_I[bit_cnt]), // SRL data output .Q31(), // SRL cascade output pin .A(addr), // 5-bit shift depth select input .CE(valid_Write), // Clock enable input .CLK(ACLK), // Clock input .D(S_MESG[bit_cnt]) // SRL data input ); end else begin : USE_16 SRLC16E # ( .INIT(32'h00000000) // Initial Value of Shift Register ) SRLC16E_inst ( .Q(M_MESG_I[bit_cnt]), // SRL data output .Q15(), // SRL cascade output pin .A0(addr[0]), // 4-bit shift depth select input 0 .A1(addr[1]), // 4-bit shift depth select input 1 .A2(addr[2]), // 4-bit shift depth select input 2 .A3(addr[3]), // 4-bit shift depth select input 3 .CE(valid_Write), // Clock enable input .CLK(ACLK), // Clock input .D(S_MESG[bit_cnt]) // SRL data input ); end // C_FIFO_DEPTH_LOG end // end for bit_cnt end // C_FAMILY endgenerate ///////////////////////////////////////////////////////////////////////////// // Pipeline stage ///////////////////////////////////////////////////////////////////////////// generate if ( C_ENABLE_REGISTERED_OUTPUT != 0 ) begin : USE_FF_OUT wire [C_FIFO_WIDTH-1:0] M_MESG_FF; // Payload wire M_VALID_FF; // FIFO not empty // Select RTL or FPGA optimized instatiations for critical parts. if ( C_FAMILY == "rtl" ) begin : USE_RTL_OUTPUT_PIPELINE reg [C_FIFO_WIDTH-1:0] M_MESG_Q; // Payload reg M_VALID_Q; // FIFO not empty always @ (posedge ACLK) begin if (ARESET) begin M_MESG_Q <= {C_FIFO_WIDTH{1'b0}}; M_VALID_Q <= 1'b0; end else begin if ( M_READY_I ) begin M_MESG_Q <= M_MESG_I; M_VALID_Q <= M_VALID_I; end end end assign M_MESG_FF = M_MESG_Q; assign M_VALID_FF = M_VALID_Q; end else begin : USE_FPGA_OUTPUT_PIPELINE reg [C_FIFO_WIDTH-1:0] M_MESG_CMB; // Payload reg M_VALID_CMB; // FIFO not empty always @ * begin if ( M_READY_I ) begin M_MESG_CMB <= M_MESG_I; M_VALID_CMB <= M_VALID_I; end else begin M_MESG_CMB <= M_MESG_FF; M_VALID_CMB <= M_VALID_FF; end end for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN FDRE #( .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) ) FDRE_inst ( .Q(M_MESG_FF[bit_cnt]), // Data output .C(ACLK), // Clock input .CE(1'b1), // Clock enable input .R(ARESET), // Synchronous reset input .D(M_MESG_CMB[bit_cnt]) // Data input ); end // end for bit_cnt FDRE #( .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) ) FDRE_inst ( .Q(M_VALID_FF), // Data output .C(ACLK), // Clock input .CE(1'b1), // Clock enable input .R(ARESET), // Synchronous reset input .D(M_VALID_CMB) // Data input ); end assign EMPTY = ~M_VALID_I & ~M_VALID_FF; assign M_MESG = M_MESG_FF; assign M_VALID = M_VALID_FF; assign M_READY_I = ( M_READY & M_VALID_FF ) | ~M_VALID_FF; end else begin : NO_FF_OUT assign EMPTY = ~M_VALID_I; assign M_MESG = M_MESG_I; assign M_VALID = M_VALID_I; assign M_READY_I = M_READY; end endgenerate endmodule
module uniphy_status #( parameter WIDTH=32, parameter NUM_UNIPHYS=2 ) ( input clk, input resetn, // Slave port input slave_read, output [WIDTH-1:0] slave_readdata, // hw.tcl won't let me index into a bit vector :( input mem0_local_cal_success, input mem0_local_cal_fail, input mem0_local_init_done, input mem1_local_cal_success, input mem1_local_cal_fail, input mem1_local_init_done, input mem2_local_cal_success, input mem2_local_cal_fail, input mem2_local_init_done, input mem3_local_cal_success, input mem3_local_cal_fail, input mem3_local_init_done, input mem4_local_cal_success, input mem4_local_cal_fail, input mem4_local_init_done, input mem5_local_cal_success, input mem5_local_cal_fail, input mem5_local_init_done, input mem6_local_cal_success, input mem6_local_cal_fail, input mem6_local_init_done, input mem7_local_cal_success, input mem7_local_cal_fail, input mem7_local_init_done, output export_local_cal_success, output export_local_cal_fail, output export_local_init_done ); reg [WIDTH-1:0] aggregate_uniphy_status; wire local_cal_success; wire local_cal_fail; wire local_init_done; wire [NUM_UNIPHYS-1:0] not_init_done; wire [7:0] mask; assign mask = (NUM_UNIPHYS < 1) ? 0 : ~(8'hff << NUM_UNIPHYS); assign local_cal_success = &( ~mask | {mem7_local_cal_success, mem6_local_cal_success, mem5_local_cal_success, mem4_local_cal_success, mem3_local_cal_success, mem2_local_cal_success, mem1_local_cal_success, mem0_local_cal_success}); assign local_cal_fail = mem0_local_cal_fail | mem1_local_cal_fail | mem2_local_cal_fail | mem3_local_cal_fail | mem4_local_cal_fail | mem5_local_cal_fail | mem6_local_cal_fail | mem7_local_cal_fail; assign local_init_done = &( ~mask |{mem7_local_init_done, mem6_local_init_done, mem5_local_init_done, mem4_local_init_done, mem3_local_init_done, mem2_local_init_done, mem1_local_init_done, mem0_local_init_done}); assign not_init_done = mask & ~{ mem7_local_init_done, mem6_local_init_done, mem5_local_init_done, mem4_local_init_done, mem3_local_init_done, mem2_local_init_done, mem1_local_init_done, mem0_local_init_done}; // Desire status==0 to imply success - may cause false positives, but the // alternative is headaches for non-uniphy memories. // Status MSB-LSB: not_init_done, 0, !calsuccess, calfail, !initdone always@(posedge clk or negedge resetn) if (!resetn) aggregate_uniphy_status <= {WIDTH{1'b0}}; else aggregate_uniphy_status <= { not_init_done, 1'b0, {~local_cal_success,local_cal_fail,~local_init_done} }; assign slave_readdata = aggregate_uniphy_status; assign export_local_cal_success = local_cal_success; assign export_local_cal_fail = local_cal_fail; assign export_local_init_done = local_init_done; endmodule
module uniphy_status #( parameter WIDTH=32, parameter NUM_UNIPHYS=2 ) ( input clk, input resetn, // Slave port input slave_read, output [WIDTH-1:0] slave_readdata, // hw.tcl won't let me index into a bit vector :( input mem0_local_cal_success, input mem0_local_cal_fail, input mem0_local_init_done, input mem1_local_cal_success, input mem1_local_cal_fail, input mem1_local_init_done, input mem2_local_cal_success, input mem2_local_cal_fail, input mem2_local_init_done, input mem3_local_cal_success, input mem3_local_cal_fail, input mem3_local_init_done, input mem4_local_cal_success, input mem4_local_cal_fail, input mem4_local_init_done, input mem5_local_cal_success, input mem5_local_cal_fail, input mem5_local_init_done, input mem6_local_cal_success, input mem6_local_cal_fail, input mem6_local_init_done, input mem7_local_cal_success, input mem7_local_cal_fail, input mem7_local_init_done, output export_local_cal_success, output export_local_cal_fail, output export_local_init_done ); reg [WIDTH-1:0] aggregate_uniphy_status; wire local_cal_success; wire local_cal_fail; wire local_init_done; wire [NUM_UNIPHYS-1:0] not_init_done; wire [7:0] mask; assign mask = (NUM_UNIPHYS < 1) ? 0 : ~(8'hff << NUM_UNIPHYS); assign local_cal_success = &( ~mask | {mem7_local_cal_success, mem6_local_cal_success, mem5_local_cal_success, mem4_local_cal_success, mem3_local_cal_success, mem2_local_cal_success, mem1_local_cal_success, mem0_local_cal_success}); assign local_cal_fail = mem0_local_cal_fail | mem1_local_cal_fail | mem2_local_cal_fail | mem3_local_cal_fail | mem4_local_cal_fail | mem5_local_cal_fail | mem6_local_cal_fail | mem7_local_cal_fail; assign local_init_done = &( ~mask |{mem7_local_init_done, mem6_local_init_done, mem5_local_init_done, mem4_local_init_done, mem3_local_init_done, mem2_local_init_done, mem1_local_init_done, mem0_local_init_done}); assign not_init_done = mask & ~{ mem7_local_init_done, mem6_local_init_done, mem5_local_init_done, mem4_local_init_done, mem3_local_init_done, mem2_local_init_done, mem1_local_init_done, mem0_local_init_done}; // Desire status==0 to imply success - may cause false positives, but the // alternative is headaches for non-uniphy memories. // Status MSB-LSB: not_init_done, 0, !calsuccess, calfail, !initdone always@(posedge clk or negedge resetn) if (!resetn) aggregate_uniphy_status <= {WIDTH{1'b0}}; else aggregate_uniphy_status <= { not_init_done, 1'b0, {~local_cal_success,local_cal_fail,~local_init_done} }; assign slave_readdata = aggregate_uniphy_status; assign export_local_cal_success = local_cal_success; assign export_local_cal_fail = local_cal_fail; assign export_local_init_done = local_init_done; endmodule
module uniphy_status #( parameter WIDTH=32, parameter NUM_UNIPHYS=2 ) ( input clk, input resetn, // Slave port input slave_read, output [WIDTH-1:0] slave_readdata, // hw.tcl won't let me index into a bit vector :( input mem0_local_cal_success, input mem0_local_cal_fail, input mem0_local_init_done, input mem1_local_cal_success, input mem1_local_cal_fail, input mem1_local_init_done, input mem2_local_cal_success, input mem2_local_cal_fail, input mem2_local_init_done, input mem3_local_cal_success, input mem3_local_cal_fail, input mem3_local_init_done, input mem4_local_cal_success, input mem4_local_cal_fail, input mem4_local_init_done, input mem5_local_cal_success, input mem5_local_cal_fail, input mem5_local_init_done, input mem6_local_cal_success, input mem6_local_cal_fail, input mem6_local_init_done, input mem7_local_cal_success, input mem7_local_cal_fail, input mem7_local_init_done, output export_local_cal_success, output export_local_cal_fail, output export_local_init_done ); reg [WIDTH-1:0] aggregate_uniphy_status; wire local_cal_success; wire local_cal_fail; wire local_init_done; wire [NUM_UNIPHYS-1:0] not_init_done; wire [7:0] mask; assign mask = (NUM_UNIPHYS < 1) ? 0 : ~(8'hff << NUM_UNIPHYS); assign local_cal_success = &( ~mask | {mem7_local_cal_success, mem6_local_cal_success, mem5_local_cal_success, mem4_local_cal_success, mem3_local_cal_success, mem2_local_cal_success, mem1_local_cal_success, mem0_local_cal_success}); assign local_cal_fail = mem0_local_cal_fail | mem1_local_cal_fail | mem2_local_cal_fail | mem3_local_cal_fail | mem4_local_cal_fail | mem5_local_cal_fail | mem6_local_cal_fail | mem7_local_cal_fail; assign local_init_done = &( ~mask |{mem7_local_init_done, mem6_local_init_done, mem5_local_init_done, mem4_local_init_done, mem3_local_init_done, mem2_local_init_done, mem1_local_init_done, mem0_local_init_done}); assign not_init_done = mask & ~{ mem7_local_init_done, mem6_local_init_done, mem5_local_init_done, mem4_local_init_done, mem3_local_init_done, mem2_local_init_done, mem1_local_init_done, mem0_local_init_done}; // Desire status==0 to imply success - may cause false positives, but the // alternative is headaches for non-uniphy memories. // Status MSB-LSB: not_init_done, 0, !calsuccess, calfail, !initdone always@(posedge clk or negedge resetn) if (!resetn) aggregate_uniphy_status <= {WIDTH{1'b0}}; else aggregate_uniphy_status <= { not_init_done, 1'b0, {~local_cal_success,local_cal_fail,~local_init_done} }; assign slave_readdata = aggregate_uniphy_status; assign export_local_cal_success = local_cal_success; assign export_local_cal_fail = local_cal_fail; assign export_local_init_done = local_init_done; endmodule
module uniphy_status #( parameter WIDTH=32, parameter NUM_UNIPHYS=2 ) ( input clk, input resetn, // Slave port input slave_read, output [WIDTH-1:0] slave_readdata, // hw.tcl won't let me index into a bit vector :( input mem0_local_cal_success, input mem0_local_cal_fail, input mem0_local_init_done, input mem1_local_cal_success, input mem1_local_cal_fail, input mem1_local_init_done, input mem2_local_cal_success, input mem2_local_cal_fail, input mem2_local_init_done, input mem3_local_cal_success, input mem3_local_cal_fail, input mem3_local_init_done, input mem4_local_cal_success, input mem4_local_cal_fail, input mem4_local_init_done, input mem5_local_cal_success, input mem5_local_cal_fail, input mem5_local_init_done, input mem6_local_cal_success, input mem6_local_cal_fail, input mem6_local_init_done, input mem7_local_cal_success, input mem7_local_cal_fail, input mem7_local_init_done, output export_local_cal_success, output export_local_cal_fail, output export_local_init_done ); reg [WIDTH-1:0] aggregate_uniphy_status; wire local_cal_success; wire local_cal_fail; wire local_init_done; wire [NUM_UNIPHYS-1:0] not_init_done; wire [7:0] mask; assign mask = (NUM_UNIPHYS < 1) ? 0 : ~(8'hff << NUM_UNIPHYS); assign local_cal_success = &( ~mask | {mem7_local_cal_success, mem6_local_cal_success, mem5_local_cal_success, mem4_local_cal_success, mem3_local_cal_success, mem2_local_cal_success, mem1_local_cal_success, mem0_local_cal_success}); assign local_cal_fail = mem0_local_cal_fail | mem1_local_cal_fail | mem2_local_cal_fail | mem3_local_cal_fail | mem4_local_cal_fail | mem5_local_cal_fail | mem6_local_cal_fail | mem7_local_cal_fail; assign local_init_done = &( ~mask |{mem7_local_init_done, mem6_local_init_done, mem5_local_init_done, mem4_local_init_done, mem3_local_init_done, mem2_local_init_done, mem1_local_init_done, mem0_local_init_done}); assign not_init_done = mask & ~{ mem7_local_init_done, mem6_local_init_done, mem5_local_init_done, mem4_local_init_done, mem3_local_init_done, mem2_local_init_done, mem1_local_init_done, mem0_local_init_done}; // Desire status==0 to imply success - may cause false positives, but the // alternative is headaches for non-uniphy memories. // Status MSB-LSB: not_init_done, 0, !calsuccess, calfail, !initdone always@(posedge clk or negedge resetn) if (!resetn) aggregate_uniphy_status <= {WIDTH{1'b0}}; else aggregate_uniphy_status <= { not_init_done, 1'b0, {~local_cal_success,local_cal_fail,~local_init_done} }; assign slave_readdata = aggregate_uniphy_status; assign export_local_cal_success = local_cal_success; assign export_local_cal_fail = local_cal_fail; assign export_local_init_done = local_init_done; endmodule
module axi_infrastructure_v1_1_0_vector2axi # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// parameter integer C_AXI_PROTOCOL = 0, parameter integer C_AXI_ID_WIDTH = 4, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0, parameter integer C_AXI_AWUSER_WIDTH = 1, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_AXI_BUSER_WIDTH = 1, parameter integer C_AXI_ARUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AWPAYLOAD_WIDTH = 61, parameter integer C_WPAYLOAD_WIDTH = 73, parameter integer C_BPAYLOAD_WIDTH = 6, parameter integer C_ARPAYLOAD_WIDTH = 61, parameter integer C_RPAYLOAD_WIDTH = 69 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // Slave Interface Write Address Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid, output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, output wire [3-1:0] m_axi_awsize, output wire [2-1:0] m_axi_awburst, output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, output wire [4-1:0] m_axi_awcache, output wire [3-1:0] m_axi_awprot, output wire [4-1:0] m_axi_awregion, output wire [4-1:0] m_axi_awqos, output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, // Slave Interface Write Data Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid, output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata, output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, output wire m_axi_wlast, output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, // Slave Interface Write Response Ports input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid, input wire [2-1:0] m_axi_bresp, input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser, // Slave Interface Read Address Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid, output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, output wire [3-1:0] m_axi_arsize, output wire [2-1:0] m_axi_arburst, output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, output wire [4-1:0] m_axi_arcache, output wire [3-1:0] m_axi_arprot, output wire [4-1:0] m_axi_arregion, output wire [4-1:0] m_axi_arqos, output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, // Slave Interface Read Data Ports input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid, input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata, input wire [2-1:0] m_axi_rresp, input wire m_axi_rlast, input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, // payloads input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload, input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload, output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload, input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload, output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload ); //////////////////////////////////////////////////////////////////////////////// // Functions //////////////////////////////////////////////////////////////////////////////// `include "axi_infrastructure_v1_1_0_header.vh" //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// // AXI4, AXI4LITE, AXI3 packing assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH]; assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH]; assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH]; assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH]; assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp; assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH]; assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH]; assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata; assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp; generate if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ; assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH]; assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH]; assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ; assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ; assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ; assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ; assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ; if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ; end else begin : gen_no_axi3_wid_packing assign m_axi_wid = 1'b0; end assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid; assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ; assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH]; assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH]; assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ; assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ; assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ; assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ; assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast; assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ; if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH]; assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH]; end else begin : gen_no_region_signals assign m_axi_awregion = 'b0; assign m_axi_arregion = 'b0; end if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH]; assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ; assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ; assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH]; assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ; end else begin : gen_no_user_signals assign m_axi_awuser = 'b0; assign m_axi_wuser = 'b0; assign m_axi_aruser = 'b0; end end else begin : gen_axi4lite_packing assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3; assign m_axi_awburst = 'b0; assign m_axi_awcache = 'b0; assign m_axi_awlen = 'b0; assign m_axi_awlock = 'b0; assign m_axi_awid = 'b0; assign m_axi_awqos = 'b0; assign m_axi_wlast = 1'b1; assign m_axi_wid = 'b0; assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3; assign m_axi_arburst = 'b0; assign m_axi_arcache = 'b0; assign m_axi_arlen = 'b0; assign m_axi_arlock = 'b0; assign m_axi_arid = 'b0; assign m_axi_arqos = 'b0; assign m_axi_awregion = 'b0; assign m_axi_arregion = 'b0; assign m_axi_awuser = 'b0; assign m_axi_wuser = 'b0; assign m_axi_aruser = 'b0; end endgenerate endmodule
module axi_infrastructure_v1_1_0_vector2axi # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// parameter integer C_AXI_PROTOCOL = 0, parameter integer C_AXI_ID_WIDTH = 4, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0, parameter integer C_AXI_AWUSER_WIDTH = 1, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_AXI_BUSER_WIDTH = 1, parameter integer C_AXI_ARUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AWPAYLOAD_WIDTH = 61, parameter integer C_WPAYLOAD_WIDTH = 73, parameter integer C_BPAYLOAD_WIDTH = 6, parameter integer C_ARPAYLOAD_WIDTH = 61, parameter integer C_RPAYLOAD_WIDTH = 69 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // Slave Interface Write Address Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid, output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, output wire [3-1:0] m_axi_awsize, output wire [2-1:0] m_axi_awburst, output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, output wire [4-1:0] m_axi_awcache, output wire [3-1:0] m_axi_awprot, output wire [4-1:0] m_axi_awregion, output wire [4-1:0] m_axi_awqos, output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, // Slave Interface Write Data Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid, output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata, output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, output wire m_axi_wlast, output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, // Slave Interface Write Response Ports input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid, input wire [2-1:0] m_axi_bresp, input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser, // Slave Interface Read Address Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid, output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, output wire [3-1:0] m_axi_arsize, output wire [2-1:0] m_axi_arburst, output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, output wire [4-1:0] m_axi_arcache, output wire [3-1:0] m_axi_arprot, output wire [4-1:0] m_axi_arregion, output wire [4-1:0] m_axi_arqos, output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, // Slave Interface Read Data Ports input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid, input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata, input wire [2-1:0] m_axi_rresp, input wire m_axi_rlast, input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, // payloads input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload, input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload, output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload, input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload, output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload ); //////////////////////////////////////////////////////////////////////////////// // Functions //////////////////////////////////////////////////////////////////////////////// `include "axi_infrastructure_v1_1_0_header.vh" //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// // AXI4, AXI4LITE, AXI3 packing assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH]; assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH]; assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH]; assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH]; assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp; assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH]; assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH]; assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata; assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp; generate if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ; assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH]; assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH]; assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ; assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ; assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ; assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ; assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ; if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ; end else begin : gen_no_axi3_wid_packing assign m_axi_wid = 1'b0; end assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid; assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ; assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH]; assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH]; assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ; assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ; assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ; assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ; assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast; assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ; if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH]; assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH]; end else begin : gen_no_region_signals assign m_axi_awregion = 'b0; assign m_axi_arregion = 'b0; end if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH]; assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ; assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ; assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH]; assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ; end else begin : gen_no_user_signals assign m_axi_awuser = 'b0; assign m_axi_wuser = 'b0; assign m_axi_aruser = 'b0; end end else begin : gen_axi4lite_packing assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3; assign m_axi_awburst = 'b0; assign m_axi_awcache = 'b0; assign m_axi_awlen = 'b0; assign m_axi_awlock = 'b0; assign m_axi_awid = 'b0; assign m_axi_awqos = 'b0; assign m_axi_wlast = 1'b1; assign m_axi_wid = 'b0; assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3; assign m_axi_arburst = 'b0; assign m_axi_arcache = 'b0; assign m_axi_arlen = 'b0; assign m_axi_arlock = 'b0; assign m_axi_arid = 'b0; assign m_axi_arqos = 'b0; assign m_axi_awregion = 'b0; assign m_axi_arregion = 'b0; assign m_axi_awuser = 'b0; assign m_axi_wuser = 'b0; assign m_axi_aruser = 'b0; end endgenerate endmodule
module axi_infrastructure_v1_1_0_vector2axi # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// parameter integer C_AXI_PROTOCOL = 0, parameter integer C_AXI_ID_WIDTH = 4, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0, parameter integer C_AXI_AWUSER_WIDTH = 1, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_AXI_BUSER_WIDTH = 1, parameter integer C_AXI_ARUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AWPAYLOAD_WIDTH = 61, parameter integer C_WPAYLOAD_WIDTH = 73, parameter integer C_BPAYLOAD_WIDTH = 6, parameter integer C_ARPAYLOAD_WIDTH = 61, parameter integer C_RPAYLOAD_WIDTH = 69 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // Slave Interface Write Address Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid, output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, output wire [3-1:0] m_axi_awsize, output wire [2-1:0] m_axi_awburst, output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, output wire [4-1:0] m_axi_awcache, output wire [3-1:0] m_axi_awprot, output wire [4-1:0] m_axi_awregion, output wire [4-1:0] m_axi_awqos, output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, // Slave Interface Write Data Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid, output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata, output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, output wire m_axi_wlast, output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, // Slave Interface Write Response Ports input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid, input wire [2-1:0] m_axi_bresp, input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser, // Slave Interface Read Address Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid, output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, output wire [3-1:0] m_axi_arsize, output wire [2-1:0] m_axi_arburst, output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, output wire [4-1:0] m_axi_arcache, output wire [3-1:0] m_axi_arprot, output wire [4-1:0] m_axi_arregion, output wire [4-1:0] m_axi_arqos, output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, // Slave Interface Read Data Ports input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid, input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata, input wire [2-1:0] m_axi_rresp, input wire m_axi_rlast, input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, // payloads input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload, input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload, output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload, input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload, output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload ); //////////////////////////////////////////////////////////////////////////////// // Functions //////////////////////////////////////////////////////////////////////////////// `include "axi_infrastructure_v1_1_0_header.vh" //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// // AXI4, AXI4LITE, AXI3 packing assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH]; assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH]; assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH]; assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH]; assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp; assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH]; assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH]; assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata; assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp; generate if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ; assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH]; assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH]; assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ; assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ; assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ; assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ; assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ; if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ; end else begin : gen_no_axi3_wid_packing assign m_axi_wid = 1'b0; end assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid; assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ; assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH]; assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH]; assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ; assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ; assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ; assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ; assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast; assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ; if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH]; assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH]; end else begin : gen_no_region_signals assign m_axi_awregion = 'b0; assign m_axi_arregion = 'b0; end if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH]; assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ; assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ; assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH]; assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ; end else begin : gen_no_user_signals assign m_axi_awuser = 'b0; assign m_axi_wuser = 'b0; assign m_axi_aruser = 'b0; end end else begin : gen_axi4lite_packing assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3; assign m_axi_awburst = 'b0; assign m_axi_awcache = 'b0; assign m_axi_awlen = 'b0; assign m_axi_awlock = 'b0; assign m_axi_awid = 'b0; assign m_axi_awqos = 'b0; assign m_axi_wlast = 1'b1; assign m_axi_wid = 'b0; assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3; assign m_axi_arburst = 'b0; assign m_axi_arcache = 'b0; assign m_axi_arlen = 'b0; assign m_axi_arlock = 'b0; assign m_axi_arid = 'b0; assign m_axi_arqos = 'b0; assign m_axi_awregion = 'b0; assign m_axi_arregion = 'b0; assign m_axi_awuser = 'b0; assign m_axi_wuser = 'b0; assign m_axi_aruser = 'b0; end endgenerate endmodule
module axi_infrastructure_v1_1_0_axi2vector # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// parameter integer C_AXI_PROTOCOL = 0, parameter integer C_AXI_ID_WIDTH = 4, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0, parameter integer C_AXI_AWUSER_WIDTH = 1, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_AXI_BUSER_WIDTH = 1, parameter integer C_AXI_ARUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AWPAYLOAD_WIDTH = 61, parameter integer C_WPAYLOAD_WIDTH = 73, parameter integer C_BPAYLOAD_WIDTH = 6, parameter integer C_ARPAYLOAD_WIDTH = 61, parameter integer C_RPAYLOAD_WIDTH = 69 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // Slave Interface Write Address Ports input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid, input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen, input wire [3-1:0] s_axi_awsize, input wire [2-1:0] s_axi_awburst, input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock, input wire [4-1:0] s_axi_awcache, input wire [3-1:0] s_axi_awprot, input wire [4-1:0] s_axi_awregion, input wire [4-1:0] s_axi_awqos, input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, // Slave Interface Write Data Ports input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid, input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata, input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, input wire s_axi_wlast, input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, // Slave Interface Write Response Ports output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid, output wire [2-1:0] s_axi_bresp, output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser, // Slave Interface Read Address Ports input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid, input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen, input wire [3-1:0] s_axi_arsize, input wire [2-1:0] s_axi_arburst, input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock, input wire [4-1:0] s_axi_arcache, input wire [3-1:0] s_axi_arprot, input wire [4-1:0] s_axi_arregion, input wire [4-1:0] s_axi_arqos, input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, // Slave Interface Read Data Ports output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid, output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata, output wire [2-1:0] s_axi_rresp, output wire s_axi_rlast, output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, // payloads output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload, output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload, input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload, output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload, input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload ); //////////////////////////////////////////////////////////////////////////////// // Functions //////////////////////////////////////////////////////////////////////////////// `include "axi_infrastructure_v1_1_0_header.vh" //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// // AXI4, AXI4LITE, AXI3 packing assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr; assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot; assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata; assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb; assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH]; assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr; assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot; assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH]; assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH]; generate if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize; assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst; assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache; assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen; assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock; assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid; assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos; assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast; if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid; end else begin : gen_no_axi3_wid_packing end assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH]; assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize; assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst; assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache; assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen; assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock; assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid; assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos; assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH]; assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH]; if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion; assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion; end else begin : gen_no_region_signals end if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser; assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser; assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH]; assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser; assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH]; end else begin : gen_no_user_signals assign s_axi_buser = 'b0; assign s_axi_ruser = 'b0; end end else begin : gen_axi4lite_packing assign s_axi_bid = 'b0; assign s_axi_buser = 'b0; assign s_axi_rlast = 1'b1; assign s_axi_rid = 'b0; assign s_axi_ruser = 'b0; end endgenerate endmodule
module generic_baseblocks_v2_1_0_comparator_sel_static # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter C_VALUE = 4'b0, // Static value to compare against. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire S, input wire [C_DATA_WIDTH-1:0] A, input wire [C_DATA_WIDTH-1:0] B, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar bit_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 2; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_FIX_DATA_WIDTH-1:0] v_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = B; assign v_local = C_VALUE; end // Instantiate one generic_baseblocks_v2_1_0_carry and per level. for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) | ( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) ); // Instantiate each LUT level. generic_baseblocks_v2_1_0_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[bit_cnt+1]), .CIN (carry_local[bit_cnt]), .S (sel[bit_cnt]) ); end // end for bit_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule
module generic_baseblocks_v2_1_0_comparator_sel_static # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter C_VALUE = 4'b0, // Static value to compare against. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire S, input wire [C_DATA_WIDTH-1:0] A, input wire [C_DATA_WIDTH-1:0] B, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar bit_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 2; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_FIX_DATA_WIDTH-1:0] v_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = B; assign v_local = C_VALUE; end // Instantiate one generic_baseblocks_v2_1_0_carry and per level. for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) | ( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) ); // Instantiate each LUT level. generic_baseblocks_v2_1_0_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[bit_cnt+1]), .CIN (carry_local[bit_cnt]), .S (sel[bit_cnt]) ); end // end for bit_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule
module generic_baseblocks_v2_1_0_comparator_sel_static # ( parameter C_FAMILY = "virtex6", // FPGA Family. Current version: virtex6 or spartan6. parameter C_VALUE = 4'b0, // Static value to compare against. parameter integer C_DATA_WIDTH = 4 // Data width for comparator. ) ( input wire CIN, input wire S, input wire [C_DATA_WIDTH-1:0] A, input wire [C_DATA_WIDTH-1:0] B, output wire COUT ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar bit_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Bits per LUT for this architecture. localparam integer C_BITS_PER_LUT = 2; // Constants for packing levels. localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; // localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : C_DATA_WIDTH; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// wire [C_FIX_DATA_WIDTH-1:0] a_local; wire [C_FIX_DATA_WIDTH-1:0] b_local; wire [C_FIX_DATA_WIDTH-1:0] v_local; wire [C_NUM_LUT-1:0] sel; wire [C_NUM_LUT:0] carry_local; ///////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////// generate // Assign input to local vectors. assign carry_local[0] = CIN; // Extend input data to fit. if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; end else begin : NO_EXTENDED_DATA assign a_local = A; assign b_local = B; assign v_local = C_VALUE; end // Instantiate one generic_baseblocks_v2_1_0_carry and per level. for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL // Create the local select signal assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) | ( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) ); // Instantiate each LUT level. generic_baseblocks_v2_1_0_carry_and # ( .C_FAMILY(C_FAMILY) ) compare_inst ( .COUT (carry_local[bit_cnt+1]), .CIN (carry_local[bit_cnt]), .S (sel[bit_cnt]) ); end // end for bit_cnt // Assign output from local vector. assign COUT = carry_local[C_NUM_LUT]; endgenerate endmodule
module axi_infrastructure_v1_1_0_axi2vector # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// parameter integer C_AXI_PROTOCOL = 0, parameter integer C_AXI_ID_WIDTH = 4, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0, parameter integer C_AXI_AWUSER_WIDTH = 1, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_AXI_BUSER_WIDTH = 1, parameter integer C_AXI_ARUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AWPAYLOAD_WIDTH = 61, parameter integer C_WPAYLOAD_WIDTH = 73, parameter integer C_BPAYLOAD_WIDTH = 6, parameter integer C_ARPAYLOAD_WIDTH = 61, parameter integer C_RPAYLOAD_WIDTH = 69 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // Slave Interface Write Address Ports input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid, input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen, input wire [3-1:0] s_axi_awsize, input wire [2-1:0] s_axi_awburst, input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock, input wire [4-1:0] s_axi_awcache, input wire [3-1:0] s_axi_awprot, input wire [4-1:0] s_axi_awregion, input wire [4-1:0] s_axi_awqos, input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, // Slave Interface Write Data Ports input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid, input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata, input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, input wire s_axi_wlast, input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, // Slave Interface Write Response Ports output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid, output wire [2-1:0] s_axi_bresp, output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser, // Slave Interface Read Address Ports input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid, input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen, input wire [3-1:0] s_axi_arsize, input wire [2-1:0] s_axi_arburst, input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock, input wire [4-1:0] s_axi_arcache, input wire [3-1:0] s_axi_arprot, input wire [4-1:0] s_axi_arregion, input wire [4-1:0] s_axi_arqos, input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, // Slave Interface Read Data Ports output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid, output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata, output wire [2-1:0] s_axi_rresp, output wire s_axi_rlast, output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, // payloads output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload, output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload, input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload, output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload, input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload ); //////////////////////////////////////////////////////////////////////////////// // Functions //////////////////////////////////////////////////////////////////////////////// `include "axi_infrastructure_v1_1_0.vh" //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// // AXI4, AXI4LITE, AXI3 packing assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr; assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot; assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata; assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb; assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH]; assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr; assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot; assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH]; assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH]; generate if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize; assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst; assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache; assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen; assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock; assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid; assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos; assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast; if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid; end else begin : gen_no_axi3_wid_packing end assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH]; assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize; assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst; assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache; assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen; assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock; assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid; assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos; assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH]; assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH]; if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion; assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion; end else begin : gen_no_region_signals end if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser; assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser; assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH]; assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser; assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH]; end else begin : gen_no_user_signals assign s_axi_buser = 'b0; assign s_axi_ruser = 'b0; end end else begin : gen_axi4lite_packing assign s_axi_bid = 'b0; assign s_axi_buser = 'b0; assign s_axi_rlast = 1'b1; assign s_axi_rid = 'b0; assign s_axi_ruser = 'b0; end endgenerate endmodule
module axi_infrastructure_v1_1_0_axic_srl_fifo #( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// parameter C_FAMILY = "virtex7", parameter integer C_PAYLOAD_WIDTH = 1, parameter integer C_FIFO_DEPTH = 16 // Range: 4-16. ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire aclk, // Clock input wire aresetn, // Reset input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data input wire s_valid, // Input data valid output reg s_ready, // Input data ready output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data output reg m_valid, // Output data valid input wire m_ready // Output data ready ); //////////////////////////////////////////////////////////////////////////////// // Functions //////////////////////////////////////////////////////////////////////////////// // ceiling logb2 function integer f_clogb2 (input integer size); integer s; begin s = size; s = s - 1; for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1) s = s >> 1; end endfunction // clogb2 //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH); //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index; wire [4-1:0] fifo_addr; wire push; wire pop ; reg areset_r1; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// always @(posedge aclk) begin areset_r1 <= ~aresetn; end always @(posedge aclk) begin if (~aresetn) begin fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}}; end else begin fifo_index <= push & ~pop ? fifo_index + 1'b1 : ~push & pop ? fifo_index - 1'b1 : fifo_index; end end assign push = s_valid & s_ready; always @(posedge aclk) begin if (~aresetn) begin s_ready <= 1'b0; end else begin s_ready <= areset_r1 ? 1'b1 : push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 : ~push & pop ? 1'b1 : s_ready; end end assign pop = m_valid & m_ready; always @(posedge aclk) begin if (~aresetn) begin m_valid <= 1'b0; end else begin m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 : push & ~pop ? 1'b1 : m_valid; end end generate if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0]; assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}}; end else begin : gen_fifo_addr assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0]; end endgenerate generate genvar i; for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit SRL16E u_srl_fifo( .Q ( m_payload[i] ) , .A0 ( fifo_addr[0] ) , .A1 ( fifo_addr[1] ) , .A2 ( fifo_addr[2] ) , .A3 ( fifo_addr[3] ) , .CE ( push ) , .CLK ( aclk ) , .D ( s_payload[i] ) ); end endgenerate endmodule
module axi_infrastructure_v1_1_0_vector2axi # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// parameter integer C_AXI_PROTOCOL = 0, parameter integer C_AXI_ID_WIDTH = 4, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0, parameter integer C_AXI_AWUSER_WIDTH = 1, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_AXI_BUSER_WIDTH = 1, parameter integer C_AXI_ARUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AWPAYLOAD_WIDTH = 61, parameter integer C_WPAYLOAD_WIDTH = 73, parameter integer C_BPAYLOAD_WIDTH = 6, parameter integer C_ARPAYLOAD_WIDTH = 61, parameter integer C_RPAYLOAD_WIDTH = 69 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // Slave Interface Write Address Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid, output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, output wire [3-1:0] m_axi_awsize, output wire [2-1:0] m_axi_awburst, output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, output wire [4-1:0] m_axi_awcache, output wire [3-1:0] m_axi_awprot, output wire [4-1:0] m_axi_awregion, output wire [4-1:0] m_axi_awqos, output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, // Slave Interface Write Data Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid, output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata, output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, output wire m_axi_wlast, output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, // Slave Interface Write Response Ports input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid, input wire [2-1:0] m_axi_bresp, input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser, // Slave Interface Read Address Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid, output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, output wire [3-1:0] m_axi_arsize, output wire [2-1:0] m_axi_arburst, output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, output wire [4-1:0] m_axi_arcache, output wire [3-1:0] m_axi_arprot, output wire [4-1:0] m_axi_arregion, output wire [4-1:0] m_axi_arqos, output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, // Slave Interface Read Data Ports input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid, input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata, input wire [2-1:0] m_axi_rresp, input wire m_axi_rlast, input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, // payloads input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload, input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload, output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload, input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload, output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload ); //////////////////////////////////////////////////////////////////////////////// // Functions //////////////////////////////////////////////////////////////////////////////// `include "axi_infrastructure_v1_1_0.vh" //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// // AXI4, AXI4LITE, AXI3 packing assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH]; assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH]; assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH]; assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH]; assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp; assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH]; assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH]; assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata; assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp; generate if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ; assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH]; assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH]; assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ; assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ; assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ; assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ; assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ; if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ; end else begin : gen_no_axi3_wid_packing assign m_axi_wid = 1'b0; end assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid; assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ; assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH]; assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH]; assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ; assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ; assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ; assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ; assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast; assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ; if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH]; assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH]; end else begin : gen_no_region_signals assign m_axi_awregion = 'b0; assign m_axi_arregion = 'b0; end if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH]; assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ; assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ; assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH]; assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ; end else begin : gen_no_user_signals assign m_axi_awuser = 'b0; assign m_axi_wuser = 'b0; assign m_axi_aruser = 'b0; end end else begin : gen_axi4lite_packing assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3; assign m_axi_awburst = 'b0; assign m_axi_awcache = 'b0; assign m_axi_awlen = 'b0; assign m_axi_awlock = 'b0; assign m_axi_awid = 'b0; assign m_axi_awqos = 'b0; assign m_axi_wlast = 1'b1; assign m_axi_wid = 'b0; assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3; assign m_axi_arburst = 'b0; assign m_axi_arcache = 'b0; assign m_axi_arlen = 'b0; assign m_axi_arlock = 'b0; assign m_axi_arid = 'b0; assign m_axi_arqos = 'b0; assign m_axi_awregion = 'b0; assign m_axi_arregion = 'b0; assign m_axi_awuser = 'b0; assign m_axi_wuser = 'b0; assign m_axi_aruser = 'b0; end endgenerate endmodule
module axi_infrastructure_v1_1_0_axic_srl_fifo #( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// parameter C_FAMILY = "virtex7", parameter integer C_PAYLOAD_WIDTH = 1, parameter integer C_FIFO_DEPTH = 16 // Range: 4-16. ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire aclk, // Clock input wire aresetn, // Reset input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data input wire s_valid, // Input data valid output reg s_ready, // Input data ready output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data output reg m_valid, // Output data valid input wire m_ready // Output data ready ); //////////////////////////////////////////////////////////////////////////////// // Functions //////////////////////////////////////////////////////////////////////////////// // ceiling logb2 function integer f_clogb2 (input integer size); integer s; begin s = size; s = s - 1; for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1) s = s >> 1; end endfunction // clogb2 //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH); //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index; wire [4-1:0] fifo_addr; wire push; wire pop ; reg areset_r1; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// always @(posedge aclk) begin areset_r1 <= ~aresetn; end always @(posedge aclk) begin if (~aresetn) begin fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}}; end else begin fifo_index <= push & ~pop ? fifo_index + 1'b1 : ~push & pop ? fifo_index - 1'b1 : fifo_index; end end assign push = s_valid & s_ready; always @(posedge aclk) begin if (~aresetn) begin s_ready <= 1'b0; end else begin s_ready <= areset_r1 ? 1'b1 : push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 : ~push & pop ? 1'b1 : s_ready; end end assign pop = m_valid & m_ready; always @(posedge aclk) begin if (~aresetn) begin m_valid <= 1'b0; end else begin m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 : push & ~pop ? 1'b1 : m_valid; end end generate if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0]; assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}}; end else begin : gen_fifo_addr assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0]; end endgenerate generate genvar i; for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit SRL16E u_srl_fifo( .Q ( m_payload[i] ) , .A0 ( fifo_addr[0] ) , .A1 ( fifo_addr[1] ) , .A2 ( fifo_addr[2] ) , .A3 ( fifo_addr[3] ) , .CE ( push ) , .CLK ( aclk ) , .D ( s_payload[i] ) ); end endgenerate endmodule
module axi_infrastructure_v1_1_0_axic_srl_fifo #( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// parameter C_FAMILY = "virtex7", parameter integer C_PAYLOAD_WIDTH = 1, parameter integer C_FIFO_DEPTH = 16 // Range: 4-16. ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire aclk, // Clock input wire aresetn, // Reset input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data input wire s_valid, // Input data valid output reg s_ready, // Input data ready output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data output reg m_valid, // Output data valid input wire m_ready // Output data ready ); //////////////////////////////////////////////////////////////////////////////// // Functions //////////////////////////////////////////////////////////////////////////////// // ceiling logb2 function integer f_clogb2 (input integer size); integer s; begin s = size; s = s - 1; for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1) s = s >> 1; end endfunction // clogb2 //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH); //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index; wire [4-1:0] fifo_addr; wire push; wire pop ; reg areset_r1; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// always @(posedge aclk) begin areset_r1 <= ~aresetn; end always @(posedge aclk) begin if (~aresetn) begin fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}}; end else begin fifo_index <= push & ~pop ? fifo_index + 1'b1 : ~push & pop ? fifo_index - 1'b1 : fifo_index; end end assign push = s_valid & s_ready; always @(posedge aclk) begin if (~aresetn) begin s_ready <= 1'b0; end else begin s_ready <= areset_r1 ? 1'b1 : push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 : ~push & pop ? 1'b1 : s_ready; end end assign pop = m_valid & m_ready; always @(posedge aclk) begin if (~aresetn) begin m_valid <= 1'b0; end else begin m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 : push & ~pop ? 1'b1 : m_valid; end end generate if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0]; assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}}; end else begin : gen_fifo_addr assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0]; end endgenerate generate genvar i; for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit SRL16E u_srl_fifo( .Q ( m_payload[i] ) , .A0 ( fifo_addr[0] ) , .A1 ( fifo_addr[1] ) , .A2 ( fifo_addr[2] ) , .A3 ( fifo_addr[3] ) , .CE ( push ) , .CLK ( aclk ) , .D ( s_payload[i] ) ); end endgenerate endmodule
module axi_infrastructure_v1_1_0_axic_srl_fifo #( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// parameter C_FAMILY = "virtex7", parameter integer C_PAYLOAD_WIDTH = 1, parameter integer C_FIFO_DEPTH = 16 // Range: 4-16. ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire aclk, // Clock input wire aresetn, // Reset input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data input wire s_valid, // Input data valid output reg s_ready, // Input data ready output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data output reg m_valid, // Output data valid input wire m_ready // Output data ready ); //////////////////////////////////////////////////////////////////////////////// // Functions //////////////////////////////////////////////////////////////////////////////// // ceiling logb2 function integer f_clogb2 (input integer size); integer s; begin s = size; s = s - 1; for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1) s = s >> 1; end endfunction // clogb2 //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH); //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index; wire [4-1:0] fifo_addr; wire push; wire pop ; reg areset_r1; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// always @(posedge aclk) begin areset_r1 <= ~aresetn; end always @(posedge aclk) begin if (~aresetn) begin fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}}; end else begin fifo_index <= push & ~pop ? fifo_index + 1'b1 : ~push & pop ? fifo_index - 1'b1 : fifo_index; end end assign push = s_valid & s_ready; always @(posedge aclk) begin if (~aresetn) begin s_ready <= 1'b0; end else begin s_ready <= areset_r1 ? 1'b1 : push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 : ~push & pop ? 1'b1 : s_ready; end end assign pop = m_valid & m_ready; always @(posedge aclk) begin if (~aresetn) begin m_valid <= 1'b0; end else begin m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 : push & ~pop ? 1'b1 : m_valid; end end generate if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0]; assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}}; end else begin : gen_fifo_addr assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0]; end endgenerate generate genvar i; for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit SRL16E u_srl_fifo( .Q ( m_payload[i] ) , .A0 ( fifo_addr[0] ) , .A1 ( fifo_addr[1] ) , .A2 ( fifo_addr[2] ) , .A3 ( fifo_addr[3] ) , .CE ( push ) , .CLK ( aclk ) , .D ( s_payload[i] ) ); end endgenerate endmodule
module reset_and_status #( parameter PIO_WIDTH=32 ) ( input clk, input resetn, output reg [PIO_WIDTH-1 : 0 ] pio_in, input [PIO_WIDTH-1 : 0 ] pio_out, input lock_kernel_pll, input fixedclk_locked, // pcie fixedclk lock input mem0_local_cal_success, input mem0_local_cal_fail, input mem0_local_init_done, input mem1_local_cal_success, input mem1_local_cal_fail, input mem1_local_init_done, output reg [1:0] mem_organization, output [1:0] mem_organization_export, output pll_reset, output reg sw_reset_n_out ); reg [1:0] pio_out_ddr_mode; reg pio_out_pll_reset; reg pio_out_sw_reset; reg [9:0] reset_count; always@(posedge clk or negedge resetn) if (!resetn) reset_count <= 10'b0; else if (pio_out_sw_reset) reset_count <= 10'b0; else if (!reset_count[9]) reset_count <= reset_count + 2'b01; // false paths set for pio_out_* (* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_out_*]\"" *) always@(posedge clk) begin pio_out_ddr_mode = pio_out[9:8]; pio_out_pll_reset = pio_out[30]; pio_out_sw_reset = pio_out[31]; end // false paths for pio_in - these are asynchronous (* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_in*]\"" *) always@(posedge clk) begin pio_in = { lock_kernel_pll, fixedclk_locked, 1'b0, 1'b0, mem1_local_cal_fail, mem0_local_cal_fail, mem1_local_cal_success, mem1_local_init_done, mem0_local_cal_success, mem0_local_init_done}; end (* altera_attribute = "-name SDC_STATEMENT \"set_false_path -from [get_registers *mem_organization*]\"" *) always@(posedge clk) mem_organization = pio_out_ddr_mode; assign mem_organization_export = mem_organization; assign pll_reset = pio_out_pll_reset; // Export sw kernel reset out of iface to connect to kernel always@(posedge clk) sw_reset_n_out = !(!reset_count[9] && (reset_count[8:0] != 0)); endmodule
module reset_and_status #( parameter PIO_WIDTH=32 ) ( input clk, input resetn, output reg [PIO_WIDTH-1 : 0 ] pio_in, input [PIO_WIDTH-1 : 0 ] pio_out, input lock_kernel_pll, input fixedclk_locked, // pcie fixedclk lock input mem0_local_cal_success, input mem0_local_cal_fail, input mem0_local_init_done, input mem1_local_cal_success, input mem1_local_cal_fail, input mem1_local_init_done, output reg [1:0] mem_organization, output [1:0] mem_organization_export, output pll_reset, output reg sw_reset_n_out ); reg [1:0] pio_out_ddr_mode; reg pio_out_pll_reset; reg pio_out_sw_reset; reg [9:0] reset_count; always@(posedge clk or negedge resetn) if (!resetn) reset_count <= 10'b0; else if (pio_out_sw_reset) reset_count <= 10'b0; else if (!reset_count[9]) reset_count <= reset_count + 2'b01; // false paths set for pio_out_* (* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_out_*]\"" *) always@(posedge clk) begin pio_out_ddr_mode = pio_out[9:8]; pio_out_pll_reset = pio_out[30]; pio_out_sw_reset = pio_out[31]; end // false paths for pio_in - these are asynchronous (* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_in*]\"" *) always@(posedge clk) begin pio_in = { lock_kernel_pll, fixedclk_locked, 1'b0, 1'b0, mem1_local_cal_fail, mem0_local_cal_fail, mem1_local_cal_success, mem1_local_init_done, mem0_local_cal_success, mem0_local_init_done}; end (* altera_attribute = "-name SDC_STATEMENT \"set_false_path -from [get_registers *mem_organization*]\"" *) always@(posedge clk) mem_organization = pio_out_ddr_mode; assign mem_organization_export = mem_organization; assign pll_reset = pio_out_pll_reset; // Export sw kernel reset out of iface to connect to kernel always@(posedge clk) sw_reset_n_out = !(!reset_count[9] && (reset_count[8:0] != 0)); endmodule
module reset_and_status #( parameter PIO_WIDTH=32 ) ( input clk, input resetn, output reg [PIO_WIDTH-1 : 0 ] pio_in, input [PIO_WIDTH-1 : 0 ] pio_out, input lock_kernel_pll, input fixedclk_locked, // pcie fixedclk lock input mem0_local_cal_success, input mem0_local_cal_fail, input mem0_local_init_done, input mem1_local_cal_success, input mem1_local_cal_fail, input mem1_local_init_done, output reg [1:0] mem_organization, output [1:0] mem_organization_export, output pll_reset, output reg sw_reset_n_out ); reg [1:0] pio_out_ddr_mode; reg pio_out_pll_reset; reg pio_out_sw_reset; reg [9:0] reset_count; always@(posedge clk or negedge resetn) if (!resetn) reset_count <= 10'b0; else if (pio_out_sw_reset) reset_count <= 10'b0; else if (!reset_count[9]) reset_count <= reset_count + 2'b01; // false paths set for pio_out_* (* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_out_*]\"" *) always@(posedge clk) begin pio_out_ddr_mode = pio_out[9:8]; pio_out_pll_reset = pio_out[30]; pio_out_sw_reset = pio_out[31]; end // false paths for pio_in - these are asynchronous (* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_in*]\"" *) always@(posedge clk) begin pio_in = { lock_kernel_pll, fixedclk_locked, 1'b0, 1'b0, mem1_local_cal_fail, mem0_local_cal_fail, mem1_local_cal_success, mem1_local_init_done, mem0_local_cal_success, mem0_local_init_done}; end (* altera_attribute = "-name SDC_STATEMENT \"set_false_path -from [get_registers *mem_organization*]\"" *) always@(posedge clk) mem_organization = pio_out_ddr_mode; assign mem_organization_export = mem_organization; assign pll_reset = pio_out_pll_reset; // Export sw kernel reset out of iface to connect to kernel always@(posedge clk) sw_reset_n_out = !(!reset_count[9] && (reset_count[8:0] != 0)); endmodule
module reset_and_status #( parameter PIO_WIDTH=32 ) ( input clk, input resetn, output reg [PIO_WIDTH-1 : 0 ] pio_in, input [PIO_WIDTH-1 : 0 ] pio_out, input lock_kernel_pll, input fixedclk_locked, // pcie fixedclk lock input mem0_local_cal_success, input mem0_local_cal_fail, input mem0_local_init_done, input mem1_local_cal_success, input mem1_local_cal_fail, input mem1_local_init_done, output reg [1:0] mem_organization, output [1:0] mem_organization_export, output pll_reset, output reg sw_reset_n_out ); reg [1:0] pio_out_ddr_mode; reg pio_out_pll_reset; reg pio_out_sw_reset; reg [9:0] reset_count; always@(posedge clk or negedge resetn) if (!resetn) reset_count <= 10'b0; else if (pio_out_sw_reset) reset_count <= 10'b0; else if (!reset_count[9]) reset_count <= reset_count + 2'b01; // false paths set for pio_out_* (* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_out_*]\"" *) always@(posedge clk) begin pio_out_ddr_mode = pio_out[9:8]; pio_out_pll_reset = pio_out[30]; pio_out_sw_reset = pio_out[31]; end // false paths for pio_in - these are asynchronous (* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_in*]\"" *) always@(posedge clk) begin pio_in = { lock_kernel_pll, fixedclk_locked, 1'b0, 1'b0, mem1_local_cal_fail, mem0_local_cal_fail, mem1_local_cal_success, mem1_local_init_done, mem0_local_cal_success, mem0_local_init_done}; end (* altera_attribute = "-name SDC_STATEMENT \"set_false_path -from [get_registers *mem_organization*]\"" *) always@(posedge clk) mem_organization = pio_out_ddr_mode; assign mem_organization_export = mem_organization; assign pll_reset = pio_out_pll_reset; // Export sw kernel reset out of iface to connect to kernel always@(posedge clk) sw_reset_n_out = !(!reset_count[9] && (reset_count[8:0] != 0)); endmodule
module generic_baseblocks_v2_1_0_mux # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_SEL_WIDTH = 4, // Data width for comparator. parameter integer C_DATA_WIDTH = 2 // Data width for comparator. ) ( input wire [C_SEL_WIDTH-1:0] S, input wire [(2**C_SEL_WIDTH)*C_DATA_WIDTH-1:0] A, output wire [C_DATA_WIDTH-1:0] O ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar bit_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Instantiate or use RTL code ///////////////////////////////////////////////////////////////////////////// generate if ( C_FAMILY == "rtl" || C_SEL_WIDTH < 3 ) begin : USE_RTL assign O = A[(S)*C_DATA_WIDTH +: C_DATA_WIDTH]; end else begin : USE_FPGA wire [C_DATA_WIDTH-1:0] C; wire [C_DATA_WIDTH-1:0] D; // Lower half recursively. generic_baseblocks_v2_1_0_mux # ( .C_FAMILY (C_FAMILY), .C_SEL_WIDTH (C_SEL_WIDTH-1), .C_DATA_WIDTH (C_DATA_WIDTH) ) mux_c_inst ( .S (S[C_SEL_WIDTH-2:0]), .A (A[(2**(C_SEL_WIDTH-1))*C_DATA_WIDTH-1 : 0]), .O (C) ); // Upper half recursively. generic_baseblocks_v2_1_0_mux # ( .C_FAMILY (C_FAMILY), .C_SEL_WIDTH (C_SEL_WIDTH-1), .C_DATA_WIDTH (C_DATA_WIDTH) ) mux_d_inst ( .S (S[C_SEL_WIDTH-2:0]), .A (A[(2**C_SEL_WIDTH)*C_DATA_WIDTH-1 : (2**(C_SEL_WIDTH-1))*C_DATA_WIDTH]), .O (D) ); // Generate instantiated generic_baseblocks_v2_1_0_mux components as required. for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : NUM if ( C_SEL_WIDTH == 4 ) begin : USE_F8 MUXF8 muxf8_inst ( .I0 (C[bit_cnt]), .I1 (D[bit_cnt]), .S (S[C_SEL_WIDTH-1]), .O (O[bit_cnt]) ); end else if ( C_SEL_WIDTH == 3 ) begin : USE_F7 MUXF7 muxf7_inst ( .I0 (C[bit_cnt]), .I1 (D[bit_cnt]), .S (S[C_SEL_WIDTH-1]), .O (O[bit_cnt]) ); end // C_SEL_WIDTH end // end for bit_cnt end endgenerate endmodule
module generic_baseblocks_v2_1_0_mux # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_SEL_WIDTH = 4, // Data width for comparator. parameter integer C_DATA_WIDTH = 2 // Data width for comparator. ) ( input wire [C_SEL_WIDTH-1:0] S, input wire [(2**C_SEL_WIDTH)*C_DATA_WIDTH-1:0] A, output wire [C_DATA_WIDTH-1:0] O ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// // Generate variable for bit vector. genvar bit_cnt; ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Instantiate or use RTL code ///////////////////////////////////////////////////////////////////////////// generate if ( C_FAMILY == "rtl" || C_SEL_WIDTH < 3 ) begin : USE_RTL assign O = A[(S)*C_DATA_WIDTH +: C_DATA_WIDTH]; end else begin : USE_FPGA wire [C_DATA_WIDTH-1:0] C; wire [C_DATA_WIDTH-1:0] D; // Lower half recursively. generic_baseblocks_v2_1_0_mux # ( .C_FAMILY (C_FAMILY), .C_SEL_WIDTH (C_SEL_WIDTH-1), .C_DATA_WIDTH (C_DATA_WIDTH) ) mux_c_inst ( .S (S[C_SEL_WIDTH-2:0]), .A (A[(2**(C_SEL_WIDTH-1))*C_DATA_WIDTH-1 : 0]), .O (C) ); // Upper half recursively. generic_baseblocks_v2_1_0_mux # ( .C_FAMILY (C_FAMILY), .C_SEL_WIDTH (C_SEL_WIDTH-1), .C_DATA_WIDTH (C_DATA_WIDTH) ) mux_d_inst ( .S (S[C_SEL_WIDTH-2:0]), .A (A[(2**C_SEL_WIDTH)*C_DATA_WIDTH-1 : (2**(C_SEL_WIDTH-1))*C_DATA_WIDTH]), .O (D) ); // Generate instantiated generic_baseblocks_v2_1_0_mux components as required. for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : NUM if ( C_SEL_WIDTH == 4 ) begin : USE_F8 MUXF8 muxf8_inst ( .I0 (C[bit_cnt]), .I1 (D[bit_cnt]), .S (S[C_SEL_WIDTH-1]), .O (O[bit_cnt]) ); end else if ( C_SEL_WIDTH == 3 ) begin : USE_F7 MUXF7 muxf7_inst ( .I0 (C[bit_cnt]), .I1 (D[bit_cnt]), .S (S[C_SEL_WIDTH-1]), .O (O[bit_cnt]) ); end // C_SEL_WIDTH end // end for bit_cnt end endgenerate endmodule
module read_signal_breakout ( read_command_data_in, // descriptor from the read FIFO read_command_data_out, // reformated descriptor to the read master // breakout of command information read_address, read_length, read_transmit_channel, read_generate_sop, read_generate_eop, read_park, read_transfer_complete_IRQ_mask, read_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground read_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground read_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground read_transmit_error, read_early_done_enable, // additional control information that needs to go out asynchronously with the command data read_stop, read_sw_reset ); parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits input [DATA_WIDTH-1:0] read_command_data_in; output wire [255:0] read_command_data_out; output wire [63:0] read_address; output wire [31:0] read_length; output wire [7:0] read_transmit_channel; output wire read_generate_sop; output wire read_generate_eop; output wire read_park; output wire read_transfer_complete_IRQ_mask; output wire [7:0] read_burst_count; output wire [15:0] read_stride; output wire [15:0] read_sequence_number; output wire [7:0] read_transmit_error; output wire read_early_done_enable; input read_stop; input read_sw_reset; assign read_address[31:0] = read_command_data_in[31:0]; assign read_length = read_command_data_in[95:64]; generate if (DATA_WIDTH == 256) begin assign read_early_done_enable = read_command_data_in[248]; assign read_transmit_error = read_command_data_in[247:240]; assign read_transmit_channel = read_command_data_in[231:224]; assign read_generate_sop = read_command_data_in[232]; assign read_generate_eop = read_command_data_in[233]; assign read_park = read_command_data_in[234]; assign read_transfer_complete_IRQ_mask = read_command_data_in[238]; assign read_burst_count = read_command_data_in[119:112]; assign read_stride = read_command_data_in[143:128]; assign read_sequence_number = read_command_data_in[111:96]; assign read_address[63:32] = read_command_data_in[191:160]; end else begin assign read_early_done_enable = read_command_data_in[120]; assign read_transmit_error = read_command_data_in[119:112]; assign read_transmit_channel = read_command_data_in[103:96]; assign read_generate_sop = read_command_data_in[104]; assign read_generate_eop = read_command_data_in[105]; assign read_park = read_command_data_in[106]; assign read_transfer_complete_IRQ_mask = read_command_data_in[110]; assign read_burst_count = 8'h00; assign read_stride = 16'h0000; assign read_sequence_number = 16'h0000; assign read_address[63:32] = 32'h00000000; end endgenerate // big concat statement to glue all the signals back together to go out to the read master (MSBs to LSBs) assign read_command_data_out = {{115{1'b0}}, // zero pad the upper 115 bits read_address[63:32], read_early_done_enable, read_transmit_error, read_stride, read_burst_count, read_sw_reset, read_stop, read_generate_eop, read_generate_sop, read_transmit_channel, read_length, read_address[31:0]}; endmodule
module dispatcher ( clk, reset, // 128/256 bit write only port for feeding the dispatcher descriptors, no address since it's only one word wide, blocking when too many descriptors are buffered descriptor_writedata, descriptor_byteenable, descriptor_write, descriptor_waitrequest, // control and status port, 32 bits wide with a read latency of 2 and non-blocking csr_writedata, csr_byteenable, csr_write, csr_readdata, csr_read, csr_address, // 4 addresses when ENHANCED_FEATURES is off (zero) otherwise 8 addresses are available csr_irq, // only available if the response port is not an ST source (in that case the SGDMA pre-fetching block will issue interrupts) // response slave port (when "RESPONSE_PORT" is set to 0), 32 bits wide, read only, and a read latency of 3 cycles mm_response_readdata, mm_response_read, mm_response_address, // only two addresses mm_response_byteenable, // last byte read pops the response FIFO mm_response_waitrequest, // response source port (when "RESPONSE_PORT" is set to 1), src_response_data, src_response_valid, src_response_ready, // write master source port (sends commands to write master) src_write_master_data, src_write_master_valid, src_write_master_ready, // write master sink port (recieves response from write master) snk_write_master_data, snk_write_master_valid, snk_write_master_ready, // read master source port (sends commands to read master) src_read_master_data, src_read_master_valid, src_read_master_ready, // read master sink port (recieves response from the read master) snk_read_master_data, snk_read_master_valid, snk_read_master_ready ); // y = log2(x) function integer log2; input integer x; begin x = x-1; for(log2=0; x>0; log2=log2+1) x = x>>1; end endfunction parameter MODE = 0; // 0 for MM->MM, 1 for MM->ST, 2 for ST->MM parameter RESPONSE_PORT = 0; // 0 for MM, 1 for ST, 2 for Disabled // normally disabled for all but ST->MM transfers parameter DESCRIPTOR_FIFO_DEPTH = 128; // 16-1024 in powers of 2 parameter ENHANCED_FEATURES = 1; // 1 for Enabled, 0 for Disabled parameter DESCRIPTOR_WIDTH = 256; // 256 when enhanced mode is on, 128 for off (needs to be controlled by callback since it influences data width) parameter DESCRIPTOR_BYTEENABLE_WIDTH = 32; // 32 when enhanced mode is on, 16 for off (needs to be controlled by callback since it influences byte enable width) parameter CSR_ADDRESS_WIDTH = 3; // always 3 bits wide localparam RESPONSE_FIFO_DEPTH = 2 * DESCRIPTOR_FIFO_DEPTH; localparam DESCRIPTOR_FIFO_DEPTH_LOG2 = log2(DESCRIPTOR_FIFO_DEPTH); localparam RESPONSE_FIFO_DEPTH_LOG2 = log2(RESPONSE_FIFO_DEPTH); input clk; input reset; input [DESCRIPTOR_WIDTH-1:0] descriptor_writedata; input [DESCRIPTOR_BYTEENABLE_WIDTH-1:0] descriptor_byteenable; input descriptor_write; output wire descriptor_waitrequest; input [31:0] csr_writedata; input [3:0] csr_byteenable; input csr_write; output wire [31:0] csr_readdata; input csr_read; input [CSR_ADDRESS_WIDTH-1:0] csr_address; output wire csr_irq; // Used by a host with a master (like Nios II) output wire [31:0] mm_response_readdata; input mm_response_read; input mm_response_address; input [3:0] mm_response_byteenable; output wire mm_response_waitrequest; // Used by a pre-fetching master output wire [255:0] src_response_data; // making wide in case we need to jam more signals in here, unnecessary bits will be grounded/optimized away output wire src_response_valid; input src_response_ready; output wire [255:0] src_write_master_data; // don't know how many bits the master will use, unnecessary bits will be grounded/optimized away output wire src_write_master_valid; input src_write_master_ready; input [255:0] snk_write_master_data; // might need to jam more bits in...... input snk_write_master_valid; output wire snk_write_master_ready; output wire [255:0] src_read_master_data; // don't know how many bits the master will use, unnecessary bits will be grounded/optimized away output wire src_read_master_valid; input src_read_master_ready; input [255:0] snk_read_master_data; // might need to jam more bits in...... input snk_read_master_valid; output wire snk_read_master_ready; /* Internal wires and registers */ // descriptor information wire read_command_valid; wire read_command_ready; wire [255:0] read_command_data; wire read_command_empty; wire read_command_full; wire [DESCRIPTOR_FIFO_DEPTH_LOG2:0] read_command_used; // true used signal so extra MSB is included wire write_command_valid; wire write_command_ready; wire [255:0] write_command_data; wire write_command_empty; wire write_command_full; wire [DESCRIPTOR_FIFO_DEPTH_LOG2:0] write_command_used; // true used signal so extra MSB is included wire [31:0] sequence_number; wire transfer_complete_IRQ_mask; wire early_termination_IRQ_mask; wire [7:0] error_IRQ_mask; wire descriptor_buffer_empty; wire descriptor_buffer_full; wire [15:0] write_descriptor_watermark; wire [15:0] read_descriptor_watermark; wire [31:0] descriptor_watermark; wire busy; wire done; wire done_strobe; wire stop_issuing_commands; wire stop; wire sw_reset; wire stop_on_error; wire stop_on_early_termination; wire stop_descriptors; wire reset_stalled; wire master_stop_state; wire descriptors_stop_state; wire stop_state; wire stopped_on_error; wire stopped_on_early_termination; wire response_fifo_full; wire response_fifo_empty; wire [15:0] response_watermark; wire [7:0] response_error; wire response_early_termination; wire [31:0] response_actual_bytes_transferred; /************************************************ REGISTERS *******************************************************/ /********************************************** END REGISTERS *****************************************************/ /******************************************* MODULE DECLERATIONS **************************************************/ // the descriptor buffers block instantiates the descriptor FIFOs and handshaking logic with the master command ports descriptor_buffers the_descriptor_buffers ( .clk (clk), .reset (reset), .writedata (descriptor_writedata), .write (descriptor_write), .byteenable (descriptor_byteenable), .waitrequest (descriptor_waitrequest), .read_command_valid (read_command_valid), .read_command_ready (read_command_ready), .read_command_data (read_command_data), .read_command_empty (read_command_empty), .read_command_full (read_command_full), .read_command_used (read_command_used), .write_command_valid (write_command_valid), .write_command_ready (write_command_ready), .write_command_data (write_command_data), .write_command_empty (write_command_empty), .write_command_full (write_command_full), .write_command_used (write_command_used), .stop_issuing_commands (stop_issuing_commands), .stop (stop), .sw_reset (sw_reset), .sequence_number (sequence_number), .transfer_complete_IRQ_mask (transfer_complete_IRQ_mask), .early_termination_IRQ_mask (early_termination_IRQ_mask), .error_IRQ_mask (error_IRQ_mask) ); defparam the_descriptor_buffers.MODE = MODE; defparam the_descriptor_buffers.DATA_WIDTH = DESCRIPTOR_WIDTH; defparam the_descriptor_buffers.BYTE_ENABLE_WIDTH = DESCRIPTOR_WIDTH/8; defparam the_descriptor_buffers.FIFO_DEPTH = DESCRIPTOR_FIFO_DEPTH; defparam the_descriptor_buffers.FIFO_DEPTH_LOG2 = DESCRIPTOR_FIFO_DEPTH_LOG2; // Control and status registers (and interrupts when a host connects directly to this block) csr_block the_csr_block ( .clk (clk), .reset (reset), .csr_writedata (csr_writedata), .csr_write (csr_write), .csr_byteenable (csr_byteenable), .csr_readdata (csr_readdata), .csr_read (csr_read), .csr_address (csr_address), .csr_irq (csr_irq), .done_strobe (done_strobe), .busy (busy), .descriptor_buffer_empty (descriptor_buffer_empty), .descriptor_buffer_full (descriptor_buffer_full), .stop_state (stop_state), .stopped_on_error (stopped_on_error), .stopped_on_early_termination (stopped_on_early_termination), .stop_descriptors (stop_descriptors), .reset_stalled (reset_stalled), // from the master(s) to tell the CSR block that it's still resetting .stop (stop), .sw_reset (sw_reset), .stop_on_error (stop_on_error), .stop_on_early_termination (stop_on_early_termination), .sequence_number (sequence_number), .descriptor_watermark (descriptor_watermark), .response_watermark (response_watermark), .response_buffer_empty (response_fifo_empty), .response_buffer_full (response_fifo_full), .transfer_complete_IRQ_mask (transfer_complete_IRQ_mask), .error_IRQ_mask (error_IRQ_mask), .early_termination_IRQ_mask (early_termination_IRQ_mask), .error (response_error), .early_termination (response_early_termination) ); defparam the_csr_block.ADDRESS_WIDTH = CSR_ADDRESS_WIDTH; // Optional response port. When using a directly connected host it'll be a slave port and using a pre-fetching descriptor master it will be a streaming source port. response_block the_response_block ( .clk (clk), .reset (reset), .mm_response_readdata (mm_response_readdata), .mm_response_read (mm_response_read), .mm_response_address (mm_response_address), .mm_response_byteenable (mm_response_byteenable), .mm_response_waitrequest (mm_response_waitrequest), .src_response_data (src_response_data), .src_response_valid (src_response_valid), .src_response_ready (src_response_ready), .sw_reset (sw_reset), .response_watermark (response_watermark), .response_fifo_full (response_fifo_full), .response_fifo_empty (response_fifo_empty), .done_strobe (done_strobe), .actual_bytes_transferred (response_actual_bytes_transferred), .error (response_error), .early_termination (response_early_termination), .transfer_complete_IRQ_mask (transfer_complete_IRQ_mask), .error_IRQ_mask (error_IRQ_mask), .early_termination_IRQ_mask (early_termination_IRQ_mask), .descriptor_buffer_full (descriptor_buffer_full) ); defparam the_response_block.RESPONSE_PORT = RESPONSE_PORT; defparam the_response_block.FIFO_DEPTH = RESPONSE_FIFO_DEPTH; defparam the_response_block.FIFO_DEPTH_LOG2 = RESPONSE_FIFO_DEPTH_LOG2; /***************************************** END MODULE DECLERATIONS ************************************************/ /****************************************** COMBINATIONAL SIGNALS *************************************************/ // this block issues the commands so it's always ready for a response. The response FIFO fill level will be used to // make sure additional ST-->MM commands are not issued if there is no room to catch the response. assign snk_write_master_ready = 1'b1; assign snk_read_master_ready = 1'b1; assign done = (MODE == 1)? snk_read_master_ready : snk_write_master_ready; assign done_strobe = (MODE == 1)? (snk_read_master_ready & snk_read_master_valid) : (snk_write_master_ready & snk_write_master_valid); assign stop_issuing_commands = (response_fifo_full == 1) | (stop_descriptors == 1); assign src_write_master_valid = write_command_valid; assign write_command_ready = src_write_master_ready; assign src_write_master_data = write_command_data; assign src_read_master_valid = read_command_valid; assign read_command_ready = src_read_master_ready; assign src_read_master_data = read_command_data; assign busy = (read_command_empty == 0) | (write_command_empty == 0) | // still have descriptors buffered in the FIFOs (done == 0); // current transfer is still occuring assign descriptor_buffer_empty = (read_command_empty == 1) & (write_command_empty == 1); assign descriptor_buffer_full = (read_command_full == 1) | (write_command_full == 1); assign write_descriptor_watermark = 16'h0000 | write_command_used; // zero padding the upper unused bits assign read_descriptor_watermark = 16'h0000 | read_command_used; // zero padding the upper unused bits assign descriptor_watermark = {write_descriptor_watermark, read_descriptor_watermark}; assign reset_stalled = snk_read_master_data[0] | snk_write_master_data[32]; assign master_stop_state = ((MODE == 0)? (snk_read_master_data[1] & snk_write_master_data[33]) : (MODE == 1)? snk_read_master_data[1] : snk_write_master_data[33]); assign descriptors_stop_state = (stop_descriptors == 1) & ((MODE == 0)? ((src_read_master_ready == 1) & (src_write_master_ready == 1)) : (MODE == 1)? (src_read_master_ready == 1) : (src_write_master_ready == 1)); assign stop_state = (master_stop_state == 1) | (descriptors_stop_state == 1); assign response_actual_bytes_transferred = snk_write_master_data[31:0]; assign response_error = snk_write_master_data[41:34]; assign response_early_termination = snk_write_master_data[42]; /**************************************** END COMBINATIONAL SIGNALS ***********************************************/ endmodule
module response_block ( clk, reset, mm_response_readdata, mm_response_read, mm_response_address, mm_response_byteenable, mm_response_waitrequest, src_response_data, src_response_valid, src_response_ready, sw_reset, response_watermark, response_fifo_full, response_fifo_empty, done_strobe, actual_bytes_transferred, error, early_termination, transfer_complete_IRQ_mask, error_IRQ_mask, early_termination_IRQ_mask, descriptor_buffer_full ); parameter RESPONSE_PORT = 0; // when disabled all the outputs will be disconnected by the component wrapper parameter FIFO_DEPTH = 256; // needs to be double the descriptor FIFO depth parameter FIFO_DEPTH_LOG2 = 8; localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51; // when 'RESPONSE_PORT' is 1 then the response port is set to streaming and must pass the interrupt masks as well input clk; input reset; output wire [31:0] mm_response_readdata; input mm_response_read; input mm_response_address; // only have 2 addresses input [3:0] mm_response_byteenable; output wire mm_response_waitrequest; output wire [255:0] src_response_data; // not going to use all these bits, the remainder will be grounded output wire src_response_valid; input src_response_ready; input sw_reset; output wire [15:0] response_watermark; output wire response_fifo_full; output wire response_fifo_empty; input done_strobe; input [31:0] actual_bytes_transferred; input [7:0] error; input early_termination; // all of these signals are only used the ST source response port since the pre-fetching master component will handle the interrupt generation as apposed to the CSR block input transfer_complete_IRQ_mask; input [7:0] error_IRQ_mask; input early_termination_IRQ_mask; input descriptor_buffer_full; // handy signal for the prefetching master to use so that it known when to blast a new descriptor into the dispatcher /* internal signals and registers */ wire [FIFO_DEPTH_LOG2-1:0] fifo_used; wire fifo_full; wire fifo_empty; wire fifo_read; wire [FIFO_WIDTH-1:0] fifo_input; wire [FIFO_WIDTH-1:0] fifo_output; generate if (RESPONSE_PORT == 0) // slave port used for response data begin assign fifo_input = {early_termination, error, actual_bytes_transferred}; assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1); // reading from the upper byte (byte offset 7) pops the fifo scfifo the_response_FIFO ( .clock (clk), .aclr (reset), .sclr (sw_reset), .data (fifo_input), .wrreq (done_strobe), .rdreq (fifo_read), .q (fifo_output), .full (fifo_full), .empty (fifo_empty), .usedw (fifo_used) ); defparam the_response_FIFO.lpm_width = FIFO_WIDTH; defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH; defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2; defparam the_response_FIFO.lpm_showahead = "ON"; defparam the_response_FIFO.use_eab = "ON"; defparam the_response_FIFO.overflow_checking = "OFF"; defparam the_response_FIFO.underflow_checking = "OFF"; defparam the_response_FIFO.add_ram_output_register = "ON"; defparam the_response_FIFO.lpm_type = "scfifo"; // either actual bytes transfered when address == 0 or {zero padding, early_termination, error[7:0]} when address = 1 assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]}; assign mm_response_waitrequest = fifo_empty; assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount assign response_fifo_full = fifo_full; assign response_fifo_empty = fifo_empty; // no streaming port so ground all of its outputs assign src_response_data = 0; assign src_response_valid = 0; end else if (RESPONSE_PORT == 1) // streaming source port used for response data (prefetcher will catch this data) begin assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred}; assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1); scfifo the_response_FIFO ( .clock (clk), .aclr (reset | sw_reset), .data (fifo_input), .wrreq (done_strobe), .rdreq (fifo_read), .q (fifo_output), .full (fifo_full), .empty (fifo_empty), .usedw (fifo_used) ); defparam the_response_FIFO.lpm_width = FIFO_WIDTH; defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH; defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2; defparam the_response_FIFO.lpm_showahead = "ON"; defparam the_response_FIFO.use_eab = "ON"; defparam the_response_FIFO.overflow_checking = "OFF"; defparam the_response_FIFO.underflow_checking = "OFF"; defparam the_response_FIFO.add_ram_output_register = "ON"; defparam the_response_FIFO.lpm_type = "scfifo"; assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output}; // zero padding the upper bits, also sending out the descriptor buffer full signal to simplify the throttling in the prefetching master (bit 52) assign src_response_valid = (fifo_empty == 0); assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount; assign response_fifo_full = fifo_full; assign response_fifo_empty = fifo_empty; // no slave port so ground all of its outputs assign mm_response_readdata = 0; assign mm_response_waitrequest = 0; end else // no response port so grounding all outputs begin assign fifo_input = 0; assign fifo_output = 0; assign mm_response_readdata = 0; assign mm_response_waitrequest = 0; assign src_response_data = 0; assign src_response_valid = 0; assign response_watermark = 0; assign response_fifo_full = 0; assign response_fifo_empty = 0; end endgenerate endmodule
module response_block ( clk, reset, mm_response_readdata, mm_response_read, mm_response_address, mm_response_byteenable, mm_response_waitrequest, src_response_data, src_response_valid, src_response_ready, sw_reset, response_watermark, response_fifo_full, response_fifo_empty, done_strobe, actual_bytes_transferred, error, early_termination, transfer_complete_IRQ_mask, error_IRQ_mask, early_termination_IRQ_mask, descriptor_buffer_full ); parameter RESPONSE_PORT = 0; // when disabled all the outputs will be disconnected by the component wrapper parameter FIFO_DEPTH = 256; // needs to be double the descriptor FIFO depth parameter FIFO_DEPTH_LOG2 = 8; localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51; // when 'RESPONSE_PORT' is 1 then the response port is set to streaming and must pass the interrupt masks as well input clk; input reset; output wire [31:0] mm_response_readdata; input mm_response_read; input mm_response_address; // only have 2 addresses input [3:0] mm_response_byteenable; output wire mm_response_waitrequest; output wire [255:0] src_response_data; // not going to use all these bits, the remainder will be grounded output wire src_response_valid; input src_response_ready; input sw_reset; output wire [15:0] response_watermark; output wire response_fifo_full; output wire response_fifo_empty; input done_strobe; input [31:0] actual_bytes_transferred; input [7:0] error; input early_termination; // all of these signals are only used the ST source response port since the pre-fetching master component will handle the interrupt generation as apposed to the CSR block input transfer_complete_IRQ_mask; input [7:0] error_IRQ_mask; input early_termination_IRQ_mask; input descriptor_buffer_full; // handy signal for the prefetching master to use so that it known when to blast a new descriptor into the dispatcher /* internal signals and registers */ wire [FIFO_DEPTH_LOG2-1:0] fifo_used; wire fifo_full; wire fifo_empty; wire fifo_read; wire [FIFO_WIDTH-1:0] fifo_input; wire [FIFO_WIDTH-1:0] fifo_output; generate if (RESPONSE_PORT == 0) // slave port used for response data begin assign fifo_input = {early_termination, error, actual_bytes_transferred}; assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1); // reading from the upper byte (byte offset 7) pops the fifo scfifo the_response_FIFO ( .clock (clk), .aclr (reset), .sclr (sw_reset), .data (fifo_input), .wrreq (done_strobe), .rdreq (fifo_read), .q (fifo_output), .full (fifo_full), .empty (fifo_empty), .usedw (fifo_used) ); defparam the_response_FIFO.lpm_width = FIFO_WIDTH; defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH; defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2; defparam the_response_FIFO.lpm_showahead = "ON"; defparam the_response_FIFO.use_eab = "ON"; defparam the_response_FIFO.overflow_checking = "OFF"; defparam the_response_FIFO.underflow_checking = "OFF"; defparam the_response_FIFO.add_ram_output_register = "ON"; defparam the_response_FIFO.lpm_type = "scfifo"; // either actual bytes transfered when address == 0 or {zero padding, early_termination, error[7:0]} when address = 1 assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]}; assign mm_response_waitrequest = fifo_empty; assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount assign response_fifo_full = fifo_full; assign response_fifo_empty = fifo_empty; // no streaming port so ground all of its outputs assign src_response_data = 0; assign src_response_valid = 0; end else if (RESPONSE_PORT == 1) // streaming source port used for response data (prefetcher will catch this data) begin assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred}; assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1); scfifo the_response_FIFO ( .clock (clk), .aclr (reset | sw_reset), .data (fifo_input), .wrreq (done_strobe), .rdreq (fifo_read), .q (fifo_output), .full (fifo_full), .empty (fifo_empty), .usedw (fifo_used) ); defparam the_response_FIFO.lpm_width = FIFO_WIDTH; defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH; defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2; defparam the_response_FIFO.lpm_showahead = "ON"; defparam the_response_FIFO.use_eab = "ON"; defparam the_response_FIFO.overflow_checking = "OFF"; defparam the_response_FIFO.underflow_checking = "OFF"; defparam the_response_FIFO.add_ram_output_register = "ON"; defparam the_response_FIFO.lpm_type = "scfifo"; assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output}; // zero padding the upper bits, also sending out the descriptor buffer full signal to simplify the throttling in the prefetching master (bit 52) assign src_response_valid = (fifo_empty == 0); assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount; assign response_fifo_full = fifo_full; assign response_fifo_empty = fifo_empty; // no slave port so ground all of its outputs assign mm_response_readdata = 0; assign mm_response_waitrequest = 0; end else // no response port so grounding all outputs begin assign fifo_input = 0; assign fifo_output = 0; assign mm_response_readdata = 0; assign mm_response_waitrequest = 0; assign src_response_data = 0; assign src_response_valid = 0; assign response_watermark = 0; assign response_fifo_full = 0; assign response_fifo_empty = 0; end endgenerate endmodule
module response_block ( clk, reset, mm_response_readdata, mm_response_read, mm_response_address, mm_response_byteenable, mm_response_waitrequest, src_response_data, src_response_valid, src_response_ready, sw_reset, response_watermark, response_fifo_full, response_fifo_empty, done_strobe, actual_bytes_transferred, error, early_termination, transfer_complete_IRQ_mask, error_IRQ_mask, early_termination_IRQ_mask, descriptor_buffer_full ); parameter RESPONSE_PORT = 0; // when disabled all the outputs will be disconnected by the component wrapper parameter FIFO_DEPTH = 256; // needs to be double the descriptor FIFO depth parameter FIFO_DEPTH_LOG2 = 8; localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51; // when 'RESPONSE_PORT' is 1 then the response port is set to streaming and must pass the interrupt masks as well input clk; input reset; output wire [31:0] mm_response_readdata; input mm_response_read; input mm_response_address; // only have 2 addresses input [3:0] mm_response_byteenable; output wire mm_response_waitrequest; output wire [255:0] src_response_data; // not going to use all these bits, the remainder will be grounded output wire src_response_valid; input src_response_ready; input sw_reset; output wire [15:0] response_watermark; output wire response_fifo_full; output wire response_fifo_empty; input done_strobe; input [31:0] actual_bytes_transferred; input [7:0] error; input early_termination; // all of these signals are only used the ST source response port since the pre-fetching master component will handle the interrupt generation as apposed to the CSR block input transfer_complete_IRQ_mask; input [7:0] error_IRQ_mask; input early_termination_IRQ_mask; input descriptor_buffer_full; // handy signal for the prefetching master to use so that it known when to blast a new descriptor into the dispatcher /* internal signals and registers */ wire [FIFO_DEPTH_LOG2-1:0] fifo_used; wire fifo_full; wire fifo_empty; wire fifo_read; wire [FIFO_WIDTH-1:0] fifo_input; wire [FIFO_WIDTH-1:0] fifo_output; generate if (RESPONSE_PORT == 0) // slave port used for response data begin assign fifo_input = {early_termination, error, actual_bytes_transferred}; assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1); // reading from the upper byte (byte offset 7) pops the fifo scfifo the_response_FIFO ( .clock (clk), .aclr (reset), .sclr (sw_reset), .data (fifo_input), .wrreq (done_strobe), .rdreq (fifo_read), .q (fifo_output), .full (fifo_full), .empty (fifo_empty), .usedw (fifo_used) ); defparam the_response_FIFO.lpm_width = FIFO_WIDTH; defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH; defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2; defparam the_response_FIFO.lpm_showahead = "ON"; defparam the_response_FIFO.use_eab = "ON"; defparam the_response_FIFO.overflow_checking = "OFF"; defparam the_response_FIFO.underflow_checking = "OFF"; defparam the_response_FIFO.add_ram_output_register = "ON"; defparam the_response_FIFO.lpm_type = "scfifo"; // either actual bytes transfered when address == 0 or {zero padding, early_termination, error[7:0]} when address = 1 assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]}; assign mm_response_waitrequest = fifo_empty; assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount assign response_fifo_full = fifo_full; assign response_fifo_empty = fifo_empty; // no streaming port so ground all of its outputs assign src_response_data = 0; assign src_response_valid = 0; end else if (RESPONSE_PORT == 1) // streaming source port used for response data (prefetcher will catch this data) begin assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred}; assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1); scfifo the_response_FIFO ( .clock (clk), .aclr (reset | sw_reset), .data (fifo_input), .wrreq (done_strobe), .rdreq (fifo_read), .q (fifo_output), .full (fifo_full), .empty (fifo_empty), .usedw (fifo_used) ); defparam the_response_FIFO.lpm_width = FIFO_WIDTH; defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH; defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2; defparam the_response_FIFO.lpm_showahead = "ON"; defparam the_response_FIFO.use_eab = "ON"; defparam the_response_FIFO.overflow_checking = "OFF"; defparam the_response_FIFO.underflow_checking = "OFF"; defparam the_response_FIFO.add_ram_output_register = "ON"; defparam the_response_FIFO.lpm_type = "scfifo"; assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output}; // zero padding the upper bits, also sending out the descriptor buffer full signal to simplify the throttling in the prefetching master (bit 52) assign src_response_valid = (fifo_empty == 0); assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount; assign response_fifo_full = fifo_full; assign response_fifo_empty = fifo_empty; // no slave port so ground all of its outputs assign mm_response_readdata = 0; assign mm_response_waitrequest = 0; end else // no response port so grounding all outputs begin assign fifo_input = 0; assign fifo_output = 0; assign mm_response_readdata = 0; assign mm_response_waitrequest = 0; assign src_response_data = 0; assign src_response_valid = 0; assign response_watermark = 0; assign response_fifo_full = 0; assign response_fifo_empty = 0; end endgenerate endmodule
module response_block ( clk, reset, mm_response_readdata, mm_response_read, mm_response_address, mm_response_byteenable, mm_response_waitrequest, src_response_data, src_response_valid, src_response_ready, sw_reset, response_watermark, response_fifo_full, response_fifo_empty, done_strobe, actual_bytes_transferred, error, early_termination, transfer_complete_IRQ_mask, error_IRQ_mask, early_termination_IRQ_mask, descriptor_buffer_full ); parameter RESPONSE_PORT = 0; // when disabled all the outputs will be disconnected by the component wrapper parameter FIFO_DEPTH = 256; // needs to be double the descriptor FIFO depth parameter FIFO_DEPTH_LOG2 = 8; localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51; // when 'RESPONSE_PORT' is 1 then the response port is set to streaming and must pass the interrupt masks as well input clk; input reset; output wire [31:0] mm_response_readdata; input mm_response_read; input mm_response_address; // only have 2 addresses input [3:0] mm_response_byteenable; output wire mm_response_waitrequest; output wire [255:0] src_response_data; // not going to use all these bits, the remainder will be grounded output wire src_response_valid; input src_response_ready; input sw_reset; output wire [15:0] response_watermark; output wire response_fifo_full; output wire response_fifo_empty; input done_strobe; input [31:0] actual_bytes_transferred; input [7:0] error; input early_termination; // all of these signals are only used the ST source response port since the pre-fetching master component will handle the interrupt generation as apposed to the CSR block input transfer_complete_IRQ_mask; input [7:0] error_IRQ_mask; input early_termination_IRQ_mask; input descriptor_buffer_full; // handy signal for the prefetching master to use so that it known when to blast a new descriptor into the dispatcher /* internal signals and registers */ wire [FIFO_DEPTH_LOG2-1:0] fifo_used; wire fifo_full; wire fifo_empty; wire fifo_read; wire [FIFO_WIDTH-1:0] fifo_input; wire [FIFO_WIDTH-1:0] fifo_output; generate if (RESPONSE_PORT == 0) // slave port used for response data begin assign fifo_input = {early_termination, error, actual_bytes_transferred}; assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1); // reading from the upper byte (byte offset 7) pops the fifo scfifo the_response_FIFO ( .clock (clk), .aclr (reset), .sclr (sw_reset), .data (fifo_input), .wrreq (done_strobe), .rdreq (fifo_read), .q (fifo_output), .full (fifo_full), .empty (fifo_empty), .usedw (fifo_used) ); defparam the_response_FIFO.lpm_width = FIFO_WIDTH; defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH; defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2; defparam the_response_FIFO.lpm_showahead = "ON"; defparam the_response_FIFO.use_eab = "ON"; defparam the_response_FIFO.overflow_checking = "OFF"; defparam the_response_FIFO.underflow_checking = "OFF"; defparam the_response_FIFO.add_ram_output_register = "ON"; defparam the_response_FIFO.lpm_type = "scfifo"; // either actual bytes transfered when address == 0 or {zero padding, early_termination, error[7:0]} when address = 1 assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]}; assign mm_response_waitrequest = fifo_empty; assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount assign response_fifo_full = fifo_full; assign response_fifo_empty = fifo_empty; // no streaming port so ground all of its outputs assign src_response_data = 0; assign src_response_valid = 0; end else if (RESPONSE_PORT == 1) // streaming source port used for response data (prefetcher will catch this data) begin assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred}; assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1); scfifo the_response_FIFO ( .clock (clk), .aclr (reset | sw_reset), .data (fifo_input), .wrreq (done_strobe), .rdreq (fifo_read), .q (fifo_output), .full (fifo_full), .empty (fifo_empty), .usedw (fifo_used) ); defparam the_response_FIFO.lpm_width = FIFO_WIDTH; defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH; defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2; defparam the_response_FIFO.lpm_showahead = "ON"; defparam the_response_FIFO.use_eab = "ON"; defparam the_response_FIFO.overflow_checking = "OFF"; defparam the_response_FIFO.underflow_checking = "OFF"; defparam the_response_FIFO.add_ram_output_register = "ON"; defparam the_response_FIFO.lpm_type = "scfifo"; assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output}; // zero padding the upper bits, also sending out the descriptor buffer full signal to simplify the throttling in the prefetching master (bit 52) assign src_response_valid = (fifo_empty == 0); assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount; assign response_fifo_full = fifo_full; assign response_fifo_empty = fifo_empty; // no slave port so ground all of its outputs assign mm_response_readdata = 0; assign mm_response_waitrequest = 0; end else // no response port so grounding all outputs begin assign fifo_input = 0; assign fifo_output = 0; assign mm_response_readdata = 0; assign mm_response_waitrequest = 0; assign src_response_data = 0; assign src_response_valid = 0; assign response_watermark = 0; assign response_fifo_full = 0; assign response_fifo_empty = 0; end endgenerate endmodule
module response_block ( clk, reset, mm_response_readdata, mm_response_read, mm_response_address, mm_response_byteenable, mm_response_waitrequest, src_response_data, src_response_valid, src_response_ready, sw_reset, response_watermark, response_fifo_full, response_fifo_empty, done_strobe, actual_bytes_transferred, error, early_termination, transfer_complete_IRQ_mask, error_IRQ_mask, early_termination_IRQ_mask, descriptor_buffer_full ); parameter RESPONSE_PORT = 0; // when disabled all the outputs will be disconnected by the component wrapper parameter FIFO_DEPTH = 256; // needs to be double the descriptor FIFO depth parameter FIFO_DEPTH_LOG2 = 8; localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51; // when 'RESPONSE_PORT' is 1 then the response port is set to streaming and must pass the interrupt masks as well input clk; input reset; output wire [31:0] mm_response_readdata; input mm_response_read; input mm_response_address; // only have 2 addresses input [3:0] mm_response_byteenable; output wire mm_response_waitrequest; output wire [255:0] src_response_data; // not going to use all these bits, the remainder will be grounded output wire src_response_valid; input src_response_ready; input sw_reset; output wire [15:0] response_watermark; output wire response_fifo_full; output wire response_fifo_empty; input done_strobe; input [31:0] actual_bytes_transferred; input [7:0] error; input early_termination; // all of these signals are only used the ST source response port since the pre-fetching master component will handle the interrupt generation as apposed to the CSR block input transfer_complete_IRQ_mask; input [7:0] error_IRQ_mask; input early_termination_IRQ_mask; input descriptor_buffer_full; // handy signal for the prefetching master to use so that it known when to blast a new descriptor into the dispatcher /* internal signals and registers */ wire [FIFO_DEPTH_LOG2-1:0] fifo_used; wire fifo_full; wire fifo_empty; wire fifo_read; wire [FIFO_WIDTH-1:0] fifo_input; wire [FIFO_WIDTH-1:0] fifo_output; generate if (RESPONSE_PORT == 0) // slave port used for response data begin assign fifo_input = {early_termination, error, actual_bytes_transferred}; assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1); // reading from the upper byte (byte offset 7) pops the fifo scfifo the_response_FIFO ( .clock (clk), .aclr (reset), .sclr (sw_reset), .data (fifo_input), .wrreq (done_strobe), .rdreq (fifo_read), .q (fifo_output), .full (fifo_full), .empty (fifo_empty), .usedw (fifo_used) ); defparam the_response_FIFO.lpm_width = FIFO_WIDTH; defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH; defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2; defparam the_response_FIFO.lpm_showahead = "ON"; defparam the_response_FIFO.use_eab = "ON"; defparam the_response_FIFO.overflow_checking = "OFF"; defparam the_response_FIFO.underflow_checking = "OFF"; defparam the_response_FIFO.add_ram_output_register = "ON"; defparam the_response_FIFO.lpm_type = "scfifo"; // either actual bytes transfered when address == 0 or {zero padding, early_termination, error[7:0]} when address = 1 assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]}; assign mm_response_waitrequest = fifo_empty; assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount assign response_fifo_full = fifo_full; assign response_fifo_empty = fifo_empty; // no streaming port so ground all of its outputs assign src_response_data = 0; assign src_response_valid = 0; end else if (RESPONSE_PORT == 1) // streaming source port used for response data (prefetcher will catch this data) begin assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred}; assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1); scfifo the_response_FIFO ( .clock (clk), .aclr (reset | sw_reset), .data (fifo_input), .wrreq (done_strobe), .rdreq (fifo_read), .q (fifo_output), .full (fifo_full), .empty (fifo_empty), .usedw (fifo_used) ); defparam the_response_FIFO.lpm_width = FIFO_WIDTH; defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH; defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2; defparam the_response_FIFO.lpm_showahead = "ON"; defparam the_response_FIFO.use_eab = "ON"; defparam the_response_FIFO.overflow_checking = "OFF"; defparam the_response_FIFO.underflow_checking = "OFF"; defparam the_response_FIFO.add_ram_output_register = "ON"; defparam the_response_FIFO.lpm_type = "scfifo"; assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output}; // zero padding the upper bits, also sending out the descriptor buffer full signal to simplify the throttling in the prefetching master (bit 52) assign src_response_valid = (fifo_empty == 0); assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount; assign response_fifo_full = fifo_full; assign response_fifo_empty = fifo_empty; // no slave port so ground all of its outputs assign mm_response_readdata = 0; assign mm_response_waitrequest = 0; end else // no response port so grounding all outputs begin assign fifo_input = 0; assign fifo_output = 0; assign mm_response_readdata = 0; assign mm_response_waitrequest = 0; assign src_response_data = 0; assign src_response_valid = 0; assign response_watermark = 0; assign response_fifo_full = 0; assign response_fifo_empty = 0; end endgenerate endmodule
module dma_pcie_bridge ( clk, reset, // DMA interface (slave) dma_address, dma_read, dma_readdata, dma_readdatavalid, dma_write, dma_writedata, dma_burstcount, dma_byteenable, dma_waitrequest, // PCIe interface (master) pcie_address, pcie_read, pcie_readdata, pcie_readdatavalid, pcie_write, pcie_writedata, pcie_burstcount, pcie_byteenable, pcie_waitrequest ); // Parameters set from the GUI parameter DMA_WIDTH = 256; parameter PCIE_WIDTH = 64; parameter DMA_BURSTCOUNT = 6; parameter PCIE_BURSTCOUNT = 10; parameter PCIE_ADDR_WIDTH = 30; // Byte-address width required parameter ADDR_OFFSET = 0; // Derived parameters localparam DMA_WIDTH_BYTES = DMA_WIDTH / 8; localparam PCIE_WIDTH_BYTES = PCIE_WIDTH / 8; localparam WIDTH_RATIO = DMA_WIDTH / PCIE_WIDTH; localparam ADDR_SHIFT = $clog2( WIDTH_RATIO ); localparam DMA_ADDR_WIDTH = PCIE_ADDR_WIDTH - $clog2( DMA_WIDTH_BYTES ); // Global ports input clk; input reset; // DMA slave ports input [DMA_ADDR_WIDTH-1:0] dma_address; input dma_read; output [DMA_WIDTH-1:0 ]dma_readdata; output dma_readdatavalid; input dma_write; input [DMA_WIDTH-1:0] dma_writedata; input [DMA_BURSTCOUNT-1:0] dma_burstcount; input [DMA_WIDTH_BYTES-1:0] dma_byteenable; output dma_waitrequest; // PCIe master ports output [31:0] pcie_address; output pcie_read; input [PCIE_WIDTH-1:0] pcie_readdata; input pcie_readdatavalid; output pcie_write; output [PCIE_WIDTH-1:0] pcie_writedata; output [PCIE_BURSTCOUNT-1:0] pcie_burstcount; output [PCIE_WIDTH_BYTES-1:0] pcie_byteenable; input pcie_waitrequest; // Address decoding into byte-address wire [31:0] dma_byte_address; assign dma_byte_address = (dma_address * DMA_WIDTH_BYTES); // Read logic - Buffer the pcie words into a full-sized dma word. The // last word gets passed through, the first few words are stored reg [DMA_WIDTH-1:0] r_buffer; // The last PCIE_WIDTH bits are not used and will be swept away reg [$clog2(WIDTH_RATIO)-1:0] r_wc; reg [DMA_WIDTH-1:0] r_demux; wire [DMA_WIDTH-1:0] r_data; wire r_full; wire r_waitrequest; // Full indicates that a full word is ready to be passed on to the DMA // as soon as the next pcie-word arrives assign r_full = &r_wc; // True when a read request is being stalled (not a function of this unit) assign r_waitrequest = pcie_waitrequest; // Groups the previously stored words with the next read data on the pcie bus assign r_data = {pcie_readdata, r_buffer[DMA_WIDTH-PCIE_WIDTH-1:0]}; // Store the first returned words in a buffer, keep track of which word // we are waiting for in the word counter (r_wc) always@(posedge clk or posedge reset) begin if(reset == 1'b1) begin r_wc <= {$clog2(DMA_WIDTH){1'b0}}; r_buffer <= {(DMA_WIDTH){1'b0}}; end else begin r_wc <= pcie_readdatavalid ? (r_wc + 1) : r_wc; if(pcie_readdatavalid) r_buffer[ r_wc*PCIE_WIDTH +: PCIE_WIDTH ] <= pcie_readdata; end end // Write logic - First word passes through, last words are registered // and passed on to the fabric in order. Master is stalled until the // full write has been completed (in PCIe word sized segments) reg [$clog2(WIDTH_RATIO)-1:0] w_wc; wire [PCIE_WIDTH_BYTES-1:0] w_byteenable; wire [PCIE_WIDTH-1:0] w_writedata; wire w_waitrequest; wire w_sent; // Indicates the successful transfer of a pcie-word to PCIe assign w_sent = pcie_write && !pcie_waitrequest; // Select the appropriate word to send downstream assign w_writedata = dma_writedata[w_wc*PCIE_WIDTH +: PCIE_WIDTH]; assign w_byteenable = dma_byteenable[w_wc*PCIE_WIDTH_BYTES +: PCIE_WIDTH_BYTES]; // True when avalon is waiting, or the full word has not been written assign w_waitrequest = (pcie_write && !(&w_wc)) || pcie_waitrequest; // Keep track of which word segment we are sending in the word counter (w_wc) always@(posedge clk or posedge reset) begin if(reset == 1'b1) w_wc <= {$clog2(DMA_WIDTH){1'b0}}; else w_wc <= w_sent ? (w_wc + 1) : w_wc; end // Shared read/write logic assign pcie_address = ADDR_OFFSET + dma_byte_address; assign pcie_read = dma_read; assign pcie_write = dma_write; assign pcie_writedata = w_writedata; assign pcie_burstcount = (dma_burstcount << ADDR_SHIFT); assign pcie_byteenable = pcie_write ? w_byteenable : dma_byteenable; assign dma_readdata = r_data; assign dma_readdatavalid = r_full && pcie_readdatavalid; assign dma_waitrequest = r_waitrequest || w_waitrequest; endmodule
module dma_pcie_bridge ( clk, reset, // DMA interface (slave) dma_address, dma_read, dma_readdata, dma_readdatavalid, dma_write, dma_writedata, dma_burstcount, dma_byteenable, dma_waitrequest, // PCIe interface (master) pcie_address, pcie_read, pcie_readdata, pcie_readdatavalid, pcie_write, pcie_writedata, pcie_burstcount, pcie_byteenable, pcie_waitrequest ); // Parameters set from the GUI parameter DMA_WIDTH = 256; parameter PCIE_WIDTH = 64; parameter DMA_BURSTCOUNT = 6; parameter PCIE_BURSTCOUNT = 10; parameter PCIE_ADDR_WIDTH = 30; // Byte-address width required parameter ADDR_OFFSET = 0; // Derived parameters localparam DMA_WIDTH_BYTES = DMA_WIDTH / 8; localparam PCIE_WIDTH_BYTES = PCIE_WIDTH / 8; localparam WIDTH_RATIO = DMA_WIDTH / PCIE_WIDTH; localparam ADDR_SHIFT = $clog2( WIDTH_RATIO ); localparam DMA_ADDR_WIDTH = PCIE_ADDR_WIDTH - $clog2( DMA_WIDTH_BYTES ); // Global ports input clk; input reset; // DMA slave ports input [DMA_ADDR_WIDTH-1:0] dma_address; input dma_read; output [DMA_WIDTH-1:0 ]dma_readdata; output dma_readdatavalid; input dma_write; input [DMA_WIDTH-1:0] dma_writedata; input [DMA_BURSTCOUNT-1:0] dma_burstcount; input [DMA_WIDTH_BYTES-1:0] dma_byteenable; output dma_waitrequest; // PCIe master ports output [31:0] pcie_address; output pcie_read; input [PCIE_WIDTH-1:0] pcie_readdata; input pcie_readdatavalid; output pcie_write; output [PCIE_WIDTH-1:0] pcie_writedata; output [PCIE_BURSTCOUNT-1:0] pcie_burstcount; output [PCIE_WIDTH_BYTES-1:0] pcie_byteenable; input pcie_waitrequest; // Address decoding into byte-address wire [31:0] dma_byte_address; assign dma_byte_address = (dma_address * DMA_WIDTH_BYTES); // Read logic - Buffer the pcie words into a full-sized dma word. The // last word gets passed through, the first few words are stored reg [DMA_WIDTH-1:0] r_buffer; // The last PCIE_WIDTH bits are not used and will be swept away reg [$clog2(WIDTH_RATIO)-1:0] r_wc; reg [DMA_WIDTH-1:0] r_demux; wire [DMA_WIDTH-1:0] r_data; wire r_full; wire r_waitrequest; // Full indicates that a full word is ready to be passed on to the DMA // as soon as the next pcie-word arrives assign r_full = &r_wc; // True when a read request is being stalled (not a function of this unit) assign r_waitrequest = pcie_waitrequest; // Groups the previously stored words with the next read data on the pcie bus assign r_data = {pcie_readdata, r_buffer[DMA_WIDTH-PCIE_WIDTH-1:0]}; // Store the first returned words in a buffer, keep track of which word // we are waiting for in the word counter (r_wc) always@(posedge clk or posedge reset) begin if(reset == 1'b1) begin r_wc <= {$clog2(DMA_WIDTH){1'b0}}; r_buffer <= {(DMA_WIDTH){1'b0}}; end else begin r_wc <= pcie_readdatavalid ? (r_wc + 1) : r_wc; if(pcie_readdatavalid) r_buffer[ r_wc*PCIE_WIDTH +: PCIE_WIDTH ] <= pcie_readdata; end end // Write logic - First word passes through, last words are registered // and passed on to the fabric in order. Master is stalled until the // full write has been completed (in PCIe word sized segments) reg [$clog2(WIDTH_RATIO)-1:0] w_wc; wire [PCIE_WIDTH_BYTES-1:0] w_byteenable; wire [PCIE_WIDTH-1:0] w_writedata; wire w_waitrequest; wire w_sent; // Indicates the successful transfer of a pcie-word to PCIe assign w_sent = pcie_write && !pcie_waitrequest; // Select the appropriate word to send downstream assign w_writedata = dma_writedata[w_wc*PCIE_WIDTH +: PCIE_WIDTH]; assign w_byteenable = dma_byteenable[w_wc*PCIE_WIDTH_BYTES +: PCIE_WIDTH_BYTES]; // True when avalon is waiting, or the full word has not been written assign w_waitrequest = (pcie_write && !(&w_wc)) || pcie_waitrequest; // Keep track of which word segment we are sending in the word counter (w_wc) always@(posedge clk or posedge reset) begin if(reset == 1'b1) w_wc <= {$clog2(DMA_WIDTH){1'b0}}; else w_wc <= w_sent ? (w_wc + 1) : w_wc; end // Shared read/write logic assign pcie_address = ADDR_OFFSET + dma_byte_address; assign pcie_read = dma_read; assign pcie_write = dma_write; assign pcie_writedata = w_writedata; assign pcie_burstcount = (dma_burstcount << ADDR_SHIFT); assign pcie_byteenable = pcie_write ? w_byteenable : dma_byteenable; assign dma_readdata = r_data; assign dma_readdatavalid = r_full && pcie_readdatavalid; assign dma_waitrequest = r_waitrequest || w_waitrequest; endmodule
module channel_ram ( // System input txclk, input reset, // USB side input [31:0] datain, input WR, input WR_done, output have_space, // Reader side output [31:0] dataout, input RD, input RD_done, output packet_waiting); reg [6:0] wr_addr, rd_addr; reg [1:0] which_ram_wr, which_ram_rd; reg [2:0] nb_packets; reg [31:0] ram0 [0:127]; reg [31:0] ram1 [0:127]; reg [31:0] ram2 [0:127]; reg [31:0] ram3 [0:127]; reg [31:0] dataout0; reg [31:0] dataout1; reg [31:0] dataout2; reg [31:0] dataout3; wire wr_done_int; wire rd_done_int; wire [6:0] rd_addr_final; wire [1:0] which_ram_rd_final; // USB side always @(posedge txclk) if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain; always @(posedge txclk) if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain; always @(posedge txclk) if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain; always @(posedge txclk) if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain; assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done); always @(posedge txclk) if(reset) wr_addr <= 0; else if (WR_done) wr_addr <= 0; else if (WR) wr_addr <= wr_addr + 7'd1; always @(posedge txclk) if(reset) which_ram_wr <= 0; else if (wr_done_int) which_ram_wr <= which_ram_wr + 2'd1; assign have_space = (nb_packets < 3'd3); // Reader side // short hand fifo // rd_addr_final is what rd_addr is going to be next clock cycle // which_ram_rd_final is what which_ram_rd is going to be next clock cycle always @(posedge txclk) dataout0 <= ram0[rd_addr_final]; always @(posedge txclk) dataout1 <= ram1[rd_addr_final]; always @(posedge txclk) dataout2 <= ram2[rd_addr_final]; always @(posedge txclk) dataout3 <= ram3[rd_addr_final]; assign dataout = (which_ram_rd_final[1]) ? (which_ram_rd_final[0] ? dataout3 : dataout2) : (which_ram_rd_final[0] ? dataout1 : dataout0); //RD_done is the only way to signal the end of one packet assign rd_done_int = RD_done; always @(posedge txclk) if (reset) rd_addr <= 0; else if (RD_done) rd_addr <= 0; else if (RD) rd_addr <= rd_addr + 7'd1; assign rd_addr_final = (reset|RD_done) ? (6'd0) : ((RD)?(rd_addr+7'd1):rd_addr); always @(posedge txclk) if (reset) which_ram_rd <= 0; else if (rd_done_int) which_ram_rd <= which_ram_rd + 2'd1; assign which_ram_rd_final = (reset) ? (2'd0): ((rd_done_int) ? (which_ram_rd + 2'd1) : which_ram_rd); //packet_waiting is set to zero if rd_done_int is high //because there is no guarantee that nb_packets will be pos. assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int)); always @(posedge txclk) if (reset) nb_packets <= 0; else if (wr_done_int & ~rd_done_int) nb_packets <= nb_packets + 3'd1; else if (rd_done_int & ~wr_done_int) nb_packets <= nb_packets - 3'd1; endmodule
module channel_ram ( // System input txclk, input reset, // USB side input [31:0] datain, input WR, input WR_done, output have_space, // Reader side output [31:0] dataout, input RD, input RD_done, output packet_waiting); reg [6:0] wr_addr, rd_addr; reg [1:0] which_ram_wr, which_ram_rd; reg [2:0] nb_packets; reg [31:0] ram0 [0:127]; reg [31:0] ram1 [0:127]; reg [31:0] ram2 [0:127]; reg [31:0] ram3 [0:127]; reg [31:0] dataout0; reg [31:0] dataout1; reg [31:0] dataout2; reg [31:0] dataout3; wire wr_done_int; wire rd_done_int; wire [6:0] rd_addr_final; wire [1:0] which_ram_rd_final; // USB side always @(posedge txclk) if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain; always @(posedge txclk) if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain; always @(posedge txclk) if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain; always @(posedge txclk) if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain; assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done); always @(posedge txclk) if(reset) wr_addr <= 0; else if (WR_done) wr_addr <= 0; else if (WR) wr_addr <= wr_addr + 7'd1; always @(posedge txclk) if(reset) which_ram_wr <= 0; else if (wr_done_int) which_ram_wr <= which_ram_wr + 2'd1; assign have_space = (nb_packets < 3'd3); // Reader side // short hand fifo // rd_addr_final is what rd_addr is going to be next clock cycle // which_ram_rd_final is what which_ram_rd is going to be next clock cycle always @(posedge txclk) dataout0 <= ram0[rd_addr_final]; always @(posedge txclk) dataout1 <= ram1[rd_addr_final]; always @(posedge txclk) dataout2 <= ram2[rd_addr_final]; always @(posedge txclk) dataout3 <= ram3[rd_addr_final]; assign dataout = (which_ram_rd_final[1]) ? (which_ram_rd_final[0] ? dataout3 : dataout2) : (which_ram_rd_final[0] ? dataout1 : dataout0); //RD_done is the only way to signal the end of one packet assign rd_done_int = RD_done; always @(posedge txclk) if (reset) rd_addr <= 0; else if (RD_done) rd_addr <= 0; else if (RD) rd_addr <= rd_addr + 7'd1; assign rd_addr_final = (reset|RD_done) ? (6'd0) : ((RD)?(rd_addr+7'd1):rd_addr); always @(posedge txclk) if (reset) which_ram_rd <= 0; else if (rd_done_int) which_ram_rd <= which_ram_rd + 2'd1; assign which_ram_rd_final = (reset) ? (2'd0): ((rd_done_int) ? (which_ram_rd + 2'd1) : which_ram_rd); //packet_waiting is set to zero if rd_done_int is high //because there is no guarantee that nb_packets will be pos. assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int)); always @(posedge txclk) if (reset) nb_packets <= 0; else if (wr_done_int & ~rd_done_int) nb_packets <= nb_packets + 3'd1; else if (rd_done_int & ~wr_done_int) nb_packets <= nb_packets - 3'd1; endmodule
module generic_baseblocks_v2_1_0_mux_enc # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_RATIO = 4, // Mux select ratio. Can be any binary value (>= 1) parameter integer C_SEL_WIDTH = 2, // Log2-ceiling of C_RATIO (>= 1) parameter integer C_DATA_WIDTH = 1 // Data width for generic_baseblocks_v2_1_0_comparator (>= 1) ) ( input wire [C_SEL_WIDTH-1:0] S, input wire [C_RATIO*C_DATA_WIDTH-1:0] A, output wire [C_DATA_WIDTH-1:0] O, input wire OE ); wire [C_DATA_WIDTH-1:0] o_i; genvar bit_cnt; function [C_DATA_WIDTH-1:0] f_mux ( input [C_SEL_WIDTH-1:0] s, input [C_RATIO*C_DATA_WIDTH-1:0] a ); integer i; reg [C_RATIO*C_DATA_WIDTH-1:0] carry; begin carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0]; for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] = carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] | ({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]); end f_mux = carry[C_DATA_WIDTH*C_RATIO-1:C_DATA_WIDTH*(C_RATIO-1)]; end endfunction function [C_DATA_WIDTH-1:0] f_mux4 ( input [1:0] s, input [4*C_DATA_WIDTH-1:0] a ); integer i; reg [4*C_DATA_WIDTH-1:0] carry; begin carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0]; for (i=1;i<4;i=i+1) begin : gen_carrychain_enc carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] = carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] | ({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]); end f_mux4 = carry[C_DATA_WIDTH*4-1:C_DATA_WIDTH*3]; end endfunction assign O = o_i & {C_DATA_WIDTH{OE}}; // OE is gated AFTER any MUXF7/8 (can only optimize forward into downstream logic) generate if ( C_RATIO < 2 ) begin : gen_bypass assign o_i = A; end else if ( C_FAMILY == "rtl" || C_RATIO < 5 ) begin : gen_rtl assign o_i = f_mux(S, A); end else begin : gen_fpga wire [C_DATA_WIDTH-1:0] l; wire [C_DATA_WIDTH-1:0] h; wire [C_DATA_WIDTH-1:0] ll; wire [C_DATA_WIDTH-1:0] lh; wire [C_DATA_WIDTH-1:0] hl; wire [C_DATA_WIDTH-1:0] hh; case (C_RATIO) 1, 5, 9, 13: assign hh = A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH]; 2, 6, 10, 14: assign hh = S[0] ? A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] : A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ; 3, 7, 11, 15: assign hh = S[1] ? A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] : (S[0] ? A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] : A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] ); 4, 8, 12, 16: assign hh = S[1] ? (S[0] ? A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] : A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ) : (S[0] ? A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] : A[(C_RATIO-4)*C_DATA_WIDTH +: C_DATA_WIDTH] ); 17: assign hh = S[1] ? (S[0] ? A[15*C_DATA_WIDTH +: C_DATA_WIDTH] : A[14*C_DATA_WIDTH +: C_DATA_WIDTH] ) : (S[0] ? A[13*C_DATA_WIDTH +: C_DATA_WIDTH] : A[12*C_DATA_WIDTH +: C_DATA_WIDTH] ); default: assign hh = 0; endcase case (C_RATIO) 5, 6, 7, 8: begin assign l = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_5_8 MUXF7 mux_s2_inst ( .I0 (l[bit_cnt]), .I1 (hh[bit_cnt]), .S (S[2]), .O (o_i[bit_cnt]) ); end end 9, 10, 11, 12: begin assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]); for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_9_12 MUXF7 muxf_s2_low_inst ( .I0 (ll[bit_cnt]), .I1 (lh[bit_cnt]), .S (S[2]), .O (l[bit_cnt]) ); MUXF8 muxf_s3_inst ( .I0 (l[bit_cnt]), .I1 (hh[bit_cnt]), .S (S[3]), .O (o_i[bit_cnt]) ); end end 13,14,15,16: begin assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]); assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]); for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_13_16 MUXF7 muxf_s2_low_inst ( .I0 (ll[bit_cnt]), .I1 (lh[bit_cnt]), .S (S[2]), .O (l[bit_cnt]) ); MUXF7 muxf_s2_hi_inst ( .I0 (hl[bit_cnt]), .I1 (hh[bit_cnt]), .S (S[2]), .O (h[bit_cnt]) ); MUXF8 muxf_s3_inst ( .I0 (l[bit_cnt]), .I1 (h[bit_cnt]), .S (S[3]), .O (o_i[bit_cnt]) ); end end 17: begin assign ll = S[4] ? A[16*C_DATA_WIDTH +: C_DATA_WIDTH] : f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); // 5-input mux assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]); assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]); for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_17 MUXF7 muxf_s2_low_inst ( .I0 (ll[bit_cnt]), .I1 (lh[bit_cnt]), .S (S[2]), .O (l[bit_cnt]) ); MUXF7 muxf_s2_hi_inst ( .I0 (hl[bit_cnt]), .I1 (hh[bit_cnt]), .S (S[2]), .O (h[bit_cnt]) ); MUXF8 muxf_s3_inst ( .I0 (l[bit_cnt]), .I1 (h[bit_cnt]), .S (S[3]), .O (o_i[bit_cnt]) ); end end default: // If RATIO > 17, use RTL assign o_i = f_mux(S, A); endcase end // gen_fpga endgenerate endmodule
module generic_baseblocks_v2_1_0_mux_enc # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6 or spartan6. parameter integer C_RATIO = 4, // Mux select ratio. Can be any binary value (>= 1) parameter integer C_SEL_WIDTH = 2, // Log2-ceiling of C_RATIO (>= 1) parameter integer C_DATA_WIDTH = 1 // Data width for generic_baseblocks_v2_1_0_comparator (>= 1) ) ( input wire [C_SEL_WIDTH-1:0] S, input wire [C_RATIO*C_DATA_WIDTH-1:0] A, output wire [C_DATA_WIDTH-1:0] O, input wire OE ); wire [C_DATA_WIDTH-1:0] o_i; genvar bit_cnt; function [C_DATA_WIDTH-1:0] f_mux ( input [C_SEL_WIDTH-1:0] s, input [C_RATIO*C_DATA_WIDTH-1:0] a ); integer i; reg [C_RATIO*C_DATA_WIDTH-1:0] carry; begin carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0]; for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] = carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] | ({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]); end f_mux = carry[C_DATA_WIDTH*C_RATIO-1:C_DATA_WIDTH*(C_RATIO-1)]; end endfunction function [C_DATA_WIDTH-1:0] f_mux4 ( input [1:0] s, input [4*C_DATA_WIDTH-1:0] a ); integer i; reg [4*C_DATA_WIDTH-1:0] carry; begin carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0]; for (i=1;i<4;i=i+1) begin : gen_carrychain_enc carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] = carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] | ({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]); end f_mux4 = carry[C_DATA_WIDTH*4-1:C_DATA_WIDTH*3]; end endfunction assign O = o_i & {C_DATA_WIDTH{OE}}; // OE is gated AFTER any MUXF7/8 (can only optimize forward into downstream logic) generate if ( C_RATIO < 2 ) begin : gen_bypass assign o_i = A; end else if ( C_FAMILY == "rtl" || C_RATIO < 5 ) begin : gen_rtl assign o_i = f_mux(S, A); end else begin : gen_fpga wire [C_DATA_WIDTH-1:0] l; wire [C_DATA_WIDTH-1:0] h; wire [C_DATA_WIDTH-1:0] ll; wire [C_DATA_WIDTH-1:0] lh; wire [C_DATA_WIDTH-1:0] hl; wire [C_DATA_WIDTH-1:0] hh; case (C_RATIO) 1, 5, 9, 13: assign hh = A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH]; 2, 6, 10, 14: assign hh = S[0] ? A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] : A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ; 3, 7, 11, 15: assign hh = S[1] ? A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] : (S[0] ? A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] : A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] ); 4, 8, 12, 16: assign hh = S[1] ? (S[0] ? A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] : A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ) : (S[0] ? A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] : A[(C_RATIO-4)*C_DATA_WIDTH +: C_DATA_WIDTH] ); 17: assign hh = S[1] ? (S[0] ? A[15*C_DATA_WIDTH +: C_DATA_WIDTH] : A[14*C_DATA_WIDTH +: C_DATA_WIDTH] ) : (S[0] ? A[13*C_DATA_WIDTH +: C_DATA_WIDTH] : A[12*C_DATA_WIDTH +: C_DATA_WIDTH] ); default: assign hh = 0; endcase case (C_RATIO) 5, 6, 7, 8: begin assign l = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_5_8 MUXF7 mux_s2_inst ( .I0 (l[bit_cnt]), .I1 (hh[bit_cnt]), .S (S[2]), .O (o_i[bit_cnt]) ); end end 9, 10, 11, 12: begin assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]); for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_9_12 MUXF7 muxf_s2_low_inst ( .I0 (ll[bit_cnt]), .I1 (lh[bit_cnt]), .S (S[2]), .O (l[bit_cnt]) ); MUXF8 muxf_s3_inst ( .I0 (l[bit_cnt]), .I1 (hh[bit_cnt]), .S (S[3]), .O (o_i[bit_cnt]) ); end end 13,14,15,16: begin assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]); assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]); for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_13_16 MUXF7 muxf_s2_low_inst ( .I0 (ll[bit_cnt]), .I1 (lh[bit_cnt]), .S (S[2]), .O (l[bit_cnt]) ); MUXF7 muxf_s2_hi_inst ( .I0 (hl[bit_cnt]), .I1 (hh[bit_cnt]), .S (S[2]), .O (h[bit_cnt]) ); MUXF8 muxf_s3_inst ( .I0 (l[bit_cnt]), .I1 (h[bit_cnt]), .S (S[3]), .O (o_i[bit_cnt]) ); end end 17: begin assign ll = S[4] ? A[16*C_DATA_WIDTH +: C_DATA_WIDTH] : f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); // 5-input mux assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]); assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]); for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_17 MUXF7 muxf_s2_low_inst ( .I0 (ll[bit_cnt]), .I1 (lh[bit_cnt]), .S (S[2]), .O (l[bit_cnt]) ); MUXF7 muxf_s2_hi_inst ( .I0 (hl[bit_cnt]), .I1 (hh[bit_cnt]), .S (S[2]), .O (h[bit_cnt]) ); MUXF8 muxf_s3_inst ( .I0 (l[bit_cnt]), .I1 (h[bit_cnt]), .S (S[3]), .O (o_i[bit_cnt]) ); end end default: // If RATIO > 17, use RTL assign o_i = f_mux(S, A); endcase end // gen_fpga endgenerate endmodule
module temp_sense_alttemp_sense_v8t ( ce, clk, clr, tsdcaldone, tsdcalo) /* synthesis synthesis_clearbox=2 */; input ce; input clk; input clr; output tsdcaldone; output [7:0] tsdcalo; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri1 ce; tri0 clr; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif wire wire_sd1_tsdcaldone; wire [7:0] wire_sd1_tsdcalo; stratixv_tsdblock sd1 ( .ce(ce), .clk(clk), .clr(clr), .tsdcaldone(wire_sd1_tsdcaldone), .tsdcalo(wire_sd1_tsdcalo)); defparam sd1.clock_divider_enable = "true", sd1.clock_divider_value = 80, sd1.sim_tsdcalo = 0, sd1.lpm_type = "stratixv_tsdblock"; assign tsdcaldone = wire_sd1_tsdcaldone, tsdcalo = wire_sd1_tsdcalo; endmodule
module temp_sense ( ce, clk, clr, tsdcaldone, tsdcalo)/* synthesis synthesis_clearbox = 2 */; input ce; input clk; input clr; output tsdcaldone; output [7:0] tsdcalo; wire [7:0] sub_wire0; wire sub_wire1; wire [7:0] tsdcalo = sub_wire0[7:0]; wire tsdcaldone = sub_wire1; temp_sense_alttemp_sense_v8t temp_sense_alttemp_sense_v8t_component ( .ce (ce), .clk (clk), .clr (clr), .tsdcalo (sub_wire0), .tsdcaldone (sub_wire1))/* synthesis synthesis_clearbox=2 clearbox_macroname = ALTTEMP_SENSE clearbox_defparam = "clk_frequency=50.0;clock_divider_enable=ON;clock_divider_value=80;intended_device_family=Stratix V;lpm_hint=UNUSED;lpm_type=alttemp_sense;number_of_samples=128;poi_cal_temperature=85;sim_tsdcalo=0;user_offset_enable=off;use_wys=on;" */; endmodule
module usb_packet_fifo ( input reset, input clock_in, input clock_out, input [15:0]ram_data_in, input write_enable, output reg [15:0]ram_data_out, output reg pkt_waiting, output reg have_space, input read_enable, input skip_packet ) ; /* Some parameters for usage later on */ parameter DATA_WIDTH = 16 ; parameter NUM_PACKETS = 4 ; /* Create the RAM here */ reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ; /* Create the address signals */ reg [7-2+NUM_PACKETS:0] usb_ram_ain ; reg [7:0] usb_ram_offset ; reg [1:0] usb_ram_packet ; wire [7-2+NUM_PACKETS:0] usb_ram_aout ; reg isfull; assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ; // Check if there is one full packet to process always @(usb_ram_ain, usb_ram_aout) begin if (reset) pkt_waiting <= 0; else if (usb_ram_ain == usb_ram_aout) pkt_waiting <= isfull; else if (usb_ram_ain > usb_ram_aout) pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= 256; else pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256; end // Check if there is room always @(usb_ram_ain, usb_ram_aout) begin if (reset) have_space <= 1; else if (usb_ram_ain == usb_ram_aout) have_space <= ~isfull; else if (usb_ram_ain > usb_ram_aout) have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1); else have_space <= (usb_ram_aout - usb_ram_ain) >= 256; end /* RAM Write Address process */ always @(posedge clock_in) begin if( reset ) usb_ram_ain <= 0 ; else if( write_enable ) begin usb_ram_ain <= usb_ram_ain + 1 ; if (usb_ram_ain + 1 == usb_ram_aout) isfull <= 1; end end /* RAM Writing process */ always @(posedge clock_in) begin if( write_enable ) begin usb_ram[usb_ram_ain] <= ram_data_in ; end end /* RAM Read Address process */ always @(posedge clock_out) begin if( reset ) begin usb_ram_packet <= 0 ; usb_ram_offset <= 0 ; isfull <= 0; end else if( skip_packet ) begin usb_ram_packet <= usb_ram_packet + 1 ; usb_ram_offset <= 0 ; end else if(read_enable) if( usb_ram_offset == 8'b11111111 ) begin usb_ram_offset <= 0 ; usb_ram_packet <= usb_ram_packet + 1 ; end else usb_ram_offset <= usb_ram_offset + 1 ; if (usb_ram_ain == usb_ram_aout) isfull <= 0; end /* RAM Reading Process */ always @(posedge clock_out) begin ram_data_out <= usb_ram[usb_ram_aout] ; end endmodule
module usb_packet_fifo ( input reset, input clock_in, input clock_out, input [15:0]ram_data_in, input write_enable, output reg [15:0]ram_data_out, output reg pkt_waiting, output reg have_space, input read_enable, input skip_packet ) ; /* Some parameters for usage later on */ parameter DATA_WIDTH = 16 ; parameter NUM_PACKETS = 4 ; /* Create the RAM here */ reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ; /* Create the address signals */ reg [7-2+NUM_PACKETS:0] usb_ram_ain ; reg [7:0] usb_ram_offset ; reg [1:0] usb_ram_packet ; wire [7-2+NUM_PACKETS:0] usb_ram_aout ; reg isfull; assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ; // Check if there is one full packet to process always @(usb_ram_ain, usb_ram_aout) begin if (reset) pkt_waiting <= 0; else if (usb_ram_ain == usb_ram_aout) pkt_waiting <= isfull; else if (usb_ram_ain > usb_ram_aout) pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= 256; else pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256; end // Check if there is room always @(usb_ram_ain, usb_ram_aout) begin if (reset) have_space <= 1; else if (usb_ram_ain == usb_ram_aout) have_space <= ~isfull; else if (usb_ram_ain > usb_ram_aout) have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1); else have_space <= (usb_ram_aout - usb_ram_ain) >= 256; end /* RAM Write Address process */ always @(posedge clock_in) begin if( reset ) usb_ram_ain <= 0 ; else if( write_enable ) begin usb_ram_ain <= usb_ram_ain + 1 ; if (usb_ram_ain + 1 == usb_ram_aout) isfull <= 1; end end /* RAM Writing process */ always @(posedge clock_in) begin if( write_enable ) begin usb_ram[usb_ram_ain] <= ram_data_in ; end end /* RAM Read Address process */ always @(posedge clock_out) begin if( reset ) begin usb_ram_packet <= 0 ; usb_ram_offset <= 0 ; isfull <= 0; end else if( skip_packet ) begin usb_ram_packet <= usb_ram_packet + 1 ; usb_ram_offset <= 0 ; end else if(read_enable) if( usb_ram_offset == 8'b11111111 ) begin usb_ram_offset <= 0 ; usb_ram_packet <= usb_ram_packet + 1 ; end else usb_ram_offset <= usb_ram_offset + 1 ; if (usb_ram_ain == usb_ram_aout) isfull <= 0; end /* RAM Reading Process */ always @(posedge clock_out) begin ram_data_out <= usb_ram[usb_ram_aout] ; end endmodule
module write_signal_breakout ( write_command_data_in, // descriptor from the write FIFO write_command_data_out, // reformated descriptor to the write master // breakout of command information write_address, write_length, write_park, write_end_on_eop, write_transfer_complete_IRQ_mask, write_early_termination_IRQ_mask, write_error_IRQ_mask, write_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground write_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground write_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground // additional control information that needs to go out asynchronously with the command data write_stop, write_sw_reset ); parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits input [DATA_WIDTH-1:0] write_command_data_in; output wire [255:0] write_command_data_out; output wire [63:0] write_address; output wire [31:0] write_length; output wire write_park; output wire write_end_on_eop; output wire write_transfer_complete_IRQ_mask; output wire write_early_termination_IRQ_mask; output wire [7:0] write_error_IRQ_mask; output wire [7:0] write_burst_count; output wire [15:0] write_stride; output wire [15:0] write_sequence_number; input write_stop; input write_sw_reset; assign write_address[31:0] = write_command_data_in[63:32]; assign write_length = write_command_data_in[95:64]; generate if (DATA_WIDTH == 256) begin assign write_park = write_command_data_in[235]; assign write_end_on_eop = write_command_data_in[236]; assign write_transfer_complete_IRQ_mask = write_command_data_in[238]; assign write_early_termination_IRQ_mask = write_command_data_in[239]; assign write_error_IRQ_mask = write_command_data_in[247:240]; assign write_burst_count = write_command_data_in[127:120]; assign write_stride = write_command_data_in[159:144]; assign write_sequence_number = write_command_data_in[111:96]; assign write_address[63:32] = write_command_data_in[223:192]; end else begin assign write_park = write_command_data_in[107]; assign write_end_on_eop = write_command_data_in[108]; assign write_transfer_complete_IRQ_mask = write_command_data_in[110]; assign write_early_termination_IRQ_mask = write_command_data_in[111]; assign write_error_IRQ_mask = write_command_data_in[119:112]; assign write_burst_count = 8'h00; assign write_stride = 16'h0000; assign write_sequence_number = 16'h0000; assign write_address[63:32] = 32'h00000000; end endgenerate // big concat statement to glue all the signals back together to go out to the write master (MSBs to LSBs) assign write_command_data_out = {{132{1'b0}}, // zero pad the upper 132 bits write_address[63:32], write_stride, write_burst_count, write_sw_reset, write_stop, 1'b0, // used to be the early termination bit so now it's reserved write_end_on_eop, write_length, write_address[31:0]}; endmodule
module write_signal_breakout ( write_command_data_in, // descriptor from the write FIFO write_command_data_out, // reformated descriptor to the write master // breakout of command information write_address, write_length, write_park, write_end_on_eop, write_transfer_complete_IRQ_mask, write_early_termination_IRQ_mask, write_error_IRQ_mask, write_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground write_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground write_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground // additional control information that needs to go out asynchronously with the command data write_stop, write_sw_reset ); parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits input [DATA_WIDTH-1:0] write_command_data_in; output wire [255:0] write_command_data_out; output wire [63:0] write_address; output wire [31:0] write_length; output wire write_park; output wire write_end_on_eop; output wire write_transfer_complete_IRQ_mask; output wire write_early_termination_IRQ_mask; output wire [7:0] write_error_IRQ_mask; output wire [7:0] write_burst_count; output wire [15:0] write_stride; output wire [15:0] write_sequence_number; input write_stop; input write_sw_reset; assign write_address[31:0] = write_command_data_in[63:32]; assign write_length = write_command_data_in[95:64]; generate if (DATA_WIDTH == 256) begin assign write_park = write_command_data_in[235]; assign write_end_on_eop = write_command_data_in[236]; assign write_transfer_complete_IRQ_mask = write_command_data_in[238]; assign write_early_termination_IRQ_mask = write_command_data_in[239]; assign write_error_IRQ_mask = write_command_data_in[247:240]; assign write_burst_count = write_command_data_in[127:120]; assign write_stride = write_command_data_in[159:144]; assign write_sequence_number = write_command_data_in[111:96]; assign write_address[63:32] = write_command_data_in[223:192]; end else begin assign write_park = write_command_data_in[107]; assign write_end_on_eop = write_command_data_in[108]; assign write_transfer_complete_IRQ_mask = write_command_data_in[110]; assign write_early_termination_IRQ_mask = write_command_data_in[111]; assign write_error_IRQ_mask = write_command_data_in[119:112]; assign write_burst_count = 8'h00; assign write_stride = 16'h0000; assign write_sequence_number = 16'h0000; assign write_address[63:32] = 32'h00000000; end endgenerate // big concat statement to glue all the signals back together to go out to the write master (MSBs to LSBs) assign write_command_data_out = {{132{1'b0}}, // zero pad the upper 132 bits write_address[63:32], write_stride, write_burst_count, write_sw_reset, write_stop, 1'b0, // used to be the early termination bit so now it's reserved write_end_on_eop, write_length, write_address[31:0]}; endmodule
module write_signal_breakout ( write_command_data_in, // descriptor from the write FIFO write_command_data_out, // reformated descriptor to the write master // breakout of command information write_address, write_length, write_park, write_end_on_eop, write_transfer_complete_IRQ_mask, write_early_termination_IRQ_mask, write_error_IRQ_mask, write_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground write_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground write_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground // additional control information that needs to go out asynchronously with the command data write_stop, write_sw_reset ); parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits input [DATA_WIDTH-1:0] write_command_data_in; output wire [255:0] write_command_data_out; output wire [63:0] write_address; output wire [31:0] write_length; output wire write_park; output wire write_end_on_eop; output wire write_transfer_complete_IRQ_mask; output wire write_early_termination_IRQ_mask; output wire [7:0] write_error_IRQ_mask; output wire [7:0] write_burst_count; output wire [15:0] write_stride; output wire [15:0] write_sequence_number; input write_stop; input write_sw_reset; assign write_address[31:0] = write_command_data_in[63:32]; assign write_length = write_command_data_in[95:64]; generate if (DATA_WIDTH == 256) begin assign write_park = write_command_data_in[235]; assign write_end_on_eop = write_command_data_in[236]; assign write_transfer_complete_IRQ_mask = write_command_data_in[238]; assign write_early_termination_IRQ_mask = write_command_data_in[239]; assign write_error_IRQ_mask = write_command_data_in[247:240]; assign write_burst_count = write_command_data_in[127:120]; assign write_stride = write_command_data_in[159:144]; assign write_sequence_number = write_command_data_in[111:96]; assign write_address[63:32] = write_command_data_in[223:192]; end else begin assign write_park = write_command_data_in[107]; assign write_end_on_eop = write_command_data_in[108]; assign write_transfer_complete_IRQ_mask = write_command_data_in[110]; assign write_early_termination_IRQ_mask = write_command_data_in[111]; assign write_error_IRQ_mask = write_command_data_in[119:112]; assign write_burst_count = 8'h00; assign write_stride = 16'h0000; assign write_sequence_number = 16'h0000; assign write_address[63:32] = 32'h00000000; end endgenerate // big concat statement to glue all the signals back together to go out to the write master (MSBs to LSBs) assign write_command_data_out = {{132{1'b0}}, // zero pad the upper 132 bits write_address[63:32], write_stride, write_burst_count, write_sw_reset, write_stop, 1'b0, // used to be the early termination bit so now it's reserved write_end_on_eop, write_length, write_address[31:0]}; endmodule
module unpipeline # ( parameter WIDTH_D = 256, parameter S_WIDTH_A = 26, parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8), parameter BURSTCOUNT_WIDTH = 1, parameter BYTEENABLE_WIDTH = WIDTH_D, parameter MAX_PENDING_READS = 64 ) ( input clk, input resetn, // Slave port input [S_WIDTH_A-1:0] slave_address, // Word address input [WIDTH_D-1:0] slave_writedata, input slave_read, input slave_write, input [BURSTCOUNT_WIDTH-1:0] slave_burstcount, input [BYTEENABLE_WIDTH-1:0] slave_byteenable, output slave_waitrequest, output [WIDTH_D-1:0] slave_readdata, output slave_readdatavalid, output [M_WIDTH_A-1:0] master_address, // Byte address output [WIDTH_D-1:0] master_writedata, output master_read, output master_write, output [BYTEENABLE_WIDTH-1:0] master_byteenable, input master_waitrequest, input [WIDTH_D-1:0] master_readdata ); assign master_read = slave_read; assign master_write = slave_write; assign master_writedata = slave_writedata; assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr assign master_byteenable = slave_byteenable; assign slave_waitrequest = master_waitrequest; assign slave_readdatavalid = slave_read & ~master_waitrequest; assign slave_readdata = master_readdata; endmodule
module unpipeline # ( parameter WIDTH_D = 256, parameter S_WIDTH_A = 26, parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8), parameter BURSTCOUNT_WIDTH = 1, parameter BYTEENABLE_WIDTH = WIDTH_D, parameter MAX_PENDING_READS = 64 ) ( input clk, input resetn, // Slave port input [S_WIDTH_A-1:0] slave_address, // Word address input [WIDTH_D-1:0] slave_writedata, input slave_read, input slave_write, input [BURSTCOUNT_WIDTH-1:0] slave_burstcount, input [BYTEENABLE_WIDTH-1:0] slave_byteenable, output slave_waitrequest, output [WIDTH_D-1:0] slave_readdata, output slave_readdatavalid, output [M_WIDTH_A-1:0] master_address, // Byte address output [WIDTH_D-1:0] master_writedata, output master_read, output master_write, output [BYTEENABLE_WIDTH-1:0] master_byteenable, input master_waitrequest, input [WIDTH_D-1:0] master_readdata ); assign master_read = slave_read; assign master_write = slave_write; assign master_writedata = slave_writedata; assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr assign master_byteenable = slave_byteenable; assign slave_waitrequest = master_waitrequest; assign slave_readdatavalid = slave_read & ~master_waitrequest; assign slave_readdata = master_readdata; endmodule
module csr_block ( clk, reset, csr_writedata, csr_write, csr_byteenable, csr_readdata, csr_read, csr_address, csr_irq, done_strobe, busy, descriptor_buffer_empty, descriptor_buffer_full, stop_state, stopped_on_error, stopped_on_early_termination, reset_stalled, stop, sw_reset, stop_on_error, stop_on_early_termination, stop_descriptors, sequence_number, descriptor_watermark, response_watermark, response_buffer_empty, response_buffer_full, transfer_complete_IRQ_mask, error_IRQ_mask, early_termination_IRQ_mask, error, early_termination ); parameter ADDRESS_WIDTH = 3; localparam CONTROL_REGISTER_ADDRESS = 3'b001; input clk; input reset; input [31:0] csr_writedata; input csr_write; input [3:0] csr_byteenable; output wire [31:0] csr_readdata; input csr_read; input [ADDRESS_WIDTH-1:0] csr_address; output wire csr_irq; input done_strobe; input busy; input descriptor_buffer_empty; input descriptor_buffer_full; input stop_state; // when the DMA runs into some error condition and you have enabled the stop on error (or when the stop control bit is written to) input reset_stalled; // the read or write master could be in the middle of a transfer/burst so it might take a while to flush the buffers output wire stop; output reg stopped_on_error; output reg stopped_on_early_termination; output reg sw_reset; output wire stop_on_error; output wire stop_on_early_termination; output wire stop_descriptors; input [31:0] sequence_number; input [31:0] descriptor_watermark; input [15:0] response_watermark; input response_buffer_empty; input response_buffer_full; input transfer_complete_IRQ_mask; input [7:0] error_IRQ_mask; input early_termination_IRQ_mask; input [7:0] error; input early_termination; /* Internal wires and registers */ wire [31:0] status; reg [31:0] control; reg [31:0] readdata; reg [31:0] readdata_d1; reg irq; // writing to the status register clears the irq bit wire set_irq; wire clear_irq; reg [15:0] irq_count; // writing to bit 0 clears the counter wire clear_irq_count; wire incr_irq_count; wire set_stopped_on_error; wire set_stopped_on_early_termination; wire set_stop; wire clear_stop; wire global_interrupt_enable; wire sw_reset_strobe; // this strobe will be one cycle earlier than sw_reset wire set_sw_reset; wire clear_sw_reset; /********************************************** Registers ***************************************************/ // read latency is 1 cycle always @ (posedge clk or posedge reset) begin if (reset) begin readdata_d1 <= 0; end else if (csr_read == 1) begin readdata_d1 <= readdata; end end always @ (posedge clk or posedge reset) begin if (reset) begin control[31:1] <= 0; end else begin if (sw_reset_strobe == 1) // reset strobe is a strobe due to this sync reset begin control[31:1] <= 0; end else begin if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1)) begin control[7:1] <= csr_writedata[7:1]; // stop bit will be handled seperately since it can be set by the csr slave port access or the SGDMA hitting an error condition end if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[1] == 1)) begin control[15:8] <= csr_writedata[15:8]; end if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[2] == 1)) begin control[23:16] <= csr_writedata[23:16]; end if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[3] == 1)) begin control[31:24] <= csr_writedata[31:24]; end end end end // control bit 0 (stop) is set by different sources so handling it seperately always @ (posedge clk or posedge reset) begin if (reset) begin control[0] <= 0; end else begin if (sw_reset_strobe == 1) begin control[0] <= 0; end else begin case ({set_stop, clear_stop}) 2'b00: control[0] <= control[0]; 2'b01: control[0] <= 1'b0; 2'b10: control[0] <= 1'b1; 2'b11: control[0] <= 1'b1; // setting will win, this case happens control[0] is being set to 0 (resume) at the same time an error/early termination stop condition occurs endcase end end end always @ (posedge clk or posedge reset) begin if (reset) begin sw_reset <= 0; end else begin if (set_sw_reset == 1) begin sw_reset <= 1; end else if (clear_sw_reset == 1) begin sw_reset <= 0; end end end always @ (posedge clk or posedge reset) begin if (reset) begin stopped_on_error <= 0; end else begin case ({set_stopped_on_error, clear_stop}) 2'b00: stopped_on_error <= stopped_on_error; 2'b01: stopped_on_error <= 1'b0; 2'b10: stopped_on_error <= 1'b1; 2'b11: stopped_on_error <= 1'b0; endcase end end always @ (posedge clk or posedge reset) begin if (reset) begin stopped_on_early_termination <= 0; end else begin case ({set_stopped_on_early_termination, clear_stop}) 2'b00: stopped_on_early_termination <= stopped_on_early_termination; 2'b01: stopped_on_early_termination <= 1'b0; 2'b10: stopped_on_early_termination <= 1'b1; 2'b11: stopped_on_early_termination <= 1'b0; endcase end end always @ (posedge clk or posedge reset) begin if (reset) begin irq <= 0; end else begin if (sw_reset_strobe == 1) begin irq <= 0; end else begin case ({clear_irq, set_irq}) 2'b00: irq <= irq; 2'b01: irq <= 1'b1; 2'b10: irq <= 1'b0; 2'b11: irq <= 1'b1; // setting will win over a clear endcase end end end always @ (posedge clk or posedge reset) begin if (reset) begin irq_count <= {16{1'b0}}; end else begin if (sw_reset_strobe == 1) begin irq_count <= {16{1'b0}}; end else begin case ({clear_irq_count, incr_irq_count}) 2'b00: irq_count <= irq_count; 2'b01: irq_count <= irq_count + 1; 2'b10: irq_count <= {16{1'b0}}; 2'b11: irq_count <= {{15{1'b0}}, 1'b1}; endcase end end end /******************************************** End Registers *************************************************/ /**************************************** Combinational Signals *********************************************/ generate if (ADDRESS_WIDTH == 3) begin always @ (csr_address or status or control or descriptor_watermark or response_watermark or sequence_number) begin case (csr_address) 3'b000: readdata = status; 3'b001: readdata = control; 3'b010: readdata = descriptor_watermark; 3'b011: readdata = response_watermark; default: readdata = sequence_number; // all other addresses will decode to the sequence number endcase end end else begin always @ (csr_address or status or control or descriptor_watermark or response_watermark) begin case (csr_address) 3'b000: readdata = status; 3'b001: readdata = control; 3'b010: readdata = descriptor_watermark; default: readdata = response_watermark; // all other addresses will decode to the response watermark endcase end end endgenerate assign clear_irq = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[1] == 1) & (csr_writedata[9] == 1); // this is the IRQ bit assign set_irq = (global_interrupt_enable == 1) & (done_strobe == 1) & // transfer ended and interrupts are enabled ((transfer_complete_IRQ_mask == 1) | // transfer ended and the transfer complete IRQ is enabled ((error & error_IRQ_mask) != 0) | // transfer ended with an error and this IRQ is enabled ((early_termination & early_termination_IRQ_mask) == 1)); // transfer ended early due to early termination and this IRQ is enabled assign csr_irq = irq; // Done count assign incr_irq_count = set_irq; // Done count just counts the number of interrupts since the last reset assign clear_irq_count = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[2] == 1) & (csr_writedata[16] == 1); // the LSB irq_count bit assign clear_stop = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 0); assign set_stopped_on_error = (done_strobe == 1) & (stop_on_error == 1) & (error != 0); // when clear_stop is set then the stopped_on_error register will be cleared assign set_stopped_on_early_termination = (done_strobe == 1) & (stop_on_early_termination == 1) & (early_termination == 1); // when clear_stop is set then the stopped_on_early_termination register will be cleared assign set_stop = ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 1)) | // host set the stop bit (set_stopped_on_error == 1) | // SGDMA setup to stop when an error occurs from the write master (set_stopped_on_early_termination == 1) ; // SGDMA setup to stop when the write master overflows assign stop = control[0]; assign set_sw_reset = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[1] == 1); assign clear_sw_reset = (sw_reset == 1) & (reset_stalled == 0); assign sw_reset_strobe = control[1]; assign stop_on_error = control[2]; assign stop_on_early_termination = control[3]; assign global_interrupt_enable = control[4]; assign stop_descriptors = control[5]; assign csr_readdata = readdata_d1; assign status = {irq_count, {6{1'b0}}, irq, stopped_on_early_termination, stopped_on_error, sw_reset, stop_state, response_buffer_full, response_buffer_empty, descriptor_buffer_full, descriptor_buffer_empty, busy}; // writing to the lower byte of the status register clears the irq bit /**************************************** Combinational Signals *********************************************/ endmodule
module csr_block ( clk, reset, csr_writedata, csr_write, csr_byteenable, csr_readdata, csr_read, csr_address, csr_irq, done_strobe, busy, descriptor_buffer_empty, descriptor_buffer_full, stop_state, stopped_on_error, stopped_on_early_termination, reset_stalled, stop, sw_reset, stop_on_error, stop_on_early_termination, stop_descriptors, sequence_number, descriptor_watermark, response_watermark, response_buffer_empty, response_buffer_full, transfer_complete_IRQ_mask, error_IRQ_mask, early_termination_IRQ_mask, error, early_termination ); parameter ADDRESS_WIDTH = 3; localparam CONTROL_REGISTER_ADDRESS = 3'b001; input clk; input reset; input [31:0] csr_writedata; input csr_write; input [3:0] csr_byteenable; output wire [31:0] csr_readdata; input csr_read; input [ADDRESS_WIDTH-1:0] csr_address; output wire csr_irq; input done_strobe; input busy; input descriptor_buffer_empty; input descriptor_buffer_full; input stop_state; // when the DMA runs into some error condition and you have enabled the stop on error (or when the stop control bit is written to) input reset_stalled; // the read or write master could be in the middle of a transfer/burst so it might take a while to flush the buffers output wire stop; output reg stopped_on_error; output reg stopped_on_early_termination; output reg sw_reset; output wire stop_on_error; output wire stop_on_early_termination; output wire stop_descriptors; input [31:0] sequence_number; input [31:0] descriptor_watermark; input [15:0] response_watermark; input response_buffer_empty; input response_buffer_full; input transfer_complete_IRQ_mask; input [7:0] error_IRQ_mask; input early_termination_IRQ_mask; input [7:0] error; input early_termination; /* Internal wires and registers */ wire [31:0] status; reg [31:0] control; reg [31:0] readdata; reg [31:0] readdata_d1; reg irq; // writing to the status register clears the irq bit wire set_irq; wire clear_irq; reg [15:0] irq_count; // writing to bit 0 clears the counter wire clear_irq_count; wire incr_irq_count; wire set_stopped_on_error; wire set_stopped_on_early_termination; wire set_stop; wire clear_stop; wire global_interrupt_enable; wire sw_reset_strobe; // this strobe will be one cycle earlier than sw_reset wire set_sw_reset; wire clear_sw_reset; /********************************************** Registers ***************************************************/ // read latency is 1 cycle always @ (posedge clk or posedge reset) begin if (reset) begin readdata_d1 <= 0; end else if (csr_read == 1) begin readdata_d1 <= readdata; end end always @ (posedge clk or posedge reset) begin if (reset) begin control[31:1] <= 0; end else begin if (sw_reset_strobe == 1) // reset strobe is a strobe due to this sync reset begin control[31:1] <= 0; end else begin if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1)) begin control[7:1] <= csr_writedata[7:1]; // stop bit will be handled seperately since it can be set by the csr slave port access or the SGDMA hitting an error condition end if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[1] == 1)) begin control[15:8] <= csr_writedata[15:8]; end if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[2] == 1)) begin control[23:16] <= csr_writedata[23:16]; end if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[3] == 1)) begin control[31:24] <= csr_writedata[31:24]; end end end end // control bit 0 (stop) is set by different sources so handling it seperately always @ (posedge clk or posedge reset) begin if (reset) begin control[0] <= 0; end else begin if (sw_reset_strobe == 1) begin control[0] <= 0; end else begin case ({set_stop, clear_stop}) 2'b00: control[0] <= control[0]; 2'b01: control[0] <= 1'b0; 2'b10: control[0] <= 1'b1; 2'b11: control[0] <= 1'b1; // setting will win, this case happens control[0] is being set to 0 (resume) at the same time an error/early termination stop condition occurs endcase end end end always @ (posedge clk or posedge reset) begin if (reset) begin sw_reset <= 0; end else begin if (set_sw_reset == 1) begin sw_reset <= 1; end else if (clear_sw_reset == 1) begin sw_reset <= 0; end end end always @ (posedge clk or posedge reset) begin if (reset) begin stopped_on_error <= 0; end else begin case ({set_stopped_on_error, clear_stop}) 2'b00: stopped_on_error <= stopped_on_error; 2'b01: stopped_on_error <= 1'b0; 2'b10: stopped_on_error <= 1'b1; 2'b11: stopped_on_error <= 1'b0; endcase end end always @ (posedge clk or posedge reset) begin if (reset) begin stopped_on_early_termination <= 0; end else begin case ({set_stopped_on_early_termination, clear_stop}) 2'b00: stopped_on_early_termination <= stopped_on_early_termination; 2'b01: stopped_on_early_termination <= 1'b0; 2'b10: stopped_on_early_termination <= 1'b1; 2'b11: stopped_on_early_termination <= 1'b0; endcase end end always @ (posedge clk or posedge reset) begin if (reset) begin irq <= 0; end else begin if (sw_reset_strobe == 1) begin irq <= 0; end else begin case ({clear_irq, set_irq}) 2'b00: irq <= irq; 2'b01: irq <= 1'b1; 2'b10: irq <= 1'b0; 2'b11: irq <= 1'b1; // setting will win over a clear endcase end end end always @ (posedge clk or posedge reset) begin if (reset) begin irq_count <= {16{1'b0}}; end else begin if (sw_reset_strobe == 1) begin irq_count <= {16{1'b0}}; end else begin case ({clear_irq_count, incr_irq_count}) 2'b00: irq_count <= irq_count; 2'b01: irq_count <= irq_count + 1; 2'b10: irq_count <= {16{1'b0}}; 2'b11: irq_count <= {{15{1'b0}}, 1'b1}; endcase end end end /******************************************** End Registers *************************************************/ /**************************************** Combinational Signals *********************************************/ generate if (ADDRESS_WIDTH == 3) begin always @ (csr_address or status or control or descriptor_watermark or response_watermark or sequence_number) begin case (csr_address) 3'b000: readdata = status; 3'b001: readdata = control; 3'b010: readdata = descriptor_watermark; 3'b011: readdata = response_watermark; default: readdata = sequence_number; // all other addresses will decode to the sequence number endcase end end else begin always @ (csr_address or status or control or descriptor_watermark or response_watermark) begin case (csr_address) 3'b000: readdata = status; 3'b001: readdata = control; 3'b010: readdata = descriptor_watermark; default: readdata = response_watermark; // all other addresses will decode to the response watermark endcase end end endgenerate assign clear_irq = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[1] == 1) & (csr_writedata[9] == 1); // this is the IRQ bit assign set_irq = (global_interrupt_enable == 1) & (done_strobe == 1) & // transfer ended and interrupts are enabled ((transfer_complete_IRQ_mask == 1) | // transfer ended and the transfer complete IRQ is enabled ((error & error_IRQ_mask) != 0) | // transfer ended with an error and this IRQ is enabled ((early_termination & early_termination_IRQ_mask) == 1)); // transfer ended early due to early termination and this IRQ is enabled assign csr_irq = irq; // Done count assign incr_irq_count = set_irq; // Done count just counts the number of interrupts since the last reset assign clear_irq_count = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[2] == 1) & (csr_writedata[16] == 1); // the LSB irq_count bit assign clear_stop = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 0); assign set_stopped_on_error = (done_strobe == 1) & (stop_on_error == 1) & (error != 0); // when clear_stop is set then the stopped_on_error register will be cleared assign set_stopped_on_early_termination = (done_strobe == 1) & (stop_on_early_termination == 1) & (early_termination == 1); // when clear_stop is set then the stopped_on_early_termination register will be cleared assign set_stop = ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 1)) | // host set the stop bit (set_stopped_on_error == 1) | // SGDMA setup to stop when an error occurs from the write master (set_stopped_on_early_termination == 1) ; // SGDMA setup to stop when the write master overflows assign stop = control[0]; assign set_sw_reset = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[1] == 1); assign clear_sw_reset = (sw_reset == 1) & (reset_stalled == 0); assign sw_reset_strobe = control[1]; assign stop_on_error = control[2]; assign stop_on_early_termination = control[3]; assign global_interrupt_enable = control[4]; assign stop_descriptors = control[5]; assign csr_readdata = readdata_d1; assign status = {irq_count, {6{1'b0}}, irq, stopped_on_early_termination, stopped_on_error, sw_reset, stop_state, response_buffer_full, response_buffer_empty, descriptor_buffer_full, descriptor_buffer_empty, busy}; // writing to the lower byte of the status register clears the irq bit /**************************************** Combinational Signals *********************************************/ endmodule
module csr_block ( clk, reset, csr_writedata, csr_write, csr_byteenable, csr_readdata, csr_read, csr_address, csr_irq, done_strobe, busy, descriptor_buffer_empty, descriptor_buffer_full, stop_state, stopped_on_error, stopped_on_early_termination, reset_stalled, stop, sw_reset, stop_on_error, stop_on_early_termination, stop_descriptors, sequence_number, descriptor_watermark, response_watermark, response_buffer_empty, response_buffer_full, transfer_complete_IRQ_mask, error_IRQ_mask, early_termination_IRQ_mask, error, early_termination ); parameter ADDRESS_WIDTH = 3; localparam CONTROL_REGISTER_ADDRESS = 3'b001; input clk; input reset; input [31:0] csr_writedata; input csr_write; input [3:0] csr_byteenable; output wire [31:0] csr_readdata; input csr_read; input [ADDRESS_WIDTH-1:0] csr_address; output wire csr_irq; input done_strobe; input busy; input descriptor_buffer_empty; input descriptor_buffer_full; input stop_state; // when the DMA runs into some error condition and you have enabled the stop on error (or when the stop control bit is written to) input reset_stalled; // the read or write master could be in the middle of a transfer/burst so it might take a while to flush the buffers output wire stop; output reg stopped_on_error; output reg stopped_on_early_termination; output reg sw_reset; output wire stop_on_error; output wire stop_on_early_termination; output wire stop_descriptors; input [31:0] sequence_number; input [31:0] descriptor_watermark; input [15:0] response_watermark; input response_buffer_empty; input response_buffer_full; input transfer_complete_IRQ_mask; input [7:0] error_IRQ_mask; input early_termination_IRQ_mask; input [7:0] error; input early_termination; /* Internal wires and registers */ wire [31:0] status; reg [31:0] control; reg [31:0] readdata; reg [31:0] readdata_d1; reg irq; // writing to the status register clears the irq bit wire set_irq; wire clear_irq; reg [15:0] irq_count; // writing to bit 0 clears the counter wire clear_irq_count; wire incr_irq_count; wire set_stopped_on_error; wire set_stopped_on_early_termination; wire set_stop; wire clear_stop; wire global_interrupt_enable; wire sw_reset_strobe; // this strobe will be one cycle earlier than sw_reset wire set_sw_reset; wire clear_sw_reset; /********************************************** Registers ***************************************************/ // read latency is 1 cycle always @ (posedge clk or posedge reset) begin if (reset) begin readdata_d1 <= 0; end else if (csr_read == 1) begin readdata_d1 <= readdata; end end always @ (posedge clk or posedge reset) begin if (reset) begin control[31:1] <= 0; end else begin if (sw_reset_strobe == 1) // reset strobe is a strobe due to this sync reset begin control[31:1] <= 0; end else begin if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1)) begin control[7:1] <= csr_writedata[7:1]; // stop bit will be handled seperately since it can be set by the csr slave port access or the SGDMA hitting an error condition end if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[1] == 1)) begin control[15:8] <= csr_writedata[15:8]; end if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[2] == 1)) begin control[23:16] <= csr_writedata[23:16]; end if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[3] == 1)) begin control[31:24] <= csr_writedata[31:24]; end end end end // control bit 0 (stop) is set by different sources so handling it seperately always @ (posedge clk or posedge reset) begin if (reset) begin control[0] <= 0; end else begin if (sw_reset_strobe == 1) begin control[0] <= 0; end else begin case ({set_stop, clear_stop}) 2'b00: control[0] <= control[0]; 2'b01: control[0] <= 1'b0; 2'b10: control[0] <= 1'b1; 2'b11: control[0] <= 1'b1; // setting will win, this case happens control[0] is being set to 0 (resume) at the same time an error/early termination stop condition occurs endcase end end end always @ (posedge clk or posedge reset) begin if (reset) begin sw_reset <= 0; end else begin if (set_sw_reset == 1) begin sw_reset <= 1; end else if (clear_sw_reset == 1) begin sw_reset <= 0; end end end always @ (posedge clk or posedge reset) begin if (reset) begin stopped_on_error <= 0; end else begin case ({set_stopped_on_error, clear_stop}) 2'b00: stopped_on_error <= stopped_on_error; 2'b01: stopped_on_error <= 1'b0; 2'b10: stopped_on_error <= 1'b1; 2'b11: stopped_on_error <= 1'b0; endcase end end always @ (posedge clk or posedge reset) begin if (reset) begin stopped_on_early_termination <= 0; end else begin case ({set_stopped_on_early_termination, clear_stop}) 2'b00: stopped_on_early_termination <= stopped_on_early_termination; 2'b01: stopped_on_early_termination <= 1'b0; 2'b10: stopped_on_early_termination <= 1'b1; 2'b11: stopped_on_early_termination <= 1'b0; endcase end end always @ (posedge clk or posedge reset) begin if (reset) begin irq <= 0; end else begin if (sw_reset_strobe == 1) begin irq <= 0; end else begin case ({clear_irq, set_irq}) 2'b00: irq <= irq; 2'b01: irq <= 1'b1; 2'b10: irq <= 1'b0; 2'b11: irq <= 1'b1; // setting will win over a clear endcase end end end always @ (posedge clk or posedge reset) begin if (reset) begin irq_count <= {16{1'b0}}; end else begin if (sw_reset_strobe == 1) begin irq_count <= {16{1'b0}}; end else begin case ({clear_irq_count, incr_irq_count}) 2'b00: irq_count <= irq_count; 2'b01: irq_count <= irq_count + 1; 2'b10: irq_count <= {16{1'b0}}; 2'b11: irq_count <= {{15{1'b0}}, 1'b1}; endcase end end end /******************************************** End Registers *************************************************/ /**************************************** Combinational Signals *********************************************/ generate if (ADDRESS_WIDTH == 3) begin always @ (csr_address or status or control or descriptor_watermark or response_watermark or sequence_number) begin case (csr_address) 3'b000: readdata = status; 3'b001: readdata = control; 3'b010: readdata = descriptor_watermark; 3'b011: readdata = response_watermark; default: readdata = sequence_number; // all other addresses will decode to the sequence number endcase end end else begin always @ (csr_address or status or control or descriptor_watermark or response_watermark) begin case (csr_address) 3'b000: readdata = status; 3'b001: readdata = control; 3'b010: readdata = descriptor_watermark; default: readdata = response_watermark; // all other addresses will decode to the response watermark endcase end end endgenerate assign clear_irq = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[1] == 1) & (csr_writedata[9] == 1); // this is the IRQ bit assign set_irq = (global_interrupt_enable == 1) & (done_strobe == 1) & // transfer ended and interrupts are enabled ((transfer_complete_IRQ_mask == 1) | // transfer ended and the transfer complete IRQ is enabled ((error & error_IRQ_mask) != 0) | // transfer ended with an error and this IRQ is enabled ((early_termination & early_termination_IRQ_mask) == 1)); // transfer ended early due to early termination and this IRQ is enabled assign csr_irq = irq; // Done count assign incr_irq_count = set_irq; // Done count just counts the number of interrupts since the last reset assign clear_irq_count = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[2] == 1) & (csr_writedata[16] == 1); // the LSB irq_count bit assign clear_stop = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 0); assign set_stopped_on_error = (done_strobe == 1) & (stop_on_error == 1) & (error != 0); // when clear_stop is set then the stopped_on_error register will be cleared assign set_stopped_on_early_termination = (done_strobe == 1) & (stop_on_early_termination == 1) & (early_termination == 1); // when clear_stop is set then the stopped_on_early_termination register will be cleared assign set_stop = ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 1)) | // host set the stop bit (set_stopped_on_error == 1) | // SGDMA setup to stop when an error occurs from the write master (set_stopped_on_early_termination == 1) ; // SGDMA setup to stop when the write master overflows assign stop = control[0]; assign set_sw_reset = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[1] == 1); assign clear_sw_reset = (sw_reset == 1) & (reset_stalled == 0); assign sw_reset_strobe = control[1]; assign stop_on_error = control[2]; assign stop_on_early_termination = control[3]; assign global_interrupt_enable = control[4]; assign stop_descriptors = control[5]; assign csr_readdata = readdata_d1; assign status = {irq_count, {6{1'b0}}, irq, stopped_on_early_termination, stopped_on_error, sw_reset, stop_state, response_buffer_full, response_buffer_empty, descriptor_buffer_full, descriptor_buffer_empty, busy}; // writing to the lower byte of the status register clears the irq bit /**************************************** Combinational Signals *********************************************/ endmodule