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module fifo_generator_v13_1_3_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_USE_DOUT_RST = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_FIFO_TYPE = 0
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input RD_CLK,
input RD_EN,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
output reg [C_DOUT_WIDTH-1:0] DOUT = 0,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL
);
//-----------------------------------------------------------------------------
// Low Latency Asynchronous FIFO
//-----------------------------------------------------------------------------
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
integer i;
initial begin
for (i = 0; i < C_WR_DEPTH; i = i + 1)
memory[i] = 0;
end
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
reg ll_afifo_full = 1'b0;
reg ll_afifo_empty = 1'b1;
wire write_allow;
wire read_allow;
assign write_allow = WR_EN & ~ll_afifo_full;
assign read_allow = RD_EN & ~ll_afifo_empty;
//-----------------------------------------------------------------------------
// Write Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
wr_pntr_ll_afifo <= 0;
else if (write_allow)
wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
end
//-----------------------------------------------------------------------------
// Read Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
rd_pntr_ll_afifo_q <= 0;
else
rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
end
assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
//-----------------------------------------------------------------------------
// Fill the Memory
//-----------------------------------------------------------------------------
always @(posedge WR_CLK) begin
if (write_allow)
memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
end
//-----------------------------------------------------------------------------
// Generate DOUT
//-----------------------------------------------------------------------------
always @(posedge RD_CLK) begin
DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
end
//-----------------------------------------------------------------------------
// Generate EMPTY
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
ll_afifo_empty <= 1'b1;
else
ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) |
(read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));
end
//-----------------------------------------------------------------------------
// Generate FULL
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
ll_afifo_full <= 1'b1;
else
ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) |
(write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));
end
always @* begin
FULL <= ll_afifo_full;
EMPTY <= ll_afifo_empty;
end
endmodule |
module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_EN;
wire RST;
wire WR_EN;
*/
// Assign ALMOST_EPMTY
generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
assign ALMOST_EMPTY = almost_empty_i;
end else begin : gnae
assign ALMOST_EMPTY = 0;
end endgenerate // gae
// Assign ALMOST_FULL
generate if (C_HAS_ALMOST_FULL==1) begin : gaf
assign ALMOST_FULL = almost_full_i;
end else begin : gnaf
assign ALMOST_FULL = 0;
end endgenerate // gaf
// Dout may change behavior based on latency
localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT = ideal_dout_out;
// Assign SBITERR and DBITERR based on latency
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
assign EMPTY = empty_i;
assign FULL = full_i;
//saftey_ckt with one register
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK)
begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)
begin
if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end
else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
valid_d1 <= #`TCQ valid_i;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end //if
endgenerate
//safety ckt with both registers
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK) begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end //if
endgenerate
//Overflow may be active-low
generate if (C_HAS_OVERFLOW==1) begin : gof
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end else begin : gnof
assign OVERFLOW = 0;
end endgenerate // gof
assign PROG_EMPTY = prog_empty_i;
assign PROG_FULL = prog_full_i;
//Valid may change behavior based on latency or active-low
generate if (C_HAS_VALID==1) begin : gvalid
assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
valid_d1 : valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end else begin : gnvalid
assign VALID = 0;
end endgenerate // gvalid
//Trim data count differently depending on set widths
generate if (C_HAS_DATA_COUNT == 1) begin : gdc
always @* begin
diff_count <= wr_pntr - rd_pntr;
if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count;
DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ;
end else begin
DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
end
end
// end else begin : gndc
// always @* DATA_COUNT <= 0;
end endgenerate // gdc
//Underflow may change behavior based on latency or active-low
generate if (C_HAS_UNDERFLOW==1) begin : guf
assign underflow_i = ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end else begin : gnuf
assign UNDERFLOW = 0;
end endgenerate // guf
//Write acknowledge may be active low
generate if (C_HAS_WR_ACK==1) begin : gwr_ack
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end else begin : gnwr_ack
assign WR_ACK = 0;
end endgenerate // gwr_ack
/*****************************************************************************
* Internal reset logic
****************************************************************************/
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;
assign rst_i = C_HAS_RST ? RST : 0;
assign srst_wrst_busy = srst_i;
assign srst_rrst_busy = srst_i;
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_both <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
valid_both <= #`TCQ 1'b0;
end else begin
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge CLK or posedge rst_i) begin
if (rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//reg ram_rd_en_d1 = 1'b0;
//Capture delayed version of dout
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
ram_rd_en_d1 <= #`TCQ 1'b0;
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
end // always
end
endgenerate
//no safety ckt with both registers
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);
if (ram_rd_en_d1 ) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end // always
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge CLK) begin
ideal_overflow <= #`TCQ WR_EN & full_i;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i);
ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);
end
end endgenerate // blockOF20
generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge CLK) begin
ideal_underflow <= #`TCQ empty_i & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge CLK) begin
//ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN;
ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;
end
end endgenerate // blockUF20
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/*************************************************************************
* Write and Read Logic
************************************************************************/
wire write_allow;
wire read_allow;
wire read_allow_dc;
wire write_only;
wire read_only;
//wire write_only_q;
reg write_only_q;
//wire read_only_q;
reg read_only_q;
reg full_reg;
reg rst_full_ff_reg1;
reg rst_full_ff_reg2;
wire ram_full_comb;
wire carry;
assign write_allow = WR_EN & ~full_i;
assign read_allow = RD_EN & ~empty_i;
assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;
//assign write_only = write_allow & ~read_allow;
//assign write_only_q = write_allow_q;
//assign read_only = read_allow & ~write_allow;
//assign read_only_q = read_allow_q ;
wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;
reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;
wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;
wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;
assign diff_pntr_pe_max = DIFF_MAX_RD;
assign diff_pntr_max = DIFF_MAX_WR;
generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym
assign write_only = write_allow & ~read_allow;
assign read_only = read_allow & ~write_allow;
end endgenerate
generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd
assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;
assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr
assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;
end endgenerate
//-----------------------------------------------------------------------------
// Write and Read pointer generation
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
wr_pntr <= 0;
rd_pntr <= 0;
end else begin
if (srst_i) begin
wr_pntr <= #`TCQ 0;
rd_pntr <= #`TCQ 0;
end else begin
if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1;
end
end
end
generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
always @(posedge CLK) begin
if (write_allow) begin
if (ENABLE_ERR_INJECTION == 1)
memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
else
memory[wr_pntr] <= #`TCQ DIN;
end
end
reg [C_DATA_WIDTH-1:0] dout_tmp_q;
reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
always @(posedge CLK) begin
dout_tmp_q <= #`TCQ ideal_dout;
end
always @* begin
if (read_allow)
ideal_dout <= memory[rd_pntr];
else
ideal_dout <= dout_tmp_q;
end
end endgenerate // gll_dm_dout
/**************************************************************************
* Write Domain Logic
**************************************************************************/
assign ram_rd_en = RD_EN & !EMPTY;
//reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
generate if (C_FIFO_TYPE != 2) begin : gnll_din
always @(posedge CLK or posedge rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //rst_i==0
if (srst_wrst_busy) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin//srst_i=0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end else begin
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
//end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //srst_i==0
end //wr_rst_i==0
end // gen_fifo_w
end endgenerate
generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout
always @(posedge CLK) begin
if (rst_i || srst_rrst_busy) begin
if (C_USE_DOUT_RST == 1) begin
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end
end
end endgenerate
generate if (C_FIFO_TYPE != 2) begin : gnll_dout
always @(posedge CLK or posedge rst_i) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rst_i) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
if (srst_rrst_busy) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets synchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end //srst_i
else begin
//rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
if (RD_EN == 1'b1) begin
if (EMPTY == 1'b1) begin
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end
else
begin
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
end
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //s_rst_i==0
end //rd_rst_i==0
end //always
end endgenerate
//-----------------------------------------------------------------------------
// Generate diff_pntr for PROG_FULL generation
// Generate diff_pntr_pe for PROG_EMPTY generation
//-----------------------------------------------------------------------------
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow
always @(posedge CLK ) begin
if (rst_i) begin
write_only_q <= 1'b0;
read_only_q <= 1'b0;
diff_pntr_reg1 <= 0;
diff_pntr_pe_reg1 <= 0;
diff_pntr_reg2 <= 0;
diff_pntr_pe_reg2 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_rrst_busy) begin
read_only_q <= #`TCQ 1'b0;
diff_pntr_pe_reg1 <= #`TCQ 0;
diff_pntr_pe_reg2 <= #`TCQ 0;
end
if (srst_wrst_busy) begin
write_only_q <= #`TCQ 1'b0;
diff_pntr_reg1 <= #`TCQ 0;
diff_pntr_reg2 <= #`TCQ 0;
end
end else begin
write_only_q <= #`TCQ write_only;
read_only_q <= #`TCQ read_only;
diff_pntr_reg2 <= #`TCQ diff_pntr_reg1;
diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1;
// Add 1 to the difference pointer value when only write happens.
if (write_only)
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;
else
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
// Add 1 to the difference pointer value when write or both write & read or no write & read happen.
if (read_only)
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;
else
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;
end
end
end
assign diff_pntr_pe = diff_pntr_pe_reg1;
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym
assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};
assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};
always @(posedge CLK ) begin
if (rst_i) begin
diff_pntr_pe_asym <= 0;
diff_pntr_reg1 <= 0;
full_reg <= 0;
rst_full_ff_reg1 <= 1;
rst_full_ff_reg2 <= 1;
diff_pntr_pe_reg1 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_wrst_busy)
diff_pntr_reg1 <= #`TCQ 0;
if (srst_rrst_busy)
full_reg <= #`TCQ 0;
rst_full_ff_reg1 <= #`TCQ 1;
rst_full_ff_reg2 <= #`TCQ 1;
diff_pntr_pe_asym <= #`TCQ 0;
diff_pntr_pe_reg1 <= #`TCQ 0;
end else begin
diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;
full_reg <= #`TCQ full_i;
rst_full_ff_reg1 <= #`TCQ RST_FULL_FF;
rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1;
if (~full_i) begin
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
end
end
end
end
assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));
assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow_asym
//-----------------------------------------------------------------------------
// Generate FULL flag
//-----------------------------------------------------------------------------
wire comp0;
wire comp1;
wire going_full;
wire leaving_full;
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad
assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim
assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1));
assign comp0 = (adj_rd_pntr_wr == wr_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym
assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_full_comb = going_full | (~leaving_full & full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
full_i <= #`TCQ ram_full_comb;
end
//-----------------------------------------------------------------------------
// Generate EMPTY flag
//-----------------------------------------------------------------------------
wire ecomp0;
wire ecomp1;
wire going_empty;
wire leaving_empty;
wire ram_empty_comb;
generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad
assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim
assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1));
assign ecomp0 = (adj_wr_pntr_rd == rd_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty = (ecomp0 & write_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp
assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty =(ecomp0 & write_allow);
end endgenerate
assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
empty_i <= 1'b1;
else if (srst_rrst_busy)
empty_i <= #`TCQ 1'b1;
else
empty_i <= #`TCQ ram_empty_comb;
end
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ ram_empty_comb;
end
end // always
//-----------------------------------------------------------------------------
// Generate Read and write data counts for asymmetic common clock
//-----------------------------------------------------------------------------
reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0;
wire [C_GRTR_PNTR_WIDTH :0] ratio;
wire decr_by_one;
wire incr_by_ratio;
wire incr_by_one;
wire decr_by_ratio;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr
assign ratio = C_DEPTH_RATIO_RD;
assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow;
assign incr_by_ratio = write_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (decr_by_one) begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc - 1;
else
count_dc <= #`TCQ count_dc - 1 + ratio ;
end
else begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc + ratio ;
end
end
end
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd
assign ratio = C_DEPTH_RATIO_WR;
assign incr_by_one = write_allow;
assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (incr_by_one) begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc + 1;
else
count_dc <= #`TCQ count_dc + 1 - ratio ;
end
else begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc - ratio ;
end
end
end
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
//-----------------------------------------------------------------------------
// Generate WR_ACK flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_wr_ack <= 1'b0;
else if (srst_wrst_busy)
ideal_wr_ack <= #`TCQ 1'b0;
else if (WR_EN & ~full_i)
ideal_wr_ack <= #`TCQ 1'b1;
else
ideal_wr_ack <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate VALID flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_valid <= 1'b0;
else if (srst_rrst_busy)
ideal_valid <= #`TCQ 1'b0;
else if (RD_EN & ~empty_i)
ideal_valid <= #`TCQ 1'b1;
else
ideal_valid <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate ALMOST_FULL flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
wire fcomp2;
wire going_afull;
wire leaving_afull;
wire ram_afull_comb;
assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym
assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
almost_full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
almost_full_i <= #`TCQ ram_afull_comb;
end
// end endgenerate // gaf_ss
//-----------------------------------------------------------------------------
// Generate ALMOST_EMPTY flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
wire ecomp2;
wire going_aempty;
wire leaving_aempty;
wire ram_aempty_comb;
assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty = (ecomp1 & write_allow & ~read_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp
assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);
end endgenerate
assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
almost_empty_i <= 1'b1;
else if (srst_rrst_busy)
almost_empty_i <= #`TCQ 1'b1;
else
almost_empty_i <= #`TCQ ram_aempty_comb;
end
// end endgenerate // gae_ss
//-----------------------------------------------------------------------------
// Generate PROG_FULL
//-----------------------------------------------------------------------------
localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT
C_PROG_FULL_THRESH_ASSERT_VAL; // STD
localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT
C_PROG_FULL_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold constant
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;
generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr>= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr) < C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b0;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate // single_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr >= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < C_PF_NEGATE_VAL)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ?
PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT
PROG_FULL_THRESH; // STD
generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
always @(posedge CLK or posedge RST_FULL_FF) begin//0
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin //1
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin//2
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin//3
if (diff_pntr > pf3_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == pf3_assert_val) begin//4
if (read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b1;
end else//4
prog_full_i <= #`TCQ 1'b0;
end else//3
prog_full_i <= #`TCQ prog_full_i;
end //2
else begin//5
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin//6
if (diff_pntr >= pf3_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf3_assert_val) begin//7
prog_full_i <= #`TCQ 1'b0;
end//7
end//6
else
prog_full_i <= #`TCQ prog_full_i;
end//5
end//1
end//0
end endgenerate //single_pf_input
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_ASSERT; // STD
wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_NEGATE; // STD
generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin
if (diff_pntr >= pf_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr == pf_negate_val && read_only_q) ||
diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin
if (diff_pntr >= pf_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_inputs
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY
//-----------------------------------------------------------------------------
localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold constant
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b0;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_NEGATE_VAL)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate //multiple_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH -2) : // FWFT
PROG_EMPTY_THRESH; // STD
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe < pe3_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == pe3_assert_val) begin
if (write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ 1'b1;
end else
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe3_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe3_assert_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_input
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT
PROG_EMPTY_THRESH_ASSERT; // STD
wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT
PROG_EMPTY_THRESH_NEGATE; // STD
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe <= pe4_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) ||
(diff_pntr_pe > pe4_negate_val)) begin
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe4_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe4_negate_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // multiple_pe_inputs
endmodule |
module fifo_generator_v13_1_3_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USERVALID_LOW = 0,
parameter C_USERUNDERFLOW_LOW = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
(
//Inputs
input SAFETY_CKT_RD_RST,
input RD_CLK,
input RD_RST,
input SRST,
input WR_RST_BUSY,
input RD_RST_BUSY,
input RD_EN,
input FIFOEMPTY,
input [C_DOUT_WIDTH-1:0] FIFODATA,
input FIFOSBITERR,
input FIFODBITERR,
//Outputs
output reg [C_DOUT_WIDTH-1:0] USERDATA,
output USERVALID,
output USERUNDERFLOW,
output USEREMPTY,
output USERALMOSTEMPTY,
output RAMVALID,
output FIFORDEN,
output reg USERSBITERR,
output reg USERDBITERR,
output reg STAGE2_REG_EN,
output fab_read_data_valid_i_o,
output read_data_valid_i_o,
output ram_valid_i_o,
output [1:0] VALID_STAGES
);
//Internal signals
wire preloadstage1;
wire preloadstage2;
reg ram_valid_i;
reg fab_valid;
reg read_data_valid_i;
reg fab_read_data_valid_i;
reg fab_read_data_valid_i_1;
reg ram_valid_i_d;
reg read_data_valid_i_d;
reg fab_read_data_valid_i_d;
wire ram_regout_en;
reg ram_regout_en_d1;
reg ram_regout_en_d2;
wire fab_regout_en;
wire ram_rd_en;
reg empty_i = 1'b1;
reg empty_sckt = 1'b1;
reg sckt_rrst_q = 1'b0;
reg sckt_rrst_done = 1'b0;
reg empty_q = 1'b1;
reg rd_en_q = 1'b0;
reg almost_empty_i = 1'b1;
reg almost_empty_q = 1'b1;
wire rd_rst_i;
wire srst_i;
reg [C_DOUT_WIDTH-1:0] userdata_both;
wire uservalid_both;
wire uservalid_one;
reg user_sbiterr_both = 1'b0;
reg user_dbiterr_both = 1'b0;
assign ram_valid_i_o = ram_valid_i;
assign read_data_valid_i_o = read_data_valid_i;
assign fab_read_data_valid_i_o = fab_read_data_valid_i;
/*************************************************************************
* FUNCTIONS
*************************************************************************/
/*************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
//*************************************************************************
// Set power-on states for regs
//*************************************************************************
initial begin
ram_valid_i = 1'b0;
fab_valid = 1'b0;
read_data_valid_i = 1'b0;
fab_read_data_valid_i = 1'b0;
fab_read_data_valid_i_1 = 1'b0;
USERDATA = hexstr_conv(C_DOUT_RST_VAL);
userdata_both = hexstr_conv(C_DOUT_RST_VAL);
USERSBITERR = 1'b0;
USERDBITERR = 1'b0;
user_sbiterr_both = 1'b0;
user_dbiterr_both = 1'b0;
end //initial
//***************************************************************************
// connect up optional reset
//***************************************************************************
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;
reg sckt_rd_rst_fwft = 1'b0;
reg fwft_rst_done_i = 1'b0;
wire fwft_rst_done;
assign fwft_rst_done = C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;
always @ (posedge RD_CLK) begin
sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i)
fwft_rst_done_i <= 1'b0;
else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)
fwft_rst_done_i <= #`TCQ 1'b1;
end
localparam INVALID = 0;
localparam STAGE1_VALID = 2;
localparam STAGE2_VALID = 1;
localparam BOTH_STAGES_VALID = 3;
reg [1:0] curr_fwft_state = INVALID;
reg [1:0] next_fwft_state = INVALID;
generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = preloadstage2;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
reg curr_state = 0;
reg next_state = 0;
reg leaving_empty_fwft = 0;
reg going_empty_fwft = 0;
reg empty_i_q = 0;
reg ram_rd_en_fwft = 0;
generate if (C_FIFO_TYPE == 2) begin : gll_fifo
always @* begin // FSM fo FWFT
case (curr_state)
1'b0: begin
if (~FIFOEMPTY)
next_state <= 1'b1;
else
next_state <= 1'b0;
end
1'b1: begin
if (FIFOEMPTY && RD_EN)
next_state <= 1'b0;
else
next_state <= 1'b1;
end
default: next_state <= 1'b0;
endcase
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_i <= 1'b1;
empty_i_q <= 1'b1;
ram_valid_i <= 1'b0;
end else if (srst_i) begin
empty_i <= #`TCQ 1'b1;
empty_i_q <= #`TCQ 1'b1;
ram_valid_i <= #`TCQ 1'b0;
end else begin
empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
empty_i_q <= #`TCQ FIFOEMPTY;
ram_valid_i <= #`TCQ next_state;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
curr_state <= 1'b0;
end else if (srst_i) begin
curr_state <= #`TCQ 1'b0;
end else begin
curr_state <= #`TCQ next_state;
end
end //always
wire fe_of_empty;
assign fe_of_empty = empty_i_q & ~FIFOEMPTY;
always @* begin // Finding leaving empty
case (curr_state)
1'b0: leaving_empty_fwft <= fe_of_empty;
1'b1: leaving_empty_fwft <= 1'b1;
default: leaving_empty_fwft <= 1'b0;
endcase
end
always @* begin // Finding going empty
case (curr_state)
1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN;
default: going_empty_fwft <= 1'b0;
endcase
end
always @* begin // Generating FWFT rd_en
case (curr_state)
1'b0: ram_rd_en_fwft <= ~FIFOEMPTY;
1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
default: ram_rd_en_fwft <= 1'b0;
endcase
end
assign ram_regout_en = ram_rd_en_fwft;
//assign ram_regout_en_d1 = ram_rd_en_fwft;
//assign ram_regout_en_d2 = ram_rd_en_fwft;
assign ram_rd_en = ram_rd_en_fwft;
end endgenerate // gll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false.
// Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (ram_rd_en == 1'b1) begin
ram_valid_i <= #`TCQ 1'b1;
end else begin
if (ram_regout_en == 1'b1)
ram_valid_i <= #`TCQ 1'b0;
else
ram_valid_i <= #`TCQ ram_valid_i;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_ram_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
generate if ( C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ FIFOEMPTY;
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
// BRAM resets synchronously
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin
always @ ( posedge rd_rst_i)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
//safety ckt with one register
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
//@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay
if (rd_rst_i == 1) begin
ram_regout_en_d1 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d1 <= #`TCQ 1'b0;
else
ram_regout_en_d1 <= #`TCQ ram_regout_en;
end
end //always
// assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));
assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1
if (rd_rst_i == 1) begin
ram_regout_en_d2 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d2 <= #`TCQ 1'b0;
else
ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;
end
end //always
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
always @ (posedge RD_CLK) begin
ram_valid_i_d <= #`TCQ ram_valid_i;
read_data_valid_i_d <= #`TCQ read_data_valid_i;
fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (ram_regout_en == 1'b1) begin
fab_valid <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
fab_valid <= #`TCQ 1'b0;
else
fab_valid <= #`TCQ fab_valid;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_fab_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG == 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else begin
if (ram_regout_en == 1'b1) begin
read_data_valid_i <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ read_data_valid_i;
end
end
end //always
end
endgenerate
//generate if(C_USE_EMBEDDED_REG == 3) begin
// always @ (posedge RD_CLK or posedge rd_rst_i) begin
// if (rd_rst_i)
// read_data_valid_i <= #`TCQ 1'b0;
// else if (srst_i)
// read_data_valid_i <= #`TCQ 1'b0;
//
// if (ram_regout_en == 1'b1) begin
// fab_read_data_valid_i <= #`TCQ 1'b0;
// end else begin
// if (fab_regout_en == 1'b1)
// fab_read_data_valid_i <= #`TCQ 1'b1;
// else
// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;
// end
// end //always
//end
//endgenerate
generate if(C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid
if (rd_rst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else
fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
always @ (posedge RD_CLK ) begin : proc_del1
begin
fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;
end
end //always
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty_both
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
reg FIFOEMPTY_1;
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @(posedge RD_CLK) begin
FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;
end
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ (~ram_valid_i);
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_sckt <= #`TCQ 1'b1;
sckt_rrst_q <= #`TCQ 1'b0;
sckt_rrst_done <= #`TCQ 1'b0;
end else begin
sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;
if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin
sckt_rrst_done <= #`TCQ 1'b1;
end else if (sckt_rrst_done) begin
// rising clock edge
empty_sckt <= #`TCQ 1'b0;
end
end
end //always
// assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;
assign USEREMPTY = empty_i;
assign USERALMOSTEMPTY = almost_empty_i;
assign FIFORDEN = ram_rd_en;
assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;
assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);
assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);
assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;
assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
//no safety ckt with both reg
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin
if (fwft_rst_done) begin
if (ram_regout_en) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end
end //always
end //if
endgenerate
//safety_ckt with both registers
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK) begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end //always
end //if
endgenerate
endmodule |
module fifo_generator_v13_1_3_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
generate
////////////////////////////////////////////////////////////////////
//
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000)
begin
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
reg load_s1;
wire load_s2;
wire load_s1_from_s2;
reg s_ready_i; //local signal of output
wire m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with slave side data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data1;
// Always load s2 on a valid transaction even if it's unnecessary
assign load_s2 = S_VALID & s_ready_i;
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
state <= ZERO;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else begin
case (state)
// No transaction stored locally
ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
s_ready_i <= 1'b0;
end
end
// TWO transaction stored locally
TWO: if (M_READY) begin
state <= ONE; // Read out one so move to ONE
s_ready_i <= 1'b1;
end
endcase // case (state)
end
end // always @ (posedge ACLK)
assign m_valid_i = state[0];
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000001)
begin
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with slave side data
always @(posedge ACLK)
begin
if (ARESET) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (m_valid_i & M_READY) begin
s_ready_i <= 1'b1;
m_valid_i <= 1'b0;
end else if (S_VALID & s_ready_i) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b1;
end
if (~m_valid_i) begin
storage_data1 <= S_PAYLOAD_DATA;
end
end
assign M_PAYLOAD_DATA = storage_data1;
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule |
module dividerp1(input wire clk,
output wire clk_out);
//-- Valor por defecto de la velocidad en baudios
parameter M = `T_100ms;
//-- Numero de bits para almacenar el divisor de baudios
localparam N = $clog2(M);
//-- Registro para implementar el contador modulo M
reg [N-1:0] divcounter = 0;
//-- Contador módulo M
always @(posedge clk)
divcounter <= (divcounter == M - 1) ? 0 : divcounter + 1;
//-- Sacar un pulso de anchura 1 ciclo de reloj si el generador
assign clk_out = (divcounter == 0) ? 1 : 0;
endmodule |
module dividerp1(input wire clk,
output wire clk_out);
//-- Valor por defecto de la velocidad en baudios
parameter M = `T_100ms;
//-- Numero de bits para almacenar el divisor de baudios
localparam N = $clog2(M);
//-- Registro para implementar el contador modulo M
reg [N-1:0] divcounter = 0;
//-- Contador módulo M
always @(posedge clk)
divcounter <= (divcounter == M - 1) ? 0 : divcounter + 1;
//-- Sacar un pulso de anchura 1 ciclo de reloj si el generador
assign clk_out = (divcounter == 0) ? 1 : 0;
endmodule |
module axi_crossbar_v2_1_addr_decoder #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_TARGETS = 2, // Number of decode targets = [1:16]
parameter integer C_NUM_TARGETS_LOG = 1, // Log2(C_NUM_TARGETS)
parameter integer C_NUM_RANGES = 1, // Number of alternative ranges that
// can match each target [1:16]
parameter integer C_ADDR_WIDTH = 32, // Width of decoder operand and of
// each base and high address [2:64]
parameter integer C_TARGET_ENC = 0, // Enable encoded target output
parameter integer C_TARGET_HOT = 1, // Enable 1-hot target output
parameter integer C_REGION_ENC = 0, // Enable REGION output
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b1}},
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b0}},
parameter [C_NUM_TARGETS:0] C_TARGET_QUAL = {C_NUM_TARGETS{1'b1}},
// Indicates whether each target has connectivity.
// Format: C_NUM_TARGETS{Bit1}.
parameter integer C_RESOLUTION = 0,
// Number of low-order ADDR bits that can be ignored when decoding.
parameter integer C_COMPARATOR_THRESHOLD = 6
// Number of decoded ADDR bits above which will implement comparator_static.
)
(
input wire [C_ADDR_WIDTH-1:0] ADDR, // Decoder input operand
output wire [C_NUM_TARGETS-1:0] TARGET_HOT, // Target matching address (1-hot)
output wire [C_NUM_TARGETS_LOG-1:0] TARGET_ENC, // Target matching address (encoded)
output wire MATCH, // Decode successful
output wire [3:0] REGION // Range within target matching address (encoded)
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
genvar target_cnt;
genvar region_cnt;
/////////////////////////////////////////////////////////////////////////////
// Function to detect addrs is in the addressable range.
// Only compare 4KB page address (ignore low-order 12 bits)
function decode_address;
input [C_ADDR_WIDTH-1:0] base, high, addr;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] mask;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] addr_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] base_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] high_page;
begin
addr_page = addr[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
base_page = base[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
high_page = high[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
if (base[C_ADDR_WIDTH-1] & ~high[C_ADDR_WIDTH-1]) begin
decode_address = 1'b0;
end else begin
mask = base_page ^ high_page;
if ( (base_page & ~mask) == (addr_page & ~mask) ) begin
decode_address = 1'b1;
end else begin
decode_address = 1'b0;
end
end
end
endfunction
// Generates a binary coded from onehotone encoded
function [3:0] f_hot2enc
(
input [15:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 16'b1010101010101010);
f_hot2enc[1] = |(one_hot & 16'b1100110011001100);
f_hot2enc[2] = |(one_hot & 16'b1111000011110000);
f_hot2enc[3] = |(one_hot & 16'b1111111100000000);
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Internal signals
wire [C_NUM_TARGETS-1:0] TARGET_HOT_I; // Target matching address (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT; // For address hit (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT_REG; // For address hit (1-hot).
wire [C_NUM_RANGES-1:0] REGION_HOT; // Reginon matching address (1-hot).
wire [3:0] TARGET_ENC_I; // Internal version of encoded hit.
/////////////////////////////////////////////////////////////////////////////
// Generate detection per region per target.
generate
for (target_cnt = 0; target_cnt < C_NUM_TARGETS; target_cnt = target_cnt + 1) begin : gen_target
for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region
// Detect if this is an address hit (including used region decoding).
if ((C_ADDR_WIDTH - C_RESOLUTION) > C_COMPARATOR_THRESHOLD) begin : gen_comparator_static
if (C_TARGET_QUAL[target_cnt] &&
((C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] == 0) ||
(C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] != 0))) begin : gen_addr_range
generic_baseblocks_v2_1_comparator_static #
(
.C_FAMILY("rtl"),
.C_VALUE(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION]),
.C_DATA_WIDTH(C_ADDR_WIDTH-C_RESOLUTION)
) addr_decode_comparator
(
.CIN(1'b1),
.A(ADDR[C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] &
~(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] ^
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION])),
.COUT(ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt])
);
end else begin : gen_null_range
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = 1'b0;
end
end else begin : gen_no_comparator_static
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = C_TARGET_QUAL[target_cnt] ?
decode_address(
C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
ADDR)
: 1'b0;
end // gen_comparator_static
assign ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS+target_cnt] = ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt];
assign REGION_HOT[region_cnt] = | ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS +: C_NUM_TARGETS];
end // gen_region
// All regions are non-overlapping
// => Or all the region detections for this target to determine if it is a hit.
assign TARGET_HOT_I[target_cnt] = | ADDRESS_HIT[target_cnt*C_NUM_RANGES +: C_NUM_RANGES];
end // gen_target
endgenerate
/////////////////////////////////////////////////////////////////////////////
// All regions are non-overlapping
// => Or all the target hit detections if it is a match.
assign MATCH = | TARGET_HOT_I;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
generate
if (C_TARGET_HOT == 1) begin : USE_TARGET_ONEHOT
assign TARGET_HOT = MATCH ? TARGET_HOT_I : 1;
end else begin : NO_TARGET_ONEHOT
assign TARGET_HOT = {C_NUM_TARGETS{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_TARGET_ENCODED
assign TARGET_ENC_I = f_hot2enc(TARGET_HOT_I);
assign TARGET_ENC = TARGET_ENC_I[C_NUM_TARGETS_LOG-1:0];
end else begin : NO_TARGET_ENCODED
assign TARGET_ENC = {C_NUM_TARGETS_LOG{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded region output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_REGION_ENCODED
assign REGION = f_hot2enc(REGION_HOT);
end else begin : NO_REGION_ENCODED
assign REGION = 4'b0;
end
endgenerate
endmodule |
module axi_crossbar_v2_1_addr_decoder #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_TARGETS = 2, // Number of decode targets = [1:16]
parameter integer C_NUM_TARGETS_LOG = 1, // Log2(C_NUM_TARGETS)
parameter integer C_NUM_RANGES = 1, // Number of alternative ranges that
// can match each target [1:16]
parameter integer C_ADDR_WIDTH = 32, // Width of decoder operand and of
// each base and high address [2:64]
parameter integer C_TARGET_ENC = 0, // Enable encoded target output
parameter integer C_TARGET_HOT = 1, // Enable 1-hot target output
parameter integer C_REGION_ENC = 0, // Enable REGION output
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b1}},
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b0}},
parameter [C_NUM_TARGETS:0] C_TARGET_QUAL = {C_NUM_TARGETS{1'b1}},
// Indicates whether each target has connectivity.
// Format: C_NUM_TARGETS{Bit1}.
parameter integer C_RESOLUTION = 0,
// Number of low-order ADDR bits that can be ignored when decoding.
parameter integer C_COMPARATOR_THRESHOLD = 6
// Number of decoded ADDR bits above which will implement comparator_static.
)
(
input wire [C_ADDR_WIDTH-1:0] ADDR, // Decoder input operand
output wire [C_NUM_TARGETS-1:0] TARGET_HOT, // Target matching address (1-hot)
output wire [C_NUM_TARGETS_LOG-1:0] TARGET_ENC, // Target matching address (encoded)
output wire MATCH, // Decode successful
output wire [3:0] REGION // Range within target matching address (encoded)
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
genvar target_cnt;
genvar region_cnt;
/////////////////////////////////////////////////////////////////////////////
// Function to detect addrs is in the addressable range.
// Only compare 4KB page address (ignore low-order 12 bits)
function decode_address;
input [C_ADDR_WIDTH-1:0] base, high, addr;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] mask;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] addr_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] base_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] high_page;
begin
addr_page = addr[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
base_page = base[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
high_page = high[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
if (base[C_ADDR_WIDTH-1] & ~high[C_ADDR_WIDTH-1]) begin
decode_address = 1'b0;
end else begin
mask = base_page ^ high_page;
if ( (base_page & ~mask) == (addr_page & ~mask) ) begin
decode_address = 1'b1;
end else begin
decode_address = 1'b0;
end
end
end
endfunction
// Generates a binary coded from onehotone encoded
function [3:0] f_hot2enc
(
input [15:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 16'b1010101010101010);
f_hot2enc[1] = |(one_hot & 16'b1100110011001100);
f_hot2enc[2] = |(one_hot & 16'b1111000011110000);
f_hot2enc[3] = |(one_hot & 16'b1111111100000000);
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Internal signals
wire [C_NUM_TARGETS-1:0] TARGET_HOT_I; // Target matching address (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT; // For address hit (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT_REG; // For address hit (1-hot).
wire [C_NUM_RANGES-1:0] REGION_HOT; // Reginon matching address (1-hot).
wire [3:0] TARGET_ENC_I; // Internal version of encoded hit.
/////////////////////////////////////////////////////////////////////////////
// Generate detection per region per target.
generate
for (target_cnt = 0; target_cnt < C_NUM_TARGETS; target_cnt = target_cnt + 1) begin : gen_target
for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region
// Detect if this is an address hit (including used region decoding).
if ((C_ADDR_WIDTH - C_RESOLUTION) > C_COMPARATOR_THRESHOLD) begin : gen_comparator_static
if (C_TARGET_QUAL[target_cnt] &&
((C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] == 0) ||
(C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] != 0))) begin : gen_addr_range
generic_baseblocks_v2_1_comparator_static #
(
.C_FAMILY("rtl"),
.C_VALUE(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION]),
.C_DATA_WIDTH(C_ADDR_WIDTH-C_RESOLUTION)
) addr_decode_comparator
(
.CIN(1'b1),
.A(ADDR[C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] &
~(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] ^
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION])),
.COUT(ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt])
);
end else begin : gen_null_range
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = 1'b0;
end
end else begin : gen_no_comparator_static
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = C_TARGET_QUAL[target_cnt] ?
decode_address(
C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
ADDR)
: 1'b0;
end // gen_comparator_static
assign ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS+target_cnt] = ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt];
assign REGION_HOT[region_cnt] = | ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS +: C_NUM_TARGETS];
end // gen_region
// All regions are non-overlapping
// => Or all the region detections for this target to determine if it is a hit.
assign TARGET_HOT_I[target_cnt] = | ADDRESS_HIT[target_cnt*C_NUM_RANGES +: C_NUM_RANGES];
end // gen_target
endgenerate
/////////////////////////////////////////////////////////////////////////////
// All regions are non-overlapping
// => Or all the target hit detections if it is a match.
assign MATCH = | TARGET_HOT_I;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
generate
if (C_TARGET_HOT == 1) begin : USE_TARGET_ONEHOT
assign TARGET_HOT = MATCH ? TARGET_HOT_I : 1;
end else begin : NO_TARGET_ONEHOT
assign TARGET_HOT = {C_NUM_TARGETS{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_TARGET_ENCODED
assign TARGET_ENC_I = f_hot2enc(TARGET_HOT_I);
assign TARGET_ENC = TARGET_ENC_I[C_NUM_TARGETS_LOG-1:0];
end else begin : NO_TARGET_ENCODED
assign TARGET_ENC = {C_NUM_TARGETS_LOG{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded region output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_REGION_ENCODED
assign REGION = f_hot2enc(REGION_HOT);
end else begin : NO_REGION_ENCODED
assign REGION = 4'b0;
end
endgenerate
endmodule |
module Tenth_Phase
//Module Parameters
/***SINGLE PRECISION***/
// W = 32
// EW = 8
// SW = 23
/***DOUBLE PRECISION***/
// W = 64
// EW = 11
// SW = 52
# (parameter W = 32, parameter EW = 8, parameter SW = 23)
// # (parameter W = 64, parameter EW = 11, parameter SW = 52)
(
//INPUTS
input wire clk, //Clock Signal
input wire rst, //Reset Signal
input wire load_i,
input wire sel_a_i, //Overflow/add/subt result's mux's selector
input wire sel_b_i, //underflow/add/subt result's mux's selector
input wire sign_i, //Sign of the largest Operand
input wire [EW-1:0] exp_ieee_i, //Final Exponent
input wire [SW-1:0] sgf_ieee_i,//Final Significand
//OUTPUTS
output wire [W-1:0] final_result_ieee_o //Final Result
);
//Wire Connection signals
wire [SW-1:0] Sgf_S_mux;
wire [EW-1:0] Exp_S_mux;
wire Sign_S_mux;
wire [W-1:0] final_result_reg;
wire overunder;
wire [EW-1:0] exp_mux_D1;
wire [SW-1:0] sgf_mux_D1;
//////////////////////////////////////////////////////////
assign overunder = sel_a_i | sel_b_i;
Mux_3x1 #(.W(1)) Sign_Mux (
.ctrl({sel_a_i,sel_b_i}),
.D0(sign_i),
.D1(1'b1),
.D2(1'b0),
.S(Sign_S_mux)
);
Multiplexer_AC #(.W(EW)) Exp_Mux (
.ctrl(overunder),
.D0(exp_ieee_i),
.D1(exp_mux_D1),
.S(Exp_S_mux)
);
Multiplexer_AC #(.W(SW)) Sgf_Mux (
.ctrl(overunder),
.D0(sgf_ieee_i),
.D1(sgf_mux_D1),
.S(Sgf_S_mux)
);
/////////////////////////////////////////////////////////
generate
if(W == 32) begin
assign exp_mux_D1 =8'hff;
assign sgf_mux_D1 =23'd0;
end
else begin
assign exp_mux_D1 =11'hfff;
assign sgf_mux_D1 =52'd0;
end
endgenerate
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
RegisterAdd #(.W(W)) Final_Result_IEEE (
.clk(clk),
.rst(rst),
.load(load_i),
.D({Sign_S_mux,Exp_S_mux,Sgf_S_mux}),
.Q(final_result_ieee_o)
);
endmodule |
module Tenth_Phase
//Module Parameters
/***SINGLE PRECISION***/
// W = 32
// EW = 8
// SW = 23
/***DOUBLE PRECISION***/
// W = 64
// EW = 11
// SW = 52
# (parameter W = 32, parameter EW = 8, parameter SW = 23)
// # (parameter W = 64, parameter EW = 11, parameter SW = 52)
(
//INPUTS
input wire clk, //Clock Signal
input wire rst, //Reset Signal
input wire load_i,
input wire sel_a_i, //Overflow/add/subt result's mux's selector
input wire sel_b_i, //underflow/add/subt result's mux's selector
input wire sign_i, //Sign of the largest Operand
input wire [EW-1:0] exp_ieee_i, //Final Exponent
input wire [SW-1:0] sgf_ieee_i,//Final Significand
//OUTPUTS
output wire [W-1:0] final_result_ieee_o //Final Result
);
//Wire Connection signals
wire [SW-1:0] Sgf_S_mux;
wire [EW-1:0] Exp_S_mux;
wire Sign_S_mux;
wire [W-1:0] final_result_reg;
wire overunder;
wire [EW-1:0] exp_mux_D1;
wire [SW-1:0] sgf_mux_D1;
//////////////////////////////////////////////////////////
assign overunder = sel_a_i | sel_b_i;
Mux_3x1 #(.W(1)) Sign_Mux (
.ctrl({sel_a_i,sel_b_i}),
.D0(sign_i),
.D1(1'b1),
.D2(1'b0),
.S(Sign_S_mux)
);
Multiplexer_AC #(.W(EW)) Exp_Mux (
.ctrl(overunder),
.D0(exp_ieee_i),
.D1(exp_mux_D1),
.S(Exp_S_mux)
);
Multiplexer_AC #(.W(SW)) Sgf_Mux (
.ctrl(overunder),
.D0(sgf_ieee_i),
.D1(sgf_mux_D1),
.S(Sgf_S_mux)
);
/////////////////////////////////////////////////////////
generate
if(W == 32) begin
assign exp_mux_D1 =8'hff;
assign sgf_mux_D1 =23'd0;
end
else begin
assign exp_mux_D1 =11'hfff;
assign sgf_mux_D1 =52'd0;
end
endgenerate
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
RegisterAdd #(.W(W)) Final_Result_IEEE (
.clk(clk),
.rst(rst),
.load(load_i),
.D({Sign_S_mux,Exp_S_mux,Sgf_S_mux}),
.Q(final_result_ieee_o)
);
endmodule |
module Tenth_Phase
//Module Parameters
/***SINGLE PRECISION***/
// W = 32
// EW = 8
// SW = 23
/***DOUBLE PRECISION***/
// W = 64
// EW = 11
// SW = 52
# (parameter W = 32, parameter EW = 8, parameter SW = 23)
// # (parameter W = 64, parameter EW = 11, parameter SW = 52)
(
//INPUTS
input wire clk, //Clock Signal
input wire rst, //Reset Signal
input wire load_i,
input wire sel_a_i, //Overflow/add/subt result's mux's selector
input wire sel_b_i, //underflow/add/subt result's mux's selector
input wire sign_i, //Sign of the largest Operand
input wire [EW-1:0] exp_ieee_i, //Final Exponent
input wire [SW-1:0] sgf_ieee_i,//Final Significand
//OUTPUTS
output wire [W-1:0] final_result_ieee_o //Final Result
);
//Wire Connection signals
wire [SW-1:0] Sgf_S_mux;
wire [EW-1:0] Exp_S_mux;
wire Sign_S_mux;
wire [W-1:0] final_result_reg;
wire overunder;
wire [EW-1:0] exp_mux_D1;
wire [SW-1:0] sgf_mux_D1;
//////////////////////////////////////////////////////////
assign overunder = sel_a_i | sel_b_i;
Mux_3x1 #(.W(1)) Sign_Mux (
.ctrl({sel_a_i,sel_b_i}),
.D0(sign_i),
.D1(1'b1),
.D2(1'b0),
.S(Sign_S_mux)
);
Multiplexer_AC #(.W(EW)) Exp_Mux (
.ctrl(overunder),
.D0(exp_ieee_i),
.D1(exp_mux_D1),
.S(Exp_S_mux)
);
Multiplexer_AC #(.W(SW)) Sgf_Mux (
.ctrl(overunder),
.D0(sgf_ieee_i),
.D1(sgf_mux_D1),
.S(Sgf_S_mux)
);
/////////////////////////////////////////////////////////
generate
if(W == 32) begin
assign exp_mux_D1 =8'hff;
assign sgf_mux_D1 =23'd0;
end
else begin
assign exp_mux_D1 =11'hfff;
assign sgf_mux_D1 =52'd0;
end
endgenerate
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
RegisterAdd #(.W(W)) Final_Result_IEEE (
.clk(clk),
.rst(rst),
.load(load_i),
.D({Sign_S_mux,Exp_S_mux,Sgf_S_mux}),
.Q(final_result_ieee_o)
);
endmodule |
module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output wire next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXBURST decodes
localparam P_AXBURST_FIXED = 2'b00;
localparam P_AXBURST_INCR = 2'b01;
localparam P_AXBURST_WRAP = 2'b10;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_AXI_ADDR_WIDTH-1:0] incr_cmd_byte_addr;
wire incr_next_pending;
wire [C_AXI_ADDR_WIDTH-1:0] wrap_cmd_byte_addr;
wire wrap_next_pending;
reg sel_first;
reg s_axburst_eq1;
reg s_axburst_eq0;
reg sel_first_i;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// INCR and WRAP translations are calcuated in independently, select the one
// for our transactions
// right shift by the UI width to the DRAM width ratio
assign m_axaddr = (s_axburst == P_AXBURST_FIXED) ? s_axaddr :
(s_axburst == P_AXBURST_INCR) ? incr_cmd_byte_addr :
wrap_cmd_byte_addr;
assign incr_burst = (s_axburst[1]) ? 1'b0 : 1'b1;
// Indicates if we are on the first transaction of a mc translation with more
// than 1 transaction.
always @(posedge clk) begin
if (reset | s_axhandshake) begin
sel_first <= 1'b1;
end else if (next) begin
sel_first <= 1'b0;
end
end
always @( * ) begin
if (reset | s_axhandshake) begin
sel_first_i = 1'b1;
end else if (next) begin
sel_first_i = 1'b0;
end else begin
sel_first_i = sel_first;
end
end
assign next_pending = s_axburst[1] ? s_axburst_eq1 : s_axburst_eq0;
always @(posedge clk) begin
if (sel_first_i || s_axburst[1]) begin
s_axburst_eq1 <= wrap_next_pending;
end else begin
s_axburst_eq1 <= incr_next_pending;
end
if (sel_first_i || !s_axburst[1]) begin
s_axburst_eq0 <= incr_next_pending;
end else begin
s_axburst_eq0 <= wrap_next_pending;
end
end
axi_protocol_converter_v2_1_b2s_incr_cmd #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
)
incr_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( s_axaddr ) ,
.axlen ( s_axlen ) ,
.axsize ( s_axsize ) ,
.axhandshake ( s_axhandshake ) ,
.cmd_byte_addr ( incr_cmd_byte_addr ) ,
.next ( next ) ,
.next_pending ( incr_next_pending )
);
axi_protocol_converter_v2_1_b2s_wrap_cmd #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
)
wrap_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( s_axaddr ) ,
.axlen ( s_axlen ) ,
.axsize ( s_axsize ) ,
.axhandshake ( s_axhandshake ) ,
.cmd_byte_addr ( wrap_cmd_byte_addr ) ,
.next ( next ) ,
.next_pending ( wrap_next_pending )
);
endmodule |
module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output wire next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXBURST decodes
localparam P_AXBURST_FIXED = 2'b00;
localparam P_AXBURST_INCR = 2'b01;
localparam P_AXBURST_WRAP = 2'b10;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_AXI_ADDR_WIDTH-1:0] incr_cmd_byte_addr;
wire incr_next_pending;
wire [C_AXI_ADDR_WIDTH-1:0] wrap_cmd_byte_addr;
wire wrap_next_pending;
reg sel_first;
reg s_axburst_eq1;
reg s_axburst_eq0;
reg sel_first_i;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// INCR and WRAP translations are calcuated in independently, select the one
// for our transactions
// right shift by the UI width to the DRAM width ratio
assign m_axaddr = (s_axburst == P_AXBURST_FIXED) ? s_axaddr :
(s_axburst == P_AXBURST_INCR) ? incr_cmd_byte_addr :
wrap_cmd_byte_addr;
assign incr_burst = (s_axburst[1]) ? 1'b0 : 1'b1;
// Indicates if we are on the first transaction of a mc translation with more
// than 1 transaction.
always @(posedge clk) begin
if (reset | s_axhandshake) begin
sel_first <= 1'b1;
end else if (next) begin
sel_first <= 1'b0;
end
end
always @( * ) begin
if (reset | s_axhandshake) begin
sel_first_i = 1'b1;
end else if (next) begin
sel_first_i = 1'b0;
end else begin
sel_first_i = sel_first;
end
end
assign next_pending = s_axburst[1] ? s_axburst_eq1 : s_axburst_eq0;
always @(posedge clk) begin
if (sel_first_i || s_axburst[1]) begin
s_axburst_eq1 <= wrap_next_pending;
end else begin
s_axburst_eq1 <= incr_next_pending;
end
if (sel_first_i || !s_axburst[1]) begin
s_axburst_eq0 <= incr_next_pending;
end else begin
s_axburst_eq0 <= wrap_next_pending;
end
end
axi_protocol_converter_v2_1_b2s_incr_cmd #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
)
incr_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( s_axaddr ) ,
.axlen ( s_axlen ) ,
.axsize ( s_axsize ) ,
.axhandshake ( s_axhandshake ) ,
.cmd_byte_addr ( incr_cmd_byte_addr ) ,
.next ( next ) ,
.next_pending ( incr_next_pending )
);
axi_protocol_converter_v2_1_b2s_wrap_cmd #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
)
wrap_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( s_axaddr ) ,
.axlen ( s_axlen ) ,
.axsize ( s_axsize ) ,
.axhandshake ( s_axhandshake ) ,
.cmd_byte_addr ( wrap_cmd_byte_addr ) ,
.next ( next ) ,
.next_pending ( wrap_next_pending )
);
endmodule |
module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output wire next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXBURST decodes
localparam P_AXBURST_FIXED = 2'b00;
localparam P_AXBURST_INCR = 2'b01;
localparam P_AXBURST_WRAP = 2'b10;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_AXI_ADDR_WIDTH-1:0] incr_cmd_byte_addr;
wire incr_next_pending;
wire [C_AXI_ADDR_WIDTH-1:0] wrap_cmd_byte_addr;
wire wrap_next_pending;
reg sel_first;
reg s_axburst_eq1;
reg s_axburst_eq0;
reg sel_first_i;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// INCR and WRAP translations are calcuated in independently, select the one
// for our transactions
// right shift by the UI width to the DRAM width ratio
assign m_axaddr = (s_axburst == P_AXBURST_FIXED) ? s_axaddr :
(s_axburst == P_AXBURST_INCR) ? incr_cmd_byte_addr :
wrap_cmd_byte_addr;
assign incr_burst = (s_axburst[1]) ? 1'b0 : 1'b1;
// Indicates if we are on the first transaction of a mc translation with more
// than 1 transaction.
always @(posedge clk) begin
if (reset | s_axhandshake) begin
sel_first <= 1'b1;
end else if (next) begin
sel_first <= 1'b0;
end
end
always @( * ) begin
if (reset | s_axhandshake) begin
sel_first_i = 1'b1;
end else if (next) begin
sel_first_i = 1'b0;
end else begin
sel_first_i = sel_first;
end
end
assign next_pending = s_axburst[1] ? s_axburst_eq1 : s_axburst_eq0;
always @(posedge clk) begin
if (sel_first_i || s_axburst[1]) begin
s_axburst_eq1 <= wrap_next_pending;
end else begin
s_axburst_eq1 <= incr_next_pending;
end
if (sel_first_i || !s_axburst[1]) begin
s_axburst_eq0 <= incr_next_pending;
end else begin
s_axburst_eq0 <= wrap_next_pending;
end
end
axi_protocol_converter_v2_1_b2s_incr_cmd #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
)
incr_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( s_axaddr ) ,
.axlen ( s_axlen ) ,
.axsize ( s_axsize ) ,
.axhandshake ( s_axhandshake ) ,
.cmd_byte_addr ( incr_cmd_byte_addr ) ,
.next ( next ) ,
.next_pending ( incr_next_pending )
);
axi_protocol_converter_v2_1_b2s_wrap_cmd #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
)
wrap_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( s_axaddr ) ,
.axlen ( s_axlen ) ,
.axsize ( s_axsize ) ,
.axhandshake ( s_axhandshake ) ,
.cmd_byte_addr ( wrap_cmd_byte_addr ) ,
.next ( next ) ,
.next_pending ( wrap_next_pending )
);
endmodule |
module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output wire next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXBURST decodes
localparam P_AXBURST_FIXED = 2'b00;
localparam P_AXBURST_INCR = 2'b01;
localparam P_AXBURST_WRAP = 2'b10;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_AXI_ADDR_WIDTH-1:0] incr_cmd_byte_addr;
wire incr_next_pending;
wire [C_AXI_ADDR_WIDTH-1:0] wrap_cmd_byte_addr;
wire wrap_next_pending;
reg sel_first;
reg s_axburst_eq1;
reg s_axburst_eq0;
reg sel_first_i;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// INCR and WRAP translations are calcuated in independently, select the one
// for our transactions
// right shift by the UI width to the DRAM width ratio
assign m_axaddr = (s_axburst == P_AXBURST_FIXED) ? s_axaddr :
(s_axburst == P_AXBURST_INCR) ? incr_cmd_byte_addr :
wrap_cmd_byte_addr;
assign incr_burst = (s_axburst[1]) ? 1'b0 : 1'b1;
// Indicates if we are on the first transaction of a mc translation with more
// than 1 transaction.
always @(posedge clk) begin
if (reset | s_axhandshake) begin
sel_first <= 1'b1;
end else if (next) begin
sel_first <= 1'b0;
end
end
always @( * ) begin
if (reset | s_axhandshake) begin
sel_first_i = 1'b1;
end else if (next) begin
sel_first_i = 1'b0;
end else begin
sel_first_i = sel_first;
end
end
assign next_pending = s_axburst[1] ? s_axburst_eq1 : s_axburst_eq0;
always @(posedge clk) begin
if (sel_first_i || s_axburst[1]) begin
s_axburst_eq1 <= wrap_next_pending;
end else begin
s_axburst_eq1 <= incr_next_pending;
end
if (sel_first_i || !s_axburst[1]) begin
s_axburst_eq0 <= incr_next_pending;
end else begin
s_axburst_eq0 <= wrap_next_pending;
end
end
axi_protocol_converter_v2_1_b2s_incr_cmd #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
)
incr_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( s_axaddr ) ,
.axlen ( s_axlen ) ,
.axsize ( s_axsize ) ,
.axhandshake ( s_axhandshake ) ,
.cmd_byte_addr ( incr_cmd_byte_addr ) ,
.next ( next ) ,
.next_pending ( incr_next_pending )
);
axi_protocol_converter_v2_1_b2s_wrap_cmd #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
)
wrap_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( s_axaddr ) ,
.axlen ( s_axlen ) ,
.axsize ( s_axsize ) ,
.axhandshake ( s_axhandshake ) ,
.cmd_byte_addr ( wrap_cmd_byte_addr ) ,
.next ( next ) ,
.next_pending ( wrap_next_pending )
);
endmodule |
module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output wire next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXBURST decodes
localparam P_AXBURST_FIXED = 2'b00;
localparam P_AXBURST_INCR = 2'b01;
localparam P_AXBURST_WRAP = 2'b10;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_AXI_ADDR_WIDTH-1:0] incr_cmd_byte_addr;
wire incr_next_pending;
wire [C_AXI_ADDR_WIDTH-1:0] wrap_cmd_byte_addr;
wire wrap_next_pending;
reg sel_first;
reg s_axburst_eq1;
reg s_axburst_eq0;
reg sel_first_i;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// INCR and WRAP translations are calcuated in independently, select the one
// for our transactions
// right shift by the UI width to the DRAM width ratio
assign m_axaddr = (s_axburst == P_AXBURST_FIXED) ? s_axaddr :
(s_axburst == P_AXBURST_INCR) ? incr_cmd_byte_addr :
wrap_cmd_byte_addr;
assign incr_burst = (s_axburst[1]) ? 1'b0 : 1'b1;
// Indicates if we are on the first transaction of a mc translation with more
// than 1 transaction.
always @(posedge clk) begin
if (reset | s_axhandshake) begin
sel_first <= 1'b1;
end else if (next) begin
sel_first <= 1'b0;
end
end
always @( * ) begin
if (reset | s_axhandshake) begin
sel_first_i = 1'b1;
end else if (next) begin
sel_first_i = 1'b0;
end else begin
sel_first_i = sel_first;
end
end
assign next_pending = s_axburst[1] ? s_axburst_eq1 : s_axburst_eq0;
always @(posedge clk) begin
if (sel_first_i || s_axburst[1]) begin
s_axburst_eq1 <= wrap_next_pending;
end else begin
s_axburst_eq1 <= incr_next_pending;
end
if (sel_first_i || !s_axburst[1]) begin
s_axburst_eq0 <= incr_next_pending;
end else begin
s_axburst_eq0 <= wrap_next_pending;
end
end
axi_protocol_converter_v2_1_b2s_incr_cmd #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
)
incr_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( s_axaddr ) ,
.axlen ( s_axlen ) ,
.axsize ( s_axsize ) ,
.axhandshake ( s_axhandshake ) ,
.cmd_byte_addr ( incr_cmd_byte_addr ) ,
.next ( next ) ,
.next_pending ( incr_next_pending )
);
axi_protocol_converter_v2_1_b2s_wrap_cmd #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
)
wrap_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( s_axaddr ) ,
.axlen ( s_axlen ) ,
.axsize ( s_axsize ) ,
.axhandshake ( s_axhandshake ) ,
.cmd_byte_addr ( wrap_cmd_byte_addr ) ,
.next ( next ) ,
.next_pending ( wrap_next_pending )
);
endmodule |
module adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
align = 4'd4,
add_0 = 4'd5,
add_1 = 4'd6,
normalise_1 = 4'd7,
normalise_2 = 4'd8,
round = 4'd9,
pack = 4'd10,
put_z = 4'd11;
reg [31:0] a, b, z;
reg [26:0] a_m, b_m;
reg [23:0] z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [27:0] sum;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= {a[22 : 0], 3'd0};
b_m <= {b[22 : 0], 3'd0};
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is inf return inf
end else if (b_e == 128) begin
z[31] <= b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if a is zero return b
end else if ((($signed(a_e) == -127) && (a_m == 0)) && (($signed(b_e) == -127) && (b_m == 0))) begin
z[31] <= a_s & b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
//if a is zero return b
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
//if b is zero return a
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s;
z[30:23] <= a_e[7:0] + 127;
z[22:0] <= a_m[26:3];
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[26] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[26] <= 1;
end
state <= align;
end
end
align:
begin
if ($signed(a_e) > $signed(b_e)) begin
b_e <= b_e + 1;
b_m <= b_m >> 1;
b_m[0] <= b_m[0] | b_m[1];
end else if ($signed(a_e) < $signed(b_e)) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
a_m[0] <= a_m[0] | a_m[1];
end else begin
state <= add_0;
end
end
add_0:
begin
z_e <= a_e;
if (a_s == b_s) begin
sum <= a_m + b_m;
z_s <= a_s;
end else begin
if (a_m >= b_m) begin
sum <= a_m - b_m;
z_s <= a_s;
end else begin
sum <= b_m - a_m;
z_s <= b_s;
end
end
state <= add_1;
end
add_1:
begin
if (sum[27]) begin
z_m <= sum[27:4];
guard <= sum[3];
round_bit <= sum[2];
sticky <= sum[1] | sum[0];
z_e <= z_e + 1;
end else begin
z_m <= sum[26:3];
guard <= sum[2];
round_bit <= sum[1];
sticky <= sum[0];
end
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
divide_0 = 4'd6,
divide_1 = 4'd7,
divide_2 = 4'd8,
divide_3 = 4'd9,
normalise_1 = 4'd10,
normalise_2 = 4'd11,
round = 4'd12,
pack = 4'd13,
put_z = 4'd14;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [50:0] quotient, divisor, dividend, remainder;
reg [5:0] count;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf and b is inf return NaN
end else if ((a_e == 128) && (b_e == 128)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is inf return zero
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is zero return inf
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= divide_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
divide_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e - b_e;
quotient <= 0;
remainder <= 0;
count <= 0;
dividend <= a_m << 27;
divisor <= b_m;
state <= divide_1;
end
divide_1:
begin
quotient <= quotient << 1;
remainder <= remainder << 1;
remainder[0] <= dividend[50];
dividend <= dividend << 1;
state <= divide_2;
end
divide_2:
begin
if (remainder >= divisor) begin
quotient[0] <= 1;
remainder <= remainder - divisor;
end
if (count == 49) begin
state <= divide_3;
end else begin
count <= count + 1;
state <= divide_1;
end
end
divide_3:
begin
z_m <= quotient[26:3];
guard <= quotient[2];
round_bit <= quotient[1];
sticky <= quotient[0] | (remainder != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
multiply_0 = 4'd6,
multiply_1 = 4'd7,
normalise_1 = 4'd8,
normalise_2 = 4'd9,
round = 4'd10,
pack = 4'd11,
put_z = 4'd12;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [49:0] product;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is inf return inf
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if b is zero return zero
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= multiply_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
multiply_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e + b_e + 1;
product <= a_m * b_m * 4;
state <= multiply_1;
end
multiply_1:
begin
z_m <= product[49:26];
guard <= product[25];
round_bit <= product[24];
sticky <= (product[23:0] != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module double_divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
divide_0 = 4'd6,
divide_1 = 4'd7,
divide_2 = 4'd8,
divide_3 = 4'd9,
normalise_1 = 4'd10,
normalise_2 = 4'd11,
round = 4'd12,
pack = 4'd13,
put_z = 4'd14;
reg [63:0] a, b, z;
reg [52:0] a_m, b_m, z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [108:0] quotient, divisor, dividend, remainder;
reg [6:0] count;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[51 : 0];
b_m <= b[51 : 0];
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf and b is inf return NaN
end else if ((a_e == 1024) && (b_e == 1024)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is inf return zero
end else if (b_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is zero return inf
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[52] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[52] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[52]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[52]) begin
state <= divide_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
divide_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e - b_e;
quotient <= 0;
remainder <= 0;
count <= 0;
dividend <= a_m << 56;
divisor <= b_m;
state <= divide_1;
end
divide_1:
begin
quotient <= quotient << 1;
remainder <= remainder << 1;
remainder[0] <= dividend[108];
dividend <= dividend << 1;
state <= divide_2;
end
divide_2:
begin
if (remainder >= divisor) begin
quotient[0] <= 1;
remainder <= remainder - divisor;
end
if (count == 107) begin
state <= divide_3;
end else begin
count <= count + 1;
state <= divide_1;
end
end
divide_3:
begin
z_m <= quotient[55:3];
guard <= quotient[2];
round_bit <= quotient[1];
sticky <= quotient[0] | (remainder != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0 && $signed(z_e) > -1022) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[10:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module double_multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
multiply_0 = 4'd6,
multiply_1 = 4'd7,
normalise_1 = 4'd8,
normalise_2 = 4'd9,
round = 4'd10,
pack = 4'd11,
put_z = 4'd12;
reg [63:0] a, b, z;
reg [52:0] a_m, b_m, z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [107:0] product;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[51 : 0];
b_m <= b[51 : 0];
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is inf return inf
end else if (b_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if b is zero return zero
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[52] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[52] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[52]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[52]) begin
state <= multiply_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
multiply_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e + b_e + 1;
product <= a_m * b_m * 4;
state <= multiply_1;
end
multiply_1:
begin
z_m <= product[107:55];
guard <= product[54];
round_bit <= product[53];
sticky <= (product[52:0] != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[11:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module double_adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
align = 4'd4,
add_0 = 4'd5,
add_1 = 4'd6,
normalise_1 = 4'd7,
normalise_2 = 4'd8,
round = 4'd9,
pack = 4'd10,
put_z = 4'd11;
reg [63:0] a, b, z;
reg [55:0] a_m, b_m;
reg [52:0] z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [56:0] sum;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= {a[51 : 0], 3'd0};
b_m <= {b[51 : 0], 3'd0};
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is inf return inf
end else if (b_e == 1024) begin
z[63] <= b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if a is zero return b
end else if ((($signed(a_e) == -1023) && (a_m == 0)) && (($signed(b_e) == -1023) && (b_m == 0))) begin
z[63] <= a_s & b_s;
z[62:52] <= b_e[10:0] + 1023;
z[51:0] <= b_m[55:3];
state <= put_z;
//if a is zero return b
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= b_s;
z[62:52] <= b_e[10:0] + 1023;
z[51:0] <= b_m[55:3];
state <= put_z;
//if b is zero return a
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s;
z[62:52] <= a_e[10:0] + 1023;
z[51:0] <= a_m[55:3];
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[55] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[55] <= 1;
end
state <= align;
end
end
align:
begin
if ($signed(a_e) > $signed(b_e)) begin
b_e <= b_e + 1;
b_m <= b_m >> 1;
b_m[0] <= b_m[0] | b_m[1];
end else if ($signed(a_e) < $signed(b_e)) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
a_m[0] <= a_m[0] | a_m[1];
end else begin
state <= add_0;
end
end
add_0:
begin
z_e <= a_e;
if (a_s == b_s) begin
sum <= {1'd0, a_m} + b_m;
z_s <= a_s;
end else begin
if (a_m > b_m) begin
sum <= {1'd0, a_m} - b_m;
z_s <= a_s;
end else begin
sum <= {1'd0, b_m} - a_m;
z_s <= b_s;
end
end
state <= add_1;
end
add_1:
begin
if (sum[56]) begin
z_m <= sum[56:4];
guard <= sum[3];
round_bit <= sum[2];
sticky <= sum[1] | sum[0];
z_e <= z_e + 1;
end else begin
z_m <= sum[55:3];
guard <= sum[2];
round_bit <= sum[1];
sticky <= sum[0];
end
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0 && $signed(z_e) > -1022) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'h1fffffffffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[10:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module int_to_float(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [2:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
convert_1 = 3'd2,
convert_2 = 3'd3,
round = 3'd4,
pack = 3'd5,
put_z = 3'd6;
reg [31:0] a, z, value;
reg [23:0] z_m;
reg [7:0] z_r;
reg [7:0] z_e;
reg z_s;
reg guard, round_bit, sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
if ( a == 0 ) begin
z_s <= 0;
z_m <= 0;
z_e <= -127;
state <= pack;
end else begin
value <= a[31] ? -a : a;
z_s <= a[31];
state <= convert_1;
end
end
convert_1:
begin
z_e <= 31;
z_m <= value[31:8];
z_r <= value[7:0];
state <= convert_2;
end
convert_2:
begin
if (!z_m[23]) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= z_r[7];
z_r <= z_r << 1;
end else begin
guard <= z_r[7];
round_bit <= z_r[6];
sticky <= z_r[5:0] != 0;
state <= round;
end
end
round:
begin
if (guard && (round_bit || sticky || z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e + 127;
z[31] <= z_s;
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module float_to_int(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg [2:0] state;
parameter get_a = 3'd0,
special_cases = 3'd1,
unpack = 3'd2,
convert = 3'd3,
put_z = 3'd4;
reg [31:0] a_m, a, z;
reg [8:0] a_e;
reg a_s;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m[31:8] <= {1'b1, a[22 : 0]};
a_m[7:0] <= 0;
a_e <= a[30 : 23] - 127;
a_s <= a[31];
state <= special_cases;
end
special_cases:
begin
if ($signed(a_e) == -127) begin
z <= 0;
state <= put_z;
end else if ($signed(a_e) > 31) begin
z <= 32'h80000000;
state <= put_z;
end else begin
state <= convert;
end
end
convert:
begin
if ($signed(a_e) < 31 && a_m) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
end else begin
if (a_m[31]) begin
z <= 32'h80000000;
end else begin
z <= a_s ? -a_m : a_m;
end
state <= put_z;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module long_to_double(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [2:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
convert_1 = 3'd2,
convert_2 = 3'd3,
round = 3'd4,
pack = 3'd5,
put_z = 3'd6;
reg [63:0] a, z, value;
reg [52:0] z_m;
reg [10:0] z_r;
reg [10:0] z_e;
reg z_s;
reg guard, round_bit, sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
if ( a == 0 ) begin
z_s <= 0;
z_m <= 0;
z_e <= -1023;
state <= pack;
end else begin
value <= a[63] ? -a : a;
z_s <= a[63];
state <= convert_1;
end
end
convert_1:
begin
z_e <= 63;
z_m <= value[63:11];
z_r <= value[10:0];
state <= convert_2;
end
convert_2:
begin
if (!z_m[52]) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= z_r[10];
z_r <= z_r << 1;
end else begin
guard <= z_r[10];
round_bit <= z_r[9];
sticky <= z_r[8:0] != 0;
state <= round;
end
end
round:
begin
if (guard && (round_bit || sticky || z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'h1fffffffffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e + 1023;
z[63] <= z_s;
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module double_to_long(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg [2:0] state;
parameter get_a = 3'd0,
special_cases = 3'd1,
unpack = 3'd2,
convert = 3'd3,
put_z = 3'd4;
reg [63:0] a_m, a, z;
reg [11:0] a_e;
reg a_s;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m[63:11] <= {1'b1, a[51 : 0]};
a_m[10:0] <= 0;
a_e <= a[62 : 52] - 1023;
a_s <= a[63];
state <= special_cases;
end
special_cases:
begin
if ($signed(a_e) == -1023) begin
//zero
z <= 0;
state <= put_z;
end else if ($signed(a_e) == 1024 && a[51:0] != 0) begin
//nan
z <= 64'h8000000000000000;
state <= put_z;
end else if ($signed(a_e) > 63) begin
//too big
if (a_s) begin
z <= 64'h8000000000000000;
end else begin
z <= 64'h0000000000000000;
end
state <= put_z;
end else begin
state <= convert;
end
end
convert:
begin
if ($signed(a_e) < 63 && a_m) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
end else begin
if (a_m[63] && a_s) begin
z <= 64'h8000000000000000;
end else begin
z <= a_s ? -a_m : a_m;
end
state <= put_z;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module float_to_double(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [1:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
normalise_0 = 3'd2,
put_z = 3'd3;
reg [63:0] z;
reg [10:0] z_e;
reg [52:0] z_m;
reg [31:0] a;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
z[63] <= a[31];
z[62:52] <= (a[30:23] - 127) + 1023;
z[51:0] <= {a[22:0], 29'd0};
if (a[30:23] == 255) begin
z[62:52] <= 2047;
end
state <= put_z;
if (a[30:23] == 0) begin
if (a[23:0]) begin
state <= normalise_0;
z_e <= 897;
z_m <= {1'd0, a[22:0], 29'd0};
end
z[62:52] <= 0;
end
end
normalise_0:
begin
if (z_m[52]) begin
z[62:52] <= z_e;
z[51:0] <= z_m[51:0];
state <= put_z;
end else begin
z_m <= {z_m[51:0], 1'd0};
z_e <= z_e - 1;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module double_to_float(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg [1:0] state;
parameter get_a = 3'd0,
unpack = 3'd1,
denormalise = 3'd2,
put_z = 3'd3;
reg [63:0] a;
reg [31:0] z;
reg [10:0] z_e;
reg [23:0] z_m;
reg guard;
reg round;
reg sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
z[31] <= a[63];
state <= put_z;
if (a[62:52] == 0) begin
z[30:23] <= 0;
z[22:0] <= 0;
end else if (a[62:52] < 897) begin
z[30:23] <= 0;
z_m <= {1'd1, a[51:29]};
z_e <= a[62:52];
guard <= a[28];
round <= a[27];
sticky <= a[26:0] != 0;
state <= denormalise;
end else if (a[62:52] == 2047) begin
z[30:23] <= 255;
z[22:0] <= 0;
if (a[51:0]) begin
z[22] <= 1;
end
end else if (a[62:52] > 1150) begin
z[30:23] <= 255;
z[22:0] <= 0;
end else begin
z[30:23] <= (a[62:52] - 1023) + 127;
if (a[28] && (a[27] || a[26:0])) begin
z[22:0] <= a[51:29] + 1;
end else begin
z[22:0] <= a[51:29];
end
end
end
denormalise:
begin
if (z_e == 897 || (z_m == 0 && guard == 0)) begin
state <= put_z;
z[22:0] <= z_m;
if (guard && (round || sticky)) begin
z[22:0] <= z_m + 1;
end
end else begin
z_e <= z_e + 1;
z_m <= {1'd0, z_m[23:1]};
guard <= z_m[0];
round <= guard;
sticky <= sticky | round;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
align = 4'd4,
add_0 = 4'd5,
add_1 = 4'd6,
normalise_1 = 4'd7,
normalise_2 = 4'd8,
round = 4'd9,
pack = 4'd10,
put_z = 4'd11;
reg [31:0] a, b, z;
reg [26:0] a_m, b_m;
reg [23:0] z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [27:0] sum;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= {a[22 : 0], 3'd0};
b_m <= {b[22 : 0], 3'd0};
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is inf return inf
end else if (b_e == 128) begin
z[31] <= b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if a is zero return b
end else if ((($signed(a_e) == -127) && (a_m == 0)) && (($signed(b_e) == -127) && (b_m == 0))) begin
z[31] <= a_s & b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
//if a is zero return b
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
//if b is zero return a
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s;
z[30:23] <= a_e[7:0] + 127;
z[22:0] <= a_m[26:3];
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[26] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[26] <= 1;
end
state <= align;
end
end
align:
begin
if ($signed(a_e) > $signed(b_e)) begin
b_e <= b_e + 1;
b_m <= b_m >> 1;
b_m[0] <= b_m[0] | b_m[1];
end else if ($signed(a_e) < $signed(b_e)) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
a_m[0] <= a_m[0] | a_m[1];
end else begin
state <= add_0;
end
end
add_0:
begin
z_e <= a_e;
if (a_s == b_s) begin
sum <= a_m + b_m;
z_s <= a_s;
end else begin
if (a_m >= b_m) begin
sum <= a_m - b_m;
z_s <= a_s;
end else begin
sum <= b_m - a_m;
z_s <= b_s;
end
end
state <= add_1;
end
add_1:
begin
if (sum[27]) begin
z_m <= sum[27:4];
guard <= sum[3];
round_bit <= sum[2];
sticky <= sum[1] | sum[0];
z_e <= z_e + 1;
end else begin
z_m <= sum[26:3];
guard <= sum[2];
round_bit <= sum[1];
sticky <= sum[0];
end
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
divide_0 = 4'd6,
divide_1 = 4'd7,
divide_2 = 4'd8,
divide_3 = 4'd9,
normalise_1 = 4'd10,
normalise_2 = 4'd11,
round = 4'd12,
pack = 4'd13,
put_z = 4'd14;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [50:0] quotient, divisor, dividend, remainder;
reg [5:0] count;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf and b is inf return NaN
end else if ((a_e == 128) && (b_e == 128)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is inf return zero
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is zero return inf
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= divide_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
divide_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e - b_e;
quotient <= 0;
remainder <= 0;
count <= 0;
dividend <= a_m << 27;
divisor <= b_m;
state <= divide_1;
end
divide_1:
begin
quotient <= quotient << 1;
remainder <= remainder << 1;
remainder[0] <= dividend[50];
dividend <= dividend << 1;
state <= divide_2;
end
divide_2:
begin
if (remainder >= divisor) begin
quotient[0] <= 1;
remainder <= remainder - divisor;
end
if (count == 49) begin
state <= divide_3;
end else begin
count <= count + 1;
state <= divide_1;
end
end
divide_3:
begin
z_m <= quotient[26:3];
guard <= quotient[2];
round_bit <= quotient[1];
sticky <= quotient[0] | (remainder != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
multiply_0 = 4'd6,
multiply_1 = 4'd7,
normalise_1 = 4'd8,
normalise_2 = 4'd9,
round = 4'd10,
pack = 4'd11,
put_z = 4'd12;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [49:0] product;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is inf return inf
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if b is zero return zero
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= multiply_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
multiply_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e + b_e + 1;
product <= a_m * b_m * 4;
state <= multiply_1;
end
multiply_1:
begin
z_m <= product[49:26];
guard <= product[25];
round_bit <= product[24];
sticky <= (product[23:0] != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module double_divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
divide_0 = 4'd6,
divide_1 = 4'd7,
divide_2 = 4'd8,
divide_3 = 4'd9,
normalise_1 = 4'd10,
normalise_2 = 4'd11,
round = 4'd12,
pack = 4'd13,
put_z = 4'd14;
reg [63:0] a, b, z;
reg [52:0] a_m, b_m, z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [108:0] quotient, divisor, dividend, remainder;
reg [6:0] count;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[51 : 0];
b_m <= b[51 : 0];
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf and b is inf return NaN
end else if ((a_e == 1024) && (b_e == 1024)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is inf return zero
end else if (b_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is zero return inf
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[52] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[52] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[52]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[52]) begin
state <= divide_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
divide_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e - b_e;
quotient <= 0;
remainder <= 0;
count <= 0;
dividend <= a_m << 56;
divisor <= b_m;
state <= divide_1;
end
divide_1:
begin
quotient <= quotient << 1;
remainder <= remainder << 1;
remainder[0] <= dividend[108];
dividend <= dividend << 1;
state <= divide_2;
end
divide_2:
begin
if (remainder >= divisor) begin
quotient[0] <= 1;
remainder <= remainder - divisor;
end
if (count == 107) begin
state <= divide_3;
end else begin
count <= count + 1;
state <= divide_1;
end
end
divide_3:
begin
z_m <= quotient[55:3];
guard <= quotient[2];
round_bit <= quotient[1];
sticky <= quotient[0] | (remainder != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0 && $signed(z_e) > -1022) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[10:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module double_multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
multiply_0 = 4'd6,
multiply_1 = 4'd7,
normalise_1 = 4'd8,
normalise_2 = 4'd9,
round = 4'd10,
pack = 4'd11,
put_z = 4'd12;
reg [63:0] a, b, z;
reg [52:0] a_m, b_m, z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [107:0] product;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[51 : 0];
b_m <= b[51 : 0];
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is inf return inf
end else if (b_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if b is zero return zero
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[52] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[52] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[52]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[52]) begin
state <= multiply_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
multiply_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e + b_e + 1;
product <= a_m * b_m * 4;
state <= multiply_1;
end
multiply_1:
begin
z_m <= product[107:55];
guard <= product[54];
round_bit <= product[53];
sticky <= (product[52:0] != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[11:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module double_adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
align = 4'd4,
add_0 = 4'd5,
add_1 = 4'd6,
normalise_1 = 4'd7,
normalise_2 = 4'd8,
round = 4'd9,
pack = 4'd10,
put_z = 4'd11;
reg [63:0] a, b, z;
reg [55:0] a_m, b_m;
reg [52:0] z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [56:0] sum;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= {a[51 : 0], 3'd0};
b_m <= {b[51 : 0], 3'd0};
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is inf return inf
end else if (b_e == 1024) begin
z[63] <= b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if a is zero return b
end else if ((($signed(a_e) == -1023) && (a_m == 0)) && (($signed(b_e) == -1023) && (b_m == 0))) begin
z[63] <= a_s & b_s;
z[62:52] <= b_e[10:0] + 1023;
z[51:0] <= b_m[55:3];
state <= put_z;
//if a is zero return b
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= b_s;
z[62:52] <= b_e[10:0] + 1023;
z[51:0] <= b_m[55:3];
state <= put_z;
//if b is zero return a
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s;
z[62:52] <= a_e[10:0] + 1023;
z[51:0] <= a_m[55:3];
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[55] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[55] <= 1;
end
state <= align;
end
end
align:
begin
if ($signed(a_e) > $signed(b_e)) begin
b_e <= b_e + 1;
b_m <= b_m >> 1;
b_m[0] <= b_m[0] | b_m[1];
end else if ($signed(a_e) < $signed(b_e)) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
a_m[0] <= a_m[0] | a_m[1];
end else begin
state <= add_0;
end
end
add_0:
begin
z_e <= a_e;
if (a_s == b_s) begin
sum <= {1'd0, a_m} + b_m;
z_s <= a_s;
end else begin
if (a_m > b_m) begin
sum <= {1'd0, a_m} - b_m;
z_s <= a_s;
end else begin
sum <= {1'd0, b_m} - a_m;
z_s <= b_s;
end
end
state <= add_1;
end
add_1:
begin
if (sum[56]) begin
z_m <= sum[56:4];
guard <= sum[3];
round_bit <= sum[2];
sticky <= sum[1] | sum[0];
z_e <= z_e + 1;
end else begin
z_m <= sum[55:3];
guard <= sum[2];
round_bit <= sum[1];
sticky <= sum[0];
end
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0 && $signed(z_e) > -1022) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'h1fffffffffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[10:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module int_to_float(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [2:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
convert_1 = 3'd2,
convert_2 = 3'd3,
round = 3'd4,
pack = 3'd5,
put_z = 3'd6;
reg [31:0] a, z, value;
reg [23:0] z_m;
reg [7:0] z_r;
reg [7:0] z_e;
reg z_s;
reg guard, round_bit, sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
if ( a == 0 ) begin
z_s <= 0;
z_m <= 0;
z_e <= -127;
state <= pack;
end else begin
value <= a[31] ? -a : a;
z_s <= a[31];
state <= convert_1;
end
end
convert_1:
begin
z_e <= 31;
z_m <= value[31:8];
z_r <= value[7:0];
state <= convert_2;
end
convert_2:
begin
if (!z_m[23]) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= z_r[7];
z_r <= z_r << 1;
end else begin
guard <= z_r[7];
round_bit <= z_r[6];
sticky <= z_r[5:0] != 0;
state <= round;
end
end
round:
begin
if (guard && (round_bit || sticky || z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e + 127;
z[31] <= z_s;
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module float_to_int(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg [2:0] state;
parameter get_a = 3'd0,
special_cases = 3'd1,
unpack = 3'd2,
convert = 3'd3,
put_z = 3'd4;
reg [31:0] a_m, a, z;
reg [8:0] a_e;
reg a_s;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m[31:8] <= {1'b1, a[22 : 0]};
a_m[7:0] <= 0;
a_e <= a[30 : 23] - 127;
a_s <= a[31];
state <= special_cases;
end
special_cases:
begin
if ($signed(a_e) == -127) begin
z <= 0;
state <= put_z;
end else if ($signed(a_e) > 31) begin
z <= 32'h80000000;
state <= put_z;
end else begin
state <= convert;
end
end
convert:
begin
if ($signed(a_e) < 31 && a_m) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
end else begin
if (a_m[31]) begin
z <= 32'h80000000;
end else begin
z <= a_s ? -a_m : a_m;
end
state <= put_z;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module long_to_double(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [2:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
convert_1 = 3'd2,
convert_2 = 3'd3,
round = 3'd4,
pack = 3'd5,
put_z = 3'd6;
reg [63:0] a, z, value;
reg [52:0] z_m;
reg [10:0] z_r;
reg [10:0] z_e;
reg z_s;
reg guard, round_bit, sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
if ( a == 0 ) begin
z_s <= 0;
z_m <= 0;
z_e <= -1023;
state <= pack;
end else begin
value <= a[63] ? -a : a;
z_s <= a[63];
state <= convert_1;
end
end
convert_1:
begin
z_e <= 63;
z_m <= value[63:11];
z_r <= value[10:0];
state <= convert_2;
end
convert_2:
begin
if (!z_m[52]) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= z_r[10];
z_r <= z_r << 1;
end else begin
guard <= z_r[10];
round_bit <= z_r[9];
sticky <= z_r[8:0] != 0;
state <= round;
end
end
round:
begin
if (guard && (round_bit || sticky || z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'h1fffffffffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e + 1023;
z[63] <= z_s;
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module double_to_long(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg [2:0] state;
parameter get_a = 3'd0,
special_cases = 3'd1,
unpack = 3'd2,
convert = 3'd3,
put_z = 3'd4;
reg [63:0] a_m, a, z;
reg [11:0] a_e;
reg a_s;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m[63:11] <= {1'b1, a[51 : 0]};
a_m[10:0] <= 0;
a_e <= a[62 : 52] - 1023;
a_s <= a[63];
state <= special_cases;
end
special_cases:
begin
if ($signed(a_e) == -1023) begin
//zero
z <= 0;
state <= put_z;
end else if ($signed(a_e) == 1024 && a[51:0] != 0) begin
//nan
z <= 64'h8000000000000000;
state <= put_z;
end else if ($signed(a_e) > 63) begin
//too big
if (a_s) begin
z <= 64'h8000000000000000;
end else begin
z <= 64'h0000000000000000;
end
state <= put_z;
end else begin
state <= convert;
end
end
convert:
begin
if ($signed(a_e) < 63 && a_m) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
end else begin
if (a_m[63] && a_s) begin
z <= 64'h8000000000000000;
end else begin
z <= a_s ? -a_m : a_m;
end
state <= put_z;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module float_to_double(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [1:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
normalise_0 = 3'd2,
put_z = 3'd3;
reg [63:0] z;
reg [10:0] z_e;
reg [52:0] z_m;
reg [31:0] a;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
z[63] <= a[31];
z[62:52] <= (a[30:23] - 127) + 1023;
z[51:0] <= {a[22:0], 29'd0};
if (a[30:23] == 255) begin
z[62:52] <= 2047;
end
state <= put_z;
if (a[30:23] == 0) begin
if (a[23:0]) begin
state <= normalise_0;
z_e <= 897;
z_m <= {1'd0, a[22:0], 29'd0};
end
z[62:52] <= 0;
end
end
normalise_0:
begin
if (z_m[52]) begin
z[62:52] <= z_e;
z[51:0] <= z_m[51:0];
state <= put_z;
end else begin
z_m <= {z_m[51:0], 1'd0};
z_e <= z_e - 1;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module double_to_float(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg [1:0] state;
parameter get_a = 3'd0,
unpack = 3'd1,
denormalise = 3'd2,
put_z = 3'd3;
reg [63:0] a;
reg [31:0] z;
reg [10:0] z_e;
reg [23:0] z_m;
reg guard;
reg round;
reg sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
z[31] <= a[63];
state <= put_z;
if (a[62:52] == 0) begin
z[30:23] <= 0;
z[22:0] <= 0;
end else if (a[62:52] < 897) begin
z[30:23] <= 0;
z_m <= {1'd1, a[51:29]};
z_e <= a[62:52];
guard <= a[28];
round <= a[27];
sticky <= a[26:0] != 0;
state <= denormalise;
end else if (a[62:52] == 2047) begin
z[30:23] <= 255;
z[22:0] <= 0;
if (a[51:0]) begin
z[22] <= 1;
end
end else if (a[62:52] > 1150) begin
z[30:23] <= 255;
z[22:0] <= 0;
end else begin
z[30:23] <= (a[62:52] - 1023) + 127;
if (a[28] && (a[27] || a[26:0])) begin
z[22:0] <= a[51:29] + 1;
end else begin
z[22:0] <= a[51:29];
end
end
end
denormalise:
begin
if (z_e == 897 || (z_m == 0 && guard == 0)) begin
state <= put_z;
z[22:0] <= z_m;
if (guard && (round || sticky)) begin
z[22:0] <= z_m + 1;
end
end else begin
z_e <= z_e + 1;
z_m <= {1'd0, z_m[23:1]};
guard <= z_m[0];
round <= guard;
sticky <= sticky | round;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule |
module testbed_lo_read;
reg pck0;
reg [7:0] adc_d;
reg lo_is_125khz;
reg [15:0] divisor;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
lo_read #(5,10) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.lo_is_125khz(lo_is_125khz),
.divisor(divisor)
);
integer idx, i, adc_val=8;
// main clock
always #5 pck0 = !pck0;
task crank_dut;
begin
@(posedge adc_clk) ;
adc_d = adc_val;
adc_val = (adc_val *2) + 53;
end
endtask
initial begin
// init inputs
pck0 = 0;
adc_d = 0;
ssp_dout = 0;
lo_is_125khz = 1;
divisor = 255; //min 16, 95=125Khz, max 255
// simulate 4 A/D cycles at 125Khz
for (i = 0 ; i < 8 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule |
module testbed_lo_read;
reg pck0;
reg [7:0] adc_d;
reg lo_is_125khz;
reg [15:0] divisor;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
lo_read #(5,10) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.lo_is_125khz(lo_is_125khz),
.divisor(divisor)
);
integer idx, i, adc_val=8;
// main clock
always #5 pck0 = !pck0;
task crank_dut;
begin
@(posedge adc_clk) ;
adc_d = adc_val;
adc_val = (adc_val *2) + 53;
end
endtask
initial begin
// init inputs
pck0 = 0;
adc_d = 0;
ssp_dout = 0;
lo_is_125khz = 1;
divisor = 255; //min 16, 95=125Khz, max 255
// simulate 4 A/D cycles at 125Khz
for (i = 0 ; i < 8 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule |
module testbed_lo_read;
reg pck0;
reg [7:0] adc_d;
reg lo_is_125khz;
reg [15:0] divisor;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
lo_read #(5,10) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.lo_is_125khz(lo_is_125khz),
.divisor(divisor)
);
integer idx, i, adc_val=8;
// main clock
always #5 pck0 = !pck0;
task crank_dut;
begin
@(posedge adc_clk) ;
adc_d = adc_val;
adc_val = (adc_val *2) + 53;
end
endtask
initial begin
// init inputs
pck0 = 0;
adc_d = 0;
ssp_dout = 0;
lo_is_125khz = 1;
divisor = 255; //min 16, 95=125Khz, max 255
// simulate 4 A/D cycles at 125Khz
for (i = 0 ; i < 8 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule |
module testbed_lo_read;
reg pck0;
reg [7:0] adc_d;
reg lo_is_125khz;
reg [15:0] divisor;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
lo_read #(5,10) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.lo_is_125khz(lo_is_125khz),
.divisor(divisor)
);
integer idx, i, adc_val=8;
// main clock
always #5 pck0 = !pck0;
task crank_dut;
begin
@(posedge adc_clk) ;
adc_d = adc_val;
adc_val = (adc_val *2) + 53;
end
endtask
initial begin
// init inputs
pck0 = 0;
adc_d = 0;
ssp_dout = 0;
lo_is_125khz = 1;
divisor = 255; //min 16, 95=125Khz, max 255
// simulate 4 A/D cycles at 125Khz
for (i = 0 ; i < 8 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule |
module soc_design_niosII_core_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule |
module soc_design_niosII_core_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule |
module soc_design_niosII_core_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule |
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule |
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule |
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule |
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0] sysclk_sreg;
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end
endmodule |
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0] sysclk_sreg;
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end
endmodule |
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0] sysclk_sreg;
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end
endmodule |
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0] sysclk_sreg;
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end
endmodule |
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule |
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule |
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule |
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule |
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule |
module or1200_ic_ram(
// Clock and reset
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, dataout
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_ICINDX;
//
// I/O
//
input clk;
input rst;
input [aw-1:0] addr;
input en;
input [3:0] we;
input [dw-1:0] datain;
output [dw-1:0] dataout;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
`ifdef OR1200_NO_IC
//
// Insn cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of IC RAM block
//
`ifdef OR1200_IC_1W_512B
or1200_spram_128x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_4KB
or1200_spram_1024x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_8KB
or1200_spram_2048x32 ic_ram0(
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
.ce(en),
.we(we[0]),
.oe(1'b1),
.addr(addr),
.di(datain),
.doq(dataout)
);
`endif
endmodule |
module m_port_ultra_quickhull
(
input clk,
input reset_n,
input processorEnable,
input [4095:0] points, //4096 / (8 * 2) = 256 points in each set
input [8:0] SS,
output [4095:0] convexPointsOutput,
output [7:0] convexSetSizeOutput
); //Same as points, 256 points
// Variables
localparam PTSIZE = 16; //Point Size: 16 bits long, two 8 bit dimensions
localparam LNSIZE = 32; //Line Size = 2 coordinates: 32 bits long
// localparam SS = 256; //Set Size, need to count up to 256 = 8 bits
reg [LNSIZE * 256 - 1 : 0] lineFIFO; //32 bits * number of points, just to be safe (100 points)
reg [15:0] lnIndex; //Line Index: only need 13 bits, but 16 just in case
reg [15:0] cxIndex; //Convex Index;only need 12 bits, but 16 just in case
reg [15:0] ptIndex;
reg [8:0] ptCount;
reg [4096:0] convexPoints;
reg [7:0] convexSetSize;
reg [PTSIZE - 1 : 0] xMinPoint;
reg [PTSIZE - 1 : 0] xMaxPoint;
reg [LNSIZE:0] line;
reg [8:0] positiveCrossCount;
reg [PTSIZE - 1 : 0] furthest;
reg [PTSIZE - 1 : 0] currPoint;
reg [(PTSIZE / 2) - 1 : 0] currPoint_X;
reg [(PTSIZE / 2) - 1 : 0] currPoint_Y;
reg [LNSIZE - 1 : 0] currLine;
reg [PTSIZE - 1 : 0] currLine_A;
reg [(PTSIZE / 2) - 1 : 0] currLine_AX;
reg [(PTSIZE / 2) - 1 : 0] currLine_AY;
reg [PTSIZE - 1 : 0] currLine_B;
reg [(PTSIZE / 2) - 1 : 0] currLine_BX;
reg [(PTSIZE / 2) - 1 : 0] currLine_BY;
reg signed [31:0] crossValue;
reg signed [31:0] furthestCrossValue;
reg [LNSIZE - 1: 0] nextLineAddr;
reg [LNSIZE - 1: 0] nextLineAddr2;
reg [PTSIZE - 1: 0] nextCXAddr;
reg [PTSIZE - 1: 0] nextCXAddr2;
reg furthestFlag;
// Output assignment
assign convexSetSizeOutput = convexSetSize;
assign convexPointsOutput = convexPoints;
// State Machine Implementation
reg[6:0] state;
assign { QEND, QHULL_RECURSE, QCROSS, QHULL_START, QFIND_MIN, QFIND_MAX, QINITIAL } = state;
localparam
INITIAL = 7'b0000001,
FIND_XMAX = 7'b0000010,
FIND_XMIN = 7'b0000100,
HULL_START = 7'b0001000,
CROSS = 7'b0010000,
HULL_RECURSE = 7'b0100000,
END = 7'b1000000;
// For loop integers
integer i;
integer j;
generate
always @(clk) begin
j = 0;
for (i = ptIndex; i < ptIndex + PTSIZE; i = i + 1) begin
currPoint[j] = points[i];
j = j + 1;
end
end
endgenerate
generate
always @(clk) begin
j = 0;
for (i = ptIndex; i < ptIndex + (PTSIZE / 2); i = i + 1) begin
currPoint_X[j] = points[i];
j = j + 1;
end
end
endgenerate
generate
always @(clk) begin
j = 0;
for (i = ptIndex + (PTSIZE / 2); i < ptIndex + PTSIZE; i = i + 1) begin
currPoint_Y[j] = points[i];
j = j + 1;
end
end
endgenerate
generate
always @(clk) begin
j = 0;
for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin
currLine[j] = lineFIFO[i];
j = j + 1;
end
end
endgenerate
generate
always @(clk) begin
j = 0;
for (i = lnIndex; i < lnIndex + (LNSIZE/2); i = i + 1) begin
currLine_A[j] = lineFIFO[i];
j = j + 1;
end
end
endgenerate
generate
always @(clk) begin
j = 0;
for (i = lnIndex; i < lnIndex + (PTSIZE/2); i = i + 1) begin
currLine_AX[j] = lineFIFO[i];
j = j + 1;
end
end
endgenerate
generate
always @(clk) begin
j = 0;
for (i = lnIndex + (PTSIZE / 2); i < lnIndex + PTSIZE; i = i + 1) begin
currLine_AY[j] = lineFIFO[i];
j = j + 1;
end
end
endgenerate
generate
always @(clk) begin
j = 0;
for (i = lnIndex + (LNSIZE/2); i < lnIndex + LNSIZE; i = i + 1) begin
currLine_B [j] = lineFIFO[i];
j = j + 1;
end
end
endgenerate
generate
always @(clk) begin
j = 0;
for (i = lnIndex + PTSIZE; i < lnIndex + LNSIZE - (PTSIZE/2); i = i + 1) begin
currLine_BX[j] = lineFIFO[i];
j = j + 1;
end
end
endgenerate
generate
always @(clk) begin
j = 0;
for (i = lnIndex + LNSIZE - (PTSIZE / 2); i < lnIndex + LNSIZE; i = i + 1) begin
currLine_BY[j] = lineFIFO[i];
j = j + 1;
end
end
endgenerate
//NSL, register assignents, and State Machine
always @(posedge clk, negedge reset_n) begin
ptIndex = PTSIZE * ptCount;
/*
for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin
nextLineAddr[j] = lineFIFO[i];
j = j + 1;
end
j = 0;
for (i = lnIndex + LNSIZE; i < lnIndex + (LNSIZE * 2); i = i + 1) begin
nextLineAddr2[j] = lineFIFO[i];
j = j + 1;
end
j = 0;
for (i = cxIndex; i < cxIndex + PTSIZE; i = i + 1) begin
nextCXAddr[j] = convexPoints[i];
j = j + 1;
end
j = 0;
for (i = cxIndex + PTSIZE; i < cxIndex + (PTSIZE * 2); i = i + 1) begin
nextCXAddr2[j] = convexPoints[i];
j = j + 1;
end
*/
crossValue = (((currLine_AX - currPoint_X) * (currLine_BY - currPoint_Y)) - ((currLine_AY - currPoint_Y) * (currLine_BX - currPoint_X)));
if (!reset_n) begin
//Reset
state <= INITIAL;
end
case (state)
INITIAL: begin
// State Logic
lineFIFO <= 0;
lnIndex <= 32;
cxIndex <= 0;
line <= 0;
ptIndex <= 0;
ptCount <= 0;
positiveCrossCount <= 0;
xMinPoint <= 0;
xMaxPoint <= 0;
crossValue <= 0;
furthest <= 0;
furthestCrossValue <= 0;
furthestFlag <= 0;
convexSetSize <= 0;
convexPoints <= 0;
// NSL
if (processorEnable) begin
state <= FIND_XMAX;
end
end
FIND_XMAX: begin
//State Logic
if (ptCount == 0) begin
xMaxPoint <= currPoint;
end
else begin
if (xMaxPoint < currPoint) begin
xMaxPoint <= currPoint;
end
else begin
//Do nothing
end
end
//NSL
if (ptCount != (SS - 1)) begin
ptCount <= ptCount + 1;
state <= FIND_XMAX;
end
else begin
ptCount <= 0;
state <= FIND_XMIN;
end
end
FIND_XMIN: begin
//State Logic
if (ptCount == 0) begin
xMinPoint <= currPoint;
end
else begin
if (xMinPoint > currPoint) begin
xMinPoint <= currPoint;
end
else begin
//Do nothing
end
end
//NSL
if (ptCount != (SS - 1)) begin
ptCount <= ptCount + 1;
state <= FIND_XMIN;
end
else begin
ptCount <= 0;
state <= HULL_START;
end
end
HULL_START: begin
// State Logic
nextLineAddr = {xMinPoint, xMaxPoint};
j = 0;
for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin
lineFIFO[i] = nextLineAddr[j];
j = j + 1;
end
nextLineAddr2 = {xMaxPoint, xMinPoint};
j = 0;
for (i = lnIndex + LNSIZE; i < lnIndex + (LNSIZE * 2); i = i + 1) begin
lineFIFO[i] = nextLineAddr2[j];
j = j + 1;
end
lnIndex <= lnIndex + LNSIZE;
// NSL
ptCount <= 0;
state <= CROSS;
end
CROSS: begin
//State Logic
//if (crossValue > 0) begin
if (crossValue > 0 && ptCount != (SS)) begin
positiveCrossCount <= positiveCrossCount + 1;
if (furthestFlag == 0) begin
furthestCrossValue <= crossValue;
furthest <= currPoint;
furthestFlag <= 1;
end
else begin
if (furthestCrossValue < crossValue) begin
furthestCrossValue <= crossValue;
furthest <= currPoint;
end
end
end
//NSL
if (ptCount != (SS)) begin
ptCount <= ptCount + 1;
state <= CROSS;
end
else begin
ptCount <= 0;
furthestFlag <= 0;
state <= HULL_RECURSE;
end
end
HULL_RECURSE: begin
// State Logic
//TODO: get number of positive cross and furthest point
if (positiveCrossCount == 1 && lnIndex != 0) begin
nextCXAddr = currLine_A;
j = 0;
for (i = cxIndex; i < cxIndex + PTSIZE; i = i + 1) begin
convexPoints[i] = nextCXAddr[j];
j = j + 1;
end
nextCXAddr2 = furthest;
j = 0;
for (i = cxIndex + PTSIZE; i < cxIndex + (PTSIZE * 2); i = i + 1) begin
convexPoints[i] = nextCXAddr2[j];
j = j + 1;
end
cxIndex <= cxIndex + (2 * PTSIZE);
convexSetSize <= convexSetSize + 2;
/*
//nextLineAddr <= 0;
for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin
lineFIFO[i] = 0;
j = j + 1;
end
*/
lnIndex <= lnIndex - LNSIZE;
end
else if (positiveCrossCount == 0 && lnIndex != 0) begin
nextCXAddr = currLine_A;
j = 0;
for (i = cxIndex; i < cxIndex + PTSIZE; i = i + 1) begin
convexPoints[i] = nextCXAddr[j];
j = j + 1;
end
cxIndex <= cxIndex + PTSIZE;
convexSetSize <= convexSetSize + 1;
/*
//nextLineAddr <= 0;
for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin
lineFIFO[i] = 0;
j = j + 1;
end
*/
lnIndex <= lnIndex - LNSIZE;
end
else begin
nextLineAddr = {furthest, currLine_A};
nextLineAddr2 = {currLine_B, furthest};
//nextLineAddr = {currLine_A[15],currLine_A[14],currLine_A[13],currLine_A[12],currLine_A[11],currLine_A[10],currLine_A[9],currLine_A[8],currLine_A[7],currLine_A[6],currLine_A[5],currLine_A[4],currLine_A[3],currLine_A[2],currLine_A[1],currLine_A[0],furthest[15],furthest[14],furthest[13],furthest[12],furthest[11],furthest[10],furthest[9],furthest[8],furthest[7],furthest[6],furthest[5],furthest[4],furthest[3],furthest[2],furthest[1],furthest[0]};
//nextLineAddr2 = {furthest[15],furthest[14],furthest[13],furthest[12],furthest[11],furthest[10],furthest[9],furthest[8],furthest[7],furthest[6],furthest[5],furthest[4],furthest[3],furthest[2],furthest[1],furthest[0],currLine_B[15],currLine_B[14],currLine_B[13],currLine_B[12],currLine_B[11],currLine_B[10],currLine_B[9],currLine_B[8],currLine_B[7],currLine_B[6],currLine_B[5],currLine_B[4],currLine_B[3],currLine_B[2],currLine_B[1],currLine_B[0]};
j = 0;
for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin
lineFIFO[i] = nextLineAddr[j];
j = j + 1;
end
j = 0;
for (i = lnIndex + LNSIZE; i < lnIndex + (LNSIZE * 2); i = i + 1) begin
lineFIFO[i] = nextLineAddr2[j];
j = j + 1;
end
lnIndex <= lnIndex + LNSIZE;
end
// NSL
if ((lnIndex) != 0) begin
positiveCrossCount <= 0;
furthest <= 0;
furthestCrossValue <= 0;
ptCount <= 0;
state <= CROSS;
end
else begin
state <= END;
end
end
END: begin
//Wait
end
endcase
end
endmodule |
module rx_descrambler #(
parameter DWIDTH=16,
parameter BITSLIP_SHIFT_RIGHT=1
)
(
input wire clk,
input wire res_n,
input wire bit_slip,
output reg locked,
input wire [DWIDTH-1:0] data_in,
output reg [DWIDTH-1:0] data_out
);
reg [14:0] lfsr; // LINEAR FEEDBACK SHIFT REGISTER
wire [14:0] lfsr_slipped; // Temporary lfsr for bitslip
wire [14:0] lfsr_steps [DWIDTH-1:0]; // LFSR values for serial time steps
wire [14:0] calculated_seed;
wire [DWIDTH-1:0] data_out_tmp;
generate
if(BITSLIP_SHIFT_RIGHT==1) begin
assign lfsr_slipped = { (lfsr_steps[DWIDTH-1][1] ^ lfsr_steps[DWIDTH-1][0]) , lfsr_steps[DWIDTH-1][14:1] };
end else begin
assign lfsr_slipped = { lfsr_steps[DWIDTH-1][13:0], (lfsr_steps[DWIDTH-1][14] ^ lfsr_steps[DWIDTH-1][0])};
end
endgenerate
// SEQUENTIAL PROCESS
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if (!res_n) begin
locked <= 1'b0;
lfsr <= 15'h0;
data_out <= {DWIDTH {1'b0}};
end else begin
data_out <= data_out_tmp;
if (!locked && |data_in) begin
lfsr <= calculated_seed;
// Locked when the calculated seeds match
if (calculated_seed == lfsr_steps[DWIDTH-1]) begin
locked <= 1'b1;
end
end else begin
if (bit_slip) begin
lfsr <= lfsr_slipped;
end else begin
lfsr <= lfsr_steps[DWIDTH-1];
end
end
end
end // serial shift right with left input
// SCRAMBLE
genvar j;
generate
localparam OFFSET = DWIDTH-15; // It breaks here if DWIDTH < 15
assign calculated_seed[14] = 1'b1; // Guess the top bit is 1
// data_in is the past state of the LFSR, so we can figure out
// the current value using a loop.
for(j = 0; j < 14; j = j + 1) begin : seed_calc
assign calculated_seed[j] = data_in[j+OFFSET] ^ data_in[j+OFFSET+1];
end
assign data_out_tmp [0] = data_in[0] ^ lfsr[0]; // single bit scrambled
assign lfsr_steps[0] = { (lfsr[1] ^ lfsr[0]) , lfsr[14:1] }; // lfsr at next bit clock
for(j = 1; j < DWIDTH; j = j + 1) begin : scrambler_gen
assign data_out_tmp[j] = data_in[j] ^ lfsr_steps[j-1][0];
assign lfsr_steps[j] = { (lfsr_steps[j-1][1] ^ lfsr_steps[j-1][0]) , lfsr_steps[j-1][14:1] };
end
endgenerate
endmodule |
module with zeros when the blank signal
// is high.
wire [10:0] write_addr = {!line_count0[0], pixel_count0[9:0]};
wire [10:0] read_addr = {line_count0[0], pixel_count0[9:0]};
wire write_enable = 1'b1; // write every clock posedge
reg [7:0] red_rainbow;
reg [7:0] green_rainbow;
reg [7:0] blue_rainbow;
// directions: 2'b00 == hold, 2'b01 == increase, 2'b10 == decrease
reg [1:0] red_direction;
reg [1:0] green_direction;
reg [1:0] blue_direction;
// compensate for the delay caused by displaying the previous line while
// calculating the current line by using a line counter that is one line
// ahead of the original line counter
always @ (posedge pixel_clock) begin
if ((line_count0 == (`V_TOTAL - 2)) & (pixel_count0 == (`H_TOTAL - 3)))
// last pixel in last line of frame, so reset line counter
line_count <= 10'h000;
else if (pixel_count0 == (`H_TOTAL - 3))
// last pixel but not last line, so increment line counter
line_count <= line_count + 1;
end
// compensate for putting the pixel_count generation and the code that
// checks it on the same clock edge
always @ (posedge pixel_clock) begin
if ((pixel_count0 == (`H_TOTAL - 3)))
// last pixel in last line of frame, so reset line counter
pixel_count <= 10'h000;
else
// last pixel but not last line, so increment line counter
pixel_count <= pixel_count + 1;
end
// cycle through all of the possible hues in a rainbow pattern
always @ (posedge pixel_clock) begin
// start last color bar at pure red
if (reset) begin
red_rainbow <= 8'hFF;
green_rainbow <= 8'h00;
blue_rainbow <= 8'h00;
red_direction <= 2'b00;
green_direction <= 2'b01;
blue_direction <= 2'b00;
end
else begin
// on the first line that is past the active region displayed,
// calculate the color for the last color bar
if ((pixel_count == 0) & (line_count == 480)) begin
if (red_direction[0]) begin
if (red_rainbow == 8'hFF) begin
red_direction <= 2'b00;
blue_direction <= 2'b10;
end
else
red_rainbow <= red_rainbow + 8'h01;
end
if (red_direction[1]) begin
if (red_rainbow == 8'h00) begin
red_direction <= 2'b00;
blue_direction <= 2'b01;
end
else
red_rainbow <= red_rainbow - 8'h01;
end
if (green_direction[0]) begin
if (green_rainbow == 8'hFF) begin
green_direction <= 2'b00;
red_direction <= 2'b10;
end
else
green_rainbow <= green_rainbow + 8'h01;
end
if (green_direction[1]) begin
if (green_rainbow == 8'h00) begin
green_direction <= 2'b00;
red_direction <= 2'b01;
end
else
green_rainbow <= green_rainbow - 8'h01;
end
if (blue_direction[0]) begin
if (blue_rainbow == 8'hFF) begin
blue_direction <= 2'b00;
green_direction <= 2'b10;
end
else
blue_rainbow <= blue_rainbow + 8'h01;
end
if (blue_direction[1]) begin
if (blue_rainbow == 8'h00) begin
blue_direction <= 2'b00;
green_direction <= 2'b01;
end
else
blue_rainbow <= blue_rainbow - 8'h01;
end
end
end
end
// select the color based on the horizontal position
always @ (posedge pixel_clock) begin
if (pixel_count < 79) begin //red
red_data <= 1'b1;
green_data <= 1'b0;
blue_data <= 1'b0;
end
else if ((pixel_count > 80) & (pixel_count < 159)) begin //yellow
red_data <= 1'b1;
green_data <= 1'b1;
blue_data <= 1'b0;
end
else if ((pixel_count > 160) & (pixel_count < 239)) begin //green
red_data <= 1'b0;
green_data <= 1'b1;
blue_data <= 1'b0;
end
else if ((pixel_count > 240) & (pixel_count < 319)) begin //cyan
red_data <= 1'b0;
green_data <= 1'b1;
blue_data <= 1'b1;
end
else if ((pixel_count > 320) & (pixel_count < 399)) begin //blue
red_data <= 1'b0;
green_data <= 1'b0;
blue_data <= 1'b1;
end
else if ((pixel_count > 400) & (pixel_count < 479)) begin //magenta
red_data <= 1'b1;
green_data <= 1'b0;
blue_data <= 1'b1;
end
else if ((pixel_count > 480) & (pixel_count < 559)) begin //white
red_data <= 1'b1;
green_data <= 1'b1;
blue_data <= 1'b1;
end
else if (pixel_count > 560) begin //rainbow pattern
red_data <= red_rainbow[7];
green_data <= green_rainbow[7];
blue_data <= blue_rainbow[7];
end
else begin //black
red_data <= 1'b0;
green_data <= 1'b0;
blue_data <= 1'b0;
end
end
// Instantiate the video RAM
VIDEO_RAM VIDEO_RAM
(
pixel_clock, // write clock
write_enable, // write eanble
write_addr, // write address
write_data, // write data
pixel_clock, // read clock
read_addr, // read address
read_data // read data
);
endmodule |
module READ_ROM32 ( input[4:0] ADDR ,output[31:0] DATA_RE,output[31:0] DATA_IM);
reg [31:0] re[0:31];
initial begin
re[0] = 32'h00000000;re[1] = 32'hFFE4CC88;re[2] = 32'h002DA5B3;re[3] = 32'hFFCE9932;
re[4] = 32'h00254173;re[5] = 32'hFFF2E19A;re[6] = 32'hFFF0C26D;re[7] = 32'h0026B1CD;
re[8] = 32'hFFCE4E3A;re[9] = 32'h002CB328;re[10] = 32'hFFE6AE85;re[11] = 32'hFFFDC9B2;
re[12] = 32'h001D07D3;re[13] = 32'hFFD17EA5;re[14] = 32'h00310311;re[15] = 32'hFFDC4195;
re[16] = 32'h000AF8A5;re[17] = 32'h0011551D;re[18] = 32'hFFD7F13F;re[19] = 32'h0031E3D5;
re[20] = 32'hFFD455CB;re[21] = 32'h001762CC;re[22] = 32'h00046B81;re[23] = 32'hFFE13261;
re[24] = 32'h002F45B3;re[25] = 32'hFFCF793E;re[26] = 32'h00222978;re[27] = 32'hFFF7329D;
re[28] = 32'hFFEC9C0A;re[29] = 32'h002957A0;re[30] = 32'hFFCE0320;re[31] = 32'h002A8B5D;
end
reg [31:0] im[0:31];
initial begin
im[0] = 32'h00000000;im[1] = 32'h00000000;im[2] = 32'h00000000;im[3] = 32'h00000000;
im[4] = 32'h00000000;im[5] = 32'h00000000;im[6] = 32'h00000000;im[7] = 32'h00000000;
im[8] = 32'h00000000;im[9] = 32'h00000000;im[10] = 32'h00000000;im[11] = 32'h00000000;
im[12] = 32'h00000000;im[13] = 32'h00000000;im[14] = 32'h00000000;im[15] = 32'h00000000;
im[16] = 32'h00000000;im[17] = 32'h00000000;im[18] = 32'h00000000;im[19] = 32'h00000000;
im[20] = 32'h00000000;im[21] = 32'h00000000;im[22] = 32'h00000000;im[23] = 32'h00000000;
im[24] = 32'h00000000;im[25] = 32'h00000000;im[26] = 32'h00000000;im[27] = 32'h00000000;
im[28] = 32'h00000000;im[29] = 32'h00000000;im[30] = 32'h00000000;im[31] = 32'h00000000;
end
assign DATA_RE = re[ADDR];
assign DATA_IM = im[ADDR];
endmodule |
module cf_dac_1c_2p (
// dac interface
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_data_out_a_p,
dac_data_out_a_n,
dac_data_out_b_p,
dac_data_out_b_n,
// vdma interface (for ddr-dds)
vdma_clk,
vdma_valid,
vdma_data,
vdma_ready,
// processor interface
up_rstn,
up_clk,
up_sel,
up_rwn,
up_addr,
up_wdata,
up_rdata,
up_ack,
up_status,
// debug signals (vdma) for chipscope
vdma_dbg_data,
vdma_dbg_trigger,
// debug signals (dac) for chipscope
dac_div3_clk,
dac_dbg_data,
dac_dbg_trigger,
// delay clock (usually 200MHz)
delay_clk);
// dac interface
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output [13:0] dac_data_out_a_p;
output [13:0] dac_data_out_a_n;
output [13:0] dac_data_out_b_p;
output [13:0] dac_data_out_b_n;
// vdma interface (for ddr-dds)
input vdma_clk;
input vdma_valid;
input [63:0] vdma_data;
output vdma_ready;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_rwn;
input [ 4:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
output [ 7:0] up_status;
// debug signals (vdma) for chipscope
output [198:0] vdma_dbg_data;
output [ 7:0] vdma_dbg_trigger;
// debug signals (dac) for chipscope
output dac_div3_clk;
output [292:0] dac_dbg_data;
output [ 7:0] dac_dbg_trigger;
// delay clock (usually 200MHz)
input delay_clk;
reg up_dds_sel = 'd0;
reg up_intp_enable = 'd0;
reg up_dds_enable = 'd0;
reg [15:0] up_dds_incr = 'd0;
reg [15:0] up_intp_scale_b = 'd0;
reg [15:0] up_intp_scale_a = 'd0;
reg [ 7:0] up_status = 'd0;
reg up_vdma_ovf_m1 = 'd0;
reg up_vdma_ovf_m2 = 'd0;
reg up_vdma_ovf = 'd0;
reg up_vdma_unf_m1 = 'd0;
reg up_vdma_unf_m2 = 'd0;
reg up_vdma_unf = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_sel_d = 'd0;
reg up_sel_2d = 'd0;
reg up_ack = 'd0;
wire up_wr_s;
wire up_ack_s;
wire vdma_ovf_s;
wire vdma_unf_s;
wire [13:0] dds_data_00_s;
wire [13:0] dds_data_01_s;
wire [13:0] dds_data_02_s;
wire [13:0] dds_data_03_s;
wire [13:0] dds_data_04_s;
wire [13:0] dds_data_05_s;
wire [13:0] dds_data_06_s;
wire [13:0] dds_data_07_s;
wire [13:0] dds_data_08_s;
wire [13:0] dds_data_09_s;
wire [13:0] dds_data_10_s;
wire [13:0] dds_data_11_s;
// processor write interface (see regmap.txt file for details of address definitions)
assign up_wr_s = up_sel & ~up_rwn;
assign up_ack_s = up_sel_d & ~up_sel_2d;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dds_sel <= 'd0;
up_intp_enable <= 'd0;
up_dds_enable <= 'd0;
up_dds_incr <= 'd0;
up_intp_scale_b <= 'd0;
up_intp_scale_a <= 'd0;
up_status <= 'd0;
up_vdma_ovf_m1 <= 'd0;
up_vdma_ovf_m2 <= 'd0;
up_vdma_ovf <= 'd0;
up_vdma_unf_m1 <= 'd0;
up_vdma_unf_m2 <= 'd0;
up_vdma_unf <= 'd0;
end else begin
if ((up_addr == 5'h01) && (up_wr_s == 1'b1)) begin
up_dds_sel <= up_wdata[18];
up_intp_enable <= up_wdata[17];
up_dds_enable <= up_wdata[16];
up_dds_incr <= up_wdata[15:0];
end
if ((up_addr == 5'h06) && (up_wr_s == 1'b1)) begin
up_intp_scale_b <= up_wdata[31:16];
up_intp_scale_a <= up_wdata[15:0];
end
up_status <= {5'd0, up_dds_sel, up_intp_enable, up_dds_enable};
up_vdma_ovf_m1 <= vdma_ovf_s;
up_vdma_ovf_m2 <= up_vdma_ovf_m1;
if (up_vdma_ovf_m2 == 1'b1) begin
up_vdma_ovf <= 1'b1;
end else if ((up_addr == 5'h09) && (up_wr_s == 1'b1)) begin
up_vdma_ovf <= up_vdma_ovf & (~up_wdata[1]);
end
up_vdma_unf_m1 <= vdma_unf_s;
up_vdma_unf_m2 <= up_vdma_unf_m1;
if (up_vdma_unf_m2 == 1'b1) begin
up_vdma_unf <= 1'b1;
end else if ((up_addr == 5'h09) && (up_wr_s == 1'b1)) begin
up_vdma_unf <= up_vdma_unf & (~up_wdata[0]);
end
end
end
// process read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_sel_d <= 'd0;
up_sel_2d <= 'd0;
up_ack <= 'd0;
end else begin
case (up_addr)
5'h00: up_rdata <= 32'h00010061;
5'h01: up_rdata <= {13'd0, up_dds_sel, up_intp_enable, up_dds_enable, up_dds_incr};
5'h06: up_rdata <= {up_intp_scale_b, up_intp_scale_a};
5'h09: up_rdata <= {30'd0, up_vdma_ovf, up_vdma_unf};
default: up_rdata <= 0;
endcase
up_sel_d <= up_sel;
up_sel_2d <= up_sel_d;
up_ack <= up_ack_s;
end
end
// DDS top, includes both DDR-DDS and Xilinx-DDS.
cf_dds_top i_dds_top (
.vdma_clk (vdma_clk),
.vdma_valid (vdma_valid),
.vdma_data (vdma_data),
.vdma_ready (vdma_ready),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s),
.dac_div3_clk (dac_div3_clk),
.dds_data_00 (dds_data_00_s),
.dds_data_01 (dds_data_01_s),
.dds_data_02 (dds_data_02_s),
.dds_data_03 (dds_data_03_s),
.dds_data_04 (dds_data_04_s),
.dds_data_05 (dds_data_05_s),
.dds_data_06 (dds_data_06_s),
.dds_data_07 (dds_data_07_s),
.dds_data_08 (dds_data_08_s),
.dds_data_09 (dds_data_09_s),
.dds_data_10 (dds_data_10_s),
.dds_data_11 (dds_data_11_s),
.up_dds_sel (up_dds_sel),
.up_dds_incr (up_dds_incr),
.up_dds_enable (up_dds_enable),
.up_intp_enable (up_intp_enable),
.up_intp_scale_a (up_intp_scale_a),
.up_intp_scale_b (up_intp_scale_b),
.vdma_dbg_data (vdma_dbg_data),
.vdma_dbg_trigger (vdma_dbg_trigger),
.dac_dbg_data (dac_dbg_data),
.dac_dbg_trigger (dac_dbg_trigger));
// DAC interface, (transfer samples from low speed clock to the dac clock)
cf_dac_if i_dac_if (
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_data_out_a_p (dac_data_out_a_p),
.dac_data_out_a_n (dac_data_out_a_n),
.dac_data_out_b_p (dac_data_out_b_p),
.dac_data_out_b_n (dac_data_out_b_n),
.dac_div3_clk (dac_div3_clk),
.dds_data_00 (dds_data_00_s),
.dds_data_01 (dds_data_01_s),
.dds_data_02 (dds_data_02_s),
.dds_data_03 (dds_data_03_s),
.dds_data_04 (dds_data_04_s),
.dds_data_05 (dds_data_05_s),
.dds_data_06 (dds_data_06_s),
.dds_data_07 (dds_data_07_s),
.dds_data_08 (dds_data_08_s),
.dds_data_09 (dds_data_09_s),
.dds_data_10 (dds_data_10_s),
.dds_data_11 (dds_data_11_s),
.up_dds_enable (up_dds_enable));
endmodule |
module strand_driver (
clk,
rst_n,
ws2811_mode,
strand_length,
current_idx,
mem_data,
start_frame,
busy,
done,
strand_clk,
strand_data
);
parameter MEM_DATA_WIDTH = 24;
parameter STRAND_PARAM_WIDTH = 16;
input clk;
input rst_n;
// Parameter inputs (from registers)
input ws2811_mode;
input [STRAND_PARAM_WIDTH-1:0] strand_length;
// Current pixel index (used to control the pixel RAM)
output reg [STRAND_PARAM_WIDTH-1:0] current_idx;
// Data in from the pixel RAM
input [MEM_DATA_WIDTH-1:0] mem_data;
// Toggle high to begin the state machine
input start_frame;
// Control outputs
output reg busy;
output reg done;
// Outputs to IOB
output reg strand_clk;
output reg strand_data;
// Locals
reg [7:0] counter;
reg [7:0] counter_preset;
reg [7:0] bit_position;
reg [2:0] current_state;
reg [2:0] next_state;
reg [MEM_DATA_WIDTH-1:0] current_data;
reg strand_clk_i;
reg strand_data_i;
reg busy_i;
reg [7:0] bit_position_i;
reg [STRAND_PARAM_WIDTH-1:0] current_idx_i;
reg counter_set_i;
reg counter_running;
wire words_to_decode;
wire current_bit;
// FSM
localparam STATE_IDLE = 3'b000,
STATE_START = 3'b001,
STATE_UNPACK = 3'b010,
STATE_DECODE_1 = 3'b011,
STATE_DECODE_2 = 3'b100;
// Output timing
localparam T1H = 8'd120, // WS2811 1-bit high period
T1L = 8'd130,
T0H = 8'd50,
T0L = 8'd200,
TRESET = 8'd255,
TCLKDIV2 = 8'd10;
// State machine
always @(posedge clk) begin
if (rst_n == 1'b0) begin
current_idx <= { STRAND_PARAM_WIDTH {1'b0} };
current_data <= { MEM_DATA_WIDTH {1'b0} };
busy <= 1'b0;
done <= 1'b0;
strand_clk <= 1'b0;
strand_data <= 1'b0;
counter <= {8 {1'b0} };
bit_position <= {8 {1'b0} };
current_state <= STATE_IDLE;
counter_running <= 1'b0;
end
else begin
busy <= busy_i;
current_idx <= current_idx_i;
strand_clk <= strand_clk_i;
strand_data <= strand_data_i;
// Latch the new data word
if (current_state == STATE_UNPACK) begin
current_data <= mem_data;
bit_position <= {8 {1'b0} };
end else begin
bit_position <= bit_position_i;
end
// Manage the timing counter
if (counter_set_i == 1'b1) begin
counter <= counter_preset;
counter_running <= 1'b1;
end else begin
if (counter > 0) begin
counter <= counter - 1;
end else begin
counter_running <= 1'b0;
end
end
current_state <= next_state;
end
end
assign words_to_decode = (current_idx < strand_length);
assign current_bit = mem_data[bit_position];
// Next state process
always @(*) begin
next_state = current_state;
strand_data_i = strand_data;
strand_clk_i = strand_clk;
counter_preset = counter;
busy_i = busy;
bit_position_i = bit_position;
current_idx_i = current_idx;
case (current_state)
STATE_IDLE: begin
// Start transmission
if (start_frame == 1'b1) begin
next_state = STATE_START;
busy_i = 1'b1;
current_idx_i = { STRAND_PARAM_WIDTH {1'b0} };
bit_position_i = {8 {1'b0} };
end
end
STATE_START: begin
// Perform any one-time initialization
// TODO: does this need to exist?
current_idx_i = { STRAND_PARAM_WIDTH {1'b0} };
bit_position_i = {8 {1'b0} };
next_state = STATE_UNPACK;
end
STATE_UNPACK: begin
// Grab the next pixel word
if (words_to_decode == 1'b1) begin
next_state = STATE_DECODE_1;
end else begin
next_state = STATE_IDLE;
busy_i = 0;
end
// Reset the bit position counter at the beginning of each word
bit_position = {8 {1'b0} };
end
STATE_DECODE_1: begin
// First output phase.
if (ws2811_mode == 1'b1) begin
// WS2811? D <= 1, T <= (bit==1) ? T1H : T0H
if (current_bit == 1'b1) begin
counter_preset = T1H;
end else begin
counter_preset = T0H;
end
strand_data_i = 1'b1;
end else begin
// WS2812? D <= bit, C <= 0, T <= TCLKDIV2
strand_data_i = mem_data[bit_position];
strand_clk_i = 1'b0;
counter_preset = TCLKDIV2;
end
counter_set_i = !counter_running;
if (counter == 0 && counter_running) begin
next_state = STATE_DECODE_2;
end
end
STATE_DECODE_2: begin
// Second output phase.
// WS2811? D <= 0, T <= (bit==1) ? T1L: T0L
// WS2812? C <= 0, T <= TCLKDIV2
if (ws2811_mode == 1'b1) begin
if (mem_data[bit_position] == 1'b1) begin
counter_preset = T1L;
end else begin
counter_preset = T0L;
end
strand_data_i = 1'b0;
end else begin
// Toggle the clock high; data remains the same
strand_data_i = strand_data;
strand_clk_i = 1'b1;
counter_preset = TCLKDIV2;
end
// Advance the bit index
if (counter == 0 && counter_running) begin
if (bit_position < 8'd23) begin
next_state = STATE_DECODE_1;
bit_position_i = bit_position + 1;
end else begin
next_state = STATE_UNPACK;
current_idx_i = current_idx + 1;
end
end
counter_set_i = !counter_running;
end
endcase
end
endmodule |
module axi_ad9434 (
// physical interface
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// delay interface
delay_clk,
// dma interface
adc_clk,
adc_enable,
adc_valid,
adc_data,
adc_dovf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
// parameters
localparam SERIES7 = 0;
localparam SERIES6 = 1;
parameter PCORE_ID = 0;
parameter PCORE_DEVTYPE = SERIES7;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
// physical interface
input adc_clk_in_p;
input adc_clk_in_n;
input [11:0] adc_data_in_p;
input [11:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// delay interface
input delay_clk;
// dma interface
output adc_clk;
output adc_valid;
output adc_enable;
output [63:0] adc_data;
input adc_dovf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire mmcm_rst;
wire up_clk;
wire adc_clk;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire [13:0] up_waddr_s;
wire [13:0] up_raddr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s;
wire up_wack_s;
wire up_rack_s;
wire [ 1:0] up_status_pn_err_s;
wire [ 1:0] up_status_pn_oos_s;
wire [ 1:0] up_status_or_s;
wire adc_status_s;
wire [12:0] up_dld_s;
wire [64:0] up_dwdata_s;
wire [64:0] up_drdata_s;
wire delay_clk_s;
wire delay_rst;
wire delay_locked_s;
wire up_drp_sel_s;
wire up_drp_wr_s;
wire [11:0] up_drp_addr_s;
wire [15:0] up_drp_wdata_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
wire up_drp_locked_s;
wire [47:0] adc_data_if_s;
wire adc_or_if_s;
// clock/reset assignments
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// single channel always enable
assign adc_enable = 1'b1;
axi_ad9434_if #(
.PCORE_DEVTYPE(PCORE_DEVTYPE),
.PCORE_IODELAY_GROUP(PCORE_IODELAY_GROUP))
i_if(
.adc_clk_in_p(adc_clk_in_p),
.adc_clk_in_n(adc_clk_in_n),
.adc_data_in_p(adc_data_in_p),
.adc_data_in_n(adc_data_in_n),
.adc_or_in_p(adc_or_in_p),
.adc_or_in_n(adc_or_in_n),
.adc_data(adc_data_if_s),
.adc_or(adc_or_if_s),
.adc_clk(adc_clk),
.adc_rst(adc_rst),
.adc_status(adc_status_s),
.up_clk (up_clk),
.up_adc_dld (up_dld_s),
.up_adc_dwdata (up_dwdata_s),
.up_adc_drdata (up_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.mmcm_rst(mmcm_rst),
.up_rstn(up_rstn),
.up_drp_sel(up_drp_sel_s),
.up_drp_wr(up_drp_wr_s),
.up_drp_addr(up_drp_addr_s),
.up_drp_wdata(up_drp_wdata_s),
.up_drp_rdata(up_drp_rdata_s),
.up_drp_ready(up_drp_ready_s),
.up_drp_locked(up_drp_locked_s));
// common processor control
axi_ad9434_core #(.PCORE_ID(PCORE_ID))
i_core (
.adc_clk(adc_clk),
.adc_data(adc_data_if_s),
.adc_or(adc_or_if_s),
.mmcm_rst (mmcm_rst),
.adc_rst (adc_rst),
.adc_status (adc_status_s),
.dma_dvalid (adc_valid),
.dma_data (adc_data),
.dma_dovf (adc_dovf),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.up_drp_sel (up_drp_sel_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_ready (up_drp_ready_s),
.up_drp_locked (up_drp_locked_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata_s),
.up_wack (up_wack_s),
.up_raddr (up_raddr_s),
.up_rreq (up_rreq_s),
.up_rack (up_rack_s));
endmodule |
module alu
(
input wire[31:0] opr_a_alu_i,
input wire[31:0] opr_b_alu_i,
input wire[5:0] op_alu_i,
output wire[31:0] res_alu_o,
output wire z_alu_o,
output wire n_alu_o
);
wire[31:0] res_alu;
wire z_alu;
wire n_alu;
wire v_alu;
wire[31:0] opr_b_negated_alu;
wire cin_alu;
wire[31:0] adder_out_alu;
wire carry_out_alu;
wire[31:0] logical_out_alu;
wire[31:0] shifter_out_alu;
wire comparator_out_alu;
assign res_alu_o = res_alu;
assign z_alu_o = z_alu;
assign n_alu_o = n_alu;
assign opr_b_negated_alu = op_alu_i[0] ? ~opr_b_alu_i : opr_b_alu_i;
assign cin_alu = op_alu_i[0];
assign z_alu = ~|adder_out_alu;
assign n_alu = (v_alu) ? opr_a_alu_i[31] : adder_out_alu[31];
assign res_alu = ((op_alu_i == `ADD_OP) || (op_alu_i == `SUB_OP)) ? adder_out_alu :
((op_alu_i == `SHL_OP) || (op_alu_i == `LSR_OP) || (op_alu_i == `ASR_OP)) ? shifter_out_alu :
((op_alu_i == `OR_OP) || (op_alu_i == `AND_OP) || (op_alu_i == `NOR_OP) || (op_alu_i == `XOR_OP)) ? logical_out_alu :
((op_alu_i == `SLTU_OP)) ? comparator_out_alu :
((op_alu_i == `SLT_OP)) ? {{31{1'b0}}, n_alu}:
31'hxxxx_xxxx;
adder A1 (
.op1 (opr_a_alu_i),
.op2 (opr_b_negated_alu),
.cin (cin_alu),
.sum (adder_out_alu),
.carry (carry_out_alu),
.v_flag (v_alu)
);
shifter S1 (
.op1 (opr_a_alu_i),
.shamt (opr_b_alu_i[5:0]),
.operation (op_alu_i[2:1]),
.res (shifter_out_alu)
);
logical L1 (
.op1 (opr_a_alu_i),
.op2 (opr_b_alu_i),
.operation (op_alu_i[5:3]),
.res (logical_out_alu)
);
comparator C1 (
.op1 (opr_a_alu_i),
.op2 (opr_b_alu_i),
.operation (op_alu_i[5:3]),
.res (comparator_out_alu)
);
endmodule |
module sky130_fd_sc_lp__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module system_xbar_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI AWID [1:0] [5:4]" *)
input wire [5 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 S02_AXI AWADDR [31:0] [95:64]" *)
input wire [95 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 S02_AXI AWLEN [7:0] [23:16]" *)
input wire [23 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 S02_AXI AWSIZE [2:0] [8:6]" *)
input wire [8 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI AWBURST [1:0] [5:4]" *)
input wire [5 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI AWLOCK [0:0] [2:2]" *)
input wire [2 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 S02_AXI AWCACHE [3:0] [11:8]" *)
input wire [11 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 S02_AXI AWPROT [2:0] [8:6]" *)
input wire [8 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 S02_AXI AWQOS [3:0] [11:8]" *)
input wire [11 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI AWVALID [0:0] [2:2]" *)
input wire [2 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI AWREADY [0:0] [2:2]" *)
output wire [2 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [63:0] [127:64], xilinx.com:interface:aximm:1.0 S02_AXI WDATA [63:0] [191:128]" *)
input wire [191 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [7:0] [15:8], xilinx.com:interface:aximm:1.0 S02_AXI WSTRB [7:0] [23:16]" *)
input wire [23 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI WLAST [0:0] [2:2]" *)
input wire [2 : 0] s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI WVALID [0:0] [2:2]" *)
input wire [2 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI WREADY [0:0] [2:2]" *)
output wire [2 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI BID [1:0] [5:4]" *)
output wire [5 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI BRESP [1:0] [5:4]" *)
output wire [5 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI BVALID [0:0] [2:2]" *)
output wire [2 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI BREADY [0:0] [2:2]" *)
input wire [2 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI ARID [1:0] [5:4]" *)
input wire [5 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 S02_AXI ARADDR [31:0] [95:64]" *)
input wire [95 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 S02_AXI ARLEN [7:0] [23:16]" *)
input wire [23 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 S02_AXI ARSIZE [2:0] [8:6]" *)
input wire [8 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI ARBURST [1:0] [5:4]" *)
input wire [5 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI ARLOCK [0:0] [2:2]" *)
input wire [2 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 S02_AXI ARCACHE [3:0] [11:8]" *)
input wire [11 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 S02_AXI ARPROT [2:0] [8:6]" *)
input wire [8 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 S02_AXI ARQOS [3:0] [11:8]" *)
input wire [11 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI ARVALID [0:0] [2:2]" *)
input wire [2 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI ARREADY [0:0] [2:2]" *)
output wire [2 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI RID [1:0] [5:4]" *)
output wire [5 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [63:0] [127:64], xilinx.com:interface:aximm:1.0 S02_AXI RDATA [63:0] [191:128]" *)
output wire [191 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI RRESP [1:0] [5:4]" *)
output wire [5 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI RLAST [0:0] [2:2]" *)
output wire [2 : 0] s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI RVALID [0:0] [2:2]" *)
output wire [2 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI RREADY [0:0] [2:2]" *)
input wire [2 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID" *)
output wire [1 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID" *)
output wire [0 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY" *)
input wire [0 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST" *)
output wire [0 : 0] m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID" *)
output wire [0 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY" *)
input wire [0 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID" *)
input wire [1 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID" *)
input wire [0 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY" *)
output wire [0 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID" *)
output wire [1 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID" *)
output wire [0 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY" *)
input wire [0 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID" *)
input wire [1 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST" *)
input wire [0 : 0] m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID" *)
input wire [0 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY" *)
output wire [0 : 0] m_axi_rready;
axi_crossbar_v2_1_12_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(3),
.C_NUM_MASTER_SLOTS(1),
.C_AXI_ID_WIDTH(2),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_PROTOCOL(0),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(64'H0000000000000000),
.C_M_AXI_ADDR_WIDTH(32'H0000001d),
.C_S_AXI_BASE_ID(96'H000000020000000100000000),
.C_S_AXI_THREAD_ID_WIDTH(96'H000000000000000000000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(32'H00000005),
.C_M_AXI_READ_CONNECTIVITY(32'H00000003),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(96'H000000000000000000000000),
.C_S_AXI_WRITE_ACCEPTANCE(96'H000000020000000200000002),
.C_S_AXI_READ_ACCEPTANCE(96'H000000020000000200000002),
.C_M_AXI_WRITE_ISSUING(32'H00000008),
.C_M_AXI_READ_ISSUING(32'H00000008),
.C_S_AXI_ARB_PRIORITY(96'H000000000000000000000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(3'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(6'H00),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(3'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(3'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule |
module scheduler1_multi(clk, reset, wen, enablein, datain, dataout, full, empty, enableout);
parameter data_width = 32;
//parameter data_width1 = 34;
parameter data_width1 = 36;
parameter address_width = 7;
parameter FIFO_depth = 128;
parameter number_mapper = 2;
input clk,reset,wen,enablein;
input [data_width-1:0] datain;
output [data_width1-1:0] dataout;
output full,empty;
output enableout;
reg[address_width-1:0] write_p,read_p;
reg[address_width:0] counter;
reg[data_width-1:0] dataout1;
wire[data_width1-1:0] dataout;
reg [data_width-1:0] memory[FIFO_depth-1:0];
reg[data_width-1:0] keywordnumber,textfilenumber;
reg enableout1;
reg[3:0] routeraddress;
reg wen1;
reg [data_width-1:0] datain1;
reg ren;
reg[5:0]counter2,counter1,counter3,counter4;
reg[3:0] mapper_p;
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
wen1=0;
else
if(wen)
wen1=1;
else
if(write_p!=0&&write_p!=1&&datain1==32'b11111111111111111111111111111111)
wen1=0;
else
wen1=wen1;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
ren=0;
else
if(write_p!=0&&write_p!=1&&datain1==32'b11111111111111111111111111111111)
ren=1;
else
if(write_p==read_p&&write_p>3)
ren=0;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
counter1=0;
else
if(ren&&counter1<2)
counter1=counter1+1;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
dataout1=0;
else
if(wen1&&(write_p<FIFO_depth-1)&&(enableout1==1))
dataout1=dataout1+1;
else
dataout1=0;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
routeraddress=0;
else
if(wen1&&(write_p<FIFO_depth-1)&&(enableout1==1))
routeraddress=1;
else
if(ren&&(read_p<write_p)&&(write_p<FIFO_depth-1))
begin
if(mapper_p==1)
routeraddress=4'b1001;
else if(mapper_p==2)
routeraddress=4'b0110;
else if(mapper_p==3)
routeraddress=4;
else if(mapper_p==4)
routeraddress=5;
else if(mapper_p==5)
routeraddress=6;
else if(mapper_p==6)
routeraddress=7;
else if(mapper_p==7)
routeraddress=8;
else if(mapper_p==8)
routeraddress=9;
end
else
routeraddress=0;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
enableout1=0;
else
if(wen1)
enableout1=1;
else
if(ren&&(read_p<write_p-1))
enableout1=1;
else
enableout1=0;
end
always@(posedge clk,negedge reset)
begin
if(!ren)
mapper_p=0;
else if(ren&&mapper_p<number_mapper)
begin
if(counter4<number_mapper+1)
begin
if(counter3==1)
mapper_p=mapper_p+1;
else
mapper_p=mapper_p;
end
else
mapper_p=mapper_p+1;
end
else
begin
if(counter4<number_mapper+1)
mapper_p=mapper_p;
else
mapper_p=1;
end
end
always@(posedge clk,negedge reset)
begin
if(!ren)
counter4=0;
else if(ren&&(counter3==1)&&(counter4<number_mapper+1))
counter4=counter4+1;
else
counter4=counter4;
end
always@(posedge clk,negedge reset)
begin
if(!ren)
counter3=1;
else if(ren&&counter3<4)
counter3=counter3+1;
else
counter3=1;
end
always@(posedge clk,negedge reset)
begin
if(!ren)
counter2=0;
else if(ren&&counter2<(4*number_mapper))
counter2=counter2+1;
else
counter2=counter2;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
read_p=3;
else if(ren&&(read_p<write_p)&&(read_p<FIFO_depth)&&counter1==2)
begin
if(read_p<7)
read_p<=read_p+1;
else if(read_p==7&&(counter2!=(4*number_mapper)))
read_p=4;
else
read_p=read_p+1;
end
else
read_p=read_p;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
dataout1=0;
else if(ren&&(read_p<=write_p)&&(enableout1==1)&&counter1==2)
dataout1=memory[read_p];
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
write_p=0;
else
if(enablein&&(write_p<FIFO_depth-1))
write_p=write_p+1;
else
write_p=write_p;
end
always@(posedge clk)
begin
if(wen1&&enablein==1)
memory[write_p]=datain;
datain1=datain;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
counter=0;
else if(wen1&&!ren&&(counter!=FIFO_depth))
counter=counter+1;
else if(ren&&!wen1&&(counter!=0))
counter=counter-1;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
keywordnumber=0;
else if (write_p>=3)
keywordnumber=memory[2];
else
keywordnumber=0;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
textfilenumber=0;
else if (write_p>=4)
textfilenumber=memory[3];
else
textfilenumber=0;
end
//*************
reg end_f;
always@(posedge clk or negedge reset)
if(!reset)
end_f <= 0;
else if(datain == 32'hffffffff)
end_f <= 1'b1;
else
end_f <= end_f;
//*************
assign full=(counter==(FIFO_depth-1));
assign empty=(counter==0);
//
//assign dataout[31:0]=dataout1;
//assign dataout[33:32]=routeraddress;
assign dataout[35:4]=dataout1;
assign dataout[3:0]=routeraddress;
//
assign enableout=enableout1;
endmodule |
module FIFO_pixelq_op_img_data_stream_1_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule |
module FIFO_pixelq_op_img_data_stream_1_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_pixelq_op_img_data_stream_1_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_pixelq_op_img_data_stream_1_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule |
module riscv_core (
input clk,
input rstn,
//Instruction memory
output [`REG_W-1:0] imem_addr,
input [`INSTR_W-1:0] imem_rdata,
//Data memory
output [`REG_W-1:0] dmem_addr,
output dmem_cs,
output dmem_rnw,
output [(`DATA_W/8)-1:0] dmem_wmask,
output [`DATA_W-1:0] dmem_wdata,
input [`DATA_W-1:0] dmem_rdata,
//Misc
output stalled
);
localparam OPCODE_IMM = 7'b0010011;
localparam OPCODE_LUI = 7'b0110111;
localparam OPCODE_AUIPC = 7'b0010111;
localparam OPCODE_OP = 7'b0110011;
localparam OPCODE_JAL = 7'b1101111;
localparam OPCODE_JALR = 7'b1100111;
localparam OPCODE_BRANCH = 7'b1100011;
localparam OPCODE_LOAD = 7'b0000011;
localparam OPCODE_STORE = 7'b0100011;
localparam OPCODE_MISC_MEM = 7'b0001111;
localparam OPCODE_SYSTEM = 7'b1110011;
reg [`REG_W-1:0] pc_reg;
reg [`REG_W-1:0] reg_file [0:31];
reg [`REG_W-1:0] pc_nxt;
reg stall_back;
reg take_branch;
reg [`REG_W-1:0] target;
initial begin
stall_back = 0;
take_branch = 0;
end
//Instruction Fetch
assign imem_addr = pc_reg;
always @ (*) begin
if (stall_back) begin
pc_nxt = pc_reg;
end
else if (take_branch) begin
pc_nxt = target;
end
else begin
pc_nxt = pc_reg + 4;
end
end
always @ (posedge clk, negedge rstn) begin
if (rstn == 0) begin
pc_reg <= 'h0;
end
else begin
pc_reg <= pc_nxt;
end
end
wire [`REG_W-1:0] instr;
assign instr = imem_rdata;
//Decode
//Split the instruction into an ALU, mem and branch function
//Reg read
wire [31:0] rsj;
wire [31:0] rsk;
assign rsj = reg_file[rsj_sel];
assign rsk = reg_file[rsk_sel];
wire [4:0] rsj_sel;
wire [4:0] rsk_sel;
wire [4:0] rsd_sel;
assign rsd_sel = instr[11:7];
assign rsj_sel = instr[19:15];
assign rsk_sel = instr[24:20];
endmodule |
module riscv_core_tb ();
reg clk;
reg rstn;
//Instruction memory
wire [`REG_W-1:0] imem_addr;
reg [`INSTR_W-1:0] imem_rdata;
//Data memory
wire [`REG_W-1:0] dmem_addr;
wire dmem_cs;
wire dmem_rnw;
wire [(`DATA_W/8)-1:0] dmem_wmask;
wire [`DATA_W-1:0] dmem_wdata;
reg [`DATA_W-1:0] dmem_rdata;
//Misc
wire stalled;
riscv_core dut (
.clk (clk),
.rstn (rstn),
.imem_addr (imem_addr),
.imem_rdata (imem_rdata),
.dmem_addr (dmem_addr),
.dmem_cs (dmem_cs),
.dmem_rnw (dmem_rnw),
.dmem_wmask (dmem_wmask),
.dmem_wdata (dmem_wdata),
.dmem_rdata (dmem_rdata),
.stalled (stalled)
);
initial begin
clk = 1;
rstn = 1;
#5 clk = 0;
rstn = 0;
#5 clk = 1;
rstn = 1;
forever begin
#5 clk = ~clk;
end
end
initial
$monitor("imem_addr : %x", imem_addr);
initial begin
$dumpfile("test.vcd");
$dumpvars(0,dut);
end
//reg [31:0] rand;
integer rand;
initial begin
repeat (20) begin
@ (posedge clk);
dut.take_branch = 0;
rand = $random;
if (rand[1:0] == 2'b11) begin
dut.take_branch = 1;
dut.target = rand;
$display("Branching to %x", dut.target);
end
end
$finish();
end
endmodule |
module sigma_delta
(input c_mod, // modulation clock
input mod_bit, // data bit from the modulator
input c, // the clock for the rest of the chip
input invert,
output [15:0] raw_d, // raw ADC word
output raw_dv,
output [15:0] d, // filtered ADC word (dumb for now)
output dv);
wire mod_bit_s; // synchronized modulator bit
sync mod_sync(.in(mod_bit), .clk(c_mod), .out(mod_bit_s));
wire invert_modclk;
sync invert_sync(.in(invert), .clk(c_mod), .out(invert_modclk));
// let's use a decimation ratio of 32 for now. This will give 11.4 ENOB
// and a settling time of 2.4 usec.
localparam W = 16;
localparam DECIM = 32;
wire [W-1:0] i0, i1, i2; // integrators
r #(W) int_0(.c(c_mod), .rst(1'b0), .en(1'b1), .d(i0 + mod_bit_s), .q(i0));
r #(W) int_1(.c(c_mod), .rst(1'b0), .en(1'b1), .d(i0 + i1), .q(i1));
r #(W) int_2(.c(c_mod), .rst(1'b0), .en(1'b1), .d(i1 + i2), .q(i2));
wire dec_match;
wire [7:0] dec_cnt;
r #(8) dec_cnt_r
(.c(c_mod), .rst(dec_match), .en(1'b1), .d(dec_cnt + 1'b1), .q(dec_cnt));
assign dec_match = dec_cnt == DECIM-1; //8'd3; //8'd31; // decimate by 32
wire [W-1:0] decim; // the simplest decimator possible
r #(W) decim_r(.c(c_mod), .rst(1'b0), .en(dec_match), .d(i2), .q(decim));
// now the differentiators
wire [W-1:0] d0, d1, d2;
wire [W-1:0] diff_0 = decim - d0;
wire [W-1:0] diff_1 = diff_0 - d1;
wire [W-1:0] diff_2 = diff_1 - d2;
r #(W) d0_r(.c(c_mod), .rst(1'b0), .en(dec_match), .d(decim), .q(d0));
r #(W) d1_r(.c(c_mod), .rst(1'b0), .en(dec_match), .d(diff_0), .q(d1));
r #(W) d2_r(.c(c_mod), .rst(1'b0), .en(dec_match), .d(diff_1), .q(d2));
wire raw_dv_d1;
d1 raw_dv_d1_r(.c(c_mod), .d(dec_match), .q(raw_dv_d1));
// delay things one clock cycle in order to meet timing
wire [15:0] raw_d_modclk; // data word, in the modulation-clock domain
wire raw_dv_modclk;
d1 #(16) raw_d_d1_r(.c(c_mod),
.d(invert_modclk ? 16'd32767 - diff_2 : diff_2),
.q(raw_d_modclk));
d1 raw_dv_d2_r(.c(c_mod), .d(raw_dv_d1), .q(raw_dv_modclk));
// clock it up to the rest of the logic speed
sync #(16) raw_d_s(.in(raw_d_modclk), .clk(c), .out(raw_d));
wire raw_dv_slow; // this signal will be synchronized to "c" but is high too long
sync #(.W(1), .S(3)) raw_dv_s(.in(raw_dv_modclk), .clk(c), .out(raw_dv_slow));
wire raw_dv_slow_d1;
d1 raw_dv_slow_d1_r(.c(c), .d(raw_dv_slow), .q(raw_dv_slow_d1));
assign raw_dv = raw_dv_slow & ~raw_dv_slow_d1; // high for only one cycle
//////////////////////////////////////
// now, implement a dumb placeholder filter. maybe in the future do something
// more sophisticated, but for now just average x32 to make a 19.531 kHz
// stream for feeding PWM
wire [4:0] sample_cnt;
r #(5) sample_cnt_r
(.c(c_mod), .en(raw_dv_modclk), .rst(1'b0),
.d(sample_cnt + 1'b1), .q(sample_cnt));
wire raw_dv_modclk_d1;
d1 raw_dv_modclk_d1_r(.c(c_mod), .d(raw_dv_modclk), .q(raw_dv_modclk_d1));
wire [21:0] accum_d, accum;
wire accum_en, accum_rst;
r #(22) accum_r
(.c(c_mod), .d(accum_d), .rst(accum_rst), .en(raw_dv_modclk), .q(accum));
assign accum_d = accum + {5'h0, raw_d};
assign accum_rst = sample_cnt == 5'h00 & raw_dv_modclk_d1;
wire [21:0] last_accum;
r #(22) last_accum_r
(.c(c_mod), .rst(1'b0), .en(accum_rst), .d(accum), .q(last_accum));
wire [15:0] filtered_modclk = last_accum[20:5]; // in the c_mod domain
wire filtered_dv_modclk;
d1 filtered_dv_d1_r(.c(c_mod), .d(accum_rst), .q(filtered_dv_modclk));
// clock it up to the rest of the logic speed
sync #(16) d_s(.in(filtered_modclk), .clk(c), .out(d));
wire dv_slow; // this signal will be synchronized to "c" but is high too long
sync #(.W(1), .S(3)) dv_s(.in(filtered_dv_modclk), .clk(c), .out(dv_slow));
wire dv_slow_d1;
d1 dv_slow_d1_r(.c(c), .d(dv_slow), .q(dv_slow_d1));
assign dv = dv_slow & ~dv_slow_d1; // high for only one cycle
endmodule |
module sigma_delta_tb();
wire c, c_mod;
sim_clk #(20) clk_20(c_mod);
sim_clk #(125) clk_125(c);
wire [2:0] hi, lo;
wire [15:0] sd_d;
reg [1:0] all_bits [3999:0];
wire sd_dv;
reg mod_bit;
reg invert;
sigma_delta sd_inst
(.c_mod(c_mod), .c(c), .invert(invert), .mod_bit(mod_bit), .d(sd_d), .dv(sd_dv));
integer i;
initial begin
$readmemh("sigma_delta_test_data.txt", all_bits, 0, 3999);
$dumpfile("sigma_delta.lxt");
$dumpvars();
mod_bit = 1'b0;
invert = 1'b0;
for (i = 0; i < 4000; i = i + 1) begin
wait(c_mod);
wait(~c_mod);
mod_bit = all_bits[i][0];
end
$finish();
end
endmodule |
module sky130_fd_sc_hd__fill ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
empty, rd_data_count, wr_data_count, prog_full, prog_empty)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[63:0],wr_en,rd_en,dout[63:0],full,empty,rd_data_count[9:0],wr_data_count[8:0],prog_full,prog_empty" */;
input rst;
input wr_clk;
input rd_clk;
input [63:0]din;
input wr_en;
input rd_en;
output [63:0]dout;
output full;
output empty;
output [9:0]rd_data_count;
output [8:0]wr_data_count;
output prog_full;
output prog_empty;
endmodule |
module BLE_v3_40_0 (
clk,
pa_en);
output clk;
output pa_en;
wire Net_55;
wire Net_60;
wire Net_53;
wire Net_102;
wire Net_101;
wire Net_100;
wire Net_99;
wire Net_98;
wire Net_97;
wire Net_96;
wire Net_95;
wire Net_94;
wire Net_93;
wire Net_92;
wire Net_91;
wire Net_72;
wire Net_71;
wire Net_70;
wire Net_90;
wire Net_89;
wire Net_88;
wire Net_15;
wire Net_14;
cy_m0s8_ble_v1_0 cy_m0s8_ble (
.interrupt(Net_15),
.rf_ext_pa_en(pa_en));
cy_isr_v1_0
#(.int_type(2'b10))
bless_isr
(.int_signal(Net_15));
cy_clock_v1_0
#(.id("34930e12-af9a-4d94-86a4-9071ff746fb7/5ae6fa4d-f41a-4a35-8821-7ce70389cb0c"),
.source_clock_id("9A908CA6-5BB3-4db0-B098-959E5D90882B"),
.divisor(0),
.period("0"),
.is_direct(1),
.is_digital(0))
LFCLK
(.clock_out(Net_53));
assign clk = Net_55 | Net_53;
assign Net_55 = 1'h0;
endmodule |
module top ;
wire Net_2582;
wire Net_2581;
electrical Net_2493;
electrical Net_2541;
electrical Net_3701;
electrical Net_3702;
cy_annotation_universal_v1_0 GND_1 (
.connect({
Net_2493
})
);
defparam GND_1.comp_name = "Gnd_v1_0";
defparam GND_1.port_names = "T1";
defparam GND_1.width = 1;
wire [0:0] tmpOE__PWM_IN_net;
wire [0:0] tmpFB_0__PWM_IN_net;
wire [0:0] tmpIO_0__PWM_IN_net;
wire [0:0] tmpINTERRUPT_0__PWM_IN_net;
electrical [0:0] tmpSIOVREF__PWM_IN_net;
cy_psoc3_pins_v1_10
#(.id("8d318d8b-cf7b-4b6b-b02c-ab1c5c49d0ba"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b1),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
PWM_IN
(.oe(tmpOE__PWM_IN_net),
.y({1'b0}),
.fb({tmpFB_0__PWM_IN_net[0:0]}),
.io({tmpIO_0__PWM_IN_net[0:0]}),
.siovref(tmpSIOVREF__PWM_IN_net),
.interrupt({tmpINTERRUPT_0__PWM_IN_net[0:0]}),
.annotation({Net_2541}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__PWM_IN_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
BLE_v3_40_0 BLE (
.clk(Net_2581),
.pa_en(Net_2582));
wire [0:0] tmpOE__STATUS_net;
wire [0:0] tmpFB_0__STATUS_net;
wire [0:0] tmpIO_0__STATUS_net;
wire [0:0] tmpINTERRUPT_0__STATUS_net;
electrical [0:0] tmpSIOVREF__STATUS_net;
cy_psoc3_pins_v1_10
#(.id("e851a3b9-efb8-48be-bbb8-b303b216c393"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
STATUS
(.oe(tmpOE__STATUS_net),
.y({1'b0}),
.fb({tmpFB_0__STATUS_net[0:0]}),
.io({tmpIO_0__STATUS_net[0:0]}),
.siovref(tmpSIOVREF__STATUS_net),
.interrupt({tmpINTERRUPT_0__STATUS_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__STATUS_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_annotation_universal_v1_0 L_1 (
.connect({
Net_2493,
Net_3701
})
);
defparam L_1.comp_name = "Inductor_v1_0";
defparam L_1.port_names = "T1, T2";
defparam L_1.width = 2;
cy_annotation_universal_v1_0 C_1 (
.connect({
Net_3701,
Net_3702
})
);
defparam C_1.comp_name = "Capacitor_v1_0";
defparam C_1.port_names = "T1, T2";
defparam C_1.width = 2;
endmodule |
module system1_nios2_gen2_0_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule |
module register_file
#(parameter ctrl_w = `RF_CTRL_WIDTH,
parameter nat_w = `SENIOR_NATIVE_WIDTH)
(
input wire clk_i,
input wire reset_i,
input wire [nat_w-1:0] pass_through_dat_i,
input wire [ctrl_w-1:0] ctrl_i,
input wire [nat_w-1:0] dat_i,
input wire [nat_w-1:0] dm_dat_i,
input wire register_enable_i,
output reg [nat_w-1:0] dat_a_o,
output reg [nat_w-1:0] dat_b_o
);
reg [nat_w-1:0] theRF [31:0];
wire [nat_w-1:0] out_a;
wire [nat_w-1:0] out_b;
// Internal Declarations
always@(posedge clk_i) begin
if(register_enable_i && ctrl_i`RF_WRITE_REG_EN) begin
theRF[ctrl_i`RF_WRITE_REG_SEL] <= dat_i;
end
if(register_enable_i && ctrl_i`RF_WRITE_REG_EN_DM &&
ctrl_i`RF_WRITE_REG_SEL != ctrl_i`RF_WRITE_REG_SEL_DM) begin
theRF[ctrl_i`RF_WRITE_REG_SEL_DM] <= dm_dat_i;
end
end
wire [5:0] ctrl_i_opa;
wire [5:0] ctrl_i_opb;
assign ctrl_i_opa = ctrl_i`RF_OPA;
assign ctrl_i_opb = ctrl_i`RF_OPB;
assign out_a = theRF[ctrl_i_opa[4:0]];
assign out_b = theRF[ctrl_i_opb[4:0]];
// output logic
// mux for operand A
always @(*) begin
case (ctrl_i_opa[5])
1'b0: dat_a_o=out_a;
1'b1: dat_a_o=pass_through_dat_i;
endcase // case(id_rf_opa_sel_i[5])
end
// mux for operand B
always@(*) begin
case (ctrl_i_opb[5])
1'b0: dat_b_o=out_b;
1'b1: dat_b_o=pass_through_dat_i;
endcase
end
endmodule |
module sky130_fd_sc_hd__tapvgnd2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module lvt_reg
#( parameter MEMD = 16, // memory depth
parameter nRP = 2 , // number of reading ports
parameter nWP = 2 , // number of writing ports
parameter RDWB = 0 , // new data for Read-During-Write
parameter ZERO = 0 , // binary / Initial RAM with zeros (has priority over FILE)
parameter FILE = "" // initialization file, optional
)( input clk , // clock
input [ nWP-1:0] WEnb , // write enable for each writing port
input [`log2(MEMD)*nWP-1:0] WAddr, // write addresses - packed from nWP write ports
input [`log2(MEMD)*nRP-1:0] RAddr, // read addresses - packed from nRP read ports
output [`log2(nWP )*nRP-1:0] RBank); // read bank selector - packed from nRP read ports
localparam ADRW = `log2(MEMD); // address width
localparam LVTW = `log2(nWP ); // required memory width
// Generate Bank ID's to write into LVT
reg [LVTW*nWP-1:0] WData1D ;
wire [LVTW -1:0] WData2D [nWP-1:0];
genvar gi;
generate
for (gi=0;gi<nWP;gi=gi+1) begin: GenerateID
assign WData2D[gi]=gi;
end
endgenerate
// packing/unpacking arrays into 1D/2D/3D structures; see utils.vh for definitions
// pack ID's into 1D array
`ARRINIT;
always @* `ARR2D1D(nWP,LVTW,WData2D,WData1D);
mpram_reg #( .MEMD (MEMD ), // memory depth
.DATW (LVTW ), // data width
.nRP (nRP ), // number of reading ports
.nWP (nWP ), // number of writing ports
.RDWB (RDWB ), // provide new data when Read-During-Write?
.ZERO (ZERO ), // binary / Initial RAM with zeros (has priority over FILE)
.FILE (FILE )) // initialization file, optional
mpram_reg_ins ( .clk (clk ), // clock - in
.WEnb (WEnb ), // write enable for each writing port - in : [ nWP-1:0]
.WAddr (WAddr ), // write addresses - packed from nWP write ports - in : [ADRW*nWP-1:0]
.WData (WData1D), // write data - packed from nRP read ports - in : [LVTW*nWP-1:0]
.RAddr (RAddr ), // read addresses - packed from nRP read ports - in : [ADRW*nRP-1:0]
.RData (RBank )); // read data - packed from nRP read ports - out: [LVTW*nRP-1:0]
endmodule |
module system_vga_transform_0_0
(clk,
enable,
x_addr_in,
y_addr_in,
rot_m00,
rot_m01,
rot_m10,
rot_m11,
t_x,
t_y,
x_addr_out,
y_addr_out);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input enable;
input [9:0]x_addr_in;
input [9:0]y_addr_in;
input [15:0]rot_m00;
input [15:0]rot_m01;
input [15:0]rot_m10;
input [15:0]rot_m11;
input [9:0]t_x;
input [9:0]t_y;
output [9:0]x_addr_out;
output [9:0]y_addr_out;
wire clk;
wire enable;
wire [15:0]rot_m00;
wire [15:0]rot_m01;
wire [15:0]rot_m10;
wire [15:0]rot_m11;
wire [9:0]t_x;
wire [9:0]t_y;
wire [9:0]x_addr_in;
wire [9:0]x_addr_out;
wire [9:0]y_addr_in;
wire [9:0]y_addr_out;
system_vga_transform_0_0_vga_transform U0
(.clk(clk),
.enable(enable),
.rot_m00(rot_m00),
.rot_m01(rot_m01),
.rot_m10(rot_m10),
.rot_m11(rot_m11),
.t_x(t_x),
.t_y(t_y),
.x_addr_in(x_addr_in),
.x_addr_out(x_addr_out),
.y_addr_in(y_addr_in),
.y_addr_out(y_addr_out));
endmodule |
module system_vga_transform_0_0_vga_transform
(x_addr_out,
y_addr_out,
rot_m01,
y_addr_in,
rot_m00,
x_addr_in,
clk,
rot_m11,
rot_m10,
enable,
t_x,
t_y);
output [9:0]x_addr_out;
output [9:0]y_addr_out;
input [15:0]rot_m01;
input [9:0]y_addr_in;
input [15:0]rot_m00;
input [9:0]x_addr_in;
input clk;
input [15:0]rot_m11;
input [15:0]rot_m10;
input enable;
input [9:0]t_x;
input [9:0]t_y;
wire clk;
wire enable;
wire [9:0]p_0_in;
wire [23:14]p_1_in;
wire [15:0]rot_m00;
wire [15:0]rot_m01;
wire [15:0]rot_m10;
wire [15:0]rot_m11;
wire [9:0]t_x;
wire [9:0]t_y;
wire [9:0]x_addr_in;
wire [9:0]x_addr_out;
wire [23:14]x_addr_out0;
wire x_addr_out0_carry__0_i_1_n_0;
wire x_addr_out0_carry__0_i_2_n_0;
wire x_addr_out0_carry__0_i_3_n_0;
wire x_addr_out0_carry__0_i_4_n_0;
wire x_addr_out0_carry__0_n_0;
wire x_addr_out0_carry__0_n_1;
wire x_addr_out0_carry__0_n_2;
wire x_addr_out0_carry__0_n_3;
wire x_addr_out0_carry__1_i_1_n_0;
wire x_addr_out0_carry__1_i_2_n_0;
wire x_addr_out0_carry__1_n_3;
wire x_addr_out0_carry_i_1_n_0;
wire x_addr_out0_carry_i_2_n_0;
wire x_addr_out0_carry_i_3_n_0;
wire x_addr_out0_carry_n_0;
wire x_addr_out0_carry_n_1;
wire x_addr_out0_carry_n_2;
wire x_addr_out0_carry_n_3;
wire x_addr_out2_carry__0_i_1_n_0;
wire x_addr_out2_carry__0_i_2_n_0;
wire x_addr_out2_carry__0_i_3_n_0;
wire x_addr_out2_carry__0_i_4_n_0;
wire x_addr_out2_carry__0_n_0;
wire x_addr_out2_carry__0_n_1;
wire x_addr_out2_carry__0_n_2;
wire x_addr_out2_carry__0_n_3;
wire x_addr_out2_carry__1_i_1_n_0;
wire x_addr_out2_carry__1_i_2_n_0;
wire x_addr_out2_carry__1_i_3_n_0;
wire x_addr_out2_carry__1_i_4_n_0;
wire x_addr_out2_carry__1_n_0;
wire x_addr_out2_carry__1_n_1;
wire x_addr_out2_carry__1_n_2;
wire x_addr_out2_carry__1_n_3;
wire x_addr_out2_carry__2_i_1_n_0;
wire x_addr_out2_carry__2_i_2_n_0;
wire x_addr_out2_carry__2_i_3_n_0;
wire x_addr_out2_carry__2_i_4_n_0;
wire x_addr_out2_carry__2_n_0;
wire x_addr_out2_carry__2_n_1;
wire x_addr_out2_carry__2_n_2;
wire x_addr_out2_carry__2_n_3;
wire x_addr_out2_carry__3_i_1_n_0;
wire x_addr_out2_carry__3_i_2_n_0;
wire x_addr_out2_carry__3_i_3_n_0;
wire x_addr_out2_carry__3_i_4_n_0;
wire x_addr_out2_carry__3_n_0;
wire x_addr_out2_carry__3_n_1;
wire x_addr_out2_carry__3_n_2;
wire x_addr_out2_carry__3_n_3;
wire x_addr_out2_carry__4_i_1_n_0;
wire x_addr_out2_carry__4_i_2_n_0;
wire x_addr_out2_carry__4_i_3_n_0;
wire x_addr_out2_carry__4_i_4_n_0;
wire x_addr_out2_carry__4_n_0;
wire x_addr_out2_carry__4_n_1;
wire x_addr_out2_carry__4_n_2;
wire x_addr_out2_carry__4_n_3;
wire x_addr_out2_carry__5_i_1_n_0;
wire x_addr_out2_carry__5_i_2_n_0;
wire x_addr_out2_carry__5_i_3_n_0;
wire x_addr_out2_carry__5_i_4_n_0;
wire x_addr_out2_carry__5_n_0;
wire x_addr_out2_carry__5_n_1;
wire x_addr_out2_carry__5_n_2;
wire x_addr_out2_carry__5_n_3;
wire x_addr_out2_carry__6_i_1_n_0;
wire x_addr_out2_carry__6_i_2_n_0;
wire x_addr_out2_carry__6_i_3_n_0;
wire x_addr_out2_carry__6_i_4_n_0;
wire x_addr_out2_carry__6_n_0;
wire x_addr_out2_carry__6_n_1;
wire x_addr_out2_carry__6_n_2;
wire x_addr_out2_carry__6_n_3;
wire x_addr_out2_carry__7_i_1_n_0;
wire x_addr_out2_carry__7_i_2_n_0;
wire x_addr_out2_carry__7_i_3_n_0;
wire x_addr_out2_carry__7_i_4_n_0;
wire x_addr_out2_carry__7_n_0;
wire x_addr_out2_carry__7_n_1;
wire x_addr_out2_carry__7_n_2;
wire x_addr_out2_carry__7_n_3;
wire x_addr_out2_carry__8_i_1_n_0;
wire x_addr_out2_carry__8_i_2_n_0;
wire x_addr_out2_carry__8_n_3;
wire x_addr_out2_carry_i_1_n_0;
wire x_addr_out2_carry_i_2_n_0;
wire x_addr_out2_carry_i_3_n_0;
wire x_addr_out2_carry_i_4_n_0;
wire x_addr_out2_carry_n_0;
wire x_addr_out2_carry_n_1;
wire x_addr_out2_carry_n_2;
wire x_addr_out2_carry_n_3;
wire x_addr_out3__0_n_100;
wire x_addr_out3__0_n_101;
wire x_addr_out3__0_n_102;
wire x_addr_out3__0_n_103;
wire x_addr_out3__0_n_104;
wire x_addr_out3__0_n_105;
wire x_addr_out3__0_n_58;
wire x_addr_out3__0_n_59;
wire x_addr_out3__0_n_60;
wire x_addr_out3__0_n_61;
wire x_addr_out3__0_n_62;
wire x_addr_out3__0_n_63;
wire x_addr_out3__0_n_64;
wire x_addr_out3__0_n_65;
wire x_addr_out3__0_n_66;
wire x_addr_out3__0_n_67;
wire x_addr_out3__0_n_68;
wire x_addr_out3__0_n_69;
wire x_addr_out3__0_n_70;
wire x_addr_out3__0_n_71;
wire x_addr_out3__0_n_72;
wire x_addr_out3__0_n_73;
wire x_addr_out3__0_n_74;
wire x_addr_out3__0_n_75;
wire x_addr_out3__0_n_76;
wire x_addr_out3__0_n_77;
wire x_addr_out3__0_n_78;
wire x_addr_out3__0_n_79;
wire x_addr_out3__0_n_80;
wire x_addr_out3__0_n_81;
wire x_addr_out3__0_n_82;
wire x_addr_out3__0_n_83;
wire x_addr_out3__0_n_84;
wire x_addr_out3__0_n_85;
wire x_addr_out3__0_n_86;
wire x_addr_out3__0_n_87;
wire x_addr_out3__0_n_88;
wire x_addr_out3__0_n_89;
wire x_addr_out3__0_n_90;
wire x_addr_out3__0_n_91;
wire x_addr_out3__0_n_92;
wire x_addr_out3__0_n_93;
wire x_addr_out3__0_n_94;
wire x_addr_out3__0_n_95;
wire x_addr_out3__0_n_96;
wire x_addr_out3__0_n_97;
wire x_addr_out3__0_n_98;
wire x_addr_out3__0_n_99;
wire x_addr_out3__1_n_100;
wire x_addr_out3__1_n_101;
wire x_addr_out3__1_n_102;
wire x_addr_out3__1_n_103;
wire x_addr_out3__1_n_104;
wire x_addr_out3__1_n_105;
wire x_addr_out3__1_n_106;
wire x_addr_out3__1_n_107;
wire x_addr_out3__1_n_108;
wire x_addr_out3__1_n_109;
wire x_addr_out3__1_n_110;
wire x_addr_out3__1_n_111;
wire x_addr_out3__1_n_112;
wire x_addr_out3__1_n_113;
wire x_addr_out3__1_n_114;
wire x_addr_out3__1_n_115;
wire x_addr_out3__1_n_116;
wire x_addr_out3__1_n_117;
wire x_addr_out3__1_n_118;
wire x_addr_out3__1_n_119;
wire x_addr_out3__1_n_120;
wire x_addr_out3__1_n_121;
wire x_addr_out3__1_n_122;
wire x_addr_out3__1_n_123;
wire x_addr_out3__1_n_124;
wire x_addr_out3__1_n_125;
wire x_addr_out3__1_n_126;
wire x_addr_out3__1_n_127;
wire x_addr_out3__1_n_128;
wire x_addr_out3__1_n_129;
wire x_addr_out3__1_n_130;
wire x_addr_out3__1_n_131;
wire x_addr_out3__1_n_132;
wire x_addr_out3__1_n_133;
wire x_addr_out3__1_n_134;
wire x_addr_out3__1_n_135;
wire x_addr_out3__1_n_136;
wire x_addr_out3__1_n_137;
wire x_addr_out3__1_n_138;
wire x_addr_out3__1_n_139;
wire x_addr_out3__1_n_140;
wire x_addr_out3__1_n_141;
wire x_addr_out3__1_n_142;
wire x_addr_out3__1_n_143;
wire x_addr_out3__1_n_144;
wire x_addr_out3__1_n_145;
wire x_addr_out3__1_n_146;
wire x_addr_out3__1_n_147;
wire x_addr_out3__1_n_148;
wire x_addr_out3__1_n_149;
wire x_addr_out3__1_n_150;
wire x_addr_out3__1_n_151;
wire x_addr_out3__1_n_152;
wire x_addr_out3__1_n_153;
wire x_addr_out3__1_n_58;
wire x_addr_out3__1_n_59;
wire x_addr_out3__1_n_60;
wire x_addr_out3__1_n_61;
wire x_addr_out3__1_n_62;
wire x_addr_out3__1_n_63;
wire x_addr_out3__1_n_64;
wire x_addr_out3__1_n_65;
wire x_addr_out3__1_n_66;
wire x_addr_out3__1_n_67;
wire x_addr_out3__1_n_68;
wire x_addr_out3__1_n_69;
wire x_addr_out3__1_n_70;
wire x_addr_out3__1_n_71;
wire x_addr_out3__1_n_72;
wire x_addr_out3__1_n_73;
wire x_addr_out3__1_n_74;
wire x_addr_out3__1_n_75;
wire x_addr_out3__1_n_76;
wire x_addr_out3__1_n_77;
wire x_addr_out3__1_n_78;
wire x_addr_out3__1_n_79;
wire x_addr_out3__1_n_80;
wire x_addr_out3__1_n_81;
wire x_addr_out3__1_n_82;
wire x_addr_out3__1_n_83;
wire x_addr_out3__1_n_84;
wire x_addr_out3__1_n_85;
wire x_addr_out3__1_n_86;
wire x_addr_out3__1_n_87;
wire x_addr_out3__1_n_88;
wire x_addr_out3__1_n_89;
wire x_addr_out3__1_n_90;
wire x_addr_out3__1_n_91;
wire x_addr_out3__1_n_92;
wire x_addr_out3__1_n_93;
wire x_addr_out3__1_n_94;
wire x_addr_out3__1_n_95;
wire x_addr_out3__1_n_96;
wire x_addr_out3__1_n_97;
wire x_addr_out3__1_n_98;
wire x_addr_out3__1_n_99;
wire x_addr_out3__2_n_100;
wire x_addr_out3__2_n_101;
wire x_addr_out3__2_n_102;
wire x_addr_out3__2_n_103;
wire x_addr_out3__2_n_104;
wire x_addr_out3__2_n_105;
wire x_addr_out3__2_n_58;
wire x_addr_out3__2_n_59;
wire x_addr_out3__2_n_60;
wire x_addr_out3__2_n_61;
wire x_addr_out3__2_n_62;
wire x_addr_out3__2_n_63;
wire x_addr_out3__2_n_64;
wire x_addr_out3__2_n_65;
wire x_addr_out3__2_n_66;
wire x_addr_out3__2_n_67;
wire x_addr_out3__2_n_68;
wire x_addr_out3__2_n_69;
wire x_addr_out3__2_n_70;
wire x_addr_out3__2_n_71;
wire x_addr_out3__2_n_72;
wire x_addr_out3__2_n_73;
wire x_addr_out3__2_n_74;
wire x_addr_out3__2_n_75;
wire x_addr_out3__2_n_76;
wire x_addr_out3__2_n_77;
wire x_addr_out3__2_n_78;
wire x_addr_out3__2_n_79;
wire x_addr_out3__2_n_80;
wire x_addr_out3__2_n_81;
wire x_addr_out3__2_n_82;
wire x_addr_out3__2_n_83;
wire x_addr_out3__2_n_84;
wire x_addr_out3__2_n_85;
wire x_addr_out3__2_n_86;
wire x_addr_out3__2_n_87;
wire x_addr_out3__2_n_88;
wire x_addr_out3__2_n_89;
wire x_addr_out3__2_n_90;
wire x_addr_out3__2_n_91;
wire x_addr_out3__2_n_92;
wire x_addr_out3__2_n_93;
wire x_addr_out3__2_n_94;
wire x_addr_out3__2_n_95;
wire x_addr_out3__2_n_96;
wire x_addr_out3__2_n_97;
wire x_addr_out3__2_n_98;
wire x_addr_out3__2_n_99;
wire x_addr_out3_n_100;
wire x_addr_out3_n_101;
wire x_addr_out3_n_102;
wire x_addr_out3_n_103;
wire x_addr_out3_n_104;
wire x_addr_out3_n_105;
wire x_addr_out3_n_106;
wire x_addr_out3_n_107;
wire x_addr_out3_n_108;
wire x_addr_out3_n_109;
wire x_addr_out3_n_110;
wire x_addr_out3_n_111;
wire x_addr_out3_n_112;
wire x_addr_out3_n_113;
wire x_addr_out3_n_114;
wire x_addr_out3_n_115;
wire x_addr_out3_n_116;
wire x_addr_out3_n_117;
wire x_addr_out3_n_118;
wire x_addr_out3_n_119;
wire x_addr_out3_n_120;
wire x_addr_out3_n_121;
wire x_addr_out3_n_122;
wire x_addr_out3_n_123;
wire x_addr_out3_n_124;
wire x_addr_out3_n_125;
wire x_addr_out3_n_126;
wire x_addr_out3_n_127;
wire x_addr_out3_n_128;
wire x_addr_out3_n_129;
wire x_addr_out3_n_130;
wire x_addr_out3_n_131;
wire x_addr_out3_n_132;
wire x_addr_out3_n_133;
wire x_addr_out3_n_134;
wire x_addr_out3_n_135;
wire x_addr_out3_n_136;
wire x_addr_out3_n_137;
wire x_addr_out3_n_138;
wire x_addr_out3_n_139;
wire x_addr_out3_n_140;
wire x_addr_out3_n_141;
wire x_addr_out3_n_142;
wire x_addr_out3_n_143;
wire x_addr_out3_n_144;
wire x_addr_out3_n_145;
wire x_addr_out3_n_146;
wire x_addr_out3_n_147;
wire x_addr_out3_n_148;
wire x_addr_out3_n_149;
wire x_addr_out3_n_150;
wire x_addr_out3_n_151;
wire x_addr_out3_n_152;
wire x_addr_out3_n_153;
wire x_addr_out3_n_58;
wire x_addr_out3_n_59;
wire x_addr_out3_n_60;
wire x_addr_out3_n_61;
wire x_addr_out3_n_62;
wire x_addr_out3_n_63;
wire x_addr_out3_n_64;
wire x_addr_out3_n_65;
wire x_addr_out3_n_66;
wire x_addr_out3_n_67;
wire x_addr_out3_n_68;
wire x_addr_out3_n_69;
wire x_addr_out3_n_70;
wire x_addr_out3_n_71;
wire x_addr_out3_n_72;
wire x_addr_out3_n_73;
wire x_addr_out3_n_74;
wire x_addr_out3_n_75;
wire x_addr_out3_n_76;
wire x_addr_out3_n_77;
wire x_addr_out3_n_78;
wire x_addr_out3_n_79;
wire x_addr_out3_n_80;
wire x_addr_out3_n_81;
wire x_addr_out3_n_82;
wire x_addr_out3_n_83;
wire x_addr_out3_n_84;
wire x_addr_out3_n_85;
wire x_addr_out3_n_86;
wire x_addr_out3_n_87;
wire x_addr_out3_n_88;
wire x_addr_out3_n_89;
wire x_addr_out3_n_90;
wire x_addr_out3_n_91;
wire x_addr_out3_n_92;
wire x_addr_out3_n_93;
wire x_addr_out3_n_94;
wire x_addr_out3_n_95;
wire x_addr_out3_n_96;
wire x_addr_out3_n_97;
wire x_addr_out3_n_98;
wire x_addr_out3_n_99;
wire \x_addr_out[0]_i_1_n_0 ;
wire \x_addr_out[1]_i_1_n_0 ;
wire \x_addr_out[2]_i_1_n_0 ;
wire \x_addr_out[3]_i_1_n_0 ;
wire \x_addr_out[4]_i_1_n_0 ;
wire \x_addr_out[5]_i_1_n_0 ;
wire \x_addr_out[6]_i_1_n_0 ;
wire \x_addr_out[7]_i_1_n_0 ;
wire \x_addr_out[8]_i_1_n_0 ;
wire \x_addr_out[9]_i_1_n_0 ;
wire [9:0]y_addr_in;
wire [9:0]y_addr_out;
wire y_addr_out0_carry__0_i_1_n_0;
wire y_addr_out0_carry__0_i_2_n_0;
wire y_addr_out0_carry__0_i_3_n_0;
wire y_addr_out0_carry__0_i_4_n_0;
wire y_addr_out0_carry__0_n_0;
wire y_addr_out0_carry__0_n_1;
wire y_addr_out0_carry__0_n_2;
wire y_addr_out0_carry__0_n_3;
wire y_addr_out0_carry__1_i_1_n_0;
wire y_addr_out0_carry__1_i_2_n_0;
wire y_addr_out0_carry__1_n_3;
wire y_addr_out0_carry_i_1_n_0;
wire y_addr_out0_carry_i_2_n_0;
wire y_addr_out0_carry_i_3_n_0;
wire y_addr_out0_carry_i_4_n_0;
wire y_addr_out0_carry_n_0;
wire y_addr_out0_carry_n_1;
wire y_addr_out0_carry_n_2;
wire y_addr_out0_carry_n_3;
wire [37:28]y_addr_out2;
wire y_addr_out2_carry__0_i_1_n_0;
wire y_addr_out2_carry__0_i_2_n_0;
wire y_addr_out2_carry__0_i_3_n_0;
wire y_addr_out2_carry__0_i_4_n_0;
wire y_addr_out2_carry__0_n_0;
wire y_addr_out2_carry__0_n_1;
wire y_addr_out2_carry__0_n_2;
wire y_addr_out2_carry__0_n_3;
wire y_addr_out2_carry__1_i_1_n_0;
wire y_addr_out2_carry__1_i_2_n_0;
wire y_addr_out2_carry__1_i_3_n_0;
wire y_addr_out2_carry__1_i_4_n_0;
wire y_addr_out2_carry__1_n_0;
wire y_addr_out2_carry__1_n_1;
wire y_addr_out2_carry__1_n_2;
wire y_addr_out2_carry__1_n_3;
wire y_addr_out2_carry__2_i_1_n_0;
wire y_addr_out2_carry__2_i_2_n_0;
wire y_addr_out2_carry__2_i_3_n_0;
wire y_addr_out2_carry__2_i_4_n_0;
wire y_addr_out2_carry__2_n_0;
wire y_addr_out2_carry__2_n_1;
wire y_addr_out2_carry__2_n_2;
wire y_addr_out2_carry__2_n_3;
wire y_addr_out2_carry__3_i_1_n_0;
wire y_addr_out2_carry__3_i_2_n_0;
wire y_addr_out2_carry__3_i_3_n_0;
wire y_addr_out2_carry__3_i_4_n_0;
wire y_addr_out2_carry__3_n_0;
wire y_addr_out2_carry__3_n_1;
wire y_addr_out2_carry__3_n_2;
wire y_addr_out2_carry__3_n_3;
wire y_addr_out2_carry__4_i_1_n_0;
wire y_addr_out2_carry__4_i_2_n_0;
wire y_addr_out2_carry__4_i_3_n_0;
wire y_addr_out2_carry__4_i_4_n_0;
wire y_addr_out2_carry__4_n_0;
wire y_addr_out2_carry__4_n_1;
wire y_addr_out2_carry__4_n_2;
wire y_addr_out2_carry__4_n_3;
wire y_addr_out2_carry__5_i_1_n_0;
wire y_addr_out2_carry__5_i_2_n_0;
wire y_addr_out2_carry__5_i_3_n_0;
wire y_addr_out2_carry__5_i_4_n_0;
wire y_addr_out2_carry__5_n_0;
wire y_addr_out2_carry__5_n_1;
wire y_addr_out2_carry__5_n_2;
wire y_addr_out2_carry__5_n_3;
wire y_addr_out2_carry__6_i_1_n_0;
wire y_addr_out2_carry__6_i_2_n_0;
wire y_addr_out2_carry__6_i_3_n_0;
wire y_addr_out2_carry__6_i_4_n_0;
wire y_addr_out2_carry__6_n_0;
wire y_addr_out2_carry__6_n_1;
wire y_addr_out2_carry__6_n_2;
wire y_addr_out2_carry__6_n_3;
wire y_addr_out2_carry__7_i_1_n_0;
wire y_addr_out2_carry__7_i_2_n_0;
wire y_addr_out2_carry__7_i_3_n_0;
wire y_addr_out2_carry__7_i_4_n_0;
wire y_addr_out2_carry__7_n_0;
wire y_addr_out2_carry__7_n_1;
wire y_addr_out2_carry__7_n_2;
wire y_addr_out2_carry__7_n_3;
wire y_addr_out2_carry__8_i_1_n_0;
wire y_addr_out2_carry__8_i_2_n_0;
wire y_addr_out2_carry__8_n_3;
wire y_addr_out2_carry_i_1_n_0;
wire y_addr_out2_carry_i_2_n_0;
wire y_addr_out2_carry_i_3_n_0;
wire y_addr_out2_carry_i_4_n_0;
wire y_addr_out2_carry_n_0;
wire y_addr_out2_carry_n_1;
wire y_addr_out2_carry_n_2;
wire y_addr_out2_carry_n_3;
wire y_addr_out3__0_n_100;
wire y_addr_out3__0_n_101;
wire y_addr_out3__0_n_102;
wire y_addr_out3__0_n_103;
wire y_addr_out3__0_n_104;
wire y_addr_out3__0_n_105;
wire y_addr_out3__0_n_58;
wire y_addr_out3__0_n_59;
wire y_addr_out3__0_n_60;
wire y_addr_out3__0_n_61;
wire y_addr_out3__0_n_62;
wire y_addr_out3__0_n_63;
wire y_addr_out3__0_n_64;
wire y_addr_out3__0_n_65;
wire y_addr_out3__0_n_66;
wire y_addr_out3__0_n_67;
wire y_addr_out3__0_n_68;
wire y_addr_out3__0_n_69;
wire y_addr_out3__0_n_70;
wire y_addr_out3__0_n_71;
wire y_addr_out3__0_n_72;
wire y_addr_out3__0_n_73;
wire y_addr_out3__0_n_74;
wire y_addr_out3__0_n_75;
wire y_addr_out3__0_n_76;
wire y_addr_out3__0_n_77;
wire y_addr_out3__0_n_78;
wire y_addr_out3__0_n_79;
wire y_addr_out3__0_n_80;
wire y_addr_out3__0_n_81;
wire y_addr_out3__0_n_82;
wire y_addr_out3__0_n_83;
wire y_addr_out3__0_n_84;
wire y_addr_out3__0_n_85;
wire y_addr_out3__0_n_86;
wire y_addr_out3__0_n_87;
wire y_addr_out3__0_n_88;
wire y_addr_out3__0_n_89;
wire y_addr_out3__0_n_90;
wire y_addr_out3__0_n_91;
wire y_addr_out3__0_n_92;
wire y_addr_out3__0_n_93;
wire y_addr_out3__0_n_94;
wire y_addr_out3__0_n_95;
wire y_addr_out3__0_n_96;
wire y_addr_out3__0_n_97;
wire y_addr_out3__0_n_98;
wire y_addr_out3__0_n_99;
wire y_addr_out3__1_n_100;
wire y_addr_out3__1_n_101;
wire y_addr_out3__1_n_102;
wire y_addr_out3__1_n_103;
wire y_addr_out3__1_n_104;
wire y_addr_out3__1_n_105;
wire y_addr_out3__1_n_106;
wire y_addr_out3__1_n_107;
wire y_addr_out3__1_n_108;
wire y_addr_out3__1_n_109;
wire y_addr_out3__1_n_110;
wire y_addr_out3__1_n_111;
wire y_addr_out3__1_n_112;
wire y_addr_out3__1_n_113;
wire y_addr_out3__1_n_114;
wire y_addr_out3__1_n_115;
wire y_addr_out3__1_n_116;
wire y_addr_out3__1_n_117;
wire y_addr_out3__1_n_118;
wire y_addr_out3__1_n_119;
wire y_addr_out3__1_n_120;
wire y_addr_out3__1_n_121;
wire y_addr_out3__1_n_122;
wire y_addr_out3__1_n_123;
wire y_addr_out3__1_n_124;
wire y_addr_out3__1_n_125;
wire y_addr_out3__1_n_126;
wire y_addr_out3__1_n_127;
wire y_addr_out3__1_n_128;
wire y_addr_out3__1_n_129;
wire y_addr_out3__1_n_130;
wire y_addr_out3__1_n_131;
wire y_addr_out3__1_n_132;
wire y_addr_out3__1_n_133;
wire y_addr_out3__1_n_134;
wire y_addr_out3__1_n_135;
wire y_addr_out3__1_n_136;
wire y_addr_out3__1_n_137;
wire y_addr_out3__1_n_138;
wire y_addr_out3__1_n_139;
wire y_addr_out3__1_n_140;
wire y_addr_out3__1_n_141;
wire y_addr_out3__1_n_142;
wire y_addr_out3__1_n_143;
wire y_addr_out3__1_n_144;
wire y_addr_out3__1_n_145;
wire y_addr_out3__1_n_146;
wire y_addr_out3__1_n_147;
wire y_addr_out3__1_n_148;
wire y_addr_out3__1_n_149;
wire y_addr_out3__1_n_150;
wire y_addr_out3__1_n_151;
wire y_addr_out3__1_n_152;
wire y_addr_out3__1_n_153;
wire y_addr_out3__1_n_58;
wire y_addr_out3__1_n_59;
wire y_addr_out3__1_n_60;
wire y_addr_out3__1_n_61;
wire y_addr_out3__1_n_62;
wire y_addr_out3__1_n_63;
wire y_addr_out3__1_n_64;
wire y_addr_out3__1_n_65;
wire y_addr_out3__1_n_66;
wire y_addr_out3__1_n_67;
wire y_addr_out3__1_n_68;
wire y_addr_out3__1_n_69;
wire y_addr_out3__1_n_70;
wire y_addr_out3__1_n_71;
wire y_addr_out3__1_n_72;
wire y_addr_out3__1_n_73;
wire y_addr_out3__1_n_74;
wire y_addr_out3__1_n_75;
wire y_addr_out3__1_n_76;
wire y_addr_out3__1_n_77;
wire y_addr_out3__1_n_78;
wire y_addr_out3__1_n_79;
wire y_addr_out3__1_n_80;
wire y_addr_out3__1_n_81;
wire y_addr_out3__1_n_82;
wire y_addr_out3__1_n_83;
wire y_addr_out3__1_n_84;
wire y_addr_out3__1_n_85;
wire y_addr_out3__1_n_86;
wire y_addr_out3__1_n_87;
wire y_addr_out3__1_n_88;
wire y_addr_out3__1_n_89;
wire y_addr_out3__1_n_90;
wire y_addr_out3__1_n_91;
wire y_addr_out3__1_n_92;
wire y_addr_out3__1_n_93;
wire y_addr_out3__1_n_94;
wire y_addr_out3__1_n_95;
wire y_addr_out3__1_n_96;
wire y_addr_out3__1_n_97;
wire y_addr_out3__1_n_98;
wire y_addr_out3__1_n_99;
wire y_addr_out3__2_n_100;
wire y_addr_out3__2_n_101;
wire y_addr_out3__2_n_102;
wire y_addr_out3__2_n_103;
wire y_addr_out3__2_n_104;
wire y_addr_out3__2_n_105;
wire y_addr_out3__2_n_58;
wire y_addr_out3__2_n_59;
wire y_addr_out3__2_n_60;
wire y_addr_out3__2_n_61;
wire y_addr_out3__2_n_62;
wire y_addr_out3__2_n_63;
wire y_addr_out3__2_n_64;
wire y_addr_out3__2_n_65;
wire y_addr_out3__2_n_66;
wire y_addr_out3__2_n_67;
wire y_addr_out3__2_n_68;
wire y_addr_out3__2_n_69;
wire y_addr_out3__2_n_70;
wire y_addr_out3__2_n_71;
wire y_addr_out3__2_n_72;
wire y_addr_out3__2_n_73;
wire y_addr_out3__2_n_74;
wire y_addr_out3__2_n_75;
wire y_addr_out3__2_n_76;
wire y_addr_out3__2_n_77;
wire y_addr_out3__2_n_78;
wire y_addr_out3__2_n_79;
wire y_addr_out3__2_n_80;
wire y_addr_out3__2_n_81;
wire y_addr_out3__2_n_82;
wire y_addr_out3__2_n_83;
wire y_addr_out3__2_n_84;
wire y_addr_out3__2_n_85;
wire y_addr_out3__2_n_86;
wire y_addr_out3__2_n_87;
wire y_addr_out3__2_n_88;
wire y_addr_out3__2_n_89;
wire y_addr_out3__2_n_90;
wire y_addr_out3__2_n_91;
wire y_addr_out3__2_n_92;
wire y_addr_out3__2_n_93;
wire y_addr_out3__2_n_94;
wire y_addr_out3__2_n_95;
wire y_addr_out3__2_n_96;
wire y_addr_out3__2_n_97;
wire y_addr_out3__2_n_98;
wire y_addr_out3__2_n_99;
wire y_addr_out3_n_100;
wire y_addr_out3_n_101;
wire y_addr_out3_n_102;
wire y_addr_out3_n_103;
wire y_addr_out3_n_104;
wire y_addr_out3_n_105;
wire y_addr_out3_n_106;
wire y_addr_out3_n_107;
wire y_addr_out3_n_108;
wire y_addr_out3_n_109;
wire y_addr_out3_n_110;
wire y_addr_out3_n_111;
wire y_addr_out3_n_112;
wire y_addr_out3_n_113;
wire y_addr_out3_n_114;
wire y_addr_out3_n_115;
wire y_addr_out3_n_116;
wire y_addr_out3_n_117;
wire y_addr_out3_n_118;
wire y_addr_out3_n_119;
wire y_addr_out3_n_120;
wire y_addr_out3_n_121;
wire y_addr_out3_n_122;
wire y_addr_out3_n_123;
wire y_addr_out3_n_124;
wire y_addr_out3_n_125;
wire y_addr_out3_n_126;
wire y_addr_out3_n_127;
wire y_addr_out3_n_128;
wire y_addr_out3_n_129;
wire y_addr_out3_n_130;
wire y_addr_out3_n_131;
wire y_addr_out3_n_132;
wire y_addr_out3_n_133;
wire y_addr_out3_n_134;
wire y_addr_out3_n_135;
wire y_addr_out3_n_136;
wire y_addr_out3_n_137;
wire y_addr_out3_n_138;
wire y_addr_out3_n_139;
wire y_addr_out3_n_140;
wire y_addr_out3_n_141;
wire y_addr_out3_n_142;
wire y_addr_out3_n_143;
wire y_addr_out3_n_144;
wire y_addr_out3_n_145;
wire y_addr_out3_n_146;
wire y_addr_out3_n_147;
wire y_addr_out3_n_148;
wire y_addr_out3_n_149;
wire y_addr_out3_n_150;
wire y_addr_out3_n_151;
wire y_addr_out3_n_152;
wire y_addr_out3_n_153;
wire y_addr_out3_n_58;
wire y_addr_out3_n_59;
wire y_addr_out3_n_60;
wire y_addr_out3_n_61;
wire y_addr_out3_n_62;
wire y_addr_out3_n_63;
wire y_addr_out3_n_64;
wire y_addr_out3_n_65;
wire y_addr_out3_n_66;
wire y_addr_out3_n_67;
wire y_addr_out3_n_68;
wire y_addr_out3_n_69;
wire y_addr_out3_n_70;
wire y_addr_out3_n_71;
wire y_addr_out3_n_72;
wire y_addr_out3_n_73;
wire y_addr_out3_n_74;
wire y_addr_out3_n_75;
wire y_addr_out3_n_76;
wire y_addr_out3_n_77;
wire y_addr_out3_n_78;
wire y_addr_out3_n_79;
wire y_addr_out3_n_80;
wire y_addr_out3_n_81;
wire y_addr_out3_n_82;
wire y_addr_out3_n_83;
wire y_addr_out3_n_84;
wire y_addr_out3_n_85;
wire y_addr_out3_n_86;
wire y_addr_out3_n_87;
wire y_addr_out3_n_88;
wire y_addr_out3_n_89;
wire y_addr_out3_n_90;
wire y_addr_out3_n_91;
wire y_addr_out3_n_92;
wire y_addr_out3_n_93;
wire y_addr_out3_n_94;
wire y_addr_out3_n_95;
wire y_addr_out3_n_96;
wire y_addr_out3_n_97;
wire y_addr_out3_n_98;
wire y_addr_out3_n_99;
wire [0:0]NLW_x_addr_out0_carry_O_UNCONNECTED;
wire [3:1]NLW_x_addr_out0_carry__1_CO_UNCONNECTED;
wire [3:2]NLW_x_addr_out0_carry__1_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry__0_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry__1_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry__2_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry__3_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry__4_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry__5_O_UNCONNECTED;
wire [3:1]NLW_x_addr_out2_carry__8_CO_UNCONNECTED;
wire [3:2]NLW_x_addr_out2_carry__8_O_UNCONNECTED;
wire NLW_x_addr_out3_CARRYCASCOUT_UNCONNECTED;
wire NLW_x_addr_out3_MULTSIGNOUT_UNCONNECTED;
wire NLW_x_addr_out3_OVERFLOW_UNCONNECTED;
wire NLW_x_addr_out3_PATTERNBDETECT_UNCONNECTED;
wire NLW_x_addr_out3_PATTERNDETECT_UNCONNECTED;
wire NLW_x_addr_out3_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_x_addr_out3_ACOUT_UNCONNECTED;
wire [17:0]NLW_x_addr_out3_BCOUT_UNCONNECTED;
wire [3:0]NLW_x_addr_out3_CARRYOUT_UNCONNECTED;
wire NLW_x_addr_out3__0_CARRYCASCOUT_UNCONNECTED;
wire NLW_x_addr_out3__0_MULTSIGNOUT_UNCONNECTED;
wire NLW_x_addr_out3__0_OVERFLOW_UNCONNECTED;
wire NLW_x_addr_out3__0_PATTERNBDETECT_UNCONNECTED;
wire NLW_x_addr_out3__0_PATTERNDETECT_UNCONNECTED;
wire NLW_x_addr_out3__0_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_x_addr_out3__0_ACOUT_UNCONNECTED;
wire [17:0]NLW_x_addr_out3__0_BCOUT_UNCONNECTED;
wire [3:0]NLW_x_addr_out3__0_CARRYOUT_UNCONNECTED;
wire [47:0]NLW_x_addr_out3__0_PCOUT_UNCONNECTED;
wire NLW_x_addr_out3__1_CARRYCASCOUT_UNCONNECTED;
wire NLW_x_addr_out3__1_MULTSIGNOUT_UNCONNECTED;
wire NLW_x_addr_out3__1_OVERFLOW_UNCONNECTED;
wire NLW_x_addr_out3__1_PATTERNBDETECT_UNCONNECTED;
wire NLW_x_addr_out3__1_PATTERNDETECT_UNCONNECTED;
wire NLW_x_addr_out3__1_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_x_addr_out3__1_ACOUT_UNCONNECTED;
wire [17:0]NLW_x_addr_out3__1_BCOUT_UNCONNECTED;
wire [3:0]NLW_x_addr_out3__1_CARRYOUT_UNCONNECTED;
wire NLW_x_addr_out3__2_CARRYCASCOUT_UNCONNECTED;
wire NLW_x_addr_out3__2_MULTSIGNOUT_UNCONNECTED;
wire NLW_x_addr_out3__2_OVERFLOW_UNCONNECTED;
wire NLW_x_addr_out3__2_PATTERNBDETECT_UNCONNECTED;
wire NLW_x_addr_out3__2_PATTERNDETECT_UNCONNECTED;
wire NLW_x_addr_out3__2_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_x_addr_out3__2_ACOUT_UNCONNECTED;
wire [17:0]NLW_x_addr_out3__2_BCOUT_UNCONNECTED;
wire [3:0]NLW_x_addr_out3__2_CARRYOUT_UNCONNECTED;
wire [47:0]NLW_x_addr_out3__2_PCOUT_UNCONNECTED;
wire [0:0]NLW_y_addr_out0_carry_O_UNCONNECTED;
wire [3:1]NLW_y_addr_out0_carry__1_CO_UNCONNECTED;
wire [3:2]NLW_y_addr_out0_carry__1_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry__0_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry__1_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry__2_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry__3_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry__4_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry__5_O_UNCONNECTED;
wire [3:1]NLW_y_addr_out2_carry__8_CO_UNCONNECTED;
wire [3:2]NLW_y_addr_out2_carry__8_O_UNCONNECTED;
wire NLW_y_addr_out3_CARRYCASCOUT_UNCONNECTED;
wire NLW_y_addr_out3_MULTSIGNOUT_UNCONNECTED;
wire NLW_y_addr_out3_OVERFLOW_UNCONNECTED;
wire NLW_y_addr_out3_PATTERNBDETECT_UNCONNECTED;
wire NLW_y_addr_out3_PATTERNDETECT_UNCONNECTED;
wire NLW_y_addr_out3_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_y_addr_out3_ACOUT_UNCONNECTED;
wire [17:0]NLW_y_addr_out3_BCOUT_UNCONNECTED;
wire [3:0]NLW_y_addr_out3_CARRYOUT_UNCONNECTED;
wire NLW_y_addr_out3__0_CARRYCASCOUT_UNCONNECTED;
wire NLW_y_addr_out3__0_MULTSIGNOUT_UNCONNECTED;
wire NLW_y_addr_out3__0_OVERFLOW_UNCONNECTED;
wire NLW_y_addr_out3__0_PATTERNBDETECT_UNCONNECTED;
wire NLW_y_addr_out3__0_PATTERNDETECT_UNCONNECTED;
wire NLW_y_addr_out3__0_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_y_addr_out3__0_ACOUT_UNCONNECTED;
wire [17:0]NLW_y_addr_out3__0_BCOUT_UNCONNECTED;
wire [3:0]NLW_y_addr_out3__0_CARRYOUT_UNCONNECTED;
wire [47:0]NLW_y_addr_out3__0_PCOUT_UNCONNECTED;
wire NLW_y_addr_out3__1_CARRYCASCOUT_UNCONNECTED;
wire NLW_y_addr_out3__1_MULTSIGNOUT_UNCONNECTED;
wire NLW_y_addr_out3__1_OVERFLOW_UNCONNECTED;
wire NLW_y_addr_out3__1_PATTERNBDETECT_UNCONNECTED;
wire NLW_y_addr_out3__1_PATTERNDETECT_UNCONNECTED;
wire NLW_y_addr_out3__1_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_y_addr_out3__1_ACOUT_UNCONNECTED;
wire [17:0]NLW_y_addr_out3__1_BCOUT_UNCONNECTED;
wire [3:0]NLW_y_addr_out3__1_CARRYOUT_UNCONNECTED;
wire NLW_y_addr_out3__2_CARRYCASCOUT_UNCONNECTED;
wire NLW_y_addr_out3__2_MULTSIGNOUT_UNCONNECTED;
wire NLW_y_addr_out3__2_OVERFLOW_UNCONNECTED;
wire NLW_y_addr_out3__2_PATTERNBDETECT_UNCONNECTED;
wire NLW_y_addr_out3__2_PATTERNDETECT_UNCONNECTED;
wire NLW_y_addr_out3__2_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_y_addr_out3__2_ACOUT_UNCONNECTED;
wire [17:0]NLW_y_addr_out3__2_BCOUT_UNCONNECTED;
wire [3:0]NLW_y_addr_out3__2_CARRYOUT_UNCONNECTED;
wire [47:0]NLW_y_addr_out3__2_PCOUT_UNCONNECTED;
CARRY4 x_addr_out0_carry
(.CI(1'b0),
.CO({x_addr_out0_carry_n_0,x_addr_out0_carry_n_1,x_addr_out0_carry_n_2,x_addr_out0_carry_n_3}),
.CYINIT(1'b0),
.DI(p_1_in[17:14]),
.O({x_addr_out0[17:15],NLW_x_addr_out0_carry_O_UNCONNECTED[0]}),
.S({x_addr_out0_carry_i_1_n_0,x_addr_out0_carry_i_2_n_0,x_addr_out0_carry_i_3_n_0,x_addr_out0[14]}));
CARRY4 x_addr_out0_carry__0
(.CI(x_addr_out0_carry_n_0),
.CO({x_addr_out0_carry__0_n_0,x_addr_out0_carry__0_n_1,x_addr_out0_carry__0_n_2,x_addr_out0_carry__0_n_3}),
.CYINIT(1'b0),
.DI(p_1_in[21:18]),
.O(x_addr_out0[21:18]),
.S({x_addr_out0_carry__0_i_1_n_0,x_addr_out0_carry__0_i_2_n_0,x_addr_out0_carry__0_i_3_n_0,x_addr_out0_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry__0_i_1
(.I0(p_1_in[21]),
.I1(t_x[7]),
.O(x_addr_out0_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry__0_i_2
(.I0(p_1_in[20]),
.I1(t_x[6]),
.O(x_addr_out0_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry__0_i_3
(.I0(p_1_in[19]),
.I1(t_x[5]),
.O(x_addr_out0_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry__0_i_4
(.I0(p_1_in[18]),
.I1(t_x[4]),
.O(x_addr_out0_carry__0_i_4_n_0));
CARRY4 x_addr_out0_carry__1
(.CI(x_addr_out0_carry__0_n_0),
.CO({NLW_x_addr_out0_carry__1_CO_UNCONNECTED[3:1],x_addr_out0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,p_1_in[22]}),
.O({NLW_x_addr_out0_carry__1_O_UNCONNECTED[3:2],x_addr_out0[23:22]}),
.S({1'b0,1'b0,x_addr_out0_carry__1_i_1_n_0,x_addr_out0_carry__1_i_2_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry__1_i_1
(.I0(p_1_in[23]),
.I1(t_x[9]),
.O(x_addr_out0_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry__1_i_2
(.I0(p_1_in[22]),
.I1(t_x[8]),
.O(x_addr_out0_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry_i_1
(.I0(p_1_in[17]),
.I1(t_x[3]),
.O(x_addr_out0_carry_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry_i_2
(.I0(p_1_in[16]),
.I1(t_x[2]),
.O(x_addr_out0_carry_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry_i_3
(.I0(p_1_in[15]),
.I1(t_x[1]),
.O(x_addr_out0_carry_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry_i_4
(.I0(p_1_in[14]),
.I1(t_x[0]),
.O(x_addr_out0[14]));
CARRY4 x_addr_out2_carry
(.CI(1'b0),
.CO({x_addr_out2_carry_n_0,x_addr_out2_carry_n_1,x_addr_out2_carry_n_2,x_addr_out2_carry_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__1_n_102,x_addr_out3__1_n_103,x_addr_out3__1_n_104,x_addr_out3__1_n_105}),
.O(NLW_x_addr_out2_carry_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry_i_1_n_0,x_addr_out2_carry_i_2_n_0,x_addr_out2_carry_i_3_n_0,x_addr_out2_carry_i_4_n_0}));
CARRY4 x_addr_out2_carry__0
(.CI(x_addr_out2_carry_n_0),
.CO({x_addr_out2_carry__0_n_0,x_addr_out2_carry__0_n_1,x_addr_out2_carry__0_n_2,x_addr_out2_carry__0_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__1_n_98,x_addr_out3__1_n_99,x_addr_out3__1_n_100,x_addr_out3__1_n_101}),
.O(NLW_x_addr_out2_carry__0_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry__0_i_1_n_0,x_addr_out2_carry__0_i_2_n_0,x_addr_out2_carry__0_i_3_n_0,x_addr_out2_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__0_i_1
(.I0(x_addr_out3__1_n_98),
.I1(x_addr_out3_n_98),
.O(x_addr_out2_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__0_i_2
(.I0(x_addr_out3__1_n_99),
.I1(x_addr_out3_n_99),
.O(x_addr_out2_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__0_i_3
(.I0(x_addr_out3__1_n_100),
.I1(x_addr_out3_n_100),
.O(x_addr_out2_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__0_i_4
(.I0(x_addr_out3__1_n_101),
.I1(x_addr_out3_n_101),
.O(x_addr_out2_carry__0_i_4_n_0));
CARRY4 x_addr_out2_carry__1
(.CI(x_addr_out2_carry__0_n_0),
.CO({x_addr_out2_carry__1_n_0,x_addr_out2_carry__1_n_1,x_addr_out2_carry__1_n_2,x_addr_out2_carry__1_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__1_n_94,x_addr_out3__1_n_95,x_addr_out3__1_n_96,x_addr_out3__1_n_97}),
.O(NLW_x_addr_out2_carry__1_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry__1_i_1_n_0,x_addr_out2_carry__1_i_2_n_0,x_addr_out2_carry__1_i_3_n_0,x_addr_out2_carry__1_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__1_i_1
(.I0(x_addr_out3__1_n_94),
.I1(x_addr_out3_n_94),
.O(x_addr_out2_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__1_i_2
(.I0(x_addr_out3__1_n_95),
.I1(x_addr_out3_n_95),
.O(x_addr_out2_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__1_i_3
(.I0(x_addr_out3__1_n_96),
.I1(x_addr_out3_n_96),
.O(x_addr_out2_carry__1_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__1_i_4
(.I0(x_addr_out3__1_n_97),
.I1(x_addr_out3_n_97),
.O(x_addr_out2_carry__1_i_4_n_0));
CARRY4 x_addr_out2_carry__2
(.CI(x_addr_out2_carry__1_n_0),
.CO({x_addr_out2_carry__2_n_0,x_addr_out2_carry__2_n_1,x_addr_out2_carry__2_n_2,x_addr_out2_carry__2_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__1_n_90,x_addr_out3__1_n_91,x_addr_out3__1_n_92,x_addr_out3__1_n_93}),
.O(NLW_x_addr_out2_carry__2_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry__2_i_1_n_0,x_addr_out2_carry__2_i_2_n_0,x_addr_out2_carry__2_i_3_n_0,x_addr_out2_carry__2_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__2_i_1
(.I0(x_addr_out3__1_n_90),
.I1(x_addr_out3_n_90),
.O(x_addr_out2_carry__2_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__2_i_2
(.I0(x_addr_out3__1_n_91),
.I1(x_addr_out3_n_91),
.O(x_addr_out2_carry__2_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__2_i_3
(.I0(x_addr_out3__1_n_92),
.I1(x_addr_out3_n_92),
.O(x_addr_out2_carry__2_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__2_i_4
(.I0(x_addr_out3__1_n_93),
.I1(x_addr_out3_n_93),
.O(x_addr_out2_carry__2_i_4_n_0));
CARRY4 x_addr_out2_carry__3
(.CI(x_addr_out2_carry__2_n_0),
.CO({x_addr_out2_carry__3_n_0,x_addr_out2_carry__3_n_1,x_addr_out2_carry__3_n_2,x_addr_out2_carry__3_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__2_n_103,x_addr_out3__2_n_104,x_addr_out3__2_n_105,x_addr_out3__1_n_89}),
.O(NLW_x_addr_out2_carry__3_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry__3_i_1_n_0,x_addr_out2_carry__3_i_2_n_0,x_addr_out2_carry__3_i_3_n_0,x_addr_out2_carry__3_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__3_i_1
(.I0(x_addr_out3__2_n_103),
.I1(x_addr_out3__0_n_103),
.O(x_addr_out2_carry__3_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__3_i_2
(.I0(x_addr_out3__2_n_104),
.I1(x_addr_out3__0_n_104),
.O(x_addr_out2_carry__3_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__3_i_3
(.I0(x_addr_out3__2_n_105),
.I1(x_addr_out3__0_n_105),
.O(x_addr_out2_carry__3_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__3_i_4
(.I0(x_addr_out3__1_n_89),
.I1(x_addr_out3_n_89),
.O(x_addr_out2_carry__3_i_4_n_0));
CARRY4 x_addr_out2_carry__4
(.CI(x_addr_out2_carry__3_n_0),
.CO({x_addr_out2_carry__4_n_0,x_addr_out2_carry__4_n_1,x_addr_out2_carry__4_n_2,x_addr_out2_carry__4_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__2_n_99,x_addr_out3__2_n_100,x_addr_out3__2_n_101,x_addr_out3__2_n_102}),
.O(NLW_x_addr_out2_carry__4_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry__4_i_1_n_0,x_addr_out2_carry__4_i_2_n_0,x_addr_out2_carry__4_i_3_n_0,x_addr_out2_carry__4_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__4_i_1
(.I0(x_addr_out3__2_n_99),
.I1(x_addr_out3__0_n_99),
.O(x_addr_out2_carry__4_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__4_i_2
(.I0(x_addr_out3__2_n_100),
.I1(x_addr_out3__0_n_100),
.O(x_addr_out2_carry__4_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__4_i_3
(.I0(x_addr_out3__2_n_101),
.I1(x_addr_out3__0_n_101),
.O(x_addr_out2_carry__4_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__4_i_4
(.I0(x_addr_out3__2_n_102),
.I1(x_addr_out3__0_n_102),
.O(x_addr_out2_carry__4_i_4_n_0));
CARRY4 x_addr_out2_carry__5
(.CI(x_addr_out2_carry__4_n_0),
.CO({x_addr_out2_carry__5_n_0,x_addr_out2_carry__5_n_1,x_addr_out2_carry__5_n_2,x_addr_out2_carry__5_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__2_n_95,x_addr_out3__2_n_96,x_addr_out3__2_n_97,x_addr_out3__2_n_98}),
.O(NLW_x_addr_out2_carry__5_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry__5_i_1_n_0,x_addr_out2_carry__5_i_2_n_0,x_addr_out2_carry__5_i_3_n_0,x_addr_out2_carry__5_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__5_i_1
(.I0(x_addr_out3__2_n_95),
.I1(x_addr_out3__0_n_95),
.O(x_addr_out2_carry__5_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__5_i_2
(.I0(x_addr_out3__2_n_96),
.I1(x_addr_out3__0_n_96),
.O(x_addr_out2_carry__5_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__5_i_3
(.I0(x_addr_out3__2_n_97),
.I1(x_addr_out3__0_n_97),
.O(x_addr_out2_carry__5_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__5_i_4
(.I0(x_addr_out3__2_n_98),
.I1(x_addr_out3__0_n_98),
.O(x_addr_out2_carry__5_i_4_n_0));
CARRY4 x_addr_out2_carry__6
(.CI(x_addr_out2_carry__5_n_0),
.CO({x_addr_out2_carry__6_n_0,x_addr_out2_carry__6_n_1,x_addr_out2_carry__6_n_2,x_addr_out2_carry__6_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__2_n_91,x_addr_out3__2_n_92,x_addr_out3__2_n_93,x_addr_out3__2_n_94}),
.O(p_1_in[17:14]),
.S({x_addr_out2_carry__6_i_1_n_0,x_addr_out2_carry__6_i_2_n_0,x_addr_out2_carry__6_i_3_n_0,x_addr_out2_carry__6_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__6_i_1
(.I0(x_addr_out3__2_n_91),
.I1(x_addr_out3__0_n_91),
.O(x_addr_out2_carry__6_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__6_i_2
(.I0(x_addr_out3__2_n_92),
.I1(x_addr_out3__0_n_92),
.O(x_addr_out2_carry__6_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__6_i_3
(.I0(x_addr_out3__2_n_93),
.I1(x_addr_out3__0_n_93),
.O(x_addr_out2_carry__6_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__6_i_4
(.I0(x_addr_out3__2_n_94),
.I1(x_addr_out3__0_n_94),
.O(x_addr_out2_carry__6_i_4_n_0));
CARRY4 x_addr_out2_carry__7
(.CI(x_addr_out2_carry__6_n_0),
.CO({x_addr_out2_carry__7_n_0,x_addr_out2_carry__7_n_1,x_addr_out2_carry__7_n_2,x_addr_out2_carry__7_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__2_n_87,x_addr_out3__2_n_88,x_addr_out3__2_n_89,x_addr_out3__2_n_90}),
.O(p_1_in[21:18]),
.S({x_addr_out2_carry__7_i_1_n_0,x_addr_out2_carry__7_i_2_n_0,x_addr_out2_carry__7_i_3_n_0,x_addr_out2_carry__7_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__7_i_1
(.I0(x_addr_out3__2_n_87),
.I1(x_addr_out3__0_n_87),
.O(x_addr_out2_carry__7_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__7_i_2
(.I0(x_addr_out3__2_n_88),
.I1(x_addr_out3__0_n_88),
.O(x_addr_out2_carry__7_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__7_i_3
(.I0(x_addr_out3__2_n_89),
.I1(x_addr_out3__0_n_89),
.O(x_addr_out2_carry__7_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__7_i_4
(.I0(x_addr_out3__2_n_90),
.I1(x_addr_out3__0_n_90),
.O(x_addr_out2_carry__7_i_4_n_0));
CARRY4 x_addr_out2_carry__8
(.CI(x_addr_out2_carry__7_n_0),
.CO({NLW_x_addr_out2_carry__8_CO_UNCONNECTED[3:1],x_addr_out2_carry__8_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,x_addr_out3__2_n_86}),
.O({NLW_x_addr_out2_carry__8_O_UNCONNECTED[3:2],p_1_in[23:22]}),
.S({1'b0,1'b0,x_addr_out2_carry__8_i_1_n_0,x_addr_out2_carry__8_i_2_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__8_i_1
(.I0(x_addr_out3__2_n_85),
.I1(x_addr_out3__0_n_85),
.O(x_addr_out2_carry__8_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__8_i_2
(.I0(x_addr_out3__2_n_86),
.I1(x_addr_out3__0_n_86),
.O(x_addr_out2_carry__8_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry_i_1
(.I0(x_addr_out3__1_n_102),
.I1(x_addr_out3_n_102),
.O(x_addr_out2_carry_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry_i_2
(.I0(x_addr_out3__1_n_103),
.I1(x_addr_out3_n_103),
.O(x_addr_out2_carry_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry_i_3
(.I0(x_addr_out3__1_n_104),
.I1(x_addr_out3_n_104),
.O(x_addr_out2_carry_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry_i_4
(.I0(x_addr_out3__1_n_105),
.I1(x_addr_out3_n_105),
.O(x_addr_out2_carry_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
x_addr_out3
(.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,y_addr_in[2:0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_x_addr_out3_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({rot_m01[15],rot_m01[15],rot_m01}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_x_addr_out3_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_x_addr_out3_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_x_addr_out3_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_x_addr_out3_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_x_addr_out3_OVERFLOW_UNCONNECTED),
.P({x_addr_out3_n_58,x_addr_out3_n_59,x_addr_out3_n_60,x_addr_out3_n_61,x_addr_out3_n_62,x_addr_out3_n_63,x_addr_out3_n_64,x_addr_out3_n_65,x_addr_out3_n_66,x_addr_out3_n_67,x_addr_out3_n_68,x_addr_out3_n_69,x_addr_out3_n_70,x_addr_out3_n_71,x_addr_out3_n_72,x_addr_out3_n_73,x_addr_out3_n_74,x_addr_out3_n_75,x_addr_out3_n_76,x_addr_out3_n_77,x_addr_out3_n_78,x_addr_out3_n_79,x_addr_out3_n_80,x_addr_out3_n_81,x_addr_out3_n_82,x_addr_out3_n_83,x_addr_out3_n_84,x_addr_out3_n_85,x_addr_out3_n_86,x_addr_out3_n_87,x_addr_out3_n_88,x_addr_out3_n_89,x_addr_out3_n_90,x_addr_out3_n_91,x_addr_out3_n_92,x_addr_out3_n_93,x_addr_out3_n_94,x_addr_out3_n_95,x_addr_out3_n_96,x_addr_out3_n_97,x_addr_out3_n_98,x_addr_out3_n_99,x_addr_out3_n_100,x_addr_out3_n_101,x_addr_out3_n_102,x_addr_out3_n_103,x_addr_out3_n_104,x_addr_out3_n_105}),
.PATTERNBDETECT(NLW_x_addr_out3_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_x_addr_out3_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT({x_addr_out3_n_106,x_addr_out3_n_107,x_addr_out3_n_108,x_addr_out3_n_109,x_addr_out3_n_110,x_addr_out3_n_111,x_addr_out3_n_112,x_addr_out3_n_113,x_addr_out3_n_114,x_addr_out3_n_115,x_addr_out3_n_116,x_addr_out3_n_117,x_addr_out3_n_118,x_addr_out3_n_119,x_addr_out3_n_120,x_addr_out3_n_121,x_addr_out3_n_122,x_addr_out3_n_123,x_addr_out3_n_124,x_addr_out3_n_125,x_addr_out3_n_126,x_addr_out3_n_127,x_addr_out3_n_128,x_addr_out3_n_129,x_addr_out3_n_130,x_addr_out3_n_131,x_addr_out3_n_132,x_addr_out3_n_133,x_addr_out3_n_134,x_addr_out3_n_135,x_addr_out3_n_136,x_addr_out3_n_137,x_addr_out3_n_138,x_addr_out3_n_139,x_addr_out3_n_140,x_addr_out3_n_141,x_addr_out3_n_142,x_addr_out3_n_143,x_addr_out3_n_144,x_addr_out3_n_145,x_addr_out3_n_146,x_addr_out3_n_147,x_addr_out3_n_148,x_addr_out3_n_149,x_addr_out3_n_150,x_addr_out3_n_151,x_addr_out3_n_152,x_addr_out3_n_153}),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_x_addr_out3_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
x_addr_out3__0
(.A({rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_x_addr_out3__0_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,y_addr_in[9:3]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_x_addr_out3__0_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_x_addr_out3__0_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_x_addr_out3__0_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_x_addr_out3__0_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b1,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_x_addr_out3__0_OVERFLOW_UNCONNECTED),
.P({x_addr_out3__0_n_58,x_addr_out3__0_n_59,x_addr_out3__0_n_60,x_addr_out3__0_n_61,x_addr_out3__0_n_62,x_addr_out3__0_n_63,x_addr_out3__0_n_64,x_addr_out3__0_n_65,x_addr_out3__0_n_66,x_addr_out3__0_n_67,x_addr_out3__0_n_68,x_addr_out3__0_n_69,x_addr_out3__0_n_70,x_addr_out3__0_n_71,x_addr_out3__0_n_72,x_addr_out3__0_n_73,x_addr_out3__0_n_74,x_addr_out3__0_n_75,x_addr_out3__0_n_76,x_addr_out3__0_n_77,x_addr_out3__0_n_78,x_addr_out3__0_n_79,x_addr_out3__0_n_80,x_addr_out3__0_n_81,x_addr_out3__0_n_82,x_addr_out3__0_n_83,x_addr_out3__0_n_84,x_addr_out3__0_n_85,x_addr_out3__0_n_86,x_addr_out3__0_n_87,x_addr_out3__0_n_88,x_addr_out3__0_n_89,x_addr_out3__0_n_90,x_addr_out3__0_n_91,x_addr_out3__0_n_92,x_addr_out3__0_n_93,x_addr_out3__0_n_94,x_addr_out3__0_n_95,x_addr_out3__0_n_96,x_addr_out3__0_n_97,x_addr_out3__0_n_98,x_addr_out3__0_n_99,x_addr_out3__0_n_100,x_addr_out3__0_n_101,x_addr_out3__0_n_102,x_addr_out3__0_n_103,x_addr_out3__0_n_104,x_addr_out3__0_n_105}),
.PATTERNBDETECT(NLW_x_addr_out3__0_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_x_addr_out3__0_PATTERNDETECT_UNCONNECTED),
.PCIN({x_addr_out3_n_106,x_addr_out3_n_107,x_addr_out3_n_108,x_addr_out3_n_109,x_addr_out3_n_110,x_addr_out3_n_111,x_addr_out3_n_112,x_addr_out3_n_113,x_addr_out3_n_114,x_addr_out3_n_115,x_addr_out3_n_116,x_addr_out3_n_117,x_addr_out3_n_118,x_addr_out3_n_119,x_addr_out3_n_120,x_addr_out3_n_121,x_addr_out3_n_122,x_addr_out3_n_123,x_addr_out3_n_124,x_addr_out3_n_125,x_addr_out3_n_126,x_addr_out3_n_127,x_addr_out3_n_128,x_addr_out3_n_129,x_addr_out3_n_130,x_addr_out3_n_131,x_addr_out3_n_132,x_addr_out3_n_133,x_addr_out3_n_134,x_addr_out3_n_135,x_addr_out3_n_136,x_addr_out3_n_137,x_addr_out3_n_138,x_addr_out3_n_139,x_addr_out3_n_140,x_addr_out3_n_141,x_addr_out3_n_142,x_addr_out3_n_143,x_addr_out3_n_144,x_addr_out3_n_145,x_addr_out3_n_146,x_addr_out3_n_147,x_addr_out3_n_148,x_addr_out3_n_149,x_addr_out3_n_150,x_addr_out3_n_151,x_addr_out3_n_152,x_addr_out3_n_153}),
.PCOUT(NLW_x_addr_out3__0_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_x_addr_out3__0_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
x_addr_out3__1
(.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,x_addr_in[2:0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_x_addr_out3__1_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({rot_m00[15],rot_m00[15],rot_m00}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_x_addr_out3__1_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_x_addr_out3__1_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_x_addr_out3__1_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_x_addr_out3__1_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_x_addr_out3__1_OVERFLOW_UNCONNECTED),
.P({x_addr_out3__1_n_58,x_addr_out3__1_n_59,x_addr_out3__1_n_60,x_addr_out3__1_n_61,x_addr_out3__1_n_62,x_addr_out3__1_n_63,x_addr_out3__1_n_64,x_addr_out3__1_n_65,x_addr_out3__1_n_66,x_addr_out3__1_n_67,x_addr_out3__1_n_68,x_addr_out3__1_n_69,x_addr_out3__1_n_70,x_addr_out3__1_n_71,x_addr_out3__1_n_72,x_addr_out3__1_n_73,x_addr_out3__1_n_74,x_addr_out3__1_n_75,x_addr_out3__1_n_76,x_addr_out3__1_n_77,x_addr_out3__1_n_78,x_addr_out3__1_n_79,x_addr_out3__1_n_80,x_addr_out3__1_n_81,x_addr_out3__1_n_82,x_addr_out3__1_n_83,x_addr_out3__1_n_84,x_addr_out3__1_n_85,x_addr_out3__1_n_86,x_addr_out3__1_n_87,x_addr_out3__1_n_88,x_addr_out3__1_n_89,x_addr_out3__1_n_90,x_addr_out3__1_n_91,x_addr_out3__1_n_92,x_addr_out3__1_n_93,x_addr_out3__1_n_94,x_addr_out3__1_n_95,x_addr_out3__1_n_96,x_addr_out3__1_n_97,x_addr_out3__1_n_98,x_addr_out3__1_n_99,x_addr_out3__1_n_100,x_addr_out3__1_n_101,x_addr_out3__1_n_102,x_addr_out3__1_n_103,x_addr_out3__1_n_104,x_addr_out3__1_n_105}),
.PATTERNBDETECT(NLW_x_addr_out3__1_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_x_addr_out3__1_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT({x_addr_out3__1_n_106,x_addr_out3__1_n_107,x_addr_out3__1_n_108,x_addr_out3__1_n_109,x_addr_out3__1_n_110,x_addr_out3__1_n_111,x_addr_out3__1_n_112,x_addr_out3__1_n_113,x_addr_out3__1_n_114,x_addr_out3__1_n_115,x_addr_out3__1_n_116,x_addr_out3__1_n_117,x_addr_out3__1_n_118,x_addr_out3__1_n_119,x_addr_out3__1_n_120,x_addr_out3__1_n_121,x_addr_out3__1_n_122,x_addr_out3__1_n_123,x_addr_out3__1_n_124,x_addr_out3__1_n_125,x_addr_out3__1_n_126,x_addr_out3__1_n_127,x_addr_out3__1_n_128,x_addr_out3__1_n_129,x_addr_out3__1_n_130,x_addr_out3__1_n_131,x_addr_out3__1_n_132,x_addr_out3__1_n_133,x_addr_out3__1_n_134,x_addr_out3__1_n_135,x_addr_out3__1_n_136,x_addr_out3__1_n_137,x_addr_out3__1_n_138,x_addr_out3__1_n_139,x_addr_out3__1_n_140,x_addr_out3__1_n_141,x_addr_out3__1_n_142,x_addr_out3__1_n_143,x_addr_out3__1_n_144,x_addr_out3__1_n_145,x_addr_out3__1_n_146,x_addr_out3__1_n_147,x_addr_out3__1_n_148,x_addr_out3__1_n_149,x_addr_out3__1_n_150,x_addr_out3__1_n_151,x_addr_out3__1_n_152,x_addr_out3__1_n_153}),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_x_addr_out3__1_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
x_addr_out3__2
(.A({rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_x_addr_out3__2_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,x_addr_in[9:3]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_x_addr_out3__2_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_x_addr_out3__2_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_x_addr_out3__2_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_x_addr_out3__2_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b1,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_x_addr_out3__2_OVERFLOW_UNCONNECTED),
.P({x_addr_out3__2_n_58,x_addr_out3__2_n_59,x_addr_out3__2_n_60,x_addr_out3__2_n_61,x_addr_out3__2_n_62,x_addr_out3__2_n_63,x_addr_out3__2_n_64,x_addr_out3__2_n_65,x_addr_out3__2_n_66,x_addr_out3__2_n_67,x_addr_out3__2_n_68,x_addr_out3__2_n_69,x_addr_out3__2_n_70,x_addr_out3__2_n_71,x_addr_out3__2_n_72,x_addr_out3__2_n_73,x_addr_out3__2_n_74,x_addr_out3__2_n_75,x_addr_out3__2_n_76,x_addr_out3__2_n_77,x_addr_out3__2_n_78,x_addr_out3__2_n_79,x_addr_out3__2_n_80,x_addr_out3__2_n_81,x_addr_out3__2_n_82,x_addr_out3__2_n_83,x_addr_out3__2_n_84,x_addr_out3__2_n_85,x_addr_out3__2_n_86,x_addr_out3__2_n_87,x_addr_out3__2_n_88,x_addr_out3__2_n_89,x_addr_out3__2_n_90,x_addr_out3__2_n_91,x_addr_out3__2_n_92,x_addr_out3__2_n_93,x_addr_out3__2_n_94,x_addr_out3__2_n_95,x_addr_out3__2_n_96,x_addr_out3__2_n_97,x_addr_out3__2_n_98,x_addr_out3__2_n_99,x_addr_out3__2_n_100,x_addr_out3__2_n_101,x_addr_out3__2_n_102,x_addr_out3__2_n_103,x_addr_out3__2_n_104,x_addr_out3__2_n_105}),
.PATTERNBDETECT(NLW_x_addr_out3__2_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_x_addr_out3__2_PATTERNDETECT_UNCONNECTED),
.PCIN({x_addr_out3__1_n_106,x_addr_out3__1_n_107,x_addr_out3__1_n_108,x_addr_out3__1_n_109,x_addr_out3__1_n_110,x_addr_out3__1_n_111,x_addr_out3__1_n_112,x_addr_out3__1_n_113,x_addr_out3__1_n_114,x_addr_out3__1_n_115,x_addr_out3__1_n_116,x_addr_out3__1_n_117,x_addr_out3__1_n_118,x_addr_out3__1_n_119,x_addr_out3__1_n_120,x_addr_out3__1_n_121,x_addr_out3__1_n_122,x_addr_out3__1_n_123,x_addr_out3__1_n_124,x_addr_out3__1_n_125,x_addr_out3__1_n_126,x_addr_out3__1_n_127,x_addr_out3__1_n_128,x_addr_out3__1_n_129,x_addr_out3__1_n_130,x_addr_out3__1_n_131,x_addr_out3__1_n_132,x_addr_out3__1_n_133,x_addr_out3__1_n_134,x_addr_out3__1_n_135,x_addr_out3__1_n_136,x_addr_out3__1_n_137,x_addr_out3__1_n_138,x_addr_out3__1_n_139,x_addr_out3__1_n_140,x_addr_out3__1_n_141,x_addr_out3__1_n_142,x_addr_out3__1_n_143,x_addr_out3__1_n_144,x_addr_out3__1_n_145,x_addr_out3__1_n_146,x_addr_out3__1_n_147,x_addr_out3__1_n_148,x_addr_out3__1_n_149,x_addr_out3__1_n_150,x_addr_out3__1_n_151,x_addr_out3__1_n_152,x_addr_out3__1_n_153}),
.PCOUT(NLW_x_addr_out3__2_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_x_addr_out3__2_UNDERFLOW_UNCONNECTED));
LUT4 #(
.INIT(16'h66F0))
\x_addr_out[0]_i_1
(.I0(p_1_in[14]),
.I1(t_x[0]),
.I2(x_addr_in[0]),
.I3(enable),
.O(\x_addr_out[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[1]_i_1
(.I0(x_addr_out0[15]),
.I1(x_addr_in[1]),
.I2(enable),
.O(\x_addr_out[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[2]_i_1
(.I0(x_addr_out0[16]),
.I1(x_addr_in[2]),
.I2(enable),
.O(\x_addr_out[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[3]_i_1
(.I0(x_addr_out0[17]),
.I1(x_addr_in[3]),
.I2(enable),
.O(\x_addr_out[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[4]_i_1
(.I0(x_addr_out0[18]),
.I1(x_addr_in[4]),
.I2(enable),
.O(\x_addr_out[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[5]_i_1
(.I0(x_addr_out0[19]),
.I1(x_addr_in[5]),
.I2(enable),
.O(\x_addr_out[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[6]_i_1
(.I0(x_addr_out0[20]),
.I1(x_addr_in[6]),
.I2(enable),
.O(\x_addr_out[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[7]_i_1
(.I0(x_addr_out0[21]),
.I1(x_addr_in[7]),
.I2(enable),
.O(\x_addr_out[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[8]_i_1
(.I0(x_addr_out0[22]),
.I1(x_addr_in[8]),
.I2(enable),
.O(\x_addr_out[8]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAC))
\x_addr_out[9]_i_1
(.I0(x_addr_out0[23]),
.I1(x_addr_in[9]),
.I2(enable),
.O(\x_addr_out[9]_i_1_n_0 ));
FDRE \x_addr_out_reg[0]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[0]_i_1_n_0 ),
.Q(x_addr_out[0]),
.R(1'b0));
FDRE \x_addr_out_reg[1]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[1]_i_1_n_0 ),
.Q(x_addr_out[1]),
.R(1'b0));
FDRE \x_addr_out_reg[2]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[2]_i_1_n_0 ),
.Q(x_addr_out[2]),
.R(1'b0));
FDRE \x_addr_out_reg[3]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[3]_i_1_n_0 ),
.Q(x_addr_out[3]),
.R(1'b0));
FDRE \x_addr_out_reg[4]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[4]_i_1_n_0 ),
.Q(x_addr_out[4]),
.R(1'b0));
FDRE \x_addr_out_reg[5]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[5]_i_1_n_0 ),
.Q(x_addr_out[5]),
.R(1'b0));
FDRE \x_addr_out_reg[6]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[6]_i_1_n_0 ),
.Q(x_addr_out[6]),
.R(1'b0));
FDRE \x_addr_out_reg[7]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[7]_i_1_n_0 ),
.Q(x_addr_out[7]),
.R(1'b0));
FDRE \x_addr_out_reg[8]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[8]_i_1_n_0 ),
.Q(x_addr_out[8]),
.R(1'b0));
FDRE \x_addr_out_reg[9]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[9]_i_1_n_0 ),
.Q(x_addr_out[9]),
.R(1'b0));
CARRY4 y_addr_out0_carry
(.CI(1'b0),
.CO({y_addr_out0_carry_n_0,y_addr_out0_carry_n_1,y_addr_out0_carry_n_2,y_addr_out0_carry_n_3}),
.CYINIT(1'b0),
.DI(y_addr_out2[31:28]),
.O({p_0_in[3:1],NLW_y_addr_out0_carry_O_UNCONNECTED[0]}),
.S({y_addr_out0_carry_i_1_n_0,y_addr_out0_carry_i_2_n_0,y_addr_out0_carry_i_3_n_0,y_addr_out0_carry_i_4_n_0}));
CARRY4 y_addr_out0_carry__0
(.CI(y_addr_out0_carry_n_0),
.CO({y_addr_out0_carry__0_n_0,y_addr_out0_carry__0_n_1,y_addr_out0_carry__0_n_2,y_addr_out0_carry__0_n_3}),
.CYINIT(1'b0),
.DI(y_addr_out2[35:32]),
.O(p_0_in[7:4]),
.S({y_addr_out0_carry__0_i_1_n_0,y_addr_out0_carry__0_i_2_n_0,y_addr_out0_carry__0_i_3_n_0,y_addr_out0_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry__0_i_1
(.I0(y_addr_out2[35]),
.I1(t_y[7]),
.O(y_addr_out0_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry__0_i_2
(.I0(y_addr_out2[34]),
.I1(t_y[6]),
.O(y_addr_out0_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry__0_i_3
(.I0(y_addr_out2[33]),
.I1(t_y[5]),
.O(y_addr_out0_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry__0_i_4
(.I0(y_addr_out2[32]),
.I1(t_y[4]),
.O(y_addr_out0_carry__0_i_4_n_0));
CARRY4 y_addr_out0_carry__1
(.CI(y_addr_out0_carry__0_n_0),
.CO({NLW_y_addr_out0_carry__1_CO_UNCONNECTED[3:1],y_addr_out0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,y_addr_out2[36]}),
.O({NLW_y_addr_out0_carry__1_O_UNCONNECTED[3:2],p_0_in[9:8]}),
.S({1'b0,1'b0,y_addr_out0_carry__1_i_1_n_0,y_addr_out0_carry__1_i_2_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry__1_i_1
(.I0(y_addr_out2[37]),
.I1(t_y[9]),
.O(y_addr_out0_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry__1_i_2
(.I0(y_addr_out2[36]),
.I1(t_y[8]),
.O(y_addr_out0_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry_i_1
(.I0(y_addr_out2[31]),
.I1(t_y[3]),
.O(y_addr_out0_carry_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry_i_2
(.I0(y_addr_out2[30]),
.I1(t_y[2]),
.O(y_addr_out0_carry_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry_i_3
(.I0(y_addr_out2[29]),
.I1(t_y[1]),
.O(y_addr_out0_carry_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry_i_4
(.I0(y_addr_out2[28]),
.I1(t_y[0]),
.O(y_addr_out0_carry_i_4_n_0));
CARRY4 y_addr_out2_carry
(.CI(1'b0),
.CO({y_addr_out2_carry_n_0,y_addr_out2_carry_n_1,y_addr_out2_carry_n_2,y_addr_out2_carry_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__1_n_102,y_addr_out3__1_n_103,y_addr_out3__1_n_104,y_addr_out3__1_n_105}),
.O(NLW_y_addr_out2_carry_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry_i_1_n_0,y_addr_out2_carry_i_2_n_0,y_addr_out2_carry_i_3_n_0,y_addr_out2_carry_i_4_n_0}));
CARRY4 y_addr_out2_carry__0
(.CI(y_addr_out2_carry_n_0),
.CO({y_addr_out2_carry__0_n_0,y_addr_out2_carry__0_n_1,y_addr_out2_carry__0_n_2,y_addr_out2_carry__0_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__1_n_98,y_addr_out3__1_n_99,y_addr_out3__1_n_100,y_addr_out3__1_n_101}),
.O(NLW_y_addr_out2_carry__0_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry__0_i_1_n_0,y_addr_out2_carry__0_i_2_n_0,y_addr_out2_carry__0_i_3_n_0,y_addr_out2_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__0_i_1
(.I0(y_addr_out3__1_n_98),
.I1(y_addr_out3_n_98),
.O(y_addr_out2_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__0_i_2
(.I0(y_addr_out3__1_n_99),
.I1(y_addr_out3_n_99),
.O(y_addr_out2_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__0_i_3
(.I0(y_addr_out3__1_n_100),
.I1(y_addr_out3_n_100),
.O(y_addr_out2_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__0_i_4
(.I0(y_addr_out3__1_n_101),
.I1(y_addr_out3_n_101),
.O(y_addr_out2_carry__0_i_4_n_0));
CARRY4 y_addr_out2_carry__1
(.CI(y_addr_out2_carry__0_n_0),
.CO({y_addr_out2_carry__1_n_0,y_addr_out2_carry__1_n_1,y_addr_out2_carry__1_n_2,y_addr_out2_carry__1_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__1_n_94,y_addr_out3__1_n_95,y_addr_out3__1_n_96,y_addr_out3__1_n_97}),
.O(NLW_y_addr_out2_carry__1_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry__1_i_1_n_0,y_addr_out2_carry__1_i_2_n_0,y_addr_out2_carry__1_i_3_n_0,y_addr_out2_carry__1_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__1_i_1
(.I0(y_addr_out3__1_n_94),
.I1(y_addr_out3_n_94),
.O(y_addr_out2_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__1_i_2
(.I0(y_addr_out3__1_n_95),
.I1(y_addr_out3_n_95),
.O(y_addr_out2_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__1_i_3
(.I0(y_addr_out3__1_n_96),
.I1(y_addr_out3_n_96),
.O(y_addr_out2_carry__1_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__1_i_4
(.I0(y_addr_out3__1_n_97),
.I1(y_addr_out3_n_97),
.O(y_addr_out2_carry__1_i_4_n_0));
CARRY4 y_addr_out2_carry__2
(.CI(y_addr_out2_carry__1_n_0),
.CO({y_addr_out2_carry__2_n_0,y_addr_out2_carry__2_n_1,y_addr_out2_carry__2_n_2,y_addr_out2_carry__2_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__1_n_90,y_addr_out3__1_n_91,y_addr_out3__1_n_92,y_addr_out3__1_n_93}),
.O(NLW_y_addr_out2_carry__2_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry__2_i_1_n_0,y_addr_out2_carry__2_i_2_n_0,y_addr_out2_carry__2_i_3_n_0,y_addr_out2_carry__2_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__2_i_1
(.I0(y_addr_out3__1_n_90),
.I1(y_addr_out3_n_90),
.O(y_addr_out2_carry__2_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__2_i_2
(.I0(y_addr_out3__1_n_91),
.I1(y_addr_out3_n_91),
.O(y_addr_out2_carry__2_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__2_i_3
(.I0(y_addr_out3__1_n_92),
.I1(y_addr_out3_n_92),
.O(y_addr_out2_carry__2_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__2_i_4
(.I0(y_addr_out3__1_n_93),
.I1(y_addr_out3_n_93),
.O(y_addr_out2_carry__2_i_4_n_0));
CARRY4 y_addr_out2_carry__3
(.CI(y_addr_out2_carry__2_n_0),
.CO({y_addr_out2_carry__3_n_0,y_addr_out2_carry__3_n_1,y_addr_out2_carry__3_n_2,y_addr_out2_carry__3_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__2_n_103,y_addr_out3__2_n_104,y_addr_out3__2_n_105,y_addr_out3__1_n_89}),
.O(NLW_y_addr_out2_carry__3_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry__3_i_1_n_0,y_addr_out2_carry__3_i_2_n_0,y_addr_out2_carry__3_i_3_n_0,y_addr_out2_carry__3_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__3_i_1
(.I0(y_addr_out3__2_n_103),
.I1(y_addr_out3__0_n_103),
.O(y_addr_out2_carry__3_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__3_i_2
(.I0(y_addr_out3__2_n_104),
.I1(y_addr_out3__0_n_104),
.O(y_addr_out2_carry__3_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__3_i_3
(.I0(y_addr_out3__2_n_105),
.I1(y_addr_out3__0_n_105),
.O(y_addr_out2_carry__3_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__3_i_4
(.I0(y_addr_out3__1_n_89),
.I1(y_addr_out3_n_89),
.O(y_addr_out2_carry__3_i_4_n_0));
CARRY4 y_addr_out2_carry__4
(.CI(y_addr_out2_carry__3_n_0),
.CO({y_addr_out2_carry__4_n_0,y_addr_out2_carry__4_n_1,y_addr_out2_carry__4_n_2,y_addr_out2_carry__4_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__2_n_99,y_addr_out3__2_n_100,y_addr_out3__2_n_101,y_addr_out3__2_n_102}),
.O(NLW_y_addr_out2_carry__4_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry__4_i_1_n_0,y_addr_out2_carry__4_i_2_n_0,y_addr_out2_carry__4_i_3_n_0,y_addr_out2_carry__4_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__4_i_1
(.I0(y_addr_out3__2_n_99),
.I1(y_addr_out3__0_n_99),
.O(y_addr_out2_carry__4_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__4_i_2
(.I0(y_addr_out3__2_n_100),
.I1(y_addr_out3__0_n_100),
.O(y_addr_out2_carry__4_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__4_i_3
(.I0(y_addr_out3__2_n_101),
.I1(y_addr_out3__0_n_101),
.O(y_addr_out2_carry__4_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__4_i_4
(.I0(y_addr_out3__2_n_102),
.I1(y_addr_out3__0_n_102),
.O(y_addr_out2_carry__4_i_4_n_0));
CARRY4 y_addr_out2_carry__5
(.CI(y_addr_out2_carry__4_n_0),
.CO({y_addr_out2_carry__5_n_0,y_addr_out2_carry__5_n_1,y_addr_out2_carry__5_n_2,y_addr_out2_carry__5_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__2_n_95,y_addr_out3__2_n_96,y_addr_out3__2_n_97,y_addr_out3__2_n_98}),
.O(NLW_y_addr_out2_carry__5_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry__5_i_1_n_0,y_addr_out2_carry__5_i_2_n_0,y_addr_out2_carry__5_i_3_n_0,y_addr_out2_carry__5_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__5_i_1
(.I0(y_addr_out3__2_n_95),
.I1(y_addr_out3__0_n_95),
.O(y_addr_out2_carry__5_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__5_i_2
(.I0(y_addr_out3__2_n_96),
.I1(y_addr_out3__0_n_96),
.O(y_addr_out2_carry__5_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__5_i_3
(.I0(y_addr_out3__2_n_97),
.I1(y_addr_out3__0_n_97),
.O(y_addr_out2_carry__5_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__5_i_4
(.I0(y_addr_out3__2_n_98),
.I1(y_addr_out3__0_n_98),
.O(y_addr_out2_carry__5_i_4_n_0));
CARRY4 y_addr_out2_carry__6
(.CI(y_addr_out2_carry__5_n_0),
.CO({y_addr_out2_carry__6_n_0,y_addr_out2_carry__6_n_1,y_addr_out2_carry__6_n_2,y_addr_out2_carry__6_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__2_n_91,y_addr_out3__2_n_92,y_addr_out3__2_n_93,y_addr_out3__2_n_94}),
.O(y_addr_out2[31:28]),
.S({y_addr_out2_carry__6_i_1_n_0,y_addr_out2_carry__6_i_2_n_0,y_addr_out2_carry__6_i_3_n_0,y_addr_out2_carry__6_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__6_i_1
(.I0(y_addr_out3__2_n_91),
.I1(y_addr_out3__0_n_91),
.O(y_addr_out2_carry__6_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__6_i_2
(.I0(y_addr_out3__2_n_92),
.I1(y_addr_out3__0_n_92),
.O(y_addr_out2_carry__6_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__6_i_3
(.I0(y_addr_out3__2_n_93),
.I1(y_addr_out3__0_n_93),
.O(y_addr_out2_carry__6_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__6_i_4
(.I0(y_addr_out3__2_n_94),
.I1(y_addr_out3__0_n_94),
.O(y_addr_out2_carry__6_i_4_n_0));
CARRY4 y_addr_out2_carry__7
(.CI(y_addr_out2_carry__6_n_0),
.CO({y_addr_out2_carry__7_n_0,y_addr_out2_carry__7_n_1,y_addr_out2_carry__7_n_2,y_addr_out2_carry__7_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__2_n_87,y_addr_out3__2_n_88,y_addr_out3__2_n_89,y_addr_out3__2_n_90}),
.O(y_addr_out2[35:32]),
.S({y_addr_out2_carry__7_i_1_n_0,y_addr_out2_carry__7_i_2_n_0,y_addr_out2_carry__7_i_3_n_0,y_addr_out2_carry__7_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__7_i_1
(.I0(y_addr_out3__2_n_87),
.I1(y_addr_out3__0_n_87),
.O(y_addr_out2_carry__7_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__7_i_2
(.I0(y_addr_out3__2_n_88),
.I1(y_addr_out3__0_n_88),
.O(y_addr_out2_carry__7_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__7_i_3
(.I0(y_addr_out3__2_n_89),
.I1(y_addr_out3__0_n_89),
.O(y_addr_out2_carry__7_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__7_i_4
(.I0(y_addr_out3__2_n_90),
.I1(y_addr_out3__0_n_90),
.O(y_addr_out2_carry__7_i_4_n_0));
CARRY4 y_addr_out2_carry__8
(.CI(y_addr_out2_carry__7_n_0),
.CO({NLW_y_addr_out2_carry__8_CO_UNCONNECTED[3:1],y_addr_out2_carry__8_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,y_addr_out3__2_n_86}),
.O({NLW_y_addr_out2_carry__8_O_UNCONNECTED[3:2],y_addr_out2[37:36]}),
.S({1'b0,1'b0,y_addr_out2_carry__8_i_1_n_0,y_addr_out2_carry__8_i_2_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__8_i_1
(.I0(y_addr_out3__2_n_85),
.I1(y_addr_out3__0_n_85),
.O(y_addr_out2_carry__8_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__8_i_2
(.I0(y_addr_out3__2_n_86),
.I1(y_addr_out3__0_n_86),
.O(y_addr_out2_carry__8_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry_i_1
(.I0(y_addr_out3__1_n_102),
.I1(y_addr_out3_n_102),
.O(y_addr_out2_carry_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry_i_2
(.I0(y_addr_out3__1_n_103),
.I1(y_addr_out3_n_103),
.O(y_addr_out2_carry_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry_i_3
(.I0(y_addr_out3__1_n_104),
.I1(y_addr_out3_n_104),
.O(y_addr_out2_carry_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry_i_4
(.I0(y_addr_out3__1_n_105),
.I1(y_addr_out3_n_105),
.O(y_addr_out2_carry_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
y_addr_out3
(.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,y_addr_in[2:0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_y_addr_out3_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({rot_m11[15],rot_m11[15],rot_m11}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_y_addr_out3_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_y_addr_out3_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_y_addr_out3_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_y_addr_out3_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_y_addr_out3_OVERFLOW_UNCONNECTED),
.P({y_addr_out3_n_58,y_addr_out3_n_59,y_addr_out3_n_60,y_addr_out3_n_61,y_addr_out3_n_62,y_addr_out3_n_63,y_addr_out3_n_64,y_addr_out3_n_65,y_addr_out3_n_66,y_addr_out3_n_67,y_addr_out3_n_68,y_addr_out3_n_69,y_addr_out3_n_70,y_addr_out3_n_71,y_addr_out3_n_72,y_addr_out3_n_73,y_addr_out3_n_74,y_addr_out3_n_75,y_addr_out3_n_76,y_addr_out3_n_77,y_addr_out3_n_78,y_addr_out3_n_79,y_addr_out3_n_80,y_addr_out3_n_81,y_addr_out3_n_82,y_addr_out3_n_83,y_addr_out3_n_84,y_addr_out3_n_85,y_addr_out3_n_86,y_addr_out3_n_87,y_addr_out3_n_88,y_addr_out3_n_89,y_addr_out3_n_90,y_addr_out3_n_91,y_addr_out3_n_92,y_addr_out3_n_93,y_addr_out3_n_94,y_addr_out3_n_95,y_addr_out3_n_96,y_addr_out3_n_97,y_addr_out3_n_98,y_addr_out3_n_99,y_addr_out3_n_100,y_addr_out3_n_101,y_addr_out3_n_102,y_addr_out3_n_103,y_addr_out3_n_104,y_addr_out3_n_105}),
.PATTERNBDETECT(NLW_y_addr_out3_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_y_addr_out3_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT({y_addr_out3_n_106,y_addr_out3_n_107,y_addr_out3_n_108,y_addr_out3_n_109,y_addr_out3_n_110,y_addr_out3_n_111,y_addr_out3_n_112,y_addr_out3_n_113,y_addr_out3_n_114,y_addr_out3_n_115,y_addr_out3_n_116,y_addr_out3_n_117,y_addr_out3_n_118,y_addr_out3_n_119,y_addr_out3_n_120,y_addr_out3_n_121,y_addr_out3_n_122,y_addr_out3_n_123,y_addr_out3_n_124,y_addr_out3_n_125,y_addr_out3_n_126,y_addr_out3_n_127,y_addr_out3_n_128,y_addr_out3_n_129,y_addr_out3_n_130,y_addr_out3_n_131,y_addr_out3_n_132,y_addr_out3_n_133,y_addr_out3_n_134,y_addr_out3_n_135,y_addr_out3_n_136,y_addr_out3_n_137,y_addr_out3_n_138,y_addr_out3_n_139,y_addr_out3_n_140,y_addr_out3_n_141,y_addr_out3_n_142,y_addr_out3_n_143,y_addr_out3_n_144,y_addr_out3_n_145,y_addr_out3_n_146,y_addr_out3_n_147,y_addr_out3_n_148,y_addr_out3_n_149,y_addr_out3_n_150,y_addr_out3_n_151,y_addr_out3_n_152,y_addr_out3_n_153}),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_y_addr_out3_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
y_addr_out3__0
(.A({rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_y_addr_out3__0_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,y_addr_in[9:3]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_y_addr_out3__0_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_y_addr_out3__0_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_y_addr_out3__0_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_y_addr_out3__0_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b1,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_y_addr_out3__0_OVERFLOW_UNCONNECTED),
.P({y_addr_out3__0_n_58,y_addr_out3__0_n_59,y_addr_out3__0_n_60,y_addr_out3__0_n_61,y_addr_out3__0_n_62,y_addr_out3__0_n_63,y_addr_out3__0_n_64,y_addr_out3__0_n_65,y_addr_out3__0_n_66,y_addr_out3__0_n_67,y_addr_out3__0_n_68,y_addr_out3__0_n_69,y_addr_out3__0_n_70,y_addr_out3__0_n_71,y_addr_out3__0_n_72,y_addr_out3__0_n_73,y_addr_out3__0_n_74,y_addr_out3__0_n_75,y_addr_out3__0_n_76,y_addr_out3__0_n_77,y_addr_out3__0_n_78,y_addr_out3__0_n_79,y_addr_out3__0_n_80,y_addr_out3__0_n_81,y_addr_out3__0_n_82,y_addr_out3__0_n_83,y_addr_out3__0_n_84,y_addr_out3__0_n_85,y_addr_out3__0_n_86,y_addr_out3__0_n_87,y_addr_out3__0_n_88,y_addr_out3__0_n_89,y_addr_out3__0_n_90,y_addr_out3__0_n_91,y_addr_out3__0_n_92,y_addr_out3__0_n_93,y_addr_out3__0_n_94,y_addr_out3__0_n_95,y_addr_out3__0_n_96,y_addr_out3__0_n_97,y_addr_out3__0_n_98,y_addr_out3__0_n_99,y_addr_out3__0_n_100,y_addr_out3__0_n_101,y_addr_out3__0_n_102,y_addr_out3__0_n_103,y_addr_out3__0_n_104,y_addr_out3__0_n_105}),
.PATTERNBDETECT(NLW_y_addr_out3__0_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_y_addr_out3__0_PATTERNDETECT_UNCONNECTED),
.PCIN({y_addr_out3_n_106,y_addr_out3_n_107,y_addr_out3_n_108,y_addr_out3_n_109,y_addr_out3_n_110,y_addr_out3_n_111,y_addr_out3_n_112,y_addr_out3_n_113,y_addr_out3_n_114,y_addr_out3_n_115,y_addr_out3_n_116,y_addr_out3_n_117,y_addr_out3_n_118,y_addr_out3_n_119,y_addr_out3_n_120,y_addr_out3_n_121,y_addr_out3_n_122,y_addr_out3_n_123,y_addr_out3_n_124,y_addr_out3_n_125,y_addr_out3_n_126,y_addr_out3_n_127,y_addr_out3_n_128,y_addr_out3_n_129,y_addr_out3_n_130,y_addr_out3_n_131,y_addr_out3_n_132,y_addr_out3_n_133,y_addr_out3_n_134,y_addr_out3_n_135,y_addr_out3_n_136,y_addr_out3_n_137,y_addr_out3_n_138,y_addr_out3_n_139,y_addr_out3_n_140,y_addr_out3_n_141,y_addr_out3_n_142,y_addr_out3_n_143,y_addr_out3_n_144,y_addr_out3_n_145,y_addr_out3_n_146,y_addr_out3_n_147,y_addr_out3_n_148,y_addr_out3_n_149,y_addr_out3_n_150,y_addr_out3_n_151,y_addr_out3_n_152,y_addr_out3_n_153}),
.PCOUT(NLW_y_addr_out3__0_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_y_addr_out3__0_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
y_addr_out3__1
(.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,x_addr_in[2:0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_y_addr_out3__1_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({rot_m10[15],rot_m10[15],rot_m10}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_y_addr_out3__1_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_y_addr_out3__1_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_y_addr_out3__1_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_y_addr_out3__1_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_y_addr_out3__1_OVERFLOW_UNCONNECTED),
.P({y_addr_out3__1_n_58,y_addr_out3__1_n_59,y_addr_out3__1_n_60,y_addr_out3__1_n_61,y_addr_out3__1_n_62,y_addr_out3__1_n_63,y_addr_out3__1_n_64,y_addr_out3__1_n_65,y_addr_out3__1_n_66,y_addr_out3__1_n_67,y_addr_out3__1_n_68,y_addr_out3__1_n_69,y_addr_out3__1_n_70,y_addr_out3__1_n_71,y_addr_out3__1_n_72,y_addr_out3__1_n_73,y_addr_out3__1_n_74,y_addr_out3__1_n_75,y_addr_out3__1_n_76,y_addr_out3__1_n_77,y_addr_out3__1_n_78,y_addr_out3__1_n_79,y_addr_out3__1_n_80,y_addr_out3__1_n_81,y_addr_out3__1_n_82,y_addr_out3__1_n_83,y_addr_out3__1_n_84,y_addr_out3__1_n_85,y_addr_out3__1_n_86,y_addr_out3__1_n_87,y_addr_out3__1_n_88,y_addr_out3__1_n_89,y_addr_out3__1_n_90,y_addr_out3__1_n_91,y_addr_out3__1_n_92,y_addr_out3__1_n_93,y_addr_out3__1_n_94,y_addr_out3__1_n_95,y_addr_out3__1_n_96,y_addr_out3__1_n_97,y_addr_out3__1_n_98,y_addr_out3__1_n_99,y_addr_out3__1_n_100,y_addr_out3__1_n_101,y_addr_out3__1_n_102,y_addr_out3__1_n_103,y_addr_out3__1_n_104,y_addr_out3__1_n_105}),
.PATTERNBDETECT(NLW_y_addr_out3__1_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_y_addr_out3__1_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT({y_addr_out3__1_n_106,y_addr_out3__1_n_107,y_addr_out3__1_n_108,y_addr_out3__1_n_109,y_addr_out3__1_n_110,y_addr_out3__1_n_111,y_addr_out3__1_n_112,y_addr_out3__1_n_113,y_addr_out3__1_n_114,y_addr_out3__1_n_115,y_addr_out3__1_n_116,y_addr_out3__1_n_117,y_addr_out3__1_n_118,y_addr_out3__1_n_119,y_addr_out3__1_n_120,y_addr_out3__1_n_121,y_addr_out3__1_n_122,y_addr_out3__1_n_123,y_addr_out3__1_n_124,y_addr_out3__1_n_125,y_addr_out3__1_n_126,y_addr_out3__1_n_127,y_addr_out3__1_n_128,y_addr_out3__1_n_129,y_addr_out3__1_n_130,y_addr_out3__1_n_131,y_addr_out3__1_n_132,y_addr_out3__1_n_133,y_addr_out3__1_n_134,y_addr_out3__1_n_135,y_addr_out3__1_n_136,y_addr_out3__1_n_137,y_addr_out3__1_n_138,y_addr_out3__1_n_139,y_addr_out3__1_n_140,y_addr_out3__1_n_141,y_addr_out3__1_n_142,y_addr_out3__1_n_143,y_addr_out3__1_n_144,y_addr_out3__1_n_145,y_addr_out3__1_n_146,y_addr_out3__1_n_147,y_addr_out3__1_n_148,y_addr_out3__1_n_149,y_addr_out3__1_n_150,y_addr_out3__1_n_151,y_addr_out3__1_n_152,y_addr_out3__1_n_153}),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_y_addr_out3__1_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
y_addr_out3__2
(.A({rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_y_addr_out3__2_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,x_addr_in[9:3]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_y_addr_out3__2_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_y_addr_out3__2_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_y_addr_out3__2_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_y_addr_out3__2_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b1,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_y_addr_out3__2_OVERFLOW_UNCONNECTED),
.P({y_addr_out3__2_n_58,y_addr_out3__2_n_59,y_addr_out3__2_n_60,y_addr_out3__2_n_61,y_addr_out3__2_n_62,y_addr_out3__2_n_63,y_addr_out3__2_n_64,y_addr_out3__2_n_65,y_addr_out3__2_n_66,y_addr_out3__2_n_67,y_addr_out3__2_n_68,y_addr_out3__2_n_69,y_addr_out3__2_n_70,y_addr_out3__2_n_71,y_addr_out3__2_n_72,y_addr_out3__2_n_73,y_addr_out3__2_n_74,y_addr_out3__2_n_75,y_addr_out3__2_n_76,y_addr_out3__2_n_77,y_addr_out3__2_n_78,y_addr_out3__2_n_79,y_addr_out3__2_n_80,y_addr_out3__2_n_81,y_addr_out3__2_n_82,y_addr_out3__2_n_83,y_addr_out3__2_n_84,y_addr_out3__2_n_85,y_addr_out3__2_n_86,y_addr_out3__2_n_87,y_addr_out3__2_n_88,y_addr_out3__2_n_89,y_addr_out3__2_n_90,y_addr_out3__2_n_91,y_addr_out3__2_n_92,y_addr_out3__2_n_93,y_addr_out3__2_n_94,y_addr_out3__2_n_95,y_addr_out3__2_n_96,y_addr_out3__2_n_97,y_addr_out3__2_n_98,y_addr_out3__2_n_99,y_addr_out3__2_n_100,y_addr_out3__2_n_101,y_addr_out3__2_n_102,y_addr_out3__2_n_103,y_addr_out3__2_n_104,y_addr_out3__2_n_105}),
.PATTERNBDETECT(NLW_y_addr_out3__2_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_y_addr_out3__2_PATTERNDETECT_UNCONNECTED),
.PCIN({y_addr_out3__1_n_106,y_addr_out3__1_n_107,y_addr_out3__1_n_108,y_addr_out3__1_n_109,y_addr_out3__1_n_110,y_addr_out3__1_n_111,y_addr_out3__1_n_112,y_addr_out3__1_n_113,y_addr_out3__1_n_114,y_addr_out3__1_n_115,y_addr_out3__1_n_116,y_addr_out3__1_n_117,y_addr_out3__1_n_118,y_addr_out3__1_n_119,y_addr_out3__1_n_120,y_addr_out3__1_n_121,y_addr_out3__1_n_122,y_addr_out3__1_n_123,y_addr_out3__1_n_124,y_addr_out3__1_n_125,y_addr_out3__1_n_126,y_addr_out3__1_n_127,y_addr_out3__1_n_128,y_addr_out3__1_n_129,y_addr_out3__1_n_130,y_addr_out3__1_n_131,y_addr_out3__1_n_132,y_addr_out3__1_n_133,y_addr_out3__1_n_134,y_addr_out3__1_n_135,y_addr_out3__1_n_136,y_addr_out3__1_n_137,y_addr_out3__1_n_138,y_addr_out3__1_n_139,y_addr_out3__1_n_140,y_addr_out3__1_n_141,y_addr_out3__1_n_142,y_addr_out3__1_n_143,y_addr_out3__1_n_144,y_addr_out3__1_n_145,y_addr_out3__1_n_146,y_addr_out3__1_n_147,y_addr_out3__1_n_148,y_addr_out3__1_n_149,y_addr_out3__1_n_150,y_addr_out3__1_n_151,y_addr_out3__1_n_152,y_addr_out3__1_n_153}),
.PCOUT(NLW_y_addr_out3__2_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_y_addr_out3__2_UNDERFLOW_UNCONNECTED));
LUT2 #(
.INIT(4'h6))
\y_addr_out[0]_i_1
(.I0(y_addr_out2[28]),
.I1(t_y[0]),
.O(p_0_in[0]));
FDRE \y_addr_out_reg[0]
(.C(clk),
.CE(enable),
.D(p_0_in[0]),
.Q(y_addr_out[0]),
.R(1'b0));
FDRE \y_addr_out_reg[1]
(.C(clk),
.CE(enable),
.D(p_0_in[1]),
.Q(y_addr_out[1]),
.R(1'b0));
FDRE \y_addr_out_reg[2]
(.C(clk),
.CE(enable),
.D(p_0_in[2]),
.Q(y_addr_out[2]),
.R(1'b0));
FDRE \y_addr_out_reg[3]
(.C(clk),
.CE(enable),
.D(p_0_in[3]),
.Q(y_addr_out[3]),
.R(1'b0));
FDRE \y_addr_out_reg[4]
(.C(clk),
.CE(enable),
.D(p_0_in[4]),
.Q(y_addr_out[4]),
.R(1'b0));
FDRE \y_addr_out_reg[5]
(.C(clk),
.CE(enable),
.D(p_0_in[5]),
.Q(y_addr_out[5]),
.R(1'b0));
FDRE \y_addr_out_reg[6]
(.C(clk),
.CE(enable),
.D(p_0_in[6]),
.Q(y_addr_out[6]),
.R(1'b0));
FDRE \y_addr_out_reg[7]
(.C(clk),
.CE(enable),
.D(p_0_in[7]),
.Q(y_addr_out[7]),
.R(1'b0));
FDRE \y_addr_out_reg[8]
(.C(clk),
.CE(enable),
.D(p_0_in[8]),
.Q(y_addr_out[8]),
.R(1'b0));
FDRE \y_addr_out_reg[9]
(.C(clk),
.CE(enable),
.D(p_0_in[9]),
.Q(y_addr_out[9]),
.R(1'b0));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module sky130_fd_sc_ls__maj3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ls__maj3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule |
module sky130_fd_sc_lp__or3b (
X ,
A ,
B ,
C_N
);
// Module ports
output X ;
input A ;
input B ;
input C_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X, B, A, not0_out );
buf buf0 (X , or0_out_X );
endmodule |
module cm_rom_final (
aclr,
address_a,
address_b,
clock,
q_a,
q_b);
input aclr;
input [8:0] address_a;
input [8:0] address_b;
input clock;
output [3:0] q_a;
output [3:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [3:0] sub_wire0;
wire [3:0] sub_wire1;
wire sub_wire2 = 1'h0;
wire [3:0] sub_wire3 = 4'h0;
wire [3:0] q_b = sub_wire0[3:0];
wire [3:0] q_a = sub_wire1[3:0];
altsyncram altsyncram_component (
.clock0 (clock),
.wren_a (sub_wire2),
.address_b (address_b),
.data_b (sub_wire3),
.wren_b (sub_wire2),
.aclr0 (aclr),
.address_a (address_a),
.data_a (sub_wire3),
.q_b (sub_wire0),
.q_a (sub_wire1)
// synopsys translate_off
,
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.clocken2 (),
.clocken3 (),
.eccstatus (),
.rden_a (),
.rden_b ()
// synopsys translate_on
);
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "output_CM_final.mif",
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.numwords_b = 512,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "CLEAR0",
altsyncram_component.outdata_aclr_b = "CLEAR0",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 9,
altsyncram_component.widthad_b = 9,
altsyncram_component.width_a = 4,
altsyncram_component.width_b = 4,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule |
module sky130_fd_sc_ls__or2b (
//# {{data|Data Signals}}
input A ,
input B_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module addrdecode(
clk,
addr_in,
bank0_addr,
bank1_addr,
bank2_addr,
bank3_addr,
sel,
odd
);
input clk;
input [12:0]addr_in;
output [9:0]bank0_addr;
output [9:0]bank1_addr;
output [9:0]bank2_addr;
output [9:0]bank3_addr;
output [1:0]sel;
output odd;
reg [9:0] bank0_addr;
reg [9:0] bank1_addr;
reg [9:0] bank2_addr;
reg [9:0] bank3_addr;
reg [1:0] sel_dlya;
reg [1:0] sel_dlyb;
reg [1:0] sel;
reg odd_dlya;
reg odd_dlyb;
reg odd;
wire [9:0] addr = addr_in[12:3];
wire [9:0] addr_pone = addr_in[12:3] + 1;
// We delay odd and sel by 2 cycle to account for:
// (1) cycle of address decode time.
// (1) cycle of memory access time.
always@(posedge clk) begin
odd_dlya <= addr_in[0];
sel_dlya <= addr_in[2:1];
end
always@(posedge clk) begin
odd_dlyb <= odd_dlya;
sel_dlyb <= sel_dlya;
end
always@(posedge clk) begin
odd <= odd_dlyb;
sel <= sel_dlyb;
end
// Decode the address.
always@(posedge clk) begin
case(addr_in[2:1])
2'b00: begin
bank0_addr <= addr;
bank1_addr <= addr;
bank2_addr <= addr;
bank3_addr <= addr;
end
2'b01: begin
bank0_addr <= addr_pone;
bank1_addr <= addr;
bank2_addr <= addr;
bank3_addr <= addr;
end
2'b10: begin
bank0_addr <= addr_pone;
bank1_addr <= addr_pone;
bank2_addr <= addr;
bank3_addr <= addr;
end
2'b11: begin
bank0_addr <= addr_pone;
bank1_addr <= addr_pone;
bank2_addr <= addr_pone;
bank3_addr <= addr;
end
endcase
end
endmodule |
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