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module seqPortAlloc(
mc,
numFlit_in,
availPortVector_in,
ppv,
allocatedPortVector,
availPortVector_out,
numFlit_out
);
input mc;
input [`PC_INDEX_WIDTH-1:0] numFlit_in;
input [`NUM_PORT-2:0] availPortVector_in, ppv;
output [`NUM_PORT-2:0] allocatedPortVector, availPortVector_out;
output [`PC_INDEX_WIDTH-1:0] numFlit_out;
wire [`PC_INDEX_WIDTH-1:0] numFlit [`NUM_PORT-1:0];
wire [`NUM_PORT-2:0] allocatedPortVector_st1, availPortVector_out_st1;
wire [`NUM_PORT-2:0] allocatedPortVector_st2, availPortVector_out_st2;
assign numFlit[0] = numFlit_in;
genvar i;
generate
// Stage 1: allocate the productive port
for (i=0; i<`NUM_PORT-1; i=i+1) begin : productiveAlloc
assign allocatedPortVector_st1[i] = ppv[i] && availPortVector_in[i] && (~mc || (mc && (numFlit[i] <= `NUM_PORT-1)));
assign numFlit[i+1] = numFlit[i] + allocatedPortVector_st1[i];
assign availPortVector_out_st1[i] = availPortVector_in[i] && ~allocatedPortVector_st1[i];
end
endgenerate
// Stage 2: deflection: find the first available port in the order of N, E, S, W
assign allocatedPortVector_st2[0] = availPortVector_out_st1[0];
assign allocatedPortVector_st2[1] = availPortVector_out_st1[1] && ~availPortVector_out_st1[0];
assign allocatedPortVector_st2[2] = availPortVector_out_st1[2] && ~availPortVector_out_st1[1] && ~availPortVector_out_st1[0];
assign allocatedPortVector_st2[3] = availPortVector_out_st1[3] && ~availPortVector_out_st1[2] && ~availPortVector_out_st1[1] && ~availPortVector_out_st1[0];
assign availPortVector_out_st2 [0] = 1'b0;
assign availPortVector_out_st2 [1] = availPortVector_out_st1[0] && availPortVector_out_st1[1];
assign availPortVector_out_st2 [2] = |availPortVector_out_st1[1:0] && availPortVector_out_st1[2];
assign availPortVector_out_st2 [3] = |availPortVector_out_st1[2:0] && availPortVector_out_st1[3];
wire get_port_st1;
assign get_port_st1 = |allocatedPortVector_st1;
assign allocatedPortVector = (~|ppv || get_port_st1) ? allocatedPortVector_st1 : allocatedPortVector_st2;
assign availPortVector_out = (~|ppv || get_port_st1) ? availPortVector_out_st1 : availPortVector_out_st2;
assign numFlit_out = (~|ppv || get_port_st1) ? numFlit[`NUM_PORT-1] : numFlit[`NUM_PORT-1] + 1'b1;
endmodule |
module eth_phy_10g_rx_frame_sync #
(
parameter HDR_WIDTH = 2,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8
)
(
input wire clk,
input wire rst,
/*
* SERDES interface
*/
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* Status
*/
output wire rx_block_lock
);
parameter BITSLIP_MAX_CYCLES = BITSLIP_HIGH_CYCLES > BITSLIP_LOW_CYCLES ? BITSLIP_HIGH_CYCLES : BITSLIP_LOW_CYCLES;
parameter BITSLIP_COUNT_WIDTH = $clog2(BITSLIP_MAX_CYCLES);
// bus width assertions
initial begin
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
reg [5:0] sh_count_reg = 6'd0, sh_count_next;
reg [3:0] sh_invalid_count_reg = 4'd0, sh_invalid_count_next;
reg [BITSLIP_COUNT_WIDTH-1:0] bitslip_count_reg = 0, bitslip_count_next;
reg serdes_rx_bitslip_reg = 1'b0, serdes_rx_bitslip_next;
reg rx_block_lock_reg = 1'b0, rx_block_lock_next;
assign serdes_rx_bitslip = serdes_rx_bitslip_reg;
assign rx_block_lock = rx_block_lock_reg;
always @* begin
sh_count_next = sh_count_reg;
sh_invalid_count_next = sh_invalid_count_reg;
bitslip_count_next = bitslip_count_reg;
serdes_rx_bitslip_next = serdes_rx_bitslip_reg;
rx_block_lock_next = rx_block_lock_reg;
if (bitslip_count_reg) begin
bitslip_count_next = bitslip_count_reg-1;
end else if (serdes_rx_bitslip_reg) begin
serdes_rx_bitslip_next = 1'b0;
bitslip_count_next = BITSLIP_LOW_CYCLES > 0 ? BITSLIP_LOW_CYCLES-1 : 0;
end else if (serdes_rx_hdr == SYNC_CTRL || serdes_rx_hdr == SYNC_DATA) begin
// valid header
sh_count_next = sh_count_reg + 1;
if (&sh_count_reg) begin
// valid count overflow, reset
sh_count_next = 0;
sh_invalid_count_next = 0;
if (!sh_invalid_count_reg) begin
rx_block_lock_next = 1'b1;
end
end
end else begin
// invalid header
sh_count_next = sh_count_reg + 1;
sh_invalid_count_next = sh_invalid_count_reg + 1;
if (!rx_block_lock_reg || &sh_invalid_count_reg) begin
// invalid count overflow, lost block lock
sh_count_next = 0;
sh_invalid_count_next = 0;
rx_block_lock_next = 1'b0;
// slip one bit
serdes_rx_bitslip_next = 1'b1;
bitslip_count_next = BITSLIP_HIGH_CYCLES > 0 ? BITSLIP_HIGH_CYCLES-1 : 0;
end else if (&sh_count_reg) begin
// valid count overflow, reset
sh_count_next = 0;
sh_invalid_count_next = 0;
end
end
end
always @(posedge clk) begin
sh_count_reg <= sh_count_next;
sh_invalid_count_reg <= sh_invalid_count_next;
bitslip_count_reg <= bitslip_count_next;
serdes_rx_bitslip_reg <= serdes_rx_bitslip_next;
rx_block_lock_reg <= rx_block_lock_next;
if (rst) begin
sh_count_reg <= 6'd0;
sh_invalid_count_reg <= 4'd0;
bitslip_count_reg <= 0;
serdes_rx_bitslip_reg <= 1'b0;
rx_block_lock_reg <= 1'b0;
end
end
endmodule |
module cx4_datram (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock;
input [7:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 3072,
altsyncram_component.numwords_b = 3072,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 12,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule |
module Binary_To_BCD(
CLK,
RST,
START,
BIN,
BCDOUT
);
// ====================================================================================
// Port Declarations
// ====================================================================================
input CLK; // 100Mhz CLK
input RST; // Reset
input START; // Signal to initialize conversion
input [8:0] BIN; // Binary value to be converted
output [15:0] BCDOUT; // 4 digit binary coded decimal output
// ====================================================================================
// Parameters, Registers, and Wires
// ====================================================================================
reg [15:0] BCDOUT;
// Stores number of shifts executed
reg [4:0] shiftCount;
// Temporary shift regsiter
reg [27:0] tmpSR;
// FSM States
parameter [2:0] state_type_Idle = 0,
state_type_Init = 1,
state_type_Shift = 2,
state_type_Check = 3,
state_type_Done = 4;
// Present state, Next State
reg [2:0] STATE;
reg [2:0] NSTATE;
// ===================================================================================
// Implementation
// ===================================================================================
//------------------------------
// State Register
//------------------------------
always @(posedge CLK or posedge RST)
begin: STATE_REGISTER
if (RST == 1'b1)
STATE <= state_type_Idle;
else
STATE <= NSTATE;
end
//------------------------------
// Output Logic/Assignment
//------------------------------
always @(posedge CLK or posedge RST)
begin: OUTPUT_LOGIC
if (RST == 1'b1) begin
// Reset/clear values
BCDOUT[11:0] <= 12'h000;
tmpSR <= 28'h0000000;
end
else
case (STATE)
// Idle State
state_type_Idle : begin
BCDOUT <= BCDOUT; // Output does not change
tmpSR <= 28'h0000000; // Temp shift reg empty
end
// Init State
state_type_Init : begin
BCDOUT <= BCDOUT; // Output does not change
tmpSR <= {19'b0000000000000000000, BIN}; // Copy input to lower 9 bits
end
// Shift State
state_type_Shift : begin
BCDOUT <= BCDOUT; // Output does not change
tmpSR <= {tmpSR[26:0], 1'b0}; // Shift left 1 bit
shiftCount <= shiftCount + 1'b1; // Count the shift
end
// Check State
state_type_Check : begin
BCDOUT <= BCDOUT; // Output does not change
// Not done converting
if (shiftCount != 4'hC)
begin
// Add 3 to thousands place
if (tmpSR[27:24] >= 4'h5)
tmpSR[27:24] <= tmpSR[27:24] + 4'h3;
// Add 3 to hundreds place
if (tmpSR[23:20] >= 4'h5)
tmpSR[23:20] <= tmpSR[23:20] + 4'h3;
// Add 3 to tens place
if (tmpSR[19:16] >= 4'h5)
tmpSR[19:16] <= tmpSR[19:16] + 4'h3;
// Add 3 to ones place
if (tmpSR[15:12] >= 4'h5)
tmpSR[15:12] <= tmpSR[15:12] + 4'h3;
end
end
// Done State
state_type_Done :
begin
BCDOUT[11:0] <= tmpSR[23:12]; // Assign output the new BCD values
tmpSR <= 28'h0000000; // Clear temp shift register
shiftCount <= 5'b00000; // Clear shift count
end
endcase
end
//------------------------------
// Next State Logic
//------------------------------
always @(START or shiftCount or STATE)
begin: NEXT_STATE_LOGIC
// Define default state to avoid latches
NSTATE <= state_type_Idle;
case (STATE)
// Idle State
state_type_Idle :
if (START == 1'b1)
NSTATE <= state_type_Init;
else
NSTATE <= state_type_Idle;
// Init State
state_type_Init :
NSTATE <= state_type_Shift;
// Shift State
state_type_Shift :
NSTATE <= state_type_Check;
// Check State
state_type_Check :
if (shiftCount != 4'hC)
NSTATE <= state_type_Shift;
else
NSTATE <= state_type_Done;
// Done State
state_type_Done :
NSTATE <= state_type_Idle;
// Default State
default : NSTATE <= state_type_Idle;
endcase
end
endmodule |
module top();
// Inputs are registered
reg UDP_IN;
reg VPWR;
reg VGND;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 UDP_IN = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 UDP_IN = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 UDP_IN = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 UDP_IN = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 UDP_IN = 1'bx;
end
sky130_fd_sc_hdll__udp_pwrgood_pp$PG dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .VGND(VGND), .UDP_OUT(UDP_OUT));
endmodule |
module bsg_cache_non_blocking_tl_stage
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(id_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(ways_p)
, parameter `BSG_INV_PARAM(sets_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter lg_ways_lp=`BSG_SAFE_CLOG2(ways_p)
, parameter lg_sets_lp=`BSG_SAFE_CLOG2(sets_p)
, parameter lg_block_size_in_words_lp=`BSG_SAFE_CLOG2(block_size_in_words_p)
, parameter data_mask_width_lp=(data_width_p>>3)
, parameter byte_sel_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3)
, parameter tag_width_lp=(addr_width_p-lg_sets_lp-lg_block_size_in_words_lp-byte_sel_width_lp)
, parameter data_mem_pkt_width_lp=
`bsg_cache_non_blocking_data_mem_pkt_width(ways_p,sets_p,block_size_in_words_p,data_width_p)
, parameter stat_mem_pkt_width_lp=
`bsg_cache_non_blocking_stat_mem_pkt_width(ways_p,sets_p)
, parameter tag_mem_pkt_width_lp=
`bsg_cache_non_blocking_tag_mem_pkt_width(ways_p,sets_p,data_width_p,tag_width_lp)
, parameter miss_fifo_entry_width_lp=
`bsg_cache_non_blocking_miss_fifo_entry_width(id_width_p,addr_width_p,data_width_p)
)
(
input clk_i
, input reset_i
// from input
, input v_i
, input [id_width_p-1:0] id_i
, input [addr_width_p-1:0] addr_i
, input [data_width_p-1:0] data_i
, input [data_mask_width_lp-1:0] mask_i
, input bsg_cache_non_blocking_decode_s decode_i
, output logic ready_o
// data_mem access (hit)
, output logic data_mem_pkt_v_o
, output logic [data_mem_pkt_width_lp-1:0] data_mem_pkt_o
, input data_mem_pkt_ready_i
, output logic block_loading_o
// stat_mem access (hit)
, output logic stat_mem_pkt_v_o
, output logic [stat_mem_pkt_width_lp-1:0] stat_mem_pkt_o
, input stat_mem_pkt_ready_i
// miss FIFO (miss)
, output logic miss_fifo_v_o
, output logic [miss_fifo_entry_width_lp-1:0] miss_fifo_entry_o
, input miss_fifo_ready_i
// to MHU (cache management)
, output logic mgmt_v_o
, output logic [ways_p-1:0] valid_tl_o
, output logic [ways_p-1:0] lock_tl_o
, output logic [ways_p-1:0][tag_width_lp-1:0] tag_tl_o
, output bsg_cache_non_blocking_decode_s decode_tl_o
, output logic [addr_width_p-1:0] addr_tl_o
, output logic [id_width_p-1:0] id_tl_o
, output logic [data_width_p-1:0] data_tl_o
, output logic [lg_ways_lp-1:0] tag_hit_way_o
, output logic tag_hit_found_o
, input mgmt_yumi_i
// from MHU
, input mhu_tag_mem_pkt_v_i
, input [tag_mem_pkt_width_lp-1:0] mhu_tag_mem_pkt_i
, input mhu_idle_i
, input recover_i
, input [lg_ways_lp-1:0] curr_mhu_way_id_i
, input [lg_sets_lp-1:0] curr_mhu_index_i
, input curr_mhu_v_i
, input [lg_ways_lp-1:0] curr_dma_way_id_i
, input [lg_sets_lp-1:0] curr_dma_index_i
, input curr_dma_v_i
);
// localparam
//
localparam block_offset_width_lp = byte_sel_width_lp+lg_block_size_in_words_lp;
// declare structs
//
`declare_bsg_cache_non_blocking_tag_mem_pkt_s(ways_p,sets_p,data_width_p,tag_width_lp);
`declare_bsg_cache_non_blocking_stat_mem_pkt_s(ways_p,sets_p);
`declare_bsg_cache_non_blocking_data_mem_pkt_s(ways_p,sets_p,block_size_in_words_p,data_width_p);
`declare_bsg_cache_non_blocking_miss_fifo_entry_s(id_width_p,addr_width_p,data_width_p);
bsg_cache_non_blocking_data_mem_pkt_s data_mem_pkt;
bsg_cache_non_blocking_stat_mem_pkt_s stat_mem_pkt;
bsg_cache_non_blocking_tag_mem_pkt_s mhu_tag_mem_pkt;
bsg_cache_non_blocking_miss_fifo_entry_s miss_fifo_entry;
assign data_mem_pkt_o = data_mem_pkt;
assign stat_mem_pkt_o = stat_mem_pkt;
assign mhu_tag_mem_pkt = mhu_tag_mem_pkt_i;
assign miss_fifo_entry_o = miss_fifo_entry;
// TL stage
//
logic v_tl_r, v_tl_n;
logic block_mode_r, block_mode_n;
logic tl_we;
bsg_cache_non_blocking_decode_s decode_tl_r;
logic [id_width_p-1:0] id_tl_r;
logic [addr_width_p-1:0] addr_tl_r;
logic [data_width_p-1:0] data_tl_r;
logic [data_mask_width_lp-1:0] mask_tl_r;
logic mgmt_op_v;
assign decode_tl_o = decode_tl_r;
assign id_tl_o = id_tl_r;
assign addr_tl_o = addr_tl_r;
assign data_tl_o = data_tl_r;
assign mgmt_op_v = decode_i.mgmt_op & v_i;
logic [lg_sets_lp-1:0] addr_index;
logic [lg_ways_lp-1:0] addr_way;
assign addr_index = addr_i[block_offset_width_lp+:lg_sets_lp];
assign addr_way = addr_i[block_offset_width_lp+lg_sets_lp+:lg_ways_lp];
logic [tag_width_lp-1:0] addr_tag_tl;
logic [lg_sets_lp-1:0] addr_index_tl;
assign addr_tag_tl = addr_tl_r[block_offset_width_lp+lg_sets_lp+:tag_width_lp];
assign addr_index_tl = addr_tl_r[block_offset_width_lp+:lg_sets_lp];
assign block_loading_o = block_mode_r;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
v_tl_r <= 1'b0;
block_mode_r <= 1'b0;
end
else begin
v_tl_r <= v_tl_n;
block_mode_r <= block_mode_n;
end
if (reset_i) begin
{decode_tl_r
,id_tl_r
,addr_tl_r
,data_tl_r
,mask_tl_r} <= '0;
end
else begin
if (tl_we) begin
decode_tl_r <= decode_i;
id_tl_r <= id_i;
addr_tl_r <= addr_i;
data_tl_r <= data_i;
mask_tl_r <= mask_i;
end
end
end
// block_load counter
//
logic counter_clear;
logic counter_up;
logic [lg_block_size_in_words_lp-1:0] counter_r;
logic counter_max;
bsg_counter_clear_up #(
.max_val_p(block_size_in_words_p-1)
,.init_val_p(0)
) block_counter (
.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(counter_clear)
,.up_i(counter_up)
,.count_o(counter_r)
);
assign counter_max = counter_r == (block_size_in_words_p-1);
// tag_mem
//
logic tag_mem_v_li;
bsg_cache_non_blocking_tag_mem_pkt_s tag_mem_pkt;
logic [ways_p-1:0] valid_tl;
logic [ways_p-1:0] lock_tl;
logic [ways_p-1:0][tag_width_lp-1:0] tag_tl;
bsg_cache_non_blocking_tag_mem #(
.sets_p(sets_p)
,.ways_p(ways_p)
,.data_width_p(data_width_p)
,.tag_width_p(tag_width_lp)
) tag_mem0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(tag_mem_v_li)
,.tag_mem_pkt_i(tag_mem_pkt)
,.valid_o(valid_tl)
,.lock_o(lock_tl)
,.tag_o(tag_tl)
);
assign valid_tl_o = valid_tl;
assign lock_tl_o = lock_tl;
assign tag_tl_o = tag_tl;
// tag hit detection
//
logic [ways_p-1:0] tag_hit;
for (genvar i = 0; i < ways_p; i++) begin
assign tag_hit[i] = (tag_tl[i] == addr_tag_tl) & valid_tl[i];
end
logic [lg_ways_lp-1:0] tag_hit_way;
bsg_priority_encode #(
.width_p(ways_p)
,.lo_to_hi_p(1)
) tag_hit_pe (
.i(tag_hit)
,.addr_o(tag_hit_way)
,.v_o() // too slow
);
assign tag_hit_way_o = tag_hit_way;
wire tag_hit_found = |tag_hit;
assign tag_hit_found_o = tag_hit_found;
// miss detection logic
wire mhu_miss_match = curr_mhu_v_i & (tag_hit_way == curr_mhu_way_id_i) & (curr_mhu_index_i == addr_index_tl);
wire dma_miss_match = curr_dma_v_i & (tag_hit_way == curr_dma_way_id_i) & (curr_dma_index_i == addr_index_tl);
// TL stage output logic
//
assign data_mem_pkt.write_not_read = decode_tl_r.st_op;
assign data_mem_pkt.way_id = tag_hit_way;
assign data_mem_pkt.addr = decode_tl_r.block_ld_op
? {addr_tl_r[block_offset_width_lp+:lg_sets_lp], counter_r}
: addr_tl_r[byte_sel_width_lp+:lg_block_size_in_words_lp+lg_sets_lp];
assign data_mem_pkt.sigext_op = decode_tl_r.sigext_op;
assign data_mem_pkt.size_op = decode_tl_r.block_ld_op
? (2)'($clog2(data_width_p>>3))
: decode_tl_r.size_op;
assign data_mem_pkt.byte_sel = decode_tl_r.block_ld_op
? {byte_sel_width_lp{1'b0}}
: addr_tl_r[0+:byte_sel_width_lp];
assign data_mem_pkt.data = data_tl_r;
assign data_mem_pkt.mask = mask_tl_r;
assign data_mem_pkt.mask_op = decode_tl_r.mask_op;
assign stat_mem_pkt.way_id = tag_hit_way;
assign stat_mem_pkt.index = addr_index_tl;
assign stat_mem_pkt.opcode = decode_tl_r.st_op
? e_stat_set_lru_and_dirty
: e_stat_set_lru;
assign miss_fifo_entry.write_not_read = decode_tl_r.st_op;
assign miss_fifo_entry.block_load = decode_tl_r.block_ld_op;
assign miss_fifo_entry.size_op = decode_tl_r.size_op;
assign miss_fifo_entry.id = id_tl_r;
assign miss_fifo_entry.addr = addr_tl_r;
assign miss_fifo_entry.data = data_tl_r;
assign miss_fifo_entry.sigext_op = decode_tl_r.sigext_op;
assign miss_fifo_entry.mask = mask_tl_r;
assign miss_fifo_entry.mask_op = decode_tl_r.mask_op;
// pipeline logic
//
logic miss_tl;
logic ld_st_hit;
logic block_ld_hit;
logic ld_st_miss;
logic ld_st_ready;
logic mgmt_op_tl;
assign miss_tl = tag_hit_found
? (mhu_miss_match | dma_miss_match)
: 1'b1;
assign ld_st_hit = v_tl_r & (decode_tl_r.ld_op | decode_tl_r.st_op) & ~miss_tl;
assign block_ld_hit = v_tl_r & decode_tl_r.block_ld_op & ~miss_tl;
assign ld_st_miss = v_tl_r & (decode_tl_r.ld_op | decode_tl_r.st_op | decode_tl_r.block_ld_op) & miss_tl;
assign ld_st_ready = data_mem_pkt_ready_i & stat_mem_pkt_ready_i;
assign mgmt_op_tl = v_tl_r & decode_tl_r.mgmt_op;
assign mgmt_v_o = mgmt_op_tl;
always_comb begin
ready_o = 1'b0;
data_mem_pkt_v_o = 1'b0;
stat_mem_pkt_v_o = 1'b0;
miss_fifo_v_o = 1'b0;
v_tl_n = v_tl_r;
tl_we = 1'b0;
tag_mem_v_li = 1'b0;
tag_mem_pkt = mhu_tag_mem_pkt;
block_mode_n = block_mode_r;
counter_up = 1'b0;
counter_clear = 1'b0;
// If there is cache management op, wait for MHU to yumi.
// Either mgmt or load/store op can come in next.
if (mgmt_op_tl) begin
ready_o = mgmt_yumi_i & ~mhu_tag_mem_pkt_v_i;
v_tl_n = mgmt_yumi_i
? (mhu_tag_mem_pkt_v_i
? 1'b0
: v_i)
: v_tl_r;
tl_we = mgmt_yumi_i & v_i & ~mhu_tag_mem_pkt_v_i;
tag_mem_v_li = mgmt_yumi_i & (v_i | mhu_tag_mem_pkt_v_i);
if (mhu_tag_mem_pkt_v_i) begin
tag_mem_pkt = mhu_tag_mem_pkt;
end
else begin
tag_mem_pkt.way_id = addr_way;
tag_mem_pkt.index = addr_index;
tag_mem_pkt.data = data_i;
tag_mem_pkt.opcode = decode_i.tagst_op
? e_tag_store
: e_tag_read;
end
end
// The recover signal from MHU forces the TL stage to read the tag_mem
// again using addr_tl. Recover logic is necessary, because when the MHU
// updates the tag, the tag_mem output may be stale, or the tag_mem output
// is perturbed, because the MHU also reads the tag_mem to make
// replacement decision to send out the next DMA request.
else if (recover_i) begin
tag_mem_v_li = v_tl_r;
tag_mem_pkt.index = addr_index_tl;
tag_mem_pkt.opcode = e_tag_read;
end
// When MHU reads the tag_mem, the TL stage is stalled.
else if (mhu_tag_mem_pkt_v_i) begin
tag_mem_v_li = 1'b1;
tag_mem_pkt = mhu_tag_mem_pkt;
end
// If there is a load/store hit, it waits for both data_mem and
// stat_mem to be ready.
else if (ld_st_hit) begin
data_mem_pkt_v_o = ld_st_ready;
stat_mem_pkt_v_o = ld_st_ready;
ready_o = ld_st_ready & ~mgmt_op_v;
v_tl_n = ld_st_ready
? (mgmt_op_v ? 1'b0 : v_i)
: v_tl_r;
tl_we = ld_st_ready & v_i & ~decode_i.mgmt_op;
tag_mem_v_li = ld_st_ready & v_i & ~decode_i.mgmt_op;
tag_mem_pkt.index = addr_index;
tag_mem_pkt.opcode = e_tag_read;
end
// If there is a load/store miss, it enques a new miss FIFO entry.
// If the miss FIFO is full, then the TL stage is stalled.
else if (ld_st_miss) begin
miss_fifo_v_o = 1'b1;
ready_o = miss_fifo_ready_i & ~mgmt_op_v;
v_tl_n = miss_fifo_ready_i
? (mgmt_op_v ? 1'b0 : v_i)
: v_tl_r;
tl_we = miss_fifo_ready_i & v_i & ~decode_i.mgmt_op;
tag_mem_v_li = miss_fifo_ready_i & v_i & ~decode_i.mgmt_op;
tag_mem_pkt.index = addr_index;
tag_mem_pkt.opcode = e_tag_read;
end
// If there is a block_load hit, it reads the data_mem word by word,
// whenever the data_mem is available. When it's time to read the last
// word in the block, it also updates the LRU bits.
// Once it reads the first word in the block, the block_mode signal goes
// on. During this time, the MHU cannot make any replacement decision or
// process any secondary miss.
else if (block_ld_hit) begin
data_mem_pkt_v_o = counter_max
? ld_st_ready
: data_mem_pkt_ready_i;
stat_mem_pkt_v_o = counter_max
? ld_st_ready
: 1'b0;
ready_o = ld_st_ready & ~mgmt_op_v & counter_max;
v_tl_n = (ld_st_ready & counter_max)
? (mgmt_op_v ? 1'b0 : v_i)
: v_tl_r;
tl_we = ld_st_ready & v_i & ~decode_i.mgmt_op & counter_max;
tag_mem_v_li = ld_st_ready & v_i & ~decode_i.mgmt_op & counter_max;
tag_mem_pkt.index = addr_index;
tag_mem_pkt.opcode = e_tag_read;
counter_up = ld_st_ready & ~counter_max;
counter_clear = ld_st_ready & counter_max;
block_mode_n = (counter_max ? ld_st_ready : data_mem_pkt_ready_i)
? (block_mode_r ? ~counter_max : 1'b1)
: block_mode_r;
end
else begin
// TL stage empty.
// cache management op cannot enter, if there is load/store in TL stage,
// or MHU is not idle.
ready_o = mgmt_op_v
? mhu_idle_i
: 1'b1;
v_tl_n = mgmt_op_v
? (mhu_idle_i ? v_i : 1'b0)
: v_i;
tl_we = mgmt_op_v
? (mhu_idle_i ? v_i : 1'b0)
: v_i;
tag_mem_v_li = mgmt_op_v
? (mhu_idle_i ? v_i : 1'b0)
: v_i;
tag_mem_pkt.way_id = addr_way;
tag_mem_pkt.index = addr_index;
tag_mem_pkt.data = data_i;
tag_mem_pkt.opcode = decode_i.tagst_op
? e_tag_store
: e_tag_read;
end
end
// synopsys translate_off
always_ff @ (negedge clk_i) begin
if (~reset_i & v_tl_r) begin
assert($countones(tag_hit) <= 1)
else $error("[BSG_ERROR] %m. t=%t. multiple hits detected.", $time);
end
if (~reset_i & v_tl_r) begin
assert($countones(lock_tl) <= ways_p-2)
else $error("[BSG_ERROR] %m. t=%t. There needs to be at least 2 unlocked ways.]", $time);
end
end
// synopsys translate_on
endmodule |
module sky130_fd_sc_ls__tapvpwrvgnd_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__tapvpwrvgnd base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ls__tapvpwrvgnd_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__tapvpwrvgnd base ();
endmodule |
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ms__clkdlyinv5sd1 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule |
module top(
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
Vaux13_v_n,
Vaux13_v_p,
Vaux15_v_n,
Vaux15_v_p,
Vaux1_v_n,
Vaux1_v_p,
Vaux5_v_n,
Vaux5_v_p,
Vaux6_v_n,
Vaux6_v_p,
Vaux9_v_n,
Vaux9_v_p,
Vp_Vn_v_n,
Vp_Vn_v_p,
btns_4bits_tri_i,
gpio_shield_sw_a5_a0_tri_io,
gpio_shield_sw_d13_d2_tri_io,
gpio_shield_sw_d1_d0_tri_io,
hdmi_in_clk_n,
hdmi_in_clk_p,
hdmi_in_data_n,
hdmi_in_data_p,
hdmi_in_ddc_scl_io,
hdmi_in_ddc_sda_io,
hdmi_in_hpd,
hdmi_out_clk_n,
hdmi_out_clk_p,
hdmi_out_data_n,
hdmi_out_data_p,
hdmi_out_ddc_scl_io,
hdmi_out_ddc_sda_io,
hdmi_out_hpd,
iic_sw_shield_scl_io,
iic_sw_shield_sda_io,
leds_4bits_tri_o,
spi_sw_shield_io0_io,
spi_sw_shield_io1_io,
spi_sw_shield_sck_io,
spi_sw_shield_ss_io,
pmodJA,
pmodJB,
pdm_audio_shutdown,
pdm_m_clk,
pdm_m_data_i,
pwm_audio_o,
rgbleds_6bits_tri_o,
sws_2bits_tri_i);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input Vaux13_v_n;
input Vaux13_v_p;
input Vaux15_v_n;
input Vaux15_v_p;
input Vaux1_v_n;
input Vaux1_v_p;
input Vaux5_v_n;
input Vaux5_v_p;
input Vaux6_v_n;
input Vaux6_v_p;
input Vaux9_v_n;
input Vaux9_v_p;
input Vp_Vn_v_n;
input Vp_Vn_v_p;
input [3:0]btns_4bits_tri_i;
inout [5:0]gpio_shield_sw_a5_a0_tri_io;
inout [11:0]gpio_shield_sw_d13_d2_tri_io;
inout [1:0]gpio_shield_sw_d1_d0_tri_io;
input hdmi_in_clk_n;
input hdmi_in_clk_p;
input [2:0]hdmi_in_data_n;
input [2:0]hdmi_in_data_p;
inout hdmi_in_ddc_scl_io;
inout hdmi_in_ddc_sda_io;
output [0:0]hdmi_in_hpd;
output hdmi_out_clk_n;
output hdmi_out_clk_p;
output [2:0]hdmi_out_data_n;
output [2:0]hdmi_out_data_p;
inout hdmi_out_ddc_scl_io;
inout hdmi_out_ddc_sda_io;
output [0:0]hdmi_out_hpd;
inout iic_sw_shield_scl_io;
inout iic_sw_shield_sda_io;
output [3:0]leds_4bits_tri_o;
input [1:0]sws_2bits_tri_i;
inout spi_sw_shield_io0_io;
inout spi_sw_shield_io1_io;
inout spi_sw_shield_sck_io;
inout spi_sw_shield_ss_io;
inout [7:0]pmodJA;
inout [7:0]pmodJB;
output [0:0]pdm_audio_shutdown;
output [0:0]pdm_m_clk;
input pdm_m_data_i;
output [5:0]rgbleds_6bits_tri_o;
output [0:0]pwm_audio_o;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire Vaux13_v_n;
wire Vaux13_v_p;
wire Vaux15_v_n;
wire Vaux15_v_p;
wire Vaux1_v_n;
wire Vaux1_v_p;
wire Vaux5_v_n;
wire Vaux5_v_p;
wire Vaux6_v_n;
wire Vaux6_v_p;
wire Vaux9_v_n;
wire Vaux9_v_p;
wire Vp_Vn_v_n;
wire Vp_Vn_v_p;
wire [3:0]btns_4bits_tri_i;
wire [5:0]shield2sw_data_in_a5_a0;
wire [11:0]shield2sw_data_in_d13_d2;
wire [1:0]shield2sw_data_in_d1_d0;
wire [5:0]sw2shield_data_out_a5_a0;
wire [11:0]sw2shield_data_out_d13_d2;
wire [1:0]sw2shield_data_out_d1_d0;
wire [5:0]sw2shield_tri_out_a5_a0;
wire [11:0]sw2shield_tri_out_d13_d2;
wire [1:0]sw2shield_tri_out_d1_d0;
// wire [0:0]gpio_shield_sw_a5_a0_tri_i_0;
// wire [1:1]gpio_shield_sw_a5_a0_tri_i_1;
// wire [2:2]gpio_shield_sw_a5_a0_tri_i_2;
// wire [3:3]gpio_shield_sw_a5_a0_tri_i_3;
// wire [4:4]gpio_shield_sw_a5_a0_tri_i_4;
// wire [5:5]gpio_shield_sw_a5_a0_tri_i_5;
// wire [0:0]gpio_shield_sw_a5_a0_tri_io_0;
// wire [1:1]gpio_shield_sw_a5_a0_tri_io_1;
// wire [2:2]gpio_shield_sw_a5_a0_tri_io_2;
// wire [3:3]gpio_shield_sw_a5_a0_tri_io_3;
// wire [4:4]gpio_shield_sw_a5_a0_tri_io_4;
// wire [5:5]gpio_shield_sw_a5_a0_tri_io_5;
// wire [0:0]gpio_shield_sw_a5_a0_tri_o_0;
// wire [1:1]gpio_shield_sw_a5_a0_tri_o_1;
// wire [2:2]gpio_shield_sw_a5_a0_tri_o_2;
// wire [3:3]gpio_shield_sw_a5_a0_tri_o_3;
// wire [4:4]gpio_shield_sw_a5_a0_tri_o_4;
// wire [5:5]gpio_shield_sw_a5_a0_tri_o_5;
// wire [0:0]gpio_shield_sw_a5_a0_tri_t_0;
// wire [1:1]gpio_shield_sw_a5_a0_tri_t_1;
// wire [2:2]gpio_shield_sw_a5_a0_tri_t_2;
// wire [3:3]gpio_shield_sw_a5_a0_tri_t_3;
// wire [4:4]gpio_shield_sw_a5_a0_tri_t_4;
// wire [5:5]gpio_shield_sw_a5_a0_tri_t_5;
// wire [0:0]gpio_shield_sw_d13_d2_tri_i_0;
// wire [1:1]gpio_shield_sw_d13_d2_tri_i_1;
// wire [10:10]gpio_shield_sw_d13_d2_tri_i_10;
// wire [11:11]gpio_shield_sw_d13_d2_tri_i_11;
// wire [2:2]gpio_shield_sw_d13_d2_tri_i_2;
// wire [3:3]gpio_shield_sw_d13_d2_tri_i_3;
// wire [4:4]gpio_shield_sw_d13_d2_tri_i_4;
// wire [5:5]gpio_shield_sw_d13_d2_tri_i_5;
// wire [6:6]gpio_shield_sw_d13_d2_tri_i_6;
// wire [7:7]gpio_shield_sw_d13_d2_tri_i_7;
// wire [8:8]gpio_shield_sw_d13_d2_tri_i_8;
// wire [9:9]gpio_shield_sw_d13_d2_tri_i_9;
// wire [0:0]gpio_shield_sw_d13_d2_tri_io_0;
// wire [1:1]gpio_shield_sw_d13_d2_tri_io_1;
// wire [10:10]gpio_shield_sw_d13_d2_tri_io_10;
// wire [11:11]gpio_shield_sw_d13_d2_tri_io_11;
// wire [2:2]gpio_shield_sw_d13_d2_tri_io_2;
// wire [3:3]gpio_shield_sw_d13_d2_tri_io_3;
// wire [4:4]gpio_shield_sw_d13_d2_tri_io_4;
// wire [5:5]gpio_shield_sw_d13_d2_tri_io_5;
// wire [6:6]gpio_shield_sw_d13_d2_tri_io_6;
// wire [7:7]gpio_shield_sw_d13_d2_tri_io_7;
// wire [8:8]gpio_shield_sw_d13_d2_tri_io_8;
// wire [9:9]gpio_shield_sw_d13_d2_tri_io_9;
// wire [0:0]gpio_shield_sw_d13_d2_tri_o_0;
// wire [1:1]gpio_shield_sw_d13_d2_tri_o_1;
// wire [10:10]gpio_shield_sw_d13_d2_tri_o_10;
// wire [11:11]gpio_shield_sw_d13_d2_tri_o_11;
// wire [2:2]gpio_shield_sw_d13_d2_tri_o_2;
// wire [3:3]gpio_shield_sw_d13_d2_tri_o_3;
// wire [4:4]gpio_shield_sw_d13_d2_tri_o_4;
// wire [5:5]gpio_shield_sw_d13_d2_tri_o_5;
// wire [6:6]gpio_shield_sw_d13_d2_tri_o_6;
// wire [7:7]gpio_shield_sw_d13_d2_tri_o_7;
// wire [8:8]gpio_shield_sw_d13_d2_tri_o_8;
// wire [9:9]gpio_shield_sw_d13_d2_tri_o_9;
// wire [0:0]gpio_shield_sw_d13_d2_tri_t_0;
// wire [1:1]gpio_shield_sw_d13_d2_tri_t_1;
// wire [10:10]gpio_shield_sw_d13_d2_tri_t_10;
// wire [11:11]gpio_shield_sw_d13_d2_tri_t_11;
// wire [2:2]gpio_shield_sw_d13_d2_tri_t_2;
// wire [3:3]gpio_shield_sw_d13_d2_tri_t_3;
// wire [4:4]gpio_shield_sw_d13_d2_tri_t_4;
// wire [5:5]gpio_shield_sw_d13_d2_tri_t_5;
// wire [6:6]gpio_shield_sw_d13_d2_tri_t_6;
// wire [7:7]gpio_shield_sw_d13_d2_tri_t_7;
// wire [8:8]gpio_shield_sw_d13_d2_tri_t_8;
// wire [9:9]gpio_shield_sw_d13_d2_tri_t_9;
// wire [0:0]gpio_shield_sw_d1_d0_tri_i_0;
// wire [1:1]gpio_shield_sw_d1_d0_tri_i_1;
// wire [0:0]gpio_shield_sw_d1_d0_tri_io_0;
// wire [1:1]gpio_shield_sw_d1_d0_tri_io_1;
// wire [0:0]gpio_shield_sw_d1_d0_tri_o_0;
// wire [1:1]gpio_shield_sw_d1_d0_tri_o_1;
// wire [0:0]gpio_shield_sw_d1_d0_tri_t_0;
// wire [1:1]gpio_shield_sw_d1_d0_tri_t_1;
wire hdmi_in_clk_n;
wire hdmi_in_clk_p;
wire [2:0]hdmi_in_data_n;
wire [2:0]hdmi_in_data_p;
wire hdmi_in_ddc_scl_i;
wire hdmi_in_ddc_scl_io;
wire hdmi_in_ddc_scl_o;
wire hdmi_in_ddc_scl_t;
wire hdmi_in_ddc_sda_i;
wire hdmi_in_ddc_sda_io;
wire hdmi_in_ddc_sda_o;
wire hdmi_in_ddc_sda_t;
wire [0:0]hdmi_in_hpd;
wire hdmi_out_clk_n;
wire hdmi_out_clk_p;
wire [2:0]hdmi_out_data_n;
wire [2:0]hdmi_out_data_p;
wire hdmi_out_ddc_scl_i;
wire hdmi_out_ddc_scl_io;
wire hdmi_out_ddc_scl_o;
wire hdmi_out_ddc_scl_t;
wire hdmi_out_ddc_sda_i;
wire hdmi_out_ddc_sda_io;
wire hdmi_out_ddc_sda_o;
wire hdmi_out_ddc_sda_t;
wire [0:0]hdmi_out_hpd;
wire shield2sw_scl_i_in;
wire shield2sw_sda_i_in;
wire sw2shield_scl_o_out;
wire sw2shield_scl_t_out;
wire sw2shield_sda_o_out;
wire sw2shield_sda_t_out;
// wire iic_sw_shield_scl_i;
wire iic_sw_shield_scl_io;
// wire iic_sw_shield_scl_o;
// wire iic_sw_shield_scl_t;
// wire iic_sw_shield_sda_i;
wire iic_sw_shield_sda_io;
// wire iic_sw_shield_sda_o;
// wire iic_sw_shield_sda_t;
wire [3:0]leds_4bits_tri_o;
wire [7:0]pmodJA_data_in;
wire [7:0]pmodJA_data_out;
wire [7:0]pmodJA_tri_out;
wire [7:0]pmodJB_data_in;
wire [7:0]pmodJB_data_out;
wire [7:0]pmodJB_tri_out;
wire spi_sw_shield_io0_i;
wire spi_sw_shield_io0_io;
wire spi_sw_shield_io0_o;
wire spi_sw_shield_io0_t;
wire spi_sw_shield_io1_i;
wire spi_sw_shield_io1_io;
wire spi_sw_shield_io1_o;
wire spi_sw_shield_io1_t;
wire spi_sw_shield_sck_i;
wire spi_sw_shield_sck_io;
wire spi_sw_shield_sck_o;
wire spi_sw_shield_sck_t;
wire spi_sw_shield_ss_i;
wire spi_sw_shield_ss_io;
wire spi_sw_shield_ss_o;
wire spi_sw_shield_ss_t;
wire [1:0]sws_2bits_tri_i;
wire [7:0]pmodJA;
wire [7:0]pmodJB;
wire [0:0]pdm_audio_shutdown;
wire [0:0]pdm_m_clk;
wire pdm_m_data_i;
wire [5:0]rgbleds_6bits_tri_o;
wire [0:0]pwm_audio_o;
// for HDMI in
IOBUF hdmi_in_ddc_scl_iobuf
(.I(hdmi_in_ddc_scl_o),
.IO(hdmi_in_ddc_scl_io),
.O(hdmi_in_ddc_scl_i),
.T(hdmi_in_ddc_scl_t));
IOBUF hdmi_in_ddc_sda_iobuf
(.I(hdmi_in_ddc_sda_o),
.IO(hdmi_in_ddc_sda_io),
.O(hdmi_in_ddc_sda_i),
.T(hdmi_in_ddc_sda_t));
// for HDMI out
IOBUF hdmi_out_ddc_scl_iobuf
(.I(hdmi_out_ddc_scl_o),
.IO(hdmi_out_ddc_scl_io),
.O(hdmi_out_ddc_scl_i),
.T(hdmi_out_ddc_scl_t));
IOBUF hdmi_out_ddc_sda_iobuf
(.I(hdmi_out_ddc_sda_o),
.IO(hdmi_out_ddc_sda_io),
.O(hdmi_out_ddc_sda_i),
.T(hdmi_out_ddc_sda_t));
// pmodJB related iobufs
IOBUF pmodJB_data_iobuf_0
(.I(pmodJB_data_out[0]),
.IO(pmodJB[0]),
.O(pmodJB_data_in[0]),
.T(pmodJB_tri_out[0]));
IOBUF pmodJB_data_iobuf_1
(.I(pmodJB_data_out[1]),
.IO(pmodJB[1]),
.O(pmodJB_data_in[1]),
.T(pmodJB_tri_out[1]));
IOBUF pmodJB_data_iobuf2
(.I(pmodJB_data_out[2]),
.IO(pmodJB[2]),
.O(pmodJB_data_in[2]),
.T(pmodJB_tri_out[2]));
IOBUF pmodJB_data_iobuf_3
(.I(pmodJB_data_out[3]),
.IO(pmodJB[3]),
.O(pmodJB_data_in[3]),
.T(pmodJB_tri_out[3]));
IOBUF pmodJB_data_iobuf_4
(.I(pmodJB_data_out[4]),
.IO(pmodJB[4]),
.O(pmodJB_data_in[4]),
.T(pmodJB_tri_out[4]));
IOBUF pmodJB_data_iobuf_5
(.I(pmodJB_data_out[5]),
.IO(pmodJB[5]),
.O(pmodJB_data_in[5]),
.T(pmodJB_tri_out[5]));
IOBUF pmodJB_data_iobuf_6
(.I(pmodJB_data_out[6]),
.IO(pmodJB[6]),
.O(pmodJB_data_in[6]),
.T(pmodJB_tri_out[6]));
IOBUF pmodJB_data_iobuf_7
(.I(pmodJB_data_out[7]),
.IO(pmodJB[7]),
.O(pmodJB_data_in[7]),
.T(pmodJB_tri_out[7]));
// pmodJA related iobufs
IOBUF pmodJA_data_iobuf_0
(.I(pmodJA_data_out[0]),
.IO(pmodJA[0]),
.O(pmodJA_data_in[0]),
.T(pmodJA_tri_out[0]));
IOBUF pmodJA_data_iobuf_1
(.I(pmodJA_data_out[1]),
.IO(pmodJA[1]),
.O(pmodJA_data_in[1]),
.T(pmodJA_tri_out[1]));
IOBUF pmodJA_data_iobuf2
(.I(pmodJA_data_out[2]),
.IO(pmodJA[2]),
.O(pmodJA_data_in[2]),
.T(pmodJA_tri_out[2]));
IOBUF pmodJA_data_iobuf_3
(.I(pmodJA_data_out[3]),
.IO(pmodJA[3]),
.O(pmodJA_data_in[3]),
.T(pmodJA_tri_out[3]));
IOBUF pmodJA_data_iobuf_4
(.I(pmodJA_data_out[4]),
.IO(pmodJA[4]),
.O(pmodJA_data_in[4]),
.T(pmodJA_tri_out[4]));
IOBUF pmodJA_data_iobuf_5
(.I(pmodJA_data_out[5]),
.IO(pmodJA[5]),
.O(pmodJA_data_in[5]),
.T(pmodJA_tri_out[5]));
IOBUF pmodJA_data_iobuf_6
(.I(pmodJA_data_out[6]),
.IO(pmodJA[6]),
.O(pmodJA_data_in[6]),
.T(pmodJA_tri_out[6]));
IOBUF pmodJA_data_iobuf_7
(.I(pmodJA_data_out[7]),
.IO(pmodJA[7]),
.O(pmodJA_data_in[7]),
.T(pmodJA_tri_out[7]));
// Arduino shield related iobufs
IOBUF gpio_shield_sw_a5_a0_tri_iobuf_0
(.I(sw2shield_data_out_a5_a0[0]),
.IO(gpio_shield_sw_a5_a0_tri_io[0]),
.O(shield2sw_data_in_a5_a0[0]),
.T(sw2shield_tri_out_a5_a0[0]));
IOBUF gpio_shield_sw_a5_a0_tri_iobuf_1
(.I(sw2shield_data_out_a5_a0[1]),
.IO(gpio_shield_sw_a5_a0_tri_io[1]),
.O(shield2sw_data_in_a5_a0[1]),
.T(sw2shield_tri_out_a5_a0[1]));
IOBUF gpio_shield_sw_a5_a0_tri_iobuf_2
(.I(sw2shield_data_out_a5_a0[2]),
.IO(gpio_shield_sw_a5_a0_tri_io[2]),
.O(shield2sw_data_in_a5_a0[2]),
.T(sw2shield_tri_out_a5_a0[2]));
IOBUF gpio_shield_sw_a5_a0_tri_iobuf_3
(.I(sw2shield_data_out_a5_a0[3]),
.IO(gpio_shield_sw_a5_a0_tri_io[3]),
.O(shield2sw_data_in_a5_a0[3]),
.T(sw2shield_tri_out_a5_a0[3]));
IOBUF gpio_shield_sw_a5_a0_tri_iobuf_4
(.I(sw2shield_data_out_a5_a0[4]),
.IO(gpio_shield_sw_a5_a0_tri_io[4]),
.O(shield2sw_data_in_a5_a0[4]),
.T(sw2shield_tri_out_a5_a0[4]));
IOBUF gpio_shield_sw_a5_a0_tri_iobuf_5
(.I(sw2shield_data_out_a5_a0[5]),
.IO(gpio_shield_sw_a5_a0_tri_io[5]),
.O(shield2sw_data_in_a5_a0[5]),
.T(sw2shield_tri_out_a5_a0[5]));
IOBUF gpio_shield_sw_d13_d2_tri_iobuf_0
(.I(sw2shield_data_out_d13_d2[0]),
.IO(gpio_shield_sw_d13_d2_tri_io[0]),
.O(shield2sw_data_in_d13_d2[0]),
.T(sw2shield_tri_out_d13_d2[0]));
IOBUF gpio_shield_sw_d13_d2_tri_iobuf_1
(.I(sw2shield_data_out_d13_d2[1]),
.IO(gpio_shield_sw_d13_d2_tri_io[1]),
.O(shield2sw_data_in_d13_d2[1]),
.T(sw2shield_tri_out_d13_d2[1]));
IOBUF gpio_shield_sw_d13_d2_tri_iobuf_10
(.I(sw2shield_data_out_d13_d2[10]),
.IO(gpio_shield_sw_d13_d2_tri_io[10]),
.O(shield2sw_data_in_d13_d2[10]),
.T(sw2shield_tri_out_d13_d2[10]));
IOBUF gpio_shield_sw_d13_d2_tri_iobuf_11
(.I(sw2shield_data_out_d13_d2[11]),
.IO(gpio_shield_sw_d13_d2_tri_io[11]),
.O(shield2sw_data_in_d13_d2[11]),
.T(sw2shield_tri_out_d13_d2[11]));
IOBUF gpio_shield_sw_d13_d2_tri_iobuf_2
(.I(sw2shield_data_out_d13_d2[2]),
.IO(gpio_shield_sw_d13_d2_tri_io[2]),
.O(shield2sw_data_in_d13_d2[2]),
.T(sw2shield_tri_out_d13_d2[2]));
IOBUF gpio_shield_sw_d13_d2_tri_iobuf_3
(.I(sw2shield_data_out_d13_d2[3]),
.IO(gpio_shield_sw_d13_d2_tri_io[3]),
.O(shield2sw_data_in_d13_d2[3]),
.T(sw2shield_tri_out_d13_d2[3]));
IOBUF gpio_shield_sw_d13_d2_tri_iobuf_4
(.I(sw2shield_data_out_d13_d2[4]),
.IO(gpio_shield_sw_d13_d2_tri_io[4]),
.O(shield2sw_data_in_d13_d2[4]),
.T(sw2shield_tri_out_d13_d2[4]));
IOBUF gpio_shield_sw_d13_d2_tri_iobuf_5
(.I(sw2shield_data_out_d13_d2[5]),
.IO(gpio_shield_sw_d13_d2_tri_io[5]),
.O(shield2sw_data_in_d13_d2[5]),
.T(sw2shield_tri_out_d13_d2[5]));
IOBUF gpio_shield_sw_d13_d2_tri_iobuf_6
(.I(sw2shield_data_out_d13_d2[6]),
.IO(gpio_shield_sw_d13_d2_tri_io[6]),
.O(shield2sw_data_in_d13_d2[6]),
.T(sw2shield_tri_out_d13_d2[6]));
IOBUF gpio_shield_sw_d13_d2_tri_iobuf_7
(.I(sw2shield_data_out_d13_d2[7]),
.IO(gpio_shield_sw_d13_d2_tri_io[7]),
.O(shield2sw_data_in_d13_d2[7]),
.T(sw2shield_tri_out_d13_d2[7]));
IOBUF gpio_shield_sw_d13_d2_tri_iobuf_8
(.I(sw2shield_data_out_d13_d2[8]),
.IO(gpio_shield_sw_d13_d2_tri_io[8]),
.O(shield2sw_data_in_d13_d2[8]),
.T(sw2shield_tri_out_d13_d2[8]));
IOBUF gpio_shield_sw_d13_d2_tri_iobuf_9
(.I(sw2shield_data_out_d13_d2[9]),
.IO(gpio_shield_sw_d13_d2_tri_io[9]),
.O(shield2sw_data_in_d13_d2[9]),
.T(sw2shield_tri_out_d13_d2[9]));
IOBUF gpio_shield_sw_d1_d0_tri_iobuf_0
(.I(sw2shield_data_out_d1_d0[0]),
.IO(gpio_shield_sw_d1_d0_tri_io[0]),
.O(shield2sw_data_in_d1_d0[0]),
.T(sw2shield_tri_out_d1_d0[0]));
IOBUF gpio_shield_sw_d1_d0_tri_iobuf_1
(.I(sw2shield_data_out_d1_d0[1]),
.IO(gpio_shield_sw_d1_d0_tri_io[1]),
.O(shield2sw_data_in_d1_d0[1]),
.T(sw2shield_tri_out_d1_d0[1]));
// Dedicated Arduino IIC shield2sw_scl_i_in
IOBUF iic_sw_shield_scl_iobuf
(.I(sw2shield_scl_o_out),
.IO(iic_sw_shield_scl_io),
.O(shield2sw_scl_i_in),
.T(sw2shield_scl_t_out));
IOBUF iic_sw_shield_sda_iobuf
(.I(sw2shield_sda_o_out),
.IO(iic_sw_shield_sda_io),
.O(shield2sw_sda_i_in),
.T(sw2shield_sda_t_out));
// Dedicated Arduino SPI
IOBUF spi_sw_shield_io0_iobuf
(.I(spi_sw_shield_io0_o),
.IO(spi_sw_shield_io0_io),
.O(spi_sw_shield_io0_i),
.T(spi_sw_shield_io0_t));
IOBUF spi_sw_shield_io1_iobuf
(.I(spi_sw_shield_io1_o),
.IO(spi_sw_shield_io1_io),
.O(spi_sw_shield_io1_i),
.T(spi_sw_shield_io1_t));
IOBUF spi_sw_shield_sck_iobuf
(.I(spi_sw_shield_sck_o),
.IO(spi_sw_shield_sck_io),
.O(spi_sw_shield_sck_i),
.T(spi_sw_shield_sck_t));
IOBUF spi_sw_shield_ss_iobuf
(.I(spi_sw_shield_ss_o),
.IO(spi_sw_shield_ss_io),
.O(spi_sw_shield_ss_i),
.T(spi_sw_shield_ss_t));
system system_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.Vaux13_v_n(Vaux13_v_n),
.Vaux13_v_p(Vaux13_v_p),
.Vaux15_v_n(Vaux15_v_n),
.Vaux15_v_p(Vaux15_v_p),
.Vaux1_v_n(Vaux1_v_n),
.Vaux1_v_p(Vaux1_v_p),
.Vaux5_v_n(Vaux5_v_n),
.Vaux5_v_p(Vaux5_v_p),
.Vaux6_v_n(Vaux6_v_n),
.Vaux6_v_p(Vaux6_v_p),
.Vaux9_v_n(Vaux9_v_n),
.Vaux9_v_p(Vaux9_v_p),
.Vp_Vn_v_n(Vp_Vn_v_n),
.Vp_Vn_v_p(Vp_Vn_v_p),
.btns_4bits_tri_i(btns_4bits_tri_i),
// .gpio_shield_sw_a5_a0_tri_i({gpio_shield_sw_a5_a0_tri_i_5,gpio_shield_sw_a5_a0_tri_i_4,gpio_shield_sw_a5_a0_tri_i_3,gpio_shield_sw_a5_a0_tri_i_2,gpio_shield_sw_a5_a0_tri_i_1,gpio_shield_sw_a5_a0_tri_i_0}),
// .gpio_shield_sw_a5_a0_tri_o({gpio_shield_sw_a5_a0_tri_o_5,gpio_shield_sw_a5_a0_tri_o_4,gpio_shield_sw_a5_a0_tri_o_3,gpio_shield_sw_a5_a0_tri_o_2,gpio_shield_sw_a5_a0_tri_o_1,gpio_shield_sw_a5_a0_tri_o_0}),
// .gpio_shield_sw_a5_a0_tri_t({gpio_shield_sw_a5_a0_tri_t_5,gpio_shield_sw_a5_a0_tri_t_4,gpio_shield_sw_a5_a0_tri_t_3,gpio_shield_sw_a5_a0_tri_t_2,gpio_shield_sw_a5_a0_tri_t_1,gpio_shield_sw_a5_a0_tri_t_0}),
// .gpio_shield_sw_d13_d2_tri_i({gpio_shield_sw_d13_d2_tri_i_11,gpio_shield_sw_d13_d2_tri_i_10,gpio_shield_sw_d13_d2_tri_i_9,gpio_shield_sw_d13_d2_tri_i_8,gpio_shield_sw_d13_d2_tri_i_7,gpio_shield_sw_d13_d2_tri_i_6,gpio_shield_sw_d13_d2_tri_i_5,gpio_shield_sw_d13_d2_tri_i_4,gpio_shield_sw_d13_d2_tri_i_3,gpio_shield_sw_d13_d2_tri_i_2,gpio_shield_sw_d13_d2_tri_i_1,gpio_shield_sw_d13_d2_tri_i_0}),
// .gpio_shield_sw_d13_d2_tri_o({gpio_shield_sw_d13_d2_tri_o_11,gpio_shield_sw_d13_d2_tri_o_10,gpio_shield_sw_d13_d2_tri_o_9,gpio_shield_sw_d13_d2_tri_o_8,gpio_shield_sw_d13_d2_tri_o_7,gpio_shield_sw_d13_d2_tri_o_6,gpio_shield_sw_d13_d2_tri_o_5,gpio_shield_sw_d13_d2_tri_o_4,gpio_shield_sw_d13_d2_tri_o_3,gpio_shield_sw_d13_d2_tri_o_2,gpio_shield_sw_d13_d2_tri_o_1,gpio_shield_sw_d13_d2_tri_o_0}),
// .gpio_shield_sw_d13_d2_tri_t({gpio_shield_sw_d13_d2_tri_t_11,gpio_shield_sw_d13_d2_tri_t_10,gpio_shield_sw_d13_d2_tri_t_9,gpio_shield_sw_d13_d2_tri_t_8,gpio_shield_sw_d13_d2_tri_t_7,gpio_shield_sw_d13_d2_tri_t_6,gpio_shield_sw_d13_d2_tri_t_5,gpio_shield_sw_d13_d2_tri_t_4,gpio_shield_sw_d13_d2_tri_t_3,gpio_shield_sw_d13_d2_tri_t_2,gpio_shield_sw_d13_d2_tri_t_1,gpio_shield_sw_d13_d2_tri_t_0}),
// .gpio_shield_sw_d1_d0_tri_i({gpio_shield_sw_d1_d0_tri_i_1,gpio_shield_sw_d1_d0_tri_i_0}),
// .gpio_shield_sw_d1_d0_tri_o({gpio_shield_sw_d1_d0_tri_o_1,gpio_shield_sw_d1_d0_tri_o_0}),
// .gpio_shield_sw_d1_d0_tri_t({gpio_shield_sw_d1_d0_tri_t_1,gpio_shield_sw_d1_d0_tri_t_0}),
.shield2sw_data_in_a5_a0(shield2sw_data_in_a5_a0),
.shield2sw_data_in_d13_d2(shield2sw_data_in_d13_d2),
.shield2sw_data_in_d1_d0(shield2sw_data_in_d1_d0),
.sw2shield_data_out_a5_a0(sw2shield_data_out_a5_a0),
.sw2shield_data_out_d13_d2(sw2shield_data_out_d13_d2),
.sw2shield_data_out_d1_d0(sw2shield_data_out_d1_d0),
.sw2shield_tri_out_a5_a0(sw2shield_tri_out_a5_a0),
.sw2shield_tri_out_d13_d2(sw2shield_tri_out_d13_d2),
.sw2shield_tri_out_d1_d0(sw2shield_tri_out_d1_d0),
.hdmi_in_clk_n(hdmi_in_clk_n),
.hdmi_in_clk_p(hdmi_in_clk_p),
.hdmi_in_data_n(hdmi_in_data_n),
.hdmi_in_data_p(hdmi_in_data_p),
.hdmi_in_ddc_scl_i(hdmi_in_ddc_scl_i),
.hdmi_in_ddc_scl_o(hdmi_in_ddc_scl_o),
.hdmi_in_ddc_scl_t(hdmi_in_ddc_scl_t),
.hdmi_in_ddc_sda_i(hdmi_in_ddc_sda_i),
.hdmi_in_ddc_sda_o(hdmi_in_ddc_sda_o),
.hdmi_in_ddc_sda_t(hdmi_in_ddc_sda_t),
.hdmi_in_hpd(hdmi_in_hpd),
.hdmi_out_clk_n(hdmi_out_clk_n),
.hdmi_out_clk_p(hdmi_out_clk_p),
.hdmi_out_data_n(hdmi_out_data_n),
.hdmi_out_data_p(hdmi_out_data_p),
.hdmi_out_ddc_scl_i(hdmi_out_ddc_scl_i),
.hdmi_out_ddc_scl_o(hdmi_out_ddc_scl_o),
.hdmi_out_ddc_scl_t(hdmi_out_ddc_scl_t),
.hdmi_out_ddc_sda_i(hdmi_out_ddc_sda_i),
.hdmi_out_ddc_sda_o(hdmi_out_ddc_sda_o),
.hdmi_out_ddc_sda_t(hdmi_out_ddc_sda_t),
.hdmi_out_hpd(hdmi_out_hpd),
// .iic_sw_shield_scl_i(iic_sw_shield_scl_i),
// .iic_sw_shield_scl_o(iic_sw_shield_scl_o),
// .iic_sw_shield_scl_t(iic_sw_shield_scl_t),
// .iic_sw_shield_sda_i(iic_sw_shield_sda_i),
// .iic_sw_shield_sda_o(iic_sw_shield_sda_o),
// .iic_sw_shield_sda_t(iic_sw_shield_sda_t),
.shield2sw_scl_i_in(shield2sw_scl_i_in),
.shield2sw_sda_i_in(shield2sw_sda_i_in),
.sw2shield_scl_o_out(sw2shield_scl_o_out),
.sw2shield_scl_t_out(sw2shield_scl_t_out),
.sw2shield_sda_o_out(sw2shield_sda_o_out),
.sw2shield_sda_t_out(sw2shield_sda_t_out),
.leds_4bits_tri_o(leds_4bits_tri_o),
.pmodJB_data_in(pmodJB_data_in),
.pmodJB_data_out(pmodJB_data_out),
.pmodJB_tri_out(pmodJB_tri_out),
.pmodJA_data_in(pmodJA_data_in),
.pmodJA_data_out(pmodJA_data_out),
.pmodJA_tri_out(pmodJA_tri_out),
.pdm_audio_shutdown(pdm_audio_shutdown),
.pdm_m_clk(pdm_m_clk),
.pdm_m_data_i(pdm_m_data_i),
.rgbleds_6bits_tri_o(rgbleds_6bits_tri_o),
.pwm_audio_o(pwm_audio_o),
.spi_sw_shield_io0_i(spi_sw_shield_io0_i),
.spi_sw_shield_io0_o(spi_sw_shield_io0_o),
.spi_sw_shield_io0_t(spi_sw_shield_io0_t),
.spi_sw_shield_io1_i(spi_sw_shield_io1_i),
.spi_sw_shield_io1_o(spi_sw_shield_io1_o),
.spi_sw_shield_io1_t(spi_sw_shield_io1_t),
.spi_sw_shield_sck_i(spi_sw_shield_sck_i),
.spi_sw_shield_sck_o(spi_sw_shield_sck_o),
.spi_sw_shield_sck_t(spi_sw_shield_sck_t),
.spi_sw_shield_ss_i(spi_sw_shield_ss_i),
.spi_sw_shield_ss_o(spi_sw_shield_ss_o),
.spi_sw_shield_ss_t(spi_sw_shield_ss_t),
.sws_2bits_tri_i(sws_2bits_tri_i));
endmodule |
module FSM_Mult_Function ( clk, rst, beg_FSM, ack_FSM, zero_flag_i,
Mult_shift_i, round_flag_i, Add_Overflow_i, load_0_o, load_1_o,
load_2_o, load_3_o, load_4_o, load_5_o, load_6_o, ctrl_select_a_o,
ctrl_select_b_o, selector_b_o, ctrl_select_c_o, exp_op_o,
shift_value_o, rst_int, ready );
output [1:0] selector_b_o;
input clk, rst, beg_FSM, ack_FSM, zero_flag_i, Mult_shift_i, round_flag_i,
Add_Overflow_i;
output load_0_o, load_1_o, load_2_o, load_3_o, load_4_o, load_5_o, load_6_o,
ctrl_select_a_o, ctrl_select_b_o, ctrl_select_c_o, exp_op_o,
shift_value_o, rst_int, ready;
wire n8, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25,
n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39,
n40, n41, n3, load_1_o, n6, n12;
wire [3:0] state_reg;
assign ctrl_select_a_o = load_1_o;
DFFRX2TS state_reg_reg_3_ ( .D(n40), .CK(clk), .RN(n12), .Q(state_reg[3]),
.QN(n8) );
DFFRX2TS state_reg_reg_0_ ( .D(n41), .CK(clk), .RN(n12), .Q(state_reg[0]),
.QN(n14) );
DFFRX2TS state_reg_reg_2_ ( .D(n38), .CK(clk), .RN(n12), .Q(state_reg[2]) );
DFFRX2TS state_reg_reg_1_ ( .D(n39), .CK(clk), .RN(n12), .Q(state_reg[1]),
.QN(n13) );
AOI32X1TS U3 ( .A0(n36), .A1(n14), .A2(state_reg[1]), .B0(n27), .B1(
Add_Overflow_i), .Y(n15) );
NOR2X2TS U4 ( .A(state_reg[1]), .B(state_reg[0]), .Y(n35) );
NOR2X2TS U5 ( .A(state_reg[2]), .B(state_reg[3]), .Y(n28) );
NAND3X1TS U6 ( .A(n37), .B(n13), .C(state_reg[0]), .Y(n29) );
AOI21X1TS U7 ( .A0(state_reg[1]), .A1(n36), .B0(n27), .Y(n30) );
NAND3X1TS U8 ( .A(n36), .B(n13), .C(state_reg[0]), .Y(n21) );
INVX2TS U9 ( .A(n19), .Y(exp_op_o) );
INVX2TS U10 ( .A(n24), .Y(n6) );
INVX2TS U11 ( .A(n17), .Y(rst_int) );
NAND2X2TS U12 ( .A(n35), .B(n36), .Y(n19) );
NAND2BX1TS U13 ( .AN(load_3_o), .B(n20), .Y(load_2_o) );
NAND2X1TS U14 ( .A(n19), .B(n15), .Y(load_3_o) );
INVX2TS U15 ( .A(n15), .Y(shift_value_o) );
INVX2TS U16 ( .A(n18), .Y(ready) );
INVX2TS U17 ( .A(n20), .Y(load_1_o) );
NAND2X1TS U18 ( .A(n35), .B(n37), .Y(n24) );
NAND2X1TS U19 ( .A(n35), .B(n28), .Y(n17) );
INVX2TS U20 ( .A(n29), .Y(load_4_o) );
NAND2X1TS U21 ( .A(n20), .B(n29), .Y(selector_b_o[0]) );
INVX2TS U22 ( .A(n31), .Y(load_5_o) );
INVX2TS U23 ( .A(n21), .Y(n3) );
INVX2TS U24 ( .A(n30), .Y(load_6_o) );
NOR2BX2TS U25 ( .AN(state_reg[2]), .B(state_reg[3]), .Y(n36) );
OAI22X2TS U26 ( .A0(beg_FSM), .A1(n17), .B0(ack_FSM), .B1(n18), .Y(n23) );
NAND4X1TS U27 ( .A(n19), .B(n20), .C(n21), .D(n22), .Y(n38) );
AOI21X1TS U28 ( .A0(state_reg[2]), .A1(n23), .B0(load_5_o), .Y(n22) );
NAND4X1TS U29 ( .A(n29), .B(n30), .C(n31), .D(n32), .Y(n40) );
AOI221X1TS U30 ( .A0(state_reg[3]), .A1(n23), .B0(zero_flag_i), .B1(exp_op_o), .C0(n6), .Y(n32) );
NOR2X2TS U31 ( .A(n8), .B(state_reg[2]), .Y(n37) );
NAND3X1TS U32 ( .A(state_reg[2]), .B(state_reg[3]), .C(n35), .Y(n18) );
AND3X2TS U33 ( .A(n37), .B(n14), .C(state_reg[1]), .Y(n27) );
AOI21X1TS U34 ( .A0(n33), .A1(n34), .B0(n23), .Y(n41) );
AOI211X1TS U35 ( .A0(n28), .A1(n14), .B0(n27), .C0(n6), .Y(n34) );
OA22X1TS U36 ( .A0(n21), .A1(Mult_shift_i), .B0(n19), .B1(zero_flag_i), .Y(
n33) );
NAND3X2TS U37 ( .A(state_reg[0]), .B(state_reg[1]), .C(n28), .Y(n20) );
NOR3BX1TS U38 ( .AN(n28), .B(n14), .C(state_reg[1]), .Y(load_0_o) );
AO21X1TS U39 ( .A0(Mult_shift_i), .A1(n3), .B0(selector_b_o[0]), .Y(
ctrl_select_b_o) );
NAND3X1TS U40 ( .A(state_reg[1]), .B(n37), .C(state_reg[0]), .Y(n31) );
OAI211X1TS U41 ( .A0(round_flag_i), .A1(n24), .B0(n25), .C0(n26), .Y(n39) );
NOR3X1TS U42 ( .A(load_4_o), .B(load_0_o), .C(n27), .Y(n26) );
AOI31X1TS U43 ( .A0(state_reg[1]), .A1(n14), .A2(n28), .B0(n3), .Y(n25) );
NOR3BX1TS U44 ( .AN(Mult_shift_i), .B(n16), .C(n14), .Y(selector_b_o[1]) );
NAND3X1TS U45 ( .A(n13), .B(n8), .C(state_reg[2]), .Y(n16) );
NOR2BX1TS U46 ( .AN(round_flag_i), .B(n24), .Y(ctrl_select_c_o) );
INVX2TS U47 ( .A(rst), .Y(n12) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module RegisterAdd_W1_3 ( clk, rst, load, D, Q );
input [0:0] D;
output [0:0] Q;
input clk, rst, load;
wire n1, n3, n2;
DFFRX4TS Q_reg_0_ ( .D(n3), .CK(clk), .RN(n2), .Q(Q[0]), .QN(n1) );
INVX2TS U2 ( .A(rst), .Y(n2) );
OAI2BB2XLTS U3 ( .B0(n1), .B1(load), .A0N(load), .A1N(D[0]), .Y(n3) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module RegisterAdd_W1_2 ( clk, rst, load, D, Q );
input [0:0] D;
output [0:0] Q;
input clk, rst, load;
wire n2, n4, n5;
DFFRX2TS Q_reg_0_ ( .D(n4), .CK(clk), .RN(n2), .Q(Q[0]), .QN(n5) );
INVX2TS U2 ( .A(rst), .Y(n2) );
OAI2BB2XLTS U3 ( .B0(n5), .B1(load), .A0N(load), .A1N(D[0]), .Y(n4) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module RegisterAdd_W2 ( clk, rst, load, D, Q );
input [1:0] D;
output [1:0] Q;
input clk, rst, load;
wire n1, n2, n3, n5, n4;
DFFRX4TS Q_reg_1_ ( .D(n5), .CK(clk), .RN(n4), .Q(Q[1]), .QN(n2) );
DFFRX4TS Q_reg_0_ ( .D(n3), .CK(clk), .RN(n4), .Q(Q[0]), .QN(n1) );
INVX2TS U2 ( .A(rst), .Y(n4) );
OAI2BB2XLTS U3 ( .B0(n1), .B1(load), .A0N(load), .A1N(D[0]), .Y(n3) );
OAI2BB2XLTS U4 ( .B0(n2), .B1(load), .A0N(D[1]), .A1N(load), .Y(n5) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module RegisterMult_W32_1 ( clk, rst, load, D, Q );
input [31:0] D;
output [31:0] Q;
input clk, rst, load;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58,
n59, n60, n61, n62, n63, n65, n64, n66, n67, n68, n69, n70, n71, n72,
n73, n74, n75, n76;
DFFRX2TS Q_reg_11_ ( .D(n44), .CK(clk), .RN(n66), .Q(Q[11]), .QN(n12) );
DFFRX2TS Q_reg_10_ ( .D(n43), .CK(clk), .RN(n66), .Q(Q[10]), .QN(n11) );
DFFRX2TS Q_reg_9_ ( .D(n42), .CK(clk), .RN(n64), .Q(Q[9]), .QN(n10) );
DFFRX2TS Q_reg_7_ ( .D(n40), .CK(clk), .RN(n64), .Q(Q[7]), .QN(n8) );
DFFRX2TS Q_reg_6_ ( .D(n39), .CK(clk), .RN(n64), .Q(Q[6]), .QN(n7) );
DFFRX2TS Q_reg_4_ ( .D(n37), .CK(clk), .RN(n64), .Q(Q[4]), .QN(n5) );
DFFRX2TS Q_reg_0_ ( .D(n33), .CK(clk), .RN(n64), .Q(Q[0]), .QN(n1) );
DFFRX2TS Q_reg_31_ ( .D(n65), .CK(clk), .RN(n76), .Q(Q[31]), .QN(n32) );
DFFRX2TS Q_reg_5_ ( .D(n38), .CK(clk), .RN(n64), .Q(Q[5]), .QN(n6) );
DFFRX2TS Q_reg_22_ ( .D(n55), .CK(clk), .RN(n67), .Q(Q[22]), .QN(n23) );
DFFRX2TS Q_reg_21_ ( .D(n54), .CK(clk), .RN(n67), .Q(Q[21]), .QN(n22) );
DFFRX2TS Q_reg_20_ ( .D(n53), .CK(clk), .RN(n67), .Q(Q[20]), .QN(n21) );
DFFRX2TS Q_reg_19_ ( .D(n52), .CK(clk), .RN(n66), .Q(Q[19]), .QN(n20) );
DFFRX2TS Q_reg_18_ ( .D(n51), .CK(clk), .RN(n66), .Q(Q[18]), .QN(n19) );
DFFRX2TS Q_reg_17_ ( .D(n50), .CK(clk), .RN(n66), .Q(Q[17]), .QN(n18) );
DFFRX2TS Q_reg_16_ ( .D(n49), .CK(clk), .RN(n66), .Q(Q[16]), .QN(n17) );
DFFRX2TS Q_reg_15_ ( .D(n48), .CK(clk), .RN(n66), .Q(Q[15]), .QN(n16) );
DFFRX2TS Q_reg_14_ ( .D(n47), .CK(clk), .RN(n66), .Q(Q[14]), .QN(n15) );
DFFRX2TS Q_reg_13_ ( .D(n46), .CK(clk), .RN(n66), .Q(Q[13]), .QN(n14) );
DFFRX2TS Q_reg_12_ ( .D(n45), .CK(clk), .RN(n66), .Q(Q[12]), .QN(n13) );
DFFRX2TS Q_reg_8_ ( .D(n41), .CK(clk), .RN(n64), .Q(Q[8]), .QN(n9) );
DFFRX2TS Q_reg_3_ ( .D(n36), .CK(clk), .RN(n64), .Q(Q[3]), .QN(n4) );
DFFRX2TS Q_reg_2_ ( .D(n35), .CK(clk), .RN(n64), .Q(Q[2]), .QN(n3) );
DFFRX2TS Q_reg_1_ ( .D(n34), .CK(clk), .RN(n64), .Q(Q[1]), .QN(n2) );
DFFRX2TS Q_reg_30_ ( .D(n63), .CK(clk), .RN(n76), .Q(Q[30]), .QN(n31) );
DFFRX2TS Q_reg_29_ ( .D(n62), .CK(clk), .RN(n67), .Q(Q[29]), .QN(n30) );
DFFRX2TS Q_reg_27_ ( .D(n60), .CK(clk), .RN(n67), .Q(Q[27]), .QN(n28) );
DFFRX2TS Q_reg_26_ ( .D(n59), .CK(clk), .RN(n67), .Q(Q[26]), .QN(n27) );
DFFRX2TS Q_reg_28_ ( .D(n61), .CK(clk), .RN(n67), .Q(Q[28]), .QN(n29) );
DFFRX2TS Q_reg_25_ ( .D(n58), .CK(clk), .RN(n67), .Q(Q[25]), .QN(n26) );
DFFRX2TS Q_reg_24_ ( .D(n57), .CK(clk), .RN(n67), .Q(Q[24]), .QN(n25) );
DFFRX2TS Q_reg_23_ ( .D(n56), .CK(clk), .RN(n67), .Q(Q[23]), .QN(n24) );
BUFX3TS U2 ( .A(n75), .Y(n70) );
BUFX3TS U3 ( .A(n75), .Y(n71) );
BUFX3TS U4 ( .A(n74), .Y(n72) );
CLKBUFX2TS U5 ( .A(n74), .Y(n73) );
BUFX3TS U6 ( .A(n76), .Y(n64) );
BUFX3TS U7 ( .A(n76), .Y(n66) );
BUFX3TS U8 ( .A(n76), .Y(n67) );
CLKBUFX2TS U9 ( .A(n68), .Y(n75) );
CLKBUFX2TS U10 ( .A(n68), .Y(n74) );
BUFX3TS U11 ( .A(n74), .Y(n69) );
INVX2TS U12 ( .A(rst), .Y(n76) );
CLKBUFX2TS U13 ( .A(load), .Y(n68) );
OAI2BB2XLTS U14 ( .B0(n1), .B1(n70), .A0N(n73), .A1N(D[0]), .Y(n33) );
OAI2BB2XLTS U15 ( .B0(n3), .B1(n70), .A0N(D[2]), .A1N(n72), .Y(n35) );
OAI2BB2XLTS U16 ( .B0(n2), .B1(n75), .A0N(D[1]), .A1N(n73), .Y(n34) );
OAI2BB2XLTS U17 ( .B0(n4), .B1(n75), .A0N(D[3]), .A1N(n72), .Y(n36) );
OAI2BB2XLTS U18 ( .B0(n5), .B1(n75), .A0N(D[4]), .A1N(n72), .Y(n37) );
OAI2BB2XLTS U19 ( .B0(n6), .B1(n68), .A0N(D[5]), .A1N(n71), .Y(n38) );
OAI2BB2XLTS U20 ( .B0(n7), .B1(load), .A0N(D[6]), .A1N(n71), .Y(n39) );
OAI2BB2XLTS U21 ( .B0(n8), .B1(n68), .A0N(D[7]), .A1N(n71), .Y(n40) );
OAI2BB2XLTS U22 ( .B0(n9), .B1(n74), .A0N(D[8]), .A1N(n70), .Y(n41) );
OAI2BB2XLTS U23 ( .B0(n10), .B1(n74), .A0N(D[9]), .A1N(n71), .Y(n42) );
OAI2BB2XLTS U24 ( .B0(n11), .B1(n74), .A0N(D[10]), .A1N(n70), .Y(n43) );
OAI2BB2XLTS U25 ( .B0(n12), .B1(n73), .A0N(D[11]), .A1N(n70), .Y(n44) );
OAI2BB2XLTS U26 ( .B0(n13), .B1(n75), .A0N(D[12]), .A1N(n70), .Y(n45) );
OAI2BB2XLTS U27 ( .B0(n14), .B1(n73), .A0N(D[13]), .A1N(n70), .Y(n46) );
OAI2BB2XLTS U28 ( .B0(n15), .B1(n75), .A0N(D[14]), .A1N(n70), .Y(n47) );
OAI2BB2XLTS U29 ( .B0(n16), .B1(n74), .A0N(D[15]), .A1N(n71), .Y(n48) );
OAI2BB2XLTS U30 ( .B0(n17), .B1(load), .A0N(D[16]), .A1N(n70), .Y(n49) );
OAI2BB2XLTS U31 ( .B0(n18), .B1(load), .A0N(D[17]), .A1N(n70), .Y(n50) );
OAI2BB2XLTS U32 ( .B0(n19), .B1(load), .A0N(D[18]), .A1N(n71), .Y(n51) );
OAI2BB2XLTS U33 ( .B0(n20), .B1(n68), .A0N(D[19]), .A1N(n71), .Y(n52) );
OAI2BB2XLTS U34 ( .B0(n21), .B1(n68), .A0N(D[20]), .A1N(n71), .Y(n53) );
OAI2BB2XLTS U35 ( .B0(n22), .B1(n69), .A0N(D[21]), .A1N(n72), .Y(n54) );
OAI2BB2XLTS U36 ( .B0(n23), .B1(n69), .A0N(D[22]), .A1N(n71), .Y(n55) );
OAI2BB2XLTS U37 ( .B0(n24), .B1(n69), .A0N(D[23]), .A1N(n71), .Y(n56) );
OAI2BB2XLTS U38 ( .B0(n25), .B1(n69), .A0N(D[24]), .A1N(n72), .Y(n57) );
OAI2BB2XLTS U39 ( .B0(n26), .B1(n69), .A0N(D[25]), .A1N(n72), .Y(n58) );
OAI2BB2XLTS U40 ( .B0(n27), .B1(n69), .A0N(D[26]), .A1N(n72), .Y(n59) );
OAI2BB2XLTS U41 ( .B0(n28), .B1(n69), .A0N(D[27]), .A1N(n72), .Y(n60) );
OAI2BB2XLTS U42 ( .B0(n29), .B1(n69), .A0N(D[28]), .A1N(n72), .Y(n61) );
OAI2BB2XLTS U43 ( .B0(n30), .B1(n69), .A0N(D[29]), .A1N(n72), .Y(n62) );
OAI2BB2XLTS U44 ( .B0(n31), .B1(n69), .A0N(D[30]), .A1N(n73), .Y(n63) );
OAI2BB2XLTS U45 ( .B0(n32), .B1(n68), .A0N(D[31]), .A1N(n73), .Y(n65) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module RegisterMult_W32_0 ( clk, rst, load, D, Q );
input [31:0] D;
output [31:0] Q;
input clk, rst, load;
wire n64, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78,
n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92,
n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116,
n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127,
n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138,
n139, n140, n141;
DFFRX2TS Q_reg_31_ ( .D(n78), .CK(clk), .RN(n77), .Q(Q[31]), .QN(n110) );
DFFRX2TS Q_reg_11_ ( .D(n98), .CK(clk), .RN(n66), .Q(Q[11]), .QN(n130) );
DFFRX2TS Q_reg_10_ ( .D(n99), .CK(clk), .RN(n66), .Q(Q[10]), .QN(n131) );
DFFRX2TS Q_reg_9_ ( .D(n100), .CK(clk), .RN(n64), .Q(Q[9]), .QN(n132) );
DFFRX2TS Q_reg_7_ ( .D(n102), .CK(clk), .RN(n64), .Q(Q[7]), .QN(n134) );
DFFRX2TS Q_reg_6_ ( .D(n103), .CK(clk), .RN(n64), .Q(Q[6]), .QN(n135) );
DFFRX2TS Q_reg_5_ ( .D(n104), .CK(clk), .RN(n64), .Q(Q[5]), .QN(n136) );
DFFRX2TS Q_reg_4_ ( .D(n105), .CK(clk), .RN(n64), .Q(Q[4]), .QN(n137) );
DFFRX2TS Q_reg_0_ ( .D(n109), .CK(clk), .RN(n64), .Q(Q[0]), .QN(n141) );
DFFRX2TS Q_reg_22_ ( .D(n87), .CK(clk), .RN(n67), .Q(Q[22]), .QN(n119) );
DFFRX2TS Q_reg_21_ ( .D(n88), .CK(clk), .RN(n67), .Q(Q[21]), .QN(n120) );
DFFRX2TS Q_reg_20_ ( .D(n89), .CK(clk), .RN(n67), .Q(Q[20]), .QN(n121) );
DFFRX2TS Q_reg_19_ ( .D(n90), .CK(clk), .RN(n66), .Q(Q[19]), .QN(n122) );
DFFRX2TS Q_reg_18_ ( .D(n91), .CK(clk), .RN(n66), .Q(Q[18]), .QN(n123) );
DFFRX2TS Q_reg_17_ ( .D(n92), .CK(clk), .RN(n66), .Q(Q[17]), .QN(n124) );
DFFRX2TS Q_reg_16_ ( .D(n93), .CK(clk), .RN(n66), .Q(Q[16]), .QN(n125) );
DFFRX2TS Q_reg_15_ ( .D(n94), .CK(clk), .RN(n66), .Q(Q[15]), .QN(n126) );
DFFRX2TS Q_reg_14_ ( .D(n95), .CK(clk), .RN(n66), .Q(Q[14]), .QN(n127) );
DFFRX2TS Q_reg_13_ ( .D(n96), .CK(clk), .RN(n66), .Q(Q[13]), .QN(n128) );
DFFRX2TS Q_reg_12_ ( .D(n97), .CK(clk), .RN(n66), .Q(Q[12]), .QN(n129) );
DFFRX2TS Q_reg_8_ ( .D(n101), .CK(clk), .RN(n64), .Q(Q[8]), .QN(n133) );
DFFRX2TS Q_reg_3_ ( .D(n106), .CK(clk), .RN(n64), .Q(Q[3]), .QN(n138) );
DFFRX2TS Q_reg_2_ ( .D(n107), .CK(clk), .RN(n64), .Q(Q[2]), .QN(n139) );
DFFRX2TS Q_reg_1_ ( .D(n108), .CK(clk), .RN(n64), .Q(Q[1]), .QN(n140) );
DFFRX2TS Q_reg_30_ ( .D(n79), .CK(clk), .RN(n77), .Q(Q[30]), .QN(n111) );
DFFRX2TS Q_reg_29_ ( .D(n80), .CK(clk), .RN(n67), .Q(Q[29]), .QN(n112) );
DFFRX2TS Q_reg_28_ ( .D(n81), .CK(clk), .RN(n67), .Q(Q[28]), .QN(n113) );
DFFRX2TS Q_reg_27_ ( .D(n82), .CK(clk), .RN(n67), .Q(Q[27]), .QN(n114) );
DFFRX2TS Q_reg_26_ ( .D(n83), .CK(clk), .RN(n67), .Q(Q[26]), .QN(n115) );
DFFRX2TS Q_reg_24_ ( .D(n85), .CK(clk), .RN(n67), .Q(Q[24]), .QN(n117) );
DFFRX2TS Q_reg_23_ ( .D(n86), .CK(clk), .RN(n67), .Q(Q[23]), .QN(n118) );
DFFRX2TS Q_reg_25_ ( .D(n84), .CK(clk), .RN(n67), .Q(Q[25]), .QN(n116) );
BUFX3TS U2 ( .A(n75), .Y(n70) );
BUFX3TS U3 ( .A(n75), .Y(n71) );
BUFX3TS U4 ( .A(n74), .Y(n72) );
CLKBUFX2TS U5 ( .A(n74), .Y(n73) );
BUFX3TS U6 ( .A(n77), .Y(n64) );
BUFX3TS U7 ( .A(n77), .Y(n66) );
BUFX3TS U8 ( .A(n77), .Y(n67) );
CLKBUFX2TS U9 ( .A(n68), .Y(n75) );
CLKBUFX2TS U10 ( .A(n68), .Y(n74) );
BUFX3TS U11 ( .A(n76), .Y(n69) );
CLKBUFX2TS U12 ( .A(load), .Y(n76) );
INVX2TS U13 ( .A(rst), .Y(n77) );
CLKBUFX2TS U14 ( .A(load), .Y(n68) );
OAI2BB2XLTS U15 ( .B0(n141), .B1(n71), .A0N(n73), .A1N(D[0]), .Y(n109) );
OAI2BB2XLTS U16 ( .B0(n139), .B1(n71), .A0N(D[2]), .A1N(n72), .Y(n107) );
OAI2BB2XLTS U17 ( .B0(n140), .B1(n75), .A0N(D[1]), .A1N(n73), .Y(n108) );
OAI2BB2XLTS U18 ( .B0(n138), .B1(n68), .A0N(D[3]), .A1N(n72), .Y(n106) );
OAI2BB2XLTS U19 ( .B0(n137), .B1(n68), .A0N(D[4]), .A1N(n72), .Y(n105) );
OAI2BB2XLTS U20 ( .B0(n136), .B1(n73), .A0N(D[5]), .A1N(n75), .Y(n104) );
OAI2BB2XLTS U21 ( .B0(n135), .B1(n68), .A0N(D[6]), .A1N(n76), .Y(n103) );
OAI2BB2XLTS U22 ( .B0(n134), .B1(n73), .A0N(D[7]), .A1N(n74), .Y(n102) );
OAI2BB2XLTS U23 ( .B0(n133), .B1(n68), .A0N(D[8]), .A1N(n71), .Y(n101) );
OAI2BB2XLTS U24 ( .B0(n132), .B1(n73), .A0N(D[9]), .A1N(n75), .Y(n100) );
OAI2BB2XLTS U25 ( .B0(n131), .B1(n74), .A0N(D[10]), .A1N(n71), .Y(n99) );
OAI2BB2XLTS U26 ( .B0(n130), .B1(n70), .A0N(D[11]), .A1N(n71), .Y(n98) );
OAI2BB2XLTS U27 ( .B0(n129), .B1(n70), .A0N(D[12]), .A1N(n71), .Y(n97) );
OAI2BB2XLTS U28 ( .B0(n128), .B1(n70), .A0N(D[13]), .A1N(n71), .Y(n96) );
OAI2BB2XLTS U29 ( .B0(n127), .B1(n70), .A0N(D[14]), .A1N(n71), .Y(n95) );
OAI2BB2XLTS U30 ( .B0(n126), .B1(n68), .A0N(D[15]), .A1N(n75), .Y(n94) );
OAI2BB2XLTS U31 ( .B0(n125), .B1(n70), .A0N(D[16]), .A1N(n71), .Y(n93) );
OAI2BB2XLTS U32 ( .B0(n124), .B1(n70), .A0N(D[17]), .A1N(n71), .Y(n92) );
OAI2BB2XLTS U33 ( .B0(n123), .B1(n70), .A0N(D[18]), .A1N(n76), .Y(n91) );
OAI2BB2XLTS U34 ( .B0(n122), .B1(n70), .A0N(D[19]), .A1N(n76), .Y(n90) );
OAI2BB2XLTS U35 ( .B0(n121), .B1(n70), .A0N(D[20]), .A1N(n76), .Y(n89) );
OAI2BB2XLTS U36 ( .B0(n120), .B1(n69), .A0N(D[21]), .A1N(n72), .Y(n88) );
OAI2BB2XLTS U37 ( .B0(n119), .B1(n69), .A0N(D[22]), .A1N(n76), .Y(n87) );
OAI2BB2XLTS U38 ( .B0(n118), .B1(n69), .A0N(D[23]), .A1N(n76), .Y(n86) );
OAI2BB2XLTS U39 ( .B0(n117), .B1(n69), .A0N(D[24]), .A1N(n72), .Y(n85) );
OAI2BB2XLTS U40 ( .B0(n116), .B1(n69), .A0N(D[25]), .A1N(n72), .Y(n84) );
OAI2BB2XLTS U41 ( .B0(n115), .B1(n69), .A0N(D[26]), .A1N(n72), .Y(n83) );
OAI2BB2XLTS U42 ( .B0(n114), .B1(n69), .A0N(D[27]), .A1N(n72), .Y(n82) );
OAI2BB2XLTS U43 ( .B0(n113), .B1(n69), .A0N(D[28]), .A1N(n72), .Y(n81) );
OAI2BB2XLTS U44 ( .B0(n112), .B1(n69), .A0N(D[29]), .A1N(n72), .Y(n80) );
OAI2BB2XLTS U45 ( .B0(n111), .B1(n69), .A0N(D[30]), .A1N(n73), .Y(n79) );
OAI2BB2XLTS U46 ( .B0(n110), .B1(n70), .A0N(D[31]), .A1N(n73), .Y(n78) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module First_Phase_M_W32 ( clk, rst, load, Data_MX, Data_MY, Op_MX, Op_MY );
input [31:0] Data_MX;
input [31:0] Data_MY;
output [31:0] Op_MX;
output [31:0] Op_MY;
input clk, rst, load;
wire n1;
RegisterMult_W32_1 XMRegister ( .clk(clk), .rst(rst), .load(n1), .D(Data_MX),
.Q(Op_MX) );
RegisterMult_W32_0 YMRegister ( .clk(clk), .rst(rst), .load(n1), .D(Data_MY),
.Q(Op_MY) );
CLKBUFX2TS U1 ( .A(load), .Y(n1) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module Comparator_Equal_S31_1 ( Data_A, Data_B, equal_sgn );
input [30:0] Data_A;
input [30:0] Data_B;
output equal_sgn;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40;
NAND4X1TS U1 ( .A(n21), .B(n22), .C(n23), .D(n24), .Y(n1) );
NOR4X1TS U2 ( .A(n37), .B(n38), .C(n39), .D(n40), .Y(n21) );
NOR4X1TS U3 ( .A(n33), .B(n34), .C(n35), .D(n36), .Y(n22) );
NOR4X1TS U4 ( .A(n25), .B(n26), .C(n27), .D(n28), .Y(n24) );
NOR4X1TS U5 ( .A(n17), .B(n18), .C(n19), .D(n20), .Y(n16) );
XOR2X1TS U6 ( .A(Data_B[1]), .B(Data_A[1]), .Y(n17) );
XOR2X1TS U7 ( .A(Data_B[2]), .B(Data_A[2]), .Y(n18) );
XOR2X1TS U8 ( .A(Data_B[3]), .B(Data_A[3]), .Y(n19) );
NOR4X1TS U9 ( .A(n29), .B(n30), .C(n31), .D(n32), .Y(n23) );
XOR2X1TS U10 ( .A(Data_B[18]), .B(Data_A[18]), .Y(n29) );
XOR2X1TS U11 ( .A(Data_B[17]), .B(Data_A[17]), .Y(n30) );
XOR2X1TS U12 ( .A(Data_B[16]), .B(Data_A[16]), .Y(n31) );
XNOR2X1TS U13 ( .A(Data_B[5]), .B(Data_A[5]), .Y(n8) );
XOR2X1TS U14 ( .A(Data_B[19]), .B(Data_A[19]), .Y(n28) );
XOR2X1TS U15 ( .A(Data_B[12]), .B(Data_A[12]), .Y(n36) );
XOR2X1TS U16 ( .A(Data_B[8]), .B(Data_A[8]), .Y(n40) );
XOR2X1TS U17 ( .A(Data_B[24]), .B(Data_A[24]), .Y(n20) );
XOR2X1TS U18 ( .A(Data_B[23]), .B(Data_A[23]), .Y(n32) );
XOR2X1TS U19 ( .A(Data_B[22]), .B(Data_A[22]), .Y(n33) );
XOR2X1TS U20 ( .A(Data_B[13]), .B(Data_A[13]), .Y(n37) );
XOR2X1TS U21 ( .A(Data_B[28]), .B(Data_A[28]), .Y(n25) );
XOR2X1TS U22 ( .A(Data_B[20]), .B(Data_A[20]), .Y(n35) );
XOR2X1TS U23 ( .A(Data_B[15]), .B(Data_A[15]), .Y(n39) );
XOR2X1TS U24 ( .A(Data_B[29]), .B(Data_A[29]), .Y(n27) );
XOR2X1TS U25 ( .A(Data_B[21]), .B(Data_A[21]), .Y(n34) );
XOR2X1TS U26 ( .A(Data_B[14]), .B(Data_A[14]), .Y(n38) );
XOR2X1TS U27 ( .A(Data_B[30]), .B(Data_A[30]), .Y(n26) );
NAND4X1TS U28 ( .A(n5), .B(n6), .C(n7), .D(n8), .Y(n4) );
XNOR2X1TS U29 ( .A(Data_B[0]), .B(Data_A[0]), .Y(n5) );
XNOR2X1TS U30 ( .A(Data_B[7]), .B(Data_A[7]), .Y(n6) );
XNOR2X1TS U31 ( .A(Data_B[6]), .B(Data_A[6]), .Y(n7) );
NAND4X1TS U32 ( .A(n13), .B(n14), .C(n15), .D(n16), .Y(n2) );
XNOR2X1TS U33 ( .A(Data_B[25]), .B(Data_A[25]), .Y(n13) );
XNOR2X1TS U34 ( .A(Data_B[27]), .B(Data_A[27]), .Y(n14) );
XNOR2X1TS U35 ( .A(Data_B[26]), .B(Data_A[26]), .Y(n15) );
NOR4X1TS U36 ( .A(n1), .B(n2), .C(n3), .D(n4), .Y(equal_sgn) );
XNOR2X1TS U37 ( .A(Data_B[9]), .B(Data_A[9]), .Y(n12) );
NAND4X1TS U38 ( .A(n9), .B(n10), .C(n11), .D(n12), .Y(n3) );
XNOR2X1TS U39 ( .A(Data_B[4]), .B(Data_A[4]), .Y(n9) );
XNOR2X1TS U40 ( .A(Data_B[11]), .B(Data_A[11]), .Y(n10) );
XNOR2X1TS U41 ( .A(Data_B[10]), .B(Data_A[10]), .Y(n11) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module Comparator_Equal_S31_0 ( Data_A, Data_B, equal_sgn );
input [30:0] Data_A;
input [30:0] Data_B;
output equal_sgn;
wire n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54,
n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68,
n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80;
NAND4X1TS U1 ( .A(n60), .B(n59), .C(n58), .D(n57), .Y(n80) );
NOR4X1TS U2 ( .A(n44), .B(n43), .C(n42), .D(n41), .Y(n60) );
NOR4X1TS U3 ( .A(n48), .B(n47), .C(n46), .D(n45), .Y(n59) );
NOR4X1TS U4 ( .A(n56), .B(n55), .C(n54), .D(n53), .Y(n57) );
NOR4X1TS U5 ( .A(n64), .B(n63), .C(n62), .D(n61), .Y(n65) );
XOR2X1TS U6 ( .A(Data_B[1]), .B(Data_A[1]), .Y(n64) );
XOR2X1TS U7 ( .A(Data_B[2]), .B(Data_A[2]), .Y(n63) );
XOR2X1TS U8 ( .A(Data_B[3]), .B(Data_A[3]), .Y(n62) );
NOR4X1TS U9 ( .A(n52), .B(n51), .C(n50), .D(n49), .Y(n58) );
XOR2X1TS U10 ( .A(Data_B[18]), .B(Data_A[18]), .Y(n52) );
XOR2X1TS U11 ( .A(Data_B[17]), .B(Data_A[17]), .Y(n51) );
XOR2X1TS U12 ( .A(Data_B[16]), .B(Data_A[16]), .Y(n50) );
XOR2X1TS U13 ( .A(Data_B[19]), .B(Data_A[19]), .Y(n53) );
XOR2X1TS U14 ( .A(Data_B[12]), .B(Data_A[12]), .Y(n45) );
XOR2X1TS U15 ( .A(Data_B[8]), .B(Data_A[8]), .Y(n41) );
XOR2X1TS U16 ( .A(Data_B[22]), .B(Data_A[22]), .Y(n48) );
XOR2X1TS U17 ( .A(Data_B[13]), .B(Data_A[13]), .Y(n44) );
XOR2X1TS U18 ( .A(Data_B[24]), .B(Data_A[24]), .Y(n61) );
XOR2X1TS U19 ( .A(Data_B[23]), .B(Data_A[23]), .Y(n49) );
XOR2X1TS U20 ( .A(Data_B[28]), .B(Data_A[28]), .Y(n56) );
XOR2X1TS U21 ( .A(Data_B[20]), .B(Data_A[20]), .Y(n46) );
XOR2X1TS U22 ( .A(Data_B[15]), .B(Data_A[15]), .Y(n42) );
XOR2X1TS U23 ( .A(Data_B[29]), .B(Data_A[29]), .Y(n54) );
XOR2X1TS U24 ( .A(Data_B[21]), .B(Data_A[21]), .Y(n47) );
XOR2X1TS U25 ( .A(Data_B[14]), .B(Data_A[14]), .Y(n43) );
XOR2X1TS U26 ( .A(Data_B[30]), .B(Data_A[30]), .Y(n55) );
NAND4X1TS U27 ( .A(n68), .B(n67), .C(n66), .D(n65), .Y(n79) );
XNOR2X1TS U28 ( .A(Data_B[25]), .B(Data_A[25]), .Y(n68) );
XNOR2X1TS U29 ( .A(Data_B[27]), .B(Data_A[27]), .Y(n67) );
XNOR2X1TS U30 ( .A(Data_B[26]), .B(Data_A[26]), .Y(n66) );
NOR4X1TS U31 ( .A(n80), .B(n79), .C(n78), .D(n77), .Y(equal_sgn) );
NAND4X1TS U32 ( .A(n76), .B(n75), .C(n74), .D(n73), .Y(n77) );
XNOR2X1TS U33 ( .A(Data_B[0]), .B(Data_A[0]), .Y(n76) );
XNOR2X1TS U34 ( .A(Data_B[7]), .B(Data_A[7]), .Y(n75) );
XNOR2X1TS U35 ( .A(Data_B[6]), .B(Data_A[6]), .Y(n74) );
NAND4X1TS U36 ( .A(n72), .B(n71), .C(n70), .D(n69), .Y(n78) );
XNOR2X1TS U37 ( .A(Data_B[4]), .B(Data_A[4]), .Y(n72) );
XNOR2X1TS U38 ( .A(Data_B[11]), .B(Data_A[11]), .Y(n71) );
XNOR2X1TS U39 ( .A(Data_B[10]), .B(Data_A[10]), .Y(n70) );
XNOR2X1TS U40 ( .A(Data_B[5]), .B(Data_A[5]), .Y(n73) );
XNOR2X1TS U41 ( .A(Data_B[9]), .B(Data_A[9]), .Y(n69) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module RegisterAdd_W1_1 ( clk, rst, load, D, Q );
input [0:0] D;
output [0:0] Q;
input clk, rst, load;
wire n2, n4, n5;
DFFRX2TS Q_reg_0_ ( .D(n4), .CK(clk), .RN(n2), .Q(Q[0]), .QN(n5) );
INVX2TS U2 ( .A(rst), .Y(n2) );
OAI2BB2XLTS U3 ( .B0(n5), .B1(load), .A0N(load), .A1N(D[0]), .Y(n4) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module Zero_InfMult_Unit_W32 ( clk, rst, load, Data_A, Data_B, zero_m_flag );
input [30:0] Data_A;
input [30:0] Data_B;
input clk, rst, load;
output zero_m_flag;
wire or_1, or_2, zero_reg;
Comparator_Equal_S31_1 Data_A_Comp ( .Data_A(Data_A), .Data_B({1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0}), .equal_sgn(or_1) );
Comparator_Equal_S31_0 Data_B_Comp ( .Data_A({1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0}), .Data_B(Data_B), .equal_sgn(or_2) );
RegisterAdd_W1_1 Zero_Info_Mult ( .clk(clk), .rst(rst), .load(load), .D(
zero_reg), .Q(zero_m_flag) );
OR2X2TS U2 ( .A(or_1), .B(or_2), .Y(zero_reg) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module Multiplexer_AC_W9 ( ctrl, D0, D1, S );
input [8:0] D0;
input [8:0] D1;
output [8:0] S;
input ctrl;
wire n1;
INVX4TS U1 ( .A(ctrl), .Y(n1) );
AO22XLTS U2 ( .A0(D1[1]), .A1(ctrl), .B0(D0[1]), .B1(n1), .Y(S[1]) );
AO22XLTS U3 ( .A0(D1[2]), .A1(ctrl), .B0(D0[2]), .B1(n1), .Y(S[2]) );
AO22XLTS U4 ( .A0(D1[3]), .A1(ctrl), .B0(D0[3]), .B1(n1), .Y(S[3]) );
AO22XLTS U5 ( .A0(D1[4]), .A1(ctrl), .B0(D0[4]), .B1(n1), .Y(S[4]) );
AO22XLTS U6 ( .A0(D1[5]), .A1(ctrl), .B0(D0[5]), .B1(n1), .Y(S[5]) );
AO22XLTS U7 ( .A0(D1[6]), .A1(ctrl), .B0(D0[6]), .B1(n1), .Y(S[6]) );
AO22XLTS U8 ( .A0(D1[7]), .A1(ctrl), .B0(D0[7]), .B1(n1), .Y(S[7]) );
AO22XLTS U9 ( .A0(ctrl), .A1(D1[8]), .B0(D0[8]), .B1(n1), .Y(S[8]) );
AO22X2TS U10 ( .A0(D1[0]), .A1(ctrl), .B0(D0[0]), .B1(n1), .Y(S[0]) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module Mux_3x1_W8 ( ctrl, D0, D1, D2, S );
input [1:0] ctrl;
input [7:0] D0;
input [7:0] D1;
input [7:0] D2;
output [7:0] S;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13;
NOR2BX4TS U18 ( .AN(ctrl[0]), .B(ctrl[1]), .Y(n4) );
NOR2BX4TS U19 ( .AN(ctrl[1]), .B(ctrl[0]), .Y(n3) );
AND2X2TS U2 ( .A(D1[2]), .B(n4), .Y(n13) );
AOI22X2TS U3 ( .A0(D2[0]), .A1(n3), .B0(D1[0]), .B1(n4), .Y(n11) );
OAI2BB1X1TS U4 ( .A0N(D0[2]), .A1N(n1), .B0(n9), .Y(S[2]) );
NOR2X1TS U5 ( .A(n12), .B(n13), .Y(n9) );
AOI22X1TS U6 ( .A0(D2[1]), .A1(n3), .B0(D1[1]), .B1(n4), .Y(n10) );
AND2X1TS U7 ( .A(D2[2]), .B(n3), .Y(n12) );
OAI2BB1X2TS U8 ( .A0N(D0[1]), .A1N(n1), .B0(n10), .Y(S[1]) );
OAI2BB1XLTS U9 ( .A0N(D0[4]), .A1N(n1), .B0(n7), .Y(S[4]) );
AOI22XLTS U10 ( .A0(D2[4]), .A1(n3), .B0(D1[4]), .B1(n4), .Y(n7) );
OAI2BB1XLTS U11 ( .A0N(D0[3]), .A1N(n1), .B0(n8), .Y(S[3]) );
AOI22XLTS U12 ( .A0(D2[3]), .A1(n3), .B0(D1[3]), .B1(n4), .Y(n8) );
OAI2BB1XLTS U13 ( .A0N(D0[5]), .A1N(n1), .B0(n6), .Y(S[5]) );
OAI2BB1XLTS U14 ( .A0N(D0[6]), .A1N(n1), .B0(n5), .Y(S[6]) );
OAI2BB1XLTS U15 ( .A0N(D0[7]), .A1N(n1), .B0(n2), .Y(S[7]) );
NOR2X4TS U16 ( .A(ctrl[0]), .B(ctrl[1]), .Y(n1) );
OAI2BB1X2TS U17 ( .A0N(D0[0]), .A1N(n1), .B0(n11), .Y(S[0]) );
AOI22XLTS U20 ( .A0(D2[5]), .A1(n3), .B0(D1[5]), .B1(n4), .Y(n6) );
AOI22XLTS U21 ( .A0(D2[6]), .A1(n3), .B0(D1[6]), .B1(n4), .Y(n5) );
AOI22XLTS U22 ( .A0(D2[7]), .A1(n3), .B0(D1[7]), .B1(n4), .Y(n2) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module add_sub_carry_out_W9_DW01_add_0 ( A, B, CI, SUM, CO );
input [9:0] A;
input [9:0] B;
output [9:0] SUM;
input CI;
output CO;
wire n1;
wire [8:2] carry;
CMPR32X2TS U1_8 ( .A(A[8]), .B(B[8]), .C(carry[8]), .CO(SUM[9]), .S(SUM[8])
);
CMPR32X2TS U1_4 ( .A(A[4]), .B(B[4]), .C(carry[4]), .CO(carry[5]), .S(SUM[4]) );
CMPR32X2TS U1_7 ( .A(A[7]), .B(B[7]), .C(carry[7]), .CO(carry[8]), .S(SUM[7]) );
CMPR32X2TS U1_6 ( .A(A[6]), .B(B[6]), .C(carry[6]), .CO(carry[7]), .S(SUM[6]) );
CMPR32X2TS U1_5 ( .A(A[5]), .B(B[5]), .C(carry[5]), .CO(carry[6]), .S(SUM[5]) );
CMPR32X2TS U1_3 ( .A(A[3]), .B(B[3]), .C(carry[3]), .CO(carry[4]), .S(SUM[3]) );
CMPR32X2TS U1_2 ( .A(A[2]), .B(B[2]), .C(carry[2]), .CO(carry[3]), .S(SUM[2]) );
ADDFHX2TS U1_1 ( .A(A[1]), .B(B[1]), .CI(n1), .CO(carry[2]), .S(SUM[1]) );
AND2X2TS U1 ( .A(B[0]), .B(A[0]), .Y(n1) );
XOR2XLTS U2 ( .A(B[0]), .B(A[0]), .Y(SUM[0]) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module add_sub_carry_out_W9_DW01_sub_0 ( A, B, CI, DIFF, CO );
input [9:0] A;
input [9:0] B;
output [9:0] DIFF;
input CI;
output CO;
wire n1, n3, n4, n5, n6, n7, n8, n9, n10, n11;
wire [9:1] carry;
CMPR32X2TS U2_8 ( .A(A[8]), .B(n11), .C(carry[8]), .CO(carry[9]), .S(DIFF[8]) );
CMPR32X2TS U2_6 ( .A(A[6]), .B(n4), .C(carry[6]), .CO(carry[7]), .S(DIFF[6])
);
CMPR32X2TS U2_5 ( .A(A[5]), .B(n5), .C(carry[5]), .CO(carry[6]), .S(DIFF[5])
);
CMPR32X2TS U2_4 ( .A(A[4]), .B(n6), .C(carry[4]), .CO(carry[5]), .S(DIFF[4])
);
CMPR32X2TS U2_3 ( .A(A[3]), .B(n7), .C(carry[3]), .CO(carry[4]), .S(DIFF[3])
);
CMPR32X2TS U2_2 ( .A(A[2]), .B(n8), .C(carry[2]), .CO(carry[3]), .S(DIFF[2])
);
ADDFHX2TS U2_7 ( .A(A[7]), .B(n3), .CI(carry[7]), .CO(carry[8]), .S(DIFF[7])
);
ADDFHX1TS U2_1 ( .A(A[1]), .B(n9), .CI(carry[1]), .CO(carry[2]), .S(DIFF[1])
);
NAND2X1TS U1 ( .A(B[0]), .B(n1), .Y(carry[1]) );
CLKINVX1TS U2 ( .A(A[0]), .Y(n1) );
XNOR2XLTS U3 ( .A(n10), .B(A[0]), .Y(DIFF[0]) );
INVX2TS U4 ( .A(B[0]), .Y(n10) );
INVX2TS U5 ( .A(B[1]), .Y(n9) );
INVX2TS U6 ( .A(B[2]), .Y(n8) );
INVX2TS U7 ( .A(B[3]), .Y(n7) );
INVX2TS U8 ( .A(B[4]), .Y(n6) );
INVX2TS U9 ( .A(B[5]), .Y(n5) );
INVX2TS U10 ( .A(B[6]), .Y(n4) );
INVX2TS U11 ( .A(B[7]), .Y(n3) );
INVX2TS U12 ( .A(B[8]), .Y(n11) );
INVX2TS U13 ( .A(carry[9]), .Y(DIFF[9]) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module add_sub_carry_out_W9 ( op_mode, Data_A, Data_B, Data_S );
input [8:0] Data_A;
input [8:0] Data_B;
output [9:0] Data_S;
input op_mode;
wire N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17,
N18, N19, N20, N21, N22, n1, n2, n3;
add_sub_carry_out_W9_DW01_add_0 add_36 ( .A({1'b0, Data_A[8:2], n1,
Data_A[0]}), .B({1'b0, Data_B}), .CI(1'b0), .SUM({N22, N21, N20, N19,
N18, N17, N16, N15, N14, N13}) );
add_sub_carry_out_W9_DW01_sub_0 sub_34 ( .A({1'b0, Data_A[8:2], n1,
Data_A[0]}), .B({1'b0, Data_B}), .CI(1'b0), .DIFF({N12, N11, N10, N9,
N8, N7, N6, N5, N4, N3}) );
BUFX3TS U3 ( .A(Data_A[1]), .Y(n1) );
AO22XLTS U4 ( .A0(N22), .A1(n3), .B0(n2), .B1(N12), .Y(Data_S[9]) );
AO22X2TS U5 ( .A0(N21), .A1(n3), .B0(N11), .B1(n2), .Y(Data_S[8]) );
INVX2TS U6 ( .A(op_mode), .Y(n3) );
BUFX3TS U7 ( .A(op_mode), .Y(n2) );
AO22X1TS U8 ( .A0(N6), .A1(n2), .B0(N16), .B1(n3), .Y(Data_S[3]) );
AO22X1TS U9 ( .A0(N9), .A1(n2), .B0(N19), .B1(n3), .Y(Data_S[6]) );
AO22X1TS U10 ( .A0(N20), .A1(n3), .B0(N10), .B1(n2), .Y(Data_S[7]) );
AO22X1TS U11 ( .A0(N7), .A1(n2), .B0(N17), .B1(n3), .Y(Data_S[4]) );
AO22X1TS U12 ( .A0(N5), .A1(n2), .B0(N15), .B1(n3), .Y(Data_S[2]) );
AO22X1TS U13 ( .A0(N4), .A1(n2), .B0(N14), .B1(n3), .Y(Data_S[1]) );
AO22X1TS U14 ( .A0(N8), .A1(n2), .B0(N18), .B1(n3), .Y(Data_S[5]) );
AO22X1TS U15 ( .A0(N3), .A1(n2), .B0(N13), .B1(n3), .Y(Data_S[0]) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module RegisterMult_W9 ( clk, rst, load, D, Q );
input [8:0] D;
output [8:0] Q;
input clk, rst, load;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n19, n18, n20, n21;
DFFRX2TS Q_reg_7_ ( .D(n17), .CK(clk), .RN(n21), .Q(Q[7]), .QN(n8) );
DFFRX2TS Q_reg_6_ ( .D(n16), .CK(clk), .RN(n21), .Q(Q[6]), .QN(n7) );
DFFRX2TS Q_reg_8_ ( .D(n19), .CK(clk), .RN(n21), .Q(Q[8]), .QN(n9) );
DFFRX2TS Q_reg_5_ ( .D(n15), .CK(clk), .RN(n21), .Q(Q[5]), .QN(n6) );
DFFRX2TS Q_reg_4_ ( .D(n14), .CK(clk), .RN(n21), .Q(Q[4]), .QN(n5) );
DFFRX2TS Q_reg_3_ ( .D(n13), .CK(clk), .RN(n21), .Q(Q[3]), .QN(n4) );
DFFRX2TS Q_reg_2_ ( .D(n12), .CK(clk), .RN(n21), .Q(Q[2]), .QN(n3) );
DFFRX2TS Q_reg_1_ ( .D(n11), .CK(clk), .RN(n21), .Q(Q[1]), .QN(n2) );
DFFRX2TS Q_reg_0_ ( .D(n10), .CK(clk), .RN(n21), .Q(Q[0]), .QN(n1) );
BUFX3TS U2 ( .A(n20), .Y(n18) );
BUFX3TS U3 ( .A(load), .Y(n20) );
INVX4TS U4 ( .A(rst), .Y(n21) );
OAI2BB2XLTS U5 ( .B0(n7), .B1(n20), .A0N(D[6]), .A1N(n18), .Y(n16) );
OAI2BB2XLTS U6 ( .B0(n8), .B1(n20), .A0N(D[7]), .A1N(n18), .Y(n17) );
OAI2BB2XLTS U7 ( .B0(n9), .B1(n20), .A0N(D[8]), .A1N(n18), .Y(n19) );
OAI2BB2XLTS U8 ( .B0(n4), .B1(n20), .A0N(D[3]), .A1N(n18), .Y(n13) );
OAI2BB2XLTS U9 ( .B0(n5), .B1(n20), .A0N(D[4]), .A1N(n18), .Y(n14) );
OAI2BB2XLTS U10 ( .B0(n6), .B1(n20), .A0N(D[5]), .A1N(n18), .Y(n15) );
OAI2BB2XLTS U11 ( .B0(n1), .B1(n20), .A0N(n18), .A1N(D[0]), .Y(n10) );
OAI2BB2XLTS U12 ( .B0(n2), .B1(n20), .A0N(D[1]), .A1N(n18), .Y(n11) );
OAI2BB2XLTS U13 ( .B0(n3), .B1(n20), .A0N(D[2]), .A1N(n18), .Y(n12) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module RegisterMult_W1_1 ( clk, rst, load, D, Q );
input [0:0] D;
output [0:0] Q;
input clk, rst, load;
wire n1, n3, n2;
DFFRX2TS Q_reg_0_ ( .D(n3), .CK(clk), .RN(n2), .Q(Q[0]), .QN(n1) );
INVX2TS U2 ( .A(rst), .Y(n2) );
OAI2BB2XLTS U3 ( .B0(n1), .B1(load), .A0N(load), .A1N(D[0]), .Y(n3) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module Comparator_Less_W9 ( Data_A, Data_B, less );
input [8:0] Data_A;
input [8:0] Data_B;
output less;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28;
CLKINVX4TS U1 ( .A(Data_A[8]), .Y(n28) );
OAI22X2TS U2 ( .A0(Data_B[8]), .A1(n28), .B0(Data_B[7]), .B1(n27), .Y(n18)
);
OAI222X1TS U3 ( .A0(Data_B[8]), .A1(n28), .B0(Data_B[8]), .B1(n14), .C0(n14),
.C1(n28), .Y(n15) );
OR3X1TS U4 ( .A(n18), .B(n17), .C(n16), .Y(n1) );
NAND2X1TS U5 ( .A(n1), .B(n15), .Y(less) );
CLKINVX2TS U6 ( .A(Data_A[6]), .Y(n26) );
CLKINVX2TS U7 ( .A(Data_A[7]), .Y(n27) );
INVX2TS U8 ( .A(Data_A[5]), .Y(n25) );
INVX2TS U9 ( .A(Data_A[3]), .Y(n24) );
INVX2TS U10 ( .A(n4), .Y(n23) );
INVX2TS U11 ( .A(Data_A[0]), .Y(n21) );
INVX2TS U12 ( .A(Data_A[1]), .Y(n22) );
INVX2TS U13 ( .A(Data_B[6]), .Y(n19) );
INVX2TS U14 ( .A(Data_B[4]), .Y(n20) );
NAND2BX1TS U15 ( .AN(Data_B[2]), .B(Data_A[2]), .Y(n4) );
AO22X1TS U16 ( .A0(n21), .A1(Data_B[0]), .B0(n22), .B1(Data_B[1]), .Y(n2) );
OAI21X1TS U17 ( .A0(Data_B[1]), .A1(n22), .B0(n2), .Y(n7) );
NOR2BX1TS U18 ( .AN(Data_B[2]), .B(Data_A[2]), .Y(n3) );
OAI22X1TS U19 ( .A0(n3), .A1(n24), .B0(Data_B[3]), .B1(n3), .Y(n6) );
OAI22X1TS U20 ( .A0(Data_B[3]), .A1(n24), .B0(Data_B[3]), .B1(n4), .Y(n5) );
AOI221X1TS U21 ( .A0(Data_A[3]), .A1(n23), .B0(n7), .B1(n6), .C0(n5), .Y(n10) );
NOR2X1TS U22 ( .A(n20), .B(Data_A[4]), .Y(n8) );
OA22X1TS U23 ( .A0(n8), .A1(Data_B[5]), .B0(n8), .B1(n25), .Y(n9) );
AOI211X1TS U24 ( .A0(Data_B[6]), .A1(n26), .B0(n10), .C0(n9), .Y(n17) );
NAND2X1TS U25 ( .A(Data_A[4]), .B(n20), .Y(n11) );
OAI222X1TS U26 ( .A0(Data_B[5]), .A1(n25), .B0(Data_B[5]), .B1(n11), .C0(n25), .C1(n11), .Y(n12) );
OAI22X1TS U27 ( .A0(Data_A[6]), .A1(n12), .B0(n19), .B1(n12), .Y(n13) );
AOI21X1TS U28 ( .A0(Data_B[6]), .A1(n26), .B0(n13), .Y(n16) );
NOR2BX1TS U29 ( .AN(Data_B[7]), .B(Data_A[7]), .Y(n14) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module RegisterMult_W1_0 ( clk, rst, load, D, Q );
input [0:0] D;
output [0:0] Q;
input clk, rst, load;
wire n1, n2, n4;
DFFRX2TS Q_reg_0_ ( .D(n4), .CK(clk), .RN(n2), .Q(Q[0]) );
INVX2TS U2 ( .A(load), .Y(n1) );
AO22X1TS U3 ( .A0(Q[0]), .A1(n1), .B0(load), .B1(D[0]), .Y(n4) );
INVX2TS U4 ( .A(rst), .Y(n2) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module Exp_Operation_m_EW8 ( clk, rst, load_a_i, load_b_i, load_c_i, Data_A_i,
Data_B_i, Add_Subt_i, Data_Result_o, Overflow_flag_o, Underflow_flag_o
);
input [8:0] Data_A_i;
input [8:0] Data_B_i;
output [8:0] Data_Result_o;
input clk, rst, load_a_i, load_b_i, load_c_i, Add_Subt_i;
output Overflow_flag_o, Underflow_flag_o;
wire Overflow_A, Overflow_flag_A, underflow_exp_reg;
wire [8:0] Data_S;
add_sub_carry_out_W9 exp_add_subt_m ( .op_mode(Add_Subt_i), .Data_A(Data_A_i), .Data_B(Data_B_i), .Data_S({Overflow_A, Data_S}) );
RegisterMult_W9 exp_result_m ( .clk(clk), .rst(rst), .load(load_c_i), .D(
Data_S), .Q(Data_Result_o) );
RegisterMult_W1_1 Oflow_A_m ( .clk(clk), .rst(rst), .load(load_b_i), .D(
Overflow_A), .Q(Overflow_flag_A) );
Comparator_Less_W9 Exp_unflow_Comparator_m ( .Data_A(Data_S), .Data_B({1'b0,
1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), .less(
underflow_exp_reg) );
RegisterMult_W1_0 Underflow_m ( .clk(clk), .rst(rst), .load(load_a_i), .D(
underflow_exp_reg), .Q(Underflow_flag_o) );
OR2X2TS U3 ( .A(Data_Result_o[8]), .B(Overflow_flag_A), .Y(Overflow_flag_o)
);
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module XOR_M ( Sgn_X, Sgn_Y, Sgn_Info );
input Sgn_X, Sgn_Y;
output Sgn_Info;
XOR2X1TS U1 ( .A(Sgn_Y), .B(Sgn_X), .Y(Sgn_Info) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module Multiplexer_AC_W24 ( ctrl, D0, D1, S );
input [23:0] D0;
input [23:0] D1;
output [23:0] S;
input ctrl;
wire n1, n2, n3, n4, n5, n6;
CLKBUFX2TS U1 ( .A(n5), .Y(n3) );
INVX2TS U2 ( .A(n3), .Y(n1) );
INVX2TS U3 ( .A(n3), .Y(n2) );
BUFX3TS U4 ( .A(n5), .Y(n4) );
CLKBUFX2TS U5 ( .A(n6), .Y(n5) );
AO22X1TS U6 ( .A0(D1[0]), .A1(ctrl), .B0(D0[0]), .B1(n3), .Y(S[0]) );
AO22X1TS U7 ( .A0(n1), .A1(D1[9]), .B0(D0[9]), .B1(n6), .Y(S[9]) );
AO22X1TS U8 ( .A0(D1[1]), .A1(n2), .B0(D0[1]), .B1(n6), .Y(S[1]) );
AO22X1TS U9 ( .A0(D1[2]), .A1(n1), .B0(D0[2]), .B1(n6), .Y(S[2]) );
AO22X1TS U10 ( .A0(D1[3]), .A1(n1), .B0(D0[3]), .B1(n6), .Y(S[3]) );
AO22X1TS U11 ( .A0(D1[4]), .A1(n1), .B0(D0[4]), .B1(n5), .Y(S[4]) );
AO22X1TS U12 ( .A0(D1[5]), .A1(n1), .B0(D0[5]), .B1(n5), .Y(S[5]) );
AO22X1TS U13 ( .A0(D1[6]), .A1(n1), .B0(D0[6]), .B1(n6), .Y(S[6]) );
AO22X1TS U14 ( .A0(D1[7]), .A1(n1), .B0(D0[7]), .B1(n6), .Y(S[7]) );
AO22X1TS U15 ( .A0(D1[8]), .A1(n1), .B0(D0[8]), .B1(n6), .Y(S[8]) );
AO22X1TS U16 ( .A0(D1[11]), .A1(ctrl), .B0(D0[11]), .B1(n4), .Y(S[11]) );
AO22X1TS U17 ( .A0(D1[12]), .A1(ctrl), .B0(D0[12]), .B1(n4), .Y(S[12]) );
AO22X1TS U18 ( .A0(D1[13]), .A1(n2), .B0(D0[13]), .B1(n4), .Y(S[13]) );
AO22X1TS U19 ( .A0(D1[14]), .A1(n2), .B0(D0[14]), .B1(n4), .Y(S[14]) );
AO22X1TS U20 ( .A0(D1[15]), .A1(n2), .B0(D0[15]), .B1(n4), .Y(S[15]) );
AO22X1TS U21 ( .A0(D1[16]), .A1(n2), .B0(D0[16]), .B1(n4), .Y(S[16]) );
AO22X1TS U22 ( .A0(D1[17]), .A1(n2), .B0(D0[17]), .B1(n4), .Y(S[17]) );
AO22X1TS U23 ( .A0(D1[18]), .A1(n2), .B0(D0[18]), .B1(n4), .Y(S[18]) );
AO22X1TS U24 ( .A0(D1[19]), .A1(n2), .B0(D0[19]), .B1(n4), .Y(S[19]) );
AO22X1TS U25 ( .A0(D1[20]), .A1(n2), .B0(D0[20]), .B1(n6), .Y(S[20]) );
AO22X1TS U26 ( .A0(D1[21]), .A1(n2), .B0(D0[21]), .B1(n6), .Y(S[21]) );
AO22X1TS U27 ( .A0(D1[22]), .A1(n1), .B0(D0[22]), .B1(n5), .Y(S[22]) );
AO22X1TS U28 ( .A0(D1[23]), .A1(n1), .B0(D0[23]), .B1(n5), .Y(S[23]) );
AO22X1TS U29 ( .A0(D1[10]), .A1(ctrl), .B0(D0[10]), .B1(n4), .Y(S[10]) );
INVX2TS U30 ( .A(ctrl), .Y(n6) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module shift_mux_array_SWR24_LEVEL0 ( Data_i, select_i, bit_shift_i, Data_o );
input [23:0] Data_i;
output [23:0] Data_o;
input select_i, bit_shift_i;
wire n1, n2, n3, n4, n5;
INVX2TS U1 ( .A(select_i), .Y(n1) );
INVX2TS U2 ( .A(select_i), .Y(n2) );
INVX2TS U3 ( .A(select_i), .Y(n3) );
BUFX3TS U4 ( .A(select_i), .Y(n4) );
BUFX3TS U5 ( .A(select_i), .Y(n5) );
AO22X1TS U6 ( .A0(select_i), .A1(Data_i[1]), .B0(Data_i[0]), .B1(n2), .Y(
Data_o[0]) );
AO22X1TS U7 ( .A0(n4), .A1(Data_i[2]), .B0(n2), .B1(Data_i[1]), .Y(Data_o[1]) );
AO22X1TS U8 ( .A0(n4), .A1(Data_i[3]), .B0(n3), .B1(Data_i[2]), .Y(Data_o[2]) );
AO22X1TS U9 ( .A0(n4), .A1(Data_i[6]), .B0(n2), .B1(Data_i[5]), .Y(Data_o[5]) );
AO22X1TS U10 ( .A0(n4), .A1(Data_i[4]), .B0(n2), .B1(Data_i[3]), .Y(
Data_o[3]) );
AO22X1TS U11 ( .A0(n4), .A1(Data_i[5]), .B0(n2), .B1(Data_i[4]), .Y(
Data_o[4]) );
AO22X1TS U12 ( .A0(n4), .A1(Data_i[7]), .B0(n3), .B1(Data_i[6]), .Y(
Data_o[6]) );
AO22X1TS U13 ( .A0(n4), .A1(Data_i[8]), .B0(n3), .B1(Data_i[7]), .Y(
Data_o[7]) );
AO22X1TS U14 ( .A0(n4), .A1(Data_i[9]), .B0(n3), .B1(Data_i[8]), .Y(
Data_o[8]) );
AO22X1TS U15 ( .A0(n1), .A1(Data_i[9]), .B0(Data_i[10]), .B1(n4), .Y(
Data_o[9]) );
AO22X1TS U16 ( .A0(n2), .A1(Data_i[10]), .B0(select_i), .B1(Data_i[11]), .Y(
Data_o[10]) );
AO22X1TS U17 ( .A0(n2), .A1(Data_i[11]), .B0(select_i), .B1(Data_i[12]), .Y(
Data_o[11]) );
AO22X1TS U18 ( .A0(n2), .A1(Data_i[12]), .B0(select_i), .B1(Data_i[13]), .Y(
Data_o[12]) );
AO22X1TS U19 ( .A0(n2), .A1(Data_i[13]), .B0(n5), .B1(Data_i[14]), .Y(
Data_o[13]) );
AO22X1TS U20 ( .A0(n2), .A1(Data_i[14]), .B0(n5), .B1(Data_i[15]), .Y(
Data_o[14]) );
AO22X1TS U21 ( .A0(n1), .A1(Data_i[15]), .B0(n5), .B1(Data_i[16]), .Y(
Data_o[15]) );
AO22X1TS U22 ( .A0(n1), .A1(Data_i[16]), .B0(n5), .B1(Data_i[17]), .Y(
Data_o[16]) );
AO22X1TS U23 ( .A0(n1), .A1(Data_i[17]), .B0(n5), .B1(Data_i[18]), .Y(
Data_o[17]) );
AO22X1TS U24 ( .A0(n1), .A1(Data_i[18]), .B0(n5), .B1(Data_i[19]), .Y(
Data_o[18]) );
AO22X1TS U25 ( .A0(n1), .A1(Data_i[19]), .B0(n5), .B1(Data_i[20]), .Y(
Data_o[19]) );
AO22X1TS U26 ( .A0(n1), .A1(Data_i[20]), .B0(n5), .B1(Data_i[21]), .Y(
Data_o[20]) );
AO22X1TS U27 ( .A0(n1), .A1(Data_i[21]), .B0(n5), .B1(Data_i[22]), .Y(
Data_o[21]) );
AO22X1TS U28 ( .A0(n1), .A1(Data_i[22]), .B0(n5), .B1(Data_i[23]), .Y(
Data_o[22]) );
AO22X1TS U29 ( .A0(n1), .A1(Data_i[23]), .B0(bit_shift_i), .B1(n4), .Y(
Data_o[23]) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module RegisterMult_W24 ( clk, rst, load, D, Q );
input [23:0] D;
output [23:0] Q;
input clk, rst, load;
wire n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n49, n48, n50, n51, n52, n53, n54, n55, n56, n57;
DFFRX2TS Q_reg_23_ ( .D(n49), .CK(clk), .RN(n57), .Q(Q[23]), .QN(n24) );
DFFRX2TS Q_reg_22_ ( .D(n47), .CK(clk), .RN(n57), .Q(Q[22]), .QN(n23) );
DFFRX2TS Q_reg_21_ ( .D(n46), .CK(clk), .RN(n57), .Q(Q[21]), .QN(n22) );
DFFRX2TS Q_reg_20_ ( .D(n45), .CK(clk), .RN(n57), .Q(Q[20]), .QN(n21) );
DFFRX2TS Q_reg_19_ ( .D(n44), .CK(clk), .RN(n51), .Q(Q[19]), .QN(n20) );
DFFRX2TS Q_reg_18_ ( .D(n43), .CK(clk), .RN(n51), .Q(Q[18]), .QN(n19) );
DFFRX2TS Q_reg_17_ ( .D(n42), .CK(clk), .RN(n51), .Q(Q[17]), .QN(n18) );
DFFRX2TS Q_reg_16_ ( .D(n41), .CK(clk), .RN(n51), .Q(Q[16]), .QN(n17) );
DFFRX2TS Q_reg_15_ ( .D(n40), .CK(clk), .RN(n51), .Q(Q[15]), .QN(n16) );
DFFRX2TS Q_reg_14_ ( .D(n39), .CK(clk), .RN(n51), .Q(Q[14]), .QN(n15) );
DFFRX2TS Q_reg_13_ ( .D(n38), .CK(clk), .RN(n51), .Q(Q[13]), .QN(n14) );
DFFRX2TS Q_reg_12_ ( .D(n37), .CK(clk), .RN(n51), .Q(Q[12]), .QN(n13) );
DFFRX2TS Q_reg_11_ ( .D(n36), .CK(clk), .RN(n51), .Q(Q[11]), .QN(n12) );
DFFRX2TS Q_reg_10_ ( .D(n35), .CK(clk), .RN(n51), .Q(Q[10]), .QN(n11) );
DFFRX4TS Q_reg_1_ ( .D(n26), .CK(clk), .RN(n50), .Q(Q[1]), .QN(n2) );
DFFRX2TS Q_reg_9_ ( .D(n34), .CK(clk), .RN(n50), .Q(Q[9]), .QN(n10) );
DFFRX2TS Q_reg_8_ ( .D(n33), .CK(clk), .RN(n50), .Q(Q[8]), .QN(n9) );
DFFRX2TS Q_reg_7_ ( .D(n32), .CK(clk), .RN(n50), .Q(Q[7]), .QN(n8) );
DFFRX2TS Q_reg_4_ ( .D(n29), .CK(clk), .RN(n50), .Q(Q[4]), .QN(n5) );
DFFRX2TS Q_reg_5_ ( .D(n30), .CK(clk), .RN(n50), .Q(Q[5]), .QN(n6) );
DFFRX4TS Q_reg_0_ ( .D(n25), .CK(clk), .RN(n50), .Q(Q[0]), .QN(n48) );
DFFRX2TS Q_reg_6_ ( .D(n31), .CK(clk), .RN(n50), .Q(Q[6]), .QN(n7) );
DFFRX2TS Q_reg_3_ ( .D(n28), .CK(clk), .RN(n50), .Q(Q[3]), .QN(n4) );
DFFRX2TS Q_reg_2_ ( .D(n27), .CK(clk), .RN(n50), .Q(Q[2]), .QN(n3) );
BUFX3TS U2 ( .A(n57), .Y(n50) );
BUFX3TS U3 ( .A(n57), .Y(n51) );
BUFX3TS U4 ( .A(n56), .Y(n53) );
BUFX3TS U5 ( .A(n56), .Y(n54) );
BUFX3TS U6 ( .A(n56), .Y(n55) );
INVX2TS U7 ( .A(rst), .Y(n57) );
BUFX3TS U8 ( .A(load), .Y(n52) );
CLKBUFX2TS U9 ( .A(load), .Y(n56) );
OAI2BB2XLTS U10 ( .B0(n48), .B1(n53), .A0N(n55), .A1N(D[0]), .Y(n25) );
OAI2BB2XLTS U11 ( .B0(n2), .B1(n53), .A0N(D[1]), .A1N(n55), .Y(n26) );
OAI2BB2XLTS U12 ( .B0(n3), .B1(n53), .A0N(D[2]), .A1N(n55), .Y(n27) );
OAI2BB2XLTS U13 ( .B0(n6), .B1(n53), .A0N(D[5]), .A1N(n54), .Y(n30) );
OAI2BB2XLTS U14 ( .B0(n4), .B1(load), .A0N(D[3]), .A1N(n55), .Y(n28) );
OAI2BB2XLTS U15 ( .B0(n5), .B1(n55), .A0N(D[4]), .A1N(n54), .Y(n29) );
OAI2BB2XLTS U16 ( .B0(n7), .B1(load), .A0N(D[6]), .A1N(n54), .Y(n31) );
OAI2BB2XLTS U17 ( .B0(n8), .B1(n55), .A0N(D[7]), .A1N(n54), .Y(n32) );
OAI2BB2XLTS U18 ( .B0(n9), .B1(n56), .A0N(D[8]), .A1N(n53), .Y(n33) );
OAI2BB2XLTS U19 ( .B0(n10), .B1(load), .A0N(D[9]), .A1N(n53), .Y(n34) );
OAI2BB2XLTS U20 ( .B0(n11), .B1(load), .A0N(D[10]), .A1N(n53), .Y(n35) );
OAI2BB2XLTS U21 ( .B0(n12), .B1(load), .A0N(D[11]), .A1N(n53), .Y(n36) );
OAI2BB2XLTS U22 ( .B0(n13), .B1(load), .A0N(D[12]), .A1N(n53), .Y(n37) );
OAI2BB2XLTS U23 ( .B0(n14), .B1(n52), .A0N(D[13]), .A1N(n53), .Y(n38) );
OAI2BB2XLTS U24 ( .B0(n15), .B1(n52), .A0N(D[14]), .A1N(n54), .Y(n39) );
OAI2BB2XLTS U25 ( .B0(n16), .B1(n52), .A0N(D[15]), .A1N(n54), .Y(n40) );
OAI2BB2XLTS U26 ( .B0(n17), .B1(n52), .A0N(D[16]), .A1N(n54), .Y(n41) );
OAI2BB2XLTS U27 ( .B0(n18), .B1(n52), .A0N(D[17]), .A1N(n54), .Y(n42) );
OAI2BB2XLTS U28 ( .B0(n19), .B1(n52), .A0N(D[18]), .A1N(n54), .Y(n43) );
OAI2BB2XLTS U29 ( .B0(n20), .B1(n52), .A0N(D[19]), .A1N(n54), .Y(n44) );
OAI2BB2XLTS U30 ( .B0(n21), .B1(n52), .A0N(D[20]), .A1N(n55), .Y(n45) );
OAI2BB2XLTS U31 ( .B0(n22), .B1(n52), .A0N(D[21]), .A1N(n55), .Y(n46) );
OAI2BB2XLTS U32 ( .B0(n23), .B1(n52), .A0N(D[22]), .A1N(n55), .Y(n47) );
OAI2BB2XLTS U33 ( .B0(n24), .B1(load), .A0N(D[23]), .A1N(n55), .Y(n49) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module Barrel_Shifter_M_SW24 ( clk, rst, load_i, Shift_Value_i, Shift_Data_i,
N_mant_o );
input [23:0] Shift_Data_i;
output [23:0] N_mant_o;
input clk, rst, load_i, Shift_Value_i;
wire [23:0] Data_Reg;
shift_mux_array_SWR24_LEVEL0 shift_mux_array ( .Data_i(Shift_Data_i),
.select_i(Shift_Value_i), .bit_shift_i(1'b1), .Data_o(Data_Reg) );
RegisterMult_W24 Output_Reg ( .clk(clk), .rst(rst), .load(load_i), .D(
Data_Reg), .Q(N_mant_o) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module OR_Module_W23 ( Sgf_Round_Part, round_ok );
input [22:0] Sgf_Round_Part;
output round_ok;
wire n1, n2, n3, n4, n5, n6, n7, n8;
NOR4BX1TS U1 ( .AN(n5), .B(Sgf_Round_Part[6]), .C(Sgf_Round_Part[4]), .D(
Sgf_Round_Part[5]), .Y(n4) );
NOR3X1TS U2 ( .A(Sgf_Round_Part[7]), .B(Sgf_Round_Part[9]), .C(
Sgf_Round_Part[8]), .Y(n5) );
NAND4X1TS U3 ( .A(n1), .B(n2), .C(n3), .D(n4), .Y(round_ok) );
NOR4BX1TS U4 ( .AN(n6), .B(Sgf_Round_Part[21]), .C(Sgf_Round_Part[1]), .D(
Sgf_Round_Part[20]), .Y(n3) );
NOR3X1TS U5 ( .A(Sgf_Round_Part[22]), .B(Sgf_Round_Part[3]), .C(
Sgf_Round_Part[2]), .Y(n6) );
NOR4BX1TS U6 ( .AN(n7), .B(Sgf_Round_Part[16]), .C(Sgf_Round_Part[14]), .D(
Sgf_Round_Part[15]), .Y(n2) );
NOR3X1TS U7 ( .A(Sgf_Round_Part[17]), .B(Sgf_Round_Part[19]), .C(
Sgf_Round_Part[18]), .Y(n7) );
NOR4BX1TS U8 ( .AN(n8), .B(Sgf_Round_Part[10]), .C(Sgf_Round_Part[0]), .D(
Sgf_Round_Part[11]), .Y(n1) );
NOR2X1TS U9 ( .A(Sgf_Round_Part[13]), .B(Sgf_Round_Part[12]), .Y(n8) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module Deco_Round_Mult ( round_mode, or_info, xor_info, ctrl );
input [1:0] round_mode;
input or_info, xor_info;
output ctrl;
wire n1, n2;
NOR3BX1TS U3 ( .AN(or_info), .B(n1), .C(n2), .Y(ctrl) );
XOR2X1TS U4 ( .A(xor_info), .B(round_mode[0]), .Y(n1) );
XNOR2X1TS U5 ( .A(round_mode[0]), .B(round_mode[1]), .Y(n2) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module Round_decoder_M_SW23 ( Round_Bits_i, Round_Mode_i, Sign_Result_i,
Round_Flag_o );
input [22:0] Round_Bits_i;
input [1:0] Round_Mode_i;
input Sign_Result_i;
output Round_Flag_o;
wire round_ok;
OR_Module_W23 OR_info_reg ( .Sgf_Round_Part(Round_Bits_i), .round_ok(
round_ok) );
Deco_Round_Mult Rounding_Deco ( .round_mode(Round_Mode_i), .or_info(round_ok), .xor_info(Sign_Result_i), .ctrl(Round_Flag_o) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module adder_W24_DW01_add_0 ( A, B, CI, SUM, CO );
input [24:0] A;
input [24:0] B;
output [24:0] SUM;
input CI;
output CO;
wire n1, n2, n3;
wire [23:2] carry;
ADDFHX2TS U1_20 ( .A(A[20]), .B(B[20]), .CI(carry[20]), .CO(carry[21]), .S(
SUM[20]) );
ADDFHX2TS U1_9 ( .A(A[9]), .B(B[9]), .CI(carry[9]), .CO(carry[10]), .S(
SUM[9]) );
ADDFHX2TS U1_15 ( .A(A[15]), .B(B[15]), .CI(carry[15]), .CO(carry[16]), .S(
SUM[15]) );
CMPR32X2TS U1_8 ( .A(A[8]), .B(B[8]), .C(carry[8]), .CO(carry[9]), .S(SUM[8]) );
ADDFHX2TS U1_23 ( .A(A[23]), .B(B[23]), .CI(carry[23]), .CO(SUM[24]), .S(
SUM[23]) );
ADDFHX4TS U1_1 ( .A(A[1]), .B(B[1]), .CI(n1), .CO(carry[2]), .S(SUM[1]) );
ADDFHX4TS U1_6 ( .A(A[6]), .B(B[6]), .CI(carry[6]), .CO(carry[7]), .S(SUM[6]) );
ADDFHX4TS U1_7 ( .A(A[7]), .B(B[7]), .CI(carry[7]), .CO(carry[8]), .S(SUM[7]) );
ADDFHX4TS U1_4 ( .A(A[4]), .B(B[4]), .CI(carry[4]), .CO(carry[5]), .S(SUM[4]) );
ADDFHX4TS U1_5 ( .A(A[5]), .B(B[5]), .CI(carry[5]), .CO(carry[6]), .S(SUM[5]) );
ADDFHX4TS U1_2 ( .A(A[2]), .B(B[2]), .CI(carry[2]), .CO(carry[3]), .S(SUM[2]) );
ADDFHX4TS U1_3 ( .A(A[3]), .B(B[3]), .CI(carry[3]), .CO(carry[4]), .S(SUM[3]) );
ADDFHX4TS U1_12 ( .A(A[12]), .B(B[12]), .CI(carry[12]), .CO(carry[13]), .S(
SUM[12]) );
ADDFHX4TS U1_10 ( .A(A[10]), .B(B[10]), .CI(carry[10]), .CO(carry[11]), .S(
SUM[10]) );
ADDFHX4TS U1_11 ( .A(A[11]), .B(B[11]), .CI(carry[11]), .CO(carry[12]), .S(
SUM[11]) );
ADDFHX4TS U1_21 ( .A(A[21]), .B(B[21]), .CI(carry[21]), .CO(carry[22]), .S(
SUM[21]) );
ADDFHX4TS U1_22 ( .A(A[22]), .B(B[22]), .CI(carry[22]), .CO(carry[23]), .S(
SUM[22]) );
ADDFHX4TS U1_16 ( .A(A[16]), .B(B[16]), .CI(carry[16]), .CO(carry[17]), .S(
SUM[16]) );
ADDFHX4TS U1_17 ( .A(A[17]), .B(B[17]), .CI(carry[17]), .CO(carry[18]), .S(
SUM[17]) );
ADDFHX4TS U1_18 ( .A(A[18]), .B(B[18]), .CI(carry[18]), .CO(carry[19]), .S(
SUM[18]) );
ADDFHX4TS U1_19 ( .A(A[19]), .B(B[19]), .CI(carry[19]), .CO(carry[20]), .S(
SUM[19]) );
ADDFHX2TS U1_13 ( .A(A[13]), .B(B[13]), .CI(carry[13]), .CO(carry[14]), .S(
SUM[13]) );
ADDFHX2TS U1_14 ( .A(A[14]), .B(B[14]), .CI(carry[14]), .CO(carry[15]), .S(
SUM[14]) );
CLKINVX8TS U1 ( .A(A[0]), .Y(n3) );
NOR2X4TS U2 ( .A(n2), .B(n3), .Y(n1) );
XOR2XLTS U3 ( .A(B[0]), .B(A[0]), .Y(SUM[0]) );
INVX2TS U4 ( .A(B[0]), .Y(n2) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module adder_W24 ( Data_A_i, Data_B_i, Data_S_o );
input [23:0] Data_A_i;
input [23:0] Data_B_i;
output [24:0] Data_S_o;
adder_W24_DW01_add_0 add_9 ( .A({1'b0, Data_A_i}), .B({1'b0, Data_B_i}),
.CI(1'b0), .SUM(Data_S_o) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module RegisterAdd_W24 ( clk, rst, load, D, Q );
input [23:0] D;
output [23:0] Q;
input clk, rst, load;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n49, n48, n50, n51, n52, n53, n54, n55, n56;
DFFRX2TS Q_reg_9_ ( .D(n34), .CK(clk), .RN(n48), .Q(Q[9]), .QN(n10) );
DFFRX2TS Q_reg_23_ ( .D(n49), .CK(clk), .RN(n56), .Q(Q[23]), .QN(n24) );
DFFRX2TS Q_reg_15_ ( .D(n40), .CK(clk), .RN(n50), .Q(Q[15]), .QN(n16) );
DFFRX2TS Q_reg_14_ ( .D(n39), .CK(clk), .RN(n50), .Q(Q[14]), .QN(n15) );
DFFRX2TS Q_reg_13_ ( .D(n38), .CK(clk), .RN(n50), .Q(Q[13]), .QN(n14) );
DFFRX2TS Q_reg_12_ ( .D(n37), .CK(clk), .RN(n50), .Q(Q[12]), .QN(n13) );
DFFRX2TS Q_reg_11_ ( .D(n36), .CK(clk), .RN(n50), .Q(Q[11]), .QN(n12) );
DFFRX2TS Q_reg_10_ ( .D(n35), .CK(clk), .RN(n50), .Q(Q[10]), .QN(n11) );
DFFRX2TS Q_reg_8_ ( .D(n33), .CK(clk), .RN(n48), .Q(Q[8]), .QN(n9) );
DFFRX2TS Q_reg_7_ ( .D(n32), .CK(clk), .RN(n48), .Q(Q[7]), .QN(n8) );
DFFRX2TS Q_reg_6_ ( .D(n31), .CK(clk), .RN(n48), .Q(Q[6]), .QN(n7) );
DFFRX2TS Q_reg_5_ ( .D(n30), .CK(clk), .RN(n48), .Q(Q[5]), .QN(n6) );
DFFRX2TS Q_reg_4_ ( .D(n29), .CK(clk), .RN(n48), .Q(Q[4]), .QN(n5) );
DFFRX2TS Q_reg_3_ ( .D(n28), .CK(clk), .RN(n48), .Q(Q[3]), .QN(n4) );
DFFRX2TS Q_reg_2_ ( .D(n27), .CK(clk), .RN(n48), .Q(Q[2]), .QN(n3) );
DFFRX2TS Q_reg_1_ ( .D(n26), .CK(clk), .RN(n48), .Q(Q[1]), .QN(n2) );
DFFRX2TS Q_reg_0_ ( .D(n25), .CK(clk), .RN(n48), .Q(Q[0]), .QN(n1) );
DFFRXLTS Q_reg_22_ ( .D(n47), .CK(clk), .RN(n56), .Q(Q[22]), .QN(n23) );
DFFRXLTS Q_reg_20_ ( .D(n45), .CK(clk), .RN(n56), .Q(Q[20]), .QN(n21) );
DFFRXLTS Q_reg_19_ ( .D(n44), .CK(clk), .RN(n50), .Q(Q[19]), .QN(n20) );
DFFRXLTS Q_reg_18_ ( .D(n43), .CK(clk), .RN(n50), .Q(Q[18]), .QN(n19) );
DFFRXLTS Q_reg_17_ ( .D(n42), .CK(clk), .RN(n50), .Q(Q[17]), .QN(n18) );
DFFRXLTS Q_reg_16_ ( .D(n41), .CK(clk), .RN(n50), .Q(Q[16]), .QN(n17) );
DFFRXLTS Q_reg_21_ ( .D(n46), .CK(clk), .RN(n56), .Q(Q[21]), .QN(n22) );
OAI2BB2X4TS U2 ( .B0(n24), .B1(n53), .A0N(D[23]), .A1N(n55), .Y(n49) );
OAI2BB2XLTS U3 ( .B0(n16), .B1(n52), .A0N(D[15]), .A1N(n54), .Y(n40) );
OAI2BB2XLTS U4 ( .B0(n22), .B1(n52), .A0N(D[21]), .A1N(n55), .Y(n46) );
BUFX3TS U5 ( .A(n51), .Y(n53) );
BUFX3TS U6 ( .A(n51), .Y(n54) );
BUFX3TS U7 ( .A(load), .Y(n55) );
BUFX3TS U8 ( .A(n51), .Y(n52) );
BUFX3TS U9 ( .A(n56), .Y(n48) );
BUFX3TS U10 ( .A(n56), .Y(n50) );
CLKBUFX2TS U11 ( .A(load), .Y(n51) );
INVX2TS U12 ( .A(rst), .Y(n56) );
OAI2BB2XLTS U13 ( .B0(n23), .B1(n52), .A0N(D[22]), .A1N(n55), .Y(n47) );
OAI2BB2XLTS U14 ( .B0(n20), .B1(n52), .A0N(D[19]), .A1N(n54), .Y(n44) );
OAI2BB2XLTS U15 ( .B0(n21), .B1(n52), .A0N(D[20]), .A1N(n55), .Y(n45) );
OAI2BB2XLTS U16 ( .B0(n17), .B1(n52), .A0N(D[16]), .A1N(n54), .Y(n41) );
OAI2BB2XLTS U17 ( .B0(n18), .B1(n52), .A0N(D[17]), .A1N(n54), .Y(n42) );
OAI2BB2XLTS U18 ( .B0(n19), .B1(n52), .A0N(D[18]), .A1N(n54), .Y(n43) );
OAI2BB2XLTS U19 ( .B0(n13), .B1(n53), .A0N(D[12]), .A1N(load), .Y(n37) );
OAI2BB2XLTS U20 ( .B0(n14), .B1(n52), .A0N(D[13]), .A1N(load), .Y(n38) );
OAI2BB2XLTS U21 ( .B0(n15), .B1(n52), .A0N(D[14]), .A1N(n54), .Y(n39) );
OAI2BB2XLTS U22 ( .B0(n10), .B1(n53), .A0N(D[9]), .A1N(load), .Y(n34) );
OAI2BB2XLTS U23 ( .B0(n11), .B1(n53), .A0N(D[10]), .A1N(load), .Y(n35) );
OAI2BB2XLTS U24 ( .B0(n12), .B1(n53), .A0N(D[11]), .A1N(n51), .Y(n36) );
OAI2BB2XLTS U25 ( .B0(n7), .B1(n53), .A0N(D[6]), .A1N(n54), .Y(n31) );
OAI2BB2XLTS U26 ( .B0(n8), .B1(n53), .A0N(D[7]), .A1N(n54), .Y(n32) );
OAI2BB2XLTS U27 ( .B0(n9), .B1(n53), .A0N(D[8]), .A1N(n51), .Y(n33) );
OAI2BB2XLTS U28 ( .B0(n1), .B1(n51), .A0N(n55), .A1N(D[0]), .Y(n25) );
OAI2BB2XLTS U29 ( .B0(n2), .B1(n55), .A0N(D[1]), .A1N(n55), .Y(n26) );
OAI2BB2XLTS U30 ( .B0(n3), .B1(n55), .A0N(D[2]), .A1N(n55), .Y(n27) );
OAI2BB2XLTS U31 ( .B0(n6), .B1(n51), .A0N(D[5]), .A1N(n54), .Y(n30) );
OAI2BB2XLTS U32 ( .B0(n4), .B1(n53), .A0N(D[3]), .A1N(n55), .Y(n28) );
OAI2BB2XLTS U33 ( .B0(n5), .B1(n53), .A0N(D[4]), .A1N(n54), .Y(n29) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module RegisterAdd_W1_0 ( clk, rst, load, D, Q );
input [0:0] D;
output [0:0] Q;
input clk, rst, load;
wire n2, n4, n5;
DFFRX1TS Q_reg_0_ ( .D(n4), .CK(clk), .RN(n2), .Q(Q[0]), .QN(n5) );
OAI2BB2X4TS U2 ( .B0(n5), .B1(load), .A0N(load), .A1N(D[0]), .Y(n4) );
INVX2TS U3 ( .A(rst), .Y(n2) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module Adder_Round_SW24 ( clk, rst, load_i, Data_A_i, Data_B_i, Data_Result_o,
FSM_C_o );
input [23:0] Data_A_i;
input [23:0] Data_B_i;
output [23:0] Data_Result_o;
input clk, rst, load_i;
output FSM_C_o;
wire [24:0] result_A_adder;
adder_W24 A_operation ( .Data_A_i(Data_A_i), .Data_B_i(Data_B_i), .Data_S_o(
result_A_adder) );
RegisterAdd_W24 Add_Subt_Result ( .clk(clk), .rst(rst), .load(load_i), .D(
result_A_adder[23:0]), .Q(Data_Result_o) );
RegisterAdd_W1_0 Add_overflow_Result ( .clk(clk), .rst(rst), .load(load_i),
.D(result_A_adder[24]), .Q(FSM_C_o) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module Mux_3x1_W1 ( ctrl, D0, D1, D2, S );
input [1:0] ctrl;
input [0:0] D0;
input [0:0] D1;
input [0:0] D2;
output [0:0] S;
wire n3, n4, n1, n2;
OAI22X1TS U2 ( .A0(ctrl[1]), .A1(n3), .B0(n2), .B1(n4), .Y(S[0]) );
INVX2TS U3 ( .A(ctrl[1]), .Y(n2) );
NAND2X1TS U4 ( .A(D2[0]), .B(n1), .Y(n4) );
AOI22X1TS U5 ( .A0(D0[0]), .A1(n1), .B0(ctrl[0]), .B1(D1[0]), .Y(n3) );
INVX2TS U6 ( .A(ctrl[0]), .Y(n1) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module Multiplexer_AC_W8 ( ctrl, D0, D1, S );
input [7:0] D0;
input [7:0] D1;
output [7:0] S;
input ctrl;
wire n1, n2;
INVX2TS U1 ( .A(n2), .Y(n1) );
INVX2TS U2 ( .A(ctrl), .Y(n2) );
AO22X1TS U3 ( .A0(D1[0]), .A1(n1), .B0(D0[0]), .B1(n2), .Y(S[0]) );
AO22X1TS U4 ( .A0(D1[1]), .A1(n1), .B0(D0[1]), .B1(n2), .Y(S[1]) );
AO22X1TS U5 ( .A0(D1[2]), .A1(n1), .B0(D0[2]), .B1(n2), .Y(S[2]) );
AO22X1TS U6 ( .A0(D1[3]), .A1(n1), .B0(D0[3]), .B1(n2), .Y(S[3]) );
AO22X1TS U7 ( .A0(D1[4]), .A1(n1), .B0(D0[4]), .B1(n2), .Y(S[4]) );
AO22X1TS U8 ( .A0(D1[5]), .A1(n1), .B0(D0[5]), .B1(n2), .Y(S[5]) );
AO22X1TS U9 ( .A0(D1[6]), .A1(n1), .B0(D0[6]), .B1(n2), .Y(S[6]) );
AO22X1TS U10 ( .A0(n1), .A1(D1[7]), .B0(D0[7]), .B1(n2), .Y(S[7]) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module Multiplexer_AC_W23 ( ctrl, D0, D1, S );
input [22:0] D0;
input [22:0] D1;
output [22:0] S;
input ctrl;
wire n1, n2, n3, n4, n5;
AO22XLTS U1 ( .A0(D1[0]), .A1(ctrl), .B0(D0[0]), .B1(n4), .Y(S[0]) );
AO22XLTS U2 ( .A0(D1[1]), .A1(n2), .B0(D0[1]), .B1(n3), .Y(S[1]) );
AO22XLTS U3 ( .A0(D1[2]), .A1(n1), .B0(D0[2]), .B1(n3), .Y(S[2]) );
AO22XLTS U4 ( .A0(D1[3]), .A1(n1), .B0(D0[3]), .B1(n3), .Y(S[3]) );
AO22XLTS U5 ( .A0(D1[4]), .A1(n1), .B0(D0[4]), .B1(n3), .Y(S[4]) );
AO22XLTS U6 ( .A0(D1[5]), .A1(n1), .B0(D0[5]), .B1(n3), .Y(S[5]) );
AO22XLTS U7 ( .A0(D1[6]), .A1(n1), .B0(D0[6]), .B1(n3), .Y(S[6]) );
AO22XLTS U8 ( .A0(D1[7]), .A1(n1), .B0(D0[7]), .B1(n3), .Y(S[7]) );
AO22XLTS U9 ( .A0(D1[8]), .A1(n1), .B0(D0[8]), .B1(n4), .Y(S[8]) );
AO22XLTS U10 ( .A0(n1), .A1(D1[9]), .B0(D0[9]), .B1(n4), .Y(S[9]) );
AO22XLTS U11 ( .A0(D1[10]), .A1(ctrl), .B0(D0[10]), .B1(n4), .Y(S[10]) );
INVX2TS U12 ( .A(n4), .Y(n1) );
INVX2TS U13 ( .A(n4), .Y(n2) );
BUFX3TS U14 ( .A(n5), .Y(n3) );
CLKBUFX2TS U15 ( .A(n5), .Y(n4) );
INVX2TS U16 ( .A(ctrl), .Y(n5) );
AO22X1TS U17 ( .A0(D1[11]), .A1(ctrl), .B0(D0[11]), .B1(n4), .Y(S[11]) );
AO22X1TS U18 ( .A0(D1[12]), .A1(n2), .B0(D0[12]), .B1(n5), .Y(S[12]) );
AO22X1TS U19 ( .A0(D1[13]), .A1(n2), .B0(D0[13]), .B1(n5), .Y(S[13]) );
AO22X1TS U20 ( .A0(D1[14]), .A1(n2), .B0(D0[14]), .B1(n5), .Y(S[14]) );
AO22X1TS U21 ( .A0(D1[15]), .A1(n2), .B0(D0[15]), .B1(n5), .Y(S[15]) );
AO22X1TS U22 ( .A0(D1[16]), .A1(n2), .B0(D0[16]), .B1(n5), .Y(S[16]) );
AO22X1TS U23 ( .A0(D1[17]), .A1(n2), .B0(D0[17]), .B1(n5), .Y(S[17]) );
AO22X1TS U24 ( .A0(D1[18]), .A1(n2), .B0(D0[18]), .B1(n5), .Y(S[18]) );
AO22X1TS U25 ( .A0(D1[19]), .A1(n2), .B0(D0[19]), .B1(n5), .Y(S[19]) );
AO22X1TS U26 ( .A0(D1[20]), .A1(n2), .B0(D0[20]), .B1(n3), .Y(S[20]) );
AO22X1TS U27 ( .A0(D1[21]), .A1(n1), .B0(D0[21]), .B1(n3), .Y(S[21]) );
AO22X1TS U28 ( .A0(D1[22]), .A1(n1), .B0(D0[22]), .B1(n3), .Y(S[22]) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module RegisterAdd_W32 ( clk, rst, load, D, Q );
input [31:0] D;
output [31:0] Q;
input clk, rst, load;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58,
n59, n60, n61, n62, n63, n65, n64, n66, n67, n68, n69, n70, n71, n72,
n73, n74, n75, n76;
DFFRX2TS Q_reg_31_ ( .D(n65), .CK(clk), .RN(n76), .Q(Q[31]), .QN(n32) );
DFFRX2TS Q_reg_30_ ( .D(n63), .CK(clk), .RN(n76), .Q(Q[30]), .QN(n31) );
DFFRX2TS Q_reg_29_ ( .D(n62), .CK(clk), .RN(n67), .Q(Q[29]), .QN(n30) );
DFFRX2TS Q_reg_28_ ( .D(n61), .CK(clk), .RN(n67), .Q(Q[28]), .QN(n29) );
DFFRX2TS Q_reg_27_ ( .D(n60), .CK(clk), .RN(n67), .Q(Q[27]), .QN(n28) );
DFFRX2TS Q_reg_26_ ( .D(n59), .CK(clk), .RN(n67), .Q(Q[26]), .QN(n27) );
DFFRX2TS Q_reg_25_ ( .D(n58), .CK(clk), .RN(n67), .Q(Q[25]), .QN(n26) );
DFFRX2TS Q_reg_24_ ( .D(n57), .CK(clk), .RN(n67), .Q(Q[24]), .QN(n25) );
DFFRX2TS Q_reg_23_ ( .D(n56), .CK(clk), .RN(n67), .Q(Q[23]), .QN(n24) );
DFFRX2TS Q_reg_22_ ( .D(n55), .CK(clk), .RN(n67), .Q(Q[22]), .QN(n23) );
DFFRX2TS Q_reg_21_ ( .D(n54), .CK(clk), .RN(n67), .Q(Q[21]), .QN(n22) );
DFFRX2TS Q_reg_20_ ( .D(n53), .CK(clk), .RN(n67), .Q(Q[20]), .QN(n21) );
DFFRX2TS Q_reg_19_ ( .D(n52), .CK(clk), .RN(n66), .Q(Q[19]), .QN(n20) );
DFFRX2TS Q_reg_18_ ( .D(n51), .CK(clk), .RN(n66), .Q(Q[18]), .QN(n19) );
DFFRX2TS Q_reg_17_ ( .D(n50), .CK(clk), .RN(n66), .Q(Q[17]), .QN(n18) );
DFFRX2TS Q_reg_16_ ( .D(n49), .CK(clk), .RN(n66), .Q(Q[16]), .QN(n17) );
DFFRX2TS Q_reg_15_ ( .D(n48), .CK(clk), .RN(n66), .Q(Q[15]), .QN(n16) );
DFFRX2TS Q_reg_14_ ( .D(n47), .CK(clk), .RN(n66), .Q(Q[14]), .QN(n15) );
DFFRX2TS Q_reg_13_ ( .D(n46), .CK(clk), .RN(n66), .Q(Q[13]), .QN(n14) );
DFFRX2TS Q_reg_12_ ( .D(n45), .CK(clk), .RN(n66), .Q(Q[12]), .QN(n13) );
DFFRX2TS Q_reg_11_ ( .D(n44), .CK(clk), .RN(n66), .Q(Q[11]), .QN(n12) );
DFFRX2TS Q_reg_10_ ( .D(n43), .CK(clk), .RN(n66), .Q(Q[10]), .QN(n11) );
DFFRX2TS Q_reg_9_ ( .D(n42), .CK(clk), .RN(n64), .Q(Q[9]), .QN(n10) );
DFFRX2TS Q_reg_8_ ( .D(n41), .CK(clk), .RN(n64), .Q(Q[8]), .QN(n9) );
DFFRX2TS Q_reg_7_ ( .D(n40), .CK(clk), .RN(n64), .Q(Q[7]), .QN(n8) );
DFFRX2TS Q_reg_6_ ( .D(n39), .CK(clk), .RN(n64), .Q(Q[6]), .QN(n7) );
DFFRX2TS Q_reg_5_ ( .D(n38), .CK(clk), .RN(n64), .Q(Q[5]), .QN(n6) );
DFFRX2TS Q_reg_4_ ( .D(n37), .CK(clk), .RN(n64), .Q(Q[4]), .QN(n5) );
DFFRX2TS Q_reg_3_ ( .D(n36), .CK(clk), .RN(n64), .Q(Q[3]), .QN(n4) );
DFFRX2TS Q_reg_2_ ( .D(n35), .CK(clk), .RN(n64), .Q(Q[2]), .QN(n3) );
DFFRX2TS Q_reg_1_ ( .D(n34), .CK(clk), .RN(n64), .Q(Q[1]), .QN(n2) );
DFFRX2TS Q_reg_0_ ( .D(n33), .CK(clk), .RN(n64), .Q(Q[0]), .QN(n1) );
BUFX3TS U2 ( .A(n75), .Y(n70) );
BUFX3TS U3 ( .A(n75), .Y(n71) );
BUFX3TS U4 ( .A(n74), .Y(n72) );
CLKBUFX2TS U5 ( .A(n74), .Y(n73) );
CLKBUFX2TS U6 ( .A(n68), .Y(n75) );
CLKBUFX2TS U7 ( .A(n68), .Y(n74) );
BUFX3TS U8 ( .A(n74), .Y(n69) );
BUFX3TS U9 ( .A(n76), .Y(n64) );
BUFX3TS U10 ( .A(n76), .Y(n66) );
BUFX3TS U11 ( .A(n76), .Y(n67) );
CLKBUFX2TS U12 ( .A(load), .Y(n68) );
INVX2TS U13 ( .A(rst), .Y(n76) );
OAI2BB2XLTS U14 ( .B0(n1), .B1(n70), .A0N(n73), .A1N(D[0]), .Y(n33) );
OAI2BB2XLTS U15 ( .B0(n3), .B1(n70), .A0N(D[2]), .A1N(n72), .Y(n35) );
OAI2BB2XLTS U16 ( .B0(n2), .B1(n73), .A0N(D[1]), .A1N(n73), .Y(n34) );
OAI2BB2XLTS U17 ( .B0(n4), .B1(n75), .A0N(D[3]), .A1N(n72), .Y(n36) );
OAI2BB2XLTS U18 ( .B0(n5), .B1(n75), .A0N(D[4]), .A1N(n72), .Y(n37) );
OAI2BB2XLTS U19 ( .B0(n6), .B1(n73), .A0N(D[5]), .A1N(n71), .Y(n38) );
OAI2BB2XLTS U20 ( .B0(n7), .B1(n74), .A0N(D[6]), .A1N(n71), .Y(n39) );
OAI2BB2XLTS U21 ( .B0(n8), .B1(n68), .A0N(D[7]), .A1N(n71), .Y(n40) );
OAI2BB2XLTS U22 ( .B0(n9), .B1(load), .A0N(D[8]), .A1N(n70), .Y(n41) );
OAI2BB2XLTS U23 ( .B0(n10), .B1(load), .A0N(D[9]), .A1N(n71), .Y(n42) );
OAI2BB2XLTS U24 ( .B0(n11), .B1(load), .A0N(D[10]), .A1N(n70), .Y(n43) );
OAI2BB2XLTS U25 ( .B0(n12), .B1(n75), .A0N(D[11]), .A1N(n70), .Y(n44) );
OAI2BB2XLTS U26 ( .B0(n13), .B1(n75), .A0N(D[12]), .A1N(n70), .Y(n45) );
OAI2BB2XLTS U27 ( .B0(n14), .B1(n75), .A0N(D[13]), .A1N(n70), .Y(n46) );
OAI2BB2XLTS U28 ( .B0(n15), .B1(load), .A0N(D[14]), .A1N(n70), .Y(n47) );
OAI2BB2XLTS U29 ( .B0(n16), .B1(load), .A0N(D[15]), .A1N(n71), .Y(n48) );
OAI2BB2XLTS U30 ( .B0(n17), .B1(load), .A0N(D[16]), .A1N(n70), .Y(n49) );
OAI2BB2XLTS U31 ( .B0(n18), .B1(n68), .A0N(D[17]), .A1N(n70), .Y(n50) );
OAI2BB2XLTS U32 ( .B0(n19), .B1(n68), .A0N(D[18]), .A1N(n71), .Y(n51) );
OAI2BB2XLTS U33 ( .B0(n20), .B1(n68), .A0N(D[19]), .A1N(n71), .Y(n52) );
OAI2BB2XLTS U34 ( .B0(n21), .B1(n68), .A0N(D[20]), .A1N(n71), .Y(n53) );
OAI2BB2XLTS U35 ( .B0(n22), .B1(n69), .A0N(D[21]), .A1N(n72), .Y(n54) );
OAI2BB2XLTS U36 ( .B0(n23), .B1(n69), .A0N(D[22]), .A1N(n71), .Y(n55) );
OAI2BB2XLTS U37 ( .B0(n24), .B1(n69), .A0N(D[23]), .A1N(n71), .Y(n56) );
OAI2BB2XLTS U38 ( .B0(n25), .B1(n69), .A0N(D[24]), .A1N(n72), .Y(n57) );
OAI2BB2XLTS U39 ( .B0(n26), .B1(n69), .A0N(D[25]), .A1N(n72), .Y(n58) );
OAI2BB2XLTS U40 ( .B0(n27), .B1(n69), .A0N(D[26]), .A1N(n72), .Y(n59) );
OAI2BB2XLTS U41 ( .B0(n28), .B1(n69), .A0N(D[27]), .A1N(n72), .Y(n60) );
OAI2BB2XLTS U42 ( .B0(n29), .B1(n69), .A0N(D[28]), .A1N(n72), .Y(n61) );
OAI2BB2XLTS U43 ( .B0(n30), .B1(n69), .A0N(D[29]), .A1N(n72), .Y(n62) );
OAI2BB2XLTS U44 ( .B0(n31), .B1(n69), .A0N(D[30]), .A1N(n73), .Y(n63) );
OAI2BB2XLTS U45 ( .B0(n32), .B1(n74), .A0N(D[31]), .A1N(n73), .Y(n65) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module Tenth_Phase_W32_EW8_SW23 ( clk, rst, load_i, sel_a_i, sel_b_i, sign_i,
exp_ieee_i, sgf_ieee_i, final_result_ieee_o );
input [7:0] exp_ieee_i;
input [22:0] sgf_ieee_i;
output [31:0] final_result_ieee_o;
input clk, rst, load_i, sel_a_i, sel_b_i, sign_i;
wire overunder, Sign_S_mux;
wire [7:0] Exp_S_mux;
wire [22:0] Sgf_S_mux;
Mux_3x1_W1 Sign_Mux ( .ctrl({sel_a_i, sel_b_i}), .D0(sign_i), .D1(1'b1),
.D2(1'b0), .S(Sign_S_mux) );
Multiplexer_AC_W8 Exp_Mux ( .ctrl(overunder), .D0(exp_ieee_i), .D1({1'b1,
1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), .S(Exp_S_mux) );
Multiplexer_AC_W23 Sgf_Mux ( .ctrl(overunder), .D0(sgf_ieee_i), .D1({1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}), .S(
Sgf_S_mux) );
RegisterAdd_W32 Final_Result_IEEE ( .clk(clk), .rst(rst), .load(load_i), .D(
{Sign_S_mux, Exp_S_mux, Sgf_S_mux}), .Q(final_result_ieee_o) );
OR2X2TS U3 ( .A(sel_a_i), .B(sel_b_i), .Y(overunder) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_round_flag, FSM_add_overflow_flag,
FSM_first_phase_load, FSM_load_first_step,
FSM_exp_operation_load_result, FSM_load_second_step,
FSM_adder_round_norm_load, FSM_final_result_load,
FSM_barrel_shifter_load, selector_A, load_b, selector_C,
FSM_exp_operation_A_S, FSM_Shift_Value, rst_int, FSM_selector_A,
FSM_selector_C, sign_final_result, n1;
wire [1:0] selector_B;
wire [1:0] FSM_selector_B;
wire [31:0] Op_MX;
wire [31:0] Op_MY;
wire [8:0] exp_oper_result;
wire [8:0] S_Oper_A_exp;
wire [7:0] S_Oper_B_exp;
wire [23:0] significand;
wire [22:0] non_significand;
wire [23:0] Add_result;
wire [23:0] S_Data_Shift;
wire [23:0] Sgf_normalized_result;
FSM_Mult_Function FS_Module ( .clk(clk), .rst(rst), .beg_FSM(beg_FSM),
.ack_FSM(ack_FSM), .zero_flag_i(zero_flag), .Mult_shift_i(1'b0),
.round_flag_i(FSM_round_flag), .Add_Overflow_i(FSM_add_overflow_flag),
.load_0_o(FSM_first_phase_load), .load_1_o(FSM_load_first_step),
.load_2_o(FSM_exp_operation_load_result), .load_3_o(
FSM_load_second_step), .load_4_o(FSM_adder_round_norm_load),
.load_5_o(FSM_final_result_load), .load_6_o(FSM_barrel_shifter_load),
.ctrl_select_a_o(selector_A), .ctrl_select_b_o(load_b), .selector_b_o(
selector_B), .ctrl_select_c_o(selector_C), .exp_op_o(
FSM_exp_operation_A_S), .shift_value_o(FSM_Shift_Value), .rst_int(
rst_int), .ready(ready) );
RegisterAdd_W1_3 Sel_A ( .clk(clk), .rst(rst_int), .load(selector_A), .D(
1'b1), .Q(FSM_selector_A) );
RegisterAdd_W1_2 Sel_C ( .clk(clk), .rst(n1), .load(selector_C), .D(1'b1),
.Q(FSM_selector_C) );
RegisterAdd_W2 Sel_B ( .clk(clk), .rst(rst_int), .load(load_b), .D(
selector_B), .Q(FSM_selector_B) );
First_Phase_M_W32 Operands_load_reg ( .clk(clk), .rst(rst_int), .load(
FSM_first_phase_load), .Data_MX(Data_MX), .Data_MY(Data_MY), .Op_MX(
Op_MX), .Op_MY(Op_MY) );
Zero_InfMult_Unit_W32 Zero_Result_Detect ( .clk(clk), .rst(n1), .load(
FSM_load_first_step), .Data_A(Op_MX[30:0]), .Data_B(Op_MY[30:0]),
.zero_m_flag(zero_flag) );
Multiplexer_AC_W9 Exp_Oper_A_mux ( .ctrl(FSM_selector_A), .D0({1'b0,
Op_MX[30:23]}), .D1(exp_oper_result), .S(S_Oper_A_exp) );
Mux_3x1_W8 Exp_Oper_B_mux ( .ctrl(FSM_selector_B), .D0(Op_MY[30:23]), .D1({
1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), .D2({1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1}), .S(S_Oper_B_exp) );
Exp_Operation_m_EW8 Exp_module ( .clk(clk), .rst(n1), .load_a_i(
FSM_load_first_step), .load_b_i(FSM_load_second_step), .load_c_i(
FSM_exp_operation_load_result), .Data_A_i(S_Oper_A_exp), .Data_B_i({
1'b0, S_Oper_B_exp}), .Add_Subt_i(FSM_exp_operation_A_S),
.Data_Result_o(exp_oper_result), .Overflow_flag_o(overflow_flag),
.Underflow_flag_o(underflow_flag) );
XOR_M Sign_operation ( .Sgn_X(Op_MX[31]), .Sgn_Y(Op_MY[31]), .Sgn_Info(
sign_final_result) );
Multiplexer_AC_W24 Barrel_Shifter_D_I_mux ( .ctrl(FSM_selector_C), .D0({1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.D1(Add_result), .S(S_Data_Shift) );
Barrel_Shifter_M_SW24 Barrel_Shifter_module ( .clk(clk), .rst(n1), .load_i(
FSM_barrel_shifter_load), .Shift_Value_i(FSM_Shift_Value),
.Shift_Data_i(S_Data_Shift), .N_mant_o(Sgf_normalized_result) );
Round_decoder_M_SW23 Round_Decoder ( .Round_Bits_i({1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}), .Round_Mode_i(round_mode),
.Sign_Result_i(sign_final_result), .Round_Flag_o(FSM_round_flag) );
Adder_Round_SW24 Adder_M ( .clk(clk), .rst(n1), .load_i(
FSM_adder_round_norm_load), .Data_A_i(Sgf_normalized_result),
.Data_B_i({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1,
1'b1, 1'b1}), .Data_Result_o(Add_result), .FSM_C_o(
FSM_add_overflow_flag) );
Tenth_Phase_W32_EW8_SW23 final_result_ieee_Module ( .clk(clk), .rst(n1),
.load_i(FSM_final_result_load), .sel_a_i(overflow_flag), .sel_b_i(
underflow_flag), .sign_i(sign_final_result), .exp_ieee_i(
exp_oper_result[7:0]), .sgf_ieee_i(Sgf_normalized_result[22:0]),
.final_result_ieee_o(final_result_ieee) );
BUFX3TS U3 ( .A(rst_int), .Y(n1) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule |
module artemis_pcie_sata (
//------------------------------- PLL Ports --------------------------------
input i_sata_reset,
input i_pcie_reset,
output o_sata_pll_detect_k,
output o_pcie_pll_detect_k,
output o_sata_reset_done,
output o_pcie_reset_done,
output o_sata_75mhz_clk,
output o_sata_300mhz_clk,
output o_pcie_62p5mhz_clk,
output o_sata_dcm_locked,
output o_pcie_dcm_locked,
//------------- Receive Ports - RX Loss-of-sync State Machine --------------
output [1:0] o_sata_loss_of_sync,
output [1:0] o_pcie_loss_of_sync,
//--------------------- Receive Ports - 8b10b Decoder ----------------------
output [3:0] o_sata_rx_char_is_comma,
output [3:0] o_sata_rx_char_is_k,
output [3:0] o_pcie_rx_char_is_k,
output [3:0] o_sata_disparity_error,
output [3:0] o_pcie_disparity_error,
output [3:0] o_sata_rx_not_in_table,
output [3:0] o_pcie_rx_not_in_table,
//-------------------- Receive Ports - Clock Correction --------------------
output [2:0] o_sata_clk_correct_count,
output [2:0] o_pcie_clk_correct_count,
//----------------- Receive Ports - RX Data Path interface -----------------
output [31:0] o_sata_rx_data,
output [31:0] o_pcie_rx_data,
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
output o_sata_rx_elec_idle,
output o_pcie_rx_elec_idle,
input [1:0] i_sata_rx_pre_amp,
input i_sata_phy_rx_p,
input i_sata_phy_rx_n,
input i_pcie_phy_rx_p,
input i_pcie_phy_rx_n,
//--------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
output o_sata_rx_byte_is_aligned,
output o_pcie_rx_byte_is_aligned,
output [2:0] o_sata_rx_status,
output [2:0] o_pcie_rx_status,
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
output o_pcie_phy_status,
output o_pcie_phy_rx_valid,
//------------------ Receive Ports - RX Polarity Control -------------------
input i_pcie_rx_polarity,
//----------------- Transmit Ports - 8b10b Encoder Control -----------------
input [3:0] i_pcie_disparity_mode,
input i_sata_tx_char_is_k,
input [3:0] i_pcie_tx_char_is_k,
//---------------- Transmit Ports - TX Data Path interface -----------------
input [31:0] i_sata_tx_data,
input [31:0] i_pcie_tx_data,
//------------- Transmit Ports - TX Driver and OOB signalling --------------
input [3:0] i_tx_diff_swing,
output o_sata_phy_tx_p,
output o_sata_phy_tx_n,
output o_pcie_phy_tx_p,
output o_pcie_phy_tx_n,
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
input i_pcie_tx_detect_rx,
input i_sata_tx_elec_idle,
input i_pcie_tx_elec_idle,
//------------------- Transmit Ports - TX Ports for SATA -------------------
input i_sata_tx_comm_start,
input i_sata_tx_comm_type,
input i_gtp0_clk_p,
input i_gtp0_clk_n,
input i_gtp1_clk_p,
input i_gtp1_clk_n
);
//Registers/Wires
wire sata_300mhz_clk;
wire sata_75mhz_clk;
//Feeds into the Pre DCM Buffer
wire [1:0] sata_gtp_clkout;
//From Pre DCM Buffer to DCM
wire sata_dcm_clkin;
wire sata_dcm_reset;
wire [1:0] pcie_gtp_clkout;
//wire pcie_gtp_clkout;
wire pcie_dcm_clkin;
wire pcie_dcm_reset;
wire pcie_250mhz_clk;
wire pcie_rx_reset;
wire tile0_gtp0_refclk_i;
wire tile0_gtp1_refclk_i;
//wire sata_txout;
//wire pcie_txout;
aps#(
.WRAPPER_SIM_GTPRESET_SPEEDUP (0 ), // Set this to 1 for simulation
.WRAPPER_SIMULATION (0 ), // Set this to 1 for simulation
.WRAPPER_CLK25_DIVIDER_0 (6 ),
.WRAPPER_CLK25_DIVIDER_1 (4 ),
//SATA 3GHz: N1 = 5, N2 = 2, D = 1, M = 1
.WRAPPER_PLL_DIVSEL_FB_0 (2 ), // N2 = 2
.WRAPPER_PLL_DIVSEL_REF_0 (1 ), // M = 1
//PCIE 2.5GHz N1 = 5, N2 = 5, D = 1, M = 2
.WRAPPER_PLL_DIVSEL_FB_1 (5 ), // N2 = 5
.WRAPPER_PLL_DIVSEL_REF_1 (2 ) // M = 2
)
artemis_pcie_sata_i(
//_____________________________________________________________________
//_____________________________________________________________________
//TILE0 (X0_Y0)
//---------------------- Loopback and Powerdown Ports ----------------------
.TILE0_RXPOWERDOWN1_IN (2'b0 ),
.TILE0_TXPOWERDOWN1_IN (2'b0 ),
//------------------------------- PLL Ports --------------------------------
.TILE0_CLK00_IN (tile0_gtp0_refclk_i ),
.TILE0_CLK01_IN (tile0_gtp1_refclk_i ),
.TILE0_GTPRESET0_IN (i_sata_reset ),
.TILE0_GTPRESET1_IN (i_pcie_reset ),
.TILE0_PLLLKDET0_OUT (o_sata_pll_detect_k ),
.TILE0_PLLLKDET1_OUT (o_pcie_pll_detect_k ),
.TILE0_RESETDONE0_OUT (o_sata_reset_done ),
.TILE0_RESETDONE1_OUT (o_pcie_reset_done ),
//--------------------- Receive Ports - 8b10b Decoder ----------------------
.TILE0_RXCHARISCOMMA0_OUT (o_sata_rx_char_is_comma ),
.TILE0_RXCHARISK0_OUT (o_sata_rx_char_is_k ),
.TILE0_RXCHARISK1_OUT (o_pcie_rx_char_is_k ),
.TILE0_RXDISPERR0_OUT (o_sata_disparity_error ),
.TILE0_RXDISPERR1_OUT (o_pcie_disparity_error ),
.TILE0_RXNOTINTABLE0_OUT (o_sata_rx_not_in_table ),
.TILE0_RXNOTINTABLE1_OUT (o_pcie_rx_not_in_table ),
//-------------------- Receive Ports - Clock Correction --------------------
.TILE0_RXCLKCORCNT0_OUT (o_sata_clk_correct_count),
.TILE0_RXCLKCORCNT1_OUT (o_pcie_clk_correct_count),
//------------- Receive Ports - Comma Detection and Alignment --------------
.TILE0_RXENMCOMMAALIGN0_IN (1'b1 ),
.TILE0_RXENMCOMMAALIGN1_IN (1'b1 ),
//XXX: should PCIE PLL Be aligned to both commas?
.TILE0_RXENPCOMMAALIGN0_IN (1'b1 ),
.TILE0_RXENPCOMMAALIGN1_IN (1'b1 ),
//----------------- Receive Ports - RX Data Path interface -----------------
.TILE0_RXDATA0_OUT (o_sata_rx_data ),
.TILE0_RXDATA1_OUT (o_pcie_rx_data ),
.TILE0_RXRECCLK0_OUT ( ),
.TILE0_RXRESET1_IN (pcie_rx_reset ),
.TILE0_RXUSRCLK0_IN (sata_300mhz_clk ),
.TILE0_RXUSRCLK1_IN (pcie_250mhz_clk ),
.TILE0_RXUSRCLK20_IN (sata_75mhz_clk ),
.TILE0_RXUSRCLK21_IN (o_pcie_62p5mhz_clk ),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
//XXX: tied 0 for both PCIE and SATA
.TILE0_GATERXELECIDLE0_IN (1'b0 ),
.TILE0_GATERXELECIDLE1_IN (1'b0 ),
//XXX: tied 0 for both PCIE and SATA
.TILE0_IGNORESIGDET0_IN (1'b0 ),
.TILE0_IGNORESIGDET1_IN (1'b0 ),
.TILE0_RXELECIDLE0_OUT (o_sata_rx_elec_idle ),
.TILE0_RXELECIDLE1_OUT (o_pcie_rx_elec_idle ),
.TILE0_RXEQMIX0_IN (i_sata_rx_pre_amp ),
.TILE0_RXP0_IN (i_sata_phy_rx_p ),
.TILE0_RXN0_IN (i_sata_phy_rx_n ),
.TILE0_RXP1_IN (i_pcie_phy_rx_p ),
.TILE0_RXN1_IN (i_pcie_phy_rx_n ),
//--------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
.TILE0_RXBYTEALIGNED0_OUT (o_sata_rx_byte_is_aligned ),
.TILE0_RXBYTEALIGNED1_OUT (o_pcie_rx_byte_is_aligned ),
.TILE0_RXSTATUS0_OUT (o_sata_rx_status ),
.TILE0_RXSTATUS1_OUT (o_pcie_rx_status ),
//------------- Receive Ports - RX Loss-of-sync State Machine --------------
.TILE0_RXLOSSOFSYNC0_OUT (o_sata_loss_of_sync ),
.TILE0_RXLOSSOFSYNC1_OUT (o_pcie_loss_of_sync ),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.TILE0_PHYSTATUS1_OUT (o_pcie_phy_status ),
.TILE0_RXVALID1_OUT (o_pcie_phy_rx_valid ),
//------------------ Receive Ports - RX Polarity Control -------------------
.TILE0_RXPOLARITY1_IN (i_pcie_rx_polarity ),
//-------------------------- TX/RX Datapath Ports --------------------------
.TILE0_GTPCLKOUT0_OUT (sata_gtp_clkout ),
.TILE0_GTPCLKOUT1_OUT (pcie_gtp_clkout ),
//----------------- Transmit Ports - 8b10b Encoder Control -----------------
.TILE0_TXCHARDISPMODE1_IN (i_pcie_disparity_mode ),
.TILE0_TXCHARISK0_IN ({1'b0, 1'b0, 1'b0, i_sata_tx_char_is_k}),
.TILE0_TXCHARISK1_IN (i_pcie_tx_char_is_k ),
//---------------- Transmit Ports - TX Data Path interface -----------------
.TILE0_TXDATA0_IN (i_sata_tx_data ),
.TILE0_TXDATA1_IN (i_pcie_tx_data ),
.TILE0_TXOUTCLK0_OUT ( ),
.TILE0_TXOUTCLK1_OUT ( ),
.TILE0_TXUSRCLK0_IN (sata_300mhz_clk ),
.TILE0_TXUSRCLK1_IN (pcie_250mhz_clk ),
.TILE0_TXUSRCLK20_IN (sata_75mhz_clk ),
.TILE0_TXUSRCLK21_IN (o_pcie_62p5mhz_clk ),
//------------- Transmit Ports - TX Driver and OOB signalling --------------
.TILE0_TXDIFFCTRL0_IN (i_tx_diff_swing ),
.TILE0_TXP0_OUT (o_sata_phy_tx_p ),
.TILE0_TXN0_OUT (o_sata_phy_tx_n ),
.TILE0_TXP1_OUT (o_pcie_phy_tx_p ),
.TILE0_TXN1_OUT (o_pcie_phy_tx_n ),
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
.TILE0_TXDETECTRX1_IN (i_pcie_tx_detect_rx ),
.TILE0_TXELECIDLE0_IN (i_sata_tx_elec_idle ),
.TILE0_TXELECIDLE1_IN (i_pcie_tx_elec_idle ),
//------------------- Transmit Ports - TX Ports for SATA -------------------
.TILE0_TXCOMSTART0_IN (i_sata_tx_comm_start ),
.TILE0_TXCOMTYPE0_IN (i_sata_tx_comm_type )
);
//---------------------Dedicated GTP Reference Clock Inputs ---------------
// Each dedicated refclk you are using in your design will need its own IBUFDS instance
//SATA Clock Path
IBUFDS tile0_gtp0_refclk_ibufds_i(
.O (tile0_gtp0_refclk_i ),
.I (i_gtp0_clk_p ), // Connect to package pin A10
.IB (i_gtp0_clk_n ) // Connect to package pin B10
);
//PHY Signals -> IBUFDS -> GTP PLL -> BUFIO2 -> PLL (Frequency Synthesis) -> All Sata Clocks
//150 MHz diff -> IBUFDS -> GTP PLL -> BUFIO2 (150MHz) -> PLL_ADV -> (USERCLK1: 300MHz, USRCLK2: 75MHz)
BUFIO2 #(
.DIVIDE (1),
.DIVIDE_BYPASS ("TRUE")
) i_sata_pll_buf (
.I (sata_gtp_clkout[0]),
.DIVCLK (sata_dcm_clkin),
.IOCLK (),
.SERDESSTROBE ()
);
assign sata_dcm_reset = !o_sata_pll_detect_k;
//wire sata_pll_feedback;
wire sata_75mhz_bufg_in;
wire sata_300mhz_bufg_in;
//wire sata_pll_feedback_out;
wire sata_pll_feedback;
/*
BUFG sata_fb_bufg(
.I (sata_pll_feedback_out),
.O (sata_txout)
);
*/
/*
BUFIO2FB sata_clkfb(
.I (sata_pll_feedback_out),
.O (sata_pll_feedback)
);
*/
PLL_BASE #(
.CLKFBOUT_MULT (4 ),
.DIVCLK_DIVIDE (1 ),
.CLK_FEEDBACK ("CLKFBOUT" ),
.COMPENSATION ("SYSTEM_SYNCHRONOUS" ),
.CLKIN_PERIOD (6.666 ),
.CLKOUT0_DIVIDE (2 ),
.CLKOUT0_PHASE (0 ),
.CLKOUT1_DIVIDE (8 ),
.CLKOUT1_PHASE (0 )
)
SATA_PLL(
.CLKIN (sata_dcm_clkin ),
//.CLKINSEL (1'b1 ),
.CLKOUT0 (sata_300mhz_bufg_in ),
.CLKOUT1 (sata_75mhz_bufg_in ),
.CLKOUT2 ( ),
.CLKOUT3 ( ),
.CLKOUT4 ( ),
.CLKOUT5 ( ),
.CLKFBOUT (sata_pll_feedback ),
.CLKFBIN (sata_pll_feedback ),
.LOCKED (o_sata_dcm_locked ),
.RST (sata_dcm_reset )
);
BUFG SATA_75MHZ_BUFG (
.I (sata_75mhz_bufg_in ),
.O (sata_75mhz_clk )
);
BUFG SATA_300MHZ_BUFG (
.I (sata_300mhz_bufg_in ),
.O (sata_300mhz_clk )
);
assign o_sata_75mhz_clk = sata_75mhz_clk;
assign o_sata_300mhz_clk = sata_300mhz_clk;
//PCIE Clock Path
/* PHY Signals -> IBUFDS -> GTP PLL -> BUFIO2 -> PLL (Frequency Synthesis) -> All PCIE Clocks
* 300 MHz diff -> IBUFDS -> GTP PLL -> BUFIO2 (300MHz) -> PLL_ADV -> (USERCLK1: 300MHz, USRCLK2: 62P5MHz)
*/
IBUFDS tile0_gtp1_refclk_ibufds_i(
.O (tile0_gtp1_refclk_i),
.I (i_gtp1_clk_p), // Connect to package pin C11
.IB (i_gtp1_clk_n) // Connect to package pin D11
);
BUFIO2 #(
.DIVIDE (1),
.DIVIDE_BYPASS ("TRUE")
) i_pcie_pll_buf (
.I (pcie_gtp_clkout[0]),
//.I (pcie_gtp_clkout),
.DIVCLK (pcie_dcm_clkin),
.IOCLK (),
.SERDESSTROBE ()
);
assign pcie_dcm_reset = !o_pcie_pll_detect_k;
//wire pcie_pll_feedback;
wire pcie_62p5mhz_bufg_in;
wire pcie_250mhz_bufg_in;
wire pcie_pll_feedback_out;
/*
BUFG pcie_clk_bufg(
.I (pcie_pll_feedback_out),
.O (pcie_txout)
);
BUFIO2FB pcie_clkfb(
.I (pcie_txout),
.O (pcie_pll_feedback)
);
*/
PLL_BASE #(
.CLKFBOUT_MULT (10 ),
.DIVCLK_DIVIDE (1 ),
.CLK_FEEDBACK ("CLKFBOUT" ),
.COMPENSATION ("SYSTEM_SYNCHRONOUS" ),
.CLKIN_PERIOD (10.000 ),
.CLKOUT0_DIVIDE (4 ),
.CLKOUT0_PHASE (0 ),
.CLKOUT1_DIVIDE (16 ),
.CLKOUT1_PHASE (0 )
)
PCIE_PLL(
.CLKIN (pcie_dcm_clkin ),
//.CLKINSEL (1'b1 ),
.CLKOUT0 (pcie_250mhz_bufg_in ),
.CLKOUT1 (pcie_62p5mhz_bufg_in ),
.CLKOUT2 ( ),
.CLKOUT3 ( ),
.CLKOUT4 ( ),
.CLKOUT5 ( ),
.CLKFBOUT (pcie_pll_feedback_out),
.CLKFBIN (pcie_pll_feedback_out),
.LOCKED (o_pcie_dcm_locked ),
.RST (pcie_dcm_reset )
);
BUFG PCIE_62P5MHZ_BUFG (
.I (pcie_62p5mhz_bufg_in ),
.O (o_pcie_62p5mhz_clk )
);
BUFG PCIE_250MHZ_BUFG (
.I (pcie_250mhz_bufg_in ),
.O (pcie_250mhz_clk )
);
assign pcie_rx_reset = !(o_pcie_dcm_locked && o_pcie_pll_detect_k);
endmodule |
module sky130_fd_sc_ls__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule |
module axi_traffic_gen_v2_0_7_cmdram #(
parameter C_FAMILY = "virtex7",
parameter C_INITRAM_0 = "NONE",
parameter C_INITRAM_1 = "NONE",
parameter C_INITRAM_2 = "NONE",
parameter C_INITRAM_3 = "NONE"
) (
input reset ,
input clk_a ,
input active ,
input [15:0 ] we_a ,
input [15:0 ] addr_a_idle ,
input [15:0 ] addr_a_active ,
input [127:0] wr_data_a ,
output [127:0] rd_data_a ,
input clk_b ,
input addr_b_idle_latch,
input [15:0 ] addr_b_idle ,
input [15:0 ] addr_b_active ,
output [127:0] rd_data_b
);
// axi_traffic_gen_v2_0_7_cmdram
wire [127:0] a_int_rd_data, b_int_rd_data;
reg [12:0] a_addr_active_ff, b_addr_active_ff;
reg [127:0] a_int_rd_ff, b_int_rd_ff;
reg [12:0] b_addr_idle_save_ff;
reg active_ff, active_2ff;
wire a_changed = (addr_a_active[4] ^ a_addr_active_ff[4]) ||
(active_ff && ~active_2ff);
wire [12:0] a_addr_act = addr_a_active[12:0] ;
wire [12:0] a_addr = (active) ? a_addr_act[12:0] : addr_a_idle[12:0];
wire [127:0] a_int_rd = (a_changed || ~active) ? a_int_rd_data[127:0] :
a_int_rd_ff[127:0];
wire b_changed = (addr_b_active[4] ^ b_addr_active_ff[4]) ||
(active_ff && ~active_2ff);
wire [12:0] b_addr_act = addr_b_active[12:0] ;
wire [12:0] b_addr_idle_save = (addr_b_idle_latch) ? addr_b_idle[12:0] :
b_addr_idle_save_ff[12:0];
wire [12:0] b_addr = (active) ? b_addr_act[12:0] : b_addr_idle_save[12:0];
wire [127:0] b_int_rd = (b_changed || ~active) ? b_int_rd_data[127:0] :
b_int_rd_ff[127:0];
always @(posedge clk_b) begin
active_ff <= active;
active_2ff <= active_ff;
a_addr_active_ff[12:0] <= addr_a_active[12:0];
b_addr_active_ff[12:0] <= addr_b_active[12:0];
a_int_rd_ff[127:0] <= a_int_rd[127:0];
b_int_rd_ff[127:0] <= b_int_rd[127:0];
b_addr_idle_save_ff[12:0] <= (reset) ? 13'b0 : b_addr_idle_save[12:0];
end
//cmdram: 512 commands each of 128-bit width
axi_traffic_gen_v2_0_7_inferram #(
.C_FAMILY (C_FAMILY ),
//.C_RAMINIT_F("/home/kpolise/cmd.mif"),
.C_RAMINIT_F(C_INITRAM_0),
.SIZE (512 ),
.ADDR_WIDTH (9 ),
.NB_COL (16 ),
.COL_WIDTH (8 ),
.INFER_TYPE (1 )
)
cmd_ram0_3 (
.clk (clk_a ),
.wea (we_a[15:0] ),
.web (16'b0 ),
.addra(a_addr[12:4] ),
.addrb(b_addr[12:4] ),
.dia (wr_data_a[127:0] ),
.dib (128'h0 ),
.doa (a_int_rd_data[127:0]),
.dob (b_int_rd_data[127:0])
);
/*
axi_traffic_gen_v2_0_7_inferram #(
.C_RAMINIT_F(C_INITRAM_0),
.NB_COL(4),
.COL_WIDTH(8)
)
ram0 (
.clk(clk_a),
.wea(we_a[3:0]),
.web(4'b0),
.addra({1'b0,a_addr[12:4]}),
.addrb({1'b0,b_addr[12:4]}),
.dia(wr_data_a[31:0]),
.dib(32'b0),
.doa(a_int_rd_data[31:0]),
.dob(b_int_rd_data[31:0])
);
axi_traffic_gen_v2_0_7_inferram #(
.C_RAMINIT_F(C_INITRAM_1),
.NB_COL(4),
.COL_WIDTH(8)
)
ram1 (
.clk(clk_a),
.wea(we_a[7:4]),
.web(4'b0),
.addra({1'b0,a_addr[12:4]}),
.addrb({1'b0,b_addr[12:4]}),
.dia(wr_data_a[63:32]),
.dib(32'b0),
.doa(a_int_rd_data[63:32]),
.dob(b_int_rd_data[63:32])
);
axi_traffic_gen_v2_0_7_inferram #(
.C_RAMINIT_F(C_INITRAM_2),
.NB_COL(4),
.COL_WIDTH(8)
)
ram2 (
.clk(clk_a),
.wea(we_a[11:8]),
.web(4'b0),
.addra({1'b0,a_addr[12:4]}),
.addrb({1'b0,b_addr[12:4]}),
.dia(wr_data_a[95:64]),
.dib(32'b0),
.doa(a_int_rd_data[95:64]),
.dob(b_int_rd_data[95:64])
);
axi_traffic_gen_v2_0_7_inferram #(
.C_RAMINIT_F(C_INITRAM_3),
.NB_COL(4),
.COL_WIDTH(8)
)
ram3 (
.clk(clk_a),
.wea(we_a[15:12]),
.web(4'b0),
.addra({1'b0,a_addr[12:4]}),
.addrb({1'b0,b_addr[12:4]}),
.dia(wr_data_a[127:96]),
.dib(32'b0),
.doa(a_int_rd_data[127:96]),
.dob(b_int_rd_data[127:96])
);
*/
assign rd_data_a[127:0] = a_int_rd_data[127:0] ;
assign rd_data_b[127:0] = b_int_rd_data[127:0] ;
endmodule |
module PGM(
input CLK, RESET,
input [1:0] MORE,
input BTN_w, BTN_e, BTN_s,
output reg [7:0] oLED
);
parameter MAXH = 10;
parameter ST_INIT = 4'b0000;
parameter ST_FA = 4'b0001;
parameter ST_SB = 4'b0010;
parameter ST_FB = 4'b0011;
parameter ST_SA = 4'b0100;
parameter ST_A = 4'b0101;
parameter ST_B = 4'b0110;
parameter ST_WAIT = 4'b0111;
parameter ST_OUTPUT = 4'b1000;
reg [3:0] state, next_state;
reg [3:0] randcard;
integer m_w;
reg inA, inB, inC;
reg [1:0] inMR;
reg [4:0] handA, handB;
reg [1:0] WIN;
reg [3:0] SUM, CARD;
wire ED_w, ED_s, ED_e;
syn_edge_detect ed1(CLK, RESET, BTN_w, ED_w);
syn_edge_detect ed2(CLK, RESET, BTN_e, ED_e);
syn_edge_detect ed3(CLK, RESET, BTN_s, ED_s);
//assign ED_w = BTN_w;
//assign ED_e = BTN_e;
//assign ED_s = BTN_s;
always @(RESET, WIN, SUM, CARD, state)
begin
if (RESET)
oLED <= 8'b00000000;
else begin
oLED[7:6] <= WIN;
case (state)
ST_OUTPUT:
oLED[3:0] <= SUM;
default:
oLED[3:0] <= CARD;
endcase
end
end
// Random number generator
always @(posedge CLK)
begin
if (RESET) begin
randcard <= 4'b0000;
m_w <= 55332;
end
else begin
m_w <= 18000 * (m_w & 65535) + (m_w >> 16);
randcard <= ((m_w >> 4) % 8) + 1;
end
end
// Synchronizer
always @(posedge CLK)
begin
if (RESET) begin
inA <= 1'b0;
inB <= 1'b0;
inC <= 1'b0;
inMR <= 2'bxx;
end
else begin
inA <= ED_e;
inB <= ED_w;
inC <= ED_s;
inMR <= MORE;
end
end
// Finite State Machine
always @(posedge CLK)
begin
if (RESET)
state <= ST_INIT;
else
state <= next_state;
end
always @(state, handA, handB, inA, inB, inC, inMR, RESET)
begin
case (state)
ST_INIT:
if (inA)
next_state = ST_FA;
else if (inB)
next_state = ST_FB;
else
next_state = ST_INIT;
ST_FA:
if (inB)
next_state = ST_SB;
else
next_state = ST_FA;
ST_SB:
if (inC) begin
if (handA > MAXH || handB > MAXH)
next_state = ST_OUTPUT;
else
next_state = ST_WAIT;
end
else
next_state = ST_SB;
ST_FB:
if (inA)
next_state = ST_SA;
else
next_state = ST_FB;
ST_SA:
if (inC)
if (handA > MAXH || handB > MAXH)
next_state = ST_OUTPUT;
else next_state = ST_WAIT;
else
next_state = ST_SA;
ST_A:
if (inC)
if (handA > MAXH || handB > MAXH)
next_state = ST_OUTPUT;
else
next_state = ST_WAIT;
else
next_state = ST_A;
ST_B:
if (inC)
if (handA > MAXH || handB > MAXH)
next_state = ST_OUTPUT;
else
next_state = ST_WAIT;
else
next_state = ST_B;
ST_WAIT:
if (inA && inMR == 2'b01)
next_state = ST_A;
else if (inB && inMR == 2'b10)
next_state = ST_B;
else if (inA && inMR == 2'b11)
next_state = ST_FA;
else if (inB && inMR == 2'b11)
next_state = ST_FB;
else if (inMR == 2'b00 && (inA || inB))
next_state = ST_OUTPUT;
else
next_state = ST_WAIT;
ST_OUTPUT: next_state = ST_OUTPUT;
default:
next_state = ST_INIT;
endcase
if (RESET)
next_state = ST_INIT;
end
// FSM Behaviour
always @(posedge CLK)
begin
case (next_state)
ST_INIT: begin
handA <= 3'b000;
handB <= 3'b000;
CARD <= 3'b000;
end
ST_FA:
if (state != ST_FA) begin
handA <= handA + randcard;
CARD <= randcard;
end
ST_SB:
if (state != ST_SB) begin
handB <= handB + randcard;
CARD <= randcard;
end
ST_FB:
if (state != ST_FB) begin
handB <= handB + randcard;
CARD <= randcard;
end
ST_SA:
if (state != ST_SA) begin
handA <= handA + randcard;
CARD <= randcard;
end
ST_A:
if (state != ST_A) begin
handA <= handA + randcard;
CARD <= randcard;
end
ST_B:
if (state != ST_B) begin
handB <= handB + randcard;
CARD <= randcard;
end
default:
CARD <= 3'b000;
endcase
if (RESET) begin
handA <= 3'b000;
handB <= 3'b000;
CARD <= 3'b000;
end
end
// Output for SUM & WIN
always @(posedge CLK)
begin
if (state == ST_OUTPUT && ~RESET)
if ((handA > handB || handB > MAXH) && handA <= MAXH) begin
WIN <= 2'b01;
SUM <= handA;
end
else if ((handB > handA || handA > MAXH) && handB <= MAXH) begin
WIN <= 2'b10;
SUM <= handB;
end
else begin
WIN <= 2'b11;
SUM <= 4'd0;
end
else begin
WIN <= 2'b00;
SUM <= 4'd0;
end
end
endmodule |
module sky130_fd_sc_lp__a2111oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, C1, D1, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module sky130_fd_sc_lp__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y, nor0_out, and0_out);
buf buf0 (Y , nor1_out_Y );
endmodule |
module eightbit_alu(a, b, sel, f, ovf, zero);
input signed [7:0] a, b;
input [2:0] sel;
output reg signed [7:0] f;
output reg ovf;
output reg zero;
always@(a, b, sel) begin
zero = 0;
ovf = 0;
f = 0;
case(sel)
3'b000: begin // f = a + b
f = a + b;
ovf = ~(a[7] ^ b[7]) & (a[7] ^ f[7]);
end
3'b001: begin // f = ~b
f = ~b;
end
3'b010: begin // f = a & b
f = a & b;
end
3'b011: begin // f = a | b
f = a | b;
end
3'b100: begin // f = a >>> 1
f = a >>> 1;
end
3'b101: begin // f = a <<< 1
f = a <<< 1;
end
3'b110: begin // zero = a == b
zero = a == b;
end
3'b111: begin // zero = a != b
zero = a != b;
end
endcase
end
endmodule |
module spw_babasu_FLAGS (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 10: 0] in_port;
input reset_n;
wire clk_en;
wire [ 10: 0] data_in;
wire [ 10: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {11 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule |
module test_subbytesall;
// Inputs
reg [127:0] subIn;
reg clk;
reg inverse;
// Outputs
wire [127:0] subOut;
// Instantiate the Unit Under Test (UUT)
subBytesAll uut (
.subOut(subOut),
.subIn(subIn),
.clk(clk),
.inverse(inverse)
);
always begin
clk = 0;
#10;
clk = 1;
#10;
end
initial begin
// Initialize Inputs
subIn = 128'h00102030405060708090a0b0c0d0e0f0;
inverse = 0;
// Wait 100 ns for global reset to finish
#10
#20 subIn = 128'h89d810e8855ace682d1843d8cb128fe4;
#20 subIn = 128'h4915598f55e5d7a0daca94fa1f0a63f7;
#20 subIn = 128'hfa636a2825b339c940668a3157244d17;
#20 subIn = 128'h247240236966b3fa6ed2753288425b6c;
#20 subIn = 128'hc81677bc9b7ac93b25027992b0261996;
// Add stimulus here
end
endmodule |
module jt51_exp2lin(
output reg signed [15:0] lin,
input signed [9:0] man,
input [2:0] exp
);
always @(*) begin
case( exp )
3'd7: lin = { man, 6'b0 };
3'd6: lin = { {1{man[9]}}, man, 5'b0 };
3'd5: lin = { {2{man[9]}}, man, 4'b0 };
3'd4: lin = { {3{man[9]}}, man, 3'b0 };
3'd3: lin = { {4{man[9]}}, man, 2'b0 };
3'd2: lin = { {5{man[9]}}, man, 1'b0 };
3'd1: lin = { {6{man[9]}}, man };
3'd0: lin = 16'd0;
endcase
end
endmodule |
module sky130_fd_sc_hs__a221o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule |
module testbench;
// Inputs
reg CLK;
reg RESET;
reg [1:0] MORE;
reg BTN_w, BTN_e, BTN_s;
// Outputs
wire [7:0] oLED;
wire [1:0] WIN;
wire [3:0] CARD;
assign WIN = oLED[7:6];
assign CARD = oLED[3:0];
//clock generation
parameter CYCLE=10.0;
always #(CYCLE/2.0) CLK = ~CLK;
// Instantiate the Unit Under Test (UUT)
PGM uut(CLK, RESET, MORE, BTN_w, BTN_e, BTN_s, oLED);
initial begin
RESET = 0;
CLK = 0;
MORE = 0;
BTN_w = 0;
BTN_e = 0;
BTN_s = 0;
#50;
RESET = 1;
#20;
RESET = 0;
#20;
BTN_w = 1;
#20;
BTN_w = 0;
#20;
BTN_w = 1;
#20;
BTN_w = 0;
#20;
BTN_e = 1;
#20;
BTN_e = 0;
#20;
BTN_e = 1;
#20;
BTN_e = 0;
#20;
BTN_s = 1;
#20;
BTN_s = 0;
MORE = 2'b01;
#20;
BTN_e = 1;
#20;
BTN_e = 0;
#20;
BTN_s = 1;
#20;
BTN_s = 0;
#20;
BTN_e = 1;
#20;
BTN_e = 0;
#20;
BTN_s = 1;
#20;
BTN_s = 0;
#20;
BTN_e = 1;
#20;
BTN_e = 0;
#20;
BTN_s = 1;
#20;
BTN_s = 0;
#20;
BTN_e = 1;
#20;
BTN_e = 0;
#20;
BTN_s = 1;
#20;
BTN_s = 0;
// Second turn.
#50;
RESET = 1;
#20;
RESET = 0;
#20;
BTN_e = 1;
#20;
BTN_e = 0;
#20;
BTN_w = 1;
#20;
BTN_w = 0;
#20;
BTN_s = 1;
#20;
BTN_s = 0;
MORE = 2'b00;
#20;
BTN_w = 1;
#20;
BTN_w = 0;
end
endmodule |
module bg3_new (
address,
clock,
q);
input [14:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites-new/bg3-new.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32768,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 15,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule |
module uart_fifo
#(parameter TX_RAM_ADDRESS_BITS = 10,
RX_RAM_ADDRESS_BITS = 10)
(input reset,
input sys_clk,
input tx_wren, // When this goes high, there's new data for the fifo
input [7:0] tx_data,
input tx_accept, // UART signals when it can accepted tx data
input [7:0] rx_data,
input rx_data_ready,
input rx_accept, // User signal describes when it accepted rx data
output reg tx_out_wren, // High to tell UART that there's data. UART responds by pulsing tx_accept
output tx_fifo_full,
output reg tx_fifo_ram_wren, // pulled high to write new data into the fifo ram
output reg [7:0] tx_data_out,
output reg [TX_RAM_ADDRESS_BITS-1:0] tx_fifo_ram_read_address,
output reg [TX_RAM_ADDRESS_BITS-1:0] tx_fifo_ram_write_address,
output reg [7:0] rx_data_out,
output reg [RX_RAM_ADDRESS_BITS-1:0] rx_fifo_ram_read_address,
output reg [RX_RAM_ADDRESS_BITS-1:0] rx_fifo_ram_write_address,
output rx_fifo_full,
output reg rx_fifo_ram_wren,
output reg rx_data_out_ready
);
localparam FIFO_TX_SIZE = 1 << TX_RAM_ADDRESS_BITS;
localparam FIFO_RX_SIZE = 1 << RX_RAM_ADDRESS_BITS;
// Ring buffer content usage...need 1 extra bit for when the buffer is full
reg [TX_RAM_ADDRESS_BITS:0] tx_count;
assign tx_fifo_full = (tx_count == FIFO_TX_SIZE);
reg [RX_RAM_ADDRESS_BITS:0] rx_count;
assign rx_fifo_full = (rx_count == FIFO_RX_SIZE);
localparam TX_IDLE=2'd0, TX_WAIT_MEM=2'd1, TX_WAIT_UART=2'd2;
reg [1:0] tx_state;
wire write_tx_ram = tx_wren && ~tx_fifo_full;
reg rx_data_ready_wait;
wire write_rx_ram = rx_data_ready && ~rx_data_ready_wait && ~rx_fifo_full;
localparam RX_IDLE=2'd0, RX_WAIT_MEM1=2'd1, RX_WAIT_MEM2=2'd2, RX_WAIT_ACCEPT=2'd3;
reg [1:0] rx_state;
////////////////////////////////////////////////////////////////////////////////
// TX protocol
always @(posedge sys_clk or posedge reset)
begin
if(reset) begin
tx_fifo_ram_read_address <= {TX_RAM_ADDRESS_BITS{1'b0}};
`ifdef USE_TEST_RAM
tx_count <= FIFO_TX_SIZE;
tx_fifo_ram_write_address <= FIFO_TX_SIZE;
`else
tx_count <= 'b0;
tx_fifo_ram_write_address <= {TX_RAM_ADDRESS_BITS{1'b0}};
`endif
tx_fifo_ram_wren <= 'b0;
tx_data_out <= 8'b0;
tx_out_wren <= 'b0;
tx_state <= TX_IDLE;
end else begin
// Allow a write to memory as long as the fifo isn't full
tx_fifo_ram_wren <= write_tx_ram;
if(write_tx_ram)
tx_data_out <= tx_data;
// write_address will move only after written to it in the last cycle, so tx_fifo_ram_wren is used instead of the write_tx_ram wire
tx_fifo_ram_write_address <= tx_fifo_ram_write_address + (tx_fifo_ram_wren ? 1 : 0);
// tx_count will go down when the UART accepts data, and up when incoming data is received
// this logic allows for both to happen simultaneously:
tx_count <= tx_count + (((tx_state == TX_WAIT_UART) && tx_accept) ? -1 : 0) + ((write_tx_ram) ? 1 : 0);
case(tx_state)
TX_IDLE: begin
// This uses the previous value of tx_count
if((| tx_count) && ~tx_accept) begin
// There's data to send, and rdaddress is already on the line,
// so waiting 1 clock cycle (to make sure RAM is ready) should be good, then flip tx_out_wren high
tx_state <= TX_WAIT_MEM;
end
end
TX_WAIT_MEM: begin
// Byte is on the line, so tell UART it's ready and wait for accept
tx_out_wren <= 1'b1;
tx_state <= TX_WAIT_UART;
end
TX_WAIT_UART: begin
if(tx_accept) begin
tx_out_wren <= 1'b0;
// free up space now that the UART has taken the data
tx_fifo_ram_read_address <= tx_fifo_ram_read_address + 1'b1;
// wait for the UART to be ready again
tx_state <= TX_IDLE;
end
end
default: begin
tx_out_wren <= 1'b0;
tx_state <= TX_IDLE;
end
endcase
end
end
////////////////////////////////////////////////////////////////////////////////
// RX protocol
always @(posedge sys_clk or posedge reset)
begin
if(reset) begin
rx_fifo_ram_read_address <= {RX_RAM_ADDRESS_BITS{1'b0}};
rx_fifo_ram_write_address <= {RX_RAM_ADDRESS_BITS{1'b0}};
rx_count <= 'b0;
rx_fifo_ram_wren <= 'b0;
rx_data_out <= 8'b0;
rx_data_out_ready <= 1'b0;
rx_data_ready_wait <= 1'b0;
rx_state <= RX_IDLE;
end else begin
// Allow a write to memory as long as the fifo isn't full but only once when data_ready is high
rx_fifo_ram_wren <= write_rx_ram;
if(write_rx_ram) begin
rx_data_out <= rx_data;
rx_data_ready_wait <= 1'b1;
end else if(~rx_data_ready && rx_data_ready_wait) begin
rx_data_ready_wait <= 1'b0;
end
// write_address will move only after it was written to it in the last cycle, so rx_fifo_ram_wren is used instead of the write_rx_ram wire
rx_fifo_ram_write_address <= rx_fifo_ram_write_address + (rx_fifo_ram_wren ? 1 : 0);
// rx_count will go down when the user accepts data, and up when UART data is received.
// this logic allows for both to happen simultaneously:
rx_count <= rx_count + (((rx_state == RX_WAIT_ACCEPT) && rx_accept) ? -1 : 0) + ((write_rx_ram) ? 1 : 0);
case(rx_state)
RX_IDLE: begin
if((| rx_count) && ~rx_accept) begin
// read address is already on the line this cycle,
// If the data out of q is being registered, another clock cycle
// must occur, so waiting two cycles seems safer
rx_state <= RX_WAIT_MEM1;
end
end
RX_WAIT_MEM1: begin
rx_state <= RX_WAIT_MEM2;
end
RX_WAIT_MEM2: begin
// data is ready, trigger to user
rx_data_out_ready <= 1'b1;
rx_state <= RX_WAIT_ACCEPT;
end
RX_WAIT_ACCEPT: begin
if(rx_accept) begin
rx_data_out_ready <= 1'b0;
rx_fifo_ram_read_address <= rx_fifo_ram_read_address + 1'b1;
rx_state <= RX_IDLE;
end
end
default: begin
rx_data_out_ready <= 1'b0;
rx_state <= RX_IDLE;
end
endcase
end
end
endmodule |
module hapara_bram_dma_dup_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer DATA_WIDTH = 32
)
(
// Users to add ports here
input [DATA_WIDTH - 1 : 0] addr_ctrl,
input [DATA_WIDTH - 1 : 0] data_in_ctrl,
output [DATA_WIDTH - 1 : 0] data_out_ctrl,
input [DATA_WIDTH / 8 - 1 : 0] we_ctrl,
input clk_ctrl,
input rst_ctrl,
input en_ctrl,
output [DATA_WIDTH - 1 : 0] addr_inst,
output [DATA_WIDTH - 1 : 0] data_in_inst,
input [DATA_WIDTH - 1 : 0] data_out_inst,
output [DATA_WIDTH / 8 - 1 : 0] we_inst,
output clk_inst,
output rst_inst,
output en_inst,
output [DATA_WIDTH - 1 : 0] addr_data,
output [DATA_WIDTH - 1 : 0] data_in_data,
input [DATA_WIDTH - 1 : 0] data_out_data,
output [DATA_WIDTH / 8 - 1 : 0] we_data,
output clk_data,
output rst_data,
output en_data
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
);
// Instantiation of Axi Bus Interface S00_AXI
// Add user logic here
assign clk_inst = clk_ctrl;
assign clk_data = clk_ctrl;
assign rst_inst = rst_ctrl;
assign rst_data = rst_ctrl;
assign we_inst = we_ctrl;
assign we_data = we_ctrl;
assign addr_inst = addr_ctrl;
assign addr_data = addr_ctrl;
assign data_in_inst = data_in_ctrl;
assign data_in_data = data_in_ctrl;
assign en_inst = en_ctrl;
assign en_data = en_ctrl;
assign data_out_ctrl = data_out_data;
// User logic ends
endmodule |
module sfifo_8x16_la (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [7:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [7:0] q;
output [3:0] usedw;
wire [3:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [7:0] sub_wire3;
wire sub_wire4;
wire [3:0] usedw = sub_wire0[3:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [7:0] q = sub_wire3[7:0];
wire almost_full = sub_wire4;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_full (sub_wire4),
.almost_empty (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.almost_full_value = 12,
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 8,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[7:0],probe19[7:0],probe20[0:0],probe21[2:0],probe22[2:0],probe23[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [63:0]probe7;
input [0:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [63:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [7:0]probe18;
input [7:0]probe19;
input [0:0]probe20;
input [2:0]probe21;
input [2:0]probe22;
input [0:0]probe23;
endmodule |
module top(input clk, ce, sr, d, output q);
/*
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b1, IS_CLR_INVERTED=1'b1,
ERROR: [Place 30-1008] Instance ff has an inverted D pin which is expected to be used as an I/O flop.
However, it is used as a regular flop.
cliff didn't have constrained, also got annoyed
he is using slightly later version
ERROR: [Place 30-1008] Instance roi/ffs[0].genblk1.genblk1.ff
has an inverted D pin which is unsupported in the UltraScale and UltraScale+ architectures.
which is fine except...he's using 7 series
and now...
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b0, IS_CLR_INVERTED=1'b1,
ERROR: [Place 30-488] Failed to commit 1 instances:
ff with block Id: 4 (FF) at SLICE_X0Y104
ERROR: [Place 30-99] Placer failed with error: 'failed to commit all instances'
IS_C_INVERTED=1'b0, IS_D_INVERTED=1'b0, IS_CLR_INVERTED=1'b1,
failed with same message
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b0, IS_CLR_INVERTED=1'b0,
built!
diff design_fdce.segd design_fdce_inv.segd
> tag CLBLL_L.SLICEL_X0.CLKINV
expected
IS_C_INVERTED=1'b0, IS_D_INVERTED=1'b1, IS_CLR_INVERTED=1'b0,
ERROR: [Place 30-1008] Instance ff has an inverted D pin which is expected to be used as an I/O flop.
However, it is used as a regular flop.
ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer stopped due to earlier errors.
Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
*/
(*
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b0, IS_CLR_INVERTED=1'b0,
LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH
*)
FDCE ff (
.C(clk),
.CE(ce),
.CLR(sr),
.D(d),
.Q(q)
);
endmodule |
module sky130_fd_sc_hd__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule |
module top();
// Inputs are registered
reg A_N;
reg B_N;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B_N = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B_N = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B_N = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B_N = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B_N = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B_N = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_lp__nand4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule |
module sky130_fd_sc_hs__a211oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
C1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
// Local signals
wire C1 and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule |
module tse_mac2 (
ff_tx_data,
ff_tx_eop,
ff_tx_err,
ff_tx_sop,
ff_tx_wren,
ff_tx_clk,
ff_rx_rdy,
ff_rx_clk,
address,
read,
writedata,
write,
clk,
reset,
mdio_in,
rxp,
ref_clk,
ff_tx_rdy,
ff_rx_data,
ff_rx_dval,
ff_rx_eop,
ff_rx_sop,
rx_err,
readdata,
waitrequest,
mdio_out,
mdio_oen,
mdc,
led_an,
led_char_err,
led_link,
led_disp_err,
led_crs,
led_col,
txp,
rx_recovclkout);
input [7:0] ff_tx_data;
input ff_tx_eop;
input ff_tx_err;
input ff_tx_sop;
input ff_tx_wren;
input ff_tx_clk;
input ff_rx_rdy;
input ff_rx_clk;
input [7:0] address;
input read;
input [31:0] writedata;
input write;
input clk;
input reset;
input mdio_in;
input rxp;
input ref_clk;
output ff_tx_rdy;
output [7:0] ff_rx_data;
output ff_rx_dval;
output ff_rx_eop;
output ff_rx_sop;
output [5:0] rx_err;
output [31:0] readdata;
output waitrequest;
output mdio_out;
output mdio_oen;
output mdc;
output led_an;
output led_char_err;
output led_link;
output led_disp_err;
output led_crs;
output led_col;
output txp;
output rx_recovclkout;
altera_tse_mac_pcs_pma altera_tse_mac_pcs_pma_inst(
.ff_tx_data(ff_tx_data),
.ff_tx_eop(ff_tx_eop),
.ff_tx_err(ff_tx_err),
.ff_tx_sop(ff_tx_sop),
.ff_tx_wren(ff_tx_wren),
.ff_tx_clk(ff_tx_clk),
.ff_rx_rdy(ff_rx_rdy),
.ff_rx_clk(ff_rx_clk),
.address(address),
.read(read),
.writedata(writedata),
.write(write),
.clk(clk),
.reset(reset),
.mdio_in(mdio_in),
.rxp(rxp),
.ref_clk(ref_clk),
.ff_tx_rdy(ff_tx_rdy),
.ff_rx_data(ff_rx_data),
.ff_rx_dval(ff_rx_dval),
.ff_rx_eop(ff_rx_eop),
.ff_rx_sop(ff_rx_sop),
.rx_err(rx_err),
.readdata(readdata),
.waitrequest(waitrequest),
.mdio_out(mdio_out),
.mdio_oen(mdio_oen),
.mdc(mdc),
.led_an(led_an),
.led_char_err(led_char_err),
.led_link(led_link),
.led_disp_err(led_disp_err),
.led_crs(led_crs),
.led_col(led_col),
.txp(txp),
.rx_recovclkout(rx_recovclkout));
defparam
altera_tse_mac_pcs_pma_inst.ENABLE_MAGIC_DETECT = 1,
altera_tse_mac_pcs_pma_inst.ENABLE_MDIO = 1,
altera_tse_mac_pcs_pma_inst.ENABLE_SHIFT16 = 0,
altera_tse_mac_pcs_pma_inst.ENABLE_SUP_ADDR = 1,
altera_tse_mac_pcs_pma_inst.CORE_VERSION = 16'h0b01,
altera_tse_mac_pcs_pma_inst.CRC32GENDELAY = 6,
altera_tse_mac_pcs_pma_inst.MDIO_CLK_DIV = 50,
altera_tse_mac_pcs_pma_inst.ENA_HASH = 1,
altera_tse_mac_pcs_pma_inst.USE_SYNC_RESET = 1,
altera_tse_mac_pcs_pma_inst.STAT_CNT_ENA = 1,
altera_tse_mac_pcs_pma_inst.ENABLE_EXTENDED_STAT_REG = 0,
altera_tse_mac_pcs_pma_inst.ENABLE_HD_LOGIC = 1,
altera_tse_mac_pcs_pma_inst.REDUCED_INTERFACE_ENA = 0,
altera_tse_mac_pcs_pma_inst.CRC32S1L2_EXTERN = 0,
altera_tse_mac_pcs_pma_inst.ENABLE_GMII_LOOPBACK = 0,
altera_tse_mac_pcs_pma_inst.CRC32DWIDTH = 8,
altera_tse_mac_pcs_pma_inst.CUST_VERSION = 0,
altera_tse_mac_pcs_pma_inst.RESET_LEVEL = 8'h01,
altera_tse_mac_pcs_pma_inst.CRC32CHECK16BIT = 8'h00,
altera_tse_mac_pcs_pma_inst.ENABLE_MAC_FLOW_CTRL = 1,
altera_tse_mac_pcs_pma_inst.ENABLE_MAC_TXADDR_SET = 1,
altera_tse_mac_pcs_pma_inst.ENABLE_MAC_RX_VLAN = 1,
altera_tse_mac_pcs_pma_inst.ENABLE_MAC_TX_VLAN = 1,
altera_tse_mac_pcs_pma_inst.SYNCHRONIZER_DEPTH = 4,
altera_tse_mac_pcs_pma_inst.EG_FIFO = 2048,
altera_tse_mac_pcs_pma_inst.EG_ADDR = 11,
altera_tse_mac_pcs_pma_inst.ING_FIFO = 2048,
altera_tse_mac_pcs_pma_inst.ENABLE_ENA = 8,
altera_tse_mac_pcs_pma_inst.ING_ADDR = 11,
altera_tse_mac_pcs_pma_inst.RAM_TYPE = "AUTO",
altera_tse_mac_pcs_pma_inst.INSERT_TA = 1,
altera_tse_mac_pcs_pma_inst.ENABLE_MACLITE = 0,
altera_tse_mac_pcs_pma_inst.MACLITE_GIGE = 0,
altera_tse_mac_pcs_pma_inst.PHY_IDENTIFIER = 32'h00000000,
altera_tse_mac_pcs_pma_inst.DEV_VERSION = 16'h0b01,
altera_tse_mac_pcs_pma_inst.ENABLE_SGMII = 1,
altera_tse_mac_pcs_pma_inst.DEVICE_FAMILY = "STRATIXIV",
altera_tse_mac_pcs_pma_inst.EXPORT_PWRDN = 0,
altera_tse_mac_pcs_pma_inst.TRANSCEIVER_OPTION = 1,
altera_tse_mac_pcs_pma_inst.ENABLE_ALT_RECONFIG = 0;
endmodule |
module mig_wrap_proc_sys_reset_0_0
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) input mb_debug_sys_rst;
input dcm_locked;
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) output mb_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) output [0:0]bus_struct_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) output [0:0]peripheral_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) output [0:0]interconnect_aresetn;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) output [0:0]peripheral_aresetn;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* C_AUX_RESET_HIGH = "1'b0" *)
(* C_AUX_RST_WIDTH = "4" *)
(* C_EXT_RESET_HIGH = "1'b1" *)
(* C_EXT_RST_WIDTH = "4" *)
(* C_FAMILY = "artix7" *)
(* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
(* C_NUM_PERP_ARESETN = "1" *)
(* C_NUM_PERP_RST = "1" *)
mig_wrap_proc_sys_reset_0_0_proc_sys_reset U0
(.aux_reset_in(aux_reset_in),
.bus_struct_reset(bus_struct_reset),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.interconnect_aresetn(interconnect_aresetn),
.mb_debug_sys_rst(mb_debug_sys_rst),
.mb_reset(mb_reset),
.peripheral_aresetn(peripheral_aresetn),
.peripheral_reset(peripheral_reset),
.slowest_sync_clk(slowest_sync_clk));
endmodule |
module mig_wrap_proc_sys_reset_0_0_cdc_sync
(lpf_exr_reg,
scndry_out,
ext_reset_in,
mb_debug_sys_rst,
lpf_exr,
p_3_out,
slowest_sync_clk);
output lpf_exr_reg;
output scndry_out;
input ext_reset_in;
input mb_debug_sys_rst;
input lpf_exr;
input [2:0]p_3_out;
input slowest_sync_clk;
wire exr_d1;
wire ext_reset_in;
wire lpf_exr;
wire lpf_exr_reg;
wire mb_debug_sys_rst;
wire [2:0]p_3_out;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(exr_d1),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT2 #(
.INIT(4'hE))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
(.I0(ext_reset_in),
.I1(mb_debug_sys_rst),
.O(exr_d1));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_exr_i_1
(.I0(lpf_exr),
.I1(p_3_out[0]),
.I2(scndry_out),
.I3(p_3_out[1]),
.I4(p_3_out[2]),
.O(lpf_exr_reg));
endmodule |
module mig_wrap_proc_sys_reset_0_0_cdc_sync_0
(lpf_asr_reg,
scndry_out,
aux_reset_in,
lpf_asr,
asr_lpf,
p_1_in,
p_2_in,
slowest_sync_clk);
output lpf_asr_reg;
output scndry_out;
input aux_reset_in;
input lpf_asr;
input [0:0]asr_lpf;
input p_1_in;
input p_2_in;
input slowest_sync_clk;
wire asr_d1;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire lpf_asr;
wire lpf_asr_reg;
wire p_1_in;
wire p_2_in;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(asr_d1),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
(.I0(aux_reset_in),
.O(asr_d1));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_asr_i_1
(.I0(lpf_asr),
.I1(asr_lpf),
.I2(scndry_out),
.I3(p_1_in),
.I4(p_2_in),
.O(lpf_asr_reg));
endmodule |
module mig_wrap_proc_sys_reset_0_0_lpf
(lpf_int,
slowest_sync_clk,
dcm_locked,
ext_reset_in,
mb_debug_sys_rst,
aux_reset_in);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input ext_reset_in;
input mb_debug_sys_rst;
input aux_reset_in;
wire \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0 ;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
wire Q;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire dcm_locked;
wire ext_reset_in;
wire lpf_asr;
wire lpf_exr;
wire lpf_int;
wire lpf_int0__0;
wire mb_debug_sys_rst;
wire p_1_in;
wire p_2_in;
wire p_3_in1_in;
wire [3:0]p_3_out;
wire slowest_sync_clk;
mig_wrap_proc_sys_reset_0_0_cdc_sync \ACTIVE_HIGH_EXT.ACT_HI_EXT
(.ext_reset_in(ext_reset_in),
.lpf_exr(lpf_exr),
.lpf_exr_reg(\ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0 ),
.mb_debug_sys_rst(mb_debug_sys_rst),
.p_3_out(p_3_out[2:0]),
.scndry_out(p_3_out[3]),
.slowest_sync_clk(slowest_sync_clk));
mig_wrap_proc_sys_reset_0_0_cdc_sync_0 \ACTIVE_LOW_AUX.ACT_LO_AUX
(.asr_lpf(asr_lpf),
.aux_reset_in(aux_reset_in),
.lpf_asr(lpf_asr),
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.p_1_in(p_1_in),
.p_2_in(p_2_in),
.scndry_out(p_3_in1_in),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
\AUX_LPF[1].asr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_in1_in),
.Q(p_2_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[2].asr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_2_in),
.Q(p_1_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[3].asr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_1_in),
.Q(asr_lpf),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[1].exr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[3]),
.Q(p_3_out[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[2].exr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(p_3_out[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[3].exr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[1]),
.Q(p_3_out[0]),
.R(1'b0));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "SRL16" *)
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
SRL16E #(
.INIT(16'hFFFF))
POR_SRL_I
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(1'b1),
.CLK(slowest_sync_clk),
.D(1'b0),
.Q(Q));
FDRE #(
.INIT(1'b0))
lpf_asr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.Q(lpf_asr),
.R(1'b0));
FDRE #(
.INIT(1'b0))
lpf_exr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0 ),
.Q(lpf_exr),
.R(1'b0));
LUT4 #(
.INIT(16'hFFEF))
lpf_int0
(.I0(Q),
.I1(lpf_asr),
.I2(dcm_locked),
.I3(lpf_exr),
.O(lpf_int0__0));
FDRE #(
.INIT(1'b0))
lpf_int_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(lpf_int0__0),
.Q(lpf_int),
.R(1'b0));
endmodule |
module mig_wrap_proc_sys_reset_0_0_proc_sys_reset
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
(* equivalent_register_removal = "no" *) output [0:0]bus_struct_reset;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_reset;
(* equivalent_register_removal = "no" *) output [0:0]interconnect_aresetn;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_aresetn;
wire Core;
wire SEQ_n_3;
wire SEQ_n_4;
wire aux_reset_in;
wire bsr;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire lpf_int;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire pr;
wire slowest_sync_clk;
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_3),
.Q(interconnect_aresetn),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_4),
.Q(peripheral_aresetn),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr),
.Q(bus_struct_reset),
.R(1'b0));
mig_wrap_proc_sys_reset_0_0_lpf EXT_LPF
(.aux_reset_in(aux_reset_in),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.lpf_int(lpf_int),
.mb_debug_sys_rst(mb_debug_sys_rst),
.slowest_sync_clk(slowest_sync_clk));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\PR_OUT_DFF[0].peripheral_reset_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr),
.Q(peripheral_reset),
.R(1'b0));
mig_wrap_proc_sys_reset_0_0_sequence_psr SEQ
(.\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] (SEQ_n_3),
.\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] (SEQ_n_4),
.Core(Core),
.bsr(bsr),
.lpf_int(lpf_int),
.pr(pr),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
mb_reset_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core),
.Q(mb_reset),
.R(1'b0));
endmodule |
module mig_wrap_proc_sys_reset_0_0_sequence_psr
(Core,
bsr,
pr,
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ,
lpf_int,
slowest_sync_clk);
output Core;
output bsr;
output pr;
output \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ;
output \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ;
input lpf_int;
input slowest_sync_clk;
wire \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ;
wire \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ;
wire Core;
wire Core_i_1_n_0;
wire bsr;
wire \bsr_dec_reg_n_0_[0] ;
wire \bsr_dec_reg_n_0_[2] ;
wire bsr_i_1_n_0;
wire \core_dec[0]_i_1_n_0 ;
wire \core_dec[2]_i_1_n_0 ;
wire \core_dec_reg_n_0_[0] ;
wire \core_dec_reg_n_0_[1] ;
wire from_sys_i_1_n_0;
wire lpf_int;
wire p_0_in;
wire [2:0]p_3_out;
wire [2:0]p_5_out;
wire pr;
wire pr_dec0__0;
wire \pr_dec_reg_n_0_[0] ;
wire \pr_dec_reg_n_0_[2] ;
wire pr_i_1_n_0;
wire seq_clr;
wire [5:0]seq_cnt;
wire seq_cnt_en;
wire slowest_sync_clk;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1
(.I0(bsr),
.O(\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1
(.I0(pr),
.O(\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
Core_i_1
(.I0(Core),
.I1(p_0_in),
.O(Core_i_1_n_0));
FDSE #(
.INIT(1'b0))
Core_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core_i_1_n_0),
.Q(Core),
.S(lpf_int));
mig_wrap_proc_sys_reset_0_0_upcnt_n SEQ_COUNTER
(.Q(seq_cnt),
.seq_clr(seq_clr),
.seq_cnt_en(seq_cnt_en),
.slowest_sync_clk(slowest_sync_clk));
LUT4 #(
.INIT(16'h0804))
\bsr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt[4]),
.O(p_5_out[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\bsr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\bsr_dec_reg_n_0_[0] ),
.O(p_5_out[2]));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[0]),
.Q(\bsr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[2]),
.Q(\bsr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
bsr_i_1
(.I0(bsr),
.I1(\bsr_dec_reg_n_0_[2] ),
.O(bsr_i_1_n_0));
FDSE #(
.INIT(1'b0))
bsr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr_i_1_n_0),
.Q(bsr),
.S(lpf_int));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h8040))
\core_dec[0]_i_1
(.I0(seq_cnt[4]),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt_en),
.O(\core_dec[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\core_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\core_dec_reg_n_0_[0] ),
.O(\core_dec[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\core_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[0]_i_1_n_0 ),
.Q(\core_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_dec0__0),
.Q(\core_dec_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[2]_i_1_n_0 ),
.Q(p_0_in),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
from_sys_i_1
(.I0(Core),
.I1(seq_cnt_en),
.O(from_sys_i_1_n_0));
FDSE #(
.INIT(1'b0))
from_sys_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(from_sys_i_1_n_0),
.Q(seq_cnt_en),
.S(lpf_int));
LUT4 #(
.INIT(16'h0210))
pr_dec0
(.I0(seq_cnt[0]),
.I1(seq_cnt[1]),
.I2(seq_cnt[2]),
.I3(seq_cnt_en),
.O(pr_dec0__0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h1080))
\pr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[5]),
.I2(seq_cnt[3]),
.I3(seq_cnt[4]),
.O(p_3_out[0]));
LUT2 #(
.INIT(4'h8))
\pr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\pr_dec_reg_n_0_[0] ),
.O(p_3_out[2]));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[0]),
.Q(\pr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(\pr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
pr_i_1
(.I0(pr),
.I1(\pr_dec_reg_n_0_[2] ),
.O(pr_i_1_n_0));
FDSE #(
.INIT(1'b0))
pr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_i_1_n_0),
.Q(pr),
.S(lpf_int));
FDRE #(
.INIT(1'b0))
seq_clr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(1'b1),
.Q(seq_clr),
.R(lpf_int));
endmodule |
module mig_wrap_proc_sys_reset_0_0_upcnt_n
(Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk);
output [5:0]Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0]Q;
wire clear;
wire [5:0]q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h1))
\q_int[0]_i_1
(.I0(Q[0]),
.O(q_int0[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\q_int[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(q_int0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\q_int[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(q_int0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\q_int[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(q_int0[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\q_int[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(q_int0[4]));
LUT1 #(
.INIT(2'h1))
\q_int[5]_i_1
(.I0(seq_clr),
.O(clear));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\q_int[5]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(q_int0[5]));
FDRE #(
.INIT(1'b1))
\q_int_reg[0]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[0]),
.Q(Q[0]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[1]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[1]),
.Q(Q[1]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[2]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[2]),
.Q(Q[2]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[3]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[3]),
.Q(Q[3]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[4]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[4]),
.Q(Q[4]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[5]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[5]),
.Q(Q[5]),
.R(clear));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module design_1_processing_system7_0_0 (
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output wire TTC0_WAVE0_OUT;
output wire TTC0_WAVE1_OUT;
output wire TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *)
output wire [1 : 0] USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *)
output wire USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *)
input wire USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
output wire M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
output wire M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
output wire M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
output wire M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
output wire M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
output wire M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
output wire [11 : 0] M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
output wire [11 : 0] M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
output wire [11 : 0] M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
output wire [1 : 0] M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
output wire [1 : 0] M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
output wire [2 : 0] M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
output wire [1 : 0] M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
output wire [1 : 0] M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
output wire [2 : 0] M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
output wire [2 : 0] M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
output wire [2 : 0] M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
output wire [31 : 0] M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
output wire [31 : 0] M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
output wire [31 : 0] M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
output wire [3 : 0] M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
output wire [3 : 0] M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
output wire [3 : 0] M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
output wire [3 : 0] M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
output wire [3 : 0] M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
output wire [3 : 0] M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
output wire [3 : 0] M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
input wire M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
input wire M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
input wire M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
input wire M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
input wire M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
input wire M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
input wire M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
input wire [11 : 0] M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
input wire [11 : 0] M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
input wire [1 : 0] M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
input wire [1 : 0] M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
input wire [31 : 0] M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARREADY" *)
output wire S_AXI_HP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWREADY" *)
output wire S_AXI_HP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BVALID" *)
output wire S_AXI_HP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RLAST" *)
output wire S_AXI_HP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RVALID" *)
output wire S_AXI_HP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WREADY" *)
output wire S_AXI_HP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BRESP" *)
output wire [1 : 0] S_AXI_HP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RRESP" *)
output wire [1 : 0] S_AXI_HP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BID" *)
output wire [5 : 0] S_AXI_HP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RID" *)
output wire [5 : 0] S_AXI_HP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RDATA" *)
output wire [63 : 0] S_AXI_HP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RCOUNT" *)
output wire [7 : 0] S_AXI_HP0_RCOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WCOUNT" *)
output wire [7 : 0] S_AXI_HP0_WCOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RACOUNT" *)
output wire [2 : 0] S_AXI_HP0_RACOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WACOUNT" *)
output wire [5 : 0] S_AXI_HP0_WACOUNT;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXI_HP0_ACLK CLK" *)
input wire S_AXI_HP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARVALID" *)
input wire S_AXI_HP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWVALID" *)
input wire S_AXI_HP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BREADY" *)
input wire S_AXI_HP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RDISSUECAPEN" *)
input wire S_AXI_HP0_RDISSUECAP1_EN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RREADY" *)
input wire S_AXI_HP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WLAST" *)
input wire S_AXI_HP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WRISSUECAPEN" *)
input wire S_AXI_HP0_WRISSUECAP1_EN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WVALID" *)
input wire S_AXI_HP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARBURST" *)
input wire [1 : 0] S_AXI_HP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLOCK" *)
input wire [1 : 0] S_AXI_HP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARSIZE" *)
input wire [2 : 0] S_AXI_HP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWBURST" *)
input wire [1 : 0] S_AXI_HP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLOCK" *)
input wire [1 : 0] S_AXI_HP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWSIZE" *)
input wire [2 : 0] S_AXI_HP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARPROT" *)
input wire [2 : 0] S_AXI_HP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWPROT" *)
input wire [2 : 0] S_AXI_HP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARADDR" *)
input wire [31 : 0] S_AXI_HP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWADDR" *)
input wire [31 : 0] S_AXI_HP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARCACHE" *)
input wire [3 : 0] S_AXI_HP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLEN" *)
input wire [3 : 0] S_AXI_HP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARQOS" *)
input wire [3 : 0] S_AXI_HP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWCACHE" *)
input wire [3 : 0] S_AXI_HP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLEN" *)
input wire [3 : 0] S_AXI_HP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWQOS" *)
input wire [3 : 0] S_AXI_HP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARID" *)
input wire [5 : 0] S_AXI_HP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWID" *)
input wire [5 : 0] S_AXI_HP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WID" *)
input wire [5 : 0] S_AXI_HP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WDATA" *)
input wire [63 : 0] S_AXI_HP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WSTRB" *)
input wire [7 : 0] S_AXI_HP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(1),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_USE_AXI_NONSECURE(0),
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_HP0(1),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_USE_S_AXI_ACP(0),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("true"),
.C_FCLK_CLK1_BUF("false"),
.C_FCLK_CLK2_BUF("false"),
.C_FCLK_CLK3_BUF("false"),
.C_PACKAGE_NAME("clg484")
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(),
.ENET0_PTP_DELAY_REQ_TX(),
.ENET0_PTP_PDELAY_REQ_RX(),
.ENET0_PTP_PDELAY_REQ_TX(),
.ENET0_PTP_PDELAY_RESP_RX(),
.ENET0_PTP_PDELAY_RESP_TX(),
.ENET0_PTP_SYNC_FRAME_RX(),
.ENET0_PTP_SYNC_FRAME_TX(),
.ENET0_SOF_RX(),
.ENET0_SOF_TX(),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(1'B0),
.I2C0_SDA_O(),
.I2C0_SDA_T(),
.I2C0_SCL_I(1'B0),
.I2C0_SCL_O(),
.I2C0_SCL_T(),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(1'B0),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY),
.S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY),
.S_AXI_HP0_BVALID(S_AXI_HP0_BVALID),
.S_AXI_HP0_RLAST(S_AXI_HP0_RLAST),
.S_AXI_HP0_RVALID(S_AXI_HP0_RVALID),
.S_AXI_HP0_WREADY(S_AXI_HP0_WREADY),
.S_AXI_HP0_BRESP(S_AXI_HP0_BRESP),
.S_AXI_HP0_RRESP(S_AXI_HP0_RRESP),
.S_AXI_HP0_BID(S_AXI_HP0_BID),
.S_AXI_HP0_RID(S_AXI_HP0_RID),
.S_AXI_HP0_RDATA(S_AXI_HP0_RDATA),
.S_AXI_HP0_RCOUNT(S_AXI_HP0_RCOUNT),
.S_AXI_HP0_WCOUNT(S_AXI_HP0_WCOUNT),
.S_AXI_HP0_RACOUNT(S_AXI_HP0_RACOUNT),
.S_AXI_HP0_WACOUNT(S_AXI_HP0_WACOUNT),
.S_AXI_HP0_ACLK(S_AXI_HP0_ACLK),
.S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID),
.S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID),
.S_AXI_HP0_BREADY(S_AXI_HP0_BREADY),
.S_AXI_HP0_RDISSUECAP1_EN(S_AXI_HP0_RDISSUECAP1_EN),
.S_AXI_HP0_RREADY(S_AXI_HP0_RREADY),
.S_AXI_HP0_WLAST(S_AXI_HP0_WLAST),
.S_AXI_HP0_WRISSUECAP1_EN(S_AXI_HP0_WRISSUECAP1_EN),
.S_AXI_HP0_WVALID(S_AXI_HP0_WVALID),
.S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST),
.S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK),
.S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE),
.S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST),
.S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK),
.S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE),
.S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT),
.S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT),
.S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR),
.S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR),
.S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE),
.S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN),
.S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS),
.S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE),
.S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN),
.S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS),
.S_AXI_HP0_ARID(S_AXI_HP0_ARID),
.S_AXI_HP0_AWID(S_AXI_HP0_AWID),
.S_AXI_HP0_WID(S_AXI_HP0_WID),
.S_AXI_HP0_WDATA(S_AXI_HP0_WDATA),
.S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(1'B0),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule |
module cheat(
input clk,
input [7:0] SNES_PA,
input [23:0] SNES_ADDR,
input [7:0] SNES_DATA,
input SNES_wr_strobe,
input SNES_rd_strobe,
input SNES_reset_strobe,
input snescmd_enable,
input nmicmd_enable,
input return_vector_enable,
input reset_vector_enable,
input branch1_enable,
input branch2_enable,
input pad_latch,
input snes_ajr,
input SNES_cycle_start,
input [2:0] pgm_idx,
input pgm_we,
input [31:0] pgm_in,
output [7:0] data_out,
output cheat_hit,
output snescmd_unlock
);
//`define IRQ_HOOK_ENABLE
wire snescmd_wr_strobe = snescmd_enable & SNES_wr_strobe;
reg cheat_enable = 0;
reg nmi_enable = 0;
reg irq_enable = 0;
reg holdoff_enable = 0; // temp disable hooks after reset
reg buttons_enable = 0;
reg wram_present = 0;
wire branch_wram = cheat_enable & wram_present;
reg auto_nmi_enable = 1;
reg auto_nmi_enable_sync = 0;
`ifdef IRQ_HOOK_ENABLE
reg auto_irq_enable = 0;
reg auto_irq_enable_sync = 0;
`endif
reg hook_enable_sync = 0;
reg [1:0] sync_delay = 2'b10;
reg [4:0] nmi_usage = 5'h00;
`ifdef IRQ_HOOK_ENABLE
reg [4:0] irq_usage = 5'h00;
`endif
reg [20:0] usage_count = 21'h1fffff;
reg [29:0] hook_enable_count = 0;
reg hook_disable = 0;
reg [1:0] vector_unlock_r = 0;
wire vector_unlock = |vector_unlock_r;
reg [1:0] reset_unlock_r = 2'b10;
wire reset_unlock = |reset_unlock_r;
reg [23:0] cheat_addr[5:0];
reg [7:0] cheat_data[5:0];
reg [5:0] cheat_enable_mask;
reg snescmd_unlock_r = 0;
assign snescmd_unlock = snescmd_unlock_r;
reg [7:0] nmicmd = 0;
reg [7:0] return_vector = 8'hea;
reg [7:0] branch1_offset = 8'h00;
reg [7:0] branch2_offset = 8'h00;
reg [15:0] pad_data = 0;
wire [5:0] cheat_match_bits ={(cheat_enable_mask[5] & (SNES_ADDR == cheat_addr[5])),
(cheat_enable_mask[4] & (SNES_ADDR == cheat_addr[4])),
(cheat_enable_mask[3] & (SNES_ADDR == cheat_addr[3])),
(cheat_enable_mask[2] & (SNES_ADDR == cheat_addr[2])),
(cheat_enable_mask[1] & (SNES_ADDR == cheat_addr[1])),
(cheat_enable_mask[0] & (SNES_ADDR == cheat_addr[0]))};
wire cheat_addr_match = |cheat_match_bits;
wire [1:0] nmi_match_bits = {SNES_ADDR == 24'h00FFEA, SNES_ADDR == 24'h00FFEB};
`ifdef IRQ_HOOK_ENABLE
wire [1:0] irq_match_bits = {SNES_ADDR == 24'h00FFEE, SNES_ADDR == 24'h00FFEF};
`endif
wire [1:0] rst_match_bits = {SNES_ADDR == 24'h00FFFC, SNES_ADDR == 24'h00FFFD};
wire nmi_addr_match = |nmi_match_bits;
`ifdef IRQ_HOOK_ENABLE
wire irq_addr_match = |irq_match_bits;
`endif
wire rst_addr_match = |rst_match_bits;
wire hook_enable = ~|hook_enable_count;
assign data_out = cheat_match_bits[0] ? cheat_data[0]
: cheat_match_bits[1] ? cheat_data[1]
: cheat_match_bits[2] ? cheat_data[2]
: cheat_match_bits[3] ? cheat_data[3]
: cheat_match_bits[4] ? cheat_data[4]
: cheat_match_bits[5] ? cheat_data[5]
: nmi_match_bits[1] ? 8'h04
`ifdef IRQ_HOOK_ENABLE
: irq_match_bits[1] ? 8'h04
`endif
: rst_match_bits[1] ? 8'h6b
: nmicmd_enable ? nmicmd
: return_vector_enable ? return_vector
: branch1_enable ? branch1_offset
: branch2_enable ? branch2_offset
: 8'h2a;
assign cheat_hit = (snescmd_unlock & hook_enable_sync & (nmicmd_enable | return_vector_enable | branch1_enable | branch2_enable))
| (reset_unlock & rst_addr_match)
| (cheat_enable & cheat_addr_match)
| (hook_enable_sync & (((auto_nmi_enable_sync & nmi_enable) & nmi_addr_match & vector_unlock)
`ifdef IRQ_HOOK_ENABLE
|((auto_irq_enable_sync & irq_enable) & irq_addr_match & vector_unlock)
`endif
));
// irq/nmi detect based on CPU access pattern
// 4 writes (mirrored to B bus) signify that the CPU pushes PB, PC and
// SR to the stack and is going to read the vector address in the next
// two cycles.
// B bus mirror is used (combined with A BUS /WR!) so the write pattern
// cannot be confused with backwards DMA transfers.
reg [7:0] next_pa_addr = 0;
reg [2:0] cpu_push_cnt = 0;
always @(posedge clk) begin
if(SNES_reset_strobe) begin
cpu_push_cnt <= 0;
end else if(SNES_wr_strobe) begin
cpu_push_cnt <= cpu_push_cnt + 1;
if(cpu_push_cnt == 3'b0) begin
next_pa_addr <= SNES_PA - 1;
end else begin
if(SNES_PA == next_pa_addr) begin
next_pa_addr <= next_pa_addr - 1;
end else begin
cpu_push_cnt <= 3'b0;
end
end
end else if(SNES_rd_strobe) begin
cpu_push_cnt <= 3'b0;
end
end
// make patched vectors visible for last cycles of NMI/IRQ handling only
always @(posedge clk) begin
if(SNES_reset_strobe) begin
vector_unlock_r <= 2'b00;
end else if(SNES_rd_strobe) begin
if(hook_enable_sync
& ((auto_nmi_enable_sync & nmi_enable & nmi_match_bits[1])
`ifdef IRQ_HOOK_ENABLE
|(auto_irq_enable_sync & irq_enable & irq_match_bits[1])
`endif
)
& cpu_push_cnt == 4) begin
vector_unlock_r <= 2'b11;
end else if(|vector_unlock_r) begin
vector_unlock_r <= vector_unlock_r - 1;
end
end
end
// make patched reset vector visible for first fetch only
// (including masked read by Ultra16)
always @(posedge clk) begin
if(SNES_reset_strobe) begin
reset_unlock_r <= 2'b11;
end else if(SNES_cycle_start) begin
if(rst_addr_match & |reset_unlock_r) begin
reset_unlock_r <= reset_unlock_r - 1;
end
end
end
reg snescmd_unlock_disable_strobe = 1'b0;
reg [6:0] snescmd_unlock_disable_countdown = 0;
reg snescmd_unlock_disable = 0;
always @(posedge clk) begin
if(SNES_reset_strobe) begin
snescmd_unlock_r <= 0;
snescmd_unlock_disable <= 0;
end else begin
if(SNES_rd_strobe) begin
if(hook_enable_sync
& ((auto_nmi_enable_sync & nmi_enable & nmi_match_bits[1])
`ifdef IRQ_HOOK_ENABLE
|(auto_irq_enable_sync & irq_enable & irq_match_bits[1])
`endif
)
& cpu_push_cnt == 4) begin
// remember where we came from (IRQ/NMI) for hook exit
return_vector <= SNES_ADDR[7:0];
snescmd_unlock_r <= 1;
end
if(rst_match_bits[1] & |reset_unlock_r) begin
snescmd_unlock_r <= 1;
end
end
// give some time to exit snescmd memory and jump to original vector
if(SNES_cycle_start) begin
if(snescmd_unlock_disable) begin
if(|snescmd_unlock_disable_countdown) begin
snescmd_unlock_disable_countdown <= snescmd_unlock_disable_countdown - 1;
end else if(snescmd_unlock_disable_countdown == 0) begin
snescmd_unlock_r <= 0;
snescmd_unlock_disable <= 0;
end
end
end
if(snescmd_unlock_disable_strobe) begin
snescmd_unlock_disable_countdown <= 7'd72;
snescmd_unlock_disable <= 1;
end
end
end
always @(posedge clk) usage_count <= usage_count - 1;
// Try and autoselect NMI or IRQ hook
always @(posedge clk) begin
if(usage_count == 21'b0) begin
nmi_usage <= SNES_cycle_start & nmi_match_bits[1];
`ifdef IRQ_HOOK_ENABLE
irq_usage <= SNES_cycle_start & irq_match_bits[1];
`endif
`ifdef IRQ_HOOK_ENABLE
if(|nmi_usage & |irq_usage) begin
auto_nmi_enable <= 1'b1;
auto_irq_enable <= 1'b0;
end else if(irq_usage == 5'b0) begin
auto_nmi_enable <= 1'b1;
auto_irq_enable <= 1'b0;
end else if(nmi_usage == 5'b0) begin
auto_nmi_enable <= 1'b0;
auto_irq_enable <= 1'b1;
end
`else
auto_nmi_enable <= |nmi_usage;
`endif
end else begin
if(SNES_cycle_start & nmi_match_bits[0]) nmi_usage <= nmi_usage + 1;
`ifdef IRQ_HOOK_ENABLE
if(SNES_cycle_start & irq_match_bits[0]) irq_usage <= irq_usage + 1;
`endif
end
end
// Do not change vectors while they are being read
always @(posedge clk) begin
if(SNES_cycle_start) begin
if(nmi_addr_match
`ifdef IRQ_HOOK_ENABLE
| irq_addr_match
`endif
) sync_delay <= 2'b10;
else begin
if (|sync_delay) sync_delay <= sync_delay - 1;
if (sync_delay == 2'b00) begin
auto_nmi_enable_sync <= auto_nmi_enable;
`ifdef IRQ_HOOK_ENABLE
auto_irq_enable_sync <= auto_irq_enable;
`endif
hook_enable_sync <= hook_enable;
end
end
end
end
// CMD 0x85: disable hooks for 10 seconds
always @(posedge clk) begin
if((snescmd_unlock & snescmd_wr_strobe & ~|SNES_ADDR[8:0] & (SNES_DATA == 8'h85))
| (holdoff_enable & SNES_reset_strobe)) begin
hook_enable_count <= 30'd960000000;
end else if (|hook_enable_count) begin
hook_enable_count <= hook_enable_count - 1;
end
end
always @(posedge clk) begin
if(SNES_reset_strobe) begin
snescmd_unlock_disable_strobe <= 1'b0;
end else begin
snescmd_unlock_disable_strobe <= 1'b0;
if(snescmd_unlock & snescmd_wr_strobe) begin
if(~|SNES_ADDR[8:0]) begin
case(SNES_DATA)
8'h82: cheat_enable <= 1;
8'h83: cheat_enable <= 0;
8'h84: {nmi_enable, irq_enable} <= 2'b00;
endcase
end else if(SNES_ADDR[8:0] == 9'h1fd) begin
snescmd_unlock_disable_strobe <= 1'b1;
end
end else if(pgm_we) begin
if(pgm_idx < 6) begin
cheat_addr[pgm_idx] <= pgm_in[31:8];
cheat_data[pgm_idx] <= pgm_in[7:0];
end else if(pgm_idx == 6) begin // set rom patch enable
cheat_enable_mask <= pgm_in[5:0];
end else if(pgm_idx == 7) begin // set/reset global enable / hooks
// pgm_in[7:4] are reset bit flags
// pgm_in[3:0] are set bit flags
{wram_present, buttons_enable, holdoff_enable, irq_enable, nmi_enable, cheat_enable}
<= ({wram_present, buttons_enable, holdoff_enable, irq_enable, nmi_enable, cheat_enable}
& ~pgm_in[13:8])
| pgm_in[5:0];
end
end
end
end
// map controller input to cmd output
// check button combinations
// L+R+Start+Select : $3030
// L+R+Select+X : $2070
// L+R+Start+A : $10b0
// L+R+Start+B : $9030
// L+R+Start+Y : $5030
// L+R+Start+X : $1070
always @(posedge clk) begin
if(snescmd_wr_strobe) begin
if(SNES_ADDR[8:0] == 9'h1f0) begin
pad_data[7:0] <= SNES_DATA;
end else if(SNES_ADDR[8:0] == 9'h1f1) begin
pad_data[15:8] <= SNES_DATA;
end
end
end
always @* begin
case(pad_data)
16'h3030: nmicmd = 8'h80;
16'h2070: nmicmd = 8'h81;
16'h10b0: nmicmd = 8'h82;
16'h9030: nmicmd = 8'h83;
16'h5030: nmicmd = 8'h84;
16'h1070: nmicmd = 8'h85;
default: nmicmd = 8'h00;
endcase
end
always @* begin
if(buttons_enable) begin
if(snes_ajr) begin
if(nmicmd) begin
branch1_offset = 8'h30; // nmi_echocmd
end else begin
if(branch_wram) begin
branch1_offset = 8'h3a; // nmi_patches
end else begin
branch1_offset = 8'h3d; // nmi_exit
end
end
end else begin
if(pad_latch) begin
if(branch_wram) begin
branch1_offset = 8'h3a; // nmi_patches
end else begin
branch1_offset = 8'h3d; // nmi_exit
end
end else begin
branch1_offset = 8'h00; // continue with MJR
end
end
end else begin
if(branch_wram) begin
branch1_offset = 8'h3a; // nmi_patches
end else begin
branch1_offset = 8'h3d; // nmi_exit
end
end
end
always @* begin
if(nmicmd == 8'h81) begin
branch2_offset = 8'h0e; // nmi_stop
end else if(branch_wram) begin
branch2_offset = 8'h00; // nmi_patches
end else begin
branch2_offset = 8'h03; // nmi_exit
end
end
endmodule |
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg A4;
reg B1;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
A4 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 A4 = 1'b0;
#100 B1 = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 A4 = 1'b1;
#240 B1 = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 A3 = 1'b0;
#360 A4 = 1'b0;
#380 B1 = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 B1 = 1'b1;
#500 A4 = 1'b1;
#520 A3 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 B1 = 1'bx;
#640 A4 = 1'bx;
#660 A3 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hs__o41ai dut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule |
module ps2 (
// Wishbone slave interface
input wb_clk_i, // Clock Input
input wb_rst_i, // Reset Input
input [15:0] wb_dat_i, // Command to send to mouse
output [15:0] wb_dat_o, // Received data
input wb_cyc_i, // Cycle
input wb_stb_i, // Strobe
input [ 2:1] wb_adr_i, // Wishbone address lines
input [ 1:0] wb_sel_i, // Wishbone Select lines
input wb_we_i, // Write enable
output wb_ack_o, // Normal bus termination
output wb_tgk_o, // Interrupt request
output wb_tgm_o, // Interrupt request
input ps2_kbd_clk_, // PS2 Keyboard Clock, Bidirectional
inout ps2_kbd_dat_, // PS2 Keyboard Data, Bidirectional
inout ps2_mse_clk_, // PS2 Mouse Clock, Bidirectional
inout ps2_mse_dat_ // PS2 Mouse Data, Bidirectional
);
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// This section is a simple WB interface
// --------------------------------------------------------------------
// --------------------------------------------------------------------
wire [7:0] dat_i;
wire [2:0] wb_ps2_addr;
wire wb_ack_i;
wire write_i;
wire read_i;
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// This section is a simple front end for the PS2 Mouse, it is NOT 100%
// 8042 compliant but is hopefully close enough to work for most apps.
// There are two variants in common use, the AT style and the PS2 style
// Interface, this is an implementation of the PS2 style which seems to be
// The most common. Reference: http://www.computer-engineering.org/ps2keyboard/
//
// |7|6|5|4|3|2|1|0| PS2 Status Register
// | | | | | | | `-- PS_IBF - Input Buffer Full-- 0: Empty, No unread input at port, 1: Data available for host to read
// | | | | | | `---- PS_OBF - Output Buffer Full-- 0: Output Buffer Empty, 1: data in buffer being processed
// | | | | | `------ PS_SYS - System flag-- POST read this to determine if power-on reset, 0: in reset, 1: BAT code received - System has already beed initialized
// | | | | `-------- PS_A2 - Address line A2-- Used internally by kbd controller, 0: A2 = 0 - Port 0x60 was last written to, 1: A2 = 1 - Port 0x64 was last written to
// | | | `---------- PS_INH - Inhibit flag-- Indicates if kbd communication is inhibited; 0: Keyboard Clock = 0 - Keyboard is inhibited , 1: Keyboard Clock = 1 - Keyboard is not inhibited
// | | `------------ PS_MOBF - Mouse Output Buffer Full; 0: Output buffer empty, 1: Output buffer full
// | `-------------- PS_TO - General Timout-- Indicates timeout during command write or response. (Same as TxTO + RxTO.)
// `---------------- RX_PERR - Parity Error-- Indicates communication error with keyboard (possibly noisy/loose connection)
//
// |7|6|5|4|3|2|1|0| PS2 Control Byte
// | | | | | | | `-- PS_INT - Input Buffer Full Interrupt-- When set, IRQ 1 is generated when data is available in the input buffer.
// | | | | | | `---- PS_INT2 - Mouse Input Buffer Full Interrupt - When set, IRQ 12 is generated when mouse data is available.
// | | | | | `------ PS_SYSF - System Flag-- Used to manually set/clear SYS flag in Status register.
// | | | | `-------- - No assignment
// | | | `---------- PS_EN - Disable keyboard-- Disables/enables keyboard interface
// | | `------------ PS_EN2 - Disable Mouse-- Disables/enables mouse interface
// | `-------------- PS_XLAT - Translate Scan Codes - Enables/disables translation to set 1 scan codes
// `---------------- - No assignment
//
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Status Register and Wires
// --------------------------------------------------------------------
wire PS_IBF;
wire PS_OBF;
wire PS_SYS;
wire PS_A2;
wire PS_INH;
wire PS_MOBF;
wire PS_TO;
wire RX_PERR;
wire [7:0] PS_STAT;
// --------------------------------------------------------------------
// Control Register and Wires
// --------------------------------------------------------------------
reg [7:0] PS_CNTL; // Control Register
wire PS_INT;
wire PS_INT2;
wire DAT_SEL;
wire DAT_wr;
wire DAT_rd;
wire CMD_SEL;
wire CMD_wr;
wire CMD_rdc;
wire CMD_wrc;
wire CMD_mwr;
wire CMD_tst;
wire CMD_mit;
wire [7:0] dat_o;
wire [7:0] d_dat_o;
wire [7:0] r_dat_o;
wire [7:0] t_dat_o;
wire [7:0] i_dat_o;
wire [7:0] p_dat_o;
wire [7:0] ps_tst_o;
wire [7:0] ps_mit_o;
wire cmd_msnd;
wire IBF;
reg cnt_r_flag; // Read Control lines flag
reg cnt_w_flag; // Write to Control lines flag
reg cmd_w_msnd; // Signal to send to mouse flag
reg cmd_r_test; // Signal to send test flag
reg cmd_r_mint; // Signal to send test flag
reg MSE_INT; // Mouse Receive interrupt signal
wire PS_READ;
wire [7:0] MSE_dat_o; // Receive Register
wire [7:0] MSE_dat_i;
wire MSE_RDY; // Signal data received
wire MSE_DONE; // Signal command finished sending
wire MSE_TOER; // Indicates a Transmit error occured
wire MSE_OVER; // Indicates buffer over run error
wire MSE_SEND;
wire KBD_INT;
wire [7:0] KBD_dat_o;
wire KBD_Txdone;
wire KBD_Rxdone;
// Unused output
wire released;
/*
* We comment this out as they are never read
*
wire PS_SYSF = PS_CNTL[2]; // 0: Power-on value - Tells POST to perform power-on tests/initialization. 1: BAT code received - Tells POST to perform "warm boot" tests/initiailization.
wire PS_EN = PS_CNTL[4]; // 0: Enable - Keyboard interface enabled. 1: Disable - All keyboard communication is disabled.
wire PS_EN2 = PS_CNTL[5]; // 0: Enable - Auxillary PS/2 device interface enabled 1: Disable - Auxillary PS/2 device interface disabled
wire PS_XLAT = PS_CNTL[6]; // 0: Translation disabled - Data appears at input buffer exactly as read from keyboard 1: Translation enabled - Scan codes translated to set 1 before put in input buffer
*/
`define default_cntl 8'b0100_0111
// --------------------------------------------------------------------
// Behaviour for Command Register
// The PS2 has this funky command byte structure:
//
// - If you write 0x60 to 0x64 port and they next byte you write to port 0x60
// is stored as the command byte (nice and confusing).
//
// - If you write 0x20 to port 0x64, the next byte you read from port
// 0x60 is the command byte read back.
//
// - If you read from 0x64, you get the status
//
// - if you read 0x60, that is either mouse or keyboard data, depending
// on the last command sent
//
// - if you write data to 0x60, either mouse or keyboard data is transmitted
// to either the mouse or keyboard depending on the last command.
//
// Right now, we do not allow sending data to the keyboard, that maybe
// will change later on.
//
// --------------------------------------------------------------------
// Controller Commands:
// ,------------------------ - Currently Supported Command
// |
// 0x20 X Read control lines - Next byte read from 0x60 is control line info
// 0x60 X Write to control lines - Next byte writen to 0x60 is control line info
// 0x90-0x9F _ Write to output port - Writes command's lower nibble to lower nibble of output port
// 0xA1 _ Get version number - Returns firmware version number.
// 0xA4 _ Get password - Returns 0xFA if password exists; otherwise, 0xF1.
// 0xA5 _ Set password - Set the new password by sending a null-terminated string of scan codes as this command's parameter.
// 0xA6 _ Check password - Compares keyboard input with current password.
// 0xA7 _ Disable mouse interface - PS/2 mode only. Similar to "Disable keyboard interface" (0xAD) command.
// 0xA8 _ Enable mouse interface - PS/2 mode only. Similar to "Enable keyboard interface" (0xAE) command.
// 0xA9 X Mouse interface test - Returns 0x00 if okay, 0x01 if Clock line stuck low, 0x02 if clock line stuck high, 0x03 if data line stuck low, and 0x04 if data line stuck high.
// 0xAA X Controller self-test - Returns 0x55 if okay.
// 0xAB _ Keyboard interface test - Returns 0x00 if okay, 0x01 if Clock line stuck low, 0x02 if clock line stuck high, 0x03 if data line stuck low, and 0x04 if data line stuck high.
// 0xAD _ Disable keybrd interface- Sets bit 4 of command byte and disables all communication with keyboard.
// 0xAE _ Enable keybrd interface - Clears bit 4 of command byte and re-enables communication with keyboard.
// 0xAF _ Get version
// 0xC0 _ Read input port - Returns values on input port (see Input Port definition.)
// 0xC1 _ Copy input port LSn - PS/2 mode only. Copy input port's low nibble to Status register (see Input Port definition)
// 0xC2 _ Copy input port MSn - PS/2 mode only. Copy input port's high nibble to Status register (see Input Port definition.)
// 0xD0 _ Read output port - Returns values on output port (see Output Port definition.)
// 0xD1 _ Write output port - Write parameter to output port (see Output Port definition.)
// 0xD2 _ Write keyboard buffer - Parameter written to input buffer as if received from keyboard.
// 0xD3 _ Write mouse buffer - Parameter written to input buffer as if received from mouse.
// 0xD4 X Write mouse Device - Sends parameter to the auxillary PS/2 device.
// 0xE0 _ Read test port - Returns values on test port (see Test Port definition.)
// 0xF0-0xFF _ Pulse output port - Pulses command's lower nibble onto lower nibble of output port (see Output Port definition.)
// --------------------------------------------------------------------
`define PS2_CMD_A9 8'hA9 // Mouse Interface test
`define PS2_CMD_AA 8'hAA // Controller self test
`define PS2_CMD_D4 8'hD4 // Write to mouse
`define PS2_CNT_RD 8'h20 // Read command byte
`define PS2_CNT_WR 8'h60 // Write control byte
`define PS2_DAT_REG 3'b000 // 0x60 - RW Transmit / Receive register
`define PS2_CMD_REG 3'b100 // 0x64 - RW - Status / command register
// --------------------------------------------------------------------
// Command Behavior
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Behavior of Control Register
// --------------------------------------------------------------------
always @(posedge wb_clk_i) begin // Synchrounous
if(wb_rst_i) begin
PS_CNTL <= `default_cntl; // Set initial default value
cnt_r_flag <= 1'b0; // Reset the flag
cnt_w_flag <= 1'b0; // Reset the flag
cmd_w_msnd <= 1'b0; // Reset the flag
cmd_r_test <= 1'b0; // Reset the flag
cmd_r_mint <= 1'b0; // Reset the flag
end
else
if(CMD_rdc) begin
cnt_r_flag <= 1'b1; // signal next read from 0x60 is control info
end
else
if(CMD_wrc) begin
cnt_w_flag <= 1'b1; // signal next write to 0x60 is control info
cmd_w_msnd <= 1'b0; // Reset the flag
end
else
if(CMD_mwr) begin
cmd_w_msnd <= 1'b1; // signal next write to 0x60 is mouse info
end
else
if(CMD_tst) begin
cmd_r_test <= 1'b1; // signal next read from 0x60 is test info
end
else
if(CMD_mit) begin
cmd_r_mint <= 1'b1; // signal next read from 0x60 is test info
end
else
if(DAT_rd) begin
if(cnt_r_flag) cnt_r_flag <= 1'b0; // Reset the flag
if(cmd_r_test) cmd_r_test <= 1'b0; // Reset the flag
if(cmd_r_mint) cmd_r_mint <= 1'b0; // Reset the flag
end
else
if(DAT_wr) begin
if(cnt_w_flag) begin
PS_CNTL <= dat_i; // User requested to write control info
cnt_w_flag <= 1'b0; // Reset the flag
end
end
if(cmd_w_msnd && MSE_DONE) cmd_w_msnd <= 1'b0; // Reset the flag
end // Synchrounous always
// --------------------------------------------------------------------
// Mouse Transceiver Section
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Mouse Receive Interrupt behavior
// --------------------------------------------------------------------
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) MSE_INT <= 1'b0; // Default value
else begin
if(MSE_RDY) MSE_INT <= 1'b1; // Latch interrupt
if(PS_READ) MSE_INT <= 1'b0; // Clear interrupt
end
end // Synchrounous always
// --------------------------------------------------------------------
// Instantiate the PS2 UART for MOUSE
// --------------------------------------------------------------------
ps2_mouse_nofifo mouse_nofifo (
.clk (wb_clk_i),
.reset (wb_rst_i),
.ps2_clk (ps2_mse_clk_),
.ps2_dat (ps2_mse_dat_),
.writedata (MSE_dat_i), // data to send
.write (MSE_SEND), // signal to send it
.command_was_sent (MSE_DONE), // Done sending
.readdata (MSE_dat_o), // data read
.irq (MSE_RDY), // signal data has arrived and is ready to be read
.error_sending_command (MSE_TOER), // Time out error
.buffer_overrun_error (MSE_OVER) // Buffer over run error
);
// --------------------------------------------------------------------
// Keyboard Receiver Section
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Instantiate the PS2 UART for KEYBOARD
// --------------------------------------------------------------------
ps2_keyb #(
.TIMER_60USEC_VALUE_PP (750),
.TIMER_60USEC_BITS_PP (10),
.TIMER_5USEC_VALUE_PP (60),
.TIMER_5USEC_BITS_PP (6)
) keyb (
.clk (wb_clk_i),
.reset (wb_rst_i),
.rx_shifting_done (KBD_Rxdone), // done receivign
.tx_shifting_done (KBD_Txdone), // done transmiting
.scancode (KBD_dat_o), // scancode
.rx_output_strobe (KBD_INT), // Signals a key presseed
.released (released),
.ps2_clk_ (ps2_kbd_clk_), // PS2 PAD signals
.ps2_data_ (ps2_kbd_dat_)
);
// Combinatorial logic
assign dat_i = wb_sel_i[0] ? wb_dat_i[7:0] : wb_dat_i[15:8]; // 8 to 16 bit WB
assign wb_dat_o = wb_sel_i[0] ? {8'h00, dat_o} : {dat_o, 8'h00}; // 8 to 16 bit WB
assign wb_ps2_addr = {wb_adr_i, wb_sel_i[1]}; // Compute Address
assign wb_ack_i = wb_stb_i & wb_cyc_i; // Immediate ack
assign wb_ack_o = wb_ack_i;
assign write_i = wb_ack_i & wb_we_i; // WISHBONE write access, Singal to send
assign read_i = wb_ack_i & ~wb_we_i; // WISHBONE write access, Singal to send
assign wb_tgm_o = MSE_INT & PS_INT2; // Mouse Receive interupts ocurred
assign wb_tgk_o = KBD_INT & PS_INT; // Keyboard Receive interupts ocurred
assign PS_IBF = IBF; // 0: Empty, No unread input at port, 1: Full, New input can be read from port 0x60
assign PS_OBF = KBD_Txdone; // 0: Ok to write to port 0x60 1: Full, Don't write to port 0x60
assign PS_SYS = 1'b1; // 1: Always 1 cuz this is fpga so will always be initialized
assign PS_A2 = 1'b0; // 0: A2 = 0 - Port 0x60 was last written to, 1: A2 = 1 - Port 0x64 was last written to
assign PS_INH = 1'b1; // 0: Keyboard Clock = 0 - Keyboard is inhibited , 1: Keyboard Clock = 1 - Keyboard is not inhibited
assign PS_MOBF = MSE_DONE; // 0: Buffer empty - Okay to write to auxillary device's output buffer, 1: Output buffer full - Don't write to port auxillary device's output buffer
assign PS_TO = MSE_TOER; // 0: No Error - Keyboard received and responded to last command, 1: Timeout Error - See TxTO and RxTO for more information.
assign RX_PERR = MSE_OVER; // 0: No Error - Odd parity received and proper command response recieved, 1: Parity Error - Even parity received or 0xFE received as command response.
assign PS_STAT = {RX_PERR, PS_TO, PS_MOBF, PS_INH, PS_A2, PS_SYS, PS_OBF, PS_IBF}; // Status Register
assign PS_INT = PS_CNTL[0]; // 0: IBF Interrupt Disabled, 1: IBF Interrupt Enabled - Keyboard driver at software int 0x09 handles input.
assign PS_INT2 = PS_CNTL[1]; // 0: Auxillary IBF Interrupt Disabled, 1: Auxillary IBF Interrupt Enabled
assign DAT_SEL = (wb_ps2_addr == `PS2_DAT_REG);
assign DAT_wr = DAT_SEL && write_i;
assign DAT_rd = DAT_SEL && read_i;
assign CMD_SEL = (wb_ps2_addr == `PS2_CMD_REG);
assign CMD_wr = CMD_SEL && write_i;
assign CMD_rdc = CMD_wr && (dat_i == `PS2_CNT_RD); // Request to read control info
assign CMD_wrc = CMD_wr && (dat_i == `PS2_CNT_WR); // Request to write control info
assign CMD_mwr = CMD_wr && (dat_i == `PS2_CMD_D4); // Signal to transmit data to mouse
assign CMD_tst = CMD_wr && (dat_i == `PS2_CMD_AA); // User requested self test
assign CMD_mit = CMD_wr && (dat_i == `PS2_CMD_A9); // User mouse interface test
assign dat_o = d_dat_o; // Select register
assign d_dat_o = DAT_SEL ? r_dat_o : PS_STAT; // Select register
assign r_dat_o = cnt_r_flag ? PS_CNTL : t_dat_o; // return control or data
assign t_dat_o = cmd_r_test ? ps_tst_o : i_dat_o; // return control or data
assign i_dat_o = cmd_r_mint ? ps_mit_o : p_dat_o; // return control or data
assign p_dat_o = MSE_INT ? MSE_dat_o : KBD_dat_o; // defer to mouse
assign ps_tst_o = 8'h55; // Controller self test
assign ps_mit_o = 8'h00; // Controller self test
assign cmd_msnd = cmd_w_msnd && DAT_wr; // OK to write to mouse
assign IBF = MSE_INT || KBD_INT || cnt_r_flag || cmd_r_test || cmd_r_mint;
assign PS_READ = DAT_rd && !(cnt_r_flag || cmd_r_test || cmd_r_mint);
assign MSE_dat_i = dat_i; // Transmit register
assign MSE_SEND = cmd_msnd; // Signal to transmit data
endmodule |
module difficult_multi(A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X, Y, Z, valid);
wire _0000_;
wire _0001_;
wire _0002_;
wire _0003_;
wire _0004_;
wire _0005_;
wire _0006_;
wire _0007_;
wire _0008_;
wire _0009_;
wire _0010_;
wire _0011_;
wire _0012_;
wire _0013_;
wire _0014_;
wire _0015_;
wire _0016_;
wire _0017_;
wire _0018_;
wire _0019_;
wire _0020_;
wire _0021_;
wire _0022_;
wire _0023_;
wire _0024_;
wire _0025_;
wire _0026_;
wire _0027_;
wire _0028_;
wire _0029_;
wire _0030_;
wire _0031_;
wire _0032_;
wire _0033_;
wire _0034_;
wire _0035_;
wire _0036_;
wire _0037_;
wire _0038_;
wire _0039_;
wire _0040_;
wire _0041_;
wire _0042_;
wire _0043_;
wire _0044_;
wire _0045_;
wire _0046_;
wire _0047_;
wire _0048_;
wire _0049_;
wire _0050_;
wire _0051_;
wire _0052_;
wire _0053_;
wire _0054_;
wire _0055_;
wire _0056_;
wire _0057_;
wire _0058_;
wire _0059_;
wire _0060_;
wire _0061_;
wire _0062_;
wire _0063_;
wire _0064_;
wire _0065_;
wire _0066_;
wire _0067_;
wire _0068_;
wire _0069_;
wire _0070_;
wire _0071_;
wire _0072_;
wire _0073_;
wire _0074_;
wire _0075_;
wire _0076_;
wire _0077_;
wire _0078_;
wire _0079_;
wire _0080_;
wire _0081_;
wire _0082_;
wire _0083_;
wire _0084_;
wire _0085_;
wire _0086_;
wire _0087_;
wire _0088_;
wire _0089_;
wire _0090_;
wire _0091_;
wire _0092_;
wire _0093_;
wire _0094_;
wire _0095_;
wire _0096_;
wire _0097_;
wire _0098_;
wire _0099_;
wire _0100_;
wire _0101_;
wire _0102_;
wire _0103_;
wire _0104_;
wire _0105_;
wire _0106_;
wire _0107_;
wire _0108_;
wire _0109_;
wire _0110_;
wire _0111_;
wire _0112_;
wire _0113_;
wire _0114_;
wire _0115_;
wire _0116_;
wire _0117_;
wire _0118_;
wire _0119_;
wire _0120_;
wire _0121_;
wire _0122_;
wire _0123_;
wire _0124_;
wire _0125_;
wire _0126_;
wire _0127_;
wire _0128_;
wire _0129_;
wire _0130_;
wire _0131_;
wire _0132_;
wire _0133_;
wire _0134_;
wire _0135_;
wire _0136_;
wire _0137_;
wire _0138_;
wire _0139_;
wire _0140_;
wire _0141_;
wire _0142_;
wire _0143_;
wire _0144_;
wire _0145_;
wire _0146_;
wire _0147_;
wire _0148_;
wire _0149_;
wire _0150_;
wire _0151_;
wire _0152_;
wire _0153_;
wire _0154_;
wire _0155_;
wire _0156_;
wire _0157_;
wire _0158_;
wire _0159_;
wire _0160_;
wire _0161_;
wire _0162_;
wire _0163_;
wire _0164_;
wire _0165_;
wire _0166_;
wire _0167_;
wire _0168_;
wire _0169_;
wire _0170_;
wire _0171_;
wire _0172_;
wire _0173_;
wire _0174_;
wire _0175_;
wire _0176_;
wire _0177_;
wire _0178_;
wire _0179_;
wire _0180_;
wire _0181_;
wire _0182_;
wire _0183_;
wire _0184_;
wire _0185_;
wire _0186_;
wire _0187_;
wire _0188_;
wire _0189_;
wire _0190_;
wire _0191_;
wire _0192_;
wire _0193_;
wire _0194_;
wire _0195_;
wire _0196_;
wire _0197_;
wire _0198_;
wire _0199_;
wire _0200_;
wire _0201_;
wire _0202_;
wire _0203_;
wire _0204_;
wire _0205_;
wire _0206_;
wire _0207_;
wire _0208_;
wire _0209_;
wire _0210_;
wire _0211_;
wire _0212_;
wire _0213_;
wire _0214_;
wire _0215_;
wire _0216_;
wire _0217_;
wire _0218_;
wire _0219_;
wire _0220_;
wire _0221_;
wire _0222_;
wire _0223_;
wire _0224_;
wire _0225_;
wire _0226_;
wire _0227_;
wire _0228_;
wire _0229_;
wire _0230_;
wire _0231_;
wire _0232_;
wire _0233_;
wire _0234_;
wire _0235_;
wire _0236_;
wire _0237_;
wire _0238_;
wire _0239_;
wire _0240_;
wire _0241_;
wire _0242_;
wire _0243_;
wire _0244_;
wire _0245_;
wire _0246_;
wire _0247_;
wire _0248_;
wire _0249_;
wire _0250_;
wire _0251_;
wire _0252_;
wire _0253_;
wire _0254_;
wire _0255_;
wire _0256_;
wire _0257_;
wire _0258_;
wire _0259_;
wire _0260_;
wire _0261_;
wire _0262_;
wire _0263_;
wire _0264_;
wire _0265_;
wire _0266_;
wire _0267_;
wire _0268_;
wire _0269_;
wire _0270_;
wire _0271_;
wire _0272_;
wire _0273_;
wire _0274_;
wire _0275_;
wire _0276_;
wire _0277_;
wire _0278_;
wire _0279_;
wire _0280_;
wire _0281_;
wire _0282_;
wire _0283_;
wire _0284_;
wire _0285_;
wire _0286_;
wire _0287_;
wire _0288_;
wire _0289_;
wire _0290_;
wire _0291_;
wire _0292_;
wire _0293_;
wire _0294_;
wire _0295_;
wire _0296_;
wire _0297_;
wire _0298_;
wire _0299_;
wire _0300_;
wire _0301_;
wire _0302_;
wire _0303_;
wire _0304_;
wire _0305_;
wire _0306_;
wire _0307_;
wire _0308_;
wire _0309_;
wire _0310_;
wire _0311_;
wire _0312_;
wire _0313_;
wire _0314_;
wire _0315_;
wire _0316_;
wire _0317_;
wire _0318_;
wire _0319_;
wire _0320_;
wire _0321_;
wire _0322_;
wire _0323_;
wire _0324_;
wire _0325_;
wire _0326_;
wire _0327_;
wire _0328_;
wire _0329_;
wire _0330_;
wire _0331_;
wire _0332_;
wire _0333_;
wire _0334_;
wire _0335_;
wire _0336_;
wire _0337_;
wire _0338_;
wire _0339_;
wire _0340_;
wire _0341_;
wire _0342_;
wire _0343_;
wire _0344_;
wire _0345_;
wire _0346_;
wire _0347_;
wire _0348_;
wire _0349_;
wire _0350_;
wire _0351_;
wire _0352_;
wire _0353_;
wire _0354_;
wire _0355_;
wire _0356_;
wire _0357_;
wire _0358_;
wire _0359_;
wire _0360_;
wire _0361_;
wire _0362_;
wire _0363_;
wire _0364_;
wire _0365_;
wire _0366_;
wire _0367_;
wire _0368_;
wire _0369_;
wire _0370_;
wire _0371_;
wire _0372_;
wire _0373_;
wire _0374_;
wire _0375_;
wire _0376_;
wire _0377_;
wire _0378_;
wire _0379_;
wire _0380_;
wire _0381_;
wire _0382_;
wire _0383_;
wire _0384_;
wire _0385_;
wire _0386_;
wire _0387_;
wire _0388_;
wire _0389_;
wire _0390_;
wire _0391_;
wire _0392_;
wire _0393_;
wire _0394_;
wire _0395_;
wire _0396_;
wire _0397_;
wire _0398_;
wire _0399_;
wire _0400_;
wire _0401_;
wire _0402_;
wire _0403_;
wire _0404_;
wire _0405_;
wire _0406_;
wire _0407_;
wire _0408_;
wire _0409_;
wire _0410_;
wire _0411_;
wire _0412_;
wire _0413_;
wire _0414_;
wire _0415_;
wire _0416_;
wire _0417_;
wire _0418_;
wire _0419_;
wire _0420_;
wire _0421_;
wire _0422_;
wire _0423_;
wire _0424_;
wire _0425_;
wire _0426_;
wire _0427_;
wire _0428_;
wire _0429_;
wire _0430_;
wire _0431_;
wire _0432_;
wire _0433_;
wire _0434_;
wire _0435_;
wire _0436_;
wire _0437_;
wire _0438_;
wire _0439_;
wire _0440_;
wire _0441_;
wire _0442_;
wire _0443_;
wire _0444_;
wire _0445_;
wire _0446_;
wire _0447_;
wire _0448_;
wire _0449_;
wire _0450_;
wire _0451_;
wire _0452_;
wire _0453_;
wire _0454_;
wire _0455_;
wire _0456_;
wire _0457_;
wire _0458_;
wire _0459_;
wire _0460_;
wire _0461_;
wire _0462_;
wire _0463_;
wire _0464_;
wire _0465_;
wire _0466_;
wire _0467_;
wire _0468_;
wire _0469_;
wire _0470_;
wire _0471_;
wire _0472_;
wire _0473_;
wire _0474_;
wire _0475_;
wire _0476_;
wire _0477_;
wire _0478_;
wire _0479_;
wire _0480_;
wire _0481_;
wire _0482_;
wire _0483_;
wire _0484_;
wire _0485_;
wire _0486_;
wire _0487_;
wire _0488_;
wire _0489_;
wire _0490_;
wire _0491_;
wire _0492_;
wire _0493_;
wire _0494_;
wire _0495_;
wire _0496_;
wire _0497_;
wire _0498_;
wire _0499_;
wire _0500_;
wire _0501_;
wire _0502_;
wire _0503_;
wire _0504_;
wire _0505_;
wire _0506_;
wire _0507_;
wire _0508_;
wire _0509_;
wire _0510_;
wire _0511_;
wire _0512_;
wire _0513_;
wire _0514_;
wire _0515_;
wire _0516_;
wire _0517_;
wire _0518_;
wire _0519_;
wire _0520_;
wire _0521_;
wire _0522_;
wire _0523_;
wire _0524_;
wire _0525_;
wire _0526_;
wire _0527_;
wire _0528_;
wire _0529_;
wire _0530_;
wire _0531_;
wire _0532_;
wire _0533_;
wire _0534_;
wire _0535_;
wire _0536_;
wire _0537_;
wire _0538_;
wire _0539_;
wire _0540_;
wire _0541_;
wire _0542_;
wire _0543_;
wire _0544_;
wire _0545_;
wire _0546_;
wire _0547_;
wire _0548_;
wire _0549_;
wire _0550_;
wire _0551_;
wire _0552_;
wire _0553_;
wire _0554_;
wire _0555_;
wire _0556_;
wire _0557_;
wire _0558_;
wire _0559_;
wire _0560_;
wire _0561_;
wire _0562_;
wire _0563_;
wire _0564_;
wire _0565_;
wire _0566_;
wire _0567_;
wire _0568_;
wire _0569_;
wire _0570_;
wire _0571_;
wire _0572_;
wire _0573_;
wire _0574_;
wire _0575_;
wire _0576_;
wire _0577_;
wire _0578_;
wire _0579_;
wire _0580_;
wire _0581_;
wire _0582_;
wire _0583_;
wire _0584_;
wire _0585_;
wire _0586_;
wire _0587_;
wire _0588_;
wire _0589_;
wire _0590_;
wire _0591_;
wire _0592_;
wire _0593_;
wire _0594_;
wire _0595_;
wire _0596_;
wire _0597_;
wire _0598_;
wire _0599_;
wire _0600_;
wire _0601_;
wire _0602_;
wire _0603_;
wire _0604_;
wire _0605_;
wire _0606_;
wire _0607_;
wire _0608_;
wire _0609_;
wire _0610_;
wire _0611_;
wire _0612_;
wire _0613_;
wire _0614_;
wire _0615_;
wire _0616_;
wire _0617_;
wire _0618_;
wire _0619_;
wire _0620_;
wire _0621_;
wire _0622_;
wire _0623_;
wire _0624_;
wire _0625_;
wire _0626_;
wire _0627_;
wire _0628_;
wire _0629_;
wire _0630_;
wire _0631_;
wire _0632_;
wire _0633_;
wire _0634_;
wire _0635_;
wire _0636_;
wire _0637_;
wire _0638_;
wire _0639_;
wire _0640_;
wire _0641_;
wire _0642_;
wire _0643_;
wire _0644_;
wire _0645_;
wire _0646_;
wire _0647_;
wire _0648_;
wire _0649_;
wire _0650_;
wire _0651_;
wire _0652_;
wire _0653_;
wire _0654_;
wire _0655_;
wire _0656_;
wire _0657_;
wire _0658_;
wire _0659_;
wire _0660_;
wire _0661_;
wire _0662_;
wire _0663_;
wire _0664_;
wire _0665_;
wire _0666_;
wire _0667_;
wire _0668_;
wire _0669_;
wire _0670_;
wire _0671_;
wire _0672_;
wire _0673_;
wire _0674_;
wire _0675_;
wire _0676_;
wire _0677_;
wire _0678_;
wire _0679_;
wire _0680_;
wire _0681_;
wire _0682_;
wire _0683_;
wire _0684_;
wire _0685_;
wire _0686_;
wire _0687_;
wire _0688_;
wire _0689_;
wire _0690_;
wire _0691_;
wire _0692_;
wire _0693_;
wire _0694_;
wire _0695_;
wire _0696_;
wire _0697_;
wire _0698_;
wire _0699_;
wire _0700_;
wire _0701_;
wire _0702_;
wire _0703_;
wire _0704_;
wire _0705_;
wire _0706_;
wire _0707_;
wire _0708_;
wire _0709_;
wire _0710_;
wire _0711_;
wire _0712_;
wire _0713_;
wire _0714_;
wire _0715_;
wire _0716_;
wire _0717_;
wire _0718_;
wire _0719_;
wire _0720_;
wire _0721_;
wire _0722_;
wire _0723_;
wire _0724_;
wire _0725_;
wire _0726_;
wire _0727_;
wire _0728_;
wire _0729_;
wire _0730_;
wire _0731_;
wire _0732_;
wire _0733_;
wire _0734_;
wire _0735_;
wire _0736_;
wire _0737_;
wire _0738_;
wire _0739_;
wire _0740_;
wire _0741_;
wire _0742_;
wire _0743_;
wire _0744_;
wire _0745_;
wire _0746_;
wire _0747_;
wire _0748_;
wire _0749_;
wire _0750_;
wire _0751_;
wire _0752_;
wire _0753_;
wire _0754_;
wire _0755_;
wire _0756_;
wire _0757_;
wire _0758_;
wire _0759_;
wire _0760_;
wire _0761_;
wire _0762_;
wire _0763_;
wire _0764_;
wire _0765_;
wire _0766_;
wire _0767_;
wire _0768_;
wire _0769_;
wire _0770_;
wire _0771_;
wire _0772_;
wire _0773_;
wire _0774_;
wire _0775_;
wire _0776_;
wire _0777_;
wire _0778_;
wire _0779_;
wire _0780_;
wire _0781_;
wire _0782_;
wire _0783_;
wire _0784_;
wire _0785_;
wire _0786_;
wire _0787_;
wire _0788_;
wire _0789_;
wire _0790_;
wire _0791_;
wire _0792_;
wire _0793_;
wire _0794_;
wire _0795_;
wire _0796_;
wire _0797_;
wire _0798_;
wire _0799_;
wire _0800_;
wire _0801_;
wire _0802_;
wire _0803_;
wire _0804_;
wire _0805_;
wire _0806_;
wire _0807_;
wire _0808_;
wire _0809_;
wire _0810_;
wire _0811_;
wire _0812_;
wire _0813_;
wire _0814_;
wire _0815_;
wire _0816_;
wire _0817_;
wire _0818_;
wire _0819_;
wire _0820_;
wire _0821_;
wire _0822_;
wire _0823_;
wire _0824_;
wire _0825_;
wire _0826_;
wire _0827_;
wire _0828_;
wire _0829_;
wire _0830_;
wire _0831_;
wire _0832_;
wire _0833_;
wire _0834_;
wire _0835_;
wire _0836_;
wire _0837_;
wire _0838_;
wire _0839_;
wire _0840_;
wire _0841_;
wire _0842_;
wire _0843_;
wire _0844_;
wire _0845_;
wire _0846_;
wire _0847_;
wire _0848_;
wire _0849_;
wire _0850_;
wire _0851_;
wire _0852_;
wire _0853_;
wire _0854_;
wire _0855_;
wire _0856_;
wire _0857_;
wire _0858_;
wire _0859_;
wire _0860_;
wire _0861_;
wire _0862_;
wire _0863_;
wire _0864_;
wire _0865_;
wire _0866_;
wire _0867_;
wire _0868_;
wire _0869_;
wire _0870_;
wire _0871_;
wire _0872_;
wire _0873_;
wire _0874_;
wire _0875_;
wire _0876_;
wire _0877_;
wire _0878_;
wire _0879_;
wire _0880_;
wire _0881_;
wire _0882_;
wire _0883_;
wire _0884_;
wire _0885_;
wire _0886_;
wire _0887_;
wire _0888_;
wire _0889_;
wire _0890_;
wire _0891_;
wire _0892_;
wire _0893_;
wire _0894_;
wire _0895_;
wire _0896_;
wire _0897_;
wire _0898_;
wire _0899_;
wire _0900_;
wire _0901_;
wire _0902_;
wire _0903_;
wire _0904_;
wire _0905_;
wire _0906_;
wire _0907_;
wire _0908_;
wire _0909_;
wire _0910_;
wire _0911_;
(* src = "difficult_multi.v:3" *)
input A;
(* src = "difficult_multi.v:3" *)
input B;
(* src = "difficult_multi.v:3" *)
input C;
(* src = "difficult_multi.v:3" *)
input D;
(* src = "difficult_multi.v:3" *)
input E;
(* src = "difficult_multi.v:3" *)
input F;
(* src = "difficult_multi.v:3" *)
input G;
(* src = "difficult_multi.v:3" *)
input H;
(* src = "difficult_multi.v:3" *)
input I;
(* src = "difficult_multi.v:3" *)
input J;
(* src = "difficult_multi.v:3" *)
input K;
(* src = "difficult_multi.v:3" *)
input L;
(* src = "difficult_multi.v:3" *)
input M;
(* src = "difficult_multi.v:3" *)
input N;
(* src = "difficult_multi.v:3" *)
input O;
(* src = "difficult_multi.v:3" *)
input P;
(* src = "difficult_multi.v:3" *)
input Q;
(* src = "difficult_multi.v:3" *)
input R;
(* src = "difficult_multi.v:3" *)
input S;
(* src = "difficult_multi.v:3" *)
input T;
(* src = "difficult_multi.v:3" *)
input U;
(* src = "difficult_multi.v:3" *)
input V;
(* src = "difficult_multi.v:3" *)
input W;
(* src = "difficult_multi.v:3" *)
input X;
(* src = "difficult_multi.v:3" *)
input Y;
(* src = "difficult_multi.v:3" *)
input Z;
(* src = "difficult_multi.v:4" *)
output valid;
assign _0180_ = ~T;
assign _0191_ = ~O;
assign _0202_ = ~K;
assign _0213_ = ~(B ^ A);
assign _0224_ = _0213_ ^ J;
assign _0235_ = _0224_ ^ _0202_;
assign _0246_ = _0235_ ^ M;
assign _0257_ = _0246_ ^ _0191_;
assign _0268_ = ~(_0257_ | _0180_);
assign _0279_ = ~P;
assign _0290_ = _0246_ | _0191_;
assign _0301_ = _0235_ & M;
assign _0312_ = _0224_ | _0202_;
assign _0323_ = B & A;
assign _0344_ = ~(B | A);
assign _0345_ = J ? _0323_ : _0344_;
assign _0356_ = _0345_ ^ _0312_;
assign _0367_ = _0356_ ^ L;
assign _0378_ = _0367_ ^ _0301_;
assign _0389_ = _0378_ ^ _0290_;
assign _0400_ = _0389_ ^ _0279_;
assign _0411_ = _0400_ ^ Q;
assign _0422_ = _0411_ ^ _0268_;
assign _0433_ = _0422_ ^ U;
assign _0444_ = _0433_ & W;
assign _0455_ = ~Q;
assign _0466_ = _0400_ | _0455_;
assign _0477_ = ~(_0389_ | _0279_);
assign _0488_ = ~((_0378_ | _0246_) & O);
assign _0499_ = ~N;
assign _0510_ = _0367_ & _0301_;
assign _0521_ = ~I;
assign _0532_ = ~D;
assign _0553_ = ~C;
assign _0554_ = _0323_ ^ _0553_;
assign _0575_ = _0554_ ^ _0532_;
assign _0576_ = _0575_ ^ G;
assign _0587_ = _0576_ ^ H;
assign _0598_ = _0587_ ^ _0521_;
assign _0609_ = _0344_ & J;
assign _0620_ = _0609_ ^ _0598_;
assign _0631_ = _0620_ ^ _0202_;
assign _0642_ = ~(_0345_ | _0312_);
assign _0653_ = _0356_ & L;
assign _0664_ = _0653_ | _0642_;
assign _0675_ = _0664_ ^ _0631_;
assign _0686_ = _0675_ ^ _0510_;
assign _0697_ = _0686_ ^ _0499_;
assign _0708_ = _0697_ ^ _0488_;
assign _0719_ = _0708_ ^ _0477_;
assign _0730_ = _0719_ ^ _0466_;
assign _0741_ = _0730_ ^ R;
assign _0752_ = _0741_ ^ S;
assign _0763_ = _0752_ ^ _0180_;
assign _0774_ = _0411_ & _0268_;
assign _0785_ = _0422_ & U;
assign _0806_ = ~(_0785_ | _0774_);
assign _0807_ = _0806_ ^ _0763_;
assign _0818_ = ~(_0807_ ^ _0444_);
assign _0829_ = _0433_ ^ W;
assign _0840_ = _0257_ ^ _0180_;
assign _0851_ = _0840_ | _0829_;
assign _0862_ = _0851_ & X;
assign _0873_ = _0862_ & _0818_;
assign _0884_ = _0763_ & _0785_;
assign _0895_ = ~(_0752_ | _0180_);
assign _0906_ = _0763_ & _0774_;
assign _0907_ = _0906_ | _0895_;
assign _0908_ = _0741_ & S;
assign _0909_ = ~(_0730_ & R);
assign _0910_ = _0719_ | _0466_;
assign _0911_ = _0708_ & _0477_;
assign _0000_ = _0697_ | _0488_;
assign _0001_ = _0686_ | _0499_;
assign _0002_ = _0675_ & _0510_;
assign _0003_ = _0631_ & _0653_;
assign _0004_ = ~_0642_;
assign _0005_ = _0620_ | _0202_;
assign _0006_ = ~(_0005_ & _0004_);
assign _0007_ = _0609_ & _0598_;
assign _0008_ = _0587_ | _0521_;
assign _0009_ = ~F;
assign _0010_ = ~(_0554_ | _0532_);
assign _0011_ = ~((_0323_ & _0553_) | _0344_);
assign _0012_ = _0011_ ^ _0010_;
assign _0013_ = _0012_ ^ _0009_;
assign _0014_ = _0576_ & H;
assign _0015_ = ~((_0575_ & G) | _0014_);
assign _0016_ = _0015_ ^ _0013_;
assign _0017_ = _0016_ ^ _0008_;
assign _0018_ = _0017_ ^ _0007_;
assign _0019_ = ~(_0018_ ^ _0006_);
assign _0020_ = _0019_ ^ _0003_;
assign _0021_ = _0020_ ^ M;
assign _0022_ = _0021_ ^ _0002_;
assign _0023_ = _0022_ ^ _0001_;
assign _0024_ = _0023_ ^ _0000_;
assign _0025_ = _0024_ ^ _0911_;
assign _0026_ = _0025_ ^ _0910_;
assign _0027_ = _0026_ ^ _0909_;
assign _0028_ = _0027_ ^ T;
assign _0029_ = _0028_ ^ _0908_;
assign _0030_ = _0029_ ^ _0907_;
assign _0031_ = _0030_ ^ _0884_;
assign _0032_ = ~W;
assign _0033_ = ~_0444_;
assign _0034_ = ~(_0807_ | _0033_);
assign _0035_ = ~(_0034_ | _0032_);
assign _0036_ = _0035_ ^ _0031_;
assign _0037_ = _0036_ ^ _0873_;
assign _0038_ = ~Y;
assign _0039_ = _0862_ ^ _0818_;
assign _0040_ = ~_0829_;
assign _0041_ = ~X;
assign _0042_ = ~(_0840_ | _0041_);
assign _0043_ = ~_0042_;
assign _0044_ = ~(_0840_ & _0041_);
assign _0045_ = _0044_ & _0043_;
assign _0046_ = ~((_0045_ & _0040_) | _0038_);
assign _0047_ = _0046_ & _0039_;
assign _0048_ = ~(_0047_ | _0038_);
assign _0049_ = _0048_ ^ _0037_;
assign _0050_ = ~Z;
assign _0051_ = ~(_0046_ ^ _0039_);
assign _0052_ = ~((_0044_ & Y) | _0042_);
assign _0053_ = _0052_ ^ _0829_;
assign _0054_ = _0053_ & _0051_;
assign _0055_ = ~(_0054_ | _0050_);
assign _0056_ = _0037_ & Y;
assign _0057_ = _0056_ | _0047_;
assign _0058_ = _0036_ & _0873_;
assign _0059_ = _0031_ & W;
assign _0060_ = ~(_0059_ | _0034_);
assign _0061_ = _0030_ & _0884_;
assign _0062_ = _0029_ & _0906_;
assign _0063_ = _0027_ & T;
assign _0064_ = _0063_ | _0895_;
assign _0065_ = _0064_ | _0062_;
assign _0066_ = ~(_0400_ & Q);
assign _0067_ = ~((_0025_ | _0719_) & Q);
assign _0068_ = ~((_0708_ | _0066_) & _0067_);
assign _0069_ = _0024_ & _0911_;
assign _0070_ = ~(_0023_ | _0000_);
assign _0071_ = _0022_ | _0001_;
assign _0072_ = ~_0002_;
assign _0073_ = ~(_0020_ & M);
assign _0074_ = ~(_0020_ | M);
assign _0075_ = ~((_0074_ | _0072_) & _0073_);
assign _0076_ = _0019_ & _0003_;
assign _0077_ = ~((_0005_ & _0004_) | _0018_);
assign _0078_ = ~_0013_;
assign _0079_ = _0078_ & _0014_;
assign _0080_ = ~(_0575_ & G);
assign _0081_ = _0013_ | _0080_;
assign _0082_ = _0012_ | _0009_;
assign _0083_ = ~_0323_;
assign _0084_ = D & C;
assign _0085_ = ~((_0084_ & _0083_) | _0344_);
assign _0086_ = _0085_ ^ _0082_;
assign _0087_ = _0086_ ^ _0081_;
assign _0088_ = _0087_ ^ H;
assign _0089_ = _0088_ ^ _0079_;
assign _0090_ = _0016_ | _0587_;
assign _0091_ = _0090_ & I;
assign _0092_ = _0091_ ^ _0089_;
assign _0093_ = ~J;
assign _0094_ = _0598_ & _0344_;
assign _0095_ = ~_0016_;
assign _0096_ = ~((_0095_ & _0094_) | _0093_);
assign _0097_ = _0096_ ^ _0092_;
assign _0098_ = _0097_ ^ _0077_;
assign _0099_ = _0098_ ^ _0076_;
assign _0100_ = ~(_0099_ ^ _0075_);
assign _0101_ = _0100_ ^ _0071_;
assign _0102_ = _0101_ ^ O;
assign _0103_ = _0102_ ^ _0070_;
assign _0104_ = _0103_ ^ P;
assign _0105_ = _0104_ ^ _0069_;
assign _0106_ = _0105_ ^ Q;
assign _0107_ = _0106_ ^ _0068_;
assign _0108_ = ~R;
assign _0109_ = ~((_0026_ & _0730_) | _0108_);
assign _0110_ = ~(_0109_ ^ _0107_);
assign _0111_ = ~(_0026_ & _0908_);
assign _0112_ = _0111_ ^ _0110_;
assign _0113_ = _0112_ ^ _0065_;
assign _0114_ = _0113_ ^ U;
assign _0115_ = _0114_ ^ _0061_;
assign _0116_ = _0115_ ^ V;
assign _0117_ = _0116_ ^ _0032_;
assign _0118_ = _0117_ ^ _0060_;
assign _0119_ = _0118_ ^ _0058_;
assign _0120_ = ~(_0119_ ^ _0057_);
assign _0121_ = ~(_0120_ | _0050_);
assign _0122_ = ~((_0055_ & _0049_) | _0121_);
assign _0123_ = _0119_ & _0057_;
assign _0124_ = _0118_ & _0058_;
assign _0125_ = ~(_0116_ & W);
assign _0126_ = ~((_0117_ | _0060_) & _0125_);
assign _0127_ = _0115_ & V;
assign _0128_ = ~_0061_;
assign _0129_ = ~(_0113_ & U);
assign _0130_ = ~(_0113_ | U);
assign _0131_ = ~((_0130_ | _0128_) & _0129_);
assign _0132_ = _0112_ & _0065_;
assign _0133_ = _0109_ & _0107_;
assign _0134_ = _0105_ & Q;
assign _0135_ = _0106_ & _0068_;
assign _0136_ = _0135_ | _0134_;
assign _0137_ = _0103_ & P;
assign _0138_ = _0104_ & _0069_;
assign _0139_ = _0138_ | _0137_;
assign _0140_ = _0101_ & O;
assign _0141_ = _0102_ & _0070_;
assign _0142_ = _0141_ | _0140_;
assign _0143_ = _0099_ & _0075_;
assign _0144_ = _0096_ & _0092_;
assign _0145_ = _0091_ & _0089_;
assign _0146_ = _0087_ & H;
assign _0147_ = _0088_ & _0079_;
assign _0148_ = _0147_ | _0146_;
assign _0149_ = ~(_0086_ | _0081_);
assign _0150_ = ~((_0085_ | _0012_) & F);
assign _0151_ = ~(_0084_ | _0323_);
assign _0152_ = _0151_ | _0344_;
assign _0153_ = _0152_ ^ _0150_;
assign _0154_ = _0153_ ^ _0149_;
assign _0155_ = _0154_ ^ _0148_;
assign _0156_ = _0155_ ^ _0145_;
assign _0157_ = _0156_ ^ _0144_;
assign _0158_ = _0097_ & _0077_;
assign _0159_ = _0098_ & _0076_;
assign _0160_ = _0159_ | _0158_;
assign _0161_ = _0160_ ^ _0157_;
assign _0162_ = _0161_ ^ _0143_;
assign _0163_ = ~(_0022_ | _0686_);
assign _0164_ = ~((_0100_ & _0163_) | _0499_);
assign _0165_ = _0164_ ^ _0162_;
assign _0166_ = _0165_ ^ _0142_;
assign _0167_ = _0166_ ^ _0139_;
assign _0168_ = _0167_ ^ _0136_;
assign _0169_ = _0168_ ^ _0133_;
assign _0170_ = ~S;
assign _0171_ = _0026_ & _0741_;
assign _0172_ = ~((_0171_ & _0110_) | _0170_);
assign _0173_ = _0172_ ^ _0169_;
assign _0174_ = _0173_ ^ _0132_;
assign _0175_ = _0174_ ^ _0131_;
assign _0176_ = _0175_ ^ _0127_;
assign _0177_ = _0176_ ^ _0126_;
assign _0178_ = _0177_ ^ _0124_;
assign _0179_ = ~(_0178_ ^ _0123_);
assign _0181_ = _0179_ | _0122_;
assign _0182_ = _0179_ & _0122_;
assign _0183_ = _0049_ ? _0055_ : _0050_;
assign _0184_ = ~_0054_;
assign _0185_ = ~(_0184_ | _0049_);
assign _0186_ = ~((_0185_ & _0121_) | (_0183_ & _0120_));
assign _0187_ = _0053_ & Z;
assign _0188_ = _0053_ | Z;
assign _0189_ = _0045_ ^ Y;
assign _0190_ = ~((_0189_ & _0188_) | _0187_);
assign _0192_ = _0051_ ? _0187_ : _0190_;
assign _0193_ = ~(_0192_ | _0186_);
assign _0194_ = ~((_0193_ | _0182_) & _0181_);
assign _0195_ = _0176_ & _0126_;
assign _0196_ = _0175_ & _0127_;
assign _0197_ = _0174_ & _0131_;
assign _0198_ = _0173_ & _0132_;
assign _0199_ = _0172_ & _0169_;
assign _0200_ = _0168_ & _0133_;
assign _0201_ = ~(_0167_ & _0136_);
assign _0203_ = _0161_ & _0143_;
assign _0204_ = _0164_ & _0162_;
assign _0205_ = _0204_ | _0203_;
assign _0206_ = _0160_ & _0157_;
assign _0207_ = ~(_0153_ & _0149_);
assign _0208_ = ~((_0152_ | _0150_) & _0207_);
assign _0209_ = ~((_0154_ & _0148_) | _0208_);
assign _0210_ = _0155_ & _0145_;
assign _0211_ = ~((_0156_ & _0144_) | _0210_);
assign _0212_ = _0211_ ^ _0209_;
assign _0214_ = _0212_ ^ _0206_;
assign _0215_ = ~(_0214_ ^ _0205_);
assign _0216_ = _0165_ & _0142_;
assign _0217_ = ~((_0166_ & _0139_) | _0216_);
assign _0218_ = ~(_0217_ ^ _0215_);
assign _0219_ = _0218_ ^ _0201_;
assign _0220_ = _0219_ ^ _0200_;
assign _0221_ = _0220_ ^ _0199_;
assign _0222_ = _0221_ ^ _0198_;
assign _0223_ = _0222_ ^ _0197_;
assign _0225_ = _0223_ ^ _0196_;
assign _0226_ = ~(_0225_ ^ _0195_);
assign _0227_ = _0177_ & _0124_;
assign _0228_ = ~((_0178_ & _0123_) | _0227_);
assign _0229_ = _0228_ ^ _0226_;
assign _0230_ = ~(Q ^ J);
assign _0231_ = _0230_ ^ R;
assign _0232_ = ~(_0231_ | _0170_);
assign _0233_ = ~(_0230_ & R);
assign _0234_ = ~(G ^ E);
assign _0236_ = _0234_ & H;
assign _0237_ = ~(_0234_ | H);
assign _0238_ = ~(_0237_ | _0236_);
assign _0239_ = _0238_ ^ _0521_;
assign _0240_ = _0239_ ^ _0093_;
assign _0241_ = _0240_ ^ K;
assign _0242_ = _0241_ ^ _0499_;
assign _0243_ = _0242_ ^ O;
assign _0244_ = _0243_ | _0279_;
assign _0245_ = ~(_0243_ & _0279_);
assign _0247_ = ~(_0245_ & _0244_);
assign _0248_ = Q & _0093_;
assign _0249_ = ~(_0247_ ^ _0248_);
assign _0250_ = _0233_ ? _0249_ : _0247_;
assign _0251_ = ~(_0250_ ^ _0232_);
assign _0252_ = _0231_ ^ _0170_;
assign _0253_ = ~(_0252_ | _0180_);
assign _0254_ = ~(_0252_ & _0180_);
assign _0255_ = ~((_0254_ & V) | _0253_);
assign _0256_ = _0255_ ^ _0251_;
assign _0258_ = ~(_0256_ | _0032_);
assign _0259_ = ~V;
assign _0260_ = ~_0251_;
assign _0261_ = ~_0253_;
assign _0262_ = _0254_ & _0261_;
assign _0263_ = ~((_0262_ & _0260_) | _0259_);
assign _0264_ = _0240_ & K;
assign _0265_ = ~(G & E);
assign _0266_ = D ^ A;
assign _0267_ = _0266_ ^ _0009_;
assign _0269_ = ~(_0267_ ^ _0265_);
assign _0270_ = ~_0269_;
assign _0271_ = ~(_0236_ | I);
assign _0272_ = _0271_ | _0237_;
assign _0273_ = _0272_ ^ _0270_;
assign _0274_ = ~_0273_;
assign _0275_ = ~(_0239_ | _0093_);
assign _0276_ = _0273_ ^ _0275_;
assign _0277_ = _0264_ ? _0274_ : _0276_;
assign _0278_ = ~(_0241_ | _0499_);
assign _0280_ = ~((_0242_ & O) | _0278_);
assign _0281_ = _0280_ ^ _0277_;
assign _0282_ = ~_0244_;
assign _0283_ = ~((_0245_ & _0248_) | _0282_);
assign _0284_ = _0283_ ^ _0281_;
assign _0285_ = ~(_0247_ | _0233_);
assign _0286_ = ~(_0285_ ^ _0284_);
assign _0287_ = ~_0232_;
assign _0288_ = ~(_0250_ | _0287_);
assign _0289_ = ~(_0288_ | _0170_);
assign _0291_ = _0289_ ^ _0286_;
assign _0292_ = _0261_ | _0251_;
assign _0293_ = _0292_ ^ _0291_;
assign _0294_ = ~(_0293_ ^ _0263_);
assign _0295_ = _0294_ & _0258_;
assign _0296_ = ~_0263_;
assign _0297_ = ~(_0293_ | _0296_);
assign _0298_ = ~_0291_;
assign _0299_ = ~(_0252_ | _0251_);
assign _0300_ = ~((_0299_ & _0298_) | _0180_);
assign _0302_ = _0281_ | J;
assign _0303_ = ~((_0302_ | _0247_) & Q);
assign _0304_ = ~(_0281_ | _0244_);
assign _0305_ = ~(_0242_ & O);
assign _0306_ = ~(_0277_ | _0305_);
assign _0307_ = ~_0277_;
assign _0308_ = _0307_ & _0278_;
assign _0309_ = ~((_0264_ | _0275_) & _0273_);
assign _0310_ = _0269_ & _0238_;
assign _0311_ = ~(_0310_ | _0521_);
assign _0313_ = ~(_0267_ | _0265_);
assign _0314_ = _0266_ | _0009_;
assign _0315_ = ~E;
assign _0316_ = ~(D & A);
assign _0317_ = ~(_0316_ ^ B);
assign _0318_ = _0317_ ^ _0315_;
assign _0319_ = _0318_ ^ _0314_;
assign _0320_ = ~(_0319_ ^ _0313_);
assign _0321_ = _0269_ & _0236_;
assign _0322_ = _0321_ ^ _0320_;
assign _0324_ = _0322_ ^ _0311_;
assign _0325_ = _0324_ ^ _0309_;
assign _0326_ = _0325_ ^ L;
assign _0327_ = _0326_ ^ _0308_;
assign _0328_ = ~(_0327_ ^ _0306_);
assign _0329_ = _0328_ ^ _0304_;
assign _0330_ = _0329_ ^ _0303_;
assign _0331_ = ~_0230_;
assign _0332_ = ~(_0247_ | _0331_);
assign _0333_ = ~((_0332_ & _0284_) | _0108_);
assign _0334_ = _0333_ ^ _0330_;
assign _0335_ = _0334_ ^ S;
assign _0336_ = _0286_ & S;
assign _0337_ = _0336_ | _0288_;
assign _0338_ = _0337_ ^ _0335_;
assign _0339_ = _0338_ ^ _0300_;
assign _0340_ = _0339_ ^ U;
assign _0341_ = _0340_ ^ _0297_;
assign _0342_ = _0341_ ^ _0295_;
assign _0343_ = _0256_ ^ _0032_;
assign _0346_ = _0262_ ^ _0259_;
assign _0347_ = _0346_ & _0343_;
assign _0348_ = _0294_ ^ _0258_;
assign _0349_ = ~((_0348_ | _0347_) & X);
assign _0350_ = ~_0349_;
assign _0351_ = _0350_ & _0342_;
assign _0352_ = ~_0351_;
assign _0353_ = _0340_ & _0297_;
assign _0354_ = ~_0339_;
assign _0355_ = _0338_ & _0300_;
assign _0357_ = ~_0286_;
assign _0358_ = _0357_ & _0288_;
assign _0359_ = _0358_ & _0335_;
assign _0360_ = _0334_ & S;
assign _0361_ = _0336_ | _0360_;
assign _0362_ = _0361_ | _0359_;
assign _0363_ = _0333_ & _0330_;
assign _0364_ = ~(_0329_ | _0303_);
assign _0365_ = _0327_ & _0306_;
assign _0366_ = _0326_ & _0308_;
assign _0368_ = ~(_0325_ & L);
assign _0369_ = ~_0311_;
assign _0370_ = ~(_0322_ | _0369_);
assign _0371_ = ~H;
assign _0372_ = _0269_ & _0234_;
assign _0373_ = ~((_0372_ & _0320_) | _0371_);
assign _0374_ = _0319_ & _0313_;
assign _0375_ = ~(_0317_ & E);
assign _0376_ = E & D;
assign _0377_ = ~_0376_;
assign _0379_ = ~(_0377_ | _0213_);
assign _0380_ = _0323_ | _0532_;
assign _0381_ = ~((_0380_ & _0375_) | _0379_);
assign _0382_ = ~_0266_;
assign _0383_ = ~((_0318_ & _0382_) | _0009_);
assign _0384_ = _0383_ ^ _0381_;
assign _0385_ = _0384_ ^ G;
assign _0386_ = _0385_ ^ _0374_;
assign _0387_ = _0386_ ^ _0373_;
assign _0388_ = ~(_0387_ ^ _0370_);
assign _0390_ = ~_0239_;
assign _0391_ = _0324_ & _0273_;
assign _0392_ = ~((_0391_ & _0390_) | _0093_);
assign _0393_ = _0392_ ^ _0388_;
assign _0394_ = _0391_ & _0264_;
assign _0395_ = _0394_ ^ _0393_;
assign _0396_ = _0395_ ^ _0368_;
assign _0397_ = _0396_ ^ M;
assign _0398_ = _0397_ ^ N;
assign _0399_ = _0398_ ^ _0366_;
assign _0401_ = _0399_ ^ O;
assign _0402_ = _0401_ ^ _0365_;
assign _0403_ = ~(_0281_ | _0243_);
assign _0404_ = ~((_0328_ & _0403_) | _0279_);
assign _0405_ = _0404_ ^ _0402_;
assign _0406_ = _0405_ ^ _0364_;
assign _0407_ = _0406_ ^ _0363_;
assign _0408_ = _0407_ ^ S;
assign _0409_ = _0408_ ^ _0362_;
assign _0410_ = _0409_ ^ T;
assign _0412_ = _0355_ ? _0409_ : _0410_;
assign _0413_ = _0412_ & U;
assign _0414_ = ~(_0339_ & U);
assign _0415_ = ~((_0412_ | U) & (_0410_ | _0414_));
assign _0416_ = ~((_0413_ & _0354_) | _0415_);
assign _0417_ = _0416_ ^ _0353_;
assign _0418_ = _0417_ ^ _0032_;
assign _0419_ = ~(_0418_ | _0352_);
assign _0420_ = _0416_ & _0353_;
assign _0421_ = ~(_0410_ | _0414_);
assign _0423_ = _0421_ | _0413_;
assign _0424_ = _0409_ & T;
assign _0425_ = _0424_ | _0355_;
assign _0426_ = _0407_ & S;
assign _0427_ = _0408_ & _0362_;
assign _0428_ = _0427_ | _0426_;
assign _0429_ = _0406_ & _0363_;
assign _0430_ = ~(_0399_ & O);
assign _0431_ = ~(_0401_ & _0365_);
assign _0432_ = ~(_0431_ & _0430_);
assign _0434_ = _0397_ & N;
assign _0435_ = _0398_ & _0366_;
assign _0436_ = _0435_ | _0434_;
assign _0437_ = _0391_ & _0240_;
assign _0438_ = ~((_0437_ & _0393_) | _0202_);
assign _0439_ = ~_0388_;
assign _0440_ = _0392_ & _0439_;
assign _0441_ = _0384_ & G;
assign _0442_ = ~((_0385_ & _0374_) | _0441_);
assign _0443_ = ~((_0377_ | _0213_) & (_0083_ | _0532_));
assign _0445_ = ~((_0383_ & _0381_) | _0443_);
assign _0446_ = ~(_0445_ | _0442_);
assign _0447_ = _0445_ & _0442_;
assign _0448_ = ~(_0447_ | _0446_);
assign _0449_ = _0386_ & _0373_;
assign _0450_ = ~((_0387_ & _0370_) | _0449_);
assign _0451_ = ~(_0450_ ^ _0448_);
assign _0452_ = _0451_ ^ _0440_;
assign _0453_ = _0452_ ^ _0438_;
assign _0454_ = ~(_0395_ | _0368_);
assign _0456_ = _0396_ & M;
assign _0457_ = _0456_ | _0454_;
assign _0458_ = _0457_ ^ _0453_;
assign _0459_ = _0458_ ^ _0436_;
assign _0460_ = _0459_ ^ _0432_;
assign _0461_ = _0404_ & _0402_;
assign _0462_ = _0405_ & _0364_;
assign _0463_ = _0462_ | _0461_;
assign _0464_ = _0463_ ^ _0460_;
assign _0465_ = _0464_ ^ _0429_;
assign _0467_ = _0465_ ^ _0428_;
assign _0468_ = _0467_ ^ _0425_;
assign _0469_ = _0468_ ^ _0423_;
assign _0470_ = ~(_0469_ ^ _0420_);
assign _0471_ = _0341_ & _0295_;
assign _0472_ = ~((_0417_ & W) | _0471_);
assign _0473_ = _0472_ ^ _0470_;
assign _0474_ = ~(_0473_ & _0419_);
assign _0475_ = _0465_ & _0428_;
assign _0476_ = _0464_ & _0429_;
assign _0478_ = _0460_ & _0462_;
assign _0479_ = _0460_ & _0461_;
assign _0480_ = _0459_ & _0432_;
assign _0481_ = _0458_ & _0436_;
assign _0482_ = _0453_ & _0456_;
assign _0483_ = ~(_0453_ & _0454_);
assign _0484_ = ~(_0387_ & _0370_);
assign _0485_ = ~_0448_;
assign _0486_ = ~(_0446_ | _0449_);
assign _0487_ = ~((_0486_ | _0447_) & (_0485_ | _0484_));
assign _0489_ = _0451_ & _0440_;
assign _0490_ = ~((_0452_ & _0438_) | _0489_);
assign _0491_ = _0490_ ^ _0487_;
assign _0492_ = _0491_ ^ _0483_;
assign _0493_ = _0492_ ^ _0482_;
assign _0494_ = _0493_ ^ _0481_;
assign _0495_ = _0494_ ^ _0480_;
assign _0496_ = _0495_ ^ _0479_;
assign _0497_ = _0496_ ^ _0478_;
assign _0498_ = _0497_ ^ _0476_;
assign _0500_ = _0498_ & _0475_;
assign _0501_ = ~(_0498_ | _0475_);
assign _0502_ = ~(_0501_ | _0500_);
assign _0503_ = _0467_ & _0425_;
assign _0504_ = _0468_ & _0423_;
assign _0505_ = _0504_ | _0503_;
assign _0506_ = _0505_ ^ _0502_;
assign _0507_ = ~(_0469_ & _0420_);
assign _0508_ = ~((_0472_ | _0470_) & _0507_);
assign _0509_ = ~(_0508_ ^ _0506_);
assign _0511_ = _0509_ | _0474_;
assign _0512_ = ~(_0502_ & _0504_);
assign _0513_ = ~(_0497_ & _0476_);
assign _0514_ = ~(_0495_ & _0479_);
assign _0515_ = ~(_0493_ & _0481_);
assign _0516_ = ~_0487_;
assign _0517_ = _0490_ | _0516_;
assign _0518_ = ~((_0491_ | _0483_) & _0517_);
assign _0519_ = ~((_0492_ & _0482_) | _0518_);
assign _0520_ = ~(_0519_ & _0515_);
assign _0522_ = ~((_0494_ & _0480_) | _0520_);
assign _0523_ = ~(_0522_ & _0514_);
assign _0524_ = ~((_0496_ & _0478_) | _0523_);
assign _0525_ = _0524_ & _0513_;
assign _0526_ = ~((_0502_ & _0503_) | _0500_);
assign _0527_ = _0526_ ^ _0525_;
assign _0528_ = ~(_0527_ ^ _0512_);
assign _0529_ = _0508_ & _0506_;
assign _0530_ = ~(_0529_ ^ _0528_);
assign _0531_ = ~(_0347_ | _0041_);
assign _0533_ = _0531_ ^ _0348_;
assign _0534_ = _0346_ & X;
assign _0535_ = ~((_0534_ & _0343_) | _0050_);
assign _0536_ = ~((_0534_ | _0343_) & _0535_);
assign _0537_ = ~_0536_;
assign _0538_ = _0349_ ^ _0342_;
assign _0539_ = ~(_0538_ | _0050_);
assign _0540_ = ~((_0533_ & Z) | _0537_);
assign _0541_ = ~(_0540_ | _0539_);
assign _0542_ = ~_0541_;
assign _0543_ = ~(_0538_ & _0050_);
assign _0544_ = _0543_ | _0533_;
assign _0545_ = ~((_0544_ & _0542_) | (_0537_ & _0533_));
assign _0546_ = _0473_ ^ _0419_;
assign _0547_ = ~(_0351_ | _0471_);
assign _0548_ = _0547_ ^ _0418_;
assign _0549_ = _0548_ & Z;
assign _0550_ = _0541_ | _0539_;
assign _0551_ = _0548_ ^ Z;
assign _0552_ = ~((_0551_ | _0550_) & (_0549_ | _0546_));
assign _0555_ = _0552_ | _0545_;
assign _0556_ = _0550_ | _0549_;
assign _0557_ = ~(_0509_ & _0474_);
assign _0558_ = ~((_0557_ & _0511_) | (_0556_ & _0546_));
assign _0559_ = ~((_0558_ & _0555_) | (_0530_ & _0511_));
assign _0560_ = _0526_ | _0525_;
assign _0561_ = _0526_ & _0525_;
assign _0562_ = ~((_0561_ | _0512_) & _0560_);
assign _0563_ = ~((_0529_ & _0528_) | _0562_);
assign _0564_ = ~((_0530_ | _0511_) & _0563_);
assign _0565_ = _0228_ | _0226_;
assign _0566_ = ~U;
assign _0567_ = E ^ C;
assign _0568_ = _0567_ ^ H;
assign _0569_ = _0568_ ^ K;
assign _0570_ = _0569_ ^ L;
assign _0571_ = _0570_ ^ _0455_;
assign _0572_ = ~(_0571_ | _0170_);
assign _0573_ = ~(_0570_ | _0455_);
assign _0574_ = _0569_ & L;
assign _0577_ = _0567_ & H;
assign _0578_ = _0568_ & K;
assign _0579_ = _0578_ | _0577_;
assign _0580_ = E ^ D;
assign _0581_ = C ? _0532_ : _0580_;
assign _0582_ = _0581_ ^ G;
assign _0583_ = _0582_ ^ _0579_;
assign _0584_ = _0583_ ^ _0574_;
assign _0585_ = _0584_ ^ _0499_;
assign _0586_ = _0585_ ^ O;
assign _0588_ = _0586_ ^ _0573_;
assign _0589_ = _0588_ ^ _0108_;
assign _0590_ = _0589_ ^ _0572_;
assign _0591_ = _0590_ ^ _0180_;
assign _0592_ = _0591_ ^ _0566_;
assign _0593_ = _0571_ ^ _0170_;
assign _0594_ = ~(_0593_ | _0259_);
assign _0595_ = ~(_0594_ ^ _0592_);
assign _0596_ = _0593_ ^ V;
assign _0597_ = _0596_ & X;
assign _0599_ = ~(_0597_ ^ _0595_);
assign _0600_ = _0599_ & Y;
assign _0601_ = ~_0592_;
assign _0602_ = _0594_ & _0601_;
assign _0603_ = ~_0602_;
assign _0604_ = ~(_0591_ | _0566_);
assign _0605_ = ~(_0590_ | _0180_);
assign _0606_ = _0589_ & _0572_;
assign _0607_ = _0588_ | _0108_;
assign _0608_ = _0586_ & _0573_;
assign _0610_ = _0582_ & _0577_;
assign _0611_ = ~G;
assign _0612_ = _0581_ | _0611_;
assign _0613_ = _0084_ ^ A;
assign _0614_ = ~((_0532_ & _0553_) | _0315_);
assign _0615_ = _0614_ ^ _0613_;
assign _0616_ = _0615_ ^ _0009_;
assign _0617_ = _0616_ ^ _0612_;
assign _0618_ = _0617_ ^ _0610_;
assign _0619_ = _0618_ ^ I;
assign _0621_ = ~(_0582_ & _0578_);
assign _0622_ = _0621_ & K;
assign _0623_ = _0622_ ^ _0619_;
assign _0624_ = ~(_0583_ & _0574_);
assign _0625_ = _0624_ & L;
assign _0626_ = _0625_ ^ _0623_;
assign _0627_ = ~(_0584_ | _0499_);
assign _0628_ = ~((_0585_ & O) | _0627_);
assign _0629_ = _0628_ ^ _0626_;
assign _0630_ = _0629_ ^ P;
assign _0632_ = _0630_ ^ _0608_;
assign _0633_ = _0632_ ^ _0607_;
assign _0634_ = _0633_ ^ _0606_;
assign _0635_ = _0634_ ^ _0605_;
assign _0636_ = _0635_ ^ _0604_;
assign _0637_ = _0636_ ^ _0603_;
assign _0638_ = ~_0595_;
assign _0639_ = ~(_0596_ & _0638_);
assign _0640_ = _0639_ & X;
assign _0641_ = _0640_ ^ _0637_;
assign _0643_ = ~_0641_;
assign _0644_ = _0643_ & _0600_;
assign _0645_ = ~_0644_;
assign _0646_ = ~((_0637_ & _0639_) | _0041_);
assign _0647_ = _0636_ | _0603_;
assign _0648_ = _0634_ | _0590_;
assign _0649_ = _0648_ & T;
assign _0650_ = ~(_0630_ & _0586_);
assign _0651_ = _0650_ | _0570_;
assign _0652_ = _0651_ & Q;
assign _0654_ = _0629_ & P;
assign _0655_ = ~_0626_;
assign _0656_ = ~((_0655_ & _0585_) | _0191_);
assign _0657_ = ~((_0623_ & L) | (_0583_ & _0574_));
assign _0658_ = ~_0621_;
assign _0659_ = ~((_0619_ & K) | _0658_);
assign _0660_ = ~(_0615_ | _0009_);
assign _0661_ = ~(_0614_ & _0613_);
assign _0662_ = ~_0661_;
assign _0663_ = _0316_ & C;
assign _0665_ = _0663_ ^ _0213_;
assign _0666_ = _0665_ ^ _0315_;
assign _0667_ = _0666_ ^ _0662_;
assign _0668_ = _0667_ ^ _0660_;
assign _0669_ = ~_0581_;
assign _0670_ = ~((_0616_ & _0669_) | _0611_);
assign _0671_ = _0670_ ^ _0668_;
assign _0672_ = _0617_ & _0610_;
assign _0673_ = ~((_0618_ & I) | _0672_);
assign _0674_ = _0673_ ^ _0671_;
assign _0676_ = _0674_ ^ _0659_;
assign _0677_ = ~(_0676_ ^ L);
assign _0678_ = ~(_0677_ ^ _0657_);
assign _0679_ = _0678_ ^ M;
assign _0680_ = _0655_ & _0627_;
assign _0681_ = ~(_0680_ ^ _0679_);
assign _0682_ = _0681_ ^ _0656_;
assign _0683_ = _0682_ ^ _0654_;
assign _0684_ = _0683_ ^ _0652_;
assign _0685_ = _0684_ ^ _0108_;
assign _0687_ = ~(_0632_ | _0607_);
assign _0688_ = ~((_0633_ & _0606_) | _0687_);
assign _0689_ = _0688_ ^ _0685_;
assign _0690_ = ~(_0689_ ^ _0649_);
assign _0691_ = _0635_ & _0604_;
assign _0692_ = ~(_0691_ | _0566_);
assign _0693_ = _0692_ ^ _0690_;
assign _0694_ = _0693_ ^ _0647_;
assign _0695_ = ~(_0694_ ^ _0646_);
assign _0696_ = ~((_0695_ | _0038_) & _0645_);
assign _0698_ = ~(_0690_ | _0566_);
assign _0699_ = ~(_0698_ | _0691_);
assign _0700_ = ~(_0633_ & _0606_);
assign _0701_ = ~(_0685_ | _0700_);
assign _0702_ = _0684_ & R;
assign _0703_ = _0702_ | _0687_;
assign _0704_ = ~_0629_;
assign _0705_ = _0682_ | _0704_;
assign _0706_ = _0705_ & P;
assign _0707_ = ~M;
assign _0709_ = ~(_0678_ | _0707_);
assign _0710_ = _0623_ | _0624_;
assign _0711_ = ~((_0676_ | _0623_) & L);
assign _0712_ = ~((_0710_ | _0677_) & _0711_);
assign _0713_ = ~(_0674_ | _0659_);
assign _0714_ = _0671_ & _0672_;
assign _0715_ = _0670_ & _0668_;
assign _0716_ = ~(_0666_ & _0662_);
assign _0717_ = ~((_0665_ | _0315_) & _0716_);
assign _0718_ = ~A;
assign _0720_ = B & _0718_;
assign _0721_ = B | _0718_;
assign _0722_ = ~((_0721_ & _0553_) | _0720_);
assign _0723_ = ~(_0722_ | D);
assign _0724_ = _0722_ & D;
assign _0725_ = ~(_0323_ & C);
assign _0726_ = ~((_0725_ & _0724_) | _0723_);
assign _0727_ = _0726_ ^ E;
assign _0728_ = _0727_ ^ _0717_;
assign _0729_ = ~(_0615_ & F);
assign _0731_ = ~(_0667_ & F);
assign _0732_ = ~((_0666_ | _0729_) & _0731_);
assign _0733_ = ~(_0732_ | _0009_);
assign _0734_ = _0733_ ^ _0728_;
assign _0735_ = _0734_ ^ _0715_;
assign _0736_ = ~(_0735_ ^ _0714_);
assign _0737_ = ~(_0671_ & _0618_);
assign _0738_ = ~(_0737_ & I);
assign _0739_ = _0738_ ^ _0736_;
assign _0740_ = _0739_ ^ _0713_;
assign _0742_ = _0740_ ^ _0712_;
assign _0743_ = _0742_ ^ _0709_;
assign _0744_ = ~(_0626_ | _0584_);
assign _0745_ = ~((_0744_ & _0679_) | _0499_);
assign _0746_ = _0745_ ^ _0743_;
assign _0747_ = _0681_ & _0656_;
assign _0748_ = ~(_0747_ | _0191_);
assign _0749_ = _0748_ ^ _0746_;
assign _0750_ = ~(_0749_ ^ _0706_);
assign _0751_ = ~(_0683_ & _0652_);
assign _0753_ = _0751_ & Q;
assign _0754_ = _0753_ ^ _0750_;
assign _0755_ = _0754_ ^ _0108_;
assign _0756_ = _0755_ ^ _0703_;
assign _0757_ = ~(_0756_ ^ _0701_);
assign _0758_ = ~(_0689_ & _0649_);
assign _0759_ = ~(_0758_ & T);
assign _0760_ = _0759_ ^ _0757_;
assign _0761_ = _0760_ ^ _0566_;
assign _0762_ = _0761_ ^ _0699_;
assign _0764_ = ~(_0636_ | _0593_);
assign _0765_ = _0764_ & _0601_;
assign _0766_ = ~((_0765_ & _0693_) | _0259_);
assign _0767_ = ~(_0766_ ^ _0762_);
assign _0768_ = ~(_0694_ & _0646_);
assign _0769_ = ~(_0768_ & X);
assign _0770_ = _0769_ ^ _0767_;
assign _0771_ = ~(_0770_ & _0696_);
assign _0772_ = ~((_0767_ | _0041_) & _0768_);
assign _0773_ = _0766_ & _0762_;
assign _0775_ = ~(_0760_ & U);
assign _0776_ = ~((_0761_ | _0699_) & _0775_);
assign _0777_ = ~((_0757_ | _0180_) & _0758_);
assign _0778_ = _0756_ & _0701_;
assign _0779_ = ~(_0755_ & _0703_);
assign _0780_ = ~((_0754_ | _0108_) & _0779_);
assign _0781_ = ~((_0750_ | _0455_) & _0751_);
assign _0782_ = _0749_ & _0706_;
assign _0783_ = ~((_0746_ & O) | _0747_);
assign _0784_ = _0740_ & _0712_;
assign _0786_ = _0739_ & _0713_;
assign _0787_ = ~((_0737_ & _0736_) | _0521_);
assign _0788_ = _0734_ & _0715_;
assign _0789_ = _0728_ & F;
assign _0790_ = _0789_ | _0732_;
assign _0791_ = _0726_ & E;
assign _0792_ = ~((_0727_ & _0717_) | _0791_);
assign _0793_ = _0084_ & A;
assign _0794_ = ~_0793_;
assign _0795_ = ~((_0083_ & _0553_) | _0344_);
assign _0796_ = ~((_0795_ | _0724_) & _0794_);
assign _0797_ = ~((_0796_ & _0792_) | _0662_);
assign _0798_ = _0797_ ^ _0790_;
assign _0799_ = _0798_ | _0788_;
assign _0800_ = ~((_0798_ & _0788_) | (_0735_ & _0714_));
assign _0801_ = _0800_ & _0799_;
assign _0802_ = _0801_ ^ _0787_;
assign _0803_ = _0802_ ^ _0786_;
assign _0804_ = _0803_ ^ _0784_;
assign _0805_ = _0742_ & _0709_;
assign _0808_ = _0745_ & _0743_;
assign _0809_ = ~(_0808_ | _0805_);
assign _0810_ = _0809_ ^ _0804_;
assign _0811_ = _0810_ ^ _0783_;
assign _0812_ = _0811_ ^ _0782_;
assign _0813_ = _0812_ ^ _0781_;
assign _0814_ = _0813_ ^ _0780_;
assign _0815_ = _0814_ ^ _0778_;
assign _0816_ = _0815_ ^ _0777_;
assign _0817_ = _0816_ ^ _0776_;
assign _0819_ = _0817_ ^ _0773_;
assign _0820_ = ~(_0819_ ^ _0772_);
assign _0821_ = ~(_0820_ | _0771_);
assign _0822_ = _0819_ & _0772_;
assign _0823_ = ~(_0817_ & _0773_);
assign _0824_ = _0816_ & _0776_;
assign _0825_ = ~(_0815_ & _0777_);
assign _0826_ = _0812_ & _0781_;
assign _0827_ = _0811_ & _0782_;
assign _0828_ = ~(_0804_ & _0808_);
assign _0830_ = ~((_0810_ | _0783_) & _0828_);
assign _0831_ = _0797_ & _0790_;
assign _0832_ = _0661_ & _0794_;
assign _0833_ = _0831_ ? _0793_ : _0832_;
assign _0834_ = _0833_ & _0800_;
assign _0835_ = _0801_ & _0787_;
assign _0836_ = ~((_0802_ & _0786_) | _0835_);
assign _0837_ = ~(_0836_ ^ _0834_);
assign _0838_ = ~((_0804_ & _0805_) | (_0802_ & _0784_));
assign _0839_ = _0838_ ^ _0837_;
assign _0841_ = _0839_ ^ _0830_;
assign _0842_ = _0841_ ^ _0827_;
assign _0843_ = ~(_0842_ ^ _0826_);
assign _0844_ = _0813_ & _0780_;
assign _0845_ = ~((_0814_ & _0778_) | _0844_);
assign _0846_ = ~(_0845_ ^ _0843_);
assign _0847_ = _0846_ ^ _0825_;
assign _0848_ = ~(_0847_ ^ _0824_);
assign _0849_ = _0848_ ^ _0823_;
assign _0850_ = _0849_ ^ _0822_;
assign _0852_ = ~(_0770_ ^ _0696_);
assign _0853_ = ~(_0644_ | _0038_);
assign _0854_ = _0853_ ^ _0695_;
assign _0855_ = _0854_ | _0050_;
assign _0856_ = ~(_0855_ | _0852_);
assign _0857_ = ~(_0596_ | X);
assign _0858_ = ~(_0599_ | Y);
assign _0859_ = ~((_0858_ | _0600_) & (_0857_ | _0597_));
assign _0860_ = ~(_0641_ ^ _0600_);
assign _0861_ = ~((_0860_ & _0859_) | Z);
assign _0863_ = _0861_ & _0854_;
assign _0864_ = ~((_0863_ & _0852_) | (_0820_ & _0771_));
assign _0865_ = _0821_ ? _0849_ : _0864_;
assign _0866_ = ~((_0865_ | _0856_) & (_0850_ | _0821_));
assign _0867_ = _0223_ & _0196_;
assign _0868_ = _0221_ & _0198_;
assign _0869_ = ~(_0219_ & _0200_);
assign _0870_ = ~(_0218_ | _0201_);
assign _0871_ = ~(_0212_ & _0206_);
assign _0872_ = ~((_0211_ | _0209_) & _0871_);
assign _0874_ = ~((_0214_ & _0205_) | _0872_);
assign _0875_ = ~((_0217_ | _0215_) & _0874_);
assign _0876_ = ~(_0875_ | _0870_);
assign _0877_ = ~(_0876_ ^ _0869_);
assign _0878_ = _0220_ & _0199_;
assign _0879_ = _0876_ ^ _0869_;
assign _0880_ = _0878_ ? _0876_ : _0879_;
assign _0881_ = _0868_ ? _0877_ : _0880_;
assign _0882_ = ~(_0222_ & _0197_);
assign _0883_ = _0881_ ^ _0882_;
assign _0885_ = _0867_ ? _0881_ : _0883_;
assign _0886_ = _0842_ & _0826_;
assign _0887_ = ~(_0836_ | _0834_);
assign _0888_ = ~((_0831_ & _0793_) | _0887_);
assign _0889_ = ~((_0838_ | _0837_) & _0888_);
assign _0890_ = ~((_0839_ & _0830_) | _0889_);
assign _0891_ = ~(_0890_ & _0886_);
assign _0892_ = ~((_0845_ | _0843_) & _0891_);
assign _0893_ = ~(_0841_ & _0827_);
assign _0894_ = _0890_ & _0893_;
assign _0896_ = ~((_0846_ | _0825_) & _0894_);
assign _0897_ = _0896_ | _0892_;
assign _0898_ = ~((_0847_ & _0824_) | _0897_);
assign _0899_ = ~((_0848_ | _0823_) & _0898_);
assign _0900_ = ~((_0849_ & _0822_) | _0899_);
assign _0901_ = _0900_ & _0885_;
assign _0902_ = ~(_0901_ & _0866_);
assign _0903_ = ~((_0225_ & _0195_) | _0902_);
assign _0904_ = _0903_ & _0565_;
assign _0905_ = ~((_0564_ | _0559_) & _0904_);
assign valid = ~((_0229_ & _0194_) | _0905_);
endmodule |
module sine_table_11bit
(input c,
input [10:0] angle,
output reg [31:0] sine);
always @(posedge c) begin
case (angle)
11'd0: sine = 32'h0;
11'd1: sine = 32'h3e9d1452;
11'd2: sine = 32'h3f1d1422;
11'd3: sine = 32'h3f6b9dba;
11'd4: sine = 32'h3f9d1360;
11'd5: sine = 32'h3fc45783;
11'd6: sine = 32'h3feb9b2c;
11'd7: sine = 32'h40096f22;
11'd8: sine = 32'h401d1059;
11'd9: sine = 32'h4030b12f;
11'd10: sine = 32'h40445199;
11'd11: sine = 32'h4057f189;
11'd12: sine = 32'h406b90f4;
11'd13: sine = 32'h407f2fce;
11'd14: sine = 32'h40896705;
11'd15: sine = 32'h409335ce;
11'd16: sine = 32'h409d043d;
11'd17: sine = 32'h40a6d24b;
11'd18: sine = 32'h40b09ff2;
11'd19: sine = 32'h40ba6d2b;
11'd20: sine = 32'h40c439f2;
11'd21: sine = 32'h40ce0640;
11'd22: sine = 32'h40d7d20f;
11'd23: sine = 32'h40e19d58;
11'd24: sine = 32'h40eb6817;
11'd25: sine = 32'h40f53244;
11'd26: sine = 32'h40fefbda;
11'd27: sine = 32'h41046269;
11'd28: sine = 32'h41094694;
11'd29: sine = 32'h410e2a6a;
11'd30: sine = 32'h41130de8;
11'd31: sine = 32'h4117f10c;
11'd32: sine = 32'h411cd3d2;
11'd33: sine = 32'h4121b637;
11'd34: sine = 32'h41269838;
11'd35: sine = 32'h412b79d3;
11'd36: sine = 32'h41305b04;
11'd37: sine = 32'h41353bc8;
11'd38: sine = 32'h413a1c1c;
11'd39: sine = 32'h413efbfe;
11'd40: sine = 32'h4143db69;
11'd41: sine = 32'h4148ba5c;
11'd42: sine = 32'h414d98d3;
11'd43: sine = 32'h415276cb;
11'd44: sine = 32'h41575442;
11'd45: sine = 32'h415c3133;
11'd46: sine = 32'h41610d9d;
11'd47: sine = 32'h4165e97c;
11'd48: sine = 32'h416ac4cd;
11'd49: sine = 32'h416f9f8d;
11'd50: sine = 32'h417479ba;
11'd51: sine = 32'h41795350;
11'd52: sine = 32'h417e2c4b;
11'd53: sine = 32'h41818255;
11'd54: sine = 32'h4183ee35;
11'd55: sine = 32'h418659c3;
11'd56: sine = 32'h4188c4ff;
11'd57: sine = 32'h418b2fe6;
11'd58: sine = 32'h418d9a77;
11'd59: sine = 32'h419004b1;
11'd60: sine = 32'h41926e92;
11'd61: sine = 32'h4194d818;
11'd62: sine = 32'h41974143;
11'd63: sine = 32'h4199aa11;
11'd64: sine = 32'h419c127f;
11'd65: sine = 32'h419e7a8e;
11'd66: sine = 32'h41a0e23b;
11'd67: sine = 32'h41a34984;
11'd68: sine = 32'h41a5b069;
11'd69: sine = 32'h41a816e7;
11'd70: sine = 32'h41aa7cfe;
11'd71: sine = 32'h41ace2ac;
11'd72: sine = 32'h41af47ef;
11'd73: sine = 32'h41b1acc6;
11'd74: sine = 32'h41b4112f;
11'd75: sine = 32'h41b67529;
11'd76: sine = 32'h41b8d8b3;
11'd77: sine = 32'h41bb3bcb;
11'd78: sine = 32'h41bd9e6f;
11'd79: sine = 32'h41c0009e;
11'd80: sine = 32'h41c26257;
11'd81: sine = 32'h41c4c398;
11'd82: sine = 32'h41c7245f;
11'd83: sine = 32'h41c984ac;
11'd84: sine = 32'h41cbe47c;
11'd85: sine = 32'h41ce43cf;
11'd86: sine = 32'h41d0a2a2;
11'd87: sine = 32'h41d300f5;
11'd88: sine = 32'h41d55ec6;
11'd89: sine = 32'h41d7bc12;
11'd90: sine = 32'h41da18da;
11'd91: sine = 32'h41dc751c;
11'd92: sine = 32'h41ded0d5;
11'd93: sine = 32'h41e12c05;
11'd94: sine = 32'h41e386aa;
11'd95: sine = 32'h41e5e0c2;
11'd96: sine = 32'h41e83a4d;
11'd97: sine = 32'h41ea9349;
11'd98: sine = 32'h41ecebb3;
11'd99: sine = 32'h41ef438c;
11'd100: sine = 32'h41f19ad1;
11'd101: sine = 32'h41f3f181;
11'd102: sine = 32'h41f6479b;
11'd103: sine = 32'h41f89d1d;
11'd104: sine = 32'h41faf205;
11'd105: sine = 32'h41fd4652;
11'd106: sine = 32'h41ff9a04;
11'd107: sine = 32'h4200f68c;
11'd108: sine = 32'h42021fc6;
11'd109: sine = 32'h420348b0;
11'd110: sine = 32'h42047149;
11'd111: sine = 32'h42059990;
11'd112: sine = 32'h4206c185;
11'd113: sine = 32'h4207e927;
11'd114: sine = 32'h42091075;
11'd115: sine = 32'h420a376e;
11'd116: sine = 32'h420b5e13;
11'd117: sine = 32'h420c8461;
11'd118: sine = 32'h420daa58;
11'd119: sine = 32'h420ecff8;
11'd120: sine = 32'h420ff540;
11'd121: sine = 32'h42111a30;
11'd122: sine = 32'h42123ec5;
11'd123: sine = 32'h42136301;
11'd124: sine = 32'h421486e1;
11'd125: sine = 32'h4215aa66;
11'd126: sine = 32'h4216cd8f;
11'd127: sine = 32'h4217f05b;
11'd128: sine = 32'h421912c8;
11'd129: sine = 32'h421a34d8;
11'd130: sine = 32'h421b5688;
11'd131: sine = 32'h421c77d9;
11'd132: sine = 32'h421d98c9;
11'd133: sine = 32'h421eb958;
11'd134: sine = 32'h421fd984;
11'd135: sine = 32'h4220f94f;
11'd136: sine = 32'h422218b6;
11'd137: sine = 32'h422337b9;
11'd138: sine = 32'h42245657;
11'd139: sine = 32'h42257490;
11'd140: sine = 32'h42269263;
11'd141: sine = 32'h4227afcf;
11'd142: sine = 32'h4228ccd4;
11'd143: sine = 32'h4229e970;
11'd144: sine = 32'h422b05a4;
11'd145: sine = 32'h422c216e;
11'd146: sine = 32'h422d3cce;
11'd147: sine = 32'h422e57c4;
11'd148: sine = 32'h422f724d;
11'd149: sine = 32'h42308c6b;
11'd150: sine = 32'h4231a61b;
11'd151: sine = 32'h4232bf5e;
11'd152: sine = 32'h4233d833;
11'd153: sine = 32'h4234f099;
11'd154: sine = 32'h4236088f;
11'd155: sine = 32'h42372015;
11'd156: sine = 32'h4238372a;
11'd157: sine = 32'h42394dcd;
11'd158: sine = 32'h423a63fe;
11'd159: sine = 32'h423b79bc;
11'd160: sine = 32'h423c8f06;
11'd161: sine = 32'h423da3dc;
11'd162: sine = 32'h423eb83e;
11'd163: sine = 32'h423fcc29;
11'd164: sine = 32'h4240df9e;
11'd165: sine = 32'h4241f29c;
11'd166: sine = 32'h42430523;
11'd167: sine = 32'h42441731;
11'd168: sine = 32'h424528c6;
11'd169: sine = 32'h424639e2;
11'd170: sine = 32'h42474a83;
11'd171: sine = 32'h42485aaa;
11'd172: sine = 32'h42496a54;
11'd173: sine = 32'h424a7983;
11'd174: sine = 32'h424b8835;
11'd175: sine = 32'h424c9669;
11'd176: sine = 32'h424da41f;
11'd177: sine = 32'h424eb156;
11'd178: sine = 32'h424fbe0d;
11'd179: sine = 32'h4250ca45;
11'd180: sine = 32'h4251d5fc;
11'd181: sine = 32'h4252e131;
11'd182: sine = 32'h4253ebe4;
11'd183: sine = 32'h4254f614;
11'd184: sine = 32'h4255ffc1;
11'd185: sine = 32'h425708ea;
11'd186: sine = 32'h4258118f;
11'd187: sine = 32'h425919ae;
11'd188: sine = 32'h425a2147;
11'd189: sine = 32'h425b285a;
11'd190: sine = 32'h425c2ee5;
11'd191: sine = 32'h425d34e9;
11'd192: sine = 32'h425e3a64;
11'd193: sine = 32'h425f3f56;
11'd194: sine = 32'h426043bf;
11'd195: sine = 32'h4261479d;
11'd196: sine = 32'h42624af0;
11'd197: sine = 32'h42634db7;
11'd198: sine = 32'h42644ff3;
11'd199: sine = 32'h426551a1;
11'd200: sine = 32'h426652c2;
11'd201: sine = 32'h42675355;
11'd202: sine = 32'h42685359;
11'd203: sine = 32'h426952ce;
11'd204: sine = 32'h426a51b3;
11'd205: sine = 32'h426b5008;
11'd206: sine = 32'h426c4dcb;
11'd207: sine = 32'h426d4afc;
11'd208: sine = 32'h426e479c;
11'd209: sine = 32'h426f43a8;
11'd210: sine = 32'h42703f20;
11'd211: sine = 32'h42713a05;
11'd212: sine = 32'h42723454;
11'd213: sine = 32'h42732e0f;
11'd214: sine = 32'h42742733;
11'd215: sine = 32'h42751fc0;
11'd216: sine = 32'h427617b7;
11'd217: sine = 32'h42770f15;
11'd218: sine = 32'h427805dc;
11'd219: sine = 32'h4278fc09;
11'd220: sine = 32'h4279f19c;
11'd221: sine = 32'h427ae696;
11'd222: sine = 32'h427bdaf4;
11'd223: sine = 32'h427cceb8;
11'd224: sine = 32'h427dc1df;
11'd225: sine = 32'h427eb46a;
11'd226: sine = 32'h427fa658;
11'd227: sine = 32'h42804bd4;
11'd228: sine = 32'h4280c42d;
11'd229: sine = 32'h42813c36;
11'd230: sine = 32'h4281b3f0;
11'd231: sine = 32'h42822b5a;
11'd232: sine = 32'h4282a273;
11'd233: sine = 32'h4283193c;
11'd234: sine = 32'h42838fb4;
11'd235: sine = 32'h428405db;
11'd236: sine = 32'h42847bb0;
11'd237: sine = 32'h4284f134;
11'd238: sine = 32'h42856665;
11'd239: sine = 32'h4285db45;
11'd240: sine = 32'h42864fd1;
11'd241: sine = 32'h4286c40b;
11'd242: sine = 32'h428737f2;
11'd243: sine = 32'h4287ab86;
11'd244: sine = 32'h42881ec5;
11'd245: sine = 32'h428891b1;
11'd246: sine = 32'h42890449;
11'd247: sine = 32'h4289768c;
11'd248: sine = 32'h4289e87a;
11'd249: sine = 32'h428a5a13;
11'd250: sine = 32'h428acb57;
11'd251: sine = 32'h428b3c45;
11'd252: sine = 32'h428bacdd;
11'd253: sine = 32'h428c1d1f;
11'd254: sine = 32'h428c8d0b;
11'd255: sine = 32'h428cfca0;
11'd256: sine = 32'h428d6bde;
11'd257: sine = 32'h428ddac5;
11'd258: sine = 32'h428e4954;
11'd259: sine = 32'h428eb78b;
11'd260: sine = 32'h428f256b;
11'd261: sine = 32'h428f92f2;
11'd262: sine = 32'h42900021;
11'd263: sine = 32'h42906cf7;
11'd264: sine = 32'h4290d973;
11'd265: sine = 32'h42914597;
11'd266: sine = 32'h4291b160;
11'd267: sine = 32'h42921cd0;
11'd268: sine = 32'h429287e6;
11'd269: sine = 32'h4292f2a1;
11'd270: sine = 32'h42935d02;
11'd271: sine = 32'h4293c708;
11'd272: sine = 32'h429430b2;
11'd273: sine = 32'h42949a02;
11'd274: sine = 32'h429502f5;
11'd275: sine = 32'h42956b8d;
11'd276: sine = 32'h4295d3c8;
11'd277: sine = 32'h42963ba7;
11'd278: sine = 32'h4296a32a;
11'd279: sine = 32'h42970a4f;
11'd280: sine = 32'h42977118;
11'd281: sine = 32'h4297d783;
11'd282: sine = 32'h42983d90;
11'd283: sine = 32'h4298a33f;
11'd284: sine = 32'h42990890;
11'd285: sine = 32'h42996d83;
11'd286: sine = 32'h4299d217;
11'd287: sine = 32'h429a364c;
11'd288: sine = 32'h429a9a22;
11'd289: sine = 32'h429afd99;
11'd290: sine = 32'h429b60b0;
11'd291: sine = 32'h429bc368;
11'd292: sine = 32'h429c25bf;
11'd293: sine = 32'h429c87b6;
11'd294: sine = 32'h429ce94c;
11'd295: sine = 32'h429d4a82;
11'd296: sine = 32'h429dab56;
11'd297: sine = 32'h429e0bc9;
11'd298: sine = 32'h429e6bdb;
11'd299: sine = 32'h429ecb8b;
11'd300: sine = 32'h429f2ad9;
11'd301: sine = 32'h429f89c5;
11'd302: sine = 32'h429fe84f;
11'd303: sine = 32'h42a04676;
11'd304: sine = 32'h42a0a43a;
11'd305: sine = 32'h42a1019b;
11'd306: sine = 32'h42a15e98;
11'd307: sine = 32'h42a1bb32;
11'd308: sine = 32'h42a21768;
11'd309: sine = 32'h42a2733b;
11'd310: sine = 32'h42a2cea9;
11'd311: sine = 32'h42a329b3;
11'd312: sine = 32'h42a38458;
11'd313: sine = 32'h42a3de98;
11'd314: sine = 32'h42a43873;
11'd315: sine = 32'h42a491e9;
11'd316: sine = 32'h42a4eaf9;
11'd317: sine = 32'h42a543a3;
11'd318: sine = 32'h42a59be8;
11'd319: sine = 32'h42a5f3c6;
11'd320: sine = 32'h42a64b3e;
11'd321: sine = 32'h42a6a250;
11'd322: sine = 32'h42a6f8fb;
11'd323: sine = 32'h42a74f3e;
11'd324: sine = 32'h42a7a51b;
11'd325: sine = 32'h42a7fa90;
11'd326: sine = 32'h42a84f9d;
11'd327: sine = 32'h42a8a443;
11'd328: sine = 32'h42a8f881;
11'd329: sine = 32'h42a94c56;
11'd330: sine = 32'h42a99fc3;
11'd331: sine = 32'h42a9f2c7;
11'd332: sine = 32'h42aa4563;
11'd333: sine = 32'h42aa9795;
11'd334: sine = 32'h42aae95e;
11'd335: sine = 32'h42ab3abe;
11'd336: sine = 32'h42ab8bb4;
11'd337: sine = 32'h42abdc41;
11'd338: sine = 32'h42ac2c63;
11'd339: sine = 32'h42ac7c1b;
11'd340: sine = 32'h42accb69;
11'd341: sine = 32'h42ad1a4c;
11'd342: sine = 32'h42ad68c4;
11'd343: sine = 32'h42adb6d2;
11'd344: sine = 32'h42ae0474;
11'd345: sine = 32'h42ae51ab;
11'd346: sine = 32'h42ae9e76;
11'd347: sine = 32'h42aeead6;
11'd348: sine = 32'h42af36ca;
11'd349: sine = 32'h42af8252;
11'd350: sine = 32'h42afcd6d;
11'd351: sine = 32'h42b0181c;
11'd352: sine = 32'h42b0625e;
11'd353: sine = 32'h42b0ac34;
11'd354: sine = 32'h42b0f59c;
11'd355: sine = 32'h42b13e98;
11'd356: sine = 32'h42b18726;
11'd357: sine = 32'h42b1cf46;
11'd358: sine = 32'h42b216f9;
11'd359: sine = 32'h42b25e3e;
11'd360: sine = 32'h42b2a515;
11'd361: sine = 32'h42b2eb7e;
11'd362: sine = 32'h42b33179;
11'd363: sine = 32'h42b37705;
11'd364: sine = 32'h42b3bc22;
11'd365: sine = 32'h42b400d0;
11'd366: sine = 32'h42b4450f;
11'd367: sine = 32'h42b488e0;
11'd368: sine = 32'h42b4cc40;
11'd369: sine = 32'h42b50f32;
11'd370: sine = 32'h42b551b3;
11'd371: sine = 32'h42b593c5;
11'd372: sine = 32'h42b5d566;
11'd373: sine = 32'h42b61698;
11'd374: sine = 32'h42b65759;
11'd375: sine = 32'h42b697aa;
11'd376: sine = 32'h42b6d78a;
11'd377: sine = 32'h42b716f9;
11'd378: sine = 32'h42b755f8;
11'd379: sine = 32'h42b79485;
11'd380: sine = 32'h42b7d2a1;
11'd381: sine = 32'h42b8104c;
11'd382: sine = 32'h42b84d85;
11'd383: sine = 32'h42b88a4c;
11'd384: sine = 32'h42b8c6a2;
11'd385: sine = 32'h42b90285;
11'd386: sine = 32'h42b93df7;
11'd387: sine = 32'h42b978f6;
11'd388: sine = 32'h42b9b383;
11'd389: sine = 32'h42b9ed9d;
11'd390: sine = 32'h42ba2745;
11'd391: sine = 32'h42ba6079;
11'd392: sine = 32'h42ba993b;
11'd393: sine = 32'h42bad18a;
11'd394: sine = 32'h42bb0965;
11'd395: sine = 32'h42bb40cd;
11'd396: sine = 32'h42bb77c2;
11'd397: sine = 32'h42bbae43;
11'd398: sine = 32'h42bbe450;
11'd399: sine = 32'h42bc19e9;
11'd400: sine = 32'h42bc4f0e;
11'd401: sine = 32'h42bc83bf;
11'd402: sine = 32'h42bcb7fc;
11'd403: sine = 32'h42bcebc4;
11'd404: sine = 32'h42bd1f18;
11'd405: sine = 32'h42bd51f7;
11'd406: sine = 32'h42bd8462;
11'd407: sine = 32'h42bdb657;
11'd408: sine = 32'h42bde7d8;
11'd409: sine = 32'h42be18e3;
11'd410: sine = 32'h42be4979;
11'd411: sine = 32'h42be799a;
11'd412: sine = 32'h42bea945;
11'd413: sine = 32'h42bed87a;
11'd414: sine = 32'h42bf073a;
11'd415: sine = 32'h42bf3584;
11'd416: sine = 32'h42bf6358;
11'd417: sine = 32'h42bf90b6;
11'd418: sine = 32'h42bfbd9e;
11'd419: sine = 32'h42bfea10;
11'd420: sine = 32'h42c0160b;
11'd421: sine = 32'h42c04190;
11'd422: sine = 32'h42c06c9e;
11'd423: sine = 32'h42c09735;
11'd424: sine = 32'h42c0c156;
11'd425: sine = 32'h42c0eaff;
11'd426: sine = 32'h42c11432;
11'd427: sine = 32'h42c13cee;
11'd428: sine = 32'h42c16532;
11'd429: sine = 32'h42c18cff;
11'd430: sine = 32'h42c1b455;
11'd431: sine = 32'h42c1db33;
11'd432: sine = 32'h42c2019a;
11'd433: sine = 32'h42c22789;
11'd434: sine = 32'h42c24d00;
11'd435: sine = 32'h42c271ff;
11'd436: sine = 32'h42c29686;
11'd437: sine = 32'h42c2ba96;
11'd438: sine = 32'h42c2de2d;
11'd439: sine = 32'h42c3014c;
11'd440: sine = 32'h42c323f3;
11'd441: sine = 32'h42c34621;
11'd442: sine = 32'h42c367d7;
11'd443: sine = 32'h42c38915;
11'd444: sine = 32'h42c3a9d9;
11'd445: sine = 32'h42c3ca25;
11'd446: sine = 32'h42c3e9f9;
11'd447: sine = 32'h42c40953;
11'd448: sine = 32'h42c42835;
11'd449: sine = 32'h42c4469d;
11'd450: sine = 32'h42c4648d;
11'd451: sine = 32'h42c48203;
11'd452: sine = 32'h42c49f00;
11'd453: sine = 32'h42c4bb84;
11'd454: sine = 32'h42c4d78e;
11'd455: sine = 32'h42c4f320;
11'd456: sine = 32'h42c50e37;
11'd457: sine = 32'h42c528d5;
11'd458: sine = 32'h42c542f9;
11'd459: sine = 32'h42c55ca4;
11'd460: sine = 32'h42c575d5;
11'd461: sine = 32'h42c58e8c;
11'd462: sine = 32'h42c5a6ca;
11'd463: sine = 32'h42c5be8d;
11'd464: sine = 32'h42c5d5d6;
11'd465: sine = 32'h42c5eca6;
11'd466: sine = 32'h42c602fb;
11'd467: sine = 32'h42c618d6;
11'd468: sine = 32'h42c62e37;
11'd469: sine = 32'h42c6431e;
11'd470: sine = 32'h42c6578a;
11'd471: sine = 32'h42c66b7c;
11'd472: sine = 32'h42c67ef4;
11'd473: sine = 32'h42c691f1;
11'd474: sine = 32'h42c6a474;
11'd475: sine = 32'h42c6b67c;
11'd476: sine = 32'h42c6c809;
11'd477: sine = 32'h42c6d91c;
11'd478: sine = 32'h42c6e9b5;
11'd479: sine = 32'h42c6f9d2;
11'd480: sine = 32'h42c70975;
11'd481: sine = 32'h42c7189d;
11'd482: sine = 32'h42c7274b;
11'd483: sine = 32'h42c7357d;
11'd484: sine = 32'h42c74335;
11'd485: sine = 32'h42c75071;
11'd486: sine = 32'h42c75d33;
11'd487: sine = 32'h42c7697a;
11'd488: sine = 32'h42c77545;
11'd489: sine = 32'h42c78096;
11'd490: sine = 32'h42c78b6c;
11'd491: sine = 32'h42c795c6;
11'd492: sine = 32'h42c79fa6;
11'd493: sine = 32'h42c7a90a;
11'd494: sine = 32'h42c7b1f3;
11'd495: sine = 32'h42c7ba61;
11'd496: sine = 32'h42c7c254;
11'd497: sine = 32'h42c7c9cb;
11'd498: sine = 32'h42c7d0c8;
11'd499: sine = 32'h42c7d749;
11'd500: sine = 32'h42c7dd4e;
11'd501: sine = 32'h42c7e2d9;
11'd502: sine = 32'h42c7e7e8;
11'd503: sine = 32'h42c7ec7c;
11'd504: sine = 32'h42c7f094;
11'd505: sine = 32'h42c7f432;
11'd506: sine = 32'h42c7f753;
11'd507: sine = 32'h42c7f9fa;
11'd508: sine = 32'h42c7fc25;
11'd509: sine = 32'h42c7fdd5;
11'd510: sine = 32'h42c7ff09;
11'd511: sine = 32'h42c7ffc2;
11'd512: sine = 32'h42c80000;
11'd513: sine = 32'h42c7ffc2;
11'd514: sine = 32'h42c7ff09;
11'd515: sine = 32'h42c7fdd5;
11'd516: sine = 32'h42c7fc25;
11'd517: sine = 32'h42c7f9fa;
11'd518: sine = 32'h42c7f753;
11'd519: sine = 32'h42c7f432;
11'd520: sine = 32'h42c7f094;
11'd521: sine = 32'h42c7ec7c;
11'd522: sine = 32'h42c7e7e8;
11'd523: sine = 32'h42c7e2d9;
11'd524: sine = 32'h42c7dd4e;
11'd525: sine = 32'h42c7d749;
11'd526: sine = 32'h42c7d0c8;
11'd527: sine = 32'h42c7c9cb;
11'd528: sine = 32'h42c7c254;
11'd529: sine = 32'h42c7ba61;
11'd530: sine = 32'h42c7b1f3;
11'd531: sine = 32'h42c7a90a;
11'd532: sine = 32'h42c79fa6;
11'd533: sine = 32'h42c795c6;
11'd534: sine = 32'h42c78b6c;
11'd535: sine = 32'h42c78096;
11'd536: sine = 32'h42c77546;
11'd537: sine = 32'h42c7697a;
11'd538: sine = 32'h42c75d33;
11'd539: sine = 32'h42c75071;
11'd540: sine = 32'h42c74335;
11'd541: sine = 32'h42c7357d;
11'd542: sine = 32'h42c7274b;
11'd543: sine = 32'h42c7189d;
11'd544: sine = 32'h42c70975;
11'd545: sine = 32'h42c6f9d2;
11'd546: sine = 32'h42c6e9b5;
11'd547: sine = 32'h42c6d91c;
11'd548: sine = 32'h42c6c809;
11'd549: sine = 32'h42c6b67c;
11'd550: sine = 32'h42c6a474;
11'd551: sine = 32'h42c691f1;
11'd552: sine = 32'h42c67ef4;
11'd553: sine = 32'h42c66b7c;
11'd554: sine = 32'h42c6578a;
11'd555: sine = 32'h42c6431e;
11'd556: sine = 32'h42c62e37;
11'd557: sine = 32'h42c618d6;
11'd558: sine = 32'h42c602fb;
11'd559: sine = 32'h42c5eca6;
11'd560: sine = 32'h42c5d5d6;
11'd561: sine = 32'h42c5be8d;
11'd562: sine = 32'h42c5a6ca;
11'd563: sine = 32'h42c58e8c;
11'd564: sine = 32'h42c575d5;
11'd565: sine = 32'h42c55ca4;
11'd566: sine = 32'h42c542fa;
11'd567: sine = 32'h42c528d5;
11'd568: sine = 32'h42c50e37;
11'd569: sine = 32'h42c4f320;
11'd570: sine = 32'h42c4d78f;
11'd571: sine = 32'h42c4bb84;
11'd572: sine = 32'h42c49f00;
11'd573: sine = 32'h42c48203;
11'd574: sine = 32'h42c4648d;
11'd575: sine = 32'h42c4469d;
11'd576: sine = 32'h42c42835;
11'd577: sine = 32'h42c40953;
11'd578: sine = 32'h42c3e9f9;
11'd579: sine = 32'h42c3ca26;
11'd580: sine = 32'h42c3a9da;
11'd581: sine = 32'h42c38915;
11'd582: sine = 32'h42c367d7;
11'd583: sine = 32'h42c34621;
11'd584: sine = 32'h42c323f3;
11'd585: sine = 32'h42c3014c;
11'd586: sine = 32'h42c2de2d;
11'd587: sine = 32'h42c2ba96;
11'd588: sine = 32'h42c29687;
11'd589: sine = 32'h42c271ff;
11'd590: sine = 32'h42c24d00;
11'd591: sine = 32'h42c22789;
11'd592: sine = 32'h42c2019a;
11'd593: sine = 32'h42c1db33;
11'd594: sine = 32'h42c1b455;
11'd595: sine = 32'h42c18cff;
11'd596: sine = 32'h42c16532;
11'd597: sine = 32'h42c13cee;
11'd598: sine = 32'h42c11432;
11'd599: sine = 32'h42c0eaff;
11'd600: sine = 32'h42c0c156;
11'd601: sine = 32'h42c09735;
11'd602: sine = 32'h42c06c9e;
11'd603: sine = 32'h42c04190;
11'd604: sine = 32'h42c0160b;
11'd605: sine = 32'h42bfea10;
11'd606: sine = 32'h42bfbd9e;
11'd607: sine = 32'h42bf90b6;
11'd608: sine = 32'h42bf6358;
11'd609: sine = 32'h42bf3584;
11'd610: sine = 32'h42bf073a;
11'd611: sine = 32'h42bed87b;
11'd612: sine = 32'h42bea945;
11'd613: sine = 32'h42be799a;
11'd614: sine = 32'h42be4979;
11'd615: sine = 32'h42be18e3;
11'd616: sine = 32'h42bde7d8;
11'd617: sine = 32'h42bdb657;
11'd618: sine = 32'h42bd8462;
11'd619: sine = 32'h42bd51f8;
11'd620: sine = 32'h42bd1f18;
11'd621: sine = 32'h42bcebc5;
11'd622: sine = 32'h42bcb7fc;
11'd623: sine = 32'h42bc83c0;
11'd624: sine = 32'h42bc4f0f;
11'd625: sine = 32'h42bc19e9;
11'd626: sine = 32'h42bbe450;
11'd627: sine = 32'h42bbae43;
11'd628: sine = 32'h42bb77c2;
11'd629: sine = 32'h42bb40ce;
11'd630: sine = 32'h42bb0965;
11'd631: sine = 32'h42bad18a;
11'd632: sine = 32'h42ba993b;
11'd633: sine = 32'h42ba607a;
11'd634: sine = 32'h42ba2745;
11'd635: sine = 32'h42b9ed9d;
11'd636: sine = 32'h42b9b383;
11'd637: sine = 32'h42b978f6;
11'd638: sine = 32'h42b93df7;
11'd639: sine = 32'h42b90286;
11'd640: sine = 32'h42b8c6a2;
11'd641: sine = 32'h42b88a4c;
11'd642: sine = 32'h42b84d85;
11'd643: sine = 32'h42b8104c;
11'd644: sine = 32'h42b7d2a1;
11'd645: sine = 32'h42b79485;
11'd646: sine = 32'h42b755f8;
11'd647: sine = 32'h42b716fa;
11'd648: sine = 32'h42b6d78a;
11'd649: sine = 32'h42b697aa;
11'd650: sine = 32'h42b65759;
11'd651: sine = 32'h42b61698;
11'd652: sine = 32'h42b5d567;
11'd653: sine = 32'h42b593c5;
11'd654: sine = 32'h42b551b3;
11'd655: sine = 32'h42b50f32;
11'd656: sine = 32'h42b4cc41;
11'd657: sine = 32'h42b488e0;
11'd658: sine = 32'h42b44510;
11'd659: sine = 32'h42b400d0;
11'd660: sine = 32'h42b3bc22;
11'd661: sine = 32'h42b37705;
11'd662: sine = 32'h42b33179;
11'd663: sine = 32'h42b2eb7f;
11'd664: sine = 32'h42b2a516;
11'd665: sine = 32'h42b25e3f;
11'd666: sine = 32'h42b216fa;
11'd667: sine = 32'h42b1cf47;
11'd668: sine = 32'h42b18726;
11'd669: sine = 32'h42b13e98;
11'd670: sine = 32'h42b0f59d;
11'd671: sine = 32'h42b0ac34;
11'd672: sine = 32'h42b0625f;
11'd673: sine = 32'h42b0181c;
11'd674: sine = 32'h42afcd6d;
11'd675: sine = 32'h42af8252;
11'd676: sine = 32'h42af36ca;
11'd677: sine = 32'h42aeead6;
11'd678: sine = 32'h42ae9e77;
11'd679: sine = 32'h42ae51ab;
11'd680: sine = 32'h42ae0474;
11'd681: sine = 32'h42adb6d2;
11'd682: sine = 32'h42ad68c5;
11'd683: sine = 32'h42ad1a4c;
11'd684: sine = 32'h42accb69;
11'd685: sine = 32'h42ac7c1c;
11'd686: sine = 32'h42ac2c63;
11'd687: sine = 32'h42abdc41;
11'd688: sine = 32'h42ab8bb5;
11'd689: sine = 32'h42ab3abf;
11'd690: sine = 32'h42aae95f;
11'd691: sine = 32'h42aa9795;
11'd692: sine = 32'h42aa4563;
11'd693: sine = 32'h42a9f2c8;
11'd694: sine = 32'h42a99fc3;
11'd695: sine = 32'h42a94c56;
11'd696: sine = 32'h42a8f881;
11'd697: sine = 32'h42a8a443;
11'd698: sine = 32'h42a84f9e;
11'd699: sine = 32'h42a7fa90;
11'd700: sine = 32'h42a7a51b;
11'd701: sine = 32'h42a74f3f;
11'd702: sine = 32'h42a6f8fb;
11'd703: sine = 32'h42a6a250;
11'd704: sine = 32'h42a64b3f;
11'd705: sine = 32'h42a5f3c7;
11'd706: sine = 32'h42a59be8;
11'd707: sine = 32'h42a543a4;
11'd708: sine = 32'h42a4eaf9;
11'd709: sine = 32'h42a491e9;
11'd710: sine = 32'h42a43873;
11'd711: sine = 32'h42a3de98;
11'd712: sine = 32'h42a38458;
11'd713: sine = 32'h42a329b3;
11'd714: sine = 32'h42a2cea9;
11'd715: sine = 32'h42a2733b;
11'd716: sine = 32'h42a21769;
11'd717: sine = 32'h42a1bb33;
11'd718: sine = 32'h42a15e99;
11'd719: sine = 32'h42a1019b;
11'd720: sine = 32'h42a0a43a;
11'd721: sine = 32'h42a04676;
11'd722: sine = 32'h429fe84f;
11'd723: sine = 32'h429f89c6;
11'd724: sine = 32'h429f2ada;
11'd725: sine = 32'h429ecb8c;
11'd726: sine = 32'h429e6bdc;
11'd727: sine = 32'h429e0bca;
11'd728: sine = 32'h429dab57;
11'd729: sine = 32'h429d4a82;
11'd730: sine = 32'h429ce94d;
11'd731: sine = 32'h429c87b6;
11'd732: sine = 32'h429c25bf;
11'd733: sine = 32'h429bc368;
11'd734: sine = 32'h429b60b1;
11'd735: sine = 32'h429afd9a;
11'd736: sine = 32'h429a9a23;
11'd737: sine = 32'h429a364d;
11'd738: sine = 32'h4299d218;
11'd739: sine = 32'h42996d83;
11'd740: sine = 32'h42990891;
11'd741: sine = 32'h4298a340;
11'd742: sine = 32'h42983d90;
11'd743: sine = 32'h4297d783;
11'd744: sine = 32'h42977118;
11'd745: sine = 32'h42970a50;
11'd746: sine = 32'h4296a32a;
11'd747: sine = 32'h42963ba8;
11'd748: sine = 32'h4295d3c9;
11'd749: sine = 32'h42956b8d;
11'd750: sine = 32'h429502f6;
11'd751: sine = 32'h42949a02;
11'd752: sine = 32'h429430b3;
11'd753: sine = 32'h4293c708;
11'd754: sine = 32'h42935d02;
11'd755: sine = 32'h4292f2a2;
11'd756: sine = 32'h429287e6;
11'd757: sine = 32'h42921cd1;
11'd758: sine = 32'h4291b161;
11'd759: sine = 32'h42914597;
11'd760: sine = 32'h4290d974;
11'd761: sine = 32'h42906cf7;
11'd762: sine = 32'h42900021;
11'd763: sine = 32'h428f92f3;
11'd764: sine = 32'h428f256b;
11'd765: sine = 32'h428eb78c;
11'd766: sine = 32'h428e4954;
11'd767: sine = 32'h428ddac5;
11'd768: sine = 32'h428d6bde;
11'd769: sine = 32'h428cfca0;
11'd770: sine = 32'h428c8d0b;
11'd771: sine = 32'h428c1d20;
11'd772: sine = 32'h428bacde;
11'd773: sine = 32'h428b3c45;
11'd774: sine = 32'h428acb57;
11'd775: sine = 32'h428a5a13;
11'd776: sine = 32'h4289e87a;
11'd777: sine = 32'h4289768c;
11'd778: sine = 32'h42890449;
11'd779: sine = 32'h428891b2;
11'd780: sine = 32'h42881ec6;
11'd781: sine = 32'h4287ab86;
11'd782: sine = 32'h428737f3;
11'd783: sine = 32'h4286c40c;
11'd784: sine = 32'h42864fd2;
11'd785: sine = 32'h4285db45;
11'd786: sine = 32'h42856666;
11'd787: sine = 32'h4284f134;
11'd788: sine = 32'h42847bb0;
11'd789: sine = 32'h428405db;
11'd790: sine = 32'h42838fb4;
11'd791: sine = 32'h4283193c;
11'd792: sine = 32'h4282a273;
11'd793: sine = 32'h42822b5a;
11'd794: sine = 32'h4281b3f0;
11'd795: sine = 32'h42813c37;
11'd796: sine = 32'h4280c42d;
11'd797: sine = 32'h42804bd4;
11'd798: sine = 32'h427fa659;
11'd799: sine = 32'h427eb46b;
11'd800: sine = 32'h427dc1e0;
11'd801: sine = 32'h427cceb9;
11'd802: sine = 32'h427bdaf6;
11'd803: sine = 32'h427ae697;
11'd804: sine = 32'h4279f19d;
11'd805: sine = 32'h4278fc0a;
11'd806: sine = 32'h427805dd;
11'd807: sine = 32'h42770f16;
11'd808: sine = 32'h427617b8;
11'd809: sine = 32'h42751fc2;
11'd810: sine = 32'h42742734;
11'd811: sine = 32'h42732e10;
11'd812: sine = 32'h42723456;
11'd813: sine = 32'h42713a06;
11'd814: sine = 32'h42703f22;
11'd815: sine = 32'h426f43a9;
11'd816: sine = 32'h426e479d;
11'd817: sine = 32'h426d4afe;
11'd818: sine = 32'h426c4dcc;
11'd819: sine = 32'h426b5009;
11'd820: sine = 32'h426a51b4;
11'd821: sine = 32'h426952cf;
11'd822: sine = 32'h4268535a;
11'd823: sine = 32'h42675356;
11'd824: sine = 32'h426652c3;
11'd825: sine = 32'h426551a2;
11'd826: sine = 32'h42644ff4;
11'd827: sine = 32'h42634db8;
11'd828: sine = 32'h42624af1;
11'd829: sine = 32'h4261479e;
11'd830: sine = 32'h426043c0;
11'd831: sine = 32'h425f3f57;
11'd832: sine = 32'h425e3a65;
11'd833: sine = 32'h425d34ea;
11'd834: sine = 32'h425c2ee6;
11'd835: sine = 32'h425b285b;
11'd836: sine = 32'h425a2148;
11'd837: sine = 32'h425919af;
11'd838: sine = 32'h42581190;
11'd839: sine = 32'h425708ec;
11'd840: sine = 32'h4255ffc3;
11'd841: sine = 32'h4254f616;
11'd842: sine = 32'h4253ebe5;
11'd843: sine = 32'h4252e132;
11'd844: sine = 32'h4251d5fd;
11'd845: sine = 32'h4250ca46;
11'd846: sine = 32'h424fbe0f;
11'd847: sine = 32'h424eb157;
11'd848: sine = 32'h424da420;
11'd849: sine = 32'h424c966a;
11'd850: sine = 32'h424b8836;
11'd851: sine = 32'h424a7984;
11'd852: sine = 32'h42496a56;
11'd853: sine = 32'h42485aab;
11'd854: sine = 32'h42474a84;
11'd855: sine = 32'h424639e3;
11'd856: sine = 32'h424528c7;
11'd857: sine = 32'h42441732;
11'd858: sine = 32'h42430524;
11'd859: sine = 32'h4241f29d;
11'd860: sine = 32'h4240df9f;
11'd861: sine = 32'h423fcc2a;
11'd862: sine = 32'h423eb83f;
11'd863: sine = 32'h423da3de;
11'd864: sine = 32'h423c8f08;
11'd865: sine = 32'h423b79bd;
11'd866: sine = 32'h423a63ff;
11'd867: sine = 32'h42394dce;
11'd868: sine = 32'h4238372b;
11'd869: sine = 32'h42372016;
11'd870: sine = 32'h42360890;
11'd871: sine = 32'h4234f09a;
11'd872: sine = 32'h4233d834;
11'd873: sine = 32'h4232bf60;
11'd874: sine = 32'h4231a61d;
11'd875: sine = 32'h42308c6c;
11'd876: sine = 32'h422f724f;
11'd877: sine = 32'h422e57c5;
11'd878: sine = 32'h422d3cd0;
11'd879: sine = 32'h422c2170;
11'd880: sine = 32'h422b05a5;
11'd881: sine = 32'h4229e972;
11'd882: sine = 32'h4228ccd5;
11'd883: sine = 32'h4227afd0;
11'd884: sine = 32'h42269264;
11'd885: sine = 32'h42257491;
11'd886: sine = 32'h42245658;
11'd887: sine = 32'h422337ba;
11'd888: sine = 32'h422218b7;
11'd889: sine = 32'h4220f950;
11'd890: sine = 32'h421fd986;
11'd891: sine = 32'h421eb959;
11'd892: sine = 32'h421d98ca;
11'd893: sine = 32'h421c77da;
11'd894: sine = 32'h421b568a;
11'd895: sine = 32'h421a34d9;
11'd896: sine = 32'h421912ca;
11'd897: sine = 32'h4217f05c;
11'd898: sine = 32'h4216cd90;
11'd899: sine = 32'h4215aa68;
11'd900: sine = 32'h421486e3;
11'd901: sine = 32'h42136302;
11'd902: sine = 32'h42123ec7;
11'd903: sine = 32'h42111a31;
11'd904: sine = 32'h420ff542;
11'd905: sine = 32'h420ecffa;
11'd906: sine = 32'h420daa59;
11'd907: sine = 32'h420c8462;
11'd908: sine = 32'h420b5e14;
11'd909: sine = 32'h420a3770;
11'd910: sine = 32'h42091076;
11'd911: sine = 32'h4207e928;
11'd912: sine = 32'h4206c187;
11'd913: sine = 32'h42059992;
11'd914: sine = 32'h4204714a;
11'd915: sine = 32'h420348b1;
11'd916: sine = 32'h42021fc7;
11'd917: sine = 32'h4200f68d;
11'd918: sine = 32'h41ff9a06;
11'd919: sine = 32'h41fd4655;
11'd920: sine = 32'h41faf208;
11'd921: sine = 32'h41f89d1f;
11'd922: sine = 32'h41f6479e;
11'd923: sine = 32'h41f3f184;
11'd924: sine = 32'h41f19ad4;
11'd925: sine = 32'h41ef438f;
11'd926: sine = 32'h41ecebb6;
11'd927: sine = 32'h41ea934b;
11'd928: sine = 32'h41e83a50;
11'd929: sine = 32'h41e5e0c5;
11'd930: sine = 32'h41e386ac;
11'd931: sine = 32'h41e12c07;
11'd932: sine = 32'h41ded0d8;
11'd933: sine = 32'h41dc751e;
11'd934: sine = 32'h41da18dd;
11'd935: sine = 32'h41d7bc15;
11'd936: sine = 32'h41d55ec8;
11'd937: sine = 32'h41d300f8;
11'd938: sine = 32'h41d0a2a5;
11'd939: sine = 32'h41ce43d2;
11'd940: sine = 32'h41cbe47f;
11'd941: sine = 32'h41c984af;
11'd942: sine = 32'h41c72462;
11'd943: sine = 32'h41c4c39b;
11'd944: sine = 32'h41c2625a;
11'd945: sine = 32'h41c000a1;
11'd946: sine = 32'h41bd9e72;
11'd947: sine = 32'h41bb3bce;
11'd948: sine = 32'h41b8d8b6;
11'd949: sine = 32'h41b6752c;
11'd950: sine = 32'h41b41132;
11'd951: sine = 32'h41b1acc9;
11'd952: sine = 32'h41af47f2;
11'd953: sine = 32'h41ace2af;
11'd954: sine = 32'h41aa7d01;
11'd955: sine = 32'h41a816ea;
11'd956: sine = 32'h41a5b06b;
11'd957: sine = 32'h41a34987;
11'd958: sine = 32'h41a0e23d;
11'd959: sine = 32'h419e7a91;
11'd960: sine = 32'h419c1282;
11'd961: sine = 32'h4199aa13;
11'd962: sine = 32'h41974146;
11'd963: sine = 32'h4194d81b;
11'd964: sine = 32'h41926e94;
11'd965: sine = 32'h419004b3;
11'd966: sine = 32'h418d9a79;
11'd967: sine = 32'h418b2fe8;
11'd968: sine = 32'h4188c501;
11'd969: sine = 32'h418659c6;
11'd970: sine = 32'h4183ee38;
11'd971: sine = 32'h41818258;
11'd972: sine = 32'h417e2c51;
11'd973: sine = 32'h41795355;
11'd974: sine = 32'h417479bf;
11'd975: sine = 32'h416f9f93;
11'd976: sine = 32'h416ac4d3;
11'd977: sine = 32'h4165e982;
11'd978: sine = 32'h41610da3;
11'd979: sine = 32'h415c3139;
11'd980: sine = 32'h41575447;
11'd981: sine = 32'h415276d1;
11'd982: sine = 32'h414d98d9;
11'd983: sine = 32'h4148ba62;
11'd984: sine = 32'h4143db6f;
11'd985: sine = 32'h413efc03;
11'd986: sine = 32'h413a1c22;
11'd987: sine = 32'h41353bce;
11'd988: sine = 32'h41305b0a;
11'd989: sine = 32'h412b79d9;
11'd990: sine = 32'h4126983e;
11'd991: sine = 32'h4121b63d;
11'd992: sine = 32'h411cd3d8;
11'd993: sine = 32'h4117f112;
11'd994: sine = 32'h41130dee;
11'd995: sine = 32'h410e2a70;
11'd996: sine = 32'h4109469a;
11'd997: sine = 32'h4104626f;
11'd998: sine = 32'h40fefbe5;
11'd999: sine = 32'h40f5324f;
11'd1000: sine = 32'h40eb6822;
11'd1001: sine = 32'h40e19d64;
11'd1002: sine = 32'h40d7d21a;
11'd1003: sine = 32'h40ce064b;
11'd1004: sine = 32'h40c439fd;
11'd1005: sine = 32'h40ba6d37;
11'd1006: sine = 32'h40b09ffd;
11'd1007: sine = 32'h40a6d256;
11'd1008: sine = 32'h409d0448;
11'd1009: sine = 32'h409335da;
11'd1010: sine = 32'h40896710;
11'd1011: sine = 32'h407f2fe4;
11'd1012: sine = 32'h406b910a;
11'd1013: sine = 32'h4057f19f;
11'd1014: sine = 32'h404451af;
11'd1015: sine = 32'h4030b146;
11'd1016: sine = 32'h401d1070;
11'd1017: sine = 32'h40096f38;
11'd1018: sine = 32'h3feb9b59;
11'd1019: sine = 32'h3fc457b0;
11'd1020: sine = 32'h3f9d138d;
11'd1021: sine = 32'h3f6b9e14;
11'd1022: sine = 32'h3f1d147c;
11'd1023: sine = 32'h3e9d1506;
11'd1024: sine = 32'h36b3d148;
11'd1025: sine = 32'hbe9d139f;
11'd1026: sine = 32'hbf1d13c8;
11'd1027: sine = 32'hbf6b9d60;
11'd1028: sine = 32'hbf9d1333;
11'd1029: sine = 32'hbfc45756;
11'd1030: sine = 32'hbfeb9aff;
11'd1031: sine = 32'hc0096f0b;
11'd1032: sine = 32'hc01d1043;
11'd1033: sine = 32'hc030b119;
11'd1034: sine = 32'hc0445182;
11'd1035: sine = 32'hc057f173;
11'd1036: sine = 32'hc06b90de;
11'd1037: sine = 32'hc07f2fb7;
11'd1038: sine = 32'hc08966fa;
11'd1039: sine = 32'hc09335c3;
11'd1040: sine = 32'hc09d0432;
11'd1041: sine = 32'hc0a6d23f;
11'd1042: sine = 32'hc0b09fe6;
11'd1043: sine = 32'hc0ba6d20;
11'd1044: sine = 32'hc0c439e7;
11'd1045: sine = 32'hc0ce0635;
11'd1046: sine = 32'hc0d7d204;
11'd1047: sine = 32'hc0e19d4d;
11'd1048: sine = 32'hc0eb680c;
11'd1049: sine = 32'hc0f53239;
11'd1050: sine = 32'hc0fefbcf;
11'd1051: sine = 32'hc1046264;
11'd1052: sine = 32'hc109468f;
11'd1053: sine = 32'hc10e2a65;
11'd1054: sine = 32'hc1130de3;
11'd1055: sine = 32'hc117f106;
11'd1056: sine = 32'hc11cd3cc;
11'd1057: sine = 32'hc121b631;
11'd1058: sine = 32'hc1269833;
11'd1059: sine = 32'hc12b79cd;
11'd1060: sine = 32'hc1305afe;
11'd1061: sine = 32'hc1353bc2;
11'd1062: sine = 32'hc13a1c17;
11'd1063: sine = 32'hc13efbf8;
11'd1064: sine = 32'hc143db64;
11'd1065: sine = 32'hc148ba57;
11'd1066: sine = 32'hc14d98ce;
11'd1067: sine = 32'hc15276c6;
11'd1068: sine = 32'hc157543c;
11'd1069: sine = 32'hc15c312e;
11'd1070: sine = 32'hc1610d98;
11'd1071: sine = 32'hc165e976;
11'd1072: sine = 32'hc16ac4c8;
11'd1073: sine = 32'hc16f9f88;
11'd1074: sine = 32'hc17479b4;
11'd1075: sine = 32'hc179534a;
11'd1076: sine = 32'hc17e2c46;
11'd1077: sine = 32'hc1818252;
11'd1078: sine = 32'hc183ee32;
11'd1079: sine = 32'hc18659c0;
11'd1080: sine = 32'hc188c4fc;
11'd1081: sine = 32'hc18b2fe3;
11'd1082: sine = 32'hc18d9a74;
11'd1083: sine = 32'hc19004ae;
11'd1084: sine = 32'hc1926e8f;
11'd1085: sine = 32'hc194d815;
11'd1086: sine = 32'hc1974140;
11'd1087: sine = 32'hc199aa0e;
11'd1088: sine = 32'hc19c127d;
11'd1089: sine = 32'hc19e7a8b;
11'd1090: sine = 32'hc1a0e238;
11'd1091: sine = 32'hc1a34981;
11'd1092: sine = 32'hc1a5b066;
11'd1093: sine = 32'hc1a816e5;
11'd1094: sine = 32'hc1aa7cfb;
11'd1095: sine = 32'hc1ace2a9;
11'd1096: sine = 32'hc1af47ec;
11'd1097: sine = 32'hc1b1acc3;
11'd1098: sine = 32'hc1b4112c;
11'd1099: sine = 32'hc1b67527;
11'd1100: sine = 32'hc1b8d8b0;
11'd1101: sine = 32'hc1bb3bc8;
11'd1102: sine = 32'hc1bd9e6c;
11'd1103: sine = 32'hc1c0009c;
11'd1104: sine = 32'hc1c26254;
11'd1105: sine = 32'hc1c4c395;
11'd1106: sine = 32'hc1c7245d;
11'd1107: sine = 32'hc1c984a9;
11'd1108: sine = 32'hc1cbe47a;
11'd1109: sine = 32'hc1ce43cc;
11'd1110: sine = 32'hc1d0a2a0;
11'd1111: sine = 32'hc1d300f2;
11'd1112: sine = 32'hc1d55ec3;
11'd1113: sine = 32'hc1d7bc10;
11'd1114: sine = 32'hc1da18d8;
11'd1115: sine = 32'hc1dc7519;
11'd1116: sine = 32'hc1ded0d2;
11'd1117: sine = 32'hc1e12c02;
11'd1118: sine = 32'hc1e386a7;
11'd1119: sine = 32'hc1e5e0c0;
11'd1120: sine = 32'hc1e83a4a;
11'd1121: sine = 32'hc1ea9346;
11'd1122: sine = 32'hc1ecebb1;
11'd1123: sine = 32'hc1ef4389;
11'd1124: sine = 32'hc1f19acf;
11'd1125: sine = 32'hc1f3f17f;
11'd1126: sine = 32'hc1f64798;
11'd1127: sine = 32'hc1f89d1a;
11'd1128: sine = 32'hc1faf202;
11'd1129: sine = 32'hc1fd4650;
11'd1130: sine = 32'hc1ff9a01;
11'd1131: sine = 32'hc200f68a;
11'd1132: sine = 32'hc2021fc5;
11'd1133: sine = 32'hc20348af;
11'd1134: sine = 32'hc2047148;
11'd1135: sine = 32'hc205998f;
11'd1136: sine = 32'hc206c184;
11'd1137: sine = 32'hc207e926;
11'd1138: sine = 32'hc2091074;
11'd1139: sine = 32'hc20a376d;
11'd1140: sine = 32'hc20b5e11;
11'd1141: sine = 32'hc20c845f;
11'd1142: sine = 32'hc20daa57;
11'd1143: sine = 32'hc20ecff7;
11'd1144: sine = 32'hc20ff53f;
11'd1145: sine = 32'hc2111a2e;
11'd1146: sine = 32'hc2123ec4;
11'd1147: sine = 32'hc21362ff;
11'd1148: sine = 32'hc21486e0;
11'd1149: sine = 32'hc215aa65;
11'd1150: sine = 32'hc216cd8e;
11'd1151: sine = 32'hc217f059;
11'd1152: sine = 32'hc21912c7;
11'd1153: sine = 32'hc21a34d7;
11'd1154: sine = 32'hc21b5687;
11'd1155: sine = 32'hc21c77d7;
11'd1156: sine = 32'hc21d98c7;
11'd1157: sine = 32'hc21eb956;
11'd1158: sine = 32'hc21fd983;
11'd1159: sine = 32'hc220f94d;
11'd1160: sine = 32'hc22218b4;
11'd1161: sine = 32'hc22337b7;
11'd1162: sine = 32'hc2245656;
11'd1163: sine = 32'hc225748f;
11'd1164: sine = 32'hc2269262;
11'd1165: sine = 32'hc227afce;
11'd1166: sine = 32'hc228ccd2;
11'd1167: sine = 32'hc229e96f;
11'd1168: sine = 32'hc22b05a3;
11'd1169: sine = 32'hc22c216d;
11'd1170: sine = 32'hc22d3ccd;
11'd1171: sine = 32'hc22e57c2;
11'd1172: sine = 32'hc22f724c;
11'd1173: sine = 32'hc2308c6a;
11'd1174: sine = 32'hc231a61a;
11'd1175: sine = 32'hc232bf5d;
11'd1176: sine = 32'hc233d832;
11'd1177: sine = 32'hc234f098;
11'd1178: sine = 32'hc236088e;
11'd1179: sine = 32'hc2372014;
11'd1180: sine = 32'hc2383729;
11'd1181: sine = 32'hc2394dcc;
11'd1182: sine = 32'hc23a63fd;
11'd1183: sine = 32'hc23b79bb;
11'd1184: sine = 32'hc23c8f05;
11'd1185: sine = 32'hc23da3db;
11'd1186: sine = 32'hc23eb83c;
11'd1187: sine = 32'hc23fcc28;
11'd1188: sine = 32'hc240df9d;
11'd1189: sine = 32'hc241f29b;
11'd1190: sine = 32'hc2430521;
11'd1191: sine = 32'hc2441730;
11'd1192: sine = 32'hc24528c5;
11'd1193: sine = 32'hc24639e1;
11'd1194: sine = 32'hc2474a82;
11'd1195: sine = 32'hc2485aa8;
11'd1196: sine = 32'hc2496a53;
11'd1197: sine = 32'hc24a7982;
11'd1198: sine = 32'hc24b8833;
11'd1199: sine = 32'hc24c9668;
11'd1200: sine = 32'hc24da41e;
11'd1201: sine = 32'hc24eb155;
11'd1202: sine = 32'hc24fbe0c;
11'd1203: sine = 32'hc250ca44;
11'd1204: sine = 32'hc251d5fa;
11'd1205: sine = 32'hc252e130;
11'd1206: sine = 32'hc253ebe3;
11'd1207: sine = 32'hc254f613;
11'd1208: sine = 32'hc255ffc0;
11'd1209: sine = 32'hc25708e9;
11'd1210: sine = 32'hc258118e;
11'd1211: sine = 32'hc25919ad;
11'd1212: sine = 32'hc25a2146;
11'd1213: sine = 32'hc25b2859;
11'd1214: sine = 32'hc25c2ee4;
11'd1215: sine = 32'hc25d34e8;
11'd1216: sine = 32'hc25e3a63;
11'd1217: sine = 32'hc25f3f55;
11'd1218: sine = 32'hc26043bd;
11'd1219: sine = 32'hc261479c;
11'd1220: sine = 32'hc2624aef;
11'd1221: sine = 32'hc2634db6;
11'd1222: sine = 32'hc2644ff1;
11'd1223: sine = 32'hc26551a0;
11'd1224: sine = 32'hc26652c1;
11'd1225: sine = 32'hc2675354;
11'd1226: sine = 32'hc2685358;
11'd1227: sine = 32'hc26952cd;
11'd1228: sine = 32'hc26a51b2;
11'd1229: sine = 32'hc26b5006;
11'd1230: sine = 32'hc26c4dca;
11'd1231: sine = 32'hc26d4afb;
11'd1232: sine = 32'hc26e479a;
11'd1233: sine = 32'hc26f43a7;
11'd1234: sine = 32'hc2703f1f;
11'd1235: sine = 32'hc2713a04;
11'd1236: sine = 32'hc2723453;
11'd1237: sine = 32'hc2732e0d;
11'd1238: sine = 32'hc2742732;
11'd1239: sine = 32'hc2751fbf;
11'd1240: sine = 32'hc27617b6;
11'd1241: sine = 32'hc2770f14;
11'd1242: sine = 32'hc27805da;
11'd1243: sine = 32'hc278fc08;
11'd1244: sine = 32'hc279f19b;
11'd1245: sine = 32'hc27ae695;
11'd1246: sine = 32'hc27bdaf3;
11'd1247: sine = 32'hc27cceb7;
11'd1248: sine = 32'hc27dc1de;
11'd1249: sine = 32'hc27eb469;
11'd1250: sine = 32'hc27fa657;
11'd1251: sine = 32'hc2804bd3;
11'd1252: sine = 32'hc280c42c;
11'd1253: sine = 32'hc2813c36;
11'd1254: sine = 32'hc281b3ef;
11'd1255: sine = 32'hc2822b59;
11'd1256: sine = 32'hc282a272;
11'd1257: sine = 32'hc283193b;
11'd1258: sine = 32'hc2838fb3;
11'd1259: sine = 32'hc28405da;
11'd1260: sine = 32'hc2847baf;
11'd1261: sine = 32'hc284f133;
11'd1262: sine = 32'hc2856665;
11'd1263: sine = 32'hc285db44;
11'd1264: sine = 32'hc2864fd1;
11'd1265: sine = 32'hc286c40b;
11'd1266: sine = 32'hc28737f2;
11'd1267: sine = 32'hc287ab85;
11'd1268: sine = 32'hc2881ec5;
11'd1269: sine = 32'hc28891b1;
11'd1270: sine = 32'hc2890448;
11'd1271: sine = 32'hc289768b;
11'd1272: sine = 32'hc289e879;
11'd1273: sine = 32'hc28a5a12;
11'd1274: sine = 32'hc28acb56;
11'd1275: sine = 32'hc28b3c44;
11'd1276: sine = 32'hc28bacdd;
11'd1277: sine = 32'hc28c1d1f;
11'd1278: sine = 32'hc28c8d0a;
11'd1279: sine = 32'hc28cfc9f;
11'd1280: sine = 32'hc28d6bdd;
11'd1281: sine = 32'hc28ddac4;
11'd1282: sine = 32'hc28e4953;
11'd1283: sine = 32'hc28eb78b;
11'd1284: sine = 32'hc28f256a;
11'd1285: sine = 32'hc28f92f2;
11'd1286: sine = 32'hc2900020;
11'd1287: sine = 32'hc2906cf6;
11'd1288: sine = 32'hc290d973;
11'd1289: sine = 32'hc2914596;
11'd1290: sine = 32'hc291b160;
11'd1291: sine = 32'hc2921cd0;
11'd1292: sine = 32'hc29287e5;
11'd1293: sine = 32'hc292f2a1;
11'd1294: sine = 32'hc2935d02;
11'd1295: sine = 32'hc293c707;
11'd1296: sine = 32'hc29430b2;
11'd1297: sine = 32'hc2949a01;
11'd1298: sine = 32'hc29502f5;
11'd1299: sine = 32'hc2956b8c;
11'd1300: sine = 32'hc295d3c8;
11'd1301: sine = 32'hc2963ba7;
11'd1302: sine = 32'hc296a329;
11'd1303: sine = 32'hc2970a4f;
11'd1304: sine = 32'hc2977117;
11'd1305: sine = 32'hc297d782;
11'd1306: sine = 32'hc2983d8f;
11'd1307: sine = 32'hc298a33f;
11'd1308: sine = 32'hc2990890;
11'd1309: sine = 32'hc2996d83;
11'd1310: sine = 32'hc299d217;
11'd1311: sine = 32'hc29a364c;
11'd1312: sine = 32'hc29a9a22;
11'd1313: sine = 32'hc29afd99;
11'd1314: sine = 32'hc29b60b0;
11'd1315: sine = 32'hc29bc367;
11'd1316: sine = 32'hc29c25be;
11'd1317: sine = 32'hc29c87b5;
11'd1318: sine = 32'hc29ce94c;
11'd1319: sine = 32'hc29d4a81;
11'd1320: sine = 32'hc29dab56;
11'd1321: sine = 32'hc29e0bc9;
11'd1322: sine = 32'hc29e6bdb;
11'd1323: sine = 32'hc29ecb8b;
11'd1324: sine = 32'hc29f2ad9;
11'd1325: sine = 32'hc29f89c5;
11'd1326: sine = 32'hc29fe84e;
11'd1327: sine = 32'hc2a04675;
11'd1328: sine = 32'hc2a0a439;
11'd1329: sine = 32'hc2a1019a;
11'd1330: sine = 32'hc2a15e98;
11'd1331: sine = 32'hc2a1bb32;
11'd1332: sine = 32'hc2a21768;
11'd1333: sine = 32'hc2a2733a;
11'd1334: sine = 32'hc2a2cea8;
11'd1335: sine = 32'hc2a329b2;
11'd1336: sine = 32'hc2a38457;
11'd1337: sine = 32'hc2a3de97;
11'd1338: sine = 32'hc2a43872;
11'd1339: sine = 32'hc2a491e8;
11'd1340: sine = 32'hc2a4eaf8;
11'd1341: sine = 32'hc2a543a3;
11'd1342: sine = 32'hc2a59be8;
11'd1343: sine = 32'hc2a5f3c6;
11'd1344: sine = 32'hc2a64b3e;
11'd1345: sine = 32'hc2a6a24f;
11'd1346: sine = 32'hc2a6f8fa;
11'd1347: sine = 32'hc2a74f3e;
11'd1348: sine = 32'hc2a7a51a;
11'd1349: sine = 32'hc2a7fa8f;
11'd1350: sine = 32'hc2a84f9d;
11'd1351: sine = 32'hc2a8a443;
11'd1352: sine = 32'hc2a8f880;
11'd1353: sine = 32'hc2a94c56;
11'd1354: sine = 32'hc2a99fc2;
11'd1355: sine = 32'hc2a9f2c7;
11'd1356: sine = 32'hc2aa4562;
11'd1357: sine = 32'hc2aa9795;
11'd1358: sine = 32'hc2aae95e;
11'd1359: sine = 32'hc2ab3abe;
11'd1360: sine = 32'hc2ab8bb4;
11'd1361: sine = 32'hc2abdc40;
11'd1362: sine = 32'hc2ac2c63;
11'd1363: sine = 32'hc2ac7c1b;
11'd1364: sine = 32'hc2accb69;
11'd1365: sine = 32'hc2ad1a4c;
11'd1366: sine = 32'hc2ad68c4;
11'd1367: sine = 32'hc2adb6d1;
11'd1368: sine = 32'hc2ae0474;
11'd1369: sine = 32'hc2ae51ab;
11'd1370: sine = 32'hc2ae9e76;
11'd1371: sine = 32'hc2aeead6;
11'd1372: sine = 32'hc2af36c9;
11'd1373: sine = 32'hc2af8251;
11'd1374: sine = 32'hc2afcd6d;
11'd1375: sine = 32'hc2b0181c;
11'd1376: sine = 32'hc2b0625e;
11'd1377: sine = 32'hc2b0ac34;
11'd1378: sine = 32'hc2b0f59c;
11'd1379: sine = 32'hc2b13e98;
11'd1380: sine = 32'hc2b18726;
11'd1381: sine = 32'hc2b1cf46;
11'd1382: sine = 32'hc2b216f9;
11'd1383: sine = 32'hc2b25e3e;
11'd1384: sine = 32'hc2b2a515;
11'd1385: sine = 32'hc2b2eb7e;
11'd1386: sine = 32'hc2b33178;
11'd1387: sine = 32'hc2b37704;
11'd1388: sine = 32'hc2b3bc22;
11'd1389: sine = 32'hc2b400d0;
11'd1390: sine = 32'hc2b4450f;
11'd1391: sine = 32'hc2b488df;
11'd1392: sine = 32'hc2b4cc40;
11'd1393: sine = 32'hc2b50f31;
11'd1394: sine = 32'hc2b551b3;
11'd1395: sine = 32'hc2b593c5;
11'd1396: sine = 32'hc2b5d566;
11'd1397: sine = 32'hc2b61698;
11'd1398: sine = 32'hc2b65759;
11'd1399: sine = 32'hc2b697aa;
11'd1400: sine = 32'hc2b6d78a;
11'd1401: sine = 32'hc2b716f9;
11'd1402: sine = 32'hc2b755f7;
11'd1403: sine = 32'hc2b79485;
11'd1404: sine = 32'hc2b7d2a1;
11'd1405: sine = 32'hc2b8104b;
11'd1406: sine = 32'hc2b84d84;
11'd1407: sine = 32'hc2b88a4c;
11'd1408: sine = 32'hc2b8c6a1;
11'd1409: sine = 32'hc2b90285;
11'd1410: sine = 32'hc2b93df7;
11'd1411: sine = 32'hc2b978f6;
11'd1412: sine = 32'hc2b9b383;
11'd1413: sine = 32'hc2b9ed9d;
11'd1414: sine = 32'hc2ba2744;
11'd1415: sine = 32'hc2ba6079;
11'd1416: sine = 32'hc2ba993b;
11'd1417: sine = 32'hc2bad18a;
11'd1418: sine = 32'hc2bb0965;
11'd1419: sine = 32'hc2bb40cd;
11'd1420: sine = 32'hc2bb77c2;
11'd1421: sine = 32'hc2bbae42;
11'd1422: sine = 32'hc2bbe450;
11'd1423: sine = 32'hc2bc19e9;
11'd1424: sine = 32'hc2bc4f0e;
11'd1425: sine = 32'hc2bc83bf;
11'd1426: sine = 32'hc2bcb7fc;
11'd1427: sine = 32'hc2bcebc4;
11'd1428: sine = 32'hc2bd1f18;
11'd1429: sine = 32'hc2bd51f7;
11'd1430: sine = 32'hc2bd8462;
11'd1431: sine = 32'hc2bdb657;
11'd1432: sine = 32'hc2bde7d7;
11'd1433: sine = 32'hc2be18e3;
11'd1434: sine = 32'hc2be4979;
11'd1435: sine = 32'hc2be7999;
11'd1436: sine = 32'hc2bea945;
11'd1437: sine = 32'hc2bed87a;
11'd1438: sine = 32'hc2bf073a;
11'd1439: sine = 32'hc2bf3584;
11'd1440: sine = 32'hc2bf6358;
11'd1441: sine = 32'hc2bf90b6;
11'd1442: sine = 32'hc2bfbd9e;
11'd1443: sine = 32'hc2bfea0f;
11'd1444: sine = 32'hc2c0160b;
11'd1445: sine = 32'hc2c0418f;
11'd1446: sine = 32'hc2c06c9d;
11'd1447: sine = 32'hc2c09735;
11'd1448: sine = 32'hc2c0c155;
11'd1449: sine = 32'hc2c0eaff;
11'd1450: sine = 32'hc2c11432;
11'd1451: sine = 32'hc2c13ced;
11'd1452: sine = 32'hc2c16532;
11'd1453: sine = 32'hc2c18cff;
11'd1454: sine = 32'hc2c1b455;
11'd1455: sine = 32'hc2c1db33;
11'd1456: sine = 32'hc2c20199;
11'd1457: sine = 32'hc2c22788;
11'd1458: sine = 32'hc2c24d00;
11'd1459: sine = 32'hc2c271ff;
11'd1460: sine = 32'hc2c29686;
11'd1461: sine = 32'hc2c2ba96;
11'd1462: sine = 32'hc2c2de2d;
11'd1463: sine = 32'hc2c3014c;
11'd1464: sine = 32'hc2c323f3;
11'd1465: sine = 32'hc2c34621;
11'd1466: sine = 32'hc2c367d7;
11'd1467: sine = 32'hc2c38914;
11'd1468: sine = 32'hc2c3a9d9;
11'd1469: sine = 32'hc2c3ca25;
11'd1470: sine = 32'hc2c3e9f9;
11'd1471: sine = 32'hc2c40953;
11'd1472: sine = 32'hc2c42835;
11'd1473: sine = 32'hc2c4469d;
11'd1474: sine = 32'hc2c4648d;
11'd1475: sine = 32'hc2c48203;
11'd1476: sine = 32'hc2c49f00;
11'd1477: sine = 32'hc2c4bb84;
11'd1478: sine = 32'hc2c4d78e;
11'd1479: sine = 32'hc2c4f31f;
11'd1480: sine = 32'hc2c50e37;
11'd1481: sine = 32'hc2c528d5;
11'd1482: sine = 32'hc2c542f9;
11'd1483: sine = 32'hc2c55ca4;
11'd1484: sine = 32'hc2c575d5;
11'd1485: sine = 32'hc2c58e8c;
11'd1486: sine = 32'hc2c5a6c9;
11'd1487: sine = 32'hc2c5be8d;
11'd1488: sine = 32'hc2c5d5d6;
11'd1489: sine = 32'hc2c5eca6;
11'd1490: sine = 32'hc2c602fb;
11'd1491: sine = 32'hc2c618d6;
11'd1492: sine = 32'hc2c62e37;
11'd1493: sine = 32'hc2c6431e;
11'd1494: sine = 32'hc2c6578a;
11'd1495: sine = 32'hc2c66b7c;
11'd1496: sine = 32'hc2c67ef4;
11'd1497: sine = 32'hc2c691f1;
11'd1498: sine = 32'hc2c6a474;
11'd1499: sine = 32'hc2c6b67c;
11'd1500: sine = 32'hc2c6c809;
11'd1501: sine = 32'hc2c6d91c;
11'd1502: sine = 32'hc2c6e9b5;
11'd1503: sine = 32'hc2c6f9d2;
11'd1504: sine = 32'hc2c70975;
11'd1505: sine = 32'hc2c7189d;
11'd1506: sine = 32'hc2c7274b;
11'd1507: sine = 32'hc2c7357d;
11'd1508: sine = 32'hc2c74335;
11'd1509: sine = 32'hc2c75071;
11'd1510: sine = 32'hc2c75d33;
11'd1511: sine = 32'hc2c7697a;
11'd1512: sine = 32'hc2c77545;
11'd1513: sine = 32'hc2c78096;
11'd1514: sine = 32'hc2c78b6c;
11'd1515: sine = 32'hc2c795c6;
11'd1516: sine = 32'hc2c79fa6;
11'd1517: sine = 32'hc2c7a90a;
11'd1518: sine = 32'hc2c7b1f3;
11'd1519: sine = 32'hc2c7ba61;
11'd1520: sine = 32'hc2c7c254;
11'd1521: sine = 32'hc2c7c9cb;
11'd1522: sine = 32'hc2c7d0c8;
11'd1523: sine = 32'hc2c7d749;
11'd1524: sine = 32'hc2c7dd4e;
11'd1525: sine = 32'hc2c7e2d9;
11'd1526: sine = 32'hc2c7e7e8;
11'd1527: sine = 32'hc2c7ec7c;
11'd1528: sine = 32'hc2c7f094;
11'd1529: sine = 32'hc2c7f432;
11'd1530: sine = 32'hc2c7f753;
11'd1531: sine = 32'hc2c7f9fa;
11'd1532: sine = 32'hc2c7fc25;
11'd1533: sine = 32'hc2c7fdd5;
11'd1534: sine = 32'hc2c7ff09;
11'd1535: sine = 32'hc2c7ffc2;
11'd1536: sine = 32'hc2c80000;
11'd1537: sine = 32'hc2c7ffc2;
11'd1538: sine = 32'hc2c7ff09;
11'd1539: sine = 32'hc2c7fdd5;
11'd1540: sine = 32'hc2c7fc25;
11'd1541: sine = 32'hc2c7f9fa;
11'd1542: sine = 32'hc2c7f753;
11'd1543: sine = 32'hc2c7f432;
11'd1544: sine = 32'hc2c7f094;
11'd1545: sine = 32'hc2c7ec7c;
11'd1546: sine = 32'hc2c7e7e8;
11'd1547: sine = 32'hc2c7e2d9;
11'd1548: sine = 32'hc2c7dd4e;
11'd1549: sine = 32'hc2c7d749;
11'd1550: sine = 32'hc2c7d0c8;
11'd1551: sine = 32'hc2c7c9cb;
11'd1552: sine = 32'hc2c7c254;
11'd1553: sine = 32'hc2c7ba61;
11'd1554: sine = 32'hc2c7b1f3;
11'd1555: sine = 32'hc2c7a90a;
11'd1556: sine = 32'hc2c79fa6;
11'd1557: sine = 32'hc2c795c6;
11'd1558: sine = 32'hc2c78b6c;
11'd1559: sine = 32'hc2c78096;
11'd1560: sine = 32'hc2c77546;
11'd1561: sine = 32'hc2c7697a;
11'd1562: sine = 32'hc2c75d33;
11'd1563: sine = 32'hc2c75071;
11'd1564: sine = 32'hc2c74335;
11'd1565: sine = 32'hc2c7357d;
11'd1566: sine = 32'hc2c7274b;
11'd1567: sine = 32'hc2c7189d;
11'd1568: sine = 32'hc2c70975;
11'd1569: sine = 32'hc2c6f9d2;
11'd1570: sine = 32'hc2c6e9b5;
11'd1571: sine = 32'hc2c6d91d;
11'd1572: sine = 32'hc2c6c80a;
11'd1573: sine = 32'hc2c6b67c;
11'd1574: sine = 32'hc2c6a474;
11'd1575: sine = 32'hc2c691f1;
11'd1576: sine = 32'hc2c67ef4;
11'd1577: sine = 32'hc2c66b7c;
11'd1578: sine = 32'hc2c6578a;
11'd1579: sine = 32'hc2c6431e;
11'd1580: sine = 32'hc2c62e37;
11'd1581: sine = 32'hc2c618d6;
11'd1582: sine = 32'hc2c602fb;
11'd1583: sine = 32'hc2c5eca6;
11'd1584: sine = 32'hc2c5d5d7;
11'd1585: sine = 32'hc2c5be8d;
11'd1586: sine = 32'hc2c5a6ca;
11'd1587: sine = 32'hc2c58e8c;
11'd1588: sine = 32'hc2c575d5;
11'd1589: sine = 32'hc2c55ca4;
11'd1590: sine = 32'hc2c542fa;
11'd1591: sine = 32'hc2c528d5;
11'd1592: sine = 32'hc2c50e37;
11'd1593: sine = 32'hc2c4f320;
11'd1594: sine = 32'hc2c4d78f;
11'd1595: sine = 32'hc2c4bb84;
11'd1596: sine = 32'hc2c49f00;
11'd1597: sine = 32'hc2c48203;
11'd1598: sine = 32'hc2c4648d;
11'd1599: sine = 32'hc2c4469e;
11'd1600: sine = 32'hc2c42835;
11'd1601: sine = 32'hc2c40954;
11'd1602: sine = 32'hc2c3e9f9;
11'd1603: sine = 32'hc2c3ca26;
11'd1604: sine = 32'hc2c3a9da;
11'd1605: sine = 32'hc2c38915;
11'd1606: sine = 32'hc2c367d8;
11'd1607: sine = 32'hc2c34622;
11'd1608: sine = 32'hc2c323f3;
11'd1609: sine = 32'hc2c3014c;
11'd1610: sine = 32'hc2c2de2d;
11'd1611: sine = 32'hc2c2ba96;
11'd1612: sine = 32'hc2c29687;
11'd1613: sine = 32'hc2c271ff;
11'd1614: sine = 32'hc2c24d00;
11'd1615: sine = 32'hc2c22789;
11'd1616: sine = 32'hc2c2019a;
11'd1617: sine = 32'hc2c1db33;
11'd1618: sine = 32'hc2c1b455;
11'd1619: sine = 32'hc2c18cff;
11'd1620: sine = 32'hc2c16532;
11'd1621: sine = 32'hc2c13cee;
11'd1622: sine = 32'hc2c11432;
11'd1623: sine = 32'hc2c0eb00;
11'd1624: sine = 32'hc2c0c156;
11'd1625: sine = 32'hc2c09735;
11'd1626: sine = 32'hc2c06c9e;
11'd1627: sine = 32'hc2c04190;
11'd1628: sine = 32'hc2c0160b;
11'd1629: sine = 32'hc2bfea10;
11'd1630: sine = 32'hc2bfbd9f;
11'd1631: sine = 32'hc2bf90b7;
11'd1632: sine = 32'hc2bf6359;
11'd1633: sine = 32'hc2bf3585;
11'd1634: sine = 32'hc2bf073b;
11'd1635: sine = 32'hc2bed87b;
11'd1636: sine = 32'hc2bea945;
11'd1637: sine = 32'hc2be799a;
11'd1638: sine = 32'hc2be4979;
11'd1639: sine = 32'hc2be18e3;
11'd1640: sine = 32'hc2bde7d8;
11'd1641: sine = 32'hc2bdb658;
11'd1642: sine = 32'hc2bd8462;
11'd1643: sine = 32'hc2bd51f8;
11'd1644: sine = 32'hc2bd1f19;
11'd1645: sine = 32'hc2bcebc5;
11'd1646: sine = 32'hc2bcb7fd;
11'd1647: sine = 32'hc2bc83c0;
11'd1648: sine = 32'hc2bc4f0f;
11'd1649: sine = 32'hc2bc19ea;
11'd1650: sine = 32'hc2bbe450;
11'd1651: sine = 32'hc2bbae43;
11'd1652: sine = 32'hc2bb77c2;
11'd1653: sine = 32'hc2bb40ce;
11'd1654: sine = 32'hc2bb0966;
11'd1655: sine = 32'hc2bad18a;
11'd1656: sine = 32'hc2ba993c;
11'd1657: sine = 32'hc2ba607a;
11'd1658: sine = 32'hc2ba2745;
11'd1659: sine = 32'hc2b9ed9e;
11'd1660: sine = 32'hc2b9b383;
11'd1661: sine = 32'hc2b978f7;
11'd1662: sine = 32'hc2b93df7;
11'd1663: sine = 32'hc2b90286;
11'd1664: sine = 32'hc2b8c6a2;
11'd1665: sine = 32'hc2b88a4d;
11'd1666: sine = 32'hc2b84d85;
11'd1667: sine = 32'hc2b8104c;
11'd1668: sine = 32'hc2b7d2a2;
11'd1669: sine = 32'hc2b79486;
11'd1670: sine = 32'hc2b755f8;
11'd1671: sine = 32'hc2b716fa;
11'd1672: sine = 32'hc2b6d78b;
11'd1673: sine = 32'hc2b697aa;
11'd1674: sine = 32'hc2b6575a;
11'd1675: sine = 32'hc2b61699;
11'd1676: sine = 32'hc2b5d567;
11'd1677: sine = 32'hc2b593c5;
11'd1678: sine = 32'hc2b551b4;
11'd1679: sine = 32'hc2b50f32;
11'd1680: sine = 32'hc2b4cc41;
11'd1681: sine = 32'hc2b488e0;
11'd1682: sine = 32'hc2b44510;
11'd1683: sine = 32'hc2b400d1;
11'd1684: sine = 32'hc2b3bc22;
11'd1685: sine = 32'hc2b37705;
11'd1686: sine = 32'hc2b33179;
11'd1687: sine = 32'hc2b2eb7f;
11'd1688: sine = 32'hc2b2a516;
11'd1689: sine = 32'hc2b25e3f;
11'd1690: sine = 32'hc2b216fa;
11'd1691: sine = 32'hc2b1cf47;
11'd1692: sine = 32'hc2b18727;
11'd1693: sine = 32'hc2b13e98;
11'd1694: sine = 32'hc2b0f59d;
11'd1695: sine = 32'hc2b0ac34;
11'd1696: sine = 32'hc2b0625f;
11'd1697: sine = 32'hc2b0181d;
11'd1698: sine = 32'hc2afcd6e;
11'd1699: sine = 32'hc2af8252;
11'd1700: sine = 32'hc2af36cb;
11'd1701: sine = 32'hc2aeead7;
11'd1702: sine = 32'hc2ae9e77;
11'd1703: sine = 32'hc2ae51ac;
11'd1704: sine = 32'hc2ae0475;
11'd1705: sine = 32'hc2adb6d3;
11'd1706: sine = 32'hc2ad68c5;
11'd1707: sine = 32'hc2ad1a4d;
11'd1708: sine = 32'hc2accb6a;
11'd1709: sine = 32'hc2ac7c1c;
11'd1710: sine = 32'hc2ac2c64;
11'd1711: sine = 32'hc2abdc41;
11'd1712: sine = 32'hc2ab8bb5;
11'd1713: sine = 32'hc2ab3abf;
11'd1714: sine = 32'hc2aae95f;
11'd1715: sine = 32'hc2aa9796;
11'd1716: sine = 32'hc2aa4563;
11'd1717: sine = 32'hc2a9f2c8;
11'd1718: sine = 32'hc2a99fc4;
11'd1719: sine = 32'hc2a94c57;
11'd1720: sine = 32'hc2a8f881;
11'd1721: sine = 32'hc2a8a444;
11'd1722: sine = 32'hc2a84f9e;
11'd1723: sine = 32'hc2a7fa91;
11'd1724: sine = 32'hc2a7a51c;
11'd1725: sine = 32'hc2a74f3f;
11'd1726: sine = 32'hc2a6f8fb;
11'd1727: sine = 32'hc2a6a251;
11'd1728: sine = 32'hc2a64b3f;
11'd1729: sine = 32'hc2a5f3c7;
11'd1730: sine = 32'hc2a59be9;
11'd1731: sine = 32'hc2a543a4;
11'd1732: sine = 32'hc2a4eafa;
11'd1733: sine = 32'hc2a491e9;
11'd1734: sine = 32'hc2a43874;
11'd1735: sine = 32'hc2a3de98;
11'd1736: sine = 32'hc2a38458;
11'd1737: sine = 32'hc2a329b3;
11'd1738: sine = 32'hc2a2ceaa;
11'd1739: sine = 32'hc2a2733c;
11'd1740: sine = 32'hc2a21769;
11'd1741: sine = 32'hc2a1bb33;
11'd1742: sine = 32'hc2a15e99;
11'd1743: sine = 32'hc2a1019b;
11'd1744: sine = 32'hc2a0a43a;
11'd1745: sine = 32'hc2a04676;
11'd1746: sine = 32'hc29fe850;
11'd1747: sine = 32'hc29f89c6;
11'd1748: sine = 32'hc29f2ada;
11'd1749: sine = 32'hc29ecb8c;
11'd1750: sine = 32'hc29e6bdc;
11'd1751: sine = 32'hc29e0bca;
11'd1752: sine = 32'hc29dab57;
11'd1753: sine = 32'hc29d4a83;
11'd1754: sine = 32'hc29ce94d;
11'd1755: sine = 32'hc29c87b7;
11'd1756: sine = 32'hc29c25c0;
11'd1757: sine = 32'hc29bc369;
11'd1758: sine = 32'hc29b60b1;
11'd1759: sine = 32'hc29afd9a;
11'd1760: sine = 32'hc29a9a23;
11'd1761: sine = 32'hc29a364d;
11'd1762: sine = 32'hc299d218;
11'd1763: sine = 32'hc2996d84;
11'd1764: sine = 32'hc2990891;
11'd1765: sine = 32'hc298a340;
11'd1766: sine = 32'hc2983d91;
11'd1767: sine = 32'hc297d783;
11'd1768: sine = 32'hc2977119;
11'd1769: sine = 32'hc2970a50;
11'd1770: sine = 32'hc296a32b;
11'd1771: sine = 32'hc2963ba8;
11'd1772: sine = 32'hc295d3c9;
11'd1773: sine = 32'hc2956b8e;
11'd1774: sine = 32'hc29502f6;
11'd1775: sine = 32'hc2949a03;
11'd1776: sine = 32'hc29430b3;
11'd1777: sine = 32'hc293c709;
11'd1778: sine = 32'hc2935d03;
11'd1779: sine = 32'hc292f2a2;
11'd1780: sine = 32'hc29287e7;
11'd1781: sine = 32'hc2921cd1;
11'd1782: sine = 32'hc291b161;
11'd1783: sine = 32'hc2914598;
11'd1784: sine = 32'hc290d974;
11'd1785: sine = 32'hc2906cf8;
11'd1786: sine = 32'hc2900022;
11'd1787: sine = 32'hc28f92f3;
11'd1788: sine = 32'hc28f256c;
11'd1789: sine = 32'hc28eb78c;
11'd1790: sine = 32'hc28e4955;
11'd1791: sine = 32'hc28ddac6;
11'd1792: sine = 32'hc28d6bdf;
11'd1793: sine = 32'hc28cfca1;
11'd1794: sine = 32'hc28c8d0c;
11'd1795: sine = 32'hc28c1d20;
11'd1796: sine = 32'hc28bacde;
11'd1797: sine = 32'hc28b3c46;
11'd1798: sine = 32'hc28acb58;
11'd1799: sine = 32'hc28a5a14;
11'd1800: sine = 32'hc289e87b;
11'd1801: sine = 32'hc289768d;
11'd1802: sine = 32'hc289044a;
11'd1803: sine = 32'hc28891b2;
11'd1804: sine = 32'hc2881ec6;
11'd1805: sine = 32'hc287ab87;
11'd1806: sine = 32'hc28737f3;
11'd1807: sine = 32'hc286c40c;
11'd1808: sine = 32'hc2864fd2;
11'd1809: sine = 32'hc285db46;
11'd1810: sine = 32'hc2856666;
11'd1811: sine = 32'hc284f135;
11'd1812: sine = 32'hc2847bb1;
11'd1813: sine = 32'hc28405dc;
11'd1814: sine = 32'hc2838fb5;
11'd1815: sine = 32'hc283193d;
11'd1816: sine = 32'hc282a274;
11'd1817: sine = 32'hc2822b5b;
11'd1818: sine = 32'hc281b3f1;
11'd1819: sine = 32'hc2813c37;
11'd1820: sine = 32'hc280c42e;
11'd1821: sine = 32'hc2804bd5;
11'd1822: sine = 32'hc27fa65a;
11'd1823: sine = 32'hc27eb46c;
11'd1824: sine = 32'hc27dc1e1;
11'd1825: sine = 32'hc27cceba;
11'd1826: sine = 32'hc27bdaf7;
11'd1827: sine = 32'hc27ae698;
11'd1828: sine = 32'hc279f19f;
11'd1829: sine = 32'hc278fc0b;
11'd1830: sine = 32'hc27805de;
11'd1831: sine = 32'hc2770f18;
11'd1832: sine = 32'hc27617b9;
11'd1833: sine = 32'hc2751fc3;
11'd1834: sine = 32'hc2742735;
11'd1835: sine = 32'hc2732e11;
11'd1836: sine = 32'hc2723457;
11'd1837: sine = 32'hc2713a07;
11'd1838: sine = 32'hc2703f23;
11'd1839: sine = 32'hc26f43aa;
11'd1840: sine = 32'hc26e479e;
11'd1841: sine = 32'hc26d4aff;
11'd1842: sine = 32'hc26c4dcd;
11'd1843: sine = 32'hc26b500a;
11'd1844: sine = 32'hc26a51b5;
11'd1845: sine = 32'hc26952d0;
11'd1846: sine = 32'hc268535b;
11'd1847: sine = 32'hc2675357;
11'd1848: sine = 32'hc26652c4;
11'd1849: sine = 32'hc26551a3;
11'd1850: sine = 32'hc2644ff5;
11'd1851: sine = 32'hc2634dba;
11'd1852: sine = 32'hc2624af2;
11'd1853: sine = 32'hc261479f;
11'd1854: sine = 32'hc26043c1;
11'd1855: sine = 32'hc25f3f59;
11'd1856: sine = 32'hc25e3a66;
11'd1857: sine = 32'hc25d34eb;
11'd1858: sine = 32'hc25c2ee8;
11'd1859: sine = 32'hc25b285c;
11'd1860: sine = 32'hc25a214a;
11'd1861: sine = 32'hc25919b0;
11'd1862: sine = 32'hc2581191;
11'd1863: sine = 32'hc25708ed;
11'd1864: sine = 32'hc255ffc4;
11'd1865: sine = 32'hc254f617;
11'd1866: sine = 32'hc253ebe6;
11'd1867: sine = 32'hc252e133;
11'd1868: sine = 32'hc251d5fe;
11'd1869: sine = 32'hc250ca47;
11'd1870: sine = 32'hc24fbe10;
11'd1871: sine = 32'hc24eb158;
11'd1872: sine = 32'hc24da421;
11'd1873: sine = 32'hc24c966b;
11'd1874: sine = 32'hc24b8837;
11'd1875: sine = 32'hc24a7985;
11'd1876: sine = 32'hc2496a57;
11'd1877: sine = 32'hc2485aac;
11'd1878: sine = 32'hc2474a86;
11'd1879: sine = 32'hc24639e4;
11'd1880: sine = 32'hc24528c9;
11'd1881: sine = 32'hc2441733;
11'd1882: sine = 32'hc2430525;
11'd1883: sine = 32'hc241f29f;
11'd1884: sine = 32'hc240dfa1;
11'd1885: sine = 32'hc23fcc2b;
11'd1886: sine = 32'hc23eb840;
11'd1887: sine = 32'hc23da3df;
11'd1888: sine = 32'hc23c8f09;
11'd1889: sine = 32'hc23b79bf;
11'd1890: sine = 32'hc23a6401;
11'd1891: sine = 32'hc2394dd0;
11'd1892: sine = 32'hc238372c;
11'd1893: sine = 32'hc2372017;
11'd1894: sine = 32'hc2360892;
11'd1895: sine = 32'hc234f09b;
11'd1896: sine = 32'hc233d836;
11'd1897: sine = 32'hc232bf61;
11'd1898: sine = 32'hc231a61e;
11'd1899: sine = 32'hc2308c6d;
11'd1900: sine = 32'hc22f7250;
11'd1901: sine = 32'hc22e57c6;
11'd1902: sine = 32'hc22d3cd1;
11'd1903: sine = 32'hc22c2171;
11'd1904: sine = 32'hc22b05a7;
11'd1905: sine = 32'hc229e973;
11'd1906: sine = 32'hc228ccd6;
11'd1907: sine = 32'hc227afd2;
11'd1908: sine = 32'hc2269265;
11'd1909: sine = 32'hc2257493;
11'd1910: sine = 32'hc224565a;
11'd1911: sine = 32'hc22337bb;
11'd1912: sine = 32'hc22218b8;
11'd1913: sine = 32'hc220f951;
11'd1914: sine = 32'hc21fd987;
11'd1915: sine = 32'hc21eb95a;
11'd1916: sine = 32'hc21d98cb;
11'd1917: sine = 32'hc21c77db;
11'd1918: sine = 32'hc21b568b;
11'd1919: sine = 32'hc21a34da;
11'd1920: sine = 32'hc21912cb;
11'd1921: sine = 32'hc217f05d;
11'd1922: sine = 32'hc216cd91;
11'd1923: sine = 32'hc215aa69;
11'd1924: sine = 32'hc21486e4;
11'd1925: sine = 32'hc2136303;
11'd1926: sine = 32'hc2123ec8;
11'd1927: sine = 32'hc2111a32;
11'd1928: sine = 32'hc20ff543;
11'd1929: sine = 32'hc20ecffb;
11'd1930: sine = 32'hc20daa5b;
11'd1931: sine = 32'hc20c8463;
11'd1932: sine = 32'hc20b5e15;
11'd1933: sine = 32'hc20a3771;
11'd1934: sine = 32'hc2091078;
11'd1935: sine = 32'hc207e92a;
11'd1936: sine = 32'hc206c188;
11'd1937: sine = 32'hc2059993;
11'd1938: sine = 32'hc204714c;
11'd1939: sine = 32'hc20348b3;
11'd1940: sine = 32'hc2021fc9;
11'd1941: sine = 32'hc200f68e;
11'd1942: sine = 32'hc1ff9a09;
11'd1943: sine = 32'hc1fd4658;
11'd1944: sine = 32'hc1faf20a;
11'd1945: sine = 32'hc1f89d22;
11'd1946: sine = 32'hc1f647a0;
11'd1947: sine = 32'hc1f3f187;
11'd1948: sine = 32'hc1f19ad7;
11'd1949: sine = 32'hc1ef4392;
11'd1950: sine = 32'hc1ecebb9;
11'd1951: sine = 32'hc1ea934e;
11'd1952: sine = 32'hc1e83a52;
11'd1953: sine = 32'hc1e5e0c8;
11'd1954: sine = 32'hc1e386af;
11'd1955: sine = 32'hc1e12c0a;
11'd1956: sine = 32'hc1ded0da;
11'd1957: sine = 32'hc1dc7521;
11'd1958: sine = 32'hc1da18e0;
11'd1959: sine = 32'hc1d7bc18;
11'd1960: sine = 32'hc1d55ecb;
11'd1961: sine = 32'hc1d300fb;
11'd1962: sine = 32'hc1d0a2a8;
11'd1963: sine = 32'hc1ce43d4;
11'd1964: sine = 32'hc1cbe482;
11'd1965: sine = 32'hc1c984b2;
11'd1966: sine = 32'hc1c72465;
11'd1967: sine = 32'hc1c4c39d;
11'd1968: sine = 32'hc1c2625c;
11'd1969: sine = 32'hc1c000a4;
11'd1970: sine = 32'hc1bd9e74;
11'd1971: sine = 32'hc1bb3bd0;
11'd1972: sine = 32'hc1b8d8b9;
11'd1973: sine = 32'hc1b6752f;
11'd1974: sine = 32'hc1b41135;
11'd1975: sine = 32'hc1b1accb;
11'd1976: sine = 32'hc1af47f4;
11'd1977: sine = 32'hc1ace2b1;
11'd1978: sine = 32'hc1aa7d04;
11'd1979: sine = 32'hc1a816ed;
11'd1980: sine = 32'hc1a5b06e;
11'd1981: sine = 32'hc1a34989;
11'd1982: sine = 32'hc1a0e240;
11'd1983: sine = 32'hc19e7a93;
11'd1984: sine = 32'hc19c1285;
11'd1985: sine = 32'hc199aa16;
11'd1986: sine = 32'hc1974149;
11'd1987: sine = 32'hc194d81e;
11'd1988: sine = 32'hc1926e97;
11'd1989: sine = 32'hc19004b6;
11'd1990: sine = 32'hc18d9a7c;
11'd1991: sine = 32'hc18b2feb;
11'd1992: sine = 32'hc188c504;
11'd1993: sine = 32'hc18659c9;
11'd1994: sine = 32'hc183ee3a;
11'd1995: sine = 32'hc181825b;
11'd1996: sine = 32'hc17e2c56;
11'd1997: sine = 32'hc179535b;
11'd1998: sine = 32'hc17479c5;
11'd1999: sine = 32'hc16f9f99;
11'd2000: sine = 32'hc16ac4d8;
11'd2001: sine = 32'hc165e987;
11'd2002: sine = 32'hc1610da8;
11'd2003: sine = 32'hc15c313f;
11'd2004: sine = 32'hc157544d;
11'd2005: sine = 32'hc15276d7;
11'd2006: sine = 32'hc14d98de;
11'd2007: sine = 32'hc148ba67;
11'd2008: sine = 32'hc143db75;
11'd2009: sine = 32'hc13efc09;
11'd2010: sine = 32'hc13a1c27;
11'd2011: sine = 32'hc1353bd3;
11'd2012: sine = 32'hc1305b0f;
11'd2013: sine = 32'hc12b79de;
11'd2014: sine = 32'hc1269844;
11'd2015: sine = 32'hc121b642;
11'd2016: sine = 32'hc11cd3dd;
11'd2017: sine = 32'hc117f117;
11'd2018: sine = 32'hc1130df4;
11'd2019: sine = 32'hc10e2a75;
11'd2020: sine = 32'hc109469f;
11'd2021: sine = 32'hc1046275;
11'd2022: sine = 32'hc0fefbf1;
11'd2023: sine = 32'hc0f5325b;
11'd2024: sine = 32'hc0eb682d;
11'd2025: sine = 32'hc0e19d6f;
11'd2026: sine = 32'hc0d7d225;
11'd2027: sine = 32'hc0ce0657;
11'd2028: sine = 32'hc0c43a09;
11'd2029: sine = 32'hc0ba6d42;
11'd2030: sine = 32'hc0b0a008;
11'd2031: sine = 32'hc0a6d261;
11'd2032: sine = 32'hc09d0453;
11'd2033: sine = 32'hc09335e5;
11'd2034: sine = 32'hc089671b;
11'd2035: sine = 32'hc07f2ffb;
11'd2036: sine = 32'hc06b9121;
11'd2037: sine = 32'hc057f1b6;
11'd2038: sine = 32'hc04451c6;
11'd2039: sine = 32'hc030b15c;
11'd2040: sine = 32'hc01d1086;
11'd2041: sine = 32'hc0096f4f;
11'd2042: sine = 32'hbfeb9b86;
11'd2043: sine = 32'hbfc457dd;
11'd2044: sine = 32'hbf9d13ba;
11'd2045: sine = 32'hbf6b9e6e;
11'd2046: sine = 32'hbf1d14d6;
11'd2047: sine = 32'hbe9d15ba;
endcase
end
endmodule |
module yl3_interface(
input CLK, // External Clock (50Mhz in my project)
input nRST, // Inverted Reset
input [63:0] DATA, // All 8 Characters (8 x 8 bits)
input LOAD, // Load the data in
output READY, // Ready for input to be loaded
output DIO, // Serial data output
output SCK, // Serial data clock
output RCK // Serial latch
);
localparam ST_READY = 2'b00; // Ready to load data
localparam ST_READCHR = 2'b01; // Read Character
localparam ST_SHIFT = 2'b10; // Shift Character
reg [7:0] chrarr [0:7]; // 8 Character array
reg [3:0] aidx; // Index of our array
reg [7:0] posreg; // Position on display
reg [7:0] chrreg; // Character in .GFEDBC inverse binary
reg [15:0] dataout; // Concatinated position and character data to output to YL-3
reg [3:0] delaycnt; // Clock divider
reg [4:0] bitcnt; // Counter / state-machine for which bit has been shifted
reg [2:0] lchcnt; // Counter for holding the latch high.
reg [1:0] state; // Our current state
reg loaded; // Data is loaded
reg EN;
reg ENA;
reg ENB;
wire RDY;
// Connect Dual SN74HC595 interface
YL3_Shift_Register ShiftReg(
.CLK(CLK),
.DATA_IN(dataout),
.EN_IN(EN),
.RDY(RDY),
.RCLK(RCK),
.SRCLK(SCK),
.SER_OUT(DIO)
);
// Load our data
always @(negedge RDY)
begin
ENA <= 0;
end
always @(posedge CLK)
begin
if(!nRST)
begin
state <= ST_READY;
chrarr[0] = 0;
chrarr[1] = 0;
chrarr[2] = 0;
chrarr[3] = 0;
chrarr[4] = 0;
chrarr[5] = 0;
chrarr[6] = 0;
chrarr[7] = 0;
aidx <= 4'b0;
posreg <= 8'b0;
chrreg <= 8'b0;
dataout <= 16'b1111_1111_1111_1111;
delaycnt <= 4'b0;
lchcnt <= 3'b0;
bitcnt <= 5'b0;
loaded <= 1'b0;
end
else
begin
if(state != ST_SHIFT)
begin
end
// Deal with the states
case(state)
ST_READY:
begin
// Read to Load data, so lets do so
if(LOAD == 1)
begin
//$display("ST_READY STATE - LOAD = 1");
if({chrarr[0], chrarr[1], chrarr[2], chrarr[3], chrarr[4], chrarr[5], chrarr[6], chrarr[7]} != DATA)
begin
//$display("NEEDS TO LOAD DATA");
chrarr[0] = DATA[63:56];
chrarr[1] = DATA[55:48];
chrarr[2] = DATA[47:40];
chrarr[3] = DATA[39:32];
chrarr[4] = DATA[31:24];
chrarr[5] = DATA[23:16];
chrarr[6] = DATA[15:8];
chrarr[7] = DATA[7:0];
end
else
begin
//$display("DATA: %h", data);
//$display("ARRY: %h", {chrarr[0], chrarr[1], chrarr[2], chrarr[3], chrarr[4], chrarr[5], chrarr[6], chrarr[7]});
//$display("DATA LOADED");
loaded <= 1'b1;
state <= ST_READCHR;
end
end
end
ST_READCHR:
begin
// Read the character from memory, convert it to 16 bit binary for position and 7-Segment leds.
//$display("DATAOUT: %b", dataout);
//$display("POSCHR : %b", {posreg, chrreg});
delaycnt <= 4'b0;
if({posreg, chrreg} != dataout)
begin
//$display("DATAOUT NEEDS TO BE CREATED!");
case (aidx)
0:
begin
posreg <= 8'b0000_0001;
end
1:
begin
posreg <= 8'b0000_0010;
end
2:
begin
posreg <= 8'b0000_0100;
end
3:
begin
posreg <= 8'b0000_1000;
end
4:
begin
posreg <= 8'b0001_0000;
end
5:
begin
posreg <= 8'b0010_0000;
end
6:
begin
posreg <= 8'b0100_0000;
end
7:
begin
posreg <= 8'b1000_0000;
end
default:
begin
//posreg <= 8'b0000_0001;
end
endcase
case (chrarr[aidx])
"0", "O":
begin
chrreg <= 8'b1100_0000;
end
"1":
begin
chrreg <= 8'b1111_1001;
end
"2":
begin
chrreg <= 8'b1010_0100;
end
"3":
begin
chrreg <= 8'b1011_0000;
end
"4":
begin
chrreg <= 8'b1001_1001;
end
"5", "S", "s":
begin
chrreg <= 8'b1001_0010;
end
"6":
begin
chrreg <= 8'b1000_0010;
end
"7":
begin
chrreg <= 8'b1111_1000;
end
"8":
begin
chrreg <= 8'b1000_0000;
end
"9":
begin
chrreg <= 8'b1001_1000;
end
"A":
begin
chrreg <= 8'b1000_1000;
end
"a":
begin
chrreg <= 8'b1010_0000;
end
"B", "b":
begin
chrreg <= 8'b1000_0011;
end
"C":
begin
chrreg <= 8'b1100_0110;
end
"c":
begin
chrreg <= 8'b1010_0111;
end
"D", "d":
begin
chrreg <= 8'b1010_0001;
end
"E":
begin
chrreg <= 8'b1000_0110;
end
"e":
begin
chrreg <= 8'b1000_0100;
end
"F", "f":
begin
chrreg <= 8'b1000_1110;
end
"G", "g":
begin
chrreg <= 8'b1001_0000;
end
"H":
begin
chrreg <= 8'b1000_1001;
end
"h":
begin
chrreg <= 8'b1000_1011;
end
"J":
begin
chrreg <= 8'b1111_0001;
end
"j":
begin
chrreg <= 8'b1111_0011;
end
"L":
begin
chrreg <= 8'b1100_0111;
end
"l":
begin
chrreg <= 8'b1110_0111;
end
"N", "n":
begin
chrreg <= 8'b1010_1011;
end
"o":
begin
chrreg <= 8'b1010_1011;
end
"P", "p":
begin
chrreg <= 8'b1000_1100;
end
"Q":
begin
chrreg <= 8'b0100_0000;
end
"q":
begin
chrreg <= 8'b0010_0011;
end
"R":
begin
chrreg <= 8'b1100_1110;
end
"r":
begin
chrreg <= 8'b1010_1111;
end
"T", "t":
begin
chrreg <= 8'b1000_0111;
end
"U":
begin
chrreg <= 8'b1100_0001;
end
"u":
begin
chrreg <= 8'b1110_0011;
end
"°":
begin
chrreg <= 8'b1001_1100;
end
".":
begin
chrreg <= 8'b0111_1111;
end
default:
begin
chrreg <= 8'b1111_1111;
end
endcase
dataout <= {posreg, chrreg};
end
else
begin
//$display("DATAOUT GOOD");
//$display("DATAOUT: %b", dataout);
aidx <= aidx + 1'b1;
state <= ST_SHIFT;
end
end
ST_SHIFT:
begin
if(RDY)
begin
if(aidx < 8)
begin
// Not done with our array (string), get next character
//$display("ST_LATCH -> ST_READCHR");
posreg <= 8'b0;
chrreg <= 8'b0;
dataout <= 16'b1;
state <= ST_READCHR;
end
else
begin
// We are done with our array (string) and let go back into ready mode.
//$display("ST_LATCH -> ST_READY");
loaded <= 1'b0;
state <= ST_READY;
end
end
end
endcase
end
end
always @(state)
begin
if(state == ST_SHIFT)
begin
if(RDY)
begin
ENB <= 1;
end
else
begin
ENB <= 0;
end
end
end
always @(*)
begin
EN <= (ENA || ENB);
end
// Assign the ready state output.
assign READY = (state == ST_READY && loaded == 0) ? 1'b1 : 1'b0;
endmodule |
module ir_recieve(
clk, rst, sda, recieve_status,recieved_data
);
input clk;
input rst;
input sda;
output recieve_status;
output [10:0] recieved_data;
reg[1:0] sda_reg;
wire falling_edge;
wire rising_edge;
reg[10:0] recieved_data;
reg[7:0] cyc_cnt;
reg[7:0] start_cnt;
reg recieve_status;
reg [31:0] time_cnt;
reg [2:0] start_bits;
reg data_start;
always @(posedge clk or negedge rst)begin
if(!rst)begin
start_bits <= 'h0;
start_cnt <= 'h0;
end
else begin
if(falling_edge && start_cnt < 'd3)begin
start_bits[start_cnt]<= 1'b1;
start_cnt <= start_cnt + 1'b1;
end
else begin
start_bits <= start_bits;
start_cnt <= start_cnt;
end
end
end
always @(posedge clk or negedge rst)begin
if(!rst)begin
time_cnt <= 'h0;
cyc_cnt <= 'h0;
data_start <= 'h0;
end
else begin
if(start_bits == 3'b111 && data_start == 0 && time_cnt < 'd44500)
time_cnt <= time_cnt + 1'b1;
else if(start_bits == 3'b111 && data_start == 0 && time_cnt == 'd44500)begin
time_cnt <= 'h0;
data_start <= 'h1;
end
else begin
if(start_bits == 3'b111 && time_cnt < 'd89000 && cyc_cnt < 'd11 && data_start == 1)begin
time_cnt <= time_cnt + 1'b1;
end
else if(start_bits == 3'b111 && time_cnt == 'd89000 && cyc_cnt < 'd11 && data_start == 1)begin
time_cnt <= 'h0;
cyc_cnt <= cyc_cnt + 1'b1;
end
else begin
time_cnt <= time_cnt;
cyc_cnt <= cyc_cnt;
data_start <= data_start;
end
end
end
end
always @(posedge clk or negedge rst)begin
if(!rst)
sda_reg <= 2'b11;
else begin
sda_reg[0] <= sda;
sda_reg[1] <= sda_reg[0];
end
end
assign falling_edge = (sda_reg[1:0] == 2'b10) ? 1'b1 : 1'b0;
assign rising_edge = (sda_reg[1:0] == 2'b01) ? 1'b1 : 1'b0;
always @(posedge clk or negedge rst)begin
if(!rst)begin
recieved_data <= 'h0;
end
else begin
if(falling_edge && time_cnt > 'd30000 && time_cnt < 'd60000 && cyc_cnt < 'd11)begin
recieved_data[cyc_cnt] <= 1'b1;
end
else if(rising_edge && time_cnt > 'd30000 && time_cnt < 'd60000 && cyc_cnt < 'd11)begin
recieved_data[cyc_cnt] <= 1'b0;
end
else begin
recieved_data <= recieved_data;
end
end
end
always @(posedge clk or negedge rst)begin
if(!rst)
recieve_status <= 1'b0;
else
recieve_status <= ( recieved_data == 11'b00011110101) ? 1'b1 : 1'b0;
//recieve_status <= ( cyc_cnt == 11) ? 1'b1 : 1'b0;
//recieve_status <= ( recieved_data == 22'b1010101010101010101010) ? 1'b1 : 1'b0;
end
endmodule |
module IOBUFDS_DIFF_OUT_DCIEN (O, OB, IO, IOB, DCITERMDISABLE, I, IBUFDISABLE, TM, TS);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SIM_DEVICE = "7SERIES";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
output OB;
inout IO;
inout IOB;
input DCITERMDISABLE;
input I;
input IBUFDISABLE;
input TM;
input TS;
// define constants
localparam MODULE_NAME = "IOBUFDS_DIFF_OUT_DCIEN";
wire t1, t2, out_val, out_b_val;
wire T_OR_IBUFDISABLE_1;
wire T_OR_IBUFDISABLE_2;
tri0 GTS = glbl.GTS;
or O1 (t1, GTS, TM);
bufif0 B1 (IO, I, t1);
or O2 (t2, GTS, TS);
notif0 N2 (IOB, I, t2);
reg O_int, OB_int;
reg DQS_BIAS_BINARY = 1'b0;
initial begin
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on IOBUFDS_DIFF_OUT_DCIEN instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
#1 $finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IOBUFDS_DIFF_OUT_DCIEN instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
#1 $finish;
end
endcase
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on IOBUFDS_DIFF_OUT_DCIEN instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DQS_BIAS);
#1 $finish;
end
endcase
if ((SIM_DEVICE != "7SERIES") &&
(SIM_DEVICE != "ULTRASCALE") &&
(SIM_DEVICE != "VERSAL_AI_CORE") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_EDGE") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_RF") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES1") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES2") &&
(SIM_DEVICE != "VERSAL_HBM") &&
(SIM_DEVICE != "VERSAL_HBM_ES1") &&
(SIM_DEVICE != "VERSAL_HBM_ES2") &&
(SIM_DEVICE != "VERSAL_PREMIUM") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES1") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES2") &&
(SIM_DEVICE != "VERSAL_PRIME") &&
(SIM_DEVICE != "VERSAL_PRIME_ES1") &&
(SIM_DEVICE != "VERSAL_PRIME_ES2")) begin
$display("Error: [Unisim %s-106] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE);
#1 $finish;
end
end
generate
case (SIM_DEVICE)
"7SERIES" : begin
assign out_val = 1'b1;
assign out_b_val = 1'b1;
end
"ULTRASCALE" : begin
assign out_val = 1'b0;
assign out_b_val = 1'bx;
end
default : begin
assign out_val = 1'b0;
assign out_b_val = 1'b0;
end
endcase
endgenerate
always @(IO or IOB or DQS_BIAS_BINARY) begin
if (IO == 1'b1 && IOB == 1'b0) begin
O_int <= IO;
OB_int <= ~IO;
end
else if (IO == 1'b0 && IOB == 1'b1) begin
O_int <= IO;
OB_int <= ~IO;
end
else if ((IO === 1'bz || IO == 1'b0) && (IOB === 1'bz || IOB == 1'b1)) begin
if (DQS_BIAS_BINARY == 1'b1) begin
O_int <= 1'b0;
OB_int <= 1'b1;
end else begin
O_int <= 1'bx;
OB_int <= 1'bx;
end
end
else begin
O_int <= 1'bx;
OB_int <= 1'bx;
end
end
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign T_OR_IBUFDISABLE_1 = ~TM || IBUFDISABLE;
assign T_OR_IBUFDISABLE_2 = ~TS || IBUFDISABLE;
assign O = (T_OR_IBUFDISABLE_1 == 1'b1) ? out_val : (T_OR_IBUFDISABLE_1 == 1'b0) ? O_int : 1'bx;
assign OB = (T_OR_IBUFDISABLE_2 == 1'b1) ? out_b_val : (T_OR_IBUFDISABLE_2 == 1'b0) ? OB_int : 1'bx;
end
"FALSE" : begin
assign O = O_int;
assign OB = OB_int;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(DCITERMDISABLE => O) = (0:0:0, 0:0:0);
(DCITERMDISABLE => OB) = (0:0:0, 0:0:0);
(DCITERMDISABLE => IO) = (0:0:0, 0:0:0);
(DCITERMDISABLE => IOB) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(I => IO) = (0:0:0, 0:0:0);
(I => IOB) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(IO => OB) = (0:0:0, 0:0:0);
(IO => IOB) = (0:0:0, 0:0:0);
(IOB => O) = (0:0:0, 0:0:0);
(IOB => OB) = (0:0:0, 0:0:0);
(IOB => IO) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => OB) = (0:0:0, 0:0:0);
(IBUFDISABLE => IO) = (0:0:0, 0:0:0);
(IBUFDISABLE => IOB) = (0:0:0, 0:0:0);
(TM => O) = (0:0:0, 0:0:0);
(TM => OB) = (0:0:0, 0:0:0);
(TM => IO) = (0:0:0, 0:0:0);
(TM => IOB) = (0:0:0, 0:0:0);
(TS => O) = (0:0:0, 0:0:0);
(TS => OB) = (0:0:0, 0:0:0);
(TS => IO) = (0:0:0, 0:0:0);
(TS => IOB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule |
module sky130_fd_sc_lp__nand4b (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule |
module sky130_fd_sc_hs__maj3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule |
module outputs)
wire [11:0] chipid; // From elink2 of axi_elink.v
wire elink0_cclk_n; // From elink0 of elink.v
wire elink0_cclk_p; // From elink0 of elink.v
wire elink0_chip_resetb; // From elink0 of elink.v
wire [11:0] elink0_chipid; // From elink0 of elink.v
wire elink0_mailbox_full; // From elink0 of elink.v
wire elink0_mailbox_not_empty;// From elink0 of elink.v
wire elink0_rxo_rd_wait_n; // From elink0 of elink.v
wire elink0_rxo_rd_wait_p; // From elink0 of elink.v
wire elink0_rxo_wr_wait_n; // From elink0 of elink.v
wire elink0_rxo_wr_wait_p; // From elink0 of elink.v
wire elink0_rxrd_access; // From elink0 of elink.v
wire [PW-1:0] elink0_rxrd_packet; // From elink0 of elink.v
wire elink0_rxrr_access; // From elink0 of elink.v
wire [PW-1:0] elink0_rxrr_packet; // From elink0 of elink.v
wire elink0_rxwr_access; // From elink0 of elink.v
wire [PW-1:0] elink0_rxwr_packet; // From elink0 of elink.v
wire elink0_timeout; // From elink0 of elink.v
wire [7:0] elink0_txo_data_n; // From elink0 of elink.v
wire [7:0] elink0_txo_data_p; // From elink0 of elink.v
wire elink0_txo_frame_n; // From elink0 of elink.v
wire elink0_txo_frame_p; // From elink0 of elink.v
wire elink0_txo_lclk_n; // From elink0 of elink.v
wire elink0_txo_lclk_p; // From elink0 of elink.v
wire elink0_txrd_wait; // From elink0 of elink.v
wire elink0_txrr_wait; // From elink0 of elink.v
wire elink0_txwr_wait; // From elink0 of elink.v
wire elink1_cclk_n; // From elink1 of elink.v
wire elink1_cclk_p; // From elink1 of elink.v
wire elink1_chip_resetb; // From elink1 of elink.v
wire [11:0] elink1_chipid; // From elink1 of elink.v
wire elink1_mailbox_full; // From elink1 of elink.v
wire elink1_mailbox_not_empty;// From elink1 of elink.v
wire elink1_rxo_rd_wait_n; // From elink1 of elink.v
wire elink1_rxo_rd_wait_p; // From elink1 of elink.v
wire elink1_rxo_wr_wait_n; // From elink1 of elink.v
wire elink1_rxo_wr_wait_p; // From elink1 of elink.v
wire elink1_rxrd_access; // From elink1 of elink.v
wire [PW-1:0] elink1_rxrd_packet; // From elink1 of elink.v
wire elink1_rxrr_access; // From elink1 of elink.v
wire [PW-1:0] elink1_rxrr_packet; // From elink1 of elink.v
wire elink1_rxwr_access; // From elink1 of elink.v
wire [PW-1:0] elink1_rxwr_packet; // From elink1 of elink.v
wire elink1_timeout; // From elink1 of elink.v
wire [7:0] elink1_txo_data_n; // From elink1 of elink.v
wire [7:0] elink1_txo_data_p; // From elink1 of elink.v
wire elink1_txo_frame_n; // From elink1 of elink.v
wire elink1_txo_frame_p; // From elink1 of elink.v
wire elink1_txo_lclk_n; // From elink1 of elink.v
wire elink1_txo_lclk_p; // From elink1 of elink.v
wire elink1_txrd_wait; // From elink1 of elink.v
wire elink1_txrr_access; // From emem of ememory.v
wire [PW-1:0] elink1_txrr_packet; // From emem of ememory.v
wire elink1_txrr_wait; // From elink1 of elink.v
wire elink1_txwr_wait; // From elink1 of elink.v
wire [31:0] m_axi_araddr; // From tx_emaxi of emaxi.v
wire [1:0] m_axi_arburst; // From tx_emaxi of emaxi.v
wire [3:0] m_axi_arcache; // From tx_emaxi of emaxi.v
wire [M_IDW-1:0] m_axi_arid; // From tx_emaxi of emaxi.v
wire [7:0] m_axi_arlen; // From tx_emaxi of emaxi.v
wire [1:0] m_axi_arlock; // From tx_emaxi of emaxi.v
wire [2:0] m_axi_arprot; // From tx_emaxi of emaxi.v
wire [3:0] m_axi_arqos; // From tx_emaxi of emaxi.v
wire m_axi_arready; // From elink2 of axi_elink.v
wire [2:0] m_axi_arsize; // From tx_emaxi of emaxi.v
wire m_axi_arvalid; // From tx_emaxi of emaxi.v
wire [31:0] m_axi_awaddr; // From tx_emaxi of emaxi.v
wire [1:0] m_axi_awburst; // From tx_emaxi of emaxi.v
wire [3:0] m_axi_awcache; // From tx_emaxi of emaxi.v
wire [M_IDW-1:0] m_axi_awid; // From tx_emaxi of emaxi.v
wire [7:0] m_axi_awlen; // From tx_emaxi of emaxi.v
wire [1:0] m_axi_awlock; // From tx_emaxi of emaxi.v
wire [2:0] m_axi_awprot; // From tx_emaxi of emaxi.v
wire [3:0] m_axi_awqos; // From tx_emaxi of emaxi.v
wire m_axi_awready; // From elink2 of axi_elink.v
wire [2:0] m_axi_awsize; // From tx_emaxi of emaxi.v
wire m_axi_awvalid; // From tx_emaxi of emaxi.v
wire [S_IDW-1:0] m_axi_bid; // From elink2 of axi_elink.v
wire m_axi_bready; // From tx_emaxi of emaxi.v
wire [1:0] m_axi_bresp; // From elink2 of axi_elink.v
wire m_axi_bvalid; // From elink2 of axi_elink.v
wire [31:0] m_axi_rdata; // From elink2 of axi_elink.v
wire [S_IDW-1:0] m_axi_rid; // From elink2 of axi_elink.v
wire m_axi_rlast; // From elink2 of axi_elink.v
wire m_axi_rready; // From tx_emaxi of emaxi.v
wire [1:0] m_axi_rresp; // From elink2 of axi_elink.v
wire m_axi_rvalid; // From elink2 of axi_elink.v
wire [63:0] m_axi_wdata; // From tx_emaxi of emaxi.v
wire [M_IDW-1:0] m_axi_wid; // From tx_emaxi of emaxi.v
wire m_axi_wlast; // From tx_emaxi of emaxi.v
wire m_axi_wready; // From elink2 of axi_elink.v
wire [7:0] m_axi_wstrb; // From tx_emaxi of emaxi.v
wire m_axi_wvalid; // From tx_emaxi of emaxi.v
wire rxo_rd_wait_n; // From elink2 of axi_elink.v
wire rxo_rd_wait_p; // From elink2 of axi_elink.v
wire rxo_wr_wait_n; // From elink2 of axi_elink.v
wire rxo_wr_wait_p; // From elink2 of axi_elink.v
wire [31:0] s_axi_araddr; // From elink2 of axi_elink.v
wire [1:0] s_axi_arburst; // From elink2 of axi_elink.v
wire [3:0] s_axi_arcache; // From elink2 of axi_elink.v
wire [M_IDW-1:0] s_axi_arid; // From elink2 of axi_elink.v
wire [7:0] s_axi_arlen; // From elink2 of axi_elink.v
wire [1:0] s_axi_arlock; // From elink2 of axi_elink.v
wire [2:0] s_axi_arprot; // From elink2 of axi_elink.v
wire [3:0] s_axi_arqos; // From elink2 of axi_elink.v
wire s_axi_arready; // From rx_esaxi of esaxi.v
wire [2:0] s_axi_arsize; // From elink2 of axi_elink.v
wire s_axi_arvalid; // From elink2 of axi_elink.v
wire [31:0] s_axi_awaddr; // From elink2 of axi_elink.v
wire [1:0] s_axi_awburst; // From elink2 of axi_elink.v
wire [3:0] s_axi_awcache; // From elink2 of axi_elink.v
wire [M_IDW-1:0] s_axi_awid; // From elink2 of axi_elink.v
wire [7:0] s_axi_awlen; // From elink2 of axi_elink.v
wire [1:0] s_axi_awlock; // From elink2 of axi_elink.v
wire [2:0] s_axi_awprot; // From elink2 of axi_elink.v
wire [3:0] s_axi_awqos; // From elink2 of axi_elink.v
wire s_axi_awready; // From rx_esaxi of esaxi.v
wire [2:0] s_axi_awsize; // From elink2 of axi_elink.v
wire s_axi_awvalid; // From elink2 of axi_elink.v
wire [S_IDW-1:0] s_axi_bid; // From rx_esaxi of esaxi.v
wire s_axi_bready; // From elink2 of axi_elink.v
wire [1:0] s_axi_bresp; // From rx_esaxi of esaxi.v
wire s_axi_bvalid; // From rx_esaxi of esaxi.v
wire [31:0] s_axi_rdata; // From rx_esaxi of esaxi.v
wire [S_IDW-1:0] s_axi_rid; // From rx_esaxi of esaxi.v
wire s_axi_rlast; // From rx_esaxi of esaxi.v
wire s_axi_rready; // From elink2 of axi_elink.v
wire [1:0] s_axi_rresp; // From rx_esaxi of esaxi.v
wire s_axi_rvalid; // From rx_esaxi of esaxi.v
wire [63:0] s_axi_wdata; // From elink2 of axi_elink.v
wire [M_IDW-1:0] s_axi_wid; // From elink2 of axi_elink.v
wire s_axi_wlast; // From elink2 of axi_elink.v
wire s_axi_wready; // From rx_esaxi of esaxi.v
wire [7:0] s_axi_wstrb; // From elink2 of axi_elink.v
wire s_axi_wvalid; // From elink2 of axi_elink.v
wire [7:0] txo_data_n; // From elink2 of axi_elink.v
wire [7:0] txo_data_p; // From elink2 of axi_elink.v
wire txo_frame_n; // From elink2 of axi_elink.v
wire txo_frame_p; // From elink2 of axi_elink.v
wire txo_lclk_n; // From elink2 of axi_elink.v
wire txo_lclk_p; // From elink2 of axi_elink.v
// End of automatics
wire elink0_rxrd_wait; // To elink0 of elink.v
wire elink0_rxrr_wait; // To elink0 of elink.v
wire elink0_rxwr_wait; // To elink0 of elink.v
wire elink1_rxrd_wait; // To elink1 of elink.v
wire elink1_rxrr_wait; // To elink1 of elink.v
wire elink1_rxwr_wait; // To elink1 of elink.v
wire [3:0] colid;
wire [3:0] rowid;
wire mailbox_full;
wire mailbox_not_empty;
wire cclk_p, cclk_n;
wire chip_resetb;
wire rx_lclk_pll;
wire emem_access;
wire [PW-1:0] emem_packet;
wire dut_access;
wire [PW-1:0] dut_packet;
wire rxrr_access;
wire [PW-1:0] rxrr_packet;
wire rxwr_access;
wire [PW-1:0] rxwr_packet;
wire rxrd_access;
wire [PW-1:0] rxrd_packet;
wire elink0_txrr_access;
wire [PW-1:0] elink0_txrr_packet;
wire elink0_txwr_access;
wire [PW-1:0] elink0_txwr_packet;
wire elink0_txrd_access;
wire [PW-1:0] elink0_txrd_packet;
wire elink1_txwr_access;
wire [PW-1:0] elink1_txwr_packet;
wire elink1_txrd_access;
wire [PW-1:0] elink1_txrd_packet;
wire [7:0] elink2_txo_data_p;
wire elink2_txo_frame_p;
wire elink2_txo_lclk_p;
wire emem_wait;
reg [31:0] etime;
wire itrace = 1'b1;
//Read path
assign elink0_txrd_access = ext_access & ~ext_packet[1];
assign elink0_txrd_packet[PW-1:0] = ext_packet[PW-1:0];
//Write path
assign elink0_txwr_access = ext_access & ext_packet[1];
assign elink0_txwr_packet[PW-1:0] = ext_packet[PW-1:0];
//TX Pushback
assign dut_rd_wait = elink0_txrd_wait;// | elink2_wait_out;
assign dut_wr_wait = elink0_txwr_wait;// | elink2_wait_out ;
//Getting results back
assign dut_access = elink0_rxrr_access;
assign dut_packet[PW-1:0] = elink0_rxrr_packet[PW-1:0];
//No pushback testing on elink0
assign elink0_rxrd_wait = 1'b0;
assign elink0_rxwr_wait = 1'b0;
assign elink0_rxrr_wait = 1'b0;
//not connected
assign elink0_txrr_access = 1'b0;
assign elink0_txrr_packet[PW-1:0] = 'b0;
//######################################################################
//1ST ELINK
//######################################################################
/*elink AUTO_TEMPLATE (
// Outputs
.sys_clk (clk),
.sys_reset (reset),
.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
);
*/
defparam elink0.ID = 12'h810;
defparam elink0.ETYPE = 0;
elink elink0 (
.rxi_lclk_p (elink1_txo_lclk_p),
.rxi_lclk_n (elink1_txo_lclk_n),
.rxi_frame_p (elink1_txo_frame_p),
.rxi_frame_n (elink1_txo_frame_n),
.rxi_data_p (elink1_txo_data_p[7:0]),
.rxi_data_n (elink1_txo_data_n[7:0]),
.txi_wr_wait_p (elink1_rxo_wr_wait_p),
.txi_wr_wait_n (elink1_rxo_wr_wait_n),
.txi_rd_wait_p (elink1_rxo_rd_wait_p),
.txi_rd_wait_n (elink1_rxo_rd_wait_n),
/*AUTOINST*/
// Outputs
.rxo_wr_wait_p (elink0_rxo_wr_wait_p), // Templated
.rxo_wr_wait_n (elink0_rxo_wr_wait_n), // Templated
.rxo_rd_wait_p (elink0_rxo_rd_wait_p), // Templated
.rxo_rd_wait_n (elink0_rxo_rd_wait_n), // Templated
.txo_lclk_p (elink0_txo_lclk_p), // Templated
.txo_lclk_n (elink0_txo_lclk_n), // Templated
.txo_frame_p (elink0_txo_frame_p), // Templated
.txo_frame_n (elink0_txo_frame_n), // Templated
.txo_data_p (elink0_txo_data_p[7:0]), // Templated
.txo_data_n (elink0_txo_data_n[7:0]), // Templated
.chipid (elink0_chipid[11:0]), // Templated
.cclk_p (elink0_cclk_p), // Templated
.cclk_n (elink0_cclk_n), // Templated
.chip_resetb (elink0_chip_resetb), // Templated
.mailbox_not_empty (elink0_mailbox_not_empty), // Templated
.mailbox_full (elink0_mailbox_full), // Templated
.timeout (elink0_timeout), // Templated
.rxwr_access (elink0_rxwr_access), // Templated
.rxwr_packet (elink0_rxwr_packet[PW-1:0]), // Templated
.rxrd_access (elink0_rxrd_access), // Templated
.rxrd_packet (elink0_rxrd_packet[PW-1:0]), // Templated
.rxrr_access (elink0_rxrr_access), // Templated
.rxrr_packet (elink0_rxrr_packet[PW-1:0]), // Templated
.txwr_wait (elink0_txwr_wait), // Templated
.txrd_wait (elink0_txrd_wait), // Templated
.txrr_wait (elink0_txrr_wait), // Templated
// Inputs
.sys_reset (reset), // Templated
.sys_clk (clk), // Templated
.rxwr_wait (elink0_rxwr_wait), // Templated
.rxrd_wait (elink0_rxrd_wait), // Templated
.rxrr_wait (elink0_rxrr_wait), // Templated
.txwr_access (elink0_txwr_access), // Templated
.txwr_packet (elink0_txwr_packet[PW-1:0]), // Templated
.txrd_access (elink0_txrd_access), // Templated
.txrd_packet (elink0_txrd_packet[PW-1:0]), // Templated
.txrr_access (elink0_txrr_access), // Templated
.txrr_packet (elink0_txrr_packet[PW-1:0])); // Templated
//######################################################################
//2ND ELINK (WITH EPIPHANY MEMORY)
//######################################################################
//No read/write from elink1 (for now)
assign elink1_txrd_access = 1'b0;
assign elink1_txrd_packet = 'b0;
assign elink1_txwr_access = 1'b0;
assign elink1_txwr_packet = 'b0;
assign elink1_rxrr_wait = 1'b0;
defparam elink1.ID = 12'h820;
defparam elink1.ETYPE = 0;
elink elink1 (
.rxi_lclk_p (elink0_txo_lclk_p),
.rxi_lclk_n (elink0_txo_lclk_n),
.rxi_frame_p (elink0_txo_frame_p),
.rxi_frame_n (elink0_txo_frame_n),
.rxi_data_p (elink0_txo_data_p[7:0]),
.rxi_data_n (elink0_txo_data_n[7:0]),
.txi_wr_wait_p (elink0_rxo_wr_wait_p),
.txi_wr_wait_n (elink0_rxo_wr_wait_n),
.txi_rd_wait_p (elink0_rxo_rd_wait_p),
.txi_rd_wait_n (elink0_rxo_rd_wait_n),
/*AUTOINST*/
// Outputs
.rxo_wr_wait_p (elink1_rxo_wr_wait_p), // Templated
.rxo_wr_wait_n (elink1_rxo_wr_wait_n), // Templated
.rxo_rd_wait_p (elink1_rxo_rd_wait_p), // Templated
.rxo_rd_wait_n (elink1_rxo_rd_wait_n), // Templated
.txo_lclk_p (elink1_txo_lclk_p), // Templated
.txo_lclk_n (elink1_txo_lclk_n), // Templated
.txo_frame_p (elink1_txo_frame_p), // Templated
.txo_frame_n (elink1_txo_frame_n), // Templated
.txo_data_p (elink1_txo_data_p[7:0]), // Templated
.txo_data_n (elink1_txo_data_n[7:0]), // Templated
.chipid (elink1_chipid[11:0]), // Templated
.cclk_p (elink1_cclk_p), // Templated
.cclk_n (elink1_cclk_n), // Templated
.chip_resetb (elink1_chip_resetb), // Templated
.mailbox_not_empty (elink1_mailbox_not_empty), // Templated
.mailbox_full (elink1_mailbox_full), // Templated
.timeout (elink1_timeout), // Templated
.rxwr_access (elink1_rxwr_access), // Templated
.rxwr_packet (elink1_rxwr_packet[PW-1:0]), // Templated
.rxrd_access (elink1_rxrd_access), // Templated
.rxrd_packet (elink1_rxrd_packet[PW-1:0]), // Templated
.rxrr_access (elink1_rxrr_access), // Templated
.rxrr_packet (elink1_rxrr_packet[PW-1:0]), // Templated
.txwr_wait (elink1_txwr_wait), // Templated
.txrd_wait (elink1_txrd_wait), // Templated
.txrr_wait (elink1_txrr_wait), // Templated
// Inputs
.sys_reset (reset), // Templated
.sys_clk (clk), // Templated
.rxwr_wait (elink1_rxwr_wait), // Templated
.rxrd_wait (elink1_rxrd_wait), // Templated
.rxrr_wait (elink1_rxrr_wait), // Templated
.txwr_access (elink1_txwr_access), // Templated
.txwr_packet (elink1_txwr_packet[PW-1:0]), // Templated
.txrd_access (elink1_txrd_access), // Templated
.txrd_packet (elink1_txrd_packet[PW-1:0]), // Templated
.txrr_access (elink1_txrr_access), // Templated
.txrr_packet (elink1_txrr_packet[PW-1:0])); // Templated
reg [8:0] counter;
wire elink1_random_wait;
always @ (posedge clk)
if(reset)
counter <= 'b0;
else
counter <= counter+1;
assign elink1_random_wait = counter > 256;
assign emem_access = (elink1_rxwr_access & ~(elink1_rxwr_packet[39:28]==elink1.ID)) |
(elink1_rxrd_access & ~(elink1_rxrd_packet[39:28]==elink1.ID));
assign emem_packet[PW-1:0] = elink1_rxwr_access ? elink1_rxwr_packet[PW-1:0]:
elink1_rxrd_packet[PW-1:0];
assign elink1_rxrd_wait = emem_wait | elink1_rxwr_access;
assign elink1_rxwr_wait = 1'b0;//elink1_random_wait
/*ememory AUTO_TEMPLATE (
// Outputs
.\(.*\)_out (elink1_txrr_\1[]),
.\(.*\)_in (emem_\1[]),
.wait_out (emem_wait),
);
*/
ememory emem (.wait_in (1'b0), //only one read at a time, set to zero for no1
.clk (clk),
.wait_out (emem_wait),
/*AUTOINST*/
// Outputs
.access_out (elink1_txrr_access), // Templated
.packet_out (elink1_txrr_packet[PW-1:0]), // Templated
// Inputs
.reset (reset),
.access_in (emem_access), // Templated
.packet_in (emem_packet[PW-1:0])); // Templated
//######################################################################
//3rd ELINK (LOOPBACK), WITH EMAXI,ESAXI
//######################################################################
/*axi_elink AUTO_TEMPLATE (.m_\(.*\) (s_\1[]),
.s_\(.*\) (m_\1[]),
);
*/
defparam elink2.ID = 12'h810;
defparam elink2.ETYPE = 0;
axi_elink elink2 (.sys_clk (clk),
.m_axi_aresetn (~reset),
.s_axi_aresetn (~reset),
.rxi_lclk_p (txo_lclk_p),
.rxi_lclk_n (txo_lclk_n),
.rxi_frame_p (txo_frame_p),
.rxi_frame_n (txo_frame_n),
.rxi_data_p (txo_data_p[7:0]),
.rxi_data_n (txo_data_n[7:0]),
.txi_wr_wait_p (rxo_wr_wait_p),
.txi_wr_wait_n (rxo_wr_wait_n),
.txi_rd_wait_p (rxo_rd_wait_p),
.txi_rd_wait_n (rxo_rd_wait_n),
.chip_resetb (chip_resetb),
.cclk_p (cclk_p),
.cclk_n (cclk_n),
/*AUTOINST*/
// Outputs
.rxo_wr_wait_p (rxo_wr_wait_p),
.rxo_wr_wait_n (rxo_wr_wait_n),
.rxo_rd_wait_p (rxo_rd_wait_p),
.rxo_rd_wait_n (rxo_rd_wait_n),
.txo_lclk_p (txo_lclk_p),
.txo_lclk_n (txo_lclk_n),
.txo_frame_p (txo_frame_p),
.txo_frame_n (txo_frame_n),
.txo_data_p (txo_data_p[7:0]),
.txo_data_n (txo_data_n[7:0]),
.chipid (chipid[11:0]),
.mailbox_not_empty (mailbox_not_empty),
.mailbox_full (mailbox_full),
.m_axi_awid (s_axi_awid[M_IDW-1:0]), // Templated
.m_axi_awaddr (s_axi_awaddr[31:0]), // Templated
.m_axi_awlen (s_axi_awlen[7:0]), // Templated
.m_axi_awsize (s_axi_awsize[2:0]), // Templated
.m_axi_awburst (s_axi_awburst[1:0]), // Templated
.m_axi_awlock (s_axi_awlock[1:0]), // Templated
.m_axi_awcache (s_axi_awcache[3:0]), // Templated
.m_axi_awprot (s_axi_awprot[2:0]), // Templated
.m_axi_awqos (s_axi_awqos[3:0]), // Templated
.m_axi_awvalid (s_axi_awvalid), // Templated
.m_axi_wid (s_axi_wid[M_IDW-1:0]), // Templated
.m_axi_wdata (s_axi_wdata[63:0]), // Templated
.m_axi_wstrb (s_axi_wstrb[7:0]), // Templated
.m_axi_wlast (s_axi_wlast), // Templated
.m_axi_wvalid (s_axi_wvalid), // Templated
.m_axi_bready (s_axi_bready), // Templated
.m_axi_arid (s_axi_arid[M_IDW-1:0]), // Templated
.m_axi_araddr (s_axi_araddr[31:0]), // Templated
.m_axi_arlen (s_axi_arlen[7:0]), // Templated
.m_axi_arsize (s_axi_arsize[2:0]), // Templated
.m_axi_arburst (s_axi_arburst[1:0]), // Templated
.m_axi_arlock (s_axi_arlock[1:0]), // Templated
.m_axi_arcache (s_axi_arcache[3:0]), // Templated
.m_axi_arprot (s_axi_arprot[2:0]), // Templated
.m_axi_arqos (s_axi_arqos[3:0]), // Templated
.m_axi_arvalid (s_axi_arvalid), // Templated
.m_axi_rready (s_axi_rready), // Templated
.s_axi_arready (m_axi_arready), // Templated
.s_axi_awready (m_axi_awready), // Templated
.s_axi_bid (m_axi_bid[S_IDW-1:0]), // Templated
.s_axi_bresp (m_axi_bresp[1:0]), // Templated
.s_axi_bvalid (m_axi_bvalid), // Templated
.s_axi_rid (m_axi_rid[S_IDW-1:0]), // Templated
.s_axi_rdata (m_axi_rdata[31:0]), // Templated
.s_axi_rlast (m_axi_rlast), // Templated
.s_axi_rresp (m_axi_rresp[1:0]), // Templated
.s_axi_rvalid (m_axi_rvalid), // Templated
.s_axi_wready (m_axi_wready), // Templated
// Inputs
.reset (reset),
.m_axi_awready (s_axi_awready), // Templated
.m_axi_wready (s_axi_wready), // Templated
.m_axi_bid (s_axi_bid[M_IDW-1:0]), // Templated
.m_axi_bresp (s_axi_bresp[1:0]), // Templated
.m_axi_bvalid (s_axi_bvalid), // Templated
.m_axi_arready (s_axi_arready), // Templated
.m_axi_rid (s_axi_rid[M_IDW-1:0]), // Templated
.m_axi_rdata (s_axi_rdata[63:0]), // Templated
.m_axi_rresp (s_axi_rresp[1:0]), // Templated
.m_axi_rlast (s_axi_rlast), // Templated
.m_axi_rvalid (s_axi_rvalid), // Templated
.s_axi_arid (m_axi_arid[S_IDW-1:0]), // Templated
.s_axi_araddr (m_axi_araddr[31:0]), // Templated
.s_axi_arburst (m_axi_arburst[1:0]), // Templated
.s_axi_arcache (m_axi_arcache[3:0]), // Templated
.s_axi_arlock (m_axi_arlock[1:0]), // Templated
.s_axi_arlen (m_axi_arlen[7:0]), // Templated
.s_axi_arprot (m_axi_arprot[2:0]), // Templated
.s_axi_arqos (m_axi_arqos[3:0]), // Templated
.s_axi_arsize (m_axi_arsize[2:0]), // Templated
.s_axi_arvalid (m_axi_arvalid), // Templated
.s_axi_awid (m_axi_awid[S_IDW-1:0]), // Templated
.s_axi_awaddr (m_axi_awaddr[31:0]), // Templated
.s_axi_awburst (m_axi_awburst[1:0]), // Templated
.s_axi_awcache (m_axi_awcache[3:0]), // Templated
.s_axi_awlock (m_axi_awlock[1:0]), // Templated
.s_axi_awlen (m_axi_awlen[7:0]), // Templated
.s_axi_awprot (m_axi_awprot[2:0]), // Templated
.s_axi_awqos (m_axi_awqos[3:0]), // Templated
.s_axi_awsize (m_axi_awsize[2:0]), // Templated
.s_axi_awvalid (m_axi_awvalid), // Templated
.s_axi_bready (m_axi_bready), // Templated
.s_axi_rready (m_axi_rready), // Templated
.s_axi_wid (m_axi_wid[S_IDW-1:0]), // Templated
.s_axi_wdata (m_axi_wdata[31:0]), // Templated
.s_axi_wlast (m_axi_wlast), // Templated
.s_axi_wstrb (m_axi_wstrb[3:0]), // Templated
.s_axi_wvalid (m_axi_wvalid)); // Templated
//HACK!!!!!
wire txrr_access;
wire [PW-1:0] txrr_packet;
//Read path
assign rxrd_access = elink_axi_access & ~elink_axi_packet[1];
assign rxrd_packet[PW-1:0] = elink_axi_packet[PW-1:0];
//Write path
assign rxwr_access = elink_axi_access & elink_axi_packet[1];
assign rxwr_packet[PW-1:0] = elink_axi_packet[PW-1:0];
wire elink_axi_access;
wire [PW-1:0] elink_axi_packet;
defparam axi_fifo.DW = 104;
defparam axi_fifo.DEPTH = 32; //TODO: fix the model, only 16/32 allowed!
fifo_cdc axi_fifo(
// Outputs
.wait_out (),
.access_out (elink_axi_access),
.packet_out (elink_axi_packet[PW-1:0]),
// Inputs
.clk_in (clk),
.clk_out (clk),
.reset_in (reset),
.reset_out (reset),
.access_in (ext_access),
.packet_in (ext_packet[PW-1:0]),
.wait_in ((rxwr_access & rxwr_wait) |
(rxrd_access & rxrd_wait)
)
);
//master interface (driving stimulus to TX path)
defparam tx_emaxi.M_IDW=M_IDW;
emaxi tx_emaxi (.m_axi_aclk (clk),
.m_axi_aresetn (~reset),
.txrr_access (), //output for monitoring
.txrr_packet (),//output for monitoring
.rxwr_wait (rxwr_wait), //ignore for now?
.rxrd_wait (rxrd_wait), //ignore for now?
.rxwr_access (rxwr_access),
.rxwr_packet (rxwr_packet[PW-1:0]),
.rxrd_access (rxrd_access),
.rxrd_packet (rxrd_packet[PW-1:0]),
.txrr_wait (1'b0),
/*AUTOINST*/
// Outputs
.m_axi_awid (m_axi_awid[M_IDW-1:0]),
.m_axi_awaddr (m_axi_awaddr[31:0]),
.m_axi_awlen (m_axi_awlen[7:0]),
.m_axi_awsize (m_axi_awsize[2:0]),
.m_axi_awburst (m_axi_awburst[1:0]),
.m_axi_awlock (m_axi_awlock[1:0]),
.m_axi_awcache (m_axi_awcache[3:0]),
.m_axi_awprot (m_axi_awprot[2:0]),
.m_axi_awqos (m_axi_awqos[3:0]),
.m_axi_awvalid (m_axi_awvalid),
.m_axi_wid (m_axi_wid[M_IDW-1:0]),
.m_axi_wdata (m_axi_wdata[63:0]),
.m_axi_wstrb (m_axi_wstrb[7:0]),
.m_axi_wlast (m_axi_wlast),
.m_axi_wvalid (m_axi_wvalid),
.m_axi_bready (m_axi_bready),
.m_axi_arid (m_axi_arid[M_IDW-1:0]),
.m_axi_araddr (m_axi_araddr[31:0]),
.m_axi_arlen (m_axi_arlen[7:0]),
.m_axi_arsize (m_axi_arsize[2:0]),
.m_axi_arburst (m_axi_arburst[1:0]),
.m_axi_arlock (m_axi_arlock[1:0]),
.m_axi_arcache (m_axi_arcache[3:0]),
.m_axi_arprot (m_axi_arprot[2:0]),
.m_axi_arqos (m_axi_arqos[3:0]),
.m_axi_arvalid (m_axi_arvalid),
.m_axi_rready (m_axi_rready),
// Inputs
.m_axi_awready (m_axi_awready),
.m_axi_wready (m_axi_wready),
.m_axi_bid (m_axi_bid[M_IDW-1:0]),
.m_axi_bresp (m_axi_bresp[1:0]),
.m_axi_bvalid (m_axi_bvalid),
.m_axi_arready (m_axi_arready),
.m_axi_rid (m_axi_rid[M_IDW-1:0]),
.m_axi_rdata (m_axi_rdata[63:0]),
.m_axi_rresp (m_axi_rresp[1:0]),
.m_axi_rlast (m_axi_rlast),
.m_axi_rvalid (m_axi_rvalid));
wire [PW-1:0] txwr_packet;
wire txwr_access;
wire [PW-1:0] txrd_packet;
wire txrd_access;
wire esaxi_rd_wait;
wire esaxi_wr_wait;
//slave interface (receiving from
defparam rx_esaxi.S_IDW=S_IDW;
esaxi rx_esaxi (.s_axi_aclk (clk),
.s_axi_aresetn (~reset),
.txwr_access (txwr_access),//output to emem2
.txwr_packet (txwr_packet[PW-1:0]),
.txrd_access (txrd_access),
.txrd_packet (txrd_packet[PW-1:0]),
.rxrr_wait (),
.txwr_wait (esaxi_wr_wait),
.txrd_wait (esaxi_rd_wait),
.rxrr_access (rxrr_access),
.rxrr_packet (rxrr_packet[PW-1:0]),
/*AUTOINST*/
// Outputs
.s_axi_arready (s_axi_arready),
.s_axi_awready (s_axi_awready),
.s_axi_bid (s_axi_bid[S_IDW-1:0]),
.s_axi_bresp (s_axi_bresp[1:0]),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_rid (s_axi_rid[S_IDW-1:0]),
.s_axi_rdata (s_axi_rdata[31:0]),
.s_axi_rlast (s_axi_rlast),
.s_axi_rresp (s_axi_rresp[1:0]),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_wready (s_axi_wready),
// Inputs
.s_axi_arid (s_axi_arid[S_IDW-1:0]),
.s_axi_araddr (s_axi_araddr[31:0]),
.s_axi_arburst (s_axi_arburst[1:0]),
.s_axi_arcache (s_axi_arcache[3:0]),
.s_axi_arlock (s_axi_arlock[1:0]),
.s_axi_arlen (s_axi_arlen[7:0]),
.s_axi_arprot (s_axi_arprot[2:0]),
.s_axi_arqos (s_axi_arqos[3:0]),
.s_axi_arsize (s_axi_arsize[2:0]),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_awid (s_axi_awid[S_IDW-1:0]),
.s_axi_awaddr (s_axi_awaddr[31:0]),
.s_axi_awburst (s_axi_awburst[1:0]),
.s_axi_awcache (s_axi_awcache[3:0]),
.s_axi_awlock (s_axi_awlock[1:0]),
.s_axi_awlen (s_axi_awlen[7:0]),
.s_axi_awprot (s_axi_awprot[2:0]),
.s_axi_awqos (s_axi_awqos[3:0]),
.s_axi_awsize (s_axi_awsize[2:0]),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_bready (s_axi_bready),
.s_axi_rready (s_axi_rready),
.s_axi_wid (s_axi_wid[S_IDW-1:0]),
.s_axi_wdata (s_axi_wdata[31:0]),
.s_axi_wlast (s_axi_wlast),
.s_axi_wstrb (s_axi_wstrb[3:0]),
.s_axi_wvalid (s_axi_wvalid));
wire emem2_access;
wire [PW-1:0] emem2_packet;
assign emem2_access = (txwr_access & ~(txwr_packet[39:28]==elink2.ID)) |
(txrd_access & ~(txrd_packet[39:28]==elink2.ID));
assign emem2_packet[PW-1:0] = txwr_access ? txwr_packet[PW-1:0]:
txrd_packet[PW-1:0];
assign esaxi_rd_wait = emem2_wait | txwr_access;
assign esaxi_wr_wait = 1'b0; //no wait on write
/*ememory AUTO_TEMPLATE (
// Outputs
.\(.*\)_out (elink1_txrr_\1[]),
.\(.*\)_in (emem_\1[]),
.wait_out (emem_wait),
);
*/
ememory emem2 (.wait_in (1'b0), //only one read at a time, set to zero for no1
.clk (clk),
.wait_out (emem2_wait),
.access_out (rxrr_access),
.packet_out (rxrr_packet[PW-1:0]),
// Inputs
.reset (reset),
.access_in (emem2_access),
.packet_in (emem2_packet[PW-1:0]));
//######################################################################
//4th ELINK (chip reference model)
//######################################################################
wire elink2_access;
wire [PW-1:0] elink2_packet;
defparam model_fifo.DW = 104;
defparam model_fifo.DEPTH = 32;
fifo_cdc model_fifo(
// Outputs
.wait_out (),
.access_out (elink2_access),
.packet_out (elink2_packet[PW-1:0]),
// Inputs
.clk_in (clk),
.clk_out (clk),
.reset_in (reset),
.reset_out (reset),
.access_in (ext_access),
.packet_in (ext_packet[PW-1:0]),
.wait_in (1'b0)//elink2_wait_out
);
elink_e16 elink_ref (
// Outputs
.rxi_rd_wait (),
.rxi_wr_wait (),
.txo_data (elink2_txo_data_p[7:0]),
.txo_lclk (elink2_txo_lclk_p),
.txo_frame (elink2_txo_frame_p),
.c0_mesh_access_out(),
.c0_mesh_write_out (),
.c0_mesh_dstaddr_out(),
.c0_mesh_srcaddr_out(),
.c0_mesh_data_out (),
.c0_mesh_datamode_out(),
.c0_mesh_ctrlmode_out(),
.c0_emesh_wait_out (),
.c0_mesh_wait_out (elink2_wait_out),
// Inputs
.reset (reset),
.c0_clk_in (clk),
.c1_clk_in (clk),
.c2_clk_in (clk),
.c3_clk_in (clk),
.rxi_data (8'b0),
.rxi_lclk (1'b0),
.rxi_frame (1'b0),
.txo_rd_wait (1'b0),
.txo_wr_wait (1'b0),
.c0_mesh_access_in (elink2_access),
.c0_mesh_write_in (elink2_packet[1]),
.c0_mesh_dstaddr_in(elink2_packet[39:8]),
.c0_mesh_srcaddr_in(elink2_packet[103:72]),
.c0_mesh_data_in (elink2_packet[71:40]),
.c0_mesh_datamode_in(elink2_packet[3:2]),
.c0_mesh_ctrlmode_in(elink2_packet[7:4])
);
//######################################################################
//TRANSACTION MONITORS
//######################################################################
always @ (posedge clk or posedge reset)
if(reset)
etime[31:0] <= 32'b0;
else
etime[31:0] <= etime[31:0]+1'b1;
/*emesh_monitor AUTO_TEMPLATE (
// Outputs
.emesh_\(.*\) (@"(substring vl-cell-name 0 3)"_\1[]),
);
*/
emesh_monitor #(.NAME("stimulus")) ext_monitor (.emesh_wait ((dut_rd_wait | dut_wr_wait)),//TODO:fix collisions
.clk (clk),
/*AUTOINST*/
// Inputs
.reset (reset),
.itrace (itrace),
.etime (etime[31:0]),
.emesh_access (ext_access), // Templated
.emesh_packet (ext_packet[PW-1:0])); // Templated
emesh_monitor #(.NAME("dut")) dut_monitor (.emesh_wait (1'b0),
.clk (clk),
/*AUTOINST*/
// Inputs
.reset (reset),
.itrace (itrace),
.etime (etime[31:0]),
.emesh_access (dut_access), // Templated
.emesh_packet (dut_packet[PW-1:0])); // Templated
emesh_monitor #(.NAME("emem")) mem_monitor (.emesh_wait (1'b0),
.clk (clk),
.emesh_access (emem_access),
.emesh_packet (emem_packet[PW-1:0]),
/*AUTOINST*/
// Inputs
.reset (reset),
.itrace (itrace),
.etime (etime[31:0]));
endmodule |
module instruction_decode_tb;
// Inputs
reg clk;
reg reset;
reg [31:0] pc_incrementado_in;
reg [31:0] instruction;
reg RegWrite;
reg [4:0] address_write;
reg [31:0] data_write;
// Outputs
wire [31:0] pc_incrementado_out;
wire [31:0] reg_data1;
wire [31:0] reg_data2;
wire [31:0] sgn_extend_data_imm;
wire [4:0] rd;
wire [4:0] rt;
wire wb_RegWrite_out;
wire wb_MemtoReg_out;
wire m_Branch_out;
wire m_MemRead_out;
wire m_MemWrite_out;
wire ex_RegDst_out;
wire ex_ALUOp0_out;
wire ex_ALUOp1_out;
wire ex_ALUSrc_out;
// Instantiate the Unit Under Test (UUT)
instruction_decode uut (
.clk(clk),
.reset(reset),
.pc_incrementado_in(pc_incrementado_in),
.instruction(instruction),
.RegWrite(RegWrite),
.address_write(address_write),
.data_write(data_write),
.pc_incrementado_out(pc_incrementado_out),
.reg_data1(reg_data1),
.reg_data2(reg_data2),
.sgn_extend_data_imm(sgn_extend_data_imm),
.rd(rd),
.rt(rt),
.wb_RegWrite_out(wb_RegWrite_out),
.wb_MemtoReg_out(wb_MemtoReg_out),
.m_Branch_out(m_Branch_out),
.m_MemRead_out(m_MemRead_out),
.m_MemWrite_out(m_MemWrite_out),
.ex_RegDst_out(ex_RegDst_out),
.ex_ALUOp0_out(ex_ALUOp0_out),
.ex_ALUOp1_out(ex_ALUOp1_out),
.ex_ALUSrc_out(ex_ALUSrc_out)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
pc_incrementado_in = 0;
instruction = 0;
RegWrite = 0;
address_write = 0;
data_write = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#5
begin
pc_incrementado_in = 32'b00000000_00000000_00000000_00000100;
instruction = 32'b00000000_00000000_00000000_00000000;
address_write = 5'b00100;
data_write = 1024;
end
#5 RegWrite = 1;
#3 RegWrite = 0;
#5 instruction = 32'b10001100_10000100_00000000_00000000;
#5 instruction = 32'b10101100_10000100_00000000_00000000;
#5 instruction = 32'b00010000_10000100_00000000_00000000;
end
always
#1 clk=~clk;
endmodule |
module jTDC_core (tdc_hits, tdc_data_codes, tdc_trigger_select, tdc_reset, clock_limit, geoid, iBIT,
CLK200, CLKBUS,
event_fifo_readrequest, data_fifo_readrequest, event_fifo_value, data_fifo_value );
parameter tdc_channels = 98; //number of tdc channels (max 100)
parameter encodedbits = 9; //includes hit bit
parameter fifocounts = 15; //max event size: (fifocounts+1)*1024-150;
input wire [99:0] tdc_hits;
input wire [tdc_channels*encodedbits-1:0] tdc_data_codes;
input wire tdc_trigger_select;
input wire tdc_reset;
input wire [23:0] clock_limit;
input wire [4:0] geoid;
input wire [7:0] iBIT;
input wire CLK200;
input wire CLKBUS;
input wire event_fifo_readrequest;
input wire data_fifo_readrequest;
output wire [31:0] event_fifo_value;
output wire [31:0] data_fifo_value;
genvar i;
//how many 36bit wide BRAM are needed for the TDC: ceil((tdc_channels*encodedbits+32)/36)
localparam tdc_width = 1+((tdc_channels*encodedbits+32)/36);
//how many hits should a single event hold
localparam max_event_size = (fifocounts+1)*1024-150;
wire [31:0] eventcounts;
wire [31:0] clkcounts;
wire [31:0] evententriescounts;
wire [31:0] tdc_slicecounts;
reg [8:0] tdc_slicecounts_current;
reg [31:0] final_evententriescounts;
reg reset_evententriescounts;
reg reset_clockcounter;
localparam reset=0, idle=1, prepare=2, fifocheck1=3, header1=4, header2=5, w4data=6, loadslice=7, fifocheck2=8, finish=9;
localparam hits0=10, hits1=11, hits2=12, hits3=13, hits4=14, hits5=15, hits6=16, w4filler1=17, w4filler2=18, w4filler3=19;
localparam w4filler4=20, filler=21, trailer=22, slicetrailer=23;
reg [31:0] state;
//-----------------------------------------------------------------------------
//-- TDC Trigger --------------------------------------------------------------
//-----------------------------------------------------------------------------
wire tdc_trigger;
reg tdc_trigger_request_sync;
reg tdc_trigger_request;
reg tdc_valid_trigger;
//trigger select NIM_IN[0] or LVDS_A_IN[0]
assign tdc_trigger = (tdc_trigger_select == 1'b0) ? tdc_hits[0] : tdc_hits[1];
//this delay is needed to compensate the pipe of the tdc_events,
//to actually see the trigger signal in the tdc data and
//to reset the clockcounter, so that the first new entry has a 0000 clk counts
(* KEEP = "true" *) reg [1:0] tdc_trigger_delay;
always@(posedge CLK200)
begin
tdc_trigger_delay[0] <= tdc_trigger;
tdc_trigger_delay[1] <= tdc_trigger_delay[0];
reset_clockcounter <= tdc_trigger_delay[0];
tdc_trigger_request <= tdc_trigger_delay[1];
end
//-----------------------------------------------------------------------------
//-- TDC Storage --------------------------------------------------------------
//-----------------------------------------------------------------------------
wire [24:0] tdc_hits_first_or;
generate
for (i=0; i < 25; i=i+1) begin : TDC_ORHITS
assign tdc_hits_first_or[i] = |tdc_hits[i*4+3:i*4];
end
endgenerate
reg [24:0] event_0;
reg [7:0] event_1;
reg [1:0] event_2;
reg tdc_event;
(* KEEP = "true" *) reg [36*tdc_width-32-1:0] tdc_data_2;
(* KEEP = "true" *) reg [36*tdc_width-32-1:0] tdc_data_1;
(* KEEP = "true" *) reg [36*tdc_width-32-1:0] tdc_data_0;
(* KEEP = "true" *) reg [36*tdc_width-32-1:0] tdc_data;
always@(posedge CLK200)
begin
//This part is independent from actual number of channels, we have 100 hit channels, some of them are dead, we do not care
event_0 <= tdc_hits_first_or;
event_1[0] <= |event_0[ 1: 0];
event_1[1] <= |event_0[ 3: 2];
event_1[2] <= |event_0[ 7: 4];
event_1[3] <= |event_0[11: 8];
event_1[4] <= |event_0[15:12];
event_1[5] <= |event_0[19:16];
event_1[6] <= |event_0[22:20];
event_1[7] <= |event_0[24:23];
event_2[0] <= |event_1[3:0];
event_2[1] <= |event_1[7:4];
tdc_data_0 <= tdc_data_codes;
tdc_data_1 <= tdc_data_0;
tdc_data_2 <= tdc_data_1;
tdc_event <= |event_2;
tdc_data <= tdc_data_2;
end
wire [36*tdc_width-1-32:0] tdc_out;
wire [31:0] tdc_clkout;
wire [7:0] data_size;
reg tdc_readnext;
(* KEEP_HIERARCHY = "true" *) BRAMTDC_256_SWITCHING #(.width(tdc_width)) BRAMTDC (
.d({tdc_data,clkcounts}),
.q({tdc_out,tdc_clkout}),
.CLK(CLK200),
.tdc_event(tdc_event),
.tdc_readnext(tdc_readnext),
.tdc_switch(tdc_valid_trigger),
.tdc_request(tdc_trigger_request_sync),
.data_size(data_size));
//-----------------------------------------------------------------------------
//-- Add Channel Numbers And Sort Zeros Out Of BRAM Data ----------------------
//-----------------------------------------------------------------------------
generate
for (i=0; i < 100; i=i+1) begin : Channel
wire [15:0] data;
if (i<tdc_channels)
begin
assign data[7:0] = {'b0,tdc_out[(i+1)*encodedbits-2:i*encodedbits]};
assign data[15] = tdc_out[(i+1)*encodedbits-1];
end else begin
assign data[7:0] = 'b0;
assign data[15] = 1'b0;
end
assign data[14:8] = i;
end
endgenerate
wire [15:0] gruppe_0_data; wire gruppe_0_more; wire gruppe_0_skip;
wire [15:0] gruppe_1_data; wire gruppe_1_more; wire gruppe_1_skip;
wire [15:0] gruppe_2_data; wire gruppe_2_more; wire gruppe_2_skip;
wire [15:0] gruppe_3_data; wire gruppe_3_more; wire gruppe_3_skip;
wire [15:0] gruppe_4_data; wire gruppe_4_more; wire gruppe_4_skip;
wire [15:0] gruppe_5_data; wire gruppe_5_more; wire gruppe_5_skip;
wire [15:0] gruppe_6_data; wire gruppe_6_more; wire gruppe_6_skip;
subgroup2x8 subgroup_0 (
.in00(Channel[16*0+ 0].data),
.in01(Channel[16*0+ 1].data),
.in02(Channel[16*0+ 2].data),
.in03(Channel[16*0+ 3].data),
.in04(Channel[16*0+ 4].data),
.in05(Channel[16*0+ 5].data),
.in06(Channel[16*0+ 6].data),
.in07(Channel[16*0+ 7].data),
.in08(Channel[16*0+ 8].data),
.in09(Channel[16*0+ 9].data),
.in10(Channel[16*0+10].data),
.in11(Channel[16*0+11].data),
.in12(Channel[16*0+12].data),
.in13(Channel[16*0+13].data),
.in14(Channel[16*0+14].data),
.in15(Channel[16*0+15].data),
.CLK(CLK200),
.load(state[loadslice]),
.active(state[hits0]),
.data(gruppe_0_data),
.skip(gruppe_0_skip),
.more(gruppe_0_more));
subgroup2x8 subgroup_1 (
.in00(Channel[16*1+ 0].data),
.in01(Channel[16*1+ 1].data),
.in02(Channel[16*1+ 2].data),
.in03(Channel[16*1+ 3].data),
.in04(Channel[16*1+ 4].data),
.in05(Channel[16*1+ 5].data),
.in06(Channel[16*1+ 6].data),
.in07(Channel[16*1+ 7].data),
.in08(Channel[16*1+ 8].data),
.in09(Channel[16*1+ 9].data),
.in10(Channel[16*1+10].data),
.in11(Channel[16*1+11].data),
.in12(Channel[16*1+12].data),
.in13(Channel[16*1+13].data),
.in14(Channel[16*1+14].data),
.in15(Channel[16*1+15].data),
.CLK(CLK200),
.load(state[loadslice]),
.active(state[hits1]),
.data(gruppe_1_data),
.skip(gruppe_1_skip),
.more(gruppe_1_more));
subgroup2x8 subgroup_2 (
.in00(Channel[16*2+ 0].data),
.in01(Channel[16*2+ 1].data),
.in02(Channel[16*2+ 2].data),
.in03(Channel[16*2+ 3].data),
.in04(Channel[16*2+ 4].data),
.in05(Channel[16*2+ 5].data),
.in06(Channel[16*2+ 6].data),
.in07(Channel[16*2+ 7].data),
.in08(Channel[16*2+ 8].data),
.in09(Channel[16*2+ 9].data),
.in10(Channel[16*2+10].data),
.in11(Channel[16*2+11].data),
.in12(Channel[16*2+12].data),
.in13(Channel[16*2+13].data),
.in14(Channel[16*2+14].data),
.in15(Channel[16*2+15].data),
.CLK(CLK200),
.load(state[loadslice]),
.active(state[hits2]),
.data(gruppe_2_data),
.skip(gruppe_2_skip),
.more(gruppe_2_more));
subgroup2x8 subgroup_3 (
.in00(Channel[16*3+ 0].data),
.in01(Channel[16*3+ 1].data),
.in02(Channel[16*3+ 2].data),
.in03(Channel[16*3+ 3].data),
.in04(Channel[16*3+ 4].data),
.in05(Channel[16*3+ 5].data),
.in06(Channel[16*3+ 6].data),
.in07(Channel[16*3+ 7].data),
.in08(Channel[16*3+ 8].data),
.in09(Channel[16*3+ 9].data),
.in10(Channel[16*3+10].data),
.in11(Channel[16*3+11].data),
.in12(Channel[16*3+12].data),
.in13(Channel[16*3+13].data),
.in14(Channel[16*3+14].data),
.in15(Channel[16*3+15].data),
.CLK(CLK200),
.load(state[loadslice]),
.active(state[hits3]),
.data(gruppe_3_data),
.skip(gruppe_3_skip),
.more(gruppe_3_more));
subgroup2x8 subgroup_4 (
.in00(Channel[16*4+ 0].data),
.in01(Channel[16*4+ 1].data),
.in02(Channel[16*4+ 2].data),
.in03(Channel[16*4+ 3].data),
.in04(Channel[16*4+ 4].data),
.in05(Channel[16*4+ 5].data),
.in06(Channel[16*4+ 6].data),
.in07(Channel[16*4+ 7].data),
.in08(Channel[16*4+ 8].data),
.in09(Channel[16*4+ 9].data),
.in10(Channel[16*4+10].data),
.in11(Channel[16*4+11].data),
.in12(Channel[16*4+12].data),
.in13(Channel[16*4+13].data),
.in14(Channel[16*4+14].data),
.in15(Channel[16*4+15].data),
.CLK(CLK200),
.load(state[loadslice]),
.active(state[hits4]),
.data(gruppe_4_data),
.skip(gruppe_4_skip),
.more(gruppe_4_more));
subgroup2x8 subgroup_5 (
.in00(Channel[16*5+ 0].data),
.in01(Channel[16*5+ 1].data),
.in02(Channel[16*5+ 2].data),
.in03(Channel[16*5+ 3].data),
.in04(Channel[16*5+ 4].data),
.in05(Channel[16*5+ 5].data),
.in06(Channel[16*5+ 6].data),
.in07(Channel[16*5+ 7].data),
.in08(Channel[16*5+ 8].data),
.in09(Channel[16*5+ 9].data),
.in10(Channel[16*5+10].data),
.in11(Channel[16*5+11].data),
.in12(Channel[16*5+12].data),
.in13(Channel[16*5+13].data),
.in14(Channel[16*5+14].data),
.in15(Channel[16*5+15].data),
.CLK(CLK200),
.load(state[loadslice]),
.active(state[hits5]),
.data(gruppe_5_data),
.skip(gruppe_5_skip),
.more(gruppe_5_more));
subgroup2x8 subgroup_6 (
.in00(Channel[16*6+ 0].data),
.in01(Channel[16*6+ 1].data),
.in02(Channel[16*6+ 2].data),
.in03(Channel[16*6+ 3].data),
.in04(16'b0),
.in05(16'b0),
.in06(16'b0),
.in07(16'b0),
.in08(16'b0),
.in09(16'b0),
.in10(16'b0),
.in11(16'b0),
.in12(16'b0),
.in13(16'b0),
.in14(16'b0),
.in15(16'b0),
.CLK(CLK200),
.load(state[loadslice]),
.active(state[hits6]),
.data(gruppe_6_data),
.skip(gruppe_6_skip),
.more(gruppe_6_more));
//-----------------------------------------------------------------------------
//-- Process tdc_trigger_request ----------------------------------------------
//-----------------------------------------------------------------------------
localparam old_tdc_data_ignored=2, data_fifo_overflow=1, trigger_during_busy=0;
reg [31:0] fifo_write;
reg [31:0] fifo_count;
reg [3:0] fifo_errors;
reg [15:0] fifo_input_header1;
reg [15:0] fifo_input_header2;
reg [15:0] fifo_input_slice;
reg [15:0] fifo_input_hits0;
reg [15:0] fifo_input_hits1;
reg [15:0] fifo_input_hits2;
reg [15:0] fifo_input_hits3;
reg [15:0] fifo_input_hits4;
reg [15:0] fifo_input_hits5;
reg [15:0] fifo_input_hits6;
reg [15:0] fifo_input_filler;
reg [15:0] fifo_input_trailer;
wire not_enough_space_for_a_slice;
reg [31:0] event_fifo_input;
reg event_fifo_write;
wire event_fifo_full;
reg [7:0] tdc_slicecounts_stop;
reg toggle;
reg tbit;
reg [31:0] latched_evententriescounts;
reg eventsize_too_big;
reg [31:0] tdc_first_clockcounter;
reg [31:0] tdc_this_clockcounter;
wire [31:0] multicycle_calculation_of_diff;
wire tdc_data_too_old;
assign multicycle_calculation_of_diff = tdc_first_clockcounter - tdc_this_clockcounter;
assign tdc_data_too_old = ((tdc_first_clockcounter - tdc_this_clockcounter) > clock_limit) ? 1'b1 : 1'b0;
wire more_slices_to_come;
assign more_slices_to_come = (tdc_slicecounts_current[8:0]>{1'b0,tdc_slicecounts_stop[7:0]}) ? 1'b0 : 1'b1;
always@(posedge CLK200)
begin
//defaults
event_fifo_input <= 32'b0;
event_fifo_write <= 1'b0;
reset_evententriescounts <= 1'b0;
tdc_trigger_request_sync <= 1'b0;
tdc_valid_trigger <= 1'b0;
tdc_readnext <= 1'b0;
state <= 'b0;
fifo_write <= 'b0;
fifo_count <= 'b0;
//this FSM is not allowed to create a MUX for FIFO_input,
//we want to have control and do it ourselves
fifo_input_header1 <= {3'b110,13'b0_0000_0000_0000};
fifo_input_header2 <= {3'b111,geoid[4:0],iBIT[7:0]};
fifo_input_slice <= {3'b100,multicycle_calculation_of_diff[12:0]};
fifo_input_hits0 <= {1'b0,gruppe_0_data[14:0]};
fifo_input_hits1 <= {1'b0,gruppe_1_data[14:0]};
fifo_input_hits2 <= {1'b0,gruppe_2_data[14:0]};
fifo_input_hits3 <= {1'b0,gruppe_3_data[14:0]};
fifo_input_hits4 <= {1'b0,gruppe_4_data[14:0]};
fifo_input_hits5 <= {1'b0,gruppe_5_data[14:0]};
fifo_input_hits6 <= {1'b0,gruppe_6_data[14:0]};
fifo_input_filler <= {4'b1011,12'b0000_0000_0000};
fifo_input_trailer <= {4'b1010,fifo_errors,eventcounts[7:0]};
//we ignore the lowest bit, since the readout is 32bit wide and only half as deep
event_fifo_input <= {eventcounts[15:0],3'b0,final_evententriescounts[13:1]};
//-- a trigger request can only be processed if the fifo is in state idle,
//-- otherwise it is an error
if (tdc_trigger_request == 1'b1 && tdc_trigger_request_sync == 1'b0)
begin
tdc_trigger_request_sync <= 1'b1;
if (state[idle] == 1'b1)
begin
//stuff that needs to be ressetted on each trigger
fifo_errors[trigger_during_busy] <= 1'b0;
tdc_valid_trigger <= 1'b1;
end
else fifo_errors[trigger_during_busy] <= 1'b1;
end
//analyse evententries
//capture evententriescounts every other clk for multi cycle calculation, we do not care if +/- 1
tbit <= ~tbit;
toggle <= tbit;
if (toggle == 1'b1)
begin
if (latched_evententriescounts<max_event_size) eventsize_too_big <= 1'b0;
else eventsize_too_big <= 1'b1;
latched_evententriescounts <= evententriescounts;
end
//forcing one-hot-encoding with exclusive(parallel) states
if (tdc_reset == 1'b1)
begin
state[reset] <= 1'b1;
end else
case (1'b1) //synthesis full_case parallel_case
state[reset] : begin
//while tdc_reset is asserted, we do not get here
//tdc_trigger_request_sync causes the BRAM to update its last read pointer
tdc_trigger_request_sync <= 1'b1;
state[idle] <= 1'b1;
end
state[idle] : if (tdc_valid_trigger == 1'b1) state[prepare] <= 1'b1;
else state[idle] <= 1'b1;
state[prepare] : begin
fifo_errors[data_fifo_overflow] <= 1'b0;
fifo_errors[old_tdc_data_ignored] <= 1'b0;
tdc_slicecounts_stop <= data_size;
state[fifocheck1] <= 1'b1;
end
state[fifocheck1] : if (not_enough_space_for_a_slice == 1'b0)
begin
state[header1] <= 1'b1;
fifo_count[trailer] <= 1'b1; //see explanation in state filler
end
else state[fifocheck1] <= 1'b1;
state[header1] : begin
fifo_write[header1] <= 1'b1;
state[header2] <= 1'b1;
end
state[header2] : begin
fifo_write[header2] <= 1'b1;
state[w4data] <= 1'b1;
end
state[w4data] : begin
state[loadslice] <= 1'b1;
fifo_count[filler] <= 1'b1; //see explanation is state filler
tdc_first_clockcounter <= tdc_clkout;
end
state[loadslice] : begin
//tdc_out (coming from BRAM and going through all manipulations/sorting)
//is valid now and contains the next/first slice
//it is stored by questioning this state, so it is now safe to shift the
//readpointer of the BRAM
tdc_readnext <= 1'b1;
//the information of tdc_this_clockcounter will be used in slicetrailer
tdc_this_clockcounter <= tdc_clkout;
state[fifocheck2] <= 1'b1;
end
//this state is also needed to load the groups
state[fifocheck2] : if (not_enough_space_for_a_slice == 1'b0) state[hits0] <= 1'b1;
else state[fifocheck2] <= 1'b1;
state[hits0] : begin
fifo_write[hits0] <= gruppe_0_data[15];
if (gruppe_0_more == 1'b1) state[hits0] <= 1'b1; else
//if (gruppe_1_skip == 1'b1) state[hits2] <= 1'b1; else
state[hits1] <= 1'b1;
end
state[hits1] : begin
fifo_write[hits1] <= gruppe_1_data[15];
if (gruppe_1_more == 1'b1) state[hits1] <= 1'b1; else
//if (gruppe_2_skip == 1'b1) state[hits3] <= 1'b1; else
state[hits2] <= 1'b1;
end
state[hits2] : begin
fifo_write[hits2] <= gruppe_2_data[15];
if (gruppe_2_more == 1'b1) state[hits2] <= 1'b1; else
//if (gruppe_3_skip == 1'b1) state[hits4] <= 1'b1; else
state[hits3] <= 1'b1;
end
state[hits3] : begin
fifo_write[hits3] <= gruppe_3_data[15];
if (gruppe_3_more == 1'b1) state[hits3] <= 1'b1; else
//if (gruppe_4_skip == 1'b1) state[hits5] <= 1'b1; else
state[hits4] <= 1'b1;
end
state[hits4] : begin
fifo_write[hits4] <= gruppe_4_data[15];
if (gruppe_4_more == 1'b1) state[hits4] <= 1'b1; else
//if (gruppe_5_skip == 1'b1) state[hits6] <= 1'b1; else
state[hits5] <= 1'b1;
end
state[hits5] : begin
fifo_write[hits5] <= gruppe_5_data[15];
if (gruppe_5_more == 1'b1) state[hits5] <= 1'b1; else
//if (gruppe_6_skip == 1'b1) state[slicetrailer] <= 1'b1; else
state[hits6] <= 1'b1;
end
state[hits6] : begin
fifo_write[hits6] <= gruppe_6_data[15];
if (gruppe_6_more == 1'b1) state[hits6] <= 1'b1; else
state[slicetrailer] <= 1'b1;
end
state[slicetrailer] : begin
//tdc_data_too_old and calculation_of_diff
//is a multicycle_calculation based on this_clockcounter
//which was updated during sliceload
//more_slices_to_come is based on tdc_slicecounts_current
//which is updated during sliceload (see counter at bottom)
//we always write this slicetrailer
fifo_write[slicetrailer] <= 1'b1;
//now what?
if (eventsize_too_big == 1'b1 || tdc_data_too_old == 1'b1 || more_slices_to_come == 1'b0)
begin
state[w4filler1] <= 1'b1;
end else
begin
state[loadslice] <= 1'b1;
end
if (eventsize_too_big == 1'b1) fifo_errors[data_fifo_overflow] <= 1'b1;
if (tdc_data_too_old == 1'b1) fifo_errors[old_tdc_data_ignored] <= 1'b1;
end
state[w4filler1] : state[w4filler2] <= 1'b1; //wait till evententriescounts is updated
state[w4filler2] : state[w4filler3] <= 1'b1; //wait till evententriescounts is updated
state[w4filler3] : state[w4filler4] <= 1'b1; //wait till evententriescounts is updated
state[w4filler4] : state[filler] <= 1'b1; //wait till evententriescounts is updated
state[filler] : begin
//store the current evententriescounts value and calculate final evententriescounts
//depending upon count we need to add one or two (filler + trailer)
//trick: We added two extra counts in state w4data2 and idle and do not have to do anything now! Why?
// Since we only need half of the evententriescounts, we can ignore the lowest bit,
// thus TWO possible values of finalcount will be "right": (5 = 10>>1 or 11>>1)
// stored events: 10 -> real events: 8 -> filler needed: yes -> final eventcount: 10/2 = 5 ==!== stored events >> 1
// stored events: 11 -> real events: 9 -> filler needed: no -> final eventcount: 10/2 = 5 ==!== stored events >> 1
// stored events: 12 -> real events:10 -> filler needed: yes -> final eventcount: 12/2 = 6 ==!== stored events >> 1
// stored events: 13 -> real events:11 -> filler needed: no -> final eventcount: 12/2 = 6 ==!== stored events >> 1
final_evententriescounts <= evententriescounts;
if (evententriescounts[0] == 1'b0) fifo_write[filler] <= 1'b1;
state[trailer] <= 1'b1;
//due to w4filler, there is no count in the pipeline anymore
//we do not need to count filler and trailer -> pipeline remains empty
//so the reset is fine (it is not piped)
end
state[trailer] : begin
fifo_write[trailer] <= 1'b1;
state[finish] <= 1'b1;
end
state[finish] : if (event_fifo_full == 1'b0)
begin
reset_evententriescounts <= 1'b1;
event_fifo_write <= 1'b1;
state[idle] <= 1'b1;
end
else state[finish] <= 1'b1;
endcase
end
//-----------------------------------------------------------------------------
//-- Generate data_fifo_input Data From Individual States Data ----------------
//-----------------------------------------------------------------------------
wire [15:0] fifo_data_11; wire fifo_select_11; wire fifo_counts_11;
wire [15:0] fifo_data_12; wire fifo_select_12; wire fifo_counts_12;
wire [15:0] fifo_data_13; wire fifo_select_13; wire fifo_counts_13;
wire [15:0] fifo_data_14; wire fifo_select_14; wire fifo_counts_14;
wire [15:0] fifo_data_15; wire fifo_select_15; wire fifo_counts_15;
wire [15:0] fifo_data_16; wire fifo_select_16; wire fifo_counts_16;
wire [15:0] fifo_data_21; wire fifo_select_21; wire fifo_counts_21;
wire [15:0] fifo_data_22; wire fifo_select_22; wire fifo_counts_22;
wire [15:0] fifo_data_23; wire fifo_select_23; wire fifo_counts_23;
//first pipe
select_if_active_LUT select_11 (.s1(fifo_write[header1]) ,.s2(fifo_write[hits6]),
.c1(fifo_write[header1]) ,.c2(fifo_write[hits6]),
.d1(fifo_input_header1) ,.d2(fifo_input_hits6),
.od(fifo_data_11),
.os(fifo_select_11),
.oc(fifo_counts_11),
.CLK(CLK200));
select_if_active_LUT select_12 (.s1(fifo_write[header2]) ,.s2(fifo_write[hits5]),
.c1(fifo_write[header2]) ,.c2(fifo_write[hits5]),
.d1(fifo_input_header2) ,.d2(fifo_input_hits5),
.od(fifo_data_12),
.os(fifo_select_12),
.oc(fifo_counts_12),
.CLK(CLK200));
select_if_active_LUT select_13 (.s1(fifo_write[slicetrailer]) ,.s2(fifo_write[hits4]),
.c1(fifo_write[slicetrailer]) ,.c2(fifo_write[hits4]),
.d1(fifo_input_slice) ,.d2(fifo_input_hits4),
.od(fifo_data_13),
.os(fifo_select_13),
.oc(fifo_counts_13),
.CLK(CLK200));
select_if_active_LUT select_14 (.s1(fifo_write[trailer]) ,.s2(fifo_write[hits3]),
.c1(fifo_count[trailer]) ,.c2(fifo_write[hits3]),
.d1(fifo_input_trailer) ,.d2(fifo_input_hits3),
.od(fifo_data_14),
.os(fifo_select_14),
.oc(fifo_counts_14),
.CLK(CLK200));
select_if_active_LUT select_15 (.s1(fifo_write[filler]) ,.s2(fifo_write[hits2]),
.c1(fifo_count[filler]) ,.c2(fifo_write[hits2]),
.d1(fifo_input_filler) ,.d2(fifo_input_hits2),
.od(fifo_data_15),
.os(fifo_select_15),
.oc(fifo_counts_15),
.CLK(CLK200));
select_if_active_LUT select_16 (.s1(fifo_write[hits0]) ,.s2(fifo_write[hits1]),
.c1(fifo_write[hits0]) ,.c2(fifo_write[hits1]),
.d1(fifo_input_hits0) ,.d2(fifo_input_hits1),
.od(fifo_data_16),
.os(fifo_select_16),
.oc(fifo_counts_16),
.CLK(CLK200));
//-- second pipe
select_if_active_LUT select_21 (.s1(fifo_select_11) ,.s2(fifo_select_12),
.c1(fifo_counts_11) ,.c2(fifo_counts_12),
.d1(fifo_data_11) ,.d2(fifo_data_12),
.od(fifo_data_21),
.os(fifo_select_21),
.oc(fifo_counts_21),
.CLK(CLK200));
select_if_active_LUT select_22 (.s1(fifo_select_13) ,.s2(fifo_select_14),
.c1(fifo_counts_13) ,.c2(fifo_counts_14),
.d1(fifo_data_13) ,.d2(fifo_data_14),
.od(fifo_data_22),
.os(fifo_select_22),
.oc(fifo_counts_22),
.CLK(CLK200));
select_if_active_LUT select_23 (.s1(fifo_select_15) ,.s2(fifo_select_16),
.c1(fifo_counts_15) ,.c2(fifo_counts_16),
.d1(fifo_data_15) ,.d2(fifo_data_16),
.od(fifo_data_23),
.os(fifo_select_23),
.oc(fifo_counts_23),
.CLK(CLK200));
//-- third pipe
reg [15:0] data_fifo_input;
reg data_fifo_write;
reg data_fifo_count;
(* KEEP = "true" *) reg [15:0] data_fifo_input_buffer;
(* KEEP = "true" *) reg data_fifo_write_buffer;
always@(posedge CLK200)
begin
data_fifo_count <= (fifo_counts_21 || fifo_counts_22 || fifo_counts_23);
data_fifo_input_buffer <= (fifo_data_21 | fifo_data_22 | fifo_data_23);
data_fifo_write_buffer <= (fifo_select_21 || fifo_select_22 || fifo_select_23);
data_fifo_input <= data_fifo_input_buffer;
data_fifo_write <= data_fifo_write_buffer;
end
//-----------------------------------------------------------------------------
//-- Data FIFO ----------------------------------------------------------------
//-----------------------------------------------------------------------------
wire [31:0] transform_data_fifo_output;
wire transform_data_fifo_read;
wire transform_data_fifo_valid;
wire [31:0] internalevent_fifo_output;
wire internalevent_fifo_read;
wire internalevent_fifo_empty;
wire [31:0] data_fifo_output;
wire data_fifo_read;
wire data_fifo_valid;
//this fifo is used to get from 200Mhz to 100Mhz, and from 16bit to 32bit
data_fifo_16 transform_data_fifo (
.rst(tdc_reset),
.wr_clk(CLK200),
.rd_clk(CLKBUS),
.din(data_fifo_input), // input [15 : 0] din
.wr_en(data_fifo_write), // input wr_en
.rd_en(transform_data_fifo_read), // input rd_en
.dout(transform_data_fifo_output), // output [31 : 0] dout
.prog_full(not_enough_space_for_a_slice),
.valid(transform_data_fifo_valid)
);
//now we auto-empty the transform-fifo and put it into a large BRAM FIFO STACK
//if valid, there has been a sucessfull read request (all at 100MHz)
generate
for (i=0; i <= fifocounts; i=i+1) begin : FifoStacks
wire fifo_full;
wire fifo_valid;
wire [31:0] fifo_output;
if (i == 0)
begin
assign transform_data_fifo_read = ~fifo_full;
assign fifo_output = transform_data_fifo_output;
assign fifo_valid = transform_data_fifo_valid;
end else begin
//this is a large BRAM FIFO @100Mhz with 32Bit width (standard fifo)
data_fifo_big data_fifo_storage (
.srst(tdc_reset),
.clk(CLKBUS),
.din(FifoStacks[i-1].fifo_output),
.wr_en(FifoStacks[i-1].fifo_valid),
.rd_en(~fifo_full),
.dout(fifo_output),
.almost_full(FifoStacks[i-1].fifo_full), //output signal
.valid(fifo_valid)
);
end
end
endgenerate
assign FifoStacks[fifocounts].fifo_full = ~data_fifo_read;
assign data_fifo_output = FifoStacks[fifocounts].fifo_output;
assign data_fifo_valid = FifoStacks[fifocounts].fifo_valid;
//auto poll data fifo
wire [31:0] data_fifo_value_before_manipulation;
standard_fifo_poll DATA_FIFO_POLL (
.readrequest(data_fifo_readrequest),
.CLK(CLKBUS),
.fifo_data(data_fifo_output),
.fifo_read(data_fifo_read),
.fifo_valid(data_fifo_valid),
.reset(tdc_reset),
.fifo_value(data_fifo_value_before_manipulation));
//catch and manipulate header1 before sending it to databus
wire [31:0] data_fifo_value_after_manipulation;
assign data_fifo_value_after_manipulation[15:0] = data_fifo_value_before_manipulation[15:0];
assign data_fifo_value_after_manipulation[31:16] = (data_fifo_value_before_manipulation[31:29] == 3'b110) ? {3'b110,internalevent_fifo_output[12:0]} : data_fifo_value_before_manipulation[31:16];
assign data_fifo_value = {data_fifo_value_after_manipulation[15:0],data_fifo_value_after_manipulation[31:16]}; //endian hack
//the info is no longer needed -> remove from internal_event_fifo after trailer is read from data_fifo
wire test = (data_fifo_value_before_manipulation[31:29] == 3'b110) ? 1'b0 : 1'b1;
signal_clipper clip_read_internal_fifo (.sig(test), .CLK(CLKBUS), .clipped_sig(internalevent_fifo_read));
//-----------------------------------------------------------------------------
//-- Event FIFO ---------------------------------------------------------------
//-----------------------------------------------------------------------------
wire [31:0] event_fifo_output;
wire event_fifo_valid;
wire event_fifo_read;
event_fifo_32 event_fifo (
.rst(tdc_reset),
.wr_clk(CLK200),
.rd_clk(CLKBUS),
.din(event_fifo_input),
.wr_en(event_fifo_write),
.rd_en(event_fifo_read),
.dout(event_fifo_output),
.full(),
.valid(event_fifo_valid)
);
standard_fifo_poll EVENT_FIFO_POLL (
.readrequest(event_fifo_readrequest),
.CLK(CLKBUS),
.fifo_data(event_fifo_output),
.fifo_read(event_fifo_read),
.fifo_valid(event_fifo_valid),
.reset(tdc_reset),
.fifo_value(event_fifo_value));
//this fifo stores everything that is stored in the real event_fifo, and is used to manipulate header1 entries during read out
event_fifo_32_FWFT internalevent_fifo (
.rst(tdc_reset),
.wr_clk(CLK200),
.rd_clk(CLKBUS),
.din(event_fifo_input),
.wr_en(event_fifo_write),
.rd_en(internalevent_fifo_read),
.dout(internalevent_fifo_output),
.empty(internalevent_fifo_empty),
.prog_full(event_fifo_full)
);
//-----------------------------------------------------------------------------
//-- Internal Counter ---------------------------------------------------------
//-----------------------------------------------------------------------------
slimfast_multioption_counter #(.clip_count(0)) CLOCK_COUNTER (
.countClock(CLK200),
.count(1'b1),
.reset(tdc_reset || reset_clockcounter),
.countout(clkcounts));
slimfast_multioption_counter #(.clip_count(0)) TOTAL_EVENT_COUNTER (
.countClock(CLK200),
.count(tdc_valid_trigger),
.reset(tdc_reset),
.countout(eventcounts));
slimfast_multioption_counter #(.clip_count(0)) EVENT_ENTRIES_COUNTER (
.countClock(CLK200),
.count(data_fifo_count),
.reset(reset_evententriescounts || tdc_reset),
.countout(evententriescounts));
slimfast_multioption_counter #(.clip_count(0)) SLICE_COUNTER (
.countClock(CLK200),
.count(state[loadslice]),
.reset(state[prepare]),
.countout(tdc_slicecounts));
always@(posedge CLK200)
begin
tdc_slicecounts_current <= tdc_slicecounts[8:0];
end
endmodule |
module dpram
#( parameter MEMD = 16, // memory depth
parameter DATW = 32, // data width
parameter ZERO = 0 , // binary / Initial RAM with zeros (has priority over FILE)
parameter FILE = "" // initialization hex file (don't pass extension), optional
)( input clk , // clock
input WEnb_A , // write enable for port A
input WEnb_B , // write enable for port B
input [`log2(MEMD)-1:0] Addr_A , // address for port A
input [`log2(MEMD)-1:0] Addr_B , // address for port B
input [DATW -1:0] WData_A, // write data for port A
input [DATW -1:0] WData_B, // write data for port B
output reg [DATW -1:0] RData_A, // read data for port A
output reg [DATW -1:0] RData_B // read data for port B
);
// initialize RAM, with zeros if ZERO or file if FILE.
integer i;
reg [DATW-1:0] mem [0:MEMD-1]; // memory array
initial
if (ZERO)
for (i=0; i<MEMD; i=i+1) mem[i] = {DATW{1'b0}};
else
if (FILE != "") $readmemh({FILE,".hex"}, mem);
// PORT A
always @(posedge clk) begin
// write/read; nonblocking statement to read old data
if (WEnb_A) begin
mem[Addr_A] <= WData_A; // Change into blocking statement (=) to read new data
RData_A <= WData_A; // flow-through
end else
RData_A <= mem[Addr_A]; //Change into blocking statement (=) to read new data
end
// PORT B
always @(posedge clk) begin
// write/read; nonblocking statement to read old data
if (WEnb_B) begin
mem[Addr_B] <= WData_B; // Change into blocking statement (=) to read new data
RData_B <= WData_B; // flow-through
end else
RData_B <= mem[Addr_B]; //Change into blocking statement (=) to read new data
end
endmodule |
module velocityControlHdl_Double_Range
(
In1_0,
In1_1,
In1_2,
Out1_0,
Out1_1,
Out1_2
);
input signed [17:0] In1_0; // sfix18_En13
input signed [17:0] In1_1; // sfix18_En13
input signed [17:0] In1_2; // sfix18_En13
output signed [17:0] Out1_0; // sfix18_En12
output signed [17:0] Out1_1; // sfix18_En12
output signed [17:0] Out1_2; // sfix18_En12
wire signed [17:0] In1 [0:2]; // sfix18_En13 [3]
wire signed [17:0] Data_Type_Conversion_out1 [0:2]; // sfix18_En12 [3]
assign In1[0] = In1_0;
assign In1[1] = In1_1;
assign In1[2] = In1_2;
// <S40>/Data Type Conversion
assign Data_Type_Conversion_out1[0] = {In1[0][17], In1[0][17:1]};
assign Data_Type_Conversion_out1[1] = {In1[1][17], In1[1][17:1]};
assign Data_Type_Conversion_out1[2] = {In1[2][17], In1[2][17:1]};
assign Out1_0 = Data_Type_Conversion_out1[0];
assign Out1_1 = Data_Type_Conversion_out1[1];
assign Out1_2 = Data_Type_Conversion_out1[2];
endmodule |
module sky130_fd_sc_hdll__nor2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module Key
( input clk,
input rst,
input left,
input right,
input up,
input down,
output reg[7:0] direction
);
reg [31:0]clk_cnt;
reg left_key_last;
reg right_key_last;
reg up_key_last;
reg down_key_last;
always@(posedge clk or negedge rst) begin
if(!rst) begin
clk_cnt <= 0;
direction <= 8'b0;
left_key_last <= 0;
right_key_last <= 0;
up_key_last <= 0;
down_key_last <= 0;
end
else begin
if(clk_cnt == 5_0000) begin
clk_cnt <= 0;
left_key_last <= left;
right_key_last <= right;
up_key_last <= up;
down_key_last <= down;
if(left_key_last == 0 && left == 1)
direction <= 8'b0000_0001;
if(right_key_last == 0 && right == 1)
direction <= 8'b0000_0010;
if(up_key_last == 0 && up == 1)
direction <= 8'b0000_0011;
if(down_key_last == 0 && down == 1)
direction <= 8'b0000_0100;
end
else begin
clk_cnt <= clk_cnt + 1;
direction <= 8'b0000_0000;
end
end
end
endmodule |
module Decode(
clk_i,
rst_i,
gbl_stl_i,
jmp_rqst_i,
wait_to_fill_pipe_i,
wait_sig_i,
p_i,
pc_i,
fetched_ops_i,
mem_stl_i,
wait_sig_o,
pc_o,
operand_o,
control_signal_o
`ifdef DEBUG
,debug_o
`endif
);
//Input signals :
input wire clk_i;
input wire rst_i;
input wire gbl_stl_i;
input wire jmp_rqst_i;
input wire wait_to_fill_pipe_i;
input wire [1:0] wait_sig_i;
input wire [7:0] p_i;
input wire [15:0] pc_i;
input wire [23:0] fetched_ops_i;
input wire mem_stl_i;
//Output signals :
output wire [1:0] wait_sig_o;
output wire [15:0] pc_o;
output wire [15:0] operand_o;
output wire [`decode_cntrl_o_width - 1:0] control_signal_o;
`ifdef DEBUG
output wire [`DEC_DBG_WIDTH - 1:0] debug_o;
`endif
//Internal registers:
reg [1:0] wait_sig_reg;
reg [1:0] used_byte_cnt_reg;
reg [15:0] pc_reg;
reg [15:0] operand_reg;
reg [`decode_cntrl_o_width - 1:0] control_signal_reg;
reg [2:0] history_inst_flag;
reg [5:0] history_inst_dest;
reg [23:0] inst_temp_reg;
//Assignments :
assign wait_sig_o = wait_sig_reg;
assign pc_o = pc_reg;
assign operand_o = operand_reg;
assign control_signal_o = control_signal_reg;
`ifdef DEBUG
assign debug_o = inst_temp_reg;
`endif
//Blocks :
always @(posedge clk_i)
begin
if(rst_i == 1'h1)
begin
wait_sig_reg <= 2'h0;
operand_reg <= 16'h0;
used_byte_cnt_reg <= 2'h0;
control_signal_reg <= `decode_cntrl_o_width'h0;
inst_temp_reg <= {3{`NOTHING}};
history_inst_flag <= {3{`nef_flags}};
history_inst_dest <= {3{`wb_dest_none}};
end
else if(gbl_stl_i == 1'h1 || mem_stl_i == 1'h1)
begin
end
else if(wait_sig_i - 2'h1 != 2'h3)
begin
used_byte_cnt_reg <= 2'h0;
history_inst_flag <= {`nef_flags, `history_flag_2, `history_flag_1};
history_inst_dest <= {`wb_dest_none, `history_dest_2, `history_dest_1};
end
else if(wait_sig_reg != 2'h0)
begin
wait_sig_reg <= wait_sig_reg - 2'h1;
used_byte_cnt_reg <= 2'h0;
history_inst_flag <= {`history_flag_2, `nef_flags, `history_flag_1};
history_inst_dest <= {`history_dest_2, `wb_dest_none, `history_dest_1};
end
else if(wait_to_fill_pipe_i == 1'h1 || jmp_rqst_i == 1'h1)
begin
inst_temp_reg <= fetched_ops_i;
end
else
begin
case(`cur_inst)
//Decode instructions ... :
//////////////////////////////////////////////////////////////////////////////////////////
// //
// ADC //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`ADC_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ADD;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ADC_ABS_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ADD;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ADC_ABS_Y : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_y)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_y)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_y)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_Y;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ADD;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ADC_IME : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IME;
`cntrl_exe_op_reg <= `ALU_ADD;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ADC_I_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_INDIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ADD;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ADC_I_Y : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
if(`history_dest_1 == `wb_dest_reg_y)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_y)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_y)
begin
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_2_reg <= `ADR_OFF_Y;
end
`cntrl_ea_adr_mod_reg <= `MOD_INDIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ADD;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ADC_ZP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ADD;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ADC_ZP_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ADD;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// AND //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`AND_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_AND;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`AND_ABS_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_AND;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`AND_ABS_Y : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_y)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_y)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_y)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_Y;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_AND;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`AND_IME : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IME;
`cntrl_exe_op_reg <= `ALU_AND;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`AND_I_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_INDIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_AND;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`AND_I_Y : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
if(`history_dest_1 == `wb_dest_reg_y)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_y)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_y)
begin
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_2_reg <= `ADR_OFF_Y;
end
`cntrl_ea_adr_mod_reg <= `MOD_INDIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_AND;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`AND_ZP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_AND;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`AND_ZP_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_AND;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// ASL //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`ASL_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_SHL;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ASL_ABS_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_SHL;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ASL_ACU : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_SHL;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ASL_ZP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_SHL;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ASL_ZP_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_SHL;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// BRANCHES //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`BCC : begin
if(`history_flag_1 == `wef_flags)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
used_byte_cnt_reg <= 2'h0;
inst_temp_reg <= inst_temp_reg;
end
else if(`history_flag_2 == `wef_flags)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
used_byte_cnt_reg <= 2'h0;
inst_temp_reg <= inst_temp_reg;
end
else
begin
if(p_i[`C] == 1'h0)
begin
if(inst_temp_reg[15] == 1'h1)
begin
operand_reg <= (pc_i - 16'h6 + used_byte_cnt_reg) - {8'h0, (8'd128 - {1'h0, inst_temp_reg[14:8]})};
end
else
begin
operand_reg <= (pc_i - 16'h6 + used_byte_cnt_reg) - {8'h0, `inst_temp_2};
end
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= {3{`NOTHING}};
`cntrl_ea_pc_jmp_reg <= `JUMP_INST;
end
else
begin
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
end
end
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
//Step 2, Generate Control Signals :
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_NOP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DC;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_none};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`BCS : begin
if(`history_flag_1 == `wef_flags)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
used_byte_cnt_reg <= 2'h0;
inst_temp_reg <= inst_temp_reg;
end
else if(`history_flag_2 == `wef_flags)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
used_byte_cnt_reg <= 2'h0;
inst_temp_reg <= inst_temp_reg;
end
else
begin
if(p_i[`C] == 1'h1)
begin
if(inst_temp_reg[15] == 1'h1)
begin
operand_reg <= (pc_i - 16'h6 + used_byte_cnt_reg) - {8'h0, (8'd128 - {1'h0, inst_temp_reg[14:8]})};
end
else
begin
operand_reg <= (pc_i - 16'h6 + used_byte_cnt_reg) - {8'h0, `inst_temp_2};
end
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= {3{`NOTHING}};
`cntrl_ea_pc_jmp_reg <= `JUMP_INST;
end
else
begin
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
end
end
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
//Step 2, Generate Control Signals :
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_NOP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DC;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_none};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`BEQ : begin
if(`history_flag_1 == `wef_flags)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
used_byte_cnt_reg <= 2'h0;
inst_temp_reg <= inst_temp_reg;
end
else if(`history_flag_2 == `wef_flags)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
used_byte_cnt_reg <= 2'h0;
inst_temp_reg <= inst_temp_reg;
end
else
begin
if(p_i[`Z] == 1'h1)
begin
if(inst_temp_reg[15] == 1'h1)
begin
operand_reg <= (pc_i - 16'h6 + used_byte_cnt_reg) - {8'h0, (8'd128 - {1'h0, inst_temp_reg[14:8]})};
end
else
begin
operand_reg <= (pc_i - 16'h6 + used_byte_cnt_reg) - {8'h0, `inst_temp_2};
end
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= {3{`NOTHING}};
`cntrl_ea_pc_jmp_reg <= `JUMP_INST;
end
else
begin
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
end
end
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
//Step 2, Generate Control Signals :
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_NOP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DC;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_none};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`BIT_ABS : begin
end
`BIT_ZP : begin
end
`BMI : begin
if(`history_flag_1 == `wef_flags)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
used_byte_cnt_reg <= 2'h0;
inst_temp_reg <= inst_temp_reg;
end
else if(`history_flag_2 == `wef_flags)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
used_byte_cnt_reg <= 2'h0;
inst_temp_reg <= inst_temp_reg;
end
else
begin
if(p_i[`N] == 1'h1)
begin
if(inst_temp_reg[15] == 1'h1)
begin
operand_reg <= (pc_i - 16'h6 + used_byte_cnt_reg) - {8'h0, (8'd128 - {1'h0, inst_temp_reg[14:8]})};
end
else
begin
operand_reg <= (pc_i - 16'h6 + used_byte_cnt_reg) - {8'h0, `inst_temp_2};
end
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= {3{`NOTHING}};
`cntrl_ea_pc_jmp_reg <= `JUMP_INST;
end
else
begin
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
end
end
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
//Step 2, Generate Control Signals :
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_NOP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DC;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_none};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`BNE : begin
if(`history_flag_1 == `wef_flags)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
used_byte_cnt_reg <= 2'h0;
inst_temp_reg <= inst_temp_reg;
end
else if(`history_flag_2 == `wef_flags)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
used_byte_cnt_reg <= 2'h0;
inst_temp_reg <= inst_temp_reg;
end
else
begin
if(p_i[`Z] == 1'h0)
begin
if(inst_temp_reg[15] == 1'h1)
begin
operand_reg <= (pc_i - 16'h6 + used_byte_cnt_reg) - {8'h0, (8'd128 - {1'h0, inst_temp_reg[14:8]})};
end
else
begin
operand_reg <= (pc_i - 16'h6 + used_byte_cnt_reg) - {8'h0, `inst_temp_2};
end
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= {3{`NOTHING}};
`cntrl_ea_pc_jmp_reg <= `JUMP_INST;
end
else
begin
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
end
end
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
//Step 2, Generate Control Signals :
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_NOP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DC;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_none};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`BPL : begin
if(`history_flag_1 == `wef_flags)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
used_byte_cnt_reg <= 2'h0;
inst_temp_reg <= inst_temp_reg;
end
else if(`history_flag_2 == `wef_flags)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
used_byte_cnt_reg <= 2'h0;
inst_temp_reg <= inst_temp_reg;
end
else
begin
if(p_i[`N] == 1'h0)
begin
if(inst_temp_reg[15] == 1'h1)
begin
operand_reg <= (pc_i - 16'h6 + used_byte_cnt_reg) - {8'h0, (8'd128 - {1'h0, inst_temp_reg[14:8]})};
end
else
begin
operand_reg <= (pc_i - 16'h6 + used_byte_cnt_reg) - {8'h0, `inst_temp_2};
end
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= {3{`NOTHING}};
`cntrl_ea_pc_jmp_reg <= `JUMP_INST;
end
else
begin
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
end
end
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
//Step 2, Generate Control Signals :
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_NOP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DC;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_none};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`BRK : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`V_ADR_IRQ_H, `V_ADR_IRQ_L};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= {3{`NOTHING}};
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `JUMP_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_INDIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_P_PC_PUSH;
`cntrl_rd_src_reg <= `TYPE_IME;
`cntrl_exe_op_reg <= `ALU_BRK;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `THR;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`BVC : begin
if(`history_flag_1 == `wef_flags)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
used_byte_cnt_reg <= 2'h0;
inst_temp_reg <= inst_temp_reg;
end
else if(`history_flag_2 == `wef_flags)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
used_byte_cnt_reg <= 2'h0;
inst_temp_reg <= inst_temp_reg;
end
else
begin
if(p_i[`V] == 1'h0)
begin
if(inst_temp_reg[15] == 1'h1)
begin
operand_reg <= (pc_i - 16'h6 + used_byte_cnt_reg) - {8'h0, (8'd128 - {1'h0, inst_temp_reg[14:8]})};
end
else
begin
operand_reg <= (pc_i - 16'h6 + used_byte_cnt_reg) - {8'h0, `inst_temp_2};
end
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= {3{`NOTHING}};
`cntrl_ea_pc_jmp_reg <= `JUMP_INST;
end
else
begin
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
end
end
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
//Step 2, Generate Control Signals :
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_NOP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DC;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_none};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`BVS : begin
if(`history_flag_1 == `wef_flags)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
used_byte_cnt_reg <= 2'h0;
inst_temp_reg <= inst_temp_reg;
end
else if(`history_flag_2 == `wef_flags)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
used_byte_cnt_reg <= 2'h0;
inst_temp_reg <= inst_temp_reg;
end
else
begin
if(p_i[`V] == 1'h1)
begin
if(inst_temp_reg[15] == 1'h1)
begin
operand_reg <= (pc_i - 16'h6 + used_byte_cnt_reg) - {8'h0, (8'd128 - {1'h0, inst_temp_reg[14:8]})};
end
else
begin
operand_reg <= (pc_i - 16'h6 + used_byte_cnt_reg) - {8'h0, `inst_temp_2};
end
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= {3{`NOTHING}};
`cntrl_ea_pc_jmp_reg <= `JUMP_INST;
end
else
begin
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
end
end
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
//Step 2, Generate Control Signals :
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_NOP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DC;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_none};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// FLAGS CLEAR //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`CLC : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_CLC;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DC;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`CLD : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_CLD;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DC;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`CLI : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_CLI;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DC;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`CLV : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_CLV;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DC;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// CMP //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`CMP_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_CMP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`CMP_ABS_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_CMP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`CMP_ABS_Y : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_y)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_y)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_y)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_Y;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_CMP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`CMP_IME : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IME;
`cntrl_exe_op_reg <= `ALU_CMP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`CMP_I_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_INDIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_CMP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`CMP_I_Y : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
if(`history_dest_1 == `wb_dest_reg_y)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_y)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_y)
begin
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_2_reg <= `ADR_OFF_Y;
end
`cntrl_ea_adr_mod_reg <= `MOD_INDIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_CMP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`CMP_ZP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_CMP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`CMP_ZP_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_CMP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// CPX //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`CPX_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_CMP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_x)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_X;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`CPX_IME : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IME;
`cntrl_exe_op_reg <= `ALU_CMP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_x)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_X;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`CPX_ZP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_CMP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_x)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_X;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// CPY //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`CPY_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_CMP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_y)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_Y;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`CPY_IME : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IME;
`cntrl_exe_op_reg <= `ALU_CMP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_y)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_Y;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`CPY_ZP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_CMP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_y)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_Y;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// DECRIMENT //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`DEC_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_DEC;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`DEC_ABS_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_DEC;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`DEC_ZP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_DEC;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`DEC_ZP_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_DEC;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`DEX : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_DEC;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_x)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_X;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `ACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_x};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`DEY : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_DEC;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_y)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_Y;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `ACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_y};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// XOR //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`EOR_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_XOR;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`EOR_ABS_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_XOR;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`EOR_ABS_Y : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_y)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_y)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_y)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_Y;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_XOR;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`EOR_IME : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IME;
`cntrl_exe_op_reg <= `ALU_XOR;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`EOR_I_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_INDIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_XOR;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`EOR_I_Y : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
if(`history_dest_1 == `wb_dest_reg_y)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_y)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_y)
begin
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_2_reg <= `ADR_OFF_Y;
end
`cntrl_ea_adr_mod_reg <= `MOD_INDIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_XOR;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`EOR_ZP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_XOR;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`EOR_ZP_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_XOR;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// INCREMENT //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`INC_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_INC;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`INC_ABS_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_INC;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`INC_ZP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_INC;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`INC_ZP_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_INC;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`INX : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_INC;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_x)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_X;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `ACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_x};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`INY : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_INC;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_y)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_Y;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `ACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_y};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// JMP //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`JMP_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= {3{`NOTHING}};
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `JUMP_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_NOP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DC;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_none};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`JMP_I : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= {3{`NOTHING}};
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `JUMP_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_INDIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_NOP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DC;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_none};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// JSR //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`JSR : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= {3{`NOTHING}};
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `JUMP_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_PC_PUSH;
`cntrl_rd_src_reg <= `TYPE_IME;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `TWO;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// LDA //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`LDA_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`LDA_ABS_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`LDA_ABS_Y : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_y)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_y)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_y)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_Y;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`LDA_IME : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IME;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`LDA_I_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_INDIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`LDA_I_Y : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
if(`history_dest_1 == `wb_dest_reg_y)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_y)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_y)
begin
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_2_reg <= `ADR_OFF_Y;
end
`cntrl_ea_adr_mod_reg <= `MOD_INDIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`LDA_ZP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`LDA_ZP_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// LDX //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`LDX_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `ACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_x};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`LDX_ABS_Y : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_y)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_y)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_y)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_Y;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `ACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_x};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`LDX_IME : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IME;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `ACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_x};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`LDX_ZP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `ACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_x};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`LDX_ZP_Y : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_y)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_y)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_y)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_Y;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `ACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_x};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// LDY //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`LDY_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `ACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_y};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`LDY_ABS_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `ACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_y};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`LDY_IME : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IME;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `ACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_y};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`LDY_ZP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `ACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_y};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`LDY_ZP_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `ACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_y};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// LSR //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`LSR_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_SHR;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`LSR_ABS_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_SHR;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`LSR_ACU : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_SHR;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`LSR_ZP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_SHR;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`LSR_ZP_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_SHR;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// NOP //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`NOP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_NOP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DC;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// ORA //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`ORA_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ORA;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ORA_ABS_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ORA;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ORA_ABS_Y : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_y)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_y)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_y)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_Y;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ORA;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ORA_IME : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IME;
`cntrl_exe_op_reg <= `ALU_ORA;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ORA_I_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_INDIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ORA;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ORA_I_Y : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
if(`history_dest_1 == `wb_dest_reg_y)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_y)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_y)
begin
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_2_reg <= `ADR_OFF_Y;
end
`cntrl_ea_adr_mod_reg <= `MOD_INDIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ORA;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ORA_ZP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ORA;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ORA_ZP_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ORA;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// PUSH, POP //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`PHA : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `SP_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_PUSH;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`PHP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `SP_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_PUSH;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_P;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`PLA : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `SP_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_POP;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`PLP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `SP_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_POP;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITF;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// ROL //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`ROL_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ROL;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ROL_ABS_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ROL;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ROL_ACU : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_ROL;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ROL_ZP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ROL;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ROL_ZP_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ROL;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// ROR //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`ROR_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ROR;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ROR_ABS_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ROR;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ROR_ACU : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_ROR;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ROR_ZP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ROR;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`ROR_ZP_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ROR;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// RETURN ORIENTED //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`RTI : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= {3{`NOTHING}};
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `JUMP_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_INDIR;
`cntrl_ea_adr_src_reg <= `SP_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_P_PC_POP;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITF;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_none};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`RTS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= {3{`NOTHING}};
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `JUMP_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_INDIR;
`cntrl_ea_adr_src_reg <= `SP_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_PC_POP;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_NOP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DC;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_none};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// SBC //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`SBC_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_SUB;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`SBC_ABS_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_SUB;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`SBC_ABS_Y : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_y)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_y)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_y)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_Y;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_SUB;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`SBC_IME : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IME;
`cntrl_exe_op_reg <= `ALU_SUB;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`SBC_I_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_INDIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_SUB;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`SBC_I_Y : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
if(`history_dest_1 == `wb_dest_reg_y)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_y)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_y)
begin
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_2_reg <= `ADR_OFF_Y;
end
`cntrl_ea_adr_mod_reg <= `MOD_INDIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_SUB;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`SBC_ZP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_SUB;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`SBC_ZP_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_SUB;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DAT;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// FLAGS SET //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`SEC : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_SEC;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DC;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`SED : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_SED;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DC;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`SEI : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_SEI;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DC;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// STA //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`STA_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`STA_ABS_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`STA_ABS_Y : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_y)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_y)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_y)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_Y;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`STA_I_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_INDIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`STA_I_Y : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
if(`history_dest_1 == `wb_dest_reg_y)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_y)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_y)
begin
`cntrl_ea_off_2_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_2_reg <= `ADR_OFF_Y;
end
`cntrl_ea_adr_mod_reg <= `MOD_INDIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`STA_ZP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`STA_ZP_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// STX //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`STX_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_x)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_X;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`STX_ZP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_x)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_X;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`STX_ZP_Y : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_y)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_y)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_y)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_Y;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_x)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_X;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// STY //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`STY_ABS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`inst_temp_3, `inst_temp_2};
used_byte_cnt_reg <= 2'h3;
inst_temp_reg <= inst_temp_reg >> 6'h18;
inst_temp_reg[23:0] <= fetched_ops_i[23:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_y)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_Y;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`STY_ZP : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_y)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_Y;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`STY_ZP_X : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {8'h0, `inst_temp_2};
used_byte_cnt_reg <= 2'h2;
inst_temp_reg <= inst_temp_reg >> 6'h10;
inst_temp_reg[23:8] <= fetched_ops_i[15:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_FORWD;
end
else
begin
`cntrl_ea_off_1_reg <= `ADR_OFF_X;
end
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_DIR;
`cntrl_ea_adr_src_reg <= `EA_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_ADR;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_y)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_Y;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `ACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `ONE;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_memry};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
//////////////////////////////////////////////////////////////////////////////////////////
// //
// TRANSFERRING RESGISTERS //
// //
//////////////////////////////////////////////////////////////////////////////////////////
`TAX : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `ACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_x};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`TAY : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_a)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_A;
end
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `ACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_y};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`TSX : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `SP_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_S;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `ACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_x};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`TXA : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_x)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_X;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
`TXS : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
if(`history_dest_1 == `wb_dest_reg_x)
begin
//Insert 2 bubbles
wait_sig_reg <= 2'h2;
`cntrl_ea_stack_op_reg <= `STACK_OP_FORWD;
end
else if(`history_dest_2 == `wb_dest_reg_x)
begin
//Insert 1 bubble
wait_sig_reg <= 2'h1;
`cntrl_ea_stack_op_reg <= `STACK_OP_FORWD;
end
else if(`history_dest_3 == `wb_dest_reg_x)
begin
`cntrl_ea_stack_op_reg <= `STACK_OP_FORWD;
end
else
begin
`cntrl_ea_stack_op_reg <= `STACK_OP_X;
end
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_NOP;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_DC;
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_DC;
`cntrl_wb_ra_ld_reg <= `DEACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_impld};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
`TYA : begin
//Step 1, Update Registers :
pc_reg <= pc_i - 16'h6 + used_byte_cnt_reg + 16'h1;
operand_reg <= {`NOP, `NOP};
used_byte_cnt_reg <= 2'h1;
inst_temp_reg <= inst_temp_reg >> 6'h8;
inst_temp_reg[23:16] <= fetched_ops_i[7:0];
//Step 2, Generate Control Signals :
`cntrl_ea_pc_jmp_reg <= `NEXT_INST;
`cntrl_ea_off_1_reg <= `ADR_OFF_NA;
`cntrl_ea_off_2_reg <= `ADR_OFF_NA;
`cntrl_ea_adr_mod_reg <= `MOD_NON;
`cntrl_ea_adr_src_reg <= `NO_ADR;
`cntrl_ea_stack_op_reg <= `STACK_OP_NONE;
`cntrl_rd_src_reg <= `TYPE_IMP;
`cntrl_exe_op_reg <= `ALU_ITO;
`cntrl_exe_op1_src_reg <= `ALU_OP1_SRC_OP2;
if(`history_dest_1 == `wb_dest_reg_y)
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_FORWD;
end
else
begin
`cntrl_exe_op2_src_reg <= `ALU_OP2_SRC_Y;
end
`cntrl_wb_ra_ld_reg <= `ACTIVE;
`cntrl_wb_rx_ld_reg <= `DEACTIVE;
`cntrl_wb_ry_ld_reg <= `DEACTIVE;
`cntrl_exe_rp_ld_reg <= `ACTIVE;
`cntrl_wb_mem_wr_reg <= `DEACTIVE;
`cntrl_wb_mem_wr_cnt_reg <= `NON;
//Step 3, Update Wire Back Destination History :
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_reg_a};
history_inst_flag <= {`history_flag_2, `history_flag_1, `wef_flags};
end
default : begin
control_signal_reg <= `decode_cntrl_o_width'h0;
used_byte_cnt_reg <= 2'h0;
history_inst_dest <= {`history_dest_2, `history_dest_1, `wb_dest_none};
history_inst_flag <= {`history_flag_2, `history_flag_1, `nef_flags};
end
endcase
end
end
endmodule |
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